1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringRef.h" 25 #include "llvm/ADT/StringSwitch.h" 26 #include "llvm/ADT/Triple.h" 27 #include "llvm/IR/Type.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include <algorithm> 31 #include <memory> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const override { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 94 // AddressSanitizer doesn't play well with source fortification, which is on 95 // by default on Darwin. 96 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 97 98 if (!Opts.ObjCAutoRefCount) { 99 // __weak is always defined, for use in blocks and with objc pointers. 100 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 101 102 // Darwin defines __strong even in C mode (just to nothing). 103 if (Opts.getGC() != LangOptions::NonGC) 104 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 105 else 106 Builder.defineMacro("__strong", ""); 107 108 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 109 // allow this in C, since one might have block pointers in structs that 110 // are used in pure C code and in Objective-C ARC. 111 Builder.defineMacro("__unsafe_unretained", ""); 112 } 113 114 if (Opts.Static) 115 Builder.defineMacro("__STATIC__"); 116 else 117 Builder.defineMacro("__DYNAMIC__"); 118 119 if (Opts.POSIXThreads) 120 Builder.defineMacro("_REENTRANT"); 121 122 // Get the platform type and version number from the triple. 123 unsigned Maj, Min, Rev; 124 if (Triple.isMacOSX()) { 125 Triple.getMacOSXVersion(Maj, Min, Rev); 126 PlatformName = "macosx"; 127 } else { 128 Triple.getOSVersion(Maj, Min, Rev); 129 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 130 } 131 132 // If -target arch-pc-win32-macho option specified, we're 133 // generating code for Win32 ABI. No need to emit 134 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 135 if (PlatformName == "win32") { 136 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 137 return; 138 } 139 140 // Set the appropriate OS version define. 141 if (Triple.isiOS()) { 142 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 143 char Str[6]; 144 Str[0] = '0' + Maj; 145 Str[1] = '0' + (Min / 10); 146 Str[2] = '0' + (Min % 10); 147 Str[3] = '0' + (Rev / 10); 148 Str[4] = '0' + (Rev % 10); 149 Str[5] = '\0'; 150 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 151 Str); 152 } else if (Triple.isMacOSX()) { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 158 char Str[7]; 159 if (Maj < 10 || (Maj == 10 && Min < 10)) { 160 Str[0] = '0' + (Maj / 10); 161 Str[1] = '0' + (Maj % 10); 162 Str[2] = '0' + std::min(Min, 9U); 163 Str[3] = '0' + std::min(Rev, 9U); 164 Str[4] = '\0'; 165 } else { 166 // Handle versions > 10.9. 167 Str[0] = '0' + (Maj / 10); 168 Str[1] = '0' + (Maj % 10); 169 Str[2] = '0' + (Min / 10); 170 Str[3] = '0' + (Min % 10); 171 Str[4] = '0' + (Rev / 10); 172 Str[5] = '0' + (Rev % 10); 173 Str[6] = '\0'; 174 } 175 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 176 } 177 178 // Tell users about the kernel if there is one. 179 if (Triple.isOSDarwin()) 180 Builder.defineMacro("__MACH__"); 181 182 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 183 } 184 185 namespace { 186 template<typename Target> 187 class DarwinTargetInfo : public OSTargetInfo<Target> { 188 protected: 189 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 190 MacroBuilder &Builder) const override { 191 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 192 this->PlatformMinVersion); 193 } 194 195 public: 196 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 197 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 198 this->MCountName = "\01mcount"; 199 } 200 201 std::string isValidSectionSpecifier(StringRef SR) const override { 202 // Let MCSectionMachO validate this. 203 StringRef Segment, Section; 204 unsigned TAA, StubSize; 205 bool HasTAA; 206 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 207 TAA, HasTAA, StubSize); 208 } 209 210 const char *getStaticInitSectionSpecifier() const override { 211 // FIXME: We should return 0 when building kexts. 212 return "__TEXT,__StaticInit,regular,pure_instructions"; 213 } 214 215 /// Darwin does not support protected visibility. Darwin's "default" 216 /// is very similar to ELF's "protected"; Darwin requires a "weak" 217 /// attribute on declarations that can be dynamically replaced. 218 bool hasProtectedVisibility() const override { 219 return false; 220 } 221 }; 222 223 224 // DragonFlyBSD Target 225 template<typename Target> 226 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 227 protected: 228 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 229 MacroBuilder &Builder) const override { 230 // DragonFly defines; list based off of gcc output 231 Builder.defineMacro("__DragonFly__"); 232 Builder.defineMacro("__DragonFly_cc_version", "100001"); 233 Builder.defineMacro("__ELF__"); 234 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 235 Builder.defineMacro("__tune_i386__"); 236 DefineStd(Builder, "unix", Opts); 237 } 238 public: 239 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 240 : OSTargetInfo<Target>(Triple) { 241 this->UserLabelPrefix = ""; 242 243 switch (Triple.getArch()) { 244 default: 245 case llvm::Triple::x86: 246 case llvm::Triple::x86_64: 247 this->MCountName = ".mcount"; 248 break; 249 } 250 } 251 }; 252 253 // FreeBSD Target 254 template<typename Target> 255 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 256 protected: 257 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 258 MacroBuilder &Builder) const override { 259 // FreeBSD defines; list based off of gcc output 260 261 unsigned Release = Triple.getOSMajorVersion(); 262 if (Release == 0U) 263 Release = 8; 264 265 Builder.defineMacro("__FreeBSD__", Twine(Release)); 266 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 267 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 268 DefineStd(Builder, "unix", Opts); 269 Builder.defineMacro("__ELF__"); 270 271 // On FreeBSD, wchar_t contains the number of the code point as 272 // used by the character set of the locale. These character sets are 273 // not necessarily a superset of ASCII. 274 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 275 } 276 public: 277 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 278 this->UserLabelPrefix = ""; 279 280 switch (Triple.getArch()) { 281 default: 282 case llvm::Triple::x86: 283 case llvm::Triple::x86_64: 284 this->MCountName = ".mcount"; 285 break; 286 case llvm::Triple::mips: 287 case llvm::Triple::mipsel: 288 case llvm::Triple::ppc: 289 case llvm::Triple::ppc64: 290 case llvm::Triple::ppc64le: 291 this->MCountName = "_mcount"; 292 break; 293 case llvm::Triple::arm: 294 this->MCountName = "__mcount"; 295 break; 296 } 297 } 298 }; 299 300 // GNU/kFreeBSD Target 301 template<typename Target> 302 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 303 protected: 304 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 305 MacroBuilder &Builder) const override { 306 // GNU/kFreeBSD defines; list based off of gcc output 307 308 DefineStd(Builder, "unix", Opts); 309 Builder.defineMacro("__FreeBSD_kernel__"); 310 Builder.defineMacro("__GLIBC__"); 311 Builder.defineMacro("__ELF__"); 312 if (Opts.POSIXThreads) 313 Builder.defineMacro("_REENTRANT"); 314 if (Opts.CPlusPlus) 315 Builder.defineMacro("_GNU_SOURCE"); 316 } 317 public: 318 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 319 this->UserLabelPrefix = ""; 320 } 321 }; 322 323 // Minix Target 324 template<typename Target> 325 class MinixTargetInfo : public OSTargetInfo<Target> { 326 protected: 327 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 328 MacroBuilder &Builder) const override { 329 // Minix defines 330 331 Builder.defineMacro("__minix", "3"); 332 Builder.defineMacro("_EM_WSIZE", "4"); 333 Builder.defineMacro("_EM_PSIZE", "4"); 334 Builder.defineMacro("_EM_SSIZE", "2"); 335 Builder.defineMacro("_EM_LSIZE", "4"); 336 Builder.defineMacro("_EM_FSIZE", "4"); 337 Builder.defineMacro("_EM_DSIZE", "8"); 338 Builder.defineMacro("__ELF__"); 339 DefineStd(Builder, "unix", Opts); 340 } 341 public: 342 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 343 this->UserLabelPrefix = ""; 344 } 345 }; 346 347 // Linux target 348 template<typename Target> 349 class LinuxTargetInfo : public OSTargetInfo<Target> { 350 protected: 351 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 352 MacroBuilder &Builder) const override { 353 // Linux defines; list based off of gcc output 354 DefineStd(Builder, "unix", Opts); 355 DefineStd(Builder, "linux", Opts); 356 Builder.defineMacro("__gnu_linux__"); 357 Builder.defineMacro("__ELF__"); 358 if (Triple.getEnvironment() == llvm::Triple::Android) 359 Builder.defineMacro("__ANDROID__", "1"); 360 if (Opts.POSIXThreads) 361 Builder.defineMacro("_REENTRANT"); 362 if (Opts.CPlusPlus) 363 Builder.defineMacro("_GNU_SOURCE"); 364 } 365 public: 366 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 367 this->UserLabelPrefix = ""; 368 this->WIntType = TargetInfo::UnsignedInt; 369 370 switch (Triple.getArch()) { 371 default: 372 break; 373 case llvm::Triple::ppc: 374 case llvm::Triple::ppc64: 375 case llvm::Triple::ppc64le: 376 this->MCountName = "_mcount"; 377 break; 378 } 379 } 380 381 const char *getStaticInitSectionSpecifier() const override { 382 return ".text.startup"; 383 } 384 }; 385 386 // NetBSD Target 387 template<typename Target> 388 class NetBSDTargetInfo : public OSTargetInfo<Target> { 389 protected: 390 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 391 MacroBuilder &Builder) const override { 392 // NetBSD defines; list based off of gcc output 393 Builder.defineMacro("__NetBSD__"); 394 Builder.defineMacro("__unix__"); 395 Builder.defineMacro("__ELF__"); 396 if (Opts.POSIXThreads) 397 Builder.defineMacro("_POSIX_THREADS"); 398 399 switch (Triple.getArch()) { 400 default: 401 break; 402 case llvm::Triple::arm: 403 case llvm::Triple::armeb: 404 case llvm::Triple::thumb: 405 case llvm::Triple::thumbeb: 406 Builder.defineMacro("__ARM_DWARF_EH__"); 407 break; 408 } 409 } 410 public: 411 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 412 this->UserLabelPrefix = ""; 413 } 414 }; 415 416 // OpenBSD Target 417 template<typename Target> 418 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 419 protected: 420 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 421 MacroBuilder &Builder) const override { 422 // OpenBSD defines; list based off of gcc output 423 424 Builder.defineMacro("__OpenBSD__"); 425 DefineStd(Builder, "unix", Opts); 426 Builder.defineMacro("__ELF__"); 427 if (Opts.POSIXThreads) 428 Builder.defineMacro("_REENTRANT"); 429 } 430 public: 431 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 432 this->UserLabelPrefix = ""; 433 this->TLSSupported = false; 434 435 switch (Triple.getArch()) { 436 default: 437 case llvm::Triple::x86: 438 case llvm::Triple::x86_64: 439 case llvm::Triple::arm: 440 case llvm::Triple::sparc: 441 this->MCountName = "__mcount"; 442 break; 443 case llvm::Triple::mips64: 444 case llvm::Triple::mips64el: 445 case llvm::Triple::ppc: 446 case llvm::Triple::sparcv9: 447 this->MCountName = "_mcount"; 448 break; 449 } 450 } 451 }; 452 453 // Bitrig Target 454 template<typename Target> 455 class BitrigTargetInfo : public OSTargetInfo<Target> { 456 protected: 457 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 458 MacroBuilder &Builder) const override { 459 // Bitrig defines; list based off of gcc output 460 461 Builder.defineMacro("__Bitrig__"); 462 DefineStd(Builder, "unix", Opts); 463 Builder.defineMacro("__ELF__"); 464 if (Opts.POSIXThreads) 465 Builder.defineMacro("_REENTRANT"); 466 } 467 public: 468 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 469 this->UserLabelPrefix = ""; 470 this->MCountName = "__mcount"; 471 } 472 }; 473 474 // PSP Target 475 template<typename Target> 476 class PSPTargetInfo : public OSTargetInfo<Target> { 477 protected: 478 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 479 MacroBuilder &Builder) const override { 480 // PSP defines; list based on the output of the pspdev gcc toolchain. 481 Builder.defineMacro("PSP"); 482 Builder.defineMacro("_PSP"); 483 Builder.defineMacro("__psp__"); 484 Builder.defineMacro("__ELF__"); 485 } 486 public: 487 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 488 this->UserLabelPrefix = ""; 489 } 490 }; 491 492 // PS3 PPU Target 493 template<typename Target> 494 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 495 protected: 496 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 497 MacroBuilder &Builder) const override { 498 // PS3 PPU defines. 499 Builder.defineMacro("__PPC__"); 500 Builder.defineMacro("__PPU__"); 501 Builder.defineMacro("__CELLOS_LV2__"); 502 Builder.defineMacro("__ELF__"); 503 Builder.defineMacro("__LP32__"); 504 Builder.defineMacro("_ARCH_PPC64"); 505 Builder.defineMacro("__powerpc64__"); 506 } 507 public: 508 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 509 this->UserLabelPrefix = ""; 510 this->LongWidth = this->LongAlign = 32; 511 this->PointerWidth = this->PointerAlign = 32; 512 this->IntMaxType = TargetInfo::SignedLongLong; 513 this->Int64Type = TargetInfo::SignedLongLong; 514 this->SizeType = TargetInfo::UnsignedInt; 515 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 516 } 517 }; 518 519 // AuroraUX target 520 template<typename Target> 521 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 522 protected: 523 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 524 MacroBuilder &Builder) const override { 525 DefineStd(Builder, "sun", Opts); 526 DefineStd(Builder, "unix", Opts); 527 Builder.defineMacro("__ELF__"); 528 Builder.defineMacro("__svr4__"); 529 Builder.defineMacro("__SVR4"); 530 } 531 public: 532 AuroraUXTargetInfo(const llvm::Triple &Triple) 533 : OSTargetInfo<Target>(Triple) { 534 this->UserLabelPrefix = ""; 535 this->WCharType = this->SignedLong; 536 // FIXME: WIntType should be SignedLong 537 } 538 }; 539 540 // Solaris target 541 template<typename Target> 542 class SolarisTargetInfo : public OSTargetInfo<Target> { 543 protected: 544 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 545 MacroBuilder &Builder) const override { 546 DefineStd(Builder, "sun", Opts); 547 DefineStd(Builder, "unix", Opts); 548 Builder.defineMacro("__ELF__"); 549 Builder.defineMacro("__svr4__"); 550 Builder.defineMacro("__SVR4"); 551 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 552 // newer, but to 500 for everything else. feature_test.h has a check to 553 // ensure that you are not using C99 with an old version of X/Open or C89 554 // with a new version. 555 if (Opts.C99 || Opts.C11) 556 Builder.defineMacro("_XOPEN_SOURCE", "600"); 557 else 558 Builder.defineMacro("_XOPEN_SOURCE", "500"); 559 if (Opts.CPlusPlus) 560 Builder.defineMacro("__C99FEATURES__"); 561 Builder.defineMacro("_LARGEFILE_SOURCE"); 562 Builder.defineMacro("_LARGEFILE64_SOURCE"); 563 Builder.defineMacro("__EXTENSIONS__"); 564 Builder.defineMacro("_REENTRANT"); 565 } 566 public: 567 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 568 this->UserLabelPrefix = ""; 569 this->WCharType = this->SignedInt; 570 // FIXME: WIntType should be SignedLong 571 } 572 }; 573 574 // Windows target 575 template<typename Target> 576 class WindowsTargetInfo : public OSTargetInfo<Target> { 577 protected: 578 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 579 MacroBuilder &Builder) const override { 580 Builder.defineMacro("_WIN32"); 581 } 582 void getVisualStudioDefines(const LangOptions &Opts, 583 MacroBuilder &Builder) const { 584 if (Opts.CPlusPlus) { 585 if (Opts.RTTIData) 586 Builder.defineMacro("_CPPRTTI"); 587 588 if (Opts.Exceptions) 589 Builder.defineMacro("_CPPUNWIND"); 590 } 591 592 if (!Opts.CharIsSigned) 593 Builder.defineMacro("_CHAR_UNSIGNED"); 594 595 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 596 // but it works for now. 597 if (Opts.POSIXThreads) 598 Builder.defineMacro("_MT"); 599 600 if (Opts.MSCompatibilityVersion) { 601 Builder.defineMacro("_MSC_VER", 602 Twine(Opts.MSCompatibilityVersion / 100000)); 603 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 604 // FIXME We cannot encode the revision information into 32-bits 605 Builder.defineMacro("_MSC_BUILD", Twine(1)); 606 } 607 608 if (Opts.MicrosoftExt) { 609 Builder.defineMacro("_MSC_EXTENSIONS"); 610 611 if (Opts.CPlusPlus11) { 612 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 613 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 614 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 615 } 616 } 617 618 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 619 } 620 621 public: 622 WindowsTargetInfo(const llvm::Triple &Triple) 623 : OSTargetInfo<Target>(Triple) {} 624 }; 625 626 template <typename Target> 627 class NaClTargetInfo : public OSTargetInfo<Target> { 628 protected: 629 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 630 MacroBuilder &Builder) const override { 631 if (Opts.POSIXThreads) 632 Builder.defineMacro("_REENTRANT"); 633 if (Opts.CPlusPlus) 634 Builder.defineMacro("_GNU_SOURCE"); 635 636 DefineStd(Builder, "unix", Opts); 637 Builder.defineMacro("__ELF__"); 638 Builder.defineMacro("__native_client__"); 639 } 640 641 public: 642 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 643 this->UserLabelPrefix = ""; 644 this->LongAlign = 32; 645 this->LongWidth = 32; 646 this->PointerAlign = 32; 647 this->PointerWidth = 32; 648 this->IntMaxType = TargetInfo::SignedLongLong; 649 this->Int64Type = TargetInfo::SignedLongLong; 650 this->DoubleAlign = 64; 651 this->LongDoubleWidth = 64; 652 this->LongDoubleAlign = 64; 653 this->LongLongWidth = 64; 654 this->LongLongAlign = 64; 655 this->SizeType = TargetInfo::UnsignedInt; 656 this->PtrDiffType = TargetInfo::SignedInt; 657 this->IntPtrType = TargetInfo::SignedInt; 658 // RegParmMax is inherited from the underlying architecture 659 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 660 if (Triple.getArch() == llvm::Triple::arm) { 661 this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S128"; 662 } else if (Triple.getArch() == llvm::Triple::x86) { 663 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 664 } else if (Triple.getArch() == llvm::Triple::x86_64) { 665 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 666 } else if (Triple.getArch() == llvm::Triple::mipsel) { 667 // Handled on mips' setDescriptionString. 668 } else { 669 assert(Triple.getArch() == llvm::Triple::le32); 670 this->DescriptionString = "e-p:32:32-i64:64"; 671 } 672 } 673 typename Target::CallingConvCheckResult checkCallingConvention( 674 CallingConv CC) const override { 675 return CC == CC_PnaclCall ? Target::CCCR_OK : 676 Target::checkCallingConvention(CC); 677 } 678 }; 679 } // end anonymous namespace. 680 681 //===----------------------------------------------------------------------===// 682 // Specific target implementations. 683 //===----------------------------------------------------------------------===// 684 685 namespace { 686 // PPC abstract base class 687 class PPCTargetInfo : public TargetInfo { 688 static const Builtin::Info BuiltinInfo[]; 689 static const char * const GCCRegNames[]; 690 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 691 std::string CPU; 692 693 // Target cpu features. 694 bool HasVSX; 695 696 protected: 697 std::string ABI; 698 699 public: 700 PPCTargetInfo(const llvm::Triple &Triple) 701 : TargetInfo(Triple), HasVSX(false) { 702 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 703 LongDoubleWidth = LongDoubleAlign = 128; 704 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 705 } 706 707 /// \brief Flags for architecture specific defines. 708 typedef enum { 709 ArchDefineNone = 0, 710 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 711 ArchDefinePpcgr = 1 << 1, 712 ArchDefinePpcsq = 1 << 2, 713 ArchDefine440 = 1 << 3, 714 ArchDefine603 = 1 << 4, 715 ArchDefine604 = 1 << 5, 716 ArchDefinePwr4 = 1 << 6, 717 ArchDefinePwr5 = 1 << 7, 718 ArchDefinePwr5x = 1 << 8, 719 ArchDefinePwr6 = 1 << 9, 720 ArchDefinePwr6x = 1 << 10, 721 ArchDefinePwr7 = 1 << 11, 722 ArchDefinePwr8 = 1 << 12, 723 ArchDefineA2 = 1 << 13, 724 ArchDefineA2q = 1 << 14 725 } ArchDefineTypes; 726 727 // Note: GCC recognizes the following additional cpus: 728 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 729 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 730 // titan, rs64. 731 bool setCPU(const std::string &Name) override { 732 bool CPUKnown = llvm::StringSwitch<bool>(Name) 733 .Case("generic", true) 734 .Case("440", true) 735 .Case("450", true) 736 .Case("601", true) 737 .Case("602", true) 738 .Case("603", true) 739 .Case("603e", true) 740 .Case("603ev", true) 741 .Case("604", true) 742 .Case("604e", true) 743 .Case("620", true) 744 .Case("630", true) 745 .Case("g3", true) 746 .Case("7400", true) 747 .Case("g4", true) 748 .Case("7450", true) 749 .Case("g4+", true) 750 .Case("750", true) 751 .Case("970", true) 752 .Case("g5", true) 753 .Case("a2", true) 754 .Case("a2q", true) 755 .Case("e500mc", true) 756 .Case("e5500", true) 757 .Case("power3", true) 758 .Case("pwr3", true) 759 .Case("power4", true) 760 .Case("pwr4", true) 761 .Case("power5", true) 762 .Case("pwr5", true) 763 .Case("power5x", true) 764 .Case("pwr5x", true) 765 .Case("power6", true) 766 .Case("pwr6", true) 767 .Case("power6x", true) 768 .Case("pwr6x", true) 769 .Case("power7", true) 770 .Case("pwr7", true) 771 .Case("power8", true) 772 .Case("pwr8", true) 773 .Case("powerpc", true) 774 .Case("ppc", true) 775 .Case("powerpc64", true) 776 .Case("ppc64", true) 777 .Case("powerpc64le", true) 778 .Case("ppc64le", true) 779 .Default(false); 780 781 if (CPUKnown) 782 CPU = Name; 783 784 return CPUKnown; 785 } 786 787 788 StringRef getABI() const override { return ABI; } 789 790 void getTargetBuiltins(const Builtin::Info *&Records, 791 unsigned &NumRecords) const override { 792 Records = BuiltinInfo; 793 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 794 } 795 796 bool isCLZForZeroUndef() const override { return false; } 797 798 void getTargetDefines(const LangOptions &Opts, 799 MacroBuilder &Builder) const override; 800 801 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 802 803 bool handleTargetFeatures(std::vector<std::string> &Features, 804 DiagnosticsEngine &Diags) override; 805 bool hasFeature(StringRef Feature) const override; 806 807 void getGCCRegNames(const char * const *&Names, 808 unsigned &NumNames) const override; 809 void getGCCRegAliases(const GCCRegAlias *&Aliases, 810 unsigned &NumAliases) const override; 811 bool validateAsmConstraint(const char *&Name, 812 TargetInfo::ConstraintInfo &Info) const override { 813 switch (*Name) { 814 default: return false; 815 case 'O': // Zero 816 break; 817 case 'b': // Base register 818 case 'f': // Floating point register 819 Info.setAllowsRegister(); 820 break; 821 // FIXME: The following are added to allow parsing. 822 // I just took a guess at what the actions should be. 823 // Also, is more specific checking needed? I.e. specific registers? 824 case 'd': // Floating point register (containing 64-bit value) 825 case 'v': // Altivec vector register 826 Info.setAllowsRegister(); 827 break; 828 case 'w': 829 switch (Name[1]) { 830 case 'd':// VSX vector register to hold vector double data 831 case 'f':// VSX vector register to hold vector float data 832 case 's':// VSX vector register to hold scalar float data 833 case 'a':// Any VSX register 834 case 'c':// An individual CR bit 835 break; 836 default: 837 return false; 838 } 839 Info.setAllowsRegister(); 840 Name++; // Skip over 'w'. 841 break; 842 case 'h': // `MQ', `CTR', or `LINK' register 843 case 'q': // `MQ' register 844 case 'c': // `CTR' register 845 case 'l': // `LINK' register 846 case 'x': // `CR' register (condition register) number 0 847 case 'y': // `CR' register (condition register) 848 case 'z': // `XER[CA]' carry bit (part of the XER register) 849 Info.setAllowsRegister(); 850 break; 851 case 'I': // Signed 16-bit constant 852 case 'J': // Unsigned 16-bit constant shifted left 16 bits 853 // (use `L' instead for SImode constants) 854 case 'K': // Unsigned 16-bit constant 855 case 'L': // Signed 16-bit constant shifted left 16 bits 856 case 'M': // Constant larger than 31 857 case 'N': // Exact power of 2 858 case 'P': // Constant whose negation is a signed 16-bit constant 859 case 'G': // Floating point constant that can be loaded into a 860 // register with one instruction per word 861 case 'H': // Integer/Floating point constant that can be loaded 862 // into a register using three instructions 863 break; 864 case 'm': // Memory operand. Note that on PowerPC targets, m can 865 // include addresses that update the base register. It 866 // is therefore only safe to use `m' in an asm statement 867 // if that asm statement accesses the operand exactly once. 868 // The asm statement must also use `%U<opno>' as a 869 // placeholder for the "update" flag in the corresponding 870 // load or store instruction. For example: 871 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 872 // is correct but: 873 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 874 // is not. Use es rather than m if you don't want the base 875 // register to be updated. 876 case 'e': 877 if (Name[1] != 's') 878 return false; 879 // es: A "stable" memory operand; that is, one which does not 880 // include any automodification of the base register. Unlike 881 // `m', this constraint can be used in asm statements that 882 // might access the operand several times, or that might not 883 // access it at all. 884 Info.setAllowsMemory(); 885 Name++; // Skip over 'e'. 886 break; 887 case 'Q': // Memory operand that is an offset from a register (it is 888 // usually better to use `m' or `es' in asm statements) 889 case 'Z': // Memory operand that is an indexed or indirect from a 890 // register (it is usually better to use `m' or `es' in 891 // asm statements) 892 Info.setAllowsMemory(); 893 Info.setAllowsRegister(); 894 break; 895 case 'R': // AIX TOC entry 896 case 'a': // Address operand that is an indexed or indirect from a 897 // register (`p' is preferable for asm statements) 898 case 'S': // Constant suitable as a 64-bit mask operand 899 case 'T': // Constant suitable as a 32-bit mask operand 900 case 'U': // System V Release 4 small data area reference 901 case 't': // AND masks that can be performed by two rldic{l, r} 902 // instructions 903 case 'W': // Vector constant that does not require memory 904 case 'j': // Vector constant that is all zeros. 905 break; 906 // End FIXME. 907 } 908 return true; 909 } 910 std::string convertConstraint(const char *&Constraint) const override { 911 std::string R; 912 switch (*Constraint) { 913 case 'e': 914 case 'w': 915 // Two-character constraint; add "^" hint for later parsing. 916 R = std::string("^") + std::string(Constraint, 2); 917 Constraint++; 918 break; 919 default: 920 return TargetInfo::convertConstraint(Constraint); 921 } 922 return R; 923 } 924 const char *getClobbers() const override { 925 return ""; 926 } 927 int getEHDataRegisterNumber(unsigned RegNo) const override { 928 if (RegNo == 0) return 3; 929 if (RegNo == 1) return 4; 930 return -1; 931 } 932 }; 933 934 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 935 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 936 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 937 ALL_LANGUAGES }, 938 #include "clang/Basic/BuiltinsPPC.def" 939 }; 940 941 /// handleTargetFeatures - Perform initialization based on the user 942 /// configured set of features. 943 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 944 DiagnosticsEngine &Diags) { 945 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 946 // Ignore disabled features. 947 if (Features[i][0] == '-') 948 continue; 949 950 StringRef Feature = StringRef(Features[i]).substr(1); 951 952 if (Feature == "vsx") { 953 HasVSX = true; 954 continue; 955 } 956 957 // TODO: Finish this list and add an assert that we've handled them 958 // all. 959 } 960 961 return true; 962 } 963 964 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 965 /// #defines that are not tied to a specific subtarget. 966 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 967 MacroBuilder &Builder) const { 968 // Target identification. 969 Builder.defineMacro("__ppc__"); 970 Builder.defineMacro("__PPC__"); 971 Builder.defineMacro("_ARCH_PPC"); 972 Builder.defineMacro("__powerpc__"); 973 Builder.defineMacro("__POWERPC__"); 974 if (PointerWidth == 64) { 975 Builder.defineMacro("_ARCH_PPC64"); 976 Builder.defineMacro("__powerpc64__"); 977 Builder.defineMacro("__ppc64__"); 978 Builder.defineMacro("__PPC64__"); 979 } 980 981 // Target properties. 982 if (getTriple().getArch() == llvm::Triple::ppc64le) { 983 Builder.defineMacro("_LITTLE_ENDIAN"); 984 } else { 985 if (getTriple().getOS() != llvm::Triple::NetBSD && 986 getTriple().getOS() != llvm::Triple::OpenBSD) 987 Builder.defineMacro("_BIG_ENDIAN"); 988 } 989 990 // ABI options. 991 if (ABI == "elfv1") 992 Builder.defineMacro("_CALL_ELF", "1"); 993 if (ABI == "elfv2") 994 Builder.defineMacro("_CALL_ELF", "2"); 995 996 // Subtarget options. 997 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 998 Builder.defineMacro("__REGISTER_PREFIX__", ""); 999 1000 // FIXME: Should be controlled by command line option. 1001 if (LongDoubleWidth == 128) 1002 Builder.defineMacro("__LONG_DOUBLE_128__"); 1003 1004 if (Opts.AltiVec) { 1005 Builder.defineMacro("__VEC__", "10206"); 1006 Builder.defineMacro("__ALTIVEC__"); 1007 } 1008 1009 // CPU identification. 1010 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1011 .Case("440", ArchDefineName) 1012 .Case("450", ArchDefineName | ArchDefine440) 1013 .Case("601", ArchDefineName) 1014 .Case("602", ArchDefineName | ArchDefinePpcgr) 1015 .Case("603", ArchDefineName | ArchDefinePpcgr) 1016 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1017 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1018 .Case("604", ArchDefineName | ArchDefinePpcgr) 1019 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1020 .Case("620", ArchDefineName | ArchDefinePpcgr) 1021 .Case("630", ArchDefineName | ArchDefinePpcgr) 1022 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1023 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1024 .Case("750", ArchDefineName | ArchDefinePpcgr) 1025 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1026 | ArchDefinePpcsq) 1027 .Case("a2", ArchDefineA2) 1028 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1029 .Case("pwr3", ArchDefinePpcgr) 1030 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1031 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1032 | ArchDefinePpcsq) 1033 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1034 | ArchDefinePpcgr | ArchDefinePpcsq) 1035 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1036 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1037 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1038 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1039 | ArchDefinePpcsq) 1040 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1041 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1042 | ArchDefinePpcgr | ArchDefinePpcsq) 1043 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1044 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1045 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1046 .Case("power3", ArchDefinePpcgr) 1047 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1048 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1049 | ArchDefinePpcsq) 1050 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1051 | ArchDefinePpcgr | ArchDefinePpcsq) 1052 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1053 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1054 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1055 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1056 | ArchDefinePpcsq) 1057 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1058 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1059 | ArchDefinePpcgr | ArchDefinePpcsq) 1060 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1061 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1062 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1063 .Default(ArchDefineNone); 1064 1065 if (defs & ArchDefineName) 1066 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1067 if (defs & ArchDefinePpcgr) 1068 Builder.defineMacro("_ARCH_PPCGR"); 1069 if (defs & ArchDefinePpcsq) 1070 Builder.defineMacro("_ARCH_PPCSQ"); 1071 if (defs & ArchDefine440) 1072 Builder.defineMacro("_ARCH_440"); 1073 if (defs & ArchDefine603) 1074 Builder.defineMacro("_ARCH_603"); 1075 if (defs & ArchDefine604) 1076 Builder.defineMacro("_ARCH_604"); 1077 if (defs & ArchDefinePwr4) 1078 Builder.defineMacro("_ARCH_PWR4"); 1079 if (defs & ArchDefinePwr5) 1080 Builder.defineMacro("_ARCH_PWR5"); 1081 if (defs & ArchDefinePwr5x) 1082 Builder.defineMacro("_ARCH_PWR5X"); 1083 if (defs & ArchDefinePwr6) 1084 Builder.defineMacro("_ARCH_PWR6"); 1085 if (defs & ArchDefinePwr6x) 1086 Builder.defineMacro("_ARCH_PWR6X"); 1087 if (defs & ArchDefinePwr7) 1088 Builder.defineMacro("_ARCH_PWR7"); 1089 if (defs & ArchDefinePwr8) 1090 Builder.defineMacro("_ARCH_PWR8"); 1091 if (defs & ArchDefineA2) 1092 Builder.defineMacro("_ARCH_A2"); 1093 if (defs & ArchDefineA2q) { 1094 Builder.defineMacro("_ARCH_A2Q"); 1095 Builder.defineMacro("_ARCH_QP"); 1096 } 1097 1098 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1099 Builder.defineMacro("__bg__"); 1100 Builder.defineMacro("__THW_BLUEGENE__"); 1101 Builder.defineMacro("__bgq__"); 1102 Builder.defineMacro("__TOS_BGQ__"); 1103 } 1104 1105 if (HasVSX) 1106 Builder.defineMacro("__VSX__"); 1107 1108 // FIXME: The following are not yet generated here by Clang, but are 1109 // generated by GCC: 1110 // 1111 // _SOFT_FLOAT_ 1112 // __RECIP_PRECISION__ 1113 // __APPLE_ALTIVEC__ 1114 // __RECIP__ 1115 // __RECIPF__ 1116 // __RSQRTE__ 1117 // __RSQRTEF__ 1118 // _SOFT_DOUBLE_ 1119 // __NO_LWSYNC__ 1120 // __HAVE_BSWAP__ 1121 // __LONGDOUBLE128 1122 // __CMODEL_MEDIUM__ 1123 // __CMODEL_LARGE__ 1124 // _CALL_SYSV 1125 // _CALL_DARWIN 1126 // __NO_FPRS__ 1127 } 1128 1129 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1130 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1131 .Case("7400", true) 1132 .Case("g4", true) 1133 .Case("7450", true) 1134 .Case("g4+", true) 1135 .Case("970", true) 1136 .Case("g5", true) 1137 .Case("pwr6", true) 1138 .Case("pwr7", true) 1139 .Case("pwr8", true) 1140 .Case("ppc64", true) 1141 .Case("ppc64le", true) 1142 .Default(false); 1143 1144 Features["qpx"] = (CPU == "a2q"); 1145 1146 if (!ABI.empty()) 1147 Features[ABI] = true; 1148 } 1149 1150 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1151 return Feature == "powerpc"; 1152 } 1153 1154 1155 const char * const PPCTargetInfo::GCCRegNames[] = { 1156 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1157 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1158 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1159 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1160 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1161 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1162 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1163 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1164 "mq", "lr", "ctr", "ap", 1165 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1166 "xer", 1167 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1168 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1169 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1170 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1171 "vrsave", "vscr", 1172 "spe_acc", "spefscr", 1173 "sfp" 1174 }; 1175 1176 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1177 unsigned &NumNames) const { 1178 Names = GCCRegNames; 1179 NumNames = llvm::array_lengthof(GCCRegNames); 1180 } 1181 1182 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1183 // While some of these aliases do map to different registers 1184 // they still share the same register name. 1185 { { "0" }, "r0" }, 1186 { { "1"}, "r1" }, 1187 { { "2" }, "r2" }, 1188 { { "3" }, "r3" }, 1189 { { "4" }, "r4" }, 1190 { { "5" }, "r5" }, 1191 { { "6" }, "r6" }, 1192 { { "7" }, "r7" }, 1193 { { "8" }, "r8" }, 1194 { { "9" }, "r9" }, 1195 { { "10" }, "r10" }, 1196 { { "11" }, "r11" }, 1197 { { "12" }, "r12" }, 1198 { { "13" }, "r13" }, 1199 { { "14" }, "r14" }, 1200 { { "15" }, "r15" }, 1201 { { "16" }, "r16" }, 1202 { { "17" }, "r17" }, 1203 { { "18" }, "r18" }, 1204 { { "19" }, "r19" }, 1205 { { "20" }, "r20" }, 1206 { { "21" }, "r21" }, 1207 { { "22" }, "r22" }, 1208 { { "23" }, "r23" }, 1209 { { "24" }, "r24" }, 1210 { { "25" }, "r25" }, 1211 { { "26" }, "r26" }, 1212 { { "27" }, "r27" }, 1213 { { "28" }, "r28" }, 1214 { { "29" }, "r29" }, 1215 { { "30" }, "r30" }, 1216 { { "31" }, "r31" }, 1217 { { "fr0" }, "f0" }, 1218 { { "fr1" }, "f1" }, 1219 { { "fr2" }, "f2" }, 1220 { { "fr3" }, "f3" }, 1221 { { "fr4" }, "f4" }, 1222 { { "fr5" }, "f5" }, 1223 { { "fr6" }, "f6" }, 1224 { { "fr7" }, "f7" }, 1225 { { "fr8" }, "f8" }, 1226 { { "fr9" }, "f9" }, 1227 { { "fr10" }, "f10" }, 1228 { { "fr11" }, "f11" }, 1229 { { "fr12" }, "f12" }, 1230 { { "fr13" }, "f13" }, 1231 { { "fr14" }, "f14" }, 1232 { { "fr15" }, "f15" }, 1233 { { "fr16" }, "f16" }, 1234 { { "fr17" }, "f17" }, 1235 { { "fr18" }, "f18" }, 1236 { { "fr19" }, "f19" }, 1237 { { "fr20" }, "f20" }, 1238 { { "fr21" }, "f21" }, 1239 { { "fr22" }, "f22" }, 1240 { { "fr23" }, "f23" }, 1241 { { "fr24" }, "f24" }, 1242 { { "fr25" }, "f25" }, 1243 { { "fr26" }, "f26" }, 1244 { { "fr27" }, "f27" }, 1245 { { "fr28" }, "f28" }, 1246 { { "fr29" }, "f29" }, 1247 { { "fr30" }, "f30" }, 1248 { { "fr31" }, "f31" }, 1249 { { "cc" }, "cr0" }, 1250 }; 1251 1252 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1253 unsigned &NumAliases) const { 1254 Aliases = GCCRegAliases; 1255 NumAliases = llvm::array_lengthof(GCCRegAliases); 1256 } 1257 } // end anonymous namespace. 1258 1259 namespace { 1260 class PPC32TargetInfo : public PPCTargetInfo { 1261 public: 1262 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1263 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1264 1265 switch (getTriple().getOS()) { 1266 case llvm::Triple::Linux: 1267 case llvm::Triple::FreeBSD: 1268 case llvm::Triple::NetBSD: 1269 SizeType = UnsignedInt; 1270 PtrDiffType = SignedInt; 1271 IntPtrType = SignedInt; 1272 break; 1273 default: 1274 break; 1275 } 1276 1277 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1278 LongDoubleWidth = LongDoubleAlign = 64; 1279 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1280 } 1281 1282 // PPC32 supports atomics up to 4 bytes. 1283 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1284 } 1285 1286 BuiltinVaListKind getBuiltinVaListKind() const override { 1287 // This is the ELF definition, and is overridden by the Darwin sub-target 1288 return TargetInfo::PowerABIBuiltinVaList; 1289 } 1290 }; 1291 } // end anonymous namespace. 1292 1293 // Note: ABI differences may eventually require us to have a separate 1294 // TargetInfo for little endian. 1295 namespace { 1296 class PPC64TargetInfo : public PPCTargetInfo { 1297 public: 1298 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1299 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1300 IntMaxType = SignedLong; 1301 Int64Type = SignedLong; 1302 1303 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1304 LongDoubleWidth = LongDoubleAlign = 64; 1305 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1306 DescriptionString = "E-m:e-i64:64-n32:64"; 1307 } else { 1308 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1309 DescriptionString = "e-m:e-i64:64-n32:64"; 1310 ABI = "elfv2"; 1311 } else { 1312 DescriptionString = "E-m:e-i64:64-n32:64"; 1313 ABI = "elfv1"; 1314 } 1315 } 1316 1317 // PPC64 supports atomics up to 8 bytes. 1318 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1319 } 1320 BuiltinVaListKind getBuiltinVaListKind() const override { 1321 return TargetInfo::CharPtrBuiltinVaList; 1322 } 1323 // PPC64 Linux-specifc ABI options. 1324 bool setABI(const std::string &Name) override { 1325 if (Name == "elfv1" || Name == "elfv2") { 1326 ABI = Name; 1327 return true; 1328 } 1329 return false; 1330 } 1331 }; 1332 } // end anonymous namespace. 1333 1334 1335 namespace { 1336 class DarwinPPC32TargetInfo : 1337 public DarwinTargetInfo<PPC32TargetInfo> { 1338 public: 1339 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1340 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1341 HasAlignMac68kSupport = true; 1342 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1343 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1344 LongLongAlign = 32; 1345 SuitableAlign = 128; 1346 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1347 } 1348 BuiltinVaListKind getBuiltinVaListKind() const override { 1349 return TargetInfo::CharPtrBuiltinVaList; 1350 } 1351 }; 1352 1353 class DarwinPPC64TargetInfo : 1354 public DarwinTargetInfo<PPC64TargetInfo> { 1355 public: 1356 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1357 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1358 HasAlignMac68kSupport = true; 1359 SuitableAlign = 128; 1360 DescriptionString = "E-m:o-i64:64-n32:64"; 1361 } 1362 }; 1363 } // end anonymous namespace. 1364 1365 namespace { 1366 static const unsigned NVPTXAddrSpaceMap[] = { 1367 1, // opencl_global 1368 3, // opencl_local 1369 4, // opencl_constant 1370 1, // cuda_device 1371 4, // cuda_constant 1372 3, // cuda_shared 1373 }; 1374 class NVPTXTargetInfo : public TargetInfo { 1375 static const char * const GCCRegNames[]; 1376 static const Builtin::Info BuiltinInfo[]; 1377 public: 1378 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1379 BigEndian = false; 1380 TLSSupported = false; 1381 LongWidth = LongAlign = 64; 1382 AddrSpaceMap = &NVPTXAddrSpaceMap; 1383 UseAddrSpaceMapMangling = true; 1384 // Define available target features 1385 // These must be defined in sorted order! 1386 NoAsmVariants = true; 1387 } 1388 void getTargetDefines(const LangOptions &Opts, 1389 MacroBuilder &Builder) const override { 1390 Builder.defineMacro("__PTX__"); 1391 Builder.defineMacro("__NVPTX__"); 1392 } 1393 void getTargetBuiltins(const Builtin::Info *&Records, 1394 unsigned &NumRecords) const override { 1395 Records = BuiltinInfo; 1396 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1397 } 1398 bool hasFeature(StringRef Feature) const override { 1399 return Feature == "ptx" || Feature == "nvptx"; 1400 } 1401 1402 void getGCCRegNames(const char * const *&Names, 1403 unsigned &NumNames) const override; 1404 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1405 unsigned &NumAliases) const override { 1406 // No aliases. 1407 Aliases = nullptr; 1408 NumAliases = 0; 1409 } 1410 bool validateAsmConstraint(const char *&Name, 1411 TargetInfo::ConstraintInfo &Info) const override { 1412 switch (*Name) { 1413 default: return false; 1414 case 'c': 1415 case 'h': 1416 case 'r': 1417 case 'l': 1418 case 'f': 1419 case 'd': 1420 Info.setAllowsRegister(); 1421 return true; 1422 } 1423 } 1424 const char *getClobbers() const override { 1425 // FIXME: Is this really right? 1426 return ""; 1427 } 1428 BuiltinVaListKind getBuiltinVaListKind() const override { 1429 // FIXME: implement 1430 return TargetInfo::CharPtrBuiltinVaList; 1431 } 1432 bool setCPU(const std::string &Name) override { 1433 bool Valid = llvm::StringSwitch<bool>(Name) 1434 .Case("sm_20", true) 1435 .Case("sm_21", true) 1436 .Case("sm_30", true) 1437 .Case("sm_35", true) 1438 .Default(false); 1439 1440 return Valid; 1441 } 1442 }; 1443 1444 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1445 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1446 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1447 ALL_LANGUAGES }, 1448 #include "clang/Basic/BuiltinsNVPTX.def" 1449 }; 1450 1451 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1452 "r0" 1453 }; 1454 1455 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1456 unsigned &NumNames) const { 1457 Names = GCCRegNames; 1458 NumNames = llvm::array_lengthof(GCCRegNames); 1459 } 1460 1461 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1462 public: 1463 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1464 PointerWidth = PointerAlign = 32; 1465 SizeType = PtrDiffType = TargetInfo::UnsignedInt; 1466 IntPtrType = TargetInfo::SignedInt; 1467 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1468 } 1469 }; 1470 1471 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1472 public: 1473 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1474 PointerWidth = PointerAlign = 64; 1475 SizeType = PtrDiffType = TargetInfo::UnsignedLongLong; 1476 IntPtrType = TargetInfo::SignedLongLong; 1477 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1478 } 1479 }; 1480 } 1481 1482 namespace { 1483 1484 static const unsigned R600AddrSpaceMap[] = { 1485 1, // opencl_global 1486 3, // opencl_local 1487 2, // opencl_constant 1488 1, // cuda_device 1489 2, // cuda_constant 1490 3 // cuda_shared 1491 }; 1492 1493 static const char *DescriptionStringR600 = 1494 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1495 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1496 1497 static const char *DescriptionStringR600DoubleOps = 1498 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1499 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1500 1501 static const char *DescriptionStringSI = 1502 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1503 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1504 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1505 1506 class R600TargetInfo : public TargetInfo { 1507 static const Builtin::Info BuiltinInfo[]; 1508 1509 /// \brief The GPU profiles supported by the R600 target. 1510 enum GPUKind { 1511 GK_NONE, 1512 GK_R600, 1513 GK_R600_DOUBLE_OPS, 1514 GK_R700, 1515 GK_R700_DOUBLE_OPS, 1516 GK_EVERGREEN, 1517 GK_EVERGREEN_DOUBLE_OPS, 1518 GK_NORTHERN_ISLANDS, 1519 GK_CAYMAN, 1520 GK_SOUTHERN_ISLANDS, 1521 GK_SEA_ISLANDS 1522 } GPU; 1523 1524 public: 1525 R600TargetInfo(const llvm::Triple &Triple) 1526 : TargetInfo(Triple), GPU(GK_R600) { 1527 DescriptionString = DescriptionStringR600; 1528 AddrSpaceMap = &R600AddrSpaceMap; 1529 UseAddrSpaceMapMangling = true; 1530 } 1531 1532 const char * getClobbers() const override { 1533 return ""; 1534 } 1535 1536 void getGCCRegNames(const char * const *&Names, 1537 unsigned &numNames) const override { 1538 Names = nullptr; 1539 numNames = 0; 1540 } 1541 1542 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1543 unsigned &NumAliases) const override { 1544 Aliases = nullptr; 1545 NumAliases = 0; 1546 } 1547 1548 bool validateAsmConstraint(const char *&Name, 1549 TargetInfo::ConstraintInfo &info) const override { 1550 return true; 1551 } 1552 1553 void getTargetBuiltins(const Builtin::Info *&Records, 1554 unsigned &NumRecords) const override { 1555 Records = BuiltinInfo; 1556 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin; 1557 } 1558 1559 void getTargetDefines(const LangOptions &Opts, 1560 MacroBuilder &Builder) const override { 1561 Builder.defineMacro("__R600__"); 1562 } 1563 1564 BuiltinVaListKind getBuiltinVaListKind() const override { 1565 return TargetInfo::CharPtrBuiltinVaList; 1566 } 1567 1568 bool setCPU(const std::string &Name) override { 1569 GPU = llvm::StringSwitch<GPUKind>(Name) 1570 .Case("r600" , GK_R600) 1571 .Case("rv610", GK_R600) 1572 .Case("rv620", GK_R600) 1573 .Case("rv630", GK_R600) 1574 .Case("rv635", GK_R600) 1575 .Case("rs780", GK_R600) 1576 .Case("rs880", GK_R600) 1577 .Case("rv670", GK_R600_DOUBLE_OPS) 1578 .Case("rv710", GK_R700) 1579 .Case("rv730", GK_R700) 1580 .Case("rv740", GK_R700_DOUBLE_OPS) 1581 .Case("rv770", GK_R700_DOUBLE_OPS) 1582 .Case("palm", GK_EVERGREEN) 1583 .Case("cedar", GK_EVERGREEN) 1584 .Case("sumo", GK_EVERGREEN) 1585 .Case("sumo2", GK_EVERGREEN) 1586 .Case("redwood", GK_EVERGREEN) 1587 .Case("juniper", GK_EVERGREEN) 1588 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1589 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1590 .Case("barts", GK_NORTHERN_ISLANDS) 1591 .Case("turks", GK_NORTHERN_ISLANDS) 1592 .Case("caicos", GK_NORTHERN_ISLANDS) 1593 .Case("cayman", GK_CAYMAN) 1594 .Case("aruba", GK_CAYMAN) 1595 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1596 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1597 .Case("verde", GK_SOUTHERN_ISLANDS) 1598 .Case("oland", GK_SOUTHERN_ISLANDS) 1599 .Case("bonaire", GK_SEA_ISLANDS) 1600 .Case("kabini", GK_SEA_ISLANDS) 1601 .Case("kaveri", GK_SEA_ISLANDS) 1602 .Case("hawaii", GK_SEA_ISLANDS) 1603 .Case("mullins", GK_SEA_ISLANDS) 1604 .Default(GK_NONE); 1605 1606 if (GPU == GK_NONE) { 1607 return false; 1608 } 1609 1610 // Set the correct data layout 1611 switch (GPU) { 1612 case GK_NONE: 1613 case GK_R600: 1614 case GK_R700: 1615 case GK_EVERGREEN: 1616 case GK_NORTHERN_ISLANDS: 1617 DescriptionString = DescriptionStringR600; 1618 break; 1619 case GK_R600_DOUBLE_OPS: 1620 case GK_R700_DOUBLE_OPS: 1621 case GK_EVERGREEN_DOUBLE_OPS: 1622 case GK_CAYMAN: 1623 DescriptionString = DescriptionStringR600DoubleOps; 1624 break; 1625 case GK_SOUTHERN_ISLANDS: 1626 case GK_SEA_ISLANDS: 1627 DescriptionString = DescriptionStringSI; 1628 break; 1629 } 1630 1631 return true; 1632 } 1633 }; 1634 1635 const Builtin::Info R600TargetInfo::BuiltinInfo[] = { 1636 #define BUILTIN(ID, TYPE, ATTRS) \ 1637 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1638 #include "clang/Basic/BuiltinsR600.def" 1639 }; 1640 1641 } // end anonymous namespace 1642 1643 namespace { 1644 // Namespace for x86 abstract base class 1645 const Builtin::Info BuiltinInfo[] = { 1646 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1647 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1648 ALL_LANGUAGES }, 1649 #include "clang/Basic/BuiltinsX86.def" 1650 }; 1651 1652 static const char* const GCCRegNames[] = { 1653 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1654 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1655 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1656 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1657 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1658 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1659 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1660 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1661 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1662 }; 1663 1664 const TargetInfo::AddlRegName AddlRegNames[] = { 1665 { { "al", "ah", "eax", "rax" }, 0 }, 1666 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1667 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1668 { { "dl", "dh", "edx", "rdx" }, 1 }, 1669 { { "esi", "rsi" }, 4 }, 1670 { { "edi", "rdi" }, 5 }, 1671 { { "esp", "rsp" }, 7 }, 1672 { { "ebp", "rbp" }, 6 }, 1673 }; 1674 1675 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1676 // most of the implementation can be shared. 1677 class X86TargetInfo : public TargetInfo { 1678 enum X86SSEEnum { 1679 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1680 } SSELevel; 1681 enum MMX3DNowEnum { 1682 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1683 } MMX3DNowLevel; 1684 enum XOPEnum { 1685 NoXOP, 1686 SSE4A, 1687 FMA4, 1688 XOP 1689 } XOPLevel; 1690 1691 bool HasAES; 1692 bool HasPCLMUL; 1693 bool HasLZCNT; 1694 bool HasRDRND; 1695 bool HasBMI; 1696 bool HasBMI2; 1697 bool HasPOPCNT; 1698 bool HasRTM; 1699 bool HasPRFCHW; 1700 bool HasRDSEED; 1701 bool HasTBM; 1702 bool HasFMA; 1703 bool HasF16C; 1704 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, HasAVX512VL; 1705 bool HasSHA; 1706 bool HasCX16; 1707 1708 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1709 /// 1710 /// Each enumeration represents a particular CPU supported by Clang. These 1711 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1712 enum CPUKind { 1713 CK_Generic, 1714 1715 /// \name i386 1716 /// i386-generation processors. 1717 //@{ 1718 CK_i386, 1719 //@} 1720 1721 /// \name i486 1722 /// i486-generation processors. 1723 //@{ 1724 CK_i486, 1725 CK_WinChipC6, 1726 CK_WinChip2, 1727 CK_C3, 1728 //@} 1729 1730 /// \name i586 1731 /// i586-generation processors, P5 microarchitecture based. 1732 //@{ 1733 CK_i586, 1734 CK_Pentium, 1735 CK_PentiumMMX, 1736 //@} 1737 1738 /// \name i686 1739 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1740 //@{ 1741 CK_i686, 1742 CK_PentiumPro, 1743 CK_Pentium2, 1744 CK_Pentium3, 1745 CK_Pentium3M, 1746 CK_PentiumM, 1747 CK_C3_2, 1748 1749 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1750 /// Clang however has some logic to suport this. 1751 // FIXME: Warn, deprecate, and potentially remove this. 1752 CK_Yonah, 1753 //@} 1754 1755 /// \name Netburst 1756 /// Netburst microarchitecture based processors. 1757 //@{ 1758 CK_Pentium4, 1759 CK_Pentium4M, 1760 CK_Prescott, 1761 CK_Nocona, 1762 //@} 1763 1764 /// \name Core 1765 /// Core microarchitecture based processors. 1766 //@{ 1767 CK_Core2, 1768 1769 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1770 /// codename which GCC no longer accepts as an option to -march, but Clang 1771 /// has some logic for recognizing it. 1772 // FIXME: Warn, deprecate, and potentially remove this. 1773 CK_Penryn, 1774 //@} 1775 1776 /// \name Atom 1777 /// Atom processors 1778 //@{ 1779 CK_Atom, 1780 CK_Silvermont, 1781 //@} 1782 1783 /// \name Nehalem 1784 /// Nehalem microarchitecture based processors. 1785 //@{ 1786 CK_Corei7, 1787 CK_Corei7AVX, 1788 CK_CoreAVXi, 1789 CK_CoreAVX2, 1790 //@} 1791 1792 /// \name Knights Landing 1793 /// Knights Landing processor. 1794 CK_KNL, 1795 1796 /// \name Skylake Server 1797 /// Skylake server processor. 1798 CK_SKX, 1799 1800 /// \name K6 1801 /// K6 architecture processors. 1802 //@{ 1803 CK_K6, 1804 CK_K6_2, 1805 CK_K6_3, 1806 //@} 1807 1808 /// \name K7 1809 /// K7 architecture processors. 1810 //@{ 1811 CK_Athlon, 1812 CK_AthlonThunderbird, 1813 CK_Athlon4, 1814 CK_AthlonXP, 1815 CK_AthlonMP, 1816 //@} 1817 1818 /// \name K8 1819 /// K8 architecture processors. 1820 //@{ 1821 CK_Athlon64, 1822 CK_Athlon64SSE3, 1823 CK_AthlonFX, 1824 CK_K8, 1825 CK_K8SSE3, 1826 CK_Opteron, 1827 CK_OpteronSSE3, 1828 CK_AMDFAM10, 1829 //@} 1830 1831 /// \name Bobcat 1832 /// Bobcat architecture processors. 1833 //@{ 1834 CK_BTVER1, 1835 CK_BTVER2, 1836 //@} 1837 1838 /// \name Bulldozer 1839 /// Bulldozer architecture processors. 1840 //@{ 1841 CK_BDVER1, 1842 CK_BDVER2, 1843 CK_BDVER3, 1844 CK_BDVER4, 1845 //@} 1846 1847 /// This specification is deprecated and will be removed in the future. 1848 /// Users should prefer \see CK_K8. 1849 // FIXME: Warn on this when the CPU is set to it. 1850 CK_x86_64, 1851 //@} 1852 1853 /// \name Geode 1854 /// Geode processors. 1855 //@{ 1856 CK_Geode 1857 //@} 1858 } CPU; 1859 1860 enum FPMathKind { 1861 FP_Default, 1862 FP_SSE, 1863 FP_387 1864 } FPMath; 1865 1866 public: 1867 X86TargetInfo(const llvm::Triple &Triple) 1868 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1869 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1870 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1871 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), 1872 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1873 HasAVX512PF(false), HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 1874 HasSHA(false), HasCX16(false), CPU(CK_Generic), 1875 FPMath(FP_Default) { 1876 BigEndian = false; 1877 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1878 } 1879 unsigned getFloatEvalMethod() const override { 1880 // X87 evaluates with 80 bits "long double" precision. 1881 return SSELevel == NoSSE ? 2 : 0; 1882 } 1883 void getTargetBuiltins(const Builtin::Info *&Records, 1884 unsigned &NumRecords) const override { 1885 Records = BuiltinInfo; 1886 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1887 } 1888 void getGCCRegNames(const char * const *&Names, 1889 unsigned &NumNames) const override { 1890 Names = GCCRegNames; 1891 NumNames = llvm::array_lengthof(GCCRegNames); 1892 } 1893 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1894 unsigned &NumAliases) const override { 1895 Aliases = nullptr; 1896 NumAliases = 0; 1897 } 1898 void getGCCAddlRegNames(const AddlRegName *&Names, 1899 unsigned &NumNames) const override { 1900 Names = AddlRegNames; 1901 NumNames = llvm::array_lengthof(AddlRegNames); 1902 } 1903 bool validateAsmConstraint(const char *&Name, 1904 TargetInfo::ConstraintInfo &info) const override; 1905 std::string convertConstraint(const char *&Constraint) const override; 1906 const char *getClobbers() const override { 1907 return "~{dirflag},~{fpsr},~{flags}"; 1908 } 1909 void getTargetDefines(const LangOptions &Opts, 1910 MacroBuilder &Builder) const override; 1911 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1912 bool Enabled); 1913 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1914 bool Enabled); 1915 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1916 bool Enabled); 1917 void setFeatureEnabled(llvm::StringMap<bool> &Features, 1918 StringRef Name, bool Enabled) const override { 1919 setFeatureEnabledImpl(Features, Name, Enabled); 1920 } 1921 // This exists purely to cut down on the number of virtual calls in 1922 // getDefaultFeatures which calls this repeatedly. 1923 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1924 StringRef Name, bool Enabled); 1925 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 1926 bool hasFeature(StringRef Feature) const override; 1927 bool handleTargetFeatures(std::vector<std::string> &Features, 1928 DiagnosticsEngine &Diags) override; 1929 StringRef getABI() const override { 1930 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1931 return "avx"; 1932 else if (getTriple().getArch() == llvm::Triple::x86 && 1933 MMX3DNowLevel == NoMMX3DNow) 1934 return "no-mmx"; 1935 return ""; 1936 } 1937 bool setCPU(const std::string &Name) override { 1938 CPU = llvm::StringSwitch<CPUKind>(Name) 1939 .Case("i386", CK_i386) 1940 .Case("i486", CK_i486) 1941 .Case("winchip-c6", CK_WinChipC6) 1942 .Case("winchip2", CK_WinChip2) 1943 .Case("c3", CK_C3) 1944 .Case("i586", CK_i586) 1945 .Case("pentium", CK_Pentium) 1946 .Case("pentium-mmx", CK_PentiumMMX) 1947 .Case("i686", CK_i686) 1948 .Case("pentiumpro", CK_PentiumPro) 1949 .Case("pentium2", CK_Pentium2) 1950 .Case("pentium3", CK_Pentium3) 1951 .Case("pentium3m", CK_Pentium3M) 1952 .Case("pentium-m", CK_PentiumM) 1953 .Case("c3-2", CK_C3_2) 1954 .Case("yonah", CK_Yonah) 1955 .Case("pentium4", CK_Pentium4) 1956 .Case("pentium4m", CK_Pentium4M) 1957 .Case("prescott", CK_Prescott) 1958 .Case("nocona", CK_Nocona) 1959 .Case("core2", CK_Core2) 1960 .Case("penryn", CK_Penryn) 1961 .Case("atom", CK_Atom) 1962 .Case("slm", CK_Silvermont) 1963 .Case("corei7", CK_Corei7) 1964 .Case("corei7-avx", CK_Corei7AVX) 1965 .Case("core-avx-i", CK_CoreAVXi) 1966 .Case("core-avx2", CK_CoreAVX2) 1967 .Case("knl", CK_KNL) 1968 .Case("skx", CK_SKX) 1969 .Case("k6", CK_K6) 1970 .Case("k6-2", CK_K6_2) 1971 .Case("k6-3", CK_K6_3) 1972 .Case("athlon", CK_Athlon) 1973 .Case("athlon-tbird", CK_AthlonThunderbird) 1974 .Case("athlon-4", CK_Athlon4) 1975 .Case("athlon-xp", CK_AthlonXP) 1976 .Case("athlon-mp", CK_AthlonMP) 1977 .Case("athlon64", CK_Athlon64) 1978 .Case("athlon64-sse3", CK_Athlon64SSE3) 1979 .Case("athlon-fx", CK_AthlonFX) 1980 .Case("k8", CK_K8) 1981 .Case("k8-sse3", CK_K8SSE3) 1982 .Case("opteron", CK_Opteron) 1983 .Case("opteron-sse3", CK_OpteronSSE3) 1984 .Case("amdfam10", CK_AMDFAM10) 1985 .Case("btver1", CK_BTVER1) 1986 .Case("btver2", CK_BTVER2) 1987 .Case("bdver1", CK_BDVER1) 1988 .Case("bdver2", CK_BDVER2) 1989 .Case("bdver3", CK_BDVER3) 1990 .Case("bdver4", CK_BDVER4) 1991 .Case("x86-64", CK_x86_64) 1992 .Case("geode", CK_Geode) 1993 .Default(CK_Generic); 1994 1995 // Perform any per-CPU checks necessary to determine if this CPU is 1996 // acceptable. 1997 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1998 // invalid without explaining *why*. 1999 switch (CPU) { 2000 case CK_Generic: 2001 // No processor selected! 2002 return false; 2003 2004 case CK_i386: 2005 case CK_i486: 2006 case CK_WinChipC6: 2007 case CK_WinChip2: 2008 case CK_C3: 2009 case CK_i586: 2010 case CK_Pentium: 2011 case CK_PentiumMMX: 2012 case CK_i686: 2013 case CK_PentiumPro: 2014 case CK_Pentium2: 2015 case CK_Pentium3: 2016 case CK_Pentium3M: 2017 case CK_PentiumM: 2018 case CK_Yonah: 2019 case CK_C3_2: 2020 case CK_Pentium4: 2021 case CK_Pentium4M: 2022 case CK_Prescott: 2023 case CK_K6: 2024 case CK_K6_2: 2025 case CK_K6_3: 2026 case CK_Athlon: 2027 case CK_AthlonThunderbird: 2028 case CK_Athlon4: 2029 case CK_AthlonXP: 2030 case CK_AthlonMP: 2031 case CK_Geode: 2032 // Only accept certain architectures when compiling in 32-bit mode. 2033 if (getTriple().getArch() != llvm::Triple::x86) 2034 return false; 2035 2036 // Fallthrough 2037 case CK_Nocona: 2038 case CK_Core2: 2039 case CK_Penryn: 2040 case CK_Atom: 2041 case CK_Silvermont: 2042 case CK_Corei7: 2043 case CK_Corei7AVX: 2044 case CK_CoreAVXi: 2045 case CK_CoreAVX2: 2046 case CK_KNL: 2047 case CK_SKX: 2048 case CK_Athlon64: 2049 case CK_Athlon64SSE3: 2050 case CK_AthlonFX: 2051 case CK_K8: 2052 case CK_K8SSE3: 2053 case CK_Opteron: 2054 case CK_OpteronSSE3: 2055 case CK_AMDFAM10: 2056 case CK_BTVER1: 2057 case CK_BTVER2: 2058 case CK_BDVER1: 2059 case CK_BDVER2: 2060 case CK_BDVER3: 2061 case CK_BDVER4: 2062 case CK_x86_64: 2063 return true; 2064 } 2065 llvm_unreachable("Unhandled CPU kind"); 2066 } 2067 2068 bool setFPMath(StringRef Name) override; 2069 2070 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2071 // We accept all non-ARM calling conventions 2072 return (CC == CC_X86ThisCall || 2073 CC == CC_X86FastCall || 2074 CC == CC_X86StdCall || 2075 CC == CC_C || 2076 CC == CC_X86Pascal || 2077 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2078 } 2079 2080 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2081 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2082 } 2083 }; 2084 2085 bool X86TargetInfo::setFPMath(StringRef Name) { 2086 if (Name == "387") { 2087 FPMath = FP_387; 2088 return true; 2089 } 2090 if (Name == "sse") { 2091 FPMath = FP_SSE; 2092 return true; 2093 } 2094 return false; 2095 } 2096 2097 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2098 // FIXME: This *really* should not be here. 2099 2100 // X86_64 always has SSE2. 2101 if (getTriple().getArch() == llvm::Triple::x86_64) 2102 setFeatureEnabledImpl(Features, "sse2", true); 2103 2104 switch (CPU) { 2105 case CK_Generic: 2106 case CK_i386: 2107 case CK_i486: 2108 case CK_i586: 2109 case CK_Pentium: 2110 case CK_i686: 2111 case CK_PentiumPro: 2112 break; 2113 case CK_PentiumMMX: 2114 case CK_Pentium2: 2115 setFeatureEnabledImpl(Features, "mmx", true); 2116 break; 2117 case CK_Pentium3: 2118 case CK_Pentium3M: 2119 setFeatureEnabledImpl(Features, "sse", true); 2120 break; 2121 case CK_PentiumM: 2122 case CK_Pentium4: 2123 case CK_Pentium4M: 2124 case CK_x86_64: 2125 setFeatureEnabledImpl(Features, "sse2", true); 2126 break; 2127 case CK_Yonah: 2128 case CK_Prescott: 2129 case CK_Nocona: 2130 setFeatureEnabledImpl(Features, "sse3", true); 2131 setFeatureEnabledImpl(Features, "cx16", true); 2132 break; 2133 case CK_Core2: 2134 setFeatureEnabledImpl(Features, "ssse3", true); 2135 setFeatureEnabledImpl(Features, "cx16", true); 2136 break; 2137 case CK_Penryn: 2138 setFeatureEnabledImpl(Features, "sse4.1", true); 2139 setFeatureEnabledImpl(Features, "cx16", true); 2140 break; 2141 case CK_Atom: 2142 setFeatureEnabledImpl(Features, "ssse3", true); 2143 setFeatureEnabledImpl(Features, "cx16", true); 2144 break; 2145 case CK_Silvermont: 2146 setFeatureEnabledImpl(Features, "sse4.2", true); 2147 setFeatureEnabledImpl(Features, "aes", true); 2148 setFeatureEnabledImpl(Features, "cx16", true); 2149 setFeatureEnabledImpl(Features, "pclmul", true); 2150 break; 2151 case CK_Corei7: 2152 setFeatureEnabledImpl(Features, "sse4.2", true); 2153 setFeatureEnabledImpl(Features, "cx16", true); 2154 break; 2155 case CK_Corei7AVX: 2156 setFeatureEnabledImpl(Features, "avx", true); 2157 setFeatureEnabledImpl(Features, "aes", true); 2158 setFeatureEnabledImpl(Features, "cx16", true); 2159 setFeatureEnabledImpl(Features, "pclmul", true); 2160 break; 2161 case CK_CoreAVXi: 2162 setFeatureEnabledImpl(Features, "avx", true); 2163 setFeatureEnabledImpl(Features, "aes", true); 2164 setFeatureEnabledImpl(Features, "pclmul", true); 2165 setFeatureEnabledImpl(Features, "rdrnd", true); 2166 setFeatureEnabledImpl(Features, "f16c", true); 2167 break; 2168 case CK_CoreAVX2: 2169 setFeatureEnabledImpl(Features, "avx2", true); 2170 setFeatureEnabledImpl(Features, "aes", true); 2171 setFeatureEnabledImpl(Features, "pclmul", true); 2172 setFeatureEnabledImpl(Features, "lzcnt", true); 2173 setFeatureEnabledImpl(Features, "rdrnd", true); 2174 setFeatureEnabledImpl(Features, "f16c", true); 2175 setFeatureEnabledImpl(Features, "bmi", true); 2176 setFeatureEnabledImpl(Features, "bmi2", true); 2177 setFeatureEnabledImpl(Features, "rtm", true); 2178 setFeatureEnabledImpl(Features, "fma", true); 2179 setFeatureEnabledImpl(Features, "cx16", true); 2180 break; 2181 case CK_KNL: 2182 setFeatureEnabledImpl(Features, "avx512f", true); 2183 setFeatureEnabledImpl(Features, "avx512cd", true); 2184 setFeatureEnabledImpl(Features, "avx512er", true); 2185 setFeatureEnabledImpl(Features, "avx512pf", true); 2186 setFeatureEnabledImpl(Features, "aes", true); 2187 setFeatureEnabledImpl(Features, "pclmul", true); 2188 setFeatureEnabledImpl(Features, "lzcnt", true); 2189 setFeatureEnabledImpl(Features, "rdrnd", true); 2190 setFeatureEnabledImpl(Features, "f16c", true); 2191 setFeatureEnabledImpl(Features, "bmi", true); 2192 setFeatureEnabledImpl(Features, "bmi2", true); 2193 setFeatureEnabledImpl(Features, "rtm", true); 2194 setFeatureEnabledImpl(Features, "fma", true); 2195 break; 2196 case CK_SKX: 2197 setFeatureEnabledImpl(Features, "avx512f", true); 2198 setFeatureEnabledImpl(Features, "avx512cd", true); 2199 setFeatureEnabledImpl(Features, "avx512dq", true); 2200 setFeatureEnabledImpl(Features, "avx512bw", true); 2201 setFeatureEnabledImpl(Features, "avx512vl", true); 2202 setFeatureEnabledImpl(Features, "aes", true); 2203 setFeatureEnabledImpl(Features, "pclmul", true); 2204 setFeatureEnabledImpl(Features, "lzcnt", true); 2205 setFeatureEnabledImpl(Features, "rdrnd", true); 2206 setFeatureEnabledImpl(Features, "f16c", true); 2207 setFeatureEnabledImpl(Features, "bmi", true); 2208 setFeatureEnabledImpl(Features, "bmi2", true); 2209 setFeatureEnabledImpl(Features, "rtm", true); 2210 setFeatureEnabledImpl(Features, "fma", true); 2211 break; 2212 case CK_K6: 2213 case CK_WinChipC6: 2214 setFeatureEnabledImpl(Features, "mmx", true); 2215 break; 2216 case CK_K6_2: 2217 case CK_K6_3: 2218 case CK_WinChip2: 2219 case CK_C3: 2220 setFeatureEnabledImpl(Features, "3dnow", true); 2221 break; 2222 case CK_Athlon: 2223 case CK_AthlonThunderbird: 2224 case CK_Geode: 2225 setFeatureEnabledImpl(Features, "3dnowa", true); 2226 break; 2227 case CK_Athlon4: 2228 case CK_AthlonXP: 2229 case CK_AthlonMP: 2230 setFeatureEnabledImpl(Features, "sse", true); 2231 setFeatureEnabledImpl(Features, "3dnowa", true); 2232 break; 2233 case CK_K8: 2234 case CK_Opteron: 2235 case CK_Athlon64: 2236 case CK_AthlonFX: 2237 setFeatureEnabledImpl(Features, "sse2", true); 2238 setFeatureEnabledImpl(Features, "3dnowa", true); 2239 break; 2240 case CK_K8SSE3: 2241 case CK_OpteronSSE3: 2242 case CK_Athlon64SSE3: 2243 setFeatureEnabledImpl(Features, "sse3", true); 2244 setFeatureEnabledImpl(Features, "3dnowa", true); 2245 break; 2246 case CK_AMDFAM10: 2247 setFeatureEnabledImpl(Features, "sse3", true); 2248 setFeatureEnabledImpl(Features, "sse4a", true); 2249 setFeatureEnabledImpl(Features, "3dnowa", true); 2250 setFeatureEnabledImpl(Features, "lzcnt", true); 2251 setFeatureEnabledImpl(Features, "popcnt", true); 2252 break; 2253 case CK_BTVER1: 2254 setFeatureEnabledImpl(Features, "ssse3", true); 2255 setFeatureEnabledImpl(Features, "sse4a", true); 2256 setFeatureEnabledImpl(Features, "cx16", true); 2257 setFeatureEnabledImpl(Features, "lzcnt", true); 2258 setFeatureEnabledImpl(Features, "popcnt", true); 2259 setFeatureEnabledImpl(Features, "prfchw", true); 2260 break; 2261 case CK_BTVER2: 2262 setFeatureEnabledImpl(Features, "avx", true); 2263 setFeatureEnabledImpl(Features, "sse4a", true); 2264 setFeatureEnabledImpl(Features, "lzcnt", true); 2265 setFeatureEnabledImpl(Features, "aes", true); 2266 setFeatureEnabledImpl(Features, "pclmul", true); 2267 setFeatureEnabledImpl(Features, "prfchw", true); 2268 setFeatureEnabledImpl(Features, "bmi", true); 2269 setFeatureEnabledImpl(Features, "f16c", true); 2270 setFeatureEnabledImpl(Features, "cx16", true); 2271 break; 2272 case CK_BDVER1: 2273 setFeatureEnabledImpl(Features, "xop", true); 2274 setFeatureEnabledImpl(Features, "lzcnt", true); 2275 setFeatureEnabledImpl(Features, "aes", true); 2276 setFeatureEnabledImpl(Features, "pclmul", true); 2277 setFeatureEnabledImpl(Features, "prfchw", true); 2278 setFeatureEnabledImpl(Features, "cx16", true); 2279 break; 2280 case CK_BDVER4: 2281 setFeatureEnabledImpl(Features, "avx2", true); 2282 setFeatureEnabledImpl(Features, "bmi2", true); 2283 // FALLTHROUGH 2284 case CK_BDVER2: 2285 case CK_BDVER3: 2286 setFeatureEnabledImpl(Features, "xop", true); 2287 setFeatureEnabledImpl(Features, "lzcnt", true); 2288 setFeatureEnabledImpl(Features, "aes", true); 2289 setFeatureEnabledImpl(Features, "pclmul", true); 2290 setFeatureEnabledImpl(Features, "prfchw", true); 2291 setFeatureEnabledImpl(Features, "bmi", true); 2292 setFeatureEnabledImpl(Features, "fma", true); 2293 setFeatureEnabledImpl(Features, "f16c", true); 2294 setFeatureEnabledImpl(Features, "tbm", true); 2295 setFeatureEnabledImpl(Features, "cx16", true); 2296 break; 2297 case CK_C3_2: 2298 setFeatureEnabledImpl(Features, "sse", true); 2299 break; 2300 } 2301 } 2302 2303 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2304 X86SSEEnum Level, bool Enabled) { 2305 if (Enabled) { 2306 switch (Level) { 2307 case AVX512F: 2308 Features["avx512f"] = true; 2309 case AVX2: 2310 Features["avx2"] = true; 2311 case AVX: 2312 Features["avx"] = true; 2313 case SSE42: 2314 Features["sse4.2"] = true; 2315 case SSE41: 2316 Features["sse4.1"] = true; 2317 case SSSE3: 2318 Features["ssse3"] = true; 2319 case SSE3: 2320 Features["sse3"] = true; 2321 case SSE2: 2322 Features["sse2"] = true; 2323 case SSE1: 2324 Features["sse"] = true; 2325 case NoSSE: 2326 break; 2327 } 2328 return; 2329 } 2330 2331 switch (Level) { 2332 case NoSSE: 2333 case SSE1: 2334 Features["sse"] = false; 2335 case SSE2: 2336 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2337 Features["sha"] = false; 2338 case SSE3: 2339 Features["sse3"] = false; 2340 setXOPLevel(Features, NoXOP, false); 2341 case SSSE3: 2342 Features["ssse3"] = false; 2343 case SSE41: 2344 Features["sse4.1"] = false; 2345 case SSE42: 2346 Features["sse4.2"] = false; 2347 case AVX: 2348 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2349 setXOPLevel(Features, FMA4, false); 2350 case AVX2: 2351 Features["avx2"] = false; 2352 case AVX512F: 2353 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = Features["avx512pf"] = 2354 Features["avx512dq"] = Features["avx512bw"] = Features["avx512vl"] = false; 2355 } 2356 } 2357 2358 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2359 MMX3DNowEnum Level, bool Enabled) { 2360 if (Enabled) { 2361 switch (Level) { 2362 case AMD3DNowAthlon: 2363 Features["3dnowa"] = true; 2364 case AMD3DNow: 2365 Features["3dnow"] = true; 2366 case MMX: 2367 Features["mmx"] = true; 2368 case NoMMX3DNow: 2369 break; 2370 } 2371 return; 2372 } 2373 2374 switch (Level) { 2375 case NoMMX3DNow: 2376 case MMX: 2377 Features["mmx"] = false; 2378 case AMD3DNow: 2379 Features["3dnow"] = false; 2380 case AMD3DNowAthlon: 2381 Features["3dnowa"] = false; 2382 } 2383 } 2384 2385 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2386 bool Enabled) { 2387 if (Enabled) { 2388 switch (Level) { 2389 case XOP: 2390 Features["xop"] = true; 2391 case FMA4: 2392 Features["fma4"] = true; 2393 setSSELevel(Features, AVX, true); 2394 case SSE4A: 2395 Features["sse4a"] = true; 2396 setSSELevel(Features, SSE3, true); 2397 case NoXOP: 2398 break; 2399 } 2400 return; 2401 } 2402 2403 switch (Level) { 2404 case NoXOP: 2405 case SSE4A: 2406 Features["sse4a"] = false; 2407 case FMA4: 2408 Features["fma4"] = false; 2409 case XOP: 2410 Features["xop"] = false; 2411 } 2412 } 2413 2414 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2415 StringRef Name, bool Enabled) { 2416 // FIXME: This *really* should not be here. We need some way of translating 2417 // options into llvm subtarget features. 2418 if (Name == "sse4") 2419 Name = "sse4.2"; 2420 2421 Features[Name] = Enabled; 2422 2423 if (Name == "mmx") { 2424 setMMXLevel(Features, MMX, Enabled); 2425 } else if (Name == "sse") { 2426 setSSELevel(Features, SSE1, Enabled); 2427 } else if (Name == "sse2") { 2428 setSSELevel(Features, SSE2, Enabled); 2429 } else if (Name == "sse3") { 2430 setSSELevel(Features, SSE3, Enabled); 2431 } else if (Name == "ssse3") { 2432 setSSELevel(Features, SSSE3, Enabled); 2433 } else if (Name == "sse4.2") { 2434 setSSELevel(Features, SSE42, Enabled); 2435 } else if (Name == "sse4.1") { 2436 setSSELevel(Features, SSE41, Enabled); 2437 } else if (Name == "3dnow") { 2438 setMMXLevel(Features, AMD3DNow, Enabled); 2439 } else if (Name == "3dnowa") { 2440 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2441 } else if (Name == "aes") { 2442 if (Enabled) 2443 setSSELevel(Features, SSE2, Enabled); 2444 } else if (Name == "pclmul") { 2445 if (Enabled) 2446 setSSELevel(Features, SSE2, Enabled); 2447 } else if (Name == "avx") { 2448 setSSELevel(Features, AVX, Enabled); 2449 } else if (Name == "avx2") { 2450 setSSELevel(Features, AVX2, Enabled); 2451 } else if (Name == "avx512f") { 2452 setSSELevel(Features, AVX512F, Enabled); 2453 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2454 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2455 if (Enabled) 2456 setSSELevel(Features, AVX512F, Enabled); 2457 } else if (Name == "fma") { 2458 if (Enabled) 2459 setSSELevel(Features, AVX, Enabled); 2460 } else if (Name == "fma4") { 2461 setXOPLevel(Features, FMA4, Enabled); 2462 } else if (Name == "xop") { 2463 setXOPLevel(Features, XOP, Enabled); 2464 } else if (Name == "sse4a") { 2465 setXOPLevel(Features, SSE4A, Enabled); 2466 } else if (Name == "f16c") { 2467 if (Enabled) 2468 setSSELevel(Features, AVX, Enabled); 2469 } else if (Name == "sha") { 2470 if (Enabled) 2471 setSSELevel(Features, SSE2, Enabled); 2472 } 2473 } 2474 2475 /// handleTargetFeatures - Perform initialization based on the user 2476 /// configured set of features. 2477 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2478 DiagnosticsEngine &Diags) { 2479 // Remember the maximum enabled sselevel. 2480 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2481 // Ignore disabled features. 2482 if (Features[i][0] == '-') 2483 continue; 2484 2485 StringRef Feature = StringRef(Features[i]).substr(1); 2486 2487 if (Feature == "aes") { 2488 HasAES = true; 2489 continue; 2490 } 2491 2492 if (Feature == "pclmul") { 2493 HasPCLMUL = true; 2494 continue; 2495 } 2496 2497 if (Feature == "lzcnt") { 2498 HasLZCNT = true; 2499 continue; 2500 } 2501 2502 if (Feature == "rdrnd") { 2503 HasRDRND = true; 2504 continue; 2505 } 2506 2507 if (Feature == "bmi") { 2508 HasBMI = true; 2509 continue; 2510 } 2511 2512 if (Feature == "bmi2") { 2513 HasBMI2 = true; 2514 continue; 2515 } 2516 2517 if (Feature == "popcnt") { 2518 HasPOPCNT = true; 2519 continue; 2520 } 2521 2522 if (Feature == "rtm") { 2523 HasRTM = true; 2524 continue; 2525 } 2526 2527 if (Feature == "prfchw") { 2528 HasPRFCHW = true; 2529 continue; 2530 } 2531 2532 if (Feature == "rdseed") { 2533 HasRDSEED = true; 2534 continue; 2535 } 2536 2537 if (Feature == "tbm") { 2538 HasTBM = true; 2539 continue; 2540 } 2541 2542 if (Feature == "fma") { 2543 HasFMA = true; 2544 continue; 2545 } 2546 2547 if (Feature == "f16c") { 2548 HasF16C = true; 2549 continue; 2550 } 2551 2552 if (Feature == "avx512cd") { 2553 HasAVX512CD = true; 2554 continue; 2555 } 2556 2557 if (Feature == "avx512er") { 2558 HasAVX512ER = true; 2559 continue; 2560 } 2561 2562 if (Feature == "avx512pf") { 2563 HasAVX512PF = true; 2564 continue; 2565 } 2566 2567 if (Feature == "avx512dq") { 2568 HasAVX512DQ = true; 2569 continue; 2570 } 2571 2572 if (Feature == "avx512bw") { 2573 HasAVX512BW = true; 2574 continue; 2575 } 2576 2577 if (Feature == "avx512vl") { 2578 HasAVX512VL = true; 2579 continue; 2580 } 2581 2582 if (Feature == "sha") { 2583 HasSHA = true; 2584 continue; 2585 } 2586 2587 if (Feature == "cx16") { 2588 HasCX16 = true; 2589 continue; 2590 } 2591 2592 assert(Features[i][0] == '+' && "Invalid target feature!"); 2593 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2594 .Case("avx512f", AVX512F) 2595 .Case("avx2", AVX2) 2596 .Case("avx", AVX) 2597 .Case("sse4.2", SSE42) 2598 .Case("sse4.1", SSE41) 2599 .Case("ssse3", SSSE3) 2600 .Case("sse3", SSE3) 2601 .Case("sse2", SSE2) 2602 .Case("sse", SSE1) 2603 .Default(NoSSE); 2604 SSELevel = std::max(SSELevel, Level); 2605 2606 MMX3DNowEnum ThreeDNowLevel = 2607 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2608 .Case("3dnowa", AMD3DNowAthlon) 2609 .Case("3dnow", AMD3DNow) 2610 .Case("mmx", MMX) 2611 .Default(NoMMX3DNow); 2612 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2613 2614 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2615 .Case("xop", XOP) 2616 .Case("fma4", FMA4) 2617 .Case("sse4a", SSE4A) 2618 .Default(NoXOP); 2619 XOPLevel = std::max(XOPLevel, XLevel); 2620 } 2621 2622 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2623 // Can't do this earlier because we need to be able to explicitly enable 2624 // popcnt and still disable sse4.2. 2625 if (!HasPOPCNT && SSELevel >= SSE42 && 2626 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2627 HasPOPCNT = true; 2628 Features.push_back("+popcnt"); 2629 } 2630 2631 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2632 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2633 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2634 HasPRFCHW = true; 2635 Features.push_back("+prfchw"); 2636 } 2637 2638 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2639 // matches the selected sse level. 2640 if (FPMath == FP_SSE && SSELevel < SSE1) { 2641 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2642 return false; 2643 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2644 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2645 return false; 2646 } 2647 2648 // Don't tell the backend if we're turning off mmx; it will end up disabling 2649 // SSE, which we don't want. 2650 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2651 // then enable MMX. 2652 std::vector<std::string>::iterator it; 2653 it = std::find(Features.begin(), Features.end(), "-mmx"); 2654 if (it != Features.end()) 2655 Features.erase(it); 2656 else if (SSELevel > NoSSE) 2657 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2658 return true; 2659 } 2660 2661 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2662 /// definitions for this particular subtarget. 2663 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2664 MacroBuilder &Builder) const { 2665 // Target identification. 2666 if (getTriple().getArch() == llvm::Triple::x86_64) { 2667 Builder.defineMacro("__amd64__"); 2668 Builder.defineMacro("__amd64"); 2669 Builder.defineMacro("__x86_64"); 2670 Builder.defineMacro("__x86_64__"); 2671 if (getTriple().getArchName() == "x86_64h") { 2672 Builder.defineMacro("__x86_64h"); 2673 Builder.defineMacro("__x86_64h__"); 2674 } 2675 } else { 2676 DefineStd(Builder, "i386", Opts); 2677 } 2678 2679 // Subtarget options. 2680 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2681 // truly should be based on -mtune options. 2682 switch (CPU) { 2683 case CK_Generic: 2684 break; 2685 case CK_i386: 2686 // The rest are coming from the i386 define above. 2687 Builder.defineMacro("__tune_i386__"); 2688 break; 2689 case CK_i486: 2690 case CK_WinChipC6: 2691 case CK_WinChip2: 2692 case CK_C3: 2693 defineCPUMacros(Builder, "i486"); 2694 break; 2695 case CK_PentiumMMX: 2696 Builder.defineMacro("__pentium_mmx__"); 2697 Builder.defineMacro("__tune_pentium_mmx__"); 2698 // Fallthrough 2699 case CK_i586: 2700 case CK_Pentium: 2701 defineCPUMacros(Builder, "i586"); 2702 defineCPUMacros(Builder, "pentium"); 2703 break; 2704 case CK_Pentium3: 2705 case CK_Pentium3M: 2706 case CK_PentiumM: 2707 Builder.defineMacro("__tune_pentium3__"); 2708 // Fallthrough 2709 case CK_Pentium2: 2710 case CK_C3_2: 2711 Builder.defineMacro("__tune_pentium2__"); 2712 // Fallthrough 2713 case CK_PentiumPro: 2714 Builder.defineMacro("__tune_i686__"); 2715 Builder.defineMacro("__tune_pentiumpro__"); 2716 // Fallthrough 2717 case CK_i686: 2718 Builder.defineMacro("__i686"); 2719 Builder.defineMacro("__i686__"); 2720 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2721 Builder.defineMacro("__pentiumpro"); 2722 Builder.defineMacro("__pentiumpro__"); 2723 break; 2724 case CK_Pentium4: 2725 case CK_Pentium4M: 2726 defineCPUMacros(Builder, "pentium4"); 2727 break; 2728 case CK_Yonah: 2729 case CK_Prescott: 2730 case CK_Nocona: 2731 defineCPUMacros(Builder, "nocona"); 2732 break; 2733 case CK_Core2: 2734 case CK_Penryn: 2735 defineCPUMacros(Builder, "core2"); 2736 break; 2737 case CK_Atom: 2738 defineCPUMacros(Builder, "atom"); 2739 break; 2740 case CK_Silvermont: 2741 defineCPUMacros(Builder, "slm"); 2742 break; 2743 case CK_Corei7: 2744 case CK_Corei7AVX: 2745 case CK_CoreAVXi: 2746 case CK_CoreAVX2: 2747 defineCPUMacros(Builder, "corei7"); 2748 break; 2749 case CK_KNL: 2750 defineCPUMacros(Builder, "knl"); 2751 break; 2752 case CK_SKX: 2753 defineCPUMacros(Builder, "skx"); 2754 break; 2755 case CK_K6_2: 2756 Builder.defineMacro("__k6_2__"); 2757 Builder.defineMacro("__tune_k6_2__"); 2758 // Fallthrough 2759 case CK_K6_3: 2760 if (CPU != CK_K6_2) { // In case of fallthrough 2761 // FIXME: GCC may be enabling these in cases where some other k6 2762 // architecture is specified but -m3dnow is explicitly provided. The 2763 // exact semantics need to be determined and emulated here. 2764 Builder.defineMacro("__k6_3__"); 2765 Builder.defineMacro("__tune_k6_3__"); 2766 } 2767 // Fallthrough 2768 case CK_K6: 2769 defineCPUMacros(Builder, "k6"); 2770 break; 2771 case CK_Athlon: 2772 case CK_AthlonThunderbird: 2773 case CK_Athlon4: 2774 case CK_AthlonXP: 2775 case CK_AthlonMP: 2776 defineCPUMacros(Builder, "athlon"); 2777 if (SSELevel != NoSSE) { 2778 Builder.defineMacro("__athlon_sse__"); 2779 Builder.defineMacro("__tune_athlon_sse__"); 2780 } 2781 break; 2782 case CK_K8: 2783 case CK_K8SSE3: 2784 case CK_x86_64: 2785 case CK_Opteron: 2786 case CK_OpteronSSE3: 2787 case CK_Athlon64: 2788 case CK_Athlon64SSE3: 2789 case CK_AthlonFX: 2790 defineCPUMacros(Builder, "k8"); 2791 break; 2792 case CK_AMDFAM10: 2793 defineCPUMacros(Builder, "amdfam10"); 2794 break; 2795 case CK_BTVER1: 2796 defineCPUMacros(Builder, "btver1"); 2797 break; 2798 case CK_BTVER2: 2799 defineCPUMacros(Builder, "btver2"); 2800 break; 2801 case CK_BDVER1: 2802 defineCPUMacros(Builder, "bdver1"); 2803 break; 2804 case CK_BDVER2: 2805 defineCPUMacros(Builder, "bdver2"); 2806 break; 2807 case CK_BDVER3: 2808 defineCPUMacros(Builder, "bdver3"); 2809 break; 2810 case CK_BDVER4: 2811 defineCPUMacros(Builder, "bdver4"); 2812 break; 2813 case CK_Geode: 2814 defineCPUMacros(Builder, "geode"); 2815 break; 2816 } 2817 2818 // Target properties. 2819 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2820 2821 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2822 // functions in glibc header files that use FP Stack inline asm which the 2823 // backend can't deal with (PR879). 2824 Builder.defineMacro("__NO_MATH_INLINES"); 2825 2826 if (HasAES) 2827 Builder.defineMacro("__AES__"); 2828 2829 if (HasPCLMUL) 2830 Builder.defineMacro("__PCLMUL__"); 2831 2832 if (HasLZCNT) 2833 Builder.defineMacro("__LZCNT__"); 2834 2835 if (HasRDRND) 2836 Builder.defineMacro("__RDRND__"); 2837 2838 if (HasBMI) 2839 Builder.defineMacro("__BMI__"); 2840 2841 if (HasBMI2) 2842 Builder.defineMacro("__BMI2__"); 2843 2844 if (HasPOPCNT) 2845 Builder.defineMacro("__POPCNT__"); 2846 2847 if (HasRTM) 2848 Builder.defineMacro("__RTM__"); 2849 2850 if (HasPRFCHW) 2851 Builder.defineMacro("__PRFCHW__"); 2852 2853 if (HasRDSEED) 2854 Builder.defineMacro("__RDSEED__"); 2855 2856 if (HasTBM) 2857 Builder.defineMacro("__TBM__"); 2858 2859 switch (XOPLevel) { 2860 case XOP: 2861 Builder.defineMacro("__XOP__"); 2862 case FMA4: 2863 Builder.defineMacro("__FMA4__"); 2864 case SSE4A: 2865 Builder.defineMacro("__SSE4A__"); 2866 case NoXOP: 2867 break; 2868 } 2869 2870 if (HasFMA) 2871 Builder.defineMacro("__FMA__"); 2872 2873 if (HasF16C) 2874 Builder.defineMacro("__F16C__"); 2875 2876 if (HasAVX512CD) 2877 Builder.defineMacro("__AVX512CD__"); 2878 if (HasAVX512ER) 2879 Builder.defineMacro("__AVX512ER__"); 2880 if (HasAVX512PF) 2881 Builder.defineMacro("__AVX512PF__"); 2882 if (HasAVX512DQ) 2883 Builder.defineMacro("__AVX512DQ__"); 2884 if (HasAVX512BW) 2885 Builder.defineMacro("__AVX512BW__"); 2886 if (HasAVX512VL) 2887 Builder.defineMacro("__AVX512VL__"); 2888 2889 if (HasSHA) 2890 Builder.defineMacro("__SHA__"); 2891 2892 if (HasCX16) 2893 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2894 2895 // Each case falls through to the previous one here. 2896 switch (SSELevel) { 2897 case AVX512F: 2898 Builder.defineMacro("__AVX512F__"); 2899 case AVX2: 2900 Builder.defineMacro("__AVX2__"); 2901 case AVX: 2902 Builder.defineMacro("__AVX__"); 2903 case SSE42: 2904 Builder.defineMacro("__SSE4_2__"); 2905 case SSE41: 2906 Builder.defineMacro("__SSE4_1__"); 2907 case SSSE3: 2908 Builder.defineMacro("__SSSE3__"); 2909 case SSE3: 2910 Builder.defineMacro("__SSE3__"); 2911 case SSE2: 2912 Builder.defineMacro("__SSE2__"); 2913 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2914 case SSE1: 2915 Builder.defineMacro("__SSE__"); 2916 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2917 case NoSSE: 2918 break; 2919 } 2920 2921 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2922 switch (SSELevel) { 2923 case AVX512F: 2924 case AVX2: 2925 case AVX: 2926 case SSE42: 2927 case SSE41: 2928 case SSSE3: 2929 case SSE3: 2930 case SSE2: 2931 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2932 break; 2933 case SSE1: 2934 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2935 break; 2936 default: 2937 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2938 } 2939 } 2940 2941 // Each case falls through to the previous one here. 2942 switch (MMX3DNowLevel) { 2943 case AMD3DNowAthlon: 2944 Builder.defineMacro("__3dNOW_A__"); 2945 case AMD3DNow: 2946 Builder.defineMacro("__3dNOW__"); 2947 case MMX: 2948 Builder.defineMacro("__MMX__"); 2949 case NoMMX3DNow: 2950 break; 2951 } 2952 2953 if (CPU >= CK_i486) { 2954 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2955 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2956 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2957 } 2958 if (CPU >= CK_i586) 2959 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2960 } 2961 2962 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2963 return llvm::StringSwitch<bool>(Feature) 2964 .Case("aes", HasAES) 2965 .Case("avx", SSELevel >= AVX) 2966 .Case("avx2", SSELevel >= AVX2) 2967 .Case("avx512f", SSELevel >= AVX512F) 2968 .Case("avx512cd", HasAVX512CD) 2969 .Case("avx512er", HasAVX512ER) 2970 .Case("avx512pf", HasAVX512PF) 2971 .Case("avx512dq", HasAVX512DQ) 2972 .Case("avx512bw", HasAVX512BW) 2973 .Case("avx512vl", HasAVX512VL) 2974 .Case("bmi", HasBMI) 2975 .Case("bmi2", HasBMI2) 2976 .Case("cx16", HasCX16) 2977 .Case("f16c", HasF16C) 2978 .Case("fma", HasFMA) 2979 .Case("fma4", XOPLevel >= FMA4) 2980 .Case("tbm", HasTBM) 2981 .Case("lzcnt", HasLZCNT) 2982 .Case("rdrnd", HasRDRND) 2983 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2984 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2985 .Case("mmx", MMX3DNowLevel >= MMX) 2986 .Case("pclmul", HasPCLMUL) 2987 .Case("popcnt", HasPOPCNT) 2988 .Case("rtm", HasRTM) 2989 .Case("prfchw", HasPRFCHW) 2990 .Case("rdseed", HasRDSEED) 2991 .Case("sha", HasSHA) 2992 .Case("sse", SSELevel >= SSE1) 2993 .Case("sse2", SSELevel >= SSE2) 2994 .Case("sse3", SSELevel >= SSE3) 2995 .Case("ssse3", SSELevel >= SSSE3) 2996 .Case("sse4.1", SSELevel >= SSE41) 2997 .Case("sse4.2", SSELevel >= SSE42) 2998 .Case("sse4a", XOPLevel >= SSE4A) 2999 .Case("x86", true) 3000 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3001 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3002 .Case("xop", XOPLevel >= XOP) 3003 .Default(false); 3004 } 3005 3006 bool 3007 X86TargetInfo::validateAsmConstraint(const char *&Name, 3008 TargetInfo::ConstraintInfo &Info) const { 3009 switch (*Name) { 3010 default: return false; 3011 case 'Y': // first letter of a pair: 3012 switch (*(Name+1)) { 3013 default: return false; 3014 case '0': // First SSE register. 3015 case 't': // Any SSE register, when SSE2 is enabled. 3016 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3017 case 'm': // any MMX register, when inter-unit moves enabled. 3018 break; // falls through to setAllowsRegister. 3019 } 3020 case 'f': // any x87 floating point stack register. 3021 // Constraint 'f' cannot be used for output operands. 3022 if (Info.ConstraintStr[0] == '=') 3023 return false; 3024 3025 Info.setAllowsRegister(); 3026 return true; 3027 case 'a': // eax. 3028 case 'b': // ebx. 3029 case 'c': // ecx. 3030 case 'd': // edx. 3031 case 'S': // esi. 3032 case 'D': // edi. 3033 case 'A': // edx:eax. 3034 case 't': // top of floating point stack. 3035 case 'u': // second from top of floating point stack. 3036 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3037 case 'y': // Any MMX register. 3038 case 'x': // Any SSE register. 3039 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3040 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3041 case 'l': // "Index" registers: any general register that can be used as an 3042 // index in a base+index memory access. 3043 Info.setAllowsRegister(); 3044 return true; 3045 case 'C': // SSE floating point constant. 3046 case 'G': // x87 floating point constant. 3047 case 'e': // 32-bit signed integer constant for use with zero-extending 3048 // x86_64 instructions. 3049 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3050 // x86_64 instructions. 3051 return true; 3052 } 3053 } 3054 3055 3056 std::string 3057 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3058 switch (*Constraint) { 3059 case 'a': return std::string("{ax}"); 3060 case 'b': return std::string("{bx}"); 3061 case 'c': return std::string("{cx}"); 3062 case 'd': return std::string("{dx}"); 3063 case 'S': return std::string("{si}"); 3064 case 'D': return std::string("{di}"); 3065 case 'p': // address 3066 return std::string("im"); 3067 case 't': // top of floating point stack. 3068 return std::string("{st}"); 3069 case 'u': // second from top of floating point stack. 3070 return std::string("{st(1)}"); // second from top of floating point stack. 3071 default: 3072 return std::string(1, *Constraint); 3073 } 3074 } 3075 } // end anonymous namespace 3076 3077 namespace { 3078 // X86-32 generic target 3079 class X86_32TargetInfo : public X86TargetInfo { 3080 public: 3081 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3082 DoubleAlign = LongLongAlign = 32; 3083 LongDoubleWidth = 96; 3084 LongDoubleAlign = 32; 3085 SuitableAlign = 128; 3086 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3087 SizeType = UnsignedInt; 3088 PtrDiffType = SignedInt; 3089 IntPtrType = SignedInt; 3090 RegParmMax = 3; 3091 3092 // Use fpret for all types. 3093 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3094 (1 << TargetInfo::Double) | 3095 (1 << TargetInfo::LongDouble)); 3096 3097 // x86-32 has atomics up to 8 bytes 3098 // FIXME: Check that we actually have cmpxchg8b before setting 3099 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3100 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3101 } 3102 BuiltinVaListKind getBuiltinVaListKind() const override { 3103 return TargetInfo::CharPtrBuiltinVaList; 3104 } 3105 3106 int getEHDataRegisterNumber(unsigned RegNo) const override { 3107 if (RegNo == 0) return 0; 3108 if (RegNo == 1) return 2; 3109 return -1; 3110 } 3111 bool validateInputSize(StringRef Constraint, 3112 unsigned Size) const override { 3113 switch (Constraint[0]) { 3114 default: break; 3115 case 'a': 3116 case 'b': 3117 case 'c': 3118 case 'd': 3119 return Size <= 32; 3120 } 3121 3122 return true; 3123 } 3124 }; 3125 } // end anonymous namespace 3126 3127 namespace { 3128 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3129 public: 3130 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3131 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3132 3133 unsigned getFloatEvalMethod() const override { 3134 unsigned Major, Minor, Micro; 3135 getTriple().getOSVersion(Major, Minor, Micro); 3136 // New NetBSD uses the default rounding mode. 3137 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3138 return X86_32TargetInfo::getFloatEvalMethod(); 3139 // NetBSD before 6.99.26 defaults to "double" rounding. 3140 return 1; 3141 } 3142 }; 3143 } // end anonymous namespace 3144 3145 namespace { 3146 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3147 public: 3148 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3149 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3150 SizeType = UnsignedLong; 3151 IntPtrType = SignedLong; 3152 PtrDiffType = SignedLong; 3153 } 3154 }; 3155 } // end anonymous namespace 3156 3157 namespace { 3158 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3159 public: 3160 BitrigI386TargetInfo(const llvm::Triple &Triple) 3161 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3162 SizeType = UnsignedLong; 3163 IntPtrType = SignedLong; 3164 PtrDiffType = SignedLong; 3165 } 3166 }; 3167 } // end anonymous namespace 3168 3169 namespace { 3170 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3171 public: 3172 DarwinI386TargetInfo(const llvm::Triple &Triple) 3173 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3174 LongDoubleWidth = 128; 3175 LongDoubleAlign = 128; 3176 SuitableAlign = 128; 3177 MaxVectorAlign = 256; 3178 SizeType = UnsignedLong; 3179 IntPtrType = SignedLong; 3180 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3181 HasAlignMac68kSupport = true; 3182 } 3183 3184 }; 3185 } // end anonymous namespace 3186 3187 namespace { 3188 // x86-32 Windows target 3189 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3190 public: 3191 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3192 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3193 WCharType = UnsignedShort; 3194 DoubleAlign = LongLongAlign = 64; 3195 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3196 } 3197 void getTargetDefines(const LangOptions &Opts, 3198 MacroBuilder &Builder) const override { 3199 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3200 } 3201 }; 3202 3203 // x86-32 Windows Visual Studio target 3204 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3205 public: 3206 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3207 : WindowsX86_32TargetInfo(Triple) { 3208 LongDoubleWidth = LongDoubleAlign = 64; 3209 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3210 } 3211 void getTargetDefines(const LangOptions &Opts, 3212 MacroBuilder &Builder) const override { 3213 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3214 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3215 // The value of the following reflects processor type. 3216 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3217 // We lost the original triple, so we use the default. 3218 Builder.defineMacro("_M_IX86", "600"); 3219 } 3220 }; 3221 } // end anonymous namespace 3222 3223 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3224 Builder.defineMacro("__MSVCRT__"); 3225 Builder.defineMacro("__MINGW32__"); 3226 3227 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports 3228 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3229 // macro anyway for pre-processor compatibility. 3230 if (Opts.MicrosoftExt) 3231 Builder.defineMacro("__declspec", "__declspec"); 3232 else 3233 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3234 3235 if (!Opts.MicrosoftExt) { 3236 // Provide macros for all the calling convention keywords. Provide both 3237 // single and double underscore prefixed variants. These are available on 3238 // x64 as well as x86, even though they have no effect. 3239 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3240 for (const char *CC : CCs) { 3241 std::string GCCSpelling = "__attribute__((__"; 3242 GCCSpelling += CC; 3243 GCCSpelling += "__))"; 3244 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3245 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3246 } 3247 } 3248 } 3249 3250 namespace { 3251 // x86-32 MinGW target 3252 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3253 public: 3254 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3255 : WindowsX86_32TargetInfo(Triple) {} 3256 void getTargetDefines(const LangOptions &Opts, 3257 MacroBuilder &Builder) const override { 3258 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3259 DefineStd(Builder, "WIN32", Opts); 3260 DefineStd(Builder, "WINNT", Opts); 3261 Builder.defineMacro("_X86_"); 3262 addMinGWDefines(Opts, Builder); 3263 } 3264 }; 3265 } // end anonymous namespace 3266 3267 namespace { 3268 // x86-32 Cygwin target 3269 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3270 public: 3271 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3272 : X86_32TargetInfo(Triple) { 3273 TLSSupported = false; 3274 WCharType = UnsignedShort; 3275 DoubleAlign = LongLongAlign = 64; 3276 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3277 } 3278 void getTargetDefines(const LangOptions &Opts, 3279 MacroBuilder &Builder) const override { 3280 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3281 Builder.defineMacro("_X86_"); 3282 Builder.defineMacro("__CYGWIN__"); 3283 Builder.defineMacro("__CYGWIN32__"); 3284 DefineStd(Builder, "unix", Opts); 3285 if (Opts.CPlusPlus) 3286 Builder.defineMacro("_GNU_SOURCE"); 3287 } 3288 }; 3289 } // end anonymous namespace 3290 3291 namespace { 3292 // x86-32 Haiku target 3293 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3294 public: 3295 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3296 SizeType = UnsignedLong; 3297 IntPtrType = SignedLong; 3298 PtrDiffType = SignedLong; 3299 ProcessIDType = SignedLong; 3300 this->UserLabelPrefix = ""; 3301 this->TLSSupported = false; 3302 } 3303 void getTargetDefines(const LangOptions &Opts, 3304 MacroBuilder &Builder) const override { 3305 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3306 Builder.defineMacro("__INTEL__"); 3307 Builder.defineMacro("__HAIKU__"); 3308 } 3309 }; 3310 } // end anonymous namespace 3311 3312 // RTEMS Target 3313 template<typename Target> 3314 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3315 protected: 3316 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3317 MacroBuilder &Builder) const override { 3318 // RTEMS defines; list based off of gcc output 3319 3320 Builder.defineMacro("__rtems__"); 3321 Builder.defineMacro("__ELF__"); 3322 } 3323 3324 public: 3325 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3326 this->UserLabelPrefix = ""; 3327 3328 switch (Triple.getArch()) { 3329 default: 3330 case llvm::Triple::x86: 3331 // this->MCountName = ".mcount"; 3332 break; 3333 case llvm::Triple::mips: 3334 case llvm::Triple::mipsel: 3335 case llvm::Triple::ppc: 3336 case llvm::Triple::ppc64: 3337 case llvm::Triple::ppc64le: 3338 // this->MCountName = "_mcount"; 3339 break; 3340 case llvm::Triple::arm: 3341 // this->MCountName = "__mcount"; 3342 break; 3343 } 3344 } 3345 }; 3346 3347 namespace { 3348 // x86-32 RTEMS target 3349 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3350 public: 3351 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3352 SizeType = UnsignedLong; 3353 IntPtrType = SignedLong; 3354 PtrDiffType = SignedLong; 3355 this->UserLabelPrefix = ""; 3356 } 3357 void getTargetDefines(const LangOptions &Opts, 3358 MacroBuilder &Builder) const override { 3359 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3360 Builder.defineMacro("__INTEL__"); 3361 Builder.defineMacro("__rtems__"); 3362 } 3363 }; 3364 } // end anonymous namespace 3365 3366 namespace { 3367 // x86-64 generic target 3368 class X86_64TargetInfo : public X86TargetInfo { 3369 public: 3370 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3371 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3372 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3373 LongDoubleWidth = 128; 3374 LongDoubleAlign = 128; 3375 LargeArrayMinWidth = 128; 3376 LargeArrayAlign = 128; 3377 SuitableAlign = 128; 3378 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3379 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3380 IntPtrType = IsX32 ? SignedInt : SignedLong; 3381 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3382 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3383 RegParmMax = 6; 3384 3385 DescriptionString = (IsX32) 3386 ? "e-m:e-" "p:32:32-" "i64:64-f80:128-n8:16:32:64-S128" 3387 : "e-m:e-" "i64:64-f80:128-n8:16:32:64-S128"; 3388 3389 // Use fpret only for long double. 3390 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3391 3392 // Use fp2ret for _Complex long double. 3393 ComplexLongDoubleUsesFP2Ret = true; 3394 3395 // x86-64 has atomics up to 16 bytes. 3396 MaxAtomicPromoteWidth = 128; 3397 MaxAtomicInlineWidth = 128; 3398 } 3399 BuiltinVaListKind getBuiltinVaListKind() const override { 3400 return TargetInfo::X86_64ABIBuiltinVaList; 3401 } 3402 3403 int getEHDataRegisterNumber(unsigned RegNo) const override { 3404 if (RegNo == 0) return 0; 3405 if (RegNo == 1) return 1; 3406 return -1; 3407 } 3408 3409 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3410 return (CC == CC_C || 3411 CC == CC_IntelOclBicc || 3412 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3413 } 3414 3415 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3416 return CC_C; 3417 } 3418 3419 // for x32 we need it here explicitly 3420 bool hasInt128Type() const override { return true; } 3421 }; 3422 } // end anonymous namespace 3423 3424 namespace { 3425 // x86-64 Windows target 3426 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3427 public: 3428 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3429 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3430 WCharType = UnsignedShort; 3431 LongWidth = LongAlign = 32; 3432 DoubleAlign = LongLongAlign = 64; 3433 IntMaxType = SignedLongLong; 3434 Int64Type = SignedLongLong; 3435 SizeType = UnsignedLongLong; 3436 PtrDiffType = SignedLongLong; 3437 IntPtrType = SignedLongLong; 3438 this->UserLabelPrefix = ""; 3439 } 3440 void getTargetDefines(const LangOptions &Opts, 3441 MacroBuilder &Builder) const override { 3442 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3443 Builder.defineMacro("_WIN64"); 3444 } 3445 BuiltinVaListKind getBuiltinVaListKind() const override { 3446 return TargetInfo::CharPtrBuiltinVaList; 3447 } 3448 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3449 return (CC == CC_C || 3450 CC == CC_IntelOclBicc || 3451 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3452 } 3453 }; 3454 } // end anonymous namespace 3455 3456 namespace { 3457 // x86-64 Windows Visual Studio target 3458 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3459 public: 3460 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3461 : WindowsX86_64TargetInfo(Triple) { 3462 LongDoubleWidth = LongDoubleAlign = 64; 3463 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3464 } 3465 void getTargetDefines(const LangOptions &Opts, 3466 MacroBuilder &Builder) const override { 3467 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3468 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3469 Builder.defineMacro("_M_X64"); 3470 Builder.defineMacro("_M_AMD64"); 3471 } 3472 }; 3473 } // end anonymous namespace 3474 3475 namespace { 3476 // x86-64 MinGW target 3477 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3478 public: 3479 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3480 : WindowsX86_64TargetInfo(Triple) {} 3481 void getTargetDefines(const LangOptions &Opts, 3482 MacroBuilder &Builder) const override { 3483 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3484 DefineStd(Builder, "WIN64", Opts); 3485 Builder.defineMacro("__MINGW64__"); 3486 addMinGWDefines(Opts, Builder); 3487 } 3488 }; 3489 } // end anonymous namespace 3490 3491 namespace { 3492 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3493 public: 3494 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3495 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3496 Int64Type = SignedLongLong; 3497 MaxVectorAlign = 256; 3498 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3499 llvm::Triple T = llvm::Triple(Triple); 3500 if (T.getOS() == llvm::Triple::IOS) 3501 UseSignedCharForObjCBool = false; 3502 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3503 } 3504 }; 3505 } // end anonymous namespace 3506 3507 namespace { 3508 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3509 public: 3510 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3511 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3512 IntMaxType = SignedLongLong; 3513 Int64Type = SignedLongLong; 3514 } 3515 }; 3516 } // end anonymous namespace 3517 3518 namespace { 3519 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3520 public: 3521 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3522 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3523 IntMaxType = SignedLongLong; 3524 Int64Type = SignedLongLong; 3525 } 3526 }; 3527 } 3528 3529 3530 namespace { 3531 class ARMTargetInfo : public TargetInfo { 3532 // Possible FPU choices. 3533 enum FPUMode { 3534 VFP2FPU = (1 << 0), 3535 VFP3FPU = (1 << 1), 3536 VFP4FPU = (1 << 2), 3537 NeonFPU = (1 << 3), 3538 FPARMV8 = (1 << 4) 3539 }; 3540 3541 // Possible HWDiv features. 3542 enum HWDivMode { 3543 HWDivThumb = (1 << 0), 3544 HWDivARM = (1 << 1) 3545 }; 3546 3547 static bool FPUModeIsVFP(FPUMode Mode) { 3548 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3549 } 3550 3551 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3552 static const char * const GCCRegNames[]; 3553 3554 std::string ABI, CPU; 3555 3556 enum { 3557 FP_Default, 3558 FP_VFP, 3559 FP_Neon 3560 } FPMath; 3561 3562 unsigned FPU : 5; 3563 3564 unsigned IsAAPCS : 1; 3565 unsigned IsThumb : 1; 3566 unsigned HWDiv : 2; 3567 3568 // Initialized via features. 3569 unsigned SoftFloat : 1; 3570 unsigned SoftFloatABI : 1; 3571 3572 unsigned CRC : 1; 3573 unsigned Crypto : 1; 3574 3575 static const Builtin::Info BuiltinInfo[]; 3576 3577 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3578 StringRef ArchName = T.getArchName(); 3579 if (T.getArch() == llvm::Triple::arm || 3580 T.getArch() == llvm::Triple::armeb) { 3581 StringRef VersionStr; 3582 if (ArchName.startswith("armv")) 3583 VersionStr = ArchName.substr(4, 1); 3584 else if (ArchName.startswith("armebv")) 3585 VersionStr = ArchName.substr(6, 1); 3586 else 3587 return false; 3588 unsigned Version; 3589 if (VersionStr.getAsInteger(10, Version)) 3590 return false; 3591 return Version >= 6; 3592 } 3593 assert(T.getArch() == llvm::Triple::thumb || 3594 T.getArch() == llvm::Triple::thumbeb); 3595 StringRef VersionStr; 3596 if (ArchName.startswith("thumbv")) 3597 VersionStr = ArchName.substr(6, 1); 3598 else if (ArchName.startswith("thumbebv")) 3599 VersionStr = ArchName.substr(8, 1); 3600 else 3601 return false; 3602 unsigned Version; 3603 if (VersionStr.getAsInteger(10, Version)) 3604 return false; 3605 return Version >= 7; 3606 } 3607 3608 void setABIAAPCS() { 3609 IsAAPCS = true; 3610 3611 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3612 const llvm::Triple &T = getTriple(); 3613 3614 // size_t is unsigned long on MachO-derived environments and NetBSD. 3615 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD) 3616 SizeType = UnsignedLong; 3617 else 3618 SizeType = UnsignedInt; 3619 3620 switch (T.getOS()) { 3621 case llvm::Triple::NetBSD: 3622 WCharType = SignedInt; 3623 break; 3624 case llvm::Triple::Win32: 3625 WCharType = UnsignedShort; 3626 break; 3627 case llvm::Triple::Linux: 3628 default: 3629 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3630 WCharType = UnsignedInt; 3631 break; 3632 } 3633 3634 UseBitFieldTypeAlignment = true; 3635 3636 ZeroLengthBitfieldBoundary = 0; 3637 3638 if (IsThumb) { 3639 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3640 // so set preferred for small types to 32. 3641 if (T.isOSBinFormatMachO()) { 3642 DescriptionString = BigEndian ? 3643 "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3644 "v128:64:128-a:0:32-n32-S64" : 3645 "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3646 "v128:64:128-a:0:32-n32-S64"; 3647 } else if (T.isOSWindows()) { 3648 // FIXME: this is invalid for WindowsCE 3649 assert(!BigEndian && "Windows on ARM does not support big endian"); 3650 DescriptionString = "e" 3651 "-m:e" 3652 "-p:32:32" 3653 "-i1:8:32-i8:8:32-i16:16:32-i64:64" 3654 "-v128:64:128" 3655 "-a:0:32" 3656 "-n32" 3657 "-S64"; 3658 } else { 3659 DescriptionString = BigEndian ? 3660 "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3661 "v128:64:128-a:0:32-n32-S64" : 3662 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3663 "v128:64:128-a:0:32-n32-S64"; 3664 } 3665 } else { 3666 if (T.isOSBinFormatMachO()) 3667 DescriptionString = BigEndian ? 3668 "E-m:o-p:32:32-i64:64-v128:64:128-n32-S64" : 3669 "e-m:o-p:32:32-i64:64-v128:64:128-n32-S64"; 3670 else 3671 DescriptionString = BigEndian ? 3672 "E-m:e-p:32:32-i64:64-v128:64:128-n32-S64" : 3673 "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"; 3674 } 3675 3676 // FIXME: Enumerated types are variable width in straight AAPCS. 3677 } 3678 3679 void setABIAPCS() { 3680 const llvm::Triple &T = getTriple(); 3681 3682 IsAAPCS = false; 3683 3684 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3685 3686 // size_t is unsigned int on FreeBSD. 3687 if (T.getOS() == llvm::Triple::FreeBSD) 3688 SizeType = UnsignedInt; 3689 else 3690 SizeType = UnsignedLong; 3691 3692 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3693 WCharType = SignedInt; 3694 3695 // Do not respect the alignment of bit-field types when laying out 3696 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3697 UseBitFieldTypeAlignment = false; 3698 3699 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3700 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3701 /// gcc. 3702 ZeroLengthBitfieldBoundary = 32; 3703 3704 if (IsThumb) { 3705 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3706 // so set preferred for small types to 32. 3707 if (T.isOSBinFormatMachO()) 3708 DescriptionString = BigEndian ? 3709 "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3710 "-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3711 "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3712 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3713 else 3714 DescriptionString = BigEndian ? 3715 "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3716 "-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3717 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3718 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3719 } else { 3720 if (T.isOSBinFormatMachO()) 3721 DescriptionString = BigEndian ? 3722 "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3723 "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3724 else 3725 DescriptionString = BigEndian ? 3726 "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3727 "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3728 } 3729 3730 // FIXME: Override "preferred align" for double and long long. 3731 } 3732 3733 public: 3734 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 3735 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3736 IsAAPCS(true) { 3737 BigEndian = IsBigEndian; 3738 3739 switch (getTriple().getOS()) { 3740 case llvm::Triple::NetBSD: 3741 PtrDiffType = SignedLong; 3742 break; 3743 default: 3744 PtrDiffType = SignedInt; 3745 break; 3746 } 3747 3748 // {} in inline assembly are neon specifiers, not assembly variant 3749 // specifiers. 3750 NoAsmVariants = true; 3751 3752 // FIXME: Should we just treat this as a feature? 3753 IsThumb = getTriple().getArchName().startswith("thumb"); 3754 3755 setABI("aapcs-linux"); 3756 3757 // ARM targets default to using the ARM C++ ABI. 3758 TheCXXABI.set(TargetCXXABI::GenericARM); 3759 3760 // ARM has atomics up to 8 bytes 3761 MaxAtomicPromoteWidth = 64; 3762 if (shouldUseInlineAtomic(getTriple())) 3763 MaxAtomicInlineWidth = 64; 3764 3765 // Do force alignment of members that follow zero length bitfields. If 3766 // the alignment of the zero-length bitfield is greater than the member 3767 // that follows it, `bar', `bar' will be aligned as the type of the 3768 // zero length bitfield. 3769 UseZeroLengthBitfieldAlignment = true; 3770 } 3771 StringRef getABI() const override { return ABI; } 3772 bool setABI(const std::string &Name) override { 3773 ABI = Name; 3774 3775 // The defaults (above) are for AAPCS, check if we need to change them. 3776 // 3777 // FIXME: We need support for -meabi... we could just mangle it into the 3778 // name. 3779 if (Name == "apcs-gnu") { 3780 setABIAPCS(); 3781 return true; 3782 } 3783 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 3784 setABIAAPCS(); 3785 return true; 3786 } 3787 return false; 3788 } 3789 3790 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 3791 if (IsAAPCS) 3792 Features["aapcs"] = true; 3793 else 3794 Features["apcs"] = true; 3795 3796 StringRef ArchName = getTriple().getArchName(); 3797 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3798 Features["vfp2"] = true; 3799 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3800 CPU == "cortex-a9-mp") { 3801 Features["vfp3"] = true; 3802 Features["neon"] = true; 3803 } 3804 else if (CPU == "cortex-a5") { 3805 Features["vfp4"] = true; 3806 Features["neon"] = true; 3807 } else if (CPU == "swift" || CPU == "cortex-a7" || 3808 CPU == "cortex-a12" || CPU == "cortex-a15" || 3809 CPU == "krait") { 3810 Features["vfp4"] = true; 3811 Features["neon"] = true; 3812 Features["hwdiv"] = true; 3813 Features["hwdiv-arm"] = true; 3814 } else if (CPU == "cyclone") { 3815 Features["v8fp"] = true; 3816 Features["neon"] = true; 3817 Features["hwdiv"] = true; 3818 Features["hwdiv-arm"] = true; 3819 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 3820 Features["fp-armv8"] = true; 3821 Features["neon"] = true; 3822 Features["hwdiv"] = true; 3823 Features["hwdiv-arm"] = true; 3824 Features["crc"] = true; 3825 Features["crypto"] = true; 3826 } else if (CPU == "cortex-r5" || 3827 // Enable the hwdiv extension for all v8a AArch32 cores by 3828 // default. 3829 ArchName == "armv8a" || ArchName == "armv8" || 3830 ArchName == "armebv8a" || ArchName == "armebv8" || 3831 ArchName == "thumbv8a" || ArchName == "thumbv8" || 3832 ArchName == "thumbebv8a" || ArchName == "thumbebv8") { 3833 Features["hwdiv"] = true; 3834 Features["hwdiv-arm"] = true; 3835 } else if (CPU == "cortex-m3" || CPU == "cortex-m4") { 3836 Features["hwdiv"] = true; 3837 } 3838 } 3839 3840 bool handleTargetFeatures(std::vector<std::string> &Features, 3841 DiagnosticsEngine &Diags) override { 3842 FPU = 0; 3843 CRC = 0; 3844 Crypto = 0; 3845 SoftFloat = SoftFloatABI = false; 3846 HWDiv = 0; 3847 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3848 if (Features[i] == "+soft-float") 3849 SoftFloat = true; 3850 else if (Features[i] == "+soft-float-abi") 3851 SoftFloatABI = true; 3852 else if (Features[i] == "+vfp2") 3853 FPU |= VFP2FPU; 3854 else if (Features[i] == "+vfp3") 3855 FPU |= VFP3FPU; 3856 else if (Features[i] == "+vfp4") 3857 FPU |= VFP4FPU; 3858 else if (Features[i] == "+fp-armv8") 3859 FPU |= FPARMV8; 3860 else if (Features[i] == "+neon") 3861 FPU |= NeonFPU; 3862 else if (Features[i] == "+hwdiv") 3863 HWDiv |= HWDivThumb; 3864 else if (Features[i] == "+hwdiv-arm") 3865 HWDiv |= HWDivARM; 3866 else if (Features[i] == "+crc") 3867 CRC = 1; 3868 else if (Features[i] == "+crypto") 3869 Crypto = 1; 3870 } 3871 3872 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 3873 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 3874 return false; 3875 } 3876 3877 if (FPMath == FP_Neon) 3878 Features.push_back("+neonfp"); 3879 else if (FPMath == FP_VFP) 3880 Features.push_back("-neonfp"); 3881 3882 // Remove front-end specific options which the backend handles differently. 3883 std::vector<std::string>::iterator it; 3884 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3885 if (it != Features.end()) 3886 Features.erase(it); 3887 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3888 if (it != Features.end()) 3889 Features.erase(it); 3890 return true; 3891 } 3892 3893 bool hasFeature(StringRef Feature) const override { 3894 return llvm::StringSwitch<bool>(Feature) 3895 .Case("arm", true) 3896 .Case("softfloat", SoftFloat) 3897 .Case("thumb", IsThumb) 3898 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 3899 .Case("hwdiv", HWDiv & HWDivThumb) 3900 .Case("hwdiv-arm", HWDiv & HWDivARM) 3901 .Default(false); 3902 } 3903 // FIXME: Should we actually have some table instead of these switches? 3904 static const char *getCPUDefineSuffix(StringRef Name) { 3905 return llvm::StringSwitch<const char*>(Name) 3906 .Cases("arm8", "arm810", "4") 3907 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3908 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3909 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3910 .Case("ep9312", "4T") 3911 .Cases("arm10tdmi", "arm1020t", "5T") 3912 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3913 .Case("arm926ej-s", "5TEJ") 3914 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3915 .Cases("xscale", "iwmmxt", "5TE") 3916 .Case("arm1136j-s", "6J") 3917 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3918 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3919 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3920 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A") 3921 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "7A") 3922 .Cases("cortex-r4", "cortex-r5", "7R") 3923 .Case("swift", "7S") 3924 .Case("cyclone", "8A") 3925 .Case("cortex-m3", "7M") 3926 .Case("cortex-m4", "7EM") 3927 .Case("cortex-m0", "6M") 3928 .Cases("cortex-a53", "cortex-a57", "8A") 3929 .Default(nullptr); 3930 } 3931 static const char *getCPUProfile(StringRef Name) { 3932 return llvm::StringSwitch<const char*>(Name) 3933 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 3934 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "A") 3935 .Cases("cortex-a53", "cortex-a57", "A") 3936 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 3937 .Cases("cortex-r4", "cortex-r5", "R") 3938 .Default(""); 3939 } 3940 bool setCPU(const std::string &Name) override { 3941 if (!getCPUDefineSuffix(Name)) 3942 return false; 3943 3944 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 3945 StringRef Profile = getCPUProfile(Name); 3946 if (Profile == "M" && MaxAtomicInlineWidth) { 3947 MaxAtomicPromoteWidth = 32; 3948 MaxAtomicInlineWidth = 32; 3949 } 3950 3951 CPU = Name; 3952 return true; 3953 } 3954 bool setFPMath(StringRef Name) override; 3955 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 3956 unsigned CPUArchVer) const { 3957 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 3958 (CPUArch.find('M') != StringRef::npos); 3959 } 3960 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 3961 unsigned CPUArchVer) const { 3962 // We check both CPUArchVer and ArchName because when only triple is 3963 // specified, the default CPU is arm1136j-s. 3964 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 3965 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 3966 } 3967 void getTargetDefines(const LangOptions &Opts, 3968 MacroBuilder &Builder) const override { 3969 // Target identification. 3970 Builder.defineMacro("__arm"); 3971 Builder.defineMacro("__arm__"); 3972 3973 // Target properties. 3974 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3975 3976 StringRef CPUArch = getCPUDefineSuffix(CPU); 3977 unsigned int CPUArchVer; 3978 if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) { 3979 llvm_unreachable("Invalid char for architecture version number"); 3980 } 3981 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 3982 3983 // ACLE 6.4.1 ARM/Thumb instruction set architecture 3984 StringRef CPUProfile = getCPUProfile(CPU); 3985 StringRef ArchName = getTriple().getArchName(); 3986 3987 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 3988 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 3989 3990 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 3991 // is not defined for the M-profile. 3992 // NOTE that the deffault profile is assumed to be 'A' 3993 if (CPUProfile.empty() || CPUProfile != "M") 3994 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 3995 3996 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 3997 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 3998 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 3999 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4000 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4001 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 4002 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4003 4004 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4005 // instruction set such as ARM or Thumb. 4006 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4007 4008 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4009 4010 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4011 if (!CPUProfile.empty()) 4012 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4013 4014 // ACLE predefines. 4015 Builder.defineMacro("__ARM_ACLE", "200"); 4016 4017 // Subtarget options. 4018 4019 // FIXME: It's more complicated than this and we don't really support 4020 // interworking. 4021 // Windows on ARM does not "support" interworking 4022 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 4023 Builder.defineMacro("__THUMB_INTERWORK__"); 4024 4025 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4026 // Embedded targets on Darwin follow AAPCS, but not EABI. 4027 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4028 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4029 Builder.defineMacro("__ARM_EABI__"); 4030 Builder.defineMacro("__ARM_PCS", "1"); 4031 4032 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4033 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4034 } 4035 4036 if (SoftFloat) 4037 Builder.defineMacro("__SOFTFP__"); 4038 4039 if (CPU == "xscale") 4040 Builder.defineMacro("__XSCALE__"); 4041 4042 if (IsThumb) { 4043 Builder.defineMacro("__THUMBEL__"); 4044 Builder.defineMacro("__thumb__"); 4045 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4046 Builder.defineMacro("__thumb2__"); 4047 } 4048 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4049 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4050 4051 // Note, this is always on in gcc, even though it doesn't make sense. 4052 Builder.defineMacro("__APCS_32__"); 4053 4054 if (FPUModeIsVFP((FPUMode) FPU)) { 4055 Builder.defineMacro("__VFP_FP__"); 4056 if (FPU & VFP2FPU) 4057 Builder.defineMacro("__ARM_VFPV2__"); 4058 if (FPU & VFP3FPU) 4059 Builder.defineMacro("__ARM_VFPV3__"); 4060 if (FPU & VFP4FPU) 4061 Builder.defineMacro("__ARM_VFPV4__"); 4062 } 4063 4064 // This only gets set when Neon instructions are actually available, unlike 4065 // the VFP define, hence the soft float and arch check. This is subtly 4066 // different from gcc, we follow the intent which was that it should be set 4067 // when Neon instructions are actually available. 4068 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4069 Builder.defineMacro("__ARM_NEON"); 4070 Builder.defineMacro("__ARM_NEON__"); 4071 } 4072 4073 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4074 Opts.ShortWChar ? "2" : "4"); 4075 4076 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4077 Opts.ShortEnums ? "1" : "4"); 4078 4079 if (CRC) 4080 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4081 4082 if (Crypto) 4083 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4084 4085 if (CPUArchVer >= 6 && CPUArch != "6M") { 4086 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4087 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4088 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4089 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4090 } 4091 } 4092 void getTargetBuiltins(const Builtin::Info *&Records, 4093 unsigned &NumRecords) const override { 4094 Records = BuiltinInfo; 4095 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4096 } 4097 bool isCLZForZeroUndef() const override { return false; } 4098 BuiltinVaListKind getBuiltinVaListKind() const override { 4099 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4100 } 4101 void getGCCRegNames(const char * const *&Names, 4102 unsigned &NumNames) const override; 4103 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4104 unsigned &NumAliases) const override; 4105 bool validateAsmConstraint(const char *&Name, 4106 TargetInfo::ConstraintInfo &Info) const override { 4107 switch (*Name) { 4108 default: break; 4109 case 'l': // r0-r7 4110 case 'h': // r8-r15 4111 case 'w': // VFP Floating point register single precision 4112 case 'P': // VFP Floating point register double precision 4113 Info.setAllowsRegister(); 4114 return true; 4115 case 'Q': // A memory address that is a single base register. 4116 Info.setAllowsMemory(); 4117 return true; 4118 case 'U': // a memory reference... 4119 switch (Name[1]) { 4120 case 'q': // ...ARMV4 ldrsb 4121 case 'v': // ...VFP load/store (reg+constant offset) 4122 case 'y': // ...iWMMXt load/store 4123 case 't': // address valid for load/store opaque types wider 4124 // than 128-bits 4125 case 'n': // valid address for Neon doubleword vector load/store 4126 case 'm': // valid address for Neon element and structure load/store 4127 case 's': // valid address for non-offset loads/stores of quad-word 4128 // values in four ARM registers 4129 Info.setAllowsMemory(); 4130 Name++; 4131 return true; 4132 } 4133 } 4134 return false; 4135 } 4136 std::string convertConstraint(const char *&Constraint) const override { 4137 std::string R; 4138 switch (*Constraint) { 4139 case 'U': // Two-character constraint; add "^" hint for later parsing. 4140 R = std::string("^") + std::string(Constraint, 2); 4141 Constraint++; 4142 break; 4143 case 'p': // 'p' should be translated to 'r' by default. 4144 R = std::string("r"); 4145 break; 4146 default: 4147 return std::string(1, *Constraint); 4148 } 4149 return R; 4150 } 4151 bool validateConstraintModifier(StringRef Constraint, const char Modifier, 4152 unsigned Size) const override { 4153 bool isOutput = (Constraint[0] == '='); 4154 bool isInOut = (Constraint[0] == '+'); 4155 4156 // Strip off constraint modifiers. 4157 while (Constraint[0] == '=' || 4158 Constraint[0] == '+' || 4159 Constraint[0] == '&') 4160 Constraint = Constraint.substr(1); 4161 4162 switch (Constraint[0]) { 4163 default: break; 4164 case 'r': { 4165 switch (Modifier) { 4166 default: 4167 return (isInOut || isOutput || Size <= 64); 4168 case 'q': 4169 // A register of size 32 cannot fit a vector type. 4170 return false; 4171 } 4172 } 4173 } 4174 4175 return true; 4176 } 4177 const char *getClobbers() const override { 4178 // FIXME: Is this really right? 4179 return ""; 4180 } 4181 4182 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4183 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4184 } 4185 4186 int getEHDataRegisterNumber(unsigned RegNo) const override { 4187 if (RegNo == 0) return 0; 4188 if (RegNo == 1) return 1; 4189 return -1; 4190 } 4191 }; 4192 4193 bool ARMTargetInfo::setFPMath(StringRef Name) { 4194 if (Name == "neon") { 4195 FPMath = FP_Neon; 4196 return true; 4197 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4198 Name == "vfp4") { 4199 FPMath = FP_VFP; 4200 return true; 4201 } 4202 return false; 4203 } 4204 4205 const char * const ARMTargetInfo::GCCRegNames[] = { 4206 // Integer registers 4207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4208 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4209 4210 // Float registers 4211 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4212 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4213 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4214 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4215 4216 // Double registers 4217 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4218 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4219 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4220 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4221 4222 // Quad registers 4223 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4224 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4225 }; 4226 4227 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4228 unsigned &NumNames) const { 4229 Names = GCCRegNames; 4230 NumNames = llvm::array_lengthof(GCCRegNames); 4231 } 4232 4233 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4234 { { "a1" }, "r0" }, 4235 { { "a2" }, "r1" }, 4236 { { "a3" }, "r2" }, 4237 { { "a4" }, "r3" }, 4238 { { "v1" }, "r4" }, 4239 { { "v2" }, "r5" }, 4240 { { "v3" }, "r6" }, 4241 { { "v4" }, "r7" }, 4242 { { "v5" }, "r8" }, 4243 { { "v6", "rfp" }, "r9" }, 4244 { { "sl" }, "r10" }, 4245 { { "fp" }, "r11" }, 4246 { { "ip" }, "r12" }, 4247 { { "r13" }, "sp" }, 4248 { { "r14" }, "lr" }, 4249 { { "r15" }, "pc" }, 4250 // The S, D and Q registers overlap, but aren't really aliases; we 4251 // don't want to substitute one of these for a different-sized one. 4252 }; 4253 4254 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4255 unsigned &NumAliases) const { 4256 Aliases = GCCRegAliases; 4257 NumAliases = llvm::array_lengthof(GCCRegAliases); 4258 } 4259 4260 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4261 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4262 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4263 ALL_LANGUAGES }, 4264 #include "clang/Basic/BuiltinsNEON.def" 4265 4266 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4267 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG }, 4268 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4269 ALL_LANGUAGES }, 4270 #include "clang/Basic/BuiltinsARM.def" 4271 }; 4272 4273 class ARMleTargetInfo : public ARMTargetInfo { 4274 public: 4275 ARMleTargetInfo(const llvm::Triple &Triple) 4276 : ARMTargetInfo(Triple, false) { } 4277 virtual void getTargetDefines(const LangOptions &Opts, 4278 MacroBuilder &Builder) const { 4279 Builder.defineMacro("__ARMEL__"); 4280 ARMTargetInfo::getTargetDefines(Opts, Builder); 4281 } 4282 }; 4283 4284 class ARMbeTargetInfo : public ARMTargetInfo { 4285 public: 4286 ARMbeTargetInfo(const llvm::Triple &Triple) 4287 : ARMTargetInfo(Triple, true) { } 4288 virtual void getTargetDefines(const LangOptions &Opts, 4289 MacroBuilder &Builder) const { 4290 Builder.defineMacro("__ARMEB__"); 4291 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4292 ARMTargetInfo::getTargetDefines(Opts, Builder); 4293 } 4294 }; 4295 } // end anonymous namespace. 4296 4297 namespace { 4298 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4299 const llvm::Triple Triple; 4300 public: 4301 WindowsARMTargetInfo(const llvm::Triple &Triple) 4302 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4303 TLSSupported = false; 4304 WCharType = UnsignedShort; 4305 SizeType = UnsignedInt; 4306 UserLabelPrefix = ""; 4307 } 4308 void getVisualStudioDefines(const LangOptions &Opts, 4309 MacroBuilder &Builder) const { 4310 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4311 4312 // FIXME: this is invalid for WindowsCE 4313 Builder.defineMacro("_M_ARM_NT", "1"); 4314 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4315 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4316 4317 assert((Triple.getArch() == llvm::Triple::arm || 4318 Triple.getArch() == llvm::Triple::thumb) && 4319 "invalid architecture for Windows ARM target info"); 4320 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4321 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4322 4323 // TODO map the complete set of values 4324 // 31: VFPv3 40: VFPv4 4325 Builder.defineMacro("_M_ARM_FP", "31"); 4326 } 4327 BuiltinVaListKind getBuiltinVaListKind() const override { 4328 return TargetInfo::CharPtrBuiltinVaList; 4329 } 4330 }; 4331 4332 // Windows ARM + Itanium C++ ABI Target 4333 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4334 public: 4335 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4336 : WindowsARMTargetInfo(Triple) { 4337 TheCXXABI.set(TargetCXXABI::GenericARM); 4338 } 4339 4340 void getTargetDefines(const LangOptions &Opts, 4341 MacroBuilder &Builder) const override { 4342 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4343 4344 if (Opts.MSVCCompat) 4345 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4346 } 4347 }; 4348 4349 // Windows ARM, MS (C++) ABI 4350 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4351 public: 4352 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4353 : WindowsARMTargetInfo(Triple) { 4354 TheCXXABI.set(TargetCXXABI::Microsoft); 4355 } 4356 4357 void getTargetDefines(const LangOptions &Opts, 4358 MacroBuilder &Builder) const override { 4359 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4360 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4361 } 4362 }; 4363 } 4364 4365 4366 namespace { 4367 class DarwinARMTargetInfo : 4368 public DarwinTargetInfo<ARMleTargetInfo> { 4369 protected: 4370 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4371 MacroBuilder &Builder) const override { 4372 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4373 } 4374 4375 public: 4376 DarwinARMTargetInfo(const llvm::Triple &Triple) 4377 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4378 HasAlignMac68kSupport = true; 4379 // iOS always has 64-bit atomic instructions. 4380 // FIXME: This should be based off of the target features in ARMleTargetInfo. 4381 MaxAtomicInlineWidth = 64; 4382 4383 // Darwin on iOS uses a variant of the ARM C++ ABI. 4384 TheCXXABI.set(TargetCXXABI::iOS); 4385 } 4386 }; 4387 } // end anonymous namespace. 4388 4389 4390 namespace { 4391 class AArch64TargetInfo : public TargetInfo { 4392 virtual void setDescriptionString() = 0; 4393 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4394 static const char *const GCCRegNames[]; 4395 4396 enum FPUModeEnum { 4397 FPUMode, 4398 NeonMode 4399 }; 4400 4401 unsigned FPU; 4402 unsigned CRC; 4403 unsigned Crypto; 4404 4405 static const Builtin::Info BuiltinInfo[]; 4406 4407 std::string ABI; 4408 4409 public: 4410 AArch64TargetInfo(const llvm::Triple &Triple) 4411 : TargetInfo(Triple), ABI("aapcs") { 4412 4413 if (getTriple().getOS() == llvm::Triple::NetBSD) { 4414 WCharType = SignedInt; 4415 4416 // NetBSD apparently prefers consistency across ARM targets to consistency 4417 // across 64-bit targets. 4418 Int64Type = SignedLongLong; 4419 IntMaxType = SignedLongLong; 4420 } else { 4421 WCharType = UnsignedInt; 4422 Int64Type = SignedLong; 4423 IntMaxType = SignedLong; 4424 } 4425 4426 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4427 MaxVectorAlign = 128; 4428 RegParmMax = 8; 4429 MaxAtomicInlineWidth = 128; 4430 MaxAtomicPromoteWidth = 128; 4431 4432 LongDoubleWidth = LongDoubleAlign = 128; 4433 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4434 4435 // {} in inline assembly are neon specifiers, not assembly variant 4436 // specifiers. 4437 NoAsmVariants = true; 4438 4439 // AArch64 targets default to using the ARM C++ ABI. 4440 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4441 } 4442 4443 StringRef getABI() const override { return ABI; } 4444 virtual bool setABI(const std::string &Name) { 4445 if (Name != "aapcs" && Name != "darwinpcs") 4446 return false; 4447 4448 ABI = Name; 4449 return true; 4450 } 4451 4452 virtual bool setCPU(const std::string &Name) { 4453 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4454 .Case("generic", true) 4455 .Cases("cortex-a53", "cortex-a57", true) 4456 .Case("cyclone", true) 4457 .Default(false); 4458 return CPUKnown; 4459 } 4460 4461 virtual void getTargetDefines(const LangOptions &Opts, 4462 MacroBuilder &Builder) const { 4463 // Target identification. 4464 Builder.defineMacro("__aarch64__"); 4465 4466 // Target properties. 4467 Builder.defineMacro("_LP64"); 4468 Builder.defineMacro("__LP64__"); 4469 4470 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4471 Builder.defineMacro("__ARM_ACLE", "200"); 4472 Builder.defineMacro("__ARM_ARCH", "8"); 4473 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4474 4475 Builder.defineMacro("__ARM_64BIT_STATE"); 4476 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4477 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4478 4479 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4480 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4481 Builder.defineMacro("__ARM_FEATURE_FMA"); 4482 Builder.defineMacro("__ARM_FEATURE_DIV"); 4483 4484 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 4485 4486 // 0xe implies support for half, single and double precision operations. 4487 Builder.defineMacro("__ARM_FP", "0xe"); 4488 4489 // PCS specifies this for SysV variants, which is all we support. Other ABIs 4490 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 4491 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 4492 4493 if (Opts.FastMath || Opts.FiniteMathOnly) 4494 Builder.defineMacro("__ARM_FP_FAST"); 4495 4496 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 4497 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 4498 4499 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 4500 4501 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4502 Opts.ShortEnums ? "1" : "4"); 4503 4504 if (FPU == NeonMode) { 4505 Builder.defineMacro("__ARM_NEON"); 4506 // 64-bit NEON supports half, single and double precision operations. 4507 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 4508 } 4509 4510 if (CRC) 4511 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4512 4513 if (Crypto) 4514 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4515 } 4516 4517 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4518 unsigned &NumRecords) const { 4519 Records = BuiltinInfo; 4520 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 4521 } 4522 4523 virtual bool hasFeature(StringRef Feature) const { 4524 return Feature == "aarch64" || 4525 Feature == "arm64" || 4526 (Feature == "neon" && FPU == NeonMode); 4527 } 4528 4529 bool handleTargetFeatures(std::vector<std::string> &Features, 4530 DiagnosticsEngine &Diags) override { 4531 FPU = FPUMode; 4532 CRC = 0; 4533 Crypto = 0; 4534 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 4535 if (Features[i] == "+neon") 4536 FPU = NeonMode; 4537 if (Features[i] == "+crc") 4538 CRC = 1; 4539 if (Features[i] == "+crypto") 4540 Crypto = 1; 4541 } 4542 4543 setDescriptionString(); 4544 4545 return true; 4546 } 4547 4548 virtual bool isCLZForZeroUndef() const { return false; } 4549 4550 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4551 return TargetInfo::AArch64ABIBuiltinVaList; 4552 } 4553 4554 virtual void getGCCRegNames(const char *const *&Names, 4555 unsigned &NumNames) const; 4556 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4557 unsigned &NumAliases) const; 4558 4559 virtual bool validateAsmConstraint(const char *&Name, 4560 TargetInfo::ConstraintInfo &Info) const { 4561 switch (*Name) { 4562 default: 4563 return false; 4564 case 'w': // Floating point and SIMD registers (V0-V31) 4565 Info.setAllowsRegister(); 4566 return true; 4567 case 'I': // Constant that can be used with an ADD instruction 4568 case 'J': // Constant that can be used with a SUB instruction 4569 case 'K': // Constant that can be used with a 32-bit logical instruction 4570 case 'L': // Constant that can be used with a 64-bit logical instruction 4571 case 'M': // Constant that can be used as a 32-bit MOV immediate 4572 case 'N': // Constant that can be used as a 64-bit MOV immediate 4573 case 'Y': // Floating point constant zero 4574 case 'Z': // Integer constant zero 4575 return true; 4576 case 'Q': // A memory reference with base register and no offset 4577 Info.setAllowsMemory(); 4578 return true; 4579 case 'S': // A symbolic address 4580 Info.setAllowsRegister(); 4581 return true; 4582 case 'U': 4583 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 4584 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 4585 // Usa: An absolute symbolic address 4586 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 4587 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 4588 case 'z': // Zero register, wzr or xzr 4589 Info.setAllowsRegister(); 4590 return true; 4591 case 'x': // Floating point and SIMD registers (V0-V15) 4592 Info.setAllowsRegister(); 4593 return true; 4594 } 4595 return false; 4596 } 4597 4598 virtual bool validateConstraintModifier(StringRef Constraint, 4599 const char Modifier, 4600 unsigned Size) const { 4601 // Strip off constraint modifiers. 4602 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 4603 Constraint = Constraint.substr(1); 4604 4605 switch (Constraint[0]) { 4606 default: 4607 return true; 4608 case 'z': 4609 case 'r': { 4610 switch (Modifier) { 4611 case 'x': 4612 case 'w': 4613 // For now assume that the person knows what they're 4614 // doing with the modifier. 4615 return true; 4616 default: 4617 // By default an 'r' constraint will be in the 'x' 4618 // registers. 4619 return Size == 64; 4620 } 4621 } 4622 } 4623 } 4624 4625 virtual const char *getClobbers() const { return ""; } 4626 4627 int getEHDataRegisterNumber(unsigned RegNo) const { 4628 if (RegNo == 0) 4629 return 0; 4630 if (RegNo == 1) 4631 return 1; 4632 return -1; 4633 } 4634 }; 4635 4636 const char *const AArch64TargetInfo::GCCRegNames[] = { 4637 // 32-bit Integer registers 4638 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 4639 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 4640 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 4641 4642 // 64-bit Integer registers 4643 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 4644 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 4645 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 4646 4647 // 32-bit floating point regsisters 4648 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 4649 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 4650 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4651 4652 // 64-bit floating point regsisters 4653 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 4654 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 4655 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4656 4657 // Vector registers 4658 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 4659 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 4660 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 4661 }; 4662 4663 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 4664 unsigned &NumNames) const { 4665 Names = GCCRegNames; 4666 NumNames = llvm::array_lengthof(GCCRegNames); 4667 } 4668 4669 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 4670 { { "w31" }, "wsp" }, 4671 { { "x29" }, "fp" }, 4672 { { "x30" }, "lr" }, 4673 { { "x31" }, "sp" }, 4674 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 4675 // don't want to substitute one of these for a different-sized one. 4676 }; 4677 4678 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4679 unsigned &NumAliases) const { 4680 Aliases = GCCRegAliases; 4681 NumAliases = llvm::array_lengthof(GCCRegAliases); 4682 } 4683 4684 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 4685 #define BUILTIN(ID, TYPE, ATTRS) \ 4686 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4687 #include "clang/Basic/BuiltinsNEON.def" 4688 4689 #define BUILTIN(ID, TYPE, ATTRS) \ 4690 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4691 #include "clang/Basic/BuiltinsAArch64.def" 4692 }; 4693 4694 class AArch64leTargetInfo : public AArch64TargetInfo { 4695 void setDescriptionString() override { 4696 if (getTriple().isOSBinFormatMachO()) 4697 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 4698 else 4699 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 4700 } 4701 4702 public: 4703 AArch64leTargetInfo(const llvm::Triple &Triple) 4704 : AArch64TargetInfo(Triple) { 4705 BigEndian = false; 4706 } 4707 void getTargetDefines(const LangOptions &Opts, 4708 MacroBuilder &Builder) const override { 4709 Builder.defineMacro("__AARCH64EL__"); 4710 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4711 } 4712 }; 4713 4714 class AArch64beTargetInfo : public AArch64TargetInfo { 4715 void setDescriptionString() override { 4716 assert(!getTriple().isOSBinFormatMachO()); 4717 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 4718 } 4719 4720 public: 4721 AArch64beTargetInfo(const llvm::Triple &Triple) 4722 : AArch64TargetInfo(Triple) { } 4723 void getTargetDefines(const LangOptions &Opts, 4724 MacroBuilder &Builder) const override { 4725 Builder.defineMacro("__AARCH64EB__"); 4726 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 4727 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4728 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4729 } 4730 }; 4731 } // end anonymous namespace. 4732 4733 namespace { 4734 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 4735 protected: 4736 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4737 MacroBuilder &Builder) const override { 4738 Builder.defineMacro("__AARCH64_SIMD__"); 4739 Builder.defineMacro("__ARM64_ARCH_8__"); 4740 Builder.defineMacro("__ARM_NEON__"); 4741 Builder.defineMacro("__LITTLE_ENDIAN__"); 4742 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4743 Builder.defineMacro("__arm64", "1"); 4744 Builder.defineMacro("__arm64__", "1"); 4745 4746 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4747 } 4748 4749 public: 4750 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 4751 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 4752 Int64Type = SignedLongLong; 4753 WCharType = SignedInt; 4754 UseSignedCharForObjCBool = false; 4755 4756 LongDoubleWidth = LongDoubleAlign = 64; 4757 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4758 4759 TheCXXABI.set(TargetCXXABI::iOS64); 4760 } 4761 4762 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4763 return TargetInfo::CharPtrBuiltinVaList; 4764 } 4765 }; 4766 } // end anonymous namespace 4767 4768 namespace { 4769 // Hexagon abstract base class 4770 class HexagonTargetInfo : public TargetInfo { 4771 static const Builtin::Info BuiltinInfo[]; 4772 static const char * const GCCRegNames[]; 4773 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4774 std::string CPU; 4775 public: 4776 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4777 BigEndian = false; 4778 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 4779 4780 // {} in inline assembly are packet specifiers, not assembly variant 4781 // specifiers. 4782 NoAsmVariants = true; 4783 } 4784 4785 void getTargetBuiltins(const Builtin::Info *&Records, 4786 unsigned &NumRecords) const override { 4787 Records = BuiltinInfo; 4788 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4789 } 4790 4791 bool validateAsmConstraint(const char *&Name, 4792 TargetInfo::ConstraintInfo &Info) const override { 4793 return true; 4794 } 4795 4796 void getTargetDefines(const LangOptions &Opts, 4797 MacroBuilder &Builder) const override; 4798 4799 bool hasFeature(StringRef Feature) const override { 4800 return Feature == "hexagon"; 4801 } 4802 4803 BuiltinVaListKind getBuiltinVaListKind() const override { 4804 return TargetInfo::CharPtrBuiltinVaList; 4805 } 4806 void getGCCRegNames(const char * const *&Names, 4807 unsigned &NumNames) const override; 4808 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4809 unsigned &NumAliases) const override; 4810 const char *getClobbers() const override { 4811 return ""; 4812 } 4813 4814 static const char *getHexagonCPUSuffix(StringRef Name) { 4815 return llvm::StringSwitch<const char*>(Name) 4816 .Case("hexagonv4", "4") 4817 .Case("hexagonv5", "5") 4818 .Default(nullptr); 4819 } 4820 4821 bool setCPU(const std::string &Name) override { 4822 if (!getHexagonCPUSuffix(Name)) 4823 return false; 4824 4825 CPU = Name; 4826 return true; 4827 } 4828 }; 4829 4830 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4831 MacroBuilder &Builder) const { 4832 Builder.defineMacro("qdsp6"); 4833 Builder.defineMacro("__qdsp6", "1"); 4834 Builder.defineMacro("__qdsp6__", "1"); 4835 4836 Builder.defineMacro("hexagon"); 4837 Builder.defineMacro("__hexagon", "1"); 4838 Builder.defineMacro("__hexagon__", "1"); 4839 4840 if(CPU == "hexagonv1") { 4841 Builder.defineMacro("__HEXAGON_V1__"); 4842 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4843 if(Opts.HexagonQdsp6Compat) { 4844 Builder.defineMacro("__QDSP6_V1__"); 4845 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4846 } 4847 } 4848 else if(CPU == "hexagonv2") { 4849 Builder.defineMacro("__HEXAGON_V2__"); 4850 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4851 if(Opts.HexagonQdsp6Compat) { 4852 Builder.defineMacro("__QDSP6_V2__"); 4853 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4854 } 4855 } 4856 else if(CPU == "hexagonv3") { 4857 Builder.defineMacro("__HEXAGON_V3__"); 4858 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4859 if(Opts.HexagonQdsp6Compat) { 4860 Builder.defineMacro("__QDSP6_V3__"); 4861 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4862 } 4863 } 4864 else if(CPU == "hexagonv4") { 4865 Builder.defineMacro("__HEXAGON_V4__"); 4866 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4867 if(Opts.HexagonQdsp6Compat) { 4868 Builder.defineMacro("__QDSP6_V4__"); 4869 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4870 } 4871 } 4872 else if(CPU == "hexagonv5") { 4873 Builder.defineMacro("__HEXAGON_V5__"); 4874 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4875 if(Opts.HexagonQdsp6Compat) { 4876 Builder.defineMacro("__QDSP6_V5__"); 4877 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4878 } 4879 } 4880 } 4881 4882 const char * const HexagonTargetInfo::GCCRegNames[] = { 4883 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4884 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4885 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4886 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4887 "p0", "p1", "p2", "p3", 4888 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4889 }; 4890 4891 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4892 unsigned &NumNames) const { 4893 Names = GCCRegNames; 4894 NumNames = llvm::array_lengthof(GCCRegNames); 4895 } 4896 4897 4898 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4899 { { "sp" }, "r29" }, 4900 { { "fp" }, "r30" }, 4901 { { "lr" }, "r31" }, 4902 }; 4903 4904 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4905 unsigned &NumAliases) const { 4906 Aliases = GCCRegAliases; 4907 NumAliases = llvm::array_lengthof(GCCRegAliases); 4908 } 4909 4910 4911 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4912 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4913 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4914 ALL_LANGUAGES }, 4915 #include "clang/Basic/BuiltinsHexagon.def" 4916 }; 4917 } 4918 4919 4920 namespace { 4921 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4922 class SparcTargetInfo : public TargetInfo { 4923 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4924 static const char * const GCCRegNames[]; 4925 bool SoftFloat; 4926 public: 4927 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4928 4929 bool handleTargetFeatures(std::vector<std::string> &Features, 4930 DiagnosticsEngine &Diags) override { 4931 SoftFloat = false; 4932 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4933 if (Features[i] == "+soft-float") 4934 SoftFloat = true; 4935 return true; 4936 } 4937 void getTargetDefines(const LangOptions &Opts, 4938 MacroBuilder &Builder) const override { 4939 DefineStd(Builder, "sparc", Opts); 4940 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4941 4942 if (SoftFloat) 4943 Builder.defineMacro("SOFT_FLOAT", "1"); 4944 } 4945 4946 bool hasFeature(StringRef Feature) const override { 4947 return llvm::StringSwitch<bool>(Feature) 4948 .Case("softfloat", SoftFloat) 4949 .Case("sparc", true) 4950 .Default(false); 4951 } 4952 4953 void getTargetBuiltins(const Builtin::Info *&Records, 4954 unsigned &NumRecords) const override { 4955 // FIXME: Implement! 4956 } 4957 BuiltinVaListKind getBuiltinVaListKind() const override { 4958 return TargetInfo::VoidPtrBuiltinVaList; 4959 } 4960 void getGCCRegNames(const char * const *&Names, 4961 unsigned &NumNames) const override; 4962 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4963 unsigned &NumAliases) const override; 4964 bool validateAsmConstraint(const char *&Name, 4965 TargetInfo::ConstraintInfo &info) const override { 4966 // FIXME: Implement! 4967 return false; 4968 } 4969 const char *getClobbers() const override { 4970 // FIXME: Implement! 4971 return ""; 4972 } 4973 }; 4974 4975 const char * const SparcTargetInfo::GCCRegNames[] = { 4976 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4977 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4978 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4979 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4980 }; 4981 4982 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4983 unsigned &NumNames) const { 4984 Names = GCCRegNames; 4985 NumNames = llvm::array_lengthof(GCCRegNames); 4986 } 4987 4988 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4989 { { "g0" }, "r0" }, 4990 { { "g1" }, "r1" }, 4991 { { "g2" }, "r2" }, 4992 { { "g3" }, "r3" }, 4993 { { "g4" }, "r4" }, 4994 { { "g5" }, "r5" }, 4995 { { "g6" }, "r6" }, 4996 { { "g7" }, "r7" }, 4997 { { "o0" }, "r8" }, 4998 { { "o1" }, "r9" }, 4999 { { "o2" }, "r10" }, 5000 { { "o3" }, "r11" }, 5001 { { "o4" }, "r12" }, 5002 { { "o5" }, "r13" }, 5003 { { "o6", "sp" }, "r14" }, 5004 { { "o7" }, "r15" }, 5005 { { "l0" }, "r16" }, 5006 { { "l1" }, "r17" }, 5007 { { "l2" }, "r18" }, 5008 { { "l3" }, "r19" }, 5009 { { "l4" }, "r20" }, 5010 { { "l5" }, "r21" }, 5011 { { "l6" }, "r22" }, 5012 { { "l7" }, "r23" }, 5013 { { "i0" }, "r24" }, 5014 { { "i1" }, "r25" }, 5015 { { "i2" }, "r26" }, 5016 { { "i3" }, "r27" }, 5017 { { "i4" }, "r28" }, 5018 { { "i5" }, "r29" }, 5019 { { "i6", "fp" }, "r30" }, 5020 { { "i7" }, "r31" }, 5021 }; 5022 5023 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5024 unsigned &NumAliases) const { 5025 Aliases = GCCRegAliases; 5026 NumAliases = llvm::array_lengthof(GCCRegAliases); 5027 } 5028 5029 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5030 class SparcV8TargetInfo : public SparcTargetInfo { 5031 public: 5032 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5033 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5034 } 5035 5036 void getTargetDefines(const LangOptions &Opts, 5037 MacroBuilder &Builder) const override { 5038 SparcTargetInfo::getTargetDefines(Opts, Builder); 5039 Builder.defineMacro("__sparcv8"); 5040 } 5041 }; 5042 5043 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5044 class SparcV9TargetInfo : public SparcTargetInfo { 5045 public: 5046 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5047 // FIXME: Support Sparc quad-precision long double? 5048 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5049 // This is an LP64 platform. 5050 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5051 5052 // OpenBSD uses long long for int64_t and intmax_t. 5053 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5054 IntMaxType = SignedLongLong; 5055 else 5056 IntMaxType = SignedLong; 5057 Int64Type = IntMaxType; 5058 5059 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5060 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5061 LongDoubleWidth = 128; 5062 LongDoubleAlign = 128; 5063 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5064 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5065 } 5066 5067 void getTargetDefines(const LangOptions &Opts, 5068 MacroBuilder &Builder) const override { 5069 SparcTargetInfo::getTargetDefines(Opts, Builder); 5070 Builder.defineMacro("__sparcv9"); 5071 Builder.defineMacro("__arch64__"); 5072 // Solaris and its derivative AuroraUX don't need these variants, but the 5073 // BSDs do. 5074 if (getTriple().getOS() != llvm::Triple::Solaris && 5075 getTriple().getOS() != llvm::Triple::AuroraUX) { 5076 Builder.defineMacro("__sparc64__"); 5077 Builder.defineMacro("__sparc_v9__"); 5078 Builder.defineMacro("__sparcv9__"); 5079 } 5080 } 5081 5082 bool setCPU(const std::string &Name) override { 5083 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5084 .Case("v9", true) 5085 .Case("ultrasparc", true) 5086 .Case("ultrasparc3", true) 5087 .Case("niagara", true) 5088 .Case("niagara2", true) 5089 .Case("niagara3", true) 5090 .Case("niagara4", true) 5091 .Default(false); 5092 5093 // No need to store the CPU yet. There aren't any CPU-specific 5094 // macros to define. 5095 return CPUKnown; 5096 } 5097 }; 5098 5099 } // end anonymous namespace. 5100 5101 namespace { 5102 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 5103 public: 5104 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 5105 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 5106 SizeType = UnsignedInt; 5107 PtrDiffType = SignedInt; 5108 } 5109 }; 5110 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 5111 public: 5112 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 5113 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 5114 SizeType = UnsignedInt; 5115 PtrDiffType = SignedInt; 5116 } 5117 }; 5118 } // end anonymous namespace. 5119 5120 namespace { 5121 class SystemZTargetInfo : public TargetInfo { 5122 static const char *const GCCRegNames[]; 5123 5124 public: 5125 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5126 TLSSupported = true; 5127 IntWidth = IntAlign = 32; 5128 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5129 PointerWidth = PointerAlign = 64; 5130 LongDoubleWidth = 128; 5131 LongDoubleAlign = 64; 5132 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5133 MinGlobalAlign = 16; 5134 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5135 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5136 } 5137 void getTargetDefines(const LangOptions &Opts, 5138 MacroBuilder &Builder) const override { 5139 Builder.defineMacro("__s390__"); 5140 Builder.defineMacro("__s390x__"); 5141 Builder.defineMacro("__zarch__"); 5142 Builder.defineMacro("__LONG_DOUBLE_128__"); 5143 } 5144 void getTargetBuiltins(const Builtin::Info *&Records, 5145 unsigned &NumRecords) const override { 5146 // FIXME: Implement. 5147 Records = nullptr; 5148 NumRecords = 0; 5149 } 5150 5151 void getGCCRegNames(const char *const *&Names, 5152 unsigned &NumNames) const override; 5153 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5154 unsigned &NumAliases) const override { 5155 // No aliases. 5156 Aliases = nullptr; 5157 NumAliases = 0; 5158 } 5159 bool validateAsmConstraint(const char *&Name, 5160 TargetInfo::ConstraintInfo &info) const override; 5161 const char *getClobbers() const override { 5162 // FIXME: Is this really right? 5163 return ""; 5164 } 5165 BuiltinVaListKind getBuiltinVaListKind() const override { 5166 return TargetInfo::SystemZBuiltinVaList; 5167 } 5168 bool setCPU(const std::string &Name) override { 5169 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5170 .Case("z10", true) 5171 .Case("z196", true) 5172 .Case("zEC12", true) 5173 .Default(false); 5174 5175 // No need to store the CPU yet. There aren't any CPU-specific 5176 // macros to define. 5177 return CPUKnown; 5178 } 5179 }; 5180 5181 const char *const SystemZTargetInfo::GCCRegNames[] = { 5182 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5183 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5184 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5185 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5186 }; 5187 5188 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5189 unsigned &NumNames) const { 5190 Names = GCCRegNames; 5191 NumNames = llvm::array_lengthof(GCCRegNames); 5192 } 5193 5194 bool SystemZTargetInfo:: 5195 validateAsmConstraint(const char *&Name, 5196 TargetInfo::ConstraintInfo &Info) const { 5197 switch (*Name) { 5198 default: 5199 return false; 5200 5201 case 'a': // Address register 5202 case 'd': // Data register (equivalent to 'r') 5203 case 'f': // Floating-point register 5204 Info.setAllowsRegister(); 5205 return true; 5206 5207 case 'I': // Unsigned 8-bit constant 5208 case 'J': // Unsigned 12-bit constant 5209 case 'K': // Signed 16-bit constant 5210 case 'L': // Signed 20-bit displacement (on all targets we support) 5211 case 'M': // 0x7fffffff 5212 return true; 5213 5214 case 'Q': // Memory with base and unsigned 12-bit displacement 5215 case 'R': // Likewise, plus an index 5216 case 'S': // Memory with base and signed 20-bit displacement 5217 case 'T': // Likewise, plus an index 5218 Info.setAllowsMemory(); 5219 return true; 5220 } 5221 } 5222 } 5223 5224 namespace { 5225 class MSP430TargetInfo : public TargetInfo { 5226 static const char * const GCCRegNames[]; 5227 public: 5228 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5229 BigEndian = false; 5230 TLSSupported = false; 5231 IntWidth = 16; IntAlign = 16; 5232 LongWidth = 32; LongLongWidth = 64; 5233 LongAlign = LongLongAlign = 16; 5234 PointerWidth = 16; PointerAlign = 16; 5235 SuitableAlign = 16; 5236 SizeType = UnsignedInt; 5237 IntMaxType = SignedLongLong; 5238 IntPtrType = SignedInt; 5239 PtrDiffType = SignedInt; 5240 SigAtomicType = SignedLong; 5241 DescriptionString = "e-m:e-p:16:16-i32:16:32-n8:16"; 5242 } 5243 void getTargetDefines(const LangOptions &Opts, 5244 MacroBuilder &Builder) const override { 5245 Builder.defineMacro("MSP430"); 5246 Builder.defineMacro("__MSP430__"); 5247 // FIXME: defines for different 'flavours' of MCU 5248 } 5249 void getTargetBuiltins(const Builtin::Info *&Records, 5250 unsigned &NumRecords) const override { 5251 // FIXME: Implement. 5252 Records = nullptr; 5253 NumRecords = 0; 5254 } 5255 bool hasFeature(StringRef Feature) const override { 5256 return Feature == "msp430"; 5257 } 5258 void getGCCRegNames(const char * const *&Names, 5259 unsigned &NumNames) const override; 5260 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5261 unsigned &NumAliases) const override { 5262 // No aliases. 5263 Aliases = nullptr; 5264 NumAliases = 0; 5265 } 5266 bool validateAsmConstraint(const char *&Name, 5267 TargetInfo::ConstraintInfo &info) const override { 5268 // No target constraints for now. 5269 return false; 5270 } 5271 const char *getClobbers() const override { 5272 // FIXME: Is this really right? 5273 return ""; 5274 } 5275 BuiltinVaListKind getBuiltinVaListKind() const override { 5276 // FIXME: implement 5277 return TargetInfo::CharPtrBuiltinVaList; 5278 } 5279 }; 5280 5281 const char * const MSP430TargetInfo::GCCRegNames[] = { 5282 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5283 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5284 }; 5285 5286 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5287 unsigned &NumNames) const { 5288 Names = GCCRegNames; 5289 NumNames = llvm::array_lengthof(GCCRegNames); 5290 } 5291 } 5292 5293 namespace { 5294 5295 // LLVM and Clang cannot be used directly to output native binaries for 5296 // target, but is used to compile C code to llvm bitcode with correct 5297 // type and alignment information. 5298 // 5299 // TCE uses the llvm bitcode as input and uses it for generating customized 5300 // target processor and program binary. TCE co-design environment is 5301 // publicly available in http://tce.cs.tut.fi 5302 5303 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5304 3, // opencl_global 5305 4, // opencl_local 5306 5, // opencl_constant 5307 0, // cuda_device 5308 0, // cuda_constant 5309 0 // cuda_shared 5310 }; 5311 5312 class TCETargetInfo : public TargetInfo{ 5313 public: 5314 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5315 TLSSupported = false; 5316 IntWidth = 32; 5317 LongWidth = LongLongWidth = 32; 5318 PointerWidth = 32; 5319 IntAlign = 32; 5320 LongAlign = LongLongAlign = 32; 5321 PointerAlign = 32; 5322 SuitableAlign = 32; 5323 SizeType = UnsignedInt; 5324 IntMaxType = SignedLong; 5325 IntPtrType = SignedInt; 5326 PtrDiffType = SignedInt; 5327 FloatWidth = 32; 5328 FloatAlign = 32; 5329 DoubleWidth = 32; 5330 DoubleAlign = 32; 5331 LongDoubleWidth = 32; 5332 LongDoubleAlign = 32; 5333 FloatFormat = &llvm::APFloat::IEEEsingle; 5334 DoubleFormat = &llvm::APFloat::IEEEsingle; 5335 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5336 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5337 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5338 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5339 UseAddrSpaceMapMangling = true; 5340 } 5341 5342 void getTargetDefines(const LangOptions &Opts, 5343 MacroBuilder &Builder) const override { 5344 DefineStd(Builder, "tce", Opts); 5345 Builder.defineMacro("__TCE__"); 5346 Builder.defineMacro("__TCE_V1__"); 5347 } 5348 bool hasFeature(StringRef Feature) const override { 5349 return Feature == "tce"; 5350 } 5351 5352 void getTargetBuiltins(const Builtin::Info *&Records, 5353 unsigned &NumRecords) const override {} 5354 const char *getClobbers() const override { 5355 return ""; 5356 } 5357 BuiltinVaListKind getBuiltinVaListKind() const override { 5358 return TargetInfo::VoidPtrBuiltinVaList; 5359 } 5360 void getGCCRegNames(const char * const *&Names, 5361 unsigned &NumNames) const override {} 5362 bool validateAsmConstraint(const char *&Name, 5363 TargetInfo::ConstraintInfo &info) const override{ 5364 return true; 5365 } 5366 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5367 unsigned &NumAliases) const override {} 5368 }; 5369 } 5370 5371 namespace { 5372 class MipsTargetInfoBase : public TargetInfo { 5373 virtual void setDescriptionString() = 0; 5374 5375 static const Builtin::Info BuiltinInfo[]; 5376 std::string CPU; 5377 bool IsMips16; 5378 bool IsMicromips; 5379 bool IsNan2008; 5380 bool IsSingleFloat; 5381 enum MipsFloatABI { 5382 HardFloat, SoftFloat 5383 } FloatABI; 5384 enum DspRevEnum { 5385 NoDSP, DSP1, DSP2 5386 } DspRev; 5387 bool HasMSA; 5388 5389 protected: 5390 bool HasFP64; 5391 std::string ABI; 5392 5393 public: 5394 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5395 const std::string &CPUStr) 5396 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5397 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5398 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 5399 5400 bool isNaN2008Default() const { 5401 return CPU == "mips32r6" || CPU == "mips64r6"; 5402 } 5403 5404 bool isFP64Default() const { 5405 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 5406 } 5407 5408 StringRef getABI() const override { return ABI; } 5409 bool setCPU(const std::string &Name) override { 5410 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 5411 getTriple().getArch() == llvm::Triple::mipsel; 5412 CPU = Name; 5413 return llvm::StringSwitch<bool>(Name) 5414 .Case("mips1", IsMips32) 5415 .Case("mips2", IsMips32) 5416 .Case("mips3", true) 5417 .Case("mips4", true) 5418 .Case("mips5", true) 5419 .Case("mips32", IsMips32) 5420 .Case("mips32r2", IsMips32) 5421 .Case("mips32r6", IsMips32) 5422 .Case("mips64", true) 5423 .Case("mips64r2", true) 5424 .Case("mips64r6", true) 5425 .Case("octeon", true) 5426 .Default(false); 5427 } 5428 const std::string& getCPU() const { return CPU; } 5429 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5430 // The backend enables certain ABI's by default according to the 5431 // architecture. 5432 // Disable both possible defaults so that we don't end up with multiple 5433 // ABI's selected and trigger an assertion. 5434 Features["o32"] = false; 5435 Features["n64"] = false; 5436 5437 Features[ABI] = true; 5438 if (CPU == "octeon") 5439 Features["mips64r2"] = Features["cnmips"] = true; 5440 else 5441 Features[CPU] = true; 5442 } 5443 5444 void getTargetDefines(const LangOptions &Opts, 5445 MacroBuilder &Builder) const override { 5446 Builder.defineMacro("__mips__"); 5447 Builder.defineMacro("_mips"); 5448 if (Opts.GNUMode) 5449 Builder.defineMacro("mips"); 5450 5451 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5452 5453 switch (FloatABI) { 5454 case HardFloat: 5455 Builder.defineMacro("__mips_hard_float", Twine(1)); 5456 break; 5457 case SoftFloat: 5458 Builder.defineMacro("__mips_soft_float", Twine(1)); 5459 break; 5460 } 5461 5462 if (IsSingleFloat) 5463 Builder.defineMacro("__mips_single_float", Twine(1)); 5464 5465 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5466 Builder.defineMacro("_MIPS_FPSET", 5467 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5468 5469 if (IsMips16) 5470 Builder.defineMacro("__mips16", Twine(1)); 5471 5472 if (IsMicromips) 5473 Builder.defineMacro("__mips_micromips", Twine(1)); 5474 5475 if (IsNan2008) 5476 Builder.defineMacro("__mips_nan2008", Twine(1)); 5477 5478 switch (DspRev) { 5479 default: 5480 break; 5481 case DSP1: 5482 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5483 Builder.defineMacro("__mips_dsp", Twine(1)); 5484 break; 5485 case DSP2: 5486 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5487 Builder.defineMacro("__mips_dspr2", Twine(1)); 5488 Builder.defineMacro("__mips_dsp", Twine(1)); 5489 break; 5490 } 5491 5492 if (HasMSA) 5493 Builder.defineMacro("__mips_msa", Twine(1)); 5494 5495 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5496 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5497 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5498 5499 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5500 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5501 } 5502 5503 void getTargetBuiltins(const Builtin::Info *&Records, 5504 unsigned &NumRecords) const override { 5505 Records = BuiltinInfo; 5506 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5507 } 5508 bool hasFeature(StringRef Feature) const override { 5509 return llvm::StringSwitch<bool>(Feature) 5510 .Case("mips", true) 5511 .Case("fp64", HasFP64) 5512 .Default(false); 5513 } 5514 BuiltinVaListKind getBuiltinVaListKind() const override { 5515 return TargetInfo::VoidPtrBuiltinVaList; 5516 } 5517 void getGCCRegNames(const char * const *&Names, 5518 unsigned &NumNames) const override { 5519 static const char *const GCCRegNames[] = { 5520 // CPU register names 5521 // Must match second column of GCCRegAliases 5522 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5523 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5524 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5525 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5526 // Floating point register names 5527 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5528 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5529 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5530 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5531 // Hi/lo and condition register names 5532 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5533 "$fcc5","$fcc6","$fcc7", 5534 // MSA register names 5535 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5536 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5537 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5538 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5539 // MSA control register names 5540 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5541 "$msarequest", "$msamap", "$msaunmap" 5542 }; 5543 Names = GCCRegNames; 5544 NumNames = llvm::array_lengthof(GCCRegNames); 5545 } 5546 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5547 unsigned &NumAliases) const override = 0; 5548 bool validateAsmConstraint(const char *&Name, 5549 TargetInfo::ConstraintInfo &Info) const override { 5550 switch (*Name) { 5551 default: 5552 return false; 5553 5554 case 'r': // CPU registers. 5555 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5556 case 'y': // Equivalent to "r", backward compatibility only. 5557 case 'f': // floating-point registers. 5558 case 'c': // $25 for indirect jumps 5559 case 'l': // lo register 5560 case 'x': // hilo register pair 5561 Info.setAllowsRegister(); 5562 return true; 5563 case 'R': // An address that can be used in a non-macro load or store 5564 Info.setAllowsMemory(); 5565 return true; 5566 } 5567 } 5568 5569 const char *getClobbers() const override { 5570 // FIXME: Implement! 5571 return ""; 5572 } 5573 5574 bool handleTargetFeatures(std::vector<std::string> &Features, 5575 DiagnosticsEngine &Diags) override { 5576 IsMips16 = false; 5577 IsMicromips = false; 5578 IsNan2008 = isNaN2008Default(); 5579 IsSingleFloat = false; 5580 FloatABI = HardFloat; 5581 DspRev = NoDSP; 5582 HasFP64 = isFP64Default(); 5583 5584 for (std::vector<std::string>::iterator it = Features.begin(), 5585 ie = Features.end(); it != ie; ++it) { 5586 if (*it == "+single-float") 5587 IsSingleFloat = true; 5588 else if (*it == "+soft-float") 5589 FloatABI = SoftFloat; 5590 else if (*it == "+mips16") 5591 IsMips16 = true; 5592 else if (*it == "+micromips") 5593 IsMicromips = true; 5594 else if (*it == "+dsp") 5595 DspRev = std::max(DspRev, DSP1); 5596 else if (*it == "+dspr2") 5597 DspRev = std::max(DspRev, DSP2); 5598 else if (*it == "+msa") 5599 HasMSA = true; 5600 else if (*it == "+fp64") 5601 HasFP64 = true; 5602 else if (*it == "-fp64") 5603 HasFP64 = false; 5604 else if (*it == "+nan2008") 5605 IsNan2008 = true; 5606 else if (*it == "-nan2008") 5607 IsNan2008 = false; 5608 } 5609 5610 // Remove front-end specific options. 5611 std::vector<std::string>::iterator it = 5612 std::find(Features.begin(), Features.end(), "+soft-float"); 5613 if (it != Features.end()) 5614 Features.erase(it); 5615 5616 setDescriptionString(); 5617 5618 return true; 5619 } 5620 5621 int getEHDataRegisterNumber(unsigned RegNo) const override { 5622 if (RegNo == 0) return 4; 5623 if (RegNo == 1) return 5; 5624 return -1; 5625 } 5626 5627 bool isCLZForZeroUndef() const override { return false; } 5628 }; 5629 5630 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5631 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5632 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5633 ALL_LANGUAGES }, 5634 #include "clang/Basic/BuiltinsMips.def" 5635 }; 5636 5637 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5638 public: 5639 Mips32TargetInfoBase(const llvm::Triple &Triple) 5640 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 5641 SizeType = UnsignedInt; 5642 PtrDiffType = SignedInt; 5643 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5644 } 5645 bool setABI(const std::string &Name) override { 5646 if (Name == "o32" || Name == "eabi") { 5647 ABI = Name; 5648 return true; 5649 } 5650 return false; 5651 } 5652 void getTargetDefines(const LangOptions &Opts, 5653 MacroBuilder &Builder) const override { 5654 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5655 5656 Builder.defineMacro("__mips", "32"); 5657 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 5658 5659 const std::string& CPUStr = getCPU(); 5660 if (CPUStr == "mips32") 5661 Builder.defineMacro("__mips_isa_rev", "1"); 5662 else if (CPUStr == "mips32r2") 5663 Builder.defineMacro("__mips_isa_rev", "2"); 5664 5665 if (ABI == "o32") { 5666 Builder.defineMacro("__mips_o32"); 5667 Builder.defineMacro("_ABIO32", "1"); 5668 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5669 } 5670 else if (ABI == "eabi") 5671 Builder.defineMacro("__mips_eabi"); 5672 else 5673 llvm_unreachable("Invalid ABI for Mips32."); 5674 } 5675 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5676 unsigned &NumAliases) const override { 5677 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5678 { { "at" }, "$1" }, 5679 { { "v0" }, "$2" }, 5680 { { "v1" }, "$3" }, 5681 { { "a0" }, "$4" }, 5682 { { "a1" }, "$5" }, 5683 { { "a2" }, "$6" }, 5684 { { "a3" }, "$7" }, 5685 { { "t0" }, "$8" }, 5686 { { "t1" }, "$9" }, 5687 { { "t2" }, "$10" }, 5688 { { "t3" }, "$11" }, 5689 { { "t4" }, "$12" }, 5690 { { "t5" }, "$13" }, 5691 { { "t6" }, "$14" }, 5692 { { "t7" }, "$15" }, 5693 { { "s0" }, "$16" }, 5694 { { "s1" }, "$17" }, 5695 { { "s2" }, "$18" }, 5696 { { "s3" }, "$19" }, 5697 { { "s4" }, "$20" }, 5698 { { "s5" }, "$21" }, 5699 { { "s6" }, "$22" }, 5700 { { "s7" }, "$23" }, 5701 { { "t8" }, "$24" }, 5702 { { "t9" }, "$25" }, 5703 { { "k0" }, "$26" }, 5704 { { "k1" }, "$27" }, 5705 { { "gp" }, "$28" }, 5706 { { "sp","$sp" }, "$29" }, 5707 { { "fp","$fp" }, "$30" }, 5708 { { "ra" }, "$31" } 5709 }; 5710 Aliases = GCCRegAliases; 5711 NumAliases = llvm::array_lengthof(GCCRegAliases); 5712 } 5713 }; 5714 5715 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5716 void setDescriptionString() override { 5717 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5718 } 5719 5720 public: 5721 Mips32EBTargetInfo(const llvm::Triple &Triple) 5722 : Mips32TargetInfoBase(Triple) { 5723 } 5724 void getTargetDefines(const LangOptions &Opts, 5725 MacroBuilder &Builder) const override { 5726 DefineStd(Builder, "MIPSEB", Opts); 5727 Builder.defineMacro("_MIPSEB"); 5728 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5729 } 5730 }; 5731 5732 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5733 void setDescriptionString() override { 5734 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5735 } 5736 5737 public: 5738 Mips32ELTargetInfo(const llvm::Triple &Triple) 5739 : Mips32TargetInfoBase(Triple) { 5740 BigEndian = false; 5741 } 5742 void getTargetDefines(const LangOptions &Opts, 5743 MacroBuilder &Builder) const override { 5744 DefineStd(Builder, "MIPSEL", Opts); 5745 Builder.defineMacro("_MIPSEL"); 5746 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5747 } 5748 }; 5749 5750 class Mips64TargetInfoBase : public MipsTargetInfoBase { 5751 public: 5752 Mips64TargetInfoBase(const llvm::Triple &Triple) 5753 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 5754 LongDoubleWidth = LongDoubleAlign = 128; 5755 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5756 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5757 LongDoubleWidth = LongDoubleAlign = 64; 5758 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5759 } 5760 setN64ABITypes(); 5761 SuitableAlign = 128; 5762 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5763 } 5764 5765 void setN64ABITypes() { 5766 LongWidth = LongAlign = 64; 5767 PointerWidth = PointerAlign = 64; 5768 SizeType = UnsignedLong; 5769 PtrDiffType = SignedLong; 5770 } 5771 5772 void setN32ABITypes() { 5773 LongWidth = LongAlign = 32; 5774 PointerWidth = PointerAlign = 32; 5775 SizeType = UnsignedInt; 5776 PtrDiffType = SignedInt; 5777 } 5778 5779 bool setABI(const std::string &Name) override { 5780 if (Name == "n32") { 5781 setN32ABITypes(); 5782 ABI = Name; 5783 return true; 5784 } 5785 if (Name == "n64") { 5786 setN64ABITypes(); 5787 ABI = Name; 5788 return true; 5789 } 5790 return false; 5791 } 5792 5793 void getTargetDefines(const LangOptions &Opts, 5794 MacroBuilder &Builder) const override { 5795 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5796 5797 Builder.defineMacro("__mips", "64"); 5798 Builder.defineMacro("__mips64"); 5799 Builder.defineMacro("__mips64__"); 5800 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 5801 5802 const std::string& CPUStr = getCPU(); 5803 if (CPUStr == "mips64") 5804 Builder.defineMacro("__mips_isa_rev", "1"); 5805 else if (CPUStr == "mips64r2") 5806 Builder.defineMacro("__mips_isa_rev", "2"); 5807 5808 if (ABI == "n32") { 5809 Builder.defineMacro("__mips_n32"); 5810 Builder.defineMacro("_ABIN32", "2"); 5811 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5812 } 5813 else if (ABI == "n64") { 5814 Builder.defineMacro("__mips_n64"); 5815 Builder.defineMacro("_ABI64", "3"); 5816 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5817 } 5818 else 5819 llvm_unreachable("Invalid ABI for Mips64."); 5820 } 5821 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5822 unsigned &NumAliases) const override { 5823 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5824 { { "at" }, "$1" }, 5825 { { "v0" }, "$2" }, 5826 { { "v1" }, "$3" }, 5827 { { "a0" }, "$4" }, 5828 { { "a1" }, "$5" }, 5829 { { "a2" }, "$6" }, 5830 { { "a3" }, "$7" }, 5831 { { "a4" }, "$8" }, 5832 { { "a5" }, "$9" }, 5833 { { "a6" }, "$10" }, 5834 { { "a7" }, "$11" }, 5835 { { "t0" }, "$12" }, 5836 { { "t1" }, "$13" }, 5837 { { "t2" }, "$14" }, 5838 { { "t3" }, "$15" }, 5839 { { "s0" }, "$16" }, 5840 { { "s1" }, "$17" }, 5841 { { "s2" }, "$18" }, 5842 { { "s3" }, "$19" }, 5843 { { "s4" }, "$20" }, 5844 { { "s5" }, "$21" }, 5845 { { "s6" }, "$22" }, 5846 { { "s7" }, "$23" }, 5847 { { "t8" }, "$24" }, 5848 { { "t9" }, "$25" }, 5849 { { "k0" }, "$26" }, 5850 { { "k1" }, "$27" }, 5851 { { "gp" }, "$28" }, 5852 { { "sp","$sp" }, "$29" }, 5853 { { "fp","$fp" }, "$30" }, 5854 { { "ra" }, "$31" } 5855 }; 5856 Aliases = GCCRegAliases; 5857 NumAliases = llvm::array_lengthof(GCCRegAliases); 5858 } 5859 5860 bool hasInt128Type() const override { return true; } 5861 }; 5862 5863 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5864 void setDescriptionString() override { 5865 if (ABI == "n32") 5866 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5867 else 5868 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5869 5870 } 5871 5872 public: 5873 Mips64EBTargetInfo(const llvm::Triple &Triple) 5874 : Mips64TargetInfoBase(Triple) {} 5875 void getTargetDefines(const LangOptions &Opts, 5876 MacroBuilder &Builder) const override { 5877 DefineStd(Builder, "MIPSEB", Opts); 5878 Builder.defineMacro("_MIPSEB"); 5879 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5880 } 5881 }; 5882 5883 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5884 void setDescriptionString() override { 5885 if (ABI == "n32") 5886 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5887 else 5888 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5889 } 5890 public: 5891 Mips64ELTargetInfo(const llvm::Triple &Triple) 5892 : Mips64TargetInfoBase(Triple) { 5893 // Default ABI is n64. 5894 BigEndian = false; 5895 } 5896 void getTargetDefines(const LangOptions &Opts, 5897 MacroBuilder &Builder) const override { 5898 DefineStd(Builder, "MIPSEL", Opts); 5899 Builder.defineMacro("_MIPSEL"); 5900 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5901 } 5902 }; 5903 } // end anonymous namespace. 5904 5905 namespace { 5906 class PNaClTargetInfo : public TargetInfo { 5907 public: 5908 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5909 BigEndian = false; 5910 this->UserLabelPrefix = ""; 5911 this->LongAlign = 32; 5912 this->LongWidth = 32; 5913 this->PointerAlign = 32; 5914 this->PointerWidth = 32; 5915 this->IntMaxType = TargetInfo::SignedLongLong; 5916 this->Int64Type = TargetInfo::SignedLongLong; 5917 this->DoubleAlign = 64; 5918 this->LongDoubleWidth = 64; 5919 this->LongDoubleAlign = 64; 5920 this->SizeType = TargetInfo::UnsignedInt; 5921 this->PtrDiffType = TargetInfo::SignedInt; 5922 this->IntPtrType = TargetInfo::SignedInt; 5923 this->RegParmMax = 0; // Disallow regparm 5924 } 5925 5926 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5927 } 5928 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 5929 Builder.defineMacro("__le32__"); 5930 Builder.defineMacro("__pnacl__"); 5931 } 5932 void getTargetDefines(const LangOptions &Opts, 5933 MacroBuilder &Builder) const override { 5934 getArchDefines(Opts, Builder); 5935 } 5936 bool hasFeature(StringRef Feature) const override { 5937 return Feature == "pnacl"; 5938 } 5939 void getTargetBuiltins(const Builtin::Info *&Records, 5940 unsigned &NumRecords) const override { 5941 } 5942 BuiltinVaListKind getBuiltinVaListKind() const override { 5943 return TargetInfo::PNaClABIBuiltinVaList; 5944 } 5945 void getGCCRegNames(const char * const *&Names, 5946 unsigned &NumNames) const override; 5947 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5948 unsigned &NumAliases) const override; 5949 bool validateAsmConstraint(const char *&Name, 5950 TargetInfo::ConstraintInfo &Info) const override { 5951 return false; 5952 } 5953 5954 const char *getClobbers() const override { 5955 return ""; 5956 } 5957 }; 5958 5959 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5960 unsigned &NumNames) const { 5961 Names = nullptr; 5962 NumNames = 0; 5963 } 5964 5965 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5966 unsigned &NumAliases) const { 5967 Aliases = nullptr; 5968 NumAliases = 0; 5969 } 5970 } // end anonymous namespace. 5971 5972 namespace { 5973 static const unsigned SPIRAddrSpaceMap[] = { 5974 1, // opencl_global 5975 3, // opencl_local 5976 2, // opencl_constant 5977 0, // cuda_device 5978 0, // cuda_constant 5979 0 // cuda_shared 5980 }; 5981 class SPIRTargetInfo : public TargetInfo { 5982 public: 5983 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5984 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5985 "SPIR target must use unknown OS"); 5986 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5987 "SPIR target must use unknown environment type"); 5988 BigEndian = false; 5989 TLSSupported = false; 5990 LongWidth = LongAlign = 64; 5991 AddrSpaceMap = &SPIRAddrSpaceMap; 5992 UseAddrSpaceMapMangling = true; 5993 // Define available target features 5994 // These must be defined in sorted order! 5995 NoAsmVariants = true; 5996 } 5997 void getTargetDefines(const LangOptions &Opts, 5998 MacroBuilder &Builder) const override { 5999 DefineStd(Builder, "SPIR", Opts); 6000 } 6001 bool hasFeature(StringRef Feature) const override { 6002 return Feature == "spir"; 6003 } 6004 6005 void getTargetBuiltins(const Builtin::Info *&Records, 6006 unsigned &NumRecords) const override {} 6007 const char *getClobbers() const override { 6008 return ""; 6009 } 6010 void getGCCRegNames(const char * const *&Names, 6011 unsigned &NumNames) const override {} 6012 bool validateAsmConstraint(const char *&Name, 6013 TargetInfo::ConstraintInfo &info) const override { 6014 return true; 6015 } 6016 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6017 unsigned &NumAliases) const override {} 6018 BuiltinVaListKind getBuiltinVaListKind() const override { 6019 return TargetInfo::VoidPtrBuiltinVaList; 6020 } 6021 }; 6022 6023 6024 class SPIR32TargetInfo : public SPIRTargetInfo { 6025 public: 6026 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6027 PointerWidth = PointerAlign = 32; 6028 SizeType = TargetInfo::UnsignedInt; 6029 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6030 DescriptionString 6031 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6032 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6033 } 6034 void getTargetDefines(const LangOptions &Opts, 6035 MacroBuilder &Builder) const override { 6036 DefineStd(Builder, "SPIR32", Opts); 6037 } 6038 }; 6039 6040 class SPIR64TargetInfo : public SPIRTargetInfo { 6041 public: 6042 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6043 PointerWidth = PointerAlign = 64; 6044 SizeType = TargetInfo::UnsignedLong; 6045 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6046 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6047 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6048 } 6049 void getTargetDefines(const LangOptions &Opts, 6050 MacroBuilder &Builder) const override { 6051 DefineStd(Builder, "SPIR64", Opts); 6052 } 6053 }; 6054 } 6055 6056 namespace { 6057 class XCoreTargetInfo : public TargetInfo { 6058 static const Builtin::Info BuiltinInfo[]; 6059 public: 6060 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6061 BigEndian = false; 6062 NoAsmVariants = true; 6063 LongLongAlign = 32; 6064 SuitableAlign = 32; 6065 DoubleAlign = LongDoubleAlign = 32; 6066 SizeType = UnsignedInt; 6067 PtrDiffType = SignedInt; 6068 IntPtrType = SignedInt; 6069 WCharType = UnsignedChar; 6070 WIntType = UnsignedInt; 6071 UseZeroLengthBitfieldAlignment = true; 6072 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6073 "-f64:32-a:0:32-n32"; 6074 } 6075 void getTargetDefines(const LangOptions &Opts, 6076 MacroBuilder &Builder) const override { 6077 Builder.defineMacro("__XS1B__"); 6078 } 6079 void getTargetBuiltins(const Builtin::Info *&Records, 6080 unsigned &NumRecords) const override { 6081 Records = BuiltinInfo; 6082 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6083 } 6084 BuiltinVaListKind getBuiltinVaListKind() const override { 6085 return TargetInfo::VoidPtrBuiltinVaList; 6086 } 6087 const char *getClobbers() const override { 6088 return ""; 6089 } 6090 void getGCCRegNames(const char * const *&Names, 6091 unsigned &NumNames) const override { 6092 static const char * const GCCRegNames[] = { 6093 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6094 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6095 }; 6096 Names = GCCRegNames; 6097 NumNames = llvm::array_lengthof(GCCRegNames); 6098 } 6099 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6100 unsigned &NumAliases) const override { 6101 Aliases = nullptr; 6102 NumAliases = 0; 6103 } 6104 bool validateAsmConstraint(const char *&Name, 6105 TargetInfo::ConstraintInfo &Info) const override { 6106 return false; 6107 } 6108 int getEHDataRegisterNumber(unsigned RegNo) const override { 6109 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6110 return (RegNo < 2)? RegNo : -1; 6111 } 6112 }; 6113 6114 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6115 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6116 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6117 ALL_LANGUAGES }, 6118 #include "clang/Basic/BuiltinsXCore.def" 6119 }; 6120 } // end anonymous namespace. 6121 6122 6123 //===----------------------------------------------------------------------===// 6124 // Driver code 6125 //===----------------------------------------------------------------------===// 6126 6127 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 6128 llvm::Triple::OSType os = Triple.getOS(); 6129 6130 switch (Triple.getArch()) { 6131 default: 6132 return nullptr; 6133 6134 case llvm::Triple::xcore: 6135 return new XCoreTargetInfo(Triple); 6136 6137 case llvm::Triple::hexagon: 6138 return new HexagonTargetInfo(Triple); 6139 6140 case llvm::Triple::aarch64: 6141 if (Triple.isOSDarwin()) 6142 return new DarwinAArch64TargetInfo(Triple); 6143 6144 switch (os) { 6145 case llvm::Triple::Linux: 6146 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6147 case llvm::Triple::NetBSD: 6148 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6149 default: 6150 return new AArch64leTargetInfo(Triple); 6151 } 6152 6153 case llvm::Triple::aarch64_be: 6154 switch (os) { 6155 case llvm::Triple::Linux: 6156 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6157 case llvm::Triple::NetBSD: 6158 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6159 default: 6160 return new AArch64beTargetInfo(Triple); 6161 } 6162 6163 case llvm::Triple::arm: 6164 case llvm::Triple::thumb: 6165 if (Triple.isOSBinFormatMachO()) 6166 return new DarwinARMTargetInfo(Triple); 6167 6168 switch (os) { 6169 case llvm::Triple::Linux: 6170 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6171 case llvm::Triple::FreeBSD: 6172 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6173 case llvm::Triple::NetBSD: 6174 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6175 case llvm::Triple::OpenBSD: 6176 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6177 case llvm::Triple::Bitrig: 6178 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6179 case llvm::Triple::RTEMS: 6180 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6181 case llvm::Triple::NaCl: 6182 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6183 case llvm::Triple::Win32: 6184 switch (Triple.getEnvironment()) { 6185 default: 6186 return new ARMleTargetInfo(Triple); 6187 case llvm::Triple::Itanium: 6188 return new ItaniumWindowsARMleTargetInfo(Triple); 6189 case llvm::Triple::MSVC: 6190 return new MicrosoftARMleTargetInfo(Triple); 6191 } 6192 default: 6193 return new ARMleTargetInfo(Triple); 6194 } 6195 6196 case llvm::Triple::armeb: 6197 case llvm::Triple::thumbeb: 6198 if (Triple.isOSDarwin()) 6199 return new DarwinARMTargetInfo(Triple); 6200 6201 switch (os) { 6202 case llvm::Triple::Linux: 6203 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 6204 case llvm::Triple::FreeBSD: 6205 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 6206 case llvm::Triple::NetBSD: 6207 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 6208 case llvm::Triple::OpenBSD: 6209 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 6210 case llvm::Triple::Bitrig: 6211 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 6212 case llvm::Triple::RTEMS: 6213 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 6214 case llvm::Triple::NaCl: 6215 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 6216 default: 6217 return new ARMbeTargetInfo(Triple); 6218 } 6219 6220 case llvm::Triple::msp430: 6221 return new MSP430TargetInfo(Triple); 6222 6223 case llvm::Triple::mips: 6224 switch (os) { 6225 case llvm::Triple::Linux: 6226 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 6227 case llvm::Triple::RTEMS: 6228 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 6229 case llvm::Triple::FreeBSD: 6230 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6231 case llvm::Triple::NetBSD: 6232 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6233 default: 6234 return new Mips32EBTargetInfo(Triple); 6235 } 6236 6237 case llvm::Triple::mipsel: 6238 switch (os) { 6239 case llvm::Triple::Linux: 6240 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 6241 case llvm::Triple::RTEMS: 6242 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 6243 case llvm::Triple::FreeBSD: 6244 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6245 case llvm::Triple::NetBSD: 6246 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6247 case llvm::Triple::NaCl: 6248 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 6249 default: 6250 return new Mips32ELTargetInfo(Triple); 6251 } 6252 6253 case llvm::Triple::mips64: 6254 switch (os) { 6255 case llvm::Triple::Linux: 6256 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 6257 case llvm::Triple::RTEMS: 6258 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 6259 case llvm::Triple::FreeBSD: 6260 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6261 case llvm::Triple::NetBSD: 6262 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6263 case llvm::Triple::OpenBSD: 6264 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6265 default: 6266 return new Mips64EBTargetInfo(Triple); 6267 } 6268 6269 case llvm::Triple::mips64el: 6270 switch (os) { 6271 case llvm::Triple::Linux: 6272 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 6273 case llvm::Triple::RTEMS: 6274 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 6275 case llvm::Triple::FreeBSD: 6276 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6277 case llvm::Triple::NetBSD: 6278 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6279 case llvm::Triple::OpenBSD: 6280 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6281 default: 6282 return new Mips64ELTargetInfo(Triple); 6283 } 6284 6285 case llvm::Triple::le32: 6286 switch (os) { 6287 case llvm::Triple::NaCl: 6288 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 6289 default: 6290 return nullptr; 6291 } 6292 6293 case llvm::Triple::ppc: 6294 if (Triple.isOSDarwin()) 6295 return new DarwinPPC32TargetInfo(Triple); 6296 switch (os) { 6297 case llvm::Triple::Linux: 6298 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 6299 case llvm::Triple::FreeBSD: 6300 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 6301 case llvm::Triple::NetBSD: 6302 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 6303 case llvm::Triple::OpenBSD: 6304 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 6305 case llvm::Triple::RTEMS: 6306 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 6307 default: 6308 return new PPC32TargetInfo(Triple); 6309 } 6310 6311 case llvm::Triple::ppc64: 6312 if (Triple.isOSDarwin()) 6313 return new DarwinPPC64TargetInfo(Triple); 6314 switch (os) { 6315 case llvm::Triple::Linux: 6316 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6317 case llvm::Triple::Lv2: 6318 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 6319 case llvm::Triple::FreeBSD: 6320 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 6321 case llvm::Triple::NetBSD: 6322 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6323 default: 6324 return new PPC64TargetInfo(Triple); 6325 } 6326 6327 case llvm::Triple::ppc64le: 6328 switch (os) { 6329 case llvm::Triple::Linux: 6330 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6331 default: 6332 return new PPC64TargetInfo(Triple); 6333 } 6334 6335 case llvm::Triple::nvptx: 6336 return new NVPTX32TargetInfo(Triple); 6337 case llvm::Triple::nvptx64: 6338 return new NVPTX64TargetInfo(Triple); 6339 6340 case llvm::Triple::r600: 6341 return new R600TargetInfo(Triple); 6342 6343 case llvm::Triple::sparc: 6344 switch (os) { 6345 case llvm::Triple::Linux: 6346 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 6347 case llvm::Triple::AuroraUX: 6348 return new AuroraUXSparcV8TargetInfo(Triple); 6349 case llvm::Triple::Solaris: 6350 return new SolarisSparcV8TargetInfo(Triple); 6351 case llvm::Triple::NetBSD: 6352 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 6353 case llvm::Triple::OpenBSD: 6354 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 6355 case llvm::Triple::RTEMS: 6356 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 6357 default: 6358 return new SparcV8TargetInfo(Triple); 6359 } 6360 6361 case llvm::Triple::sparcv9: 6362 switch (os) { 6363 case llvm::Triple::Linux: 6364 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 6365 case llvm::Triple::AuroraUX: 6366 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 6367 case llvm::Triple::Solaris: 6368 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 6369 case llvm::Triple::NetBSD: 6370 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 6371 case llvm::Triple::OpenBSD: 6372 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 6373 case llvm::Triple::FreeBSD: 6374 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 6375 default: 6376 return new SparcV9TargetInfo(Triple); 6377 } 6378 6379 case llvm::Triple::systemz: 6380 switch (os) { 6381 case llvm::Triple::Linux: 6382 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 6383 default: 6384 return new SystemZTargetInfo(Triple); 6385 } 6386 6387 case llvm::Triple::tce: 6388 return new TCETargetInfo(Triple); 6389 6390 case llvm::Triple::x86: 6391 if (Triple.isOSDarwin()) 6392 return new DarwinI386TargetInfo(Triple); 6393 6394 switch (os) { 6395 case llvm::Triple::AuroraUX: 6396 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 6397 case llvm::Triple::Linux: 6398 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 6399 case llvm::Triple::DragonFly: 6400 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 6401 case llvm::Triple::NetBSD: 6402 return new NetBSDI386TargetInfo(Triple); 6403 case llvm::Triple::OpenBSD: 6404 return new OpenBSDI386TargetInfo(Triple); 6405 case llvm::Triple::Bitrig: 6406 return new BitrigI386TargetInfo(Triple); 6407 case llvm::Triple::FreeBSD: 6408 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6409 case llvm::Triple::KFreeBSD: 6410 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6411 case llvm::Triple::Minix: 6412 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 6413 case llvm::Triple::Solaris: 6414 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 6415 case llvm::Triple::Win32: { 6416 switch (Triple.getEnvironment()) { 6417 default: 6418 return new X86_32TargetInfo(Triple); 6419 case llvm::Triple::Cygnus: 6420 return new CygwinX86_32TargetInfo(Triple); 6421 case llvm::Triple::GNU: 6422 return new MinGWX86_32TargetInfo(Triple); 6423 case llvm::Triple::Itanium: 6424 case llvm::Triple::MSVC: 6425 return new MicrosoftX86_32TargetInfo(Triple); 6426 } 6427 } 6428 case llvm::Triple::Haiku: 6429 return new HaikuX86_32TargetInfo(Triple); 6430 case llvm::Triple::RTEMS: 6431 return new RTEMSX86_32TargetInfo(Triple); 6432 case llvm::Triple::NaCl: 6433 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 6434 default: 6435 return new X86_32TargetInfo(Triple); 6436 } 6437 6438 case llvm::Triple::x86_64: 6439 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 6440 return new DarwinX86_64TargetInfo(Triple); 6441 6442 switch (os) { 6443 case llvm::Triple::AuroraUX: 6444 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 6445 case llvm::Triple::Linux: 6446 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 6447 case llvm::Triple::DragonFly: 6448 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 6449 case llvm::Triple::NetBSD: 6450 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 6451 case llvm::Triple::OpenBSD: 6452 return new OpenBSDX86_64TargetInfo(Triple); 6453 case llvm::Triple::Bitrig: 6454 return new BitrigX86_64TargetInfo(Triple); 6455 case llvm::Triple::FreeBSD: 6456 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6457 case llvm::Triple::KFreeBSD: 6458 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6459 case llvm::Triple::Solaris: 6460 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 6461 case llvm::Triple::Win32: { 6462 switch (Triple.getEnvironment()) { 6463 default: 6464 return new X86_64TargetInfo(Triple); 6465 case llvm::Triple::GNU: 6466 return new MinGWX86_64TargetInfo(Triple); 6467 case llvm::Triple::MSVC: 6468 return new MicrosoftX86_64TargetInfo(Triple); 6469 } 6470 } 6471 case llvm::Triple::NaCl: 6472 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 6473 default: 6474 return new X86_64TargetInfo(Triple); 6475 } 6476 6477 case llvm::Triple::spir: { 6478 if (Triple.getOS() != llvm::Triple::UnknownOS || 6479 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6480 return nullptr; 6481 return new SPIR32TargetInfo(Triple); 6482 } 6483 case llvm::Triple::spir64: { 6484 if (Triple.getOS() != llvm::Triple::UnknownOS || 6485 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6486 return nullptr; 6487 return new SPIR64TargetInfo(Triple); 6488 } 6489 } 6490 } 6491 6492 /// CreateTargetInfo - Return the target info object for the specified target 6493 /// triple. 6494 TargetInfo * 6495 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 6496 const std::shared_ptr<TargetOptions> &Opts) { 6497 llvm::Triple Triple(Opts->Triple); 6498 6499 // Construct the target 6500 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 6501 if (!Target) { 6502 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 6503 return nullptr; 6504 } 6505 Target->TargetOpts = Opts; 6506 6507 // Set the target CPU if specified. 6508 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 6509 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 6510 return nullptr; 6511 } 6512 6513 // Set the target ABI if specified. 6514 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 6515 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 6516 return nullptr; 6517 } 6518 6519 // Set the fp math unit. 6520 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 6521 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 6522 return nullptr; 6523 } 6524 6525 // Compute the default target features, we need the target to handle this 6526 // because features may have dependencies on one another. 6527 llvm::StringMap<bool> Features; 6528 Target->getDefaultFeatures(Features); 6529 6530 // Apply the user specified deltas. 6531 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 6532 I < N; ++I) { 6533 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 6534 // Apply the feature via the target. 6535 bool Enabled = Name[0] == '+'; 6536 Target->setFeatureEnabled(Features, Name + 1, Enabled); 6537 } 6538 6539 // Add the features to the compile options. 6540 // 6541 // FIXME: If we are completely confident that we have the right set, we only 6542 // need to pass the minuses. 6543 Opts->Features.clear(); 6544 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 6545 ie = Features.end(); it != ie; ++it) 6546 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 6547 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 6548 return nullptr; 6549 6550 return Target.release(); 6551 } 6552