1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 } 469 if (Opts.POSIXThreads) 470 Builder.defineMacro("_REENTRANT"); 471 if (Opts.CPlusPlus) 472 Builder.defineMacro("_GNU_SOURCE"); 473 if (this->HasFloat128) 474 Builder.defineMacro("__FLOAT128__"); 475 } 476 public: 477 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 478 : OSTargetInfo<Target>(Triple, Opts) { 479 this->WIntType = TargetInfo::UnsignedInt; 480 481 switch (Triple.getArch()) { 482 default: 483 break; 484 case llvm::Triple::ppc: 485 case llvm::Triple::ppc64: 486 case llvm::Triple::ppc64le: 487 this->MCountName = "_mcount"; 488 break; 489 case llvm::Triple::x86: 490 case llvm::Triple::x86_64: 491 case llvm::Triple::systemz: 492 this->HasFloat128 = true; 493 break; 494 } 495 } 496 497 const char *getStaticInitSectionSpecifier() const override { 498 return ".text.startup"; 499 } 500 }; 501 502 // NetBSD Target 503 template<typename Target> 504 class NetBSDTargetInfo : public OSTargetInfo<Target> { 505 protected: 506 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 507 MacroBuilder &Builder) const override { 508 // NetBSD defines; list based off of gcc output 509 Builder.defineMacro("__NetBSD__"); 510 Builder.defineMacro("__unix__"); 511 Builder.defineMacro("__ELF__"); 512 if (Opts.POSIXThreads) 513 Builder.defineMacro("_POSIX_THREADS"); 514 515 switch (Triple.getArch()) { 516 default: 517 break; 518 case llvm::Triple::arm: 519 case llvm::Triple::armeb: 520 case llvm::Triple::thumb: 521 case llvm::Triple::thumbeb: 522 Builder.defineMacro("__ARM_DWARF_EH__"); 523 break; 524 } 525 } 526 public: 527 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 528 : OSTargetInfo<Target>(Triple, Opts) { 529 this->MCountName = "_mcount"; 530 } 531 }; 532 533 // OpenBSD Target 534 template<typename Target> 535 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 536 protected: 537 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 538 MacroBuilder &Builder) const override { 539 // OpenBSD defines; list based off of gcc output 540 541 Builder.defineMacro("__OpenBSD__"); 542 DefineStd(Builder, "unix", Opts); 543 Builder.defineMacro("__ELF__"); 544 if (Opts.POSIXThreads) 545 Builder.defineMacro("_REENTRANT"); 546 } 547 public: 548 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 549 : OSTargetInfo<Target>(Triple, Opts) { 550 this->TLSSupported = false; 551 552 switch (Triple.getArch()) { 553 default: 554 case llvm::Triple::x86: 555 case llvm::Triple::x86_64: 556 case llvm::Triple::arm: 557 case llvm::Triple::sparc: 558 this->MCountName = "__mcount"; 559 break; 560 case llvm::Triple::mips64: 561 case llvm::Triple::mips64el: 562 case llvm::Triple::ppc: 563 case llvm::Triple::sparcv9: 564 this->MCountName = "_mcount"; 565 break; 566 } 567 } 568 }; 569 570 // Bitrig Target 571 template<typename Target> 572 class BitrigTargetInfo : public OSTargetInfo<Target> { 573 protected: 574 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 575 MacroBuilder &Builder) const override { 576 // Bitrig defines; list based off of gcc output 577 578 Builder.defineMacro("__Bitrig__"); 579 DefineStd(Builder, "unix", Opts); 580 Builder.defineMacro("__ELF__"); 581 if (Opts.POSIXThreads) 582 Builder.defineMacro("_REENTRANT"); 583 584 switch (Triple.getArch()) { 585 default: 586 break; 587 case llvm::Triple::arm: 588 case llvm::Triple::armeb: 589 case llvm::Triple::thumb: 590 case llvm::Triple::thumbeb: 591 Builder.defineMacro("__ARM_DWARF_EH__"); 592 break; 593 } 594 } 595 public: 596 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 597 : OSTargetInfo<Target>(Triple, Opts) { 598 this->MCountName = "__mcount"; 599 } 600 }; 601 602 // PSP Target 603 template<typename Target> 604 class PSPTargetInfo : public OSTargetInfo<Target> { 605 protected: 606 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 607 MacroBuilder &Builder) const override { 608 // PSP defines; list based on the output of the pspdev gcc toolchain. 609 Builder.defineMacro("PSP"); 610 Builder.defineMacro("_PSP"); 611 Builder.defineMacro("__psp__"); 612 Builder.defineMacro("__ELF__"); 613 } 614 public: 615 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 616 }; 617 618 // PS3 PPU Target 619 template<typename Target> 620 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 621 protected: 622 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 623 MacroBuilder &Builder) const override { 624 // PS3 PPU defines. 625 Builder.defineMacro("__PPC__"); 626 Builder.defineMacro("__PPU__"); 627 Builder.defineMacro("__CELLOS_LV2__"); 628 Builder.defineMacro("__ELF__"); 629 Builder.defineMacro("__LP32__"); 630 Builder.defineMacro("_ARCH_PPC64"); 631 Builder.defineMacro("__powerpc64__"); 632 } 633 public: 634 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 635 : OSTargetInfo<Target>(Triple, Opts) { 636 this->LongWidth = this->LongAlign = 32; 637 this->PointerWidth = this->PointerAlign = 32; 638 this->IntMaxType = TargetInfo::SignedLongLong; 639 this->Int64Type = TargetInfo::SignedLongLong; 640 this->SizeType = TargetInfo::UnsignedInt; 641 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 642 } 643 }; 644 645 template <typename Target> 646 class PS4OSTargetInfo : public OSTargetInfo<Target> { 647 protected: 648 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 649 MacroBuilder &Builder) const override { 650 Builder.defineMacro("__FreeBSD__", "9"); 651 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 652 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 653 DefineStd(Builder, "unix", Opts); 654 Builder.defineMacro("__ELF__"); 655 Builder.defineMacro("__ORBIS__"); 656 } 657 public: 658 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 659 : OSTargetInfo<Target>(Triple, Opts) { 660 this->WCharType = this->UnsignedShort; 661 662 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 663 this->MaxTLSAlign = 256; 664 665 // On PS4, do not honor explicit bit field alignment, 666 // as in "__attribute__((aligned(2))) int b : 1;". 667 this->UseExplicitBitFieldAlignment = false; 668 669 switch (Triple.getArch()) { 670 default: 671 case llvm::Triple::x86_64: 672 this->MCountName = ".mcount"; 673 break; 674 } 675 } 676 }; 677 678 // Solaris target 679 template<typename Target> 680 class SolarisTargetInfo : public OSTargetInfo<Target> { 681 protected: 682 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 683 MacroBuilder &Builder) const override { 684 DefineStd(Builder, "sun", Opts); 685 DefineStd(Builder, "unix", Opts); 686 Builder.defineMacro("__ELF__"); 687 Builder.defineMacro("__svr4__"); 688 Builder.defineMacro("__SVR4"); 689 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 690 // newer, but to 500 for everything else. feature_test.h has a check to 691 // ensure that you are not using C99 with an old version of X/Open or C89 692 // with a new version. 693 if (Opts.C99) 694 Builder.defineMacro("_XOPEN_SOURCE", "600"); 695 else 696 Builder.defineMacro("_XOPEN_SOURCE", "500"); 697 if (Opts.CPlusPlus) 698 Builder.defineMacro("__C99FEATURES__"); 699 Builder.defineMacro("_LARGEFILE_SOURCE"); 700 Builder.defineMacro("_LARGEFILE64_SOURCE"); 701 Builder.defineMacro("__EXTENSIONS__"); 702 Builder.defineMacro("_REENTRANT"); 703 } 704 public: 705 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 706 : OSTargetInfo<Target>(Triple, Opts) { 707 this->WCharType = this->SignedInt; 708 // FIXME: WIntType should be SignedLong 709 } 710 }; 711 712 // Windows target 713 template<typename Target> 714 class WindowsTargetInfo : public OSTargetInfo<Target> { 715 protected: 716 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 717 MacroBuilder &Builder) const override { 718 Builder.defineMacro("_WIN32"); 719 } 720 void getVisualStudioDefines(const LangOptions &Opts, 721 MacroBuilder &Builder) const { 722 if (Opts.CPlusPlus) { 723 if (Opts.RTTIData) 724 Builder.defineMacro("_CPPRTTI"); 725 726 if (Opts.CXXExceptions) 727 Builder.defineMacro("_CPPUNWIND"); 728 } 729 730 if (Opts.Bool) 731 Builder.defineMacro("__BOOL_DEFINED"); 732 733 if (!Opts.CharIsSigned) 734 Builder.defineMacro("_CHAR_UNSIGNED"); 735 736 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 737 // but it works for now. 738 if (Opts.POSIXThreads) 739 Builder.defineMacro("_MT"); 740 741 if (Opts.MSCompatibilityVersion) { 742 Builder.defineMacro("_MSC_VER", 743 Twine(Opts.MSCompatibilityVersion / 100000)); 744 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 745 // FIXME We cannot encode the revision information into 32-bits 746 Builder.defineMacro("_MSC_BUILD", Twine(1)); 747 748 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 749 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 750 751 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 752 if (Opts.CPlusPlus1z) 753 Builder.defineMacro("_MSVC_LANG", "201403L"); 754 else if (Opts.CPlusPlus14) 755 Builder.defineMacro("_MSVC_LANG", "201402L"); 756 } 757 } 758 759 if (Opts.MicrosoftExt) { 760 Builder.defineMacro("_MSC_EXTENSIONS"); 761 762 if (Opts.CPlusPlus11) { 763 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 764 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 765 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 766 } 767 } 768 769 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 770 } 771 772 public: 773 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 774 : OSTargetInfo<Target>(Triple, Opts) {} 775 }; 776 777 template <typename Target> 778 class NaClTargetInfo : public OSTargetInfo<Target> { 779 protected: 780 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 781 MacroBuilder &Builder) const override { 782 if (Opts.POSIXThreads) 783 Builder.defineMacro("_REENTRANT"); 784 if (Opts.CPlusPlus) 785 Builder.defineMacro("_GNU_SOURCE"); 786 787 DefineStd(Builder, "unix", Opts); 788 Builder.defineMacro("__ELF__"); 789 Builder.defineMacro("__native_client__"); 790 } 791 792 public: 793 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 794 : OSTargetInfo<Target>(Triple, Opts) { 795 this->LongAlign = 32; 796 this->LongWidth = 32; 797 this->PointerAlign = 32; 798 this->PointerWidth = 32; 799 this->IntMaxType = TargetInfo::SignedLongLong; 800 this->Int64Type = TargetInfo::SignedLongLong; 801 this->DoubleAlign = 64; 802 this->LongDoubleWidth = 64; 803 this->LongDoubleAlign = 64; 804 this->LongLongWidth = 64; 805 this->LongLongAlign = 64; 806 this->SizeType = TargetInfo::UnsignedInt; 807 this->PtrDiffType = TargetInfo::SignedInt; 808 this->IntPtrType = TargetInfo::SignedInt; 809 // RegParmMax is inherited from the underlying architecture. 810 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 811 if (Triple.getArch() == llvm::Triple::arm) { 812 // Handled in ARM's setABI(). 813 } else if (Triple.getArch() == llvm::Triple::x86) { 814 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 815 } else if (Triple.getArch() == llvm::Triple::x86_64) { 816 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 817 } else if (Triple.getArch() == llvm::Triple::mipsel) { 818 // Handled on mips' setDataLayout. 819 } else { 820 assert(Triple.getArch() == llvm::Triple::le32); 821 this->resetDataLayout("e-p:32:32-i64:64"); 822 } 823 } 824 }; 825 826 // Fuchsia Target 827 template<typename Target> 828 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 829 protected: 830 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 831 MacroBuilder &Builder) const override { 832 Builder.defineMacro("__Fuchsia__"); 833 Builder.defineMacro("__ELF__"); 834 if (Opts.POSIXThreads) 835 Builder.defineMacro("_REENTRANT"); 836 // Required by the libc++ locale support. 837 if (Opts.CPlusPlus) 838 Builder.defineMacro("_GNU_SOURCE"); 839 } 840 public: 841 FuchsiaTargetInfo(const llvm::Triple &Triple, 842 const TargetOptions &Opts) 843 : OSTargetInfo<Target>(Triple, Opts) { 844 this->MCountName = "__mcount"; 845 } 846 }; 847 848 // WebAssembly target 849 template <typename Target> 850 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 851 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 852 MacroBuilder &Builder) const final { 853 // A common platform macro. 854 if (Opts.POSIXThreads) 855 Builder.defineMacro("_REENTRANT"); 856 // Follow g++ convention and predefine _GNU_SOURCE for C++. 857 if (Opts.CPlusPlus) 858 Builder.defineMacro("_GNU_SOURCE"); 859 } 860 861 // As an optimization, group static init code together in a section. 862 const char *getStaticInitSectionSpecifier() const final { 863 return ".text.__startup"; 864 } 865 866 public: 867 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 868 const TargetOptions &Opts) 869 : OSTargetInfo<Target>(Triple, Opts) { 870 this->MCountName = "__mcount"; 871 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 872 } 873 }; 874 875 //===----------------------------------------------------------------------===// 876 // Specific target implementations. 877 //===----------------------------------------------------------------------===// 878 879 // PPC abstract base class 880 class PPCTargetInfo : public TargetInfo { 881 static const Builtin::Info BuiltinInfo[]; 882 static const char * const GCCRegNames[]; 883 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 884 std::string CPU; 885 886 // Target cpu features. 887 bool HasVSX; 888 bool HasP8Vector; 889 bool HasP8Crypto; 890 bool HasDirectMove; 891 bool HasQPX; 892 bool HasHTM; 893 bool HasBPERMD; 894 bool HasExtDiv; 895 bool HasP9Vector; 896 897 protected: 898 std::string ABI; 899 900 public: 901 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 902 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 903 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 904 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 905 SimdDefaultAlign = 128; 906 LongDoubleWidth = LongDoubleAlign = 128; 907 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 908 } 909 910 /// \brief Flags for architecture specific defines. 911 typedef enum { 912 ArchDefineNone = 0, 913 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 914 ArchDefinePpcgr = 1 << 1, 915 ArchDefinePpcsq = 1 << 2, 916 ArchDefine440 = 1 << 3, 917 ArchDefine603 = 1 << 4, 918 ArchDefine604 = 1 << 5, 919 ArchDefinePwr4 = 1 << 6, 920 ArchDefinePwr5 = 1 << 7, 921 ArchDefinePwr5x = 1 << 8, 922 ArchDefinePwr6 = 1 << 9, 923 ArchDefinePwr6x = 1 << 10, 924 ArchDefinePwr7 = 1 << 11, 925 ArchDefinePwr8 = 1 << 12, 926 ArchDefinePwr9 = 1 << 13, 927 ArchDefineA2 = 1 << 14, 928 ArchDefineA2q = 1 << 15 929 } ArchDefineTypes; 930 931 // Note: GCC recognizes the following additional cpus: 932 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 933 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 934 // titan, rs64. 935 bool setCPU(const std::string &Name) override { 936 bool CPUKnown = llvm::StringSwitch<bool>(Name) 937 .Case("generic", true) 938 .Case("440", true) 939 .Case("450", true) 940 .Case("601", true) 941 .Case("602", true) 942 .Case("603", true) 943 .Case("603e", true) 944 .Case("603ev", true) 945 .Case("604", true) 946 .Case("604e", true) 947 .Case("620", true) 948 .Case("630", true) 949 .Case("g3", true) 950 .Case("7400", true) 951 .Case("g4", true) 952 .Case("7450", true) 953 .Case("g4+", true) 954 .Case("750", true) 955 .Case("970", true) 956 .Case("g5", true) 957 .Case("a2", true) 958 .Case("a2q", true) 959 .Case("e500mc", true) 960 .Case("e5500", true) 961 .Case("power3", true) 962 .Case("pwr3", true) 963 .Case("power4", true) 964 .Case("pwr4", true) 965 .Case("power5", true) 966 .Case("pwr5", true) 967 .Case("power5x", true) 968 .Case("pwr5x", true) 969 .Case("power6", true) 970 .Case("pwr6", true) 971 .Case("power6x", true) 972 .Case("pwr6x", true) 973 .Case("power7", true) 974 .Case("pwr7", true) 975 .Case("power8", true) 976 .Case("pwr8", true) 977 .Case("power9", true) 978 .Case("pwr9", true) 979 .Case("powerpc", true) 980 .Case("ppc", true) 981 .Case("powerpc64", true) 982 .Case("ppc64", true) 983 .Case("powerpc64le", true) 984 .Case("ppc64le", true) 985 .Default(false); 986 987 if (CPUKnown) 988 CPU = Name; 989 990 return CPUKnown; 991 } 992 993 994 StringRef getABI() const override { return ABI; } 995 996 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 997 return llvm::makeArrayRef(BuiltinInfo, 998 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 999 } 1000 1001 bool isCLZForZeroUndef() const override { return false; } 1002 1003 void getTargetDefines(const LangOptions &Opts, 1004 MacroBuilder &Builder) const override; 1005 1006 bool 1007 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1008 StringRef CPU, 1009 const std::vector<std::string> &FeaturesVec) const override; 1010 1011 bool handleTargetFeatures(std::vector<std::string> &Features, 1012 DiagnosticsEngine &Diags) override; 1013 bool hasFeature(StringRef Feature) const override; 1014 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1015 bool Enabled) const override; 1016 1017 ArrayRef<const char *> getGCCRegNames() const override; 1018 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1019 bool validateAsmConstraint(const char *&Name, 1020 TargetInfo::ConstraintInfo &Info) const override { 1021 switch (*Name) { 1022 default: return false; 1023 case 'O': // Zero 1024 break; 1025 case 'b': // Base register 1026 case 'f': // Floating point register 1027 Info.setAllowsRegister(); 1028 break; 1029 // FIXME: The following are added to allow parsing. 1030 // I just took a guess at what the actions should be. 1031 // Also, is more specific checking needed? I.e. specific registers? 1032 case 'd': // Floating point register (containing 64-bit value) 1033 case 'v': // Altivec vector register 1034 Info.setAllowsRegister(); 1035 break; 1036 case 'w': 1037 switch (Name[1]) { 1038 case 'd':// VSX vector register to hold vector double data 1039 case 'f':// VSX vector register to hold vector float data 1040 case 's':// VSX vector register to hold scalar float data 1041 case 'a':// Any VSX register 1042 case 'c':// An individual CR bit 1043 break; 1044 default: 1045 return false; 1046 } 1047 Info.setAllowsRegister(); 1048 Name++; // Skip over 'w'. 1049 break; 1050 case 'h': // `MQ', `CTR', or `LINK' register 1051 case 'q': // `MQ' register 1052 case 'c': // `CTR' register 1053 case 'l': // `LINK' register 1054 case 'x': // `CR' register (condition register) number 0 1055 case 'y': // `CR' register (condition register) 1056 case 'z': // `XER[CA]' carry bit (part of the XER register) 1057 Info.setAllowsRegister(); 1058 break; 1059 case 'I': // Signed 16-bit constant 1060 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1061 // (use `L' instead for SImode constants) 1062 case 'K': // Unsigned 16-bit constant 1063 case 'L': // Signed 16-bit constant shifted left 16 bits 1064 case 'M': // Constant larger than 31 1065 case 'N': // Exact power of 2 1066 case 'P': // Constant whose negation is a signed 16-bit constant 1067 case 'G': // Floating point constant that can be loaded into a 1068 // register with one instruction per word 1069 case 'H': // Integer/Floating point constant that can be loaded 1070 // into a register using three instructions 1071 break; 1072 case 'm': // Memory operand. Note that on PowerPC targets, m can 1073 // include addresses that update the base register. It 1074 // is therefore only safe to use `m' in an asm statement 1075 // if that asm statement accesses the operand exactly once. 1076 // The asm statement must also use `%U<opno>' as a 1077 // placeholder for the "update" flag in the corresponding 1078 // load or store instruction. For example: 1079 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1080 // is correct but: 1081 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1082 // is not. Use es rather than m if you don't want the base 1083 // register to be updated. 1084 case 'e': 1085 if (Name[1] != 's') 1086 return false; 1087 // es: A "stable" memory operand; that is, one which does not 1088 // include any automodification of the base register. Unlike 1089 // `m', this constraint can be used in asm statements that 1090 // might access the operand several times, or that might not 1091 // access it at all. 1092 Info.setAllowsMemory(); 1093 Name++; // Skip over 'e'. 1094 break; 1095 case 'Q': // Memory operand that is an offset from a register (it is 1096 // usually better to use `m' or `es' in asm statements) 1097 case 'Z': // Memory operand that is an indexed or indirect from a 1098 // register (it is usually better to use `m' or `es' in 1099 // asm statements) 1100 Info.setAllowsMemory(); 1101 Info.setAllowsRegister(); 1102 break; 1103 case 'R': // AIX TOC entry 1104 case 'a': // Address operand that is an indexed or indirect from a 1105 // register (`p' is preferable for asm statements) 1106 case 'S': // Constant suitable as a 64-bit mask operand 1107 case 'T': // Constant suitable as a 32-bit mask operand 1108 case 'U': // System V Release 4 small data area reference 1109 case 't': // AND masks that can be performed by two rldic{l, r} 1110 // instructions 1111 case 'W': // Vector constant that does not require memory 1112 case 'j': // Vector constant that is all zeros. 1113 break; 1114 // End FIXME. 1115 } 1116 return true; 1117 } 1118 std::string convertConstraint(const char *&Constraint) const override { 1119 std::string R; 1120 switch (*Constraint) { 1121 case 'e': 1122 case 'w': 1123 // Two-character constraint; add "^" hint for later parsing. 1124 R = std::string("^") + std::string(Constraint, 2); 1125 Constraint++; 1126 break; 1127 default: 1128 return TargetInfo::convertConstraint(Constraint); 1129 } 1130 return R; 1131 } 1132 const char *getClobbers() const override { 1133 return ""; 1134 } 1135 int getEHDataRegisterNumber(unsigned RegNo) const override { 1136 if (RegNo == 0) return 3; 1137 if (RegNo == 1) return 4; 1138 return -1; 1139 } 1140 1141 bool hasSjLjLowering() const override { 1142 return true; 1143 } 1144 1145 bool useFloat128ManglingForLongDouble() const override { 1146 return LongDoubleWidth == 128 && 1147 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1148 getTriple().isOSBinFormatELF(); 1149 } 1150 }; 1151 1152 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1153 #define BUILTIN(ID, TYPE, ATTRS) \ 1154 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1155 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1156 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1157 #include "clang/Basic/BuiltinsPPC.def" 1158 }; 1159 1160 /// handleTargetFeatures - Perform initialization based on the user 1161 /// configured set of features. 1162 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1163 DiagnosticsEngine &Diags) { 1164 for (const auto &Feature : Features) { 1165 if (Feature == "+vsx") { 1166 HasVSX = true; 1167 } else if (Feature == "+bpermd") { 1168 HasBPERMD = true; 1169 } else if (Feature == "+extdiv") { 1170 HasExtDiv = true; 1171 } else if (Feature == "+power8-vector") { 1172 HasP8Vector = true; 1173 } else if (Feature == "+crypto") { 1174 HasP8Crypto = true; 1175 } else if (Feature == "+direct-move") { 1176 HasDirectMove = true; 1177 } else if (Feature == "+qpx") { 1178 HasQPX = true; 1179 } else if (Feature == "+htm") { 1180 HasHTM = true; 1181 } else if (Feature == "+float128") { 1182 HasFloat128 = true; 1183 } else if (Feature == "+power9-vector") { 1184 HasP9Vector = true; 1185 } 1186 // TODO: Finish this list and add an assert that we've handled them 1187 // all. 1188 } 1189 1190 return true; 1191 } 1192 1193 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1194 /// #defines that are not tied to a specific subtarget. 1195 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1196 MacroBuilder &Builder) const { 1197 // Target identification. 1198 Builder.defineMacro("__ppc__"); 1199 Builder.defineMacro("__PPC__"); 1200 Builder.defineMacro("_ARCH_PPC"); 1201 Builder.defineMacro("__powerpc__"); 1202 Builder.defineMacro("__POWERPC__"); 1203 if (PointerWidth == 64) { 1204 Builder.defineMacro("_ARCH_PPC64"); 1205 Builder.defineMacro("__powerpc64__"); 1206 Builder.defineMacro("__ppc64__"); 1207 Builder.defineMacro("__PPC64__"); 1208 } 1209 1210 // Target properties. 1211 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1212 Builder.defineMacro("_LITTLE_ENDIAN"); 1213 } else { 1214 if (getTriple().getOS() != llvm::Triple::NetBSD && 1215 getTriple().getOS() != llvm::Triple::OpenBSD) 1216 Builder.defineMacro("_BIG_ENDIAN"); 1217 } 1218 1219 // ABI options. 1220 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1221 Builder.defineMacro("_CALL_ELF", "1"); 1222 if (ABI == "elfv2") 1223 Builder.defineMacro("_CALL_ELF", "2"); 1224 1225 // Subtarget options. 1226 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1227 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1228 1229 // FIXME: Should be controlled by command line option. 1230 if (LongDoubleWidth == 128) 1231 Builder.defineMacro("__LONG_DOUBLE_128__"); 1232 1233 if (Opts.AltiVec) { 1234 Builder.defineMacro("__VEC__", "10206"); 1235 Builder.defineMacro("__ALTIVEC__"); 1236 } 1237 1238 // CPU identification. 1239 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1240 .Case("440", ArchDefineName) 1241 .Case("450", ArchDefineName | ArchDefine440) 1242 .Case("601", ArchDefineName) 1243 .Case("602", ArchDefineName | ArchDefinePpcgr) 1244 .Case("603", ArchDefineName | ArchDefinePpcgr) 1245 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1246 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1247 .Case("604", ArchDefineName | ArchDefinePpcgr) 1248 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1249 .Case("620", ArchDefineName | ArchDefinePpcgr) 1250 .Case("630", ArchDefineName | ArchDefinePpcgr) 1251 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1252 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1253 .Case("750", ArchDefineName | ArchDefinePpcgr) 1254 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1255 | ArchDefinePpcsq) 1256 .Case("a2", ArchDefineA2) 1257 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1258 .Case("pwr3", ArchDefinePpcgr) 1259 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1260 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1261 | ArchDefinePpcsq) 1262 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1263 | ArchDefinePpcgr | ArchDefinePpcsq) 1264 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1265 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1266 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1267 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1268 | ArchDefinePpcsq) 1269 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1270 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1271 | ArchDefinePpcgr | ArchDefinePpcsq) 1272 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1273 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1274 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1275 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1276 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1277 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1278 | ArchDefinePpcsq) 1279 .Case("power3", ArchDefinePpcgr) 1280 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1281 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1282 | ArchDefinePpcsq) 1283 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1284 | ArchDefinePpcgr | ArchDefinePpcsq) 1285 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1286 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1287 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1288 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1289 | ArchDefinePpcsq) 1290 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1291 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1292 | ArchDefinePpcgr | ArchDefinePpcsq) 1293 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1294 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1295 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1296 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1297 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1298 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1299 | ArchDefinePpcsq) 1300 .Default(ArchDefineNone); 1301 1302 if (defs & ArchDefineName) 1303 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1304 if (defs & ArchDefinePpcgr) 1305 Builder.defineMacro("_ARCH_PPCGR"); 1306 if (defs & ArchDefinePpcsq) 1307 Builder.defineMacro("_ARCH_PPCSQ"); 1308 if (defs & ArchDefine440) 1309 Builder.defineMacro("_ARCH_440"); 1310 if (defs & ArchDefine603) 1311 Builder.defineMacro("_ARCH_603"); 1312 if (defs & ArchDefine604) 1313 Builder.defineMacro("_ARCH_604"); 1314 if (defs & ArchDefinePwr4) 1315 Builder.defineMacro("_ARCH_PWR4"); 1316 if (defs & ArchDefinePwr5) 1317 Builder.defineMacro("_ARCH_PWR5"); 1318 if (defs & ArchDefinePwr5x) 1319 Builder.defineMacro("_ARCH_PWR5X"); 1320 if (defs & ArchDefinePwr6) 1321 Builder.defineMacro("_ARCH_PWR6"); 1322 if (defs & ArchDefinePwr6x) 1323 Builder.defineMacro("_ARCH_PWR6X"); 1324 if (defs & ArchDefinePwr7) 1325 Builder.defineMacro("_ARCH_PWR7"); 1326 if (defs & ArchDefinePwr8) 1327 Builder.defineMacro("_ARCH_PWR8"); 1328 if (defs & ArchDefinePwr9) 1329 Builder.defineMacro("_ARCH_PWR9"); 1330 if (defs & ArchDefineA2) 1331 Builder.defineMacro("_ARCH_A2"); 1332 if (defs & ArchDefineA2q) { 1333 Builder.defineMacro("_ARCH_A2Q"); 1334 Builder.defineMacro("_ARCH_QP"); 1335 } 1336 1337 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1338 Builder.defineMacro("__bg__"); 1339 Builder.defineMacro("__THW_BLUEGENE__"); 1340 Builder.defineMacro("__bgq__"); 1341 Builder.defineMacro("__TOS_BGQ__"); 1342 } 1343 1344 if (HasVSX) 1345 Builder.defineMacro("__VSX__"); 1346 if (HasP8Vector) 1347 Builder.defineMacro("__POWER8_VECTOR__"); 1348 if (HasP8Crypto) 1349 Builder.defineMacro("__CRYPTO__"); 1350 if (HasHTM) 1351 Builder.defineMacro("__HTM__"); 1352 if (HasFloat128) 1353 Builder.defineMacro("__FLOAT128__"); 1354 if (HasP9Vector) 1355 Builder.defineMacro("__POWER9_VECTOR__"); 1356 1357 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1358 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1359 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1360 if (PointerWidth == 64) 1361 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1362 1363 // FIXME: The following are not yet generated here by Clang, but are 1364 // generated by GCC: 1365 // 1366 // _SOFT_FLOAT_ 1367 // __RECIP_PRECISION__ 1368 // __APPLE_ALTIVEC__ 1369 // __RECIP__ 1370 // __RECIPF__ 1371 // __RSQRTE__ 1372 // __RSQRTEF__ 1373 // _SOFT_DOUBLE_ 1374 // __NO_LWSYNC__ 1375 // __HAVE_BSWAP__ 1376 // __LONGDOUBLE128 1377 // __CMODEL_MEDIUM__ 1378 // __CMODEL_LARGE__ 1379 // _CALL_SYSV 1380 // _CALL_DARWIN 1381 // __NO_FPRS__ 1382 } 1383 1384 // Handle explicit options being passed to the compiler here: if we've 1385 // explicitly turned off vsx and turned on any of: 1386 // - power8-vector 1387 // - direct-move 1388 // - float128 1389 // - power9-vector 1390 // then go ahead and error since the customer has expressed an incompatible 1391 // set of options. 1392 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1393 const std::vector<std::string> &FeaturesVec) { 1394 1395 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1396 FeaturesVec.end()) { 1397 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1398 FeaturesVec.end()) { 1399 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1400 << "-mno-vsx"; 1401 return false; 1402 } 1403 1404 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1405 FeaturesVec.end()) { 1406 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1407 << "-mno-vsx"; 1408 return false; 1409 } 1410 1411 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1412 FeaturesVec.end()) { 1413 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1414 << "-mno-vsx"; 1415 return false; 1416 } 1417 1418 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1419 FeaturesVec.end()) { 1420 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1421 << "-mno-vsx"; 1422 return false; 1423 } 1424 } 1425 1426 return true; 1427 } 1428 1429 bool PPCTargetInfo::initFeatureMap( 1430 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1431 const std::vector<std::string> &FeaturesVec) const { 1432 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1433 .Case("7400", true) 1434 .Case("g4", true) 1435 .Case("7450", true) 1436 .Case("g4+", true) 1437 .Case("970", true) 1438 .Case("g5", true) 1439 .Case("pwr6", true) 1440 .Case("pwr7", true) 1441 .Case("pwr8", true) 1442 .Case("pwr9", true) 1443 .Case("ppc64", true) 1444 .Case("ppc64le", true) 1445 .Default(false); 1446 1447 Features["qpx"] = (CPU == "a2q"); 1448 Features["power9-vector"] = (CPU == "pwr9"); 1449 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1450 .Case("ppc64le", true) 1451 .Case("pwr9", true) 1452 .Case("pwr8", true) 1453 .Default(false); 1454 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1455 .Case("ppc64le", true) 1456 .Case("pwr9", true) 1457 .Case("pwr8", true) 1458 .Default(false); 1459 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1460 .Case("ppc64le", true) 1461 .Case("pwr9", true) 1462 .Case("pwr8", true) 1463 .Case("pwr7", true) 1464 .Default(false); 1465 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1466 .Case("ppc64le", true) 1467 .Case("pwr9", true) 1468 .Case("pwr8", true) 1469 .Case("pwr7", true) 1470 .Default(false); 1471 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1472 .Case("ppc64le", true) 1473 .Case("pwr9", true) 1474 .Case("pwr8", true) 1475 .Default(false); 1476 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1477 .Case("ppc64le", true) 1478 .Case("pwr9", true) 1479 .Case("pwr8", true) 1480 .Case("pwr7", true) 1481 .Default(false); 1482 1483 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1484 return false; 1485 1486 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1487 } 1488 1489 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1490 return llvm::StringSwitch<bool>(Feature) 1491 .Case("powerpc", true) 1492 .Case("vsx", HasVSX) 1493 .Case("power8-vector", HasP8Vector) 1494 .Case("crypto", HasP8Crypto) 1495 .Case("direct-move", HasDirectMove) 1496 .Case("qpx", HasQPX) 1497 .Case("htm", HasHTM) 1498 .Case("bpermd", HasBPERMD) 1499 .Case("extdiv", HasExtDiv) 1500 .Case("float128", HasFloat128) 1501 .Case("power9-vector", HasP9Vector) 1502 .Default(false); 1503 } 1504 1505 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1506 StringRef Name, bool Enabled) const { 1507 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1508 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1509 // incompatible options. 1510 if (Enabled) { 1511 if (Name == "direct-move" || 1512 Name == "power8-vector" || 1513 Name == "float128" || 1514 Name == "power9-vector") { 1515 // power9-vector is really a superset of power8-vector so encode that. 1516 Features[Name] = Features["vsx"] = true; 1517 if (Name == "power9-vector") 1518 Features["power8-vector"] = true; 1519 } else { 1520 Features[Name] = true; 1521 } 1522 } else { 1523 if (Name == "vsx") { 1524 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1525 Features["float128"] = Features["power9-vector"] = false; 1526 } else { 1527 Features[Name] = false; 1528 } 1529 } 1530 } 1531 1532 const char * const PPCTargetInfo::GCCRegNames[] = { 1533 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1534 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1535 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1536 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1537 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1538 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1539 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1540 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1541 "mq", "lr", "ctr", "ap", 1542 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1543 "xer", 1544 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1545 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1546 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1547 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1548 "vrsave", "vscr", 1549 "spe_acc", "spefscr", 1550 "sfp" 1551 }; 1552 1553 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1554 return llvm::makeArrayRef(GCCRegNames); 1555 } 1556 1557 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1558 // While some of these aliases do map to different registers 1559 // they still share the same register name. 1560 { { "0" }, "r0" }, 1561 { { "1"}, "r1" }, 1562 { { "2" }, "r2" }, 1563 { { "3" }, "r3" }, 1564 { { "4" }, "r4" }, 1565 { { "5" }, "r5" }, 1566 { { "6" }, "r6" }, 1567 { { "7" }, "r7" }, 1568 { { "8" }, "r8" }, 1569 { { "9" }, "r9" }, 1570 { { "10" }, "r10" }, 1571 { { "11" }, "r11" }, 1572 { { "12" }, "r12" }, 1573 { { "13" }, "r13" }, 1574 { { "14" }, "r14" }, 1575 { { "15" }, "r15" }, 1576 { { "16" }, "r16" }, 1577 { { "17" }, "r17" }, 1578 { { "18" }, "r18" }, 1579 { { "19" }, "r19" }, 1580 { { "20" }, "r20" }, 1581 { { "21" }, "r21" }, 1582 { { "22" }, "r22" }, 1583 { { "23" }, "r23" }, 1584 { { "24" }, "r24" }, 1585 { { "25" }, "r25" }, 1586 { { "26" }, "r26" }, 1587 { { "27" }, "r27" }, 1588 { { "28" }, "r28" }, 1589 { { "29" }, "r29" }, 1590 { { "30" }, "r30" }, 1591 { { "31" }, "r31" }, 1592 { { "fr0" }, "f0" }, 1593 { { "fr1" }, "f1" }, 1594 { { "fr2" }, "f2" }, 1595 { { "fr3" }, "f3" }, 1596 { { "fr4" }, "f4" }, 1597 { { "fr5" }, "f5" }, 1598 { { "fr6" }, "f6" }, 1599 { { "fr7" }, "f7" }, 1600 { { "fr8" }, "f8" }, 1601 { { "fr9" }, "f9" }, 1602 { { "fr10" }, "f10" }, 1603 { { "fr11" }, "f11" }, 1604 { { "fr12" }, "f12" }, 1605 { { "fr13" }, "f13" }, 1606 { { "fr14" }, "f14" }, 1607 { { "fr15" }, "f15" }, 1608 { { "fr16" }, "f16" }, 1609 { { "fr17" }, "f17" }, 1610 { { "fr18" }, "f18" }, 1611 { { "fr19" }, "f19" }, 1612 { { "fr20" }, "f20" }, 1613 { { "fr21" }, "f21" }, 1614 { { "fr22" }, "f22" }, 1615 { { "fr23" }, "f23" }, 1616 { { "fr24" }, "f24" }, 1617 { { "fr25" }, "f25" }, 1618 { { "fr26" }, "f26" }, 1619 { { "fr27" }, "f27" }, 1620 { { "fr28" }, "f28" }, 1621 { { "fr29" }, "f29" }, 1622 { { "fr30" }, "f30" }, 1623 { { "fr31" }, "f31" }, 1624 { { "cc" }, "cr0" }, 1625 }; 1626 1627 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1628 return llvm::makeArrayRef(GCCRegAliases); 1629 } 1630 1631 class PPC32TargetInfo : public PPCTargetInfo { 1632 public: 1633 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1634 : PPCTargetInfo(Triple, Opts) { 1635 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1636 1637 switch (getTriple().getOS()) { 1638 case llvm::Triple::Linux: 1639 case llvm::Triple::FreeBSD: 1640 case llvm::Triple::NetBSD: 1641 SizeType = UnsignedInt; 1642 PtrDiffType = SignedInt; 1643 IntPtrType = SignedInt; 1644 break; 1645 default: 1646 break; 1647 } 1648 1649 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1650 LongDoubleWidth = LongDoubleAlign = 64; 1651 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1652 } 1653 1654 // PPC32 supports atomics up to 4 bytes. 1655 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1656 } 1657 1658 BuiltinVaListKind getBuiltinVaListKind() const override { 1659 // This is the ELF definition, and is overridden by the Darwin sub-target 1660 return TargetInfo::PowerABIBuiltinVaList; 1661 } 1662 }; 1663 1664 // Note: ABI differences may eventually require us to have a separate 1665 // TargetInfo for little endian. 1666 class PPC64TargetInfo : public PPCTargetInfo { 1667 public: 1668 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1669 : PPCTargetInfo(Triple, Opts) { 1670 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1671 IntMaxType = SignedLong; 1672 Int64Type = SignedLong; 1673 1674 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1675 resetDataLayout("e-m:e-i64:64-n32:64"); 1676 ABI = "elfv2"; 1677 } else { 1678 resetDataLayout("E-m:e-i64:64-n32:64"); 1679 ABI = "elfv1"; 1680 } 1681 1682 switch (getTriple().getOS()) { 1683 case llvm::Triple::FreeBSD: 1684 LongDoubleWidth = LongDoubleAlign = 64; 1685 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1686 break; 1687 case llvm::Triple::NetBSD: 1688 IntMaxType = SignedLongLong; 1689 Int64Type = SignedLongLong; 1690 break; 1691 default: 1692 break; 1693 } 1694 1695 // PPC64 supports atomics up to 8 bytes. 1696 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1697 } 1698 BuiltinVaListKind getBuiltinVaListKind() const override { 1699 return TargetInfo::CharPtrBuiltinVaList; 1700 } 1701 // PPC64 Linux-specific ABI options. 1702 bool setABI(const std::string &Name) override { 1703 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1704 ABI = Name; 1705 return true; 1706 } 1707 return false; 1708 } 1709 }; 1710 1711 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1712 public: 1713 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1714 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1715 HasAlignMac68kSupport = true; 1716 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1717 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1718 LongLongAlign = 32; 1719 SuitableAlign = 128; 1720 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1721 } 1722 BuiltinVaListKind getBuiltinVaListKind() const override { 1723 return TargetInfo::CharPtrBuiltinVaList; 1724 } 1725 }; 1726 1727 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1728 public: 1729 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1730 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1731 HasAlignMac68kSupport = true; 1732 SuitableAlign = 128; 1733 resetDataLayout("E-m:o-i64:64-n32:64"); 1734 } 1735 }; 1736 1737 static const unsigned NVPTXAddrSpaceMap[] = { 1738 1, // opencl_global 1739 3, // opencl_local 1740 4, // opencl_constant 1741 // FIXME: generic has to be added to the target 1742 0, // opencl_generic 1743 1, // cuda_device 1744 4, // cuda_constant 1745 3, // cuda_shared 1746 }; 1747 1748 class NVPTXTargetInfo : public TargetInfo { 1749 static const char *const GCCRegNames[]; 1750 static const Builtin::Info BuiltinInfo[]; 1751 CudaArch GPU; 1752 1753 public: 1754 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1755 : TargetInfo(Triple) { 1756 TLSSupported = false; 1757 LongWidth = LongAlign = 64; 1758 AddrSpaceMap = &NVPTXAddrSpaceMap; 1759 UseAddrSpaceMapMangling = true; 1760 // Define available target features 1761 // These must be defined in sorted order! 1762 NoAsmVariants = true; 1763 GPU = CudaArch::SM_20; 1764 1765 // If possible, get a TargetInfo for our host triple, so we can match its 1766 // types. 1767 llvm::Triple HostTriple(Opts.HostTriple); 1768 if (HostTriple.isNVPTX()) 1769 return; 1770 std::unique_ptr<TargetInfo> HostTarget( 1771 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1772 if (!HostTarget) { 1773 return; 1774 } 1775 1776 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1777 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1778 BoolWidth = HostTarget->getBoolWidth(); 1779 BoolAlign = HostTarget->getBoolAlign(); 1780 IntWidth = HostTarget->getIntWidth(); 1781 IntAlign = HostTarget->getIntAlign(); 1782 HalfWidth = HostTarget->getHalfWidth(); 1783 HalfAlign = HostTarget->getHalfAlign(); 1784 FloatWidth = HostTarget->getFloatWidth(); 1785 FloatAlign = HostTarget->getFloatAlign(); 1786 DoubleWidth = HostTarget->getDoubleWidth(); 1787 DoubleAlign = HostTarget->getDoubleAlign(); 1788 LongWidth = HostTarget->getLongWidth(); 1789 LongAlign = HostTarget->getLongAlign(); 1790 LongLongWidth = HostTarget->getLongLongWidth(); 1791 LongLongAlign = HostTarget->getLongLongAlign(); 1792 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1793 NewAlign = HostTarget->getNewAlign(); 1794 DefaultAlignForAttributeAligned = 1795 HostTarget->getDefaultAlignForAttributeAligned(); 1796 SizeType = HostTarget->getSizeType(); 1797 IntMaxType = HostTarget->getIntMaxType(); 1798 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1799 IntPtrType = HostTarget->getIntPtrType(); 1800 WCharType = HostTarget->getWCharType(); 1801 WIntType = HostTarget->getWIntType(); 1802 Char16Type = HostTarget->getChar16Type(); 1803 Char32Type = HostTarget->getChar32Type(); 1804 Int64Type = HostTarget->getInt64Type(); 1805 SigAtomicType = HostTarget->getSigAtomicType(); 1806 ProcessIDType = HostTarget->getProcessIDType(); 1807 1808 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1809 UseZeroLengthBitfieldAlignment = 1810 HostTarget->useZeroLengthBitfieldAlignment(); 1811 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1812 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1813 1814 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1815 // we need those macros to be identical on host and device, because (among 1816 // other things) they affect which standard library classes are defined, and 1817 // we need all classes to be defined on both the host and device. 1818 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1819 1820 // Properties intentionally not copied from host: 1821 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1822 // host/device boundary. 1823 // - SuitableAlign: Not visible across the host/device boundary, and may 1824 // correctly be different on host/device, e.g. if host has wider vector 1825 // types than device. 1826 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1827 // as its double type, but that's not necessarily true on the host. 1828 // TODO: nvcc emits a warning when using long double on device; we should 1829 // do the same. 1830 } 1831 void getTargetDefines(const LangOptions &Opts, 1832 MacroBuilder &Builder) const override { 1833 Builder.defineMacro("__PTX__"); 1834 Builder.defineMacro("__NVPTX__"); 1835 if (Opts.CUDAIsDevice) { 1836 // Set __CUDA_ARCH__ for the GPU specified. 1837 std::string CUDAArchCode = [this] { 1838 switch (GPU) { 1839 case CudaArch::UNKNOWN: 1840 assert(false && "No GPU arch when compiling CUDA device code."); 1841 return ""; 1842 case CudaArch::SM_20: 1843 return "200"; 1844 case CudaArch::SM_21: 1845 return "210"; 1846 case CudaArch::SM_30: 1847 return "300"; 1848 case CudaArch::SM_32: 1849 return "320"; 1850 case CudaArch::SM_35: 1851 return "350"; 1852 case CudaArch::SM_37: 1853 return "370"; 1854 case CudaArch::SM_50: 1855 return "500"; 1856 case CudaArch::SM_52: 1857 return "520"; 1858 case CudaArch::SM_53: 1859 return "530"; 1860 case CudaArch::SM_60: 1861 return "600"; 1862 case CudaArch::SM_61: 1863 return "610"; 1864 case CudaArch::SM_62: 1865 return "620"; 1866 } 1867 llvm_unreachable("unhandled CudaArch"); 1868 }(); 1869 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1870 } 1871 } 1872 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1873 return llvm::makeArrayRef(BuiltinInfo, 1874 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1875 } 1876 bool 1877 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1878 StringRef CPU, 1879 const std::vector<std::string> &FeaturesVec) const override { 1880 Features["satom"] = GPU >= CudaArch::SM_60; 1881 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1882 } 1883 1884 bool hasFeature(StringRef Feature) const override { 1885 return llvm::StringSwitch<bool>(Feature) 1886 .Cases("ptx", "nvptx", true) 1887 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1888 .Default(false); 1889 } 1890 1891 ArrayRef<const char *> getGCCRegNames() const override; 1892 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1893 // No aliases. 1894 return None; 1895 } 1896 bool validateAsmConstraint(const char *&Name, 1897 TargetInfo::ConstraintInfo &Info) const override { 1898 switch (*Name) { 1899 default: 1900 return false; 1901 case 'c': 1902 case 'h': 1903 case 'r': 1904 case 'l': 1905 case 'f': 1906 case 'd': 1907 Info.setAllowsRegister(); 1908 return true; 1909 } 1910 } 1911 const char *getClobbers() const override { 1912 // FIXME: Is this really right? 1913 return ""; 1914 } 1915 BuiltinVaListKind getBuiltinVaListKind() const override { 1916 // FIXME: implement 1917 return TargetInfo::CharPtrBuiltinVaList; 1918 } 1919 bool setCPU(const std::string &Name) override { 1920 GPU = StringToCudaArch(Name); 1921 return GPU != CudaArch::UNKNOWN; 1922 } 1923 void setSupportedOpenCLOpts() override { 1924 auto &Opts = getSupportedOpenCLOpts(); 1925 Opts.cl_clang_storage_class_specifiers = 1; 1926 Opts.cl_khr_gl_sharing = 1; 1927 Opts.cl_khr_icd = 1; 1928 1929 Opts.cl_khr_fp64 = 1; 1930 Opts.cl_khr_byte_addressable_store = 1; 1931 Opts.cl_khr_global_int32_base_atomics = 1; 1932 Opts.cl_khr_global_int32_extended_atomics = 1; 1933 Opts.cl_khr_local_int32_base_atomics = 1; 1934 Opts.cl_khr_local_int32_extended_atomics = 1; 1935 } 1936 }; 1937 1938 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1939 #define BUILTIN(ID, TYPE, ATTRS) \ 1940 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1941 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1942 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1943 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 1944 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 1945 #include "clang/Basic/BuiltinsNVPTX.def" 1946 }; 1947 1948 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1949 1950 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1951 return llvm::makeArrayRef(GCCRegNames); 1952 } 1953 1954 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1955 public: 1956 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1957 : NVPTXTargetInfo(Triple, Opts) { 1958 LongWidth = LongAlign = 32; 1959 PointerWidth = PointerAlign = 32; 1960 SizeType = TargetInfo::UnsignedInt; 1961 PtrDiffType = TargetInfo::SignedInt; 1962 IntPtrType = TargetInfo::SignedInt; 1963 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1964 } 1965 }; 1966 1967 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1968 public: 1969 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1970 : NVPTXTargetInfo(Triple, Opts) { 1971 PointerWidth = PointerAlign = 64; 1972 SizeType = TargetInfo::UnsignedLong; 1973 PtrDiffType = TargetInfo::SignedLong; 1974 IntPtrType = TargetInfo::SignedLong; 1975 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1976 } 1977 }; 1978 1979 static const unsigned AMDGPUAddrSpaceMap[] = { 1980 1, // opencl_global 1981 3, // opencl_local 1982 2, // opencl_constant 1983 4, // opencl_generic 1984 1, // cuda_device 1985 2, // cuda_constant 1986 3 // cuda_shared 1987 }; 1988 1989 // If you edit the description strings, make sure you update 1990 // getPointerWidthV(). 1991 1992 static const char *const DataLayoutStringR600 = 1993 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1994 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1995 1996 static const char *const DataLayoutStringSI = 1997 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 1998 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1999 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2000 2001 class AMDGPUTargetInfo final : public TargetInfo { 2002 static const Builtin::Info BuiltinInfo[]; 2003 static const char * const GCCRegNames[]; 2004 2005 /// \brief The GPU profiles supported by the AMDGPU target. 2006 enum GPUKind { 2007 GK_NONE, 2008 GK_R600, 2009 GK_R600_DOUBLE_OPS, 2010 GK_R700, 2011 GK_R700_DOUBLE_OPS, 2012 GK_EVERGREEN, 2013 GK_EVERGREEN_DOUBLE_OPS, 2014 GK_NORTHERN_ISLANDS, 2015 GK_CAYMAN, 2016 GK_GFX6, 2017 GK_GFX7, 2018 GK_GFX8 2019 } GPU; 2020 2021 bool hasFP64:1; 2022 bool hasFMAF:1; 2023 bool hasLDEXPF:1; 2024 bool hasFullSpeedFP32Denorms:1; 2025 2026 static bool isAMDGCN(const llvm::Triple &TT) { 2027 return TT.getArch() == llvm::Triple::amdgcn; 2028 } 2029 2030 public: 2031 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2032 : TargetInfo(Triple) , 2033 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2034 hasFP64(false), 2035 hasFMAF(false), 2036 hasLDEXPF(false), 2037 hasFullSpeedFP32Denorms(false){ 2038 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2039 hasFP64 = true; 2040 hasFMAF = true; 2041 hasLDEXPF = true; 2042 } 2043 2044 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2045 DataLayoutStringSI : DataLayoutStringR600); 2046 2047 AddrSpaceMap = &AMDGPUAddrSpaceMap; 2048 UseAddrSpaceMapMangling = true; 2049 } 2050 2051 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2052 if (GPU <= GK_CAYMAN) 2053 return 32; 2054 2055 switch(AddrSpace) { 2056 default: 2057 return 64; 2058 case 0: 2059 case 3: 2060 case 5: 2061 return 32; 2062 } 2063 } 2064 2065 uint64_t getMaxPointerWidth() const override { 2066 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2067 } 2068 2069 const char * getClobbers() const override { 2070 return ""; 2071 } 2072 2073 ArrayRef<const char *> getGCCRegNames() const override; 2074 2075 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2076 return None; 2077 } 2078 2079 bool validateAsmConstraint(const char *&Name, 2080 TargetInfo::ConstraintInfo &Info) const override { 2081 switch (*Name) { 2082 default: break; 2083 case 'v': // vgpr 2084 case 's': // sgpr 2085 Info.setAllowsRegister(); 2086 return true; 2087 } 2088 return false; 2089 } 2090 2091 bool initFeatureMap(llvm::StringMap<bool> &Features, 2092 DiagnosticsEngine &Diags, StringRef CPU, 2093 const std::vector<std::string> &FeatureVec) const override; 2094 2095 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2096 TargetOptions &TargetOpts) const override { 2097 bool hasFP32Denormals = false; 2098 bool hasFP64Denormals = false; 2099 for (auto &I : TargetOpts.FeaturesAsWritten) { 2100 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2101 hasFP32Denormals = true; 2102 if (I == "+fp64-denormals" || I == "-fp64-denormals") 2103 hasFP64Denormals = true; 2104 } 2105 if (!hasFP32Denormals) 2106 TargetOpts.Features.push_back((Twine(hasFullSpeedFP32Denorms && 2107 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2108 // Always do not flush fp64 denorms. 2109 if (!hasFP64Denormals && hasFP64) 2110 TargetOpts.Features.push_back("+fp64-denormals"); 2111 } 2112 2113 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2114 return llvm::makeArrayRef(BuiltinInfo, 2115 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2116 } 2117 2118 void getTargetDefines(const LangOptions &Opts, 2119 MacroBuilder &Builder) const override { 2120 if (getTriple().getArch() == llvm::Triple::amdgcn) 2121 Builder.defineMacro("__AMDGCN__"); 2122 else 2123 Builder.defineMacro("__R600__"); 2124 2125 if (hasFMAF) 2126 Builder.defineMacro("__HAS_FMAF__"); 2127 if (hasLDEXPF) 2128 Builder.defineMacro("__HAS_LDEXPF__"); 2129 if (hasFP64) 2130 Builder.defineMacro("__HAS_FP64__"); 2131 } 2132 2133 BuiltinVaListKind getBuiltinVaListKind() const override { 2134 return TargetInfo::CharPtrBuiltinVaList; 2135 } 2136 2137 static GPUKind parseR600Name(StringRef Name) { 2138 return llvm::StringSwitch<GPUKind>(Name) 2139 .Case("r600" , GK_R600) 2140 .Case("rv610", GK_R600) 2141 .Case("rv620", GK_R600) 2142 .Case("rv630", GK_R600) 2143 .Case("rv635", GK_R600) 2144 .Case("rs780", GK_R600) 2145 .Case("rs880", GK_R600) 2146 .Case("rv670", GK_R600_DOUBLE_OPS) 2147 .Case("rv710", GK_R700) 2148 .Case("rv730", GK_R700) 2149 .Case("rv740", GK_R700_DOUBLE_OPS) 2150 .Case("rv770", GK_R700_DOUBLE_OPS) 2151 .Case("palm", GK_EVERGREEN) 2152 .Case("cedar", GK_EVERGREEN) 2153 .Case("sumo", GK_EVERGREEN) 2154 .Case("sumo2", GK_EVERGREEN) 2155 .Case("redwood", GK_EVERGREEN) 2156 .Case("juniper", GK_EVERGREEN) 2157 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2158 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2159 .Case("barts", GK_NORTHERN_ISLANDS) 2160 .Case("turks", GK_NORTHERN_ISLANDS) 2161 .Case("caicos", GK_NORTHERN_ISLANDS) 2162 .Case("cayman", GK_CAYMAN) 2163 .Case("aruba", GK_CAYMAN) 2164 .Default(GK_NONE); 2165 } 2166 2167 static GPUKind parseAMDGCNName(StringRef Name) { 2168 return llvm::StringSwitch<GPUKind>(Name) 2169 .Case("tahiti", GK_GFX6) 2170 .Case("pitcairn", GK_GFX6) 2171 .Case("verde", GK_GFX6) 2172 .Case("oland", GK_GFX6) 2173 .Case("hainan", GK_GFX6) 2174 .Case("bonaire", GK_GFX7) 2175 .Case("kabini", GK_GFX7) 2176 .Case("kaveri", GK_GFX7) 2177 .Case("hawaii", GK_GFX7) 2178 .Case("mullins", GK_GFX7) 2179 .Case("tonga", GK_GFX8) 2180 .Case("iceland", GK_GFX8) 2181 .Case("carrizo", GK_GFX8) 2182 .Case("fiji", GK_GFX8) 2183 .Case("stoney", GK_GFX8) 2184 .Case("polaris10", GK_GFX8) 2185 .Case("polaris11", GK_GFX8) 2186 .Default(GK_NONE); 2187 } 2188 2189 bool setCPU(const std::string &Name) override { 2190 if (getTriple().getArch() == llvm::Triple::amdgcn) 2191 GPU = parseAMDGCNName(Name); 2192 else 2193 GPU = parseR600Name(Name); 2194 2195 return GPU != GK_NONE; 2196 } 2197 2198 void setSupportedOpenCLOpts() override { 2199 auto &Opts = getSupportedOpenCLOpts(); 2200 Opts.cl_clang_storage_class_specifiers = 1; 2201 Opts.cl_khr_icd = 1; 2202 2203 if (hasFP64) 2204 Opts.cl_khr_fp64 = 1; 2205 if (GPU >= GK_EVERGREEN) { 2206 Opts.cl_khr_byte_addressable_store = 1; 2207 Opts.cl_khr_global_int32_base_atomics = 1; 2208 Opts.cl_khr_global_int32_extended_atomics = 1; 2209 Opts.cl_khr_local_int32_base_atomics = 1; 2210 Opts.cl_khr_local_int32_extended_atomics = 1; 2211 } 2212 if (GPU >= GK_GFX6) { 2213 Opts.cl_khr_fp16 = 1; 2214 Opts.cl_khr_int64_base_atomics = 1; 2215 Opts.cl_khr_int64_extended_atomics = 1; 2216 Opts.cl_khr_mipmap_image = 1; 2217 Opts.cl_khr_subgroups = 1; 2218 Opts.cl_khr_3d_image_writes = 1; 2219 Opts.cl_amd_media_ops = 1; 2220 Opts.cl_amd_media_ops2 = 1; 2221 } 2222 } 2223 2224 LangAS::ID getOpenCLImageAddrSpace() const override { 2225 return LangAS::opencl_constant; 2226 } 2227 2228 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2229 switch (CC) { 2230 default: 2231 return CCCR_Warning; 2232 case CC_C: 2233 case CC_OpenCLKernel: 2234 return CCCR_OK; 2235 } 2236 } 2237 }; 2238 2239 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2240 #define BUILTIN(ID, TYPE, ATTRS) \ 2241 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2242 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2243 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2244 #include "clang/Basic/BuiltinsAMDGPU.def" 2245 }; 2246 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2247 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2248 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2249 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2250 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2251 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2252 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2253 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2254 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2255 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2256 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2257 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2258 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2259 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2260 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2261 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2262 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2263 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2264 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2265 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2266 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2267 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2268 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2269 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2270 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2271 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2272 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2273 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2274 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2275 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2276 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2277 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2278 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2279 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2280 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2281 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2282 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2283 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2284 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2285 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2286 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2287 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2288 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2289 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2290 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2291 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2292 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2293 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2294 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2295 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2296 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2297 }; 2298 2299 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2300 return llvm::makeArrayRef(GCCRegNames); 2301 } 2302 2303 bool AMDGPUTargetInfo::initFeatureMap( 2304 llvm::StringMap<bool> &Features, 2305 DiagnosticsEngine &Diags, StringRef CPU, 2306 const std::vector<std::string> &FeatureVec) const { 2307 2308 // XXX - What does the member GPU mean if device name string passed here? 2309 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2310 if (CPU.empty()) 2311 CPU = "tahiti"; 2312 2313 switch (parseAMDGCNName(CPU)) { 2314 case GK_GFX6: 2315 case GK_GFX7: 2316 break; 2317 2318 case GK_GFX8: 2319 Features["s-memrealtime"] = true; 2320 Features["16-bit-insts"] = true; 2321 break; 2322 2323 case GK_NONE: 2324 return false; 2325 default: 2326 llvm_unreachable("unhandled subtarget"); 2327 } 2328 } else { 2329 if (CPU.empty()) 2330 CPU = "r600"; 2331 2332 switch (parseR600Name(CPU)) { 2333 case GK_R600: 2334 case GK_R700: 2335 case GK_EVERGREEN: 2336 case GK_NORTHERN_ISLANDS: 2337 break; 2338 case GK_R600_DOUBLE_OPS: 2339 case GK_R700_DOUBLE_OPS: 2340 case GK_EVERGREEN_DOUBLE_OPS: 2341 case GK_CAYMAN: 2342 Features["fp64"] = true; 2343 break; 2344 case GK_NONE: 2345 return false; 2346 default: 2347 llvm_unreachable("unhandled subtarget"); 2348 } 2349 } 2350 2351 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2352 } 2353 2354 const Builtin::Info BuiltinInfoX86[] = { 2355 #define BUILTIN(ID, TYPE, ATTRS) \ 2356 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2357 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2358 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2359 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2360 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2361 #include "clang/Basic/BuiltinsX86.def" 2362 2363 #define BUILTIN(ID, TYPE, ATTRS) \ 2364 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2365 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2366 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2367 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2368 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2369 #include "clang/Basic/BuiltinsX86_64.def" 2370 }; 2371 2372 2373 static const char* const GCCRegNames[] = { 2374 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2375 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2376 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2377 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2378 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2379 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2380 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2381 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2382 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2383 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2384 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2385 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2386 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2387 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2388 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2389 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2390 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2391 }; 2392 2393 const TargetInfo::AddlRegName AddlRegNames[] = { 2394 { { "al", "ah", "eax", "rax" }, 0 }, 2395 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2396 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2397 { { "dl", "dh", "edx", "rdx" }, 1 }, 2398 { { "esi", "rsi" }, 4 }, 2399 { { "edi", "rdi" }, 5 }, 2400 { { "esp", "rsp" }, 7 }, 2401 { { "ebp", "rbp" }, 6 }, 2402 { { "r8d", "r8w", "r8b" }, 38 }, 2403 { { "r9d", "r9w", "r9b" }, 39 }, 2404 { { "r10d", "r10w", "r10b" }, 40 }, 2405 { { "r11d", "r11w", "r11b" }, 41 }, 2406 { { "r12d", "r12w", "r12b" }, 42 }, 2407 { { "r13d", "r13w", "r13b" }, 43 }, 2408 { { "r14d", "r14w", "r14b" }, 44 }, 2409 { { "r15d", "r15w", "r15b" }, 45 }, 2410 }; 2411 2412 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2413 // most of the implementation can be shared. 2414 class X86TargetInfo : public TargetInfo { 2415 enum X86SSEEnum { 2416 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2417 } SSELevel = NoSSE; 2418 enum MMX3DNowEnum { 2419 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2420 } MMX3DNowLevel = NoMMX3DNow; 2421 enum XOPEnum { 2422 NoXOP, 2423 SSE4A, 2424 FMA4, 2425 XOP 2426 } XOPLevel = NoXOP; 2427 2428 bool HasAES = false; 2429 bool HasPCLMUL = false; 2430 bool HasLZCNT = false; 2431 bool HasRDRND = false; 2432 bool HasFSGSBASE = false; 2433 bool HasBMI = false; 2434 bool HasBMI2 = false; 2435 bool HasPOPCNT = false; 2436 bool HasRTM = false; 2437 bool HasPRFCHW = false; 2438 bool HasRDSEED = false; 2439 bool HasADX = false; 2440 bool HasTBM = false; 2441 bool HasFMA = false; 2442 bool HasF16C = false; 2443 bool HasAVX512CD = false; 2444 bool HasAVX512ER = false; 2445 bool HasAVX512PF = false; 2446 bool HasAVX512DQ = false; 2447 bool HasAVX512BW = false; 2448 bool HasAVX512VL = false; 2449 bool HasAVX512VBMI = false; 2450 bool HasAVX512IFMA = false; 2451 bool HasSHA = false; 2452 bool HasMPX = false; 2453 bool HasSGX = false; 2454 bool HasCX16 = false; 2455 bool HasFXSR = false; 2456 bool HasXSAVE = false; 2457 bool HasXSAVEOPT = false; 2458 bool HasXSAVEC = false; 2459 bool HasXSAVES = false; 2460 bool HasMWAITX = false; 2461 bool HasPKU = false; 2462 bool HasCLFLUSHOPT = false; 2463 bool HasPCOMMIT = false; 2464 bool HasCLWB = false; 2465 bool HasUMIP = false; 2466 bool HasMOVBE = false; 2467 bool HasPREFETCHWT1 = false; 2468 2469 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2470 /// 2471 /// Each enumeration represents a particular CPU supported by Clang. These 2472 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2473 enum CPUKind { 2474 CK_Generic, 2475 2476 /// \name i386 2477 /// i386-generation processors. 2478 //@{ 2479 CK_i386, 2480 //@} 2481 2482 /// \name i486 2483 /// i486-generation processors. 2484 //@{ 2485 CK_i486, 2486 CK_WinChipC6, 2487 CK_WinChip2, 2488 CK_C3, 2489 //@} 2490 2491 /// \name i586 2492 /// i586-generation processors, P5 microarchitecture based. 2493 //@{ 2494 CK_i586, 2495 CK_Pentium, 2496 CK_PentiumMMX, 2497 //@} 2498 2499 /// \name i686 2500 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2501 //@{ 2502 CK_i686, 2503 CK_PentiumPro, 2504 CK_Pentium2, 2505 CK_Pentium3, 2506 CK_Pentium3M, 2507 CK_PentiumM, 2508 CK_C3_2, 2509 2510 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2511 /// Clang however has some logic to suport this. 2512 // FIXME: Warn, deprecate, and potentially remove this. 2513 CK_Yonah, 2514 //@} 2515 2516 /// \name Netburst 2517 /// Netburst microarchitecture based processors. 2518 //@{ 2519 CK_Pentium4, 2520 CK_Pentium4M, 2521 CK_Prescott, 2522 CK_Nocona, 2523 //@} 2524 2525 /// \name Core 2526 /// Core microarchitecture based processors. 2527 //@{ 2528 CK_Core2, 2529 2530 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2531 /// codename which GCC no longer accepts as an option to -march, but Clang 2532 /// has some logic for recognizing it. 2533 // FIXME: Warn, deprecate, and potentially remove this. 2534 CK_Penryn, 2535 //@} 2536 2537 /// \name Atom 2538 /// Atom processors 2539 //@{ 2540 CK_Bonnell, 2541 CK_Silvermont, 2542 //@} 2543 2544 /// \name Nehalem 2545 /// Nehalem microarchitecture based processors. 2546 CK_Nehalem, 2547 2548 /// \name Westmere 2549 /// Westmere microarchitecture based processors. 2550 CK_Westmere, 2551 2552 /// \name Sandy Bridge 2553 /// Sandy Bridge microarchitecture based processors. 2554 CK_SandyBridge, 2555 2556 /// \name Ivy Bridge 2557 /// Ivy Bridge microarchitecture based processors. 2558 CK_IvyBridge, 2559 2560 /// \name Haswell 2561 /// Haswell microarchitecture based processors. 2562 CK_Haswell, 2563 2564 /// \name Broadwell 2565 /// Broadwell microarchitecture based processors. 2566 CK_Broadwell, 2567 2568 /// \name Skylake Client 2569 /// Skylake client microarchitecture based processors. 2570 CK_SkylakeClient, 2571 2572 /// \name Skylake Server 2573 /// Skylake server microarchitecture based processors. 2574 CK_SkylakeServer, 2575 2576 /// \name Cannonlake Client 2577 /// Cannonlake client microarchitecture based processors. 2578 CK_Cannonlake, 2579 2580 /// \name Knights Landing 2581 /// Knights Landing processor. 2582 CK_KNL, 2583 2584 /// \name Lakemont 2585 /// Lakemont microarchitecture based processors. 2586 CK_Lakemont, 2587 2588 /// \name K6 2589 /// K6 architecture processors. 2590 //@{ 2591 CK_K6, 2592 CK_K6_2, 2593 CK_K6_3, 2594 //@} 2595 2596 /// \name K7 2597 /// K7 architecture processors. 2598 //@{ 2599 CK_Athlon, 2600 CK_AthlonThunderbird, 2601 CK_Athlon4, 2602 CK_AthlonXP, 2603 CK_AthlonMP, 2604 //@} 2605 2606 /// \name K8 2607 /// K8 architecture processors. 2608 //@{ 2609 CK_Athlon64, 2610 CK_Athlon64SSE3, 2611 CK_AthlonFX, 2612 CK_K8, 2613 CK_K8SSE3, 2614 CK_Opteron, 2615 CK_OpteronSSE3, 2616 CK_AMDFAM10, 2617 //@} 2618 2619 /// \name Bobcat 2620 /// Bobcat architecture processors. 2621 //@{ 2622 CK_BTVER1, 2623 CK_BTVER2, 2624 //@} 2625 2626 /// \name Bulldozer 2627 /// Bulldozer architecture processors. 2628 //@{ 2629 CK_BDVER1, 2630 CK_BDVER2, 2631 CK_BDVER3, 2632 CK_BDVER4, 2633 //@} 2634 2635 /// This specification is deprecated and will be removed in the future. 2636 /// Users should prefer \see CK_K8. 2637 // FIXME: Warn on this when the CPU is set to it. 2638 //@{ 2639 CK_x86_64, 2640 //@} 2641 2642 /// \name Geode 2643 /// Geode processors. 2644 //@{ 2645 CK_Geode 2646 //@} 2647 } CPU = CK_Generic; 2648 2649 CPUKind getCPUKind(StringRef CPU) const { 2650 return llvm::StringSwitch<CPUKind>(CPU) 2651 .Case("i386", CK_i386) 2652 .Case("i486", CK_i486) 2653 .Case("winchip-c6", CK_WinChipC6) 2654 .Case("winchip2", CK_WinChip2) 2655 .Case("c3", CK_C3) 2656 .Case("i586", CK_i586) 2657 .Case("pentium", CK_Pentium) 2658 .Case("pentium-mmx", CK_PentiumMMX) 2659 .Case("i686", CK_i686) 2660 .Case("pentiumpro", CK_PentiumPro) 2661 .Case("pentium2", CK_Pentium2) 2662 .Case("pentium3", CK_Pentium3) 2663 .Case("pentium3m", CK_Pentium3M) 2664 .Case("pentium-m", CK_PentiumM) 2665 .Case("c3-2", CK_C3_2) 2666 .Case("yonah", CK_Yonah) 2667 .Case("pentium4", CK_Pentium4) 2668 .Case("pentium4m", CK_Pentium4M) 2669 .Case("prescott", CK_Prescott) 2670 .Case("nocona", CK_Nocona) 2671 .Case("core2", CK_Core2) 2672 .Case("penryn", CK_Penryn) 2673 .Case("bonnell", CK_Bonnell) 2674 .Case("atom", CK_Bonnell) // Legacy name. 2675 .Case("silvermont", CK_Silvermont) 2676 .Case("slm", CK_Silvermont) // Legacy name. 2677 .Case("nehalem", CK_Nehalem) 2678 .Case("corei7", CK_Nehalem) // Legacy name. 2679 .Case("westmere", CK_Westmere) 2680 .Case("sandybridge", CK_SandyBridge) 2681 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2682 .Case("ivybridge", CK_IvyBridge) 2683 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2684 .Case("haswell", CK_Haswell) 2685 .Case("core-avx2", CK_Haswell) // Legacy name. 2686 .Case("broadwell", CK_Broadwell) 2687 .Case("skylake", CK_SkylakeClient) 2688 .Case("skylake-avx512", CK_SkylakeServer) 2689 .Case("skx", CK_SkylakeServer) // Legacy name. 2690 .Case("cannonlake", CK_Cannonlake) 2691 .Case("knl", CK_KNL) 2692 .Case("lakemont", CK_Lakemont) 2693 .Case("k6", CK_K6) 2694 .Case("k6-2", CK_K6_2) 2695 .Case("k6-3", CK_K6_3) 2696 .Case("athlon", CK_Athlon) 2697 .Case("athlon-tbird", CK_AthlonThunderbird) 2698 .Case("athlon-4", CK_Athlon4) 2699 .Case("athlon-xp", CK_AthlonXP) 2700 .Case("athlon-mp", CK_AthlonMP) 2701 .Case("athlon64", CK_Athlon64) 2702 .Case("athlon64-sse3", CK_Athlon64SSE3) 2703 .Case("athlon-fx", CK_AthlonFX) 2704 .Case("k8", CK_K8) 2705 .Case("k8-sse3", CK_K8SSE3) 2706 .Case("opteron", CK_Opteron) 2707 .Case("opteron-sse3", CK_OpteronSSE3) 2708 .Case("barcelona", CK_AMDFAM10) 2709 .Case("amdfam10", CK_AMDFAM10) 2710 .Case("btver1", CK_BTVER1) 2711 .Case("btver2", CK_BTVER2) 2712 .Case("bdver1", CK_BDVER1) 2713 .Case("bdver2", CK_BDVER2) 2714 .Case("bdver3", CK_BDVER3) 2715 .Case("bdver4", CK_BDVER4) 2716 .Case("x86-64", CK_x86_64) 2717 .Case("geode", CK_Geode) 2718 .Default(CK_Generic); 2719 } 2720 2721 enum FPMathKind { 2722 FP_Default, 2723 FP_SSE, 2724 FP_387 2725 } FPMath = FP_Default; 2726 2727 public: 2728 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2729 : TargetInfo(Triple) { 2730 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2731 } 2732 unsigned getFloatEvalMethod() const override { 2733 // X87 evaluates with 80 bits "long double" precision. 2734 return SSELevel == NoSSE ? 2 : 0; 2735 } 2736 ArrayRef<const char *> getGCCRegNames() const override { 2737 return llvm::makeArrayRef(GCCRegNames); 2738 } 2739 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2740 return None; 2741 } 2742 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2743 return llvm::makeArrayRef(AddlRegNames); 2744 } 2745 bool validateCpuSupports(StringRef Name) const override; 2746 bool validateAsmConstraint(const char *&Name, 2747 TargetInfo::ConstraintInfo &info) const override; 2748 2749 bool validateGlobalRegisterVariable(StringRef RegName, 2750 unsigned RegSize, 2751 bool &HasSizeMismatch) const override { 2752 // esp and ebp are the only 32-bit registers the x86 backend can currently 2753 // handle. 2754 if (RegName.equals("esp") || RegName.equals("ebp")) { 2755 // Check that the register size is 32-bit. 2756 HasSizeMismatch = RegSize != 32; 2757 return true; 2758 } 2759 2760 return false; 2761 } 2762 2763 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2764 2765 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2766 2767 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2768 2769 std::string convertConstraint(const char *&Constraint) const override; 2770 const char *getClobbers() const override { 2771 return "~{dirflag},~{fpsr},~{flags}"; 2772 } 2773 void getTargetDefines(const LangOptions &Opts, 2774 MacroBuilder &Builder) const override; 2775 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2776 bool Enabled); 2777 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2778 bool Enabled); 2779 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2780 bool Enabled); 2781 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2782 StringRef Name, bool Enabled) const override { 2783 setFeatureEnabledImpl(Features, Name, Enabled); 2784 } 2785 // This exists purely to cut down on the number of virtual calls in 2786 // initFeatureMap which calls this repeatedly. 2787 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2788 StringRef Name, bool Enabled); 2789 bool 2790 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2791 StringRef CPU, 2792 const std::vector<std::string> &FeaturesVec) const override; 2793 bool hasFeature(StringRef Feature) const override; 2794 bool handleTargetFeatures(std::vector<std::string> &Features, 2795 DiagnosticsEngine &Diags) override; 2796 StringRef getABI() const override { 2797 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2798 return "avx512"; 2799 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2800 return "avx"; 2801 if (getTriple().getArch() == llvm::Triple::x86 && 2802 MMX3DNowLevel == NoMMX3DNow) 2803 return "no-mmx"; 2804 return ""; 2805 } 2806 bool setCPU(const std::string &Name) override { 2807 CPU = getCPUKind(Name); 2808 2809 // Perform any per-CPU checks necessary to determine if this CPU is 2810 // acceptable. 2811 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2812 // invalid without explaining *why*. 2813 switch (CPU) { 2814 case CK_Generic: 2815 // No processor selected! 2816 return false; 2817 2818 case CK_i386: 2819 case CK_i486: 2820 case CK_WinChipC6: 2821 case CK_WinChip2: 2822 case CK_C3: 2823 case CK_i586: 2824 case CK_Pentium: 2825 case CK_PentiumMMX: 2826 case CK_i686: 2827 case CK_PentiumPro: 2828 case CK_Pentium2: 2829 case CK_Pentium3: 2830 case CK_Pentium3M: 2831 case CK_PentiumM: 2832 case CK_Yonah: 2833 case CK_C3_2: 2834 case CK_Pentium4: 2835 case CK_Pentium4M: 2836 case CK_Lakemont: 2837 case CK_Prescott: 2838 case CK_K6: 2839 case CK_K6_2: 2840 case CK_K6_3: 2841 case CK_Athlon: 2842 case CK_AthlonThunderbird: 2843 case CK_Athlon4: 2844 case CK_AthlonXP: 2845 case CK_AthlonMP: 2846 case CK_Geode: 2847 // Only accept certain architectures when compiling in 32-bit mode. 2848 if (getTriple().getArch() != llvm::Triple::x86) 2849 return false; 2850 2851 // Fallthrough 2852 case CK_Nocona: 2853 case CK_Core2: 2854 case CK_Penryn: 2855 case CK_Bonnell: 2856 case CK_Silvermont: 2857 case CK_Nehalem: 2858 case CK_Westmere: 2859 case CK_SandyBridge: 2860 case CK_IvyBridge: 2861 case CK_Haswell: 2862 case CK_Broadwell: 2863 case CK_SkylakeClient: 2864 case CK_SkylakeServer: 2865 case CK_Cannonlake: 2866 case CK_KNL: 2867 case CK_Athlon64: 2868 case CK_Athlon64SSE3: 2869 case CK_AthlonFX: 2870 case CK_K8: 2871 case CK_K8SSE3: 2872 case CK_Opteron: 2873 case CK_OpteronSSE3: 2874 case CK_AMDFAM10: 2875 case CK_BTVER1: 2876 case CK_BTVER2: 2877 case CK_BDVER1: 2878 case CK_BDVER2: 2879 case CK_BDVER3: 2880 case CK_BDVER4: 2881 case CK_x86_64: 2882 return true; 2883 } 2884 llvm_unreachable("Unhandled CPU kind"); 2885 } 2886 2887 bool setFPMath(StringRef Name) override; 2888 2889 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2890 // Most of the non-ARM calling conventions are i386 conventions. 2891 switch (CC) { 2892 case CC_X86ThisCall: 2893 case CC_X86FastCall: 2894 case CC_X86StdCall: 2895 case CC_X86VectorCall: 2896 case CC_C: 2897 case CC_Swift: 2898 case CC_X86Pascal: 2899 case CC_IntelOclBicc: 2900 return CCCR_OK; 2901 default: 2902 return CCCR_Warning; 2903 } 2904 } 2905 2906 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2907 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2908 } 2909 2910 bool hasSjLjLowering() const override { 2911 return true; 2912 } 2913 2914 void setSupportedOpenCLOpts() override { 2915 getSupportedOpenCLOpts().setAll(); 2916 } 2917 }; 2918 2919 bool X86TargetInfo::setFPMath(StringRef Name) { 2920 if (Name == "387") { 2921 FPMath = FP_387; 2922 return true; 2923 } 2924 if (Name == "sse") { 2925 FPMath = FP_SSE; 2926 return true; 2927 } 2928 return false; 2929 } 2930 2931 bool X86TargetInfo::initFeatureMap( 2932 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2933 const std::vector<std::string> &FeaturesVec) const { 2934 // FIXME: This *really* should not be here. 2935 // X86_64 always has SSE2. 2936 if (getTriple().getArch() == llvm::Triple::x86_64) 2937 setFeatureEnabledImpl(Features, "sse2", true); 2938 2939 const CPUKind Kind = getCPUKind(CPU); 2940 2941 // Enable X87 for all X86 processors but Lakemont. 2942 if (Kind != CK_Lakemont) 2943 setFeatureEnabledImpl(Features, "x87", true); 2944 2945 switch (Kind) { 2946 case CK_Generic: 2947 case CK_i386: 2948 case CK_i486: 2949 case CK_i586: 2950 case CK_Pentium: 2951 case CK_i686: 2952 case CK_PentiumPro: 2953 case CK_Lakemont: 2954 break; 2955 case CK_PentiumMMX: 2956 case CK_Pentium2: 2957 case CK_K6: 2958 case CK_WinChipC6: 2959 setFeatureEnabledImpl(Features, "mmx", true); 2960 break; 2961 case CK_Pentium3: 2962 case CK_Pentium3M: 2963 case CK_C3_2: 2964 setFeatureEnabledImpl(Features, "sse", true); 2965 setFeatureEnabledImpl(Features, "fxsr", true); 2966 break; 2967 case CK_PentiumM: 2968 case CK_Pentium4: 2969 case CK_Pentium4M: 2970 case CK_x86_64: 2971 setFeatureEnabledImpl(Features, "sse2", true); 2972 setFeatureEnabledImpl(Features, "fxsr", true); 2973 break; 2974 case CK_Yonah: 2975 case CK_Prescott: 2976 case CK_Nocona: 2977 setFeatureEnabledImpl(Features, "sse3", true); 2978 setFeatureEnabledImpl(Features, "fxsr", true); 2979 setFeatureEnabledImpl(Features, "cx16", true); 2980 break; 2981 case CK_Core2: 2982 case CK_Bonnell: 2983 setFeatureEnabledImpl(Features, "ssse3", true); 2984 setFeatureEnabledImpl(Features, "fxsr", true); 2985 setFeatureEnabledImpl(Features, "cx16", true); 2986 break; 2987 case CK_Penryn: 2988 setFeatureEnabledImpl(Features, "sse4.1", true); 2989 setFeatureEnabledImpl(Features, "fxsr", true); 2990 setFeatureEnabledImpl(Features, "cx16", true); 2991 break; 2992 case CK_Cannonlake: 2993 setFeatureEnabledImpl(Features, "avx512ifma", true); 2994 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2995 setFeatureEnabledImpl(Features, "sha", true); 2996 setFeatureEnabledImpl(Features, "umip", true); 2997 // FALLTHROUGH 2998 case CK_SkylakeServer: 2999 setFeatureEnabledImpl(Features, "avx512f", true); 3000 setFeatureEnabledImpl(Features, "avx512cd", true); 3001 setFeatureEnabledImpl(Features, "avx512dq", true); 3002 setFeatureEnabledImpl(Features, "avx512bw", true); 3003 setFeatureEnabledImpl(Features, "avx512vl", true); 3004 setFeatureEnabledImpl(Features, "pku", true); 3005 setFeatureEnabledImpl(Features, "pcommit", true); 3006 setFeatureEnabledImpl(Features, "clwb", true); 3007 // FALLTHROUGH 3008 case CK_SkylakeClient: 3009 setFeatureEnabledImpl(Features, "xsavec", true); 3010 setFeatureEnabledImpl(Features, "xsaves", true); 3011 setFeatureEnabledImpl(Features, "mpx", true); 3012 setFeatureEnabledImpl(Features, "sgx", true); 3013 setFeatureEnabledImpl(Features, "clflushopt", true); 3014 // FALLTHROUGH 3015 case CK_Broadwell: 3016 setFeatureEnabledImpl(Features, "rdseed", true); 3017 setFeatureEnabledImpl(Features, "adx", true); 3018 // FALLTHROUGH 3019 case CK_Haswell: 3020 setFeatureEnabledImpl(Features, "avx2", true); 3021 setFeatureEnabledImpl(Features, "lzcnt", true); 3022 setFeatureEnabledImpl(Features, "bmi", true); 3023 setFeatureEnabledImpl(Features, "bmi2", true); 3024 setFeatureEnabledImpl(Features, "rtm", true); 3025 setFeatureEnabledImpl(Features, "fma", true); 3026 setFeatureEnabledImpl(Features, "movbe", true); 3027 // FALLTHROUGH 3028 case CK_IvyBridge: 3029 setFeatureEnabledImpl(Features, "rdrnd", true); 3030 setFeatureEnabledImpl(Features, "f16c", true); 3031 setFeatureEnabledImpl(Features, "fsgsbase", true); 3032 // FALLTHROUGH 3033 case CK_SandyBridge: 3034 setFeatureEnabledImpl(Features, "avx", true); 3035 setFeatureEnabledImpl(Features, "xsave", true); 3036 setFeatureEnabledImpl(Features, "xsaveopt", true); 3037 // FALLTHROUGH 3038 case CK_Westmere: 3039 case CK_Silvermont: 3040 setFeatureEnabledImpl(Features, "aes", true); 3041 setFeatureEnabledImpl(Features, "pclmul", true); 3042 // FALLTHROUGH 3043 case CK_Nehalem: 3044 setFeatureEnabledImpl(Features, "sse4.2", true); 3045 setFeatureEnabledImpl(Features, "fxsr", true); 3046 setFeatureEnabledImpl(Features, "cx16", true); 3047 break; 3048 case CK_KNL: 3049 setFeatureEnabledImpl(Features, "avx512f", true); 3050 setFeatureEnabledImpl(Features, "avx512cd", true); 3051 setFeatureEnabledImpl(Features, "avx512er", true); 3052 setFeatureEnabledImpl(Features, "avx512pf", true); 3053 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3054 setFeatureEnabledImpl(Features, "fxsr", true); 3055 setFeatureEnabledImpl(Features, "rdseed", true); 3056 setFeatureEnabledImpl(Features, "adx", true); 3057 setFeatureEnabledImpl(Features, "lzcnt", true); 3058 setFeatureEnabledImpl(Features, "bmi", true); 3059 setFeatureEnabledImpl(Features, "bmi2", true); 3060 setFeatureEnabledImpl(Features, "rtm", true); 3061 setFeatureEnabledImpl(Features, "fma", true); 3062 setFeatureEnabledImpl(Features, "rdrnd", true); 3063 setFeatureEnabledImpl(Features, "f16c", true); 3064 setFeatureEnabledImpl(Features, "fsgsbase", true); 3065 setFeatureEnabledImpl(Features, "aes", true); 3066 setFeatureEnabledImpl(Features, "pclmul", true); 3067 setFeatureEnabledImpl(Features, "cx16", true); 3068 setFeatureEnabledImpl(Features, "xsaveopt", true); 3069 setFeatureEnabledImpl(Features, "xsave", true); 3070 setFeatureEnabledImpl(Features, "movbe", true); 3071 break; 3072 case CK_K6_2: 3073 case CK_K6_3: 3074 case CK_WinChip2: 3075 case CK_C3: 3076 setFeatureEnabledImpl(Features, "3dnow", true); 3077 break; 3078 case CK_Athlon: 3079 case CK_AthlonThunderbird: 3080 case CK_Geode: 3081 setFeatureEnabledImpl(Features, "3dnowa", true); 3082 break; 3083 case CK_Athlon4: 3084 case CK_AthlonXP: 3085 case CK_AthlonMP: 3086 setFeatureEnabledImpl(Features, "sse", true); 3087 setFeatureEnabledImpl(Features, "3dnowa", true); 3088 setFeatureEnabledImpl(Features, "fxsr", true); 3089 break; 3090 case CK_K8: 3091 case CK_Opteron: 3092 case CK_Athlon64: 3093 case CK_AthlonFX: 3094 setFeatureEnabledImpl(Features, "sse2", true); 3095 setFeatureEnabledImpl(Features, "3dnowa", true); 3096 setFeatureEnabledImpl(Features, "fxsr", true); 3097 break; 3098 case CK_AMDFAM10: 3099 setFeatureEnabledImpl(Features, "sse4a", true); 3100 setFeatureEnabledImpl(Features, "lzcnt", true); 3101 setFeatureEnabledImpl(Features, "popcnt", true); 3102 // FALLTHROUGH 3103 case CK_K8SSE3: 3104 case CK_OpteronSSE3: 3105 case CK_Athlon64SSE3: 3106 setFeatureEnabledImpl(Features, "sse3", true); 3107 setFeatureEnabledImpl(Features, "3dnowa", true); 3108 setFeatureEnabledImpl(Features, "fxsr", true); 3109 break; 3110 case CK_BTVER2: 3111 setFeatureEnabledImpl(Features, "avx", true); 3112 setFeatureEnabledImpl(Features, "aes", true); 3113 setFeatureEnabledImpl(Features, "pclmul", true); 3114 setFeatureEnabledImpl(Features, "bmi", true); 3115 setFeatureEnabledImpl(Features, "f16c", true); 3116 setFeatureEnabledImpl(Features, "xsaveopt", true); 3117 // FALLTHROUGH 3118 case CK_BTVER1: 3119 setFeatureEnabledImpl(Features, "ssse3", true); 3120 setFeatureEnabledImpl(Features, "sse4a", true); 3121 setFeatureEnabledImpl(Features, "lzcnt", true); 3122 setFeatureEnabledImpl(Features, "popcnt", true); 3123 setFeatureEnabledImpl(Features, "prfchw", true); 3124 setFeatureEnabledImpl(Features, "cx16", true); 3125 setFeatureEnabledImpl(Features, "fxsr", true); 3126 break; 3127 case CK_BDVER4: 3128 setFeatureEnabledImpl(Features, "avx2", true); 3129 setFeatureEnabledImpl(Features, "bmi2", true); 3130 setFeatureEnabledImpl(Features, "mwaitx", true); 3131 // FALLTHROUGH 3132 case CK_BDVER3: 3133 setFeatureEnabledImpl(Features, "fsgsbase", true); 3134 setFeatureEnabledImpl(Features, "xsaveopt", true); 3135 // FALLTHROUGH 3136 case CK_BDVER2: 3137 setFeatureEnabledImpl(Features, "bmi", true); 3138 setFeatureEnabledImpl(Features, "fma", true); 3139 setFeatureEnabledImpl(Features, "f16c", true); 3140 setFeatureEnabledImpl(Features, "tbm", true); 3141 // FALLTHROUGH 3142 case CK_BDVER1: 3143 // xop implies avx, sse4a and fma4. 3144 setFeatureEnabledImpl(Features, "xop", true); 3145 setFeatureEnabledImpl(Features, "lzcnt", true); 3146 setFeatureEnabledImpl(Features, "aes", true); 3147 setFeatureEnabledImpl(Features, "pclmul", true); 3148 setFeatureEnabledImpl(Features, "prfchw", true); 3149 setFeatureEnabledImpl(Features, "cx16", true); 3150 setFeatureEnabledImpl(Features, "fxsr", true); 3151 setFeatureEnabledImpl(Features, "xsave", true); 3152 break; 3153 } 3154 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3155 return false; 3156 3157 // Can't do this earlier because we need to be able to explicitly enable 3158 // or disable these features and the things that they depend upon. 3159 3160 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3161 auto I = Features.find("sse4.2"); 3162 if (I != Features.end() && I->getValue() && 3163 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3164 FeaturesVec.end()) 3165 Features["popcnt"] = true; 3166 3167 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3168 I = Features.find("3dnow"); 3169 if (I != Features.end() && I->getValue() && 3170 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3171 FeaturesVec.end()) 3172 Features["prfchw"] = true; 3173 3174 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3175 // then enable MMX. 3176 I = Features.find("sse"); 3177 if (I != Features.end() && I->getValue() && 3178 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3179 FeaturesVec.end()) 3180 Features["mmx"] = true; 3181 3182 return true; 3183 } 3184 3185 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3186 X86SSEEnum Level, bool Enabled) { 3187 if (Enabled) { 3188 switch (Level) { 3189 case AVX512F: 3190 Features["avx512f"] = true; 3191 case AVX2: 3192 Features["avx2"] = true; 3193 case AVX: 3194 Features["avx"] = true; 3195 Features["xsave"] = true; 3196 case SSE42: 3197 Features["sse4.2"] = true; 3198 case SSE41: 3199 Features["sse4.1"] = true; 3200 case SSSE3: 3201 Features["ssse3"] = true; 3202 case SSE3: 3203 Features["sse3"] = true; 3204 case SSE2: 3205 Features["sse2"] = true; 3206 case SSE1: 3207 Features["sse"] = true; 3208 case NoSSE: 3209 break; 3210 } 3211 return; 3212 } 3213 3214 switch (Level) { 3215 case NoSSE: 3216 case SSE1: 3217 Features["sse"] = false; 3218 case SSE2: 3219 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3220 Features["sha"] = false; 3221 case SSE3: 3222 Features["sse3"] = false; 3223 setXOPLevel(Features, NoXOP, false); 3224 case SSSE3: 3225 Features["ssse3"] = false; 3226 case SSE41: 3227 Features["sse4.1"] = false; 3228 case SSE42: 3229 Features["sse4.2"] = false; 3230 case AVX: 3231 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3232 Features["xsaveopt"] = false; 3233 setXOPLevel(Features, FMA4, false); 3234 case AVX2: 3235 Features["avx2"] = false; 3236 case AVX512F: 3237 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3238 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3239 Features["avx512vl"] = Features["avx512vbmi"] = 3240 Features["avx512ifma"] = false; 3241 } 3242 } 3243 3244 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3245 MMX3DNowEnum Level, bool Enabled) { 3246 if (Enabled) { 3247 switch (Level) { 3248 case AMD3DNowAthlon: 3249 Features["3dnowa"] = true; 3250 case AMD3DNow: 3251 Features["3dnow"] = true; 3252 case MMX: 3253 Features["mmx"] = true; 3254 case NoMMX3DNow: 3255 break; 3256 } 3257 return; 3258 } 3259 3260 switch (Level) { 3261 case NoMMX3DNow: 3262 case MMX: 3263 Features["mmx"] = false; 3264 case AMD3DNow: 3265 Features["3dnow"] = false; 3266 case AMD3DNowAthlon: 3267 Features["3dnowa"] = false; 3268 } 3269 } 3270 3271 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3272 bool Enabled) { 3273 if (Enabled) { 3274 switch (Level) { 3275 case XOP: 3276 Features["xop"] = true; 3277 case FMA4: 3278 Features["fma4"] = true; 3279 setSSELevel(Features, AVX, true); 3280 case SSE4A: 3281 Features["sse4a"] = true; 3282 setSSELevel(Features, SSE3, true); 3283 case NoXOP: 3284 break; 3285 } 3286 return; 3287 } 3288 3289 switch (Level) { 3290 case NoXOP: 3291 case SSE4A: 3292 Features["sse4a"] = false; 3293 case FMA4: 3294 Features["fma4"] = false; 3295 case XOP: 3296 Features["xop"] = false; 3297 } 3298 } 3299 3300 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3301 StringRef Name, bool Enabled) { 3302 // This is a bit of a hack to deal with the sse4 target feature when used 3303 // as part of the target attribute. We handle sse4 correctly everywhere 3304 // else. See below for more information on how we handle the sse4 options. 3305 if (Name != "sse4") 3306 Features[Name] = Enabled; 3307 3308 if (Name == "mmx") { 3309 setMMXLevel(Features, MMX, Enabled); 3310 } else if (Name == "sse") { 3311 setSSELevel(Features, SSE1, Enabled); 3312 } else if (Name == "sse2") { 3313 setSSELevel(Features, SSE2, Enabled); 3314 } else if (Name == "sse3") { 3315 setSSELevel(Features, SSE3, Enabled); 3316 } else if (Name == "ssse3") { 3317 setSSELevel(Features, SSSE3, Enabled); 3318 } else if (Name == "sse4.2") { 3319 setSSELevel(Features, SSE42, Enabled); 3320 } else if (Name == "sse4.1") { 3321 setSSELevel(Features, SSE41, Enabled); 3322 } else if (Name == "3dnow") { 3323 setMMXLevel(Features, AMD3DNow, Enabled); 3324 } else if (Name == "3dnowa") { 3325 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3326 } else if (Name == "aes") { 3327 if (Enabled) 3328 setSSELevel(Features, SSE2, Enabled); 3329 } else if (Name == "pclmul") { 3330 if (Enabled) 3331 setSSELevel(Features, SSE2, Enabled); 3332 } else if (Name == "avx") { 3333 setSSELevel(Features, AVX, Enabled); 3334 } else if (Name == "avx2") { 3335 setSSELevel(Features, AVX2, Enabled); 3336 } else if (Name == "avx512f") { 3337 setSSELevel(Features, AVX512F, Enabled); 3338 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3339 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3340 Name == "avx512vbmi" || Name == "avx512ifma") { 3341 if (Enabled) 3342 setSSELevel(Features, AVX512F, Enabled); 3343 } else if (Name == "fma") { 3344 if (Enabled) 3345 setSSELevel(Features, AVX, Enabled); 3346 } else if (Name == "fma4") { 3347 setXOPLevel(Features, FMA4, Enabled); 3348 } else if (Name == "xop") { 3349 setXOPLevel(Features, XOP, Enabled); 3350 } else if (Name == "sse4a") { 3351 setXOPLevel(Features, SSE4A, Enabled); 3352 } else if (Name == "f16c") { 3353 if (Enabled) 3354 setSSELevel(Features, AVX, Enabled); 3355 } else if (Name == "sha") { 3356 if (Enabled) 3357 setSSELevel(Features, SSE2, Enabled); 3358 } else if (Name == "sse4") { 3359 // We can get here via the __target__ attribute since that's not controlled 3360 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3361 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3362 // disabled. 3363 if (Enabled) 3364 setSSELevel(Features, SSE42, Enabled); 3365 else 3366 setSSELevel(Features, SSE41, Enabled); 3367 } else if (Name == "xsave") { 3368 if (!Enabled) 3369 Features["xsaveopt"] = false; 3370 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3371 if (Enabled) 3372 Features["xsave"] = true; 3373 } 3374 } 3375 3376 /// handleTargetFeatures - Perform initialization based on the user 3377 /// configured set of features. 3378 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3379 DiagnosticsEngine &Diags) { 3380 for (const auto &Feature : Features) { 3381 if (Feature[0] != '+') 3382 continue; 3383 3384 if (Feature == "+aes") { 3385 HasAES = true; 3386 } else if (Feature == "+pclmul") { 3387 HasPCLMUL = true; 3388 } else if (Feature == "+lzcnt") { 3389 HasLZCNT = true; 3390 } else if (Feature == "+rdrnd") { 3391 HasRDRND = true; 3392 } else if (Feature == "+fsgsbase") { 3393 HasFSGSBASE = true; 3394 } else if (Feature == "+bmi") { 3395 HasBMI = true; 3396 } else if (Feature == "+bmi2") { 3397 HasBMI2 = true; 3398 } else if (Feature == "+popcnt") { 3399 HasPOPCNT = true; 3400 } else if (Feature == "+rtm") { 3401 HasRTM = true; 3402 } else if (Feature == "+prfchw") { 3403 HasPRFCHW = true; 3404 } else if (Feature == "+rdseed") { 3405 HasRDSEED = true; 3406 } else if (Feature == "+adx") { 3407 HasADX = true; 3408 } else if (Feature == "+tbm") { 3409 HasTBM = true; 3410 } else if (Feature == "+fma") { 3411 HasFMA = true; 3412 } else if (Feature == "+f16c") { 3413 HasF16C = true; 3414 } else if (Feature == "+avx512cd") { 3415 HasAVX512CD = true; 3416 } else if (Feature == "+avx512er") { 3417 HasAVX512ER = true; 3418 } else if (Feature == "+avx512pf") { 3419 HasAVX512PF = true; 3420 } else if (Feature == "+avx512dq") { 3421 HasAVX512DQ = true; 3422 } else if (Feature == "+avx512bw") { 3423 HasAVX512BW = true; 3424 } else if (Feature == "+avx512vl") { 3425 HasAVX512VL = true; 3426 } else if (Feature == "+avx512vbmi") { 3427 HasAVX512VBMI = true; 3428 } else if (Feature == "+avx512ifma") { 3429 HasAVX512IFMA = true; 3430 } else if (Feature == "+sha") { 3431 HasSHA = true; 3432 } else if (Feature == "+mpx") { 3433 HasMPX = true; 3434 } else if (Feature == "+movbe") { 3435 HasMOVBE = true; 3436 } else if (Feature == "+sgx") { 3437 HasSGX = true; 3438 } else if (Feature == "+cx16") { 3439 HasCX16 = true; 3440 } else if (Feature == "+fxsr") { 3441 HasFXSR = true; 3442 } else if (Feature == "+xsave") { 3443 HasXSAVE = true; 3444 } else if (Feature == "+xsaveopt") { 3445 HasXSAVEOPT = true; 3446 } else if (Feature == "+xsavec") { 3447 HasXSAVEC = true; 3448 } else if (Feature == "+xsaves") { 3449 HasXSAVES = true; 3450 } else if (Feature == "+mwaitx") { 3451 HasMWAITX = true; 3452 } else if (Feature == "+pku") { 3453 HasPKU = true; 3454 } else if (Feature == "+clflushopt") { 3455 HasCLFLUSHOPT = true; 3456 } else if (Feature == "+pcommit") { 3457 HasPCOMMIT = true; 3458 } else if (Feature == "+clwb") { 3459 HasCLWB = true; 3460 } else if (Feature == "+umip") { 3461 HasUMIP = true; 3462 } else if (Feature == "+prefetchwt1") { 3463 HasPREFETCHWT1 = true; 3464 } 3465 3466 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3467 .Case("+avx512f", AVX512F) 3468 .Case("+avx2", AVX2) 3469 .Case("+avx", AVX) 3470 .Case("+sse4.2", SSE42) 3471 .Case("+sse4.1", SSE41) 3472 .Case("+ssse3", SSSE3) 3473 .Case("+sse3", SSE3) 3474 .Case("+sse2", SSE2) 3475 .Case("+sse", SSE1) 3476 .Default(NoSSE); 3477 SSELevel = std::max(SSELevel, Level); 3478 3479 MMX3DNowEnum ThreeDNowLevel = 3480 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3481 .Case("+3dnowa", AMD3DNowAthlon) 3482 .Case("+3dnow", AMD3DNow) 3483 .Case("+mmx", MMX) 3484 .Default(NoMMX3DNow); 3485 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3486 3487 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3488 .Case("+xop", XOP) 3489 .Case("+fma4", FMA4) 3490 .Case("+sse4a", SSE4A) 3491 .Default(NoXOP); 3492 XOPLevel = std::max(XOPLevel, XLevel); 3493 } 3494 3495 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3496 // matches the selected sse level. 3497 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3498 (FPMath == FP_387 && SSELevel >= SSE1)) { 3499 Diags.Report(diag::err_target_unsupported_fpmath) << 3500 (FPMath == FP_SSE ? "sse" : "387"); 3501 return false; 3502 } 3503 3504 SimdDefaultAlign = 3505 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3506 return true; 3507 } 3508 3509 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3510 /// definitions for this particular subtarget. 3511 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3512 MacroBuilder &Builder) const { 3513 // Target identification. 3514 if (getTriple().getArch() == llvm::Triple::x86_64) { 3515 Builder.defineMacro("__amd64__"); 3516 Builder.defineMacro("__amd64"); 3517 Builder.defineMacro("__x86_64"); 3518 Builder.defineMacro("__x86_64__"); 3519 if (getTriple().getArchName() == "x86_64h") { 3520 Builder.defineMacro("__x86_64h"); 3521 Builder.defineMacro("__x86_64h__"); 3522 } 3523 } else { 3524 DefineStd(Builder, "i386", Opts); 3525 } 3526 3527 // Subtarget options. 3528 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3529 // truly should be based on -mtune options. 3530 switch (CPU) { 3531 case CK_Generic: 3532 break; 3533 case CK_i386: 3534 // The rest are coming from the i386 define above. 3535 Builder.defineMacro("__tune_i386__"); 3536 break; 3537 case CK_i486: 3538 case CK_WinChipC6: 3539 case CK_WinChip2: 3540 case CK_C3: 3541 defineCPUMacros(Builder, "i486"); 3542 break; 3543 case CK_PentiumMMX: 3544 Builder.defineMacro("__pentium_mmx__"); 3545 Builder.defineMacro("__tune_pentium_mmx__"); 3546 // Fallthrough 3547 case CK_i586: 3548 case CK_Pentium: 3549 defineCPUMacros(Builder, "i586"); 3550 defineCPUMacros(Builder, "pentium"); 3551 break; 3552 case CK_Pentium3: 3553 case CK_Pentium3M: 3554 case CK_PentiumM: 3555 Builder.defineMacro("__tune_pentium3__"); 3556 // Fallthrough 3557 case CK_Pentium2: 3558 case CK_C3_2: 3559 Builder.defineMacro("__tune_pentium2__"); 3560 // Fallthrough 3561 case CK_PentiumPro: 3562 Builder.defineMacro("__tune_i686__"); 3563 Builder.defineMacro("__tune_pentiumpro__"); 3564 // Fallthrough 3565 case CK_i686: 3566 Builder.defineMacro("__i686"); 3567 Builder.defineMacro("__i686__"); 3568 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3569 Builder.defineMacro("__pentiumpro"); 3570 Builder.defineMacro("__pentiumpro__"); 3571 break; 3572 case CK_Pentium4: 3573 case CK_Pentium4M: 3574 defineCPUMacros(Builder, "pentium4"); 3575 break; 3576 case CK_Yonah: 3577 case CK_Prescott: 3578 case CK_Nocona: 3579 defineCPUMacros(Builder, "nocona"); 3580 break; 3581 case CK_Core2: 3582 case CK_Penryn: 3583 defineCPUMacros(Builder, "core2"); 3584 break; 3585 case CK_Bonnell: 3586 defineCPUMacros(Builder, "atom"); 3587 break; 3588 case CK_Silvermont: 3589 defineCPUMacros(Builder, "slm"); 3590 break; 3591 case CK_Nehalem: 3592 case CK_Westmere: 3593 case CK_SandyBridge: 3594 case CK_IvyBridge: 3595 case CK_Haswell: 3596 case CK_Broadwell: 3597 case CK_SkylakeClient: 3598 // FIXME: Historically, we defined this legacy name, it would be nice to 3599 // remove it at some point. We've never exposed fine-grained names for 3600 // recent primary x86 CPUs, and we should keep it that way. 3601 defineCPUMacros(Builder, "corei7"); 3602 break; 3603 case CK_SkylakeServer: 3604 defineCPUMacros(Builder, "skx"); 3605 break; 3606 case CK_Cannonlake: 3607 break; 3608 case CK_KNL: 3609 defineCPUMacros(Builder, "knl"); 3610 break; 3611 case CK_Lakemont: 3612 Builder.defineMacro("__tune_lakemont__"); 3613 break; 3614 case CK_K6_2: 3615 Builder.defineMacro("__k6_2__"); 3616 Builder.defineMacro("__tune_k6_2__"); 3617 // Fallthrough 3618 case CK_K6_3: 3619 if (CPU != CK_K6_2) { // In case of fallthrough 3620 // FIXME: GCC may be enabling these in cases where some other k6 3621 // architecture is specified but -m3dnow is explicitly provided. The 3622 // exact semantics need to be determined and emulated here. 3623 Builder.defineMacro("__k6_3__"); 3624 Builder.defineMacro("__tune_k6_3__"); 3625 } 3626 // Fallthrough 3627 case CK_K6: 3628 defineCPUMacros(Builder, "k6"); 3629 break; 3630 case CK_Athlon: 3631 case CK_AthlonThunderbird: 3632 case CK_Athlon4: 3633 case CK_AthlonXP: 3634 case CK_AthlonMP: 3635 defineCPUMacros(Builder, "athlon"); 3636 if (SSELevel != NoSSE) { 3637 Builder.defineMacro("__athlon_sse__"); 3638 Builder.defineMacro("__tune_athlon_sse__"); 3639 } 3640 break; 3641 case CK_K8: 3642 case CK_K8SSE3: 3643 case CK_x86_64: 3644 case CK_Opteron: 3645 case CK_OpteronSSE3: 3646 case CK_Athlon64: 3647 case CK_Athlon64SSE3: 3648 case CK_AthlonFX: 3649 defineCPUMacros(Builder, "k8"); 3650 break; 3651 case CK_AMDFAM10: 3652 defineCPUMacros(Builder, "amdfam10"); 3653 break; 3654 case CK_BTVER1: 3655 defineCPUMacros(Builder, "btver1"); 3656 break; 3657 case CK_BTVER2: 3658 defineCPUMacros(Builder, "btver2"); 3659 break; 3660 case CK_BDVER1: 3661 defineCPUMacros(Builder, "bdver1"); 3662 break; 3663 case CK_BDVER2: 3664 defineCPUMacros(Builder, "bdver2"); 3665 break; 3666 case CK_BDVER3: 3667 defineCPUMacros(Builder, "bdver3"); 3668 break; 3669 case CK_BDVER4: 3670 defineCPUMacros(Builder, "bdver4"); 3671 break; 3672 case CK_Geode: 3673 defineCPUMacros(Builder, "geode"); 3674 break; 3675 } 3676 3677 // Target properties. 3678 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3679 3680 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3681 // functions in glibc header files that use FP Stack inline asm which the 3682 // backend can't deal with (PR879). 3683 Builder.defineMacro("__NO_MATH_INLINES"); 3684 3685 if (HasAES) 3686 Builder.defineMacro("__AES__"); 3687 3688 if (HasPCLMUL) 3689 Builder.defineMacro("__PCLMUL__"); 3690 3691 if (HasLZCNT) 3692 Builder.defineMacro("__LZCNT__"); 3693 3694 if (HasRDRND) 3695 Builder.defineMacro("__RDRND__"); 3696 3697 if (HasFSGSBASE) 3698 Builder.defineMacro("__FSGSBASE__"); 3699 3700 if (HasBMI) 3701 Builder.defineMacro("__BMI__"); 3702 3703 if (HasBMI2) 3704 Builder.defineMacro("__BMI2__"); 3705 3706 if (HasPOPCNT) 3707 Builder.defineMacro("__POPCNT__"); 3708 3709 if (HasRTM) 3710 Builder.defineMacro("__RTM__"); 3711 3712 if (HasPRFCHW) 3713 Builder.defineMacro("__PRFCHW__"); 3714 3715 if (HasRDSEED) 3716 Builder.defineMacro("__RDSEED__"); 3717 3718 if (HasADX) 3719 Builder.defineMacro("__ADX__"); 3720 3721 if (HasTBM) 3722 Builder.defineMacro("__TBM__"); 3723 3724 if (HasMWAITX) 3725 Builder.defineMacro("__MWAITX__"); 3726 3727 switch (XOPLevel) { 3728 case XOP: 3729 Builder.defineMacro("__XOP__"); 3730 case FMA4: 3731 Builder.defineMacro("__FMA4__"); 3732 case SSE4A: 3733 Builder.defineMacro("__SSE4A__"); 3734 case NoXOP: 3735 break; 3736 } 3737 3738 if (HasFMA) 3739 Builder.defineMacro("__FMA__"); 3740 3741 if (HasF16C) 3742 Builder.defineMacro("__F16C__"); 3743 3744 if (HasAVX512CD) 3745 Builder.defineMacro("__AVX512CD__"); 3746 if (HasAVX512ER) 3747 Builder.defineMacro("__AVX512ER__"); 3748 if (HasAVX512PF) 3749 Builder.defineMacro("__AVX512PF__"); 3750 if (HasAVX512DQ) 3751 Builder.defineMacro("__AVX512DQ__"); 3752 if (HasAVX512BW) 3753 Builder.defineMacro("__AVX512BW__"); 3754 if (HasAVX512VL) 3755 Builder.defineMacro("__AVX512VL__"); 3756 if (HasAVX512VBMI) 3757 Builder.defineMacro("__AVX512VBMI__"); 3758 if (HasAVX512IFMA) 3759 Builder.defineMacro("__AVX512IFMA__"); 3760 3761 if (HasSHA) 3762 Builder.defineMacro("__SHA__"); 3763 3764 if (HasFXSR) 3765 Builder.defineMacro("__FXSR__"); 3766 if (HasXSAVE) 3767 Builder.defineMacro("__XSAVE__"); 3768 if (HasXSAVEOPT) 3769 Builder.defineMacro("__XSAVEOPT__"); 3770 if (HasXSAVEC) 3771 Builder.defineMacro("__XSAVEC__"); 3772 if (HasXSAVES) 3773 Builder.defineMacro("__XSAVES__"); 3774 if (HasPKU) 3775 Builder.defineMacro("__PKU__"); 3776 if (HasCX16) 3777 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3778 3779 // Each case falls through to the previous one here. 3780 switch (SSELevel) { 3781 case AVX512F: 3782 Builder.defineMacro("__AVX512F__"); 3783 case AVX2: 3784 Builder.defineMacro("__AVX2__"); 3785 case AVX: 3786 Builder.defineMacro("__AVX__"); 3787 case SSE42: 3788 Builder.defineMacro("__SSE4_2__"); 3789 case SSE41: 3790 Builder.defineMacro("__SSE4_1__"); 3791 case SSSE3: 3792 Builder.defineMacro("__SSSE3__"); 3793 case SSE3: 3794 Builder.defineMacro("__SSE3__"); 3795 case SSE2: 3796 Builder.defineMacro("__SSE2__"); 3797 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3798 case SSE1: 3799 Builder.defineMacro("__SSE__"); 3800 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3801 case NoSSE: 3802 break; 3803 } 3804 3805 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3806 switch (SSELevel) { 3807 case AVX512F: 3808 case AVX2: 3809 case AVX: 3810 case SSE42: 3811 case SSE41: 3812 case SSSE3: 3813 case SSE3: 3814 case SSE2: 3815 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3816 break; 3817 case SSE1: 3818 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3819 break; 3820 default: 3821 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3822 } 3823 } 3824 3825 // Each case falls through to the previous one here. 3826 switch (MMX3DNowLevel) { 3827 case AMD3DNowAthlon: 3828 Builder.defineMacro("__3dNOW_A__"); 3829 case AMD3DNow: 3830 Builder.defineMacro("__3dNOW__"); 3831 case MMX: 3832 Builder.defineMacro("__MMX__"); 3833 case NoMMX3DNow: 3834 break; 3835 } 3836 3837 if (CPU >= CK_i486) { 3838 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3839 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3840 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3841 } 3842 if (CPU >= CK_i586) 3843 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3844 } 3845 3846 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3847 return llvm::StringSwitch<bool>(Feature) 3848 .Case("aes", HasAES) 3849 .Case("avx", SSELevel >= AVX) 3850 .Case("avx2", SSELevel >= AVX2) 3851 .Case("avx512f", SSELevel >= AVX512F) 3852 .Case("avx512cd", HasAVX512CD) 3853 .Case("avx512er", HasAVX512ER) 3854 .Case("avx512pf", HasAVX512PF) 3855 .Case("avx512dq", HasAVX512DQ) 3856 .Case("avx512bw", HasAVX512BW) 3857 .Case("avx512vl", HasAVX512VL) 3858 .Case("avx512vbmi", HasAVX512VBMI) 3859 .Case("avx512ifma", HasAVX512IFMA) 3860 .Case("bmi", HasBMI) 3861 .Case("bmi2", HasBMI2) 3862 .Case("clflushopt", HasCLFLUSHOPT) 3863 .Case("clwb", HasCLWB) 3864 .Case("cx16", HasCX16) 3865 .Case("f16c", HasF16C) 3866 .Case("fma", HasFMA) 3867 .Case("fma4", XOPLevel >= FMA4) 3868 .Case("fsgsbase", HasFSGSBASE) 3869 .Case("fxsr", HasFXSR) 3870 .Case("lzcnt", HasLZCNT) 3871 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3872 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3873 .Case("mmx", MMX3DNowLevel >= MMX) 3874 .Case("movbe", HasMOVBE) 3875 .Case("mpx", HasMPX) 3876 .Case("pclmul", HasPCLMUL) 3877 .Case("pcommit", HasPCOMMIT) 3878 .Case("pku", HasPKU) 3879 .Case("popcnt", HasPOPCNT) 3880 .Case("prefetchwt1", HasPREFETCHWT1) 3881 .Case("prfchw", HasPRFCHW) 3882 .Case("rdrnd", HasRDRND) 3883 .Case("rdseed", HasRDSEED) 3884 .Case("rtm", HasRTM) 3885 .Case("sgx", HasSGX) 3886 .Case("sha", HasSHA) 3887 .Case("sse", SSELevel >= SSE1) 3888 .Case("sse2", SSELevel >= SSE2) 3889 .Case("sse3", SSELevel >= SSE3) 3890 .Case("ssse3", SSELevel >= SSSE3) 3891 .Case("sse4.1", SSELevel >= SSE41) 3892 .Case("sse4.2", SSELevel >= SSE42) 3893 .Case("sse4a", XOPLevel >= SSE4A) 3894 .Case("tbm", HasTBM) 3895 .Case("umip", HasUMIP) 3896 .Case("x86", true) 3897 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3898 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3899 .Case("xop", XOPLevel >= XOP) 3900 .Case("xsave", HasXSAVE) 3901 .Case("xsavec", HasXSAVEC) 3902 .Case("xsaves", HasXSAVES) 3903 .Case("xsaveopt", HasXSAVEOPT) 3904 .Default(false); 3905 } 3906 3907 // We can't use a generic validation scheme for the features accepted here 3908 // versus subtarget features accepted in the target attribute because the 3909 // bitfield structure that's initialized in the runtime only supports the 3910 // below currently rather than the full range of subtarget features. (See 3911 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3912 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3913 return llvm::StringSwitch<bool>(FeatureStr) 3914 .Case("cmov", true) 3915 .Case("mmx", true) 3916 .Case("popcnt", true) 3917 .Case("sse", true) 3918 .Case("sse2", true) 3919 .Case("sse3", true) 3920 .Case("ssse3", true) 3921 .Case("sse4.1", true) 3922 .Case("sse4.2", true) 3923 .Case("avx", true) 3924 .Case("avx2", true) 3925 .Case("sse4a", true) 3926 .Case("fma4", true) 3927 .Case("xop", true) 3928 .Case("fma", true) 3929 .Case("avx512f", true) 3930 .Case("bmi", true) 3931 .Case("bmi2", true) 3932 .Case("aes", true) 3933 .Case("pclmul", true) 3934 .Case("avx512vl", true) 3935 .Case("avx512bw", true) 3936 .Case("avx512dq", true) 3937 .Case("avx512cd", true) 3938 .Case("avx512er", true) 3939 .Case("avx512pf", true) 3940 .Case("avx512vbmi", true) 3941 .Case("avx512ifma", true) 3942 .Default(false); 3943 } 3944 3945 bool 3946 X86TargetInfo::validateAsmConstraint(const char *&Name, 3947 TargetInfo::ConstraintInfo &Info) const { 3948 switch (*Name) { 3949 default: return false; 3950 // Constant constraints. 3951 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3952 // instructions. 3953 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3954 // x86_64 instructions. 3955 case 's': 3956 Info.setRequiresImmediate(); 3957 return true; 3958 case 'I': 3959 Info.setRequiresImmediate(0, 31); 3960 return true; 3961 case 'J': 3962 Info.setRequiresImmediate(0, 63); 3963 return true; 3964 case 'K': 3965 Info.setRequiresImmediate(-128, 127); 3966 return true; 3967 case 'L': 3968 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3969 return true; 3970 case 'M': 3971 Info.setRequiresImmediate(0, 3); 3972 return true; 3973 case 'N': 3974 Info.setRequiresImmediate(0, 255); 3975 return true; 3976 case 'O': 3977 Info.setRequiresImmediate(0, 127); 3978 return true; 3979 // Register constraints. 3980 case 'Y': // 'Y' is the first character for several 2-character constraints. 3981 // Shift the pointer to the second character of the constraint. 3982 Name++; 3983 switch (*Name) { 3984 default: 3985 return false; 3986 case '0': // First SSE register. 3987 case 't': // Any SSE register, when SSE2 is enabled. 3988 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3989 case 'm': // Any MMX register, when inter-unit moves enabled. 3990 Info.setAllowsRegister(); 3991 return true; 3992 } 3993 case 'f': // Any x87 floating point stack register. 3994 // Constraint 'f' cannot be used for output operands. 3995 if (Info.ConstraintStr[0] == '=') 3996 return false; 3997 Info.setAllowsRegister(); 3998 return true; 3999 case 'a': // eax. 4000 case 'b': // ebx. 4001 case 'c': // ecx. 4002 case 'd': // edx. 4003 case 'S': // esi. 4004 case 'D': // edi. 4005 case 'A': // edx:eax. 4006 case 't': // Top of floating point stack. 4007 case 'u': // Second from top of floating point stack. 4008 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4009 case 'y': // Any MMX register. 4010 case 'x': // Any SSE register. 4011 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4012 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4013 case 'l': // "Index" registers: any general register that can be used as an 4014 // index in a base+index memory access. 4015 Info.setAllowsRegister(); 4016 return true; 4017 // Floating point constant constraints. 4018 case 'C': // SSE floating point constant. 4019 case 'G': // x87 floating point constant. 4020 return true; 4021 } 4022 } 4023 4024 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4025 unsigned Size) const { 4026 // Strip off constraint modifiers. 4027 while (Constraint[0] == '=' || 4028 Constraint[0] == '+' || 4029 Constraint[0] == '&') 4030 Constraint = Constraint.substr(1); 4031 4032 return validateOperandSize(Constraint, Size); 4033 } 4034 4035 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4036 unsigned Size) const { 4037 return validateOperandSize(Constraint, Size); 4038 } 4039 4040 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4041 unsigned Size) const { 4042 switch (Constraint[0]) { 4043 default: break; 4044 case 'y': 4045 return Size <= 64; 4046 case 'f': 4047 case 't': 4048 case 'u': 4049 return Size <= 128; 4050 case 'x': 4051 if (SSELevel >= AVX512F) 4052 // 512-bit zmm registers can be used if target supports AVX512F. 4053 return Size <= 512U; 4054 else if (SSELevel >= AVX) 4055 // 256-bit ymm registers can be used if target supports AVX. 4056 return Size <= 256U; 4057 return Size <= 128U; 4058 case 'Y': 4059 // 'Y' is the first character for several 2-character constraints. 4060 switch (Constraint[1]) { 4061 default: break; 4062 case 'm': 4063 // 'Ym' is synonymous with 'y'. 4064 return Size <= 64; 4065 case 'i': 4066 case 't': 4067 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4068 if (SSELevel >= AVX512F) 4069 return Size <= 512U; 4070 else if (SSELevel >= AVX) 4071 return Size <= 256U; 4072 return SSELevel >= SSE2 && Size <= 128U; 4073 } 4074 4075 } 4076 4077 return true; 4078 } 4079 4080 std::string 4081 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4082 switch (*Constraint) { 4083 case 'a': return std::string("{ax}"); 4084 case 'b': return std::string("{bx}"); 4085 case 'c': return std::string("{cx}"); 4086 case 'd': return std::string("{dx}"); 4087 case 'S': return std::string("{si}"); 4088 case 'D': return std::string("{di}"); 4089 case 'p': // address 4090 return std::string("im"); 4091 case 't': // top of floating point stack. 4092 return std::string("{st}"); 4093 case 'u': // second from top of floating point stack. 4094 return std::string("{st(1)}"); // second from top of floating point stack. 4095 default: 4096 return std::string(1, *Constraint); 4097 } 4098 } 4099 4100 // X86-32 generic target 4101 class X86_32TargetInfo : public X86TargetInfo { 4102 public: 4103 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4104 : X86TargetInfo(Triple, Opts) { 4105 DoubleAlign = LongLongAlign = 32; 4106 LongDoubleWidth = 96; 4107 LongDoubleAlign = 32; 4108 SuitableAlign = 128; 4109 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4110 SizeType = UnsignedInt; 4111 PtrDiffType = SignedInt; 4112 IntPtrType = SignedInt; 4113 RegParmMax = 3; 4114 4115 // Use fpret for all types. 4116 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4117 (1 << TargetInfo::Double) | 4118 (1 << TargetInfo::LongDouble)); 4119 4120 // x86-32 has atomics up to 8 bytes 4121 // FIXME: Check that we actually have cmpxchg8b before setting 4122 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4123 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4124 } 4125 BuiltinVaListKind getBuiltinVaListKind() const override { 4126 return TargetInfo::CharPtrBuiltinVaList; 4127 } 4128 4129 int getEHDataRegisterNumber(unsigned RegNo) const override { 4130 if (RegNo == 0) return 0; 4131 if (RegNo == 1) return 2; 4132 return -1; 4133 } 4134 bool validateOperandSize(StringRef Constraint, 4135 unsigned Size) const override { 4136 switch (Constraint[0]) { 4137 default: break; 4138 case 'R': 4139 case 'q': 4140 case 'Q': 4141 case 'a': 4142 case 'b': 4143 case 'c': 4144 case 'd': 4145 case 'S': 4146 case 'D': 4147 return Size <= 32; 4148 case 'A': 4149 return Size <= 64; 4150 } 4151 4152 return X86TargetInfo::validateOperandSize(Constraint, Size); 4153 } 4154 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4155 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4156 Builtin::FirstTSBuiltin + 1); 4157 } 4158 }; 4159 4160 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4161 public: 4162 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4163 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4164 4165 unsigned getFloatEvalMethod() const override { 4166 unsigned Major, Minor, Micro; 4167 getTriple().getOSVersion(Major, Minor, Micro); 4168 // New NetBSD uses the default rounding mode. 4169 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4170 return X86_32TargetInfo::getFloatEvalMethod(); 4171 // NetBSD before 6.99.26 defaults to "double" rounding. 4172 return 1; 4173 } 4174 }; 4175 4176 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4177 public: 4178 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4179 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4180 SizeType = UnsignedLong; 4181 IntPtrType = SignedLong; 4182 PtrDiffType = SignedLong; 4183 } 4184 }; 4185 4186 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4187 public: 4188 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4189 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4190 SizeType = UnsignedLong; 4191 IntPtrType = SignedLong; 4192 PtrDiffType = SignedLong; 4193 } 4194 }; 4195 4196 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4197 public: 4198 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4199 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4200 LongDoubleWidth = 128; 4201 LongDoubleAlign = 128; 4202 SuitableAlign = 128; 4203 MaxVectorAlign = 256; 4204 // The watchOS simulator uses the builtin bool type for Objective-C. 4205 llvm::Triple T = llvm::Triple(Triple); 4206 if (T.isWatchOS()) 4207 UseSignedCharForObjCBool = false; 4208 SizeType = UnsignedLong; 4209 IntPtrType = SignedLong; 4210 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4211 HasAlignMac68kSupport = true; 4212 } 4213 4214 bool handleTargetFeatures(std::vector<std::string> &Features, 4215 DiagnosticsEngine &Diags) override { 4216 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4217 Diags)) 4218 return false; 4219 // We now know the features we have: we can decide how to align vectors. 4220 MaxVectorAlign = 4221 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4222 return true; 4223 } 4224 }; 4225 4226 // x86-32 Windows target 4227 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4228 public: 4229 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4230 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4231 WCharType = UnsignedShort; 4232 DoubleAlign = LongLongAlign = 64; 4233 bool IsWinCOFF = 4234 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4235 resetDataLayout(IsWinCOFF 4236 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4237 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4238 } 4239 void getTargetDefines(const LangOptions &Opts, 4240 MacroBuilder &Builder) const override { 4241 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4242 } 4243 }; 4244 4245 // x86-32 Windows Visual Studio target 4246 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4247 public: 4248 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4249 const TargetOptions &Opts) 4250 : WindowsX86_32TargetInfo(Triple, Opts) { 4251 LongDoubleWidth = LongDoubleAlign = 64; 4252 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4253 } 4254 void getTargetDefines(const LangOptions &Opts, 4255 MacroBuilder &Builder) const override { 4256 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4257 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4258 // The value of the following reflects processor type. 4259 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4260 // We lost the original triple, so we use the default. 4261 Builder.defineMacro("_M_IX86", "600"); 4262 } 4263 }; 4264 4265 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4266 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4267 // supports __declspec natively under -fms-extensions, but we define a no-op 4268 // __declspec macro anyway for pre-processor compatibility. 4269 if (Opts.MicrosoftExt) 4270 Builder.defineMacro("__declspec", "__declspec"); 4271 else 4272 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4273 4274 if (!Opts.MicrosoftExt) { 4275 // Provide macros for all the calling convention keywords. Provide both 4276 // single and double underscore prefixed variants. These are available on 4277 // x64 as well as x86, even though they have no effect. 4278 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4279 for (const char *CC : CCs) { 4280 std::string GCCSpelling = "__attribute__((__"; 4281 GCCSpelling += CC; 4282 GCCSpelling += "__))"; 4283 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4284 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4285 } 4286 } 4287 } 4288 4289 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4290 Builder.defineMacro("__MSVCRT__"); 4291 Builder.defineMacro("__MINGW32__"); 4292 addCygMingDefines(Opts, Builder); 4293 } 4294 4295 // x86-32 MinGW target 4296 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4297 public: 4298 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4299 : WindowsX86_32TargetInfo(Triple, Opts) {} 4300 void getTargetDefines(const LangOptions &Opts, 4301 MacroBuilder &Builder) const override { 4302 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4303 DefineStd(Builder, "WIN32", Opts); 4304 DefineStd(Builder, "WINNT", Opts); 4305 Builder.defineMacro("_X86_"); 4306 addMinGWDefines(Opts, Builder); 4307 } 4308 }; 4309 4310 // x86-32 Cygwin target 4311 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4312 public: 4313 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4314 : X86_32TargetInfo(Triple, Opts) { 4315 WCharType = UnsignedShort; 4316 DoubleAlign = LongLongAlign = 64; 4317 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4318 } 4319 void getTargetDefines(const LangOptions &Opts, 4320 MacroBuilder &Builder) const override { 4321 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4322 Builder.defineMacro("_X86_"); 4323 Builder.defineMacro("__CYGWIN__"); 4324 Builder.defineMacro("__CYGWIN32__"); 4325 addCygMingDefines(Opts, Builder); 4326 DefineStd(Builder, "unix", Opts); 4327 if (Opts.CPlusPlus) 4328 Builder.defineMacro("_GNU_SOURCE"); 4329 } 4330 }; 4331 4332 // x86-32 Haiku target 4333 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4334 public: 4335 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4336 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4337 } 4338 void getTargetDefines(const LangOptions &Opts, 4339 MacroBuilder &Builder) const override { 4340 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4341 Builder.defineMacro("__INTEL__"); 4342 } 4343 }; 4344 4345 // X86-32 MCU target 4346 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4347 public: 4348 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4349 : X86_32TargetInfo(Triple, Opts) { 4350 LongDoubleWidth = 64; 4351 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4352 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4353 WIntType = UnsignedInt; 4354 } 4355 4356 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4357 // On MCU we support only C calling convention. 4358 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4359 } 4360 4361 void getTargetDefines(const LangOptions &Opts, 4362 MacroBuilder &Builder) const override { 4363 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4364 Builder.defineMacro("__iamcu"); 4365 Builder.defineMacro("__iamcu__"); 4366 } 4367 4368 bool allowsLargerPreferedTypeAlignment() const override { 4369 return false; 4370 } 4371 }; 4372 4373 // RTEMS Target 4374 template<typename Target> 4375 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4376 protected: 4377 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4378 MacroBuilder &Builder) const override { 4379 // RTEMS defines; list based off of gcc output 4380 4381 Builder.defineMacro("__rtems__"); 4382 Builder.defineMacro("__ELF__"); 4383 } 4384 4385 public: 4386 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4387 : OSTargetInfo<Target>(Triple, Opts) { 4388 switch (Triple.getArch()) { 4389 default: 4390 case llvm::Triple::x86: 4391 // this->MCountName = ".mcount"; 4392 break; 4393 case llvm::Triple::mips: 4394 case llvm::Triple::mipsel: 4395 case llvm::Triple::ppc: 4396 case llvm::Triple::ppc64: 4397 case llvm::Triple::ppc64le: 4398 // this->MCountName = "_mcount"; 4399 break; 4400 case llvm::Triple::arm: 4401 // this->MCountName = "__mcount"; 4402 break; 4403 } 4404 } 4405 }; 4406 4407 // x86-32 RTEMS target 4408 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4409 public: 4410 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4411 : X86_32TargetInfo(Triple, Opts) { 4412 SizeType = UnsignedLong; 4413 IntPtrType = SignedLong; 4414 PtrDiffType = SignedLong; 4415 } 4416 void getTargetDefines(const LangOptions &Opts, 4417 MacroBuilder &Builder) const override { 4418 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4419 Builder.defineMacro("__INTEL__"); 4420 Builder.defineMacro("__rtems__"); 4421 } 4422 }; 4423 4424 // x86-64 generic target 4425 class X86_64TargetInfo : public X86TargetInfo { 4426 public: 4427 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4428 : X86TargetInfo(Triple, Opts) { 4429 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4430 bool IsWinCOFF = 4431 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4432 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4433 LongDoubleWidth = 128; 4434 LongDoubleAlign = 128; 4435 LargeArrayMinWidth = 128; 4436 LargeArrayAlign = 128; 4437 SuitableAlign = 128; 4438 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4439 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4440 IntPtrType = IsX32 ? SignedInt : SignedLong; 4441 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4442 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4443 RegParmMax = 6; 4444 4445 // Pointers are 32-bit in x32. 4446 resetDataLayout(IsX32 4447 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4448 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4449 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4450 4451 // Use fpret only for long double. 4452 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4453 4454 // Use fp2ret for _Complex long double. 4455 ComplexLongDoubleUsesFP2Ret = true; 4456 4457 // Make __builtin_ms_va_list available. 4458 HasBuiltinMSVaList = true; 4459 4460 // x86-64 has atomics up to 16 bytes. 4461 MaxAtomicPromoteWidth = 128; 4462 MaxAtomicInlineWidth = 128; 4463 } 4464 BuiltinVaListKind getBuiltinVaListKind() const override { 4465 return TargetInfo::X86_64ABIBuiltinVaList; 4466 } 4467 4468 int getEHDataRegisterNumber(unsigned RegNo) const override { 4469 if (RegNo == 0) return 0; 4470 if (RegNo == 1) return 1; 4471 return -1; 4472 } 4473 4474 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4475 switch (CC) { 4476 case CC_C: 4477 case CC_Swift: 4478 case CC_X86VectorCall: 4479 case CC_IntelOclBicc: 4480 case CC_X86_64Win64: 4481 case CC_PreserveMost: 4482 case CC_PreserveAll: 4483 return CCCR_OK; 4484 default: 4485 return CCCR_Warning; 4486 } 4487 } 4488 4489 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4490 return CC_C; 4491 } 4492 4493 // for x32 we need it here explicitly 4494 bool hasInt128Type() const override { return true; } 4495 unsigned getUnwindWordWidth() const override { return 64; } 4496 unsigned getRegisterWidth() const override { return 64; } 4497 4498 bool validateGlobalRegisterVariable(StringRef RegName, 4499 unsigned RegSize, 4500 bool &HasSizeMismatch) const override { 4501 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4502 // handle. 4503 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4504 // Check that the register size is 64-bit. 4505 HasSizeMismatch = RegSize != 64; 4506 return true; 4507 } 4508 4509 // Check if the register is a 32-bit register the backend can handle. 4510 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4511 HasSizeMismatch); 4512 } 4513 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4514 return llvm::makeArrayRef(BuiltinInfoX86, 4515 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4516 } 4517 }; 4518 4519 // x86-64 Windows target 4520 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4521 public: 4522 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4523 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4524 WCharType = UnsignedShort; 4525 LongWidth = LongAlign = 32; 4526 DoubleAlign = LongLongAlign = 64; 4527 IntMaxType = SignedLongLong; 4528 Int64Type = SignedLongLong; 4529 SizeType = UnsignedLongLong; 4530 PtrDiffType = SignedLongLong; 4531 IntPtrType = SignedLongLong; 4532 } 4533 4534 void getTargetDefines(const LangOptions &Opts, 4535 MacroBuilder &Builder) const override { 4536 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4537 Builder.defineMacro("_WIN64"); 4538 } 4539 4540 BuiltinVaListKind getBuiltinVaListKind() const override { 4541 return TargetInfo::CharPtrBuiltinVaList; 4542 } 4543 4544 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4545 switch (CC) { 4546 case CC_X86StdCall: 4547 case CC_X86ThisCall: 4548 case CC_X86FastCall: 4549 return CCCR_Ignore; 4550 case CC_C: 4551 case CC_X86VectorCall: 4552 case CC_IntelOclBicc: 4553 case CC_X86_64SysV: 4554 case CC_Swift: 4555 return CCCR_OK; 4556 default: 4557 return CCCR_Warning; 4558 } 4559 } 4560 }; 4561 4562 // x86-64 Windows Visual Studio target 4563 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4564 public: 4565 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4566 const TargetOptions &Opts) 4567 : WindowsX86_64TargetInfo(Triple, Opts) { 4568 LongDoubleWidth = LongDoubleAlign = 64; 4569 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4570 } 4571 void getTargetDefines(const LangOptions &Opts, 4572 MacroBuilder &Builder) const override { 4573 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4574 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4575 Builder.defineMacro("_M_X64", "100"); 4576 Builder.defineMacro("_M_AMD64", "100"); 4577 } 4578 }; 4579 4580 // x86-64 MinGW target 4581 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4582 public: 4583 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4584 : WindowsX86_64TargetInfo(Triple, Opts) { 4585 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4586 // with x86 FP ops. Weird. 4587 LongDoubleWidth = LongDoubleAlign = 128; 4588 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4589 } 4590 4591 void getTargetDefines(const LangOptions &Opts, 4592 MacroBuilder &Builder) const override { 4593 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4594 DefineStd(Builder, "WIN64", Opts); 4595 Builder.defineMacro("__MINGW64__"); 4596 addMinGWDefines(Opts, Builder); 4597 4598 // GCC defines this macro when it is using __gxx_personality_seh0. 4599 if (!Opts.SjLjExceptions) 4600 Builder.defineMacro("__SEH__"); 4601 } 4602 }; 4603 4604 // x86-64 Cygwin target 4605 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4606 public: 4607 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4608 : X86_64TargetInfo(Triple, Opts) { 4609 TLSSupported = false; 4610 WCharType = UnsignedShort; 4611 } 4612 void getTargetDefines(const LangOptions &Opts, 4613 MacroBuilder &Builder) const override { 4614 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4615 Builder.defineMacro("__x86_64__"); 4616 Builder.defineMacro("__CYGWIN__"); 4617 Builder.defineMacro("__CYGWIN64__"); 4618 addCygMingDefines(Opts, Builder); 4619 DefineStd(Builder, "unix", Opts); 4620 if (Opts.CPlusPlus) 4621 Builder.defineMacro("_GNU_SOURCE"); 4622 4623 // GCC defines this macro when it is using __gxx_personality_seh0. 4624 if (!Opts.SjLjExceptions) 4625 Builder.defineMacro("__SEH__"); 4626 } 4627 }; 4628 4629 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4630 public: 4631 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4632 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4633 Int64Type = SignedLongLong; 4634 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4635 llvm::Triple T = llvm::Triple(Triple); 4636 if (T.isiOS()) 4637 UseSignedCharForObjCBool = false; 4638 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4639 } 4640 4641 bool handleTargetFeatures(std::vector<std::string> &Features, 4642 DiagnosticsEngine &Diags) override { 4643 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4644 Diags)) 4645 return false; 4646 // We now know the features we have: we can decide how to align vectors. 4647 MaxVectorAlign = 4648 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4649 return true; 4650 } 4651 }; 4652 4653 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4654 public: 4655 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4656 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4657 IntMaxType = SignedLongLong; 4658 Int64Type = SignedLongLong; 4659 } 4660 }; 4661 4662 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4663 public: 4664 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4665 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4666 IntMaxType = SignedLongLong; 4667 Int64Type = SignedLongLong; 4668 } 4669 }; 4670 4671 class ARMTargetInfo : public TargetInfo { 4672 // Possible FPU choices. 4673 enum FPUMode { 4674 VFP2FPU = (1 << 0), 4675 VFP3FPU = (1 << 1), 4676 VFP4FPU = (1 << 2), 4677 NeonFPU = (1 << 3), 4678 FPARMV8 = (1 << 4) 4679 }; 4680 4681 // Possible HWDiv features. 4682 enum HWDivMode { 4683 HWDivThumb = (1 << 0), 4684 HWDivARM = (1 << 1) 4685 }; 4686 4687 static bool FPUModeIsVFP(FPUMode Mode) { 4688 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4689 } 4690 4691 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4692 static const char * const GCCRegNames[]; 4693 4694 std::string ABI, CPU; 4695 4696 StringRef CPUProfile; 4697 StringRef CPUAttr; 4698 4699 enum { 4700 FP_Default, 4701 FP_VFP, 4702 FP_Neon 4703 } FPMath; 4704 4705 unsigned ArchISA; 4706 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4707 unsigned ArchProfile; 4708 unsigned ArchVersion; 4709 4710 unsigned FPU : 5; 4711 4712 unsigned IsAAPCS : 1; 4713 unsigned HWDiv : 2; 4714 4715 // Initialized via features. 4716 unsigned SoftFloat : 1; 4717 unsigned SoftFloatABI : 1; 4718 4719 unsigned CRC : 1; 4720 unsigned Crypto : 1; 4721 unsigned DSP : 1; 4722 unsigned Unaligned : 1; 4723 4724 enum { 4725 LDREX_B = (1 << 0), /// byte (8-bit) 4726 LDREX_H = (1 << 1), /// half (16-bit) 4727 LDREX_W = (1 << 2), /// word (32-bit) 4728 LDREX_D = (1 << 3), /// double (64-bit) 4729 }; 4730 4731 uint32_t LDREX; 4732 4733 // ACLE 6.5.1 Hardware floating point 4734 enum { 4735 HW_FP_HP = (1 << 1), /// half (16-bit) 4736 HW_FP_SP = (1 << 2), /// single (32-bit) 4737 HW_FP_DP = (1 << 3), /// double (64-bit) 4738 }; 4739 uint32_t HW_FP; 4740 4741 static const Builtin::Info BuiltinInfo[]; 4742 4743 void setABIAAPCS() { 4744 IsAAPCS = true; 4745 4746 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4747 const llvm::Triple &T = getTriple(); 4748 4749 // size_t is unsigned long on MachO-derived environments, NetBSD, 4750 // OpenBSD and Bitrig. 4751 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4752 T.getOS() == llvm::Triple::OpenBSD || 4753 T.getOS() == llvm::Triple::Bitrig) 4754 SizeType = UnsignedLong; 4755 else 4756 SizeType = UnsignedInt; 4757 4758 switch (T.getOS()) { 4759 case llvm::Triple::NetBSD: 4760 case llvm::Triple::OpenBSD: 4761 WCharType = SignedInt; 4762 break; 4763 case llvm::Triple::Win32: 4764 WCharType = UnsignedShort; 4765 break; 4766 case llvm::Triple::Linux: 4767 default: 4768 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4769 WCharType = UnsignedInt; 4770 break; 4771 } 4772 4773 UseBitFieldTypeAlignment = true; 4774 4775 ZeroLengthBitfieldBoundary = 0; 4776 4777 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4778 // so set preferred for small types to 32. 4779 if (T.isOSBinFormatMachO()) { 4780 resetDataLayout(BigEndian 4781 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4782 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4783 } else if (T.isOSWindows()) { 4784 assert(!BigEndian && "Windows on ARM does not support big endian"); 4785 resetDataLayout("e" 4786 "-m:w" 4787 "-p:32:32" 4788 "-i64:64" 4789 "-v128:64:128" 4790 "-a:0:32" 4791 "-n32" 4792 "-S64"); 4793 } else if (T.isOSNaCl()) { 4794 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4795 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4796 } else { 4797 resetDataLayout(BigEndian 4798 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4799 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4800 } 4801 4802 // FIXME: Enumerated types are variable width in straight AAPCS. 4803 } 4804 4805 void setABIAPCS(bool IsAAPCS16) { 4806 const llvm::Triple &T = getTriple(); 4807 4808 IsAAPCS = false; 4809 4810 if (IsAAPCS16) 4811 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4812 else 4813 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4814 4815 // size_t is unsigned int on FreeBSD. 4816 if (T.getOS() == llvm::Triple::FreeBSD) 4817 SizeType = UnsignedInt; 4818 else 4819 SizeType = UnsignedLong; 4820 4821 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4822 WCharType = SignedInt; 4823 4824 // Do not respect the alignment of bit-field types when laying out 4825 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4826 UseBitFieldTypeAlignment = false; 4827 4828 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4829 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4830 /// gcc. 4831 ZeroLengthBitfieldBoundary = 32; 4832 4833 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4834 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4835 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4836 } else if (T.isOSBinFormatMachO()) 4837 resetDataLayout( 4838 BigEndian 4839 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4840 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4841 else 4842 resetDataLayout( 4843 BigEndian 4844 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4845 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4846 4847 // FIXME: Override "preferred align" for double and long long. 4848 } 4849 4850 void setArchInfo() { 4851 StringRef ArchName = getTriple().getArchName(); 4852 4853 ArchISA = llvm::ARM::parseArchISA(ArchName); 4854 CPU = llvm::ARM::getDefaultCPU(ArchName); 4855 unsigned AK = llvm::ARM::parseArch(ArchName); 4856 if (AK != llvm::ARM::AK_INVALID) 4857 ArchKind = AK; 4858 setArchInfo(ArchKind); 4859 } 4860 4861 void setArchInfo(unsigned Kind) { 4862 StringRef SubArch; 4863 4864 // cache TargetParser info 4865 ArchKind = Kind; 4866 SubArch = llvm::ARM::getSubArch(ArchKind); 4867 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4868 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4869 4870 // cache CPU related strings 4871 CPUAttr = getCPUAttr(); 4872 CPUProfile = getCPUProfile(); 4873 } 4874 4875 void setAtomic() { 4876 // when triple does not specify a sub arch, 4877 // then we are not using inline atomics 4878 bool ShouldUseInlineAtomic = 4879 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4880 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4881 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4882 if (ArchProfile == llvm::ARM::PK_M) { 4883 MaxAtomicPromoteWidth = 32; 4884 if (ShouldUseInlineAtomic) 4885 MaxAtomicInlineWidth = 32; 4886 } 4887 else { 4888 MaxAtomicPromoteWidth = 64; 4889 if (ShouldUseInlineAtomic) 4890 MaxAtomicInlineWidth = 64; 4891 } 4892 } 4893 4894 bool isThumb() const { 4895 return (ArchISA == llvm::ARM::IK_THUMB); 4896 } 4897 4898 bool supportsThumb() const { 4899 return CPUAttr.count('T') || ArchVersion >= 6; 4900 } 4901 4902 bool supportsThumb2() const { 4903 return CPUAttr.equals("6T2") || 4904 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4905 } 4906 4907 StringRef getCPUAttr() const { 4908 // For most sub-arches, the build attribute CPU name is enough. 4909 // For Cortex variants, it's slightly different. 4910 switch(ArchKind) { 4911 default: 4912 return llvm::ARM::getCPUAttr(ArchKind); 4913 case llvm::ARM::AK_ARMV6M: 4914 return "6M"; 4915 case llvm::ARM::AK_ARMV7S: 4916 return "7S"; 4917 case llvm::ARM::AK_ARMV7A: 4918 return "7A"; 4919 case llvm::ARM::AK_ARMV7R: 4920 return "7R"; 4921 case llvm::ARM::AK_ARMV7M: 4922 return "7M"; 4923 case llvm::ARM::AK_ARMV7EM: 4924 return "7EM"; 4925 case llvm::ARM::AK_ARMV8A: 4926 return "8A"; 4927 case llvm::ARM::AK_ARMV8_1A: 4928 return "8_1A"; 4929 case llvm::ARM::AK_ARMV8_2A: 4930 return "8_2A"; 4931 case llvm::ARM::AK_ARMV8MBaseline: 4932 return "8M_BASE"; 4933 case llvm::ARM::AK_ARMV8MMainline: 4934 return "8M_MAIN"; 4935 case llvm::ARM::AK_ARMV8R: 4936 return "8R"; 4937 } 4938 } 4939 4940 StringRef getCPUProfile() const { 4941 switch(ArchProfile) { 4942 case llvm::ARM::PK_A: 4943 return "A"; 4944 case llvm::ARM::PK_R: 4945 return "R"; 4946 case llvm::ARM::PK_M: 4947 return "M"; 4948 default: 4949 return ""; 4950 } 4951 } 4952 4953 public: 4954 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4955 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4956 HW_FP(0) { 4957 4958 switch (getTriple().getOS()) { 4959 case llvm::Triple::NetBSD: 4960 case llvm::Triple::OpenBSD: 4961 PtrDiffType = SignedLong; 4962 break; 4963 default: 4964 PtrDiffType = SignedInt; 4965 break; 4966 } 4967 4968 // Cache arch related info. 4969 setArchInfo(); 4970 4971 // {} in inline assembly are neon specifiers, not assembly variant 4972 // specifiers. 4973 NoAsmVariants = true; 4974 4975 // FIXME: This duplicates code from the driver that sets the -target-abi 4976 // option - this code is used if -target-abi isn't passed and should 4977 // be unified in some way. 4978 if (Triple.isOSBinFormatMachO()) { 4979 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4980 // the frontend matches that. 4981 if (Triple.getEnvironment() == llvm::Triple::EABI || 4982 Triple.getOS() == llvm::Triple::UnknownOS || 4983 ArchProfile == llvm::ARM::PK_M) { 4984 setABI("aapcs"); 4985 } else if (Triple.isWatchABI()) { 4986 setABI("aapcs16"); 4987 } else { 4988 setABI("apcs-gnu"); 4989 } 4990 } else if (Triple.isOSWindows()) { 4991 // FIXME: this is invalid for WindowsCE 4992 setABI("aapcs"); 4993 } else { 4994 // Select the default based on the platform. 4995 switch (Triple.getEnvironment()) { 4996 case llvm::Triple::Android: 4997 case llvm::Triple::GNUEABI: 4998 case llvm::Triple::GNUEABIHF: 4999 case llvm::Triple::MuslEABI: 5000 case llvm::Triple::MuslEABIHF: 5001 setABI("aapcs-linux"); 5002 break; 5003 case llvm::Triple::EABIHF: 5004 case llvm::Triple::EABI: 5005 setABI("aapcs"); 5006 break; 5007 case llvm::Triple::GNU: 5008 setABI("apcs-gnu"); 5009 break; 5010 default: 5011 if (Triple.getOS() == llvm::Triple::NetBSD) 5012 setABI("apcs-gnu"); 5013 else 5014 setABI("aapcs"); 5015 break; 5016 } 5017 } 5018 5019 // ARM targets default to using the ARM C++ ABI. 5020 TheCXXABI.set(TargetCXXABI::GenericARM); 5021 5022 // ARM has atomics up to 8 bytes 5023 setAtomic(); 5024 5025 // Do force alignment of members that follow zero length bitfields. If 5026 // the alignment of the zero-length bitfield is greater than the member 5027 // that follows it, `bar', `bar' will be aligned as the type of the 5028 // zero length bitfield. 5029 UseZeroLengthBitfieldAlignment = true; 5030 5031 if (Triple.getOS() == llvm::Triple::Linux || 5032 Triple.getOS() == llvm::Triple::UnknownOS) 5033 this->MCountName = 5034 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5035 } 5036 5037 StringRef getABI() const override { return ABI; } 5038 5039 bool setABI(const std::string &Name) override { 5040 ABI = Name; 5041 5042 // The defaults (above) are for AAPCS, check if we need to change them. 5043 // 5044 // FIXME: We need support for -meabi... we could just mangle it into the 5045 // name. 5046 if (Name == "apcs-gnu" || Name == "aapcs16") { 5047 setABIAPCS(Name == "aapcs16"); 5048 return true; 5049 } 5050 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5051 setABIAAPCS(); 5052 return true; 5053 } 5054 return false; 5055 } 5056 5057 // FIXME: This should be based on Arch attributes, not CPU names. 5058 bool 5059 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5060 StringRef CPU, 5061 const std::vector<std::string> &FeaturesVec) const override { 5062 5063 std::vector<StringRef> TargetFeatures; 5064 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5065 5066 // get default FPU features 5067 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5068 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5069 5070 // get default Extension features 5071 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5072 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5073 5074 for (auto Feature : TargetFeatures) 5075 if (Feature[0] == '+') 5076 Features[Feature.drop_front(1)] = true; 5077 5078 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5079 } 5080 5081 bool handleTargetFeatures(std::vector<std::string> &Features, 5082 DiagnosticsEngine &Diags) override { 5083 FPU = 0; 5084 CRC = 0; 5085 Crypto = 0; 5086 DSP = 0; 5087 Unaligned = 1; 5088 SoftFloat = SoftFloatABI = false; 5089 HWDiv = 0; 5090 5091 // This does not diagnose illegal cases like having both 5092 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5093 uint32_t HW_FP_remove = 0; 5094 for (const auto &Feature : Features) { 5095 if (Feature == "+soft-float") { 5096 SoftFloat = true; 5097 } else if (Feature == "+soft-float-abi") { 5098 SoftFloatABI = true; 5099 } else if (Feature == "+vfp2") { 5100 FPU |= VFP2FPU; 5101 HW_FP |= HW_FP_SP | HW_FP_DP; 5102 } else if (Feature == "+vfp3") { 5103 FPU |= VFP3FPU; 5104 HW_FP |= HW_FP_SP | HW_FP_DP; 5105 } else if (Feature == "+vfp4") { 5106 FPU |= VFP4FPU; 5107 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5108 } else if (Feature == "+fp-armv8") { 5109 FPU |= FPARMV8; 5110 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5111 } else if (Feature == "+neon") { 5112 FPU |= NeonFPU; 5113 HW_FP |= HW_FP_SP | HW_FP_DP; 5114 } else if (Feature == "+hwdiv") { 5115 HWDiv |= HWDivThumb; 5116 } else if (Feature == "+hwdiv-arm") { 5117 HWDiv |= HWDivARM; 5118 } else if (Feature == "+crc") { 5119 CRC = 1; 5120 } else if (Feature == "+crypto") { 5121 Crypto = 1; 5122 } else if (Feature == "+dsp") { 5123 DSP = 1; 5124 } else if (Feature == "+fp-only-sp") { 5125 HW_FP_remove |= HW_FP_DP; 5126 } else if (Feature == "+strict-align") { 5127 Unaligned = 0; 5128 } else if (Feature == "+fp16") { 5129 HW_FP |= HW_FP_HP; 5130 } 5131 } 5132 HW_FP &= ~HW_FP_remove; 5133 5134 switch (ArchVersion) { 5135 case 6: 5136 if (ArchProfile == llvm::ARM::PK_M) 5137 LDREX = 0; 5138 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5139 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5140 else 5141 LDREX = LDREX_W; 5142 break; 5143 case 7: 5144 if (ArchProfile == llvm::ARM::PK_M) 5145 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5146 else 5147 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5148 break; 5149 case 8: 5150 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5151 } 5152 5153 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5154 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5155 return false; 5156 } 5157 5158 if (FPMath == FP_Neon) 5159 Features.push_back("+neonfp"); 5160 else if (FPMath == FP_VFP) 5161 Features.push_back("-neonfp"); 5162 5163 // Remove front-end specific options which the backend handles differently. 5164 auto Feature = 5165 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5166 if (Feature != Features.end()) 5167 Features.erase(Feature); 5168 5169 return true; 5170 } 5171 5172 bool hasFeature(StringRef Feature) const override { 5173 return llvm::StringSwitch<bool>(Feature) 5174 .Case("arm", true) 5175 .Case("aarch32", true) 5176 .Case("softfloat", SoftFloat) 5177 .Case("thumb", isThumb()) 5178 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5179 .Case("hwdiv", HWDiv & HWDivThumb) 5180 .Case("hwdiv-arm", HWDiv & HWDivARM) 5181 .Default(false); 5182 } 5183 5184 bool setCPU(const std::string &Name) override { 5185 if (Name != "generic") 5186 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5187 5188 if (ArchKind == llvm::ARM::AK_INVALID) 5189 return false; 5190 setAtomic(); 5191 CPU = Name; 5192 return true; 5193 } 5194 5195 bool setFPMath(StringRef Name) override; 5196 5197 void getTargetDefines(const LangOptions &Opts, 5198 MacroBuilder &Builder) const override { 5199 // Target identification. 5200 Builder.defineMacro("__arm"); 5201 Builder.defineMacro("__arm__"); 5202 // For bare-metal none-eabi. 5203 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5204 getTriple().getEnvironment() == llvm::Triple::EABI) 5205 Builder.defineMacro("__ELF__"); 5206 5207 // Target properties. 5208 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5209 5210 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5211 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5212 if (getTriple().isWatchABI()) 5213 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5214 5215 if (!CPUAttr.empty()) 5216 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5217 5218 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5219 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5220 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5221 5222 if (ArchVersion >= 8) { 5223 // ACLE 6.5.7 Crypto Extension 5224 if (Crypto) 5225 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5226 // ACLE 6.5.8 CRC32 Extension 5227 if (CRC) 5228 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5229 // ACLE 6.5.10 Numeric Maximum and Minimum 5230 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5231 // ACLE 6.5.9 Directed Rounding 5232 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5233 } 5234 5235 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5236 // is not defined for the M-profile. 5237 // NOTE that the default profile is assumed to be 'A' 5238 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5239 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5240 5241 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5242 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5243 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5244 // v7 and v8 architectures excluding v8-M Baseline. 5245 if (supportsThumb2()) 5246 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5247 else if (supportsThumb()) 5248 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5249 5250 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5251 // instruction set such as ARM or Thumb. 5252 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5253 5254 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5255 5256 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5257 if (!CPUProfile.empty()) 5258 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5259 5260 // ACLE 6.4.3 Unaligned access supported in hardware 5261 if (Unaligned) 5262 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5263 5264 // ACLE 6.4.4 LDREX/STREX 5265 if (LDREX) 5266 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5267 5268 // ACLE 6.4.5 CLZ 5269 if (ArchVersion == 5 || 5270 (ArchVersion == 6 && CPUProfile != "M") || 5271 ArchVersion > 6) 5272 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5273 5274 // ACLE 6.5.1 Hardware Floating Point 5275 if (HW_FP) 5276 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5277 5278 // ACLE predefines. 5279 Builder.defineMacro("__ARM_ACLE", "200"); 5280 5281 // FP16 support (we currently only support IEEE format). 5282 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5283 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5284 5285 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5286 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5287 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5288 5289 // Subtarget options. 5290 5291 // FIXME: It's more complicated than this and we don't really support 5292 // interworking. 5293 // Windows on ARM does not "support" interworking 5294 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5295 Builder.defineMacro("__THUMB_INTERWORK__"); 5296 5297 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5298 // Embedded targets on Darwin follow AAPCS, but not EABI. 5299 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5300 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5301 Builder.defineMacro("__ARM_EABI__"); 5302 Builder.defineMacro("__ARM_PCS", "1"); 5303 } 5304 5305 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5306 ABI == "aapcs16") 5307 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5308 5309 if (SoftFloat) 5310 Builder.defineMacro("__SOFTFP__"); 5311 5312 if (ArchKind == llvm::ARM::AK_XSCALE) 5313 Builder.defineMacro("__XSCALE__"); 5314 5315 if (isThumb()) { 5316 Builder.defineMacro("__THUMBEL__"); 5317 Builder.defineMacro("__thumb__"); 5318 if (supportsThumb2()) 5319 Builder.defineMacro("__thumb2__"); 5320 } 5321 5322 // ACLE 6.4.9 32-bit SIMD instructions 5323 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5324 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5325 5326 // ACLE 6.4.10 Hardware Integer Divide 5327 if (((HWDiv & HWDivThumb) && isThumb()) || 5328 ((HWDiv & HWDivARM) && !isThumb())) { 5329 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5330 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5331 } 5332 5333 // Note, this is always on in gcc, even though it doesn't make sense. 5334 Builder.defineMacro("__APCS_32__"); 5335 5336 if (FPUModeIsVFP((FPUMode) FPU)) { 5337 Builder.defineMacro("__VFP_FP__"); 5338 if (FPU & VFP2FPU) 5339 Builder.defineMacro("__ARM_VFPV2__"); 5340 if (FPU & VFP3FPU) 5341 Builder.defineMacro("__ARM_VFPV3__"); 5342 if (FPU & VFP4FPU) 5343 Builder.defineMacro("__ARM_VFPV4__"); 5344 } 5345 5346 // This only gets set when Neon instructions are actually available, unlike 5347 // the VFP define, hence the soft float and arch check. This is subtly 5348 // different from gcc, we follow the intent which was that it should be set 5349 // when Neon instructions are actually available. 5350 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5351 Builder.defineMacro("__ARM_NEON", "1"); 5352 Builder.defineMacro("__ARM_NEON__"); 5353 // current AArch32 NEON implementations do not support double-precision 5354 // floating-point even when it is present in VFP. 5355 Builder.defineMacro("__ARM_NEON_FP", 5356 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5357 } 5358 5359 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5360 Opts.ShortWChar ? "2" : "4"); 5361 5362 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5363 Opts.ShortEnums ? "1" : "4"); 5364 5365 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5366 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5367 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5368 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5369 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5370 } 5371 5372 // ACLE 6.4.7 DSP instructions 5373 if (DSP) { 5374 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5375 } 5376 5377 // ACLE 6.4.8 Saturation instructions 5378 bool SAT = false; 5379 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5380 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5381 SAT = true; 5382 } 5383 5384 // ACLE 6.4.6 Q (saturation) flag 5385 if (DSP || SAT) 5386 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5387 5388 if (Opts.UnsafeFPMath) 5389 Builder.defineMacro("__ARM_FP_FAST", "1"); 5390 5391 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5392 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5393 } 5394 5395 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5396 return llvm::makeArrayRef(BuiltinInfo, 5397 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5398 } 5399 bool isCLZForZeroUndef() const override { return false; } 5400 BuiltinVaListKind getBuiltinVaListKind() const override { 5401 return IsAAPCS 5402 ? AAPCSABIBuiltinVaList 5403 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5404 : TargetInfo::VoidPtrBuiltinVaList); 5405 } 5406 ArrayRef<const char *> getGCCRegNames() const override; 5407 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5408 bool validateAsmConstraint(const char *&Name, 5409 TargetInfo::ConstraintInfo &Info) const override { 5410 switch (*Name) { 5411 default: break; 5412 case 'l': // r0-r7 5413 case 'h': // r8-r15 5414 case 't': // VFP Floating point register single precision 5415 case 'w': // VFP Floating point register double precision 5416 Info.setAllowsRegister(); 5417 return true; 5418 case 'I': 5419 case 'J': 5420 case 'K': 5421 case 'L': 5422 case 'M': 5423 // FIXME 5424 return true; 5425 case 'Q': // A memory address that is a single base register. 5426 Info.setAllowsMemory(); 5427 return true; 5428 case 'U': // a memory reference... 5429 switch (Name[1]) { 5430 case 'q': // ...ARMV4 ldrsb 5431 case 'v': // ...VFP load/store (reg+constant offset) 5432 case 'y': // ...iWMMXt load/store 5433 case 't': // address valid for load/store opaque types wider 5434 // than 128-bits 5435 case 'n': // valid address for Neon doubleword vector load/store 5436 case 'm': // valid address for Neon element and structure load/store 5437 case 's': // valid address for non-offset loads/stores of quad-word 5438 // values in four ARM registers 5439 Info.setAllowsMemory(); 5440 Name++; 5441 return true; 5442 } 5443 } 5444 return false; 5445 } 5446 std::string convertConstraint(const char *&Constraint) const override { 5447 std::string R; 5448 switch (*Constraint) { 5449 case 'U': // Two-character constraint; add "^" hint for later parsing. 5450 R = std::string("^") + std::string(Constraint, 2); 5451 Constraint++; 5452 break; 5453 case 'p': // 'p' should be translated to 'r' by default. 5454 R = std::string("r"); 5455 break; 5456 default: 5457 return std::string(1, *Constraint); 5458 } 5459 return R; 5460 } 5461 bool 5462 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5463 std::string &SuggestedModifier) const override { 5464 bool isOutput = (Constraint[0] == '='); 5465 bool isInOut = (Constraint[0] == '+'); 5466 5467 // Strip off constraint modifiers. 5468 while (Constraint[0] == '=' || 5469 Constraint[0] == '+' || 5470 Constraint[0] == '&') 5471 Constraint = Constraint.substr(1); 5472 5473 switch (Constraint[0]) { 5474 default: break; 5475 case 'r': { 5476 switch (Modifier) { 5477 default: 5478 return (isInOut || isOutput || Size <= 64); 5479 case 'q': 5480 // A register of size 32 cannot fit a vector type. 5481 return false; 5482 } 5483 } 5484 } 5485 5486 return true; 5487 } 5488 const char *getClobbers() const override { 5489 // FIXME: Is this really right? 5490 return ""; 5491 } 5492 5493 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5494 switch (CC) { 5495 case CC_AAPCS: 5496 case CC_AAPCS_VFP: 5497 case CC_Swift: 5498 return CCCR_OK; 5499 default: 5500 return CCCR_Warning; 5501 } 5502 } 5503 5504 int getEHDataRegisterNumber(unsigned RegNo) const override { 5505 if (RegNo == 0) return 0; 5506 if (RegNo == 1) return 1; 5507 return -1; 5508 } 5509 5510 bool hasSjLjLowering() const override { 5511 return true; 5512 } 5513 }; 5514 5515 bool ARMTargetInfo::setFPMath(StringRef Name) { 5516 if (Name == "neon") { 5517 FPMath = FP_Neon; 5518 return true; 5519 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5520 Name == "vfp4") { 5521 FPMath = FP_VFP; 5522 return true; 5523 } 5524 return false; 5525 } 5526 5527 const char * const ARMTargetInfo::GCCRegNames[] = { 5528 // Integer registers 5529 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5530 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5531 5532 // Float registers 5533 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5534 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5535 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5536 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5537 5538 // Double registers 5539 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5540 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5541 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5542 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5543 5544 // Quad registers 5545 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5546 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5547 }; 5548 5549 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5550 return llvm::makeArrayRef(GCCRegNames); 5551 } 5552 5553 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5554 { { "a1" }, "r0" }, 5555 { { "a2" }, "r1" }, 5556 { { "a3" }, "r2" }, 5557 { { "a4" }, "r3" }, 5558 { { "v1" }, "r4" }, 5559 { { "v2" }, "r5" }, 5560 { { "v3" }, "r6" }, 5561 { { "v4" }, "r7" }, 5562 { { "v5" }, "r8" }, 5563 { { "v6", "rfp" }, "r9" }, 5564 { { "sl" }, "r10" }, 5565 { { "fp" }, "r11" }, 5566 { { "ip" }, "r12" }, 5567 { { "r13" }, "sp" }, 5568 { { "r14" }, "lr" }, 5569 { { "r15" }, "pc" }, 5570 // The S, D and Q registers overlap, but aren't really aliases; we 5571 // don't want to substitute one of these for a different-sized one. 5572 }; 5573 5574 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5575 return llvm::makeArrayRef(GCCRegAliases); 5576 } 5577 5578 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5579 #define BUILTIN(ID, TYPE, ATTRS) \ 5580 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5581 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5582 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5583 #include "clang/Basic/BuiltinsNEON.def" 5584 5585 #define BUILTIN(ID, TYPE, ATTRS) \ 5586 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5587 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5588 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5589 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5590 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5591 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5592 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5593 #include "clang/Basic/BuiltinsARM.def" 5594 }; 5595 5596 class ARMleTargetInfo : public ARMTargetInfo { 5597 public: 5598 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5599 : ARMTargetInfo(Triple, Opts) {} 5600 void getTargetDefines(const LangOptions &Opts, 5601 MacroBuilder &Builder) const override { 5602 Builder.defineMacro("__ARMEL__"); 5603 ARMTargetInfo::getTargetDefines(Opts, Builder); 5604 } 5605 }; 5606 5607 class ARMbeTargetInfo : public ARMTargetInfo { 5608 public: 5609 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5610 : ARMTargetInfo(Triple, Opts) {} 5611 void getTargetDefines(const LangOptions &Opts, 5612 MacroBuilder &Builder) const override { 5613 Builder.defineMacro("__ARMEB__"); 5614 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5615 ARMTargetInfo::getTargetDefines(Opts, Builder); 5616 } 5617 }; 5618 5619 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5620 const llvm::Triple Triple; 5621 public: 5622 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5623 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5624 WCharType = UnsignedShort; 5625 SizeType = UnsignedInt; 5626 } 5627 void getVisualStudioDefines(const LangOptions &Opts, 5628 MacroBuilder &Builder) const { 5629 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5630 5631 // FIXME: this is invalid for WindowsCE 5632 Builder.defineMacro("_M_ARM_NT", "1"); 5633 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5634 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5635 5636 assert((Triple.getArch() == llvm::Triple::arm || 5637 Triple.getArch() == llvm::Triple::thumb) && 5638 "invalid architecture for Windows ARM target info"); 5639 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5640 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5641 5642 // TODO map the complete set of values 5643 // 31: VFPv3 40: VFPv4 5644 Builder.defineMacro("_M_ARM_FP", "31"); 5645 } 5646 BuiltinVaListKind getBuiltinVaListKind() const override { 5647 return TargetInfo::CharPtrBuiltinVaList; 5648 } 5649 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5650 switch (CC) { 5651 case CC_X86StdCall: 5652 case CC_X86ThisCall: 5653 case CC_X86FastCall: 5654 case CC_X86VectorCall: 5655 return CCCR_Ignore; 5656 case CC_C: 5657 return CCCR_OK; 5658 default: 5659 return CCCR_Warning; 5660 } 5661 } 5662 }; 5663 5664 // Windows ARM + Itanium C++ ABI Target 5665 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5666 public: 5667 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5668 const TargetOptions &Opts) 5669 : WindowsARMTargetInfo(Triple, Opts) { 5670 TheCXXABI.set(TargetCXXABI::GenericARM); 5671 } 5672 5673 void getTargetDefines(const LangOptions &Opts, 5674 MacroBuilder &Builder) const override { 5675 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5676 5677 if (Opts.MSVCCompat) 5678 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5679 } 5680 }; 5681 5682 // Windows ARM, MS (C++) ABI 5683 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5684 public: 5685 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5686 const TargetOptions &Opts) 5687 : WindowsARMTargetInfo(Triple, Opts) { 5688 TheCXXABI.set(TargetCXXABI::Microsoft); 5689 } 5690 5691 void getTargetDefines(const LangOptions &Opts, 5692 MacroBuilder &Builder) const override { 5693 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5694 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5695 } 5696 }; 5697 5698 // ARM MinGW target 5699 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5700 public: 5701 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5702 : WindowsARMTargetInfo(Triple, Opts) { 5703 TheCXXABI.set(TargetCXXABI::GenericARM); 5704 } 5705 5706 void getTargetDefines(const LangOptions &Opts, 5707 MacroBuilder &Builder) const override { 5708 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5709 DefineStd(Builder, "WIN32", Opts); 5710 DefineStd(Builder, "WINNT", Opts); 5711 Builder.defineMacro("_ARM_"); 5712 addMinGWDefines(Opts, Builder); 5713 } 5714 }; 5715 5716 // ARM Cygwin target 5717 class CygwinARMTargetInfo : public ARMleTargetInfo { 5718 public: 5719 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5720 : ARMleTargetInfo(Triple, Opts) { 5721 TLSSupported = false; 5722 WCharType = UnsignedShort; 5723 DoubleAlign = LongLongAlign = 64; 5724 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5725 } 5726 void getTargetDefines(const LangOptions &Opts, 5727 MacroBuilder &Builder) const override { 5728 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5729 Builder.defineMacro("_ARM_"); 5730 Builder.defineMacro("__CYGWIN__"); 5731 Builder.defineMacro("__CYGWIN32__"); 5732 DefineStd(Builder, "unix", Opts); 5733 if (Opts.CPlusPlus) 5734 Builder.defineMacro("_GNU_SOURCE"); 5735 } 5736 }; 5737 5738 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5739 protected: 5740 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5741 MacroBuilder &Builder) const override { 5742 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5743 } 5744 5745 public: 5746 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5747 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5748 HasAlignMac68kSupport = true; 5749 // iOS always has 64-bit atomic instructions. 5750 // FIXME: This should be based off of the target features in 5751 // ARMleTargetInfo. 5752 MaxAtomicInlineWidth = 64; 5753 5754 if (Triple.isWatchABI()) { 5755 // Darwin on iOS uses a variant of the ARM C++ ABI. 5756 TheCXXABI.set(TargetCXXABI::WatchOS); 5757 5758 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5759 // size_t is long, it's a bit weird for it to be int. 5760 PtrDiffType = SignedLong; 5761 5762 // BOOL should be a real boolean on the new ABI 5763 UseSignedCharForObjCBool = false; 5764 } else 5765 TheCXXABI.set(TargetCXXABI::iOS); 5766 } 5767 }; 5768 5769 class AArch64TargetInfo : public TargetInfo { 5770 virtual void setDataLayout() = 0; 5771 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5772 static const char *const GCCRegNames[]; 5773 5774 enum FPUModeEnum { 5775 FPUMode, 5776 NeonMode 5777 }; 5778 5779 unsigned FPU; 5780 unsigned CRC; 5781 unsigned Crypto; 5782 unsigned Unaligned; 5783 unsigned V8_1A; 5784 5785 static const Builtin::Info BuiltinInfo[]; 5786 5787 std::string ABI; 5788 5789 public: 5790 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5791 : TargetInfo(Triple), ABI("aapcs") { 5792 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5793 WCharType = SignedInt; 5794 5795 // NetBSD apparently prefers consistency across ARM targets to consistency 5796 // across 64-bit targets. 5797 Int64Type = SignedLongLong; 5798 IntMaxType = SignedLongLong; 5799 } else { 5800 WCharType = UnsignedInt; 5801 Int64Type = SignedLong; 5802 IntMaxType = SignedLong; 5803 } 5804 5805 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5806 MaxVectorAlign = 128; 5807 MaxAtomicInlineWidth = 128; 5808 MaxAtomicPromoteWidth = 128; 5809 5810 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5811 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5812 5813 // {} in inline assembly are neon specifiers, not assembly variant 5814 // specifiers. 5815 NoAsmVariants = true; 5816 5817 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5818 // contributes to the alignment of the containing aggregate in the same way 5819 // a plain (non bit-field) member of that type would, without exception for 5820 // zero-sized or anonymous bit-fields." 5821 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5822 UseZeroLengthBitfieldAlignment = true; 5823 5824 // AArch64 targets default to using the ARM C++ ABI. 5825 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5826 5827 if (Triple.getOS() == llvm::Triple::Linux || 5828 Triple.getOS() == llvm::Triple::UnknownOS) 5829 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5830 } 5831 5832 StringRef getABI() const override { return ABI; } 5833 bool setABI(const std::string &Name) override { 5834 if (Name != "aapcs" && Name != "darwinpcs") 5835 return false; 5836 5837 ABI = Name; 5838 return true; 5839 } 5840 5841 bool setCPU(const std::string &Name) override { 5842 return Name == "generic" || 5843 llvm::AArch64::parseCPUArch(Name) != 5844 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 5845 } 5846 5847 void getTargetDefines(const LangOptions &Opts, 5848 MacroBuilder &Builder) const override { 5849 // Target identification. 5850 Builder.defineMacro("__aarch64__"); 5851 5852 // Target properties. 5853 Builder.defineMacro("_LP64"); 5854 Builder.defineMacro("__LP64__"); 5855 5856 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5857 Builder.defineMacro("__ARM_ACLE", "200"); 5858 Builder.defineMacro("__ARM_ARCH", "8"); 5859 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5860 5861 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5862 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5863 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5864 5865 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5866 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5867 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5868 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5869 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5870 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5871 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5872 5873 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5874 5875 // 0xe implies support for half, single and double precision operations. 5876 Builder.defineMacro("__ARM_FP", "0xE"); 5877 5878 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5879 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5880 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5881 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5882 5883 if (Opts.UnsafeFPMath) 5884 Builder.defineMacro("__ARM_FP_FAST", "1"); 5885 5886 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5887 5888 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5889 Opts.ShortEnums ? "1" : "4"); 5890 5891 if (FPU == NeonMode) { 5892 Builder.defineMacro("__ARM_NEON", "1"); 5893 // 64-bit NEON supports half, single and double precision operations. 5894 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5895 } 5896 5897 if (CRC) 5898 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5899 5900 if (Crypto) 5901 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5902 5903 if (Unaligned) 5904 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5905 5906 if (V8_1A) 5907 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5908 5909 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5910 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5911 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5912 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5913 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5914 } 5915 5916 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5917 return llvm::makeArrayRef(BuiltinInfo, 5918 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5919 } 5920 5921 bool hasFeature(StringRef Feature) const override { 5922 return Feature == "aarch64" || 5923 Feature == "arm64" || 5924 Feature == "arm" || 5925 (Feature == "neon" && FPU == NeonMode); 5926 } 5927 5928 bool handleTargetFeatures(std::vector<std::string> &Features, 5929 DiagnosticsEngine &Diags) override { 5930 FPU = FPUMode; 5931 CRC = 0; 5932 Crypto = 0; 5933 Unaligned = 1; 5934 V8_1A = 0; 5935 5936 for (const auto &Feature : Features) { 5937 if (Feature == "+neon") 5938 FPU = NeonMode; 5939 if (Feature == "+crc") 5940 CRC = 1; 5941 if (Feature == "+crypto") 5942 Crypto = 1; 5943 if (Feature == "+strict-align") 5944 Unaligned = 0; 5945 if (Feature == "+v8.1a") 5946 V8_1A = 1; 5947 } 5948 5949 setDataLayout(); 5950 5951 return true; 5952 } 5953 5954 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5955 switch (CC) { 5956 case CC_C: 5957 case CC_Swift: 5958 case CC_PreserveMost: 5959 case CC_PreserveAll: 5960 return CCCR_OK; 5961 default: 5962 return CCCR_Warning; 5963 } 5964 } 5965 5966 bool isCLZForZeroUndef() const override { return false; } 5967 5968 BuiltinVaListKind getBuiltinVaListKind() const override { 5969 return TargetInfo::AArch64ABIBuiltinVaList; 5970 } 5971 5972 ArrayRef<const char *> getGCCRegNames() const override; 5973 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5974 5975 bool validateAsmConstraint(const char *&Name, 5976 TargetInfo::ConstraintInfo &Info) const override { 5977 switch (*Name) { 5978 default: 5979 return false; 5980 case 'w': // Floating point and SIMD registers (V0-V31) 5981 Info.setAllowsRegister(); 5982 return true; 5983 case 'I': // Constant that can be used with an ADD instruction 5984 case 'J': // Constant that can be used with a SUB instruction 5985 case 'K': // Constant that can be used with a 32-bit logical instruction 5986 case 'L': // Constant that can be used with a 64-bit logical instruction 5987 case 'M': // Constant that can be used as a 32-bit MOV immediate 5988 case 'N': // Constant that can be used as a 64-bit MOV immediate 5989 case 'Y': // Floating point constant zero 5990 case 'Z': // Integer constant zero 5991 return true; 5992 case 'Q': // A memory reference with base register and no offset 5993 Info.setAllowsMemory(); 5994 return true; 5995 case 'S': // A symbolic address 5996 Info.setAllowsRegister(); 5997 return true; 5998 case 'U': 5999 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6000 // Utf: A memory address suitable for ldp/stp in TF mode. 6001 // Usa: An absolute symbolic address. 6002 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6003 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6004 case 'z': // Zero register, wzr or xzr 6005 Info.setAllowsRegister(); 6006 return true; 6007 case 'x': // Floating point and SIMD registers (V0-V15) 6008 Info.setAllowsRegister(); 6009 return true; 6010 } 6011 return false; 6012 } 6013 6014 bool 6015 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6016 std::string &SuggestedModifier) const override { 6017 // Strip off constraint modifiers. 6018 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6019 Constraint = Constraint.substr(1); 6020 6021 switch (Constraint[0]) { 6022 default: 6023 return true; 6024 case 'z': 6025 case 'r': { 6026 switch (Modifier) { 6027 case 'x': 6028 case 'w': 6029 // For now assume that the person knows what they're 6030 // doing with the modifier. 6031 return true; 6032 default: 6033 // By default an 'r' constraint will be in the 'x' 6034 // registers. 6035 if (Size == 64) 6036 return true; 6037 6038 SuggestedModifier = "w"; 6039 return false; 6040 } 6041 } 6042 } 6043 } 6044 6045 const char *getClobbers() const override { return ""; } 6046 6047 int getEHDataRegisterNumber(unsigned RegNo) const override { 6048 if (RegNo == 0) 6049 return 0; 6050 if (RegNo == 1) 6051 return 1; 6052 return -1; 6053 } 6054 }; 6055 6056 const char *const AArch64TargetInfo::GCCRegNames[] = { 6057 // 32-bit Integer registers 6058 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6059 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6060 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6061 6062 // 64-bit Integer registers 6063 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6064 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6065 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6066 6067 // 32-bit floating point regsisters 6068 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6069 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6070 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6071 6072 // 64-bit floating point regsisters 6073 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6074 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6075 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6076 6077 // Vector registers 6078 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6079 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6080 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6081 }; 6082 6083 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6084 return llvm::makeArrayRef(GCCRegNames); 6085 } 6086 6087 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6088 { { "w31" }, "wsp" }, 6089 { { "x29" }, "fp" }, 6090 { { "x30" }, "lr" }, 6091 { { "x31" }, "sp" }, 6092 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6093 // don't want to substitute one of these for a different-sized one. 6094 }; 6095 6096 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6097 return llvm::makeArrayRef(GCCRegAliases); 6098 } 6099 6100 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6101 #define BUILTIN(ID, TYPE, ATTRS) \ 6102 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6103 #include "clang/Basic/BuiltinsNEON.def" 6104 6105 #define BUILTIN(ID, TYPE, ATTRS) \ 6106 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6107 #include "clang/Basic/BuiltinsAArch64.def" 6108 }; 6109 6110 class AArch64leTargetInfo : public AArch64TargetInfo { 6111 void setDataLayout() override { 6112 if (getTriple().isOSBinFormatMachO()) 6113 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6114 else 6115 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6116 } 6117 6118 public: 6119 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6120 : AArch64TargetInfo(Triple, Opts) { 6121 } 6122 void getTargetDefines(const LangOptions &Opts, 6123 MacroBuilder &Builder) const override { 6124 Builder.defineMacro("__AARCH64EL__"); 6125 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6126 } 6127 }; 6128 6129 class AArch64beTargetInfo : public AArch64TargetInfo { 6130 void setDataLayout() override { 6131 assert(!getTriple().isOSBinFormatMachO()); 6132 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6133 } 6134 6135 public: 6136 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6137 : AArch64TargetInfo(Triple, Opts) {} 6138 void getTargetDefines(const LangOptions &Opts, 6139 MacroBuilder &Builder) const override { 6140 Builder.defineMacro("__AARCH64EB__"); 6141 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6142 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6143 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6144 } 6145 }; 6146 6147 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6148 protected: 6149 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6150 MacroBuilder &Builder) const override { 6151 Builder.defineMacro("__AARCH64_SIMD__"); 6152 Builder.defineMacro("__ARM64_ARCH_8__"); 6153 Builder.defineMacro("__ARM_NEON__"); 6154 Builder.defineMacro("__LITTLE_ENDIAN__"); 6155 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6156 Builder.defineMacro("__arm64", "1"); 6157 Builder.defineMacro("__arm64__", "1"); 6158 6159 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6160 } 6161 6162 public: 6163 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6164 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6165 Int64Type = SignedLongLong; 6166 WCharType = SignedInt; 6167 UseSignedCharForObjCBool = false; 6168 6169 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6170 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6171 6172 TheCXXABI.set(TargetCXXABI::iOS64); 6173 } 6174 6175 BuiltinVaListKind getBuiltinVaListKind() const override { 6176 return TargetInfo::CharPtrBuiltinVaList; 6177 } 6178 }; 6179 6180 // Hexagon abstract base class 6181 class HexagonTargetInfo : public TargetInfo { 6182 static const Builtin::Info BuiltinInfo[]; 6183 static const char * const GCCRegNames[]; 6184 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6185 std::string CPU; 6186 bool HasHVX, HasHVXDouble; 6187 bool UseLongCalls; 6188 6189 public: 6190 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6191 : TargetInfo(Triple) { 6192 // Specify the vector alignment explicitly. For v512x1, the calculated 6193 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6194 // the required minimum of 64 bytes. 6195 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6196 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6197 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6198 SizeType = UnsignedInt; 6199 PtrDiffType = SignedInt; 6200 IntPtrType = SignedInt; 6201 6202 // {} in inline assembly are packet specifiers, not assembly variant 6203 // specifiers. 6204 NoAsmVariants = true; 6205 6206 LargeArrayMinWidth = 64; 6207 LargeArrayAlign = 64; 6208 UseBitFieldTypeAlignment = true; 6209 ZeroLengthBitfieldBoundary = 32; 6210 HasHVX = HasHVXDouble = false; 6211 UseLongCalls = false; 6212 } 6213 6214 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6215 return llvm::makeArrayRef(BuiltinInfo, 6216 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6217 } 6218 6219 bool validateAsmConstraint(const char *&Name, 6220 TargetInfo::ConstraintInfo &Info) const override { 6221 switch (*Name) { 6222 case 'v': 6223 case 'q': 6224 if (HasHVX) { 6225 Info.setAllowsRegister(); 6226 return true; 6227 } 6228 break; 6229 case 's': 6230 // Relocatable constant. 6231 return true; 6232 } 6233 return false; 6234 } 6235 6236 void getTargetDefines(const LangOptions &Opts, 6237 MacroBuilder &Builder) const override; 6238 6239 bool isCLZForZeroUndef() const override { return false; } 6240 6241 bool hasFeature(StringRef Feature) const override { 6242 return llvm::StringSwitch<bool>(Feature) 6243 .Case("hexagon", true) 6244 .Case("hvx", HasHVX) 6245 .Case("hvx-double", HasHVXDouble) 6246 .Case("long-calls", UseLongCalls) 6247 .Default(false); 6248 } 6249 6250 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6251 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6252 const override; 6253 6254 bool handleTargetFeatures(std::vector<std::string> &Features, 6255 DiagnosticsEngine &Diags) override; 6256 6257 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6258 bool Enabled) const override; 6259 6260 BuiltinVaListKind getBuiltinVaListKind() const override { 6261 return TargetInfo::CharPtrBuiltinVaList; 6262 } 6263 ArrayRef<const char *> getGCCRegNames() const override; 6264 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6265 const char *getClobbers() const override { 6266 return ""; 6267 } 6268 6269 static const char *getHexagonCPUSuffix(StringRef Name) { 6270 return llvm::StringSwitch<const char*>(Name) 6271 .Case("hexagonv4", "4") 6272 .Case("hexagonv5", "5") 6273 .Case("hexagonv55", "55") 6274 .Case("hexagonv60", "60") 6275 .Default(nullptr); 6276 } 6277 6278 bool setCPU(const std::string &Name) override { 6279 if (!getHexagonCPUSuffix(Name)) 6280 return false; 6281 CPU = Name; 6282 return true; 6283 } 6284 6285 int getEHDataRegisterNumber(unsigned RegNo) const override { 6286 return RegNo < 2 ? RegNo : -1; 6287 } 6288 }; 6289 6290 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6291 MacroBuilder &Builder) const { 6292 Builder.defineMacro("__qdsp6__", "1"); 6293 Builder.defineMacro("__hexagon__", "1"); 6294 6295 if (CPU == "hexagonv4") { 6296 Builder.defineMacro("__HEXAGON_V4__"); 6297 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6298 if (Opts.HexagonQdsp6Compat) { 6299 Builder.defineMacro("__QDSP6_V4__"); 6300 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6301 } 6302 } else if (CPU == "hexagonv5") { 6303 Builder.defineMacro("__HEXAGON_V5__"); 6304 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6305 if(Opts.HexagonQdsp6Compat) { 6306 Builder.defineMacro("__QDSP6_V5__"); 6307 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6308 } 6309 } else if (CPU == "hexagonv55") { 6310 Builder.defineMacro("__HEXAGON_V55__"); 6311 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6312 Builder.defineMacro("__QDSP6_V55__"); 6313 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6314 } else if (CPU == "hexagonv60") { 6315 Builder.defineMacro("__HEXAGON_V60__"); 6316 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6317 Builder.defineMacro("__QDSP6_V60__"); 6318 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6319 } 6320 6321 if (hasFeature("hvx")) { 6322 Builder.defineMacro("__HVX__"); 6323 if (hasFeature("hvx-double")) 6324 Builder.defineMacro("__HVXDBL__"); 6325 } 6326 } 6327 6328 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6329 DiagnosticsEngine &Diags, StringRef CPU, 6330 const std::vector<std::string> &FeaturesVec) const { 6331 // Default for v60: -hvx, -hvx-double. 6332 Features["hvx"] = false; 6333 Features["hvx-double"] = false; 6334 Features["long-calls"] = false; 6335 6336 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6337 } 6338 6339 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6340 DiagnosticsEngine &Diags) { 6341 for (auto &F : Features) { 6342 if (F == "+hvx") 6343 HasHVX = true; 6344 else if (F == "-hvx") 6345 HasHVX = HasHVXDouble = false; 6346 else if (F == "+hvx-double") 6347 HasHVX = HasHVXDouble = true; 6348 else if (F == "-hvx-double") 6349 HasHVXDouble = false; 6350 6351 if (F == "+long-calls") 6352 UseLongCalls = true; 6353 else if (F == "-long-calls") 6354 UseLongCalls = false; 6355 } 6356 return true; 6357 } 6358 6359 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6360 StringRef Name, bool Enabled) const { 6361 if (Enabled) { 6362 if (Name == "hvx-double") 6363 Features["hvx"] = true; 6364 } else { 6365 if (Name == "hvx") 6366 Features["hvx-double"] = false; 6367 } 6368 Features[Name] = Enabled; 6369 } 6370 6371 const char *const HexagonTargetInfo::GCCRegNames[] = { 6372 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6373 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6374 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6375 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6376 "p0", "p1", "p2", "p3", 6377 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6378 }; 6379 6380 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6381 return llvm::makeArrayRef(GCCRegNames); 6382 } 6383 6384 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6385 { { "sp" }, "r29" }, 6386 { { "fp" }, "r30" }, 6387 { { "lr" }, "r31" }, 6388 }; 6389 6390 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6391 return llvm::makeArrayRef(GCCRegAliases); 6392 } 6393 6394 6395 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6396 #define BUILTIN(ID, TYPE, ATTRS) \ 6397 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6398 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6399 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6400 #include "clang/Basic/BuiltinsHexagon.def" 6401 }; 6402 6403 class LanaiTargetInfo : public TargetInfo { 6404 // Class for Lanai (32-bit). 6405 // The CPU profiles supported by the Lanai backend 6406 enum CPUKind { 6407 CK_NONE, 6408 CK_V11, 6409 } CPU; 6410 6411 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6412 static const char *const GCCRegNames[]; 6413 6414 public: 6415 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6416 : TargetInfo(Triple) { 6417 // Description string has to be kept in sync with backend. 6418 resetDataLayout("E" // Big endian 6419 "-m:e" // ELF name manging 6420 "-p:32:32" // 32 bit pointers, 32 bit aligned 6421 "-i64:64" // 64 bit integers, 64 bit aligned 6422 "-a:0:32" // 32 bit alignment of objects of aggregate type 6423 "-n32" // 32 bit native integer width 6424 "-S64" // 64 bit natural stack alignment 6425 ); 6426 6427 // Setting RegParmMax equal to what mregparm was set to in the old 6428 // toolchain 6429 RegParmMax = 4; 6430 6431 // Set the default CPU to V11 6432 CPU = CK_V11; 6433 6434 // Temporary approach to make everything at least word-aligned and allow for 6435 // safely casting between pointers with different alignment requirements. 6436 // TODO: Remove this when there are no more cast align warnings on the 6437 // firmware. 6438 MinGlobalAlign = 32; 6439 } 6440 6441 void getTargetDefines(const LangOptions &Opts, 6442 MacroBuilder &Builder) const override { 6443 // Define __lanai__ when building for target lanai. 6444 Builder.defineMacro("__lanai__"); 6445 6446 // Set define for the CPU specified. 6447 switch (CPU) { 6448 case CK_V11: 6449 Builder.defineMacro("__LANAI_V11__"); 6450 break; 6451 case CK_NONE: 6452 llvm_unreachable("Unhandled target CPU"); 6453 } 6454 } 6455 6456 bool setCPU(const std::string &Name) override { 6457 CPU = llvm::StringSwitch<CPUKind>(Name) 6458 .Case("v11", CK_V11) 6459 .Default(CK_NONE); 6460 6461 return CPU != CK_NONE; 6462 } 6463 6464 bool hasFeature(StringRef Feature) const override { 6465 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6466 } 6467 6468 ArrayRef<const char *> getGCCRegNames() const override; 6469 6470 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6471 6472 BuiltinVaListKind getBuiltinVaListKind() const override { 6473 return TargetInfo::VoidPtrBuiltinVaList; 6474 } 6475 6476 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6477 6478 bool validateAsmConstraint(const char *&Name, 6479 TargetInfo::ConstraintInfo &info) const override { 6480 return false; 6481 } 6482 6483 const char *getClobbers() const override { return ""; } 6484 }; 6485 6486 const char *const LanaiTargetInfo::GCCRegNames[] = { 6487 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6488 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6489 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6490 6491 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6492 return llvm::makeArrayRef(GCCRegNames); 6493 } 6494 6495 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6496 {{"pc"}, "r2"}, 6497 {{"sp"}, "r4"}, 6498 {{"fp"}, "r5"}, 6499 {{"rv"}, "r8"}, 6500 {{"rr1"}, "r10"}, 6501 {{"rr2"}, "r11"}, 6502 {{"rca"}, "r15"}, 6503 }; 6504 6505 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6506 return llvm::makeArrayRef(GCCRegAliases); 6507 } 6508 6509 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6510 class SparcTargetInfo : public TargetInfo { 6511 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6512 static const char * const GCCRegNames[]; 6513 bool SoftFloat; 6514 public: 6515 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6516 : TargetInfo(Triple), SoftFloat(false) {} 6517 6518 int getEHDataRegisterNumber(unsigned RegNo) const override { 6519 if (RegNo == 0) return 24; 6520 if (RegNo == 1) return 25; 6521 return -1; 6522 } 6523 6524 bool handleTargetFeatures(std::vector<std::string> &Features, 6525 DiagnosticsEngine &Diags) override { 6526 // Check if software floating point is enabled 6527 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6528 if (Feature != Features.end()) { 6529 SoftFloat = true; 6530 } 6531 return true; 6532 } 6533 void getTargetDefines(const LangOptions &Opts, 6534 MacroBuilder &Builder) const override { 6535 DefineStd(Builder, "sparc", Opts); 6536 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6537 6538 if (SoftFloat) 6539 Builder.defineMacro("SOFT_FLOAT", "1"); 6540 } 6541 6542 bool hasFeature(StringRef Feature) const override { 6543 return llvm::StringSwitch<bool>(Feature) 6544 .Case("softfloat", SoftFloat) 6545 .Case("sparc", true) 6546 .Default(false); 6547 } 6548 6549 bool hasSjLjLowering() const override { 6550 return true; 6551 } 6552 6553 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6554 // FIXME: Implement! 6555 return None; 6556 } 6557 BuiltinVaListKind getBuiltinVaListKind() const override { 6558 return TargetInfo::VoidPtrBuiltinVaList; 6559 } 6560 ArrayRef<const char *> getGCCRegNames() const override; 6561 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6562 bool validateAsmConstraint(const char *&Name, 6563 TargetInfo::ConstraintInfo &info) const override { 6564 // FIXME: Implement! 6565 switch (*Name) { 6566 case 'I': // Signed 13-bit constant 6567 case 'J': // Zero 6568 case 'K': // 32-bit constant with the low 12 bits clear 6569 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6570 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6571 case 'N': // Same as 'K' but zext (required for SIMode) 6572 case 'O': // The constant 4096 6573 return true; 6574 } 6575 return false; 6576 } 6577 const char *getClobbers() const override { 6578 // FIXME: Implement! 6579 return ""; 6580 } 6581 6582 // No Sparc V7 for now, the backend doesn't support it anyway. 6583 enum CPUKind { 6584 CK_GENERIC, 6585 CK_V8, 6586 CK_SUPERSPARC, 6587 CK_SPARCLITE, 6588 CK_F934, 6589 CK_HYPERSPARC, 6590 CK_SPARCLITE86X, 6591 CK_SPARCLET, 6592 CK_TSC701, 6593 CK_V9, 6594 CK_ULTRASPARC, 6595 CK_ULTRASPARC3, 6596 CK_NIAGARA, 6597 CK_NIAGARA2, 6598 CK_NIAGARA3, 6599 CK_NIAGARA4, 6600 CK_MYRIAD2100, 6601 CK_MYRIAD2150, 6602 CK_MYRIAD2450, 6603 CK_LEON2, 6604 CK_LEON2_AT697E, 6605 CK_LEON2_AT697F, 6606 CK_LEON3, 6607 CK_LEON3_UT699, 6608 CK_LEON3_GR712RC, 6609 CK_LEON4, 6610 CK_LEON4_GR740 6611 } CPU = CK_GENERIC; 6612 6613 enum CPUGeneration { 6614 CG_V8, 6615 CG_V9, 6616 }; 6617 6618 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6619 switch (Kind) { 6620 case CK_GENERIC: 6621 case CK_V8: 6622 case CK_SUPERSPARC: 6623 case CK_SPARCLITE: 6624 case CK_F934: 6625 case CK_HYPERSPARC: 6626 case CK_SPARCLITE86X: 6627 case CK_SPARCLET: 6628 case CK_TSC701: 6629 case CK_MYRIAD2100: 6630 case CK_MYRIAD2150: 6631 case CK_MYRIAD2450: 6632 case CK_LEON2: 6633 case CK_LEON2_AT697E: 6634 case CK_LEON2_AT697F: 6635 case CK_LEON3: 6636 case CK_LEON3_UT699: 6637 case CK_LEON3_GR712RC: 6638 case CK_LEON4: 6639 case CK_LEON4_GR740: 6640 return CG_V8; 6641 case CK_V9: 6642 case CK_ULTRASPARC: 6643 case CK_ULTRASPARC3: 6644 case CK_NIAGARA: 6645 case CK_NIAGARA2: 6646 case CK_NIAGARA3: 6647 case CK_NIAGARA4: 6648 return CG_V9; 6649 } 6650 llvm_unreachable("Unexpected CPU kind"); 6651 } 6652 6653 CPUKind getCPUKind(StringRef Name) const { 6654 return llvm::StringSwitch<CPUKind>(Name) 6655 .Case("v8", CK_V8) 6656 .Case("supersparc", CK_SUPERSPARC) 6657 .Case("sparclite", CK_SPARCLITE) 6658 .Case("f934", CK_F934) 6659 .Case("hypersparc", CK_HYPERSPARC) 6660 .Case("sparclite86x", CK_SPARCLITE86X) 6661 .Case("sparclet", CK_SPARCLET) 6662 .Case("tsc701", CK_TSC701) 6663 .Case("v9", CK_V9) 6664 .Case("ultrasparc", CK_ULTRASPARC) 6665 .Case("ultrasparc3", CK_ULTRASPARC3) 6666 .Case("niagara", CK_NIAGARA) 6667 .Case("niagara2", CK_NIAGARA2) 6668 .Case("niagara3", CK_NIAGARA3) 6669 .Case("niagara4", CK_NIAGARA4) 6670 .Case("ma2100", CK_MYRIAD2100) 6671 .Case("ma2150", CK_MYRIAD2150) 6672 .Case("ma2450", CK_MYRIAD2450) 6673 // FIXME: the myriad2[.n] spellings are obsolete, 6674 // but a grace period is needed to allow updating dependent builds. 6675 .Case("myriad2", CK_MYRIAD2100) 6676 .Case("myriad2.1", CK_MYRIAD2100) 6677 .Case("myriad2.2", CK_MYRIAD2150) 6678 .Case("leon2", CK_LEON2) 6679 .Case("at697e", CK_LEON2_AT697E) 6680 .Case("at697f", CK_LEON2_AT697F) 6681 .Case("leon3", CK_LEON3) 6682 .Case("ut699", CK_LEON3_UT699) 6683 .Case("gr712rc", CK_LEON3_GR712RC) 6684 .Case("leon4", CK_LEON4) 6685 .Case("gr740", CK_LEON4_GR740) 6686 .Default(CK_GENERIC); 6687 } 6688 6689 bool setCPU(const std::string &Name) override { 6690 CPU = getCPUKind(Name); 6691 return CPU != CK_GENERIC; 6692 } 6693 }; 6694 6695 const char * const SparcTargetInfo::GCCRegNames[] = { 6696 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6697 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6698 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6699 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6700 }; 6701 6702 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6703 return llvm::makeArrayRef(GCCRegNames); 6704 } 6705 6706 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6707 { { "g0" }, "r0" }, 6708 { { "g1" }, "r1" }, 6709 { { "g2" }, "r2" }, 6710 { { "g3" }, "r3" }, 6711 { { "g4" }, "r4" }, 6712 { { "g5" }, "r5" }, 6713 { { "g6" }, "r6" }, 6714 { { "g7" }, "r7" }, 6715 { { "o0" }, "r8" }, 6716 { { "o1" }, "r9" }, 6717 { { "o2" }, "r10" }, 6718 { { "o3" }, "r11" }, 6719 { { "o4" }, "r12" }, 6720 { { "o5" }, "r13" }, 6721 { { "o6", "sp" }, "r14" }, 6722 { { "o7" }, "r15" }, 6723 { { "l0" }, "r16" }, 6724 { { "l1" }, "r17" }, 6725 { { "l2" }, "r18" }, 6726 { { "l3" }, "r19" }, 6727 { { "l4" }, "r20" }, 6728 { { "l5" }, "r21" }, 6729 { { "l6" }, "r22" }, 6730 { { "l7" }, "r23" }, 6731 { { "i0" }, "r24" }, 6732 { { "i1" }, "r25" }, 6733 { { "i2" }, "r26" }, 6734 { { "i3" }, "r27" }, 6735 { { "i4" }, "r28" }, 6736 { { "i5" }, "r29" }, 6737 { { "i6", "fp" }, "r30" }, 6738 { { "i7" }, "r31" }, 6739 }; 6740 6741 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6742 return llvm::makeArrayRef(GCCRegAliases); 6743 } 6744 6745 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6746 class SparcV8TargetInfo : public SparcTargetInfo { 6747 public: 6748 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6749 : SparcTargetInfo(Triple, Opts) { 6750 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6751 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6752 switch (getTriple().getOS()) { 6753 default: 6754 SizeType = UnsignedInt; 6755 IntPtrType = SignedInt; 6756 PtrDiffType = SignedInt; 6757 break; 6758 case llvm::Triple::NetBSD: 6759 case llvm::Triple::OpenBSD: 6760 SizeType = UnsignedLong; 6761 IntPtrType = SignedLong; 6762 PtrDiffType = SignedLong; 6763 break; 6764 } 6765 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6766 } 6767 6768 void getTargetDefines(const LangOptions &Opts, 6769 MacroBuilder &Builder) const override { 6770 SparcTargetInfo::getTargetDefines(Opts, Builder); 6771 switch (getCPUGeneration(CPU)) { 6772 case CG_V8: 6773 Builder.defineMacro("__sparcv8"); 6774 if (getTriple().getOS() != llvm::Triple::Solaris) 6775 Builder.defineMacro("__sparcv8__"); 6776 break; 6777 case CG_V9: 6778 Builder.defineMacro("__sparcv9"); 6779 if (getTriple().getOS() != llvm::Triple::Solaris) { 6780 Builder.defineMacro("__sparcv9__"); 6781 Builder.defineMacro("__sparc_v9__"); 6782 } 6783 break; 6784 } 6785 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6786 std::string MyriadArchValue, Myriad2Value; 6787 Builder.defineMacro("__sparc_v8__"); 6788 Builder.defineMacro("__leon__"); 6789 switch (CPU) { 6790 case CK_MYRIAD2150: 6791 MyriadArchValue = "__ma2150"; 6792 Myriad2Value = "2"; 6793 break; 6794 case CK_MYRIAD2450: 6795 MyriadArchValue = "__ma2450"; 6796 Myriad2Value = "2"; 6797 break; 6798 default: 6799 MyriadArchValue = "__ma2100"; 6800 Myriad2Value = "1"; 6801 break; 6802 } 6803 Builder.defineMacro(MyriadArchValue, "1"); 6804 Builder.defineMacro(MyriadArchValue+"__", "1"); 6805 Builder.defineMacro("__myriad2__", Myriad2Value); 6806 Builder.defineMacro("__myriad2", Myriad2Value); 6807 } 6808 } 6809 6810 bool hasSjLjLowering() const override { 6811 return true; 6812 } 6813 }; 6814 6815 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6816 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6817 public: 6818 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6819 : SparcV8TargetInfo(Triple, Opts) { 6820 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6821 } 6822 }; 6823 6824 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6825 class SparcV9TargetInfo : public SparcTargetInfo { 6826 public: 6827 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6828 : SparcTargetInfo(Triple, Opts) { 6829 // FIXME: Support Sparc quad-precision long double? 6830 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6831 // This is an LP64 platform. 6832 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6833 6834 // OpenBSD uses long long for int64_t and intmax_t. 6835 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6836 IntMaxType = SignedLongLong; 6837 else 6838 IntMaxType = SignedLong; 6839 Int64Type = IntMaxType; 6840 6841 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6842 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6843 LongDoubleWidth = 128; 6844 LongDoubleAlign = 128; 6845 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6846 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6847 } 6848 6849 void getTargetDefines(const LangOptions &Opts, 6850 MacroBuilder &Builder) const override { 6851 SparcTargetInfo::getTargetDefines(Opts, Builder); 6852 Builder.defineMacro("__sparcv9"); 6853 Builder.defineMacro("__arch64__"); 6854 // Solaris doesn't need these variants, but the BSDs do. 6855 if (getTriple().getOS() != llvm::Triple::Solaris) { 6856 Builder.defineMacro("__sparc64__"); 6857 Builder.defineMacro("__sparc_v9__"); 6858 Builder.defineMacro("__sparcv9__"); 6859 } 6860 } 6861 6862 bool setCPU(const std::string &Name) override { 6863 if (!SparcTargetInfo::setCPU(Name)) 6864 return false; 6865 return getCPUGeneration(CPU) == CG_V9; 6866 } 6867 }; 6868 6869 class SystemZTargetInfo : public TargetInfo { 6870 static const Builtin::Info BuiltinInfo[]; 6871 static const char *const GCCRegNames[]; 6872 std::string CPU; 6873 bool HasTransactionalExecution; 6874 bool HasVector; 6875 6876 public: 6877 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6878 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6879 HasVector(false) { 6880 IntMaxType = SignedLong; 6881 Int64Type = SignedLong; 6882 TLSSupported = true; 6883 IntWidth = IntAlign = 32; 6884 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6885 PointerWidth = PointerAlign = 64; 6886 LongDoubleWidth = 128; 6887 LongDoubleAlign = 64; 6888 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6889 DefaultAlignForAttributeAligned = 64; 6890 MinGlobalAlign = 16; 6891 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6892 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6893 } 6894 void getTargetDefines(const LangOptions &Opts, 6895 MacroBuilder &Builder) const override { 6896 Builder.defineMacro("__s390__"); 6897 Builder.defineMacro("__s390x__"); 6898 Builder.defineMacro("__zarch__"); 6899 Builder.defineMacro("__LONG_DOUBLE_128__"); 6900 6901 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6902 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6903 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6904 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6905 6906 if (HasTransactionalExecution) 6907 Builder.defineMacro("__HTM__"); 6908 if (Opts.ZVector) 6909 Builder.defineMacro("__VEC__", "10301"); 6910 } 6911 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6912 return llvm::makeArrayRef(BuiltinInfo, 6913 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6914 } 6915 6916 ArrayRef<const char *> getGCCRegNames() const override; 6917 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6918 // No aliases. 6919 return None; 6920 } 6921 bool validateAsmConstraint(const char *&Name, 6922 TargetInfo::ConstraintInfo &info) const override; 6923 const char *getClobbers() const override { 6924 // FIXME: Is this really right? 6925 return ""; 6926 } 6927 BuiltinVaListKind getBuiltinVaListKind() const override { 6928 return TargetInfo::SystemZBuiltinVaList; 6929 } 6930 bool setCPU(const std::string &Name) override { 6931 CPU = Name; 6932 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6933 .Case("z10", true) 6934 .Case("z196", true) 6935 .Case("zEC12", true) 6936 .Case("z13", true) 6937 .Default(false); 6938 6939 return CPUKnown; 6940 } 6941 bool 6942 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6943 StringRef CPU, 6944 const std::vector<std::string> &FeaturesVec) const override { 6945 if (CPU == "zEC12") 6946 Features["transactional-execution"] = true; 6947 if (CPU == "z13") { 6948 Features["transactional-execution"] = true; 6949 Features["vector"] = true; 6950 } 6951 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6952 } 6953 6954 bool handleTargetFeatures(std::vector<std::string> &Features, 6955 DiagnosticsEngine &Diags) override { 6956 HasTransactionalExecution = false; 6957 for (const auto &Feature : Features) { 6958 if (Feature == "+transactional-execution") 6959 HasTransactionalExecution = true; 6960 else if (Feature == "+vector") 6961 HasVector = true; 6962 } 6963 // If we use the vector ABI, vector types are 64-bit aligned. 6964 if (HasVector) { 6965 MaxVectorAlign = 64; 6966 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6967 "-v128:64-a:8:16-n32:64"); 6968 } 6969 return true; 6970 } 6971 6972 bool hasFeature(StringRef Feature) const override { 6973 return llvm::StringSwitch<bool>(Feature) 6974 .Case("systemz", true) 6975 .Case("htm", HasTransactionalExecution) 6976 .Case("vx", HasVector) 6977 .Default(false); 6978 } 6979 6980 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6981 switch (CC) { 6982 case CC_C: 6983 case CC_Swift: 6984 return CCCR_OK; 6985 default: 6986 return CCCR_Warning; 6987 } 6988 } 6989 6990 StringRef getABI() const override { 6991 if (HasVector) 6992 return "vector"; 6993 return ""; 6994 } 6995 6996 bool useFloat128ManglingForLongDouble() const override { 6997 return true; 6998 } 6999 }; 7000 7001 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7002 #define BUILTIN(ID, TYPE, ATTRS) \ 7003 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7004 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7005 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7006 #include "clang/Basic/BuiltinsSystemZ.def" 7007 }; 7008 7009 const char *const SystemZTargetInfo::GCCRegNames[] = { 7010 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7011 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7012 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7013 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7014 }; 7015 7016 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7017 return llvm::makeArrayRef(GCCRegNames); 7018 } 7019 7020 bool SystemZTargetInfo:: 7021 validateAsmConstraint(const char *&Name, 7022 TargetInfo::ConstraintInfo &Info) const { 7023 switch (*Name) { 7024 default: 7025 return false; 7026 7027 case 'a': // Address register 7028 case 'd': // Data register (equivalent to 'r') 7029 case 'f': // Floating-point register 7030 Info.setAllowsRegister(); 7031 return true; 7032 7033 case 'I': // Unsigned 8-bit constant 7034 case 'J': // Unsigned 12-bit constant 7035 case 'K': // Signed 16-bit constant 7036 case 'L': // Signed 20-bit displacement (on all targets we support) 7037 case 'M': // 0x7fffffff 7038 return true; 7039 7040 case 'Q': // Memory with base and unsigned 12-bit displacement 7041 case 'R': // Likewise, plus an index 7042 case 'S': // Memory with base and signed 20-bit displacement 7043 case 'T': // Likewise, plus an index 7044 Info.setAllowsMemory(); 7045 return true; 7046 } 7047 } 7048 7049 class MSP430TargetInfo : public TargetInfo { 7050 static const char *const GCCRegNames[]; 7051 7052 public: 7053 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7054 : TargetInfo(Triple) { 7055 TLSSupported = false; 7056 IntWidth = 16; 7057 IntAlign = 16; 7058 LongWidth = 32; 7059 LongLongWidth = 64; 7060 LongAlign = LongLongAlign = 16; 7061 PointerWidth = 16; 7062 PointerAlign = 16; 7063 SuitableAlign = 16; 7064 SizeType = UnsignedInt; 7065 IntMaxType = SignedLongLong; 7066 IntPtrType = SignedInt; 7067 PtrDiffType = SignedInt; 7068 SigAtomicType = SignedLong; 7069 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7070 } 7071 void getTargetDefines(const LangOptions &Opts, 7072 MacroBuilder &Builder) const override { 7073 Builder.defineMacro("MSP430"); 7074 Builder.defineMacro("__MSP430__"); 7075 // FIXME: defines for different 'flavours' of MCU 7076 } 7077 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7078 // FIXME: Implement. 7079 return None; 7080 } 7081 bool hasFeature(StringRef Feature) const override { 7082 return Feature == "msp430"; 7083 } 7084 ArrayRef<const char *> getGCCRegNames() const override; 7085 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7086 // No aliases. 7087 return None; 7088 } 7089 bool validateAsmConstraint(const char *&Name, 7090 TargetInfo::ConstraintInfo &info) const override { 7091 // FIXME: implement 7092 switch (*Name) { 7093 case 'K': // the constant 1 7094 case 'L': // constant -1^20 .. 1^19 7095 case 'M': // constant 1-4: 7096 return true; 7097 } 7098 // No target constraints for now. 7099 return false; 7100 } 7101 const char *getClobbers() const override { 7102 // FIXME: Is this really right? 7103 return ""; 7104 } 7105 BuiltinVaListKind getBuiltinVaListKind() const override { 7106 // FIXME: implement 7107 return TargetInfo::CharPtrBuiltinVaList; 7108 } 7109 }; 7110 7111 const char *const MSP430TargetInfo::GCCRegNames[] = { 7112 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7113 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7114 7115 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7116 return llvm::makeArrayRef(GCCRegNames); 7117 } 7118 7119 // LLVM and Clang cannot be used directly to output native binaries for 7120 // target, but is used to compile C code to llvm bitcode with correct 7121 // type and alignment information. 7122 // 7123 // TCE uses the llvm bitcode as input and uses it for generating customized 7124 // target processor and program binary. TCE co-design environment is 7125 // publicly available in http://tce.cs.tut.fi 7126 7127 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7128 3, // opencl_global 7129 4, // opencl_local 7130 5, // opencl_constant 7131 // FIXME: generic has to be added to the target 7132 0, // opencl_generic 7133 0, // cuda_device 7134 0, // cuda_constant 7135 0 // cuda_shared 7136 }; 7137 7138 class TCETargetInfo : public TargetInfo { 7139 public: 7140 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7141 : TargetInfo(Triple) { 7142 TLSSupported = false; 7143 IntWidth = 32; 7144 LongWidth = LongLongWidth = 32; 7145 PointerWidth = 32; 7146 IntAlign = 32; 7147 LongAlign = LongLongAlign = 32; 7148 PointerAlign = 32; 7149 SuitableAlign = 32; 7150 SizeType = UnsignedInt; 7151 IntMaxType = SignedLong; 7152 IntPtrType = SignedInt; 7153 PtrDiffType = SignedInt; 7154 FloatWidth = 32; 7155 FloatAlign = 32; 7156 DoubleWidth = 32; 7157 DoubleAlign = 32; 7158 LongDoubleWidth = 32; 7159 LongDoubleAlign = 32; 7160 FloatFormat = &llvm::APFloat::IEEEsingle; 7161 DoubleFormat = &llvm::APFloat::IEEEsingle; 7162 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 7163 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 7164 "-f64:32-v64:32-v128:32-a:0:32-n32"); 7165 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7166 UseAddrSpaceMapMangling = true; 7167 } 7168 7169 void getTargetDefines(const LangOptions &Opts, 7170 MacroBuilder &Builder) const override { 7171 DefineStd(Builder, "tce", Opts); 7172 Builder.defineMacro("__TCE__"); 7173 Builder.defineMacro("__TCE_V1__"); 7174 } 7175 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7176 7177 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7178 const char *getClobbers() const override { return ""; } 7179 BuiltinVaListKind getBuiltinVaListKind() const override { 7180 return TargetInfo::VoidPtrBuiltinVaList; 7181 } 7182 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7183 bool validateAsmConstraint(const char *&Name, 7184 TargetInfo::ConstraintInfo &info) const override { 7185 return true; 7186 } 7187 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7188 return None; 7189 } 7190 }; 7191 7192 class BPFTargetInfo : public TargetInfo { 7193 public: 7194 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7195 : TargetInfo(Triple) { 7196 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7197 SizeType = UnsignedLong; 7198 PtrDiffType = SignedLong; 7199 IntPtrType = SignedLong; 7200 IntMaxType = SignedLong; 7201 Int64Type = SignedLong; 7202 RegParmMax = 5; 7203 if (Triple.getArch() == llvm::Triple::bpfeb) { 7204 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7205 } else { 7206 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7207 } 7208 MaxAtomicPromoteWidth = 64; 7209 MaxAtomicInlineWidth = 64; 7210 TLSSupported = false; 7211 } 7212 void getTargetDefines(const LangOptions &Opts, 7213 MacroBuilder &Builder) const override { 7214 DefineStd(Builder, "bpf", Opts); 7215 Builder.defineMacro("__BPF__"); 7216 } 7217 bool hasFeature(StringRef Feature) const override { 7218 return Feature == "bpf"; 7219 } 7220 7221 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7222 const char *getClobbers() const override { 7223 return ""; 7224 } 7225 BuiltinVaListKind getBuiltinVaListKind() const override { 7226 return TargetInfo::VoidPtrBuiltinVaList; 7227 } 7228 ArrayRef<const char *> getGCCRegNames() const override { 7229 return None; 7230 } 7231 bool validateAsmConstraint(const char *&Name, 7232 TargetInfo::ConstraintInfo &info) const override { 7233 return true; 7234 } 7235 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7236 return None; 7237 } 7238 }; 7239 7240 class MipsTargetInfo : public TargetInfo { 7241 void setDataLayout() { 7242 StringRef Layout; 7243 7244 if (ABI == "o32") 7245 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7246 else if (ABI == "n32") 7247 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7248 else if (ABI == "n64") 7249 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7250 else 7251 llvm_unreachable("Invalid ABI"); 7252 7253 if (BigEndian) 7254 resetDataLayout(("E-" + Layout).str()); 7255 else 7256 resetDataLayout(("e-" + Layout).str()); 7257 } 7258 7259 7260 static const Builtin::Info BuiltinInfo[]; 7261 std::string CPU; 7262 bool IsMips16; 7263 bool IsMicromips; 7264 bool IsNan2008; 7265 bool IsSingleFloat; 7266 enum MipsFloatABI { 7267 HardFloat, SoftFloat 7268 } FloatABI; 7269 enum DspRevEnum { 7270 NoDSP, DSP1, DSP2 7271 } DspRev; 7272 bool HasMSA; 7273 7274 protected: 7275 bool HasFP64; 7276 std::string ABI; 7277 7278 public: 7279 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7280 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7281 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7282 DspRev(NoDSP), HasMSA(false), HasFP64(false) { 7283 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7284 7285 setABI((getTriple().getArch() == llvm::Triple::mips || 7286 getTriple().getArch() == llvm::Triple::mipsel) 7287 ? "o32" 7288 : "n64"); 7289 7290 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7291 } 7292 7293 bool isNaN2008Default() const { 7294 return CPU == "mips32r6" || CPU == "mips64r6"; 7295 } 7296 7297 bool isFP64Default() const { 7298 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7299 } 7300 7301 bool isNan2008() const override { 7302 return IsNan2008; 7303 } 7304 7305 bool processorSupportsGPR64() const { 7306 return llvm::StringSwitch<bool>(CPU) 7307 .Case("mips3", true) 7308 .Case("mips4", true) 7309 .Case("mips5", true) 7310 .Case("mips64", true) 7311 .Case("mips64r2", true) 7312 .Case("mips64r3", true) 7313 .Case("mips64r5", true) 7314 .Case("mips64r6", true) 7315 .Case("octeon", true) 7316 .Default(false); 7317 return false; 7318 } 7319 7320 StringRef getABI() const override { return ABI; } 7321 bool setABI(const std::string &Name) override { 7322 if (Name == "o32") { 7323 setO32ABITypes(); 7324 ABI = Name; 7325 return true; 7326 } 7327 7328 if (Name == "n32") { 7329 setN32ABITypes(); 7330 ABI = Name; 7331 return true; 7332 } 7333 if (Name == "n64") { 7334 setN64ABITypes(); 7335 ABI = Name; 7336 return true; 7337 } 7338 return false; 7339 } 7340 7341 void setO32ABITypes() { 7342 Int64Type = SignedLongLong; 7343 IntMaxType = Int64Type; 7344 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7345 LongDoubleWidth = LongDoubleAlign = 64; 7346 LongWidth = LongAlign = 32; 7347 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7348 PointerWidth = PointerAlign = 32; 7349 PtrDiffType = SignedInt; 7350 SizeType = UnsignedInt; 7351 SuitableAlign = 64; 7352 } 7353 7354 void setN32N64ABITypes() { 7355 LongDoubleWidth = LongDoubleAlign = 128; 7356 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7357 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7358 LongDoubleWidth = LongDoubleAlign = 64; 7359 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7360 } 7361 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7362 SuitableAlign = 128; 7363 } 7364 7365 void setN64ABITypes() { 7366 setN32N64ABITypes(); 7367 Int64Type = SignedLong; 7368 IntMaxType = Int64Type; 7369 LongWidth = LongAlign = 64; 7370 PointerWidth = PointerAlign = 64; 7371 PtrDiffType = SignedLong; 7372 SizeType = UnsignedLong; 7373 } 7374 7375 void setN32ABITypes() { 7376 setN32N64ABITypes(); 7377 Int64Type = SignedLongLong; 7378 IntMaxType = Int64Type; 7379 LongWidth = LongAlign = 32; 7380 PointerWidth = PointerAlign = 32; 7381 PtrDiffType = SignedInt; 7382 SizeType = UnsignedInt; 7383 } 7384 7385 bool setCPU(const std::string &Name) override { 7386 CPU = Name; 7387 return llvm::StringSwitch<bool>(Name) 7388 .Case("mips1", true) 7389 .Case("mips2", true) 7390 .Case("mips3", true) 7391 .Case("mips4", true) 7392 .Case("mips5", true) 7393 .Case("mips32", true) 7394 .Case("mips32r2", true) 7395 .Case("mips32r3", true) 7396 .Case("mips32r5", true) 7397 .Case("mips32r6", true) 7398 .Case("mips64", true) 7399 .Case("mips64r2", true) 7400 .Case("mips64r3", true) 7401 .Case("mips64r5", true) 7402 .Case("mips64r6", true) 7403 .Case("octeon", true) 7404 .Case("p5600", true) 7405 .Default(false); 7406 } 7407 const std::string& getCPU() const { return CPU; } 7408 bool 7409 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7410 StringRef CPU, 7411 const std::vector<std::string> &FeaturesVec) const override { 7412 if (CPU.empty()) 7413 CPU = getCPU(); 7414 if (CPU == "octeon") 7415 Features["mips64r2"] = Features["cnmips"] = true; 7416 else 7417 Features[CPU] = true; 7418 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7419 } 7420 7421 void getTargetDefines(const LangOptions &Opts, 7422 MacroBuilder &Builder) const override { 7423 if (BigEndian) { 7424 DefineStd(Builder, "MIPSEB", Opts); 7425 Builder.defineMacro("_MIPSEB"); 7426 } else { 7427 DefineStd(Builder, "MIPSEL", Opts); 7428 Builder.defineMacro("_MIPSEL"); 7429 } 7430 7431 Builder.defineMacro("__mips__"); 7432 Builder.defineMacro("_mips"); 7433 if (Opts.GNUMode) 7434 Builder.defineMacro("mips"); 7435 7436 if (ABI == "o32") { 7437 Builder.defineMacro("__mips", "32"); 7438 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7439 } else { 7440 Builder.defineMacro("__mips", "64"); 7441 Builder.defineMacro("__mips64"); 7442 Builder.defineMacro("__mips64__"); 7443 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7444 } 7445 7446 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7447 .Cases("mips32", "mips64", "1") 7448 .Cases("mips32r2", "mips64r2", "2") 7449 .Cases("mips32r3", "mips64r3", "3") 7450 .Cases("mips32r5", "mips64r5", "5") 7451 .Cases("mips32r6", "mips64r6", "6") 7452 .Default(""); 7453 if (!ISARev.empty()) 7454 Builder.defineMacro("__mips_isa_rev", ISARev); 7455 7456 if (ABI == "o32") { 7457 Builder.defineMacro("__mips_o32"); 7458 Builder.defineMacro("_ABIO32", "1"); 7459 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7460 } else if (ABI == "n32") { 7461 Builder.defineMacro("__mips_n32"); 7462 Builder.defineMacro("_ABIN32", "2"); 7463 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7464 } else if (ABI == "n64") { 7465 Builder.defineMacro("__mips_n64"); 7466 Builder.defineMacro("_ABI64", "3"); 7467 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7468 } else 7469 llvm_unreachable("Invalid ABI."); 7470 7471 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7472 7473 switch (FloatABI) { 7474 case HardFloat: 7475 Builder.defineMacro("__mips_hard_float", Twine(1)); 7476 break; 7477 case SoftFloat: 7478 Builder.defineMacro("__mips_soft_float", Twine(1)); 7479 break; 7480 } 7481 7482 if (IsSingleFloat) 7483 Builder.defineMacro("__mips_single_float", Twine(1)); 7484 7485 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7486 Builder.defineMacro("_MIPS_FPSET", 7487 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7488 7489 if (IsMips16) 7490 Builder.defineMacro("__mips16", Twine(1)); 7491 7492 if (IsMicromips) 7493 Builder.defineMacro("__mips_micromips", Twine(1)); 7494 7495 if (IsNan2008) 7496 Builder.defineMacro("__mips_nan2008", Twine(1)); 7497 7498 switch (DspRev) { 7499 default: 7500 break; 7501 case DSP1: 7502 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7503 Builder.defineMacro("__mips_dsp", Twine(1)); 7504 break; 7505 case DSP2: 7506 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7507 Builder.defineMacro("__mips_dspr2", Twine(1)); 7508 Builder.defineMacro("__mips_dsp", Twine(1)); 7509 break; 7510 } 7511 7512 if (HasMSA) 7513 Builder.defineMacro("__mips_msa", Twine(1)); 7514 7515 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7516 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7517 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7518 7519 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7520 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7521 7522 // These shouldn't be defined for MIPS-I but there's no need to check 7523 // for that since MIPS-I isn't supported. 7524 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7525 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7526 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7527 7528 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7529 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7530 // the instructions exist but using them violates the ABI since they 7531 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7532 if (ABI == "n32" || ABI == "n64") 7533 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7534 } 7535 7536 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7537 return llvm::makeArrayRef(BuiltinInfo, 7538 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7539 } 7540 bool hasFeature(StringRef Feature) const override { 7541 return llvm::StringSwitch<bool>(Feature) 7542 .Case("mips", true) 7543 .Case("fp64", HasFP64) 7544 .Default(false); 7545 } 7546 BuiltinVaListKind getBuiltinVaListKind() const override { 7547 return TargetInfo::VoidPtrBuiltinVaList; 7548 } 7549 ArrayRef<const char *> getGCCRegNames() const override { 7550 static const char *const GCCRegNames[] = { 7551 // CPU register names 7552 // Must match second column of GCCRegAliases 7553 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7554 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7555 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7556 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7557 // Floating point register names 7558 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7559 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7560 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7561 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7562 // Hi/lo and condition register names 7563 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7564 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7565 "$ac3hi","$ac3lo", 7566 // MSA register names 7567 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7568 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7569 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7570 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7571 // MSA control register names 7572 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7573 "$msarequest", "$msamap", "$msaunmap" 7574 }; 7575 return llvm::makeArrayRef(GCCRegNames); 7576 } 7577 bool validateAsmConstraint(const char *&Name, 7578 TargetInfo::ConstraintInfo &Info) const override { 7579 switch (*Name) { 7580 default: 7581 return false; 7582 case 'r': // CPU registers. 7583 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7584 case 'y': // Equivalent to "r", backward compatibility only. 7585 case 'f': // floating-point registers. 7586 case 'c': // $25 for indirect jumps 7587 case 'l': // lo register 7588 case 'x': // hilo register pair 7589 Info.setAllowsRegister(); 7590 return true; 7591 case 'I': // Signed 16-bit constant 7592 case 'J': // Integer 0 7593 case 'K': // Unsigned 16-bit constant 7594 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7595 case 'M': // Constants not loadable via lui, addiu, or ori 7596 case 'N': // Constant -1 to -65535 7597 case 'O': // A signed 15-bit constant 7598 case 'P': // A constant between 1 go 65535 7599 return true; 7600 case 'R': // An address that can be used in a non-macro load or store 7601 Info.setAllowsMemory(); 7602 return true; 7603 case 'Z': 7604 if (Name[1] == 'C') { // An address usable by ll, and sc. 7605 Info.setAllowsMemory(); 7606 Name++; // Skip over 'Z'. 7607 return true; 7608 } 7609 return false; 7610 } 7611 } 7612 7613 std::string convertConstraint(const char *&Constraint) const override { 7614 std::string R; 7615 switch (*Constraint) { 7616 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7617 if (Constraint[1] == 'C') { 7618 R = std::string("^") + std::string(Constraint, 2); 7619 Constraint++; 7620 return R; 7621 } 7622 break; 7623 } 7624 return TargetInfo::convertConstraint(Constraint); 7625 } 7626 7627 const char *getClobbers() const override { 7628 // In GCC, $1 is not widely used in generated code (it's used only in a few 7629 // specific situations), so there is no real need for users to add it to 7630 // the clobbers list if they want to use it in their inline assembly code. 7631 // 7632 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7633 // code generation, so using it in inline assembly without adding it to the 7634 // clobbers list can cause conflicts between the inline assembly code and 7635 // the surrounding generated code. 7636 // 7637 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7638 // operands, which will conflict with the ".set at" assembler option (which 7639 // we use only for inline assembly, in order to maintain compatibility with 7640 // GCC) and will also conflict with the user's usage of $1. 7641 // 7642 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7643 // register for generated code is to automatically clobber $1 for all inline 7644 // assembly code. 7645 // 7646 // FIXME: We should automatically clobber $1 only for inline assembly code 7647 // which actually uses it. This would allow LLVM to use $1 for inline 7648 // assembly operands if the user's assembly code doesn't use it. 7649 return "~{$1}"; 7650 } 7651 7652 bool handleTargetFeatures(std::vector<std::string> &Features, 7653 DiagnosticsEngine &Diags) override { 7654 IsMips16 = false; 7655 IsMicromips = false; 7656 IsNan2008 = isNaN2008Default(); 7657 IsSingleFloat = false; 7658 FloatABI = HardFloat; 7659 DspRev = NoDSP; 7660 HasFP64 = isFP64Default(); 7661 7662 for (const auto &Feature : Features) { 7663 if (Feature == "+single-float") 7664 IsSingleFloat = true; 7665 else if (Feature == "+soft-float") 7666 FloatABI = SoftFloat; 7667 else if (Feature == "+mips16") 7668 IsMips16 = true; 7669 else if (Feature == "+micromips") 7670 IsMicromips = true; 7671 else if (Feature == "+dsp") 7672 DspRev = std::max(DspRev, DSP1); 7673 else if (Feature == "+dspr2") 7674 DspRev = std::max(DspRev, DSP2); 7675 else if (Feature == "+msa") 7676 HasMSA = true; 7677 else if (Feature == "+fp64") 7678 HasFP64 = true; 7679 else if (Feature == "-fp64") 7680 HasFP64 = false; 7681 else if (Feature == "+nan2008") 7682 IsNan2008 = true; 7683 else if (Feature == "-nan2008") 7684 IsNan2008 = false; 7685 } 7686 7687 setDataLayout(); 7688 7689 return true; 7690 } 7691 7692 int getEHDataRegisterNumber(unsigned RegNo) const override { 7693 if (RegNo == 0) return 4; 7694 if (RegNo == 1) return 5; 7695 return -1; 7696 } 7697 7698 bool isCLZForZeroUndef() const override { return false; } 7699 7700 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7701 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7702 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7703 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7704 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7705 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7706 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7707 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7708 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7709 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7710 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7711 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7712 {{"ra"}, "$31"}}; 7713 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7714 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7715 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7716 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7717 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7718 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7719 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7720 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7721 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7722 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7723 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7724 {{"ra"}, "$31"}}; 7725 if (ABI == "o32") 7726 return llvm::makeArrayRef(O32RegAliases); 7727 return llvm::makeArrayRef(NewABIRegAliases); 7728 } 7729 7730 bool hasInt128Type() const override { 7731 return ABI == "n32" || ABI == "n64"; 7732 } 7733 7734 bool validateTarget(DiagnosticsEngine &Diags) const override { 7735 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7736 // this yet. It's better to fail here than on the backend assertion. 7737 if (processorSupportsGPR64() && ABI == "o32") { 7738 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7739 return false; 7740 } 7741 7742 // 64-bit ABI's require 64-bit CPU's. 7743 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 7744 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7745 return false; 7746 } 7747 7748 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 7749 // can't handle this yet. It's better to fail here than on the 7750 // backend assertion. 7751 if ((getTriple().getArch() == llvm::Triple::mips64 || 7752 getTriple().getArch() == llvm::Triple::mips64el) && 7753 ABI == "o32") { 7754 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7755 << ABI << getTriple().str(); 7756 return false; 7757 } 7758 7759 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 7760 // can't handle this yet. It's better to fail here than on the 7761 // backend assertion. 7762 if ((getTriple().getArch() == llvm::Triple::mips || 7763 getTriple().getArch() == llvm::Triple::mipsel) && 7764 (ABI == "n32" || ABI == "n64")) { 7765 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7766 << ABI << getTriple().str(); 7767 return false; 7768 } 7769 7770 return true; 7771 } 7772 }; 7773 7774 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7775 #define BUILTIN(ID, TYPE, ATTRS) \ 7776 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7777 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7778 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7779 #include "clang/Basic/BuiltinsMips.def" 7780 }; 7781 7782 class PNaClTargetInfo : public TargetInfo { 7783 public: 7784 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7785 : TargetInfo(Triple) { 7786 this->LongAlign = 32; 7787 this->LongWidth = 32; 7788 this->PointerAlign = 32; 7789 this->PointerWidth = 32; 7790 this->IntMaxType = TargetInfo::SignedLongLong; 7791 this->Int64Type = TargetInfo::SignedLongLong; 7792 this->DoubleAlign = 64; 7793 this->LongDoubleWidth = 64; 7794 this->LongDoubleAlign = 64; 7795 this->SizeType = TargetInfo::UnsignedInt; 7796 this->PtrDiffType = TargetInfo::SignedInt; 7797 this->IntPtrType = TargetInfo::SignedInt; 7798 this->RegParmMax = 0; // Disallow regparm 7799 } 7800 7801 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7802 Builder.defineMacro("__le32__"); 7803 Builder.defineMacro("__pnacl__"); 7804 } 7805 void getTargetDefines(const LangOptions &Opts, 7806 MacroBuilder &Builder) const override { 7807 getArchDefines(Opts, Builder); 7808 } 7809 bool hasFeature(StringRef Feature) const override { 7810 return Feature == "pnacl"; 7811 } 7812 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7813 BuiltinVaListKind getBuiltinVaListKind() const override { 7814 return TargetInfo::PNaClABIBuiltinVaList; 7815 } 7816 ArrayRef<const char *> getGCCRegNames() const override; 7817 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7818 bool validateAsmConstraint(const char *&Name, 7819 TargetInfo::ConstraintInfo &Info) const override { 7820 return false; 7821 } 7822 7823 const char *getClobbers() const override { 7824 return ""; 7825 } 7826 }; 7827 7828 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7829 return None; 7830 } 7831 7832 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7833 return None; 7834 } 7835 7836 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7837 class NaClMips32TargetInfo : public MipsTargetInfo { 7838 public: 7839 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7840 : MipsTargetInfo(Triple, Opts) {} 7841 7842 BuiltinVaListKind getBuiltinVaListKind() const override { 7843 return TargetInfo::PNaClABIBuiltinVaList; 7844 } 7845 }; 7846 7847 class Le64TargetInfo : public TargetInfo { 7848 static const Builtin::Info BuiltinInfo[]; 7849 7850 public: 7851 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7852 : TargetInfo(Triple) { 7853 NoAsmVariants = true; 7854 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7855 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7856 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7857 } 7858 7859 void getTargetDefines(const LangOptions &Opts, 7860 MacroBuilder &Builder) const override { 7861 DefineStd(Builder, "unix", Opts); 7862 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7863 Builder.defineMacro("__ELF__"); 7864 } 7865 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7866 return llvm::makeArrayRef(BuiltinInfo, 7867 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7868 } 7869 BuiltinVaListKind getBuiltinVaListKind() const override { 7870 return TargetInfo::PNaClABIBuiltinVaList; 7871 } 7872 const char *getClobbers() const override { return ""; } 7873 ArrayRef<const char *> getGCCRegNames() const override { 7874 return None; 7875 } 7876 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7877 return None; 7878 } 7879 bool validateAsmConstraint(const char *&Name, 7880 TargetInfo::ConstraintInfo &Info) const override { 7881 return false; 7882 } 7883 7884 bool hasProtectedVisibility() const override { return false; } 7885 }; 7886 7887 class WebAssemblyTargetInfo : public TargetInfo { 7888 static const Builtin::Info BuiltinInfo[]; 7889 7890 enum SIMDEnum { 7891 NoSIMD, 7892 SIMD128, 7893 } SIMDLevel; 7894 7895 public: 7896 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7897 : TargetInfo(T), SIMDLevel(NoSIMD) { 7898 NoAsmVariants = true; 7899 SuitableAlign = 128; 7900 LargeArrayMinWidth = 128; 7901 LargeArrayAlign = 128; 7902 SimdDefaultAlign = 128; 7903 SigAtomicType = SignedLong; 7904 LongDoubleWidth = LongDoubleAlign = 128; 7905 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7906 SizeType = UnsignedInt; 7907 PtrDiffType = SignedInt; 7908 IntPtrType = SignedInt; 7909 } 7910 7911 protected: 7912 void getTargetDefines(const LangOptions &Opts, 7913 MacroBuilder &Builder) const override { 7914 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7915 if (SIMDLevel >= SIMD128) 7916 Builder.defineMacro("__wasm_simd128__"); 7917 } 7918 7919 private: 7920 bool 7921 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7922 StringRef CPU, 7923 const std::vector<std::string> &FeaturesVec) const override { 7924 if (CPU == "bleeding-edge") 7925 Features["simd128"] = true; 7926 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7927 } 7928 bool hasFeature(StringRef Feature) const final { 7929 return llvm::StringSwitch<bool>(Feature) 7930 .Case("simd128", SIMDLevel >= SIMD128) 7931 .Default(false); 7932 } 7933 bool handleTargetFeatures(std::vector<std::string> &Features, 7934 DiagnosticsEngine &Diags) final { 7935 for (const auto &Feature : Features) { 7936 if (Feature == "+simd128") { 7937 SIMDLevel = std::max(SIMDLevel, SIMD128); 7938 continue; 7939 } 7940 if (Feature == "-simd128") { 7941 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7942 continue; 7943 } 7944 7945 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7946 << "-target-feature"; 7947 return false; 7948 } 7949 return true; 7950 } 7951 bool setCPU(const std::string &Name) final { 7952 return llvm::StringSwitch<bool>(Name) 7953 .Case("mvp", true) 7954 .Case("bleeding-edge", true) 7955 .Case("generic", true) 7956 .Default(false); 7957 } 7958 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7959 return llvm::makeArrayRef(BuiltinInfo, 7960 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7961 } 7962 BuiltinVaListKind getBuiltinVaListKind() const final { 7963 return VoidPtrBuiltinVaList; 7964 } 7965 ArrayRef<const char *> getGCCRegNames() const final { 7966 return None; 7967 } 7968 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7969 return None; 7970 } 7971 bool 7972 validateAsmConstraint(const char *&Name, 7973 TargetInfo::ConstraintInfo &Info) const final { 7974 return false; 7975 } 7976 const char *getClobbers() const final { return ""; } 7977 bool isCLZForZeroUndef() const final { return false; } 7978 bool hasInt128Type() const final { return true; } 7979 IntType getIntTypeByWidth(unsigned BitWidth, 7980 bool IsSigned) const final { 7981 // WebAssembly prefers long long for explicitly 64-bit integers. 7982 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7983 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7984 } 7985 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7986 bool IsSigned) const final { 7987 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7988 return BitWidth == 64 7989 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7990 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7991 } 7992 }; 7993 7994 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7995 #define BUILTIN(ID, TYPE, ATTRS) \ 7996 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7997 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7998 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7999 #include "clang/Basic/BuiltinsWebAssembly.def" 8000 }; 8001 8002 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8003 public: 8004 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8005 const TargetOptions &Opts) 8006 : WebAssemblyTargetInfo(T, Opts) { 8007 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8008 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8009 } 8010 8011 protected: 8012 void getTargetDefines(const LangOptions &Opts, 8013 MacroBuilder &Builder) const override { 8014 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8015 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8016 } 8017 }; 8018 8019 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8020 public: 8021 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8022 const TargetOptions &Opts) 8023 : WebAssemblyTargetInfo(T, Opts) { 8024 LongAlign = LongWidth = 64; 8025 PointerAlign = PointerWidth = 64; 8026 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8027 SizeType = UnsignedLong; 8028 PtrDiffType = SignedLong; 8029 IntPtrType = SignedLong; 8030 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8031 } 8032 8033 protected: 8034 void getTargetDefines(const LangOptions &Opts, 8035 MacroBuilder &Builder) const override { 8036 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8037 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8038 } 8039 }; 8040 8041 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8042 #define BUILTIN(ID, TYPE, ATTRS) \ 8043 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8044 #include "clang/Basic/BuiltinsLe64.def" 8045 }; 8046 8047 static const unsigned SPIRAddrSpaceMap[] = { 8048 1, // opencl_global 8049 3, // opencl_local 8050 2, // opencl_constant 8051 4, // opencl_generic 8052 0, // cuda_device 8053 0, // cuda_constant 8054 0 // cuda_shared 8055 }; 8056 class SPIRTargetInfo : public TargetInfo { 8057 public: 8058 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8059 : TargetInfo(Triple) { 8060 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8061 "SPIR target must use unknown OS"); 8062 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8063 "SPIR target must use unknown environment type"); 8064 TLSSupported = false; 8065 LongWidth = LongAlign = 64; 8066 AddrSpaceMap = &SPIRAddrSpaceMap; 8067 UseAddrSpaceMapMangling = true; 8068 // Define available target features 8069 // These must be defined in sorted order! 8070 NoAsmVariants = true; 8071 } 8072 void getTargetDefines(const LangOptions &Opts, 8073 MacroBuilder &Builder) const override { 8074 DefineStd(Builder, "SPIR", Opts); 8075 } 8076 bool hasFeature(StringRef Feature) const override { 8077 return Feature == "spir"; 8078 } 8079 8080 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8081 const char *getClobbers() const override { return ""; } 8082 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8083 bool validateAsmConstraint(const char *&Name, 8084 TargetInfo::ConstraintInfo &info) const override { 8085 return true; 8086 } 8087 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8088 return None; 8089 } 8090 BuiltinVaListKind getBuiltinVaListKind() const override { 8091 return TargetInfo::VoidPtrBuiltinVaList; 8092 } 8093 8094 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8095 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8096 : CCCR_Warning; 8097 } 8098 8099 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8100 return CC_SpirFunction; 8101 } 8102 8103 void setSupportedOpenCLOpts() override { 8104 // Assume all OpenCL extensions and optional core features are supported 8105 // for SPIR since it is a generic target. 8106 getSupportedOpenCLOpts().setAll(); 8107 } 8108 }; 8109 8110 class SPIR32TargetInfo : public SPIRTargetInfo { 8111 public: 8112 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8113 : SPIRTargetInfo(Triple, Opts) { 8114 PointerWidth = PointerAlign = 32; 8115 SizeType = TargetInfo::UnsignedInt; 8116 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8117 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8118 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8119 } 8120 void getTargetDefines(const LangOptions &Opts, 8121 MacroBuilder &Builder) const override { 8122 DefineStd(Builder, "SPIR32", Opts); 8123 } 8124 }; 8125 8126 class SPIR64TargetInfo : public SPIRTargetInfo { 8127 public: 8128 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8129 : SPIRTargetInfo(Triple, Opts) { 8130 PointerWidth = PointerAlign = 64; 8131 SizeType = TargetInfo::UnsignedLong; 8132 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8133 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8134 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8135 } 8136 void getTargetDefines(const LangOptions &Opts, 8137 MacroBuilder &Builder) const override { 8138 DefineStd(Builder, "SPIR64", Opts); 8139 } 8140 }; 8141 8142 class XCoreTargetInfo : public TargetInfo { 8143 static const Builtin::Info BuiltinInfo[]; 8144 public: 8145 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8146 : TargetInfo(Triple) { 8147 NoAsmVariants = true; 8148 LongLongAlign = 32; 8149 SuitableAlign = 32; 8150 DoubleAlign = LongDoubleAlign = 32; 8151 SizeType = UnsignedInt; 8152 PtrDiffType = SignedInt; 8153 IntPtrType = SignedInt; 8154 WCharType = UnsignedChar; 8155 WIntType = UnsignedInt; 8156 UseZeroLengthBitfieldAlignment = true; 8157 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8158 "-f64:32-a:0:32-n32"); 8159 } 8160 void getTargetDefines(const LangOptions &Opts, 8161 MacroBuilder &Builder) const override { 8162 Builder.defineMacro("__XS1B__"); 8163 } 8164 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8165 return llvm::makeArrayRef(BuiltinInfo, 8166 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8167 } 8168 BuiltinVaListKind getBuiltinVaListKind() const override { 8169 return TargetInfo::VoidPtrBuiltinVaList; 8170 } 8171 const char *getClobbers() const override { 8172 return ""; 8173 } 8174 ArrayRef<const char *> getGCCRegNames() const override { 8175 static const char * const GCCRegNames[] = { 8176 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8177 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8178 }; 8179 return llvm::makeArrayRef(GCCRegNames); 8180 } 8181 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8182 return None; 8183 } 8184 bool validateAsmConstraint(const char *&Name, 8185 TargetInfo::ConstraintInfo &Info) const override { 8186 return false; 8187 } 8188 int getEHDataRegisterNumber(unsigned RegNo) const override { 8189 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8190 return (RegNo < 2)? RegNo : -1; 8191 } 8192 bool allowsLargerPreferedTypeAlignment() const override { 8193 return false; 8194 } 8195 }; 8196 8197 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8198 #define BUILTIN(ID, TYPE, ATTRS) \ 8199 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8200 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8201 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8202 #include "clang/Basic/BuiltinsXCore.def" 8203 }; 8204 8205 // x86_32 Android target 8206 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8207 public: 8208 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8209 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8210 SuitableAlign = 32; 8211 LongDoubleWidth = 64; 8212 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 8213 } 8214 }; 8215 8216 // x86_64 Android target 8217 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8218 public: 8219 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8220 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8221 LongDoubleFormat = &llvm::APFloat::IEEEquad; 8222 } 8223 8224 bool useFloat128ManglingForLongDouble() const override { 8225 return true; 8226 } 8227 }; 8228 8229 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8230 class RenderScript32TargetInfo : public ARMleTargetInfo { 8231 public: 8232 RenderScript32TargetInfo(const llvm::Triple &Triple, 8233 const TargetOptions &Opts) 8234 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8235 Triple.getOSName(), 8236 Triple.getEnvironmentName()), 8237 Opts) { 8238 IsRenderScriptTarget = true; 8239 LongWidth = LongAlign = 64; 8240 } 8241 void getTargetDefines(const LangOptions &Opts, 8242 MacroBuilder &Builder) const override { 8243 Builder.defineMacro("__RENDERSCRIPT__"); 8244 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8245 } 8246 }; 8247 8248 // 64-bit RenderScript is aarch64 8249 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8250 public: 8251 RenderScript64TargetInfo(const llvm::Triple &Triple, 8252 const TargetOptions &Opts) 8253 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8254 Triple.getOSName(), 8255 Triple.getEnvironmentName()), 8256 Opts) { 8257 IsRenderScriptTarget = true; 8258 } 8259 8260 void getTargetDefines(const LangOptions &Opts, 8261 MacroBuilder &Builder) const override { 8262 Builder.defineMacro("__RENDERSCRIPT__"); 8263 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8264 } 8265 }; 8266 8267 } // end anonymous namespace 8268 8269 //===----------------------------------------------------------------------===// 8270 // Driver code 8271 //===----------------------------------------------------------------------===// 8272 8273 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8274 const TargetOptions &Opts) { 8275 llvm::Triple::OSType os = Triple.getOS(); 8276 8277 switch (Triple.getArch()) { 8278 default: 8279 return nullptr; 8280 8281 case llvm::Triple::xcore: 8282 return new XCoreTargetInfo(Triple, Opts); 8283 8284 case llvm::Triple::hexagon: 8285 return new HexagonTargetInfo(Triple, Opts); 8286 8287 case llvm::Triple::lanai: 8288 return new LanaiTargetInfo(Triple, Opts); 8289 8290 case llvm::Triple::aarch64: 8291 if (Triple.isOSDarwin()) 8292 return new DarwinAArch64TargetInfo(Triple, Opts); 8293 8294 switch (os) { 8295 case llvm::Triple::CloudABI: 8296 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8297 case llvm::Triple::FreeBSD: 8298 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8299 case llvm::Triple::Linux: 8300 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8301 case llvm::Triple::NetBSD: 8302 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8303 case llvm::Triple::Fuchsia: 8304 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8305 default: 8306 return new AArch64leTargetInfo(Triple, Opts); 8307 } 8308 8309 case llvm::Triple::aarch64_be: 8310 switch (os) { 8311 case llvm::Triple::FreeBSD: 8312 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8313 case llvm::Triple::Linux: 8314 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8315 case llvm::Triple::NetBSD: 8316 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8317 default: 8318 return new AArch64beTargetInfo(Triple, Opts); 8319 } 8320 8321 case llvm::Triple::arm: 8322 case llvm::Triple::thumb: 8323 if (Triple.isOSBinFormatMachO()) 8324 return new DarwinARMTargetInfo(Triple, Opts); 8325 8326 switch (os) { 8327 case llvm::Triple::CloudABI: 8328 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 8329 case llvm::Triple::Linux: 8330 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8331 case llvm::Triple::FreeBSD: 8332 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8333 case llvm::Triple::NetBSD: 8334 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8335 case llvm::Triple::OpenBSD: 8336 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8337 case llvm::Triple::Bitrig: 8338 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8339 case llvm::Triple::RTEMS: 8340 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8341 case llvm::Triple::NaCl: 8342 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8343 case llvm::Triple::Win32: 8344 switch (Triple.getEnvironment()) { 8345 case llvm::Triple::Cygnus: 8346 return new CygwinARMTargetInfo(Triple, Opts); 8347 case llvm::Triple::GNU: 8348 return new MinGWARMTargetInfo(Triple, Opts); 8349 case llvm::Triple::Itanium: 8350 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8351 case llvm::Triple::MSVC: 8352 default: // Assume MSVC for unknown environments 8353 return new MicrosoftARMleTargetInfo(Triple, Opts); 8354 } 8355 default: 8356 return new ARMleTargetInfo(Triple, Opts); 8357 } 8358 8359 case llvm::Triple::armeb: 8360 case llvm::Triple::thumbeb: 8361 if (Triple.isOSDarwin()) 8362 return new DarwinARMTargetInfo(Triple, Opts); 8363 8364 switch (os) { 8365 case llvm::Triple::Linux: 8366 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8367 case llvm::Triple::FreeBSD: 8368 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8369 case llvm::Triple::NetBSD: 8370 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8371 case llvm::Triple::OpenBSD: 8372 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8373 case llvm::Triple::Bitrig: 8374 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8375 case llvm::Triple::RTEMS: 8376 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8377 case llvm::Triple::NaCl: 8378 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8379 default: 8380 return new ARMbeTargetInfo(Triple, Opts); 8381 } 8382 8383 case llvm::Triple::bpfeb: 8384 case llvm::Triple::bpfel: 8385 return new BPFTargetInfo(Triple, Opts); 8386 8387 case llvm::Triple::msp430: 8388 return new MSP430TargetInfo(Triple, Opts); 8389 8390 case llvm::Triple::mips: 8391 switch (os) { 8392 case llvm::Triple::Linux: 8393 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8394 case llvm::Triple::RTEMS: 8395 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8396 case llvm::Triple::FreeBSD: 8397 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8398 case llvm::Triple::NetBSD: 8399 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8400 default: 8401 return new MipsTargetInfo(Triple, Opts); 8402 } 8403 8404 case llvm::Triple::mipsel: 8405 switch (os) { 8406 case llvm::Triple::Linux: 8407 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8408 case llvm::Triple::RTEMS: 8409 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8410 case llvm::Triple::FreeBSD: 8411 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8412 case llvm::Triple::NetBSD: 8413 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8414 case llvm::Triple::NaCl: 8415 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 8416 default: 8417 return new MipsTargetInfo(Triple, Opts); 8418 } 8419 8420 case llvm::Triple::mips64: 8421 switch (os) { 8422 case llvm::Triple::Linux: 8423 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8424 case llvm::Triple::RTEMS: 8425 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8426 case llvm::Triple::FreeBSD: 8427 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8428 case llvm::Triple::NetBSD: 8429 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8430 case llvm::Triple::OpenBSD: 8431 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8432 default: 8433 return new MipsTargetInfo(Triple, Opts); 8434 } 8435 8436 case llvm::Triple::mips64el: 8437 switch (os) { 8438 case llvm::Triple::Linux: 8439 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8440 case llvm::Triple::RTEMS: 8441 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8442 case llvm::Triple::FreeBSD: 8443 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8444 case llvm::Triple::NetBSD: 8445 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8446 case llvm::Triple::OpenBSD: 8447 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8448 default: 8449 return new MipsTargetInfo(Triple, Opts); 8450 } 8451 8452 case llvm::Triple::le32: 8453 switch (os) { 8454 case llvm::Triple::NaCl: 8455 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8456 default: 8457 return nullptr; 8458 } 8459 8460 case llvm::Triple::le64: 8461 return new Le64TargetInfo(Triple, Opts); 8462 8463 case llvm::Triple::ppc: 8464 if (Triple.isOSDarwin()) 8465 return new DarwinPPC32TargetInfo(Triple, Opts); 8466 switch (os) { 8467 case llvm::Triple::Linux: 8468 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8469 case llvm::Triple::FreeBSD: 8470 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8471 case llvm::Triple::NetBSD: 8472 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8473 case llvm::Triple::OpenBSD: 8474 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8475 case llvm::Triple::RTEMS: 8476 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8477 default: 8478 return new PPC32TargetInfo(Triple, Opts); 8479 } 8480 8481 case llvm::Triple::ppc64: 8482 if (Triple.isOSDarwin()) 8483 return new DarwinPPC64TargetInfo(Triple, Opts); 8484 switch (os) { 8485 case llvm::Triple::Linux: 8486 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8487 case llvm::Triple::Lv2: 8488 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8489 case llvm::Triple::FreeBSD: 8490 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8491 case llvm::Triple::NetBSD: 8492 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8493 default: 8494 return new PPC64TargetInfo(Triple, Opts); 8495 } 8496 8497 case llvm::Triple::ppc64le: 8498 switch (os) { 8499 case llvm::Triple::Linux: 8500 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8501 case llvm::Triple::NetBSD: 8502 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8503 default: 8504 return new PPC64TargetInfo(Triple, Opts); 8505 } 8506 8507 case llvm::Triple::nvptx: 8508 return new NVPTX32TargetInfo(Triple, Opts); 8509 case llvm::Triple::nvptx64: 8510 return new NVPTX64TargetInfo(Triple, Opts); 8511 8512 case llvm::Triple::amdgcn: 8513 case llvm::Triple::r600: 8514 return new AMDGPUTargetInfo(Triple, Opts); 8515 8516 case llvm::Triple::sparc: 8517 switch (os) { 8518 case llvm::Triple::Linux: 8519 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8520 case llvm::Triple::Solaris: 8521 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8522 case llvm::Triple::NetBSD: 8523 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8524 case llvm::Triple::OpenBSD: 8525 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8526 case llvm::Triple::RTEMS: 8527 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8528 default: 8529 return new SparcV8TargetInfo(Triple, Opts); 8530 } 8531 8532 // The 'sparcel' architecture copies all the above cases except for Solaris. 8533 case llvm::Triple::sparcel: 8534 switch (os) { 8535 case llvm::Triple::Linux: 8536 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8537 case llvm::Triple::NetBSD: 8538 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8539 case llvm::Triple::OpenBSD: 8540 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8541 case llvm::Triple::RTEMS: 8542 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8543 default: 8544 return new SparcV8elTargetInfo(Triple, Opts); 8545 } 8546 8547 case llvm::Triple::sparcv9: 8548 switch (os) { 8549 case llvm::Triple::Linux: 8550 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8551 case llvm::Triple::Solaris: 8552 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8553 case llvm::Triple::NetBSD: 8554 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8555 case llvm::Triple::OpenBSD: 8556 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8557 case llvm::Triple::FreeBSD: 8558 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8559 default: 8560 return new SparcV9TargetInfo(Triple, Opts); 8561 } 8562 8563 case llvm::Triple::systemz: 8564 switch (os) { 8565 case llvm::Triple::Linux: 8566 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8567 default: 8568 return new SystemZTargetInfo(Triple, Opts); 8569 } 8570 8571 case llvm::Triple::tce: 8572 return new TCETargetInfo(Triple, Opts); 8573 8574 case llvm::Triple::x86: 8575 if (Triple.isOSDarwin()) 8576 return new DarwinI386TargetInfo(Triple, Opts); 8577 8578 switch (os) { 8579 case llvm::Triple::CloudABI: 8580 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8581 case llvm::Triple::Linux: { 8582 switch (Triple.getEnvironment()) { 8583 default: 8584 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8585 case llvm::Triple::Android: 8586 return new AndroidX86_32TargetInfo(Triple, Opts); 8587 } 8588 } 8589 case llvm::Triple::DragonFly: 8590 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8591 case llvm::Triple::NetBSD: 8592 return new NetBSDI386TargetInfo(Triple, Opts); 8593 case llvm::Triple::OpenBSD: 8594 return new OpenBSDI386TargetInfo(Triple, Opts); 8595 case llvm::Triple::Bitrig: 8596 return new BitrigI386TargetInfo(Triple, Opts); 8597 case llvm::Triple::FreeBSD: 8598 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8599 case llvm::Triple::KFreeBSD: 8600 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8601 case llvm::Triple::Minix: 8602 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8603 case llvm::Triple::Solaris: 8604 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8605 case llvm::Triple::Win32: { 8606 switch (Triple.getEnvironment()) { 8607 case llvm::Triple::Cygnus: 8608 return new CygwinX86_32TargetInfo(Triple, Opts); 8609 case llvm::Triple::GNU: 8610 return new MinGWX86_32TargetInfo(Triple, Opts); 8611 case llvm::Triple::Itanium: 8612 case llvm::Triple::MSVC: 8613 default: // Assume MSVC for unknown environments 8614 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8615 } 8616 } 8617 case llvm::Triple::Haiku: 8618 return new HaikuX86_32TargetInfo(Triple, Opts); 8619 case llvm::Triple::RTEMS: 8620 return new RTEMSX86_32TargetInfo(Triple, Opts); 8621 case llvm::Triple::NaCl: 8622 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8623 case llvm::Triple::ELFIAMCU: 8624 return new MCUX86_32TargetInfo(Triple, Opts); 8625 default: 8626 return new X86_32TargetInfo(Triple, Opts); 8627 } 8628 8629 case llvm::Triple::x86_64: 8630 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8631 return new DarwinX86_64TargetInfo(Triple, Opts); 8632 8633 switch (os) { 8634 case llvm::Triple::CloudABI: 8635 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8636 case llvm::Triple::Linux: { 8637 switch (Triple.getEnvironment()) { 8638 default: 8639 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8640 case llvm::Triple::Android: 8641 return new AndroidX86_64TargetInfo(Triple, Opts); 8642 } 8643 } 8644 case llvm::Triple::DragonFly: 8645 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8646 case llvm::Triple::NetBSD: 8647 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8648 case llvm::Triple::OpenBSD: 8649 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8650 case llvm::Triple::Bitrig: 8651 return new BitrigX86_64TargetInfo(Triple, Opts); 8652 case llvm::Triple::FreeBSD: 8653 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8654 case llvm::Triple::KFreeBSD: 8655 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8656 case llvm::Triple::Solaris: 8657 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8658 case llvm::Triple::Win32: { 8659 switch (Triple.getEnvironment()) { 8660 case llvm::Triple::Cygnus: 8661 return new CygwinX86_64TargetInfo(Triple, Opts); 8662 case llvm::Triple::GNU: 8663 return new MinGWX86_64TargetInfo(Triple, Opts); 8664 case llvm::Triple::MSVC: 8665 default: // Assume MSVC for unknown environments 8666 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8667 } 8668 } 8669 case llvm::Triple::Haiku: 8670 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8671 case llvm::Triple::NaCl: 8672 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8673 case llvm::Triple::Fuchsia: 8674 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 8675 case llvm::Triple::PS4: 8676 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8677 default: 8678 return new X86_64TargetInfo(Triple, Opts); 8679 } 8680 8681 case llvm::Triple::spir: { 8682 if (Triple.getOS() != llvm::Triple::UnknownOS || 8683 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8684 return nullptr; 8685 return new SPIR32TargetInfo(Triple, Opts); 8686 } 8687 case llvm::Triple::spir64: { 8688 if (Triple.getOS() != llvm::Triple::UnknownOS || 8689 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8690 return nullptr; 8691 return new SPIR64TargetInfo(Triple, Opts); 8692 } 8693 case llvm::Triple::wasm32: 8694 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8695 return nullptr; 8696 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8697 case llvm::Triple::wasm64: 8698 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8699 return nullptr; 8700 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8701 8702 case llvm::Triple::renderscript32: 8703 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 8704 case llvm::Triple::renderscript64: 8705 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 8706 } 8707 } 8708 8709 /// CreateTargetInfo - Return the target info object for the specified target 8710 /// options. 8711 TargetInfo * 8712 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8713 const std::shared_ptr<TargetOptions> &Opts) { 8714 llvm::Triple Triple(Opts->Triple); 8715 8716 // Construct the target 8717 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8718 if (!Target) { 8719 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8720 return nullptr; 8721 } 8722 Target->TargetOpts = Opts; 8723 8724 // Set the target CPU if specified. 8725 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8726 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8727 return nullptr; 8728 } 8729 8730 // Set the target ABI if specified. 8731 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8732 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8733 return nullptr; 8734 } 8735 8736 // Set the fp math unit. 8737 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8738 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8739 return nullptr; 8740 } 8741 8742 // Compute the default target features, we need the target to handle this 8743 // because features may have dependencies on one another. 8744 llvm::StringMap<bool> Features; 8745 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8746 Opts->FeaturesAsWritten)) 8747 return nullptr; 8748 8749 // Add the features to the compile options. 8750 Opts->Features.clear(); 8751 for (const auto &F : Features) 8752 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8753 8754 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8755 return nullptr; 8756 8757 Target->setSupportedOpenCLOpts(); 8758 8759 if (!Target->validateTarget(Diags)) 8760 return nullptr; 8761 8762 return Target.release(); 8763 } 8764