1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 if (Maj) 469 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 470 } 471 if (Opts.POSIXThreads) 472 Builder.defineMacro("_REENTRANT"); 473 if (Opts.CPlusPlus) 474 Builder.defineMacro("_GNU_SOURCE"); 475 if (this->HasFloat128) 476 Builder.defineMacro("__FLOAT128__"); 477 } 478 public: 479 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 480 : OSTargetInfo<Target>(Triple, Opts) { 481 this->WIntType = TargetInfo::UnsignedInt; 482 483 switch (Triple.getArch()) { 484 default: 485 break; 486 case llvm::Triple::ppc: 487 case llvm::Triple::ppc64: 488 case llvm::Triple::ppc64le: 489 this->MCountName = "_mcount"; 490 break; 491 case llvm::Triple::x86: 492 case llvm::Triple::x86_64: 493 case llvm::Triple::systemz: 494 this->HasFloat128 = true; 495 break; 496 } 497 } 498 499 const char *getStaticInitSectionSpecifier() const override { 500 return ".text.startup"; 501 } 502 }; 503 504 // NetBSD Target 505 template<typename Target> 506 class NetBSDTargetInfo : public OSTargetInfo<Target> { 507 protected: 508 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 509 MacroBuilder &Builder) const override { 510 // NetBSD defines; list based off of gcc output 511 Builder.defineMacro("__NetBSD__"); 512 Builder.defineMacro("__unix__"); 513 Builder.defineMacro("__ELF__"); 514 if (Opts.POSIXThreads) 515 Builder.defineMacro("_REENTRANT"); 516 517 switch (Triple.getArch()) { 518 default: 519 break; 520 case llvm::Triple::arm: 521 case llvm::Triple::armeb: 522 case llvm::Triple::thumb: 523 case llvm::Triple::thumbeb: 524 Builder.defineMacro("__ARM_DWARF_EH__"); 525 break; 526 } 527 } 528 public: 529 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 530 : OSTargetInfo<Target>(Triple, Opts) { 531 this->MCountName = "_mcount"; 532 } 533 }; 534 535 // OpenBSD Target 536 template<typename Target> 537 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 538 protected: 539 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 540 MacroBuilder &Builder) const override { 541 // OpenBSD defines; list based off of gcc output 542 543 Builder.defineMacro("__OpenBSD__"); 544 DefineStd(Builder, "unix", Opts); 545 Builder.defineMacro("__ELF__"); 546 if (Opts.POSIXThreads) 547 Builder.defineMacro("_REENTRANT"); 548 if (this->HasFloat128) 549 Builder.defineMacro("__FLOAT128__"); 550 } 551 public: 552 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 553 : OSTargetInfo<Target>(Triple, Opts) { 554 this->TLSSupported = false; 555 556 switch (Triple.getArch()) { 557 case llvm::Triple::x86: 558 case llvm::Triple::x86_64: 559 this->HasFloat128 = true; 560 // FALLTHROUGH 561 default: 562 this->MCountName = "__mcount"; 563 break; 564 case llvm::Triple::mips64: 565 case llvm::Triple::mips64el: 566 case llvm::Triple::ppc: 567 case llvm::Triple::sparcv9: 568 this->MCountName = "_mcount"; 569 break; 570 } 571 } 572 }; 573 574 // Bitrig Target 575 template<typename Target> 576 class BitrigTargetInfo : public OSTargetInfo<Target> { 577 protected: 578 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 579 MacroBuilder &Builder) const override { 580 // Bitrig defines; list based off of gcc output 581 582 Builder.defineMacro("__Bitrig__"); 583 DefineStd(Builder, "unix", Opts); 584 Builder.defineMacro("__ELF__"); 585 if (Opts.POSIXThreads) 586 Builder.defineMacro("_REENTRANT"); 587 588 switch (Triple.getArch()) { 589 default: 590 break; 591 case llvm::Triple::arm: 592 case llvm::Triple::armeb: 593 case llvm::Triple::thumb: 594 case llvm::Triple::thumbeb: 595 Builder.defineMacro("__ARM_DWARF_EH__"); 596 break; 597 } 598 } 599 public: 600 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 601 : OSTargetInfo<Target>(Triple, Opts) { 602 this->MCountName = "__mcount"; 603 } 604 }; 605 606 // PSP Target 607 template<typename Target> 608 class PSPTargetInfo : public OSTargetInfo<Target> { 609 protected: 610 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 611 MacroBuilder &Builder) const override { 612 // PSP defines; list based on the output of the pspdev gcc toolchain. 613 Builder.defineMacro("PSP"); 614 Builder.defineMacro("_PSP"); 615 Builder.defineMacro("__psp__"); 616 Builder.defineMacro("__ELF__"); 617 } 618 public: 619 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 620 }; 621 622 // PS3 PPU Target 623 template<typename Target> 624 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 625 protected: 626 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 627 MacroBuilder &Builder) const override { 628 // PS3 PPU defines. 629 Builder.defineMacro("__PPC__"); 630 Builder.defineMacro("__PPU__"); 631 Builder.defineMacro("__CELLOS_LV2__"); 632 Builder.defineMacro("__ELF__"); 633 Builder.defineMacro("__LP32__"); 634 Builder.defineMacro("_ARCH_PPC64"); 635 Builder.defineMacro("__powerpc64__"); 636 } 637 public: 638 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 639 : OSTargetInfo<Target>(Triple, Opts) { 640 this->LongWidth = this->LongAlign = 32; 641 this->PointerWidth = this->PointerAlign = 32; 642 this->IntMaxType = TargetInfo::SignedLongLong; 643 this->Int64Type = TargetInfo::SignedLongLong; 644 this->SizeType = TargetInfo::UnsignedInt; 645 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 646 } 647 }; 648 649 template <typename Target> 650 class PS4OSTargetInfo : public OSTargetInfo<Target> { 651 protected: 652 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 653 MacroBuilder &Builder) const override { 654 Builder.defineMacro("__FreeBSD__", "9"); 655 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 656 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 657 DefineStd(Builder, "unix", Opts); 658 Builder.defineMacro("__ELF__"); 659 Builder.defineMacro("__ORBIS__"); 660 } 661 public: 662 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 663 : OSTargetInfo<Target>(Triple, Opts) { 664 this->WCharType = this->UnsignedShort; 665 666 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 667 this->MaxTLSAlign = 256; 668 669 // On PS4, do not honor explicit bit field alignment, 670 // as in "__attribute__((aligned(2))) int b : 1;". 671 this->UseExplicitBitFieldAlignment = false; 672 673 switch (Triple.getArch()) { 674 default: 675 case llvm::Triple::x86_64: 676 this->MCountName = ".mcount"; 677 break; 678 } 679 } 680 }; 681 682 // Solaris target 683 template<typename Target> 684 class SolarisTargetInfo : public OSTargetInfo<Target> { 685 protected: 686 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 687 MacroBuilder &Builder) const override { 688 DefineStd(Builder, "sun", Opts); 689 DefineStd(Builder, "unix", Opts); 690 Builder.defineMacro("__ELF__"); 691 Builder.defineMacro("__svr4__"); 692 Builder.defineMacro("__SVR4"); 693 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 694 // newer, but to 500 for everything else. feature_test.h has a check to 695 // ensure that you are not using C99 with an old version of X/Open or C89 696 // with a new version. 697 if (Opts.C99) 698 Builder.defineMacro("_XOPEN_SOURCE", "600"); 699 else 700 Builder.defineMacro("_XOPEN_SOURCE", "500"); 701 if (Opts.CPlusPlus) 702 Builder.defineMacro("__C99FEATURES__"); 703 Builder.defineMacro("_LARGEFILE_SOURCE"); 704 Builder.defineMacro("_LARGEFILE64_SOURCE"); 705 Builder.defineMacro("__EXTENSIONS__"); 706 Builder.defineMacro("_REENTRANT"); 707 } 708 public: 709 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 710 : OSTargetInfo<Target>(Triple, Opts) { 711 this->WCharType = this->SignedInt; 712 // FIXME: WIntType should be SignedLong 713 } 714 }; 715 716 // Windows target 717 template<typename Target> 718 class WindowsTargetInfo : public OSTargetInfo<Target> { 719 protected: 720 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 721 MacroBuilder &Builder) const override { 722 Builder.defineMacro("_WIN32"); 723 } 724 void getVisualStudioDefines(const LangOptions &Opts, 725 MacroBuilder &Builder) const { 726 if (Opts.CPlusPlus) { 727 if (Opts.RTTIData) 728 Builder.defineMacro("_CPPRTTI"); 729 730 if (Opts.CXXExceptions) 731 Builder.defineMacro("_CPPUNWIND"); 732 } 733 734 if (Opts.Bool) 735 Builder.defineMacro("__BOOL_DEFINED"); 736 737 if (!Opts.CharIsSigned) 738 Builder.defineMacro("_CHAR_UNSIGNED"); 739 740 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 741 // but it works for now. 742 if (Opts.POSIXThreads) 743 Builder.defineMacro("_MT"); 744 745 if (Opts.MSCompatibilityVersion) { 746 Builder.defineMacro("_MSC_VER", 747 Twine(Opts.MSCompatibilityVersion / 100000)); 748 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 749 // FIXME We cannot encode the revision information into 32-bits 750 Builder.defineMacro("_MSC_BUILD", Twine(1)); 751 752 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 753 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 754 755 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 756 if (Opts.CPlusPlus1z) 757 Builder.defineMacro("_MSVC_LANG", "201403L"); 758 else if (Opts.CPlusPlus14) 759 Builder.defineMacro("_MSVC_LANG", "201402L"); 760 } 761 } 762 763 if (Opts.MicrosoftExt) { 764 Builder.defineMacro("_MSC_EXTENSIONS"); 765 766 if (Opts.CPlusPlus11) { 767 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 768 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 769 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 770 } 771 } 772 773 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 774 } 775 776 public: 777 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 778 : OSTargetInfo<Target>(Triple, Opts) {} 779 }; 780 781 template <typename Target> 782 class NaClTargetInfo : public OSTargetInfo<Target> { 783 protected: 784 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 785 MacroBuilder &Builder) const override { 786 if (Opts.POSIXThreads) 787 Builder.defineMacro("_REENTRANT"); 788 if (Opts.CPlusPlus) 789 Builder.defineMacro("_GNU_SOURCE"); 790 791 DefineStd(Builder, "unix", Opts); 792 Builder.defineMacro("__ELF__"); 793 Builder.defineMacro("__native_client__"); 794 } 795 796 public: 797 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 798 : OSTargetInfo<Target>(Triple, Opts) { 799 this->LongAlign = 32; 800 this->LongWidth = 32; 801 this->PointerAlign = 32; 802 this->PointerWidth = 32; 803 this->IntMaxType = TargetInfo::SignedLongLong; 804 this->Int64Type = TargetInfo::SignedLongLong; 805 this->DoubleAlign = 64; 806 this->LongDoubleWidth = 64; 807 this->LongDoubleAlign = 64; 808 this->LongLongWidth = 64; 809 this->LongLongAlign = 64; 810 this->SizeType = TargetInfo::UnsignedInt; 811 this->PtrDiffType = TargetInfo::SignedInt; 812 this->IntPtrType = TargetInfo::SignedInt; 813 // RegParmMax is inherited from the underlying architecture. 814 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 815 if (Triple.getArch() == llvm::Triple::arm) { 816 // Handled in ARM's setABI(). 817 } else if (Triple.getArch() == llvm::Triple::x86) { 818 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 819 } else if (Triple.getArch() == llvm::Triple::x86_64) { 820 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 821 } else if (Triple.getArch() == llvm::Triple::mipsel) { 822 // Handled on mips' setDataLayout. 823 } else { 824 assert(Triple.getArch() == llvm::Triple::le32); 825 this->resetDataLayout("e-p:32:32-i64:64"); 826 } 827 } 828 }; 829 830 // Fuchsia Target 831 template<typename Target> 832 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 833 protected: 834 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 835 MacroBuilder &Builder) const override { 836 Builder.defineMacro("__Fuchsia__"); 837 Builder.defineMacro("__ELF__"); 838 if (Opts.POSIXThreads) 839 Builder.defineMacro("_REENTRANT"); 840 // Required by the libc++ locale support. 841 if (Opts.CPlusPlus) 842 Builder.defineMacro("_GNU_SOURCE"); 843 } 844 public: 845 FuchsiaTargetInfo(const llvm::Triple &Triple, 846 const TargetOptions &Opts) 847 : OSTargetInfo<Target>(Triple, Opts) { 848 this->MCountName = "__mcount"; 849 } 850 }; 851 852 // WebAssembly target 853 template <typename Target> 854 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 855 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 856 MacroBuilder &Builder) const final { 857 // A common platform macro. 858 if (Opts.POSIXThreads) 859 Builder.defineMacro("_REENTRANT"); 860 // Follow g++ convention and predefine _GNU_SOURCE for C++. 861 if (Opts.CPlusPlus) 862 Builder.defineMacro("_GNU_SOURCE"); 863 } 864 865 // As an optimization, group static init code together in a section. 866 const char *getStaticInitSectionSpecifier() const final { 867 return ".text.__startup"; 868 } 869 870 public: 871 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 872 const TargetOptions &Opts) 873 : OSTargetInfo<Target>(Triple, Opts) { 874 this->MCountName = "__mcount"; 875 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 876 } 877 }; 878 879 //===----------------------------------------------------------------------===// 880 // Specific target implementations. 881 //===----------------------------------------------------------------------===// 882 883 // PPC abstract base class 884 class PPCTargetInfo : public TargetInfo { 885 static const Builtin::Info BuiltinInfo[]; 886 static const char * const GCCRegNames[]; 887 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 888 std::string CPU; 889 890 // Target cpu features. 891 bool HasAltivec; 892 bool HasVSX; 893 bool HasP8Vector; 894 bool HasP8Crypto; 895 bool HasDirectMove; 896 bool HasQPX; 897 bool HasHTM; 898 bool HasBPERMD; 899 bool HasExtDiv; 900 bool HasP9Vector; 901 902 protected: 903 std::string ABI; 904 905 public: 906 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 907 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false), 908 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 909 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 910 SuitableAlign = 128; 911 SimdDefaultAlign = 128; 912 LongDoubleWidth = LongDoubleAlign = 128; 913 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 914 } 915 916 /// \brief Flags for architecture specific defines. 917 typedef enum { 918 ArchDefineNone = 0, 919 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 920 ArchDefinePpcgr = 1 << 1, 921 ArchDefinePpcsq = 1 << 2, 922 ArchDefine440 = 1 << 3, 923 ArchDefine603 = 1 << 4, 924 ArchDefine604 = 1 << 5, 925 ArchDefinePwr4 = 1 << 6, 926 ArchDefinePwr5 = 1 << 7, 927 ArchDefinePwr5x = 1 << 8, 928 ArchDefinePwr6 = 1 << 9, 929 ArchDefinePwr6x = 1 << 10, 930 ArchDefinePwr7 = 1 << 11, 931 ArchDefinePwr8 = 1 << 12, 932 ArchDefinePwr9 = 1 << 13, 933 ArchDefineA2 = 1 << 14, 934 ArchDefineA2q = 1 << 15 935 } ArchDefineTypes; 936 937 // Set the language option for altivec based on our value. 938 void adjust(LangOptions &Opts) override { 939 if (HasAltivec) 940 Opts.AltiVec = 1; 941 TargetInfo::adjust(Opts); 942 } 943 944 // Note: GCC recognizes the following additional cpus: 945 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 946 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 947 // titan, rs64. 948 bool setCPU(const std::string &Name) override { 949 bool CPUKnown = llvm::StringSwitch<bool>(Name) 950 .Case("generic", true) 951 .Case("440", true) 952 .Case("450", true) 953 .Case("601", true) 954 .Case("602", true) 955 .Case("603", true) 956 .Case("603e", true) 957 .Case("603ev", true) 958 .Case("604", true) 959 .Case("604e", true) 960 .Case("620", true) 961 .Case("630", true) 962 .Case("g3", true) 963 .Case("7400", true) 964 .Case("g4", true) 965 .Case("7450", true) 966 .Case("g4+", true) 967 .Case("750", true) 968 .Case("970", true) 969 .Case("g5", true) 970 .Case("a2", true) 971 .Case("a2q", true) 972 .Case("e500mc", true) 973 .Case("e5500", true) 974 .Case("power3", true) 975 .Case("pwr3", true) 976 .Case("power4", true) 977 .Case("pwr4", true) 978 .Case("power5", true) 979 .Case("pwr5", true) 980 .Case("power5x", true) 981 .Case("pwr5x", true) 982 .Case("power6", true) 983 .Case("pwr6", true) 984 .Case("power6x", true) 985 .Case("pwr6x", true) 986 .Case("power7", true) 987 .Case("pwr7", true) 988 .Case("power8", true) 989 .Case("pwr8", true) 990 .Case("power9", true) 991 .Case("pwr9", true) 992 .Case("powerpc", true) 993 .Case("ppc", true) 994 .Case("powerpc64", true) 995 .Case("ppc64", true) 996 .Case("powerpc64le", true) 997 .Case("ppc64le", true) 998 .Default(false); 999 1000 if (CPUKnown) 1001 CPU = Name; 1002 1003 return CPUKnown; 1004 } 1005 1006 1007 StringRef getABI() const override { return ABI; } 1008 1009 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1010 return llvm::makeArrayRef(BuiltinInfo, 1011 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1012 } 1013 1014 bool isCLZForZeroUndef() const override { return false; } 1015 1016 void getTargetDefines(const LangOptions &Opts, 1017 MacroBuilder &Builder) const override; 1018 1019 bool 1020 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1021 StringRef CPU, 1022 const std::vector<std::string> &FeaturesVec) const override; 1023 1024 bool handleTargetFeatures(std::vector<std::string> &Features, 1025 DiagnosticsEngine &Diags) override; 1026 bool hasFeature(StringRef Feature) const override; 1027 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1028 bool Enabled) const override; 1029 1030 ArrayRef<const char *> getGCCRegNames() const override; 1031 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1032 bool validateAsmConstraint(const char *&Name, 1033 TargetInfo::ConstraintInfo &Info) const override { 1034 switch (*Name) { 1035 default: return false; 1036 case 'O': // Zero 1037 break; 1038 case 'b': // Base register 1039 case 'f': // Floating point register 1040 Info.setAllowsRegister(); 1041 break; 1042 // FIXME: The following are added to allow parsing. 1043 // I just took a guess at what the actions should be. 1044 // Also, is more specific checking needed? I.e. specific registers? 1045 case 'd': // Floating point register (containing 64-bit value) 1046 case 'v': // Altivec vector register 1047 Info.setAllowsRegister(); 1048 break; 1049 case 'w': 1050 switch (Name[1]) { 1051 case 'd':// VSX vector register to hold vector double data 1052 case 'f':// VSX vector register to hold vector float data 1053 case 's':// VSX vector register to hold scalar float data 1054 case 'a':// Any VSX register 1055 case 'c':// An individual CR bit 1056 break; 1057 default: 1058 return false; 1059 } 1060 Info.setAllowsRegister(); 1061 Name++; // Skip over 'w'. 1062 break; 1063 case 'h': // `MQ', `CTR', or `LINK' register 1064 case 'q': // `MQ' register 1065 case 'c': // `CTR' register 1066 case 'l': // `LINK' register 1067 case 'x': // `CR' register (condition register) number 0 1068 case 'y': // `CR' register (condition register) 1069 case 'z': // `XER[CA]' carry bit (part of the XER register) 1070 Info.setAllowsRegister(); 1071 break; 1072 case 'I': // Signed 16-bit constant 1073 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1074 // (use `L' instead for SImode constants) 1075 case 'K': // Unsigned 16-bit constant 1076 case 'L': // Signed 16-bit constant shifted left 16 bits 1077 case 'M': // Constant larger than 31 1078 case 'N': // Exact power of 2 1079 case 'P': // Constant whose negation is a signed 16-bit constant 1080 case 'G': // Floating point constant that can be loaded into a 1081 // register with one instruction per word 1082 case 'H': // Integer/Floating point constant that can be loaded 1083 // into a register using three instructions 1084 break; 1085 case 'm': // Memory operand. Note that on PowerPC targets, m can 1086 // include addresses that update the base register. It 1087 // is therefore only safe to use `m' in an asm statement 1088 // if that asm statement accesses the operand exactly once. 1089 // The asm statement must also use `%U<opno>' as a 1090 // placeholder for the "update" flag in the corresponding 1091 // load or store instruction. For example: 1092 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1093 // is correct but: 1094 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1095 // is not. Use es rather than m if you don't want the base 1096 // register to be updated. 1097 case 'e': 1098 if (Name[1] != 's') 1099 return false; 1100 // es: A "stable" memory operand; that is, one which does not 1101 // include any automodification of the base register. Unlike 1102 // `m', this constraint can be used in asm statements that 1103 // might access the operand several times, or that might not 1104 // access it at all. 1105 Info.setAllowsMemory(); 1106 Name++; // Skip over 'e'. 1107 break; 1108 case 'Q': // Memory operand that is an offset from a register (it is 1109 // usually better to use `m' or `es' in asm statements) 1110 case 'Z': // Memory operand that is an indexed or indirect from a 1111 // register (it is usually better to use `m' or `es' in 1112 // asm statements) 1113 Info.setAllowsMemory(); 1114 Info.setAllowsRegister(); 1115 break; 1116 case 'R': // AIX TOC entry 1117 case 'a': // Address operand that is an indexed or indirect from a 1118 // register (`p' is preferable for asm statements) 1119 case 'S': // Constant suitable as a 64-bit mask operand 1120 case 'T': // Constant suitable as a 32-bit mask operand 1121 case 'U': // System V Release 4 small data area reference 1122 case 't': // AND masks that can be performed by two rldic{l, r} 1123 // instructions 1124 case 'W': // Vector constant that does not require memory 1125 case 'j': // Vector constant that is all zeros. 1126 break; 1127 // End FIXME. 1128 } 1129 return true; 1130 } 1131 std::string convertConstraint(const char *&Constraint) const override { 1132 std::string R; 1133 switch (*Constraint) { 1134 case 'e': 1135 case 'w': 1136 // Two-character constraint; add "^" hint for later parsing. 1137 R = std::string("^") + std::string(Constraint, 2); 1138 Constraint++; 1139 break; 1140 default: 1141 return TargetInfo::convertConstraint(Constraint); 1142 } 1143 return R; 1144 } 1145 const char *getClobbers() const override { 1146 return ""; 1147 } 1148 int getEHDataRegisterNumber(unsigned RegNo) const override { 1149 if (RegNo == 0) return 3; 1150 if (RegNo == 1) return 4; 1151 return -1; 1152 } 1153 1154 bool hasSjLjLowering() const override { 1155 return true; 1156 } 1157 1158 bool useFloat128ManglingForLongDouble() const override { 1159 return LongDoubleWidth == 128 && 1160 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1161 getTriple().isOSBinFormatELF(); 1162 } 1163 }; 1164 1165 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1166 #define BUILTIN(ID, TYPE, ATTRS) \ 1167 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1168 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1169 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1170 #include "clang/Basic/BuiltinsPPC.def" 1171 }; 1172 1173 /// handleTargetFeatures - Perform initialization based on the user 1174 /// configured set of features. 1175 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1176 DiagnosticsEngine &Diags) { 1177 for (const auto &Feature : Features) { 1178 if (Feature == "+altivec") { 1179 HasAltivec = true; 1180 } else if (Feature == "+vsx") { 1181 HasVSX = true; 1182 } else if (Feature == "+bpermd") { 1183 HasBPERMD = true; 1184 } else if (Feature == "+extdiv") { 1185 HasExtDiv = true; 1186 } else if (Feature == "+power8-vector") { 1187 HasP8Vector = true; 1188 } else if (Feature == "+crypto") { 1189 HasP8Crypto = true; 1190 } else if (Feature == "+direct-move") { 1191 HasDirectMove = true; 1192 } else if (Feature == "+qpx") { 1193 HasQPX = true; 1194 } else if (Feature == "+htm") { 1195 HasHTM = true; 1196 } else if (Feature == "+float128") { 1197 HasFloat128 = true; 1198 } else if (Feature == "+power9-vector") { 1199 HasP9Vector = true; 1200 } 1201 // TODO: Finish this list and add an assert that we've handled them 1202 // all. 1203 } 1204 1205 return true; 1206 } 1207 1208 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1209 /// #defines that are not tied to a specific subtarget. 1210 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1211 MacroBuilder &Builder) const { 1212 // Target identification. 1213 Builder.defineMacro("__ppc__"); 1214 Builder.defineMacro("__PPC__"); 1215 Builder.defineMacro("_ARCH_PPC"); 1216 Builder.defineMacro("__powerpc__"); 1217 Builder.defineMacro("__POWERPC__"); 1218 if (PointerWidth == 64) { 1219 Builder.defineMacro("_ARCH_PPC64"); 1220 Builder.defineMacro("__powerpc64__"); 1221 Builder.defineMacro("__ppc64__"); 1222 Builder.defineMacro("__PPC64__"); 1223 } 1224 1225 // Target properties. 1226 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1227 Builder.defineMacro("_LITTLE_ENDIAN"); 1228 } else { 1229 if (getTriple().getOS() != llvm::Triple::NetBSD && 1230 getTriple().getOS() != llvm::Triple::OpenBSD) 1231 Builder.defineMacro("_BIG_ENDIAN"); 1232 } 1233 1234 // ABI options. 1235 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1236 Builder.defineMacro("_CALL_ELF", "1"); 1237 if (ABI == "elfv2") 1238 Builder.defineMacro("_CALL_ELF", "2"); 1239 1240 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 1241 // our suppport post-dates this and it should work on all 64-bit ppc linux 1242 // platforms. It is guaranteed to work on all elfv2 platforms. 1243 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 1244 Builder.defineMacro("_CALL_LINUX", "1"); 1245 1246 // Subtarget options. 1247 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1248 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1249 1250 // FIXME: Should be controlled by command line option. 1251 if (LongDoubleWidth == 128) { 1252 Builder.defineMacro("__LONG_DOUBLE_128__"); 1253 Builder.defineMacro("__LONGDOUBLE128"); 1254 } 1255 1256 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1257 if (ABI == "elfv2" || 1258 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1259 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1260 1261 // CPU identification. 1262 ArchDefineTypes defs = 1263 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1264 .Case("440", ArchDefineName) 1265 .Case("450", ArchDefineName | ArchDefine440) 1266 .Case("601", ArchDefineName) 1267 .Case("602", ArchDefineName | ArchDefinePpcgr) 1268 .Case("603", ArchDefineName | ArchDefinePpcgr) 1269 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1270 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1271 .Case("604", ArchDefineName | ArchDefinePpcgr) 1272 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1273 .Case("620", ArchDefineName | ArchDefinePpcgr) 1274 .Case("630", ArchDefineName | ArchDefinePpcgr) 1275 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1276 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1277 .Case("750", ArchDefineName | ArchDefinePpcgr) 1278 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1279 ArchDefinePpcsq) 1280 .Case("a2", ArchDefineA2) 1281 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1282 .Case("pwr3", ArchDefinePpcgr) 1283 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1284 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1285 ArchDefinePpcsq) 1286 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 | 1287 ArchDefinePpcgr | ArchDefinePpcsq) 1288 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 | 1289 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1290 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x | 1291 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1292 ArchDefinePpcsq) 1293 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 | 1294 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1295 ArchDefinePpcgr | ArchDefinePpcsq) 1296 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x | 1297 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1298 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1299 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 | 1300 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1301 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1302 ArchDefinePpcsq) 1303 .Case("power3", ArchDefinePpcgr) 1304 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1305 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1306 ArchDefinePpcsq) 1307 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1308 ArchDefinePpcgr | ArchDefinePpcsq) 1309 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1310 ArchDefinePwr4 | ArchDefinePpcgr | 1311 ArchDefinePpcsq) 1312 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1313 ArchDefinePwr5 | ArchDefinePwr4 | 1314 ArchDefinePpcgr | ArchDefinePpcsq) 1315 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | 1316 ArchDefinePwr5x | ArchDefinePwr5 | 1317 ArchDefinePwr4 | ArchDefinePpcgr | 1318 ArchDefinePpcsq) 1319 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1320 ArchDefinePwr6 | ArchDefinePwr5x | 1321 ArchDefinePwr5 | ArchDefinePwr4 | 1322 ArchDefinePpcgr | ArchDefinePpcsq) 1323 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 1324 ArchDefinePwr6x | ArchDefinePwr6 | 1325 ArchDefinePwr5x | ArchDefinePwr5 | 1326 ArchDefinePwr4 | ArchDefinePpcgr | 1327 ArchDefinePpcsq) 1328 // powerpc64le automatically defaults to at least power8. 1329 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1330 ArchDefinePwr6 | ArchDefinePwr5x | 1331 ArchDefinePwr5 | ArchDefinePwr4 | 1332 ArchDefinePpcgr | ArchDefinePpcsq) 1333 .Default(ArchDefineNone); 1334 1335 if (defs & ArchDefineName) 1336 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1337 if (defs & ArchDefinePpcgr) 1338 Builder.defineMacro("_ARCH_PPCGR"); 1339 if (defs & ArchDefinePpcsq) 1340 Builder.defineMacro("_ARCH_PPCSQ"); 1341 if (defs & ArchDefine440) 1342 Builder.defineMacro("_ARCH_440"); 1343 if (defs & ArchDefine603) 1344 Builder.defineMacro("_ARCH_603"); 1345 if (defs & ArchDefine604) 1346 Builder.defineMacro("_ARCH_604"); 1347 if (defs & ArchDefinePwr4) 1348 Builder.defineMacro("_ARCH_PWR4"); 1349 if (defs & ArchDefinePwr5) 1350 Builder.defineMacro("_ARCH_PWR5"); 1351 if (defs & ArchDefinePwr5x) 1352 Builder.defineMacro("_ARCH_PWR5X"); 1353 if (defs & ArchDefinePwr6) 1354 Builder.defineMacro("_ARCH_PWR6"); 1355 if (defs & ArchDefinePwr6x) 1356 Builder.defineMacro("_ARCH_PWR6X"); 1357 if (defs & ArchDefinePwr7) 1358 Builder.defineMacro("_ARCH_PWR7"); 1359 if (defs & ArchDefinePwr8) 1360 Builder.defineMacro("_ARCH_PWR8"); 1361 if (defs & ArchDefinePwr9) 1362 Builder.defineMacro("_ARCH_PWR9"); 1363 if (defs & ArchDefineA2) 1364 Builder.defineMacro("_ARCH_A2"); 1365 if (defs & ArchDefineA2q) { 1366 Builder.defineMacro("_ARCH_A2Q"); 1367 Builder.defineMacro("_ARCH_QP"); 1368 } 1369 1370 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1371 Builder.defineMacro("__bg__"); 1372 Builder.defineMacro("__THW_BLUEGENE__"); 1373 Builder.defineMacro("__bgq__"); 1374 Builder.defineMacro("__TOS_BGQ__"); 1375 } 1376 1377 if (HasAltivec) { 1378 Builder.defineMacro("__VEC__", "10206"); 1379 Builder.defineMacro("__ALTIVEC__"); 1380 } 1381 if (HasVSX) 1382 Builder.defineMacro("__VSX__"); 1383 if (HasP8Vector) 1384 Builder.defineMacro("__POWER8_VECTOR__"); 1385 if (HasP8Crypto) 1386 Builder.defineMacro("__CRYPTO__"); 1387 if (HasHTM) 1388 Builder.defineMacro("__HTM__"); 1389 if (HasFloat128) 1390 Builder.defineMacro("__FLOAT128__"); 1391 if (HasP9Vector) 1392 Builder.defineMacro("__POWER9_VECTOR__"); 1393 1394 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1395 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1397 if (PointerWidth == 64) 1398 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1399 1400 // We have support for the bswap intrinsics so we can define this. 1401 Builder.defineMacro("__HAVE_BSWAP__", "1"); 1402 1403 // FIXME: The following are not yet generated here by Clang, but are 1404 // generated by GCC: 1405 // 1406 // _SOFT_FLOAT_ 1407 // __RECIP_PRECISION__ 1408 // __APPLE_ALTIVEC__ 1409 // __RECIP__ 1410 // __RECIPF__ 1411 // __RSQRTE__ 1412 // __RSQRTEF__ 1413 // _SOFT_DOUBLE_ 1414 // __NO_LWSYNC__ 1415 // __CMODEL_MEDIUM__ 1416 // __CMODEL_LARGE__ 1417 // _CALL_SYSV 1418 // _CALL_DARWIN 1419 // __NO_FPRS__ 1420 } 1421 1422 // Handle explicit options being passed to the compiler here: if we've 1423 // explicitly turned off vsx and turned on any of: 1424 // - power8-vector 1425 // - direct-move 1426 // - float128 1427 // - power9-vector 1428 // then go ahead and error since the customer has expressed an incompatible 1429 // set of options. 1430 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1431 const std::vector<std::string> &FeaturesVec) { 1432 1433 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1434 FeaturesVec.end()) { 1435 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1436 FeaturesVec.end()) { 1437 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1438 << "-mno-vsx"; 1439 return false; 1440 } 1441 1442 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1443 FeaturesVec.end()) { 1444 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1445 << "-mno-vsx"; 1446 return false; 1447 } 1448 1449 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1450 FeaturesVec.end()) { 1451 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1452 << "-mno-vsx"; 1453 return false; 1454 } 1455 1456 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1457 FeaturesVec.end()) { 1458 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1459 << "-mno-vsx"; 1460 return false; 1461 } 1462 } 1463 1464 return true; 1465 } 1466 1467 bool PPCTargetInfo::initFeatureMap( 1468 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1469 const std::vector<std::string> &FeaturesVec) const { 1470 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1471 .Case("7400", true) 1472 .Case("g4", true) 1473 .Case("7450", true) 1474 .Case("g4+", true) 1475 .Case("970", true) 1476 .Case("g5", true) 1477 .Case("pwr6", true) 1478 .Case("pwr7", true) 1479 .Case("pwr8", true) 1480 .Case("pwr9", true) 1481 .Case("ppc64", true) 1482 .Case("ppc64le", true) 1483 .Default(false); 1484 1485 Features["qpx"] = (CPU == "a2q"); 1486 Features["power9-vector"] = (CPU == "pwr9"); 1487 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1488 .Case("ppc64le", true) 1489 .Case("pwr9", true) 1490 .Case("pwr8", true) 1491 .Default(false); 1492 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1493 .Case("ppc64le", true) 1494 .Case("pwr9", true) 1495 .Case("pwr8", true) 1496 .Default(false); 1497 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1498 .Case("ppc64le", true) 1499 .Case("pwr9", true) 1500 .Case("pwr8", true) 1501 .Case("pwr7", true) 1502 .Default(false); 1503 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1504 .Case("ppc64le", true) 1505 .Case("pwr9", true) 1506 .Case("pwr8", true) 1507 .Case("pwr7", true) 1508 .Default(false); 1509 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1510 .Case("ppc64le", true) 1511 .Case("pwr9", true) 1512 .Case("pwr8", true) 1513 .Default(false); 1514 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1515 .Case("ppc64le", true) 1516 .Case("pwr9", true) 1517 .Case("pwr8", true) 1518 .Case("pwr7", true) 1519 .Default(false); 1520 Features["htm"] = llvm::StringSwitch<bool>(CPU) 1521 .Case("ppc64le", true) 1522 .Case("pwr9", true) 1523 .Case("pwr8", true) 1524 .Default(false); 1525 1526 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1527 return false; 1528 1529 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1530 } 1531 1532 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1533 return llvm::StringSwitch<bool>(Feature) 1534 .Case("powerpc", true) 1535 .Case("altivec", HasAltivec) 1536 .Case("vsx", HasVSX) 1537 .Case("power8-vector", HasP8Vector) 1538 .Case("crypto", HasP8Crypto) 1539 .Case("direct-move", HasDirectMove) 1540 .Case("qpx", HasQPX) 1541 .Case("htm", HasHTM) 1542 .Case("bpermd", HasBPERMD) 1543 .Case("extdiv", HasExtDiv) 1544 .Case("float128", HasFloat128) 1545 .Case("power9-vector", HasP9Vector) 1546 .Default(false); 1547 } 1548 1549 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1550 StringRef Name, bool Enabled) const { 1551 if (Enabled) { 1552 // If we're enabling any of the vsx based features then enable vsx and 1553 // altivec. We'll diagnose any problems later. 1554 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name) 1555 .Case("vsx", true) 1556 .Case("direct-move", true) 1557 .Case("power8-vector", true) 1558 .Case("power9-vector", true) 1559 .Case("float128", true) 1560 .Default(false); 1561 if (FeatureHasVSX) 1562 Features["vsx"] = Features["altivec"] = true; 1563 if (Name == "power9-vector") 1564 Features["power8-vector"] = true; 1565 Features[Name] = true; 1566 } else { 1567 // If we're disabling altivec or vsx go ahead and disable all of the vsx 1568 // features. 1569 if ((Name == "altivec") || (Name == "vsx")) 1570 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] = 1571 Features["float128"] = Features["power9-vector"] = false; 1572 if (Name == "power8-vector") 1573 Features["power9-vector"] = false; 1574 Features[Name] = false; 1575 } 1576 } 1577 1578 const char * const PPCTargetInfo::GCCRegNames[] = { 1579 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1580 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1581 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1582 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1583 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1584 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1585 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1586 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1587 "mq", "lr", "ctr", "ap", 1588 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1589 "xer", 1590 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1591 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1592 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1593 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1594 "vrsave", "vscr", 1595 "spe_acc", "spefscr", 1596 "sfp" 1597 }; 1598 1599 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1600 return llvm::makeArrayRef(GCCRegNames); 1601 } 1602 1603 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1604 // While some of these aliases do map to different registers 1605 // they still share the same register name. 1606 { { "0" }, "r0" }, 1607 { { "1"}, "r1" }, 1608 { { "2" }, "r2" }, 1609 { { "3" }, "r3" }, 1610 { { "4" }, "r4" }, 1611 { { "5" }, "r5" }, 1612 { { "6" }, "r6" }, 1613 { { "7" }, "r7" }, 1614 { { "8" }, "r8" }, 1615 { { "9" }, "r9" }, 1616 { { "10" }, "r10" }, 1617 { { "11" }, "r11" }, 1618 { { "12" }, "r12" }, 1619 { { "13" }, "r13" }, 1620 { { "14" }, "r14" }, 1621 { { "15" }, "r15" }, 1622 { { "16" }, "r16" }, 1623 { { "17" }, "r17" }, 1624 { { "18" }, "r18" }, 1625 { { "19" }, "r19" }, 1626 { { "20" }, "r20" }, 1627 { { "21" }, "r21" }, 1628 { { "22" }, "r22" }, 1629 { { "23" }, "r23" }, 1630 { { "24" }, "r24" }, 1631 { { "25" }, "r25" }, 1632 { { "26" }, "r26" }, 1633 { { "27" }, "r27" }, 1634 { { "28" }, "r28" }, 1635 { { "29" }, "r29" }, 1636 { { "30" }, "r30" }, 1637 { { "31" }, "r31" }, 1638 { { "fr0" }, "f0" }, 1639 { { "fr1" }, "f1" }, 1640 { { "fr2" }, "f2" }, 1641 { { "fr3" }, "f3" }, 1642 { { "fr4" }, "f4" }, 1643 { { "fr5" }, "f5" }, 1644 { { "fr6" }, "f6" }, 1645 { { "fr7" }, "f7" }, 1646 { { "fr8" }, "f8" }, 1647 { { "fr9" }, "f9" }, 1648 { { "fr10" }, "f10" }, 1649 { { "fr11" }, "f11" }, 1650 { { "fr12" }, "f12" }, 1651 { { "fr13" }, "f13" }, 1652 { { "fr14" }, "f14" }, 1653 { { "fr15" }, "f15" }, 1654 { { "fr16" }, "f16" }, 1655 { { "fr17" }, "f17" }, 1656 { { "fr18" }, "f18" }, 1657 { { "fr19" }, "f19" }, 1658 { { "fr20" }, "f20" }, 1659 { { "fr21" }, "f21" }, 1660 { { "fr22" }, "f22" }, 1661 { { "fr23" }, "f23" }, 1662 { { "fr24" }, "f24" }, 1663 { { "fr25" }, "f25" }, 1664 { { "fr26" }, "f26" }, 1665 { { "fr27" }, "f27" }, 1666 { { "fr28" }, "f28" }, 1667 { { "fr29" }, "f29" }, 1668 { { "fr30" }, "f30" }, 1669 { { "fr31" }, "f31" }, 1670 { { "cc" }, "cr0" }, 1671 }; 1672 1673 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1674 return llvm::makeArrayRef(GCCRegAliases); 1675 } 1676 1677 class PPC32TargetInfo : public PPCTargetInfo { 1678 public: 1679 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1680 : PPCTargetInfo(Triple, Opts) { 1681 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1682 1683 switch (getTriple().getOS()) { 1684 case llvm::Triple::Linux: 1685 case llvm::Triple::FreeBSD: 1686 case llvm::Triple::NetBSD: 1687 SizeType = UnsignedInt; 1688 PtrDiffType = SignedInt; 1689 IntPtrType = SignedInt; 1690 break; 1691 default: 1692 break; 1693 } 1694 1695 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1696 LongDoubleWidth = LongDoubleAlign = 64; 1697 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1698 } 1699 1700 // PPC32 supports atomics up to 4 bytes. 1701 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1702 } 1703 1704 BuiltinVaListKind getBuiltinVaListKind() const override { 1705 // This is the ELF definition, and is overridden by the Darwin sub-target 1706 return TargetInfo::PowerABIBuiltinVaList; 1707 } 1708 }; 1709 1710 // Note: ABI differences may eventually require us to have a separate 1711 // TargetInfo for little endian. 1712 class PPC64TargetInfo : public PPCTargetInfo { 1713 public: 1714 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1715 : PPCTargetInfo(Triple, Opts) { 1716 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1717 IntMaxType = SignedLong; 1718 Int64Type = SignedLong; 1719 1720 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1721 resetDataLayout("e-m:e-i64:64-n32:64"); 1722 ABI = "elfv2"; 1723 } else { 1724 resetDataLayout("E-m:e-i64:64-n32:64"); 1725 ABI = "elfv1"; 1726 } 1727 1728 switch (getTriple().getOS()) { 1729 case llvm::Triple::FreeBSD: 1730 LongDoubleWidth = LongDoubleAlign = 64; 1731 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1732 break; 1733 case llvm::Triple::NetBSD: 1734 IntMaxType = SignedLongLong; 1735 Int64Type = SignedLongLong; 1736 break; 1737 default: 1738 break; 1739 } 1740 1741 // PPC64 supports atomics up to 8 bytes. 1742 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1743 } 1744 BuiltinVaListKind getBuiltinVaListKind() const override { 1745 return TargetInfo::CharPtrBuiltinVaList; 1746 } 1747 // PPC64 Linux-specific ABI options. 1748 bool setABI(const std::string &Name) override { 1749 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1750 ABI = Name; 1751 return true; 1752 } 1753 return false; 1754 } 1755 }; 1756 1757 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1758 public: 1759 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1760 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1761 HasAlignMac68kSupport = true; 1762 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1763 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1764 LongLongAlign = 32; 1765 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1766 } 1767 BuiltinVaListKind getBuiltinVaListKind() const override { 1768 return TargetInfo::CharPtrBuiltinVaList; 1769 } 1770 }; 1771 1772 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1773 public: 1774 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1775 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1776 HasAlignMac68kSupport = true; 1777 resetDataLayout("E-m:o-i64:64-n32:64"); 1778 } 1779 }; 1780 1781 static const unsigned NVPTXAddrSpaceMap[] = { 1782 0, // Default 1783 1, // opencl_global 1784 3, // opencl_local 1785 4, // opencl_constant 1786 // FIXME: generic has to be added to the target 1787 0, // opencl_generic 1788 1, // cuda_device 1789 4, // cuda_constant 1790 3, // cuda_shared 1791 }; 1792 1793 class NVPTXTargetInfo : public TargetInfo { 1794 static const char *const GCCRegNames[]; 1795 static const Builtin::Info BuiltinInfo[]; 1796 CudaArch GPU; 1797 std::unique_ptr<TargetInfo> HostTarget; 1798 1799 public: 1800 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1801 unsigned TargetPointerWidth) 1802 : TargetInfo(Triple) { 1803 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1804 "NVPTX only supports 32- and 64-bit modes."); 1805 1806 TLSSupported = false; 1807 AddrSpaceMap = &NVPTXAddrSpaceMap; 1808 UseAddrSpaceMapMangling = true; 1809 1810 // Define available target features 1811 // These must be defined in sorted order! 1812 NoAsmVariants = true; 1813 GPU = CudaArch::SM_20; 1814 1815 if (TargetPointerWidth == 32) 1816 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1817 else 1818 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1819 1820 // If possible, get a TargetInfo for our host triple, so we can match its 1821 // types. 1822 llvm::Triple HostTriple(Opts.HostTriple); 1823 if (!HostTriple.isNVPTX()) 1824 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1825 1826 // If no host target, make some guesses about the data layout and return. 1827 if (!HostTarget) { 1828 LongWidth = LongAlign = TargetPointerWidth; 1829 PointerWidth = PointerAlign = TargetPointerWidth; 1830 switch (TargetPointerWidth) { 1831 case 32: 1832 SizeType = TargetInfo::UnsignedInt; 1833 PtrDiffType = TargetInfo::SignedInt; 1834 IntPtrType = TargetInfo::SignedInt; 1835 break; 1836 case 64: 1837 SizeType = TargetInfo::UnsignedLong; 1838 PtrDiffType = TargetInfo::SignedLong; 1839 IntPtrType = TargetInfo::SignedLong; 1840 break; 1841 default: 1842 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1843 } 1844 return; 1845 } 1846 1847 // Copy properties from host target. 1848 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1849 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1850 BoolWidth = HostTarget->getBoolWidth(); 1851 BoolAlign = HostTarget->getBoolAlign(); 1852 IntWidth = HostTarget->getIntWidth(); 1853 IntAlign = HostTarget->getIntAlign(); 1854 HalfWidth = HostTarget->getHalfWidth(); 1855 HalfAlign = HostTarget->getHalfAlign(); 1856 FloatWidth = HostTarget->getFloatWidth(); 1857 FloatAlign = HostTarget->getFloatAlign(); 1858 DoubleWidth = HostTarget->getDoubleWidth(); 1859 DoubleAlign = HostTarget->getDoubleAlign(); 1860 LongWidth = HostTarget->getLongWidth(); 1861 LongAlign = HostTarget->getLongAlign(); 1862 LongLongWidth = HostTarget->getLongLongWidth(); 1863 LongLongAlign = HostTarget->getLongLongAlign(); 1864 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1865 NewAlign = HostTarget->getNewAlign(); 1866 DefaultAlignForAttributeAligned = 1867 HostTarget->getDefaultAlignForAttributeAligned(); 1868 SizeType = HostTarget->getSizeType(); 1869 IntMaxType = HostTarget->getIntMaxType(); 1870 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1871 IntPtrType = HostTarget->getIntPtrType(); 1872 WCharType = HostTarget->getWCharType(); 1873 WIntType = HostTarget->getWIntType(); 1874 Char16Type = HostTarget->getChar16Type(); 1875 Char32Type = HostTarget->getChar32Type(); 1876 Int64Type = HostTarget->getInt64Type(); 1877 SigAtomicType = HostTarget->getSigAtomicType(); 1878 ProcessIDType = HostTarget->getProcessIDType(); 1879 1880 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1881 UseZeroLengthBitfieldAlignment = 1882 HostTarget->useZeroLengthBitfieldAlignment(); 1883 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1884 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1885 1886 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1887 // we need those macros to be identical on host and device, because (among 1888 // other things) they affect which standard library classes are defined, and 1889 // we need all classes to be defined on both the host and device. 1890 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1891 1892 // Properties intentionally not copied from host: 1893 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1894 // host/device boundary. 1895 // - SuitableAlign: Not visible across the host/device boundary, and may 1896 // correctly be different on host/device, e.g. if host has wider vector 1897 // types than device. 1898 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1899 // as its double type, but that's not necessarily true on the host. 1900 // TODO: nvcc emits a warning when using long double on device; we should 1901 // do the same. 1902 } 1903 void getTargetDefines(const LangOptions &Opts, 1904 MacroBuilder &Builder) const override { 1905 Builder.defineMacro("__PTX__"); 1906 Builder.defineMacro("__NVPTX__"); 1907 if (Opts.CUDAIsDevice) { 1908 // Set __CUDA_ARCH__ for the GPU specified. 1909 std::string CUDAArchCode = [this] { 1910 switch (GPU) { 1911 case CudaArch::UNKNOWN: 1912 assert(false && "No GPU arch when compiling CUDA device code."); 1913 return ""; 1914 case CudaArch::SM_20: 1915 return "200"; 1916 case CudaArch::SM_21: 1917 return "210"; 1918 case CudaArch::SM_30: 1919 return "300"; 1920 case CudaArch::SM_32: 1921 return "320"; 1922 case CudaArch::SM_35: 1923 return "350"; 1924 case CudaArch::SM_37: 1925 return "370"; 1926 case CudaArch::SM_50: 1927 return "500"; 1928 case CudaArch::SM_52: 1929 return "520"; 1930 case CudaArch::SM_53: 1931 return "530"; 1932 case CudaArch::SM_60: 1933 return "600"; 1934 case CudaArch::SM_61: 1935 return "610"; 1936 case CudaArch::SM_62: 1937 return "620"; 1938 } 1939 llvm_unreachable("unhandled CudaArch"); 1940 }(); 1941 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1942 } 1943 } 1944 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1945 return llvm::makeArrayRef(BuiltinInfo, 1946 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1947 } 1948 bool 1949 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1950 StringRef CPU, 1951 const std::vector<std::string> &FeaturesVec) const override { 1952 Features["satom"] = GPU >= CudaArch::SM_60; 1953 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1954 } 1955 1956 bool hasFeature(StringRef Feature) const override { 1957 return llvm::StringSwitch<bool>(Feature) 1958 .Cases("ptx", "nvptx", true) 1959 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1960 .Default(false); 1961 } 1962 1963 ArrayRef<const char *> getGCCRegNames() const override; 1964 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1965 // No aliases. 1966 return None; 1967 } 1968 bool validateAsmConstraint(const char *&Name, 1969 TargetInfo::ConstraintInfo &Info) const override { 1970 switch (*Name) { 1971 default: 1972 return false; 1973 case 'c': 1974 case 'h': 1975 case 'r': 1976 case 'l': 1977 case 'f': 1978 case 'd': 1979 Info.setAllowsRegister(); 1980 return true; 1981 } 1982 } 1983 const char *getClobbers() const override { 1984 // FIXME: Is this really right? 1985 return ""; 1986 } 1987 BuiltinVaListKind getBuiltinVaListKind() const override { 1988 // FIXME: implement 1989 return TargetInfo::CharPtrBuiltinVaList; 1990 } 1991 bool setCPU(const std::string &Name) override { 1992 GPU = StringToCudaArch(Name); 1993 return GPU != CudaArch::UNKNOWN; 1994 } 1995 void setSupportedOpenCLOpts() override { 1996 auto &Opts = getSupportedOpenCLOpts(); 1997 Opts.support("cl_clang_storage_class_specifiers"); 1998 Opts.support("cl_khr_gl_sharing"); 1999 Opts.support("cl_khr_icd"); 2000 2001 Opts.support("cl_khr_fp64"); 2002 Opts.support("cl_khr_byte_addressable_store"); 2003 Opts.support("cl_khr_global_int32_base_atomics"); 2004 Opts.support("cl_khr_global_int32_extended_atomics"); 2005 Opts.support("cl_khr_local_int32_base_atomics"); 2006 Opts.support("cl_khr_local_int32_extended_atomics"); 2007 } 2008 2009 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2010 // CUDA compilations support all of the host's calling conventions. 2011 // 2012 // TODO: We should warn if you apply a non-default CC to anything other than 2013 // a host function. 2014 if (HostTarget) 2015 return HostTarget->checkCallingConvention(CC); 2016 return CCCR_Warning; 2017 } 2018 }; 2019 2020 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 2021 #define BUILTIN(ID, TYPE, ATTRS) \ 2022 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2023 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2024 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2025 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2026 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2027 #include "clang/Basic/BuiltinsNVPTX.def" 2028 }; 2029 2030 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 2031 2032 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 2033 return llvm::makeArrayRef(GCCRegNames); 2034 } 2035 2036 static const LangAS::Map AMDGPUPrivateIsZeroMap = { 2037 4, // Default 2038 1, // opencl_global 2039 3, // opencl_local 2040 2, // opencl_constant 2041 4, // opencl_generic 2042 1, // cuda_device 2043 2, // cuda_constant 2044 3 // cuda_shared 2045 }; 2046 static const LangAS::Map AMDGPUGenericIsZeroMap = { 2047 0, // Default 2048 1, // opencl_global 2049 3, // opencl_local 2050 2, // opencl_constant 2051 0, // opencl_generic 2052 1, // cuda_device 2053 2, // cuda_constant 2054 3 // cuda_shared 2055 }; 2056 2057 // If you edit the description strings, make sure you update 2058 // getPointerWidthV(). 2059 2060 static const char *const DataLayoutStringR600 = 2061 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2062 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2063 2064 static const char *const DataLayoutStringSIPrivateIsZero = 2065 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2066 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2067 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2068 2069 static const char *const DataLayoutStringSIGenericIsZero = 2070 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" 2071 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2072 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; 2073 2074 class AMDGPUTargetInfo final : public TargetInfo { 2075 static const Builtin::Info BuiltinInfo[]; 2076 static const char * const GCCRegNames[]; 2077 2078 struct AddrSpace { 2079 unsigned Generic, Global, Local, Constant, Private; 2080 AddrSpace(bool IsGenericZero_ = false){ 2081 if (IsGenericZero_) { 2082 Generic = 0; 2083 Global = 1; 2084 Local = 3; 2085 Constant = 2; 2086 Private = 5; 2087 } else { 2088 Generic = 4; 2089 Global = 1; 2090 Local = 3; 2091 Constant = 2; 2092 Private = 0; 2093 } 2094 } 2095 }; 2096 2097 /// \brief The GPU profiles supported by the AMDGPU target. 2098 enum GPUKind { 2099 GK_NONE, 2100 GK_R600, 2101 GK_R600_DOUBLE_OPS, 2102 GK_R700, 2103 GK_R700_DOUBLE_OPS, 2104 GK_EVERGREEN, 2105 GK_EVERGREEN_DOUBLE_OPS, 2106 GK_NORTHERN_ISLANDS, 2107 GK_CAYMAN, 2108 GK_GFX6, 2109 GK_GFX7, 2110 GK_GFX8, 2111 GK_GFX9 2112 } GPU; 2113 2114 bool hasFP64:1; 2115 bool hasFMAF:1; 2116 bool hasLDEXPF:1; 2117 const AddrSpace AS; 2118 2119 static bool hasFullSpeedFMAF32(StringRef GPUName) { 2120 return parseAMDGCNName(GPUName) >= GK_GFX9; 2121 } 2122 2123 static bool isAMDGCN(const llvm::Triple &TT) { 2124 return TT.getArch() == llvm::Triple::amdgcn; 2125 } 2126 2127 static bool isGenericZero(const llvm::Triple &TT) { 2128 return TT.getEnvironmentName() == "amdgiz" || 2129 TT.getEnvironmentName() == "amdgizcl"; 2130 } 2131 public: 2132 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2133 : TargetInfo(Triple) , 2134 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2135 hasFP64(false), 2136 hasFMAF(false), 2137 hasLDEXPF(false), 2138 AS(isGenericZero(Triple)){ 2139 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2140 hasFP64 = true; 2141 hasFMAF = true; 2142 hasLDEXPF = true; 2143 } 2144 auto IsGenericZero = isGenericZero(Triple); 2145 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2146 (IsGenericZero ? DataLayoutStringSIGenericIsZero : 2147 DataLayoutStringSIPrivateIsZero) 2148 : DataLayoutStringR600); 2149 assert(DataLayout->getAllocaAddrSpace() == AS.Private); 2150 2151 AddrSpaceMap = IsGenericZero ? &AMDGPUGenericIsZeroMap : 2152 &AMDGPUPrivateIsZeroMap; 2153 UseAddrSpaceMapMangling = true; 2154 } 2155 2156 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2157 if (GPU <= GK_CAYMAN) 2158 return 32; 2159 2160 if (AddrSpace == AS.Private || AddrSpace == AS.Local) { 2161 return 32; 2162 } 2163 return 64; 2164 } 2165 2166 uint64_t getMaxPointerWidth() const override { 2167 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2168 } 2169 2170 const char * getClobbers() const override { 2171 return ""; 2172 } 2173 2174 ArrayRef<const char *> getGCCRegNames() const override; 2175 2176 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2177 return None; 2178 } 2179 2180 bool validateAsmConstraint(const char *&Name, 2181 TargetInfo::ConstraintInfo &Info) const override { 2182 switch (*Name) { 2183 default: break; 2184 case 'v': // vgpr 2185 case 's': // sgpr 2186 Info.setAllowsRegister(); 2187 return true; 2188 } 2189 return false; 2190 } 2191 2192 bool initFeatureMap(llvm::StringMap<bool> &Features, 2193 DiagnosticsEngine &Diags, StringRef CPU, 2194 const std::vector<std::string> &FeatureVec) const override; 2195 2196 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2197 TargetOptions &TargetOpts) const override { 2198 bool hasFP32Denormals = false; 2199 bool hasFP64Denormals = false; 2200 for (auto &I : TargetOpts.FeaturesAsWritten) { 2201 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2202 hasFP32Denormals = true; 2203 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2204 hasFP64Denormals = true; 2205 } 2206 if (!hasFP32Denormals) 2207 TargetOpts.Features.push_back( 2208 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) && 2209 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2210 // Always do not flush fp64 or fp16 denorms. 2211 if (!hasFP64Denormals && hasFP64) 2212 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2213 } 2214 2215 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2216 return llvm::makeArrayRef(BuiltinInfo, 2217 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2218 } 2219 2220 void getTargetDefines(const LangOptions &Opts, 2221 MacroBuilder &Builder) const override { 2222 if (getTriple().getArch() == llvm::Triple::amdgcn) 2223 Builder.defineMacro("__AMDGCN__"); 2224 else 2225 Builder.defineMacro("__R600__"); 2226 2227 if (hasFMAF) 2228 Builder.defineMacro("__HAS_FMAF__"); 2229 if (hasLDEXPF) 2230 Builder.defineMacro("__HAS_LDEXPF__"); 2231 if (hasFP64) 2232 Builder.defineMacro("__HAS_FP64__"); 2233 } 2234 2235 BuiltinVaListKind getBuiltinVaListKind() const override { 2236 return TargetInfo::CharPtrBuiltinVaList; 2237 } 2238 2239 static GPUKind parseR600Name(StringRef Name) { 2240 return llvm::StringSwitch<GPUKind>(Name) 2241 .Case("r600" , GK_R600) 2242 .Case("rv610", GK_R600) 2243 .Case("rv620", GK_R600) 2244 .Case("rv630", GK_R600) 2245 .Case("rv635", GK_R600) 2246 .Case("rs780", GK_R600) 2247 .Case("rs880", GK_R600) 2248 .Case("rv670", GK_R600_DOUBLE_OPS) 2249 .Case("rv710", GK_R700) 2250 .Case("rv730", GK_R700) 2251 .Case("rv740", GK_R700_DOUBLE_OPS) 2252 .Case("rv770", GK_R700_DOUBLE_OPS) 2253 .Case("palm", GK_EVERGREEN) 2254 .Case("cedar", GK_EVERGREEN) 2255 .Case("sumo", GK_EVERGREEN) 2256 .Case("sumo2", GK_EVERGREEN) 2257 .Case("redwood", GK_EVERGREEN) 2258 .Case("juniper", GK_EVERGREEN) 2259 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2260 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2261 .Case("barts", GK_NORTHERN_ISLANDS) 2262 .Case("turks", GK_NORTHERN_ISLANDS) 2263 .Case("caicos", GK_NORTHERN_ISLANDS) 2264 .Case("cayman", GK_CAYMAN) 2265 .Case("aruba", GK_CAYMAN) 2266 .Default(GK_NONE); 2267 } 2268 2269 static GPUKind parseAMDGCNName(StringRef Name) { 2270 return llvm::StringSwitch<GPUKind>(Name) 2271 .Case("tahiti", GK_GFX6) 2272 .Case("pitcairn", GK_GFX6) 2273 .Case("verde", GK_GFX6) 2274 .Case("oland", GK_GFX6) 2275 .Case("hainan", GK_GFX6) 2276 .Case("bonaire", GK_GFX7) 2277 .Case("kabini", GK_GFX7) 2278 .Case("kaveri", GK_GFX7) 2279 .Case("hawaii", GK_GFX7) 2280 .Case("mullins", GK_GFX7) 2281 .Case("gfx700", GK_GFX7) 2282 .Case("gfx701", GK_GFX7) 2283 .Case("gfx702", GK_GFX7) 2284 .Case("tonga", GK_GFX8) 2285 .Case("iceland", GK_GFX8) 2286 .Case("carrizo", GK_GFX8) 2287 .Case("fiji", GK_GFX8) 2288 .Case("stoney", GK_GFX8) 2289 .Case("polaris10", GK_GFX8) 2290 .Case("polaris11", GK_GFX8) 2291 .Case("gfx800", GK_GFX8) 2292 .Case("gfx801", GK_GFX8) 2293 .Case("gfx802", GK_GFX8) 2294 .Case("gfx803", GK_GFX8) 2295 .Case("gfx804", GK_GFX8) 2296 .Case("gfx810", GK_GFX8) 2297 .Case("gfx900", GK_GFX9) 2298 .Case("gfx901", GK_GFX9) 2299 .Default(GK_NONE); 2300 } 2301 2302 bool setCPU(const std::string &Name) override { 2303 if (getTriple().getArch() == llvm::Triple::amdgcn) 2304 GPU = parseAMDGCNName(Name); 2305 else 2306 GPU = parseR600Name(Name); 2307 2308 return GPU != GK_NONE; 2309 } 2310 2311 void setSupportedOpenCLOpts() override { 2312 auto &Opts = getSupportedOpenCLOpts(); 2313 Opts.support("cl_clang_storage_class_specifiers"); 2314 Opts.support("cl_khr_icd"); 2315 2316 if (hasFP64) 2317 Opts.support("cl_khr_fp64"); 2318 if (GPU >= GK_EVERGREEN) { 2319 Opts.support("cl_khr_byte_addressable_store"); 2320 Opts.support("cl_khr_global_int32_base_atomics"); 2321 Opts.support("cl_khr_global_int32_extended_atomics"); 2322 Opts.support("cl_khr_local_int32_base_atomics"); 2323 Opts.support("cl_khr_local_int32_extended_atomics"); 2324 } 2325 if (GPU >= GK_GFX6) { 2326 Opts.support("cl_khr_fp16"); 2327 Opts.support("cl_khr_int64_base_atomics"); 2328 Opts.support("cl_khr_int64_extended_atomics"); 2329 Opts.support("cl_khr_mipmap_image"); 2330 Opts.support("cl_khr_subgroups"); 2331 Opts.support("cl_khr_3d_image_writes"); 2332 Opts.support("cl_amd_media_ops"); 2333 Opts.support("cl_amd_media_ops2"); 2334 } 2335 } 2336 2337 LangAS::ID getOpenCLImageAddrSpace() const override { 2338 return LangAS::opencl_constant; 2339 } 2340 2341 /// \returns Target specific vtbl ptr address space. 2342 unsigned getVtblPtrAddressSpace() const override { 2343 // \todo: We currently have address spaces defined in AMDGPU Backend. It 2344 // would be nice if we could use it here instead of using bare numbers (same 2345 // applies to getDWARFAddressSpace). 2346 return 2; // constant. 2347 } 2348 2349 /// \returns If a target requires an address within a target specific address 2350 /// space \p AddressSpace to be converted in order to be used, then return the 2351 /// corresponding target specific DWARF address space. 2352 /// 2353 /// \returns Otherwise return None and no conversion will be emitted in the 2354 /// DWARF. 2355 Optional<unsigned> getDWARFAddressSpace( 2356 unsigned AddressSpace) const override { 2357 const unsigned DWARF_Private = 1; 2358 const unsigned DWARF_Local = 2; 2359 if (AddressSpace == AS.Private) { 2360 return DWARF_Private; 2361 } else if (AddressSpace == AS.Local) { 2362 return DWARF_Local; 2363 } else { 2364 return None; 2365 } 2366 } 2367 2368 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2369 switch (CC) { 2370 default: 2371 return CCCR_Warning; 2372 case CC_C: 2373 case CC_OpenCLKernel: 2374 return CCCR_OK; 2375 } 2376 } 2377 2378 // In amdgcn target the null pointer in global, constant, and generic 2379 // address space has value 0 but in private and local address space has 2380 // value ~0. 2381 uint64_t getNullPointerValue(unsigned AS) const override { 2382 return AS == LangAS::opencl_local ? ~0 : 0; 2383 } 2384 }; 2385 2386 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2387 #define BUILTIN(ID, TYPE, ATTRS) \ 2388 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2389 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2390 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2391 #include "clang/Basic/BuiltinsAMDGPU.def" 2392 }; 2393 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2394 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2395 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2396 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2397 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2398 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2399 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2400 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2401 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2402 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2403 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2404 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2405 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2406 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2407 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2408 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2409 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2410 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2411 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2412 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2413 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2414 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2415 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2416 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2417 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2418 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2419 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2420 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2421 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2422 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2423 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2424 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2425 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2426 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2427 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2428 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2429 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2430 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2431 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2432 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2433 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2434 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2435 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2436 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2437 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2438 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2439 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2440 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2441 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2442 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2443 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2444 }; 2445 2446 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2447 return llvm::makeArrayRef(GCCRegNames); 2448 } 2449 2450 bool AMDGPUTargetInfo::initFeatureMap( 2451 llvm::StringMap<bool> &Features, 2452 DiagnosticsEngine &Diags, StringRef CPU, 2453 const std::vector<std::string> &FeatureVec) const { 2454 2455 // XXX - What does the member GPU mean if device name string passed here? 2456 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2457 if (CPU.empty()) 2458 CPU = "tahiti"; 2459 2460 switch (parseAMDGCNName(CPU)) { 2461 case GK_GFX6: 2462 case GK_GFX7: 2463 break; 2464 2465 case GK_GFX9: 2466 Features["gfx9-insts"] = true; 2467 LLVM_FALLTHROUGH; 2468 case GK_GFX8: 2469 Features["s-memrealtime"] = true; 2470 Features["16-bit-insts"] = true; 2471 Features["dpp"] = true; 2472 break; 2473 2474 case GK_NONE: 2475 return false; 2476 default: 2477 llvm_unreachable("unhandled subtarget"); 2478 } 2479 } else { 2480 if (CPU.empty()) 2481 CPU = "r600"; 2482 2483 switch (parseR600Name(CPU)) { 2484 case GK_R600: 2485 case GK_R700: 2486 case GK_EVERGREEN: 2487 case GK_NORTHERN_ISLANDS: 2488 break; 2489 case GK_R600_DOUBLE_OPS: 2490 case GK_R700_DOUBLE_OPS: 2491 case GK_EVERGREEN_DOUBLE_OPS: 2492 case GK_CAYMAN: 2493 Features["fp64"] = true; 2494 break; 2495 case GK_NONE: 2496 return false; 2497 default: 2498 llvm_unreachable("unhandled subtarget"); 2499 } 2500 } 2501 2502 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2503 } 2504 2505 const Builtin::Info BuiltinInfoX86[] = { 2506 #define BUILTIN(ID, TYPE, ATTRS) \ 2507 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2508 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2509 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2510 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2511 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2512 #include "clang/Basic/BuiltinsX86.def" 2513 2514 #define BUILTIN(ID, TYPE, ATTRS) \ 2515 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2516 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2517 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2518 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2519 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2520 #include "clang/Basic/BuiltinsX86_64.def" 2521 }; 2522 2523 2524 static const char* const GCCRegNames[] = { 2525 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2526 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2527 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2528 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2529 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2530 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2531 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2532 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2533 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2534 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2535 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2536 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2537 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2538 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2539 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2540 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2541 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2542 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2543 }; 2544 2545 const TargetInfo::AddlRegName AddlRegNames[] = { 2546 { { "al", "ah", "eax", "rax" }, 0 }, 2547 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2548 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2549 { { "dl", "dh", "edx", "rdx" }, 1 }, 2550 { { "esi", "rsi" }, 4 }, 2551 { { "edi", "rdi" }, 5 }, 2552 { { "esp", "rsp" }, 7 }, 2553 { { "ebp", "rbp" }, 6 }, 2554 { { "r8d", "r8w", "r8b" }, 38 }, 2555 { { "r9d", "r9w", "r9b" }, 39 }, 2556 { { "r10d", "r10w", "r10b" }, 40 }, 2557 { { "r11d", "r11w", "r11b" }, 41 }, 2558 { { "r12d", "r12w", "r12b" }, 42 }, 2559 { { "r13d", "r13w", "r13b" }, 43 }, 2560 { { "r14d", "r14w", "r14b" }, 44 }, 2561 { { "r15d", "r15w", "r15b" }, 45 }, 2562 }; 2563 2564 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2565 // most of the implementation can be shared. 2566 class X86TargetInfo : public TargetInfo { 2567 enum X86SSEEnum { 2568 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2569 } SSELevel = NoSSE; 2570 enum MMX3DNowEnum { 2571 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2572 } MMX3DNowLevel = NoMMX3DNow; 2573 enum XOPEnum { 2574 NoXOP, 2575 SSE4A, 2576 FMA4, 2577 XOP 2578 } XOPLevel = NoXOP; 2579 2580 bool HasAES = false; 2581 bool HasPCLMUL = false; 2582 bool HasLZCNT = false; 2583 bool HasRDRND = false; 2584 bool HasFSGSBASE = false; 2585 bool HasBMI = false; 2586 bool HasBMI2 = false; 2587 bool HasPOPCNT = false; 2588 bool HasRTM = false; 2589 bool HasPRFCHW = false; 2590 bool HasRDSEED = false; 2591 bool HasADX = false; 2592 bool HasTBM = false; 2593 bool HasFMA = false; 2594 bool HasF16C = false; 2595 bool HasAVX512CD = false; 2596 bool HasAVX512ER = false; 2597 bool HasAVX512PF = false; 2598 bool HasAVX512DQ = false; 2599 bool HasAVX512BW = false; 2600 bool HasAVX512VL = false; 2601 bool HasAVX512VBMI = false; 2602 bool HasAVX512IFMA = false; 2603 bool HasSHA = false; 2604 bool HasMPX = false; 2605 bool HasSGX = false; 2606 bool HasCX16 = false; 2607 bool HasFXSR = false; 2608 bool HasXSAVE = false; 2609 bool HasXSAVEOPT = false; 2610 bool HasXSAVEC = false; 2611 bool HasXSAVES = false; 2612 bool HasMWAITX = false; 2613 bool HasCLZERO = false; 2614 bool HasPKU = false; 2615 bool HasCLFLUSHOPT = false; 2616 bool HasCLWB = false; 2617 bool HasMOVBE = false; 2618 bool HasPREFETCHWT1 = false; 2619 2620 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2621 /// 2622 /// Each enumeration represents a particular CPU supported by Clang. These 2623 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2624 enum CPUKind { 2625 CK_Generic, 2626 2627 /// \name i386 2628 /// i386-generation processors. 2629 //@{ 2630 CK_i386, 2631 //@} 2632 2633 /// \name i486 2634 /// i486-generation processors. 2635 //@{ 2636 CK_i486, 2637 CK_WinChipC6, 2638 CK_WinChip2, 2639 CK_C3, 2640 //@} 2641 2642 /// \name i586 2643 /// i586-generation processors, P5 microarchitecture based. 2644 //@{ 2645 CK_i586, 2646 CK_Pentium, 2647 CK_PentiumMMX, 2648 //@} 2649 2650 /// \name i686 2651 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2652 //@{ 2653 CK_i686, 2654 CK_PentiumPro, 2655 CK_Pentium2, 2656 CK_Pentium3, 2657 CK_Pentium3M, 2658 CK_PentiumM, 2659 CK_C3_2, 2660 2661 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2662 /// Clang however has some logic to suport this. 2663 // FIXME: Warn, deprecate, and potentially remove this. 2664 CK_Yonah, 2665 //@} 2666 2667 /// \name Netburst 2668 /// Netburst microarchitecture based processors. 2669 //@{ 2670 CK_Pentium4, 2671 CK_Pentium4M, 2672 CK_Prescott, 2673 CK_Nocona, 2674 //@} 2675 2676 /// \name Core 2677 /// Core microarchitecture based processors. 2678 //@{ 2679 CK_Core2, 2680 2681 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2682 /// codename which GCC no longer accepts as an option to -march, but Clang 2683 /// has some logic for recognizing it. 2684 // FIXME: Warn, deprecate, and potentially remove this. 2685 CK_Penryn, 2686 //@} 2687 2688 /// \name Atom 2689 /// Atom processors 2690 //@{ 2691 CK_Bonnell, 2692 CK_Silvermont, 2693 //@} 2694 2695 /// \name Nehalem 2696 /// Nehalem microarchitecture based processors. 2697 CK_Nehalem, 2698 2699 /// \name Westmere 2700 /// Westmere microarchitecture based processors. 2701 CK_Westmere, 2702 2703 /// \name Sandy Bridge 2704 /// Sandy Bridge microarchitecture based processors. 2705 CK_SandyBridge, 2706 2707 /// \name Ivy Bridge 2708 /// Ivy Bridge microarchitecture based processors. 2709 CK_IvyBridge, 2710 2711 /// \name Haswell 2712 /// Haswell microarchitecture based processors. 2713 CK_Haswell, 2714 2715 /// \name Broadwell 2716 /// Broadwell microarchitecture based processors. 2717 CK_Broadwell, 2718 2719 /// \name Skylake Client 2720 /// Skylake client microarchitecture based processors. 2721 CK_SkylakeClient, 2722 2723 /// \name Skylake Server 2724 /// Skylake server microarchitecture based processors. 2725 CK_SkylakeServer, 2726 2727 /// \name Cannonlake Client 2728 /// Cannonlake client microarchitecture based processors. 2729 CK_Cannonlake, 2730 2731 /// \name Knights Landing 2732 /// Knights Landing processor. 2733 CK_KNL, 2734 2735 /// \name Lakemont 2736 /// Lakemont microarchitecture based processors. 2737 CK_Lakemont, 2738 2739 /// \name K6 2740 /// K6 architecture processors. 2741 //@{ 2742 CK_K6, 2743 CK_K6_2, 2744 CK_K6_3, 2745 //@} 2746 2747 /// \name K7 2748 /// K7 architecture processors. 2749 //@{ 2750 CK_Athlon, 2751 CK_AthlonThunderbird, 2752 CK_Athlon4, 2753 CK_AthlonXP, 2754 CK_AthlonMP, 2755 //@} 2756 2757 /// \name K8 2758 /// K8 architecture processors. 2759 //@{ 2760 CK_Athlon64, 2761 CK_Athlon64SSE3, 2762 CK_AthlonFX, 2763 CK_K8, 2764 CK_K8SSE3, 2765 CK_Opteron, 2766 CK_OpteronSSE3, 2767 CK_AMDFAM10, 2768 //@} 2769 2770 /// \name Bobcat 2771 /// Bobcat architecture processors. 2772 //@{ 2773 CK_BTVER1, 2774 CK_BTVER2, 2775 //@} 2776 2777 /// \name Bulldozer 2778 /// Bulldozer architecture processors. 2779 //@{ 2780 CK_BDVER1, 2781 CK_BDVER2, 2782 CK_BDVER3, 2783 CK_BDVER4, 2784 //@} 2785 2786 /// \name zen 2787 /// Zen architecture processors. 2788 //@{ 2789 CK_ZNVER1, 2790 //@} 2791 2792 /// This specification is deprecated and will be removed in the future. 2793 /// Users should prefer \see CK_K8. 2794 // FIXME: Warn on this when the CPU is set to it. 2795 //@{ 2796 CK_x86_64, 2797 //@} 2798 2799 /// \name Geode 2800 /// Geode processors. 2801 //@{ 2802 CK_Geode 2803 //@} 2804 } CPU = CK_Generic; 2805 2806 CPUKind getCPUKind(StringRef CPU) const { 2807 return llvm::StringSwitch<CPUKind>(CPU) 2808 .Case("i386", CK_i386) 2809 .Case("i486", CK_i486) 2810 .Case("winchip-c6", CK_WinChipC6) 2811 .Case("winchip2", CK_WinChip2) 2812 .Case("c3", CK_C3) 2813 .Case("i586", CK_i586) 2814 .Case("pentium", CK_Pentium) 2815 .Case("pentium-mmx", CK_PentiumMMX) 2816 .Case("i686", CK_i686) 2817 .Case("pentiumpro", CK_PentiumPro) 2818 .Case("pentium2", CK_Pentium2) 2819 .Case("pentium3", CK_Pentium3) 2820 .Case("pentium3m", CK_Pentium3M) 2821 .Case("pentium-m", CK_PentiumM) 2822 .Case("c3-2", CK_C3_2) 2823 .Case("yonah", CK_Yonah) 2824 .Case("pentium4", CK_Pentium4) 2825 .Case("pentium4m", CK_Pentium4M) 2826 .Case("prescott", CK_Prescott) 2827 .Case("nocona", CK_Nocona) 2828 .Case("core2", CK_Core2) 2829 .Case("penryn", CK_Penryn) 2830 .Case("bonnell", CK_Bonnell) 2831 .Case("atom", CK_Bonnell) // Legacy name. 2832 .Case("silvermont", CK_Silvermont) 2833 .Case("slm", CK_Silvermont) // Legacy name. 2834 .Case("nehalem", CK_Nehalem) 2835 .Case("corei7", CK_Nehalem) // Legacy name. 2836 .Case("westmere", CK_Westmere) 2837 .Case("sandybridge", CK_SandyBridge) 2838 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2839 .Case("ivybridge", CK_IvyBridge) 2840 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2841 .Case("haswell", CK_Haswell) 2842 .Case("core-avx2", CK_Haswell) // Legacy name. 2843 .Case("broadwell", CK_Broadwell) 2844 .Case("skylake", CK_SkylakeClient) 2845 .Case("skylake-avx512", CK_SkylakeServer) 2846 .Case("skx", CK_SkylakeServer) // Legacy name. 2847 .Case("cannonlake", CK_Cannonlake) 2848 .Case("knl", CK_KNL) 2849 .Case("lakemont", CK_Lakemont) 2850 .Case("k6", CK_K6) 2851 .Case("k6-2", CK_K6_2) 2852 .Case("k6-3", CK_K6_3) 2853 .Case("athlon", CK_Athlon) 2854 .Case("athlon-tbird", CK_AthlonThunderbird) 2855 .Case("athlon-4", CK_Athlon4) 2856 .Case("athlon-xp", CK_AthlonXP) 2857 .Case("athlon-mp", CK_AthlonMP) 2858 .Case("athlon64", CK_Athlon64) 2859 .Case("athlon64-sse3", CK_Athlon64SSE3) 2860 .Case("athlon-fx", CK_AthlonFX) 2861 .Case("k8", CK_K8) 2862 .Case("k8-sse3", CK_K8SSE3) 2863 .Case("opteron", CK_Opteron) 2864 .Case("opteron-sse3", CK_OpteronSSE3) 2865 .Case("barcelona", CK_AMDFAM10) 2866 .Case("amdfam10", CK_AMDFAM10) 2867 .Case("btver1", CK_BTVER1) 2868 .Case("btver2", CK_BTVER2) 2869 .Case("bdver1", CK_BDVER1) 2870 .Case("bdver2", CK_BDVER2) 2871 .Case("bdver3", CK_BDVER3) 2872 .Case("bdver4", CK_BDVER4) 2873 .Case("znver1", CK_ZNVER1) 2874 .Case("x86-64", CK_x86_64) 2875 .Case("geode", CK_Geode) 2876 .Default(CK_Generic); 2877 } 2878 2879 enum FPMathKind { 2880 FP_Default, 2881 FP_SSE, 2882 FP_387 2883 } FPMath = FP_Default; 2884 2885 public: 2886 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2887 : TargetInfo(Triple) { 2888 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2889 } 2890 unsigned getFloatEvalMethod() const override { 2891 // X87 evaluates with 80 bits "long double" precision. 2892 return SSELevel == NoSSE ? 2 : 0; 2893 } 2894 ArrayRef<const char *> getGCCRegNames() const override { 2895 return llvm::makeArrayRef(GCCRegNames); 2896 } 2897 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2898 return None; 2899 } 2900 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2901 return llvm::makeArrayRef(AddlRegNames); 2902 } 2903 bool validateCpuSupports(StringRef Name) const override; 2904 bool validateAsmConstraint(const char *&Name, 2905 TargetInfo::ConstraintInfo &info) const override; 2906 2907 bool validateGlobalRegisterVariable(StringRef RegName, 2908 unsigned RegSize, 2909 bool &HasSizeMismatch) const override { 2910 // esp and ebp are the only 32-bit registers the x86 backend can currently 2911 // handle. 2912 if (RegName.equals("esp") || RegName.equals("ebp")) { 2913 // Check that the register size is 32-bit. 2914 HasSizeMismatch = RegSize != 32; 2915 return true; 2916 } 2917 2918 return false; 2919 } 2920 2921 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2922 2923 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2924 2925 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2926 2927 std::string convertConstraint(const char *&Constraint) const override; 2928 const char *getClobbers() const override { 2929 return "~{dirflag},~{fpsr},~{flags}"; 2930 } 2931 2932 StringRef getConstraintRegister(const StringRef &Constraint, 2933 const StringRef &Expression) const override { 2934 StringRef::iterator I, E; 2935 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 2936 if (isalpha(*I)) 2937 break; 2938 } 2939 if (I == E) 2940 return ""; 2941 switch (*I) { 2942 // For the register constraints, return the matching register name 2943 case 'a': 2944 return "ax"; 2945 case 'b': 2946 return "bx"; 2947 case 'c': 2948 return "cx"; 2949 case 'd': 2950 return "dx"; 2951 case 'S': 2952 return "si"; 2953 case 'D': 2954 return "di"; 2955 // In case the constraint is 'r' we need to return Expression 2956 case 'r': 2957 return Expression; 2958 default: 2959 // Default value if there is no constraint for the register 2960 return ""; 2961 } 2962 return ""; 2963 } 2964 2965 void getTargetDefines(const LangOptions &Opts, 2966 MacroBuilder &Builder) const override; 2967 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2968 bool Enabled); 2969 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2970 bool Enabled); 2971 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2972 bool Enabled); 2973 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2974 StringRef Name, bool Enabled) const override { 2975 setFeatureEnabledImpl(Features, Name, Enabled); 2976 } 2977 // This exists purely to cut down on the number of virtual calls in 2978 // initFeatureMap which calls this repeatedly. 2979 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2980 StringRef Name, bool Enabled); 2981 bool 2982 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2983 StringRef CPU, 2984 const std::vector<std::string> &FeaturesVec) const override; 2985 bool hasFeature(StringRef Feature) const override; 2986 bool handleTargetFeatures(std::vector<std::string> &Features, 2987 DiagnosticsEngine &Diags) override; 2988 StringRef getABI() const override { 2989 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2990 return "avx512"; 2991 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2992 return "avx"; 2993 if (getTriple().getArch() == llvm::Triple::x86 && 2994 MMX3DNowLevel == NoMMX3DNow) 2995 return "no-mmx"; 2996 return ""; 2997 } 2998 bool setCPU(const std::string &Name) override { 2999 CPU = getCPUKind(Name); 3000 3001 // Perform any per-CPU checks necessary to determine if this CPU is 3002 // acceptable. 3003 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 3004 // invalid without explaining *why*. 3005 switch (CPU) { 3006 case CK_Generic: 3007 // No processor selected! 3008 return false; 3009 3010 case CK_i386: 3011 case CK_i486: 3012 case CK_WinChipC6: 3013 case CK_WinChip2: 3014 case CK_C3: 3015 case CK_i586: 3016 case CK_Pentium: 3017 case CK_PentiumMMX: 3018 case CK_i686: 3019 case CK_PentiumPro: 3020 case CK_Pentium2: 3021 case CK_Pentium3: 3022 case CK_Pentium3M: 3023 case CK_PentiumM: 3024 case CK_Yonah: 3025 case CK_C3_2: 3026 case CK_Pentium4: 3027 case CK_Pentium4M: 3028 case CK_Lakemont: 3029 case CK_Prescott: 3030 case CK_K6: 3031 case CK_K6_2: 3032 case CK_K6_3: 3033 case CK_Athlon: 3034 case CK_AthlonThunderbird: 3035 case CK_Athlon4: 3036 case CK_AthlonXP: 3037 case CK_AthlonMP: 3038 case CK_Geode: 3039 // Only accept certain architectures when compiling in 32-bit mode. 3040 if (getTriple().getArch() != llvm::Triple::x86) 3041 return false; 3042 3043 // Fallthrough 3044 case CK_Nocona: 3045 case CK_Core2: 3046 case CK_Penryn: 3047 case CK_Bonnell: 3048 case CK_Silvermont: 3049 case CK_Nehalem: 3050 case CK_Westmere: 3051 case CK_SandyBridge: 3052 case CK_IvyBridge: 3053 case CK_Haswell: 3054 case CK_Broadwell: 3055 case CK_SkylakeClient: 3056 case CK_SkylakeServer: 3057 case CK_Cannonlake: 3058 case CK_KNL: 3059 case CK_Athlon64: 3060 case CK_Athlon64SSE3: 3061 case CK_AthlonFX: 3062 case CK_K8: 3063 case CK_K8SSE3: 3064 case CK_Opteron: 3065 case CK_OpteronSSE3: 3066 case CK_AMDFAM10: 3067 case CK_BTVER1: 3068 case CK_BTVER2: 3069 case CK_BDVER1: 3070 case CK_BDVER2: 3071 case CK_BDVER3: 3072 case CK_BDVER4: 3073 case CK_ZNVER1: 3074 case CK_x86_64: 3075 return true; 3076 } 3077 llvm_unreachable("Unhandled CPU kind"); 3078 } 3079 3080 bool setFPMath(StringRef Name) override; 3081 3082 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3083 // Most of the non-ARM calling conventions are i386 conventions. 3084 switch (CC) { 3085 case CC_X86ThisCall: 3086 case CC_X86FastCall: 3087 case CC_X86StdCall: 3088 case CC_X86VectorCall: 3089 case CC_X86RegCall: 3090 case CC_C: 3091 case CC_Swift: 3092 case CC_X86Pascal: 3093 case CC_IntelOclBicc: 3094 return CCCR_OK; 3095 default: 3096 return CCCR_Warning; 3097 } 3098 } 3099 3100 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3101 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 3102 } 3103 3104 bool hasSjLjLowering() const override { 3105 return true; 3106 } 3107 3108 void setSupportedOpenCLOpts() override { 3109 getSupportedOpenCLOpts().supportAll(); 3110 } 3111 }; 3112 3113 bool X86TargetInfo::setFPMath(StringRef Name) { 3114 if (Name == "387") { 3115 FPMath = FP_387; 3116 return true; 3117 } 3118 if (Name == "sse") { 3119 FPMath = FP_SSE; 3120 return true; 3121 } 3122 return false; 3123 } 3124 3125 bool X86TargetInfo::initFeatureMap( 3126 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3127 const std::vector<std::string> &FeaturesVec) const { 3128 // FIXME: This *really* should not be here. 3129 // X86_64 always has SSE2. 3130 if (getTriple().getArch() == llvm::Triple::x86_64) 3131 setFeatureEnabledImpl(Features, "sse2", true); 3132 3133 const CPUKind Kind = getCPUKind(CPU); 3134 3135 // Enable X87 for all X86 processors but Lakemont. 3136 if (Kind != CK_Lakemont) 3137 setFeatureEnabledImpl(Features, "x87", true); 3138 3139 switch (Kind) { 3140 case CK_Generic: 3141 case CK_i386: 3142 case CK_i486: 3143 case CK_i586: 3144 case CK_Pentium: 3145 case CK_i686: 3146 case CK_PentiumPro: 3147 case CK_Lakemont: 3148 break; 3149 case CK_PentiumMMX: 3150 case CK_Pentium2: 3151 case CK_K6: 3152 case CK_WinChipC6: 3153 setFeatureEnabledImpl(Features, "mmx", true); 3154 break; 3155 case CK_Pentium3: 3156 case CK_Pentium3M: 3157 case CK_C3_2: 3158 setFeatureEnabledImpl(Features, "sse", true); 3159 setFeatureEnabledImpl(Features, "fxsr", true); 3160 break; 3161 case CK_PentiumM: 3162 case CK_Pentium4: 3163 case CK_Pentium4M: 3164 case CK_x86_64: 3165 setFeatureEnabledImpl(Features, "sse2", true); 3166 setFeatureEnabledImpl(Features, "fxsr", true); 3167 break; 3168 case CK_Yonah: 3169 case CK_Prescott: 3170 case CK_Nocona: 3171 setFeatureEnabledImpl(Features, "sse3", true); 3172 setFeatureEnabledImpl(Features, "fxsr", true); 3173 setFeatureEnabledImpl(Features, "cx16", true); 3174 break; 3175 case CK_Core2: 3176 case CK_Bonnell: 3177 setFeatureEnabledImpl(Features, "ssse3", true); 3178 setFeatureEnabledImpl(Features, "fxsr", true); 3179 setFeatureEnabledImpl(Features, "cx16", true); 3180 break; 3181 case CK_Penryn: 3182 setFeatureEnabledImpl(Features, "sse4.1", true); 3183 setFeatureEnabledImpl(Features, "fxsr", true); 3184 setFeatureEnabledImpl(Features, "cx16", true); 3185 break; 3186 case CK_Cannonlake: 3187 setFeatureEnabledImpl(Features, "avx512ifma", true); 3188 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3189 setFeatureEnabledImpl(Features, "sha", true); 3190 LLVM_FALLTHROUGH; 3191 case CK_SkylakeServer: 3192 setFeatureEnabledImpl(Features, "avx512f", true); 3193 setFeatureEnabledImpl(Features, "avx512cd", true); 3194 setFeatureEnabledImpl(Features, "avx512dq", true); 3195 setFeatureEnabledImpl(Features, "avx512bw", true); 3196 setFeatureEnabledImpl(Features, "avx512vl", true); 3197 setFeatureEnabledImpl(Features, "pku", true); 3198 setFeatureEnabledImpl(Features, "clwb", true); 3199 LLVM_FALLTHROUGH; 3200 case CK_SkylakeClient: 3201 setFeatureEnabledImpl(Features, "xsavec", true); 3202 setFeatureEnabledImpl(Features, "xsaves", true); 3203 setFeatureEnabledImpl(Features, "mpx", true); 3204 setFeatureEnabledImpl(Features, "sgx", true); 3205 setFeatureEnabledImpl(Features, "clflushopt", true); 3206 setFeatureEnabledImpl(Features, "rtm", true); 3207 LLVM_FALLTHROUGH; 3208 case CK_Broadwell: 3209 setFeatureEnabledImpl(Features, "rdseed", true); 3210 setFeatureEnabledImpl(Features, "adx", true); 3211 LLVM_FALLTHROUGH; 3212 case CK_Haswell: 3213 setFeatureEnabledImpl(Features, "avx2", true); 3214 setFeatureEnabledImpl(Features, "lzcnt", true); 3215 setFeatureEnabledImpl(Features, "bmi", true); 3216 setFeatureEnabledImpl(Features, "bmi2", true); 3217 setFeatureEnabledImpl(Features, "fma", true); 3218 setFeatureEnabledImpl(Features, "movbe", true); 3219 LLVM_FALLTHROUGH; 3220 case CK_IvyBridge: 3221 setFeatureEnabledImpl(Features, "rdrnd", true); 3222 setFeatureEnabledImpl(Features, "f16c", true); 3223 setFeatureEnabledImpl(Features, "fsgsbase", true); 3224 LLVM_FALLTHROUGH; 3225 case CK_SandyBridge: 3226 setFeatureEnabledImpl(Features, "avx", true); 3227 setFeatureEnabledImpl(Features, "xsave", true); 3228 setFeatureEnabledImpl(Features, "xsaveopt", true); 3229 LLVM_FALLTHROUGH; 3230 case CK_Westmere: 3231 case CK_Silvermont: 3232 setFeatureEnabledImpl(Features, "aes", true); 3233 setFeatureEnabledImpl(Features, "pclmul", true); 3234 LLVM_FALLTHROUGH; 3235 case CK_Nehalem: 3236 setFeatureEnabledImpl(Features, "sse4.2", true); 3237 setFeatureEnabledImpl(Features, "fxsr", true); 3238 setFeatureEnabledImpl(Features, "cx16", true); 3239 break; 3240 case CK_KNL: 3241 setFeatureEnabledImpl(Features, "avx512f", true); 3242 setFeatureEnabledImpl(Features, "avx512cd", true); 3243 setFeatureEnabledImpl(Features, "avx512er", true); 3244 setFeatureEnabledImpl(Features, "avx512pf", true); 3245 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3246 setFeatureEnabledImpl(Features, "fxsr", true); 3247 setFeatureEnabledImpl(Features, "rdseed", true); 3248 setFeatureEnabledImpl(Features, "adx", true); 3249 setFeatureEnabledImpl(Features, "lzcnt", true); 3250 setFeatureEnabledImpl(Features, "bmi", true); 3251 setFeatureEnabledImpl(Features, "bmi2", true); 3252 setFeatureEnabledImpl(Features, "rtm", true); 3253 setFeatureEnabledImpl(Features, "fma", true); 3254 setFeatureEnabledImpl(Features, "rdrnd", true); 3255 setFeatureEnabledImpl(Features, "f16c", true); 3256 setFeatureEnabledImpl(Features, "fsgsbase", true); 3257 setFeatureEnabledImpl(Features, "aes", true); 3258 setFeatureEnabledImpl(Features, "pclmul", true); 3259 setFeatureEnabledImpl(Features, "cx16", true); 3260 setFeatureEnabledImpl(Features, "xsaveopt", true); 3261 setFeatureEnabledImpl(Features, "xsave", true); 3262 setFeatureEnabledImpl(Features, "movbe", true); 3263 break; 3264 case CK_K6_2: 3265 case CK_K6_3: 3266 case CK_WinChip2: 3267 case CK_C3: 3268 setFeatureEnabledImpl(Features, "3dnow", true); 3269 break; 3270 case CK_Athlon: 3271 case CK_AthlonThunderbird: 3272 case CK_Geode: 3273 setFeatureEnabledImpl(Features, "3dnowa", true); 3274 break; 3275 case CK_Athlon4: 3276 case CK_AthlonXP: 3277 case CK_AthlonMP: 3278 setFeatureEnabledImpl(Features, "sse", true); 3279 setFeatureEnabledImpl(Features, "3dnowa", true); 3280 setFeatureEnabledImpl(Features, "fxsr", true); 3281 break; 3282 case CK_K8: 3283 case CK_Opteron: 3284 case CK_Athlon64: 3285 case CK_AthlonFX: 3286 setFeatureEnabledImpl(Features, "sse2", true); 3287 setFeatureEnabledImpl(Features, "3dnowa", true); 3288 setFeatureEnabledImpl(Features, "fxsr", true); 3289 break; 3290 case CK_AMDFAM10: 3291 setFeatureEnabledImpl(Features, "sse4a", true); 3292 setFeatureEnabledImpl(Features, "lzcnt", true); 3293 setFeatureEnabledImpl(Features, "popcnt", true); 3294 LLVM_FALLTHROUGH; 3295 case CK_K8SSE3: 3296 case CK_OpteronSSE3: 3297 case CK_Athlon64SSE3: 3298 setFeatureEnabledImpl(Features, "sse3", true); 3299 setFeatureEnabledImpl(Features, "3dnowa", true); 3300 setFeatureEnabledImpl(Features, "fxsr", true); 3301 break; 3302 case CK_BTVER2: 3303 setFeatureEnabledImpl(Features, "avx", true); 3304 setFeatureEnabledImpl(Features, "aes", true); 3305 setFeatureEnabledImpl(Features, "pclmul", true); 3306 setFeatureEnabledImpl(Features, "bmi", true); 3307 setFeatureEnabledImpl(Features, "f16c", true); 3308 setFeatureEnabledImpl(Features, "xsaveopt", true); 3309 LLVM_FALLTHROUGH; 3310 case CK_BTVER1: 3311 setFeatureEnabledImpl(Features, "ssse3", true); 3312 setFeatureEnabledImpl(Features, "sse4a", true); 3313 setFeatureEnabledImpl(Features, "lzcnt", true); 3314 setFeatureEnabledImpl(Features, "popcnt", true); 3315 setFeatureEnabledImpl(Features, "prfchw", true); 3316 setFeatureEnabledImpl(Features, "cx16", true); 3317 setFeatureEnabledImpl(Features, "fxsr", true); 3318 break; 3319 case CK_ZNVER1: 3320 setFeatureEnabledImpl(Features, "adx", true); 3321 setFeatureEnabledImpl(Features, "aes", true); 3322 setFeatureEnabledImpl(Features, "avx2", true); 3323 setFeatureEnabledImpl(Features, "bmi", true); 3324 setFeatureEnabledImpl(Features, "bmi2", true); 3325 setFeatureEnabledImpl(Features, "clflushopt", true); 3326 setFeatureEnabledImpl(Features, "clzero", true); 3327 setFeatureEnabledImpl(Features, "cx16", true); 3328 setFeatureEnabledImpl(Features, "f16c", true); 3329 setFeatureEnabledImpl(Features, "fma", true); 3330 setFeatureEnabledImpl(Features, "fsgsbase", true); 3331 setFeatureEnabledImpl(Features, "fxsr", true); 3332 setFeatureEnabledImpl(Features, "lzcnt", true); 3333 setFeatureEnabledImpl(Features, "mwaitx", true); 3334 setFeatureEnabledImpl(Features, "movbe", true); 3335 setFeatureEnabledImpl(Features, "pclmul", true); 3336 setFeatureEnabledImpl(Features, "popcnt", true); 3337 setFeatureEnabledImpl(Features, "prfchw", true); 3338 setFeatureEnabledImpl(Features, "rdrnd", true); 3339 setFeatureEnabledImpl(Features, "rdseed", true); 3340 setFeatureEnabledImpl(Features, "sha", true); 3341 setFeatureEnabledImpl(Features, "sse4a", true); 3342 setFeatureEnabledImpl(Features, "xsave", true); 3343 setFeatureEnabledImpl(Features, "xsavec", true); 3344 setFeatureEnabledImpl(Features, "xsaveopt", true); 3345 setFeatureEnabledImpl(Features, "xsaves", true); 3346 break; 3347 case CK_BDVER4: 3348 setFeatureEnabledImpl(Features, "avx2", true); 3349 setFeatureEnabledImpl(Features, "bmi2", true); 3350 setFeatureEnabledImpl(Features, "mwaitx", true); 3351 LLVM_FALLTHROUGH; 3352 case CK_BDVER3: 3353 setFeatureEnabledImpl(Features, "fsgsbase", true); 3354 setFeatureEnabledImpl(Features, "xsaveopt", true); 3355 LLVM_FALLTHROUGH; 3356 case CK_BDVER2: 3357 setFeatureEnabledImpl(Features, "bmi", true); 3358 setFeatureEnabledImpl(Features, "fma", true); 3359 setFeatureEnabledImpl(Features, "f16c", true); 3360 setFeatureEnabledImpl(Features, "tbm", true); 3361 LLVM_FALLTHROUGH; 3362 case CK_BDVER1: 3363 // xop implies avx, sse4a and fma4. 3364 setFeatureEnabledImpl(Features, "xop", true); 3365 setFeatureEnabledImpl(Features, "lzcnt", true); 3366 setFeatureEnabledImpl(Features, "aes", true); 3367 setFeatureEnabledImpl(Features, "pclmul", true); 3368 setFeatureEnabledImpl(Features, "prfchw", true); 3369 setFeatureEnabledImpl(Features, "cx16", true); 3370 setFeatureEnabledImpl(Features, "fxsr", true); 3371 setFeatureEnabledImpl(Features, "xsave", true); 3372 break; 3373 } 3374 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3375 return false; 3376 3377 // Can't do this earlier because we need to be able to explicitly enable 3378 // or disable these features and the things that they depend upon. 3379 3380 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3381 auto I = Features.find("sse4.2"); 3382 if (I != Features.end() && I->getValue() && 3383 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3384 FeaturesVec.end()) 3385 Features["popcnt"] = true; 3386 3387 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3388 I = Features.find("3dnow"); 3389 if (I != Features.end() && I->getValue() && 3390 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3391 FeaturesVec.end()) 3392 Features["prfchw"] = true; 3393 3394 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3395 // then enable MMX. 3396 I = Features.find("sse"); 3397 if (I != Features.end() && I->getValue() && 3398 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3399 FeaturesVec.end()) 3400 Features["mmx"] = true; 3401 3402 return true; 3403 } 3404 3405 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3406 X86SSEEnum Level, bool Enabled) { 3407 if (Enabled) { 3408 switch (Level) { 3409 case AVX512F: 3410 Features["avx512f"] = true; 3411 case AVX2: 3412 Features["avx2"] = true; 3413 case AVX: 3414 Features["avx"] = true; 3415 Features["xsave"] = true; 3416 case SSE42: 3417 Features["sse4.2"] = true; 3418 case SSE41: 3419 Features["sse4.1"] = true; 3420 case SSSE3: 3421 Features["ssse3"] = true; 3422 case SSE3: 3423 Features["sse3"] = true; 3424 case SSE2: 3425 Features["sse2"] = true; 3426 case SSE1: 3427 Features["sse"] = true; 3428 case NoSSE: 3429 break; 3430 } 3431 return; 3432 } 3433 3434 switch (Level) { 3435 case NoSSE: 3436 case SSE1: 3437 Features["sse"] = false; 3438 case SSE2: 3439 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3440 Features["sha"] = false; 3441 case SSE3: 3442 Features["sse3"] = false; 3443 setXOPLevel(Features, NoXOP, false); 3444 case SSSE3: 3445 Features["ssse3"] = false; 3446 case SSE41: 3447 Features["sse4.1"] = false; 3448 case SSE42: 3449 Features["sse4.2"] = false; 3450 case AVX: 3451 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3452 Features["xsaveopt"] = false; 3453 setXOPLevel(Features, FMA4, false); 3454 case AVX2: 3455 Features["avx2"] = false; 3456 case AVX512F: 3457 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3458 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3459 Features["avx512vl"] = Features["avx512vbmi"] = 3460 Features["avx512ifma"] = false; 3461 } 3462 } 3463 3464 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3465 MMX3DNowEnum Level, bool Enabled) { 3466 if (Enabled) { 3467 switch (Level) { 3468 case AMD3DNowAthlon: 3469 Features["3dnowa"] = true; 3470 case AMD3DNow: 3471 Features["3dnow"] = true; 3472 case MMX: 3473 Features["mmx"] = true; 3474 case NoMMX3DNow: 3475 break; 3476 } 3477 return; 3478 } 3479 3480 switch (Level) { 3481 case NoMMX3DNow: 3482 case MMX: 3483 Features["mmx"] = false; 3484 case AMD3DNow: 3485 Features["3dnow"] = false; 3486 case AMD3DNowAthlon: 3487 Features["3dnowa"] = false; 3488 } 3489 } 3490 3491 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3492 bool Enabled) { 3493 if (Enabled) { 3494 switch (Level) { 3495 case XOP: 3496 Features["xop"] = true; 3497 case FMA4: 3498 Features["fma4"] = true; 3499 setSSELevel(Features, AVX, true); 3500 case SSE4A: 3501 Features["sse4a"] = true; 3502 setSSELevel(Features, SSE3, true); 3503 case NoXOP: 3504 break; 3505 } 3506 return; 3507 } 3508 3509 switch (Level) { 3510 case NoXOP: 3511 case SSE4A: 3512 Features["sse4a"] = false; 3513 case FMA4: 3514 Features["fma4"] = false; 3515 case XOP: 3516 Features["xop"] = false; 3517 } 3518 } 3519 3520 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3521 StringRef Name, bool Enabled) { 3522 // This is a bit of a hack to deal with the sse4 target feature when used 3523 // as part of the target attribute. We handle sse4 correctly everywhere 3524 // else. See below for more information on how we handle the sse4 options. 3525 if (Name != "sse4") 3526 Features[Name] = Enabled; 3527 3528 if (Name == "mmx") { 3529 setMMXLevel(Features, MMX, Enabled); 3530 } else if (Name == "sse") { 3531 setSSELevel(Features, SSE1, Enabled); 3532 } else if (Name == "sse2") { 3533 setSSELevel(Features, SSE2, Enabled); 3534 } else if (Name == "sse3") { 3535 setSSELevel(Features, SSE3, Enabled); 3536 } else if (Name == "ssse3") { 3537 setSSELevel(Features, SSSE3, Enabled); 3538 } else if (Name == "sse4.2") { 3539 setSSELevel(Features, SSE42, Enabled); 3540 } else if (Name == "sse4.1") { 3541 setSSELevel(Features, SSE41, Enabled); 3542 } else if (Name == "3dnow") { 3543 setMMXLevel(Features, AMD3DNow, Enabled); 3544 } else if (Name == "3dnowa") { 3545 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3546 } else if (Name == "aes") { 3547 if (Enabled) 3548 setSSELevel(Features, SSE2, Enabled); 3549 } else if (Name == "pclmul") { 3550 if (Enabled) 3551 setSSELevel(Features, SSE2, Enabled); 3552 } else if (Name == "avx") { 3553 setSSELevel(Features, AVX, Enabled); 3554 } else if (Name == "avx2") { 3555 setSSELevel(Features, AVX2, Enabled); 3556 } else if (Name == "avx512f") { 3557 setSSELevel(Features, AVX512F, Enabled); 3558 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3559 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3560 Name == "avx512vbmi" || Name == "avx512ifma") { 3561 if (Enabled) 3562 setSSELevel(Features, AVX512F, Enabled); 3563 // Enable BWI instruction if VBMI is being enabled. 3564 if (Name == "avx512vbmi" && Enabled) 3565 Features["avx512bw"] = true; 3566 // Also disable VBMI if BWI is being disabled. 3567 if (Name == "avx512bw" && !Enabled) 3568 Features["avx512vbmi"] = false; 3569 } else if (Name == "fma") { 3570 if (Enabled) 3571 setSSELevel(Features, AVX, Enabled); 3572 } else if (Name == "fma4") { 3573 setXOPLevel(Features, FMA4, Enabled); 3574 } else if (Name == "xop") { 3575 setXOPLevel(Features, XOP, Enabled); 3576 } else if (Name == "sse4a") { 3577 setXOPLevel(Features, SSE4A, Enabled); 3578 } else if (Name == "f16c") { 3579 if (Enabled) 3580 setSSELevel(Features, AVX, Enabled); 3581 } else if (Name == "sha") { 3582 if (Enabled) 3583 setSSELevel(Features, SSE2, Enabled); 3584 } else if (Name == "sse4") { 3585 // We can get here via the __target__ attribute since that's not controlled 3586 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3587 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3588 // disabled. 3589 if (Enabled) 3590 setSSELevel(Features, SSE42, Enabled); 3591 else 3592 setSSELevel(Features, SSE41, Enabled); 3593 } else if (Name == "xsave") { 3594 if (!Enabled) 3595 Features["xsaveopt"] = false; 3596 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3597 if (Enabled) 3598 Features["xsave"] = true; 3599 } 3600 } 3601 3602 /// handleTargetFeatures - Perform initialization based on the user 3603 /// configured set of features. 3604 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3605 DiagnosticsEngine &Diags) { 3606 for (const auto &Feature : Features) { 3607 if (Feature[0] != '+') 3608 continue; 3609 3610 if (Feature == "+aes") { 3611 HasAES = true; 3612 } else if (Feature == "+pclmul") { 3613 HasPCLMUL = true; 3614 } else if (Feature == "+lzcnt") { 3615 HasLZCNT = true; 3616 } else if (Feature == "+rdrnd") { 3617 HasRDRND = true; 3618 } else if (Feature == "+fsgsbase") { 3619 HasFSGSBASE = true; 3620 } else if (Feature == "+bmi") { 3621 HasBMI = true; 3622 } else if (Feature == "+bmi2") { 3623 HasBMI2 = true; 3624 } else if (Feature == "+popcnt") { 3625 HasPOPCNT = true; 3626 } else if (Feature == "+rtm") { 3627 HasRTM = true; 3628 } else if (Feature == "+prfchw") { 3629 HasPRFCHW = true; 3630 } else if (Feature == "+rdseed") { 3631 HasRDSEED = true; 3632 } else if (Feature == "+adx") { 3633 HasADX = true; 3634 } else if (Feature == "+tbm") { 3635 HasTBM = true; 3636 } else if (Feature == "+fma") { 3637 HasFMA = true; 3638 } else if (Feature == "+f16c") { 3639 HasF16C = true; 3640 } else if (Feature == "+avx512cd") { 3641 HasAVX512CD = true; 3642 } else if (Feature == "+avx512er") { 3643 HasAVX512ER = true; 3644 } else if (Feature == "+avx512pf") { 3645 HasAVX512PF = true; 3646 } else if (Feature == "+avx512dq") { 3647 HasAVX512DQ = true; 3648 } else if (Feature == "+avx512bw") { 3649 HasAVX512BW = true; 3650 } else if (Feature == "+avx512vl") { 3651 HasAVX512VL = true; 3652 } else if (Feature == "+avx512vbmi") { 3653 HasAVX512VBMI = true; 3654 } else if (Feature == "+avx512ifma") { 3655 HasAVX512IFMA = true; 3656 } else if (Feature == "+sha") { 3657 HasSHA = true; 3658 } else if (Feature == "+mpx") { 3659 HasMPX = true; 3660 } else if (Feature == "+movbe") { 3661 HasMOVBE = true; 3662 } else if (Feature == "+sgx") { 3663 HasSGX = true; 3664 } else if (Feature == "+cx16") { 3665 HasCX16 = true; 3666 } else if (Feature == "+fxsr") { 3667 HasFXSR = true; 3668 } else if (Feature == "+xsave") { 3669 HasXSAVE = true; 3670 } else if (Feature == "+xsaveopt") { 3671 HasXSAVEOPT = true; 3672 } else if (Feature == "+xsavec") { 3673 HasXSAVEC = true; 3674 } else if (Feature == "+xsaves") { 3675 HasXSAVES = true; 3676 } else if (Feature == "+mwaitx") { 3677 HasMWAITX = true; 3678 } else if (Feature == "+pku") { 3679 HasPKU = true; 3680 } else if (Feature == "+clflushopt") { 3681 HasCLFLUSHOPT = true; 3682 } else if (Feature == "+clwb") { 3683 HasCLWB = true; 3684 } else if (Feature == "+prefetchwt1") { 3685 HasPREFETCHWT1 = true; 3686 } else if (Feature == "+clzero") { 3687 HasCLZERO = true; 3688 } 3689 3690 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3691 .Case("+avx512f", AVX512F) 3692 .Case("+avx2", AVX2) 3693 .Case("+avx", AVX) 3694 .Case("+sse4.2", SSE42) 3695 .Case("+sse4.1", SSE41) 3696 .Case("+ssse3", SSSE3) 3697 .Case("+sse3", SSE3) 3698 .Case("+sse2", SSE2) 3699 .Case("+sse", SSE1) 3700 .Default(NoSSE); 3701 SSELevel = std::max(SSELevel, Level); 3702 3703 MMX3DNowEnum ThreeDNowLevel = 3704 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3705 .Case("+3dnowa", AMD3DNowAthlon) 3706 .Case("+3dnow", AMD3DNow) 3707 .Case("+mmx", MMX) 3708 .Default(NoMMX3DNow); 3709 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3710 3711 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3712 .Case("+xop", XOP) 3713 .Case("+fma4", FMA4) 3714 .Case("+sse4a", SSE4A) 3715 .Default(NoXOP); 3716 XOPLevel = std::max(XOPLevel, XLevel); 3717 } 3718 3719 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3720 // matches the selected sse level. 3721 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3722 (FPMath == FP_387 && SSELevel >= SSE1)) { 3723 Diags.Report(diag::err_target_unsupported_fpmath) << 3724 (FPMath == FP_SSE ? "sse" : "387"); 3725 return false; 3726 } 3727 3728 SimdDefaultAlign = 3729 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3730 return true; 3731 } 3732 3733 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3734 /// definitions for this particular subtarget. 3735 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3736 MacroBuilder &Builder) const { 3737 // Target identification. 3738 if (getTriple().getArch() == llvm::Triple::x86_64) { 3739 Builder.defineMacro("__amd64__"); 3740 Builder.defineMacro("__amd64"); 3741 Builder.defineMacro("__x86_64"); 3742 Builder.defineMacro("__x86_64__"); 3743 if (getTriple().getArchName() == "x86_64h") { 3744 Builder.defineMacro("__x86_64h"); 3745 Builder.defineMacro("__x86_64h__"); 3746 } 3747 } else { 3748 DefineStd(Builder, "i386", Opts); 3749 } 3750 3751 // Subtarget options. 3752 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3753 // truly should be based on -mtune options. 3754 switch (CPU) { 3755 case CK_Generic: 3756 break; 3757 case CK_i386: 3758 // The rest are coming from the i386 define above. 3759 Builder.defineMacro("__tune_i386__"); 3760 break; 3761 case CK_i486: 3762 case CK_WinChipC6: 3763 case CK_WinChip2: 3764 case CK_C3: 3765 defineCPUMacros(Builder, "i486"); 3766 break; 3767 case CK_PentiumMMX: 3768 Builder.defineMacro("__pentium_mmx__"); 3769 Builder.defineMacro("__tune_pentium_mmx__"); 3770 // Fallthrough 3771 case CK_i586: 3772 case CK_Pentium: 3773 defineCPUMacros(Builder, "i586"); 3774 defineCPUMacros(Builder, "pentium"); 3775 break; 3776 case CK_Pentium3: 3777 case CK_Pentium3M: 3778 case CK_PentiumM: 3779 Builder.defineMacro("__tune_pentium3__"); 3780 // Fallthrough 3781 case CK_Pentium2: 3782 case CK_C3_2: 3783 Builder.defineMacro("__tune_pentium2__"); 3784 // Fallthrough 3785 case CK_PentiumPro: 3786 Builder.defineMacro("__tune_i686__"); 3787 Builder.defineMacro("__tune_pentiumpro__"); 3788 // Fallthrough 3789 case CK_i686: 3790 Builder.defineMacro("__i686"); 3791 Builder.defineMacro("__i686__"); 3792 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3793 Builder.defineMacro("__pentiumpro"); 3794 Builder.defineMacro("__pentiumpro__"); 3795 break; 3796 case CK_Pentium4: 3797 case CK_Pentium4M: 3798 defineCPUMacros(Builder, "pentium4"); 3799 break; 3800 case CK_Yonah: 3801 case CK_Prescott: 3802 case CK_Nocona: 3803 defineCPUMacros(Builder, "nocona"); 3804 break; 3805 case CK_Core2: 3806 case CK_Penryn: 3807 defineCPUMacros(Builder, "core2"); 3808 break; 3809 case CK_Bonnell: 3810 defineCPUMacros(Builder, "atom"); 3811 break; 3812 case CK_Silvermont: 3813 defineCPUMacros(Builder, "slm"); 3814 break; 3815 case CK_Nehalem: 3816 case CK_Westmere: 3817 case CK_SandyBridge: 3818 case CK_IvyBridge: 3819 case CK_Haswell: 3820 case CK_Broadwell: 3821 case CK_SkylakeClient: 3822 // FIXME: Historically, we defined this legacy name, it would be nice to 3823 // remove it at some point. We've never exposed fine-grained names for 3824 // recent primary x86 CPUs, and we should keep it that way. 3825 defineCPUMacros(Builder, "corei7"); 3826 break; 3827 case CK_SkylakeServer: 3828 defineCPUMacros(Builder, "skx"); 3829 break; 3830 case CK_Cannonlake: 3831 break; 3832 case CK_KNL: 3833 defineCPUMacros(Builder, "knl"); 3834 break; 3835 case CK_Lakemont: 3836 Builder.defineMacro("__tune_lakemont__"); 3837 break; 3838 case CK_K6_2: 3839 Builder.defineMacro("__k6_2__"); 3840 Builder.defineMacro("__tune_k6_2__"); 3841 // Fallthrough 3842 case CK_K6_3: 3843 if (CPU != CK_K6_2) { // In case of fallthrough 3844 // FIXME: GCC may be enabling these in cases where some other k6 3845 // architecture is specified but -m3dnow is explicitly provided. The 3846 // exact semantics need to be determined and emulated here. 3847 Builder.defineMacro("__k6_3__"); 3848 Builder.defineMacro("__tune_k6_3__"); 3849 } 3850 // Fallthrough 3851 case CK_K6: 3852 defineCPUMacros(Builder, "k6"); 3853 break; 3854 case CK_Athlon: 3855 case CK_AthlonThunderbird: 3856 case CK_Athlon4: 3857 case CK_AthlonXP: 3858 case CK_AthlonMP: 3859 defineCPUMacros(Builder, "athlon"); 3860 if (SSELevel != NoSSE) { 3861 Builder.defineMacro("__athlon_sse__"); 3862 Builder.defineMacro("__tune_athlon_sse__"); 3863 } 3864 break; 3865 case CK_K8: 3866 case CK_K8SSE3: 3867 case CK_x86_64: 3868 case CK_Opteron: 3869 case CK_OpteronSSE3: 3870 case CK_Athlon64: 3871 case CK_Athlon64SSE3: 3872 case CK_AthlonFX: 3873 defineCPUMacros(Builder, "k8"); 3874 break; 3875 case CK_AMDFAM10: 3876 defineCPUMacros(Builder, "amdfam10"); 3877 break; 3878 case CK_BTVER1: 3879 defineCPUMacros(Builder, "btver1"); 3880 break; 3881 case CK_BTVER2: 3882 defineCPUMacros(Builder, "btver2"); 3883 break; 3884 case CK_BDVER1: 3885 defineCPUMacros(Builder, "bdver1"); 3886 break; 3887 case CK_BDVER2: 3888 defineCPUMacros(Builder, "bdver2"); 3889 break; 3890 case CK_BDVER3: 3891 defineCPUMacros(Builder, "bdver3"); 3892 break; 3893 case CK_BDVER4: 3894 defineCPUMacros(Builder, "bdver4"); 3895 break; 3896 case CK_ZNVER1: 3897 defineCPUMacros(Builder, "znver1"); 3898 break; 3899 case CK_Geode: 3900 defineCPUMacros(Builder, "geode"); 3901 break; 3902 } 3903 3904 // Target properties. 3905 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3906 3907 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3908 // functions in glibc header files that use FP Stack inline asm which the 3909 // backend can't deal with (PR879). 3910 Builder.defineMacro("__NO_MATH_INLINES"); 3911 3912 if (HasAES) 3913 Builder.defineMacro("__AES__"); 3914 3915 if (HasPCLMUL) 3916 Builder.defineMacro("__PCLMUL__"); 3917 3918 if (HasLZCNT) 3919 Builder.defineMacro("__LZCNT__"); 3920 3921 if (HasRDRND) 3922 Builder.defineMacro("__RDRND__"); 3923 3924 if (HasFSGSBASE) 3925 Builder.defineMacro("__FSGSBASE__"); 3926 3927 if (HasBMI) 3928 Builder.defineMacro("__BMI__"); 3929 3930 if (HasBMI2) 3931 Builder.defineMacro("__BMI2__"); 3932 3933 if (HasPOPCNT) 3934 Builder.defineMacro("__POPCNT__"); 3935 3936 if (HasRTM) 3937 Builder.defineMacro("__RTM__"); 3938 3939 if (HasPRFCHW) 3940 Builder.defineMacro("__PRFCHW__"); 3941 3942 if (HasRDSEED) 3943 Builder.defineMacro("__RDSEED__"); 3944 3945 if (HasADX) 3946 Builder.defineMacro("__ADX__"); 3947 3948 if (HasTBM) 3949 Builder.defineMacro("__TBM__"); 3950 3951 if (HasMWAITX) 3952 Builder.defineMacro("__MWAITX__"); 3953 3954 switch (XOPLevel) { 3955 case XOP: 3956 Builder.defineMacro("__XOP__"); 3957 case FMA4: 3958 Builder.defineMacro("__FMA4__"); 3959 case SSE4A: 3960 Builder.defineMacro("__SSE4A__"); 3961 case NoXOP: 3962 break; 3963 } 3964 3965 if (HasFMA) 3966 Builder.defineMacro("__FMA__"); 3967 3968 if (HasF16C) 3969 Builder.defineMacro("__F16C__"); 3970 3971 if (HasAVX512CD) 3972 Builder.defineMacro("__AVX512CD__"); 3973 if (HasAVX512ER) 3974 Builder.defineMacro("__AVX512ER__"); 3975 if (HasAVX512PF) 3976 Builder.defineMacro("__AVX512PF__"); 3977 if (HasAVX512DQ) 3978 Builder.defineMacro("__AVX512DQ__"); 3979 if (HasAVX512BW) 3980 Builder.defineMacro("__AVX512BW__"); 3981 if (HasAVX512VL) 3982 Builder.defineMacro("__AVX512VL__"); 3983 if (HasAVX512VBMI) 3984 Builder.defineMacro("__AVX512VBMI__"); 3985 if (HasAVX512IFMA) 3986 Builder.defineMacro("__AVX512IFMA__"); 3987 3988 if (HasSHA) 3989 Builder.defineMacro("__SHA__"); 3990 3991 if (HasFXSR) 3992 Builder.defineMacro("__FXSR__"); 3993 if (HasXSAVE) 3994 Builder.defineMacro("__XSAVE__"); 3995 if (HasXSAVEOPT) 3996 Builder.defineMacro("__XSAVEOPT__"); 3997 if (HasXSAVEC) 3998 Builder.defineMacro("__XSAVEC__"); 3999 if (HasXSAVES) 4000 Builder.defineMacro("__XSAVES__"); 4001 if (HasPKU) 4002 Builder.defineMacro("__PKU__"); 4003 if (HasCX16) 4004 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 4005 if (HasCLFLUSHOPT) 4006 Builder.defineMacro("__CLFLUSHOPT__"); 4007 if (HasCLWB) 4008 Builder.defineMacro("__CLWB__"); 4009 if (HasMPX) 4010 Builder.defineMacro("__MPX__"); 4011 if (HasSGX) 4012 Builder.defineMacro("__SGX__"); 4013 if (HasPREFETCHWT1) 4014 Builder.defineMacro("__PREFETCHWT1__"); 4015 if (HasCLZERO) 4016 Builder.defineMacro("__CLZERO__"); 4017 4018 // Each case falls through to the previous one here. 4019 switch (SSELevel) { 4020 case AVX512F: 4021 Builder.defineMacro("__AVX512F__"); 4022 case AVX2: 4023 Builder.defineMacro("__AVX2__"); 4024 case AVX: 4025 Builder.defineMacro("__AVX__"); 4026 case SSE42: 4027 Builder.defineMacro("__SSE4_2__"); 4028 case SSE41: 4029 Builder.defineMacro("__SSE4_1__"); 4030 case SSSE3: 4031 Builder.defineMacro("__SSSE3__"); 4032 case SSE3: 4033 Builder.defineMacro("__SSE3__"); 4034 case SSE2: 4035 Builder.defineMacro("__SSE2__"); 4036 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 4037 case SSE1: 4038 Builder.defineMacro("__SSE__"); 4039 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 4040 case NoSSE: 4041 break; 4042 } 4043 4044 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 4045 switch (SSELevel) { 4046 case AVX512F: 4047 case AVX2: 4048 case AVX: 4049 case SSE42: 4050 case SSE41: 4051 case SSSE3: 4052 case SSE3: 4053 case SSE2: 4054 Builder.defineMacro("_M_IX86_FP", Twine(2)); 4055 break; 4056 case SSE1: 4057 Builder.defineMacro("_M_IX86_FP", Twine(1)); 4058 break; 4059 default: 4060 Builder.defineMacro("_M_IX86_FP", Twine(0)); 4061 } 4062 } 4063 4064 // Each case falls through to the previous one here. 4065 switch (MMX3DNowLevel) { 4066 case AMD3DNowAthlon: 4067 Builder.defineMacro("__3dNOW_A__"); 4068 case AMD3DNow: 4069 Builder.defineMacro("__3dNOW__"); 4070 case MMX: 4071 Builder.defineMacro("__MMX__"); 4072 case NoMMX3DNow: 4073 break; 4074 } 4075 4076 if (CPU >= CK_i486) { 4077 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4078 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4079 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4080 } 4081 if (CPU >= CK_i586) 4082 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4083 } 4084 4085 bool X86TargetInfo::hasFeature(StringRef Feature) const { 4086 return llvm::StringSwitch<bool>(Feature) 4087 .Case("aes", HasAES) 4088 .Case("avx", SSELevel >= AVX) 4089 .Case("avx2", SSELevel >= AVX2) 4090 .Case("avx512f", SSELevel >= AVX512F) 4091 .Case("avx512cd", HasAVX512CD) 4092 .Case("avx512er", HasAVX512ER) 4093 .Case("avx512pf", HasAVX512PF) 4094 .Case("avx512dq", HasAVX512DQ) 4095 .Case("avx512bw", HasAVX512BW) 4096 .Case("avx512vl", HasAVX512VL) 4097 .Case("avx512vbmi", HasAVX512VBMI) 4098 .Case("avx512ifma", HasAVX512IFMA) 4099 .Case("bmi", HasBMI) 4100 .Case("bmi2", HasBMI2) 4101 .Case("clflushopt", HasCLFLUSHOPT) 4102 .Case("clwb", HasCLWB) 4103 .Case("clzero", HasCLZERO) 4104 .Case("cx16", HasCX16) 4105 .Case("f16c", HasF16C) 4106 .Case("fma", HasFMA) 4107 .Case("fma4", XOPLevel >= FMA4) 4108 .Case("fsgsbase", HasFSGSBASE) 4109 .Case("fxsr", HasFXSR) 4110 .Case("lzcnt", HasLZCNT) 4111 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4112 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4113 .Case("mmx", MMX3DNowLevel >= MMX) 4114 .Case("movbe", HasMOVBE) 4115 .Case("mpx", HasMPX) 4116 .Case("pclmul", HasPCLMUL) 4117 .Case("pku", HasPKU) 4118 .Case("popcnt", HasPOPCNT) 4119 .Case("prefetchwt1", HasPREFETCHWT1) 4120 .Case("prfchw", HasPRFCHW) 4121 .Case("rdrnd", HasRDRND) 4122 .Case("rdseed", HasRDSEED) 4123 .Case("rtm", HasRTM) 4124 .Case("sgx", HasSGX) 4125 .Case("sha", HasSHA) 4126 .Case("sse", SSELevel >= SSE1) 4127 .Case("sse2", SSELevel >= SSE2) 4128 .Case("sse3", SSELevel >= SSE3) 4129 .Case("ssse3", SSELevel >= SSSE3) 4130 .Case("sse4.1", SSELevel >= SSE41) 4131 .Case("sse4.2", SSELevel >= SSE42) 4132 .Case("sse4a", XOPLevel >= SSE4A) 4133 .Case("tbm", HasTBM) 4134 .Case("x86", true) 4135 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4136 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4137 .Case("xop", XOPLevel >= XOP) 4138 .Case("xsave", HasXSAVE) 4139 .Case("xsavec", HasXSAVEC) 4140 .Case("xsaves", HasXSAVES) 4141 .Case("xsaveopt", HasXSAVEOPT) 4142 .Default(false); 4143 } 4144 4145 // We can't use a generic validation scheme for the features accepted here 4146 // versus subtarget features accepted in the target attribute because the 4147 // bitfield structure that's initialized in the runtime only supports the 4148 // below currently rather than the full range of subtarget features. (See 4149 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4150 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4151 return llvm::StringSwitch<bool>(FeatureStr) 4152 .Case("cmov", true) 4153 .Case("mmx", true) 4154 .Case("popcnt", true) 4155 .Case("sse", true) 4156 .Case("sse2", true) 4157 .Case("sse3", true) 4158 .Case("ssse3", true) 4159 .Case("sse4.1", true) 4160 .Case("sse4.2", true) 4161 .Case("avx", true) 4162 .Case("avx2", true) 4163 .Case("sse4a", true) 4164 .Case("fma4", true) 4165 .Case("xop", true) 4166 .Case("fma", true) 4167 .Case("avx512f", true) 4168 .Case("bmi", true) 4169 .Case("bmi2", true) 4170 .Case("aes", true) 4171 .Case("pclmul", true) 4172 .Case("avx512vl", true) 4173 .Case("avx512bw", true) 4174 .Case("avx512dq", true) 4175 .Case("avx512cd", true) 4176 .Case("avx512er", true) 4177 .Case("avx512pf", true) 4178 .Case("avx512vbmi", true) 4179 .Case("avx512ifma", true) 4180 .Default(false); 4181 } 4182 4183 bool 4184 X86TargetInfo::validateAsmConstraint(const char *&Name, 4185 TargetInfo::ConstraintInfo &Info) const { 4186 switch (*Name) { 4187 default: return false; 4188 // Constant constraints. 4189 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4190 // instructions. 4191 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4192 // x86_64 instructions. 4193 case 's': 4194 Info.setRequiresImmediate(); 4195 return true; 4196 case 'I': 4197 Info.setRequiresImmediate(0, 31); 4198 return true; 4199 case 'J': 4200 Info.setRequiresImmediate(0, 63); 4201 return true; 4202 case 'K': 4203 Info.setRequiresImmediate(-128, 127); 4204 return true; 4205 case 'L': 4206 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4207 return true; 4208 case 'M': 4209 Info.setRequiresImmediate(0, 3); 4210 return true; 4211 case 'N': 4212 Info.setRequiresImmediate(0, 255); 4213 return true; 4214 case 'O': 4215 Info.setRequiresImmediate(0, 127); 4216 return true; 4217 // Register constraints. 4218 case 'Y': // 'Y' is the first character for several 2-character constraints. 4219 // Shift the pointer to the second character of the constraint. 4220 Name++; 4221 switch (*Name) { 4222 default: 4223 return false; 4224 case '0': // First SSE register. 4225 case 't': // Any SSE register, when SSE2 is enabled. 4226 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4227 case 'm': // Any MMX register, when inter-unit moves enabled. 4228 case 'k': // AVX512 arch mask registers: k1-k7. 4229 Info.setAllowsRegister(); 4230 return true; 4231 } 4232 case 'f': // Any x87 floating point stack register. 4233 // Constraint 'f' cannot be used for output operands. 4234 if (Info.ConstraintStr[0] == '=') 4235 return false; 4236 Info.setAllowsRegister(); 4237 return true; 4238 case 'a': // eax. 4239 case 'b': // ebx. 4240 case 'c': // ecx. 4241 case 'd': // edx. 4242 case 'S': // esi. 4243 case 'D': // edi. 4244 case 'A': // edx:eax. 4245 case 't': // Top of floating point stack. 4246 case 'u': // Second from top of floating point stack. 4247 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4248 case 'y': // Any MMX register. 4249 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4250 case 'x': // Any SSE register. 4251 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4252 // for intermideate k reg operations). 4253 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4254 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4255 case 'l': // "Index" registers: any general register that can be used as an 4256 // index in a base+index memory access. 4257 Info.setAllowsRegister(); 4258 return true; 4259 // Floating point constant constraints. 4260 case 'C': // SSE floating point constant. 4261 case 'G': // x87 floating point constant. 4262 return true; 4263 } 4264 } 4265 4266 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4267 unsigned Size) const { 4268 // Strip off constraint modifiers. 4269 while (Constraint[0] == '=' || 4270 Constraint[0] == '+' || 4271 Constraint[0] == '&') 4272 Constraint = Constraint.substr(1); 4273 4274 return validateOperandSize(Constraint, Size); 4275 } 4276 4277 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4278 unsigned Size) const { 4279 return validateOperandSize(Constraint, Size); 4280 } 4281 4282 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4283 unsigned Size) const { 4284 switch (Constraint[0]) { 4285 default: break; 4286 case 'k': 4287 // Registers k0-k7 (AVX512) size limit is 64 bit. 4288 case 'y': 4289 return Size <= 64; 4290 case 'f': 4291 case 't': 4292 case 'u': 4293 return Size <= 128; 4294 case 'v': 4295 case 'x': 4296 if (SSELevel >= AVX512F) 4297 // 512-bit zmm registers can be used if target supports AVX512F. 4298 return Size <= 512U; 4299 else if (SSELevel >= AVX) 4300 // 256-bit ymm registers can be used if target supports AVX. 4301 return Size <= 256U; 4302 return Size <= 128U; 4303 case 'Y': 4304 // 'Y' is the first character for several 2-character constraints. 4305 switch (Constraint[1]) { 4306 default: break; 4307 case 'm': 4308 // 'Ym' is synonymous with 'y'. 4309 case 'k': 4310 return Size <= 64; 4311 case 'i': 4312 case 't': 4313 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4314 if (SSELevel >= AVX512F) 4315 return Size <= 512U; 4316 else if (SSELevel >= AVX) 4317 return Size <= 256U; 4318 return SSELevel >= SSE2 && Size <= 128U; 4319 } 4320 4321 } 4322 4323 return true; 4324 } 4325 4326 std::string 4327 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4328 switch (*Constraint) { 4329 case 'a': return std::string("{ax}"); 4330 case 'b': return std::string("{bx}"); 4331 case 'c': return std::string("{cx}"); 4332 case 'd': return std::string("{dx}"); 4333 case 'S': return std::string("{si}"); 4334 case 'D': return std::string("{di}"); 4335 case 'p': // address 4336 return std::string("im"); 4337 case 't': // top of floating point stack. 4338 return std::string("{st}"); 4339 case 'u': // second from top of floating point stack. 4340 return std::string("{st(1)}"); // second from top of floating point stack. 4341 case 'Y': 4342 switch (Constraint[1]) { 4343 default: 4344 // Break from inner switch and fall through (copy single char), 4345 // continue parsing after copying the current constraint into 4346 // the return string. 4347 break; 4348 case 'k': 4349 // "^" hints llvm that this is a 2 letter constraint. 4350 // "Constraint++" is used to promote the string iterator 4351 // to the next constraint. 4352 return std::string("^") + std::string(Constraint++, 2); 4353 } 4354 LLVM_FALLTHROUGH; 4355 default: 4356 return std::string(1, *Constraint); 4357 } 4358 } 4359 4360 // X86-32 generic target 4361 class X86_32TargetInfo : public X86TargetInfo { 4362 public: 4363 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4364 : X86TargetInfo(Triple, Opts) { 4365 DoubleAlign = LongLongAlign = 32; 4366 LongDoubleWidth = 96; 4367 LongDoubleAlign = 32; 4368 SuitableAlign = 128; 4369 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4370 SizeType = UnsignedInt; 4371 PtrDiffType = SignedInt; 4372 IntPtrType = SignedInt; 4373 RegParmMax = 3; 4374 4375 // Use fpret for all types. 4376 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4377 (1 << TargetInfo::Double) | 4378 (1 << TargetInfo::LongDouble)); 4379 4380 // x86-32 has atomics up to 8 bytes 4381 // FIXME: Check that we actually have cmpxchg8b before setting 4382 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4383 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4384 } 4385 BuiltinVaListKind getBuiltinVaListKind() const override { 4386 return TargetInfo::CharPtrBuiltinVaList; 4387 } 4388 4389 int getEHDataRegisterNumber(unsigned RegNo) const override { 4390 if (RegNo == 0) return 0; 4391 if (RegNo == 1) return 2; 4392 return -1; 4393 } 4394 bool validateOperandSize(StringRef Constraint, 4395 unsigned Size) const override { 4396 switch (Constraint[0]) { 4397 default: break; 4398 case 'R': 4399 case 'q': 4400 case 'Q': 4401 case 'a': 4402 case 'b': 4403 case 'c': 4404 case 'd': 4405 case 'S': 4406 case 'D': 4407 return Size <= 32; 4408 case 'A': 4409 return Size <= 64; 4410 } 4411 4412 return X86TargetInfo::validateOperandSize(Constraint, Size); 4413 } 4414 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4415 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4416 Builtin::FirstTSBuiltin + 1); 4417 } 4418 }; 4419 4420 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4421 public: 4422 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4423 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4424 4425 unsigned getFloatEvalMethod() const override { 4426 unsigned Major, Minor, Micro; 4427 getTriple().getOSVersion(Major, Minor, Micro); 4428 // New NetBSD uses the default rounding mode. 4429 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4430 return X86_32TargetInfo::getFloatEvalMethod(); 4431 // NetBSD before 6.99.26 defaults to "double" rounding. 4432 return 1; 4433 } 4434 }; 4435 4436 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4437 public: 4438 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4439 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4440 SizeType = UnsignedLong; 4441 IntPtrType = SignedLong; 4442 PtrDiffType = SignedLong; 4443 } 4444 }; 4445 4446 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4447 public: 4448 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4449 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4450 SizeType = UnsignedLong; 4451 IntPtrType = SignedLong; 4452 PtrDiffType = SignedLong; 4453 } 4454 }; 4455 4456 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4457 public: 4458 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4459 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4460 LongDoubleWidth = 128; 4461 LongDoubleAlign = 128; 4462 SuitableAlign = 128; 4463 MaxVectorAlign = 256; 4464 // The watchOS simulator uses the builtin bool type for Objective-C. 4465 llvm::Triple T = llvm::Triple(Triple); 4466 if (T.isWatchOS()) 4467 UseSignedCharForObjCBool = false; 4468 SizeType = UnsignedLong; 4469 IntPtrType = SignedLong; 4470 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4471 HasAlignMac68kSupport = true; 4472 } 4473 4474 bool handleTargetFeatures(std::vector<std::string> &Features, 4475 DiagnosticsEngine &Diags) override { 4476 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4477 Diags)) 4478 return false; 4479 // We now know the features we have: we can decide how to align vectors. 4480 MaxVectorAlign = 4481 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4482 return true; 4483 } 4484 }; 4485 4486 // x86-32 Windows target 4487 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4488 public: 4489 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4490 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4491 WCharType = UnsignedShort; 4492 DoubleAlign = LongLongAlign = 64; 4493 bool IsWinCOFF = 4494 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4495 resetDataLayout(IsWinCOFF 4496 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4497 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4498 } 4499 void getTargetDefines(const LangOptions &Opts, 4500 MacroBuilder &Builder) const override { 4501 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4502 } 4503 }; 4504 4505 // x86-32 Windows Visual Studio target 4506 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4507 public: 4508 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4509 const TargetOptions &Opts) 4510 : WindowsX86_32TargetInfo(Triple, Opts) { 4511 LongDoubleWidth = LongDoubleAlign = 64; 4512 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4513 } 4514 void getTargetDefines(const LangOptions &Opts, 4515 MacroBuilder &Builder) const override { 4516 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4517 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4518 // The value of the following reflects processor type. 4519 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4520 // We lost the original triple, so we use the default. 4521 Builder.defineMacro("_M_IX86", "600"); 4522 } 4523 }; 4524 4525 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4526 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4527 // supports __declspec natively under -fms-extensions, but we define a no-op 4528 // __declspec macro anyway for pre-processor compatibility. 4529 if (Opts.MicrosoftExt) 4530 Builder.defineMacro("__declspec", "__declspec"); 4531 else 4532 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4533 4534 if (!Opts.MicrosoftExt) { 4535 // Provide macros for all the calling convention keywords. Provide both 4536 // single and double underscore prefixed variants. These are available on 4537 // x64 as well as x86, even though they have no effect. 4538 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4539 for (const char *CC : CCs) { 4540 std::string GCCSpelling = "__attribute__((__"; 4541 GCCSpelling += CC; 4542 GCCSpelling += "__))"; 4543 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4544 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4545 } 4546 } 4547 } 4548 4549 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4550 Builder.defineMacro("__MSVCRT__"); 4551 Builder.defineMacro("__MINGW32__"); 4552 addCygMingDefines(Opts, Builder); 4553 } 4554 4555 // x86-32 MinGW target 4556 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4557 public: 4558 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4559 : WindowsX86_32TargetInfo(Triple, Opts) {} 4560 void getTargetDefines(const LangOptions &Opts, 4561 MacroBuilder &Builder) const override { 4562 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4563 DefineStd(Builder, "WIN32", Opts); 4564 DefineStd(Builder, "WINNT", Opts); 4565 Builder.defineMacro("_X86_"); 4566 addMinGWDefines(Opts, Builder); 4567 } 4568 }; 4569 4570 // x86-32 Cygwin target 4571 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4572 public: 4573 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4574 : X86_32TargetInfo(Triple, Opts) { 4575 WCharType = UnsignedShort; 4576 DoubleAlign = LongLongAlign = 64; 4577 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4578 } 4579 void getTargetDefines(const LangOptions &Opts, 4580 MacroBuilder &Builder) const override { 4581 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4582 Builder.defineMacro("_X86_"); 4583 Builder.defineMacro("__CYGWIN__"); 4584 Builder.defineMacro("__CYGWIN32__"); 4585 addCygMingDefines(Opts, Builder); 4586 DefineStd(Builder, "unix", Opts); 4587 if (Opts.CPlusPlus) 4588 Builder.defineMacro("_GNU_SOURCE"); 4589 } 4590 }; 4591 4592 // x86-32 Haiku target 4593 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4594 public: 4595 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4596 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4597 } 4598 void getTargetDefines(const LangOptions &Opts, 4599 MacroBuilder &Builder) const override { 4600 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4601 Builder.defineMacro("__INTEL__"); 4602 } 4603 }; 4604 4605 // X86-32 MCU target 4606 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4607 public: 4608 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4609 : X86_32TargetInfo(Triple, Opts) { 4610 LongDoubleWidth = 64; 4611 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4612 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4613 WIntType = UnsignedInt; 4614 } 4615 4616 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4617 // On MCU we support only C calling convention. 4618 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4619 } 4620 4621 void getTargetDefines(const LangOptions &Opts, 4622 MacroBuilder &Builder) const override { 4623 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4624 Builder.defineMacro("__iamcu"); 4625 Builder.defineMacro("__iamcu__"); 4626 } 4627 4628 bool allowsLargerPreferedTypeAlignment() const override { 4629 return false; 4630 } 4631 }; 4632 4633 // RTEMS Target 4634 template<typename Target> 4635 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4636 protected: 4637 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4638 MacroBuilder &Builder) const override { 4639 // RTEMS defines; list based off of gcc output 4640 4641 Builder.defineMacro("__rtems__"); 4642 Builder.defineMacro("__ELF__"); 4643 } 4644 4645 public: 4646 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4647 : OSTargetInfo<Target>(Triple, Opts) { 4648 switch (Triple.getArch()) { 4649 default: 4650 case llvm::Triple::x86: 4651 // this->MCountName = ".mcount"; 4652 break; 4653 case llvm::Triple::mips: 4654 case llvm::Triple::mipsel: 4655 case llvm::Triple::ppc: 4656 case llvm::Triple::ppc64: 4657 case llvm::Triple::ppc64le: 4658 // this->MCountName = "_mcount"; 4659 break; 4660 case llvm::Triple::arm: 4661 // this->MCountName = "__mcount"; 4662 break; 4663 } 4664 } 4665 }; 4666 4667 // x86-32 RTEMS target 4668 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4669 public: 4670 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4671 : X86_32TargetInfo(Triple, Opts) { 4672 SizeType = UnsignedLong; 4673 IntPtrType = SignedLong; 4674 PtrDiffType = SignedLong; 4675 } 4676 void getTargetDefines(const LangOptions &Opts, 4677 MacroBuilder &Builder) const override { 4678 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4679 Builder.defineMacro("__INTEL__"); 4680 Builder.defineMacro("__rtems__"); 4681 } 4682 }; 4683 4684 // x86-64 generic target 4685 class X86_64TargetInfo : public X86TargetInfo { 4686 public: 4687 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4688 : X86TargetInfo(Triple, Opts) { 4689 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4690 bool IsWinCOFF = 4691 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4692 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4693 LongDoubleWidth = 128; 4694 LongDoubleAlign = 128; 4695 LargeArrayMinWidth = 128; 4696 LargeArrayAlign = 128; 4697 SuitableAlign = 128; 4698 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4699 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4700 IntPtrType = IsX32 ? SignedInt : SignedLong; 4701 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4702 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4703 RegParmMax = 6; 4704 4705 // Pointers are 32-bit in x32. 4706 resetDataLayout(IsX32 4707 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4708 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4709 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4710 4711 // Use fpret only for long double. 4712 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4713 4714 // Use fp2ret for _Complex long double. 4715 ComplexLongDoubleUsesFP2Ret = true; 4716 4717 // Make __builtin_ms_va_list available. 4718 HasBuiltinMSVaList = true; 4719 4720 // x86-64 has atomics up to 16 bytes. 4721 MaxAtomicPromoteWidth = 128; 4722 MaxAtomicInlineWidth = 128; 4723 } 4724 BuiltinVaListKind getBuiltinVaListKind() const override { 4725 return TargetInfo::X86_64ABIBuiltinVaList; 4726 } 4727 4728 int getEHDataRegisterNumber(unsigned RegNo) const override { 4729 if (RegNo == 0) return 0; 4730 if (RegNo == 1) return 1; 4731 return -1; 4732 } 4733 4734 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4735 switch (CC) { 4736 case CC_C: 4737 case CC_Swift: 4738 case CC_X86VectorCall: 4739 case CC_IntelOclBicc: 4740 case CC_X86_64Win64: 4741 case CC_PreserveMost: 4742 case CC_PreserveAll: 4743 case CC_X86RegCall: 4744 return CCCR_OK; 4745 default: 4746 return CCCR_Warning; 4747 } 4748 } 4749 4750 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4751 return CC_C; 4752 } 4753 4754 // for x32 we need it here explicitly 4755 bool hasInt128Type() const override { return true; } 4756 unsigned getUnwindWordWidth() const override { return 64; } 4757 unsigned getRegisterWidth() const override { return 64; } 4758 4759 bool validateGlobalRegisterVariable(StringRef RegName, 4760 unsigned RegSize, 4761 bool &HasSizeMismatch) const override { 4762 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4763 // handle. 4764 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4765 // Check that the register size is 64-bit. 4766 HasSizeMismatch = RegSize != 64; 4767 return true; 4768 } 4769 4770 // Check if the register is a 32-bit register the backend can handle. 4771 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4772 HasSizeMismatch); 4773 } 4774 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4775 return llvm::makeArrayRef(BuiltinInfoX86, 4776 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4777 } 4778 }; 4779 4780 // x86-64 Windows target 4781 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4782 public: 4783 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4784 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4785 WCharType = UnsignedShort; 4786 LongWidth = LongAlign = 32; 4787 DoubleAlign = LongLongAlign = 64; 4788 IntMaxType = SignedLongLong; 4789 Int64Type = SignedLongLong; 4790 SizeType = UnsignedLongLong; 4791 PtrDiffType = SignedLongLong; 4792 IntPtrType = SignedLongLong; 4793 } 4794 4795 void getTargetDefines(const LangOptions &Opts, 4796 MacroBuilder &Builder) const override { 4797 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4798 Builder.defineMacro("_WIN64"); 4799 } 4800 4801 BuiltinVaListKind getBuiltinVaListKind() const override { 4802 return TargetInfo::CharPtrBuiltinVaList; 4803 } 4804 4805 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4806 switch (CC) { 4807 case CC_X86StdCall: 4808 case CC_X86ThisCall: 4809 case CC_X86FastCall: 4810 return CCCR_Ignore; 4811 case CC_C: 4812 case CC_X86VectorCall: 4813 case CC_IntelOclBicc: 4814 case CC_X86_64SysV: 4815 case CC_Swift: 4816 case CC_X86RegCall: 4817 return CCCR_OK; 4818 default: 4819 return CCCR_Warning; 4820 } 4821 } 4822 }; 4823 4824 // x86-64 Windows Visual Studio target 4825 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4826 public: 4827 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4828 const TargetOptions &Opts) 4829 : WindowsX86_64TargetInfo(Triple, Opts) { 4830 LongDoubleWidth = LongDoubleAlign = 64; 4831 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4832 } 4833 void getTargetDefines(const LangOptions &Opts, 4834 MacroBuilder &Builder) const override { 4835 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4836 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4837 Builder.defineMacro("_M_X64", "100"); 4838 Builder.defineMacro("_M_AMD64", "100"); 4839 } 4840 }; 4841 4842 // x86-64 MinGW target 4843 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4844 public: 4845 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4846 : WindowsX86_64TargetInfo(Triple, Opts) { 4847 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4848 // with x86 FP ops. Weird. 4849 LongDoubleWidth = LongDoubleAlign = 128; 4850 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 4851 } 4852 4853 void getTargetDefines(const LangOptions &Opts, 4854 MacroBuilder &Builder) const override { 4855 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4856 DefineStd(Builder, "WIN64", Opts); 4857 Builder.defineMacro("__MINGW64__"); 4858 addMinGWDefines(Opts, Builder); 4859 4860 // GCC defines this macro when it is using __gxx_personality_seh0. 4861 if (!Opts.SjLjExceptions) 4862 Builder.defineMacro("__SEH__"); 4863 } 4864 }; 4865 4866 // x86-64 Cygwin target 4867 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4868 public: 4869 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4870 : X86_64TargetInfo(Triple, Opts) { 4871 TLSSupported = false; 4872 WCharType = UnsignedShort; 4873 } 4874 void getTargetDefines(const LangOptions &Opts, 4875 MacroBuilder &Builder) const override { 4876 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4877 Builder.defineMacro("__x86_64__"); 4878 Builder.defineMacro("__CYGWIN__"); 4879 Builder.defineMacro("__CYGWIN64__"); 4880 addCygMingDefines(Opts, Builder); 4881 DefineStd(Builder, "unix", Opts); 4882 if (Opts.CPlusPlus) 4883 Builder.defineMacro("_GNU_SOURCE"); 4884 4885 // GCC defines this macro when it is using __gxx_personality_seh0. 4886 if (!Opts.SjLjExceptions) 4887 Builder.defineMacro("__SEH__"); 4888 } 4889 }; 4890 4891 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4892 public: 4893 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4894 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4895 Int64Type = SignedLongLong; 4896 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4897 llvm::Triple T = llvm::Triple(Triple); 4898 if (T.isiOS()) 4899 UseSignedCharForObjCBool = false; 4900 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4901 } 4902 4903 bool handleTargetFeatures(std::vector<std::string> &Features, 4904 DiagnosticsEngine &Diags) override { 4905 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4906 Diags)) 4907 return false; 4908 // We now know the features we have: we can decide how to align vectors. 4909 MaxVectorAlign = 4910 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4911 return true; 4912 } 4913 }; 4914 4915 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4916 public: 4917 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4918 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4919 IntMaxType = SignedLongLong; 4920 Int64Type = SignedLongLong; 4921 } 4922 }; 4923 4924 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4925 public: 4926 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4927 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4928 IntMaxType = SignedLongLong; 4929 Int64Type = SignedLongLong; 4930 } 4931 }; 4932 4933 class ARMTargetInfo : public TargetInfo { 4934 // Possible FPU choices. 4935 enum FPUMode { 4936 VFP2FPU = (1 << 0), 4937 VFP3FPU = (1 << 1), 4938 VFP4FPU = (1 << 2), 4939 NeonFPU = (1 << 3), 4940 FPARMV8 = (1 << 4) 4941 }; 4942 4943 // Possible HWDiv features. 4944 enum HWDivMode { 4945 HWDivThumb = (1 << 0), 4946 HWDivARM = (1 << 1) 4947 }; 4948 4949 static bool FPUModeIsVFP(FPUMode Mode) { 4950 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4951 } 4952 4953 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4954 static const char * const GCCRegNames[]; 4955 4956 std::string ABI, CPU; 4957 4958 StringRef CPUProfile; 4959 StringRef CPUAttr; 4960 4961 enum { 4962 FP_Default, 4963 FP_VFP, 4964 FP_Neon 4965 } FPMath; 4966 4967 unsigned ArchISA; 4968 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4969 unsigned ArchProfile; 4970 unsigned ArchVersion; 4971 4972 unsigned FPU : 5; 4973 4974 unsigned IsAAPCS : 1; 4975 unsigned HWDiv : 2; 4976 4977 // Initialized via features. 4978 unsigned SoftFloat : 1; 4979 unsigned SoftFloatABI : 1; 4980 4981 unsigned CRC : 1; 4982 unsigned Crypto : 1; 4983 unsigned DSP : 1; 4984 unsigned Unaligned : 1; 4985 4986 enum { 4987 LDREX_B = (1 << 0), /// byte (8-bit) 4988 LDREX_H = (1 << 1), /// half (16-bit) 4989 LDREX_W = (1 << 2), /// word (32-bit) 4990 LDREX_D = (1 << 3), /// double (64-bit) 4991 }; 4992 4993 uint32_t LDREX; 4994 4995 // ACLE 6.5.1 Hardware floating point 4996 enum { 4997 HW_FP_HP = (1 << 1), /// half (16-bit) 4998 HW_FP_SP = (1 << 2), /// single (32-bit) 4999 HW_FP_DP = (1 << 3), /// double (64-bit) 5000 }; 5001 uint32_t HW_FP; 5002 5003 static const Builtin::Info BuiltinInfo[]; 5004 5005 void setABIAAPCS() { 5006 IsAAPCS = true; 5007 5008 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5009 const llvm::Triple &T = getTriple(); 5010 5011 // size_t is unsigned long on MachO-derived environments, NetBSD, 5012 // OpenBSD and Bitrig. 5013 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 5014 T.getOS() == llvm::Triple::OpenBSD || 5015 T.getOS() == llvm::Triple::Bitrig) 5016 SizeType = UnsignedLong; 5017 else 5018 SizeType = UnsignedInt; 5019 5020 switch (T.getOS()) { 5021 case llvm::Triple::NetBSD: 5022 case llvm::Triple::OpenBSD: 5023 WCharType = SignedInt; 5024 break; 5025 case llvm::Triple::Win32: 5026 WCharType = UnsignedShort; 5027 break; 5028 case llvm::Triple::Linux: 5029 default: 5030 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 5031 WCharType = UnsignedInt; 5032 break; 5033 } 5034 5035 UseBitFieldTypeAlignment = true; 5036 5037 ZeroLengthBitfieldBoundary = 0; 5038 5039 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 5040 // so set preferred for small types to 32. 5041 if (T.isOSBinFormatMachO()) { 5042 resetDataLayout(BigEndian 5043 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5044 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5045 } else if (T.isOSWindows()) { 5046 assert(!BigEndian && "Windows on ARM does not support big endian"); 5047 resetDataLayout("e" 5048 "-m:w" 5049 "-p:32:32" 5050 "-i64:64" 5051 "-v128:64:128" 5052 "-a:0:32" 5053 "-n32" 5054 "-S64"); 5055 } else if (T.isOSNaCl()) { 5056 assert(!BigEndian && "NaCl on ARM does not support big endian"); 5057 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 5058 } else { 5059 resetDataLayout(BigEndian 5060 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5061 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5062 } 5063 5064 // FIXME: Enumerated types are variable width in straight AAPCS. 5065 } 5066 5067 void setABIAPCS(bool IsAAPCS16) { 5068 const llvm::Triple &T = getTriple(); 5069 5070 IsAAPCS = false; 5071 5072 if (IsAAPCS16) 5073 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5074 else 5075 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 5076 5077 // size_t is unsigned int on FreeBSD. 5078 if (T.getOS() == llvm::Triple::FreeBSD) 5079 SizeType = UnsignedInt; 5080 else 5081 SizeType = UnsignedLong; 5082 5083 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 5084 WCharType = SignedInt; 5085 5086 // Do not respect the alignment of bit-field types when laying out 5087 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 5088 UseBitFieldTypeAlignment = false; 5089 5090 /// gcc forces the alignment to 4 bytes, regardless of the type of the 5091 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 5092 /// gcc. 5093 ZeroLengthBitfieldBoundary = 32; 5094 5095 if (T.isOSBinFormatMachO() && IsAAPCS16) { 5096 assert(!BigEndian && "AAPCS16 does not support big-endian"); 5097 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 5098 } else if (T.isOSBinFormatMachO()) 5099 resetDataLayout( 5100 BigEndian 5101 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5102 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5103 else 5104 resetDataLayout( 5105 BigEndian 5106 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5107 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5108 5109 // FIXME: Override "preferred align" for double and long long. 5110 } 5111 5112 void setArchInfo() { 5113 StringRef ArchName = getTriple().getArchName(); 5114 5115 ArchISA = llvm::ARM::parseArchISA(ArchName); 5116 CPU = llvm::ARM::getDefaultCPU(ArchName); 5117 unsigned AK = llvm::ARM::parseArch(ArchName); 5118 if (AK != llvm::ARM::AK_INVALID) 5119 ArchKind = AK; 5120 setArchInfo(ArchKind); 5121 } 5122 5123 void setArchInfo(unsigned Kind) { 5124 StringRef SubArch; 5125 5126 // cache TargetParser info 5127 ArchKind = Kind; 5128 SubArch = llvm::ARM::getSubArch(ArchKind); 5129 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5130 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5131 5132 // cache CPU related strings 5133 CPUAttr = getCPUAttr(); 5134 CPUProfile = getCPUProfile(); 5135 } 5136 5137 void setAtomic() { 5138 // when triple does not specify a sub arch, 5139 // then we are not using inline atomics 5140 bool ShouldUseInlineAtomic = 5141 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5142 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5143 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5144 if (ArchProfile == llvm::ARM::PK_M) { 5145 MaxAtomicPromoteWidth = 32; 5146 if (ShouldUseInlineAtomic) 5147 MaxAtomicInlineWidth = 32; 5148 } 5149 else { 5150 MaxAtomicPromoteWidth = 64; 5151 if (ShouldUseInlineAtomic) 5152 MaxAtomicInlineWidth = 64; 5153 } 5154 } 5155 5156 bool isThumb() const { 5157 return (ArchISA == llvm::ARM::IK_THUMB); 5158 } 5159 5160 bool supportsThumb() const { 5161 return CPUAttr.count('T') || ArchVersion >= 6; 5162 } 5163 5164 bool supportsThumb2() const { 5165 return CPUAttr.equals("6T2") || 5166 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5167 } 5168 5169 StringRef getCPUAttr() const { 5170 // For most sub-arches, the build attribute CPU name is enough. 5171 // For Cortex variants, it's slightly different. 5172 switch(ArchKind) { 5173 default: 5174 return llvm::ARM::getCPUAttr(ArchKind); 5175 case llvm::ARM::AK_ARMV6M: 5176 return "6M"; 5177 case llvm::ARM::AK_ARMV7S: 5178 return "7S"; 5179 case llvm::ARM::AK_ARMV7A: 5180 return "7A"; 5181 case llvm::ARM::AK_ARMV7R: 5182 return "7R"; 5183 case llvm::ARM::AK_ARMV7M: 5184 return "7M"; 5185 case llvm::ARM::AK_ARMV7EM: 5186 return "7EM"; 5187 case llvm::ARM::AK_ARMV7VE: 5188 return "7VE"; 5189 case llvm::ARM::AK_ARMV8A: 5190 return "8A"; 5191 case llvm::ARM::AK_ARMV8_1A: 5192 return "8_1A"; 5193 case llvm::ARM::AK_ARMV8_2A: 5194 return "8_2A"; 5195 case llvm::ARM::AK_ARMV8MBaseline: 5196 return "8M_BASE"; 5197 case llvm::ARM::AK_ARMV8MMainline: 5198 return "8M_MAIN"; 5199 case llvm::ARM::AK_ARMV8R: 5200 return "8R"; 5201 } 5202 } 5203 5204 StringRef getCPUProfile() const { 5205 switch(ArchProfile) { 5206 case llvm::ARM::PK_A: 5207 return "A"; 5208 case llvm::ARM::PK_R: 5209 return "R"; 5210 case llvm::ARM::PK_M: 5211 return "M"; 5212 default: 5213 return ""; 5214 } 5215 } 5216 5217 public: 5218 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5219 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5220 HW_FP(0) { 5221 5222 switch (getTriple().getOS()) { 5223 case llvm::Triple::NetBSD: 5224 case llvm::Triple::OpenBSD: 5225 PtrDiffType = SignedLong; 5226 break; 5227 default: 5228 PtrDiffType = SignedInt; 5229 break; 5230 } 5231 5232 // Cache arch related info. 5233 setArchInfo(); 5234 5235 // {} in inline assembly are neon specifiers, not assembly variant 5236 // specifiers. 5237 NoAsmVariants = true; 5238 5239 // FIXME: This duplicates code from the driver that sets the -target-abi 5240 // option - this code is used if -target-abi isn't passed and should 5241 // be unified in some way. 5242 if (Triple.isOSBinFormatMachO()) { 5243 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5244 // the frontend matches that. 5245 if (Triple.getEnvironment() == llvm::Triple::EABI || 5246 Triple.getOS() == llvm::Triple::UnknownOS || 5247 ArchProfile == llvm::ARM::PK_M) { 5248 setABI("aapcs"); 5249 } else if (Triple.isWatchABI()) { 5250 setABI("aapcs16"); 5251 } else { 5252 setABI("apcs-gnu"); 5253 } 5254 } else if (Triple.isOSWindows()) { 5255 // FIXME: this is invalid for WindowsCE 5256 setABI("aapcs"); 5257 } else { 5258 // Select the default based on the platform. 5259 switch (Triple.getEnvironment()) { 5260 case llvm::Triple::Android: 5261 case llvm::Triple::GNUEABI: 5262 case llvm::Triple::GNUEABIHF: 5263 case llvm::Triple::MuslEABI: 5264 case llvm::Triple::MuslEABIHF: 5265 setABI("aapcs-linux"); 5266 break; 5267 case llvm::Triple::EABIHF: 5268 case llvm::Triple::EABI: 5269 setABI("aapcs"); 5270 break; 5271 case llvm::Triple::GNU: 5272 setABI("apcs-gnu"); 5273 break; 5274 default: 5275 if (Triple.getOS() == llvm::Triple::NetBSD) 5276 setABI("apcs-gnu"); 5277 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5278 setABI("aapcs-linux"); 5279 else 5280 setABI("aapcs"); 5281 break; 5282 } 5283 } 5284 5285 // ARM targets default to using the ARM C++ ABI. 5286 TheCXXABI.set(TargetCXXABI::GenericARM); 5287 5288 // ARM has atomics up to 8 bytes 5289 setAtomic(); 5290 5291 // Do force alignment of members that follow zero length bitfields. If 5292 // the alignment of the zero-length bitfield is greater than the member 5293 // that follows it, `bar', `bar' will be aligned as the type of the 5294 // zero length bitfield. 5295 UseZeroLengthBitfieldAlignment = true; 5296 5297 if (Triple.getOS() == llvm::Triple::Linux || 5298 Triple.getOS() == llvm::Triple::UnknownOS) 5299 this->MCountName = 5300 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5301 } 5302 5303 StringRef getABI() const override { return ABI; } 5304 5305 bool setABI(const std::string &Name) override { 5306 ABI = Name; 5307 5308 // The defaults (above) are for AAPCS, check if we need to change them. 5309 // 5310 // FIXME: We need support for -meabi... we could just mangle it into the 5311 // name. 5312 if (Name == "apcs-gnu" || Name == "aapcs16") { 5313 setABIAPCS(Name == "aapcs16"); 5314 return true; 5315 } 5316 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5317 setABIAAPCS(); 5318 return true; 5319 } 5320 return false; 5321 } 5322 5323 // FIXME: This should be based on Arch attributes, not CPU names. 5324 bool 5325 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5326 StringRef CPU, 5327 const std::vector<std::string> &FeaturesVec) const override { 5328 5329 std::vector<StringRef> TargetFeatures; 5330 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5331 5332 // get default FPU features 5333 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5334 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5335 5336 // get default Extension features 5337 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5338 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5339 5340 for (auto Feature : TargetFeatures) 5341 if (Feature[0] == '+') 5342 Features[Feature.drop_front(1)] = true; 5343 5344 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5345 } 5346 5347 bool handleTargetFeatures(std::vector<std::string> &Features, 5348 DiagnosticsEngine &Diags) override { 5349 FPU = 0; 5350 CRC = 0; 5351 Crypto = 0; 5352 DSP = 0; 5353 Unaligned = 1; 5354 SoftFloat = SoftFloatABI = false; 5355 HWDiv = 0; 5356 5357 // This does not diagnose illegal cases like having both 5358 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5359 uint32_t HW_FP_remove = 0; 5360 for (const auto &Feature : Features) { 5361 if (Feature == "+soft-float") { 5362 SoftFloat = true; 5363 } else if (Feature == "+soft-float-abi") { 5364 SoftFloatABI = true; 5365 } else if (Feature == "+vfp2") { 5366 FPU |= VFP2FPU; 5367 HW_FP |= HW_FP_SP | HW_FP_DP; 5368 } else if (Feature == "+vfp3") { 5369 FPU |= VFP3FPU; 5370 HW_FP |= HW_FP_SP | HW_FP_DP; 5371 } else if (Feature == "+vfp4") { 5372 FPU |= VFP4FPU; 5373 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5374 } else if (Feature == "+fp-armv8") { 5375 FPU |= FPARMV8; 5376 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5377 } else if (Feature == "+neon") { 5378 FPU |= NeonFPU; 5379 HW_FP |= HW_FP_SP | HW_FP_DP; 5380 } else if (Feature == "+hwdiv") { 5381 HWDiv |= HWDivThumb; 5382 } else if (Feature == "+hwdiv-arm") { 5383 HWDiv |= HWDivARM; 5384 } else if (Feature == "+crc") { 5385 CRC = 1; 5386 } else if (Feature == "+crypto") { 5387 Crypto = 1; 5388 } else if (Feature == "+dsp") { 5389 DSP = 1; 5390 } else if (Feature == "+fp-only-sp") { 5391 HW_FP_remove |= HW_FP_DP; 5392 } else if (Feature == "+strict-align") { 5393 Unaligned = 0; 5394 } else if (Feature == "+fp16") { 5395 HW_FP |= HW_FP_HP; 5396 } 5397 } 5398 HW_FP &= ~HW_FP_remove; 5399 5400 switch (ArchVersion) { 5401 case 6: 5402 if (ArchProfile == llvm::ARM::PK_M) 5403 LDREX = 0; 5404 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5405 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5406 else 5407 LDREX = LDREX_W; 5408 break; 5409 case 7: 5410 if (ArchProfile == llvm::ARM::PK_M) 5411 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5412 else 5413 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5414 break; 5415 case 8: 5416 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5417 } 5418 5419 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5420 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5421 return false; 5422 } 5423 5424 if (FPMath == FP_Neon) 5425 Features.push_back("+neonfp"); 5426 else if (FPMath == FP_VFP) 5427 Features.push_back("-neonfp"); 5428 5429 // Remove front-end specific options which the backend handles differently. 5430 auto Feature = 5431 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5432 if (Feature != Features.end()) 5433 Features.erase(Feature); 5434 5435 return true; 5436 } 5437 5438 bool hasFeature(StringRef Feature) const override { 5439 return llvm::StringSwitch<bool>(Feature) 5440 .Case("arm", true) 5441 .Case("aarch32", true) 5442 .Case("softfloat", SoftFloat) 5443 .Case("thumb", isThumb()) 5444 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5445 .Case("hwdiv", HWDiv & HWDivThumb) 5446 .Case("hwdiv-arm", HWDiv & HWDivARM) 5447 .Default(false); 5448 } 5449 5450 bool setCPU(const std::string &Name) override { 5451 if (Name != "generic") 5452 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5453 5454 if (ArchKind == llvm::ARM::AK_INVALID) 5455 return false; 5456 setAtomic(); 5457 CPU = Name; 5458 return true; 5459 } 5460 5461 bool setFPMath(StringRef Name) override; 5462 5463 void getTargetDefines(const LangOptions &Opts, 5464 MacroBuilder &Builder) const override { 5465 // Target identification. 5466 Builder.defineMacro("__arm"); 5467 Builder.defineMacro("__arm__"); 5468 // For bare-metal none-eabi. 5469 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5470 getTriple().getEnvironment() == llvm::Triple::EABI) 5471 Builder.defineMacro("__ELF__"); 5472 5473 // Target properties. 5474 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5475 5476 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5477 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5478 if (getTriple().isWatchABI()) 5479 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5480 5481 if (!CPUAttr.empty()) 5482 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5483 5484 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5485 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5486 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5487 5488 if (ArchVersion >= 8) { 5489 // ACLE 6.5.7 Crypto Extension 5490 if (Crypto) 5491 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5492 // ACLE 6.5.8 CRC32 Extension 5493 if (CRC) 5494 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5495 // ACLE 6.5.10 Numeric Maximum and Minimum 5496 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5497 // ACLE 6.5.9 Directed Rounding 5498 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5499 } 5500 5501 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5502 // is not defined for the M-profile. 5503 // NOTE that the default profile is assumed to be 'A' 5504 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5505 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5506 5507 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5508 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5509 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5510 // v7 and v8 architectures excluding v8-M Baseline. 5511 if (supportsThumb2()) 5512 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5513 else if (supportsThumb()) 5514 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5515 5516 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5517 // instruction set such as ARM or Thumb. 5518 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5519 5520 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5521 5522 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5523 if (!CPUProfile.empty()) 5524 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5525 5526 // ACLE 6.4.3 Unaligned access supported in hardware 5527 if (Unaligned) 5528 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5529 5530 // ACLE 6.4.4 LDREX/STREX 5531 if (LDREX) 5532 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5533 5534 // ACLE 6.4.5 CLZ 5535 if (ArchVersion == 5 || 5536 (ArchVersion == 6 && CPUProfile != "M") || 5537 ArchVersion > 6) 5538 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5539 5540 // ACLE 6.5.1 Hardware Floating Point 5541 if (HW_FP) 5542 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5543 5544 // ACLE predefines. 5545 Builder.defineMacro("__ARM_ACLE", "200"); 5546 5547 // FP16 support (we currently only support IEEE format). 5548 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5549 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5550 5551 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5552 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5553 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5554 5555 // Subtarget options. 5556 5557 // FIXME: It's more complicated than this and we don't really support 5558 // interworking. 5559 // Windows on ARM does not "support" interworking 5560 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5561 Builder.defineMacro("__THUMB_INTERWORK__"); 5562 5563 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5564 // Embedded targets on Darwin follow AAPCS, but not EABI. 5565 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5566 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5567 Builder.defineMacro("__ARM_EABI__"); 5568 Builder.defineMacro("__ARM_PCS", "1"); 5569 } 5570 5571 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5572 ABI == "aapcs16") 5573 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5574 5575 if (SoftFloat) 5576 Builder.defineMacro("__SOFTFP__"); 5577 5578 if (ArchKind == llvm::ARM::AK_XSCALE) 5579 Builder.defineMacro("__XSCALE__"); 5580 5581 if (isThumb()) { 5582 Builder.defineMacro("__THUMBEL__"); 5583 Builder.defineMacro("__thumb__"); 5584 if (supportsThumb2()) 5585 Builder.defineMacro("__thumb2__"); 5586 } 5587 5588 // ACLE 6.4.9 32-bit SIMD instructions 5589 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5590 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5591 5592 // ACLE 6.4.10 Hardware Integer Divide 5593 if (((HWDiv & HWDivThumb) && isThumb()) || 5594 ((HWDiv & HWDivARM) && !isThumb())) { 5595 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5596 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5597 } 5598 5599 // Note, this is always on in gcc, even though it doesn't make sense. 5600 Builder.defineMacro("__APCS_32__"); 5601 5602 if (FPUModeIsVFP((FPUMode) FPU)) { 5603 Builder.defineMacro("__VFP_FP__"); 5604 if (FPU & VFP2FPU) 5605 Builder.defineMacro("__ARM_VFPV2__"); 5606 if (FPU & VFP3FPU) 5607 Builder.defineMacro("__ARM_VFPV3__"); 5608 if (FPU & VFP4FPU) 5609 Builder.defineMacro("__ARM_VFPV4__"); 5610 if (FPU & FPARMV8) 5611 Builder.defineMacro("__ARM_FPV5__"); 5612 } 5613 5614 // This only gets set when Neon instructions are actually available, unlike 5615 // the VFP define, hence the soft float and arch check. This is subtly 5616 // different from gcc, we follow the intent which was that it should be set 5617 // when Neon instructions are actually available. 5618 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5619 Builder.defineMacro("__ARM_NEON", "1"); 5620 Builder.defineMacro("__ARM_NEON__"); 5621 // current AArch32 NEON implementations do not support double-precision 5622 // floating-point even when it is present in VFP. 5623 Builder.defineMacro("__ARM_NEON_FP", 5624 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5625 } 5626 5627 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5628 Opts.ShortWChar ? "2" : "4"); 5629 5630 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5631 Opts.ShortEnums ? "1" : "4"); 5632 5633 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5634 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5635 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5636 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5637 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5638 } 5639 5640 // ACLE 6.4.7 DSP instructions 5641 if (DSP) { 5642 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5643 } 5644 5645 // ACLE 6.4.8 Saturation instructions 5646 bool SAT = false; 5647 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5648 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5649 SAT = true; 5650 } 5651 5652 // ACLE 6.4.6 Q (saturation) flag 5653 if (DSP || SAT) 5654 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5655 5656 if (Opts.UnsafeFPMath) 5657 Builder.defineMacro("__ARM_FP_FAST", "1"); 5658 5659 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5660 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5661 } 5662 5663 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5664 return llvm::makeArrayRef(BuiltinInfo, 5665 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5666 } 5667 bool isCLZForZeroUndef() const override { return false; } 5668 BuiltinVaListKind getBuiltinVaListKind() const override { 5669 return IsAAPCS 5670 ? AAPCSABIBuiltinVaList 5671 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5672 : TargetInfo::VoidPtrBuiltinVaList); 5673 } 5674 ArrayRef<const char *> getGCCRegNames() const override; 5675 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5676 bool validateAsmConstraint(const char *&Name, 5677 TargetInfo::ConstraintInfo &Info) const override { 5678 switch (*Name) { 5679 default: break; 5680 case 'l': // r0-r7 5681 case 'h': // r8-r15 5682 case 't': // VFP Floating point register single precision 5683 case 'w': // VFP Floating point register double precision 5684 Info.setAllowsRegister(); 5685 return true; 5686 case 'I': 5687 case 'J': 5688 case 'K': 5689 case 'L': 5690 case 'M': 5691 // FIXME 5692 return true; 5693 case 'Q': // A memory address that is a single base register. 5694 Info.setAllowsMemory(); 5695 return true; 5696 case 'U': // a memory reference... 5697 switch (Name[1]) { 5698 case 'q': // ...ARMV4 ldrsb 5699 case 'v': // ...VFP load/store (reg+constant offset) 5700 case 'y': // ...iWMMXt load/store 5701 case 't': // address valid for load/store opaque types wider 5702 // than 128-bits 5703 case 'n': // valid address for Neon doubleword vector load/store 5704 case 'm': // valid address for Neon element and structure load/store 5705 case 's': // valid address for non-offset loads/stores of quad-word 5706 // values in four ARM registers 5707 Info.setAllowsMemory(); 5708 Name++; 5709 return true; 5710 } 5711 } 5712 return false; 5713 } 5714 std::string convertConstraint(const char *&Constraint) const override { 5715 std::string R; 5716 switch (*Constraint) { 5717 case 'U': // Two-character constraint; add "^" hint for later parsing. 5718 R = std::string("^") + std::string(Constraint, 2); 5719 Constraint++; 5720 break; 5721 case 'p': // 'p' should be translated to 'r' by default. 5722 R = std::string("r"); 5723 break; 5724 default: 5725 return std::string(1, *Constraint); 5726 } 5727 return R; 5728 } 5729 bool 5730 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5731 std::string &SuggestedModifier) const override { 5732 bool isOutput = (Constraint[0] == '='); 5733 bool isInOut = (Constraint[0] == '+'); 5734 5735 // Strip off constraint modifiers. 5736 while (Constraint[0] == '=' || 5737 Constraint[0] == '+' || 5738 Constraint[0] == '&') 5739 Constraint = Constraint.substr(1); 5740 5741 switch (Constraint[0]) { 5742 default: break; 5743 case 'r': { 5744 switch (Modifier) { 5745 default: 5746 return (isInOut || isOutput || Size <= 64); 5747 case 'q': 5748 // A register of size 32 cannot fit a vector type. 5749 return false; 5750 } 5751 } 5752 } 5753 5754 return true; 5755 } 5756 const char *getClobbers() const override { 5757 // FIXME: Is this really right? 5758 return ""; 5759 } 5760 5761 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5762 switch (CC) { 5763 case CC_AAPCS: 5764 case CC_AAPCS_VFP: 5765 case CC_Swift: 5766 return CCCR_OK; 5767 default: 5768 return CCCR_Warning; 5769 } 5770 } 5771 5772 int getEHDataRegisterNumber(unsigned RegNo) const override { 5773 if (RegNo == 0) return 0; 5774 if (RegNo == 1) return 1; 5775 return -1; 5776 } 5777 5778 bool hasSjLjLowering() const override { 5779 return true; 5780 } 5781 }; 5782 5783 bool ARMTargetInfo::setFPMath(StringRef Name) { 5784 if (Name == "neon") { 5785 FPMath = FP_Neon; 5786 return true; 5787 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5788 Name == "vfp4") { 5789 FPMath = FP_VFP; 5790 return true; 5791 } 5792 return false; 5793 } 5794 5795 const char * const ARMTargetInfo::GCCRegNames[] = { 5796 // Integer registers 5797 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5798 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5799 5800 // Float registers 5801 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5802 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5803 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5804 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5805 5806 // Double registers 5807 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5808 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5809 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5810 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5811 5812 // Quad registers 5813 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5814 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5815 }; 5816 5817 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5818 return llvm::makeArrayRef(GCCRegNames); 5819 } 5820 5821 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5822 { { "a1" }, "r0" }, 5823 { { "a2" }, "r1" }, 5824 { { "a3" }, "r2" }, 5825 { { "a4" }, "r3" }, 5826 { { "v1" }, "r4" }, 5827 { { "v2" }, "r5" }, 5828 { { "v3" }, "r6" }, 5829 { { "v4" }, "r7" }, 5830 { { "v5" }, "r8" }, 5831 { { "v6", "rfp" }, "r9" }, 5832 { { "sl" }, "r10" }, 5833 { { "fp" }, "r11" }, 5834 { { "ip" }, "r12" }, 5835 { { "r13" }, "sp" }, 5836 { { "r14" }, "lr" }, 5837 { { "r15" }, "pc" }, 5838 // The S, D and Q registers overlap, but aren't really aliases; we 5839 // don't want to substitute one of these for a different-sized one. 5840 }; 5841 5842 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5843 return llvm::makeArrayRef(GCCRegAliases); 5844 } 5845 5846 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5847 #define BUILTIN(ID, TYPE, ATTRS) \ 5848 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5849 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5850 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5851 #include "clang/Basic/BuiltinsNEON.def" 5852 5853 #define BUILTIN(ID, TYPE, ATTRS) \ 5854 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5855 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5856 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5857 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5858 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5859 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5860 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5861 #include "clang/Basic/BuiltinsARM.def" 5862 }; 5863 5864 class ARMleTargetInfo : public ARMTargetInfo { 5865 public: 5866 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5867 : ARMTargetInfo(Triple, Opts) {} 5868 void getTargetDefines(const LangOptions &Opts, 5869 MacroBuilder &Builder) const override { 5870 Builder.defineMacro("__ARMEL__"); 5871 ARMTargetInfo::getTargetDefines(Opts, Builder); 5872 } 5873 }; 5874 5875 class ARMbeTargetInfo : public ARMTargetInfo { 5876 public: 5877 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5878 : ARMTargetInfo(Triple, Opts) {} 5879 void getTargetDefines(const LangOptions &Opts, 5880 MacroBuilder &Builder) const override { 5881 Builder.defineMacro("__ARMEB__"); 5882 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5883 ARMTargetInfo::getTargetDefines(Opts, Builder); 5884 } 5885 }; 5886 5887 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5888 const llvm::Triple Triple; 5889 public: 5890 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5891 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5892 WCharType = UnsignedShort; 5893 SizeType = UnsignedInt; 5894 } 5895 void getVisualStudioDefines(const LangOptions &Opts, 5896 MacroBuilder &Builder) const { 5897 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5898 5899 // FIXME: this is invalid for WindowsCE 5900 Builder.defineMacro("_M_ARM_NT", "1"); 5901 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5902 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5903 5904 assert((Triple.getArch() == llvm::Triple::arm || 5905 Triple.getArch() == llvm::Triple::thumb) && 5906 "invalid architecture for Windows ARM target info"); 5907 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5908 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5909 5910 // TODO map the complete set of values 5911 // 31: VFPv3 40: VFPv4 5912 Builder.defineMacro("_M_ARM_FP", "31"); 5913 } 5914 BuiltinVaListKind getBuiltinVaListKind() const override { 5915 return TargetInfo::CharPtrBuiltinVaList; 5916 } 5917 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5918 switch (CC) { 5919 case CC_X86StdCall: 5920 case CC_X86ThisCall: 5921 case CC_X86FastCall: 5922 case CC_X86VectorCall: 5923 return CCCR_Ignore; 5924 case CC_C: 5925 return CCCR_OK; 5926 default: 5927 return CCCR_Warning; 5928 } 5929 } 5930 }; 5931 5932 // Windows ARM + Itanium C++ ABI Target 5933 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5934 public: 5935 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5936 const TargetOptions &Opts) 5937 : WindowsARMTargetInfo(Triple, Opts) { 5938 TheCXXABI.set(TargetCXXABI::GenericARM); 5939 } 5940 5941 void getTargetDefines(const LangOptions &Opts, 5942 MacroBuilder &Builder) const override { 5943 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5944 5945 if (Opts.MSVCCompat) 5946 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5947 } 5948 }; 5949 5950 // Windows ARM, MS (C++) ABI 5951 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5952 public: 5953 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5954 const TargetOptions &Opts) 5955 : WindowsARMTargetInfo(Triple, Opts) { 5956 TheCXXABI.set(TargetCXXABI::Microsoft); 5957 } 5958 5959 void getTargetDefines(const LangOptions &Opts, 5960 MacroBuilder &Builder) const override { 5961 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5962 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5963 } 5964 }; 5965 5966 // ARM MinGW target 5967 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5968 public: 5969 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5970 : WindowsARMTargetInfo(Triple, Opts) { 5971 TheCXXABI.set(TargetCXXABI::GenericARM); 5972 } 5973 5974 void getTargetDefines(const LangOptions &Opts, 5975 MacroBuilder &Builder) const override { 5976 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5977 DefineStd(Builder, "WIN32", Opts); 5978 DefineStd(Builder, "WINNT", Opts); 5979 Builder.defineMacro("_ARM_"); 5980 addMinGWDefines(Opts, Builder); 5981 } 5982 }; 5983 5984 // ARM Cygwin target 5985 class CygwinARMTargetInfo : public ARMleTargetInfo { 5986 public: 5987 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5988 : ARMleTargetInfo(Triple, Opts) { 5989 TLSSupported = false; 5990 WCharType = UnsignedShort; 5991 DoubleAlign = LongLongAlign = 64; 5992 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5993 } 5994 void getTargetDefines(const LangOptions &Opts, 5995 MacroBuilder &Builder) const override { 5996 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5997 Builder.defineMacro("_ARM_"); 5998 Builder.defineMacro("__CYGWIN__"); 5999 Builder.defineMacro("__CYGWIN32__"); 6000 DefineStd(Builder, "unix", Opts); 6001 if (Opts.CPlusPlus) 6002 Builder.defineMacro("_GNU_SOURCE"); 6003 } 6004 }; 6005 6006 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 6007 protected: 6008 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6009 MacroBuilder &Builder) const override { 6010 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6011 } 6012 6013 public: 6014 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6015 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 6016 HasAlignMac68kSupport = true; 6017 // iOS always has 64-bit atomic instructions. 6018 // FIXME: This should be based off of the target features in 6019 // ARMleTargetInfo. 6020 MaxAtomicInlineWidth = 64; 6021 6022 if (Triple.isWatchABI()) { 6023 // Darwin on iOS uses a variant of the ARM C++ ABI. 6024 TheCXXABI.set(TargetCXXABI::WatchOS); 6025 6026 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 6027 // size_t is long, it's a bit weird for it to be int. 6028 PtrDiffType = SignedLong; 6029 6030 // BOOL should be a real boolean on the new ABI 6031 UseSignedCharForObjCBool = false; 6032 } else 6033 TheCXXABI.set(TargetCXXABI::iOS); 6034 } 6035 }; 6036 6037 class AArch64TargetInfo : public TargetInfo { 6038 virtual void setDataLayout() = 0; 6039 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6040 static const char *const GCCRegNames[]; 6041 6042 enum FPUModeEnum { 6043 FPUMode, 6044 NeonMode 6045 }; 6046 6047 unsigned FPU; 6048 unsigned CRC; 6049 unsigned Crypto; 6050 unsigned Unaligned; 6051 unsigned V8_1A; 6052 6053 static const Builtin::Info BuiltinInfo[]; 6054 6055 std::string ABI; 6056 6057 public: 6058 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6059 : TargetInfo(Triple), ABI("aapcs") { 6060 if (getTriple().getOS() == llvm::Triple::NetBSD || 6061 getTriple().getOS() == llvm::Triple::OpenBSD) { 6062 WCharType = SignedInt; 6063 6064 // NetBSD apparently prefers consistency across ARM targets to consistency 6065 // across 64-bit targets. 6066 Int64Type = SignedLongLong; 6067 IntMaxType = SignedLongLong; 6068 } else { 6069 WCharType = UnsignedInt; 6070 Int64Type = SignedLong; 6071 IntMaxType = SignedLong; 6072 } 6073 6074 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6075 MaxVectorAlign = 128; 6076 MaxAtomicInlineWidth = 128; 6077 MaxAtomicPromoteWidth = 128; 6078 6079 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 6080 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6081 6082 // {} in inline assembly are neon specifiers, not assembly variant 6083 // specifiers. 6084 NoAsmVariants = true; 6085 6086 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 6087 // contributes to the alignment of the containing aggregate in the same way 6088 // a plain (non bit-field) member of that type would, without exception for 6089 // zero-sized or anonymous bit-fields." 6090 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 6091 UseZeroLengthBitfieldAlignment = true; 6092 6093 // AArch64 targets default to using the ARM C++ ABI. 6094 TheCXXABI.set(TargetCXXABI::GenericAArch64); 6095 6096 if (Triple.getOS() == llvm::Triple::Linux) 6097 this->MCountName = "\01_mcount"; 6098 else if (Triple.getOS() == llvm::Triple::UnknownOS) 6099 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 6100 } 6101 6102 StringRef getABI() const override { return ABI; } 6103 bool setABI(const std::string &Name) override { 6104 if (Name != "aapcs" && Name != "darwinpcs") 6105 return false; 6106 6107 ABI = Name; 6108 return true; 6109 } 6110 6111 bool setCPU(const std::string &Name) override { 6112 return Name == "generic" || 6113 llvm::AArch64::parseCPUArch(Name) != 6114 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6115 } 6116 6117 void getTargetDefines(const LangOptions &Opts, 6118 MacroBuilder &Builder) const override { 6119 // Target identification. 6120 Builder.defineMacro("__aarch64__"); 6121 6122 // Target properties. 6123 Builder.defineMacro("_LP64"); 6124 Builder.defineMacro("__LP64__"); 6125 6126 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6127 Builder.defineMacro("__ARM_ACLE", "200"); 6128 Builder.defineMacro("__ARM_ARCH", "8"); 6129 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6130 6131 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6132 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6133 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6134 6135 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6136 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6137 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6138 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6139 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6140 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6141 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6142 6143 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6144 6145 // 0xe implies support for half, single and double precision operations. 6146 Builder.defineMacro("__ARM_FP", "0xE"); 6147 6148 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6149 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6150 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6151 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6152 6153 if (Opts.UnsafeFPMath) 6154 Builder.defineMacro("__ARM_FP_FAST", "1"); 6155 6156 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6157 6158 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6159 Opts.ShortEnums ? "1" : "4"); 6160 6161 if (FPU == NeonMode) { 6162 Builder.defineMacro("__ARM_NEON", "1"); 6163 // 64-bit NEON supports half, single and double precision operations. 6164 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6165 } 6166 6167 if (CRC) 6168 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6169 6170 if (Crypto) 6171 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6172 6173 if (Unaligned) 6174 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6175 6176 if (V8_1A) 6177 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6178 6179 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6180 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6181 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6182 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6183 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6184 } 6185 6186 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6187 return llvm::makeArrayRef(BuiltinInfo, 6188 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6189 } 6190 6191 bool hasFeature(StringRef Feature) const override { 6192 return Feature == "aarch64" || 6193 Feature == "arm64" || 6194 Feature == "arm" || 6195 (Feature == "neon" && FPU == NeonMode); 6196 } 6197 6198 bool handleTargetFeatures(std::vector<std::string> &Features, 6199 DiagnosticsEngine &Diags) override { 6200 FPU = FPUMode; 6201 CRC = 0; 6202 Crypto = 0; 6203 Unaligned = 1; 6204 V8_1A = 0; 6205 6206 for (const auto &Feature : Features) { 6207 if (Feature == "+neon") 6208 FPU = NeonMode; 6209 if (Feature == "+crc") 6210 CRC = 1; 6211 if (Feature == "+crypto") 6212 Crypto = 1; 6213 if (Feature == "+strict-align") 6214 Unaligned = 0; 6215 if (Feature == "+v8.1a") 6216 V8_1A = 1; 6217 } 6218 6219 setDataLayout(); 6220 6221 return true; 6222 } 6223 6224 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6225 switch (CC) { 6226 case CC_C: 6227 case CC_Swift: 6228 case CC_PreserveMost: 6229 case CC_PreserveAll: 6230 return CCCR_OK; 6231 default: 6232 return CCCR_Warning; 6233 } 6234 } 6235 6236 bool isCLZForZeroUndef() const override { return false; } 6237 6238 BuiltinVaListKind getBuiltinVaListKind() const override { 6239 return TargetInfo::AArch64ABIBuiltinVaList; 6240 } 6241 6242 ArrayRef<const char *> getGCCRegNames() const override; 6243 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6244 6245 bool validateAsmConstraint(const char *&Name, 6246 TargetInfo::ConstraintInfo &Info) const override { 6247 switch (*Name) { 6248 default: 6249 return false; 6250 case 'w': // Floating point and SIMD registers (V0-V31) 6251 Info.setAllowsRegister(); 6252 return true; 6253 case 'I': // Constant that can be used with an ADD instruction 6254 case 'J': // Constant that can be used with a SUB instruction 6255 case 'K': // Constant that can be used with a 32-bit logical instruction 6256 case 'L': // Constant that can be used with a 64-bit logical instruction 6257 case 'M': // Constant that can be used as a 32-bit MOV immediate 6258 case 'N': // Constant that can be used as a 64-bit MOV immediate 6259 case 'Y': // Floating point constant zero 6260 case 'Z': // Integer constant zero 6261 return true; 6262 case 'Q': // A memory reference with base register and no offset 6263 Info.setAllowsMemory(); 6264 return true; 6265 case 'S': // A symbolic address 6266 Info.setAllowsRegister(); 6267 return true; 6268 case 'U': 6269 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6270 // Utf: A memory address suitable for ldp/stp in TF mode. 6271 // Usa: An absolute symbolic address. 6272 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6273 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6274 case 'z': // Zero register, wzr or xzr 6275 Info.setAllowsRegister(); 6276 return true; 6277 case 'x': // Floating point and SIMD registers (V0-V15) 6278 Info.setAllowsRegister(); 6279 return true; 6280 } 6281 return false; 6282 } 6283 6284 bool 6285 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6286 std::string &SuggestedModifier) const override { 6287 // Strip off constraint modifiers. 6288 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6289 Constraint = Constraint.substr(1); 6290 6291 switch (Constraint[0]) { 6292 default: 6293 return true; 6294 case 'z': 6295 case 'r': { 6296 switch (Modifier) { 6297 case 'x': 6298 case 'w': 6299 // For now assume that the person knows what they're 6300 // doing with the modifier. 6301 return true; 6302 default: 6303 // By default an 'r' constraint will be in the 'x' 6304 // registers. 6305 if (Size == 64) 6306 return true; 6307 6308 SuggestedModifier = "w"; 6309 return false; 6310 } 6311 } 6312 } 6313 } 6314 6315 const char *getClobbers() const override { return ""; } 6316 6317 int getEHDataRegisterNumber(unsigned RegNo) const override { 6318 if (RegNo == 0) 6319 return 0; 6320 if (RegNo == 1) 6321 return 1; 6322 return -1; 6323 } 6324 }; 6325 6326 const char *const AArch64TargetInfo::GCCRegNames[] = { 6327 // 32-bit Integer registers 6328 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6329 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6330 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6331 6332 // 64-bit Integer registers 6333 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6334 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6335 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6336 6337 // 32-bit floating point regsisters 6338 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6339 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6340 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6341 6342 // 64-bit floating point regsisters 6343 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6344 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6345 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6346 6347 // Vector registers 6348 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6349 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6350 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6351 }; 6352 6353 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6354 return llvm::makeArrayRef(GCCRegNames); 6355 } 6356 6357 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6358 { { "w31" }, "wsp" }, 6359 { { "x29" }, "fp" }, 6360 { { "x30" }, "lr" }, 6361 { { "x31" }, "sp" }, 6362 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6363 // don't want to substitute one of these for a different-sized one. 6364 }; 6365 6366 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6367 return llvm::makeArrayRef(GCCRegAliases); 6368 } 6369 6370 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6371 #define BUILTIN(ID, TYPE, ATTRS) \ 6372 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6373 #include "clang/Basic/BuiltinsNEON.def" 6374 6375 #define BUILTIN(ID, TYPE, ATTRS) \ 6376 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6377 #include "clang/Basic/BuiltinsAArch64.def" 6378 }; 6379 6380 class AArch64leTargetInfo : public AArch64TargetInfo { 6381 void setDataLayout() override { 6382 if (getTriple().isOSBinFormatMachO()) 6383 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6384 else 6385 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6386 } 6387 6388 public: 6389 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6390 : AArch64TargetInfo(Triple, Opts) { 6391 } 6392 void getTargetDefines(const LangOptions &Opts, 6393 MacroBuilder &Builder) const override { 6394 Builder.defineMacro("__AARCH64EL__"); 6395 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6396 } 6397 }; 6398 6399 class AArch64beTargetInfo : public AArch64TargetInfo { 6400 void setDataLayout() override { 6401 assert(!getTriple().isOSBinFormatMachO()); 6402 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6403 } 6404 6405 public: 6406 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6407 : AArch64TargetInfo(Triple, Opts) {} 6408 void getTargetDefines(const LangOptions &Opts, 6409 MacroBuilder &Builder) const override { 6410 Builder.defineMacro("__AARCH64EB__"); 6411 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6412 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6413 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6414 } 6415 }; 6416 6417 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6418 protected: 6419 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6420 MacroBuilder &Builder) const override { 6421 Builder.defineMacro("__AARCH64_SIMD__"); 6422 Builder.defineMacro("__ARM64_ARCH_8__"); 6423 Builder.defineMacro("__ARM_NEON__"); 6424 Builder.defineMacro("__LITTLE_ENDIAN__"); 6425 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6426 Builder.defineMacro("__arm64", "1"); 6427 Builder.defineMacro("__arm64__", "1"); 6428 6429 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6430 } 6431 6432 public: 6433 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6434 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6435 Int64Type = SignedLongLong; 6436 WCharType = SignedInt; 6437 UseSignedCharForObjCBool = false; 6438 6439 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6440 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6441 6442 TheCXXABI.set(TargetCXXABI::iOS64); 6443 } 6444 6445 BuiltinVaListKind getBuiltinVaListKind() const override { 6446 return TargetInfo::CharPtrBuiltinVaList; 6447 } 6448 }; 6449 6450 // Hexagon abstract base class 6451 class HexagonTargetInfo : public TargetInfo { 6452 static const Builtin::Info BuiltinInfo[]; 6453 static const char * const GCCRegNames[]; 6454 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6455 std::string CPU; 6456 bool HasHVX, HasHVXDouble; 6457 bool UseLongCalls; 6458 6459 public: 6460 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6461 : TargetInfo(Triple) { 6462 // Specify the vector alignment explicitly. For v512x1, the calculated 6463 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6464 // the required minimum of 64 bytes. 6465 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6466 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6467 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6468 SizeType = UnsignedInt; 6469 PtrDiffType = SignedInt; 6470 IntPtrType = SignedInt; 6471 6472 // {} in inline assembly are packet specifiers, not assembly variant 6473 // specifiers. 6474 NoAsmVariants = true; 6475 6476 LargeArrayMinWidth = 64; 6477 LargeArrayAlign = 64; 6478 UseBitFieldTypeAlignment = true; 6479 ZeroLengthBitfieldBoundary = 32; 6480 HasHVX = HasHVXDouble = false; 6481 UseLongCalls = false; 6482 } 6483 6484 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6485 return llvm::makeArrayRef(BuiltinInfo, 6486 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6487 } 6488 6489 bool validateAsmConstraint(const char *&Name, 6490 TargetInfo::ConstraintInfo &Info) const override { 6491 switch (*Name) { 6492 case 'v': 6493 case 'q': 6494 if (HasHVX) { 6495 Info.setAllowsRegister(); 6496 return true; 6497 } 6498 break; 6499 case 's': 6500 // Relocatable constant. 6501 return true; 6502 } 6503 return false; 6504 } 6505 6506 void getTargetDefines(const LangOptions &Opts, 6507 MacroBuilder &Builder) const override; 6508 6509 bool isCLZForZeroUndef() const override { return false; } 6510 6511 bool hasFeature(StringRef Feature) const override { 6512 return llvm::StringSwitch<bool>(Feature) 6513 .Case("hexagon", true) 6514 .Case("hvx", HasHVX) 6515 .Case("hvx-double", HasHVXDouble) 6516 .Case("long-calls", UseLongCalls) 6517 .Default(false); 6518 } 6519 6520 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6521 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6522 const override; 6523 6524 bool handleTargetFeatures(std::vector<std::string> &Features, 6525 DiagnosticsEngine &Diags) override; 6526 6527 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6528 bool Enabled) const override; 6529 6530 BuiltinVaListKind getBuiltinVaListKind() const override { 6531 return TargetInfo::CharPtrBuiltinVaList; 6532 } 6533 ArrayRef<const char *> getGCCRegNames() const override; 6534 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6535 const char *getClobbers() const override { 6536 return ""; 6537 } 6538 6539 static const char *getHexagonCPUSuffix(StringRef Name) { 6540 return llvm::StringSwitch<const char*>(Name) 6541 .Case("hexagonv4", "4") 6542 .Case("hexagonv5", "5") 6543 .Case("hexagonv55", "55") 6544 .Case("hexagonv60", "60") 6545 .Case("hexagonv62", "62") 6546 .Default(nullptr); 6547 } 6548 6549 bool setCPU(const std::string &Name) override { 6550 if (!getHexagonCPUSuffix(Name)) 6551 return false; 6552 CPU = Name; 6553 return true; 6554 } 6555 6556 int getEHDataRegisterNumber(unsigned RegNo) const override { 6557 return RegNo < 2 ? RegNo : -1; 6558 } 6559 }; 6560 6561 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6562 MacroBuilder &Builder) const { 6563 Builder.defineMacro("__qdsp6__", "1"); 6564 Builder.defineMacro("__hexagon__", "1"); 6565 6566 if (CPU == "hexagonv4") { 6567 Builder.defineMacro("__HEXAGON_V4__"); 6568 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6569 if (Opts.HexagonQdsp6Compat) { 6570 Builder.defineMacro("__QDSP6_V4__"); 6571 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6572 } 6573 } else if (CPU == "hexagonv5") { 6574 Builder.defineMacro("__HEXAGON_V5__"); 6575 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6576 if(Opts.HexagonQdsp6Compat) { 6577 Builder.defineMacro("__QDSP6_V5__"); 6578 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6579 } 6580 } else if (CPU == "hexagonv55") { 6581 Builder.defineMacro("__HEXAGON_V55__"); 6582 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6583 Builder.defineMacro("__QDSP6_V55__"); 6584 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6585 } else if (CPU == "hexagonv60") { 6586 Builder.defineMacro("__HEXAGON_V60__"); 6587 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6588 Builder.defineMacro("__QDSP6_V60__"); 6589 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6590 } else if (CPU == "hexagonv62") { 6591 Builder.defineMacro("__HEXAGON_V62__"); 6592 Builder.defineMacro("__HEXAGON_ARCH__", "62"); 6593 } 6594 6595 if (hasFeature("hvx")) { 6596 Builder.defineMacro("__HVX__"); 6597 if (hasFeature("hvx-double")) 6598 Builder.defineMacro("__HVXDBL__"); 6599 } 6600 } 6601 6602 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6603 DiagnosticsEngine &Diags, StringRef CPU, 6604 const std::vector<std::string> &FeaturesVec) const { 6605 // Default for v60: -hvx, -hvx-double. 6606 Features["hvx"] = false; 6607 Features["hvx-double"] = false; 6608 Features["long-calls"] = false; 6609 6610 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6611 } 6612 6613 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6614 DiagnosticsEngine &Diags) { 6615 for (auto &F : Features) { 6616 if (F == "+hvx") 6617 HasHVX = true; 6618 else if (F == "-hvx") 6619 HasHVX = HasHVXDouble = false; 6620 else if (F == "+hvx-double") 6621 HasHVX = HasHVXDouble = true; 6622 else if (F == "-hvx-double") 6623 HasHVXDouble = false; 6624 6625 if (F == "+long-calls") 6626 UseLongCalls = true; 6627 else if (F == "-long-calls") 6628 UseLongCalls = false; 6629 } 6630 return true; 6631 } 6632 6633 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6634 StringRef Name, bool Enabled) const { 6635 if (Enabled) { 6636 if (Name == "hvx-double") 6637 Features["hvx"] = true; 6638 } else { 6639 if (Name == "hvx") 6640 Features["hvx-double"] = false; 6641 } 6642 Features[Name] = Enabled; 6643 } 6644 6645 const char *const HexagonTargetInfo::GCCRegNames[] = { 6646 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6647 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6648 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6649 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6650 "p0", "p1", "p2", "p3", 6651 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6652 }; 6653 6654 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6655 return llvm::makeArrayRef(GCCRegNames); 6656 } 6657 6658 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6659 { { "sp" }, "r29" }, 6660 { { "fp" }, "r30" }, 6661 { { "lr" }, "r31" }, 6662 }; 6663 6664 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6665 return llvm::makeArrayRef(GCCRegAliases); 6666 } 6667 6668 6669 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6670 #define BUILTIN(ID, TYPE, ATTRS) \ 6671 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6672 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6673 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6674 #include "clang/Basic/BuiltinsHexagon.def" 6675 }; 6676 6677 class LanaiTargetInfo : public TargetInfo { 6678 // Class for Lanai (32-bit). 6679 // The CPU profiles supported by the Lanai backend 6680 enum CPUKind { 6681 CK_NONE, 6682 CK_V11, 6683 } CPU; 6684 6685 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6686 static const char *const GCCRegNames[]; 6687 6688 public: 6689 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6690 : TargetInfo(Triple) { 6691 // Description string has to be kept in sync with backend. 6692 resetDataLayout("E" // Big endian 6693 "-m:e" // ELF name manging 6694 "-p:32:32" // 32 bit pointers, 32 bit aligned 6695 "-i64:64" // 64 bit integers, 64 bit aligned 6696 "-a:0:32" // 32 bit alignment of objects of aggregate type 6697 "-n32" // 32 bit native integer width 6698 "-S64" // 64 bit natural stack alignment 6699 ); 6700 6701 // Setting RegParmMax equal to what mregparm was set to in the old 6702 // toolchain 6703 RegParmMax = 4; 6704 6705 // Set the default CPU to V11 6706 CPU = CK_V11; 6707 6708 // Temporary approach to make everything at least word-aligned and allow for 6709 // safely casting between pointers with different alignment requirements. 6710 // TODO: Remove this when there are no more cast align warnings on the 6711 // firmware. 6712 MinGlobalAlign = 32; 6713 } 6714 6715 void getTargetDefines(const LangOptions &Opts, 6716 MacroBuilder &Builder) const override { 6717 // Define __lanai__ when building for target lanai. 6718 Builder.defineMacro("__lanai__"); 6719 6720 // Set define for the CPU specified. 6721 switch (CPU) { 6722 case CK_V11: 6723 Builder.defineMacro("__LANAI_V11__"); 6724 break; 6725 case CK_NONE: 6726 llvm_unreachable("Unhandled target CPU"); 6727 } 6728 } 6729 6730 bool setCPU(const std::string &Name) override { 6731 CPU = llvm::StringSwitch<CPUKind>(Name) 6732 .Case("v11", CK_V11) 6733 .Default(CK_NONE); 6734 6735 return CPU != CK_NONE; 6736 } 6737 6738 bool hasFeature(StringRef Feature) const override { 6739 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6740 } 6741 6742 ArrayRef<const char *> getGCCRegNames() const override; 6743 6744 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6745 6746 BuiltinVaListKind getBuiltinVaListKind() const override { 6747 return TargetInfo::VoidPtrBuiltinVaList; 6748 } 6749 6750 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6751 6752 bool validateAsmConstraint(const char *&Name, 6753 TargetInfo::ConstraintInfo &info) const override { 6754 return false; 6755 } 6756 6757 const char *getClobbers() const override { return ""; } 6758 }; 6759 6760 const char *const LanaiTargetInfo::GCCRegNames[] = { 6761 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6762 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6763 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6764 6765 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6766 return llvm::makeArrayRef(GCCRegNames); 6767 } 6768 6769 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6770 {{"pc"}, "r2"}, 6771 {{"sp"}, "r4"}, 6772 {{"fp"}, "r5"}, 6773 {{"rv"}, "r8"}, 6774 {{"rr1"}, "r10"}, 6775 {{"rr2"}, "r11"}, 6776 {{"rca"}, "r15"}, 6777 }; 6778 6779 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6780 return llvm::makeArrayRef(GCCRegAliases); 6781 } 6782 6783 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6784 class SparcTargetInfo : public TargetInfo { 6785 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6786 static const char * const GCCRegNames[]; 6787 bool SoftFloat; 6788 public: 6789 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6790 : TargetInfo(Triple), SoftFloat(false) {} 6791 6792 int getEHDataRegisterNumber(unsigned RegNo) const override { 6793 if (RegNo == 0) return 24; 6794 if (RegNo == 1) return 25; 6795 return -1; 6796 } 6797 6798 bool handleTargetFeatures(std::vector<std::string> &Features, 6799 DiagnosticsEngine &Diags) override { 6800 // Check if software floating point is enabled 6801 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6802 if (Feature != Features.end()) { 6803 SoftFloat = true; 6804 } 6805 return true; 6806 } 6807 void getTargetDefines(const LangOptions &Opts, 6808 MacroBuilder &Builder) const override { 6809 DefineStd(Builder, "sparc", Opts); 6810 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6811 6812 if (SoftFloat) 6813 Builder.defineMacro("SOFT_FLOAT", "1"); 6814 } 6815 6816 bool hasFeature(StringRef Feature) const override { 6817 return llvm::StringSwitch<bool>(Feature) 6818 .Case("softfloat", SoftFloat) 6819 .Case("sparc", true) 6820 .Default(false); 6821 } 6822 6823 bool hasSjLjLowering() const override { 6824 return true; 6825 } 6826 6827 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6828 // FIXME: Implement! 6829 return None; 6830 } 6831 BuiltinVaListKind getBuiltinVaListKind() const override { 6832 return TargetInfo::VoidPtrBuiltinVaList; 6833 } 6834 ArrayRef<const char *> getGCCRegNames() const override; 6835 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6836 bool validateAsmConstraint(const char *&Name, 6837 TargetInfo::ConstraintInfo &info) const override { 6838 // FIXME: Implement! 6839 switch (*Name) { 6840 case 'I': // Signed 13-bit constant 6841 case 'J': // Zero 6842 case 'K': // 32-bit constant with the low 12 bits clear 6843 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6844 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6845 case 'N': // Same as 'K' but zext (required for SIMode) 6846 case 'O': // The constant 4096 6847 return true; 6848 } 6849 return false; 6850 } 6851 const char *getClobbers() const override { 6852 // FIXME: Implement! 6853 return ""; 6854 } 6855 6856 // No Sparc V7 for now, the backend doesn't support it anyway. 6857 enum CPUKind { 6858 CK_GENERIC, 6859 CK_V8, 6860 CK_SUPERSPARC, 6861 CK_SPARCLITE, 6862 CK_F934, 6863 CK_HYPERSPARC, 6864 CK_SPARCLITE86X, 6865 CK_SPARCLET, 6866 CK_TSC701, 6867 CK_V9, 6868 CK_ULTRASPARC, 6869 CK_ULTRASPARC3, 6870 CK_NIAGARA, 6871 CK_NIAGARA2, 6872 CK_NIAGARA3, 6873 CK_NIAGARA4, 6874 CK_MYRIAD2100, 6875 CK_MYRIAD2150, 6876 CK_MYRIAD2450, 6877 CK_LEON2, 6878 CK_LEON2_AT697E, 6879 CK_LEON2_AT697F, 6880 CK_LEON3, 6881 CK_LEON3_UT699, 6882 CK_LEON3_GR712RC, 6883 CK_LEON4, 6884 CK_LEON4_GR740 6885 } CPU = CK_GENERIC; 6886 6887 enum CPUGeneration { 6888 CG_V8, 6889 CG_V9, 6890 }; 6891 6892 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6893 switch (Kind) { 6894 case CK_GENERIC: 6895 case CK_V8: 6896 case CK_SUPERSPARC: 6897 case CK_SPARCLITE: 6898 case CK_F934: 6899 case CK_HYPERSPARC: 6900 case CK_SPARCLITE86X: 6901 case CK_SPARCLET: 6902 case CK_TSC701: 6903 case CK_MYRIAD2100: 6904 case CK_MYRIAD2150: 6905 case CK_MYRIAD2450: 6906 case CK_LEON2: 6907 case CK_LEON2_AT697E: 6908 case CK_LEON2_AT697F: 6909 case CK_LEON3: 6910 case CK_LEON3_UT699: 6911 case CK_LEON3_GR712RC: 6912 case CK_LEON4: 6913 case CK_LEON4_GR740: 6914 return CG_V8; 6915 case CK_V9: 6916 case CK_ULTRASPARC: 6917 case CK_ULTRASPARC3: 6918 case CK_NIAGARA: 6919 case CK_NIAGARA2: 6920 case CK_NIAGARA3: 6921 case CK_NIAGARA4: 6922 return CG_V9; 6923 } 6924 llvm_unreachable("Unexpected CPU kind"); 6925 } 6926 6927 CPUKind getCPUKind(StringRef Name) const { 6928 return llvm::StringSwitch<CPUKind>(Name) 6929 .Case("v8", CK_V8) 6930 .Case("supersparc", CK_SUPERSPARC) 6931 .Case("sparclite", CK_SPARCLITE) 6932 .Case("f934", CK_F934) 6933 .Case("hypersparc", CK_HYPERSPARC) 6934 .Case("sparclite86x", CK_SPARCLITE86X) 6935 .Case("sparclet", CK_SPARCLET) 6936 .Case("tsc701", CK_TSC701) 6937 .Case("v9", CK_V9) 6938 .Case("ultrasparc", CK_ULTRASPARC) 6939 .Case("ultrasparc3", CK_ULTRASPARC3) 6940 .Case("niagara", CK_NIAGARA) 6941 .Case("niagara2", CK_NIAGARA2) 6942 .Case("niagara3", CK_NIAGARA3) 6943 .Case("niagara4", CK_NIAGARA4) 6944 .Case("ma2100", CK_MYRIAD2100) 6945 .Case("ma2150", CK_MYRIAD2150) 6946 .Case("ma2450", CK_MYRIAD2450) 6947 // FIXME: the myriad2[.n] spellings are obsolete, 6948 // but a grace period is needed to allow updating dependent builds. 6949 .Case("myriad2", CK_MYRIAD2100) 6950 .Case("myriad2.1", CK_MYRIAD2100) 6951 .Case("myriad2.2", CK_MYRIAD2150) 6952 .Case("leon2", CK_LEON2) 6953 .Case("at697e", CK_LEON2_AT697E) 6954 .Case("at697f", CK_LEON2_AT697F) 6955 .Case("leon3", CK_LEON3) 6956 .Case("ut699", CK_LEON3_UT699) 6957 .Case("gr712rc", CK_LEON3_GR712RC) 6958 .Case("leon4", CK_LEON4) 6959 .Case("gr740", CK_LEON4_GR740) 6960 .Default(CK_GENERIC); 6961 } 6962 6963 bool setCPU(const std::string &Name) override { 6964 CPU = getCPUKind(Name); 6965 return CPU != CK_GENERIC; 6966 } 6967 }; 6968 6969 const char * const SparcTargetInfo::GCCRegNames[] = { 6970 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6971 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6972 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6973 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6974 }; 6975 6976 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6977 return llvm::makeArrayRef(GCCRegNames); 6978 } 6979 6980 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6981 { { "g0" }, "r0" }, 6982 { { "g1" }, "r1" }, 6983 { { "g2" }, "r2" }, 6984 { { "g3" }, "r3" }, 6985 { { "g4" }, "r4" }, 6986 { { "g5" }, "r5" }, 6987 { { "g6" }, "r6" }, 6988 { { "g7" }, "r7" }, 6989 { { "o0" }, "r8" }, 6990 { { "o1" }, "r9" }, 6991 { { "o2" }, "r10" }, 6992 { { "o3" }, "r11" }, 6993 { { "o4" }, "r12" }, 6994 { { "o5" }, "r13" }, 6995 { { "o6", "sp" }, "r14" }, 6996 { { "o7" }, "r15" }, 6997 { { "l0" }, "r16" }, 6998 { { "l1" }, "r17" }, 6999 { { "l2" }, "r18" }, 7000 { { "l3" }, "r19" }, 7001 { { "l4" }, "r20" }, 7002 { { "l5" }, "r21" }, 7003 { { "l6" }, "r22" }, 7004 { { "l7" }, "r23" }, 7005 { { "i0" }, "r24" }, 7006 { { "i1" }, "r25" }, 7007 { { "i2" }, "r26" }, 7008 { { "i3" }, "r27" }, 7009 { { "i4" }, "r28" }, 7010 { { "i5" }, "r29" }, 7011 { { "i6", "fp" }, "r30" }, 7012 { { "i7" }, "r31" }, 7013 }; 7014 7015 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 7016 return llvm::makeArrayRef(GCCRegAliases); 7017 } 7018 7019 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 7020 class SparcV8TargetInfo : public SparcTargetInfo { 7021 public: 7022 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7023 : SparcTargetInfo(Triple, Opts) { 7024 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7025 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 7026 switch (getTriple().getOS()) { 7027 default: 7028 SizeType = UnsignedInt; 7029 IntPtrType = SignedInt; 7030 PtrDiffType = SignedInt; 7031 break; 7032 case llvm::Triple::NetBSD: 7033 case llvm::Triple::OpenBSD: 7034 SizeType = UnsignedLong; 7035 IntPtrType = SignedLong; 7036 PtrDiffType = SignedLong; 7037 break; 7038 } 7039 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 7040 // on up to 64 bits. 7041 MaxAtomicPromoteWidth = 64; 7042 MaxAtomicInlineWidth = 32; 7043 } 7044 7045 void getTargetDefines(const LangOptions &Opts, 7046 MacroBuilder &Builder) const override { 7047 SparcTargetInfo::getTargetDefines(Opts, Builder); 7048 switch (getCPUGeneration(CPU)) { 7049 case CG_V8: 7050 Builder.defineMacro("__sparcv8"); 7051 if (getTriple().getOS() != llvm::Triple::Solaris) 7052 Builder.defineMacro("__sparcv8__"); 7053 break; 7054 case CG_V9: 7055 Builder.defineMacro("__sparcv9"); 7056 if (getTriple().getOS() != llvm::Triple::Solaris) { 7057 Builder.defineMacro("__sparcv9__"); 7058 Builder.defineMacro("__sparc_v9__"); 7059 } 7060 break; 7061 } 7062 if (getTriple().getVendor() == llvm::Triple::Myriad) { 7063 std::string MyriadArchValue, Myriad2Value; 7064 Builder.defineMacro("__sparc_v8__"); 7065 Builder.defineMacro("__leon__"); 7066 switch (CPU) { 7067 case CK_MYRIAD2150: 7068 MyriadArchValue = "__ma2150"; 7069 Myriad2Value = "2"; 7070 break; 7071 case CK_MYRIAD2450: 7072 MyriadArchValue = "__ma2450"; 7073 Myriad2Value = "2"; 7074 break; 7075 default: 7076 MyriadArchValue = "__ma2100"; 7077 Myriad2Value = "1"; 7078 break; 7079 } 7080 Builder.defineMacro(MyriadArchValue, "1"); 7081 Builder.defineMacro(MyriadArchValue+"__", "1"); 7082 Builder.defineMacro("__myriad2__", Myriad2Value); 7083 Builder.defineMacro("__myriad2", Myriad2Value); 7084 } 7085 } 7086 7087 bool hasSjLjLowering() const override { 7088 return true; 7089 } 7090 }; 7091 7092 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 7093 class SparcV8elTargetInfo : public SparcV8TargetInfo { 7094 public: 7095 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7096 : SparcV8TargetInfo(Triple, Opts) { 7097 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7098 } 7099 }; 7100 7101 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 7102 class SparcV9TargetInfo : public SparcTargetInfo { 7103 public: 7104 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7105 : SparcTargetInfo(Triple, Opts) { 7106 // FIXME: Support Sparc quad-precision long double? 7107 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 7108 // This is an LP64 platform. 7109 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7110 7111 // OpenBSD uses long long for int64_t and intmax_t. 7112 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7113 IntMaxType = SignedLongLong; 7114 else 7115 IntMaxType = SignedLong; 7116 Int64Type = IntMaxType; 7117 7118 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7119 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7120 LongDoubleWidth = 128; 7121 LongDoubleAlign = 128; 7122 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7123 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7124 } 7125 7126 void getTargetDefines(const LangOptions &Opts, 7127 MacroBuilder &Builder) const override { 7128 SparcTargetInfo::getTargetDefines(Opts, Builder); 7129 Builder.defineMacro("__sparcv9"); 7130 Builder.defineMacro("__arch64__"); 7131 // Solaris doesn't need these variants, but the BSDs do. 7132 if (getTriple().getOS() != llvm::Triple::Solaris) { 7133 Builder.defineMacro("__sparc64__"); 7134 Builder.defineMacro("__sparc_v9__"); 7135 Builder.defineMacro("__sparcv9__"); 7136 } 7137 } 7138 7139 bool setCPU(const std::string &Name) override { 7140 if (!SparcTargetInfo::setCPU(Name)) 7141 return false; 7142 return getCPUGeneration(CPU) == CG_V9; 7143 } 7144 }; 7145 7146 class SystemZTargetInfo : public TargetInfo { 7147 static const Builtin::Info BuiltinInfo[]; 7148 static const char *const GCCRegNames[]; 7149 std::string CPU; 7150 bool HasTransactionalExecution; 7151 bool HasVector; 7152 7153 public: 7154 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7155 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 7156 HasVector(false) { 7157 IntMaxType = SignedLong; 7158 Int64Type = SignedLong; 7159 TLSSupported = true; 7160 IntWidth = IntAlign = 32; 7161 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7162 PointerWidth = PointerAlign = 64; 7163 LongDoubleWidth = 128; 7164 LongDoubleAlign = 64; 7165 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7166 DefaultAlignForAttributeAligned = 64; 7167 MinGlobalAlign = 16; 7168 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7169 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7170 } 7171 void getTargetDefines(const LangOptions &Opts, 7172 MacroBuilder &Builder) const override { 7173 Builder.defineMacro("__s390__"); 7174 Builder.defineMacro("__s390x__"); 7175 Builder.defineMacro("__zarch__"); 7176 Builder.defineMacro("__LONG_DOUBLE_128__"); 7177 7178 const std::string ISARev = llvm::StringSwitch<std::string>(CPU) 7179 .Cases("arch8", "z10", "8") 7180 .Cases("arch9", "z196", "9") 7181 .Cases("arch10", "zEC12", "10") 7182 .Cases("arch11", "z13", "11") 7183 .Default(""); 7184 if (!ISARev.empty()) 7185 Builder.defineMacro("__ARCH__", ISARev); 7186 7187 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7188 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7189 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7190 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7191 7192 if (HasTransactionalExecution) 7193 Builder.defineMacro("__HTM__"); 7194 if (HasVector) 7195 Builder.defineMacro("__VX__"); 7196 if (Opts.ZVector) 7197 Builder.defineMacro("__VEC__", "10301"); 7198 } 7199 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7200 return llvm::makeArrayRef(BuiltinInfo, 7201 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7202 } 7203 7204 ArrayRef<const char *> getGCCRegNames() const override; 7205 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7206 // No aliases. 7207 return None; 7208 } 7209 bool validateAsmConstraint(const char *&Name, 7210 TargetInfo::ConstraintInfo &info) const override; 7211 const char *getClobbers() const override { 7212 // FIXME: Is this really right? 7213 return ""; 7214 } 7215 BuiltinVaListKind getBuiltinVaListKind() const override { 7216 return TargetInfo::SystemZBuiltinVaList; 7217 } 7218 bool setCPU(const std::string &Name) override { 7219 CPU = Name; 7220 bool CPUKnown = llvm::StringSwitch<bool>(Name) 7221 .Case("z10", true) 7222 .Case("arch8", true) 7223 .Case("z196", true) 7224 .Case("arch9", true) 7225 .Case("zEC12", true) 7226 .Case("arch10", true) 7227 .Case("z13", true) 7228 .Case("arch11", true) 7229 .Default(false); 7230 7231 return CPUKnown; 7232 } 7233 bool 7234 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7235 StringRef CPU, 7236 const std::vector<std::string> &FeaturesVec) const override { 7237 if (CPU == "zEC12" || CPU == "arch10") 7238 Features["transactional-execution"] = true; 7239 if (CPU == "z13" || CPU == "arch11") { 7240 Features["transactional-execution"] = true; 7241 Features["vector"] = true; 7242 } 7243 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7244 } 7245 7246 bool handleTargetFeatures(std::vector<std::string> &Features, 7247 DiagnosticsEngine &Diags) override { 7248 HasTransactionalExecution = false; 7249 for (const auto &Feature : Features) { 7250 if (Feature == "+transactional-execution") 7251 HasTransactionalExecution = true; 7252 else if (Feature == "+vector") 7253 HasVector = true; 7254 } 7255 // If we use the vector ABI, vector types are 64-bit aligned. 7256 if (HasVector) { 7257 MaxVectorAlign = 64; 7258 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7259 "-v128:64-a:8:16-n32:64"); 7260 } 7261 return true; 7262 } 7263 7264 bool hasFeature(StringRef Feature) const override { 7265 return llvm::StringSwitch<bool>(Feature) 7266 .Case("systemz", true) 7267 .Case("htm", HasTransactionalExecution) 7268 .Case("vx", HasVector) 7269 .Default(false); 7270 } 7271 7272 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7273 switch (CC) { 7274 case CC_C: 7275 case CC_Swift: 7276 return CCCR_OK; 7277 default: 7278 return CCCR_Warning; 7279 } 7280 } 7281 7282 StringRef getABI() const override { 7283 if (HasVector) 7284 return "vector"; 7285 return ""; 7286 } 7287 7288 bool useFloat128ManglingForLongDouble() const override { 7289 return true; 7290 } 7291 }; 7292 7293 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7294 #define BUILTIN(ID, TYPE, ATTRS) \ 7295 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7296 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7297 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7298 #include "clang/Basic/BuiltinsSystemZ.def" 7299 }; 7300 7301 const char *const SystemZTargetInfo::GCCRegNames[] = { 7302 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7303 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7304 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7305 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7306 }; 7307 7308 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7309 return llvm::makeArrayRef(GCCRegNames); 7310 } 7311 7312 bool SystemZTargetInfo:: 7313 validateAsmConstraint(const char *&Name, 7314 TargetInfo::ConstraintInfo &Info) const { 7315 switch (*Name) { 7316 default: 7317 return false; 7318 7319 case 'a': // Address register 7320 case 'd': // Data register (equivalent to 'r') 7321 case 'f': // Floating-point register 7322 Info.setAllowsRegister(); 7323 return true; 7324 7325 case 'I': // Unsigned 8-bit constant 7326 case 'J': // Unsigned 12-bit constant 7327 case 'K': // Signed 16-bit constant 7328 case 'L': // Signed 20-bit displacement (on all targets we support) 7329 case 'M': // 0x7fffffff 7330 return true; 7331 7332 case 'Q': // Memory with base and unsigned 12-bit displacement 7333 case 'R': // Likewise, plus an index 7334 case 'S': // Memory with base and signed 20-bit displacement 7335 case 'T': // Likewise, plus an index 7336 Info.setAllowsMemory(); 7337 return true; 7338 } 7339 } 7340 7341 class MSP430TargetInfo : public TargetInfo { 7342 static const char *const GCCRegNames[]; 7343 7344 public: 7345 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7346 : TargetInfo(Triple) { 7347 TLSSupported = false; 7348 IntWidth = 16; 7349 IntAlign = 16; 7350 LongWidth = 32; 7351 LongLongWidth = 64; 7352 LongAlign = LongLongAlign = 16; 7353 PointerWidth = 16; 7354 PointerAlign = 16; 7355 SuitableAlign = 16; 7356 SizeType = UnsignedInt; 7357 IntMaxType = SignedLongLong; 7358 IntPtrType = SignedInt; 7359 PtrDiffType = SignedInt; 7360 SigAtomicType = SignedLong; 7361 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7362 } 7363 void getTargetDefines(const LangOptions &Opts, 7364 MacroBuilder &Builder) const override { 7365 Builder.defineMacro("MSP430"); 7366 Builder.defineMacro("__MSP430__"); 7367 // FIXME: defines for different 'flavours' of MCU 7368 } 7369 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7370 // FIXME: Implement. 7371 return None; 7372 } 7373 bool hasFeature(StringRef Feature) const override { 7374 return Feature == "msp430"; 7375 } 7376 ArrayRef<const char *> getGCCRegNames() const override; 7377 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7378 // No aliases. 7379 return None; 7380 } 7381 bool validateAsmConstraint(const char *&Name, 7382 TargetInfo::ConstraintInfo &info) const override { 7383 // FIXME: implement 7384 switch (*Name) { 7385 case 'K': // the constant 1 7386 case 'L': // constant -1^20 .. 1^19 7387 case 'M': // constant 1-4: 7388 return true; 7389 } 7390 // No target constraints for now. 7391 return false; 7392 } 7393 const char *getClobbers() const override { 7394 // FIXME: Is this really right? 7395 return ""; 7396 } 7397 BuiltinVaListKind getBuiltinVaListKind() const override { 7398 // FIXME: implement 7399 return TargetInfo::CharPtrBuiltinVaList; 7400 } 7401 }; 7402 7403 const char *const MSP430TargetInfo::GCCRegNames[] = { 7404 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7405 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7406 7407 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7408 return llvm::makeArrayRef(GCCRegNames); 7409 } 7410 7411 // LLVM and Clang cannot be used directly to output native binaries for 7412 // target, but is used to compile C code to llvm bitcode with correct 7413 // type and alignment information. 7414 // 7415 // TCE uses the llvm bitcode as input and uses it for generating customized 7416 // target processor and program binary. TCE co-design environment is 7417 // publicly available in http://tce.cs.tut.fi 7418 7419 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7420 0, // Default 7421 3, // opencl_global 7422 4, // opencl_local 7423 5, // opencl_constant 7424 // FIXME: generic has to be added to the target 7425 0, // opencl_generic 7426 0, // cuda_device 7427 0, // cuda_constant 7428 0 // cuda_shared 7429 }; 7430 7431 class TCETargetInfo : public TargetInfo { 7432 public: 7433 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7434 : TargetInfo(Triple) { 7435 TLSSupported = false; 7436 IntWidth = 32; 7437 LongWidth = LongLongWidth = 32; 7438 PointerWidth = 32; 7439 IntAlign = 32; 7440 LongAlign = LongLongAlign = 32; 7441 PointerAlign = 32; 7442 SuitableAlign = 32; 7443 SizeType = UnsignedInt; 7444 IntMaxType = SignedLong; 7445 IntPtrType = SignedInt; 7446 PtrDiffType = SignedInt; 7447 FloatWidth = 32; 7448 FloatAlign = 32; 7449 DoubleWidth = 32; 7450 DoubleAlign = 32; 7451 LongDoubleWidth = 32; 7452 LongDoubleAlign = 32; 7453 FloatFormat = &llvm::APFloat::IEEEsingle(); 7454 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7455 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7456 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7457 "i16:16:32-i32:32:32-i64:32:32-" 7458 "f32:32:32-f64:32:32-v64:32:32-" 7459 "v128:32:32-v256:32:32-v512:32:32-" 7460 "v1024:32:32-a0:0:32-n32"); 7461 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7462 UseAddrSpaceMapMangling = true; 7463 } 7464 7465 void getTargetDefines(const LangOptions &Opts, 7466 MacroBuilder &Builder) const override { 7467 DefineStd(Builder, "tce", Opts); 7468 Builder.defineMacro("__TCE__"); 7469 Builder.defineMacro("__TCE_V1__"); 7470 } 7471 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7472 7473 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7474 const char *getClobbers() const override { return ""; } 7475 BuiltinVaListKind getBuiltinVaListKind() const override { 7476 return TargetInfo::VoidPtrBuiltinVaList; 7477 } 7478 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7479 bool validateAsmConstraint(const char *&Name, 7480 TargetInfo::ConstraintInfo &info) const override { 7481 return true; 7482 } 7483 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7484 return None; 7485 } 7486 }; 7487 7488 class TCELETargetInfo : public TCETargetInfo { 7489 public: 7490 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7491 : TCETargetInfo(Triple, Opts) { 7492 BigEndian = false; 7493 7494 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7495 "i16:16:32-i32:32:32-i64:32:32-" 7496 "f32:32:32-f64:32:32-v64:32:32-" 7497 "v128:32:32-v256:32:32-v512:32:32-" 7498 "v1024:32:32-a0:0:32-n32"); 7499 7500 } 7501 7502 virtual void getTargetDefines(const LangOptions &Opts, 7503 MacroBuilder &Builder) const { 7504 DefineStd(Builder, "tcele", Opts); 7505 Builder.defineMacro("__TCE__"); 7506 Builder.defineMacro("__TCE_V1__"); 7507 Builder.defineMacro("__TCELE__"); 7508 Builder.defineMacro("__TCELE_V1__"); 7509 } 7510 7511 }; 7512 7513 class BPFTargetInfo : public TargetInfo { 7514 public: 7515 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7516 : TargetInfo(Triple) { 7517 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7518 SizeType = UnsignedLong; 7519 PtrDiffType = SignedLong; 7520 IntPtrType = SignedLong; 7521 IntMaxType = SignedLong; 7522 Int64Type = SignedLong; 7523 RegParmMax = 5; 7524 if (Triple.getArch() == llvm::Triple::bpfeb) { 7525 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7526 } else { 7527 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7528 } 7529 MaxAtomicPromoteWidth = 64; 7530 MaxAtomicInlineWidth = 64; 7531 TLSSupported = false; 7532 } 7533 void getTargetDefines(const LangOptions &Opts, 7534 MacroBuilder &Builder) const override { 7535 DefineStd(Builder, "bpf", Opts); 7536 Builder.defineMacro("__BPF__"); 7537 } 7538 bool hasFeature(StringRef Feature) const override { 7539 return Feature == "bpf"; 7540 } 7541 7542 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7543 const char *getClobbers() const override { 7544 return ""; 7545 } 7546 BuiltinVaListKind getBuiltinVaListKind() const override { 7547 return TargetInfo::VoidPtrBuiltinVaList; 7548 } 7549 ArrayRef<const char *> getGCCRegNames() const override { 7550 return None; 7551 } 7552 bool validateAsmConstraint(const char *&Name, 7553 TargetInfo::ConstraintInfo &info) const override { 7554 return true; 7555 } 7556 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7557 return None; 7558 } 7559 }; 7560 7561 class MipsTargetInfo : public TargetInfo { 7562 void setDataLayout() { 7563 StringRef Layout; 7564 7565 if (ABI == "o32") 7566 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7567 else if (ABI == "n32") 7568 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7569 else if (ABI == "n64") 7570 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7571 else 7572 llvm_unreachable("Invalid ABI"); 7573 7574 if (BigEndian) 7575 resetDataLayout(("E-" + Layout).str()); 7576 else 7577 resetDataLayout(("e-" + Layout).str()); 7578 } 7579 7580 7581 static const Builtin::Info BuiltinInfo[]; 7582 std::string CPU; 7583 bool IsMips16; 7584 bool IsMicromips; 7585 bool IsNan2008; 7586 bool IsSingleFloat; 7587 bool IsNoABICalls; 7588 bool CanUseBSDABICalls; 7589 enum MipsFloatABI { 7590 HardFloat, SoftFloat 7591 } FloatABI; 7592 enum DspRevEnum { 7593 NoDSP, DSP1, DSP2 7594 } DspRev; 7595 bool HasMSA; 7596 7597 protected: 7598 bool HasFP64; 7599 std::string ABI; 7600 7601 public: 7602 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7603 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7604 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 7605 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 7606 HasMSA(false), HasFP64(false) { 7607 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7608 7609 setABI((getTriple().getArch() == llvm::Triple::mips || 7610 getTriple().getArch() == llvm::Triple::mipsel) 7611 ? "o32" 7612 : "n64"); 7613 7614 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7615 7616 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 7617 Triple.getOS() == llvm::Triple::OpenBSD; 7618 } 7619 7620 bool isNaN2008Default() const { 7621 return CPU == "mips32r6" || CPU == "mips64r6"; 7622 } 7623 7624 bool isFP64Default() const { 7625 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7626 } 7627 7628 bool isNan2008() const override { 7629 return IsNan2008; 7630 } 7631 7632 bool processorSupportsGPR64() const { 7633 return llvm::StringSwitch<bool>(CPU) 7634 .Case("mips3", true) 7635 .Case("mips4", true) 7636 .Case("mips5", true) 7637 .Case("mips64", true) 7638 .Case("mips64r2", true) 7639 .Case("mips64r3", true) 7640 .Case("mips64r5", true) 7641 .Case("mips64r6", true) 7642 .Case("octeon", true) 7643 .Default(false); 7644 return false; 7645 } 7646 7647 StringRef getABI() const override { return ABI; } 7648 bool setABI(const std::string &Name) override { 7649 if (Name == "o32") { 7650 setO32ABITypes(); 7651 ABI = Name; 7652 return true; 7653 } 7654 7655 if (Name == "n32") { 7656 setN32ABITypes(); 7657 ABI = Name; 7658 return true; 7659 } 7660 if (Name == "n64") { 7661 setN64ABITypes(); 7662 ABI = Name; 7663 return true; 7664 } 7665 return false; 7666 } 7667 7668 void setO32ABITypes() { 7669 Int64Type = SignedLongLong; 7670 IntMaxType = Int64Type; 7671 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7672 LongDoubleWidth = LongDoubleAlign = 64; 7673 LongWidth = LongAlign = 32; 7674 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7675 PointerWidth = PointerAlign = 32; 7676 PtrDiffType = SignedInt; 7677 SizeType = UnsignedInt; 7678 SuitableAlign = 64; 7679 } 7680 7681 void setN32N64ABITypes() { 7682 LongDoubleWidth = LongDoubleAlign = 128; 7683 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7684 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7685 LongDoubleWidth = LongDoubleAlign = 64; 7686 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7687 } 7688 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7689 SuitableAlign = 128; 7690 } 7691 7692 void setN64ABITypes() { 7693 setN32N64ABITypes(); 7694 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 7695 Int64Type = SignedLongLong; 7696 } else { 7697 Int64Type = SignedLong; 7698 } 7699 IntMaxType = Int64Type; 7700 LongWidth = LongAlign = 64; 7701 PointerWidth = PointerAlign = 64; 7702 PtrDiffType = SignedLong; 7703 SizeType = UnsignedLong; 7704 } 7705 7706 void setN32ABITypes() { 7707 setN32N64ABITypes(); 7708 Int64Type = SignedLongLong; 7709 IntMaxType = Int64Type; 7710 LongWidth = LongAlign = 32; 7711 PointerWidth = PointerAlign = 32; 7712 PtrDiffType = SignedInt; 7713 SizeType = UnsignedInt; 7714 } 7715 7716 bool setCPU(const std::string &Name) override { 7717 CPU = Name; 7718 return llvm::StringSwitch<bool>(Name) 7719 .Case("mips1", true) 7720 .Case("mips2", true) 7721 .Case("mips3", true) 7722 .Case("mips4", true) 7723 .Case("mips5", true) 7724 .Case("mips32", true) 7725 .Case("mips32r2", true) 7726 .Case("mips32r3", true) 7727 .Case("mips32r5", true) 7728 .Case("mips32r6", true) 7729 .Case("mips64", true) 7730 .Case("mips64r2", true) 7731 .Case("mips64r3", true) 7732 .Case("mips64r5", true) 7733 .Case("mips64r6", true) 7734 .Case("octeon", true) 7735 .Case("p5600", true) 7736 .Default(false); 7737 } 7738 const std::string& getCPU() const { return CPU; } 7739 bool 7740 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7741 StringRef CPU, 7742 const std::vector<std::string> &FeaturesVec) const override { 7743 if (CPU.empty()) 7744 CPU = getCPU(); 7745 if (CPU == "octeon") 7746 Features["mips64r2"] = Features["cnmips"] = true; 7747 else 7748 Features[CPU] = true; 7749 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7750 } 7751 7752 void getTargetDefines(const LangOptions &Opts, 7753 MacroBuilder &Builder) const override { 7754 if (BigEndian) { 7755 DefineStd(Builder, "MIPSEB", Opts); 7756 Builder.defineMacro("_MIPSEB"); 7757 } else { 7758 DefineStd(Builder, "MIPSEL", Opts); 7759 Builder.defineMacro("_MIPSEL"); 7760 } 7761 7762 Builder.defineMacro("__mips__"); 7763 Builder.defineMacro("_mips"); 7764 if (Opts.GNUMode) 7765 Builder.defineMacro("mips"); 7766 7767 if (ABI == "o32") { 7768 Builder.defineMacro("__mips", "32"); 7769 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7770 } else { 7771 Builder.defineMacro("__mips", "64"); 7772 Builder.defineMacro("__mips64"); 7773 Builder.defineMacro("__mips64__"); 7774 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7775 } 7776 7777 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7778 .Cases("mips32", "mips64", "1") 7779 .Cases("mips32r2", "mips64r2", "2") 7780 .Cases("mips32r3", "mips64r3", "3") 7781 .Cases("mips32r5", "mips64r5", "5") 7782 .Cases("mips32r6", "mips64r6", "6") 7783 .Default(""); 7784 if (!ISARev.empty()) 7785 Builder.defineMacro("__mips_isa_rev", ISARev); 7786 7787 if (ABI == "o32") { 7788 Builder.defineMacro("__mips_o32"); 7789 Builder.defineMacro("_ABIO32", "1"); 7790 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7791 } else if (ABI == "n32") { 7792 Builder.defineMacro("__mips_n32"); 7793 Builder.defineMacro("_ABIN32", "2"); 7794 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7795 } else if (ABI == "n64") { 7796 Builder.defineMacro("__mips_n64"); 7797 Builder.defineMacro("_ABI64", "3"); 7798 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7799 } else 7800 llvm_unreachable("Invalid ABI."); 7801 7802 if (!IsNoABICalls) { 7803 Builder.defineMacro("__mips_abicalls"); 7804 if (CanUseBSDABICalls) 7805 Builder.defineMacro("__ABICALLS__"); 7806 } 7807 7808 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7809 7810 switch (FloatABI) { 7811 case HardFloat: 7812 Builder.defineMacro("__mips_hard_float", Twine(1)); 7813 break; 7814 case SoftFloat: 7815 Builder.defineMacro("__mips_soft_float", Twine(1)); 7816 break; 7817 } 7818 7819 if (IsSingleFloat) 7820 Builder.defineMacro("__mips_single_float", Twine(1)); 7821 7822 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7823 Builder.defineMacro("_MIPS_FPSET", 7824 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7825 7826 if (IsMips16) 7827 Builder.defineMacro("__mips16", Twine(1)); 7828 7829 if (IsMicromips) 7830 Builder.defineMacro("__mips_micromips", Twine(1)); 7831 7832 if (IsNan2008) 7833 Builder.defineMacro("__mips_nan2008", Twine(1)); 7834 7835 switch (DspRev) { 7836 default: 7837 break; 7838 case DSP1: 7839 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7840 Builder.defineMacro("__mips_dsp", Twine(1)); 7841 break; 7842 case DSP2: 7843 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7844 Builder.defineMacro("__mips_dspr2", Twine(1)); 7845 Builder.defineMacro("__mips_dsp", Twine(1)); 7846 break; 7847 } 7848 7849 if (HasMSA) 7850 Builder.defineMacro("__mips_msa", Twine(1)); 7851 7852 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7853 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7854 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7855 7856 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7857 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7858 7859 // These shouldn't be defined for MIPS-I but there's no need to check 7860 // for that since MIPS-I isn't supported. 7861 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7862 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7863 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7864 7865 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7866 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7867 // the instructions exist but using them violates the ABI since they 7868 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7869 if (ABI == "n32" || ABI == "n64") 7870 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7871 } 7872 7873 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7874 return llvm::makeArrayRef(BuiltinInfo, 7875 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7876 } 7877 bool hasFeature(StringRef Feature) const override { 7878 return llvm::StringSwitch<bool>(Feature) 7879 .Case("mips", true) 7880 .Case("fp64", HasFP64) 7881 .Default(false); 7882 } 7883 BuiltinVaListKind getBuiltinVaListKind() const override { 7884 return TargetInfo::VoidPtrBuiltinVaList; 7885 } 7886 ArrayRef<const char *> getGCCRegNames() const override { 7887 static const char *const GCCRegNames[] = { 7888 // CPU register names 7889 // Must match second column of GCCRegAliases 7890 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7891 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7892 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7893 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7894 // Floating point register names 7895 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7896 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7897 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7898 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7899 // Hi/lo and condition register names 7900 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7901 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7902 "$ac3hi","$ac3lo", 7903 // MSA register names 7904 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7905 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7906 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7907 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7908 // MSA control register names 7909 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7910 "$msarequest", "$msamap", "$msaunmap" 7911 }; 7912 return llvm::makeArrayRef(GCCRegNames); 7913 } 7914 bool validateAsmConstraint(const char *&Name, 7915 TargetInfo::ConstraintInfo &Info) const override { 7916 switch (*Name) { 7917 default: 7918 return false; 7919 case 'r': // CPU registers. 7920 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7921 case 'y': // Equivalent to "r", backward compatibility only. 7922 case 'f': // floating-point registers. 7923 case 'c': // $25 for indirect jumps 7924 case 'l': // lo register 7925 case 'x': // hilo register pair 7926 Info.setAllowsRegister(); 7927 return true; 7928 case 'I': // Signed 16-bit constant 7929 case 'J': // Integer 0 7930 case 'K': // Unsigned 16-bit constant 7931 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7932 case 'M': // Constants not loadable via lui, addiu, or ori 7933 case 'N': // Constant -1 to -65535 7934 case 'O': // A signed 15-bit constant 7935 case 'P': // A constant between 1 go 65535 7936 return true; 7937 case 'R': // An address that can be used in a non-macro load or store 7938 Info.setAllowsMemory(); 7939 return true; 7940 case 'Z': 7941 if (Name[1] == 'C') { // An address usable by ll, and sc. 7942 Info.setAllowsMemory(); 7943 Name++; // Skip over 'Z'. 7944 return true; 7945 } 7946 return false; 7947 } 7948 } 7949 7950 std::string convertConstraint(const char *&Constraint) const override { 7951 std::string R; 7952 switch (*Constraint) { 7953 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7954 if (Constraint[1] == 'C') { 7955 R = std::string("^") + std::string(Constraint, 2); 7956 Constraint++; 7957 return R; 7958 } 7959 break; 7960 } 7961 return TargetInfo::convertConstraint(Constraint); 7962 } 7963 7964 const char *getClobbers() const override { 7965 // In GCC, $1 is not widely used in generated code (it's used only in a few 7966 // specific situations), so there is no real need for users to add it to 7967 // the clobbers list if they want to use it in their inline assembly code. 7968 // 7969 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7970 // code generation, so using it in inline assembly without adding it to the 7971 // clobbers list can cause conflicts between the inline assembly code and 7972 // the surrounding generated code. 7973 // 7974 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7975 // operands, which will conflict with the ".set at" assembler option (which 7976 // we use only for inline assembly, in order to maintain compatibility with 7977 // GCC) and will also conflict with the user's usage of $1. 7978 // 7979 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7980 // register for generated code is to automatically clobber $1 for all inline 7981 // assembly code. 7982 // 7983 // FIXME: We should automatically clobber $1 only for inline assembly code 7984 // which actually uses it. This would allow LLVM to use $1 for inline 7985 // assembly operands if the user's assembly code doesn't use it. 7986 return "~{$1}"; 7987 } 7988 7989 bool handleTargetFeatures(std::vector<std::string> &Features, 7990 DiagnosticsEngine &Diags) override { 7991 IsMips16 = false; 7992 IsMicromips = false; 7993 IsNan2008 = isNaN2008Default(); 7994 IsSingleFloat = false; 7995 FloatABI = HardFloat; 7996 DspRev = NoDSP; 7997 HasFP64 = isFP64Default(); 7998 7999 for (const auto &Feature : Features) { 8000 if (Feature == "+single-float") 8001 IsSingleFloat = true; 8002 else if (Feature == "+soft-float") 8003 FloatABI = SoftFloat; 8004 else if (Feature == "+mips16") 8005 IsMips16 = true; 8006 else if (Feature == "+micromips") 8007 IsMicromips = true; 8008 else if (Feature == "+dsp") 8009 DspRev = std::max(DspRev, DSP1); 8010 else if (Feature == "+dspr2") 8011 DspRev = std::max(DspRev, DSP2); 8012 else if (Feature == "+msa") 8013 HasMSA = true; 8014 else if (Feature == "+fp64") 8015 HasFP64 = true; 8016 else if (Feature == "-fp64") 8017 HasFP64 = false; 8018 else if (Feature == "+nan2008") 8019 IsNan2008 = true; 8020 else if (Feature == "-nan2008") 8021 IsNan2008 = false; 8022 else if (Feature == "+noabicalls") 8023 IsNoABICalls = true; 8024 } 8025 8026 setDataLayout(); 8027 8028 return true; 8029 } 8030 8031 int getEHDataRegisterNumber(unsigned RegNo) const override { 8032 if (RegNo == 0) return 4; 8033 if (RegNo == 1) return 5; 8034 return -1; 8035 } 8036 8037 bool isCLZForZeroUndef() const override { return false; } 8038 8039 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8040 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 8041 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8042 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8043 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 8044 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 8045 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 8046 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8047 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8048 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8049 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8050 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8051 {{"ra"}, "$31"}}; 8052 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 8053 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8054 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8055 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 8056 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 8057 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 8058 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8059 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8060 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8061 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8062 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8063 {{"ra"}, "$31"}}; 8064 if (ABI == "o32") 8065 return llvm::makeArrayRef(O32RegAliases); 8066 return llvm::makeArrayRef(NewABIRegAliases); 8067 } 8068 8069 bool hasInt128Type() const override { 8070 return ABI == "n32" || ABI == "n64"; 8071 } 8072 8073 bool validateTarget(DiagnosticsEngine &Diags) const override { 8074 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 8075 // this yet. It's better to fail here than on the backend assertion. 8076 if (processorSupportsGPR64() && ABI == "o32") { 8077 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8078 return false; 8079 } 8080 8081 // 64-bit ABI's require 64-bit CPU's. 8082 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 8083 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8084 return false; 8085 } 8086 8087 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 8088 // can't handle this yet. It's better to fail here than on the 8089 // backend assertion. 8090 if ((getTriple().getArch() == llvm::Triple::mips64 || 8091 getTriple().getArch() == llvm::Triple::mips64el) && 8092 ABI == "o32") { 8093 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8094 << ABI << getTriple().str(); 8095 return false; 8096 } 8097 8098 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 8099 // can't handle this yet. It's better to fail here than on the 8100 // backend assertion. 8101 if ((getTriple().getArch() == llvm::Triple::mips || 8102 getTriple().getArch() == llvm::Triple::mipsel) && 8103 (ABI == "n32" || ABI == "n64")) { 8104 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8105 << ABI << getTriple().str(); 8106 return false; 8107 } 8108 8109 return true; 8110 } 8111 }; 8112 8113 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 8114 #define BUILTIN(ID, TYPE, ATTRS) \ 8115 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8116 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8117 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8118 #include "clang/Basic/BuiltinsMips.def" 8119 }; 8120 8121 class PNaClTargetInfo : public TargetInfo { 8122 public: 8123 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8124 : TargetInfo(Triple) { 8125 this->LongAlign = 32; 8126 this->LongWidth = 32; 8127 this->PointerAlign = 32; 8128 this->PointerWidth = 32; 8129 this->IntMaxType = TargetInfo::SignedLongLong; 8130 this->Int64Type = TargetInfo::SignedLongLong; 8131 this->DoubleAlign = 64; 8132 this->LongDoubleWidth = 64; 8133 this->LongDoubleAlign = 64; 8134 this->SizeType = TargetInfo::UnsignedInt; 8135 this->PtrDiffType = TargetInfo::SignedInt; 8136 this->IntPtrType = TargetInfo::SignedInt; 8137 this->RegParmMax = 0; // Disallow regparm 8138 } 8139 8140 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8141 Builder.defineMacro("__le32__"); 8142 Builder.defineMacro("__pnacl__"); 8143 } 8144 void getTargetDefines(const LangOptions &Opts, 8145 MacroBuilder &Builder) const override { 8146 getArchDefines(Opts, Builder); 8147 } 8148 bool hasFeature(StringRef Feature) const override { 8149 return Feature == "pnacl"; 8150 } 8151 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8152 BuiltinVaListKind getBuiltinVaListKind() const override { 8153 return TargetInfo::PNaClABIBuiltinVaList; 8154 } 8155 ArrayRef<const char *> getGCCRegNames() const override; 8156 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8157 bool validateAsmConstraint(const char *&Name, 8158 TargetInfo::ConstraintInfo &Info) const override { 8159 return false; 8160 } 8161 8162 const char *getClobbers() const override { 8163 return ""; 8164 } 8165 }; 8166 8167 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8168 return None; 8169 } 8170 8171 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8172 return None; 8173 } 8174 8175 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8176 class NaClMips32TargetInfo : public MipsTargetInfo { 8177 public: 8178 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8179 : MipsTargetInfo(Triple, Opts) {} 8180 8181 BuiltinVaListKind getBuiltinVaListKind() const override { 8182 return TargetInfo::PNaClABIBuiltinVaList; 8183 } 8184 }; 8185 8186 class Le64TargetInfo : public TargetInfo { 8187 static const Builtin::Info BuiltinInfo[]; 8188 8189 public: 8190 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8191 : TargetInfo(Triple) { 8192 NoAsmVariants = true; 8193 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8194 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8195 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8196 } 8197 8198 void getTargetDefines(const LangOptions &Opts, 8199 MacroBuilder &Builder) const override { 8200 DefineStd(Builder, "unix", Opts); 8201 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8202 Builder.defineMacro("__ELF__"); 8203 } 8204 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8205 return llvm::makeArrayRef(BuiltinInfo, 8206 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8207 } 8208 BuiltinVaListKind getBuiltinVaListKind() const override { 8209 return TargetInfo::PNaClABIBuiltinVaList; 8210 } 8211 const char *getClobbers() const override { return ""; } 8212 ArrayRef<const char *> getGCCRegNames() const override { 8213 return None; 8214 } 8215 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8216 return None; 8217 } 8218 bool validateAsmConstraint(const char *&Name, 8219 TargetInfo::ConstraintInfo &Info) const override { 8220 return false; 8221 } 8222 8223 bool hasProtectedVisibility() const override { return false; } 8224 }; 8225 8226 class WebAssemblyTargetInfo : public TargetInfo { 8227 static const Builtin::Info BuiltinInfo[]; 8228 8229 enum SIMDEnum { 8230 NoSIMD, 8231 SIMD128, 8232 } SIMDLevel; 8233 8234 public: 8235 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8236 : TargetInfo(T), SIMDLevel(NoSIMD) { 8237 NoAsmVariants = true; 8238 SuitableAlign = 128; 8239 LargeArrayMinWidth = 128; 8240 LargeArrayAlign = 128; 8241 SimdDefaultAlign = 128; 8242 SigAtomicType = SignedLong; 8243 LongDoubleWidth = LongDoubleAlign = 128; 8244 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8245 SizeType = UnsignedInt; 8246 PtrDiffType = SignedInt; 8247 IntPtrType = SignedInt; 8248 } 8249 8250 protected: 8251 void getTargetDefines(const LangOptions &Opts, 8252 MacroBuilder &Builder) const override { 8253 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8254 if (SIMDLevel >= SIMD128) 8255 Builder.defineMacro("__wasm_simd128__"); 8256 } 8257 8258 private: 8259 bool 8260 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8261 StringRef CPU, 8262 const std::vector<std::string> &FeaturesVec) const override { 8263 if (CPU == "bleeding-edge") 8264 Features["simd128"] = true; 8265 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8266 } 8267 bool hasFeature(StringRef Feature) const final { 8268 return llvm::StringSwitch<bool>(Feature) 8269 .Case("simd128", SIMDLevel >= SIMD128) 8270 .Default(false); 8271 } 8272 bool handleTargetFeatures(std::vector<std::string> &Features, 8273 DiagnosticsEngine &Diags) final { 8274 for (const auto &Feature : Features) { 8275 if (Feature == "+simd128") { 8276 SIMDLevel = std::max(SIMDLevel, SIMD128); 8277 continue; 8278 } 8279 if (Feature == "-simd128") { 8280 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8281 continue; 8282 } 8283 8284 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8285 << "-target-feature"; 8286 return false; 8287 } 8288 return true; 8289 } 8290 bool setCPU(const std::string &Name) final { 8291 return llvm::StringSwitch<bool>(Name) 8292 .Case("mvp", true) 8293 .Case("bleeding-edge", true) 8294 .Case("generic", true) 8295 .Default(false); 8296 } 8297 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8298 return llvm::makeArrayRef(BuiltinInfo, 8299 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8300 } 8301 BuiltinVaListKind getBuiltinVaListKind() const final { 8302 return VoidPtrBuiltinVaList; 8303 } 8304 ArrayRef<const char *> getGCCRegNames() const final { 8305 return None; 8306 } 8307 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8308 return None; 8309 } 8310 bool 8311 validateAsmConstraint(const char *&Name, 8312 TargetInfo::ConstraintInfo &Info) const final { 8313 return false; 8314 } 8315 const char *getClobbers() const final { return ""; } 8316 bool isCLZForZeroUndef() const final { return false; } 8317 bool hasInt128Type() const final { return true; } 8318 IntType getIntTypeByWidth(unsigned BitWidth, 8319 bool IsSigned) const final { 8320 // WebAssembly prefers long long for explicitly 64-bit integers. 8321 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8322 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8323 } 8324 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8325 bool IsSigned) const final { 8326 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8327 return BitWidth == 64 8328 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8329 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8330 } 8331 }; 8332 8333 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8334 #define BUILTIN(ID, TYPE, ATTRS) \ 8335 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8336 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8337 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8338 #include "clang/Basic/BuiltinsWebAssembly.def" 8339 }; 8340 8341 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8342 public: 8343 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8344 const TargetOptions &Opts) 8345 : WebAssemblyTargetInfo(T, Opts) { 8346 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8347 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8348 } 8349 8350 protected: 8351 void getTargetDefines(const LangOptions &Opts, 8352 MacroBuilder &Builder) const override { 8353 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8354 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8355 } 8356 }; 8357 8358 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8359 public: 8360 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8361 const TargetOptions &Opts) 8362 : WebAssemblyTargetInfo(T, Opts) { 8363 LongAlign = LongWidth = 64; 8364 PointerAlign = PointerWidth = 64; 8365 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8366 SizeType = UnsignedLong; 8367 PtrDiffType = SignedLong; 8368 IntPtrType = SignedLong; 8369 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8370 } 8371 8372 protected: 8373 void getTargetDefines(const LangOptions &Opts, 8374 MacroBuilder &Builder) const override { 8375 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8376 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8377 } 8378 }; 8379 8380 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8381 #define BUILTIN(ID, TYPE, ATTRS) \ 8382 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8383 #include "clang/Basic/BuiltinsLe64.def" 8384 }; 8385 8386 static const unsigned SPIRAddrSpaceMap[] = { 8387 0, // Default 8388 1, // opencl_global 8389 3, // opencl_local 8390 2, // opencl_constant 8391 4, // opencl_generic 8392 0, // cuda_device 8393 0, // cuda_constant 8394 0 // cuda_shared 8395 }; 8396 class SPIRTargetInfo : public TargetInfo { 8397 public: 8398 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8399 : TargetInfo(Triple) { 8400 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8401 "SPIR target must use unknown OS"); 8402 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8403 "SPIR target must use unknown environment type"); 8404 TLSSupported = false; 8405 LongWidth = LongAlign = 64; 8406 AddrSpaceMap = &SPIRAddrSpaceMap; 8407 UseAddrSpaceMapMangling = true; 8408 // Define available target features 8409 // These must be defined in sorted order! 8410 NoAsmVariants = true; 8411 } 8412 void getTargetDefines(const LangOptions &Opts, 8413 MacroBuilder &Builder) const override { 8414 DefineStd(Builder, "SPIR", Opts); 8415 } 8416 bool hasFeature(StringRef Feature) const override { 8417 return Feature == "spir"; 8418 } 8419 8420 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8421 const char *getClobbers() const override { return ""; } 8422 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8423 bool validateAsmConstraint(const char *&Name, 8424 TargetInfo::ConstraintInfo &info) const override { 8425 return true; 8426 } 8427 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8428 return None; 8429 } 8430 BuiltinVaListKind getBuiltinVaListKind() const override { 8431 return TargetInfo::VoidPtrBuiltinVaList; 8432 } 8433 8434 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8435 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8436 : CCCR_Warning; 8437 } 8438 8439 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8440 return CC_SpirFunction; 8441 } 8442 8443 void setSupportedOpenCLOpts() override { 8444 // Assume all OpenCL extensions and optional core features are supported 8445 // for SPIR since it is a generic target. 8446 getSupportedOpenCLOpts().supportAll(); 8447 } 8448 }; 8449 8450 class SPIR32TargetInfo : public SPIRTargetInfo { 8451 public: 8452 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8453 : SPIRTargetInfo(Triple, Opts) { 8454 PointerWidth = PointerAlign = 32; 8455 SizeType = TargetInfo::UnsignedInt; 8456 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8457 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8458 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8459 } 8460 void getTargetDefines(const LangOptions &Opts, 8461 MacroBuilder &Builder) const override { 8462 DefineStd(Builder, "SPIR32", Opts); 8463 } 8464 }; 8465 8466 class SPIR64TargetInfo : public SPIRTargetInfo { 8467 public: 8468 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8469 : SPIRTargetInfo(Triple, Opts) { 8470 PointerWidth = PointerAlign = 64; 8471 SizeType = TargetInfo::UnsignedLong; 8472 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8473 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8474 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8475 } 8476 void getTargetDefines(const LangOptions &Opts, 8477 MacroBuilder &Builder) const override { 8478 DefineStd(Builder, "SPIR64", Opts); 8479 } 8480 }; 8481 8482 class XCoreTargetInfo : public TargetInfo { 8483 static const Builtin::Info BuiltinInfo[]; 8484 public: 8485 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8486 : TargetInfo(Triple) { 8487 NoAsmVariants = true; 8488 LongLongAlign = 32; 8489 SuitableAlign = 32; 8490 DoubleAlign = LongDoubleAlign = 32; 8491 SizeType = UnsignedInt; 8492 PtrDiffType = SignedInt; 8493 IntPtrType = SignedInt; 8494 WCharType = UnsignedChar; 8495 WIntType = UnsignedInt; 8496 UseZeroLengthBitfieldAlignment = true; 8497 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8498 "-f64:32-a:0:32-n32"); 8499 } 8500 void getTargetDefines(const LangOptions &Opts, 8501 MacroBuilder &Builder) const override { 8502 Builder.defineMacro("__XS1B__"); 8503 } 8504 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8505 return llvm::makeArrayRef(BuiltinInfo, 8506 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8507 } 8508 BuiltinVaListKind getBuiltinVaListKind() const override { 8509 return TargetInfo::VoidPtrBuiltinVaList; 8510 } 8511 const char *getClobbers() const override { 8512 return ""; 8513 } 8514 ArrayRef<const char *> getGCCRegNames() const override { 8515 static const char * const GCCRegNames[] = { 8516 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8517 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8518 }; 8519 return llvm::makeArrayRef(GCCRegNames); 8520 } 8521 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8522 return None; 8523 } 8524 bool validateAsmConstraint(const char *&Name, 8525 TargetInfo::ConstraintInfo &Info) const override { 8526 return false; 8527 } 8528 int getEHDataRegisterNumber(unsigned RegNo) const override { 8529 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8530 return (RegNo < 2)? RegNo : -1; 8531 } 8532 bool allowsLargerPreferedTypeAlignment() const override { 8533 return false; 8534 } 8535 }; 8536 8537 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8538 #define BUILTIN(ID, TYPE, ATTRS) \ 8539 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8540 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8541 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8542 #include "clang/Basic/BuiltinsXCore.def" 8543 }; 8544 8545 // x86_32 Android target 8546 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8547 public: 8548 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8549 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8550 SuitableAlign = 32; 8551 LongDoubleWidth = 64; 8552 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8553 } 8554 }; 8555 8556 // x86_64 Android target 8557 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8558 public: 8559 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8560 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8561 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8562 } 8563 8564 bool useFloat128ManglingForLongDouble() const override { 8565 return true; 8566 } 8567 }; 8568 8569 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8570 class RenderScript32TargetInfo : public ARMleTargetInfo { 8571 public: 8572 RenderScript32TargetInfo(const llvm::Triple &Triple, 8573 const TargetOptions &Opts) 8574 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8575 Triple.getOSName(), 8576 Triple.getEnvironmentName()), 8577 Opts) { 8578 IsRenderScriptTarget = true; 8579 LongWidth = LongAlign = 64; 8580 } 8581 void getTargetDefines(const LangOptions &Opts, 8582 MacroBuilder &Builder) const override { 8583 Builder.defineMacro("__RENDERSCRIPT__"); 8584 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8585 } 8586 }; 8587 8588 // 64-bit RenderScript is aarch64 8589 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8590 public: 8591 RenderScript64TargetInfo(const llvm::Triple &Triple, 8592 const TargetOptions &Opts) 8593 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8594 Triple.getOSName(), 8595 Triple.getEnvironmentName()), 8596 Opts) { 8597 IsRenderScriptTarget = true; 8598 } 8599 8600 void getTargetDefines(const LangOptions &Opts, 8601 MacroBuilder &Builder) const override { 8602 Builder.defineMacro("__RENDERSCRIPT__"); 8603 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8604 } 8605 }; 8606 8607 /// Information about a specific microcontroller. 8608 struct MCUInfo { 8609 const char *Name; 8610 const char *DefineName; 8611 }; 8612 8613 // This list should be kept up-to-date with AVRDevices.td in LLVM. 8614 static ArrayRef<MCUInfo> AVRMcus = { 8615 { "at90s1200", "__AVR_AT90S1200__" }, 8616 { "attiny11", "__AVR_ATtiny11__" }, 8617 { "attiny12", "__AVR_ATtiny12__" }, 8618 { "attiny15", "__AVR_ATtiny15__" }, 8619 { "attiny28", "__AVR_ATtiny28__" }, 8620 { "at90s2313", "__AVR_AT90S2313__" }, 8621 { "at90s2323", "__AVR_AT90S2323__" }, 8622 { "at90s2333", "__AVR_AT90S2333__" }, 8623 { "at90s2343", "__AVR_AT90S2343__" }, 8624 { "attiny22", "__AVR_ATtiny22__" }, 8625 { "attiny26", "__AVR_ATtiny26__" }, 8626 { "at86rf401", "__AVR_AT86RF401__" }, 8627 { "at90s4414", "__AVR_AT90S4414__" }, 8628 { "at90s4433", "__AVR_AT90S4433__" }, 8629 { "at90s4434", "__AVR_AT90S4434__" }, 8630 { "at90s8515", "__AVR_AT90S8515__" }, 8631 { "at90c8534", "__AVR_AT90c8534__" }, 8632 { "at90s8535", "__AVR_AT90S8535__" }, 8633 { "ata5272", "__AVR_ATA5272__" }, 8634 { "attiny13", "__AVR_ATtiny13__" }, 8635 { "attiny13a", "__AVR_ATtiny13A__" }, 8636 { "attiny2313", "__AVR_ATtiny2313__" }, 8637 { "attiny2313a", "__AVR_ATtiny2313A__" }, 8638 { "attiny24", "__AVR_ATtiny24__" }, 8639 { "attiny24a", "__AVR_ATtiny24A__" }, 8640 { "attiny4313", "__AVR_ATtiny4313__" }, 8641 { "attiny44", "__AVR_ATtiny44__" }, 8642 { "attiny44a", "__AVR_ATtiny44A__" }, 8643 { "attiny84", "__AVR_ATtiny84__" }, 8644 { "attiny84a", "__AVR_ATtiny84A__" }, 8645 { "attiny25", "__AVR_ATtiny25__" }, 8646 { "attiny45", "__AVR_ATtiny45__" }, 8647 { "attiny85", "__AVR_ATtiny85__" }, 8648 { "attiny261", "__AVR_ATtiny261__" }, 8649 { "attiny261a", "__AVR_ATtiny261A__" }, 8650 { "attiny461", "__AVR_ATtiny461__" }, 8651 { "attiny461a", "__AVR_ATtiny461A__" }, 8652 { "attiny861", "__AVR_ATtiny861__" }, 8653 { "attiny861a", "__AVR_ATtiny861A__" }, 8654 { "attiny87", "__AVR_ATtiny87__" }, 8655 { "attiny43u", "__AVR_ATtiny43U__" }, 8656 { "attiny48", "__AVR_ATtiny48__" }, 8657 { "attiny88", "__AVR_ATtiny88__" }, 8658 { "attiny828", "__AVR_ATtiny828__" }, 8659 { "at43usb355", "__AVR_AT43USB355__" }, 8660 { "at76c711", "__AVR_AT76C711__" }, 8661 { "atmega103", "__AVR_ATmega103__" }, 8662 { "at43usb320", "__AVR_AT43USB320__" }, 8663 { "attiny167", "__AVR_ATtiny167__" }, 8664 { "at90usb82", "__AVR_AT90USB82__" }, 8665 { "at90usb162", "__AVR_AT90USB162__" }, 8666 { "ata5505", "__AVR_ATA5505__" }, 8667 { "atmega8u2", "__AVR_ATmega8U2__" }, 8668 { "atmega16u2", "__AVR_ATmega16U2__" }, 8669 { "atmega32u2", "__AVR_ATmega32U2__" }, 8670 { "attiny1634", "__AVR_ATtiny1634__" }, 8671 { "atmega8", "__AVR_ATmega8__" }, 8672 { "ata6289", "__AVR_ATA6289__" }, 8673 { "atmega8a", "__AVR_ATmega8A__" }, 8674 { "ata6285", "__AVR_ATA6285__" }, 8675 { "ata6286", "__AVR_ATA6286__" }, 8676 { "atmega48", "__AVR_ATmega48__" }, 8677 { "atmega48a", "__AVR_ATmega48A__" }, 8678 { "atmega48pa", "__AVR_ATmega48PA__" }, 8679 { "atmega48p", "__AVR_ATmega48P__" }, 8680 { "atmega88", "__AVR_ATmega88__" }, 8681 { "atmega88a", "__AVR_ATmega88A__" }, 8682 { "atmega88p", "__AVR_ATmega88P__" }, 8683 { "atmega88pa", "__AVR_ATmega88PA__" }, 8684 { "atmega8515", "__AVR_ATmega8515__" }, 8685 { "atmega8535", "__AVR_ATmega8535__" }, 8686 { "atmega8hva", "__AVR_ATmega8HVA__" }, 8687 { "at90pwm1", "__AVR_AT90PWM1__" }, 8688 { "at90pwm2", "__AVR_AT90PWM2__" }, 8689 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 8690 { "at90pwm3", "__AVR_AT90PWM3__" }, 8691 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 8692 { "at90pwm81", "__AVR_AT90PWM81__" }, 8693 { "ata5790", "__AVR_ATA5790__" }, 8694 { "ata5795", "__AVR_ATA5795__" }, 8695 { "atmega16", "__AVR_ATmega16__" }, 8696 { "atmega16a", "__AVR_ATmega16A__" }, 8697 { "atmega161", "__AVR_ATmega161__" }, 8698 { "atmega162", "__AVR_ATmega162__" }, 8699 { "atmega163", "__AVR_ATmega163__" }, 8700 { "atmega164a", "__AVR_ATmega164A__" }, 8701 { "atmega164p", "__AVR_ATmega164P__" }, 8702 { "atmega164pa", "__AVR_ATmega164PA__" }, 8703 { "atmega165", "__AVR_ATmega165__" }, 8704 { "atmega165a", "__AVR_ATmega165A__" }, 8705 { "atmega165p", "__AVR_ATmega165P__" }, 8706 { "atmega165pa", "__AVR_ATmega165PA__" }, 8707 { "atmega168", "__AVR_ATmega168__" }, 8708 { "atmega168a", "__AVR_ATmega168A__" }, 8709 { "atmega168p", "__AVR_ATmega168P__" }, 8710 { "atmega168pa", "__AVR_ATmega168PA__" }, 8711 { "atmega169", "__AVR_ATmega169__" }, 8712 { "atmega169a", "__AVR_ATmega169A__" }, 8713 { "atmega169p", "__AVR_ATmega169P__" }, 8714 { "atmega169pa", "__AVR_ATmega169PA__" }, 8715 { "atmega32", "__AVR_ATmega32__" }, 8716 { "atmega32a", "__AVR_ATmega32A__" }, 8717 { "atmega323", "__AVR_ATmega323__" }, 8718 { "atmega324a", "__AVR_ATmega324A__" }, 8719 { "atmega324p", "__AVR_ATmega324P__" }, 8720 { "atmega324pa", "__AVR_ATmega324PA__" }, 8721 { "atmega325", "__AVR_ATmega325__" }, 8722 { "atmega325a", "__AVR_ATmega325A__" }, 8723 { "atmega325p", "__AVR_ATmega325P__" }, 8724 { "atmega325pa", "__AVR_ATmega325PA__" }, 8725 { "atmega3250", "__AVR_ATmega3250__" }, 8726 { "atmega3250a", "__AVR_ATmega3250A__" }, 8727 { "atmega3250p", "__AVR_ATmega3250P__" }, 8728 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 8729 { "atmega328", "__AVR_ATmega328__" }, 8730 { "atmega328p", "__AVR_ATmega328P__" }, 8731 { "atmega329", "__AVR_ATmega329__" }, 8732 { "atmega329a", "__AVR_ATmega329A__" }, 8733 { "atmega329p", "__AVR_ATmega329P__" }, 8734 { "atmega329pa", "__AVR_ATmega329PA__" }, 8735 { "atmega3290", "__AVR_ATmega3290__" }, 8736 { "atmega3290a", "__AVR_ATmega3290A__" }, 8737 { "atmega3290p", "__AVR_ATmega3290P__" }, 8738 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 8739 { "atmega406", "__AVR_ATmega406__" }, 8740 { "atmega64", "__AVR_ATmega64__" }, 8741 { "atmega64a", "__AVR_ATmega64A__" }, 8742 { "atmega640", "__AVR_ATmega640__" }, 8743 { "atmega644", "__AVR_ATmega644__" }, 8744 { "atmega644a", "__AVR_ATmega644A__" }, 8745 { "atmega644p", "__AVR_ATmega644P__" }, 8746 { "atmega644pa", "__AVR_ATmega644PA__" }, 8747 { "atmega645", "__AVR_ATmega645__" }, 8748 { "atmega645a", "__AVR_ATmega645A__" }, 8749 { "atmega645p", "__AVR_ATmega645P__" }, 8750 { "atmega649", "__AVR_ATmega649__" }, 8751 { "atmega649a", "__AVR_ATmega649A__" }, 8752 { "atmega649p", "__AVR_ATmega649P__" }, 8753 { "atmega6450", "__AVR_ATmega6450__" }, 8754 { "atmega6450a", "__AVR_ATmega6450A__" }, 8755 { "atmega6450p", "__AVR_ATmega6450P__" }, 8756 { "atmega6490", "__AVR_ATmega6490__" }, 8757 { "atmega6490a", "__AVR_ATmega6490A__" }, 8758 { "atmega6490p", "__AVR_ATmega6490P__" }, 8759 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 8760 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 8761 { "atmega16hva", "__AVR_ATmega16HVA__" }, 8762 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 8763 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 8764 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 8765 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 8766 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 8767 { "atmega64hve", "__AVR_ATmega64HVE__" }, 8768 { "at90can32", "__AVR_AT90CAN32__" }, 8769 { "at90can64", "__AVR_AT90CAN64__" }, 8770 { "at90pwm161", "__AVR_AT90PWM161__" }, 8771 { "at90pwm216", "__AVR_AT90PWM216__" }, 8772 { "at90pwm316", "__AVR_AT90PWM316__" }, 8773 { "atmega32c1", "__AVR_ATmega32C1__" }, 8774 { "atmega64c1", "__AVR_ATmega64C1__" }, 8775 { "atmega16m1", "__AVR_ATmega16M1__" }, 8776 { "atmega32m1", "__AVR_ATmega32M1__" }, 8777 { "atmega64m1", "__AVR_ATmega64M1__" }, 8778 { "atmega16u4", "__AVR_ATmega16U4__" }, 8779 { "atmega32u4", "__AVR_ATmega32U4__" }, 8780 { "atmega32u6", "__AVR_ATmega32U6__" }, 8781 { "at90usb646", "__AVR_AT90USB646__" }, 8782 { "at90usb647", "__AVR_AT90USB647__" }, 8783 { "at90scr100", "__AVR_AT90SCR100__" }, 8784 { "at94k", "__AVR_AT94K__" }, 8785 { "m3000", "__AVR_AT000__" }, 8786 { "atmega128", "__AVR_ATmega128__" }, 8787 { "atmega128a", "__AVR_ATmega128A__" }, 8788 { "atmega1280", "__AVR_ATmega1280__" }, 8789 { "atmega1281", "__AVR_ATmega1281__" }, 8790 { "atmega1284", "__AVR_ATmega1284__" }, 8791 { "atmega1284p", "__AVR_ATmega1284P__" }, 8792 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 8793 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 8794 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 8795 { "at90can128", "__AVR_AT90CAN128__" }, 8796 { "at90usb1286", "__AVR_AT90USB1286__" }, 8797 { "at90usb1287", "__AVR_AT90USB1287__" }, 8798 { "atmega2560", "__AVR_ATmega2560__" }, 8799 { "atmega2561", "__AVR_ATmega2561__" }, 8800 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 8801 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 8802 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 8803 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 8804 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 8805 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 8806 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 8807 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 8808 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 8809 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 8810 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 8811 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 8812 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 8813 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 8814 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 8815 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 8816 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 8817 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 8818 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 8819 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 8820 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 8821 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 8822 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 8823 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 8824 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 8825 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 8826 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 8827 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 8828 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 8829 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 8830 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 8831 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 8832 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 8833 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 8834 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 8835 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 8836 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 8837 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 8838 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 8839 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 8840 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 8841 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 8842 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 8843 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 8844 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 8845 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 8846 { "attiny4", "__AVR_ATtiny4__" }, 8847 { "attiny5", "__AVR_ATtiny5__" }, 8848 { "attiny9", "__AVR_ATtiny9__" }, 8849 { "attiny10", "__AVR_ATtiny10__" }, 8850 { "attiny20", "__AVR_ATtiny20__" }, 8851 { "attiny40", "__AVR_ATtiny40__" }, 8852 { "attiny102", "__AVR_ATtiny102__" }, 8853 { "attiny104", "__AVR_ATtiny104__" }, 8854 }; 8855 8856 // AVR Target 8857 class AVRTargetInfo : public TargetInfo { 8858 public: 8859 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8860 : TargetInfo(Triple) { 8861 TLSSupported = false; 8862 PointerWidth = 16; 8863 PointerAlign = 8; 8864 IntWidth = 16; 8865 IntAlign = 8; 8866 LongWidth = 32; 8867 LongAlign = 8; 8868 LongLongWidth = 64; 8869 LongLongAlign = 8; 8870 SuitableAlign = 8; 8871 DefaultAlignForAttributeAligned = 8; 8872 HalfWidth = 16; 8873 HalfAlign = 8; 8874 FloatWidth = 32; 8875 FloatAlign = 8; 8876 DoubleWidth = 32; 8877 DoubleAlign = 8; 8878 DoubleFormat = &llvm::APFloat::IEEEsingle(); 8879 LongDoubleWidth = 32; 8880 LongDoubleAlign = 8; 8881 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 8882 SizeType = UnsignedInt; 8883 PtrDiffType = SignedInt; 8884 IntPtrType = SignedInt; 8885 Char16Type = UnsignedInt; 8886 WCharType = SignedInt; 8887 WIntType = SignedInt; 8888 Char32Type = UnsignedLong; 8889 SigAtomicType = SignedChar; 8890 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 8891 "-f32:32:32-f64:64:64-n8"); 8892 } 8893 8894 void getTargetDefines(const LangOptions &Opts, 8895 MacroBuilder &Builder) const override { 8896 Builder.defineMacro("AVR"); 8897 Builder.defineMacro("__AVR"); 8898 Builder.defineMacro("__AVR__"); 8899 8900 if (!this->CPU.empty()) { 8901 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 8902 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 8903 8904 if (It != AVRMcus.end()) 8905 Builder.defineMacro(It->DefineName); 8906 } 8907 } 8908 8909 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8910 return None; 8911 } 8912 8913 BuiltinVaListKind getBuiltinVaListKind() const override { 8914 return TargetInfo::VoidPtrBuiltinVaList; 8915 } 8916 8917 const char *getClobbers() const override { 8918 return ""; 8919 } 8920 8921 ArrayRef<const char *> getGCCRegNames() const override { 8922 static const char * const GCCRegNames[] = { 8923 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8924 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 8925 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 8926 "r24", "r25", "X", "Y", "Z", "SP" 8927 }; 8928 return llvm::makeArrayRef(GCCRegNames); 8929 } 8930 8931 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8932 return None; 8933 } 8934 8935 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 8936 static const TargetInfo::AddlRegName AddlRegNames[] = { 8937 { { "r26", "r27"}, 26 }, 8938 { { "r28", "r29"}, 27 }, 8939 { { "r30", "r31"}, 28 }, 8940 { { "SPL", "SPH"}, 29 }, 8941 }; 8942 return llvm::makeArrayRef(AddlRegNames); 8943 } 8944 8945 bool validateAsmConstraint(const char *&Name, 8946 TargetInfo::ConstraintInfo &Info) const override { 8947 // There aren't any multi-character AVR specific constraints. 8948 if (StringRef(Name).size() > 1) return false; 8949 8950 switch (*Name) { 8951 default: return false; 8952 case 'a': // Simple upper registers 8953 case 'b': // Base pointer registers pairs 8954 case 'd': // Upper register 8955 case 'l': // Lower registers 8956 case 'e': // Pointer register pairs 8957 case 'q': // Stack pointer register 8958 case 'r': // Any register 8959 case 'w': // Special upper register pairs 8960 case 't': // Temporary register 8961 case 'x': case 'X': // Pointer register pair X 8962 case 'y': case 'Y': // Pointer register pair Y 8963 case 'z': case 'Z': // Pointer register pair Z 8964 Info.setAllowsRegister(); 8965 return true; 8966 case 'I': // 6-bit positive integer constant 8967 Info.setRequiresImmediate(0, 63); 8968 return true; 8969 case 'J': // 6-bit negative integer constant 8970 Info.setRequiresImmediate(-63, 0); 8971 return true; 8972 case 'K': // Integer constant (Range: 2) 8973 Info.setRequiresImmediate(2); 8974 return true; 8975 case 'L': // Integer constant (Range: 0) 8976 Info.setRequiresImmediate(0); 8977 return true; 8978 case 'M': // 8-bit integer constant 8979 Info.setRequiresImmediate(0, 0xff); 8980 return true; 8981 case 'N': // Integer constant (Range: -1) 8982 Info.setRequiresImmediate(-1); 8983 return true; 8984 case 'O': // Integer constant (Range: 8, 16, 24) 8985 Info.setRequiresImmediate({8, 16, 24}); 8986 return true; 8987 case 'P': // Integer constant (Range: 1) 8988 Info.setRequiresImmediate(1); 8989 return true; 8990 case 'R': // Integer constant (Range: -6 to 5) 8991 Info.setRequiresImmediate(-6, 5); 8992 return true; 8993 case 'G': // Floating point constant 8994 case 'Q': // A memory address based on Y or Z pointer with displacement. 8995 return true; 8996 } 8997 8998 return false; 8999 } 9000 9001 IntType getIntTypeByWidth(unsigned BitWidth, 9002 bool IsSigned) const final { 9003 // AVR prefers int for 16-bit integers. 9004 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 9005 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 9006 } 9007 9008 IntType getLeastIntTypeByWidth(unsigned BitWidth, 9009 bool IsSigned) const final { 9010 // AVR uses int for int_least16_t and int_fast16_t. 9011 return BitWidth == 16 9012 ? (IsSigned ? SignedInt : UnsignedInt) 9013 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 9014 } 9015 9016 bool setCPU(const std::string &Name) override { 9017 bool IsFamily = llvm::StringSwitch<bool>(Name) 9018 .Case("avr1", true) 9019 .Case("avr2", true) 9020 .Case("avr25", true) 9021 .Case("avr3", true) 9022 .Case("avr31", true) 9023 .Case("avr35", true) 9024 .Case("avr4", true) 9025 .Case("avr5", true) 9026 .Case("avr51", true) 9027 .Case("avr6", true) 9028 .Case("avrxmega1", true) 9029 .Case("avrxmega2", true) 9030 .Case("avrxmega3", true) 9031 .Case("avrxmega4", true) 9032 .Case("avrxmega5", true) 9033 .Case("avrxmega6", true) 9034 .Case("avrxmega7", true) 9035 .Case("avrtiny", true) 9036 .Default(false); 9037 9038 if (IsFamily) this->CPU = Name; 9039 9040 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9041 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 9042 9043 if (IsMCU) this->CPU = Name; 9044 9045 return IsFamily || IsMCU; 9046 } 9047 9048 protected: 9049 std::string CPU; 9050 }; 9051 9052 } // end anonymous namespace 9053 9054 //===----------------------------------------------------------------------===// 9055 // Driver code 9056 //===----------------------------------------------------------------------===// 9057 9058 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 9059 const TargetOptions &Opts) { 9060 llvm::Triple::OSType os = Triple.getOS(); 9061 9062 switch (Triple.getArch()) { 9063 default: 9064 return nullptr; 9065 9066 case llvm::Triple::xcore: 9067 return new XCoreTargetInfo(Triple, Opts); 9068 9069 case llvm::Triple::hexagon: 9070 return new HexagonTargetInfo(Triple, Opts); 9071 9072 case llvm::Triple::lanai: 9073 return new LanaiTargetInfo(Triple, Opts); 9074 9075 case llvm::Triple::aarch64: 9076 if (Triple.isOSDarwin()) 9077 return new DarwinAArch64TargetInfo(Triple, Opts); 9078 9079 switch (os) { 9080 case llvm::Triple::CloudABI: 9081 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 9082 case llvm::Triple::FreeBSD: 9083 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9084 case llvm::Triple::Fuchsia: 9085 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9086 case llvm::Triple::Linux: 9087 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9088 case llvm::Triple::NetBSD: 9089 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9090 case llvm::Triple::OpenBSD: 9091 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9092 default: 9093 return new AArch64leTargetInfo(Triple, Opts); 9094 } 9095 9096 case llvm::Triple::aarch64_be: 9097 switch (os) { 9098 case llvm::Triple::FreeBSD: 9099 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9100 case llvm::Triple::Fuchsia: 9101 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9102 case llvm::Triple::Linux: 9103 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9104 case llvm::Triple::NetBSD: 9105 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9106 default: 9107 return new AArch64beTargetInfo(Triple, Opts); 9108 } 9109 9110 case llvm::Triple::arm: 9111 case llvm::Triple::thumb: 9112 if (Triple.isOSBinFormatMachO()) 9113 return new DarwinARMTargetInfo(Triple, Opts); 9114 9115 switch (os) { 9116 case llvm::Triple::CloudABI: 9117 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9118 case llvm::Triple::Linux: 9119 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9120 case llvm::Triple::FreeBSD: 9121 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9122 case llvm::Triple::NetBSD: 9123 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9124 case llvm::Triple::OpenBSD: 9125 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9126 case llvm::Triple::Bitrig: 9127 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9128 case llvm::Triple::RTEMS: 9129 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9130 case llvm::Triple::NaCl: 9131 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9132 case llvm::Triple::Win32: 9133 switch (Triple.getEnvironment()) { 9134 case llvm::Triple::Cygnus: 9135 return new CygwinARMTargetInfo(Triple, Opts); 9136 case llvm::Triple::GNU: 9137 return new MinGWARMTargetInfo(Triple, Opts); 9138 case llvm::Triple::Itanium: 9139 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9140 case llvm::Triple::MSVC: 9141 default: // Assume MSVC for unknown environments 9142 return new MicrosoftARMleTargetInfo(Triple, Opts); 9143 } 9144 default: 9145 return new ARMleTargetInfo(Triple, Opts); 9146 } 9147 9148 case llvm::Triple::armeb: 9149 case llvm::Triple::thumbeb: 9150 if (Triple.isOSDarwin()) 9151 return new DarwinARMTargetInfo(Triple, Opts); 9152 9153 switch (os) { 9154 case llvm::Triple::Linux: 9155 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9156 case llvm::Triple::FreeBSD: 9157 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9158 case llvm::Triple::NetBSD: 9159 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9160 case llvm::Triple::OpenBSD: 9161 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9162 case llvm::Triple::Bitrig: 9163 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9164 case llvm::Triple::RTEMS: 9165 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9166 case llvm::Triple::NaCl: 9167 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9168 default: 9169 return new ARMbeTargetInfo(Triple, Opts); 9170 } 9171 9172 case llvm::Triple::avr: 9173 return new AVRTargetInfo(Triple, Opts); 9174 case llvm::Triple::bpfeb: 9175 case llvm::Triple::bpfel: 9176 return new BPFTargetInfo(Triple, Opts); 9177 9178 case llvm::Triple::msp430: 9179 return new MSP430TargetInfo(Triple, Opts); 9180 9181 case llvm::Triple::mips: 9182 switch (os) { 9183 case llvm::Triple::Linux: 9184 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9185 case llvm::Triple::RTEMS: 9186 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9187 case llvm::Triple::FreeBSD: 9188 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9189 case llvm::Triple::NetBSD: 9190 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9191 default: 9192 return new MipsTargetInfo(Triple, Opts); 9193 } 9194 9195 case llvm::Triple::mipsel: 9196 switch (os) { 9197 case llvm::Triple::Linux: 9198 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9199 case llvm::Triple::RTEMS: 9200 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9201 case llvm::Triple::FreeBSD: 9202 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9203 case llvm::Triple::NetBSD: 9204 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9205 case llvm::Triple::NaCl: 9206 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9207 default: 9208 return new MipsTargetInfo(Triple, Opts); 9209 } 9210 9211 case llvm::Triple::mips64: 9212 switch (os) { 9213 case llvm::Triple::Linux: 9214 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9215 case llvm::Triple::RTEMS: 9216 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9217 case llvm::Triple::FreeBSD: 9218 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9219 case llvm::Triple::NetBSD: 9220 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9221 case llvm::Triple::OpenBSD: 9222 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9223 default: 9224 return new MipsTargetInfo(Triple, Opts); 9225 } 9226 9227 case llvm::Triple::mips64el: 9228 switch (os) { 9229 case llvm::Triple::Linux: 9230 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9231 case llvm::Triple::RTEMS: 9232 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9233 case llvm::Triple::FreeBSD: 9234 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9235 case llvm::Triple::NetBSD: 9236 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9237 case llvm::Triple::OpenBSD: 9238 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9239 default: 9240 return new MipsTargetInfo(Triple, Opts); 9241 } 9242 9243 case llvm::Triple::le32: 9244 switch (os) { 9245 case llvm::Triple::NaCl: 9246 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9247 default: 9248 return nullptr; 9249 } 9250 9251 case llvm::Triple::le64: 9252 return new Le64TargetInfo(Triple, Opts); 9253 9254 case llvm::Triple::ppc: 9255 if (Triple.isOSDarwin()) 9256 return new DarwinPPC32TargetInfo(Triple, Opts); 9257 switch (os) { 9258 case llvm::Triple::Linux: 9259 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9260 case llvm::Triple::FreeBSD: 9261 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9262 case llvm::Triple::NetBSD: 9263 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9264 case llvm::Triple::OpenBSD: 9265 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9266 case llvm::Triple::RTEMS: 9267 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9268 default: 9269 return new PPC32TargetInfo(Triple, Opts); 9270 } 9271 9272 case llvm::Triple::ppc64: 9273 if (Triple.isOSDarwin()) 9274 return new DarwinPPC64TargetInfo(Triple, Opts); 9275 switch (os) { 9276 case llvm::Triple::Linux: 9277 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9278 case llvm::Triple::Lv2: 9279 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9280 case llvm::Triple::FreeBSD: 9281 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9282 case llvm::Triple::NetBSD: 9283 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9284 default: 9285 return new PPC64TargetInfo(Triple, Opts); 9286 } 9287 9288 case llvm::Triple::ppc64le: 9289 switch (os) { 9290 case llvm::Triple::Linux: 9291 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9292 case llvm::Triple::NetBSD: 9293 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9294 default: 9295 return new PPC64TargetInfo(Triple, Opts); 9296 } 9297 9298 case llvm::Triple::nvptx: 9299 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9300 case llvm::Triple::nvptx64: 9301 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9302 9303 case llvm::Triple::amdgcn: 9304 case llvm::Triple::r600: 9305 return new AMDGPUTargetInfo(Triple, Opts); 9306 9307 case llvm::Triple::sparc: 9308 switch (os) { 9309 case llvm::Triple::Linux: 9310 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9311 case llvm::Triple::Solaris: 9312 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9313 case llvm::Triple::NetBSD: 9314 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9315 case llvm::Triple::OpenBSD: 9316 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9317 case llvm::Triple::RTEMS: 9318 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9319 default: 9320 return new SparcV8TargetInfo(Triple, Opts); 9321 } 9322 9323 // The 'sparcel' architecture copies all the above cases except for Solaris. 9324 case llvm::Triple::sparcel: 9325 switch (os) { 9326 case llvm::Triple::Linux: 9327 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9328 case llvm::Triple::NetBSD: 9329 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9330 case llvm::Triple::OpenBSD: 9331 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9332 case llvm::Triple::RTEMS: 9333 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9334 default: 9335 return new SparcV8elTargetInfo(Triple, Opts); 9336 } 9337 9338 case llvm::Triple::sparcv9: 9339 switch (os) { 9340 case llvm::Triple::Linux: 9341 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9342 case llvm::Triple::Solaris: 9343 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9344 case llvm::Triple::NetBSD: 9345 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9346 case llvm::Triple::OpenBSD: 9347 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9348 case llvm::Triple::FreeBSD: 9349 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9350 default: 9351 return new SparcV9TargetInfo(Triple, Opts); 9352 } 9353 9354 case llvm::Triple::systemz: 9355 switch (os) { 9356 case llvm::Triple::Linux: 9357 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9358 default: 9359 return new SystemZTargetInfo(Triple, Opts); 9360 } 9361 9362 case llvm::Triple::tce: 9363 return new TCETargetInfo(Triple, Opts); 9364 9365 case llvm::Triple::tcele: 9366 return new TCELETargetInfo(Triple, Opts); 9367 9368 case llvm::Triple::x86: 9369 if (Triple.isOSDarwin()) 9370 return new DarwinI386TargetInfo(Triple, Opts); 9371 9372 switch (os) { 9373 case llvm::Triple::CloudABI: 9374 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9375 case llvm::Triple::Linux: { 9376 switch (Triple.getEnvironment()) { 9377 default: 9378 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9379 case llvm::Triple::Android: 9380 return new AndroidX86_32TargetInfo(Triple, Opts); 9381 } 9382 } 9383 case llvm::Triple::DragonFly: 9384 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9385 case llvm::Triple::NetBSD: 9386 return new NetBSDI386TargetInfo(Triple, Opts); 9387 case llvm::Triple::OpenBSD: 9388 return new OpenBSDI386TargetInfo(Triple, Opts); 9389 case llvm::Triple::Bitrig: 9390 return new BitrigI386TargetInfo(Triple, Opts); 9391 case llvm::Triple::FreeBSD: 9392 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9393 case llvm::Triple::KFreeBSD: 9394 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9395 case llvm::Triple::Minix: 9396 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9397 case llvm::Triple::Solaris: 9398 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9399 case llvm::Triple::Win32: { 9400 switch (Triple.getEnvironment()) { 9401 case llvm::Triple::Cygnus: 9402 return new CygwinX86_32TargetInfo(Triple, Opts); 9403 case llvm::Triple::GNU: 9404 return new MinGWX86_32TargetInfo(Triple, Opts); 9405 case llvm::Triple::Itanium: 9406 case llvm::Triple::MSVC: 9407 default: // Assume MSVC for unknown environments 9408 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9409 } 9410 } 9411 case llvm::Triple::Haiku: 9412 return new HaikuX86_32TargetInfo(Triple, Opts); 9413 case llvm::Triple::RTEMS: 9414 return new RTEMSX86_32TargetInfo(Triple, Opts); 9415 case llvm::Triple::NaCl: 9416 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9417 case llvm::Triple::ELFIAMCU: 9418 return new MCUX86_32TargetInfo(Triple, Opts); 9419 default: 9420 return new X86_32TargetInfo(Triple, Opts); 9421 } 9422 9423 case llvm::Triple::x86_64: 9424 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9425 return new DarwinX86_64TargetInfo(Triple, Opts); 9426 9427 switch (os) { 9428 case llvm::Triple::CloudABI: 9429 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9430 case llvm::Triple::Linux: { 9431 switch (Triple.getEnvironment()) { 9432 default: 9433 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9434 case llvm::Triple::Android: 9435 return new AndroidX86_64TargetInfo(Triple, Opts); 9436 } 9437 } 9438 case llvm::Triple::DragonFly: 9439 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9440 case llvm::Triple::NetBSD: 9441 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9442 case llvm::Triple::OpenBSD: 9443 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9444 case llvm::Triple::Bitrig: 9445 return new BitrigX86_64TargetInfo(Triple, Opts); 9446 case llvm::Triple::FreeBSD: 9447 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9448 case llvm::Triple::Fuchsia: 9449 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9450 case llvm::Triple::KFreeBSD: 9451 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9452 case llvm::Triple::Solaris: 9453 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9454 case llvm::Triple::Win32: { 9455 switch (Triple.getEnvironment()) { 9456 case llvm::Triple::Cygnus: 9457 return new CygwinX86_64TargetInfo(Triple, Opts); 9458 case llvm::Triple::GNU: 9459 return new MinGWX86_64TargetInfo(Triple, Opts); 9460 case llvm::Triple::MSVC: 9461 default: // Assume MSVC for unknown environments 9462 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9463 } 9464 } 9465 case llvm::Triple::Haiku: 9466 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9467 case llvm::Triple::NaCl: 9468 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9469 case llvm::Triple::PS4: 9470 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9471 default: 9472 return new X86_64TargetInfo(Triple, Opts); 9473 } 9474 9475 case llvm::Triple::spir: { 9476 if (Triple.getOS() != llvm::Triple::UnknownOS || 9477 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9478 return nullptr; 9479 return new SPIR32TargetInfo(Triple, Opts); 9480 } 9481 case llvm::Triple::spir64: { 9482 if (Triple.getOS() != llvm::Triple::UnknownOS || 9483 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9484 return nullptr; 9485 return new SPIR64TargetInfo(Triple, Opts); 9486 } 9487 case llvm::Triple::wasm32: 9488 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9489 Triple.getVendor() != llvm::Triple::UnknownVendor || 9490 Triple.getOS() != llvm::Triple::UnknownOS || 9491 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9492 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9493 return nullptr; 9494 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9495 case llvm::Triple::wasm64: 9496 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9497 Triple.getVendor() != llvm::Triple::UnknownVendor || 9498 Triple.getOS() != llvm::Triple::UnknownOS || 9499 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9500 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9501 return nullptr; 9502 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9503 9504 case llvm::Triple::renderscript32: 9505 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9506 case llvm::Triple::renderscript64: 9507 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9508 } 9509 } 9510 9511 /// CreateTargetInfo - Return the target info object for the specified target 9512 /// options. 9513 TargetInfo * 9514 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9515 const std::shared_ptr<TargetOptions> &Opts) { 9516 llvm::Triple Triple(Opts->Triple); 9517 9518 // Construct the target 9519 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9520 if (!Target) { 9521 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9522 return nullptr; 9523 } 9524 Target->TargetOpts = Opts; 9525 9526 // Set the target CPU if specified. 9527 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9528 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9529 return nullptr; 9530 } 9531 9532 // Set the target ABI if specified. 9533 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 9534 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 9535 return nullptr; 9536 } 9537 9538 // Set the fp math unit. 9539 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 9540 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 9541 return nullptr; 9542 } 9543 9544 // Compute the default target features, we need the target to handle this 9545 // because features may have dependencies on one another. 9546 llvm::StringMap<bool> Features; 9547 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 9548 Opts->FeaturesAsWritten)) 9549 return nullptr; 9550 9551 // Add the features to the compile options. 9552 Opts->Features.clear(); 9553 for (const auto &F : Features) 9554 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 9555 9556 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 9557 return nullptr; 9558 9559 Target->setSupportedOpenCLOpts(); 9560 Target->setOpenCLExtensionOpts(); 9561 9562 if (!Target->validateTarget(Diags)) 9563 return nullptr; 9564 9565 return Target.release(); 9566 } 9567