1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 if (Maj) 469 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 470 } 471 if (Opts.POSIXThreads) 472 Builder.defineMacro("_REENTRANT"); 473 if (Opts.CPlusPlus) 474 Builder.defineMacro("_GNU_SOURCE"); 475 if (this->HasFloat128) 476 Builder.defineMacro("__FLOAT128__"); 477 } 478 public: 479 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 480 : OSTargetInfo<Target>(Triple, Opts) { 481 this->WIntType = TargetInfo::UnsignedInt; 482 483 switch (Triple.getArch()) { 484 default: 485 break; 486 case llvm::Triple::ppc: 487 case llvm::Triple::ppc64: 488 case llvm::Triple::ppc64le: 489 this->MCountName = "_mcount"; 490 break; 491 case llvm::Triple::x86: 492 case llvm::Triple::x86_64: 493 case llvm::Triple::systemz: 494 this->HasFloat128 = true; 495 break; 496 } 497 } 498 499 const char *getStaticInitSectionSpecifier() const override { 500 return ".text.startup"; 501 } 502 }; 503 504 // NetBSD Target 505 template<typename Target> 506 class NetBSDTargetInfo : public OSTargetInfo<Target> { 507 protected: 508 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 509 MacroBuilder &Builder) const override { 510 // NetBSD defines; list based off of gcc output 511 Builder.defineMacro("__NetBSD__"); 512 Builder.defineMacro("__unix__"); 513 Builder.defineMacro("__ELF__"); 514 if (Opts.POSIXThreads) 515 Builder.defineMacro("_REENTRANT"); 516 517 switch (Triple.getArch()) { 518 default: 519 break; 520 case llvm::Triple::arm: 521 case llvm::Triple::armeb: 522 case llvm::Triple::thumb: 523 case llvm::Triple::thumbeb: 524 Builder.defineMacro("__ARM_DWARF_EH__"); 525 break; 526 } 527 } 528 public: 529 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 530 : OSTargetInfo<Target>(Triple, Opts) { 531 this->MCountName = "_mcount"; 532 } 533 }; 534 535 // OpenBSD Target 536 template<typename Target> 537 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 538 protected: 539 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 540 MacroBuilder &Builder) const override { 541 // OpenBSD defines; list based off of gcc output 542 543 Builder.defineMacro("__OpenBSD__"); 544 DefineStd(Builder, "unix", Opts); 545 Builder.defineMacro("__ELF__"); 546 if (Opts.POSIXThreads) 547 Builder.defineMacro("_REENTRANT"); 548 } 549 public: 550 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 551 : OSTargetInfo<Target>(Triple, Opts) { 552 this->TLSSupported = false; 553 554 switch (Triple.getArch()) { 555 default: 556 case llvm::Triple::x86: 557 case llvm::Triple::x86_64: 558 case llvm::Triple::arm: 559 case llvm::Triple::sparc: 560 this->MCountName = "__mcount"; 561 break; 562 case llvm::Triple::mips64: 563 case llvm::Triple::mips64el: 564 case llvm::Triple::ppc: 565 case llvm::Triple::sparcv9: 566 this->MCountName = "_mcount"; 567 break; 568 } 569 } 570 }; 571 572 // Bitrig Target 573 template<typename Target> 574 class BitrigTargetInfo : public OSTargetInfo<Target> { 575 protected: 576 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 577 MacroBuilder &Builder) const override { 578 // Bitrig defines; list based off of gcc output 579 580 Builder.defineMacro("__Bitrig__"); 581 DefineStd(Builder, "unix", Opts); 582 Builder.defineMacro("__ELF__"); 583 if (Opts.POSIXThreads) 584 Builder.defineMacro("_REENTRANT"); 585 586 switch (Triple.getArch()) { 587 default: 588 break; 589 case llvm::Triple::arm: 590 case llvm::Triple::armeb: 591 case llvm::Triple::thumb: 592 case llvm::Triple::thumbeb: 593 Builder.defineMacro("__ARM_DWARF_EH__"); 594 break; 595 } 596 } 597 public: 598 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 599 : OSTargetInfo<Target>(Triple, Opts) { 600 this->MCountName = "__mcount"; 601 } 602 }; 603 604 // PSP Target 605 template<typename Target> 606 class PSPTargetInfo : public OSTargetInfo<Target> { 607 protected: 608 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 609 MacroBuilder &Builder) const override { 610 // PSP defines; list based on the output of the pspdev gcc toolchain. 611 Builder.defineMacro("PSP"); 612 Builder.defineMacro("_PSP"); 613 Builder.defineMacro("__psp__"); 614 Builder.defineMacro("__ELF__"); 615 } 616 public: 617 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 618 }; 619 620 // PS3 PPU Target 621 template<typename Target> 622 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 623 protected: 624 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 625 MacroBuilder &Builder) const override { 626 // PS3 PPU defines. 627 Builder.defineMacro("__PPC__"); 628 Builder.defineMacro("__PPU__"); 629 Builder.defineMacro("__CELLOS_LV2__"); 630 Builder.defineMacro("__ELF__"); 631 Builder.defineMacro("__LP32__"); 632 Builder.defineMacro("_ARCH_PPC64"); 633 Builder.defineMacro("__powerpc64__"); 634 } 635 public: 636 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 637 : OSTargetInfo<Target>(Triple, Opts) { 638 this->LongWidth = this->LongAlign = 32; 639 this->PointerWidth = this->PointerAlign = 32; 640 this->IntMaxType = TargetInfo::SignedLongLong; 641 this->Int64Type = TargetInfo::SignedLongLong; 642 this->SizeType = TargetInfo::UnsignedInt; 643 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 644 } 645 }; 646 647 template <typename Target> 648 class PS4OSTargetInfo : public OSTargetInfo<Target> { 649 protected: 650 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 651 MacroBuilder &Builder) const override { 652 Builder.defineMacro("__FreeBSD__", "9"); 653 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 654 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 655 DefineStd(Builder, "unix", Opts); 656 Builder.defineMacro("__ELF__"); 657 Builder.defineMacro("__ORBIS__"); 658 } 659 public: 660 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 661 : OSTargetInfo<Target>(Triple, Opts) { 662 this->WCharType = this->UnsignedShort; 663 664 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 665 this->MaxTLSAlign = 256; 666 667 // On PS4, do not honor explicit bit field alignment, 668 // as in "__attribute__((aligned(2))) int b : 1;". 669 this->UseExplicitBitFieldAlignment = false; 670 671 switch (Triple.getArch()) { 672 default: 673 case llvm::Triple::x86_64: 674 this->MCountName = ".mcount"; 675 break; 676 } 677 } 678 }; 679 680 // Solaris target 681 template<typename Target> 682 class SolarisTargetInfo : public OSTargetInfo<Target> { 683 protected: 684 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 685 MacroBuilder &Builder) const override { 686 DefineStd(Builder, "sun", Opts); 687 DefineStd(Builder, "unix", Opts); 688 Builder.defineMacro("__ELF__"); 689 Builder.defineMacro("__svr4__"); 690 Builder.defineMacro("__SVR4"); 691 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 692 // newer, but to 500 for everything else. feature_test.h has a check to 693 // ensure that you are not using C99 with an old version of X/Open or C89 694 // with a new version. 695 if (Opts.C99) 696 Builder.defineMacro("_XOPEN_SOURCE", "600"); 697 else 698 Builder.defineMacro("_XOPEN_SOURCE", "500"); 699 if (Opts.CPlusPlus) 700 Builder.defineMacro("__C99FEATURES__"); 701 Builder.defineMacro("_LARGEFILE_SOURCE"); 702 Builder.defineMacro("_LARGEFILE64_SOURCE"); 703 Builder.defineMacro("__EXTENSIONS__"); 704 Builder.defineMacro("_REENTRANT"); 705 } 706 public: 707 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 708 : OSTargetInfo<Target>(Triple, Opts) { 709 this->WCharType = this->SignedInt; 710 // FIXME: WIntType should be SignedLong 711 } 712 }; 713 714 // Windows target 715 template<typename Target> 716 class WindowsTargetInfo : public OSTargetInfo<Target> { 717 protected: 718 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 719 MacroBuilder &Builder) const override { 720 Builder.defineMacro("_WIN32"); 721 } 722 void getVisualStudioDefines(const LangOptions &Opts, 723 MacroBuilder &Builder) const { 724 if (Opts.CPlusPlus) { 725 if (Opts.RTTIData) 726 Builder.defineMacro("_CPPRTTI"); 727 728 if (Opts.CXXExceptions) 729 Builder.defineMacro("_CPPUNWIND"); 730 } 731 732 if (Opts.Bool) 733 Builder.defineMacro("__BOOL_DEFINED"); 734 735 if (!Opts.CharIsSigned) 736 Builder.defineMacro("_CHAR_UNSIGNED"); 737 738 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 739 // but it works for now. 740 if (Opts.POSIXThreads) 741 Builder.defineMacro("_MT"); 742 743 if (Opts.MSCompatibilityVersion) { 744 Builder.defineMacro("_MSC_VER", 745 Twine(Opts.MSCompatibilityVersion / 100000)); 746 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 747 // FIXME We cannot encode the revision information into 32-bits 748 Builder.defineMacro("_MSC_BUILD", Twine(1)); 749 750 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 751 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 752 753 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 754 if (Opts.CPlusPlus1z) 755 Builder.defineMacro("_MSVC_LANG", "201403L"); 756 else if (Opts.CPlusPlus14) 757 Builder.defineMacro("_MSVC_LANG", "201402L"); 758 } 759 } 760 761 if (Opts.MicrosoftExt) { 762 Builder.defineMacro("_MSC_EXTENSIONS"); 763 764 if (Opts.CPlusPlus11) { 765 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 766 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 767 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 768 } 769 } 770 771 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 772 } 773 774 public: 775 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 776 : OSTargetInfo<Target>(Triple, Opts) {} 777 }; 778 779 template <typename Target> 780 class NaClTargetInfo : public OSTargetInfo<Target> { 781 protected: 782 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 783 MacroBuilder &Builder) const override { 784 if (Opts.POSIXThreads) 785 Builder.defineMacro("_REENTRANT"); 786 if (Opts.CPlusPlus) 787 Builder.defineMacro("_GNU_SOURCE"); 788 789 DefineStd(Builder, "unix", Opts); 790 Builder.defineMacro("__ELF__"); 791 Builder.defineMacro("__native_client__"); 792 } 793 794 public: 795 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 796 : OSTargetInfo<Target>(Triple, Opts) { 797 this->LongAlign = 32; 798 this->LongWidth = 32; 799 this->PointerAlign = 32; 800 this->PointerWidth = 32; 801 this->IntMaxType = TargetInfo::SignedLongLong; 802 this->Int64Type = TargetInfo::SignedLongLong; 803 this->DoubleAlign = 64; 804 this->LongDoubleWidth = 64; 805 this->LongDoubleAlign = 64; 806 this->LongLongWidth = 64; 807 this->LongLongAlign = 64; 808 this->SizeType = TargetInfo::UnsignedInt; 809 this->PtrDiffType = TargetInfo::SignedInt; 810 this->IntPtrType = TargetInfo::SignedInt; 811 // RegParmMax is inherited from the underlying architecture. 812 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 813 if (Triple.getArch() == llvm::Triple::arm) { 814 // Handled in ARM's setABI(). 815 } else if (Triple.getArch() == llvm::Triple::x86) { 816 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 817 } else if (Triple.getArch() == llvm::Triple::x86_64) { 818 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 819 } else if (Triple.getArch() == llvm::Triple::mipsel) { 820 // Handled on mips' setDataLayout. 821 } else { 822 assert(Triple.getArch() == llvm::Triple::le32); 823 this->resetDataLayout("e-p:32:32-i64:64"); 824 } 825 } 826 }; 827 828 // Fuchsia Target 829 template<typename Target> 830 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 831 protected: 832 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 833 MacroBuilder &Builder) const override { 834 Builder.defineMacro("__Fuchsia__"); 835 Builder.defineMacro("__ELF__"); 836 if (Opts.POSIXThreads) 837 Builder.defineMacro("_REENTRANT"); 838 // Required by the libc++ locale support. 839 if (Opts.CPlusPlus) 840 Builder.defineMacro("_GNU_SOURCE"); 841 } 842 public: 843 FuchsiaTargetInfo(const llvm::Triple &Triple, 844 const TargetOptions &Opts) 845 : OSTargetInfo<Target>(Triple, Opts) { 846 this->MCountName = "__mcount"; 847 } 848 }; 849 850 // WebAssembly target 851 template <typename Target> 852 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 853 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 854 MacroBuilder &Builder) const final { 855 // A common platform macro. 856 if (Opts.POSIXThreads) 857 Builder.defineMacro("_REENTRANT"); 858 // Follow g++ convention and predefine _GNU_SOURCE for C++. 859 if (Opts.CPlusPlus) 860 Builder.defineMacro("_GNU_SOURCE"); 861 } 862 863 // As an optimization, group static init code together in a section. 864 const char *getStaticInitSectionSpecifier() const final { 865 return ".text.__startup"; 866 } 867 868 public: 869 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 870 const TargetOptions &Opts) 871 : OSTargetInfo<Target>(Triple, Opts) { 872 this->MCountName = "__mcount"; 873 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 874 } 875 }; 876 877 //===----------------------------------------------------------------------===// 878 // Specific target implementations. 879 //===----------------------------------------------------------------------===// 880 881 // PPC abstract base class 882 class PPCTargetInfo : public TargetInfo { 883 static const Builtin::Info BuiltinInfo[]; 884 static const char * const GCCRegNames[]; 885 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 886 std::string CPU; 887 888 // Target cpu features. 889 bool HasVSX; 890 bool HasP8Vector; 891 bool HasP8Crypto; 892 bool HasDirectMove; 893 bool HasQPX; 894 bool HasHTM; 895 bool HasBPERMD; 896 bool HasExtDiv; 897 bool HasP9Vector; 898 899 protected: 900 std::string ABI; 901 902 public: 903 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 904 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 905 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 906 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 907 SimdDefaultAlign = 128; 908 LongDoubleWidth = LongDoubleAlign = 128; 909 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 910 } 911 912 /// \brief Flags for architecture specific defines. 913 typedef enum { 914 ArchDefineNone = 0, 915 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 916 ArchDefinePpcgr = 1 << 1, 917 ArchDefinePpcsq = 1 << 2, 918 ArchDefine440 = 1 << 3, 919 ArchDefine603 = 1 << 4, 920 ArchDefine604 = 1 << 5, 921 ArchDefinePwr4 = 1 << 6, 922 ArchDefinePwr5 = 1 << 7, 923 ArchDefinePwr5x = 1 << 8, 924 ArchDefinePwr6 = 1 << 9, 925 ArchDefinePwr6x = 1 << 10, 926 ArchDefinePwr7 = 1 << 11, 927 ArchDefinePwr8 = 1 << 12, 928 ArchDefinePwr9 = 1 << 13, 929 ArchDefineA2 = 1 << 14, 930 ArchDefineA2q = 1 << 15 931 } ArchDefineTypes; 932 933 // Note: GCC recognizes the following additional cpus: 934 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 935 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 936 // titan, rs64. 937 bool setCPU(const std::string &Name) override { 938 bool CPUKnown = llvm::StringSwitch<bool>(Name) 939 .Case("generic", true) 940 .Case("440", true) 941 .Case("450", true) 942 .Case("601", true) 943 .Case("602", true) 944 .Case("603", true) 945 .Case("603e", true) 946 .Case("603ev", true) 947 .Case("604", true) 948 .Case("604e", true) 949 .Case("620", true) 950 .Case("630", true) 951 .Case("g3", true) 952 .Case("7400", true) 953 .Case("g4", true) 954 .Case("7450", true) 955 .Case("g4+", true) 956 .Case("750", true) 957 .Case("970", true) 958 .Case("g5", true) 959 .Case("a2", true) 960 .Case("a2q", true) 961 .Case("e500mc", true) 962 .Case("e5500", true) 963 .Case("power3", true) 964 .Case("pwr3", true) 965 .Case("power4", true) 966 .Case("pwr4", true) 967 .Case("power5", true) 968 .Case("pwr5", true) 969 .Case("power5x", true) 970 .Case("pwr5x", true) 971 .Case("power6", true) 972 .Case("pwr6", true) 973 .Case("power6x", true) 974 .Case("pwr6x", true) 975 .Case("power7", true) 976 .Case("pwr7", true) 977 .Case("power8", true) 978 .Case("pwr8", true) 979 .Case("power9", true) 980 .Case("pwr9", true) 981 .Case("powerpc", true) 982 .Case("ppc", true) 983 .Case("powerpc64", true) 984 .Case("ppc64", true) 985 .Case("powerpc64le", true) 986 .Case("ppc64le", true) 987 .Default(false); 988 989 if (CPUKnown) 990 CPU = Name; 991 992 return CPUKnown; 993 } 994 995 996 StringRef getABI() const override { return ABI; } 997 998 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 999 return llvm::makeArrayRef(BuiltinInfo, 1000 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1001 } 1002 1003 bool isCLZForZeroUndef() const override { return false; } 1004 1005 void getTargetDefines(const LangOptions &Opts, 1006 MacroBuilder &Builder) const override; 1007 1008 bool 1009 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1010 StringRef CPU, 1011 const std::vector<std::string> &FeaturesVec) const override; 1012 1013 bool handleTargetFeatures(std::vector<std::string> &Features, 1014 DiagnosticsEngine &Diags) override; 1015 bool hasFeature(StringRef Feature) const override; 1016 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1017 bool Enabled) const override; 1018 1019 ArrayRef<const char *> getGCCRegNames() const override; 1020 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1021 bool validateAsmConstraint(const char *&Name, 1022 TargetInfo::ConstraintInfo &Info) const override { 1023 switch (*Name) { 1024 default: return false; 1025 case 'O': // Zero 1026 break; 1027 case 'b': // Base register 1028 case 'f': // Floating point register 1029 Info.setAllowsRegister(); 1030 break; 1031 // FIXME: The following are added to allow parsing. 1032 // I just took a guess at what the actions should be. 1033 // Also, is more specific checking needed? I.e. specific registers? 1034 case 'd': // Floating point register (containing 64-bit value) 1035 case 'v': // Altivec vector register 1036 Info.setAllowsRegister(); 1037 break; 1038 case 'w': 1039 switch (Name[1]) { 1040 case 'd':// VSX vector register to hold vector double data 1041 case 'f':// VSX vector register to hold vector float data 1042 case 's':// VSX vector register to hold scalar float data 1043 case 'a':// Any VSX register 1044 case 'c':// An individual CR bit 1045 break; 1046 default: 1047 return false; 1048 } 1049 Info.setAllowsRegister(); 1050 Name++; // Skip over 'w'. 1051 break; 1052 case 'h': // `MQ', `CTR', or `LINK' register 1053 case 'q': // `MQ' register 1054 case 'c': // `CTR' register 1055 case 'l': // `LINK' register 1056 case 'x': // `CR' register (condition register) number 0 1057 case 'y': // `CR' register (condition register) 1058 case 'z': // `XER[CA]' carry bit (part of the XER register) 1059 Info.setAllowsRegister(); 1060 break; 1061 case 'I': // Signed 16-bit constant 1062 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1063 // (use `L' instead for SImode constants) 1064 case 'K': // Unsigned 16-bit constant 1065 case 'L': // Signed 16-bit constant shifted left 16 bits 1066 case 'M': // Constant larger than 31 1067 case 'N': // Exact power of 2 1068 case 'P': // Constant whose negation is a signed 16-bit constant 1069 case 'G': // Floating point constant that can be loaded into a 1070 // register with one instruction per word 1071 case 'H': // Integer/Floating point constant that can be loaded 1072 // into a register using three instructions 1073 break; 1074 case 'm': // Memory operand. Note that on PowerPC targets, m can 1075 // include addresses that update the base register. It 1076 // is therefore only safe to use `m' in an asm statement 1077 // if that asm statement accesses the operand exactly once. 1078 // The asm statement must also use `%U<opno>' as a 1079 // placeholder for the "update" flag in the corresponding 1080 // load or store instruction. For example: 1081 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1082 // is correct but: 1083 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1084 // is not. Use es rather than m if you don't want the base 1085 // register to be updated. 1086 case 'e': 1087 if (Name[1] != 's') 1088 return false; 1089 // es: A "stable" memory operand; that is, one which does not 1090 // include any automodification of the base register. Unlike 1091 // `m', this constraint can be used in asm statements that 1092 // might access the operand several times, or that might not 1093 // access it at all. 1094 Info.setAllowsMemory(); 1095 Name++; // Skip over 'e'. 1096 break; 1097 case 'Q': // Memory operand that is an offset from a register (it is 1098 // usually better to use `m' or `es' in asm statements) 1099 case 'Z': // Memory operand that is an indexed or indirect from a 1100 // register (it is usually better to use `m' or `es' in 1101 // asm statements) 1102 Info.setAllowsMemory(); 1103 Info.setAllowsRegister(); 1104 break; 1105 case 'R': // AIX TOC entry 1106 case 'a': // Address operand that is an indexed or indirect from a 1107 // register (`p' is preferable for asm statements) 1108 case 'S': // Constant suitable as a 64-bit mask operand 1109 case 'T': // Constant suitable as a 32-bit mask operand 1110 case 'U': // System V Release 4 small data area reference 1111 case 't': // AND masks that can be performed by two rldic{l, r} 1112 // instructions 1113 case 'W': // Vector constant that does not require memory 1114 case 'j': // Vector constant that is all zeros. 1115 break; 1116 // End FIXME. 1117 } 1118 return true; 1119 } 1120 std::string convertConstraint(const char *&Constraint) const override { 1121 std::string R; 1122 switch (*Constraint) { 1123 case 'e': 1124 case 'w': 1125 // Two-character constraint; add "^" hint for later parsing. 1126 R = std::string("^") + std::string(Constraint, 2); 1127 Constraint++; 1128 break; 1129 default: 1130 return TargetInfo::convertConstraint(Constraint); 1131 } 1132 return R; 1133 } 1134 const char *getClobbers() const override { 1135 return ""; 1136 } 1137 int getEHDataRegisterNumber(unsigned RegNo) const override { 1138 if (RegNo == 0) return 3; 1139 if (RegNo == 1) return 4; 1140 return -1; 1141 } 1142 1143 bool hasSjLjLowering() const override { 1144 return true; 1145 } 1146 1147 bool useFloat128ManglingForLongDouble() const override { 1148 return LongDoubleWidth == 128 && 1149 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1150 getTriple().isOSBinFormatELF(); 1151 } 1152 }; 1153 1154 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1155 #define BUILTIN(ID, TYPE, ATTRS) \ 1156 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1157 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1158 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1159 #include "clang/Basic/BuiltinsPPC.def" 1160 }; 1161 1162 /// handleTargetFeatures - Perform initialization based on the user 1163 /// configured set of features. 1164 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1165 DiagnosticsEngine &Diags) { 1166 for (const auto &Feature : Features) { 1167 if (Feature == "+vsx") { 1168 HasVSX = true; 1169 } else if (Feature == "+bpermd") { 1170 HasBPERMD = true; 1171 } else if (Feature == "+extdiv") { 1172 HasExtDiv = true; 1173 } else if (Feature == "+power8-vector") { 1174 HasP8Vector = true; 1175 } else if (Feature == "+crypto") { 1176 HasP8Crypto = true; 1177 } else if (Feature == "+direct-move") { 1178 HasDirectMove = true; 1179 } else if (Feature == "+qpx") { 1180 HasQPX = true; 1181 } else if (Feature == "+htm") { 1182 HasHTM = true; 1183 } else if (Feature == "+float128") { 1184 HasFloat128 = true; 1185 } else if (Feature == "+power9-vector") { 1186 HasP9Vector = true; 1187 } 1188 // TODO: Finish this list and add an assert that we've handled them 1189 // all. 1190 } 1191 1192 return true; 1193 } 1194 1195 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1196 /// #defines that are not tied to a specific subtarget. 1197 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1198 MacroBuilder &Builder) const { 1199 // Target identification. 1200 Builder.defineMacro("__ppc__"); 1201 Builder.defineMacro("__PPC__"); 1202 Builder.defineMacro("_ARCH_PPC"); 1203 Builder.defineMacro("__powerpc__"); 1204 Builder.defineMacro("__POWERPC__"); 1205 if (PointerWidth == 64) { 1206 Builder.defineMacro("_ARCH_PPC64"); 1207 Builder.defineMacro("__powerpc64__"); 1208 Builder.defineMacro("__ppc64__"); 1209 Builder.defineMacro("__PPC64__"); 1210 } 1211 1212 // Target properties. 1213 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1214 Builder.defineMacro("_LITTLE_ENDIAN"); 1215 } else { 1216 if (getTriple().getOS() != llvm::Triple::NetBSD && 1217 getTriple().getOS() != llvm::Triple::OpenBSD) 1218 Builder.defineMacro("_BIG_ENDIAN"); 1219 } 1220 1221 // ABI options. 1222 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1223 Builder.defineMacro("_CALL_ELF", "1"); 1224 if (ABI == "elfv2") 1225 Builder.defineMacro("_CALL_ELF", "2"); 1226 1227 // Subtarget options. 1228 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1229 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1230 1231 // FIXME: Should be controlled by command line option. 1232 if (LongDoubleWidth == 128) 1233 Builder.defineMacro("__LONG_DOUBLE_128__"); 1234 1235 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1236 if (ABI == "elfv2" || 1237 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1238 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1239 1240 if (Opts.AltiVec) { 1241 Builder.defineMacro("__VEC__", "10206"); 1242 Builder.defineMacro("__ALTIVEC__"); 1243 } 1244 1245 // CPU identification. 1246 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1247 .Case("440", ArchDefineName) 1248 .Case("450", ArchDefineName | ArchDefine440) 1249 .Case("601", ArchDefineName) 1250 .Case("602", ArchDefineName | ArchDefinePpcgr) 1251 .Case("603", ArchDefineName | ArchDefinePpcgr) 1252 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1253 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1254 .Case("604", ArchDefineName | ArchDefinePpcgr) 1255 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1256 .Case("620", ArchDefineName | ArchDefinePpcgr) 1257 .Case("630", ArchDefineName | ArchDefinePpcgr) 1258 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1259 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1260 .Case("750", ArchDefineName | ArchDefinePpcgr) 1261 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1262 | ArchDefinePpcsq) 1263 .Case("a2", ArchDefineA2) 1264 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1265 .Case("pwr3", ArchDefinePpcgr) 1266 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1267 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1268 | ArchDefinePpcsq) 1269 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1270 | ArchDefinePpcgr | ArchDefinePpcsq) 1271 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1272 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1273 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1274 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1275 | ArchDefinePpcsq) 1276 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1277 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1278 | ArchDefinePpcgr | ArchDefinePpcsq) 1279 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1280 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1281 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1282 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1283 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1284 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1285 | ArchDefinePpcsq) 1286 .Case("power3", ArchDefinePpcgr) 1287 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1288 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1289 | ArchDefinePpcsq) 1290 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1291 | ArchDefinePpcgr | ArchDefinePpcsq) 1292 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1293 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1294 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1295 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1296 | ArchDefinePpcsq) 1297 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1298 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1299 | ArchDefinePpcgr | ArchDefinePpcsq) 1300 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1301 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1302 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1303 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1304 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1305 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1306 | ArchDefinePpcsq) 1307 .Default(ArchDefineNone); 1308 1309 if (defs & ArchDefineName) 1310 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1311 if (defs & ArchDefinePpcgr) 1312 Builder.defineMacro("_ARCH_PPCGR"); 1313 if (defs & ArchDefinePpcsq) 1314 Builder.defineMacro("_ARCH_PPCSQ"); 1315 if (defs & ArchDefine440) 1316 Builder.defineMacro("_ARCH_440"); 1317 if (defs & ArchDefine603) 1318 Builder.defineMacro("_ARCH_603"); 1319 if (defs & ArchDefine604) 1320 Builder.defineMacro("_ARCH_604"); 1321 if (defs & ArchDefinePwr4) 1322 Builder.defineMacro("_ARCH_PWR4"); 1323 if (defs & ArchDefinePwr5) 1324 Builder.defineMacro("_ARCH_PWR5"); 1325 if (defs & ArchDefinePwr5x) 1326 Builder.defineMacro("_ARCH_PWR5X"); 1327 if (defs & ArchDefinePwr6) 1328 Builder.defineMacro("_ARCH_PWR6"); 1329 if (defs & ArchDefinePwr6x) 1330 Builder.defineMacro("_ARCH_PWR6X"); 1331 if (defs & ArchDefinePwr7) 1332 Builder.defineMacro("_ARCH_PWR7"); 1333 if (defs & ArchDefinePwr8) 1334 Builder.defineMacro("_ARCH_PWR8"); 1335 if (defs & ArchDefinePwr9) 1336 Builder.defineMacro("_ARCH_PWR9"); 1337 if (defs & ArchDefineA2) 1338 Builder.defineMacro("_ARCH_A2"); 1339 if (defs & ArchDefineA2q) { 1340 Builder.defineMacro("_ARCH_A2Q"); 1341 Builder.defineMacro("_ARCH_QP"); 1342 } 1343 1344 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1345 Builder.defineMacro("__bg__"); 1346 Builder.defineMacro("__THW_BLUEGENE__"); 1347 Builder.defineMacro("__bgq__"); 1348 Builder.defineMacro("__TOS_BGQ__"); 1349 } 1350 1351 if (HasVSX) 1352 Builder.defineMacro("__VSX__"); 1353 if (HasP8Vector) 1354 Builder.defineMacro("__POWER8_VECTOR__"); 1355 if (HasP8Crypto) 1356 Builder.defineMacro("__CRYPTO__"); 1357 if (HasHTM) 1358 Builder.defineMacro("__HTM__"); 1359 if (HasFloat128) 1360 Builder.defineMacro("__FLOAT128__"); 1361 if (HasP9Vector) 1362 Builder.defineMacro("__POWER9_VECTOR__"); 1363 1364 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1365 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1366 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1367 if (PointerWidth == 64) 1368 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1369 1370 // FIXME: The following are not yet generated here by Clang, but are 1371 // generated by GCC: 1372 // 1373 // _SOFT_FLOAT_ 1374 // __RECIP_PRECISION__ 1375 // __APPLE_ALTIVEC__ 1376 // __RECIP__ 1377 // __RECIPF__ 1378 // __RSQRTE__ 1379 // __RSQRTEF__ 1380 // _SOFT_DOUBLE_ 1381 // __NO_LWSYNC__ 1382 // __HAVE_BSWAP__ 1383 // __LONGDOUBLE128 1384 // __CMODEL_MEDIUM__ 1385 // __CMODEL_LARGE__ 1386 // _CALL_SYSV 1387 // _CALL_DARWIN 1388 // __NO_FPRS__ 1389 } 1390 1391 // Handle explicit options being passed to the compiler here: if we've 1392 // explicitly turned off vsx and turned on any of: 1393 // - power8-vector 1394 // - direct-move 1395 // - float128 1396 // - power9-vector 1397 // then go ahead and error since the customer has expressed an incompatible 1398 // set of options. 1399 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1400 const std::vector<std::string> &FeaturesVec) { 1401 1402 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1403 FeaturesVec.end()) { 1404 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1405 FeaturesVec.end()) { 1406 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1407 << "-mno-vsx"; 1408 return false; 1409 } 1410 1411 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1412 FeaturesVec.end()) { 1413 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1414 << "-mno-vsx"; 1415 return false; 1416 } 1417 1418 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1419 FeaturesVec.end()) { 1420 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1421 << "-mno-vsx"; 1422 return false; 1423 } 1424 1425 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1426 FeaturesVec.end()) { 1427 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1428 << "-mno-vsx"; 1429 return false; 1430 } 1431 } 1432 1433 return true; 1434 } 1435 1436 bool PPCTargetInfo::initFeatureMap( 1437 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1438 const std::vector<std::string> &FeaturesVec) const { 1439 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1440 .Case("7400", true) 1441 .Case("g4", true) 1442 .Case("7450", true) 1443 .Case("g4+", true) 1444 .Case("970", true) 1445 .Case("g5", true) 1446 .Case("pwr6", true) 1447 .Case("pwr7", true) 1448 .Case("pwr8", true) 1449 .Case("pwr9", true) 1450 .Case("ppc64", true) 1451 .Case("ppc64le", true) 1452 .Default(false); 1453 1454 Features["qpx"] = (CPU == "a2q"); 1455 Features["power9-vector"] = (CPU == "pwr9"); 1456 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1457 .Case("ppc64le", true) 1458 .Case("pwr9", true) 1459 .Case("pwr8", true) 1460 .Default(false); 1461 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1462 .Case("ppc64le", true) 1463 .Case("pwr9", true) 1464 .Case("pwr8", true) 1465 .Default(false); 1466 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1467 .Case("ppc64le", true) 1468 .Case("pwr9", true) 1469 .Case("pwr8", true) 1470 .Case("pwr7", true) 1471 .Default(false); 1472 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1473 .Case("ppc64le", true) 1474 .Case("pwr9", true) 1475 .Case("pwr8", true) 1476 .Case("pwr7", true) 1477 .Default(false); 1478 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1479 .Case("ppc64le", true) 1480 .Case("pwr9", true) 1481 .Case("pwr8", true) 1482 .Default(false); 1483 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1484 .Case("ppc64le", true) 1485 .Case("pwr9", true) 1486 .Case("pwr8", true) 1487 .Case("pwr7", true) 1488 .Default(false); 1489 1490 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1491 return false; 1492 1493 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1494 } 1495 1496 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1497 return llvm::StringSwitch<bool>(Feature) 1498 .Case("powerpc", true) 1499 .Case("vsx", HasVSX) 1500 .Case("power8-vector", HasP8Vector) 1501 .Case("crypto", HasP8Crypto) 1502 .Case("direct-move", HasDirectMove) 1503 .Case("qpx", HasQPX) 1504 .Case("htm", HasHTM) 1505 .Case("bpermd", HasBPERMD) 1506 .Case("extdiv", HasExtDiv) 1507 .Case("float128", HasFloat128) 1508 .Case("power9-vector", HasP9Vector) 1509 .Default(false); 1510 } 1511 1512 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1513 StringRef Name, bool Enabled) const { 1514 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1515 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1516 // incompatible options. 1517 if (Enabled) { 1518 if (Name == "direct-move" || 1519 Name == "power8-vector" || 1520 Name == "float128" || 1521 Name == "power9-vector") { 1522 // power9-vector is really a superset of power8-vector so encode that. 1523 Features[Name] = Features["vsx"] = true; 1524 if (Name == "power9-vector") 1525 Features["power8-vector"] = true; 1526 } else { 1527 Features[Name] = true; 1528 } 1529 } else { 1530 if (Name == "vsx") { 1531 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1532 Features["float128"] = Features["power9-vector"] = false; 1533 } else { 1534 Features[Name] = false; 1535 } 1536 } 1537 } 1538 1539 const char * const PPCTargetInfo::GCCRegNames[] = { 1540 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1541 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1542 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1543 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1544 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1545 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1546 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1547 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1548 "mq", "lr", "ctr", "ap", 1549 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1550 "xer", 1551 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1552 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1553 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1554 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1555 "vrsave", "vscr", 1556 "spe_acc", "spefscr", 1557 "sfp" 1558 }; 1559 1560 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1561 return llvm::makeArrayRef(GCCRegNames); 1562 } 1563 1564 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1565 // While some of these aliases do map to different registers 1566 // they still share the same register name. 1567 { { "0" }, "r0" }, 1568 { { "1"}, "r1" }, 1569 { { "2" }, "r2" }, 1570 { { "3" }, "r3" }, 1571 { { "4" }, "r4" }, 1572 { { "5" }, "r5" }, 1573 { { "6" }, "r6" }, 1574 { { "7" }, "r7" }, 1575 { { "8" }, "r8" }, 1576 { { "9" }, "r9" }, 1577 { { "10" }, "r10" }, 1578 { { "11" }, "r11" }, 1579 { { "12" }, "r12" }, 1580 { { "13" }, "r13" }, 1581 { { "14" }, "r14" }, 1582 { { "15" }, "r15" }, 1583 { { "16" }, "r16" }, 1584 { { "17" }, "r17" }, 1585 { { "18" }, "r18" }, 1586 { { "19" }, "r19" }, 1587 { { "20" }, "r20" }, 1588 { { "21" }, "r21" }, 1589 { { "22" }, "r22" }, 1590 { { "23" }, "r23" }, 1591 { { "24" }, "r24" }, 1592 { { "25" }, "r25" }, 1593 { { "26" }, "r26" }, 1594 { { "27" }, "r27" }, 1595 { { "28" }, "r28" }, 1596 { { "29" }, "r29" }, 1597 { { "30" }, "r30" }, 1598 { { "31" }, "r31" }, 1599 { { "fr0" }, "f0" }, 1600 { { "fr1" }, "f1" }, 1601 { { "fr2" }, "f2" }, 1602 { { "fr3" }, "f3" }, 1603 { { "fr4" }, "f4" }, 1604 { { "fr5" }, "f5" }, 1605 { { "fr6" }, "f6" }, 1606 { { "fr7" }, "f7" }, 1607 { { "fr8" }, "f8" }, 1608 { { "fr9" }, "f9" }, 1609 { { "fr10" }, "f10" }, 1610 { { "fr11" }, "f11" }, 1611 { { "fr12" }, "f12" }, 1612 { { "fr13" }, "f13" }, 1613 { { "fr14" }, "f14" }, 1614 { { "fr15" }, "f15" }, 1615 { { "fr16" }, "f16" }, 1616 { { "fr17" }, "f17" }, 1617 { { "fr18" }, "f18" }, 1618 { { "fr19" }, "f19" }, 1619 { { "fr20" }, "f20" }, 1620 { { "fr21" }, "f21" }, 1621 { { "fr22" }, "f22" }, 1622 { { "fr23" }, "f23" }, 1623 { { "fr24" }, "f24" }, 1624 { { "fr25" }, "f25" }, 1625 { { "fr26" }, "f26" }, 1626 { { "fr27" }, "f27" }, 1627 { { "fr28" }, "f28" }, 1628 { { "fr29" }, "f29" }, 1629 { { "fr30" }, "f30" }, 1630 { { "fr31" }, "f31" }, 1631 { { "cc" }, "cr0" }, 1632 }; 1633 1634 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1635 return llvm::makeArrayRef(GCCRegAliases); 1636 } 1637 1638 class PPC32TargetInfo : public PPCTargetInfo { 1639 public: 1640 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1641 : PPCTargetInfo(Triple, Opts) { 1642 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1643 1644 switch (getTriple().getOS()) { 1645 case llvm::Triple::Linux: 1646 case llvm::Triple::FreeBSD: 1647 case llvm::Triple::NetBSD: 1648 SizeType = UnsignedInt; 1649 PtrDiffType = SignedInt; 1650 IntPtrType = SignedInt; 1651 break; 1652 default: 1653 break; 1654 } 1655 1656 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1657 LongDoubleWidth = LongDoubleAlign = 64; 1658 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1659 } 1660 1661 // PPC32 supports atomics up to 4 bytes. 1662 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1663 } 1664 1665 BuiltinVaListKind getBuiltinVaListKind() const override { 1666 // This is the ELF definition, and is overridden by the Darwin sub-target 1667 return TargetInfo::PowerABIBuiltinVaList; 1668 } 1669 }; 1670 1671 // Note: ABI differences may eventually require us to have a separate 1672 // TargetInfo for little endian. 1673 class PPC64TargetInfo : public PPCTargetInfo { 1674 public: 1675 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1676 : PPCTargetInfo(Triple, Opts) { 1677 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1678 IntMaxType = SignedLong; 1679 Int64Type = SignedLong; 1680 1681 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1682 resetDataLayout("e-m:e-i64:64-n32:64"); 1683 ABI = "elfv2"; 1684 } else { 1685 resetDataLayout("E-m:e-i64:64-n32:64"); 1686 ABI = "elfv1"; 1687 } 1688 1689 switch (getTriple().getOS()) { 1690 case llvm::Triple::FreeBSD: 1691 LongDoubleWidth = LongDoubleAlign = 64; 1692 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1693 break; 1694 case llvm::Triple::NetBSD: 1695 IntMaxType = SignedLongLong; 1696 Int64Type = SignedLongLong; 1697 break; 1698 default: 1699 break; 1700 } 1701 1702 // PPC64 supports atomics up to 8 bytes. 1703 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1704 } 1705 BuiltinVaListKind getBuiltinVaListKind() const override { 1706 return TargetInfo::CharPtrBuiltinVaList; 1707 } 1708 // PPC64 Linux-specific ABI options. 1709 bool setABI(const std::string &Name) override { 1710 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1711 ABI = Name; 1712 return true; 1713 } 1714 return false; 1715 } 1716 }; 1717 1718 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1719 public: 1720 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1721 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1722 HasAlignMac68kSupport = true; 1723 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1724 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1725 LongLongAlign = 32; 1726 SuitableAlign = 128; 1727 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1728 } 1729 BuiltinVaListKind getBuiltinVaListKind() const override { 1730 return TargetInfo::CharPtrBuiltinVaList; 1731 } 1732 }; 1733 1734 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1735 public: 1736 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1737 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1738 HasAlignMac68kSupport = true; 1739 SuitableAlign = 128; 1740 resetDataLayout("E-m:o-i64:64-n32:64"); 1741 } 1742 }; 1743 1744 static const unsigned NVPTXAddrSpaceMap[] = { 1745 1, // opencl_global 1746 3, // opencl_local 1747 4, // opencl_constant 1748 // FIXME: generic has to be added to the target 1749 0, // opencl_generic 1750 1, // cuda_device 1751 4, // cuda_constant 1752 3, // cuda_shared 1753 }; 1754 1755 class NVPTXTargetInfo : public TargetInfo { 1756 static const char *const GCCRegNames[]; 1757 static const Builtin::Info BuiltinInfo[]; 1758 CudaArch GPU; 1759 std::unique_ptr<TargetInfo> HostTarget; 1760 1761 public: 1762 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1763 unsigned TargetPointerWidth) 1764 : TargetInfo(Triple) { 1765 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1766 "NVPTX only supports 32- and 64-bit modes."); 1767 1768 TLSSupported = false; 1769 AddrSpaceMap = &NVPTXAddrSpaceMap; 1770 UseAddrSpaceMapMangling = true; 1771 1772 // Define available target features 1773 // These must be defined in sorted order! 1774 NoAsmVariants = true; 1775 GPU = CudaArch::SM_20; 1776 1777 if (TargetPointerWidth == 32) 1778 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1779 else 1780 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1781 1782 // If possible, get a TargetInfo for our host triple, so we can match its 1783 // types. 1784 llvm::Triple HostTriple(Opts.HostTriple); 1785 if (!HostTriple.isNVPTX()) 1786 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1787 1788 // If no host target, make some guesses about the data layout and return. 1789 if (!HostTarget) { 1790 LongWidth = LongAlign = TargetPointerWidth; 1791 PointerWidth = PointerAlign = TargetPointerWidth; 1792 switch (TargetPointerWidth) { 1793 case 32: 1794 SizeType = TargetInfo::UnsignedInt; 1795 PtrDiffType = TargetInfo::SignedInt; 1796 IntPtrType = TargetInfo::SignedInt; 1797 break; 1798 case 64: 1799 SizeType = TargetInfo::UnsignedLong; 1800 PtrDiffType = TargetInfo::SignedLong; 1801 IntPtrType = TargetInfo::SignedLong; 1802 break; 1803 default: 1804 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1805 } 1806 return; 1807 } 1808 1809 // Copy properties from host target. 1810 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1811 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1812 BoolWidth = HostTarget->getBoolWidth(); 1813 BoolAlign = HostTarget->getBoolAlign(); 1814 IntWidth = HostTarget->getIntWidth(); 1815 IntAlign = HostTarget->getIntAlign(); 1816 HalfWidth = HostTarget->getHalfWidth(); 1817 HalfAlign = HostTarget->getHalfAlign(); 1818 FloatWidth = HostTarget->getFloatWidth(); 1819 FloatAlign = HostTarget->getFloatAlign(); 1820 DoubleWidth = HostTarget->getDoubleWidth(); 1821 DoubleAlign = HostTarget->getDoubleAlign(); 1822 LongWidth = HostTarget->getLongWidth(); 1823 LongAlign = HostTarget->getLongAlign(); 1824 LongLongWidth = HostTarget->getLongLongWidth(); 1825 LongLongAlign = HostTarget->getLongLongAlign(); 1826 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1827 NewAlign = HostTarget->getNewAlign(); 1828 DefaultAlignForAttributeAligned = 1829 HostTarget->getDefaultAlignForAttributeAligned(); 1830 SizeType = HostTarget->getSizeType(); 1831 IntMaxType = HostTarget->getIntMaxType(); 1832 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1833 IntPtrType = HostTarget->getIntPtrType(); 1834 WCharType = HostTarget->getWCharType(); 1835 WIntType = HostTarget->getWIntType(); 1836 Char16Type = HostTarget->getChar16Type(); 1837 Char32Type = HostTarget->getChar32Type(); 1838 Int64Type = HostTarget->getInt64Type(); 1839 SigAtomicType = HostTarget->getSigAtomicType(); 1840 ProcessIDType = HostTarget->getProcessIDType(); 1841 1842 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1843 UseZeroLengthBitfieldAlignment = 1844 HostTarget->useZeroLengthBitfieldAlignment(); 1845 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1846 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1847 1848 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1849 // we need those macros to be identical on host and device, because (among 1850 // other things) they affect which standard library classes are defined, and 1851 // we need all classes to be defined on both the host and device. 1852 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1853 1854 // Properties intentionally not copied from host: 1855 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1856 // host/device boundary. 1857 // - SuitableAlign: Not visible across the host/device boundary, and may 1858 // correctly be different on host/device, e.g. if host has wider vector 1859 // types than device. 1860 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1861 // as its double type, but that's not necessarily true on the host. 1862 // TODO: nvcc emits a warning when using long double on device; we should 1863 // do the same. 1864 } 1865 void getTargetDefines(const LangOptions &Opts, 1866 MacroBuilder &Builder) const override { 1867 Builder.defineMacro("__PTX__"); 1868 Builder.defineMacro("__NVPTX__"); 1869 if (Opts.CUDAIsDevice) { 1870 // Set __CUDA_ARCH__ for the GPU specified. 1871 std::string CUDAArchCode = [this] { 1872 switch (GPU) { 1873 case CudaArch::UNKNOWN: 1874 assert(false && "No GPU arch when compiling CUDA device code."); 1875 return ""; 1876 case CudaArch::SM_20: 1877 return "200"; 1878 case CudaArch::SM_21: 1879 return "210"; 1880 case CudaArch::SM_30: 1881 return "300"; 1882 case CudaArch::SM_32: 1883 return "320"; 1884 case CudaArch::SM_35: 1885 return "350"; 1886 case CudaArch::SM_37: 1887 return "370"; 1888 case CudaArch::SM_50: 1889 return "500"; 1890 case CudaArch::SM_52: 1891 return "520"; 1892 case CudaArch::SM_53: 1893 return "530"; 1894 case CudaArch::SM_60: 1895 return "600"; 1896 case CudaArch::SM_61: 1897 return "610"; 1898 case CudaArch::SM_62: 1899 return "620"; 1900 } 1901 llvm_unreachable("unhandled CudaArch"); 1902 }(); 1903 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1904 } 1905 } 1906 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1907 return llvm::makeArrayRef(BuiltinInfo, 1908 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1909 } 1910 bool 1911 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1912 StringRef CPU, 1913 const std::vector<std::string> &FeaturesVec) const override { 1914 Features["satom"] = GPU >= CudaArch::SM_60; 1915 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1916 } 1917 1918 bool hasFeature(StringRef Feature) const override { 1919 return llvm::StringSwitch<bool>(Feature) 1920 .Cases("ptx", "nvptx", true) 1921 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1922 .Default(false); 1923 } 1924 1925 ArrayRef<const char *> getGCCRegNames() const override; 1926 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1927 // No aliases. 1928 return None; 1929 } 1930 bool validateAsmConstraint(const char *&Name, 1931 TargetInfo::ConstraintInfo &Info) const override { 1932 switch (*Name) { 1933 default: 1934 return false; 1935 case 'c': 1936 case 'h': 1937 case 'r': 1938 case 'l': 1939 case 'f': 1940 case 'd': 1941 Info.setAllowsRegister(); 1942 return true; 1943 } 1944 } 1945 const char *getClobbers() const override { 1946 // FIXME: Is this really right? 1947 return ""; 1948 } 1949 BuiltinVaListKind getBuiltinVaListKind() const override { 1950 // FIXME: implement 1951 return TargetInfo::CharPtrBuiltinVaList; 1952 } 1953 bool setCPU(const std::string &Name) override { 1954 GPU = StringToCudaArch(Name); 1955 return GPU != CudaArch::UNKNOWN; 1956 } 1957 void setSupportedOpenCLOpts() override { 1958 auto &Opts = getSupportedOpenCLOpts(); 1959 Opts.support("cl_clang_storage_class_specifiers"); 1960 Opts.support("cl_khr_gl_sharing"); 1961 Opts.support("cl_khr_icd"); 1962 1963 Opts.support("cl_khr_fp64"); 1964 Opts.support("cl_khr_byte_addressable_store"); 1965 Opts.support("cl_khr_global_int32_base_atomics"); 1966 Opts.support("cl_khr_global_int32_extended_atomics"); 1967 Opts.support("cl_khr_local_int32_base_atomics"); 1968 Opts.support("cl_khr_local_int32_extended_atomics"); 1969 } 1970 1971 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 1972 // CUDA compilations support all of the host's calling conventions. 1973 // 1974 // TODO: We should warn if you apply a non-default CC to anything other than 1975 // a host function. 1976 if (HostTarget) 1977 return HostTarget->checkCallingConvention(CC); 1978 return CCCR_Warning; 1979 } 1980 }; 1981 1982 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1983 #define BUILTIN(ID, TYPE, ATTRS) \ 1984 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1985 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1986 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1987 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 1988 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 1989 #include "clang/Basic/BuiltinsNVPTX.def" 1990 }; 1991 1992 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1993 1994 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1995 return llvm::makeArrayRef(GCCRegNames); 1996 } 1997 1998 static const unsigned AMDGPUAddrSpaceMap[] = { 1999 1, // opencl_global 2000 3, // opencl_local 2001 2, // opencl_constant 2002 4, // opencl_generic 2003 1, // cuda_device 2004 2, // cuda_constant 2005 3 // cuda_shared 2006 }; 2007 2008 // If you edit the description strings, make sure you update 2009 // getPointerWidthV(). 2010 2011 static const char *const DataLayoutStringR600 = 2012 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2013 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2014 2015 static const char *const DataLayoutStringSI = 2016 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2017 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2018 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2019 2020 class AMDGPUTargetInfo final : public TargetInfo { 2021 static const Builtin::Info BuiltinInfo[]; 2022 static const char * const GCCRegNames[]; 2023 2024 /// \brief The GPU profiles supported by the AMDGPU target. 2025 enum GPUKind { 2026 GK_NONE, 2027 GK_R600, 2028 GK_R600_DOUBLE_OPS, 2029 GK_R700, 2030 GK_R700_DOUBLE_OPS, 2031 GK_EVERGREEN, 2032 GK_EVERGREEN_DOUBLE_OPS, 2033 GK_NORTHERN_ISLANDS, 2034 GK_CAYMAN, 2035 GK_GFX6, 2036 GK_GFX7, 2037 GK_GFX8 2038 } GPU; 2039 2040 bool hasFP64:1; 2041 bool hasFMAF:1; 2042 bool hasLDEXPF:1; 2043 bool hasFullSpeedFP32Denorms:1; 2044 2045 static bool isAMDGCN(const llvm::Triple &TT) { 2046 return TT.getArch() == llvm::Triple::amdgcn; 2047 } 2048 2049 public: 2050 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2051 : TargetInfo(Triple) , 2052 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2053 hasFP64(false), 2054 hasFMAF(false), 2055 hasLDEXPF(false), 2056 hasFullSpeedFP32Denorms(false){ 2057 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2058 hasFP64 = true; 2059 hasFMAF = true; 2060 hasLDEXPF = true; 2061 } 2062 2063 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2064 DataLayoutStringSI : DataLayoutStringR600); 2065 2066 AddrSpaceMap = &AMDGPUAddrSpaceMap; 2067 UseAddrSpaceMapMangling = true; 2068 } 2069 2070 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2071 if (GPU <= GK_CAYMAN) 2072 return 32; 2073 2074 switch(AddrSpace) { 2075 default: 2076 return 64; 2077 case 0: 2078 case 3: 2079 case 5: 2080 return 32; 2081 } 2082 } 2083 2084 uint64_t getMaxPointerWidth() const override { 2085 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2086 } 2087 2088 const char * getClobbers() const override { 2089 return ""; 2090 } 2091 2092 ArrayRef<const char *> getGCCRegNames() const override; 2093 2094 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2095 return None; 2096 } 2097 2098 bool validateAsmConstraint(const char *&Name, 2099 TargetInfo::ConstraintInfo &Info) const override { 2100 switch (*Name) { 2101 default: break; 2102 case 'v': // vgpr 2103 case 's': // sgpr 2104 Info.setAllowsRegister(); 2105 return true; 2106 } 2107 return false; 2108 } 2109 2110 bool initFeatureMap(llvm::StringMap<bool> &Features, 2111 DiagnosticsEngine &Diags, StringRef CPU, 2112 const std::vector<std::string> &FeatureVec) const override; 2113 2114 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2115 TargetOptions &TargetOpts) const override { 2116 bool hasFP32Denormals = false; 2117 bool hasFP64Denormals = false; 2118 for (auto &I : TargetOpts.FeaturesAsWritten) { 2119 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2120 hasFP32Denormals = true; 2121 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2122 hasFP64Denormals = true; 2123 } 2124 if (!hasFP32Denormals) 2125 TargetOpts.Features.push_back((Twine(hasFullSpeedFP32Denorms && 2126 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2127 // Always do not flush fp64 or fp16 denorms. 2128 if (!hasFP64Denormals && hasFP64) 2129 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2130 } 2131 2132 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2133 return llvm::makeArrayRef(BuiltinInfo, 2134 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2135 } 2136 2137 void getTargetDefines(const LangOptions &Opts, 2138 MacroBuilder &Builder) const override { 2139 if (getTriple().getArch() == llvm::Triple::amdgcn) 2140 Builder.defineMacro("__AMDGCN__"); 2141 else 2142 Builder.defineMacro("__R600__"); 2143 2144 if (hasFMAF) 2145 Builder.defineMacro("__HAS_FMAF__"); 2146 if (hasLDEXPF) 2147 Builder.defineMacro("__HAS_LDEXPF__"); 2148 if (hasFP64) 2149 Builder.defineMacro("__HAS_FP64__"); 2150 } 2151 2152 BuiltinVaListKind getBuiltinVaListKind() const override { 2153 return TargetInfo::CharPtrBuiltinVaList; 2154 } 2155 2156 static GPUKind parseR600Name(StringRef Name) { 2157 return llvm::StringSwitch<GPUKind>(Name) 2158 .Case("r600" , GK_R600) 2159 .Case("rv610", GK_R600) 2160 .Case("rv620", GK_R600) 2161 .Case("rv630", GK_R600) 2162 .Case("rv635", GK_R600) 2163 .Case("rs780", GK_R600) 2164 .Case("rs880", GK_R600) 2165 .Case("rv670", GK_R600_DOUBLE_OPS) 2166 .Case("rv710", GK_R700) 2167 .Case("rv730", GK_R700) 2168 .Case("rv740", GK_R700_DOUBLE_OPS) 2169 .Case("rv770", GK_R700_DOUBLE_OPS) 2170 .Case("palm", GK_EVERGREEN) 2171 .Case("cedar", GK_EVERGREEN) 2172 .Case("sumo", GK_EVERGREEN) 2173 .Case("sumo2", GK_EVERGREEN) 2174 .Case("redwood", GK_EVERGREEN) 2175 .Case("juniper", GK_EVERGREEN) 2176 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2177 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2178 .Case("barts", GK_NORTHERN_ISLANDS) 2179 .Case("turks", GK_NORTHERN_ISLANDS) 2180 .Case("caicos", GK_NORTHERN_ISLANDS) 2181 .Case("cayman", GK_CAYMAN) 2182 .Case("aruba", GK_CAYMAN) 2183 .Default(GK_NONE); 2184 } 2185 2186 static GPUKind parseAMDGCNName(StringRef Name) { 2187 return llvm::StringSwitch<GPUKind>(Name) 2188 .Case("tahiti", GK_GFX6) 2189 .Case("pitcairn", GK_GFX6) 2190 .Case("verde", GK_GFX6) 2191 .Case("oland", GK_GFX6) 2192 .Case("hainan", GK_GFX6) 2193 .Case("bonaire", GK_GFX7) 2194 .Case("kabini", GK_GFX7) 2195 .Case("kaveri", GK_GFX7) 2196 .Case("hawaii", GK_GFX7) 2197 .Case("mullins", GK_GFX7) 2198 .Case("gfx700", GK_GFX7) 2199 .Case("gfx701", GK_GFX7) 2200 .Case("gfx702", GK_GFX7) 2201 .Case("tonga", GK_GFX8) 2202 .Case("iceland", GK_GFX8) 2203 .Case("carrizo", GK_GFX8) 2204 .Case("fiji", GK_GFX8) 2205 .Case("stoney", GK_GFX8) 2206 .Case("polaris10", GK_GFX8) 2207 .Case("polaris11", GK_GFX8) 2208 .Case("gfx800", GK_GFX8) 2209 .Case("gfx801", GK_GFX8) 2210 .Case("gfx802", GK_GFX8) 2211 .Case("gfx803", GK_GFX8) 2212 .Case("gfx804", GK_GFX8) 2213 .Case("gfx810", GK_GFX8) 2214 .Default(GK_NONE); 2215 } 2216 2217 bool setCPU(const std::string &Name) override { 2218 if (getTriple().getArch() == llvm::Triple::amdgcn) 2219 GPU = parseAMDGCNName(Name); 2220 else 2221 GPU = parseR600Name(Name); 2222 2223 return GPU != GK_NONE; 2224 } 2225 2226 void setSupportedOpenCLOpts() override { 2227 auto &Opts = getSupportedOpenCLOpts(); 2228 Opts.support("cl_clang_storage_class_specifiers"); 2229 Opts.support("cl_khr_icd"); 2230 2231 if (hasFP64) 2232 Opts.support("cl_khr_fp64"); 2233 if (GPU >= GK_EVERGREEN) { 2234 Opts.support("cl_khr_byte_addressable_store"); 2235 Opts.support("cl_khr_global_int32_base_atomics"); 2236 Opts.support("cl_khr_global_int32_extended_atomics"); 2237 Opts.support("cl_khr_local_int32_base_atomics"); 2238 Opts.support("cl_khr_local_int32_extended_atomics"); 2239 } 2240 if (GPU >= GK_GFX6) { 2241 Opts.support("cl_khr_fp16"); 2242 Opts.support("cl_khr_int64_base_atomics"); 2243 Opts.support("cl_khr_int64_extended_atomics"); 2244 Opts.support("cl_khr_mipmap_image"); 2245 Opts.support("cl_khr_subgroups"); 2246 Opts.support("cl_khr_3d_image_writes"); 2247 Opts.support("cl_amd_media_ops"); 2248 Opts.support("cl_amd_media_ops2"); 2249 } 2250 } 2251 2252 LangAS::ID getOpenCLImageAddrSpace() const override { 2253 return LangAS::opencl_constant; 2254 } 2255 2256 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2257 switch (CC) { 2258 default: 2259 return CCCR_Warning; 2260 case CC_C: 2261 case CC_OpenCLKernel: 2262 return CCCR_OK; 2263 } 2264 } 2265 2266 // In amdgcn target the null pointer in global, constant, and generic 2267 // address space has value 0 but in private and local address space has 2268 // value ~0. 2269 uint64_t getNullPointerValue(unsigned AS) const override { 2270 return AS != LangAS::opencl_local && AS != 0 ? 0 : ~0; 2271 } 2272 }; 2273 2274 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2275 #define BUILTIN(ID, TYPE, ATTRS) \ 2276 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2277 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2278 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2279 #include "clang/Basic/BuiltinsAMDGPU.def" 2280 }; 2281 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2282 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2283 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2284 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2285 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2286 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2287 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2288 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2289 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2290 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2291 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2292 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2293 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2294 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2295 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2296 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2297 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2298 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2299 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2300 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2301 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2302 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2303 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2304 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2305 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2306 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2307 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2308 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2309 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2310 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2311 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2312 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2313 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2314 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2315 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2316 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2317 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2318 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2319 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2320 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2321 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2322 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2323 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2324 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2325 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2326 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2327 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2328 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2329 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2330 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2331 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2332 }; 2333 2334 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2335 return llvm::makeArrayRef(GCCRegNames); 2336 } 2337 2338 bool AMDGPUTargetInfo::initFeatureMap( 2339 llvm::StringMap<bool> &Features, 2340 DiagnosticsEngine &Diags, StringRef CPU, 2341 const std::vector<std::string> &FeatureVec) const { 2342 2343 // XXX - What does the member GPU mean if device name string passed here? 2344 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2345 if (CPU.empty()) 2346 CPU = "tahiti"; 2347 2348 switch (parseAMDGCNName(CPU)) { 2349 case GK_GFX6: 2350 case GK_GFX7: 2351 break; 2352 2353 case GK_GFX8: 2354 Features["s-memrealtime"] = true; 2355 Features["16-bit-insts"] = true; 2356 break; 2357 2358 case GK_NONE: 2359 return false; 2360 default: 2361 llvm_unreachable("unhandled subtarget"); 2362 } 2363 } else { 2364 if (CPU.empty()) 2365 CPU = "r600"; 2366 2367 switch (parseR600Name(CPU)) { 2368 case GK_R600: 2369 case GK_R700: 2370 case GK_EVERGREEN: 2371 case GK_NORTHERN_ISLANDS: 2372 break; 2373 case GK_R600_DOUBLE_OPS: 2374 case GK_R700_DOUBLE_OPS: 2375 case GK_EVERGREEN_DOUBLE_OPS: 2376 case GK_CAYMAN: 2377 Features["fp64"] = true; 2378 break; 2379 case GK_NONE: 2380 return false; 2381 default: 2382 llvm_unreachable("unhandled subtarget"); 2383 } 2384 } 2385 2386 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2387 } 2388 2389 const Builtin::Info BuiltinInfoX86[] = { 2390 #define BUILTIN(ID, TYPE, ATTRS) \ 2391 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2392 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2393 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2394 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2395 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2396 #include "clang/Basic/BuiltinsX86.def" 2397 2398 #define BUILTIN(ID, TYPE, ATTRS) \ 2399 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2400 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2401 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2402 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2403 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2404 #include "clang/Basic/BuiltinsX86_64.def" 2405 }; 2406 2407 2408 static const char* const GCCRegNames[] = { 2409 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2410 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2411 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2412 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2413 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2414 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2415 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2416 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2417 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2418 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2419 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2420 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2421 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2422 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2423 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2424 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2425 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2426 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2427 }; 2428 2429 const TargetInfo::AddlRegName AddlRegNames[] = { 2430 { { "al", "ah", "eax", "rax" }, 0 }, 2431 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2432 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2433 { { "dl", "dh", "edx", "rdx" }, 1 }, 2434 { { "esi", "rsi" }, 4 }, 2435 { { "edi", "rdi" }, 5 }, 2436 { { "esp", "rsp" }, 7 }, 2437 { { "ebp", "rbp" }, 6 }, 2438 { { "r8d", "r8w", "r8b" }, 38 }, 2439 { { "r9d", "r9w", "r9b" }, 39 }, 2440 { { "r10d", "r10w", "r10b" }, 40 }, 2441 { { "r11d", "r11w", "r11b" }, 41 }, 2442 { { "r12d", "r12w", "r12b" }, 42 }, 2443 { { "r13d", "r13w", "r13b" }, 43 }, 2444 { { "r14d", "r14w", "r14b" }, 44 }, 2445 { { "r15d", "r15w", "r15b" }, 45 }, 2446 }; 2447 2448 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2449 // most of the implementation can be shared. 2450 class X86TargetInfo : public TargetInfo { 2451 enum X86SSEEnum { 2452 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2453 } SSELevel = NoSSE; 2454 enum MMX3DNowEnum { 2455 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2456 } MMX3DNowLevel = NoMMX3DNow; 2457 enum XOPEnum { 2458 NoXOP, 2459 SSE4A, 2460 FMA4, 2461 XOP 2462 } XOPLevel = NoXOP; 2463 2464 bool HasAES = false; 2465 bool HasPCLMUL = false; 2466 bool HasLZCNT = false; 2467 bool HasRDRND = false; 2468 bool HasFSGSBASE = false; 2469 bool HasBMI = false; 2470 bool HasBMI2 = false; 2471 bool HasPOPCNT = false; 2472 bool HasRTM = false; 2473 bool HasPRFCHW = false; 2474 bool HasRDSEED = false; 2475 bool HasADX = false; 2476 bool HasTBM = false; 2477 bool HasFMA = false; 2478 bool HasF16C = false; 2479 bool HasAVX512CD = false; 2480 bool HasAVX512ER = false; 2481 bool HasAVX512PF = false; 2482 bool HasAVX512DQ = false; 2483 bool HasAVX512BW = false; 2484 bool HasAVX512VL = false; 2485 bool HasAVX512VBMI = false; 2486 bool HasAVX512IFMA = false; 2487 bool HasSHA = false; 2488 bool HasMPX = false; 2489 bool HasSGX = false; 2490 bool HasCX16 = false; 2491 bool HasFXSR = false; 2492 bool HasXSAVE = false; 2493 bool HasXSAVEOPT = false; 2494 bool HasXSAVEC = false; 2495 bool HasXSAVES = false; 2496 bool HasMWAITX = false; 2497 bool HasCLZERO = false; 2498 bool HasPKU = false; 2499 bool HasCLFLUSHOPT = false; 2500 bool HasCLWB = false; 2501 bool HasMOVBE = false; 2502 bool HasPREFETCHWT1 = false; 2503 2504 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2505 /// 2506 /// Each enumeration represents a particular CPU supported by Clang. These 2507 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2508 enum CPUKind { 2509 CK_Generic, 2510 2511 /// \name i386 2512 /// i386-generation processors. 2513 //@{ 2514 CK_i386, 2515 //@} 2516 2517 /// \name i486 2518 /// i486-generation processors. 2519 //@{ 2520 CK_i486, 2521 CK_WinChipC6, 2522 CK_WinChip2, 2523 CK_C3, 2524 //@} 2525 2526 /// \name i586 2527 /// i586-generation processors, P5 microarchitecture based. 2528 //@{ 2529 CK_i586, 2530 CK_Pentium, 2531 CK_PentiumMMX, 2532 //@} 2533 2534 /// \name i686 2535 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2536 //@{ 2537 CK_i686, 2538 CK_PentiumPro, 2539 CK_Pentium2, 2540 CK_Pentium3, 2541 CK_Pentium3M, 2542 CK_PentiumM, 2543 CK_C3_2, 2544 2545 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2546 /// Clang however has some logic to suport this. 2547 // FIXME: Warn, deprecate, and potentially remove this. 2548 CK_Yonah, 2549 //@} 2550 2551 /// \name Netburst 2552 /// Netburst microarchitecture based processors. 2553 //@{ 2554 CK_Pentium4, 2555 CK_Pentium4M, 2556 CK_Prescott, 2557 CK_Nocona, 2558 //@} 2559 2560 /// \name Core 2561 /// Core microarchitecture based processors. 2562 //@{ 2563 CK_Core2, 2564 2565 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2566 /// codename which GCC no longer accepts as an option to -march, but Clang 2567 /// has some logic for recognizing it. 2568 // FIXME: Warn, deprecate, and potentially remove this. 2569 CK_Penryn, 2570 //@} 2571 2572 /// \name Atom 2573 /// Atom processors 2574 //@{ 2575 CK_Bonnell, 2576 CK_Silvermont, 2577 //@} 2578 2579 /// \name Nehalem 2580 /// Nehalem microarchitecture based processors. 2581 CK_Nehalem, 2582 2583 /// \name Westmere 2584 /// Westmere microarchitecture based processors. 2585 CK_Westmere, 2586 2587 /// \name Sandy Bridge 2588 /// Sandy Bridge microarchitecture based processors. 2589 CK_SandyBridge, 2590 2591 /// \name Ivy Bridge 2592 /// Ivy Bridge microarchitecture based processors. 2593 CK_IvyBridge, 2594 2595 /// \name Haswell 2596 /// Haswell microarchitecture based processors. 2597 CK_Haswell, 2598 2599 /// \name Broadwell 2600 /// Broadwell microarchitecture based processors. 2601 CK_Broadwell, 2602 2603 /// \name Skylake Client 2604 /// Skylake client microarchitecture based processors. 2605 CK_SkylakeClient, 2606 2607 /// \name Skylake Server 2608 /// Skylake server microarchitecture based processors. 2609 CK_SkylakeServer, 2610 2611 /// \name Cannonlake Client 2612 /// Cannonlake client microarchitecture based processors. 2613 CK_Cannonlake, 2614 2615 /// \name Knights Landing 2616 /// Knights Landing processor. 2617 CK_KNL, 2618 2619 /// \name Lakemont 2620 /// Lakemont microarchitecture based processors. 2621 CK_Lakemont, 2622 2623 /// \name K6 2624 /// K6 architecture processors. 2625 //@{ 2626 CK_K6, 2627 CK_K6_2, 2628 CK_K6_3, 2629 //@} 2630 2631 /// \name K7 2632 /// K7 architecture processors. 2633 //@{ 2634 CK_Athlon, 2635 CK_AthlonThunderbird, 2636 CK_Athlon4, 2637 CK_AthlonXP, 2638 CK_AthlonMP, 2639 //@} 2640 2641 /// \name K8 2642 /// K8 architecture processors. 2643 //@{ 2644 CK_Athlon64, 2645 CK_Athlon64SSE3, 2646 CK_AthlonFX, 2647 CK_K8, 2648 CK_K8SSE3, 2649 CK_Opteron, 2650 CK_OpteronSSE3, 2651 CK_AMDFAM10, 2652 //@} 2653 2654 /// \name Bobcat 2655 /// Bobcat architecture processors. 2656 //@{ 2657 CK_BTVER1, 2658 CK_BTVER2, 2659 //@} 2660 2661 /// \name Bulldozer 2662 /// Bulldozer architecture processors. 2663 //@{ 2664 CK_BDVER1, 2665 CK_BDVER2, 2666 CK_BDVER3, 2667 CK_BDVER4, 2668 //@} 2669 2670 /// \name zen 2671 /// Zen architecture processors. 2672 //@{ 2673 CK_ZNVER1, 2674 //@} 2675 2676 /// This specification is deprecated and will be removed in the future. 2677 /// Users should prefer \see CK_K8. 2678 // FIXME: Warn on this when the CPU is set to it. 2679 //@{ 2680 CK_x86_64, 2681 //@} 2682 2683 /// \name Geode 2684 /// Geode processors. 2685 //@{ 2686 CK_Geode 2687 //@} 2688 } CPU = CK_Generic; 2689 2690 CPUKind getCPUKind(StringRef CPU) const { 2691 return llvm::StringSwitch<CPUKind>(CPU) 2692 .Case("i386", CK_i386) 2693 .Case("i486", CK_i486) 2694 .Case("winchip-c6", CK_WinChipC6) 2695 .Case("winchip2", CK_WinChip2) 2696 .Case("c3", CK_C3) 2697 .Case("i586", CK_i586) 2698 .Case("pentium", CK_Pentium) 2699 .Case("pentium-mmx", CK_PentiumMMX) 2700 .Case("i686", CK_i686) 2701 .Case("pentiumpro", CK_PentiumPro) 2702 .Case("pentium2", CK_Pentium2) 2703 .Case("pentium3", CK_Pentium3) 2704 .Case("pentium3m", CK_Pentium3M) 2705 .Case("pentium-m", CK_PentiumM) 2706 .Case("c3-2", CK_C3_2) 2707 .Case("yonah", CK_Yonah) 2708 .Case("pentium4", CK_Pentium4) 2709 .Case("pentium4m", CK_Pentium4M) 2710 .Case("prescott", CK_Prescott) 2711 .Case("nocona", CK_Nocona) 2712 .Case("core2", CK_Core2) 2713 .Case("penryn", CK_Penryn) 2714 .Case("bonnell", CK_Bonnell) 2715 .Case("atom", CK_Bonnell) // Legacy name. 2716 .Case("silvermont", CK_Silvermont) 2717 .Case("slm", CK_Silvermont) // Legacy name. 2718 .Case("nehalem", CK_Nehalem) 2719 .Case("corei7", CK_Nehalem) // Legacy name. 2720 .Case("westmere", CK_Westmere) 2721 .Case("sandybridge", CK_SandyBridge) 2722 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2723 .Case("ivybridge", CK_IvyBridge) 2724 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2725 .Case("haswell", CK_Haswell) 2726 .Case("core-avx2", CK_Haswell) // Legacy name. 2727 .Case("broadwell", CK_Broadwell) 2728 .Case("skylake", CK_SkylakeClient) 2729 .Case("skylake-avx512", CK_SkylakeServer) 2730 .Case("skx", CK_SkylakeServer) // Legacy name. 2731 .Case("cannonlake", CK_Cannonlake) 2732 .Case("knl", CK_KNL) 2733 .Case("lakemont", CK_Lakemont) 2734 .Case("k6", CK_K6) 2735 .Case("k6-2", CK_K6_2) 2736 .Case("k6-3", CK_K6_3) 2737 .Case("athlon", CK_Athlon) 2738 .Case("athlon-tbird", CK_AthlonThunderbird) 2739 .Case("athlon-4", CK_Athlon4) 2740 .Case("athlon-xp", CK_AthlonXP) 2741 .Case("athlon-mp", CK_AthlonMP) 2742 .Case("athlon64", CK_Athlon64) 2743 .Case("athlon64-sse3", CK_Athlon64SSE3) 2744 .Case("athlon-fx", CK_AthlonFX) 2745 .Case("k8", CK_K8) 2746 .Case("k8-sse3", CK_K8SSE3) 2747 .Case("opteron", CK_Opteron) 2748 .Case("opteron-sse3", CK_OpteronSSE3) 2749 .Case("barcelona", CK_AMDFAM10) 2750 .Case("amdfam10", CK_AMDFAM10) 2751 .Case("btver1", CK_BTVER1) 2752 .Case("btver2", CK_BTVER2) 2753 .Case("bdver1", CK_BDVER1) 2754 .Case("bdver2", CK_BDVER2) 2755 .Case("bdver3", CK_BDVER3) 2756 .Case("bdver4", CK_BDVER4) 2757 .Case("znver1", CK_ZNVER1) 2758 .Case("x86-64", CK_x86_64) 2759 .Case("geode", CK_Geode) 2760 .Default(CK_Generic); 2761 } 2762 2763 enum FPMathKind { 2764 FP_Default, 2765 FP_SSE, 2766 FP_387 2767 } FPMath = FP_Default; 2768 2769 public: 2770 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2771 : TargetInfo(Triple) { 2772 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2773 } 2774 unsigned getFloatEvalMethod() const override { 2775 // X87 evaluates with 80 bits "long double" precision. 2776 return SSELevel == NoSSE ? 2 : 0; 2777 } 2778 ArrayRef<const char *> getGCCRegNames() const override { 2779 return llvm::makeArrayRef(GCCRegNames); 2780 } 2781 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2782 return None; 2783 } 2784 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2785 return llvm::makeArrayRef(AddlRegNames); 2786 } 2787 bool validateCpuSupports(StringRef Name) const override; 2788 bool validateAsmConstraint(const char *&Name, 2789 TargetInfo::ConstraintInfo &info) const override; 2790 2791 bool validateGlobalRegisterVariable(StringRef RegName, 2792 unsigned RegSize, 2793 bool &HasSizeMismatch) const override { 2794 // esp and ebp are the only 32-bit registers the x86 backend can currently 2795 // handle. 2796 if (RegName.equals("esp") || RegName.equals("ebp")) { 2797 // Check that the register size is 32-bit. 2798 HasSizeMismatch = RegSize != 32; 2799 return true; 2800 } 2801 2802 return false; 2803 } 2804 2805 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2806 2807 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2808 2809 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2810 2811 std::string convertConstraint(const char *&Constraint) const override; 2812 const char *getClobbers() const override { 2813 return "~{dirflag},~{fpsr},~{flags}"; 2814 } 2815 2816 StringRef getConstraintRegister(const StringRef &Constraint, 2817 const StringRef &Expression) const override { 2818 StringRef::iterator I, E; 2819 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 2820 if (isalpha(*I)) 2821 break; 2822 } 2823 if (I == E) 2824 return ""; 2825 switch (*I) { 2826 // For the register constraints, return the matching register name 2827 case 'a': 2828 return "ax"; 2829 case 'b': 2830 return "bx"; 2831 case 'c': 2832 return "cx"; 2833 case 'd': 2834 return "dx"; 2835 case 'S': 2836 return "si"; 2837 case 'D': 2838 return "di"; 2839 // In case the constraint is 'r' we need to return Expression 2840 case 'r': 2841 return Expression; 2842 default: 2843 // Default value if there is no constraint for the register 2844 return ""; 2845 } 2846 return ""; 2847 } 2848 2849 void getTargetDefines(const LangOptions &Opts, 2850 MacroBuilder &Builder) const override; 2851 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2852 bool Enabled); 2853 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2854 bool Enabled); 2855 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2856 bool Enabled); 2857 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2858 StringRef Name, bool Enabled) const override { 2859 setFeatureEnabledImpl(Features, Name, Enabled); 2860 } 2861 // This exists purely to cut down on the number of virtual calls in 2862 // initFeatureMap which calls this repeatedly. 2863 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2864 StringRef Name, bool Enabled); 2865 bool 2866 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2867 StringRef CPU, 2868 const std::vector<std::string> &FeaturesVec) const override; 2869 bool hasFeature(StringRef Feature) const override; 2870 bool handleTargetFeatures(std::vector<std::string> &Features, 2871 DiagnosticsEngine &Diags) override; 2872 StringRef getABI() const override { 2873 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2874 return "avx512"; 2875 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2876 return "avx"; 2877 if (getTriple().getArch() == llvm::Triple::x86 && 2878 MMX3DNowLevel == NoMMX3DNow) 2879 return "no-mmx"; 2880 return ""; 2881 } 2882 bool setCPU(const std::string &Name) override { 2883 CPU = getCPUKind(Name); 2884 2885 // Perform any per-CPU checks necessary to determine if this CPU is 2886 // acceptable. 2887 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2888 // invalid without explaining *why*. 2889 switch (CPU) { 2890 case CK_Generic: 2891 // No processor selected! 2892 return false; 2893 2894 case CK_i386: 2895 case CK_i486: 2896 case CK_WinChipC6: 2897 case CK_WinChip2: 2898 case CK_C3: 2899 case CK_i586: 2900 case CK_Pentium: 2901 case CK_PentiumMMX: 2902 case CK_i686: 2903 case CK_PentiumPro: 2904 case CK_Pentium2: 2905 case CK_Pentium3: 2906 case CK_Pentium3M: 2907 case CK_PentiumM: 2908 case CK_Yonah: 2909 case CK_C3_2: 2910 case CK_Pentium4: 2911 case CK_Pentium4M: 2912 case CK_Lakemont: 2913 case CK_Prescott: 2914 case CK_K6: 2915 case CK_K6_2: 2916 case CK_K6_3: 2917 case CK_Athlon: 2918 case CK_AthlonThunderbird: 2919 case CK_Athlon4: 2920 case CK_AthlonXP: 2921 case CK_AthlonMP: 2922 case CK_Geode: 2923 // Only accept certain architectures when compiling in 32-bit mode. 2924 if (getTriple().getArch() != llvm::Triple::x86) 2925 return false; 2926 2927 // Fallthrough 2928 case CK_Nocona: 2929 case CK_Core2: 2930 case CK_Penryn: 2931 case CK_Bonnell: 2932 case CK_Silvermont: 2933 case CK_Nehalem: 2934 case CK_Westmere: 2935 case CK_SandyBridge: 2936 case CK_IvyBridge: 2937 case CK_Haswell: 2938 case CK_Broadwell: 2939 case CK_SkylakeClient: 2940 case CK_SkylakeServer: 2941 case CK_Cannonlake: 2942 case CK_KNL: 2943 case CK_Athlon64: 2944 case CK_Athlon64SSE3: 2945 case CK_AthlonFX: 2946 case CK_K8: 2947 case CK_K8SSE3: 2948 case CK_Opteron: 2949 case CK_OpteronSSE3: 2950 case CK_AMDFAM10: 2951 case CK_BTVER1: 2952 case CK_BTVER2: 2953 case CK_BDVER1: 2954 case CK_BDVER2: 2955 case CK_BDVER3: 2956 case CK_BDVER4: 2957 case CK_ZNVER1: 2958 case CK_x86_64: 2959 return true; 2960 } 2961 llvm_unreachable("Unhandled CPU kind"); 2962 } 2963 2964 bool setFPMath(StringRef Name) override; 2965 2966 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2967 // Most of the non-ARM calling conventions are i386 conventions. 2968 switch (CC) { 2969 case CC_X86ThisCall: 2970 case CC_X86FastCall: 2971 case CC_X86StdCall: 2972 case CC_X86VectorCall: 2973 case CC_X86RegCall: 2974 case CC_C: 2975 case CC_Swift: 2976 case CC_X86Pascal: 2977 case CC_IntelOclBicc: 2978 return CCCR_OK; 2979 default: 2980 return CCCR_Warning; 2981 } 2982 } 2983 2984 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2985 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2986 } 2987 2988 bool hasSjLjLowering() const override { 2989 return true; 2990 } 2991 2992 void setSupportedOpenCLOpts() override { 2993 getSupportedOpenCLOpts().supportAll(); 2994 } 2995 }; 2996 2997 bool X86TargetInfo::setFPMath(StringRef Name) { 2998 if (Name == "387") { 2999 FPMath = FP_387; 3000 return true; 3001 } 3002 if (Name == "sse") { 3003 FPMath = FP_SSE; 3004 return true; 3005 } 3006 return false; 3007 } 3008 3009 bool X86TargetInfo::initFeatureMap( 3010 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3011 const std::vector<std::string> &FeaturesVec) const { 3012 // FIXME: This *really* should not be here. 3013 // X86_64 always has SSE2. 3014 if (getTriple().getArch() == llvm::Triple::x86_64) 3015 setFeatureEnabledImpl(Features, "sse2", true); 3016 3017 const CPUKind Kind = getCPUKind(CPU); 3018 3019 // Enable X87 for all X86 processors but Lakemont. 3020 if (Kind != CK_Lakemont) 3021 setFeatureEnabledImpl(Features, "x87", true); 3022 3023 switch (Kind) { 3024 case CK_Generic: 3025 case CK_i386: 3026 case CK_i486: 3027 case CK_i586: 3028 case CK_Pentium: 3029 case CK_i686: 3030 case CK_PentiumPro: 3031 case CK_Lakemont: 3032 break; 3033 case CK_PentiumMMX: 3034 case CK_Pentium2: 3035 case CK_K6: 3036 case CK_WinChipC6: 3037 setFeatureEnabledImpl(Features, "mmx", true); 3038 break; 3039 case CK_Pentium3: 3040 case CK_Pentium3M: 3041 case CK_C3_2: 3042 setFeatureEnabledImpl(Features, "sse", true); 3043 setFeatureEnabledImpl(Features, "fxsr", true); 3044 break; 3045 case CK_PentiumM: 3046 case CK_Pentium4: 3047 case CK_Pentium4M: 3048 case CK_x86_64: 3049 setFeatureEnabledImpl(Features, "sse2", true); 3050 setFeatureEnabledImpl(Features, "fxsr", true); 3051 break; 3052 case CK_Yonah: 3053 case CK_Prescott: 3054 case CK_Nocona: 3055 setFeatureEnabledImpl(Features, "sse3", true); 3056 setFeatureEnabledImpl(Features, "fxsr", true); 3057 setFeatureEnabledImpl(Features, "cx16", true); 3058 break; 3059 case CK_Core2: 3060 case CK_Bonnell: 3061 setFeatureEnabledImpl(Features, "ssse3", true); 3062 setFeatureEnabledImpl(Features, "fxsr", true); 3063 setFeatureEnabledImpl(Features, "cx16", true); 3064 break; 3065 case CK_Penryn: 3066 setFeatureEnabledImpl(Features, "sse4.1", true); 3067 setFeatureEnabledImpl(Features, "fxsr", true); 3068 setFeatureEnabledImpl(Features, "cx16", true); 3069 break; 3070 case CK_Cannonlake: 3071 setFeatureEnabledImpl(Features, "avx512ifma", true); 3072 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3073 setFeatureEnabledImpl(Features, "sha", true); 3074 LLVM_FALLTHROUGH; 3075 case CK_SkylakeServer: 3076 setFeatureEnabledImpl(Features, "avx512f", true); 3077 setFeatureEnabledImpl(Features, "avx512cd", true); 3078 setFeatureEnabledImpl(Features, "avx512dq", true); 3079 setFeatureEnabledImpl(Features, "avx512bw", true); 3080 setFeatureEnabledImpl(Features, "avx512vl", true); 3081 setFeatureEnabledImpl(Features, "pku", true); 3082 setFeatureEnabledImpl(Features, "clwb", true); 3083 LLVM_FALLTHROUGH; 3084 case CK_SkylakeClient: 3085 setFeatureEnabledImpl(Features, "xsavec", true); 3086 setFeatureEnabledImpl(Features, "xsaves", true); 3087 setFeatureEnabledImpl(Features, "mpx", true); 3088 setFeatureEnabledImpl(Features, "sgx", true); 3089 setFeatureEnabledImpl(Features, "clflushopt", true); 3090 LLVM_FALLTHROUGH; 3091 case CK_Broadwell: 3092 setFeatureEnabledImpl(Features, "rdseed", true); 3093 setFeatureEnabledImpl(Features, "adx", true); 3094 LLVM_FALLTHROUGH; 3095 case CK_Haswell: 3096 setFeatureEnabledImpl(Features, "avx2", true); 3097 setFeatureEnabledImpl(Features, "lzcnt", true); 3098 setFeatureEnabledImpl(Features, "bmi", true); 3099 setFeatureEnabledImpl(Features, "bmi2", true); 3100 setFeatureEnabledImpl(Features, "rtm", true); 3101 setFeatureEnabledImpl(Features, "fma", true); 3102 setFeatureEnabledImpl(Features, "movbe", true); 3103 LLVM_FALLTHROUGH; 3104 case CK_IvyBridge: 3105 setFeatureEnabledImpl(Features, "rdrnd", true); 3106 setFeatureEnabledImpl(Features, "f16c", true); 3107 setFeatureEnabledImpl(Features, "fsgsbase", true); 3108 LLVM_FALLTHROUGH; 3109 case CK_SandyBridge: 3110 setFeatureEnabledImpl(Features, "avx", true); 3111 setFeatureEnabledImpl(Features, "xsave", true); 3112 setFeatureEnabledImpl(Features, "xsaveopt", true); 3113 LLVM_FALLTHROUGH; 3114 case CK_Westmere: 3115 case CK_Silvermont: 3116 setFeatureEnabledImpl(Features, "aes", true); 3117 setFeatureEnabledImpl(Features, "pclmul", true); 3118 LLVM_FALLTHROUGH; 3119 case CK_Nehalem: 3120 setFeatureEnabledImpl(Features, "sse4.2", true); 3121 setFeatureEnabledImpl(Features, "fxsr", true); 3122 setFeatureEnabledImpl(Features, "cx16", true); 3123 break; 3124 case CK_KNL: 3125 setFeatureEnabledImpl(Features, "avx512f", true); 3126 setFeatureEnabledImpl(Features, "avx512cd", true); 3127 setFeatureEnabledImpl(Features, "avx512er", true); 3128 setFeatureEnabledImpl(Features, "avx512pf", true); 3129 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3130 setFeatureEnabledImpl(Features, "fxsr", true); 3131 setFeatureEnabledImpl(Features, "rdseed", true); 3132 setFeatureEnabledImpl(Features, "adx", true); 3133 setFeatureEnabledImpl(Features, "lzcnt", true); 3134 setFeatureEnabledImpl(Features, "bmi", true); 3135 setFeatureEnabledImpl(Features, "bmi2", true); 3136 setFeatureEnabledImpl(Features, "rtm", true); 3137 setFeatureEnabledImpl(Features, "fma", true); 3138 setFeatureEnabledImpl(Features, "rdrnd", true); 3139 setFeatureEnabledImpl(Features, "f16c", true); 3140 setFeatureEnabledImpl(Features, "fsgsbase", true); 3141 setFeatureEnabledImpl(Features, "aes", true); 3142 setFeatureEnabledImpl(Features, "pclmul", true); 3143 setFeatureEnabledImpl(Features, "cx16", true); 3144 setFeatureEnabledImpl(Features, "xsaveopt", true); 3145 setFeatureEnabledImpl(Features, "xsave", true); 3146 setFeatureEnabledImpl(Features, "movbe", true); 3147 break; 3148 case CK_K6_2: 3149 case CK_K6_3: 3150 case CK_WinChip2: 3151 case CK_C3: 3152 setFeatureEnabledImpl(Features, "3dnow", true); 3153 break; 3154 case CK_Athlon: 3155 case CK_AthlonThunderbird: 3156 case CK_Geode: 3157 setFeatureEnabledImpl(Features, "3dnowa", true); 3158 break; 3159 case CK_Athlon4: 3160 case CK_AthlonXP: 3161 case CK_AthlonMP: 3162 setFeatureEnabledImpl(Features, "sse", true); 3163 setFeatureEnabledImpl(Features, "3dnowa", true); 3164 setFeatureEnabledImpl(Features, "fxsr", true); 3165 break; 3166 case CK_K8: 3167 case CK_Opteron: 3168 case CK_Athlon64: 3169 case CK_AthlonFX: 3170 setFeatureEnabledImpl(Features, "sse2", true); 3171 setFeatureEnabledImpl(Features, "3dnowa", true); 3172 setFeatureEnabledImpl(Features, "fxsr", true); 3173 break; 3174 case CK_AMDFAM10: 3175 setFeatureEnabledImpl(Features, "sse4a", true); 3176 setFeatureEnabledImpl(Features, "lzcnt", true); 3177 setFeatureEnabledImpl(Features, "popcnt", true); 3178 LLVM_FALLTHROUGH; 3179 case CK_K8SSE3: 3180 case CK_OpteronSSE3: 3181 case CK_Athlon64SSE3: 3182 setFeatureEnabledImpl(Features, "sse3", true); 3183 setFeatureEnabledImpl(Features, "3dnowa", true); 3184 setFeatureEnabledImpl(Features, "fxsr", true); 3185 break; 3186 case CK_BTVER2: 3187 setFeatureEnabledImpl(Features, "avx", true); 3188 setFeatureEnabledImpl(Features, "aes", true); 3189 setFeatureEnabledImpl(Features, "pclmul", true); 3190 setFeatureEnabledImpl(Features, "bmi", true); 3191 setFeatureEnabledImpl(Features, "f16c", true); 3192 setFeatureEnabledImpl(Features, "xsaveopt", true); 3193 LLVM_FALLTHROUGH; 3194 case CK_BTVER1: 3195 setFeatureEnabledImpl(Features, "ssse3", true); 3196 setFeatureEnabledImpl(Features, "sse4a", true); 3197 setFeatureEnabledImpl(Features, "lzcnt", true); 3198 setFeatureEnabledImpl(Features, "popcnt", true); 3199 setFeatureEnabledImpl(Features, "prfchw", true); 3200 setFeatureEnabledImpl(Features, "cx16", true); 3201 setFeatureEnabledImpl(Features, "fxsr", true); 3202 break; 3203 case CK_ZNVER1: 3204 setFeatureEnabledImpl(Features, "adx", true); 3205 setFeatureEnabledImpl(Features, "aes", true); 3206 setFeatureEnabledImpl(Features, "avx2", true); 3207 setFeatureEnabledImpl(Features, "bmi", true); 3208 setFeatureEnabledImpl(Features, "bmi2", true); 3209 setFeatureEnabledImpl(Features, "clflushopt", true); 3210 setFeatureEnabledImpl(Features, "clzero", true); 3211 setFeatureEnabledImpl(Features, "cx16", true); 3212 setFeatureEnabledImpl(Features, "f16c", true); 3213 setFeatureEnabledImpl(Features, "fma", true); 3214 setFeatureEnabledImpl(Features, "fsgsbase", true); 3215 setFeatureEnabledImpl(Features, "fxsr", true); 3216 setFeatureEnabledImpl(Features, "lzcnt", true); 3217 setFeatureEnabledImpl(Features, "mwaitx", true); 3218 setFeatureEnabledImpl(Features, "movbe", true); 3219 setFeatureEnabledImpl(Features, "pclmul", true); 3220 setFeatureEnabledImpl(Features, "popcnt", true); 3221 setFeatureEnabledImpl(Features, "prfchw", true); 3222 setFeatureEnabledImpl(Features, "rdrnd", true); 3223 setFeatureEnabledImpl(Features, "rdseed", true); 3224 setFeatureEnabledImpl(Features, "sha", true); 3225 setFeatureEnabledImpl(Features, "sse4a", true); 3226 setFeatureEnabledImpl(Features, "xsave", true); 3227 setFeatureEnabledImpl(Features, "xsavec", true); 3228 setFeatureEnabledImpl(Features, "xsaveopt", true); 3229 setFeatureEnabledImpl(Features, "xsaves", true); 3230 break; 3231 case CK_BDVER4: 3232 setFeatureEnabledImpl(Features, "avx2", true); 3233 setFeatureEnabledImpl(Features, "bmi2", true); 3234 setFeatureEnabledImpl(Features, "mwaitx", true); 3235 LLVM_FALLTHROUGH; 3236 case CK_BDVER3: 3237 setFeatureEnabledImpl(Features, "fsgsbase", true); 3238 setFeatureEnabledImpl(Features, "xsaveopt", true); 3239 LLVM_FALLTHROUGH; 3240 case CK_BDVER2: 3241 setFeatureEnabledImpl(Features, "bmi", true); 3242 setFeatureEnabledImpl(Features, "fma", true); 3243 setFeatureEnabledImpl(Features, "f16c", true); 3244 setFeatureEnabledImpl(Features, "tbm", true); 3245 LLVM_FALLTHROUGH; 3246 case CK_BDVER1: 3247 // xop implies avx, sse4a and fma4. 3248 setFeatureEnabledImpl(Features, "xop", true); 3249 setFeatureEnabledImpl(Features, "lzcnt", true); 3250 setFeatureEnabledImpl(Features, "aes", true); 3251 setFeatureEnabledImpl(Features, "pclmul", true); 3252 setFeatureEnabledImpl(Features, "prfchw", true); 3253 setFeatureEnabledImpl(Features, "cx16", true); 3254 setFeatureEnabledImpl(Features, "fxsr", true); 3255 setFeatureEnabledImpl(Features, "xsave", true); 3256 break; 3257 } 3258 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3259 return false; 3260 3261 // Can't do this earlier because we need to be able to explicitly enable 3262 // or disable these features and the things that they depend upon. 3263 3264 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3265 auto I = Features.find("sse4.2"); 3266 if (I != Features.end() && I->getValue() && 3267 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3268 FeaturesVec.end()) 3269 Features["popcnt"] = true; 3270 3271 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3272 I = Features.find("3dnow"); 3273 if (I != Features.end() && I->getValue() && 3274 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3275 FeaturesVec.end()) 3276 Features["prfchw"] = true; 3277 3278 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3279 // then enable MMX. 3280 I = Features.find("sse"); 3281 if (I != Features.end() && I->getValue() && 3282 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3283 FeaturesVec.end()) 3284 Features["mmx"] = true; 3285 3286 return true; 3287 } 3288 3289 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3290 X86SSEEnum Level, bool Enabled) { 3291 if (Enabled) { 3292 switch (Level) { 3293 case AVX512F: 3294 Features["avx512f"] = true; 3295 case AVX2: 3296 Features["avx2"] = true; 3297 case AVX: 3298 Features["avx"] = true; 3299 Features["xsave"] = true; 3300 case SSE42: 3301 Features["sse4.2"] = true; 3302 case SSE41: 3303 Features["sse4.1"] = true; 3304 case SSSE3: 3305 Features["ssse3"] = true; 3306 case SSE3: 3307 Features["sse3"] = true; 3308 case SSE2: 3309 Features["sse2"] = true; 3310 case SSE1: 3311 Features["sse"] = true; 3312 case NoSSE: 3313 break; 3314 } 3315 return; 3316 } 3317 3318 switch (Level) { 3319 case NoSSE: 3320 case SSE1: 3321 Features["sse"] = false; 3322 case SSE2: 3323 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3324 Features["sha"] = false; 3325 case SSE3: 3326 Features["sse3"] = false; 3327 setXOPLevel(Features, NoXOP, false); 3328 case SSSE3: 3329 Features["ssse3"] = false; 3330 case SSE41: 3331 Features["sse4.1"] = false; 3332 case SSE42: 3333 Features["sse4.2"] = false; 3334 case AVX: 3335 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3336 Features["xsaveopt"] = false; 3337 setXOPLevel(Features, FMA4, false); 3338 case AVX2: 3339 Features["avx2"] = false; 3340 case AVX512F: 3341 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3342 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3343 Features["avx512vl"] = Features["avx512vbmi"] = 3344 Features["avx512ifma"] = false; 3345 } 3346 } 3347 3348 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3349 MMX3DNowEnum Level, bool Enabled) { 3350 if (Enabled) { 3351 switch (Level) { 3352 case AMD3DNowAthlon: 3353 Features["3dnowa"] = true; 3354 case AMD3DNow: 3355 Features["3dnow"] = true; 3356 case MMX: 3357 Features["mmx"] = true; 3358 case NoMMX3DNow: 3359 break; 3360 } 3361 return; 3362 } 3363 3364 switch (Level) { 3365 case NoMMX3DNow: 3366 case MMX: 3367 Features["mmx"] = false; 3368 case AMD3DNow: 3369 Features["3dnow"] = false; 3370 case AMD3DNowAthlon: 3371 Features["3dnowa"] = false; 3372 } 3373 } 3374 3375 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3376 bool Enabled) { 3377 if (Enabled) { 3378 switch (Level) { 3379 case XOP: 3380 Features["xop"] = true; 3381 case FMA4: 3382 Features["fma4"] = true; 3383 setSSELevel(Features, AVX, true); 3384 case SSE4A: 3385 Features["sse4a"] = true; 3386 setSSELevel(Features, SSE3, true); 3387 case NoXOP: 3388 break; 3389 } 3390 return; 3391 } 3392 3393 switch (Level) { 3394 case NoXOP: 3395 case SSE4A: 3396 Features["sse4a"] = false; 3397 case FMA4: 3398 Features["fma4"] = false; 3399 case XOP: 3400 Features["xop"] = false; 3401 } 3402 } 3403 3404 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3405 StringRef Name, bool Enabled) { 3406 // This is a bit of a hack to deal with the sse4 target feature when used 3407 // as part of the target attribute. We handle sse4 correctly everywhere 3408 // else. See below for more information on how we handle the sse4 options. 3409 if (Name != "sse4") 3410 Features[Name] = Enabled; 3411 3412 if (Name == "mmx") { 3413 setMMXLevel(Features, MMX, Enabled); 3414 } else if (Name == "sse") { 3415 setSSELevel(Features, SSE1, Enabled); 3416 } else if (Name == "sse2") { 3417 setSSELevel(Features, SSE2, Enabled); 3418 } else if (Name == "sse3") { 3419 setSSELevel(Features, SSE3, Enabled); 3420 } else if (Name == "ssse3") { 3421 setSSELevel(Features, SSSE3, Enabled); 3422 } else if (Name == "sse4.2") { 3423 setSSELevel(Features, SSE42, Enabled); 3424 } else if (Name == "sse4.1") { 3425 setSSELevel(Features, SSE41, Enabled); 3426 } else if (Name == "3dnow") { 3427 setMMXLevel(Features, AMD3DNow, Enabled); 3428 } else if (Name == "3dnowa") { 3429 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3430 } else if (Name == "aes") { 3431 if (Enabled) 3432 setSSELevel(Features, SSE2, Enabled); 3433 } else if (Name == "pclmul") { 3434 if (Enabled) 3435 setSSELevel(Features, SSE2, Enabled); 3436 } else if (Name == "avx") { 3437 setSSELevel(Features, AVX, Enabled); 3438 } else if (Name == "avx2") { 3439 setSSELevel(Features, AVX2, Enabled); 3440 } else if (Name == "avx512f") { 3441 setSSELevel(Features, AVX512F, Enabled); 3442 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3443 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3444 Name == "avx512vbmi" || Name == "avx512ifma") { 3445 if (Enabled) 3446 setSSELevel(Features, AVX512F, Enabled); 3447 // Enable BWI instruction if VBMI is being enabled. 3448 if (Name == "avx512vbmi" && Enabled) 3449 Features["avx512bw"] = true; 3450 // Also disable VBMI if BWI is being disabled. 3451 if (Name == "avx512bw" && !Enabled) 3452 Features["avx512vbmi"] = false; 3453 } else if (Name == "fma") { 3454 if (Enabled) 3455 setSSELevel(Features, AVX, Enabled); 3456 } else if (Name == "fma4") { 3457 setXOPLevel(Features, FMA4, Enabled); 3458 } else if (Name == "xop") { 3459 setXOPLevel(Features, XOP, Enabled); 3460 } else if (Name == "sse4a") { 3461 setXOPLevel(Features, SSE4A, Enabled); 3462 } else if (Name == "f16c") { 3463 if (Enabled) 3464 setSSELevel(Features, AVX, Enabled); 3465 } else if (Name == "sha") { 3466 if (Enabled) 3467 setSSELevel(Features, SSE2, Enabled); 3468 } else if (Name == "sse4") { 3469 // We can get here via the __target__ attribute since that's not controlled 3470 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3471 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3472 // disabled. 3473 if (Enabled) 3474 setSSELevel(Features, SSE42, Enabled); 3475 else 3476 setSSELevel(Features, SSE41, Enabled); 3477 } else if (Name == "xsave") { 3478 if (!Enabled) 3479 Features["xsaveopt"] = false; 3480 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3481 if (Enabled) 3482 Features["xsave"] = true; 3483 } 3484 } 3485 3486 /// handleTargetFeatures - Perform initialization based on the user 3487 /// configured set of features. 3488 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3489 DiagnosticsEngine &Diags) { 3490 for (const auto &Feature : Features) { 3491 if (Feature[0] != '+') 3492 continue; 3493 3494 if (Feature == "+aes") { 3495 HasAES = true; 3496 } else if (Feature == "+pclmul") { 3497 HasPCLMUL = true; 3498 } else if (Feature == "+lzcnt") { 3499 HasLZCNT = true; 3500 } else if (Feature == "+rdrnd") { 3501 HasRDRND = true; 3502 } else if (Feature == "+fsgsbase") { 3503 HasFSGSBASE = true; 3504 } else if (Feature == "+bmi") { 3505 HasBMI = true; 3506 } else if (Feature == "+bmi2") { 3507 HasBMI2 = true; 3508 } else if (Feature == "+popcnt") { 3509 HasPOPCNT = true; 3510 } else if (Feature == "+rtm") { 3511 HasRTM = true; 3512 } else if (Feature == "+prfchw") { 3513 HasPRFCHW = true; 3514 } else if (Feature == "+rdseed") { 3515 HasRDSEED = true; 3516 } else if (Feature == "+adx") { 3517 HasADX = true; 3518 } else if (Feature == "+tbm") { 3519 HasTBM = true; 3520 } else if (Feature == "+fma") { 3521 HasFMA = true; 3522 } else if (Feature == "+f16c") { 3523 HasF16C = true; 3524 } else if (Feature == "+avx512cd") { 3525 HasAVX512CD = true; 3526 } else if (Feature == "+avx512er") { 3527 HasAVX512ER = true; 3528 } else if (Feature == "+avx512pf") { 3529 HasAVX512PF = true; 3530 } else if (Feature == "+avx512dq") { 3531 HasAVX512DQ = true; 3532 } else if (Feature == "+avx512bw") { 3533 HasAVX512BW = true; 3534 } else if (Feature == "+avx512vl") { 3535 HasAVX512VL = true; 3536 } else if (Feature == "+avx512vbmi") { 3537 HasAVX512VBMI = true; 3538 } else if (Feature == "+avx512ifma") { 3539 HasAVX512IFMA = true; 3540 } else if (Feature == "+sha") { 3541 HasSHA = true; 3542 } else if (Feature == "+mpx") { 3543 HasMPX = true; 3544 } else if (Feature == "+movbe") { 3545 HasMOVBE = true; 3546 } else if (Feature == "+sgx") { 3547 HasSGX = true; 3548 } else if (Feature == "+cx16") { 3549 HasCX16 = true; 3550 } else if (Feature == "+fxsr") { 3551 HasFXSR = true; 3552 } else if (Feature == "+xsave") { 3553 HasXSAVE = true; 3554 } else if (Feature == "+xsaveopt") { 3555 HasXSAVEOPT = true; 3556 } else if (Feature == "+xsavec") { 3557 HasXSAVEC = true; 3558 } else if (Feature == "+xsaves") { 3559 HasXSAVES = true; 3560 } else if (Feature == "+mwaitx") { 3561 HasMWAITX = true; 3562 } else if (Feature == "+pku") { 3563 HasPKU = true; 3564 } else if (Feature == "+clflushopt") { 3565 HasCLFLUSHOPT = true; 3566 } else if (Feature == "+clwb") { 3567 HasCLWB = true; 3568 } else if (Feature == "+prefetchwt1") { 3569 HasPREFETCHWT1 = true; 3570 } else if (Feature == "+clzero") { 3571 HasCLZERO = true; 3572 } 3573 3574 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3575 .Case("+avx512f", AVX512F) 3576 .Case("+avx2", AVX2) 3577 .Case("+avx", AVX) 3578 .Case("+sse4.2", SSE42) 3579 .Case("+sse4.1", SSE41) 3580 .Case("+ssse3", SSSE3) 3581 .Case("+sse3", SSE3) 3582 .Case("+sse2", SSE2) 3583 .Case("+sse", SSE1) 3584 .Default(NoSSE); 3585 SSELevel = std::max(SSELevel, Level); 3586 3587 MMX3DNowEnum ThreeDNowLevel = 3588 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3589 .Case("+3dnowa", AMD3DNowAthlon) 3590 .Case("+3dnow", AMD3DNow) 3591 .Case("+mmx", MMX) 3592 .Default(NoMMX3DNow); 3593 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3594 3595 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3596 .Case("+xop", XOP) 3597 .Case("+fma4", FMA4) 3598 .Case("+sse4a", SSE4A) 3599 .Default(NoXOP); 3600 XOPLevel = std::max(XOPLevel, XLevel); 3601 } 3602 3603 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3604 // matches the selected sse level. 3605 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3606 (FPMath == FP_387 && SSELevel >= SSE1)) { 3607 Diags.Report(diag::err_target_unsupported_fpmath) << 3608 (FPMath == FP_SSE ? "sse" : "387"); 3609 return false; 3610 } 3611 3612 SimdDefaultAlign = 3613 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3614 return true; 3615 } 3616 3617 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3618 /// definitions for this particular subtarget. 3619 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3620 MacroBuilder &Builder) const { 3621 // Target identification. 3622 if (getTriple().getArch() == llvm::Triple::x86_64) { 3623 Builder.defineMacro("__amd64__"); 3624 Builder.defineMacro("__amd64"); 3625 Builder.defineMacro("__x86_64"); 3626 Builder.defineMacro("__x86_64__"); 3627 if (getTriple().getArchName() == "x86_64h") { 3628 Builder.defineMacro("__x86_64h"); 3629 Builder.defineMacro("__x86_64h__"); 3630 } 3631 } else { 3632 DefineStd(Builder, "i386", Opts); 3633 } 3634 3635 // Subtarget options. 3636 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3637 // truly should be based on -mtune options. 3638 switch (CPU) { 3639 case CK_Generic: 3640 break; 3641 case CK_i386: 3642 // The rest are coming from the i386 define above. 3643 Builder.defineMacro("__tune_i386__"); 3644 break; 3645 case CK_i486: 3646 case CK_WinChipC6: 3647 case CK_WinChip2: 3648 case CK_C3: 3649 defineCPUMacros(Builder, "i486"); 3650 break; 3651 case CK_PentiumMMX: 3652 Builder.defineMacro("__pentium_mmx__"); 3653 Builder.defineMacro("__tune_pentium_mmx__"); 3654 // Fallthrough 3655 case CK_i586: 3656 case CK_Pentium: 3657 defineCPUMacros(Builder, "i586"); 3658 defineCPUMacros(Builder, "pentium"); 3659 break; 3660 case CK_Pentium3: 3661 case CK_Pentium3M: 3662 case CK_PentiumM: 3663 Builder.defineMacro("__tune_pentium3__"); 3664 // Fallthrough 3665 case CK_Pentium2: 3666 case CK_C3_2: 3667 Builder.defineMacro("__tune_pentium2__"); 3668 // Fallthrough 3669 case CK_PentiumPro: 3670 Builder.defineMacro("__tune_i686__"); 3671 Builder.defineMacro("__tune_pentiumpro__"); 3672 // Fallthrough 3673 case CK_i686: 3674 Builder.defineMacro("__i686"); 3675 Builder.defineMacro("__i686__"); 3676 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3677 Builder.defineMacro("__pentiumpro"); 3678 Builder.defineMacro("__pentiumpro__"); 3679 break; 3680 case CK_Pentium4: 3681 case CK_Pentium4M: 3682 defineCPUMacros(Builder, "pentium4"); 3683 break; 3684 case CK_Yonah: 3685 case CK_Prescott: 3686 case CK_Nocona: 3687 defineCPUMacros(Builder, "nocona"); 3688 break; 3689 case CK_Core2: 3690 case CK_Penryn: 3691 defineCPUMacros(Builder, "core2"); 3692 break; 3693 case CK_Bonnell: 3694 defineCPUMacros(Builder, "atom"); 3695 break; 3696 case CK_Silvermont: 3697 defineCPUMacros(Builder, "slm"); 3698 break; 3699 case CK_Nehalem: 3700 case CK_Westmere: 3701 case CK_SandyBridge: 3702 case CK_IvyBridge: 3703 case CK_Haswell: 3704 case CK_Broadwell: 3705 case CK_SkylakeClient: 3706 // FIXME: Historically, we defined this legacy name, it would be nice to 3707 // remove it at some point. We've never exposed fine-grained names for 3708 // recent primary x86 CPUs, and we should keep it that way. 3709 defineCPUMacros(Builder, "corei7"); 3710 break; 3711 case CK_SkylakeServer: 3712 defineCPUMacros(Builder, "skx"); 3713 break; 3714 case CK_Cannonlake: 3715 break; 3716 case CK_KNL: 3717 defineCPUMacros(Builder, "knl"); 3718 break; 3719 case CK_Lakemont: 3720 Builder.defineMacro("__tune_lakemont__"); 3721 break; 3722 case CK_K6_2: 3723 Builder.defineMacro("__k6_2__"); 3724 Builder.defineMacro("__tune_k6_2__"); 3725 // Fallthrough 3726 case CK_K6_3: 3727 if (CPU != CK_K6_2) { // In case of fallthrough 3728 // FIXME: GCC may be enabling these in cases where some other k6 3729 // architecture is specified but -m3dnow is explicitly provided. The 3730 // exact semantics need to be determined and emulated here. 3731 Builder.defineMacro("__k6_3__"); 3732 Builder.defineMacro("__tune_k6_3__"); 3733 } 3734 // Fallthrough 3735 case CK_K6: 3736 defineCPUMacros(Builder, "k6"); 3737 break; 3738 case CK_Athlon: 3739 case CK_AthlonThunderbird: 3740 case CK_Athlon4: 3741 case CK_AthlonXP: 3742 case CK_AthlonMP: 3743 defineCPUMacros(Builder, "athlon"); 3744 if (SSELevel != NoSSE) { 3745 Builder.defineMacro("__athlon_sse__"); 3746 Builder.defineMacro("__tune_athlon_sse__"); 3747 } 3748 break; 3749 case CK_K8: 3750 case CK_K8SSE3: 3751 case CK_x86_64: 3752 case CK_Opteron: 3753 case CK_OpteronSSE3: 3754 case CK_Athlon64: 3755 case CK_Athlon64SSE3: 3756 case CK_AthlonFX: 3757 defineCPUMacros(Builder, "k8"); 3758 break; 3759 case CK_AMDFAM10: 3760 defineCPUMacros(Builder, "amdfam10"); 3761 break; 3762 case CK_BTVER1: 3763 defineCPUMacros(Builder, "btver1"); 3764 break; 3765 case CK_BTVER2: 3766 defineCPUMacros(Builder, "btver2"); 3767 break; 3768 case CK_BDVER1: 3769 defineCPUMacros(Builder, "bdver1"); 3770 break; 3771 case CK_BDVER2: 3772 defineCPUMacros(Builder, "bdver2"); 3773 break; 3774 case CK_BDVER3: 3775 defineCPUMacros(Builder, "bdver3"); 3776 break; 3777 case CK_BDVER4: 3778 defineCPUMacros(Builder, "bdver4"); 3779 break; 3780 case CK_ZNVER1: 3781 defineCPUMacros(Builder, "znver1"); 3782 break; 3783 case CK_Geode: 3784 defineCPUMacros(Builder, "geode"); 3785 break; 3786 } 3787 3788 // Target properties. 3789 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3790 3791 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3792 // functions in glibc header files that use FP Stack inline asm which the 3793 // backend can't deal with (PR879). 3794 Builder.defineMacro("__NO_MATH_INLINES"); 3795 3796 if (HasAES) 3797 Builder.defineMacro("__AES__"); 3798 3799 if (HasPCLMUL) 3800 Builder.defineMacro("__PCLMUL__"); 3801 3802 if (HasLZCNT) 3803 Builder.defineMacro("__LZCNT__"); 3804 3805 if (HasRDRND) 3806 Builder.defineMacro("__RDRND__"); 3807 3808 if (HasFSGSBASE) 3809 Builder.defineMacro("__FSGSBASE__"); 3810 3811 if (HasBMI) 3812 Builder.defineMacro("__BMI__"); 3813 3814 if (HasBMI2) 3815 Builder.defineMacro("__BMI2__"); 3816 3817 if (HasPOPCNT) 3818 Builder.defineMacro("__POPCNT__"); 3819 3820 if (HasRTM) 3821 Builder.defineMacro("__RTM__"); 3822 3823 if (HasPRFCHW) 3824 Builder.defineMacro("__PRFCHW__"); 3825 3826 if (HasRDSEED) 3827 Builder.defineMacro("__RDSEED__"); 3828 3829 if (HasADX) 3830 Builder.defineMacro("__ADX__"); 3831 3832 if (HasTBM) 3833 Builder.defineMacro("__TBM__"); 3834 3835 if (HasMWAITX) 3836 Builder.defineMacro("__MWAITX__"); 3837 3838 switch (XOPLevel) { 3839 case XOP: 3840 Builder.defineMacro("__XOP__"); 3841 case FMA4: 3842 Builder.defineMacro("__FMA4__"); 3843 case SSE4A: 3844 Builder.defineMacro("__SSE4A__"); 3845 case NoXOP: 3846 break; 3847 } 3848 3849 if (HasFMA) 3850 Builder.defineMacro("__FMA__"); 3851 3852 if (HasF16C) 3853 Builder.defineMacro("__F16C__"); 3854 3855 if (HasAVX512CD) 3856 Builder.defineMacro("__AVX512CD__"); 3857 if (HasAVX512ER) 3858 Builder.defineMacro("__AVX512ER__"); 3859 if (HasAVX512PF) 3860 Builder.defineMacro("__AVX512PF__"); 3861 if (HasAVX512DQ) 3862 Builder.defineMacro("__AVX512DQ__"); 3863 if (HasAVX512BW) 3864 Builder.defineMacro("__AVX512BW__"); 3865 if (HasAVX512VL) 3866 Builder.defineMacro("__AVX512VL__"); 3867 if (HasAVX512VBMI) 3868 Builder.defineMacro("__AVX512VBMI__"); 3869 if (HasAVX512IFMA) 3870 Builder.defineMacro("__AVX512IFMA__"); 3871 3872 if (HasSHA) 3873 Builder.defineMacro("__SHA__"); 3874 3875 if (HasFXSR) 3876 Builder.defineMacro("__FXSR__"); 3877 if (HasXSAVE) 3878 Builder.defineMacro("__XSAVE__"); 3879 if (HasXSAVEOPT) 3880 Builder.defineMacro("__XSAVEOPT__"); 3881 if (HasXSAVEC) 3882 Builder.defineMacro("__XSAVEC__"); 3883 if (HasXSAVES) 3884 Builder.defineMacro("__XSAVES__"); 3885 if (HasPKU) 3886 Builder.defineMacro("__PKU__"); 3887 if (HasCX16) 3888 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3889 if (HasCLFLUSHOPT) 3890 Builder.defineMacro("__CLFLUSHOPT__"); 3891 if (HasCLWB) 3892 Builder.defineMacro("__CLWB__"); 3893 if (HasMPX) 3894 Builder.defineMacro("__MPX__"); 3895 if (HasSGX) 3896 Builder.defineMacro("__SGX__"); 3897 if (HasPREFETCHWT1) 3898 Builder.defineMacro("__PREFETCHWT1__"); 3899 if (HasCLZERO) 3900 Builder.defineMacro("__CLZERO__"); 3901 3902 // Each case falls through to the previous one here. 3903 switch (SSELevel) { 3904 case AVX512F: 3905 Builder.defineMacro("__AVX512F__"); 3906 case AVX2: 3907 Builder.defineMacro("__AVX2__"); 3908 case AVX: 3909 Builder.defineMacro("__AVX__"); 3910 case SSE42: 3911 Builder.defineMacro("__SSE4_2__"); 3912 case SSE41: 3913 Builder.defineMacro("__SSE4_1__"); 3914 case SSSE3: 3915 Builder.defineMacro("__SSSE3__"); 3916 case SSE3: 3917 Builder.defineMacro("__SSE3__"); 3918 case SSE2: 3919 Builder.defineMacro("__SSE2__"); 3920 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3921 case SSE1: 3922 Builder.defineMacro("__SSE__"); 3923 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3924 case NoSSE: 3925 break; 3926 } 3927 3928 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3929 switch (SSELevel) { 3930 case AVX512F: 3931 case AVX2: 3932 case AVX: 3933 case SSE42: 3934 case SSE41: 3935 case SSSE3: 3936 case SSE3: 3937 case SSE2: 3938 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3939 break; 3940 case SSE1: 3941 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3942 break; 3943 default: 3944 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3945 } 3946 } 3947 3948 // Each case falls through to the previous one here. 3949 switch (MMX3DNowLevel) { 3950 case AMD3DNowAthlon: 3951 Builder.defineMacro("__3dNOW_A__"); 3952 case AMD3DNow: 3953 Builder.defineMacro("__3dNOW__"); 3954 case MMX: 3955 Builder.defineMacro("__MMX__"); 3956 case NoMMX3DNow: 3957 break; 3958 } 3959 3960 if (CPU >= CK_i486) { 3961 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3962 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3963 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3964 } 3965 if (CPU >= CK_i586) 3966 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3967 } 3968 3969 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3970 return llvm::StringSwitch<bool>(Feature) 3971 .Case("aes", HasAES) 3972 .Case("avx", SSELevel >= AVX) 3973 .Case("avx2", SSELevel >= AVX2) 3974 .Case("avx512f", SSELevel >= AVX512F) 3975 .Case("avx512cd", HasAVX512CD) 3976 .Case("avx512er", HasAVX512ER) 3977 .Case("avx512pf", HasAVX512PF) 3978 .Case("avx512dq", HasAVX512DQ) 3979 .Case("avx512bw", HasAVX512BW) 3980 .Case("avx512vl", HasAVX512VL) 3981 .Case("avx512vbmi", HasAVX512VBMI) 3982 .Case("avx512ifma", HasAVX512IFMA) 3983 .Case("bmi", HasBMI) 3984 .Case("bmi2", HasBMI2) 3985 .Case("clflushopt", HasCLFLUSHOPT) 3986 .Case("clwb", HasCLWB) 3987 .Case("clzero", HasCLZERO) 3988 .Case("cx16", HasCX16) 3989 .Case("f16c", HasF16C) 3990 .Case("fma", HasFMA) 3991 .Case("fma4", XOPLevel >= FMA4) 3992 .Case("fsgsbase", HasFSGSBASE) 3993 .Case("fxsr", HasFXSR) 3994 .Case("lzcnt", HasLZCNT) 3995 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3996 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3997 .Case("mmx", MMX3DNowLevel >= MMX) 3998 .Case("movbe", HasMOVBE) 3999 .Case("mpx", HasMPX) 4000 .Case("pclmul", HasPCLMUL) 4001 .Case("pku", HasPKU) 4002 .Case("popcnt", HasPOPCNT) 4003 .Case("prefetchwt1", HasPREFETCHWT1) 4004 .Case("prfchw", HasPRFCHW) 4005 .Case("rdrnd", HasRDRND) 4006 .Case("rdseed", HasRDSEED) 4007 .Case("rtm", HasRTM) 4008 .Case("sgx", HasSGX) 4009 .Case("sha", HasSHA) 4010 .Case("sse", SSELevel >= SSE1) 4011 .Case("sse2", SSELevel >= SSE2) 4012 .Case("sse3", SSELevel >= SSE3) 4013 .Case("ssse3", SSELevel >= SSSE3) 4014 .Case("sse4.1", SSELevel >= SSE41) 4015 .Case("sse4.2", SSELevel >= SSE42) 4016 .Case("sse4a", XOPLevel >= SSE4A) 4017 .Case("tbm", HasTBM) 4018 .Case("x86", true) 4019 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4020 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4021 .Case("xop", XOPLevel >= XOP) 4022 .Case("xsave", HasXSAVE) 4023 .Case("xsavec", HasXSAVEC) 4024 .Case("xsaves", HasXSAVES) 4025 .Case("xsaveopt", HasXSAVEOPT) 4026 .Default(false); 4027 } 4028 4029 // We can't use a generic validation scheme for the features accepted here 4030 // versus subtarget features accepted in the target attribute because the 4031 // bitfield structure that's initialized in the runtime only supports the 4032 // below currently rather than the full range of subtarget features. (See 4033 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4034 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4035 return llvm::StringSwitch<bool>(FeatureStr) 4036 .Case("cmov", true) 4037 .Case("mmx", true) 4038 .Case("popcnt", true) 4039 .Case("sse", true) 4040 .Case("sse2", true) 4041 .Case("sse3", true) 4042 .Case("ssse3", true) 4043 .Case("sse4.1", true) 4044 .Case("sse4.2", true) 4045 .Case("avx", true) 4046 .Case("avx2", true) 4047 .Case("sse4a", true) 4048 .Case("fma4", true) 4049 .Case("xop", true) 4050 .Case("fma", true) 4051 .Case("avx512f", true) 4052 .Case("bmi", true) 4053 .Case("bmi2", true) 4054 .Case("aes", true) 4055 .Case("pclmul", true) 4056 .Case("avx512vl", true) 4057 .Case("avx512bw", true) 4058 .Case("avx512dq", true) 4059 .Case("avx512cd", true) 4060 .Case("avx512er", true) 4061 .Case("avx512pf", true) 4062 .Case("avx512vbmi", true) 4063 .Case("avx512ifma", true) 4064 .Default(false); 4065 } 4066 4067 bool 4068 X86TargetInfo::validateAsmConstraint(const char *&Name, 4069 TargetInfo::ConstraintInfo &Info) const { 4070 switch (*Name) { 4071 default: return false; 4072 // Constant constraints. 4073 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4074 // instructions. 4075 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4076 // x86_64 instructions. 4077 case 's': 4078 Info.setRequiresImmediate(); 4079 return true; 4080 case 'I': 4081 Info.setRequiresImmediate(0, 31); 4082 return true; 4083 case 'J': 4084 Info.setRequiresImmediate(0, 63); 4085 return true; 4086 case 'K': 4087 Info.setRequiresImmediate(-128, 127); 4088 return true; 4089 case 'L': 4090 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4091 return true; 4092 case 'M': 4093 Info.setRequiresImmediate(0, 3); 4094 return true; 4095 case 'N': 4096 Info.setRequiresImmediate(0, 255); 4097 return true; 4098 case 'O': 4099 Info.setRequiresImmediate(0, 127); 4100 return true; 4101 // Register constraints. 4102 case 'Y': // 'Y' is the first character for several 2-character constraints. 4103 // Shift the pointer to the second character of the constraint. 4104 Name++; 4105 switch (*Name) { 4106 default: 4107 return false; 4108 case '0': // First SSE register. 4109 case 't': // Any SSE register, when SSE2 is enabled. 4110 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4111 case 'm': // Any MMX register, when inter-unit moves enabled. 4112 case 'k': // AVX512 arch mask registers: k1-k7. 4113 Info.setAllowsRegister(); 4114 return true; 4115 } 4116 case 'f': // Any x87 floating point stack register. 4117 // Constraint 'f' cannot be used for output operands. 4118 if (Info.ConstraintStr[0] == '=') 4119 return false; 4120 Info.setAllowsRegister(); 4121 return true; 4122 case 'a': // eax. 4123 case 'b': // ebx. 4124 case 'c': // ecx. 4125 case 'd': // edx. 4126 case 'S': // esi. 4127 case 'D': // edi. 4128 case 'A': // edx:eax. 4129 case 't': // Top of floating point stack. 4130 case 'u': // Second from top of floating point stack. 4131 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4132 case 'y': // Any MMX register. 4133 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4134 case 'x': // Any SSE register. 4135 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4136 // for intermideate k reg operations). 4137 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4138 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4139 case 'l': // "Index" registers: any general register that can be used as an 4140 // index in a base+index memory access. 4141 Info.setAllowsRegister(); 4142 return true; 4143 // Floating point constant constraints. 4144 case 'C': // SSE floating point constant. 4145 case 'G': // x87 floating point constant. 4146 return true; 4147 } 4148 } 4149 4150 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4151 unsigned Size) const { 4152 // Strip off constraint modifiers. 4153 while (Constraint[0] == '=' || 4154 Constraint[0] == '+' || 4155 Constraint[0] == '&') 4156 Constraint = Constraint.substr(1); 4157 4158 return validateOperandSize(Constraint, Size); 4159 } 4160 4161 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4162 unsigned Size) const { 4163 return validateOperandSize(Constraint, Size); 4164 } 4165 4166 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4167 unsigned Size) const { 4168 switch (Constraint[0]) { 4169 default: break; 4170 case 'k': 4171 // Registers k0-k7 (AVX512) size limit is 64 bit. 4172 case 'y': 4173 return Size <= 64; 4174 case 'f': 4175 case 't': 4176 case 'u': 4177 return Size <= 128; 4178 case 'v': 4179 case 'x': 4180 if (SSELevel >= AVX512F) 4181 // 512-bit zmm registers can be used if target supports AVX512F. 4182 return Size <= 512U; 4183 else if (SSELevel >= AVX) 4184 // 256-bit ymm registers can be used if target supports AVX. 4185 return Size <= 256U; 4186 return Size <= 128U; 4187 case 'Y': 4188 // 'Y' is the first character for several 2-character constraints. 4189 switch (Constraint[1]) { 4190 default: break; 4191 case 'm': 4192 // 'Ym' is synonymous with 'y'. 4193 case 'k': 4194 return Size <= 64; 4195 case 'i': 4196 case 't': 4197 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4198 if (SSELevel >= AVX512F) 4199 return Size <= 512U; 4200 else if (SSELevel >= AVX) 4201 return Size <= 256U; 4202 return SSELevel >= SSE2 && Size <= 128U; 4203 } 4204 4205 } 4206 4207 return true; 4208 } 4209 4210 std::string 4211 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4212 switch (*Constraint) { 4213 case 'a': return std::string("{ax}"); 4214 case 'b': return std::string("{bx}"); 4215 case 'c': return std::string("{cx}"); 4216 case 'd': return std::string("{dx}"); 4217 case 'S': return std::string("{si}"); 4218 case 'D': return std::string("{di}"); 4219 case 'p': // address 4220 return std::string("im"); 4221 case 't': // top of floating point stack. 4222 return std::string("{st}"); 4223 case 'u': // second from top of floating point stack. 4224 return std::string("{st(1)}"); // second from top of floating point stack. 4225 case 'Y': 4226 switch (Constraint[1]) { 4227 default: 4228 // Break from inner switch and fall through (copy single char), 4229 // continue parsing after copying the current constraint into 4230 // the return string. 4231 break; 4232 case 'k': 4233 // "^" hints llvm that this is a 2 letter constraint. 4234 // "Constraint++" is used to promote the string iterator 4235 // to the next constraint. 4236 return std::string("^") + std::string(Constraint++, 2); 4237 } 4238 LLVM_FALLTHROUGH; 4239 default: 4240 return std::string(1, *Constraint); 4241 } 4242 } 4243 4244 // X86-32 generic target 4245 class X86_32TargetInfo : public X86TargetInfo { 4246 public: 4247 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4248 : X86TargetInfo(Triple, Opts) { 4249 DoubleAlign = LongLongAlign = 32; 4250 LongDoubleWidth = 96; 4251 LongDoubleAlign = 32; 4252 SuitableAlign = 128; 4253 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4254 SizeType = UnsignedInt; 4255 PtrDiffType = SignedInt; 4256 IntPtrType = SignedInt; 4257 RegParmMax = 3; 4258 4259 // Use fpret for all types. 4260 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4261 (1 << TargetInfo::Double) | 4262 (1 << TargetInfo::LongDouble)); 4263 4264 // x86-32 has atomics up to 8 bytes 4265 // FIXME: Check that we actually have cmpxchg8b before setting 4266 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4267 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4268 } 4269 BuiltinVaListKind getBuiltinVaListKind() const override { 4270 return TargetInfo::CharPtrBuiltinVaList; 4271 } 4272 4273 int getEHDataRegisterNumber(unsigned RegNo) const override { 4274 if (RegNo == 0) return 0; 4275 if (RegNo == 1) return 2; 4276 return -1; 4277 } 4278 bool validateOperandSize(StringRef Constraint, 4279 unsigned Size) const override { 4280 switch (Constraint[0]) { 4281 default: break; 4282 case 'R': 4283 case 'q': 4284 case 'Q': 4285 case 'a': 4286 case 'b': 4287 case 'c': 4288 case 'd': 4289 case 'S': 4290 case 'D': 4291 return Size <= 32; 4292 case 'A': 4293 return Size <= 64; 4294 } 4295 4296 return X86TargetInfo::validateOperandSize(Constraint, Size); 4297 } 4298 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4299 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4300 Builtin::FirstTSBuiltin + 1); 4301 } 4302 }; 4303 4304 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4305 public: 4306 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4307 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4308 4309 unsigned getFloatEvalMethod() const override { 4310 unsigned Major, Minor, Micro; 4311 getTriple().getOSVersion(Major, Minor, Micro); 4312 // New NetBSD uses the default rounding mode. 4313 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4314 return X86_32TargetInfo::getFloatEvalMethod(); 4315 // NetBSD before 6.99.26 defaults to "double" rounding. 4316 return 1; 4317 } 4318 }; 4319 4320 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4321 public: 4322 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4323 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4324 SizeType = UnsignedLong; 4325 IntPtrType = SignedLong; 4326 PtrDiffType = SignedLong; 4327 } 4328 }; 4329 4330 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4331 public: 4332 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4333 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4334 SizeType = UnsignedLong; 4335 IntPtrType = SignedLong; 4336 PtrDiffType = SignedLong; 4337 } 4338 }; 4339 4340 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4341 public: 4342 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4343 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4344 LongDoubleWidth = 128; 4345 LongDoubleAlign = 128; 4346 SuitableAlign = 128; 4347 MaxVectorAlign = 256; 4348 // The watchOS simulator uses the builtin bool type for Objective-C. 4349 llvm::Triple T = llvm::Triple(Triple); 4350 if (T.isWatchOS()) 4351 UseSignedCharForObjCBool = false; 4352 SizeType = UnsignedLong; 4353 IntPtrType = SignedLong; 4354 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4355 HasAlignMac68kSupport = true; 4356 } 4357 4358 bool handleTargetFeatures(std::vector<std::string> &Features, 4359 DiagnosticsEngine &Diags) override { 4360 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4361 Diags)) 4362 return false; 4363 // We now know the features we have: we can decide how to align vectors. 4364 MaxVectorAlign = 4365 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4366 return true; 4367 } 4368 }; 4369 4370 // x86-32 Windows target 4371 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4372 public: 4373 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4374 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4375 WCharType = UnsignedShort; 4376 DoubleAlign = LongLongAlign = 64; 4377 bool IsWinCOFF = 4378 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4379 resetDataLayout(IsWinCOFF 4380 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4381 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4382 } 4383 void getTargetDefines(const LangOptions &Opts, 4384 MacroBuilder &Builder) const override { 4385 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4386 } 4387 }; 4388 4389 // x86-32 Windows Visual Studio target 4390 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4391 public: 4392 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4393 const TargetOptions &Opts) 4394 : WindowsX86_32TargetInfo(Triple, Opts) { 4395 LongDoubleWidth = LongDoubleAlign = 64; 4396 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4397 } 4398 void getTargetDefines(const LangOptions &Opts, 4399 MacroBuilder &Builder) const override { 4400 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4401 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4402 // The value of the following reflects processor type. 4403 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4404 // We lost the original triple, so we use the default. 4405 Builder.defineMacro("_M_IX86", "600"); 4406 } 4407 }; 4408 4409 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4410 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4411 // supports __declspec natively under -fms-extensions, but we define a no-op 4412 // __declspec macro anyway for pre-processor compatibility. 4413 if (Opts.MicrosoftExt) 4414 Builder.defineMacro("__declspec", "__declspec"); 4415 else 4416 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4417 4418 if (!Opts.MicrosoftExt) { 4419 // Provide macros for all the calling convention keywords. Provide both 4420 // single and double underscore prefixed variants. These are available on 4421 // x64 as well as x86, even though they have no effect. 4422 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4423 for (const char *CC : CCs) { 4424 std::string GCCSpelling = "__attribute__((__"; 4425 GCCSpelling += CC; 4426 GCCSpelling += "__))"; 4427 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4428 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4429 } 4430 } 4431 } 4432 4433 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4434 Builder.defineMacro("__MSVCRT__"); 4435 Builder.defineMacro("__MINGW32__"); 4436 addCygMingDefines(Opts, Builder); 4437 } 4438 4439 // x86-32 MinGW target 4440 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4441 public: 4442 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4443 : WindowsX86_32TargetInfo(Triple, Opts) {} 4444 void getTargetDefines(const LangOptions &Opts, 4445 MacroBuilder &Builder) const override { 4446 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4447 DefineStd(Builder, "WIN32", Opts); 4448 DefineStd(Builder, "WINNT", Opts); 4449 Builder.defineMacro("_X86_"); 4450 addMinGWDefines(Opts, Builder); 4451 } 4452 }; 4453 4454 // x86-32 Cygwin target 4455 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4456 public: 4457 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4458 : X86_32TargetInfo(Triple, Opts) { 4459 WCharType = UnsignedShort; 4460 DoubleAlign = LongLongAlign = 64; 4461 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4462 } 4463 void getTargetDefines(const LangOptions &Opts, 4464 MacroBuilder &Builder) const override { 4465 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4466 Builder.defineMacro("_X86_"); 4467 Builder.defineMacro("__CYGWIN__"); 4468 Builder.defineMacro("__CYGWIN32__"); 4469 addCygMingDefines(Opts, Builder); 4470 DefineStd(Builder, "unix", Opts); 4471 if (Opts.CPlusPlus) 4472 Builder.defineMacro("_GNU_SOURCE"); 4473 } 4474 }; 4475 4476 // x86-32 Haiku target 4477 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4478 public: 4479 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4480 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4481 } 4482 void getTargetDefines(const LangOptions &Opts, 4483 MacroBuilder &Builder) const override { 4484 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4485 Builder.defineMacro("__INTEL__"); 4486 } 4487 }; 4488 4489 // X86-32 MCU target 4490 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4491 public: 4492 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4493 : X86_32TargetInfo(Triple, Opts) { 4494 LongDoubleWidth = 64; 4495 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4496 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4497 WIntType = UnsignedInt; 4498 } 4499 4500 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4501 // On MCU we support only C calling convention. 4502 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4503 } 4504 4505 void getTargetDefines(const LangOptions &Opts, 4506 MacroBuilder &Builder) const override { 4507 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4508 Builder.defineMacro("__iamcu"); 4509 Builder.defineMacro("__iamcu__"); 4510 } 4511 4512 bool allowsLargerPreferedTypeAlignment() const override { 4513 return false; 4514 } 4515 }; 4516 4517 // RTEMS Target 4518 template<typename Target> 4519 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4520 protected: 4521 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4522 MacroBuilder &Builder) const override { 4523 // RTEMS defines; list based off of gcc output 4524 4525 Builder.defineMacro("__rtems__"); 4526 Builder.defineMacro("__ELF__"); 4527 } 4528 4529 public: 4530 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4531 : OSTargetInfo<Target>(Triple, Opts) { 4532 switch (Triple.getArch()) { 4533 default: 4534 case llvm::Triple::x86: 4535 // this->MCountName = ".mcount"; 4536 break; 4537 case llvm::Triple::mips: 4538 case llvm::Triple::mipsel: 4539 case llvm::Triple::ppc: 4540 case llvm::Triple::ppc64: 4541 case llvm::Triple::ppc64le: 4542 // this->MCountName = "_mcount"; 4543 break; 4544 case llvm::Triple::arm: 4545 // this->MCountName = "__mcount"; 4546 break; 4547 } 4548 } 4549 }; 4550 4551 // x86-32 RTEMS target 4552 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4553 public: 4554 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4555 : X86_32TargetInfo(Triple, Opts) { 4556 SizeType = UnsignedLong; 4557 IntPtrType = SignedLong; 4558 PtrDiffType = SignedLong; 4559 } 4560 void getTargetDefines(const LangOptions &Opts, 4561 MacroBuilder &Builder) const override { 4562 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4563 Builder.defineMacro("__INTEL__"); 4564 Builder.defineMacro("__rtems__"); 4565 } 4566 }; 4567 4568 // x86-64 generic target 4569 class X86_64TargetInfo : public X86TargetInfo { 4570 public: 4571 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4572 : X86TargetInfo(Triple, Opts) { 4573 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4574 bool IsWinCOFF = 4575 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4576 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4577 LongDoubleWidth = 128; 4578 LongDoubleAlign = 128; 4579 LargeArrayMinWidth = 128; 4580 LargeArrayAlign = 128; 4581 SuitableAlign = 128; 4582 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4583 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4584 IntPtrType = IsX32 ? SignedInt : SignedLong; 4585 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4586 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4587 RegParmMax = 6; 4588 4589 // Pointers are 32-bit in x32. 4590 resetDataLayout(IsX32 4591 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4592 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4593 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4594 4595 // Use fpret only for long double. 4596 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4597 4598 // Use fp2ret for _Complex long double. 4599 ComplexLongDoubleUsesFP2Ret = true; 4600 4601 // Make __builtin_ms_va_list available. 4602 HasBuiltinMSVaList = true; 4603 4604 // x86-64 has atomics up to 16 bytes. 4605 MaxAtomicPromoteWidth = 128; 4606 MaxAtomicInlineWidth = 128; 4607 } 4608 BuiltinVaListKind getBuiltinVaListKind() const override { 4609 return TargetInfo::X86_64ABIBuiltinVaList; 4610 } 4611 4612 int getEHDataRegisterNumber(unsigned RegNo) const override { 4613 if (RegNo == 0) return 0; 4614 if (RegNo == 1) return 1; 4615 return -1; 4616 } 4617 4618 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4619 switch (CC) { 4620 case CC_C: 4621 case CC_Swift: 4622 case CC_X86VectorCall: 4623 case CC_IntelOclBicc: 4624 case CC_X86_64Win64: 4625 case CC_PreserveMost: 4626 case CC_PreserveAll: 4627 case CC_X86RegCall: 4628 return CCCR_OK; 4629 default: 4630 return CCCR_Warning; 4631 } 4632 } 4633 4634 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4635 return CC_C; 4636 } 4637 4638 // for x32 we need it here explicitly 4639 bool hasInt128Type() const override { return true; } 4640 unsigned getUnwindWordWidth() const override { return 64; } 4641 unsigned getRegisterWidth() const override { return 64; } 4642 4643 bool validateGlobalRegisterVariable(StringRef RegName, 4644 unsigned RegSize, 4645 bool &HasSizeMismatch) const override { 4646 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4647 // handle. 4648 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4649 // Check that the register size is 64-bit. 4650 HasSizeMismatch = RegSize != 64; 4651 return true; 4652 } 4653 4654 // Check if the register is a 32-bit register the backend can handle. 4655 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4656 HasSizeMismatch); 4657 } 4658 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4659 return llvm::makeArrayRef(BuiltinInfoX86, 4660 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4661 } 4662 }; 4663 4664 // x86-64 Windows target 4665 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4666 public: 4667 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4668 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4669 WCharType = UnsignedShort; 4670 LongWidth = LongAlign = 32; 4671 DoubleAlign = LongLongAlign = 64; 4672 IntMaxType = SignedLongLong; 4673 Int64Type = SignedLongLong; 4674 SizeType = UnsignedLongLong; 4675 PtrDiffType = SignedLongLong; 4676 IntPtrType = SignedLongLong; 4677 } 4678 4679 void getTargetDefines(const LangOptions &Opts, 4680 MacroBuilder &Builder) const override { 4681 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4682 Builder.defineMacro("_WIN64"); 4683 } 4684 4685 BuiltinVaListKind getBuiltinVaListKind() const override { 4686 return TargetInfo::CharPtrBuiltinVaList; 4687 } 4688 4689 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4690 switch (CC) { 4691 case CC_X86StdCall: 4692 case CC_X86ThisCall: 4693 case CC_X86FastCall: 4694 return CCCR_Ignore; 4695 case CC_C: 4696 case CC_X86VectorCall: 4697 case CC_IntelOclBicc: 4698 case CC_X86_64SysV: 4699 case CC_Swift: 4700 case CC_X86RegCall: 4701 return CCCR_OK; 4702 default: 4703 return CCCR_Warning; 4704 } 4705 } 4706 }; 4707 4708 // x86-64 Windows Visual Studio target 4709 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4710 public: 4711 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4712 const TargetOptions &Opts) 4713 : WindowsX86_64TargetInfo(Triple, Opts) { 4714 LongDoubleWidth = LongDoubleAlign = 64; 4715 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4716 } 4717 void getTargetDefines(const LangOptions &Opts, 4718 MacroBuilder &Builder) const override { 4719 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4720 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4721 Builder.defineMacro("_M_X64", "100"); 4722 Builder.defineMacro("_M_AMD64", "100"); 4723 } 4724 }; 4725 4726 // x86-64 MinGW target 4727 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4728 public: 4729 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4730 : WindowsX86_64TargetInfo(Triple, Opts) { 4731 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4732 // with x86 FP ops. Weird. 4733 LongDoubleWidth = LongDoubleAlign = 128; 4734 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 4735 } 4736 4737 void getTargetDefines(const LangOptions &Opts, 4738 MacroBuilder &Builder) const override { 4739 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4740 DefineStd(Builder, "WIN64", Opts); 4741 Builder.defineMacro("__MINGW64__"); 4742 addMinGWDefines(Opts, Builder); 4743 4744 // GCC defines this macro when it is using __gxx_personality_seh0. 4745 if (!Opts.SjLjExceptions) 4746 Builder.defineMacro("__SEH__"); 4747 } 4748 }; 4749 4750 // x86-64 Cygwin target 4751 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4752 public: 4753 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4754 : X86_64TargetInfo(Triple, Opts) { 4755 TLSSupported = false; 4756 WCharType = UnsignedShort; 4757 } 4758 void getTargetDefines(const LangOptions &Opts, 4759 MacroBuilder &Builder) const override { 4760 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4761 Builder.defineMacro("__x86_64__"); 4762 Builder.defineMacro("__CYGWIN__"); 4763 Builder.defineMacro("__CYGWIN64__"); 4764 addCygMingDefines(Opts, Builder); 4765 DefineStd(Builder, "unix", Opts); 4766 if (Opts.CPlusPlus) 4767 Builder.defineMacro("_GNU_SOURCE"); 4768 4769 // GCC defines this macro when it is using __gxx_personality_seh0. 4770 if (!Opts.SjLjExceptions) 4771 Builder.defineMacro("__SEH__"); 4772 } 4773 }; 4774 4775 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4776 public: 4777 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4778 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4779 Int64Type = SignedLongLong; 4780 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4781 llvm::Triple T = llvm::Triple(Triple); 4782 if (T.isiOS()) 4783 UseSignedCharForObjCBool = false; 4784 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4785 } 4786 4787 bool handleTargetFeatures(std::vector<std::string> &Features, 4788 DiagnosticsEngine &Diags) override { 4789 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4790 Diags)) 4791 return false; 4792 // We now know the features we have: we can decide how to align vectors. 4793 MaxVectorAlign = 4794 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4795 return true; 4796 } 4797 }; 4798 4799 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4800 public: 4801 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4802 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4803 IntMaxType = SignedLongLong; 4804 Int64Type = SignedLongLong; 4805 } 4806 }; 4807 4808 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4809 public: 4810 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4811 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4812 IntMaxType = SignedLongLong; 4813 Int64Type = SignedLongLong; 4814 } 4815 }; 4816 4817 class ARMTargetInfo : public TargetInfo { 4818 // Possible FPU choices. 4819 enum FPUMode { 4820 VFP2FPU = (1 << 0), 4821 VFP3FPU = (1 << 1), 4822 VFP4FPU = (1 << 2), 4823 NeonFPU = (1 << 3), 4824 FPARMV8 = (1 << 4) 4825 }; 4826 4827 // Possible HWDiv features. 4828 enum HWDivMode { 4829 HWDivThumb = (1 << 0), 4830 HWDivARM = (1 << 1) 4831 }; 4832 4833 static bool FPUModeIsVFP(FPUMode Mode) { 4834 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4835 } 4836 4837 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4838 static const char * const GCCRegNames[]; 4839 4840 std::string ABI, CPU; 4841 4842 StringRef CPUProfile; 4843 StringRef CPUAttr; 4844 4845 enum { 4846 FP_Default, 4847 FP_VFP, 4848 FP_Neon 4849 } FPMath; 4850 4851 unsigned ArchISA; 4852 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4853 unsigned ArchProfile; 4854 unsigned ArchVersion; 4855 4856 unsigned FPU : 5; 4857 4858 unsigned IsAAPCS : 1; 4859 unsigned HWDiv : 2; 4860 4861 // Initialized via features. 4862 unsigned SoftFloat : 1; 4863 unsigned SoftFloatABI : 1; 4864 4865 unsigned CRC : 1; 4866 unsigned Crypto : 1; 4867 unsigned DSP : 1; 4868 unsigned Unaligned : 1; 4869 4870 enum { 4871 LDREX_B = (1 << 0), /// byte (8-bit) 4872 LDREX_H = (1 << 1), /// half (16-bit) 4873 LDREX_W = (1 << 2), /// word (32-bit) 4874 LDREX_D = (1 << 3), /// double (64-bit) 4875 }; 4876 4877 uint32_t LDREX; 4878 4879 // ACLE 6.5.1 Hardware floating point 4880 enum { 4881 HW_FP_HP = (1 << 1), /// half (16-bit) 4882 HW_FP_SP = (1 << 2), /// single (32-bit) 4883 HW_FP_DP = (1 << 3), /// double (64-bit) 4884 }; 4885 uint32_t HW_FP; 4886 4887 static const Builtin::Info BuiltinInfo[]; 4888 4889 void setABIAAPCS() { 4890 IsAAPCS = true; 4891 4892 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4893 const llvm::Triple &T = getTriple(); 4894 4895 // size_t is unsigned long on MachO-derived environments, NetBSD, 4896 // OpenBSD and Bitrig. 4897 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4898 T.getOS() == llvm::Triple::OpenBSD || 4899 T.getOS() == llvm::Triple::Bitrig) 4900 SizeType = UnsignedLong; 4901 else 4902 SizeType = UnsignedInt; 4903 4904 switch (T.getOS()) { 4905 case llvm::Triple::NetBSD: 4906 case llvm::Triple::OpenBSD: 4907 WCharType = SignedInt; 4908 break; 4909 case llvm::Triple::Win32: 4910 WCharType = UnsignedShort; 4911 break; 4912 case llvm::Triple::Linux: 4913 default: 4914 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4915 WCharType = UnsignedInt; 4916 break; 4917 } 4918 4919 UseBitFieldTypeAlignment = true; 4920 4921 ZeroLengthBitfieldBoundary = 0; 4922 4923 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4924 // so set preferred for small types to 32. 4925 if (T.isOSBinFormatMachO()) { 4926 resetDataLayout(BigEndian 4927 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4928 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4929 } else if (T.isOSWindows()) { 4930 assert(!BigEndian && "Windows on ARM does not support big endian"); 4931 resetDataLayout("e" 4932 "-m:w" 4933 "-p:32:32" 4934 "-i64:64" 4935 "-v128:64:128" 4936 "-a:0:32" 4937 "-n32" 4938 "-S64"); 4939 } else if (T.isOSNaCl()) { 4940 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4941 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4942 } else { 4943 resetDataLayout(BigEndian 4944 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4945 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4946 } 4947 4948 // FIXME: Enumerated types are variable width in straight AAPCS. 4949 } 4950 4951 void setABIAPCS(bool IsAAPCS16) { 4952 const llvm::Triple &T = getTriple(); 4953 4954 IsAAPCS = false; 4955 4956 if (IsAAPCS16) 4957 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4958 else 4959 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4960 4961 // size_t is unsigned int on FreeBSD. 4962 if (T.getOS() == llvm::Triple::FreeBSD) 4963 SizeType = UnsignedInt; 4964 else 4965 SizeType = UnsignedLong; 4966 4967 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4968 WCharType = SignedInt; 4969 4970 // Do not respect the alignment of bit-field types when laying out 4971 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4972 UseBitFieldTypeAlignment = false; 4973 4974 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4975 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4976 /// gcc. 4977 ZeroLengthBitfieldBoundary = 32; 4978 4979 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4980 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4981 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4982 } else if (T.isOSBinFormatMachO()) 4983 resetDataLayout( 4984 BigEndian 4985 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4986 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4987 else 4988 resetDataLayout( 4989 BigEndian 4990 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4991 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4992 4993 // FIXME: Override "preferred align" for double and long long. 4994 } 4995 4996 void setArchInfo() { 4997 StringRef ArchName = getTriple().getArchName(); 4998 4999 ArchISA = llvm::ARM::parseArchISA(ArchName); 5000 CPU = llvm::ARM::getDefaultCPU(ArchName); 5001 unsigned AK = llvm::ARM::parseArch(ArchName); 5002 if (AK != llvm::ARM::AK_INVALID) 5003 ArchKind = AK; 5004 setArchInfo(ArchKind); 5005 } 5006 5007 void setArchInfo(unsigned Kind) { 5008 StringRef SubArch; 5009 5010 // cache TargetParser info 5011 ArchKind = Kind; 5012 SubArch = llvm::ARM::getSubArch(ArchKind); 5013 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5014 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5015 5016 // cache CPU related strings 5017 CPUAttr = getCPUAttr(); 5018 CPUProfile = getCPUProfile(); 5019 } 5020 5021 void setAtomic() { 5022 // when triple does not specify a sub arch, 5023 // then we are not using inline atomics 5024 bool ShouldUseInlineAtomic = 5025 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5026 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5027 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5028 if (ArchProfile == llvm::ARM::PK_M) { 5029 MaxAtomicPromoteWidth = 32; 5030 if (ShouldUseInlineAtomic) 5031 MaxAtomicInlineWidth = 32; 5032 } 5033 else { 5034 MaxAtomicPromoteWidth = 64; 5035 if (ShouldUseInlineAtomic) 5036 MaxAtomicInlineWidth = 64; 5037 } 5038 } 5039 5040 bool isThumb() const { 5041 return (ArchISA == llvm::ARM::IK_THUMB); 5042 } 5043 5044 bool supportsThumb() const { 5045 return CPUAttr.count('T') || ArchVersion >= 6; 5046 } 5047 5048 bool supportsThumb2() const { 5049 return CPUAttr.equals("6T2") || 5050 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5051 } 5052 5053 StringRef getCPUAttr() const { 5054 // For most sub-arches, the build attribute CPU name is enough. 5055 // For Cortex variants, it's slightly different. 5056 switch(ArchKind) { 5057 default: 5058 return llvm::ARM::getCPUAttr(ArchKind); 5059 case llvm::ARM::AK_ARMV6M: 5060 return "6M"; 5061 case llvm::ARM::AK_ARMV7S: 5062 return "7S"; 5063 case llvm::ARM::AK_ARMV7A: 5064 return "7A"; 5065 case llvm::ARM::AK_ARMV7R: 5066 return "7R"; 5067 case llvm::ARM::AK_ARMV7M: 5068 return "7M"; 5069 case llvm::ARM::AK_ARMV7EM: 5070 return "7EM"; 5071 case llvm::ARM::AK_ARMV7VE: 5072 return "7VE"; 5073 case llvm::ARM::AK_ARMV8A: 5074 return "8A"; 5075 case llvm::ARM::AK_ARMV8_1A: 5076 return "8_1A"; 5077 case llvm::ARM::AK_ARMV8_2A: 5078 return "8_2A"; 5079 case llvm::ARM::AK_ARMV8MBaseline: 5080 return "8M_BASE"; 5081 case llvm::ARM::AK_ARMV8MMainline: 5082 return "8M_MAIN"; 5083 case llvm::ARM::AK_ARMV8R: 5084 return "8R"; 5085 } 5086 } 5087 5088 StringRef getCPUProfile() const { 5089 switch(ArchProfile) { 5090 case llvm::ARM::PK_A: 5091 return "A"; 5092 case llvm::ARM::PK_R: 5093 return "R"; 5094 case llvm::ARM::PK_M: 5095 return "M"; 5096 default: 5097 return ""; 5098 } 5099 } 5100 5101 public: 5102 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5103 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5104 HW_FP(0) { 5105 5106 switch (getTriple().getOS()) { 5107 case llvm::Triple::NetBSD: 5108 case llvm::Triple::OpenBSD: 5109 PtrDiffType = SignedLong; 5110 break; 5111 default: 5112 PtrDiffType = SignedInt; 5113 break; 5114 } 5115 5116 // Cache arch related info. 5117 setArchInfo(); 5118 5119 // {} in inline assembly are neon specifiers, not assembly variant 5120 // specifiers. 5121 NoAsmVariants = true; 5122 5123 // FIXME: This duplicates code from the driver that sets the -target-abi 5124 // option - this code is used if -target-abi isn't passed and should 5125 // be unified in some way. 5126 if (Triple.isOSBinFormatMachO()) { 5127 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5128 // the frontend matches that. 5129 if (Triple.getEnvironment() == llvm::Triple::EABI || 5130 Triple.getOS() == llvm::Triple::UnknownOS || 5131 ArchProfile == llvm::ARM::PK_M) { 5132 setABI("aapcs"); 5133 } else if (Triple.isWatchABI()) { 5134 setABI("aapcs16"); 5135 } else { 5136 setABI("apcs-gnu"); 5137 } 5138 } else if (Triple.isOSWindows()) { 5139 // FIXME: this is invalid for WindowsCE 5140 setABI("aapcs"); 5141 } else { 5142 // Select the default based on the platform. 5143 switch (Triple.getEnvironment()) { 5144 case llvm::Triple::Android: 5145 case llvm::Triple::GNUEABI: 5146 case llvm::Triple::GNUEABIHF: 5147 case llvm::Triple::MuslEABI: 5148 case llvm::Triple::MuslEABIHF: 5149 setABI("aapcs-linux"); 5150 break; 5151 case llvm::Triple::EABIHF: 5152 case llvm::Triple::EABI: 5153 setABI("aapcs"); 5154 break; 5155 case llvm::Triple::GNU: 5156 setABI("apcs-gnu"); 5157 break; 5158 default: 5159 if (Triple.getOS() == llvm::Triple::NetBSD) 5160 setABI("apcs-gnu"); 5161 else 5162 setABI("aapcs"); 5163 break; 5164 } 5165 } 5166 5167 // ARM targets default to using the ARM C++ ABI. 5168 TheCXXABI.set(TargetCXXABI::GenericARM); 5169 5170 // ARM has atomics up to 8 bytes 5171 setAtomic(); 5172 5173 // Do force alignment of members that follow zero length bitfields. If 5174 // the alignment of the zero-length bitfield is greater than the member 5175 // that follows it, `bar', `bar' will be aligned as the type of the 5176 // zero length bitfield. 5177 UseZeroLengthBitfieldAlignment = true; 5178 5179 if (Triple.getOS() == llvm::Triple::Linux || 5180 Triple.getOS() == llvm::Triple::UnknownOS) 5181 this->MCountName = 5182 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5183 } 5184 5185 StringRef getABI() const override { return ABI; } 5186 5187 bool setABI(const std::string &Name) override { 5188 ABI = Name; 5189 5190 // The defaults (above) are for AAPCS, check if we need to change them. 5191 // 5192 // FIXME: We need support for -meabi... we could just mangle it into the 5193 // name. 5194 if (Name == "apcs-gnu" || Name == "aapcs16") { 5195 setABIAPCS(Name == "aapcs16"); 5196 return true; 5197 } 5198 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5199 setABIAAPCS(); 5200 return true; 5201 } 5202 return false; 5203 } 5204 5205 // FIXME: This should be based on Arch attributes, not CPU names. 5206 bool 5207 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5208 StringRef CPU, 5209 const std::vector<std::string> &FeaturesVec) const override { 5210 5211 std::vector<StringRef> TargetFeatures; 5212 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5213 5214 // get default FPU features 5215 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5216 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5217 5218 // get default Extension features 5219 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5220 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5221 5222 for (auto Feature : TargetFeatures) 5223 if (Feature[0] == '+') 5224 Features[Feature.drop_front(1)] = true; 5225 5226 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5227 } 5228 5229 bool handleTargetFeatures(std::vector<std::string> &Features, 5230 DiagnosticsEngine &Diags) override { 5231 FPU = 0; 5232 CRC = 0; 5233 Crypto = 0; 5234 DSP = 0; 5235 Unaligned = 1; 5236 SoftFloat = SoftFloatABI = false; 5237 HWDiv = 0; 5238 5239 // This does not diagnose illegal cases like having both 5240 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5241 uint32_t HW_FP_remove = 0; 5242 for (const auto &Feature : Features) { 5243 if (Feature == "+soft-float") { 5244 SoftFloat = true; 5245 } else if (Feature == "+soft-float-abi") { 5246 SoftFloatABI = true; 5247 } else if (Feature == "+vfp2") { 5248 FPU |= VFP2FPU; 5249 HW_FP |= HW_FP_SP | HW_FP_DP; 5250 } else if (Feature == "+vfp3") { 5251 FPU |= VFP3FPU; 5252 HW_FP |= HW_FP_SP | HW_FP_DP; 5253 } else if (Feature == "+vfp4") { 5254 FPU |= VFP4FPU; 5255 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5256 } else if (Feature == "+fp-armv8") { 5257 FPU |= FPARMV8; 5258 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5259 } else if (Feature == "+neon") { 5260 FPU |= NeonFPU; 5261 HW_FP |= HW_FP_SP | HW_FP_DP; 5262 } else if (Feature == "+hwdiv") { 5263 HWDiv |= HWDivThumb; 5264 } else if (Feature == "+hwdiv-arm") { 5265 HWDiv |= HWDivARM; 5266 } else if (Feature == "+crc") { 5267 CRC = 1; 5268 } else if (Feature == "+crypto") { 5269 Crypto = 1; 5270 } else if (Feature == "+dsp") { 5271 DSP = 1; 5272 } else if (Feature == "+fp-only-sp") { 5273 HW_FP_remove |= HW_FP_DP; 5274 } else if (Feature == "+strict-align") { 5275 Unaligned = 0; 5276 } else if (Feature == "+fp16") { 5277 HW_FP |= HW_FP_HP; 5278 } 5279 } 5280 HW_FP &= ~HW_FP_remove; 5281 5282 switch (ArchVersion) { 5283 case 6: 5284 if (ArchProfile == llvm::ARM::PK_M) 5285 LDREX = 0; 5286 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5287 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5288 else 5289 LDREX = LDREX_W; 5290 break; 5291 case 7: 5292 if (ArchProfile == llvm::ARM::PK_M) 5293 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5294 else 5295 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5296 break; 5297 case 8: 5298 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5299 } 5300 5301 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5302 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5303 return false; 5304 } 5305 5306 if (FPMath == FP_Neon) 5307 Features.push_back("+neonfp"); 5308 else if (FPMath == FP_VFP) 5309 Features.push_back("-neonfp"); 5310 5311 // Remove front-end specific options which the backend handles differently. 5312 auto Feature = 5313 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5314 if (Feature != Features.end()) 5315 Features.erase(Feature); 5316 5317 return true; 5318 } 5319 5320 bool hasFeature(StringRef Feature) const override { 5321 return llvm::StringSwitch<bool>(Feature) 5322 .Case("arm", true) 5323 .Case("aarch32", true) 5324 .Case("softfloat", SoftFloat) 5325 .Case("thumb", isThumb()) 5326 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5327 .Case("hwdiv", HWDiv & HWDivThumb) 5328 .Case("hwdiv-arm", HWDiv & HWDivARM) 5329 .Default(false); 5330 } 5331 5332 bool setCPU(const std::string &Name) override { 5333 if (Name != "generic") 5334 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5335 5336 if (ArchKind == llvm::ARM::AK_INVALID) 5337 return false; 5338 setAtomic(); 5339 CPU = Name; 5340 return true; 5341 } 5342 5343 bool setFPMath(StringRef Name) override; 5344 5345 void getTargetDefines(const LangOptions &Opts, 5346 MacroBuilder &Builder) const override { 5347 // Target identification. 5348 Builder.defineMacro("__arm"); 5349 Builder.defineMacro("__arm__"); 5350 // For bare-metal none-eabi. 5351 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5352 getTriple().getEnvironment() == llvm::Triple::EABI) 5353 Builder.defineMacro("__ELF__"); 5354 5355 // Target properties. 5356 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5357 5358 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5359 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5360 if (getTriple().isWatchABI()) 5361 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5362 5363 if (!CPUAttr.empty()) 5364 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5365 5366 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5367 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5368 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5369 5370 if (ArchVersion >= 8) { 5371 // ACLE 6.5.7 Crypto Extension 5372 if (Crypto) 5373 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5374 // ACLE 6.5.8 CRC32 Extension 5375 if (CRC) 5376 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5377 // ACLE 6.5.10 Numeric Maximum and Minimum 5378 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5379 // ACLE 6.5.9 Directed Rounding 5380 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5381 } 5382 5383 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5384 // is not defined for the M-profile. 5385 // NOTE that the default profile is assumed to be 'A' 5386 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5387 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5388 5389 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5390 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5391 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5392 // v7 and v8 architectures excluding v8-M Baseline. 5393 if (supportsThumb2()) 5394 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5395 else if (supportsThumb()) 5396 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5397 5398 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5399 // instruction set such as ARM or Thumb. 5400 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5401 5402 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5403 5404 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5405 if (!CPUProfile.empty()) 5406 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5407 5408 // ACLE 6.4.3 Unaligned access supported in hardware 5409 if (Unaligned) 5410 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5411 5412 // ACLE 6.4.4 LDREX/STREX 5413 if (LDREX) 5414 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5415 5416 // ACLE 6.4.5 CLZ 5417 if (ArchVersion == 5 || 5418 (ArchVersion == 6 && CPUProfile != "M") || 5419 ArchVersion > 6) 5420 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5421 5422 // ACLE 6.5.1 Hardware Floating Point 5423 if (HW_FP) 5424 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5425 5426 // ACLE predefines. 5427 Builder.defineMacro("__ARM_ACLE", "200"); 5428 5429 // FP16 support (we currently only support IEEE format). 5430 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5431 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5432 5433 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5434 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5435 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5436 5437 // Subtarget options. 5438 5439 // FIXME: It's more complicated than this and we don't really support 5440 // interworking. 5441 // Windows on ARM does not "support" interworking 5442 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5443 Builder.defineMacro("__THUMB_INTERWORK__"); 5444 5445 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5446 // Embedded targets on Darwin follow AAPCS, but not EABI. 5447 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5448 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5449 Builder.defineMacro("__ARM_EABI__"); 5450 Builder.defineMacro("__ARM_PCS", "1"); 5451 } 5452 5453 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5454 ABI == "aapcs16") 5455 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5456 5457 if (SoftFloat) 5458 Builder.defineMacro("__SOFTFP__"); 5459 5460 if (ArchKind == llvm::ARM::AK_XSCALE) 5461 Builder.defineMacro("__XSCALE__"); 5462 5463 if (isThumb()) { 5464 Builder.defineMacro("__THUMBEL__"); 5465 Builder.defineMacro("__thumb__"); 5466 if (supportsThumb2()) 5467 Builder.defineMacro("__thumb2__"); 5468 } 5469 5470 // ACLE 6.4.9 32-bit SIMD instructions 5471 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5472 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5473 5474 // ACLE 6.4.10 Hardware Integer Divide 5475 if (((HWDiv & HWDivThumb) && isThumb()) || 5476 ((HWDiv & HWDivARM) && !isThumb())) { 5477 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5478 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5479 } 5480 5481 // Note, this is always on in gcc, even though it doesn't make sense. 5482 Builder.defineMacro("__APCS_32__"); 5483 5484 if (FPUModeIsVFP((FPUMode) FPU)) { 5485 Builder.defineMacro("__VFP_FP__"); 5486 if (FPU & VFP2FPU) 5487 Builder.defineMacro("__ARM_VFPV2__"); 5488 if (FPU & VFP3FPU) 5489 Builder.defineMacro("__ARM_VFPV3__"); 5490 if (FPU & VFP4FPU) 5491 Builder.defineMacro("__ARM_VFPV4__"); 5492 if (FPU & FPARMV8) 5493 Builder.defineMacro("__ARM_FPV5__"); 5494 } 5495 5496 // This only gets set when Neon instructions are actually available, unlike 5497 // the VFP define, hence the soft float and arch check. This is subtly 5498 // different from gcc, we follow the intent which was that it should be set 5499 // when Neon instructions are actually available. 5500 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5501 Builder.defineMacro("__ARM_NEON", "1"); 5502 Builder.defineMacro("__ARM_NEON__"); 5503 // current AArch32 NEON implementations do not support double-precision 5504 // floating-point even when it is present in VFP. 5505 Builder.defineMacro("__ARM_NEON_FP", 5506 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5507 } 5508 5509 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5510 Opts.ShortWChar ? "2" : "4"); 5511 5512 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5513 Opts.ShortEnums ? "1" : "4"); 5514 5515 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5516 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5517 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5518 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5519 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5520 } 5521 5522 // ACLE 6.4.7 DSP instructions 5523 if (DSP) { 5524 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5525 } 5526 5527 // ACLE 6.4.8 Saturation instructions 5528 bool SAT = false; 5529 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5530 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5531 SAT = true; 5532 } 5533 5534 // ACLE 6.4.6 Q (saturation) flag 5535 if (DSP || SAT) 5536 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5537 5538 if (Opts.UnsafeFPMath) 5539 Builder.defineMacro("__ARM_FP_FAST", "1"); 5540 5541 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5542 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5543 } 5544 5545 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5546 return llvm::makeArrayRef(BuiltinInfo, 5547 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5548 } 5549 bool isCLZForZeroUndef() const override { return false; } 5550 BuiltinVaListKind getBuiltinVaListKind() const override { 5551 return IsAAPCS 5552 ? AAPCSABIBuiltinVaList 5553 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5554 : TargetInfo::VoidPtrBuiltinVaList); 5555 } 5556 ArrayRef<const char *> getGCCRegNames() const override; 5557 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5558 bool validateAsmConstraint(const char *&Name, 5559 TargetInfo::ConstraintInfo &Info) const override { 5560 switch (*Name) { 5561 default: break; 5562 case 'l': // r0-r7 5563 case 'h': // r8-r15 5564 case 't': // VFP Floating point register single precision 5565 case 'w': // VFP Floating point register double precision 5566 Info.setAllowsRegister(); 5567 return true; 5568 case 'I': 5569 case 'J': 5570 case 'K': 5571 case 'L': 5572 case 'M': 5573 // FIXME 5574 return true; 5575 case 'Q': // A memory address that is a single base register. 5576 Info.setAllowsMemory(); 5577 return true; 5578 case 'U': // a memory reference... 5579 switch (Name[1]) { 5580 case 'q': // ...ARMV4 ldrsb 5581 case 'v': // ...VFP load/store (reg+constant offset) 5582 case 'y': // ...iWMMXt load/store 5583 case 't': // address valid for load/store opaque types wider 5584 // than 128-bits 5585 case 'n': // valid address for Neon doubleword vector load/store 5586 case 'm': // valid address for Neon element and structure load/store 5587 case 's': // valid address for non-offset loads/stores of quad-word 5588 // values in four ARM registers 5589 Info.setAllowsMemory(); 5590 Name++; 5591 return true; 5592 } 5593 } 5594 return false; 5595 } 5596 std::string convertConstraint(const char *&Constraint) const override { 5597 std::string R; 5598 switch (*Constraint) { 5599 case 'U': // Two-character constraint; add "^" hint for later parsing. 5600 R = std::string("^") + std::string(Constraint, 2); 5601 Constraint++; 5602 break; 5603 case 'p': // 'p' should be translated to 'r' by default. 5604 R = std::string("r"); 5605 break; 5606 default: 5607 return std::string(1, *Constraint); 5608 } 5609 return R; 5610 } 5611 bool 5612 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5613 std::string &SuggestedModifier) const override { 5614 bool isOutput = (Constraint[0] == '='); 5615 bool isInOut = (Constraint[0] == '+'); 5616 5617 // Strip off constraint modifiers. 5618 while (Constraint[0] == '=' || 5619 Constraint[0] == '+' || 5620 Constraint[0] == '&') 5621 Constraint = Constraint.substr(1); 5622 5623 switch (Constraint[0]) { 5624 default: break; 5625 case 'r': { 5626 switch (Modifier) { 5627 default: 5628 return (isInOut || isOutput || Size <= 64); 5629 case 'q': 5630 // A register of size 32 cannot fit a vector type. 5631 return false; 5632 } 5633 } 5634 } 5635 5636 return true; 5637 } 5638 const char *getClobbers() const override { 5639 // FIXME: Is this really right? 5640 return ""; 5641 } 5642 5643 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5644 switch (CC) { 5645 case CC_AAPCS: 5646 case CC_AAPCS_VFP: 5647 case CC_Swift: 5648 return CCCR_OK; 5649 default: 5650 return CCCR_Warning; 5651 } 5652 } 5653 5654 int getEHDataRegisterNumber(unsigned RegNo) const override { 5655 if (RegNo == 0) return 0; 5656 if (RegNo == 1) return 1; 5657 return -1; 5658 } 5659 5660 bool hasSjLjLowering() const override { 5661 return true; 5662 } 5663 }; 5664 5665 bool ARMTargetInfo::setFPMath(StringRef Name) { 5666 if (Name == "neon") { 5667 FPMath = FP_Neon; 5668 return true; 5669 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5670 Name == "vfp4") { 5671 FPMath = FP_VFP; 5672 return true; 5673 } 5674 return false; 5675 } 5676 5677 const char * const ARMTargetInfo::GCCRegNames[] = { 5678 // Integer registers 5679 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5680 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5681 5682 // Float registers 5683 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5684 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5685 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5686 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5687 5688 // Double registers 5689 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5690 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5691 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5692 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5693 5694 // Quad registers 5695 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5696 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5697 }; 5698 5699 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5700 return llvm::makeArrayRef(GCCRegNames); 5701 } 5702 5703 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5704 { { "a1" }, "r0" }, 5705 { { "a2" }, "r1" }, 5706 { { "a3" }, "r2" }, 5707 { { "a4" }, "r3" }, 5708 { { "v1" }, "r4" }, 5709 { { "v2" }, "r5" }, 5710 { { "v3" }, "r6" }, 5711 { { "v4" }, "r7" }, 5712 { { "v5" }, "r8" }, 5713 { { "v6", "rfp" }, "r9" }, 5714 { { "sl" }, "r10" }, 5715 { { "fp" }, "r11" }, 5716 { { "ip" }, "r12" }, 5717 { { "r13" }, "sp" }, 5718 { { "r14" }, "lr" }, 5719 { { "r15" }, "pc" }, 5720 // The S, D and Q registers overlap, but aren't really aliases; we 5721 // don't want to substitute one of these for a different-sized one. 5722 }; 5723 5724 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5725 return llvm::makeArrayRef(GCCRegAliases); 5726 } 5727 5728 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5729 #define BUILTIN(ID, TYPE, ATTRS) \ 5730 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5731 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5732 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5733 #include "clang/Basic/BuiltinsNEON.def" 5734 5735 #define BUILTIN(ID, TYPE, ATTRS) \ 5736 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5737 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5738 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5739 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5740 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5741 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5742 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5743 #include "clang/Basic/BuiltinsARM.def" 5744 }; 5745 5746 class ARMleTargetInfo : public ARMTargetInfo { 5747 public: 5748 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5749 : ARMTargetInfo(Triple, Opts) {} 5750 void getTargetDefines(const LangOptions &Opts, 5751 MacroBuilder &Builder) const override { 5752 Builder.defineMacro("__ARMEL__"); 5753 ARMTargetInfo::getTargetDefines(Opts, Builder); 5754 } 5755 }; 5756 5757 class ARMbeTargetInfo : public ARMTargetInfo { 5758 public: 5759 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5760 : ARMTargetInfo(Triple, Opts) {} 5761 void getTargetDefines(const LangOptions &Opts, 5762 MacroBuilder &Builder) const override { 5763 Builder.defineMacro("__ARMEB__"); 5764 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5765 ARMTargetInfo::getTargetDefines(Opts, Builder); 5766 } 5767 }; 5768 5769 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5770 const llvm::Triple Triple; 5771 public: 5772 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5773 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5774 WCharType = UnsignedShort; 5775 SizeType = UnsignedInt; 5776 } 5777 void getVisualStudioDefines(const LangOptions &Opts, 5778 MacroBuilder &Builder) const { 5779 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5780 5781 // FIXME: this is invalid for WindowsCE 5782 Builder.defineMacro("_M_ARM_NT", "1"); 5783 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5784 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5785 5786 assert((Triple.getArch() == llvm::Triple::arm || 5787 Triple.getArch() == llvm::Triple::thumb) && 5788 "invalid architecture for Windows ARM target info"); 5789 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5790 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5791 5792 // TODO map the complete set of values 5793 // 31: VFPv3 40: VFPv4 5794 Builder.defineMacro("_M_ARM_FP", "31"); 5795 } 5796 BuiltinVaListKind getBuiltinVaListKind() const override { 5797 return TargetInfo::CharPtrBuiltinVaList; 5798 } 5799 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5800 switch (CC) { 5801 case CC_X86StdCall: 5802 case CC_X86ThisCall: 5803 case CC_X86FastCall: 5804 case CC_X86VectorCall: 5805 return CCCR_Ignore; 5806 case CC_C: 5807 return CCCR_OK; 5808 default: 5809 return CCCR_Warning; 5810 } 5811 } 5812 }; 5813 5814 // Windows ARM + Itanium C++ ABI Target 5815 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5816 public: 5817 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5818 const TargetOptions &Opts) 5819 : WindowsARMTargetInfo(Triple, Opts) { 5820 TheCXXABI.set(TargetCXXABI::GenericARM); 5821 } 5822 5823 void getTargetDefines(const LangOptions &Opts, 5824 MacroBuilder &Builder) const override { 5825 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5826 5827 if (Opts.MSVCCompat) 5828 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5829 } 5830 }; 5831 5832 // Windows ARM, MS (C++) ABI 5833 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5834 public: 5835 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5836 const TargetOptions &Opts) 5837 : WindowsARMTargetInfo(Triple, Opts) { 5838 TheCXXABI.set(TargetCXXABI::Microsoft); 5839 } 5840 5841 void getTargetDefines(const LangOptions &Opts, 5842 MacroBuilder &Builder) const override { 5843 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5844 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5845 } 5846 }; 5847 5848 // ARM MinGW target 5849 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5850 public: 5851 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5852 : WindowsARMTargetInfo(Triple, Opts) { 5853 TheCXXABI.set(TargetCXXABI::GenericARM); 5854 } 5855 5856 void getTargetDefines(const LangOptions &Opts, 5857 MacroBuilder &Builder) const override { 5858 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5859 DefineStd(Builder, "WIN32", Opts); 5860 DefineStd(Builder, "WINNT", Opts); 5861 Builder.defineMacro("_ARM_"); 5862 addMinGWDefines(Opts, Builder); 5863 } 5864 }; 5865 5866 // ARM Cygwin target 5867 class CygwinARMTargetInfo : public ARMleTargetInfo { 5868 public: 5869 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5870 : ARMleTargetInfo(Triple, Opts) { 5871 TLSSupported = false; 5872 WCharType = UnsignedShort; 5873 DoubleAlign = LongLongAlign = 64; 5874 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5875 } 5876 void getTargetDefines(const LangOptions &Opts, 5877 MacroBuilder &Builder) const override { 5878 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5879 Builder.defineMacro("_ARM_"); 5880 Builder.defineMacro("__CYGWIN__"); 5881 Builder.defineMacro("__CYGWIN32__"); 5882 DefineStd(Builder, "unix", Opts); 5883 if (Opts.CPlusPlus) 5884 Builder.defineMacro("_GNU_SOURCE"); 5885 } 5886 }; 5887 5888 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5889 protected: 5890 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5891 MacroBuilder &Builder) const override { 5892 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5893 } 5894 5895 public: 5896 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5897 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5898 HasAlignMac68kSupport = true; 5899 // iOS always has 64-bit atomic instructions. 5900 // FIXME: This should be based off of the target features in 5901 // ARMleTargetInfo. 5902 MaxAtomicInlineWidth = 64; 5903 5904 if (Triple.isWatchABI()) { 5905 // Darwin on iOS uses a variant of the ARM C++ ABI. 5906 TheCXXABI.set(TargetCXXABI::WatchOS); 5907 5908 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5909 // size_t is long, it's a bit weird for it to be int. 5910 PtrDiffType = SignedLong; 5911 5912 // BOOL should be a real boolean on the new ABI 5913 UseSignedCharForObjCBool = false; 5914 } else 5915 TheCXXABI.set(TargetCXXABI::iOS); 5916 } 5917 }; 5918 5919 class AArch64TargetInfo : public TargetInfo { 5920 virtual void setDataLayout() = 0; 5921 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5922 static const char *const GCCRegNames[]; 5923 5924 enum FPUModeEnum { 5925 FPUMode, 5926 NeonMode 5927 }; 5928 5929 unsigned FPU; 5930 unsigned CRC; 5931 unsigned Crypto; 5932 unsigned Unaligned; 5933 unsigned V8_1A; 5934 5935 static const Builtin::Info BuiltinInfo[]; 5936 5937 std::string ABI; 5938 5939 public: 5940 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5941 : TargetInfo(Triple), ABI("aapcs") { 5942 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5943 WCharType = SignedInt; 5944 5945 // NetBSD apparently prefers consistency across ARM targets to consistency 5946 // across 64-bit targets. 5947 Int64Type = SignedLongLong; 5948 IntMaxType = SignedLongLong; 5949 } else { 5950 WCharType = UnsignedInt; 5951 Int64Type = SignedLong; 5952 IntMaxType = SignedLong; 5953 } 5954 5955 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5956 MaxVectorAlign = 128; 5957 MaxAtomicInlineWidth = 128; 5958 MaxAtomicPromoteWidth = 128; 5959 5960 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5961 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 5962 5963 // {} in inline assembly are neon specifiers, not assembly variant 5964 // specifiers. 5965 NoAsmVariants = true; 5966 5967 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5968 // contributes to the alignment of the containing aggregate in the same way 5969 // a plain (non bit-field) member of that type would, without exception for 5970 // zero-sized or anonymous bit-fields." 5971 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5972 UseZeroLengthBitfieldAlignment = true; 5973 5974 // AArch64 targets default to using the ARM C++ ABI. 5975 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5976 5977 if (Triple.getOS() == llvm::Triple::Linux || 5978 Triple.getOS() == llvm::Triple::UnknownOS) 5979 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5980 } 5981 5982 StringRef getABI() const override { return ABI; } 5983 bool setABI(const std::string &Name) override { 5984 if (Name != "aapcs" && Name != "darwinpcs") 5985 return false; 5986 5987 ABI = Name; 5988 return true; 5989 } 5990 5991 bool setCPU(const std::string &Name) override { 5992 return Name == "generic" || 5993 llvm::AArch64::parseCPUArch(Name) != 5994 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 5995 } 5996 5997 void getTargetDefines(const LangOptions &Opts, 5998 MacroBuilder &Builder) const override { 5999 // Target identification. 6000 Builder.defineMacro("__aarch64__"); 6001 6002 // Target properties. 6003 Builder.defineMacro("_LP64"); 6004 Builder.defineMacro("__LP64__"); 6005 6006 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6007 Builder.defineMacro("__ARM_ACLE", "200"); 6008 Builder.defineMacro("__ARM_ARCH", "8"); 6009 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6010 6011 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6012 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6013 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6014 6015 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6016 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6017 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6018 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6019 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6020 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6021 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6022 6023 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6024 6025 // 0xe implies support for half, single and double precision operations. 6026 Builder.defineMacro("__ARM_FP", "0xE"); 6027 6028 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6029 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6030 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6031 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6032 6033 if (Opts.UnsafeFPMath) 6034 Builder.defineMacro("__ARM_FP_FAST", "1"); 6035 6036 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6037 6038 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6039 Opts.ShortEnums ? "1" : "4"); 6040 6041 if (FPU == NeonMode) { 6042 Builder.defineMacro("__ARM_NEON", "1"); 6043 // 64-bit NEON supports half, single and double precision operations. 6044 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6045 } 6046 6047 if (CRC) 6048 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6049 6050 if (Crypto) 6051 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6052 6053 if (Unaligned) 6054 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6055 6056 if (V8_1A) 6057 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6058 6059 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6060 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6061 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6062 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6063 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6064 } 6065 6066 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6067 return llvm::makeArrayRef(BuiltinInfo, 6068 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6069 } 6070 6071 bool hasFeature(StringRef Feature) const override { 6072 return Feature == "aarch64" || 6073 Feature == "arm64" || 6074 Feature == "arm" || 6075 (Feature == "neon" && FPU == NeonMode); 6076 } 6077 6078 bool handleTargetFeatures(std::vector<std::string> &Features, 6079 DiagnosticsEngine &Diags) override { 6080 FPU = FPUMode; 6081 CRC = 0; 6082 Crypto = 0; 6083 Unaligned = 1; 6084 V8_1A = 0; 6085 6086 for (const auto &Feature : Features) { 6087 if (Feature == "+neon") 6088 FPU = NeonMode; 6089 if (Feature == "+crc") 6090 CRC = 1; 6091 if (Feature == "+crypto") 6092 Crypto = 1; 6093 if (Feature == "+strict-align") 6094 Unaligned = 0; 6095 if (Feature == "+v8.1a") 6096 V8_1A = 1; 6097 } 6098 6099 setDataLayout(); 6100 6101 return true; 6102 } 6103 6104 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6105 switch (CC) { 6106 case CC_C: 6107 case CC_Swift: 6108 case CC_PreserveMost: 6109 case CC_PreserveAll: 6110 return CCCR_OK; 6111 default: 6112 return CCCR_Warning; 6113 } 6114 } 6115 6116 bool isCLZForZeroUndef() const override { return false; } 6117 6118 BuiltinVaListKind getBuiltinVaListKind() const override { 6119 return TargetInfo::AArch64ABIBuiltinVaList; 6120 } 6121 6122 ArrayRef<const char *> getGCCRegNames() const override; 6123 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6124 6125 bool validateAsmConstraint(const char *&Name, 6126 TargetInfo::ConstraintInfo &Info) const override { 6127 switch (*Name) { 6128 default: 6129 return false; 6130 case 'w': // Floating point and SIMD registers (V0-V31) 6131 Info.setAllowsRegister(); 6132 return true; 6133 case 'I': // Constant that can be used with an ADD instruction 6134 case 'J': // Constant that can be used with a SUB instruction 6135 case 'K': // Constant that can be used with a 32-bit logical instruction 6136 case 'L': // Constant that can be used with a 64-bit logical instruction 6137 case 'M': // Constant that can be used as a 32-bit MOV immediate 6138 case 'N': // Constant that can be used as a 64-bit MOV immediate 6139 case 'Y': // Floating point constant zero 6140 case 'Z': // Integer constant zero 6141 return true; 6142 case 'Q': // A memory reference with base register and no offset 6143 Info.setAllowsMemory(); 6144 return true; 6145 case 'S': // A symbolic address 6146 Info.setAllowsRegister(); 6147 return true; 6148 case 'U': 6149 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6150 // Utf: A memory address suitable for ldp/stp in TF mode. 6151 // Usa: An absolute symbolic address. 6152 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6153 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6154 case 'z': // Zero register, wzr or xzr 6155 Info.setAllowsRegister(); 6156 return true; 6157 case 'x': // Floating point and SIMD registers (V0-V15) 6158 Info.setAllowsRegister(); 6159 return true; 6160 } 6161 return false; 6162 } 6163 6164 bool 6165 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6166 std::string &SuggestedModifier) const override { 6167 // Strip off constraint modifiers. 6168 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6169 Constraint = Constraint.substr(1); 6170 6171 switch (Constraint[0]) { 6172 default: 6173 return true; 6174 case 'z': 6175 case 'r': { 6176 switch (Modifier) { 6177 case 'x': 6178 case 'w': 6179 // For now assume that the person knows what they're 6180 // doing with the modifier. 6181 return true; 6182 default: 6183 // By default an 'r' constraint will be in the 'x' 6184 // registers. 6185 if (Size == 64) 6186 return true; 6187 6188 SuggestedModifier = "w"; 6189 return false; 6190 } 6191 } 6192 } 6193 } 6194 6195 const char *getClobbers() const override { return ""; } 6196 6197 int getEHDataRegisterNumber(unsigned RegNo) const override { 6198 if (RegNo == 0) 6199 return 0; 6200 if (RegNo == 1) 6201 return 1; 6202 return -1; 6203 } 6204 }; 6205 6206 const char *const AArch64TargetInfo::GCCRegNames[] = { 6207 // 32-bit Integer registers 6208 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6209 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6210 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6211 6212 // 64-bit Integer registers 6213 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6214 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6215 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6216 6217 // 32-bit floating point regsisters 6218 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6219 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6220 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6221 6222 // 64-bit floating point regsisters 6223 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6224 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6225 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6226 6227 // Vector registers 6228 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6229 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6230 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6231 }; 6232 6233 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6234 return llvm::makeArrayRef(GCCRegNames); 6235 } 6236 6237 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6238 { { "w31" }, "wsp" }, 6239 { { "x29" }, "fp" }, 6240 { { "x30" }, "lr" }, 6241 { { "x31" }, "sp" }, 6242 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6243 // don't want to substitute one of these for a different-sized one. 6244 }; 6245 6246 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6247 return llvm::makeArrayRef(GCCRegAliases); 6248 } 6249 6250 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6251 #define BUILTIN(ID, TYPE, ATTRS) \ 6252 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6253 #include "clang/Basic/BuiltinsNEON.def" 6254 6255 #define BUILTIN(ID, TYPE, ATTRS) \ 6256 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6257 #include "clang/Basic/BuiltinsAArch64.def" 6258 }; 6259 6260 class AArch64leTargetInfo : public AArch64TargetInfo { 6261 void setDataLayout() override { 6262 if (getTriple().isOSBinFormatMachO()) 6263 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6264 else 6265 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6266 } 6267 6268 public: 6269 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6270 : AArch64TargetInfo(Triple, Opts) { 6271 } 6272 void getTargetDefines(const LangOptions &Opts, 6273 MacroBuilder &Builder) const override { 6274 Builder.defineMacro("__AARCH64EL__"); 6275 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6276 } 6277 }; 6278 6279 class AArch64beTargetInfo : public AArch64TargetInfo { 6280 void setDataLayout() override { 6281 assert(!getTriple().isOSBinFormatMachO()); 6282 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6283 } 6284 6285 public: 6286 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6287 : AArch64TargetInfo(Triple, Opts) {} 6288 void getTargetDefines(const LangOptions &Opts, 6289 MacroBuilder &Builder) const override { 6290 Builder.defineMacro("__AARCH64EB__"); 6291 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6292 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6293 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6294 } 6295 }; 6296 6297 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6298 protected: 6299 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6300 MacroBuilder &Builder) const override { 6301 Builder.defineMacro("__AARCH64_SIMD__"); 6302 Builder.defineMacro("__ARM64_ARCH_8__"); 6303 Builder.defineMacro("__ARM_NEON__"); 6304 Builder.defineMacro("__LITTLE_ENDIAN__"); 6305 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6306 Builder.defineMacro("__arm64", "1"); 6307 Builder.defineMacro("__arm64__", "1"); 6308 6309 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6310 } 6311 6312 public: 6313 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6314 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6315 Int64Type = SignedLongLong; 6316 WCharType = SignedInt; 6317 UseSignedCharForObjCBool = false; 6318 6319 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6320 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6321 6322 TheCXXABI.set(TargetCXXABI::iOS64); 6323 } 6324 6325 BuiltinVaListKind getBuiltinVaListKind() const override { 6326 return TargetInfo::CharPtrBuiltinVaList; 6327 } 6328 }; 6329 6330 // Hexagon abstract base class 6331 class HexagonTargetInfo : public TargetInfo { 6332 static const Builtin::Info BuiltinInfo[]; 6333 static const char * const GCCRegNames[]; 6334 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6335 std::string CPU; 6336 bool HasHVX, HasHVXDouble; 6337 bool UseLongCalls; 6338 6339 public: 6340 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6341 : TargetInfo(Triple) { 6342 // Specify the vector alignment explicitly. For v512x1, the calculated 6343 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6344 // the required minimum of 64 bytes. 6345 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6346 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6347 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6348 SizeType = UnsignedInt; 6349 PtrDiffType = SignedInt; 6350 IntPtrType = SignedInt; 6351 6352 // {} in inline assembly are packet specifiers, not assembly variant 6353 // specifiers. 6354 NoAsmVariants = true; 6355 6356 LargeArrayMinWidth = 64; 6357 LargeArrayAlign = 64; 6358 UseBitFieldTypeAlignment = true; 6359 ZeroLengthBitfieldBoundary = 32; 6360 HasHVX = HasHVXDouble = false; 6361 UseLongCalls = false; 6362 } 6363 6364 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6365 return llvm::makeArrayRef(BuiltinInfo, 6366 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6367 } 6368 6369 bool validateAsmConstraint(const char *&Name, 6370 TargetInfo::ConstraintInfo &Info) const override { 6371 switch (*Name) { 6372 case 'v': 6373 case 'q': 6374 if (HasHVX) { 6375 Info.setAllowsRegister(); 6376 return true; 6377 } 6378 break; 6379 case 's': 6380 // Relocatable constant. 6381 return true; 6382 } 6383 return false; 6384 } 6385 6386 void getTargetDefines(const LangOptions &Opts, 6387 MacroBuilder &Builder) const override; 6388 6389 bool isCLZForZeroUndef() const override { return false; } 6390 6391 bool hasFeature(StringRef Feature) const override { 6392 return llvm::StringSwitch<bool>(Feature) 6393 .Case("hexagon", true) 6394 .Case("hvx", HasHVX) 6395 .Case("hvx-double", HasHVXDouble) 6396 .Case("long-calls", UseLongCalls) 6397 .Default(false); 6398 } 6399 6400 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6401 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6402 const override; 6403 6404 bool handleTargetFeatures(std::vector<std::string> &Features, 6405 DiagnosticsEngine &Diags) override; 6406 6407 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6408 bool Enabled) const override; 6409 6410 BuiltinVaListKind getBuiltinVaListKind() const override { 6411 return TargetInfo::CharPtrBuiltinVaList; 6412 } 6413 ArrayRef<const char *> getGCCRegNames() const override; 6414 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6415 const char *getClobbers() const override { 6416 return ""; 6417 } 6418 6419 static const char *getHexagonCPUSuffix(StringRef Name) { 6420 return llvm::StringSwitch<const char*>(Name) 6421 .Case("hexagonv4", "4") 6422 .Case("hexagonv5", "5") 6423 .Case("hexagonv55", "55") 6424 .Case("hexagonv60", "60") 6425 .Default(nullptr); 6426 } 6427 6428 bool setCPU(const std::string &Name) override { 6429 if (!getHexagonCPUSuffix(Name)) 6430 return false; 6431 CPU = Name; 6432 return true; 6433 } 6434 6435 int getEHDataRegisterNumber(unsigned RegNo) const override { 6436 return RegNo < 2 ? RegNo : -1; 6437 } 6438 }; 6439 6440 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6441 MacroBuilder &Builder) const { 6442 Builder.defineMacro("__qdsp6__", "1"); 6443 Builder.defineMacro("__hexagon__", "1"); 6444 6445 if (CPU == "hexagonv4") { 6446 Builder.defineMacro("__HEXAGON_V4__"); 6447 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6448 if (Opts.HexagonQdsp6Compat) { 6449 Builder.defineMacro("__QDSP6_V4__"); 6450 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6451 } 6452 } else if (CPU == "hexagonv5") { 6453 Builder.defineMacro("__HEXAGON_V5__"); 6454 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6455 if(Opts.HexagonQdsp6Compat) { 6456 Builder.defineMacro("__QDSP6_V5__"); 6457 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6458 } 6459 } else if (CPU == "hexagonv55") { 6460 Builder.defineMacro("__HEXAGON_V55__"); 6461 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6462 Builder.defineMacro("__QDSP6_V55__"); 6463 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6464 } else if (CPU == "hexagonv60") { 6465 Builder.defineMacro("__HEXAGON_V60__"); 6466 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6467 Builder.defineMacro("__QDSP6_V60__"); 6468 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6469 } 6470 6471 if (hasFeature("hvx")) { 6472 Builder.defineMacro("__HVX__"); 6473 if (hasFeature("hvx-double")) 6474 Builder.defineMacro("__HVXDBL__"); 6475 } 6476 } 6477 6478 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6479 DiagnosticsEngine &Diags, StringRef CPU, 6480 const std::vector<std::string> &FeaturesVec) const { 6481 // Default for v60: -hvx, -hvx-double. 6482 Features["hvx"] = false; 6483 Features["hvx-double"] = false; 6484 Features["long-calls"] = false; 6485 6486 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6487 } 6488 6489 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6490 DiagnosticsEngine &Diags) { 6491 for (auto &F : Features) { 6492 if (F == "+hvx") 6493 HasHVX = true; 6494 else if (F == "-hvx") 6495 HasHVX = HasHVXDouble = false; 6496 else if (F == "+hvx-double") 6497 HasHVX = HasHVXDouble = true; 6498 else if (F == "-hvx-double") 6499 HasHVXDouble = false; 6500 6501 if (F == "+long-calls") 6502 UseLongCalls = true; 6503 else if (F == "-long-calls") 6504 UseLongCalls = false; 6505 } 6506 return true; 6507 } 6508 6509 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6510 StringRef Name, bool Enabled) const { 6511 if (Enabled) { 6512 if (Name == "hvx-double") 6513 Features["hvx"] = true; 6514 } else { 6515 if (Name == "hvx") 6516 Features["hvx-double"] = false; 6517 } 6518 Features[Name] = Enabled; 6519 } 6520 6521 const char *const HexagonTargetInfo::GCCRegNames[] = { 6522 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6523 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6524 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6525 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6526 "p0", "p1", "p2", "p3", 6527 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6528 }; 6529 6530 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6531 return llvm::makeArrayRef(GCCRegNames); 6532 } 6533 6534 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6535 { { "sp" }, "r29" }, 6536 { { "fp" }, "r30" }, 6537 { { "lr" }, "r31" }, 6538 }; 6539 6540 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6541 return llvm::makeArrayRef(GCCRegAliases); 6542 } 6543 6544 6545 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6546 #define BUILTIN(ID, TYPE, ATTRS) \ 6547 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6548 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6549 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6550 #include "clang/Basic/BuiltinsHexagon.def" 6551 }; 6552 6553 class LanaiTargetInfo : public TargetInfo { 6554 // Class for Lanai (32-bit). 6555 // The CPU profiles supported by the Lanai backend 6556 enum CPUKind { 6557 CK_NONE, 6558 CK_V11, 6559 } CPU; 6560 6561 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6562 static const char *const GCCRegNames[]; 6563 6564 public: 6565 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6566 : TargetInfo(Triple) { 6567 // Description string has to be kept in sync with backend. 6568 resetDataLayout("E" // Big endian 6569 "-m:e" // ELF name manging 6570 "-p:32:32" // 32 bit pointers, 32 bit aligned 6571 "-i64:64" // 64 bit integers, 64 bit aligned 6572 "-a:0:32" // 32 bit alignment of objects of aggregate type 6573 "-n32" // 32 bit native integer width 6574 "-S64" // 64 bit natural stack alignment 6575 ); 6576 6577 // Setting RegParmMax equal to what mregparm was set to in the old 6578 // toolchain 6579 RegParmMax = 4; 6580 6581 // Set the default CPU to V11 6582 CPU = CK_V11; 6583 6584 // Temporary approach to make everything at least word-aligned and allow for 6585 // safely casting between pointers with different alignment requirements. 6586 // TODO: Remove this when there are no more cast align warnings on the 6587 // firmware. 6588 MinGlobalAlign = 32; 6589 } 6590 6591 void getTargetDefines(const LangOptions &Opts, 6592 MacroBuilder &Builder) const override { 6593 // Define __lanai__ when building for target lanai. 6594 Builder.defineMacro("__lanai__"); 6595 6596 // Set define for the CPU specified. 6597 switch (CPU) { 6598 case CK_V11: 6599 Builder.defineMacro("__LANAI_V11__"); 6600 break; 6601 case CK_NONE: 6602 llvm_unreachable("Unhandled target CPU"); 6603 } 6604 } 6605 6606 bool setCPU(const std::string &Name) override { 6607 CPU = llvm::StringSwitch<CPUKind>(Name) 6608 .Case("v11", CK_V11) 6609 .Default(CK_NONE); 6610 6611 return CPU != CK_NONE; 6612 } 6613 6614 bool hasFeature(StringRef Feature) const override { 6615 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6616 } 6617 6618 ArrayRef<const char *> getGCCRegNames() const override; 6619 6620 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6621 6622 BuiltinVaListKind getBuiltinVaListKind() const override { 6623 return TargetInfo::VoidPtrBuiltinVaList; 6624 } 6625 6626 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6627 6628 bool validateAsmConstraint(const char *&Name, 6629 TargetInfo::ConstraintInfo &info) const override { 6630 return false; 6631 } 6632 6633 const char *getClobbers() const override { return ""; } 6634 }; 6635 6636 const char *const LanaiTargetInfo::GCCRegNames[] = { 6637 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6638 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6639 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6640 6641 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6642 return llvm::makeArrayRef(GCCRegNames); 6643 } 6644 6645 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6646 {{"pc"}, "r2"}, 6647 {{"sp"}, "r4"}, 6648 {{"fp"}, "r5"}, 6649 {{"rv"}, "r8"}, 6650 {{"rr1"}, "r10"}, 6651 {{"rr2"}, "r11"}, 6652 {{"rca"}, "r15"}, 6653 }; 6654 6655 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6656 return llvm::makeArrayRef(GCCRegAliases); 6657 } 6658 6659 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6660 class SparcTargetInfo : public TargetInfo { 6661 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6662 static const char * const GCCRegNames[]; 6663 bool SoftFloat; 6664 public: 6665 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6666 : TargetInfo(Triple), SoftFloat(false) {} 6667 6668 int getEHDataRegisterNumber(unsigned RegNo) const override { 6669 if (RegNo == 0) return 24; 6670 if (RegNo == 1) return 25; 6671 return -1; 6672 } 6673 6674 bool handleTargetFeatures(std::vector<std::string> &Features, 6675 DiagnosticsEngine &Diags) override { 6676 // Check if software floating point is enabled 6677 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6678 if (Feature != Features.end()) { 6679 SoftFloat = true; 6680 } 6681 return true; 6682 } 6683 void getTargetDefines(const LangOptions &Opts, 6684 MacroBuilder &Builder) const override { 6685 DefineStd(Builder, "sparc", Opts); 6686 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6687 6688 if (SoftFloat) 6689 Builder.defineMacro("SOFT_FLOAT", "1"); 6690 } 6691 6692 bool hasFeature(StringRef Feature) const override { 6693 return llvm::StringSwitch<bool>(Feature) 6694 .Case("softfloat", SoftFloat) 6695 .Case("sparc", true) 6696 .Default(false); 6697 } 6698 6699 bool hasSjLjLowering() const override { 6700 return true; 6701 } 6702 6703 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6704 // FIXME: Implement! 6705 return None; 6706 } 6707 BuiltinVaListKind getBuiltinVaListKind() const override { 6708 return TargetInfo::VoidPtrBuiltinVaList; 6709 } 6710 ArrayRef<const char *> getGCCRegNames() const override; 6711 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6712 bool validateAsmConstraint(const char *&Name, 6713 TargetInfo::ConstraintInfo &info) const override { 6714 // FIXME: Implement! 6715 switch (*Name) { 6716 case 'I': // Signed 13-bit constant 6717 case 'J': // Zero 6718 case 'K': // 32-bit constant with the low 12 bits clear 6719 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6720 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6721 case 'N': // Same as 'K' but zext (required for SIMode) 6722 case 'O': // The constant 4096 6723 return true; 6724 } 6725 return false; 6726 } 6727 const char *getClobbers() const override { 6728 // FIXME: Implement! 6729 return ""; 6730 } 6731 6732 // No Sparc V7 for now, the backend doesn't support it anyway. 6733 enum CPUKind { 6734 CK_GENERIC, 6735 CK_V8, 6736 CK_SUPERSPARC, 6737 CK_SPARCLITE, 6738 CK_F934, 6739 CK_HYPERSPARC, 6740 CK_SPARCLITE86X, 6741 CK_SPARCLET, 6742 CK_TSC701, 6743 CK_V9, 6744 CK_ULTRASPARC, 6745 CK_ULTRASPARC3, 6746 CK_NIAGARA, 6747 CK_NIAGARA2, 6748 CK_NIAGARA3, 6749 CK_NIAGARA4, 6750 CK_MYRIAD2100, 6751 CK_MYRIAD2150, 6752 CK_MYRIAD2450, 6753 CK_LEON2, 6754 CK_LEON2_AT697E, 6755 CK_LEON2_AT697F, 6756 CK_LEON3, 6757 CK_LEON3_UT699, 6758 CK_LEON3_GR712RC, 6759 CK_LEON4, 6760 CK_LEON4_GR740 6761 } CPU = CK_GENERIC; 6762 6763 enum CPUGeneration { 6764 CG_V8, 6765 CG_V9, 6766 }; 6767 6768 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6769 switch (Kind) { 6770 case CK_GENERIC: 6771 case CK_V8: 6772 case CK_SUPERSPARC: 6773 case CK_SPARCLITE: 6774 case CK_F934: 6775 case CK_HYPERSPARC: 6776 case CK_SPARCLITE86X: 6777 case CK_SPARCLET: 6778 case CK_TSC701: 6779 case CK_MYRIAD2100: 6780 case CK_MYRIAD2150: 6781 case CK_MYRIAD2450: 6782 case CK_LEON2: 6783 case CK_LEON2_AT697E: 6784 case CK_LEON2_AT697F: 6785 case CK_LEON3: 6786 case CK_LEON3_UT699: 6787 case CK_LEON3_GR712RC: 6788 case CK_LEON4: 6789 case CK_LEON4_GR740: 6790 return CG_V8; 6791 case CK_V9: 6792 case CK_ULTRASPARC: 6793 case CK_ULTRASPARC3: 6794 case CK_NIAGARA: 6795 case CK_NIAGARA2: 6796 case CK_NIAGARA3: 6797 case CK_NIAGARA4: 6798 return CG_V9; 6799 } 6800 llvm_unreachable("Unexpected CPU kind"); 6801 } 6802 6803 CPUKind getCPUKind(StringRef Name) const { 6804 return llvm::StringSwitch<CPUKind>(Name) 6805 .Case("v8", CK_V8) 6806 .Case("supersparc", CK_SUPERSPARC) 6807 .Case("sparclite", CK_SPARCLITE) 6808 .Case("f934", CK_F934) 6809 .Case("hypersparc", CK_HYPERSPARC) 6810 .Case("sparclite86x", CK_SPARCLITE86X) 6811 .Case("sparclet", CK_SPARCLET) 6812 .Case("tsc701", CK_TSC701) 6813 .Case("v9", CK_V9) 6814 .Case("ultrasparc", CK_ULTRASPARC) 6815 .Case("ultrasparc3", CK_ULTRASPARC3) 6816 .Case("niagara", CK_NIAGARA) 6817 .Case("niagara2", CK_NIAGARA2) 6818 .Case("niagara3", CK_NIAGARA3) 6819 .Case("niagara4", CK_NIAGARA4) 6820 .Case("ma2100", CK_MYRIAD2100) 6821 .Case("ma2150", CK_MYRIAD2150) 6822 .Case("ma2450", CK_MYRIAD2450) 6823 // FIXME: the myriad2[.n] spellings are obsolete, 6824 // but a grace period is needed to allow updating dependent builds. 6825 .Case("myriad2", CK_MYRIAD2100) 6826 .Case("myriad2.1", CK_MYRIAD2100) 6827 .Case("myriad2.2", CK_MYRIAD2150) 6828 .Case("leon2", CK_LEON2) 6829 .Case("at697e", CK_LEON2_AT697E) 6830 .Case("at697f", CK_LEON2_AT697F) 6831 .Case("leon3", CK_LEON3) 6832 .Case("ut699", CK_LEON3_UT699) 6833 .Case("gr712rc", CK_LEON3_GR712RC) 6834 .Case("leon4", CK_LEON4) 6835 .Case("gr740", CK_LEON4_GR740) 6836 .Default(CK_GENERIC); 6837 } 6838 6839 bool setCPU(const std::string &Name) override { 6840 CPU = getCPUKind(Name); 6841 return CPU != CK_GENERIC; 6842 } 6843 }; 6844 6845 const char * const SparcTargetInfo::GCCRegNames[] = { 6846 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6847 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6848 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6849 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6850 }; 6851 6852 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6853 return llvm::makeArrayRef(GCCRegNames); 6854 } 6855 6856 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6857 { { "g0" }, "r0" }, 6858 { { "g1" }, "r1" }, 6859 { { "g2" }, "r2" }, 6860 { { "g3" }, "r3" }, 6861 { { "g4" }, "r4" }, 6862 { { "g5" }, "r5" }, 6863 { { "g6" }, "r6" }, 6864 { { "g7" }, "r7" }, 6865 { { "o0" }, "r8" }, 6866 { { "o1" }, "r9" }, 6867 { { "o2" }, "r10" }, 6868 { { "o3" }, "r11" }, 6869 { { "o4" }, "r12" }, 6870 { { "o5" }, "r13" }, 6871 { { "o6", "sp" }, "r14" }, 6872 { { "o7" }, "r15" }, 6873 { { "l0" }, "r16" }, 6874 { { "l1" }, "r17" }, 6875 { { "l2" }, "r18" }, 6876 { { "l3" }, "r19" }, 6877 { { "l4" }, "r20" }, 6878 { { "l5" }, "r21" }, 6879 { { "l6" }, "r22" }, 6880 { { "l7" }, "r23" }, 6881 { { "i0" }, "r24" }, 6882 { { "i1" }, "r25" }, 6883 { { "i2" }, "r26" }, 6884 { { "i3" }, "r27" }, 6885 { { "i4" }, "r28" }, 6886 { { "i5" }, "r29" }, 6887 { { "i6", "fp" }, "r30" }, 6888 { { "i7" }, "r31" }, 6889 }; 6890 6891 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6892 return llvm::makeArrayRef(GCCRegAliases); 6893 } 6894 6895 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6896 class SparcV8TargetInfo : public SparcTargetInfo { 6897 public: 6898 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6899 : SparcTargetInfo(Triple, Opts) { 6900 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6901 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6902 switch (getTriple().getOS()) { 6903 default: 6904 SizeType = UnsignedInt; 6905 IntPtrType = SignedInt; 6906 PtrDiffType = SignedInt; 6907 break; 6908 case llvm::Triple::NetBSD: 6909 case llvm::Triple::OpenBSD: 6910 SizeType = UnsignedLong; 6911 IntPtrType = SignedLong; 6912 PtrDiffType = SignedLong; 6913 break; 6914 } 6915 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 6916 // on up to 64 bits. 6917 MaxAtomicPromoteWidth = 64; 6918 MaxAtomicInlineWidth = 32; 6919 } 6920 6921 void getTargetDefines(const LangOptions &Opts, 6922 MacroBuilder &Builder) const override { 6923 SparcTargetInfo::getTargetDefines(Opts, Builder); 6924 switch (getCPUGeneration(CPU)) { 6925 case CG_V8: 6926 Builder.defineMacro("__sparcv8"); 6927 if (getTriple().getOS() != llvm::Triple::Solaris) 6928 Builder.defineMacro("__sparcv8__"); 6929 break; 6930 case CG_V9: 6931 Builder.defineMacro("__sparcv9"); 6932 if (getTriple().getOS() != llvm::Triple::Solaris) { 6933 Builder.defineMacro("__sparcv9__"); 6934 Builder.defineMacro("__sparc_v9__"); 6935 } 6936 break; 6937 } 6938 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6939 std::string MyriadArchValue, Myriad2Value; 6940 Builder.defineMacro("__sparc_v8__"); 6941 Builder.defineMacro("__leon__"); 6942 switch (CPU) { 6943 case CK_MYRIAD2150: 6944 MyriadArchValue = "__ma2150"; 6945 Myriad2Value = "2"; 6946 break; 6947 case CK_MYRIAD2450: 6948 MyriadArchValue = "__ma2450"; 6949 Myriad2Value = "2"; 6950 break; 6951 default: 6952 MyriadArchValue = "__ma2100"; 6953 Myriad2Value = "1"; 6954 break; 6955 } 6956 Builder.defineMacro(MyriadArchValue, "1"); 6957 Builder.defineMacro(MyriadArchValue+"__", "1"); 6958 Builder.defineMacro("__myriad2__", Myriad2Value); 6959 Builder.defineMacro("__myriad2", Myriad2Value); 6960 } 6961 } 6962 6963 bool hasSjLjLowering() const override { 6964 return true; 6965 } 6966 }; 6967 6968 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6969 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6970 public: 6971 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6972 : SparcV8TargetInfo(Triple, Opts) { 6973 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6974 } 6975 }; 6976 6977 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6978 class SparcV9TargetInfo : public SparcTargetInfo { 6979 public: 6980 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6981 : SparcTargetInfo(Triple, Opts) { 6982 // FIXME: Support Sparc quad-precision long double? 6983 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6984 // This is an LP64 platform. 6985 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6986 6987 // OpenBSD uses long long for int64_t and intmax_t. 6988 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6989 IntMaxType = SignedLongLong; 6990 else 6991 IntMaxType = SignedLong; 6992 Int64Type = IntMaxType; 6993 6994 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6995 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6996 LongDoubleWidth = 128; 6997 LongDoubleAlign = 128; 6998 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6999 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7000 } 7001 7002 void getTargetDefines(const LangOptions &Opts, 7003 MacroBuilder &Builder) const override { 7004 SparcTargetInfo::getTargetDefines(Opts, Builder); 7005 Builder.defineMacro("__sparcv9"); 7006 Builder.defineMacro("__arch64__"); 7007 // Solaris doesn't need these variants, but the BSDs do. 7008 if (getTriple().getOS() != llvm::Triple::Solaris) { 7009 Builder.defineMacro("__sparc64__"); 7010 Builder.defineMacro("__sparc_v9__"); 7011 Builder.defineMacro("__sparcv9__"); 7012 } 7013 } 7014 7015 bool setCPU(const std::string &Name) override { 7016 if (!SparcTargetInfo::setCPU(Name)) 7017 return false; 7018 return getCPUGeneration(CPU) == CG_V9; 7019 } 7020 }; 7021 7022 class SystemZTargetInfo : public TargetInfo { 7023 static const Builtin::Info BuiltinInfo[]; 7024 static const char *const GCCRegNames[]; 7025 std::string CPU; 7026 bool HasTransactionalExecution; 7027 bool HasVector; 7028 7029 public: 7030 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7031 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 7032 HasVector(false) { 7033 IntMaxType = SignedLong; 7034 Int64Type = SignedLong; 7035 TLSSupported = true; 7036 IntWidth = IntAlign = 32; 7037 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7038 PointerWidth = PointerAlign = 64; 7039 LongDoubleWidth = 128; 7040 LongDoubleAlign = 64; 7041 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7042 DefaultAlignForAttributeAligned = 64; 7043 MinGlobalAlign = 16; 7044 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7045 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7046 } 7047 void getTargetDefines(const LangOptions &Opts, 7048 MacroBuilder &Builder) const override { 7049 Builder.defineMacro("__s390__"); 7050 Builder.defineMacro("__s390x__"); 7051 Builder.defineMacro("__zarch__"); 7052 Builder.defineMacro("__LONG_DOUBLE_128__"); 7053 7054 const std::string ISARev = llvm::StringSwitch<std::string>(CPU) 7055 .Cases("arch8", "z10", "8") 7056 .Cases("arch9", "z196", "9") 7057 .Cases("arch10", "zEC12", "10") 7058 .Cases("arch11", "z13", "11") 7059 .Default(""); 7060 if (!ISARev.empty()) 7061 Builder.defineMacro("__ARCH__", ISARev); 7062 7063 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7064 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7065 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7066 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7067 7068 if (HasTransactionalExecution) 7069 Builder.defineMacro("__HTM__"); 7070 if (HasVector) 7071 Builder.defineMacro("__VX__"); 7072 if (Opts.ZVector) 7073 Builder.defineMacro("__VEC__", "10301"); 7074 } 7075 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7076 return llvm::makeArrayRef(BuiltinInfo, 7077 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7078 } 7079 7080 ArrayRef<const char *> getGCCRegNames() const override; 7081 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7082 // No aliases. 7083 return None; 7084 } 7085 bool validateAsmConstraint(const char *&Name, 7086 TargetInfo::ConstraintInfo &info) const override; 7087 const char *getClobbers() const override { 7088 // FIXME: Is this really right? 7089 return ""; 7090 } 7091 BuiltinVaListKind getBuiltinVaListKind() const override { 7092 return TargetInfo::SystemZBuiltinVaList; 7093 } 7094 bool setCPU(const std::string &Name) override { 7095 CPU = Name; 7096 bool CPUKnown = llvm::StringSwitch<bool>(Name) 7097 .Case("z10", true) 7098 .Case("arch8", true) 7099 .Case("z196", true) 7100 .Case("arch9", true) 7101 .Case("zEC12", true) 7102 .Case("arch10", true) 7103 .Case("z13", true) 7104 .Case("arch11", true) 7105 .Default(false); 7106 7107 return CPUKnown; 7108 } 7109 bool 7110 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7111 StringRef CPU, 7112 const std::vector<std::string> &FeaturesVec) const override { 7113 if (CPU == "zEC12" || CPU == "arch10") 7114 Features["transactional-execution"] = true; 7115 if (CPU == "z13" || CPU == "arch11") { 7116 Features["transactional-execution"] = true; 7117 Features["vector"] = true; 7118 } 7119 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7120 } 7121 7122 bool handleTargetFeatures(std::vector<std::string> &Features, 7123 DiagnosticsEngine &Diags) override { 7124 HasTransactionalExecution = false; 7125 for (const auto &Feature : Features) { 7126 if (Feature == "+transactional-execution") 7127 HasTransactionalExecution = true; 7128 else if (Feature == "+vector") 7129 HasVector = true; 7130 } 7131 // If we use the vector ABI, vector types are 64-bit aligned. 7132 if (HasVector) { 7133 MaxVectorAlign = 64; 7134 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7135 "-v128:64-a:8:16-n32:64"); 7136 } 7137 return true; 7138 } 7139 7140 bool hasFeature(StringRef Feature) const override { 7141 return llvm::StringSwitch<bool>(Feature) 7142 .Case("systemz", true) 7143 .Case("htm", HasTransactionalExecution) 7144 .Case("vx", HasVector) 7145 .Default(false); 7146 } 7147 7148 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7149 switch (CC) { 7150 case CC_C: 7151 case CC_Swift: 7152 return CCCR_OK; 7153 default: 7154 return CCCR_Warning; 7155 } 7156 } 7157 7158 StringRef getABI() const override { 7159 if (HasVector) 7160 return "vector"; 7161 return ""; 7162 } 7163 7164 bool useFloat128ManglingForLongDouble() const override { 7165 return true; 7166 } 7167 }; 7168 7169 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7170 #define BUILTIN(ID, TYPE, ATTRS) \ 7171 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7172 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7173 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7174 #include "clang/Basic/BuiltinsSystemZ.def" 7175 }; 7176 7177 const char *const SystemZTargetInfo::GCCRegNames[] = { 7178 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7179 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7180 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7181 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7182 }; 7183 7184 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7185 return llvm::makeArrayRef(GCCRegNames); 7186 } 7187 7188 bool SystemZTargetInfo:: 7189 validateAsmConstraint(const char *&Name, 7190 TargetInfo::ConstraintInfo &Info) const { 7191 switch (*Name) { 7192 default: 7193 return false; 7194 7195 case 'a': // Address register 7196 case 'd': // Data register (equivalent to 'r') 7197 case 'f': // Floating-point register 7198 Info.setAllowsRegister(); 7199 return true; 7200 7201 case 'I': // Unsigned 8-bit constant 7202 case 'J': // Unsigned 12-bit constant 7203 case 'K': // Signed 16-bit constant 7204 case 'L': // Signed 20-bit displacement (on all targets we support) 7205 case 'M': // 0x7fffffff 7206 return true; 7207 7208 case 'Q': // Memory with base and unsigned 12-bit displacement 7209 case 'R': // Likewise, plus an index 7210 case 'S': // Memory with base and signed 20-bit displacement 7211 case 'T': // Likewise, plus an index 7212 Info.setAllowsMemory(); 7213 return true; 7214 } 7215 } 7216 7217 class MSP430TargetInfo : public TargetInfo { 7218 static const char *const GCCRegNames[]; 7219 7220 public: 7221 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7222 : TargetInfo(Triple) { 7223 TLSSupported = false; 7224 IntWidth = 16; 7225 IntAlign = 16; 7226 LongWidth = 32; 7227 LongLongWidth = 64; 7228 LongAlign = LongLongAlign = 16; 7229 PointerWidth = 16; 7230 PointerAlign = 16; 7231 SuitableAlign = 16; 7232 SizeType = UnsignedInt; 7233 IntMaxType = SignedLongLong; 7234 IntPtrType = SignedInt; 7235 PtrDiffType = SignedInt; 7236 SigAtomicType = SignedLong; 7237 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7238 } 7239 void getTargetDefines(const LangOptions &Opts, 7240 MacroBuilder &Builder) const override { 7241 Builder.defineMacro("MSP430"); 7242 Builder.defineMacro("__MSP430__"); 7243 // FIXME: defines for different 'flavours' of MCU 7244 } 7245 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7246 // FIXME: Implement. 7247 return None; 7248 } 7249 bool hasFeature(StringRef Feature) const override { 7250 return Feature == "msp430"; 7251 } 7252 ArrayRef<const char *> getGCCRegNames() const override; 7253 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7254 // No aliases. 7255 return None; 7256 } 7257 bool validateAsmConstraint(const char *&Name, 7258 TargetInfo::ConstraintInfo &info) const override { 7259 // FIXME: implement 7260 switch (*Name) { 7261 case 'K': // the constant 1 7262 case 'L': // constant -1^20 .. 1^19 7263 case 'M': // constant 1-4: 7264 return true; 7265 } 7266 // No target constraints for now. 7267 return false; 7268 } 7269 const char *getClobbers() const override { 7270 // FIXME: Is this really right? 7271 return ""; 7272 } 7273 BuiltinVaListKind getBuiltinVaListKind() const override { 7274 // FIXME: implement 7275 return TargetInfo::CharPtrBuiltinVaList; 7276 } 7277 }; 7278 7279 const char *const MSP430TargetInfo::GCCRegNames[] = { 7280 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7281 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7282 7283 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7284 return llvm::makeArrayRef(GCCRegNames); 7285 } 7286 7287 // LLVM and Clang cannot be used directly to output native binaries for 7288 // target, but is used to compile C code to llvm bitcode with correct 7289 // type and alignment information. 7290 // 7291 // TCE uses the llvm bitcode as input and uses it for generating customized 7292 // target processor and program binary. TCE co-design environment is 7293 // publicly available in http://tce.cs.tut.fi 7294 7295 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7296 3, // opencl_global 7297 4, // opencl_local 7298 5, // opencl_constant 7299 // FIXME: generic has to be added to the target 7300 0, // opencl_generic 7301 0, // cuda_device 7302 0, // cuda_constant 7303 0 // cuda_shared 7304 }; 7305 7306 class TCETargetInfo : public TargetInfo { 7307 public: 7308 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7309 : TargetInfo(Triple) { 7310 TLSSupported = false; 7311 IntWidth = 32; 7312 LongWidth = LongLongWidth = 32; 7313 PointerWidth = 32; 7314 IntAlign = 32; 7315 LongAlign = LongLongAlign = 32; 7316 PointerAlign = 32; 7317 SuitableAlign = 32; 7318 SizeType = UnsignedInt; 7319 IntMaxType = SignedLong; 7320 IntPtrType = SignedInt; 7321 PtrDiffType = SignedInt; 7322 FloatWidth = 32; 7323 FloatAlign = 32; 7324 DoubleWidth = 32; 7325 DoubleAlign = 32; 7326 LongDoubleWidth = 32; 7327 LongDoubleAlign = 32; 7328 FloatFormat = &llvm::APFloat::IEEEsingle(); 7329 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7330 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7331 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7332 "i16:16:32-i32:32:32-i64:32:32-" 7333 "f32:32:32-f64:32:32-v64:32:32-" 7334 "v128:32:32-v256:32:32-v512:32:32-" 7335 "v1024:32:32-a0:0:32-n32"); 7336 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7337 UseAddrSpaceMapMangling = true; 7338 } 7339 7340 void getTargetDefines(const LangOptions &Opts, 7341 MacroBuilder &Builder) const override { 7342 DefineStd(Builder, "tce", Opts); 7343 Builder.defineMacro("__TCE__"); 7344 Builder.defineMacro("__TCE_V1__"); 7345 } 7346 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7347 7348 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7349 const char *getClobbers() const override { return ""; } 7350 BuiltinVaListKind getBuiltinVaListKind() const override { 7351 return TargetInfo::VoidPtrBuiltinVaList; 7352 } 7353 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7354 bool validateAsmConstraint(const char *&Name, 7355 TargetInfo::ConstraintInfo &info) const override { 7356 return true; 7357 } 7358 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7359 return None; 7360 } 7361 }; 7362 7363 class TCELETargetInfo : public TCETargetInfo { 7364 public: 7365 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7366 : TCETargetInfo(Triple, Opts) { 7367 BigEndian = false; 7368 7369 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7370 "i16:16:32-i32:32:32-i64:32:32-" 7371 "f32:32:32-f64:32:32-v64:32:32-" 7372 "v128:32:32-v256:32:32-v512:32:32-" 7373 "v1024:32:32-a0:0:32-n32"); 7374 7375 } 7376 7377 virtual void getTargetDefines(const LangOptions &Opts, 7378 MacroBuilder &Builder) const { 7379 DefineStd(Builder, "tcele", Opts); 7380 Builder.defineMacro("__TCE__"); 7381 Builder.defineMacro("__TCE_V1__"); 7382 Builder.defineMacro("__TCELE__"); 7383 Builder.defineMacro("__TCELE_V1__"); 7384 } 7385 7386 }; 7387 7388 class BPFTargetInfo : public TargetInfo { 7389 public: 7390 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7391 : TargetInfo(Triple) { 7392 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7393 SizeType = UnsignedLong; 7394 PtrDiffType = SignedLong; 7395 IntPtrType = SignedLong; 7396 IntMaxType = SignedLong; 7397 Int64Type = SignedLong; 7398 RegParmMax = 5; 7399 if (Triple.getArch() == llvm::Triple::bpfeb) { 7400 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7401 } else { 7402 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7403 } 7404 MaxAtomicPromoteWidth = 64; 7405 MaxAtomicInlineWidth = 64; 7406 TLSSupported = false; 7407 } 7408 void getTargetDefines(const LangOptions &Opts, 7409 MacroBuilder &Builder) const override { 7410 DefineStd(Builder, "bpf", Opts); 7411 Builder.defineMacro("__BPF__"); 7412 } 7413 bool hasFeature(StringRef Feature) const override { 7414 return Feature == "bpf"; 7415 } 7416 7417 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7418 const char *getClobbers() const override { 7419 return ""; 7420 } 7421 BuiltinVaListKind getBuiltinVaListKind() const override { 7422 return TargetInfo::VoidPtrBuiltinVaList; 7423 } 7424 ArrayRef<const char *> getGCCRegNames() const override { 7425 return None; 7426 } 7427 bool validateAsmConstraint(const char *&Name, 7428 TargetInfo::ConstraintInfo &info) const override { 7429 return true; 7430 } 7431 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7432 return None; 7433 } 7434 }; 7435 7436 class MipsTargetInfo : public TargetInfo { 7437 void setDataLayout() { 7438 StringRef Layout; 7439 7440 if (ABI == "o32") 7441 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7442 else if (ABI == "n32") 7443 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7444 else if (ABI == "n64") 7445 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7446 else 7447 llvm_unreachable("Invalid ABI"); 7448 7449 if (BigEndian) 7450 resetDataLayout(("E-" + Layout).str()); 7451 else 7452 resetDataLayout(("e-" + Layout).str()); 7453 } 7454 7455 7456 static const Builtin::Info BuiltinInfo[]; 7457 std::string CPU; 7458 bool IsMips16; 7459 bool IsMicromips; 7460 bool IsNan2008; 7461 bool IsSingleFloat; 7462 enum MipsFloatABI { 7463 HardFloat, SoftFloat 7464 } FloatABI; 7465 enum DspRevEnum { 7466 NoDSP, DSP1, DSP2 7467 } DspRev; 7468 bool HasMSA; 7469 7470 protected: 7471 bool HasFP64; 7472 std::string ABI; 7473 7474 public: 7475 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7476 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7477 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7478 DspRev(NoDSP), HasMSA(false), HasFP64(false) { 7479 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7480 7481 setABI((getTriple().getArch() == llvm::Triple::mips || 7482 getTriple().getArch() == llvm::Triple::mipsel) 7483 ? "o32" 7484 : "n64"); 7485 7486 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7487 } 7488 7489 bool isNaN2008Default() const { 7490 return CPU == "mips32r6" || CPU == "mips64r6"; 7491 } 7492 7493 bool isFP64Default() const { 7494 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7495 } 7496 7497 bool isNan2008() const override { 7498 return IsNan2008; 7499 } 7500 7501 bool processorSupportsGPR64() const { 7502 return llvm::StringSwitch<bool>(CPU) 7503 .Case("mips3", true) 7504 .Case("mips4", true) 7505 .Case("mips5", true) 7506 .Case("mips64", true) 7507 .Case("mips64r2", true) 7508 .Case("mips64r3", true) 7509 .Case("mips64r5", true) 7510 .Case("mips64r6", true) 7511 .Case("octeon", true) 7512 .Default(false); 7513 return false; 7514 } 7515 7516 StringRef getABI() const override { return ABI; } 7517 bool setABI(const std::string &Name) override { 7518 if (Name == "o32") { 7519 setO32ABITypes(); 7520 ABI = Name; 7521 return true; 7522 } 7523 7524 if (Name == "n32") { 7525 setN32ABITypes(); 7526 ABI = Name; 7527 return true; 7528 } 7529 if (Name == "n64") { 7530 setN64ABITypes(); 7531 ABI = Name; 7532 return true; 7533 } 7534 return false; 7535 } 7536 7537 void setO32ABITypes() { 7538 Int64Type = SignedLongLong; 7539 IntMaxType = Int64Type; 7540 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7541 LongDoubleWidth = LongDoubleAlign = 64; 7542 LongWidth = LongAlign = 32; 7543 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7544 PointerWidth = PointerAlign = 32; 7545 PtrDiffType = SignedInt; 7546 SizeType = UnsignedInt; 7547 SuitableAlign = 64; 7548 } 7549 7550 void setN32N64ABITypes() { 7551 LongDoubleWidth = LongDoubleAlign = 128; 7552 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7553 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7554 LongDoubleWidth = LongDoubleAlign = 64; 7555 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7556 } 7557 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7558 SuitableAlign = 128; 7559 } 7560 7561 void setN64ABITypes() { 7562 setN32N64ABITypes(); 7563 Int64Type = SignedLong; 7564 IntMaxType = Int64Type; 7565 LongWidth = LongAlign = 64; 7566 PointerWidth = PointerAlign = 64; 7567 PtrDiffType = SignedLong; 7568 SizeType = UnsignedLong; 7569 } 7570 7571 void setN32ABITypes() { 7572 setN32N64ABITypes(); 7573 Int64Type = SignedLongLong; 7574 IntMaxType = Int64Type; 7575 LongWidth = LongAlign = 32; 7576 PointerWidth = PointerAlign = 32; 7577 PtrDiffType = SignedInt; 7578 SizeType = UnsignedInt; 7579 } 7580 7581 bool setCPU(const std::string &Name) override { 7582 CPU = Name; 7583 return llvm::StringSwitch<bool>(Name) 7584 .Case("mips1", true) 7585 .Case("mips2", true) 7586 .Case("mips3", true) 7587 .Case("mips4", true) 7588 .Case("mips5", true) 7589 .Case("mips32", true) 7590 .Case("mips32r2", true) 7591 .Case("mips32r3", true) 7592 .Case("mips32r5", true) 7593 .Case("mips32r6", true) 7594 .Case("mips64", true) 7595 .Case("mips64r2", true) 7596 .Case("mips64r3", true) 7597 .Case("mips64r5", true) 7598 .Case("mips64r6", true) 7599 .Case("octeon", true) 7600 .Case("p5600", true) 7601 .Default(false); 7602 } 7603 const std::string& getCPU() const { return CPU; } 7604 bool 7605 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7606 StringRef CPU, 7607 const std::vector<std::string> &FeaturesVec) const override { 7608 if (CPU.empty()) 7609 CPU = getCPU(); 7610 if (CPU == "octeon") 7611 Features["mips64r2"] = Features["cnmips"] = true; 7612 else 7613 Features[CPU] = true; 7614 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7615 } 7616 7617 void getTargetDefines(const LangOptions &Opts, 7618 MacroBuilder &Builder) const override { 7619 if (BigEndian) { 7620 DefineStd(Builder, "MIPSEB", Opts); 7621 Builder.defineMacro("_MIPSEB"); 7622 } else { 7623 DefineStd(Builder, "MIPSEL", Opts); 7624 Builder.defineMacro("_MIPSEL"); 7625 } 7626 7627 Builder.defineMacro("__mips__"); 7628 Builder.defineMacro("_mips"); 7629 if (Opts.GNUMode) 7630 Builder.defineMacro("mips"); 7631 7632 if (ABI == "o32") { 7633 Builder.defineMacro("__mips", "32"); 7634 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7635 } else { 7636 Builder.defineMacro("__mips", "64"); 7637 Builder.defineMacro("__mips64"); 7638 Builder.defineMacro("__mips64__"); 7639 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7640 } 7641 7642 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7643 .Cases("mips32", "mips64", "1") 7644 .Cases("mips32r2", "mips64r2", "2") 7645 .Cases("mips32r3", "mips64r3", "3") 7646 .Cases("mips32r5", "mips64r5", "5") 7647 .Cases("mips32r6", "mips64r6", "6") 7648 .Default(""); 7649 if (!ISARev.empty()) 7650 Builder.defineMacro("__mips_isa_rev", ISARev); 7651 7652 if (ABI == "o32") { 7653 Builder.defineMacro("__mips_o32"); 7654 Builder.defineMacro("_ABIO32", "1"); 7655 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7656 } else if (ABI == "n32") { 7657 Builder.defineMacro("__mips_n32"); 7658 Builder.defineMacro("_ABIN32", "2"); 7659 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7660 } else if (ABI == "n64") { 7661 Builder.defineMacro("__mips_n64"); 7662 Builder.defineMacro("_ABI64", "3"); 7663 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7664 } else 7665 llvm_unreachable("Invalid ABI."); 7666 7667 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7668 7669 switch (FloatABI) { 7670 case HardFloat: 7671 Builder.defineMacro("__mips_hard_float", Twine(1)); 7672 break; 7673 case SoftFloat: 7674 Builder.defineMacro("__mips_soft_float", Twine(1)); 7675 break; 7676 } 7677 7678 if (IsSingleFloat) 7679 Builder.defineMacro("__mips_single_float", Twine(1)); 7680 7681 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7682 Builder.defineMacro("_MIPS_FPSET", 7683 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7684 7685 if (IsMips16) 7686 Builder.defineMacro("__mips16", Twine(1)); 7687 7688 if (IsMicromips) 7689 Builder.defineMacro("__mips_micromips", Twine(1)); 7690 7691 if (IsNan2008) 7692 Builder.defineMacro("__mips_nan2008", Twine(1)); 7693 7694 switch (DspRev) { 7695 default: 7696 break; 7697 case DSP1: 7698 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7699 Builder.defineMacro("__mips_dsp", Twine(1)); 7700 break; 7701 case DSP2: 7702 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7703 Builder.defineMacro("__mips_dspr2", Twine(1)); 7704 Builder.defineMacro("__mips_dsp", Twine(1)); 7705 break; 7706 } 7707 7708 if (HasMSA) 7709 Builder.defineMacro("__mips_msa", Twine(1)); 7710 7711 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7712 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7713 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7714 7715 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7716 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7717 7718 // These shouldn't be defined for MIPS-I but there's no need to check 7719 // for that since MIPS-I isn't supported. 7720 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7721 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7722 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7723 7724 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7725 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7726 // the instructions exist but using them violates the ABI since they 7727 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7728 if (ABI == "n32" || ABI == "n64") 7729 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7730 } 7731 7732 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7733 return llvm::makeArrayRef(BuiltinInfo, 7734 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7735 } 7736 bool hasFeature(StringRef Feature) const override { 7737 return llvm::StringSwitch<bool>(Feature) 7738 .Case("mips", true) 7739 .Case("fp64", HasFP64) 7740 .Default(false); 7741 } 7742 BuiltinVaListKind getBuiltinVaListKind() const override { 7743 return TargetInfo::VoidPtrBuiltinVaList; 7744 } 7745 ArrayRef<const char *> getGCCRegNames() const override { 7746 static const char *const GCCRegNames[] = { 7747 // CPU register names 7748 // Must match second column of GCCRegAliases 7749 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7750 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7751 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7752 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7753 // Floating point register names 7754 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7755 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7756 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7757 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7758 // Hi/lo and condition register names 7759 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7760 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7761 "$ac3hi","$ac3lo", 7762 // MSA register names 7763 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7764 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7765 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7766 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7767 // MSA control register names 7768 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7769 "$msarequest", "$msamap", "$msaunmap" 7770 }; 7771 return llvm::makeArrayRef(GCCRegNames); 7772 } 7773 bool validateAsmConstraint(const char *&Name, 7774 TargetInfo::ConstraintInfo &Info) const override { 7775 switch (*Name) { 7776 default: 7777 return false; 7778 case 'r': // CPU registers. 7779 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7780 case 'y': // Equivalent to "r", backward compatibility only. 7781 case 'f': // floating-point registers. 7782 case 'c': // $25 for indirect jumps 7783 case 'l': // lo register 7784 case 'x': // hilo register pair 7785 Info.setAllowsRegister(); 7786 return true; 7787 case 'I': // Signed 16-bit constant 7788 case 'J': // Integer 0 7789 case 'K': // Unsigned 16-bit constant 7790 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7791 case 'M': // Constants not loadable via lui, addiu, or ori 7792 case 'N': // Constant -1 to -65535 7793 case 'O': // A signed 15-bit constant 7794 case 'P': // A constant between 1 go 65535 7795 return true; 7796 case 'R': // An address that can be used in a non-macro load or store 7797 Info.setAllowsMemory(); 7798 return true; 7799 case 'Z': 7800 if (Name[1] == 'C') { // An address usable by ll, and sc. 7801 Info.setAllowsMemory(); 7802 Name++; // Skip over 'Z'. 7803 return true; 7804 } 7805 return false; 7806 } 7807 } 7808 7809 std::string convertConstraint(const char *&Constraint) const override { 7810 std::string R; 7811 switch (*Constraint) { 7812 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7813 if (Constraint[1] == 'C') { 7814 R = std::string("^") + std::string(Constraint, 2); 7815 Constraint++; 7816 return R; 7817 } 7818 break; 7819 } 7820 return TargetInfo::convertConstraint(Constraint); 7821 } 7822 7823 const char *getClobbers() const override { 7824 // In GCC, $1 is not widely used in generated code (it's used only in a few 7825 // specific situations), so there is no real need for users to add it to 7826 // the clobbers list if they want to use it in their inline assembly code. 7827 // 7828 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7829 // code generation, so using it in inline assembly without adding it to the 7830 // clobbers list can cause conflicts between the inline assembly code and 7831 // the surrounding generated code. 7832 // 7833 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7834 // operands, which will conflict with the ".set at" assembler option (which 7835 // we use only for inline assembly, in order to maintain compatibility with 7836 // GCC) and will also conflict with the user's usage of $1. 7837 // 7838 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7839 // register for generated code is to automatically clobber $1 for all inline 7840 // assembly code. 7841 // 7842 // FIXME: We should automatically clobber $1 only for inline assembly code 7843 // which actually uses it. This would allow LLVM to use $1 for inline 7844 // assembly operands if the user's assembly code doesn't use it. 7845 return "~{$1}"; 7846 } 7847 7848 bool handleTargetFeatures(std::vector<std::string> &Features, 7849 DiagnosticsEngine &Diags) override { 7850 IsMips16 = false; 7851 IsMicromips = false; 7852 IsNan2008 = isNaN2008Default(); 7853 IsSingleFloat = false; 7854 FloatABI = HardFloat; 7855 DspRev = NoDSP; 7856 HasFP64 = isFP64Default(); 7857 7858 for (const auto &Feature : Features) { 7859 if (Feature == "+single-float") 7860 IsSingleFloat = true; 7861 else if (Feature == "+soft-float") 7862 FloatABI = SoftFloat; 7863 else if (Feature == "+mips16") 7864 IsMips16 = true; 7865 else if (Feature == "+micromips") 7866 IsMicromips = true; 7867 else if (Feature == "+dsp") 7868 DspRev = std::max(DspRev, DSP1); 7869 else if (Feature == "+dspr2") 7870 DspRev = std::max(DspRev, DSP2); 7871 else if (Feature == "+msa") 7872 HasMSA = true; 7873 else if (Feature == "+fp64") 7874 HasFP64 = true; 7875 else if (Feature == "-fp64") 7876 HasFP64 = false; 7877 else if (Feature == "+nan2008") 7878 IsNan2008 = true; 7879 else if (Feature == "-nan2008") 7880 IsNan2008 = false; 7881 } 7882 7883 setDataLayout(); 7884 7885 return true; 7886 } 7887 7888 int getEHDataRegisterNumber(unsigned RegNo) const override { 7889 if (RegNo == 0) return 4; 7890 if (RegNo == 1) return 5; 7891 return -1; 7892 } 7893 7894 bool isCLZForZeroUndef() const override { return false; } 7895 7896 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7897 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7898 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7899 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7900 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7901 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7902 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7903 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7904 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7905 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7906 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7907 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7908 {{"ra"}, "$31"}}; 7909 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7910 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7911 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7912 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7913 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7914 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7915 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7916 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7917 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7918 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7919 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7920 {{"ra"}, "$31"}}; 7921 if (ABI == "o32") 7922 return llvm::makeArrayRef(O32RegAliases); 7923 return llvm::makeArrayRef(NewABIRegAliases); 7924 } 7925 7926 bool hasInt128Type() const override { 7927 return ABI == "n32" || ABI == "n64"; 7928 } 7929 7930 bool validateTarget(DiagnosticsEngine &Diags) const override { 7931 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7932 // this yet. It's better to fail here than on the backend assertion. 7933 if (processorSupportsGPR64() && ABI == "o32") { 7934 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7935 return false; 7936 } 7937 7938 // 64-bit ABI's require 64-bit CPU's. 7939 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 7940 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7941 return false; 7942 } 7943 7944 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 7945 // can't handle this yet. It's better to fail here than on the 7946 // backend assertion. 7947 if ((getTriple().getArch() == llvm::Triple::mips64 || 7948 getTriple().getArch() == llvm::Triple::mips64el) && 7949 ABI == "o32") { 7950 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7951 << ABI << getTriple().str(); 7952 return false; 7953 } 7954 7955 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 7956 // can't handle this yet. It's better to fail here than on the 7957 // backend assertion. 7958 if ((getTriple().getArch() == llvm::Triple::mips || 7959 getTriple().getArch() == llvm::Triple::mipsel) && 7960 (ABI == "n32" || ABI == "n64")) { 7961 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7962 << ABI << getTriple().str(); 7963 return false; 7964 } 7965 7966 return true; 7967 } 7968 }; 7969 7970 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7971 #define BUILTIN(ID, TYPE, ATTRS) \ 7972 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7973 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7974 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7975 #include "clang/Basic/BuiltinsMips.def" 7976 }; 7977 7978 class PNaClTargetInfo : public TargetInfo { 7979 public: 7980 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7981 : TargetInfo(Triple) { 7982 this->LongAlign = 32; 7983 this->LongWidth = 32; 7984 this->PointerAlign = 32; 7985 this->PointerWidth = 32; 7986 this->IntMaxType = TargetInfo::SignedLongLong; 7987 this->Int64Type = TargetInfo::SignedLongLong; 7988 this->DoubleAlign = 64; 7989 this->LongDoubleWidth = 64; 7990 this->LongDoubleAlign = 64; 7991 this->SizeType = TargetInfo::UnsignedInt; 7992 this->PtrDiffType = TargetInfo::SignedInt; 7993 this->IntPtrType = TargetInfo::SignedInt; 7994 this->RegParmMax = 0; // Disallow regparm 7995 } 7996 7997 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7998 Builder.defineMacro("__le32__"); 7999 Builder.defineMacro("__pnacl__"); 8000 } 8001 void getTargetDefines(const LangOptions &Opts, 8002 MacroBuilder &Builder) const override { 8003 getArchDefines(Opts, Builder); 8004 } 8005 bool hasFeature(StringRef Feature) const override { 8006 return Feature == "pnacl"; 8007 } 8008 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8009 BuiltinVaListKind getBuiltinVaListKind() const override { 8010 return TargetInfo::PNaClABIBuiltinVaList; 8011 } 8012 ArrayRef<const char *> getGCCRegNames() const override; 8013 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8014 bool validateAsmConstraint(const char *&Name, 8015 TargetInfo::ConstraintInfo &Info) const override { 8016 return false; 8017 } 8018 8019 const char *getClobbers() const override { 8020 return ""; 8021 } 8022 }; 8023 8024 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8025 return None; 8026 } 8027 8028 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8029 return None; 8030 } 8031 8032 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8033 class NaClMips32TargetInfo : public MipsTargetInfo { 8034 public: 8035 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8036 : MipsTargetInfo(Triple, Opts) {} 8037 8038 BuiltinVaListKind getBuiltinVaListKind() const override { 8039 return TargetInfo::PNaClABIBuiltinVaList; 8040 } 8041 }; 8042 8043 class Le64TargetInfo : public TargetInfo { 8044 static const Builtin::Info BuiltinInfo[]; 8045 8046 public: 8047 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8048 : TargetInfo(Triple) { 8049 NoAsmVariants = true; 8050 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8051 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8052 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8053 } 8054 8055 void getTargetDefines(const LangOptions &Opts, 8056 MacroBuilder &Builder) const override { 8057 DefineStd(Builder, "unix", Opts); 8058 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8059 Builder.defineMacro("__ELF__"); 8060 } 8061 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8062 return llvm::makeArrayRef(BuiltinInfo, 8063 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8064 } 8065 BuiltinVaListKind getBuiltinVaListKind() const override { 8066 return TargetInfo::PNaClABIBuiltinVaList; 8067 } 8068 const char *getClobbers() const override { return ""; } 8069 ArrayRef<const char *> getGCCRegNames() const override { 8070 return None; 8071 } 8072 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8073 return None; 8074 } 8075 bool validateAsmConstraint(const char *&Name, 8076 TargetInfo::ConstraintInfo &Info) const override { 8077 return false; 8078 } 8079 8080 bool hasProtectedVisibility() const override { return false; } 8081 }; 8082 8083 class WebAssemblyTargetInfo : public TargetInfo { 8084 static const Builtin::Info BuiltinInfo[]; 8085 8086 enum SIMDEnum { 8087 NoSIMD, 8088 SIMD128, 8089 } SIMDLevel; 8090 8091 public: 8092 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8093 : TargetInfo(T), SIMDLevel(NoSIMD) { 8094 NoAsmVariants = true; 8095 SuitableAlign = 128; 8096 LargeArrayMinWidth = 128; 8097 LargeArrayAlign = 128; 8098 SimdDefaultAlign = 128; 8099 SigAtomicType = SignedLong; 8100 LongDoubleWidth = LongDoubleAlign = 128; 8101 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8102 SizeType = UnsignedInt; 8103 PtrDiffType = SignedInt; 8104 IntPtrType = SignedInt; 8105 } 8106 8107 protected: 8108 void getTargetDefines(const LangOptions &Opts, 8109 MacroBuilder &Builder) const override { 8110 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8111 if (SIMDLevel >= SIMD128) 8112 Builder.defineMacro("__wasm_simd128__"); 8113 } 8114 8115 private: 8116 bool 8117 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8118 StringRef CPU, 8119 const std::vector<std::string> &FeaturesVec) const override { 8120 if (CPU == "bleeding-edge") 8121 Features["simd128"] = true; 8122 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8123 } 8124 bool hasFeature(StringRef Feature) const final { 8125 return llvm::StringSwitch<bool>(Feature) 8126 .Case("simd128", SIMDLevel >= SIMD128) 8127 .Default(false); 8128 } 8129 bool handleTargetFeatures(std::vector<std::string> &Features, 8130 DiagnosticsEngine &Diags) final { 8131 for (const auto &Feature : Features) { 8132 if (Feature == "+simd128") { 8133 SIMDLevel = std::max(SIMDLevel, SIMD128); 8134 continue; 8135 } 8136 if (Feature == "-simd128") { 8137 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8138 continue; 8139 } 8140 8141 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8142 << "-target-feature"; 8143 return false; 8144 } 8145 return true; 8146 } 8147 bool setCPU(const std::string &Name) final { 8148 return llvm::StringSwitch<bool>(Name) 8149 .Case("mvp", true) 8150 .Case("bleeding-edge", true) 8151 .Case("generic", true) 8152 .Default(false); 8153 } 8154 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8155 return llvm::makeArrayRef(BuiltinInfo, 8156 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8157 } 8158 BuiltinVaListKind getBuiltinVaListKind() const final { 8159 return VoidPtrBuiltinVaList; 8160 } 8161 ArrayRef<const char *> getGCCRegNames() const final { 8162 return None; 8163 } 8164 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8165 return None; 8166 } 8167 bool 8168 validateAsmConstraint(const char *&Name, 8169 TargetInfo::ConstraintInfo &Info) const final { 8170 return false; 8171 } 8172 const char *getClobbers() const final { return ""; } 8173 bool isCLZForZeroUndef() const final { return false; } 8174 bool hasInt128Type() const final { return true; } 8175 IntType getIntTypeByWidth(unsigned BitWidth, 8176 bool IsSigned) const final { 8177 // WebAssembly prefers long long for explicitly 64-bit integers. 8178 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8179 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8180 } 8181 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8182 bool IsSigned) const final { 8183 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8184 return BitWidth == 64 8185 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8186 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8187 } 8188 }; 8189 8190 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8191 #define BUILTIN(ID, TYPE, ATTRS) \ 8192 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8193 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8194 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8195 #include "clang/Basic/BuiltinsWebAssembly.def" 8196 }; 8197 8198 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8199 public: 8200 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8201 const TargetOptions &Opts) 8202 : WebAssemblyTargetInfo(T, Opts) { 8203 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8204 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8205 } 8206 8207 protected: 8208 void getTargetDefines(const LangOptions &Opts, 8209 MacroBuilder &Builder) const override { 8210 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8211 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8212 } 8213 }; 8214 8215 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8216 public: 8217 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8218 const TargetOptions &Opts) 8219 : WebAssemblyTargetInfo(T, Opts) { 8220 LongAlign = LongWidth = 64; 8221 PointerAlign = PointerWidth = 64; 8222 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8223 SizeType = UnsignedLong; 8224 PtrDiffType = SignedLong; 8225 IntPtrType = SignedLong; 8226 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8227 } 8228 8229 protected: 8230 void getTargetDefines(const LangOptions &Opts, 8231 MacroBuilder &Builder) const override { 8232 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8233 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8234 } 8235 }; 8236 8237 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8238 #define BUILTIN(ID, TYPE, ATTRS) \ 8239 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8240 #include "clang/Basic/BuiltinsLe64.def" 8241 }; 8242 8243 static const unsigned SPIRAddrSpaceMap[] = { 8244 1, // opencl_global 8245 3, // opencl_local 8246 2, // opencl_constant 8247 4, // opencl_generic 8248 0, // cuda_device 8249 0, // cuda_constant 8250 0 // cuda_shared 8251 }; 8252 class SPIRTargetInfo : public TargetInfo { 8253 public: 8254 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8255 : TargetInfo(Triple) { 8256 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8257 "SPIR target must use unknown OS"); 8258 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8259 "SPIR target must use unknown environment type"); 8260 TLSSupported = false; 8261 LongWidth = LongAlign = 64; 8262 AddrSpaceMap = &SPIRAddrSpaceMap; 8263 UseAddrSpaceMapMangling = true; 8264 // Define available target features 8265 // These must be defined in sorted order! 8266 NoAsmVariants = true; 8267 } 8268 void getTargetDefines(const LangOptions &Opts, 8269 MacroBuilder &Builder) const override { 8270 DefineStd(Builder, "SPIR", Opts); 8271 } 8272 bool hasFeature(StringRef Feature) const override { 8273 return Feature == "spir"; 8274 } 8275 8276 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8277 const char *getClobbers() const override { return ""; } 8278 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8279 bool validateAsmConstraint(const char *&Name, 8280 TargetInfo::ConstraintInfo &info) const override { 8281 return true; 8282 } 8283 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8284 return None; 8285 } 8286 BuiltinVaListKind getBuiltinVaListKind() const override { 8287 return TargetInfo::VoidPtrBuiltinVaList; 8288 } 8289 8290 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8291 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8292 : CCCR_Warning; 8293 } 8294 8295 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8296 return CC_SpirFunction; 8297 } 8298 8299 void setSupportedOpenCLOpts() override { 8300 // Assume all OpenCL extensions and optional core features are supported 8301 // for SPIR since it is a generic target. 8302 getSupportedOpenCLOpts().supportAll(); 8303 } 8304 }; 8305 8306 class SPIR32TargetInfo : public SPIRTargetInfo { 8307 public: 8308 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8309 : SPIRTargetInfo(Triple, Opts) { 8310 PointerWidth = PointerAlign = 32; 8311 SizeType = TargetInfo::UnsignedInt; 8312 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8313 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8314 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8315 } 8316 void getTargetDefines(const LangOptions &Opts, 8317 MacroBuilder &Builder) const override { 8318 DefineStd(Builder, "SPIR32", Opts); 8319 } 8320 }; 8321 8322 class SPIR64TargetInfo : public SPIRTargetInfo { 8323 public: 8324 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8325 : SPIRTargetInfo(Triple, Opts) { 8326 PointerWidth = PointerAlign = 64; 8327 SizeType = TargetInfo::UnsignedLong; 8328 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8329 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8330 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8331 } 8332 void getTargetDefines(const LangOptions &Opts, 8333 MacroBuilder &Builder) const override { 8334 DefineStd(Builder, "SPIR64", Opts); 8335 } 8336 }; 8337 8338 class XCoreTargetInfo : public TargetInfo { 8339 static const Builtin::Info BuiltinInfo[]; 8340 public: 8341 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8342 : TargetInfo(Triple) { 8343 NoAsmVariants = true; 8344 LongLongAlign = 32; 8345 SuitableAlign = 32; 8346 DoubleAlign = LongDoubleAlign = 32; 8347 SizeType = UnsignedInt; 8348 PtrDiffType = SignedInt; 8349 IntPtrType = SignedInt; 8350 WCharType = UnsignedChar; 8351 WIntType = UnsignedInt; 8352 UseZeroLengthBitfieldAlignment = true; 8353 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8354 "-f64:32-a:0:32-n32"); 8355 } 8356 void getTargetDefines(const LangOptions &Opts, 8357 MacroBuilder &Builder) const override { 8358 Builder.defineMacro("__XS1B__"); 8359 } 8360 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8361 return llvm::makeArrayRef(BuiltinInfo, 8362 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8363 } 8364 BuiltinVaListKind getBuiltinVaListKind() const override { 8365 return TargetInfo::VoidPtrBuiltinVaList; 8366 } 8367 const char *getClobbers() const override { 8368 return ""; 8369 } 8370 ArrayRef<const char *> getGCCRegNames() const override { 8371 static const char * const GCCRegNames[] = { 8372 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8373 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8374 }; 8375 return llvm::makeArrayRef(GCCRegNames); 8376 } 8377 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8378 return None; 8379 } 8380 bool validateAsmConstraint(const char *&Name, 8381 TargetInfo::ConstraintInfo &Info) const override { 8382 return false; 8383 } 8384 int getEHDataRegisterNumber(unsigned RegNo) const override { 8385 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8386 return (RegNo < 2)? RegNo : -1; 8387 } 8388 bool allowsLargerPreferedTypeAlignment() const override { 8389 return false; 8390 } 8391 }; 8392 8393 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8394 #define BUILTIN(ID, TYPE, ATTRS) \ 8395 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8396 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8397 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8398 #include "clang/Basic/BuiltinsXCore.def" 8399 }; 8400 8401 // x86_32 Android target 8402 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8403 public: 8404 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8405 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8406 SuitableAlign = 32; 8407 LongDoubleWidth = 64; 8408 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8409 } 8410 }; 8411 8412 // x86_64 Android target 8413 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8414 public: 8415 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8416 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8417 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8418 } 8419 8420 bool useFloat128ManglingForLongDouble() const override { 8421 return true; 8422 } 8423 }; 8424 8425 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8426 class RenderScript32TargetInfo : public ARMleTargetInfo { 8427 public: 8428 RenderScript32TargetInfo(const llvm::Triple &Triple, 8429 const TargetOptions &Opts) 8430 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8431 Triple.getOSName(), 8432 Triple.getEnvironmentName()), 8433 Opts) { 8434 IsRenderScriptTarget = true; 8435 LongWidth = LongAlign = 64; 8436 } 8437 void getTargetDefines(const LangOptions &Opts, 8438 MacroBuilder &Builder) const override { 8439 Builder.defineMacro("__RENDERSCRIPT__"); 8440 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8441 } 8442 }; 8443 8444 // 64-bit RenderScript is aarch64 8445 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8446 public: 8447 RenderScript64TargetInfo(const llvm::Triple &Triple, 8448 const TargetOptions &Opts) 8449 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8450 Triple.getOSName(), 8451 Triple.getEnvironmentName()), 8452 Opts) { 8453 IsRenderScriptTarget = true; 8454 } 8455 8456 void getTargetDefines(const LangOptions &Opts, 8457 MacroBuilder &Builder) const override { 8458 Builder.defineMacro("__RENDERSCRIPT__"); 8459 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8460 } 8461 }; 8462 8463 /// Information about a specific microcontroller. 8464 struct MCUInfo { 8465 const char *Name; 8466 const char *DefineName; 8467 }; 8468 8469 // This list should be kept up-to-date with AVRDevices.td in LLVM. 8470 static ArrayRef<MCUInfo> AVRMcus = { 8471 { "at90s1200", "__AVR_AT90S1200__" }, 8472 { "attiny11", "__AVR_ATtiny11__" }, 8473 { "attiny12", "__AVR_ATtiny12__" }, 8474 { "attiny15", "__AVR_ATtiny15__" }, 8475 { "attiny28", "__AVR_ATtiny28__" }, 8476 { "at90s2313", "__AVR_AT90S2313__" }, 8477 { "at90s2323", "__AVR_AT90S2323__" }, 8478 { "at90s2333", "__AVR_AT90S2333__" }, 8479 { "at90s2343", "__AVR_AT90S2343__" }, 8480 { "attiny22", "__AVR_ATtiny22__" }, 8481 { "attiny26", "__AVR_ATtiny26__" }, 8482 { "at86rf401", "__AVR_AT86RF401__" }, 8483 { "at90s4414", "__AVR_AT90S4414__" }, 8484 { "at90s4433", "__AVR_AT90S4433__" }, 8485 { "at90s4434", "__AVR_AT90S4434__" }, 8486 { "at90s8515", "__AVR_AT90S8515__" }, 8487 { "at90c8534", "__AVR_AT90c8534__" }, 8488 { "at90s8535", "__AVR_AT90S8535__" }, 8489 { "ata5272", "__AVR_ATA5272__" }, 8490 { "attiny13", "__AVR_ATtiny13__" }, 8491 { "attiny13a", "__AVR_ATtiny13A__" }, 8492 { "attiny2313", "__AVR_ATtiny2313__" }, 8493 { "attiny2313a", "__AVR_ATtiny2313A__" }, 8494 { "attiny24", "__AVR_ATtiny24__" }, 8495 { "attiny24a", "__AVR_ATtiny24A__" }, 8496 { "attiny4313", "__AVR_ATtiny4313__" }, 8497 { "attiny44", "__AVR_ATtiny44__" }, 8498 { "attiny44a", "__AVR_ATtiny44A__" }, 8499 { "attiny84", "__AVR_ATtiny84__" }, 8500 { "attiny84a", "__AVR_ATtiny84A__" }, 8501 { "attiny25", "__AVR_ATtiny25__" }, 8502 { "attiny45", "__AVR_ATtiny45__" }, 8503 { "attiny85", "__AVR_ATtiny85__" }, 8504 { "attiny261", "__AVR_ATtiny261__" }, 8505 { "attiny261a", "__AVR_ATtiny261A__" }, 8506 { "attiny461", "__AVR_ATtiny461__" }, 8507 { "attiny461a", "__AVR_ATtiny461A__" }, 8508 { "attiny861", "__AVR_ATtiny861__" }, 8509 { "attiny861a", "__AVR_ATtiny861A__" }, 8510 { "attiny87", "__AVR_ATtiny87__" }, 8511 { "attiny43u", "__AVR_ATtiny43U__" }, 8512 { "attiny48", "__AVR_ATtiny48__" }, 8513 { "attiny88", "__AVR_ATtiny88__" }, 8514 { "attiny828", "__AVR_ATtiny828__" }, 8515 { "at43usb355", "__AVR_AT43USB355__" }, 8516 { "at76c711", "__AVR_AT76C711__" }, 8517 { "atmega103", "__AVR_ATmega103__" }, 8518 { "at43usb320", "__AVR_AT43USB320__" }, 8519 { "attiny167", "__AVR_ATtiny167__" }, 8520 { "at90usb82", "__AVR_AT90USB82__" }, 8521 { "at90usb162", "__AVR_AT90USB162__" }, 8522 { "ata5505", "__AVR_ATA5505__" }, 8523 { "atmega8u2", "__AVR_ATmega8U2__" }, 8524 { "atmega16u2", "__AVR_ATmega16U2__" }, 8525 { "atmega32u2", "__AVR_ATmega32U2__" }, 8526 { "attiny1634", "__AVR_ATtiny1634__" }, 8527 { "atmega8", "__AVR_ATmega8__" }, 8528 { "ata6289", "__AVR_ATA6289__" }, 8529 { "atmega8a", "__AVR_ATmega8A__" }, 8530 { "ata6285", "__AVR_ATA6285__" }, 8531 { "ata6286", "__AVR_ATA6286__" }, 8532 { "atmega48", "__AVR_ATmega48__" }, 8533 { "atmega48a", "__AVR_ATmega48A__" }, 8534 { "atmega48pa", "__AVR_ATmega48PA__" }, 8535 { "atmega48p", "__AVR_ATmega48P__" }, 8536 { "atmega88", "__AVR_ATmega88__" }, 8537 { "atmega88a", "__AVR_ATmega88A__" }, 8538 { "atmega88p", "__AVR_ATmega88P__" }, 8539 { "atmega88pa", "__AVR_ATmega88PA__" }, 8540 { "atmega8515", "__AVR_ATmega8515__" }, 8541 { "atmega8535", "__AVR_ATmega8535__" }, 8542 { "atmega8hva", "__AVR_ATmega8HVA__" }, 8543 { "at90pwm1", "__AVR_AT90PWM1__" }, 8544 { "at90pwm2", "__AVR_AT90PWM2__" }, 8545 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 8546 { "at90pwm3", "__AVR_AT90PWM3__" }, 8547 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 8548 { "at90pwm81", "__AVR_AT90PWM81__" }, 8549 { "ata5790", "__AVR_ATA5790__" }, 8550 { "ata5795", "__AVR_ATA5795__" }, 8551 { "atmega16", "__AVR_ATmega16__" }, 8552 { "atmega16a", "__AVR_ATmega16A__" }, 8553 { "atmega161", "__AVR_ATmega161__" }, 8554 { "atmega162", "__AVR_ATmega162__" }, 8555 { "atmega163", "__AVR_ATmega163__" }, 8556 { "atmega164a", "__AVR_ATmega164A__" }, 8557 { "atmega164p", "__AVR_ATmega164P__" }, 8558 { "atmega164pa", "__AVR_ATmega164PA__" }, 8559 { "atmega165", "__AVR_ATmega165__" }, 8560 { "atmega165a", "__AVR_ATmega165A__" }, 8561 { "atmega165p", "__AVR_ATmega165P__" }, 8562 { "atmega165pa", "__AVR_ATmega165PA__" }, 8563 { "atmega168", "__AVR_ATmega168__" }, 8564 { "atmega168a", "__AVR_ATmega168A__" }, 8565 { "atmega168p", "__AVR_ATmega168P__" }, 8566 { "atmega168pa", "__AVR_ATmega168PA__" }, 8567 { "atmega169", "__AVR_ATmega169__" }, 8568 { "atmega169a", "__AVR_ATmega169A__" }, 8569 { "atmega169p", "__AVR_ATmega169P__" }, 8570 { "atmega169pa", "__AVR_ATmega169PA__" }, 8571 { "atmega32", "__AVR_ATmega32__" }, 8572 { "atmega32a", "__AVR_ATmega32A__" }, 8573 { "atmega323", "__AVR_ATmega323__" }, 8574 { "atmega324a", "__AVR_ATmega324A__" }, 8575 { "atmega324p", "__AVR_ATmega324P__" }, 8576 { "atmega324pa", "__AVR_ATmega324PA__" }, 8577 { "atmega325", "__AVR_ATmega325__" }, 8578 { "atmega325a", "__AVR_ATmega325A__" }, 8579 { "atmega325p", "__AVR_ATmega325P__" }, 8580 { "atmega325pa", "__AVR_ATmega325PA__" }, 8581 { "atmega3250", "__AVR_ATmega3250__" }, 8582 { "atmega3250a", "__AVR_ATmega3250A__" }, 8583 { "atmega3250p", "__AVR_ATmega3250P__" }, 8584 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 8585 { "atmega328", "__AVR_ATmega328__" }, 8586 { "atmega328p", "__AVR_ATmega328P__" }, 8587 { "atmega329", "__AVR_ATmega329__" }, 8588 { "atmega329a", "__AVR_ATmega329A__" }, 8589 { "atmega329p", "__AVR_ATmega329P__" }, 8590 { "atmega329pa", "__AVR_ATmega329PA__" }, 8591 { "atmega3290", "__AVR_ATmega3290__" }, 8592 { "atmega3290a", "__AVR_ATmega3290A__" }, 8593 { "atmega3290p", "__AVR_ATmega3290P__" }, 8594 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 8595 { "atmega406", "__AVR_ATmega406__" }, 8596 { "atmega64", "__AVR_ATmega64__" }, 8597 { "atmega64a", "__AVR_ATmega64A__" }, 8598 { "atmega640", "__AVR_ATmega640__" }, 8599 { "atmega644", "__AVR_ATmega644__" }, 8600 { "atmega644a", "__AVR_ATmega644A__" }, 8601 { "atmega644p", "__AVR_ATmega644P__" }, 8602 { "atmega644pa", "__AVR_ATmega644PA__" }, 8603 { "atmega645", "__AVR_ATmega645__" }, 8604 { "atmega645a", "__AVR_ATmega645A__" }, 8605 { "atmega645p", "__AVR_ATmega645P__" }, 8606 { "atmega649", "__AVR_ATmega649__" }, 8607 { "atmega649a", "__AVR_ATmega649A__" }, 8608 { "atmega649p", "__AVR_ATmega649P__" }, 8609 { "atmega6450", "__AVR_ATmega6450__" }, 8610 { "atmega6450a", "__AVR_ATmega6450A__" }, 8611 { "atmega6450p", "__AVR_ATmega6450P__" }, 8612 { "atmega6490", "__AVR_ATmega6490__" }, 8613 { "atmega6490a", "__AVR_ATmega6490A__" }, 8614 { "atmega6490p", "__AVR_ATmega6490P__" }, 8615 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 8616 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 8617 { "atmega16hva", "__AVR_ATmega16HVA__" }, 8618 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 8619 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 8620 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 8621 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 8622 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 8623 { "atmega64hve", "__AVR_ATmega64HVE__" }, 8624 { "at90can32", "__AVR_AT90CAN32__" }, 8625 { "at90can64", "__AVR_AT90CAN64__" }, 8626 { "at90pwm161", "__AVR_AT90PWM161__" }, 8627 { "at90pwm216", "__AVR_AT90PWM216__" }, 8628 { "at90pwm316", "__AVR_AT90PWM316__" }, 8629 { "atmega32c1", "__AVR_ATmega32C1__" }, 8630 { "atmega64c1", "__AVR_ATmega64C1__" }, 8631 { "atmega16m1", "__AVR_ATmega16M1__" }, 8632 { "atmega32m1", "__AVR_ATmega32M1__" }, 8633 { "atmega64m1", "__AVR_ATmega64M1__" }, 8634 { "atmega16u4", "__AVR_ATmega16U4__" }, 8635 { "atmega32u4", "__AVR_ATmega32U4__" }, 8636 { "atmega32u6", "__AVR_ATmega32U6__" }, 8637 { "at90usb646", "__AVR_AT90USB646__" }, 8638 { "at90usb647", "__AVR_AT90USB647__" }, 8639 { "at90scr100", "__AVR_AT90SCR100__" }, 8640 { "at94k", "__AVR_AT94K__" }, 8641 { "m3000", "__AVR_AT000__" }, 8642 { "atmega128", "__AVR_ATmega128__" }, 8643 { "atmega128a", "__AVR_ATmega128A__" }, 8644 { "atmega1280", "__AVR_ATmega1280__" }, 8645 { "atmega1281", "__AVR_ATmega1281__" }, 8646 { "atmega1284", "__AVR_ATmega1284__" }, 8647 { "atmega1284p", "__AVR_ATmega1284P__" }, 8648 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 8649 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 8650 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 8651 { "at90can128", "__AVR_AT90CAN128__" }, 8652 { "at90usb1286", "__AVR_AT90USB1286__" }, 8653 { "at90usb1287", "__AVR_AT90USB1287__" }, 8654 { "atmega2560", "__AVR_ATmega2560__" }, 8655 { "atmega2561", "__AVR_ATmega2561__" }, 8656 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 8657 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 8658 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 8659 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 8660 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 8661 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 8662 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 8663 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 8664 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 8665 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 8666 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 8667 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 8668 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 8669 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 8670 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 8671 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 8672 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 8673 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 8674 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 8675 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 8676 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 8677 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 8678 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 8679 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 8680 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 8681 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 8682 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 8683 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 8684 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 8685 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 8686 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 8687 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 8688 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 8689 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 8690 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 8691 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 8692 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 8693 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 8694 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 8695 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 8696 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 8697 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 8698 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 8699 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 8700 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 8701 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 8702 { "attiny4", "__AVR_ATtiny4__" }, 8703 { "attiny5", "__AVR_ATtiny5__" }, 8704 { "attiny9", "__AVR_ATtiny9__" }, 8705 { "attiny10", "__AVR_ATtiny10__" }, 8706 { "attiny20", "__AVR_ATtiny20__" }, 8707 { "attiny40", "__AVR_ATtiny40__" }, 8708 { "attiny102", "__AVR_ATtiny102__" }, 8709 { "attiny104", "__AVR_ATtiny104__" }, 8710 }; 8711 8712 // AVR Target 8713 class AVRTargetInfo : public TargetInfo { 8714 public: 8715 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8716 : TargetInfo(Triple) { 8717 TLSSupported = false; 8718 PointerWidth = 16; 8719 PointerAlign = 8; 8720 IntWidth = 16; 8721 IntAlign = 8; 8722 LongWidth = 32; 8723 LongAlign = 8; 8724 LongLongWidth = 64; 8725 LongLongAlign = 8; 8726 SuitableAlign = 8; 8727 DefaultAlignForAttributeAligned = 8; 8728 HalfWidth = 16; 8729 HalfAlign = 8; 8730 FloatWidth = 32; 8731 FloatAlign = 8; 8732 DoubleWidth = 32; 8733 DoubleAlign = 8; 8734 DoubleFormat = &llvm::APFloat::IEEEsingle(); 8735 LongDoubleWidth = 32; 8736 LongDoubleAlign = 8; 8737 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 8738 SizeType = UnsignedInt; 8739 PtrDiffType = SignedInt; 8740 IntPtrType = SignedInt; 8741 Char16Type = UnsignedInt; 8742 WCharType = SignedInt; 8743 WIntType = SignedInt; 8744 Char32Type = UnsignedLong; 8745 SigAtomicType = SignedChar; 8746 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 8747 "-f32:32:32-f64:64:64-n8"); 8748 } 8749 8750 void getTargetDefines(const LangOptions &Opts, 8751 MacroBuilder &Builder) const override { 8752 Builder.defineMacro("AVR"); 8753 Builder.defineMacro("__AVR"); 8754 Builder.defineMacro("__AVR__"); 8755 8756 if (!this->CPU.empty()) { 8757 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 8758 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 8759 8760 if (It != AVRMcus.end()) 8761 Builder.defineMacro(It->DefineName); 8762 } 8763 } 8764 8765 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8766 return None; 8767 } 8768 8769 BuiltinVaListKind getBuiltinVaListKind() const override { 8770 return TargetInfo::VoidPtrBuiltinVaList; 8771 } 8772 8773 const char *getClobbers() const override { 8774 return ""; 8775 } 8776 8777 ArrayRef<const char *> getGCCRegNames() const override { 8778 static const char * const GCCRegNames[] = { 8779 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8780 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 8781 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 8782 "r24", "r25", "X", "Y", "Z", "SP" 8783 }; 8784 return llvm::makeArrayRef(GCCRegNames); 8785 } 8786 8787 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8788 return None; 8789 } 8790 8791 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 8792 static const TargetInfo::AddlRegName AddlRegNames[] = { 8793 { { "r26", "r27"}, 26 }, 8794 { { "r28", "r29"}, 27 }, 8795 { { "r30", "r31"}, 28 }, 8796 { { "SPL", "SPH"}, 29 }, 8797 }; 8798 return llvm::makeArrayRef(AddlRegNames); 8799 } 8800 8801 bool validateAsmConstraint(const char *&Name, 8802 TargetInfo::ConstraintInfo &Info) const override { 8803 // There aren't any multi-character AVR specific constraints. 8804 if (StringRef(Name).size() > 1) return false; 8805 8806 switch (*Name) { 8807 default: return false; 8808 case 'a': // Simple upper registers 8809 case 'b': // Base pointer registers pairs 8810 case 'd': // Upper register 8811 case 'l': // Lower registers 8812 case 'e': // Pointer register pairs 8813 case 'q': // Stack pointer register 8814 case 'r': // Any register 8815 case 'w': // Special upper register pairs 8816 case 't': // Temporary register 8817 case 'x': case 'X': // Pointer register pair X 8818 case 'y': case 'Y': // Pointer register pair Y 8819 case 'z': case 'Z': // Pointer register pair Z 8820 Info.setAllowsRegister(); 8821 return true; 8822 case 'I': // 6-bit positive integer constant 8823 Info.setRequiresImmediate(0, 63); 8824 return true; 8825 case 'J': // 6-bit negative integer constant 8826 Info.setRequiresImmediate(-63, 0); 8827 return true; 8828 case 'K': // Integer constant (Range: 2) 8829 Info.setRequiresImmediate(2); 8830 return true; 8831 case 'L': // Integer constant (Range: 0) 8832 Info.setRequiresImmediate(0); 8833 return true; 8834 case 'M': // 8-bit integer constant 8835 Info.setRequiresImmediate(0, 0xff); 8836 return true; 8837 case 'N': // Integer constant (Range: -1) 8838 Info.setRequiresImmediate(-1); 8839 return true; 8840 case 'O': // Integer constant (Range: 8, 16, 24) 8841 Info.setRequiresImmediate({8, 16, 24}); 8842 return true; 8843 case 'P': // Integer constant (Range: 1) 8844 Info.setRequiresImmediate(1); 8845 return true; 8846 case 'R': // Integer constant (Range: -6 to 5) 8847 Info.setRequiresImmediate(-6, 5); 8848 return true; 8849 case 'G': // Floating point constant 8850 case 'Q': // A memory address based on Y or Z pointer with displacement. 8851 return true; 8852 } 8853 8854 return false; 8855 } 8856 8857 IntType getIntTypeByWidth(unsigned BitWidth, 8858 bool IsSigned) const final { 8859 // AVR prefers int for 16-bit integers. 8860 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 8861 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8862 } 8863 8864 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8865 bool IsSigned) const final { 8866 // AVR uses int for int_least16_t and int_fast16_t. 8867 return BitWidth == 16 8868 ? (IsSigned ? SignedInt : UnsignedInt) 8869 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8870 } 8871 8872 bool setCPU(const std::string &Name) override { 8873 bool IsFamily = llvm::StringSwitch<bool>(Name) 8874 .Case("avr1", true) 8875 .Case("avr2", true) 8876 .Case("avr25", true) 8877 .Case("avr3", true) 8878 .Case("avr31", true) 8879 .Case("avr35", true) 8880 .Case("avr4", true) 8881 .Case("avr5", true) 8882 .Case("avr51", true) 8883 .Case("avr6", true) 8884 .Case("avrxmega1", true) 8885 .Case("avrxmega2", true) 8886 .Case("avrxmega3", true) 8887 .Case("avrxmega4", true) 8888 .Case("avrxmega5", true) 8889 .Case("avrxmega6", true) 8890 .Case("avrxmega7", true) 8891 .Case("avrtiny", true) 8892 .Default(false); 8893 8894 if (IsFamily) this->CPU = Name; 8895 8896 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 8897 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 8898 8899 if (IsMCU) this->CPU = Name; 8900 8901 return IsFamily || IsMCU; 8902 } 8903 8904 protected: 8905 std::string CPU; 8906 }; 8907 8908 } // end anonymous namespace 8909 8910 //===----------------------------------------------------------------------===// 8911 // Driver code 8912 //===----------------------------------------------------------------------===// 8913 8914 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8915 const TargetOptions &Opts) { 8916 llvm::Triple::OSType os = Triple.getOS(); 8917 8918 switch (Triple.getArch()) { 8919 default: 8920 return nullptr; 8921 8922 case llvm::Triple::xcore: 8923 return new XCoreTargetInfo(Triple, Opts); 8924 8925 case llvm::Triple::hexagon: 8926 return new HexagonTargetInfo(Triple, Opts); 8927 8928 case llvm::Triple::lanai: 8929 return new LanaiTargetInfo(Triple, Opts); 8930 8931 case llvm::Triple::aarch64: 8932 if (Triple.isOSDarwin()) 8933 return new DarwinAArch64TargetInfo(Triple, Opts); 8934 8935 switch (os) { 8936 case llvm::Triple::CloudABI: 8937 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8938 case llvm::Triple::FreeBSD: 8939 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8940 case llvm::Triple::Fuchsia: 8941 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8942 case llvm::Triple::Linux: 8943 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8944 case llvm::Triple::NetBSD: 8945 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8946 default: 8947 return new AArch64leTargetInfo(Triple, Opts); 8948 } 8949 8950 case llvm::Triple::aarch64_be: 8951 switch (os) { 8952 case llvm::Triple::FreeBSD: 8953 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8954 case llvm::Triple::Fuchsia: 8955 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8956 case llvm::Triple::Linux: 8957 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8958 case llvm::Triple::NetBSD: 8959 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8960 default: 8961 return new AArch64beTargetInfo(Triple, Opts); 8962 } 8963 8964 case llvm::Triple::arm: 8965 case llvm::Triple::thumb: 8966 if (Triple.isOSBinFormatMachO()) 8967 return new DarwinARMTargetInfo(Triple, Opts); 8968 8969 switch (os) { 8970 case llvm::Triple::CloudABI: 8971 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 8972 case llvm::Triple::Linux: 8973 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8974 case llvm::Triple::FreeBSD: 8975 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8976 case llvm::Triple::NetBSD: 8977 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8978 case llvm::Triple::OpenBSD: 8979 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8980 case llvm::Triple::Bitrig: 8981 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8982 case llvm::Triple::RTEMS: 8983 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8984 case llvm::Triple::NaCl: 8985 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8986 case llvm::Triple::Win32: 8987 switch (Triple.getEnvironment()) { 8988 case llvm::Triple::Cygnus: 8989 return new CygwinARMTargetInfo(Triple, Opts); 8990 case llvm::Triple::GNU: 8991 return new MinGWARMTargetInfo(Triple, Opts); 8992 case llvm::Triple::Itanium: 8993 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8994 case llvm::Triple::MSVC: 8995 default: // Assume MSVC for unknown environments 8996 return new MicrosoftARMleTargetInfo(Triple, Opts); 8997 } 8998 default: 8999 return new ARMleTargetInfo(Triple, Opts); 9000 } 9001 9002 case llvm::Triple::armeb: 9003 case llvm::Triple::thumbeb: 9004 if (Triple.isOSDarwin()) 9005 return new DarwinARMTargetInfo(Triple, Opts); 9006 9007 switch (os) { 9008 case llvm::Triple::Linux: 9009 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9010 case llvm::Triple::FreeBSD: 9011 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9012 case llvm::Triple::NetBSD: 9013 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9014 case llvm::Triple::OpenBSD: 9015 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9016 case llvm::Triple::Bitrig: 9017 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9018 case llvm::Triple::RTEMS: 9019 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9020 case llvm::Triple::NaCl: 9021 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9022 default: 9023 return new ARMbeTargetInfo(Triple, Opts); 9024 } 9025 9026 case llvm::Triple::avr: 9027 return new AVRTargetInfo(Triple, Opts); 9028 case llvm::Triple::bpfeb: 9029 case llvm::Triple::bpfel: 9030 return new BPFTargetInfo(Triple, Opts); 9031 9032 case llvm::Triple::msp430: 9033 return new MSP430TargetInfo(Triple, Opts); 9034 9035 case llvm::Triple::mips: 9036 switch (os) { 9037 case llvm::Triple::Linux: 9038 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9039 case llvm::Triple::RTEMS: 9040 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9041 case llvm::Triple::FreeBSD: 9042 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9043 case llvm::Triple::NetBSD: 9044 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9045 default: 9046 return new MipsTargetInfo(Triple, Opts); 9047 } 9048 9049 case llvm::Triple::mipsel: 9050 switch (os) { 9051 case llvm::Triple::Linux: 9052 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9053 case llvm::Triple::RTEMS: 9054 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9055 case llvm::Triple::FreeBSD: 9056 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9057 case llvm::Triple::NetBSD: 9058 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9059 case llvm::Triple::NaCl: 9060 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9061 default: 9062 return new MipsTargetInfo(Triple, Opts); 9063 } 9064 9065 case llvm::Triple::mips64: 9066 switch (os) { 9067 case llvm::Triple::Linux: 9068 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9069 case llvm::Triple::RTEMS: 9070 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9071 case llvm::Triple::FreeBSD: 9072 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9073 case llvm::Triple::NetBSD: 9074 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9075 case llvm::Triple::OpenBSD: 9076 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9077 default: 9078 return new MipsTargetInfo(Triple, Opts); 9079 } 9080 9081 case llvm::Triple::mips64el: 9082 switch (os) { 9083 case llvm::Triple::Linux: 9084 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9085 case llvm::Triple::RTEMS: 9086 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9087 case llvm::Triple::FreeBSD: 9088 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9089 case llvm::Triple::NetBSD: 9090 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9091 case llvm::Triple::OpenBSD: 9092 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9093 default: 9094 return new MipsTargetInfo(Triple, Opts); 9095 } 9096 9097 case llvm::Triple::le32: 9098 switch (os) { 9099 case llvm::Triple::NaCl: 9100 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9101 default: 9102 return nullptr; 9103 } 9104 9105 case llvm::Triple::le64: 9106 return new Le64TargetInfo(Triple, Opts); 9107 9108 case llvm::Triple::ppc: 9109 if (Triple.isOSDarwin()) 9110 return new DarwinPPC32TargetInfo(Triple, Opts); 9111 switch (os) { 9112 case llvm::Triple::Linux: 9113 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9114 case llvm::Triple::FreeBSD: 9115 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9116 case llvm::Triple::NetBSD: 9117 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9118 case llvm::Triple::OpenBSD: 9119 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9120 case llvm::Triple::RTEMS: 9121 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9122 default: 9123 return new PPC32TargetInfo(Triple, Opts); 9124 } 9125 9126 case llvm::Triple::ppc64: 9127 if (Triple.isOSDarwin()) 9128 return new DarwinPPC64TargetInfo(Triple, Opts); 9129 switch (os) { 9130 case llvm::Triple::Linux: 9131 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9132 case llvm::Triple::Lv2: 9133 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9134 case llvm::Triple::FreeBSD: 9135 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9136 case llvm::Triple::NetBSD: 9137 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9138 default: 9139 return new PPC64TargetInfo(Triple, Opts); 9140 } 9141 9142 case llvm::Triple::ppc64le: 9143 switch (os) { 9144 case llvm::Triple::Linux: 9145 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9146 case llvm::Triple::NetBSD: 9147 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9148 default: 9149 return new PPC64TargetInfo(Triple, Opts); 9150 } 9151 9152 case llvm::Triple::nvptx: 9153 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9154 case llvm::Triple::nvptx64: 9155 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9156 9157 case llvm::Triple::amdgcn: 9158 case llvm::Triple::r600: 9159 return new AMDGPUTargetInfo(Triple, Opts); 9160 9161 case llvm::Triple::sparc: 9162 switch (os) { 9163 case llvm::Triple::Linux: 9164 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9165 case llvm::Triple::Solaris: 9166 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9167 case llvm::Triple::NetBSD: 9168 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9169 case llvm::Triple::OpenBSD: 9170 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9171 case llvm::Triple::RTEMS: 9172 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9173 default: 9174 return new SparcV8TargetInfo(Triple, Opts); 9175 } 9176 9177 // The 'sparcel' architecture copies all the above cases except for Solaris. 9178 case llvm::Triple::sparcel: 9179 switch (os) { 9180 case llvm::Triple::Linux: 9181 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9182 case llvm::Triple::NetBSD: 9183 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9184 case llvm::Triple::OpenBSD: 9185 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9186 case llvm::Triple::RTEMS: 9187 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9188 default: 9189 return new SparcV8elTargetInfo(Triple, Opts); 9190 } 9191 9192 case llvm::Triple::sparcv9: 9193 switch (os) { 9194 case llvm::Triple::Linux: 9195 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9196 case llvm::Triple::Solaris: 9197 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9198 case llvm::Triple::NetBSD: 9199 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9200 case llvm::Triple::OpenBSD: 9201 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9202 case llvm::Triple::FreeBSD: 9203 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9204 default: 9205 return new SparcV9TargetInfo(Triple, Opts); 9206 } 9207 9208 case llvm::Triple::systemz: 9209 switch (os) { 9210 case llvm::Triple::Linux: 9211 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9212 default: 9213 return new SystemZTargetInfo(Triple, Opts); 9214 } 9215 9216 case llvm::Triple::tce: 9217 return new TCETargetInfo(Triple, Opts); 9218 9219 case llvm::Triple::tcele: 9220 return new TCELETargetInfo(Triple, Opts); 9221 9222 case llvm::Triple::x86: 9223 if (Triple.isOSDarwin()) 9224 return new DarwinI386TargetInfo(Triple, Opts); 9225 9226 switch (os) { 9227 case llvm::Triple::CloudABI: 9228 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9229 case llvm::Triple::Linux: { 9230 switch (Triple.getEnvironment()) { 9231 default: 9232 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9233 case llvm::Triple::Android: 9234 return new AndroidX86_32TargetInfo(Triple, Opts); 9235 } 9236 } 9237 case llvm::Triple::DragonFly: 9238 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9239 case llvm::Triple::NetBSD: 9240 return new NetBSDI386TargetInfo(Triple, Opts); 9241 case llvm::Triple::OpenBSD: 9242 return new OpenBSDI386TargetInfo(Triple, Opts); 9243 case llvm::Triple::Bitrig: 9244 return new BitrigI386TargetInfo(Triple, Opts); 9245 case llvm::Triple::FreeBSD: 9246 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9247 case llvm::Triple::KFreeBSD: 9248 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9249 case llvm::Triple::Minix: 9250 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9251 case llvm::Triple::Solaris: 9252 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9253 case llvm::Triple::Win32: { 9254 switch (Triple.getEnvironment()) { 9255 case llvm::Triple::Cygnus: 9256 return new CygwinX86_32TargetInfo(Triple, Opts); 9257 case llvm::Triple::GNU: 9258 return new MinGWX86_32TargetInfo(Triple, Opts); 9259 case llvm::Triple::Itanium: 9260 case llvm::Triple::MSVC: 9261 default: // Assume MSVC for unknown environments 9262 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9263 } 9264 } 9265 case llvm::Triple::Haiku: 9266 return new HaikuX86_32TargetInfo(Triple, Opts); 9267 case llvm::Triple::RTEMS: 9268 return new RTEMSX86_32TargetInfo(Triple, Opts); 9269 case llvm::Triple::NaCl: 9270 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9271 case llvm::Triple::ELFIAMCU: 9272 return new MCUX86_32TargetInfo(Triple, Opts); 9273 default: 9274 return new X86_32TargetInfo(Triple, Opts); 9275 } 9276 9277 case llvm::Triple::x86_64: 9278 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9279 return new DarwinX86_64TargetInfo(Triple, Opts); 9280 9281 switch (os) { 9282 case llvm::Triple::CloudABI: 9283 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9284 case llvm::Triple::Linux: { 9285 switch (Triple.getEnvironment()) { 9286 default: 9287 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9288 case llvm::Triple::Android: 9289 return new AndroidX86_64TargetInfo(Triple, Opts); 9290 } 9291 } 9292 case llvm::Triple::DragonFly: 9293 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9294 case llvm::Triple::NetBSD: 9295 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9296 case llvm::Triple::OpenBSD: 9297 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9298 case llvm::Triple::Bitrig: 9299 return new BitrigX86_64TargetInfo(Triple, Opts); 9300 case llvm::Triple::FreeBSD: 9301 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9302 case llvm::Triple::Fuchsia: 9303 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9304 case llvm::Triple::KFreeBSD: 9305 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9306 case llvm::Triple::Solaris: 9307 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9308 case llvm::Triple::Win32: { 9309 switch (Triple.getEnvironment()) { 9310 case llvm::Triple::Cygnus: 9311 return new CygwinX86_64TargetInfo(Triple, Opts); 9312 case llvm::Triple::GNU: 9313 return new MinGWX86_64TargetInfo(Triple, Opts); 9314 case llvm::Triple::MSVC: 9315 default: // Assume MSVC for unknown environments 9316 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9317 } 9318 } 9319 case llvm::Triple::Haiku: 9320 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9321 case llvm::Triple::NaCl: 9322 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9323 case llvm::Triple::PS4: 9324 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9325 default: 9326 return new X86_64TargetInfo(Triple, Opts); 9327 } 9328 9329 case llvm::Triple::spir: { 9330 if (Triple.getOS() != llvm::Triple::UnknownOS || 9331 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9332 return nullptr; 9333 return new SPIR32TargetInfo(Triple, Opts); 9334 } 9335 case llvm::Triple::spir64: { 9336 if (Triple.getOS() != llvm::Triple::UnknownOS || 9337 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9338 return nullptr; 9339 return new SPIR64TargetInfo(Triple, Opts); 9340 } 9341 case llvm::Triple::wasm32: 9342 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9343 Triple.getVendor() != llvm::Triple::UnknownVendor || 9344 Triple.getOS() != llvm::Triple::UnknownOS || 9345 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9346 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9347 return nullptr; 9348 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9349 case llvm::Triple::wasm64: 9350 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9351 Triple.getVendor() != llvm::Triple::UnknownVendor || 9352 Triple.getOS() != llvm::Triple::UnknownOS || 9353 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9354 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9355 return nullptr; 9356 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9357 9358 case llvm::Triple::renderscript32: 9359 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9360 case llvm::Triple::renderscript64: 9361 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9362 } 9363 } 9364 9365 /// CreateTargetInfo - Return the target info object for the specified target 9366 /// options. 9367 TargetInfo * 9368 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9369 const std::shared_ptr<TargetOptions> &Opts) { 9370 llvm::Triple Triple(Opts->Triple); 9371 9372 // Construct the target 9373 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9374 if (!Target) { 9375 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9376 return nullptr; 9377 } 9378 Target->TargetOpts = Opts; 9379 9380 // Set the target CPU if specified. 9381 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9382 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9383 return nullptr; 9384 } 9385 9386 // Set the target ABI if specified. 9387 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 9388 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 9389 return nullptr; 9390 } 9391 9392 // Set the fp math unit. 9393 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 9394 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 9395 return nullptr; 9396 } 9397 9398 // Compute the default target features, we need the target to handle this 9399 // because features may have dependencies on one another. 9400 llvm::StringMap<bool> Features; 9401 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 9402 Opts->FeaturesAsWritten)) 9403 return nullptr; 9404 9405 // Add the features to the compile options. 9406 Opts->Features.clear(); 9407 for (const auto &F : Features) 9408 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 9409 9410 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 9411 return nullptr; 9412 9413 Target->setSupportedOpenCLOpts(); 9414 Target->setOpenCLExtensionOpts(); 9415 9416 if (!Target->validateTarget(Diags)) 9417 return nullptr; 9418 9419 return Target.release(); 9420 } 9421