1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/TargetParser.h" 31 #include <algorithm> 32 #include <memory> 33 34 using namespace clang; 35 36 //===----------------------------------------------------------------------===// 37 // Common code shared among targets. 38 //===----------------------------------------------------------------------===// 39 40 /// DefineStd - Define a macro name and standard variants. For example if 41 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 42 /// when in GNU mode. 43 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 44 const LangOptions &Opts) { 45 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 46 47 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 48 // in the user's namespace. 49 if (Opts.GNUMode) 50 Builder.defineMacro(MacroName); 51 52 // Define __unix. 53 Builder.defineMacro("__" + MacroName); 54 55 // Define __unix__. 56 Builder.defineMacro("__" + MacroName + "__"); 57 } 58 59 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 60 bool Tuning = true) { 61 Builder.defineMacro("__" + CPUName); 62 Builder.defineMacro("__" + CPUName + "__"); 63 if (Tuning) 64 Builder.defineMacro("__tune_" + CPUName + "__"); 65 } 66 67 //===----------------------------------------------------------------------===// 68 // Defines specific to certain operating systems. 69 //===----------------------------------------------------------------------===// 70 71 namespace { 72 template<typename TgtInfo> 73 class OSTargetInfo : public TgtInfo { 74 protected: 75 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 76 MacroBuilder &Builder) const=0; 77 public: 78 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 79 void getTargetDefines(const LangOptions &Opts, 80 MacroBuilder &Builder) const override { 81 TgtInfo::getTargetDefines(Opts, Builder); 82 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 83 } 84 85 }; 86 87 // CloudABI Target 88 template <typename Target> 89 class CloudABITargetInfo : public OSTargetInfo<Target> { 90 protected: 91 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 92 MacroBuilder &Builder) const override { 93 Builder.defineMacro("__CloudABI__"); 94 Builder.defineMacro("__ELF__"); 95 96 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 97 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 98 Builder.defineMacro("__STDC_UTF_16__"); 99 Builder.defineMacro("__STDC_UTF_32__"); 100 } 101 102 public: 103 CloudABITargetInfo(const llvm::Triple &Triple) 104 : OSTargetInfo<Target>(Triple) { 105 this->UserLabelPrefix = ""; 106 } 107 }; 108 109 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 110 const llvm::Triple &Triple, 111 StringRef &PlatformName, 112 VersionTuple &PlatformMinVersion) { 113 Builder.defineMacro("__APPLE_CC__", "6000"); 114 Builder.defineMacro("__APPLE__"); 115 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 116 // AddressSanitizer doesn't play well with source fortification, which is on 117 // by default on Darwin. 118 if (Opts.Sanitize.has(SanitizerKind::Address)) 119 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 120 121 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 122 if (!Opts.ObjC1) { 123 // __weak is always defined, for use in blocks and with objc pointers. 124 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 125 Builder.defineMacro("__strong", ""); 126 Builder.defineMacro("__unsafe_unretained", ""); 127 } 128 129 if (Opts.Static) 130 Builder.defineMacro("__STATIC__"); 131 else 132 Builder.defineMacro("__DYNAMIC__"); 133 134 if (Opts.POSIXThreads) 135 Builder.defineMacro("_REENTRANT"); 136 137 // Get the platform type and version number from the triple. 138 unsigned Maj, Min, Rev; 139 if (Triple.isMacOSX()) { 140 Triple.getMacOSXVersion(Maj, Min, Rev); 141 PlatformName = "macosx"; 142 } else { 143 Triple.getOSVersion(Maj, Min, Rev); 144 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 145 } 146 147 // If -target arch-pc-win32-macho option specified, we're 148 // generating code for Win32 ABI. No need to emit 149 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 150 if (PlatformName == "win32") { 151 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 152 return; 153 } 154 155 // Set the appropriate OS version define. 156 if (Triple.isiOS()) { 157 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 158 char Str[6]; 159 Str[0] = '0' + Maj; 160 Str[1] = '0' + (Min / 10); 161 Str[2] = '0' + (Min % 10); 162 Str[3] = '0' + (Rev / 10); 163 Str[4] = '0' + (Rev % 10); 164 Str[5] = '\0'; 165 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str); 166 } else if (Triple.isMacOSX()) { 167 // Note that the Driver allows versions which aren't representable in the 168 // define (because we only get a single digit for the minor and micro 169 // revision numbers). So, we limit them to the maximum representable 170 // version. 171 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 172 char Str[7]; 173 if (Maj < 10 || (Maj == 10 && Min < 10)) { 174 Str[0] = '0' + (Maj / 10); 175 Str[1] = '0' + (Maj % 10); 176 Str[2] = '0' + std::min(Min, 9U); 177 Str[3] = '0' + std::min(Rev, 9U); 178 Str[4] = '\0'; 179 } else { 180 // Handle versions > 10.9. 181 Str[0] = '0' + (Maj / 10); 182 Str[1] = '0' + (Maj % 10); 183 Str[2] = '0' + (Min / 10); 184 Str[3] = '0' + (Min % 10); 185 Str[4] = '0' + (Rev / 10); 186 Str[5] = '0' + (Rev % 10); 187 Str[6] = '\0'; 188 } 189 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 190 } 191 192 // Tell users about the kernel if there is one. 193 if (Triple.isOSDarwin()) 194 Builder.defineMacro("__MACH__"); 195 196 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 197 } 198 199 template<typename Target> 200 class DarwinTargetInfo : public OSTargetInfo<Target> { 201 protected: 202 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 203 MacroBuilder &Builder) const override { 204 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 205 this->PlatformMinVersion); 206 } 207 208 public: 209 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 210 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 211 this->MCountName = "\01mcount"; 212 } 213 214 std::string isValidSectionSpecifier(StringRef SR) const override { 215 // Let MCSectionMachO validate this. 216 StringRef Segment, Section; 217 unsigned TAA, StubSize; 218 bool HasTAA; 219 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 220 TAA, HasTAA, StubSize); 221 } 222 223 const char *getStaticInitSectionSpecifier() const override { 224 // FIXME: We should return 0 when building kexts. 225 return "__TEXT,__StaticInit,regular,pure_instructions"; 226 } 227 228 /// Darwin does not support protected visibility. Darwin's "default" 229 /// is very similar to ELF's "protected"; Darwin requires a "weak" 230 /// attribute on declarations that can be dynamically replaced. 231 bool hasProtectedVisibility() const override { 232 return false; 233 } 234 }; 235 236 237 // DragonFlyBSD Target 238 template<typename Target> 239 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 240 protected: 241 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 242 MacroBuilder &Builder) const override { 243 // DragonFly defines; list based off of gcc output 244 Builder.defineMacro("__DragonFly__"); 245 Builder.defineMacro("__DragonFly_cc_version", "100001"); 246 Builder.defineMacro("__ELF__"); 247 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 248 Builder.defineMacro("__tune_i386__"); 249 DefineStd(Builder, "unix", Opts); 250 } 251 public: 252 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 253 : OSTargetInfo<Target>(Triple) { 254 this->UserLabelPrefix = ""; 255 256 switch (Triple.getArch()) { 257 default: 258 case llvm::Triple::x86: 259 case llvm::Triple::x86_64: 260 this->MCountName = ".mcount"; 261 break; 262 } 263 } 264 }; 265 266 // FreeBSD Target 267 template<typename Target> 268 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 269 protected: 270 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 271 MacroBuilder &Builder) const override { 272 // FreeBSD defines; list based off of gcc output 273 274 unsigned Release = Triple.getOSMajorVersion(); 275 if (Release == 0U) 276 Release = 8; 277 278 Builder.defineMacro("__FreeBSD__", Twine(Release)); 279 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 280 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 281 DefineStd(Builder, "unix", Opts); 282 Builder.defineMacro("__ELF__"); 283 284 // On FreeBSD, wchar_t contains the number of the code point as 285 // used by the character set of the locale. These character sets are 286 // not necessarily a superset of ASCII. 287 // 288 // FIXME: This is wrong; the macro refers to the numerical values 289 // of wchar_t *literals*, which are not locale-dependent. However, 290 // FreeBSD systems apparently depend on us getting this wrong, and 291 // setting this to 1 is conforming even if all the basic source 292 // character literals have the same encoding as char and wchar_t. 293 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 294 } 295 public: 296 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 297 this->UserLabelPrefix = ""; 298 299 switch (Triple.getArch()) { 300 default: 301 case llvm::Triple::x86: 302 case llvm::Triple::x86_64: 303 this->MCountName = ".mcount"; 304 break; 305 case llvm::Triple::mips: 306 case llvm::Triple::mipsel: 307 case llvm::Triple::ppc: 308 case llvm::Triple::ppc64: 309 case llvm::Triple::ppc64le: 310 this->MCountName = "_mcount"; 311 break; 312 case llvm::Triple::arm: 313 this->MCountName = "__mcount"; 314 break; 315 } 316 } 317 }; 318 319 // GNU/kFreeBSD Target 320 template<typename Target> 321 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 322 protected: 323 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 324 MacroBuilder &Builder) const override { 325 // GNU/kFreeBSD defines; list based off of gcc output 326 327 DefineStd(Builder, "unix", Opts); 328 Builder.defineMacro("__FreeBSD_kernel__"); 329 Builder.defineMacro("__GLIBC__"); 330 Builder.defineMacro("__ELF__"); 331 if (Opts.POSIXThreads) 332 Builder.defineMacro("_REENTRANT"); 333 if (Opts.CPlusPlus) 334 Builder.defineMacro("_GNU_SOURCE"); 335 } 336 public: 337 KFreeBSDTargetInfo(const llvm::Triple &Triple) 338 : OSTargetInfo<Target>(Triple) { 339 this->UserLabelPrefix = ""; 340 } 341 }; 342 343 // Minix Target 344 template<typename Target> 345 class MinixTargetInfo : public OSTargetInfo<Target> { 346 protected: 347 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 348 MacroBuilder &Builder) const override { 349 // Minix defines 350 351 Builder.defineMacro("__minix", "3"); 352 Builder.defineMacro("_EM_WSIZE", "4"); 353 Builder.defineMacro("_EM_PSIZE", "4"); 354 Builder.defineMacro("_EM_SSIZE", "2"); 355 Builder.defineMacro("_EM_LSIZE", "4"); 356 Builder.defineMacro("_EM_FSIZE", "4"); 357 Builder.defineMacro("_EM_DSIZE", "8"); 358 Builder.defineMacro("__ELF__"); 359 DefineStd(Builder, "unix", Opts); 360 } 361 public: 362 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 363 this->UserLabelPrefix = ""; 364 } 365 }; 366 367 // Linux target 368 template<typename Target> 369 class LinuxTargetInfo : public OSTargetInfo<Target> { 370 protected: 371 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 372 MacroBuilder &Builder) const override { 373 // Linux defines; list based off of gcc output 374 DefineStd(Builder, "unix", Opts); 375 DefineStd(Builder, "linux", Opts); 376 Builder.defineMacro("__gnu_linux__"); 377 Builder.defineMacro("__ELF__"); 378 if (Triple.isAndroid()) { 379 Builder.defineMacro("__ANDROID__", "1"); 380 unsigned Maj, Min, Rev; 381 Triple.getEnvironmentVersion(Maj, Min, Rev); 382 this->PlatformName = "android"; 383 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 384 } 385 if (Opts.POSIXThreads) 386 Builder.defineMacro("_REENTRANT"); 387 if (Opts.CPlusPlus) 388 Builder.defineMacro("_GNU_SOURCE"); 389 } 390 public: 391 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 392 this->UserLabelPrefix = ""; 393 this->WIntType = TargetInfo::UnsignedInt; 394 395 switch (Triple.getArch()) { 396 default: 397 break; 398 case llvm::Triple::ppc: 399 case llvm::Triple::ppc64: 400 case llvm::Triple::ppc64le: 401 this->MCountName = "_mcount"; 402 break; 403 } 404 } 405 406 const char *getStaticInitSectionSpecifier() const override { 407 return ".text.startup"; 408 } 409 }; 410 411 // NetBSD Target 412 template<typename Target> 413 class NetBSDTargetInfo : public OSTargetInfo<Target> { 414 protected: 415 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 416 MacroBuilder &Builder) const override { 417 // NetBSD defines; list based off of gcc output 418 Builder.defineMacro("__NetBSD__"); 419 Builder.defineMacro("__unix__"); 420 Builder.defineMacro("__ELF__"); 421 if (Opts.POSIXThreads) 422 Builder.defineMacro("_POSIX_THREADS"); 423 424 switch (Triple.getArch()) { 425 default: 426 break; 427 case llvm::Triple::arm: 428 case llvm::Triple::armeb: 429 case llvm::Triple::thumb: 430 case llvm::Triple::thumbeb: 431 Builder.defineMacro("__ARM_DWARF_EH__"); 432 break; 433 } 434 } 435 public: 436 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 437 this->UserLabelPrefix = ""; 438 this->MCountName = "_mcount"; 439 } 440 }; 441 442 // OpenBSD Target 443 template<typename Target> 444 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 445 protected: 446 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 447 MacroBuilder &Builder) const override { 448 // OpenBSD defines; list based off of gcc output 449 450 Builder.defineMacro("__OpenBSD__"); 451 DefineStd(Builder, "unix", Opts); 452 Builder.defineMacro("__ELF__"); 453 if (Opts.POSIXThreads) 454 Builder.defineMacro("_REENTRANT"); 455 } 456 public: 457 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 458 this->UserLabelPrefix = ""; 459 this->TLSSupported = false; 460 461 switch (Triple.getArch()) { 462 default: 463 case llvm::Triple::x86: 464 case llvm::Triple::x86_64: 465 case llvm::Triple::arm: 466 case llvm::Triple::sparc: 467 this->MCountName = "__mcount"; 468 break; 469 case llvm::Triple::mips64: 470 case llvm::Triple::mips64el: 471 case llvm::Triple::ppc: 472 case llvm::Triple::sparcv9: 473 this->MCountName = "_mcount"; 474 break; 475 } 476 } 477 }; 478 479 // Bitrig Target 480 template<typename Target> 481 class BitrigTargetInfo : public OSTargetInfo<Target> { 482 protected: 483 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 484 MacroBuilder &Builder) const override { 485 // Bitrig defines; list based off of gcc output 486 487 Builder.defineMacro("__Bitrig__"); 488 DefineStd(Builder, "unix", Opts); 489 Builder.defineMacro("__ELF__"); 490 if (Opts.POSIXThreads) 491 Builder.defineMacro("_REENTRANT"); 492 493 switch (Triple.getArch()) { 494 default: 495 break; 496 case llvm::Triple::arm: 497 case llvm::Triple::armeb: 498 case llvm::Triple::thumb: 499 case llvm::Triple::thumbeb: 500 Builder.defineMacro("__ARM_DWARF_EH__"); 501 break; 502 } 503 } 504 public: 505 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 506 this->UserLabelPrefix = ""; 507 this->MCountName = "__mcount"; 508 } 509 }; 510 511 // PSP Target 512 template<typename Target> 513 class PSPTargetInfo : public OSTargetInfo<Target> { 514 protected: 515 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 516 MacroBuilder &Builder) const override { 517 // PSP defines; list based on the output of the pspdev gcc toolchain. 518 Builder.defineMacro("PSP"); 519 Builder.defineMacro("_PSP"); 520 Builder.defineMacro("__psp__"); 521 Builder.defineMacro("__ELF__"); 522 } 523 public: 524 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 525 this->UserLabelPrefix = ""; 526 } 527 }; 528 529 // PS3 PPU Target 530 template<typename Target> 531 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 532 protected: 533 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 534 MacroBuilder &Builder) const override { 535 // PS3 PPU defines. 536 Builder.defineMacro("__PPC__"); 537 Builder.defineMacro("__PPU__"); 538 Builder.defineMacro("__CELLOS_LV2__"); 539 Builder.defineMacro("__ELF__"); 540 Builder.defineMacro("__LP32__"); 541 Builder.defineMacro("_ARCH_PPC64"); 542 Builder.defineMacro("__powerpc64__"); 543 } 544 public: 545 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 546 this->UserLabelPrefix = ""; 547 this->LongWidth = this->LongAlign = 32; 548 this->PointerWidth = this->PointerAlign = 32; 549 this->IntMaxType = TargetInfo::SignedLongLong; 550 this->Int64Type = TargetInfo::SignedLongLong; 551 this->SizeType = TargetInfo::UnsignedInt; 552 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64"; 553 } 554 }; 555 556 template <typename Target> 557 class PS4OSTargetInfo : public OSTargetInfo<Target> { 558 protected: 559 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 560 MacroBuilder &Builder) const override { 561 Builder.defineMacro("__FreeBSD__", "9"); 562 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 563 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 564 DefineStd(Builder, "unix", Opts); 565 Builder.defineMacro("__ELF__"); 566 Builder.defineMacro("__PS4__"); 567 } 568 public: 569 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 570 this->WCharType = this->UnsignedShort; 571 572 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 573 this->MaxTLSAlign = 256; 574 this->UserLabelPrefix = ""; 575 576 switch (Triple.getArch()) { 577 default: 578 case llvm::Triple::x86_64: 579 this->MCountName = ".mcount"; 580 break; 581 } 582 } 583 }; 584 585 // Solaris target 586 template<typename Target> 587 class SolarisTargetInfo : public OSTargetInfo<Target> { 588 protected: 589 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 590 MacroBuilder &Builder) const override { 591 DefineStd(Builder, "sun", Opts); 592 DefineStd(Builder, "unix", Opts); 593 Builder.defineMacro("__ELF__"); 594 Builder.defineMacro("__svr4__"); 595 Builder.defineMacro("__SVR4"); 596 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 597 // newer, but to 500 for everything else. feature_test.h has a check to 598 // ensure that you are not using C99 with an old version of X/Open or C89 599 // with a new version. 600 if (Opts.C99) 601 Builder.defineMacro("_XOPEN_SOURCE", "600"); 602 else 603 Builder.defineMacro("_XOPEN_SOURCE", "500"); 604 if (Opts.CPlusPlus) 605 Builder.defineMacro("__C99FEATURES__"); 606 Builder.defineMacro("_LARGEFILE_SOURCE"); 607 Builder.defineMacro("_LARGEFILE64_SOURCE"); 608 Builder.defineMacro("__EXTENSIONS__"); 609 Builder.defineMacro("_REENTRANT"); 610 } 611 public: 612 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 613 this->UserLabelPrefix = ""; 614 this->WCharType = this->SignedInt; 615 // FIXME: WIntType should be SignedLong 616 } 617 }; 618 619 // Windows target 620 template<typename Target> 621 class WindowsTargetInfo : public OSTargetInfo<Target> { 622 protected: 623 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 624 MacroBuilder &Builder) const override { 625 Builder.defineMacro("_WIN32"); 626 } 627 void getVisualStudioDefines(const LangOptions &Opts, 628 MacroBuilder &Builder) const { 629 if (Opts.CPlusPlus) { 630 if (Opts.RTTIData) 631 Builder.defineMacro("_CPPRTTI"); 632 633 if (Opts.CXXExceptions) 634 Builder.defineMacro("_CPPUNWIND"); 635 } 636 637 if (Opts.Bool) 638 Builder.defineMacro("__BOOL_DEFINED"); 639 640 if (!Opts.CharIsSigned) 641 Builder.defineMacro("_CHAR_UNSIGNED"); 642 643 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 644 // but it works for now. 645 if (Opts.POSIXThreads) 646 Builder.defineMacro("_MT"); 647 648 if (Opts.MSCompatibilityVersion) { 649 Builder.defineMacro("_MSC_VER", 650 Twine(Opts.MSCompatibilityVersion / 100000)); 651 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 652 // FIXME We cannot encode the revision information into 32-bits 653 Builder.defineMacro("_MSC_BUILD", Twine(1)); 654 655 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 656 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 657 } 658 659 if (Opts.MicrosoftExt) { 660 Builder.defineMacro("_MSC_EXTENSIONS"); 661 662 if (Opts.CPlusPlus11) { 663 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 664 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 665 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 666 } 667 } 668 669 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 670 } 671 672 public: 673 WindowsTargetInfo(const llvm::Triple &Triple) 674 : OSTargetInfo<Target>(Triple) {} 675 }; 676 677 template <typename Target> 678 class NaClTargetInfo : public OSTargetInfo<Target> { 679 protected: 680 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 681 MacroBuilder &Builder) const override { 682 if (Opts.POSIXThreads) 683 Builder.defineMacro("_REENTRANT"); 684 if (Opts.CPlusPlus) 685 Builder.defineMacro("_GNU_SOURCE"); 686 687 DefineStd(Builder, "unix", Opts); 688 Builder.defineMacro("__ELF__"); 689 Builder.defineMacro("__native_client__"); 690 } 691 692 public: 693 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 694 this->UserLabelPrefix = ""; 695 this->LongAlign = 32; 696 this->LongWidth = 32; 697 this->PointerAlign = 32; 698 this->PointerWidth = 32; 699 this->IntMaxType = TargetInfo::SignedLongLong; 700 this->Int64Type = TargetInfo::SignedLongLong; 701 this->DoubleAlign = 64; 702 this->LongDoubleWidth = 64; 703 this->LongDoubleAlign = 64; 704 this->LongLongWidth = 64; 705 this->LongLongAlign = 64; 706 this->SizeType = TargetInfo::UnsignedInt; 707 this->PtrDiffType = TargetInfo::SignedInt; 708 this->IntPtrType = TargetInfo::SignedInt; 709 // RegParmMax is inherited from the underlying architecture 710 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 711 if (Triple.getArch() == llvm::Triple::arm) { 712 // Handled in ARM's setABI(). 713 } else if (Triple.getArch() == llvm::Triple::x86) { 714 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 715 } else if (Triple.getArch() == llvm::Triple::x86_64) { 716 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 717 } else if (Triple.getArch() == llvm::Triple::mipsel) { 718 // Handled on mips' setDataLayoutString. 719 } else { 720 assert(Triple.getArch() == llvm::Triple::le32); 721 this->DataLayoutString = "e-p:32:32-i64:64"; 722 } 723 } 724 }; 725 726 // WebAssembly target 727 template <typename Target> 728 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 729 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 730 MacroBuilder &Builder) const final { 731 // A common platform macro. 732 if (Opts.POSIXThreads) 733 Builder.defineMacro("_REENTRANT"); 734 // Follow g++ convention and predefine _GNU_SOURCE for C++. 735 if (Opts.CPlusPlus) 736 Builder.defineMacro("_GNU_SOURCE"); 737 } 738 739 // As an optimization, group static init code together in a section. 740 const char *getStaticInitSectionSpecifier() const final { 741 return ".text.__startup"; 742 } 743 744 public: 745 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 746 : OSTargetInfo<Target>(Triple) { 747 this->MCountName = "__mcount"; 748 this->UserLabelPrefix = ""; 749 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 750 } 751 }; 752 753 //===----------------------------------------------------------------------===// 754 // Specific target implementations. 755 //===----------------------------------------------------------------------===// 756 757 // PPC abstract base class 758 class PPCTargetInfo : public TargetInfo { 759 static const Builtin::Info BuiltinInfo[]; 760 static const char * const GCCRegNames[]; 761 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 762 std::string CPU; 763 764 // Target cpu features. 765 bool HasVSX; 766 bool HasP8Vector; 767 bool HasP8Crypto; 768 bool HasDirectMove; 769 bool HasQPX; 770 bool HasHTM; 771 bool HasBPERMD; 772 bool HasExtDiv; 773 774 protected: 775 std::string ABI; 776 777 public: 778 PPCTargetInfo(const llvm::Triple &Triple) 779 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 780 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 781 HasBPERMD(false), HasExtDiv(false) { 782 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 783 SimdDefaultAlign = 128; 784 LongDoubleWidth = LongDoubleAlign = 128; 785 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 786 } 787 788 /// \brief Flags for architecture specific defines. 789 typedef enum { 790 ArchDefineNone = 0, 791 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 792 ArchDefinePpcgr = 1 << 1, 793 ArchDefinePpcsq = 1 << 2, 794 ArchDefine440 = 1 << 3, 795 ArchDefine603 = 1 << 4, 796 ArchDefine604 = 1 << 5, 797 ArchDefinePwr4 = 1 << 6, 798 ArchDefinePwr5 = 1 << 7, 799 ArchDefinePwr5x = 1 << 8, 800 ArchDefinePwr6 = 1 << 9, 801 ArchDefinePwr6x = 1 << 10, 802 ArchDefinePwr7 = 1 << 11, 803 ArchDefinePwr8 = 1 << 12, 804 ArchDefineA2 = 1 << 13, 805 ArchDefineA2q = 1 << 14 806 } ArchDefineTypes; 807 808 // Note: GCC recognizes the following additional cpus: 809 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 810 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 811 // titan, rs64. 812 bool setCPU(const std::string &Name) override { 813 bool CPUKnown = llvm::StringSwitch<bool>(Name) 814 .Case("generic", true) 815 .Case("440", true) 816 .Case("450", true) 817 .Case("601", true) 818 .Case("602", true) 819 .Case("603", true) 820 .Case("603e", true) 821 .Case("603ev", true) 822 .Case("604", true) 823 .Case("604e", true) 824 .Case("620", true) 825 .Case("630", true) 826 .Case("g3", true) 827 .Case("7400", true) 828 .Case("g4", true) 829 .Case("7450", true) 830 .Case("g4+", true) 831 .Case("750", true) 832 .Case("970", true) 833 .Case("g5", true) 834 .Case("a2", true) 835 .Case("a2q", true) 836 .Case("e500mc", true) 837 .Case("e5500", true) 838 .Case("power3", true) 839 .Case("pwr3", true) 840 .Case("power4", true) 841 .Case("pwr4", true) 842 .Case("power5", true) 843 .Case("pwr5", true) 844 .Case("power5x", true) 845 .Case("pwr5x", true) 846 .Case("power6", true) 847 .Case("pwr6", true) 848 .Case("power6x", true) 849 .Case("pwr6x", true) 850 .Case("power7", true) 851 .Case("pwr7", true) 852 .Case("power8", true) 853 .Case("pwr8", true) 854 .Case("powerpc", true) 855 .Case("ppc", true) 856 .Case("powerpc64", true) 857 .Case("ppc64", true) 858 .Case("powerpc64le", true) 859 .Case("ppc64le", true) 860 .Default(false); 861 862 if (CPUKnown) 863 CPU = Name; 864 865 return CPUKnown; 866 } 867 868 869 StringRef getABI() const override { return ABI; } 870 871 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 872 return llvm::makeArrayRef(BuiltinInfo, 873 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 874 } 875 876 bool isCLZForZeroUndef() const override { return false; } 877 878 void getTargetDefines(const LangOptions &Opts, 879 MacroBuilder &Builder) const override; 880 881 bool 882 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 883 StringRef CPU, 884 const std::vector<std::string> &FeaturesVec) const override; 885 886 bool handleTargetFeatures(std::vector<std::string> &Features, 887 DiagnosticsEngine &Diags) override; 888 bool hasFeature(StringRef Feature) const override; 889 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 890 bool Enabled) const override; 891 892 ArrayRef<const char *> getGCCRegNames() const override; 893 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 894 bool validateAsmConstraint(const char *&Name, 895 TargetInfo::ConstraintInfo &Info) const override { 896 switch (*Name) { 897 default: return false; 898 case 'O': // Zero 899 break; 900 case 'b': // Base register 901 case 'f': // Floating point register 902 Info.setAllowsRegister(); 903 break; 904 // FIXME: The following are added to allow parsing. 905 // I just took a guess at what the actions should be. 906 // Also, is more specific checking needed? I.e. specific registers? 907 case 'd': // Floating point register (containing 64-bit value) 908 case 'v': // Altivec vector register 909 Info.setAllowsRegister(); 910 break; 911 case 'w': 912 switch (Name[1]) { 913 case 'd':// VSX vector register to hold vector double data 914 case 'f':// VSX vector register to hold vector float data 915 case 's':// VSX vector register to hold scalar float data 916 case 'a':// Any VSX register 917 case 'c':// An individual CR bit 918 break; 919 default: 920 return false; 921 } 922 Info.setAllowsRegister(); 923 Name++; // Skip over 'w'. 924 break; 925 case 'h': // `MQ', `CTR', or `LINK' register 926 case 'q': // `MQ' register 927 case 'c': // `CTR' register 928 case 'l': // `LINK' register 929 case 'x': // `CR' register (condition register) number 0 930 case 'y': // `CR' register (condition register) 931 case 'z': // `XER[CA]' carry bit (part of the XER register) 932 Info.setAllowsRegister(); 933 break; 934 case 'I': // Signed 16-bit constant 935 case 'J': // Unsigned 16-bit constant shifted left 16 bits 936 // (use `L' instead for SImode constants) 937 case 'K': // Unsigned 16-bit constant 938 case 'L': // Signed 16-bit constant shifted left 16 bits 939 case 'M': // Constant larger than 31 940 case 'N': // Exact power of 2 941 case 'P': // Constant whose negation is a signed 16-bit constant 942 case 'G': // Floating point constant that can be loaded into a 943 // register with one instruction per word 944 case 'H': // Integer/Floating point constant that can be loaded 945 // into a register using three instructions 946 break; 947 case 'm': // Memory operand. Note that on PowerPC targets, m can 948 // include addresses that update the base register. It 949 // is therefore only safe to use `m' in an asm statement 950 // if that asm statement accesses the operand exactly once. 951 // The asm statement must also use `%U<opno>' as a 952 // placeholder for the "update" flag in the corresponding 953 // load or store instruction. For example: 954 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 955 // is correct but: 956 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 957 // is not. Use es rather than m if you don't want the base 958 // register to be updated. 959 case 'e': 960 if (Name[1] != 's') 961 return false; 962 // es: A "stable" memory operand; that is, one which does not 963 // include any automodification of the base register. Unlike 964 // `m', this constraint can be used in asm statements that 965 // might access the operand several times, or that might not 966 // access it at all. 967 Info.setAllowsMemory(); 968 Name++; // Skip over 'e'. 969 break; 970 case 'Q': // Memory operand that is an offset from a register (it is 971 // usually better to use `m' or `es' in asm statements) 972 case 'Z': // Memory operand that is an indexed or indirect from a 973 // register (it is usually better to use `m' or `es' in 974 // asm statements) 975 Info.setAllowsMemory(); 976 Info.setAllowsRegister(); 977 break; 978 case 'R': // AIX TOC entry 979 case 'a': // Address operand that is an indexed or indirect from a 980 // register (`p' is preferable for asm statements) 981 case 'S': // Constant suitable as a 64-bit mask operand 982 case 'T': // Constant suitable as a 32-bit mask operand 983 case 'U': // System V Release 4 small data area reference 984 case 't': // AND masks that can be performed by two rldic{l, r} 985 // instructions 986 case 'W': // Vector constant that does not require memory 987 case 'j': // Vector constant that is all zeros. 988 break; 989 // End FIXME. 990 } 991 return true; 992 } 993 std::string convertConstraint(const char *&Constraint) const override { 994 std::string R; 995 switch (*Constraint) { 996 case 'e': 997 case 'w': 998 // Two-character constraint; add "^" hint for later parsing. 999 R = std::string("^") + std::string(Constraint, 2); 1000 Constraint++; 1001 break; 1002 default: 1003 return TargetInfo::convertConstraint(Constraint); 1004 } 1005 return R; 1006 } 1007 const char *getClobbers() const override { 1008 return ""; 1009 } 1010 int getEHDataRegisterNumber(unsigned RegNo) const override { 1011 if (RegNo == 0) return 3; 1012 if (RegNo == 1) return 4; 1013 return -1; 1014 } 1015 1016 bool hasSjLjLowering() const override { 1017 return true; 1018 } 1019 1020 bool useFloat128ManglingForLongDouble() const override { 1021 return LongDoubleWidth == 128 && 1022 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1023 getTriple().isOSBinFormatELF(); 1024 } 1025 }; 1026 1027 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1028 #define BUILTIN(ID, TYPE, ATTRS) \ 1029 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1030 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1031 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1032 #include "clang/Basic/BuiltinsPPC.def" 1033 }; 1034 1035 /// handleTargetFeatures - Perform initialization based on the user 1036 /// configured set of features. 1037 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1038 DiagnosticsEngine &Diags) { 1039 for (const auto &Feature : Features) { 1040 if (Feature == "+vsx") { 1041 HasVSX = true; 1042 } else if (Feature == "+bpermd") { 1043 HasBPERMD = true; 1044 } else if (Feature == "+extdiv") { 1045 HasExtDiv = true; 1046 } else if (Feature == "+power8-vector") { 1047 HasP8Vector = true; 1048 } else if (Feature == "+crypto") { 1049 HasP8Crypto = true; 1050 } else if (Feature == "+direct-move") { 1051 HasDirectMove = true; 1052 } else if (Feature == "+qpx") { 1053 HasQPX = true; 1054 } else if (Feature == "+htm") { 1055 HasHTM = true; 1056 } 1057 // TODO: Finish this list and add an assert that we've handled them 1058 // all. 1059 } 1060 1061 return true; 1062 } 1063 1064 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1065 /// #defines that are not tied to a specific subtarget. 1066 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1067 MacroBuilder &Builder) const { 1068 // Target identification. 1069 Builder.defineMacro("__ppc__"); 1070 Builder.defineMacro("__PPC__"); 1071 Builder.defineMacro("_ARCH_PPC"); 1072 Builder.defineMacro("__powerpc__"); 1073 Builder.defineMacro("__POWERPC__"); 1074 if (PointerWidth == 64) { 1075 Builder.defineMacro("_ARCH_PPC64"); 1076 Builder.defineMacro("__powerpc64__"); 1077 Builder.defineMacro("__ppc64__"); 1078 Builder.defineMacro("__PPC64__"); 1079 } 1080 1081 // Target properties. 1082 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1083 Builder.defineMacro("_LITTLE_ENDIAN"); 1084 } else { 1085 if (getTriple().getOS() != llvm::Triple::NetBSD && 1086 getTriple().getOS() != llvm::Triple::OpenBSD) 1087 Builder.defineMacro("_BIG_ENDIAN"); 1088 } 1089 1090 // ABI options. 1091 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1092 Builder.defineMacro("_CALL_ELF", "1"); 1093 if (ABI == "elfv2") 1094 Builder.defineMacro("_CALL_ELF", "2"); 1095 1096 // Subtarget options. 1097 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1098 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1099 1100 // FIXME: Should be controlled by command line option. 1101 if (LongDoubleWidth == 128) 1102 Builder.defineMacro("__LONG_DOUBLE_128__"); 1103 1104 if (Opts.AltiVec) { 1105 Builder.defineMacro("__VEC__", "10206"); 1106 Builder.defineMacro("__ALTIVEC__"); 1107 } 1108 1109 // CPU identification. 1110 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1111 .Case("440", ArchDefineName) 1112 .Case("450", ArchDefineName | ArchDefine440) 1113 .Case("601", ArchDefineName) 1114 .Case("602", ArchDefineName | ArchDefinePpcgr) 1115 .Case("603", ArchDefineName | ArchDefinePpcgr) 1116 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1117 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1118 .Case("604", ArchDefineName | ArchDefinePpcgr) 1119 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1120 .Case("620", ArchDefineName | ArchDefinePpcgr) 1121 .Case("630", ArchDefineName | ArchDefinePpcgr) 1122 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1123 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1124 .Case("750", ArchDefineName | ArchDefinePpcgr) 1125 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1126 | ArchDefinePpcsq) 1127 .Case("a2", ArchDefineA2) 1128 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1129 .Case("pwr3", ArchDefinePpcgr) 1130 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1131 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1132 | ArchDefinePpcsq) 1133 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1134 | ArchDefinePpcgr | ArchDefinePpcsq) 1135 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1136 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1137 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1138 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1139 | ArchDefinePpcsq) 1140 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1141 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1142 | ArchDefinePpcgr | ArchDefinePpcsq) 1143 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1144 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1145 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1146 .Case("power3", ArchDefinePpcgr) 1147 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1148 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1149 | ArchDefinePpcsq) 1150 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1151 | ArchDefinePpcgr | ArchDefinePpcsq) 1152 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1153 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1154 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1155 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1156 | ArchDefinePpcsq) 1157 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1158 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1159 | ArchDefinePpcgr | ArchDefinePpcsq) 1160 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1161 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1162 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1163 .Default(ArchDefineNone); 1164 1165 if (defs & ArchDefineName) 1166 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1167 if (defs & ArchDefinePpcgr) 1168 Builder.defineMacro("_ARCH_PPCGR"); 1169 if (defs & ArchDefinePpcsq) 1170 Builder.defineMacro("_ARCH_PPCSQ"); 1171 if (defs & ArchDefine440) 1172 Builder.defineMacro("_ARCH_440"); 1173 if (defs & ArchDefine603) 1174 Builder.defineMacro("_ARCH_603"); 1175 if (defs & ArchDefine604) 1176 Builder.defineMacro("_ARCH_604"); 1177 if (defs & ArchDefinePwr4) 1178 Builder.defineMacro("_ARCH_PWR4"); 1179 if (defs & ArchDefinePwr5) 1180 Builder.defineMacro("_ARCH_PWR5"); 1181 if (defs & ArchDefinePwr5x) 1182 Builder.defineMacro("_ARCH_PWR5X"); 1183 if (defs & ArchDefinePwr6) 1184 Builder.defineMacro("_ARCH_PWR6"); 1185 if (defs & ArchDefinePwr6x) 1186 Builder.defineMacro("_ARCH_PWR6X"); 1187 if (defs & ArchDefinePwr7) 1188 Builder.defineMacro("_ARCH_PWR7"); 1189 if (defs & ArchDefinePwr8) 1190 Builder.defineMacro("_ARCH_PWR8"); 1191 if (defs & ArchDefineA2) 1192 Builder.defineMacro("_ARCH_A2"); 1193 if (defs & ArchDefineA2q) { 1194 Builder.defineMacro("_ARCH_A2Q"); 1195 Builder.defineMacro("_ARCH_QP"); 1196 } 1197 1198 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1199 Builder.defineMacro("__bg__"); 1200 Builder.defineMacro("__THW_BLUEGENE__"); 1201 Builder.defineMacro("__bgq__"); 1202 Builder.defineMacro("__TOS_BGQ__"); 1203 } 1204 1205 if (HasVSX) 1206 Builder.defineMacro("__VSX__"); 1207 if (HasP8Vector) 1208 Builder.defineMacro("__POWER8_VECTOR__"); 1209 if (HasP8Crypto) 1210 Builder.defineMacro("__CRYPTO__"); 1211 if (HasHTM) 1212 Builder.defineMacro("__HTM__"); 1213 1214 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1215 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1216 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1217 if (PointerWidth == 64) 1218 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1219 1220 // FIXME: The following are not yet generated here by Clang, but are 1221 // generated by GCC: 1222 // 1223 // _SOFT_FLOAT_ 1224 // __RECIP_PRECISION__ 1225 // __APPLE_ALTIVEC__ 1226 // __RECIP__ 1227 // __RECIPF__ 1228 // __RSQRTE__ 1229 // __RSQRTEF__ 1230 // _SOFT_DOUBLE_ 1231 // __NO_LWSYNC__ 1232 // __HAVE_BSWAP__ 1233 // __LONGDOUBLE128 1234 // __CMODEL_MEDIUM__ 1235 // __CMODEL_LARGE__ 1236 // _CALL_SYSV 1237 // _CALL_DARWIN 1238 // __NO_FPRS__ 1239 } 1240 1241 // Handle explicit options being passed to the compiler here: if we've 1242 // explicitly turned off vsx and turned on power8-vector or direct-move then 1243 // go ahead and error since the customer has expressed a somewhat incompatible 1244 // set of options. 1245 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1246 const std::vector<std::string> &FeaturesVec) { 1247 1248 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1249 FeaturesVec.end()) { 1250 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1251 FeaturesVec.end()) { 1252 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1253 << "-mno-vsx"; 1254 return false; 1255 } 1256 1257 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1258 FeaturesVec.end()) { 1259 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1260 << "-mno-vsx"; 1261 return false; 1262 } 1263 } 1264 1265 return true; 1266 } 1267 1268 bool PPCTargetInfo::initFeatureMap( 1269 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1270 const std::vector<std::string> &FeaturesVec) const { 1271 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1272 .Case("7400", true) 1273 .Case("g4", true) 1274 .Case("7450", true) 1275 .Case("g4+", true) 1276 .Case("970", true) 1277 .Case("g5", true) 1278 .Case("pwr6", true) 1279 .Case("pwr7", true) 1280 .Case("pwr8", true) 1281 .Case("ppc64", true) 1282 .Case("ppc64le", true) 1283 .Default(false); 1284 1285 Features["qpx"] = (CPU == "a2q"); 1286 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1287 .Case("ppc64le", true) 1288 .Case("pwr8", true) 1289 .Default(false); 1290 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1291 .Case("ppc64le", true) 1292 .Case("pwr8", true) 1293 .Default(false); 1294 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1295 .Case("ppc64le", true) 1296 .Case("pwr8", true) 1297 .Case("pwr7", true) 1298 .Default(false); 1299 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1300 .Case("ppc64le", true) 1301 .Case("pwr8", true) 1302 .Case("pwr7", true) 1303 .Default(false); 1304 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1305 .Case("ppc64le", true) 1306 .Case("pwr8", true) 1307 .Default(false); 1308 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1309 .Case("ppc64le", true) 1310 .Case("pwr8", true) 1311 .Case("pwr7", true) 1312 .Default(false); 1313 1314 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1315 return false; 1316 1317 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1318 } 1319 1320 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1321 return llvm::StringSwitch<bool>(Feature) 1322 .Case("powerpc", true) 1323 .Case("vsx", HasVSX) 1324 .Case("power8-vector", HasP8Vector) 1325 .Case("crypto", HasP8Crypto) 1326 .Case("direct-move", HasDirectMove) 1327 .Case("qpx", HasQPX) 1328 .Case("htm", HasHTM) 1329 .Case("bpermd", HasBPERMD) 1330 .Case("extdiv", HasExtDiv) 1331 .Default(false); 1332 } 1333 1334 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1335 StringRef Name, bool Enabled) const { 1336 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1337 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1338 // incompatible options. 1339 if (Enabled) { 1340 if (Name == "vsx") { 1341 Features[Name] = true; 1342 } else if (Name == "direct-move") { 1343 Features[Name] = Features["vsx"] = true; 1344 } else if (Name == "power8-vector") { 1345 Features[Name] = Features["vsx"] = true; 1346 } else { 1347 Features[Name] = true; 1348 } 1349 } else { 1350 if (Name == "vsx") { 1351 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1352 false; 1353 } else { 1354 Features[Name] = false; 1355 } 1356 } 1357 } 1358 1359 const char * const PPCTargetInfo::GCCRegNames[] = { 1360 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1361 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1362 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1363 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1364 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1365 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1366 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1367 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1368 "mq", "lr", "ctr", "ap", 1369 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1370 "xer", 1371 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1372 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1373 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1374 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1375 "vrsave", "vscr", 1376 "spe_acc", "spefscr", 1377 "sfp" 1378 }; 1379 1380 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1381 return llvm::makeArrayRef(GCCRegNames); 1382 } 1383 1384 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1385 // While some of these aliases do map to different registers 1386 // they still share the same register name. 1387 { { "0" }, "r0" }, 1388 { { "1"}, "r1" }, 1389 { { "2" }, "r2" }, 1390 { { "3" }, "r3" }, 1391 { { "4" }, "r4" }, 1392 { { "5" }, "r5" }, 1393 { { "6" }, "r6" }, 1394 { { "7" }, "r7" }, 1395 { { "8" }, "r8" }, 1396 { { "9" }, "r9" }, 1397 { { "10" }, "r10" }, 1398 { { "11" }, "r11" }, 1399 { { "12" }, "r12" }, 1400 { { "13" }, "r13" }, 1401 { { "14" }, "r14" }, 1402 { { "15" }, "r15" }, 1403 { { "16" }, "r16" }, 1404 { { "17" }, "r17" }, 1405 { { "18" }, "r18" }, 1406 { { "19" }, "r19" }, 1407 { { "20" }, "r20" }, 1408 { { "21" }, "r21" }, 1409 { { "22" }, "r22" }, 1410 { { "23" }, "r23" }, 1411 { { "24" }, "r24" }, 1412 { { "25" }, "r25" }, 1413 { { "26" }, "r26" }, 1414 { { "27" }, "r27" }, 1415 { { "28" }, "r28" }, 1416 { { "29" }, "r29" }, 1417 { { "30" }, "r30" }, 1418 { { "31" }, "r31" }, 1419 { { "fr0" }, "f0" }, 1420 { { "fr1" }, "f1" }, 1421 { { "fr2" }, "f2" }, 1422 { { "fr3" }, "f3" }, 1423 { { "fr4" }, "f4" }, 1424 { { "fr5" }, "f5" }, 1425 { { "fr6" }, "f6" }, 1426 { { "fr7" }, "f7" }, 1427 { { "fr8" }, "f8" }, 1428 { { "fr9" }, "f9" }, 1429 { { "fr10" }, "f10" }, 1430 { { "fr11" }, "f11" }, 1431 { { "fr12" }, "f12" }, 1432 { { "fr13" }, "f13" }, 1433 { { "fr14" }, "f14" }, 1434 { { "fr15" }, "f15" }, 1435 { { "fr16" }, "f16" }, 1436 { { "fr17" }, "f17" }, 1437 { { "fr18" }, "f18" }, 1438 { { "fr19" }, "f19" }, 1439 { { "fr20" }, "f20" }, 1440 { { "fr21" }, "f21" }, 1441 { { "fr22" }, "f22" }, 1442 { { "fr23" }, "f23" }, 1443 { { "fr24" }, "f24" }, 1444 { { "fr25" }, "f25" }, 1445 { { "fr26" }, "f26" }, 1446 { { "fr27" }, "f27" }, 1447 { { "fr28" }, "f28" }, 1448 { { "fr29" }, "f29" }, 1449 { { "fr30" }, "f30" }, 1450 { { "fr31" }, "f31" }, 1451 { { "cc" }, "cr0" }, 1452 }; 1453 1454 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1455 return llvm::makeArrayRef(GCCRegAliases); 1456 } 1457 1458 class PPC32TargetInfo : public PPCTargetInfo { 1459 public: 1460 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1461 DataLayoutString = "E-m:e-p:32:32-i64:64-n32"; 1462 1463 switch (getTriple().getOS()) { 1464 case llvm::Triple::Linux: 1465 case llvm::Triple::FreeBSD: 1466 case llvm::Triple::NetBSD: 1467 SizeType = UnsignedInt; 1468 PtrDiffType = SignedInt; 1469 IntPtrType = SignedInt; 1470 break; 1471 default: 1472 break; 1473 } 1474 1475 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1476 LongDoubleWidth = LongDoubleAlign = 64; 1477 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1478 } 1479 1480 // PPC32 supports atomics up to 4 bytes. 1481 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1482 } 1483 1484 BuiltinVaListKind getBuiltinVaListKind() const override { 1485 // This is the ELF definition, and is overridden by the Darwin sub-target 1486 return TargetInfo::PowerABIBuiltinVaList; 1487 } 1488 }; 1489 1490 // Note: ABI differences may eventually require us to have a separate 1491 // TargetInfo for little endian. 1492 class PPC64TargetInfo : public PPCTargetInfo { 1493 public: 1494 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1495 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1496 IntMaxType = SignedLong; 1497 Int64Type = SignedLong; 1498 1499 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1500 DataLayoutString = "e-m:e-i64:64-n32:64"; 1501 ABI = "elfv2"; 1502 } else { 1503 DataLayoutString = "E-m:e-i64:64-n32:64"; 1504 ABI = "elfv1"; 1505 } 1506 1507 switch (getTriple().getOS()) { 1508 case llvm::Triple::FreeBSD: 1509 LongDoubleWidth = LongDoubleAlign = 64; 1510 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1511 break; 1512 case llvm::Triple::NetBSD: 1513 IntMaxType = SignedLongLong; 1514 Int64Type = SignedLongLong; 1515 break; 1516 default: 1517 break; 1518 } 1519 1520 // PPC64 supports atomics up to 8 bytes. 1521 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1522 } 1523 BuiltinVaListKind getBuiltinVaListKind() const override { 1524 return TargetInfo::CharPtrBuiltinVaList; 1525 } 1526 // PPC64 Linux-specific ABI options. 1527 bool setABI(const std::string &Name) override { 1528 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1529 ABI = Name; 1530 return true; 1531 } 1532 return false; 1533 } 1534 }; 1535 1536 class DarwinPPC32TargetInfo : 1537 public DarwinTargetInfo<PPC32TargetInfo> { 1538 public: 1539 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1540 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1541 HasAlignMac68kSupport = true; 1542 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1543 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1544 LongLongAlign = 32; 1545 SuitableAlign = 128; 1546 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32"; 1547 } 1548 BuiltinVaListKind getBuiltinVaListKind() const override { 1549 return TargetInfo::CharPtrBuiltinVaList; 1550 } 1551 }; 1552 1553 class DarwinPPC64TargetInfo : 1554 public DarwinTargetInfo<PPC64TargetInfo> { 1555 public: 1556 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1557 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1558 HasAlignMac68kSupport = true; 1559 SuitableAlign = 128; 1560 DataLayoutString = "E-m:o-i64:64-n32:64"; 1561 } 1562 }; 1563 1564 static const unsigned NVPTXAddrSpaceMap[] = { 1565 1, // opencl_global 1566 3, // opencl_local 1567 4, // opencl_constant 1568 // FIXME: generic has to be added to the target 1569 0, // opencl_generic 1570 1, // cuda_device 1571 4, // cuda_constant 1572 3, // cuda_shared 1573 }; 1574 1575 class NVPTXTargetInfo : public TargetInfo { 1576 static const char *const GCCRegNames[]; 1577 static const Builtin::Info BuiltinInfo[]; 1578 1579 // The GPU profiles supported by the NVPTX backend 1580 enum GPUKind { 1581 GK_NONE, 1582 GK_SM20, 1583 GK_SM21, 1584 GK_SM30, 1585 GK_SM35, 1586 GK_SM37, 1587 } GPU; 1588 1589 public: 1590 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1591 BigEndian = false; 1592 TLSSupported = false; 1593 LongWidth = LongAlign = 64; 1594 AddrSpaceMap = &NVPTXAddrSpaceMap; 1595 UseAddrSpaceMapMangling = true; 1596 // Define available target features 1597 // These must be defined in sorted order! 1598 NoAsmVariants = true; 1599 // Set the default GPU to sm20 1600 GPU = GK_SM20; 1601 } 1602 void getTargetDefines(const LangOptions &Opts, 1603 MacroBuilder &Builder) const override { 1604 Builder.defineMacro("__PTX__"); 1605 Builder.defineMacro("__NVPTX__"); 1606 if (Opts.CUDAIsDevice) { 1607 // Set __CUDA_ARCH__ for the GPU specified. 1608 std::string CUDAArchCode; 1609 switch (GPU) { 1610 case GK_SM20: 1611 CUDAArchCode = "200"; 1612 break; 1613 case GK_SM21: 1614 CUDAArchCode = "210"; 1615 break; 1616 case GK_SM30: 1617 CUDAArchCode = "300"; 1618 break; 1619 case GK_SM35: 1620 CUDAArchCode = "350"; 1621 break; 1622 case GK_SM37: 1623 CUDAArchCode = "370"; 1624 break; 1625 default: 1626 llvm_unreachable("Unhandled target CPU"); 1627 } 1628 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1629 } 1630 } 1631 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1632 return llvm::makeArrayRef(BuiltinInfo, 1633 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1634 } 1635 bool hasFeature(StringRef Feature) const override { 1636 return Feature == "ptx" || Feature == "nvptx"; 1637 } 1638 1639 ArrayRef<const char *> getGCCRegNames() const override; 1640 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1641 // No aliases. 1642 return None; 1643 } 1644 bool validateAsmConstraint(const char *&Name, 1645 TargetInfo::ConstraintInfo &Info) const override { 1646 switch (*Name) { 1647 default: 1648 return false; 1649 case 'c': 1650 case 'h': 1651 case 'r': 1652 case 'l': 1653 case 'f': 1654 case 'd': 1655 Info.setAllowsRegister(); 1656 return true; 1657 } 1658 } 1659 const char *getClobbers() const override { 1660 // FIXME: Is this really right? 1661 return ""; 1662 } 1663 BuiltinVaListKind getBuiltinVaListKind() const override { 1664 // FIXME: implement 1665 return TargetInfo::CharPtrBuiltinVaList; 1666 } 1667 bool setCPU(const std::string &Name) override { 1668 GPU = llvm::StringSwitch<GPUKind>(Name) 1669 .Case("sm_20", GK_SM20) 1670 .Case("sm_21", GK_SM21) 1671 .Case("sm_30", GK_SM30) 1672 .Case("sm_35", GK_SM35) 1673 .Case("sm_37", GK_SM37) 1674 .Default(GK_NONE); 1675 1676 return GPU != GK_NONE; 1677 } 1678 }; 1679 1680 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1681 #define BUILTIN(ID, TYPE, ATTRS) \ 1682 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1683 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1684 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1685 #include "clang/Basic/BuiltinsNVPTX.def" 1686 }; 1687 1688 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1689 1690 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1691 return llvm::makeArrayRef(GCCRegNames); 1692 } 1693 1694 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1695 public: 1696 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1697 LongWidth = LongAlign = 32; 1698 PointerWidth = PointerAlign = 32; 1699 SizeType = TargetInfo::UnsignedInt; 1700 PtrDiffType = TargetInfo::SignedInt; 1701 IntPtrType = TargetInfo::SignedInt; 1702 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1703 } 1704 }; 1705 1706 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1707 public: 1708 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1709 PointerWidth = PointerAlign = 64; 1710 SizeType = TargetInfo::UnsignedLong; 1711 PtrDiffType = TargetInfo::SignedLong; 1712 IntPtrType = TargetInfo::SignedLong; 1713 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1714 } 1715 }; 1716 1717 static const unsigned AMDGPUAddrSpaceMap[] = { 1718 1, // opencl_global 1719 3, // opencl_local 1720 2, // opencl_constant 1721 4, // opencl_generic 1722 1, // cuda_device 1723 2, // cuda_constant 1724 3 // cuda_shared 1725 }; 1726 1727 // If you edit the description strings, make sure you update 1728 // getPointerWidthV(). 1729 1730 static const char *const DataLayoutStringR600 = 1731 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1732 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1733 1734 static const char *const DataLayoutStringR600DoubleOps = 1735 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1736 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1737 1738 static const char *const DataLayoutStringSI = 1739 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1740 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1741 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1742 1743 class AMDGPUTargetInfo : public TargetInfo { 1744 static const Builtin::Info BuiltinInfo[]; 1745 static const char * const GCCRegNames[]; 1746 1747 /// \brief The GPU profiles supported by the AMDGPU target. 1748 enum GPUKind { 1749 GK_NONE, 1750 GK_R600, 1751 GK_R600_DOUBLE_OPS, 1752 GK_R700, 1753 GK_R700_DOUBLE_OPS, 1754 GK_EVERGREEN, 1755 GK_EVERGREEN_DOUBLE_OPS, 1756 GK_NORTHERN_ISLANDS, 1757 GK_CAYMAN, 1758 GK_SOUTHERN_ISLANDS, 1759 GK_SEA_ISLANDS, 1760 GK_VOLCANIC_ISLANDS 1761 } GPU; 1762 1763 bool hasFP64:1; 1764 bool hasFMAF:1; 1765 bool hasLDEXPF:1; 1766 1767 public: 1768 AMDGPUTargetInfo(const llvm::Triple &Triple) 1769 : TargetInfo(Triple) { 1770 1771 if (Triple.getArch() == llvm::Triple::amdgcn) { 1772 DataLayoutString = DataLayoutStringSI; 1773 GPU = GK_SOUTHERN_ISLANDS; 1774 hasFP64 = true; 1775 hasFMAF = true; 1776 hasLDEXPF = true; 1777 } else { 1778 DataLayoutString = DataLayoutStringR600; 1779 GPU = GK_R600; 1780 hasFP64 = false; 1781 hasFMAF = false; 1782 hasLDEXPF = false; 1783 } 1784 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1785 UseAddrSpaceMapMangling = true; 1786 } 1787 1788 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1789 if (GPU <= GK_CAYMAN) 1790 return 32; 1791 1792 switch(AddrSpace) { 1793 default: 1794 return 64; 1795 case 0: 1796 case 3: 1797 case 5: 1798 return 32; 1799 } 1800 } 1801 1802 const char * getClobbers() const override { 1803 return ""; 1804 } 1805 1806 ArrayRef<const char *> getGCCRegNames() const override; 1807 1808 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1809 return None; 1810 } 1811 1812 bool validateAsmConstraint(const char *&Name, 1813 TargetInfo::ConstraintInfo &info) const override { 1814 return true; 1815 } 1816 1817 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1818 return llvm::makeArrayRef(BuiltinInfo, 1819 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1820 } 1821 1822 void getTargetDefines(const LangOptions &Opts, 1823 MacroBuilder &Builder) const override { 1824 Builder.defineMacro("__R600__"); 1825 if (hasFMAF) 1826 Builder.defineMacro("__HAS_FMAF__"); 1827 if (hasLDEXPF) 1828 Builder.defineMacro("__HAS_LDEXPF__"); 1829 if (hasFP64 && Opts.OpenCL) 1830 Builder.defineMacro("cl_khr_fp64"); 1831 if (Opts.OpenCL) { 1832 if (GPU >= GK_NORTHERN_ISLANDS) { 1833 Builder.defineMacro("cl_khr_byte_addressable_store"); 1834 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1835 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1836 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1837 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1838 } 1839 } 1840 } 1841 1842 BuiltinVaListKind getBuiltinVaListKind() const override { 1843 return TargetInfo::CharPtrBuiltinVaList; 1844 } 1845 1846 bool setCPU(const std::string &Name) override { 1847 GPU = llvm::StringSwitch<GPUKind>(Name) 1848 .Case("r600" , GK_R600) 1849 .Case("rv610", GK_R600) 1850 .Case("rv620", GK_R600) 1851 .Case("rv630", GK_R600) 1852 .Case("rv635", GK_R600) 1853 .Case("rs780", GK_R600) 1854 .Case("rs880", GK_R600) 1855 .Case("rv670", GK_R600_DOUBLE_OPS) 1856 .Case("rv710", GK_R700) 1857 .Case("rv730", GK_R700) 1858 .Case("rv740", GK_R700_DOUBLE_OPS) 1859 .Case("rv770", GK_R700_DOUBLE_OPS) 1860 .Case("palm", GK_EVERGREEN) 1861 .Case("cedar", GK_EVERGREEN) 1862 .Case("sumo", GK_EVERGREEN) 1863 .Case("sumo2", GK_EVERGREEN) 1864 .Case("redwood", GK_EVERGREEN) 1865 .Case("juniper", GK_EVERGREEN) 1866 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1867 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1868 .Case("barts", GK_NORTHERN_ISLANDS) 1869 .Case("turks", GK_NORTHERN_ISLANDS) 1870 .Case("caicos", GK_NORTHERN_ISLANDS) 1871 .Case("cayman", GK_CAYMAN) 1872 .Case("aruba", GK_CAYMAN) 1873 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1874 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1875 .Case("verde", GK_SOUTHERN_ISLANDS) 1876 .Case("oland", GK_SOUTHERN_ISLANDS) 1877 .Case("hainan", GK_SOUTHERN_ISLANDS) 1878 .Case("bonaire", GK_SEA_ISLANDS) 1879 .Case("kabini", GK_SEA_ISLANDS) 1880 .Case("kaveri", GK_SEA_ISLANDS) 1881 .Case("hawaii", GK_SEA_ISLANDS) 1882 .Case("mullins", GK_SEA_ISLANDS) 1883 .Case("tonga", GK_VOLCANIC_ISLANDS) 1884 .Case("iceland", GK_VOLCANIC_ISLANDS) 1885 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1886 .Default(GK_NONE); 1887 1888 if (GPU == GK_NONE) { 1889 return false; 1890 } 1891 1892 // Set the correct data layout 1893 switch (GPU) { 1894 case GK_NONE: 1895 case GK_R600: 1896 case GK_R700: 1897 case GK_EVERGREEN: 1898 case GK_NORTHERN_ISLANDS: 1899 DataLayoutString = DataLayoutStringR600; 1900 hasFP64 = false; 1901 hasFMAF = false; 1902 hasLDEXPF = false; 1903 break; 1904 case GK_R600_DOUBLE_OPS: 1905 case GK_R700_DOUBLE_OPS: 1906 case GK_EVERGREEN_DOUBLE_OPS: 1907 case GK_CAYMAN: 1908 DataLayoutString = DataLayoutStringR600DoubleOps; 1909 hasFP64 = true; 1910 hasFMAF = true; 1911 hasLDEXPF = false; 1912 break; 1913 case GK_SOUTHERN_ISLANDS: 1914 case GK_SEA_ISLANDS: 1915 case GK_VOLCANIC_ISLANDS: 1916 DataLayoutString = DataLayoutStringSI; 1917 hasFP64 = true; 1918 hasFMAF = true; 1919 hasLDEXPF = true; 1920 break; 1921 } 1922 1923 return true; 1924 } 1925 }; 1926 1927 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1928 #define BUILTIN(ID, TYPE, ATTRS) \ 1929 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1930 #include "clang/Basic/BuiltinsAMDGPU.def" 1931 }; 1932 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1933 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1934 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1935 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1936 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1937 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1938 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1939 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1940 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1941 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1942 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1943 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1944 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1945 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1946 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1947 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1948 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1949 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1950 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1951 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1952 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1953 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1954 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1955 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1956 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1957 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1958 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1959 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1960 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1961 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1962 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1963 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1964 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1965 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1966 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1967 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1968 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1969 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1970 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1971 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1972 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1973 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1974 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 1975 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 1976 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 1977 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 1978 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 1979 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 1980 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 1981 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 1982 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 1983 }; 1984 1985 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 1986 return llvm::makeArrayRef(GCCRegNames); 1987 } 1988 1989 // Namespace for x86 abstract base class 1990 const Builtin::Info BuiltinInfo[] = { 1991 #define BUILTIN(ID, TYPE, ATTRS) \ 1992 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1993 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1994 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1995 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 1996 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 1997 #include "clang/Basic/BuiltinsX86.def" 1998 }; 1999 2000 static const char* const GCCRegNames[] = { 2001 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2002 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2003 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2004 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2005 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2006 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2007 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2008 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2009 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2010 }; 2011 2012 const TargetInfo::AddlRegName AddlRegNames[] = { 2013 { { "al", "ah", "eax", "rax" }, 0 }, 2014 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2015 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2016 { { "dl", "dh", "edx", "rdx" }, 1 }, 2017 { { "esi", "rsi" }, 4 }, 2018 { { "edi", "rdi" }, 5 }, 2019 { { "esp", "rsp" }, 7 }, 2020 { { "ebp", "rbp" }, 6 }, 2021 { { "r8d", "r8w", "r8b" }, 38 }, 2022 { { "r9d", "r9w", "r9b" }, 39 }, 2023 { { "r10d", "r10w", "r10b" }, 40 }, 2024 { { "r11d", "r11w", "r11b" }, 41 }, 2025 { { "r12d", "r12w", "r12b" }, 42 }, 2026 { { "r13d", "r13w", "r13b" }, 43 }, 2027 { { "r14d", "r14w", "r14b" }, 44 }, 2028 { { "r15d", "r15w", "r15b" }, 45 }, 2029 }; 2030 2031 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2032 // most of the implementation can be shared. 2033 class X86TargetInfo : public TargetInfo { 2034 enum X86SSEEnum { 2035 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2036 } SSELevel = NoSSE; 2037 enum MMX3DNowEnum { 2038 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2039 } MMX3DNowLevel = NoMMX3DNow; 2040 enum XOPEnum { 2041 NoXOP, 2042 SSE4A, 2043 FMA4, 2044 XOP 2045 } XOPLevel = NoXOP; 2046 2047 bool HasAES = false; 2048 bool HasPCLMUL = false; 2049 bool HasLZCNT = false; 2050 bool HasRDRND = false; 2051 bool HasFSGSBASE = false; 2052 bool HasBMI = false; 2053 bool HasBMI2 = false; 2054 bool HasPOPCNT = false; 2055 bool HasRTM = false; 2056 bool HasPRFCHW = false; 2057 bool HasRDSEED = false; 2058 bool HasADX = false; 2059 bool HasTBM = false; 2060 bool HasFMA = false; 2061 bool HasF16C = false; 2062 bool HasAVX512CD = false; 2063 bool HasAVX512ER = false; 2064 bool HasAVX512PF = false; 2065 bool HasAVX512DQ = false; 2066 bool HasAVX512BW = false; 2067 bool HasAVX512VL = false; 2068 bool HasSHA = false; 2069 bool HasCX16 = false; 2070 bool HasFXSR = false; 2071 bool HasXSAVE = false; 2072 bool HasXSAVEOPT = false; 2073 bool HasXSAVEC = false; 2074 bool HasXSAVES = false; 2075 2076 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2077 /// 2078 /// Each enumeration represents a particular CPU supported by Clang. These 2079 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2080 enum CPUKind { 2081 CK_Generic, 2082 2083 /// \name i386 2084 /// i386-generation processors. 2085 //@{ 2086 CK_i386, 2087 //@} 2088 2089 /// \name i486 2090 /// i486-generation processors. 2091 //@{ 2092 CK_i486, 2093 CK_WinChipC6, 2094 CK_WinChip2, 2095 CK_C3, 2096 //@} 2097 2098 /// \name i586 2099 /// i586-generation processors, P5 microarchitecture based. 2100 //@{ 2101 CK_i586, 2102 CK_Pentium, 2103 CK_PentiumMMX, 2104 //@} 2105 2106 /// \name i686 2107 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2108 //@{ 2109 CK_i686, 2110 CK_PentiumPro, 2111 CK_Pentium2, 2112 CK_Pentium3, 2113 CK_Pentium3M, 2114 CK_PentiumM, 2115 CK_C3_2, 2116 2117 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2118 /// Clang however has some logic to suport this. 2119 // FIXME: Warn, deprecate, and potentially remove this. 2120 CK_Yonah, 2121 //@} 2122 2123 /// \name Netburst 2124 /// Netburst microarchitecture based processors. 2125 //@{ 2126 CK_Pentium4, 2127 CK_Pentium4M, 2128 CK_Prescott, 2129 CK_Nocona, 2130 //@} 2131 2132 /// \name Core 2133 /// Core microarchitecture based processors. 2134 //@{ 2135 CK_Core2, 2136 2137 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2138 /// codename which GCC no longer accepts as an option to -march, but Clang 2139 /// has some logic for recognizing it. 2140 // FIXME: Warn, deprecate, and potentially remove this. 2141 CK_Penryn, 2142 //@} 2143 2144 /// \name Atom 2145 /// Atom processors 2146 //@{ 2147 CK_Bonnell, 2148 CK_Silvermont, 2149 //@} 2150 2151 /// \name Nehalem 2152 /// Nehalem microarchitecture based processors. 2153 CK_Nehalem, 2154 2155 /// \name Westmere 2156 /// Westmere microarchitecture based processors. 2157 CK_Westmere, 2158 2159 /// \name Sandy Bridge 2160 /// Sandy Bridge microarchitecture based processors. 2161 CK_SandyBridge, 2162 2163 /// \name Ivy Bridge 2164 /// Ivy Bridge microarchitecture based processors. 2165 CK_IvyBridge, 2166 2167 /// \name Haswell 2168 /// Haswell microarchitecture based processors. 2169 CK_Haswell, 2170 2171 /// \name Broadwell 2172 /// Broadwell microarchitecture based processors. 2173 CK_Broadwell, 2174 2175 /// \name Skylake 2176 /// Skylake microarchitecture based processors. 2177 CK_Skylake, 2178 2179 /// \name Knights Landing 2180 /// Knights Landing processor. 2181 CK_KNL, 2182 2183 /// \name K6 2184 /// K6 architecture processors. 2185 //@{ 2186 CK_K6, 2187 CK_K6_2, 2188 CK_K6_3, 2189 //@} 2190 2191 /// \name K7 2192 /// K7 architecture processors. 2193 //@{ 2194 CK_Athlon, 2195 CK_AthlonThunderbird, 2196 CK_Athlon4, 2197 CK_AthlonXP, 2198 CK_AthlonMP, 2199 //@} 2200 2201 /// \name K8 2202 /// K8 architecture processors. 2203 //@{ 2204 CK_Athlon64, 2205 CK_Athlon64SSE3, 2206 CK_AthlonFX, 2207 CK_K8, 2208 CK_K8SSE3, 2209 CK_Opteron, 2210 CK_OpteronSSE3, 2211 CK_AMDFAM10, 2212 //@} 2213 2214 /// \name Bobcat 2215 /// Bobcat architecture processors. 2216 //@{ 2217 CK_BTVER1, 2218 CK_BTVER2, 2219 //@} 2220 2221 /// \name Bulldozer 2222 /// Bulldozer architecture processors. 2223 //@{ 2224 CK_BDVER1, 2225 CK_BDVER2, 2226 CK_BDVER3, 2227 CK_BDVER4, 2228 //@} 2229 2230 /// This specification is deprecated and will be removed in the future. 2231 /// Users should prefer \see CK_K8. 2232 // FIXME: Warn on this when the CPU is set to it. 2233 //@{ 2234 CK_x86_64, 2235 //@} 2236 2237 /// \name Geode 2238 /// Geode processors. 2239 //@{ 2240 CK_Geode 2241 //@} 2242 } CPU = CK_Generic; 2243 2244 CPUKind getCPUKind(StringRef CPU) const { 2245 return llvm::StringSwitch<CPUKind>(CPU) 2246 .Case("i386", CK_i386) 2247 .Case("i486", CK_i486) 2248 .Case("winchip-c6", CK_WinChipC6) 2249 .Case("winchip2", CK_WinChip2) 2250 .Case("c3", CK_C3) 2251 .Case("i586", CK_i586) 2252 .Case("pentium", CK_Pentium) 2253 .Case("pentium-mmx", CK_PentiumMMX) 2254 .Case("i686", CK_i686) 2255 .Case("pentiumpro", CK_PentiumPro) 2256 .Case("pentium2", CK_Pentium2) 2257 .Case("pentium3", CK_Pentium3) 2258 .Case("pentium3m", CK_Pentium3M) 2259 .Case("pentium-m", CK_PentiumM) 2260 .Case("c3-2", CK_C3_2) 2261 .Case("yonah", CK_Yonah) 2262 .Case("pentium4", CK_Pentium4) 2263 .Case("pentium4m", CK_Pentium4M) 2264 .Case("prescott", CK_Prescott) 2265 .Case("nocona", CK_Nocona) 2266 .Case("core2", CK_Core2) 2267 .Case("penryn", CK_Penryn) 2268 .Case("bonnell", CK_Bonnell) 2269 .Case("atom", CK_Bonnell) // Legacy name. 2270 .Case("silvermont", CK_Silvermont) 2271 .Case("slm", CK_Silvermont) // Legacy name. 2272 .Case("nehalem", CK_Nehalem) 2273 .Case("corei7", CK_Nehalem) // Legacy name. 2274 .Case("westmere", CK_Westmere) 2275 .Case("sandybridge", CK_SandyBridge) 2276 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2277 .Case("ivybridge", CK_IvyBridge) 2278 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2279 .Case("haswell", CK_Haswell) 2280 .Case("core-avx2", CK_Haswell) // Legacy name. 2281 .Case("broadwell", CK_Broadwell) 2282 .Case("skylake", CK_Skylake) 2283 .Case("skx", CK_Skylake) // Legacy name. 2284 .Case("knl", CK_KNL) 2285 .Case("k6", CK_K6) 2286 .Case("k6-2", CK_K6_2) 2287 .Case("k6-3", CK_K6_3) 2288 .Case("athlon", CK_Athlon) 2289 .Case("athlon-tbird", CK_AthlonThunderbird) 2290 .Case("athlon-4", CK_Athlon4) 2291 .Case("athlon-xp", CK_AthlonXP) 2292 .Case("athlon-mp", CK_AthlonMP) 2293 .Case("athlon64", CK_Athlon64) 2294 .Case("athlon64-sse3", CK_Athlon64SSE3) 2295 .Case("athlon-fx", CK_AthlonFX) 2296 .Case("k8", CK_K8) 2297 .Case("k8-sse3", CK_K8SSE3) 2298 .Case("opteron", CK_Opteron) 2299 .Case("opteron-sse3", CK_OpteronSSE3) 2300 .Case("barcelona", CK_AMDFAM10) 2301 .Case("amdfam10", CK_AMDFAM10) 2302 .Case("btver1", CK_BTVER1) 2303 .Case("btver2", CK_BTVER2) 2304 .Case("bdver1", CK_BDVER1) 2305 .Case("bdver2", CK_BDVER2) 2306 .Case("bdver3", CK_BDVER3) 2307 .Case("bdver4", CK_BDVER4) 2308 .Case("x86-64", CK_x86_64) 2309 .Case("geode", CK_Geode) 2310 .Default(CK_Generic); 2311 } 2312 2313 enum FPMathKind { 2314 FP_Default, 2315 FP_SSE, 2316 FP_387 2317 } FPMath = FP_Default; 2318 2319 public: 2320 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 2321 BigEndian = false; 2322 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2323 } 2324 unsigned getFloatEvalMethod() const override { 2325 // X87 evaluates with 80 bits "long double" precision. 2326 return SSELevel == NoSSE ? 2 : 0; 2327 } 2328 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2329 return llvm::makeArrayRef(BuiltinInfo, 2330 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2331 } 2332 ArrayRef<const char *> getGCCRegNames() const override { 2333 return llvm::makeArrayRef(GCCRegNames); 2334 } 2335 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2336 return None; 2337 } 2338 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2339 return llvm::makeArrayRef(AddlRegNames); 2340 } 2341 bool validateCpuSupports(StringRef Name) const override; 2342 bool validateAsmConstraint(const char *&Name, 2343 TargetInfo::ConstraintInfo &info) const override; 2344 2345 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2346 2347 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2348 2349 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2350 2351 std::string convertConstraint(const char *&Constraint) const override; 2352 const char *getClobbers() const override { 2353 return "~{dirflag},~{fpsr},~{flags}"; 2354 } 2355 void getTargetDefines(const LangOptions &Opts, 2356 MacroBuilder &Builder) const override; 2357 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2358 bool Enabled); 2359 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2360 bool Enabled); 2361 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2362 bool Enabled); 2363 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2364 StringRef Name, bool Enabled) const override { 2365 setFeatureEnabledImpl(Features, Name, Enabled); 2366 } 2367 // This exists purely to cut down on the number of virtual calls in 2368 // initFeatureMap which calls this repeatedly. 2369 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2370 StringRef Name, bool Enabled); 2371 bool 2372 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2373 StringRef CPU, 2374 const std::vector<std::string> &FeaturesVec) const override; 2375 bool hasFeature(StringRef Feature) const override; 2376 bool handleTargetFeatures(std::vector<std::string> &Features, 2377 DiagnosticsEngine &Diags) override; 2378 StringRef getABI() const override { 2379 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2380 return "avx512"; 2381 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2382 return "avx"; 2383 if (getTriple().getArch() == llvm::Triple::x86 && 2384 MMX3DNowLevel == NoMMX3DNow) 2385 return "no-mmx"; 2386 return ""; 2387 } 2388 bool setCPU(const std::string &Name) override { 2389 CPU = getCPUKind(Name); 2390 2391 // Perform any per-CPU checks necessary to determine if this CPU is 2392 // acceptable. 2393 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2394 // invalid without explaining *why*. 2395 switch (CPU) { 2396 case CK_Generic: 2397 // No processor selected! 2398 return false; 2399 2400 case CK_i386: 2401 case CK_i486: 2402 case CK_WinChipC6: 2403 case CK_WinChip2: 2404 case CK_C3: 2405 case CK_i586: 2406 case CK_Pentium: 2407 case CK_PentiumMMX: 2408 case CK_i686: 2409 case CK_PentiumPro: 2410 case CK_Pentium2: 2411 case CK_Pentium3: 2412 case CK_Pentium3M: 2413 case CK_PentiumM: 2414 case CK_Yonah: 2415 case CK_C3_2: 2416 case CK_Pentium4: 2417 case CK_Pentium4M: 2418 case CK_Prescott: 2419 case CK_K6: 2420 case CK_K6_2: 2421 case CK_K6_3: 2422 case CK_Athlon: 2423 case CK_AthlonThunderbird: 2424 case CK_Athlon4: 2425 case CK_AthlonXP: 2426 case CK_AthlonMP: 2427 case CK_Geode: 2428 // Only accept certain architectures when compiling in 32-bit mode. 2429 if (getTriple().getArch() != llvm::Triple::x86) 2430 return false; 2431 2432 // Fallthrough 2433 case CK_Nocona: 2434 case CK_Core2: 2435 case CK_Penryn: 2436 case CK_Bonnell: 2437 case CK_Silvermont: 2438 case CK_Nehalem: 2439 case CK_Westmere: 2440 case CK_SandyBridge: 2441 case CK_IvyBridge: 2442 case CK_Haswell: 2443 case CK_Broadwell: 2444 case CK_Skylake: 2445 case CK_KNL: 2446 case CK_Athlon64: 2447 case CK_Athlon64SSE3: 2448 case CK_AthlonFX: 2449 case CK_K8: 2450 case CK_K8SSE3: 2451 case CK_Opteron: 2452 case CK_OpteronSSE3: 2453 case CK_AMDFAM10: 2454 case CK_BTVER1: 2455 case CK_BTVER2: 2456 case CK_BDVER1: 2457 case CK_BDVER2: 2458 case CK_BDVER3: 2459 case CK_BDVER4: 2460 case CK_x86_64: 2461 return true; 2462 } 2463 llvm_unreachable("Unhandled CPU kind"); 2464 } 2465 2466 bool setFPMath(StringRef Name) override; 2467 2468 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2469 // We accept all non-ARM calling conventions 2470 return (CC == CC_X86ThisCall || 2471 CC == CC_X86FastCall || 2472 CC == CC_X86StdCall || 2473 CC == CC_X86VectorCall || 2474 CC == CC_C || 2475 CC == CC_X86Pascal || 2476 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2477 } 2478 2479 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2480 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2481 } 2482 2483 bool hasSjLjLowering() const override { 2484 return true; 2485 } 2486 }; 2487 2488 bool X86TargetInfo::setFPMath(StringRef Name) { 2489 if (Name == "387") { 2490 FPMath = FP_387; 2491 return true; 2492 } 2493 if (Name == "sse") { 2494 FPMath = FP_SSE; 2495 return true; 2496 } 2497 return false; 2498 } 2499 2500 bool X86TargetInfo::initFeatureMap( 2501 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2502 const std::vector<std::string> &FeaturesVec) const { 2503 // FIXME: This *really* should not be here. 2504 // X86_64 always has SSE2. 2505 if (getTriple().getArch() == llvm::Triple::x86_64) 2506 setFeatureEnabledImpl(Features, "sse2", true); 2507 2508 switch (getCPUKind(CPU)) { 2509 case CK_Generic: 2510 case CK_i386: 2511 case CK_i486: 2512 case CK_i586: 2513 case CK_Pentium: 2514 case CK_i686: 2515 case CK_PentiumPro: 2516 break; 2517 case CK_PentiumMMX: 2518 case CK_Pentium2: 2519 case CK_K6: 2520 case CK_WinChipC6: 2521 setFeatureEnabledImpl(Features, "mmx", true); 2522 break; 2523 case CK_Pentium3: 2524 case CK_Pentium3M: 2525 case CK_C3_2: 2526 setFeatureEnabledImpl(Features, "sse", true); 2527 setFeatureEnabledImpl(Features, "fxsr", true); 2528 break; 2529 case CK_PentiumM: 2530 case CK_Pentium4: 2531 case CK_Pentium4M: 2532 case CK_x86_64: 2533 setFeatureEnabledImpl(Features, "sse2", true); 2534 setFeatureEnabledImpl(Features, "fxsr", true); 2535 break; 2536 case CK_Yonah: 2537 case CK_Prescott: 2538 case CK_Nocona: 2539 setFeatureEnabledImpl(Features, "sse3", true); 2540 setFeatureEnabledImpl(Features, "fxsr", true); 2541 setFeatureEnabledImpl(Features, "cx16", true); 2542 break; 2543 case CK_Core2: 2544 case CK_Bonnell: 2545 setFeatureEnabledImpl(Features, "ssse3", true); 2546 setFeatureEnabledImpl(Features, "fxsr", true); 2547 setFeatureEnabledImpl(Features, "cx16", true); 2548 break; 2549 case CK_Penryn: 2550 setFeatureEnabledImpl(Features, "sse4.1", true); 2551 setFeatureEnabledImpl(Features, "fxsr", true); 2552 setFeatureEnabledImpl(Features, "cx16", true); 2553 break; 2554 case CK_Skylake: 2555 setFeatureEnabledImpl(Features, "avx512f", true); 2556 setFeatureEnabledImpl(Features, "avx512cd", true); 2557 setFeatureEnabledImpl(Features, "avx512dq", true); 2558 setFeatureEnabledImpl(Features, "avx512bw", true); 2559 setFeatureEnabledImpl(Features, "avx512vl", true); 2560 setFeatureEnabledImpl(Features, "xsavec", true); 2561 setFeatureEnabledImpl(Features, "xsaves", true); 2562 // FALLTHROUGH 2563 case CK_Broadwell: 2564 setFeatureEnabledImpl(Features, "rdseed", true); 2565 setFeatureEnabledImpl(Features, "adx", true); 2566 // FALLTHROUGH 2567 case CK_Haswell: 2568 setFeatureEnabledImpl(Features, "avx2", true); 2569 setFeatureEnabledImpl(Features, "lzcnt", true); 2570 setFeatureEnabledImpl(Features, "bmi", true); 2571 setFeatureEnabledImpl(Features, "bmi2", true); 2572 setFeatureEnabledImpl(Features, "rtm", true); 2573 setFeatureEnabledImpl(Features, "fma", true); 2574 // FALLTHROUGH 2575 case CK_IvyBridge: 2576 setFeatureEnabledImpl(Features, "rdrnd", true); 2577 setFeatureEnabledImpl(Features, "f16c", true); 2578 setFeatureEnabledImpl(Features, "fsgsbase", true); 2579 // FALLTHROUGH 2580 case CK_SandyBridge: 2581 setFeatureEnabledImpl(Features, "avx", true); 2582 setFeatureEnabledImpl(Features, "xsave", true); 2583 setFeatureEnabledImpl(Features, "xsaveopt", true); 2584 // FALLTHROUGH 2585 case CK_Westmere: 2586 case CK_Silvermont: 2587 setFeatureEnabledImpl(Features, "aes", true); 2588 setFeatureEnabledImpl(Features, "pclmul", true); 2589 // FALLTHROUGH 2590 case CK_Nehalem: 2591 setFeatureEnabledImpl(Features, "sse4.2", true); 2592 setFeatureEnabledImpl(Features, "fxsr", true); 2593 setFeatureEnabledImpl(Features, "cx16", true); 2594 break; 2595 case CK_KNL: 2596 setFeatureEnabledImpl(Features, "avx512f", true); 2597 setFeatureEnabledImpl(Features, "avx512cd", true); 2598 setFeatureEnabledImpl(Features, "avx512er", true); 2599 setFeatureEnabledImpl(Features, "avx512pf", true); 2600 setFeatureEnabledImpl(Features, "fxsr", true); 2601 setFeatureEnabledImpl(Features, "rdseed", true); 2602 setFeatureEnabledImpl(Features, "adx", true); 2603 setFeatureEnabledImpl(Features, "lzcnt", true); 2604 setFeatureEnabledImpl(Features, "bmi", true); 2605 setFeatureEnabledImpl(Features, "bmi2", true); 2606 setFeatureEnabledImpl(Features, "rtm", true); 2607 setFeatureEnabledImpl(Features, "fma", true); 2608 setFeatureEnabledImpl(Features, "rdrnd", true); 2609 setFeatureEnabledImpl(Features, "f16c", true); 2610 setFeatureEnabledImpl(Features, "fsgsbase", true); 2611 setFeatureEnabledImpl(Features, "aes", true); 2612 setFeatureEnabledImpl(Features, "pclmul", true); 2613 setFeatureEnabledImpl(Features, "cx16", true); 2614 setFeatureEnabledImpl(Features, "xsaveopt", true); 2615 setFeatureEnabledImpl(Features, "xsave", true); 2616 break; 2617 case CK_K6_2: 2618 case CK_K6_3: 2619 case CK_WinChip2: 2620 case CK_C3: 2621 setFeatureEnabledImpl(Features, "3dnow", true); 2622 break; 2623 case CK_Athlon: 2624 case CK_AthlonThunderbird: 2625 case CK_Geode: 2626 setFeatureEnabledImpl(Features, "3dnowa", true); 2627 break; 2628 case CK_Athlon4: 2629 case CK_AthlonXP: 2630 case CK_AthlonMP: 2631 setFeatureEnabledImpl(Features, "sse", true); 2632 setFeatureEnabledImpl(Features, "3dnowa", true); 2633 setFeatureEnabledImpl(Features, "fxsr", true); 2634 break; 2635 case CK_K8: 2636 case CK_Opteron: 2637 case CK_Athlon64: 2638 case CK_AthlonFX: 2639 setFeatureEnabledImpl(Features, "sse2", true); 2640 setFeatureEnabledImpl(Features, "3dnowa", true); 2641 setFeatureEnabledImpl(Features, "fxsr", true); 2642 break; 2643 case CK_AMDFAM10: 2644 setFeatureEnabledImpl(Features, "sse4a", true); 2645 setFeatureEnabledImpl(Features, "lzcnt", true); 2646 setFeatureEnabledImpl(Features, "popcnt", true); 2647 // FALLTHROUGH 2648 case CK_K8SSE3: 2649 case CK_OpteronSSE3: 2650 case CK_Athlon64SSE3: 2651 setFeatureEnabledImpl(Features, "sse3", true); 2652 setFeatureEnabledImpl(Features, "3dnowa", true); 2653 setFeatureEnabledImpl(Features, "fxsr", true); 2654 break; 2655 case CK_BTVER2: 2656 setFeatureEnabledImpl(Features, "avx", true); 2657 setFeatureEnabledImpl(Features, "aes", true); 2658 setFeatureEnabledImpl(Features, "pclmul", true); 2659 setFeatureEnabledImpl(Features, "bmi", true); 2660 setFeatureEnabledImpl(Features, "f16c", true); 2661 setFeatureEnabledImpl(Features, "xsaveopt", true); 2662 // FALLTHROUGH 2663 case CK_BTVER1: 2664 setFeatureEnabledImpl(Features, "ssse3", true); 2665 setFeatureEnabledImpl(Features, "sse4a", true); 2666 setFeatureEnabledImpl(Features, "lzcnt", true); 2667 setFeatureEnabledImpl(Features, "popcnt", true); 2668 setFeatureEnabledImpl(Features, "prfchw", true); 2669 setFeatureEnabledImpl(Features, "cx16", true); 2670 setFeatureEnabledImpl(Features, "fxsr", true); 2671 setFeatureEnabledImpl(Features, "xsave", true); 2672 break; 2673 case CK_BDVER4: 2674 setFeatureEnabledImpl(Features, "avx2", true); 2675 setFeatureEnabledImpl(Features, "bmi2", true); 2676 // FALLTHROUGH 2677 case CK_BDVER3: 2678 setFeatureEnabledImpl(Features, "fsgsbase", true); 2679 setFeatureEnabledImpl(Features, "xsaveopt", true); 2680 // FALLTHROUGH 2681 case CK_BDVER2: 2682 setFeatureEnabledImpl(Features, "bmi", true); 2683 setFeatureEnabledImpl(Features, "fma", true); 2684 setFeatureEnabledImpl(Features, "f16c", true); 2685 setFeatureEnabledImpl(Features, "tbm", true); 2686 // FALLTHROUGH 2687 case CK_BDVER1: 2688 // xop implies avx, sse4a and fma4. 2689 setFeatureEnabledImpl(Features, "xop", true); 2690 setFeatureEnabledImpl(Features, "lzcnt", true); 2691 setFeatureEnabledImpl(Features, "aes", true); 2692 setFeatureEnabledImpl(Features, "pclmul", true); 2693 setFeatureEnabledImpl(Features, "prfchw", true); 2694 setFeatureEnabledImpl(Features, "cx16", true); 2695 setFeatureEnabledImpl(Features, "fxsr", true); 2696 setFeatureEnabledImpl(Features, "xsave", true); 2697 break; 2698 } 2699 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2700 return false; 2701 2702 // Can't do this earlier because we need to be able to explicitly enable 2703 // or disable these features and the things that they depend upon. 2704 2705 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2706 auto I = Features.find("sse4.2"); 2707 if (I != Features.end() && I->getValue() && 2708 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2709 FeaturesVec.end()) 2710 Features["popcnt"] = true; 2711 2712 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2713 I = Features.find("3dnow"); 2714 if (I != Features.end() && I->getValue() && 2715 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2716 FeaturesVec.end()) 2717 Features["prfchw"] = true; 2718 2719 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2720 // then enable MMX. 2721 I = Features.find("sse"); 2722 if (I != Features.end() && I->getValue() && 2723 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2724 FeaturesVec.end()) 2725 Features["mmx"] = true; 2726 2727 return true; 2728 } 2729 2730 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2731 X86SSEEnum Level, bool Enabled) { 2732 if (Enabled) { 2733 switch (Level) { 2734 case AVX512F: 2735 Features["avx512f"] = true; 2736 case AVX2: 2737 Features["avx2"] = true; 2738 case AVX: 2739 Features["avx"] = true; 2740 Features["xsave"] = true; 2741 case SSE42: 2742 Features["sse4.2"] = true; 2743 case SSE41: 2744 Features["sse4.1"] = true; 2745 case SSSE3: 2746 Features["ssse3"] = true; 2747 case SSE3: 2748 Features["sse3"] = true; 2749 case SSE2: 2750 Features["sse2"] = true; 2751 case SSE1: 2752 Features["sse"] = true; 2753 case NoSSE: 2754 break; 2755 } 2756 return; 2757 } 2758 2759 switch (Level) { 2760 case NoSSE: 2761 case SSE1: 2762 Features["sse"] = false; 2763 case SSE2: 2764 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2765 Features["sha"] = false; 2766 case SSE3: 2767 Features["sse3"] = false; 2768 setXOPLevel(Features, NoXOP, false); 2769 case SSSE3: 2770 Features["ssse3"] = false; 2771 case SSE41: 2772 Features["sse4.1"] = false; 2773 case SSE42: 2774 Features["sse4.2"] = false; 2775 case AVX: 2776 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2777 Features["xsaveopt"] = false; 2778 setXOPLevel(Features, FMA4, false); 2779 case AVX2: 2780 Features["avx2"] = false; 2781 case AVX512F: 2782 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2783 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2784 Features["avx512vl"] = false; 2785 } 2786 } 2787 2788 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2789 MMX3DNowEnum Level, bool Enabled) { 2790 if (Enabled) { 2791 switch (Level) { 2792 case AMD3DNowAthlon: 2793 Features["3dnowa"] = true; 2794 case AMD3DNow: 2795 Features["3dnow"] = true; 2796 case MMX: 2797 Features["mmx"] = true; 2798 case NoMMX3DNow: 2799 break; 2800 } 2801 return; 2802 } 2803 2804 switch (Level) { 2805 case NoMMX3DNow: 2806 case MMX: 2807 Features["mmx"] = false; 2808 case AMD3DNow: 2809 Features["3dnow"] = false; 2810 case AMD3DNowAthlon: 2811 Features["3dnowa"] = false; 2812 } 2813 } 2814 2815 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2816 bool Enabled) { 2817 if (Enabled) { 2818 switch (Level) { 2819 case XOP: 2820 Features["xop"] = true; 2821 case FMA4: 2822 Features["fma4"] = true; 2823 setSSELevel(Features, AVX, true); 2824 case SSE4A: 2825 Features["sse4a"] = true; 2826 setSSELevel(Features, SSE3, true); 2827 case NoXOP: 2828 break; 2829 } 2830 return; 2831 } 2832 2833 switch (Level) { 2834 case NoXOP: 2835 case SSE4A: 2836 Features["sse4a"] = false; 2837 case FMA4: 2838 Features["fma4"] = false; 2839 case XOP: 2840 Features["xop"] = false; 2841 } 2842 } 2843 2844 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2845 StringRef Name, bool Enabled) { 2846 // This is a bit of a hack to deal with the sse4 target feature when used 2847 // as part of the target attribute. We handle sse4 correctly everywhere 2848 // else. See below for more information on how we handle the sse4 options. 2849 if (Name != "sse4") 2850 Features[Name] = Enabled; 2851 2852 if (Name == "mmx") { 2853 setMMXLevel(Features, MMX, Enabled); 2854 } else if (Name == "sse") { 2855 setSSELevel(Features, SSE1, Enabled); 2856 } else if (Name == "sse2") { 2857 setSSELevel(Features, SSE2, Enabled); 2858 } else if (Name == "sse3") { 2859 setSSELevel(Features, SSE3, Enabled); 2860 } else if (Name == "ssse3") { 2861 setSSELevel(Features, SSSE3, Enabled); 2862 } else if (Name == "sse4.2") { 2863 setSSELevel(Features, SSE42, Enabled); 2864 } else if (Name == "sse4.1") { 2865 setSSELevel(Features, SSE41, Enabled); 2866 } else if (Name == "3dnow") { 2867 setMMXLevel(Features, AMD3DNow, Enabled); 2868 } else if (Name == "3dnowa") { 2869 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2870 } else if (Name == "aes") { 2871 if (Enabled) 2872 setSSELevel(Features, SSE2, Enabled); 2873 } else if (Name == "pclmul") { 2874 if (Enabled) 2875 setSSELevel(Features, SSE2, Enabled); 2876 } else if (Name == "avx") { 2877 setSSELevel(Features, AVX, Enabled); 2878 } else if (Name == "avx2") { 2879 setSSELevel(Features, AVX2, Enabled); 2880 } else if (Name == "avx512f") { 2881 setSSELevel(Features, AVX512F, Enabled); 2882 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2883 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2884 if (Enabled) 2885 setSSELevel(Features, AVX512F, Enabled); 2886 } else if (Name == "fma") { 2887 if (Enabled) 2888 setSSELevel(Features, AVX, Enabled); 2889 } else if (Name == "fma4") { 2890 setXOPLevel(Features, FMA4, Enabled); 2891 } else if (Name == "xop") { 2892 setXOPLevel(Features, XOP, Enabled); 2893 } else if (Name == "sse4a") { 2894 setXOPLevel(Features, SSE4A, Enabled); 2895 } else if (Name == "f16c") { 2896 if (Enabled) 2897 setSSELevel(Features, AVX, Enabled); 2898 } else if (Name == "sha") { 2899 if (Enabled) 2900 setSSELevel(Features, SSE2, Enabled); 2901 } else if (Name == "sse4") { 2902 // We can get here via the __target__ attribute since that's not controlled 2903 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2904 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2905 // disabled. 2906 if (Enabled) 2907 setSSELevel(Features, SSE42, Enabled); 2908 else 2909 setSSELevel(Features, SSE41, Enabled); 2910 } else if (Name == "xsave") { 2911 if (Enabled) 2912 setSSELevel(Features, AVX, Enabled); 2913 else 2914 Features["xsaveopt"] = false; 2915 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 2916 if (Enabled) { 2917 Features["xsave"] = true; 2918 setSSELevel(Features, AVX, Enabled); 2919 } 2920 } 2921 } 2922 2923 /// handleTargetFeatures - Perform initialization based on the user 2924 /// configured set of features. 2925 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2926 DiagnosticsEngine &Diags) { 2927 for (const auto &Feature : Features) { 2928 if (Feature[0] != '+') 2929 continue; 2930 2931 if (Feature == "+aes") { 2932 HasAES = true; 2933 } else if (Feature == "+pclmul") { 2934 HasPCLMUL = true; 2935 } else if (Feature == "+lzcnt") { 2936 HasLZCNT = true; 2937 } else if (Feature == "+rdrnd") { 2938 HasRDRND = true; 2939 } else if (Feature == "+fsgsbase") { 2940 HasFSGSBASE = true; 2941 } else if (Feature == "+bmi") { 2942 HasBMI = true; 2943 } else if (Feature == "+bmi2") { 2944 HasBMI2 = true; 2945 } else if (Feature == "+popcnt") { 2946 HasPOPCNT = true; 2947 } else if (Feature == "+rtm") { 2948 HasRTM = true; 2949 } else if (Feature == "+prfchw") { 2950 HasPRFCHW = true; 2951 } else if (Feature == "+rdseed") { 2952 HasRDSEED = true; 2953 } else if (Feature == "+adx") { 2954 HasADX = true; 2955 } else if (Feature == "+tbm") { 2956 HasTBM = true; 2957 } else if (Feature == "+fma") { 2958 HasFMA = true; 2959 } else if (Feature == "+f16c") { 2960 HasF16C = true; 2961 } else if (Feature == "+avx512cd") { 2962 HasAVX512CD = true; 2963 } else if (Feature == "+avx512er") { 2964 HasAVX512ER = true; 2965 } else if (Feature == "+avx512pf") { 2966 HasAVX512PF = true; 2967 } else if (Feature == "+avx512dq") { 2968 HasAVX512DQ = true; 2969 } else if (Feature == "+avx512bw") { 2970 HasAVX512BW = true; 2971 } else if (Feature == "+avx512vl") { 2972 HasAVX512VL = true; 2973 } else if (Feature == "+sha") { 2974 HasSHA = true; 2975 } else if (Feature == "+cx16") { 2976 HasCX16 = true; 2977 } else if (Feature == "+fxsr") { 2978 HasFXSR = true; 2979 } else if (Feature == "+xsave") { 2980 HasXSAVE = true; 2981 } else if (Feature == "+xsaveopt") { 2982 HasXSAVEOPT = true; 2983 } else if (Feature == "+xsavec") { 2984 HasXSAVEC = true; 2985 } else if (Feature == "+xsaves") { 2986 HasXSAVES = true; 2987 } 2988 2989 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2990 .Case("+avx512f", AVX512F) 2991 .Case("+avx2", AVX2) 2992 .Case("+avx", AVX) 2993 .Case("+sse4.2", SSE42) 2994 .Case("+sse4.1", SSE41) 2995 .Case("+ssse3", SSSE3) 2996 .Case("+sse3", SSE3) 2997 .Case("+sse2", SSE2) 2998 .Case("+sse", SSE1) 2999 .Default(NoSSE); 3000 SSELevel = std::max(SSELevel, Level); 3001 3002 MMX3DNowEnum ThreeDNowLevel = 3003 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3004 .Case("+3dnowa", AMD3DNowAthlon) 3005 .Case("+3dnow", AMD3DNow) 3006 .Case("+mmx", MMX) 3007 .Default(NoMMX3DNow); 3008 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3009 3010 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3011 .Case("+xop", XOP) 3012 .Case("+fma4", FMA4) 3013 .Case("+sse4a", SSE4A) 3014 .Default(NoXOP); 3015 XOPLevel = std::max(XOPLevel, XLevel); 3016 } 3017 3018 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3019 // matches the selected sse level. 3020 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3021 (FPMath == FP_387 && SSELevel >= SSE1)) { 3022 Diags.Report(diag::err_target_unsupported_fpmath) << 3023 (FPMath == FP_SSE ? "sse" : "387"); 3024 return false; 3025 } 3026 3027 SimdDefaultAlign = 3028 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3029 return true; 3030 } 3031 3032 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3033 /// definitions for this particular subtarget. 3034 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3035 MacroBuilder &Builder) const { 3036 // Target identification. 3037 if (getTriple().getArch() == llvm::Triple::x86_64) { 3038 Builder.defineMacro("__amd64__"); 3039 Builder.defineMacro("__amd64"); 3040 Builder.defineMacro("__x86_64"); 3041 Builder.defineMacro("__x86_64__"); 3042 if (getTriple().getArchName() == "x86_64h") { 3043 Builder.defineMacro("__x86_64h"); 3044 Builder.defineMacro("__x86_64h__"); 3045 } 3046 } else { 3047 DefineStd(Builder, "i386", Opts); 3048 } 3049 3050 // Subtarget options. 3051 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3052 // truly should be based on -mtune options. 3053 switch (CPU) { 3054 case CK_Generic: 3055 break; 3056 case CK_i386: 3057 // The rest are coming from the i386 define above. 3058 Builder.defineMacro("__tune_i386__"); 3059 break; 3060 case CK_i486: 3061 case CK_WinChipC6: 3062 case CK_WinChip2: 3063 case CK_C3: 3064 defineCPUMacros(Builder, "i486"); 3065 break; 3066 case CK_PentiumMMX: 3067 Builder.defineMacro("__pentium_mmx__"); 3068 Builder.defineMacro("__tune_pentium_mmx__"); 3069 // Fallthrough 3070 case CK_i586: 3071 case CK_Pentium: 3072 defineCPUMacros(Builder, "i586"); 3073 defineCPUMacros(Builder, "pentium"); 3074 break; 3075 case CK_Pentium3: 3076 case CK_Pentium3M: 3077 case CK_PentiumM: 3078 Builder.defineMacro("__tune_pentium3__"); 3079 // Fallthrough 3080 case CK_Pentium2: 3081 case CK_C3_2: 3082 Builder.defineMacro("__tune_pentium2__"); 3083 // Fallthrough 3084 case CK_PentiumPro: 3085 Builder.defineMacro("__tune_i686__"); 3086 Builder.defineMacro("__tune_pentiumpro__"); 3087 // Fallthrough 3088 case CK_i686: 3089 Builder.defineMacro("__i686"); 3090 Builder.defineMacro("__i686__"); 3091 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3092 Builder.defineMacro("__pentiumpro"); 3093 Builder.defineMacro("__pentiumpro__"); 3094 break; 3095 case CK_Pentium4: 3096 case CK_Pentium4M: 3097 defineCPUMacros(Builder, "pentium4"); 3098 break; 3099 case CK_Yonah: 3100 case CK_Prescott: 3101 case CK_Nocona: 3102 defineCPUMacros(Builder, "nocona"); 3103 break; 3104 case CK_Core2: 3105 case CK_Penryn: 3106 defineCPUMacros(Builder, "core2"); 3107 break; 3108 case CK_Bonnell: 3109 defineCPUMacros(Builder, "atom"); 3110 break; 3111 case CK_Silvermont: 3112 defineCPUMacros(Builder, "slm"); 3113 break; 3114 case CK_Nehalem: 3115 case CK_Westmere: 3116 case CK_SandyBridge: 3117 case CK_IvyBridge: 3118 case CK_Haswell: 3119 case CK_Broadwell: 3120 // FIXME: Historically, we defined this legacy name, it would be nice to 3121 // remove it at some point. We've never exposed fine-grained names for 3122 // recent primary x86 CPUs, and we should keep it that way. 3123 defineCPUMacros(Builder, "corei7"); 3124 break; 3125 case CK_Skylake: 3126 // FIXME: Historically, we defined this legacy name, it would be nice to 3127 // remove it at some point. This is the only fine-grained CPU macro in the 3128 // main intel CPU line, and it would be better to not have these and force 3129 // people to use ISA macros. 3130 defineCPUMacros(Builder, "skx"); 3131 break; 3132 case CK_KNL: 3133 defineCPUMacros(Builder, "knl"); 3134 break; 3135 case CK_K6_2: 3136 Builder.defineMacro("__k6_2__"); 3137 Builder.defineMacro("__tune_k6_2__"); 3138 // Fallthrough 3139 case CK_K6_3: 3140 if (CPU != CK_K6_2) { // In case of fallthrough 3141 // FIXME: GCC may be enabling these in cases where some other k6 3142 // architecture is specified but -m3dnow is explicitly provided. The 3143 // exact semantics need to be determined and emulated here. 3144 Builder.defineMacro("__k6_3__"); 3145 Builder.defineMacro("__tune_k6_3__"); 3146 } 3147 // Fallthrough 3148 case CK_K6: 3149 defineCPUMacros(Builder, "k6"); 3150 break; 3151 case CK_Athlon: 3152 case CK_AthlonThunderbird: 3153 case CK_Athlon4: 3154 case CK_AthlonXP: 3155 case CK_AthlonMP: 3156 defineCPUMacros(Builder, "athlon"); 3157 if (SSELevel != NoSSE) { 3158 Builder.defineMacro("__athlon_sse__"); 3159 Builder.defineMacro("__tune_athlon_sse__"); 3160 } 3161 break; 3162 case CK_K8: 3163 case CK_K8SSE3: 3164 case CK_x86_64: 3165 case CK_Opteron: 3166 case CK_OpteronSSE3: 3167 case CK_Athlon64: 3168 case CK_Athlon64SSE3: 3169 case CK_AthlonFX: 3170 defineCPUMacros(Builder, "k8"); 3171 break; 3172 case CK_AMDFAM10: 3173 defineCPUMacros(Builder, "amdfam10"); 3174 break; 3175 case CK_BTVER1: 3176 defineCPUMacros(Builder, "btver1"); 3177 break; 3178 case CK_BTVER2: 3179 defineCPUMacros(Builder, "btver2"); 3180 break; 3181 case CK_BDVER1: 3182 defineCPUMacros(Builder, "bdver1"); 3183 break; 3184 case CK_BDVER2: 3185 defineCPUMacros(Builder, "bdver2"); 3186 break; 3187 case CK_BDVER3: 3188 defineCPUMacros(Builder, "bdver3"); 3189 break; 3190 case CK_BDVER4: 3191 defineCPUMacros(Builder, "bdver4"); 3192 break; 3193 case CK_Geode: 3194 defineCPUMacros(Builder, "geode"); 3195 break; 3196 } 3197 3198 // Target properties. 3199 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3200 3201 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3202 // functions in glibc header files that use FP Stack inline asm which the 3203 // backend can't deal with (PR879). 3204 Builder.defineMacro("__NO_MATH_INLINES"); 3205 3206 if (HasAES) 3207 Builder.defineMacro("__AES__"); 3208 3209 if (HasPCLMUL) 3210 Builder.defineMacro("__PCLMUL__"); 3211 3212 if (HasLZCNT) 3213 Builder.defineMacro("__LZCNT__"); 3214 3215 if (HasRDRND) 3216 Builder.defineMacro("__RDRND__"); 3217 3218 if (HasFSGSBASE) 3219 Builder.defineMacro("__FSGSBASE__"); 3220 3221 if (HasBMI) 3222 Builder.defineMacro("__BMI__"); 3223 3224 if (HasBMI2) 3225 Builder.defineMacro("__BMI2__"); 3226 3227 if (HasPOPCNT) 3228 Builder.defineMacro("__POPCNT__"); 3229 3230 if (HasRTM) 3231 Builder.defineMacro("__RTM__"); 3232 3233 if (HasPRFCHW) 3234 Builder.defineMacro("__PRFCHW__"); 3235 3236 if (HasRDSEED) 3237 Builder.defineMacro("__RDSEED__"); 3238 3239 if (HasADX) 3240 Builder.defineMacro("__ADX__"); 3241 3242 if (HasTBM) 3243 Builder.defineMacro("__TBM__"); 3244 3245 switch (XOPLevel) { 3246 case XOP: 3247 Builder.defineMacro("__XOP__"); 3248 case FMA4: 3249 Builder.defineMacro("__FMA4__"); 3250 case SSE4A: 3251 Builder.defineMacro("__SSE4A__"); 3252 case NoXOP: 3253 break; 3254 } 3255 3256 if (HasFMA) 3257 Builder.defineMacro("__FMA__"); 3258 3259 if (HasF16C) 3260 Builder.defineMacro("__F16C__"); 3261 3262 if (HasAVX512CD) 3263 Builder.defineMacro("__AVX512CD__"); 3264 if (HasAVX512ER) 3265 Builder.defineMacro("__AVX512ER__"); 3266 if (HasAVX512PF) 3267 Builder.defineMacro("__AVX512PF__"); 3268 if (HasAVX512DQ) 3269 Builder.defineMacro("__AVX512DQ__"); 3270 if (HasAVX512BW) 3271 Builder.defineMacro("__AVX512BW__"); 3272 if (HasAVX512VL) 3273 Builder.defineMacro("__AVX512VL__"); 3274 3275 if (HasSHA) 3276 Builder.defineMacro("__SHA__"); 3277 3278 if (HasFXSR) 3279 Builder.defineMacro("__FXSR__"); 3280 if (HasXSAVE) 3281 Builder.defineMacro("__XSAVE__"); 3282 if (HasXSAVEOPT) 3283 Builder.defineMacro("__XSAVEOPT__"); 3284 if (HasXSAVEC) 3285 Builder.defineMacro("__XSAVEC__"); 3286 if (HasXSAVES) 3287 Builder.defineMacro("__XSAVES__"); 3288 3289 if (HasCX16) 3290 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3291 3292 // Each case falls through to the previous one here. 3293 switch (SSELevel) { 3294 case AVX512F: 3295 Builder.defineMacro("__AVX512F__"); 3296 case AVX2: 3297 Builder.defineMacro("__AVX2__"); 3298 case AVX: 3299 Builder.defineMacro("__AVX__"); 3300 case SSE42: 3301 Builder.defineMacro("__SSE4_2__"); 3302 case SSE41: 3303 Builder.defineMacro("__SSE4_1__"); 3304 case SSSE3: 3305 Builder.defineMacro("__SSSE3__"); 3306 case SSE3: 3307 Builder.defineMacro("__SSE3__"); 3308 case SSE2: 3309 Builder.defineMacro("__SSE2__"); 3310 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3311 case SSE1: 3312 Builder.defineMacro("__SSE__"); 3313 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3314 case NoSSE: 3315 break; 3316 } 3317 3318 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3319 switch (SSELevel) { 3320 case AVX512F: 3321 case AVX2: 3322 case AVX: 3323 case SSE42: 3324 case SSE41: 3325 case SSSE3: 3326 case SSE3: 3327 case SSE2: 3328 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3329 break; 3330 case SSE1: 3331 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3332 break; 3333 default: 3334 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3335 } 3336 } 3337 3338 // Each case falls through to the previous one here. 3339 switch (MMX3DNowLevel) { 3340 case AMD3DNowAthlon: 3341 Builder.defineMacro("__3dNOW_A__"); 3342 case AMD3DNow: 3343 Builder.defineMacro("__3dNOW__"); 3344 case MMX: 3345 Builder.defineMacro("__MMX__"); 3346 case NoMMX3DNow: 3347 break; 3348 } 3349 3350 if (CPU >= CK_i486) { 3351 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3352 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3353 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3354 } 3355 if (CPU >= CK_i586) 3356 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3357 } 3358 3359 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3360 return llvm::StringSwitch<bool>(Feature) 3361 .Case("aes", HasAES) 3362 .Case("avx", SSELevel >= AVX) 3363 .Case("avx2", SSELevel >= AVX2) 3364 .Case("avx512f", SSELevel >= AVX512F) 3365 .Case("avx512cd", HasAVX512CD) 3366 .Case("avx512er", HasAVX512ER) 3367 .Case("avx512pf", HasAVX512PF) 3368 .Case("avx512dq", HasAVX512DQ) 3369 .Case("avx512bw", HasAVX512BW) 3370 .Case("avx512vl", HasAVX512VL) 3371 .Case("bmi", HasBMI) 3372 .Case("bmi2", HasBMI2) 3373 .Case("cx16", HasCX16) 3374 .Case("f16c", HasF16C) 3375 .Case("fma", HasFMA) 3376 .Case("fma4", XOPLevel >= FMA4) 3377 .Case("fsgsbase", HasFSGSBASE) 3378 .Case("fxsr", HasFXSR) 3379 .Case("lzcnt", HasLZCNT) 3380 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3381 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3382 .Case("mmx", MMX3DNowLevel >= MMX) 3383 .Case("pclmul", HasPCLMUL) 3384 .Case("popcnt", HasPOPCNT) 3385 .Case("prfchw", HasPRFCHW) 3386 .Case("rdrnd", HasRDRND) 3387 .Case("rdseed", HasRDSEED) 3388 .Case("rtm", HasRTM) 3389 .Case("sha", HasSHA) 3390 .Case("sse", SSELevel >= SSE1) 3391 .Case("sse2", SSELevel >= SSE2) 3392 .Case("sse3", SSELevel >= SSE3) 3393 .Case("ssse3", SSELevel >= SSSE3) 3394 .Case("sse4.1", SSELevel >= SSE41) 3395 .Case("sse4.2", SSELevel >= SSE42) 3396 .Case("sse4a", XOPLevel >= SSE4A) 3397 .Case("tbm", HasTBM) 3398 .Case("x86", true) 3399 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3400 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3401 .Case("xop", XOPLevel >= XOP) 3402 .Case("xsave", HasXSAVE) 3403 .Case("xsavec", HasXSAVEC) 3404 .Case("xsaves", HasXSAVES) 3405 .Case("xsaveopt", HasXSAVEOPT) 3406 .Default(false); 3407 } 3408 3409 // We can't use a generic validation scheme for the features accepted here 3410 // versus subtarget features accepted in the target attribute because the 3411 // bitfield structure that's initialized in the runtime only supports the 3412 // below currently rather than the full range of subtarget features. (See 3413 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3414 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3415 return llvm::StringSwitch<bool>(FeatureStr) 3416 .Case("cmov", true) 3417 .Case("mmx", true) 3418 .Case("popcnt", true) 3419 .Case("sse", true) 3420 .Case("sse2", true) 3421 .Case("sse3", true) 3422 .Case("sse4.1", true) 3423 .Case("sse4.2", true) 3424 .Case("avx", true) 3425 .Case("avx2", true) 3426 .Case("sse4a", true) 3427 .Case("fma4", true) 3428 .Case("xop", true) 3429 .Case("fma", true) 3430 .Case("avx512f", true) 3431 .Case("bmi", true) 3432 .Case("bmi2", true) 3433 .Default(false); 3434 } 3435 3436 bool 3437 X86TargetInfo::validateAsmConstraint(const char *&Name, 3438 TargetInfo::ConstraintInfo &Info) const { 3439 switch (*Name) { 3440 default: return false; 3441 // Constant constraints. 3442 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3443 // instructions. 3444 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3445 // x86_64 instructions. 3446 case 's': 3447 Info.setRequiresImmediate(); 3448 return true; 3449 case 'I': 3450 Info.setRequiresImmediate(0, 31); 3451 return true; 3452 case 'J': 3453 Info.setRequiresImmediate(0, 63); 3454 return true; 3455 case 'K': 3456 Info.setRequiresImmediate(-128, 127); 3457 return true; 3458 case 'L': 3459 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3460 return true; 3461 case 'M': 3462 Info.setRequiresImmediate(0, 3); 3463 return true; 3464 case 'N': 3465 Info.setRequiresImmediate(0, 255); 3466 return true; 3467 case 'O': 3468 Info.setRequiresImmediate(0, 127); 3469 return true; 3470 // Register constraints. 3471 case 'Y': // 'Y' is the first character for several 2-character constraints. 3472 // Shift the pointer to the second character of the constraint. 3473 Name++; 3474 switch (*Name) { 3475 default: 3476 return false; 3477 case '0': // First SSE register. 3478 case 't': // Any SSE register, when SSE2 is enabled. 3479 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3480 case 'm': // Any MMX register, when inter-unit moves enabled. 3481 Info.setAllowsRegister(); 3482 return true; 3483 } 3484 case 'f': // Any x87 floating point stack register. 3485 // Constraint 'f' cannot be used for output operands. 3486 if (Info.ConstraintStr[0] == '=') 3487 return false; 3488 Info.setAllowsRegister(); 3489 return true; 3490 case 'a': // eax. 3491 case 'b': // ebx. 3492 case 'c': // ecx. 3493 case 'd': // edx. 3494 case 'S': // esi. 3495 case 'D': // edi. 3496 case 'A': // edx:eax. 3497 case 't': // Top of floating point stack. 3498 case 'u': // Second from top of floating point stack. 3499 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3500 case 'y': // Any MMX register. 3501 case 'x': // Any SSE register. 3502 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3503 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3504 case 'l': // "Index" registers: any general register that can be used as an 3505 // index in a base+index memory access. 3506 Info.setAllowsRegister(); 3507 return true; 3508 // Floating point constant constraints. 3509 case 'C': // SSE floating point constant. 3510 case 'G': // x87 floating point constant. 3511 return true; 3512 } 3513 } 3514 3515 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3516 unsigned Size) const { 3517 // Strip off constraint modifiers. 3518 while (Constraint[0] == '=' || 3519 Constraint[0] == '+' || 3520 Constraint[0] == '&') 3521 Constraint = Constraint.substr(1); 3522 3523 return validateOperandSize(Constraint, Size); 3524 } 3525 3526 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3527 unsigned Size) const { 3528 return validateOperandSize(Constraint, Size); 3529 } 3530 3531 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3532 unsigned Size) const { 3533 switch (Constraint[0]) { 3534 default: break; 3535 case 'y': 3536 return Size <= 64; 3537 case 'f': 3538 case 't': 3539 case 'u': 3540 return Size <= 128; 3541 case 'x': 3542 if (SSELevel >= AVX512F) 3543 // 512-bit zmm registers can be used if target supports AVX512F. 3544 return Size <= 512U; 3545 else if (SSELevel >= AVX) 3546 // 256-bit ymm registers can be used if target supports AVX. 3547 return Size <= 256U; 3548 return Size <= 128U; 3549 case 'Y': 3550 // 'Y' is the first character for several 2-character constraints. 3551 switch (Constraint[1]) { 3552 default: break; 3553 case 'm': 3554 // 'Ym' is synonymous with 'y'. 3555 return Size <= 64; 3556 case 'i': 3557 case 't': 3558 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3559 if (SSELevel >= AVX512F) 3560 return Size <= 512U; 3561 else if (SSELevel >= AVX) 3562 return Size <= 256U; 3563 return SSELevel >= SSE2 && Size <= 128U; 3564 } 3565 3566 } 3567 3568 return true; 3569 } 3570 3571 std::string 3572 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3573 switch (*Constraint) { 3574 case 'a': return std::string("{ax}"); 3575 case 'b': return std::string("{bx}"); 3576 case 'c': return std::string("{cx}"); 3577 case 'd': return std::string("{dx}"); 3578 case 'S': return std::string("{si}"); 3579 case 'D': return std::string("{di}"); 3580 case 'p': // address 3581 return std::string("im"); 3582 case 't': // top of floating point stack. 3583 return std::string("{st}"); 3584 case 'u': // second from top of floating point stack. 3585 return std::string("{st(1)}"); // second from top of floating point stack. 3586 default: 3587 return std::string(1, *Constraint); 3588 } 3589 } 3590 3591 // X86-32 generic target 3592 class X86_32TargetInfo : public X86TargetInfo { 3593 public: 3594 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3595 DoubleAlign = LongLongAlign = 32; 3596 LongDoubleWidth = 96; 3597 LongDoubleAlign = 32; 3598 SuitableAlign = 128; 3599 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3600 SizeType = UnsignedInt; 3601 PtrDiffType = SignedInt; 3602 IntPtrType = SignedInt; 3603 RegParmMax = 3; 3604 3605 // Use fpret for all types. 3606 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3607 (1 << TargetInfo::Double) | 3608 (1 << TargetInfo::LongDouble)); 3609 3610 // x86-32 has atomics up to 8 bytes 3611 // FIXME: Check that we actually have cmpxchg8b before setting 3612 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3613 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3614 } 3615 BuiltinVaListKind getBuiltinVaListKind() const override { 3616 return TargetInfo::CharPtrBuiltinVaList; 3617 } 3618 3619 int getEHDataRegisterNumber(unsigned RegNo) const override { 3620 if (RegNo == 0) return 0; 3621 if (RegNo == 1) return 2; 3622 return -1; 3623 } 3624 bool validateOperandSize(StringRef Constraint, 3625 unsigned Size) const override { 3626 switch (Constraint[0]) { 3627 default: break; 3628 case 'R': 3629 case 'q': 3630 case 'Q': 3631 case 'a': 3632 case 'b': 3633 case 'c': 3634 case 'd': 3635 case 'S': 3636 case 'D': 3637 return Size <= 32; 3638 case 'A': 3639 return Size <= 64; 3640 } 3641 3642 return X86TargetInfo::validateOperandSize(Constraint, Size); 3643 } 3644 }; 3645 3646 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3647 public: 3648 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3649 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3650 3651 unsigned getFloatEvalMethod() const override { 3652 unsigned Major, Minor, Micro; 3653 getTriple().getOSVersion(Major, Minor, Micro); 3654 // New NetBSD uses the default rounding mode. 3655 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3656 return X86_32TargetInfo::getFloatEvalMethod(); 3657 // NetBSD before 6.99.26 defaults to "double" rounding. 3658 return 1; 3659 } 3660 }; 3661 3662 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3663 public: 3664 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3665 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3666 SizeType = UnsignedLong; 3667 IntPtrType = SignedLong; 3668 PtrDiffType = SignedLong; 3669 } 3670 }; 3671 3672 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3673 public: 3674 BitrigI386TargetInfo(const llvm::Triple &Triple) 3675 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3676 SizeType = UnsignedLong; 3677 IntPtrType = SignedLong; 3678 PtrDiffType = SignedLong; 3679 } 3680 }; 3681 3682 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3683 public: 3684 DarwinI386TargetInfo(const llvm::Triple &Triple) 3685 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3686 LongDoubleWidth = 128; 3687 LongDoubleAlign = 128; 3688 SuitableAlign = 128; 3689 SizeType = UnsignedLong; 3690 IntPtrType = SignedLong; 3691 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3692 HasAlignMac68kSupport = true; 3693 } 3694 3695 bool handleTargetFeatures(std::vector<std::string> &Features, 3696 DiagnosticsEngine &Diags) override { 3697 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3698 Diags)) 3699 return false; 3700 // We now know the features we have: we can decide how to align vectors. 3701 MaxVectorAlign = 3702 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3703 return true; 3704 } 3705 }; 3706 3707 // x86-32 Windows target 3708 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3709 public: 3710 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3711 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3712 WCharType = UnsignedShort; 3713 DoubleAlign = LongLongAlign = 64; 3714 bool IsWinCOFF = 3715 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3716 DataLayoutString = IsWinCOFF 3717 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3718 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3719 } 3720 void getTargetDefines(const LangOptions &Opts, 3721 MacroBuilder &Builder) const override { 3722 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3723 } 3724 }; 3725 3726 // x86-32 Windows Visual Studio target 3727 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3728 public: 3729 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3730 : WindowsX86_32TargetInfo(Triple) { 3731 LongDoubleWidth = LongDoubleAlign = 64; 3732 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3733 } 3734 void getTargetDefines(const LangOptions &Opts, 3735 MacroBuilder &Builder) const override { 3736 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3737 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3738 // The value of the following reflects processor type. 3739 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3740 // We lost the original triple, so we use the default. 3741 Builder.defineMacro("_M_IX86", "600"); 3742 } 3743 }; 3744 3745 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3746 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3747 // supports __declspec natively under -fms-extensions, but we define a no-op 3748 // __declspec macro anyway for pre-processor compatibility. 3749 if (Opts.MicrosoftExt) 3750 Builder.defineMacro("__declspec", "__declspec"); 3751 else 3752 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3753 3754 if (!Opts.MicrosoftExt) { 3755 // Provide macros for all the calling convention keywords. Provide both 3756 // single and double underscore prefixed variants. These are available on 3757 // x64 as well as x86, even though they have no effect. 3758 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3759 for (const char *CC : CCs) { 3760 std::string GCCSpelling = "__attribute__((__"; 3761 GCCSpelling += CC; 3762 GCCSpelling += "__))"; 3763 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3764 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3765 } 3766 } 3767 } 3768 3769 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3770 Builder.defineMacro("__MSVCRT__"); 3771 Builder.defineMacro("__MINGW32__"); 3772 addCygMingDefines(Opts, Builder); 3773 } 3774 3775 // x86-32 MinGW target 3776 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3777 public: 3778 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3779 : WindowsX86_32TargetInfo(Triple) {} 3780 void getTargetDefines(const LangOptions &Opts, 3781 MacroBuilder &Builder) const override { 3782 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3783 DefineStd(Builder, "WIN32", Opts); 3784 DefineStd(Builder, "WINNT", Opts); 3785 Builder.defineMacro("_X86_"); 3786 addMinGWDefines(Opts, Builder); 3787 } 3788 }; 3789 3790 // x86-32 Cygwin target 3791 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3792 public: 3793 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3794 : X86_32TargetInfo(Triple) { 3795 TLSSupported = false; 3796 WCharType = UnsignedShort; 3797 DoubleAlign = LongLongAlign = 64; 3798 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3799 } 3800 void getTargetDefines(const LangOptions &Opts, 3801 MacroBuilder &Builder) const override { 3802 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3803 Builder.defineMacro("_X86_"); 3804 Builder.defineMacro("__CYGWIN__"); 3805 Builder.defineMacro("__CYGWIN32__"); 3806 addCygMingDefines(Opts, Builder); 3807 DefineStd(Builder, "unix", Opts); 3808 if (Opts.CPlusPlus) 3809 Builder.defineMacro("_GNU_SOURCE"); 3810 } 3811 }; 3812 3813 // x86-32 Haiku target 3814 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3815 public: 3816 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3817 SizeType = UnsignedLong; 3818 IntPtrType = SignedLong; 3819 PtrDiffType = SignedLong; 3820 ProcessIDType = SignedLong; 3821 this->UserLabelPrefix = ""; 3822 this->TLSSupported = false; 3823 } 3824 void getTargetDefines(const LangOptions &Opts, 3825 MacroBuilder &Builder) const override { 3826 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3827 Builder.defineMacro("__INTEL__"); 3828 Builder.defineMacro("__HAIKU__"); 3829 } 3830 }; 3831 3832 // RTEMS Target 3833 template<typename Target> 3834 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3835 protected: 3836 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3837 MacroBuilder &Builder) const override { 3838 // RTEMS defines; list based off of gcc output 3839 3840 Builder.defineMacro("__rtems__"); 3841 Builder.defineMacro("__ELF__"); 3842 } 3843 3844 public: 3845 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3846 this->UserLabelPrefix = ""; 3847 3848 switch (Triple.getArch()) { 3849 default: 3850 case llvm::Triple::x86: 3851 // this->MCountName = ".mcount"; 3852 break; 3853 case llvm::Triple::mips: 3854 case llvm::Triple::mipsel: 3855 case llvm::Triple::ppc: 3856 case llvm::Triple::ppc64: 3857 case llvm::Triple::ppc64le: 3858 // this->MCountName = "_mcount"; 3859 break; 3860 case llvm::Triple::arm: 3861 // this->MCountName = "__mcount"; 3862 break; 3863 } 3864 } 3865 }; 3866 3867 // x86-32 RTEMS target 3868 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3869 public: 3870 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3871 SizeType = UnsignedLong; 3872 IntPtrType = SignedLong; 3873 PtrDiffType = SignedLong; 3874 this->UserLabelPrefix = ""; 3875 } 3876 void getTargetDefines(const LangOptions &Opts, 3877 MacroBuilder &Builder) const override { 3878 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3879 Builder.defineMacro("__INTEL__"); 3880 Builder.defineMacro("__rtems__"); 3881 } 3882 }; 3883 3884 // x86-64 generic target 3885 class X86_64TargetInfo : public X86TargetInfo { 3886 public: 3887 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3888 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3889 bool IsWinCOFF = 3890 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3891 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3892 LongDoubleWidth = 128; 3893 LongDoubleAlign = 128; 3894 LargeArrayMinWidth = 128; 3895 LargeArrayAlign = 128; 3896 SuitableAlign = 128; 3897 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3898 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3899 IntPtrType = IsX32 ? SignedInt : SignedLong; 3900 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3901 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3902 RegParmMax = 6; 3903 3904 // Pointers are 32-bit in x32. 3905 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3906 : IsWinCOFF 3907 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3908 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3909 3910 // Use fpret only for long double. 3911 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3912 3913 // Use fp2ret for _Complex long double. 3914 ComplexLongDoubleUsesFP2Ret = true; 3915 3916 // Make __builtin_ms_va_list available. 3917 HasBuiltinMSVaList = true; 3918 3919 // x86-64 has atomics up to 16 bytes. 3920 MaxAtomicPromoteWidth = 128; 3921 MaxAtomicInlineWidth = 128; 3922 } 3923 BuiltinVaListKind getBuiltinVaListKind() const override { 3924 return TargetInfo::X86_64ABIBuiltinVaList; 3925 } 3926 3927 int getEHDataRegisterNumber(unsigned RegNo) const override { 3928 if (RegNo == 0) return 0; 3929 if (RegNo == 1) return 1; 3930 return -1; 3931 } 3932 3933 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3934 return (CC == CC_C || 3935 CC == CC_X86VectorCall || 3936 CC == CC_IntelOclBicc || 3937 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3938 } 3939 3940 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3941 return CC_C; 3942 } 3943 3944 // for x32 we need it here explicitly 3945 bool hasInt128Type() const override { return true; } 3946 }; 3947 3948 // x86-64 Windows target 3949 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3950 public: 3951 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3952 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3953 WCharType = UnsignedShort; 3954 LongWidth = LongAlign = 32; 3955 DoubleAlign = LongLongAlign = 64; 3956 IntMaxType = SignedLongLong; 3957 Int64Type = SignedLongLong; 3958 SizeType = UnsignedLongLong; 3959 PtrDiffType = SignedLongLong; 3960 IntPtrType = SignedLongLong; 3961 this->UserLabelPrefix = ""; 3962 } 3963 3964 void getTargetDefines(const LangOptions &Opts, 3965 MacroBuilder &Builder) const override { 3966 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3967 Builder.defineMacro("_WIN64"); 3968 } 3969 3970 BuiltinVaListKind getBuiltinVaListKind() const override { 3971 return TargetInfo::CharPtrBuiltinVaList; 3972 } 3973 3974 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3975 switch (CC) { 3976 case CC_X86StdCall: 3977 case CC_X86ThisCall: 3978 case CC_X86FastCall: 3979 return CCCR_Ignore; 3980 case CC_C: 3981 case CC_X86VectorCall: 3982 case CC_IntelOclBicc: 3983 case CC_X86_64SysV: 3984 return CCCR_OK; 3985 default: 3986 return CCCR_Warning; 3987 } 3988 } 3989 }; 3990 3991 // x86-64 Windows Visual Studio target 3992 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3993 public: 3994 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3995 : WindowsX86_64TargetInfo(Triple) { 3996 LongDoubleWidth = LongDoubleAlign = 64; 3997 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3998 } 3999 void getTargetDefines(const LangOptions &Opts, 4000 MacroBuilder &Builder) const override { 4001 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4002 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4003 Builder.defineMacro("_M_X64", "100"); 4004 Builder.defineMacro("_M_AMD64", "100"); 4005 } 4006 }; 4007 4008 // x86-64 MinGW target 4009 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4010 public: 4011 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4012 : WindowsX86_64TargetInfo(Triple) { 4013 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4014 // with x86 FP ops. Weird. 4015 LongDoubleWidth = LongDoubleAlign = 128; 4016 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4017 } 4018 4019 void getTargetDefines(const LangOptions &Opts, 4020 MacroBuilder &Builder) const override { 4021 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4022 DefineStd(Builder, "WIN64", Opts); 4023 Builder.defineMacro("__MINGW64__"); 4024 addMinGWDefines(Opts, Builder); 4025 4026 // GCC defines this macro when it is using __gxx_personality_seh0. 4027 if (!Opts.SjLjExceptions) 4028 Builder.defineMacro("__SEH__"); 4029 } 4030 }; 4031 4032 // x86-64 Cygwin target 4033 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4034 public: 4035 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4036 : X86_64TargetInfo(Triple) { 4037 TLSSupported = false; 4038 WCharType = UnsignedShort; 4039 } 4040 void getTargetDefines(const LangOptions &Opts, 4041 MacroBuilder &Builder) const override { 4042 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4043 Builder.defineMacro("__x86_64__"); 4044 Builder.defineMacro("__CYGWIN__"); 4045 Builder.defineMacro("__CYGWIN64__"); 4046 addCygMingDefines(Opts, Builder); 4047 DefineStd(Builder, "unix", Opts); 4048 if (Opts.CPlusPlus) 4049 Builder.defineMacro("_GNU_SOURCE"); 4050 4051 // GCC defines this macro when it is using __gxx_personality_seh0. 4052 if (!Opts.SjLjExceptions) 4053 Builder.defineMacro("__SEH__"); 4054 } 4055 }; 4056 4057 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4058 public: 4059 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4060 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4061 Int64Type = SignedLongLong; 4062 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4063 llvm::Triple T = llvm::Triple(Triple); 4064 if (T.isiOS()) 4065 UseSignedCharForObjCBool = false; 4066 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 4067 } 4068 4069 bool handleTargetFeatures(std::vector<std::string> &Features, 4070 DiagnosticsEngine &Diags) override { 4071 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4072 Diags)) 4073 return false; 4074 // We now know the features we have: we can decide how to align vectors. 4075 MaxVectorAlign = 4076 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4077 return true; 4078 } 4079 }; 4080 4081 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4082 public: 4083 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4084 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4085 IntMaxType = SignedLongLong; 4086 Int64Type = SignedLongLong; 4087 } 4088 }; 4089 4090 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4091 public: 4092 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4093 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4094 IntMaxType = SignedLongLong; 4095 Int64Type = SignedLongLong; 4096 } 4097 }; 4098 4099 class ARMTargetInfo : public TargetInfo { 4100 // Possible FPU choices. 4101 enum FPUMode { 4102 VFP2FPU = (1 << 0), 4103 VFP3FPU = (1 << 1), 4104 VFP4FPU = (1 << 2), 4105 NeonFPU = (1 << 3), 4106 FPARMV8 = (1 << 4) 4107 }; 4108 4109 // Possible HWDiv features. 4110 enum HWDivMode { 4111 HWDivThumb = (1 << 0), 4112 HWDivARM = (1 << 1) 4113 }; 4114 4115 static bool FPUModeIsVFP(FPUMode Mode) { 4116 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4117 } 4118 4119 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4120 static const char * const GCCRegNames[]; 4121 4122 std::string ABI, CPU; 4123 4124 StringRef CPUProfile; 4125 StringRef CPUAttr; 4126 4127 enum { 4128 FP_Default, 4129 FP_VFP, 4130 FP_Neon 4131 } FPMath; 4132 4133 unsigned ArchISA; 4134 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4135 unsigned ArchProfile; 4136 unsigned ArchVersion; 4137 4138 unsigned FPU : 5; 4139 4140 unsigned IsAAPCS : 1; 4141 unsigned HWDiv : 2; 4142 4143 // Initialized via features. 4144 unsigned SoftFloat : 1; 4145 unsigned SoftFloatABI : 1; 4146 4147 unsigned CRC : 1; 4148 unsigned Crypto : 1; 4149 unsigned DSP : 1; 4150 unsigned Unaligned : 1; 4151 4152 enum { 4153 LDREX_B = (1 << 0), /// byte (8-bit) 4154 LDREX_H = (1 << 1), /// half (16-bit) 4155 LDREX_W = (1 << 2), /// word (32-bit) 4156 LDREX_D = (1 << 3), /// double (64-bit) 4157 }; 4158 4159 uint32_t LDREX; 4160 4161 // ACLE 6.5.1 Hardware floating point 4162 enum { 4163 HW_FP_HP = (1 << 1), /// half (16-bit) 4164 HW_FP_SP = (1 << 2), /// single (32-bit) 4165 HW_FP_DP = (1 << 3), /// double (64-bit) 4166 }; 4167 uint32_t HW_FP; 4168 4169 static const Builtin::Info BuiltinInfo[]; 4170 4171 void setABIAAPCS() { 4172 IsAAPCS = true; 4173 4174 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4175 const llvm::Triple &T = getTriple(); 4176 4177 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4178 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4179 T.getOS() == llvm::Triple::Bitrig) 4180 SizeType = UnsignedLong; 4181 else 4182 SizeType = UnsignedInt; 4183 4184 switch (T.getOS()) { 4185 case llvm::Triple::NetBSD: 4186 WCharType = SignedInt; 4187 break; 4188 case llvm::Triple::Win32: 4189 WCharType = UnsignedShort; 4190 break; 4191 case llvm::Triple::Linux: 4192 default: 4193 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4194 WCharType = UnsignedInt; 4195 break; 4196 } 4197 4198 UseBitFieldTypeAlignment = true; 4199 4200 ZeroLengthBitfieldBoundary = 0; 4201 4202 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4203 // so set preferred for small types to 32. 4204 if (T.isOSBinFormatMachO()) { 4205 DataLayoutString = 4206 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4207 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4208 } else if (T.isOSWindows()) { 4209 assert(!BigEndian && "Windows on ARM does not support big endian"); 4210 DataLayoutString = "e" 4211 "-m:w" 4212 "-p:32:32" 4213 "-i64:64" 4214 "-v128:64:128" 4215 "-a:0:32" 4216 "-n32" 4217 "-S64"; 4218 } else if (T.isOSNaCl()) { 4219 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4220 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4221 } else { 4222 DataLayoutString = 4223 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4224 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4225 } 4226 4227 // FIXME: Enumerated types are variable width in straight AAPCS. 4228 } 4229 4230 void setABIAPCS() { 4231 const llvm::Triple &T = getTriple(); 4232 4233 IsAAPCS = false; 4234 4235 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4236 4237 // size_t is unsigned int on FreeBSD. 4238 if (T.getOS() == llvm::Triple::FreeBSD) 4239 SizeType = UnsignedInt; 4240 else 4241 SizeType = UnsignedLong; 4242 4243 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4244 WCharType = SignedInt; 4245 4246 // Do not respect the alignment of bit-field types when laying out 4247 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4248 UseBitFieldTypeAlignment = false; 4249 4250 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4251 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4252 /// gcc. 4253 ZeroLengthBitfieldBoundary = 32; 4254 4255 if (T.isOSBinFormatMachO()) 4256 DataLayoutString = 4257 BigEndian 4258 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4259 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4260 else 4261 DataLayoutString = 4262 BigEndian 4263 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4264 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4265 4266 // FIXME: Override "preferred align" for double and long long. 4267 } 4268 4269 void setArchInfo() { 4270 StringRef ArchName = getTriple().getArchName(); 4271 4272 ArchISA = llvm::ARM::parseArchISA(ArchName); 4273 CPU = llvm::ARM::getDefaultCPU(ArchName); 4274 unsigned AK = llvm::ARM::parseArch(ArchName); 4275 if (AK != llvm::ARM::AK_INVALID) 4276 ArchKind = AK; 4277 setArchInfo(ArchKind); 4278 } 4279 4280 void setArchInfo(unsigned Kind) { 4281 StringRef SubArch; 4282 4283 // cache TargetParser info 4284 ArchKind = Kind; 4285 SubArch = llvm::ARM::getSubArch(ArchKind); 4286 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4287 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4288 4289 // cache CPU related strings 4290 CPUAttr = getCPUAttr(); 4291 CPUProfile = getCPUProfile(); 4292 } 4293 4294 void setAtomic() { 4295 // when triple does not specify a sub arch, 4296 // then we are not using inline atomics 4297 bool ShouldUseInlineAtomic = 4298 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4299 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4300 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4301 if (ArchProfile == llvm::ARM::PK_M) { 4302 MaxAtomicPromoteWidth = 32; 4303 if (ShouldUseInlineAtomic) 4304 MaxAtomicInlineWidth = 32; 4305 } 4306 else { 4307 MaxAtomicPromoteWidth = 64; 4308 if (ShouldUseInlineAtomic) 4309 MaxAtomicInlineWidth = 64; 4310 } 4311 } 4312 4313 bool isThumb() const { 4314 return (ArchISA == llvm::ARM::IK_THUMB); 4315 } 4316 4317 bool supportsThumb() const { 4318 return CPUAttr.count('T') || ArchVersion >= 6; 4319 } 4320 4321 bool supportsThumb2() const { 4322 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4323 } 4324 4325 StringRef getCPUAttr() const { 4326 // For most sub-arches, the build attribute CPU name is enough. 4327 // For Cortex variants, it's slightly different. 4328 switch(ArchKind) { 4329 default: 4330 return llvm::ARM::getCPUAttr(ArchKind); 4331 case llvm::ARM::AK_ARMV6M: 4332 case llvm::ARM::AK_ARMV6SM: 4333 case llvm::ARM::AK_ARMV6HL: 4334 return "6M"; 4335 case llvm::ARM::AK_ARMV7S: 4336 return "7S"; 4337 case llvm::ARM::AK_ARMV7: 4338 case llvm::ARM::AK_ARMV7A: 4339 case llvm::ARM::AK_ARMV7L: 4340 case llvm::ARM::AK_ARMV7HL: 4341 return "7A"; 4342 case llvm::ARM::AK_ARMV7R: 4343 return "7R"; 4344 case llvm::ARM::AK_ARMV7M: 4345 return "7M"; 4346 case llvm::ARM::AK_ARMV7EM: 4347 return "7EM"; 4348 case llvm::ARM::AK_ARMV8A: 4349 return "8A"; 4350 case llvm::ARM::AK_ARMV8_1A: 4351 return "8_1A"; 4352 } 4353 } 4354 4355 StringRef getCPUProfile() const { 4356 switch(ArchProfile) { 4357 case llvm::ARM::PK_A: 4358 return "A"; 4359 case llvm::ARM::PK_R: 4360 return "R"; 4361 case llvm::ARM::PK_M: 4362 return "M"; 4363 default: 4364 return ""; 4365 } 4366 } 4367 4368 public: 4369 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4370 : TargetInfo(Triple), FPMath(FP_Default), 4371 IsAAPCS(true), LDREX(0), HW_FP(0) { 4372 BigEndian = IsBigEndian; 4373 4374 switch (getTriple().getOS()) { 4375 case llvm::Triple::NetBSD: 4376 PtrDiffType = SignedLong; 4377 break; 4378 default: 4379 PtrDiffType = SignedInt; 4380 break; 4381 } 4382 4383 // Cache arch related info. 4384 setArchInfo(); 4385 4386 // {} in inline assembly are neon specifiers, not assembly variant 4387 // specifiers. 4388 NoAsmVariants = true; 4389 4390 // FIXME: This duplicates code from the driver that sets the -target-abi 4391 // option - this code is used if -target-abi isn't passed and should 4392 // be unified in some way. 4393 if (Triple.isOSBinFormatMachO()) { 4394 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4395 // the frontend matches that. 4396 if (Triple.getEnvironment() == llvm::Triple::EABI || 4397 Triple.getOS() == llvm::Triple::UnknownOS || 4398 StringRef(CPU).startswith("cortex-m")) { 4399 setABI("aapcs"); 4400 } else { 4401 setABI("apcs-gnu"); 4402 } 4403 } else if (Triple.isOSWindows()) { 4404 // FIXME: this is invalid for WindowsCE 4405 setABI("aapcs"); 4406 } else { 4407 // Select the default based on the platform. 4408 switch (Triple.getEnvironment()) { 4409 case llvm::Triple::Android: 4410 case llvm::Triple::GNUEABI: 4411 case llvm::Triple::GNUEABIHF: 4412 setABI("aapcs-linux"); 4413 break; 4414 case llvm::Triple::EABIHF: 4415 case llvm::Triple::EABI: 4416 setABI("aapcs"); 4417 break; 4418 case llvm::Triple::GNU: 4419 setABI("apcs-gnu"); 4420 break; 4421 default: 4422 if (Triple.getOS() == llvm::Triple::NetBSD) 4423 setABI("apcs-gnu"); 4424 else 4425 setABI("aapcs"); 4426 break; 4427 } 4428 } 4429 4430 // ARM targets default to using the ARM C++ ABI. 4431 TheCXXABI.set(TargetCXXABI::GenericARM); 4432 4433 // ARM has atomics up to 8 bytes 4434 setAtomic(); 4435 4436 // Do force alignment of members that follow zero length bitfields. If 4437 // the alignment of the zero-length bitfield is greater than the member 4438 // that follows it, `bar', `bar' will be aligned as the type of the 4439 // zero length bitfield. 4440 UseZeroLengthBitfieldAlignment = true; 4441 } 4442 4443 StringRef getABI() const override { return ABI; } 4444 4445 bool setABI(const std::string &Name) override { 4446 ABI = Name; 4447 4448 // The defaults (above) are for AAPCS, check if we need to change them. 4449 // 4450 // FIXME: We need support for -meabi... we could just mangle it into the 4451 // name. 4452 if (Name == "apcs-gnu") { 4453 setABIAPCS(); 4454 return true; 4455 } 4456 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4457 setABIAAPCS(); 4458 return true; 4459 } 4460 return false; 4461 } 4462 4463 // FIXME: This should be based on Arch attributes, not CPU names. 4464 bool 4465 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4466 StringRef CPU, 4467 const std::vector<std::string> &FeaturesVec) const override { 4468 4469 std::vector<const char*> TargetFeatures; 4470 4471 // get default FPU features 4472 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU); 4473 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4474 4475 // get default Extension features 4476 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU); 4477 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4478 4479 for (const char *Feature : TargetFeatures) 4480 if (Feature[0] == '+') 4481 Features[Feature+1] = true; 4482 4483 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4484 } 4485 4486 bool handleTargetFeatures(std::vector<std::string> &Features, 4487 DiagnosticsEngine &Diags) override { 4488 FPU = 0; 4489 CRC = 0; 4490 Crypto = 0; 4491 DSP = 0; 4492 Unaligned = 1; 4493 SoftFloat = SoftFloatABI = false; 4494 HWDiv = 0; 4495 4496 // This does not diagnose illegal cases like having both 4497 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4498 uint32_t HW_FP_remove = 0; 4499 for (const auto &Feature : Features) { 4500 if (Feature == "+soft-float") { 4501 SoftFloat = true; 4502 } else if (Feature == "+soft-float-abi") { 4503 SoftFloatABI = true; 4504 } else if (Feature == "+vfp2") { 4505 FPU |= VFP2FPU; 4506 HW_FP |= HW_FP_SP | HW_FP_DP; 4507 } else if (Feature == "+vfp3") { 4508 FPU |= VFP3FPU; 4509 HW_FP |= HW_FP_SP | HW_FP_DP; 4510 } else if (Feature == "+vfp4") { 4511 FPU |= VFP4FPU; 4512 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4513 } else if (Feature == "+fp-armv8") { 4514 FPU |= FPARMV8; 4515 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4516 } else if (Feature == "+neon") { 4517 FPU |= NeonFPU; 4518 HW_FP |= HW_FP_SP | HW_FP_DP; 4519 } else if (Feature == "+hwdiv") { 4520 HWDiv |= HWDivThumb; 4521 } else if (Feature == "+hwdiv-arm") { 4522 HWDiv |= HWDivARM; 4523 } else if (Feature == "+crc") { 4524 CRC = 1; 4525 } else if (Feature == "+crypto") { 4526 Crypto = 1; 4527 } else if (Feature == "+dsp") { 4528 DSP = 1; 4529 } else if (Feature == "+fp-only-sp") { 4530 HW_FP_remove |= HW_FP_DP; 4531 } else if (Feature == "+strict-align") { 4532 Unaligned = 0; 4533 } else if (Feature == "+fp16") { 4534 HW_FP |= HW_FP_HP; 4535 } 4536 } 4537 HW_FP &= ~HW_FP_remove; 4538 4539 switch (ArchVersion) { 4540 case 6: 4541 if (ArchProfile == llvm::ARM::PK_M) 4542 LDREX = 0; 4543 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4544 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4545 else 4546 LDREX = LDREX_W; 4547 break; 4548 case 7: 4549 if (ArchProfile == llvm::ARM::PK_M) 4550 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4551 else 4552 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4553 break; 4554 case 8: 4555 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4556 } 4557 4558 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4559 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4560 return false; 4561 } 4562 4563 if (FPMath == FP_Neon) 4564 Features.push_back("+neonfp"); 4565 else if (FPMath == FP_VFP) 4566 Features.push_back("-neonfp"); 4567 4568 // Remove front-end specific options which the backend handles differently. 4569 auto Feature = 4570 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4571 if (Feature != Features.end()) 4572 Features.erase(Feature); 4573 4574 return true; 4575 } 4576 4577 bool hasFeature(StringRef Feature) const override { 4578 return llvm::StringSwitch<bool>(Feature) 4579 .Case("arm", true) 4580 .Case("aarch32", true) 4581 .Case("softfloat", SoftFloat) 4582 .Case("thumb", isThumb()) 4583 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4584 .Case("hwdiv", HWDiv & HWDivThumb) 4585 .Case("hwdiv-arm", HWDiv & HWDivARM) 4586 .Default(false); 4587 } 4588 4589 bool setCPU(const std::string &Name) override { 4590 if (Name != "generic") 4591 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4592 4593 if (ArchKind == llvm::ARM::AK_INVALID) 4594 return false; 4595 setAtomic(); 4596 CPU = Name; 4597 return true; 4598 } 4599 4600 bool setFPMath(StringRef Name) override; 4601 4602 void getTargetDefines(const LangOptions &Opts, 4603 MacroBuilder &Builder) const override { 4604 // Target identification. 4605 Builder.defineMacro("__arm"); 4606 Builder.defineMacro("__arm__"); 4607 4608 // Target properties. 4609 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4610 if (!CPUAttr.empty()) 4611 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4612 4613 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4614 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4615 Builder.defineMacro("__ARM_ARCH", llvm::utostr(ArchVersion)); 4616 4617 if (ArchVersion >= 8) { 4618 // ACLE 6.5.7 Crypto Extension 4619 if (Crypto) 4620 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4621 // ACLE 6.5.8 CRC32 Extension 4622 if (CRC) 4623 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4624 // ACLE 6.5.10 Numeric Maximum and Minimum 4625 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4626 // ACLE 6.5.9 Directed Rounding 4627 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4628 } 4629 4630 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4631 // is not defined for the M-profile. 4632 // NOTE that the deffault profile is assumed to be 'A' 4633 if (CPUProfile.empty() || CPUProfile != "M") 4634 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4635 4636 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4637 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4638 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4639 if (supportsThumb2()) 4640 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4641 else if (supportsThumb()) 4642 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4643 4644 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4645 // instruction set such as ARM or Thumb. 4646 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4647 4648 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4649 4650 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4651 if (!CPUProfile.empty()) 4652 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4653 4654 // ACLE 6.4.3 Unaligned access supported in hardware 4655 if (Unaligned) 4656 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4657 4658 // ACLE 6.4.4 LDREX/STREX 4659 if (LDREX) 4660 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4661 4662 // ACLE 6.4.5 CLZ 4663 if (ArchVersion == 5 || 4664 (ArchVersion == 6 && CPUProfile != "M") || 4665 ArchVersion > 6) 4666 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4667 4668 // ACLE 6.5.1 Hardware Floating Point 4669 if (HW_FP) 4670 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4671 4672 // ACLE predefines. 4673 Builder.defineMacro("__ARM_ACLE", "200"); 4674 4675 // FP16 support (we currently only support IEEE format). 4676 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4677 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4678 4679 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4680 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4681 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4682 4683 // Subtarget options. 4684 4685 // FIXME: It's more complicated than this and we don't really support 4686 // interworking. 4687 // Windows on ARM does not "support" interworking 4688 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4689 Builder.defineMacro("__THUMB_INTERWORK__"); 4690 4691 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4692 // Embedded targets on Darwin follow AAPCS, but not EABI. 4693 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4694 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4695 Builder.defineMacro("__ARM_EABI__"); 4696 Builder.defineMacro("__ARM_PCS", "1"); 4697 4698 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4699 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4700 } 4701 4702 if (SoftFloat) 4703 Builder.defineMacro("__SOFTFP__"); 4704 4705 if (CPU == "xscale") 4706 Builder.defineMacro("__XSCALE__"); 4707 4708 if (isThumb()) { 4709 Builder.defineMacro("__THUMBEL__"); 4710 Builder.defineMacro("__thumb__"); 4711 if (supportsThumb2()) 4712 Builder.defineMacro("__thumb2__"); 4713 } 4714 4715 // ACLE 6.4.9 32-bit SIMD instructions 4716 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4717 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4718 4719 // ACLE 6.4.10 Hardware Integer Divide 4720 if (((HWDiv & HWDivThumb) && isThumb()) || 4721 ((HWDiv & HWDivARM) && !isThumb())) { 4722 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4723 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4724 } 4725 4726 // Note, this is always on in gcc, even though it doesn't make sense. 4727 Builder.defineMacro("__APCS_32__"); 4728 4729 if (FPUModeIsVFP((FPUMode) FPU)) { 4730 Builder.defineMacro("__VFP_FP__"); 4731 if (FPU & VFP2FPU) 4732 Builder.defineMacro("__ARM_VFPV2__"); 4733 if (FPU & VFP3FPU) 4734 Builder.defineMacro("__ARM_VFPV3__"); 4735 if (FPU & VFP4FPU) 4736 Builder.defineMacro("__ARM_VFPV4__"); 4737 } 4738 4739 // This only gets set when Neon instructions are actually available, unlike 4740 // the VFP define, hence the soft float and arch check. This is subtly 4741 // different from gcc, we follow the intent which was that it should be set 4742 // when Neon instructions are actually available. 4743 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4744 Builder.defineMacro("__ARM_NEON", "1"); 4745 Builder.defineMacro("__ARM_NEON__"); 4746 // current AArch32 NEON implementations do not support double-precision 4747 // floating-point even when it is present in VFP. 4748 Builder.defineMacro("__ARM_NEON_FP", 4749 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4750 } 4751 4752 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4753 Opts.ShortWChar ? "2" : "4"); 4754 4755 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4756 Opts.ShortEnums ? "1" : "4"); 4757 4758 if (ArchVersion >= 6 && CPUAttr != "6M") { 4759 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4760 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4761 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4762 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4763 } 4764 4765 // ACLE 6.4.7 DSP instructions 4766 if (DSP) { 4767 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4768 } 4769 4770 // ACLE 6.4.8 Saturation instructions 4771 bool SAT = false; 4772 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4773 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4774 SAT = true; 4775 } 4776 4777 // ACLE 6.4.6 Q (saturation) flag 4778 if (DSP || SAT) 4779 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 4780 4781 if (Opts.UnsafeFPMath) 4782 Builder.defineMacro("__ARM_FP_FAST", "1"); 4783 } 4784 4785 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4786 return llvm::makeArrayRef(BuiltinInfo, 4787 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 4788 } 4789 bool isCLZForZeroUndef() const override { return false; } 4790 BuiltinVaListKind getBuiltinVaListKind() const override { 4791 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4792 } 4793 ArrayRef<const char *> getGCCRegNames() const override; 4794 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 4795 bool validateAsmConstraint(const char *&Name, 4796 TargetInfo::ConstraintInfo &Info) const override { 4797 switch (*Name) { 4798 default: break; 4799 case 'l': // r0-r7 4800 case 'h': // r8-r15 4801 case 'w': // VFP Floating point register single precision 4802 case 'P': // VFP Floating point register double precision 4803 Info.setAllowsRegister(); 4804 return true; 4805 case 'I': 4806 case 'J': 4807 case 'K': 4808 case 'L': 4809 case 'M': 4810 // FIXME 4811 return true; 4812 case 'Q': // A memory address that is a single base register. 4813 Info.setAllowsMemory(); 4814 return true; 4815 case 'U': // a memory reference... 4816 switch (Name[1]) { 4817 case 'q': // ...ARMV4 ldrsb 4818 case 'v': // ...VFP load/store (reg+constant offset) 4819 case 'y': // ...iWMMXt load/store 4820 case 't': // address valid for load/store opaque types wider 4821 // than 128-bits 4822 case 'n': // valid address for Neon doubleword vector load/store 4823 case 'm': // valid address for Neon element and structure load/store 4824 case 's': // valid address for non-offset loads/stores of quad-word 4825 // values in four ARM registers 4826 Info.setAllowsMemory(); 4827 Name++; 4828 return true; 4829 } 4830 } 4831 return false; 4832 } 4833 std::string convertConstraint(const char *&Constraint) const override { 4834 std::string R; 4835 switch (*Constraint) { 4836 case 'U': // Two-character constraint; add "^" hint for later parsing. 4837 R = std::string("^") + std::string(Constraint, 2); 4838 Constraint++; 4839 break; 4840 case 'p': // 'p' should be translated to 'r' by default. 4841 R = std::string("r"); 4842 break; 4843 default: 4844 return std::string(1, *Constraint); 4845 } 4846 return R; 4847 } 4848 bool 4849 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4850 std::string &SuggestedModifier) const override { 4851 bool isOutput = (Constraint[0] == '='); 4852 bool isInOut = (Constraint[0] == '+'); 4853 4854 // Strip off constraint modifiers. 4855 while (Constraint[0] == '=' || 4856 Constraint[0] == '+' || 4857 Constraint[0] == '&') 4858 Constraint = Constraint.substr(1); 4859 4860 switch (Constraint[0]) { 4861 default: break; 4862 case 'r': { 4863 switch (Modifier) { 4864 default: 4865 return (isInOut || isOutput || Size <= 64); 4866 case 'q': 4867 // A register of size 32 cannot fit a vector type. 4868 return false; 4869 } 4870 } 4871 } 4872 4873 return true; 4874 } 4875 const char *getClobbers() const override { 4876 // FIXME: Is this really right? 4877 return ""; 4878 } 4879 4880 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4881 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4882 } 4883 4884 int getEHDataRegisterNumber(unsigned RegNo) const override { 4885 if (RegNo == 0) return 0; 4886 if (RegNo == 1) return 1; 4887 return -1; 4888 } 4889 4890 bool hasSjLjLowering() const override { 4891 return true; 4892 } 4893 }; 4894 4895 bool ARMTargetInfo::setFPMath(StringRef Name) { 4896 if (Name == "neon") { 4897 FPMath = FP_Neon; 4898 return true; 4899 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4900 Name == "vfp4") { 4901 FPMath = FP_VFP; 4902 return true; 4903 } 4904 return false; 4905 } 4906 4907 const char * const ARMTargetInfo::GCCRegNames[] = { 4908 // Integer registers 4909 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4910 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4911 4912 // Float registers 4913 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4914 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4915 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4916 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4917 4918 // Double registers 4919 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4920 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4921 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4922 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4923 4924 // Quad registers 4925 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4926 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4927 }; 4928 4929 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 4930 return llvm::makeArrayRef(GCCRegNames); 4931 } 4932 4933 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4934 { { "a1" }, "r0" }, 4935 { { "a2" }, "r1" }, 4936 { { "a3" }, "r2" }, 4937 { { "a4" }, "r3" }, 4938 { { "v1" }, "r4" }, 4939 { { "v2" }, "r5" }, 4940 { { "v3" }, "r6" }, 4941 { { "v4" }, "r7" }, 4942 { { "v5" }, "r8" }, 4943 { { "v6", "rfp" }, "r9" }, 4944 { { "sl" }, "r10" }, 4945 { { "fp" }, "r11" }, 4946 { { "ip" }, "r12" }, 4947 { { "r13" }, "sp" }, 4948 { { "r14" }, "lr" }, 4949 { { "r15" }, "pc" }, 4950 // The S, D and Q registers overlap, but aren't really aliases; we 4951 // don't want to substitute one of these for a different-sized one. 4952 }; 4953 4954 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 4955 return llvm::makeArrayRef(GCCRegAliases); 4956 } 4957 4958 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4959 #define BUILTIN(ID, TYPE, ATTRS) \ 4960 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 4961 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 4962 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 4963 #include "clang/Basic/BuiltinsNEON.def" 4964 4965 #define BUILTIN(ID, TYPE, ATTRS) \ 4966 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 4967 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 4968 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 4969 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 4970 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 4971 #include "clang/Basic/BuiltinsARM.def" 4972 }; 4973 4974 class ARMleTargetInfo : public ARMTargetInfo { 4975 public: 4976 ARMleTargetInfo(const llvm::Triple &Triple) 4977 : ARMTargetInfo(Triple, false) { } 4978 void getTargetDefines(const LangOptions &Opts, 4979 MacroBuilder &Builder) const override { 4980 Builder.defineMacro("__ARMEL__"); 4981 ARMTargetInfo::getTargetDefines(Opts, Builder); 4982 } 4983 }; 4984 4985 class ARMbeTargetInfo : public ARMTargetInfo { 4986 public: 4987 ARMbeTargetInfo(const llvm::Triple &Triple) 4988 : ARMTargetInfo(Triple, true) { } 4989 void getTargetDefines(const LangOptions &Opts, 4990 MacroBuilder &Builder) const override { 4991 Builder.defineMacro("__ARMEB__"); 4992 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4993 ARMTargetInfo::getTargetDefines(Opts, Builder); 4994 } 4995 }; 4996 4997 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4998 const llvm::Triple Triple; 4999 public: 5000 WindowsARMTargetInfo(const llvm::Triple &Triple) 5001 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 5002 TLSSupported = false; 5003 WCharType = UnsignedShort; 5004 SizeType = UnsignedInt; 5005 UserLabelPrefix = ""; 5006 } 5007 void getVisualStudioDefines(const LangOptions &Opts, 5008 MacroBuilder &Builder) const { 5009 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5010 5011 // FIXME: this is invalid for WindowsCE 5012 Builder.defineMacro("_M_ARM_NT", "1"); 5013 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5014 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5015 5016 assert((Triple.getArch() == llvm::Triple::arm || 5017 Triple.getArch() == llvm::Triple::thumb) && 5018 "invalid architecture for Windows ARM target info"); 5019 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5020 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5021 5022 // TODO map the complete set of values 5023 // 31: VFPv3 40: VFPv4 5024 Builder.defineMacro("_M_ARM_FP", "31"); 5025 } 5026 BuiltinVaListKind getBuiltinVaListKind() const override { 5027 return TargetInfo::CharPtrBuiltinVaList; 5028 } 5029 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5030 switch (CC) { 5031 case CC_X86StdCall: 5032 case CC_X86ThisCall: 5033 case CC_X86FastCall: 5034 case CC_X86VectorCall: 5035 return CCCR_Ignore; 5036 case CC_C: 5037 return CCCR_OK; 5038 default: 5039 return CCCR_Warning; 5040 } 5041 } 5042 }; 5043 5044 // Windows ARM + Itanium C++ ABI Target 5045 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5046 public: 5047 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5048 : WindowsARMTargetInfo(Triple) { 5049 TheCXXABI.set(TargetCXXABI::GenericARM); 5050 } 5051 5052 void getTargetDefines(const LangOptions &Opts, 5053 MacroBuilder &Builder) const override { 5054 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5055 5056 if (Opts.MSVCCompat) 5057 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5058 } 5059 }; 5060 5061 // Windows ARM, MS (C++) ABI 5062 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5063 public: 5064 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5065 : WindowsARMTargetInfo(Triple) { 5066 TheCXXABI.set(TargetCXXABI::Microsoft); 5067 } 5068 5069 void getTargetDefines(const LangOptions &Opts, 5070 MacroBuilder &Builder) const override { 5071 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5072 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5073 } 5074 }; 5075 5076 // ARM MinGW target 5077 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5078 public: 5079 MinGWARMTargetInfo(const llvm::Triple &Triple) 5080 : WindowsARMTargetInfo(Triple) { 5081 TheCXXABI.set(TargetCXXABI::GenericARM); 5082 } 5083 5084 void getTargetDefines(const LangOptions &Opts, 5085 MacroBuilder &Builder) const override { 5086 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5087 DefineStd(Builder, "WIN32", Opts); 5088 DefineStd(Builder, "WINNT", Opts); 5089 Builder.defineMacro("_ARM_"); 5090 addMinGWDefines(Opts, Builder); 5091 } 5092 }; 5093 5094 // ARM Cygwin target 5095 class CygwinARMTargetInfo : public ARMleTargetInfo { 5096 public: 5097 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5098 TLSSupported = false; 5099 WCharType = UnsignedShort; 5100 DoubleAlign = LongLongAlign = 64; 5101 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 5102 } 5103 void getTargetDefines(const LangOptions &Opts, 5104 MacroBuilder &Builder) const override { 5105 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5106 Builder.defineMacro("_ARM_"); 5107 Builder.defineMacro("__CYGWIN__"); 5108 Builder.defineMacro("__CYGWIN32__"); 5109 DefineStd(Builder, "unix", Opts); 5110 if (Opts.CPlusPlus) 5111 Builder.defineMacro("_GNU_SOURCE"); 5112 } 5113 }; 5114 5115 class DarwinARMTargetInfo : 5116 public DarwinTargetInfo<ARMleTargetInfo> { 5117 protected: 5118 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5119 MacroBuilder &Builder) const override { 5120 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5121 } 5122 5123 public: 5124 DarwinARMTargetInfo(const llvm::Triple &Triple) 5125 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5126 HasAlignMac68kSupport = true; 5127 // iOS always has 64-bit atomic instructions. 5128 // FIXME: This should be based off of the target features in 5129 // ARMleTargetInfo. 5130 MaxAtomicInlineWidth = 64; 5131 5132 // Darwin on iOS uses a variant of the ARM C++ ABI. 5133 TheCXXABI.set(TargetCXXABI::iOS); 5134 } 5135 }; 5136 5137 class AArch64TargetInfo : public TargetInfo { 5138 virtual void setDataLayoutString() = 0; 5139 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5140 static const char *const GCCRegNames[]; 5141 5142 enum FPUModeEnum { 5143 FPUMode, 5144 NeonMode 5145 }; 5146 5147 unsigned FPU; 5148 unsigned CRC; 5149 unsigned Crypto; 5150 unsigned Unaligned; 5151 5152 static const Builtin::Info BuiltinInfo[]; 5153 5154 std::string ABI; 5155 5156 public: 5157 AArch64TargetInfo(const llvm::Triple &Triple) 5158 : TargetInfo(Triple), ABI("aapcs") { 5159 5160 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5161 WCharType = SignedInt; 5162 5163 // NetBSD apparently prefers consistency across ARM targets to consistency 5164 // across 64-bit targets. 5165 Int64Type = SignedLongLong; 5166 IntMaxType = SignedLongLong; 5167 } else { 5168 WCharType = UnsignedInt; 5169 Int64Type = SignedLong; 5170 IntMaxType = SignedLong; 5171 } 5172 5173 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5174 MaxVectorAlign = 128; 5175 MaxAtomicInlineWidth = 128; 5176 MaxAtomicPromoteWidth = 128; 5177 5178 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5179 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5180 5181 // {} in inline assembly are neon specifiers, not assembly variant 5182 // specifiers. 5183 NoAsmVariants = true; 5184 5185 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5186 // contributes to the alignment of the containing aggregate in the same way 5187 // a plain (non bit-field) member of that type would, without exception for 5188 // zero-sized or anonymous bit-fields." 5189 UseBitFieldTypeAlignment = true; 5190 UseZeroLengthBitfieldAlignment = true; 5191 5192 // AArch64 targets default to using the ARM C++ ABI. 5193 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5194 } 5195 5196 StringRef getABI() const override { return ABI; } 5197 bool setABI(const std::string &Name) override { 5198 if (Name != "aapcs" && Name != "darwinpcs") 5199 return false; 5200 5201 ABI = Name; 5202 return true; 5203 } 5204 5205 bool setCPU(const std::string &Name) override { 5206 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5207 .Case("generic", true) 5208 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 5209 .Case("cyclone", true) 5210 .Default(false); 5211 return CPUKnown; 5212 } 5213 5214 void getTargetDefines(const LangOptions &Opts, 5215 MacroBuilder &Builder) const override { 5216 // Target identification. 5217 Builder.defineMacro("__aarch64__"); 5218 5219 // Target properties. 5220 Builder.defineMacro("_LP64"); 5221 Builder.defineMacro("__LP64__"); 5222 5223 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5224 Builder.defineMacro("__ARM_ACLE", "200"); 5225 Builder.defineMacro("__ARM_ARCH", "8"); 5226 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5227 5228 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5229 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5230 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5231 5232 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5233 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5234 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5235 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5236 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5237 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5238 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5239 5240 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5241 5242 // 0xe implies support for half, single and double precision operations. 5243 Builder.defineMacro("__ARM_FP", "0xE"); 5244 5245 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5246 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5247 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5248 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5249 5250 if (Opts.UnsafeFPMath) 5251 Builder.defineMacro("__ARM_FP_FAST", "1"); 5252 5253 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5254 5255 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5256 Opts.ShortEnums ? "1" : "4"); 5257 5258 if (FPU == NeonMode) { 5259 Builder.defineMacro("__ARM_NEON", "1"); 5260 // 64-bit NEON supports half, single and double precision operations. 5261 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5262 } 5263 5264 if (CRC) 5265 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5266 5267 if (Crypto) 5268 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5269 5270 if (Unaligned) 5271 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5272 5273 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5274 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5275 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5276 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5277 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5278 } 5279 5280 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5281 return llvm::makeArrayRef(BuiltinInfo, 5282 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5283 } 5284 5285 bool hasFeature(StringRef Feature) const override { 5286 return Feature == "aarch64" || 5287 Feature == "arm64" || 5288 Feature == "arm" || 5289 (Feature == "neon" && FPU == NeonMode); 5290 } 5291 5292 bool handleTargetFeatures(std::vector<std::string> &Features, 5293 DiagnosticsEngine &Diags) override { 5294 FPU = FPUMode; 5295 CRC = 0; 5296 Crypto = 0; 5297 Unaligned = 1; 5298 5299 for (const auto &Feature : Features) { 5300 if (Feature == "+neon") 5301 FPU = NeonMode; 5302 if (Feature == "+crc") 5303 CRC = 1; 5304 if (Feature == "+crypto") 5305 Crypto = 1; 5306 if (Feature == "+strict-align") 5307 Unaligned = 0; 5308 } 5309 5310 setDataLayoutString(); 5311 5312 return true; 5313 } 5314 5315 bool isCLZForZeroUndef() const override { return false; } 5316 5317 BuiltinVaListKind getBuiltinVaListKind() const override { 5318 return TargetInfo::AArch64ABIBuiltinVaList; 5319 } 5320 5321 ArrayRef<const char *> getGCCRegNames() const override; 5322 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5323 5324 bool validateAsmConstraint(const char *&Name, 5325 TargetInfo::ConstraintInfo &Info) const override { 5326 switch (*Name) { 5327 default: 5328 return false; 5329 case 'w': // Floating point and SIMD registers (V0-V31) 5330 Info.setAllowsRegister(); 5331 return true; 5332 case 'I': // Constant that can be used with an ADD instruction 5333 case 'J': // Constant that can be used with a SUB instruction 5334 case 'K': // Constant that can be used with a 32-bit logical instruction 5335 case 'L': // Constant that can be used with a 64-bit logical instruction 5336 case 'M': // Constant that can be used as a 32-bit MOV immediate 5337 case 'N': // Constant that can be used as a 64-bit MOV immediate 5338 case 'Y': // Floating point constant zero 5339 case 'Z': // Integer constant zero 5340 return true; 5341 case 'Q': // A memory reference with base register and no offset 5342 Info.setAllowsMemory(); 5343 return true; 5344 case 'S': // A symbolic address 5345 Info.setAllowsRegister(); 5346 return true; 5347 case 'U': 5348 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5349 // Utf: A memory address suitable for ldp/stp in TF mode. 5350 // Usa: An absolute symbolic address. 5351 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5352 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5353 case 'z': // Zero register, wzr or xzr 5354 Info.setAllowsRegister(); 5355 return true; 5356 case 'x': // Floating point and SIMD registers (V0-V15) 5357 Info.setAllowsRegister(); 5358 return true; 5359 } 5360 return false; 5361 } 5362 5363 bool 5364 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5365 std::string &SuggestedModifier) const override { 5366 // Strip off constraint modifiers. 5367 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5368 Constraint = Constraint.substr(1); 5369 5370 switch (Constraint[0]) { 5371 default: 5372 return true; 5373 case 'z': 5374 case 'r': { 5375 switch (Modifier) { 5376 case 'x': 5377 case 'w': 5378 // For now assume that the person knows what they're 5379 // doing with the modifier. 5380 return true; 5381 default: 5382 // By default an 'r' constraint will be in the 'x' 5383 // registers. 5384 if (Size == 64) 5385 return true; 5386 5387 SuggestedModifier = "w"; 5388 return false; 5389 } 5390 } 5391 } 5392 } 5393 5394 const char *getClobbers() const override { return ""; } 5395 5396 int getEHDataRegisterNumber(unsigned RegNo) const override { 5397 if (RegNo == 0) 5398 return 0; 5399 if (RegNo == 1) 5400 return 1; 5401 return -1; 5402 } 5403 }; 5404 5405 const char *const AArch64TargetInfo::GCCRegNames[] = { 5406 // 32-bit Integer registers 5407 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5408 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5409 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5410 5411 // 64-bit Integer registers 5412 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5413 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5414 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5415 5416 // 32-bit floating point regsisters 5417 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5418 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5419 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5420 5421 // 64-bit floating point regsisters 5422 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5423 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5424 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5425 5426 // Vector registers 5427 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5428 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5429 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5430 }; 5431 5432 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5433 return llvm::makeArrayRef(GCCRegNames); 5434 } 5435 5436 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5437 { { "w31" }, "wsp" }, 5438 { { "x29" }, "fp" }, 5439 { { "x30" }, "lr" }, 5440 { { "x31" }, "sp" }, 5441 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5442 // don't want to substitute one of these for a different-sized one. 5443 }; 5444 5445 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5446 return llvm::makeArrayRef(GCCRegAliases); 5447 } 5448 5449 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5450 #define BUILTIN(ID, TYPE, ATTRS) \ 5451 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5452 #include "clang/Basic/BuiltinsNEON.def" 5453 5454 #define BUILTIN(ID, TYPE, ATTRS) \ 5455 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5456 #include "clang/Basic/BuiltinsAArch64.def" 5457 }; 5458 5459 class AArch64leTargetInfo : public AArch64TargetInfo { 5460 void setDataLayoutString() override { 5461 if (getTriple().isOSBinFormatMachO()) 5462 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5463 else 5464 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5465 } 5466 5467 public: 5468 AArch64leTargetInfo(const llvm::Triple &Triple) 5469 : AArch64TargetInfo(Triple) { 5470 BigEndian = false; 5471 } 5472 void getTargetDefines(const LangOptions &Opts, 5473 MacroBuilder &Builder) const override { 5474 Builder.defineMacro("__AARCH64EL__"); 5475 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5476 } 5477 }; 5478 5479 class AArch64beTargetInfo : public AArch64TargetInfo { 5480 void setDataLayoutString() override { 5481 assert(!getTriple().isOSBinFormatMachO()); 5482 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5483 } 5484 5485 public: 5486 AArch64beTargetInfo(const llvm::Triple &Triple) 5487 : AArch64TargetInfo(Triple) { } 5488 void getTargetDefines(const LangOptions &Opts, 5489 MacroBuilder &Builder) const override { 5490 Builder.defineMacro("__AARCH64EB__"); 5491 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5492 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5493 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5494 } 5495 }; 5496 5497 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5498 protected: 5499 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5500 MacroBuilder &Builder) const override { 5501 Builder.defineMacro("__AARCH64_SIMD__"); 5502 Builder.defineMacro("__ARM64_ARCH_8__"); 5503 Builder.defineMacro("__ARM_NEON__"); 5504 Builder.defineMacro("__LITTLE_ENDIAN__"); 5505 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5506 Builder.defineMacro("__arm64", "1"); 5507 Builder.defineMacro("__arm64__", "1"); 5508 5509 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5510 } 5511 5512 public: 5513 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5514 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5515 Int64Type = SignedLongLong; 5516 WCharType = SignedInt; 5517 UseSignedCharForObjCBool = false; 5518 5519 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5520 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5521 5522 TheCXXABI.set(TargetCXXABI::iOS64); 5523 } 5524 5525 BuiltinVaListKind getBuiltinVaListKind() const override { 5526 return TargetInfo::CharPtrBuiltinVaList; 5527 } 5528 }; 5529 5530 // Hexagon abstract base class 5531 class HexagonTargetInfo : public TargetInfo { 5532 static const Builtin::Info BuiltinInfo[]; 5533 static const char * const GCCRegNames[]; 5534 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5535 std::string CPU; 5536 public: 5537 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5538 BigEndian = false; 5539 DataLayoutString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5540 5541 // {} in inline assembly are packet specifiers, not assembly variant 5542 // specifiers. 5543 NoAsmVariants = true; 5544 } 5545 5546 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5547 return llvm::makeArrayRef(BuiltinInfo, 5548 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5549 } 5550 5551 bool validateAsmConstraint(const char *&Name, 5552 TargetInfo::ConstraintInfo &Info) const override { 5553 return true; 5554 } 5555 5556 void getTargetDefines(const LangOptions &Opts, 5557 MacroBuilder &Builder) const override; 5558 5559 bool hasFeature(StringRef Feature) const override { 5560 return Feature == "hexagon"; 5561 } 5562 5563 BuiltinVaListKind getBuiltinVaListKind() const override { 5564 return TargetInfo::CharPtrBuiltinVaList; 5565 } 5566 ArrayRef<const char *> getGCCRegNames() const override; 5567 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5568 const char *getClobbers() const override { 5569 return ""; 5570 } 5571 5572 static const char *getHexagonCPUSuffix(StringRef Name) { 5573 return llvm::StringSwitch<const char*>(Name) 5574 .Case("hexagonv4", "4") 5575 .Case("hexagonv5", "5") 5576 .Default(nullptr); 5577 } 5578 5579 bool setCPU(const std::string &Name) override { 5580 if (!getHexagonCPUSuffix(Name)) 5581 return false; 5582 5583 CPU = Name; 5584 return true; 5585 } 5586 }; 5587 5588 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5589 MacroBuilder &Builder) const { 5590 Builder.defineMacro("qdsp6"); 5591 Builder.defineMacro("__qdsp6", "1"); 5592 Builder.defineMacro("__qdsp6__", "1"); 5593 5594 Builder.defineMacro("hexagon"); 5595 Builder.defineMacro("__hexagon", "1"); 5596 Builder.defineMacro("__hexagon__", "1"); 5597 5598 if(CPU == "hexagonv1") { 5599 Builder.defineMacro("__HEXAGON_V1__"); 5600 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5601 if(Opts.HexagonQdsp6Compat) { 5602 Builder.defineMacro("__QDSP6_V1__"); 5603 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5604 } 5605 } 5606 else if(CPU == "hexagonv2") { 5607 Builder.defineMacro("__HEXAGON_V2__"); 5608 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5609 if(Opts.HexagonQdsp6Compat) { 5610 Builder.defineMacro("__QDSP6_V2__"); 5611 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5612 } 5613 } 5614 else if(CPU == "hexagonv3") { 5615 Builder.defineMacro("__HEXAGON_V3__"); 5616 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5617 if(Opts.HexagonQdsp6Compat) { 5618 Builder.defineMacro("__QDSP6_V3__"); 5619 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5620 } 5621 } 5622 else if(CPU == "hexagonv4") { 5623 Builder.defineMacro("__HEXAGON_V4__"); 5624 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5625 if(Opts.HexagonQdsp6Compat) { 5626 Builder.defineMacro("__QDSP6_V4__"); 5627 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5628 } 5629 } 5630 else if(CPU == "hexagonv5") { 5631 Builder.defineMacro("__HEXAGON_V5__"); 5632 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5633 if(Opts.HexagonQdsp6Compat) { 5634 Builder.defineMacro("__QDSP6_V5__"); 5635 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5636 } 5637 } 5638 } 5639 5640 const char * const HexagonTargetInfo::GCCRegNames[] = { 5641 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5642 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5643 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5644 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5645 "p0", "p1", "p2", "p3", 5646 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5647 }; 5648 5649 ArrayRef<const char *> HexagonTargetInfo::getGCCRegNames() const { 5650 return llvm::makeArrayRef(GCCRegNames); 5651 } 5652 5653 5654 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5655 { { "sp" }, "r29" }, 5656 { { "fp" }, "r30" }, 5657 { { "lr" }, "r31" }, 5658 }; 5659 5660 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 5661 return llvm::makeArrayRef(GCCRegAliases); 5662 } 5663 5664 5665 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5666 #define BUILTIN(ID, TYPE, ATTRS) \ 5667 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5668 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5669 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5670 #include "clang/Basic/BuiltinsHexagon.def" 5671 }; 5672 5673 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5674 class SparcTargetInfo : public TargetInfo { 5675 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5676 static const char * const GCCRegNames[]; 5677 bool SoftFloat; 5678 public: 5679 SparcTargetInfo(const llvm::Triple &Triple) 5680 : TargetInfo(Triple), SoftFloat(false) {} 5681 5682 bool handleTargetFeatures(std::vector<std::string> &Features, 5683 DiagnosticsEngine &Diags) override { 5684 // The backend doesn't actually handle soft float yet, but in case someone 5685 // is using the support for the front end continue to support it. 5686 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5687 if (Feature != Features.end()) { 5688 SoftFloat = true; 5689 Features.erase(Feature); 5690 } 5691 return true; 5692 } 5693 void getTargetDefines(const LangOptions &Opts, 5694 MacroBuilder &Builder) const override { 5695 DefineStd(Builder, "sparc", Opts); 5696 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5697 5698 if (SoftFloat) 5699 Builder.defineMacro("SOFT_FLOAT", "1"); 5700 } 5701 5702 bool hasFeature(StringRef Feature) const override { 5703 return llvm::StringSwitch<bool>(Feature) 5704 .Case("softfloat", SoftFloat) 5705 .Case("sparc", true) 5706 .Default(false); 5707 } 5708 5709 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5710 // FIXME: Implement! 5711 return None; 5712 } 5713 BuiltinVaListKind getBuiltinVaListKind() const override { 5714 return TargetInfo::VoidPtrBuiltinVaList; 5715 } 5716 ArrayRef<const char *> getGCCRegNames() const override; 5717 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5718 bool validateAsmConstraint(const char *&Name, 5719 TargetInfo::ConstraintInfo &info) const override { 5720 // FIXME: Implement! 5721 switch (*Name) { 5722 case 'I': // Signed 13-bit constant 5723 case 'J': // Zero 5724 case 'K': // 32-bit constant with the low 12 bits clear 5725 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5726 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5727 case 'N': // Same as 'K' but zext (required for SIMode) 5728 case 'O': // The constant 4096 5729 return true; 5730 } 5731 return false; 5732 } 5733 const char *getClobbers() const override { 5734 // FIXME: Implement! 5735 return ""; 5736 } 5737 }; 5738 5739 const char * const SparcTargetInfo::GCCRegNames[] = { 5740 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5741 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5742 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5743 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5744 }; 5745 5746 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 5747 return llvm::makeArrayRef(GCCRegNames); 5748 } 5749 5750 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5751 { { "g0" }, "r0" }, 5752 { { "g1" }, "r1" }, 5753 { { "g2" }, "r2" }, 5754 { { "g3" }, "r3" }, 5755 { { "g4" }, "r4" }, 5756 { { "g5" }, "r5" }, 5757 { { "g6" }, "r6" }, 5758 { { "g7" }, "r7" }, 5759 { { "o0" }, "r8" }, 5760 { { "o1" }, "r9" }, 5761 { { "o2" }, "r10" }, 5762 { { "o3" }, "r11" }, 5763 { { "o4" }, "r12" }, 5764 { { "o5" }, "r13" }, 5765 { { "o6", "sp" }, "r14" }, 5766 { { "o7" }, "r15" }, 5767 { { "l0" }, "r16" }, 5768 { { "l1" }, "r17" }, 5769 { { "l2" }, "r18" }, 5770 { { "l3" }, "r19" }, 5771 { { "l4" }, "r20" }, 5772 { { "l5" }, "r21" }, 5773 { { "l6" }, "r22" }, 5774 { { "l7" }, "r23" }, 5775 { { "i0" }, "r24" }, 5776 { { "i1" }, "r25" }, 5777 { { "i2" }, "r26" }, 5778 { { "i3" }, "r27" }, 5779 { { "i4" }, "r28" }, 5780 { { "i5" }, "r29" }, 5781 { { "i6", "fp" }, "r30" }, 5782 { { "i7" }, "r31" }, 5783 }; 5784 5785 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 5786 return llvm::makeArrayRef(GCCRegAliases); 5787 } 5788 5789 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5790 class SparcV8TargetInfo : public SparcTargetInfo { 5791 public: 5792 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5793 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5794 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 5795 switch (getTriple().getOS()) { 5796 default: 5797 SizeType = UnsignedInt; 5798 IntPtrType = SignedInt; 5799 PtrDiffType = SignedInt; 5800 break; 5801 case llvm::Triple::NetBSD: 5802 case llvm::Triple::OpenBSD: 5803 SizeType = UnsignedLong; 5804 IntPtrType = SignedLong; 5805 PtrDiffType = SignedLong; 5806 break; 5807 } 5808 } 5809 5810 void getTargetDefines(const LangOptions &Opts, 5811 MacroBuilder &Builder) const override { 5812 SparcTargetInfo::getTargetDefines(Opts, Builder); 5813 Builder.defineMacro("__sparcv8"); 5814 } 5815 }; 5816 5817 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 5818 class SparcV8elTargetInfo : public SparcV8TargetInfo { 5819 public: 5820 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 5821 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5822 BigEndian = false; 5823 } 5824 }; 5825 5826 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5827 class SparcV9TargetInfo : public SparcTargetInfo { 5828 public: 5829 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5830 // FIXME: Support Sparc quad-precision long double? 5831 DataLayoutString = "E-m:e-i64:64-n32:64-S128"; 5832 // This is an LP64 platform. 5833 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5834 5835 // OpenBSD uses long long for int64_t and intmax_t. 5836 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5837 IntMaxType = SignedLongLong; 5838 else 5839 IntMaxType = SignedLong; 5840 Int64Type = IntMaxType; 5841 5842 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5843 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5844 LongDoubleWidth = 128; 5845 LongDoubleAlign = 128; 5846 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5847 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5848 } 5849 5850 void getTargetDefines(const LangOptions &Opts, 5851 MacroBuilder &Builder) const override { 5852 SparcTargetInfo::getTargetDefines(Opts, Builder); 5853 Builder.defineMacro("__sparcv9"); 5854 Builder.defineMacro("__arch64__"); 5855 // Solaris doesn't need these variants, but the BSDs do. 5856 if (getTriple().getOS() != llvm::Triple::Solaris) { 5857 Builder.defineMacro("__sparc64__"); 5858 Builder.defineMacro("__sparc_v9__"); 5859 Builder.defineMacro("__sparcv9__"); 5860 } 5861 } 5862 5863 bool setCPU(const std::string &Name) override { 5864 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5865 .Case("v9", true) 5866 .Case("ultrasparc", true) 5867 .Case("ultrasparc3", true) 5868 .Case("niagara", true) 5869 .Case("niagara2", true) 5870 .Case("niagara3", true) 5871 .Case("niagara4", true) 5872 .Default(false); 5873 5874 // No need to store the CPU yet. There aren't any CPU-specific 5875 // macros to define. 5876 return CPUKnown; 5877 } 5878 }; 5879 5880 class SystemZTargetInfo : public TargetInfo { 5881 static const Builtin::Info BuiltinInfo[]; 5882 static const char *const GCCRegNames[]; 5883 std::string CPU; 5884 bool HasTransactionalExecution; 5885 bool HasVector; 5886 5887 public: 5888 SystemZTargetInfo(const llvm::Triple &Triple) 5889 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 5890 HasVector(false) { 5891 IntMaxType = SignedLong; 5892 Int64Type = SignedLong; 5893 TLSSupported = true; 5894 IntWidth = IntAlign = 32; 5895 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5896 PointerWidth = PointerAlign = 64; 5897 LongDoubleWidth = 128; 5898 LongDoubleAlign = 64; 5899 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5900 DefaultAlignForAttributeAligned = 64; 5901 MinGlobalAlign = 16; 5902 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5903 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5904 } 5905 void getTargetDefines(const LangOptions &Opts, 5906 MacroBuilder &Builder) const override { 5907 Builder.defineMacro("__s390__"); 5908 Builder.defineMacro("__s390x__"); 5909 Builder.defineMacro("__zarch__"); 5910 Builder.defineMacro("__LONG_DOUBLE_128__"); 5911 if (HasTransactionalExecution) 5912 Builder.defineMacro("__HTM__"); 5913 if (Opts.ZVector) 5914 Builder.defineMacro("__VEC__", "10301"); 5915 } 5916 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5917 return llvm::makeArrayRef(BuiltinInfo, 5918 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 5919 } 5920 5921 ArrayRef<const char *> getGCCRegNames() const override; 5922 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 5923 // No aliases. 5924 return None; 5925 } 5926 bool validateAsmConstraint(const char *&Name, 5927 TargetInfo::ConstraintInfo &info) const override; 5928 const char *getClobbers() const override { 5929 // FIXME: Is this really right? 5930 return ""; 5931 } 5932 BuiltinVaListKind getBuiltinVaListKind() const override { 5933 return TargetInfo::SystemZBuiltinVaList; 5934 } 5935 bool setCPU(const std::string &Name) override { 5936 CPU = Name; 5937 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5938 .Case("z10", true) 5939 .Case("z196", true) 5940 .Case("zEC12", true) 5941 .Case("z13", true) 5942 .Default(false); 5943 5944 return CPUKnown; 5945 } 5946 bool 5947 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5948 StringRef CPU, 5949 const std::vector<std::string> &FeaturesVec) const override { 5950 if (CPU == "zEC12") 5951 Features["transactional-execution"] = true; 5952 if (CPU == "z13") { 5953 Features["transactional-execution"] = true; 5954 Features["vector"] = true; 5955 } 5956 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5957 } 5958 5959 bool handleTargetFeatures(std::vector<std::string> &Features, 5960 DiagnosticsEngine &Diags) override { 5961 HasTransactionalExecution = false; 5962 for (const auto &Feature : Features) { 5963 if (Feature == "+transactional-execution") 5964 HasTransactionalExecution = true; 5965 else if (Feature == "+vector") 5966 HasVector = true; 5967 } 5968 // If we use the vector ABI, vector types are 64-bit aligned. 5969 if (HasVector) { 5970 MaxVectorAlign = 64; 5971 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 5972 "-v128:64-a:8:16-n32:64"; 5973 } 5974 return true; 5975 } 5976 5977 bool hasFeature(StringRef Feature) const override { 5978 return llvm::StringSwitch<bool>(Feature) 5979 .Case("systemz", true) 5980 .Case("htm", HasTransactionalExecution) 5981 .Case("vx", HasVector) 5982 .Default(false); 5983 } 5984 5985 StringRef getABI() const override { 5986 if (HasVector) 5987 return "vector"; 5988 return ""; 5989 } 5990 5991 bool useFloat128ManglingForLongDouble() const override { 5992 return true; 5993 } 5994 }; 5995 5996 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 5997 #define BUILTIN(ID, TYPE, ATTRS) \ 5998 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5999 #include "clang/Basic/BuiltinsSystemZ.def" 6000 }; 6001 6002 const char *const SystemZTargetInfo::GCCRegNames[] = { 6003 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6004 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6005 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6006 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6007 }; 6008 6009 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6010 return llvm::makeArrayRef(GCCRegNames); 6011 } 6012 6013 bool SystemZTargetInfo:: 6014 validateAsmConstraint(const char *&Name, 6015 TargetInfo::ConstraintInfo &Info) const { 6016 switch (*Name) { 6017 default: 6018 return false; 6019 6020 case 'a': // Address register 6021 case 'd': // Data register (equivalent to 'r') 6022 case 'f': // Floating-point register 6023 Info.setAllowsRegister(); 6024 return true; 6025 6026 case 'I': // Unsigned 8-bit constant 6027 case 'J': // Unsigned 12-bit constant 6028 case 'K': // Signed 16-bit constant 6029 case 'L': // Signed 20-bit displacement (on all targets we support) 6030 case 'M': // 0x7fffffff 6031 return true; 6032 6033 case 'Q': // Memory with base and unsigned 12-bit displacement 6034 case 'R': // Likewise, plus an index 6035 case 'S': // Memory with base and signed 20-bit displacement 6036 case 'T': // Likewise, plus an index 6037 Info.setAllowsMemory(); 6038 return true; 6039 } 6040 } 6041 6042 class MSP430TargetInfo : public TargetInfo { 6043 static const char *const GCCRegNames[]; 6044 6045 public: 6046 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6047 BigEndian = false; 6048 TLSSupported = false; 6049 IntWidth = 16; 6050 IntAlign = 16; 6051 LongWidth = 32; 6052 LongLongWidth = 64; 6053 LongAlign = LongLongAlign = 16; 6054 PointerWidth = 16; 6055 PointerAlign = 16; 6056 SuitableAlign = 16; 6057 SizeType = UnsignedInt; 6058 IntMaxType = SignedLongLong; 6059 IntPtrType = SignedInt; 6060 PtrDiffType = SignedInt; 6061 SigAtomicType = SignedLong; 6062 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 6063 } 6064 void getTargetDefines(const LangOptions &Opts, 6065 MacroBuilder &Builder) const override { 6066 Builder.defineMacro("MSP430"); 6067 Builder.defineMacro("__MSP430__"); 6068 // FIXME: defines for different 'flavours' of MCU 6069 } 6070 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6071 // FIXME: Implement. 6072 return None; 6073 } 6074 bool hasFeature(StringRef Feature) const override { 6075 return Feature == "msp430"; 6076 } 6077 ArrayRef<const char *> getGCCRegNames() const override; 6078 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6079 // No aliases. 6080 return None; 6081 } 6082 bool validateAsmConstraint(const char *&Name, 6083 TargetInfo::ConstraintInfo &info) const override { 6084 // FIXME: implement 6085 switch (*Name) { 6086 case 'K': // the constant 1 6087 case 'L': // constant -1^20 .. 1^19 6088 case 'M': // constant 1-4: 6089 return true; 6090 } 6091 // No target constraints for now. 6092 return false; 6093 } 6094 const char *getClobbers() const override { 6095 // FIXME: Is this really right? 6096 return ""; 6097 } 6098 BuiltinVaListKind getBuiltinVaListKind() const override { 6099 // FIXME: implement 6100 return TargetInfo::CharPtrBuiltinVaList; 6101 } 6102 }; 6103 6104 const char *const MSP430TargetInfo::GCCRegNames[] = { 6105 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6106 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6107 6108 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6109 return llvm::makeArrayRef(GCCRegNames); 6110 } 6111 6112 // LLVM and Clang cannot be used directly to output native binaries for 6113 // target, but is used to compile C code to llvm bitcode with correct 6114 // type and alignment information. 6115 // 6116 // TCE uses the llvm bitcode as input and uses it for generating customized 6117 // target processor and program binary. TCE co-design environment is 6118 // publicly available in http://tce.cs.tut.fi 6119 6120 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6121 3, // opencl_global 6122 4, // opencl_local 6123 5, // opencl_constant 6124 // FIXME: generic has to be added to the target 6125 0, // opencl_generic 6126 0, // cuda_device 6127 0, // cuda_constant 6128 0 // cuda_shared 6129 }; 6130 6131 class TCETargetInfo : public TargetInfo { 6132 public: 6133 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6134 TLSSupported = false; 6135 IntWidth = 32; 6136 LongWidth = LongLongWidth = 32; 6137 PointerWidth = 32; 6138 IntAlign = 32; 6139 LongAlign = LongLongAlign = 32; 6140 PointerAlign = 32; 6141 SuitableAlign = 32; 6142 SizeType = UnsignedInt; 6143 IntMaxType = SignedLong; 6144 IntPtrType = SignedInt; 6145 PtrDiffType = SignedInt; 6146 FloatWidth = 32; 6147 FloatAlign = 32; 6148 DoubleWidth = 32; 6149 DoubleAlign = 32; 6150 LongDoubleWidth = 32; 6151 LongDoubleAlign = 32; 6152 FloatFormat = &llvm::APFloat::IEEEsingle; 6153 DoubleFormat = &llvm::APFloat::IEEEsingle; 6154 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6155 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6156 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6157 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6158 UseAddrSpaceMapMangling = true; 6159 } 6160 6161 void getTargetDefines(const LangOptions &Opts, 6162 MacroBuilder &Builder) const override { 6163 DefineStd(Builder, "tce", Opts); 6164 Builder.defineMacro("__TCE__"); 6165 Builder.defineMacro("__TCE_V1__"); 6166 } 6167 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6168 6169 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6170 const char *getClobbers() const override { return ""; } 6171 BuiltinVaListKind getBuiltinVaListKind() const override { 6172 return TargetInfo::VoidPtrBuiltinVaList; 6173 } 6174 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6175 bool validateAsmConstraint(const char *&Name, 6176 TargetInfo::ConstraintInfo &info) const override { 6177 return true; 6178 } 6179 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6180 return None; 6181 } 6182 }; 6183 6184 class BPFTargetInfo : public TargetInfo { 6185 public: 6186 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6187 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6188 SizeType = UnsignedLong; 6189 PtrDiffType = SignedLong; 6190 IntPtrType = SignedLong; 6191 IntMaxType = SignedLong; 6192 Int64Type = SignedLong; 6193 RegParmMax = 5; 6194 if (Triple.getArch() == llvm::Triple::bpfeb) { 6195 BigEndian = true; 6196 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6197 } else { 6198 BigEndian = false; 6199 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6200 } 6201 MaxAtomicPromoteWidth = 64; 6202 MaxAtomicInlineWidth = 64; 6203 TLSSupported = false; 6204 } 6205 void getTargetDefines(const LangOptions &Opts, 6206 MacroBuilder &Builder) const override { 6207 DefineStd(Builder, "bpf", Opts); 6208 Builder.defineMacro("__BPF__"); 6209 } 6210 bool hasFeature(StringRef Feature) const override { 6211 return Feature == "bpf"; 6212 } 6213 6214 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6215 const char *getClobbers() const override { 6216 return ""; 6217 } 6218 BuiltinVaListKind getBuiltinVaListKind() const override { 6219 return TargetInfo::VoidPtrBuiltinVaList; 6220 } 6221 ArrayRef<const char *> getGCCRegNames() const override { 6222 return None; 6223 } 6224 bool validateAsmConstraint(const char *&Name, 6225 TargetInfo::ConstraintInfo &info) const override { 6226 return true; 6227 } 6228 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6229 return None; 6230 } 6231 }; 6232 6233 class MipsTargetInfoBase : public TargetInfo { 6234 virtual void setDataLayoutString() = 0; 6235 6236 static const Builtin::Info BuiltinInfo[]; 6237 std::string CPU; 6238 bool IsMips16; 6239 bool IsMicromips; 6240 bool IsNan2008; 6241 bool IsSingleFloat; 6242 enum MipsFloatABI { 6243 HardFloat, SoftFloat 6244 } FloatABI; 6245 enum DspRevEnum { 6246 NoDSP, DSP1, DSP2 6247 } DspRev; 6248 bool HasMSA; 6249 6250 protected: 6251 bool HasFP64; 6252 std::string ABI; 6253 6254 public: 6255 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6256 const std::string &CPUStr) 6257 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6258 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6259 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6260 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6261 } 6262 6263 bool isNaN2008Default() const { 6264 return CPU == "mips32r6" || CPU == "mips64r6"; 6265 } 6266 6267 bool isFP64Default() const { 6268 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6269 } 6270 6271 bool isNan2008() const override { 6272 return IsNan2008; 6273 } 6274 6275 StringRef getABI() const override { return ABI; } 6276 bool setCPU(const std::string &Name) override { 6277 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6278 getTriple().getArch() == llvm::Triple::mipsel; 6279 CPU = Name; 6280 return llvm::StringSwitch<bool>(Name) 6281 .Case("mips1", IsMips32) 6282 .Case("mips2", IsMips32) 6283 .Case("mips3", true) 6284 .Case("mips4", true) 6285 .Case("mips5", true) 6286 .Case("mips32", IsMips32) 6287 .Case("mips32r2", IsMips32) 6288 .Case("mips32r3", IsMips32) 6289 .Case("mips32r5", IsMips32) 6290 .Case("mips32r6", IsMips32) 6291 .Case("mips64", true) 6292 .Case("mips64r2", true) 6293 .Case("mips64r3", true) 6294 .Case("mips64r5", true) 6295 .Case("mips64r6", true) 6296 .Case("octeon", true) 6297 .Case("p5600", true) 6298 .Default(false); 6299 } 6300 const std::string& getCPU() const { return CPU; } 6301 bool 6302 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6303 StringRef CPU, 6304 const std::vector<std::string> &FeaturesVec) const override { 6305 if (CPU == "octeon") 6306 Features["mips64r2"] = Features["cnmips"] = true; 6307 else 6308 Features[CPU] = true; 6309 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6310 } 6311 6312 void getTargetDefines(const LangOptions &Opts, 6313 MacroBuilder &Builder) const override { 6314 Builder.defineMacro("__mips__"); 6315 Builder.defineMacro("_mips"); 6316 if (Opts.GNUMode) 6317 Builder.defineMacro("mips"); 6318 6319 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6320 6321 switch (FloatABI) { 6322 case HardFloat: 6323 Builder.defineMacro("__mips_hard_float", Twine(1)); 6324 break; 6325 case SoftFloat: 6326 Builder.defineMacro("__mips_soft_float", Twine(1)); 6327 break; 6328 } 6329 6330 if (IsSingleFloat) 6331 Builder.defineMacro("__mips_single_float", Twine(1)); 6332 6333 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6334 Builder.defineMacro("_MIPS_FPSET", 6335 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6336 6337 if (IsMips16) 6338 Builder.defineMacro("__mips16", Twine(1)); 6339 6340 if (IsMicromips) 6341 Builder.defineMacro("__mips_micromips", Twine(1)); 6342 6343 if (IsNan2008) 6344 Builder.defineMacro("__mips_nan2008", Twine(1)); 6345 6346 switch (DspRev) { 6347 default: 6348 break; 6349 case DSP1: 6350 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6351 Builder.defineMacro("__mips_dsp", Twine(1)); 6352 break; 6353 case DSP2: 6354 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6355 Builder.defineMacro("__mips_dspr2", Twine(1)); 6356 Builder.defineMacro("__mips_dsp", Twine(1)); 6357 break; 6358 } 6359 6360 if (HasMSA) 6361 Builder.defineMacro("__mips_msa", Twine(1)); 6362 6363 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6364 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6365 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6366 6367 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6368 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6369 } 6370 6371 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6372 return llvm::makeArrayRef(BuiltinInfo, 6373 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 6374 } 6375 bool hasFeature(StringRef Feature) const override { 6376 return llvm::StringSwitch<bool>(Feature) 6377 .Case("mips", true) 6378 .Case("fp64", HasFP64) 6379 .Default(false); 6380 } 6381 BuiltinVaListKind getBuiltinVaListKind() const override { 6382 return TargetInfo::VoidPtrBuiltinVaList; 6383 } 6384 ArrayRef<const char *> getGCCRegNames() const override { 6385 static const char *const GCCRegNames[] = { 6386 // CPU register names 6387 // Must match second column of GCCRegAliases 6388 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6389 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6390 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6391 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6392 // Floating point register names 6393 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6394 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6395 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6396 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6397 // Hi/lo and condition register names 6398 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6399 "$fcc5","$fcc6","$fcc7", 6400 // MSA register names 6401 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6402 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6403 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6404 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6405 // MSA control register names 6406 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6407 "$msarequest", "$msamap", "$msaunmap" 6408 }; 6409 return llvm::makeArrayRef(GCCRegNames); 6410 } 6411 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 6412 bool validateAsmConstraint(const char *&Name, 6413 TargetInfo::ConstraintInfo &Info) const override { 6414 switch (*Name) { 6415 default: 6416 return false; 6417 case 'r': // CPU registers. 6418 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6419 case 'y': // Equivalent to "r", backward compatibility only. 6420 case 'f': // floating-point registers. 6421 case 'c': // $25 for indirect jumps 6422 case 'l': // lo register 6423 case 'x': // hilo register pair 6424 Info.setAllowsRegister(); 6425 return true; 6426 case 'I': // Signed 16-bit constant 6427 case 'J': // Integer 0 6428 case 'K': // Unsigned 16-bit constant 6429 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6430 case 'M': // Constants not loadable via lui, addiu, or ori 6431 case 'N': // Constant -1 to -65535 6432 case 'O': // A signed 15-bit constant 6433 case 'P': // A constant between 1 go 65535 6434 return true; 6435 case 'R': // An address that can be used in a non-macro load or store 6436 Info.setAllowsMemory(); 6437 return true; 6438 case 'Z': 6439 if (Name[1] == 'C') { // An address usable by ll, and sc. 6440 Info.setAllowsMemory(); 6441 Name++; // Skip over 'Z'. 6442 return true; 6443 } 6444 return false; 6445 } 6446 } 6447 6448 std::string convertConstraint(const char *&Constraint) const override { 6449 std::string R; 6450 switch (*Constraint) { 6451 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6452 if (Constraint[1] == 'C') { 6453 R = std::string("^") + std::string(Constraint, 2); 6454 Constraint++; 6455 return R; 6456 } 6457 break; 6458 } 6459 return TargetInfo::convertConstraint(Constraint); 6460 } 6461 6462 const char *getClobbers() const override { 6463 // In GCC, $1 is not widely used in generated code (it's used only in a few 6464 // specific situations), so there is no real need for users to add it to 6465 // the clobbers list if they want to use it in their inline assembly code. 6466 // 6467 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6468 // code generation, so using it in inline assembly without adding it to the 6469 // clobbers list can cause conflicts between the inline assembly code and 6470 // the surrounding generated code. 6471 // 6472 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6473 // operands, which will conflict with the ".set at" assembler option (which 6474 // we use only for inline assembly, in order to maintain compatibility with 6475 // GCC) and will also conflict with the user's usage of $1. 6476 // 6477 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6478 // register for generated code is to automatically clobber $1 for all inline 6479 // assembly code. 6480 // 6481 // FIXME: We should automatically clobber $1 only for inline assembly code 6482 // which actually uses it. This would allow LLVM to use $1 for inline 6483 // assembly operands if the user's assembly code doesn't use it. 6484 return "~{$1}"; 6485 } 6486 6487 bool handleTargetFeatures(std::vector<std::string> &Features, 6488 DiagnosticsEngine &Diags) override { 6489 IsMips16 = false; 6490 IsMicromips = false; 6491 IsNan2008 = isNaN2008Default(); 6492 IsSingleFloat = false; 6493 FloatABI = HardFloat; 6494 DspRev = NoDSP; 6495 HasFP64 = isFP64Default(); 6496 6497 for (const auto &Feature : Features) { 6498 if (Feature == "+single-float") 6499 IsSingleFloat = true; 6500 else if (Feature == "+soft-float") 6501 FloatABI = SoftFloat; 6502 else if (Feature == "+mips16") 6503 IsMips16 = true; 6504 else if (Feature == "+micromips") 6505 IsMicromips = true; 6506 else if (Feature == "+dsp") 6507 DspRev = std::max(DspRev, DSP1); 6508 else if (Feature == "+dspr2") 6509 DspRev = std::max(DspRev, DSP2); 6510 else if (Feature == "+msa") 6511 HasMSA = true; 6512 else if (Feature == "+fp64") 6513 HasFP64 = true; 6514 else if (Feature == "-fp64") 6515 HasFP64 = false; 6516 else if (Feature == "+nan2008") 6517 IsNan2008 = true; 6518 else if (Feature == "-nan2008") 6519 IsNan2008 = false; 6520 } 6521 6522 setDataLayoutString(); 6523 6524 return true; 6525 } 6526 6527 int getEHDataRegisterNumber(unsigned RegNo) const override { 6528 if (RegNo == 0) return 4; 6529 if (RegNo == 1) return 5; 6530 return -1; 6531 } 6532 6533 bool isCLZForZeroUndef() const override { return false; } 6534 }; 6535 6536 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6537 #define BUILTIN(ID, TYPE, ATTRS) \ 6538 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6539 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6540 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6541 #include "clang/Basic/BuiltinsMips.def" 6542 }; 6543 6544 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6545 public: 6546 Mips32TargetInfoBase(const llvm::Triple &Triple) 6547 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6548 SizeType = UnsignedInt; 6549 PtrDiffType = SignedInt; 6550 Int64Type = SignedLongLong; 6551 IntMaxType = Int64Type; 6552 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6553 } 6554 bool setABI(const std::string &Name) override { 6555 if (Name == "o32" || Name == "eabi") { 6556 ABI = Name; 6557 return true; 6558 } 6559 return false; 6560 } 6561 void getTargetDefines(const LangOptions &Opts, 6562 MacroBuilder &Builder) const override { 6563 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6564 6565 Builder.defineMacro("__mips", "32"); 6566 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6567 6568 const std::string& CPUStr = getCPU(); 6569 if (CPUStr == "mips32") 6570 Builder.defineMacro("__mips_isa_rev", "1"); 6571 else if (CPUStr == "mips32r2") 6572 Builder.defineMacro("__mips_isa_rev", "2"); 6573 else if (CPUStr == "mips32r3") 6574 Builder.defineMacro("__mips_isa_rev", "3"); 6575 else if (CPUStr == "mips32r5") 6576 Builder.defineMacro("__mips_isa_rev", "5"); 6577 else if (CPUStr == "mips32r6") 6578 Builder.defineMacro("__mips_isa_rev", "6"); 6579 6580 if (ABI == "o32") { 6581 Builder.defineMacro("__mips_o32"); 6582 Builder.defineMacro("_ABIO32", "1"); 6583 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6584 } 6585 else if (ABI == "eabi") 6586 Builder.defineMacro("__mips_eabi"); 6587 else 6588 llvm_unreachable("Invalid ABI for Mips32."); 6589 } 6590 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6591 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6592 { { "at" }, "$1" }, 6593 { { "v0" }, "$2" }, 6594 { { "v1" }, "$3" }, 6595 { { "a0" }, "$4" }, 6596 { { "a1" }, "$5" }, 6597 { { "a2" }, "$6" }, 6598 { { "a3" }, "$7" }, 6599 { { "t0" }, "$8" }, 6600 { { "t1" }, "$9" }, 6601 { { "t2" }, "$10" }, 6602 { { "t3" }, "$11" }, 6603 { { "t4" }, "$12" }, 6604 { { "t5" }, "$13" }, 6605 { { "t6" }, "$14" }, 6606 { { "t7" }, "$15" }, 6607 { { "s0" }, "$16" }, 6608 { { "s1" }, "$17" }, 6609 { { "s2" }, "$18" }, 6610 { { "s3" }, "$19" }, 6611 { { "s4" }, "$20" }, 6612 { { "s5" }, "$21" }, 6613 { { "s6" }, "$22" }, 6614 { { "s7" }, "$23" }, 6615 { { "t8" }, "$24" }, 6616 { { "t9" }, "$25" }, 6617 { { "k0" }, "$26" }, 6618 { { "k1" }, "$27" }, 6619 { { "gp" }, "$28" }, 6620 { { "sp","$sp" }, "$29" }, 6621 { { "fp","$fp" }, "$30" }, 6622 { { "ra" }, "$31" } 6623 }; 6624 return llvm::makeArrayRef(GCCRegAliases); 6625 } 6626 }; 6627 6628 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6629 void setDataLayoutString() override { 6630 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6631 } 6632 6633 public: 6634 Mips32EBTargetInfo(const llvm::Triple &Triple) 6635 : Mips32TargetInfoBase(Triple) { 6636 } 6637 void getTargetDefines(const LangOptions &Opts, 6638 MacroBuilder &Builder) const override { 6639 DefineStd(Builder, "MIPSEB", Opts); 6640 Builder.defineMacro("_MIPSEB"); 6641 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6642 } 6643 }; 6644 6645 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6646 void setDataLayoutString() override { 6647 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6648 } 6649 6650 public: 6651 Mips32ELTargetInfo(const llvm::Triple &Triple) 6652 : Mips32TargetInfoBase(Triple) { 6653 BigEndian = false; 6654 } 6655 void getTargetDefines(const LangOptions &Opts, 6656 MacroBuilder &Builder) const override { 6657 DefineStd(Builder, "MIPSEL", Opts); 6658 Builder.defineMacro("_MIPSEL"); 6659 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6660 } 6661 }; 6662 6663 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6664 public: 6665 Mips64TargetInfoBase(const llvm::Triple &Triple) 6666 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6667 LongDoubleWidth = LongDoubleAlign = 128; 6668 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6669 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6670 LongDoubleWidth = LongDoubleAlign = 64; 6671 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6672 } 6673 setN64ABITypes(); 6674 SuitableAlign = 128; 6675 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6676 } 6677 6678 void setN64ABITypes() { 6679 LongWidth = LongAlign = 64; 6680 PointerWidth = PointerAlign = 64; 6681 SizeType = UnsignedLong; 6682 PtrDiffType = SignedLong; 6683 Int64Type = SignedLong; 6684 IntMaxType = Int64Type; 6685 } 6686 6687 void setN32ABITypes() { 6688 LongWidth = LongAlign = 32; 6689 PointerWidth = PointerAlign = 32; 6690 SizeType = UnsignedInt; 6691 PtrDiffType = SignedInt; 6692 Int64Type = SignedLongLong; 6693 IntMaxType = Int64Type; 6694 } 6695 6696 bool setABI(const std::string &Name) override { 6697 if (Name == "n32") { 6698 setN32ABITypes(); 6699 ABI = Name; 6700 return true; 6701 } 6702 if (Name == "n64") { 6703 setN64ABITypes(); 6704 ABI = Name; 6705 return true; 6706 } 6707 return false; 6708 } 6709 6710 void getTargetDefines(const LangOptions &Opts, 6711 MacroBuilder &Builder) const override { 6712 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6713 6714 Builder.defineMacro("__mips", "64"); 6715 Builder.defineMacro("__mips64"); 6716 Builder.defineMacro("__mips64__"); 6717 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6718 6719 const std::string& CPUStr = getCPU(); 6720 if (CPUStr == "mips64") 6721 Builder.defineMacro("__mips_isa_rev", "1"); 6722 else if (CPUStr == "mips64r2") 6723 Builder.defineMacro("__mips_isa_rev", "2"); 6724 else if (CPUStr == "mips64r3") 6725 Builder.defineMacro("__mips_isa_rev", "3"); 6726 else if (CPUStr == "mips64r5") 6727 Builder.defineMacro("__mips_isa_rev", "5"); 6728 else if (CPUStr == "mips64r6") 6729 Builder.defineMacro("__mips_isa_rev", "6"); 6730 6731 if (ABI == "n32") { 6732 Builder.defineMacro("__mips_n32"); 6733 Builder.defineMacro("_ABIN32", "2"); 6734 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6735 } 6736 else if (ABI == "n64") { 6737 Builder.defineMacro("__mips_n64"); 6738 Builder.defineMacro("_ABI64", "3"); 6739 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6740 } 6741 else 6742 llvm_unreachable("Invalid ABI for Mips64."); 6743 } 6744 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6745 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6746 { { "at" }, "$1" }, 6747 { { "v0" }, "$2" }, 6748 { { "v1" }, "$3" }, 6749 { { "a0" }, "$4" }, 6750 { { "a1" }, "$5" }, 6751 { { "a2" }, "$6" }, 6752 { { "a3" }, "$7" }, 6753 { { "a4" }, "$8" }, 6754 { { "a5" }, "$9" }, 6755 { { "a6" }, "$10" }, 6756 { { "a7" }, "$11" }, 6757 { { "t0" }, "$12" }, 6758 { { "t1" }, "$13" }, 6759 { { "t2" }, "$14" }, 6760 { { "t3" }, "$15" }, 6761 { { "s0" }, "$16" }, 6762 { { "s1" }, "$17" }, 6763 { { "s2" }, "$18" }, 6764 { { "s3" }, "$19" }, 6765 { { "s4" }, "$20" }, 6766 { { "s5" }, "$21" }, 6767 { { "s6" }, "$22" }, 6768 { { "s7" }, "$23" }, 6769 { { "t8" }, "$24" }, 6770 { { "t9" }, "$25" }, 6771 { { "k0" }, "$26" }, 6772 { { "k1" }, "$27" }, 6773 { { "gp" }, "$28" }, 6774 { { "sp","$sp" }, "$29" }, 6775 { { "fp","$fp" }, "$30" }, 6776 { { "ra" }, "$31" } 6777 }; 6778 return llvm::makeArrayRef(GCCRegAliases); 6779 } 6780 6781 bool hasInt128Type() const override { return true; } 6782 }; 6783 6784 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6785 void setDataLayoutString() override { 6786 if (ABI == "n32") 6787 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6788 else 6789 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6790 6791 } 6792 6793 public: 6794 Mips64EBTargetInfo(const llvm::Triple &Triple) 6795 : Mips64TargetInfoBase(Triple) {} 6796 void getTargetDefines(const LangOptions &Opts, 6797 MacroBuilder &Builder) const override { 6798 DefineStd(Builder, "MIPSEB", Opts); 6799 Builder.defineMacro("_MIPSEB"); 6800 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6801 } 6802 }; 6803 6804 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6805 void setDataLayoutString() override { 6806 if (ABI == "n32") 6807 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6808 else 6809 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6810 } 6811 public: 6812 Mips64ELTargetInfo(const llvm::Triple &Triple) 6813 : Mips64TargetInfoBase(Triple) { 6814 // Default ABI is n64. 6815 BigEndian = false; 6816 } 6817 void getTargetDefines(const LangOptions &Opts, 6818 MacroBuilder &Builder) const override { 6819 DefineStd(Builder, "MIPSEL", Opts); 6820 Builder.defineMacro("_MIPSEL"); 6821 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6822 } 6823 }; 6824 6825 class PNaClTargetInfo : public TargetInfo { 6826 public: 6827 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6828 BigEndian = false; 6829 this->UserLabelPrefix = ""; 6830 this->LongAlign = 32; 6831 this->LongWidth = 32; 6832 this->PointerAlign = 32; 6833 this->PointerWidth = 32; 6834 this->IntMaxType = TargetInfo::SignedLongLong; 6835 this->Int64Type = TargetInfo::SignedLongLong; 6836 this->DoubleAlign = 64; 6837 this->LongDoubleWidth = 64; 6838 this->LongDoubleAlign = 64; 6839 this->SizeType = TargetInfo::UnsignedInt; 6840 this->PtrDiffType = TargetInfo::SignedInt; 6841 this->IntPtrType = TargetInfo::SignedInt; 6842 this->RegParmMax = 0; // Disallow regparm 6843 } 6844 6845 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6846 Builder.defineMacro("__le32__"); 6847 Builder.defineMacro("__pnacl__"); 6848 } 6849 void getTargetDefines(const LangOptions &Opts, 6850 MacroBuilder &Builder) const override { 6851 getArchDefines(Opts, Builder); 6852 } 6853 bool hasFeature(StringRef Feature) const override { 6854 return Feature == "pnacl"; 6855 } 6856 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6857 BuiltinVaListKind getBuiltinVaListKind() const override { 6858 return TargetInfo::PNaClABIBuiltinVaList; 6859 } 6860 ArrayRef<const char *> getGCCRegNames() const override; 6861 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6862 bool validateAsmConstraint(const char *&Name, 6863 TargetInfo::ConstraintInfo &Info) const override { 6864 return false; 6865 } 6866 6867 const char *getClobbers() const override { 6868 return ""; 6869 } 6870 }; 6871 6872 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 6873 return None; 6874 } 6875 6876 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 6877 return None; 6878 } 6879 6880 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 6881 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 6882 public: 6883 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 6884 Mips32ELTargetInfo(Triple) { 6885 } 6886 6887 BuiltinVaListKind getBuiltinVaListKind() const override { 6888 return TargetInfo::PNaClABIBuiltinVaList; 6889 } 6890 }; 6891 6892 class Le64TargetInfo : public TargetInfo { 6893 static const Builtin::Info BuiltinInfo[]; 6894 6895 public: 6896 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6897 BigEndian = false; 6898 NoAsmVariants = true; 6899 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6900 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6901 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6902 } 6903 6904 void getTargetDefines(const LangOptions &Opts, 6905 MacroBuilder &Builder) const override { 6906 DefineStd(Builder, "unix", Opts); 6907 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6908 Builder.defineMacro("__ELF__"); 6909 } 6910 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6911 return llvm::makeArrayRef(BuiltinInfo, 6912 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6913 } 6914 BuiltinVaListKind getBuiltinVaListKind() const override { 6915 return TargetInfo::PNaClABIBuiltinVaList; 6916 } 6917 const char *getClobbers() const override { return ""; } 6918 ArrayRef<const char *> getGCCRegNames() const override { 6919 return None; 6920 } 6921 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6922 return None; 6923 } 6924 bool validateAsmConstraint(const char *&Name, 6925 TargetInfo::ConstraintInfo &Info) const override { 6926 return false; 6927 } 6928 6929 bool hasProtectedVisibility() const override { return false; } 6930 }; 6931 6932 class WebAssemblyTargetInfo : public TargetInfo { 6933 static const Builtin::Info BuiltinInfo[]; 6934 6935 enum SIMDEnum { 6936 NoSIMD, 6937 SIMD128, 6938 } SIMDLevel; 6939 6940 public: 6941 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 6942 : TargetInfo(T), SIMDLevel(NoSIMD) { 6943 BigEndian = false; 6944 NoAsmVariants = true; 6945 SuitableAlign = 128; 6946 LargeArrayMinWidth = 128; 6947 LargeArrayAlign = 128; 6948 SimdDefaultAlign = 128; 6949 SigAtomicType = SignedLong; 6950 } 6951 6952 protected: 6953 void getTargetDefines(const LangOptions &Opts, 6954 MacroBuilder &Builder) const override { 6955 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 6956 if (SIMDLevel >= SIMD128) 6957 Builder.defineMacro("__wasm_simd128__"); 6958 } 6959 6960 private: 6961 bool 6962 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6963 StringRef CPU, 6964 const std::vector<std::string> &FeaturesVec) const override { 6965 if (CPU == "bleeding-edge") 6966 Features["simd128"] = true; 6967 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6968 } 6969 bool hasFeature(StringRef Feature) const final { 6970 return llvm::StringSwitch<bool>(Feature) 6971 .Case("simd128", SIMDLevel >= SIMD128) 6972 .Default(false); 6973 } 6974 bool handleTargetFeatures(std::vector<std::string> &Features, 6975 DiagnosticsEngine &Diags) final { 6976 for (const auto &Feature : Features) { 6977 if (Feature == "+simd128") { 6978 SIMDLevel = std::max(SIMDLevel, SIMD128); 6979 continue; 6980 } 6981 if (Feature == "-simd128") { 6982 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 6983 continue; 6984 } 6985 6986 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 6987 << "-target-feature"; 6988 return false; 6989 } 6990 return true; 6991 } 6992 bool setCPU(const std::string &Name) final { 6993 return llvm::StringSwitch<bool>(Name) 6994 .Case("mvp", true) 6995 .Case("bleeding-edge", true) 6996 .Case("generic", true) 6997 .Default(false); 6998 } 6999 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7000 return llvm::makeArrayRef(BuiltinInfo, 7001 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7002 } 7003 BuiltinVaListKind getBuiltinVaListKind() const final { 7004 // TODO: Implement va_list properly. 7005 return VoidPtrBuiltinVaList; 7006 } 7007 ArrayRef<const char *> getGCCRegNames() const final { 7008 return None; 7009 } 7010 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7011 return None; 7012 } 7013 bool 7014 validateAsmConstraint(const char *&Name, 7015 TargetInfo::ConstraintInfo &Info) const final { 7016 return false; 7017 } 7018 const char *getClobbers() const final { return ""; } 7019 bool isCLZForZeroUndef() const final { return false; } 7020 bool hasInt128Type() const final { return true; } 7021 IntType getIntTypeByWidth(unsigned BitWidth, 7022 bool IsSigned) const final { 7023 // WebAssembly prefers long long for explicitly 64-bit integers. 7024 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7025 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7026 } 7027 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7028 bool IsSigned) const final { 7029 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7030 return BitWidth == 64 7031 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7032 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7033 } 7034 }; 7035 7036 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7037 #define BUILTIN(ID, TYPE, ATTRS) \ 7038 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7039 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7040 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7041 #include "clang/Basic/BuiltinsWebAssembly.def" 7042 }; 7043 7044 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7045 public: 7046 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7047 : WebAssemblyTargetInfo(T) { 7048 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7049 DataLayoutString = "e-p:32:32-i64:64-n32:64-S128"; 7050 } 7051 7052 protected: 7053 void getTargetDefines(const LangOptions &Opts, 7054 MacroBuilder &Builder) const override { 7055 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7056 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7057 } 7058 }; 7059 7060 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7061 public: 7062 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7063 : WebAssemblyTargetInfo(T) { 7064 LongAlign = LongWidth = 64; 7065 PointerAlign = PointerWidth = 64; 7066 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7067 DataLayoutString = "e-p:64:64-i64:64-n32:64-S128"; 7068 } 7069 7070 protected: 7071 void getTargetDefines(const LangOptions &Opts, 7072 MacroBuilder &Builder) const override { 7073 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7074 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7075 } 7076 }; 7077 7078 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7079 #define BUILTIN(ID, TYPE, ATTRS) \ 7080 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7081 #include "clang/Basic/BuiltinsLe64.def" 7082 }; 7083 7084 static const unsigned SPIRAddrSpaceMap[] = { 7085 1, // opencl_global 7086 3, // opencl_local 7087 2, // opencl_constant 7088 4, // opencl_generic 7089 0, // cuda_device 7090 0, // cuda_constant 7091 0 // cuda_shared 7092 }; 7093 class SPIRTargetInfo : public TargetInfo { 7094 public: 7095 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7096 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7097 "SPIR target must use unknown OS"); 7098 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7099 "SPIR target must use unknown environment type"); 7100 BigEndian = false; 7101 TLSSupported = false; 7102 LongWidth = LongAlign = 64; 7103 AddrSpaceMap = &SPIRAddrSpaceMap; 7104 UseAddrSpaceMapMangling = true; 7105 // Define available target features 7106 // These must be defined in sorted order! 7107 NoAsmVariants = true; 7108 } 7109 void getTargetDefines(const LangOptions &Opts, 7110 MacroBuilder &Builder) const override { 7111 DefineStd(Builder, "SPIR", Opts); 7112 } 7113 bool hasFeature(StringRef Feature) const override { 7114 return Feature == "spir"; 7115 } 7116 7117 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7118 const char *getClobbers() const override { return ""; } 7119 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7120 bool validateAsmConstraint(const char *&Name, 7121 TargetInfo::ConstraintInfo &info) const override { 7122 return true; 7123 } 7124 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7125 return None; 7126 } 7127 BuiltinVaListKind getBuiltinVaListKind() const override { 7128 return TargetInfo::VoidPtrBuiltinVaList; 7129 } 7130 7131 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7132 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7133 : CCCR_Warning; 7134 } 7135 7136 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7137 return CC_SpirFunction; 7138 } 7139 }; 7140 7141 class SPIR32TargetInfo : public SPIRTargetInfo { 7142 public: 7143 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7144 PointerWidth = PointerAlign = 32; 7145 SizeType = TargetInfo::UnsignedInt; 7146 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7147 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7148 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7149 } 7150 void getTargetDefines(const LangOptions &Opts, 7151 MacroBuilder &Builder) const override { 7152 DefineStd(Builder, "SPIR32", Opts); 7153 } 7154 }; 7155 7156 class SPIR64TargetInfo : public SPIRTargetInfo { 7157 public: 7158 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7159 PointerWidth = PointerAlign = 64; 7160 SizeType = TargetInfo::UnsignedLong; 7161 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7162 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7163 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7164 } 7165 void getTargetDefines(const LangOptions &Opts, 7166 MacroBuilder &Builder) const override { 7167 DefineStd(Builder, "SPIR64", Opts); 7168 } 7169 }; 7170 7171 class XCoreTargetInfo : public TargetInfo { 7172 static const Builtin::Info BuiltinInfo[]; 7173 public: 7174 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7175 BigEndian = false; 7176 NoAsmVariants = true; 7177 LongLongAlign = 32; 7178 SuitableAlign = 32; 7179 DoubleAlign = LongDoubleAlign = 32; 7180 SizeType = UnsignedInt; 7181 PtrDiffType = SignedInt; 7182 IntPtrType = SignedInt; 7183 WCharType = UnsignedChar; 7184 WIntType = UnsignedInt; 7185 UseZeroLengthBitfieldAlignment = true; 7186 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7187 "-f64:32-a:0:32-n32"; 7188 } 7189 void getTargetDefines(const LangOptions &Opts, 7190 MacroBuilder &Builder) const override { 7191 Builder.defineMacro("__XS1B__"); 7192 } 7193 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7194 return llvm::makeArrayRef(BuiltinInfo, 7195 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7196 } 7197 BuiltinVaListKind getBuiltinVaListKind() const override { 7198 return TargetInfo::VoidPtrBuiltinVaList; 7199 } 7200 const char *getClobbers() const override { 7201 return ""; 7202 } 7203 ArrayRef<const char *> getGCCRegNames() const override { 7204 static const char * const GCCRegNames[] = { 7205 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7206 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7207 }; 7208 return llvm::makeArrayRef(GCCRegNames); 7209 } 7210 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7211 return None; 7212 } 7213 bool validateAsmConstraint(const char *&Name, 7214 TargetInfo::ConstraintInfo &Info) const override { 7215 return false; 7216 } 7217 int getEHDataRegisterNumber(unsigned RegNo) const override { 7218 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7219 return (RegNo < 2)? RegNo : -1; 7220 } 7221 }; 7222 7223 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7224 #define BUILTIN(ID, TYPE, ATTRS) \ 7225 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7226 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7227 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7228 #include "clang/Basic/BuiltinsXCore.def" 7229 }; 7230 7231 // x86_32 Android target 7232 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7233 public: 7234 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7235 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7236 SuitableAlign = 32; 7237 LongDoubleWidth = 64; 7238 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7239 } 7240 }; 7241 7242 // x86_64 Android target 7243 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7244 public: 7245 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7246 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7247 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7248 } 7249 7250 bool useFloat128ManglingForLongDouble() const override { 7251 return true; 7252 } 7253 }; 7254 } // end anonymous namespace 7255 7256 //===----------------------------------------------------------------------===// 7257 // Driver code 7258 //===----------------------------------------------------------------------===// 7259 7260 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7261 llvm::Triple::OSType os = Triple.getOS(); 7262 7263 switch (Triple.getArch()) { 7264 default: 7265 return nullptr; 7266 7267 case llvm::Triple::xcore: 7268 return new XCoreTargetInfo(Triple); 7269 7270 case llvm::Triple::hexagon: 7271 return new HexagonTargetInfo(Triple); 7272 7273 case llvm::Triple::aarch64: 7274 if (Triple.isOSDarwin()) 7275 return new DarwinAArch64TargetInfo(Triple); 7276 7277 switch (os) { 7278 case llvm::Triple::CloudABI: 7279 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple); 7280 case llvm::Triple::FreeBSD: 7281 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7282 case llvm::Triple::Linux: 7283 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7284 case llvm::Triple::NetBSD: 7285 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7286 default: 7287 return new AArch64leTargetInfo(Triple); 7288 } 7289 7290 case llvm::Triple::aarch64_be: 7291 switch (os) { 7292 case llvm::Triple::FreeBSD: 7293 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7294 case llvm::Triple::Linux: 7295 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7296 case llvm::Triple::NetBSD: 7297 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7298 default: 7299 return new AArch64beTargetInfo(Triple); 7300 } 7301 7302 case llvm::Triple::arm: 7303 case llvm::Triple::thumb: 7304 if (Triple.isOSBinFormatMachO()) 7305 return new DarwinARMTargetInfo(Triple); 7306 7307 switch (os) { 7308 case llvm::Triple::Linux: 7309 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7310 case llvm::Triple::FreeBSD: 7311 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7312 case llvm::Triple::NetBSD: 7313 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7314 case llvm::Triple::OpenBSD: 7315 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7316 case llvm::Triple::Bitrig: 7317 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7318 case llvm::Triple::RTEMS: 7319 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7320 case llvm::Triple::NaCl: 7321 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7322 case llvm::Triple::Win32: 7323 switch (Triple.getEnvironment()) { 7324 case llvm::Triple::Cygnus: 7325 return new CygwinARMTargetInfo(Triple); 7326 case llvm::Triple::GNU: 7327 return new MinGWARMTargetInfo(Triple); 7328 case llvm::Triple::Itanium: 7329 return new ItaniumWindowsARMleTargetInfo(Triple); 7330 case llvm::Triple::MSVC: 7331 default: // Assume MSVC for unknown environments 7332 return new MicrosoftARMleTargetInfo(Triple); 7333 } 7334 default: 7335 return new ARMleTargetInfo(Triple); 7336 } 7337 7338 case llvm::Triple::armeb: 7339 case llvm::Triple::thumbeb: 7340 if (Triple.isOSDarwin()) 7341 return new DarwinARMTargetInfo(Triple); 7342 7343 switch (os) { 7344 case llvm::Triple::Linux: 7345 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7346 case llvm::Triple::FreeBSD: 7347 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7348 case llvm::Triple::NetBSD: 7349 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7350 case llvm::Triple::OpenBSD: 7351 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7352 case llvm::Triple::Bitrig: 7353 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7354 case llvm::Triple::RTEMS: 7355 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7356 case llvm::Triple::NaCl: 7357 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7358 default: 7359 return new ARMbeTargetInfo(Triple); 7360 } 7361 7362 case llvm::Triple::bpfeb: 7363 case llvm::Triple::bpfel: 7364 return new BPFTargetInfo(Triple); 7365 7366 case llvm::Triple::msp430: 7367 return new MSP430TargetInfo(Triple); 7368 7369 case llvm::Triple::mips: 7370 switch (os) { 7371 case llvm::Triple::Linux: 7372 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7373 case llvm::Triple::RTEMS: 7374 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7375 case llvm::Triple::FreeBSD: 7376 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7377 case llvm::Triple::NetBSD: 7378 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7379 default: 7380 return new Mips32EBTargetInfo(Triple); 7381 } 7382 7383 case llvm::Triple::mipsel: 7384 switch (os) { 7385 case llvm::Triple::Linux: 7386 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7387 case llvm::Triple::RTEMS: 7388 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7389 case llvm::Triple::FreeBSD: 7390 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7391 case llvm::Triple::NetBSD: 7392 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7393 case llvm::Triple::NaCl: 7394 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7395 default: 7396 return new Mips32ELTargetInfo(Triple); 7397 } 7398 7399 case llvm::Triple::mips64: 7400 switch (os) { 7401 case llvm::Triple::Linux: 7402 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7403 case llvm::Triple::RTEMS: 7404 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7405 case llvm::Triple::FreeBSD: 7406 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7407 case llvm::Triple::NetBSD: 7408 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7409 case llvm::Triple::OpenBSD: 7410 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7411 default: 7412 return new Mips64EBTargetInfo(Triple); 7413 } 7414 7415 case llvm::Triple::mips64el: 7416 switch (os) { 7417 case llvm::Triple::Linux: 7418 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7419 case llvm::Triple::RTEMS: 7420 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7421 case llvm::Triple::FreeBSD: 7422 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7423 case llvm::Triple::NetBSD: 7424 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7425 case llvm::Triple::OpenBSD: 7426 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7427 default: 7428 return new Mips64ELTargetInfo(Triple); 7429 } 7430 7431 case llvm::Triple::le32: 7432 switch (os) { 7433 case llvm::Triple::NaCl: 7434 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7435 default: 7436 return nullptr; 7437 } 7438 7439 case llvm::Triple::le64: 7440 return new Le64TargetInfo(Triple); 7441 7442 case llvm::Triple::ppc: 7443 if (Triple.isOSDarwin()) 7444 return new DarwinPPC32TargetInfo(Triple); 7445 switch (os) { 7446 case llvm::Triple::Linux: 7447 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7448 case llvm::Triple::FreeBSD: 7449 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7450 case llvm::Triple::NetBSD: 7451 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7452 case llvm::Triple::OpenBSD: 7453 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7454 case llvm::Triple::RTEMS: 7455 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7456 default: 7457 return new PPC32TargetInfo(Triple); 7458 } 7459 7460 case llvm::Triple::ppc64: 7461 if (Triple.isOSDarwin()) 7462 return new DarwinPPC64TargetInfo(Triple); 7463 switch (os) { 7464 case llvm::Triple::Linux: 7465 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7466 case llvm::Triple::Lv2: 7467 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7468 case llvm::Triple::FreeBSD: 7469 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7470 case llvm::Triple::NetBSD: 7471 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7472 default: 7473 return new PPC64TargetInfo(Triple); 7474 } 7475 7476 case llvm::Triple::ppc64le: 7477 switch (os) { 7478 case llvm::Triple::Linux: 7479 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7480 case llvm::Triple::NetBSD: 7481 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7482 default: 7483 return new PPC64TargetInfo(Triple); 7484 } 7485 7486 case llvm::Triple::nvptx: 7487 return new NVPTX32TargetInfo(Triple); 7488 case llvm::Triple::nvptx64: 7489 return new NVPTX64TargetInfo(Triple); 7490 7491 case llvm::Triple::amdgcn: 7492 case llvm::Triple::r600: 7493 return new AMDGPUTargetInfo(Triple); 7494 7495 case llvm::Triple::sparc: 7496 switch (os) { 7497 case llvm::Triple::Linux: 7498 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7499 case llvm::Triple::Solaris: 7500 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7501 case llvm::Triple::NetBSD: 7502 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7503 case llvm::Triple::OpenBSD: 7504 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7505 case llvm::Triple::RTEMS: 7506 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7507 default: 7508 return new SparcV8TargetInfo(Triple); 7509 } 7510 7511 // The 'sparcel' architecture copies all the above cases except for Solaris. 7512 case llvm::Triple::sparcel: 7513 switch (os) { 7514 case llvm::Triple::Linux: 7515 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7516 case llvm::Triple::NetBSD: 7517 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7518 case llvm::Triple::OpenBSD: 7519 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7520 case llvm::Triple::RTEMS: 7521 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7522 default: 7523 return new SparcV8elTargetInfo(Triple); 7524 } 7525 7526 case llvm::Triple::sparcv9: 7527 switch (os) { 7528 case llvm::Triple::Linux: 7529 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7530 case llvm::Triple::Solaris: 7531 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7532 case llvm::Triple::NetBSD: 7533 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7534 case llvm::Triple::OpenBSD: 7535 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7536 case llvm::Triple::FreeBSD: 7537 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7538 default: 7539 return new SparcV9TargetInfo(Triple); 7540 } 7541 7542 case llvm::Triple::systemz: 7543 switch (os) { 7544 case llvm::Triple::Linux: 7545 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7546 default: 7547 return new SystemZTargetInfo(Triple); 7548 } 7549 7550 case llvm::Triple::tce: 7551 return new TCETargetInfo(Triple); 7552 7553 case llvm::Triple::x86: 7554 if (Triple.isOSDarwin()) 7555 return new DarwinI386TargetInfo(Triple); 7556 7557 switch (os) { 7558 case llvm::Triple::CloudABI: 7559 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7560 case llvm::Triple::Linux: { 7561 switch (Triple.getEnvironment()) { 7562 default: 7563 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7564 case llvm::Triple::Android: 7565 return new AndroidX86_32TargetInfo(Triple); 7566 } 7567 } 7568 case llvm::Triple::DragonFly: 7569 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7570 case llvm::Triple::NetBSD: 7571 return new NetBSDI386TargetInfo(Triple); 7572 case llvm::Triple::OpenBSD: 7573 return new OpenBSDI386TargetInfo(Triple); 7574 case llvm::Triple::Bitrig: 7575 return new BitrigI386TargetInfo(Triple); 7576 case llvm::Triple::FreeBSD: 7577 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7578 case llvm::Triple::KFreeBSD: 7579 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7580 case llvm::Triple::Minix: 7581 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7582 case llvm::Triple::Solaris: 7583 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7584 case llvm::Triple::Win32: { 7585 switch (Triple.getEnvironment()) { 7586 case llvm::Triple::Cygnus: 7587 return new CygwinX86_32TargetInfo(Triple); 7588 case llvm::Triple::GNU: 7589 return new MinGWX86_32TargetInfo(Triple); 7590 case llvm::Triple::Itanium: 7591 case llvm::Triple::MSVC: 7592 default: // Assume MSVC for unknown environments 7593 return new MicrosoftX86_32TargetInfo(Triple); 7594 } 7595 } 7596 case llvm::Triple::Haiku: 7597 return new HaikuX86_32TargetInfo(Triple); 7598 case llvm::Triple::RTEMS: 7599 return new RTEMSX86_32TargetInfo(Triple); 7600 case llvm::Triple::NaCl: 7601 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7602 default: 7603 return new X86_32TargetInfo(Triple); 7604 } 7605 7606 case llvm::Triple::x86_64: 7607 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7608 return new DarwinX86_64TargetInfo(Triple); 7609 7610 switch (os) { 7611 case llvm::Triple::CloudABI: 7612 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7613 case llvm::Triple::Linux: { 7614 switch (Triple.getEnvironment()) { 7615 default: 7616 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7617 case llvm::Triple::Android: 7618 return new AndroidX86_64TargetInfo(Triple); 7619 } 7620 } 7621 case llvm::Triple::DragonFly: 7622 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7623 case llvm::Triple::NetBSD: 7624 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7625 case llvm::Triple::OpenBSD: 7626 return new OpenBSDX86_64TargetInfo(Triple); 7627 case llvm::Triple::Bitrig: 7628 return new BitrigX86_64TargetInfo(Triple); 7629 case llvm::Triple::FreeBSD: 7630 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7631 case llvm::Triple::KFreeBSD: 7632 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7633 case llvm::Triple::Solaris: 7634 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7635 case llvm::Triple::Win32: { 7636 switch (Triple.getEnvironment()) { 7637 case llvm::Triple::Cygnus: 7638 return new CygwinX86_64TargetInfo(Triple); 7639 case llvm::Triple::GNU: 7640 return new MinGWX86_64TargetInfo(Triple); 7641 case llvm::Triple::MSVC: 7642 default: // Assume MSVC for unknown environments 7643 return new MicrosoftX86_64TargetInfo(Triple); 7644 } 7645 } 7646 case llvm::Triple::NaCl: 7647 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7648 case llvm::Triple::PS4: 7649 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7650 default: 7651 return new X86_64TargetInfo(Triple); 7652 } 7653 7654 case llvm::Triple::spir: { 7655 if (Triple.getOS() != llvm::Triple::UnknownOS || 7656 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7657 return nullptr; 7658 return new SPIR32TargetInfo(Triple); 7659 } 7660 case llvm::Triple::spir64: { 7661 if (Triple.getOS() != llvm::Triple::UnknownOS || 7662 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7663 return nullptr; 7664 return new SPIR64TargetInfo(Triple); 7665 } 7666 case llvm::Triple::wasm32: 7667 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 7668 return nullptr; 7669 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 7670 case llvm::Triple::wasm64: 7671 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 7672 return nullptr; 7673 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 7674 } 7675 } 7676 7677 /// CreateTargetInfo - Return the target info object for the specified target 7678 /// options. 7679 TargetInfo * 7680 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7681 const std::shared_ptr<TargetOptions> &Opts) { 7682 llvm::Triple Triple(Opts->Triple); 7683 7684 // Construct the target 7685 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7686 if (!Target) { 7687 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7688 return nullptr; 7689 } 7690 Target->TargetOpts = Opts; 7691 7692 // Set the target CPU if specified. 7693 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7694 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7695 return nullptr; 7696 } 7697 7698 // Set the target ABI if specified. 7699 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7700 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7701 return nullptr; 7702 } 7703 7704 // Set the fp math unit. 7705 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7706 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7707 return nullptr; 7708 } 7709 7710 // Compute the default target features, we need the target to handle this 7711 // because features may have dependencies on one another. 7712 llvm::StringMap<bool> Features; 7713 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 7714 Opts->FeaturesAsWritten)) 7715 return nullptr; 7716 7717 // Add the features to the compile options. 7718 Opts->Features.clear(); 7719 for (const auto &F : Features) 7720 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 7721 7722 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7723 return nullptr; 7724 7725 return Target.release(); 7726 } 7727