1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 //===----------------------------------------------------------------------===// 69 // Defines specific to certain operating systems. 70 //===----------------------------------------------------------------------===// 71 72 namespace { 73 template<typename TgtInfo> 74 class OSTargetInfo : public TgtInfo { 75 protected: 76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 77 MacroBuilder &Builder) const=0; 78 public: 79 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 80 : TgtInfo(Triple, Opts) {} 81 void getTargetDefines(const LangOptions &Opts, 82 MacroBuilder &Builder) const override { 83 TgtInfo::getTargetDefines(Opts, Builder); 84 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 85 } 86 87 }; 88 89 // CloudABI Target 90 template <typename Target> 91 class CloudABITargetInfo : public OSTargetInfo<Target> { 92 protected: 93 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 94 MacroBuilder &Builder) const override { 95 Builder.defineMacro("__CloudABI__"); 96 Builder.defineMacro("__ELF__"); 97 98 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 99 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 100 Builder.defineMacro("__STDC_UTF_16__"); 101 Builder.defineMacro("__STDC_UTF_32__"); 102 } 103 104 public: 105 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 106 : OSTargetInfo<Target>(Triple, Opts) {} 107 }; 108 109 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 110 const llvm::Triple &Triple, 111 StringRef &PlatformName, 112 VersionTuple &PlatformMinVersion) { 113 Builder.defineMacro("__APPLE_CC__", "6000"); 114 Builder.defineMacro("__APPLE__"); 115 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 116 // AddressSanitizer doesn't play well with source fortification, which is on 117 // by default on Darwin. 118 if (Opts.Sanitize.has(SanitizerKind::Address)) 119 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 120 121 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 122 if (!Opts.ObjC1) { 123 // __weak is always defined, for use in blocks and with objc pointers. 124 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 125 Builder.defineMacro("__strong", ""); 126 Builder.defineMacro("__unsafe_unretained", ""); 127 } 128 129 if (Opts.Static) 130 Builder.defineMacro("__STATIC__"); 131 else 132 Builder.defineMacro("__DYNAMIC__"); 133 134 if (Opts.POSIXThreads) 135 Builder.defineMacro("_REENTRANT"); 136 137 // Get the platform type and version number from the triple. 138 unsigned Maj, Min, Rev; 139 if (Triple.isMacOSX()) { 140 Triple.getMacOSXVersion(Maj, Min, Rev); 141 PlatformName = "macosx"; 142 } else { 143 Triple.getOSVersion(Maj, Min, Rev); 144 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 145 } 146 147 // If -target arch-pc-win32-macho option specified, we're 148 // generating code for Win32 ABI. No need to emit 149 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 150 if (PlatformName == "win32") { 151 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 152 return; 153 } 154 155 // Set the appropriate OS version define. 156 if (Triple.isiOS()) { 157 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 158 char Str[6]; 159 Str[0] = '0' + Maj; 160 Str[1] = '0' + (Min / 10); 161 Str[2] = '0' + (Min % 10); 162 Str[3] = '0' + (Rev / 10); 163 Str[4] = '0' + (Rev % 10); 164 Str[5] = '\0'; 165 if (Triple.isTvOS()) 166 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 167 else 168 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 169 Str); 170 171 } else if (Triple.isWatchOS()) { 172 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 173 char Str[6]; 174 Str[0] = '0' + Maj; 175 Str[1] = '0' + (Min / 10); 176 Str[2] = '0' + (Min % 10); 177 Str[3] = '0' + (Rev / 10); 178 Str[4] = '0' + (Rev % 10); 179 Str[5] = '\0'; 180 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 181 } else if (Triple.isMacOSX()) { 182 // Note that the Driver allows versions which aren't representable in the 183 // define (because we only get a single digit for the minor and micro 184 // revision numbers). So, we limit them to the maximum representable 185 // version. 186 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 187 char Str[7]; 188 if (Maj < 10 || (Maj == 10 && Min < 10)) { 189 Str[0] = '0' + (Maj / 10); 190 Str[1] = '0' + (Maj % 10); 191 Str[2] = '0' + std::min(Min, 9U); 192 Str[3] = '0' + std::min(Rev, 9U); 193 Str[4] = '\0'; 194 } else { 195 // Handle versions > 10.9. 196 Str[0] = '0' + (Maj / 10); 197 Str[1] = '0' + (Maj % 10); 198 Str[2] = '0' + (Min / 10); 199 Str[3] = '0' + (Min % 10); 200 Str[4] = '0' + (Rev / 10); 201 Str[5] = '0' + (Rev % 10); 202 Str[6] = '\0'; 203 } 204 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 205 } 206 207 // Tell users about the kernel if there is one. 208 if (Triple.isOSDarwin()) 209 Builder.defineMacro("__MACH__"); 210 211 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 212 } 213 214 template<typename Target> 215 class DarwinTargetInfo : public OSTargetInfo<Target> { 216 protected: 217 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 218 MacroBuilder &Builder) const override { 219 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 220 this->PlatformMinVersion); 221 } 222 223 public: 224 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 225 : OSTargetInfo<Target>(Triple, Opts) { 226 // By default, no TLS, and we whitelist permitted architecture/OS 227 // combinations. 228 this->TLSSupported = false; 229 230 if (Triple.isMacOSX()) 231 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 232 else if (Triple.isiOS()) { 233 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 234 if (Triple.getArch() == llvm::Triple::x86_64 || 235 Triple.getArch() == llvm::Triple::aarch64) 236 this->TLSSupported = !Triple.isOSVersionLT(8); 237 else if (Triple.getArch() == llvm::Triple::x86 || 238 Triple.getArch() == llvm::Triple::arm || 239 Triple.getArch() == llvm::Triple::thumb) 240 this->TLSSupported = !Triple.isOSVersionLT(9); 241 } else if (Triple.isWatchOS()) 242 this->TLSSupported = !Triple.isOSVersionLT(2); 243 244 this->MCountName = "\01mcount"; 245 } 246 247 std::string isValidSectionSpecifier(StringRef SR) const override { 248 // Let MCSectionMachO validate this. 249 StringRef Segment, Section; 250 unsigned TAA, StubSize; 251 bool HasTAA; 252 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 253 TAA, HasTAA, StubSize); 254 } 255 256 const char *getStaticInitSectionSpecifier() const override { 257 // FIXME: We should return 0 when building kexts. 258 return "__TEXT,__StaticInit,regular,pure_instructions"; 259 } 260 261 /// Darwin does not support protected visibility. Darwin's "default" 262 /// is very similar to ELF's "protected"; Darwin requires a "weak" 263 /// attribute on declarations that can be dynamically replaced. 264 bool hasProtectedVisibility() const override { 265 return false; 266 } 267 268 unsigned getExnObjectAlignment() const override { 269 // The alignment of an exception object is 8-bytes for darwin since 270 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 271 // and therefore doesn't guarantee 16-byte alignment. 272 return 64; 273 } 274 }; 275 276 277 // DragonFlyBSD Target 278 template<typename Target> 279 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 280 protected: 281 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 282 MacroBuilder &Builder) const override { 283 // DragonFly defines; list based off of gcc output 284 Builder.defineMacro("__DragonFly__"); 285 Builder.defineMacro("__DragonFly_cc_version", "100001"); 286 Builder.defineMacro("__ELF__"); 287 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 288 Builder.defineMacro("__tune_i386__"); 289 DefineStd(Builder, "unix", Opts); 290 } 291 public: 292 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 293 : OSTargetInfo<Target>(Triple, Opts) { 294 switch (Triple.getArch()) { 295 default: 296 case llvm::Triple::x86: 297 case llvm::Triple::x86_64: 298 this->MCountName = ".mcount"; 299 break; 300 } 301 } 302 }; 303 304 // FreeBSD Target 305 template<typename Target> 306 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 307 protected: 308 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 309 MacroBuilder &Builder) const override { 310 // FreeBSD defines; list based off of gcc output 311 312 unsigned Release = Triple.getOSMajorVersion(); 313 if (Release == 0U) 314 Release = 8; 315 316 Builder.defineMacro("__FreeBSD__", Twine(Release)); 317 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 318 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 319 DefineStd(Builder, "unix", Opts); 320 Builder.defineMacro("__ELF__"); 321 322 // On FreeBSD, wchar_t contains the number of the code point as 323 // used by the character set of the locale. These character sets are 324 // not necessarily a superset of ASCII. 325 // 326 // FIXME: This is wrong; the macro refers to the numerical values 327 // of wchar_t *literals*, which are not locale-dependent. However, 328 // FreeBSD systems apparently depend on us getting this wrong, and 329 // setting this to 1 is conforming even if all the basic source 330 // character literals have the same encoding as char and wchar_t. 331 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 332 } 333 public: 334 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 335 : OSTargetInfo<Target>(Triple, Opts) { 336 switch (Triple.getArch()) { 337 default: 338 case llvm::Triple::x86: 339 case llvm::Triple::x86_64: 340 this->MCountName = ".mcount"; 341 break; 342 case llvm::Triple::mips: 343 case llvm::Triple::mipsel: 344 case llvm::Triple::ppc: 345 case llvm::Triple::ppc64: 346 case llvm::Triple::ppc64le: 347 this->MCountName = "_mcount"; 348 break; 349 case llvm::Triple::arm: 350 this->MCountName = "__mcount"; 351 break; 352 } 353 } 354 }; 355 356 // GNU/kFreeBSD Target 357 template<typename Target> 358 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 359 protected: 360 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 361 MacroBuilder &Builder) const override { 362 // GNU/kFreeBSD defines; list based off of gcc output 363 364 DefineStd(Builder, "unix", Opts); 365 Builder.defineMacro("__FreeBSD_kernel__"); 366 Builder.defineMacro("__GLIBC__"); 367 Builder.defineMacro("__ELF__"); 368 if (Opts.POSIXThreads) 369 Builder.defineMacro("_REENTRANT"); 370 if (Opts.CPlusPlus) 371 Builder.defineMacro("_GNU_SOURCE"); 372 } 373 public: 374 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 375 : OSTargetInfo<Target>(Triple, Opts) {} 376 }; 377 378 // Minix Target 379 template<typename Target> 380 class MinixTargetInfo : public OSTargetInfo<Target> { 381 protected: 382 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 383 MacroBuilder &Builder) const override { 384 // Minix defines 385 386 Builder.defineMacro("__minix", "3"); 387 Builder.defineMacro("_EM_WSIZE", "4"); 388 Builder.defineMacro("_EM_PSIZE", "4"); 389 Builder.defineMacro("_EM_SSIZE", "2"); 390 Builder.defineMacro("_EM_LSIZE", "4"); 391 Builder.defineMacro("_EM_FSIZE", "4"); 392 Builder.defineMacro("_EM_DSIZE", "8"); 393 Builder.defineMacro("__ELF__"); 394 DefineStd(Builder, "unix", Opts); 395 } 396 public: 397 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 398 : OSTargetInfo<Target>(Triple, Opts) {} 399 }; 400 401 // Linux target 402 template<typename Target> 403 class LinuxTargetInfo : public OSTargetInfo<Target> { 404 protected: 405 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 406 MacroBuilder &Builder) const override { 407 // Linux defines; list based off of gcc output 408 DefineStd(Builder, "unix", Opts); 409 DefineStd(Builder, "linux", Opts); 410 Builder.defineMacro("__gnu_linux__"); 411 Builder.defineMacro("__ELF__"); 412 if (Triple.isAndroid()) { 413 Builder.defineMacro("__ANDROID__", "1"); 414 unsigned Maj, Min, Rev; 415 Triple.getEnvironmentVersion(Maj, Min, Rev); 416 this->PlatformName = "android"; 417 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 418 } 419 if (Opts.POSIXThreads) 420 Builder.defineMacro("_REENTRANT"); 421 if (Opts.CPlusPlus) 422 Builder.defineMacro("_GNU_SOURCE"); 423 } 424 public: 425 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 426 : OSTargetInfo<Target>(Triple, Opts) { 427 this->WIntType = TargetInfo::UnsignedInt; 428 429 switch (Triple.getArch()) { 430 default: 431 break; 432 case llvm::Triple::ppc: 433 case llvm::Triple::ppc64: 434 case llvm::Triple::ppc64le: 435 this->MCountName = "_mcount"; 436 break; 437 } 438 } 439 440 const char *getStaticInitSectionSpecifier() const override { 441 return ".text.startup"; 442 } 443 }; 444 445 // NetBSD Target 446 template<typename Target> 447 class NetBSDTargetInfo : public OSTargetInfo<Target> { 448 protected: 449 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 450 MacroBuilder &Builder) const override { 451 // NetBSD defines; list based off of gcc output 452 Builder.defineMacro("__NetBSD__"); 453 Builder.defineMacro("__unix__"); 454 Builder.defineMacro("__ELF__"); 455 if (Opts.POSIXThreads) 456 Builder.defineMacro("_POSIX_THREADS"); 457 458 switch (Triple.getArch()) { 459 default: 460 break; 461 case llvm::Triple::arm: 462 case llvm::Triple::armeb: 463 case llvm::Triple::thumb: 464 case llvm::Triple::thumbeb: 465 Builder.defineMacro("__ARM_DWARF_EH__"); 466 break; 467 } 468 } 469 public: 470 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 471 : OSTargetInfo<Target>(Triple, Opts) { 472 this->MCountName = "_mcount"; 473 } 474 }; 475 476 // OpenBSD Target 477 template<typename Target> 478 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 479 protected: 480 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 481 MacroBuilder &Builder) const override { 482 // OpenBSD defines; list based off of gcc output 483 484 Builder.defineMacro("__OpenBSD__"); 485 DefineStd(Builder, "unix", Opts); 486 Builder.defineMacro("__ELF__"); 487 if (Opts.POSIXThreads) 488 Builder.defineMacro("_REENTRANT"); 489 } 490 public: 491 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 492 : OSTargetInfo<Target>(Triple, Opts) { 493 this->TLSSupported = false; 494 495 switch (Triple.getArch()) { 496 default: 497 case llvm::Triple::x86: 498 case llvm::Triple::x86_64: 499 case llvm::Triple::arm: 500 case llvm::Triple::sparc: 501 this->MCountName = "__mcount"; 502 break; 503 case llvm::Triple::mips64: 504 case llvm::Triple::mips64el: 505 case llvm::Triple::ppc: 506 case llvm::Triple::sparcv9: 507 this->MCountName = "_mcount"; 508 break; 509 } 510 } 511 }; 512 513 // Bitrig Target 514 template<typename Target> 515 class BitrigTargetInfo : public OSTargetInfo<Target> { 516 protected: 517 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 518 MacroBuilder &Builder) const override { 519 // Bitrig defines; list based off of gcc output 520 521 Builder.defineMacro("__Bitrig__"); 522 DefineStd(Builder, "unix", Opts); 523 Builder.defineMacro("__ELF__"); 524 if (Opts.POSIXThreads) 525 Builder.defineMacro("_REENTRANT"); 526 527 switch (Triple.getArch()) { 528 default: 529 break; 530 case llvm::Triple::arm: 531 case llvm::Triple::armeb: 532 case llvm::Triple::thumb: 533 case llvm::Triple::thumbeb: 534 Builder.defineMacro("__ARM_DWARF_EH__"); 535 break; 536 } 537 } 538 public: 539 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 540 : OSTargetInfo<Target>(Triple, Opts) { 541 this->MCountName = "__mcount"; 542 } 543 }; 544 545 // PSP Target 546 template<typename Target> 547 class PSPTargetInfo : public OSTargetInfo<Target> { 548 protected: 549 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 550 MacroBuilder &Builder) const override { 551 // PSP defines; list based on the output of the pspdev gcc toolchain. 552 Builder.defineMacro("PSP"); 553 Builder.defineMacro("_PSP"); 554 Builder.defineMacro("__psp__"); 555 Builder.defineMacro("__ELF__"); 556 } 557 public: 558 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 559 }; 560 561 // PS3 PPU Target 562 template<typename Target> 563 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 564 protected: 565 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 566 MacroBuilder &Builder) const override { 567 // PS3 PPU defines. 568 Builder.defineMacro("__PPC__"); 569 Builder.defineMacro("__PPU__"); 570 Builder.defineMacro("__CELLOS_LV2__"); 571 Builder.defineMacro("__ELF__"); 572 Builder.defineMacro("__LP32__"); 573 Builder.defineMacro("_ARCH_PPC64"); 574 Builder.defineMacro("__powerpc64__"); 575 } 576 public: 577 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 578 : OSTargetInfo<Target>(Triple, Opts) { 579 this->LongWidth = this->LongAlign = 32; 580 this->PointerWidth = this->PointerAlign = 32; 581 this->IntMaxType = TargetInfo::SignedLongLong; 582 this->Int64Type = TargetInfo::SignedLongLong; 583 this->SizeType = TargetInfo::UnsignedInt; 584 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 585 } 586 }; 587 588 template <typename Target> 589 class PS4OSTargetInfo : public OSTargetInfo<Target> { 590 protected: 591 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 592 MacroBuilder &Builder) const override { 593 Builder.defineMacro("__FreeBSD__", "9"); 594 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 595 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 596 DefineStd(Builder, "unix", Opts); 597 Builder.defineMacro("__ELF__"); 598 Builder.defineMacro("__PS4__"); 599 } 600 public: 601 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 602 : OSTargetInfo<Target>(Triple, Opts) { 603 this->WCharType = this->UnsignedShort; 604 605 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 606 this->MaxTLSAlign = 256; 607 608 // On PS4, do not honor explicit bit field alignment, 609 // as in "__attribute__((aligned(2))) int b : 1;". 610 this->UseExplicitBitFieldAlignment = false; 611 612 switch (Triple.getArch()) { 613 default: 614 case llvm::Triple::x86_64: 615 this->MCountName = ".mcount"; 616 break; 617 } 618 } 619 }; 620 621 // Solaris target 622 template<typename Target> 623 class SolarisTargetInfo : public OSTargetInfo<Target> { 624 protected: 625 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 626 MacroBuilder &Builder) const override { 627 DefineStd(Builder, "sun", Opts); 628 DefineStd(Builder, "unix", Opts); 629 Builder.defineMacro("__ELF__"); 630 Builder.defineMacro("__svr4__"); 631 Builder.defineMacro("__SVR4"); 632 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 633 // newer, but to 500 for everything else. feature_test.h has a check to 634 // ensure that you are not using C99 with an old version of X/Open or C89 635 // with a new version. 636 if (Opts.C99) 637 Builder.defineMacro("_XOPEN_SOURCE", "600"); 638 else 639 Builder.defineMacro("_XOPEN_SOURCE", "500"); 640 if (Opts.CPlusPlus) 641 Builder.defineMacro("__C99FEATURES__"); 642 Builder.defineMacro("_LARGEFILE_SOURCE"); 643 Builder.defineMacro("_LARGEFILE64_SOURCE"); 644 Builder.defineMacro("__EXTENSIONS__"); 645 Builder.defineMacro("_REENTRANT"); 646 } 647 public: 648 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 649 : OSTargetInfo<Target>(Triple, Opts) { 650 this->WCharType = this->SignedInt; 651 // FIXME: WIntType should be SignedLong 652 } 653 }; 654 655 // Windows target 656 template<typename Target> 657 class WindowsTargetInfo : public OSTargetInfo<Target> { 658 protected: 659 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 660 MacroBuilder &Builder) const override { 661 Builder.defineMacro("_WIN32"); 662 } 663 void getVisualStudioDefines(const LangOptions &Opts, 664 MacroBuilder &Builder) const { 665 if (Opts.CPlusPlus) { 666 if (Opts.RTTIData) 667 Builder.defineMacro("_CPPRTTI"); 668 669 if (Opts.CXXExceptions) 670 Builder.defineMacro("_CPPUNWIND"); 671 } 672 673 if (Opts.Bool) 674 Builder.defineMacro("__BOOL_DEFINED"); 675 676 if (!Opts.CharIsSigned) 677 Builder.defineMacro("_CHAR_UNSIGNED"); 678 679 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 680 // but it works for now. 681 if (Opts.POSIXThreads) 682 Builder.defineMacro("_MT"); 683 684 if (Opts.MSCompatibilityVersion) { 685 Builder.defineMacro("_MSC_VER", 686 Twine(Opts.MSCompatibilityVersion / 100000)); 687 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 688 // FIXME We cannot encode the revision information into 32-bits 689 Builder.defineMacro("_MSC_BUILD", Twine(1)); 690 691 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 692 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 693 } 694 695 if (Opts.MicrosoftExt) { 696 Builder.defineMacro("_MSC_EXTENSIONS"); 697 698 if (Opts.CPlusPlus11) { 699 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 700 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 701 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 702 } 703 } 704 705 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 706 } 707 708 public: 709 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 710 : OSTargetInfo<Target>(Triple, Opts) {} 711 }; 712 713 template <typename Target> 714 class NaClTargetInfo : public OSTargetInfo<Target> { 715 protected: 716 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 717 MacroBuilder &Builder) const override { 718 if (Opts.POSIXThreads) 719 Builder.defineMacro("_REENTRANT"); 720 if (Opts.CPlusPlus) 721 Builder.defineMacro("_GNU_SOURCE"); 722 723 DefineStd(Builder, "unix", Opts); 724 Builder.defineMacro("__ELF__"); 725 Builder.defineMacro("__native_client__"); 726 } 727 728 public: 729 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 730 : OSTargetInfo<Target>(Triple, Opts) { 731 this->LongAlign = 32; 732 this->LongWidth = 32; 733 this->PointerAlign = 32; 734 this->PointerWidth = 32; 735 this->IntMaxType = TargetInfo::SignedLongLong; 736 this->Int64Type = TargetInfo::SignedLongLong; 737 this->DoubleAlign = 64; 738 this->LongDoubleWidth = 64; 739 this->LongDoubleAlign = 64; 740 this->LongLongWidth = 64; 741 this->LongLongAlign = 64; 742 this->SizeType = TargetInfo::UnsignedInt; 743 this->PtrDiffType = TargetInfo::SignedInt; 744 this->IntPtrType = TargetInfo::SignedInt; 745 // RegParmMax is inherited from the underlying architecture 746 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 747 if (Triple.getArch() == llvm::Triple::arm) { 748 // Handled in ARM's setABI(). 749 } else if (Triple.getArch() == llvm::Triple::x86) { 750 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 751 } else if (Triple.getArch() == llvm::Triple::x86_64) { 752 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 753 } else if (Triple.getArch() == llvm::Triple::mipsel) { 754 // Handled on mips' setDataLayout. 755 } else { 756 assert(Triple.getArch() == llvm::Triple::le32); 757 this->resetDataLayout("e-p:32:32-i64:64"); 758 } 759 } 760 }; 761 762 // WebAssembly target 763 template <typename Target> 764 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 765 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 766 MacroBuilder &Builder) const final { 767 // A common platform macro. 768 if (Opts.POSIXThreads) 769 Builder.defineMacro("_REENTRANT"); 770 // Follow g++ convention and predefine _GNU_SOURCE for C++. 771 if (Opts.CPlusPlus) 772 Builder.defineMacro("_GNU_SOURCE"); 773 } 774 775 // As an optimization, group static init code together in a section. 776 const char *getStaticInitSectionSpecifier() const final { 777 return ".text.__startup"; 778 } 779 780 public: 781 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 782 const TargetOptions &Opts) 783 : OSTargetInfo<Target>(Triple, Opts) { 784 this->MCountName = "__mcount"; 785 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 786 } 787 }; 788 789 //===----------------------------------------------------------------------===// 790 // Specific target implementations. 791 //===----------------------------------------------------------------------===// 792 793 // PPC abstract base class 794 class PPCTargetInfo : public TargetInfo { 795 static const Builtin::Info BuiltinInfo[]; 796 static const char * const GCCRegNames[]; 797 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 798 std::string CPU; 799 800 // Target cpu features. 801 bool HasVSX; 802 bool HasP8Vector; 803 bool HasP8Crypto; 804 bool HasDirectMove; 805 bool HasQPX; 806 bool HasHTM; 807 bool HasBPERMD; 808 bool HasExtDiv; 809 810 protected: 811 std::string ABI; 812 813 public: 814 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 815 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 816 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 817 HasBPERMD(false), HasExtDiv(false) { 818 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 819 SimdDefaultAlign = 128; 820 LongDoubleWidth = LongDoubleAlign = 128; 821 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 822 } 823 824 /// \brief Flags for architecture specific defines. 825 typedef enum { 826 ArchDefineNone = 0, 827 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 828 ArchDefinePpcgr = 1 << 1, 829 ArchDefinePpcsq = 1 << 2, 830 ArchDefine440 = 1 << 3, 831 ArchDefine603 = 1 << 4, 832 ArchDefine604 = 1 << 5, 833 ArchDefinePwr4 = 1 << 6, 834 ArchDefinePwr5 = 1 << 7, 835 ArchDefinePwr5x = 1 << 8, 836 ArchDefinePwr6 = 1 << 9, 837 ArchDefinePwr6x = 1 << 10, 838 ArchDefinePwr7 = 1 << 11, 839 ArchDefinePwr8 = 1 << 12, 840 ArchDefineA2 = 1 << 13, 841 ArchDefineA2q = 1 << 14 842 } ArchDefineTypes; 843 844 // Note: GCC recognizes the following additional cpus: 845 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 846 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 847 // titan, rs64. 848 bool setCPU(const std::string &Name) override { 849 bool CPUKnown = llvm::StringSwitch<bool>(Name) 850 .Case("generic", true) 851 .Case("440", true) 852 .Case("450", true) 853 .Case("601", true) 854 .Case("602", true) 855 .Case("603", true) 856 .Case("603e", true) 857 .Case("603ev", true) 858 .Case("604", true) 859 .Case("604e", true) 860 .Case("620", true) 861 .Case("630", true) 862 .Case("g3", true) 863 .Case("7400", true) 864 .Case("g4", true) 865 .Case("7450", true) 866 .Case("g4+", true) 867 .Case("750", true) 868 .Case("970", true) 869 .Case("g5", true) 870 .Case("a2", true) 871 .Case("a2q", true) 872 .Case("e500mc", true) 873 .Case("e5500", true) 874 .Case("power3", true) 875 .Case("pwr3", true) 876 .Case("power4", true) 877 .Case("pwr4", true) 878 .Case("power5", true) 879 .Case("pwr5", true) 880 .Case("power5x", true) 881 .Case("pwr5x", true) 882 .Case("power6", true) 883 .Case("pwr6", true) 884 .Case("power6x", true) 885 .Case("pwr6x", true) 886 .Case("power7", true) 887 .Case("pwr7", true) 888 .Case("power8", true) 889 .Case("pwr8", true) 890 .Case("powerpc", true) 891 .Case("ppc", true) 892 .Case("powerpc64", true) 893 .Case("ppc64", true) 894 .Case("powerpc64le", true) 895 .Case("ppc64le", true) 896 .Default(false); 897 898 if (CPUKnown) 899 CPU = Name; 900 901 return CPUKnown; 902 } 903 904 905 StringRef getABI() const override { return ABI; } 906 907 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 908 return llvm::makeArrayRef(BuiltinInfo, 909 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 910 } 911 912 bool isCLZForZeroUndef() const override { return false; } 913 914 void getTargetDefines(const LangOptions &Opts, 915 MacroBuilder &Builder) const override; 916 917 bool 918 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 919 StringRef CPU, 920 const std::vector<std::string> &FeaturesVec) const override; 921 922 bool handleTargetFeatures(std::vector<std::string> &Features, 923 DiagnosticsEngine &Diags) override; 924 bool hasFeature(StringRef Feature) const override; 925 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 926 bool Enabled) const override; 927 928 ArrayRef<const char *> getGCCRegNames() const override; 929 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 930 bool validateAsmConstraint(const char *&Name, 931 TargetInfo::ConstraintInfo &Info) const override { 932 switch (*Name) { 933 default: return false; 934 case 'O': // Zero 935 break; 936 case 'b': // Base register 937 case 'f': // Floating point register 938 Info.setAllowsRegister(); 939 break; 940 // FIXME: The following are added to allow parsing. 941 // I just took a guess at what the actions should be. 942 // Also, is more specific checking needed? I.e. specific registers? 943 case 'd': // Floating point register (containing 64-bit value) 944 case 'v': // Altivec vector register 945 Info.setAllowsRegister(); 946 break; 947 case 'w': 948 switch (Name[1]) { 949 case 'd':// VSX vector register to hold vector double data 950 case 'f':// VSX vector register to hold vector float data 951 case 's':// VSX vector register to hold scalar float data 952 case 'a':// Any VSX register 953 case 'c':// An individual CR bit 954 break; 955 default: 956 return false; 957 } 958 Info.setAllowsRegister(); 959 Name++; // Skip over 'w'. 960 break; 961 case 'h': // `MQ', `CTR', or `LINK' register 962 case 'q': // `MQ' register 963 case 'c': // `CTR' register 964 case 'l': // `LINK' register 965 case 'x': // `CR' register (condition register) number 0 966 case 'y': // `CR' register (condition register) 967 case 'z': // `XER[CA]' carry bit (part of the XER register) 968 Info.setAllowsRegister(); 969 break; 970 case 'I': // Signed 16-bit constant 971 case 'J': // Unsigned 16-bit constant shifted left 16 bits 972 // (use `L' instead for SImode constants) 973 case 'K': // Unsigned 16-bit constant 974 case 'L': // Signed 16-bit constant shifted left 16 bits 975 case 'M': // Constant larger than 31 976 case 'N': // Exact power of 2 977 case 'P': // Constant whose negation is a signed 16-bit constant 978 case 'G': // Floating point constant that can be loaded into a 979 // register with one instruction per word 980 case 'H': // Integer/Floating point constant that can be loaded 981 // into a register using three instructions 982 break; 983 case 'm': // Memory operand. Note that on PowerPC targets, m can 984 // include addresses that update the base register. It 985 // is therefore only safe to use `m' in an asm statement 986 // if that asm statement accesses the operand exactly once. 987 // The asm statement must also use `%U<opno>' as a 988 // placeholder for the "update" flag in the corresponding 989 // load or store instruction. For example: 990 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 991 // is correct but: 992 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 993 // is not. Use es rather than m if you don't want the base 994 // register to be updated. 995 case 'e': 996 if (Name[1] != 's') 997 return false; 998 // es: A "stable" memory operand; that is, one which does not 999 // include any automodification of the base register. Unlike 1000 // `m', this constraint can be used in asm statements that 1001 // might access the operand several times, or that might not 1002 // access it at all. 1003 Info.setAllowsMemory(); 1004 Name++; // Skip over 'e'. 1005 break; 1006 case 'Q': // Memory operand that is an offset from a register (it is 1007 // usually better to use `m' or `es' in asm statements) 1008 case 'Z': // Memory operand that is an indexed or indirect from a 1009 // register (it is usually better to use `m' or `es' in 1010 // asm statements) 1011 Info.setAllowsMemory(); 1012 Info.setAllowsRegister(); 1013 break; 1014 case 'R': // AIX TOC entry 1015 case 'a': // Address operand that is an indexed or indirect from a 1016 // register (`p' is preferable for asm statements) 1017 case 'S': // Constant suitable as a 64-bit mask operand 1018 case 'T': // Constant suitable as a 32-bit mask operand 1019 case 'U': // System V Release 4 small data area reference 1020 case 't': // AND masks that can be performed by two rldic{l, r} 1021 // instructions 1022 case 'W': // Vector constant that does not require memory 1023 case 'j': // Vector constant that is all zeros. 1024 break; 1025 // End FIXME. 1026 } 1027 return true; 1028 } 1029 std::string convertConstraint(const char *&Constraint) const override { 1030 std::string R; 1031 switch (*Constraint) { 1032 case 'e': 1033 case 'w': 1034 // Two-character constraint; add "^" hint for later parsing. 1035 R = std::string("^") + std::string(Constraint, 2); 1036 Constraint++; 1037 break; 1038 default: 1039 return TargetInfo::convertConstraint(Constraint); 1040 } 1041 return R; 1042 } 1043 const char *getClobbers() const override { 1044 return ""; 1045 } 1046 int getEHDataRegisterNumber(unsigned RegNo) const override { 1047 if (RegNo == 0) return 3; 1048 if (RegNo == 1) return 4; 1049 return -1; 1050 } 1051 1052 bool hasSjLjLowering() const override { 1053 return true; 1054 } 1055 1056 bool useFloat128ManglingForLongDouble() const override { 1057 return LongDoubleWidth == 128 && 1058 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1059 getTriple().isOSBinFormatELF(); 1060 } 1061 }; 1062 1063 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1064 #define BUILTIN(ID, TYPE, ATTRS) \ 1065 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1066 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1067 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1068 #include "clang/Basic/BuiltinsPPC.def" 1069 }; 1070 1071 /// handleTargetFeatures - Perform initialization based on the user 1072 /// configured set of features. 1073 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1074 DiagnosticsEngine &Diags) { 1075 for (const auto &Feature : Features) { 1076 if (Feature == "+vsx") { 1077 HasVSX = true; 1078 } else if (Feature == "+bpermd") { 1079 HasBPERMD = true; 1080 } else if (Feature == "+extdiv") { 1081 HasExtDiv = true; 1082 } else if (Feature == "+power8-vector") { 1083 HasP8Vector = true; 1084 } else if (Feature == "+crypto") { 1085 HasP8Crypto = true; 1086 } else if (Feature == "+direct-move") { 1087 HasDirectMove = true; 1088 } else if (Feature == "+qpx") { 1089 HasQPX = true; 1090 } else if (Feature == "+htm") { 1091 HasHTM = true; 1092 } 1093 // TODO: Finish this list and add an assert that we've handled them 1094 // all. 1095 } 1096 1097 return true; 1098 } 1099 1100 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1101 /// #defines that are not tied to a specific subtarget. 1102 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1103 MacroBuilder &Builder) const { 1104 // Target identification. 1105 Builder.defineMacro("__ppc__"); 1106 Builder.defineMacro("__PPC__"); 1107 Builder.defineMacro("_ARCH_PPC"); 1108 Builder.defineMacro("__powerpc__"); 1109 Builder.defineMacro("__POWERPC__"); 1110 if (PointerWidth == 64) { 1111 Builder.defineMacro("_ARCH_PPC64"); 1112 Builder.defineMacro("__powerpc64__"); 1113 Builder.defineMacro("__ppc64__"); 1114 Builder.defineMacro("__PPC64__"); 1115 } 1116 1117 // Target properties. 1118 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1119 Builder.defineMacro("_LITTLE_ENDIAN"); 1120 } else { 1121 if (getTriple().getOS() != llvm::Triple::NetBSD && 1122 getTriple().getOS() != llvm::Triple::OpenBSD) 1123 Builder.defineMacro("_BIG_ENDIAN"); 1124 } 1125 1126 // ABI options. 1127 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1128 Builder.defineMacro("_CALL_ELF", "1"); 1129 if (ABI == "elfv2") 1130 Builder.defineMacro("_CALL_ELF", "2"); 1131 1132 // Subtarget options. 1133 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1134 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1135 1136 // FIXME: Should be controlled by command line option. 1137 if (LongDoubleWidth == 128) 1138 Builder.defineMacro("__LONG_DOUBLE_128__"); 1139 1140 if (Opts.AltiVec) { 1141 Builder.defineMacro("__VEC__", "10206"); 1142 Builder.defineMacro("__ALTIVEC__"); 1143 } 1144 1145 // CPU identification. 1146 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1147 .Case("440", ArchDefineName) 1148 .Case("450", ArchDefineName | ArchDefine440) 1149 .Case("601", ArchDefineName) 1150 .Case("602", ArchDefineName | ArchDefinePpcgr) 1151 .Case("603", ArchDefineName | ArchDefinePpcgr) 1152 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1153 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1154 .Case("604", ArchDefineName | ArchDefinePpcgr) 1155 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1156 .Case("620", ArchDefineName | ArchDefinePpcgr) 1157 .Case("630", ArchDefineName | ArchDefinePpcgr) 1158 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1159 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1160 .Case("750", ArchDefineName | ArchDefinePpcgr) 1161 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1162 | ArchDefinePpcsq) 1163 .Case("a2", ArchDefineA2) 1164 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1165 .Case("pwr3", ArchDefinePpcgr) 1166 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1167 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1168 | ArchDefinePpcsq) 1169 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1170 | ArchDefinePpcgr | ArchDefinePpcsq) 1171 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1172 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1173 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1174 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1175 | ArchDefinePpcsq) 1176 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1177 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1178 | ArchDefinePpcgr | ArchDefinePpcsq) 1179 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1180 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1181 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1182 .Case("power3", ArchDefinePpcgr) 1183 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1184 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1185 | ArchDefinePpcsq) 1186 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1187 | ArchDefinePpcgr | ArchDefinePpcsq) 1188 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1189 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1190 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1191 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1192 | ArchDefinePpcsq) 1193 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1194 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1195 | ArchDefinePpcgr | ArchDefinePpcsq) 1196 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1197 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1198 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1199 .Default(ArchDefineNone); 1200 1201 if (defs & ArchDefineName) 1202 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1203 if (defs & ArchDefinePpcgr) 1204 Builder.defineMacro("_ARCH_PPCGR"); 1205 if (defs & ArchDefinePpcsq) 1206 Builder.defineMacro("_ARCH_PPCSQ"); 1207 if (defs & ArchDefine440) 1208 Builder.defineMacro("_ARCH_440"); 1209 if (defs & ArchDefine603) 1210 Builder.defineMacro("_ARCH_603"); 1211 if (defs & ArchDefine604) 1212 Builder.defineMacro("_ARCH_604"); 1213 if (defs & ArchDefinePwr4) 1214 Builder.defineMacro("_ARCH_PWR4"); 1215 if (defs & ArchDefinePwr5) 1216 Builder.defineMacro("_ARCH_PWR5"); 1217 if (defs & ArchDefinePwr5x) 1218 Builder.defineMacro("_ARCH_PWR5X"); 1219 if (defs & ArchDefinePwr6) 1220 Builder.defineMacro("_ARCH_PWR6"); 1221 if (defs & ArchDefinePwr6x) 1222 Builder.defineMacro("_ARCH_PWR6X"); 1223 if (defs & ArchDefinePwr7) 1224 Builder.defineMacro("_ARCH_PWR7"); 1225 if (defs & ArchDefinePwr8) 1226 Builder.defineMacro("_ARCH_PWR8"); 1227 if (defs & ArchDefineA2) 1228 Builder.defineMacro("_ARCH_A2"); 1229 if (defs & ArchDefineA2q) { 1230 Builder.defineMacro("_ARCH_A2Q"); 1231 Builder.defineMacro("_ARCH_QP"); 1232 } 1233 1234 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1235 Builder.defineMacro("__bg__"); 1236 Builder.defineMacro("__THW_BLUEGENE__"); 1237 Builder.defineMacro("__bgq__"); 1238 Builder.defineMacro("__TOS_BGQ__"); 1239 } 1240 1241 if (HasVSX) 1242 Builder.defineMacro("__VSX__"); 1243 if (HasP8Vector) 1244 Builder.defineMacro("__POWER8_VECTOR__"); 1245 if (HasP8Crypto) 1246 Builder.defineMacro("__CRYPTO__"); 1247 if (HasHTM) 1248 Builder.defineMacro("__HTM__"); 1249 1250 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1251 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1252 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1253 if (PointerWidth == 64) 1254 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1255 1256 // FIXME: The following are not yet generated here by Clang, but are 1257 // generated by GCC: 1258 // 1259 // _SOFT_FLOAT_ 1260 // __RECIP_PRECISION__ 1261 // __APPLE_ALTIVEC__ 1262 // __RECIP__ 1263 // __RECIPF__ 1264 // __RSQRTE__ 1265 // __RSQRTEF__ 1266 // _SOFT_DOUBLE_ 1267 // __NO_LWSYNC__ 1268 // __HAVE_BSWAP__ 1269 // __LONGDOUBLE128 1270 // __CMODEL_MEDIUM__ 1271 // __CMODEL_LARGE__ 1272 // _CALL_SYSV 1273 // _CALL_DARWIN 1274 // __NO_FPRS__ 1275 } 1276 1277 // Handle explicit options being passed to the compiler here: if we've 1278 // explicitly turned off vsx and turned on power8-vector or direct-move then 1279 // go ahead and error since the customer has expressed a somewhat incompatible 1280 // set of options. 1281 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1282 const std::vector<std::string> &FeaturesVec) { 1283 1284 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1285 FeaturesVec.end()) { 1286 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1287 FeaturesVec.end()) { 1288 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1289 << "-mno-vsx"; 1290 return false; 1291 } 1292 1293 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1294 FeaturesVec.end()) { 1295 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1296 << "-mno-vsx"; 1297 return false; 1298 } 1299 } 1300 1301 return true; 1302 } 1303 1304 bool PPCTargetInfo::initFeatureMap( 1305 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1306 const std::vector<std::string> &FeaturesVec) const { 1307 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1308 .Case("7400", true) 1309 .Case("g4", true) 1310 .Case("7450", true) 1311 .Case("g4+", true) 1312 .Case("970", true) 1313 .Case("g5", true) 1314 .Case("pwr6", true) 1315 .Case("pwr7", true) 1316 .Case("pwr8", true) 1317 .Case("ppc64", true) 1318 .Case("ppc64le", true) 1319 .Default(false); 1320 1321 Features["qpx"] = (CPU == "a2q"); 1322 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1323 .Case("ppc64le", true) 1324 .Case("pwr8", true) 1325 .Default(false); 1326 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1327 .Case("ppc64le", true) 1328 .Case("pwr8", true) 1329 .Default(false); 1330 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1331 .Case("ppc64le", true) 1332 .Case("pwr8", true) 1333 .Case("pwr7", true) 1334 .Default(false); 1335 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1336 .Case("ppc64le", true) 1337 .Case("pwr8", true) 1338 .Case("pwr7", true) 1339 .Default(false); 1340 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1341 .Case("ppc64le", true) 1342 .Case("pwr8", true) 1343 .Default(false); 1344 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1345 .Case("ppc64le", true) 1346 .Case("pwr8", true) 1347 .Case("pwr7", true) 1348 .Default(false); 1349 1350 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1351 return false; 1352 1353 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1354 } 1355 1356 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1357 return llvm::StringSwitch<bool>(Feature) 1358 .Case("powerpc", true) 1359 .Case("vsx", HasVSX) 1360 .Case("power8-vector", HasP8Vector) 1361 .Case("crypto", HasP8Crypto) 1362 .Case("direct-move", HasDirectMove) 1363 .Case("qpx", HasQPX) 1364 .Case("htm", HasHTM) 1365 .Case("bpermd", HasBPERMD) 1366 .Case("extdiv", HasExtDiv) 1367 .Default(false); 1368 } 1369 1370 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1371 StringRef Name, bool Enabled) const { 1372 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1373 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1374 // incompatible options. 1375 if (Enabled) { 1376 if (Name == "vsx") { 1377 Features[Name] = true; 1378 } else if (Name == "direct-move") { 1379 Features[Name] = Features["vsx"] = true; 1380 } else if (Name == "power8-vector") { 1381 Features[Name] = Features["vsx"] = true; 1382 } else { 1383 Features[Name] = true; 1384 } 1385 } else { 1386 if (Name == "vsx") { 1387 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1388 false; 1389 } else { 1390 Features[Name] = false; 1391 } 1392 } 1393 } 1394 1395 const char * const PPCTargetInfo::GCCRegNames[] = { 1396 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1397 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1398 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1399 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1400 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1401 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1402 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1403 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1404 "mq", "lr", "ctr", "ap", 1405 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1406 "xer", 1407 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1408 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1409 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1410 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1411 "vrsave", "vscr", 1412 "spe_acc", "spefscr", 1413 "sfp" 1414 }; 1415 1416 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1417 return llvm::makeArrayRef(GCCRegNames); 1418 } 1419 1420 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1421 // While some of these aliases do map to different registers 1422 // they still share the same register name. 1423 { { "0" }, "r0" }, 1424 { { "1"}, "r1" }, 1425 { { "2" }, "r2" }, 1426 { { "3" }, "r3" }, 1427 { { "4" }, "r4" }, 1428 { { "5" }, "r5" }, 1429 { { "6" }, "r6" }, 1430 { { "7" }, "r7" }, 1431 { { "8" }, "r8" }, 1432 { { "9" }, "r9" }, 1433 { { "10" }, "r10" }, 1434 { { "11" }, "r11" }, 1435 { { "12" }, "r12" }, 1436 { { "13" }, "r13" }, 1437 { { "14" }, "r14" }, 1438 { { "15" }, "r15" }, 1439 { { "16" }, "r16" }, 1440 { { "17" }, "r17" }, 1441 { { "18" }, "r18" }, 1442 { { "19" }, "r19" }, 1443 { { "20" }, "r20" }, 1444 { { "21" }, "r21" }, 1445 { { "22" }, "r22" }, 1446 { { "23" }, "r23" }, 1447 { { "24" }, "r24" }, 1448 { { "25" }, "r25" }, 1449 { { "26" }, "r26" }, 1450 { { "27" }, "r27" }, 1451 { { "28" }, "r28" }, 1452 { { "29" }, "r29" }, 1453 { { "30" }, "r30" }, 1454 { { "31" }, "r31" }, 1455 { { "fr0" }, "f0" }, 1456 { { "fr1" }, "f1" }, 1457 { { "fr2" }, "f2" }, 1458 { { "fr3" }, "f3" }, 1459 { { "fr4" }, "f4" }, 1460 { { "fr5" }, "f5" }, 1461 { { "fr6" }, "f6" }, 1462 { { "fr7" }, "f7" }, 1463 { { "fr8" }, "f8" }, 1464 { { "fr9" }, "f9" }, 1465 { { "fr10" }, "f10" }, 1466 { { "fr11" }, "f11" }, 1467 { { "fr12" }, "f12" }, 1468 { { "fr13" }, "f13" }, 1469 { { "fr14" }, "f14" }, 1470 { { "fr15" }, "f15" }, 1471 { { "fr16" }, "f16" }, 1472 { { "fr17" }, "f17" }, 1473 { { "fr18" }, "f18" }, 1474 { { "fr19" }, "f19" }, 1475 { { "fr20" }, "f20" }, 1476 { { "fr21" }, "f21" }, 1477 { { "fr22" }, "f22" }, 1478 { { "fr23" }, "f23" }, 1479 { { "fr24" }, "f24" }, 1480 { { "fr25" }, "f25" }, 1481 { { "fr26" }, "f26" }, 1482 { { "fr27" }, "f27" }, 1483 { { "fr28" }, "f28" }, 1484 { { "fr29" }, "f29" }, 1485 { { "fr30" }, "f30" }, 1486 { { "fr31" }, "f31" }, 1487 { { "cc" }, "cr0" }, 1488 }; 1489 1490 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1491 return llvm::makeArrayRef(GCCRegAliases); 1492 } 1493 1494 class PPC32TargetInfo : public PPCTargetInfo { 1495 public: 1496 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1497 : PPCTargetInfo(Triple, Opts) { 1498 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1499 1500 switch (getTriple().getOS()) { 1501 case llvm::Triple::Linux: 1502 case llvm::Triple::FreeBSD: 1503 case llvm::Triple::NetBSD: 1504 SizeType = UnsignedInt; 1505 PtrDiffType = SignedInt; 1506 IntPtrType = SignedInt; 1507 break; 1508 default: 1509 break; 1510 } 1511 1512 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1513 LongDoubleWidth = LongDoubleAlign = 64; 1514 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1515 } 1516 1517 // PPC32 supports atomics up to 4 bytes. 1518 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1519 } 1520 1521 BuiltinVaListKind getBuiltinVaListKind() const override { 1522 // This is the ELF definition, and is overridden by the Darwin sub-target 1523 return TargetInfo::PowerABIBuiltinVaList; 1524 } 1525 }; 1526 1527 // Note: ABI differences may eventually require us to have a separate 1528 // TargetInfo for little endian. 1529 class PPC64TargetInfo : public PPCTargetInfo { 1530 public: 1531 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1532 : PPCTargetInfo(Triple, Opts) { 1533 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1534 IntMaxType = SignedLong; 1535 Int64Type = SignedLong; 1536 1537 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1538 resetDataLayout("e-m:e-i64:64-n32:64"); 1539 ABI = "elfv2"; 1540 } else { 1541 resetDataLayout("E-m:e-i64:64-n32:64"); 1542 ABI = "elfv1"; 1543 } 1544 1545 switch (getTriple().getOS()) { 1546 case llvm::Triple::FreeBSD: 1547 LongDoubleWidth = LongDoubleAlign = 64; 1548 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1549 break; 1550 case llvm::Triple::NetBSD: 1551 IntMaxType = SignedLongLong; 1552 Int64Type = SignedLongLong; 1553 break; 1554 default: 1555 break; 1556 } 1557 1558 // PPC64 supports atomics up to 8 bytes. 1559 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1560 } 1561 BuiltinVaListKind getBuiltinVaListKind() const override { 1562 return TargetInfo::CharPtrBuiltinVaList; 1563 } 1564 // PPC64 Linux-specific ABI options. 1565 bool setABI(const std::string &Name) override { 1566 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1567 ABI = Name; 1568 return true; 1569 } 1570 return false; 1571 } 1572 }; 1573 1574 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1575 public: 1576 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1577 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1578 HasAlignMac68kSupport = true; 1579 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1580 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1581 LongLongAlign = 32; 1582 SuitableAlign = 128; 1583 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1584 } 1585 BuiltinVaListKind getBuiltinVaListKind() const override { 1586 return TargetInfo::CharPtrBuiltinVaList; 1587 } 1588 }; 1589 1590 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1591 public: 1592 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1593 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1594 HasAlignMac68kSupport = true; 1595 SuitableAlign = 128; 1596 resetDataLayout("E-m:o-i64:64-n32:64"); 1597 } 1598 }; 1599 1600 static const unsigned NVPTXAddrSpaceMap[] = { 1601 1, // opencl_global 1602 3, // opencl_local 1603 4, // opencl_constant 1604 // FIXME: generic has to be added to the target 1605 0, // opencl_generic 1606 1, // cuda_device 1607 4, // cuda_constant 1608 3, // cuda_shared 1609 }; 1610 1611 class NVPTXTargetInfo : public TargetInfo { 1612 static const char *const GCCRegNames[]; 1613 static const Builtin::Info BuiltinInfo[]; 1614 1615 // The GPU profiles supported by the NVPTX backend 1616 enum GPUKind { 1617 GK_NONE, 1618 GK_SM20, 1619 GK_SM21, 1620 GK_SM30, 1621 GK_SM35, 1622 GK_SM37, 1623 } GPU; 1624 1625 public: 1626 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 1627 : TargetInfo(Triple) { 1628 BigEndian = false; 1629 TLSSupported = false; 1630 LongWidth = LongAlign = 64; 1631 AddrSpaceMap = &NVPTXAddrSpaceMap; 1632 UseAddrSpaceMapMangling = true; 1633 // Define available target features 1634 // These must be defined in sorted order! 1635 NoAsmVariants = true; 1636 // Set the default GPU to sm20 1637 GPU = GK_SM20; 1638 } 1639 void getTargetDefines(const LangOptions &Opts, 1640 MacroBuilder &Builder) const override { 1641 Builder.defineMacro("__PTX__"); 1642 Builder.defineMacro("__NVPTX__"); 1643 if (Opts.CUDAIsDevice) { 1644 // Set __CUDA_ARCH__ for the GPU specified. 1645 std::string CUDAArchCode; 1646 switch (GPU) { 1647 case GK_SM20: 1648 CUDAArchCode = "200"; 1649 break; 1650 case GK_SM21: 1651 CUDAArchCode = "210"; 1652 break; 1653 case GK_SM30: 1654 CUDAArchCode = "300"; 1655 break; 1656 case GK_SM35: 1657 CUDAArchCode = "350"; 1658 break; 1659 case GK_SM37: 1660 CUDAArchCode = "370"; 1661 break; 1662 default: 1663 llvm_unreachable("Unhandled target CPU"); 1664 } 1665 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1666 } 1667 } 1668 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1669 return llvm::makeArrayRef(BuiltinInfo, 1670 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1671 } 1672 bool hasFeature(StringRef Feature) const override { 1673 return Feature == "ptx" || Feature == "nvptx"; 1674 } 1675 1676 ArrayRef<const char *> getGCCRegNames() const override; 1677 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1678 // No aliases. 1679 return None; 1680 } 1681 bool validateAsmConstraint(const char *&Name, 1682 TargetInfo::ConstraintInfo &Info) const override { 1683 switch (*Name) { 1684 default: 1685 return false; 1686 case 'c': 1687 case 'h': 1688 case 'r': 1689 case 'l': 1690 case 'f': 1691 case 'd': 1692 Info.setAllowsRegister(); 1693 return true; 1694 } 1695 } 1696 const char *getClobbers() const override { 1697 // FIXME: Is this really right? 1698 return ""; 1699 } 1700 BuiltinVaListKind getBuiltinVaListKind() const override { 1701 // FIXME: implement 1702 return TargetInfo::CharPtrBuiltinVaList; 1703 } 1704 bool setCPU(const std::string &Name) override { 1705 GPU = llvm::StringSwitch<GPUKind>(Name) 1706 .Case("sm_20", GK_SM20) 1707 .Case("sm_21", GK_SM21) 1708 .Case("sm_30", GK_SM30) 1709 .Case("sm_35", GK_SM35) 1710 .Case("sm_37", GK_SM37) 1711 .Default(GK_NONE); 1712 1713 return GPU != GK_NONE; 1714 } 1715 }; 1716 1717 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1718 #define BUILTIN(ID, TYPE, ATTRS) \ 1719 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1720 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1721 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1722 #include "clang/Basic/BuiltinsNVPTX.def" 1723 }; 1724 1725 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1726 1727 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1728 return llvm::makeArrayRef(GCCRegNames); 1729 } 1730 1731 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1732 public: 1733 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1734 : NVPTXTargetInfo(Triple, Opts) { 1735 LongWidth = LongAlign = 32; 1736 PointerWidth = PointerAlign = 32; 1737 SizeType = TargetInfo::UnsignedInt; 1738 PtrDiffType = TargetInfo::SignedInt; 1739 IntPtrType = TargetInfo::SignedInt; 1740 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1741 } 1742 }; 1743 1744 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1745 public: 1746 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1747 : NVPTXTargetInfo(Triple, Opts) { 1748 PointerWidth = PointerAlign = 64; 1749 SizeType = TargetInfo::UnsignedLong; 1750 PtrDiffType = TargetInfo::SignedLong; 1751 IntPtrType = TargetInfo::SignedLong; 1752 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1753 } 1754 }; 1755 1756 static const unsigned AMDGPUAddrSpaceMap[] = { 1757 1, // opencl_global 1758 3, // opencl_local 1759 2, // opencl_constant 1760 4, // opencl_generic 1761 1, // cuda_device 1762 2, // cuda_constant 1763 3 // cuda_shared 1764 }; 1765 1766 // If you edit the description strings, make sure you update 1767 // getPointerWidthV(). 1768 1769 static const char *const DataLayoutStringR600 = 1770 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1771 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1772 1773 static const char *const DataLayoutStringSI = 1774 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1775 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1776 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1777 1778 class AMDGPUTargetInfo : public TargetInfo { 1779 static const Builtin::Info BuiltinInfo[]; 1780 static const char * const GCCRegNames[]; 1781 1782 /// \brief The GPU profiles supported by the AMDGPU target. 1783 enum GPUKind { 1784 GK_NONE, 1785 GK_R600, 1786 GK_R600_DOUBLE_OPS, 1787 GK_R700, 1788 GK_R700_DOUBLE_OPS, 1789 GK_EVERGREEN, 1790 GK_EVERGREEN_DOUBLE_OPS, 1791 GK_NORTHERN_ISLANDS, 1792 GK_CAYMAN, 1793 GK_SOUTHERN_ISLANDS, 1794 GK_SEA_ISLANDS, 1795 GK_VOLCANIC_ISLANDS 1796 } GPU; 1797 1798 bool hasFP64:1; 1799 bool hasFMAF:1; 1800 bool hasLDEXPF:1; 1801 1802 public: 1803 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 1804 : TargetInfo(Triple) { 1805 if (Triple.getArch() == llvm::Triple::amdgcn) { 1806 resetDataLayout(DataLayoutStringSI); 1807 GPU = GK_SOUTHERN_ISLANDS; 1808 hasFP64 = true; 1809 hasFMAF = true; 1810 hasLDEXPF = true; 1811 } else { 1812 resetDataLayout(DataLayoutStringR600); 1813 GPU = GK_R600; 1814 hasFP64 = false; 1815 hasFMAF = false; 1816 hasLDEXPF = false; 1817 } 1818 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1819 UseAddrSpaceMapMangling = true; 1820 } 1821 1822 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1823 if (GPU <= GK_CAYMAN) 1824 return 32; 1825 1826 switch(AddrSpace) { 1827 default: 1828 return 64; 1829 case 0: 1830 case 3: 1831 case 5: 1832 return 32; 1833 } 1834 } 1835 1836 const char * getClobbers() const override { 1837 return ""; 1838 } 1839 1840 ArrayRef<const char *> getGCCRegNames() const override; 1841 1842 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1843 return None; 1844 } 1845 1846 bool validateAsmConstraint(const char *&Name, 1847 TargetInfo::ConstraintInfo &Info) const override { 1848 switch (*Name) { 1849 default: break; 1850 case 'v': // vgpr 1851 case 's': // sgpr 1852 Info.setAllowsRegister(); 1853 return true; 1854 } 1855 return false; 1856 } 1857 1858 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1859 return llvm::makeArrayRef(BuiltinInfo, 1860 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1861 } 1862 1863 void getTargetDefines(const LangOptions &Opts, 1864 MacroBuilder &Builder) const override { 1865 if (getTriple().getArch() == llvm::Triple::amdgcn) 1866 Builder.defineMacro("__AMDGCN__"); 1867 else 1868 Builder.defineMacro("__R600__"); 1869 1870 if (hasFMAF) 1871 Builder.defineMacro("__HAS_FMAF__"); 1872 if (hasLDEXPF) 1873 Builder.defineMacro("__HAS_LDEXPF__"); 1874 if (hasFP64 && Opts.OpenCL) 1875 Builder.defineMacro("cl_khr_fp64"); 1876 if (Opts.OpenCL) { 1877 if (GPU >= GK_NORTHERN_ISLANDS) { 1878 Builder.defineMacro("cl_khr_byte_addressable_store"); 1879 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1880 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1881 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1882 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1883 } 1884 } 1885 } 1886 1887 BuiltinVaListKind getBuiltinVaListKind() const override { 1888 return TargetInfo::CharPtrBuiltinVaList; 1889 } 1890 1891 bool setCPU(const std::string &Name) override { 1892 GPU = llvm::StringSwitch<GPUKind>(Name) 1893 .Case("r600" , GK_R600) 1894 .Case("rv610", GK_R600) 1895 .Case("rv620", GK_R600) 1896 .Case("rv630", GK_R600) 1897 .Case("rv635", GK_R600) 1898 .Case("rs780", GK_R600) 1899 .Case("rs880", GK_R600) 1900 .Case("rv670", GK_R600_DOUBLE_OPS) 1901 .Case("rv710", GK_R700) 1902 .Case("rv730", GK_R700) 1903 .Case("rv740", GK_R700_DOUBLE_OPS) 1904 .Case("rv770", GK_R700_DOUBLE_OPS) 1905 .Case("palm", GK_EVERGREEN) 1906 .Case("cedar", GK_EVERGREEN) 1907 .Case("sumo", GK_EVERGREEN) 1908 .Case("sumo2", GK_EVERGREEN) 1909 .Case("redwood", GK_EVERGREEN) 1910 .Case("juniper", GK_EVERGREEN) 1911 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1912 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1913 .Case("barts", GK_NORTHERN_ISLANDS) 1914 .Case("turks", GK_NORTHERN_ISLANDS) 1915 .Case("caicos", GK_NORTHERN_ISLANDS) 1916 .Case("cayman", GK_CAYMAN) 1917 .Case("aruba", GK_CAYMAN) 1918 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1919 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1920 .Case("verde", GK_SOUTHERN_ISLANDS) 1921 .Case("oland", GK_SOUTHERN_ISLANDS) 1922 .Case("hainan", GK_SOUTHERN_ISLANDS) 1923 .Case("bonaire", GK_SEA_ISLANDS) 1924 .Case("kabini", GK_SEA_ISLANDS) 1925 .Case("kaveri", GK_SEA_ISLANDS) 1926 .Case("hawaii", GK_SEA_ISLANDS) 1927 .Case("mullins", GK_SEA_ISLANDS) 1928 .Case("tonga", GK_VOLCANIC_ISLANDS) 1929 .Case("iceland", GK_VOLCANIC_ISLANDS) 1930 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1931 .Case("fiji", GK_VOLCANIC_ISLANDS) 1932 .Case("stoney", GK_VOLCANIC_ISLANDS) 1933 .Default(GK_NONE); 1934 1935 if (GPU == GK_NONE) { 1936 return false; 1937 } 1938 1939 // Set the correct data layout 1940 switch (GPU) { 1941 case GK_NONE: 1942 case GK_R600: 1943 case GK_R700: 1944 case GK_EVERGREEN: 1945 case GK_NORTHERN_ISLANDS: 1946 resetDataLayout(DataLayoutStringR600); 1947 hasFP64 = false; 1948 hasFMAF = false; 1949 hasLDEXPF = false; 1950 break; 1951 case GK_R600_DOUBLE_OPS: 1952 case GK_R700_DOUBLE_OPS: 1953 case GK_EVERGREEN_DOUBLE_OPS: 1954 case GK_CAYMAN: 1955 resetDataLayout(DataLayoutStringR600); 1956 hasFP64 = true; 1957 hasFMAF = true; 1958 hasLDEXPF = false; 1959 break; 1960 case GK_SOUTHERN_ISLANDS: 1961 case GK_SEA_ISLANDS: 1962 case GK_VOLCANIC_ISLANDS: 1963 resetDataLayout(DataLayoutStringSI); 1964 hasFP64 = true; 1965 hasFMAF = true; 1966 hasLDEXPF = true; 1967 break; 1968 } 1969 1970 return true; 1971 } 1972 }; 1973 1974 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1975 #define BUILTIN(ID, TYPE, ATTRS) \ 1976 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1977 #include "clang/Basic/BuiltinsAMDGPU.def" 1978 }; 1979 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1980 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1981 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1982 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1983 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1984 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1985 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1986 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1987 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1988 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1989 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1990 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1991 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1992 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1993 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1994 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1995 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1996 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1997 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1998 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1999 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2000 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2001 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2002 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2003 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2004 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2005 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2006 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2007 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2008 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2009 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2010 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2011 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2012 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2013 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2014 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2015 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2016 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2017 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2018 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2019 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2020 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2021 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2022 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2023 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2024 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2025 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2026 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2027 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2028 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2029 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2030 }; 2031 2032 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2033 return llvm::makeArrayRef(GCCRegNames); 2034 } 2035 2036 // Namespace for x86 abstract base class 2037 const Builtin::Info BuiltinInfo[] = { 2038 #define BUILTIN(ID, TYPE, ATTRS) \ 2039 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2040 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2041 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2042 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2043 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2044 #include "clang/Basic/BuiltinsX86.def" 2045 }; 2046 2047 static const char* const GCCRegNames[] = { 2048 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2049 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2050 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2051 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2052 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2053 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2054 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2055 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2056 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2057 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2058 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2059 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2060 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2061 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2062 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2063 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2064 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2065 }; 2066 2067 const TargetInfo::AddlRegName AddlRegNames[] = { 2068 { { "al", "ah", "eax", "rax" }, 0 }, 2069 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2070 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2071 { { "dl", "dh", "edx", "rdx" }, 1 }, 2072 { { "esi", "rsi" }, 4 }, 2073 { { "edi", "rdi" }, 5 }, 2074 { { "esp", "rsp" }, 7 }, 2075 { { "ebp", "rbp" }, 6 }, 2076 { { "r8d", "r8w", "r8b" }, 38 }, 2077 { { "r9d", "r9w", "r9b" }, 39 }, 2078 { { "r10d", "r10w", "r10b" }, 40 }, 2079 { { "r11d", "r11w", "r11b" }, 41 }, 2080 { { "r12d", "r12w", "r12b" }, 42 }, 2081 { { "r13d", "r13w", "r13b" }, 43 }, 2082 { { "r14d", "r14w", "r14b" }, 44 }, 2083 { { "r15d", "r15w", "r15b" }, 45 }, 2084 }; 2085 2086 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2087 // most of the implementation can be shared. 2088 class X86TargetInfo : public TargetInfo { 2089 enum X86SSEEnum { 2090 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2091 } SSELevel = NoSSE; 2092 enum MMX3DNowEnum { 2093 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2094 } MMX3DNowLevel = NoMMX3DNow; 2095 enum XOPEnum { 2096 NoXOP, 2097 SSE4A, 2098 FMA4, 2099 XOP 2100 } XOPLevel = NoXOP; 2101 2102 bool HasAES = false; 2103 bool HasPCLMUL = false; 2104 bool HasLZCNT = false; 2105 bool HasRDRND = false; 2106 bool HasFSGSBASE = false; 2107 bool HasBMI = false; 2108 bool HasBMI2 = false; 2109 bool HasPOPCNT = false; 2110 bool HasRTM = false; 2111 bool HasPRFCHW = false; 2112 bool HasRDSEED = false; 2113 bool HasADX = false; 2114 bool HasTBM = false; 2115 bool HasFMA = false; 2116 bool HasF16C = false; 2117 bool HasAVX512CD = false; 2118 bool HasAVX512ER = false; 2119 bool HasAVX512PF = false; 2120 bool HasAVX512DQ = false; 2121 bool HasAVX512BW = false; 2122 bool HasAVX512VL = false; 2123 bool HasAVX512VBMI = false; 2124 bool HasAVX512IFMA = false; 2125 bool HasSHA = false; 2126 bool HasMPX = false; 2127 bool HasSGX = false; 2128 bool HasCX16 = false; 2129 bool HasFXSR = false; 2130 bool HasXSAVE = false; 2131 bool HasXSAVEOPT = false; 2132 bool HasXSAVEC = false; 2133 bool HasXSAVES = false; 2134 bool HasPKU = false; 2135 bool HasCLFLUSHOPT = false; 2136 bool HasPCOMMIT = false; 2137 bool HasCLWB = false; 2138 bool HasUMIP = false; 2139 bool HasMOVBE = false; 2140 bool HasPREFETCHWT1 = false; 2141 2142 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2143 /// 2144 /// Each enumeration represents a particular CPU supported by Clang. These 2145 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2146 enum CPUKind { 2147 CK_Generic, 2148 2149 /// \name i386 2150 /// i386-generation processors. 2151 //@{ 2152 CK_i386, 2153 //@} 2154 2155 /// \name i486 2156 /// i486-generation processors. 2157 //@{ 2158 CK_i486, 2159 CK_WinChipC6, 2160 CK_WinChip2, 2161 CK_C3, 2162 //@} 2163 2164 /// \name i586 2165 /// i586-generation processors, P5 microarchitecture based. 2166 //@{ 2167 CK_i586, 2168 CK_Pentium, 2169 CK_PentiumMMX, 2170 //@} 2171 2172 /// \name i686 2173 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2174 //@{ 2175 CK_i686, 2176 CK_PentiumPro, 2177 CK_Pentium2, 2178 CK_Pentium3, 2179 CK_Pentium3M, 2180 CK_PentiumM, 2181 CK_C3_2, 2182 2183 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2184 /// Clang however has some logic to suport this. 2185 // FIXME: Warn, deprecate, and potentially remove this. 2186 CK_Yonah, 2187 //@} 2188 2189 /// \name Netburst 2190 /// Netburst microarchitecture based processors. 2191 //@{ 2192 CK_Pentium4, 2193 CK_Pentium4M, 2194 CK_Prescott, 2195 CK_Nocona, 2196 //@} 2197 2198 /// \name Core 2199 /// Core microarchitecture based processors. 2200 //@{ 2201 CK_Core2, 2202 2203 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2204 /// codename which GCC no longer accepts as an option to -march, but Clang 2205 /// has some logic for recognizing it. 2206 // FIXME: Warn, deprecate, and potentially remove this. 2207 CK_Penryn, 2208 //@} 2209 2210 /// \name Atom 2211 /// Atom processors 2212 //@{ 2213 CK_Bonnell, 2214 CK_Silvermont, 2215 //@} 2216 2217 /// \name Nehalem 2218 /// Nehalem microarchitecture based processors. 2219 CK_Nehalem, 2220 2221 /// \name Westmere 2222 /// Westmere microarchitecture based processors. 2223 CK_Westmere, 2224 2225 /// \name Sandy Bridge 2226 /// Sandy Bridge microarchitecture based processors. 2227 CK_SandyBridge, 2228 2229 /// \name Ivy Bridge 2230 /// Ivy Bridge microarchitecture based processors. 2231 CK_IvyBridge, 2232 2233 /// \name Haswell 2234 /// Haswell microarchitecture based processors. 2235 CK_Haswell, 2236 2237 /// \name Broadwell 2238 /// Broadwell microarchitecture based processors. 2239 CK_Broadwell, 2240 2241 /// \name Skylake Client 2242 /// Skylake client microarchitecture based processors. 2243 CK_SkylakeClient, 2244 2245 /// \name Skylake Server 2246 /// Skylake server microarchitecture based processors. 2247 CK_SkylakeServer, 2248 2249 /// \name Cannonlake Client 2250 /// Cannonlake client microarchitecture based processors. 2251 CK_Cannonlake, 2252 2253 /// \name Knights Landing 2254 /// Knights Landing processor. 2255 CK_KNL, 2256 2257 /// \name Lakemont 2258 /// Lakemont microarchitecture based processors. 2259 CK_Lakemont, 2260 2261 /// \name K6 2262 /// K6 architecture processors. 2263 //@{ 2264 CK_K6, 2265 CK_K6_2, 2266 CK_K6_3, 2267 //@} 2268 2269 /// \name K7 2270 /// K7 architecture processors. 2271 //@{ 2272 CK_Athlon, 2273 CK_AthlonThunderbird, 2274 CK_Athlon4, 2275 CK_AthlonXP, 2276 CK_AthlonMP, 2277 //@} 2278 2279 /// \name K8 2280 /// K8 architecture processors. 2281 //@{ 2282 CK_Athlon64, 2283 CK_Athlon64SSE3, 2284 CK_AthlonFX, 2285 CK_K8, 2286 CK_K8SSE3, 2287 CK_Opteron, 2288 CK_OpteronSSE3, 2289 CK_AMDFAM10, 2290 //@} 2291 2292 /// \name Bobcat 2293 /// Bobcat architecture processors. 2294 //@{ 2295 CK_BTVER1, 2296 CK_BTVER2, 2297 //@} 2298 2299 /// \name Bulldozer 2300 /// Bulldozer architecture processors. 2301 //@{ 2302 CK_BDVER1, 2303 CK_BDVER2, 2304 CK_BDVER3, 2305 CK_BDVER4, 2306 //@} 2307 2308 /// This specification is deprecated and will be removed in the future. 2309 /// Users should prefer \see CK_K8. 2310 // FIXME: Warn on this when the CPU is set to it. 2311 //@{ 2312 CK_x86_64, 2313 //@} 2314 2315 /// \name Geode 2316 /// Geode processors. 2317 //@{ 2318 CK_Geode 2319 //@} 2320 } CPU = CK_Generic; 2321 2322 CPUKind getCPUKind(StringRef CPU) const { 2323 return llvm::StringSwitch<CPUKind>(CPU) 2324 .Case("i386", CK_i386) 2325 .Case("i486", CK_i486) 2326 .Case("winchip-c6", CK_WinChipC6) 2327 .Case("winchip2", CK_WinChip2) 2328 .Case("c3", CK_C3) 2329 .Case("i586", CK_i586) 2330 .Case("pentium", CK_Pentium) 2331 .Case("pentium-mmx", CK_PentiumMMX) 2332 .Case("i686", CK_i686) 2333 .Case("pentiumpro", CK_PentiumPro) 2334 .Case("pentium2", CK_Pentium2) 2335 .Case("pentium3", CK_Pentium3) 2336 .Case("pentium3m", CK_Pentium3M) 2337 .Case("pentium-m", CK_PentiumM) 2338 .Case("c3-2", CK_C3_2) 2339 .Case("yonah", CK_Yonah) 2340 .Case("pentium4", CK_Pentium4) 2341 .Case("pentium4m", CK_Pentium4M) 2342 .Case("prescott", CK_Prescott) 2343 .Case("nocona", CK_Nocona) 2344 .Case("core2", CK_Core2) 2345 .Case("penryn", CK_Penryn) 2346 .Case("bonnell", CK_Bonnell) 2347 .Case("atom", CK_Bonnell) // Legacy name. 2348 .Case("silvermont", CK_Silvermont) 2349 .Case("slm", CK_Silvermont) // Legacy name. 2350 .Case("nehalem", CK_Nehalem) 2351 .Case("corei7", CK_Nehalem) // Legacy name. 2352 .Case("westmere", CK_Westmere) 2353 .Case("sandybridge", CK_SandyBridge) 2354 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2355 .Case("ivybridge", CK_IvyBridge) 2356 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2357 .Case("haswell", CK_Haswell) 2358 .Case("core-avx2", CK_Haswell) // Legacy name. 2359 .Case("broadwell", CK_Broadwell) 2360 .Case("skylake", CK_SkylakeClient) 2361 .Case("skylake-avx512", CK_SkylakeServer) 2362 .Case("skx", CK_SkylakeServer) // Legacy name. 2363 .Case("cannonlake", CK_Cannonlake) 2364 .Case("knl", CK_KNL) 2365 .Case("lakemont", CK_Lakemont) 2366 .Case("k6", CK_K6) 2367 .Case("k6-2", CK_K6_2) 2368 .Case("k6-3", CK_K6_3) 2369 .Case("athlon", CK_Athlon) 2370 .Case("athlon-tbird", CK_AthlonThunderbird) 2371 .Case("athlon-4", CK_Athlon4) 2372 .Case("athlon-xp", CK_AthlonXP) 2373 .Case("athlon-mp", CK_AthlonMP) 2374 .Case("athlon64", CK_Athlon64) 2375 .Case("athlon64-sse3", CK_Athlon64SSE3) 2376 .Case("athlon-fx", CK_AthlonFX) 2377 .Case("k8", CK_K8) 2378 .Case("k8-sse3", CK_K8SSE3) 2379 .Case("opteron", CK_Opteron) 2380 .Case("opteron-sse3", CK_OpteronSSE3) 2381 .Case("barcelona", CK_AMDFAM10) 2382 .Case("amdfam10", CK_AMDFAM10) 2383 .Case("btver1", CK_BTVER1) 2384 .Case("btver2", CK_BTVER2) 2385 .Case("bdver1", CK_BDVER1) 2386 .Case("bdver2", CK_BDVER2) 2387 .Case("bdver3", CK_BDVER3) 2388 .Case("bdver4", CK_BDVER4) 2389 .Case("x86-64", CK_x86_64) 2390 .Case("geode", CK_Geode) 2391 .Default(CK_Generic); 2392 } 2393 2394 enum FPMathKind { 2395 FP_Default, 2396 FP_SSE, 2397 FP_387 2398 } FPMath = FP_Default; 2399 2400 public: 2401 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2402 : TargetInfo(Triple) { 2403 BigEndian = false; 2404 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2405 } 2406 unsigned getFloatEvalMethod() const override { 2407 // X87 evaluates with 80 bits "long double" precision. 2408 return SSELevel == NoSSE ? 2 : 0; 2409 } 2410 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2411 return llvm::makeArrayRef(BuiltinInfo, 2412 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2413 } 2414 ArrayRef<const char *> getGCCRegNames() const override { 2415 return llvm::makeArrayRef(GCCRegNames); 2416 } 2417 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2418 return None; 2419 } 2420 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2421 return llvm::makeArrayRef(AddlRegNames); 2422 } 2423 bool validateCpuSupports(StringRef Name) const override; 2424 bool validateAsmConstraint(const char *&Name, 2425 TargetInfo::ConstraintInfo &info) const override; 2426 2427 bool validateGlobalRegisterVariable(StringRef RegName, 2428 unsigned RegSize, 2429 bool &HasSizeMismatch) const override { 2430 // esp and ebp are the only 32-bit registers the x86 backend can currently 2431 // handle. 2432 if (RegName.equals("esp") || RegName.equals("ebp")) { 2433 // Check that the register size is 32-bit. 2434 HasSizeMismatch = RegSize != 32; 2435 return true; 2436 } 2437 2438 return false; 2439 } 2440 2441 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2442 2443 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2444 2445 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2446 2447 std::string convertConstraint(const char *&Constraint) const override; 2448 const char *getClobbers() const override { 2449 return "~{dirflag},~{fpsr},~{flags}"; 2450 } 2451 void getTargetDefines(const LangOptions &Opts, 2452 MacroBuilder &Builder) const override; 2453 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2454 bool Enabled); 2455 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2456 bool Enabled); 2457 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2458 bool Enabled); 2459 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2460 StringRef Name, bool Enabled) const override { 2461 setFeatureEnabledImpl(Features, Name, Enabled); 2462 } 2463 // This exists purely to cut down on the number of virtual calls in 2464 // initFeatureMap which calls this repeatedly. 2465 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2466 StringRef Name, bool Enabled); 2467 bool 2468 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2469 StringRef CPU, 2470 const std::vector<std::string> &FeaturesVec) const override; 2471 bool hasFeature(StringRef Feature) const override; 2472 bool handleTargetFeatures(std::vector<std::string> &Features, 2473 DiagnosticsEngine &Diags) override; 2474 StringRef getABI() const override { 2475 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2476 return "avx512"; 2477 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2478 return "avx"; 2479 if (getTriple().getArch() == llvm::Triple::x86 && 2480 MMX3DNowLevel == NoMMX3DNow) 2481 return "no-mmx"; 2482 return ""; 2483 } 2484 bool setCPU(const std::string &Name) override { 2485 CPU = getCPUKind(Name); 2486 2487 // Perform any per-CPU checks necessary to determine if this CPU is 2488 // acceptable. 2489 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2490 // invalid without explaining *why*. 2491 switch (CPU) { 2492 case CK_Generic: 2493 // No processor selected! 2494 return false; 2495 2496 case CK_i386: 2497 case CK_i486: 2498 case CK_WinChipC6: 2499 case CK_WinChip2: 2500 case CK_C3: 2501 case CK_i586: 2502 case CK_Pentium: 2503 case CK_PentiumMMX: 2504 case CK_i686: 2505 case CK_PentiumPro: 2506 case CK_Pentium2: 2507 case CK_Pentium3: 2508 case CK_Pentium3M: 2509 case CK_PentiumM: 2510 case CK_Yonah: 2511 case CK_C3_2: 2512 case CK_Pentium4: 2513 case CK_Pentium4M: 2514 case CK_Lakemont: 2515 case CK_Prescott: 2516 case CK_K6: 2517 case CK_K6_2: 2518 case CK_K6_3: 2519 case CK_Athlon: 2520 case CK_AthlonThunderbird: 2521 case CK_Athlon4: 2522 case CK_AthlonXP: 2523 case CK_AthlonMP: 2524 case CK_Geode: 2525 // Only accept certain architectures when compiling in 32-bit mode. 2526 if (getTriple().getArch() != llvm::Triple::x86) 2527 return false; 2528 2529 // Fallthrough 2530 case CK_Nocona: 2531 case CK_Core2: 2532 case CK_Penryn: 2533 case CK_Bonnell: 2534 case CK_Silvermont: 2535 case CK_Nehalem: 2536 case CK_Westmere: 2537 case CK_SandyBridge: 2538 case CK_IvyBridge: 2539 case CK_Haswell: 2540 case CK_Broadwell: 2541 case CK_SkylakeClient: 2542 case CK_SkylakeServer: 2543 case CK_Cannonlake: 2544 case CK_KNL: 2545 case CK_Athlon64: 2546 case CK_Athlon64SSE3: 2547 case CK_AthlonFX: 2548 case CK_K8: 2549 case CK_K8SSE3: 2550 case CK_Opteron: 2551 case CK_OpteronSSE3: 2552 case CK_AMDFAM10: 2553 case CK_BTVER1: 2554 case CK_BTVER2: 2555 case CK_BDVER1: 2556 case CK_BDVER2: 2557 case CK_BDVER3: 2558 case CK_BDVER4: 2559 case CK_x86_64: 2560 return true; 2561 } 2562 llvm_unreachable("Unhandled CPU kind"); 2563 } 2564 2565 bool setFPMath(StringRef Name) override; 2566 2567 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2568 // Most of the non-ARM calling conventions are i386 conventions. 2569 switch (CC) { 2570 case CC_X86ThisCall: 2571 case CC_X86FastCall: 2572 case CC_X86StdCall: 2573 case CC_X86VectorCall: 2574 case CC_C: 2575 case CC_Swift: 2576 case CC_X86Pascal: 2577 case CC_IntelOclBicc: 2578 return CCCR_OK; 2579 default: 2580 return CCCR_Warning; 2581 } 2582 } 2583 2584 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2585 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2586 } 2587 2588 bool hasSjLjLowering() const override { 2589 return true; 2590 } 2591 }; 2592 2593 bool X86TargetInfo::setFPMath(StringRef Name) { 2594 if (Name == "387") { 2595 FPMath = FP_387; 2596 return true; 2597 } 2598 if (Name == "sse") { 2599 FPMath = FP_SSE; 2600 return true; 2601 } 2602 return false; 2603 } 2604 2605 bool X86TargetInfo::initFeatureMap( 2606 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2607 const std::vector<std::string> &FeaturesVec) const { 2608 // FIXME: This *really* should not be here. 2609 // X86_64 always has SSE2. 2610 if (getTriple().getArch() == llvm::Triple::x86_64) 2611 setFeatureEnabledImpl(Features, "sse2", true); 2612 2613 const CPUKind Kind = getCPUKind(CPU); 2614 2615 // Enable X87 for all X86 processors but Lakemont. 2616 if (Kind != CK_Lakemont) 2617 setFeatureEnabledImpl(Features, "x87", true); 2618 2619 switch (Kind) { 2620 case CK_Generic: 2621 case CK_i386: 2622 case CK_i486: 2623 case CK_i586: 2624 case CK_Pentium: 2625 case CK_i686: 2626 case CK_PentiumPro: 2627 case CK_Lakemont: 2628 break; 2629 case CK_PentiumMMX: 2630 case CK_Pentium2: 2631 case CK_K6: 2632 case CK_WinChipC6: 2633 setFeatureEnabledImpl(Features, "mmx", true); 2634 break; 2635 case CK_Pentium3: 2636 case CK_Pentium3M: 2637 case CK_C3_2: 2638 setFeatureEnabledImpl(Features, "sse", true); 2639 setFeatureEnabledImpl(Features, "fxsr", true); 2640 break; 2641 case CK_PentiumM: 2642 case CK_Pentium4: 2643 case CK_Pentium4M: 2644 case CK_x86_64: 2645 setFeatureEnabledImpl(Features, "sse2", true); 2646 setFeatureEnabledImpl(Features, "fxsr", true); 2647 break; 2648 case CK_Yonah: 2649 case CK_Prescott: 2650 case CK_Nocona: 2651 setFeatureEnabledImpl(Features, "sse3", true); 2652 setFeatureEnabledImpl(Features, "fxsr", true); 2653 setFeatureEnabledImpl(Features, "cx16", true); 2654 break; 2655 case CK_Core2: 2656 case CK_Bonnell: 2657 setFeatureEnabledImpl(Features, "ssse3", true); 2658 setFeatureEnabledImpl(Features, "fxsr", true); 2659 setFeatureEnabledImpl(Features, "cx16", true); 2660 break; 2661 case CK_Penryn: 2662 setFeatureEnabledImpl(Features, "sse4.1", true); 2663 setFeatureEnabledImpl(Features, "fxsr", true); 2664 setFeatureEnabledImpl(Features, "cx16", true); 2665 break; 2666 case CK_Cannonlake: 2667 setFeatureEnabledImpl(Features, "avx512ifma", true); 2668 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2669 setFeatureEnabledImpl(Features, "sha", true); 2670 setFeatureEnabledImpl(Features, "umip", true); 2671 // FALLTHROUGH 2672 case CK_SkylakeServer: 2673 setFeatureEnabledImpl(Features, "avx512f", true); 2674 setFeatureEnabledImpl(Features, "avx512cd", true); 2675 setFeatureEnabledImpl(Features, "avx512dq", true); 2676 setFeatureEnabledImpl(Features, "avx512bw", true); 2677 setFeatureEnabledImpl(Features, "avx512vl", true); 2678 setFeatureEnabledImpl(Features, "pku", true); 2679 setFeatureEnabledImpl(Features, "pcommit", true); 2680 setFeatureEnabledImpl(Features, "clwb", true); 2681 // FALLTHROUGH 2682 case CK_SkylakeClient: 2683 setFeatureEnabledImpl(Features, "xsavec", true); 2684 setFeatureEnabledImpl(Features, "xsaves", true); 2685 setFeatureEnabledImpl(Features, "mpx", true); 2686 setFeatureEnabledImpl(Features, "sgx", true); 2687 setFeatureEnabledImpl(Features, "clflushopt", true); 2688 // FALLTHROUGH 2689 case CK_Broadwell: 2690 setFeatureEnabledImpl(Features, "rdseed", true); 2691 setFeatureEnabledImpl(Features, "adx", true); 2692 // FALLTHROUGH 2693 case CK_Haswell: 2694 setFeatureEnabledImpl(Features, "avx2", true); 2695 setFeatureEnabledImpl(Features, "lzcnt", true); 2696 setFeatureEnabledImpl(Features, "bmi", true); 2697 setFeatureEnabledImpl(Features, "bmi2", true); 2698 setFeatureEnabledImpl(Features, "rtm", true); 2699 setFeatureEnabledImpl(Features, "fma", true); 2700 setFeatureEnabledImpl(Features, "movbe", true); 2701 // FALLTHROUGH 2702 case CK_IvyBridge: 2703 setFeatureEnabledImpl(Features, "rdrnd", true); 2704 setFeatureEnabledImpl(Features, "f16c", true); 2705 setFeatureEnabledImpl(Features, "fsgsbase", true); 2706 // FALLTHROUGH 2707 case CK_SandyBridge: 2708 setFeatureEnabledImpl(Features, "avx", true); 2709 setFeatureEnabledImpl(Features, "xsave", true); 2710 setFeatureEnabledImpl(Features, "xsaveopt", true); 2711 // FALLTHROUGH 2712 case CK_Westmere: 2713 case CK_Silvermont: 2714 setFeatureEnabledImpl(Features, "aes", true); 2715 setFeatureEnabledImpl(Features, "pclmul", true); 2716 // FALLTHROUGH 2717 case CK_Nehalem: 2718 setFeatureEnabledImpl(Features, "sse4.2", true); 2719 setFeatureEnabledImpl(Features, "fxsr", true); 2720 setFeatureEnabledImpl(Features, "cx16", true); 2721 break; 2722 case CK_KNL: 2723 setFeatureEnabledImpl(Features, "avx512f", true); 2724 setFeatureEnabledImpl(Features, "avx512cd", true); 2725 setFeatureEnabledImpl(Features, "avx512er", true); 2726 setFeatureEnabledImpl(Features, "avx512pf", true); 2727 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2728 setFeatureEnabledImpl(Features, "fxsr", true); 2729 setFeatureEnabledImpl(Features, "rdseed", true); 2730 setFeatureEnabledImpl(Features, "adx", true); 2731 setFeatureEnabledImpl(Features, "lzcnt", true); 2732 setFeatureEnabledImpl(Features, "bmi", true); 2733 setFeatureEnabledImpl(Features, "bmi2", true); 2734 setFeatureEnabledImpl(Features, "rtm", true); 2735 setFeatureEnabledImpl(Features, "fma", true); 2736 setFeatureEnabledImpl(Features, "rdrnd", true); 2737 setFeatureEnabledImpl(Features, "f16c", true); 2738 setFeatureEnabledImpl(Features, "fsgsbase", true); 2739 setFeatureEnabledImpl(Features, "aes", true); 2740 setFeatureEnabledImpl(Features, "pclmul", true); 2741 setFeatureEnabledImpl(Features, "cx16", true); 2742 setFeatureEnabledImpl(Features, "xsaveopt", true); 2743 setFeatureEnabledImpl(Features, "xsave", true); 2744 setFeatureEnabledImpl(Features, "movbe", true); 2745 break; 2746 case CK_K6_2: 2747 case CK_K6_3: 2748 case CK_WinChip2: 2749 case CK_C3: 2750 setFeatureEnabledImpl(Features, "3dnow", true); 2751 break; 2752 case CK_Athlon: 2753 case CK_AthlonThunderbird: 2754 case CK_Geode: 2755 setFeatureEnabledImpl(Features, "3dnowa", true); 2756 break; 2757 case CK_Athlon4: 2758 case CK_AthlonXP: 2759 case CK_AthlonMP: 2760 setFeatureEnabledImpl(Features, "sse", true); 2761 setFeatureEnabledImpl(Features, "3dnowa", true); 2762 setFeatureEnabledImpl(Features, "fxsr", true); 2763 break; 2764 case CK_K8: 2765 case CK_Opteron: 2766 case CK_Athlon64: 2767 case CK_AthlonFX: 2768 setFeatureEnabledImpl(Features, "sse2", true); 2769 setFeatureEnabledImpl(Features, "3dnowa", true); 2770 setFeatureEnabledImpl(Features, "fxsr", true); 2771 break; 2772 case CK_AMDFAM10: 2773 setFeatureEnabledImpl(Features, "sse4a", true); 2774 setFeatureEnabledImpl(Features, "lzcnt", true); 2775 setFeatureEnabledImpl(Features, "popcnt", true); 2776 // FALLTHROUGH 2777 case CK_K8SSE3: 2778 case CK_OpteronSSE3: 2779 case CK_Athlon64SSE3: 2780 setFeatureEnabledImpl(Features, "sse3", true); 2781 setFeatureEnabledImpl(Features, "3dnowa", true); 2782 setFeatureEnabledImpl(Features, "fxsr", true); 2783 break; 2784 case CK_BTVER2: 2785 setFeatureEnabledImpl(Features, "avx", true); 2786 setFeatureEnabledImpl(Features, "aes", true); 2787 setFeatureEnabledImpl(Features, "pclmul", true); 2788 setFeatureEnabledImpl(Features, "bmi", true); 2789 setFeatureEnabledImpl(Features, "f16c", true); 2790 setFeatureEnabledImpl(Features, "xsaveopt", true); 2791 // FALLTHROUGH 2792 case CK_BTVER1: 2793 setFeatureEnabledImpl(Features, "ssse3", true); 2794 setFeatureEnabledImpl(Features, "sse4a", true); 2795 setFeatureEnabledImpl(Features, "lzcnt", true); 2796 setFeatureEnabledImpl(Features, "popcnt", true); 2797 setFeatureEnabledImpl(Features, "prfchw", true); 2798 setFeatureEnabledImpl(Features, "cx16", true); 2799 setFeatureEnabledImpl(Features, "fxsr", true); 2800 break; 2801 case CK_BDVER4: 2802 setFeatureEnabledImpl(Features, "avx2", true); 2803 setFeatureEnabledImpl(Features, "bmi2", true); 2804 // FALLTHROUGH 2805 case CK_BDVER3: 2806 setFeatureEnabledImpl(Features, "fsgsbase", true); 2807 setFeatureEnabledImpl(Features, "xsaveopt", true); 2808 // FALLTHROUGH 2809 case CK_BDVER2: 2810 setFeatureEnabledImpl(Features, "bmi", true); 2811 setFeatureEnabledImpl(Features, "fma", true); 2812 setFeatureEnabledImpl(Features, "f16c", true); 2813 setFeatureEnabledImpl(Features, "tbm", true); 2814 // FALLTHROUGH 2815 case CK_BDVER1: 2816 // xop implies avx, sse4a and fma4. 2817 setFeatureEnabledImpl(Features, "xop", true); 2818 setFeatureEnabledImpl(Features, "lzcnt", true); 2819 setFeatureEnabledImpl(Features, "aes", true); 2820 setFeatureEnabledImpl(Features, "pclmul", true); 2821 setFeatureEnabledImpl(Features, "prfchw", true); 2822 setFeatureEnabledImpl(Features, "cx16", true); 2823 setFeatureEnabledImpl(Features, "fxsr", true); 2824 setFeatureEnabledImpl(Features, "xsave", true); 2825 break; 2826 } 2827 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2828 return false; 2829 2830 // Can't do this earlier because we need to be able to explicitly enable 2831 // or disable these features and the things that they depend upon. 2832 2833 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2834 auto I = Features.find("sse4.2"); 2835 if (I != Features.end() && I->getValue() && 2836 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2837 FeaturesVec.end()) 2838 Features["popcnt"] = true; 2839 2840 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2841 I = Features.find("3dnow"); 2842 if (I != Features.end() && I->getValue() && 2843 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2844 FeaturesVec.end()) 2845 Features["prfchw"] = true; 2846 2847 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2848 // then enable MMX. 2849 I = Features.find("sse"); 2850 if (I != Features.end() && I->getValue() && 2851 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2852 FeaturesVec.end()) 2853 Features["mmx"] = true; 2854 2855 return true; 2856 } 2857 2858 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2859 X86SSEEnum Level, bool Enabled) { 2860 if (Enabled) { 2861 switch (Level) { 2862 case AVX512F: 2863 Features["avx512f"] = true; 2864 case AVX2: 2865 Features["avx2"] = true; 2866 case AVX: 2867 Features["avx"] = true; 2868 Features["xsave"] = true; 2869 case SSE42: 2870 Features["sse4.2"] = true; 2871 case SSE41: 2872 Features["sse4.1"] = true; 2873 case SSSE3: 2874 Features["ssse3"] = true; 2875 case SSE3: 2876 Features["sse3"] = true; 2877 case SSE2: 2878 Features["sse2"] = true; 2879 case SSE1: 2880 Features["sse"] = true; 2881 case NoSSE: 2882 break; 2883 } 2884 return; 2885 } 2886 2887 switch (Level) { 2888 case NoSSE: 2889 case SSE1: 2890 Features["sse"] = false; 2891 case SSE2: 2892 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2893 Features["sha"] = false; 2894 case SSE3: 2895 Features["sse3"] = false; 2896 setXOPLevel(Features, NoXOP, false); 2897 case SSSE3: 2898 Features["ssse3"] = false; 2899 case SSE41: 2900 Features["sse4.1"] = false; 2901 case SSE42: 2902 Features["sse4.2"] = false; 2903 case AVX: 2904 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2905 Features["xsaveopt"] = false; 2906 setXOPLevel(Features, FMA4, false); 2907 case AVX2: 2908 Features["avx2"] = false; 2909 case AVX512F: 2910 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2911 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2912 Features["avx512vl"] = Features["avx512vbmi"] = 2913 Features["avx512ifma"] = false; 2914 } 2915 } 2916 2917 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2918 MMX3DNowEnum Level, bool Enabled) { 2919 if (Enabled) { 2920 switch (Level) { 2921 case AMD3DNowAthlon: 2922 Features["3dnowa"] = true; 2923 case AMD3DNow: 2924 Features["3dnow"] = true; 2925 case MMX: 2926 Features["mmx"] = true; 2927 case NoMMX3DNow: 2928 break; 2929 } 2930 return; 2931 } 2932 2933 switch (Level) { 2934 case NoMMX3DNow: 2935 case MMX: 2936 Features["mmx"] = false; 2937 case AMD3DNow: 2938 Features["3dnow"] = false; 2939 case AMD3DNowAthlon: 2940 Features["3dnowa"] = false; 2941 } 2942 } 2943 2944 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2945 bool Enabled) { 2946 if (Enabled) { 2947 switch (Level) { 2948 case XOP: 2949 Features["xop"] = true; 2950 case FMA4: 2951 Features["fma4"] = true; 2952 setSSELevel(Features, AVX, true); 2953 case SSE4A: 2954 Features["sse4a"] = true; 2955 setSSELevel(Features, SSE3, true); 2956 case NoXOP: 2957 break; 2958 } 2959 return; 2960 } 2961 2962 switch (Level) { 2963 case NoXOP: 2964 case SSE4A: 2965 Features["sse4a"] = false; 2966 case FMA4: 2967 Features["fma4"] = false; 2968 case XOP: 2969 Features["xop"] = false; 2970 } 2971 } 2972 2973 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2974 StringRef Name, bool Enabled) { 2975 // This is a bit of a hack to deal with the sse4 target feature when used 2976 // as part of the target attribute. We handle sse4 correctly everywhere 2977 // else. See below for more information on how we handle the sse4 options. 2978 if (Name != "sse4") 2979 Features[Name] = Enabled; 2980 2981 if (Name == "mmx") { 2982 setMMXLevel(Features, MMX, Enabled); 2983 } else if (Name == "sse") { 2984 setSSELevel(Features, SSE1, Enabled); 2985 } else if (Name == "sse2") { 2986 setSSELevel(Features, SSE2, Enabled); 2987 } else if (Name == "sse3") { 2988 setSSELevel(Features, SSE3, Enabled); 2989 } else if (Name == "ssse3") { 2990 setSSELevel(Features, SSSE3, Enabled); 2991 } else if (Name == "sse4.2") { 2992 setSSELevel(Features, SSE42, Enabled); 2993 } else if (Name == "sse4.1") { 2994 setSSELevel(Features, SSE41, Enabled); 2995 } else if (Name == "3dnow") { 2996 setMMXLevel(Features, AMD3DNow, Enabled); 2997 } else if (Name == "3dnowa") { 2998 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2999 } else if (Name == "aes") { 3000 if (Enabled) 3001 setSSELevel(Features, SSE2, Enabled); 3002 } else if (Name == "pclmul") { 3003 if (Enabled) 3004 setSSELevel(Features, SSE2, Enabled); 3005 } else if (Name == "avx") { 3006 setSSELevel(Features, AVX, Enabled); 3007 } else if (Name == "avx2") { 3008 setSSELevel(Features, AVX2, Enabled); 3009 } else if (Name == "avx512f") { 3010 setSSELevel(Features, AVX512F, Enabled); 3011 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3012 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3013 Name == "avx512vbmi" || Name == "avx512ifma") { 3014 if (Enabled) 3015 setSSELevel(Features, AVX512F, Enabled); 3016 } else if (Name == "fma") { 3017 if (Enabled) 3018 setSSELevel(Features, AVX, Enabled); 3019 } else if (Name == "fma4") { 3020 setXOPLevel(Features, FMA4, Enabled); 3021 } else if (Name == "xop") { 3022 setXOPLevel(Features, XOP, Enabled); 3023 } else if (Name == "sse4a") { 3024 setXOPLevel(Features, SSE4A, Enabled); 3025 } else if (Name == "f16c") { 3026 if (Enabled) 3027 setSSELevel(Features, AVX, Enabled); 3028 } else if (Name == "sha") { 3029 if (Enabled) 3030 setSSELevel(Features, SSE2, Enabled); 3031 } else if (Name == "sse4") { 3032 // We can get here via the __target__ attribute since that's not controlled 3033 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3034 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3035 // disabled. 3036 if (Enabled) 3037 setSSELevel(Features, SSE42, Enabled); 3038 else 3039 setSSELevel(Features, SSE41, Enabled); 3040 } else if (Name == "xsave") { 3041 if (!Enabled) 3042 Features["xsaveopt"] = false; 3043 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3044 if (Enabled) 3045 Features["xsave"] = true; 3046 } 3047 } 3048 3049 /// handleTargetFeatures - Perform initialization based on the user 3050 /// configured set of features. 3051 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3052 DiagnosticsEngine &Diags) { 3053 for (const auto &Feature : Features) { 3054 if (Feature[0] != '+') 3055 continue; 3056 3057 if (Feature == "+aes") { 3058 HasAES = true; 3059 } else if (Feature == "+pclmul") { 3060 HasPCLMUL = true; 3061 } else if (Feature == "+lzcnt") { 3062 HasLZCNT = true; 3063 } else if (Feature == "+rdrnd") { 3064 HasRDRND = true; 3065 } else if (Feature == "+fsgsbase") { 3066 HasFSGSBASE = true; 3067 } else if (Feature == "+bmi") { 3068 HasBMI = true; 3069 } else if (Feature == "+bmi2") { 3070 HasBMI2 = true; 3071 } else if (Feature == "+popcnt") { 3072 HasPOPCNT = true; 3073 } else if (Feature == "+rtm") { 3074 HasRTM = true; 3075 } else if (Feature == "+prfchw") { 3076 HasPRFCHW = true; 3077 } else if (Feature == "+rdseed") { 3078 HasRDSEED = true; 3079 } else if (Feature == "+adx") { 3080 HasADX = true; 3081 } else if (Feature == "+tbm") { 3082 HasTBM = true; 3083 } else if (Feature == "+fma") { 3084 HasFMA = true; 3085 } else if (Feature == "+f16c") { 3086 HasF16C = true; 3087 } else if (Feature == "+avx512cd") { 3088 HasAVX512CD = true; 3089 } else if (Feature == "+avx512er") { 3090 HasAVX512ER = true; 3091 } else if (Feature == "+avx512pf") { 3092 HasAVX512PF = true; 3093 } else if (Feature == "+avx512dq") { 3094 HasAVX512DQ = true; 3095 } else if (Feature == "+avx512bw") { 3096 HasAVX512BW = true; 3097 } else if (Feature == "+avx512vl") { 3098 HasAVX512VL = true; 3099 } else if (Feature == "+avx512vbmi") { 3100 HasAVX512VBMI = true; 3101 } else if (Feature == "+avx512ifma") { 3102 HasAVX512IFMA = true; 3103 } else if (Feature == "+sha") { 3104 HasSHA = true; 3105 } else if (Feature == "+mpx") { 3106 HasMPX = true; 3107 } else if (Feature == "+movbe") { 3108 HasMOVBE = true; 3109 } else if (Feature == "+sgx") { 3110 HasSGX = true; 3111 } else if (Feature == "+cx16") { 3112 HasCX16 = true; 3113 } else if (Feature == "+fxsr") { 3114 HasFXSR = true; 3115 } else if (Feature == "+xsave") { 3116 HasXSAVE = true; 3117 } else if (Feature == "+xsaveopt") { 3118 HasXSAVEOPT = true; 3119 } else if (Feature == "+xsavec") { 3120 HasXSAVEC = true; 3121 } else if (Feature == "+xsaves") { 3122 HasXSAVES = true; 3123 } else if (Feature == "+pku") { 3124 HasPKU = true; 3125 } else if (Feature == "+clflushopt") { 3126 HasCLFLUSHOPT = true; 3127 } else if (Feature == "+pcommit") { 3128 HasPCOMMIT = true; 3129 } else if (Feature == "+clwb") { 3130 HasCLWB = true; 3131 } else if (Feature == "+umip") { 3132 HasUMIP = true; 3133 } else if (Feature == "+prefetchwt1") { 3134 HasPREFETCHWT1 = true; 3135 } 3136 3137 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3138 .Case("+avx512f", AVX512F) 3139 .Case("+avx2", AVX2) 3140 .Case("+avx", AVX) 3141 .Case("+sse4.2", SSE42) 3142 .Case("+sse4.1", SSE41) 3143 .Case("+ssse3", SSSE3) 3144 .Case("+sse3", SSE3) 3145 .Case("+sse2", SSE2) 3146 .Case("+sse", SSE1) 3147 .Default(NoSSE); 3148 SSELevel = std::max(SSELevel, Level); 3149 3150 MMX3DNowEnum ThreeDNowLevel = 3151 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3152 .Case("+3dnowa", AMD3DNowAthlon) 3153 .Case("+3dnow", AMD3DNow) 3154 .Case("+mmx", MMX) 3155 .Default(NoMMX3DNow); 3156 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3157 3158 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3159 .Case("+xop", XOP) 3160 .Case("+fma4", FMA4) 3161 .Case("+sse4a", SSE4A) 3162 .Default(NoXOP); 3163 XOPLevel = std::max(XOPLevel, XLevel); 3164 } 3165 3166 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3167 // matches the selected sse level. 3168 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3169 (FPMath == FP_387 && SSELevel >= SSE1)) { 3170 Diags.Report(diag::err_target_unsupported_fpmath) << 3171 (FPMath == FP_SSE ? "sse" : "387"); 3172 return false; 3173 } 3174 3175 SimdDefaultAlign = 3176 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3177 return true; 3178 } 3179 3180 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3181 /// definitions for this particular subtarget. 3182 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3183 MacroBuilder &Builder) const { 3184 // Target identification. 3185 if (getTriple().getArch() == llvm::Triple::x86_64) { 3186 Builder.defineMacro("__amd64__"); 3187 Builder.defineMacro("__amd64"); 3188 Builder.defineMacro("__x86_64"); 3189 Builder.defineMacro("__x86_64__"); 3190 if (getTriple().getArchName() == "x86_64h") { 3191 Builder.defineMacro("__x86_64h"); 3192 Builder.defineMacro("__x86_64h__"); 3193 } 3194 } else { 3195 DefineStd(Builder, "i386", Opts); 3196 } 3197 3198 // Subtarget options. 3199 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3200 // truly should be based on -mtune options. 3201 switch (CPU) { 3202 case CK_Generic: 3203 break; 3204 case CK_i386: 3205 // The rest are coming from the i386 define above. 3206 Builder.defineMacro("__tune_i386__"); 3207 break; 3208 case CK_i486: 3209 case CK_WinChipC6: 3210 case CK_WinChip2: 3211 case CK_C3: 3212 defineCPUMacros(Builder, "i486"); 3213 break; 3214 case CK_PentiumMMX: 3215 Builder.defineMacro("__pentium_mmx__"); 3216 Builder.defineMacro("__tune_pentium_mmx__"); 3217 // Fallthrough 3218 case CK_i586: 3219 case CK_Pentium: 3220 defineCPUMacros(Builder, "i586"); 3221 defineCPUMacros(Builder, "pentium"); 3222 break; 3223 case CK_Pentium3: 3224 case CK_Pentium3M: 3225 case CK_PentiumM: 3226 Builder.defineMacro("__tune_pentium3__"); 3227 // Fallthrough 3228 case CK_Pentium2: 3229 case CK_C3_2: 3230 Builder.defineMacro("__tune_pentium2__"); 3231 // Fallthrough 3232 case CK_PentiumPro: 3233 Builder.defineMacro("__tune_i686__"); 3234 Builder.defineMacro("__tune_pentiumpro__"); 3235 // Fallthrough 3236 case CK_i686: 3237 Builder.defineMacro("__i686"); 3238 Builder.defineMacro("__i686__"); 3239 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3240 Builder.defineMacro("__pentiumpro"); 3241 Builder.defineMacro("__pentiumpro__"); 3242 break; 3243 case CK_Pentium4: 3244 case CK_Pentium4M: 3245 defineCPUMacros(Builder, "pentium4"); 3246 break; 3247 case CK_Yonah: 3248 case CK_Prescott: 3249 case CK_Nocona: 3250 defineCPUMacros(Builder, "nocona"); 3251 break; 3252 case CK_Core2: 3253 case CK_Penryn: 3254 defineCPUMacros(Builder, "core2"); 3255 break; 3256 case CK_Bonnell: 3257 defineCPUMacros(Builder, "atom"); 3258 break; 3259 case CK_Silvermont: 3260 defineCPUMacros(Builder, "slm"); 3261 break; 3262 case CK_Nehalem: 3263 case CK_Westmere: 3264 case CK_SandyBridge: 3265 case CK_IvyBridge: 3266 case CK_Haswell: 3267 case CK_Broadwell: 3268 case CK_SkylakeClient: 3269 // FIXME: Historically, we defined this legacy name, it would be nice to 3270 // remove it at some point. We've never exposed fine-grained names for 3271 // recent primary x86 CPUs, and we should keep it that way. 3272 defineCPUMacros(Builder, "corei7"); 3273 break; 3274 case CK_SkylakeServer: 3275 defineCPUMacros(Builder, "skx"); 3276 break; 3277 case CK_Cannonlake: 3278 break; 3279 case CK_KNL: 3280 defineCPUMacros(Builder, "knl"); 3281 break; 3282 case CK_Lakemont: 3283 Builder.defineMacro("__tune_lakemont__"); 3284 break; 3285 case CK_K6_2: 3286 Builder.defineMacro("__k6_2__"); 3287 Builder.defineMacro("__tune_k6_2__"); 3288 // Fallthrough 3289 case CK_K6_3: 3290 if (CPU != CK_K6_2) { // In case of fallthrough 3291 // FIXME: GCC may be enabling these in cases where some other k6 3292 // architecture is specified but -m3dnow is explicitly provided. The 3293 // exact semantics need to be determined and emulated here. 3294 Builder.defineMacro("__k6_3__"); 3295 Builder.defineMacro("__tune_k6_3__"); 3296 } 3297 // Fallthrough 3298 case CK_K6: 3299 defineCPUMacros(Builder, "k6"); 3300 break; 3301 case CK_Athlon: 3302 case CK_AthlonThunderbird: 3303 case CK_Athlon4: 3304 case CK_AthlonXP: 3305 case CK_AthlonMP: 3306 defineCPUMacros(Builder, "athlon"); 3307 if (SSELevel != NoSSE) { 3308 Builder.defineMacro("__athlon_sse__"); 3309 Builder.defineMacro("__tune_athlon_sse__"); 3310 } 3311 break; 3312 case CK_K8: 3313 case CK_K8SSE3: 3314 case CK_x86_64: 3315 case CK_Opteron: 3316 case CK_OpteronSSE3: 3317 case CK_Athlon64: 3318 case CK_Athlon64SSE3: 3319 case CK_AthlonFX: 3320 defineCPUMacros(Builder, "k8"); 3321 break; 3322 case CK_AMDFAM10: 3323 defineCPUMacros(Builder, "amdfam10"); 3324 break; 3325 case CK_BTVER1: 3326 defineCPUMacros(Builder, "btver1"); 3327 break; 3328 case CK_BTVER2: 3329 defineCPUMacros(Builder, "btver2"); 3330 break; 3331 case CK_BDVER1: 3332 defineCPUMacros(Builder, "bdver1"); 3333 break; 3334 case CK_BDVER2: 3335 defineCPUMacros(Builder, "bdver2"); 3336 break; 3337 case CK_BDVER3: 3338 defineCPUMacros(Builder, "bdver3"); 3339 break; 3340 case CK_BDVER4: 3341 defineCPUMacros(Builder, "bdver4"); 3342 break; 3343 case CK_Geode: 3344 defineCPUMacros(Builder, "geode"); 3345 break; 3346 } 3347 3348 // Target properties. 3349 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3350 3351 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3352 // functions in glibc header files that use FP Stack inline asm which the 3353 // backend can't deal with (PR879). 3354 Builder.defineMacro("__NO_MATH_INLINES"); 3355 3356 if (HasAES) 3357 Builder.defineMacro("__AES__"); 3358 3359 if (HasPCLMUL) 3360 Builder.defineMacro("__PCLMUL__"); 3361 3362 if (HasLZCNT) 3363 Builder.defineMacro("__LZCNT__"); 3364 3365 if (HasRDRND) 3366 Builder.defineMacro("__RDRND__"); 3367 3368 if (HasFSGSBASE) 3369 Builder.defineMacro("__FSGSBASE__"); 3370 3371 if (HasBMI) 3372 Builder.defineMacro("__BMI__"); 3373 3374 if (HasBMI2) 3375 Builder.defineMacro("__BMI2__"); 3376 3377 if (HasPOPCNT) 3378 Builder.defineMacro("__POPCNT__"); 3379 3380 if (HasRTM) 3381 Builder.defineMacro("__RTM__"); 3382 3383 if (HasPRFCHW) 3384 Builder.defineMacro("__PRFCHW__"); 3385 3386 if (HasRDSEED) 3387 Builder.defineMacro("__RDSEED__"); 3388 3389 if (HasADX) 3390 Builder.defineMacro("__ADX__"); 3391 3392 if (HasTBM) 3393 Builder.defineMacro("__TBM__"); 3394 3395 switch (XOPLevel) { 3396 case XOP: 3397 Builder.defineMacro("__XOP__"); 3398 case FMA4: 3399 Builder.defineMacro("__FMA4__"); 3400 case SSE4A: 3401 Builder.defineMacro("__SSE4A__"); 3402 case NoXOP: 3403 break; 3404 } 3405 3406 if (HasFMA) 3407 Builder.defineMacro("__FMA__"); 3408 3409 if (HasF16C) 3410 Builder.defineMacro("__F16C__"); 3411 3412 if (HasAVX512CD) 3413 Builder.defineMacro("__AVX512CD__"); 3414 if (HasAVX512ER) 3415 Builder.defineMacro("__AVX512ER__"); 3416 if (HasAVX512PF) 3417 Builder.defineMacro("__AVX512PF__"); 3418 if (HasAVX512DQ) 3419 Builder.defineMacro("__AVX512DQ__"); 3420 if (HasAVX512BW) 3421 Builder.defineMacro("__AVX512BW__"); 3422 if (HasAVX512VL) 3423 Builder.defineMacro("__AVX512VL__"); 3424 if (HasAVX512VBMI) 3425 Builder.defineMacro("__AVX512VBMI__"); 3426 if (HasAVX512IFMA) 3427 Builder.defineMacro("__AVX512IFMA__"); 3428 3429 if (HasSHA) 3430 Builder.defineMacro("__SHA__"); 3431 3432 if (HasFXSR) 3433 Builder.defineMacro("__FXSR__"); 3434 if (HasXSAVE) 3435 Builder.defineMacro("__XSAVE__"); 3436 if (HasXSAVEOPT) 3437 Builder.defineMacro("__XSAVEOPT__"); 3438 if (HasXSAVEC) 3439 Builder.defineMacro("__XSAVEC__"); 3440 if (HasXSAVES) 3441 Builder.defineMacro("__XSAVES__"); 3442 if (HasPKU) 3443 Builder.defineMacro("__PKU__"); 3444 if (HasCX16) 3445 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3446 3447 // Each case falls through to the previous one here. 3448 switch (SSELevel) { 3449 case AVX512F: 3450 Builder.defineMacro("__AVX512F__"); 3451 case AVX2: 3452 Builder.defineMacro("__AVX2__"); 3453 case AVX: 3454 Builder.defineMacro("__AVX__"); 3455 case SSE42: 3456 Builder.defineMacro("__SSE4_2__"); 3457 case SSE41: 3458 Builder.defineMacro("__SSE4_1__"); 3459 case SSSE3: 3460 Builder.defineMacro("__SSSE3__"); 3461 case SSE3: 3462 Builder.defineMacro("__SSE3__"); 3463 case SSE2: 3464 Builder.defineMacro("__SSE2__"); 3465 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3466 case SSE1: 3467 Builder.defineMacro("__SSE__"); 3468 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3469 case NoSSE: 3470 break; 3471 } 3472 3473 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3474 switch (SSELevel) { 3475 case AVX512F: 3476 case AVX2: 3477 case AVX: 3478 case SSE42: 3479 case SSE41: 3480 case SSSE3: 3481 case SSE3: 3482 case SSE2: 3483 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3484 break; 3485 case SSE1: 3486 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3487 break; 3488 default: 3489 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3490 } 3491 } 3492 3493 // Each case falls through to the previous one here. 3494 switch (MMX3DNowLevel) { 3495 case AMD3DNowAthlon: 3496 Builder.defineMacro("__3dNOW_A__"); 3497 case AMD3DNow: 3498 Builder.defineMacro("__3dNOW__"); 3499 case MMX: 3500 Builder.defineMacro("__MMX__"); 3501 case NoMMX3DNow: 3502 break; 3503 } 3504 3505 if (CPU >= CK_i486) { 3506 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3507 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3508 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3509 } 3510 if (CPU >= CK_i586) 3511 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3512 } 3513 3514 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3515 return llvm::StringSwitch<bool>(Feature) 3516 .Case("aes", HasAES) 3517 .Case("avx", SSELevel >= AVX) 3518 .Case("avx2", SSELevel >= AVX2) 3519 .Case("avx512f", SSELevel >= AVX512F) 3520 .Case("avx512cd", HasAVX512CD) 3521 .Case("avx512er", HasAVX512ER) 3522 .Case("avx512pf", HasAVX512PF) 3523 .Case("avx512dq", HasAVX512DQ) 3524 .Case("avx512bw", HasAVX512BW) 3525 .Case("avx512vl", HasAVX512VL) 3526 .Case("avx512vbmi", HasAVX512VBMI) 3527 .Case("avx512ifma", HasAVX512IFMA) 3528 .Case("bmi", HasBMI) 3529 .Case("bmi2", HasBMI2) 3530 .Case("clflushopt", HasCLFLUSHOPT) 3531 .Case("clwb", HasCLWB) 3532 .Case("cx16", HasCX16) 3533 .Case("f16c", HasF16C) 3534 .Case("fma", HasFMA) 3535 .Case("fma4", XOPLevel >= FMA4) 3536 .Case("fsgsbase", HasFSGSBASE) 3537 .Case("fxsr", HasFXSR) 3538 .Case("lzcnt", HasLZCNT) 3539 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3540 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3541 .Case("mmx", MMX3DNowLevel >= MMX) 3542 .Case("movbe", HasMOVBE) 3543 .Case("mpx", HasMPX) 3544 .Case("pclmul", HasPCLMUL) 3545 .Case("pcommit", HasPCOMMIT) 3546 .Case("pku", HasPKU) 3547 .Case("popcnt", HasPOPCNT) 3548 .Case("prefetchwt1", HasPREFETCHWT1) 3549 .Case("prfchw", HasPRFCHW) 3550 .Case("rdrnd", HasRDRND) 3551 .Case("rdseed", HasRDSEED) 3552 .Case("rtm", HasRTM) 3553 .Case("sgx", HasSGX) 3554 .Case("sha", HasSHA) 3555 .Case("sse", SSELevel >= SSE1) 3556 .Case("sse2", SSELevel >= SSE2) 3557 .Case("sse3", SSELevel >= SSE3) 3558 .Case("ssse3", SSELevel >= SSSE3) 3559 .Case("sse4.1", SSELevel >= SSE41) 3560 .Case("sse4.2", SSELevel >= SSE42) 3561 .Case("sse4a", XOPLevel >= SSE4A) 3562 .Case("tbm", HasTBM) 3563 .Case("umip", HasUMIP) 3564 .Case("x86", true) 3565 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3566 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3567 .Case("xop", XOPLevel >= XOP) 3568 .Case("xsave", HasXSAVE) 3569 .Case("xsavec", HasXSAVEC) 3570 .Case("xsaves", HasXSAVES) 3571 .Case("xsaveopt", HasXSAVEOPT) 3572 .Default(false); 3573 } 3574 3575 // We can't use a generic validation scheme for the features accepted here 3576 // versus subtarget features accepted in the target attribute because the 3577 // bitfield structure that's initialized in the runtime only supports the 3578 // below currently rather than the full range of subtarget features. (See 3579 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3580 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3581 return llvm::StringSwitch<bool>(FeatureStr) 3582 .Case("cmov", true) 3583 .Case("mmx", true) 3584 .Case("popcnt", true) 3585 .Case("sse", true) 3586 .Case("sse2", true) 3587 .Case("sse3", true) 3588 .Case("sse4.1", true) 3589 .Case("sse4.2", true) 3590 .Case("avx", true) 3591 .Case("avx2", true) 3592 .Case("sse4a", true) 3593 .Case("fma4", true) 3594 .Case("xop", true) 3595 .Case("fma", true) 3596 .Case("avx512f", true) 3597 .Case("bmi", true) 3598 .Case("bmi2", true) 3599 .Default(false); 3600 } 3601 3602 bool 3603 X86TargetInfo::validateAsmConstraint(const char *&Name, 3604 TargetInfo::ConstraintInfo &Info) const { 3605 switch (*Name) { 3606 default: return false; 3607 // Constant constraints. 3608 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3609 // instructions. 3610 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3611 // x86_64 instructions. 3612 case 's': 3613 Info.setRequiresImmediate(); 3614 return true; 3615 case 'I': 3616 Info.setRequiresImmediate(0, 31); 3617 return true; 3618 case 'J': 3619 Info.setRequiresImmediate(0, 63); 3620 return true; 3621 case 'K': 3622 Info.setRequiresImmediate(-128, 127); 3623 return true; 3624 case 'L': 3625 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3626 return true; 3627 case 'M': 3628 Info.setRequiresImmediate(0, 3); 3629 return true; 3630 case 'N': 3631 Info.setRequiresImmediate(0, 255); 3632 return true; 3633 case 'O': 3634 Info.setRequiresImmediate(0, 127); 3635 return true; 3636 // Register constraints. 3637 case 'Y': // 'Y' is the first character for several 2-character constraints. 3638 // Shift the pointer to the second character of the constraint. 3639 Name++; 3640 switch (*Name) { 3641 default: 3642 return false; 3643 case '0': // First SSE register. 3644 case 't': // Any SSE register, when SSE2 is enabled. 3645 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3646 case 'm': // Any MMX register, when inter-unit moves enabled. 3647 Info.setAllowsRegister(); 3648 return true; 3649 } 3650 case 'f': // Any x87 floating point stack register. 3651 // Constraint 'f' cannot be used for output operands. 3652 if (Info.ConstraintStr[0] == '=') 3653 return false; 3654 Info.setAllowsRegister(); 3655 return true; 3656 case 'a': // eax. 3657 case 'b': // ebx. 3658 case 'c': // ecx. 3659 case 'd': // edx. 3660 case 'S': // esi. 3661 case 'D': // edi. 3662 case 'A': // edx:eax. 3663 case 't': // Top of floating point stack. 3664 case 'u': // Second from top of floating point stack. 3665 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3666 case 'y': // Any MMX register. 3667 case 'x': // Any SSE register. 3668 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3669 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3670 case 'l': // "Index" registers: any general register that can be used as an 3671 // index in a base+index memory access. 3672 Info.setAllowsRegister(); 3673 return true; 3674 // Floating point constant constraints. 3675 case 'C': // SSE floating point constant. 3676 case 'G': // x87 floating point constant. 3677 return true; 3678 } 3679 } 3680 3681 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3682 unsigned Size) const { 3683 // Strip off constraint modifiers. 3684 while (Constraint[0] == '=' || 3685 Constraint[0] == '+' || 3686 Constraint[0] == '&') 3687 Constraint = Constraint.substr(1); 3688 3689 return validateOperandSize(Constraint, Size); 3690 } 3691 3692 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3693 unsigned Size) const { 3694 return validateOperandSize(Constraint, Size); 3695 } 3696 3697 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3698 unsigned Size) const { 3699 switch (Constraint[0]) { 3700 default: break; 3701 case 'y': 3702 return Size <= 64; 3703 case 'f': 3704 case 't': 3705 case 'u': 3706 return Size <= 128; 3707 case 'x': 3708 if (SSELevel >= AVX512F) 3709 // 512-bit zmm registers can be used if target supports AVX512F. 3710 return Size <= 512U; 3711 else if (SSELevel >= AVX) 3712 // 256-bit ymm registers can be used if target supports AVX. 3713 return Size <= 256U; 3714 return Size <= 128U; 3715 case 'Y': 3716 // 'Y' is the first character for several 2-character constraints. 3717 switch (Constraint[1]) { 3718 default: break; 3719 case 'm': 3720 // 'Ym' is synonymous with 'y'. 3721 return Size <= 64; 3722 case 'i': 3723 case 't': 3724 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3725 if (SSELevel >= AVX512F) 3726 return Size <= 512U; 3727 else if (SSELevel >= AVX) 3728 return Size <= 256U; 3729 return SSELevel >= SSE2 && Size <= 128U; 3730 } 3731 3732 } 3733 3734 return true; 3735 } 3736 3737 std::string 3738 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3739 switch (*Constraint) { 3740 case 'a': return std::string("{ax}"); 3741 case 'b': return std::string("{bx}"); 3742 case 'c': return std::string("{cx}"); 3743 case 'd': return std::string("{dx}"); 3744 case 'S': return std::string("{si}"); 3745 case 'D': return std::string("{di}"); 3746 case 'p': // address 3747 return std::string("im"); 3748 case 't': // top of floating point stack. 3749 return std::string("{st}"); 3750 case 'u': // second from top of floating point stack. 3751 return std::string("{st(1)}"); // second from top of floating point stack. 3752 default: 3753 return std::string(1, *Constraint); 3754 } 3755 } 3756 3757 // X86-32 generic target 3758 class X86_32TargetInfo : public X86TargetInfo { 3759 public: 3760 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3761 : X86TargetInfo(Triple, Opts) { 3762 DoubleAlign = LongLongAlign = 32; 3763 LongDoubleWidth = 96; 3764 LongDoubleAlign = 32; 3765 SuitableAlign = 128; 3766 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 3767 SizeType = UnsignedInt; 3768 PtrDiffType = SignedInt; 3769 IntPtrType = SignedInt; 3770 RegParmMax = 3; 3771 3772 // Use fpret for all types. 3773 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3774 (1 << TargetInfo::Double) | 3775 (1 << TargetInfo::LongDouble)); 3776 3777 // x86-32 has atomics up to 8 bytes 3778 // FIXME: Check that we actually have cmpxchg8b before setting 3779 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3780 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3781 } 3782 BuiltinVaListKind getBuiltinVaListKind() const override { 3783 return TargetInfo::CharPtrBuiltinVaList; 3784 } 3785 3786 int getEHDataRegisterNumber(unsigned RegNo) const override { 3787 if (RegNo == 0) return 0; 3788 if (RegNo == 1) return 2; 3789 return -1; 3790 } 3791 bool validateOperandSize(StringRef Constraint, 3792 unsigned Size) const override { 3793 switch (Constraint[0]) { 3794 default: break; 3795 case 'R': 3796 case 'q': 3797 case 'Q': 3798 case 'a': 3799 case 'b': 3800 case 'c': 3801 case 'd': 3802 case 'S': 3803 case 'D': 3804 return Size <= 32; 3805 case 'A': 3806 return Size <= 64; 3807 } 3808 3809 return X86TargetInfo::validateOperandSize(Constraint, Size); 3810 } 3811 }; 3812 3813 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3814 public: 3815 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3816 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 3817 3818 unsigned getFloatEvalMethod() const override { 3819 unsigned Major, Minor, Micro; 3820 getTriple().getOSVersion(Major, Minor, Micro); 3821 // New NetBSD uses the default rounding mode. 3822 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3823 return X86_32TargetInfo::getFloatEvalMethod(); 3824 // NetBSD before 6.99.26 defaults to "double" rounding. 3825 return 1; 3826 } 3827 }; 3828 3829 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3830 public: 3831 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3832 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 3833 SizeType = UnsignedLong; 3834 IntPtrType = SignedLong; 3835 PtrDiffType = SignedLong; 3836 } 3837 }; 3838 3839 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3840 public: 3841 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3842 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 3843 SizeType = UnsignedLong; 3844 IntPtrType = SignedLong; 3845 PtrDiffType = SignedLong; 3846 } 3847 }; 3848 3849 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3850 public: 3851 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3852 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 3853 LongDoubleWidth = 128; 3854 LongDoubleAlign = 128; 3855 SuitableAlign = 128; 3856 MaxVectorAlign = 256; 3857 // The watchOS simulator uses the builtin bool type for Objective-C. 3858 llvm::Triple T = llvm::Triple(Triple); 3859 if (T.isWatchOS()) 3860 UseSignedCharForObjCBool = false; 3861 SizeType = UnsignedLong; 3862 IntPtrType = SignedLong; 3863 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 3864 HasAlignMac68kSupport = true; 3865 } 3866 3867 bool handleTargetFeatures(std::vector<std::string> &Features, 3868 DiagnosticsEngine &Diags) override { 3869 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3870 Diags)) 3871 return false; 3872 // We now know the features we have: we can decide how to align vectors. 3873 MaxVectorAlign = 3874 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3875 return true; 3876 } 3877 }; 3878 3879 // x86-32 Windows target 3880 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3881 public: 3882 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3883 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 3884 WCharType = UnsignedShort; 3885 DoubleAlign = LongLongAlign = 64; 3886 bool IsWinCOFF = 3887 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3888 resetDataLayout(IsWinCOFF 3889 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3890 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 3891 } 3892 void getTargetDefines(const LangOptions &Opts, 3893 MacroBuilder &Builder) const override { 3894 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3895 } 3896 }; 3897 3898 // x86-32 Windows Visual Studio target 3899 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3900 public: 3901 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 3902 const TargetOptions &Opts) 3903 : WindowsX86_32TargetInfo(Triple, Opts) { 3904 LongDoubleWidth = LongDoubleAlign = 64; 3905 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3906 } 3907 void getTargetDefines(const LangOptions &Opts, 3908 MacroBuilder &Builder) const override { 3909 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3910 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3911 // The value of the following reflects processor type. 3912 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3913 // We lost the original triple, so we use the default. 3914 Builder.defineMacro("_M_IX86", "600"); 3915 } 3916 }; 3917 3918 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3919 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3920 // supports __declspec natively under -fms-extensions, but we define a no-op 3921 // __declspec macro anyway for pre-processor compatibility. 3922 if (Opts.MicrosoftExt) 3923 Builder.defineMacro("__declspec", "__declspec"); 3924 else 3925 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3926 3927 if (!Opts.MicrosoftExt) { 3928 // Provide macros for all the calling convention keywords. Provide both 3929 // single and double underscore prefixed variants. These are available on 3930 // x64 as well as x86, even though they have no effect. 3931 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3932 for (const char *CC : CCs) { 3933 std::string GCCSpelling = "__attribute__((__"; 3934 GCCSpelling += CC; 3935 GCCSpelling += "__))"; 3936 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3937 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3938 } 3939 } 3940 } 3941 3942 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3943 Builder.defineMacro("__MSVCRT__"); 3944 Builder.defineMacro("__MINGW32__"); 3945 addCygMingDefines(Opts, Builder); 3946 } 3947 3948 // x86-32 MinGW target 3949 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3950 public: 3951 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3952 : WindowsX86_32TargetInfo(Triple, Opts) {} 3953 void getTargetDefines(const LangOptions &Opts, 3954 MacroBuilder &Builder) const override { 3955 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3956 DefineStd(Builder, "WIN32", Opts); 3957 DefineStd(Builder, "WINNT", Opts); 3958 Builder.defineMacro("_X86_"); 3959 addMinGWDefines(Opts, Builder); 3960 } 3961 }; 3962 3963 // x86-32 Cygwin target 3964 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3965 public: 3966 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3967 : X86_32TargetInfo(Triple, Opts) { 3968 WCharType = UnsignedShort; 3969 DoubleAlign = LongLongAlign = 64; 3970 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 3971 } 3972 void getTargetDefines(const LangOptions &Opts, 3973 MacroBuilder &Builder) const override { 3974 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3975 Builder.defineMacro("_X86_"); 3976 Builder.defineMacro("__CYGWIN__"); 3977 Builder.defineMacro("__CYGWIN32__"); 3978 addCygMingDefines(Opts, Builder); 3979 DefineStd(Builder, "unix", Opts); 3980 if (Opts.CPlusPlus) 3981 Builder.defineMacro("_GNU_SOURCE"); 3982 } 3983 }; 3984 3985 // x86-32 Haiku target 3986 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3987 public: 3988 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3989 : X86_32TargetInfo(Triple, Opts) { 3990 SizeType = UnsignedLong; 3991 IntPtrType = SignedLong; 3992 PtrDiffType = SignedLong; 3993 ProcessIDType = SignedLong; 3994 this->TLSSupported = false; 3995 } 3996 void getTargetDefines(const LangOptions &Opts, 3997 MacroBuilder &Builder) const override { 3998 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3999 Builder.defineMacro("__INTEL__"); 4000 Builder.defineMacro("__HAIKU__"); 4001 } 4002 }; 4003 4004 // X86-32 MCU target 4005 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4006 public: 4007 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4008 : X86_32TargetInfo(Triple, Opts) { 4009 LongDoubleWidth = 64; 4010 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4011 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4012 WIntType = UnsignedInt; 4013 } 4014 4015 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4016 // On MCU we support only C calling convention. 4017 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4018 } 4019 4020 void getTargetDefines(const LangOptions &Opts, 4021 MacroBuilder &Builder) const override { 4022 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4023 Builder.defineMacro("__iamcu"); 4024 Builder.defineMacro("__iamcu__"); 4025 } 4026 4027 bool allowsLargerPreferedTypeAlignment() const override { 4028 return false; 4029 } 4030 }; 4031 4032 // RTEMS Target 4033 template<typename Target> 4034 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4035 protected: 4036 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4037 MacroBuilder &Builder) const override { 4038 // RTEMS defines; list based off of gcc output 4039 4040 Builder.defineMacro("__rtems__"); 4041 Builder.defineMacro("__ELF__"); 4042 } 4043 4044 public: 4045 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4046 : OSTargetInfo<Target>(Triple, Opts) { 4047 switch (Triple.getArch()) { 4048 default: 4049 case llvm::Triple::x86: 4050 // this->MCountName = ".mcount"; 4051 break; 4052 case llvm::Triple::mips: 4053 case llvm::Triple::mipsel: 4054 case llvm::Triple::ppc: 4055 case llvm::Triple::ppc64: 4056 case llvm::Triple::ppc64le: 4057 // this->MCountName = "_mcount"; 4058 break; 4059 case llvm::Triple::arm: 4060 // this->MCountName = "__mcount"; 4061 break; 4062 } 4063 } 4064 }; 4065 4066 // x86-32 RTEMS target 4067 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4068 public: 4069 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4070 : X86_32TargetInfo(Triple, Opts) { 4071 SizeType = UnsignedLong; 4072 IntPtrType = SignedLong; 4073 PtrDiffType = SignedLong; 4074 } 4075 void getTargetDefines(const LangOptions &Opts, 4076 MacroBuilder &Builder) const override { 4077 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4078 Builder.defineMacro("__INTEL__"); 4079 Builder.defineMacro("__rtems__"); 4080 } 4081 }; 4082 4083 // x86-64 generic target 4084 class X86_64TargetInfo : public X86TargetInfo { 4085 public: 4086 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4087 : X86TargetInfo(Triple, Opts) { 4088 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4089 bool IsWinCOFF = 4090 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4091 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4092 LongDoubleWidth = 128; 4093 LongDoubleAlign = 128; 4094 LargeArrayMinWidth = 128; 4095 LargeArrayAlign = 128; 4096 SuitableAlign = 128; 4097 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4098 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4099 IntPtrType = IsX32 ? SignedInt : SignedLong; 4100 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4101 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4102 RegParmMax = 6; 4103 4104 // Pointers are 32-bit in x32. 4105 resetDataLayout(IsX32 4106 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4107 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4108 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4109 4110 // Use fpret only for long double. 4111 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4112 4113 // Use fp2ret for _Complex long double. 4114 ComplexLongDoubleUsesFP2Ret = true; 4115 4116 // Make __builtin_ms_va_list available. 4117 HasBuiltinMSVaList = true; 4118 4119 // x86-64 has atomics up to 16 bytes. 4120 MaxAtomicPromoteWidth = 128; 4121 MaxAtomicInlineWidth = 128; 4122 } 4123 BuiltinVaListKind getBuiltinVaListKind() const override { 4124 return TargetInfo::X86_64ABIBuiltinVaList; 4125 } 4126 4127 int getEHDataRegisterNumber(unsigned RegNo) const override { 4128 if (RegNo == 0) return 0; 4129 if (RegNo == 1) return 1; 4130 return -1; 4131 } 4132 4133 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4134 switch (CC) { 4135 case CC_C: 4136 case CC_Swift: 4137 case CC_X86VectorCall: 4138 case CC_IntelOclBicc: 4139 case CC_X86_64Win64: 4140 case CC_PreserveMost: 4141 case CC_PreserveAll: 4142 return CCCR_OK; 4143 default: 4144 return CCCR_Warning; 4145 } 4146 } 4147 4148 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4149 return CC_C; 4150 } 4151 4152 // for x32 we need it here explicitly 4153 bool hasInt128Type() const override { return true; } 4154 unsigned getUnwindWordWidth() const override { return 64; } 4155 unsigned getRegisterWidth() const override { return 64; } 4156 4157 bool validateGlobalRegisterVariable(StringRef RegName, 4158 unsigned RegSize, 4159 bool &HasSizeMismatch) const override { 4160 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4161 // handle. 4162 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4163 // Check that the register size is 64-bit. 4164 HasSizeMismatch = RegSize != 64; 4165 return true; 4166 } 4167 4168 // Check if the register is a 32-bit register the backend can handle. 4169 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4170 HasSizeMismatch); 4171 } 4172 }; 4173 4174 // x86-64 Windows target 4175 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4176 public: 4177 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4178 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4179 WCharType = UnsignedShort; 4180 LongWidth = LongAlign = 32; 4181 DoubleAlign = LongLongAlign = 64; 4182 IntMaxType = SignedLongLong; 4183 Int64Type = SignedLongLong; 4184 SizeType = UnsignedLongLong; 4185 PtrDiffType = SignedLongLong; 4186 IntPtrType = SignedLongLong; 4187 } 4188 4189 void getTargetDefines(const LangOptions &Opts, 4190 MacroBuilder &Builder) const override { 4191 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4192 Builder.defineMacro("_WIN64"); 4193 } 4194 4195 BuiltinVaListKind getBuiltinVaListKind() const override { 4196 return TargetInfo::CharPtrBuiltinVaList; 4197 } 4198 4199 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4200 switch (CC) { 4201 case CC_X86StdCall: 4202 case CC_X86ThisCall: 4203 case CC_X86FastCall: 4204 return CCCR_Ignore; 4205 case CC_C: 4206 case CC_X86VectorCall: 4207 case CC_IntelOclBicc: 4208 case CC_X86_64SysV: 4209 return CCCR_OK; 4210 default: 4211 return CCCR_Warning; 4212 } 4213 } 4214 }; 4215 4216 // x86-64 Windows Visual Studio target 4217 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4218 public: 4219 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4220 const TargetOptions &Opts) 4221 : WindowsX86_64TargetInfo(Triple, Opts) { 4222 LongDoubleWidth = LongDoubleAlign = 64; 4223 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4224 } 4225 void getTargetDefines(const LangOptions &Opts, 4226 MacroBuilder &Builder) const override { 4227 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4228 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4229 Builder.defineMacro("_M_X64", "100"); 4230 Builder.defineMacro("_M_AMD64", "100"); 4231 } 4232 }; 4233 4234 // x86-64 MinGW target 4235 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4236 public: 4237 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4238 : WindowsX86_64TargetInfo(Triple, Opts) { 4239 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4240 // with x86 FP ops. Weird. 4241 LongDoubleWidth = LongDoubleAlign = 128; 4242 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4243 } 4244 4245 void getTargetDefines(const LangOptions &Opts, 4246 MacroBuilder &Builder) const override { 4247 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4248 DefineStd(Builder, "WIN64", Opts); 4249 Builder.defineMacro("__MINGW64__"); 4250 addMinGWDefines(Opts, Builder); 4251 4252 // GCC defines this macro when it is using __gxx_personality_seh0. 4253 if (!Opts.SjLjExceptions) 4254 Builder.defineMacro("__SEH__"); 4255 } 4256 }; 4257 4258 // x86-64 Cygwin target 4259 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4260 public: 4261 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4262 : X86_64TargetInfo(Triple, Opts) { 4263 TLSSupported = false; 4264 WCharType = UnsignedShort; 4265 } 4266 void getTargetDefines(const LangOptions &Opts, 4267 MacroBuilder &Builder) const override { 4268 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4269 Builder.defineMacro("__x86_64__"); 4270 Builder.defineMacro("__CYGWIN__"); 4271 Builder.defineMacro("__CYGWIN64__"); 4272 addCygMingDefines(Opts, Builder); 4273 DefineStd(Builder, "unix", Opts); 4274 if (Opts.CPlusPlus) 4275 Builder.defineMacro("_GNU_SOURCE"); 4276 4277 // GCC defines this macro when it is using __gxx_personality_seh0. 4278 if (!Opts.SjLjExceptions) 4279 Builder.defineMacro("__SEH__"); 4280 } 4281 }; 4282 4283 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4284 public: 4285 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4286 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4287 Int64Type = SignedLongLong; 4288 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4289 llvm::Triple T = llvm::Triple(Triple); 4290 if (T.isiOS()) 4291 UseSignedCharForObjCBool = false; 4292 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4293 } 4294 4295 bool handleTargetFeatures(std::vector<std::string> &Features, 4296 DiagnosticsEngine &Diags) override { 4297 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4298 Diags)) 4299 return false; 4300 // We now know the features we have: we can decide how to align vectors. 4301 MaxVectorAlign = 4302 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4303 return true; 4304 } 4305 }; 4306 4307 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4308 public: 4309 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4310 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4311 IntMaxType = SignedLongLong; 4312 Int64Type = SignedLongLong; 4313 } 4314 }; 4315 4316 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4317 public: 4318 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4319 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4320 IntMaxType = SignedLongLong; 4321 Int64Type = SignedLongLong; 4322 } 4323 }; 4324 4325 class ARMTargetInfo : public TargetInfo { 4326 // Possible FPU choices. 4327 enum FPUMode { 4328 VFP2FPU = (1 << 0), 4329 VFP3FPU = (1 << 1), 4330 VFP4FPU = (1 << 2), 4331 NeonFPU = (1 << 3), 4332 FPARMV8 = (1 << 4) 4333 }; 4334 4335 // Possible HWDiv features. 4336 enum HWDivMode { 4337 HWDivThumb = (1 << 0), 4338 HWDivARM = (1 << 1) 4339 }; 4340 4341 static bool FPUModeIsVFP(FPUMode Mode) { 4342 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4343 } 4344 4345 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4346 static const char * const GCCRegNames[]; 4347 4348 std::string ABI, CPU; 4349 4350 StringRef CPUProfile; 4351 StringRef CPUAttr; 4352 4353 enum { 4354 FP_Default, 4355 FP_VFP, 4356 FP_Neon 4357 } FPMath; 4358 4359 unsigned ArchISA; 4360 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4361 unsigned ArchProfile; 4362 unsigned ArchVersion; 4363 4364 unsigned FPU : 5; 4365 4366 unsigned IsAAPCS : 1; 4367 unsigned HWDiv : 2; 4368 4369 // Initialized via features. 4370 unsigned SoftFloat : 1; 4371 unsigned SoftFloatABI : 1; 4372 4373 unsigned CRC : 1; 4374 unsigned Crypto : 1; 4375 unsigned DSP : 1; 4376 unsigned Unaligned : 1; 4377 4378 enum { 4379 LDREX_B = (1 << 0), /// byte (8-bit) 4380 LDREX_H = (1 << 1), /// half (16-bit) 4381 LDREX_W = (1 << 2), /// word (32-bit) 4382 LDREX_D = (1 << 3), /// double (64-bit) 4383 }; 4384 4385 uint32_t LDREX; 4386 4387 // ACLE 6.5.1 Hardware floating point 4388 enum { 4389 HW_FP_HP = (1 << 1), /// half (16-bit) 4390 HW_FP_SP = (1 << 2), /// single (32-bit) 4391 HW_FP_DP = (1 << 3), /// double (64-bit) 4392 }; 4393 uint32_t HW_FP; 4394 4395 static const Builtin::Info BuiltinInfo[]; 4396 4397 void setABIAAPCS() { 4398 IsAAPCS = true; 4399 4400 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4401 const llvm::Triple &T = getTriple(); 4402 4403 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4404 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4405 T.getOS() == llvm::Triple::Bitrig) 4406 SizeType = UnsignedLong; 4407 else 4408 SizeType = UnsignedInt; 4409 4410 switch (T.getOS()) { 4411 case llvm::Triple::NetBSD: 4412 WCharType = SignedInt; 4413 break; 4414 case llvm::Triple::Win32: 4415 WCharType = UnsignedShort; 4416 break; 4417 case llvm::Triple::Linux: 4418 default: 4419 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4420 WCharType = UnsignedInt; 4421 break; 4422 } 4423 4424 UseBitFieldTypeAlignment = true; 4425 4426 ZeroLengthBitfieldBoundary = 0; 4427 4428 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4429 // so set preferred for small types to 32. 4430 if (T.isOSBinFormatMachO()) { 4431 resetDataLayout(BigEndian 4432 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4433 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4434 } else if (T.isOSWindows()) { 4435 assert(!BigEndian && "Windows on ARM does not support big endian"); 4436 resetDataLayout("e" 4437 "-m:w" 4438 "-p:32:32" 4439 "-i64:64" 4440 "-v128:64:128" 4441 "-a:0:32" 4442 "-n32" 4443 "-S64"); 4444 } else if (T.isOSNaCl()) { 4445 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4446 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4447 } else { 4448 resetDataLayout(BigEndian 4449 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4450 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4451 } 4452 4453 // FIXME: Enumerated types are variable width in straight AAPCS. 4454 } 4455 4456 void setABIAPCS(bool IsAAPCS16) { 4457 const llvm::Triple &T = getTriple(); 4458 4459 IsAAPCS = false; 4460 4461 if (IsAAPCS16) 4462 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4463 else 4464 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4465 4466 // size_t is unsigned int on FreeBSD. 4467 if (T.getOS() == llvm::Triple::FreeBSD) 4468 SizeType = UnsignedInt; 4469 else 4470 SizeType = UnsignedLong; 4471 4472 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4473 WCharType = SignedInt; 4474 4475 // Do not respect the alignment of bit-field types when laying out 4476 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4477 UseBitFieldTypeAlignment = false; 4478 4479 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4480 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4481 /// gcc. 4482 ZeroLengthBitfieldBoundary = 32; 4483 4484 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4485 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4486 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4487 } else if (T.isOSBinFormatMachO()) 4488 resetDataLayout( 4489 BigEndian 4490 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4491 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4492 else 4493 resetDataLayout( 4494 BigEndian 4495 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4496 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4497 4498 // FIXME: Override "preferred align" for double and long long. 4499 } 4500 4501 void setArchInfo() { 4502 StringRef ArchName = getTriple().getArchName(); 4503 4504 ArchISA = llvm::ARM::parseArchISA(ArchName); 4505 CPU = llvm::ARM::getDefaultCPU(ArchName); 4506 unsigned AK = llvm::ARM::parseArch(ArchName); 4507 if (AK != llvm::ARM::AK_INVALID) 4508 ArchKind = AK; 4509 setArchInfo(ArchKind); 4510 } 4511 4512 void setArchInfo(unsigned Kind) { 4513 StringRef SubArch; 4514 4515 // cache TargetParser info 4516 ArchKind = Kind; 4517 SubArch = llvm::ARM::getSubArch(ArchKind); 4518 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4519 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4520 4521 // cache CPU related strings 4522 CPUAttr = getCPUAttr(); 4523 CPUProfile = getCPUProfile(); 4524 } 4525 4526 void setAtomic() { 4527 // when triple does not specify a sub arch, 4528 // then we are not using inline atomics 4529 bool ShouldUseInlineAtomic = 4530 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4531 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4532 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4533 if (ArchProfile == llvm::ARM::PK_M) { 4534 MaxAtomicPromoteWidth = 32; 4535 if (ShouldUseInlineAtomic) 4536 MaxAtomicInlineWidth = 32; 4537 } 4538 else { 4539 MaxAtomicPromoteWidth = 64; 4540 if (ShouldUseInlineAtomic) 4541 MaxAtomicInlineWidth = 64; 4542 } 4543 } 4544 4545 bool isThumb() const { 4546 return (ArchISA == llvm::ARM::IK_THUMB); 4547 } 4548 4549 bool supportsThumb() const { 4550 return CPUAttr.count('T') || ArchVersion >= 6; 4551 } 4552 4553 bool supportsThumb2() const { 4554 return CPUAttr.equals("6T2") || 4555 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4556 } 4557 4558 StringRef getCPUAttr() const { 4559 // For most sub-arches, the build attribute CPU name is enough. 4560 // For Cortex variants, it's slightly different. 4561 switch(ArchKind) { 4562 default: 4563 return llvm::ARM::getCPUAttr(ArchKind); 4564 case llvm::ARM::AK_ARMV6M: 4565 return "6M"; 4566 case llvm::ARM::AK_ARMV7S: 4567 return "7S"; 4568 case llvm::ARM::AK_ARMV7A: 4569 return "7A"; 4570 case llvm::ARM::AK_ARMV7R: 4571 return "7R"; 4572 case llvm::ARM::AK_ARMV7M: 4573 return "7M"; 4574 case llvm::ARM::AK_ARMV7EM: 4575 return "7EM"; 4576 case llvm::ARM::AK_ARMV8A: 4577 return "8A"; 4578 case llvm::ARM::AK_ARMV8_1A: 4579 return "8_1A"; 4580 case llvm::ARM::AK_ARMV8_2A: 4581 return "8_2A"; 4582 case llvm::ARM::AK_ARMV8MBaseline: 4583 return "8M_BASE"; 4584 case llvm::ARM::AK_ARMV8MMainline: 4585 return "8M_MAIN"; 4586 } 4587 } 4588 4589 StringRef getCPUProfile() const { 4590 switch(ArchProfile) { 4591 case llvm::ARM::PK_A: 4592 return "A"; 4593 case llvm::ARM::PK_R: 4594 return "R"; 4595 case llvm::ARM::PK_M: 4596 return "M"; 4597 default: 4598 return ""; 4599 } 4600 } 4601 4602 public: 4603 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 4604 bool IsBigEndian) 4605 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4606 HW_FP(0) { 4607 BigEndian = IsBigEndian; 4608 4609 switch (getTriple().getOS()) { 4610 case llvm::Triple::NetBSD: 4611 PtrDiffType = SignedLong; 4612 break; 4613 default: 4614 PtrDiffType = SignedInt; 4615 break; 4616 } 4617 4618 // Cache arch related info. 4619 setArchInfo(); 4620 4621 // {} in inline assembly are neon specifiers, not assembly variant 4622 // specifiers. 4623 NoAsmVariants = true; 4624 4625 // FIXME: This duplicates code from the driver that sets the -target-abi 4626 // option - this code is used if -target-abi isn't passed and should 4627 // be unified in some way. 4628 if (Triple.isOSBinFormatMachO()) { 4629 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4630 // the frontend matches that. 4631 if (Triple.getEnvironment() == llvm::Triple::EABI || 4632 Triple.getOS() == llvm::Triple::UnknownOS || 4633 StringRef(CPU).startswith("cortex-m")) { 4634 setABI("aapcs"); 4635 } else if (Triple.isWatchABI()) { 4636 setABI("aapcs16"); 4637 } else { 4638 setABI("apcs-gnu"); 4639 } 4640 } else if (Triple.isOSWindows()) { 4641 // FIXME: this is invalid for WindowsCE 4642 setABI("aapcs"); 4643 } else { 4644 // Select the default based on the platform. 4645 switch (Triple.getEnvironment()) { 4646 case llvm::Triple::Android: 4647 case llvm::Triple::GNUEABI: 4648 case llvm::Triple::GNUEABIHF: 4649 setABI("aapcs-linux"); 4650 break; 4651 case llvm::Triple::EABIHF: 4652 case llvm::Triple::EABI: 4653 setABI("aapcs"); 4654 break; 4655 case llvm::Triple::GNU: 4656 setABI("apcs-gnu"); 4657 break; 4658 default: 4659 if (Triple.getOS() == llvm::Triple::NetBSD) 4660 setABI("apcs-gnu"); 4661 else 4662 setABI("aapcs"); 4663 break; 4664 } 4665 } 4666 4667 // ARM targets default to using the ARM C++ ABI. 4668 TheCXXABI.set(TargetCXXABI::GenericARM); 4669 4670 // ARM has atomics up to 8 bytes 4671 setAtomic(); 4672 4673 // Do force alignment of members that follow zero length bitfields. If 4674 // the alignment of the zero-length bitfield is greater than the member 4675 // that follows it, `bar', `bar' will be aligned as the type of the 4676 // zero length bitfield. 4677 UseZeroLengthBitfieldAlignment = true; 4678 4679 if (Triple.getOS() == llvm::Triple::Linux || 4680 Triple.getOS() == llvm::Triple::UnknownOS) 4681 this->MCountName = 4682 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 4683 } 4684 4685 StringRef getABI() const override { return ABI; } 4686 4687 bool setABI(const std::string &Name) override { 4688 ABI = Name; 4689 4690 // The defaults (above) are for AAPCS, check if we need to change them. 4691 // 4692 // FIXME: We need support for -meabi... we could just mangle it into the 4693 // name. 4694 if (Name == "apcs-gnu" || Name == "aapcs16") { 4695 setABIAPCS(Name == "aapcs16"); 4696 return true; 4697 } 4698 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4699 setABIAAPCS(); 4700 return true; 4701 } 4702 return false; 4703 } 4704 4705 // FIXME: This should be based on Arch attributes, not CPU names. 4706 bool 4707 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4708 StringRef CPU, 4709 const std::vector<std::string> &FeaturesVec) const override { 4710 4711 std::vector<const char*> TargetFeatures; 4712 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4713 4714 // get default FPU features 4715 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4716 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4717 4718 // get default Extension features 4719 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4720 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4721 4722 for (const char *Feature : TargetFeatures) 4723 if (Feature[0] == '+') 4724 Features[Feature+1] = true; 4725 4726 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4727 } 4728 4729 bool handleTargetFeatures(std::vector<std::string> &Features, 4730 DiagnosticsEngine &Diags) override { 4731 FPU = 0; 4732 CRC = 0; 4733 Crypto = 0; 4734 DSP = 0; 4735 Unaligned = 1; 4736 SoftFloat = SoftFloatABI = false; 4737 HWDiv = 0; 4738 4739 // This does not diagnose illegal cases like having both 4740 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4741 uint32_t HW_FP_remove = 0; 4742 for (const auto &Feature : Features) { 4743 if (Feature == "+soft-float") { 4744 SoftFloat = true; 4745 } else if (Feature == "+soft-float-abi") { 4746 SoftFloatABI = true; 4747 } else if (Feature == "+vfp2") { 4748 FPU |= VFP2FPU; 4749 HW_FP |= HW_FP_SP | HW_FP_DP; 4750 } else if (Feature == "+vfp3") { 4751 FPU |= VFP3FPU; 4752 HW_FP |= HW_FP_SP | HW_FP_DP; 4753 } else if (Feature == "+vfp4") { 4754 FPU |= VFP4FPU; 4755 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4756 } else if (Feature == "+fp-armv8") { 4757 FPU |= FPARMV8; 4758 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4759 } else if (Feature == "+neon") { 4760 FPU |= NeonFPU; 4761 HW_FP |= HW_FP_SP | HW_FP_DP; 4762 } else if (Feature == "+hwdiv") { 4763 HWDiv |= HWDivThumb; 4764 } else if (Feature == "+hwdiv-arm") { 4765 HWDiv |= HWDivARM; 4766 } else if (Feature == "+crc") { 4767 CRC = 1; 4768 } else if (Feature == "+crypto") { 4769 Crypto = 1; 4770 } else if (Feature == "+dsp") { 4771 DSP = 1; 4772 } else if (Feature == "+fp-only-sp") { 4773 HW_FP_remove |= HW_FP_DP; 4774 } else if (Feature == "+strict-align") { 4775 Unaligned = 0; 4776 } else if (Feature == "+fp16") { 4777 HW_FP |= HW_FP_HP; 4778 } 4779 } 4780 HW_FP &= ~HW_FP_remove; 4781 4782 switch (ArchVersion) { 4783 case 6: 4784 if (ArchProfile == llvm::ARM::PK_M) 4785 LDREX = 0; 4786 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4787 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4788 else 4789 LDREX = LDREX_W; 4790 break; 4791 case 7: 4792 if (ArchProfile == llvm::ARM::PK_M) 4793 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4794 else 4795 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4796 break; 4797 case 8: 4798 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4799 } 4800 4801 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4802 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4803 return false; 4804 } 4805 4806 if (FPMath == FP_Neon) 4807 Features.push_back("+neonfp"); 4808 else if (FPMath == FP_VFP) 4809 Features.push_back("-neonfp"); 4810 4811 // Remove front-end specific options which the backend handles differently. 4812 auto Feature = 4813 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4814 if (Feature != Features.end()) 4815 Features.erase(Feature); 4816 4817 return true; 4818 } 4819 4820 bool hasFeature(StringRef Feature) const override { 4821 return llvm::StringSwitch<bool>(Feature) 4822 .Case("arm", true) 4823 .Case("aarch32", true) 4824 .Case("softfloat", SoftFloat) 4825 .Case("thumb", isThumb()) 4826 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4827 .Case("hwdiv", HWDiv & HWDivThumb) 4828 .Case("hwdiv-arm", HWDiv & HWDivARM) 4829 .Default(false); 4830 } 4831 4832 bool setCPU(const std::string &Name) override { 4833 if (Name != "generic") 4834 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4835 4836 if (ArchKind == llvm::ARM::AK_INVALID) 4837 return false; 4838 setAtomic(); 4839 CPU = Name; 4840 return true; 4841 } 4842 4843 bool setFPMath(StringRef Name) override; 4844 4845 void getTargetDefines(const LangOptions &Opts, 4846 MacroBuilder &Builder) const override { 4847 // Target identification. 4848 Builder.defineMacro("__arm"); 4849 Builder.defineMacro("__arm__"); 4850 4851 // Target properties. 4852 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4853 4854 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4855 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 4856 if (getTriple().isWatchABI()) 4857 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 4858 4859 if (!CPUAttr.empty()) 4860 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4861 4862 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4863 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4864 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 4865 4866 if (ArchVersion >= 8) { 4867 // ACLE 6.5.7 Crypto Extension 4868 if (Crypto) 4869 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4870 // ACLE 6.5.8 CRC32 Extension 4871 if (CRC) 4872 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4873 // ACLE 6.5.10 Numeric Maximum and Minimum 4874 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4875 // ACLE 6.5.9 Directed Rounding 4876 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4877 } 4878 4879 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4880 // is not defined for the M-profile. 4881 // NOTE that the default profile is assumed to be 'A' 4882 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 4883 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4884 4885 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 4886 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 4887 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 4888 // v7 and v8 architectures excluding v8-M Baseline. 4889 if (supportsThumb2()) 4890 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4891 else if (supportsThumb()) 4892 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4893 4894 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4895 // instruction set such as ARM or Thumb. 4896 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4897 4898 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4899 4900 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4901 if (!CPUProfile.empty()) 4902 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4903 4904 // ACLE 6.4.3 Unaligned access supported in hardware 4905 if (Unaligned) 4906 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4907 4908 // ACLE 6.4.4 LDREX/STREX 4909 if (LDREX) 4910 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4911 4912 // ACLE 6.4.5 CLZ 4913 if (ArchVersion == 5 || 4914 (ArchVersion == 6 && CPUProfile != "M") || 4915 ArchVersion > 6) 4916 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4917 4918 // ACLE 6.5.1 Hardware Floating Point 4919 if (HW_FP) 4920 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4921 4922 // ACLE predefines. 4923 Builder.defineMacro("__ARM_ACLE", "200"); 4924 4925 // FP16 support (we currently only support IEEE format). 4926 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4927 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4928 4929 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4930 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4931 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4932 4933 // Subtarget options. 4934 4935 // FIXME: It's more complicated than this and we don't really support 4936 // interworking. 4937 // Windows on ARM does not "support" interworking 4938 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4939 Builder.defineMacro("__THUMB_INTERWORK__"); 4940 4941 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4942 // Embedded targets on Darwin follow AAPCS, but not EABI. 4943 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4944 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4945 Builder.defineMacro("__ARM_EABI__"); 4946 Builder.defineMacro("__ARM_PCS", "1"); 4947 4948 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4949 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4950 } 4951 4952 if (SoftFloat) 4953 Builder.defineMacro("__SOFTFP__"); 4954 4955 if (CPU == "xscale") 4956 Builder.defineMacro("__XSCALE__"); 4957 4958 if (isThumb()) { 4959 Builder.defineMacro("__THUMBEL__"); 4960 Builder.defineMacro("__thumb__"); 4961 if (supportsThumb2()) 4962 Builder.defineMacro("__thumb2__"); 4963 } 4964 4965 // ACLE 6.4.9 32-bit SIMD instructions 4966 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4967 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4968 4969 // ACLE 6.4.10 Hardware Integer Divide 4970 if (((HWDiv & HWDivThumb) && isThumb()) || 4971 ((HWDiv & HWDivARM) && !isThumb())) { 4972 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4973 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4974 } 4975 4976 // Note, this is always on in gcc, even though it doesn't make sense. 4977 Builder.defineMacro("__APCS_32__"); 4978 4979 if (FPUModeIsVFP((FPUMode) FPU)) { 4980 Builder.defineMacro("__VFP_FP__"); 4981 if (FPU & VFP2FPU) 4982 Builder.defineMacro("__ARM_VFPV2__"); 4983 if (FPU & VFP3FPU) 4984 Builder.defineMacro("__ARM_VFPV3__"); 4985 if (FPU & VFP4FPU) 4986 Builder.defineMacro("__ARM_VFPV4__"); 4987 } 4988 4989 // This only gets set when Neon instructions are actually available, unlike 4990 // the VFP define, hence the soft float and arch check. This is subtly 4991 // different from gcc, we follow the intent which was that it should be set 4992 // when Neon instructions are actually available. 4993 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4994 Builder.defineMacro("__ARM_NEON", "1"); 4995 Builder.defineMacro("__ARM_NEON__"); 4996 // current AArch32 NEON implementations do not support double-precision 4997 // floating-point even when it is present in VFP. 4998 Builder.defineMacro("__ARM_NEON_FP", 4999 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5000 } 5001 5002 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5003 Opts.ShortWChar ? "2" : "4"); 5004 5005 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5006 Opts.ShortEnums ? "1" : "4"); 5007 5008 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5009 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5010 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5011 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5012 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5013 } 5014 5015 // ACLE 6.4.7 DSP instructions 5016 if (DSP) { 5017 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5018 } 5019 5020 // ACLE 6.4.8 Saturation instructions 5021 bool SAT = false; 5022 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5023 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5024 SAT = true; 5025 } 5026 5027 // ACLE 6.4.6 Q (saturation) flag 5028 if (DSP || SAT) 5029 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5030 5031 if (Opts.UnsafeFPMath) 5032 Builder.defineMacro("__ARM_FP_FAST", "1"); 5033 5034 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5035 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5036 } 5037 5038 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5039 return llvm::makeArrayRef(BuiltinInfo, 5040 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5041 } 5042 bool isCLZForZeroUndef() const override { return false; } 5043 BuiltinVaListKind getBuiltinVaListKind() const override { 5044 return IsAAPCS 5045 ? AAPCSABIBuiltinVaList 5046 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5047 : TargetInfo::VoidPtrBuiltinVaList); 5048 } 5049 ArrayRef<const char *> getGCCRegNames() const override; 5050 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5051 bool validateAsmConstraint(const char *&Name, 5052 TargetInfo::ConstraintInfo &Info) const override { 5053 switch (*Name) { 5054 default: break; 5055 case 'l': // r0-r7 5056 case 'h': // r8-r15 5057 case 't': // VFP Floating point register single precision 5058 case 'w': // VFP Floating point register double precision 5059 Info.setAllowsRegister(); 5060 return true; 5061 case 'I': 5062 case 'J': 5063 case 'K': 5064 case 'L': 5065 case 'M': 5066 // FIXME 5067 return true; 5068 case 'Q': // A memory address that is a single base register. 5069 Info.setAllowsMemory(); 5070 return true; 5071 case 'U': // a memory reference... 5072 switch (Name[1]) { 5073 case 'q': // ...ARMV4 ldrsb 5074 case 'v': // ...VFP load/store (reg+constant offset) 5075 case 'y': // ...iWMMXt load/store 5076 case 't': // address valid for load/store opaque types wider 5077 // than 128-bits 5078 case 'n': // valid address for Neon doubleword vector load/store 5079 case 'm': // valid address for Neon element and structure load/store 5080 case 's': // valid address for non-offset loads/stores of quad-word 5081 // values in four ARM registers 5082 Info.setAllowsMemory(); 5083 Name++; 5084 return true; 5085 } 5086 } 5087 return false; 5088 } 5089 std::string convertConstraint(const char *&Constraint) const override { 5090 std::string R; 5091 switch (*Constraint) { 5092 case 'U': // Two-character constraint; add "^" hint for later parsing. 5093 R = std::string("^") + std::string(Constraint, 2); 5094 Constraint++; 5095 break; 5096 case 'p': // 'p' should be translated to 'r' by default. 5097 R = std::string("r"); 5098 break; 5099 default: 5100 return std::string(1, *Constraint); 5101 } 5102 return R; 5103 } 5104 bool 5105 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5106 std::string &SuggestedModifier) const override { 5107 bool isOutput = (Constraint[0] == '='); 5108 bool isInOut = (Constraint[0] == '+'); 5109 5110 // Strip off constraint modifiers. 5111 while (Constraint[0] == '=' || 5112 Constraint[0] == '+' || 5113 Constraint[0] == '&') 5114 Constraint = Constraint.substr(1); 5115 5116 switch (Constraint[0]) { 5117 default: break; 5118 case 'r': { 5119 switch (Modifier) { 5120 default: 5121 return (isInOut || isOutput || Size <= 64); 5122 case 'q': 5123 // A register of size 32 cannot fit a vector type. 5124 return false; 5125 } 5126 } 5127 } 5128 5129 return true; 5130 } 5131 const char *getClobbers() const override { 5132 // FIXME: Is this really right? 5133 return ""; 5134 } 5135 5136 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5137 switch (CC) { 5138 case CC_AAPCS: 5139 case CC_AAPCS_VFP: 5140 case CC_Swift: 5141 return CCCR_OK; 5142 default: 5143 return CCCR_Warning; 5144 } 5145 } 5146 5147 int getEHDataRegisterNumber(unsigned RegNo) const override { 5148 if (RegNo == 0) return 0; 5149 if (RegNo == 1) return 1; 5150 return -1; 5151 } 5152 5153 bool hasSjLjLowering() const override { 5154 return true; 5155 } 5156 }; 5157 5158 bool ARMTargetInfo::setFPMath(StringRef Name) { 5159 if (Name == "neon") { 5160 FPMath = FP_Neon; 5161 return true; 5162 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5163 Name == "vfp4") { 5164 FPMath = FP_VFP; 5165 return true; 5166 } 5167 return false; 5168 } 5169 5170 const char * const ARMTargetInfo::GCCRegNames[] = { 5171 // Integer registers 5172 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5173 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5174 5175 // Float registers 5176 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5177 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5178 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5179 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5180 5181 // Double registers 5182 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5183 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5184 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5185 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5186 5187 // Quad registers 5188 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5189 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5190 }; 5191 5192 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5193 return llvm::makeArrayRef(GCCRegNames); 5194 } 5195 5196 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5197 { { "a1" }, "r0" }, 5198 { { "a2" }, "r1" }, 5199 { { "a3" }, "r2" }, 5200 { { "a4" }, "r3" }, 5201 { { "v1" }, "r4" }, 5202 { { "v2" }, "r5" }, 5203 { { "v3" }, "r6" }, 5204 { { "v4" }, "r7" }, 5205 { { "v5" }, "r8" }, 5206 { { "v6", "rfp" }, "r9" }, 5207 { { "sl" }, "r10" }, 5208 { { "fp" }, "r11" }, 5209 { { "ip" }, "r12" }, 5210 { { "r13" }, "sp" }, 5211 { { "r14" }, "lr" }, 5212 { { "r15" }, "pc" }, 5213 // The S, D and Q registers overlap, but aren't really aliases; we 5214 // don't want to substitute one of these for a different-sized one. 5215 }; 5216 5217 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5218 return llvm::makeArrayRef(GCCRegAliases); 5219 } 5220 5221 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5222 #define BUILTIN(ID, TYPE, ATTRS) \ 5223 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5224 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5225 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5226 #include "clang/Basic/BuiltinsNEON.def" 5227 5228 #define BUILTIN(ID, TYPE, ATTRS) \ 5229 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5230 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5231 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5232 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5233 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5234 #include "clang/Basic/BuiltinsARM.def" 5235 }; 5236 5237 class ARMleTargetInfo : public ARMTargetInfo { 5238 public: 5239 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5240 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/false) {} 5241 void getTargetDefines(const LangOptions &Opts, 5242 MacroBuilder &Builder) const override { 5243 Builder.defineMacro("__ARMEL__"); 5244 ARMTargetInfo::getTargetDefines(Opts, Builder); 5245 } 5246 }; 5247 5248 class ARMbeTargetInfo : public ARMTargetInfo { 5249 public: 5250 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5251 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/true) {} 5252 void getTargetDefines(const LangOptions &Opts, 5253 MacroBuilder &Builder) const override { 5254 Builder.defineMacro("__ARMEB__"); 5255 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5256 ARMTargetInfo::getTargetDefines(Opts, Builder); 5257 } 5258 }; 5259 5260 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5261 const llvm::Triple Triple; 5262 public: 5263 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5264 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5265 WCharType = UnsignedShort; 5266 SizeType = UnsignedInt; 5267 } 5268 void getVisualStudioDefines(const LangOptions &Opts, 5269 MacroBuilder &Builder) const { 5270 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5271 5272 // FIXME: this is invalid for WindowsCE 5273 Builder.defineMacro("_M_ARM_NT", "1"); 5274 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5275 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5276 5277 assert((Triple.getArch() == llvm::Triple::arm || 5278 Triple.getArch() == llvm::Triple::thumb) && 5279 "invalid architecture for Windows ARM target info"); 5280 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5281 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5282 5283 // TODO map the complete set of values 5284 // 31: VFPv3 40: VFPv4 5285 Builder.defineMacro("_M_ARM_FP", "31"); 5286 } 5287 BuiltinVaListKind getBuiltinVaListKind() const override { 5288 return TargetInfo::CharPtrBuiltinVaList; 5289 } 5290 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5291 switch (CC) { 5292 case CC_X86StdCall: 5293 case CC_X86ThisCall: 5294 case CC_X86FastCall: 5295 case CC_X86VectorCall: 5296 return CCCR_Ignore; 5297 case CC_C: 5298 return CCCR_OK; 5299 default: 5300 return CCCR_Warning; 5301 } 5302 } 5303 }; 5304 5305 // Windows ARM + Itanium C++ ABI Target 5306 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5307 public: 5308 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5309 const TargetOptions &Opts) 5310 : WindowsARMTargetInfo(Triple, Opts) { 5311 TheCXXABI.set(TargetCXXABI::GenericARM); 5312 } 5313 5314 void getTargetDefines(const LangOptions &Opts, 5315 MacroBuilder &Builder) const override { 5316 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5317 5318 if (Opts.MSVCCompat) 5319 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5320 } 5321 }; 5322 5323 // Windows ARM, MS (C++) ABI 5324 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5325 public: 5326 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5327 const TargetOptions &Opts) 5328 : WindowsARMTargetInfo(Triple, Opts) { 5329 TheCXXABI.set(TargetCXXABI::Microsoft); 5330 } 5331 5332 void getTargetDefines(const LangOptions &Opts, 5333 MacroBuilder &Builder) const override { 5334 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5335 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5336 } 5337 }; 5338 5339 // ARM MinGW target 5340 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5341 public: 5342 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5343 : WindowsARMTargetInfo(Triple, Opts) { 5344 TheCXXABI.set(TargetCXXABI::GenericARM); 5345 } 5346 5347 void getTargetDefines(const LangOptions &Opts, 5348 MacroBuilder &Builder) const override { 5349 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5350 DefineStd(Builder, "WIN32", Opts); 5351 DefineStd(Builder, "WINNT", Opts); 5352 Builder.defineMacro("_ARM_"); 5353 addMinGWDefines(Opts, Builder); 5354 } 5355 }; 5356 5357 // ARM Cygwin target 5358 class CygwinARMTargetInfo : public ARMleTargetInfo { 5359 public: 5360 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5361 : ARMleTargetInfo(Triple, Opts) { 5362 TLSSupported = false; 5363 WCharType = UnsignedShort; 5364 DoubleAlign = LongLongAlign = 64; 5365 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5366 } 5367 void getTargetDefines(const LangOptions &Opts, 5368 MacroBuilder &Builder) const override { 5369 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5370 Builder.defineMacro("_ARM_"); 5371 Builder.defineMacro("__CYGWIN__"); 5372 Builder.defineMacro("__CYGWIN32__"); 5373 DefineStd(Builder, "unix", Opts); 5374 if (Opts.CPlusPlus) 5375 Builder.defineMacro("_GNU_SOURCE"); 5376 } 5377 }; 5378 5379 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5380 protected: 5381 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5382 MacroBuilder &Builder) const override { 5383 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5384 } 5385 5386 public: 5387 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5388 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5389 HasAlignMac68kSupport = true; 5390 // iOS always has 64-bit atomic instructions. 5391 // FIXME: This should be based off of the target features in 5392 // ARMleTargetInfo. 5393 MaxAtomicInlineWidth = 64; 5394 5395 if (Triple.isWatchABI()) { 5396 // Darwin on iOS uses a variant of the ARM C++ ABI. 5397 TheCXXABI.set(TargetCXXABI::WatchOS); 5398 5399 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5400 // size_t is long, it's a bit weird for it to be int. 5401 PtrDiffType = SignedLong; 5402 5403 // BOOL should be a real boolean on the new ABI 5404 UseSignedCharForObjCBool = false; 5405 } else 5406 TheCXXABI.set(TargetCXXABI::iOS); 5407 } 5408 }; 5409 5410 class AArch64TargetInfo : public TargetInfo { 5411 virtual void setDataLayout() = 0; 5412 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5413 static const char *const GCCRegNames[]; 5414 5415 enum FPUModeEnum { 5416 FPUMode, 5417 NeonMode 5418 }; 5419 5420 unsigned FPU; 5421 unsigned CRC; 5422 unsigned Crypto; 5423 unsigned Unaligned; 5424 unsigned V8_1A; 5425 5426 static const Builtin::Info BuiltinInfo[]; 5427 5428 std::string ABI; 5429 5430 public: 5431 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5432 : TargetInfo(Triple), ABI("aapcs") { 5433 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5434 WCharType = SignedInt; 5435 5436 // NetBSD apparently prefers consistency across ARM targets to consistency 5437 // across 64-bit targets. 5438 Int64Type = SignedLongLong; 5439 IntMaxType = SignedLongLong; 5440 } else { 5441 WCharType = UnsignedInt; 5442 Int64Type = SignedLong; 5443 IntMaxType = SignedLong; 5444 } 5445 5446 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5447 MaxVectorAlign = 128; 5448 MaxAtomicInlineWidth = 128; 5449 MaxAtomicPromoteWidth = 128; 5450 5451 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5452 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5453 5454 // {} in inline assembly are neon specifiers, not assembly variant 5455 // specifiers. 5456 NoAsmVariants = true; 5457 5458 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5459 // contributes to the alignment of the containing aggregate in the same way 5460 // a plain (non bit-field) member of that type would, without exception for 5461 // zero-sized or anonymous bit-fields." 5462 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5463 UseZeroLengthBitfieldAlignment = true; 5464 5465 // AArch64 targets default to using the ARM C++ ABI. 5466 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5467 5468 if (Triple.getOS() == llvm::Triple::Linux || 5469 Triple.getOS() == llvm::Triple::UnknownOS) 5470 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5471 } 5472 5473 StringRef getABI() const override { return ABI; } 5474 bool setABI(const std::string &Name) override { 5475 if (Name != "aapcs" && Name != "darwinpcs") 5476 return false; 5477 5478 ABI = Name; 5479 return true; 5480 } 5481 5482 bool setCPU(const std::string &Name) override { 5483 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5484 .Case("generic", true) 5485 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5486 "cortex-a35", "exynos-m1", true) 5487 .Case("cyclone", true) 5488 .Case("kryo", true) 5489 .Default(false); 5490 return CPUKnown; 5491 } 5492 5493 void getTargetDefines(const LangOptions &Opts, 5494 MacroBuilder &Builder) const override { 5495 // Target identification. 5496 Builder.defineMacro("__aarch64__"); 5497 5498 // Target properties. 5499 Builder.defineMacro("_LP64"); 5500 Builder.defineMacro("__LP64__"); 5501 5502 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5503 Builder.defineMacro("__ARM_ACLE", "200"); 5504 Builder.defineMacro("__ARM_ARCH", "8"); 5505 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5506 5507 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5508 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5509 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5510 5511 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5512 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5513 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5514 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5515 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5516 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5517 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5518 5519 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5520 5521 // 0xe implies support for half, single and double precision operations. 5522 Builder.defineMacro("__ARM_FP", "0xE"); 5523 5524 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5525 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5526 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5527 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5528 5529 if (Opts.UnsafeFPMath) 5530 Builder.defineMacro("__ARM_FP_FAST", "1"); 5531 5532 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5533 5534 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5535 Opts.ShortEnums ? "1" : "4"); 5536 5537 if (FPU == NeonMode) { 5538 Builder.defineMacro("__ARM_NEON", "1"); 5539 // 64-bit NEON supports half, single and double precision operations. 5540 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5541 } 5542 5543 if (CRC) 5544 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5545 5546 if (Crypto) 5547 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5548 5549 if (Unaligned) 5550 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5551 5552 if (V8_1A) 5553 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5554 5555 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5556 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5557 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5558 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5559 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5560 } 5561 5562 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5563 return llvm::makeArrayRef(BuiltinInfo, 5564 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5565 } 5566 5567 bool hasFeature(StringRef Feature) const override { 5568 return Feature == "aarch64" || 5569 Feature == "arm64" || 5570 Feature == "arm" || 5571 (Feature == "neon" && FPU == NeonMode); 5572 } 5573 5574 bool handleTargetFeatures(std::vector<std::string> &Features, 5575 DiagnosticsEngine &Diags) override { 5576 FPU = FPUMode; 5577 CRC = 0; 5578 Crypto = 0; 5579 Unaligned = 1; 5580 V8_1A = 0; 5581 5582 for (const auto &Feature : Features) { 5583 if (Feature == "+neon") 5584 FPU = NeonMode; 5585 if (Feature == "+crc") 5586 CRC = 1; 5587 if (Feature == "+crypto") 5588 Crypto = 1; 5589 if (Feature == "+strict-align") 5590 Unaligned = 0; 5591 if (Feature == "+v8.1a") 5592 V8_1A = 1; 5593 } 5594 5595 setDataLayout(); 5596 5597 return true; 5598 } 5599 5600 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5601 switch (CC) { 5602 case CC_C: 5603 case CC_Swift: 5604 case CC_PreserveMost: 5605 case CC_PreserveAll: 5606 return CCCR_OK; 5607 default: 5608 return CCCR_Warning; 5609 } 5610 } 5611 5612 bool isCLZForZeroUndef() const override { return false; } 5613 5614 BuiltinVaListKind getBuiltinVaListKind() const override { 5615 return TargetInfo::AArch64ABIBuiltinVaList; 5616 } 5617 5618 ArrayRef<const char *> getGCCRegNames() const override; 5619 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5620 5621 bool validateAsmConstraint(const char *&Name, 5622 TargetInfo::ConstraintInfo &Info) const override { 5623 switch (*Name) { 5624 default: 5625 return false; 5626 case 'w': // Floating point and SIMD registers (V0-V31) 5627 Info.setAllowsRegister(); 5628 return true; 5629 case 'I': // Constant that can be used with an ADD instruction 5630 case 'J': // Constant that can be used with a SUB instruction 5631 case 'K': // Constant that can be used with a 32-bit logical instruction 5632 case 'L': // Constant that can be used with a 64-bit logical instruction 5633 case 'M': // Constant that can be used as a 32-bit MOV immediate 5634 case 'N': // Constant that can be used as a 64-bit MOV immediate 5635 case 'Y': // Floating point constant zero 5636 case 'Z': // Integer constant zero 5637 return true; 5638 case 'Q': // A memory reference with base register and no offset 5639 Info.setAllowsMemory(); 5640 return true; 5641 case 'S': // A symbolic address 5642 Info.setAllowsRegister(); 5643 return true; 5644 case 'U': 5645 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5646 // Utf: A memory address suitable for ldp/stp in TF mode. 5647 // Usa: An absolute symbolic address. 5648 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5649 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5650 case 'z': // Zero register, wzr or xzr 5651 Info.setAllowsRegister(); 5652 return true; 5653 case 'x': // Floating point and SIMD registers (V0-V15) 5654 Info.setAllowsRegister(); 5655 return true; 5656 } 5657 return false; 5658 } 5659 5660 bool 5661 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5662 std::string &SuggestedModifier) const override { 5663 // Strip off constraint modifiers. 5664 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5665 Constraint = Constraint.substr(1); 5666 5667 switch (Constraint[0]) { 5668 default: 5669 return true; 5670 case 'z': 5671 case 'r': { 5672 switch (Modifier) { 5673 case 'x': 5674 case 'w': 5675 // For now assume that the person knows what they're 5676 // doing with the modifier. 5677 return true; 5678 default: 5679 // By default an 'r' constraint will be in the 'x' 5680 // registers. 5681 if (Size == 64) 5682 return true; 5683 5684 SuggestedModifier = "w"; 5685 return false; 5686 } 5687 } 5688 } 5689 } 5690 5691 const char *getClobbers() const override { return ""; } 5692 5693 int getEHDataRegisterNumber(unsigned RegNo) const override { 5694 if (RegNo == 0) 5695 return 0; 5696 if (RegNo == 1) 5697 return 1; 5698 return -1; 5699 } 5700 }; 5701 5702 const char *const AArch64TargetInfo::GCCRegNames[] = { 5703 // 32-bit Integer registers 5704 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5705 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5706 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5707 5708 // 64-bit Integer registers 5709 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5710 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5711 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5712 5713 // 32-bit floating point regsisters 5714 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5715 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5716 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5717 5718 // 64-bit floating point regsisters 5719 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5720 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5721 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5722 5723 // Vector registers 5724 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5725 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5726 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5727 }; 5728 5729 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5730 return llvm::makeArrayRef(GCCRegNames); 5731 } 5732 5733 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5734 { { "w31" }, "wsp" }, 5735 { { "x29" }, "fp" }, 5736 { { "x30" }, "lr" }, 5737 { { "x31" }, "sp" }, 5738 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5739 // don't want to substitute one of these for a different-sized one. 5740 }; 5741 5742 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5743 return llvm::makeArrayRef(GCCRegAliases); 5744 } 5745 5746 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5747 #define BUILTIN(ID, TYPE, ATTRS) \ 5748 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5749 #include "clang/Basic/BuiltinsNEON.def" 5750 5751 #define BUILTIN(ID, TYPE, ATTRS) \ 5752 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5753 #include "clang/Basic/BuiltinsAArch64.def" 5754 }; 5755 5756 class AArch64leTargetInfo : public AArch64TargetInfo { 5757 void setDataLayout() override { 5758 if (getTriple().isOSBinFormatMachO()) 5759 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 5760 else 5761 resetDataLayout("e-m:e-i64:64-i128:128-n32:64-S128"); 5762 } 5763 5764 public: 5765 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5766 : AArch64TargetInfo(Triple, Opts) { 5767 BigEndian = false; 5768 } 5769 void getTargetDefines(const LangOptions &Opts, 5770 MacroBuilder &Builder) const override { 5771 Builder.defineMacro("__AARCH64EL__"); 5772 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5773 } 5774 }; 5775 5776 class AArch64beTargetInfo : public AArch64TargetInfo { 5777 void setDataLayout() override { 5778 assert(!getTriple().isOSBinFormatMachO()); 5779 resetDataLayout("E-m:e-i64:64-i128:128-n32:64-S128"); 5780 } 5781 5782 public: 5783 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5784 : AArch64TargetInfo(Triple, Opts) {} 5785 void getTargetDefines(const LangOptions &Opts, 5786 MacroBuilder &Builder) const override { 5787 Builder.defineMacro("__AARCH64EB__"); 5788 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5789 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5790 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5791 } 5792 }; 5793 5794 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5795 protected: 5796 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5797 MacroBuilder &Builder) const override { 5798 Builder.defineMacro("__AARCH64_SIMD__"); 5799 Builder.defineMacro("__ARM64_ARCH_8__"); 5800 Builder.defineMacro("__ARM_NEON__"); 5801 Builder.defineMacro("__LITTLE_ENDIAN__"); 5802 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5803 Builder.defineMacro("__arm64", "1"); 5804 Builder.defineMacro("__arm64__", "1"); 5805 5806 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5807 } 5808 5809 public: 5810 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5811 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 5812 Int64Type = SignedLongLong; 5813 WCharType = SignedInt; 5814 UseSignedCharForObjCBool = false; 5815 5816 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5817 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5818 5819 TheCXXABI.set(TargetCXXABI::iOS64); 5820 } 5821 5822 BuiltinVaListKind getBuiltinVaListKind() const override { 5823 return TargetInfo::CharPtrBuiltinVaList; 5824 } 5825 }; 5826 5827 // Hexagon abstract base class 5828 class HexagonTargetInfo : public TargetInfo { 5829 static const Builtin::Info BuiltinInfo[]; 5830 static const char * const GCCRegNames[]; 5831 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5832 std::string CPU; 5833 bool HasHVX, HasHVXDouble; 5834 5835 public: 5836 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 5837 : TargetInfo(Triple) { 5838 BigEndian = false; 5839 // Specify the vector alignment explicitly. For v512x1, the calculated 5840 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 5841 // the required minimum of 64 bytes. 5842 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 5843 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 5844 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 5845 SizeType = UnsignedInt; 5846 PtrDiffType = SignedInt; 5847 IntPtrType = SignedInt; 5848 5849 // {} in inline assembly are packet specifiers, not assembly variant 5850 // specifiers. 5851 NoAsmVariants = true; 5852 5853 LargeArrayMinWidth = 64; 5854 LargeArrayAlign = 64; 5855 UseBitFieldTypeAlignment = true; 5856 ZeroLengthBitfieldBoundary = 32; 5857 HasHVX = HasHVXDouble = false; 5858 } 5859 5860 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5861 return llvm::makeArrayRef(BuiltinInfo, 5862 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5863 } 5864 5865 bool validateAsmConstraint(const char *&Name, 5866 TargetInfo::ConstraintInfo &Info) const override { 5867 return true; 5868 } 5869 5870 void getTargetDefines(const LangOptions &Opts, 5871 MacroBuilder &Builder) const override; 5872 5873 bool isCLZForZeroUndef() const override { return false; } 5874 5875 bool hasFeature(StringRef Feature) const override { 5876 return llvm::StringSwitch<bool>(Feature) 5877 .Case("hexagon", true) 5878 .Case("hvx", HasHVX) 5879 .Case("hvx-double", HasHVXDouble) 5880 .Default(false); 5881 } 5882 5883 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5884 StringRef CPU, const std::vector<std::string> &FeaturesVec) 5885 const override; 5886 5887 bool handleTargetFeatures(std::vector<std::string> &Features, 5888 DiagnosticsEngine &Diags) override; 5889 5890 BuiltinVaListKind getBuiltinVaListKind() const override { 5891 return TargetInfo::CharPtrBuiltinVaList; 5892 } 5893 ArrayRef<const char *> getGCCRegNames() const override; 5894 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5895 const char *getClobbers() const override { 5896 return ""; 5897 } 5898 5899 static const char *getHexagonCPUSuffix(StringRef Name) { 5900 return llvm::StringSwitch<const char*>(Name) 5901 .Case("hexagonv4", "4") 5902 .Case("hexagonv5", "5") 5903 .Case("hexagonv55", "55") 5904 .Case("hexagonv60", "60") 5905 .Default(nullptr); 5906 } 5907 5908 bool setCPU(const std::string &Name) override { 5909 if (!getHexagonCPUSuffix(Name)) 5910 return false; 5911 CPU = Name; 5912 return true; 5913 } 5914 5915 int getEHDataRegisterNumber(unsigned RegNo) const override { 5916 return RegNo < 2 ? RegNo : -1; 5917 } 5918 }; 5919 5920 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5921 MacroBuilder &Builder) const { 5922 Builder.defineMacro("__qdsp6__", "1"); 5923 Builder.defineMacro("__hexagon__", "1"); 5924 5925 if (CPU == "hexagonv4") { 5926 Builder.defineMacro("__HEXAGON_V4__"); 5927 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5928 if (Opts.HexagonQdsp6Compat) { 5929 Builder.defineMacro("__QDSP6_V4__"); 5930 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5931 } 5932 } else if (CPU == "hexagonv5") { 5933 Builder.defineMacro("__HEXAGON_V5__"); 5934 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5935 if(Opts.HexagonQdsp6Compat) { 5936 Builder.defineMacro("__QDSP6_V5__"); 5937 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5938 } 5939 } else if (CPU == "hexagonv60") { 5940 Builder.defineMacro("__HEXAGON_V60__"); 5941 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 5942 Builder.defineMacro("__QDSP6_V60__"); 5943 Builder.defineMacro("__QDSP6_ARCH__", "60"); 5944 } 5945 } 5946 5947 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 5948 DiagnosticsEngine &Diags) { 5949 for (auto &F : Features) { 5950 if (F == "+hvx") 5951 HasHVX = true; 5952 else if (F == "-hvx") 5953 HasHVX = HasHVXDouble = false; 5954 else if (F == "+hvx-double") 5955 HasHVX = HasHVXDouble = true; 5956 else if (F == "-hvx-double") 5957 HasHVXDouble = false; 5958 } 5959 return true; 5960 } 5961 5962 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 5963 DiagnosticsEngine &Diags, StringRef CPU, 5964 const std::vector<std::string> &FeaturesVec) const { 5965 // Default for v60: -hvx, -hvx-double. 5966 Features["hvx"] = false; 5967 Features["hvx-double"] = false; 5968 5969 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5970 } 5971 5972 5973 const char *const HexagonTargetInfo::GCCRegNames[] = { 5974 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5975 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5976 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5977 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5978 "p0", "p1", "p2", "p3", 5979 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5980 }; 5981 5982 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 5983 return llvm::makeArrayRef(GCCRegNames); 5984 } 5985 5986 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5987 { { "sp" }, "r29" }, 5988 { { "fp" }, "r30" }, 5989 { { "lr" }, "r31" }, 5990 }; 5991 5992 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 5993 return llvm::makeArrayRef(GCCRegAliases); 5994 } 5995 5996 5997 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5998 #define BUILTIN(ID, TYPE, ATTRS) \ 5999 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6000 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6001 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6002 #include "clang/Basic/BuiltinsHexagon.def" 6003 }; 6004 6005 class LanaiTargetInfo : public TargetInfo { 6006 // Class for Lanai (32-bit). 6007 // The CPU profiles supported by the Lanai backend 6008 enum CPUKind { 6009 CK_NONE, 6010 CK_V11, 6011 } CPU; 6012 6013 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6014 static const char *const GCCRegNames[]; 6015 6016 public: 6017 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6018 : TargetInfo(Triple) { 6019 // Description string has to be kept in sync with backend. 6020 resetDataLayout("E" // Big endian 6021 "-m:e" // ELF name manging 6022 "-p:32:32" // 32 bit pointers, 32 bit aligned 6023 "-i64:64" // 64 bit integers, 64 bit aligned 6024 "-a:0:32" // 32 bit alignment of objects of aggregate type 6025 "-n32" // 32 bit native integer width 6026 "-S64" // 64 bit natural stack alignment 6027 ); 6028 6029 // Setting RegParmMax equal to what mregparm was set to in the old 6030 // toolchain 6031 RegParmMax = 4; 6032 6033 // Set the default CPU to V11 6034 CPU = CK_V11; 6035 6036 // Temporary approach to make everything at least word-aligned and allow for 6037 // safely casting between pointers with different alignment requirements. 6038 // TODO: Remove this when there are no more cast align warnings on the 6039 // firmware. 6040 MinGlobalAlign = 32; 6041 } 6042 6043 void getTargetDefines(const LangOptions &Opts, 6044 MacroBuilder &Builder) const override { 6045 // Define __lanai__ when building for target lanai. 6046 Builder.defineMacro("__lanai__"); 6047 6048 // Set define for the CPU specified. 6049 switch (CPU) { 6050 case CK_V11: 6051 Builder.defineMacro("__LANAI_V11__"); 6052 break; 6053 case CK_NONE: 6054 llvm_unreachable("Unhandled target CPU"); 6055 } 6056 } 6057 6058 bool setCPU(const std::string &Name) override { 6059 CPU = llvm::StringSwitch<CPUKind>(Name) 6060 .Case("v11", CK_V11) 6061 .Default(CK_NONE); 6062 6063 return CPU != CK_NONE; 6064 } 6065 6066 bool hasFeature(StringRef Feature) const override { 6067 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6068 } 6069 6070 ArrayRef<const char *> getGCCRegNames() const override; 6071 6072 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6073 6074 BuiltinVaListKind getBuiltinVaListKind() const override { 6075 return TargetInfo::VoidPtrBuiltinVaList; 6076 } 6077 6078 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6079 6080 bool validateAsmConstraint(const char *&Name, 6081 TargetInfo::ConstraintInfo &info) const override { 6082 return false; 6083 } 6084 6085 const char *getClobbers() const override { return ""; } 6086 }; 6087 6088 const char *const LanaiTargetInfo::GCCRegNames[] = { 6089 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6090 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6091 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6092 6093 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6094 return llvm::makeArrayRef(GCCRegNames); 6095 } 6096 6097 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6098 {{"pc"}, "r2"}, 6099 {{"sp"}, "r4"}, 6100 {{"fp"}, "r5"}, 6101 {{"rv"}, "r8"}, 6102 {{"rr1"}, "r10"}, 6103 {{"rr2"}, "r11"}, 6104 {{"rca"}, "r15"}, 6105 }; 6106 6107 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6108 return llvm::makeArrayRef(GCCRegAliases); 6109 } 6110 6111 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6112 class SparcTargetInfo : public TargetInfo { 6113 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6114 static const char * const GCCRegNames[]; 6115 bool SoftFloat; 6116 public: 6117 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6118 : TargetInfo(Triple), SoftFloat(false) {} 6119 6120 int getEHDataRegisterNumber(unsigned RegNo) const override { 6121 if (RegNo == 0) return 24; 6122 if (RegNo == 1) return 25; 6123 return -1; 6124 } 6125 6126 bool handleTargetFeatures(std::vector<std::string> &Features, 6127 DiagnosticsEngine &Diags) override { 6128 // The backend doesn't actually handle soft float yet, but in case someone 6129 // is using the support for the front end continue to support it. 6130 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6131 if (Feature != Features.end()) { 6132 SoftFloat = true; 6133 Features.erase(Feature); 6134 } 6135 return true; 6136 } 6137 void getTargetDefines(const LangOptions &Opts, 6138 MacroBuilder &Builder) const override { 6139 DefineStd(Builder, "sparc", Opts); 6140 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6141 6142 if (SoftFloat) 6143 Builder.defineMacro("SOFT_FLOAT", "1"); 6144 } 6145 6146 bool hasFeature(StringRef Feature) const override { 6147 return llvm::StringSwitch<bool>(Feature) 6148 .Case("softfloat", SoftFloat) 6149 .Case("sparc", true) 6150 .Default(false); 6151 } 6152 6153 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6154 // FIXME: Implement! 6155 return None; 6156 } 6157 BuiltinVaListKind getBuiltinVaListKind() const override { 6158 return TargetInfo::VoidPtrBuiltinVaList; 6159 } 6160 ArrayRef<const char *> getGCCRegNames() const override; 6161 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6162 bool validateAsmConstraint(const char *&Name, 6163 TargetInfo::ConstraintInfo &info) const override { 6164 // FIXME: Implement! 6165 switch (*Name) { 6166 case 'I': // Signed 13-bit constant 6167 case 'J': // Zero 6168 case 'K': // 32-bit constant with the low 12 bits clear 6169 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6170 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6171 case 'N': // Same as 'K' but zext (required for SIMode) 6172 case 'O': // The constant 4096 6173 return true; 6174 } 6175 return false; 6176 } 6177 const char *getClobbers() const override { 6178 // FIXME: Implement! 6179 return ""; 6180 } 6181 6182 // No Sparc V7 for now, the backend doesn't support it anyway. 6183 enum CPUKind { 6184 CK_GENERIC, 6185 CK_V8, 6186 CK_SUPERSPARC, 6187 CK_SPARCLITE, 6188 CK_F934, 6189 CK_HYPERSPARC, 6190 CK_SPARCLITE86X, 6191 CK_SPARCLET, 6192 CK_TSC701, 6193 CK_V9, 6194 CK_ULTRASPARC, 6195 CK_ULTRASPARC3, 6196 CK_NIAGARA, 6197 CK_NIAGARA2, 6198 CK_NIAGARA3, 6199 CK_NIAGARA4, 6200 CK_MYRIAD2_1, 6201 CK_MYRIAD2_2 6202 } CPU = CK_GENERIC; 6203 6204 enum CPUGeneration { 6205 CG_V8, 6206 CG_V9, 6207 }; 6208 6209 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6210 switch (Kind) { 6211 case CK_GENERIC: 6212 case CK_V8: 6213 case CK_SUPERSPARC: 6214 case CK_SPARCLITE: 6215 case CK_F934: 6216 case CK_HYPERSPARC: 6217 case CK_SPARCLITE86X: 6218 case CK_SPARCLET: 6219 case CK_TSC701: 6220 case CK_MYRIAD2_1: 6221 case CK_MYRIAD2_2: 6222 return CG_V8; 6223 case CK_V9: 6224 case CK_ULTRASPARC: 6225 case CK_ULTRASPARC3: 6226 case CK_NIAGARA: 6227 case CK_NIAGARA2: 6228 case CK_NIAGARA3: 6229 case CK_NIAGARA4: 6230 return CG_V9; 6231 } 6232 llvm_unreachable("Unexpected CPU kind"); 6233 } 6234 6235 CPUKind getCPUKind(StringRef Name) const { 6236 return llvm::StringSwitch<CPUKind>(Name) 6237 .Case("v8", CK_V8) 6238 .Case("supersparc", CK_SUPERSPARC) 6239 .Case("sparclite", CK_SPARCLITE) 6240 .Case("f934", CK_F934) 6241 .Case("hypersparc", CK_HYPERSPARC) 6242 .Case("sparclite86x", CK_SPARCLITE86X) 6243 .Case("sparclet", CK_SPARCLET) 6244 .Case("tsc701", CK_TSC701) 6245 .Case("v9", CK_V9) 6246 .Case("ultrasparc", CK_ULTRASPARC) 6247 .Case("ultrasparc3", CK_ULTRASPARC3) 6248 .Case("niagara", CK_NIAGARA) 6249 .Case("niagara2", CK_NIAGARA2) 6250 .Case("niagara3", CK_NIAGARA3) 6251 .Case("niagara4", CK_NIAGARA4) 6252 .Case("myriad2", CK_MYRIAD2_1) 6253 .Case("myriad2.1", CK_MYRIAD2_1) 6254 .Case("myriad2.2", CK_MYRIAD2_2) 6255 .Default(CK_GENERIC); 6256 } 6257 6258 bool setCPU(const std::string &Name) override { 6259 CPU = getCPUKind(Name); 6260 return CPU != CK_GENERIC; 6261 } 6262 }; 6263 6264 const char * const SparcTargetInfo::GCCRegNames[] = { 6265 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6266 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6267 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6268 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6269 }; 6270 6271 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6272 return llvm::makeArrayRef(GCCRegNames); 6273 } 6274 6275 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6276 { { "g0" }, "r0" }, 6277 { { "g1" }, "r1" }, 6278 { { "g2" }, "r2" }, 6279 { { "g3" }, "r3" }, 6280 { { "g4" }, "r4" }, 6281 { { "g5" }, "r5" }, 6282 { { "g6" }, "r6" }, 6283 { { "g7" }, "r7" }, 6284 { { "o0" }, "r8" }, 6285 { { "o1" }, "r9" }, 6286 { { "o2" }, "r10" }, 6287 { { "o3" }, "r11" }, 6288 { { "o4" }, "r12" }, 6289 { { "o5" }, "r13" }, 6290 { { "o6", "sp" }, "r14" }, 6291 { { "o7" }, "r15" }, 6292 { { "l0" }, "r16" }, 6293 { { "l1" }, "r17" }, 6294 { { "l2" }, "r18" }, 6295 { { "l3" }, "r19" }, 6296 { { "l4" }, "r20" }, 6297 { { "l5" }, "r21" }, 6298 { { "l6" }, "r22" }, 6299 { { "l7" }, "r23" }, 6300 { { "i0" }, "r24" }, 6301 { { "i1" }, "r25" }, 6302 { { "i2" }, "r26" }, 6303 { { "i3" }, "r27" }, 6304 { { "i4" }, "r28" }, 6305 { { "i5" }, "r29" }, 6306 { { "i6", "fp" }, "r30" }, 6307 { { "i7" }, "r31" }, 6308 }; 6309 6310 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6311 return llvm::makeArrayRef(GCCRegAliases); 6312 } 6313 6314 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6315 class SparcV8TargetInfo : public SparcTargetInfo { 6316 public: 6317 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6318 : SparcTargetInfo(Triple, Opts) { 6319 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6320 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6321 switch (getTriple().getOS()) { 6322 default: 6323 SizeType = UnsignedInt; 6324 IntPtrType = SignedInt; 6325 PtrDiffType = SignedInt; 6326 break; 6327 case llvm::Triple::NetBSD: 6328 case llvm::Triple::OpenBSD: 6329 SizeType = UnsignedLong; 6330 IntPtrType = SignedLong; 6331 PtrDiffType = SignedLong; 6332 break; 6333 } 6334 } 6335 6336 void getTargetDefines(const LangOptions &Opts, 6337 MacroBuilder &Builder) const override { 6338 SparcTargetInfo::getTargetDefines(Opts, Builder); 6339 switch (getCPUGeneration(CPU)) { 6340 case CG_V8: 6341 Builder.defineMacro("__sparcv8"); 6342 if (getTriple().getOS() != llvm::Triple::Solaris) 6343 Builder.defineMacro("__sparcv8__"); 6344 break; 6345 case CG_V9: 6346 Builder.defineMacro("__sparcv9"); 6347 if (getTriple().getOS() != llvm::Triple::Solaris) { 6348 Builder.defineMacro("__sparcv9__"); 6349 Builder.defineMacro("__sparc_v9__"); 6350 } 6351 break; 6352 } 6353 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6354 switch (CPU) { 6355 case CK_MYRIAD2_1: 6356 Builder.defineMacro("__myriad2", "1"); 6357 Builder.defineMacro("__myriad2__", "1"); 6358 break; 6359 case CK_MYRIAD2_2: 6360 Builder.defineMacro("__myriad2", "2"); 6361 Builder.defineMacro("__myriad2__", "2"); 6362 break; 6363 default: 6364 break; 6365 } 6366 } 6367 } 6368 }; 6369 6370 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6371 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6372 public: 6373 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6374 : SparcV8TargetInfo(Triple, Opts) { 6375 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6376 BigEndian = false; 6377 } 6378 }; 6379 6380 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6381 class SparcV9TargetInfo : public SparcTargetInfo { 6382 public: 6383 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6384 : SparcTargetInfo(Triple, Opts) { 6385 // FIXME: Support Sparc quad-precision long double? 6386 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6387 // This is an LP64 platform. 6388 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6389 6390 // OpenBSD uses long long for int64_t and intmax_t. 6391 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6392 IntMaxType = SignedLongLong; 6393 else 6394 IntMaxType = SignedLong; 6395 Int64Type = IntMaxType; 6396 6397 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6398 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6399 LongDoubleWidth = 128; 6400 LongDoubleAlign = 128; 6401 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6402 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6403 } 6404 6405 void getTargetDefines(const LangOptions &Opts, 6406 MacroBuilder &Builder) const override { 6407 SparcTargetInfo::getTargetDefines(Opts, Builder); 6408 Builder.defineMacro("__sparcv9"); 6409 Builder.defineMacro("__arch64__"); 6410 // Solaris doesn't need these variants, but the BSDs do. 6411 if (getTriple().getOS() != llvm::Triple::Solaris) { 6412 Builder.defineMacro("__sparc64__"); 6413 Builder.defineMacro("__sparc_v9__"); 6414 Builder.defineMacro("__sparcv9__"); 6415 } 6416 } 6417 6418 bool setCPU(const std::string &Name) override { 6419 if (!SparcTargetInfo::setCPU(Name)) 6420 return false; 6421 return getCPUGeneration(CPU) == CG_V9; 6422 } 6423 }; 6424 6425 class SystemZTargetInfo : public TargetInfo { 6426 static const Builtin::Info BuiltinInfo[]; 6427 static const char *const GCCRegNames[]; 6428 std::string CPU; 6429 bool HasTransactionalExecution; 6430 bool HasVector; 6431 6432 public: 6433 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6434 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6435 HasVector(false) { 6436 IntMaxType = SignedLong; 6437 Int64Type = SignedLong; 6438 TLSSupported = true; 6439 IntWidth = IntAlign = 32; 6440 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6441 PointerWidth = PointerAlign = 64; 6442 LongDoubleWidth = 128; 6443 LongDoubleAlign = 64; 6444 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6445 DefaultAlignForAttributeAligned = 64; 6446 MinGlobalAlign = 16; 6447 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6448 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6449 } 6450 void getTargetDefines(const LangOptions &Opts, 6451 MacroBuilder &Builder) const override { 6452 Builder.defineMacro("__s390__"); 6453 Builder.defineMacro("__s390x__"); 6454 Builder.defineMacro("__zarch__"); 6455 Builder.defineMacro("__LONG_DOUBLE_128__"); 6456 6457 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6458 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6459 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6460 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6461 6462 if (HasTransactionalExecution) 6463 Builder.defineMacro("__HTM__"); 6464 if (Opts.ZVector) 6465 Builder.defineMacro("__VEC__", "10301"); 6466 } 6467 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6468 return llvm::makeArrayRef(BuiltinInfo, 6469 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6470 } 6471 6472 ArrayRef<const char *> getGCCRegNames() const override; 6473 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6474 // No aliases. 6475 return None; 6476 } 6477 bool validateAsmConstraint(const char *&Name, 6478 TargetInfo::ConstraintInfo &info) const override; 6479 const char *getClobbers() const override { 6480 // FIXME: Is this really right? 6481 return ""; 6482 } 6483 BuiltinVaListKind getBuiltinVaListKind() const override { 6484 return TargetInfo::SystemZBuiltinVaList; 6485 } 6486 bool setCPU(const std::string &Name) override { 6487 CPU = Name; 6488 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6489 .Case("z10", true) 6490 .Case("z196", true) 6491 .Case("zEC12", true) 6492 .Case("z13", true) 6493 .Default(false); 6494 6495 return CPUKnown; 6496 } 6497 bool 6498 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6499 StringRef CPU, 6500 const std::vector<std::string> &FeaturesVec) const override { 6501 if (CPU == "zEC12") 6502 Features["transactional-execution"] = true; 6503 if (CPU == "z13") { 6504 Features["transactional-execution"] = true; 6505 Features["vector"] = true; 6506 } 6507 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6508 } 6509 6510 bool handleTargetFeatures(std::vector<std::string> &Features, 6511 DiagnosticsEngine &Diags) override { 6512 HasTransactionalExecution = false; 6513 for (const auto &Feature : Features) { 6514 if (Feature == "+transactional-execution") 6515 HasTransactionalExecution = true; 6516 else if (Feature == "+vector") 6517 HasVector = true; 6518 } 6519 // If we use the vector ABI, vector types are 64-bit aligned. 6520 if (HasVector) { 6521 MaxVectorAlign = 64; 6522 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6523 "-v128:64-a:8:16-n32:64"); 6524 } 6525 return true; 6526 } 6527 6528 bool hasFeature(StringRef Feature) const override { 6529 return llvm::StringSwitch<bool>(Feature) 6530 .Case("systemz", true) 6531 .Case("htm", HasTransactionalExecution) 6532 .Case("vx", HasVector) 6533 .Default(false); 6534 } 6535 6536 StringRef getABI() const override { 6537 if (HasVector) 6538 return "vector"; 6539 return ""; 6540 } 6541 6542 bool useFloat128ManglingForLongDouble() const override { 6543 return true; 6544 } 6545 }; 6546 6547 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6548 #define BUILTIN(ID, TYPE, ATTRS) \ 6549 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6550 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6551 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6552 #include "clang/Basic/BuiltinsSystemZ.def" 6553 }; 6554 6555 const char *const SystemZTargetInfo::GCCRegNames[] = { 6556 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6557 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6558 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6559 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6560 }; 6561 6562 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6563 return llvm::makeArrayRef(GCCRegNames); 6564 } 6565 6566 bool SystemZTargetInfo:: 6567 validateAsmConstraint(const char *&Name, 6568 TargetInfo::ConstraintInfo &Info) const { 6569 switch (*Name) { 6570 default: 6571 return false; 6572 6573 case 'a': // Address register 6574 case 'd': // Data register (equivalent to 'r') 6575 case 'f': // Floating-point register 6576 Info.setAllowsRegister(); 6577 return true; 6578 6579 case 'I': // Unsigned 8-bit constant 6580 case 'J': // Unsigned 12-bit constant 6581 case 'K': // Signed 16-bit constant 6582 case 'L': // Signed 20-bit displacement (on all targets we support) 6583 case 'M': // 0x7fffffff 6584 return true; 6585 6586 case 'Q': // Memory with base and unsigned 12-bit displacement 6587 case 'R': // Likewise, plus an index 6588 case 'S': // Memory with base and signed 20-bit displacement 6589 case 'T': // Likewise, plus an index 6590 Info.setAllowsMemory(); 6591 return true; 6592 } 6593 } 6594 6595 class MSP430TargetInfo : public TargetInfo { 6596 static const char *const GCCRegNames[]; 6597 6598 public: 6599 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6600 : TargetInfo(Triple) { 6601 BigEndian = false; 6602 TLSSupported = false; 6603 IntWidth = 16; 6604 IntAlign = 16; 6605 LongWidth = 32; 6606 LongLongWidth = 64; 6607 LongAlign = LongLongAlign = 16; 6608 PointerWidth = 16; 6609 PointerAlign = 16; 6610 SuitableAlign = 16; 6611 SizeType = UnsignedInt; 6612 IntMaxType = SignedLongLong; 6613 IntPtrType = SignedInt; 6614 PtrDiffType = SignedInt; 6615 SigAtomicType = SignedLong; 6616 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6617 } 6618 void getTargetDefines(const LangOptions &Opts, 6619 MacroBuilder &Builder) const override { 6620 Builder.defineMacro("MSP430"); 6621 Builder.defineMacro("__MSP430__"); 6622 // FIXME: defines for different 'flavours' of MCU 6623 } 6624 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6625 // FIXME: Implement. 6626 return None; 6627 } 6628 bool hasFeature(StringRef Feature) const override { 6629 return Feature == "msp430"; 6630 } 6631 ArrayRef<const char *> getGCCRegNames() const override; 6632 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6633 // No aliases. 6634 return None; 6635 } 6636 bool validateAsmConstraint(const char *&Name, 6637 TargetInfo::ConstraintInfo &info) const override { 6638 // FIXME: implement 6639 switch (*Name) { 6640 case 'K': // the constant 1 6641 case 'L': // constant -1^20 .. 1^19 6642 case 'M': // constant 1-4: 6643 return true; 6644 } 6645 // No target constraints for now. 6646 return false; 6647 } 6648 const char *getClobbers() const override { 6649 // FIXME: Is this really right? 6650 return ""; 6651 } 6652 BuiltinVaListKind getBuiltinVaListKind() const override { 6653 // FIXME: implement 6654 return TargetInfo::CharPtrBuiltinVaList; 6655 } 6656 }; 6657 6658 const char *const MSP430TargetInfo::GCCRegNames[] = { 6659 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6660 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6661 6662 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6663 return llvm::makeArrayRef(GCCRegNames); 6664 } 6665 6666 // LLVM and Clang cannot be used directly to output native binaries for 6667 // target, but is used to compile C code to llvm bitcode with correct 6668 // type and alignment information. 6669 // 6670 // TCE uses the llvm bitcode as input and uses it for generating customized 6671 // target processor and program binary. TCE co-design environment is 6672 // publicly available in http://tce.cs.tut.fi 6673 6674 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6675 3, // opencl_global 6676 4, // opencl_local 6677 5, // opencl_constant 6678 // FIXME: generic has to be added to the target 6679 0, // opencl_generic 6680 0, // cuda_device 6681 0, // cuda_constant 6682 0 // cuda_shared 6683 }; 6684 6685 class TCETargetInfo : public TargetInfo { 6686 public: 6687 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6688 : TargetInfo(Triple) { 6689 TLSSupported = false; 6690 IntWidth = 32; 6691 LongWidth = LongLongWidth = 32; 6692 PointerWidth = 32; 6693 IntAlign = 32; 6694 LongAlign = LongLongAlign = 32; 6695 PointerAlign = 32; 6696 SuitableAlign = 32; 6697 SizeType = UnsignedInt; 6698 IntMaxType = SignedLong; 6699 IntPtrType = SignedInt; 6700 PtrDiffType = SignedInt; 6701 FloatWidth = 32; 6702 FloatAlign = 32; 6703 DoubleWidth = 32; 6704 DoubleAlign = 32; 6705 LongDoubleWidth = 32; 6706 LongDoubleAlign = 32; 6707 FloatFormat = &llvm::APFloat::IEEEsingle; 6708 DoubleFormat = &llvm::APFloat::IEEEsingle; 6709 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6710 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 6711 "-f64:32-v64:32-v128:32-a:0:32-n32"); 6712 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6713 UseAddrSpaceMapMangling = true; 6714 } 6715 6716 void getTargetDefines(const LangOptions &Opts, 6717 MacroBuilder &Builder) const override { 6718 DefineStd(Builder, "tce", Opts); 6719 Builder.defineMacro("__TCE__"); 6720 Builder.defineMacro("__TCE_V1__"); 6721 } 6722 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6723 6724 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6725 const char *getClobbers() const override { return ""; } 6726 BuiltinVaListKind getBuiltinVaListKind() const override { 6727 return TargetInfo::VoidPtrBuiltinVaList; 6728 } 6729 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6730 bool validateAsmConstraint(const char *&Name, 6731 TargetInfo::ConstraintInfo &info) const override { 6732 return true; 6733 } 6734 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6735 return None; 6736 } 6737 }; 6738 6739 class BPFTargetInfo : public TargetInfo { 6740 public: 6741 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6742 : TargetInfo(Triple) { 6743 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6744 SizeType = UnsignedLong; 6745 PtrDiffType = SignedLong; 6746 IntPtrType = SignedLong; 6747 IntMaxType = SignedLong; 6748 Int64Type = SignedLong; 6749 RegParmMax = 5; 6750 if (Triple.getArch() == llvm::Triple::bpfeb) { 6751 BigEndian = true; 6752 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 6753 } else { 6754 BigEndian = false; 6755 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 6756 } 6757 MaxAtomicPromoteWidth = 64; 6758 MaxAtomicInlineWidth = 64; 6759 TLSSupported = false; 6760 } 6761 void getTargetDefines(const LangOptions &Opts, 6762 MacroBuilder &Builder) const override { 6763 DefineStd(Builder, "bpf", Opts); 6764 Builder.defineMacro("__BPF__"); 6765 } 6766 bool hasFeature(StringRef Feature) const override { 6767 return Feature == "bpf"; 6768 } 6769 6770 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6771 const char *getClobbers() const override { 6772 return ""; 6773 } 6774 BuiltinVaListKind getBuiltinVaListKind() const override { 6775 return TargetInfo::VoidPtrBuiltinVaList; 6776 } 6777 ArrayRef<const char *> getGCCRegNames() const override { 6778 return None; 6779 } 6780 bool validateAsmConstraint(const char *&Name, 6781 TargetInfo::ConstraintInfo &info) const override { 6782 return true; 6783 } 6784 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6785 return None; 6786 } 6787 }; 6788 6789 class MipsTargetInfoBase : public TargetInfo { 6790 virtual void setDataLayout() = 0; 6791 6792 static const Builtin::Info BuiltinInfo[]; 6793 std::string CPU; 6794 bool IsMips16; 6795 bool IsMicromips; 6796 bool IsNan2008; 6797 bool IsSingleFloat; 6798 enum MipsFloatABI { 6799 HardFloat, SoftFloat 6800 } FloatABI; 6801 enum DspRevEnum { 6802 NoDSP, DSP1, DSP2 6803 } DspRev; 6804 bool HasMSA; 6805 6806 protected: 6807 bool HasFP64; 6808 std::string ABI; 6809 6810 public: 6811 MipsTargetInfoBase(const llvm::Triple &Triple, const TargetOptions &, 6812 const std::string &ABIStr, const std::string &CPUStr) 6813 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6814 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6815 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6816 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6817 } 6818 6819 bool isNaN2008Default() const { 6820 return CPU == "mips32r6" || CPU == "mips64r6"; 6821 } 6822 6823 bool isFP64Default() const { 6824 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6825 } 6826 6827 bool isNan2008() const override { 6828 return IsNan2008; 6829 } 6830 6831 StringRef getABI() const override { return ABI; } 6832 bool setCPU(const std::string &Name) override { 6833 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6834 getTriple().getArch() == llvm::Triple::mipsel; 6835 CPU = Name; 6836 return llvm::StringSwitch<bool>(Name) 6837 .Case("mips1", IsMips32) 6838 .Case("mips2", IsMips32) 6839 .Case("mips3", true) 6840 .Case("mips4", true) 6841 .Case("mips5", true) 6842 .Case("mips32", IsMips32) 6843 .Case("mips32r2", IsMips32) 6844 .Case("mips32r3", IsMips32) 6845 .Case("mips32r5", IsMips32) 6846 .Case("mips32r6", IsMips32) 6847 .Case("mips64", true) 6848 .Case("mips64r2", true) 6849 .Case("mips64r3", true) 6850 .Case("mips64r5", true) 6851 .Case("mips64r6", true) 6852 .Case("octeon", true) 6853 .Case("p5600", true) 6854 .Default(false); 6855 } 6856 const std::string& getCPU() const { return CPU; } 6857 bool 6858 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6859 StringRef CPU, 6860 const std::vector<std::string> &FeaturesVec) const override { 6861 if (CPU.empty()) 6862 CPU = getCPU(); 6863 if (CPU == "octeon") 6864 Features["mips64r2"] = Features["cnmips"] = true; 6865 else 6866 Features[CPU] = true; 6867 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6868 } 6869 6870 void getTargetDefines(const LangOptions &Opts, 6871 MacroBuilder &Builder) const override { 6872 Builder.defineMacro("__mips__"); 6873 Builder.defineMacro("_mips"); 6874 if (Opts.GNUMode) 6875 Builder.defineMacro("mips"); 6876 6877 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6878 6879 switch (FloatABI) { 6880 case HardFloat: 6881 Builder.defineMacro("__mips_hard_float", Twine(1)); 6882 break; 6883 case SoftFloat: 6884 Builder.defineMacro("__mips_soft_float", Twine(1)); 6885 break; 6886 } 6887 6888 if (IsSingleFloat) 6889 Builder.defineMacro("__mips_single_float", Twine(1)); 6890 6891 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6892 Builder.defineMacro("_MIPS_FPSET", 6893 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6894 6895 if (IsMips16) 6896 Builder.defineMacro("__mips16", Twine(1)); 6897 6898 if (IsMicromips) 6899 Builder.defineMacro("__mips_micromips", Twine(1)); 6900 6901 if (IsNan2008) 6902 Builder.defineMacro("__mips_nan2008", Twine(1)); 6903 6904 switch (DspRev) { 6905 default: 6906 break; 6907 case DSP1: 6908 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6909 Builder.defineMacro("__mips_dsp", Twine(1)); 6910 break; 6911 case DSP2: 6912 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6913 Builder.defineMacro("__mips_dspr2", Twine(1)); 6914 Builder.defineMacro("__mips_dsp", Twine(1)); 6915 break; 6916 } 6917 6918 if (HasMSA) 6919 Builder.defineMacro("__mips_msa", Twine(1)); 6920 6921 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6922 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6923 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6924 6925 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6926 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6927 6928 // These shouldn't be defined for MIPS-I but there's no need to check 6929 // for that since MIPS-I isn't supported. 6930 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6931 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6932 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6933 } 6934 6935 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6936 return llvm::makeArrayRef(BuiltinInfo, 6937 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 6938 } 6939 bool hasFeature(StringRef Feature) const override { 6940 return llvm::StringSwitch<bool>(Feature) 6941 .Case("mips", true) 6942 .Case("fp64", HasFP64) 6943 .Default(false); 6944 } 6945 BuiltinVaListKind getBuiltinVaListKind() const override { 6946 return TargetInfo::VoidPtrBuiltinVaList; 6947 } 6948 ArrayRef<const char *> getGCCRegNames() const override { 6949 static const char *const GCCRegNames[] = { 6950 // CPU register names 6951 // Must match second column of GCCRegAliases 6952 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6953 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6954 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6955 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6956 // Floating point register names 6957 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6958 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6959 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6960 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6961 // Hi/lo and condition register names 6962 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6963 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 6964 "$ac3hi","$ac3lo", 6965 // MSA register names 6966 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6967 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6968 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6969 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6970 // MSA control register names 6971 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6972 "$msarequest", "$msamap", "$msaunmap" 6973 }; 6974 return llvm::makeArrayRef(GCCRegNames); 6975 } 6976 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 6977 bool validateAsmConstraint(const char *&Name, 6978 TargetInfo::ConstraintInfo &Info) const override { 6979 switch (*Name) { 6980 default: 6981 return false; 6982 case 'r': // CPU registers. 6983 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6984 case 'y': // Equivalent to "r", backward compatibility only. 6985 case 'f': // floating-point registers. 6986 case 'c': // $25 for indirect jumps 6987 case 'l': // lo register 6988 case 'x': // hilo register pair 6989 Info.setAllowsRegister(); 6990 return true; 6991 case 'I': // Signed 16-bit constant 6992 case 'J': // Integer 0 6993 case 'K': // Unsigned 16-bit constant 6994 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6995 case 'M': // Constants not loadable via lui, addiu, or ori 6996 case 'N': // Constant -1 to -65535 6997 case 'O': // A signed 15-bit constant 6998 case 'P': // A constant between 1 go 65535 6999 return true; 7000 case 'R': // An address that can be used in a non-macro load or store 7001 Info.setAllowsMemory(); 7002 return true; 7003 case 'Z': 7004 if (Name[1] == 'C') { // An address usable by ll, and sc. 7005 Info.setAllowsMemory(); 7006 Name++; // Skip over 'Z'. 7007 return true; 7008 } 7009 return false; 7010 } 7011 } 7012 7013 std::string convertConstraint(const char *&Constraint) const override { 7014 std::string R; 7015 switch (*Constraint) { 7016 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7017 if (Constraint[1] == 'C') { 7018 R = std::string("^") + std::string(Constraint, 2); 7019 Constraint++; 7020 return R; 7021 } 7022 break; 7023 } 7024 return TargetInfo::convertConstraint(Constraint); 7025 } 7026 7027 const char *getClobbers() const override { 7028 // In GCC, $1 is not widely used in generated code (it's used only in a few 7029 // specific situations), so there is no real need for users to add it to 7030 // the clobbers list if they want to use it in their inline assembly code. 7031 // 7032 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7033 // code generation, so using it in inline assembly without adding it to the 7034 // clobbers list can cause conflicts between the inline assembly code and 7035 // the surrounding generated code. 7036 // 7037 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7038 // operands, which will conflict with the ".set at" assembler option (which 7039 // we use only for inline assembly, in order to maintain compatibility with 7040 // GCC) and will also conflict with the user's usage of $1. 7041 // 7042 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7043 // register for generated code is to automatically clobber $1 for all inline 7044 // assembly code. 7045 // 7046 // FIXME: We should automatically clobber $1 only for inline assembly code 7047 // which actually uses it. This would allow LLVM to use $1 for inline 7048 // assembly operands if the user's assembly code doesn't use it. 7049 return "~{$1}"; 7050 } 7051 7052 bool handleTargetFeatures(std::vector<std::string> &Features, 7053 DiagnosticsEngine &Diags) override { 7054 IsMips16 = false; 7055 IsMicromips = false; 7056 IsNan2008 = isNaN2008Default(); 7057 IsSingleFloat = false; 7058 FloatABI = HardFloat; 7059 DspRev = NoDSP; 7060 HasFP64 = isFP64Default(); 7061 7062 for (const auto &Feature : Features) { 7063 if (Feature == "+single-float") 7064 IsSingleFloat = true; 7065 else if (Feature == "+soft-float") 7066 FloatABI = SoftFloat; 7067 else if (Feature == "+mips16") 7068 IsMips16 = true; 7069 else if (Feature == "+micromips") 7070 IsMicromips = true; 7071 else if (Feature == "+dsp") 7072 DspRev = std::max(DspRev, DSP1); 7073 else if (Feature == "+dspr2") 7074 DspRev = std::max(DspRev, DSP2); 7075 else if (Feature == "+msa") 7076 HasMSA = true; 7077 else if (Feature == "+fp64") 7078 HasFP64 = true; 7079 else if (Feature == "-fp64") 7080 HasFP64 = false; 7081 else if (Feature == "+nan2008") 7082 IsNan2008 = true; 7083 else if (Feature == "-nan2008") 7084 IsNan2008 = false; 7085 } 7086 7087 setDataLayout(); 7088 7089 return true; 7090 } 7091 7092 int getEHDataRegisterNumber(unsigned RegNo) const override { 7093 if (RegNo == 0) return 4; 7094 if (RegNo == 1) return 5; 7095 return -1; 7096 } 7097 7098 bool isCLZForZeroUndef() const override { return false; } 7099 }; 7100 7101 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 7102 #define BUILTIN(ID, TYPE, ATTRS) \ 7103 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7104 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7105 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7106 #include "clang/Basic/BuiltinsMips.def" 7107 }; 7108 7109 class Mips32TargetInfoBase : public MipsTargetInfoBase { 7110 public: 7111 Mips32TargetInfoBase(const llvm::Triple &Triple, const TargetOptions &Opts) 7112 : MipsTargetInfoBase(Triple, Opts, "o32", "mips32r2") { 7113 SizeType = UnsignedInt; 7114 PtrDiffType = SignedInt; 7115 Int64Type = SignedLongLong; 7116 IntMaxType = Int64Type; 7117 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7118 } 7119 bool setABI(const std::string &Name) override { 7120 if (Name == "o32" || Name == "eabi") { 7121 ABI = Name; 7122 return true; 7123 } 7124 return false; 7125 } 7126 void getTargetDefines(const LangOptions &Opts, 7127 MacroBuilder &Builder) const override { 7128 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7129 7130 Builder.defineMacro("__mips", "32"); 7131 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7132 7133 const std::string& CPUStr = getCPU(); 7134 if (CPUStr == "mips32") 7135 Builder.defineMacro("__mips_isa_rev", "1"); 7136 else if (CPUStr == "mips32r2") 7137 Builder.defineMacro("__mips_isa_rev", "2"); 7138 else if (CPUStr == "mips32r3") 7139 Builder.defineMacro("__mips_isa_rev", "3"); 7140 else if (CPUStr == "mips32r5") 7141 Builder.defineMacro("__mips_isa_rev", "5"); 7142 else if (CPUStr == "mips32r6") 7143 Builder.defineMacro("__mips_isa_rev", "6"); 7144 7145 if (ABI == "o32") { 7146 Builder.defineMacro("__mips_o32"); 7147 Builder.defineMacro("_ABIO32", "1"); 7148 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7149 } 7150 else if (ABI == "eabi") 7151 Builder.defineMacro("__mips_eabi"); 7152 else 7153 llvm_unreachable("Invalid ABI for Mips32."); 7154 } 7155 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7156 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7157 { { "at" }, "$1" }, 7158 { { "v0" }, "$2" }, 7159 { { "v1" }, "$3" }, 7160 { { "a0" }, "$4" }, 7161 { { "a1" }, "$5" }, 7162 { { "a2" }, "$6" }, 7163 { { "a3" }, "$7" }, 7164 { { "t0" }, "$8" }, 7165 { { "t1" }, "$9" }, 7166 { { "t2" }, "$10" }, 7167 { { "t3" }, "$11" }, 7168 { { "t4" }, "$12" }, 7169 { { "t5" }, "$13" }, 7170 { { "t6" }, "$14" }, 7171 { { "t7" }, "$15" }, 7172 { { "s0" }, "$16" }, 7173 { { "s1" }, "$17" }, 7174 { { "s2" }, "$18" }, 7175 { { "s3" }, "$19" }, 7176 { { "s4" }, "$20" }, 7177 { { "s5" }, "$21" }, 7178 { { "s6" }, "$22" }, 7179 { { "s7" }, "$23" }, 7180 { { "t8" }, "$24" }, 7181 { { "t9" }, "$25" }, 7182 { { "k0" }, "$26" }, 7183 { { "k1" }, "$27" }, 7184 { { "gp" }, "$28" }, 7185 { { "sp","$sp" }, "$29" }, 7186 { { "fp","$fp" }, "$30" }, 7187 { { "ra" }, "$31" } 7188 }; 7189 return llvm::makeArrayRef(GCCRegAliases); 7190 } 7191 }; 7192 7193 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 7194 void setDataLayout() override { 7195 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7196 } 7197 7198 public: 7199 Mips32EBTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7200 : Mips32TargetInfoBase(Triple, Opts) { 7201 } 7202 void getTargetDefines(const LangOptions &Opts, 7203 MacroBuilder &Builder) const override { 7204 DefineStd(Builder, "MIPSEB", Opts); 7205 Builder.defineMacro("_MIPSEB"); 7206 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7207 } 7208 }; 7209 7210 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 7211 void setDataLayout() override { 7212 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7213 } 7214 7215 public: 7216 Mips32ELTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7217 : Mips32TargetInfoBase(Triple, Opts) { 7218 BigEndian = false; 7219 } 7220 void getTargetDefines(const LangOptions &Opts, 7221 MacroBuilder &Builder) const override { 7222 DefineStd(Builder, "MIPSEL", Opts); 7223 Builder.defineMacro("_MIPSEL"); 7224 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7225 } 7226 }; 7227 7228 class Mips64TargetInfoBase : public MipsTargetInfoBase { 7229 public: 7230 Mips64TargetInfoBase(const llvm::Triple &Triple, const TargetOptions &Opts) 7231 : MipsTargetInfoBase(Triple, Opts, "n64", "mips64r2") { 7232 LongDoubleWidth = LongDoubleAlign = 128; 7233 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7234 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7235 LongDoubleWidth = LongDoubleAlign = 64; 7236 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7237 } 7238 setN64ABITypes(); 7239 SuitableAlign = 128; 7240 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7241 } 7242 7243 void setN64ABITypes() { 7244 LongWidth = LongAlign = 64; 7245 PointerWidth = PointerAlign = 64; 7246 SizeType = UnsignedLong; 7247 PtrDiffType = SignedLong; 7248 Int64Type = SignedLong; 7249 IntMaxType = Int64Type; 7250 } 7251 7252 void setN32ABITypes() { 7253 LongWidth = LongAlign = 32; 7254 PointerWidth = PointerAlign = 32; 7255 SizeType = UnsignedInt; 7256 PtrDiffType = SignedInt; 7257 Int64Type = SignedLongLong; 7258 IntMaxType = Int64Type; 7259 } 7260 7261 bool setABI(const std::string &Name) override { 7262 if (Name == "n32") { 7263 setN32ABITypes(); 7264 ABI = Name; 7265 return true; 7266 } 7267 if (Name == "n64") { 7268 setN64ABITypes(); 7269 ABI = Name; 7270 return true; 7271 } 7272 return false; 7273 } 7274 7275 void getTargetDefines(const LangOptions &Opts, 7276 MacroBuilder &Builder) const override { 7277 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7278 7279 Builder.defineMacro("__mips", "64"); 7280 Builder.defineMacro("__mips64"); 7281 Builder.defineMacro("__mips64__"); 7282 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7283 7284 const std::string& CPUStr = getCPU(); 7285 if (CPUStr == "mips64") 7286 Builder.defineMacro("__mips_isa_rev", "1"); 7287 else if (CPUStr == "mips64r2") 7288 Builder.defineMacro("__mips_isa_rev", "2"); 7289 else if (CPUStr == "mips64r3") 7290 Builder.defineMacro("__mips_isa_rev", "3"); 7291 else if (CPUStr == "mips64r5") 7292 Builder.defineMacro("__mips_isa_rev", "5"); 7293 else if (CPUStr == "mips64r6") 7294 Builder.defineMacro("__mips_isa_rev", "6"); 7295 7296 if (ABI == "n32") { 7297 Builder.defineMacro("__mips_n32"); 7298 Builder.defineMacro("_ABIN32", "2"); 7299 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7300 } 7301 else if (ABI == "n64") { 7302 Builder.defineMacro("__mips_n64"); 7303 Builder.defineMacro("_ABI64", "3"); 7304 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7305 } 7306 else 7307 llvm_unreachable("Invalid ABI for Mips64."); 7308 7309 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7310 } 7311 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7312 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7313 { { "at" }, "$1" }, 7314 { { "v0" }, "$2" }, 7315 { { "v1" }, "$3" }, 7316 { { "a0" }, "$4" }, 7317 { { "a1" }, "$5" }, 7318 { { "a2" }, "$6" }, 7319 { { "a3" }, "$7" }, 7320 { { "a4" }, "$8" }, 7321 { { "a5" }, "$9" }, 7322 { { "a6" }, "$10" }, 7323 { { "a7" }, "$11" }, 7324 { { "t0" }, "$12" }, 7325 { { "t1" }, "$13" }, 7326 { { "t2" }, "$14" }, 7327 { { "t3" }, "$15" }, 7328 { { "s0" }, "$16" }, 7329 { { "s1" }, "$17" }, 7330 { { "s2" }, "$18" }, 7331 { { "s3" }, "$19" }, 7332 { { "s4" }, "$20" }, 7333 { { "s5" }, "$21" }, 7334 { { "s6" }, "$22" }, 7335 { { "s7" }, "$23" }, 7336 { { "t8" }, "$24" }, 7337 { { "t9" }, "$25" }, 7338 { { "k0" }, "$26" }, 7339 { { "k1" }, "$27" }, 7340 { { "gp" }, "$28" }, 7341 { { "sp","$sp" }, "$29" }, 7342 { { "fp","$fp" }, "$30" }, 7343 { { "ra" }, "$31" } 7344 }; 7345 return llvm::makeArrayRef(GCCRegAliases); 7346 } 7347 7348 bool hasInt128Type() const override { return true; } 7349 }; 7350 7351 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 7352 void setDataLayout() override { 7353 if (ABI == "n32") 7354 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7355 else 7356 resetDataLayout("E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7357 } 7358 7359 public: 7360 Mips64EBTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7361 : Mips64TargetInfoBase(Triple, Opts) {} 7362 void getTargetDefines(const LangOptions &Opts, 7363 MacroBuilder &Builder) const override { 7364 DefineStd(Builder, "MIPSEB", Opts); 7365 Builder.defineMacro("_MIPSEB"); 7366 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7367 } 7368 }; 7369 7370 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 7371 void setDataLayout() override { 7372 if (ABI == "n32") 7373 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7374 else 7375 resetDataLayout("e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7376 } 7377 public: 7378 Mips64ELTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7379 : Mips64TargetInfoBase(Triple, Opts) { 7380 // Default ABI is n64. 7381 BigEndian = false; 7382 } 7383 void getTargetDefines(const LangOptions &Opts, 7384 MacroBuilder &Builder) const override { 7385 DefineStd(Builder, "MIPSEL", Opts); 7386 Builder.defineMacro("_MIPSEL"); 7387 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7388 } 7389 }; 7390 7391 class PNaClTargetInfo : public TargetInfo { 7392 public: 7393 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7394 : TargetInfo(Triple) { 7395 BigEndian = false; 7396 this->LongAlign = 32; 7397 this->LongWidth = 32; 7398 this->PointerAlign = 32; 7399 this->PointerWidth = 32; 7400 this->IntMaxType = TargetInfo::SignedLongLong; 7401 this->Int64Type = TargetInfo::SignedLongLong; 7402 this->DoubleAlign = 64; 7403 this->LongDoubleWidth = 64; 7404 this->LongDoubleAlign = 64; 7405 this->SizeType = TargetInfo::UnsignedInt; 7406 this->PtrDiffType = TargetInfo::SignedInt; 7407 this->IntPtrType = TargetInfo::SignedInt; 7408 this->RegParmMax = 0; // Disallow regparm 7409 } 7410 7411 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7412 Builder.defineMacro("__le32__"); 7413 Builder.defineMacro("__pnacl__"); 7414 } 7415 void getTargetDefines(const LangOptions &Opts, 7416 MacroBuilder &Builder) const override { 7417 getArchDefines(Opts, Builder); 7418 } 7419 bool hasFeature(StringRef Feature) const override { 7420 return Feature == "pnacl"; 7421 } 7422 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7423 BuiltinVaListKind getBuiltinVaListKind() const override { 7424 return TargetInfo::PNaClABIBuiltinVaList; 7425 } 7426 ArrayRef<const char *> getGCCRegNames() const override; 7427 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7428 bool validateAsmConstraint(const char *&Name, 7429 TargetInfo::ConstraintInfo &Info) const override { 7430 return false; 7431 } 7432 7433 const char *getClobbers() const override { 7434 return ""; 7435 } 7436 }; 7437 7438 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7439 return None; 7440 } 7441 7442 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7443 return None; 7444 } 7445 7446 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7447 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7448 public: 7449 NaClMips32ELTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7450 : Mips32ELTargetInfo(Triple, Opts) {} 7451 7452 BuiltinVaListKind getBuiltinVaListKind() const override { 7453 return TargetInfo::PNaClABIBuiltinVaList; 7454 } 7455 }; 7456 7457 class Le64TargetInfo : public TargetInfo { 7458 static const Builtin::Info BuiltinInfo[]; 7459 7460 public: 7461 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7462 : TargetInfo(Triple) { 7463 BigEndian = false; 7464 NoAsmVariants = true; 7465 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7466 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7467 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7468 } 7469 7470 void getTargetDefines(const LangOptions &Opts, 7471 MacroBuilder &Builder) const override { 7472 DefineStd(Builder, "unix", Opts); 7473 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7474 Builder.defineMacro("__ELF__"); 7475 } 7476 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7477 return llvm::makeArrayRef(BuiltinInfo, 7478 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7479 } 7480 BuiltinVaListKind getBuiltinVaListKind() const override { 7481 return TargetInfo::PNaClABIBuiltinVaList; 7482 } 7483 const char *getClobbers() const override { return ""; } 7484 ArrayRef<const char *> getGCCRegNames() const override { 7485 return None; 7486 } 7487 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7488 return None; 7489 } 7490 bool validateAsmConstraint(const char *&Name, 7491 TargetInfo::ConstraintInfo &Info) const override { 7492 return false; 7493 } 7494 7495 bool hasProtectedVisibility() const override { return false; } 7496 }; 7497 7498 class WebAssemblyTargetInfo : public TargetInfo { 7499 static const Builtin::Info BuiltinInfo[]; 7500 7501 enum SIMDEnum { 7502 NoSIMD, 7503 SIMD128, 7504 } SIMDLevel; 7505 7506 public: 7507 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7508 : TargetInfo(T), SIMDLevel(NoSIMD) { 7509 BigEndian = false; 7510 NoAsmVariants = true; 7511 SuitableAlign = 128; 7512 LargeArrayMinWidth = 128; 7513 LargeArrayAlign = 128; 7514 SimdDefaultAlign = 128; 7515 SigAtomicType = SignedLong; 7516 LongDoubleWidth = LongDoubleAlign = 128; 7517 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7518 } 7519 7520 protected: 7521 void getTargetDefines(const LangOptions &Opts, 7522 MacroBuilder &Builder) const override { 7523 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7524 if (SIMDLevel >= SIMD128) 7525 Builder.defineMacro("__wasm_simd128__"); 7526 } 7527 7528 private: 7529 bool 7530 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7531 StringRef CPU, 7532 const std::vector<std::string> &FeaturesVec) const override { 7533 if (CPU == "bleeding-edge") 7534 Features["simd128"] = true; 7535 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7536 } 7537 bool hasFeature(StringRef Feature) const final { 7538 return llvm::StringSwitch<bool>(Feature) 7539 .Case("simd128", SIMDLevel >= SIMD128) 7540 .Default(false); 7541 } 7542 bool handleTargetFeatures(std::vector<std::string> &Features, 7543 DiagnosticsEngine &Diags) final { 7544 for (const auto &Feature : Features) { 7545 if (Feature == "+simd128") { 7546 SIMDLevel = std::max(SIMDLevel, SIMD128); 7547 continue; 7548 } 7549 if (Feature == "-simd128") { 7550 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7551 continue; 7552 } 7553 7554 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7555 << "-target-feature"; 7556 return false; 7557 } 7558 return true; 7559 } 7560 bool setCPU(const std::string &Name) final { 7561 return llvm::StringSwitch<bool>(Name) 7562 .Case("mvp", true) 7563 .Case("bleeding-edge", true) 7564 .Case("generic", true) 7565 .Default(false); 7566 } 7567 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7568 return llvm::makeArrayRef(BuiltinInfo, 7569 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7570 } 7571 BuiltinVaListKind getBuiltinVaListKind() const final { 7572 return VoidPtrBuiltinVaList; 7573 } 7574 ArrayRef<const char *> getGCCRegNames() const final { 7575 return None; 7576 } 7577 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7578 return None; 7579 } 7580 bool 7581 validateAsmConstraint(const char *&Name, 7582 TargetInfo::ConstraintInfo &Info) const final { 7583 return false; 7584 } 7585 const char *getClobbers() const final { return ""; } 7586 bool isCLZForZeroUndef() const final { return false; } 7587 bool hasInt128Type() const final { return true; } 7588 IntType getIntTypeByWidth(unsigned BitWidth, 7589 bool IsSigned) const final { 7590 // WebAssembly prefers long long for explicitly 64-bit integers. 7591 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7592 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7593 } 7594 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7595 bool IsSigned) const final { 7596 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7597 return BitWidth == 64 7598 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7599 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7600 } 7601 }; 7602 7603 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7604 #define BUILTIN(ID, TYPE, ATTRS) \ 7605 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7606 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7607 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7608 #include "clang/Basic/BuiltinsWebAssembly.def" 7609 }; 7610 7611 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7612 public: 7613 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 7614 const TargetOptions &Opts) 7615 : WebAssemblyTargetInfo(T, Opts) { 7616 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7617 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7618 } 7619 7620 protected: 7621 void getTargetDefines(const LangOptions &Opts, 7622 MacroBuilder &Builder) const override { 7623 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7624 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7625 } 7626 }; 7627 7628 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7629 public: 7630 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 7631 const TargetOptions &Opts) 7632 : WebAssemblyTargetInfo(T, Opts) { 7633 LongAlign = LongWidth = 64; 7634 PointerAlign = PointerWidth = 64; 7635 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7636 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7637 } 7638 7639 protected: 7640 void getTargetDefines(const LangOptions &Opts, 7641 MacroBuilder &Builder) const override { 7642 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7643 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7644 } 7645 }; 7646 7647 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7648 #define BUILTIN(ID, TYPE, ATTRS) \ 7649 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7650 #include "clang/Basic/BuiltinsLe64.def" 7651 }; 7652 7653 static const unsigned SPIRAddrSpaceMap[] = { 7654 1, // opencl_global 7655 3, // opencl_local 7656 2, // opencl_constant 7657 4, // opencl_generic 7658 0, // cuda_device 7659 0, // cuda_constant 7660 0 // cuda_shared 7661 }; 7662 class SPIRTargetInfo : public TargetInfo { 7663 public: 7664 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7665 : TargetInfo(Triple) { 7666 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7667 "SPIR target must use unknown OS"); 7668 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7669 "SPIR target must use unknown environment type"); 7670 BigEndian = false; 7671 TLSSupported = false; 7672 LongWidth = LongAlign = 64; 7673 AddrSpaceMap = &SPIRAddrSpaceMap; 7674 UseAddrSpaceMapMangling = true; 7675 // Define available target features 7676 // These must be defined in sorted order! 7677 NoAsmVariants = true; 7678 } 7679 void getTargetDefines(const LangOptions &Opts, 7680 MacroBuilder &Builder) const override { 7681 DefineStd(Builder, "SPIR", Opts); 7682 } 7683 bool hasFeature(StringRef Feature) const override { 7684 return Feature == "spir"; 7685 } 7686 7687 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7688 const char *getClobbers() const override { return ""; } 7689 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7690 bool validateAsmConstraint(const char *&Name, 7691 TargetInfo::ConstraintInfo &info) const override { 7692 return true; 7693 } 7694 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7695 return None; 7696 } 7697 BuiltinVaListKind getBuiltinVaListKind() const override { 7698 return TargetInfo::VoidPtrBuiltinVaList; 7699 } 7700 7701 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7702 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7703 : CCCR_Warning; 7704 } 7705 7706 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7707 return CC_SpirFunction; 7708 } 7709 }; 7710 7711 class SPIR32TargetInfo : public SPIRTargetInfo { 7712 public: 7713 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7714 : SPIRTargetInfo(Triple, Opts) { 7715 PointerWidth = PointerAlign = 32; 7716 SizeType = TargetInfo::UnsignedInt; 7717 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7718 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7719 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7720 } 7721 void getTargetDefines(const LangOptions &Opts, 7722 MacroBuilder &Builder) const override { 7723 DefineStd(Builder, "SPIR32", Opts); 7724 } 7725 }; 7726 7727 class SPIR64TargetInfo : public SPIRTargetInfo { 7728 public: 7729 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7730 : SPIRTargetInfo(Triple, Opts) { 7731 PointerWidth = PointerAlign = 64; 7732 SizeType = TargetInfo::UnsignedLong; 7733 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7734 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7735 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7736 } 7737 void getTargetDefines(const LangOptions &Opts, 7738 MacroBuilder &Builder) const override { 7739 DefineStd(Builder, "SPIR64", Opts); 7740 } 7741 }; 7742 7743 class XCoreTargetInfo : public TargetInfo { 7744 static const Builtin::Info BuiltinInfo[]; 7745 public: 7746 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7747 : TargetInfo(Triple) { 7748 BigEndian = false; 7749 NoAsmVariants = true; 7750 LongLongAlign = 32; 7751 SuitableAlign = 32; 7752 DoubleAlign = LongDoubleAlign = 32; 7753 SizeType = UnsignedInt; 7754 PtrDiffType = SignedInt; 7755 IntPtrType = SignedInt; 7756 WCharType = UnsignedChar; 7757 WIntType = UnsignedInt; 7758 UseZeroLengthBitfieldAlignment = true; 7759 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7760 "-f64:32-a:0:32-n32"); 7761 } 7762 void getTargetDefines(const LangOptions &Opts, 7763 MacroBuilder &Builder) const override { 7764 Builder.defineMacro("__XS1B__"); 7765 } 7766 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7767 return llvm::makeArrayRef(BuiltinInfo, 7768 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7769 } 7770 BuiltinVaListKind getBuiltinVaListKind() const override { 7771 return TargetInfo::VoidPtrBuiltinVaList; 7772 } 7773 const char *getClobbers() const override { 7774 return ""; 7775 } 7776 ArrayRef<const char *> getGCCRegNames() const override { 7777 static const char * const GCCRegNames[] = { 7778 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7779 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7780 }; 7781 return llvm::makeArrayRef(GCCRegNames); 7782 } 7783 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7784 return None; 7785 } 7786 bool validateAsmConstraint(const char *&Name, 7787 TargetInfo::ConstraintInfo &Info) const override { 7788 return false; 7789 } 7790 int getEHDataRegisterNumber(unsigned RegNo) const override { 7791 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7792 return (RegNo < 2)? RegNo : -1; 7793 } 7794 bool allowsLargerPreferedTypeAlignment() const override { 7795 return false; 7796 } 7797 }; 7798 7799 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7800 #define BUILTIN(ID, TYPE, ATTRS) \ 7801 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7802 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7803 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7804 #include "clang/Basic/BuiltinsXCore.def" 7805 }; 7806 7807 // x86_32 Android target 7808 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7809 public: 7810 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7811 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 7812 SuitableAlign = 32; 7813 LongDoubleWidth = 64; 7814 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7815 } 7816 }; 7817 7818 // x86_64 Android target 7819 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7820 public: 7821 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7822 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 7823 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7824 } 7825 7826 bool useFloat128ManglingForLongDouble() const override { 7827 return true; 7828 } 7829 }; 7830 } // end anonymous namespace 7831 7832 //===----------------------------------------------------------------------===// 7833 // Driver code 7834 //===----------------------------------------------------------------------===// 7835 7836 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 7837 const TargetOptions &Opts) { 7838 llvm::Triple::OSType os = Triple.getOS(); 7839 7840 switch (Triple.getArch()) { 7841 default: 7842 return nullptr; 7843 7844 case llvm::Triple::xcore: 7845 return new XCoreTargetInfo(Triple, Opts); 7846 7847 case llvm::Triple::hexagon: 7848 return new HexagonTargetInfo(Triple, Opts); 7849 7850 case llvm::Triple::lanai: 7851 return new LanaiTargetInfo(Triple, Opts); 7852 7853 case llvm::Triple::aarch64: 7854 if (Triple.isOSDarwin()) 7855 return new DarwinAArch64TargetInfo(Triple, Opts); 7856 7857 switch (os) { 7858 case llvm::Triple::CloudABI: 7859 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 7860 case llvm::Triple::FreeBSD: 7861 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 7862 case llvm::Triple::Linux: 7863 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 7864 case llvm::Triple::NetBSD: 7865 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 7866 default: 7867 return new AArch64leTargetInfo(Triple, Opts); 7868 } 7869 7870 case llvm::Triple::aarch64_be: 7871 switch (os) { 7872 case llvm::Triple::FreeBSD: 7873 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 7874 case llvm::Triple::Linux: 7875 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 7876 case llvm::Triple::NetBSD: 7877 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 7878 default: 7879 return new AArch64beTargetInfo(Triple, Opts); 7880 } 7881 7882 case llvm::Triple::arm: 7883 case llvm::Triple::thumb: 7884 if (Triple.isOSBinFormatMachO()) 7885 return new DarwinARMTargetInfo(Triple, Opts); 7886 7887 switch (os) { 7888 case llvm::Triple::Linux: 7889 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 7890 case llvm::Triple::FreeBSD: 7891 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 7892 case llvm::Triple::NetBSD: 7893 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 7894 case llvm::Triple::OpenBSD: 7895 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 7896 case llvm::Triple::Bitrig: 7897 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 7898 case llvm::Triple::RTEMS: 7899 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 7900 case llvm::Triple::NaCl: 7901 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 7902 case llvm::Triple::Win32: 7903 switch (Triple.getEnvironment()) { 7904 case llvm::Triple::Cygnus: 7905 return new CygwinARMTargetInfo(Triple, Opts); 7906 case llvm::Triple::GNU: 7907 return new MinGWARMTargetInfo(Triple, Opts); 7908 case llvm::Triple::Itanium: 7909 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 7910 case llvm::Triple::MSVC: 7911 default: // Assume MSVC for unknown environments 7912 return new MicrosoftARMleTargetInfo(Triple, Opts); 7913 } 7914 default: 7915 return new ARMleTargetInfo(Triple, Opts); 7916 } 7917 7918 case llvm::Triple::armeb: 7919 case llvm::Triple::thumbeb: 7920 if (Triple.isOSDarwin()) 7921 return new DarwinARMTargetInfo(Triple, Opts); 7922 7923 switch (os) { 7924 case llvm::Triple::Linux: 7925 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 7926 case llvm::Triple::FreeBSD: 7927 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 7928 case llvm::Triple::NetBSD: 7929 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 7930 case llvm::Triple::OpenBSD: 7931 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 7932 case llvm::Triple::Bitrig: 7933 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 7934 case llvm::Triple::RTEMS: 7935 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 7936 case llvm::Triple::NaCl: 7937 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 7938 default: 7939 return new ARMbeTargetInfo(Triple, Opts); 7940 } 7941 7942 case llvm::Triple::bpfeb: 7943 case llvm::Triple::bpfel: 7944 return new BPFTargetInfo(Triple, Opts); 7945 7946 case llvm::Triple::msp430: 7947 return new MSP430TargetInfo(Triple, Opts); 7948 7949 case llvm::Triple::mips: 7950 switch (os) { 7951 case llvm::Triple::Linux: 7952 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 7953 case llvm::Triple::RTEMS: 7954 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 7955 case llvm::Triple::FreeBSD: 7956 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 7957 case llvm::Triple::NetBSD: 7958 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 7959 default: 7960 return new Mips32EBTargetInfo(Triple, Opts); 7961 } 7962 7963 case llvm::Triple::mipsel: 7964 switch (os) { 7965 case llvm::Triple::Linux: 7966 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 7967 case llvm::Triple::RTEMS: 7968 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 7969 case llvm::Triple::FreeBSD: 7970 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 7971 case llvm::Triple::NetBSD: 7972 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 7973 case llvm::Triple::NaCl: 7974 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple, Opts); 7975 default: 7976 return new Mips32ELTargetInfo(Triple, Opts); 7977 } 7978 7979 case llvm::Triple::mips64: 7980 switch (os) { 7981 case llvm::Triple::Linux: 7982 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 7983 case llvm::Triple::RTEMS: 7984 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 7985 case llvm::Triple::FreeBSD: 7986 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 7987 case llvm::Triple::NetBSD: 7988 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 7989 case llvm::Triple::OpenBSD: 7990 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 7991 default: 7992 return new Mips64EBTargetInfo(Triple, Opts); 7993 } 7994 7995 case llvm::Triple::mips64el: 7996 switch (os) { 7997 case llvm::Triple::Linux: 7998 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 7999 case llvm::Triple::RTEMS: 8000 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8001 case llvm::Triple::FreeBSD: 8002 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8003 case llvm::Triple::NetBSD: 8004 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8005 case llvm::Triple::OpenBSD: 8006 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8007 default: 8008 return new Mips64ELTargetInfo(Triple, Opts); 8009 } 8010 8011 case llvm::Triple::le32: 8012 switch (os) { 8013 case llvm::Triple::NaCl: 8014 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8015 default: 8016 return nullptr; 8017 } 8018 8019 case llvm::Triple::le64: 8020 return new Le64TargetInfo(Triple, Opts); 8021 8022 case llvm::Triple::ppc: 8023 if (Triple.isOSDarwin()) 8024 return new DarwinPPC32TargetInfo(Triple, Opts); 8025 switch (os) { 8026 case llvm::Triple::Linux: 8027 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8028 case llvm::Triple::FreeBSD: 8029 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8030 case llvm::Triple::NetBSD: 8031 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8032 case llvm::Triple::OpenBSD: 8033 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8034 case llvm::Triple::RTEMS: 8035 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8036 default: 8037 return new PPC32TargetInfo(Triple, Opts); 8038 } 8039 8040 case llvm::Triple::ppc64: 8041 if (Triple.isOSDarwin()) 8042 return new DarwinPPC64TargetInfo(Triple, Opts); 8043 switch (os) { 8044 case llvm::Triple::Linux: 8045 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8046 case llvm::Triple::Lv2: 8047 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8048 case llvm::Triple::FreeBSD: 8049 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8050 case llvm::Triple::NetBSD: 8051 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8052 default: 8053 return new PPC64TargetInfo(Triple, Opts); 8054 } 8055 8056 case llvm::Triple::ppc64le: 8057 switch (os) { 8058 case llvm::Triple::Linux: 8059 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8060 case llvm::Triple::NetBSD: 8061 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8062 default: 8063 return new PPC64TargetInfo(Triple, Opts); 8064 } 8065 8066 case llvm::Triple::nvptx: 8067 return new NVPTX32TargetInfo(Triple, Opts); 8068 case llvm::Triple::nvptx64: 8069 return new NVPTX64TargetInfo(Triple, Opts); 8070 8071 case llvm::Triple::amdgcn: 8072 case llvm::Triple::r600: 8073 return new AMDGPUTargetInfo(Triple, Opts); 8074 8075 case llvm::Triple::sparc: 8076 switch (os) { 8077 case llvm::Triple::Linux: 8078 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8079 case llvm::Triple::Solaris: 8080 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8081 case llvm::Triple::NetBSD: 8082 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8083 case llvm::Triple::OpenBSD: 8084 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8085 case llvm::Triple::RTEMS: 8086 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8087 default: 8088 return new SparcV8TargetInfo(Triple, Opts); 8089 } 8090 8091 // The 'sparcel' architecture copies all the above cases except for Solaris. 8092 case llvm::Triple::sparcel: 8093 switch (os) { 8094 case llvm::Triple::Linux: 8095 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8096 case llvm::Triple::NetBSD: 8097 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8098 case llvm::Triple::OpenBSD: 8099 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8100 case llvm::Triple::RTEMS: 8101 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8102 default: 8103 return new SparcV8elTargetInfo(Triple, Opts); 8104 } 8105 8106 case llvm::Triple::sparcv9: 8107 switch (os) { 8108 case llvm::Triple::Linux: 8109 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8110 case llvm::Triple::Solaris: 8111 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8112 case llvm::Triple::NetBSD: 8113 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8114 case llvm::Triple::OpenBSD: 8115 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8116 case llvm::Triple::FreeBSD: 8117 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8118 default: 8119 return new SparcV9TargetInfo(Triple, Opts); 8120 } 8121 8122 case llvm::Triple::systemz: 8123 switch (os) { 8124 case llvm::Triple::Linux: 8125 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8126 default: 8127 return new SystemZTargetInfo(Triple, Opts); 8128 } 8129 8130 case llvm::Triple::tce: 8131 return new TCETargetInfo(Triple, Opts); 8132 8133 case llvm::Triple::x86: 8134 if (Triple.isOSDarwin()) 8135 return new DarwinI386TargetInfo(Triple, Opts); 8136 8137 switch (os) { 8138 case llvm::Triple::CloudABI: 8139 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8140 case llvm::Triple::Linux: { 8141 switch (Triple.getEnvironment()) { 8142 default: 8143 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8144 case llvm::Triple::Android: 8145 return new AndroidX86_32TargetInfo(Triple, Opts); 8146 } 8147 } 8148 case llvm::Triple::DragonFly: 8149 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8150 case llvm::Triple::NetBSD: 8151 return new NetBSDI386TargetInfo(Triple, Opts); 8152 case llvm::Triple::OpenBSD: 8153 return new OpenBSDI386TargetInfo(Triple, Opts); 8154 case llvm::Triple::Bitrig: 8155 return new BitrigI386TargetInfo(Triple, Opts); 8156 case llvm::Triple::FreeBSD: 8157 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8158 case llvm::Triple::KFreeBSD: 8159 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8160 case llvm::Triple::Minix: 8161 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8162 case llvm::Triple::Solaris: 8163 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8164 case llvm::Triple::Win32: { 8165 switch (Triple.getEnvironment()) { 8166 case llvm::Triple::Cygnus: 8167 return new CygwinX86_32TargetInfo(Triple, Opts); 8168 case llvm::Triple::GNU: 8169 return new MinGWX86_32TargetInfo(Triple, Opts); 8170 case llvm::Triple::Itanium: 8171 case llvm::Triple::MSVC: 8172 default: // Assume MSVC for unknown environments 8173 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8174 } 8175 } 8176 case llvm::Triple::Haiku: 8177 return new HaikuX86_32TargetInfo(Triple, Opts); 8178 case llvm::Triple::RTEMS: 8179 return new RTEMSX86_32TargetInfo(Triple, Opts); 8180 case llvm::Triple::NaCl: 8181 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8182 case llvm::Triple::ELFIAMCU: 8183 return new MCUX86_32TargetInfo(Triple, Opts); 8184 default: 8185 return new X86_32TargetInfo(Triple, Opts); 8186 } 8187 8188 case llvm::Triple::x86_64: 8189 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8190 return new DarwinX86_64TargetInfo(Triple, Opts); 8191 8192 switch (os) { 8193 case llvm::Triple::CloudABI: 8194 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8195 case llvm::Triple::Linux: { 8196 switch (Triple.getEnvironment()) { 8197 default: 8198 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8199 case llvm::Triple::Android: 8200 return new AndroidX86_64TargetInfo(Triple, Opts); 8201 } 8202 } 8203 case llvm::Triple::DragonFly: 8204 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8205 case llvm::Triple::NetBSD: 8206 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8207 case llvm::Triple::OpenBSD: 8208 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8209 case llvm::Triple::Bitrig: 8210 return new BitrigX86_64TargetInfo(Triple, Opts); 8211 case llvm::Triple::FreeBSD: 8212 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8213 case llvm::Triple::KFreeBSD: 8214 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8215 case llvm::Triple::Solaris: 8216 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8217 case llvm::Triple::Win32: { 8218 switch (Triple.getEnvironment()) { 8219 case llvm::Triple::Cygnus: 8220 return new CygwinX86_64TargetInfo(Triple, Opts); 8221 case llvm::Triple::GNU: 8222 return new MinGWX86_64TargetInfo(Triple, Opts); 8223 case llvm::Triple::MSVC: 8224 default: // Assume MSVC for unknown environments 8225 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8226 } 8227 } 8228 case llvm::Triple::NaCl: 8229 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8230 case llvm::Triple::PS4: 8231 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8232 default: 8233 return new X86_64TargetInfo(Triple, Opts); 8234 } 8235 8236 case llvm::Triple::spir: { 8237 if (Triple.getOS() != llvm::Triple::UnknownOS || 8238 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8239 return nullptr; 8240 return new SPIR32TargetInfo(Triple, Opts); 8241 } 8242 case llvm::Triple::spir64: { 8243 if (Triple.getOS() != llvm::Triple::UnknownOS || 8244 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8245 return nullptr; 8246 return new SPIR64TargetInfo(Triple, Opts); 8247 } 8248 case llvm::Triple::wasm32: 8249 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8250 return nullptr; 8251 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8252 case llvm::Triple::wasm64: 8253 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8254 return nullptr; 8255 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8256 } 8257 } 8258 8259 /// CreateTargetInfo - Return the target info object for the specified target 8260 /// options. 8261 TargetInfo * 8262 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8263 const std::shared_ptr<TargetOptions> &Opts) { 8264 llvm::Triple Triple(Opts->Triple); 8265 8266 // Construct the target 8267 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8268 if (!Target) { 8269 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8270 return nullptr; 8271 } 8272 Target->TargetOpts = Opts; 8273 8274 // Set the target CPU if specified. 8275 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8276 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8277 return nullptr; 8278 } 8279 8280 // Set the target ABI if specified. 8281 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8282 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8283 return nullptr; 8284 } 8285 8286 // Set the fp math unit. 8287 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8288 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8289 return nullptr; 8290 } 8291 8292 // Compute the default target features, we need the target to handle this 8293 // because features may have dependencies on one another. 8294 llvm::StringMap<bool> Features; 8295 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8296 Opts->FeaturesAsWritten)) 8297 return nullptr; 8298 8299 // Add the features to the compile options. 8300 Opts->Features.clear(); 8301 for (const auto &F : Features) 8302 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8303 8304 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8305 return nullptr; 8306 8307 return Target.release(); 8308 } 8309