1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/TargetParser.h" 31 #include <algorithm> 32 #include <memory> 33 using namespace clang; 34 35 //===----------------------------------------------------------------------===// 36 // Common code shared among targets. 37 //===----------------------------------------------------------------------===// 38 39 /// DefineStd - Define a macro name and standard variants. For example if 40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 41 /// when in GNU mode. 42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 43 const LangOptions &Opts) { 44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 45 46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 47 // in the user's namespace. 48 if (Opts.GNUMode) 49 Builder.defineMacro(MacroName); 50 51 // Define __unix. 52 Builder.defineMacro("__" + MacroName); 53 54 // Define __unix__. 55 Builder.defineMacro("__" + MacroName + "__"); 56 } 57 58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 59 bool Tuning = true) { 60 Builder.defineMacro("__" + CPUName); 61 Builder.defineMacro("__" + CPUName + "__"); 62 if (Tuning) 63 Builder.defineMacro("__tune_" + CPUName + "__"); 64 } 65 66 //===----------------------------------------------------------------------===// 67 // Defines specific to certain operating systems. 68 //===----------------------------------------------------------------------===// 69 70 namespace { 71 template<typename TgtInfo> 72 class OSTargetInfo : public TgtInfo { 73 protected: 74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 75 MacroBuilder &Builder) const=0; 76 public: 77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 78 void getTargetDefines(const LangOptions &Opts, 79 MacroBuilder &Builder) const override { 80 TgtInfo::getTargetDefines(Opts, Builder); 81 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 82 } 83 84 }; 85 } // end anonymous namespace 86 87 88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 89 const llvm::Triple &Triple, 90 StringRef &PlatformName, 91 VersionTuple &PlatformMinVersion) { 92 Builder.defineMacro("__APPLE_CC__", "6000"); 93 Builder.defineMacro("__APPLE__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.has(SanitizerKind::Address)) 98 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 99 100 if (!Opts.ObjCAutoRefCount) { 101 // __weak is always defined, for use in blocks and with objc pointers. 102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 103 104 // Darwin defines __strong even in C mode (just to nothing). 105 if (Opts.getGC() != LangOptions::NonGC) 106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 107 else 108 Builder.defineMacro("__strong", ""); 109 110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 111 // allow this in C, since one might have block pointers in structs that 112 // are used in pure C code and in Objective-C ARC. 113 Builder.defineMacro("__unsafe_unretained", ""); 114 } 115 116 if (Opts.Static) 117 Builder.defineMacro("__STATIC__"); 118 else 119 Builder.defineMacro("__DYNAMIC__"); 120 121 if (Opts.POSIXThreads) 122 Builder.defineMacro("_REENTRANT"); 123 124 // Get the platform type and version number from the triple. 125 unsigned Maj, Min, Rev; 126 if (Triple.isMacOSX()) { 127 Triple.getMacOSXVersion(Maj, Min, Rev); 128 PlatformName = "macosx"; 129 } else { 130 Triple.getOSVersion(Maj, Min, Rev); 131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 132 } 133 134 // If -target arch-pc-win32-macho option specified, we're 135 // generating code for Win32 ABI. No need to emit 136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 137 if (PlatformName == "win32") { 138 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 139 return; 140 } 141 142 // Set the appropriate OS version define. 143 if (Triple.isiOS()) { 144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 145 char Str[6]; 146 Str[0] = '0' + Maj; 147 Str[1] = '0' + (Min / 10); 148 Str[2] = '0' + (Min % 10); 149 Str[3] = '0' + (Rev / 10); 150 Str[4] = '0' + (Rev % 10); 151 Str[5] = '\0'; 152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 153 Str); 154 } else if (Triple.isMacOSX()) { 155 // Note that the Driver allows versions which aren't representable in the 156 // define (because we only get a single digit for the minor and micro 157 // revision numbers). So, we limit them to the maximum representable 158 // version. 159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 160 char Str[7]; 161 if (Maj < 10 || (Maj == 10 && Min < 10)) { 162 Str[0] = '0' + (Maj / 10); 163 Str[1] = '0' + (Maj % 10); 164 Str[2] = '0' + std::min(Min, 9U); 165 Str[3] = '0' + std::min(Rev, 9U); 166 Str[4] = '\0'; 167 } else { 168 // Handle versions > 10.9. 169 Str[0] = '0' + (Maj / 10); 170 Str[1] = '0' + (Maj % 10); 171 Str[2] = '0' + (Min / 10); 172 Str[3] = '0' + (Min % 10); 173 Str[4] = '0' + (Rev / 10); 174 Str[5] = '0' + (Rev % 10); 175 Str[6] = '\0'; 176 } 177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 178 } 179 180 // Tell users about the kernel if there is one. 181 if (Triple.isOSDarwin()) 182 Builder.defineMacro("__MACH__"); 183 184 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 185 } 186 187 namespace { 188 // CloudABI Target 189 template <typename Target> 190 class CloudABITargetInfo : public OSTargetInfo<Target> { 191 protected: 192 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 193 MacroBuilder &Builder) const override { 194 Builder.defineMacro("__CloudABI__"); 195 Builder.defineMacro("__ELF__"); 196 197 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 198 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 199 Builder.defineMacro("__STDC_UTF_16__"); 200 Builder.defineMacro("__STDC_UTF_32__"); 201 } 202 203 public: 204 CloudABITargetInfo(const llvm::Triple &Triple) 205 : OSTargetInfo<Target>(Triple) { 206 this->UserLabelPrefix = ""; 207 } 208 }; 209 210 template<typename Target> 211 class DarwinTargetInfo : public OSTargetInfo<Target> { 212 protected: 213 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 214 MacroBuilder &Builder) const override { 215 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 216 this->PlatformMinVersion); 217 } 218 219 public: 220 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 221 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 222 this->MCountName = "\01mcount"; 223 } 224 225 std::string isValidSectionSpecifier(StringRef SR) const override { 226 // Let MCSectionMachO validate this. 227 StringRef Segment, Section; 228 unsigned TAA, StubSize; 229 bool HasTAA; 230 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 231 TAA, HasTAA, StubSize); 232 } 233 234 const char *getStaticInitSectionSpecifier() const override { 235 // FIXME: We should return 0 when building kexts. 236 return "__TEXT,__StaticInit,regular,pure_instructions"; 237 } 238 239 /// Darwin does not support protected visibility. Darwin's "default" 240 /// is very similar to ELF's "protected"; Darwin requires a "weak" 241 /// attribute on declarations that can be dynamically replaced. 242 bool hasProtectedVisibility() const override { 243 return false; 244 } 245 }; 246 247 248 // DragonFlyBSD Target 249 template<typename Target> 250 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 251 protected: 252 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 253 MacroBuilder &Builder) const override { 254 // DragonFly defines; list based off of gcc output 255 Builder.defineMacro("__DragonFly__"); 256 Builder.defineMacro("__DragonFly_cc_version", "100001"); 257 Builder.defineMacro("__ELF__"); 258 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 259 Builder.defineMacro("__tune_i386__"); 260 DefineStd(Builder, "unix", Opts); 261 } 262 public: 263 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 264 : OSTargetInfo<Target>(Triple) { 265 this->UserLabelPrefix = ""; 266 267 switch (Triple.getArch()) { 268 default: 269 case llvm::Triple::x86: 270 case llvm::Triple::x86_64: 271 this->MCountName = ".mcount"; 272 break; 273 } 274 } 275 }; 276 277 // FreeBSD Target 278 template<typename Target> 279 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 280 protected: 281 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 282 MacroBuilder &Builder) const override { 283 // FreeBSD defines; list based off of gcc output 284 285 unsigned Release = Triple.getOSMajorVersion(); 286 if (Release == 0U) 287 Release = 8; 288 289 Builder.defineMacro("__FreeBSD__", Twine(Release)); 290 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 291 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 292 DefineStd(Builder, "unix", Opts); 293 Builder.defineMacro("__ELF__"); 294 295 // On FreeBSD, wchar_t contains the number of the code point as 296 // used by the character set of the locale. These character sets are 297 // not necessarily a superset of ASCII. 298 // 299 // FIXME: This is wrong; the macro refers to the numerical values 300 // of wchar_t *literals*, which are not locale-dependent. However, 301 // FreeBSD systems apparently depend on us getting this wrong, and 302 // setting this to 1 is conforming even if all the basic source 303 // character literals have the same encoding as char and wchar_t. 304 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 305 } 306 public: 307 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 310 switch (Triple.getArch()) { 311 default: 312 case llvm::Triple::x86: 313 case llvm::Triple::x86_64: 314 this->MCountName = ".mcount"; 315 break; 316 case llvm::Triple::mips: 317 case llvm::Triple::mipsel: 318 case llvm::Triple::ppc: 319 case llvm::Triple::ppc64: 320 case llvm::Triple::ppc64le: 321 this->MCountName = "_mcount"; 322 break; 323 case llvm::Triple::arm: 324 this->MCountName = "__mcount"; 325 break; 326 } 327 } 328 }; 329 330 // GNU/kFreeBSD Target 331 template<typename Target> 332 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 333 protected: 334 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 335 MacroBuilder &Builder) const override { 336 // GNU/kFreeBSD defines; list based off of gcc output 337 338 DefineStd(Builder, "unix", Opts); 339 Builder.defineMacro("__FreeBSD_kernel__"); 340 Builder.defineMacro("__GLIBC__"); 341 Builder.defineMacro("__ELF__"); 342 if (Opts.POSIXThreads) 343 Builder.defineMacro("_REENTRANT"); 344 if (Opts.CPlusPlus) 345 Builder.defineMacro("_GNU_SOURCE"); 346 } 347 public: 348 KFreeBSDTargetInfo(const llvm::Triple &Triple) 349 : OSTargetInfo<Target>(Triple) { 350 this->UserLabelPrefix = ""; 351 } 352 }; 353 354 // Minix Target 355 template<typename Target> 356 class MinixTargetInfo : public OSTargetInfo<Target> { 357 protected: 358 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 359 MacroBuilder &Builder) const override { 360 // Minix defines 361 362 Builder.defineMacro("__minix", "3"); 363 Builder.defineMacro("_EM_WSIZE", "4"); 364 Builder.defineMacro("_EM_PSIZE", "4"); 365 Builder.defineMacro("_EM_SSIZE", "2"); 366 Builder.defineMacro("_EM_LSIZE", "4"); 367 Builder.defineMacro("_EM_FSIZE", "4"); 368 Builder.defineMacro("_EM_DSIZE", "8"); 369 Builder.defineMacro("__ELF__"); 370 DefineStd(Builder, "unix", Opts); 371 } 372 public: 373 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 374 this->UserLabelPrefix = ""; 375 } 376 }; 377 378 // Linux target 379 template<typename Target> 380 class LinuxTargetInfo : public OSTargetInfo<Target> { 381 protected: 382 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 383 MacroBuilder &Builder) const override { 384 // Linux defines; list based off of gcc output 385 DefineStd(Builder, "unix", Opts); 386 DefineStd(Builder, "linux", Opts); 387 Builder.defineMacro("__gnu_linux__"); 388 Builder.defineMacro("__ELF__"); 389 if (Triple.getEnvironment() == llvm::Triple::Android) { 390 Builder.defineMacro("__ANDROID__", "1"); 391 unsigned Maj, Min, Rev; 392 Triple.getEnvironmentVersion(Maj, Min, Rev); 393 this->PlatformName = "android"; 394 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 395 } 396 if (Opts.POSIXThreads) 397 Builder.defineMacro("_REENTRANT"); 398 if (Opts.CPlusPlus) 399 Builder.defineMacro("_GNU_SOURCE"); 400 } 401 public: 402 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 403 this->UserLabelPrefix = ""; 404 this->WIntType = TargetInfo::UnsignedInt; 405 406 switch (Triple.getArch()) { 407 default: 408 break; 409 case llvm::Triple::ppc: 410 case llvm::Triple::ppc64: 411 case llvm::Triple::ppc64le: 412 this->MCountName = "_mcount"; 413 break; 414 } 415 } 416 417 const char *getStaticInitSectionSpecifier() const override { 418 return ".text.startup"; 419 } 420 }; 421 422 // NetBSD Target 423 template<typename Target> 424 class NetBSDTargetInfo : public OSTargetInfo<Target> { 425 protected: 426 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 427 MacroBuilder &Builder) const override { 428 // NetBSD defines; list based off of gcc output 429 Builder.defineMacro("__NetBSD__"); 430 Builder.defineMacro("__unix__"); 431 Builder.defineMacro("__ELF__"); 432 if (Opts.POSIXThreads) 433 Builder.defineMacro("_POSIX_THREADS"); 434 435 switch (Triple.getArch()) { 436 default: 437 break; 438 case llvm::Triple::arm: 439 case llvm::Triple::armeb: 440 case llvm::Triple::thumb: 441 case llvm::Triple::thumbeb: 442 Builder.defineMacro("__ARM_DWARF_EH__"); 443 break; 444 } 445 } 446 public: 447 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 448 this->UserLabelPrefix = ""; 449 this->MCountName = "_mcount"; 450 } 451 }; 452 453 // OpenBSD Target 454 template<typename Target> 455 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 456 protected: 457 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 458 MacroBuilder &Builder) const override { 459 // OpenBSD defines; list based off of gcc output 460 461 Builder.defineMacro("__OpenBSD__"); 462 DefineStd(Builder, "unix", Opts); 463 Builder.defineMacro("__ELF__"); 464 if (Opts.POSIXThreads) 465 Builder.defineMacro("_REENTRANT"); 466 } 467 public: 468 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 469 this->UserLabelPrefix = ""; 470 this->TLSSupported = false; 471 472 switch (Triple.getArch()) { 473 default: 474 case llvm::Triple::x86: 475 case llvm::Triple::x86_64: 476 case llvm::Triple::arm: 477 case llvm::Triple::sparc: 478 this->MCountName = "__mcount"; 479 break; 480 case llvm::Triple::mips64: 481 case llvm::Triple::mips64el: 482 case llvm::Triple::ppc: 483 case llvm::Triple::sparcv9: 484 this->MCountName = "_mcount"; 485 break; 486 } 487 } 488 }; 489 490 // Bitrig Target 491 template<typename Target> 492 class BitrigTargetInfo : public OSTargetInfo<Target> { 493 protected: 494 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 495 MacroBuilder &Builder) const override { 496 // Bitrig defines; list based off of gcc output 497 498 Builder.defineMacro("__Bitrig__"); 499 DefineStd(Builder, "unix", Opts); 500 Builder.defineMacro("__ELF__"); 501 if (Opts.POSIXThreads) 502 Builder.defineMacro("_REENTRANT"); 503 504 switch (Triple.getArch()) { 505 default: 506 break; 507 case llvm::Triple::arm: 508 case llvm::Triple::armeb: 509 case llvm::Triple::thumb: 510 case llvm::Triple::thumbeb: 511 Builder.defineMacro("__ARM_DWARF_EH__"); 512 break; 513 } 514 } 515 public: 516 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 517 this->UserLabelPrefix = ""; 518 this->MCountName = "__mcount"; 519 } 520 }; 521 522 // PSP Target 523 template<typename Target> 524 class PSPTargetInfo : public OSTargetInfo<Target> { 525 protected: 526 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 527 MacroBuilder &Builder) const override { 528 // PSP defines; list based on the output of the pspdev gcc toolchain. 529 Builder.defineMacro("PSP"); 530 Builder.defineMacro("_PSP"); 531 Builder.defineMacro("__psp__"); 532 Builder.defineMacro("__ELF__"); 533 } 534 public: 535 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 536 this->UserLabelPrefix = ""; 537 } 538 }; 539 540 // PS3 PPU Target 541 template<typename Target> 542 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 543 protected: 544 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 545 MacroBuilder &Builder) const override { 546 // PS3 PPU defines. 547 Builder.defineMacro("__PPC__"); 548 Builder.defineMacro("__PPU__"); 549 Builder.defineMacro("__CELLOS_LV2__"); 550 Builder.defineMacro("__ELF__"); 551 Builder.defineMacro("__LP32__"); 552 Builder.defineMacro("_ARCH_PPC64"); 553 Builder.defineMacro("__powerpc64__"); 554 } 555 public: 556 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 557 this->UserLabelPrefix = ""; 558 this->LongWidth = this->LongAlign = 32; 559 this->PointerWidth = this->PointerAlign = 32; 560 this->IntMaxType = TargetInfo::SignedLongLong; 561 this->Int64Type = TargetInfo::SignedLongLong; 562 this->SizeType = TargetInfo::UnsignedInt; 563 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 564 } 565 }; 566 567 template <typename Target> 568 class PS4OSTargetInfo : public OSTargetInfo<Target> { 569 protected: 570 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 571 MacroBuilder &Builder) const override { 572 Builder.defineMacro("__FreeBSD__", "9"); 573 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 574 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 575 DefineStd(Builder, "unix", Opts); 576 Builder.defineMacro("__ELF__"); 577 Builder.defineMacro("__PS4__"); 578 } 579 public: 580 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 581 this->WCharType = this->UnsignedShort; 582 583 this->UserLabelPrefix = ""; 584 585 switch (Triple.getArch()) { 586 default: 587 case llvm::Triple::x86_64: 588 this->MCountName = ".mcount"; 589 break; 590 } 591 } 592 }; 593 594 // Solaris target 595 template<typename Target> 596 class SolarisTargetInfo : public OSTargetInfo<Target> { 597 protected: 598 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 599 MacroBuilder &Builder) const override { 600 DefineStd(Builder, "sun", Opts); 601 DefineStd(Builder, "unix", Opts); 602 Builder.defineMacro("__ELF__"); 603 Builder.defineMacro("__svr4__"); 604 Builder.defineMacro("__SVR4"); 605 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 606 // newer, but to 500 for everything else. feature_test.h has a check to 607 // ensure that you are not using C99 with an old version of X/Open or C89 608 // with a new version. 609 if (Opts.C99) 610 Builder.defineMacro("_XOPEN_SOURCE", "600"); 611 else 612 Builder.defineMacro("_XOPEN_SOURCE", "500"); 613 if (Opts.CPlusPlus) 614 Builder.defineMacro("__C99FEATURES__"); 615 Builder.defineMacro("_LARGEFILE_SOURCE"); 616 Builder.defineMacro("_LARGEFILE64_SOURCE"); 617 Builder.defineMacro("__EXTENSIONS__"); 618 Builder.defineMacro("_REENTRANT"); 619 } 620 public: 621 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 622 this->UserLabelPrefix = ""; 623 this->WCharType = this->SignedInt; 624 // FIXME: WIntType should be SignedLong 625 } 626 }; 627 628 // Windows target 629 template<typename Target> 630 class WindowsTargetInfo : public OSTargetInfo<Target> { 631 protected: 632 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 633 MacroBuilder &Builder) const override { 634 Builder.defineMacro("_WIN32"); 635 } 636 void getVisualStudioDefines(const LangOptions &Opts, 637 MacroBuilder &Builder) const { 638 if (Opts.CPlusPlus) { 639 if (Opts.RTTIData) 640 Builder.defineMacro("_CPPRTTI"); 641 642 if (Opts.CXXExceptions) 643 Builder.defineMacro("_CPPUNWIND"); 644 } 645 646 if (!Opts.CharIsSigned) 647 Builder.defineMacro("_CHAR_UNSIGNED"); 648 649 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 650 // but it works for now. 651 if (Opts.POSIXThreads) 652 Builder.defineMacro("_MT"); 653 654 if (Opts.MSCompatibilityVersion) { 655 Builder.defineMacro("_MSC_VER", 656 Twine(Opts.MSCompatibilityVersion / 100000)); 657 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 658 // FIXME We cannot encode the revision information into 32-bits 659 Builder.defineMacro("_MSC_BUILD", Twine(1)); 660 661 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 662 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 663 } 664 665 if (Opts.MicrosoftExt) { 666 Builder.defineMacro("_MSC_EXTENSIONS"); 667 668 if (Opts.CPlusPlus11) { 669 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 670 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 671 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 672 } 673 } 674 675 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 676 } 677 678 public: 679 WindowsTargetInfo(const llvm::Triple &Triple) 680 : OSTargetInfo<Target>(Triple) {} 681 }; 682 683 template <typename Target> 684 class NaClTargetInfo : public OSTargetInfo<Target> { 685 protected: 686 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 687 MacroBuilder &Builder) const override { 688 if (Opts.POSIXThreads) 689 Builder.defineMacro("_REENTRANT"); 690 if (Opts.CPlusPlus) 691 Builder.defineMacro("_GNU_SOURCE"); 692 693 DefineStd(Builder, "unix", Opts); 694 Builder.defineMacro("__ELF__"); 695 Builder.defineMacro("__native_client__"); 696 } 697 698 public: 699 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 700 this->UserLabelPrefix = ""; 701 this->LongAlign = 32; 702 this->LongWidth = 32; 703 this->PointerAlign = 32; 704 this->PointerWidth = 32; 705 this->IntMaxType = TargetInfo::SignedLongLong; 706 this->Int64Type = TargetInfo::SignedLongLong; 707 this->DoubleAlign = 64; 708 this->LongDoubleWidth = 64; 709 this->LongDoubleAlign = 64; 710 this->LongLongWidth = 64; 711 this->LongLongAlign = 64; 712 this->SizeType = TargetInfo::UnsignedInt; 713 this->PtrDiffType = TargetInfo::SignedInt; 714 this->IntPtrType = TargetInfo::SignedInt; 715 // RegParmMax is inherited from the underlying architecture 716 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 717 if (Triple.getArch() == llvm::Triple::arm) { 718 // Handled in ARM's setABI(). 719 } else if (Triple.getArch() == llvm::Triple::x86) { 720 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 721 } else if (Triple.getArch() == llvm::Triple::x86_64) { 722 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 723 } else if (Triple.getArch() == llvm::Triple::mipsel) { 724 // Handled on mips' setDescriptionString. 725 } else { 726 assert(Triple.getArch() == llvm::Triple::le32); 727 this->DescriptionString = "e-p:32:32-i64:64"; 728 } 729 } 730 }; 731 732 //===----------------------------------------------------------------------===// 733 // Specific target implementations. 734 //===----------------------------------------------------------------------===// 735 736 // PPC abstract base class 737 class PPCTargetInfo : public TargetInfo { 738 static const Builtin::Info BuiltinInfo[]; 739 static const char * const GCCRegNames[]; 740 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 741 std::string CPU; 742 743 // Target cpu features. 744 bool HasVSX; 745 bool HasP8Vector; 746 bool HasP8Crypto; 747 bool HasDirectMove; 748 bool HasQPX; 749 bool HasHTM; 750 bool HasBPERMD; 751 bool HasExtDiv; 752 753 protected: 754 std::string ABI; 755 756 public: 757 PPCTargetInfo(const llvm::Triple &Triple) 758 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 759 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 760 HasBPERMD(false), HasExtDiv(false) { 761 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 762 SimdDefaultAlign = 128; 763 LongDoubleWidth = LongDoubleAlign = 128; 764 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 765 } 766 767 /// \brief Flags for architecture specific defines. 768 typedef enum { 769 ArchDefineNone = 0, 770 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 771 ArchDefinePpcgr = 1 << 1, 772 ArchDefinePpcsq = 1 << 2, 773 ArchDefine440 = 1 << 3, 774 ArchDefine603 = 1 << 4, 775 ArchDefine604 = 1 << 5, 776 ArchDefinePwr4 = 1 << 6, 777 ArchDefinePwr5 = 1 << 7, 778 ArchDefinePwr5x = 1 << 8, 779 ArchDefinePwr6 = 1 << 9, 780 ArchDefinePwr6x = 1 << 10, 781 ArchDefinePwr7 = 1 << 11, 782 ArchDefinePwr8 = 1 << 12, 783 ArchDefineA2 = 1 << 13, 784 ArchDefineA2q = 1 << 14 785 } ArchDefineTypes; 786 787 // Note: GCC recognizes the following additional cpus: 788 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 789 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 790 // titan, rs64. 791 bool setCPU(const std::string &Name) override { 792 bool CPUKnown = llvm::StringSwitch<bool>(Name) 793 .Case("generic", true) 794 .Case("440", true) 795 .Case("450", true) 796 .Case("601", true) 797 .Case("602", true) 798 .Case("603", true) 799 .Case("603e", true) 800 .Case("603ev", true) 801 .Case("604", true) 802 .Case("604e", true) 803 .Case("620", true) 804 .Case("630", true) 805 .Case("g3", true) 806 .Case("7400", true) 807 .Case("g4", true) 808 .Case("7450", true) 809 .Case("g4+", true) 810 .Case("750", true) 811 .Case("970", true) 812 .Case("g5", true) 813 .Case("a2", true) 814 .Case("a2q", true) 815 .Case("e500mc", true) 816 .Case("e5500", true) 817 .Case("power3", true) 818 .Case("pwr3", true) 819 .Case("power4", true) 820 .Case("pwr4", true) 821 .Case("power5", true) 822 .Case("pwr5", true) 823 .Case("power5x", true) 824 .Case("pwr5x", true) 825 .Case("power6", true) 826 .Case("pwr6", true) 827 .Case("power6x", true) 828 .Case("pwr6x", true) 829 .Case("power7", true) 830 .Case("pwr7", true) 831 .Case("power8", true) 832 .Case("pwr8", true) 833 .Case("powerpc", true) 834 .Case("ppc", true) 835 .Case("powerpc64", true) 836 .Case("ppc64", true) 837 .Case("powerpc64le", true) 838 .Case("ppc64le", true) 839 .Default(false); 840 841 if (CPUKnown) 842 CPU = Name; 843 844 return CPUKnown; 845 } 846 847 848 StringRef getABI() const override { return ABI; } 849 850 void getTargetBuiltins(const Builtin::Info *&Records, 851 unsigned &NumRecords) const override { 852 Records = BuiltinInfo; 853 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 854 } 855 856 bool isCLZForZeroUndef() const override { return false; } 857 858 void getTargetDefines(const LangOptions &Opts, 859 MacroBuilder &Builder) const override; 860 861 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 862 863 bool handleTargetFeatures(std::vector<std::string> &Features, 864 DiagnosticsEngine &Diags) override; 865 bool hasFeature(StringRef Feature) const override; 866 867 void getGCCRegNames(const char * const *&Names, 868 unsigned &NumNames) const override; 869 void getGCCRegAliases(const GCCRegAlias *&Aliases, 870 unsigned &NumAliases) const override; 871 bool validateAsmConstraint(const char *&Name, 872 TargetInfo::ConstraintInfo &Info) const override { 873 switch (*Name) { 874 default: return false; 875 case 'O': // Zero 876 break; 877 case 'b': // Base register 878 case 'f': // Floating point register 879 Info.setAllowsRegister(); 880 break; 881 // FIXME: The following are added to allow parsing. 882 // I just took a guess at what the actions should be. 883 // Also, is more specific checking needed? I.e. specific registers? 884 case 'd': // Floating point register (containing 64-bit value) 885 case 'v': // Altivec vector register 886 Info.setAllowsRegister(); 887 break; 888 case 'w': 889 switch (Name[1]) { 890 case 'd':// VSX vector register to hold vector double data 891 case 'f':// VSX vector register to hold vector float data 892 case 's':// VSX vector register to hold scalar float data 893 case 'a':// Any VSX register 894 case 'c':// An individual CR bit 895 break; 896 default: 897 return false; 898 } 899 Info.setAllowsRegister(); 900 Name++; // Skip over 'w'. 901 break; 902 case 'h': // `MQ', `CTR', or `LINK' register 903 case 'q': // `MQ' register 904 case 'c': // `CTR' register 905 case 'l': // `LINK' register 906 case 'x': // `CR' register (condition register) number 0 907 case 'y': // `CR' register (condition register) 908 case 'z': // `XER[CA]' carry bit (part of the XER register) 909 Info.setAllowsRegister(); 910 break; 911 case 'I': // Signed 16-bit constant 912 case 'J': // Unsigned 16-bit constant shifted left 16 bits 913 // (use `L' instead for SImode constants) 914 case 'K': // Unsigned 16-bit constant 915 case 'L': // Signed 16-bit constant shifted left 16 bits 916 case 'M': // Constant larger than 31 917 case 'N': // Exact power of 2 918 case 'P': // Constant whose negation is a signed 16-bit constant 919 case 'G': // Floating point constant that can be loaded into a 920 // register with one instruction per word 921 case 'H': // Integer/Floating point constant that can be loaded 922 // into a register using three instructions 923 break; 924 case 'm': // Memory operand. Note that on PowerPC targets, m can 925 // include addresses that update the base register. It 926 // is therefore only safe to use `m' in an asm statement 927 // if that asm statement accesses the operand exactly once. 928 // The asm statement must also use `%U<opno>' as a 929 // placeholder for the "update" flag in the corresponding 930 // load or store instruction. For example: 931 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 932 // is correct but: 933 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 934 // is not. Use es rather than m if you don't want the base 935 // register to be updated. 936 case 'e': 937 if (Name[1] != 's') 938 return false; 939 // es: A "stable" memory operand; that is, one which does not 940 // include any automodification of the base register. Unlike 941 // `m', this constraint can be used in asm statements that 942 // might access the operand several times, or that might not 943 // access it at all. 944 Info.setAllowsMemory(); 945 Name++; // Skip over 'e'. 946 break; 947 case 'Q': // Memory operand that is an offset from a register (it is 948 // usually better to use `m' or `es' in asm statements) 949 case 'Z': // Memory operand that is an indexed or indirect from a 950 // register (it is usually better to use `m' or `es' in 951 // asm statements) 952 Info.setAllowsMemory(); 953 Info.setAllowsRegister(); 954 break; 955 case 'R': // AIX TOC entry 956 case 'a': // Address operand that is an indexed or indirect from a 957 // register (`p' is preferable for asm statements) 958 case 'S': // Constant suitable as a 64-bit mask operand 959 case 'T': // Constant suitable as a 32-bit mask operand 960 case 'U': // System V Release 4 small data area reference 961 case 't': // AND masks that can be performed by two rldic{l, r} 962 // instructions 963 case 'W': // Vector constant that does not require memory 964 case 'j': // Vector constant that is all zeros. 965 break; 966 // End FIXME. 967 } 968 return true; 969 } 970 std::string convertConstraint(const char *&Constraint) const override { 971 std::string R; 972 switch (*Constraint) { 973 case 'e': 974 case 'w': 975 // Two-character constraint; add "^" hint for later parsing. 976 R = std::string("^") + std::string(Constraint, 2); 977 Constraint++; 978 break; 979 default: 980 return TargetInfo::convertConstraint(Constraint); 981 } 982 return R; 983 } 984 const char *getClobbers() const override { 985 return ""; 986 } 987 int getEHDataRegisterNumber(unsigned RegNo) const override { 988 if (RegNo == 0) return 3; 989 if (RegNo == 1) return 4; 990 return -1; 991 } 992 993 bool hasSjLjLowering() const override { 994 return true; 995 } 996 997 bool useFloat128ManglingForLongDouble() const override { 998 return LongDoubleWidth == 128 && 999 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1000 getTriple().isOSBinFormatELF(); 1001 } 1002 }; 1003 1004 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1005 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1006 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1007 ALL_LANGUAGES }, 1008 #include "clang/Basic/BuiltinsPPC.def" 1009 }; 1010 1011 /// handleTargetFeatures - Perform initialization based on the user 1012 /// configured set of features. 1013 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1014 DiagnosticsEngine &Diags) { 1015 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 1016 // Ignore disabled features. 1017 if (Features[i][0] == '-') 1018 continue; 1019 1020 StringRef Feature = StringRef(Features[i]).substr(1); 1021 1022 if (Feature == "vsx") { 1023 HasVSX = true; 1024 continue; 1025 } 1026 1027 if (Feature == "bpermd") { 1028 HasBPERMD = true; 1029 continue; 1030 } 1031 1032 if (Feature == "extdiv") { 1033 HasExtDiv = true; 1034 continue; 1035 } 1036 1037 if (Feature == "power8-vector") { 1038 HasP8Vector = true; 1039 HasVSX = true; 1040 continue; 1041 } 1042 1043 if (Feature == "crypto") { 1044 HasP8Crypto = true; 1045 continue; 1046 } 1047 1048 if (Feature == "direct-move") { 1049 HasDirectMove = true; 1050 HasVSX = true; 1051 continue; 1052 } 1053 1054 if (Feature == "qpx") { 1055 HasQPX = true; 1056 continue; 1057 } 1058 1059 if (Feature == "htm") { 1060 HasHTM = true; 1061 continue; 1062 } 1063 1064 // TODO: Finish this list and add an assert that we've handled them 1065 // all. 1066 } 1067 1068 return true; 1069 } 1070 1071 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1072 /// #defines that are not tied to a specific subtarget. 1073 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1074 MacroBuilder &Builder) const { 1075 // Target identification. 1076 Builder.defineMacro("__ppc__"); 1077 Builder.defineMacro("__PPC__"); 1078 Builder.defineMacro("_ARCH_PPC"); 1079 Builder.defineMacro("__powerpc__"); 1080 Builder.defineMacro("__POWERPC__"); 1081 if (PointerWidth == 64) { 1082 Builder.defineMacro("_ARCH_PPC64"); 1083 Builder.defineMacro("__powerpc64__"); 1084 Builder.defineMacro("__ppc64__"); 1085 Builder.defineMacro("__PPC64__"); 1086 } 1087 1088 // Target properties. 1089 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1090 Builder.defineMacro("_LITTLE_ENDIAN"); 1091 } else { 1092 if (getTriple().getOS() != llvm::Triple::NetBSD && 1093 getTriple().getOS() != llvm::Triple::OpenBSD) 1094 Builder.defineMacro("_BIG_ENDIAN"); 1095 } 1096 1097 // ABI options. 1098 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1099 Builder.defineMacro("_CALL_ELF", "1"); 1100 if (ABI == "elfv2") 1101 Builder.defineMacro("_CALL_ELF", "2"); 1102 1103 // Subtarget options. 1104 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1105 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1106 1107 // FIXME: Should be controlled by command line option. 1108 if (LongDoubleWidth == 128) 1109 Builder.defineMacro("__LONG_DOUBLE_128__"); 1110 1111 if (Opts.AltiVec) { 1112 Builder.defineMacro("__VEC__", "10206"); 1113 Builder.defineMacro("__ALTIVEC__"); 1114 } 1115 1116 // CPU identification. 1117 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1118 .Case("440", ArchDefineName) 1119 .Case("450", ArchDefineName | ArchDefine440) 1120 .Case("601", ArchDefineName) 1121 .Case("602", ArchDefineName | ArchDefinePpcgr) 1122 .Case("603", ArchDefineName | ArchDefinePpcgr) 1123 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1124 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1125 .Case("604", ArchDefineName | ArchDefinePpcgr) 1126 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1127 .Case("620", ArchDefineName | ArchDefinePpcgr) 1128 .Case("630", ArchDefineName | ArchDefinePpcgr) 1129 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1130 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1131 .Case("750", ArchDefineName | ArchDefinePpcgr) 1132 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1133 | ArchDefinePpcsq) 1134 .Case("a2", ArchDefineA2) 1135 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1136 .Case("pwr3", ArchDefinePpcgr) 1137 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1138 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1139 | ArchDefinePpcsq) 1140 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1141 | ArchDefinePpcgr | ArchDefinePpcsq) 1142 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1143 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1144 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1145 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1146 | ArchDefinePpcsq) 1147 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1148 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1149 | ArchDefinePpcgr | ArchDefinePpcsq) 1150 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1151 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1152 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1153 .Case("power3", ArchDefinePpcgr) 1154 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1155 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1156 | ArchDefinePpcsq) 1157 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1158 | ArchDefinePpcgr | ArchDefinePpcsq) 1159 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1160 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1161 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1162 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1163 | ArchDefinePpcsq) 1164 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1165 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1166 | ArchDefinePpcgr | ArchDefinePpcsq) 1167 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1168 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1169 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1170 .Default(ArchDefineNone); 1171 1172 if (defs & ArchDefineName) 1173 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1174 if (defs & ArchDefinePpcgr) 1175 Builder.defineMacro("_ARCH_PPCGR"); 1176 if (defs & ArchDefinePpcsq) 1177 Builder.defineMacro("_ARCH_PPCSQ"); 1178 if (defs & ArchDefine440) 1179 Builder.defineMacro("_ARCH_440"); 1180 if (defs & ArchDefine603) 1181 Builder.defineMacro("_ARCH_603"); 1182 if (defs & ArchDefine604) 1183 Builder.defineMacro("_ARCH_604"); 1184 if (defs & ArchDefinePwr4) 1185 Builder.defineMacro("_ARCH_PWR4"); 1186 if (defs & ArchDefinePwr5) 1187 Builder.defineMacro("_ARCH_PWR5"); 1188 if (defs & ArchDefinePwr5x) 1189 Builder.defineMacro("_ARCH_PWR5X"); 1190 if (defs & ArchDefinePwr6) 1191 Builder.defineMacro("_ARCH_PWR6"); 1192 if (defs & ArchDefinePwr6x) 1193 Builder.defineMacro("_ARCH_PWR6X"); 1194 if (defs & ArchDefinePwr7) 1195 Builder.defineMacro("_ARCH_PWR7"); 1196 if (defs & ArchDefinePwr8) 1197 Builder.defineMacro("_ARCH_PWR8"); 1198 if (defs & ArchDefineA2) 1199 Builder.defineMacro("_ARCH_A2"); 1200 if (defs & ArchDefineA2q) { 1201 Builder.defineMacro("_ARCH_A2Q"); 1202 Builder.defineMacro("_ARCH_QP"); 1203 } 1204 1205 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1206 Builder.defineMacro("__bg__"); 1207 Builder.defineMacro("__THW_BLUEGENE__"); 1208 Builder.defineMacro("__bgq__"); 1209 Builder.defineMacro("__TOS_BGQ__"); 1210 } 1211 1212 if (HasVSX) 1213 Builder.defineMacro("__VSX__"); 1214 if (HasP8Vector) 1215 Builder.defineMacro("__POWER8_VECTOR__"); 1216 if (HasP8Crypto) 1217 Builder.defineMacro("__CRYPTO__"); 1218 if (HasHTM) 1219 Builder.defineMacro("__HTM__"); 1220 if (getTriple().getArch() == llvm::Triple::ppc64le || 1221 (defs & ArchDefinePwr8) || (CPU == "pwr8")) { 1222 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1223 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1224 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1225 if (PointerWidth == 64) 1226 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1227 } 1228 1229 // FIXME: The following are not yet generated here by Clang, but are 1230 // generated by GCC: 1231 // 1232 // _SOFT_FLOAT_ 1233 // __RECIP_PRECISION__ 1234 // __APPLE_ALTIVEC__ 1235 // __RECIP__ 1236 // __RECIPF__ 1237 // __RSQRTE__ 1238 // __RSQRTEF__ 1239 // _SOFT_DOUBLE_ 1240 // __NO_LWSYNC__ 1241 // __HAVE_BSWAP__ 1242 // __LONGDOUBLE128 1243 // __CMODEL_MEDIUM__ 1244 // __CMODEL_LARGE__ 1245 // _CALL_SYSV 1246 // _CALL_DARWIN 1247 // __NO_FPRS__ 1248 } 1249 1250 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1251 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1252 .Case("7400", true) 1253 .Case("g4", true) 1254 .Case("7450", true) 1255 .Case("g4+", true) 1256 .Case("970", true) 1257 .Case("g5", true) 1258 .Case("pwr6", true) 1259 .Case("pwr7", true) 1260 .Case("pwr8", true) 1261 .Case("ppc64", true) 1262 .Case("ppc64le", true) 1263 .Default(false); 1264 1265 Features["qpx"] = (CPU == "a2q"); 1266 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1267 .Case("ppc64le", true) 1268 .Case("pwr8", true) 1269 .Default(false); 1270 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1271 .Case("ppc64le", true) 1272 .Case("pwr8", true) 1273 .Default(false); 1274 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1275 .Case("ppc64le", true) 1276 .Case("pwr8", true) 1277 .Case("pwr7", true) 1278 .Default(false); 1279 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1280 .Case("ppc64le", true) 1281 .Case("pwr8", true) 1282 .Case("pwr7", true) 1283 .Default(false); 1284 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1285 .Case("ppc64le", true) 1286 .Case("pwr8", true) 1287 .Default(false); 1288 } 1289 1290 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1291 return llvm::StringSwitch<bool>(Feature) 1292 .Case("powerpc", true) 1293 .Case("vsx", HasVSX) 1294 .Case("power8-vector", HasP8Vector) 1295 .Case("crypto", HasP8Crypto) 1296 .Case("direct-move", HasDirectMove) 1297 .Case("qpx", HasQPX) 1298 .Case("htm", HasHTM) 1299 .Case("bpermd", HasBPERMD) 1300 .Case("extdiv", HasExtDiv) 1301 .Default(false); 1302 } 1303 1304 const char * const PPCTargetInfo::GCCRegNames[] = { 1305 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1306 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1307 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1308 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1309 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1310 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1311 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1312 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1313 "mq", "lr", "ctr", "ap", 1314 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1315 "xer", 1316 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1317 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1318 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1319 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1320 "vrsave", "vscr", 1321 "spe_acc", "spefscr", 1322 "sfp" 1323 }; 1324 1325 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1326 unsigned &NumNames) const { 1327 Names = GCCRegNames; 1328 NumNames = llvm::array_lengthof(GCCRegNames); 1329 } 1330 1331 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1332 // While some of these aliases do map to different registers 1333 // they still share the same register name. 1334 { { "0" }, "r0" }, 1335 { { "1"}, "r1" }, 1336 { { "2" }, "r2" }, 1337 { { "3" }, "r3" }, 1338 { { "4" }, "r4" }, 1339 { { "5" }, "r5" }, 1340 { { "6" }, "r6" }, 1341 { { "7" }, "r7" }, 1342 { { "8" }, "r8" }, 1343 { { "9" }, "r9" }, 1344 { { "10" }, "r10" }, 1345 { { "11" }, "r11" }, 1346 { { "12" }, "r12" }, 1347 { { "13" }, "r13" }, 1348 { { "14" }, "r14" }, 1349 { { "15" }, "r15" }, 1350 { { "16" }, "r16" }, 1351 { { "17" }, "r17" }, 1352 { { "18" }, "r18" }, 1353 { { "19" }, "r19" }, 1354 { { "20" }, "r20" }, 1355 { { "21" }, "r21" }, 1356 { { "22" }, "r22" }, 1357 { { "23" }, "r23" }, 1358 { { "24" }, "r24" }, 1359 { { "25" }, "r25" }, 1360 { { "26" }, "r26" }, 1361 { { "27" }, "r27" }, 1362 { { "28" }, "r28" }, 1363 { { "29" }, "r29" }, 1364 { { "30" }, "r30" }, 1365 { { "31" }, "r31" }, 1366 { { "fr0" }, "f0" }, 1367 { { "fr1" }, "f1" }, 1368 { { "fr2" }, "f2" }, 1369 { { "fr3" }, "f3" }, 1370 { { "fr4" }, "f4" }, 1371 { { "fr5" }, "f5" }, 1372 { { "fr6" }, "f6" }, 1373 { { "fr7" }, "f7" }, 1374 { { "fr8" }, "f8" }, 1375 { { "fr9" }, "f9" }, 1376 { { "fr10" }, "f10" }, 1377 { { "fr11" }, "f11" }, 1378 { { "fr12" }, "f12" }, 1379 { { "fr13" }, "f13" }, 1380 { { "fr14" }, "f14" }, 1381 { { "fr15" }, "f15" }, 1382 { { "fr16" }, "f16" }, 1383 { { "fr17" }, "f17" }, 1384 { { "fr18" }, "f18" }, 1385 { { "fr19" }, "f19" }, 1386 { { "fr20" }, "f20" }, 1387 { { "fr21" }, "f21" }, 1388 { { "fr22" }, "f22" }, 1389 { { "fr23" }, "f23" }, 1390 { { "fr24" }, "f24" }, 1391 { { "fr25" }, "f25" }, 1392 { { "fr26" }, "f26" }, 1393 { { "fr27" }, "f27" }, 1394 { { "fr28" }, "f28" }, 1395 { { "fr29" }, "f29" }, 1396 { { "fr30" }, "f30" }, 1397 { { "fr31" }, "f31" }, 1398 { { "cc" }, "cr0" }, 1399 }; 1400 1401 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1402 unsigned &NumAliases) const { 1403 Aliases = GCCRegAliases; 1404 NumAliases = llvm::array_lengthof(GCCRegAliases); 1405 } 1406 1407 class PPC32TargetInfo : public PPCTargetInfo { 1408 public: 1409 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1410 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1411 1412 switch (getTriple().getOS()) { 1413 case llvm::Triple::Linux: 1414 case llvm::Triple::FreeBSD: 1415 case llvm::Triple::NetBSD: 1416 SizeType = UnsignedInt; 1417 PtrDiffType = SignedInt; 1418 IntPtrType = SignedInt; 1419 break; 1420 default: 1421 break; 1422 } 1423 1424 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1425 LongDoubleWidth = LongDoubleAlign = 64; 1426 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1427 } 1428 1429 // PPC32 supports atomics up to 4 bytes. 1430 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1431 } 1432 1433 BuiltinVaListKind getBuiltinVaListKind() const override { 1434 // This is the ELF definition, and is overridden by the Darwin sub-target 1435 return TargetInfo::PowerABIBuiltinVaList; 1436 } 1437 }; 1438 1439 // Note: ABI differences may eventually require us to have a separate 1440 // TargetInfo for little endian. 1441 class PPC64TargetInfo : public PPCTargetInfo { 1442 public: 1443 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1444 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1445 IntMaxType = SignedLong; 1446 Int64Type = SignedLong; 1447 1448 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1449 DescriptionString = "e-m:e-i64:64-n32:64"; 1450 ABI = "elfv2"; 1451 } else { 1452 DescriptionString = "E-m:e-i64:64-n32:64"; 1453 ABI = "elfv1"; 1454 } 1455 1456 switch (getTriple().getOS()) { 1457 case llvm::Triple::FreeBSD: 1458 LongDoubleWidth = LongDoubleAlign = 64; 1459 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1460 break; 1461 case llvm::Triple::NetBSD: 1462 IntMaxType = SignedLongLong; 1463 Int64Type = SignedLongLong; 1464 break; 1465 default: 1466 break; 1467 } 1468 1469 // PPC64 supports atomics up to 8 bytes. 1470 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1471 } 1472 BuiltinVaListKind getBuiltinVaListKind() const override { 1473 return TargetInfo::CharPtrBuiltinVaList; 1474 } 1475 // PPC64 Linux-specifc ABI options. 1476 bool setABI(const std::string &Name) override { 1477 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1478 ABI = Name; 1479 return true; 1480 } 1481 return false; 1482 } 1483 }; 1484 1485 class DarwinPPC32TargetInfo : 1486 public DarwinTargetInfo<PPC32TargetInfo> { 1487 public: 1488 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1489 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1490 HasAlignMac68kSupport = true; 1491 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1492 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1493 LongLongAlign = 32; 1494 SuitableAlign = 128; 1495 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1496 } 1497 BuiltinVaListKind getBuiltinVaListKind() const override { 1498 return TargetInfo::CharPtrBuiltinVaList; 1499 } 1500 }; 1501 1502 class DarwinPPC64TargetInfo : 1503 public DarwinTargetInfo<PPC64TargetInfo> { 1504 public: 1505 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1506 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1507 HasAlignMac68kSupport = true; 1508 SuitableAlign = 128; 1509 DescriptionString = "E-m:o-i64:64-n32:64"; 1510 } 1511 }; 1512 1513 static const unsigned NVPTXAddrSpaceMap[] = { 1514 1, // opencl_global 1515 3, // opencl_local 1516 4, // opencl_constant 1517 // FIXME: generic has to be added to the target 1518 0, // opencl_generic 1519 1, // cuda_device 1520 4, // cuda_constant 1521 3, // cuda_shared 1522 }; 1523 class NVPTXTargetInfo : public TargetInfo { 1524 static const char * const GCCRegNames[]; 1525 static const Builtin::Info BuiltinInfo[]; 1526 1527 // The GPU profiles supported by the NVPTX backend 1528 enum GPUKind { 1529 GK_NONE, 1530 GK_SM20, 1531 GK_SM21, 1532 GK_SM30, 1533 GK_SM35, 1534 GK_SM37, 1535 } GPU; 1536 1537 public: 1538 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1539 BigEndian = false; 1540 TLSSupported = false; 1541 LongWidth = LongAlign = 64; 1542 AddrSpaceMap = &NVPTXAddrSpaceMap; 1543 UseAddrSpaceMapMangling = true; 1544 // Define available target features 1545 // These must be defined in sorted order! 1546 NoAsmVariants = true; 1547 // Set the default GPU to sm20 1548 GPU = GK_SM20; 1549 } 1550 void getTargetDefines(const LangOptions &Opts, 1551 MacroBuilder &Builder) const override { 1552 Builder.defineMacro("__PTX__"); 1553 Builder.defineMacro("__NVPTX__"); 1554 if (Opts.CUDAIsDevice) { 1555 // Set __CUDA_ARCH__ for the GPU specified. 1556 std::string CUDAArchCode; 1557 switch (GPU) { 1558 case GK_SM20: 1559 CUDAArchCode = "200"; 1560 break; 1561 case GK_SM21: 1562 CUDAArchCode = "210"; 1563 break; 1564 case GK_SM30: 1565 CUDAArchCode = "300"; 1566 break; 1567 case GK_SM35: 1568 CUDAArchCode = "350"; 1569 break; 1570 case GK_SM37: 1571 CUDAArchCode = "370"; 1572 break; 1573 default: 1574 llvm_unreachable("Unhandled target CPU"); 1575 } 1576 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1577 } 1578 } 1579 void getTargetBuiltins(const Builtin::Info *&Records, 1580 unsigned &NumRecords) const override { 1581 Records = BuiltinInfo; 1582 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1583 } 1584 bool hasFeature(StringRef Feature) const override { 1585 return Feature == "ptx" || Feature == "nvptx"; 1586 } 1587 1588 void getGCCRegNames(const char * const *&Names, 1589 unsigned &NumNames) const override; 1590 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1591 unsigned &NumAliases) const override { 1592 // No aliases. 1593 Aliases = nullptr; 1594 NumAliases = 0; 1595 } 1596 bool 1597 validateAsmConstraint(const char *&Name, 1598 TargetInfo::ConstraintInfo &Info) const override { 1599 switch (*Name) { 1600 default: return false; 1601 case 'c': 1602 case 'h': 1603 case 'r': 1604 case 'l': 1605 case 'f': 1606 case 'd': 1607 Info.setAllowsRegister(); 1608 return true; 1609 } 1610 } 1611 const char *getClobbers() const override { 1612 // FIXME: Is this really right? 1613 return ""; 1614 } 1615 BuiltinVaListKind getBuiltinVaListKind() const override { 1616 // FIXME: implement 1617 return TargetInfo::CharPtrBuiltinVaList; 1618 } 1619 bool setCPU(const std::string &Name) override { 1620 GPU = llvm::StringSwitch<GPUKind>(Name) 1621 .Case("sm_20", GK_SM20) 1622 .Case("sm_21", GK_SM21) 1623 .Case("sm_30", GK_SM30) 1624 .Case("sm_35", GK_SM35) 1625 .Case("sm_37", GK_SM37) 1626 .Default(GK_NONE); 1627 1628 return GPU != GK_NONE; 1629 } 1630 }; 1631 1632 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1633 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1634 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1635 ALL_LANGUAGES }, 1636 #include "clang/Basic/BuiltinsNVPTX.def" 1637 }; 1638 1639 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1640 "r0" 1641 }; 1642 1643 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1644 unsigned &NumNames) const { 1645 Names = GCCRegNames; 1646 NumNames = llvm::array_lengthof(GCCRegNames); 1647 } 1648 1649 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1650 public: 1651 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1652 PointerWidth = PointerAlign = 32; 1653 SizeType = TargetInfo::UnsignedInt; 1654 PtrDiffType = TargetInfo::SignedInt; 1655 IntPtrType = TargetInfo::SignedInt; 1656 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1657 } 1658 }; 1659 1660 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1661 public: 1662 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1663 PointerWidth = PointerAlign = 64; 1664 SizeType = TargetInfo::UnsignedLong; 1665 PtrDiffType = TargetInfo::SignedLong; 1666 IntPtrType = TargetInfo::SignedLong; 1667 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1668 } 1669 }; 1670 1671 static const unsigned AMDGPUAddrSpaceMap[] = { 1672 1, // opencl_global 1673 3, // opencl_local 1674 2, // opencl_constant 1675 4, // opencl_generic 1676 1, // cuda_device 1677 2, // cuda_constant 1678 3 // cuda_shared 1679 }; 1680 1681 // If you edit the description strings, make sure you update 1682 // getPointerWidthV(). 1683 1684 static const char *DescriptionStringR600 = 1685 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1686 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1687 1688 static const char *DescriptionStringR600DoubleOps = 1689 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1690 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1691 1692 static const char *DescriptionStringSI = 1693 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1694 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1695 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1696 1697 class AMDGPUTargetInfo : public TargetInfo { 1698 static const Builtin::Info BuiltinInfo[]; 1699 static const char * const GCCRegNames[]; 1700 1701 /// \brief The GPU profiles supported by the AMDGPU target. 1702 enum GPUKind { 1703 GK_NONE, 1704 GK_R600, 1705 GK_R600_DOUBLE_OPS, 1706 GK_R700, 1707 GK_R700_DOUBLE_OPS, 1708 GK_EVERGREEN, 1709 GK_EVERGREEN_DOUBLE_OPS, 1710 GK_NORTHERN_ISLANDS, 1711 GK_CAYMAN, 1712 GK_SOUTHERN_ISLANDS, 1713 GK_SEA_ISLANDS, 1714 GK_VOLCANIC_ISLANDS 1715 } GPU; 1716 1717 bool hasFP64:1; 1718 bool hasFMAF:1; 1719 bool hasLDEXPF:1; 1720 1721 public: 1722 AMDGPUTargetInfo(const llvm::Triple &Triple) 1723 : TargetInfo(Triple) { 1724 1725 if (Triple.getArch() == llvm::Triple::amdgcn) { 1726 DescriptionString = DescriptionStringSI; 1727 GPU = GK_SOUTHERN_ISLANDS; 1728 hasFP64 = true; 1729 hasFMAF = true; 1730 hasLDEXPF = true; 1731 } else { 1732 DescriptionString = DescriptionStringR600; 1733 GPU = GK_R600; 1734 hasFP64 = false; 1735 hasFMAF = false; 1736 hasLDEXPF = false; 1737 } 1738 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1739 UseAddrSpaceMapMangling = true; 1740 } 1741 1742 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1743 if (GPU <= GK_CAYMAN) 1744 return 32; 1745 1746 switch(AddrSpace) { 1747 default: 1748 return 64; 1749 case 0: 1750 case 3: 1751 case 5: 1752 return 32; 1753 } 1754 } 1755 1756 const char * getClobbers() const override { 1757 return ""; 1758 } 1759 1760 void getGCCRegNames(const char * const *&Names, 1761 unsigned &NumNames) const override; 1762 1763 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1764 unsigned &NumAliases) const override { 1765 Aliases = nullptr; 1766 NumAliases = 0; 1767 } 1768 1769 bool validateAsmConstraint(const char *&Name, 1770 TargetInfo::ConstraintInfo &info) const override { 1771 return true; 1772 } 1773 1774 void getTargetBuiltins(const Builtin::Info *&Records, 1775 unsigned &NumRecords) const override { 1776 Records = BuiltinInfo; 1777 NumRecords = clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin; 1778 } 1779 1780 void getTargetDefines(const LangOptions &Opts, 1781 MacroBuilder &Builder) const override { 1782 Builder.defineMacro("__R600__"); 1783 if (hasFMAF) 1784 Builder.defineMacro("__HAS_FMAF__"); 1785 if (hasLDEXPF) 1786 Builder.defineMacro("__HAS_LDEXPF__"); 1787 if (hasFP64 && Opts.OpenCL) { 1788 Builder.defineMacro("cl_khr_fp64"); 1789 } 1790 } 1791 1792 BuiltinVaListKind getBuiltinVaListKind() const override { 1793 return TargetInfo::CharPtrBuiltinVaList; 1794 } 1795 1796 bool setCPU(const std::string &Name) override { 1797 GPU = llvm::StringSwitch<GPUKind>(Name) 1798 .Case("r600" , GK_R600) 1799 .Case("rv610", GK_R600) 1800 .Case("rv620", GK_R600) 1801 .Case("rv630", GK_R600) 1802 .Case("rv635", GK_R600) 1803 .Case("rs780", GK_R600) 1804 .Case("rs880", GK_R600) 1805 .Case("rv670", GK_R600_DOUBLE_OPS) 1806 .Case("rv710", GK_R700) 1807 .Case("rv730", GK_R700) 1808 .Case("rv740", GK_R700_DOUBLE_OPS) 1809 .Case("rv770", GK_R700_DOUBLE_OPS) 1810 .Case("palm", GK_EVERGREEN) 1811 .Case("cedar", GK_EVERGREEN) 1812 .Case("sumo", GK_EVERGREEN) 1813 .Case("sumo2", GK_EVERGREEN) 1814 .Case("redwood", GK_EVERGREEN) 1815 .Case("juniper", GK_EVERGREEN) 1816 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1817 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1818 .Case("barts", GK_NORTHERN_ISLANDS) 1819 .Case("turks", GK_NORTHERN_ISLANDS) 1820 .Case("caicos", GK_NORTHERN_ISLANDS) 1821 .Case("cayman", GK_CAYMAN) 1822 .Case("aruba", GK_CAYMAN) 1823 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1824 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1825 .Case("verde", GK_SOUTHERN_ISLANDS) 1826 .Case("oland", GK_SOUTHERN_ISLANDS) 1827 .Case("hainan", GK_SOUTHERN_ISLANDS) 1828 .Case("bonaire", GK_SEA_ISLANDS) 1829 .Case("kabini", GK_SEA_ISLANDS) 1830 .Case("kaveri", GK_SEA_ISLANDS) 1831 .Case("hawaii", GK_SEA_ISLANDS) 1832 .Case("mullins", GK_SEA_ISLANDS) 1833 .Case("tonga", GK_VOLCANIC_ISLANDS) 1834 .Case("iceland", GK_VOLCANIC_ISLANDS) 1835 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1836 .Default(GK_NONE); 1837 1838 if (GPU == GK_NONE) { 1839 return false; 1840 } 1841 1842 // Set the correct data layout 1843 switch (GPU) { 1844 case GK_NONE: 1845 case GK_R600: 1846 case GK_R700: 1847 case GK_EVERGREEN: 1848 case GK_NORTHERN_ISLANDS: 1849 DescriptionString = DescriptionStringR600; 1850 hasFP64 = false; 1851 hasFMAF = false; 1852 hasLDEXPF = false; 1853 break; 1854 case GK_R600_DOUBLE_OPS: 1855 case GK_R700_DOUBLE_OPS: 1856 case GK_EVERGREEN_DOUBLE_OPS: 1857 case GK_CAYMAN: 1858 DescriptionString = DescriptionStringR600DoubleOps; 1859 hasFP64 = true; 1860 hasFMAF = true; 1861 hasLDEXPF = false; 1862 break; 1863 case GK_SOUTHERN_ISLANDS: 1864 case GK_SEA_ISLANDS: 1865 case GK_VOLCANIC_ISLANDS: 1866 DescriptionString = DescriptionStringSI; 1867 hasFP64 = true; 1868 hasFMAF = true; 1869 hasLDEXPF = true; 1870 break; 1871 } 1872 1873 return true; 1874 } 1875 }; 1876 1877 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1878 #define BUILTIN(ID, TYPE, ATTRS) \ 1879 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1880 #include "clang/Basic/BuiltinsAMDGPU.def" 1881 }; 1882 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1883 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1884 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1885 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1886 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1887 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1888 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1889 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1890 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1891 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1892 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1893 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1894 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1895 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1896 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1897 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1898 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1899 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1900 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1901 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1902 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1903 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1904 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1905 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1906 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1907 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1908 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1909 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1910 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1911 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1912 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1913 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1914 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1915 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1916 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1917 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1918 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1919 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1920 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1921 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1922 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1923 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1924 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 1925 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 1926 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 1927 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 1928 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 1929 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 1930 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 1931 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 1932 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 1933 }; 1934 1935 void AMDGPUTargetInfo::getGCCRegNames(const char * const *&Names, 1936 unsigned &NumNames) const { 1937 Names = GCCRegNames; 1938 NumNames = llvm::array_lengthof(GCCRegNames); 1939 } 1940 1941 // Namespace for x86 abstract base class 1942 const Builtin::Info BuiltinInfo[] = { 1943 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1944 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1945 ALL_LANGUAGES }, 1946 #include "clang/Basic/BuiltinsX86.def" 1947 }; 1948 1949 static const char* const GCCRegNames[] = { 1950 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1951 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1952 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1953 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1954 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1955 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1956 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1957 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1958 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1959 }; 1960 1961 const TargetInfo::AddlRegName AddlRegNames[] = { 1962 { { "al", "ah", "eax", "rax" }, 0 }, 1963 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1964 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1965 { { "dl", "dh", "edx", "rdx" }, 1 }, 1966 { { "esi", "rsi" }, 4 }, 1967 { { "edi", "rdi" }, 5 }, 1968 { { "esp", "rsp" }, 7 }, 1969 { { "ebp", "rbp" }, 6 }, 1970 }; 1971 1972 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1973 // most of the implementation can be shared. 1974 class X86TargetInfo : public TargetInfo { 1975 enum X86SSEEnum { 1976 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1977 } SSELevel; 1978 enum MMX3DNowEnum { 1979 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1980 } MMX3DNowLevel; 1981 enum XOPEnum { 1982 NoXOP, 1983 SSE4A, 1984 FMA4, 1985 XOP 1986 } XOPLevel; 1987 1988 bool HasAES; 1989 bool HasPCLMUL; 1990 bool HasLZCNT; 1991 bool HasRDRND; 1992 bool HasFSGSBASE; 1993 bool HasBMI; 1994 bool HasBMI2; 1995 bool HasPOPCNT; 1996 bool HasRTM; 1997 bool HasPRFCHW; 1998 bool HasRDSEED; 1999 bool HasADX; 2000 bool HasTBM; 2001 bool HasFMA; 2002 bool HasF16C; 2003 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 2004 HasAVX512VL; 2005 bool HasSHA; 2006 bool HasCX16; 2007 2008 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2009 /// 2010 /// Each enumeration represents a particular CPU supported by Clang. These 2011 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2012 enum CPUKind { 2013 CK_Generic, 2014 2015 /// \name i386 2016 /// i386-generation processors. 2017 //@{ 2018 CK_i386, 2019 //@} 2020 2021 /// \name i486 2022 /// i486-generation processors. 2023 //@{ 2024 CK_i486, 2025 CK_WinChipC6, 2026 CK_WinChip2, 2027 CK_C3, 2028 //@} 2029 2030 /// \name i586 2031 /// i586-generation processors, P5 microarchitecture based. 2032 //@{ 2033 CK_i586, 2034 CK_Pentium, 2035 CK_PentiumMMX, 2036 //@} 2037 2038 /// \name i686 2039 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2040 //@{ 2041 CK_i686, 2042 CK_PentiumPro, 2043 CK_Pentium2, 2044 CK_Pentium3, 2045 CK_Pentium3M, 2046 CK_PentiumM, 2047 CK_C3_2, 2048 2049 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2050 /// Clang however has some logic to suport this. 2051 // FIXME: Warn, deprecate, and potentially remove this. 2052 CK_Yonah, 2053 //@} 2054 2055 /// \name Netburst 2056 /// Netburst microarchitecture based processors. 2057 //@{ 2058 CK_Pentium4, 2059 CK_Pentium4M, 2060 CK_Prescott, 2061 CK_Nocona, 2062 //@} 2063 2064 /// \name Core 2065 /// Core microarchitecture based processors. 2066 //@{ 2067 CK_Core2, 2068 2069 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2070 /// codename which GCC no longer accepts as an option to -march, but Clang 2071 /// has some logic for recognizing it. 2072 // FIXME: Warn, deprecate, and potentially remove this. 2073 CK_Penryn, 2074 //@} 2075 2076 /// \name Atom 2077 /// Atom processors 2078 //@{ 2079 CK_Bonnell, 2080 CK_Silvermont, 2081 //@} 2082 2083 /// \name Nehalem 2084 /// Nehalem microarchitecture based processors. 2085 CK_Nehalem, 2086 2087 /// \name Westmere 2088 /// Westmere microarchitecture based processors. 2089 CK_Westmere, 2090 2091 /// \name Sandy Bridge 2092 /// Sandy Bridge microarchitecture based processors. 2093 CK_SandyBridge, 2094 2095 /// \name Ivy Bridge 2096 /// Ivy Bridge microarchitecture based processors. 2097 CK_IvyBridge, 2098 2099 /// \name Haswell 2100 /// Haswell microarchitecture based processors. 2101 CK_Haswell, 2102 2103 /// \name Broadwell 2104 /// Broadwell microarchitecture based processors. 2105 CK_Broadwell, 2106 2107 /// \name Skylake 2108 /// Skylake microarchitecture based processors. 2109 CK_Skylake, 2110 2111 /// \name Knights Landing 2112 /// Knights Landing processor. 2113 CK_KNL, 2114 2115 /// \name K6 2116 /// K6 architecture processors. 2117 //@{ 2118 CK_K6, 2119 CK_K6_2, 2120 CK_K6_3, 2121 //@} 2122 2123 /// \name K7 2124 /// K7 architecture processors. 2125 //@{ 2126 CK_Athlon, 2127 CK_AthlonThunderbird, 2128 CK_Athlon4, 2129 CK_AthlonXP, 2130 CK_AthlonMP, 2131 //@} 2132 2133 /// \name K8 2134 /// K8 architecture processors. 2135 //@{ 2136 CK_Athlon64, 2137 CK_Athlon64SSE3, 2138 CK_AthlonFX, 2139 CK_K8, 2140 CK_K8SSE3, 2141 CK_Opteron, 2142 CK_OpteronSSE3, 2143 CK_AMDFAM10, 2144 //@} 2145 2146 /// \name Bobcat 2147 /// Bobcat architecture processors. 2148 //@{ 2149 CK_BTVER1, 2150 CK_BTVER2, 2151 //@} 2152 2153 /// \name Bulldozer 2154 /// Bulldozer architecture processors. 2155 //@{ 2156 CK_BDVER1, 2157 CK_BDVER2, 2158 CK_BDVER3, 2159 CK_BDVER4, 2160 //@} 2161 2162 /// This specification is deprecated and will be removed in the future. 2163 /// Users should prefer \see CK_K8. 2164 // FIXME: Warn on this when the CPU is set to it. 2165 //@{ 2166 CK_x86_64, 2167 //@} 2168 2169 /// \name Geode 2170 /// Geode processors. 2171 //@{ 2172 CK_Geode 2173 //@} 2174 } CPU; 2175 2176 enum FPMathKind { 2177 FP_Default, 2178 FP_SSE, 2179 FP_387 2180 } FPMath; 2181 2182 public: 2183 X86TargetInfo(const llvm::Triple &Triple) 2184 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 2185 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 2186 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 2187 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 2188 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 2189 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 2190 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 2191 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 2192 BigEndian = false; 2193 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2194 } 2195 unsigned getFloatEvalMethod() const override { 2196 // X87 evaluates with 80 bits "long double" precision. 2197 return SSELevel == NoSSE ? 2 : 0; 2198 } 2199 void getTargetBuiltins(const Builtin::Info *&Records, 2200 unsigned &NumRecords) const override { 2201 Records = BuiltinInfo; 2202 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 2203 } 2204 void getGCCRegNames(const char * const *&Names, 2205 unsigned &NumNames) const override { 2206 Names = GCCRegNames; 2207 NumNames = llvm::array_lengthof(GCCRegNames); 2208 } 2209 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2210 unsigned &NumAliases) const override { 2211 Aliases = nullptr; 2212 NumAliases = 0; 2213 } 2214 void getGCCAddlRegNames(const AddlRegName *&Names, 2215 unsigned &NumNames) const override { 2216 Names = AddlRegNames; 2217 NumNames = llvm::array_lengthof(AddlRegNames); 2218 } 2219 bool validateCpuSupports(StringRef Name) const override; 2220 bool validateAsmConstraint(const char *&Name, 2221 TargetInfo::ConstraintInfo &info) const override; 2222 2223 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2224 2225 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2226 2227 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2228 2229 std::string convertConstraint(const char *&Constraint) const override; 2230 const char *getClobbers() const override { 2231 return "~{dirflag},~{fpsr},~{flags}"; 2232 } 2233 void getTargetDefines(const LangOptions &Opts, 2234 MacroBuilder &Builder) const override; 2235 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2236 bool Enabled); 2237 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2238 bool Enabled); 2239 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2240 bool Enabled); 2241 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2242 StringRef Name, bool Enabled) const override { 2243 setFeatureEnabledImpl(Features, Name, Enabled); 2244 } 2245 // This exists purely to cut down on the number of virtual calls in 2246 // getDefaultFeatures which calls this repeatedly. 2247 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2248 StringRef Name, bool Enabled); 2249 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 2250 bool hasFeature(StringRef Feature) const override; 2251 bool handleTargetFeatures(std::vector<std::string> &Features, 2252 DiagnosticsEngine &Diags) override; 2253 StringRef getABI() const override { 2254 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2255 return "avx512"; 2256 else if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2257 return "avx"; 2258 else if (getTriple().getArch() == llvm::Triple::x86 && 2259 MMX3DNowLevel == NoMMX3DNow) 2260 return "no-mmx"; 2261 return ""; 2262 } 2263 bool setCPU(const std::string &Name) override { 2264 CPU = llvm::StringSwitch<CPUKind>(Name) 2265 .Case("i386", CK_i386) 2266 .Case("i486", CK_i486) 2267 .Case("winchip-c6", CK_WinChipC6) 2268 .Case("winchip2", CK_WinChip2) 2269 .Case("c3", CK_C3) 2270 .Case("i586", CK_i586) 2271 .Case("pentium", CK_Pentium) 2272 .Case("pentium-mmx", CK_PentiumMMX) 2273 .Case("i686", CK_i686) 2274 .Case("pentiumpro", CK_PentiumPro) 2275 .Case("pentium2", CK_Pentium2) 2276 .Case("pentium3", CK_Pentium3) 2277 .Case("pentium3m", CK_Pentium3M) 2278 .Case("pentium-m", CK_PentiumM) 2279 .Case("c3-2", CK_C3_2) 2280 .Case("yonah", CK_Yonah) 2281 .Case("pentium4", CK_Pentium4) 2282 .Case("pentium4m", CK_Pentium4M) 2283 .Case("prescott", CK_Prescott) 2284 .Case("nocona", CK_Nocona) 2285 .Case("core2", CK_Core2) 2286 .Case("penryn", CK_Penryn) 2287 .Case("bonnell", CK_Bonnell) 2288 .Case("atom", CK_Bonnell) // Legacy name. 2289 .Case("silvermont", CK_Silvermont) 2290 .Case("slm", CK_Silvermont) // Legacy name. 2291 .Case("nehalem", CK_Nehalem) 2292 .Case("corei7", CK_Nehalem) // Legacy name. 2293 .Case("westmere", CK_Westmere) 2294 .Case("sandybridge", CK_SandyBridge) 2295 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2296 .Case("ivybridge", CK_IvyBridge) 2297 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2298 .Case("haswell", CK_Haswell) 2299 .Case("core-avx2", CK_Haswell) // Legacy name. 2300 .Case("broadwell", CK_Broadwell) 2301 .Case("skylake", CK_Skylake) 2302 .Case("skx", CK_Skylake) // Legacy name. 2303 .Case("knl", CK_KNL) 2304 .Case("k6", CK_K6) 2305 .Case("k6-2", CK_K6_2) 2306 .Case("k6-3", CK_K6_3) 2307 .Case("athlon", CK_Athlon) 2308 .Case("athlon-tbird", CK_AthlonThunderbird) 2309 .Case("athlon-4", CK_Athlon4) 2310 .Case("athlon-xp", CK_AthlonXP) 2311 .Case("athlon-mp", CK_AthlonMP) 2312 .Case("athlon64", CK_Athlon64) 2313 .Case("athlon64-sse3", CK_Athlon64SSE3) 2314 .Case("athlon-fx", CK_AthlonFX) 2315 .Case("k8", CK_K8) 2316 .Case("k8-sse3", CK_K8SSE3) 2317 .Case("opteron", CK_Opteron) 2318 .Case("opteron-sse3", CK_OpteronSSE3) 2319 .Case("barcelona", CK_AMDFAM10) 2320 .Case("amdfam10", CK_AMDFAM10) 2321 .Case("btver1", CK_BTVER1) 2322 .Case("btver2", CK_BTVER2) 2323 .Case("bdver1", CK_BDVER1) 2324 .Case("bdver2", CK_BDVER2) 2325 .Case("bdver3", CK_BDVER3) 2326 .Case("bdver4", CK_BDVER4) 2327 .Case("x86-64", CK_x86_64) 2328 .Case("geode", CK_Geode) 2329 .Default(CK_Generic); 2330 2331 // Perform any per-CPU checks necessary to determine if this CPU is 2332 // acceptable. 2333 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2334 // invalid without explaining *why*. 2335 switch (CPU) { 2336 case CK_Generic: 2337 // No processor selected! 2338 return false; 2339 2340 case CK_i386: 2341 case CK_i486: 2342 case CK_WinChipC6: 2343 case CK_WinChip2: 2344 case CK_C3: 2345 case CK_i586: 2346 case CK_Pentium: 2347 case CK_PentiumMMX: 2348 case CK_i686: 2349 case CK_PentiumPro: 2350 case CK_Pentium2: 2351 case CK_Pentium3: 2352 case CK_Pentium3M: 2353 case CK_PentiumM: 2354 case CK_Yonah: 2355 case CK_C3_2: 2356 case CK_Pentium4: 2357 case CK_Pentium4M: 2358 case CK_Prescott: 2359 case CK_K6: 2360 case CK_K6_2: 2361 case CK_K6_3: 2362 case CK_Athlon: 2363 case CK_AthlonThunderbird: 2364 case CK_Athlon4: 2365 case CK_AthlonXP: 2366 case CK_AthlonMP: 2367 case CK_Geode: 2368 // Only accept certain architectures when compiling in 32-bit mode. 2369 if (getTriple().getArch() != llvm::Triple::x86) 2370 return false; 2371 2372 // Fallthrough 2373 case CK_Nocona: 2374 case CK_Core2: 2375 case CK_Penryn: 2376 case CK_Bonnell: 2377 case CK_Silvermont: 2378 case CK_Nehalem: 2379 case CK_Westmere: 2380 case CK_SandyBridge: 2381 case CK_IvyBridge: 2382 case CK_Haswell: 2383 case CK_Broadwell: 2384 case CK_Skylake: 2385 case CK_KNL: 2386 case CK_Athlon64: 2387 case CK_Athlon64SSE3: 2388 case CK_AthlonFX: 2389 case CK_K8: 2390 case CK_K8SSE3: 2391 case CK_Opteron: 2392 case CK_OpteronSSE3: 2393 case CK_AMDFAM10: 2394 case CK_BTVER1: 2395 case CK_BTVER2: 2396 case CK_BDVER1: 2397 case CK_BDVER2: 2398 case CK_BDVER3: 2399 case CK_BDVER4: 2400 case CK_x86_64: 2401 return true; 2402 } 2403 llvm_unreachable("Unhandled CPU kind"); 2404 } 2405 2406 bool setFPMath(StringRef Name) override; 2407 2408 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2409 // We accept all non-ARM calling conventions 2410 return (CC == CC_X86ThisCall || 2411 CC == CC_X86FastCall || 2412 CC == CC_X86StdCall || 2413 CC == CC_X86VectorCall || 2414 CC == CC_C || 2415 CC == CC_X86Pascal || 2416 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2417 } 2418 2419 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2420 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2421 } 2422 2423 bool hasSjLjLowering() const override { 2424 return true; 2425 } 2426 }; 2427 2428 bool X86TargetInfo::setFPMath(StringRef Name) { 2429 if (Name == "387") { 2430 FPMath = FP_387; 2431 return true; 2432 } 2433 if (Name == "sse") { 2434 FPMath = FP_SSE; 2435 return true; 2436 } 2437 return false; 2438 } 2439 2440 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2441 // FIXME: This *really* should not be here. 2442 2443 // X86_64 always has SSE2. 2444 if (getTriple().getArch() == llvm::Triple::x86_64) 2445 setFeatureEnabledImpl(Features, "sse2", true); 2446 2447 switch (CPU) { 2448 case CK_Generic: 2449 case CK_i386: 2450 case CK_i486: 2451 case CK_i586: 2452 case CK_Pentium: 2453 case CK_i686: 2454 case CK_PentiumPro: 2455 break; 2456 case CK_PentiumMMX: 2457 case CK_Pentium2: 2458 case CK_K6: 2459 case CK_WinChipC6: 2460 setFeatureEnabledImpl(Features, "mmx", true); 2461 break; 2462 case CK_Pentium3: 2463 case CK_Pentium3M: 2464 case CK_C3_2: 2465 setFeatureEnabledImpl(Features, "sse", true); 2466 break; 2467 case CK_PentiumM: 2468 case CK_Pentium4: 2469 case CK_Pentium4M: 2470 case CK_x86_64: 2471 setFeatureEnabledImpl(Features, "sse2", true); 2472 break; 2473 case CK_Yonah: 2474 case CK_Prescott: 2475 case CK_Nocona: 2476 setFeatureEnabledImpl(Features, "sse3", true); 2477 setFeatureEnabledImpl(Features, "cx16", true); 2478 break; 2479 case CK_Core2: 2480 case CK_Bonnell: 2481 setFeatureEnabledImpl(Features, "ssse3", true); 2482 setFeatureEnabledImpl(Features, "cx16", true); 2483 break; 2484 case CK_Penryn: 2485 setFeatureEnabledImpl(Features, "sse4.1", true); 2486 setFeatureEnabledImpl(Features, "cx16", true); 2487 break; 2488 case CK_Skylake: 2489 setFeatureEnabledImpl(Features, "avx512f", true); 2490 setFeatureEnabledImpl(Features, "avx512cd", true); 2491 setFeatureEnabledImpl(Features, "avx512dq", true); 2492 setFeatureEnabledImpl(Features, "avx512bw", true); 2493 setFeatureEnabledImpl(Features, "avx512vl", true); 2494 // FALLTHROUGH 2495 case CK_Broadwell: 2496 setFeatureEnabledImpl(Features, "rdseed", true); 2497 setFeatureEnabledImpl(Features, "adx", true); 2498 // FALLTHROUGH 2499 case CK_Haswell: 2500 setFeatureEnabledImpl(Features, "avx2", true); 2501 setFeatureEnabledImpl(Features, "lzcnt", true); 2502 setFeatureEnabledImpl(Features, "bmi", true); 2503 setFeatureEnabledImpl(Features, "bmi2", true); 2504 setFeatureEnabledImpl(Features, "rtm", true); 2505 setFeatureEnabledImpl(Features, "fma", true); 2506 // FALLTHROUGH 2507 case CK_IvyBridge: 2508 setFeatureEnabledImpl(Features, "rdrnd", true); 2509 setFeatureEnabledImpl(Features, "f16c", true); 2510 setFeatureEnabledImpl(Features, "fsgsbase", true); 2511 // FALLTHROUGH 2512 case CK_SandyBridge: 2513 setFeatureEnabledImpl(Features, "avx", true); 2514 // FALLTHROUGH 2515 case CK_Westmere: 2516 case CK_Silvermont: 2517 setFeatureEnabledImpl(Features, "aes", true); 2518 setFeatureEnabledImpl(Features, "pclmul", true); 2519 // FALLTHROUGH 2520 case CK_Nehalem: 2521 setFeatureEnabledImpl(Features, "sse4.2", true); 2522 setFeatureEnabledImpl(Features, "cx16", true); 2523 break; 2524 case CK_KNL: 2525 setFeatureEnabledImpl(Features, "avx512f", true); 2526 setFeatureEnabledImpl(Features, "avx512cd", true); 2527 setFeatureEnabledImpl(Features, "avx512er", true); 2528 setFeatureEnabledImpl(Features, "avx512pf", true); 2529 setFeatureEnabledImpl(Features, "rdseed", true); 2530 setFeatureEnabledImpl(Features, "adx", true); 2531 setFeatureEnabledImpl(Features, "lzcnt", true); 2532 setFeatureEnabledImpl(Features, "bmi", true); 2533 setFeatureEnabledImpl(Features, "bmi2", true); 2534 setFeatureEnabledImpl(Features, "rtm", true); 2535 setFeatureEnabledImpl(Features, "fma", true); 2536 setFeatureEnabledImpl(Features, "rdrnd", true); 2537 setFeatureEnabledImpl(Features, "f16c", true); 2538 setFeatureEnabledImpl(Features, "fsgsbase", true); 2539 setFeatureEnabledImpl(Features, "aes", true); 2540 setFeatureEnabledImpl(Features, "pclmul", true); 2541 setFeatureEnabledImpl(Features, "cx16", true); 2542 break; 2543 case CK_K6_2: 2544 case CK_K6_3: 2545 case CK_WinChip2: 2546 case CK_C3: 2547 setFeatureEnabledImpl(Features, "3dnow", true); 2548 break; 2549 case CK_Athlon: 2550 case CK_AthlonThunderbird: 2551 case CK_Geode: 2552 setFeatureEnabledImpl(Features, "3dnowa", true); 2553 break; 2554 case CK_Athlon4: 2555 case CK_AthlonXP: 2556 case CK_AthlonMP: 2557 setFeatureEnabledImpl(Features, "sse", true); 2558 setFeatureEnabledImpl(Features, "3dnowa", true); 2559 break; 2560 case CK_K8: 2561 case CK_Opteron: 2562 case CK_Athlon64: 2563 case CK_AthlonFX: 2564 setFeatureEnabledImpl(Features, "sse2", true); 2565 setFeatureEnabledImpl(Features, "3dnowa", true); 2566 break; 2567 case CK_AMDFAM10: 2568 setFeatureEnabledImpl(Features, "sse4a", true); 2569 setFeatureEnabledImpl(Features, "lzcnt", true); 2570 setFeatureEnabledImpl(Features, "popcnt", true); 2571 // FALLTHROUGH 2572 case CK_K8SSE3: 2573 case CK_OpteronSSE3: 2574 case CK_Athlon64SSE3: 2575 setFeatureEnabledImpl(Features, "sse3", true); 2576 setFeatureEnabledImpl(Features, "3dnowa", true); 2577 break; 2578 case CK_BTVER2: 2579 setFeatureEnabledImpl(Features, "avx", true); 2580 setFeatureEnabledImpl(Features, "aes", true); 2581 setFeatureEnabledImpl(Features, "pclmul", true); 2582 setFeatureEnabledImpl(Features, "bmi", true); 2583 setFeatureEnabledImpl(Features, "f16c", true); 2584 // FALLTHROUGH 2585 case CK_BTVER1: 2586 setFeatureEnabledImpl(Features, "ssse3", true); 2587 setFeatureEnabledImpl(Features, "sse4a", true); 2588 setFeatureEnabledImpl(Features, "lzcnt", true); 2589 setFeatureEnabledImpl(Features, "popcnt", true); 2590 setFeatureEnabledImpl(Features, "prfchw", true); 2591 setFeatureEnabledImpl(Features, "cx16", true); 2592 break; 2593 case CK_BDVER4: 2594 setFeatureEnabledImpl(Features, "avx2", true); 2595 setFeatureEnabledImpl(Features, "bmi2", true); 2596 // FALLTHROUGH 2597 case CK_BDVER3: 2598 setFeatureEnabledImpl(Features, "fsgsbase", true); 2599 // FALLTHROUGH 2600 case CK_BDVER2: 2601 setFeatureEnabledImpl(Features, "bmi", true); 2602 setFeatureEnabledImpl(Features, "fma", true); 2603 setFeatureEnabledImpl(Features, "f16c", true); 2604 setFeatureEnabledImpl(Features, "tbm", true); 2605 // FALLTHROUGH 2606 case CK_BDVER1: 2607 // xop implies avx, sse4a and fma4. 2608 setFeatureEnabledImpl(Features, "xop", true); 2609 setFeatureEnabledImpl(Features, "lzcnt", true); 2610 setFeatureEnabledImpl(Features, "aes", true); 2611 setFeatureEnabledImpl(Features, "pclmul", true); 2612 setFeatureEnabledImpl(Features, "prfchw", true); 2613 setFeatureEnabledImpl(Features, "cx16", true); 2614 break; 2615 } 2616 } 2617 2618 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2619 X86SSEEnum Level, bool Enabled) { 2620 if (Enabled) { 2621 switch (Level) { 2622 case AVX512F: 2623 Features["avx512f"] = true; 2624 case AVX2: 2625 Features["avx2"] = true; 2626 case AVX: 2627 Features["avx"] = true; 2628 case SSE42: 2629 Features["sse4.2"] = true; 2630 case SSE41: 2631 Features["sse4.1"] = true; 2632 case SSSE3: 2633 Features["ssse3"] = true; 2634 case SSE3: 2635 Features["sse3"] = true; 2636 case SSE2: 2637 Features["sse2"] = true; 2638 case SSE1: 2639 Features["sse"] = true; 2640 case NoSSE: 2641 break; 2642 } 2643 return; 2644 } 2645 2646 switch (Level) { 2647 case NoSSE: 2648 case SSE1: 2649 Features["sse"] = false; 2650 case SSE2: 2651 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2652 Features["sha"] = false; 2653 case SSE3: 2654 Features["sse3"] = false; 2655 setXOPLevel(Features, NoXOP, false); 2656 case SSSE3: 2657 Features["ssse3"] = false; 2658 case SSE41: 2659 Features["sse4.1"] = false; 2660 case SSE42: 2661 Features["sse4.2"] = false; 2662 case AVX: 2663 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2664 setXOPLevel(Features, FMA4, false); 2665 case AVX2: 2666 Features["avx2"] = false; 2667 case AVX512F: 2668 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2669 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2670 Features["avx512vl"] = false; 2671 } 2672 } 2673 2674 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2675 MMX3DNowEnum Level, bool Enabled) { 2676 if (Enabled) { 2677 switch (Level) { 2678 case AMD3DNowAthlon: 2679 Features["3dnowa"] = true; 2680 case AMD3DNow: 2681 Features["3dnow"] = true; 2682 case MMX: 2683 Features["mmx"] = true; 2684 case NoMMX3DNow: 2685 break; 2686 } 2687 return; 2688 } 2689 2690 switch (Level) { 2691 case NoMMX3DNow: 2692 case MMX: 2693 Features["mmx"] = false; 2694 case AMD3DNow: 2695 Features["3dnow"] = false; 2696 case AMD3DNowAthlon: 2697 Features["3dnowa"] = false; 2698 } 2699 } 2700 2701 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2702 bool Enabled) { 2703 if (Enabled) { 2704 switch (Level) { 2705 case XOP: 2706 Features["xop"] = true; 2707 case FMA4: 2708 Features["fma4"] = true; 2709 setSSELevel(Features, AVX, true); 2710 case SSE4A: 2711 Features["sse4a"] = true; 2712 setSSELevel(Features, SSE3, true); 2713 case NoXOP: 2714 break; 2715 } 2716 return; 2717 } 2718 2719 switch (Level) { 2720 case NoXOP: 2721 case SSE4A: 2722 Features["sse4a"] = false; 2723 case FMA4: 2724 Features["fma4"] = false; 2725 case XOP: 2726 Features["xop"] = false; 2727 } 2728 } 2729 2730 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2731 StringRef Name, bool Enabled) { 2732 // This is a bit of a hack to deal with the sse4 target feature when used 2733 // as part of the target attribute. We handle sse4 correctly everywhere 2734 // else. See below for more information on how we handle the sse4 options. 2735 if (Name != "sse4") 2736 Features[Name] = Enabled; 2737 2738 if (Name == "mmx") { 2739 setMMXLevel(Features, MMX, Enabled); 2740 } else if (Name == "sse") { 2741 setSSELevel(Features, SSE1, Enabled); 2742 } else if (Name == "sse2") { 2743 setSSELevel(Features, SSE2, Enabled); 2744 } else if (Name == "sse3") { 2745 setSSELevel(Features, SSE3, Enabled); 2746 } else if (Name == "ssse3") { 2747 setSSELevel(Features, SSSE3, Enabled); 2748 } else if (Name == "sse4.2") { 2749 setSSELevel(Features, SSE42, Enabled); 2750 } else if (Name == "sse4.1") { 2751 setSSELevel(Features, SSE41, Enabled); 2752 } else if (Name == "3dnow") { 2753 setMMXLevel(Features, AMD3DNow, Enabled); 2754 } else if (Name == "3dnowa") { 2755 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2756 } else if (Name == "aes") { 2757 if (Enabled) 2758 setSSELevel(Features, SSE2, Enabled); 2759 } else if (Name == "pclmul") { 2760 if (Enabled) 2761 setSSELevel(Features, SSE2, Enabled); 2762 } else if (Name == "avx") { 2763 setSSELevel(Features, AVX, Enabled); 2764 } else if (Name == "avx2") { 2765 setSSELevel(Features, AVX2, Enabled); 2766 } else if (Name == "avx512f") { 2767 setSSELevel(Features, AVX512F, Enabled); 2768 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2769 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2770 if (Enabled) 2771 setSSELevel(Features, AVX512F, Enabled); 2772 } else if (Name == "fma") { 2773 if (Enabled) 2774 setSSELevel(Features, AVX, Enabled); 2775 } else if (Name == "fma4") { 2776 setXOPLevel(Features, FMA4, Enabled); 2777 } else if (Name == "xop") { 2778 setXOPLevel(Features, XOP, Enabled); 2779 } else if (Name == "sse4a") { 2780 setXOPLevel(Features, SSE4A, Enabled); 2781 } else if (Name == "f16c") { 2782 if (Enabled) 2783 setSSELevel(Features, AVX, Enabled); 2784 } else if (Name == "sha") { 2785 if (Enabled) 2786 setSSELevel(Features, SSE2, Enabled); 2787 } else if (Name == "sse4") { 2788 // We can get here via the __target__ attribute since that's not controlled 2789 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2790 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2791 // disabled. 2792 if (Enabled) 2793 setSSELevel(Features, SSE42, Enabled); 2794 else 2795 setSSELevel(Features, SSE41, Enabled); 2796 } 2797 } 2798 2799 /// handleTargetFeatures - Perform initialization based on the user 2800 /// configured set of features. 2801 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2802 DiagnosticsEngine &Diags) { 2803 // Remember the maximum enabled sselevel. 2804 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2805 // Ignore disabled features. 2806 if (Features[i][0] == '-') 2807 continue; 2808 2809 StringRef Feature = StringRef(Features[i]).substr(1); 2810 2811 if (Feature == "aes") { 2812 HasAES = true; 2813 continue; 2814 } 2815 2816 if (Feature == "pclmul") { 2817 HasPCLMUL = true; 2818 continue; 2819 } 2820 2821 if (Feature == "lzcnt") { 2822 HasLZCNT = true; 2823 continue; 2824 } 2825 2826 if (Feature == "rdrnd") { 2827 HasRDRND = true; 2828 continue; 2829 } 2830 2831 if (Feature == "fsgsbase") { 2832 HasFSGSBASE = true; 2833 continue; 2834 } 2835 2836 if (Feature == "bmi") { 2837 HasBMI = true; 2838 continue; 2839 } 2840 2841 if (Feature == "bmi2") { 2842 HasBMI2 = true; 2843 continue; 2844 } 2845 2846 if (Feature == "popcnt") { 2847 HasPOPCNT = true; 2848 continue; 2849 } 2850 2851 if (Feature == "rtm") { 2852 HasRTM = true; 2853 continue; 2854 } 2855 2856 if (Feature == "prfchw") { 2857 HasPRFCHW = true; 2858 continue; 2859 } 2860 2861 if (Feature == "rdseed") { 2862 HasRDSEED = true; 2863 continue; 2864 } 2865 2866 if (Feature == "adx") { 2867 HasADX = true; 2868 continue; 2869 } 2870 2871 if (Feature == "tbm") { 2872 HasTBM = true; 2873 continue; 2874 } 2875 2876 if (Feature == "fma") { 2877 HasFMA = true; 2878 continue; 2879 } 2880 2881 if (Feature == "f16c") { 2882 HasF16C = true; 2883 continue; 2884 } 2885 2886 if (Feature == "avx512cd") { 2887 HasAVX512CD = true; 2888 continue; 2889 } 2890 2891 if (Feature == "avx512er") { 2892 HasAVX512ER = true; 2893 continue; 2894 } 2895 2896 if (Feature == "avx512pf") { 2897 HasAVX512PF = true; 2898 continue; 2899 } 2900 2901 if (Feature == "avx512dq") { 2902 HasAVX512DQ = true; 2903 continue; 2904 } 2905 2906 if (Feature == "avx512bw") { 2907 HasAVX512BW = true; 2908 continue; 2909 } 2910 2911 if (Feature == "avx512vl") { 2912 HasAVX512VL = true; 2913 continue; 2914 } 2915 2916 if (Feature == "sha") { 2917 HasSHA = true; 2918 continue; 2919 } 2920 2921 if (Feature == "cx16") { 2922 HasCX16 = true; 2923 continue; 2924 } 2925 2926 assert(Features[i][0] == '+' && "Invalid target feature!"); 2927 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2928 .Case("avx512f", AVX512F) 2929 .Case("avx2", AVX2) 2930 .Case("avx", AVX) 2931 .Case("sse4.2", SSE42) 2932 .Case("sse4.1", SSE41) 2933 .Case("ssse3", SSSE3) 2934 .Case("sse3", SSE3) 2935 .Case("sse2", SSE2) 2936 .Case("sse", SSE1) 2937 .Default(NoSSE); 2938 SSELevel = std::max(SSELevel, Level); 2939 2940 MMX3DNowEnum ThreeDNowLevel = 2941 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2942 .Case("3dnowa", AMD3DNowAthlon) 2943 .Case("3dnow", AMD3DNow) 2944 .Case("mmx", MMX) 2945 .Default(NoMMX3DNow); 2946 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2947 2948 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2949 .Case("xop", XOP) 2950 .Case("fma4", FMA4) 2951 .Case("sse4a", SSE4A) 2952 .Default(NoXOP); 2953 XOPLevel = std::max(XOPLevel, XLevel); 2954 } 2955 2956 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2957 // Can't do this earlier because we need to be able to explicitly enable 2958 // popcnt and still disable sse4.2. 2959 if (!HasPOPCNT && SSELevel >= SSE42 && 2960 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2961 HasPOPCNT = true; 2962 Features.push_back("+popcnt"); 2963 } 2964 2965 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2966 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2967 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2968 HasPRFCHW = true; 2969 Features.push_back("+prfchw"); 2970 } 2971 2972 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2973 // matches the selected sse level. 2974 if (FPMath == FP_SSE && SSELevel < SSE1) { 2975 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2976 return false; 2977 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2978 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2979 return false; 2980 } 2981 2982 // Don't tell the backend if we're turning off mmx; it will end up disabling 2983 // SSE, which we don't want. 2984 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2985 // then enable MMX. 2986 std::vector<std::string>::iterator it; 2987 it = std::find(Features.begin(), Features.end(), "-mmx"); 2988 if (it != Features.end()) 2989 Features.erase(it); 2990 else if (SSELevel > NoSSE) 2991 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2992 2993 SimdDefaultAlign = 2994 (getABI() == "avx512") ? 512 : (getABI() == "avx") ? 256 : 128; 2995 return true; 2996 } 2997 2998 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2999 /// definitions for this particular subtarget. 3000 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3001 MacroBuilder &Builder) const { 3002 // Target identification. 3003 if (getTriple().getArch() == llvm::Triple::x86_64) { 3004 Builder.defineMacro("__amd64__"); 3005 Builder.defineMacro("__amd64"); 3006 Builder.defineMacro("__x86_64"); 3007 Builder.defineMacro("__x86_64__"); 3008 if (getTriple().getArchName() == "x86_64h") { 3009 Builder.defineMacro("__x86_64h"); 3010 Builder.defineMacro("__x86_64h__"); 3011 } 3012 } else { 3013 DefineStd(Builder, "i386", Opts); 3014 } 3015 3016 // Subtarget options. 3017 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3018 // truly should be based on -mtune options. 3019 switch (CPU) { 3020 case CK_Generic: 3021 break; 3022 case CK_i386: 3023 // The rest are coming from the i386 define above. 3024 Builder.defineMacro("__tune_i386__"); 3025 break; 3026 case CK_i486: 3027 case CK_WinChipC6: 3028 case CK_WinChip2: 3029 case CK_C3: 3030 defineCPUMacros(Builder, "i486"); 3031 break; 3032 case CK_PentiumMMX: 3033 Builder.defineMacro("__pentium_mmx__"); 3034 Builder.defineMacro("__tune_pentium_mmx__"); 3035 // Fallthrough 3036 case CK_i586: 3037 case CK_Pentium: 3038 defineCPUMacros(Builder, "i586"); 3039 defineCPUMacros(Builder, "pentium"); 3040 break; 3041 case CK_Pentium3: 3042 case CK_Pentium3M: 3043 case CK_PentiumM: 3044 Builder.defineMacro("__tune_pentium3__"); 3045 // Fallthrough 3046 case CK_Pentium2: 3047 case CK_C3_2: 3048 Builder.defineMacro("__tune_pentium2__"); 3049 // Fallthrough 3050 case CK_PentiumPro: 3051 Builder.defineMacro("__tune_i686__"); 3052 Builder.defineMacro("__tune_pentiumpro__"); 3053 // Fallthrough 3054 case CK_i686: 3055 Builder.defineMacro("__i686"); 3056 Builder.defineMacro("__i686__"); 3057 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3058 Builder.defineMacro("__pentiumpro"); 3059 Builder.defineMacro("__pentiumpro__"); 3060 break; 3061 case CK_Pentium4: 3062 case CK_Pentium4M: 3063 defineCPUMacros(Builder, "pentium4"); 3064 break; 3065 case CK_Yonah: 3066 case CK_Prescott: 3067 case CK_Nocona: 3068 defineCPUMacros(Builder, "nocona"); 3069 break; 3070 case CK_Core2: 3071 case CK_Penryn: 3072 defineCPUMacros(Builder, "core2"); 3073 break; 3074 case CK_Bonnell: 3075 defineCPUMacros(Builder, "atom"); 3076 break; 3077 case CK_Silvermont: 3078 defineCPUMacros(Builder, "slm"); 3079 break; 3080 case CK_Nehalem: 3081 case CK_Westmere: 3082 case CK_SandyBridge: 3083 case CK_IvyBridge: 3084 case CK_Haswell: 3085 case CK_Broadwell: 3086 // FIXME: Historically, we defined this legacy name, it would be nice to 3087 // remove it at some point. We've never exposed fine-grained names for 3088 // recent primary x86 CPUs, and we should keep it that way. 3089 defineCPUMacros(Builder, "corei7"); 3090 break; 3091 case CK_Skylake: 3092 // FIXME: Historically, we defined this legacy name, it would be nice to 3093 // remove it at some point. This is the only fine-grained CPU macro in the 3094 // main intel CPU line, and it would be better to not have these and force 3095 // people to use ISA macros. 3096 defineCPUMacros(Builder, "skx"); 3097 break; 3098 case CK_KNL: 3099 defineCPUMacros(Builder, "knl"); 3100 break; 3101 case CK_K6_2: 3102 Builder.defineMacro("__k6_2__"); 3103 Builder.defineMacro("__tune_k6_2__"); 3104 // Fallthrough 3105 case CK_K6_3: 3106 if (CPU != CK_K6_2) { // In case of fallthrough 3107 // FIXME: GCC may be enabling these in cases where some other k6 3108 // architecture is specified but -m3dnow is explicitly provided. The 3109 // exact semantics need to be determined and emulated here. 3110 Builder.defineMacro("__k6_3__"); 3111 Builder.defineMacro("__tune_k6_3__"); 3112 } 3113 // Fallthrough 3114 case CK_K6: 3115 defineCPUMacros(Builder, "k6"); 3116 break; 3117 case CK_Athlon: 3118 case CK_AthlonThunderbird: 3119 case CK_Athlon4: 3120 case CK_AthlonXP: 3121 case CK_AthlonMP: 3122 defineCPUMacros(Builder, "athlon"); 3123 if (SSELevel != NoSSE) { 3124 Builder.defineMacro("__athlon_sse__"); 3125 Builder.defineMacro("__tune_athlon_sse__"); 3126 } 3127 break; 3128 case CK_K8: 3129 case CK_K8SSE3: 3130 case CK_x86_64: 3131 case CK_Opteron: 3132 case CK_OpteronSSE3: 3133 case CK_Athlon64: 3134 case CK_Athlon64SSE3: 3135 case CK_AthlonFX: 3136 defineCPUMacros(Builder, "k8"); 3137 break; 3138 case CK_AMDFAM10: 3139 defineCPUMacros(Builder, "amdfam10"); 3140 break; 3141 case CK_BTVER1: 3142 defineCPUMacros(Builder, "btver1"); 3143 break; 3144 case CK_BTVER2: 3145 defineCPUMacros(Builder, "btver2"); 3146 break; 3147 case CK_BDVER1: 3148 defineCPUMacros(Builder, "bdver1"); 3149 break; 3150 case CK_BDVER2: 3151 defineCPUMacros(Builder, "bdver2"); 3152 break; 3153 case CK_BDVER3: 3154 defineCPUMacros(Builder, "bdver3"); 3155 break; 3156 case CK_BDVER4: 3157 defineCPUMacros(Builder, "bdver4"); 3158 break; 3159 case CK_Geode: 3160 defineCPUMacros(Builder, "geode"); 3161 break; 3162 } 3163 3164 // Target properties. 3165 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3166 3167 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3168 // functions in glibc header files that use FP Stack inline asm which the 3169 // backend can't deal with (PR879). 3170 Builder.defineMacro("__NO_MATH_INLINES"); 3171 3172 if (HasAES) 3173 Builder.defineMacro("__AES__"); 3174 3175 if (HasPCLMUL) 3176 Builder.defineMacro("__PCLMUL__"); 3177 3178 if (HasLZCNT) 3179 Builder.defineMacro("__LZCNT__"); 3180 3181 if (HasRDRND) 3182 Builder.defineMacro("__RDRND__"); 3183 3184 if (HasFSGSBASE) 3185 Builder.defineMacro("__FSGSBASE__"); 3186 3187 if (HasBMI) 3188 Builder.defineMacro("__BMI__"); 3189 3190 if (HasBMI2) 3191 Builder.defineMacro("__BMI2__"); 3192 3193 if (HasPOPCNT) 3194 Builder.defineMacro("__POPCNT__"); 3195 3196 if (HasRTM) 3197 Builder.defineMacro("__RTM__"); 3198 3199 if (HasPRFCHW) 3200 Builder.defineMacro("__PRFCHW__"); 3201 3202 if (HasRDSEED) 3203 Builder.defineMacro("__RDSEED__"); 3204 3205 if (HasADX) 3206 Builder.defineMacro("__ADX__"); 3207 3208 if (HasTBM) 3209 Builder.defineMacro("__TBM__"); 3210 3211 switch (XOPLevel) { 3212 case XOP: 3213 Builder.defineMacro("__XOP__"); 3214 case FMA4: 3215 Builder.defineMacro("__FMA4__"); 3216 case SSE4A: 3217 Builder.defineMacro("__SSE4A__"); 3218 case NoXOP: 3219 break; 3220 } 3221 3222 if (HasFMA) 3223 Builder.defineMacro("__FMA__"); 3224 3225 if (HasF16C) 3226 Builder.defineMacro("__F16C__"); 3227 3228 if (HasAVX512CD) 3229 Builder.defineMacro("__AVX512CD__"); 3230 if (HasAVX512ER) 3231 Builder.defineMacro("__AVX512ER__"); 3232 if (HasAVX512PF) 3233 Builder.defineMacro("__AVX512PF__"); 3234 if (HasAVX512DQ) 3235 Builder.defineMacro("__AVX512DQ__"); 3236 if (HasAVX512BW) 3237 Builder.defineMacro("__AVX512BW__"); 3238 if (HasAVX512VL) 3239 Builder.defineMacro("__AVX512VL__"); 3240 3241 if (HasSHA) 3242 Builder.defineMacro("__SHA__"); 3243 3244 if (HasCX16) 3245 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3246 3247 // Each case falls through to the previous one here. 3248 switch (SSELevel) { 3249 case AVX512F: 3250 Builder.defineMacro("__AVX512F__"); 3251 case AVX2: 3252 Builder.defineMacro("__AVX2__"); 3253 case AVX: 3254 Builder.defineMacro("__AVX__"); 3255 case SSE42: 3256 Builder.defineMacro("__SSE4_2__"); 3257 case SSE41: 3258 Builder.defineMacro("__SSE4_1__"); 3259 case SSSE3: 3260 Builder.defineMacro("__SSSE3__"); 3261 case SSE3: 3262 Builder.defineMacro("__SSE3__"); 3263 case SSE2: 3264 Builder.defineMacro("__SSE2__"); 3265 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3266 case SSE1: 3267 Builder.defineMacro("__SSE__"); 3268 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3269 case NoSSE: 3270 break; 3271 } 3272 3273 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3274 switch (SSELevel) { 3275 case AVX512F: 3276 case AVX2: 3277 case AVX: 3278 case SSE42: 3279 case SSE41: 3280 case SSSE3: 3281 case SSE3: 3282 case SSE2: 3283 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3284 break; 3285 case SSE1: 3286 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3287 break; 3288 default: 3289 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3290 } 3291 } 3292 3293 // Each case falls through to the previous one here. 3294 switch (MMX3DNowLevel) { 3295 case AMD3DNowAthlon: 3296 Builder.defineMacro("__3dNOW_A__"); 3297 case AMD3DNow: 3298 Builder.defineMacro("__3dNOW__"); 3299 case MMX: 3300 Builder.defineMacro("__MMX__"); 3301 case NoMMX3DNow: 3302 break; 3303 } 3304 3305 if (CPU >= CK_i486) { 3306 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3307 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3308 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3309 } 3310 if (CPU >= CK_i586) 3311 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3312 } 3313 3314 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3315 return llvm::StringSwitch<bool>(Feature) 3316 .Case("aes", HasAES) 3317 .Case("avx", SSELevel >= AVX) 3318 .Case("avx2", SSELevel >= AVX2) 3319 .Case("avx512f", SSELevel >= AVX512F) 3320 .Case("avx512cd", HasAVX512CD) 3321 .Case("avx512er", HasAVX512ER) 3322 .Case("avx512pf", HasAVX512PF) 3323 .Case("avx512dq", HasAVX512DQ) 3324 .Case("avx512bw", HasAVX512BW) 3325 .Case("avx512vl", HasAVX512VL) 3326 .Case("bmi", HasBMI) 3327 .Case("bmi2", HasBMI2) 3328 .Case("cx16", HasCX16) 3329 .Case("f16c", HasF16C) 3330 .Case("fma", HasFMA) 3331 .Case("fma4", XOPLevel >= FMA4) 3332 .Case("fsgsbase", HasFSGSBASE) 3333 .Case("lzcnt", HasLZCNT) 3334 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3335 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3336 .Case("mmx", MMX3DNowLevel >= MMX) 3337 .Case("pclmul", HasPCLMUL) 3338 .Case("popcnt", HasPOPCNT) 3339 .Case("prfchw", HasPRFCHW) 3340 .Case("rdrnd", HasRDRND) 3341 .Case("rdseed", HasRDSEED) 3342 .Case("rtm", HasRTM) 3343 .Case("sha", HasSHA) 3344 .Case("sse", SSELevel >= SSE1) 3345 .Case("sse2", SSELevel >= SSE2) 3346 .Case("sse3", SSELevel >= SSE3) 3347 .Case("ssse3", SSELevel >= SSSE3) 3348 .Case("sse4.1", SSELevel >= SSE41) 3349 .Case("sse4.2", SSELevel >= SSE42) 3350 .Case("sse4a", XOPLevel >= SSE4A) 3351 .Case("tbm", HasTBM) 3352 .Case("x86", true) 3353 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3354 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3355 .Case("xop", XOPLevel >= XOP) 3356 .Default(false); 3357 } 3358 3359 // We can't use a generic validation scheme for the features accepted here 3360 // versus subtarget features accepted in the target attribute because the 3361 // bitfield structure that's initialized in the runtime only supports the 3362 // below currently rather than the full range of subtarget features. (See 3363 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3364 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3365 return llvm::StringSwitch<bool>(FeatureStr) 3366 .Case("cmov", true) 3367 .Case("mmx", true) 3368 .Case("popcnt", true) 3369 .Case("sse", true) 3370 .Case("sse2", true) 3371 .Case("sse3", true) 3372 .Case("sse4.1", true) 3373 .Case("sse4.2", true) 3374 .Case("avx", true) 3375 .Case("avx2", true) 3376 .Case("sse4a", true) 3377 .Case("fma4", true) 3378 .Case("xop", true) 3379 .Case("fma", true) 3380 .Case("avx512f", true) 3381 .Case("bmi", true) 3382 .Case("bmi2", true) 3383 .Default(false); 3384 } 3385 3386 bool 3387 X86TargetInfo::validateAsmConstraint(const char *&Name, 3388 TargetInfo::ConstraintInfo &Info) const { 3389 switch (*Name) { 3390 default: return false; 3391 case 'I': 3392 Info.setRequiresImmediate(0, 31); 3393 return true; 3394 case 'J': 3395 Info.setRequiresImmediate(0, 63); 3396 return true; 3397 case 'K': 3398 Info.setRequiresImmediate(-128, 127); 3399 return true; 3400 case 'L': 3401 // FIXME: properly analyze this constraint: 3402 // must be one of 0xff, 0xffff, or 0xffffffff 3403 return true; 3404 case 'M': 3405 Info.setRequiresImmediate(0, 3); 3406 return true; 3407 case 'N': 3408 Info.setRequiresImmediate(0, 255); 3409 return true; 3410 case 'O': 3411 Info.setRequiresImmediate(0, 127); 3412 return true; 3413 case 'Y': // first letter of a pair: 3414 switch (*(Name+1)) { 3415 default: return false; 3416 case '0': // First SSE register. 3417 case 't': // Any SSE register, when SSE2 is enabled. 3418 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3419 case 'm': // any MMX register, when inter-unit moves enabled. 3420 break; // falls through to setAllowsRegister. 3421 } 3422 case 'f': // any x87 floating point stack register. 3423 // Constraint 'f' cannot be used for output operands. 3424 if (Info.ConstraintStr[0] == '=') 3425 return false; 3426 3427 Info.setAllowsRegister(); 3428 return true; 3429 case 'a': // eax. 3430 case 'b': // ebx. 3431 case 'c': // ecx. 3432 case 'd': // edx. 3433 case 'S': // esi. 3434 case 'D': // edi. 3435 case 'A': // edx:eax. 3436 case 't': // top of floating point stack. 3437 case 'u': // second from top of floating point stack. 3438 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3439 case 'y': // Any MMX register. 3440 case 'x': // Any SSE register. 3441 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3442 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3443 case 'l': // "Index" registers: any general register that can be used as an 3444 // index in a base+index memory access. 3445 Info.setAllowsRegister(); 3446 return true; 3447 case 'C': // SSE floating point constant. 3448 case 'G': // x87 floating point constant. 3449 case 'e': // 32-bit signed integer constant for use with zero-extending 3450 // x86_64 instructions. 3451 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3452 // x86_64 instructions. 3453 return true; 3454 } 3455 } 3456 3457 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3458 unsigned Size) const { 3459 // Strip off constraint modifiers. 3460 while (Constraint[0] == '=' || 3461 Constraint[0] == '+' || 3462 Constraint[0] == '&') 3463 Constraint = Constraint.substr(1); 3464 3465 return validateOperandSize(Constraint, Size); 3466 } 3467 3468 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3469 unsigned Size) const { 3470 return validateOperandSize(Constraint, Size); 3471 } 3472 3473 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3474 unsigned Size) const { 3475 switch (Constraint[0]) { 3476 default: break; 3477 case 'y': 3478 return Size <= 64; 3479 case 'f': 3480 case 't': 3481 case 'u': 3482 return Size <= 128; 3483 case 'x': 3484 // 256-bit ymm registers can be used if target supports AVX. 3485 return Size <= (SSELevel >= AVX ? 256U : 128U); 3486 } 3487 3488 return true; 3489 } 3490 3491 std::string 3492 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3493 switch (*Constraint) { 3494 case 'a': return std::string("{ax}"); 3495 case 'b': return std::string("{bx}"); 3496 case 'c': return std::string("{cx}"); 3497 case 'd': return std::string("{dx}"); 3498 case 'S': return std::string("{si}"); 3499 case 'D': return std::string("{di}"); 3500 case 'p': // address 3501 return std::string("im"); 3502 case 't': // top of floating point stack. 3503 return std::string("{st}"); 3504 case 'u': // second from top of floating point stack. 3505 return std::string("{st(1)}"); // second from top of floating point stack. 3506 default: 3507 return std::string(1, *Constraint); 3508 } 3509 } 3510 3511 // X86-32 generic target 3512 class X86_32TargetInfo : public X86TargetInfo { 3513 public: 3514 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3515 DoubleAlign = LongLongAlign = 32; 3516 LongDoubleWidth = 96; 3517 LongDoubleAlign = 32; 3518 SuitableAlign = 128; 3519 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3520 SizeType = UnsignedInt; 3521 PtrDiffType = SignedInt; 3522 IntPtrType = SignedInt; 3523 RegParmMax = 3; 3524 3525 // Use fpret for all types. 3526 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3527 (1 << TargetInfo::Double) | 3528 (1 << TargetInfo::LongDouble)); 3529 3530 // x86-32 has atomics up to 8 bytes 3531 // FIXME: Check that we actually have cmpxchg8b before setting 3532 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3533 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3534 } 3535 BuiltinVaListKind getBuiltinVaListKind() const override { 3536 return TargetInfo::CharPtrBuiltinVaList; 3537 } 3538 3539 int getEHDataRegisterNumber(unsigned RegNo) const override { 3540 if (RegNo == 0) return 0; 3541 if (RegNo == 1) return 2; 3542 return -1; 3543 } 3544 bool validateOperandSize(StringRef Constraint, 3545 unsigned Size) const override { 3546 switch (Constraint[0]) { 3547 default: break; 3548 case 'R': 3549 case 'q': 3550 case 'Q': 3551 case 'a': 3552 case 'b': 3553 case 'c': 3554 case 'd': 3555 case 'S': 3556 case 'D': 3557 return Size <= 32; 3558 case 'A': 3559 return Size <= 64; 3560 } 3561 3562 return X86TargetInfo::validateOperandSize(Constraint, Size); 3563 } 3564 }; 3565 3566 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3567 public: 3568 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3569 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3570 3571 unsigned getFloatEvalMethod() const override { 3572 unsigned Major, Minor, Micro; 3573 getTriple().getOSVersion(Major, Minor, Micro); 3574 // New NetBSD uses the default rounding mode. 3575 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3576 return X86_32TargetInfo::getFloatEvalMethod(); 3577 // NetBSD before 6.99.26 defaults to "double" rounding. 3578 return 1; 3579 } 3580 }; 3581 3582 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3583 public: 3584 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3585 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3586 SizeType = UnsignedLong; 3587 IntPtrType = SignedLong; 3588 PtrDiffType = SignedLong; 3589 } 3590 }; 3591 3592 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3593 public: 3594 BitrigI386TargetInfo(const llvm::Triple &Triple) 3595 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3596 SizeType = UnsignedLong; 3597 IntPtrType = SignedLong; 3598 PtrDiffType = SignedLong; 3599 } 3600 }; 3601 3602 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3603 public: 3604 DarwinI386TargetInfo(const llvm::Triple &Triple) 3605 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3606 LongDoubleWidth = 128; 3607 LongDoubleAlign = 128; 3608 SuitableAlign = 128; 3609 MaxVectorAlign = 256; 3610 SizeType = UnsignedLong; 3611 IntPtrType = SignedLong; 3612 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3613 HasAlignMac68kSupport = true; 3614 } 3615 3616 }; 3617 3618 // x86-32 Windows target 3619 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3620 public: 3621 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3622 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3623 WCharType = UnsignedShort; 3624 DoubleAlign = LongLongAlign = 64; 3625 bool IsWinCOFF = 3626 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3627 DescriptionString = IsWinCOFF 3628 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3629 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3630 } 3631 void getTargetDefines(const LangOptions &Opts, 3632 MacroBuilder &Builder) const override { 3633 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3634 } 3635 }; 3636 3637 // x86-32 Windows Visual Studio target 3638 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3639 public: 3640 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3641 : WindowsX86_32TargetInfo(Triple) { 3642 LongDoubleWidth = LongDoubleAlign = 64; 3643 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3644 } 3645 void getTargetDefines(const LangOptions &Opts, 3646 MacroBuilder &Builder) const override { 3647 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3648 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3649 // The value of the following reflects processor type. 3650 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3651 // We lost the original triple, so we use the default. 3652 Builder.defineMacro("_M_IX86", "600"); 3653 } 3654 }; 3655 } // end anonymous namespace 3656 3657 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3658 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang supports 3659 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3660 // macro anyway for pre-processor compatibility. 3661 if (Opts.MicrosoftExt) 3662 Builder.defineMacro("__declspec", "__declspec"); 3663 else 3664 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3665 3666 if (!Opts.MicrosoftExt) { 3667 // Provide macros for all the calling convention keywords. Provide both 3668 // single and double underscore prefixed variants. These are available on 3669 // x64 as well as x86, even though they have no effect. 3670 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3671 for (const char *CC : CCs) { 3672 std::string GCCSpelling = "__attribute__((__"; 3673 GCCSpelling += CC; 3674 GCCSpelling += "__))"; 3675 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3676 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3677 } 3678 } 3679 } 3680 3681 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3682 Builder.defineMacro("__MSVCRT__"); 3683 Builder.defineMacro("__MINGW32__"); 3684 addCygMingDefines(Opts, Builder); 3685 } 3686 3687 namespace { 3688 // x86-32 MinGW target 3689 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3690 public: 3691 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3692 : WindowsX86_32TargetInfo(Triple) {} 3693 void getTargetDefines(const LangOptions &Opts, 3694 MacroBuilder &Builder) const override { 3695 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3696 DefineStd(Builder, "WIN32", Opts); 3697 DefineStd(Builder, "WINNT", Opts); 3698 Builder.defineMacro("_X86_"); 3699 addMinGWDefines(Opts, Builder); 3700 } 3701 }; 3702 3703 // x86-32 Cygwin target 3704 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3705 public: 3706 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3707 : X86_32TargetInfo(Triple) { 3708 TLSSupported = false; 3709 WCharType = UnsignedShort; 3710 DoubleAlign = LongLongAlign = 64; 3711 DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3712 } 3713 void getTargetDefines(const LangOptions &Opts, 3714 MacroBuilder &Builder) const override { 3715 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3716 Builder.defineMacro("_X86_"); 3717 Builder.defineMacro("__CYGWIN__"); 3718 Builder.defineMacro("__CYGWIN32__"); 3719 addCygMingDefines(Opts, Builder); 3720 DefineStd(Builder, "unix", Opts); 3721 if (Opts.CPlusPlus) 3722 Builder.defineMacro("_GNU_SOURCE"); 3723 } 3724 }; 3725 3726 // x86-32 Haiku target 3727 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3728 public: 3729 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3730 SizeType = UnsignedLong; 3731 IntPtrType = SignedLong; 3732 PtrDiffType = SignedLong; 3733 ProcessIDType = SignedLong; 3734 this->UserLabelPrefix = ""; 3735 this->TLSSupported = false; 3736 } 3737 void getTargetDefines(const LangOptions &Opts, 3738 MacroBuilder &Builder) const override { 3739 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3740 Builder.defineMacro("__INTEL__"); 3741 Builder.defineMacro("__HAIKU__"); 3742 } 3743 }; 3744 3745 // RTEMS Target 3746 template<typename Target> 3747 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3748 protected: 3749 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3750 MacroBuilder &Builder) const override { 3751 // RTEMS defines; list based off of gcc output 3752 3753 Builder.defineMacro("__rtems__"); 3754 Builder.defineMacro("__ELF__"); 3755 } 3756 3757 public: 3758 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3759 this->UserLabelPrefix = ""; 3760 3761 switch (Triple.getArch()) { 3762 default: 3763 case llvm::Triple::x86: 3764 // this->MCountName = ".mcount"; 3765 break; 3766 case llvm::Triple::mips: 3767 case llvm::Triple::mipsel: 3768 case llvm::Triple::ppc: 3769 case llvm::Triple::ppc64: 3770 case llvm::Triple::ppc64le: 3771 // this->MCountName = "_mcount"; 3772 break; 3773 case llvm::Triple::arm: 3774 // this->MCountName = "__mcount"; 3775 break; 3776 } 3777 } 3778 }; 3779 3780 // x86-32 RTEMS target 3781 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3782 public: 3783 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3784 SizeType = UnsignedLong; 3785 IntPtrType = SignedLong; 3786 PtrDiffType = SignedLong; 3787 this->UserLabelPrefix = ""; 3788 } 3789 void getTargetDefines(const LangOptions &Opts, 3790 MacroBuilder &Builder) const override { 3791 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3792 Builder.defineMacro("__INTEL__"); 3793 Builder.defineMacro("__rtems__"); 3794 } 3795 }; 3796 3797 // x86-64 generic target 3798 class X86_64TargetInfo : public X86TargetInfo { 3799 public: 3800 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3801 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3802 bool IsWinCOFF = 3803 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3804 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3805 LongDoubleWidth = 128; 3806 LongDoubleAlign = 128; 3807 LargeArrayMinWidth = 128; 3808 LargeArrayAlign = 128; 3809 SuitableAlign = 128; 3810 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3811 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3812 IntPtrType = IsX32 ? SignedInt : SignedLong; 3813 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3814 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3815 RegParmMax = 6; 3816 3817 // Pointers are 32-bit in x32. 3818 DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3819 : IsWinCOFF 3820 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3821 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3822 3823 // Use fpret only for long double. 3824 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3825 3826 // Use fp2ret for _Complex long double. 3827 ComplexLongDoubleUsesFP2Ret = true; 3828 3829 // x86-64 has atomics up to 16 bytes. 3830 MaxAtomicPromoteWidth = 128; 3831 MaxAtomicInlineWidth = 128; 3832 } 3833 BuiltinVaListKind getBuiltinVaListKind() const override { 3834 return TargetInfo::X86_64ABIBuiltinVaList; 3835 } 3836 3837 int getEHDataRegisterNumber(unsigned RegNo) const override { 3838 if (RegNo == 0) return 0; 3839 if (RegNo == 1) return 1; 3840 return -1; 3841 } 3842 3843 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3844 return (CC == CC_C || 3845 CC == CC_X86VectorCall || 3846 CC == CC_IntelOclBicc || 3847 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3848 } 3849 3850 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3851 return CC_C; 3852 } 3853 3854 // for x32 we need it here explicitly 3855 bool hasInt128Type() const override { return true; } 3856 }; 3857 3858 // x86-64 Windows target 3859 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3860 public: 3861 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3862 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3863 WCharType = UnsignedShort; 3864 LongWidth = LongAlign = 32; 3865 DoubleAlign = LongLongAlign = 64; 3866 IntMaxType = SignedLongLong; 3867 Int64Type = SignedLongLong; 3868 SizeType = UnsignedLongLong; 3869 PtrDiffType = SignedLongLong; 3870 IntPtrType = SignedLongLong; 3871 this->UserLabelPrefix = ""; 3872 } 3873 3874 void getTargetDefines(const LangOptions &Opts, 3875 MacroBuilder &Builder) const override { 3876 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3877 Builder.defineMacro("_WIN64"); 3878 } 3879 3880 BuiltinVaListKind getBuiltinVaListKind() const override { 3881 return TargetInfo::CharPtrBuiltinVaList; 3882 } 3883 3884 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3885 switch (CC) { 3886 case CC_X86StdCall: 3887 case CC_X86ThisCall: 3888 case CC_X86FastCall: 3889 return CCCR_Ignore; 3890 case CC_C: 3891 case CC_X86VectorCall: 3892 case CC_IntelOclBicc: 3893 case CC_X86_64SysV: 3894 return CCCR_OK; 3895 default: 3896 return CCCR_Warning; 3897 } 3898 } 3899 }; 3900 3901 // x86-64 Windows Visual Studio target 3902 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3903 public: 3904 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3905 : WindowsX86_64TargetInfo(Triple) { 3906 LongDoubleWidth = LongDoubleAlign = 64; 3907 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3908 } 3909 void getTargetDefines(const LangOptions &Opts, 3910 MacroBuilder &Builder) const override { 3911 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3912 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3913 Builder.defineMacro("_M_X64"); 3914 Builder.defineMacro("_M_AMD64"); 3915 } 3916 }; 3917 3918 // x86-64 MinGW target 3919 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3920 public: 3921 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3922 : WindowsX86_64TargetInfo(Triple) {} 3923 void getTargetDefines(const LangOptions &Opts, 3924 MacroBuilder &Builder) const override { 3925 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3926 DefineStd(Builder, "WIN64", Opts); 3927 Builder.defineMacro("__MINGW64__"); 3928 addMinGWDefines(Opts, Builder); 3929 3930 // GCC defines this macro when it is using __gxx_personality_seh0. 3931 if (!Opts.SjLjExceptions) 3932 Builder.defineMacro("__SEH__"); 3933 } 3934 }; 3935 3936 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3937 public: 3938 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3939 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3940 Int64Type = SignedLongLong; 3941 MaxVectorAlign = 256; 3942 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3943 llvm::Triple T = llvm::Triple(Triple); 3944 if (T.isiOS()) 3945 UseSignedCharForObjCBool = false; 3946 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3947 } 3948 }; 3949 3950 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3951 public: 3952 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3953 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3954 IntMaxType = SignedLongLong; 3955 Int64Type = SignedLongLong; 3956 } 3957 }; 3958 3959 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3960 public: 3961 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3962 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3963 IntMaxType = SignedLongLong; 3964 Int64Type = SignedLongLong; 3965 } 3966 }; 3967 3968 class ARMTargetInfo : public TargetInfo { 3969 // Possible FPU choices. 3970 enum FPUMode { 3971 VFP2FPU = (1 << 0), 3972 VFP3FPU = (1 << 1), 3973 VFP4FPU = (1 << 2), 3974 NeonFPU = (1 << 3), 3975 FPARMV8 = (1 << 4) 3976 }; 3977 3978 // Possible HWDiv features. 3979 enum HWDivMode { 3980 HWDivThumb = (1 << 0), 3981 HWDivARM = (1 << 1) 3982 }; 3983 3984 static bool FPUModeIsVFP(FPUMode Mode) { 3985 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3986 } 3987 3988 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3989 static const char * const GCCRegNames[]; 3990 3991 std::string ABI, CPU; 3992 3993 enum { 3994 FP_Default, 3995 FP_VFP, 3996 FP_Neon 3997 } FPMath; 3998 3999 unsigned FPU : 5; 4000 4001 unsigned IsAAPCS : 1; 4002 unsigned IsThumb : 1; 4003 unsigned HWDiv : 2; 4004 4005 // Initialized via features. 4006 unsigned SoftFloat : 1; 4007 unsigned SoftFloatABI : 1; 4008 4009 unsigned CRC : 1; 4010 unsigned Crypto : 1; 4011 4012 // ACLE 6.5.1 Hardware floating point 4013 enum { 4014 HW_FP_HP = (1 << 1), /// half (16-bit) 4015 HW_FP_SP = (1 << 2), /// single (32-bit) 4016 HW_FP_DP = (1 << 3), /// double (64-bit) 4017 }; 4018 uint32_t HW_FP; 4019 4020 static const Builtin::Info BuiltinInfo[]; 4021 4022 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 4023 StringRef ArchName = T.getArchName(); 4024 if (T.getArch() == llvm::Triple::arm || 4025 T.getArch() == llvm::Triple::armeb) { 4026 StringRef VersionStr; 4027 if (ArchName.startswith("armv")) 4028 VersionStr = ArchName.substr(4, 1); 4029 else if (ArchName.startswith("armebv")) 4030 VersionStr = ArchName.substr(6, 1); 4031 else 4032 return false; 4033 unsigned Version; 4034 if (VersionStr.getAsInteger(10, Version)) 4035 return false; 4036 return Version >= 6; 4037 } 4038 assert(T.getArch() == llvm::Triple::thumb || 4039 T.getArch() == llvm::Triple::thumbeb); 4040 StringRef VersionStr; 4041 if (ArchName.startswith("thumbv")) 4042 VersionStr = ArchName.substr(6, 1); 4043 else if (ArchName.startswith("thumbebv")) 4044 VersionStr = ArchName.substr(8, 1); 4045 else 4046 return false; 4047 unsigned Version; 4048 if (VersionStr.getAsInteger(10, Version)) 4049 return false; 4050 return Version >= 7; 4051 } 4052 4053 void setABIAAPCS() { 4054 IsAAPCS = true; 4055 4056 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4057 const llvm::Triple &T = getTriple(); 4058 4059 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4060 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4061 T.getOS() == llvm::Triple::Bitrig) 4062 SizeType = UnsignedLong; 4063 else 4064 SizeType = UnsignedInt; 4065 4066 switch (T.getOS()) { 4067 case llvm::Triple::NetBSD: 4068 WCharType = SignedInt; 4069 break; 4070 case llvm::Triple::Win32: 4071 WCharType = UnsignedShort; 4072 break; 4073 case llvm::Triple::Linux: 4074 default: 4075 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4076 WCharType = UnsignedInt; 4077 break; 4078 } 4079 4080 UseBitFieldTypeAlignment = true; 4081 4082 ZeroLengthBitfieldBoundary = 0; 4083 4084 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4085 // so set preferred for small types to 32. 4086 if (T.isOSBinFormatMachO()) { 4087 DescriptionString = 4088 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4089 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4090 } else if (T.isOSWindows()) { 4091 assert(!BigEndian && "Windows on ARM does not support big endian"); 4092 DescriptionString = "e" 4093 "-m:w" 4094 "-p:32:32" 4095 "-i64:64" 4096 "-v128:64:128" 4097 "-a:0:32" 4098 "-n32" 4099 "-S64"; 4100 } else if (T.isOSNaCl()) { 4101 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4102 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4103 } else { 4104 DescriptionString = 4105 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4106 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4107 } 4108 4109 // FIXME: Enumerated types are variable width in straight AAPCS. 4110 } 4111 4112 void setABIAPCS() { 4113 const llvm::Triple &T = getTriple(); 4114 4115 IsAAPCS = false; 4116 4117 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4118 4119 // size_t is unsigned int on FreeBSD. 4120 if (T.getOS() == llvm::Triple::FreeBSD) 4121 SizeType = UnsignedInt; 4122 else 4123 SizeType = UnsignedLong; 4124 4125 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4126 WCharType = SignedInt; 4127 4128 // Do not respect the alignment of bit-field types when laying out 4129 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4130 UseBitFieldTypeAlignment = false; 4131 4132 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4133 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4134 /// gcc. 4135 ZeroLengthBitfieldBoundary = 32; 4136 4137 if (T.isOSBinFormatMachO()) 4138 DescriptionString = 4139 BigEndian 4140 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4141 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4142 else 4143 DescriptionString = 4144 BigEndian 4145 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4146 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4147 4148 // FIXME: Override "preferred align" for double and long long. 4149 } 4150 4151 public: 4152 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4153 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 4154 IsAAPCS(true), HW_FP(0) { 4155 BigEndian = IsBigEndian; 4156 4157 switch (getTriple().getOS()) { 4158 case llvm::Triple::NetBSD: 4159 PtrDiffType = SignedLong; 4160 break; 4161 default: 4162 PtrDiffType = SignedInt; 4163 break; 4164 } 4165 4166 // {} in inline assembly are neon specifiers, not assembly variant 4167 // specifiers. 4168 NoAsmVariants = true; 4169 4170 // FIXME: Should we just treat this as a feature? 4171 IsThumb = getTriple().getArchName().startswith("thumb"); 4172 4173 // FIXME: This duplicates code from the driver that sets the -target-abi 4174 // option - this code is used if -target-abi isn't passed and should 4175 // be unified in some way. 4176 if (Triple.isOSBinFormatMachO()) { 4177 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4178 // the frontend matches that. 4179 if (Triple.getEnvironment() == llvm::Triple::EABI || 4180 Triple.getOS() == llvm::Triple::UnknownOS || 4181 StringRef(CPU).startswith("cortex-m")) { 4182 setABI("aapcs"); 4183 } else { 4184 setABI("apcs-gnu"); 4185 } 4186 } else if (Triple.isOSWindows()) { 4187 // FIXME: this is invalid for WindowsCE 4188 setABI("aapcs"); 4189 } else { 4190 // Select the default based on the platform. 4191 switch (Triple.getEnvironment()) { 4192 case llvm::Triple::Android: 4193 case llvm::Triple::GNUEABI: 4194 case llvm::Triple::GNUEABIHF: 4195 setABI("aapcs-linux"); 4196 break; 4197 case llvm::Triple::EABIHF: 4198 case llvm::Triple::EABI: 4199 setABI("aapcs"); 4200 break; 4201 case llvm::Triple::GNU: 4202 setABI("apcs-gnu"); 4203 break; 4204 default: 4205 if (Triple.getOS() == llvm::Triple::NetBSD) 4206 setABI("apcs-gnu"); 4207 else 4208 setABI("aapcs"); 4209 break; 4210 } 4211 } 4212 4213 // ARM targets default to using the ARM C++ ABI. 4214 TheCXXABI.set(TargetCXXABI::GenericARM); 4215 4216 // ARM has atomics up to 8 bytes 4217 MaxAtomicPromoteWidth = 64; 4218 if (shouldUseInlineAtomic(getTriple())) 4219 MaxAtomicInlineWidth = 64; 4220 4221 // Do force alignment of members that follow zero length bitfields. If 4222 // the alignment of the zero-length bitfield is greater than the member 4223 // that follows it, `bar', `bar' will be aligned as the type of the 4224 // zero length bitfield. 4225 UseZeroLengthBitfieldAlignment = true; 4226 } 4227 4228 StringRef getABI() const override { return ABI; } 4229 4230 bool setABI(const std::string &Name) override { 4231 ABI = Name; 4232 4233 // The defaults (above) are for AAPCS, check if we need to change them. 4234 // 4235 // FIXME: We need support for -meabi... we could just mangle it into the 4236 // name. 4237 if (Name == "apcs-gnu") { 4238 setABIAPCS(); 4239 return true; 4240 } 4241 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4242 setABIAAPCS(); 4243 return true; 4244 } 4245 return false; 4246 } 4247 4248 // FIXME: This should be based on Arch attributes, not CPU names. 4249 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4250 StringRef ArchName = getTriple().getArchName(); 4251 unsigned ArchKind = llvm::ARMTargetParser::parseArch(ArchName); 4252 bool IsV8 = (ArchKind == llvm::ARM::AK_ARMV8A || 4253 ArchKind == llvm::ARM::AK_ARMV8_1A); 4254 4255 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 4256 Features["vfp2"] = true; 4257 else if (CPU == "cortex-a8" || CPU == "cortex-a9") { 4258 Features["vfp3"] = true; 4259 Features["neon"] = true; 4260 } 4261 else if (CPU == "cortex-a5") { 4262 Features["vfp4"] = true; 4263 Features["neon"] = true; 4264 } else if (CPU == "swift" || CPU == "cortex-a7" || 4265 CPU == "cortex-a12" || CPU == "cortex-a15" || 4266 CPU == "cortex-a17" || CPU == "krait") { 4267 Features["vfp4"] = true; 4268 Features["neon"] = true; 4269 Features["hwdiv"] = true; 4270 Features["hwdiv-arm"] = true; 4271 } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" || 4272 CPU == "cortex-a72") { 4273 Features["fp-armv8"] = true; 4274 Features["neon"] = true; 4275 Features["hwdiv"] = true; 4276 Features["hwdiv-arm"] = true; 4277 Features["crc"] = true; 4278 Features["crypto"] = true; 4279 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || IsV8) { 4280 Features["hwdiv"] = true; 4281 Features["hwdiv-arm"] = true; 4282 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" || 4283 CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") { 4284 Features["hwdiv"] = true; 4285 } 4286 } 4287 4288 bool handleTargetFeatures(std::vector<std::string> &Features, 4289 DiagnosticsEngine &Diags) override { 4290 FPU = 0; 4291 CRC = 0; 4292 Crypto = 0; 4293 SoftFloat = SoftFloatABI = false; 4294 HWDiv = 0; 4295 4296 // This does not diagnose illegal cases like having both 4297 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4298 uint32_t HW_FP_remove = 0; 4299 for (const auto &Feature : Features) { 4300 if (Feature == "+soft-float") { 4301 SoftFloat = true; 4302 } else if (Feature == "+soft-float-abi") { 4303 SoftFloatABI = true; 4304 } else if (Feature == "+vfp2") { 4305 FPU |= VFP2FPU; 4306 HW_FP |= HW_FP_SP | HW_FP_DP; 4307 } else if (Feature == "+vfp3") { 4308 FPU |= VFP3FPU; 4309 HW_FP |= HW_FP_SP | HW_FP_DP; 4310 } else if (Feature == "+vfp4") { 4311 FPU |= VFP4FPU; 4312 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4313 } else if (Feature == "+fp-armv8") { 4314 FPU |= FPARMV8; 4315 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4316 } else if (Feature == "+neon") { 4317 FPU |= NeonFPU; 4318 HW_FP |= HW_FP_SP | HW_FP_DP; 4319 } else if (Feature == "+hwdiv") { 4320 HWDiv |= HWDivThumb; 4321 } else if (Feature == "+hwdiv-arm") { 4322 HWDiv |= HWDivARM; 4323 } else if (Feature == "+crc") { 4324 CRC = 1; 4325 } else if (Feature == "+crypto") { 4326 Crypto = 1; 4327 } else if (Feature == "+fp-only-sp") { 4328 HW_FP_remove |= HW_FP_DP | HW_FP_HP; 4329 } 4330 } 4331 HW_FP &= ~HW_FP_remove; 4332 4333 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4334 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4335 return false; 4336 } 4337 4338 if (FPMath == FP_Neon) 4339 Features.push_back("+neonfp"); 4340 else if (FPMath == FP_VFP) 4341 Features.push_back("-neonfp"); 4342 4343 // Remove front-end specific options which the backend handles differently. 4344 auto Feature = 4345 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4346 if (Feature != Features.end()) 4347 Features.erase(Feature); 4348 4349 return true; 4350 } 4351 4352 bool hasFeature(StringRef Feature) const override { 4353 return llvm::StringSwitch<bool>(Feature) 4354 .Case("arm", true) 4355 .Case("softfloat", SoftFloat) 4356 .Case("thumb", IsThumb) 4357 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4358 .Case("hwdiv", HWDiv & HWDivThumb) 4359 .Case("hwdiv-arm", HWDiv & HWDivARM) 4360 .Default(false); 4361 } 4362 const char *getCPUDefineSuffix(StringRef Name) const { 4363 if(Name == "generic") { 4364 auto subarch = getTriple().getSubArch(); 4365 switch (subarch) { 4366 case llvm::Triple::SubArchType::ARMSubArch_v8_1a: 4367 return "8_1A"; 4368 default: 4369 break; 4370 } 4371 } 4372 4373 unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(Name); 4374 if (ArchKind == llvm::ARM::AK_INVALID) 4375 return ""; 4376 4377 // For most sub-arches, the build attribute CPU name is enough. 4378 // For Cortex variants, it's slightly different. 4379 switch(ArchKind) { 4380 default: 4381 return llvm::ARMTargetParser::getCPUAttr(ArchKind); 4382 case llvm::ARM::AK_ARMV6M: 4383 case llvm::ARM::AK_ARMV6SM: 4384 return "6M"; 4385 case llvm::ARM::AK_ARMV7: 4386 case llvm::ARM::AK_ARMV7A: 4387 case llvm::ARM::AK_ARMV7S: 4388 return "7A"; 4389 case llvm::ARM::AK_ARMV7R: 4390 return "7R"; 4391 case llvm::ARM::AK_ARMV7M: 4392 return "7M"; 4393 case llvm::ARM::AK_ARMV7EM: 4394 return "7EM"; 4395 case llvm::ARM::AK_ARMV8A: 4396 return "8A"; 4397 case llvm::ARM::AK_ARMV8_1A: 4398 return "8_1A"; 4399 } 4400 } 4401 const char *getCPUProfile(StringRef Name) const { 4402 if(Name == "generic") { 4403 auto subarch = getTriple().getSubArch(); 4404 switch (subarch) { 4405 case llvm::Triple::SubArchType::ARMSubArch_v8_1a: 4406 return "A"; 4407 default: 4408 break; 4409 } 4410 } 4411 4412 unsigned CPUArch = llvm::ARMTargetParser::parseCPUArch(Name); 4413 if (CPUArch == llvm::ARM::AK_INVALID) 4414 return ""; 4415 4416 StringRef ArchName = llvm::ARMTargetParser::getArchName(CPUArch); 4417 switch(llvm::ARMTargetParser::parseArchProfile(ArchName)) { 4418 case llvm::ARM::PK_A: 4419 return "A"; 4420 case llvm::ARM::PK_R: 4421 return "R"; 4422 case llvm::ARM::PK_M: 4423 return "M"; 4424 default: 4425 return ""; 4426 } 4427 } 4428 bool setCPU(const std::string &Name) override { 4429 if (!getCPUDefineSuffix(Name)) 4430 return false; 4431 4432 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4433 StringRef Profile = getCPUProfile(Name); 4434 if (Profile == "M" && MaxAtomicInlineWidth) { 4435 MaxAtomicPromoteWidth = 32; 4436 MaxAtomicInlineWidth = 32; 4437 } 4438 4439 CPU = Name; 4440 return true; 4441 } 4442 bool setFPMath(StringRef Name) override; 4443 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 4444 unsigned CPUArchVer) const { 4445 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 4446 (CPUArch.find('M') != StringRef::npos); 4447 } 4448 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 4449 unsigned CPUArchVer) const { 4450 // We check both CPUArchVer and ArchName because when only triple is 4451 // specified, the default CPU is arm1136j-s. 4452 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 4453 ArchName.endswith("v8.1a") || 4454 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 4455 } 4456 void getTargetDefines(const LangOptions &Opts, 4457 MacroBuilder &Builder) const override { 4458 // Target identification. 4459 Builder.defineMacro("__arm"); 4460 Builder.defineMacro("__arm__"); 4461 4462 // Target properties. 4463 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4464 4465 StringRef CPUArch = getCPUDefineSuffix(CPU); 4466 unsigned int CPUArchVer; 4467 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) 4468 llvm_unreachable("Invalid char for architecture version number"); 4469 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4470 4471 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4472 StringRef CPUProfile = getCPUProfile(CPU); 4473 StringRef ArchName = getTriple().getArchName(); 4474 4475 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4476 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4477 if (CPUArch[0] >= '8') { 4478 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4479 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4480 } 4481 4482 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4483 // is not defined for the M-profile. 4484 // NOTE that the deffault profile is assumed to be 'A' 4485 if (CPUProfile.empty() || CPUProfile != "M") 4486 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4487 4488 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4489 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4490 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4491 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4492 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4493 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 4494 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4495 4496 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4497 // instruction set such as ARM or Thumb. 4498 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4499 4500 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4501 4502 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4503 if (!CPUProfile.empty()) 4504 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4505 4506 // ACLE 6.5.1 Hardware Floating Point 4507 if (HW_FP) 4508 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4509 4510 // ACLE predefines. 4511 Builder.defineMacro("__ARM_ACLE", "200"); 4512 4513 // Subtarget options. 4514 4515 // FIXME: It's more complicated than this and we don't really support 4516 // interworking. 4517 // Windows on ARM does not "support" interworking 4518 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 4519 Builder.defineMacro("__THUMB_INTERWORK__"); 4520 4521 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4522 // Embedded targets on Darwin follow AAPCS, but not EABI. 4523 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4524 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4525 Builder.defineMacro("__ARM_EABI__"); 4526 Builder.defineMacro("__ARM_PCS", "1"); 4527 4528 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4529 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4530 } 4531 4532 if (SoftFloat) 4533 Builder.defineMacro("__SOFTFP__"); 4534 4535 if (CPU == "xscale") 4536 Builder.defineMacro("__XSCALE__"); 4537 4538 if (IsThumb) { 4539 Builder.defineMacro("__THUMBEL__"); 4540 Builder.defineMacro("__thumb__"); 4541 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4542 Builder.defineMacro("__thumb2__"); 4543 } 4544 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4545 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4546 4547 // Note, this is always on in gcc, even though it doesn't make sense. 4548 Builder.defineMacro("__APCS_32__"); 4549 4550 if (FPUModeIsVFP((FPUMode) FPU)) { 4551 Builder.defineMacro("__VFP_FP__"); 4552 if (FPU & VFP2FPU) 4553 Builder.defineMacro("__ARM_VFPV2__"); 4554 if (FPU & VFP3FPU) 4555 Builder.defineMacro("__ARM_VFPV3__"); 4556 if (FPU & VFP4FPU) 4557 Builder.defineMacro("__ARM_VFPV4__"); 4558 } 4559 4560 // This only gets set when Neon instructions are actually available, unlike 4561 // the VFP define, hence the soft float and arch check. This is subtly 4562 // different from gcc, we follow the intent which was that it should be set 4563 // when Neon instructions are actually available. 4564 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4565 Builder.defineMacro("__ARM_NEON"); 4566 Builder.defineMacro("__ARM_NEON__"); 4567 } 4568 4569 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4570 Opts.ShortWChar ? "2" : "4"); 4571 4572 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4573 Opts.ShortEnums ? "1" : "4"); 4574 4575 if (CRC) 4576 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4577 4578 if (Crypto) 4579 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4580 4581 if (CPUArchVer >= 6 && CPUArch != "6M") { 4582 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4583 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4584 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4585 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4586 } 4587 4588 bool is5EOrAbove = (CPUArchVer >= 6 || 4589 (CPUArchVer == 5 && 4590 CPUArch.find('E') != StringRef::npos)); 4591 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer)); 4592 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM")) 4593 Builder.defineMacro("__ARM_FEATURE_DSP"); 4594 } 4595 void getTargetBuiltins(const Builtin::Info *&Records, 4596 unsigned &NumRecords) const override { 4597 Records = BuiltinInfo; 4598 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4599 } 4600 bool isCLZForZeroUndef() const override { return false; } 4601 BuiltinVaListKind getBuiltinVaListKind() const override { 4602 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4603 } 4604 void getGCCRegNames(const char * const *&Names, 4605 unsigned &NumNames) const override; 4606 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4607 unsigned &NumAliases) const override; 4608 bool validateAsmConstraint(const char *&Name, 4609 TargetInfo::ConstraintInfo &Info) const override { 4610 switch (*Name) { 4611 default: break; 4612 case 'l': // r0-r7 4613 case 'h': // r8-r15 4614 case 'w': // VFP Floating point register single precision 4615 case 'P': // VFP Floating point register double precision 4616 Info.setAllowsRegister(); 4617 return true; 4618 case 'I': 4619 case 'J': 4620 case 'K': 4621 case 'L': 4622 case 'M': 4623 // FIXME 4624 return true; 4625 case 'Q': // A memory address that is a single base register. 4626 Info.setAllowsMemory(); 4627 return true; 4628 case 'U': // a memory reference... 4629 switch (Name[1]) { 4630 case 'q': // ...ARMV4 ldrsb 4631 case 'v': // ...VFP load/store (reg+constant offset) 4632 case 'y': // ...iWMMXt load/store 4633 case 't': // address valid for load/store opaque types wider 4634 // than 128-bits 4635 case 'n': // valid address for Neon doubleword vector load/store 4636 case 'm': // valid address for Neon element and structure load/store 4637 case 's': // valid address for non-offset loads/stores of quad-word 4638 // values in four ARM registers 4639 Info.setAllowsMemory(); 4640 Name++; 4641 return true; 4642 } 4643 } 4644 return false; 4645 } 4646 std::string convertConstraint(const char *&Constraint) const override { 4647 std::string R; 4648 switch (*Constraint) { 4649 case 'U': // Two-character constraint; add "^" hint for later parsing. 4650 R = std::string("^") + std::string(Constraint, 2); 4651 Constraint++; 4652 break; 4653 case 'p': // 'p' should be translated to 'r' by default. 4654 R = std::string("r"); 4655 break; 4656 default: 4657 return std::string(1, *Constraint); 4658 } 4659 return R; 4660 } 4661 bool 4662 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4663 std::string &SuggestedModifier) const override { 4664 bool isOutput = (Constraint[0] == '='); 4665 bool isInOut = (Constraint[0] == '+'); 4666 4667 // Strip off constraint modifiers. 4668 while (Constraint[0] == '=' || 4669 Constraint[0] == '+' || 4670 Constraint[0] == '&') 4671 Constraint = Constraint.substr(1); 4672 4673 switch (Constraint[0]) { 4674 default: break; 4675 case 'r': { 4676 switch (Modifier) { 4677 default: 4678 return (isInOut || isOutput || Size <= 64); 4679 case 'q': 4680 // A register of size 32 cannot fit a vector type. 4681 return false; 4682 } 4683 } 4684 } 4685 4686 return true; 4687 } 4688 const char *getClobbers() const override { 4689 // FIXME: Is this really right? 4690 return ""; 4691 } 4692 4693 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4694 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4695 } 4696 4697 int getEHDataRegisterNumber(unsigned RegNo) const override { 4698 if (RegNo == 0) return 0; 4699 if (RegNo == 1) return 1; 4700 return -1; 4701 } 4702 }; 4703 4704 bool ARMTargetInfo::setFPMath(StringRef Name) { 4705 if (Name == "neon") { 4706 FPMath = FP_Neon; 4707 return true; 4708 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4709 Name == "vfp4") { 4710 FPMath = FP_VFP; 4711 return true; 4712 } 4713 return false; 4714 } 4715 4716 const char * const ARMTargetInfo::GCCRegNames[] = { 4717 // Integer registers 4718 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4719 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4720 4721 // Float registers 4722 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4723 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4724 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4725 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4726 4727 // Double registers 4728 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4729 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4730 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4731 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4732 4733 // Quad registers 4734 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4735 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4736 }; 4737 4738 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4739 unsigned &NumNames) const { 4740 Names = GCCRegNames; 4741 NumNames = llvm::array_lengthof(GCCRegNames); 4742 } 4743 4744 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4745 { { "a1" }, "r0" }, 4746 { { "a2" }, "r1" }, 4747 { { "a3" }, "r2" }, 4748 { { "a4" }, "r3" }, 4749 { { "v1" }, "r4" }, 4750 { { "v2" }, "r5" }, 4751 { { "v3" }, "r6" }, 4752 { { "v4" }, "r7" }, 4753 { { "v5" }, "r8" }, 4754 { { "v6", "rfp" }, "r9" }, 4755 { { "sl" }, "r10" }, 4756 { { "fp" }, "r11" }, 4757 { { "ip" }, "r12" }, 4758 { { "r13" }, "sp" }, 4759 { { "r14" }, "lr" }, 4760 { { "r15" }, "pc" }, 4761 // The S, D and Q registers overlap, but aren't really aliases; we 4762 // don't want to substitute one of these for a different-sized one. 4763 }; 4764 4765 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4766 unsigned &NumAliases) const { 4767 Aliases = GCCRegAliases; 4768 NumAliases = llvm::array_lengthof(GCCRegAliases); 4769 } 4770 4771 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4772 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4773 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4774 ALL_LANGUAGES }, 4775 #include "clang/Basic/BuiltinsNEON.def" 4776 4777 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4778 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG }, 4779 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4780 ALL_LANGUAGES }, 4781 #include "clang/Basic/BuiltinsARM.def" 4782 }; 4783 4784 class ARMleTargetInfo : public ARMTargetInfo { 4785 public: 4786 ARMleTargetInfo(const llvm::Triple &Triple) 4787 : ARMTargetInfo(Triple, false) { } 4788 void getTargetDefines(const LangOptions &Opts, 4789 MacroBuilder &Builder) const override { 4790 Builder.defineMacro("__ARMEL__"); 4791 ARMTargetInfo::getTargetDefines(Opts, Builder); 4792 } 4793 }; 4794 4795 class ARMbeTargetInfo : public ARMTargetInfo { 4796 public: 4797 ARMbeTargetInfo(const llvm::Triple &Triple) 4798 : ARMTargetInfo(Triple, true) { } 4799 void getTargetDefines(const LangOptions &Opts, 4800 MacroBuilder &Builder) const override { 4801 Builder.defineMacro("__ARMEB__"); 4802 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4803 ARMTargetInfo::getTargetDefines(Opts, Builder); 4804 } 4805 }; 4806 4807 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4808 const llvm::Triple Triple; 4809 public: 4810 WindowsARMTargetInfo(const llvm::Triple &Triple) 4811 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4812 TLSSupported = false; 4813 WCharType = UnsignedShort; 4814 SizeType = UnsignedInt; 4815 UserLabelPrefix = ""; 4816 } 4817 void getVisualStudioDefines(const LangOptions &Opts, 4818 MacroBuilder &Builder) const { 4819 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4820 4821 // FIXME: this is invalid for WindowsCE 4822 Builder.defineMacro("_M_ARM_NT", "1"); 4823 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4824 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4825 4826 assert((Triple.getArch() == llvm::Triple::arm || 4827 Triple.getArch() == llvm::Triple::thumb) && 4828 "invalid architecture for Windows ARM target info"); 4829 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4830 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4831 4832 // TODO map the complete set of values 4833 // 31: VFPv3 40: VFPv4 4834 Builder.defineMacro("_M_ARM_FP", "31"); 4835 } 4836 BuiltinVaListKind getBuiltinVaListKind() const override { 4837 return TargetInfo::CharPtrBuiltinVaList; 4838 } 4839 }; 4840 4841 // Windows ARM + Itanium C++ ABI Target 4842 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4843 public: 4844 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4845 : WindowsARMTargetInfo(Triple) { 4846 TheCXXABI.set(TargetCXXABI::GenericARM); 4847 } 4848 4849 void getTargetDefines(const LangOptions &Opts, 4850 MacroBuilder &Builder) const override { 4851 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4852 4853 if (Opts.MSVCCompat) 4854 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4855 } 4856 }; 4857 4858 // Windows ARM, MS (C++) ABI 4859 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4860 public: 4861 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4862 : WindowsARMTargetInfo(Triple) { 4863 TheCXXABI.set(TargetCXXABI::Microsoft); 4864 } 4865 4866 void getTargetDefines(const LangOptions &Opts, 4867 MacroBuilder &Builder) const override { 4868 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4869 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4870 } 4871 }; 4872 4873 class DarwinARMTargetInfo : 4874 public DarwinTargetInfo<ARMleTargetInfo> { 4875 protected: 4876 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4877 MacroBuilder &Builder) const override { 4878 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4879 } 4880 4881 public: 4882 DarwinARMTargetInfo(const llvm::Triple &Triple) 4883 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4884 HasAlignMac68kSupport = true; 4885 // iOS always has 64-bit atomic instructions. 4886 // FIXME: This should be based off of the target features in 4887 // ARMleTargetInfo. 4888 MaxAtomicInlineWidth = 64; 4889 4890 // Darwin on iOS uses a variant of the ARM C++ ABI. 4891 TheCXXABI.set(TargetCXXABI::iOS); 4892 } 4893 }; 4894 4895 class AArch64TargetInfo : public TargetInfo { 4896 virtual void setDescriptionString() = 0; 4897 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4898 static const char *const GCCRegNames[]; 4899 4900 enum FPUModeEnum { 4901 FPUMode, 4902 NeonMode 4903 }; 4904 4905 unsigned FPU; 4906 unsigned CRC; 4907 unsigned Crypto; 4908 4909 static const Builtin::Info BuiltinInfo[]; 4910 4911 std::string ABI; 4912 4913 public: 4914 AArch64TargetInfo(const llvm::Triple &Triple) 4915 : TargetInfo(Triple), ABI("aapcs") { 4916 4917 if (getTriple().getOS() == llvm::Triple::NetBSD) { 4918 WCharType = SignedInt; 4919 4920 // NetBSD apparently prefers consistency across ARM targets to consistency 4921 // across 64-bit targets. 4922 Int64Type = SignedLongLong; 4923 IntMaxType = SignedLongLong; 4924 } else { 4925 WCharType = UnsignedInt; 4926 Int64Type = SignedLong; 4927 IntMaxType = SignedLong; 4928 } 4929 4930 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4931 MaxVectorAlign = 128; 4932 RegParmMax = 8; 4933 MaxAtomicInlineWidth = 128; 4934 MaxAtomicPromoteWidth = 128; 4935 4936 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 4937 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4938 4939 // {} in inline assembly are neon specifiers, not assembly variant 4940 // specifiers. 4941 NoAsmVariants = true; 4942 4943 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 4944 // contributes to the alignment of the containing aggregate in the same way 4945 // a plain (non bit-field) member of that type would, without exception for 4946 // zero-sized or anonymous bit-fields." 4947 UseBitFieldTypeAlignment = true; 4948 UseZeroLengthBitfieldAlignment = true; 4949 4950 // AArch64 targets default to using the ARM C++ ABI. 4951 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4952 } 4953 4954 StringRef getABI() const override { return ABI; } 4955 bool setABI(const std::string &Name) override { 4956 if (Name != "aapcs" && Name != "darwinpcs") 4957 return false; 4958 4959 ABI = Name; 4960 return true; 4961 } 4962 4963 bool setCPU(const std::string &Name) override { 4964 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4965 .Case("generic", true) 4966 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 4967 .Case("cyclone", true) 4968 .Default(false); 4969 return CPUKnown; 4970 } 4971 4972 void getTargetDefines(const LangOptions &Opts, 4973 MacroBuilder &Builder) const override { 4974 // Target identification. 4975 Builder.defineMacro("__aarch64__"); 4976 4977 // Target properties. 4978 Builder.defineMacro("_LP64"); 4979 Builder.defineMacro("__LP64__"); 4980 4981 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4982 Builder.defineMacro("__ARM_ACLE", "200"); 4983 Builder.defineMacro("__ARM_ARCH", "8"); 4984 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4985 4986 Builder.defineMacro("__ARM_64BIT_STATE"); 4987 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4988 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4989 4990 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4991 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4992 Builder.defineMacro("__ARM_FEATURE_FMA"); 4993 Builder.defineMacro("__ARM_FEATURE_DIV"); 4994 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE 4995 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 4996 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4997 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4998 4999 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5000 5001 // 0xe implies support for half, single and double precision operations. 5002 Builder.defineMacro("__ARM_FP", "0xe"); 5003 5004 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5005 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5006 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 5007 5008 if (Opts.FastMath || Opts.FiniteMathOnly) 5009 Builder.defineMacro("__ARM_FP_FAST"); 5010 5011 if (Opts.C99 && !Opts.Freestanding) 5012 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 5013 5014 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5015 5016 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5017 Opts.ShortEnums ? "1" : "4"); 5018 5019 if (FPU == NeonMode) { 5020 Builder.defineMacro("__ARM_NEON"); 5021 // 64-bit NEON supports half, single and double precision operations. 5022 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 5023 } 5024 5025 if (CRC) 5026 Builder.defineMacro("__ARM_FEATURE_CRC32"); 5027 5028 if (Crypto) 5029 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 5030 5031 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5032 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5033 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5034 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5035 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5036 } 5037 5038 void getTargetBuiltins(const Builtin::Info *&Records, 5039 unsigned &NumRecords) const override { 5040 Records = BuiltinInfo; 5041 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 5042 } 5043 5044 bool hasFeature(StringRef Feature) const override { 5045 return Feature == "aarch64" || 5046 Feature == "arm64" || 5047 (Feature == "neon" && FPU == NeonMode); 5048 } 5049 5050 bool handleTargetFeatures(std::vector<std::string> &Features, 5051 DiagnosticsEngine &Diags) override { 5052 FPU = FPUMode; 5053 CRC = 0; 5054 Crypto = 0; 5055 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 5056 if (Features[i] == "+neon") 5057 FPU = NeonMode; 5058 if (Features[i] == "+crc") 5059 CRC = 1; 5060 if (Features[i] == "+crypto") 5061 Crypto = 1; 5062 } 5063 5064 setDescriptionString(); 5065 5066 return true; 5067 } 5068 5069 bool isCLZForZeroUndef() const override { return false; } 5070 5071 BuiltinVaListKind getBuiltinVaListKind() const override { 5072 return TargetInfo::AArch64ABIBuiltinVaList; 5073 } 5074 5075 void getGCCRegNames(const char *const *&Names, 5076 unsigned &NumNames) const override; 5077 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5078 unsigned &NumAliases) const override; 5079 5080 bool validateAsmConstraint(const char *&Name, 5081 TargetInfo::ConstraintInfo &Info) const override { 5082 switch (*Name) { 5083 default: 5084 return false; 5085 case 'w': // Floating point and SIMD registers (V0-V31) 5086 Info.setAllowsRegister(); 5087 return true; 5088 case 'I': // Constant that can be used with an ADD instruction 5089 case 'J': // Constant that can be used with a SUB instruction 5090 case 'K': // Constant that can be used with a 32-bit logical instruction 5091 case 'L': // Constant that can be used with a 64-bit logical instruction 5092 case 'M': // Constant that can be used as a 32-bit MOV immediate 5093 case 'N': // Constant that can be used as a 64-bit MOV immediate 5094 case 'Y': // Floating point constant zero 5095 case 'Z': // Integer constant zero 5096 return true; 5097 case 'Q': // A memory reference with base register and no offset 5098 Info.setAllowsMemory(); 5099 return true; 5100 case 'S': // A symbolic address 5101 Info.setAllowsRegister(); 5102 return true; 5103 case 'U': 5104 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5105 // Utf: A memory address suitable for ldp/stp in TF mode. 5106 // Usa: An absolute symbolic address. 5107 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5108 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5109 case 'z': // Zero register, wzr or xzr 5110 Info.setAllowsRegister(); 5111 return true; 5112 case 'x': // Floating point and SIMD registers (V0-V15) 5113 Info.setAllowsRegister(); 5114 return true; 5115 } 5116 return false; 5117 } 5118 5119 bool 5120 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5121 std::string &SuggestedModifier) const override { 5122 // Strip off constraint modifiers. 5123 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5124 Constraint = Constraint.substr(1); 5125 5126 switch (Constraint[0]) { 5127 default: 5128 return true; 5129 case 'z': 5130 case 'r': { 5131 switch (Modifier) { 5132 case 'x': 5133 case 'w': 5134 // For now assume that the person knows what they're 5135 // doing with the modifier. 5136 return true; 5137 default: 5138 // By default an 'r' constraint will be in the 'x' 5139 // registers. 5140 if (Size == 64) 5141 return true; 5142 5143 SuggestedModifier = "w"; 5144 return false; 5145 } 5146 } 5147 } 5148 } 5149 5150 const char *getClobbers() const override { return ""; } 5151 5152 int getEHDataRegisterNumber(unsigned RegNo) const override { 5153 if (RegNo == 0) 5154 return 0; 5155 if (RegNo == 1) 5156 return 1; 5157 return -1; 5158 } 5159 }; 5160 5161 const char *const AArch64TargetInfo::GCCRegNames[] = { 5162 // 32-bit Integer registers 5163 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5164 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5165 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5166 5167 // 64-bit Integer registers 5168 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5169 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5170 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5171 5172 // 32-bit floating point regsisters 5173 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5174 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5175 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5176 5177 // 64-bit floating point regsisters 5178 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5179 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5180 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5181 5182 // Vector registers 5183 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5184 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5185 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5186 }; 5187 5188 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 5189 unsigned &NumNames) const { 5190 Names = GCCRegNames; 5191 NumNames = llvm::array_lengthof(GCCRegNames); 5192 } 5193 5194 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5195 { { "w31" }, "wsp" }, 5196 { { "x29" }, "fp" }, 5197 { { "x30" }, "lr" }, 5198 { { "x31" }, "sp" }, 5199 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5200 // don't want to substitute one of these for a different-sized one. 5201 }; 5202 5203 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5204 unsigned &NumAliases) const { 5205 Aliases = GCCRegAliases; 5206 NumAliases = llvm::array_lengthof(GCCRegAliases); 5207 } 5208 5209 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5210 #define BUILTIN(ID, TYPE, ATTRS) \ 5211 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5212 #include "clang/Basic/BuiltinsNEON.def" 5213 5214 #define BUILTIN(ID, TYPE, ATTRS) \ 5215 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5216 #include "clang/Basic/BuiltinsAArch64.def" 5217 }; 5218 5219 class AArch64leTargetInfo : public AArch64TargetInfo { 5220 void setDescriptionString() override { 5221 if (getTriple().isOSBinFormatMachO()) 5222 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5223 else 5224 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5225 } 5226 5227 public: 5228 AArch64leTargetInfo(const llvm::Triple &Triple) 5229 : AArch64TargetInfo(Triple) { 5230 BigEndian = false; 5231 } 5232 void getTargetDefines(const LangOptions &Opts, 5233 MacroBuilder &Builder) const override { 5234 Builder.defineMacro("__AARCH64EL__"); 5235 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5236 } 5237 }; 5238 5239 class AArch64beTargetInfo : public AArch64TargetInfo { 5240 void setDescriptionString() override { 5241 assert(!getTriple().isOSBinFormatMachO()); 5242 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5243 } 5244 5245 public: 5246 AArch64beTargetInfo(const llvm::Triple &Triple) 5247 : AArch64TargetInfo(Triple) { } 5248 void getTargetDefines(const LangOptions &Opts, 5249 MacroBuilder &Builder) const override { 5250 Builder.defineMacro("__AARCH64EB__"); 5251 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5252 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5253 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5254 } 5255 }; 5256 5257 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5258 protected: 5259 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5260 MacroBuilder &Builder) const override { 5261 Builder.defineMacro("__AARCH64_SIMD__"); 5262 Builder.defineMacro("__ARM64_ARCH_8__"); 5263 Builder.defineMacro("__ARM_NEON__"); 5264 Builder.defineMacro("__LITTLE_ENDIAN__"); 5265 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5266 Builder.defineMacro("__arm64", "1"); 5267 Builder.defineMacro("__arm64__", "1"); 5268 5269 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5270 } 5271 5272 public: 5273 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5274 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5275 Int64Type = SignedLongLong; 5276 WCharType = SignedInt; 5277 UseSignedCharForObjCBool = false; 5278 5279 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5280 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5281 5282 TheCXXABI.set(TargetCXXABI::iOS64); 5283 } 5284 5285 BuiltinVaListKind getBuiltinVaListKind() const override { 5286 return TargetInfo::CharPtrBuiltinVaList; 5287 } 5288 }; 5289 5290 // Hexagon abstract base class 5291 class HexagonTargetInfo : public TargetInfo { 5292 static const Builtin::Info BuiltinInfo[]; 5293 static const char * const GCCRegNames[]; 5294 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5295 std::string CPU; 5296 public: 5297 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5298 BigEndian = false; 5299 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5300 5301 // {} in inline assembly are packet specifiers, not assembly variant 5302 // specifiers. 5303 NoAsmVariants = true; 5304 } 5305 5306 void getTargetBuiltins(const Builtin::Info *&Records, 5307 unsigned &NumRecords) const override { 5308 Records = BuiltinInfo; 5309 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5310 } 5311 5312 bool validateAsmConstraint(const char *&Name, 5313 TargetInfo::ConstraintInfo &Info) const override { 5314 return true; 5315 } 5316 5317 void getTargetDefines(const LangOptions &Opts, 5318 MacroBuilder &Builder) const override; 5319 5320 bool hasFeature(StringRef Feature) const override { 5321 return Feature == "hexagon"; 5322 } 5323 5324 BuiltinVaListKind getBuiltinVaListKind() const override { 5325 return TargetInfo::CharPtrBuiltinVaList; 5326 } 5327 void getGCCRegNames(const char * const *&Names, 5328 unsigned &NumNames) const override; 5329 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5330 unsigned &NumAliases) const override; 5331 const char *getClobbers() const override { 5332 return ""; 5333 } 5334 5335 static const char *getHexagonCPUSuffix(StringRef Name) { 5336 return llvm::StringSwitch<const char*>(Name) 5337 .Case("hexagonv4", "4") 5338 .Case("hexagonv5", "5") 5339 .Default(nullptr); 5340 } 5341 5342 bool setCPU(const std::string &Name) override { 5343 if (!getHexagonCPUSuffix(Name)) 5344 return false; 5345 5346 CPU = Name; 5347 return true; 5348 } 5349 }; 5350 5351 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5352 MacroBuilder &Builder) const { 5353 Builder.defineMacro("qdsp6"); 5354 Builder.defineMacro("__qdsp6", "1"); 5355 Builder.defineMacro("__qdsp6__", "1"); 5356 5357 Builder.defineMacro("hexagon"); 5358 Builder.defineMacro("__hexagon", "1"); 5359 Builder.defineMacro("__hexagon__", "1"); 5360 5361 if(CPU == "hexagonv1") { 5362 Builder.defineMacro("__HEXAGON_V1__"); 5363 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5364 if(Opts.HexagonQdsp6Compat) { 5365 Builder.defineMacro("__QDSP6_V1__"); 5366 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5367 } 5368 } 5369 else if(CPU == "hexagonv2") { 5370 Builder.defineMacro("__HEXAGON_V2__"); 5371 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5372 if(Opts.HexagonQdsp6Compat) { 5373 Builder.defineMacro("__QDSP6_V2__"); 5374 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5375 } 5376 } 5377 else if(CPU == "hexagonv3") { 5378 Builder.defineMacro("__HEXAGON_V3__"); 5379 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5380 if(Opts.HexagonQdsp6Compat) { 5381 Builder.defineMacro("__QDSP6_V3__"); 5382 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5383 } 5384 } 5385 else if(CPU == "hexagonv4") { 5386 Builder.defineMacro("__HEXAGON_V4__"); 5387 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5388 if(Opts.HexagonQdsp6Compat) { 5389 Builder.defineMacro("__QDSP6_V4__"); 5390 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5391 } 5392 } 5393 else if(CPU == "hexagonv5") { 5394 Builder.defineMacro("__HEXAGON_V5__"); 5395 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5396 if(Opts.HexagonQdsp6Compat) { 5397 Builder.defineMacro("__QDSP6_V5__"); 5398 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5399 } 5400 } 5401 } 5402 5403 const char * const HexagonTargetInfo::GCCRegNames[] = { 5404 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5405 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5406 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5407 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5408 "p0", "p1", "p2", "p3", 5409 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5410 }; 5411 5412 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5413 unsigned &NumNames) const { 5414 Names = GCCRegNames; 5415 NumNames = llvm::array_lengthof(GCCRegNames); 5416 } 5417 5418 5419 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5420 { { "sp" }, "r29" }, 5421 { { "fp" }, "r30" }, 5422 { { "lr" }, "r31" }, 5423 }; 5424 5425 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5426 unsigned &NumAliases) const { 5427 Aliases = GCCRegAliases; 5428 NumAliases = llvm::array_lengthof(GCCRegAliases); 5429 } 5430 5431 5432 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5433 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5434 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5435 ALL_LANGUAGES }, 5436 #include "clang/Basic/BuiltinsHexagon.def" 5437 }; 5438 5439 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5440 class SparcTargetInfo : public TargetInfo { 5441 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5442 static const char * const GCCRegNames[]; 5443 bool SoftFloat; 5444 public: 5445 SparcTargetInfo(const llvm::Triple &Triple) 5446 : TargetInfo(Triple), SoftFloat(false) {} 5447 5448 bool handleTargetFeatures(std::vector<std::string> &Features, 5449 DiagnosticsEngine &Diags) override { 5450 // The backend doesn't actually handle soft float yet, but in case someone 5451 // is using the support for the front end continue to support it. 5452 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5453 if (Feature != Features.end()) { 5454 SoftFloat = true; 5455 Features.erase(Feature); 5456 } 5457 return true; 5458 } 5459 void getTargetDefines(const LangOptions &Opts, 5460 MacroBuilder &Builder) const override { 5461 DefineStd(Builder, "sparc", Opts); 5462 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5463 5464 if (SoftFloat) 5465 Builder.defineMacro("SOFT_FLOAT", "1"); 5466 } 5467 5468 bool hasFeature(StringRef Feature) const override { 5469 return llvm::StringSwitch<bool>(Feature) 5470 .Case("softfloat", SoftFloat) 5471 .Case("sparc", true) 5472 .Default(false); 5473 } 5474 5475 void getTargetBuiltins(const Builtin::Info *&Records, 5476 unsigned &NumRecords) const override { 5477 // FIXME: Implement! 5478 } 5479 BuiltinVaListKind getBuiltinVaListKind() const override { 5480 return TargetInfo::VoidPtrBuiltinVaList; 5481 } 5482 void getGCCRegNames(const char * const *&Names, 5483 unsigned &NumNames) const override; 5484 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5485 unsigned &NumAliases) const override; 5486 bool validateAsmConstraint(const char *&Name, 5487 TargetInfo::ConstraintInfo &info) const override { 5488 // FIXME: Implement! 5489 switch (*Name) { 5490 case 'I': // Signed 13-bit constant 5491 case 'J': // Zero 5492 case 'K': // 32-bit constant with the low 12 bits clear 5493 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5494 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5495 case 'N': // Same as 'K' but zext (required for SIMode) 5496 case 'O': // The constant 4096 5497 return true; 5498 } 5499 return false; 5500 } 5501 const char *getClobbers() const override { 5502 // FIXME: Implement! 5503 return ""; 5504 } 5505 }; 5506 5507 const char * const SparcTargetInfo::GCCRegNames[] = { 5508 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5509 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5510 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5511 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5512 }; 5513 5514 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5515 unsigned &NumNames) const { 5516 Names = GCCRegNames; 5517 NumNames = llvm::array_lengthof(GCCRegNames); 5518 } 5519 5520 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5521 { { "g0" }, "r0" }, 5522 { { "g1" }, "r1" }, 5523 { { "g2" }, "r2" }, 5524 { { "g3" }, "r3" }, 5525 { { "g4" }, "r4" }, 5526 { { "g5" }, "r5" }, 5527 { { "g6" }, "r6" }, 5528 { { "g7" }, "r7" }, 5529 { { "o0" }, "r8" }, 5530 { { "o1" }, "r9" }, 5531 { { "o2" }, "r10" }, 5532 { { "o3" }, "r11" }, 5533 { { "o4" }, "r12" }, 5534 { { "o5" }, "r13" }, 5535 { { "o6", "sp" }, "r14" }, 5536 { { "o7" }, "r15" }, 5537 { { "l0" }, "r16" }, 5538 { { "l1" }, "r17" }, 5539 { { "l2" }, "r18" }, 5540 { { "l3" }, "r19" }, 5541 { { "l4" }, "r20" }, 5542 { { "l5" }, "r21" }, 5543 { { "l6" }, "r22" }, 5544 { { "l7" }, "r23" }, 5545 { { "i0" }, "r24" }, 5546 { { "i1" }, "r25" }, 5547 { { "i2" }, "r26" }, 5548 { { "i3" }, "r27" }, 5549 { { "i4" }, "r28" }, 5550 { { "i5" }, "r29" }, 5551 { { "i6", "fp" }, "r30" }, 5552 { { "i7" }, "r31" }, 5553 }; 5554 5555 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5556 unsigned &NumAliases) const { 5557 Aliases = GCCRegAliases; 5558 NumAliases = llvm::array_lengthof(GCCRegAliases); 5559 } 5560 5561 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5562 class SparcV8TargetInfo : public SparcTargetInfo { 5563 public: 5564 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5565 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5566 // NetBSD uses long (same as llvm default); everyone else uses int. 5567 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5568 SizeType = UnsignedLong; 5569 IntPtrType = SignedLong; 5570 PtrDiffType = SignedLong; 5571 } else { 5572 SizeType = UnsignedInt; 5573 IntPtrType = SignedInt; 5574 PtrDiffType = SignedInt; 5575 } 5576 } 5577 5578 void getTargetDefines(const LangOptions &Opts, 5579 MacroBuilder &Builder) const override { 5580 SparcTargetInfo::getTargetDefines(Opts, Builder); 5581 Builder.defineMacro("__sparcv8"); 5582 } 5583 }; 5584 5585 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 5586 class SparcV8elTargetInfo : public SparcV8TargetInfo { 5587 public: 5588 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 5589 DescriptionString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5590 BigEndian = false; 5591 } 5592 }; 5593 5594 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5595 class SparcV9TargetInfo : public SparcTargetInfo { 5596 public: 5597 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5598 // FIXME: Support Sparc quad-precision long double? 5599 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5600 // This is an LP64 platform. 5601 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5602 5603 // OpenBSD uses long long for int64_t and intmax_t. 5604 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5605 IntMaxType = SignedLongLong; 5606 else 5607 IntMaxType = SignedLong; 5608 Int64Type = IntMaxType; 5609 5610 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5611 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5612 LongDoubleWidth = 128; 5613 LongDoubleAlign = 128; 5614 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5615 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5616 } 5617 5618 void getTargetDefines(const LangOptions &Opts, 5619 MacroBuilder &Builder) const override { 5620 SparcTargetInfo::getTargetDefines(Opts, Builder); 5621 Builder.defineMacro("__sparcv9"); 5622 Builder.defineMacro("__arch64__"); 5623 // Solaris doesn't need these variants, but the BSDs do. 5624 if (getTriple().getOS() != llvm::Triple::Solaris) { 5625 Builder.defineMacro("__sparc64__"); 5626 Builder.defineMacro("__sparc_v9__"); 5627 Builder.defineMacro("__sparcv9__"); 5628 } 5629 } 5630 5631 bool setCPU(const std::string &Name) override { 5632 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5633 .Case("v9", true) 5634 .Case("ultrasparc", true) 5635 .Case("ultrasparc3", true) 5636 .Case("niagara", true) 5637 .Case("niagara2", true) 5638 .Case("niagara3", true) 5639 .Case("niagara4", true) 5640 .Default(false); 5641 5642 // No need to store the CPU yet. There aren't any CPU-specific 5643 // macros to define. 5644 return CPUKnown; 5645 } 5646 }; 5647 5648 class SystemZTargetInfo : public TargetInfo { 5649 static const Builtin::Info BuiltinInfo[]; 5650 static const char *const GCCRegNames[]; 5651 std::string CPU; 5652 bool HasTransactionalExecution; 5653 bool HasVector; 5654 5655 public: 5656 SystemZTargetInfo(const llvm::Triple &Triple) 5657 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) { 5658 IntMaxType = SignedLong; 5659 Int64Type = SignedLong; 5660 TLSSupported = true; 5661 IntWidth = IntAlign = 32; 5662 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5663 PointerWidth = PointerAlign = 64; 5664 LongDoubleWidth = 128; 5665 LongDoubleAlign = 64; 5666 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5667 DefaultAlignForAttributeAligned = 64; 5668 MinGlobalAlign = 16; 5669 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5670 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5671 } 5672 void getTargetDefines(const LangOptions &Opts, 5673 MacroBuilder &Builder) const override { 5674 Builder.defineMacro("__s390__"); 5675 Builder.defineMacro("__s390x__"); 5676 Builder.defineMacro("__zarch__"); 5677 Builder.defineMacro("__LONG_DOUBLE_128__"); 5678 if (HasTransactionalExecution) 5679 Builder.defineMacro("__HTM__"); 5680 } 5681 void getTargetBuiltins(const Builtin::Info *&Records, 5682 unsigned &NumRecords) const override { 5683 Records = BuiltinInfo; 5684 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin; 5685 } 5686 5687 void getGCCRegNames(const char *const *&Names, 5688 unsigned &NumNames) const override; 5689 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5690 unsigned &NumAliases) const override { 5691 // No aliases. 5692 Aliases = nullptr; 5693 NumAliases = 0; 5694 } 5695 bool validateAsmConstraint(const char *&Name, 5696 TargetInfo::ConstraintInfo &info) const override; 5697 const char *getClobbers() const override { 5698 // FIXME: Is this really right? 5699 return ""; 5700 } 5701 BuiltinVaListKind getBuiltinVaListKind() const override { 5702 return TargetInfo::SystemZBuiltinVaList; 5703 } 5704 bool setCPU(const std::string &Name) override { 5705 CPU = Name; 5706 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5707 .Case("z10", true) 5708 .Case("z196", true) 5709 .Case("zEC12", true) 5710 .Case("z13", true) 5711 .Default(false); 5712 5713 return CPUKnown; 5714 } 5715 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5716 if (CPU == "zEC12") 5717 Features["transactional-execution"] = true; 5718 if (CPU == "z13") { 5719 Features["transactional-execution"] = true; 5720 Features["vector"] = true; 5721 } 5722 } 5723 5724 bool handleTargetFeatures(std::vector<std::string> &Features, 5725 DiagnosticsEngine &Diags) override { 5726 HasTransactionalExecution = false; 5727 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 5728 if (Features[i] == "+transactional-execution") 5729 HasTransactionalExecution = true; 5730 if (Features[i] == "+vector") 5731 HasVector = true; 5732 } 5733 // If we use the vector ABI, vector types are 64-bit aligned. 5734 if (HasVector) { 5735 MaxVectorAlign = 64; 5736 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 5737 "-v128:64-a:8:16-n32:64"; 5738 } 5739 return true; 5740 } 5741 5742 bool hasFeature(StringRef Feature) const override { 5743 return llvm::StringSwitch<bool>(Feature) 5744 .Case("systemz", true) 5745 .Case("htm", HasTransactionalExecution) 5746 .Case("vx", HasVector) 5747 .Default(false); 5748 } 5749 5750 StringRef getABI() const override { 5751 if (HasVector) 5752 return "vector"; 5753 return ""; 5754 } 5755 5756 bool useFloat128ManglingForLongDouble() const override { 5757 return true; 5758 } 5759 }; 5760 5761 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 5762 #define BUILTIN(ID, TYPE, ATTRS) \ 5763 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5764 #include "clang/Basic/BuiltinsSystemZ.def" 5765 }; 5766 5767 const char *const SystemZTargetInfo::GCCRegNames[] = { 5768 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5769 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5770 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5771 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5772 }; 5773 5774 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5775 unsigned &NumNames) const { 5776 Names = GCCRegNames; 5777 NumNames = llvm::array_lengthof(GCCRegNames); 5778 } 5779 5780 bool SystemZTargetInfo:: 5781 validateAsmConstraint(const char *&Name, 5782 TargetInfo::ConstraintInfo &Info) const { 5783 switch (*Name) { 5784 default: 5785 return false; 5786 5787 case 'a': // Address register 5788 case 'd': // Data register (equivalent to 'r') 5789 case 'f': // Floating-point register 5790 Info.setAllowsRegister(); 5791 return true; 5792 5793 case 'I': // Unsigned 8-bit constant 5794 case 'J': // Unsigned 12-bit constant 5795 case 'K': // Signed 16-bit constant 5796 case 'L': // Signed 20-bit displacement (on all targets we support) 5797 case 'M': // 0x7fffffff 5798 return true; 5799 5800 case 'Q': // Memory with base and unsigned 12-bit displacement 5801 case 'R': // Likewise, plus an index 5802 case 'S': // Memory with base and signed 20-bit displacement 5803 case 'T': // Likewise, plus an index 5804 Info.setAllowsMemory(); 5805 return true; 5806 } 5807 } 5808 5809 class MSP430TargetInfo : public TargetInfo { 5810 static const char * const GCCRegNames[]; 5811 public: 5812 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5813 BigEndian = false; 5814 TLSSupported = false; 5815 IntWidth = 16; IntAlign = 16; 5816 LongWidth = 32; LongLongWidth = 64; 5817 LongAlign = LongLongAlign = 16; 5818 PointerWidth = 16; PointerAlign = 16; 5819 SuitableAlign = 16; 5820 SizeType = UnsignedInt; 5821 IntMaxType = SignedLongLong; 5822 IntPtrType = SignedInt; 5823 PtrDiffType = SignedInt; 5824 SigAtomicType = SignedLong; 5825 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 5826 } 5827 void getTargetDefines(const LangOptions &Opts, 5828 MacroBuilder &Builder) const override { 5829 Builder.defineMacro("MSP430"); 5830 Builder.defineMacro("__MSP430__"); 5831 // FIXME: defines for different 'flavours' of MCU 5832 } 5833 void getTargetBuiltins(const Builtin::Info *&Records, 5834 unsigned &NumRecords) const override { 5835 // FIXME: Implement. 5836 Records = nullptr; 5837 NumRecords = 0; 5838 } 5839 bool hasFeature(StringRef Feature) const override { 5840 return Feature == "msp430"; 5841 } 5842 void getGCCRegNames(const char * const *&Names, 5843 unsigned &NumNames) const override; 5844 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5845 unsigned &NumAliases) const override { 5846 // No aliases. 5847 Aliases = nullptr; 5848 NumAliases = 0; 5849 } 5850 bool 5851 validateAsmConstraint(const char *&Name, 5852 TargetInfo::ConstraintInfo &info) const override { 5853 // FIXME: implement 5854 switch (*Name) { 5855 case 'K': // the constant 1 5856 case 'L': // constant -1^20 .. 1^19 5857 case 'M': // constant 1-4: 5858 return true; 5859 } 5860 // No target constraints for now. 5861 return false; 5862 } 5863 const char *getClobbers() const override { 5864 // FIXME: Is this really right? 5865 return ""; 5866 } 5867 BuiltinVaListKind getBuiltinVaListKind() const override { 5868 // FIXME: implement 5869 return TargetInfo::CharPtrBuiltinVaList; 5870 } 5871 }; 5872 5873 const char * const MSP430TargetInfo::GCCRegNames[] = { 5874 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5875 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5876 }; 5877 5878 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5879 unsigned &NumNames) const { 5880 Names = GCCRegNames; 5881 NumNames = llvm::array_lengthof(GCCRegNames); 5882 } 5883 5884 // LLVM and Clang cannot be used directly to output native binaries for 5885 // target, but is used to compile C code to llvm bitcode with correct 5886 // type and alignment information. 5887 // 5888 // TCE uses the llvm bitcode as input and uses it for generating customized 5889 // target processor and program binary. TCE co-design environment is 5890 // publicly available in http://tce.cs.tut.fi 5891 5892 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5893 3, // opencl_global 5894 4, // opencl_local 5895 5, // opencl_constant 5896 // FIXME: generic has to be added to the target 5897 0, // opencl_generic 5898 0, // cuda_device 5899 0, // cuda_constant 5900 0 // cuda_shared 5901 }; 5902 5903 class TCETargetInfo : public TargetInfo{ 5904 public: 5905 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5906 TLSSupported = false; 5907 IntWidth = 32; 5908 LongWidth = LongLongWidth = 32; 5909 PointerWidth = 32; 5910 IntAlign = 32; 5911 LongAlign = LongLongAlign = 32; 5912 PointerAlign = 32; 5913 SuitableAlign = 32; 5914 SizeType = UnsignedInt; 5915 IntMaxType = SignedLong; 5916 IntPtrType = SignedInt; 5917 PtrDiffType = SignedInt; 5918 FloatWidth = 32; 5919 FloatAlign = 32; 5920 DoubleWidth = 32; 5921 DoubleAlign = 32; 5922 LongDoubleWidth = 32; 5923 LongDoubleAlign = 32; 5924 FloatFormat = &llvm::APFloat::IEEEsingle; 5925 DoubleFormat = &llvm::APFloat::IEEEsingle; 5926 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5927 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5928 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5929 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5930 UseAddrSpaceMapMangling = true; 5931 } 5932 5933 void getTargetDefines(const LangOptions &Opts, 5934 MacroBuilder &Builder) const override { 5935 DefineStd(Builder, "tce", Opts); 5936 Builder.defineMacro("__TCE__"); 5937 Builder.defineMacro("__TCE_V1__"); 5938 } 5939 bool hasFeature(StringRef Feature) const override { 5940 return Feature == "tce"; 5941 } 5942 5943 void getTargetBuiltins(const Builtin::Info *&Records, 5944 unsigned &NumRecords) const override {} 5945 const char *getClobbers() const override { 5946 return ""; 5947 } 5948 BuiltinVaListKind getBuiltinVaListKind() const override { 5949 return TargetInfo::VoidPtrBuiltinVaList; 5950 } 5951 void getGCCRegNames(const char * const *&Names, 5952 unsigned &NumNames) const override {} 5953 bool validateAsmConstraint(const char *&Name, 5954 TargetInfo::ConstraintInfo &info) const override{ 5955 return true; 5956 } 5957 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5958 unsigned &NumAliases) const override {} 5959 }; 5960 5961 class BPFTargetInfo : public TargetInfo { 5962 public: 5963 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5964 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5965 SizeType = UnsignedLong; 5966 PtrDiffType = SignedLong; 5967 IntPtrType = SignedLong; 5968 IntMaxType = SignedLong; 5969 Int64Type = SignedLong; 5970 RegParmMax = 5; 5971 if (Triple.getArch() == llvm::Triple::bpfeb) { 5972 BigEndian = true; 5973 DescriptionString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 5974 } else { 5975 BigEndian = false; 5976 DescriptionString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 5977 } 5978 MaxAtomicPromoteWidth = 64; 5979 MaxAtomicInlineWidth = 64; 5980 TLSSupported = false; 5981 } 5982 void getTargetDefines(const LangOptions &Opts, 5983 MacroBuilder &Builder) const override { 5984 DefineStd(Builder, "bpf", Opts); 5985 Builder.defineMacro("__BPF__"); 5986 } 5987 bool hasFeature(StringRef Feature) const override { 5988 return Feature == "bpf"; 5989 } 5990 5991 void getTargetBuiltins(const Builtin::Info *&Records, 5992 unsigned &NumRecords) const override {} 5993 const char *getClobbers() const override { 5994 return ""; 5995 } 5996 BuiltinVaListKind getBuiltinVaListKind() const override { 5997 return TargetInfo::VoidPtrBuiltinVaList; 5998 } 5999 void getGCCRegNames(const char * const *&Names, 6000 unsigned &NumNames) const override { 6001 Names = nullptr; 6002 NumNames = 0; 6003 } 6004 bool validateAsmConstraint(const char *&Name, 6005 TargetInfo::ConstraintInfo &info) const override { 6006 return true; 6007 } 6008 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6009 unsigned &NumAliases) const override { 6010 Aliases = nullptr; 6011 NumAliases = 0; 6012 } 6013 }; 6014 6015 class MipsTargetInfoBase : public TargetInfo { 6016 virtual void setDescriptionString() = 0; 6017 6018 static const Builtin::Info BuiltinInfo[]; 6019 std::string CPU; 6020 bool IsMips16; 6021 bool IsMicromips; 6022 bool IsNan2008; 6023 bool IsSingleFloat; 6024 enum MipsFloatABI { 6025 HardFloat, SoftFloat 6026 } FloatABI; 6027 enum DspRevEnum { 6028 NoDSP, DSP1, DSP2 6029 } DspRev; 6030 bool HasMSA; 6031 6032 protected: 6033 bool HasFP64; 6034 std::string ABI; 6035 6036 public: 6037 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6038 const std::string &CPUStr) 6039 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6040 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6041 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6042 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6043 } 6044 6045 bool isNaN2008Default() const { 6046 return CPU == "mips32r6" || CPU == "mips64r6"; 6047 } 6048 6049 bool isFP64Default() const { 6050 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6051 } 6052 6053 bool isNan2008() const override { 6054 return IsNan2008; 6055 } 6056 6057 StringRef getABI() const override { return ABI; } 6058 bool setCPU(const std::string &Name) override { 6059 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6060 getTriple().getArch() == llvm::Triple::mipsel; 6061 CPU = Name; 6062 return llvm::StringSwitch<bool>(Name) 6063 .Case("mips1", IsMips32) 6064 .Case("mips2", IsMips32) 6065 .Case("mips3", true) 6066 .Case("mips4", true) 6067 .Case("mips5", true) 6068 .Case("mips32", IsMips32) 6069 .Case("mips32r2", IsMips32) 6070 .Case("mips32r3", IsMips32) 6071 .Case("mips32r5", IsMips32) 6072 .Case("mips32r6", IsMips32) 6073 .Case("mips64", true) 6074 .Case("mips64r2", true) 6075 .Case("mips64r3", true) 6076 .Case("mips64r5", true) 6077 .Case("mips64r6", true) 6078 .Case("octeon", true) 6079 .Default(false); 6080 } 6081 const std::string& getCPU() const { return CPU; } 6082 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6083 if (CPU == "octeon") 6084 Features["mips64r2"] = Features["cnmips"] = true; 6085 else 6086 Features[CPU] = true; 6087 } 6088 6089 void getTargetDefines(const LangOptions &Opts, 6090 MacroBuilder &Builder) const override { 6091 Builder.defineMacro("__mips__"); 6092 Builder.defineMacro("_mips"); 6093 if (Opts.GNUMode) 6094 Builder.defineMacro("mips"); 6095 6096 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6097 6098 switch (FloatABI) { 6099 case HardFloat: 6100 Builder.defineMacro("__mips_hard_float", Twine(1)); 6101 break; 6102 case SoftFloat: 6103 Builder.defineMacro("__mips_soft_float", Twine(1)); 6104 break; 6105 } 6106 6107 if (IsSingleFloat) 6108 Builder.defineMacro("__mips_single_float", Twine(1)); 6109 6110 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6111 Builder.defineMacro("_MIPS_FPSET", 6112 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6113 6114 if (IsMips16) 6115 Builder.defineMacro("__mips16", Twine(1)); 6116 6117 if (IsMicromips) 6118 Builder.defineMacro("__mips_micromips", Twine(1)); 6119 6120 if (IsNan2008) 6121 Builder.defineMacro("__mips_nan2008", Twine(1)); 6122 6123 switch (DspRev) { 6124 default: 6125 break; 6126 case DSP1: 6127 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6128 Builder.defineMacro("__mips_dsp", Twine(1)); 6129 break; 6130 case DSP2: 6131 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6132 Builder.defineMacro("__mips_dspr2", Twine(1)); 6133 Builder.defineMacro("__mips_dsp", Twine(1)); 6134 break; 6135 } 6136 6137 if (HasMSA) 6138 Builder.defineMacro("__mips_msa", Twine(1)); 6139 6140 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6141 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6142 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6143 6144 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6145 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6146 } 6147 6148 void getTargetBuiltins(const Builtin::Info *&Records, 6149 unsigned &NumRecords) const override { 6150 Records = BuiltinInfo; 6151 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 6152 } 6153 bool hasFeature(StringRef Feature) const override { 6154 return llvm::StringSwitch<bool>(Feature) 6155 .Case("mips", true) 6156 .Case("fp64", HasFP64) 6157 .Default(false); 6158 } 6159 BuiltinVaListKind getBuiltinVaListKind() const override { 6160 return TargetInfo::VoidPtrBuiltinVaList; 6161 } 6162 void getGCCRegNames(const char * const *&Names, 6163 unsigned &NumNames) const override { 6164 static const char *const GCCRegNames[] = { 6165 // CPU register names 6166 // Must match second column of GCCRegAliases 6167 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6168 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6169 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6170 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6171 // Floating point register names 6172 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6173 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6174 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6175 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6176 // Hi/lo and condition register names 6177 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6178 "$fcc5","$fcc6","$fcc7", 6179 // MSA register names 6180 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6181 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6182 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6183 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6184 // MSA control register names 6185 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6186 "$msarequest", "$msamap", "$msaunmap" 6187 }; 6188 Names = GCCRegNames; 6189 NumNames = llvm::array_lengthof(GCCRegNames); 6190 } 6191 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6192 unsigned &NumAliases) const override = 0; 6193 bool validateAsmConstraint(const char *&Name, 6194 TargetInfo::ConstraintInfo &Info) const override { 6195 switch (*Name) { 6196 default: 6197 return false; 6198 case 'r': // CPU registers. 6199 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6200 case 'y': // Equivalent to "r", backward compatibility only. 6201 case 'f': // floating-point registers. 6202 case 'c': // $25 for indirect jumps 6203 case 'l': // lo register 6204 case 'x': // hilo register pair 6205 Info.setAllowsRegister(); 6206 return true; 6207 case 'I': // Signed 16-bit constant 6208 case 'J': // Integer 0 6209 case 'K': // Unsigned 16-bit constant 6210 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6211 case 'M': // Constants not loadable via lui, addiu, or ori 6212 case 'N': // Constant -1 to -65535 6213 case 'O': // A signed 15-bit constant 6214 case 'P': // A constant between 1 go 65535 6215 return true; 6216 case 'R': // An address that can be used in a non-macro load or store 6217 Info.setAllowsMemory(); 6218 return true; 6219 case 'Z': 6220 if (Name[1] == 'C') { // An address usable by ll, and sc. 6221 Info.setAllowsMemory(); 6222 Name++; // Skip over 'Z'. 6223 return true; 6224 } 6225 return false; 6226 } 6227 } 6228 6229 std::string convertConstraint(const char *&Constraint) const override { 6230 std::string R; 6231 switch (*Constraint) { 6232 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6233 if (Constraint[1] == 'C') { 6234 R = std::string("^") + std::string(Constraint, 2); 6235 Constraint++; 6236 return R; 6237 } 6238 break; 6239 } 6240 return TargetInfo::convertConstraint(Constraint); 6241 } 6242 6243 const char *getClobbers() const override { 6244 // In GCC, $1 is not widely used in generated code (it's used only in a few 6245 // specific situations), so there is no real need for users to add it to 6246 // the clobbers list if they want to use it in their inline assembly code. 6247 // 6248 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6249 // code generation, so using it in inline assembly without adding it to the 6250 // clobbers list can cause conflicts between the inline assembly code and 6251 // the surrounding generated code. 6252 // 6253 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6254 // operands, which will conflict with the ".set at" assembler option (which 6255 // we use only for inline assembly, in order to maintain compatibility with 6256 // GCC) and will also conflict with the user's usage of $1. 6257 // 6258 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6259 // register for generated code is to automatically clobber $1 for all inline 6260 // assembly code. 6261 // 6262 // FIXME: We should automatically clobber $1 only for inline assembly code 6263 // which actually uses it. This would allow LLVM to use $1 for inline 6264 // assembly operands if the user's assembly code doesn't use it. 6265 return "~{$1}"; 6266 } 6267 6268 bool handleTargetFeatures(std::vector<std::string> &Features, 6269 DiagnosticsEngine &Diags) override { 6270 IsMips16 = false; 6271 IsMicromips = false; 6272 IsNan2008 = isNaN2008Default(); 6273 IsSingleFloat = false; 6274 FloatABI = HardFloat; 6275 DspRev = NoDSP; 6276 HasFP64 = isFP64Default(); 6277 6278 for (std::vector<std::string>::iterator it = Features.begin(), 6279 ie = Features.end(); it != ie; ++it) { 6280 if (*it == "+single-float") 6281 IsSingleFloat = true; 6282 else if (*it == "+soft-float") 6283 FloatABI = SoftFloat; 6284 else if (*it == "+mips16") 6285 IsMips16 = true; 6286 else if (*it == "+micromips") 6287 IsMicromips = true; 6288 else if (*it == "+dsp") 6289 DspRev = std::max(DspRev, DSP1); 6290 else if (*it == "+dspr2") 6291 DspRev = std::max(DspRev, DSP2); 6292 else if (*it == "+msa") 6293 HasMSA = true; 6294 else if (*it == "+fp64") 6295 HasFP64 = true; 6296 else if (*it == "-fp64") 6297 HasFP64 = false; 6298 else if (*it == "+nan2008") 6299 IsNan2008 = true; 6300 else if (*it == "-nan2008") 6301 IsNan2008 = false; 6302 } 6303 6304 setDescriptionString(); 6305 6306 return true; 6307 } 6308 6309 int getEHDataRegisterNumber(unsigned RegNo) const override { 6310 if (RegNo == 0) return 4; 6311 if (RegNo == 1) return 5; 6312 return -1; 6313 } 6314 6315 bool isCLZForZeroUndef() const override { return false; } 6316 }; 6317 6318 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6319 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6320 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6321 ALL_LANGUAGES }, 6322 #include "clang/Basic/BuiltinsMips.def" 6323 }; 6324 6325 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6326 public: 6327 Mips32TargetInfoBase(const llvm::Triple &Triple) 6328 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6329 SizeType = UnsignedInt; 6330 PtrDiffType = SignedInt; 6331 Int64Type = SignedLongLong; 6332 IntMaxType = Int64Type; 6333 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6334 } 6335 bool setABI(const std::string &Name) override { 6336 if (Name == "o32" || Name == "eabi") { 6337 ABI = Name; 6338 return true; 6339 } 6340 return false; 6341 } 6342 void getTargetDefines(const LangOptions &Opts, 6343 MacroBuilder &Builder) const override { 6344 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6345 6346 Builder.defineMacro("__mips", "32"); 6347 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6348 6349 const std::string& CPUStr = getCPU(); 6350 if (CPUStr == "mips32") 6351 Builder.defineMacro("__mips_isa_rev", "1"); 6352 else if (CPUStr == "mips32r2") 6353 Builder.defineMacro("__mips_isa_rev", "2"); 6354 else if (CPUStr == "mips32r3") 6355 Builder.defineMacro("__mips_isa_rev", "3"); 6356 else if (CPUStr == "mips32r5") 6357 Builder.defineMacro("__mips_isa_rev", "5"); 6358 else if (CPUStr == "mips32r6") 6359 Builder.defineMacro("__mips_isa_rev", "6"); 6360 6361 if (ABI == "o32") { 6362 Builder.defineMacro("__mips_o32"); 6363 Builder.defineMacro("_ABIO32", "1"); 6364 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6365 } 6366 else if (ABI == "eabi") 6367 Builder.defineMacro("__mips_eabi"); 6368 else 6369 llvm_unreachable("Invalid ABI for Mips32."); 6370 } 6371 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6372 unsigned &NumAliases) const override { 6373 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6374 { { "at" }, "$1" }, 6375 { { "v0" }, "$2" }, 6376 { { "v1" }, "$3" }, 6377 { { "a0" }, "$4" }, 6378 { { "a1" }, "$5" }, 6379 { { "a2" }, "$6" }, 6380 { { "a3" }, "$7" }, 6381 { { "t0" }, "$8" }, 6382 { { "t1" }, "$9" }, 6383 { { "t2" }, "$10" }, 6384 { { "t3" }, "$11" }, 6385 { { "t4" }, "$12" }, 6386 { { "t5" }, "$13" }, 6387 { { "t6" }, "$14" }, 6388 { { "t7" }, "$15" }, 6389 { { "s0" }, "$16" }, 6390 { { "s1" }, "$17" }, 6391 { { "s2" }, "$18" }, 6392 { { "s3" }, "$19" }, 6393 { { "s4" }, "$20" }, 6394 { { "s5" }, "$21" }, 6395 { { "s6" }, "$22" }, 6396 { { "s7" }, "$23" }, 6397 { { "t8" }, "$24" }, 6398 { { "t9" }, "$25" }, 6399 { { "k0" }, "$26" }, 6400 { { "k1" }, "$27" }, 6401 { { "gp" }, "$28" }, 6402 { { "sp","$sp" }, "$29" }, 6403 { { "fp","$fp" }, "$30" }, 6404 { { "ra" }, "$31" } 6405 }; 6406 Aliases = GCCRegAliases; 6407 NumAliases = llvm::array_lengthof(GCCRegAliases); 6408 } 6409 }; 6410 6411 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6412 void setDescriptionString() override { 6413 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6414 } 6415 6416 public: 6417 Mips32EBTargetInfo(const llvm::Triple &Triple) 6418 : Mips32TargetInfoBase(Triple) { 6419 } 6420 void getTargetDefines(const LangOptions &Opts, 6421 MacroBuilder &Builder) const override { 6422 DefineStd(Builder, "MIPSEB", Opts); 6423 Builder.defineMacro("_MIPSEB"); 6424 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6425 } 6426 }; 6427 6428 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6429 void setDescriptionString() override { 6430 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6431 } 6432 6433 public: 6434 Mips32ELTargetInfo(const llvm::Triple &Triple) 6435 : Mips32TargetInfoBase(Triple) { 6436 BigEndian = false; 6437 } 6438 void getTargetDefines(const LangOptions &Opts, 6439 MacroBuilder &Builder) const override { 6440 DefineStd(Builder, "MIPSEL", Opts); 6441 Builder.defineMacro("_MIPSEL"); 6442 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6443 } 6444 }; 6445 6446 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6447 public: 6448 Mips64TargetInfoBase(const llvm::Triple &Triple) 6449 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6450 LongDoubleWidth = LongDoubleAlign = 128; 6451 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6452 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6453 LongDoubleWidth = LongDoubleAlign = 64; 6454 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6455 } 6456 setN64ABITypes(); 6457 SuitableAlign = 128; 6458 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6459 } 6460 6461 void setN64ABITypes() { 6462 LongWidth = LongAlign = 64; 6463 PointerWidth = PointerAlign = 64; 6464 SizeType = UnsignedLong; 6465 PtrDiffType = SignedLong; 6466 Int64Type = SignedLong; 6467 IntMaxType = Int64Type; 6468 } 6469 6470 void setN32ABITypes() { 6471 LongWidth = LongAlign = 32; 6472 PointerWidth = PointerAlign = 32; 6473 SizeType = UnsignedInt; 6474 PtrDiffType = SignedInt; 6475 Int64Type = SignedLongLong; 6476 IntMaxType = Int64Type; 6477 } 6478 6479 bool setABI(const std::string &Name) override { 6480 if (Name == "n32") { 6481 setN32ABITypes(); 6482 ABI = Name; 6483 return true; 6484 } 6485 if (Name == "n64") { 6486 setN64ABITypes(); 6487 ABI = Name; 6488 return true; 6489 } 6490 return false; 6491 } 6492 6493 void getTargetDefines(const LangOptions &Opts, 6494 MacroBuilder &Builder) const override { 6495 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6496 6497 Builder.defineMacro("__mips", "64"); 6498 Builder.defineMacro("__mips64"); 6499 Builder.defineMacro("__mips64__"); 6500 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6501 6502 const std::string& CPUStr = getCPU(); 6503 if (CPUStr == "mips64") 6504 Builder.defineMacro("__mips_isa_rev", "1"); 6505 else if (CPUStr == "mips64r2") 6506 Builder.defineMacro("__mips_isa_rev", "2"); 6507 else if (CPUStr == "mips64r3") 6508 Builder.defineMacro("__mips_isa_rev", "3"); 6509 else if (CPUStr == "mips64r5") 6510 Builder.defineMacro("__mips_isa_rev", "5"); 6511 else if (CPUStr == "mips64r6") 6512 Builder.defineMacro("__mips_isa_rev", "6"); 6513 6514 if (ABI == "n32") { 6515 Builder.defineMacro("__mips_n32"); 6516 Builder.defineMacro("_ABIN32", "2"); 6517 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6518 } 6519 else if (ABI == "n64") { 6520 Builder.defineMacro("__mips_n64"); 6521 Builder.defineMacro("_ABI64", "3"); 6522 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6523 } 6524 else 6525 llvm_unreachable("Invalid ABI for Mips64."); 6526 } 6527 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6528 unsigned &NumAliases) const override { 6529 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6530 { { "at" }, "$1" }, 6531 { { "v0" }, "$2" }, 6532 { { "v1" }, "$3" }, 6533 { { "a0" }, "$4" }, 6534 { { "a1" }, "$5" }, 6535 { { "a2" }, "$6" }, 6536 { { "a3" }, "$7" }, 6537 { { "a4" }, "$8" }, 6538 { { "a5" }, "$9" }, 6539 { { "a6" }, "$10" }, 6540 { { "a7" }, "$11" }, 6541 { { "t0" }, "$12" }, 6542 { { "t1" }, "$13" }, 6543 { { "t2" }, "$14" }, 6544 { { "t3" }, "$15" }, 6545 { { "s0" }, "$16" }, 6546 { { "s1" }, "$17" }, 6547 { { "s2" }, "$18" }, 6548 { { "s3" }, "$19" }, 6549 { { "s4" }, "$20" }, 6550 { { "s5" }, "$21" }, 6551 { { "s6" }, "$22" }, 6552 { { "s7" }, "$23" }, 6553 { { "t8" }, "$24" }, 6554 { { "t9" }, "$25" }, 6555 { { "k0" }, "$26" }, 6556 { { "k1" }, "$27" }, 6557 { { "gp" }, "$28" }, 6558 { { "sp","$sp" }, "$29" }, 6559 { { "fp","$fp" }, "$30" }, 6560 { { "ra" }, "$31" } 6561 }; 6562 Aliases = GCCRegAliases; 6563 NumAliases = llvm::array_lengthof(GCCRegAliases); 6564 } 6565 6566 bool hasInt128Type() const override { return true; } 6567 }; 6568 6569 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6570 void setDescriptionString() override { 6571 if (ABI == "n32") 6572 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6573 else 6574 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6575 6576 } 6577 6578 public: 6579 Mips64EBTargetInfo(const llvm::Triple &Triple) 6580 : Mips64TargetInfoBase(Triple) {} 6581 void getTargetDefines(const LangOptions &Opts, 6582 MacroBuilder &Builder) const override { 6583 DefineStd(Builder, "MIPSEB", Opts); 6584 Builder.defineMacro("_MIPSEB"); 6585 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6586 } 6587 }; 6588 6589 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6590 void setDescriptionString() override { 6591 if (ABI == "n32") 6592 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6593 else 6594 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6595 } 6596 public: 6597 Mips64ELTargetInfo(const llvm::Triple &Triple) 6598 : Mips64TargetInfoBase(Triple) { 6599 // Default ABI is n64. 6600 BigEndian = false; 6601 } 6602 void getTargetDefines(const LangOptions &Opts, 6603 MacroBuilder &Builder) const override { 6604 DefineStd(Builder, "MIPSEL", Opts); 6605 Builder.defineMacro("_MIPSEL"); 6606 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6607 } 6608 }; 6609 6610 class PNaClTargetInfo : public TargetInfo { 6611 public: 6612 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6613 BigEndian = false; 6614 this->UserLabelPrefix = ""; 6615 this->LongAlign = 32; 6616 this->LongWidth = 32; 6617 this->PointerAlign = 32; 6618 this->PointerWidth = 32; 6619 this->IntMaxType = TargetInfo::SignedLongLong; 6620 this->Int64Type = TargetInfo::SignedLongLong; 6621 this->DoubleAlign = 64; 6622 this->LongDoubleWidth = 64; 6623 this->LongDoubleAlign = 64; 6624 this->SizeType = TargetInfo::UnsignedInt; 6625 this->PtrDiffType = TargetInfo::SignedInt; 6626 this->IntPtrType = TargetInfo::SignedInt; 6627 this->RegParmMax = 0; // Disallow regparm 6628 } 6629 6630 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6631 } 6632 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6633 Builder.defineMacro("__le32__"); 6634 Builder.defineMacro("__pnacl__"); 6635 } 6636 void getTargetDefines(const LangOptions &Opts, 6637 MacroBuilder &Builder) const override { 6638 getArchDefines(Opts, Builder); 6639 } 6640 bool hasFeature(StringRef Feature) const override { 6641 return Feature == "pnacl"; 6642 } 6643 void getTargetBuiltins(const Builtin::Info *&Records, 6644 unsigned &NumRecords) const override { 6645 } 6646 BuiltinVaListKind getBuiltinVaListKind() const override { 6647 return TargetInfo::PNaClABIBuiltinVaList; 6648 } 6649 void getGCCRegNames(const char * const *&Names, 6650 unsigned &NumNames) const override; 6651 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6652 unsigned &NumAliases) const override; 6653 bool validateAsmConstraint(const char *&Name, 6654 TargetInfo::ConstraintInfo &Info) const override { 6655 return false; 6656 } 6657 6658 const char *getClobbers() const override { 6659 return ""; 6660 } 6661 }; 6662 6663 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6664 unsigned &NumNames) const { 6665 Names = nullptr; 6666 NumNames = 0; 6667 } 6668 6669 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6670 unsigned &NumAliases) const { 6671 Aliases = nullptr; 6672 NumAliases = 0; 6673 } 6674 6675 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 6676 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 6677 public: 6678 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 6679 Mips32ELTargetInfo(Triple) { 6680 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 0; 6681 } 6682 6683 BuiltinVaListKind getBuiltinVaListKind() const override { 6684 return TargetInfo::PNaClABIBuiltinVaList; 6685 } 6686 }; 6687 6688 class Le64TargetInfo : public TargetInfo { 6689 static const Builtin::Info BuiltinInfo[]; 6690 6691 public: 6692 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6693 BigEndian = false; 6694 NoAsmVariants = true; 6695 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6696 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6697 DescriptionString = 6698 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6699 } 6700 6701 void getTargetDefines(const LangOptions &Opts, 6702 MacroBuilder &Builder) const override { 6703 DefineStd(Builder, "unix", Opts); 6704 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6705 Builder.defineMacro("__ELF__"); 6706 } 6707 void getTargetBuiltins(const Builtin::Info *&Records, 6708 unsigned &NumRecords) const override { 6709 Records = BuiltinInfo; 6710 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6711 } 6712 BuiltinVaListKind getBuiltinVaListKind() const override { 6713 return TargetInfo::PNaClABIBuiltinVaList; 6714 } 6715 const char *getClobbers() const override { return ""; } 6716 void getGCCRegNames(const char *const *&Names, 6717 unsigned &NumNames) const override { 6718 Names = nullptr; 6719 NumNames = 0; 6720 } 6721 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6722 unsigned &NumAliases) const override { 6723 Aliases = nullptr; 6724 NumAliases = 0; 6725 } 6726 bool validateAsmConstraint(const char *&Name, 6727 TargetInfo::ConstraintInfo &Info) const override { 6728 return false; 6729 } 6730 6731 bool hasProtectedVisibility() const override { return false; } 6732 }; 6733 } // end anonymous namespace. 6734 6735 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 6736 #define BUILTIN(ID, TYPE, ATTRS) \ 6737 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6738 #include "clang/Basic/BuiltinsLe64.def" 6739 }; 6740 6741 namespace { 6742 static const unsigned SPIRAddrSpaceMap[] = { 6743 1, // opencl_global 6744 3, // opencl_local 6745 2, // opencl_constant 6746 4, // opencl_generic 6747 0, // cuda_device 6748 0, // cuda_constant 6749 0 // cuda_shared 6750 }; 6751 class SPIRTargetInfo : public TargetInfo { 6752 public: 6753 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6754 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 6755 "SPIR target must use unknown OS"); 6756 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 6757 "SPIR target must use unknown environment type"); 6758 BigEndian = false; 6759 TLSSupported = false; 6760 LongWidth = LongAlign = 64; 6761 AddrSpaceMap = &SPIRAddrSpaceMap; 6762 UseAddrSpaceMapMangling = true; 6763 // Define available target features 6764 // These must be defined in sorted order! 6765 NoAsmVariants = true; 6766 } 6767 void getTargetDefines(const LangOptions &Opts, 6768 MacroBuilder &Builder) const override { 6769 DefineStd(Builder, "SPIR", Opts); 6770 } 6771 bool hasFeature(StringRef Feature) const override { 6772 return Feature == "spir"; 6773 } 6774 6775 void getTargetBuiltins(const Builtin::Info *&Records, 6776 unsigned &NumRecords) const override {} 6777 const char *getClobbers() const override { 6778 return ""; 6779 } 6780 void getGCCRegNames(const char * const *&Names, 6781 unsigned &NumNames) const override {} 6782 bool 6783 validateAsmConstraint(const char *&Name, 6784 TargetInfo::ConstraintInfo &info) const override { 6785 return true; 6786 } 6787 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6788 unsigned &NumAliases) const override {} 6789 BuiltinVaListKind getBuiltinVaListKind() const override { 6790 return TargetInfo::VoidPtrBuiltinVaList; 6791 } 6792 6793 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6794 return (CC == CC_SpirFunction || 6795 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning; 6796 } 6797 6798 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 6799 return CC_SpirFunction; 6800 } 6801 }; 6802 6803 6804 class SPIR32TargetInfo : public SPIRTargetInfo { 6805 public: 6806 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6807 PointerWidth = PointerAlign = 32; 6808 SizeType = TargetInfo::UnsignedInt; 6809 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6810 DescriptionString 6811 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6812 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6813 } 6814 void getTargetDefines(const LangOptions &Opts, 6815 MacroBuilder &Builder) const override { 6816 DefineStd(Builder, "SPIR32", Opts); 6817 } 6818 }; 6819 6820 class SPIR64TargetInfo : public SPIRTargetInfo { 6821 public: 6822 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6823 PointerWidth = PointerAlign = 64; 6824 SizeType = TargetInfo::UnsignedLong; 6825 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6826 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6827 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6828 } 6829 void getTargetDefines(const LangOptions &Opts, 6830 MacroBuilder &Builder) const override { 6831 DefineStd(Builder, "SPIR64", Opts); 6832 } 6833 }; 6834 6835 class XCoreTargetInfo : public TargetInfo { 6836 static const Builtin::Info BuiltinInfo[]; 6837 public: 6838 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6839 BigEndian = false; 6840 NoAsmVariants = true; 6841 LongLongAlign = 32; 6842 SuitableAlign = 32; 6843 DoubleAlign = LongDoubleAlign = 32; 6844 SizeType = UnsignedInt; 6845 PtrDiffType = SignedInt; 6846 IntPtrType = SignedInt; 6847 WCharType = UnsignedChar; 6848 WIntType = UnsignedInt; 6849 UseZeroLengthBitfieldAlignment = true; 6850 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6851 "-f64:32-a:0:32-n32"; 6852 } 6853 void getTargetDefines(const LangOptions &Opts, 6854 MacroBuilder &Builder) const override { 6855 Builder.defineMacro("__XS1B__"); 6856 } 6857 void getTargetBuiltins(const Builtin::Info *&Records, 6858 unsigned &NumRecords) const override { 6859 Records = BuiltinInfo; 6860 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6861 } 6862 BuiltinVaListKind getBuiltinVaListKind() const override { 6863 return TargetInfo::VoidPtrBuiltinVaList; 6864 } 6865 const char *getClobbers() const override { 6866 return ""; 6867 } 6868 void getGCCRegNames(const char * const *&Names, 6869 unsigned &NumNames) const override { 6870 static const char * const GCCRegNames[] = { 6871 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6872 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6873 }; 6874 Names = GCCRegNames; 6875 NumNames = llvm::array_lengthof(GCCRegNames); 6876 } 6877 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6878 unsigned &NumAliases) const override { 6879 Aliases = nullptr; 6880 NumAliases = 0; 6881 } 6882 bool validateAsmConstraint(const char *&Name, 6883 TargetInfo::ConstraintInfo &Info) const override { 6884 return false; 6885 } 6886 int getEHDataRegisterNumber(unsigned RegNo) const override { 6887 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6888 return (RegNo < 2)? RegNo : -1; 6889 } 6890 }; 6891 6892 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6893 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6894 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6895 ALL_LANGUAGES }, 6896 #include "clang/Basic/BuiltinsXCore.def" 6897 }; 6898 } // end anonymous namespace. 6899 6900 namespace { 6901 // x86_32 Android target 6902 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 6903 public: 6904 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 6905 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 6906 SuitableAlign = 32; 6907 LongDoubleWidth = 64; 6908 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6909 } 6910 }; 6911 } // end anonymous namespace 6912 6913 namespace { 6914 // x86_64 Android target 6915 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 6916 public: 6917 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 6918 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 6919 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6920 } 6921 }; 6922 } // end anonymous namespace 6923 6924 6925 //===----------------------------------------------------------------------===// 6926 // Driver code 6927 //===----------------------------------------------------------------------===// 6928 6929 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 6930 llvm::Triple::OSType os = Triple.getOS(); 6931 6932 switch (Triple.getArch()) { 6933 default: 6934 return nullptr; 6935 6936 case llvm::Triple::xcore: 6937 return new XCoreTargetInfo(Triple); 6938 6939 case llvm::Triple::hexagon: 6940 return new HexagonTargetInfo(Triple); 6941 6942 case llvm::Triple::aarch64: 6943 if (Triple.isOSDarwin()) 6944 return new DarwinAArch64TargetInfo(Triple); 6945 6946 switch (os) { 6947 case llvm::Triple::FreeBSD: 6948 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 6949 case llvm::Triple::Linux: 6950 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6951 case llvm::Triple::NetBSD: 6952 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6953 default: 6954 return new AArch64leTargetInfo(Triple); 6955 } 6956 6957 case llvm::Triple::aarch64_be: 6958 switch (os) { 6959 case llvm::Triple::FreeBSD: 6960 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 6961 case llvm::Triple::Linux: 6962 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6963 case llvm::Triple::NetBSD: 6964 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6965 default: 6966 return new AArch64beTargetInfo(Triple); 6967 } 6968 6969 case llvm::Triple::arm: 6970 case llvm::Triple::thumb: 6971 if (Triple.isOSBinFormatMachO()) 6972 return new DarwinARMTargetInfo(Triple); 6973 6974 switch (os) { 6975 case llvm::Triple::Linux: 6976 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6977 case llvm::Triple::FreeBSD: 6978 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6979 case llvm::Triple::NetBSD: 6980 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6981 case llvm::Triple::OpenBSD: 6982 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6983 case llvm::Triple::Bitrig: 6984 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6985 case llvm::Triple::RTEMS: 6986 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6987 case llvm::Triple::NaCl: 6988 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6989 case llvm::Triple::Win32: 6990 switch (Triple.getEnvironment()) { 6991 default: 6992 return new ARMleTargetInfo(Triple); 6993 case llvm::Triple::Itanium: 6994 return new ItaniumWindowsARMleTargetInfo(Triple); 6995 case llvm::Triple::MSVC: 6996 return new MicrosoftARMleTargetInfo(Triple); 6997 } 6998 default: 6999 return new ARMleTargetInfo(Triple); 7000 } 7001 7002 case llvm::Triple::armeb: 7003 case llvm::Triple::thumbeb: 7004 if (Triple.isOSDarwin()) 7005 return new DarwinARMTargetInfo(Triple); 7006 7007 switch (os) { 7008 case llvm::Triple::Linux: 7009 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7010 case llvm::Triple::FreeBSD: 7011 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7012 case llvm::Triple::NetBSD: 7013 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7014 case llvm::Triple::OpenBSD: 7015 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7016 case llvm::Triple::Bitrig: 7017 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7018 case llvm::Triple::RTEMS: 7019 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7020 case llvm::Triple::NaCl: 7021 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7022 default: 7023 return new ARMbeTargetInfo(Triple); 7024 } 7025 7026 case llvm::Triple::bpfeb: 7027 case llvm::Triple::bpfel: 7028 return new BPFTargetInfo(Triple); 7029 7030 case llvm::Triple::msp430: 7031 return new MSP430TargetInfo(Triple); 7032 7033 case llvm::Triple::mips: 7034 switch (os) { 7035 case llvm::Triple::Linux: 7036 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7037 case llvm::Triple::RTEMS: 7038 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7039 case llvm::Triple::FreeBSD: 7040 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7041 case llvm::Triple::NetBSD: 7042 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7043 default: 7044 return new Mips32EBTargetInfo(Triple); 7045 } 7046 7047 case llvm::Triple::mipsel: 7048 switch (os) { 7049 case llvm::Triple::Linux: 7050 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7051 case llvm::Triple::RTEMS: 7052 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7053 case llvm::Triple::FreeBSD: 7054 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7055 case llvm::Triple::NetBSD: 7056 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7057 case llvm::Triple::NaCl: 7058 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7059 default: 7060 return new Mips32ELTargetInfo(Triple); 7061 } 7062 7063 case llvm::Triple::mips64: 7064 switch (os) { 7065 case llvm::Triple::Linux: 7066 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7067 case llvm::Triple::RTEMS: 7068 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7069 case llvm::Triple::FreeBSD: 7070 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7071 case llvm::Triple::NetBSD: 7072 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7073 case llvm::Triple::OpenBSD: 7074 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7075 default: 7076 return new Mips64EBTargetInfo(Triple); 7077 } 7078 7079 case llvm::Triple::mips64el: 7080 switch (os) { 7081 case llvm::Triple::Linux: 7082 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7083 case llvm::Triple::RTEMS: 7084 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7085 case llvm::Triple::FreeBSD: 7086 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7087 case llvm::Triple::NetBSD: 7088 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7089 case llvm::Triple::OpenBSD: 7090 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7091 default: 7092 return new Mips64ELTargetInfo(Triple); 7093 } 7094 7095 case llvm::Triple::le32: 7096 switch (os) { 7097 case llvm::Triple::NaCl: 7098 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7099 default: 7100 return nullptr; 7101 } 7102 7103 case llvm::Triple::le64: 7104 return new Le64TargetInfo(Triple); 7105 7106 case llvm::Triple::ppc: 7107 if (Triple.isOSDarwin()) 7108 return new DarwinPPC32TargetInfo(Triple); 7109 switch (os) { 7110 case llvm::Triple::Linux: 7111 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7112 case llvm::Triple::FreeBSD: 7113 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7114 case llvm::Triple::NetBSD: 7115 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7116 case llvm::Triple::OpenBSD: 7117 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7118 case llvm::Triple::RTEMS: 7119 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7120 default: 7121 return new PPC32TargetInfo(Triple); 7122 } 7123 7124 case llvm::Triple::ppc64: 7125 if (Triple.isOSDarwin()) 7126 return new DarwinPPC64TargetInfo(Triple); 7127 switch (os) { 7128 case llvm::Triple::Linux: 7129 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7130 case llvm::Triple::Lv2: 7131 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7132 case llvm::Triple::FreeBSD: 7133 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7134 case llvm::Triple::NetBSD: 7135 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7136 default: 7137 return new PPC64TargetInfo(Triple); 7138 } 7139 7140 case llvm::Triple::ppc64le: 7141 switch (os) { 7142 case llvm::Triple::Linux: 7143 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7144 case llvm::Triple::NetBSD: 7145 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7146 default: 7147 return new PPC64TargetInfo(Triple); 7148 } 7149 7150 case llvm::Triple::nvptx: 7151 return new NVPTX32TargetInfo(Triple); 7152 case llvm::Triple::nvptx64: 7153 return new NVPTX64TargetInfo(Triple); 7154 7155 case llvm::Triple::amdgcn: 7156 case llvm::Triple::r600: 7157 return new AMDGPUTargetInfo(Triple); 7158 7159 case llvm::Triple::sparc: 7160 switch (os) { 7161 case llvm::Triple::Linux: 7162 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7163 case llvm::Triple::Solaris: 7164 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7165 case llvm::Triple::NetBSD: 7166 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7167 case llvm::Triple::OpenBSD: 7168 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7169 case llvm::Triple::RTEMS: 7170 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7171 default: 7172 return new SparcV8TargetInfo(Triple); 7173 } 7174 7175 // The 'sparcel' architecture copies all the above cases except for Solaris. 7176 case llvm::Triple::sparcel: 7177 switch (os) { 7178 case llvm::Triple::Linux: 7179 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7180 case llvm::Triple::NetBSD: 7181 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7182 case llvm::Triple::OpenBSD: 7183 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7184 case llvm::Triple::RTEMS: 7185 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7186 default: 7187 return new SparcV8elTargetInfo(Triple); 7188 } 7189 7190 case llvm::Triple::sparcv9: 7191 switch (os) { 7192 case llvm::Triple::Linux: 7193 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7194 case llvm::Triple::Solaris: 7195 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7196 case llvm::Triple::NetBSD: 7197 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7198 case llvm::Triple::OpenBSD: 7199 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7200 case llvm::Triple::FreeBSD: 7201 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7202 default: 7203 return new SparcV9TargetInfo(Triple); 7204 } 7205 7206 case llvm::Triple::systemz: 7207 switch (os) { 7208 case llvm::Triple::Linux: 7209 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7210 default: 7211 return new SystemZTargetInfo(Triple); 7212 } 7213 7214 case llvm::Triple::tce: 7215 return new TCETargetInfo(Triple); 7216 7217 case llvm::Triple::x86: 7218 if (Triple.isOSDarwin()) 7219 return new DarwinI386TargetInfo(Triple); 7220 7221 switch (os) { 7222 case llvm::Triple::CloudABI: 7223 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7224 case llvm::Triple::Linux: { 7225 switch (Triple.getEnvironment()) { 7226 default: 7227 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7228 case llvm::Triple::Android: 7229 return new AndroidX86_32TargetInfo(Triple); 7230 } 7231 } 7232 case llvm::Triple::DragonFly: 7233 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7234 case llvm::Triple::NetBSD: 7235 return new NetBSDI386TargetInfo(Triple); 7236 case llvm::Triple::OpenBSD: 7237 return new OpenBSDI386TargetInfo(Triple); 7238 case llvm::Triple::Bitrig: 7239 return new BitrigI386TargetInfo(Triple); 7240 case llvm::Triple::FreeBSD: 7241 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7242 case llvm::Triple::KFreeBSD: 7243 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7244 case llvm::Triple::Minix: 7245 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7246 case llvm::Triple::Solaris: 7247 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7248 case llvm::Triple::Win32: { 7249 switch (Triple.getEnvironment()) { 7250 default: 7251 return new X86_32TargetInfo(Triple); 7252 case llvm::Triple::Cygnus: 7253 return new CygwinX86_32TargetInfo(Triple); 7254 case llvm::Triple::GNU: 7255 return new MinGWX86_32TargetInfo(Triple); 7256 case llvm::Triple::Itanium: 7257 case llvm::Triple::MSVC: 7258 return new MicrosoftX86_32TargetInfo(Triple); 7259 } 7260 } 7261 case llvm::Triple::Haiku: 7262 return new HaikuX86_32TargetInfo(Triple); 7263 case llvm::Triple::RTEMS: 7264 return new RTEMSX86_32TargetInfo(Triple); 7265 case llvm::Triple::NaCl: 7266 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7267 default: 7268 return new X86_32TargetInfo(Triple); 7269 } 7270 7271 case llvm::Triple::x86_64: 7272 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7273 return new DarwinX86_64TargetInfo(Triple); 7274 7275 switch (os) { 7276 case llvm::Triple::CloudABI: 7277 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7278 case llvm::Triple::Linux: { 7279 switch (Triple.getEnvironment()) { 7280 default: 7281 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7282 case llvm::Triple::Android: 7283 return new AndroidX86_64TargetInfo(Triple); 7284 } 7285 } 7286 case llvm::Triple::DragonFly: 7287 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7288 case llvm::Triple::NetBSD: 7289 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7290 case llvm::Triple::OpenBSD: 7291 return new OpenBSDX86_64TargetInfo(Triple); 7292 case llvm::Triple::Bitrig: 7293 return new BitrigX86_64TargetInfo(Triple); 7294 case llvm::Triple::FreeBSD: 7295 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7296 case llvm::Triple::KFreeBSD: 7297 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7298 case llvm::Triple::Solaris: 7299 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7300 case llvm::Triple::Win32: { 7301 switch (Triple.getEnvironment()) { 7302 default: 7303 return new X86_64TargetInfo(Triple); 7304 case llvm::Triple::GNU: 7305 return new MinGWX86_64TargetInfo(Triple); 7306 case llvm::Triple::MSVC: 7307 return new MicrosoftX86_64TargetInfo(Triple); 7308 } 7309 } 7310 case llvm::Triple::NaCl: 7311 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7312 case llvm::Triple::PS4: 7313 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7314 default: 7315 return new X86_64TargetInfo(Triple); 7316 } 7317 7318 case llvm::Triple::spir: { 7319 if (Triple.getOS() != llvm::Triple::UnknownOS || 7320 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7321 return nullptr; 7322 return new SPIR32TargetInfo(Triple); 7323 } 7324 case llvm::Triple::spir64: { 7325 if (Triple.getOS() != llvm::Triple::UnknownOS || 7326 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7327 return nullptr; 7328 return new SPIR64TargetInfo(Triple); 7329 } 7330 } 7331 } 7332 7333 /// CreateTargetInfo - Return the target info object for the specified target 7334 /// triple. 7335 TargetInfo * 7336 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7337 const std::shared_ptr<TargetOptions> &Opts) { 7338 llvm::Triple Triple(Opts->Triple); 7339 7340 // Construct the target 7341 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7342 if (!Target) { 7343 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7344 return nullptr; 7345 } 7346 Target->TargetOpts = Opts; 7347 7348 // Set the target CPU if specified. 7349 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7350 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7351 return nullptr; 7352 } 7353 7354 // Set the target ABI if specified. 7355 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7356 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7357 return nullptr; 7358 } 7359 7360 // Set the fp math unit. 7361 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7362 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7363 return nullptr; 7364 } 7365 7366 // Compute the default target features, we need the target to handle this 7367 // because features may have dependencies on one another. 7368 llvm::StringMap<bool> Features; 7369 Target->getDefaultFeatures(Features); 7370 7371 // Apply the user specified deltas. 7372 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 7373 I < N; ++I) { 7374 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 7375 // Apply the feature via the target. 7376 bool Enabled = Name[0] == '+'; 7377 Target->setFeatureEnabled(Features, Name + 1, Enabled); 7378 } 7379 7380 // Add the features to the compile options. 7381 // 7382 // FIXME: If we are completely confident that we have the right set, we only 7383 // need to pass the minuses. 7384 Opts->Features.clear(); 7385 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 7386 ie = Features.end(); it != ie; ++it) 7387 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 7388 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7389 return nullptr; 7390 7391 return Target.release(); 7392 } 7393