1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/OwningPtr.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include <algorithm>
32 using namespace clang;
33 
34 //===----------------------------------------------------------------------===//
35 //  Common code shared among targets.
36 //===----------------------------------------------------------------------===//
37 
38 /// DefineStd - Define a macro name and standard variants.  For example if
39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40 /// when in GNU mode.
41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                       const LangOptions &Opts) {
43   assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44 
45   // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46   // in the user's namespace.
47   if (Opts.GNUMode)
48     Builder.defineMacro(MacroName);
49 
50   // Define __unix.
51   Builder.defineMacro("__" + MacroName);
52 
53   // Define __unix__.
54   Builder.defineMacro("__" + MacroName + "__");
55 }
56 
57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                             bool Tuning = true) {
59   Builder.defineMacro("__" + CPUName);
60   Builder.defineMacro("__" + CPUName + "__");
61   if (Tuning)
62     Builder.defineMacro("__tune_" + CPUName + "__");
63 }
64 
65 //===----------------------------------------------------------------------===//
66 // Defines specific to certain operating systems.
67 //===----------------------------------------------------------------------===//
68 
69 namespace {
70 template<typename TgtInfo>
71 class OSTargetInfo : public TgtInfo {
72 protected:
73   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                             MacroBuilder &Builder) const=0;
75 public:
76   OSTargetInfo(const std::string& triple) : TgtInfo(triple) {}
77   virtual void getTargetDefines(const LangOptions &Opts,
78                                 MacroBuilder &Builder) const {
79     TgtInfo::getTargetDefines(Opts, Builder);
80     getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81   }
82 
83 };
84 } // end anonymous namespace
85 
86 
87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                              const llvm::Triple &Triple,
89                              StringRef &PlatformName,
90                              VersionTuple &PlatformMinVersion) {
91   Builder.defineMacro("__APPLE_CC__", "5621");
92   Builder.defineMacro("__APPLE__");
93   Builder.defineMacro("__MACH__");
94   Builder.defineMacro("OBJC_NEW_PROPERTIES");
95   // AddressSanitizer doesn't play well with source fortification, which is on
96   // by default on Darwin.
97   if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98 
99   if (!Opts.ObjCAutoRefCount) {
100     // __weak is always defined, for use in blocks and with objc pointers.
101     Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102 
103     // Darwin defines __strong even in C mode (just to nothing).
104     if (Opts.getGC() != LangOptions::NonGC)
105       Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106     else
107       Builder.defineMacro("__strong", "");
108 
109     // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110     // allow this in C, since one might have block pointers in structs that
111     // are used in pure C code and in Objective-C ARC.
112     Builder.defineMacro("__unsafe_unretained", "");
113   }
114 
115   if (Opts.Static)
116     Builder.defineMacro("__STATIC__");
117   else
118     Builder.defineMacro("__DYNAMIC__");
119 
120   if (Opts.POSIXThreads)
121     Builder.defineMacro("_REENTRANT");
122 
123   // Get the platform type and version number from the triple.
124   unsigned Maj, Min, Rev;
125   if (Triple.isMacOSX()) {
126     Triple.getMacOSXVersion(Maj, Min, Rev);
127     PlatformName = "macosx";
128   } else {
129     Triple.getOSVersion(Maj, Min, Rev);
130     PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131   }
132 
133   // If -target arch-pc-win32-macho option specified, we're
134   // generating code for Win32 ABI. No need to emit
135   // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136   if (PlatformName == "win32") {
137     PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138     return;
139   }
140 
141   // Set the appropriate OS version define.
142   if (Triple.getOS() == llvm::Triple::IOS) {
143     assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144     char Str[6];
145     Str[0] = '0' + Maj;
146     Str[1] = '0' + (Min / 10);
147     Str[2] = '0' + (Min % 10);
148     Str[3] = '0' + (Rev / 10);
149     Str[4] = '0' + (Rev % 10);
150     Str[5] = '\0';
151     Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
152   } else {
153     // Note that the Driver allows versions which aren't representable in the
154     // define (because we only get a single digit for the minor and micro
155     // revision numbers). So, we limit them to the maximum representable
156     // version.
157     assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
158     assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159     char Str[5];
160     Str[0] = '0' + (Maj / 10);
161     Str[1] = '0' + (Maj % 10);
162     Str[2] = '0' + std::min(Min, 9U);
163     Str[3] = '0' + std::min(Rev, 9U);
164     Str[4] = '\0';
165     Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
166   }
167 
168   PlatformMinVersion = VersionTuple(Maj, Min, Rev);
169 }
170 
171 namespace {
172 template<typename Target>
173 class DarwinTargetInfo : public OSTargetInfo<Target> {
174 protected:
175   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
176                             MacroBuilder &Builder) const {
177     getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
178                      this->PlatformMinVersion);
179   }
180 
181 public:
182   DarwinTargetInfo(const std::string& triple) :
183     OSTargetInfo<Target>(triple) {
184       llvm::Triple T = llvm::Triple(triple);
185       this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7);
186       this->MCountName = "\01mcount";
187     }
188 
189   virtual std::string isValidSectionSpecifier(StringRef SR) const {
190     // Let MCSectionMachO validate this.
191     StringRef Segment, Section;
192     unsigned TAA, StubSize;
193     bool HasTAA;
194     return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
195                                                        TAA, HasTAA, StubSize);
196   }
197 
198   virtual const char *getStaticInitSectionSpecifier() const {
199     // FIXME: We should return 0 when building kexts.
200     return "__TEXT,__StaticInit,regular,pure_instructions";
201   }
202 
203   /// Darwin does not support protected visibility.  Darwin's "default"
204   /// is very similar to ELF's "protected";  Darwin requires a "weak"
205   /// attribute on declarations that can be dynamically replaced.
206   virtual bool hasProtectedVisibility() const {
207     return false;
208   }
209 };
210 
211 
212 // DragonFlyBSD Target
213 template<typename Target>
214 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
215 protected:
216   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
217                             MacroBuilder &Builder) const {
218     // DragonFly defines; list based off of gcc output
219     Builder.defineMacro("__DragonFly__");
220     Builder.defineMacro("__DragonFly_cc_version", "100001");
221     Builder.defineMacro("__ELF__");
222     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
223     Builder.defineMacro("__tune_i386__");
224     DefineStd(Builder, "unix", Opts);
225   }
226 public:
227   DragonFlyBSDTargetInfo(const std::string &triple)
228     : OSTargetInfo<Target>(triple) {
229       this->UserLabelPrefix = "";
230 
231       llvm::Triple Triple(triple);
232       switch (Triple.getArch()) {
233         default:
234         case llvm::Triple::x86:
235         case llvm::Triple::x86_64:
236           this->MCountName = ".mcount";
237           break;
238       }
239   }
240 };
241 
242 // FreeBSD Target
243 template<typename Target>
244 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
245 protected:
246   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
247                             MacroBuilder &Builder) const {
248     // FreeBSD defines; list based off of gcc output
249 
250     unsigned Release = Triple.getOSMajorVersion();
251     if (Release == 0U)
252       Release = 8;
253 
254     Builder.defineMacro("__FreeBSD__", Twine(Release));
255     Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
256     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
257     DefineStd(Builder, "unix", Opts);
258     Builder.defineMacro("__ELF__");
259   }
260 public:
261   FreeBSDTargetInfo(const std::string &triple)
262     : OSTargetInfo<Target>(triple) {
263       this->UserLabelPrefix = "";
264 
265       llvm::Triple Triple(triple);
266       switch (Triple.getArch()) {
267         default:
268         case llvm::Triple::x86:
269         case llvm::Triple::x86_64:
270           this->MCountName = ".mcount";
271           break;
272         case llvm::Triple::mips:
273         case llvm::Triple::mipsel:
274         case llvm::Triple::ppc:
275         case llvm::Triple::ppc64:
276           this->MCountName = "_mcount";
277           break;
278         case llvm::Triple::arm:
279           this->MCountName = "__mcount";
280           break;
281       }
282 
283     }
284 };
285 
286 // Minix Target
287 template<typename Target>
288 class MinixTargetInfo : public OSTargetInfo<Target> {
289 protected:
290   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
291                             MacroBuilder &Builder) const {
292     // Minix defines
293 
294     Builder.defineMacro("__minix", "3");
295     Builder.defineMacro("_EM_WSIZE", "4");
296     Builder.defineMacro("_EM_PSIZE", "4");
297     Builder.defineMacro("_EM_SSIZE", "2");
298     Builder.defineMacro("_EM_LSIZE", "4");
299     Builder.defineMacro("_EM_FSIZE", "4");
300     Builder.defineMacro("_EM_DSIZE", "8");
301     Builder.defineMacro("__ELF__");
302     DefineStd(Builder, "unix", Opts);
303   }
304 public:
305   MinixTargetInfo(const std::string &triple)
306     : OSTargetInfo<Target>(triple) {
307       this->UserLabelPrefix = "";
308     }
309 };
310 
311 // Linux target
312 template<typename Target>
313 class LinuxTargetInfo : public OSTargetInfo<Target> {
314 protected:
315   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
316                             MacroBuilder &Builder) const {
317     // Linux defines; list based off of gcc output
318     DefineStd(Builder, "unix", Opts);
319     DefineStd(Builder, "linux", Opts);
320     Builder.defineMacro("__gnu_linux__");
321     Builder.defineMacro("__ELF__");
322     if (Triple.getEnvironment() == llvm::Triple::Android)
323       Builder.defineMacro("__ANDROID__", "1");
324     if (Opts.POSIXThreads)
325       Builder.defineMacro("_REENTRANT");
326     if (Opts.CPlusPlus)
327       Builder.defineMacro("_GNU_SOURCE");
328   }
329 public:
330   LinuxTargetInfo(const std::string& triple)
331     : OSTargetInfo<Target>(triple) {
332     this->UserLabelPrefix = "";
333     this->WIntType = TargetInfo::UnsignedInt;
334   }
335 
336   virtual const char *getStaticInitSectionSpecifier() const {
337     return ".text.startup";
338   }
339 };
340 
341 // NetBSD Target
342 template<typename Target>
343 class NetBSDTargetInfo : public OSTargetInfo<Target> {
344 protected:
345   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
346                             MacroBuilder &Builder) const {
347     // NetBSD defines; list based off of gcc output
348     Builder.defineMacro("__NetBSD__");
349     Builder.defineMacro("__unix__");
350     Builder.defineMacro("__ELF__");
351     if (Opts.POSIXThreads)
352       Builder.defineMacro("_POSIX_THREADS");
353   }
354 public:
355   NetBSDTargetInfo(const std::string &triple)
356     : OSTargetInfo<Target>(triple) {
357       this->UserLabelPrefix = "";
358     }
359 };
360 
361 // OpenBSD Target
362 template<typename Target>
363 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
364 protected:
365   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
366                             MacroBuilder &Builder) const {
367     // OpenBSD defines; list based off of gcc output
368 
369     Builder.defineMacro("__OpenBSD__");
370     DefineStd(Builder, "unix", Opts);
371     Builder.defineMacro("__ELF__");
372     if (Opts.POSIXThreads)
373       Builder.defineMacro("_REENTRANT");
374   }
375 public:
376   OpenBSDTargetInfo(const std::string &triple)
377     : OSTargetInfo<Target>(triple) {
378       this->UserLabelPrefix = "";
379       this->TLSSupported = false;
380 
381       llvm::Triple Triple(triple);
382       switch (Triple.getArch()) {
383         default:
384         case llvm::Triple::x86:
385         case llvm::Triple::x86_64:
386         case llvm::Triple::arm:
387         case llvm::Triple::sparc:
388           this->MCountName = "__mcount";
389           break;
390         case llvm::Triple::mips64:
391         case llvm::Triple::mips64el:
392         case llvm::Triple::ppc:
393         case llvm::Triple::sparcv9:
394           this->MCountName = "_mcount";
395           break;
396       }
397   }
398 };
399 
400 // Bitrig Target
401 template<typename Target>
402 class BitrigTargetInfo : public OSTargetInfo<Target> {
403 protected:
404   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
405                             MacroBuilder &Builder) const {
406     // Bitrig defines; list based off of gcc output
407 
408     Builder.defineMacro("__Bitrig__");
409     DefineStd(Builder, "unix", Opts);
410     Builder.defineMacro("__ELF__");
411     if (Opts.POSIXThreads)
412       Builder.defineMacro("_REENTRANT");
413   }
414 public:
415   BitrigTargetInfo(const std::string &triple)
416     : OSTargetInfo<Target>(triple) {
417       this->UserLabelPrefix = "";
418       this->TLSSupported = false;
419       this->MCountName = "__mcount";
420   }
421 };
422 
423 // PSP Target
424 template<typename Target>
425 class PSPTargetInfo : public OSTargetInfo<Target> {
426 protected:
427   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
428                             MacroBuilder &Builder) const {
429     // PSP defines; list based on the output of the pspdev gcc toolchain.
430     Builder.defineMacro("PSP");
431     Builder.defineMacro("_PSP");
432     Builder.defineMacro("__psp__");
433     Builder.defineMacro("__ELF__");
434   }
435 public:
436   PSPTargetInfo(const std::string& triple)
437     : OSTargetInfo<Target>(triple) {
438     this->UserLabelPrefix = "";
439   }
440 };
441 
442 // PS3 PPU Target
443 template<typename Target>
444 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
445 protected:
446   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
447                             MacroBuilder &Builder) const {
448     // PS3 PPU defines.
449     Builder.defineMacro("__PPC__");
450     Builder.defineMacro("__PPU__");
451     Builder.defineMacro("__CELLOS_LV2__");
452     Builder.defineMacro("__ELF__");
453     Builder.defineMacro("__LP32__");
454     Builder.defineMacro("_ARCH_PPC64");
455     Builder.defineMacro("__powerpc64__");
456   }
457 public:
458   PS3PPUTargetInfo(const std::string& triple)
459     : OSTargetInfo<Target>(triple) {
460     this->UserLabelPrefix = "";
461     this->LongWidth = this->LongAlign = 32;
462     this->PointerWidth = this->PointerAlign = 32;
463     this->IntMaxType = TargetInfo::SignedLongLong;
464     this->UIntMaxType = TargetInfo::UnsignedLongLong;
465     this->Int64Type = TargetInfo::SignedLongLong;
466     this->SizeType = TargetInfo::UnsignedInt;
467     this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
468                               "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
469   }
470 };
471 
472 // FIXME: Need a real SPU target.
473 // PS3 SPU Target
474 template<typename Target>
475 class PS3SPUTargetInfo : public OSTargetInfo<Target> {
476 protected:
477   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
478                             MacroBuilder &Builder) const {
479     // PS3 PPU defines.
480     Builder.defineMacro("__SPU__");
481     Builder.defineMacro("__ELF__");
482   }
483 public:
484   PS3SPUTargetInfo(const std::string& triple)
485     : OSTargetInfo<Target>(triple) {
486     this->UserLabelPrefix = "";
487   }
488 };
489 
490 // AuroraUX target
491 template<typename Target>
492 class AuroraUXTargetInfo : public OSTargetInfo<Target> {
493 protected:
494   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495                             MacroBuilder &Builder) const {
496     DefineStd(Builder, "sun", Opts);
497     DefineStd(Builder, "unix", Opts);
498     Builder.defineMacro("__ELF__");
499     Builder.defineMacro("__svr4__");
500     Builder.defineMacro("__SVR4");
501   }
502 public:
503   AuroraUXTargetInfo(const std::string& triple)
504     : OSTargetInfo<Target>(triple) {
505     this->UserLabelPrefix = "";
506     this->WCharType = this->SignedLong;
507     // FIXME: WIntType should be SignedLong
508   }
509 };
510 
511 // Solaris target
512 template<typename Target>
513 class SolarisTargetInfo : public OSTargetInfo<Target> {
514 protected:
515   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
516                             MacroBuilder &Builder) const {
517     DefineStd(Builder, "sun", Opts);
518     DefineStd(Builder, "unix", Opts);
519     Builder.defineMacro("__ELF__");
520     Builder.defineMacro("__svr4__");
521     Builder.defineMacro("__SVR4");
522     // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
523     // newer, but to 500 for everything else.  feature_test.h has a check to
524     // ensure that you are not using C99 with an old version of X/Open or C89
525     // with a new version.
526     if (Opts.C99 || Opts.C11)
527       Builder.defineMacro("_XOPEN_SOURCE", "600");
528     else
529       Builder.defineMacro("_XOPEN_SOURCE", "500");
530     if (Opts.CPlusPlus)
531       Builder.defineMacro("__C99FEATURES__");
532     Builder.defineMacro("_LARGEFILE_SOURCE");
533     Builder.defineMacro("_LARGEFILE64_SOURCE");
534     Builder.defineMacro("__EXTENSIONS__");
535     Builder.defineMacro("_REENTRANT");
536   }
537 public:
538   SolarisTargetInfo(const std::string& triple)
539     : OSTargetInfo<Target>(triple) {
540     this->UserLabelPrefix = "";
541     this->WCharType = this->SignedInt;
542     // FIXME: WIntType should be SignedLong
543   }
544 };
545 
546 // Windows target
547 template<typename Target>
548 class WindowsTargetInfo : public OSTargetInfo<Target> {
549 protected:
550   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
551                             MacroBuilder &Builder) const {
552     Builder.defineMacro("_WIN32");
553   }
554   void getVisualStudioDefines(const LangOptions &Opts,
555                               MacroBuilder &Builder) const {
556     if (Opts.CPlusPlus) {
557       if (Opts.RTTI)
558         Builder.defineMacro("_CPPRTTI");
559 
560       if (Opts.Exceptions)
561         Builder.defineMacro("_CPPUNWIND");
562     }
563 
564     if (!Opts.CharIsSigned)
565       Builder.defineMacro("_CHAR_UNSIGNED");
566 
567     // FIXME: POSIXThreads isn't exactly the option this should be defined for,
568     //        but it works for now.
569     if (Opts.POSIXThreads)
570       Builder.defineMacro("_MT");
571 
572     if (Opts.MSCVersion != 0)
573       Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
574 
575     if (Opts.MicrosoftExt) {
576       Builder.defineMacro("_MSC_EXTENSIONS");
577 
578       if (Opts.CPlusPlus11) {
579         Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
580         Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
581         Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
582       }
583     }
584 
585     Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
586   }
587 
588 public:
589   WindowsTargetInfo(const std::string &triple)
590     : OSTargetInfo<Target>(triple) {}
591 };
592 
593 template <typename Target>
594 class NaClTargetInfo : public OSTargetInfo<Target> {
595  protected:
596   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
597                             MacroBuilder &Builder) const {
598     if (Opts.POSIXThreads)
599       Builder.defineMacro("_REENTRANT");
600     if (Opts.CPlusPlus)
601       Builder.defineMacro("_GNU_SOURCE");
602 
603     DefineStd(Builder, "unix", Opts);
604     Builder.defineMacro("__ELF__");
605     Builder.defineMacro("__native_client__");
606   }
607  public:
608   NaClTargetInfo(const std::string &triple)
609     : OSTargetInfo<Target>(triple) {
610     this->UserLabelPrefix = "";
611     this->LongAlign = 32;
612     this->LongWidth = 32;
613     this->PointerAlign = 32;
614     this->PointerWidth = 32;
615     this->IntMaxType = TargetInfo::SignedLongLong;
616     this->UIntMaxType = TargetInfo::UnsignedLongLong;
617     this->Int64Type = TargetInfo::SignedLongLong;
618     this->DoubleAlign = 64;
619     this->LongDoubleWidth = 64;
620     this->LongDoubleAlign = 64;
621     this->SizeType = TargetInfo::UnsignedInt;
622     this->PtrDiffType = TargetInfo::SignedInt;
623     this->IntPtrType = TargetInfo::SignedInt;
624     // RegParmMax is inherited from the underlying architecture
625     this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
626     this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
627                               "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
628   }
629   virtual typename Target::CallingConvCheckResult checkCallingConvention(
630       CallingConv CC) const {
631     return CC == CC_PnaclCall ? Target::CCCR_OK :
632         Target::checkCallingConvention(CC);
633   }
634 };
635 } // end anonymous namespace.
636 
637 //===----------------------------------------------------------------------===//
638 // Specific target implementations.
639 //===----------------------------------------------------------------------===//
640 
641 namespace {
642 // PPC abstract base class
643 class PPCTargetInfo : public TargetInfo {
644   static const Builtin::Info BuiltinInfo[];
645   static const char * const GCCRegNames[];
646   static const TargetInfo::GCCRegAlias GCCRegAliases[];
647   std::string CPU;
648 public:
649   PPCTargetInfo(const std::string& triple) : TargetInfo(triple) {
650     LongDoubleWidth = LongDoubleAlign = 128;
651     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
652   }
653 
654   /// \brief Flags for architecture specific defines.
655   typedef enum {
656     ArchDefineNone  = 0,
657     ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
658     ArchDefinePpcgr = 1 << 1,
659     ArchDefinePpcsq = 1 << 2,
660     ArchDefine440   = 1 << 3,
661     ArchDefine603   = 1 << 4,
662     ArchDefine604   = 1 << 5,
663     ArchDefinePwr4  = 1 << 6,
664     ArchDefinePwr5  = 1 << 7,
665     ArchDefinePwr5x = 1 << 8,
666     ArchDefinePwr6  = 1 << 9,
667     ArchDefinePwr6x = 1 << 10,
668     ArchDefinePwr7  = 1 << 11,
669     ArchDefineA2    = 1 << 12,
670     ArchDefineA2q   = 1 << 13
671   } ArchDefineTypes;
672 
673   // Note: GCC recognizes the following additional cpus:
674   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
675   //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
676   //  titan, rs64.
677   virtual bool setCPU(const std::string &Name) {
678     bool CPUKnown = llvm::StringSwitch<bool>(Name)
679       .Case("generic", true)
680       .Case("440", true)
681       .Case("450", true)
682       .Case("601", true)
683       .Case("602", true)
684       .Case("603", true)
685       .Case("603e", true)
686       .Case("603ev", true)
687       .Case("604", true)
688       .Case("604e", true)
689       .Case("620", true)
690       .Case("630", true)
691       .Case("g3", true)
692       .Case("7400", true)
693       .Case("g4", true)
694       .Case("7450", true)
695       .Case("g4+", true)
696       .Case("750", true)
697       .Case("970", true)
698       .Case("g5", true)
699       .Case("a2", true)
700       .Case("a2q", true)
701       .Case("e500mc", true)
702       .Case("e5500", true)
703       .Case("power3", true)
704       .Case("pwr3", true)
705       .Case("power4", true)
706       .Case("pwr4", true)
707       .Case("power5", true)
708       .Case("pwr5", true)
709       .Case("power5x", true)
710       .Case("pwr5x", true)
711       .Case("power6", true)
712       .Case("pwr6", true)
713       .Case("power6x", true)
714       .Case("pwr6x", true)
715       .Case("power7", true)
716       .Case("pwr7", true)
717       .Case("powerpc", true)
718       .Case("ppc", true)
719       .Case("powerpc64", true)
720       .Case("ppc64", true)
721       .Default(false);
722 
723     if (CPUKnown)
724       CPU = Name;
725 
726     return CPUKnown;
727   }
728 
729   virtual void getTargetBuiltins(const Builtin::Info *&Records,
730                                  unsigned &NumRecords) const {
731     Records = BuiltinInfo;
732     NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
733   }
734 
735   virtual bool isCLZForZeroUndef() const { return false; }
736 
737   virtual void getTargetDefines(const LangOptions &Opts,
738                                 MacroBuilder &Builder) const;
739 
740   virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
741 
742   virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
743                                  StringRef Name,
744                                  bool Enabled) const;
745 
746   virtual bool hasFeature(StringRef Feature) const;
747 
748   virtual void getGCCRegNames(const char * const *&Names,
749                               unsigned &NumNames) const;
750   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
751                                 unsigned &NumAliases) const;
752   virtual bool validateAsmConstraint(const char *&Name,
753                                      TargetInfo::ConstraintInfo &Info) const {
754     switch (*Name) {
755     default: return false;
756     case 'O': // Zero
757       break;
758     case 'b': // Base register
759     case 'f': // Floating point register
760       Info.setAllowsRegister();
761       break;
762     // FIXME: The following are added to allow parsing.
763     // I just took a guess at what the actions should be.
764     // Also, is more specific checking needed?  I.e. specific registers?
765     case 'd': // Floating point register (containing 64-bit value)
766     case 'v': // Altivec vector register
767       Info.setAllowsRegister();
768       break;
769     case 'w':
770       switch (Name[1]) {
771         case 'd':// VSX vector register to hold vector double data
772         case 'f':// VSX vector register to hold vector float data
773         case 's':// VSX vector register to hold scalar float data
774         case 'a':// Any VSX register
775           break;
776         default:
777           return false;
778       }
779       Info.setAllowsRegister();
780       Name++; // Skip over 'w'.
781       break;
782     case 'h': // `MQ', `CTR', or `LINK' register
783     case 'q': // `MQ' register
784     case 'c': // `CTR' register
785     case 'l': // `LINK' register
786     case 'x': // `CR' register (condition register) number 0
787     case 'y': // `CR' register (condition register)
788     case 'z': // `XER[CA]' carry bit (part of the XER register)
789       Info.setAllowsRegister();
790       break;
791     case 'I': // Signed 16-bit constant
792     case 'J': // Unsigned 16-bit constant shifted left 16 bits
793               //  (use `L' instead for SImode constants)
794     case 'K': // Unsigned 16-bit constant
795     case 'L': // Signed 16-bit constant shifted left 16 bits
796     case 'M': // Constant larger than 31
797     case 'N': // Exact power of 2
798     case 'P': // Constant whose negation is a signed 16-bit constant
799     case 'G': // Floating point constant that can be loaded into a
800               // register with one instruction per word
801     case 'H': // Integer/Floating point constant that can be loaded
802               // into a register using three instructions
803       break;
804     case 'm': // Memory operand. Note that on PowerPC targets, m can
805               // include addresses that update the base register. It
806               // is therefore only safe to use `m' in an asm statement
807               // if that asm statement accesses the operand exactly once.
808               // The asm statement must also use `%U<opno>' as a
809               // placeholder for the "update" flag in the corresponding
810               // load or store instruction. For example:
811               // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
812               // is correct but:
813               // asm ("st %1,%0" : "=m" (mem) : "r" (val));
814               // is not. Use es rather than m if you don't want the base
815               // register to be updated.
816     case 'e':
817       if (Name[1] != 's')
818           return false;
819               // es: A "stable" memory operand; that is, one which does not
820               // include any automodification of the base register. Unlike
821               // `m', this constraint can be used in asm statements that
822               // might access the operand several times, or that might not
823               // access it at all.
824       Info.setAllowsMemory();
825       Name++; // Skip over 'e'.
826       break;
827     case 'Q': // Memory operand that is an offset from a register (it is
828               // usually better to use `m' or `es' in asm statements)
829     case 'Z': // Memory operand that is an indexed or indirect from a
830               // register (it is usually better to use `m' or `es' in
831               // asm statements)
832       Info.setAllowsMemory();
833       Info.setAllowsRegister();
834       break;
835     case 'R': // AIX TOC entry
836     case 'a': // Address operand that is an indexed or indirect from a
837               // register (`p' is preferable for asm statements)
838     case 'S': // Constant suitable as a 64-bit mask operand
839     case 'T': // Constant suitable as a 32-bit mask operand
840     case 'U': // System V Release 4 small data area reference
841     case 't': // AND masks that can be performed by two rldic{l, r}
842               // instructions
843     case 'W': // Vector constant that does not require memory
844     case 'j': // Vector constant that is all zeros.
845       break;
846     // End FIXME.
847     }
848     return true;
849   }
850   virtual const char *getClobbers() const {
851     return "";
852   }
853   int getEHDataRegisterNumber(unsigned RegNo) const {
854     if (RegNo == 0) return 3;
855     if (RegNo == 1) return 4;
856     return -1;
857   }
858 };
859 
860 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
861 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
862 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
863                                               ALL_LANGUAGES },
864 #include "clang/Basic/BuiltinsPPC.def"
865 };
866 
867 
868 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
869 /// #defines that are not tied to a specific subtarget.
870 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
871                                      MacroBuilder &Builder) const {
872   // Target identification.
873   Builder.defineMacro("__ppc__");
874   Builder.defineMacro("_ARCH_PPC");
875   Builder.defineMacro("__powerpc__");
876   Builder.defineMacro("__POWERPC__");
877   if (PointerWidth == 64) {
878     Builder.defineMacro("_ARCH_PPC64");
879     Builder.defineMacro("__powerpc64__");
880     Builder.defineMacro("__ppc64__");
881   } else {
882     Builder.defineMacro("__ppc__");
883   }
884 
885   // Target properties.
886   if (getTriple().getOS() != llvm::Triple::NetBSD &&
887       getTriple().getOS() != llvm::Triple::OpenBSD)
888     Builder.defineMacro("_BIG_ENDIAN");
889   Builder.defineMacro("__BIG_ENDIAN__");
890 
891   // Subtarget options.
892   Builder.defineMacro("__NATURAL_ALIGNMENT__");
893   Builder.defineMacro("__REGISTER_PREFIX__", "");
894 
895   // FIXME: Should be controlled by command line option.
896   Builder.defineMacro("__LONG_DOUBLE_128__");
897 
898   if (Opts.AltiVec) {
899     Builder.defineMacro("__VEC__", "10206");
900     Builder.defineMacro("__ALTIVEC__");
901   }
902 
903   // CPU identification.
904   ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
905     .Case("440",   ArchDefineName)
906     .Case("450",   ArchDefineName | ArchDefine440)
907     .Case("601",   ArchDefineName)
908     .Case("602",   ArchDefineName | ArchDefinePpcgr)
909     .Case("603",   ArchDefineName | ArchDefinePpcgr)
910     .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
911     .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
912     .Case("604",   ArchDefineName | ArchDefinePpcgr)
913     .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
914     .Case("620",   ArchDefineName | ArchDefinePpcgr)
915     .Case("630",   ArchDefineName | ArchDefinePpcgr)
916     .Case("7400",  ArchDefineName | ArchDefinePpcgr)
917     .Case("7450",  ArchDefineName | ArchDefinePpcgr)
918     .Case("750",   ArchDefineName | ArchDefinePpcgr)
919     .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
920                      | ArchDefinePpcsq)
921     .Case("a2",    ArchDefineA2)
922     .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
923     .Case("pwr3",  ArchDefinePpcgr)
924     .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
925     .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
926                      | ArchDefinePpcsq)
927     .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
928                      | ArchDefinePpcgr | ArchDefinePpcsq)
929     .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
930                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
931     .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
932                      | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
933                      | ArchDefinePpcsq)
934     .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
935                      | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
936                      | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
937     .Case("power3",  ArchDefinePpcgr)
938     .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
939     .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
940                        | ArchDefinePpcsq)
941     .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
942                        | ArchDefinePpcgr | ArchDefinePpcsq)
943     .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
944                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
945     .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
946                        | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
947                        | ArchDefinePpcsq)
948     .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
949                        | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
950                        | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
951     .Default(ArchDefineNone);
952 
953   if (defs & ArchDefineName)
954     Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
955   if (defs & ArchDefinePpcgr)
956     Builder.defineMacro("_ARCH_PPCGR");
957   if (defs & ArchDefinePpcsq)
958     Builder.defineMacro("_ARCH_PPCSQ");
959   if (defs & ArchDefine440)
960     Builder.defineMacro("_ARCH_440");
961   if (defs & ArchDefine603)
962     Builder.defineMacro("_ARCH_603");
963   if (defs & ArchDefine604)
964     Builder.defineMacro("_ARCH_604");
965   if (defs & ArchDefinePwr4)
966     Builder.defineMacro("_ARCH_PWR4");
967   if (defs & ArchDefinePwr5)
968     Builder.defineMacro("_ARCH_PWR5");
969   if (defs & ArchDefinePwr5x)
970     Builder.defineMacro("_ARCH_PWR5X");
971   if (defs & ArchDefinePwr6)
972     Builder.defineMacro("_ARCH_PWR6");
973   if (defs & ArchDefinePwr6x)
974     Builder.defineMacro("_ARCH_PWR6X");
975   if (defs & ArchDefinePwr7)
976     Builder.defineMacro("_ARCH_PWR7");
977   if (defs & ArchDefineA2)
978     Builder.defineMacro("_ARCH_A2");
979   if (defs & ArchDefineA2q) {
980     Builder.defineMacro("_ARCH_A2Q");
981     Builder.defineMacro("_ARCH_QP");
982   }
983 
984   if (getTriple().getVendor() == llvm::Triple::BGQ) {
985     Builder.defineMacro("__bg__");
986     Builder.defineMacro("__THW_BLUEGENE__");
987     Builder.defineMacro("__bgq__");
988     Builder.defineMacro("__TOS_BGQ__");
989   }
990 
991   // FIXME: The following are not yet generated here by Clang, but are
992   //        generated by GCC:
993   //
994   //   _SOFT_FLOAT_
995   //   __RECIP_PRECISION__
996   //   __APPLE_ALTIVEC__
997   //   __VSX__
998   //   __RECIP__
999   //   __RECIPF__
1000   //   __RSQRTE__
1001   //   __RSQRTEF__
1002   //   _SOFT_DOUBLE_
1003   //   __NO_LWSYNC__
1004   //   __HAVE_BSWAP__
1005   //   __LONGDOUBLE128
1006   //   __CMODEL_MEDIUM__
1007   //   __CMODEL_LARGE__
1008   //   _CALL_SYSV
1009   //   _CALL_DARWIN
1010   //   __NO_FPRS__
1011 }
1012 
1013 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1014   Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1015     .Case("7400", true)
1016     .Case("g4", true)
1017     .Case("7450", true)
1018     .Case("g4+", true)
1019     .Case("970", true)
1020     .Case("g5", true)
1021     .Case("pwr6", true)
1022     .Case("pwr7", true)
1023     .Case("ppc64", true)
1024     .Default(false);
1025 
1026   Features["qpx"] = (CPU == "a2q");
1027 }
1028 
1029 bool PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1030                                          StringRef Name,
1031                                          bool Enabled) const {
1032   if (Name == "altivec" || Name == "fprnd" || Name == "mfocrf" ||
1033       Name == "popcntd" || Name == "qpx") {
1034     Features[Name] = Enabled;
1035     return true;
1036   }
1037 
1038   return false;
1039 }
1040 
1041 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1042   return Feature == "powerpc";
1043 }
1044 
1045 
1046 const char * const PPCTargetInfo::GCCRegNames[] = {
1047   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1048   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1049   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1050   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1051   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1052   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1053   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1054   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1055   "mq", "lr", "ctr", "ap",
1056   "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1057   "xer",
1058   "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1059   "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1060   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1061   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1062   "vrsave", "vscr",
1063   "spe_acc", "spefscr",
1064   "sfp"
1065 };
1066 
1067 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1068                                    unsigned &NumNames) const {
1069   Names = GCCRegNames;
1070   NumNames = llvm::array_lengthof(GCCRegNames);
1071 }
1072 
1073 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1074   // While some of these aliases do map to different registers
1075   // they still share the same register name.
1076   { { "0" }, "r0" },
1077   { { "1"}, "r1" },
1078   { { "2" }, "r2" },
1079   { { "3" }, "r3" },
1080   { { "4" }, "r4" },
1081   { { "5" }, "r5" },
1082   { { "6" }, "r6" },
1083   { { "7" }, "r7" },
1084   { { "8" }, "r8" },
1085   { { "9" }, "r9" },
1086   { { "10" }, "r10" },
1087   { { "11" }, "r11" },
1088   { { "12" }, "r12" },
1089   { { "13" }, "r13" },
1090   { { "14" }, "r14" },
1091   { { "15" }, "r15" },
1092   { { "16" }, "r16" },
1093   { { "17" }, "r17" },
1094   { { "18" }, "r18" },
1095   { { "19" }, "r19" },
1096   { { "20" }, "r20" },
1097   { { "21" }, "r21" },
1098   { { "22" }, "r22" },
1099   { { "23" }, "r23" },
1100   { { "24" }, "r24" },
1101   { { "25" }, "r25" },
1102   { { "26" }, "r26" },
1103   { { "27" }, "r27" },
1104   { { "28" }, "r28" },
1105   { { "29" }, "r29" },
1106   { { "30" }, "r30" },
1107   { { "31" }, "r31" },
1108   { { "fr0" }, "f0" },
1109   { { "fr1" }, "f1" },
1110   { { "fr2" }, "f2" },
1111   { { "fr3" }, "f3" },
1112   { { "fr4" }, "f4" },
1113   { { "fr5" }, "f5" },
1114   { { "fr6" }, "f6" },
1115   { { "fr7" }, "f7" },
1116   { { "fr8" }, "f8" },
1117   { { "fr9" }, "f9" },
1118   { { "fr10" }, "f10" },
1119   { { "fr11" }, "f11" },
1120   { { "fr12" }, "f12" },
1121   { { "fr13" }, "f13" },
1122   { { "fr14" }, "f14" },
1123   { { "fr15" }, "f15" },
1124   { { "fr16" }, "f16" },
1125   { { "fr17" }, "f17" },
1126   { { "fr18" }, "f18" },
1127   { { "fr19" }, "f19" },
1128   { { "fr20" }, "f20" },
1129   { { "fr21" }, "f21" },
1130   { { "fr22" }, "f22" },
1131   { { "fr23" }, "f23" },
1132   { { "fr24" }, "f24" },
1133   { { "fr25" }, "f25" },
1134   { { "fr26" }, "f26" },
1135   { { "fr27" }, "f27" },
1136   { { "fr28" }, "f28" },
1137   { { "fr29" }, "f29" },
1138   { { "fr30" }, "f30" },
1139   { { "fr31" }, "f31" },
1140   { { "cc" }, "cr0" },
1141 };
1142 
1143 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1144                                      unsigned &NumAliases) const {
1145   Aliases = GCCRegAliases;
1146   NumAliases = llvm::array_lengthof(GCCRegAliases);
1147 }
1148 } // end anonymous namespace.
1149 
1150 namespace {
1151 class PPC32TargetInfo : public PPCTargetInfo {
1152 public:
1153   PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) {
1154     DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1155                         "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1156 
1157     switch (getTriple().getOS()) {
1158     case llvm::Triple::Linux:
1159     case llvm::Triple::FreeBSD:
1160     case llvm::Triple::NetBSD:
1161       SizeType = UnsignedInt;
1162       PtrDiffType = SignedInt;
1163       IntPtrType = SignedInt;
1164       break;
1165     default:
1166       break;
1167     }
1168 
1169     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1170       LongDoubleWidth = LongDoubleAlign = 64;
1171       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1172     }
1173 
1174     // PPC32 supports atomics up to 4 bytes.
1175     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1176   }
1177 
1178   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1179     // This is the ELF definition, and is overridden by the Darwin sub-target
1180     return TargetInfo::PowerABIBuiltinVaList;
1181   }
1182 };
1183 } // end anonymous namespace.
1184 
1185 namespace {
1186 class PPC64TargetInfo : public PPCTargetInfo {
1187 public:
1188   PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) {
1189     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1190     IntMaxType = SignedLong;
1191     UIntMaxType = UnsignedLong;
1192     Int64Type = SignedLong;
1193 
1194     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1195       LongDoubleWidth = LongDoubleAlign = 64;
1196       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1197       DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1198                           "i64:64:64-f32:32:32-f64:64:64-f128:64:64-"
1199                           "v128:128:128-n32:64";
1200     } else
1201       DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1202                           "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1203                           "v128:128:128-n32:64";
1204 
1205     // PPC64 supports atomics up to 8 bytes.
1206     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1207   }
1208   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1209     return TargetInfo::CharPtrBuiltinVaList;
1210   }
1211 };
1212 } // end anonymous namespace.
1213 
1214 
1215 namespace {
1216 class DarwinPPC32TargetInfo :
1217   public DarwinTargetInfo<PPC32TargetInfo> {
1218 public:
1219   DarwinPPC32TargetInfo(const std::string& triple)
1220     : DarwinTargetInfo<PPC32TargetInfo>(triple) {
1221     HasAlignMac68kSupport = true;
1222     BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1223     LongLongAlign = 32;
1224     SuitableAlign = 128;
1225     DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1226                         "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1227   }
1228   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1229     return TargetInfo::CharPtrBuiltinVaList;
1230   }
1231 };
1232 
1233 class DarwinPPC64TargetInfo :
1234   public DarwinTargetInfo<PPC64TargetInfo> {
1235 public:
1236   DarwinPPC64TargetInfo(const std::string& triple)
1237     : DarwinTargetInfo<PPC64TargetInfo>(triple) {
1238     HasAlignMac68kSupport = true;
1239     SuitableAlign = 128;
1240     DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1241                         "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1242   }
1243 };
1244 } // end anonymous namespace.
1245 
1246 namespace {
1247   static const unsigned NVPTXAddrSpaceMap[] = {
1248     1,    // opencl_global
1249     3,    // opencl_local
1250     4,    // opencl_constant
1251     1,    // cuda_device
1252     4,    // cuda_constant
1253     3,    // cuda_shared
1254   };
1255   class NVPTXTargetInfo : public TargetInfo {
1256     static const char * const GCCRegNames[];
1257     static const Builtin::Info BuiltinInfo[];
1258     std::vector<StringRef> AvailableFeatures;
1259   public:
1260     NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) {
1261       BigEndian = false;
1262       TLSSupported = false;
1263       LongWidth = LongAlign = 64;
1264       AddrSpaceMap = &NVPTXAddrSpaceMap;
1265       // Define available target features
1266       // These must be defined in sorted order!
1267       NoAsmVariants = true;
1268     }
1269     virtual void getTargetDefines(const LangOptions &Opts,
1270                                   MacroBuilder &Builder) const {
1271       Builder.defineMacro("__PTX__");
1272       Builder.defineMacro("__NVPTX__");
1273     }
1274     virtual void getTargetBuiltins(const Builtin::Info *&Records,
1275                                    unsigned &NumRecords) const {
1276       Records = BuiltinInfo;
1277       NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1278     }
1279     virtual bool hasFeature(StringRef Feature) const {
1280       return Feature == "ptx" || Feature == "nvptx";
1281     }
1282 
1283     virtual void getGCCRegNames(const char * const *&Names,
1284                                 unsigned &NumNames) const;
1285     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1286                                   unsigned &NumAliases) const {
1287       // No aliases.
1288       Aliases = 0;
1289       NumAliases = 0;
1290     }
1291     virtual bool validateAsmConstraint(const char *&Name,
1292                                        TargetInfo::ConstraintInfo &info) const {
1293       // FIXME: implement
1294       return true;
1295     }
1296     virtual const char *getClobbers() const {
1297       // FIXME: Is this really right?
1298       return "";
1299     }
1300     virtual BuiltinVaListKind getBuiltinVaListKind() const {
1301       // FIXME: implement
1302       return TargetInfo::CharPtrBuiltinVaList;
1303     }
1304     virtual bool setCPU(const std::string &Name) {
1305       bool Valid = llvm::StringSwitch<bool>(Name)
1306         .Case("sm_20", true)
1307         .Case("sm_21", true)
1308         .Case("sm_30", true)
1309         .Case("sm_35", true)
1310         .Default(false);
1311 
1312       return Valid;
1313     }
1314     virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1315                                    StringRef Name,
1316                                    bool Enabled) const;
1317   };
1318 
1319   const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1320 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1321 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1322                                               ALL_LANGUAGES },
1323 #include "clang/Basic/BuiltinsNVPTX.def"
1324   };
1325 
1326   const char * const NVPTXTargetInfo::GCCRegNames[] = {
1327     "r0"
1328   };
1329 
1330   void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1331                                      unsigned &NumNames) const {
1332     Names = GCCRegNames;
1333     NumNames = llvm::array_lengthof(GCCRegNames);
1334   }
1335 
1336   bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1337                                           StringRef Name,
1338                                           bool Enabled) const {
1339     if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(),
1340                           Name)) {
1341       Features[Name] = Enabled;
1342       return true;
1343     } else {
1344       return false;
1345     }
1346   }
1347 
1348   class NVPTX32TargetInfo : public NVPTXTargetInfo {
1349   public:
1350     NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1351       PointerWidth = PointerAlign = 32;
1352       SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1353       DescriptionString
1354         = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1355           "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1356           "n16:32:64";
1357   }
1358   };
1359 
1360   class NVPTX64TargetInfo : public NVPTXTargetInfo {
1361   public:
1362     NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1363       PointerWidth = PointerAlign = 64;
1364       SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1365       DescriptionString
1366         = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1367           "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1368           "n16:32:64";
1369   }
1370   };
1371 }
1372 
1373 namespace {
1374 
1375 static const unsigned R600AddrSpaceMap[] = {
1376   1,    // opencl_global
1377   3,    // opencl_local
1378   2,    // opencl_constant
1379   1,    // cuda_device
1380   2,    // cuda_constant
1381   3     // cuda_shared
1382 };
1383 
1384 static const char *DescriptionStringR600 =
1385   "e"
1386   "-p:32:32:32"
1387   "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
1388   "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1389   "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1390   "-n32:64";
1391 
1392 static const char *DescriptionStringR600DoubleOps =
1393   "e"
1394   "-p:32:32:32"
1395   "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1396   "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1397   "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1398   "-n32:64";
1399 
1400 static const char *DescriptionStringSI =
1401   "e"
1402   "-p:64:64:64"
1403   "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1404   "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1405   "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1406   "-n32:64";
1407 
1408 class R600TargetInfo : public TargetInfo {
1409   /// \brief The GPU profiles supported by the R600 target.
1410   enum GPUKind {
1411     GK_NONE,
1412     GK_R600,
1413     GK_R600_DOUBLE_OPS,
1414     GK_R700,
1415     GK_R700_DOUBLE_OPS,
1416     GK_EVERGREEN,
1417     GK_EVERGREEN_DOUBLE_OPS,
1418     GK_NORTHERN_ISLANDS,
1419     GK_CAYMAN,
1420     GK_SOUTHERN_ISLANDS
1421   } GPU;
1422 
1423 public:
1424   R600TargetInfo(const std::string& triple)
1425     : TargetInfo(triple),
1426       GPU(GK_R600) {
1427     DescriptionString = DescriptionStringR600;
1428     AddrSpaceMap = &R600AddrSpaceMap;
1429   }
1430 
1431   virtual const char * getClobbers() const {
1432     return "";
1433   }
1434 
1435   virtual void getGCCRegNames(const char * const *&Names,
1436                               unsigned &numNames) const  {
1437     Names = NULL;
1438     numNames = 0;
1439   }
1440 
1441   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1442                                 unsigned &NumAliases) const {
1443     Aliases = NULL;
1444     NumAliases = 0;
1445   }
1446 
1447   virtual bool validateAsmConstraint(const char *&Name,
1448                                      TargetInfo::ConstraintInfo &info) const {
1449     return true;
1450   }
1451 
1452   virtual void getTargetBuiltins(const Builtin::Info *&Records,
1453                                  unsigned &NumRecords) const {
1454     Records = NULL;
1455     NumRecords = 0;
1456   }
1457 
1458 
1459   virtual void getTargetDefines(const LangOptions &Opts,
1460                                 MacroBuilder &Builder) const {
1461     Builder.defineMacro("__R600__");
1462   }
1463 
1464   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1465     return TargetInfo::CharPtrBuiltinVaList;
1466   }
1467 
1468   virtual bool setCPU(const std::string &Name) {
1469     GPU = llvm::StringSwitch<GPUKind>(Name)
1470       .Case("r600" ,    GK_R600)
1471       .Case("rv610",    GK_R600)
1472       .Case("rv620",    GK_R600)
1473       .Case("rv630",    GK_R600)
1474       .Case("rv635",    GK_R600)
1475       .Case("rs780",    GK_R600)
1476       .Case("rs880",    GK_R600)
1477       .Case("rv670",    GK_R600_DOUBLE_OPS)
1478       .Case("rv710",    GK_R700)
1479       .Case("rv730",    GK_R700)
1480       .Case("rv740",    GK_R700_DOUBLE_OPS)
1481       .Case("rv770",    GK_R700_DOUBLE_OPS)
1482       .Case("palm",     GK_EVERGREEN)
1483       .Case("cedar",    GK_EVERGREEN)
1484       .Case("sumo",     GK_EVERGREEN)
1485       .Case("sumo2",    GK_EVERGREEN)
1486       .Case("redwood",  GK_EVERGREEN)
1487       .Case("juniper",  GK_EVERGREEN)
1488       .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1489       .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1490       .Case("barts",    GK_NORTHERN_ISLANDS)
1491       .Case("turks",    GK_NORTHERN_ISLANDS)
1492       .Case("caicos",   GK_NORTHERN_ISLANDS)
1493       .Case("cayman",   GK_CAYMAN)
1494       .Case("aruba",    GK_CAYMAN)
1495       .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1496       .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1497       .Case("verde",    GK_SOUTHERN_ISLANDS)
1498       .Case("oland",    GK_SOUTHERN_ISLANDS)
1499       .Default(GK_NONE);
1500 
1501     if (GPU == GK_NONE) {
1502       return false;
1503     }
1504 
1505     // Set the correct data layout
1506     switch (GPU) {
1507     case GK_NONE:
1508     case GK_R600:
1509     case GK_R700:
1510     case GK_EVERGREEN:
1511     case GK_NORTHERN_ISLANDS:
1512       DescriptionString = DescriptionStringR600;
1513       break;
1514     case GK_R600_DOUBLE_OPS:
1515     case GK_R700_DOUBLE_OPS:
1516     case GK_EVERGREEN_DOUBLE_OPS:
1517     case GK_CAYMAN:
1518       DescriptionString = DescriptionStringR600DoubleOps;
1519       break;
1520     case GK_SOUTHERN_ISLANDS:
1521       DescriptionString = DescriptionStringSI;
1522       break;
1523     }
1524 
1525     return true;
1526   }
1527 };
1528 
1529 } // end anonymous namespace
1530 
1531 namespace {
1532 // MBlaze abstract base class
1533 class MBlazeTargetInfo : public TargetInfo {
1534   static const char * const GCCRegNames[];
1535   static const TargetInfo::GCCRegAlias GCCRegAliases[];
1536 
1537 public:
1538   MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) {
1539     DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16";
1540   }
1541 
1542   virtual void getTargetBuiltins(const Builtin::Info *&Records,
1543                                  unsigned &NumRecords) const {
1544     // FIXME: Implement.
1545     Records = 0;
1546     NumRecords = 0;
1547   }
1548 
1549   virtual void getTargetDefines(const LangOptions &Opts,
1550                                 MacroBuilder &Builder) const;
1551 
1552   virtual bool hasFeature(StringRef Feature) const {
1553     return Feature == "mblaze";
1554   }
1555 
1556   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1557     return TargetInfo::CharPtrBuiltinVaList;
1558   }
1559   virtual const char *getTargetPrefix() const {
1560     return "mblaze";
1561   }
1562   virtual void getGCCRegNames(const char * const *&Names,
1563                               unsigned &NumNames) const;
1564   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1565                                 unsigned &NumAliases) const;
1566   virtual bool validateAsmConstraint(const char *&Name,
1567                                      TargetInfo::ConstraintInfo &Info) const {
1568     switch (*Name) {
1569     default: return false;
1570     case 'O': // Zero
1571       return true;
1572     case 'b': // Base register
1573     case 'f': // Floating point register
1574       Info.setAllowsRegister();
1575       return true;
1576     }
1577   }
1578   virtual const char *getClobbers() const {
1579     return "";
1580   }
1581 };
1582 
1583 /// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific
1584 /// #defines that are not tied to a specific subtarget.
1585 void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts,
1586                                      MacroBuilder &Builder) const {
1587   // Target identification.
1588   Builder.defineMacro("__microblaze__");
1589   Builder.defineMacro("_ARCH_MICROBLAZE");
1590   Builder.defineMacro("__MICROBLAZE__");
1591 
1592   // Target properties.
1593   Builder.defineMacro("_BIG_ENDIAN");
1594   Builder.defineMacro("__BIG_ENDIAN__");
1595 
1596   // Subtarget options.
1597   Builder.defineMacro("__REGISTER_PREFIX__", "");
1598 }
1599 
1600 
1601 const char * const MBlazeTargetInfo::GCCRegNames[] = {
1602   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
1603   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
1604   "r16",  "r17",  "r18",  "r19",  "r20",  "r21",  "r22",  "r23",
1605   "r24",  "r25",  "r26",  "r27",  "r28",  "r29",  "r30",  "r31",
1606   "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
1607   "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1608   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1609   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
1610   "hi",   "lo",   "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4",
1611   "$fcc5","$fcc6","$fcc7","$ap",  "$rap", "$frp"
1612 };
1613 
1614 void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names,
1615                                    unsigned &NumNames) const {
1616   Names = GCCRegNames;
1617   NumNames = llvm::array_lengthof(GCCRegNames);
1618 }
1619 
1620 const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = {
1621   { {"f0"},  "r0" },
1622   { {"f1"},  "r1" },
1623   { {"f2"},  "r2" },
1624   { {"f3"},  "r3" },
1625   { {"f4"},  "r4" },
1626   { {"f5"},  "r5" },
1627   { {"f6"},  "r6" },
1628   { {"f7"},  "r7" },
1629   { {"f8"},  "r8" },
1630   { {"f9"},  "r9" },
1631   { {"f10"}, "r10" },
1632   { {"f11"}, "r11" },
1633   { {"f12"}, "r12" },
1634   { {"f13"}, "r13" },
1635   { {"f14"}, "r14" },
1636   { {"f15"}, "r15" },
1637   { {"f16"}, "r16" },
1638   { {"f17"}, "r17" },
1639   { {"f18"}, "r18" },
1640   { {"f19"}, "r19" },
1641   { {"f20"}, "r20" },
1642   { {"f21"}, "r21" },
1643   { {"f22"}, "r22" },
1644   { {"f23"}, "r23" },
1645   { {"f24"}, "r24" },
1646   { {"f25"}, "r25" },
1647   { {"f26"}, "r26" },
1648   { {"f27"}, "r27" },
1649   { {"f28"}, "r28" },
1650   { {"f29"}, "r29" },
1651   { {"f30"}, "r30" },
1652   { {"f31"}, "r31" },
1653 };
1654 
1655 void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1656                                      unsigned &NumAliases) const {
1657   Aliases = GCCRegAliases;
1658   NumAliases = llvm::array_lengthof(GCCRegAliases);
1659 }
1660 } // end anonymous namespace.
1661 
1662 namespace {
1663 // Namespace for x86 abstract base class
1664 const Builtin::Info BuiltinInfo[] = {
1665 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1666 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1667                                               ALL_LANGUAGES },
1668 #include "clang/Basic/BuiltinsX86.def"
1669 };
1670 
1671 static const char* const GCCRegNames[] = {
1672   "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1673   "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1674   "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1675   "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1676   "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1677   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1678   "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1679   "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1680   "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1681 };
1682 
1683 const TargetInfo::AddlRegName AddlRegNames[] = {
1684   { { "al", "ah", "eax", "rax" }, 0 },
1685   { { "bl", "bh", "ebx", "rbx" }, 3 },
1686   { { "cl", "ch", "ecx", "rcx" }, 2 },
1687   { { "dl", "dh", "edx", "rdx" }, 1 },
1688   { { "esi", "rsi" }, 4 },
1689   { { "edi", "rdi" }, 5 },
1690   { { "esp", "rsp" }, 7 },
1691   { { "ebp", "rbp" }, 6 },
1692 };
1693 
1694 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1695 // most of the implementation can be shared.
1696 class X86TargetInfo : public TargetInfo {
1697   enum X86SSEEnum {
1698     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
1699   } SSELevel;
1700   enum MMX3DNowEnum {
1701     NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1702   } MMX3DNowLevel;
1703 
1704   bool HasAES;
1705   bool HasPCLMUL;
1706   bool HasLZCNT;
1707   bool HasRDRND;
1708   bool HasBMI;
1709   bool HasBMI2;
1710   bool HasPOPCNT;
1711   bool HasRTM;
1712   bool HasPRFCHW;
1713   bool HasRDSEED;
1714   bool HasSSE4a;
1715   bool HasFMA4;
1716   bool HasFMA;
1717   bool HasXOP;
1718   bool HasF16C;
1719 
1720   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1721   ///
1722   /// Each enumeration represents a particular CPU supported by Clang. These
1723   /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1724   enum CPUKind {
1725     CK_Generic,
1726 
1727     /// \name i386
1728     /// i386-generation processors.
1729     //@{
1730     CK_i386,
1731     //@}
1732 
1733     /// \name i486
1734     /// i486-generation processors.
1735     //@{
1736     CK_i486,
1737     CK_WinChipC6,
1738     CK_WinChip2,
1739     CK_C3,
1740     //@}
1741 
1742     /// \name i586
1743     /// i586-generation processors, P5 microarchitecture based.
1744     //@{
1745     CK_i586,
1746     CK_Pentium,
1747     CK_PentiumMMX,
1748     //@}
1749 
1750     /// \name i686
1751     /// i686-generation processors, P6 / Pentium M microarchitecture based.
1752     //@{
1753     CK_i686,
1754     CK_PentiumPro,
1755     CK_Pentium2,
1756     CK_Pentium3,
1757     CK_Pentium3M,
1758     CK_PentiumM,
1759     CK_C3_2,
1760 
1761     /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1762     /// Clang however has some logic to suport this.
1763     // FIXME: Warn, deprecate, and potentially remove this.
1764     CK_Yonah,
1765     //@}
1766 
1767     /// \name Netburst
1768     /// Netburst microarchitecture based processors.
1769     //@{
1770     CK_Pentium4,
1771     CK_Pentium4M,
1772     CK_Prescott,
1773     CK_Nocona,
1774     //@}
1775 
1776     /// \name Core
1777     /// Core microarchitecture based processors.
1778     //@{
1779     CK_Core2,
1780 
1781     /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1782     /// codename which GCC no longer accepts as an option to -march, but Clang
1783     /// has some logic for recognizing it.
1784     // FIXME: Warn, deprecate, and potentially remove this.
1785     CK_Penryn,
1786     //@}
1787 
1788     /// \name Atom
1789     /// Atom processors
1790     //@{
1791     CK_Atom,
1792     //@}
1793 
1794     /// \name Nehalem
1795     /// Nehalem microarchitecture based processors.
1796     //@{
1797     CK_Corei7,
1798     CK_Corei7AVX,
1799     CK_CoreAVXi,
1800     CK_CoreAVX2,
1801     //@}
1802 
1803     /// \name K6
1804     /// K6 architecture processors.
1805     //@{
1806     CK_K6,
1807     CK_K6_2,
1808     CK_K6_3,
1809     //@}
1810 
1811     /// \name K7
1812     /// K7 architecture processors.
1813     //@{
1814     CK_Athlon,
1815     CK_AthlonThunderbird,
1816     CK_Athlon4,
1817     CK_AthlonXP,
1818     CK_AthlonMP,
1819     //@}
1820 
1821     /// \name K8
1822     /// K8 architecture processors.
1823     //@{
1824     CK_Athlon64,
1825     CK_Athlon64SSE3,
1826     CK_AthlonFX,
1827     CK_K8,
1828     CK_K8SSE3,
1829     CK_Opteron,
1830     CK_OpteronSSE3,
1831     CK_AMDFAM10,
1832     //@}
1833 
1834     /// \name Bobcat
1835     /// Bobcat architecture processors.
1836     //@{
1837     CK_BTVER1,
1838     CK_BTVER2,
1839     //@}
1840 
1841     /// \name Bulldozer
1842     /// Bulldozer architecture processors.
1843     //@{
1844     CK_BDVER1,
1845     CK_BDVER2,
1846     //@}
1847 
1848     /// This specification is deprecated and will be removed in the future.
1849     /// Users should prefer \see CK_K8.
1850     // FIXME: Warn on this when the CPU is set to it.
1851     CK_x86_64,
1852     //@}
1853 
1854     /// \name Geode
1855     /// Geode processors.
1856     //@{
1857     CK_Geode
1858     //@}
1859   } CPU;
1860 
1861 public:
1862   X86TargetInfo(const std::string& triple)
1863     : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1864       HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false),
1865       HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false),
1866       HasPRFCHW(false), HasRDSEED(false), HasSSE4a(false), HasFMA4(false),
1867       HasFMA(false), HasXOP(false), HasF16C(false), CPU(CK_Generic) {
1868     BigEndian = false;
1869     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1870   }
1871   virtual unsigned getFloatEvalMethod() const {
1872     // X87 evaluates with 80 bits "long double" precision.
1873     return SSELevel == NoSSE ? 2 : 0;
1874   }
1875   virtual void getTargetBuiltins(const Builtin::Info *&Records,
1876                                  unsigned &NumRecords) const {
1877     Records = BuiltinInfo;
1878     NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1879   }
1880   virtual void getGCCRegNames(const char * const *&Names,
1881                               unsigned &NumNames) const {
1882     Names = GCCRegNames;
1883     NumNames = llvm::array_lengthof(GCCRegNames);
1884   }
1885   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1886                                 unsigned &NumAliases) const {
1887     Aliases = 0;
1888     NumAliases = 0;
1889   }
1890   virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1891                                   unsigned &NumNames) const {
1892     Names = AddlRegNames;
1893     NumNames = llvm::array_lengthof(AddlRegNames);
1894   }
1895   virtual bool validateAsmConstraint(const char *&Name,
1896                                      TargetInfo::ConstraintInfo &info) const;
1897   virtual std::string convertConstraint(const char *&Constraint) const;
1898   virtual const char *getClobbers() const {
1899     return "~{dirflag},~{fpsr},~{flags}";
1900   }
1901   virtual void getTargetDefines(const LangOptions &Opts,
1902                                 MacroBuilder &Builder) const;
1903   virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1904                                  StringRef Name,
1905                                  bool Enabled) const;
1906   virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1907   virtual bool hasFeature(StringRef Feature) const;
1908   virtual void HandleTargetFeatures(std::vector<std::string> &Features);
1909   virtual const char* getABI() const {
1910     if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1911       return "avx";
1912     else if (getTriple().getArch() == llvm::Triple::x86 &&
1913              MMX3DNowLevel == NoMMX3DNow)
1914       return "no-mmx";
1915     return "";
1916   }
1917   virtual bool setCPU(const std::string &Name) {
1918     CPU = llvm::StringSwitch<CPUKind>(Name)
1919       .Case("i386", CK_i386)
1920       .Case("i486", CK_i486)
1921       .Case("winchip-c6", CK_WinChipC6)
1922       .Case("winchip2", CK_WinChip2)
1923       .Case("c3", CK_C3)
1924       .Case("i586", CK_i586)
1925       .Case("pentium", CK_Pentium)
1926       .Case("pentium-mmx", CK_PentiumMMX)
1927       .Case("i686", CK_i686)
1928       .Case("pentiumpro", CK_PentiumPro)
1929       .Case("pentium2", CK_Pentium2)
1930       .Case("pentium3", CK_Pentium3)
1931       .Case("pentium3m", CK_Pentium3M)
1932       .Case("pentium-m", CK_PentiumM)
1933       .Case("c3-2", CK_C3_2)
1934       .Case("yonah", CK_Yonah)
1935       .Case("pentium4", CK_Pentium4)
1936       .Case("pentium4m", CK_Pentium4M)
1937       .Case("prescott", CK_Prescott)
1938       .Case("nocona", CK_Nocona)
1939       .Case("core2", CK_Core2)
1940       .Case("penryn", CK_Penryn)
1941       .Case("atom", CK_Atom)
1942       .Case("corei7", CK_Corei7)
1943       .Case("corei7-avx", CK_Corei7AVX)
1944       .Case("core-avx-i", CK_CoreAVXi)
1945       .Case("core-avx2", CK_CoreAVX2)
1946       .Case("k6", CK_K6)
1947       .Case("k6-2", CK_K6_2)
1948       .Case("k6-3", CK_K6_3)
1949       .Case("athlon", CK_Athlon)
1950       .Case("athlon-tbird", CK_AthlonThunderbird)
1951       .Case("athlon-4", CK_Athlon4)
1952       .Case("athlon-xp", CK_AthlonXP)
1953       .Case("athlon-mp", CK_AthlonMP)
1954       .Case("athlon64", CK_Athlon64)
1955       .Case("athlon64-sse3", CK_Athlon64SSE3)
1956       .Case("athlon-fx", CK_AthlonFX)
1957       .Case("k8", CK_K8)
1958       .Case("k8-sse3", CK_K8SSE3)
1959       .Case("opteron", CK_Opteron)
1960       .Case("opteron-sse3", CK_OpteronSSE3)
1961       .Case("amdfam10", CK_AMDFAM10)
1962       .Case("btver1", CK_BTVER1)
1963       .Case("btver2", CK_BTVER2)
1964       .Case("bdver1", CK_BDVER1)
1965       .Case("bdver2", CK_BDVER2)
1966       .Case("x86-64", CK_x86_64)
1967       .Case("geode", CK_Geode)
1968       .Default(CK_Generic);
1969 
1970     // Perform any per-CPU checks necessary to determine if this CPU is
1971     // acceptable.
1972     // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1973     // invalid without explaining *why*.
1974     switch (CPU) {
1975     case CK_Generic:
1976       // No processor selected!
1977       return false;
1978 
1979     case CK_i386:
1980     case CK_i486:
1981     case CK_WinChipC6:
1982     case CK_WinChip2:
1983     case CK_C3:
1984     case CK_i586:
1985     case CK_Pentium:
1986     case CK_PentiumMMX:
1987     case CK_i686:
1988     case CK_PentiumPro:
1989     case CK_Pentium2:
1990     case CK_Pentium3:
1991     case CK_Pentium3M:
1992     case CK_PentiumM:
1993     case CK_Yonah:
1994     case CK_C3_2:
1995     case CK_Pentium4:
1996     case CK_Pentium4M:
1997     case CK_Prescott:
1998     case CK_K6:
1999     case CK_K6_2:
2000     case CK_K6_3:
2001     case CK_Athlon:
2002     case CK_AthlonThunderbird:
2003     case CK_Athlon4:
2004     case CK_AthlonXP:
2005     case CK_AthlonMP:
2006     case CK_Geode:
2007       // Only accept certain architectures when compiling in 32-bit mode.
2008       if (getTriple().getArch() != llvm::Triple::x86)
2009         return false;
2010 
2011       // Fallthrough
2012     case CK_Nocona:
2013     case CK_Core2:
2014     case CK_Penryn:
2015     case CK_Atom:
2016     case CK_Corei7:
2017     case CK_Corei7AVX:
2018     case CK_CoreAVXi:
2019     case CK_CoreAVX2:
2020     case CK_Athlon64:
2021     case CK_Athlon64SSE3:
2022     case CK_AthlonFX:
2023     case CK_K8:
2024     case CK_K8SSE3:
2025     case CK_Opteron:
2026     case CK_OpteronSSE3:
2027     case CK_AMDFAM10:
2028     case CK_BTVER1:
2029     case CK_BTVER2:
2030     case CK_BDVER1:
2031     case CK_BDVER2:
2032     case CK_x86_64:
2033       return true;
2034     }
2035     llvm_unreachable("Unhandled CPU kind");
2036   }
2037 
2038   virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
2039     // We accept all non-ARM calling conventions
2040     return (CC == CC_X86ThisCall ||
2041             CC == CC_X86FastCall ||
2042             CC == CC_X86StdCall ||
2043             CC == CC_C ||
2044             CC == CC_X86Pascal ||
2045             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2046   }
2047 
2048   virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
2049     return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2050   }
2051 };
2052 
2053 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2054   // FIXME: This should not be here.
2055   Features["3dnow"] = false;
2056   Features["3dnowa"] = false;
2057   Features["mmx"] = false;
2058   Features["sse"] = false;
2059   Features["sse2"] = false;
2060   Features["sse3"] = false;
2061   Features["ssse3"] = false;
2062   Features["sse41"] = false;
2063   Features["sse42"] = false;
2064   Features["sse4a"] = false;
2065   Features["aes"] = false;
2066   Features["pclmul"] = false;
2067   Features["avx"] = false;
2068   Features["avx2"] = false;
2069   Features["lzcnt"] = false;
2070   Features["rdrand"] = false;
2071   Features["bmi"] = false;
2072   Features["bmi2"] = false;
2073   Features["popcnt"] = false;
2074   Features["rtm"] = false;
2075   Features["prfchw"] = false;
2076   Features["rdseed"] = false;
2077   Features["fma4"] = false;
2078   Features["fma"] = false;
2079   Features["xop"] = false;
2080   Features["f16c"] = false;
2081 
2082   // FIXME: This *really* should not be here.
2083 
2084   // X86_64 always has SSE2.
2085   if (getTriple().getArch() == llvm::Triple::x86_64)
2086     setFeatureEnabled(Features, "sse2", true);
2087 
2088   switch (CPU) {
2089   case CK_Generic:
2090   case CK_i386:
2091   case CK_i486:
2092   case CK_i586:
2093   case CK_Pentium:
2094   case CK_i686:
2095   case CK_PentiumPro:
2096     break;
2097   case CK_PentiumMMX:
2098   case CK_Pentium2:
2099     setFeatureEnabled(Features, "mmx", true);
2100     break;
2101   case CK_Pentium3:
2102   case CK_Pentium3M:
2103     setFeatureEnabled(Features, "sse", true);
2104     break;
2105   case CK_PentiumM:
2106   case CK_Pentium4:
2107   case CK_Pentium4M:
2108   case CK_x86_64:
2109     setFeatureEnabled(Features, "sse2", true);
2110     break;
2111   case CK_Yonah:
2112   case CK_Prescott:
2113   case CK_Nocona:
2114     setFeatureEnabled(Features, "sse3", true);
2115     break;
2116   case CK_Core2:
2117     setFeatureEnabled(Features, "ssse3", true);
2118     break;
2119   case CK_Penryn:
2120     setFeatureEnabled(Features, "sse4.1", true);
2121     break;
2122   case CK_Atom:
2123     setFeatureEnabled(Features, "ssse3", true);
2124     break;
2125   case CK_Corei7:
2126     setFeatureEnabled(Features, "sse4", true);
2127     break;
2128   case CK_Corei7AVX:
2129     setFeatureEnabled(Features, "avx", true);
2130     setFeatureEnabled(Features, "aes", true);
2131     setFeatureEnabled(Features, "pclmul", true);
2132     break;
2133   case CK_CoreAVXi:
2134     setFeatureEnabled(Features, "avx", true);
2135     setFeatureEnabled(Features, "aes", true);
2136     setFeatureEnabled(Features, "pclmul", true);
2137     setFeatureEnabled(Features, "rdrnd", true);
2138     setFeatureEnabled(Features, "f16c", true);
2139     break;
2140   case CK_CoreAVX2:
2141     setFeatureEnabled(Features, "avx2", true);
2142     setFeatureEnabled(Features, "aes", true);
2143     setFeatureEnabled(Features, "pclmul", true);
2144     setFeatureEnabled(Features, "lzcnt", true);
2145     setFeatureEnabled(Features, "rdrnd", true);
2146     setFeatureEnabled(Features, "f16c", true);
2147     setFeatureEnabled(Features, "bmi", true);
2148     setFeatureEnabled(Features, "bmi2", true);
2149     setFeatureEnabled(Features, "rtm", true);
2150     setFeatureEnabled(Features, "fma", true);
2151     break;
2152   case CK_K6:
2153   case CK_WinChipC6:
2154     setFeatureEnabled(Features, "mmx", true);
2155     break;
2156   case CK_K6_2:
2157   case CK_K6_3:
2158   case CK_WinChip2:
2159   case CK_C3:
2160     setFeatureEnabled(Features, "3dnow", true);
2161     break;
2162   case CK_Athlon:
2163   case CK_AthlonThunderbird:
2164   case CK_Geode:
2165     setFeatureEnabled(Features, "3dnowa", true);
2166     break;
2167   case CK_Athlon4:
2168   case CK_AthlonXP:
2169   case CK_AthlonMP:
2170     setFeatureEnabled(Features, "sse", true);
2171     setFeatureEnabled(Features, "3dnowa", true);
2172     break;
2173   case CK_K8:
2174   case CK_Opteron:
2175   case CK_Athlon64:
2176   case CK_AthlonFX:
2177     setFeatureEnabled(Features, "sse2", true);
2178     setFeatureEnabled(Features, "3dnowa", true);
2179     break;
2180   case CK_K8SSE3:
2181   case CK_OpteronSSE3:
2182   case CK_Athlon64SSE3:
2183     setFeatureEnabled(Features, "sse3", true);
2184     setFeatureEnabled(Features, "3dnowa", true);
2185     break;
2186   case CK_AMDFAM10:
2187     setFeatureEnabled(Features, "sse3", true);
2188     setFeatureEnabled(Features, "sse4a", true);
2189     setFeatureEnabled(Features, "3dnowa", true);
2190     setFeatureEnabled(Features, "lzcnt", true);
2191     setFeatureEnabled(Features, "popcnt", true);
2192     break;
2193   case CK_BTVER1:
2194     setFeatureEnabled(Features, "ssse3", true);
2195     setFeatureEnabled(Features, "sse4a", true);
2196     setFeatureEnabled(Features, "lzcnt", true);
2197     setFeatureEnabled(Features, "popcnt", true);
2198     break;
2199   case CK_BTVER2:
2200     setFeatureEnabled(Features, "avx", true);
2201     setFeatureEnabled(Features, "sse4a", true);
2202     setFeatureEnabled(Features, "lzcnt", true);
2203     setFeatureEnabled(Features, "aes", true);
2204     setFeatureEnabled(Features, "pclmul", true);
2205     setFeatureEnabled(Features, "bmi", true);
2206     setFeatureEnabled(Features, "f16c", true);
2207     break;
2208   case CK_BDVER1:
2209     setFeatureEnabled(Features, "xop", true);
2210     setFeatureEnabled(Features, "lzcnt", true);
2211     setFeatureEnabled(Features, "aes", true);
2212     setFeatureEnabled(Features, "pclmul", true);
2213     break;
2214   case CK_BDVER2:
2215     setFeatureEnabled(Features, "xop", true);
2216     setFeatureEnabled(Features, "lzcnt", true);
2217     setFeatureEnabled(Features, "aes", true);
2218     setFeatureEnabled(Features, "pclmul", true);
2219     setFeatureEnabled(Features, "bmi", true);
2220     setFeatureEnabled(Features, "fma", true);
2221     setFeatureEnabled(Features, "f16c", true);
2222     break;
2223   case CK_C3_2:
2224     setFeatureEnabled(Features, "sse", true);
2225     break;
2226   }
2227 }
2228 
2229 bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
2230                                       StringRef Name,
2231                                       bool Enabled) const {
2232   // FIXME: This *really* should not be here.  We need some way of translating
2233   // options into llvm subtarget features.
2234   if (!Features.count(Name) &&
2235       (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" &&
2236        Name != "rdrnd"))
2237     return false;
2238 
2239   // FIXME: this should probably use a switch with fall through.
2240 
2241   if (Enabled) {
2242     if (Name == "mmx")
2243       Features["mmx"] = true;
2244     else if (Name == "sse")
2245       Features["mmx"] = Features["sse"] = true;
2246     else if (Name == "sse2")
2247       Features["mmx"] = Features["sse"] = Features["sse2"] = true;
2248     else if (Name == "sse3")
2249       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2250         true;
2251     else if (Name == "ssse3")
2252       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2253         Features["ssse3"] = true;
2254     else if (Name == "sse4" || Name == "sse4.2")
2255       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2256         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2257         Features["popcnt"] = true;
2258     else if (Name == "sse4.1")
2259       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2260         Features["ssse3"] = Features["sse41"] = true;
2261     else if (Name == "3dnow")
2262       Features["mmx"] = Features["3dnow"] = true;
2263     else if (Name == "3dnowa")
2264       Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true;
2265     else if (Name == "aes")
2266       Features["sse"] = Features["sse2"] = Features["aes"] = true;
2267     else if (Name == "pclmul")
2268       Features["sse"] = Features["sse2"] = Features["pclmul"] = true;
2269     else if (Name == "avx")
2270       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2271         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2272         Features["popcnt"] = Features["avx"] = true;
2273     else if (Name == "avx2")
2274       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2275         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2276         Features["popcnt"] = Features["avx"] = Features["avx2"] = true;
2277     else if (Name == "fma")
2278       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2279         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2280         Features["popcnt"] = Features["avx"] = Features["fma"] = true;
2281     else if (Name == "fma4")
2282       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2283         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2284         Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2285         Features["fma4"] = true;
2286     else if (Name == "xop")
2287       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2288         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2289         Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2290         Features["fma4"] = Features["xop"] = true;
2291     else if (Name == "sse4a")
2292       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2293         Features["sse4a"] = true;
2294     else if (Name == "lzcnt")
2295       Features["lzcnt"] = true;
2296     else if (Name == "rdrnd")
2297       Features["rdrand"] = true;
2298     else if (Name == "bmi")
2299       Features["bmi"] = true;
2300     else if (Name == "bmi2")
2301       Features["bmi2"] = true;
2302     else if (Name == "popcnt")
2303       Features["popcnt"] = true;
2304     else if (Name == "f16c")
2305       Features["f16c"] = true;
2306     else if (Name == "rtm")
2307       Features["rtm"] = true;
2308     else if (Name == "prfchw")
2309       Features["prfchw"] = true;
2310     else if (Name == "rdseed")
2311       Features["rdseed"] = true;
2312   } else {
2313     if (Name == "mmx")
2314       Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false;
2315     else if (Name == "sse")
2316       Features["sse"] = Features["sse2"] = Features["sse3"] =
2317         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2318         Features["sse4a"] = Features["avx"] = Features["avx2"] =
2319         Features["fma"] = Features["fma4"] = Features["aes"] =
2320         Features["pclmul"] = Features["xop"] = false;
2321     else if (Name == "sse2")
2322       Features["sse2"] = Features["sse3"] = Features["ssse3"] =
2323         Features["sse41"] = Features["sse42"] = Features["sse4a"] =
2324         Features["avx"] = Features["avx2"] = Features["fma"] =
2325         Features["fma4"] = Features["aes"] = Features["pclmul"] =
2326         Features["xop"] = false;
2327     else if (Name == "sse3")
2328       Features["sse3"] = Features["ssse3"] = Features["sse41"] =
2329         Features["sse42"] = Features["sse4a"] = Features["avx"] =
2330         Features["avx2"] = Features["fma"] = Features["fma4"] =
2331         Features["xop"] = false;
2332     else if (Name == "ssse3")
2333       Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2334         Features["avx"] = Features["avx2"] = Features["fma"] = false;
2335     else if (Name == "sse4" || Name == "sse4.1")
2336       Features["sse41"] = Features["sse42"] = Features["avx"] =
2337         Features["avx2"] = Features["fma"] = false;
2338     else if (Name == "sse4.2")
2339       Features["sse42"] = Features["avx"] = Features["avx2"] =
2340         Features["fma"] = false;
2341     else if (Name == "3dnow")
2342       Features["3dnow"] = Features["3dnowa"] = false;
2343     else if (Name == "3dnowa")
2344       Features["3dnowa"] = false;
2345     else if (Name == "aes")
2346       Features["aes"] = false;
2347     else if (Name == "pclmul")
2348       Features["pclmul"] = false;
2349     else if (Name == "avx")
2350       Features["avx"] = Features["avx2"] = Features["fma"] =
2351         Features["fma4"] = Features["xop"] = false;
2352     else if (Name == "avx2")
2353       Features["avx2"] = false;
2354     else if (Name == "fma")
2355       Features["fma"] = false;
2356     else if (Name == "sse4a")
2357       Features["sse4a"] = Features["fma4"] = Features["xop"] = false;
2358     else if (Name == "lzcnt")
2359       Features["lzcnt"] = false;
2360     else if (Name == "rdrnd")
2361       Features["rdrand"] = false;
2362     else if (Name == "bmi")
2363       Features["bmi"] = false;
2364     else if (Name == "bmi2")
2365       Features["bmi2"] = false;
2366     else if (Name == "popcnt")
2367       Features["popcnt"] = false;
2368     else if (Name == "fma4")
2369       Features["fma4"] = Features["xop"] = false;
2370     else if (Name == "xop")
2371       Features["xop"] = false;
2372     else if (Name == "f16c")
2373       Features["f16c"] = false;
2374     else if (Name == "rtm")
2375       Features["rtm"] = false;
2376     else if (Name == "prfchw")
2377       Features["prfchw"] = false;
2378     else if (Name == "rdseed")
2379       Features["rdseed"] = false;
2380   }
2381 
2382   return true;
2383 }
2384 
2385 /// HandleTargetOptions - Perform initialization based on the user
2386 /// configured set of features.
2387 void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) {
2388   // Remember the maximum enabled sselevel.
2389   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2390     // Ignore disabled features.
2391     if (Features[i][0] == '-')
2392       continue;
2393 
2394     StringRef Feature = StringRef(Features[i]).substr(1);
2395 
2396     if (Feature == "aes") {
2397       HasAES = true;
2398       continue;
2399     }
2400 
2401     if (Feature == "pclmul") {
2402       HasPCLMUL = true;
2403       continue;
2404     }
2405 
2406     if (Feature == "lzcnt") {
2407       HasLZCNT = true;
2408       continue;
2409     }
2410 
2411     if (Feature == "rdrand") {
2412       HasRDRND = true;
2413       continue;
2414     }
2415 
2416     if (Feature == "bmi") {
2417       HasBMI = true;
2418       continue;
2419     }
2420 
2421     if (Feature == "bmi2") {
2422       HasBMI2 = true;
2423       continue;
2424     }
2425 
2426     if (Feature == "popcnt") {
2427       HasPOPCNT = true;
2428       continue;
2429     }
2430 
2431     if (Feature == "rtm") {
2432       HasRTM = true;
2433       continue;
2434     }
2435 
2436     if (Feature == "prfchw") {
2437       HasPRFCHW = true;
2438       continue;
2439     }
2440 
2441     if (Feature == "rdseed") {
2442       HasRDSEED = true;
2443       continue;
2444     }
2445 
2446     if (Feature == "sse4a") {
2447       HasSSE4a = true;
2448       continue;
2449     }
2450 
2451     if (Feature == "fma4") {
2452       HasFMA4 = true;
2453       continue;
2454     }
2455 
2456     if (Feature == "fma") {
2457       HasFMA = true;
2458       continue;
2459     }
2460 
2461     if (Feature == "xop") {
2462       HasXOP = true;
2463       continue;
2464     }
2465 
2466     if (Feature == "f16c") {
2467       HasF16C = true;
2468       continue;
2469     }
2470 
2471     assert(Features[i][0] == '+' && "Invalid target feature!");
2472     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2473       .Case("avx2", AVX2)
2474       .Case("avx", AVX)
2475       .Case("sse42", SSE42)
2476       .Case("sse41", SSE41)
2477       .Case("ssse3", SSSE3)
2478       .Case("sse3", SSE3)
2479       .Case("sse2", SSE2)
2480       .Case("sse", SSE1)
2481       .Default(NoSSE);
2482     SSELevel = std::max(SSELevel, Level);
2483 
2484     MMX3DNowEnum ThreeDNowLevel =
2485       llvm::StringSwitch<MMX3DNowEnum>(Feature)
2486         .Case("3dnowa", AMD3DNowAthlon)
2487         .Case("3dnow", AMD3DNow)
2488         .Case("mmx", MMX)
2489         .Default(NoMMX3DNow);
2490 
2491     MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2492   }
2493 
2494   // Don't tell the backend if we're turning off mmx; it will end up disabling
2495   // SSE, which we don't want.
2496   std::vector<std::string>::iterator it;
2497   it = std::find(Features.begin(), Features.end(), "-mmx");
2498   if (it != Features.end())
2499     Features.erase(it);
2500 }
2501 
2502 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2503 /// definitions for this particular subtarget.
2504 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2505                                      MacroBuilder &Builder) const {
2506   // Target identification.
2507   if (getTriple().getArch() == llvm::Triple::x86_64) {
2508     Builder.defineMacro("__amd64__");
2509     Builder.defineMacro("__amd64");
2510     Builder.defineMacro("__x86_64");
2511     Builder.defineMacro("__x86_64__");
2512   } else {
2513     DefineStd(Builder, "i386", Opts);
2514   }
2515 
2516   // Subtarget options.
2517   // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2518   // truly should be based on -mtune options.
2519   switch (CPU) {
2520   case CK_Generic:
2521     break;
2522   case CK_i386:
2523     // The rest are coming from the i386 define above.
2524     Builder.defineMacro("__tune_i386__");
2525     break;
2526   case CK_i486:
2527   case CK_WinChipC6:
2528   case CK_WinChip2:
2529   case CK_C3:
2530     defineCPUMacros(Builder, "i486");
2531     break;
2532   case CK_PentiumMMX:
2533     Builder.defineMacro("__pentium_mmx__");
2534     Builder.defineMacro("__tune_pentium_mmx__");
2535     // Fallthrough
2536   case CK_i586:
2537   case CK_Pentium:
2538     defineCPUMacros(Builder, "i586");
2539     defineCPUMacros(Builder, "pentium");
2540     break;
2541   case CK_Pentium3:
2542   case CK_Pentium3M:
2543   case CK_PentiumM:
2544     Builder.defineMacro("__tune_pentium3__");
2545     // Fallthrough
2546   case CK_Pentium2:
2547   case CK_C3_2:
2548     Builder.defineMacro("__tune_pentium2__");
2549     // Fallthrough
2550   case CK_PentiumPro:
2551     Builder.defineMacro("__tune_i686__");
2552     Builder.defineMacro("__tune_pentiumpro__");
2553     // Fallthrough
2554   case CK_i686:
2555     Builder.defineMacro("__i686");
2556     Builder.defineMacro("__i686__");
2557     // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2558     Builder.defineMacro("__pentiumpro");
2559     Builder.defineMacro("__pentiumpro__");
2560     break;
2561   case CK_Pentium4:
2562   case CK_Pentium4M:
2563     defineCPUMacros(Builder, "pentium4");
2564     break;
2565   case CK_Yonah:
2566   case CK_Prescott:
2567   case CK_Nocona:
2568     defineCPUMacros(Builder, "nocona");
2569     break;
2570   case CK_Core2:
2571   case CK_Penryn:
2572     defineCPUMacros(Builder, "core2");
2573     break;
2574   case CK_Atom:
2575     defineCPUMacros(Builder, "atom");
2576     break;
2577   case CK_Corei7:
2578   case CK_Corei7AVX:
2579   case CK_CoreAVXi:
2580   case CK_CoreAVX2:
2581     defineCPUMacros(Builder, "corei7");
2582     break;
2583   case CK_K6_2:
2584     Builder.defineMacro("__k6_2__");
2585     Builder.defineMacro("__tune_k6_2__");
2586     // Fallthrough
2587   case CK_K6_3:
2588     if (CPU != CK_K6_2) {  // In case of fallthrough
2589       // FIXME: GCC may be enabling these in cases where some other k6
2590       // architecture is specified but -m3dnow is explicitly provided. The
2591       // exact semantics need to be determined and emulated here.
2592       Builder.defineMacro("__k6_3__");
2593       Builder.defineMacro("__tune_k6_3__");
2594     }
2595     // Fallthrough
2596   case CK_K6:
2597     defineCPUMacros(Builder, "k6");
2598     break;
2599   case CK_Athlon:
2600   case CK_AthlonThunderbird:
2601   case CK_Athlon4:
2602   case CK_AthlonXP:
2603   case CK_AthlonMP:
2604     defineCPUMacros(Builder, "athlon");
2605     if (SSELevel != NoSSE) {
2606       Builder.defineMacro("__athlon_sse__");
2607       Builder.defineMacro("__tune_athlon_sse__");
2608     }
2609     break;
2610   case CK_K8:
2611   case CK_K8SSE3:
2612   case CK_x86_64:
2613   case CK_Opteron:
2614   case CK_OpteronSSE3:
2615   case CK_Athlon64:
2616   case CK_Athlon64SSE3:
2617   case CK_AthlonFX:
2618     defineCPUMacros(Builder, "k8");
2619     break;
2620   case CK_AMDFAM10:
2621     defineCPUMacros(Builder, "amdfam10");
2622     break;
2623   case CK_BTVER1:
2624     defineCPUMacros(Builder, "btver1");
2625     break;
2626   case CK_BTVER2:
2627     defineCPUMacros(Builder, "btver2");
2628     break;
2629   case CK_BDVER1:
2630     defineCPUMacros(Builder, "bdver1");
2631     break;
2632   case CK_BDVER2:
2633     defineCPUMacros(Builder, "bdver2");
2634     break;
2635   case CK_Geode:
2636     defineCPUMacros(Builder, "geode");
2637     break;
2638   }
2639 
2640   // Target properties.
2641   Builder.defineMacro("__LITTLE_ENDIAN__");
2642   Builder.defineMacro("__REGISTER_PREFIX__", "");
2643 
2644   // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2645   // functions in glibc header files that use FP Stack inline asm which the
2646   // backend can't deal with (PR879).
2647   Builder.defineMacro("__NO_MATH_INLINES");
2648 
2649   if (HasAES)
2650     Builder.defineMacro("__AES__");
2651 
2652   if (HasPCLMUL)
2653     Builder.defineMacro("__PCLMUL__");
2654 
2655   if (HasLZCNT)
2656     Builder.defineMacro("__LZCNT__");
2657 
2658   if (HasRDRND)
2659     Builder.defineMacro("__RDRND__");
2660 
2661   if (HasBMI)
2662     Builder.defineMacro("__BMI__");
2663 
2664   if (HasBMI2)
2665     Builder.defineMacro("__BMI2__");
2666 
2667   if (HasPOPCNT)
2668     Builder.defineMacro("__POPCNT__");
2669 
2670   if (HasRTM)
2671     Builder.defineMacro("__RTM__");
2672 
2673   if (HasPRFCHW)
2674     Builder.defineMacro("__PRFCHW__");
2675 
2676   if (HasRDSEED)
2677     Builder.defineMacro("__RDSEED__");
2678 
2679   if (HasSSE4a)
2680     Builder.defineMacro("__SSE4A__");
2681 
2682   if (HasFMA4)
2683     Builder.defineMacro("__FMA4__");
2684 
2685   if (HasFMA)
2686     Builder.defineMacro("__FMA__");
2687 
2688   if (HasXOP)
2689     Builder.defineMacro("__XOP__");
2690 
2691   if (HasF16C)
2692     Builder.defineMacro("__F16C__");
2693 
2694   // Each case falls through to the previous one here.
2695   switch (SSELevel) {
2696   case AVX2:
2697     Builder.defineMacro("__AVX2__");
2698   case AVX:
2699     Builder.defineMacro("__AVX__");
2700   case SSE42:
2701     Builder.defineMacro("__SSE4_2__");
2702   case SSE41:
2703     Builder.defineMacro("__SSE4_1__");
2704   case SSSE3:
2705     Builder.defineMacro("__SSSE3__");
2706   case SSE3:
2707     Builder.defineMacro("__SSE3__");
2708   case SSE2:
2709     Builder.defineMacro("__SSE2__");
2710     Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2711   case SSE1:
2712     Builder.defineMacro("__SSE__");
2713     Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2714   case NoSSE:
2715     break;
2716   }
2717 
2718   if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2719     switch (SSELevel) {
2720     case AVX2:
2721     case AVX:
2722     case SSE42:
2723     case SSE41:
2724     case SSSE3:
2725     case SSE3:
2726     case SSE2:
2727       Builder.defineMacro("_M_IX86_FP", Twine(2));
2728       break;
2729     case SSE1:
2730       Builder.defineMacro("_M_IX86_FP", Twine(1));
2731       break;
2732     default:
2733       Builder.defineMacro("_M_IX86_FP", Twine(0));
2734     }
2735   }
2736 
2737   // Each case falls through to the previous one here.
2738   switch (MMX3DNowLevel) {
2739   case AMD3DNowAthlon:
2740     Builder.defineMacro("__3dNOW_A__");
2741   case AMD3DNow:
2742     Builder.defineMacro("__3dNOW__");
2743   case MMX:
2744     Builder.defineMacro("__MMX__");
2745   case NoMMX3DNow:
2746     break;
2747   }
2748 
2749   if (CPU >= CK_i486) {
2750     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
2751     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
2752     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
2753   }
2754   if (CPU >= CK_i586)
2755     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
2756 }
2757 
2758 bool X86TargetInfo::hasFeature(StringRef Feature) const {
2759   return llvm::StringSwitch<bool>(Feature)
2760       .Case("aes", HasAES)
2761       .Case("avx", SSELevel >= AVX)
2762       .Case("avx2", SSELevel >= AVX2)
2763       .Case("bmi", HasBMI)
2764       .Case("bmi2", HasBMI2)
2765       .Case("fma", HasFMA)
2766       .Case("fma4", HasFMA4)
2767       .Case("lzcnt", HasLZCNT)
2768       .Case("rdrnd", HasRDRND)
2769       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2770       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2771       .Case("mmx", MMX3DNowLevel >= MMX)
2772       .Case("pclmul", HasPCLMUL)
2773       .Case("popcnt", HasPOPCNT)
2774       .Case("rtm", HasRTM)
2775       .Case("prfchw", HasPRFCHW)
2776       .Case("rdseed", HasRDSEED)
2777       .Case("sse", SSELevel >= SSE1)
2778       .Case("sse2", SSELevel >= SSE2)
2779       .Case("sse3", SSELevel >= SSE3)
2780       .Case("ssse3", SSELevel >= SSSE3)
2781       .Case("sse41", SSELevel >= SSE41)
2782       .Case("sse42", SSELevel >= SSE42)
2783       .Case("sse4a", HasSSE4a)
2784       .Case("x86", true)
2785       .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2786       .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2787       .Case("xop", HasXOP)
2788       .Case("f16c", HasF16C)
2789       .Default(false);
2790 }
2791 
2792 bool
2793 X86TargetInfo::validateAsmConstraint(const char *&Name,
2794                                      TargetInfo::ConstraintInfo &Info) const {
2795   switch (*Name) {
2796   default: return false;
2797   case 'Y': // first letter of a pair:
2798     switch (*(Name+1)) {
2799     default: return false;
2800     case '0':  // First SSE register.
2801     case 't':  // Any SSE register, when SSE2 is enabled.
2802     case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
2803     case 'm':  // any MMX register, when inter-unit moves enabled.
2804       break;   // falls through to setAllowsRegister.
2805   }
2806   case 'a': // eax.
2807   case 'b': // ebx.
2808   case 'c': // ecx.
2809   case 'd': // edx.
2810   case 'S': // esi.
2811   case 'D': // edi.
2812   case 'A': // edx:eax.
2813   case 'f': // any x87 floating point stack register.
2814   case 't': // top of floating point stack.
2815   case 'u': // second from top of floating point stack.
2816   case 'q': // Any register accessible as [r]l: a, b, c, and d.
2817   case 'y': // Any MMX register.
2818   case 'x': // Any SSE register.
2819   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2820   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2821   case 'l': // "Index" registers: any general register that can be used as an
2822             // index in a base+index memory access.
2823     Info.setAllowsRegister();
2824     return true;
2825   case 'C': // SSE floating point constant.
2826   case 'G': // x87 floating point constant.
2827   case 'e': // 32-bit signed integer constant for use with zero-extending
2828             // x86_64 instructions.
2829   case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2830             // x86_64 instructions.
2831     return true;
2832   }
2833 }
2834 
2835 
2836 std::string
2837 X86TargetInfo::convertConstraint(const char *&Constraint) const {
2838   switch (*Constraint) {
2839   case 'a': return std::string("{ax}");
2840   case 'b': return std::string("{bx}");
2841   case 'c': return std::string("{cx}");
2842   case 'd': return std::string("{dx}");
2843   case 'S': return std::string("{si}");
2844   case 'D': return std::string("{di}");
2845   case 'p': // address
2846     return std::string("im");
2847   case 't': // top of floating point stack.
2848     return std::string("{st}");
2849   case 'u': // second from top of floating point stack.
2850     return std::string("{st(1)}"); // second from top of floating point stack.
2851   default:
2852     return std::string(1, *Constraint);
2853   }
2854 }
2855 } // end anonymous namespace
2856 
2857 namespace {
2858 // X86-32 generic target
2859 class X86_32TargetInfo : public X86TargetInfo {
2860 public:
2861   X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) {
2862     DoubleAlign = LongLongAlign = 32;
2863     LongDoubleWidth = 96;
2864     LongDoubleAlign = 32;
2865     SuitableAlign = 128;
2866     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2867                         "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2868                         "a0:0:64-f80:32:32-n8:16:32-S128";
2869     SizeType = UnsignedInt;
2870     PtrDiffType = SignedInt;
2871     IntPtrType = SignedInt;
2872     RegParmMax = 3;
2873 
2874     // Use fpret for all types.
2875     RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2876                              (1 << TargetInfo::Double) |
2877                              (1 << TargetInfo::LongDouble));
2878 
2879     // x86-32 has atomics up to 8 bytes
2880     // FIXME: Check that we actually have cmpxchg8b before setting
2881     // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2882     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2883   }
2884   virtual BuiltinVaListKind getBuiltinVaListKind() const {
2885     return TargetInfo::CharPtrBuiltinVaList;
2886   }
2887 
2888   int getEHDataRegisterNumber(unsigned RegNo) const {
2889     if (RegNo == 0) return 0;
2890     if (RegNo == 1) return 2;
2891     return -1;
2892   }
2893   virtual bool validateInputSize(StringRef Constraint,
2894                                  unsigned Size) const {
2895     switch (Constraint[0]) {
2896     default: break;
2897     case 'a':
2898     case 'b':
2899     case 'c':
2900     case 'd':
2901       return Size <= 32;
2902     }
2903 
2904     return true;
2905   }
2906 };
2907 } // end anonymous namespace
2908 
2909 namespace {
2910 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2911 public:
2912   NetBSDI386TargetInfo(const std::string &triple) :
2913     NetBSDTargetInfo<X86_32TargetInfo>(triple) {
2914   }
2915 
2916   virtual unsigned getFloatEvalMethod() const {
2917     // NetBSD defaults to "double" rounding
2918     return 1;
2919   }
2920 };
2921 } // end anonymous namespace
2922 
2923 namespace {
2924 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
2925 public:
2926   OpenBSDI386TargetInfo(const std::string& triple) :
2927     OpenBSDTargetInfo<X86_32TargetInfo>(triple) {
2928     SizeType = UnsignedLong;
2929     IntPtrType = SignedLong;
2930     PtrDiffType = SignedLong;
2931   }
2932 };
2933 } // end anonymous namespace
2934 
2935 namespace {
2936 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
2937 public:
2938   BitrigI386TargetInfo(const std::string& triple) :
2939     BitrigTargetInfo<X86_32TargetInfo>(triple) {
2940     SizeType = UnsignedLong;
2941     IntPtrType = SignedLong;
2942     PtrDiffType = SignedLong;
2943   }
2944 };
2945 } // end anonymous namespace
2946 
2947 namespace {
2948 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
2949 public:
2950   DarwinI386TargetInfo(const std::string& triple) :
2951     DarwinTargetInfo<X86_32TargetInfo>(triple) {
2952     LongDoubleWidth = 128;
2953     LongDoubleAlign = 128;
2954     SuitableAlign = 128;
2955     MaxVectorAlign = 256;
2956     SizeType = UnsignedLong;
2957     IntPtrType = SignedLong;
2958     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2959                         "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2960                         "a0:0:64-f80:128:128-n8:16:32-S128";
2961     HasAlignMac68kSupport = true;
2962   }
2963 
2964 };
2965 } // end anonymous namespace
2966 
2967 namespace {
2968 // x86-32 Windows target
2969 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
2970 public:
2971   WindowsX86_32TargetInfo(const std::string& triple)
2972     : WindowsTargetInfo<X86_32TargetInfo>(triple) {
2973     TLSSupported = false;
2974     WCharType = UnsignedShort;
2975     DoubleAlign = LongLongAlign = 64;
2976     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2977                         "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
2978                         "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
2979   }
2980   virtual void getTargetDefines(const LangOptions &Opts,
2981                                 MacroBuilder &Builder) const {
2982     WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
2983   }
2984 };
2985 } // end anonymous namespace
2986 
2987 namespace {
2988 
2989 // x86-32 Windows Visual Studio target
2990 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
2991 public:
2992   VisualStudioWindowsX86_32TargetInfo(const std::string& triple)
2993     : WindowsX86_32TargetInfo(triple) {
2994     LongDoubleWidth = LongDoubleAlign = 64;
2995     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
2996   }
2997   virtual void getTargetDefines(const LangOptions &Opts,
2998                                 MacroBuilder &Builder) const {
2999     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3000     WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3001     // The value of the following reflects processor type.
3002     // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3003     // We lost the original triple, so we use the default.
3004     Builder.defineMacro("_M_IX86", "600");
3005   }
3006 };
3007 } // end anonymous namespace
3008 
3009 namespace {
3010 // x86-32 MinGW target
3011 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3012 public:
3013   MinGWX86_32TargetInfo(const std::string& triple)
3014     : WindowsX86_32TargetInfo(triple) {
3015   }
3016   virtual void getTargetDefines(const LangOptions &Opts,
3017                                 MacroBuilder &Builder) const {
3018     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3019     DefineStd(Builder, "WIN32", Opts);
3020     DefineStd(Builder, "WINNT", Opts);
3021     Builder.defineMacro("_X86_");
3022     Builder.defineMacro("__MSVCRT__");
3023     Builder.defineMacro("__MINGW32__");
3024 
3025     // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3026     // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3027     if (Opts.MicrosoftExt)
3028       // Provide "as-is" __declspec.
3029       Builder.defineMacro("__declspec", "__declspec");
3030     else
3031       // Provide alias of __attribute__ like mingw32-gcc.
3032       Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3033   }
3034 };
3035 } // end anonymous namespace
3036 
3037 namespace {
3038 // x86-32 Cygwin target
3039 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3040 public:
3041   CygwinX86_32TargetInfo(const std::string& triple)
3042     : X86_32TargetInfo(triple) {
3043     TLSSupported = false;
3044     WCharType = UnsignedShort;
3045     DoubleAlign = LongLongAlign = 64;
3046     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3047                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3048                         "a0:0:64-f80:32:32-n8:16:32-S32";
3049   }
3050   virtual void getTargetDefines(const LangOptions &Opts,
3051                                 MacroBuilder &Builder) const {
3052     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3053     Builder.defineMacro("_X86_");
3054     Builder.defineMacro("__CYGWIN__");
3055     Builder.defineMacro("__CYGWIN32__");
3056     DefineStd(Builder, "unix", Opts);
3057     if (Opts.CPlusPlus)
3058       Builder.defineMacro("_GNU_SOURCE");
3059   }
3060 };
3061 } // end anonymous namespace
3062 
3063 namespace {
3064 // x86-32 Haiku target
3065 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3066 public:
3067   HaikuX86_32TargetInfo(const std::string& triple)
3068     : X86_32TargetInfo(triple) {
3069     SizeType = UnsignedLong;
3070     IntPtrType = SignedLong;
3071     PtrDiffType = SignedLong;
3072     ProcessIDType = SignedLong;
3073     this->UserLabelPrefix = "";
3074     this->TLSSupported = false;
3075   }
3076   virtual void getTargetDefines(const LangOptions &Opts,
3077                                 MacroBuilder &Builder) const {
3078     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3079     Builder.defineMacro("__INTEL__");
3080     Builder.defineMacro("__HAIKU__");
3081   }
3082 };
3083 } // end anonymous namespace
3084 
3085 // RTEMS Target
3086 template<typename Target>
3087 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3088 protected:
3089   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3090                             MacroBuilder &Builder) const {
3091     // RTEMS defines; list based off of gcc output
3092 
3093     Builder.defineMacro("__rtems__");
3094     Builder.defineMacro("__ELF__");
3095   }
3096 public:
3097   RTEMSTargetInfo(const std::string &triple)
3098     : OSTargetInfo<Target>(triple) {
3099       this->UserLabelPrefix = "";
3100 
3101       llvm::Triple Triple(triple);
3102       switch (Triple.getArch()) {
3103         default:
3104         case llvm::Triple::x86:
3105           // this->MCountName = ".mcount";
3106           break;
3107         case llvm::Triple::mips:
3108         case llvm::Triple::mipsel:
3109         case llvm::Triple::ppc:
3110         case llvm::Triple::ppc64:
3111           // this->MCountName = "_mcount";
3112           break;
3113         case llvm::Triple::arm:
3114           // this->MCountName = "__mcount";
3115           break;
3116       }
3117 
3118     }
3119 };
3120 
3121 namespace {
3122 // x86-32 RTEMS target
3123 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3124 public:
3125   RTEMSX86_32TargetInfo(const std::string& triple)
3126     : X86_32TargetInfo(triple) {
3127     SizeType = UnsignedLong;
3128     IntPtrType = SignedLong;
3129     PtrDiffType = SignedLong;
3130     this->UserLabelPrefix = "";
3131   }
3132   virtual void getTargetDefines(const LangOptions &Opts,
3133                                 MacroBuilder &Builder) const {
3134     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3135     Builder.defineMacro("__INTEL__");
3136     Builder.defineMacro("__rtems__");
3137   }
3138 };
3139 } // end anonymous namespace
3140 
3141 namespace {
3142 // x86-64 generic target
3143 class X86_64TargetInfo : public X86TargetInfo {
3144 public:
3145   X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) {
3146     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
3147     LongDoubleWidth = 128;
3148     LongDoubleAlign = 128;
3149     LargeArrayMinWidth = 128;
3150     LargeArrayAlign = 128;
3151     SuitableAlign = 128;
3152     IntMaxType = SignedLong;
3153     UIntMaxType = UnsignedLong;
3154     Int64Type = SignedLong;
3155     RegParmMax = 6;
3156 
3157     DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3158                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3159                         "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
3160 
3161     // Use fpret only for long double.
3162     RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3163 
3164     // Use fp2ret for _Complex long double.
3165     ComplexLongDoubleUsesFP2Ret = true;
3166 
3167     // x86-64 has atomics up to 16 bytes.
3168     // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
3169     // on CPUs with cmpxchg16b
3170     MaxAtomicPromoteWidth = 128;
3171     MaxAtomicInlineWidth = 64;
3172   }
3173   virtual BuiltinVaListKind getBuiltinVaListKind() const {
3174     return TargetInfo::X86_64ABIBuiltinVaList;
3175   }
3176 
3177   int getEHDataRegisterNumber(unsigned RegNo) const {
3178     if (RegNo == 0) return 0;
3179     if (RegNo == 1) return 1;
3180     return -1;
3181   }
3182 
3183   virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3184     return (CC == CC_Default ||
3185             CC == CC_C ||
3186             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
3187   }
3188 
3189   virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
3190     return CC_C;
3191   }
3192 
3193 };
3194 } // end anonymous namespace
3195 
3196 namespace {
3197 // x86-64 Windows target
3198 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3199 public:
3200   WindowsX86_64TargetInfo(const std::string& triple)
3201     : WindowsTargetInfo<X86_64TargetInfo>(triple) {
3202     TLSSupported = false;
3203     WCharType = UnsignedShort;
3204     LongWidth = LongAlign = 32;
3205     DoubleAlign = LongLongAlign = 64;
3206     IntMaxType = SignedLongLong;
3207     UIntMaxType = UnsignedLongLong;
3208     Int64Type = SignedLongLong;
3209     SizeType = UnsignedLongLong;
3210     PtrDiffType = SignedLongLong;
3211     IntPtrType = SignedLongLong;
3212     this->UserLabelPrefix = "";
3213   }
3214   virtual void getTargetDefines(const LangOptions &Opts,
3215                                 MacroBuilder &Builder) const {
3216     WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3217     Builder.defineMacro("_WIN64");
3218   }
3219   virtual BuiltinVaListKind getBuiltinVaListKind() const {
3220     return TargetInfo::CharPtrBuiltinVaList;
3221   }
3222 };
3223 } // end anonymous namespace
3224 
3225 namespace {
3226 // x86-64 Windows Visual Studio target
3227 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
3228 public:
3229   VisualStudioWindowsX86_64TargetInfo(const std::string& triple)
3230     : WindowsX86_64TargetInfo(triple) {
3231     LongDoubleWidth = LongDoubleAlign = 64;
3232     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3233   }
3234   virtual void getTargetDefines(const LangOptions &Opts,
3235                                 MacroBuilder &Builder) const {
3236     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3237     WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3238     Builder.defineMacro("_M_X64");
3239     Builder.defineMacro("_M_AMD64");
3240   }
3241 };
3242 } // end anonymous namespace
3243 
3244 namespace {
3245 // x86-64 MinGW target
3246 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3247 public:
3248   MinGWX86_64TargetInfo(const std::string& triple)
3249     : WindowsX86_64TargetInfo(triple) {
3250   }
3251   virtual void getTargetDefines(const LangOptions &Opts,
3252                                 MacroBuilder &Builder) const {
3253     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3254     DefineStd(Builder, "WIN64", Opts);
3255     Builder.defineMacro("__MSVCRT__");
3256     Builder.defineMacro("__MINGW32__");
3257     Builder.defineMacro("__MINGW64__");
3258 
3259     // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3260     // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3261     if (Opts.MicrosoftExt)
3262       // Provide "as-is" __declspec.
3263       Builder.defineMacro("__declspec", "__declspec");
3264     else
3265       // Provide alias of __attribute__ like mingw32-gcc.
3266       Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3267   }
3268 };
3269 } // end anonymous namespace
3270 
3271 namespace {
3272 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3273 public:
3274   DarwinX86_64TargetInfo(const std::string& triple)
3275       : DarwinTargetInfo<X86_64TargetInfo>(triple) {
3276     Int64Type = SignedLongLong;
3277     MaxVectorAlign = 256;
3278   }
3279 };
3280 } // end anonymous namespace
3281 
3282 namespace {
3283 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3284 public:
3285   OpenBSDX86_64TargetInfo(const std::string& triple)
3286       : OpenBSDTargetInfo<X86_64TargetInfo>(triple) {
3287     IntMaxType = SignedLongLong;
3288     UIntMaxType = UnsignedLongLong;
3289     Int64Type = SignedLongLong;
3290   }
3291 };
3292 } // end anonymous namespace
3293 
3294 namespace {
3295 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3296 public:
3297   BitrigX86_64TargetInfo(const std::string& triple)
3298       : BitrigTargetInfo<X86_64TargetInfo>(triple) {
3299      IntMaxType = SignedLongLong;
3300      UIntMaxType = UnsignedLongLong;
3301      Int64Type = SignedLongLong;
3302   }
3303 };
3304 }
3305 
3306 namespace {
3307 class AArch64TargetInfo : public TargetInfo {
3308   static const char * const GCCRegNames[];
3309   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3310 
3311   static const Builtin::Info BuiltinInfo[];
3312 public:
3313   AArch64TargetInfo(const std::string& triple) : TargetInfo(triple) {
3314     BigEndian = false;
3315     LongWidth = LongAlign = 64;
3316     LongDoubleWidth = LongDoubleAlign = 128;
3317     PointerWidth = PointerAlign = 64;
3318     SuitableAlign = 128;
3319     DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3320                         "i64:64:64-i128:128:128-f32:32:32-f64:64:64-"
3321                         "f128:128:128-n32:64-S128";
3322 
3323     WCharType = UnsignedInt;
3324     LongDoubleFormat = &llvm::APFloat::IEEEquad;
3325 
3326     // AArch64 backend supports 64-bit operations at the moment. In principle
3327     // 128-bit is possible if register-pairs are used.
3328     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3329 
3330     TheCXXABI.set(TargetCXXABI::GenericAArch64);
3331   }
3332   virtual void getTargetDefines(const LangOptions &Opts,
3333                                 MacroBuilder &Builder) const {
3334     // GCC defines theses currently
3335     Builder.defineMacro("__aarch64__");
3336     Builder.defineMacro("__AARCH64EL__");
3337 
3338     // ACLE predefines. Many can only have one possible value on v8 AArch64.
3339 
3340     // FIXME: these were written based on an unreleased version of a 32-bit ACLE
3341     // which was intended to be compatible with a 64-bit implementation. They
3342     // will need updating when a real 64-bit ACLE exists. Particularly pressing
3343     // instances are: __ARM_ARCH_ISA_ARM, __ARM_ARCH_ISA_THUMB, __ARM_PCS.
3344     Builder.defineMacro("__ARM_ACLE",         "101");
3345     Builder.defineMacro("__ARM_ARCH",         "8");
3346     Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
3347 
3348     Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
3349     Builder.defineMacro("__ARM_FEATURE_CLZ");
3350     Builder.defineMacro("__ARM_FEATURE_FMA");
3351 
3352     // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean
3353     // 128-bit LDXP present, at which point this becomes 0x1f.
3354     Builder.defineMacro("__ARM_FEATURE_LDREX", "0xf");
3355 
3356     // 0xe implies support for half, single and double precision operations.
3357     Builder.defineMacro("__ARM_FP", "0xe");
3358 
3359     // PCS specifies this for SysV variants, which is all we support. Other ABIs
3360     // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
3361     Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
3362 
3363     if (Opts.FastMath || Opts.FiniteMathOnly)
3364       Builder.defineMacro("__ARM_FP_FAST");
3365 
3366     if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
3367       Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
3368 
3369     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
3370                         Opts.ShortWChar ? "2" : "4");
3371 
3372     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
3373                         Opts.ShortEnums ? "1" : "4");
3374 
3375     if (BigEndian)
3376       Builder.defineMacro("__ARM_BIG_ENDIAN");
3377   }
3378   virtual void getTargetBuiltins(const Builtin::Info *&Records,
3379                                  unsigned &NumRecords) const {
3380     Records = BuiltinInfo;
3381     NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin;
3382   }
3383   virtual bool hasFeature(StringRef Feature) const {
3384     return Feature == "aarch64";
3385   }
3386   virtual void getGCCRegNames(const char * const *&Names,
3387                               unsigned &NumNames) const;
3388   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3389                                 unsigned &NumAliases) const;
3390 
3391   virtual bool isCLZForZeroUndef() const { return false; }
3392 
3393   virtual bool validateAsmConstraint(const char *&Name,
3394                                      TargetInfo::ConstraintInfo &Info) const {
3395     switch (*Name) {
3396     default: return false;
3397     case 'w': // An FP/SIMD vector register
3398       Info.setAllowsRegister();
3399       return true;
3400     case 'I': // Constant that can be used with an ADD instruction
3401     case 'J': // Constant that can be used with a SUB instruction
3402     case 'K': // Constant that can be used with a 32-bit logical instruction
3403     case 'L': // Constant that can be used with a 64-bit logical instruction
3404     case 'M': // Constant that can be used as a 32-bit MOV immediate
3405     case 'N': // Constant that can be used as a 64-bit MOV immediate
3406     case 'Y': // Floating point constant zero
3407     case 'Z': // Integer constant zero
3408       return true;
3409     case 'Q': // A memory reference with base register and no offset
3410       Info.setAllowsMemory();
3411       return true;
3412     case 'S': // A symbolic address
3413       Info.setAllowsRegister();
3414       return true;
3415     case 'U':
3416       // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
3417       // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
3418       // Usa: An absolute symbolic address
3419       // Ush: The high part (bits 32:12) of a pc-relative symbolic address
3420       llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
3421     }
3422   }
3423 
3424   virtual const char *getClobbers() const {
3425     // There are no AArch64 clobbers shared by all asm statements.
3426     return "";
3427   }
3428 
3429   virtual BuiltinVaListKind getBuiltinVaListKind() const {
3430     return TargetInfo::AArch64ABIBuiltinVaList;
3431   }
3432 };
3433 
3434 const char * const AArch64TargetInfo::GCCRegNames[] = {
3435   "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3436   "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3437   "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3438   "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
3439 
3440   "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
3441   "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3442   "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
3443   "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
3444 
3445   "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
3446   "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
3447   "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
3448   "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
3449 
3450   "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
3451   "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
3452   "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
3453   "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
3454 
3455   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3456   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3457   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3458   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3459 
3460   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3461   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3462   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3463   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3464 
3465   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3466   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3467   "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
3468   "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
3469 };
3470 
3471 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
3472                                        unsigned &NumNames) const {
3473   Names = GCCRegNames;
3474   NumNames = llvm::array_lengthof(GCCRegNames);
3475 }
3476 
3477 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
3478   { { "x16" }, "ip0"},
3479   { { "x17" }, "ip1"},
3480   { { "x29" }, "fp" },
3481   { { "x30" }, "lr" }
3482 };
3483 
3484 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3485                                          unsigned &NumAliases) const {
3486   Aliases = GCCRegAliases;
3487   NumAliases = llvm::array_lengthof(GCCRegAliases);
3488 
3489 }
3490 
3491 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
3492 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3493 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3494                                               ALL_LANGUAGES },
3495 #include "clang/Basic/BuiltinsAArch64.def"
3496 };
3497 
3498 } // end anonymous namespace
3499 
3500 namespace {
3501 class ARMTargetInfo : public TargetInfo {
3502   // Possible FPU choices.
3503   enum FPUMode {
3504     VFP2FPU = (1 << 0),
3505     VFP3FPU = (1 << 1),
3506     VFP4FPU = (1 << 2),
3507     NeonFPU = (1 << 3)
3508   };
3509 
3510   static bool FPUModeIsVFP(FPUMode Mode) {
3511     return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU);
3512   }
3513 
3514   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3515   static const char * const GCCRegNames[];
3516 
3517   std::string ABI, CPU;
3518 
3519   unsigned FPU : 4;
3520 
3521   unsigned IsAAPCS : 1;
3522   unsigned IsThumb : 1;
3523 
3524   // Initialized via features.
3525   unsigned SoftFloat : 1;
3526   unsigned SoftFloatABI : 1;
3527 
3528   static const Builtin::Info BuiltinInfo[];
3529 
3530 public:
3531   ARMTargetInfo(const std::string &TripleStr)
3532     : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s"), IsAAPCS(true)
3533   {
3534     BigEndian = false;
3535     SizeType = UnsignedInt;
3536     PtrDiffType = SignedInt;
3537     // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3538     WCharType = UnsignedInt;
3539 
3540     // {} in inline assembly are neon specifiers, not assembly variant
3541     // specifiers.
3542     NoAsmVariants = true;
3543 
3544     // FIXME: Should we just treat this as a feature?
3545     IsThumb = getTriple().getArchName().startswith("thumb");
3546     if (IsThumb) {
3547       // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3548       // so set preferred for small types to 32.
3549       DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3550                            "i64:64:64-f32:32:32-f64:64:64-"
3551                            "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3552     } else {
3553       DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3554                            "i64:64:64-f32:32:32-f64:64:64-"
3555                            "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3556     }
3557 
3558     // ARM targets default to using the ARM C++ ABI.
3559     TheCXXABI.set(TargetCXXABI::GenericARM);
3560 
3561     // ARM has atomics up to 8 bytes
3562     // FIXME: Set MaxAtomicInlineWidth if we have the feature v6e
3563     MaxAtomicPromoteWidth = 64;
3564 
3565     // Do force alignment of members that follow zero length bitfields.  If
3566     // the alignment of the zero-length bitfield is greater than the member
3567     // that follows it, `bar', `bar' will be aligned as the  type of the
3568     // zero length bitfield.
3569     UseZeroLengthBitfieldAlignment = true;
3570   }
3571   virtual const char *getABI() const { return ABI.c_str(); }
3572   virtual bool setABI(const std::string &Name) {
3573     ABI = Name;
3574 
3575     // The defaults (above) are for AAPCS, check if we need to change them.
3576     //
3577     // FIXME: We need support for -meabi... we could just mangle it into the
3578     // name.
3579     if (Name == "apcs-gnu") {
3580       DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3581       // size_t is unsigned int on FreeBSD.
3582       if (getTriple().getOS() != llvm::Triple::FreeBSD)
3583         SizeType = UnsignedLong;
3584 
3585       // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3586       WCharType = SignedInt;
3587 
3588       // Do not respect the alignment of bit-field types when laying out
3589       // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3590       UseBitFieldTypeAlignment = false;
3591 
3592       /// gcc forces the alignment to 4 bytes, regardless of the type of the
3593       /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3594       /// gcc.
3595       ZeroLengthBitfieldBoundary = 32;
3596 
3597       IsAAPCS = false;
3598 
3599       if (IsThumb) {
3600         // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3601         // so set preferred for small types to 32.
3602         DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3603                              "i64:32:64-f32:32:32-f64:32:64-"
3604                              "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3605       } else {
3606         DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3607                              "i64:32:64-f32:32:32-f64:32:64-"
3608                              "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3609       }
3610 
3611       // FIXME: Override "preferred align" for double and long long.
3612     } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3613       IsAAPCS = true;
3614       // FIXME: Enumerated types are variable width in straight AAPCS.
3615     } else if (Name == "aapcs-linux") {
3616       IsAAPCS = true;
3617     } else
3618       return false;
3619 
3620     return true;
3621   }
3622 
3623   void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3624     if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3625       Features["vfp2"] = true;
3626     else if (CPU == "cortex-a8" || CPU == "cortex-a15" ||
3627              CPU == "cortex-a9" || CPU == "cortex-a9-mp")
3628       Features["neon"] = true;
3629     else if (CPU == "swift" || CPU == "cortex-a7") {
3630       Features["vfp4"] = true;
3631       Features["neon"] = true;
3632     }
3633   }
3634 
3635   virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3636                                  StringRef Name,
3637                                  bool Enabled) const {
3638     if (Name == "soft-float" || Name == "soft-float-abi" ||
3639         Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" ||
3640         Name == "d16" || Name == "neonfp") {
3641       Features[Name] = Enabled;
3642     } else
3643       return false;
3644 
3645     return true;
3646   }
3647 
3648   virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3649     FPU = 0;
3650     SoftFloat = SoftFloatABI = false;
3651     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3652       if (Features[i] == "+soft-float")
3653         SoftFloat = true;
3654       else if (Features[i] == "+soft-float-abi")
3655         SoftFloatABI = true;
3656       else if (Features[i] == "+vfp2")
3657         FPU |= VFP2FPU;
3658       else if (Features[i] == "+vfp3")
3659         FPU |= VFP3FPU;
3660       else if (Features[i] == "+vfp4")
3661         FPU |= VFP4FPU;
3662       else if (Features[i] == "+neon")
3663         FPU |= NeonFPU;
3664     }
3665 
3666     // Remove front-end specific options which the backend handles differently.
3667     std::vector<std::string>::iterator it;
3668     it = std::find(Features.begin(), Features.end(), "+soft-float");
3669     if (it != Features.end())
3670       Features.erase(it);
3671     it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3672     if (it != Features.end())
3673       Features.erase(it);
3674   }
3675 
3676   virtual bool hasFeature(StringRef Feature) const {
3677     return llvm::StringSwitch<bool>(Feature)
3678         .Case("arm", true)
3679         .Case("softfloat", SoftFloat)
3680         .Case("thumb", IsThumb)
3681         .Case("neon", FPU == NeonFPU && !SoftFloat &&
3682               StringRef(getCPUDefineSuffix(CPU)).startswith("7"))
3683         .Default(false);
3684   }
3685   // FIXME: Should we actually have some table instead of these switches?
3686   static const char *getCPUDefineSuffix(StringRef Name) {
3687     return llvm::StringSwitch<const char*>(Name)
3688       .Cases("arm8", "arm810", "4")
3689       .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3690       .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3691       .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3692       .Case("ep9312", "4T")
3693       .Cases("arm10tdmi", "arm1020t", "5T")
3694       .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3695       .Case("arm926ej-s", "5TEJ")
3696       .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3697       .Cases("xscale", "iwmmxt", "5TE")
3698       .Case("arm1136j-s", "6J")
3699       .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3700       .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3701       .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3702       .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
3703       .Cases("cortex-a9", "cortex-a15", "7A")
3704       .Case("cortex-r5", "7R")
3705       .Case("cortex-a9-mp", "7F")
3706       .Case("swift", "7S")
3707       .Cases("cortex-m3", "cortex-m4", "7M")
3708       .Case("cortex-m0", "6M")
3709       .Default(0);
3710   }
3711   static const char *getCPUProfile(StringRef Name) {
3712     return llvm::StringSwitch<const char*>(Name)
3713       .Cases("cortex-a8", "cortex-a9", "A")
3714       .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3715       .Case("cortex-r5", "R")
3716       .Default("");
3717   }
3718   virtual bool setCPU(const std::string &Name) {
3719     if (!getCPUDefineSuffix(Name))
3720       return false;
3721 
3722     CPU = Name;
3723     return true;
3724   }
3725   virtual void getTargetDefines(const LangOptions &Opts,
3726                                 MacroBuilder &Builder) const {
3727     // Target identification.
3728     Builder.defineMacro("__arm");
3729     Builder.defineMacro("__arm__");
3730 
3731     // Target properties.
3732     Builder.defineMacro("__ARMEL__");
3733     Builder.defineMacro("__LITTLE_ENDIAN__");
3734     Builder.defineMacro("__REGISTER_PREFIX__", "");
3735 
3736     StringRef CPUArch = getCPUDefineSuffix(CPU);
3737     Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3738     Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3739     StringRef CPUProfile = getCPUProfile(CPU);
3740     if (!CPUProfile.empty())
3741       Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3742 
3743     // Subtarget options.
3744 
3745     // FIXME: It's more complicated than this and we don't really support
3746     // interworking.
3747     if ('5' <= CPUArch[0] && CPUArch[0] <= '7')
3748       Builder.defineMacro("__THUMB_INTERWORK__");
3749 
3750     if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3751       // M-class CPUs on Darwin follow AAPCS, but not EABI.
3752       if (!(getTriple().isOSDarwin() && CPUProfile == "M"))
3753         Builder.defineMacro("__ARM_EABI__");
3754       Builder.defineMacro("__ARM_PCS", "1");
3755 
3756       if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3757         Builder.defineMacro("__ARM_PCS_VFP", "1");
3758     }
3759 
3760     if (SoftFloat)
3761       Builder.defineMacro("__SOFTFP__");
3762 
3763     if (CPU == "xscale")
3764       Builder.defineMacro("__XSCALE__");
3765 
3766     bool IsARMv7 = CPUArch.startswith("7");
3767     if (IsThumb) {
3768       Builder.defineMacro("__THUMBEL__");
3769       Builder.defineMacro("__thumb__");
3770       if (CPUArch == "6T2" || IsARMv7)
3771         Builder.defineMacro("__thumb2__");
3772     }
3773 
3774     // Note, this is always on in gcc, even though it doesn't make sense.
3775     Builder.defineMacro("__APCS_32__");
3776 
3777     if (FPUModeIsVFP((FPUMode) FPU)) {
3778       Builder.defineMacro("__VFP_FP__");
3779       if (FPU & VFP2FPU)
3780         Builder.defineMacro("__ARM_VFPV2__");
3781       if (FPU & VFP3FPU)
3782         Builder.defineMacro("__ARM_VFPV3__");
3783       if (FPU & VFP4FPU)
3784         Builder.defineMacro("__ARM_VFPV4__");
3785     }
3786 
3787     // This only gets set when Neon instructions are actually available, unlike
3788     // the VFP define, hence the soft float and arch check. This is subtly
3789     // different from gcc, we follow the intent which was that it should be set
3790     // when Neon instructions are actually available.
3791     if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
3792       Builder.defineMacro("__ARM_NEON__");
3793   }
3794   virtual void getTargetBuiltins(const Builtin::Info *&Records,
3795                                  unsigned &NumRecords) const {
3796     Records = BuiltinInfo;
3797     NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
3798   }
3799   virtual bool isCLZForZeroUndef() const { return false; }
3800   virtual BuiltinVaListKind getBuiltinVaListKind() const {
3801     return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
3802   }
3803   virtual void getGCCRegNames(const char * const *&Names,
3804                               unsigned &NumNames) const;
3805   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3806                                 unsigned &NumAliases) const;
3807   virtual bool validateAsmConstraint(const char *&Name,
3808                                      TargetInfo::ConstraintInfo &Info) const {
3809     switch (*Name) {
3810     default: break;
3811     case 'l': // r0-r7
3812     case 'h': // r8-r15
3813     case 'w': // VFP Floating point register single precision
3814     case 'P': // VFP Floating point register double precision
3815       Info.setAllowsRegister();
3816       return true;
3817     case 'Q': // A memory address that is a single base register.
3818       Info.setAllowsMemory();
3819       return true;
3820     case 'U': // a memory reference...
3821       switch (Name[1]) {
3822       case 'q': // ...ARMV4 ldrsb
3823       case 'v': // ...VFP load/store (reg+constant offset)
3824       case 'y': // ...iWMMXt load/store
3825       case 't': // address valid for load/store opaque types wider
3826                 // than 128-bits
3827       case 'n': // valid address for Neon doubleword vector load/store
3828       case 'm': // valid address for Neon element and structure load/store
3829       case 's': // valid address for non-offset loads/stores of quad-word
3830                 // values in four ARM registers
3831         Info.setAllowsMemory();
3832         Name++;
3833         return true;
3834       }
3835     }
3836     return false;
3837   }
3838   virtual std::string convertConstraint(const char *&Constraint) const {
3839     std::string R;
3840     switch (*Constraint) {
3841     case 'U':   // Two-character constraint; add "^" hint for later parsing.
3842       R = std::string("^") + std::string(Constraint, 2);
3843       Constraint++;
3844       break;
3845     case 'p': // 'p' should be translated to 'r' by default.
3846       R = std::string("r");
3847       break;
3848     default:
3849       return std::string(1, *Constraint);
3850     }
3851     return R;
3852   }
3853   virtual bool validateConstraintModifier(StringRef Constraint,
3854                                           const char Modifier,
3855                                           unsigned Size) const {
3856     bool isOutput = (Constraint[0] == '=');
3857     bool isInOut = (Constraint[0] == '+');
3858 
3859     // Strip off constraint modifiers.
3860     while (Constraint[0] == '=' ||
3861            Constraint[0] == '+' ||
3862            Constraint[0] == '&')
3863       Constraint = Constraint.substr(1);
3864 
3865     switch (Constraint[0]) {
3866     default: break;
3867     case 'r': {
3868       switch (Modifier) {
3869       default:
3870         return isInOut || (isOutput && Size >= 32) ||
3871           (!isOutput && !isInOut && Size <= 32);
3872       case 'q':
3873         // A register of size 32 cannot fit a vector type.
3874         return false;
3875       }
3876     }
3877     }
3878 
3879     return true;
3880   }
3881   virtual const char *getClobbers() const {
3882     // FIXME: Is this really right?
3883     return "";
3884   }
3885 
3886   virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3887     return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
3888   }
3889 
3890   virtual int getEHDataRegisterNumber(unsigned RegNo) const {
3891     if (RegNo == 0) return 0;
3892     if (RegNo == 1) return 1;
3893     return -1;
3894   }
3895 };
3896 
3897 const char * const ARMTargetInfo::GCCRegNames[] = {
3898   // Integer registers
3899   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3900   "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
3901 
3902   // Float registers
3903   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3904   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3905   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3906   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3907 
3908   // Double registers
3909   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3910   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3911   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3912   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3913 
3914   // Quad registers
3915   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3916   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
3917 };
3918 
3919 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
3920                                    unsigned &NumNames) const {
3921   Names = GCCRegNames;
3922   NumNames = llvm::array_lengthof(GCCRegNames);
3923 }
3924 
3925 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
3926   { { "a1" }, "r0" },
3927   { { "a2" }, "r1" },
3928   { { "a3" }, "r2" },
3929   { { "a4" }, "r3" },
3930   { { "v1" }, "r4" },
3931   { { "v2" }, "r5" },
3932   { { "v3" }, "r6" },
3933   { { "v4" }, "r7" },
3934   { { "v5" }, "r8" },
3935   { { "v6", "rfp" }, "r9" },
3936   { { "sl" }, "r10" },
3937   { { "fp" }, "r11" },
3938   { { "ip" }, "r12" },
3939   { { "r13" }, "sp" },
3940   { { "r14" }, "lr" },
3941   { { "r15" }, "pc" },
3942   // The S, D and Q registers overlap, but aren't really aliases; we
3943   // don't want to substitute one of these for a different-sized one.
3944 };
3945 
3946 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3947                                        unsigned &NumAliases) const {
3948   Aliases = GCCRegAliases;
3949   NumAliases = llvm::array_lengthof(GCCRegAliases);
3950 }
3951 
3952 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
3953 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3954 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3955                                               ALL_LANGUAGES },
3956 #include "clang/Basic/BuiltinsARM.def"
3957 };
3958 } // end anonymous namespace.
3959 
3960 namespace {
3961 class DarwinARMTargetInfo :
3962   public DarwinTargetInfo<ARMTargetInfo> {
3963 protected:
3964   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3965                             MacroBuilder &Builder) const {
3966     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
3967   }
3968 
3969 public:
3970   DarwinARMTargetInfo(const std::string& triple)
3971     : DarwinTargetInfo<ARMTargetInfo>(triple) {
3972     HasAlignMac68kSupport = true;
3973     // iOS always has 64-bit atomic instructions.
3974     // FIXME: This should be based off of the target features in ARMTargetInfo.
3975     MaxAtomicInlineWidth = 64;
3976 
3977     // Darwin on iOS uses a variant of the ARM C++ ABI.
3978     TheCXXABI.set(TargetCXXABI::iOS);
3979   }
3980 };
3981 } // end anonymous namespace.
3982 
3983 
3984 namespace {
3985 // Hexagon abstract base class
3986 class HexagonTargetInfo : public TargetInfo {
3987   static const Builtin::Info BuiltinInfo[];
3988   static const char * const GCCRegNames[];
3989   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3990   std::string CPU;
3991 public:
3992   HexagonTargetInfo(const std::string& triple) : TargetInfo(triple)  {
3993     BigEndian = false;
3994     DescriptionString = ("e-p:32:32:32-"
3995                          "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
3996                          "f64:64:64-f32:32:32-a0:0-n32");
3997 
3998     // {} in inline assembly are packet specifiers, not assembly variant
3999     // specifiers.
4000     NoAsmVariants = true;
4001   }
4002 
4003   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4004                                  unsigned &NumRecords) const {
4005     Records = BuiltinInfo;
4006     NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
4007   }
4008 
4009   virtual bool validateAsmConstraint(const char *&Name,
4010                                      TargetInfo::ConstraintInfo &Info) const {
4011     return true;
4012   }
4013 
4014   virtual void getTargetDefines(const LangOptions &Opts,
4015                                 MacroBuilder &Builder) const;
4016 
4017   virtual bool hasFeature(StringRef Feature) const {
4018     return Feature == "hexagon";
4019   }
4020 
4021   virtual BuiltinVaListKind getBuiltinVaListKind() const {
4022     return TargetInfo::CharPtrBuiltinVaList;
4023   }
4024   virtual void getGCCRegNames(const char * const *&Names,
4025                               unsigned &NumNames) const;
4026   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4027                                 unsigned &NumAliases) const;
4028   virtual const char *getClobbers() const {
4029     return "";
4030   }
4031 
4032   static const char *getHexagonCPUSuffix(StringRef Name) {
4033     return llvm::StringSwitch<const char*>(Name)
4034       .Case("hexagonv4", "4")
4035       .Case("hexagonv5", "5")
4036       .Default(0);
4037   }
4038 
4039   virtual bool setCPU(const std::string &Name) {
4040     if (!getHexagonCPUSuffix(Name))
4041       return false;
4042 
4043     CPU = Name;
4044     return true;
4045   }
4046 };
4047 
4048 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4049                                 MacroBuilder &Builder) const {
4050   Builder.defineMacro("qdsp6");
4051   Builder.defineMacro("__qdsp6", "1");
4052   Builder.defineMacro("__qdsp6__", "1");
4053 
4054   Builder.defineMacro("hexagon");
4055   Builder.defineMacro("__hexagon", "1");
4056   Builder.defineMacro("__hexagon__", "1");
4057 
4058   if(CPU == "hexagonv1") {
4059     Builder.defineMacro("__HEXAGON_V1__");
4060     Builder.defineMacro("__HEXAGON_ARCH__", "1");
4061     if(Opts.HexagonQdsp6Compat) {
4062       Builder.defineMacro("__QDSP6_V1__");
4063       Builder.defineMacro("__QDSP6_ARCH__", "1");
4064     }
4065   }
4066   else if(CPU == "hexagonv2") {
4067     Builder.defineMacro("__HEXAGON_V2__");
4068     Builder.defineMacro("__HEXAGON_ARCH__", "2");
4069     if(Opts.HexagonQdsp6Compat) {
4070       Builder.defineMacro("__QDSP6_V2__");
4071       Builder.defineMacro("__QDSP6_ARCH__", "2");
4072     }
4073   }
4074   else if(CPU == "hexagonv3") {
4075     Builder.defineMacro("__HEXAGON_V3__");
4076     Builder.defineMacro("__HEXAGON_ARCH__", "3");
4077     if(Opts.HexagonQdsp6Compat) {
4078       Builder.defineMacro("__QDSP6_V3__");
4079       Builder.defineMacro("__QDSP6_ARCH__", "3");
4080     }
4081   }
4082   else if(CPU == "hexagonv4") {
4083     Builder.defineMacro("__HEXAGON_V4__");
4084     Builder.defineMacro("__HEXAGON_ARCH__", "4");
4085     if(Opts.HexagonQdsp6Compat) {
4086       Builder.defineMacro("__QDSP6_V4__");
4087       Builder.defineMacro("__QDSP6_ARCH__", "4");
4088     }
4089   }
4090   else if(CPU == "hexagonv5") {
4091     Builder.defineMacro("__HEXAGON_V5__");
4092     Builder.defineMacro("__HEXAGON_ARCH__", "5");
4093     if(Opts.HexagonQdsp6Compat) {
4094       Builder.defineMacro("__QDSP6_V5__");
4095       Builder.defineMacro("__QDSP6_ARCH__", "5");
4096     }
4097   }
4098 }
4099 
4100 const char * const HexagonTargetInfo::GCCRegNames[] = {
4101   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4102   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4103   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4104   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4105   "p0", "p1", "p2", "p3",
4106   "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4107 };
4108 
4109 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4110                                    unsigned &NumNames) const {
4111   Names = GCCRegNames;
4112   NumNames = llvm::array_lengthof(GCCRegNames);
4113 }
4114 
4115 
4116 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4117   { { "sp" }, "r29" },
4118   { { "fp" }, "r30" },
4119   { { "lr" }, "r31" },
4120  };
4121 
4122 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4123                                      unsigned &NumAliases) const {
4124   Aliases = GCCRegAliases;
4125   NumAliases = llvm::array_lengthof(GCCRegAliases);
4126 }
4127 
4128 
4129 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
4130 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4131 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4132                                               ALL_LANGUAGES },
4133 #include "clang/Basic/BuiltinsHexagon.def"
4134 };
4135 }
4136 
4137 
4138 namespace {
4139 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
4140 class SparcTargetInfo : public TargetInfo {
4141   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4142   static const char * const GCCRegNames[];
4143   bool SoftFloat;
4144 public:
4145   SparcTargetInfo(const std::string &triple) : TargetInfo(triple) {}
4146 
4147   virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4148                                  StringRef Name,
4149                                  bool Enabled) const {
4150     if (Name == "soft-float")
4151       Features[Name] = Enabled;
4152     else
4153       return false;
4154 
4155     return true;
4156   }
4157   virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4158     SoftFloat = false;
4159     for (unsigned i = 0, e = Features.size(); i != e; ++i)
4160       if (Features[i] == "+soft-float")
4161         SoftFloat = true;
4162   }
4163   virtual void getTargetDefines(const LangOptions &Opts,
4164                                 MacroBuilder &Builder) const {
4165     DefineStd(Builder, "sparc", Opts);
4166     Builder.defineMacro("__REGISTER_PREFIX__", "");
4167 
4168     if (SoftFloat)
4169       Builder.defineMacro("SOFT_FLOAT", "1");
4170   }
4171 
4172   virtual bool hasFeature(StringRef Feature) const {
4173     return llvm::StringSwitch<bool>(Feature)
4174              .Case("softfloat", SoftFloat)
4175              .Case("sparc", true)
4176              .Default(false);
4177   }
4178 
4179   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4180                                  unsigned &NumRecords) const {
4181     // FIXME: Implement!
4182   }
4183   virtual BuiltinVaListKind getBuiltinVaListKind() const {
4184     return TargetInfo::VoidPtrBuiltinVaList;
4185   }
4186   virtual void getGCCRegNames(const char * const *&Names,
4187                               unsigned &NumNames) const;
4188   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4189                                 unsigned &NumAliases) const;
4190   virtual bool validateAsmConstraint(const char *&Name,
4191                                      TargetInfo::ConstraintInfo &info) const {
4192     // FIXME: Implement!
4193     return false;
4194   }
4195   virtual const char *getClobbers() const {
4196     // FIXME: Implement!
4197     return "";
4198   }
4199 };
4200 
4201 const char * const SparcTargetInfo::GCCRegNames[] = {
4202   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4203   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4204   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4205   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4206 };
4207 
4208 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
4209                                      unsigned &NumNames) const {
4210   Names = GCCRegNames;
4211   NumNames = llvm::array_lengthof(GCCRegNames);
4212 }
4213 
4214 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
4215   { { "g0" }, "r0" },
4216   { { "g1" }, "r1" },
4217   { { "g2" }, "r2" },
4218   { { "g3" }, "r3" },
4219   { { "g4" }, "r4" },
4220   { { "g5" }, "r5" },
4221   { { "g6" }, "r6" },
4222   { { "g7" }, "r7" },
4223   { { "o0" }, "r8" },
4224   { { "o1" }, "r9" },
4225   { { "o2" }, "r10" },
4226   { { "o3" }, "r11" },
4227   { { "o4" }, "r12" },
4228   { { "o5" }, "r13" },
4229   { { "o6", "sp" }, "r14" },
4230   { { "o7" }, "r15" },
4231   { { "l0" }, "r16" },
4232   { { "l1" }, "r17" },
4233   { { "l2" }, "r18" },
4234   { { "l3" }, "r19" },
4235   { { "l4" }, "r20" },
4236   { { "l5" }, "r21" },
4237   { { "l6" }, "r22" },
4238   { { "l7" }, "r23" },
4239   { { "i0" }, "r24" },
4240   { { "i1" }, "r25" },
4241   { { "i2" }, "r26" },
4242   { { "i3" }, "r27" },
4243   { { "i4" }, "r28" },
4244   { { "i5" }, "r29" },
4245   { { "i6", "fp" }, "r30" },
4246   { { "i7" }, "r31" },
4247 };
4248 
4249 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4250                                        unsigned &NumAliases) const {
4251   Aliases = GCCRegAliases;
4252   NumAliases = llvm::array_lengthof(GCCRegAliases);
4253 }
4254 
4255 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
4256 class SparcV8TargetInfo : public SparcTargetInfo {
4257 public:
4258   SparcV8TargetInfo(const std::string& triple) : SparcTargetInfo(triple) {
4259     // FIXME: Support Sparc quad-precision long double?
4260     DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4261                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4262   }
4263 
4264   virtual void getTargetDefines(const LangOptions &Opts,
4265                                 MacroBuilder &Builder) const {
4266     SparcTargetInfo::getTargetDefines(Opts, Builder);
4267     Builder.defineMacro("__sparcv8");
4268   }
4269 };
4270 
4271 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
4272 class SparcV9TargetInfo : public SparcTargetInfo {
4273 public:
4274   SparcV9TargetInfo(const std::string& triple) : SparcTargetInfo(triple) {
4275     // FIXME: Support Sparc quad-precision long double?
4276     DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4277                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128";
4278   }
4279 
4280   virtual void getTargetDefines(const LangOptions &Opts,
4281                                 MacroBuilder &Builder) const {
4282     SparcTargetInfo::getTargetDefines(Opts, Builder);
4283     Builder.defineMacro("__sparcv9");
4284     Builder.defineMacro("__arch64__");
4285     // Solaris and its derivative AuroraUX don't need these variants, but the
4286     // BSDs do.
4287     if (getTriple().getOS() != llvm::Triple::Solaris &&
4288         getTriple().getOS() != llvm::Triple::AuroraUX) {
4289       Builder.defineMacro("__sparc64__");
4290       Builder.defineMacro("__sparc_v9__");
4291       Builder.defineMacro("__sparcv9__");
4292     }
4293   }
4294 };
4295 
4296 } // end anonymous namespace.
4297 
4298 namespace {
4299 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4300 public:
4301   AuroraUXSparcV8TargetInfo(const std::string& triple) :
4302       AuroraUXTargetInfo<SparcV8TargetInfo>(triple) {
4303     SizeType = UnsignedInt;
4304     PtrDiffType = SignedInt;
4305   }
4306 };
4307 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
4308 public:
4309   SolarisSparcV8TargetInfo(const std::string& triple) :
4310       SolarisTargetInfo<SparcV8TargetInfo>(triple) {
4311     SizeType = UnsignedInt;
4312     PtrDiffType = SignedInt;
4313   }
4314 };
4315 } // end anonymous namespace.
4316 
4317 namespace {
4318   class SystemZTargetInfo : public TargetInfo {
4319     static const char *const GCCRegNames[];
4320 
4321   public:
4322     SystemZTargetInfo(const std::string& triple) : TargetInfo(triple) {
4323       TLSSupported = true;
4324       IntWidth = IntAlign = 32;
4325       LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
4326       PointerWidth = PointerAlign = 64;
4327       LongDoubleWidth = 128;
4328       LongDoubleAlign = 64;
4329       LongDoubleFormat = &llvm::APFloat::IEEEquad;
4330       MinGlobalAlign = 16;
4331       DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64"
4332        "-f32:32-f64:64-f128:64-a0:8:16-n32:64";
4333       MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4334     }
4335     virtual void getTargetDefines(const LangOptions &Opts,
4336                                   MacroBuilder &Builder) const {
4337       Builder.defineMacro("__s390__");
4338       Builder.defineMacro("__s390x__");
4339       Builder.defineMacro("__zarch__");
4340       Builder.defineMacro("__LONG_DOUBLE_128__");
4341     }
4342     virtual void getTargetBuiltins(const Builtin::Info *&Records,
4343                                    unsigned &NumRecords) const {
4344       // FIXME: Implement.
4345       Records = 0;
4346       NumRecords = 0;
4347     }
4348 
4349     virtual void getGCCRegNames(const char *const *&Names,
4350                                 unsigned &NumNames) const;
4351     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4352                                   unsigned &NumAliases) const {
4353       // No aliases.
4354       Aliases = 0;
4355       NumAliases = 0;
4356     }
4357     virtual bool validateAsmConstraint(const char *&Name,
4358                                        TargetInfo::ConstraintInfo &info) const;
4359     virtual const char *getClobbers() const {
4360       // FIXME: Is this really right?
4361       return "";
4362     }
4363     virtual BuiltinVaListKind getBuiltinVaListKind() const {
4364       return TargetInfo::SystemZBuiltinVaList;
4365     }
4366   };
4367 
4368   const char *const SystemZTargetInfo::GCCRegNames[] = {
4369     "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
4370     "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
4371     "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
4372     "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
4373   };
4374 
4375   void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
4376                                          unsigned &NumNames) const {
4377     Names = GCCRegNames;
4378     NumNames = llvm::array_lengthof(GCCRegNames);
4379   }
4380 
4381   bool SystemZTargetInfo::
4382   validateAsmConstraint(const char *&Name,
4383                         TargetInfo::ConstraintInfo &Info) const {
4384     switch (*Name) {
4385     default:
4386       return false;
4387 
4388     case 'a': // Address register
4389     case 'd': // Data register (equivalent to 'r')
4390     case 'f': // Floating-point register
4391       Info.setAllowsRegister();
4392       return true;
4393 
4394     case 'I': // Unsigned 8-bit constant
4395     case 'J': // Unsigned 12-bit constant
4396     case 'K': // Signed 16-bit constant
4397     case 'L': // Signed 20-bit displacement (on all targets we support)
4398     case 'M': // 0x7fffffff
4399       return true;
4400 
4401     case 'Q': // Memory with base and unsigned 12-bit displacement
4402     case 'R': // Likewise, plus an index
4403     case 'S': // Memory with base and signed 20-bit displacement
4404     case 'T': // Likewise, plus an index
4405       Info.setAllowsMemory();
4406       return true;
4407     }
4408   }
4409 }
4410 
4411 namespace {
4412   class MSP430TargetInfo : public TargetInfo {
4413     static const char * const GCCRegNames[];
4414   public:
4415     MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) {
4416       BigEndian = false;
4417       TLSSupported = false;
4418       IntWidth = 16; IntAlign = 16;
4419       LongWidth = 32; LongLongWidth = 64;
4420       LongAlign = LongLongAlign = 16;
4421       PointerWidth = 16; PointerAlign = 16;
4422       SuitableAlign = 16;
4423       SizeType = UnsignedInt;
4424       IntMaxType = SignedLong;
4425       UIntMaxType = UnsignedLong;
4426       IntPtrType = SignedShort;
4427       PtrDiffType = SignedInt;
4428       SigAtomicType = SignedLong;
4429       DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
4430    }
4431     virtual void getTargetDefines(const LangOptions &Opts,
4432                                   MacroBuilder &Builder) const {
4433       Builder.defineMacro("MSP430");
4434       Builder.defineMacro("__MSP430__");
4435       // FIXME: defines for different 'flavours' of MCU
4436     }
4437     virtual void getTargetBuiltins(const Builtin::Info *&Records,
4438                                    unsigned &NumRecords) const {
4439      // FIXME: Implement.
4440       Records = 0;
4441       NumRecords = 0;
4442     }
4443     virtual bool hasFeature(StringRef Feature) const {
4444       return Feature == "msp430";
4445     }
4446     virtual void getGCCRegNames(const char * const *&Names,
4447                                 unsigned &NumNames) const;
4448     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4449                                   unsigned &NumAliases) const {
4450       // No aliases.
4451       Aliases = 0;
4452       NumAliases = 0;
4453     }
4454     virtual bool validateAsmConstraint(const char *&Name,
4455                                        TargetInfo::ConstraintInfo &info) const {
4456       // No target constraints for now.
4457       return false;
4458     }
4459     virtual const char *getClobbers() const {
4460       // FIXME: Is this really right?
4461       return "";
4462     }
4463     virtual BuiltinVaListKind getBuiltinVaListKind() const {
4464       // FIXME: implement
4465       return TargetInfo::CharPtrBuiltinVaList;
4466    }
4467   };
4468 
4469   const char * const MSP430TargetInfo::GCCRegNames[] = {
4470     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4471     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4472   };
4473 
4474   void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
4475                                         unsigned &NumNames) const {
4476     Names = GCCRegNames;
4477     NumNames = llvm::array_lengthof(GCCRegNames);
4478   }
4479 }
4480 
4481 namespace {
4482 
4483   // LLVM and Clang cannot be used directly to output native binaries for
4484   // target, but is used to compile C code to llvm bitcode with correct
4485   // type and alignment information.
4486   //
4487   // TCE uses the llvm bitcode as input and uses it for generating customized
4488   // target processor and program binary. TCE co-design environment is
4489   // publicly available in http://tce.cs.tut.fi
4490 
4491   static const unsigned TCEOpenCLAddrSpaceMap[] = {
4492       3, // opencl_global
4493       4, // opencl_local
4494       5, // opencl_constant
4495       0, // cuda_device
4496       0, // cuda_constant
4497       0  // cuda_shared
4498   };
4499 
4500   class TCETargetInfo : public TargetInfo{
4501   public:
4502     TCETargetInfo(const std::string& triple) : TargetInfo(triple) {
4503       TLSSupported = false;
4504       IntWidth = 32;
4505       LongWidth = LongLongWidth = 32;
4506       PointerWidth = 32;
4507       IntAlign = 32;
4508       LongAlign = LongLongAlign = 32;
4509       PointerAlign = 32;
4510       SuitableAlign = 32;
4511       SizeType = UnsignedInt;
4512       IntMaxType = SignedLong;
4513       UIntMaxType = UnsignedLong;
4514       IntPtrType = SignedInt;
4515       PtrDiffType = SignedInt;
4516       FloatWidth = 32;
4517       FloatAlign = 32;
4518       DoubleWidth = 32;
4519       DoubleAlign = 32;
4520       LongDoubleWidth = 32;
4521       LongDoubleAlign = 32;
4522       FloatFormat = &llvm::APFloat::IEEEsingle;
4523       DoubleFormat = &llvm::APFloat::IEEEsingle;
4524       LongDoubleFormat = &llvm::APFloat::IEEEsingle;
4525       DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
4526                           "i16:16:32-i32:32:32-i64:32:32-"
4527                           "f32:32:32-f64:32:32-v64:32:32-"
4528                           "v128:32:32-a0:0:32-n32";
4529       AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
4530     }
4531 
4532     virtual void getTargetDefines(const LangOptions &Opts,
4533                                   MacroBuilder &Builder) const {
4534       DefineStd(Builder, "tce", Opts);
4535       Builder.defineMacro("__TCE__");
4536       Builder.defineMacro("__TCE_V1__");
4537     }
4538     virtual bool hasFeature(StringRef Feature) const {
4539       return Feature == "tce";
4540     }
4541 
4542     virtual void getTargetBuiltins(const Builtin::Info *&Records,
4543                                    unsigned &NumRecords) const {}
4544     virtual const char *getClobbers() const {
4545       return "";
4546     }
4547     virtual BuiltinVaListKind getBuiltinVaListKind() const {
4548       return TargetInfo::VoidPtrBuiltinVaList;
4549     }
4550     virtual void getGCCRegNames(const char * const *&Names,
4551                                 unsigned &NumNames) const {}
4552     virtual bool validateAsmConstraint(const char *&Name,
4553                                        TargetInfo::ConstraintInfo &info) const {
4554       return true;
4555     }
4556     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4557                                   unsigned &NumAliases) const {}
4558   };
4559 }
4560 
4561 namespace {
4562 class MipsTargetInfoBase : public TargetInfo {
4563   static const Builtin::Info BuiltinInfo[];
4564   std::string CPU;
4565   bool IsMips16;
4566   bool IsMicromips;
4567   bool IsSingleFloat;
4568   enum MipsFloatABI {
4569     HardFloat, SoftFloat
4570   } FloatABI;
4571   enum DspRevEnum {
4572     NoDSP, DSP1, DSP2
4573   } DspRev;
4574 
4575 protected:
4576   std::string ABI;
4577 
4578 public:
4579   MipsTargetInfoBase(const std::string& triple,
4580                      const std::string& ABIStr,
4581                      const std::string& CPUStr)
4582     : TargetInfo(triple),
4583       CPU(CPUStr),
4584       IsMips16(false),
4585       IsMicromips(false),
4586       IsSingleFloat(false),
4587       FloatABI(HardFloat),
4588       DspRev(NoDSP),
4589       ABI(ABIStr)
4590   {}
4591 
4592   virtual const char *getABI() const { return ABI.c_str(); }
4593   virtual bool setABI(const std::string &Name) = 0;
4594   virtual bool setCPU(const std::string &Name) {
4595     CPU = Name;
4596     return true;
4597   }
4598   void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4599     Features[ABI] = true;
4600     Features[CPU] = true;
4601   }
4602 
4603   virtual void getTargetDefines(const LangOptions &Opts,
4604                                 MacroBuilder &Builder) const {
4605     DefineStd(Builder, "mips", Opts);
4606     Builder.defineMacro("_mips");
4607     Builder.defineMacro("__REGISTER_PREFIX__", "");
4608 
4609     switch (FloatABI) {
4610     case HardFloat:
4611       Builder.defineMacro("__mips_hard_float", Twine(1));
4612       break;
4613     case SoftFloat:
4614       Builder.defineMacro("__mips_soft_float", Twine(1));
4615       break;
4616     }
4617 
4618     if (IsSingleFloat)
4619       Builder.defineMacro("__mips_single_float", Twine(1));
4620 
4621     if (IsMips16)
4622       Builder.defineMacro("__mips16", Twine(1));
4623 
4624     if (IsMicromips)
4625       Builder.defineMacro("__mips_micromips", Twine(1));
4626 
4627     switch (DspRev) {
4628     default:
4629       break;
4630     case DSP1:
4631       Builder.defineMacro("__mips_dsp_rev", Twine(1));
4632       Builder.defineMacro("__mips_dsp", Twine(1));
4633       break;
4634     case DSP2:
4635       Builder.defineMacro("__mips_dsp_rev", Twine(2));
4636       Builder.defineMacro("__mips_dspr2", Twine(1));
4637       Builder.defineMacro("__mips_dsp", Twine(1));
4638       break;
4639     }
4640 
4641     Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
4642     Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
4643     Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
4644 
4645     Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
4646     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
4647   }
4648 
4649   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4650                                  unsigned &NumRecords) const {
4651     Records = BuiltinInfo;
4652     NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
4653   }
4654   virtual bool hasFeature(StringRef Feature) const {
4655     return Feature == "mips";
4656   }
4657   virtual BuiltinVaListKind getBuiltinVaListKind() const {
4658     return TargetInfo::VoidPtrBuiltinVaList;
4659   }
4660   virtual void getGCCRegNames(const char * const *&Names,
4661                               unsigned &NumNames) const {
4662     static const char * const GCCRegNames[] = {
4663       // CPU register names
4664       // Must match second column of GCCRegAliases
4665       "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
4666       "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
4667       "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
4668       "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
4669       // Floating point register names
4670       "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
4671       "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4672       "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4673       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4674       // Hi/lo and condition register names
4675       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4676       "$fcc5","$fcc6","$fcc7"
4677     };
4678     Names = GCCRegNames;
4679     NumNames = llvm::array_lengthof(GCCRegNames);
4680   }
4681   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4682                                 unsigned &NumAliases) const = 0;
4683   virtual bool validateAsmConstraint(const char *&Name,
4684                                      TargetInfo::ConstraintInfo &Info) const {
4685     switch (*Name) {
4686     default:
4687       return false;
4688 
4689     case 'r': // CPU registers.
4690     case 'd': // Equivalent to "r" unless generating MIPS16 code.
4691     case 'y': // Equivalent to "r", backwards compatibility only.
4692     case 'f': // floating-point registers.
4693     case 'c': // $25 for indirect jumps
4694     case 'l': // lo register
4695     case 'x': // hilo register pair
4696       Info.setAllowsRegister();
4697       return true;
4698     case 'R': // An address that can be used in a non-macro load or store
4699       Info.setAllowsMemory();
4700       return true;
4701     }
4702   }
4703 
4704   virtual const char *getClobbers() const {
4705     // FIXME: Implement!
4706     return "";
4707   }
4708 
4709   virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4710                                  StringRef Name,
4711                                  bool Enabled) const {
4712     if (Name == "soft-float" || Name == "single-float" ||
4713         Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" ||
4714         Name == "mips32" || Name == "mips32r2" ||
4715         Name == "mips64" || Name == "mips64r2" ||
4716         Name == "mips16" || Name == "micromips" ||
4717         Name == "dsp" || Name == "dspr2") {
4718       Features[Name] = Enabled;
4719       return true;
4720     } else if (Name == "32") {
4721       Features["o32"] = Enabled;
4722       return true;
4723     } else if (Name == "64") {
4724       Features["n64"] = Enabled;
4725       return true;
4726     }
4727     return false;
4728   }
4729 
4730   virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4731     IsMips16 = false;
4732     IsMicromips = false;
4733     IsSingleFloat = false;
4734     FloatABI = HardFloat;
4735     DspRev = NoDSP;
4736 
4737     for (std::vector<std::string>::iterator it = Features.begin(),
4738          ie = Features.end(); it != ie; ++it) {
4739       if (*it == "+single-float")
4740         IsSingleFloat = true;
4741       else if (*it == "+soft-float")
4742         FloatABI = SoftFloat;
4743       else if (*it == "+mips16")
4744         IsMips16 = true;
4745       else if (*it == "+micromips")
4746         IsMicromips = true;
4747       else if (*it == "+dsp")
4748         DspRev = std::max(DspRev, DSP1);
4749       else if (*it == "+dspr2")
4750         DspRev = std::max(DspRev, DSP2);
4751     }
4752 
4753     // Remove front-end specific option.
4754     std::vector<std::string>::iterator it =
4755       std::find(Features.begin(), Features.end(), "+soft-float");
4756     if (it != Features.end())
4757       Features.erase(it);
4758   }
4759 
4760   virtual int getEHDataRegisterNumber(unsigned RegNo) const {
4761     if (RegNo == 0) return 4;
4762     if (RegNo == 1) return 5;
4763     return -1;
4764   }
4765 };
4766 
4767 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
4768 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4769 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4770                                               ALL_LANGUAGES },
4771 #include "clang/Basic/BuiltinsMips.def"
4772 };
4773 
4774 class Mips32TargetInfoBase : public MipsTargetInfoBase {
4775 public:
4776   Mips32TargetInfoBase(const std::string& triple) :
4777     MipsTargetInfoBase(triple, "o32", "mips32") {
4778     SizeType = UnsignedInt;
4779     PtrDiffType = SignedInt;
4780     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
4781   }
4782   virtual bool setABI(const std::string &Name) {
4783     if ((Name == "o32") || (Name == "eabi")) {
4784       ABI = Name;
4785       return true;
4786     } else if (Name == "32") {
4787       ABI = "o32";
4788       return true;
4789     } else
4790       return false;
4791   }
4792   virtual void getTargetDefines(const LangOptions &Opts,
4793                                 MacroBuilder &Builder) const {
4794     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4795 
4796     if (ABI == "o32") {
4797       Builder.defineMacro("__mips_o32");
4798       Builder.defineMacro("_ABIO32", "1");
4799       Builder.defineMacro("_MIPS_SIM", "_ABIO32");
4800     }
4801     else if (ABI == "eabi")
4802       Builder.defineMacro("__mips_eabi");
4803     else
4804       llvm_unreachable("Invalid ABI for Mips32.");
4805   }
4806   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4807                                 unsigned &NumAliases) const {
4808     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4809       { { "at" },  "$1" },
4810       { { "v0" },  "$2" },
4811       { { "v1" },  "$3" },
4812       { { "a0" },  "$4" },
4813       { { "a1" },  "$5" },
4814       { { "a2" },  "$6" },
4815       { { "a3" },  "$7" },
4816       { { "t0" },  "$8" },
4817       { { "t1" },  "$9" },
4818       { { "t2" }, "$10" },
4819       { { "t3" }, "$11" },
4820       { { "t4" }, "$12" },
4821       { { "t5" }, "$13" },
4822       { { "t6" }, "$14" },
4823       { { "t7" }, "$15" },
4824       { { "s0" }, "$16" },
4825       { { "s1" }, "$17" },
4826       { { "s2" }, "$18" },
4827       { { "s3" }, "$19" },
4828       { { "s4" }, "$20" },
4829       { { "s5" }, "$21" },
4830       { { "s6" }, "$22" },
4831       { { "s7" }, "$23" },
4832       { { "t8" }, "$24" },
4833       { { "t9" }, "$25" },
4834       { { "k0" }, "$26" },
4835       { { "k1" }, "$27" },
4836       { { "gp" }, "$28" },
4837       { { "sp","$sp" }, "$29" },
4838       { { "fp","$fp" }, "$30" },
4839       { { "ra" }, "$31" }
4840     };
4841     Aliases = GCCRegAliases;
4842     NumAliases = llvm::array_lengthof(GCCRegAliases);
4843   }
4844 };
4845 
4846 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
4847 public:
4848   Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4849     DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4850                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4851   }
4852   virtual void getTargetDefines(const LangOptions &Opts,
4853                                 MacroBuilder &Builder) const {
4854     DefineStd(Builder, "MIPSEB", Opts);
4855     Builder.defineMacro("_MIPSEB");
4856     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4857   }
4858 };
4859 
4860 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
4861 public:
4862   Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4863     BigEndian = false;
4864     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4865                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4866   }
4867   virtual void getTargetDefines(const LangOptions &Opts,
4868                                 MacroBuilder &Builder) const {
4869     DefineStd(Builder, "MIPSEL", Opts);
4870     Builder.defineMacro("_MIPSEL");
4871     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4872   }
4873 };
4874 
4875 class Mips64TargetInfoBase : public MipsTargetInfoBase {
4876   virtual void SetDescriptionString(const std::string &Name) = 0;
4877 public:
4878   Mips64TargetInfoBase(const std::string& triple) :
4879     MipsTargetInfoBase(triple, "n64", "mips64") {
4880     LongWidth = LongAlign = 64;
4881     PointerWidth = PointerAlign = 64;
4882     LongDoubleWidth = LongDoubleAlign = 128;
4883     LongDoubleFormat = &llvm::APFloat::IEEEquad;
4884     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
4885       LongDoubleWidth = LongDoubleAlign = 64;
4886       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4887     }
4888     SuitableAlign = 128;
4889     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4890   }
4891   virtual bool setABI(const std::string &Name) {
4892     SetDescriptionString(Name);
4893     if (Name == "n32") {
4894       LongWidth = LongAlign = 32;
4895       PointerWidth = PointerAlign = 32;
4896       ABI = Name;
4897       return true;
4898     } else if (Name == "n64") {
4899       ABI = Name;
4900       return true;
4901     } else if (Name == "64") {
4902       ABI = "n64";
4903       return true;
4904     } else
4905       return false;
4906   }
4907   virtual void getTargetDefines(const LangOptions &Opts,
4908                                 MacroBuilder &Builder) const {
4909     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4910 
4911     Builder.defineMacro("__mips64");
4912     Builder.defineMacro("__mips64__");
4913 
4914     if (ABI == "n32") {
4915       Builder.defineMacro("__mips_n32");
4916       Builder.defineMacro("_ABIN32", "2");
4917       Builder.defineMacro("_MIPS_SIM", "_ABIN32");
4918     }
4919     else if (ABI == "n64") {
4920       Builder.defineMacro("__mips_n64");
4921       Builder.defineMacro("_ABI64", "3");
4922       Builder.defineMacro("_MIPS_SIM", "_ABI64");
4923     }
4924     else
4925       llvm_unreachable("Invalid ABI for Mips64.");
4926   }
4927   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4928                                 unsigned &NumAliases) const {
4929     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4930       { { "at" },  "$1" },
4931       { { "v0" },  "$2" },
4932       { { "v1" },  "$3" },
4933       { { "a0" },  "$4" },
4934       { { "a1" },  "$5" },
4935       { { "a2" },  "$6" },
4936       { { "a3" },  "$7" },
4937       { { "a4" },  "$8" },
4938       { { "a5" },  "$9" },
4939       { { "a6" }, "$10" },
4940       { { "a7" }, "$11" },
4941       { { "t0" }, "$12" },
4942       { { "t1" }, "$13" },
4943       { { "t2" }, "$14" },
4944       { { "t3" }, "$15" },
4945       { { "s0" }, "$16" },
4946       { { "s1" }, "$17" },
4947       { { "s2" }, "$18" },
4948       { { "s3" }, "$19" },
4949       { { "s4" }, "$20" },
4950       { { "s5" }, "$21" },
4951       { { "s6" }, "$22" },
4952       { { "s7" }, "$23" },
4953       { { "t8" }, "$24" },
4954       { { "t9" }, "$25" },
4955       { { "k0" }, "$26" },
4956       { { "k1" }, "$27" },
4957       { { "gp" }, "$28" },
4958       { { "sp","$sp" }, "$29" },
4959       { { "fp","$fp" }, "$30" },
4960       { { "ra" }, "$31" }
4961     };
4962     Aliases = GCCRegAliases;
4963     NumAliases = llvm::array_lengthof(GCCRegAliases);
4964   }
4965 };
4966 
4967 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
4968   virtual void SetDescriptionString(const std::string &Name) {
4969     // Change DescriptionString only if ABI is n32.
4970     if (Name == "n32")
4971       DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4972                           "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4973                           "v64:64:64-n32:64-S128";
4974   }
4975 public:
4976   Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
4977     // Default ABI is n64.
4978     DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4979                         "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4980                         "v64:64:64-n32:64-S128";
4981   }
4982   virtual void getTargetDefines(const LangOptions &Opts,
4983                                 MacroBuilder &Builder) const {
4984     DefineStd(Builder, "MIPSEB", Opts);
4985     Builder.defineMacro("_MIPSEB");
4986     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4987   }
4988 };
4989 
4990 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
4991   virtual void SetDescriptionString(const std::string &Name) {
4992     // Change DescriptionString only if ABI is n32.
4993     if (Name == "n32")
4994       DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4995                           "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
4996                           "-v64:64:64-n32:64-S128";
4997   }
4998 public:
4999   Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
5000     // Default ABI is n64.
5001     BigEndian = false;
5002     DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5003                         "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5004                         "v64:64:64-n32:64-S128";
5005   }
5006   virtual void getTargetDefines(const LangOptions &Opts,
5007                                 MacroBuilder &Builder) const {
5008     DefineStd(Builder, "MIPSEL", Opts);
5009     Builder.defineMacro("_MIPSEL");
5010     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5011   }
5012 };
5013 } // end anonymous namespace.
5014 
5015 namespace {
5016 class PNaClTargetInfo : public TargetInfo {
5017 public:
5018   PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) {
5019     BigEndian = false;
5020     this->UserLabelPrefix = "";
5021     this->LongAlign = 32;
5022     this->LongWidth = 32;
5023     this->PointerAlign = 32;
5024     this->PointerWidth = 32;
5025     this->IntMaxType = TargetInfo::SignedLongLong;
5026     this->UIntMaxType = TargetInfo::UnsignedLongLong;
5027     this->Int64Type = TargetInfo::SignedLongLong;
5028     this->DoubleAlign = 64;
5029     this->LongDoubleWidth = 64;
5030     this->LongDoubleAlign = 64;
5031     this->SizeType = TargetInfo::UnsignedInt;
5032     this->PtrDiffType = TargetInfo::SignedInt;
5033     this->IntPtrType = TargetInfo::SignedInt;
5034     this->RegParmMax = 0; // Disallow regparm
5035     DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5036                         "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
5037   }
5038 
5039   void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
5040   }
5041   virtual void getArchDefines(const LangOptions &Opts,
5042                               MacroBuilder &Builder) const {
5043     Builder.defineMacro("__le32__");
5044     Builder.defineMacro("__pnacl__");
5045   }
5046   virtual void getTargetDefines(const LangOptions &Opts,
5047                                 MacroBuilder &Builder) const {
5048     Builder.defineMacro("__LITTLE_ENDIAN__");
5049     getArchDefines(Opts, Builder);
5050   }
5051   virtual bool hasFeature(StringRef Feature) const {
5052     return Feature == "pnacl";
5053   }
5054   virtual void getTargetBuiltins(const Builtin::Info *&Records,
5055                                  unsigned &NumRecords) const {
5056   }
5057   virtual BuiltinVaListKind getBuiltinVaListKind() const {
5058     return TargetInfo::PNaClABIBuiltinVaList;
5059   }
5060   virtual void getGCCRegNames(const char * const *&Names,
5061                               unsigned &NumNames) const;
5062   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5063                                 unsigned &NumAliases) const;
5064   virtual bool validateAsmConstraint(const char *&Name,
5065                                      TargetInfo::ConstraintInfo &Info) const {
5066     return false;
5067   }
5068 
5069   virtual const char *getClobbers() const {
5070     return "";
5071   }
5072 };
5073 
5074 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
5075                                      unsigned &NumNames) const {
5076   Names = NULL;
5077   NumNames = 0;
5078 }
5079 
5080 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5081                                        unsigned &NumAliases) const {
5082   Aliases = NULL;
5083   NumAliases = 0;
5084 }
5085 } // end anonymous namespace.
5086 
5087 namespace {
5088   static const unsigned SPIRAddrSpaceMap[] = {
5089     1,    // opencl_global
5090     3,    // opencl_local
5091     2,    // opencl_constant
5092     0,    // cuda_device
5093     0,    // cuda_constant
5094     0     // cuda_shared
5095   };
5096   class SPIRTargetInfo : public TargetInfo {
5097     static const char * const GCCRegNames[];
5098     static const Builtin::Info BuiltinInfo[];
5099     std::vector<StringRef> AvailableFeatures;
5100   public:
5101     SPIRTargetInfo(const std::string& triple) : TargetInfo(triple) {
5102       assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
5103         "SPIR target must use unknown OS");
5104       assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
5105         "SPIR target must use unknown environment type");
5106       BigEndian = false;
5107       TLSSupported = false;
5108       LongWidth = LongAlign = 64;
5109       AddrSpaceMap = &SPIRAddrSpaceMap;
5110       // Define available target features
5111       // These must be defined in sorted order!
5112       NoAsmVariants = true;
5113     }
5114     virtual void getTargetDefines(const LangOptions &Opts,
5115                                   MacroBuilder &Builder) const {
5116       DefineStd(Builder, "SPIR", Opts);
5117     }
5118     virtual bool hasFeature(StringRef Feature) const {
5119       return Feature == "spir";
5120     }
5121 
5122     virtual void getTargetBuiltins(const Builtin::Info *&Records,
5123                                    unsigned &NumRecords) const {}
5124     virtual const char *getClobbers() const {
5125       return "";
5126     }
5127     virtual void getGCCRegNames(const char * const *&Names,
5128                                 unsigned &NumNames) const {}
5129     virtual bool validateAsmConstraint(const char *&Name,
5130                                        TargetInfo::ConstraintInfo &info) const {
5131       return true;
5132     }
5133     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5134                                   unsigned &NumAliases) const {}
5135     virtual BuiltinVaListKind getBuiltinVaListKind() const {
5136       return TargetInfo::VoidPtrBuiltinVaList;
5137     }
5138   };
5139 
5140 
5141   class SPIR32TargetInfo : public SPIRTargetInfo {
5142   public:
5143     SPIR32TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
5144       PointerWidth = PointerAlign = 32;
5145       SizeType     = TargetInfo::UnsignedInt;
5146       PtrDiffType = IntPtrType = TargetInfo::SignedInt;
5147       DescriptionString
5148         = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5149           "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5150           "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5151           "v512:512:512-v1024:1024:1024";
5152     }
5153     virtual void getTargetDefines(const LangOptions &Opts,
5154                                   MacroBuilder &Builder) const {
5155       DefineStd(Builder, "SPIR32", Opts);
5156     }
5157   };
5158 
5159   class SPIR64TargetInfo : public SPIRTargetInfo {
5160   public:
5161     SPIR64TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
5162       PointerWidth = PointerAlign = 64;
5163       SizeType     = TargetInfo::UnsignedLong;
5164       PtrDiffType = IntPtrType = TargetInfo::SignedLong;
5165       DescriptionString
5166         = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5167           "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5168           "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5169           "v512:512:512-v1024:1024:1024";
5170     }
5171     virtual void getTargetDefines(const LangOptions &Opts,
5172                                   MacroBuilder &Builder) const {
5173       DefineStd(Builder, "SPIR64", Opts);
5174     }
5175   };
5176 }
5177 
5178 
5179 //===----------------------------------------------------------------------===//
5180 // Driver code
5181 //===----------------------------------------------------------------------===//
5182 
5183 static TargetInfo *AllocateTarget(const std::string &T) {
5184   llvm::Triple Triple(T);
5185   llvm::Triple::OSType os = Triple.getOS();
5186 
5187   switch (Triple.getArch()) {
5188   default:
5189     return NULL;
5190 
5191   case llvm::Triple::hexagon:
5192     return new HexagonTargetInfo(T);
5193 
5194   case llvm::Triple::aarch64:
5195     switch (os) {
5196     case llvm::Triple::Linux:
5197       return new LinuxTargetInfo<AArch64TargetInfo>(T);
5198     default:
5199       return new AArch64TargetInfo(T);
5200     }
5201 
5202   case llvm::Triple::arm:
5203   case llvm::Triple::thumb:
5204     if (Triple.isOSDarwin())
5205       return new DarwinARMTargetInfo(T);
5206 
5207     switch (os) {
5208     case llvm::Triple::Linux:
5209       return new LinuxTargetInfo<ARMTargetInfo>(T);
5210     case llvm::Triple::FreeBSD:
5211       return new FreeBSDTargetInfo<ARMTargetInfo>(T);
5212     case llvm::Triple::NetBSD:
5213       return new NetBSDTargetInfo<ARMTargetInfo>(T);
5214     case llvm::Triple::OpenBSD:
5215       return new OpenBSDTargetInfo<ARMTargetInfo>(T);
5216     case llvm::Triple::Bitrig:
5217       return new BitrigTargetInfo<ARMTargetInfo>(T);
5218     case llvm::Triple::RTEMS:
5219       return new RTEMSTargetInfo<ARMTargetInfo>(T);
5220     case llvm::Triple::NaCl:
5221       return new NaClTargetInfo<ARMTargetInfo>(T);
5222     default:
5223       return new ARMTargetInfo(T);
5224     }
5225 
5226   case llvm::Triple::msp430:
5227     return new MSP430TargetInfo(T);
5228 
5229   case llvm::Triple::mips:
5230     switch (os) {
5231     case llvm::Triple::Linux:
5232       return new LinuxTargetInfo<Mips32EBTargetInfo>(T);
5233     case llvm::Triple::RTEMS:
5234       return new RTEMSTargetInfo<Mips32EBTargetInfo>(T);
5235     case llvm::Triple::FreeBSD:
5236       return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T);
5237     case llvm::Triple::NetBSD:
5238       return new NetBSDTargetInfo<Mips32EBTargetInfo>(T);
5239     default:
5240       return new Mips32EBTargetInfo(T);
5241     }
5242 
5243   case llvm::Triple::mipsel:
5244     switch (os) {
5245     case llvm::Triple::Linux:
5246       return new LinuxTargetInfo<Mips32ELTargetInfo>(T);
5247     case llvm::Triple::RTEMS:
5248       return new RTEMSTargetInfo<Mips32ELTargetInfo>(T);
5249     case llvm::Triple::FreeBSD:
5250       return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T);
5251     case llvm::Triple::NetBSD:
5252       return new NetBSDTargetInfo<Mips32ELTargetInfo>(T);
5253     default:
5254       return new Mips32ELTargetInfo(T);
5255     }
5256 
5257   case llvm::Triple::mips64:
5258     switch (os) {
5259     case llvm::Triple::Linux:
5260       return new LinuxTargetInfo<Mips64EBTargetInfo>(T);
5261     case llvm::Triple::RTEMS:
5262       return new RTEMSTargetInfo<Mips64EBTargetInfo>(T);
5263     case llvm::Triple::FreeBSD:
5264       return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T);
5265     case llvm::Triple::NetBSD:
5266       return new NetBSDTargetInfo<Mips64EBTargetInfo>(T);
5267     case llvm::Triple::OpenBSD:
5268       return new OpenBSDTargetInfo<Mips64EBTargetInfo>(T);
5269     default:
5270       return new Mips64EBTargetInfo(T);
5271     }
5272 
5273   case llvm::Triple::mips64el:
5274     switch (os) {
5275     case llvm::Triple::Linux:
5276       return new LinuxTargetInfo<Mips64ELTargetInfo>(T);
5277     case llvm::Triple::RTEMS:
5278       return new RTEMSTargetInfo<Mips64ELTargetInfo>(T);
5279     case llvm::Triple::FreeBSD:
5280       return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T);
5281     case llvm::Triple::NetBSD:
5282       return new NetBSDTargetInfo<Mips64ELTargetInfo>(T);
5283     case llvm::Triple::OpenBSD:
5284       return new OpenBSDTargetInfo<Mips64ELTargetInfo>(T);
5285     default:
5286       return new Mips64ELTargetInfo(T);
5287     }
5288 
5289   case llvm::Triple::le32:
5290     switch (os) {
5291       case llvm::Triple::NaCl:
5292         return new NaClTargetInfo<PNaClTargetInfo>(T);
5293       default:
5294         return NULL;
5295     }
5296 
5297   case llvm::Triple::ppc:
5298     if (Triple.isOSDarwin())
5299       return new DarwinPPC32TargetInfo(T);
5300     switch (os) {
5301     case llvm::Triple::Linux:
5302       return new LinuxTargetInfo<PPC32TargetInfo>(T);
5303     case llvm::Triple::FreeBSD:
5304       return new FreeBSDTargetInfo<PPC32TargetInfo>(T);
5305     case llvm::Triple::NetBSD:
5306       return new NetBSDTargetInfo<PPC32TargetInfo>(T);
5307     case llvm::Triple::OpenBSD:
5308       return new OpenBSDTargetInfo<PPC32TargetInfo>(T);
5309     case llvm::Triple::RTEMS:
5310       return new RTEMSTargetInfo<PPC32TargetInfo>(T);
5311     default:
5312       return new PPC32TargetInfo(T);
5313     }
5314 
5315   case llvm::Triple::ppc64:
5316     if (Triple.isOSDarwin())
5317       return new DarwinPPC64TargetInfo(T);
5318     switch (os) {
5319     case llvm::Triple::Linux:
5320       return new LinuxTargetInfo<PPC64TargetInfo>(T);
5321     case llvm::Triple::Lv2:
5322       return new PS3PPUTargetInfo<PPC64TargetInfo>(T);
5323     case llvm::Triple::FreeBSD:
5324       return new FreeBSDTargetInfo<PPC64TargetInfo>(T);
5325     case llvm::Triple::NetBSD:
5326       return new NetBSDTargetInfo<PPC64TargetInfo>(T);
5327     default:
5328       return new PPC64TargetInfo(T);
5329     }
5330 
5331   case llvm::Triple::nvptx:
5332     return new NVPTX32TargetInfo(T);
5333   case llvm::Triple::nvptx64:
5334     return new NVPTX64TargetInfo(T);
5335 
5336   case llvm::Triple::mblaze:
5337     return new MBlazeTargetInfo(T);
5338 
5339   case llvm::Triple::r600:
5340     return new R600TargetInfo(T);
5341 
5342   case llvm::Triple::sparc:
5343     switch (os) {
5344     case llvm::Triple::Linux:
5345       return new LinuxTargetInfo<SparcV8TargetInfo>(T);
5346     case llvm::Triple::AuroraUX:
5347       return new AuroraUXSparcV8TargetInfo(T);
5348     case llvm::Triple::Solaris:
5349       return new SolarisSparcV8TargetInfo(T);
5350     case llvm::Triple::NetBSD:
5351       return new NetBSDTargetInfo<SparcV8TargetInfo>(T);
5352     case llvm::Triple::OpenBSD:
5353       return new OpenBSDTargetInfo<SparcV8TargetInfo>(T);
5354     case llvm::Triple::RTEMS:
5355       return new RTEMSTargetInfo<SparcV8TargetInfo>(T);
5356     default:
5357       return new SparcV8TargetInfo(T);
5358     }
5359 
5360   case llvm::Triple::sparcv9:
5361     switch (os) {
5362     case llvm::Triple::Linux:
5363       return new LinuxTargetInfo<SparcV9TargetInfo>(T);
5364     case llvm::Triple::AuroraUX:
5365       return new AuroraUXTargetInfo<SparcV9TargetInfo>(T);
5366     case llvm::Triple::Solaris:
5367       return new SolarisTargetInfo<SparcV9TargetInfo>(T);
5368     case llvm::Triple::NetBSD:
5369       return new NetBSDTargetInfo<SparcV9TargetInfo>(T);
5370     case llvm::Triple::OpenBSD:
5371       return new OpenBSDTargetInfo<SparcV9TargetInfo>(T);
5372     case llvm::Triple::FreeBSD:
5373       return new FreeBSDTargetInfo<SparcV9TargetInfo>(T);
5374     default:
5375       return new SparcV9TargetInfo(T);
5376     }
5377 
5378   case llvm::Triple::systemz:
5379     switch (os) {
5380     case llvm::Triple::Linux:
5381       return new LinuxTargetInfo<SystemZTargetInfo>(T);
5382     default:
5383       return new SystemZTargetInfo(T);
5384     }
5385 
5386   case llvm::Triple::tce:
5387     return new TCETargetInfo(T);
5388 
5389   case llvm::Triple::x86:
5390     if (Triple.isOSDarwin())
5391       return new DarwinI386TargetInfo(T);
5392 
5393     switch (os) {
5394     case llvm::Triple::AuroraUX:
5395       return new AuroraUXTargetInfo<X86_32TargetInfo>(T);
5396     case llvm::Triple::Linux:
5397       return new LinuxTargetInfo<X86_32TargetInfo>(T);
5398     case llvm::Triple::DragonFly:
5399       return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T);
5400     case llvm::Triple::NetBSD:
5401       return new NetBSDI386TargetInfo(T);
5402     case llvm::Triple::OpenBSD:
5403       return new OpenBSDI386TargetInfo(T);
5404     case llvm::Triple::Bitrig:
5405       return new BitrigI386TargetInfo(T);
5406     case llvm::Triple::FreeBSD:
5407       return new FreeBSDTargetInfo<X86_32TargetInfo>(T);
5408     case llvm::Triple::Minix:
5409       return new MinixTargetInfo<X86_32TargetInfo>(T);
5410     case llvm::Triple::Solaris:
5411       return new SolarisTargetInfo<X86_32TargetInfo>(T);
5412     case llvm::Triple::Cygwin:
5413       return new CygwinX86_32TargetInfo(T);
5414     case llvm::Triple::MinGW32:
5415       return new MinGWX86_32TargetInfo(T);
5416     case llvm::Triple::Win32:
5417       return new VisualStudioWindowsX86_32TargetInfo(T);
5418     case llvm::Triple::Haiku:
5419       return new HaikuX86_32TargetInfo(T);
5420     case llvm::Triple::RTEMS:
5421       return new RTEMSX86_32TargetInfo(T);
5422     case llvm::Triple::NaCl:
5423       return new NaClTargetInfo<X86_32TargetInfo>(T);
5424     default:
5425       return new X86_32TargetInfo(T);
5426     }
5427 
5428   case llvm::Triple::x86_64:
5429     if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
5430       return new DarwinX86_64TargetInfo(T);
5431 
5432     switch (os) {
5433     case llvm::Triple::AuroraUX:
5434       return new AuroraUXTargetInfo<X86_64TargetInfo>(T);
5435     case llvm::Triple::Linux:
5436       return new LinuxTargetInfo<X86_64TargetInfo>(T);
5437     case llvm::Triple::DragonFly:
5438       return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T);
5439     case llvm::Triple::NetBSD:
5440       return new NetBSDTargetInfo<X86_64TargetInfo>(T);
5441     case llvm::Triple::OpenBSD:
5442       return new OpenBSDX86_64TargetInfo(T);
5443     case llvm::Triple::Bitrig:
5444       return new BitrigX86_64TargetInfo(T);
5445     case llvm::Triple::FreeBSD:
5446       return new FreeBSDTargetInfo<X86_64TargetInfo>(T);
5447     case llvm::Triple::Solaris:
5448       return new SolarisTargetInfo<X86_64TargetInfo>(T);
5449     case llvm::Triple::MinGW32:
5450       return new MinGWX86_64TargetInfo(T);
5451     case llvm::Triple::Win32:   // This is what Triple.h supports now.
5452       return new VisualStudioWindowsX86_64TargetInfo(T);
5453     case llvm::Triple::NaCl:
5454       return new NaClTargetInfo<X86_64TargetInfo>(T);
5455     default:
5456       return new X86_64TargetInfo(T);
5457     }
5458 
5459     case llvm::Triple::spir: {
5460       llvm::Triple Triple(T);
5461       if (Triple.getOS() != llvm::Triple::UnknownOS ||
5462         Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5463         return NULL;
5464       return new SPIR32TargetInfo(T);
5465     }
5466     case llvm::Triple::spir64: {
5467       llvm::Triple Triple(T);
5468       if (Triple.getOS() != llvm::Triple::UnknownOS ||
5469         Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5470         return NULL;
5471       return new SPIR64TargetInfo(T);
5472     }
5473   }
5474 }
5475 
5476 /// CreateTargetInfo - Return the target info object for the specified target
5477 /// triple.
5478 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
5479                                          TargetOptions *Opts) {
5480   llvm::Triple Triple(Opts->Triple);
5481 
5482   // Construct the target
5483   OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str()));
5484   if (!Target) {
5485     Diags.Report(diag::err_target_unknown_triple) << Triple.str();
5486     return 0;
5487   }
5488   Target->setTargetOpts(Opts);
5489 
5490   // Set the target CPU if specified.
5491   if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
5492     Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
5493     return 0;
5494   }
5495 
5496   // Set the target ABI if specified.
5497   if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
5498     Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
5499     return 0;
5500   }
5501 
5502   // Set the target C++ ABI.
5503   if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
5504     Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
5505     return 0;
5506   }
5507 
5508   // Compute the default target features, we need the target to handle this
5509   // because features may have dependencies on one another.
5510   llvm::StringMap<bool> Features;
5511   Target->getDefaultFeatures(Features);
5512 
5513   // Apply the user specified deltas.
5514   // First the enables.
5515   for (std::vector<std::string>::const_iterator
5516          it = Opts->FeaturesAsWritten.begin(),
5517          ie = Opts->FeaturesAsWritten.end();
5518        it != ie; ++it) {
5519     const char *Name = it->c_str();
5520 
5521     if (Name[0] != '+')
5522       continue;
5523 
5524     // Apply the feature via the target.
5525     if (!Target->setFeatureEnabled(Features, Name + 1, true)) {
5526       Diags.Report(diag::err_target_invalid_feature) << Name;
5527       return 0;
5528     }
5529   }
5530 
5531   // Then the disables.
5532   for (std::vector<std::string>::const_iterator
5533          it = Opts->FeaturesAsWritten.begin(),
5534          ie = Opts->FeaturesAsWritten.end();
5535        it != ie; ++it) {
5536     const char *Name = it->c_str();
5537 
5538     if (Name[0] == '+')
5539       continue;
5540 
5541     // Apply the feature via the target.
5542     if (Name[0] != '-' ||
5543         !Target->setFeatureEnabled(Features, Name + 1, false)) {
5544       Diags.Report(diag::err_target_invalid_feature) << Name;
5545       return 0;
5546     }
5547   }
5548 
5549   // Add the features to the compile options.
5550   //
5551   // FIXME: If we are completely confident that we have the right set, we only
5552   // need to pass the minuses.
5553   Opts->Features.clear();
5554   for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
5555          ie = Features.end(); it != ie; ++it)
5556     Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
5557   Target->HandleTargetFeatures(Opts->Features);
5558 
5559   return Target.take();
5560 }
5561