1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/IR/Type.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include <algorithm> 32 #include <memory> 33 using namespace clang; 34 35 //===----------------------------------------------------------------------===// 36 // Common code shared among targets. 37 //===----------------------------------------------------------------------===// 38 39 /// DefineStd - Define a macro name and standard variants. For example if 40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 41 /// when in GNU mode. 42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 43 const LangOptions &Opts) { 44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 45 46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 47 // in the user's namespace. 48 if (Opts.GNUMode) 49 Builder.defineMacro(MacroName); 50 51 // Define __unix. 52 Builder.defineMacro("__" + MacroName); 53 54 // Define __unix__. 55 Builder.defineMacro("__" + MacroName + "__"); 56 } 57 58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 59 bool Tuning = true) { 60 Builder.defineMacro("__" + CPUName); 61 Builder.defineMacro("__" + CPUName + "__"); 62 if (Tuning) 63 Builder.defineMacro("__tune_" + CPUName + "__"); 64 } 65 66 //===----------------------------------------------------------------------===// 67 // Defines specific to certain operating systems. 68 //===----------------------------------------------------------------------===// 69 70 namespace { 71 template<typename TgtInfo> 72 class OSTargetInfo : public TgtInfo { 73 protected: 74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 75 MacroBuilder &Builder) const=0; 76 public: 77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 78 void getTargetDefines(const LangOptions &Opts, 79 MacroBuilder &Builder) const override { 80 TgtInfo::getTargetDefines(Opts, Builder); 81 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 82 } 83 84 }; 85 } // end anonymous namespace 86 87 88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 89 const llvm::Triple &Triple, 90 StringRef &PlatformName, 91 VersionTuple &PlatformMinVersion) { 92 Builder.defineMacro("__APPLE_CC__", "6000"); 93 Builder.defineMacro("__APPLE__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.has(SanitizerKind::Address)) 98 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 99 100 if (!Opts.ObjCAutoRefCount) { 101 // __weak is always defined, for use in blocks and with objc pointers. 102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 103 104 // Darwin defines __strong even in C mode (just to nothing). 105 if (Opts.getGC() != LangOptions::NonGC) 106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 107 else 108 Builder.defineMacro("__strong", ""); 109 110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 111 // allow this in C, since one might have block pointers in structs that 112 // are used in pure C code and in Objective-C ARC. 113 Builder.defineMacro("__unsafe_unretained", ""); 114 } 115 116 if (Opts.Static) 117 Builder.defineMacro("__STATIC__"); 118 else 119 Builder.defineMacro("__DYNAMIC__"); 120 121 if (Opts.POSIXThreads) 122 Builder.defineMacro("_REENTRANT"); 123 124 // Get the platform type and version number from the triple. 125 unsigned Maj, Min, Rev; 126 if (Triple.isMacOSX()) { 127 Triple.getMacOSXVersion(Maj, Min, Rev); 128 PlatformName = "macosx"; 129 } else { 130 Triple.getOSVersion(Maj, Min, Rev); 131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 132 } 133 134 // If -target arch-pc-win32-macho option specified, we're 135 // generating code for Win32 ABI. No need to emit 136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 137 if (PlatformName == "win32") { 138 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 139 return; 140 } 141 142 // Set the appropriate OS version define. 143 if (Triple.isiOS()) { 144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 145 char Str[6]; 146 Str[0] = '0' + Maj; 147 Str[1] = '0' + (Min / 10); 148 Str[2] = '0' + (Min % 10); 149 Str[3] = '0' + (Rev / 10); 150 Str[4] = '0' + (Rev % 10); 151 Str[5] = '\0'; 152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 153 Str); 154 } else if (Triple.isMacOSX()) { 155 // Note that the Driver allows versions which aren't representable in the 156 // define (because we only get a single digit for the minor and micro 157 // revision numbers). So, we limit them to the maximum representable 158 // version. 159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 160 char Str[7]; 161 if (Maj < 10 || (Maj == 10 && Min < 10)) { 162 Str[0] = '0' + (Maj / 10); 163 Str[1] = '0' + (Maj % 10); 164 Str[2] = '0' + std::min(Min, 9U); 165 Str[3] = '0' + std::min(Rev, 9U); 166 Str[4] = '\0'; 167 } else { 168 // Handle versions > 10.9. 169 Str[0] = '0' + (Maj / 10); 170 Str[1] = '0' + (Maj % 10); 171 Str[2] = '0' + (Min / 10); 172 Str[3] = '0' + (Min % 10); 173 Str[4] = '0' + (Rev / 10); 174 Str[5] = '0' + (Rev % 10); 175 Str[6] = '\0'; 176 } 177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 178 } 179 180 // Tell users about the kernel if there is one. 181 if (Triple.isOSDarwin()) 182 Builder.defineMacro("__MACH__"); 183 184 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 185 } 186 187 namespace { 188 template<typename Target> 189 class DarwinTargetInfo : public OSTargetInfo<Target> { 190 protected: 191 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 192 MacroBuilder &Builder) const override { 193 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 194 this->PlatformMinVersion); 195 } 196 197 public: 198 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 199 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 200 this->MCountName = "\01mcount"; 201 } 202 203 std::string isValidSectionSpecifier(StringRef SR) const override { 204 // Let MCSectionMachO validate this. 205 StringRef Segment, Section; 206 unsigned TAA, StubSize; 207 bool HasTAA; 208 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 209 TAA, HasTAA, StubSize); 210 } 211 212 const char *getStaticInitSectionSpecifier() const override { 213 // FIXME: We should return 0 when building kexts. 214 return "__TEXT,__StaticInit,regular,pure_instructions"; 215 } 216 217 /// Darwin does not support protected visibility. Darwin's "default" 218 /// is very similar to ELF's "protected"; Darwin requires a "weak" 219 /// attribute on declarations that can be dynamically replaced. 220 bool hasProtectedVisibility() const override { 221 return false; 222 } 223 }; 224 225 226 // DragonFlyBSD Target 227 template<typename Target> 228 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 229 protected: 230 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 231 MacroBuilder &Builder) const override { 232 // DragonFly defines; list based off of gcc output 233 Builder.defineMacro("__DragonFly__"); 234 Builder.defineMacro("__DragonFly_cc_version", "100001"); 235 Builder.defineMacro("__ELF__"); 236 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 237 Builder.defineMacro("__tune_i386__"); 238 DefineStd(Builder, "unix", Opts); 239 } 240 public: 241 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 242 : OSTargetInfo<Target>(Triple) { 243 this->UserLabelPrefix = ""; 244 245 switch (Triple.getArch()) { 246 default: 247 case llvm::Triple::x86: 248 case llvm::Triple::x86_64: 249 this->MCountName = ".mcount"; 250 break; 251 } 252 } 253 }; 254 255 // FreeBSD Target 256 template<typename Target> 257 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 258 protected: 259 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 260 MacroBuilder &Builder) const override { 261 // FreeBSD defines; list based off of gcc output 262 263 unsigned Release = Triple.getOSMajorVersion(); 264 if (Release == 0U) 265 Release = 8; 266 267 Builder.defineMacro("__FreeBSD__", Twine(Release)); 268 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 269 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 270 DefineStd(Builder, "unix", Opts); 271 Builder.defineMacro("__ELF__"); 272 273 // On FreeBSD, wchar_t contains the number of the code point as 274 // used by the character set of the locale. These character sets are 275 // not necessarily a superset of ASCII. 276 // 277 // FIXME: This is wrong; the macro refers to the numerical values 278 // of wchar_t *literals*, which are not locale-dependent. However, 279 // FreeBSD systems apparently depend on us getting this wrong, and 280 // setting this to 1 is conforming even if all the basic source 281 // character literals have the same encoding as char and wchar_t. 282 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 283 } 284 public: 285 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 286 this->UserLabelPrefix = ""; 287 288 switch (Triple.getArch()) { 289 default: 290 case llvm::Triple::x86: 291 case llvm::Triple::x86_64: 292 this->MCountName = ".mcount"; 293 break; 294 case llvm::Triple::mips: 295 case llvm::Triple::mipsel: 296 case llvm::Triple::ppc: 297 case llvm::Triple::ppc64: 298 case llvm::Triple::ppc64le: 299 this->MCountName = "_mcount"; 300 break; 301 case llvm::Triple::arm: 302 this->MCountName = "__mcount"; 303 break; 304 } 305 } 306 }; 307 308 // GNU/kFreeBSD Target 309 template<typename Target> 310 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 311 protected: 312 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 313 MacroBuilder &Builder) const override { 314 // GNU/kFreeBSD defines; list based off of gcc output 315 316 DefineStd(Builder, "unix", Opts); 317 Builder.defineMacro("__FreeBSD_kernel__"); 318 Builder.defineMacro("__GLIBC__"); 319 Builder.defineMacro("__ELF__"); 320 if (Opts.POSIXThreads) 321 Builder.defineMacro("_REENTRANT"); 322 if (Opts.CPlusPlus) 323 Builder.defineMacro("_GNU_SOURCE"); 324 } 325 public: 326 KFreeBSDTargetInfo(const llvm::Triple &Triple) 327 : OSTargetInfo<Target>(Triple) { 328 this->UserLabelPrefix = ""; 329 } 330 }; 331 332 // Minix Target 333 template<typename Target> 334 class MinixTargetInfo : public OSTargetInfo<Target> { 335 protected: 336 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 337 MacroBuilder &Builder) const override { 338 // Minix defines 339 340 Builder.defineMacro("__minix", "3"); 341 Builder.defineMacro("_EM_WSIZE", "4"); 342 Builder.defineMacro("_EM_PSIZE", "4"); 343 Builder.defineMacro("_EM_SSIZE", "2"); 344 Builder.defineMacro("_EM_LSIZE", "4"); 345 Builder.defineMacro("_EM_FSIZE", "4"); 346 Builder.defineMacro("_EM_DSIZE", "8"); 347 Builder.defineMacro("__ELF__"); 348 DefineStd(Builder, "unix", Opts); 349 } 350 public: 351 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 352 this->UserLabelPrefix = ""; 353 } 354 }; 355 356 // Linux target 357 template<typename Target> 358 class LinuxTargetInfo : public OSTargetInfo<Target> { 359 protected: 360 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 361 MacroBuilder &Builder) const override { 362 // Linux defines; list based off of gcc output 363 DefineStd(Builder, "unix", Opts); 364 DefineStd(Builder, "linux", Opts); 365 Builder.defineMacro("__gnu_linux__"); 366 Builder.defineMacro("__ELF__"); 367 if (Triple.getEnvironment() == llvm::Triple::Android) 368 Builder.defineMacro("__ANDROID__", "1"); 369 if (Opts.POSIXThreads) 370 Builder.defineMacro("_REENTRANT"); 371 if (Opts.CPlusPlus) 372 Builder.defineMacro("_GNU_SOURCE"); 373 } 374 public: 375 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 376 this->UserLabelPrefix = ""; 377 this->WIntType = TargetInfo::UnsignedInt; 378 379 switch (Triple.getArch()) { 380 default: 381 break; 382 case llvm::Triple::ppc: 383 case llvm::Triple::ppc64: 384 case llvm::Triple::ppc64le: 385 this->MCountName = "_mcount"; 386 break; 387 } 388 } 389 390 const char *getStaticInitSectionSpecifier() const override { 391 return ".text.startup"; 392 } 393 }; 394 395 // NetBSD Target 396 template<typename Target> 397 class NetBSDTargetInfo : public OSTargetInfo<Target> { 398 protected: 399 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 400 MacroBuilder &Builder) const override { 401 // NetBSD defines; list based off of gcc output 402 Builder.defineMacro("__NetBSD__"); 403 Builder.defineMacro("__unix__"); 404 Builder.defineMacro("__ELF__"); 405 if (Opts.POSIXThreads) 406 Builder.defineMacro("_POSIX_THREADS"); 407 408 switch (Triple.getArch()) { 409 default: 410 break; 411 case llvm::Triple::arm: 412 case llvm::Triple::armeb: 413 case llvm::Triple::thumb: 414 case llvm::Triple::thumbeb: 415 Builder.defineMacro("__ARM_DWARF_EH__"); 416 break; 417 } 418 } 419 public: 420 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 421 this->UserLabelPrefix = ""; 422 } 423 }; 424 425 // OpenBSD Target 426 template<typename Target> 427 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 428 protected: 429 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 430 MacroBuilder &Builder) const override { 431 // OpenBSD defines; list based off of gcc output 432 433 Builder.defineMacro("__OpenBSD__"); 434 DefineStd(Builder, "unix", Opts); 435 Builder.defineMacro("__ELF__"); 436 if (Opts.POSIXThreads) 437 Builder.defineMacro("_REENTRANT"); 438 } 439 public: 440 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 441 this->UserLabelPrefix = ""; 442 this->TLSSupported = false; 443 444 switch (Triple.getArch()) { 445 default: 446 case llvm::Triple::x86: 447 case llvm::Triple::x86_64: 448 case llvm::Triple::arm: 449 case llvm::Triple::sparc: 450 this->MCountName = "__mcount"; 451 break; 452 case llvm::Triple::mips64: 453 case llvm::Triple::mips64el: 454 case llvm::Triple::ppc: 455 case llvm::Triple::sparcv9: 456 this->MCountName = "_mcount"; 457 break; 458 } 459 } 460 }; 461 462 // Bitrig Target 463 template<typename Target> 464 class BitrigTargetInfo : public OSTargetInfo<Target> { 465 protected: 466 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 467 MacroBuilder &Builder) const override { 468 // Bitrig defines; list based off of gcc output 469 470 Builder.defineMacro("__Bitrig__"); 471 DefineStd(Builder, "unix", Opts); 472 Builder.defineMacro("__ELF__"); 473 if (Opts.POSIXThreads) 474 Builder.defineMacro("_REENTRANT"); 475 } 476 public: 477 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 478 this->UserLabelPrefix = ""; 479 this->MCountName = "__mcount"; 480 } 481 }; 482 483 // PSP Target 484 template<typename Target> 485 class PSPTargetInfo : public OSTargetInfo<Target> { 486 protected: 487 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 488 MacroBuilder &Builder) const override { 489 // PSP defines; list based on the output of the pspdev gcc toolchain. 490 Builder.defineMacro("PSP"); 491 Builder.defineMacro("_PSP"); 492 Builder.defineMacro("__psp__"); 493 Builder.defineMacro("__ELF__"); 494 } 495 public: 496 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 497 this->UserLabelPrefix = ""; 498 } 499 }; 500 501 // PS3 PPU Target 502 template<typename Target> 503 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 504 protected: 505 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 506 MacroBuilder &Builder) const override { 507 // PS3 PPU defines. 508 Builder.defineMacro("__PPC__"); 509 Builder.defineMacro("__PPU__"); 510 Builder.defineMacro("__CELLOS_LV2__"); 511 Builder.defineMacro("__ELF__"); 512 Builder.defineMacro("__LP32__"); 513 Builder.defineMacro("_ARCH_PPC64"); 514 Builder.defineMacro("__powerpc64__"); 515 } 516 public: 517 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 518 this->UserLabelPrefix = ""; 519 this->LongWidth = this->LongAlign = 32; 520 this->PointerWidth = this->PointerAlign = 32; 521 this->IntMaxType = TargetInfo::SignedLongLong; 522 this->Int64Type = TargetInfo::SignedLongLong; 523 this->SizeType = TargetInfo::UnsignedInt; 524 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 525 } 526 }; 527 528 template <typename Target> 529 class PS4OSTargetInfo : public OSTargetInfo<Target> { 530 protected: 531 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 532 MacroBuilder &Builder) const override { 533 Builder.defineMacro("__FreeBSD__", "9"); 534 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 535 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 536 DefineStd(Builder, "unix", Opts); 537 Builder.defineMacro("__ELF__"); 538 Builder.defineMacro("__PS4__"); 539 } 540 public: 541 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 542 this->WCharType = this->UnsignedShort; 543 544 this->UserLabelPrefix = ""; 545 546 switch (Triple.getArch()) { 547 default: 548 case llvm::Triple::x86_64: 549 this->MCountName = ".mcount"; 550 break; 551 } 552 } 553 }; 554 555 // Solaris target 556 template<typename Target> 557 class SolarisTargetInfo : public OSTargetInfo<Target> { 558 protected: 559 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 560 MacroBuilder &Builder) const override { 561 DefineStd(Builder, "sun", Opts); 562 DefineStd(Builder, "unix", Opts); 563 Builder.defineMacro("__ELF__"); 564 Builder.defineMacro("__svr4__"); 565 Builder.defineMacro("__SVR4"); 566 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 567 // newer, but to 500 for everything else. feature_test.h has a check to 568 // ensure that you are not using C99 with an old version of X/Open or C89 569 // with a new version. 570 if (Opts.C99) 571 Builder.defineMacro("_XOPEN_SOURCE", "600"); 572 else 573 Builder.defineMacro("_XOPEN_SOURCE", "500"); 574 if (Opts.CPlusPlus) 575 Builder.defineMacro("__C99FEATURES__"); 576 Builder.defineMacro("_LARGEFILE_SOURCE"); 577 Builder.defineMacro("_LARGEFILE64_SOURCE"); 578 Builder.defineMacro("__EXTENSIONS__"); 579 Builder.defineMacro("_REENTRANT"); 580 } 581 public: 582 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 583 this->UserLabelPrefix = ""; 584 this->WCharType = this->SignedInt; 585 // FIXME: WIntType should be SignedLong 586 } 587 }; 588 589 // Windows target 590 template<typename Target> 591 class WindowsTargetInfo : public OSTargetInfo<Target> { 592 protected: 593 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 594 MacroBuilder &Builder) const override { 595 Builder.defineMacro("_WIN32"); 596 } 597 void getVisualStudioDefines(const LangOptions &Opts, 598 MacroBuilder &Builder) const { 599 if (Opts.CPlusPlus) { 600 if (Opts.RTTIData) 601 Builder.defineMacro("_CPPRTTI"); 602 603 if (Opts.CXXExceptions) 604 Builder.defineMacro("_CPPUNWIND"); 605 } 606 607 if (!Opts.CharIsSigned) 608 Builder.defineMacro("_CHAR_UNSIGNED"); 609 610 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 611 // but it works for now. 612 if (Opts.POSIXThreads) 613 Builder.defineMacro("_MT"); 614 615 if (Opts.MSCompatibilityVersion) { 616 Builder.defineMacro("_MSC_VER", 617 Twine(Opts.MSCompatibilityVersion / 100000)); 618 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 619 // FIXME We cannot encode the revision information into 32-bits 620 Builder.defineMacro("_MSC_BUILD", Twine(1)); 621 } 622 623 if (Opts.MicrosoftExt) { 624 Builder.defineMacro("_MSC_EXTENSIONS"); 625 626 if (Opts.CPlusPlus11) { 627 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 628 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 629 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 630 } 631 } 632 633 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 634 } 635 636 public: 637 WindowsTargetInfo(const llvm::Triple &Triple) 638 : OSTargetInfo<Target>(Triple) {} 639 }; 640 641 template <typename Target> 642 class NaClTargetInfo : public OSTargetInfo<Target> { 643 protected: 644 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 645 MacroBuilder &Builder) const override { 646 if (Opts.POSIXThreads) 647 Builder.defineMacro("_REENTRANT"); 648 if (Opts.CPlusPlus) 649 Builder.defineMacro("_GNU_SOURCE"); 650 651 DefineStd(Builder, "unix", Opts); 652 Builder.defineMacro("__ELF__"); 653 Builder.defineMacro("__native_client__"); 654 } 655 656 public: 657 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 658 this->UserLabelPrefix = ""; 659 this->LongAlign = 32; 660 this->LongWidth = 32; 661 this->PointerAlign = 32; 662 this->PointerWidth = 32; 663 this->IntMaxType = TargetInfo::SignedLongLong; 664 this->Int64Type = TargetInfo::SignedLongLong; 665 this->DoubleAlign = 64; 666 this->LongDoubleWidth = 64; 667 this->LongDoubleAlign = 64; 668 this->LongLongWidth = 64; 669 this->LongLongAlign = 64; 670 this->SizeType = TargetInfo::UnsignedInt; 671 this->PtrDiffType = TargetInfo::SignedInt; 672 this->IntPtrType = TargetInfo::SignedInt; 673 // RegParmMax is inherited from the underlying architecture 674 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 675 if (Triple.getArch() == llvm::Triple::arm) { 676 this->DescriptionString = 677 "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 678 } else if (Triple.getArch() == llvm::Triple::x86) { 679 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 680 } else if (Triple.getArch() == llvm::Triple::x86_64) { 681 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 682 } else if (Triple.getArch() == llvm::Triple::mipsel) { 683 // Handled on mips' setDescriptionString. 684 } else { 685 assert(Triple.getArch() == llvm::Triple::le32); 686 this->DescriptionString = "e-p:32:32-i64:64"; 687 } 688 } 689 }; 690 } // end anonymous namespace. 691 692 //===----------------------------------------------------------------------===// 693 // Specific target implementations. 694 //===----------------------------------------------------------------------===// 695 696 namespace { 697 // PPC abstract base class 698 class PPCTargetInfo : public TargetInfo { 699 static const Builtin::Info BuiltinInfo[]; 700 static const char * const GCCRegNames[]; 701 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 702 std::string CPU; 703 704 // Target cpu features. 705 bool HasVSX; 706 bool HasP8Vector; 707 708 protected: 709 std::string ABI; 710 711 public: 712 PPCTargetInfo(const llvm::Triple &Triple) 713 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false) { 714 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 715 LongDoubleWidth = LongDoubleAlign = 128; 716 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 717 } 718 719 /// \brief Flags for architecture specific defines. 720 typedef enum { 721 ArchDefineNone = 0, 722 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 723 ArchDefinePpcgr = 1 << 1, 724 ArchDefinePpcsq = 1 << 2, 725 ArchDefine440 = 1 << 3, 726 ArchDefine603 = 1 << 4, 727 ArchDefine604 = 1 << 5, 728 ArchDefinePwr4 = 1 << 6, 729 ArchDefinePwr5 = 1 << 7, 730 ArchDefinePwr5x = 1 << 8, 731 ArchDefinePwr6 = 1 << 9, 732 ArchDefinePwr6x = 1 << 10, 733 ArchDefinePwr7 = 1 << 11, 734 ArchDefinePwr8 = 1 << 12, 735 ArchDefineA2 = 1 << 13, 736 ArchDefineA2q = 1 << 14 737 } ArchDefineTypes; 738 739 // Note: GCC recognizes the following additional cpus: 740 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 741 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 742 // titan, rs64. 743 bool setCPU(const std::string &Name) override { 744 bool CPUKnown = llvm::StringSwitch<bool>(Name) 745 .Case("generic", true) 746 .Case("440", true) 747 .Case("450", true) 748 .Case("601", true) 749 .Case("602", true) 750 .Case("603", true) 751 .Case("603e", true) 752 .Case("603ev", true) 753 .Case("604", true) 754 .Case("604e", true) 755 .Case("620", true) 756 .Case("630", true) 757 .Case("g3", true) 758 .Case("7400", true) 759 .Case("g4", true) 760 .Case("7450", true) 761 .Case("g4+", true) 762 .Case("750", true) 763 .Case("970", true) 764 .Case("g5", true) 765 .Case("a2", true) 766 .Case("a2q", true) 767 .Case("e500mc", true) 768 .Case("e5500", true) 769 .Case("power3", true) 770 .Case("pwr3", true) 771 .Case("power4", true) 772 .Case("pwr4", true) 773 .Case("power5", true) 774 .Case("pwr5", true) 775 .Case("power5x", true) 776 .Case("pwr5x", true) 777 .Case("power6", true) 778 .Case("pwr6", true) 779 .Case("power6x", true) 780 .Case("pwr6x", true) 781 .Case("power7", true) 782 .Case("pwr7", true) 783 .Case("power8", true) 784 .Case("pwr8", true) 785 .Case("powerpc", true) 786 .Case("ppc", true) 787 .Case("powerpc64", true) 788 .Case("ppc64", true) 789 .Case("powerpc64le", true) 790 .Case("ppc64le", true) 791 .Default(false); 792 793 if (CPUKnown) 794 CPU = Name; 795 796 return CPUKnown; 797 } 798 799 800 StringRef getABI() const override { return ABI; } 801 802 void getTargetBuiltins(const Builtin::Info *&Records, 803 unsigned &NumRecords) const override { 804 Records = BuiltinInfo; 805 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 806 } 807 808 bool isCLZForZeroUndef() const override { return false; } 809 810 void getTargetDefines(const LangOptions &Opts, 811 MacroBuilder &Builder) const override; 812 813 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 814 815 bool handleTargetFeatures(std::vector<std::string> &Features, 816 DiagnosticsEngine &Diags) override; 817 bool hasFeature(StringRef Feature) const override; 818 819 void getGCCRegNames(const char * const *&Names, 820 unsigned &NumNames) const override; 821 void getGCCRegAliases(const GCCRegAlias *&Aliases, 822 unsigned &NumAliases) const override; 823 bool validateAsmConstraint(const char *&Name, 824 TargetInfo::ConstraintInfo &Info) const override { 825 switch (*Name) { 826 default: return false; 827 case 'O': // Zero 828 break; 829 case 'b': // Base register 830 case 'f': // Floating point register 831 Info.setAllowsRegister(); 832 break; 833 // FIXME: The following are added to allow parsing. 834 // I just took a guess at what the actions should be. 835 // Also, is more specific checking needed? I.e. specific registers? 836 case 'd': // Floating point register (containing 64-bit value) 837 case 'v': // Altivec vector register 838 Info.setAllowsRegister(); 839 break; 840 case 'w': 841 switch (Name[1]) { 842 case 'd':// VSX vector register to hold vector double data 843 case 'f':// VSX vector register to hold vector float data 844 case 's':// VSX vector register to hold scalar float data 845 case 'a':// Any VSX register 846 case 'c':// An individual CR bit 847 break; 848 default: 849 return false; 850 } 851 Info.setAllowsRegister(); 852 Name++; // Skip over 'w'. 853 break; 854 case 'h': // `MQ', `CTR', or `LINK' register 855 case 'q': // `MQ' register 856 case 'c': // `CTR' register 857 case 'l': // `LINK' register 858 case 'x': // `CR' register (condition register) number 0 859 case 'y': // `CR' register (condition register) 860 case 'z': // `XER[CA]' carry bit (part of the XER register) 861 Info.setAllowsRegister(); 862 break; 863 case 'I': // Signed 16-bit constant 864 case 'J': // Unsigned 16-bit constant shifted left 16 bits 865 // (use `L' instead for SImode constants) 866 case 'K': // Unsigned 16-bit constant 867 case 'L': // Signed 16-bit constant shifted left 16 bits 868 case 'M': // Constant larger than 31 869 case 'N': // Exact power of 2 870 case 'P': // Constant whose negation is a signed 16-bit constant 871 case 'G': // Floating point constant that can be loaded into a 872 // register with one instruction per word 873 case 'H': // Integer/Floating point constant that can be loaded 874 // into a register using three instructions 875 break; 876 case 'm': // Memory operand. Note that on PowerPC targets, m can 877 // include addresses that update the base register. It 878 // is therefore only safe to use `m' in an asm statement 879 // if that asm statement accesses the operand exactly once. 880 // The asm statement must also use `%U<opno>' as a 881 // placeholder for the "update" flag in the corresponding 882 // load or store instruction. For example: 883 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 884 // is correct but: 885 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 886 // is not. Use es rather than m if you don't want the base 887 // register to be updated. 888 case 'e': 889 if (Name[1] != 's') 890 return false; 891 // es: A "stable" memory operand; that is, one which does not 892 // include any automodification of the base register. Unlike 893 // `m', this constraint can be used in asm statements that 894 // might access the operand several times, or that might not 895 // access it at all. 896 Info.setAllowsMemory(); 897 Name++; // Skip over 'e'. 898 break; 899 case 'Q': // Memory operand that is an offset from a register (it is 900 // usually better to use `m' or `es' in asm statements) 901 case 'Z': // Memory operand that is an indexed or indirect from a 902 // register (it is usually better to use `m' or `es' in 903 // asm statements) 904 Info.setAllowsMemory(); 905 Info.setAllowsRegister(); 906 break; 907 case 'R': // AIX TOC entry 908 case 'a': // Address operand that is an indexed or indirect from a 909 // register (`p' is preferable for asm statements) 910 case 'S': // Constant suitable as a 64-bit mask operand 911 case 'T': // Constant suitable as a 32-bit mask operand 912 case 'U': // System V Release 4 small data area reference 913 case 't': // AND masks that can be performed by two rldic{l, r} 914 // instructions 915 case 'W': // Vector constant that does not require memory 916 case 'j': // Vector constant that is all zeros. 917 break; 918 // End FIXME. 919 } 920 return true; 921 } 922 std::string convertConstraint(const char *&Constraint) const override { 923 std::string R; 924 switch (*Constraint) { 925 case 'e': 926 case 'w': 927 // Two-character constraint; add "^" hint for later parsing. 928 R = std::string("^") + std::string(Constraint, 2); 929 Constraint++; 930 break; 931 default: 932 return TargetInfo::convertConstraint(Constraint); 933 } 934 return R; 935 } 936 const char *getClobbers() const override { 937 return ""; 938 } 939 int getEHDataRegisterNumber(unsigned RegNo) const override { 940 if (RegNo == 0) return 3; 941 if (RegNo == 1) return 4; 942 return -1; 943 } 944 }; 945 946 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 947 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 948 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 949 ALL_LANGUAGES }, 950 #include "clang/Basic/BuiltinsPPC.def" 951 }; 952 953 /// handleTargetFeatures - Perform initialization based on the user 954 /// configured set of features. 955 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 956 DiagnosticsEngine &Diags) { 957 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 958 // Ignore disabled features. 959 if (Features[i][0] == '-') 960 continue; 961 962 StringRef Feature = StringRef(Features[i]).substr(1); 963 964 if (Feature == "vsx") { 965 HasVSX = true; 966 continue; 967 } 968 969 if (Feature == "power8-vector") { 970 HasP8Vector = true; 971 continue; 972 } 973 974 // TODO: Finish this list and add an assert that we've handled them 975 // all. 976 } 977 978 return true; 979 } 980 981 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 982 /// #defines that are not tied to a specific subtarget. 983 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 984 MacroBuilder &Builder) const { 985 // Target identification. 986 Builder.defineMacro("__ppc__"); 987 Builder.defineMacro("__PPC__"); 988 Builder.defineMacro("_ARCH_PPC"); 989 Builder.defineMacro("__powerpc__"); 990 Builder.defineMacro("__POWERPC__"); 991 if (PointerWidth == 64) { 992 Builder.defineMacro("_ARCH_PPC64"); 993 Builder.defineMacro("__powerpc64__"); 994 Builder.defineMacro("__ppc64__"); 995 Builder.defineMacro("__PPC64__"); 996 } 997 998 // Target properties. 999 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1000 Builder.defineMacro("_LITTLE_ENDIAN"); 1001 } else { 1002 if (getTriple().getOS() != llvm::Triple::NetBSD && 1003 getTriple().getOS() != llvm::Triple::OpenBSD) 1004 Builder.defineMacro("_BIG_ENDIAN"); 1005 } 1006 1007 // ABI options. 1008 if (ABI == "elfv1") 1009 Builder.defineMacro("_CALL_ELF", "1"); 1010 if (ABI == "elfv2") 1011 Builder.defineMacro("_CALL_ELF", "2"); 1012 1013 // Subtarget options. 1014 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1015 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1016 1017 // FIXME: Should be controlled by command line option. 1018 if (LongDoubleWidth == 128) 1019 Builder.defineMacro("__LONG_DOUBLE_128__"); 1020 1021 if (Opts.AltiVec) { 1022 Builder.defineMacro("__VEC__", "10206"); 1023 Builder.defineMacro("__ALTIVEC__"); 1024 } 1025 1026 // CPU identification. 1027 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1028 .Case("440", ArchDefineName) 1029 .Case("450", ArchDefineName | ArchDefine440) 1030 .Case("601", ArchDefineName) 1031 .Case("602", ArchDefineName | ArchDefinePpcgr) 1032 .Case("603", ArchDefineName | ArchDefinePpcgr) 1033 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1034 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1035 .Case("604", ArchDefineName | ArchDefinePpcgr) 1036 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1037 .Case("620", ArchDefineName | ArchDefinePpcgr) 1038 .Case("630", ArchDefineName | ArchDefinePpcgr) 1039 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1040 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1041 .Case("750", ArchDefineName | ArchDefinePpcgr) 1042 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1043 | ArchDefinePpcsq) 1044 .Case("a2", ArchDefineA2) 1045 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1046 .Case("pwr3", ArchDefinePpcgr) 1047 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1048 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1049 | ArchDefinePpcsq) 1050 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1051 | ArchDefinePpcgr | ArchDefinePpcsq) 1052 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1053 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1054 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1055 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1056 | ArchDefinePpcsq) 1057 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1058 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1059 | ArchDefinePpcgr | ArchDefinePpcsq) 1060 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1061 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1062 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1063 .Case("power3", ArchDefinePpcgr) 1064 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1065 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1066 | ArchDefinePpcsq) 1067 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1068 | ArchDefinePpcgr | ArchDefinePpcsq) 1069 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1070 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1071 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1072 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1073 | ArchDefinePpcsq) 1074 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1075 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1076 | ArchDefinePpcgr | ArchDefinePpcsq) 1077 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1078 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1079 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1080 .Default(ArchDefineNone); 1081 1082 if (defs & ArchDefineName) 1083 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1084 if (defs & ArchDefinePpcgr) 1085 Builder.defineMacro("_ARCH_PPCGR"); 1086 if (defs & ArchDefinePpcsq) 1087 Builder.defineMacro("_ARCH_PPCSQ"); 1088 if (defs & ArchDefine440) 1089 Builder.defineMacro("_ARCH_440"); 1090 if (defs & ArchDefine603) 1091 Builder.defineMacro("_ARCH_603"); 1092 if (defs & ArchDefine604) 1093 Builder.defineMacro("_ARCH_604"); 1094 if (defs & ArchDefinePwr4) 1095 Builder.defineMacro("_ARCH_PWR4"); 1096 if (defs & ArchDefinePwr5) 1097 Builder.defineMacro("_ARCH_PWR5"); 1098 if (defs & ArchDefinePwr5x) 1099 Builder.defineMacro("_ARCH_PWR5X"); 1100 if (defs & ArchDefinePwr6) 1101 Builder.defineMacro("_ARCH_PWR6"); 1102 if (defs & ArchDefinePwr6x) 1103 Builder.defineMacro("_ARCH_PWR6X"); 1104 if (defs & ArchDefinePwr7) 1105 Builder.defineMacro("_ARCH_PWR7"); 1106 if (defs & ArchDefinePwr8) 1107 Builder.defineMacro("_ARCH_PWR8"); 1108 if (defs & ArchDefineA2) 1109 Builder.defineMacro("_ARCH_A2"); 1110 if (defs & ArchDefineA2q) { 1111 Builder.defineMacro("_ARCH_A2Q"); 1112 Builder.defineMacro("_ARCH_QP"); 1113 } 1114 1115 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1116 Builder.defineMacro("__bg__"); 1117 Builder.defineMacro("__THW_BLUEGENE__"); 1118 Builder.defineMacro("__bgq__"); 1119 Builder.defineMacro("__TOS_BGQ__"); 1120 } 1121 1122 if (HasVSX) 1123 Builder.defineMacro("__VSX__"); 1124 if (HasP8Vector) 1125 Builder.defineMacro("__POWER8_VECTOR__"); 1126 1127 // FIXME: The following are not yet generated here by Clang, but are 1128 // generated by GCC: 1129 // 1130 // _SOFT_FLOAT_ 1131 // __RECIP_PRECISION__ 1132 // __APPLE_ALTIVEC__ 1133 // __RECIP__ 1134 // __RECIPF__ 1135 // __RSQRTE__ 1136 // __RSQRTEF__ 1137 // _SOFT_DOUBLE_ 1138 // __NO_LWSYNC__ 1139 // __HAVE_BSWAP__ 1140 // __LONGDOUBLE128 1141 // __CMODEL_MEDIUM__ 1142 // __CMODEL_LARGE__ 1143 // _CALL_SYSV 1144 // _CALL_DARWIN 1145 // __NO_FPRS__ 1146 } 1147 1148 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1149 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1150 .Case("7400", true) 1151 .Case("g4", true) 1152 .Case("7450", true) 1153 .Case("g4+", true) 1154 .Case("970", true) 1155 .Case("g5", true) 1156 .Case("pwr6", true) 1157 .Case("pwr7", true) 1158 .Case("pwr8", true) 1159 .Case("ppc64", true) 1160 .Case("ppc64le", true) 1161 .Default(false); 1162 1163 Features["qpx"] = (CPU == "a2q"); 1164 } 1165 1166 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1167 return llvm::StringSwitch<bool>(Feature) 1168 .Case("powerpc", true) 1169 .Case("vsx", HasVSX) 1170 .Case("power8-vector", HasP8Vector) 1171 .Default(false); 1172 } 1173 1174 const char * const PPCTargetInfo::GCCRegNames[] = { 1175 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1176 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1177 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1178 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1179 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1180 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1181 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1182 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1183 "mq", "lr", "ctr", "ap", 1184 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1185 "xer", 1186 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1187 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1188 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1189 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1190 "vrsave", "vscr", 1191 "spe_acc", "spefscr", 1192 "sfp" 1193 }; 1194 1195 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1196 unsigned &NumNames) const { 1197 Names = GCCRegNames; 1198 NumNames = llvm::array_lengthof(GCCRegNames); 1199 } 1200 1201 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1202 // While some of these aliases do map to different registers 1203 // they still share the same register name. 1204 { { "0" }, "r0" }, 1205 { { "1"}, "r1" }, 1206 { { "2" }, "r2" }, 1207 { { "3" }, "r3" }, 1208 { { "4" }, "r4" }, 1209 { { "5" }, "r5" }, 1210 { { "6" }, "r6" }, 1211 { { "7" }, "r7" }, 1212 { { "8" }, "r8" }, 1213 { { "9" }, "r9" }, 1214 { { "10" }, "r10" }, 1215 { { "11" }, "r11" }, 1216 { { "12" }, "r12" }, 1217 { { "13" }, "r13" }, 1218 { { "14" }, "r14" }, 1219 { { "15" }, "r15" }, 1220 { { "16" }, "r16" }, 1221 { { "17" }, "r17" }, 1222 { { "18" }, "r18" }, 1223 { { "19" }, "r19" }, 1224 { { "20" }, "r20" }, 1225 { { "21" }, "r21" }, 1226 { { "22" }, "r22" }, 1227 { { "23" }, "r23" }, 1228 { { "24" }, "r24" }, 1229 { { "25" }, "r25" }, 1230 { { "26" }, "r26" }, 1231 { { "27" }, "r27" }, 1232 { { "28" }, "r28" }, 1233 { { "29" }, "r29" }, 1234 { { "30" }, "r30" }, 1235 { { "31" }, "r31" }, 1236 { { "fr0" }, "f0" }, 1237 { { "fr1" }, "f1" }, 1238 { { "fr2" }, "f2" }, 1239 { { "fr3" }, "f3" }, 1240 { { "fr4" }, "f4" }, 1241 { { "fr5" }, "f5" }, 1242 { { "fr6" }, "f6" }, 1243 { { "fr7" }, "f7" }, 1244 { { "fr8" }, "f8" }, 1245 { { "fr9" }, "f9" }, 1246 { { "fr10" }, "f10" }, 1247 { { "fr11" }, "f11" }, 1248 { { "fr12" }, "f12" }, 1249 { { "fr13" }, "f13" }, 1250 { { "fr14" }, "f14" }, 1251 { { "fr15" }, "f15" }, 1252 { { "fr16" }, "f16" }, 1253 { { "fr17" }, "f17" }, 1254 { { "fr18" }, "f18" }, 1255 { { "fr19" }, "f19" }, 1256 { { "fr20" }, "f20" }, 1257 { { "fr21" }, "f21" }, 1258 { { "fr22" }, "f22" }, 1259 { { "fr23" }, "f23" }, 1260 { { "fr24" }, "f24" }, 1261 { { "fr25" }, "f25" }, 1262 { { "fr26" }, "f26" }, 1263 { { "fr27" }, "f27" }, 1264 { { "fr28" }, "f28" }, 1265 { { "fr29" }, "f29" }, 1266 { { "fr30" }, "f30" }, 1267 { { "fr31" }, "f31" }, 1268 { { "cc" }, "cr0" }, 1269 }; 1270 1271 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1272 unsigned &NumAliases) const { 1273 Aliases = GCCRegAliases; 1274 NumAliases = llvm::array_lengthof(GCCRegAliases); 1275 } 1276 } // end anonymous namespace. 1277 1278 namespace { 1279 class PPC32TargetInfo : public PPCTargetInfo { 1280 public: 1281 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1282 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1283 1284 switch (getTriple().getOS()) { 1285 case llvm::Triple::Linux: 1286 case llvm::Triple::FreeBSD: 1287 case llvm::Triple::NetBSD: 1288 SizeType = UnsignedInt; 1289 PtrDiffType = SignedInt; 1290 IntPtrType = SignedInt; 1291 break; 1292 default: 1293 break; 1294 } 1295 1296 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1297 LongDoubleWidth = LongDoubleAlign = 64; 1298 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1299 } 1300 1301 // PPC32 supports atomics up to 4 bytes. 1302 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1303 } 1304 1305 BuiltinVaListKind getBuiltinVaListKind() const override { 1306 // This is the ELF definition, and is overridden by the Darwin sub-target 1307 return TargetInfo::PowerABIBuiltinVaList; 1308 } 1309 }; 1310 } // end anonymous namespace. 1311 1312 // Note: ABI differences may eventually require us to have a separate 1313 // TargetInfo for little endian. 1314 namespace { 1315 class PPC64TargetInfo : public PPCTargetInfo { 1316 public: 1317 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1318 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1319 IntMaxType = SignedLong; 1320 Int64Type = SignedLong; 1321 1322 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1323 DescriptionString = "e-m:e-i64:64-n32:64"; 1324 ABI = "elfv2"; 1325 } else { 1326 DescriptionString = "E-m:e-i64:64-n32:64"; 1327 ABI = "elfv1"; 1328 } 1329 1330 switch (getTriple().getOS()) { 1331 case llvm::Triple::FreeBSD: 1332 LongDoubleWidth = LongDoubleAlign = 64; 1333 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1334 break; 1335 case llvm::Triple::NetBSD: 1336 IntMaxType = SignedLongLong; 1337 Int64Type = SignedLongLong; 1338 break; 1339 default: 1340 break; 1341 } 1342 1343 // PPC64 supports atomics up to 8 bytes. 1344 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1345 } 1346 BuiltinVaListKind getBuiltinVaListKind() const override { 1347 return TargetInfo::CharPtrBuiltinVaList; 1348 } 1349 // PPC64 Linux-specifc ABI options. 1350 bool setABI(const std::string &Name) override { 1351 if (Name == "elfv1" || Name == "elfv2") { 1352 ABI = Name; 1353 return true; 1354 } 1355 return false; 1356 } 1357 }; 1358 } // end anonymous namespace. 1359 1360 1361 namespace { 1362 class DarwinPPC32TargetInfo : 1363 public DarwinTargetInfo<PPC32TargetInfo> { 1364 public: 1365 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1366 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1367 HasAlignMac68kSupport = true; 1368 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1369 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1370 LongLongAlign = 32; 1371 SuitableAlign = 128; 1372 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1373 } 1374 BuiltinVaListKind getBuiltinVaListKind() const override { 1375 return TargetInfo::CharPtrBuiltinVaList; 1376 } 1377 }; 1378 1379 class DarwinPPC64TargetInfo : 1380 public DarwinTargetInfo<PPC64TargetInfo> { 1381 public: 1382 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1383 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1384 HasAlignMac68kSupport = true; 1385 SuitableAlign = 128; 1386 DescriptionString = "E-m:o-i64:64-n32:64"; 1387 } 1388 }; 1389 } // end anonymous namespace. 1390 1391 namespace { 1392 static const unsigned NVPTXAddrSpaceMap[] = { 1393 1, // opencl_global 1394 3, // opencl_local 1395 4, // opencl_constant 1396 // FIXME: generic has to be added to the target 1397 0, // opencl_generic 1398 1, // cuda_device 1399 4, // cuda_constant 1400 3, // cuda_shared 1401 }; 1402 class NVPTXTargetInfo : public TargetInfo { 1403 static const char * const GCCRegNames[]; 1404 static const Builtin::Info BuiltinInfo[]; 1405 1406 // The GPU profiles supported by the NVPTX backend 1407 enum GPUKind { 1408 GK_NONE, 1409 GK_SM20, 1410 GK_SM21, 1411 GK_SM30, 1412 GK_SM35, 1413 } GPU; 1414 1415 public: 1416 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1417 BigEndian = false; 1418 TLSSupported = false; 1419 LongWidth = LongAlign = 64; 1420 AddrSpaceMap = &NVPTXAddrSpaceMap; 1421 UseAddrSpaceMapMangling = true; 1422 // Define available target features 1423 // These must be defined in sorted order! 1424 NoAsmVariants = true; 1425 // Set the default GPU to sm20 1426 GPU = GK_SM20; 1427 } 1428 void getTargetDefines(const LangOptions &Opts, 1429 MacroBuilder &Builder) const override { 1430 Builder.defineMacro("__PTX__"); 1431 Builder.defineMacro("__NVPTX__"); 1432 if (Opts.CUDAIsDevice) { 1433 // Set __CUDA_ARCH__ for the GPU specified. 1434 std::string CUDAArchCode; 1435 switch (GPU) { 1436 case GK_SM20: 1437 CUDAArchCode = "200"; 1438 break; 1439 case GK_SM21: 1440 CUDAArchCode = "210"; 1441 break; 1442 case GK_SM30: 1443 CUDAArchCode = "300"; 1444 break; 1445 case GK_SM35: 1446 CUDAArchCode = "350"; 1447 break; 1448 default: 1449 llvm_unreachable("Unhandled target CPU"); 1450 } 1451 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1452 } 1453 } 1454 void getTargetBuiltins(const Builtin::Info *&Records, 1455 unsigned &NumRecords) const override { 1456 Records = BuiltinInfo; 1457 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1458 } 1459 bool hasFeature(StringRef Feature) const override { 1460 return Feature == "ptx" || Feature == "nvptx"; 1461 } 1462 1463 void getGCCRegNames(const char * const *&Names, 1464 unsigned &NumNames) const override; 1465 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1466 unsigned &NumAliases) const override { 1467 // No aliases. 1468 Aliases = nullptr; 1469 NumAliases = 0; 1470 } 1471 bool 1472 validateAsmConstraint(const char *&Name, 1473 TargetInfo::ConstraintInfo &Info) const override { 1474 switch (*Name) { 1475 default: return false; 1476 case 'c': 1477 case 'h': 1478 case 'r': 1479 case 'l': 1480 case 'f': 1481 case 'd': 1482 Info.setAllowsRegister(); 1483 return true; 1484 } 1485 } 1486 const char *getClobbers() const override { 1487 // FIXME: Is this really right? 1488 return ""; 1489 } 1490 BuiltinVaListKind getBuiltinVaListKind() const override { 1491 // FIXME: implement 1492 return TargetInfo::CharPtrBuiltinVaList; 1493 } 1494 bool setCPU(const std::string &Name) override { 1495 GPU = llvm::StringSwitch<GPUKind>(Name) 1496 .Case("sm_20", GK_SM20) 1497 .Case("sm_21", GK_SM21) 1498 .Case("sm_30", GK_SM30) 1499 .Case("sm_35", GK_SM35) 1500 .Default(GK_NONE); 1501 1502 return GPU != GK_NONE; 1503 } 1504 }; 1505 1506 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1507 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1508 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1509 ALL_LANGUAGES }, 1510 #include "clang/Basic/BuiltinsNVPTX.def" 1511 }; 1512 1513 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1514 "r0" 1515 }; 1516 1517 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1518 unsigned &NumNames) const { 1519 Names = GCCRegNames; 1520 NumNames = llvm::array_lengthof(GCCRegNames); 1521 } 1522 1523 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1524 public: 1525 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1526 PointerWidth = PointerAlign = 32; 1527 SizeType = PtrDiffType = TargetInfo::UnsignedInt; 1528 IntPtrType = TargetInfo::SignedInt; 1529 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1530 } 1531 }; 1532 1533 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1534 public: 1535 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1536 PointerWidth = PointerAlign = 64; 1537 SizeType = PtrDiffType = TargetInfo::UnsignedLongLong; 1538 IntPtrType = TargetInfo::SignedLongLong; 1539 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1540 } 1541 }; 1542 } 1543 1544 namespace { 1545 1546 static const unsigned R600AddrSpaceMap[] = { 1547 1, // opencl_global 1548 3, // opencl_local 1549 2, // opencl_constant 1550 4, // opencl_generic 1551 1, // cuda_device 1552 2, // cuda_constant 1553 3 // cuda_shared 1554 }; 1555 1556 // If you edit the description strings, make sure you update 1557 // getPointerWidthV(). 1558 1559 static const char *DescriptionStringR600 = 1560 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1561 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1562 1563 static const char *DescriptionStringR600DoubleOps = 1564 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1565 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1566 1567 static const char *DescriptionStringSI = 1568 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1569 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1570 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1571 1572 class R600TargetInfo : public TargetInfo { 1573 static const Builtin::Info BuiltinInfo[]; 1574 1575 /// \brief The GPU profiles supported by the R600 target. 1576 enum GPUKind { 1577 GK_NONE, 1578 GK_R600, 1579 GK_R600_DOUBLE_OPS, 1580 GK_R700, 1581 GK_R700_DOUBLE_OPS, 1582 GK_EVERGREEN, 1583 GK_EVERGREEN_DOUBLE_OPS, 1584 GK_NORTHERN_ISLANDS, 1585 GK_CAYMAN, 1586 GK_SOUTHERN_ISLANDS, 1587 GK_SEA_ISLANDS 1588 } GPU; 1589 1590 public: 1591 R600TargetInfo(const llvm::Triple &Triple) 1592 : TargetInfo(Triple) { 1593 1594 if (Triple.getArch() == llvm::Triple::amdgcn) { 1595 DescriptionString = DescriptionStringSI; 1596 GPU = GK_SOUTHERN_ISLANDS; 1597 } else { 1598 DescriptionString = DescriptionStringR600; 1599 GPU = GK_R600; 1600 } 1601 AddrSpaceMap = &R600AddrSpaceMap; 1602 UseAddrSpaceMapMangling = true; 1603 } 1604 1605 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1606 if (GPU <= GK_CAYMAN) 1607 return 32; 1608 1609 switch(AddrSpace) { 1610 default: 1611 return 64; 1612 case 0: 1613 case 3: 1614 case 5: 1615 return 32; 1616 } 1617 } 1618 1619 const char * getClobbers() const override { 1620 return ""; 1621 } 1622 1623 void getGCCRegNames(const char * const *&Names, 1624 unsigned &numNames) const override { 1625 Names = nullptr; 1626 numNames = 0; 1627 } 1628 1629 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1630 unsigned &NumAliases) const override { 1631 Aliases = nullptr; 1632 NumAliases = 0; 1633 } 1634 1635 bool validateAsmConstraint(const char *&Name, 1636 TargetInfo::ConstraintInfo &info) const override { 1637 return true; 1638 } 1639 1640 void getTargetBuiltins(const Builtin::Info *&Records, 1641 unsigned &NumRecords) const override { 1642 Records = BuiltinInfo; 1643 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin; 1644 } 1645 1646 void getTargetDefines(const LangOptions &Opts, 1647 MacroBuilder &Builder) const override { 1648 Builder.defineMacro("__R600__"); 1649 } 1650 1651 BuiltinVaListKind getBuiltinVaListKind() const override { 1652 return TargetInfo::CharPtrBuiltinVaList; 1653 } 1654 1655 bool setCPU(const std::string &Name) override { 1656 GPU = llvm::StringSwitch<GPUKind>(Name) 1657 .Case("r600" , GK_R600) 1658 .Case("rv610", GK_R600) 1659 .Case("rv620", GK_R600) 1660 .Case("rv630", GK_R600) 1661 .Case("rv635", GK_R600) 1662 .Case("rs780", GK_R600) 1663 .Case("rs880", GK_R600) 1664 .Case("rv670", GK_R600_DOUBLE_OPS) 1665 .Case("rv710", GK_R700) 1666 .Case("rv730", GK_R700) 1667 .Case("rv740", GK_R700_DOUBLE_OPS) 1668 .Case("rv770", GK_R700_DOUBLE_OPS) 1669 .Case("palm", GK_EVERGREEN) 1670 .Case("cedar", GK_EVERGREEN) 1671 .Case("sumo", GK_EVERGREEN) 1672 .Case("sumo2", GK_EVERGREEN) 1673 .Case("redwood", GK_EVERGREEN) 1674 .Case("juniper", GK_EVERGREEN) 1675 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1676 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1677 .Case("barts", GK_NORTHERN_ISLANDS) 1678 .Case("turks", GK_NORTHERN_ISLANDS) 1679 .Case("caicos", GK_NORTHERN_ISLANDS) 1680 .Case("cayman", GK_CAYMAN) 1681 .Case("aruba", GK_CAYMAN) 1682 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1683 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1684 .Case("verde", GK_SOUTHERN_ISLANDS) 1685 .Case("oland", GK_SOUTHERN_ISLANDS) 1686 .Case("hainan", GK_SOUTHERN_ISLANDS) 1687 .Case("bonaire", GK_SEA_ISLANDS) 1688 .Case("kabini", GK_SEA_ISLANDS) 1689 .Case("kaveri", GK_SEA_ISLANDS) 1690 .Case("hawaii", GK_SEA_ISLANDS) 1691 .Case("mullins", GK_SEA_ISLANDS) 1692 .Default(GK_NONE); 1693 1694 if (GPU == GK_NONE) { 1695 return false; 1696 } 1697 1698 // Set the correct data layout 1699 switch (GPU) { 1700 case GK_NONE: 1701 case GK_R600: 1702 case GK_R700: 1703 case GK_EVERGREEN: 1704 case GK_NORTHERN_ISLANDS: 1705 DescriptionString = DescriptionStringR600; 1706 break; 1707 case GK_R600_DOUBLE_OPS: 1708 case GK_R700_DOUBLE_OPS: 1709 case GK_EVERGREEN_DOUBLE_OPS: 1710 case GK_CAYMAN: 1711 DescriptionString = DescriptionStringR600DoubleOps; 1712 break; 1713 case GK_SOUTHERN_ISLANDS: 1714 case GK_SEA_ISLANDS: 1715 DescriptionString = DescriptionStringSI; 1716 break; 1717 } 1718 1719 return true; 1720 } 1721 }; 1722 1723 const Builtin::Info R600TargetInfo::BuiltinInfo[] = { 1724 #define BUILTIN(ID, TYPE, ATTRS) \ 1725 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1726 #include "clang/Basic/BuiltinsR600.def" 1727 }; 1728 1729 } // end anonymous namespace 1730 1731 namespace { 1732 // Namespace for x86 abstract base class 1733 const Builtin::Info BuiltinInfo[] = { 1734 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1735 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1736 ALL_LANGUAGES }, 1737 #include "clang/Basic/BuiltinsX86.def" 1738 }; 1739 1740 static const char* const GCCRegNames[] = { 1741 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1742 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1743 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1744 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1745 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1746 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1747 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1748 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1749 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1750 }; 1751 1752 const TargetInfo::AddlRegName AddlRegNames[] = { 1753 { { "al", "ah", "eax", "rax" }, 0 }, 1754 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1755 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1756 { { "dl", "dh", "edx", "rdx" }, 1 }, 1757 { { "esi", "rsi" }, 4 }, 1758 { { "edi", "rdi" }, 5 }, 1759 { { "esp", "rsp" }, 7 }, 1760 { { "ebp", "rbp" }, 6 }, 1761 }; 1762 1763 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1764 // most of the implementation can be shared. 1765 class X86TargetInfo : public TargetInfo { 1766 enum X86SSEEnum { 1767 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1768 } SSELevel; 1769 enum MMX3DNowEnum { 1770 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1771 } MMX3DNowLevel; 1772 enum XOPEnum { 1773 NoXOP, 1774 SSE4A, 1775 FMA4, 1776 XOP 1777 } XOPLevel; 1778 1779 bool HasAES; 1780 bool HasPCLMUL; 1781 bool HasLZCNT; 1782 bool HasRDRND; 1783 bool HasFSGSBASE; 1784 bool HasBMI; 1785 bool HasBMI2; 1786 bool HasPOPCNT; 1787 bool HasRTM; 1788 bool HasPRFCHW; 1789 bool HasRDSEED; 1790 bool HasADX; 1791 bool HasTBM; 1792 bool HasFMA; 1793 bool HasF16C; 1794 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 1795 HasAVX512VL; 1796 bool HasSHA; 1797 bool HasCX16; 1798 1799 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1800 /// 1801 /// Each enumeration represents a particular CPU supported by Clang. These 1802 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1803 enum CPUKind { 1804 CK_Generic, 1805 1806 /// \name i386 1807 /// i386-generation processors. 1808 //@{ 1809 CK_i386, 1810 //@} 1811 1812 /// \name i486 1813 /// i486-generation processors. 1814 //@{ 1815 CK_i486, 1816 CK_WinChipC6, 1817 CK_WinChip2, 1818 CK_C3, 1819 //@} 1820 1821 /// \name i586 1822 /// i586-generation processors, P5 microarchitecture based. 1823 //@{ 1824 CK_i586, 1825 CK_Pentium, 1826 CK_PentiumMMX, 1827 //@} 1828 1829 /// \name i686 1830 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1831 //@{ 1832 CK_i686, 1833 CK_PentiumPro, 1834 CK_Pentium2, 1835 CK_Pentium3, 1836 CK_Pentium3M, 1837 CK_PentiumM, 1838 CK_C3_2, 1839 1840 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1841 /// Clang however has some logic to suport this. 1842 // FIXME: Warn, deprecate, and potentially remove this. 1843 CK_Yonah, 1844 //@} 1845 1846 /// \name Netburst 1847 /// Netburst microarchitecture based processors. 1848 //@{ 1849 CK_Pentium4, 1850 CK_Pentium4M, 1851 CK_Prescott, 1852 CK_Nocona, 1853 //@} 1854 1855 /// \name Core 1856 /// Core microarchitecture based processors. 1857 //@{ 1858 CK_Core2, 1859 1860 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1861 /// codename which GCC no longer accepts as an option to -march, but Clang 1862 /// has some logic for recognizing it. 1863 // FIXME: Warn, deprecate, and potentially remove this. 1864 CK_Penryn, 1865 //@} 1866 1867 /// \name Atom 1868 /// Atom processors 1869 //@{ 1870 CK_Bonnell, 1871 CK_Silvermont, 1872 //@} 1873 1874 /// \name Nehalem 1875 /// Nehalem microarchitecture based processors. 1876 CK_Nehalem, 1877 1878 /// \name Westmere 1879 /// Westmere microarchitecture based processors. 1880 CK_Westmere, 1881 1882 /// \name Sandy Bridge 1883 /// Sandy Bridge microarchitecture based processors. 1884 CK_SandyBridge, 1885 1886 /// \name Ivy Bridge 1887 /// Ivy Bridge microarchitecture based processors. 1888 CK_IvyBridge, 1889 1890 /// \name Haswell 1891 /// Haswell microarchitecture based processors. 1892 CK_Haswell, 1893 1894 /// \name Broadwell 1895 /// Broadwell microarchitecture based processors. 1896 CK_Broadwell, 1897 1898 /// \name Skylake 1899 /// Skylake microarchitecture based processors. 1900 CK_Skylake, 1901 1902 /// \name Knights Landing 1903 /// Knights Landing processor. 1904 CK_KNL, 1905 1906 /// \name K6 1907 /// K6 architecture processors. 1908 //@{ 1909 CK_K6, 1910 CK_K6_2, 1911 CK_K6_3, 1912 //@} 1913 1914 /// \name K7 1915 /// K7 architecture processors. 1916 //@{ 1917 CK_Athlon, 1918 CK_AthlonThunderbird, 1919 CK_Athlon4, 1920 CK_AthlonXP, 1921 CK_AthlonMP, 1922 //@} 1923 1924 /// \name K8 1925 /// K8 architecture processors. 1926 //@{ 1927 CK_Athlon64, 1928 CK_Athlon64SSE3, 1929 CK_AthlonFX, 1930 CK_K8, 1931 CK_K8SSE3, 1932 CK_Opteron, 1933 CK_OpteronSSE3, 1934 CK_AMDFAM10, 1935 //@} 1936 1937 /// \name Bobcat 1938 /// Bobcat architecture processors. 1939 //@{ 1940 CK_BTVER1, 1941 CK_BTVER2, 1942 //@} 1943 1944 /// \name Bulldozer 1945 /// Bulldozer architecture processors. 1946 //@{ 1947 CK_BDVER1, 1948 CK_BDVER2, 1949 CK_BDVER3, 1950 CK_BDVER4, 1951 //@} 1952 1953 /// This specification is deprecated and will be removed in the future. 1954 /// Users should prefer \see CK_K8. 1955 // FIXME: Warn on this when the CPU is set to it. 1956 //@{ 1957 CK_x86_64, 1958 //@} 1959 1960 /// \name Geode 1961 /// Geode processors. 1962 //@{ 1963 CK_Geode 1964 //@} 1965 } CPU; 1966 1967 enum FPMathKind { 1968 FP_Default, 1969 FP_SSE, 1970 FP_387 1971 } FPMath; 1972 1973 public: 1974 X86TargetInfo(const llvm::Triple &Triple) 1975 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1976 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1977 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 1978 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 1979 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 1980 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 1981 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 1982 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 1983 BigEndian = false; 1984 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1985 } 1986 unsigned getFloatEvalMethod() const override { 1987 // X87 evaluates with 80 bits "long double" precision. 1988 return SSELevel == NoSSE ? 2 : 0; 1989 } 1990 void getTargetBuiltins(const Builtin::Info *&Records, 1991 unsigned &NumRecords) const override { 1992 Records = BuiltinInfo; 1993 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1994 } 1995 void getGCCRegNames(const char * const *&Names, 1996 unsigned &NumNames) const override { 1997 Names = GCCRegNames; 1998 NumNames = llvm::array_lengthof(GCCRegNames); 1999 } 2000 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2001 unsigned &NumAliases) const override { 2002 Aliases = nullptr; 2003 NumAliases = 0; 2004 } 2005 void getGCCAddlRegNames(const AddlRegName *&Names, 2006 unsigned &NumNames) const override { 2007 Names = AddlRegNames; 2008 NumNames = llvm::array_lengthof(AddlRegNames); 2009 } 2010 bool validateAsmConstraint(const char *&Name, 2011 TargetInfo::ConstraintInfo &info) const override; 2012 2013 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2014 2015 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2016 2017 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2018 2019 std::string convertConstraint(const char *&Constraint) const override; 2020 const char *getClobbers() const override { 2021 return "~{dirflag},~{fpsr},~{flags}"; 2022 } 2023 void getTargetDefines(const LangOptions &Opts, 2024 MacroBuilder &Builder) const override; 2025 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2026 bool Enabled); 2027 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2028 bool Enabled); 2029 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2030 bool Enabled); 2031 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2032 StringRef Name, bool Enabled) const override { 2033 setFeatureEnabledImpl(Features, Name, Enabled); 2034 } 2035 // This exists purely to cut down on the number of virtual calls in 2036 // getDefaultFeatures which calls this repeatedly. 2037 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2038 StringRef Name, bool Enabled); 2039 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 2040 bool hasFeature(StringRef Feature) const override; 2041 bool handleTargetFeatures(std::vector<std::string> &Features, 2042 DiagnosticsEngine &Diags) override; 2043 StringRef getABI() const override { 2044 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2045 return "avx"; 2046 else if (getTriple().getArch() == llvm::Triple::x86 && 2047 MMX3DNowLevel == NoMMX3DNow) 2048 return "no-mmx"; 2049 return ""; 2050 } 2051 bool setCPU(const std::string &Name) override { 2052 CPU = llvm::StringSwitch<CPUKind>(Name) 2053 .Case("i386", CK_i386) 2054 .Case("i486", CK_i486) 2055 .Case("winchip-c6", CK_WinChipC6) 2056 .Case("winchip2", CK_WinChip2) 2057 .Case("c3", CK_C3) 2058 .Case("i586", CK_i586) 2059 .Case("pentium", CK_Pentium) 2060 .Case("pentium-mmx", CK_PentiumMMX) 2061 .Case("i686", CK_i686) 2062 .Case("pentiumpro", CK_PentiumPro) 2063 .Case("pentium2", CK_Pentium2) 2064 .Case("pentium3", CK_Pentium3) 2065 .Case("pentium3m", CK_Pentium3M) 2066 .Case("pentium-m", CK_PentiumM) 2067 .Case("c3-2", CK_C3_2) 2068 .Case("yonah", CK_Yonah) 2069 .Case("pentium4", CK_Pentium4) 2070 .Case("pentium4m", CK_Pentium4M) 2071 .Case("prescott", CK_Prescott) 2072 .Case("nocona", CK_Nocona) 2073 .Case("core2", CK_Core2) 2074 .Case("penryn", CK_Penryn) 2075 .Case("bonnell", CK_Bonnell) 2076 .Case("atom", CK_Bonnell) // Legacy name. 2077 .Case("silvermont", CK_Silvermont) 2078 .Case("slm", CK_Silvermont) // Legacy name. 2079 .Case("nehalem", CK_Nehalem) 2080 .Case("corei7", CK_Nehalem) // Legacy name. 2081 .Case("westmere", CK_Westmere) 2082 .Case("sandybridge", CK_SandyBridge) 2083 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2084 .Case("ivybridge", CK_IvyBridge) 2085 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2086 .Case("haswell", CK_Haswell) 2087 .Case("core-avx2", CK_Haswell) // Legacy name. 2088 .Case("broadwell", CK_Broadwell) 2089 .Case("skylake", CK_Skylake) 2090 .Case("skx", CK_Skylake) // Legacy name. 2091 .Case("knl", CK_KNL) 2092 .Case("k6", CK_K6) 2093 .Case("k6-2", CK_K6_2) 2094 .Case("k6-3", CK_K6_3) 2095 .Case("athlon", CK_Athlon) 2096 .Case("athlon-tbird", CK_AthlonThunderbird) 2097 .Case("athlon-4", CK_Athlon4) 2098 .Case("athlon-xp", CK_AthlonXP) 2099 .Case("athlon-mp", CK_AthlonMP) 2100 .Case("athlon64", CK_Athlon64) 2101 .Case("athlon64-sse3", CK_Athlon64SSE3) 2102 .Case("athlon-fx", CK_AthlonFX) 2103 .Case("k8", CK_K8) 2104 .Case("k8-sse3", CK_K8SSE3) 2105 .Case("opteron", CK_Opteron) 2106 .Case("opteron-sse3", CK_OpteronSSE3) 2107 .Case("barcelona", CK_AMDFAM10) 2108 .Case("amdfam10", CK_AMDFAM10) 2109 .Case("btver1", CK_BTVER1) 2110 .Case("btver2", CK_BTVER2) 2111 .Case("bdver1", CK_BDVER1) 2112 .Case("bdver2", CK_BDVER2) 2113 .Case("bdver3", CK_BDVER3) 2114 .Case("bdver4", CK_BDVER4) 2115 .Case("x86-64", CK_x86_64) 2116 .Case("geode", CK_Geode) 2117 .Default(CK_Generic); 2118 2119 // Perform any per-CPU checks necessary to determine if this CPU is 2120 // acceptable. 2121 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2122 // invalid without explaining *why*. 2123 switch (CPU) { 2124 case CK_Generic: 2125 // No processor selected! 2126 return false; 2127 2128 case CK_i386: 2129 case CK_i486: 2130 case CK_WinChipC6: 2131 case CK_WinChip2: 2132 case CK_C3: 2133 case CK_i586: 2134 case CK_Pentium: 2135 case CK_PentiumMMX: 2136 case CK_i686: 2137 case CK_PentiumPro: 2138 case CK_Pentium2: 2139 case CK_Pentium3: 2140 case CK_Pentium3M: 2141 case CK_PentiumM: 2142 case CK_Yonah: 2143 case CK_C3_2: 2144 case CK_Pentium4: 2145 case CK_Pentium4M: 2146 case CK_Prescott: 2147 case CK_K6: 2148 case CK_K6_2: 2149 case CK_K6_3: 2150 case CK_Athlon: 2151 case CK_AthlonThunderbird: 2152 case CK_Athlon4: 2153 case CK_AthlonXP: 2154 case CK_AthlonMP: 2155 case CK_Geode: 2156 // Only accept certain architectures when compiling in 32-bit mode. 2157 if (getTriple().getArch() != llvm::Triple::x86) 2158 return false; 2159 2160 // Fallthrough 2161 case CK_Nocona: 2162 case CK_Core2: 2163 case CK_Penryn: 2164 case CK_Bonnell: 2165 case CK_Silvermont: 2166 case CK_Nehalem: 2167 case CK_Westmere: 2168 case CK_SandyBridge: 2169 case CK_IvyBridge: 2170 case CK_Haswell: 2171 case CK_Broadwell: 2172 case CK_Skylake: 2173 case CK_KNL: 2174 case CK_Athlon64: 2175 case CK_Athlon64SSE3: 2176 case CK_AthlonFX: 2177 case CK_K8: 2178 case CK_K8SSE3: 2179 case CK_Opteron: 2180 case CK_OpteronSSE3: 2181 case CK_AMDFAM10: 2182 case CK_BTVER1: 2183 case CK_BTVER2: 2184 case CK_BDVER1: 2185 case CK_BDVER2: 2186 case CK_BDVER3: 2187 case CK_BDVER4: 2188 case CK_x86_64: 2189 return true; 2190 } 2191 llvm_unreachable("Unhandled CPU kind"); 2192 } 2193 2194 bool setFPMath(StringRef Name) override; 2195 2196 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2197 // We accept all non-ARM calling conventions 2198 return (CC == CC_X86ThisCall || 2199 CC == CC_X86FastCall || 2200 CC == CC_X86StdCall || 2201 CC == CC_X86VectorCall || 2202 CC == CC_C || 2203 CC == CC_X86Pascal || 2204 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2205 } 2206 2207 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2208 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2209 } 2210 }; 2211 2212 bool X86TargetInfo::setFPMath(StringRef Name) { 2213 if (Name == "387") { 2214 FPMath = FP_387; 2215 return true; 2216 } 2217 if (Name == "sse") { 2218 FPMath = FP_SSE; 2219 return true; 2220 } 2221 return false; 2222 } 2223 2224 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2225 // FIXME: This *really* should not be here. 2226 2227 // X86_64 always has SSE2. 2228 if (getTriple().getArch() == llvm::Triple::x86_64) 2229 setFeatureEnabledImpl(Features, "sse2", true); 2230 2231 switch (CPU) { 2232 case CK_Generic: 2233 case CK_i386: 2234 case CK_i486: 2235 case CK_i586: 2236 case CK_Pentium: 2237 case CK_i686: 2238 case CK_PentiumPro: 2239 break; 2240 case CK_PentiumMMX: 2241 case CK_Pentium2: 2242 case CK_K6: 2243 case CK_WinChipC6: 2244 setFeatureEnabledImpl(Features, "mmx", true); 2245 break; 2246 case CK_Pentium3: 2247 case CK_Pentium3M: 2248 case CK_C3_2: 2249 setFeatureEnabledImpl(Features, "sse", true); 2250 break; 2251 case CK_PentiumM: 2252 case CK_Pentium4: 2253 case CK_Pentium4M: 2254 case CK_x86_64: 2255 setFeatureEnabledImpl(Features, "sse2", true); 2256 break; 2257 case CK_Yonah: 2258 case CK_Prescott: 2259 case CK_Nocona: 2260 setFeatureEnabledImpl(Features, "sse3", true); 2261 setFeatureEnabledImpl(Features, "cx16", true); 2262 break; 2263 case CK_Core2: 2264 case CK_Bonnell: 2265 setFeatureEnabledImpl(Features, "ssse3", true); 2266 setFeatureEnabledImpl(Features, "cx16", true); 2267 break; 2268 case CK_Penryn: 2269 setFeatureEnabledImpl(Features, "sse4.1", true); 2270 setFeatureEnabledImpl(Features, "cx16", true); 2271 break; 2272 case CK_Skylake: 2273 setFeatureEnabledImpl(Features, "avx512f", true); 2274 setFeatureEnabledImpl(Features, "avx512cd", true); 2275 setFeatureEnabledImpl(Features, "avx512dq", true); 2276 setFeatureEnabledImpl(Features, "avx512bw", true); 2277 setFeatureEnabledImpl(Features, "avx512vl", true); 2278 // FALLTHROUGH 2279 case CK_Broadwell: 2280 setFeatureEnabledImpl(Features, "rdseed", true); 2281 setFeatureEnabledImpl(Features, "adx", true); 2282 // FALLTHROUGH 2283 case CK_Haswell: 2284 setFeatureEnabledImpl(Features, "avx2", true); 2285 setFeatureEnabledImpl(Features, "lzcnt", true); 2286 setFeatureEnabledImpl(Features, "bmi", true); 2287 setFeatureEnabledImpl(Features, "bmi2", true); 2288 setFeatureEnabledImpl(Features, "rtm", true); 2289 setFeatureEnabledImpl(Features, "fma", true); 2290 // FALLTHROUGH 2291 case CK_IvyBridge: 2292 setFeatureEnabledImpl(Features, "rdrnd", true); 2293 setFeatureEnabledImpl(Features, "f16c", true); 2294 setFeatureEnabledImpl(Features, "fsgsbase", true); 2295 // FALLTHROUGH 2296 case CK_SandyBridge: 2297 setFeatureEnabledImpl(Features, "avx", true); 2298 // FALLTHROUGH 2299 case CK_Westmere: 2300 case CK_Silvermont: 2301 setFeatureEnabledImpl(Features, "aes", true); 2302 setFeatureEnabledImpl(Features, "pclmul", true); 2303 // FALLTHROUGH 2304 case CK_Nehalem: 2305 setFeatureEnabledImpl(Features, "sse4.2", true); 2306 setFeatureEnabledImpl(Features, "cx16", true); 2307 break; 2308 case CK_KNL: 2309 setFeatureEnabledImpl(Features, "avx512f", true); 2310 setFeatureEnabledImpl(Features, "avx512cd", true); 2311 setFeatureEnabledImpl(Features, "avx512er", true); 2312 setFeatureEnabledImpl(Features, "avx512pf", true); 2313 setFeatureEnabledImpl(Features, "rdseed", true); 2314 setFeatureEnabledImpl(Features, "adx", true); 2315 setFeatureEnabledImpl(Features, "lzcnt", true); 2316 setFeatureEnabledImpl(Features, "bmi", true); 2317 setFeatureEnabledImpl(Features, "bmi2", true); 2318 setFeatureEnabledImpl(Features, "rtm", true); 2319 setFeatureEnabledImpl(Features, "fma", true); 2320 setFeatureEnabledImpl(Features, "rdrnd", true); 2321 setFeatureEnabledImpl(Features, "f16c", true); 2322 setFeatureEnabledImpl(Features, "fsgsbase", true); 2323 setFeatureEnabledImpl(Features, "aes", true); 2324 setFeatureEnabledImpl(Features, "pclmul", true); 2325 setFeatureEnabledImpl(Features, "cx16", true); 2326 break; 2327 case CK_K6_2: 2328 case CK_K6_3: 2329 case CK_WinChip2: 2330 case CK_C3: 2331 setFeatureEnabledImpl(Features, "3dnow", true); 2332 break; 2333 case CK_Athlon: 2334 case CK_AthlonThunderbird: 2335 case CK_Geode: 2336 setFeatureEnabledImpl(Features, "3dnowa", true); 2337 break; 2338 case CK_Athlon4: 2339 case CK_AthlonXP: 2340 case CK_AthlonMP: 2341 setFeatureEnabledImpl(Features, "sse", true); 2342 setFeatureEnabledImpl(Features, "3dnowa", true); 2343 break; 2344 case CK_K8: 2345 case CK_Opteron: 2346 case CK_Athlon64: 2347 case CK_AthlonFX: 2348 setFeatureEnabledImpl(Features, "sse2", true); 2349 setFeatureEnabledImpl(Features, "3dnowa", true); 2350 break; 2351 case CK_AMDFAM10: 2352 setFeatureEnabledImpl(Features, "sse4a", true); 2353 setFeatureEnabledImpl(Features, "lzcnt", true); 2354 setFeatureEnabledImpl(Features, "popcnt", true); 2355 // FALLTHROUGH 2356 case CK_K8SSE3: 2357 case CK_OpteronSSE3: 2358 case CK_Athlon64SSE3: 2359 setFeatureEnabledImpl(Features, "sse3", true); 2360 setFeatureEnabledImpl(Features, "3dnowa", true); 2361 break; 2362 case CK_BTVER2: 2363 setFeatureEnabledImpl(Features, "avx", true); 2364 setFeatureEnabledImpl(Features, "aes", true); 2365 setFeatureEnabledImpl(Features, "pclmul", true); 2366 setFeatureEnabledImpl(Features, "bmi", true); 2367 setFeatureEnabledImpl(Features, "f16c", true); 2368 // FALLTHROUGH 2369 case CK_BTVER1: 2370 setFeatureEnabledImpl(Features, "ssse3", true); 2371 setFeatureEnabledImpl(Features, "sse4a", true); 2372 setFeatureEnabledImpl(Features, "lzcnt", true); 2373 setFeatureEnabledImpl(Features, "popcnt", true); 2374 setFeatureEnabledImpl(Features, "prfchw", true); 2375 setFeatureEnabledImpl(Features, "cx16", true); 2376 break; 2377 case CK_BDVER4: 2378 setFeatureEnabledImpl(Features, "avx2", true); 2379 setFeatureEnabledImpl(Features, "bmi2", true); 2380 // FALLTHROUGH 2381 case CK_BDVER3: 2382 setFeatureEnabledImpl(Features, "fsgsbase", true); 2383 // FALLTHROUGH 2384 case CK_BDVER2: 2385 setFeatureEnabledImpl(Features, "bmi", true); 2386 setFeatureEnabledImpl(Features, "fma", true); 2387 setFeatureEnabledImpl(Features, "f16c", true); 2388 setFeatureEnabledImpl(Features, "tbm", true); 2389 // FALLTHROUGH 2390 case CK_BDVER1: 2391 // xop implies avx, sse4a and fma4. 2392 setFeatureEnabledImpl(Features, "xop", true); 2393 setFeatureEnabledImpl(Features, "lzcnt", true); 2394 setFeatureEnabledImpl(Features, "aes", true); 2395 setFeatureEnabledImpl(Features, "pclmul", true); 2396 setFeatureEnabledImpl(Features, "prfchw", true); 2397 setFeatureEnabledImpl(Features, "cx16", true); 2398 break; 2399 } 2400 } 2401 2402 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2403 X86SSEEnum Level, bool Enabled) { 2404 if (Enabled) { 2405 switch (Level) { 2406 case AVX512F: 2407 Features["avx512f"] = true; 2408 case AVX2: 2409 Features["avx2"] = true; 2410 case AVX: 2411 Features["avx"] = true; 2412 case SSE42: 2413 Features["sse4.2"] = true; 2414 case SSE41: 2415 Features["sse4.1"] = true; 2416 case SSSE3: 2417 Features["ssse3"] = true; 2418 case SSE3: 2419 Features["sse3"] = true; 2420 case SSE2: 2421 Features["sse2"] = true; 2422 case SSE1: 2423 Features["sse"] = true; 2424 case NoSSE: 2425 break; 2426 } 2427 return; 2428 } 2429 2430 switch (Level) { 2431 case NoSSE: 2432 case SSE1: 2433 Features["sse"] = false; 2434 case SSE2: 2435 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2436 Features["sha"] = false; 2437 case SSE3: 2438 Features["sse3"] = false; 2439 setXOPLevel(Features, NoXOP, false); 2440 case SSSE3: 2441 Features["ssse3"] = false; 2442 case SSE41: 2443 Features["sse4.1"] = false; 2444 case SSE42: 2445 Features["sse4.2"] = false; 2446 case AVX: 2447 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2448 setXOPLevel(Features, FMA4, false); 2449 case AVX2: 2450 Features["avx2"] = false; 2451 case AVX512F: 2452 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2453 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2454 Features["avx512vl"] = false; 2455 } 2456 } 2457 2458 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2459 MMX3DNowEnum Level, bool Enabled) { 2460 if (Enabled) { 2461 switch (Level) { 2462 case AMD3DNowAthlon: 2463 Features["3dnowa"] = true; 2464 case AMD3DNow: 2465 Features["3dnow"] = true; 2466 case MMX: 2467 Features["mmx"] = true; 2468 case NoMMX3DNow: 2469 break; 2470 } 2471 return; 2472 } 2473 2474 switch (Level) { 2475 case NoMMX3DNow: 2476 case MMX: 2477 Features["mmx"] = false; 2478 case AMD3DNow: 2479 Features["3dnow"] = false; 2480 case AMD3DNowAthlon: 2481 Features["3dnowa"] = false; 2482 } 2483 } 2484 2485 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2486 bool Enabled) { 2487 if (Enabled) { 2488 switch (Level) { 2489 case XOP: 2490 Features["xop"] = true; 2491 case FMA4: 2492 Features["fma4"] = true; 2493 setSSELevel(Features, AVX, true); 2494 case SSE4A: 2495 Features["sse4a"] = true; 2496 setSSELevel(Features, SSE3, true); 2497 case NoXOP: 2498 break; 2499 } 2500 return; 2501 } 2502 2503 switch (Level) { 2504 case NoXOP: 2505 case SSE4A: 2506 Features["sse4a"] = false; 2507 case FMA4: 2508 Features["fma4"] = false; 2509 case XOP: 2510 Features["xop"] = false; 2511 } 2512 } 2513 2514 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2515 StringRef Name, bool Enabled) { 2516 // FIXME: This *really* should not be here. We need some way of translating 2517 // options into llvm subtarget features. 2518 if (Name == "sse4") 2519 Name = "sse4.2"; 2520 2521 Features[Name] = Enabled; 2522 2523 if (Name == "mmx") { 2524 setMMXLevel(Features, MMX, Enabled); 2525 } else if (Name == "sse") { 2526 setSSELevel(Features, SSE1, Enabled); 2527 } else if (Name == "sse2") { 2528 setSSELevel(Features, SSE2, Enabled); 2529 } else if (Name == "sse3") { 2530 setSSELevel(Features, SSE3, Enabled); 2531 } else if (Name == "ssse3") { 2532 setSSELevel(Features, SSSE3, Enabled); 2533 } else if (Name == "sse4.2") { 2534 setSSELevel(Features, SSE42, Enabled); 2535 } else if (Name == "sse4.1") { 2536 setSSELevel(Features, SSE41, Enabled); 2537 } else if (Name == "3dnow") { 2538 setMMXLevel(Features, AMD3DNow, Enabled); 2539 } else if (Name == "3dnowa") { 2540 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2541 } else if (Name == "aes") { 2542 if (Enabled) 2543 setSSELevel(Features, SSE2, Enabled); 2544 } else if (Name == "pclmul") { 2545 if (Enabled) 2546 setSSELevel(Features, SSE2, Enabled); 2547 } else if (Name == "avx") { 2548 setSSELevel(Features, AVX, Enabled); 2549 } else if (Name == "avx2") { 2550 setSSELevel(Features, AVX2, Enabled); 2551 } else if (Name == "avx512f") { 2552 setSSELevel(Features, AVX512F, Enabled); 2553 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2554 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2555 if (Enabled) 2556 setSSELevel(Features, AVX512F, Enabled); 2557 } else if (Name == "fma") { 2558 if (Enabled) 2559 setSSELevel(Features, AVX, Enabled); 2560 } else if (Name == "fma4") { 2561 setXOPLevel(Features, FMA4, Enabled); 2562 } else if (Name == "xop") { 2563 setXOPLevel(Features, XOP, Enabled); 2564 } else if (Name == "sse4a") { 2565 setXOPLevel(Features, SSE4A, Enabled); 2566 } else if (Name == "f16c") { 2567 if (Enabled) 2568 setSSELevel(Features, AVX, Enabled); 2569 } else if (Name == "sha") { 2570 if (Enabled) 2571 setSSELevel(Features, SSE2, Enabled); 2572 } 2573 } 2574 2575 /// handleTargetFeatures - Perform initialization based on the user 2576 /// configured set of features. 2577 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2578 DiagnosticsEngine &Diags) { 2579 // Remember the maximum enabled sselevel. 2580 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2581 // Ignore disabled features. 2582 if (Features[i][0] == '-') 2583 continue; 2584 2585 StringRef Feature = StringRef(Features[i]).substr(1); 2586 2587 if (Feature == "aes") { 2588 HasAES = true; 2589 continue; 2590 } 2591 2592 if (Feature == "pclmul") { 2593 HasPCLMUL = true; 2594 continue; 2595 } 2596 2597 if (Feature == "lzcnt") { 2598 HasLZCNT = true; 2599 continue; 2600 } 2601 2602 if (Feature == "rdrnd") { 2603 HasRDRND = true; 2604 continue; 2605 } 2606 2607 if (Feature == "fsgsbase") { 2608 HasFSGSBASE = true; 2609 continue; 2610 } 2611 2612 if (Feature == "bmi") { 2613 HasBMI = true; 2614 continue; 2615 } 2616 2617 if (Feature == "bmi2") { 2618 HasBMI2 = true; 2619 continue; 2620 } 2621 2622 if (Feature == "popcnt") { 2623 HasPOPCNT = true; 2624 continue; 2625 } 2626 2627 if (Feature == "rtm") { 2628 HasRTM = true; 2629 continue; 2630 } 2631 2632 if (Feature == "prfchw") { 2633 HasPRFCHW = true; 2634 continue; 2635 } 2636 2637 if (Feature == "rdseed") { 2638 HasRDSEED = true; 2639 continue; 2640 } 2641 2642 if (Feature == "adx") { 2643 HasADX = true; 2644 continue; 2645 } 2646 2647 if (Feature == "tbm") { 2648 HasTBM = true; 2649 continue; 2650 } 2651 2652 if (Feature == "fma") { 2653 HasFMA = true; 2654 continue; 2655 } 2656 2657 if (Feature == "f16c") { 2658 HasF16C = true; 2659 continue; 2660 } 2661 2662 if (Feature == "avx512cd") { 2663 HasAVX512CD = true; 2664 continue; 2665 } 2666 2667 if (Feature == "avx512er") { 2668 HasAVX512ER = true; 2669 continue; 2670 } 2671 2672 if (Feature == "avx512pf") { 2673 HasAVX512PF = true; 2674 continue; 2675 } 2676 2677 if (Feature == "avx512dq") { 2678 HasAVX512DQ = true; 2679 continue; 2680 } 2681 2682 if (Feature == "avx512bw") { 2683 HasAVX512BW = true; 2684 continue; 2685 } 2686 2687 if (Feature == "avx512vl") { 2688 HasAVX512VL = true; 2689 continue; 2690 } 2691 2692 if (Feature == "sha") { 2693 HasSHA = true; 2694 continue; 2695 } 2696 2697 if (Feature == "cx16") { 2698 HasCX16 = true; 2699 continue; 2700 } 2701 2702 assert(Features[i][0] == '+' && "Invalid target feature!"); 2703 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2704 .Case("avx512f", AVX512F) 2705 .Case("avx2", AVX2) 2706 .Case("avx", AVX) 2707 .Case("sse4.2", SSE42) 2708 .Case("sse4.1", SSE41) 2709 .Case("ssse3", SSSE3) 2710 .Case("sse3", SSE3) 2711 .Case("sse2", SSE2) 2712 .Case("sse", SSE1) 2713 .Default(NoSSE); 2714 SSELevel = std::max(SSELevel, Level); 2715 2716 MMX3DNowEnum ThreeDNowLevel = 2717 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2718 .Case("3dnowa", AMD3DNowAthlon) 2719 .Case("3dnow", AMD3DNow) 2720 .Case("mmx", MMX) 2721 .Default(NoMMX3DNow); 2722 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2723 2724 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2725 .Case("xop", XOP) 2726 .Case("fma4", FMA4) 2727 .Case("sse4a", SSE4A) 2728 .Default(NoXOP); 2729 XOPLevel = std::max(XOPLevel, XLevel); 2730 } 2731 2732 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2733 // Can't do this earlier because we need to be able to explicitly enable 2734 // popcnt and still disable sse4.2. 2735 if (!HasPOPCNT && SSELevel >= SSE42 && 2736 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2737 HasPOPCNT = true; 2738 Features.push_back("+popcnt"); 2739 } 2740 2741 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2742 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2743 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2744 HasPRFCHW = true; 2745 Features.push_back("+prfchw"); 2746 } 2747 2748 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2749 // matches the selected sse level. 2750 if (FPMath == FP_SSE && SSELevel < SSE1) { 2751 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2752 return false; 2753 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2754 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2755 return false; 2756 } 2757 2758 // Don't tell the backend if we're turning off mmx; it will end up disabling 2759 // SSE, which we don't want. 2760 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2761 // then enable MMX. 2762 std::vector<std::string>::iterator it; 2763 it = std::find(Features.begin(), Features.end(), "-mmx"); 2764 if (it != Features.end()) 2765 Features.erase(it); 2766 else if (SSELevel > NoSSE) 2767 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2768 return true; 2769 } 2770 2771 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2772 /// definitions for this particular subtarget. 2773 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2774 MacroBuilder &Builder) const { 2775 // Target identification. 2776 if (getTriple().getArch() == llvm::Triple::x86_64) { 2777 Builder.defineMacro("__amd64__"); 2778 Builder.defineMacro("__amd64"); 2779 Builder.defineMacro("__x86_64"); 2780 Builder.defineMacro("__x86_64__"); 2781 if (getTriple().getArchName() == "x86_64h") { 2782 Builder.defineMacro("__x86_64h"); 2783 Builder.defineMacro("__x86_64h__"); 2784 } 2785 } else { 2786 DefineStd(Builder, "i386", Opts); 2787 } 2788 2789 // Subtarget options. 2790 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2791 // truly should be based on -mtune options. 2792 switch (CPU) { 2793 case CK_Generic: 2794 break; 2795 case CK_i386: 2796 // The rest are coming from the i386 define above. 2797 Builder.defineMacro("__tune_i386__"); 2798 break; 2799 case CK_i486: 2800 case CK_WinChipC6: 2801 case CK_WinChip2: 2802 case CK_C3: 2803 defineCPUMacros(Builder, "i486"); 2804 break; 2805 case CK_PentiumMMX: 2806 Builder.defineMacro("__pentium_mmx__"); 2807 Builder.defineMacro("__tune_pentium_mmx__"); 2808 // Fallthrough 2809 case CK_i586: 2810 case CK_Pentium: 2811 defineCPUMacros(Builder, "i586"); 2812 defineCPUMacros(Builder, "pentium"); 2813 break; 2814 case CK_Pentium3: 2815 case CK_Pentium3M: 2816 case CK_PentiumM: 2817 Builder.defineMacro("__tune_pentium3__"); 2818 // Fallthrough 2819 case CK_Pentium2: 2820 case CK_C3_2: 2821 Builder.defineMacro("__tune_pentium2__"); 2822 // Fallthrough 2823 case CK_PentiumPro: 2824 Builder.defineMacro("__tune_i686__"); 2825 Builder.defineMacro("__tune_pentiumpro__"); 2826 // Fallthrough 2827 case CK_i686: 2828 Builder.defineMacro("__i686"); 2829 Builder.defineMacro("__i686__"); 2830 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2831 Builder.defineMacro("__pentiumpro"); 2832 Builder.defineMacro("__pentiumpro__"); 2833 break; 2834 case CK_Pentium4: 2835 case CK_Pentium4M: 2836 defineCPUMacros(Builder, "pentium4"); 2837 break; 2838 case CK_Yonah: 2839 case CK_Prescott: 2840 case CK_Nocona: 2841 defineCPUMacros(Builder, "nocona"); 2842 break; 2843 case CK_Core2: 2844 case CK_Penryn: 2845 defineCPUMacros(Builder, "core2"); 2846 break; 2847 case CK_Bonnell: 2848 defineCPUMacros(Builder, "atom"); 2849 break; 2850 case CK_Silvermont: 2851 defineCPUMacros(Builder, "slm"); 2852 break; 2853 case CK_Nehalem: 2854 case CK_Westmere: 2855 case CK_SandyBridge: 2856 case CK_IvyBridge: 2857 case CK_Haswell: 2858 case CK_Broadwell: 2859 // FIXME: Historically, we defined this legacy name, it would be nice to 2860 // remove it at some point. We've never exposed fine-grained names for 2861 // recent primary x86 CPUs, and we should keep it that way. 2862 defineCPUMacros(Builder, "corei7"); 2863 break; 2864 case CK_Skylake: 2865 // FIXME: Historically, we defined this legacy name, it would be nice to 2866 // remove it at some point. This is the only fine-grained CPU macro in the 2867 // main intel CPU line, and it would be better to not have these and force 2868 // people to use ISA macros. 2869 defineCPUMacros(Builder, "skx"); 2870 break; 2871 case CK_KNL: 2872 defineCPUMacros(Builder, "knl"); 2873 break; 2874 case CK_K6_2: 2875 Builder.defineMacro("__k6_2__"); 2876 Builder.defineMacro("__tune_k6_2__"); 2877 // Fallthrough 2878 case CK_K6_3: 2879 if (CPU != CK_K6_2) { // In case of fallthrough 2880 // FIXME: GCC may be enabling these in cases where some other k6 2881 // architecture is specified but -m3dnow is explicitly provided. The 2882 // exact semantics need to be determined and emulated here. 2883 Builder.defineMacro("__k6_3__"); 2884 Builder.defineMacro("__tune_k6_3__"); 2885 } 2886 // Fallthrough 2887 case CK_K6: 2888 defineCPUMacros(Builder, "k6"); 2889 break; 2890 case CK_Athlon: 2891 case CK_AthlonThunderbird: 2892 case CK_Athlon4: 2893 case CK_AthlonXP: 2894 case CK_AthlonMP: 2895 defineCPUMacros(Builder, "athlon"); 2896 if (SSELevel != NoSSE) { 2897 Builder.defineMacro("__athlon_sse__"); 2898 Builder.defineMacro("__tune_athlon_sse__"); 2899 } 2900 break; 2901 case CK_K8: 2902 case CK_K8SSE3: 2903 case CK_x86_64: 2904 case CK_Opteron: 2905 case CK_OpteronSSE3: 2906 case CK_Athlon64: 2907 case CK_Athlon64SSE3: 2908 case CK_AthlonFX: 2909 defineCPUMacros(Builder, "k8"); 2910 break; 2911 case CK_AMDFAM10: 2912 defineCPUMacros(Builder, "amdfam10"); 2913 break; 2914 case CK_BTVER1: 2915 defineCPUMacros(Builder, "btver1"); 2916 break; 2917 case CK_BTVER2: 2918 defineCPUMacros(Builder, "btver2"); 2919 break; 2920 case CK_BDVER1: 2921 defineCPUMacros(Builder, "bdver1"); 2922 break; 2923 case CK_BDVER2: 2924 defineCPUMacros(Builder, "bdver2"); 2925 break; 2926 case CK_BDVER3: 2927 defineCPUMacros(Builder, "bdver3"); 2928 break; 2929 case CK_BDVER4: 2930 defineCPUMacros(Builder, "bdver4"); 2931 break; 2932 case CK_Geode: 2933 defineCPUMacros(Builder, "geode"); 2934 break; 2935 } 2936 2937 // Target properties. 2938 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2939 2940 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2941 // functions in glibc header files that use FP Stack inline asm which the 2942 // backend can't deal with (PR879). 2943 Builder.defineMacro("__NO_MATH_INLINES"); 2944 2945 if (HasAES) 2946 Builder.defineMacro("__AES__"); 2947 2948 if (HasPCLMUL) 2949 Builder.defineMacro("__PCLMUL__"); 2950 2951 if (HasLZCNT) 2952 Builder.defineMacro("__LZCNT__"); 2953 2954 if (HasRDRND) 2955 Builder.defineMacro("__RDRND__"); 2956 2957 if (HasFSGSBASE) 2958 Builder.defineMacro("__FSGSBASE__"); 2959 2960 if (HasBMI) 2961 Builder.defineMacro("__BMI__"); 2962 2963 if (HasBMI2) 2964 Builder.defineMacro("__BMI2__"); 2965 2966 if (HasPOPCNT) 2967 Builder.defineMacro("__POPCNT__"); 2968 2969 if (HasRTM) 2970 Builder.defineMacro("__RTM__"); 2971 2972 if (HasPRFCHW) 2973 Builder.defineMacro("__PRFCHW__"); 2974 2975 if (HasRDSEED) 2976 Builder.defineMacro("__RDSEED__"); 2977 2978 if (HasADX) 2979 Builder.defineMacro("__ADX__"); 2980 2981 if (HasTBM) 2982 Builder.defineMacro("__TBM__"); 2983 2984 switch (XOPLevel) { 2985 case XOP: 2986 Builder.defineMacro("__XOP__"); 2987 case FMA4: 2988 Builder.defineMacro("__FMA4__"); 2989 case SSE4A: 2990 Builder.defineMacro("__SSE4A__"); 2991 case NoXOP: 2992 break; 2993 } 2994 2995 if (HasFMA) 2996 Builder.defineMacro("__FMA__"); 2997 2998 if (HasF16C) 2999 Builder.defineMacro("__F16C__"); 3000 3001 if (HasAVX512CD) 3002 Builder.defineMacro("__AVX512CD__"); 3003 if (HasAVX512ER) 3004 Builder.defineMacro("__AVX512ER__"); 3005 if (HasAVX512PF) 3006 Builder.defineMacro("__AVX512PF__"); 3007 if (HasAVX512DQ) 3008 Builder.defineMacro("__AVX512DQ__"); 3009 if (HasAVX512BW) 3010 Builder.defineMacro("__AVX512BW__"); 3011 if (HasAVX512VL) 3012 Builder.defineMacro("__AVX512VL__"); 3013 3014 if (HasSHA) 3015 Builder.defineMacro("__SHA__"); 3016 3017 if (HasCX16) 3018 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3019 3020 // Each case falls through to the previous one here. 3021 switch (SSELevel) { 3022 case AVX512F: 3023 Builder.defineMacro("__AVX512F__"); 3024 case AVX2: 3025 Builder.defineMacro("__AVX2__"); 3026 case AVX: 3027 Builder.defineMacro("__AVX__"); 3028 case SSE42: 3029 Builder.defineMacro("__SSE4_2__"); 3030 case SSE41: 3031 Builder.defineMacro("__SSE4_1__"); 3032 case SSSE3: 3033 Builder.defineMacro("__SSSE3__"); 3034 case SSE3: 3035 Builder.defineMacro("__SSE3__"); 3036 case SSE2: 3037 Builder.defineMacro("__SSE2__"); 3038 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3039 case SSE1: 3040 Builder.defineMacro("__SSE__"); 3041 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3042 case NoSSE: 3043 break; 3044 } 3045 3046 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3047 switch (SSELevel) { 3048 case AVX512F: 3049 case AVX2: 3050 case AVX: 3051 case SSE42: 3052 case SSE41: 3053 case SSSE3: 3054 case SSE3: 3055 case SSE2: 3056 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3057 break; 3058 case SSE1: 3059 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3060 break; 3061 default: 3062 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3063 } 3064 } 3065 3066 // Each case falls through to the previous one here. 3067 switch (MMX3DNowLevel) { 3068 case AMD3DNowAthlon: 3069 Builder.defineMacro("__3dNOW_A__"); 3070 case AMD3DNow: 3071 Builder.defineMacro("__3dNOW__"); 3072 case MMX: 3073 Builder.defineMacro("__MMX__"); 3074 case NoMMX3DNow: 3075 break; 3076 } 3077 3078 if (CPU >= CK_i486) { 3079 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3080 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3081 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3082 } 3083 if (CPU >= CK_i586) 3084 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3085 } 3086 3087 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3088 return llvm::StringSwitch<bool>(Feature) 3089 .Case("aes", HasAES) 3090 .Case("avx", SSELevel >= AVX) 3091 .Case("avx2", SSELevel >= AVX2) 3092 .Case("avx512f", SSELevel >= AVX512F) 3093 .Case("avx512cd", HasAVX512CD) 3094 .Case("avx512er", HasAVX512ER) 3095 .Case("avx512pf", HasAVX512PF) 3096 .Case("avx512dq", HasAVX512DQ) 3097 .Case("avx512bw", HasAVX512BW) 3098 .Case("avx512vl", HasAVX512VL) 3099 .Case("bmi", HasBMI) 3100 .Case("bmi2", HasBMI2) 3101 .Case("cx16", HasCX16) 3102 .Case("f16c", HasF16C) 3103 .Case("fma", HasFMA) 3104 .Case("fma4", XOPLevel >= FMA4) 3105 .Case("fsgsbase", HasFSGSBASE) 3106 .Case("lzcnt", HasLZCNT) 3107 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3108 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3109 .Case("mmx", MMX3DNowLevel >= MMX) 3110 .Case("pclmul", HasPCLMUL) 3111 .Case("popcnt", HasPOPCNT) 3112 .Case("prfchw", HasPRFCHW) 3113 .Case("rdrnd", HasRDRND) 3114 .Case("rdseed", HasRDSEED) 3115 .Case("rtm", HasRTM) 3116 .Case("sha", HasSHA) 3117 .Case("sse", SSELevel >= SSE1) 3118 .Case("sse2", SSELevel >= SSE2) 3119 .Case("sse3", SSELevel >= SSE3) 3120 .Case("ssse3", SSELevel >= SSSE3) 3121 .Case("sse4.1", SSELevel >= SSE41) 3122 .Case("sse4.2", SSELevel >= SSE42) 3123 .Case("sse4a", XOPLevel >= SSE4A) 3124 .Case("tbm", HasTBM) 3125 .Case("x86", true) 3126 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3127 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3128 .Case("xop", XOPLevel >= XOP) 3129 .Default(false); 3130 } 3131 3132 bool 3133 X86TargetInfo::validateAsmConstraint(const char *&Name, 3134 TargetInfo::ConstraintInfo &Info) const { 3135 switch (*Name) { 3136 default: return false; 3137 case 'I': 3138 Info.setRequiresImmediate(0, 31); 3139 return true; 3140 case 'J': 3141 Info.setRequiresImmediate(0, 63); 3142 return true; 3143 case 'K': 3144 Info.setRequiresImmediate(-128, 127); 3145 return true; 3146 case 'L': 3147 // FIXME: properly analyze this constraint: 3148 // must be one of 0xff, 0xffff, or 0xffffffff 3149 return true; 3150 case 'M': 3151 Info.setRequiresImmediate(0, 3); 3152 return true; 3153 case 'N': 3154 Info.setRequiresImmediate(0, 255); 3155 return true; 3156 case 'O': 3157 Info.setRequiresImmediate(0, 127); 3158 return true; 3159 case 'Y': // first letter of a pair: 3160 switch (*(Name+1)) { 3161 default: return false; 3162 case '0': // First SSE register. 3163 case 't': // Any SSE register, when SSE2 is enabled. 3164 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3165 case 'm': // any MMX register, when inter-unit moves enabled. 3166 break; // falls through to setAllowsRegister. 3167 } 3168 case 'f': // any x87 floating point stack register. 3169 // Constraint 'f' cannot be used for output operands. 3170 if (Info.ConstraintStr[0] == '=') 3171 return false; 3172 3173 Info.setAllowsRegister(); 3174 return true; 3175 case 'a': // eax. 3176 case 'b': // ebx. 3177 case 'c': // ecx. 3178 case 'd': // edx. 3179 case 'S': // esi. 3180 case 'D': // edi. 3181 case 'A': // edx:eax. 3182 case 't': // top of floating point stack. 3183 case 'u': // second from top of floating point stack. 3184 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3185 case 'y': // Any MMX register. 3186 case 'x': // Any SSE register. 3187 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3188 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3189 case 'l': // "Index" registers: any general register that can be used as an 3190 // index in a base+index memory access. 3191 Info.setAllowsRegister(); 3192 return true; 3193 case 'C': // SSE floating point constant. 3194 case 'G': // x87 floating point constant. 3195 case 'e': // 32-bit signed integer constant for use with zero-extending 3196 // x86_64 instructions. 3197 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3198 // x86_64 instructions. 3199 return true; 3200 } 3201 } 3202 3203 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3204 unsigned Size) const { 3205 // Strip off constraint modifiers. 3206 while (Constraint[0] == '=' || 3207 Constraint[0] == '+' || 3208 Constraint[0] == '&') 3209 Constraint = Constraint.substr(1); 3210 3211 return validateOperandSize(Constraint, Size); 3212 } 3213 3214 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3215 unsigned Size) const { 3216 return validateOperandSize(Constraint, Size); 3217 } 3218 3219 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3220 unsigned Size) const { 3221 switch (Constraint[0]) { 3222 default: break; 3223 case 'y': 3224 return Size <= 64; 3225 case 'f': 3226 case 't': 3227 case 'u': 3228 return Size <= 128; 3229 case 'x': 3230 // 256-bit ymm registers can be used if target supports AVX. 3231 return Size <= (SSELevel >= AVX ? 256U : 128U); 3232 } 3233 3234 return true; 3235 } 3236 3237 std::string 3238 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3239 switch (*Constraint) { 3240 case 'a': return std::string("{ax}"); 3241 case 'b': return std::string("{bx}"); 3242 case 'c': return std::string("{cx}"); 3243 case 'd': return std::string("{dx}"); 3244 case 'S': return std::string("{si}"); 3245 case 'D': return std::string("{di}"); 3246 case 'p': // address 3247 return std::string("im"); 3248 case 't': // top of floating point stack. 3249 return std::string("{st}"); 3250 case 'u': // second from top of floating point stack. 3251 return std::string("{st(1)}"); // second from top of floating point stack. 3252 default: 3253 return std::string(1, *Constraint); 3254 } 3255 } 3256 } // end anonymous namespace 3257 3258 namespace { 3259 // X86-32 generic target 3260 class X86_32TargetInfo : public X86TargetInfo { 3261 public: 3262 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3263 DoubleAlign = LongLongAlign = 32; 3264 LongDoubleWidth = 96; 3265 LongDoubleAlign = 32; 3266 SuitableAlign = 128; 3267 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3268 SizeType = UnsignedInt; 3269 PtrDiffType = SignedInt; 3270 IntPtrType = SignedInt; 3271 RegParmMax = 3; 3272 3273 // Use fpret for all types. 3274 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3275 (1 << TargetInfo::Double) | 3276 (1 << TargetInfo::LongDouble)); 3277 3278 // x86-32 has atomics up to 8 bytes 3279 // FIXME: Check that we actually have cmpxchg8b before setting 3280 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3281 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3282 } 3283 BuiltinVaListKind getBuiltinVaListKind() const override { 3284 return TargetInfo::CharPtrBuiltinVaList; 3285 } 3286 3287 int getEHDataRegisterNumber(unsigned RegNo) const override { 3288 if (RegNo == 0) return 0; 3289 if (RegNo == 1) return 2; 3290 return -1; 3291 } 3292 bool validateOperandSize(StringRef Constraint, 3293 unsigned Size) const override { 3294 switch (Constraint[0]) { 3295 default: break; 3296 case 'R': 3297 case 'q': 3298 case 'Q': 3299 case 'a': 3300 case 'b': 3301 case 'c': 3302 case 'd': 3303 case 'S': 3304 case 'D': 3305 return Size <= 32; 3306 case 'A': 3307 return Size <= 64; 3308 } 3309 3310 return X86TargetInfo::validateOperandSize(Constraint, Size); 3311 } 3312 }; 3313 } // end anonymous namespace 3314 3315 namespace { 3316 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3317 public: 3318 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3319 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3320 3321 unsigned getFloatEvalMethod() const override { 3322 unsigned Major, Minor, Micro; 3323 getTriple().getOSVersion(Major, Minor, Micro); 3324 // New NetBSD uses the default rounding mode. 3325 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3326 return X86_32TargetInfo::getFloatEvalMethod(); 3327 // NetBSD before 6.99.26 defaults to "double" rounding. 3328 return 1; 3329 } 3330 }; 3331 } // end anonymous namespace 3332 3333 namespace { 3334 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3335 public: 3336 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3337 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3338 SizeType = UnsignedLong; 3339 IntPtrType = SignedLong; 3340 PtrDiffType = SignedLong; 3341 } 3342 }; 3343 } // end anonymous namespace 3344 3345 namespace { 3346 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3347 public: 3348 BitrigI386TargetInfo(const llvm::Triple &Triple) 3349 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3350 SizeType = UnsignedLong; 3351 IntPtrType = SignedLong; 3352 PtrDiffType = SignedLong; 3353 } 3354 }; 3355 } // end anonymous namespace 3356 3357 namespace { 3358 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3359 public: 3360 DarwinI386TargetInfo(const llvm::Triple &Triple) 3361 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3362 LongDoubleWidth = 128; 3363 LongDoubleAlign = 128; 3364 SuitableAlign = 128; 3365 MaxVectorAlign = 256; 3366 SizeType = UnsignedLong; 3367 IntPtrType = SignedLong; 3368 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3369 HasAlignMac68kSupport = true; 3370 } 3371 3372 }; 3373 } // end anonymous namespace 3374 3375 namespace { 3376 // x86-32 Windows target 3377 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3378 public: 3379 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3380 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3381 WCharType = UnsignedShort; 3382 DoubleAlign = LongLongAlign = 64; 3383 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3384 } 3385 void getTargetDefines(const LangOptions &Opts, 3386 MacroBuilder &Builder) const override { 3387 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3388 } 3389 }; 3390 3391 // x86-32 Windows Visual Studio target 3392 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3393 public: 3394 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3395 : WindowsX86_32TargetInfo(Triple) { 3396 LongDoubleWidth = LongDoubleAlign = 64; 3397 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3398 } 3399 void getTargetDefines(const LangOptions &Opts, 3400 MacroBuilder &Builder) const override { 3401 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3402 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3403 // The value of the following reflects processor type. 3404 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3405 // We lost the original triple, so we use the default. 3406 Builder.defineMacro("_M_IX86", "600"); 3407 } 3408 }; 3409 } // end anonymous namespace 3410 3411 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3412 Builder.defineMacro("__MSVCRT__"); 3413 Builder.defineMacro("__MINGW32__"); 3414 3415 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports 3416 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3417 // macro anyway for pre-processor compatibility. 3418 if (Opts.MicrosoftExt) 3419 Builder.defineMacro("__declspec", "__declspec"); 3420 else 3421 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3422 3423 if (!Opts.MicrosoftExt) { 3424 // Provide macros for all the calling convention keywords. Provide both 3425 // single and double underscore prefixed variants. These are available on 3426 // x64 as well as x86, even though they have no effect. 3427 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3428 for (const char *CC : CCs) { 3429 std::string GCCSpelling = "__attribute__((__"; 3430 GCCSpelling += CC; 3431 GCCSpelling += "__))"; 3432 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3433 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3434 } 3435 } 3436 } 3437 3438 namespace { 3439 // x86-32 MinGW target 3440 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3441 public: 3442 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3443 : WindowsX86_32TargetInfo(Triple) {} 3444 void getTargetDefines(const LangOptions &Opts, 3445 MacroBuilder &Builder) const override { 3446 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3447 DefineStd(Builder, "WIN32", Opts); 3448 DefineStd(Builder, "WINNT", Opts); 3449 Builder.defineMacro("_X86_"); 3450 addMinGWDefines(Opts, Builder); 3451 } 3452 }; 3453 } // end anonymous namespace 3454 3455 namespace { 3456 // x86-32 Cygwin target 3457 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3458 public: 3459 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3460 : X86_32TargetInfo(Triple) { 3461 TLSSupported = false; 3462 WCharType = UnsignedShort; 3463 DoubleAlign = LongLongAlign = 64; 3464 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3465 } 3466 void getTargetDefines(const LangOptions &Opts, 3467 MacroBuilder &Builder) const override { 3468 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3469 Builder.defineMacro("_X86_"); 3470 Builder.defineMacro("__CYGWIN__"); 3471 Builder.defineMacro("__CYGWIN32__"); 3472 DefineStd(Builder, "unix", Opts); 3473 if (Opts.CPlusPlus) 3474 Builder.defineMacro("_GNU_SOURCE"); 3475 } 3476 }; 3477 } // end anonymous namespace 3478 3479 namespace { 3480 // x86-32 Haiku target 3481 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3482 public: 3483 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3484 SizeType = UnsignedLong; 3485 IntPtrType = SignedLong; 3486 PtrDiffType = SignedLong; 3487 ProcessIDType = SignedLong; 3488 this->UserLabelPrefix = ""; 3489 this->TLSSupported = false; 3490 } 3491 void getTargetDefines(const LangOptions &Opts, 3492 MacroBuilder &Builder) const override { 3493 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3494 Builder.defineMacro("__INTEL__"); 3495 Builder.defineMacro("__HAIKU__"); 3496 } 3497 }; 3498 } // end anonymous namespace 3499 3500 // RTEMS Target 3501 template<typename Target> 3502 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3503 protected: 3504 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3505 MacroBuilder &Builder) const override { 3506 // RTEMS defines; list based off of gcc output 3507 3508 Builder.defineMacro("__rtems__"); 3509 Builder.defineMacro("__ELF__"); 3510 } 3511 3512 public: 3513 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3514 this->UserLabelPrefix = ""; 3515 3516 switch (Triple.getArch()) { 3517 default: 3518 case llvm::Triple::x86: 3519 // this->MCountName = ".mcount"; 3520 break; 3521 case llvm::Triple::mips: 3522 case llvm::Triple::mipsel: 3523 case llvm::Triple::ppc: 3524 case llvm::Triple::ppc64: 3525 case llvm::Triple::ppc64le: 3526 // this->MCountName = "_mcount"; 3527 break; 3528 case llvm::Triple::arm: 3529 // this->MCountName = "__mcount"; 3530 break; 3531 } 3532 } 3533 }; 3534 3535 namespace { 3536 // x86-32 RTEMS target 3537 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3538 public: 3539 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3540 SizeType = UnsignedLong; 3541 IntPtrType = SignedLong; 3542 PtrDiffType = SignedLong; 3543 this->UserLabelPrefix = ""; 3544 } 3545 void getTargetDefines(const LangOptions &Opts, 3546 MacroBuilder &Builder) const override { 3547 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3548 Builder.defineMacro("__INTEL__"); 3549 Builder.defineMacro("__rtems__"); 3550 } 3551 }; 3552 } // end anonymous namespace 3553 3554 namespace { 3555 // x86-64 generic target 3556 class X86_64TargetInfo : public X86TargetInfo { 3557 public: 3558 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3559 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3560 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3561 LongDoubleWidth = 128; 3562 LongDoubleAlign = 128; 3563 LargeArrayMinWidth = 128; 3564 LargeArrayAlign = 128; 3565 SuitableAlign = 128; 3566 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3567 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3568 IntPtrType = IsX32 ? SignedInt : SignedLong; 3569 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3570 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3571 RegParmMax = 6; 3572 3573 // Pointers are 32-bit in x32. 3574 DescriptionString = (IsX32) 3575 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3576 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3577 3578 // Use fpret only for long double. 3579 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3580 3581 // Use fp2ret for _Complex long double. 3582 ComplexLongDoubleUsesFP2Ret = true; 3583 3584 // x86-64 has atomics up to 16 bytes. 3585 MaxAtomicPromoteWidth = 128; 3586 MaxAtomicInlineWidth = 128; 3587 } 3588 BuiltinVaListKind getBuiltinVaListKind() const override { 3589 return TargetInfo::X86_64ABIBuiltinVaList; 3590 } 3591 3592 int getEHDataRegisterNumber(unsigned RegNo) const override { 3593 if (RegNo == 0) return 0; 3594 if (RegNo == 1) return 1; 3595 return -1; 3596 } 3597 3598 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3599 return (CC == CC_C || 3600 CC == CC_X86VectorCall || 3601 CC == CC_IntelOclBicc || 3602 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3603 } 3604 3605 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3606 return CC_C; 3607 } 3608 3609 // for x32 we need it here explicitly 3610 bool hasInt128Type() const override { return true; } 3611 }; 3612 } // end anonymous namespace 3613 3614 namespace { 3615 // x86-64 Windows target 3616 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3617 public: 3618 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3619 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3620 WCharType = UnsignedShort; 3621 LongWidth = LongAlign = 32; 3622 DoubleAlign = LongLongAlign = 64; 3623 IntMaxType = SignedLongLong; 3624 Int64Type = SignedLongLong; 3625 SizeType = UnsignedLongLong; 3626 PtrDiffType = SignedLongLong; 3627 IntPtrType = SignedLongLong; 3628 this->UserLabelPrefix = ""; 3629 } 3630 void getTargetDefines(const LangOptions &Opts, 3631 MacroBuilder &Builder) const override { 3632 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3633 Builder.defineMacro("_WIN64"); 3634 } 3635 BuiltinVaListKind getBuiltinVaListKind() const override { 3636 return TargetInfo::CharPtrBuiltinVaList; 3637 } 3638 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3639 return (CC == CC_C || 3640 CC == CC_X86VectorCall || 3641 CC == CC_IntelOclBicc || 3642 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3643 } 3644 }; 3645 } // end anonymous namespace 3646 3647 namespace { 3648 // x86-64 Windows Visual Studio target 3649 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3650 public: 3651 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3652 : WindowsX86_64TargetInfo(Triple) { 3653 LongDoubleWidth = LongDoubleAlign = 64; 3654 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3655 } 3656 void getTargetDefines(const LangOptions &Opts, 3657 MacroBuilder &Builder) const override { 3658 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3659 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3660 Builder.defineMacro("_M_X64"); 3661 Builder.defineMacro("_M_AMD64"); 3662 } 3663 }; 3664 } // end anonymous namespace 3665 3666 namespace { 3667 // x86-64 MinGW target 3668 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3669 public: 3670 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3671 : WindowsX86_64TargetInfo(Triple) {} 3672 void getTargetDefines(const LangOptions &Opts, 3673 MacroBuilder &Builder) const override { 3674 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3675 DefineStd(Builder, "WIN64", Opts); 3676 Builder.defineMacro("__MINGW64__"); 3677 addMinGWDefines(Opts, Builder); 3678 3679 // GCC defines this macro when it is using __gxx_personality_seh0. 3680 if (!Opts.SjLjExceptions) 3681 Builder.defineMacro("__SEH__"); 3682 } 3683 }; 3684 } // end anonymous namespace 3685 3686 namespace { 3687 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3688 public: 3689 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3690 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3691 Int64Type = SignedLongLong; 3692 MaxVectorAlign = 256; 3693 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3694 llvm::Triple T = llvm::Triple(Triple); 3695 if (T.isiOS()) 3696 UseSignedCharForObjCBool = false; 3697 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3698 } 3699 }; 3700 } // end anonymous namespace 3701 3702 namespace { 3703 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3704 public: 3705 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3706 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3707 IntMaxType = SignedLongLong; 3708 Int64Type = SignedLongLong; 3709 } 3710 }; 3711 } // end anonymous namespace 3712 3713 namespace { 3714 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3715 public: 3716 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3717 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3718 IntMaxType = SignedLongLong; 3719 Int64Type = SignedLongLong; 3720 } 3721 }; 3722 } 3723 3724 3725 namespace { 3726 class ARMTargetInfo : public TargetInfo { 3727 // Possible FPU choices. 3728 enum FPUMode { 3729 VFP2FPU = (1 << 0), 3730 VFP3FPU = (1 << 1), 3731 VFP4FPU = (1 << 2), 3732 NeonFPU = (1 << 3), 3733 FPARMV8 = (1 << 4) 3734 }; 3735 3736 // Possible HWDiv features. 3737 enum HWDivMode { 3738 HWDivThumb = (1 << 0), 3739 HWDivARM = (1 << 1) 3740 }; 3741 3742 static bool FPUModeIsVFP(FPUMode Mode) { 3743 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3744 } 3745 3746 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3747 static const char * const GCCRegNames[]; 3748 3749 std::string ABI, CPU; 3750 3751 enum { 3752 FP_Default, 3753 FP_VFP, 3754 FP_Neon 3755 } FPMath; 3756 3757 unsigned FPU : 5; 3758 3759 unsigned IsAAPCS : 1; 3760 unsigned IsThumb : 1; 3761 unsigned HWDiv : 2; 3762 3763 // Initialized via features. 3764 unsigned SoftFloat : 1; 3765 unsigned SoftFloatABI : 1; 3766 3767 unsigned CRC : 1; 3768 unsigned Crypto : 1; 3769 3770 // ACLE 6.5.1 Hardware floating point 3771 enum { 3772 HW_FP_HP = (1 << 1), /// half (16-bit) 3773 HW_FP_SP = (1 << 2), /// single (32-bit) 3774 HW_FP_DP = (1 << 3), /// double (64-bit) 3775 }; 3776 uint32_t HW_FP; 3777 3778 static const Builtin::Info BuiltinInfo[]; 3779 3780 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3781 StringRef ArchName = T.getArchName(); 3782 if (T.getArch() == llvm::Triple::arm || 3783 T.getArch() == llvm::Triple::armeb) { 3784 StringRef VersionStr; 3785 if (ArchName.startswith("armv")) 3786 VersionStr = ArchName.substr(4, 1); 3787 else if (ArchName.startswith("armebv")) 3788 VersionStr = ArchName.substr(6, 1); 3789 else 3790 return false; 3791 unsigned Version; 3792 if (VersionStr.getAsInteger(10, Version)) 3793 return false; 3794 return Version >= 6; 3795 } 3796 assert(T.getArch() == llvm::Triple::thumb || 3797 T.getArch() == llvm::Triple::thumbeb); 3798 StringRef VersionStr; 3799 if (ArchName.startswith("thumbv")) 3800 VersionStr = ArchName.substr(6, 1); 3801 else if (ArchName.startswith("thumbebv")) 3802 VersionStr = ArchName.substr(8, 1); 3803 else 3804 return false; 3805 unsigned Version; 3806 if (VersionStr.getAsInteger(10, Version)) 3807 return false; 3808 return Version >= 7; 3809 } 3810 3811 void setABIAAPCS() { 3812 IsAAPCS = true; 3813 3814 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3815 const llvm::Triple &T = getTriple(); 3816 3817 // size_t is unsigned long on MachO-derived environments and NetBSD. 3818 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD) 3819 SizeType = UnsignedLong; 3820 else 3821 SizeType = UnsignedInt; 3822 3823 switch (T.getOS()) { 3824 case llvm::Triple::NetBSD: 3825 WCharType = SignedInt; 3826 break; 3827 case llvm::Triple::Win32: 3828 WCharType = UnsignedShort; 3829 break; 3830 case llvm::Triple::Linux: 3831 default: 3832 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3833 WCharType = UnsignedInt; 3834 break; 3835 } 3836 3837 UseBitFieldTypeAlignment = true; 3838 3839 ZeroLengthBitfieldBoundary = 0; 3840 3841 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3842 // so set preferred for small types to 32. 3843 if (T.isOSBinFormatMachO()) { 3844 DescriptionString = 3845 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 3846 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 3847 } else if (T.isOSWindows()) { 3848 // FIXME: this is invalid for WindowsCE 3849 assert(!BigEndian && "Windows on ARM does not support big endian"); 3850 DescriptionString = "e" 3851 "-m:e" 3852 "-p:32:32" 3853 "-i64:64" 3854 "-v128:64:128" 3855 "-a:0:32" 3856 "-n32" 3857 "-S64"; 3858 } else { 3859 DescriptionString = 3860 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 3861 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 3862 } 3863 3864 // FIXME: Enumerated types are variable width in straight AAPCS. 3865 } 3866 3867 void setABIAPCS() { 3868 const llvm::Triple &T = getTriple(); 3869 3870 IsAAPCS = false; 3871 3872 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3873 3874 // size_t is unsigned int on FreeBSD. 3875 if (T.getOS() == llvm::Triple::FreeBSD) 3876 SizeType = UnsignedInt; 3877 else 3878 SizeType = UnsignedLong; 3879 3880 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3881 WCharType = SignedInt; 3882 3883 // Do not respect the alignment of bit-field types when laying out 3884 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3885 UseBitFieldTypeAlignment = false; 3886 3887 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3888 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3889 /// gcc. 3890 ZeroLengthBitfieldBoundary = 32; 3891 3892 if (T.isOSBinFormatMachO()) 3893 DescriptionString = 3894 BigEndian 3895 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 3896 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3897 else 3898 DescriptionString = 3899 BigEndian 3900 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 3901 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3902 3903 // FIXME: Override "preferred align" for double and long long. 3904 } 3905 3906 public: 3907 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 3908 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3909 IsAAPCS(true), HW_FP(0) { 3910 BigEndian = IsBigEndian; 3911 3912 switch (getTriple().getOS()) { 3913 case llvm::Triple::NetBSD: 3914 PtrDiffType = SignedLong; 3915 break; 3916 default: 3917 PtrDiffType = SignedInt; 3918 break; 3919 } 3920 3921 // {} in inline assembly are neon specifiers, not assembly variant 3922 // specifiers. 3923 NoAsmVariants = true; 3924 3925 // FIXME: Should we just treat this as a feature? 3926 IsThumb = getTriple().getArchName().startswith("thumb"); 3927 3928 // FIXME: This duplicates code from the driver that sets the -target-abi 3929 // option - this code is used if -target-abi isn't passed and should 3930 // be unified in some way. 3931 if (Triple.isOSBinFormatMachO()) { 3932 // The backend is hardwired to assume AAPCS for M-class processors, ensure 3933 // the frontend matches that. 3934 if (Triple.getEnvironment() == llvm::Triple::EABI || 3935 Triple.getOS() == llvm::Triple::UnknownOS || 3936 StringRef(CPU).startswith("cortex-m")) { 3937 setABI("aapcs"); 3938 } else { 3939 setABI("apcs-gnu"); 3940 } 3941 } else if (Triple.isOSWindows()) { 3942 // FIXME: this is invalid for WindowsCE 3943 setABI("aapcs"); 3944 } else { 3945 // Select the default based on the platform. 3946 switch (Triple.getEnvironment()) { 3947 case llvm::Triple::Android: 3948 case llvm::Triple::GNUEABI: 3949 case llvm::Triple::GNUEABIHF: 3950 setABI("aapcs-linux"); 3951 break; 3952 case llvm::Triple::EABIHF: 3953 case llvm::Triple::EABI: 3954 setABI("aapcs"); 3955 break; 3956 case llvm::Triple::GNU: 3957 setABI("apcs-gnu"); 3958 break; 3959 default: 3960 if (Triple.getOS() == llvm::Triple::NetBSD) 3961 setABI("apcs-gnu"); 3962 else 3963 setABI("aapcs"); 3964 break; 3965 } 3966 } 3967 3968 // ARM targets default to using the ARM C++ ABI. 3969 TheCXXABI.set(TargetCXXABI::GenericARM); 3970 3971 // ARM has atomics up to 8 bytes 3972 MaxAtomicPromoteWidth = 64; 3973 if (shouldUseInlineAtomic(getTriple())) 3974 MaxAtomicInlineWidth = 64; 3975 3976 // Do force alignment of members that follow zero length bitfields. If 3977 // the alignment of the zero-length bitfield is greater than the member 3978 // that follows it, `bar', `bar' will be aligned as the type of the 3979 // zero length bitfield. 3980 UseZeroLengthBitfieldAlignment = true; 3981 } 3982 StringRef getABI() const override { return ABI; } 3983 bool setABI(const std::string &Name) override { 3984 ABI = Name; 3985 3986 // The defaults (above) are for AAPCS, check if we need to change them. 3987 // 3988 // FIXME: We need support for -meabi... we could just mangle it into the 3989 // name. 3990 if (Name == "apcs-gnu") { 3991 setABIAPCS(); 3992 return true; 3993 } 3994 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 3995 setABIAAPCS(); 3996 return true; 3997 } 3998 return false; 3999 } 4000 4001 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4002 StringRef ArchName = getTriple().getArchName(); 4003 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 4004 Features["vfp2"] = true; 4005 else if (CPU == "cortex-a8" || CPU == "cortex-a9") { 4006 Features["vfp3"] = true; 4007 Features["neon"] = true; 4008 } 4009 else if (CPU == "cortex-a5") { 4010 Features["vfp4"] = true; 4011 Features["neon"] = true; 4012 } else if (CPU == "swift" || CPU == "cortex-a7" || 4013 CPU == "cortex-a12" || CPU == "cortex-a15" || 4014 CPU == "cortex-a17" || CPU == "krait") { 4015 Features["vfp4"] = true; 4016 Features["neon"] = true; 4017 Features["hwdiv"] = true; 4018 Features["hwdiv-arm"] = true; 4019 } else if (CPU == "cyclone") { 4020 Features["v8fp"] = true; 4021 Features["neon"] = true; 4022 Features["hwdiv"] = true; 4023 Features["hwdiv-arm"] = true; 4024 } else if (CPU == "cortex-a53" || CPU == "cortex-a57" || CPU == "cortex-a72") { 4025 Features["fp-armv8"] = true; 4026 Features["neon"] = true; 4027 Features["hwdiv"] = true; 4028 Features["hwdiv-arm"] = true; 4029 Features["crc"] = true; 4030 Features["crypto"] = true; 4031 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || 4032 // Enable the hwdiv extension for all v8a AArch32 cores by 4033 // default. 4034 ArchName == "armv8a" || ArchName == "armv8" || 4035 ArchName == "armebv8a" || ArchName == "armebv8" || 4036 ArchName == "thumbv8a" || ArchName == "thumbv8" || 4037 ArchName == "thumbebv8a" || ArchName == "thumbebv8") { 4038 Features["hwdiv"] = true; 4039 Features["hwdiv-arm"] = true; 4040 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" || 4041 CPU == "sc300") { 4042 Features["hwdiv"] = true; 4043 } 4044 } 4045 4046 bool handleTargetFeatures(std::vector<std::string> &Features, 4047 DiagnosticsEngine &Diags) override { 4048 FPU = 0; 4049 CRC = 0; 4050 Crypto = 0; 4051 SoftFloat = SoftFloatABI = false; 4052 HWDiv = 0; 4053 4054 for (const auto &Feature : Features) { 4055 if (Feature == "+soft-float") { 4056 SoftFloat = true; 4057 } else if (Feature == "+soft-float-abi") { 4058 SoftFloatABI = true; 4059 } else if (Feature == "+vfp2") { 4060 FPU |= VFP2FPU; 4061 HW_FP = HW_FP_SP | HW_FP_DP; 4062 } else if (Feature == "+vfp3") { 4063 FPU |= VFP3FPU; 4064 HW_FP = HW_FP_SP | HW_FP_DP; 4065 } else if (Feature == "+vfp4") { 4066 FPU |= VFP4FPU; 4067 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 4068 } else if (Feature == "+fp-armv8") { 4069 FPU |= FPARMV8; 4070 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 4071 } else if (Feature == "+neon") { 4072 FPU |= NeonFPU; 4073 HW_FP = HW_FP_SP | HW_FP_DP; 4074 } else if (Feature == "+hwdiv") { 4075 HWDiv |= HWDivThumb; 4076 } else if (Feature == "+hwdiv-arm") { 4077 HWDiv |= HWDivARM; 4078 } else if (Feature == "+crc") { 4079 CRC = 1; 4080 } else if (Feature == "+crypto") { 4081 Crypto = 1; 4082 } else if (Feature == "+fp-only-sp") { 4083 HW_FP &= ~HW_FP_DP; 4084 } 4085 } 4086 4087 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4088 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4089 return false; 4090 } 4091 4092 if (FPMath == FP_Neon) 4093 Features.push_back("+neonfp"); 4094 else if (FPMath == FP_VFP) 4095 Features.push_back("-neonfp"); 4096 4097 // Remove front-end specific options which the backend handles differently. 4098 const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" }; 4099 for (const auto &FEFeature : FrontEndFeatures) { 4100 auto Feature = std::find(Features.begin(), Features.end(), FEFeature); 4101 if (Feature != Features.end()) 4102 Features.erase(Feature); 4103 } 4104 4105 return true; 4106 } 4107 4108 bool hasFeature(StringRef Feature) const override { 4109 return llvm::StringSwitch<bool>(Feature) 4110 .Case("arm", true) 4111 .Case("softfloat", SoftFloat) 4112 .Case("thumb", IsThumb) 4113 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4114 .Case("hwdiv", HWDiv & HWDivThumb) 4115 .Case("hwdiv-arm", HWDiv & HWDivARM) 4116 .Default(false); 4117 } 4118 // FIXME: Should we actually have some table instead of these switches? 4119 static const char *getCPUDefineSuffix(StringRef Name) { 4120 return llvm::StringSwitch<const char *>(Name) 4121 .Cases("arm8", "arm810", "4") 4122 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", 4123 "4") 4124 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 4125 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 4126 .Case("ep9312", "4T") 4127 .Cases("arm10tdmi", "arm1020t", "5T") 4128 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 4129 .Case("arm926ej-s", "5TEJ") 4130 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 4131 .Cases("xscale", "iwmmxt", "5TE") 4132 .Case("arm1136j-s", "6J") 4133 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 4134 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 4135 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 4136 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A") 4137 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", 4138 "7A") 4139 .Cases("cortex-r4", "cortex-r5", "cortex-r7", "7R") 4140 .Case("swift", "7S") 4141 .Case("cyclone", "8A") 4142 .Cases("sc300", "cortex-m3", "7M") 4143 .Cases("cortex-m4", "cortex-m7", "7EM") 4144 .Cases("sc000", "cortex-m0", "cortex-m0plus", "cortex-m1", "6M") 4145 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "8A") 4146 .Default(nullptr); 4147 } 4148 static const char *getCPUProfile(StringRef Name) { 4149 return llvm::StringSwitch<const char *>(Name) 4150 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 4151 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", 4152 "A") 4153 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "A") 4154 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m0plus", "M") 4155 .Cases("cortex-m1", "cortex-m7", "sc000", "sc300", "M") 4156 .Cases("cortex-r4", "cortex-r5", "cortex-r7", "R") 4157 .Default(""); 4158 } 4159 bool setCPU(const std::string &Name) override { 4160 if (!getCPUDefineSuffix(Name)) 4161 return false; 4162 4163 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4164 StringRef Profile = getCPUProfile(Name); 4165 if (Profile == "M" && MaxAtomicInlineWidth) { 4166 MaxAtomicPromoteWidth = 32; 4167 MaxAtomicInlineWidth = 32; 4168 } 4169 4170 CPU = Name; 4171 return true; 4172 } 4173 bool setFPMath(StringRef Name) override; 4174 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 4175 unsigned CPUArchVer) const { 4176 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 4177 (CPUArch.find('M') != StringRef::npos); 4178 } 4179 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 4180 unsigned CPUArchVer) const { 4181 // We check both CPUArchVer and ArchName because when only triple is 4182 // specified, the default CPU is arm1136j-s. 4183 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 4184 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 4185 } 4186 void getTargetDefines(const LangOptions &Opts, 4187 MacroBuilder &Builder) const override { 4188 // Target identification. 4189 Builder.defineMacro("__arm"); 4190 Builder.defineMacro("__arm__"); 4191 4192 // Target properties. 4193 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4194 4195 StringRef CPUArch = getCPUDefineSuffix(CPU); 4196 unsigned int CPUArchVer; 4197 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) 4198 llvm_unreachable("Invalid char for architecture version number"); 4199 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4200 4201 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4202 StringRef CPUProfile = getCPUProfile(CPU); 4203 StringRef ArchName = getTriple().getArchName(); 4204 4205 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4206 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4207 if (CPUArch[0] >= '8') { 4208 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4209 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4210 } 4211 4212 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4213 // is not defined for the M-profile. 4214 // NOTE that the deffault profile is assumed to be 'A' 4215 if (CPUProfile.empty() || CPUProfile != "M") 4216 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4217 4218 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4219 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4220 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4221 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4222 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4223 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 4224 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4225 4226 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4227 // instruction set such as ARM or Thumb. 4228 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4229 4230 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4231 4232 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4233 if (!CPUProfile.empty()) 4234 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4235 4236 // ACLE 6.5.1 Hardware Floating Point 4237 if (HW_FP) 4238 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4239 4240 // ACLE predefines. 4241 Builder.defineMacro("__ARM_ACLE", "200"); 4242 4243 // Subtarget options. 4244 4245 // FIXME: It's more complicated than this and we don't really support 4246 // interworking. 4247 // Windows on ARM does not "support" interworking 4248 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 4249 Builder.defineMacro("__THUMB_INTERWORK__"); 4250 4251 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4252 // Embedded targets on Darwin follow AAPCS, but not EABI. 4253 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4254 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4255 Builder.defineMacro("__ARM_EABI__"); 4256 Builder.defineMacro("__ARM_PCS", "1"); 4257 4258 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4259 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4260 } 4261 4262 if (SoftFloat) 4263 Builder.defineMacro("__SOFTFP__"); 4264 4265 if (CPU == "xscale") 4266 Builder.defineMacro("__XSCALE__"); 4267 4268 if (IsThumb) { 4269 Builder.defineMacro("__THUMBEL__"); 4270 Builder.defineMacro("__thumb__"); 4271 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4272 Builder.defineMacro("__thumb2__"); 4273 } 4274 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4275 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4276 4277 // Note, this is always on in gcc, even though it doesn't make sense. 4278 Builder.defineMacro("__APCS_32__"); 4279 4280 if (FPUModeIsVFP((FPUMode) FPU)) { 4281 Builder.defineMacro("__VFP_FP__"); 4282 if (FPU & VFP2FPU) 4283 Builder.defineMacro("__ARM_VFPV2__"); 4284 if (FPU & VFP3FPU) 4285 Builder.defineMacro("__ARM_VFPV3__"); 4286 if (FPU & VFP4FPU) 4287 Builder.defineMacro("__ARM_VFPV4__"); 4288 } 4289 4290 // This only gets set when Neon instructions are actually available, unlike 4291 // the VFP define, hence the soft float and arch check. This is subtly 4292 // different from gcc, we follow the intent which was that it should be set 4293 // when Neon instructions are actually available. 4294 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4295 Builder.defineMacro("__ARM_NEON"); 4296 Builder.defineMacro("__ARM_NEON__"); 4297 } 4298 4299 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4300 Opts.ShortWChar ? "2" : "4"); 4301 4302 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4303 Opts.ShortEnums ? "1" : "4"); 4304 4305 if (CRC) 4306 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4307 4308 if (Crypto) 4309 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4310 4311 if (CPUArchVer >= 6 && CPUArch != "6M") { 4312 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4313 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4314 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4315 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4316 } 4317 4318 bool is5EOrAbove = (CPUArchVer >= 6 || 4319 (CPUArchVer == 5 && 4320 CPUArch.find('E') != StringRef::npos)); 4321 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer)); 4322 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM")) 4323 Builder.defineMacro("__ARM_FEATURE_DSP"); 4324 } 4325 void getTargetBuiltins(const Builtin::Info *&Records, 4326 unsigned &NumRecords) const override { 4327 Records = BuiltinInfo; 4328 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4329 } 4330 bool isCLZForZeroUndef() const override { return false; } 4331 BuiltinVaListKind getBuiltinVaListKind() const override { 4332 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4333 } 4334 void getGCCRegNames(const char * const *&Names, 4335 unsigned &NumNames) const override; 4336 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4337 unsigned &NumAliases) const override; 4338 bool validateAsmConstraint(const char *&Name, 4339 TargetInfo::ConstraintInfo &Info) const override { 4340 switch (*Name) { 4341 default: break; 4342 case 'l': // r0-r7 4343 case 'h': // r8-r15 4344 case 'w': // VFP Floating point register single precision 4345 case 'P': // VFP Floating point register double precision 4346 Info.setAllowsRegister(); 4347 return true; 4348 case 'I': 4349 case 'J': 4350 case 'K': 4351 case 'L': 4352 case 'M': 4353 // FIXME 4354 return true; 4355 case 'Q': // A memory address that is a single base register. 4356 Info.setAllowsMemory(); 4357 return true; 4358 case 'U': // a memory reference... 4359 switch (Name[1]) { 4360 case 'q': // ...ARMV4 ldrsb 4361 case 'v': // ...VFP load/store (reg+constant offset) 4362 case 'y': // ...iWMMXt load/store 4363 case 't': // address valid for load/store opaque types wider 4364 // than 128-bits 4365 case 'n': // valid address for Neon doubleword vector load/store 4366 case 'm': // valid address for Neon element and structure load/store 4367 case 's': // valid address for non-offset loads/stores of quad-word 4368 // values in four ARM registers 4369 Info.setAllowsMemory(); 4370 Name++; 4371 return true; 4372 } 4373 } 4374 return false; 4375 } 4376 std::string convertConstraint(const char *&Constraint) const override { 4377 std::string R; 4378 switch (*Constraint) { 4379 case 'U': // Two-character constraint; add "^" hint for later parsing. 4380 R = std::string("^") + std::string(Constraint, 2); 4381 Constraint++; 4382 break; 4383 case 'p': // 'p' should be translated to 'r' by default. 4384 R = std::string("r"); 4385 break; 4386 default: 4387 return std::string(1, *Constraint); 4388 } 4389 return R; 4390 } 4391 bool 4392 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4393 std::string &SuggestedModifier) const override { 4394 bool isOutput = (Constraint[0] == '='); 4395 bool isInOut = (Constraint[0] == '+'); 4396 4397 // Strip off constraint modifiers. 4398 while (Constraint[0] == '=' || 4399 Constraint[0] == '+' || 4400 Constraint[0] == '&') 4401 Constraint = Constraint.substr(1); 4402 4403 switch (Constraint[0]) { 4404 default: break; 4405 case 'r': { 4406 switch (Modifier) { 4407 default: 4408 return (isInOut || isOutput || Size <= 64); 4409 case 'q': 4410 // A register of size 32 cannot fit a vector type. 4411 return false; 4412 } 4413 } 4414 } 4415 4416 return true; 4417 } 4418 const char *getClobbers() const override { 4419 // FIXME: Is this really right? 4420 return ""; 4421 } 4422 4423 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4424 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4425 } 4426 4427 int getEHDataRegisterNumber(unsigned RegNo) const override { 4428 if (RegNo == 0) return 0; 4429 if (RegNo == 1) return 1; 4430 return -1; 4431 } 4432 }; 4433 4434 bool ARMTargetInfo::setFPMath(StringRef Name) { 4435 if (Name == "neon") { 4436 FPMath = FP_Neon; 4437 return true; 4438 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4439 Name == "vfp4") { 4440 FPMath = FP_VFP; 4441 return true; 4442 } 4443 return false; 4444 } 4445 4446 const char * const ARMTargetInfo::GCCRegNames[] = { 4447 // Integer registers 4448 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4449 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4450 4451 // Float registers 4452 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4453 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4454 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4455 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4456 4457 // Double registers 4458 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4459 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4460 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4461 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4462 4463 // Quad registers 4464 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4465 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4466 }; 4467 4468 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4469 unsigned &NumNames) const { 4470 Names = GCCRegNames; 4471 NumNames = llvm::array_lengthof(GCCRegNames); 4472 } 4473 4474 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4475 { { "a1" }, "r0" }, 4476 { { "a2" }, "r1" }, 4477 { { "a3" }, "r2" }, 4478 { { "a4" }, "r3" }, 4479 { { "v1" }, "r4" }, 4480 { { "v2" }, "r5" }, 4481 { { "v3" }, "r6" }, 4482 { { "v4" }, "r7" }, 4483 { { "v5" }, "r8" }, 4484 { { "v6", "rfp" }, "r9" }, 4485 { { "sl" }, "r10" }, 4486 { { "fp" }, "r11" }, 4487 { { "ip" }, "r12" }, 4488 { { "r13" }, "sp" }, 4489 { { "r14" }, "lr" }, 4490 { { "r15" }, "pc" }, 4491 // The S, D and Q registers overlap, but aren't really aliases; we 4492 // don't want to substitute one of these for a different-sized one. 4493 }; 4494 4495 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4496 unsigned &NumAliases) const { 4497 Aliases = GCCRegAliases; 4498 NumAliases = llvm::array_lengthof(GCCRegAliases); 4499 } 4500 4501 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4502 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4503 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4504 ALL_LANGUAGES }, 4505 #include "clang/Basic/BuiltinsNEON.def" 4506 4507 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4508 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG }, 4509 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4510 ALL_LANGUAGES }, 4511 #include "clang/Basic/BuiltinsARM.def" 4512 }; 4513 4514 class ARMleTargetInfo : public ARMTargetInfo { 4515 public: 4516 ARMleTargetInfo(const llvm::Triple &Triple) 4517 : ARMTargetInfo(Triple, false) { } 4518 virtual void getTargetDefines(const LangOptions &Opts, 4519 MacroBuilder &Builder) const { 4520 Builder.defineMacro("__ARMEL__"); 4521 ARMTargetInfo::getTargetDefines(Opts, Builder); 4522 } 4523 }; 4524 4525 class ARMbeTargetInfo : public ARMTargetInfo { 4526 public: 4527 ARMbeTargetInfo(const llvm::Triple &Triple) 4528 : ARMTargetInfo(Triple, true) { } 4529 virtual void getTargetDefines(const LangOptions &Opts, 4530 MacroBuilder &Builder) const { 4531 Builder.defineMacro("__ARMEB__"); 4532 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4533 ARMTargetInfo::getTargetDefines(Opts, Builder); 4534 } 4535 }; 4536 } // end anonymous namespace. 4537 4538 namespace { 4539 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4540 const llvm::Triple Triple; 4541 public: 4542 WindowsARMTargetInfo(const llvm::Triple &Triple) 4543 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4544 TLSSupported = false; 4545 WCharType = UnsignedShort; 4546 SizeType = UnsignedInt; 4547 UserLabelPrefix = ""; 4548 } 4549 void getVisualStudioDefines(const LangOptions &Opts, 4550 MacroBuilder &Builder) const { 4551 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4552 4553 // FIXME: this is invalid for WindowsCE 4554 Builder.defineMacro("_M_ARM_NT", "1"); 4555 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4556 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4557 4558 assert((Triple.getArch() == llvm::Triple::arm || 4559 Triple.getArch() == llvm::Triple::thumb) && 4560 "invalid architecture for Windows ARM target info"); 4561 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4562 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4563 4564 // TODO map the complete set of values 4565 // 31: VFPv3 40: VFPv4 4566 Builder.defineMacro("_M_ARM_FP", "31"); 4567 } 4568 BuiltinVaListKind getBuiltinVaListKind() const override { 4569 return TargetInfo::CharPtrBuiltinVaList; 4570 } 4571 }; 4572 4573 // Windows ARM + Itanium C++ ABI Target 4574 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4575 public: 4576 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4577 : WindowsARMTargetInfo(Triple) { 4578 TheCXXABI.set(TargetCXXABI::GenericARM); 4579 } 4580 4581 void getTargetDefines(const LangOptions &Opts, 4582 MacroBuilder &Builder) const override { 4583 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4584 4585 if (Opts.MSVCCompat) 4586 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4587 } 4588 }; 4589 4590 // Windows ARM, MS (C++) ABI 4591 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4592 public: 4593 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4594 : WindowsARMTargetInfo(Triple) { 4595 TheCXXABI.set(TargetCXXABI::Microsoft); 4596 } 4597 4598 void getTargetDefines(const LangOptions &Opts, 4599 MacroBuilder &Builder) const override { 4600 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4601 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4602 } 4603 }; 4604 } 4605 4606 4607 namespace { 4608 class DarwinARMTargetInfo : 4609 public DarwinTargetInfo<ARMleTargetInfo> { 4610 protected: 4611 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4612 MacroBuilder &Builder) const override { 4613 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4614 } 4615 4616 public: 4617 DarwinARMTargetInfo(const llvm::Triple &Triple) 4618 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4619 HasAlignMac68kSupport = true; 4620 // iOS always has 64-bit atomic instructions. 4621 // FIXME: This should be based off of the target features in 4622 // ARMleTargetInfo. 4623 MaxAtomicInlineWidth = 64; 4624 4625 // Darwin on iOS uses a variant of the ARM C++ ABI. 4626 TheCXXABI.set(TargetCXXABI::iOS); 4627 } 4628 }; 4629 } // end anonymous namespace. 4630 4631 4632 namespace { 4633 class AArch64TargetInfo : public TargetInfo { 4634 virtual void setDescriptionString() = 0; 4635 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4636 static const char *const GCCRegNames[]; 4637 4638 enum FPUModeEnum { 4639 FPUMode, 4640 NeonMode 4641 }; 4642 4643 unsigned FPU; 4644 unsigned CRC; 4645 unsigned Crypto; 4646 4647 static const Builtin::Info BuiltinInfo[]; 4648 4649 std::string ABI; 4650 4651 public: 4652 AArch64TargetInfo(const llvm::Triple &Triple) 4653 : TargetInfo(Triple), ABI("aapcs") { 4654 4655 if (getTriple().getOS() == llvm::Triple::NetBSD) { 4656 WCharType = SignedInt; 4657 4658 // NetBSD apparently prefers consistency across ARM targets to consistency 4659 // across 64-bit targets. 4660 Int64Type = SignedLongLong; 4661 IntMaxType = SignedLongLong; 4662 } else { 4663 WCharType = UnsignedInt; 4664 Int64Type = SignedLong; 4665 IntMaxType = SignedLong; 4666 } 4667 4668 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4669 MaxVectorAlign = 128; 4670 RegParmMax = 8; 4671 MaxAtomicInlineWidth = 128; 4672 MaxAtomicPromoteWidth = 128; 4673 4674 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 4675 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4676 4677 // {} in inline assembly are neon specifiers, not assembly variant 4678 // specifiers. 4679 NoAsmVariants = true; 4680 4681 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 4682 // contributes to the alignment of the containing aggregate in the same way 4683 // a plain (non bit-field) member of that type would, without exception for 4684 // zero-sized or anonymous bit-fields." 4685 UseBitFieldTypeAlignment = true; 4686 UseZeroLengthBitfieldAlignment = true; 4687 4688 // AArch64 targets default to using the ARM C++ ABI. 4689 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4690 } 4691 4692 StringRef getABI() const override { return ABI; } 4693 bool setABI(const std::string &Name) override { 4694 if (Name != "aapcs" && Name != "darwinpcs") 4695 return false; 4696 4697 ABI = Name; 4698 return true; 4699 } 4700 4701 bool setCPU(const std::string &Name) override { 4702 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4703 .Case("generic", true) 4704 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 4705 .Case("cyclone", true) 4706 .Default(false); 4707 return CPUKnown; 4708 } 4709 4710 virtual void getTargetDefines(const LangOptions &Opts, 4711 MacroBuilder &Builder) const override { 4712 // Target identification. 4713 Builder.defineMacro("__aarch64__"); 4714 4715 // Target properties. 4716 Builder.defineMacro("_LP64"); 4717 Builder.defineMacro("__LP64__"); 4718 4719 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4720 Builder.defineMacro("__ARM_ACLE", "200"); 4721 Builder.defineMacro("__ARM_ARCH", "8"); 4722 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4723 4724 Builder.defineMacro("__ARM_64BIT_STATE"); 4725 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4726 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4727 4728 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4729 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4730 Builder.defineMacro("__ARM_FEATURE_FMA"); 4731 Builder.defineMacro("__ARM_FEATURE_DIV"); 4732 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE 4733 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 4734 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4735 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4736 4737 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 4738 4739 // 0xe implies support for half, single and double precision operations. 4740 Builder.defineMacro("__ARM_FP", "0xe"); 4741 4742 // PCS specifies this for SysV variants, which is all we support. Other ABIs 4743 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 4744 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 4745 4746 if (Opts.FastMath || Opts.FiniteMathOnly) 4747 Builder.defineMacro("__ARM_FP_FAST"); 4748 4749 if (Opts.C99 && !Opts.Freestanding) 4750 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 4751 4752 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 4753 4754 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4755 Opts.ShortEnums ? "1" : "4"); 4756 4757 if (FPU == NeonMode) { 4758 Builder.defineMacro("__ARM_NEON"); 4759 // 64-bit NEON supports half, single and double precision operations. 4760 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 4761 } 4762 4763 if (CRC) 4764 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4765 4766 if (Crypto) 4767 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4768 } 4769 4770 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4771 unsigned &NumRecords) const override { 4772 Records = BuiltinInfo; 4773 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 4774 } 4775 4776 bool hasFeature(StringRef Feature) const override { 4777 return Feature == "aarch64" || 4778 Feature == "arm64" || 4779 (Feature == "neon" && FPU == NeonMode); 4780 } 4781 4782 bool handleTargetFeatures(std::vector<std::string> &Features, 4783 DiagnosticsEngine &Diags) override { 4784 FPU = FPUMode; 4785 CRC = 0; 4786 Crypto = 0; 4787 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 4788 if (Features[i] == "+neon") 4789 FPU = NeonMode; 4790 if (Features[i] == "+crc") 4791 CRC = 1; 4792 if (Features[i] == "+crypto") 4793 Crypto = 1; 4794 } 4795 4796 setDescriptionString(); 4797 4798 return true; 4799 } 4800 4801 bool isCLZForZeroUndef() const override { return false; } 4802 4803 BuiltinVaListKind getBuiltinVaListKind() const override { 4804 return TargetInfo::AArch64ABIBuiltinVaList; 4805 } 4806 4807 virtual void getGCCRegNames(const char *const *&Names, 4808 unsigned &NumNames) const override; 4809 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4810 unsigned &NumAliases) const override; 4811 4812 virtual bool 4813 validateAsmConstraint(const char *&Name, 4814 TargetInfo::ConstraintInfo &Info) const override { 4815 switch (*Name) { 4816 default: 4817 return false; 4818 case 'w': // Floating point and SIMD registers (V0-V31) 4819 Info.setAllowsRegister(); 4820 return true; 4821 case 'I': // Constant that can be used with an ADD instruction 4822 case 'J': // Constant that can be used with a SUB instruction 4823 case 'K': // Constant that can be used with a 32-bit logical instruction 4824 case 'L': // Constant that can be used with a 64-bit logical instruction 4825 case 'M': // Constant that can be used as a 32-bit MOV immediate 4826 case 'N': // Constant that can be used as a 64-bit MOV immediate 4827 case 'Y': // Floating point constant zero 4828 case 'Z': // Integer constant zero 4829 return true; 4830 case 'Q': // A memory reference with base register and no offset 4831 Info.setAllowsMemory(); 4832 return true; 4833 case 'S': // A symbolic address 4834 Info.setAllowsRegister(); 4835 return true; 4836 case 'U': 4837 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 4838 // Utf: A memory address suitable for ldp/stp in TF mode. 4839 // Usa: An absolute symbolic address. 4840 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 4841 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 4842 case 'z': // Zero register, wzr or xzr 4843 Info.setAllowsRegister(); 4844 return true; 4845 case 'x': // Floating point and SIMD registers (V0-V15) 4846 Info.setAllowsRegister(); 4847 return true; 4848 } 4849 return false; 4850 } 4851 4852 bool 4853 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4854 std::string &SuggestedModifier) const override { 4855 // Strip off constraint modifiers. 4856 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 4857 Constraint = Constraint.substr(1); 4858 4859 switch (Constraint[0]) { 4860 default: 4861 return true; 4862 case 'z': 4863 case 'r': { 4864 switch (Modifier) { 4865 case 'x': 4866 case 'w': 4867 // For now assume that the person knows what they're 4868 // doing with the modifier. 4869 return true; 4870 default: 4871 // By default an 'r' constraint will be in the 'x' 4872 // registers. 4873 if (Size == 64) 4874 return true; 4875 4876 SuggestedModifier = "w"; 4877 return false; 4878 } 4879 } 4880 } 4881 } 4882 4883 const char *getClobbers() const override { return ""; } 4884 4885 int getEHDataRegisterNumber(unsigned RegNo) const override { 4886 if (RegNo == 0) 4887 return 0; 4888 if (RegNo == 1) 4889 return 1; 4890 return -1; 4891 } 4892 }; 4893 4894 const char *const AArch64TargetInfo::GCCRegNames[] = { 4895 // 32-bit Integer registers 4896 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 4897 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 4898 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 4899 4900 // 64-bit Integer registers 4901 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 4902 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 4903 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 4904 4905 // 32-bit floating point regsisters 4906 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 4907 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 4908 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4909 4910 // 64-bit floating point regsisters 4911 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 4912 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 4913 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4914 4915 // Vector registers 4916 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 4917 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 4918 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 4919 }; 4920 4921 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 4922 unsigned &NumNames) const { 4923 Names = GCCRegNames; 4924 NumNames = llvm::array_lengthof(GCCRegNames); 4925 } 4926 4927 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 4928 { { "w31" }, "wsp" }, 4929 { { "x29" }, "fp" }, 4930 { { "x30" }, "lr" }, 4931 { { "x31" }, "sp" }, 4932 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 4933 // don't want to substitute one of these for a different-sized one. 4934 }; 4935 4936 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4937 unsigned &NumAliases) const { 4938 Aliases = GCCRegAliases; 4939 NumAliases = llvm::array_lengthof(GCCRegAliases); 4940 } 4941 4942 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 4943 #define BUILTIN(ID, TYPE, ATTRS) \ 4944 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4945 #include "clang/Basic/BuiltinsNEON.def" 4946 4947 #define BUILTIN(ID, TYPE, ATTRS) \ 4948 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4949 #include "clang/Basic/BuiltinsAArch64.def" 4950 }; 4951 4952 class AArch64leTargetInfo : public AArch64TargetInfo { 4953 void setDescriptionString() override { 4954 if (getTriple().isOSBinFormatMachO()) 4955 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 4956 else 4957 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 4958 } 4959 4960 public: 4961 AArch64leTargetInfo(const llvm::Triple &Triple) 4962 : AArch64TargetInfo(Triple) { 4963 BigEndian = false; 4964 } 4965 void getTargetDefines(const LangOptions &Opts, 4966 MacroBuilder &Builder) const override { 4967 Builder.defineMacro("__AARCH64EL__"); 4968 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4969 } 4970 }; 4971 4972 class AArch64beTargetInfo : public AArch64TargetInfo { 4973 void setDescriptionString() override { 4974 assert(!getTriple().isOSBinFormatMachO()); 4975 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 4976 } 4977 4978 public: 4979 AArch64beTargetInfo(const llvm::Triple &Triple) 4980 : AArch64TargetInfo(Triple) { } 4981 void getTargetDefines(const LangOptions &Opts, 4982 MacroBuilder &Builder) const override { 4983 Builder.defineMacro("__AARCH64EB__"); 4984 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 4985 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4986 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4987 } 4988 }; 4989 } // end anonymous namespace. 4990 4991 namespace { 4992 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 4993 protected: 4994 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4995 MacroBuilder &Builder) const override { 4996 Builder.defineMacro("__AARCH64_SIMD__"); 4997 Builder.defineMacro("__ARM64_ARCH_8__"); 4998 Builder.defineMacro("__ARM_NEON__"); 4999 Builder.defineMacro("__LITTLE_ENDIAN__"); 5000 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5001 Builder.defineMacro("__arm64", "1"); 5002 Builder.defineMacro("__arm64__", "1"); 5003 5004 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5005 } 5006 5007 public: 5008 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5009 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5010 Int64Type = SignedLongLong; 5011 WCharType = SignedInt; 5012 UseSignedCharForObjCBool = false; 5013 5014 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5015 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5016 5017 TheCXXABI.set(TargetCXXABI::iOS64); 5018 } 5019 5020 BuiltinVaListKind getBuiltinVaListKind() const override { 5021 return TargetInfo::CharPtrBuiltinVaList; 5022 } 5023 }; 5024 } // end anonymous namespace 5025 5026 namespace { 5027 // Hexagon abstract base class 5028 class HexagonTargetInfo : public TargetInfo { 5029 static const Builtin::Info BuiltinInfo[]; 5030 static const char * const GCCRegNames[]; 5031 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5032 std::string CPU; 5033 public: 5034 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5035 BigEndian = false; 5036 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5037 5038 // {} in inline assembly are packet specifiers, not assembly variant 5039 // specifiers. 5040 NoAsmVariants = true; 5041 } 5042 5043 void getTargetBuiltins(const Builtin::Info *&Records, 5044 unsigned &NumRecords) const override { 5045 Records = BuiltinInfo; 5046 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5047 } 5048 5049 bool validateAsmConstraint(const char *&Name, 5050 TargetInfo::ConstraintInfo &Info) const override { 5051 return true; 5052 } 5053 5054 void getTargetDefines(const LangOptions &Opts, 5055 MacroBuilder &Builder) const override; 5056 5057 bool hasFeature(StringRef Feature) const override { 5058 return Feature == "hexagon"; 5059 } 5060 5061 BuiltinVaListKind getBuiltinVaListKind() const override { 5062 return TargetInfo::CharPtrBuiltinVaList; 5063 } 5064 void getGCCRegNames(const char * const *&Names, 5065 unsigned &NumNames) const override; 5066 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5067 unsigned &NumAliases) const override; 5068 const char *getClobbers() const override { 5069 return ""; 5070 } 5071 5072 static const char *getHexagonCPUSuffix(StringRef Name) { 5073 return llvm::StringSwitch<const char*>(Name) 5074 .Case("hexagonv4", "4") 5075 .Case("hexagonv5", "5") 5076 .Default(nullptr); 5077 } 5078 5079 bool setCPU(const std::string &Name) override { 5080 if (!getHexagonCPUSuffix(Name)) 5081 return false; 5082 5083 CPU = Name; 5084 return true; 5085 } 5086 }; 5087 5088 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5089 MacroBuilder &Builder) const { 5090 Builder.defineMacro("qdsp6"); 5091 Builder.defineMacro("__qdsp6", "1"); 5092 Builder.defineMacro("__qdsp6__", "1"); 5093 5094 Builder.defineMacro("hexagon"); 5095 Builder.defineMacro("__hexagon", "1"); 5096 Builder.defineMacro("__hexagon__", "1"); 5097 5098 if(CPU == "hexagonv1") { 5099 Builder.defineMacro("__HEXAGON_V1__"); 5100 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5101 if(Opts.HexagonQdsp6Compat) { 5102 Builder.defineMacro("__QDSP6_V1__"); 5103 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5104 } 5105 } 5106 else if(CPU == "hexagonv2") { 5107 Builder.defineMacro("__HEXAGON_V2__"); 5108 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5109 if(Opts.HexagonQdsp6Compat) { 5110 Builder.defineMacro("__QDSP6_V2__"); 5111 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5112 } 5113 } 5114 else if(CPU == "hexagonv3") { 5115 Builder.defineMacro("__HEXAGON_V3__"); 5116 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5117 if(Opts.HexagonQdsp6Compat) { 5118 Builder.defineMacro("__QDSP6_V3__"); 5119 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5120 } 5121 } 5122 else if(CPU == "hexagonv4") { 5123 Builder.defineMacro("__HEXAGON_V4__"); 5124 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5125 if(Opts.HexagonQdsp6Compat) { 5126 Builder.defineMacro("__QDSP6_V4__"); 5127 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5128 } 5129 } 5130 else if(CPU == "hexagonv5") { 5131 Builder.defineMacro("__HEXAGON_V5__"); 5132 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5133 if(Opts.HexagonQdsp6Compat) { 5134 Builder.defineMacro("__QDSP6_V5__"); 5135 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5136 } 5137 } 5138 } 5139 5140 const char * const HexagonTargetInfo::GCCRegNames[] = { 5141 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5142 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5143 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5144 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5145 "p0", "p1", "p2", "p3", 5146 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5147 }; 5148 5149 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5150 unsigned &NumNames) const { 5151 Names = GCCRegNames; 5152 NumNames = llvm::array_lengthof(GCCRegNames); 5153 } 5154 5155 5156 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5157 { { "sp" }, "r29" }, 5158 { { "fp" }, "r30" }, 5159 { { "lr" }, "r31" }, 5160 }; 5161 5162 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5163 unsigned &NumAliases) const { 5164 Aliases = GCCRegAliases; 5165 NumAliases = llvm::array_lengthof(GCCRegAliases); 5166 } 5167 5168 5169 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5170 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5171 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5172 ALL_LANGUAGES }, 5173 #include "clang/Basic/BuiltinsHexagon.def" 5174 }; 5175 } 5176 5177 5178 namespace { 5179 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5180 class SparcTargetInfo : public TargetInfo { 5181 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5182 static const char * const GCCRegNames[]; 5183 bool SoftFloat; 5184 public: 5185 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 5186 5187 bool handleTargetFeatures(std::vector<std::string> &Features, 5188 DiagnosticsEngine &Diags) override { 5189 SoftFloat = false; 5190 for (unsigned i = 0, e = Features.size(); i != e; ++i) 5191 if (Features[i] == "+soft-float") 5192 SoftFloat = true; 5193 return true; 5194 } 5195 void getTargetDefines(const LangOptions &Opts, 5196 MacroBuilder &Builder) const override { 5197 DefineStd(Builder, "sparc", Opts); 5198 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5199 5200 if (SoftFloat) 5201 Builder.defineMacro("SOFT_FLOAT", "1"); 5202 } 5203 5204 bool hasFeature(StringRef Feature) const override { 5205 return llvm::StringSwitch<bool>(Feature) 5206 .Case("softfloat", SoftFloat) 5207 .Case("sparc", true) 5208 .Default(false); 5209 } 5210 5211 void getTargetBuiltins(const Builtin::Info *&Records, 5212 unsigned &NumRecords) const override { 5213 // FIXME: Implement! 5214 } 5215 BuiltinVaListKind getBuiltinVaListKind() const override { 5216 return TargetInfo::VoidPtrBuiltinVaList; 5217 } 5218 void getGCCRegNames(const char * const *&Names, 5219 unsigned &NumNames) const override; 5220 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5221 unsigned &NumAliases) const override; 5222 bool validateAsmConstraint(const char *&Name, 5223 TargetInfo::ConstraintInfo &info) const override { 5224 // FIXME: Implement! 5225 switch (*Name) { 5226 case 'I': // Signed 13-bit constant 5227 case 'J': // Zero 5228 case 'K': // 32-bit constant with the low 12 bits clear 5229 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5230 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5231 case 'N': // Same as 'K' but zext (required for SIMode) 5232 case 'O': // The constant 4096 5233 return true; 5234 } 5235 return false; 5236 } 5237 const char *getClobbers() const override { 5238 // FIXME: Implement! 5239 return ""; 5240 } 5241 }; 5242 5243 const char * const SparcTargetInfo::GCCRegNames[] = { 5244 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5245 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5246 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5247 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5248 }; 5249 5250 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5251 unsigned &NumNames) const { 5252 Names = GCCRegNames; 5253 NumNames = llvm::array_lengthof(GCCRegNames); 5254 } 5255 5256 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5257 { { "g0" }, "r0" }, 5258 { { "g1" }, "r1" }, 5259 { { "g2" }, "r2" }, 5260 { { "g3" }, "r3" }, 5261 { { "g4" }, "r4" }, 5262 { { "g5" }, "r5" }, 5263 { { "g6" }, "r6" }, 5264 { { "g7" }, "r7" }, 5265 { { "o0" }, "r8" }, 5266 { { "o1" }, "r9" }, 5267 { { "o2" }, "r10" }, 5268 { { "o3" }, "r11" }, 5269 { { "o4" }, "r12" }, 5270 { { "o5" }, "r13" }, 5271 { { "o6", "sp" }, "r14" }, 5272 { { "o7" }, "r15" }, 5273 { { "l0" }, "r16" }, 5274 { { "l1" }, "r17" }, 5275 { { "l2" }, "r18" }, 5276 { { "l3" }, "r19" }, 5277 { { "l4" }, "r20" }, 5278 { { "l5" }, "r21" }, 5279 { { "l6" }, "r22" }, 5280 { { "l7" }, "r23" }, 5281 { { "i0" }, "r24" }, 5282 { { "i1" }, "r25" }, 5283 { { "i2" }, "r26" }, 5284 { { "i3" }, "r27" }, 5285 { { "i4" }, "r28" }, 5286 { { "i5" }, "r29" }, 5287 { { "i6", "fp" }, "r30" }, 5288 { { "i7" }, "r31" }, 5289 }; 5290 5291 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5292 unsigned &NumAliases) const { 5293 Aliases = GCCRegAliases; 5294 NumAliases = llvm::array_lengthof(GCCRegAliases); 5295 } 5296 5297 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5298 class SparcV8TargetInfo : public SparcTargetInfo { 5299 public: 5300 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5301 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5302 } 5303 5304 void getTargetDefines(const LangOptions &Opts, 5305 MacroBuilder &Builder) const override { 5306 SparcTargetInfo::getTargetDefines(Opts, Builder); 5307 Builder.defineMacro("__sparcv8"); 5308 } 5309 }; 5310 5311 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5312 class SparcV9TargetInfo : public SparcTargetInfo { 5313 public: 5314 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5315 // FIXME: Support Sparc quad-precision long double? 5316 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5317 // This is an LP64 platform. 5318 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5319 5320 // OpenBSD uses long long for int64_t and intmax_t. 5321 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5322 IntMaxType = SignedLongLong; 5323 else 5324 IntMaxType = SignedLong; 5325 Int64Type = IntMaxType; 5326 5327 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5328 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5329 LongDoubleWidth = 128; 5330 LongDoubleAlign = 128; 5331 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5332 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5333 } 5334 5335 void getTargetDefines(const LangOptions &Opts, 5336 MacroBuilder &Builder) const override { 5337 SparcTargetInfo::getTargetDefines(Opts, Builder); 5338 Builder.defineMacro("__sparcv9"); 5339 Builder.defineMacro("__arch64__"); 5340 // Solaris doesn't need these variants, but the BSDs do. 5341 if (getTriple().getOS() != llvm::Triple::Solaris) { 5342 Builder.defineMacro("__sparc64__"); 5343 Builder.defineMacro("__sparc_v9__"); 5344 Builder.defineMacro("__sparcv9__"); 5345 } 5346 } 5347 5348 bool setCPU(const std::string &Name) override { 5349 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5350 .Case("v9", true) 5351 .Case("ultrasparc", true) 5352 .Case("ultrasparc3", true) 5353 .Case("niagara", true) 5354 .Case("niagara2", true) 5355 .Case("niagara3", true) 5356 .Case("niagara4", true) 5357 .Default(false); 5358 5359 // No need to store the CPU yet. There aren't any CPU-specific 5360 // macros to define. 5361 return CPUKnown; 5362 } 5363 }; 5364 5365 } // end anonymous namespace. 5366 5367 namespace { 5368 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 5369 public: 5370 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 5371 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 5372 SizeType = UnsignedInt; 5373 PtrDiffType = SignedInt; 5374 } 5375 }; 5376 } // end anonymous namespace. 5377 5378 namespace { 5379 class SystemZTargetInfo : public TargetInfo { 5380 static const char *const GCCRegNames[]; 5381 5382 public: 5383 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5384 TLSSupported = true; 5385 IntWidth = IntAlign = 32; 5386 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5387 PointerWidth = PointerAlign = 64; 5388 LongDoubleWidth = 128; 5389 LongDoubleAlign = 64; 5390 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5391 MinGlobalAlign = 16; 5392 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5393 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5394 } 5395 void getTargetDefines(const LangOptions &Opts, 5396 MacroBuilder &Builder) const override { 5397 Builder.defineMacro("__s390__"); 5398 Builder.defineMacro("__s390x__"); 5399 Builder.defineMacro("__zarch__"); 5400 Builder.defineMacro("__LONG_DOUBLE_128__"); 5401 } 5402 void getTargetBuiltins(const Builtin::Info *&Records, 5403 unsigned &NumRecords) const override { 5404 // FIXME: Implement. 5405 Records = nullptr; 5406 NumRecords = 0; 5407 } 5408 5409 void getGCCRegNames(const char *const *&Names, 5410 unsigned &NumNames) const override; 5411 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5412 unsigned &NumAliases) const override { 5413 // No aliases. 5414 Aliases = nullptr; 5415 NumAliases = 0; 5416 } 5417 bool validateAsmConstraint(const char *&Name, 5418 TargetInfo::ConstraintInfo &info) const override; 5419 const char *getClobbers() const override { 5420 // FIXME: Is this really right? 5421 return ""; 5422 } 5423 BuiltinVaListKind getBuiltinVaListKind() const override { 5424 return TargetInfo::SystemZBuiltinVaList; 5425 } 5426 bool setCPU(const std::string &Name) override { 5427 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5428 .Case("z10", true) 5429 .Case("z196", true) 5430 .Case("zEC12", true) 5431 .Default(false); 5432 5433 // No need to store the CPU yet. There aren't any CPU-specific 5434 // macros to define. 5435 return CPUKnown; 5436 } 5437 }; 5438 5439 const char *const SystemZTargetInfo::GCCRegNames[] = { 5440 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5441 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5442 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5443 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5444 }; 5445 5446 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5447 unsigned &NumNames) const { 5448 Names = GCCRegNames; 5449 NumNames = llvm::array_lengthof(GCCRegNames); 5450 } 5451 5452 bool SystemZTargetInfo:: 5453 validateAsmConstraint(const char *&Name, 5454 TargetInfo::ConstraintInfo &Info) const { 5455 switch (*Name) { 5456 default: 5457 return false; 5458 5459 case 'a': // Address register 5460 case 'd': // Data register (equivalent to 'r') 5461 case 'f': // Floating-point register 5462 Info.setAllowsRegister(); 5463 return true; 5464 5465 case 'I': // Unsigned 8-bit constant 5466 case 'J': // Unsigned 12-bit constant 5467 case 'K': // Signed 16-bit constant 5468 case 'L': // Signed 20-bit displacement (on all targets we support) 5469 case 'M': // 0x7fffffff 5470 return true; 5471 5472 case 'Q': // Memory with base and unsigned 12-bit displacement 5473 case 'R': // Likewise, plus an index 5474 case 'S': // Memory with base and signed 20-bit displacement 5475 case 'T': // Likewise, plus an index 5476 Info.setAllowsMemory(); 5477 return true; 5478 } 5479 } 5480 } 5481 5482 namespace { 5483 class MSP430TargetInfo : public TargetInfo { 5484 static const char * const GCCRegNames[]; 5485 public: 5486 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5487 BigEndian = false; 5488 TLSSupported = false; 5489 IntWidth = 16; IntAlign = 16; 5490 LongWidth = 32; LongLongWidth = 64; 5491 LongAlign = LongLongAlign = 16; 5492 PointerWidth = 16; PointerAlign = 16; 5493 SuitableAlign = 16; 5494 SizeType = UnsignedInt; 5495 IntMaxType = SignedLongLong; 5496 IntPtrType = SignedInt; 5497 PtrDiffType = SignedInt; 5498 SigAtomicType = SignedLong; 5499 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 5500 } 5501 void getTargetDefines(const LangOptions &Opts, 5502 MacroBuilder &Builder) const override { 5503 Builder.defineMacro("MSP430"); 5504 Builder.defineMacro("__MSP430__"); 5505 // FIXME: defines for different 'flavours' of MCU 5506 } 5507 void getTargetBuiltins(const Builtin::Info *&Records, 5508 unsigned &NumRecords) const override { 5509 // FIXME: Implement. 5510 Records = nullptr; 5511 NumRecords = 0; 5512 } 5513 bool hasFeature(StringRef Feature) const override { 5514 return Feature == "msp430"; 5515 } 5516 void getGCCRegNames(const char * const *&Names, 5517 unsigned &NumNames) const override; 5518 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5519 unsigned &NumAliases) const override { 5520 // No aliases. 5521 Aliases = nullptr; 5522 NumAliases = 0; 5523 } 5524 bool 5525 validateAsmConstraint(const char *&Name, 5526 TargetInfo::ConstraintInfo &info) const override { 5527 // FIXME: implement 5528 switch (*Name) { 5529 case 'K': // the constant 1 5530 case 'L': // constant -1^20 .. 1^19 5531 case 'M': // constant 1-4: 5532 return true; 5533 } 5534 // No target constraints for now. 5535 return false; 5536 } 5537 const char *getClobbers() const override { 5538 // FIXME: Is this really right? 5539 return ""; 5540 } 5541 BuiltinVaListKind getBuiltinVaListKind() const override { 5542 // FIXME: implement 5543 return TargetInfo::CharPtrBuiltinVaList; 5544 } 5545 }; 5546 5547 const char * const MSP430TargetInfo::GCCRegNames[] = { 5548 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5549 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5550 }; 5551 5552 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5553 unsigned &NumNames) const { 5554 Names = GCCRegNames; 5555 NumNames = llvm::array_lengthof(GCCRegNames); 5556 } 5557 } 5558 5559 namespace { 5560 5561 // LLVM and Clang cannot be used directly to output native binaries for 5562 // target, but is used to compile C code to llvm bitcode with correct 5563 // type and alignment information. 5564 // 5565 // TCE uses the llvm bitcode as input and uses it for generating customized 5566 // target processor and program binary. TCE co-design environment is 5567 // publicly available in http://tce.cs.tut.fi 5568 5569 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5570 3, // opencl_global 5571 4, // opencl_local 5572 5, // opencl_constant 5573 // FIXME: generic has to be added to the target 5574 0, // opencl_generic 5575 0, // cuda_device 5576 0, // cuda_constant 5577 0 // cuda_shared 5578 }; 5579 5580 class TCETargetInfo : public TargetInfo{ 5581 public: 5582 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5583 TLSSupported = false; 5584 IntWidth = 32; 5585 LongWidth = LongLongWidth = 32; 5586 PointerWidth = 32; 5587 IntAlign = 32; 5588 LongAlign = LongLongAlign = 32; 5589 PointerAlign = 32; 5590 SuitableAlign = 32; 5591 SizeType = UnsignedInt; 5592 IntMaxType = SignedLong; 5593 IntPtrType = SignedInt; 5594 PtrDiffType = SignedInt; 5595 FloatWidth = 32; 5596 FloatAlign = 32; 5597 DoubleWidth = 32; 5598 DoubleAlign = 32; 5599 LongDoubleWidth = 32; 5600 LongDoubleAlign = 32; 5601 FloatFormat = &llvm::APFloat::IEEEsingle; 5602 DoubleFormat = &llvm::APFloat::IEEEsingle; 5603 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5604 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5605 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5606 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5607 UseAddrSpaceMapMangling = true; 5608 } 5609 5610 void getTargetDefines(const LangOptions &Opts, 5611 MacroBuilder &Builder) const override { 5612 DefineStd(Builder, "tce", Opts); 5613 Builder.defineMacro("__TCE__"); 5614 Builder.defineMacro("__TCE_V1__"); 5615 } 5616 bool hasFeature(StringRef Feature) const override { 5617 return Feature == "tce"; 5618 } 5619 5620 void getTargetBuiltins(const Builtin::Info *&Records, 5621 unsigned &NumRecords) const override {} 5622 const char *getClobbers() const override { 5623 return ""; 5624 } 5625 BuiltinVaListKind getBuiltinVaListKind() const override { 5626 return TargetInfo::VoidPtrBuiltinVaList; 5627 } 5628 void getGCCRegNames(const char * const *&Names, 5629 unsigned &NumNames) const override {} 5630 bool validateAsmConstraint(const char *&Name, 5631 TargetInfo::ConstraintInfo &info) const override{ 5632 return true; 5633 } 5634 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5635 unsigned &NumAliases) const override {} 5636 }; 5637 } 5638 5639 namespace { 5640 class MipsTargetInfoBase : public TargetInfo { 5641 virtual void setDescriptionString() = 0; 5642 5643 static const Builtin::Info BuiltinInfo[]; 5644 std::string CPU; 5645 bool IsMips16; 5646 bool IsMicromips; 5647 bool IsNan2008; 5648 bool IsSingleFloat; 5649 enum MipsFloatABI { 5650 HardFloat, SoftFloat 5651 } FloatABI; 5652 enum DspRevEnum { 5653 NoDSP, DSP1, DSP2 5654 } DspRev; 5655 bool HasMSA; 5656 5657 protected: 5658 bool HasFP64; 5659 std::string ABI; 5660 5661 public: 5662 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5663 const std::string &CPUStr) 5664 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5665 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5666 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 5667 TheCXXABI.set(TargetCXXABI::GenericMIPS); 5668 } 5669 5670 bool isNaN2008Default() const { 5671 return CPU == "mips32r6" || CPU == "mips64r6"; 5672 } 5673 5674 bool isFP64Default() const { 5675 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 5676 } 5677 5678 StringRef getABI() const override { return ABI; } 5679 bool setCPU(const std::string &Name) override { 5680 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 5681 getTriple().getArch() == llvm::Triple::mipsel; 5682 CPU = Name; 5683 return llvm::StringSwitch<bool>(Name) 5684 .Case("mips1", IsMips32) 5685 .Case("mips2", IsMips32) 5686 .Case("mips3", true) 5687 .Case("mips4", true) 5688 .Case("mips5", true) 5689 .Case("mips32", IsMips32) 5690 .Case("mips32r2", IsMips32) 5691 .Case("mips32r3", IsMips32) 5692 .Case("mips32r5", IsMips32) 5693 .Case("mips32r6", IsMips32) 5694 .Case("mips64", true) 5695 .Case("mips64r2", true) 5696 .Case("mips64r3", true) 5697 .Case("mips64r5", true) 5698 .Case("mips64r6", true) 5699 .Case("octeon", true) 5700 .Default(false); 5701 } 5702 const std::string& getCPU() const { return CPU; } 5703 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5704 if (CPU == "octeon") 5705 Features["mips64r2"] = Features["cnmips"] = true; 5706 else 5707 Features[CPU] = true; 5708 } 5709 5710 void getTargetDefines(const LangOptions &Opts, 5711 MacroBuilder &Builder) const override { 5712 Builder.defineMacro("__mips__"); 5713 Builder.defineMacro("_mips"); 5714 if (Opts.GNUMode) 5715 Builder.defineMacro("mips"); 5716 5717 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5718 5719 switch (FloatABI) { 5720 case HardFloat: 5721 Builder.defineMacro("__mips_hard_float", Twine(1)); 5722 break; 5723 case SoftFloat: 5724 Builder.defineMacro("__mips_soft_float", Twine(1)); 5725 break; 5726 } 5727 5728 if (IsSingleFloat) 5729 Builder.defineMacro("__mips_single_float", Twine(1)); 5730 5731 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5732 Builder.defineMacro("_MIPS_FPSET", 5733 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5734 5735 if (IsMips16) 5736 Builder.defineMacro("__mips16", Twine(1)); 5737 5738 if (IsMicromips) 5739 Builder.defineMacro("__mips_micromips", Twine(1)); 5740 5741 if (IsNan2008) 5742 Builder.defineMacro("__mips_nan2008", Twine(1)); 5743 5744 switch (DspRev) { 5745 default: 5746 break; 5747 case DSP1: 5748 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5749 Builder.defineMacro("__mips_dsp", Twine(1)); 5750 break; 5751 case DSP2: 5752 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5753 Builder.defineMacro("__mips_dspr2", Twine(1)); 5754 Builder.defineMacro("__mips_dsp", Twine(1)); 5755 break; 5756 } 5757 5758 if (HasMSA) 5759 Builder.defineMacro("__mips_msa", Twine(1)); 5760 5761 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5762 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5763 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5764 5765 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5766 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5767 } 5768 5769 void getTargetBuiltins(const Builtin::Info *&Records, 5770 unsigned &NumRecords) const override { 5771 Records = BuiltinInfo; 5772 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5773 } 5774 bool hasFeature(StringRef Feature) const override { 5775 return llvm::StringSwitch<bool>(Feature) 5776 .Case("mips", true) 5777 .Case("fp64", HasFP64) 5778 .Default(false); 5779 } 5780 BuiltinVaListKind getBuiltinVaListKind() const override { 5781 return TargetInfo::VoidPtrBuiltinVaList; 5782 } 5783 void getGCCRegNames(const char * const *&Names, 5784 unsigned &NumNames) const override { 5785 static const char *const GCCRegNames[] = { 5786 // CPU register names 5787 // Must match second column of GCCRegAliases 5788 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5789 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5790 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5791 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5792 // Floating point register names 5793 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5794 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5795 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5796 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5797 // Hi/lo and condition register names 5798 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5799 "$fcc5","$fcc6","$fcc7", 5800 // MSA register names 5801 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5802 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5803 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5804 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5805 // MSA control register names 5806 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5807 "$msarequest", "$msamap", "$msaunmap" 5808 }; 5809 Names = GCCRegNames; 5810 NumNames = llvm::array_lengthof(GCCRegNames); 5811 } 5812 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5813 unsigned &NumAliases) const override = 0; 5814 bool validateAsmConstraint(const char *&Name, 5815 TargetInfo::ConstraintInfo &Info) const override { 5816 switch (*Name) { 5817 default: 5818 return false; 5819 case 'r': // CPU registers. 5820 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5821 case 'y': // Equivalent to "r", backward compatibility only. 5822 case 'f': // floating-point registers. 5823 case 'c': // $25 for indirect jumps 5824 case 'l': // lo register 5825 case 'x': // hilo register pair 5826 Info.setAllowsRegister(); 5827 return true; 5828 case 'I': // Signed 16-bit constant 5829 case 'J': // Integer 0 5830 case 'K': // Unsigned 16-bit constant 5831 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 5832 case 'M': // Constants not loadable via lui, addiu, or ori 5833 case 'N': // Constant -1 to -65535 5834 case 'O': // A signed 15-bit constant 5835 case 'P': // A constant between 1 go 65535 5836 return true; 5837 case 'R': // An address that can be used in a non-macro load or store 5838 Info.setAllowsMemory(); 5839 return true; 5840 } 5841 } 5842 5843 const char *getClobbers() const override { 5844 // In GCC, $1 is not widely used in generated code (it's used only in a few 5845 // specific situations), so there is no real need for users to add it to 5846 // the clobbers list if they want to use it in their inline assembly code. 5847 // 5848 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 5849 // code generation, so using it in inline assembly without adding it to the 5850 // clobbers list can cause conflicts between the inline assembly code and 5851 // the surrounding generated code. 5852 // 5853 // Another problem is that LLVM is allowed to choose $1 for inline assembly 5854 // operands, which will conflict with the ".set at" assembler option (which 5855 // we use only for inline assembly, in order to maintain compatibility with 5856 // GCC) and will also conflict with the user's usage of $1. 5857 // 5858 // The easiest way to avoid these conflicts and keep $1 as an allocatable 5859 // register for generated code is to automatically clobber $1 for all inline 5860 // assembly code. 5861 // 5862 // FIXME: We should automatically clobber $1 only for inline assembly code 5863 // which actually uses it. This would allow LLVM to use $1 for inline 5864 // assembly operands if the user's assembly code doesn't use it. 5865 return "~{$1}"; 5866 } 5867 5868 bool handleTargetFeatures(std::vector<std::string> &Features, 5869 DiagnosticsEngine &Diags) override { 5870 IsMips16 = false; 5871 IsMicromips = false; 5872 IsNan2008 = isNaN2008Default(); 5873 IsSingleFloat = false; 5874 FloatABI = HardFloat; 5875 DspRev = NoDSP; 5876 HasFP64 = isFP64Default(); 5877 5878 for (std::vector<std::string>::iterator it = Features.begin(), 5879 ie = Features.end(); it != ie; ++it) { 5880 if (*it == "+single-float") 5881 IsSingleFloat = true; 5882 else if (*it == "+soft-float") 5883 FloatABI = SoftFloat; 5884 else if (*it == "+mips16") 5885 IsMips16 = true; 5886 else if (*it == "+micromips") 5887 IsMicromips = true; 5888 else if (*it == "+dsp") 5889 DspRev = std::max(DspRev, DSP1); 5890 else if (*it == "+dspr2") 5891 DspRev = std::max(DspRev, DSP2); 5892 else if (*it == "+msa") 5893 HasMSA = true; 5894 else if (*it == "+fp64") 5895 HasFP64 = true; 5896 else if (*it == "-fp64") 5897 HasFP64 = false; 5898 else if (*it == "+nan2008") 5899 IsNan2008 = true; 5900 else if (*it == "-nan2008") 5901 IsNan2008 = false; 5902 } 5903 5904 // Remove front-end specific options. 5905 std::vector<std::string>::iterator it = 5906 std::find(Features.begin(), Features.end(), "+soft-float"); 5907 if (it != Features.end()) 5908 Features.erase(it); 5909 5910 setDescriptionString(); 5911 5912 return true; 5913 } 5914 5915 int getEHDataRegisterNumber(unsigned RegNo) const override { 5916 if (RegNo == 0) return 4; 5917 if (RegNo == 1) return 5; 5918 return -1; 5919 } 5920 5921 bool isCLZForZeroUndef() const override { return false; } 5922 }; 5923 5924 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5925 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5926 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5927 ALL_LANGUAGES }, 5928 #include "clang/Basic/BuiltinsMips.def" 5929 }; 5930 5931 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5932 public: 5933 Mips32TargetInfoBase(const llvm::Triple &Triple) 5934 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 5935 SizeType = UnsignedInt; 5936 PtrDiffType = SignedInt; 5937 Int64Type = SignedLongLong; 5938 IntMaxType = Int64Type; 5939 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5940 } 5941 bool setABI(const std::string &Name) override { 5942 if (Name == "o32" || Name == "eabi") { 5943 ABI = Name; 5944 return true; 5945 } 5946 return false; 5947 } 5948 void getTargetDefines(const LangOptions &Opts, 5949 MacroBuilder &Builder) const override { 5950 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5951 5952 Builder.defineMacro("__mips", "32"); 5953 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 5954 5955 const std::string& CPUStr = getCPU(); 5956 if (CPUStr == "mips32") 5957 Builder.defineMacro("__mips_isa_rev", "1"); 5958 else if (CPUStr == "mips32r2") 5959 Builder.defineMacro("__mips_isa_rev", "2"); 5960 else if (CPUStr == "mips32r3") 5961 Builder.defineMacro("__mips_isa_rev", "3"); 5962 else if (CPUStr == "mips32r5") 5963 Builder.defineMacro("__mips_isa_rev", "5"); 5964 else if (CPUStr == "mips32r6") 5965 Builder.defineMacro("__mips_isa_rev", "6"); 5966 5967 if (ABI == "o32") { 5968 Builder.defineMacro("__mips_o32"); 5969 Builder.defineMacro("_ABIO32", "1"); 5970 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5971 } 5972 else if (ABI == "eabi") 5973 Builder.defineMacro("__mips_eabi"); 5974 else 5975 llvm_unreachable("Invalid ABI for Mips32."); 5976 } 5977 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5978 unsigned &NumAliases) const override { 5979 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5980 { { "at" }, "$1" }, 5981 { { "v0" }, "$2" }, 5982 { { "v1" }, "$3" }, 5983 { { "a0" }, "$4" }, 5984 { { "a1" }, "$5" }, 5985 { { "a2" }, "$6" }, 5986 { { "a3" }, "$7" }, 5987 { { "t0" }, "$8" }, 5988 { { "t1" }, "$9" }, 5989 { { "t2" }, "$10" }, 5990 { { "t3" }, "$11" }, 5991 { { "t4" }, "$12" }, 5992 { { "t5" }, "$13" }, 5993 { { "t6" }, "$14" }, 5994 { { "t7" }, "$15" }, 5995 { { "s0" }, "$16" }, 5996 { { "s1" }, "$17" }, 5997 { { "s2" }, "$18" }, 5998 { { "s3" }, "$19" }, 5999 { { "s4" }, "$20" }, 6000 { { "s5" }, "$21" }, 6001 { { "s6" }, "$22" }, 6002 { { "s7" }, "$23" }, 6003 { { "t8" }, "$24" }, 6004 { { "t9" }, "$25" }, 6005 { { "k0" }, "$26" }, 6006 { { "k1" }, "$27" }, 6007 { { "gp" }, "$28" }, 6008 { { "sp","$sp" }, "$29" }, 6009 { { "fp","$fp" }, "$30" }, 6010 { { "ra" }, "$31" } 6011 }; 6012 Aliases = GCCRegAliases; 6013 NumAliases = llvm::array_lengthof(GCCRegAliases); 6014 } 6015 }; 6016 6017 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6018 void setDescriptionString() override { 6019 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6020 } 6021 6022 public: 6023 Mips32EBTargetInfo(const llvm::Triple &Triple) 6024 : Mips32TargetInfoBase(Triple) { 6025 } 6026 void getTargetDefines(const LangOptions &Opts, 6027 MacroBuilder &Builder) const override { 6028 DefineStd(Builder, "MIPSEB", Opts); 6029 Builder.defineMacro("_MIPSEB"); 6030 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6031 } 6032 }; 6033 6034 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6035 void setDescriptionString() override { 6036 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6037 } 6038 6039 public: 6040 Mips32ELTargetInfo(const llvm::Triple &Triple) 6041 : Mips32TargetInfoBase(Triple) { 6042 BigEndian = false; 6043 } 6044 void getTargetDefines(const LangOptions &Opts, 6045 MacroBuilder &Builder) const override { 6046 DefineStd(Builder, "MIPSEL", Opts); 6047 Builder.defineMacro("_MIPSEL"); 6048 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6049 } 6050 }; 6051 6052 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6053 public: 6054 Mips64TargetInfoBase(const llvm::Triple &Triple) 6055 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6056 LongDoubleWidth = LongDoubleAlign = 128; 6057 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6058 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6059 LongDoubleWidth = LongDoubleAlign = 64; 6060 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6061 } 6062 setN64ABITypes(); 6063 SuitableAlign = 128; 6064 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6065 } 6066 6067 void setN64ABITypes() { 6068 LongWidth = LongAlign = 64; 6069 PointerWidth = PointerAlign = 64; 6070 SizeType = UnsignedLong; 6071 PtrDiffType = SignedLong; 6072 Int64Type = SignedLong; 6073 IntMaxType = Int64Type; 6074 } 6075 6076 void setN32ABITypes() { 6077 LongWidth = LongAlign = 32; 6078 PointerWidth = PointerAlign = 32; 6079 SizeType = UnsignedInt; 6080 PtrDiffType = SignedInt; 6081 Int64Type = SignedLongLong; 6082 IntMaxType = Int64Type; 6083 } 6084 6085 bool setABI(const std::string &Name) override { 6086 if (Name == "n32") { 6087 setN32ABITypes(); 6088 ABI = Name; 6089 return true; 6090 } 6091 if (Name == "n64") { 6092 setN64ABITypes(); 6093 ABI = Name; 6094 return true; 6095 } 6096 return false; 6097 } 6098 6099 void getTargetDefines(const LangOptions &Opts, 6100 MacroBuilder &Builder) const override { 6101 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6102 6103 Builder.defineMacro("__mips", "64"); 6104 Builder.defineMacro("__mips64"); 6105 Builder.defineMacro("__mips64__"); 6106 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6107 6108 const std::string& CPUStr = getCPU(); 6109 if (CPUStr == "mips64") 6110 Builder.defineMacro("__mips_isa_rev", "1"); 6111 else if (CPUStr == "mips64r2") 6112 Builder.defineMacro("__mips_isa_rev", "2"); 6113 else if (CPUStr == "mips64r3") 6114 Builder.defineMacro("__mips_isa_rev", "3"); 6115 else if (CPUStr == "mips64r5") 6116 Builder.defineMacro("__mips_isa_rev", "5"); 6117 else if (CPUStr == "mips64r6") 6118 Builder.defineMacro("__mips_isa_rev", "6"); 6119 6120 if (ABI == "n32") { 6121 Builder.defineMacro("__mips_n32"); 6122 Builder.defineMacro("_ABIN32", "2"); 6123 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6124 } 6125 else if (ABI == "n64") { 6126 Builder.defineMacro("__mips_n64"); 6127 Builder.defineMacro("_ABI64", "3"); 6128 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6129 } 6130 else 6131 llvm_unreachable("Invalid ABI for Mips64."); 6132 } 6133 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6134 unsigned &NumAliases) const override { 6135 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6136 { { "at" }, "$1" }, 6137 { { "v0" }, "$2" }, 6138 { { "v1" }, "$3" }, 6139 { { "a0" }, "$4" }, 6140 { { "a1" }, "$5" }, 6141 { { "a2" }, "$6" }, 6142 { { "a3" }, "$7" }, 6143 { { "a4" }, "$8" }, 6144 { { "a5" }, "$9" }, 6145 { { "a6" }, "$10" }, 6146 { { "a7" }, "$11" }, 6147 { { "t0" }, "$12" }, 6148 { { "t1" }, "$13" }, 6149 { { "t2" }, "$14" }, 6150 { { "t3" }, "$15" }, 6151 { { "s0" }, "$16" }, 6152 { { "s1" }, "$17" }, 6153 { { "s2" }, "$18" }, 6154 { { "s3" }, "$19" }, 6155 { { "s4" }, "$20" }, 6156 { { "s5" }, "$21" }, 6157 { { "s6" }, "$22" }, 6158 { { "s7" }, "$23" }, 6159 { { "t8" }, "$24" }, 6160 { { "t9" }, "$25" }, 6161 { { "k0" }, "$26" }, 6162 { { "k1" }, "$27" }, 6163 { { "gp" }, "$28" }, 6164 { { "sp","$sp" }, "$29" }, 6165 { { "fp","$fp" }, "$30" }, 6166 { { "ra" }, "$31" } 6167 }; 6168 Aliases = GCCRegAliases; 6169 NumAliases = llvm::array_lengthof(GCCRegAliases); 6170 } 6171 6172 bool hasInt128Type() const override { return true; } 6173 }; 6174 6175 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6176 void setDescriptionString() override { 6177 if (ABI == "n32") 6178 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6179 else 6180 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6181 6182 } 6183 6184 public: 6185 Mips64EBTargetInfo(const llvm::Triple &Triple) 6186 : Mips64TargetInfoBase(Triple) {} 6187 void getTargetDefines(const LangOptions &Opts, 6188 MacroBuilder &Builder) const override { 6189 DefineStd(Builder, "MIPSEB", Opts); 6190 Builder.defineMacro("_MIPSEB"); 6191 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6192 } 6193 }; 6194 6195 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6196 void setDescriptionString() override { 6197 if (ABI == "n32") 6198 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6199 else 6200 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6201 } 6202 public: 6203 Mips64ELTargetInfo(const llvm::Triple &Triple) 6204 : Mips64TargetInfoBase(Triple) { 6205 // Default ABI is n64. 6206 BigEndian = false; 6207 } 6208 void getTargetDefines(const LangOptions &Opts, 6209 MacroBuilder &Builder) const override { 6210 DefineStd(Builder, "MIPSEL", Opts); 6211 Builder.defineMacro("_MIPSEL"); 6212 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6213 } 6214 }; 6215 } // end anonymous namespace. 6216 6217 namespace { 6218 class PNaClTargetInfo : public TargetInfo { 6219 public: 6220 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6221 BigEndian = false; 6222 this->UserLabelPrefix = ""; 6223 this->LongAlign = 32; 6224 this->LongWidth = 32; 6225 this->PointerAlign = 32; 6226 this->PointerWidth = 32; 6227 this->IntMaxType = TargetInfo::SignedLongLong; 6228 this->Int64Type = TargetInfo::SignedLongLong; 6229 this->DoubleAlign = 64; 6230 this->LongDoubleWidth = 64; 6231 this->LongDoubleAlign = 64; 6232 this->SizeType = TargetInfo::UnsignedInt; 6233 this->PtrDiffType = TargetInfo::SignedInt; 6234 this->IntPtrType = TargetInfo::SignedInt; 6235 this->RegParmMax = 0; // Disallow regparm 6236 } 6237 6238 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6239 } 6240 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6241 Builder.defineMacro("__le32__"); 6242 Builder.defineMacro("__pnacl__"); 6243 } 6244 void getTargetDefines(const LangOptions &Opts, 6245 MacroBuilder &Builder) const override { 6246 getArchDefines(Opts, Builder); 6247 } 6248 bool hasFeature(StringRef Feature) const override { 6249 return Feature == "pnacl"; 6250 } 6251 void getTargetBuiltins(const Builtin::Info *&Records, 6252 unsigned &NumRecords) const override { 6253 } 6254 BuiltinVaListKind getBuiltinVaListKind() const override { 6255 return TargetInfo::PNaClABIBuiltinVaList; 6256 } 6257 void getGCCRegNames(const char * const *&Names, 6258 unsigned &NumNames) const override; 6259 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6260 unsigned &NumAliases) const override; 6261 bool validateAsmConstraint(const char *&Name, 6262 TargetInfo::ConstraintInfo &Info) const override { 6263 return false; 6264 } 6265 6266 const char *getClobbers() const override { 6267 return ""; 6268 } 6269 }; 6270 6271 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6272 unsigned &NumNames) const { 6273 Names = nullptr; 6274 NumNames = 0; 6275 } 6276 6277 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6278 unsigned &NumAliases) const { 6279 Aliases = nullptr; 6280 NumAliases = 0; 6281 } 6282 } // end anonymous namespace. 6283 6284 namespace { 6285 class Le64TargetInfo : public TargetInfo { 6286 static const Builtin::Info BuiltinInfo[]; 6287 6288 public: 6289 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6290 BigEndian = false; 6291 NoAsmVariants = true; 6292 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6293 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6294 DescriptionString = 6295 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6296 } 6297 6298 void getTargetDefines(const LangOptions &Opts, 6299 MacroBuilder &Builder) const override { 6300 DefineStd(Builder, "unix", Opts); 6301 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6302 Builder.defineMacro("__ELF__"); 6303 } 6304 void getTargetBuiltins(const Builtin::Info *&Records, 6305 unsigned &NumRecords) const override { 6306 Records = BuiltinInfo; 6307 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6308 } 6309 BuiltinVaListKind getBuiltinVaListKind() const override { 6310 return TargetInfo::PNaClABIBuiltinVaList; 6311 } 6312 const char *getClobbers() const override { return ""; } 6313 void getGCCRegNames(const char *const *&Names, 6314 unsigned &NumNames) const override { 6315 Names = nullptr; 6316 NumNames = 0; 6317 } 6318 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6319 unsigned &NumAliases) const override { 6320 Aliases = nullptr; 6321 NumAliases = 0; 6322 } 6323 bool validateAsmConstraint(const char *&Name, 6324 TargetInfo::ConstraintInfo &Info) const override { 6325 return false; 6326 } 6327 6328 bool hasProtectedVisibility() const override { return false; } 6329 }; 6330 } // end anonymous namespace. 6331 6332 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 6333 #define BUILTIN(ID, TYPE, ATTRS) \ 6334 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6335 #include "clang/Basic/BuiltinsLe64.def" 6336 }; 6337 6338 namespace { 6339 static const unsigned SPIRAddrSpaceMap[] = { 6340 1, // opencl_global 6341 3, // opencl_local 6342 2, // opencl_constant 6343 4, // opencl_generic 6344 0, // cuda_device 6345 0, // cuda_constant 6346 0 // cuda_shared 6347 }; 6348 class SPIRTargetInfo : public TargetInfo { 6349 public: 6350 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6351 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 6352 "SPIR target must use unknown OS"); 6353 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 6354 "SPIR target must use unknown environment type"); 6355 BigEndian = false; 6356 TLSSupported = false; 6357 LongWidth = LongAlign = 64; 6358 AddrSpaceMap = &SPIRAddrSpaceMap; 6359 UseAddrSpaceMapMangling = true; 6360 // Define available target features 6361 // These must be defined in sorted order! 6362 NoAsmVariants = true; 6363 } 6364 void getTargetDefines(const LangOptions &Opts, 6365 MacroBuilder &Builder) const override { 6366 DefineStd(Builder, "SPIR", Opts); 6367 } 6368 bool hasFeature(StringRef Feature) const override { 6369 return Feature == "spir"; 6370 } 6371 6372 void getTargetBuiltins(const Builtin::Info *&Records, 6373 unsigned &NumRecords) const override {} 6374 const char *getClobbers() const override { 6375 return ""; 6376 } 6377 void getGCCRegNames(const char * const *&Names, 6378 unsigned &NumNames) const override {} 6379 bool 6380 validateAsmConstraint(const char *&Name, 6381 TargetInfo::ConstraintInfo &info) const override { 6382 return true; 6383 } 6384 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6385 unsigned &NumAliases) const override {} 6386 BuiltinVaListKind getBuiltinVaListKind() const override { 6387 return TargetInfo::VoidPtrBuiltinVaList; 6388 } 6389 6390 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6391 return (CC == CC_SpirFunction || 6392 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning; 6393 } 6394 6395 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 6396 return CC_SpirFunction; 6397 } 6398 }; 6399 6400 6401 class SPIR32TargetInfo : public SPIRTargetInfo { 6402 public: 6403 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6404 PointerWidth = PointerAlign = 32; 6405 SizeType = TargetInfo::UnsignedInt; 6406 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6407 DescriptionString 6408 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6409 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6410 } 6411 void getTargetDefines(const LangOptions &Opts, 6412 MacroBuilder &Builder) const override { 6413 DefineStd(Builder, "SPIR32", Opts); 6414 } 6415 }; 6416 6417 class SPIR64TargetInfo : public SPIRTargetInfo { 6418 public: 6419 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6420 PointerWidth = PointerAlign = 64; 6421 SizeType = TargetInfo::UnsignedLong; 6422 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6423 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6424 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6425 } 6426 void getTargetDefines(const LangOptions &Opts, 6427 MacroBuilder &Builder) const override { 6428 DefineStd(Builder, "SPIR64", Opts); 6429 } 6430 }; 6431 } 6432 6433 namespace { 6434 class XCoreTargetInfo : public TargetInfo { 6435 static const Builtin::Info BuiltinInfo[]; 6436 public: 6437 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6438 BigEndian = false; 6439 NoAsmVariants = true; 6440 LongLongAlign = 32; 6441 SuitableAlign = 32; 6442 DoubleAlign = LongDoubleAlign = 32; 6443 SizeType = UnsignedInt; 6444 PtrDiffType = SignedInt; 6445 IntPtrType = SignedInt; 6446 WCharType = UnsignedChar; 6447 WIntType = UnsignedInt; 6448 UseZeroLengthBitfieldAlignment = true; 6449 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6450 "-f64:32-a:0:32-n32"; 6451 } 6452 void getTargetDefines(const LangOptions &Opts, 6453 MacroBuilder &Builder) const override { 6454 Builder.defineMacro("__XS1B__"); 6455 } 6456 void getTargetBuiltins(const Builtin::Info *&Records, 6457 unsigned &NumRecords) const override { 6458 Records = BuiltinInfo; 6459 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6460 } 6461 BuiltinVaListKind getBuiltinVaListKind() const override { 6462 return TargetInfo::VoidPtrBuiltinVaList; 6463 } 6464 const char *getClobbers() const override { 6465 return ""; 6466 } 6467 void getGCCRegNames(const char * const *&Names, 6468 unsigned &NumNames) const override { 6469 static const char * const GCCRegNames[] = { 6470 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6471 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6472 }; 6473 Names = GCCRegNames; 6474 NumNames = llvm::array_lengthof(GCCRegNames); 6475 } 6476 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6477 unsigned &NumAliases) const override { 6478 Aliases = nullptr; 6479 NumAliases = 0; 6480 } 6481 bool validateAsmConstraint(const char *&Name, 6482 TargetInfo::ConstraintInfo &Info) const override { 6483 return false; 6484 } 6485 int getEHDataRegisterNumber(unsigned RegNo) const override { 6486 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6487 return (RegNo < 2)? RegNo : -1; 6488 } 6489 }; 6490 6491 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6492 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6493 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6494 ALL_LANGUAGES }, 6495 #include "clang/Basic/BuiltinsXCore.def" 6496 }; 6497 } // end anonymous namespace. 6498 6499 6500 //===----------------------------------------------------------------------===// 6501 // Driver code 6502 //===----------------------------------------------------------------------===// 6503 6504 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 6505 llvm::Triple::OSType os = Triple.getOS(); 6506 6507 switch (Triple.getArch()) { 6508 default: 6509 return nullptr; 6510 6511 case llvm::Triple::xcore: 6512 return new XCoreTargetInfo(Triple); 6513 6514 case llvm::Triple::hexagon: 6515 return new HexagonTargetInfo(Triple); 6516 6517 case llvm::Triple::aarch64: 6518 if (Triple.isOSDarwin()) 6519 return new DarwinAArch64TargetInfo(Triple); 6520 6521 switch (os) { 6522 case llvm::Triple::FreeBSD: 6523 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 6524 case llvm::Triple::Linux: 6525 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6526 case llvm::Triple::NetBSD: 6527 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6528 default: 6529 return new AArch64leTargetInfo(Triple); 6530 } 6531 6532 case llvm::Triple::aarch64_be: 6533 switch (os) { 6534 case llvm::Triple::FreeBSD: 6535 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 6536 case llvm::Triple::Linux: 6537 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6538 case llvm::Triple::NetBSD: 6539 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6540 default: 6541 return new AArch64beTargetInfo(Triple); 6542 } 6543 6544 case llvm::Triple::arm: 6545 case llvm::Triple::thumb: 6546 if (Triple.isOSBinFormatMachO()) 6547 return new DarwinARMTargetInfo(Triple); 6548 6549 switch (os) { 6550 case llvm::Triple::Linux: 6551 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6552 case llvm::Triple::FreeBSD: 6553 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6554 case llvm::Triple::NetBSD: 6555 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6556 case llvm::Triple::OpenBSD: 6557 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6558 case llvm::Triple::Bitrig: 6559 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6560 case llvm::Triple::RTEMS: 6561 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6562 case llvm::Triple::NaCl: 6563 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6564 case llvm::Triple::Win32: 6565 switch (Triple.getEnvironment()) { 6566 default: 6567 return new ARMleTargetInfo(Triple); 6568 case llvm::Triple::Itanium: 6569 return new ItaniumWindowsARMleTargetInfo(Triple); 6570 case llvm::Triple::MSVC: 6571 return new MicrosoftARMleTargetInfo(Triple); 6572 } 6573 default: 6574 return new ARMleTargetInfo(Triple); 6575 } 6576 6577 case llvm::Triple::armeb: 6578 case llvm::Triple::thumbeb: 6579 if (Triple.isOSDarwin()) 6580 return new DarwinARMTargetInfo(Triple); 6581 6582 switch (os) { 6583 case llvm::Triple::Linux: 6584 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 6585 case llvm::Triple::FreeBSD: 6586 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 6587 case llvm::Triple::NetBSD: 6588 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 6589 case llvm::Triple::OpenBSD: 6590 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 6591 case llvm::Triple::Bitrig: 6592 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 6593 case llvm::Triple::RTEMS: 6594 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 6595 case llvm::Triple::NaCl: 6596 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 6597 default: 6598 return new ARMbeTargetInfo(Triple); 6599 } 6600 6601 case llvm::Triple::msp430: 6602 return new MSP430TargetInfo(Triple); 6603 6604 case llvm::Triple::mips: 6605 switch (os) { 6606 case llvm::Triple::Linux: 6607 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 6608 case llvm::Triple::RTEMS: 6609 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 6610 case llvm::Triple::FreeBSD: 6611 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6612 case llvm::Triple::NetBSD: 6613 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6614 default: 6615 return new Mips32EBTargetInfo(Triple); 6616 } 6617 6618 case llvm::Triple::mipsel: 6619 switch (os) { 6620 case llvm::Triple::Linux: 6621 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 6622 case llvm::Triple::RTEMS: 6623 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 6624 case llvm::Triple::FreeBSD: 6625 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6626 case llvm::Triple::NetBSD: 6627 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6628 case llvm::Triple::NaCl: 6629 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 6630 default: 6631 return new Mips32ELTargetInfo(Triple); 6632 } 6633 6634 case llvm::Triple::mips64: 6635 switch (os) { 6636 case llvm::Triple::Linux: 6637 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 6638 case llvm::Triple::RTEMS: 6639 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 6640 case llvm::Triple::FreeBSD: 6641 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6642 case llvm::Triple::NetBSD: 6643 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6644 case llvm::Triple::OpenBSD: 6645 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6646 default: 6647 return new Mips64EBTargetInfo(Triple); 6648 } 6649 6650 case llvm::Triple::mips64el: 6651 switch (os) { 6652 case llvm::Triple::Linux: 6653 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 6654 case llvm::Triple::RTEMS: 6655 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 6656 case llvm::Triple::FreeBSD: 6657 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6658 case llvm::Triple::NetBSD: 6659 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6660 case llvm::Triple::OpenBSD: 6661 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6662 default: 6663 return new Mips64ELTargetInfo(Triple); 6664 } 6665 6666 case llvm::Triple::le32: 6667 switch (os) { 6668 case llvm::Triple::NaCl: 6669 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 6670 default: 6671 return nullptr; 6672 } 6673 6674 case llvm::Triple::le64: 6675 return new Le64TargetInfo(Triple); 6676 6677 case llvm::Triple::ppc: 6678 if (Triple.isOSDarwin()) 6679 return new DarwinPPC32TargetInfo(Triple); 6680 switch (os) { 6681 case llvm::Triple::Linux: 6682 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 6683 case llvm::Triple::FreeBSD: 6684 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 6685 case llvm::Triple::NetBSD: 6686 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 6687 case llvm::Triple::OpenBSD: 6688 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 6689 case llvm::Triple::RTEMS: 6690 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 6691 default: 6692 return new PPC32TargetInfo(Triple); 6693 } 6694 6695 case llvm::Triple::ppc64: 6696 if (Triple.isOSDarwin()) 6697 return new DarwinPPC64TargetInfo(Triple); 6698 switch (os) { 6699 case llvm::Triple::Linux: 6700 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6701 case llvm::Triple::Lv2: 6702 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 6703 case llvm::Triple::FreeBSD: 6704 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 6705 case llvm::Triple::NetBSD: 6706 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6707 default: 6708 return new PPC64TargetInfo(Triple); 6709 } 6710 6711 case llvm::Triple::ppc64le: 6712 switch (os) { 6713 case llvm::Triple::Linux: 6714 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6715 default: 6716 return new PPC64TargetInfo(Triple); 6717 } 6718 6719 case llvm::Triple::nvptx: 6720 return new NVPTX32TargetInfo(Triple); 6721 case llvm::Triple::nvptx64: 6722 return new NVPTX64TargetInfo(Triple); 6723 6724 case llvm::Triple::amdgcn: 6725 case llvm::Triple::r600: 6726 return new R600TargetInfo(Triple); 6727 6728 case llvm::Triple::sparc: 6729 switch (os) { 6730 case llvm::Triple::Linux: 6731 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 6732 case llvm::Triple::Solaris: 6733 return new SolarisSparcV8TargetInfo(Triple); 6734 case llvm::Triple::NetBSD: 6735 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 6736 case llvm::Triple::OpenBSD: 6737 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 6738 case llvm::Triple::RTEMS: 6739 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 6740 default: 6741 return new SparcV8TargetInfo(Triple); 6742 } 6743 6744 case llvm::Triple::sparcv9: 6745 switch (os) { 6746 case llvm::Triple::Linux: 6747 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 6748 case llvm::Triple::Solaris: 6749 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 6750 case llvm::Triple::NetBSD: 6751 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 6752 case llvm::Triple::OpenBSD: 6753 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 6754 case llvm::Triple::FreeBSD: 6755 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 6756 default: 6757 return new SparcV9TargetInfo(Triple); 6758 } 6759 6760 case llvm::Triple::systemz: 6761 switch (os) { 6762 case llvm::Triple::Linux: 6763 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 6764 default: 6765 return new SystemZTargetInfo(Triple); 6766 } 6767 6768 case llvm::Triple::tce: 6769 return new TCETargetInfo(Triple); 6770 6771 case llvm::Triple::x86: 6772 if (Triple.isOSDarwin()) 6773 return new DarwinI386TargetInfo(Triple); 6774 6775 switch (os) { 6776 case llvm::Triple::Linux: 6777 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 6778 case llvm::Triple::DragonFly: 6779 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 6780 case llvm::Triple::NetBSD: 6781 return new NetBSDI386TargetInfo(Triple); 6782 case llvm::Triple::OpenBSD: 6783 return new OpenBSDI386TargetInfo(Triple); 6784 case llvm::Triple::Bitrig: 6785 return new BitrigI386TargetInfo(Triple); 6786 case llvm::Triple::FreeBSD: 6787 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6788 case llvm::Triple::KFreeBSD: 6789 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6790 case llvm::Triple::Minix: 6791 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 6792 case llvm::Triple::Solaris: 6793 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 6794 case llvm::Triple::Win32: { 6795 switch (Triple.getEnvironment()) { 6796 default: 6797 return new X86_32TargetInfo(Triple); 6798 case llvm::Triple::Cygnus: 6799 return new CygwinX86_32TargetInfo(Triple); 6800 case llvm::Triple::GNU: 6801 return new MinGWX86_32TargetInfo(Triple); 6802 case llvm::Triple::Itanium: 6803 case llvm::Triple::MSVC: 6804 return new MicrosoftX86_32TargetInfo(Triple); 6805 } 6806 } 6807 case llvm::Triple::Haiku: 6808 return new HaikuX86_32TargetInfo(Triple); 6809 case llvm::Triple::RTEMS: 6810 return new RTEMSX86_32TargetInfo(Triple); 6811 case llvm::Triple::NaCl: 6812 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 6813 default: 6814 return new X86_32TargetInfo(Triple); 6815 } 6816 6817 case llvm::Triple::x86_64: 6818 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 6819 return new DarwinX86_64TargetInfo(Triple); 6820 6821 switch (os) { 6822 case llvm::Triple::Linux: 6823 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 6824 case llvm::Triple::DragonFly: 6825 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 6826 case llvm::Triple::NetBSD: 6827 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 6828 case llvm::Triple::OpenBSD: 6829 return new OpenBSDX86_64TargetInfo(Triple); 6830 case llvm::Triple::Bitrig: 6831 return new BitrigX86_64TargetInfo(Triple); 6832 case llvm::Triple::FreeBSD: 6833 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6834 case llvm::Triple::KFreeBSD: 6835 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6836 case llvm::Triple::Solaris: 6837 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 6838 case llvm::Triple::Win32: { 6839 switch (Triple.getEnvironment()) { 6840 default: 6841 return new X86_64TargetInfo(Triple); 6842 case llvm::Triple::GNU: 6843 return new MinGWX86_64TargetInfo(Triple); 6844 case llvm::Triple::MSVC: 6845 return new MicrosoftX86_64TargetInfo(Triple); 6846 } 6847 } 6848 case llvm::Triple::NaCl: 6849 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 6850 case llvm::Triple::PS4: 6851 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 6852 default: 6853 return new X86_64TargetInfo(Triple); 6854 } 6855 6856 case llvm::Triple::spir: { 6857 if (Triple.getOS() != llvm::Triple::UnknownOS || 6858 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6859 return nullptr; 6860 return new SPIR32TargetInfo(Triple); 6861 } 6862 case llvm::Triple::spir64: { 6863 if (Triple.getOS() != llvm::Triple::UnknownOS || 6864 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6865 return nullptr; 6866 return new SPIR64TargetInfo(Triple); 6867 } 6868 } 6869 } 6870 6871 /// CreateTargetInfo - Return the target info object for the specified target 6872 /// triple. 6873 TargetInfo * 6874 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 6875 const std::shared_ptr<TargetOptions> &Opts) { 6876 llvm::Triple Triple(Opts->Triple); 6877 6878 // Construct the target 6879 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 6880 if (!Target) { 6881 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 6882 return nullptr; 6883 } 6884 Target->TargetOpts = Opts; 6885 6886 // Set the target CPU if specified. 6887 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 6888 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 6889 return nullptr; 6890 } 6891 6892 // Set the target ABI if specified. 6893 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 6894 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 6895 return nullptr; 6896 } 6897 6898 // Set the fp math unit. 6899 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 6900 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 6901 return nullptr; 6902 } 6903 6904 // Compute the default target features, we need the target to handle this 6905 // because features may have dependencies on one another. 6906 llvm::StringMap<bool> Features; 6907 Target->getDefaultFeatures(Features); 6908 6909 // Apply the user specified deltas. 6910 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 6911 I < N; ++I) { 6912 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 6913 // Apply the feature via the target. 6914 bool Enabled = Name[0] == '+'; 6915 Target->setFeatureEnabled(Features, Name + 1, Enabled); 6916 } 6917 6918 // Add the features to the compile options. 6919 // 6920 // FIXME: If we are completely confident that we have the right set, we only 6921 // need to pass the minuses. 6922 Opts->Features.clear(); 6923 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 6924 ie = Features.end(); it != ie; ++it) 6925 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 6926 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 6927 return nullptr; 6928 6929 return Target.release(); 6930 } 6931