1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/OwningPtr.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/IR/Type.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include <algorithm> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 virtual void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("__MACH__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 98 99 if (!Opts.ObjCAutoRefCount) { 100 // __weak is always defined, for use in blocks and with objc pointers. 101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 102 103 // Darwin defines __strong even in C mode (just to nothing). 104 if (Opts.getGC() != LangOptions::NonGC) 105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 106 else 107 Builder.defineMacro("__strong", ""); 108 109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 110 // allow this in C, since one might have block pointers in structs that 111 // are used in pure C code and in Objective-C ARC. 112 Builder.defineMacro("__unsafe_unretained", ""); 113 } 114 115 if (Opts.Static) 116 Builder.defineMacro("__STATIC__"); 117 else 118 Builder.defineMacro("__DYNAMIC__"); 119 120 if (Opts.POSIXThreads) 121 Builder.defineMacro("_REENTRANT"); 122 123 // Get the platform type and version number from the triple. 124 unsigned Maj, Min, Rev; 125 if (Triple.isMacOSX()) { 126 Triple.getMacOSXVersion(Maj, Min, Rev); 127 PlatformName = "macosx"; 128 } else { 129 Triple.getOSVersion(Maj, Min, Rev); 130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 131 } 132 133 // If -target arch-pc-win32-macho option specified, we're 134 // generating code for Win32 ABI. No need to emit 135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 136 if (PlatformName == "win32") { 137 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 138 return; 139 } 140 141 // If there's an environment specified in the triple, that means we're dealing 142 // with an embedded variant of some sort and don't want the platform 143 // version-min defines, so only add them if there's not one. 144 if (Triple.getEnvironmentName().empty()) { 145 // Set the appropriate OS version define. 146 if (Triple.isiOS()) { 147 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 148 char Str[6]; 149 Str[0] = '0' + Maj; 150 Str[1] = '0' + (Min / 10); 151 Str[2] = '0' + (Min % 10); 152 Str[3] = '0' + (Rev / 10); 153 Str[4] = '0' + (Rev % 10); 154 Str[5] = '\0'; 155 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 156 Str); 157 } else { 158 // Note that the Driver allows versions which aren't representable in the 159 // define (because we only get a single digit for the minor and micro 160 // revision numbers). So, we limit them to the maximum representable 161 // version. 162 assert(Triple.getEnvironmentName().empty() && "Invalid environment!"); 163 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 164 char Str[5]; 165 Str[0] = '0' + (Maj / 10); 166 Str[1] = '0' + (Maj % 10); 167 Str[2] = '0' + std::min(Min, 9U); 168 Str[3] = '0' + std::min(Rev, 9U); 169 Str[4] = '\0'; 170 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 171 } 172 } 173 174 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 175 } 176 177 namespace { 178 template<typename Target> 179 class DarwinTargetInfo : public OSTargetInfo<Target> { 180 protected: 181 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 182 MacroBuilder &Builder) const { 183 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 184 this->PlatformMinVersion); 185 } 186 187 public: 188 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 189 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 190 this->MCountName = "\01mcount"; 191 } 192 193 virtual std::string isValidSectionSpecifier(StringRef SR) const { 194 // Let MCSectionMachO validate this. 195 StringRef Segment, Section; 196 unsigned TAA, StubSize; 197 bool HasTAA; 198 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 199 TAA, HasTAA, StubSize); 200 } 201 202 virtual const char *getStaticInitSectionSpecifier() const { 203 // FIXME: We should return 0 when building kexts. 204 return "__TEXT,__StaticInit,regular,pure_instructions"; 205 } 206 207 /// Darwin does not support protected visibility. Darwin's "default" 208 /// is very similar to ELF's "protected"; Darwin requires a "weak" 209 /// attribute on declarations that can be dynamically replaced. 210 virtual bool hasProtectedVisibility() const { 211 return false; 212 } 213 }; 214 215 216 // DragonFlyBSD Target 217 template<typename Target> 218 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 219 protected: 220 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 221 MacroBuilder &Builder) const { 222 // DragonFly defines; list based off of gcc output 223 Builder.defineMacro("__DragonFly__"); 224 Builder.defineMacro("__DragonFly_cc_version", "100001"); 225 Builder.defineMacro("__ELF__"); 226 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 227 Builder.defineMacro("__tune_i386__"); 228 DefineStd(Builder, "unix", Opts); 229 } 230 public: 231 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 232 : OSTargetInfo<Target>(Triple) { 233 this->UserLabelPrefix = ""; 234 235 switch (Triple.getArch()) { 236 default: 237 case llvm::Triple::x86: 238 case llvm::Triple::x86_64: 239 this->MCountName = ".mcount"; 240 break; 241 } 242 } 243 }; 244 245 // FreeBSD Target 246 template<typename Target> 247 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 248 protected: 249 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 250 MacroBuilder &Builder) const { 251 // FreeBSD defines; list based off of gcc output 252 253 unsigned Release = Triple.getOSMajorVersion(); 254 if (Release == 0U) 255 Release = 8; 256 257 Builder.defineMacro("__FreeBSD__", Twine(Release)); 258 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 259 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 260 DefineStd(Builder, "unix", Opts); 261 Builder.defineMacro("__ELF__"); 262 263 // On FreeBSD, wchar_t contains the number of the code point as 264 // used by the character set of the locale. These character sets are 265 // not necessarily a superset of ASCII. 266 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 267 } 268 public: 269 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 270 this->UserLabelPrefix = ""; 271 272 switch (Triple.getArch()) { 273 default: 274 case llvm::Triple::x86: 275 case llvm::Triple::x86_64: 276 this->MCountName = ".mcount"; 277 break; 278 case llvm::Triple::mips: 279 case llvm::Triple::mipsel: 280 case llvm::Triple::ppc: 281 case llvm::Triple::ppc64: 282 case llvm::Triple::ppc64le: 283 this->MCountName = "_mcount"; 284 break; 285 case llvm::Triple::arm: 286 this->MCountName = "__mcount"; 287 break; 288 } 289 } 290 }; 291 292 // GNU/kFreeBSD Target 293 template<typename Target> 294 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 295 protected: 296 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 297 MacroBuilder &Builder) const { 298 // GNU/kFreeBSD defines; list based off of gcc output 299 300 DefineStd(Builder, "unix", Opts); 301 Builder.defineMacro("__FreeBSD_kernel__"); 302 Builder.defineMacro("__GLIBC__"); 303 Builder.defineMacro("__ELF__"); 304 if (Opts.POSIXThreads) 305 Builder.defineMacro("_REENTRANT"); 306 if (Opts.CPlusPlus) 307 Builder.defineMacro("_GNU_SOURCE"); 308 } 309 public: 310 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 311 this->UserLabelPrefix = ""; 312 } 313 }; 314 315 // Minix Target 316 template<typename Target> 317 class MinixTargetInfo : public OSTargetInfo<Target> { 318 protected: 319 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 320 MacroBuilder &Builder) const { 321 // Minix defines 322 323 Builder.defineMacro("__minix", "3"); 324 Builder.defineMacro("_EM_WSIZE", "4"); 325 Builder.defineMacro("_EM_PSIZE", "4"); 326 Builder.defineMacro("_EM_SSIZE", "2"); 327 Builder.defineMacro("_EM_LSIZE", "4"); 328 Builder.defineMacro("_EM_FSIZE", "4"); 329 Builder.defineMacro("_EM_DSIZE", "8"); 330 Builder.defineMacro("__ELF__"); 331 DefineStd(Builder, "unix", Opts); 332 } 333 public: 334 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 335 this->UserLabelPrefix = ""; 336 } 337 }; 338 339 // Linux target 340 template<typename Target> 341 class LinuxTargetInfo : public OSTargetInfo<Target> { 342 protected: 343 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 344 MacroBuilder &Builder) const { 345 // Linux defines; list based off of gcc output 346 DefineStd(Builder, "unix", Opts); 347 DefineStd(Builder, "linux", Opts); 348 Builder.defineMacro("__gnu_linux__"); 349 Builder.defineMacro("__ELF__"); 350 if (Triple.getEnvironment() == llvm::Triple::Android) 351 Builder.defineMacro("__ANDROID__", "1"); 352 if (Opts.POSIXThreads) 353 Builder.defineMacro("_REENTRANT"); 354 if (Opts.CPlusPlus) 355 Builder.defineMacro("_GNU_SOURCE"); 356 } 357 public: 358 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 359 this->UserLabelPrefix = ""; 360 this->WIntType = TargetInfo::UnsignedInt; 361 } 362 363 virtual const char *getStaticInitSectionSpecifier() const { 364 return ".text.startup"; 365 } 366 }; 367 368 // NetBSD Target 369 template<typename Target> 370 class NetBSDTargetInfo : public OSTargetInfo<Target> { 371 protected: 372 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 373 MacroBuilder &Builder) const { 374 // NetBSD defines; list based off of gcc output 375 Builder.defineMacro("__NetBSD__"); 376 Builder.defineMacro("__unix__"); 377 Builder.defineMacro("__ELF__"); 378 if (Opts.POSIXThreads) 379 Builder.defineMacro("_POSIX_THREADS"); 380 } 381 public: 382 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 383 this->UserLabelPrefix = ""; 384 } 385 }; 386 387 // OpenBSD Target 388 template<typename Target> 389 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 390 protected: 391 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 392 MacroBuilder &Builder) const { 393 // OpenBSD defines; list based off of gcc output 394 395 Builder.defineMacro("__OpenBSD__"); 396 DefineStd(Builder, "unix", Opts); 397 Builder.defineMacro("__ELF__"); 398 if (Opts.POSIXThreads) 399 Builder.defineMacro("_REENTRANT"); 400 } 401 public: 402 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 403 this->UserLabelPrefix = ""; 404 this->TLSSupported = false; 405 406 switch (Triple.getArch()) { 407 default: 408 case llvm::Triple::x86: 409 case llvm::Triple::x86_64: 410 case llvm::Triple::arm: 411 case llvm::Triple::sparc: 412 this->MCountName = "__mcount"; 413 break; 414 case llvm::Triple::mips64: 415 case llvm::Triple::mips64el: 416 case llvm::Triple::ppc: 417 case llvm::Triple::sparcv9: 418 this->MCountName = "_mcount"; 419 break; 420 } 421 } 422 }; 423 424 // Bitrig Target 425 template<typename Target> 426 class BitrigTargetInfo : public OSTargetInfo<Target> { 427 protected: 428 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 429 MacroBuilder &Builder) const { 430 // Bitrig defines; list based off of gcc output 431 432 Builder.defineMacro("__Bitrig__"); 433 DefineStd(Builder, "unix", Opts); 434 Builder.defineMacro("__ELF__"); 435 if (Opts.POSIXThreads) 436 Builder.defineMacro("_REENTRANT"); 437 } 438 public: 439 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 440 this->UserLabelPrefix = ""; 441 this->TLSSupported = false; 442 this->MCountName = "__mcount"; 443 } 444 }; 445 446 // PSP Target 447 template<typename Target> 448 class PSPTargetInfo : public OSTargetInfo<Target> { 449 protected: 450 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 451 MacroBuilder &Builder) const { 452 // PSP defines; list based on the output of the pspdev gcc toolchain. 453 Builder.defineMacro("PSP"); 454 Builder.defineMacro("_PSP"); 455 Builder.defineMacro("__psp__"); 456 Builder.defineMacro("__ELF__"); 457 } 458 public: 459 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 460 this->UserLabelPrefix = ""; 461 } 462 }; 463 464 // PS3 PPU Target 465 template<typename Target> 466 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 467 protected: 468 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 469 MacroBuilder &Builder) const { 470 // PS3 PPU defines. 471 Builder.defineMacro("__PPC__"); 472 Builder.defineMacro("__PPU__"); 473 Builder.defineMacro("__CELLOS_LV2__"); 474 Builder.defineMacro("__ELF__"); 475 Builder.defineMacro("__LP32__"); 476 Builder.defineMacro("_ARCH_PPC64"); 477 Builder.defineMacro("__powerpc64__"); 478 } 479 public: 480 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 481 this->UserLabelPrefix = ""; 482 this->LongWidth = this->LongAlign = 32; 483 this->PointerWidth = this->PointerAlign = 32; 484 this->IntMaxType = TargetInfo::SignedLongLong; 485 this->UIntMaxType = TargetInfo::UnsignedLongLong; 486 this->Int64Type = TargetInfo::SignedLongLong; 487 this->SizeType = TargetInfo::UnsignedInt; 488 this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 489 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 490 } 491 }; 492 493 // FIXME: Need a real SPU target. 494 // PS3 SPU Target 495 template<typename Target> 496 class PS3SPUTargetInfo : public OSTargetInfo<Target> { 497 protected: 498 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 499 MacroBuilder &Builder) const { 500 // PS3 PPU defines. 501 Builder.defineMacro("__SPU__"); 502 Builder.defineMacro("__ELF__"); 503 } 504 public: 505 PS3SPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 506 this->UserLabelPrefix = ""; 507 } 508 }; 509 510 // AuroraUX target 511 template<typename Target> 512 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 513 protected: 514 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 515 MacroBuilder &Builder) const { 516 DefineStd(Builder, "sun", Opts); 517 DefineStd(Builder, "unix", Opts); 518 Builder.defineMacro("__ELF__"); 519 Builder.defineMacro("__svr4__"); 520 Builder.defineMacro("__SVR4"); 521 } 522 public: 523 AuroraUXTargetInfo(const llvm::Triple &Triple) 524 : OSTargetInfo<Target>(Triple) { 525 this->UserLabelPrefix = ""; 526 this->WCharType = this->SignedLong; 527 // FIXME: WIntType should be SignedLong 528 } 529 }; 530 531 // Solaris target 532 template<typename Target> 533 class SolarisTargetInfo : public OSTargetInfo<Target> { 534 protected: 535 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 536 MacroBuilder &Builder) const { 537 DefineStd(Builder, "sun", Opts); 538 DefineStd(Builder, "unix", Opts); 539 Builder.defineMacro("__ELF__"); 540 Builder.defineMacro("__svr4__"); 541 Builder.defineMacro("__SVR4"); 542 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 543 // newer, but to 500 for everything else. feature_test.h has a check to 544 // ensure that you are not using C99 with an old version of X/Open or C89 545 // with a new version. 546 if (Opts.C99 || Opts.C11) 547 Builder.defineMacro("_XOPEN_SOURCE", "600"); 548 else 549 Builder.defineMacro("_XOPEN_SOURCE", "500"); 550 if (Opts.CPlusPlus) 551 Builder.defineMacro("__C99FEATURES__"); 552 Builder.defineMacro("_LARGEFILE_SOURCE"); 553 Builder.defineMacro("_LARGEFILE64_SOURCE"); 554 Builder.defineMacro("__EXTENSIONS__"); 555 Builder.defineMacro("_REENTRANT"); 556 } 557 public: 558 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 559 this->UserLabelPrefix = ""; 560 this->WCharType = this->SignedInt; 561 // FIXME: WIntType should be SignedLong 562 } 563 }; 564 565 // Windows target 566 template<typename Target> 567 class WindowsTargetInfo : public OSTargetInfo<Target> { 568 protected: 569 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 570 MacroBuilder &Builder) const { 571 Builder.defineMacro("_WIN32"); 572 } 573 void getVisualStudioDefines(const LangOptions &Opts, 574 MacroBuilder &Builder) const { 575 if (Opts.CPlusPlus) { 576 if (Opts.RTTI) 577 Builder.defineMacro("_CPPRTTI"); 578 579 if (Opts.Exceptions) 580 Builder.defineMacro("_CPPUNWIND"); 581 } 582 583 if (!Opts.CharIsSigned) 584 Builder.defineMacro("_CHAR_UNSIGNED"); 585 586 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 587 // but it works for now. 588 if (Opts.POSIXThreads) 589 Builder.defineMacro("_MT"); 590 591 if (Opts.MSCVersion != 0) 592 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 593 594 if (Opts.MicrosoftExt) { 595 Builder.defineMacro("_MSC_EXTENSIONS"); 596 597 if (Opts.CPlusPlus11) { 598 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 599 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 600 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 601 } 602 } 603 604 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 605 } 606 607 public: 608 WindowsTargetInfo(const llvm::Triple &Triple) 609 : OSTargetInfo<Target>(Triple) {} 610 }; 611 612 template <typename Target> 613 class NaClTargetInfo : public OSTargetInfo<Target> { 614 protected: 615 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 616 MacroBuilder &Builder) const { 617 if (Opts.POSIXThreads) 618 Builder.defineMacro("_REENTRANT"); 619 if (Opts.CPlusPlus) 620 Builder.defineMacro("_GNU_SOURCE"); 621 622 DefineStd(Builder, "unix", Opts); 623 Builder.defineMacro("__ELF__"); 624 Builder.defineMacro("__native_client__"); 625 } 626 627 public: 628 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 629 this->UserLabelPrefix = ""; 630 this->LongAlign = 32; 631 this->LongWidth = 32; 632 this->PointerAlign = 32; 633 this->PointerWidth = 32; 634 this->IntMaxType = TargetInfo::SignedLongLong; 635 this->UIntMaxType = TargetInfo::UnsignedLongLong; 636 this->Int64Type = TargetInfo::SignedLongLong; 637 this->DoubleAlign = 64; 638 this->LongDoubleWidth = 64; 639 this->LongDoubleAlign = 64; 640 this->SizeType = TargetInfo::UnsignedInt; 641 this->PtrDiffType = TargetInfo::SignedInt; 642 this->IntPtrType = TargetInfo::SignedInt; 643 // RegParmMax is inherited from the underlying architecture 644 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 645 this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 646 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 647 } 648 virtual typename Target::CallingConvCheckResult checkCallingConvention( 649 CallingConv CC) const { 650 return CC == CC_PnaclCall ? Target::CCCR_OK : 651 Target::checkCallingConvention(CC); 652 } 653 }; 654 } // end anonymous namespace. 655 656 //===----------------------------------------------------------------------===// 657 // Specific target implementations. 658 //===----------------------------------------------------------------------===// 659 660 namespace { 661 // PPC abstract base class 662 class PPCTargetInfo : public TargetInfo { 663 static const Builtin::Info BuiltinInfo[]; 664 static const char * const GCCRegNames[]; 665 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 666 std::string CPU; 667 668 // Target cpu features. 669 bool HasVSX; 670 671 public: 672 PPCTargetInfo(const llvm::Triple &Triple) 673 : TargetInfo(Triple), HasVSX(false) { 674 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 675 LongDoubleWidth = LongDoubleAlign = 128; 676 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 677 } 678 679 /// \brief Flags for architecture specific defines. 680 typedef enum { 681 ArchDefineNone = 0, 682 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 683 ArchDefinePpcgr = 1 << 1, 684 ArchDefinePpcsq = 1 << 2, 685 ArchDefine440 = 1 << 3, 686 ArchDefine603 = 1 << 4, 687 ArchDefine604 = 1 << 5, 688 ArchDefinePwr4 = 1 << 6, 689 ArchDefinePwr5 = 1 << 7, 690 ArchDefinePwr5x = 1 << 8, 691 ArchDefinePwr6 = 1 << 9, 692 ArchDefinePwr6x = 1 << 10, 693 ArchDefinePwr7 = 1 << 11, 694 ArchDefineA2 = 1 << 12, 695 ArchDefineA2q = 1 << 13 696 } ArchDefineTypes; 697 698 // Note: GCC recognizes the following additional cpus: 699 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 700 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 701 // titan, rs64. 702 virtual bool setCPU(const std::string &Name) { 703 bool CPUKnown = llvm::StringSwitch<bool>(Name) 704 .Case("generic", true) 705 .Case("440", true) 706 .Case("450", true) 707 .Case("601", true) 708 .Case("602", true) 709 .Case("603", true) 710 .Case("603e", true) 711 .Case("603ev", true) 712 .Case("604", true) 713 .Case("604e", true) 714 .Case("620", true) 715 .Case("630", true) 716 .Case("g3", true) 717 .Case("7400", true) 718 .Case("g4", true) 719 .Case("7450", true) 720 .Case("g4+", true) 721 .Case("750", true) 722 .Case("970", true) 723 .Case("g5", true) 724 .Case("a2", true) 725 .Case("a2q", true) 726 .Case("e500mc", true) 727 .Case("e5500", true) 728 .Case("power3", true) 729 .Case("pwr3", true) 730 .Case("power4", true) 731 .Case("pwr4", true) 732 .Case("power5", true) 733 .Case("pwr5", true) 734 .Case("power5x", true) 735 .Case("pwr5x", true) 736 .Case("power6", true) 737 .Case("pwr6", true) 738 .Case("power6x", true) 739 .Case("pwr6x", true) 740 .Case("power7", true) 741 .Case("pwr7", true) 742 .Case("powerpc", true) 743 .Case("ppc", true) 744 .Case("powerpc64", true) 745 .Case("ppc64", true) 746 .Case("powerpc64le", true) 747 .Case("ppc64le", true) 748 .Default(false); 749 750 if (CPUKnown) 751 CPU = Name; 752 753 return CPUKnown; 754 } 755 756 virtual void getTargetBuiltins(const Builtin::Info *&Records, 757 unsigned &NumRecords) const { 758 Records = BuiltinInfo; 759 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 760 } 761 762 virtual bool isCLZForZeroUndef() const { return false; } 763 764 virtual void getTargetDefines(const LangOptions &Opts, 765 MacroBuilder &Builder) const; 766 767 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 768 769 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 770 DiagnosticsEngine &Diags); 771 virtual bool hasFeature(StringRef Feature) const; 772 773 virtual void getGCCRegNames(const char * const *&Names, 774 unsigned &NumNames) const; 775 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 776 unsigned &NumAliases) const; 777 virtual bool validateAsmConstraint(const char *&Name, 778 TargetInfo::ConstraintInfo &Info) const { 779 switch (*Name) { 780 default: return false; 781 case 'O': // Zero 782 break; 783 case 'b': // Base register 784 case 'f': // Floating point register 785 Info.setAllowsRegister(); 786 break; 787 // FIXME: The following are added to allow parsing. 788 // I just took a guess at what the actions should be. 789 // Also, is more specific checking needed? I.e. specific registers? 790 case 'd': // Floating point register (containing 64-bit value) 791 case 'v': // Altivec vector register 792 Info.setAllowsRegister(); 793 break; 794 case 'w': 795 switch (Name[1]) { 796 case 'd':// VSX vector register to hold vector double data 797 case 'f':// VSX vector register to hold vector float data 798 case 's':// VSX vector register to hold scalar float data 799 case 'a':// Any VSX register 800 break; 801 default: 802 return false; 803 } 804 Info.setAllowsRegister(); 805 Name++; // Skip over 'w'. 806 break; 807 case 'h': // `MQ', `CTR', or `LINK' register 808 case 'q': // `MQ' register 809 case 'c': // `CTR' register 810 case 'l': // `LINK' register 811 case 'x': // `CR' register (condition register) number 0 812 case 'y': // `CR' register (condition register) 813 case 'z': // `XER[CA]' carry bit (part of the XER register) 814 Info.setAllowsRegister(); 815 break; 816 case 'I': // Signed 16-bit constant 817 case 'J': // Unsigned 16-bit constant shifted left 16 bits 818 // (use `L' instead for SImode constants) 819 case 'K': // Unsigned 16-bit constant 820 case 'L': // Signed 16-bit constant shifted left 16 bits 821 case 'M': // Constant larger than 31 822 case 'N': // Exact power of 2 823 case 'P': // Constant whose negation is a signed 16-bit constant 824 case 'G': // Floating point constant that can be loaded into a 825 // register with one instruction per word 826 case 'H': // Integer/Floating point constant that can be loaded 827 // into a register using three instructions 828 break; 829 case 'm': // Memory operand. Note that on PowerPC targets, m can 830 // include addresses that update the base register. It 831 // is therefore only safe to use `m' in an asm statement 832 // if that asm statement accesses the operand exactly once. 833 // The asm statement must also use `%U<opno>' as a 834 // placeholder for the "update" flag in the corresponding 835 // load or store instruction. For example: 836 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 837 // is correct but: 838 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 839 // is not. Use es rather than m if you don't want the base 840 // register to be updated. 841 case 'e': 842 if (Name[1] != 's') 843 return false; 844 // es: A "stable" memory operand; that is, one which does not 845 // include any automodification of the base register. Unlike 846 // `m', this constraint can be used in asm statements that 847 // might access the operand several times, or that might not 848 // access it at all. 849 Info.setAllowsMemory(); 850 Name++; // Skip over 'e'. 851 break; 852 case 'Q': // Memory operand that is an offset from a register (it is 853 // usually better to use `m' or `es' in asm statements) 854 case 'Z': // Memory operand that is an indexed or indirect from a 855 // register (it is usually better to use `m' or `es' in 856 // asm statements) 857 Info.setAllowsMemory(); 858 Info.setAllowsRegister(); 859 break; 860 case 'R': // AIX TOC entry 861 case 'a': // Address operand that is an indexed or indirect from a 862 // register (`p' is preferable for asm statements) 863 case 'S': // Constant suitable as a 64-bit mask operand 864 case 'T': // Constant suitable as a 32-bit mask operand 865 case 'U': // System V Release 4 small data area reference 866 case 't': // AND masks that can be performed by two rldic{l, r} 867 // instructions 868 case 'W': // Vector constant that does not require memory 869 case 'j': // Vector constant that is all zeros. 870 break; 871 // End FIXME. 872 } 873 return true; 874 } 875 virtual const char *getClobbers() const { 876 return ""; 877 } 878 int getEHDataRegisterNumber(unsigned RegNo) const { 879 if (RegNo == 0) return 3; 880 if (RegNo == 1) return 4; 881 return -1; 882 } 883 }; 884 885 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 886 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 887 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 888 ALL_LANGUAGES }, 889 #include "clang/Basic/BuiltinsPPC.def" 890 }; 891 892 /// handleTargetFeatures - Perform initialization based on the user 893 /// configured set of features. 894 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 895 DiagnosticsEngine &Diags) { 896 // Remember the maximum enabled sselevel. 897 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 898 // Ignore disabled features. 899 if (Features[i][0] == '-') 900 continue; 901 902 StringRef Feature = StringRef(Features[i]).substr(1); 903 904 if (Feature == "vsx") { 905 HasVSX = true; 906 continue; 907 } 908 909 // TODO: Finish this list and add an assert that we've handled them 910 // all. 911 } 912 913 return true; 914 } 915 916 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 917 /// #defines that are not tied to a specific subtarget. 918 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 919 MacroBuilder &Builder) const { 920 // Target identification. 921 Builder.defineMacro("__ppc__"); 922 Builder.defineMacro("__PPC__"); 923 Builder.defineMacro("_ARCH_PPC"); 924 Builder.defineMacro("__powerpc__"); 925 Builder.defineMacro("__POWERPC__"); 926 if (PointerWidth == 64) { 927 Builder.defineMacro("_ARCH_PPC64"); 928 Builder.defineMacro("__powerpc64__"); 929 Builder.defineMacro("__ppc64__"); 930 Builder.defineMacro("__PPC64__"); 931 } 932 933 // Target properties. 934 if (getTriple().getArch() == llvm::Triple::ppc64le) { 935 Builder.defineMacro("_LITTLE_ENDIAN"); 936 Builder.defineMacro("__LITTLE_ENDIAN__"); 937 } else { 938 if (getTriple().getOS() != llvm::Triple::NetBSD && 939 getTriple().getOS() != llvm::Triple::OpenBSD) 940 Builder.defineMacro("_BIG_ENDIAN"); 941 Builder.defineMacro("__BIG_ENDIAN__"); 942 } 943 944 // Subtarget options. 945 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 946 Builder.defineMacro("__REGISTER_PREFIX__", ""); 947 948 // FIXME: Should be controlled by command line option. 949 if (LongDoubleWidth == 128) 950 Builder.defineMacro("__LONG_DOUBLE_128__"); 951 952 if (Opts.AltiVec) { 953 Builder.defineMacro("__VEC__", "10206"); 954 Builder.defineMacro("__ALTIVEC__"); 955 } 956 957 // CPU identification. 958 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 959 .Case("440", ArchDefineName) 960 .Case("450", ArchDefineName | ArchDefine440) 961 .Case("601", ArchDefineName) 962 .Case("602", ArchDefineName | ArchDefinePpcgr) 963 .Case("603", ArchDefineName | ArchDefinePpcgr) 964 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 965 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 966 .Case("604", ArchDefineName | ArchDefinePpcgr) 967 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 968 .Case("620", ArchDefineName | ArchDefinePpcgr) 969 .Case("630", ArchDefineName | ArchDefinePpcgr) 970 .Case("7400", ArchDefineName | ArchDefinePpcgr) 971 .Case("7450", ArchDefineName | ArchDefinePpcgr) 972 .Case("750", ArchDefineName | ArchDefinePpcgr) 973 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 974 | ArchDefinePpcsq) 975 .Case("a2", ArchDefineA2) 976 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 977 .Case("pwr3", ArchDefinePpcgr) 978 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 979 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 980 | ArchDefinePpcsq) 981 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 982 | ArchDefinePpcgr | ArchDefinePpcsq) 983 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 984 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 985 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 986 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 987 | ArchDefinePpcsq) 988 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 989 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 990 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 991 .Case("power3", ArchDefinePpcgr) 992 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 993 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 994 | ArchDefinePpcsq) 995 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 996 | ArchDefinePpcgr | ArchDefinePpcsq) 997 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 998 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 999 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1000 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1001 | ArchDefinePpcsq) 1002 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1003 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1004 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 1005 .Default(ArchDefineNone); 1006 1007 if (defs & ArchDefineName) 1008 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1009 if (defs & ArchDefinePpcgr) 1010 Builder.defineMacro("_ARCH_PPCGR"); 1011 if (defs & ArchDefinePpcsq) 1012 Builder.defineMacro("_ARCH_PPCSQ"); 1013 if (defs & ArchDefine440) 1014 Builder.defineMacro("_ARCH_440"); 1015 if (defs & ArchDefine603) 1016 Builder.defineMacro("_ARCH_603"); 1017 if (defs & ArchDefine604) 1018 Builder.defineMacro("_ARCH_604"); 1019 if (defs & ArchDefinePwr4) 1020 Builder.defineMacro("_ARCH_PWR4"); 1021 if (defs & ArchDefinePwr5) 1022 Builder.defineMacro("_ARCH_PWR5"); 1023 if (defs & ArchDefinePwr5x) 1024 Builder.defineMacro("_ARCH_PWR5X"); 1025 if (defs & ArchDefinePwr6) 1026 Builder.defineMacro("_ARCH_PWR6"); 1027 if (defs & ArchDefinePwr6x) 1028 Builder.defineMacro("_ARCH_PWR6X"); 1029 if (defs & ArchDefinePwr7) 1030 Builder.defineMacro("_ARCH_PWR7"); 1031 if (defs & ArchDefineA2) 1032 Builder.defineMacro("_ARCH_A2"); 1033 if (defs & ArchDefineA2q) { 1034 Builder.defineMacro("_ARCH_A2Q"); 1035 Builder.defineMacro("_ARCH_QP"); 1036 } 1037 1038 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1039 Builder.defineMacro("__bg__"); 1040 Builder.defineMacro("__THW_BLUEGENE__"); 1041 Builder.defineMacro("__bgq__"); 1042 Builder.defineMacro("__TOS_BGQ__"); 1043 } 1044 1045 if (HasVSX) 1046 Builder.defineMacro("__VSX__"); 1047 1048 // FIXME: The following are not yet generated here by Clang, but are 1049 // generated by GCC: 1050 // 1051 // _SOFT_FLOAT_ 1052 // __RECIP_PRECISION__ 1053 // __APPLE_ALTIVEC__ 1054 // __RECIP__ 1055 // __RECIPF__ 1056 // __RSQRTE__ 1057 // __RSQRTEF__ 1058 // _SOFT_DOUBLE_ 1059 // __NO_LWSYNC__ 1060 // __HAVE_BSWAP__ 1061 // __LONGDOUBLE128 1062 // __CMODEL_MEDIUM__ 1063 // __CMODEL_LARGE__ 1064 // _CALL_SYSV 1065 // _CALL_DARWIN 1066 // __NO_FPRS__ 1067 } 1068 1069 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1070 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1071 .Case("7400", true) 1072 .Case("g4", true) 1073 .Case("7450", true) 1074 .Case("g4+", true) 1075 .Case("970", true) 1076 .Case("g5", true) 1077 .Case("pwr6", true) 1078 .Case("pwr7", true) 1079 .Case("ppc64", true) 1080 .Case("ppc64le", true) 1081 .Default(false); 1082 1083 Features["qpx"] = (CPU == "a2q"); 1084 } 1085 1086 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1087 return Feature == "powerpc"; 1088 } 1089 1090 1091 const char * const PPCTargetInfo::GCCRegNames[] = { 1092 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1093 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1094 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1095 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1096 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1097 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1098 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1099 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1100 "mq", "lr", "ctr", "ap", 1101 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1102 "xer", 1103 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1104 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1105 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1106 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1107 "vrsave", "vscr", 1108 "spe_acc", "spefscr", 1109 "sfp" 1110 }; 1111 1112 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1113 unsigned &NumNames) const { 1114 Names = GCCRegNames; 1115 NumNames = llvm::array_lengthof(GCCRegNames); 1116 } 1117 1118 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1119 // While some of these aliases do map to different registers 1120 // they still share the same register name. 1121 { { "0" }, "r0" }, 1122 { { "1"}, "r1" }, 1123 { { "2" }, "r2" }, 1124 { { "3" }, "r3" }, 1125 { { "4" }, "r4" }, 1126 { { "5" }, "r5" }, 1127 { { "6" }, "r6" }, 1128 { { "7" }, "r7" }, 1129 { { "8" }, "r8" }, 1130 { { "9" }, "r9" }, 1131 { { "10" }, "r10" }, 1132 { { "11" }, "r11" }, 1133 { { "12" }, "r12" }, 1134 { { "13" }, "r13" }, 1135 { { "14" }, "r14" }, 1136 { { "15" }, "r15" }, 1137 { { "16" }, "r16" }, 1138 { { "17" }, "r17" }, 1139 { { "18" }, "r18" }, 1140 { { "19" }, "r19" }, 1141 { { "20" }, "r20" }, 1142 { { "21" }, "r21" }, 1143 { { "22" }, "r22" }, 1144 { { "23" }, "r23" }, 1145 { { "24" }, "r24" }, 1146 { { "25" }, "r25" }, 1147 { { "26" }, "r26" }, 1148 { { "27" }, "r27" }, 1149 { { "28" }, "r28" }, 1150 { { "29" }, "r29" }, 1151 { { "30" }, "r30" }, 1152 { { "31" }, "r31" }, 1153 { { "fr0" }, "f0" }, 1154 { { "fr1" }, "f1" }, 1155 { { "fr2" }, "f2" }, 1156 { { "fr3" }, "f3" }, 1157 { { "fr4" }, "f4" }, 1158 { { "fr5" }, "f5" }, 1159 { { "fr6" }, "f6" }, 1160 { { "fr7" }, "f7" }, 1161 { { "fr8" }, "f8" }, 1162 { { "fr9" }, "f9" }, 1163 { { "fr10" }, "f10" }, 1164 { { "fr11" }, "f11" }, 1165 { { "fr12" }, "f12" }, 1166 { { "fr13" }, "f13" }, 1167 { { "fr14" }, "f14" }, 1168 { { "fr15" }, "f15" }, 1169 { { "fr16" }, "f16" }, 1170 { { "fr17" }, "f17" }, 1171 { { "fr18" }, "f18" }, 1172 { { "fr19" }, "f19" }, 1173 { { "fr20" }, "f20" }, 1174 { { "fr21" }, "f21" }, 1175 { { "fr22" }, "f22" }, 1176 { { "fr23" }, "f23" }, 1177 { { "fr24" }, "f24" }, 1178 { { "fr25" }, "f25" }, 1179 { { "fr26" }, "f26" }, 1180 { { "fr27" }, "f27" }, 1181 { { "fr28" }, "f28" }, 1182 { { "fr29" }, "f29" }, 1183 { { "fr30" }, "f30" }, 1184 { { "fr31" }, "f31" }, 1185 { { "cc" }, "cr0" }, 1186 }; 1187 1188 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1189 unsigned &NumAliases) const { 1190 Aliases = GCCRegAliases; 1191 NumAliases = llvm::array_lengthof(GCCRegAliases); 1192 } 1193 } // end anonymous namespace. 1194 1195 namespace { 1196 class PPC32TargetInfo : public PPCTargetInfo { 1197 public: 1198 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1199 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1200 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1201 1202 switch (getTriple().getOS()) { 1203 case llvm::Triple::Linux: 1204 case llvm::Triple::FreeBSD: 1205 case llvm::Triple::NetBSD: 1206 SizeType = UnsignedInt; 1207 PtrDiffType = SignedInt; 1208 IntPtrType = SignedInt; 1209 break; 1210 default: 1211 break; 1212 } 1213 1214 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1215 LongDoubleWidth = LongDoubleAlign = 64; 1216 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1217 } 1218 1219 // PPC32 supports atomics up to 4 bytes. 1220 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1221 } 1222 1223 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1224 // This is the ELF definition, and is overridden by the Darwin sub-target 1225 return TargetInfo::PowerABIBuiltinVaList; 1226 } 1227 }; 1228 } // end anonymous namespace. 1229 1230 // Note: ABI differences may eventually require us to have a separate 1231 // TargetInfo for little endian. 1232 namespace { 1233 class PPC64TargetInfo : public PPCTargetInfo { 1234 public: 1235 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1236 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1237 IntMaxType = SignedLong; 1238 UIntMaxType = UnsignedLong; 1239 Int64Type = SignedLong; 1240 1241 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1242 LongDoubleWidth = LongDoubleAlign = 64; 1243 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1244 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1245 "i64:64:64-f32:32:32-f64:64:64-" 1246 "v128:128:128-n32:64"; 1247 } else 1248 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1249 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 1250 "v128:128:128-n32:64"; 1251 1252 // PPC64 supports atomics up to 8 bytes. 1253 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1254 } 1255 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1256 return TargetInfo::CharPtrBuiltinVaList; 1257 } 1258 }; 1259 } // end anonymous namespace. 1260 1261 1262 namespace { 1263 class DarwinPPC32TargetInfo : 1264 public DarwinTargetInfo<PPC32TargetInfo> { 1265 public: 1266 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1267 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1268 HasAlignMac68kSupport = true; 1269 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1270 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1271 LongLongAlign = 32; 1272 SuitableAlign = 128; 1273 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1274 "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1275 } 1276 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1277 return TargetInfo::CharPtrBuiltinVaList; 1278 } 1279 }; 1280 1281 class DarwinPPC64TargetInfo : 1282 public DarwinTargetInfo<PPC64TargetInfo> { 1283 public: 1284 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1285 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1286 HasAlignMac68kSupport = true; 1287 SuitableAlign = 128; 1288 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1289 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"; 1290 } 1291 }; 1292 } // end anonymous namespace. 1293 1294 namespace { 1295 static const unsigned NVPTXAddrSpaceMap[] = { 1296 1, // opencl_global 1297 3, // opencl_local 1298 4, // opencl_constant 1299 1, // cuda_device 1300 4, // cuda_constant 1301 3, // cuda_shared 1302 }; 1303 class NVPTXTargetInfo : public TargetInfo { 1304 static const char * const GCCRegNames[]; 1305 static const Builtin::Info BuiltinInfo[]; 1306 public: 1307 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1308 BigEndian = false; 1309 TLSSupported = false; 1310 LongWidth = LongAlign = 64; 1311 AddrSpaceMap = &NVPTXAddrSpaceMap; 1312 UseAddrSpaceMapMangling = true; 1313 // Define available target features 1314 // These must be defined in sorted order! 1315 NoAsmVariants = true; 1316 } 1317 virtual void getTargetDefines(const LangOptions &Opts, 1318 MacroBuilder &Builder) const { 1319 Builder.defineMacro("__PTX__"); 1320 Builder.defineMacro("__NVPTX__"); 1321 } 1322 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1323 unsigned &NumRecords) const { 1324 Records = BuiltinInfo; 1325 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1326 } 1327 virtual bool hasFeature(StringRef Feature) const { 1328 return Feature == "ptx" || Feature == "nvptx"; 1329 } 1330 1331 virtual void getGCCRegNames(const char * const *&Names, 1332 unsigned &NumNames) const; 1333 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1334 unsigned &NumAliases) const { 1335 // No aliases. 1336 Aliases = 0; 1337 NumAliases = 0; 1338 } 1339 virtual bool validateAsmConstraint(const char *&Name, 1340 TargetInfo::ConstraintInfo &Info) const { 1341 switch (*Name) { 1342 default: return false; 1343 case 'c': 1344 case 'h': 1345 case 'r': 1346 case 'l': 1347 case 'f': 1348 case 'd': 1349 Info.setAllowsRegister(); 1350 return true; 1351 } 1352 } 1353 virtual const char *getClobbers() const { 1354 // FIXME: Is this really right? 1355 return ""; 1356 } 1357 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1358 // FIXME: implement 1359 return TargetInfo::CharPtrBuiltinVaList; 1360 } 1361 virtual bool setCPU(const std::string &Name) { 1362 bool Valid = llvm::StringSwitch<bool>(Name) 1363 .Case("sm_20", true) 1364 .Case("sm_21", true) 1365 .Case("sm_30", true) 1366 .Case("sm_35", true) 1367 .Default(false); 1368 1369 return Valid; 1370 } 1371 }; 1372 1373 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1374 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1375 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1376 ALL_LANGUAGES }, 1377 #include "clang/Basic/BuiltinsNVPTX.def" 1378 }; 1379 1380 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1381 "r0" 1382 }; 1383 1384 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1385 unsigned &NumNames) const { 1386 Names = GCCRegNames; 1387 NumNames = llvm::array_lengthof(GCCRegNames); 1388 } 1389 1390 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1391 public: 1392 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1393 PointerWidth = PointerAlign = 32; 1394 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1395 DescriptionString 1396 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1397 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1398 "n16:32:64"; 1399 } 1400 }; 1401 1402 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1403 public: 1404 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1405 PointerWidth = PointerAlign = 64; 1406 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1407 DescriptionString 1408 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1409 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1410 "n16:32:64"; 1411 } 1412 }; 1413 } 1414 1415 namespace { 1416 1417 static const unsigned R600AddrSpaceMap[] = { 1418 1, // opencl_global 1419 3, // opencl_local 1420 2, // opencl_constant 1421 1, // cuda_device 1422 2, // cuda_constant 1423 3 // cuda_shared 1424 }; 1425 1426 static const char *DescriptionStringR600 = 1427 "e" 1428 "-p:32:32:32" 1429 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32" 1430 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1431 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1432 "-n32:64"; 1433 1434 static const char *DescriptionStringR600DoubleOps = 1435 "e" 1436 "-p:32:32:32" 1437 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64" 1438 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1439 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1440 "-n32:64"; 1441 1442 static const char *DescriptionStringSI = 1443 "e" 1444 "-p:64:64:64" 1445 "-p3:32:32:32" 1446 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64" 1447 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1448 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1449 "-n32:64"; 1450 1451 class R600TargetInfo : public TargetInfo { 1452 /// \brief The GPU profiles supported by the R600 target. 1453 enum GPUKind { 1454 GK_NONE, 1455 GK_R600, 1456 GK_R600_DOUBLE_OPS, 1457 GK_R700, 1458 GK_R700_DOUBLE_OPS, 1459 GK_EVERGREEN, 1460 GK_EVERGREEN_DOUBLE_OPS, 1461 GK_NORTHERN_ISLANDS, 1462 GK_CAYMAN, 1463 GK_SOUTHERN_ISLANDS, 1464 GK_SEA_ISLANDS 1465 } GPU; 1466 1467 public: 1468 R600TargetInfo(const llvm::Triple &Triple) 1469 : TargetInfo(Triple), GPU(GK_R600) { 1470 DescriptionString = DescriptionStringR600; 1471 AddrSpaceMap = &R600AddrSpaceMap; 1472 UseAddrSpaceMapMangling = true; 1473 } 1474 1475 virtual const char * getClobbers() const { 1476 return ""; 1477 } 1478 1479 virtual void getGCCRegNames(const char * const *&Names, 1480 unsigned &numNames) const { 1481 Names = NULL; 1482 numNames = 0; 1483 } 1484 1485 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1486 unsigned &NumAliases) const { 1487 Aliases = NULL; 1488 NumAliases = 0; 1489 } 1490 1491 virtual bool validateAsmConstraint(const char *&Name, 1492 TargetInfo::ConstraintInfo &info) const { 1493 return true; 1494 } 1495 1496 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1497 unsigned &NumRecords) const { 1498 Records = NULL; 1499 NumRecords = 0; 1500 } 1501 1502 1503 virtual void getTargetDefines(const LangOptions &Opts, 1504 MacroBuilder &Builder) const { 1505 Builder.defineMacro("__R600__"); 1506 } 1507 1508 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1509 return TargetInfo::CharPtrBuiltinVaList; 1510 } 1511 1512 virtual bool setCPU(const std::string &Name) { 1513 GPU = llvm::StringSwitch<GPUKind>(Name) 1514 .Case("r600" , GK_R600) 1515 .Case("rv610", GK_R600) 1516 .Case("rv620", GK_R600) 1517 .Case("rv630", GK_R600) 1518 .Case("rv635", GK_R600) 1519 .Case("rs780", GK_R600) 1520 .Case("rs880", GK_R600) 1521 .Case("rv670", GK_R600_DOUBLE_OPS) 1522 .Case("rv710", GK_R700) 1523 .Case("rv730", GK_R700) 1524 .Case("rv740", GK_R700_DOUBLE_OPS) 1525 .Case("rv770", GK_R700_DOUBLE_OPS) 1526 .Case("palm", GK_EVERGREEN) 1527 .Case("cedar", GK_EVERGREEN) 1528 .Case("sumo", GK_EVERGREEN) 1529 .Case("sumo2", GK_EVERGREEN) 1530 .Case("redwood", GK_EVERGREEN) 1531 .Case("juniper", GK_EVERGREEN) 1532 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1533 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1534 .Case("barts", GK_NORTHERN_ISLANDS) 1535 .Case("turks", GK_NORTHERN_ISLANDS) 1536 .Case("caicos", GK_NORTHERN_ISLANDS) 1537 .Case("cayman", GK_CAYMAN) 1538 .Case("aruba", GK_CAYMAN) 1539 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1540 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1541 .Case("verde", GK_SOUTHERN_ISLANDS) 1542 .Case("oland", GK_SOUTHERN_ISLANDS) 1543 .Case("bonaire", GK_SEA_ISLANDS) 1544 .Case("kabini", GK_SEA_ISLANDS) 1545 .Case("kaveri", GK_SEA_ISLANDS) 1546 .Case("hawaii", GK_SEA_ISLANDS) 1547 .Default(GK_NONE); 1548 1549 if (GPU == GK_NONE) { 1550 return false; 1551 } 1552 1553 // Set the correct data layout 1554 switch (GPU) { 1555 case GK_NONE: 1556 case GK_R600: 1557 case GK_R700: 1558 case GK_EVERGREEN: 1559 case GK_NORTHERN_ISLANDS: 1560 DescriptionString = DescriptionStringR600; 1561 break; 1562 case GK_R600_DOUBLE_OPS: 1563 case GK_R700_DOUBLE_OPS: 1564 case GK_EVERGREEN_DOUBLE_OPS: 1565 case GK_CAYMAN: 1566 DescriptionString = DescriptionStringR600DoubleOps; 1567 break; 1568 case GK_SOUTHERN_ISLANDS: 1569 case GK_SEA_ISLANDS: 1570 DescriptionString = DescriptionStringSI; 1571 break; 1572 } 1573 1574 return true; 1575 } 1576 }; 1577 1578 } // end anonymous namespace 1579 1580 namespace { 1581 // Namespace for x86 abstract base class 1582 const Builtin::Info BuiltinInfo[] = { 1583 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1584 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1585 ALL_LANGUAGES }, 1586 #include "clang/Basic/BuiltinsX86.def" 1587 }; 1588 1589 static const char* const GCCRegNames[] = { 1590 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1591 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1592 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1593 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1594 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1595 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1596 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1597 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1598 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1599 }; 1600 1601 const TargetInfo::AddlRegName AddlRegNames[] = { 1602 { { "al", "ah", "eax", "rax" }, 0 }, 1603 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1604 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1605 { { "dl", "dh", "edx", "rdx" }, 1 }, 1606 { { "esi", "rsi" }, 4 }, 1607 { { "edi", "rdi" }, 5 }, 1608 { { "esp", "rsp" }, 7 }, 1609 { { "ebp", "rbp" }, 6 }, 1610 }; 1611 1612 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1613 // most of the implementation can be shared. 1614 class X86TargetInfo : public TargetInfo { 1615 enum X86SSEEnum { 1616 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1617 } SSELevel; 1618 enum MMX3DNowEnum { 1619 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1620 } MMX3DNowLevel; 1621 enum XOPEnum { 1622 NoXOP, 1623 SSE4A, 1624 FMA4, 1625 XOP 1626 } XOPLevel; 1627 1628 bool HasAES; 1629 bool HasPCLMUL; 1630 bool HasLZCNT; 1631 bool HasRDRND; 1632 bool HasBMI; 1633 bool HasBMI2; 1634 bool HasPOPCNT; 1635 bool HasRTM; 1636 bool HasPRFCHW; 1637 bool HasRDSEED; 1638 bool HasTBM; 1639 bool HasFMA; 1640 bool HasF16C; 1641 bool HasAVX512CD, HasAVX512ER, HasAVX512PF; 1642 bool HasSHA; 1643 bool HasCX16; 1644 1645 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1646 /// 1647 /// Each enumeration represents a particular CPU supported by Clang. These 1648 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1649 enum CPUKind { 1650 CK_Generic, 1651 1652 /// \name i386 1653 /// i386-generation processors. 1654 //@{ 1655 CK_i386, 1656 //@} 1657 1658 /// \name i486 1659 /// i486-generation processors. 1660 //@{ 1661 CK_i486, 1662 CK_WinChipC6, 1663 CK_WinChip2, 1664 CK_C3, 1665 //@} 1666 1667 /// \name i586 1668 /// i586-generation processors, P5 microarchitecture based. 1669 //@{ 1670 CK_i586, 1671 CK_Pentium, 1672 CK_PentiumMMX, 1673 //@} 1674 1675 /// \name i686 1676 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1677 //@{ 1678 CK_i686, 1679 CK_PentiumPro, 1680 CK_Pentium2, 1681 CK_Pentium3, 1682 CK_Pentium3M, 1683 CK_PentiumM, 1684 CK_C3_2, 1685 1686 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1687 /// Clang however has some logic to suport this. 1688 // FIXME: Warn, deprecate, and potentially remove this. 1689 CK_Yonah, 1690 //@} 1691 1692 /// \name Netburst 1693 /// Netburst microarchitecture based processors. 1694 //@{ 1695 CK_Pentium4, 1696 CK_Pentium4M, 1697 CK_Prescott, 1698 CK_Nocona, 1699 //@} 1700 1701 /// \name Core 1702 /// Core microarchitecture based processors. 1703 //@{ 1704 CK_Core2, 1705 1706 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1707 /// codename which GCC no longer accepts as an option to -march, but Clang 1708 /// has some logic for recognizing it. 1709 // FIXME: Warn, deprecate, and potentially remove this. 1710 CK_Penryn, 1711 //@} 1712 1713 /// \name Atom 1714 /// Atom processors 1715 //@{ 1716 CK_Atom, 1717 CK_Silvermont, 1718 //@} 1719 1720 /// \name Nehalem 1721 /// Nehalem microarchitecture based processors. 1722 //@{ 1723 CK_Corei7, 1724 CK_Corei7AVX, 1725 CK_CoreAVXi, 1726 CK_CoreAVX2, 1727 //@} 1728 1729 /// \name Knights Landing 1730 /// Knights Landing processor. 1731 CK_KNL, 1732 1733 /// \name K6 1734 /// K6 architecture processors. 1735 //@{ 1736 CK_K6, 1737 CK_K6_2, 1738 CK_K6_3, 1739 //@} 1740 1741 /// \name K7 1742 /// K7 architecture processors. 1743 //@{ 1744 CK_Athlon, 1745 CK_AthlonThunderbird, 1746 CK_Athlon4, 1747 CK_AthlonXP, 1748 CK_AthlonMP, 1749 //@} 1750 1751 /// \name K8 1752 /// K8 architecture processors. 1753 //@{ 1754 CK_Athlon64, 1755 CK_Athlon64SSE3, 1756 CK_AthlonFX, 1757 CK_K8, 1758 CK_K8SSE3, 1759 CK_Opteron, 1760 CK_OpteronSSE3, 1761 CK_AMDFAM10, 1762 //@} 1763 1764 /// \name Bobcat 1765 /// Bobcat architecture processors. 1766 //@{ 1767 CK_BTVER1, 1768 CK_BTVER2, 1769 //@} 1770 1771 /// \name Bulldozer 1772 /// Bulldozer architecture processors. 1773 //@{ 1774 CK_BDVER1, 1775 CK_BDVER2, 1776 CK_BDVER3, 1777 //@} 1778 1779 /// This specification is deprecated and will be removed in the future. 1780 /// Users should prefer \see CK_K8. 1781 // FIXME: Warn on this when the CPU is set to it. 1782 CK_x86_64, 1783 //@} 1784 1785 /// \name Geode 1786 /// Geode processors. 1787 //@{ 1788 CK_Geode 1789 //@} 1790 } CPU; 1791 1792 enum FPMathKind { 1793 FP_Default, 1794 FP_SSE, 1795 FP_387 1796 } FPMath; 1797 1798 public: 1799 X86TargetInfo(const llvm::Triple &Triple) 1800 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1801 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1802 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1803 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), 1804 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1805 HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic), 1806 FPMath(FP_Default) { 1807 BigEndian = false; 1808 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1809 } 1810 virtual unsigned getFloatEvalMethod() const { 1811 // X87 evaluates with 80 bits "long double" precision. 1812 return SSELevel == NoSSE ? 2 : 0; 1813 } 1814 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1815 unsigned &NumRecords) const { 1816 Records = BuiltinInfo; 1817 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1818 } 1819 virtual void getGCCRegNames(const char * const *&Names, 1820 unsigned &NumNames) const { 1821 Names = GCCRegNames; 1822 NumNames = llvm::array_lengthof(GCCRegNames); 1823 } 1824 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1825 unsigned &NumAliases) const { 1826 Aliases = 0; 1827 NumAliases = 0; 1828 } 1829 virtual void getGCCAddlRegNames(const AddlRegName *&Names, 1830 unsigned &NumNames) const { 1831 Names = AddlRegNames; 1832 NumNames = llvm::array_lengthof(AddlRegNames); 1833 } 1834 virtual bool validateAsmConstraint(const char *&Name, 1835 TargetInfo::ConstraintInfo &info) const; 1836 virtual std::string convertConstraint(const char *&Constraint) const; 1837 virtual const char *getClobbers() const { 1838 return "~{dirflag},~{fpsr},~{flags}"; 1839 } 1840 virtual void getTargetDefines(const LangOptions &Opts, 1841 MacroBuilder &Builder) const; 1842 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1843 bool Enabled); 1844 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1845 bool Enabled); 1846 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1847 bool Enabled); 1848 virtual void setFeatureEnabled(llvm::StringMap<bool> &Features, 1849 StringRef Name, bool Enabled) const { 1850 setFeatureEnabledImpl(Features, Name, Enabled); 1851 } 1852 // This exists purely to cut down on the number of virtual calls in 1853 // getDefaultFeatures which calls this repeatedly. 1854 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1855 StringRef Name, bool Enabled); 1856 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 1857 virtual bool hasFeature(StringRef Feature) const; 1858 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 1859 DiagnosticsEngine &Diags); 1860 virtual const char* getABI() const { 1861 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1862 return "avx"; 1863 else if (getTriple().getArch() == llvm::Triple::x86 && 1864 MMX3DNowLevel == NoMMX3DNow) 1865 return "no-mmx"; 1866 return ""; 1867 } 1868 virtual bool setCPU(const std::string &Name) { 1869 CPU = llvm::StringSwitch<CPUKind>(Name) 1870 .Case("i386", CK_i386) 1871 .Case("i486", CK_i486) 1872 .Case("winchip-c6", CK_WinChipC6) 1873 .Case("winchip2", CK_WinChip2) 1874 .Case("c3", CK_C3) 1875 .Case("i586", CK_i586) 1876 .Case("pentium", CK_Pentium) 1877 .Case("pentium-mmx", CK_PentiumMMX) 1878 .Case("i686", CK_i686) 1879 .Case("pentiumpro", CK_PentiumPro) 1880 .Case("pentium2", CK_Pentium2) 1881 .Case("pentium3", CK_Pentium3) 1882 .Case("pentium3m", CK_Pentium3M) 1883 .Case("pentium-m", CK_PentiumM) 1884 .Case("c3-2", CK_C3_2) 1885 .Case("yonah", CK_Yonah) 1886 .Case("pentium4", CK_Pentium4) 1887 .Case("pentium4m", CK_Pentium4M) 1888 .Case("prescott", CK_Prescott) 1889 .Case("nocona", CK_Nocona) 1890 .Case("core2", CK_Core2) 1891 .Case("penryn", CK_Penryn) 1892 .Case("atom", CK_Atom) 1893 .Case("slm", CK_Silvermont) 1894 .Case("corei7", CK_Corei7) 1895 .Case("corei7-avx", CK_Corei7AVX) 1896 .Case("core-avx-i", CK_CoreAVXi) 1897 .Case("core-avx2", CK_CoreAVX2) 1898 .Case("knl", CK_KNL) 1899 .Case("k6", CK_K6) 1900 .Case("k6-2", CK_K6_2) 1901 .Case("k6-3", CK_K6_3) 1902 .Case("athlon", CK_Athlon) 1903 .Case("athlon-tbird", CK_AthlonThunderbird) 1904 .Case("athlon-4", CK_Athlon4) 1905 .Case("athlon-xp", CK_AthlonXP) 1906 .Case("athlon-mp", CK_AthlonMP) 1907 .Case("athlon64", CK_Athlon64) 1908 .Case("athlon64-sse3", CK_Athlon64SSE3) 1909 .Case("athlon-fx", CK_AthlonFX) 1910 .Case("k8", CK_K8) 1911 .Case("k8-sse3", CK_K8SSE3) 1912 .Case("opteron", CK_Opteron) 1913 .Case("opteron-sse3", CK_OpteronSSE3) 1914 .Case("amdfam10", CK_AMDFAM10) 1915 .Case("btver1", CK_BTVER1) 1916 .Case("btver2", CK_BTVER2) 1917 .Case("bdver1", CK_BDVER1) 1918 .Case("bdver2", CK_BDVER2) 1919 .Case("bdver3", CK_BDVER3) 1920 .Case("x86-64", CK_x86_64) 1921 .Case("geode", CK_Geode) 1922 .Default(CK_Generic); 1923 1924 // Perform any per-CPU checks necessary to determine if this CPU is 1925 // acceptable. 1926 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1927 // invalid without explaining *why*. 1928 switch (CPU) { 1929 case CK_Generic: 1930 // No processor selected! 1931 return false; 1932 1933 case CK_i386: 1934 case CK_i486: 1935 case CK_WinChipC6: 1936 case CK_WinChip2: 1937 case CK_C3: 1938 case CK_i586: 1939 case CK_Pentium: 1940 case CK_PentiumMMX: 1941 case CK_i686: 1942 case CK_PentiumPro: 1943 case CK_Pentium2: 1944 case CK_Pentium3: 1945 case CK_Pentium3M: 1946 case CK_PentiumM: 1947 case CK_Yonah: 1948 case CK_C3_2: 1949 case CK_Pentium4: 1950 case CK_Pentium4M: 1951 case CK_Prescott: 1952 case CK_K6: 1953 case CK_K6_2: 1954 case CK_K6_3: 1955 case CK_Athlon: 1956 case CK_AthlonThunderbird: 1957 case CK_Athlon4: 1958 case CK_AthlonXP: 1959 case CK_AthlonMP: 1960 case CK_Geode: 1961 // Only accept certain architectures when compiling in 32-bit mode. 1962 if (getTriple().getArch() != llvm::Triple::x86) 1963 return false; 1964 1965 // Fallthrough 1966 case CK_Nocona: 1967 case CK_Core2: 1968 case CK_Penryn: 1969 case CK_Atom: 1970 case CK_Silvermont: 1971 case CK_Corei7: 1972 case CK_Corei7AVX: 1973 case CK_CoreAVXi: 1974 case CK_CoreAVX2: 1975 case CK_KNL: 1976 case CK_Athlon64: 1977 case CK_Athlon64SSE3: 1978 case CK_AthlonFX: 1979 case CK_K8: 1980 case CK_K8SSE3: 1981 case CK_Opteron: 1982 case CK_OpteronSSE3: 1983 case CK_AMDFAM10: 1984 case CK_BTVER1: 1985 case CK_BTVER2: 1986 case CK_BDVER1: 1987 case CK_BDVER2: 1988 case CK_BDVER3: 1989 case CK_x86_64: 1990 return true; 1991 } 1992 llvm_unreachable("Unhandled CPU kind"); 1993 } 1994 1995 virtual bool setFPMath(StringRef Name); 1996 1997 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 1998 // We accept all non-ARM calling conventions 1999 return (CC == CC_X86ThisCall || 2000 CC == CC_X86FastCall || 2001 CC == CC_X86StdCall || 2002 CC == CC_C || 2003 CC == CC_X86Pascal || 2004 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2005 } 2006 2007 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 2008 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2009 } 2010 }; 2011 2012 bool X86TargetInfo::setFPMath(StringRef Name) { 2013 if (Name == "387") { 2014 FPMath = FP_387; 2015 return true; 2016 } 2017 if (Name == "sse") { 2018 FPMath = FP_SSE; 2019 return true; 2020 } 2021 return false; 2022 } 2023 2024 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2025 // FIXME: This *really* should not be here. 2026 2027 // X86_64 always has SSE2. 2028 if (getTriple().getArch() == llvm::Triple::x86_64) 2029 setFeatureEnabledImpl(Features, "sse2", true); 2030 2031 switch (CPU) { 2032 case CK_Generic: 2033 case CK_i386: 2034 case CK_i486: 2035 case CK_i586: 2036 case CK_Pentium: 2037 case CK_i686: 2038 case CK_PentiumPro: 2039 break; 2040 case CK_PentiumMMX: 2041 case CK_Pentium2: 2042 setFeatureEnabledImpl(Features, "mmx", true); 2043 break; 2044 case CK_Pentium3: 2045 case CK_Pentium3M: 2046 setFeatureEnabledImpl(Features, "sse", true); 2047 break; 2048 case CK_PentiumM: 2049 case CK_Pentium4: 2050 case CK_Pentium4M: 2051 case CK_x86_64: 2052 setFeatureEnabledImpl(Features, "sse2", true); 2053 break; 2054 case CK_Yonah: 2055 case CK_Prescott: 2056 case CK_Nocona: 2057 setFeatureEnabledImpl(Features, "sse3", true); 2058 setFeatureEnabledImpl(Features, "cx16", true); 2059 break; 2060 case CK_Core2: 2061 setFeatureEnabledImpl(Features, "ssse3", true); 2062 setFeatureEnabledImpl(Features, "cx16", true); 2063 break; 2064 case CK_Penryn: 2065 setFeatureEnabledImpl(Features, "sse4.1", true); 2066 setFeatureEnabledImpl(Features, "cx16", true); 2067 break; 2068 case CK_Atom: 2069 setFeatureEnabledImpl(Features, "ssse3", true); 2070 setFeatureEnabledImpl(Features, "cx16", true); 2071 break; 2072 case CK_Silvermont: 2073 setFeatureEnabledImpl(Features, "sse4.2", true); 2074 setFeatureEnabledImpl(Features, "aes", true); 2075 setFeatureEnabledImpl(Features, "cx16", true); 2076 setFeatureEnabledImpl(Features, "pclmul", true); 2077 break; 2078 case CK_Corei7: 2079 setFeatureEnabledImpl(Features, "sse4.2", true); 2080 setFeatureEnabledImpl(Features, "cx16", true); 2081 break; 2082 case CK_Corei7AVX: 2083 setFeatureEnabledImpl(Features, "avx", true); 2084 setFeatureEnabledImpl(Features, "aes", true); 2085 setFeatureEnabledImpl(Features, "cx16", true); 2086 setFeatureEnabledImpl(Features, "pclmul", true); 2087 break; 2088 case CK_CoreAVXi: 2089 setFeatureEnabledImpl(Features, "avx", true); 2090 setFeatureEnabledImpl(Features, "aes", true); 2091 setFeatureEnabledImpl(Features, "pclmul", true); 2092 setFeatureEnabledImpl(Features, "rdrnd", true); 2093 setFeatureEnabledImpl(Features, "f16c", true); 2094 break; 2095 case CK_CoreAVX2: 2096 setFeatureEnabledImpl(Features, "avx2", true); 2097 setFeatureEnabledImpl(Features, "aes", true); 2098 setFeatureEnabledImpl(Features, "pclmul", true); 2099 setFeatureEnabledImpl(Features, "lzcnt", true); 2100 setFeatureEnabledImpl(Features, "rdrnd", true); 2101 setFeatureEnabledImpl(Features, "f16c", true); 2102 setFeatureEnabledImpl(Features, "bmi", true); 2103 setFeatureEnabledImpl(Features, "bmi2", true); 2104 setFeatureEnabledImpl(Features, "rtm", true); 2105 setFeatureEnabledImpl(Features, "fma", true); 2106 setFeatureEnabledImpl(Features, "cx16", true); 2107 break; 2108 case CK_KNL: 2109 setFeatureEnabledImpl(Features, "avx512f", true); 2110 setFeatureEnabledImpl(Features, "avx512cd", true); 2111 setFeatureEnabledImpl(Features, "avx512er", true); 2112 setFeatureEnabledImpl(Features, "avx512pf", true); 2113 setFeatureEnabledImpl(Features, "aes", true); 2114 setFeatureEnabledImpl(Features, "pclmul", true); 2115 setFeatureEnabledImpl(Features, "lzcnt", true); 2116 setFeatureEnabledImpl(Features, "rdrnd", true); 2117 setFeatureEnabledImpl(Features, "f16c", true); 2118 setFeatureEnabledImpl(Features, "bmi", true); 2119 setFeatureEnabledImpl(Features, "bmi2", true); 2120 setFeatureEnabledImpl(Features, "rtm", true); 2121 setFeatureEnabledImpl(Features, "fma", true); 2122 break; 2123 case CK_K6: 2124 case CK_WinChipC6: 2125 setFeatureEnabledImpl(Features, "mmx", true); 2126 break; 2127 case CK_K6_2: 2128 case CK_K6_3: 2129 case CK_WinChip2: 2130 case CK_C3: 2131 setFeatureEnabledImpl(Features, "3dnow", true); 2132 break; 2133 case CK_Athlon: 2134 case CK_AthlonThunderbird: 2135 case CK_Geode: 2136 setFeatureEnabledImpl(Features, "3dnowa", true); 2137 break; 2138 case CK_Athlon4: 2139 case CK_AthlonXP: 2140 case CK_AthlonMP: 2141 setFeatureEnabledImpl(Features, "sse", true); 2142 setFeatureEnabledImpl(Features, "3dnowa", true); 2143 break; 2144 case CK_K8: 2145 case CK_Opteron: 2146 case CK_Athlon64: 2147 case CK_AthlonFX: 2148 setFeatureEnabledImpl(Features, "sse2", true); 2149 setFeatureEnabledImpl(Features, "3dnowa", true); 2150 break; 2151 case CK_K8SSE3: 2152 case CK_OpteronSSE3: 2153 case CK_Athlon64SSE3: 2154 setFeatureEnabledImpl(Features, "sse3", true); 2155 setFeatureEnabledImpl(Features, "3dnowa", true); 2156 break; 2157 case CK_AMDFAM10: 2158 setFeatureEnabledImpl(Features, "sse3", true); 2159 setFeatureEnabledImpl(Features, "sse4a", true); 2160 setFeatureEnabledImpl(Features, "3dnowa", true); 2161 setFeatureEnabledImpl(Features, "lzcnt", true); 2162 setFeatureEnabledImpl(Features, "popcnt", true); 2163 break; 2164 case CK_BTVER1: 2165 setFeatureEnabledImpl(Features, "ssse3", true); 2166 setFeatureEnabledImpl(Features, "sse4a", true); 2167 setFeatureEnabledImpl(Features, "cx16", true); 2168 setFeatureEnabledImpl(Features, "lzcnt", true); 2169 setFeatureEnabledImpl(Features, "popcnt", true); 2170 setFeatureEnabledImpl(Features, "prfchw", true); 2171 break; 2172 case CK_BTVER2: 2173 setFeatureEnabledImpl(Features, "avx", true); 2174 setFeatureEnabledImpl(Features, "sse4a", true); 2175 setFeatureEnabledImpl(Features, "lzcnt", true); 2176 setFeatureEnabledImpl(Features, "aes", true); 2177 setFeatureEnabledImpl(Features, "pclmul", true); 2178 setFeatureEnabledImpl(Features, "prfchw", true); 2179 setFeatureEnabledImpl(Features, "bmi", true); 2180 setFeatureEnabledImpl(Features, "f16c", true); 2181 setFeatureEnabledImpl(Features, "cx16", true); 2182 break; 2183 case CK_BDVER1: 2184 setFeatureEnabledImpl(Features, "xop", true); 2185 setFeatureEnabledImpl(Features, "lzcnt", true); 2186 setFeatureEnabledImpl(Features, "aes", true); 2187 setFeatureEnabledImpl(Features, "pclmul", true); 2188 setFeatureEnabledImpl(Features, "prfchw", true); 2189 setFeatureEnabledImpl(Features, "cx16", true); 2190 break; 2191 case CK_BDVER2: 2192 case CK_BDVER3: 2193 setFeatureEnabledImpl(Features, "xop", true); 2194 setFeatureEnabledImpl(Features, "lzcnt", true); 2195 setFeatureEnabledImpl(Features, "aes", true); 2196 setFeatureEnabledImpl(Features, "pclmul", true); 2197 setFeatureEnabledImpl(Features, "prfchw", true); 2198 setFeatureEnabledImpl(Features, "bmi", true); 2199 setFeatureEnabledImpl(Features, "fma", true); 2200 setFeatureEnabledImpl(Features, "f16c", true); 2201 setFeatureEnabledImpl(Features, "tbm", true); 2202 setFeatureEnabledImpl(Features, "cx16", true); 2203 break; 2204 case CK_C3_2: 2205 setFeatureEnabledImpl(Features, "sse", true); 2206 break; 2207 } 2208 } 2209 2210 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2211 X86SSEEnum Level, bool Enabled) { 2212 if (Enabled) { 2213 switch (Level) { 2214 case AVX512F: 2215 Features["avx512f"] = true; 2216 case AVX2: 2217 Features["avx2"] = true; 2218 case AVX: 2219 Features["avx"] = true; 2220 case SSE42: 2221 Features["sse4.2"] = true; 2222 case SSE41: 2223 Features["sse4.1"] = true; 2224 case SSSE3: 2225 Features["ssse3"] = true; 2226 case SSE3: 2227 Features["sse3"] = true; 2228 case SSE2: 2229 Features["sse2"] = true; 2230 case SSE1: 2231 Features["sse"] = true; 2232 case NoSSE: 2233 break; 2234 } 2235 return; 2236 } 2237 2238 switch (Level) { 2239 case NoSSE: 2240 case SSE1: 2241 Features["sse"] = false; 2242 case SSE2: 2243 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2244 Features["sha"] = false; 2245 case SSE3: 2246 Features["sse3"] = false; 2247 setXOPLevel(Features, NoXOP, false); 2248 case SSSE3: 2249 Features["ssse3"] = false; 2250 case SSE41: 2251 Features["sse4.1"] = false; 2252 case SSE42: 2253 Features["sse4.2"] = false; 2254 case AVX: 2255 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2256 setXOPLevel(Features, FMA4, false); 2257 case AVX2: 2258 Features["avx2"] = false; 2259 case AVX512F: 2260 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2261 Features["avx512pf"] = false; 2262 } 2263 } 2264 2265 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2266 MMX3DNowEnum Level, bool Enabled) { 2267 if (Enabled) { 2268 switch (Level) { 2269 case AMD3DNowAthlon: 2270 Features["3dnowa"] = true; 2271 case AMD3DNow: 2272 Features["3dnow"] = true; 2273 case MMX: 2274 Features["mmx"] = true; 2275 case NoMMX3DNow: 2276 break; 2277 } 2278 return; 2279 } 2280 2281 switch (Level) { 2282 case NoMMX3DNow: 2283 case MMX: 2284 Features["mmx"] = false; 2285 case AMD3DNow: 2286 Features["3dnow"] = false; 2287 case AMD3DNowAthlon: 2288 Features["3dnowa"] = false; 2289 } 2290 } 2291 2292 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2293 bool Enabled) { 2294 if (Enabled) { 2295 switch (Level) { 2296 case XOP: 2297 Features["xop"] = true; 2298 case FMA4: 2299 Features["fma4"] = true; 2300 setSSELevel(Features, AVX, true); 2301 case SSE4A: 2302 Features["sse4a"] = true; 2303 setSSELevel(Features, SSE3, true); 2304 case NoXOP: 2305 break; 2306 } 2307 return; 2308 } 2309 2310 switch (Level) { 2311 case NoXOP: 2312 case SSE4A: 2313 Features["sse4a"] = false; 2314 case FMA4: 2315 Features["fma4"] = false; 2316 case XOP: 2317 Features["xop"] = false; 2318 } 2319 } 2320 2321 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2322 StringRef Name, bool Enabled) { 2323 // FIXME: This *really* should not be here. We need some way of translating 2324 // options into llvm subtarget features. 2325 if (Name == "sse4") 2326 Name = "sse4.2"; 2327 2328 Features[Name] = Enabled; 2329 2330 if (Name == "mmx") { 2331 setMMXLevel(Features, MMX, Enabled); 2332 } else if (Name == "sse") { 2333 setSSELevel(Features, SSE1, Enabled); 2334 } else if (Name == "sse2") { 2335 setSSELevel(Features, SSE2, Enabled); 2336 } else if (Name == "sse3") { 2337 setSSELevel(Features, SSE3, Enabled); 2338 } else if (Name == "ssse3") { 2339 setSSELevel(Features, SSSE3, Enabled); 2340 } else if (Name == "sse4.2") { 2341 setSSELevel(Features, SSE42, Enabled); 2342 } else if (Name == "sse4.1") { 2343 setSSELevel(Features, SSE41, Enabled); 2344 } else if (Name == "3dnow") { 2345 setMMXLevel(Features, AMD3DNow, Enabled); 2346 } else if (Name == "3dnowa") { 2347 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2348 } else if (Name == "aes") { 2349 if (Enabled) 2350 setSSELevel(Features, SSE2, Enabled); 2351 } else if (Name == "pclmul") { 2352 if (Enabled) 2353 setSSELevel(Features, SSE2, Enabled); 2354 } else if (Name == "avx") { 2355 setSSELevel(Features, AVX, Enabled); 2356 } else if (Name == "avx2") { 2357 setSSELevel(Features, AVX2, Enabled); 2358 } else if (Name == "avx512f") { 2359 setSSELevel(Features, AVX512F, Enabled); 2360 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") { 2361 if (Enabled) 2362 setSSELevel(Features, AVX512F, Enabled); 2363 } else if (Name == "fma") { 2364 if (Enabled) 2365 setSSELevel(Features, AVX, Enabled); 2366 } else if (Name == "fma4") { 2367 setXOPLevel(Features, FMA4, Enabled); 2368 } else if (Name == "xop") { 2369 setXOPLevel(Features, XOP, Enabled); 2370 } else if (Name == "sse4a") { 2371 setXOPLevel(Features, SSE4A, Enabled); 2372 } else if (Name == "f16c") { 2373 if (Enabled) 2374 setSSELevel(Features, AVX, Enabled); 2375 } else if (Name == "sha") { 2376 if (Enabled) 2377 setSSELevel(Features, SSE2, Enabled); 2378 } 2379 } 2380 2381 /// handleTargetFeatures - Perform initialization based on the user 2382 /// configured set of features. 2383 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2384 DiagnosticsEngine &Diags) { 2385 // Remember the maximum enabled sselevel. 2386 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2387 // Ignore disabled features. 2388 if (Features[i][0] == '-') 2389 continue; 2390 2391 StringRef Feature = StringRef(Features[i]).substr(1); 2392 2393 if (Feature == "aes") { 2394 HasAES = true; 2395 continue; 2396 } 2397 2398 if (Feature == "pclmul") { 2399 HasPCLMUL = true; 2400 continue; 2401 } 2402 2403 if (Feature == "lzcnt") { 2404 HasLZCNT = true; 2405 continue; 2406 } 2407 2408 if (Feature == "rdrnd") { 2409 HasRDRND = true; 2410 continue; 2411 } 2412 2413 if (Feature == "bmi") { 2414 HasBMI = true; 2415 continue; 2416 } 2417 2418 if (Feature == "bmi2") { 2419 HasBMI2 = true; 2420 continue; 2421 } 2422 2423 if (Feature == "popcnt") { 2424 HasPOPCNT = true; 2425 continue; 2426 } 2427 2428 if (Feature == "rtm") { 2429 HasRTM = true; 2430 continue; 2431 } 2432 2433 if (Feature == "prfchw") { 2434 HasPRFCHW = true; 2435 continue; 2436 } 2437 2438 if (Feature == "rdseed") { 2439 HasRDSEED = true; 2440 continue; 2441 } 2442 2443 if (Feature == "tbm") { 2444 HasTBM = true; 2445 continue; 2446 } 2447 2448 if (Feature == "fma") { 2449 HasFMA = true; 2450 continue; 2451 } 2452 2453 if (Feature == "f16c") { 2454 HasF16C = true; 2455 continue; 2456 } 2457 2458 if (Feature == "avx512cd") { 2459 HasAVX512CD = true; 2460 continue; 2461 } 2462 2463 if (Feature == "avx512er") { 2464 HasAVX512ER = true; 2465 continue; 2466 } 2467 2468 if (Feature == "avx512pf") { 2469 HasAVX512PF = true; 2470 continue; 2471 } 2472 2473 if (Feature == "sha") { 2474 HasSHA = true; 2475 continue; 2476 } 2477 2478 if (Feature == "cx16") { 2479 HasCX16 = true; 2480 continue; 2481 } 2482 2483 assert(Features[i][0] == '+' && "Invalid target feature!"); 2484 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2485 .Case("avx512f", AVX512F) 2486 .Case("avx2", AVX2) 2487 .Case("avx", AVX) 2488 .Case("sse4.2", SSE42) 2489 .Case("sse4.1", SSE41) 2490 .Case("ssse3", SSSE3) 2491 .Case("sse3", SSE3) 2492 .Case("sse2", SSE2) 2493 .Case("sse", SSE1) 2494 .Default(NoSSE); 2495 SSELevel = std::max(SSELevel, Level); 2496 2497 MMX3DNowEnum ThreeDNowLevel = 2498 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2499 .Case("3dnowa", AMD3DNowAthlon) 2500 .Case("3dnow", AMD3DNow) 2501 .Case("mmx", MMX) 2502 .Default(NoMMX3DNow); 2503 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2504 2505 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2506 .Case("xop", XOP) 2507 .Case("fma4", FMA4) 2508 .Case("sse4a", SSE4A) 2509 .Default(NoXOP); 2510 XOPLevel = std::max(XOPLevel, XLevel); 2511 } 2512 2513 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2514 // Can't do this earlier because we need to be able to explicitly enable 2515 // popcnt and still disable sse4.2. 2516 if (!HasPOPCNT && SSELevel >= SSE42 && 2517 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2518 HasPOPCNT = true; 2519 Features.push_back("+popcnt"); 2520 } 2521 2522 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2523 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2524 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2525 HasPRFCHW = true; 2526 Features.push_back("+prfchw"); 2527 } 2528 2529 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2530 // matches the selected sse level. 2531 if (FPMath == FP_SSE && SSELevel < SSE1) { 2532 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2533 return false; 2534 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2535 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2536 return false; 2537 } 2538 2539 // Don't tell the backend if we're turning off mmx; it will end up disabling 2540 // SSE, which we don't want. 2541 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2542 // then enable MMX. 2543 std::vector<std::string>::iterator it; 2544 it = std::find(Features.begin(), Features.end(), "-mmx"); 2545 if (it != Features.end()) 2546 Features.erase(it); 2547 else if (SSELevel > NoSSE) 2548 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2549 return true; 2550 } 2551 2552 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2553 /// definitions for this particular subtarget. 2554 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2555 MacroBuilder &Builder) const { 2556 // Target identification. 2557 if (getTriple().getArch() == llvm::Triple::x86_64) { 2558 Builder.defineMacro("__amd64__"); 2559 Builder.defineMacro("__amd64"); 2560 Builder.defineMacro("__x86_64"); 2561 Builder.defineMacro("__x86_64__"); 2562 } else { 2563 DefineStd(Builder, "i386", Opts); 2564 } 2565 2566 // Subtarget options. 2567 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2568 // truly should be based on -mtune options. 2569 switch (CPU) { 2570 case CK_Generic: 2571 break; 2572 case CK_i386: 2573 // The rest are coming from the i386 define above. 2574 Builder.defineMacro("__tune_i386__"); 2575 break; 2576 case CK_i486: 2577 case CK_WinChipC6: 2578 case CK_WinChip2: 2579 case CK_C3: 2580 defineCPUMacros(Builder, "i486"); 2581 break; 2582 case CK_PentiumMMX: 2583 Builder.defineMacro("__pentium_mmx__"); 2584 Builder.defineMacro("__tune_pentium_mmx__"); 2585 // Fallthrough 2586 case CK_i586: 2587 case CK_Pentium: 2588 defineCPUMacros(Builder, "i586"); 2589 defineCPUMacros(Builder, "pentium"); 2590 break; 2591 case CK_Pentium3: 2592 case CK_Pentium3M: 2593 case CK_PentiumM: 2594 Builder.defineMacro("__tune_pentium3__"); 2595 // Fallthrough 2596 case CK_Pentium2: 2597 case CK_C3_2: 2598 Builder.defineMacro("__tune_pentium2__"); 2599 // Fallthrough 2600 case CK_PentiumPro: 2601 Builder.defineMacro("__tune_i686__"); 2602 Builder.defineMacro("__tune_pentiumpro__"); 2603 // Fallthrough 2604 case CK_i686: 2605 Builder.defineMacro("__i686"); 2606 Builder.defineMacro("__i686__"); 2607 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2608 Builder.defineMacro("__pentiumpro"); 2609 Builder.defineMacro("__pentiumpro__"); 2610 break; 2611 case CK_Pentium4: 2612 case CK_Pentium4M: 2613 defineCPUMacros(Builder, "pentium4"); 2614 break; 2615 case CK_Yonah: 2616 case CK_Prescott: 2617 case CK_Nocona: 2618 defineCPUMacros(Builder, "nocona"); 2619 break; 2620 case CK_Core2: 2621 case CK_Penryn: 2622 defineCPUMacros(Builder, "core2"); 2623 break; 2624 case CK_Atom: 2625 defineCPUMacros(Builder, "atom"); 2626 break; 2627 case CK_Silvermont: 2628 defineCPUMacros(Builder, "slm"); 2629 break; 2630 case CK_Corei7: 2631 case CK_Corei7AVX: 2632 case CK_CoreAVXi: 2633 case CK_CoreAVX2: 2634 defineCPUMacros(Builder, "corei7"); 2635 break; 2636 case CK_KNL: 2637 defineCPUMacros(Builder, "knl"); 2638 break; 2639 case CK_K6_2: 2640 Builder.defineMacro("__k6_2__"); 2641 Builder.defineMacro("__tune_k6_2__"); 2642 // Fallthrough 2643 case CK_K6_3: 2644 if (CPU != CK_K6_2) { // In case of fallthrough 2645 // FIXME: GCC may be enabling these in cases where some other k6 2646 // architecture is specified but -m3dnow is explicitly provided. The 2647 // exact semantics need to be determined and emulated here. 2648 Builder.defineMacro("__k6_3__"); 2649 Builder.defineMacro("__tune_k6_3__"); 2650 } 2651 // Fallthrough 2652 case CK_K6: 2653 defineCPUMacros(Builder, "k6"); 2654 break; 2655 case CK_Athlon: 2656 case CK_AthlonThunderbird: 2657 case CK_Athlon4: 2658 case CK_AthlonXP: 2659 case CK_AthlonMP: 2660 defineCPUMacros(Builder, "athlon"); 2661 if (SSELevel != NoSSE) { 2662 Builder.defineMacro("__athlon_sse__"); 2663 Builder.defineMacro("__tune_athlon_sse__"); 2664 } 2665 break; 2666 case CK_K8: 2667 case CK_K8SSE3: 2668 case CK_x86_64: 2669 case CK_Opteron: 2670 case CK_OpteronSSE3: 2671 case CK_Athlon64: 2672 case CK_Athlon64SSE3: 2673 case CK_AthlonFX: 2674 defineCPUMacros(Builder, "k8"); 2675 break; 2676 case CK_AMDFAM10: 2677 defineCPUMacros(Builder, "amdfam10"); 2678 break; 2679 case CK_BTVER1: 2680 defineCPUMacros(Builder, "btver1"); 2681 break; 2682 case CK_BTVER2: 2683 defineCPUMacros(Builder, "btver2"); 2684 break; 2685 case CK_BDVER1: 2686 defineCPUMacros(Builder, "bdver1"); 2687 break; 2688 case CK_BDVER2: 2689 defineCPUMacros(Builder, "bdver2"); 2690 break; 2691 case CK_BDVER3: 2692 defineCPUMacros(Builder, "bdver3"); 2693 break; 2694 case CK_Geode: 2695 defineCPUMacros(Builder, "geode"); 2696 break; 2697 } 2698 2699 // Target properties. 2700 Builder.defineMacro("__LITTLE_ENDIAN__"); 2701 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2702 2703 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2704 // functions in glibc header files that use FP Stack inline asm which the 2705 // backend can't deal with (PR879). 2706 Builder.defineMacro("__NO_MATH_INLINES"); 2707 2708 if (HasAES) 2709 Builder.defineMacro("__AES__"); 2710 2711 if (HasPCLMUL) 2712 Builder.defineMacro("__PCLMUL__"); 2713 2714 if (HasLZCNT) 2715 Builder.defineMacro("__LZCNT__"); 2716 2717 if (HasRDRND) 2718 Builder.defineMacro("__RDRND__"); 2719 2720 if (HasBMI) 2721 Builder.defineMacro("__BMI__"); 2722 2723 if (HasBMI2) 2724 Builder.defineMacro("__BMI2__"); 2725 2726 if (HasPOPCNT) 2727 Builder.defineMacro("__POPCNT__"); 2728 2729 if (HasRTM) 2730 Builder.defineMacro("__RTM__"); 2731 2732 if (HasPRFCHW) 2733 Builder.defineMacro("__PRFCHW__"); 2734 2735 if (HasRDSEED) 2736 Builder.defineMacro("__RDSEED__"); 2737 2738 if (HasTBM) 2739 Builder.defineMacro("__TBM__"); 2740 2741 switch (XOPLevel) { 2742 case XOP: 2743 Builder.defineMacro("__XOP__"); 2744 case FMA4: 2745 Builder.defineMacro("__FMA4__"); 2746 case SSE4A: 2747 Builder.defineMacro("__SSE4A__"); 2748 case NoXOP: 2749 break; 2750 } 2751 2752 if (HasFMA) 2753 Builder.defineMacro("__FMA__"); 2754 2755 if (HasF16C) 2756 Builder.defineMacro("__F16C__"); 2757 2758 if (HasAVX512CD) 2759 Builder.defineMacro("__AVX512CD__"); 2760 if (HasAVX512ER) 2761 Builder.defineMacro("__AVX512ER__"); 2762 if (HasAVX512PF) 2763 Builder.defineMacro("__AVX512PF__"); 2764 2765 if (HasSHA) 2766 Builder.defineMacro("__SHA__"); 2767 2768 if (HasCX16) 2769 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2770 2771 // Each case falls through to the previous one here. 2772 switch (SSELevel) { 2773 case AVX512F: 2774 Builder.defineMacro("__AVX512F__"); 2775 case AVX2: 2776 Builder.defineMacro("__AVX2__"); 2777 case AVX: 2778 Builder.defineMacro("__AVX__"); 2779 case SSE42: 2780 Builder.defineMacro("__SSE4_2__"); 2781 case SSE41: 2782 Builder.defineMacro("__SSE4_1__"); 2783 case SSSE3: 2784 Builder.defineMacro("__SSSE3__"); 2785 case SSE3: 2786 Builder.defineMacro("__SSE3__"); 2787 case SSE2: 2788 Builder.defineMacro("__SSE2__"); 2789 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2790 case SSE1: 2791 Builder.defineMacro("__SSE__"); 2792 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2793 case NoSSE: 2794 break; 2795 } 2796 2797 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2798 switch (SSELevel) { 2799 case AVX512F: 2800 case AVX2: 2801 case AVX: 2802 case SSE42: 2803 case SSE41: 2804 case SSSE3: 2805 case SSE3: 2806 case SSE2: 2807 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2808 break; 2809 case SSE1: 2810 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2811 break; 2812 default: 2813 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2814 } 2815 } 2816 2817 // Each case falls through to the previous one here. 2818 switch (MMX3DNowLevel) { 2819 case AMD3DNowAthlon: 2820 Builder.defineMacro("__3dNOW_A__"); 2821 case AMD3DNow: 2822 Builder.defineMacro("__3dNOW__"); 2823 case MMX: 2824 Builder.defineMacro("__MMX__"); 2825 case NoMMX3DNow: 2826 break; 2827 } 2828 2829 if (CPU >= CK_i486) { 2830 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2831 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2832 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2833 } 2834 if (CPU >= CK_i586) 2835 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2836 } 2837 2838 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2839 return llvm::StringSwitch<bool>(Feature) 2840 .Case("aes", HasAES) 2841 .Case("avx", SSELevel >= AVX) 2842 .Case("avx2", SSELevel >= AVX2) 2843 .Case("avx512f", SSELevel >= AVX512F) 2844 .Case("avx512cd", HasAVX512CD) 2845 .Case("avx512er", HasAVX512ER) 2846 .Case("avx512pf", HasAVX512PF) 2847 .Case("bmi", HasBMI) 2848 .Case("bmi2", HasBMI2) 2849 .Case("cx16", HasCX16) 2850 .Case("f16c", HasF16C) 2851 .Case("fma", HasFMA) 2852 .Case("fma4", XOPLevel >= FMA4) 2853 .Case("tbm", HasTBM) 2854 .Case("lzcnt", HasLZCNT) 2855 .Case("rdrnd", HasRDRND) 2856 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2857 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2858 .Case("mmx", MMX3DNowLevel >= MMX) 2859 .Case("pclmul", HasPCLMUL) 2860 .Case("popcnt", HasPOPCNT) 2861 .Case("rtm", HasRTM) 2862 .Case("prfchw", HasPRFCHW) 2863 .Case("rdseed", HasRDSEED) 2864 .Case("sha", HasSHA) 2865 .Case("sse", SSELevel >= SSE1) 2866 .Case("sse2", SSELevel >= SSE2) 2867 .Case("sse3", SSELevel >= SSE3) 2868 .Case("ssse3", SSELevel >= SSSE3) 2869 .Case("sse4.1", SSELevel >= SSE41) 2870 .Case("sse4.2", SSELevel >= SSE42) 2871 .Case("sse4a", XOPLevel >= SSE4A) 2872 .Case("x86", true) 2873 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2874 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2875 .Case("xop", XOPLevel >= XOP) 2876 .Default(false); 2877 } 2878 2879 bool 2880 X86TargetInfo::validateAsmConstraint(const char *&Name, 2881 TargetInfo::ConstraintInfo &Info) const { 2882 switch (*Name) { 2883 default: return false; 2884 case 'Y': // first letter of a pair: 2885 switch (*(Name+1)) { 2886 default: return false; 2887 case '0': // First SSE register. 2888 case 't': // Any SSE register, when SSE2 is enabled. 2889 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2890 case 'm': // any MMX register, when inter-unit moves enabled. 2891 break; // falls through to setAllowsRegister. 2892 } 2893 case 'a': // eax. 2894 case 'b': // ebx. 2895 case 'c': // ecx. 2896 case 'd': // edx. 2897 case 'S': // esi. 2898 case 'D': // edi. 2899 case 'A': // edx:eax. 2900 case 'f': // any x87 floating point stack register. 2901 case 't': // top of floating point stack. 2902 case 'u': // second from top of floating point stack. 2903 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2904 case 'y': // Any MMX register. 2905 case 'x': // Any SSE register. 2906 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2907 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2908 case 'l': // "Index" registers: any general register that can be used as an 2909 // index in a base+index memory access. 2910 Info.setAllowsRegister(); 2911 return true; 2912 case 'C': // SSE floating point constant. 2913 case 'G': // x87 floating point constant. 2914 case 'e': // 32-bit signed integer constant for use with zero-extending 2915 // x86_64 instructions. 2916 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2917 // x86_64 instructions. 2918 return true; 2919 } 2920 } 2921 2922 2923 std::string 2924 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2925 switch (*Constraint) { 2926 case 'a': return std::string("{ax}"); 2927 case 'b': return std::string("{bx}"); 2928 case 'c': return std::string("{cx}"); 2929 case 'd': return std::string("{dx}"); 2930 case 'S': return std::string("{si}"); 2931 case 'D': return std::string("{di}"); 2932 case 'p': // address 2933 return std::string("im"); 2934 case 't': // top of floating point stack. 2935 return std::string("{st}"); 2936 case 'u': // second from top of floating point stack. 2937 return std::string("{st(1)}"); // second from top of floating point stack. 2938 default: 2939 return std::string(1, *Constraint); 2940 } 2941 } 2942 } // end anonymous namespace 2943 2944 namespace { 2945 // X86-32 generic target 2946 class X86_32TargetInfo : public X86TargetInfo { 2947 public: 2948 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 2949 DoubleAlign = LongLongAlign = 32; 2950 LongDoubleWidth = 96; 2951 LongDoubleAlign = 32; 2952 SuitableAlign = 128; 2953 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2954 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2955 "a0:0:64-f80:32:32-n8:16:32-S128"; 2956 SizeType = UnsignedInt; 2957 PtrDiffType = SignedInt; 2958 IntPtrType = SignedInt; 2959 RegParmMax = 3; 2960 2961 // Use fpret for all types. 2962 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2963 (1 << TargetInfo::Double) | 2964 (1 << TargetInfo::LongDouble)); 2965 2966 // x86-32 has atomics up to 8 bytes 2967 // FIXME: Check that we actually have cmpxchg8b before setting 2968 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2969 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2970 } 2971 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2972 return TargetInfo::CharPtrBuiltinVaList; 2973 } 2974 2975 int getEHDataRegisterNumber(unsigned RegNo) const { 2976 if (RegNo == 0) return 0; 2977 if (RegNo == 1) return 2; 2978 return -1; 2979 } 2980 virtual bool validateInputSize(StringRef Constraint, 2981 unsigned Size) const { 2982 switch (Constraint[0]) { 2983 default: break; 2984 case 'a': 2985 case 'b': 2986 case 'c': 2987 case 'd': 2988 return Size <= 32; 2989 } 2990 2991 return true; 2992 } 2993 }; 2994 } // end anonymous namespace 2995 2996 namespace { 2997 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2998 public: 2999 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3000 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3001 3002 virtual unsigned getFloatEvalMethod() const { 3003 unsigned Major, Minor, Micro; 3004 getTriple().getOSVersion(Major, Minor, Micro); 3005 // New NetBSD uses the default rounding mode. 3006 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3007 return X86_32TargetInfo::getFloatEvalMethod(); 3008 // NetBSD before 6.99.26 defaults to "double" rounding. 3009 return 1; 3010 } 3011 }; 3012 } // end anonymous namespace 3013 3014 namespace { 3015 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3016 public: 3017 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3018 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3019 SizeType = UnsignedLong; 3020 IntPtrType = SignedLong; 3021 PtrDiffType = SignedLong; 3022 } 3023 }; 3024 } // end anonymous namespace 3025 3026 namespace { 3027 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3028 public: 3029 BitrigI386TargetInfo(const llvm::Triple &Triple) 3030 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3031 SizeType = UnsignedLong; 3032 IntPtrType = SignedLong; 3033 PtrDiffType = SignedLong; 3034 } 3035 }; 3036 } // end anonymous namespace 3037 3038 namespace { 3039 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3040 public: 3041 DarwinI386TargetInfo(const llvm::Triple &Triple) 3042 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3043 LongDoubleWidth = 128; 3044 LongDoubleAlign = 128; 3045 SuitableAlign = 128; 3046 MaxVectorAlign = 256; 3047 SizeType = UnsignedLong; 3048 IntPtrType = SignedLong; 3049 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3050 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 3051 "a0:0:64-f80:128:128-n8:16:32-S128"; 3052 HasAlignMac68kSupport = true; 3053 } 3054 3055 }; 3056 } // end anonymous namespace 3057 3058 namespace { 3059 // x86-32 Windows target 3060 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3061 public: 3062 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3063 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3064 TLSSupported = false; 3065 WCharType = UnsignedShort; 3066 DoubleAlign = LongLongAlign = 64; 3067 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3068 "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-" 3069 "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"; 3070 } 3071 virtual void getTargetDefines(const LangOptions &Opts, 3072 MacroBuilder &Builder) const { 3073 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3074 } 3075 }; 3076 } // end anonymous namespace 3077 3078 namespace { 3079 3080 // x86-32 Windows Visual Studio target 3081 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 3082 public: 3083 VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple) 3084 : WindowsX86_32TargetInfo(Triple) { 3085 LongDoubleWidth = LongDoubleAlign = 64; 3086 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3087 } 3088 virtual void getTargetDefines(const LangOptions &Opts, 3089 MacroBuilder &Builder) const { 3090 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3091 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3092 // The value of the following reflects processor type. 3093 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3094 // We lost the original triple, so we use the default. 3095 Builder.defineMacro("_M_IX86", "600"); 3096 } 3097 }; 3098 } // end anonymous namespace 3099 3100 namespace { 3101 // x86-32 MinGW target 3102 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3103 public: 3104 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3105 : WindowsX86_32TargetInfo(Triple) {} 3106 virtual void getTargetDefines(const LangOptions &Opts, 3107 MacroBuilder &Builder) const { 3108 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3109 DefineStd(Builder, "WIN32", Opts); 3110 DefineStd(Builder, "WINNT", Opts); 3111 Builder.defineMacro("_X86_"); 3112 Builder.defineMacro("__MSVCRT__"); 3113 Builder.defineMacro("__MINGW32__"); 3114 3115 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3116 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3117 if (Opts.MicrosoftExt) 3118 // Provide "as-is" __declspec. 3119 Builder.defineMacro("__declspec", "__declspec"); 3120 else 3121 // Provide alias of __attribute__ like mingw32-gcc. 3122 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3123 } 3124 }; 3125 } // end anonymous namespace 3126 3127 namespace { 3128 // x86-32 Cygwin target 3129 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3130 public: 3131 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3132 : X86_32TargetInfo(Triple) { 3133 TLSSupported = false; 3134 WCharType = UnsignedShort; 3135 DoubleAlign = LongLongAlign = 64; 3136 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3137 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 3138 "a0:0:64-f80:32:32-n8:16:32-S32"; 3139 } 3140 virtual void getTargetDefines(const LangOptions &Opts, 3141 MacroBuilder &Builder) const { 3142 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3143 Builder.defineMacro("_X86_"); 3144 Builder.defineMacro("__CYGWIN__"); 3145 Builder.defineMacro("__CYGWIN32__"); 3146 DefineStd(Builder, "unix", Opts); 3147 if (Opts.CPlusPlus) 3148 Builder.defineMacro("_GNU_SOURCE"); 3149 } 3150 }; 3151 } // end anonymous namespace 3152 3153 namespace { 3154 // x86-32 Haiku target 3155 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3156 public: 3157 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3158 SizeType = UnsignedLong; 3159 IntPtrType = SignedLong; 3160 PtrDiffType = SignedLong; 3161 ProcessIDType = SignedLong; 3162 this->UserLabelPrefix = ""; 3163 this->TLSSupported = false; 3164 } 3165 virtual void getTargetDefines(const LangOptions &Opts, 3166 MacroBuilder &Builder) const { 3167 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3168 Builder.defineMacro("__INTEL__"); 3169 Builder.defineMacro("__HAIKU__"); 3170 } 3171 }; 3172 } // end anonymous namespace 3173 3174 // RTEMS Target 3175 template<typename Target> 3176 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3177 protected: 3178 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3179 MacroBuilder &Builder) const { 3180 // RTEMS defines; list based off of gcc output 3181 3182 Builder.defineMacro("__rtems__"); 3183 Builder.defineMacro("__ELF__"); 3184 } 3185 3186 public: 3187 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3188 this->UserLabelPrefix = ""; 3189 3190 switch (Triple.getArch()) { 3191 default: 3192 case llvm::Triple::x86: 3193 // this->MCountName = ".mcount"; 3194 break; 3195 case llvm::Triple::mips: 3196 case llvm::Triple::mipsel: 3197 case llvm::Triple::ppc: 3198 case llvm::Triple::ppc64: 3199 case llvm::Triple::ppc64le: 3200 // this->MCountName = "_mcount"; 3201 break; 3202 case llvm::Triple::arm: 3203 // this->MCountName = "__mcount"; 3204 break; 3205 } 3206 } 3207 }; 3208 3209 namespace { 3210 // x86-32 RTEMS target 3211 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3212 public: 3213 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3214 SizeType = UnsignedLong; 3215 IntPtrType = SignedLong; 3216 PtrDiffType = SignedLong; 3217 this->UserLabelPrefix = ""; 3218 } 3219 virtual void getTargetDefines(const LangOptions &Opts, 3220 MacroBuilder &Builder) const { 3221 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3222 Builder.defineMacro("__INTEL__"); 3223 Builder.defineMacro("__rtems__"); 3224 } 3225 }; 3226 } // end anonymous namespace 3227 3228 namespace { 3229 // x86-64 generic target 3230 class X86_64TargetInfo : public X86TargetInfo { 3231 public: 3232 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3233 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 3234 LongDoubleWidth = 128; 3235 LongDoubleAlign = 128; 3236 LargeArrayMinWidth = 128; 3237 LargeArrayAlign = 128; 3238 SuitableAlign = 128; 3239 IntMaxType = SignedLong; 3240 UIntMaxType = UnsignedLong; 3241 Int64Type = SignedLong; 3242 RegParmMax = 6; 3243 3244 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3245 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 3246 "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"; 3247 3248 // Use fpret only for long double. 3249 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3250 3251 // Use fp2ret for _Complex long double. 3252 ComplexLongDoubleUsesFP2Ret = true; 3253 3254 // x86-64 has atomics up to 16 bytes. 3255 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 3256 // on CPUs with cmpxchg16b 3257 MaxAtomicPromoteWidth = 128; 3258 MaxAtomicInlineWidth = 64; 3259 } 3260 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3261 return TargetInfo::X86_64ABIBuiltinVaList; 3262 } 3263 3264 int getEHDataRegisterNumber(unsigned RegNo) const { 3265 if (RegNo == 0) return 0; 3266 if (RegNo == 1) return 1; 3267 return -1; 3268 } 3269 3270 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3271 return (CC == CC_C || 3272 CC == CC_IntelOclBicc || 3273 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3274 } 3275 3276 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 3277 return CC_C; 3278 } 3279 3280 }; 3281 } // end anonymous namespace 3282 3283 namespace { 3284 // x86-64 Windows target 3285 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3286 public: 3287 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3288 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3289 TLSSupported = false; 3290 WCharType = UnsignedShort; 3291 LongWidth = LongAlign = 32; 3292 DoubleAlign = LongLongAlign = 64; 3293 IntMaxType = SignedLongLong; 3294 UIntMaxType = UnsignedLongLong; 3295 Int64Type = SignedLongLong; 3296 SizeType = UnsignedLongLong; 3297 PtrDiffType = SignedLongLong; 3298 IntPtrType = SignedLongLong; 3299 this->UserLabelPrefix = ""; 3300 } 3301 virtual void getTargetDefines(const LangOptions &Opts, 3302 MacroBuilder &Builder) const { 3303 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3304 Builder.defineMacro("_WIN64"); 3305 } 3306 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3307 return TargetInfo::CharPtrBuiltinVaList; 3308 } 3309 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3310 return (CC == CC_C || 3311 CC == CC_IntelOclBicc || 3312 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3313 } 3314 }; 3315 } // end anonymous namespace 3316 3317 namespace { 3318 // x86-64 Windows Visual Studio target 3319 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 3320 public: 3321 VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple) 3322 : WindowsX86_64TargetInfo(Triple) { 3323 LongDoubleWidth = LongDoubleAlign = 64; 3324 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3325 } 3326 virtual void getTargetDefines(const LangOptions &Opts, 3327 MacroBuilder &Builder) const { 3328 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3329 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3330 Builder.defineMacro("_M_X64"); 3331 Builder.defineMacro("_M_AMD64"); 3332 } 3333 }; 3334 } // end anonymous namespace 3335 3336 namespace { 3337 // x86-64 MinGW target 3338 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3339 public: 3340 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3341 : WindowsX86_64TargetInfo(Triple) {} 3342 virtual void getTargetDefines(const LangOptions &Opts, 3343 MacroBuilder &Builder) const { 3344 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3345 DefineStd(Builder, "WIN64", Opts); 3346 Builder.defineMacro("__MSVCRT__"); 3347 Builder.defineMacro("__MINGW32__"); 3348 Builder.defineMacro("__MINGW64__"); 3349 3350 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3351 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3352 if (Opts.MicrosoftExt) 3353 // Provide "as-is" __declspec. 3354 Builder.defineMacro("__declspec", "__declspec"); 3355 else 3356 // Provide alias of __attribute__ like mingw32-gcc. 3357 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3358 } 3359 }; 3360 } // end anonymous namespace 3361 3362 namespace { 3363 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3364 public: 3365 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3366 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3367 Int64Type = SignedLongLong; 3368 MaxVectorAlign = 256; 3369 } 3370 }; 3371 } // end anonymous namespace 3372 3373 namespace { 3374 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3375 public: 3376 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3377 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3378 IntMaxType = SignedLongLong; 3379 UIntMaxType = UnsignedLongLong; 3380 Int64Type = SignedLongLong; 3381 } 3382 }; 3383 } // end anonymous namespace 3384 3385 namespace { 3386 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3387 public: 3388 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3389 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3390 IntMaxType = SignedLongLong; 3391 UIntMaxType = UnsignedLongLong; 3392 Int64Type = SignedLongLong; 3393 } 3394 }; 3395 } 3396 3397 namespace { 3398 class AArch64TargetInfo : public TargetInfo { 3399 static const char * const GCCRegNames[]; 3400 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3401 3402 enum FPUModeEnum { 3403 FPUMode, 3404 NeonMode 3405 }; 3406 3407 unsigned FPU; 3408 unsigned Crypto; 3409 static const Builtin::Info BuiltinInfo[]; 3410 3411 public: 3412 AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 3413 BigEndian = false; 3414 LongWidth = LongAlign = 64; 3415 LongDoubleWidth = LongDoubleAlign = 128; 3416 PointerWidth = PointerAlign = 64; 3417 SuitableAlign = 128; 3418 DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3419 "i64:64:64-i128:128:128-f32:32:32-f64:64:64-" 3420 "f128:128:128-n32:64-S128"; 3421 3422 WCharType = UnsignedInt; 3423 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3424 3425 // AArch64 backend supports 64-bit operations at the moment. In principle 3426 // 128-bit is possible if register-pairs are used. 3427 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3428 3429 TheCXXABI.set(TargetCXXABI::GenericAArch64); 3430 } 3431 virtual void getTargetDefines(const LangOptions &Opts, 3432 MacroBuilder &Builder) const { 3433 // GCC defines theses currently 3434 Builder.defineMacro("__aarch64__"); 3435 Builder.defineMacro("__AARCH64EL__"); 3436 3437 // ACLE predefines. Many can only have one possible value on v8 AArch64. 3438 Builder.defineMacro("__ARM_ACLE", "200"); 3439 Builder.defineMacro("__ARM_ARCH", "8"); 3440 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 3441 3442 Builder.defineMacro("__ARM_64BIT_STATE"); 3443 Builder.defineMacro("__ARM_PCS_AAPCS64"); 3444 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 3445 3446 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 3447 Builder.defineMacro("__ARM_FEATURE_CLZ"); 3448 Builder.defineMacro("__ARM_FEATURE_FMA"); 3449 Builder.defineMacro("__ARM_FEATURE_DIV"); 3450 3451 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 3452 3453 // 0xe implies support for half, single and double precision operations. 3454 Builder.defineMacro("__ARM_FP", "0xe"); 3455 3456 // PCS specifies this for SysV variants, which is all we support. Other ABIs 3457 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 3458 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 3459 3460 if (Opts.FastMath || Opts.FiniteMathOnly) 3461 Builder.defineMacro("__ARM_FP_FAST"); 3462 3463 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 3464 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 3465 3466 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3467 Opts.ShortWChar ? "2" : "4"); 3468 3469 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3470 Opts.ShortEnums ? "1" : "4"); 3471 3472 if (BigEndian) 3473 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 3474 3475 if (FPU == NeonMode) { 3476 Builder.defineMacro("__ARM_NEON"); 3477 // 64-bit NEON supports half, single and double precision operations. 3478 Builder.defineMacro("__ARM_NEON_FP", "7"); 3479 } 3480 3481 if (Crypto) { 3482 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 3483 } 3484 } 3485 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3486 unsigned &NumRecords) const { 3487 Records = BuiltinInfo; 3488 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin; 3489 } 3490 virtual bool hasFeature(StringRef Feature) const { 3491 return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode); 3492 } 3493 3494 virtual bool setCPU(const std::string &Name) { 3495 return llvm::StringSwitch<bool>(Name) 3496 .Case("generic", true) 3497 .Cases("cortex-a53", "cortex-a57", true) 3498 .Default(false); 3499 } 3500 3501 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 3502 DiagnosticsEngine &Diags) { 3503 FPU = FPUMode; 3504 Crypto = 0; 3505 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3506 if (Features[i] == "+neon") 3507 FPU = NeonMode; 3508 if (Features[i] == "+crypto") 3509 Crypto = 1; 3510 } 3511 return true; 3512 } 3513 3514 virtual void getGCCRegNames(const char *const *&Names, 3515 unsigned &NumNames) const; 3516 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3517 unsigned &NumAliases) const; 3518 3519 virtual bool isCLZForZeroUndef() const { return false; } 3520 3521 virtual bool validateAsmConstraint(const char *&Name, 3522 TargetInfo::ConstraintInfo &Info) const { 3523 switch (*Name) { 3524 default: return false; 3525 case 'w': // An FP/SIMD vector register 3526 Info.setAllowsRegister(); 3527 return true; 3528 case 'I': // Constant that can be used with an ADD instruction 3529 case 'J': // Constant that can be used with a SUB instruction 3530 case 'K': // Constant that can be used with a 32-bit logical instruction 3531 case 'L': // Constant that can be used with a 64-bit logical instruction 3532 case 'M': // Constant that can be used as a 32-bit MOV immediate 3533 case 'N': // Constant that can be used as a 64-bit MOV immediate 3534 case 'Y': // Floating point constant zero 3535 case 'Z': // Integer constant zero 3536 return true; 3537 case 'Q': // A memory reference with base register and no offset 3538 Info.setAllowsMemory(); 3539 return true; 3540 case 'S': // A symbolic address 3541 Info.setAllowsRegister(); 3542 return true; 3543 case 'U': 3544 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 3545 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 3546 // Usa: An absolute symbolic address 3547 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 3548 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 3549 } 3550 } 3551 3552 virtual const char *getClobbers() const { 3553 // There are no AArch64 clobbers shared by all asm statements. 3554 return ""; 3555 } 3556 3557 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3558 return TargetInfo::AArch64ABIBuiltinVaList; 3559 } 3560 }; 3561 3562 const char * const AArch64TargetInfo::GCCRegNames[] = { 3563 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", 3564 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", 3565 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", 3566 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr", 3567 3568 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 3569 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 3570 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 3571 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr", 3572 3573 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", 3574 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", 3575 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", 3576 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31", 3577 3578 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", 3579 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", 3580 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", 3581 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", 3582 3583 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3584 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3585 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3586 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3587 3588 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3589 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3590 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3591 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3592 3593 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3594 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", 3595 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", 3596 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" 3597 }; 3598 3599 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names, 3600 unsigned &NumNames) const { 3601 Names = GCCRegNames; 3602 NumNames = llvm::array_lengthof(GCCRegNames); 3603 } 3604 3605 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 3606 { { "x16" }, "ip0"}, 3607 { { "x17" }, "ip1"}, 3608 { { "x29" }, "fp" }, 3609 { { "x30" }, "lr" } 3610 }; 3611 3612 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3613 unsigned &NumAliases) const { 3614 Aliases = GCCRegAliases; 3615 NumAliases = llvm::array_lengthof(GCCRegAliases); 3616 3617 } 3618 3619 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 3620 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3621 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3622 ALL_LANGUAGES }, 3623 #include "clang/Basic/BuiltinsAArch64.def" 3624 }; 3625 3626 } // end anonymous namespace 3627 3628 namespace { 3629 class ARMTargetInfo : public TargetInfo { 3630 // Possible FPU choices. 3631 enum FPUMode { 3632 VFP2FPU = (1 << 0), 3633 VFP3FPU = (1 << 1), 3634 VFP4FPU = (1 << 2), 3635 NeonFPU = (1 << 3), 3636 FPARMV8 = (1 << 4) 3637 }; 3638 3639 // Possible HWDiv features. 3640 enum HWDivMode { 3641 HWDivThumb = (1 << 0), 3642 HWDivARM = (1 << 1) 3643 }; 3644 3645 static bool FPUModeIsVFP(FPUMode Mode) { 3646 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3647 } 3648 3649 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3650 static const char * const GCCRegNames[]; 3651 3652 std::string ABI, CPU; 3653 3654 enum { 3655 FP_Default, 3656 FP_VFP, 3657 FP_Neon 3658 } FPMath; 3659 3660 unsigned FPU : 5; 3661 3662 unsigned IsAAPCS : 1; 3663 unsigned IsThumb : 1; 3664 unsigned HWDiv : 2; 3665 3666 // Initialized via features. 3667 unsigned SoftFloat : 1; 3668 unsigned SoftFloatABI : 1; 3669 3670 unsigned CRC : 1; 3671 3672 static const Builtin::Info BuiltinInfo[]; 3673 3674 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3675 // On linux, binaries targeting old cpus call functions in libgcc to 3676 // perform atomic operations. The implementation in libgcc then calls into 3677 // the kernel which on armv6 and newer uses ldrex and strex. The net result 3678 // is that if we assume the kernel is at least as recent as the hardware, 3679 // it is safe to use atomic instructions on armv6 and newer. 3680 if (!T.isOSLinux() && 3681 T.getOS() != llvm::Triple::FreeBSD && 3682 T.getOS() != llvm::Triple::NetBSD && 3683 T.getOS() != llvm::Triple::Bitrig) 3684 return false; 3685 StringRef ArchName = T.getArchName(); 3686 if (T.getArch() == llvm::Triple::arm) { 3687 if (!ArchName.startswith("armv")) 3688 return false; 3689 StringRef VersionStr = ArchName.substr(4); 3690 unsigned Version; 3691 if (VersionStr.getAsInteger(10, Version)) 3692 return false; 3693 return Version >= 6; 3694 } 3695 assert(T.getArch() == llvm::Triple::thumb); 3696 if (!ArchName.startswith("thumbv")) 3697 return false; 3698 StringRef VersionStr = ArchName.substr(6); 3699 unsigned Version; 3700 if (VersionStr.getAsInteger(10, Version)) 3701 return false; 3702 return Version >= 7; 3703 } 3704 3705 public: 3706 ARMTargetInfo(const llvm::Triple &Triple) 3707 : TargetInfo(Triple), ABI("aapcs-linux"), CPU("arm1136j-s"), 3708 FPMath(FP_Default), IsAAPCS(true) { 3709 BigEndian = false; 3710 switch (getTriple().getOS()) { 3711 case llvm::Triple::NetBSD: 3712 SizeType = UnsignedLong; 3713 PtrDiffType = SignedLong; 3714 WCharType = SignedInt; 3715 break; 3716 default: 3717 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3718 WCharType = UnsignedInt; 3719 SizeType = UnsignedInt; 3720 PtrDiffType = SignedInt; 3721 break; 3722 } 3723 3724 // {} in inline assembly are neon specifiers, not assembly variant 3725 // specifiers. 3726 NoAsmVariants = true; 3727 3728 // FIXME: Should we just treat this as a feature? 3729 IsThumb = getTriple().getArchName().startswith("thumb"); 3730 if (IsThumb) { 3731 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3732 // so set preferred for small types to 32. 3733 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3734 "i64:64:64-f32:32:32-f64:64:64-" 3735 "v64:64:64-v128:64:128-a0:0:32-n32-S64"); 3736 } else { 3737 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3738 "i64:64:64-f32:32:32-f64:64:64-" 3739 "v64:64:64-v128:64:128-a0:0:64-n32-S64"); 3740 } 3741 3742 // ARM targets default to using the ARM C++ ABI. 3743 TheCXXABI.set(TargetCXXABI::GenericARM); 3744 3745 // ARM has atomics up to 8 bytes 3746 MaxAtomicPromoteWidth = 64; 3747 if (shouldUseInlineAtomic(getTriple())) 3748 MaxAtomicInlineWidth = 64; 3749 3750 // Do force alignment of members that follow zero length bitfields. If 3751 // the alignment of the zero-length bitfield is greater than the member 3752 // that follows it, `bar', `bar' will be aligned as the type of the 3753 // zero length bitfield. 3754 UseZeroLengthBitfieldAlignment = true; 3755 } 3756 virtual const char *getABI() const { return ABI.c_str(); } 3757 virtual bool setABI(const std::string &Name) { 3758 ABI = Name; 3759 3760 // The defaults (above) are for AAPCS, check if we need to change them. 3761 // 3762 // FIXME: We need support for -meabi... we could just mangle it into the 3763 // name. 3764 if (Name == "apcs-gnu") { 3765 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3766 // size_t is unsigned int on FreeBSD. 3767 if (getTriple().getOS() != llvm::Triple::FreeBSD) 3768 SizeType = UnsignedLong; 3769 3770 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3771 WCharType = SignedInt; 3772 3773 // Do not respect the alignment of bit-field types when laying out 3774 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3775 UseBitFieldTypeAlignment = false; 3776 3777 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3778 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3779 /// gcc. 3780 ZeroLengthBitfieldBoundary = 32; 3781 3782 IsAAPCS = false; 3783 3784 if (IsThumb) { 3785 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3786 // so set preferred for small types to 32. 3787 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3788 "i64:32:64-f32:32:32-f64:32:64-" 3789 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3790 } else { 3791 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3792 "i64:32:64-f32:32:32-f64:32:64-" 3793 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3794 } 3795 3796 // FIXME: Override "preferred align" for double and long long. 3797 } else if (Name == "aapcs" || Name == "aapcs-vfp") { 3798 // size_t is unsigned long on Darwin. 3799 if (getTriple().isOSDarwin()) 3800 SizeType = UnsignedLong; 3801 IsAAPCS = true; 3802 // FIXME: Enumerated types are variable width in straight AAPCS. 3803 } else if (Name == "aapcs-linux") { 3804 IsAAPCS = true; 3805 } else 3806 return false; 3807 3808 return true; 3809 } 3810 3811 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3812 StringRef ArchName = getTriple().getArchName(); 3813 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3814 Features["vfp2"] = true; 3815 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3816 CPU == "cortex-a9-mp") { 3817 Features["vfp3"] = true; 3818 Features["neon"] = true; 3819 } 3820 else if (CPU == "cortex-a5") { 3821 Features["vfp4"] = true; 3822 Features["neon"] = true; 3823 } else if (CPU == "swift" || CPU == "cortex-a7" || CPU == "cortex-a12" || CPU == "cortex-a15") { 3824 Features["vfp4"] = true; 3825 Features["neon"] = true; 3826 Features["hwdiv"] = true; 3827 Features["hwdiv-arm"] = true; 3828 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 3829 Features["fp-armv8"] = true; 3830 Features["neon"] = true; 3831 Features["hwdiv"] = true; 3832 Features["hwdiv-arm"] = true; 3833 Features["crc"] = true; 3834 } else if (CPU == "cortex-r5" || CPU == "cortex-m3" || 3835 CPU == "cortex-m4" || 3836 // Enable the hwdiv extension for all v8a AArch32 cores by 3837 // default. 3838 ArchName == "armv8a" || ArchName == "armv8" || 3839 ArchName == "thumbv8a" || ArchName == "thumbv8") { 3840 Features["hwdiv"] = true; 3841 Features["hwdiv-arm"] = true; 3842 } 3843 } 3844 3845 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 3846 DiagnosticsEngine &Diags) { 3847 FPU = 0; 3848 CRC = 0; 3849 SoftFloat = SoftFloatABI = false; 3850 HWDiv = 0; 3851 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3852 if (Features[i] == "+soft-float") 3853 SoftFloat = true; 3854 else if (Features[i] == "+soft-float-abi") 3855 SoftFloatABI = true; 3856 else if (Features[i] == "+vfp2") 3857 FPU |= VFP2FPU; 3858 else if (Features[i] == "+vfp3") 3859 FPU |= VFP3FPU; 3860 else if (Features[i] == "+vfp4") 3861 FPU |= VFP4FPU; 3862 else if (Features[i] == "+fp-armv8") 3863 FPU |= FPARMV8; 3864 else if (Features[i] == "+neon") 3865 FPU |= NeonFPU; 3866 else if (Features[i] == "+hwdiv") 3867 HWDiv |= HWDivThumb; 3868 else if (Features[i] == "+hwdiv-arm") 3869 HWDiv |= HWDivARM; 3870 else if (Features[i] == "+crc") 3871 CRC = 1; 3872 } 3873 3874 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 3875 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 3876 return false; 3877 } 3878 3879 if (FPMath == FP_Neon) 3880 Features.push_back("+neonfp"); 3881 else if (FPMath == FP_VFP) 3882 Features.push_back("-neonfp"); 3883 3884 // Remove front-end specific options which the backend handles differently. 3885 std::vector<std::string>::iterator it; 3886 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3887 if (it != Features.end()) 3888 Features.erase(it); 3889 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3890 if (it != Features.end()) 3891 Features.erase(it); 3892 return true; 3893 } 3894 3895 virtual bool hasFeature(StringRef Feature) const { 3896 return llvm::StringSwitch<bool>(Feature) 3897 .Case("arm", true) 3898 .Case("softfloat", SoftFloat) 3899 .Case("thumb", IsThumb) 3900 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 3901 .Case("hwdiv", HWDiv & HWDivThumb) 3902 .Case("hwdiv-arm", HWDiv & HWDivARM) 3903 .Default(false); 3904 } 3905 // FIXME: Should we actually have some table instead of these switches? 3906 static const char *getCPUDefineSuffix(StringRef Name) { 3907 return llvm::StringSwitch<const char*>(Name) 3908 .Cases("arm8", "arm810", "4") 3909 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3910 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3911 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3912 .Case("ep9312", "4T") 3913 .Cases("arm10tdmi", "arm1020t", "5T") 3914 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3915 .Case("arm926ej-s", "5TEJ") 3916 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3917 .Cases("xscale", "iwmmxt", "5TE") 3918 .Case("arm1136j-s", "6J") 3919 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3920 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3921 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3922 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A") 3923 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "7A") 3924 .Cases("cortex-r4", "cortex-r5", "7R") 3925 .Case("cortex-a9-mp", "7F") 3926 .Case("swift", "7S") 3927 .Cases("cortex-m3", "cortex-m4", "7M") 3928 .Case("cortex-m0", "6M") 3929 .Cases("cortex-a53", "cortex-a57", "8A") 3930 .Default(0); 3931 } 3932 static const char *getCPUProfile(StringRef Name) { 3933 return llvm::StringSwitch<const char*>(Name) 3934 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 3935 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "A") 3936 .Cases("cortex-a53", "cortex-a57", "A") 3937 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 3938 .Cases("cortex-r4", "cortex-r5", "R") 3939 .Default(""); 3940 } 3941 virtual bool setCPU(const std::string &Name) { 3942 if (!getCPUDefineSuffix(Name)) 3943 return false; 3944 3945 CPU = Name; 3946 return true; 3947 } 3948 virtual bool setFPMath(StringRef Name); 3949 virtual void getTargetDefines(const LangOptions &Opts, 3950 MacroBuilder &Builder) const { 3951 // Target identification. 3952 Builder.defineMacro("__arm"); 3953 Builder.defineMacro("__arm__"); 3954 3955 // Target properties. 3956 Builder.defineMacro("__ARMEL__"); 3957 Builder.defineMacro("__LITTLE_ENDIAN__"); 3958 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3959 3960 StringRef CPUArch = getCPUDefineSuffix(CPU); 3961 unsigned int CPUArchVer; 3962 if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) { 3963 llvm_unreachable("Invalid char for architecture version number"); 3964 } 3965 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 3966 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 3967 StringRef CPUProfile = getCPUProfile(CPU); 3968 if (!CPUProfile.empty()) 3969 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 3970 3971 // Subtarget options. 3972 3973 // FIXME: It's more complicated than this and we don't really support 3974 // interworking. 3975 if (5 <= CPUArchVer && CPUArchVer <= 7) 3976 Builder.defineMacro("__THUMB_INTERWORK__"); 3977 3978 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 3979 // Embedded targets on Darwin follow AAPCS, but not EABI. 3980 if (!getTriple().isOSDarwin()) 3981 Builder.defineMacro("__ARM_EABI__"); 3982 Builder.defineMacro("__ARM_PCS", "1"); 3983 3984 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 3985 Builder.defineMacro("__ARM_PCS_VFP", "1"); 3986 } 3987 3988 if (SoftFloat) 3989 Builder.defineMacro("__SOFTFP__"); 3990 3991 if (CPU == "xscale") 3992 Builder.defineMacro("__XSCALE__"); 3993 3994 if (IsThumb) { 3995 Builder.defineMacro("__THUMBEL__"); 3996 Builder.defineMacro("__thumb__"); 3997 if (CPUArch == "6T2" || CPUArchVer == 7) 3998 Builder.defineMacro("__thumb2__"); 3999 } 4000 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4001 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4002 4003 // Note, this is always on in gcc, even though it doesn't make sense. 4004 Builder.defineMacro("__APCS_32__"); 4005 4006 if (FPUModeIsVFP((FPUMode) FPU)) { 4007 Builder.defineMacro("__VFP_FP__"); 4008 if (FPU & VFP2FPU) 4009 Builder.defineMacro("__ARM_VFPV2__"); 4010 if (FPU & VFP3FPU) 4011 Builder.defineMacro("__ARM_VFPV3__"); 4012 if (FPU & VFP4FPU) 4013 Builder.defineMacro("__ARM_VFPV4__"); 4014 } 4015 4016 // This only gets set when Neon instructions are actually available, unlike 4017 // the VFP define, hence the soft float and arch check. This is subtly 4018 // different from gcc, we follow the intent which was that it should be set 4019 // when Neon instructions are actually available. 4020 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4021 Builder.defineMacro("__ARM_NEON"); 4022 Builder.defineMacro("__ARM_NEON__"); 4023 } 4024 4025 if (CRC) 4026 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4027 4028 if (CPUArchVer >= 6 && CPUArch != "6M") { 4029 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4030 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4031 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4032 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4033 } 4034 } 4035 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4036 unsigned &NumRecords) const { 4037 Records = BuiltinInfo; 4038 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4039 } 4040 virtual bool isCLZForZeroUndef() const { return false; } 4041 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4042 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4043 } 4044 virtual void getGCCRegNames(const char * const *&Names, 4045 unsigned &NumNames) const; 4046 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4047 unsigned &NumAliases) const; 4048 virtual bool validateAsmConstraint(const char *&Name, 4049 TargetInfo::ConstraintInfo &Info) const { 4050 switch (*Name) { 4051 default: break; 4052 case 'l': // r0-r7 4053 case 'h': // r8-r15 4054 case 'w': // VFP Floating point register single precision 4055 case 'P': // VFP Floating point register double precision 4056 Info.setAllowsRegister(); 4057 return true; 4058 case 'Q': // A memory address that is a single base register. 4059 Info.setAllowsMemory(); 4060 return true; 4061 case 'U': // a memory reference... 4062 switch (Name[1]) { 4063 case 'q': // ...ARMV4 ldrsb 4064 case 'v': // ...VFP load/store (reg+constant offset) 4065 case 'y': // ...iWMMXt load/store 4066 case 't': // address valid for load/store opaque types wider 4067 // than 128-bits 4068 case 'n': // valid address for Neon doubleword vector load/store 4069 case 'm': // valid address for Neon element and structure load/store 4070 case 's': // valid address for non-offset loads/stores of quad-word 4071 // values in four ARM registers 4072 Info.setAllowsMemory(); 4073 Name++; 4074 return true; 4075 } 4076 } 4077 return false; 4078 } 4079 virtual std::string convertConstraint(const char *&Constraint) const { 4080 std::string R; 4081 switch (*Constraint) { 4082 case 'U': // Two-character constraint; add "^" hint for later parsing. 4083 R = std::string("^") + std::string(Constraint, 2); 4084 Constraint++; 4085 break; 4086 case 'p': // 'p' should be translated to 'r' by default. 4087 R = std::string("r"); 4088 break; 4089 default: 4090 return std::string(1, *Constraint); 4091 } 4092 return R; 4093 } 4094 virtual bool validateConstraintModifier(StringRef Constraint, 4095 const char Modifier, 4096 unsigned Size) const { 4097 bool isOutput = (Constraint[0] == '='); 4098 bool isInOut = (Constraint[0] == '+'); 4099 4100 // Strip off constraint modifiers. 4101 while (Constraint[0] == '=' || 4102 Constraint[0] == '+' || 4103 Constraint[0] == '&') 4104 Constraint = Constraint.substr(1); 4105 4106 switch (Constraint[0]) { 4107 default: break; 4108 case 'r': { 4109 switch (Modifier) { 4110 default: 4111 return (isInOut || isOutput || Size <= 32); 4112 case 'q': 4113 // A register of size 32 cannot fit a vector type. 4114 return false; 4115 } 4116 } 4117 } 4118 4119 return true; 4120 } 4121 virtual const char *getClobbers() const { 4122 // FIXME: Is this really right? 4123 return ""; 4124 } 4125 4126 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 4127 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4128 } 4129 4130 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 4131 if (RegNo == 0) return 0; 4132 if (RegNo == 1) return 1; 4133 return -1; 4134 } 4135 }; 4136 4137 bool ARMTargetInfo::setFPMath(StringRef Name) { 4138 if (Name == "neon") { 4139 FPMath = FP_Neon; 4140 return true; 4141 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4142 Name == "vfp4") { 4143 FPMath = FP_VFP; 4144 return true; 4145 } 4146 return false; 4147 } 4148 4149 const char * const ARMTargetInfo::GCCRegNames[] = { 4150 // Integer registers 4151 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4152 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4153 4154 // Float registers 4155 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4156 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4157 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4158 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4159 4160 // Double registers 4161 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4162 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4163 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4164 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4165 4166 // Quad registers 4167 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4168 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4169 }; 4170 4171 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4172 unsigned &NumNames) const { 4173 Names = GCCRegNames; 4174 NumNames = llvm::array_lengthof(GCCRegNames); 4175 } 4176 4177 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4178 { { "a1" }, "r0" }, 4179 { { "a2" }, "r1" }, 4180 { { "a3" }, "r2" }, 4181 { { "a4" }, "r3" }, 4182 { { "v1" }, "r4" }, 4183 { { "v2" }, "r5" }, 4184 { { "v3" }, "r6" }, 4185 { { "v4" }, "r7" }, 4186 { { "v5" }, "r8" }, 4187 { { "v6", "rfp" }, "r9" }, 4188 { { "sl" }, "r10" }, 4189 { { "fp" }, "r11" }, 4190 { { "ip" }, "r12" }, 4191 { { "r13" }, "sp" }, 4192 { { "r14" }, "lr" }, 4193 { { "r15" }, "pc" }, 4194 // The S, D and Q registers overlap, but aren't really aliases; we 4195 // don't want to substitute one of these for a different-sized one. 4196 }; 4197 4198 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4199 unsigned &NumAliases) const { 4200 Aliases = GCCRegAliases; 4201 NumAliases = llvm::array_lengthof(GCCRegAliases); 4202 } 4203 4204 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4205 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4206 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4207 ALL_LANGUAGES }, 4208 #include "clang/Basic/BuiltinsARM.def" 4209 }; 4210 } // end anonymous namespace. 4211 4212 namespace { 4213 class DarwinARMTargetInfo : 4214 public DarwinTargetInfo<ARMTargetInfo> { 4215 protected: 4216 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4217 MacroBuilder &Builder) const { 4218 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4219 } 4220 4221 public: 4222 DarwinARMTargetInfo(const llvm::Triple &Triple) 4223 : DarwinTargetInfo<ARMTargetInfo>(Triple) { 4224 HasAlignMac68kSupport = true; 4225 // iOS always has 64-bit atomic instructions. 4226 // FIXME: This should be based off of the target features in ARMTargetInfo. 4227 MaxAtomicInlineWidth = 64; 4228 4229 // Darwin on iOS uses a variant of the ARM C++ ABI. 4230 TheCXXABI.set(TargetCXXABI::iOS); 4231 } 4232 }; 4233 } // end anonymous namespace. 4234 4235 4236 namespace { 4237 // Hexagon abstract base class 4238 class HexagonTargetInfo : public TargetInfo { 4239 static const Builtin::Info BuiltinInfo[]; 4240 static const char * const GCCRegNames[]; 4241 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4242 std::string CPU; 4243 public: 4244 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4245 BigEndian = false; 4246 DescriptionString = ("e-p:32:32:32-" 4247 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-" 4248 "f64:64:64-f32:32:32-a0:0-n32"); 4249 4250 // {} in inline assembly are packet specifiers, not assembly variant 4251 // specifiers. 4252 NoAsmVariants = true; 4253 } 4254 4255 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4256 unsigned &NumRecords) const { 4257 Records = BuiltinInfo; 4258 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4259 } 4260 4261 virtual bool validateAsmConstraint(const char *&Name, 4262 TargetInfo::ConstraintInfo &Info) const { 4263 return true; 4264 } 4265 4266 virtual void getTargetDefines(const LangOptions &Opts, 4267 MacroBuilder &Builder) const; 4268 4269 virtual bool hasFeature(StringRef Feature) const { 4270 return Feature == "hexagon"; 4271 } 4272 4273 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4274 return TargetInfo::CharPtrBuiltinVaList; 4275 } 4276 virtual void getGCCRegNames(const char * const *&Names, 4277 unsigned &NumNames) const; 4278 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4279 unsigned &NumAliases) const; 4280 virtual const char *getClobbers() const { 4281 return ""; 4282 } 4283 4284 static const char *getHexagonCPUSuffix(StringRef Name) { 4285 return llvm::StringSwitch<const char*>(Name) 4286 .Case("hexagonv4", "4") 4287 .Case("hexagonv5", "5") 4288 .Default(0); 4289 } 4290 4291 virtual bool setCPU(const std::string &Name) { 4292 if (!getHexagonCPUSuffix(Name)) 4293 return false; 4294 4295 CPU = Name; 4296 return true; 4297 } 4298 }; 4299 4300 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4301 MacroBuilder &Builder) const { 4302 Builder.defineMacro("qdsp6"); 4303 Builder.defineMacro("__qdsp6", "1"); 4304 Builder.defineMacro("__qdsp6__", "1"); 4305 4306 Builder.defineMacro("hexagon"); 4307 Builder.defineMacro("__hexagon", "1"); 4308 Builder.defineMacro("__hexagon__", "1"); 4309 4310 if(CPU == "hexagonv1") { 4311 Builder.defineMacro("__HEXAGON_V1__"); 4312 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4313 if(Opts.HexagonQdsp6Compat) { 4314 Builder.defineMacro("__QDSP6_V1__"); 4315 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4316 } 4317 } 4318 else if(CPU == "hexagonv2") { 4319 Builder.defineMacro("__HEXAGON_V2__"); 4320 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4321 if(Opts.HexagonQdsp6Compat) { 4322 Builder.defineMacro("__QDSP6_V2__"); 4323 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4324 } 4325 } 4326 else if(CPU == "hexagonv3") { 4327 Builder.defineMacro("__HEXAGON_V3__"); 4328 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4329 if(Opts.HexagonQdsp6Compat) { 4330 Builder.defineMacro("__QDSP6_V3__"); 4331 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4332 } 4333 } 4334 else if(CPU == "hexagonv4") { 4335 Builder.defineMacro("__HEXAGON_V4__"); 4336 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4337 if(Opts.HexagonQdsp6Compat) { 4338 Builder.defineMacro("__QDSP6_V4__"); 4339 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4340 } 4341 } 4342 else if(CPU == "hexagonv5") { 4343 Builder.defineMacro("__HEXAGON_V5__"); 4344 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4345 if(Opts.HexagonQdsp6Compat) { 4346 Builder.defineMacro("__QDSP6_V5__"); 4347 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4348 } 4349 } 4350 } 4351 4352 const char * const HexagonTargetInfo::GCCRegNames[] = { 4353 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4354 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4355 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4356 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4357 "p0", "p1", "p2", "p3", 4358 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4359 }; 4360 4361 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4362 unsigned &NumNames) const { 4363 Names = GCCRegNames; 4364 NumNames = llvm::array_lengthof(GCCRegNames); 4365 } 4366 4367 4368 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4369 { { "sp" }, "r29" }, 4370 { { "fp" }, "r30" }, 4371 { { "lr" }, "r31" }, 4372 }; 4373 4374 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4375 unsigned &NumAliases) const { 4376 Aliases = GCCRegAliases; 4377 NumAliases = llvm::array_lengthof(GCCRegAliases); 4378 } 4379 4380 4381 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4382 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4383 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4384 ALL_LANGUAGES }, 4385 #include "clang/Basic/BuiltinsHexagon.def" 4386 }; 4387 } 4388 4389 4390 namespace { 4391 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4392 class SparcTargetInfo : public TargetInfo { 4393 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4394 static const char * const GCCRegNames[]; 4395 bool SoftFloat; 4396 public: 4397 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4398 4399 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 4400 DiagnosticsEngine &Diags) { 4401 SoftFloat = false; 4402 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4403 if (Features[i] == "+soft-float") 4404 SoftFloat = true; 4405 return true; 4406 } 4407 virtual void getTargetDefines(const LangOptions &Opts, 4408 MacroBuilder &Builder) const { 4409 DefineStd(Builder, "sparc", Opts); 4410 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4411 4412 if (SoftFloat) 4413 Builder.defineMacro("SOFT_FLOAT", "1"); 4414 } 4415 4416 virtual bool hasFeature(StringRef Feature) const { 4417 return llvm::StringSwitch<bool>(Feature) 4418 .Case("softfloat", SoftFloat) 4419 .Case("sparc", true) 4420 .Default(false); 4421 } 4422 4423 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4424 unsigned &NumRecords) const { 4425 // FIXME: Implement! 4426 } 4427 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4428 return TargetInfo::VoidPtrBuiltinVaList; 4429 } 4430 virtual void getGCCRegNames(const char * const *&Names, 4431 unsigned &NumNames) const; 4432 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4433 unsigned &NumAliases) const; 4434 virtual bool validateAsmConstraint(const char *&Name, 4435 TargetInfo::ConstraintInfo &info) const { 4436 // FIXME: Implement! 4437 return false; 4438 } 4439 virtual const char *getClobbers() const { 4440 // FIXME: Implement! 4441 return ""; 4442 } 4443 }; 4444 4445 const char * const SparcTargetInfo::GCCRegNames[] = { 4446 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4447 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4448 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4449 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4450 }; 4451 4452 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4453 unsigned &NumNames) const { 4454 Names = GCCRegNames; 4455 NumNames = llvm::array_lengthof(GCCRegNames); 4456 } 4457 4458 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4459 { { "g0" }, "r0" }, 4460 { { "g1" }, "r1" }, 4461 { { "g2" }, "r2" }, 4462 { { "g3" }, "r3" }, 4463 { { "g4" }, "r4" }, 4464 { { "g5" }, "r5" }, 4465 { { "g6" }, "r6" }, 4466 { { "g7" }, "r7" }, 4467 { { "o0" }, "r8" }, 4468 { { "o1" }, "r9" }, 4469 { { "o2" }, "r10" }, 4470 { { "o3" }, "r11" }, 4471 { { "o4" }, "r12" }, 4472 { { "o5" }, "r13" }, 4473 { { "o6", "sp" }, "r14" }, 4474 { { "o7" }, "r15" }, 4475 { { "l0" }, "r16" }, 4476 { { "l1" }, "r17" }, 4477 { { "l2" }, "r18" }, 4478 { { "l3" }, "r19" }, 4479 { { "l4" }, "r20" }, 4480 { { "l5" }, "r21" }, 4481 { { "l6" }, "r22" }, 4482 { { "l7" }, "r23" }, 4483 { { "i0" }, "r24" }, 4484 { { "i1" }, "r25" }, 4485 { { "i2" }, "r26" }, 4486 { { "i3" }, "r27" }, 4487 { { "i4" }, "r28" }, 4488 { { "i5" }, "r29" }, 4489 { { "i6", "fp" }, "r30" }, 4490 { { "i7" }, "r31" }, 4491 }; 4492 4493 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4494 unsigned &NumAliases) const { 4495 Aliases = GCCRegAliases; 4496 NumAliases = llvm::array_lengthof(GCCRegAliases); 4497 } 4498 4499 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 4500 class SparcV8TargetInfo : public SparcTargetInfo { 4501 public: 4502 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4503 // FIXME: Support Sparc quad-precision long double? 4504 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 4505 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 4506 } 4507 4508 virtual void getTargetDefines(const LangOptions &Opts, 4509 MacroBuilder &Builder) const { 4510 SparcTargetInfo::getTargetDefines(Opts, Builder); 4511 Builder.defineMacro("__sparcv8"); 4512 } 4513 }; 4514 4515 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 4516 class SparcV9TargetInfo : public SparcTargetInfo { 4517 public: 4518 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4519 // FIXME: Support Sparc quad-precision long double? 4520 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 4521 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128"; 4522 // This is an LP64 platform. 4523 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4524 4525 // OpenBSD uses long long for int64_t and intmax_t. 4526 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 4527 IntMaxType = SignedLongLong; 4528 UIntMaxType = UnsignedLongLong; 4529 } else { 4530 IntMaxType = SignedLong; 4531 UIntMaxType = UnsignedLong; 4532 } 4533 Int64Type = IntMaxType; 4534 } 4535 4536 virtual void getTargetDefines(const LangOptions &Opts, 4537 MacroBuilder &Builder) const { 4538 SparcTargetInfo::getTargetDefines(Opts, Builder); 4539 Builder.defineMacro("__sparcv9"); 4540 Builder.defineMacro("__arch64__"); 4541 // Solaris and its derivative AuroraUX don't need these variants, but the 4542 // BSDs do. 4543 if (getTriple().getOS() != llvm::Triple::Solaris && 4544 getTriple().getOS() != llvm::Triple::AuroraUX) { 4545 Builder.defineMacro("__sparc64__"); 4546 Builder.defineMacro("__sparc_v9__"); 4547 Builder.defineMacro("__sparcv9__"); 4548 } 4549 } 4550 }; 4551 4552 } // end anonymous namespace. 4553 4554 namespace { 4555 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 4556 public: 4557 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 4558 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 4559 SizeType = UnsignedInt; 4560 PtrDiffType = SignedInt; 4561 } 4562 }; 4563 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 4564 public: 4565 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 4566 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 4567 SizeType = UnsignedInt; 4568 PtrDiffType = SignedInt; 4569 } 4570 }; 4571 } // end anonymous namespace. 4572 4573 namespace { 4574 class SystemZTargetInfo : public TargetInfo { 4575 static const char *const GCCRegNames[]; 4576 4577 public: 4578 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4579 TLSSupported = true; 4580 IntWidth = IntAlign = 32; 4581 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 4582 PointerWidth = PointerAlign = 64; 4583 LongDoubleWidth = 128; 4584 LongDoubleAlign = 64; 4585 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4586 MinGlobalAlign = 16; 4587 DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64" 4588 "-f32:32-f64:64-f128:64-a0:8:16-n32:64"; 4589 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4590 } 4591 virtual void getTargetDefines(const LangOptions &Opts, 4592 MacroBuilder &Builder) const { 4593 Builder.defineMacro("__s390__"); 4594 Builder.defineMacro("__s390x__"); 4595 Builder.defineMacro("__zarch__"); 4596 Builder.defineMacro("__LONG_DOUBLE_128__"); 4597 } 4598 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4599 unsigned &NumRecords) const { 4600 // FIXME: Implement. 4601 Records = 0; 4602 NumRecords = 0; 4603 } 4604 4605 virtual void getGCCRegNames(const char *const *&Names, 4606 unsigned &NumNames) const; 4607 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4608 unsigned &NumAliases) const { 4609 // No aliases. 4610 Aliases = 0; 4611 NumAliases = 0; 4612 } 4613 virtual bool validateAsmConstraint(const char *&Name, 4614 TargetInfo::ConstraintInfo &info) const; 4615 virtual const char *getClobbers() const { 4616 // FIXME: Is this really right? 4617 return ""; 4618 } 4619 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4620 return TargetInfo::SystemZBuiltinVaList; 4621 } 4622 virtual bool setCPU(const std::string &Name) { 4623 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4624 .Case("z10", true) 4625 .Case("z196", true) 4626 .Case("zEC12", true) 4627 .Default(false); 4628 4629 // No need to store the CPU yet. There aren't any CPU-specific 4630 // macros to define. 4631 return CPUKnown; 4632 } 4633 }; 4634 4635 const char *const SystemZTargetInfo::GCCRegNames[] = { 4636 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4637 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4638 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 4639 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 4640 }; 4641 4642 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 4643 unsigned &NumNames) const { 4644 Names = GCCRegNames; 4645 NumNames = llvm::array_lengthof(GCCRegNames); 4646 } 4647 4648 bool SystemZTargetInfo:: 4649 validateAsmConstraint(const char *&Name, 4650 TargetInfo::ConstraintInfo &Info) const { 4651 switch (*Name) { 4652 default: 4653 return false; 4654 4655 case 'a': // Address register 4656 case 'd': // Data register (equivalent to 'r') 4657 case 'f': // Floating-point register 4658 Info.setAllowsRegister(); 4659 return true; 4660 4661 case 'I': // Unsigned 8-bit constant 4662 case 'J': // Unsigned 12-bit constant 4663 case 'K': // Signed 16-bit constant 4664 case 'L': // Signed 20-bit displacement (on all targets we support) 4665 case 'M': // 0x7fffffff 4666 return true; 4667 4668 case 'Q': // Memory with base and unsigned 12-bit displacement 4669 case 'R': // Likewise, plus an index 4670 case 'S': // Memory with base and signed 20-bit displacement 4671 case 'T': // Likewise, plus an index 4672 Info.setAllowsMemory(); 4673 return true; 4674 } 4675 } 4676 } 4677 4678 namespace { 4679 class MSP430TargetInfo : public TargetInfo { 4680 static const char * const GCCRegNames[]; 4681 public: 4682 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4683 BigEndian = false; 4684 TLSSupported = false; 4685 IntWidth = 16; IntAlign = 16; 4686 LongWidth = 32; LongLongWidth = 64; 4687 LongAlign = LongLongAlign = 16; 4688 PointerWidth = 16; PointerAlign = 16; 4689 SuitableAlign = 16; 4690 SizeType = UnsignedInt; 4691 IntMaxType = SignedLongLong; 4692 UIntMaxType = UnsignedLongLong; 4693 IntPtrType = SignedInt; 4694 PtrDiffType = SignedInt; 4695 SigAtomicType = SignedLong; 4696 DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"; 4697 } 4698 virtual void getTargetDefines(const LangOptions &Opts, 4699 MacroBuilder &Builder) const { 4700 Builder.defineMacro("MSP430"); 4701 Builder.defineMacro("__MSP430__"); 4702 // FIXME: defines for different 'flavours' of MCU 4703 } 4704 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4705 unsigned &NumRecords) const { 4706 // FIXME: Implement. 4707 Records = 0; 4708 NumRecords = 0; 4709 } 4710 virtual bool hasFeature(StringRef Feature) const { 4711 return Feature == "msp430"; 4712 } 4713 virtual void getGCCRegNames(const char * const *&Names, 4714 unsigned &NumNames) const; 4715 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4716 unsigned &NumAliases) const { 4717 // No aliases. 4718 Aliases = 0; 4719 NumAliases = 0; 4720 } 4721 virtual bool validateAsmConstraint(const char *&Name, 4722 TargetInfo::ConstraintInfo &info) const { 4723 // No target constraints for now. 4724 return false; 4725 } 4726 virtual const char *getClobbers() const { 4727 // FIXME: Is this really right? 4728 return ""; 4729 } 4730 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4731 // FIXME: implement 4732 return TargetInfo::CharPtrBuiltinVaList; 4733 } 4734 }; 4735 4736 const char * const MSP430TargetInfo::GCCRegNames[] = { 4737 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4738 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 4739 }; 4740 4741 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 4742 unsigned &NumNames) const { 4743 Names = GCCRegNames; 4744 NumNames = llvm::array_lengthof(GCCRegNames); 4745 } 4746 } 4747 4748 namespace { 4749 4750 // LLVM and Clang cannot be used directly to output native binaries for 4751 // target, but is used to compile C code to llvm bitcode with correct 4752 // type and alignment information. 4753 // 4754 // TCE uses the llvm bitcode as input and uses it for generating customized 4755 // target processor and program binary. TCE co-design environment is 4756 // publicly available in http://tce.cs.tut.fi 4757 4758 static const unsigned TCEOpenCLAddrSpaceMap[] = { 4759 3, // opencl_global 4760 4, // opencl_local 4761 5, // opencl_constant 4762 0, // cuda_device 4763 0, // cuda_constant 4764 0 // cuda_shared 4765 }; 4766 4767 class TCETargetInfo : public TargetInfo{ 4768 public: 4769 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4770 TLSSupported = false; 4771 IntWidth = 32; 4772 LongWidth = LongLongWidth = 32; 4773 PointerWidth = 32; 4774 IntAlign = 32; 4775 LongAlign = LongLongAlign = 32; 4776 PointerAlign = 32; 4777 SuitableAlign = 32; 4778 SizeType = UnsignedInt; 4779 IntMaxType = SignedLong; 4780 UIntMaxType = UnsignedLong; 4781 IntPtrType = SignedInt; 4782 PtrDiffType = SignedInt; 4783 FloatWidth = 32; 4784 FloatAlign = 32; 4785 DoubleWidth = 32; 4786 DoubleAlign = 32; 4787 LongDoubleWidth = 32; 4788 LongDoubleAlign = 32; 4789 FloatFormat = &llvm::APFloat::IEEEsingle; 4790 DoubleFormat = &llvm::APFloat::IEEEsingle; 4791 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 4792 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-" 4793 "i16:16:32-i32:32:32-i64:32:32-" 4794 "f32:32:32-f64:32:32-v64:32:32-" 4795 "v128:32:32-a0:0:32-n32"; 4796 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 4797 UseAddrSpaceMapMangling = true; 4798 } 4799 4800 virtual void getTargetDefines(const LangOptions &Opts, 4801 MacroBuilder &Builder) const { 4802 DefineStd(Builder, "tce", Opts); 4803 Builder.defineMacro("__TCE__"); 4804 Builder.defineMacro("__TCE_V1__"); 4805 } 4806 virtual bool hasFeature(StringRef Feature) const { 4807 return Feature == "tce"; 4808 } 4809 4810 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4811 unsigned &NumRecords) const {} 4812 virtual const char *getClobbers() const { 4813 return ""; 4814 } 4815 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4816 return TargetInfo::VoidPtrBuiltinVaList; 4817 } 4818 virtual void getGCCRegNames(const char * const *&Names, 4819 unsigned &NumNames) const {} 4820 virtual bool validateAsmConstraint(const char *&Name, 4821 TargetInfo::ConstraintInfo &info) const { 4822 return true; 4823 } 4824 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4825 unsigned &NumAliases) const {} 4826 }; 4827 } 4828 4829 namespace { 4830 class MipsTargetInfoBase : public TargetInfo { 4831 virtual void setDescriptionString() = 0; 4832 4833 static const Builtin::Info BuiltinInfo[]; 4834 std::string CPU; 4835 bool IsMips16; 4836 bool IsMicromips; 4837 bool IsNan2008; 4838 bool IsSingleFloat; 4839 enum MipsFloatABI { 4840 HardFloat, SoftFloat 4841 } FloatABI; 4842 enum DspRevEnum { 4843 NoDSP, DSP1, DSP2 4844 } DspRev; 4845 bool HasMSA; 4846 4847 protected: 4848 bool HasFP64; 4849 std::string ABI; 4850 4851 public: 4852 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 4853 const std::string &CPUStr) 4854 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 4855 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 4856 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 4857 4858 virtual const char *getABI() const { return ABI.c_str(); } 4859 virtual bool setABI(const std::string &Name) = 0; 4860 virtual bool setCPU(const std::string &Name) { 4861 CPU = Name; 4862 return true; 4863 } 4864 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 4865 Features[ABI] = true; 4866 Features[CPU] = true; 4867 } 4868 4869 virtual void getTargetDefines(const LangOptions &Opts, 4870 MacroBuilder &Builder) const { 4871 DefineStd(Builder, "mips", Opts); 4872 Builder.defineMacro("_mips"); 4873 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4874 4875 switch (FloatABI) { 4876 case HardFloat: 4877 Builder.defineMacro("__mips_hard_float", Twine(1)); 4878 break; 4879 case SoftFloat: 4880 Builder.defineMacro("__mips_soft_float", Twine(1)); 4881 break; 4882 } 4883 4884 if (IsSingleFloat) 4885 Builder.defineMacro("__mips_single_float", Twine(1)); 4886 4887 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 4888 Builder.defineMacro("_MIPS_FPSET", 4889 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 4890 4891 if (IsMips16) 4892 Builder.defineMacro("__mips16", Twine(1)); 4893 4894 if (IsMicromips) 4895 Builder.defineMacro("__mips_micromips", Twine(1)); 4896 4897 if (IsNan2008) 4898 Builder.defineMacro("__mips_nan2008", Twine(1)); 4899 4900 switch (DspRev) { 4901 default: 4902 break; 4903 case DSP1: 4904 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 4905 Builder.defineMacro("__mips_dsp", Twine(1)); 4906 break; 4907 case DSP2: 4908 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 4909 Builder.defineMacro("__mips_dspr2", Twine(1)); 4910 Builder.defineMacro("__mips_dsp", Twine(1)); 4911 break; 4912 } 4913 4914 if (HasMSA) 4915 Builder.defineMacro("__mips_msa", Twine(1)); 4916 4917 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 4918 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 4919 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 4920 4921 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 4922 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 4923 } 4924 4925 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4926 unsigned &NumRecords) const { 4927 Records = BuiltinInfo; 4928 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 4929 } 4930 virtual bool hasFeature(StringRef Feature) const { 4931 return llvm::StringSwitch<bool>(Feature) 4932 .Case("mips", true) 4933 .Case("fp64", HasFP64) 4934 .Default(false); 4935 } 4936 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4937 return TargetInfo::VoidPtrBuiltinVaList; 4938 } 4939 virtual void getGCCRegNames(const char * const *&Names, 4940 unsigned &NumNames) const { 4941 static const char *const GCCRegNames[] = { 4942 // CPU register names 4943 // Must match second column of GCCRegAliases 4944 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 4945 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 4946 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 4947 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 4948 // Floating point register names 4949 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 4950 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 4951 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 4952 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 4953 // Hi/lo and condition register names 4954 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 4955 "$fcc5","$fcc6","$fcc7", 4956 // MSA register names 4957 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 4958 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 4959 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 4960 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 4961 // MSA control register names 4962 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 4963 "$msarequest", "$msamap", "$msaunmap" 4964 }; 4965 Names = GCCRegNames; 4966 NumNames = llvm::array_lengthof(GCCRegNames); 4967 } 4968 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4969 unsigned &NumAliases) const = 0; 4970 virtual bool validateAsmConstraint(const char *&Name, 4971 TargetInfo::ConstraintInfo &Info) const { 4972 switch (*Name) { 4973 default: 4974 return false; 4975 4976 case 'r': // CPU registers. 4977 case 'd': // Equivalent to "r" unless generating MIPS16 code. 4978 case 'y': // Equivalent to "r", backwards compatibility only. 4979 case 'f': // floating-point registers. 4980 case 'c': // $25 for indirect jumps 4981 case 'l': // lo register 4982 case 'x': // hilo register pair 4983 Info.setAllowsRegister(); 4984 return true; 4985 case 'R': // An address that can be used in a non-macro load or store 4986 Info.setAllowsMemory(); 4987 return true; 4988 } 4989 } 4990 4991 virtual const char *getClobbers() const { 4992 // FIXME: Implement! 4993 return ""; 4994 } 4995 4996 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 4997 DiagnosticsEngine &Diags) { 4998 IsMips16 = false; 4999 IsMicromips = false; 5000 IsNan2008 = false; 5001 IsSingleFloat = false; 5002 FloatABI = HardFloat; 5003 DspRev = NoDSP; 5004 HasFP64 = ABI == "n32" || ABI == "n64" || ABI == "64"; 5005 5006 for (std::vector<std::string>::iterator it = Features.begin(), 5007 ie = Features.end(); it != ie; ++it) { 5008 if (*it == "+single-float") 5009 IsSingleFloat = true; 5010 else if (*it == "+soft-float") 5011 FloatABI = SoftFloat; 5012 else if (*it == "+mips16") 5013 IsMips16 = true; 5014 else if (*it == "+micromips") 5015 IsMicromips = true; 5016 else if (*it == "+dsp") 5017 DspRev = std::max(DspRev, DSP1); 5018 else if (*it == "+dspr2") 5019 DspRev = std::max(DspRev, DSP2); 5020 else if (*it == "+msa") 5021 HasMSA = true; 5022 else if (*it == "+fp64") 5023 HasFP64 = true; 5024 else if (*it == "-fp64") 5025 HasFP64 = false; 5026 else if (*it == "+nan2008") 5027 IsNan2008 = true; 5028 } 5029 5030 // Remove front-end specific options. 5031 std::vector<std::string>::iterator it = 5032 std::find(Features.begin(), Features.end(), "+soft-float"); 5033 if (it != Features.end()) 5034 Features.erase(it); 5035 it = std::find(Features.begin(), Features.end(), "+nan2008"); 5036 if (it != Features.end()) 5037 Features.erase(it); 5038 5039 setDescriptionString(); 5040 5041 return true; 5042 } 5043 5044 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 5045 if (RegNo == 0) return 4; 5046 if (RegNo == 1) return 5; 5047 return -1; 5048 } 5049 }; 5050 5051 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5052 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5053 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5054 ALL_LANGUAGES }, 5055 #include "clang/Basic/BuiltinsMips.def" 5056 }; 5057 5058 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5059 public: 5060 Mips32TargetInfoBase(const llvm::Triple &Triple) 5061 : MipsTargetInfoBase(Triple, "o32", "mips32") { 5062 SizeType = UnsignedInt; 5063 PtrDiffType = SignedInt; 5064 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5065 } 5066 virtual bool setABI(const std::string &Name) { 5067 if ((Name == "o32") || (Name == "eabi")) { 5068 ABI = Name; 5069 return true; 5070 } else if (Name == "32") { 5071 ABI = "o32"; 5072 return true; 5073 } else 5074 return false; 5075 } 5076 virtual void getTargetDefines(const LangOptions &Opts, 5077 MacroBuilder &Builder) const { 5078 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5079 5080 if (ABI == "o32") { 5081 Builder.defineMacro("__mips_o32"); 5082 Builder.defineMacro("_ABIO32", "1"); 5083 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5084 } 5085 else if (ABI == "eabi") 5086 Builder.defineMacro("__mips_eabi"); 5087 else 5088 llvm_unreachable("Invalid ABI for Mips32."); 5089 } 5090 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5091 unsigned &NumAliases) const { 5092 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5093 { { "at" }, "$1" }, 5094 { { "v0" }, "$2" }, 5095 { { "v1" }, "$3" }, 5096 { { "a0" }, "$4" }, 5097 { { "a1" }, "$5" }, 5098 { { "a2" }, "$6" }, 5099 { { "a3" }, "$7" }, 5100 { { "t0" }, "$8" }, 5101 { { "t1" }, "$9" }, 5102 { { "t2" }, "$10" }, 5103 { { "t3" }, "$11" }, 5104 { { "t4" }, "$12" }, 5105 { { "t5" }, "$13" }, 5106 { { "t6" }, "$14" }, 5107 { { "t7" }, "$15" }, 5108 { { "s0" }, "$16" }, 5109 { { "s1" }, "$17" }, 5110 { { "s2" }, "$18" }, 5111 { { "s3" }, "$19" }, 5112 { { "s4" }, "$20" }, 5113 { { "s5" }, "$21" }, 5114 { { "s6" }, "$22" }, 5115 { { "s7" }, "$23" }, 5116 { { "t8" }, "$24" }, 5117 { { "t9" }, "$25" }, 5118 { { "k0" }, "$26" }, 5119 { { "k1" }, "$27" }, 5120 { { "gp" }, "$28" }, 5121 { { "sp","$sp" }, "$29" }, 5122 { { "fp","$fp" }, "$30" }, 5123 { { "ra" }, "$31" } 5124 }; 5125 Aliases = GCCRegAliases; 5126 NumAliases = llvm::array_lengthof(GCCRegAliases); 5127 } 5128 }; 5129 5130 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5131 virtual void setDescriptionString() { 5132 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5133 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 5134 } 5135 5136 public: 5137 Mips32EBTargetInfo(const llvm::Triple &Triple) 5138 : Mips32TargetInfoBase(Triple) { 5139 } 5140 virtual void getTargetDefines(const LangOptions &Opts, 5141 MacroBuilder &Builder) const { 5142 DefineStd(Builder, "MIPSEB", Opts); 5143 Builder.defineMacro("_MIPSEB"); 5144 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5145 } 5146 }; 5147 5148 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5149 virtual void setDescriptionString() { 5150 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5151 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 5152 } 5153 5154 public: 5155 Mips32ELTargetInfo(const llvm::Triple &Triple) 5156 : Mips32TargetInfoBase(Triple) { 5157 BigEndian = false; 5158 } 5159 virtual void getTargetDefines(const LangOptions &Opts, 5160 MacroBuilder &Builder) const { 5161 DefineStd(Builder, "MIPSEL", Opts); 5162 Builder.defineMacro("_MIPSEL"); 5163 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5164 } 5165 }; 5166 5167 class Mips64TargetInfoBase : public MipsTargetInfoBase { 5168 public: 5169 Mips64TargetInfoBase(const llvm::Triple &Triple) 5170 : MipsTargetInfoBase(Triple, "n64", "mips64") { 5171 LongWidth = LongAlign = 64; 5172 PointerWidth = PointerAlign = 64; 5173 LongDoubleWidth = LongDoubleAlign = 128; 5174 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5175 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5176 LongDoubleWidth = LongDoubleAlign = 64; 5177 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5178 } 5179 SuitableAlign = 128; 5180 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5181 } 5182 virtual bool setABI(const std::string &Name) { 5183 if (Name == "n32") { 5184 LongWidth = LongAlign = 32; 5185 PointerWidth = PointerAlign = 32; 5186 ABI = Name; 5187 return true; 5188 } else if (Name == "n64") { 5189 ABI = Name; 5190 return true; 5191 } else if (Name == "64") { 5192 ABI = "n64"; 5193 return true; 5194 } else 5195 return false; 5196 } 5197 virtual void getTargetDefines(const LangOptions &Opts, 5198 MacroBuilder &Builder) const { 5199 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5200 5201 Builder.defineMacro("__mips64"); 5202 Builder.defineMacro("__mips64__"); 5203 5204 if (ABI == "n32") { 5205 Builder.defineMacro("__mips_n32"); 5206 Builder.defineMacro("_ABIN32", "2"); 5207 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5208 } 5209 else if (ABI == "n64") { 5210 Builder.defineMacro("__mips_n64"); 5211 Builder.defineMacro("_ABI64", "3"); 5212 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5213 } 5214 else 5215 llvm_unreachable("Invalid ABI for Mips64."); 5216 } 5217 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5218 unsigned &NumAliases) const { 5219 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5220 { { "at" }, "$1" }, 5221 { { "v0" }, "$2" }, 5222 { { "v1" }, "$3" }, 5223 { { "a0" }, "$4" }, 5224 { { "a1" }, "$5" }, 5225 { { "a2" }, "$6" }, 5226 { { "a3" }, "$7" }, 5227 { { "a4" }, "$8" }, 5228 { { "a5" }, "$9" }, 5229 { { "a6" }, "$10" }, 5230 { { "a7" }, "$11" }, 5231 { { "t0" }, "$12" }, 5232 { { "t1" }, "$13" }, 5233 { { "t2" }, "$14" }, 5234 { { "t3" }, "$15" }, 5235 { { "s0" }, "$16" }, 5236 { { "s1" }, "$17" }, 5237 { { "s2" }, "$18" }, 5238 { { "s3" }, "$19" }, 5239 { { "s4" }, "$20" }, 5240 { { "s5" }, "$21" }, 5241 { { "s6" }, "$22" }, 5242 { { "s7" }, "$23" }, 5243 { { "t8" }, "$24" }, 5244 { { "t9" }, "$25" }, 5245 { { "k0" }, "$26" }, 5246 { { "k1" }, "$27" }, 5247 { { "gp" }, "$28" }, 5248 { { "sp","$sp" }, "$29" }, 5249 { { "fp","$fp" }, "$30" }, 5250 { { "ra" }, "$31" } 5251 }; 5252 Aliases = GCCRegAliases; 5253 NumAliases = llvm::array_lengthof(GCCRegAliases); 5254 } 5255 }; 5256 5257 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5258 virtual void setDescriptionString() { 5259 if (ABI == "n32") 5260 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5261 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5262 "v64:64:64-n32:64-S128"; 5263 else 5264 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5265 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5266 "v64:64:64-n32:64-S128"; 5267 5268 } 5269 5270 public: 5271 Mips64EBTargetInfo(const llvm::Triple &Triple) 5272 : Mips64TargetInfoBase(Triple) {} 5273 virtual void getTargetDefines(const LangOptions &Opts, 5274 MacroBuilder &Builder) const { 5275 DefineStd(Builder, "MIPSEB", Opts); 5276 Builder.defineMacro("_MIPSEB"); 5277 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5278 } 5279 }; 5280 5281 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5282 virtual void setDescriptionString() { 5283 if (ABI == "n32") 5284 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5285 "i64:64:64-f32:32:32-f64:64:64-f128:128:128" 5286 "-v64:64:64-n32:64-S128"; 5287 else 5288 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5289 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5290 "v64:64:64-n32:64-S128"; 5291 } 5292 public: 5293 Mips64ELTargetInfo(const llvm::Triple &Triple) 5294 : Mips64TargetInfoBase(Triple) { 5295 // Default ABI is n64. 5296 BigEndian = false; 5297 } 5298 virtual void getTargetDefines(const LangOptions &Opts, 5299 MacroBuilder &Builder) const { 5300 DefineStd(Builder, "MIPSEL", Opts); 5301 Builder.defineMacro("_MIPSEL"); 5302 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5303 } 5304 }; 5305 } // end anonymous namespace. 5306 5307 namespace { 5308 class PNaClTargetInfo : public TargetInfo { 5309 public: 5310 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5311 BigEndian = false; 5312 this->UserLabelPrefix = ""; 5313 this->LongAlign = 32; 5314 this->LongWidth = 32; 5315 this->PointerAlign = 32; 5316 this->PointerWidth = 32; 5317 this->IntMaxType = TargetInfo::SignedLongLong; 5318 this->UIntMaxType = TargetInfo::UnsignedLongLong; 5319 this->Int64Type = TargetInfo::SignedLongLong; 5320 this->DoubleAlign = 64; 5321 this->LongDoubleWidth = 64; 5322 this->LongDoubleAlign = 64; 5323 this->SizeType = TargetInfo::UnsignedInt; 5324 this->PtrDiffType = TargetInfo::SignedInt; 5325 this->IntPtrType = TargetInfo::SignedInt; 5326 this->RegParmMax = 0; // Disallow regparm 5327 DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5328 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 5329 } 5330 5331 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 5332 } 5333 virtual void getArchDefines(const LangOptions &Opts, 5334 MacroBuilder &Builder) const { 5335 Builder.defineMacro("__le32__"); 5336 Builder.defineMacro("__pnacl__"); 5337 } 5338 virtual void getTargetDefines(const LangOptions &Opts, 5339 MacroBuilder &Builder) const { 5340 Builder.defineMacro("__LITTLE_ENDIAN__"); 5341 getArchDefines(Opts, Builder); 5342 } 5343 virtual bool hasFeature(StringRef Feature) const { 5344 return Feature == "pnacl"; 5345 } 5346 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5347 unsigned &NumRecords) const { 5348 } 5349 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5350 return TargetInfo::PNaClABIBuiltinVaList; 5351 } 5352 virtual void getGCCRegNames(const char * const *&Names, 5353 unsigned &NumNames) const; 5354 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5355 unsigned &NumAliases) const; 5356 virtual bool validateAsmConstraint(const char *&Name, 5357 TargetInfo::ConstraintInfo &Info) const { 5358 return false; 5359 } 5360 5361 virtual const char *getClobbers() const { 5362 return ""; 5363 } 5364 }; 5365 5366 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5367 unsigned &NumNames) const { 5368 Names = NULL; 5369 NumNames = 0; 5370 } 5371 5372 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5373 unsigned &NumAliases) const { 5374 Aliases = NULL; 5375 NumAliases = 0; 5376 } 5377 } // end anonymous namespace. 5378 5379 namespace { 5380 static const unsigned SPIRAddrSpaceMap[] = { 5381 1, // opencl_global 5382 3, // opencl_local 5383 2, // opencl_constant 5384 0, // cuda_device 5385 0, // cuda_constant 5386 0 // cuda_shared 5387 }; 5388 class SPIRTargetInfo : public TargetInfo { 5389 public: 5390 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5391 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5392 "SPIR target must use unknown OS"); 5393 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5394 "SPIR target must use unknown environment type"); 5395 BigEndian = false; 5396 TLSSupported = false; 5397 LongWidth = LongAlign = 64; 5398 AddrSpaceMap = &SPIRAddrSpaceMap; 5399 UseAddrSpaceMapMangling = true; 5400 // Define available target features 5401 // These must be defined in sorted order! 5402 NoAsmVariants = true; 5403 } 5404 virtual void getTargetDefines(const LangOptions &Opts, 5405 MacroBuilder &Builder) const { 5406 DefineStd(Builder, "SPIR", Opts); 5407 } 5408 virtual bool hasFeature(StringRef Feature) const { 5409 return Feature == "spir"; 5410 } 5411 5412 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5413 unsigned &NumRecords) const {} 5414 virtual const char *getClobbers() const { 5415 return ""; 5416 } 5417 virtual void getGCCRegNames(const char * const *&Names, 5418 unsigned &NumNames) const {} 5419 virtual bool validateAsmConstraint(const char *&Name, 5420 TargetInfo::ConstraintInfo &info) const { 5421 return true; 5422 } 5423 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5424 unsigned &NumAliases) const {} 5425 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5426 return TargetInfo::VoidPtrBuiltinVaList; 5427 } 5428 }; 5429 5430 5431 class SPIR32TargetInfo : public SPIRTargetInfo { 5432 public: 5433 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5434 PointerWidth = PointerAlign = 32; 5435 SizeType = TargetInfo::UnsignedInt; 5436 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 5437 DescriptionString 5438 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5439 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-" 5440 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-" 5441 "v512:512:512-v1024:1024:1024"; 5442 } 5443 virtual void getTargetDefines(const LangOptions &Opts, 5444 MacroBuilder &Builder) const { 5445 DefineStd(Builder, "SPIR32", Opts); 5446 } 5447 }; 5448 5449 class SPIR64TargetInfo : public SPIRTargetInfo { 5450 public: 5451 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5452 PointerWidth = PointerAlign = 64; 5453 SizeType = TargetInfo::UnsignedLong; 5454 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 5455 DescriptionString 5456 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5457 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-" 5458 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-" 5459 "v512:512:512-v1024:1024:1024"; 5460 } 5461 virtual void getTargetDefines(const LangOptions &Opts, 5462 MacroBuilder &Builder) const { 5463 DefineStd(Builder, "SPIR64", Opts); 5464 } 5465 }; 5466 } 5467 5468 namespace { 5469 class XCoreTargetInfo : public TargetInfo { 5470 static const Builtin::Info BuiltinInfo[]; 5471 public: 5472 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5473 BigEndian = false; 5474 NoAsmVariants = true; 5475 LongLongAlign = 32; 5476 SuitableAlign = 32; 5477 DoubleAlign = LongDoubleAlign = 32; 5478 SizeType = UnsignedInt; 5479 PtrDiffType = SignedInt; 5480 IntPtrType = SignedInt; 5481 WCharType = UnsignedChar; 5482 WIntType = UnsignedInt; 5483 UseZeroLengthBitfieldAlignment = true; 5484 DescriptionString = "e-p:32:32:32-a0:0:32-n32" 5485 "-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32" 5486 "-f16:16:32-f32:32:32-f64:32:32"; 5487 } 5488 virtual void getTargetDefines(const LangOptions &Opts, 5489 MacroBuilder &Builder) const { 5490 Builder.defineMacro("__XS1B__"); 5491 } 5492 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5493 unsigned &NumRecords) const { 5494 Records = BuiltinInfo; 5495 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 5496 } 5497 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5498 return TargetInfo::VoidPtrBuiltinVaList; 5499 } 5500 virtual const char *getClobbers() const { 5501 return ""; 5502 } 5503 virtual void getGCCRegNames(const char * const *&Names, 5504 unsigned &NumNames) const { 5505 static const char * const GCCRegNames[] = { 5506 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5507 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 5508 }; 5509 Names = GCCRegNames; 5510 NumNames = llvm::array_lengthof(GCCRegNames); 5511 } 5512 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5513 unsigned &NumAliases) const { 5514 Aliases = NULL; 5515 NumAliases = 0; 5516 } 5517 virtual bool validateAsmConstraint(const char *&Name, 5518 TargetInfo::ConstraintInfo &Info) const { 5519 return false; 5520 } 5521 }; 5522 5523 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 5524 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5525 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5526 ALL_LANGUAGES }, 5527 #include "clang/Basic/BuiltinsXCore.def" 5528 }; 5529 } // end anonymous namespace. 5530 5531 5532 //===----------------------------------------------------------------------===// 5533 // Driver code 5534 //===----------------------------------------------------------------------===// 5535 5536 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 5537 llvm::Triple::OSType os = Triple.getOS(); 5538 5539 switch (Triple.getArch()) { 5540 default: 5541 return NULL; 5542 5543 case llvm::Triple::xcore: 5544 return new XCoreTargetInfo(Triple); 5545 5546 case llvm::Triple::hexagon: 5547 return new HexagonTargetInfo(Triple); 5548 5549 case llvm::Triple::aarch64: 5550 switch (os) { 5551 case llvm::Triple::Linux: 5552 return new LinuxTargetInfo<AArch64TargetInfo>(Triple); 5553 default: 5554 return new AArch64TargetInfo(Triple); 5555 } 5556 5557 case llvm::Triple::arm: 5558 case llvm::Triple::thumb: 5559 if (Triple.isOSDarwin()) 5560 return new DarwinARMTargetInfo(Triple); 5561 5562 switch (os) { 5563 case llvm::Triple::Linux: 5564 return new LinuxTargetInfo<ARMTargetInfo>(Triple); 5565 case llvm::Triple::FreeBSD: 5566 return new FreeBSDTargetInfo<ARMTargetInfo>(Triple); 5567 case llvm::Triple::NetBSD: 5568 return new NetBSDTargetInfo<ARMTargetInfo>(Triple); 5569 case llvm::Triple::OpenBSD: 5570 return new OpenBSDTargetInfo<ARMTargetInfo>(Triple); 5571 case llvm::Triple::Bitrig: 5572 return new BitrigTargetInfo<ARMTargetInfo>(Triple); 5573 case llvm::Triple::RTEMS: 5574 return new RTEMSTargetInfo<ARMTargetInfo>(Triple); 5575 case llvm::Triple::NaCl: 5576 return new NaClTargetInfo<ARMTargetInfo>(Triple); 5577 default: 5578 return new ARMTargetInfo(Triple); 5579 } 5580 5581 case llvm::Triple::msp430: 5582 return new MSP430TargetInfo(Triple); 5583 5584 case llvm::Triple::mips: 5585 switch (os) { 5586 case llvm::Triple::Linux: 5587 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 5588 case llvm::Triple::RTEMS: 5589 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 5590 case llvm::Triple::FreeBSD: 5591 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5592 case llvm::Triple::NetBSD: 5593 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5594 default: 5595 return new Mips32EBTargetInfo(Triple); 5596 } 5597 5598 case llvm::Triple::mipsel: 5599 switch (os) { 5600 case llvm::Triple::Linux: 5601 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 5602 case llvm::Triple::RTEMS: 5603 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 5604 case llvm::Triple::FreeBSD: 5605 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5606 case llvm::Triple::NetBSD: 5607 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5608 case llvm::Triple::NaCl: 5609 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 5610 default: 5611 return new Mips32ELTargetInfo(Triple); 5612 } 5613 5614 case llvm::Triple::mips64: 5615 switch (os) { 5616 case llvm::Triple::Linux: 5617 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 5618 case llvm::Triple::RTEMS: 5619 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 5620 case llvm::Triple::FreeBSD: 5621 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5622 case llvm::Triple::NetBSD: 5623 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5624 case llvm::Triple::OpenBSD: 5625 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5626 default: 5627 return new Mips64EBTargetInfo(Triple); 5628 } 5629 5630 case llvm::Triple::mips64el: 5631 switch (os) { 5632 case llvm::Triple::Linux: 5633 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 5634 case llvm::Triple::RTEMS: 5635 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 5636 case llvm::Triple::FreeBSD: 5637 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5638 case llvm::Triple::NetBSD: 5639 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5640 case llvm::Triple::OpenBSD: 5641 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5642 default: 5643 return new Mips64ELTargetInfo(Triple); 5644 } 5645 5646 case llvm::Triple::le32: 5647 switch (os) { 5648 case llvm::Triple::NaCl: 5649 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 5650 default: 5651 return NULL; 5652 } 5653 5654 case llvm::Triple::ppc: 5655 if (Triple.isOSDarwin()) 5656 return new DarwinPPC32TargetInfo(Triple); 5657 switch (os) { 5658 case llvm::Triple::Linux: 5659 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 5660 case llvm::Triple::FreeBSD: 5661 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 5662 case llvm::Triple::NetBSD: 5663 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 5664 case llvm::Triple::OpenBSD: 5665 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 5666 case llvm::Triple::RTEMS: 5667 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 5668 default: 5669 return new PPC32TargetInfo(Triple); 5670 } 5671 5672 case llvm::Triple::ppc64: 5673 if (Triple.isOSDarwin()) 5674 return new DarwinPPC64TargetInfo(Triple); 5675 switch (os) { 5676 case llvm::Triple::Linux: 5677 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5678 case llvm::Triple::Lv2: 5679 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 5680 case llvm::Triple::FreeBSD: 5681 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 5682 case llvm::Triple::NetBSD: 5683 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 5684 default: 5685 return new PPC64TargetInfo(Triple); 5686 } 5687 5688 case llvm::Triple::ppc64le: 5689 switch (os) { 5690 case llvm::Triple::Linux: 5691 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5692 default: 5693 return new PPC64TargetInfo(Triple); 5694 } 5695 5696 case llvm::Triple::nvptx: 5697 return new NVPTX32TargetInfo(Triple); 5698 case llvm::Triple::nvptx64: 5699 return new NVPTX64TargetInfo(Triple); 5700 5701 case llvm::Triple::r600: 5702 return new R600TargetInfo(Triple); 5703 5704 case llvm::Triple::sparc: 5705 switch (os) { 5706 case llvm::Triple::Linux: 5707 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 5708 case llvm::Triple::AuroraUX: 5709 return new AuroraUXSparcV8TargetInfo(Triple); 5710 case llvm::Triple::Solaris: 5711 return new SolarisSparcV8TargetInfo(Triple); 5712 case llvm::Triple::NetBSD: 5713 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 5714 case llvm::Triple::OpenBSD: 5715 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 5716 case llvm::Triple::RTEMS: 5717 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 5718 default: 5719 return new SparcV8TargetInfo(Triple); 5720 } 5721 5722 case llvm::Triple::sparcv9: 5723 switch (os) { 5724 case llvm::Triple::Linux: 5725 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 5726 case llvm::Triple::AuroraUX: 5727 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 5728 case llvm::Triple::Solaris: 5729 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 5730 case llvm::Triple::NetBSD: 5731 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 5732 case llvm::Triple::OpenBSD: 5733 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 5734 case llvm::Triple::FreeBSD: 5735 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 5736 default: 5737 return new SparcV9TargetInfo(Triple); 5738 } 5739 5740 case llvm::Triple::systemz: 5741 switch (os) { 5742 case llvm::Triple::Linux: 5743 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 5744 default: 5745 return new SystemZTargetInfo(Triple); 5746 } 5747 5748 case llvm::Triple::tce: 5749 return new TCETargetInfo(Triple); 5750 5751 case llvm::Triple::x86: 5752 if (Triple.isOSDarwin()) 5753 return new DarwinI386TargetInfo(Triple); 5754 5755 switch (os) { 5756 case llvm::Triple::AuroraUX: 5757 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 5758 case llvm::Triple::Linux: 5759 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 5760 case llvm::Triple::DragonFly: 5761 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 5762 case llvm::Triple::NetBSD: 5763 return new NetBSDI386TargetInfo(Triple); 5764 case llvm::Triple::OpenBSD: 5765 return new OpenBSDI386TargetInfo(Triple); 5766 case llvm::Triple::Bitrig: 5767 return new BitrigI386TargetInfo(Triple); 5768 case llvm::Triple::FreeBSD: 5769 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5770 case llvm::Triple::KFreeBSD: 5771 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5772 case llvm::Triple::Minix: 5773 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 5774 case llvm::Triple::Solaris: 5775 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 5776 case llvm::Triple::Cygwin: 5777 return new CygwinX86_32TargetInfo(Triple); 5778 case llvm::Triple::MinGW32: 5779 return new MinGWX86_32TargetInfo(Triple); 5780 case llvm::Triple::Win32: 5781 return new VisualStudioWindowsX86_32TargetInfo(Triple); 5782 case llvm::Triple::Haiku: 5783 return new HaikuX86_32TargetInfo(Triple); 5784 case llvm::Triple::RTEMS: 5785 return new RTEMSX86_32TargetInfo(Triple); 5786 case llvm::Triple::NaCl: 5787 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 5788 default: 5789 return new X86_32TargetInfo(Triple); 5790 } 5791 5792 case llvm::Triple::x86_64: 5793 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO) 5794 return new DarwinX86_64TargetInfo(Triple); 5795 5796 switch (os) { 5797 case llvm::Triple::AuroraUX: 5798 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 5799 case llvm::Triple::Linux: 5800 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 5801 case llvm::Triple::DragonFly: 5802 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 5803 case llvm::Triple::NetBSD: 5804 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 5805 case llvm::Triple::OpenBSD: 5806 return new OpenBSDX86_64TargetInfo(Triple); 5807 case llvm::Triple::Bitrig: 5808 return new BitrigX86_64TargetInfo(Triple); 5809 case llvm::Triple::FreeBSD: 5810 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5811 case llvm::Triple::KFreeBSD: 5812 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5813 case llvm::Triple::Solaris: 5814 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 5815 case llvm::Triple::MinGW32: 5816 return new MinGWX86_64TargetInfo(Triple); 5817 case llvm::Triple::Win32: // This is what Triple.h supports now. 5818 return new VisualStudioWindowsX86_64TargetInfo(Triple); 5819 case llvm::Triple::NaCl: 5820 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 5821 default: 5822 return new X86_64TargetInfo(Triple); 5823 } 5824 5825 case llvm::Triple::spir: { 5826 if (Triple.getOS() != llvm::Triple::UnknownOS || 5827 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5828 return NULL; 5829 return new SPIR32TargetInfo(Triple); 5830 } 5831 case llvm::Triple::spir64: { 5832 if (Triple.getOS() != llvm::Triple::UnknownOS || 5833 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5834 return NULL; 5835 return new SPIR64TargetInfo(Triple); 5836 } 5837 } 5838 } 5839 5840 /// CreateTargetInfo - Return the target info object for the specified target 5841 /// triple. 5842 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 5843 TargetOptions *Opts) { 5844 llvm::Triple Triple(Opts->Triple); 5845 5846 // Construct the target 5847 OwningPtr<TargetInfo> Target(AllocateTarget(Triple)); 5848 if (!Target) { 5849 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 5850 return 0; 5851 } 5852 Target->setTargetOpts(Opts); 5853 5854 // Set the target CPU if specified. 5855 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 5856 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 5857 return 0; 5858 } 5859 5860 // Set the target ABI if specified. 5861 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 5862 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 5863 return 0; 5864 } 5865 5866 // Set the target C++ ABI. 5867 if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) { 5868 Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI; 5869 return 0; 5870 } 5871 5872 // Set the fp math unit. 5873 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 5874 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 5875 return 0; 5876 } 5877 5878 // Compute the default target features, we need the target to handle this 5879 // because features may have dependencies on one another. 5880 llvm::StringMap<bool> Features; 5881 Target->getDefaultFeatures(Features); 5882 5883 // Apply the user specified deltas. 5884 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 5885 I < N; ++I) { 5886 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 5887 // Apply the feature via the target. 5888 bool Enabled = Name[0] == '+'; 5889 Target->setFeatureEnabled(Features, Name + 1, Enabled); 5890 } 5891 5892 // Add the features to the compile options. 5893 // 5894 // FIXME: If we are completely confident that we have the right set, we only 5895 // need to pass the minuses. 5896 Opts->Features.clear(); 5897 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 5898 ie = Features.end(); it != ie; ++it) 5899 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 5900 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 5901 return 0; 5902 5903 return Target.take(); 5904 } 5905