1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/OwningPtr.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Type.h" 31 #include <algorithm> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const std::string& triple) : TgtInfo(triple) {} 77 virtual void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "5621"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("__MACH__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 96 if (!Opts.ObjCAutoRefCount) { 97 // __weak is always defined, for use in blocks and with objc pointers. 98 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 99 100 // Darwin defines __strong even in C mode (just to nothing). 101 if (Opts.getGC() != LangOptions::NonGC) 102 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 103 else 104 Builder.defineMacro("__strong", ""); 105 106 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 107 // allow this in C, since one might have block pointers in structs that 108 // are used in pure C code and in Objective-C ARC. 109 Builder.defineMacro("__unsafe_unretained", ""); 110 } 111 112 if (Opts.Static) 113 Builder.defineMacro("__STATIC__"); 114 else 115 Builder.defineMacro("__DYNAMIC__"); 116 117 if (Opts.POSIXThreads) 118 Builder.defineMacro("_REENTRANT"); 119 120 // Get the platform type and version number from the triple. 121 unsigned Maj, Min, Rev; 122 if (Triple.isMacOSX()) { 123 Triple.getMacOSXVersion(Maj, Min, Rev); 124 PlatformName = "macosx"; 125 } else { 126 Triple.getOSVersion(Maj, Min, Rev); 127 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 128 } 129 130 // If -target arch-pc-win32-macho option specified, we're 131 // generating code for Win32 ABI. No need to emit 132 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 133 if (PlatformName == "win32") { 134 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 135 return; 136 } 137 138 // Set the appropriate OS version define. 139 if (Triple.getOS() == llvm::Triple::IOS) { 140 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 141 char Str[6]; 142 Str[0] = '0' + Maj; 143 Str[1] = '0' + (Min / 10); 144 Str[2] = '0' + (Min % 10); 145 Str[3] = '0' + (Rev / 10); 146 Str[4] = '0' + (Rev % 10); 147 Str[5] = '\0'; 148 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str); 149 } else { 150 // Note that the Driver allows versions which aren't representable in the 151 // define (because we only get a single digit for the minor and micro 152 // revision numbers). So, we limit them to the maximum representable 153 // version. 154 assert(Triple.getEnvironmentName().empty() && "Invalid environment!"); 155 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 156 char Str[5]; 157 Str[0] = '0' + (Maj / 10); 158 Str[1] = '0' + (Maj % 10); 159 Str[2] = '0' + std::min(Min, 9U); 160 Str[3] = '0' + std::min(Rev, 9U); 161 Str[4] = '\0'; 162 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 163 } 164 165 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 166 } 167 168 namespace { 169 template<typename Target> 170 class DarwinTargetInfo : public OSTargetInfo<Target> { 171 protected: 172 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 173 MacroBuilder &Builder) const { 174 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 175 this->PlatformMinVersion); 176 } 177 178 public: 179 DarwinTargetInfo(const std::string& triple) : 180 OSTargetInfo<Target>(triple) { 181 llvm::Triple T = llvm::Triple(triple); 182 this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7); 183 this->MCountName = "\01mcount"; 184 } 185 186 virtual std::string isValidSectionSpecifier(StringRef SR) const { 187 // Let MCSectionMachO validate this. 188 StringRef Segment, Section; 189 unsigned TAA, StubSize; 190 bool HasTAA; 191 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 192 TAA, HasTAA, StubSize); 193 } 194 195 virtual const char *getStaticInitSectionSpecifier() const { 196 // FIXME: We should return 0 when building kexts. 197 return "__TEXT,__StaticInit,regular,pure_instructions"; 198 } 199 200 /// Darwin does not support protected visibility. Darwin's "default" 201 /// is very similar to ELF's "protected"; Darwin requires a "weak" 202 /// attribute on declarations that can be dynamically replaced. 203 virtual bool hasProtectedVisibility() const { 204 return false; 205 } 206 }; 207 208 209 // DragonFlyBSD Target 210 template<typename Target> 211 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 212 protected: 213 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 214 MacroBuilder &Builder) const { 215 // DragonFly defines; list based off of gcc output 216 Builder.defineMacro("__DragonFly__"); 217 Builder.defineMacro("__DragonFly_cc_version", "100001"); 218 Builder.defineMacro("__ELF__"); 219 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 220 Builder.defineMacro("__tune_i386__"); 221 DefineStd(Builder, "unix", Opts); 222 } 223 public: 224 DragonFlyBSDTargetInfo(const std::string &triple) 225 : OSTargetInfo<Target>(triple) { 226 this->UserLabelPrefix = ""; 227 228 llvm::Triple Triple(triple); 229 switch (Triple.getArch()) { 230 default: 231 case llvm::Triple::x86: 232 case llvm::Triple::x86_64: 233 this->MCountName = ".mcount"; 234 break; 235 } 236 } 237 }; 238 239 // FreeBSD Target 240 template<typename Target> 241 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 242 protected: 243 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 244 MacroBuilder &Builder) const { 245 // FreeBSD defines; list based off of gcc output 246 247 unsigned Release = Triple.getOSMajorVersion(); 248 if (Release == 0U) 249 Release = 8; 250 251 Builder.defineMacro("__FreeBSD__", Twine(Release)); 252 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 253 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 254 DefineStd(Builder, "unix", Opts); 255 Builder.defineMacro("__ELF__"); 256 } 257 public: 258 FreeBSDTargetInfo(const std::string &triple) 259 : OSTargetInfo<Target>(triple) { 260 this->UserLabelPrefix = ""; 261 262 llvm::Triple Triple(triple); 263 switch (Triple.getArch()) { 264 default: 265 case llvm::Triple::x86: 266 case llvm::Triple::x86_64: 267 this->MCountName = ".mcount"; 268 break; 269 case llvm::Triple::mips: 270 case llvm::Triple::mipsel: 271 case llvm::Triple::ppc: 272 case llvm::Triple::ppc64: 273 this->MCountName = "_mcount"; 274 break; 275 case llvm::Triple::arm: 276 this->MCountName = "__mcount"; 277 break; 278 } 279 280 } 281 }; 282 283 // Minix Target 284 template<typename Target> 285 class MinixTargetInfo : public OSTargetInfo<Target> { 286 protected: 287 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 288 MacroBuilder &Builder) const { 289 // Minix defines 290 291 Builder.defineMacro("__minix", "3"); 292 Builder.defineMacro("_EM_WSIZE", "4"); 293 Builder.defineMacro("_EM_PSIZE", "4"); 294 Builder.defineMacro("_EM_SSIZE", "2"); 295 Builder.defineMacro("_EM_LSIZE", "4"); 296 Builder.defineMacro("_EM_FSIZE", "4"); 297 Builder.defineMacro("_EM_DSIZE", "8"); 298 Builder.defineMacro("__ELF__"); 299 DefineStd(Builder, "unix", Opts); 300 } 301 public: 302 MinixTargetInfo(const std::string &triple) 303 : OSTargetInfo<Target>(triple) { 304 this->UserLabelPrefix = ""; 305 } 306 }; 307 308 // Linux target 309 template<typename Target> 310 class LinuxTargetInfo : public OSTargetInfo<Target> { 311 protected: 312 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 313 MacroBuilder &Builder) const { 314 // Linux defines; list based off of gcc output 315 DefineStd(Builder, "unix", Opts); 316 DefineStd(Builder, "linux", Opts); 317 Builder.defineMacro("__gnu_linux__"); 318 Builder.defineMacro("__ELF__"); 319 if (Triple.getEnvironment() == llvm::Triple::ANDROIDEABI) 320 Builder.defineMacro("__ANDROID__", "1"); 321 if (Opts.POSIXThreads) 322 Builder.defineMacro("_REENTRANT"); 323 if (Opts.CPlusPlus) 324 Builder.defineMacro("_GNU_SOURCE"); 325 } 326 public: 327 LinuxTargetInfo(const std::string& triple) 328 : OSTargetInfo<Target>(triple) { 329 this->UserLabelPrefix = ""; 330 this->WIntType = TargetInfo::UnsignedInt; 331 } 332 333 virtual const char *getStaticInitSectionSpecifier() const { 334 return ".text.startup"; 335 } 336 }; 337 338 // NetBSD Target 339 template<typename Target> 340 class NetBSDTargetInfo : public OSTargetInfo<Target> { 341 protected: 342 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 343 MacroBuilder &Builder) const { 344 // NetBSD defines; list based off of gcc output 345 Builder.defineMacro("__NetBSD__"); 346 Builder.defineMacro("__unix__"); 347 Builder.defineMacro("__ELF__"); 348 if (Opts.POSIXThreads) 349 Builder.defineMacro("_POSIX_THREADS"); 350 } 351 public: 352 NetBSDTargetInfo(const std::string &triple) 353 : OSTargetInfo<Target>(triple) { 354 this->UserLabelPrefix = ""; 355 } 356 }; 357 358 // OpenBSD Target 359 template<typename Target> 360 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 361 protected: 362 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 363 MacroBuilder &Builder) const { 364 // OpenBSD defines; list based off of gcc output 365 366 Builder.defineMacro("__OpenBSD__"); 367 DefineStd(Builder, "unix", Opts); 368 Builder.defineMacro("__ELF__"); 369 if (Opts.POSIXThreads) 370 Builder.defineMacro("_REENTRANT"); 371 } 372 public: 373 OpenBSDTargetInfo(const std::string &triple) 374 : OSTargetInfo<Target>(triple) { 375 this->UserLabelPrefix = ""; 376 377 llvm::Triple Triple(triple); 378 switch (Triple.getArch()) { 379 default: 380 case llvm::Triple::x86: 381 case llvm::Triple::x86_64: 382 case llvm::Triple::arm: 383 case llvm::Triple::sparc: 384 this->MCountName = "__mcount"; 385 break; 386 case llvm::Triple::mips64: 387 case llvm::Triple::mips64el: 388 case llvm::Triple::ppc: 389 case llvm::Triple::sparcv9: 390 this->MCountName = "_mcount"; 391 break; 392 } 393 } 394 }; 395 396 // PSP Target 397 template<typename Target> 398 class PSPTargetInfo : public OSTargetInfo<Target> { 399 protected: 400 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 401 MacroBuilder &Builder) const { 402 // PSP defines; list based on the output of the pspdev gcc toolchain. 403 Builder.defineMacro("PSP"); 404 Builder.defineMacro("_PSP"); 405 Builder.defineMacro("__psp__"); 406 Builder.defineMacro("__ELF__"); 407 } 408 public: 409 PSPTargetInfo(const std::string& triple) 410 : OSTargetInfo<Target>(triple) { 411 this->UserLabelPrefix = ""; 412 } 413 }; 414 415 // PS3 PPU Target 416 template<typename Target> 417 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 418 protected: 419 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 420 MacroBuilder &Builder) const { 421 // PS3 PPU defines. 422 Builder.defineMacro("__PPC__"); 423 Builder.defineMacro("__PPU__"); 424 Builder.defineMacro("__CELLOS_LV2__"); 425 Builder.defineMacro("__ELF__"); 426 Builder.defineMacro("__LP32__"); 427 Builder.defineMacro("_ARCH_PPC64"); 428 Builder.defineMacro("__powerpc64__"); 429 } 430 public: 431 PS3PPUTargetInfo(const std::string& triple) 432 : OSTargetInfo<Target>(triple) { 433 this->UserLabelPrefix = ""; 434 this->LongWidth = this->LongAlign = 32; 435 this->PointerWidth = this->PointerAlign = 32; 436 this->IntMaxType = TargetInfo::SignedLongLong; 437 this->UIntMaxType = TargetInfo::UnsignedLongLong; 438 this->Int64Type = TargetInfo::SignedLongLong; 439 this->SizeType = TargetInfo::UnsignedInt; 440 this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 441 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 442 } 443 }; 444 445 // FIXME: Need a real SPU target. 446 // PS3 SPU Target 447 template<typename Target> 448 class PS3SPUTargetInfo : public OSTargetInfo<Target> { 449 protected: 450 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 451 MacroBuilder &Builder) const { 452 // PS3 PPU defines. 453 Builder.defineMacro("__SPU__"); 454 Builder.defineMacro("__ELF__"); 455 } 456 public: 457 PS3SPUTargetInfo(const std::string& triple) 458 : OSTargetInfo<Target>(triple) { 459 this->UserLabelPrefix = ""; 460 } 461 }; 462 463 // AuroraUX target 464 template<typename Target> 465 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 466 protected: 467 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 468 MacroBuilder &Builder) const { 469 DefineStd(Builder, "sun", Opts); 470 DefineStd(Builder, "unix", Opts); 471 Builder.defineMacro("__ELF__"); 472 Builder.defineMacro("__svr4__"); 473 Builder.defineMacro("__SVR4"); 474 } 475 public: 476 AuroraUXTargetInfo(const std::string& triple) 477 : OSTargetInfo<Target>(triple) { 478 this->UserLabelPrefix = ""; 479 this->WCharType = this->SignedLong; 480 // FIXME: WIntType should be SignedLong 481 } 482 }; 483 484 // Solaris target 485 template<typename Target> 486 class SolarisTargetInfo : public OSTargetInfo<Target> { 487 protected: 488 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 489 MacroBuilder &Builder) const { 490 DefineStd(Builder, "sun", Opts); 491 DefineStd(Builder, "unix", Opts); 492 Builder.defineMacro("__ELF__"); 493 Builder.defineMacro("__svr4__"); 494 Builder.defineMacro("__SVR4"); 495 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 496 // newer, but to 500 for everything else. feature_test.h has a check to 497 // ensure that you are not using C99 with an old version of X/Open or C89 498 // with a new version. 499 if (Opts.C99 || Opts.C11) 500 Builder.defineMacro("_XOPEN_SOURCE", "600"); 501 else 502 Builder.defineMacro("_XOPEN_SOURCE", "500"); 503 if (Opts.CPlusPlus) 504 Builder.defineMacro("__C99FEATURES__"); 505 Builder.defineMacro("_LARGEFILE_SOURCE"); 506 Builder.defineMacro("_LARGEFILE64_SOURCE"); 507 Builder.defineMacro("__EXTENSIONS__"); 508 Builder.defineMacro("_REENTRANT"); 509 } 510 public: 511 SolarisTargetInfo(const std::string& triple) 512 : OSTargetInfo<Target>(triple) { 513 this->UserLabelPrefix = ""; 514 this->WCharType = this->SignedInt; 515 // FIXME: WIntType should be SignedLong 516 } 517 }; 518 519 // Windows target 520 template<typename Target> 521 class WindowsTargetInfo : public OSTargetInfo<Target> { 522 protected: 523 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 524 MacroBuilder &Builder) const { 525 Builder.defineMacro("_WIN32"); 526 } 527 void getVisualStudioDefines(const LangOptions &Opts, 528 MacroBuilder &Builder) const { 529 if (Opts.CPlusPlus) { 530 if (Opts.RTTI) 531 Builder.defineMacro("_CPPRTTI"); 532 533 if (Opts.Exceptions) 534 Builder.defineMacro("_CPPUNWIND"); 535 } 536 537 if (!Opts.CharIsSigned) 538 Builder.defineMacro("_CHAR_UNSIGNED"); 539 540 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 541 // but it works for now. 542 if (Opts.POSIXThreads) 543 Builder.defineMacro("_MT"); 544 545 if (Opts.MSCVersion != 0) 546 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 547 548 if (Opts.MicrosoftExt) { 549 Builder.defineMacro("_MSC_EXTENSIONS"); 550 551 if (Opts.CPlusPlus0x) { 552 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 553 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 554 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 555 } 556 } 557 558 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 559 } 560 561 public: 562 WindowsTargetInfo(const std::string &triple) 563 : OSTargetInfo<Target>(triple) {} 564 }; 565 566 } // end anonymous namespace. 567 568 //===----------------------------------------------------------------------===// 569 // Specific target implementations. 570 //===----------------------------------------------------------------------===// 571 572 namespace { 573 // PPC abstract base class 574 class PPCTargetInfo : public TargetInfo { 575 static const Builtin::Info BuiltinInfo[]; 576 static const char * const GCCRegNames[]; 577 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 578 public: 579 PPCTargetInfo(const std::string& triple) : TargetInfo(triple) { 580 LongDoubleWidth = LongDoubleAlign = 128; 581 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 582 } 583 584 virtual void getTargetBuiltins(const Builtin::Info *&Records, 585 unsigned &NumRecords) const { 586 Records = BuiltinInfo; 587 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 588 } 589 590 virtual bool isCLZForZeroUndef() const { return false; } 591 592 virtual void getTargetDefines(const LangOptions &Opts, 593 MacroBuilder &Builder) const; 594 595 virtual bool hasFeature(StringRef Feature) const; 596 597 virtual void getGCCRegNames(const char * const *&Names, 598 unsigned &NumNames) const; 599 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 600 unsigned &NumAliases) const; 601 virtual bool validateAsmConstraint(const char *&Name, 602 TargetInfo::ConstraintInfo &Info) const { 603 switch (*Name) { 604 default: return false; 605 case 'O': // Zero 606 break; 607 case 'b': // Base register 608 case 'f': // Floating point register 609 Info.setAllowsRegister(); 610 break; 611 // FIXME: The following are added to allow parsing. 612 // I just took a guess at what the actions should be. 613 // Also, is more specific checking needed? I.e. specific registers? 614 case 'd': // Floating point register (containing 64-bit value) 615 case 'v': // Altivec vector register 616 Info.setAllowsRegister(); 617 break; 618 case 'w': 619 switch (Name[1]) { 620 case 'd':// VSX vector register to hold vector double data 621 case 'f':// VSX vector register to hold vector float data 622 case 's':// VSX vector register to hold scalar float data 623 case 'a':// Any VSX register 624 break; 625 default: 626 return false; 627 } 628 Info.setAllowsRegister(); 629 Name++; // Skip over 'w'. 630 break; 631 case 'h': // `MQ', `CTR', or `LINK' register 632 case 'q': // `MQ' register 633 case 'c': // `CTR' register 634 case 'l': // `LINK' register 635 case 'x': // `CR' register (condition register) number 0 636 case 'y': // `CR' register (condition register) 637 case 'z': // `XER[CA]' carry bit (part of the XER register) 638 Info.setAllowsRegister(); 639 break; 640 case 'I': // Signed 16-bit constant 641 case 'J': // Unsigned 16-bit constant shifted left 16 bits 642 // (use `L' instead for SImode constants) 643 case 'K': // Unsigned 16-bit constant 644 case 'L': // Signed 16-bit constant shifted left 16 bits 645 case 'M': // Constant larger than 31 646 case 'N': // Exact power of 2 647 case 'P': // Constant whose negation is a signed 16-bit constant 648 case 'G': // Floating point constant that can be loaded into a 649 // register with one instruction per word 650 case 'H': // Integer/Floating point constant that can be loaded 651 // into a register using three instructions 652 break; 653 case 'm': // Memory operand. Note that on PowerPC targets, m can 654 // include addresses that update the base register. It 655 // is therefore only safe to use `m' in an asm statement 656 // if that asm statement accesses the operand exactly once. 657 // The asm statement must also use `%U<opno>' as a 658 // placeholder for the "update" flag in the corresponding 659 // load or store instruction. For example: 660 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 661 // is correct but: 662 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 663 // is not. Use es rather than m if you don't want the base 664 // register to be updated. 665 case 'e': 666 if (Name[1] != 's') 667 return false; 668 // es: A "stable" memory operand; that is, one which does not 669 // include any automodification of the base register. Unlike 670 // `m', this constraint can be used in asm statements that 671 // might access the operand several times, or that might not 672 // access it at all. 673 Info.setAllowsMemory(); 674 Name++; // Skip over 'e'. 675 break; 676 case 'Q': // Memory operand that is an offset from a register (it is 677 // usually better to use `m' or `es' in asm statements) 678 case 'Z': // Memory operand that is an indexed or indirect from a 679 // register (it is usually better to use `m' or `es' in 680 // asm statements) 681 Info.setAllowsMemory(); 682 Info.setAllowsRegister(); 683 break; 684 case 'R': // AIX TOC entry 685 case 'a': // Address operand that is an indexed or indirect from a 686 // register (`p' is preferable for asm statements) 687 case 'S': // Constant suitable as a 64-bit mask operand 688 case 'T': // Constant suitable as a 32-bit mask operand 689 case 'U': // System V Release 4 small data area reference 690 case 't': // AND masks that can be performed by two rldic{l, r} 691 // instructions 692 case 'W': // Vector constant that does not require memory 693 case 'j': // Vector constant that is all zeros. 694 break; 695 // End FIXME. 696 } 697 return true; 698 } 699 virtual const char *getClobbers() const { 700 return ""; 701 } 702 }; 703 704 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 705 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 706 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 707 ALL_LANGUAGES }, 708 #include "clang/Basic/BuiltinsPPC.def" 709 }; 710 711 712 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 713 /// #defines that are not tied to a specific subtarget. 714 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 715 MacroBuilder &Builder) const { 716 // Target identification. 717 Builder.defineMacro("__ppc__"); 718 Builder.defineMacro("_ARCH_PPC"); 719 Builder.defineMacro("__powerpc__"); 720 Builder.defineMacro("__POWERPC__"); 721 if (PointerWidth == 64) { 722 Builder.defineMacro("_ARCH_PPC64"); 723 Builder.defineMacro("_LP64"); 724 Builder.defineMacro("__LP64__"); 725 Builder.defineMacro("__powerpc64__"); 726 Builder.defineMacro("__ppc64__"); 727 } else { 728 Builder.defineMacro("__ppc__"); 729 } 730 731 // Target properties. 732 if (getTriple().getOS() != llvm::Triple::NetBSD) 733 Builder.defineMacro("_BIG_ENDIAN"); 734 Builder.defineMacro("__BIG_ENDIAN__"); 735 736 // Subtarget options. 737 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 738 Builder.defineMacro("__REGISTER_PREFIX__", ""); 739 740 // FIXME: Should be controlled by command line option. 741 Builder.defineMacro("__LONG_DOUBLE_128__"); 742 743 if (Opts.AltiVec) { 744 Builder.defineMacro("__VEC__", "10206"); 745 Builder.defineMacro("__ALTIVEC__"); 746 } 747 } 748 749 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 750 return Feature == "powerpc"; 751 } 752 753 754 const char * const PPCTargetInfo::GCCRegNames[] = { 755 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 756 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 757 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 758 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 759 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 760 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 761 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 762 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 763 "mq", "lr", "ctr", "ap", 764 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 765 "xer", 766 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 767 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 768 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 769 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 770 "vrsave", "vscr", 771 "spe_acc", "spefscr", 772 "sfp" 773 }; 774 775 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 776 unsigned &NumNames) const { 777 Names = GCCRegNames; 778 NumNames = llvm::array_lengthof(GCCRegNames); 779 } 780 781 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 782 // While some of these aliases do map to different registers 783 // they still share the same register name. 784 { { "0" }, "r0" }, 785 { { "1"}, "r1" }, 786 { { "2" }, "r2" }, 787 { { "3" }, "r3" }, 788 { { "4" }, "r4" }, 789 { { "5" }, "r5" }, 790 { { "6" }, "r6" }, 791 { { "7" }, "r7" }, 792 { { "8" }, "r8" }, 793 { { "9" }, "r9" }, 794 { { "10" }, "r10" }, 795 { { "11" }, "r11" }, 796 { { "12" }, "r12" }, 797 { { "13" }, "r13" }, 798 { { "14" }, "r14" }, 799 { { "15" }, "r15" }, 800 { { "16" }, "r16" }, 801 { { "17" }, "r17" }, 802 { { "18" }, "r18" }, 803 { { "19" }, "r19" }, 804 { { "20" }, "r20" }, 805 { { "21" }, "r21" }, 806 { { "22" }, "r22" }, 807 { { "23" }, "r23" }, 808 { { "24" }, "r24" }, 809 { { "25" }, "r25" }, 810 { { "26" }, "r26" }, 811 { { "27" }, "r27" }, 812 { { "28" }, "r28" }, 813 { { "29" }, "r29" }, 814 { { "30" }, "r30" }, 815 { { "31" }, "r31" }, 816 { { "fr0" }, "f0" }, 817 { { "fr1" }, "f1" }, 818 { { "fr2" }, "f2" }, 819 { { "fr3" }, "f3" }, 820 { { "fr4" }, "f4" }, 821 { { "fr5" }, "f5" }, 822 { { "fr6" }, "f6" }, 823 { { "fr7" }, "f7" }, 824 { { "fr8" }, "f8" }, 825 { { "fr9" }, "f9" }, 826 { { "fr10" }, "f10" }, 827 { { "fr11" }, "f11" }, 828 { { "fr12" }, "f12" }, 829 { { "fr13" }, "f13" }, 830 { { "fr14" }, "f14" }, 831 { { "fr15" }, "f15" }, 832 { { "fr16" }, "f16" }, 833 { { "fr17" }, "f17" }, 834 { { "fr18" }, "f18" }, 835 { { "fr19" }, "f19" }, 836 { { "fr20" }, "f20" }, 837 { { "fr21" }, "f21" }, 838 { { "fr22" }, "f22" }, 839 { { "fr23" }, "f23" }, 840 { { "fr24" }, "f24" }, 841 { { "fr25" }, "f25" }, 842 { { "fr26" }, "f26" }, 843 { { "fr27" }, "f27" }, 844 { { "fr28" }, "f28" }, 845 { { "fr29" }, "f29" }, 846 { { "fr30" }, "f30" }, 847 { { "fr31" }, "f31" }, 848 { { "cc" }, "cr0" }, 849 }; 850 851 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 852 unsigned &NumAliases) const { 853 Aliases = GCCRegAliases; 854 NumAliases = llvm::array_lengthof(GCCRegAliases); 855 } 856 } // end anonymous namespace. 857 858 namespace { 859 class PPC32TargetInfo : public PPCTargetInfo { 860 public: 861 PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) { 862 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 863 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 864 865 switch (getTriple().getOS()) { 866 case llvm::Triple::Linux: 867 case llvm::Triple::FreeBSD: 868 case llvm::Triple::NetBSD: 869 SizeType = UnsignedInt; 870 PtrDiffType = SignedInt; 871 IntPtrType = SignedInt; 872 break; 873 default: 874 break; 875 } 876 877 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 878 LongDoubleWidth = LongDoubleAlign = 64; 879 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 880 } 881 } 882 883 virtual const char *getVAListDeclaration() const { 884 // This is the ELF definition, and is overridden by the Darwin sub-target 885 return "typedef struct __va_list_tag {" 886 " unsigned char gpr;" 887 " unsigned char fpr;" 888 " unsigned short reserved;" 889 " void* overflow_arg_area;" 890 " void* reg_save_area;" 891 "} __builtin_va_list[1];"; 892 } 893 }; 894 } // end anonymous namespace. 895 896 namespace { 897 class PPC64TargetInfo : public PPCTargetInfo { 898 public: 899 PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) { 900 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 901 IntMaxType = SignedLong; 902 UIntMaxType = UnsignedLong; 903 Int64Type = SignedLong; 904 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 905 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"; 906 907 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 908 LongDoubleWidth = LongDoubleAlign = 64; 909 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 910 } 911 } 912 virtual const char *getVAListDeclaration() const { 913 return "typedef char* __builtin_va_list;"; 914 } 915 }; 916 } // end anonymous namespace. 917 918 919 namespace { 920 class DarwinPPC32TargetInfo : 921 public DarwinTargetInfo<PPC32TargetInfo> { 922 public: 923 DarwinPPC32TargetInfo(const std::string& triple) 924 : DarwinTargetInfo<PPC32TargetInfo>(triple) { 925 HasAlignMac68kSupport = true; 926 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 927 LongLongAlign = 32; 928 SuitableAlign = 128; 929 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 930 "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32"; 931 } 932 virtual const char *getVAListDeclaration() const { 933 return "typedef char* __builtin_va_list;"; 934 } 935 }; 936 937 class DarwinPPC64TargetInfo : 938 public DarwinTargetInfo<PPC64TargetInfo> { 939 public: 940 DarwinPPC64TargetInfo(const std::string& triple) 941 : DarwinTargetInfo<PPC64TargetInfo>(triple) { 942 HasAlignMac68kSupport = true; 943 SuitableAlign = 128; 944 } 945 }; 946 } // end anonymous namespace. 947 948 namespace { 949 static const unsigned NVPTXAddrSpaceMap[] = { 950 1, // opencl_global 951 3, // opencl_local 952 4, // opencl_constant 953 1, // cuda_device 954 4, // cuda_constant 955 3, // cuda_shared 956 }; 957 class NVPTXTargetInfo : public TargetInfo { 958 static const char * const GCCRegNames[]; 959 static const Builtin::Info BuiltinInfo[]; 960 std::vector<llvm::StringRef> AvailableFeatures; 961 public: 962 NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) { 963 BigEndian = false; 964 TLSSupported = false; 965 LongWidth = LongAlign = 64; 966 AddrSpaceMap = &NVPTXAddrSpaceMap; 967 // Define available target features 968 // These must be defined in sorted order! 969 } 970 virtual void getTargetDefines(const LangOptions &Opts, 971 MacroBuilder &Builder) const { 972 Builder.defineMacro("__PTX__"); 973 Builder.defineMacro("__NVPTX__"); 974 } 975 virtual void getTargetBuiltins(const Builtin::Info *&Records, 976 unsigned &NumRecords) const { 977 Records = BuiltinInfo; 978 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 979 } 980 virtual bool hasFeature(StringRef Feature) const { 981 return Feature == "ptx" || Feature == "nvptx"; 982 } 983 984 virtual void getGCCRegNames(const char * const *&Names, 985 unsigned &NumNames) const; 986 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 987 unsigned &NumAliases) const { 988 // No aliases. 989 Aliases = 0; 990 NumAliases = 0; 991 } 992 virtual bool validateAsmConstraint(const char *&Name, 993 TargetInfo::ConstraintInfo &info) const { 994 // FIXME: implement 995 return true; 996 } 997 virtual const char *getClobbers() const { 998 // FIXME: Is this really right? 999 return ""; 1000 } 1001 virtual const char *getVAListDeclaration() const { 1002 // FIXME: implement 1003 return "typedef char* __builtin_va_list;"; 1004 } 1005 virtual bool setCPU(const std::string &Name) { 1006 return Name == "sm_10" || Name == "sm_13" || Name == "sm_20"; 1007 } 1008 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 1009 StringRef Name, 1010 bool Enabled) const; 1011 }; 1012 1013 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1014 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1015 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1016 ALL_LANGUAGES }, 1017 #include "clang/Basic/BuiltinsNVPTX.def" 1018 }; 1019 1020 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1021 "r0" 1022 }; 1023 1024 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1025 unsigned &NumNames) const { 1026 Names = GCCRegNames; 1027 NumNames = llvm::array_lengthof(GCCRegNames); 1028 } 1029 1030 bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1031 StringRef Name, 1032 bool Enabled) const { 1033 if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(), 1034 Name)) { 1035 Features[Name] = Enabled; 1036 return true; 1037 } else { 1038 return false; 1039 } 1040 } 1041 1042 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1043 public: 1044 NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) { 1045 PointerWidth = PointerAlign = 32; 1046 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1047 DescriptionString 1048 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1049 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1050 "n16:32:64"; 1051 } 1052 }; 1053 1054 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1055 public: 1056 NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) { 1057 PointerWidth = PointerAlign = 64; 1058 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1059 DescriptionString 1060 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1061 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1062 "n16:32:64"; 1063 } 1064 }; 1065 } 1066 1067 namespace { 1068 // MBlaze abstract base class 1069 class MBlazeTargetInfo : public TargetInfo { 1070 static const char * const GCCRegNames[]; 1071 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 1072 1073 public: 1074 MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) { 1075 DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16"; 1076 } 1077 1078 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1079 unsigned &NumRecords) const { 1080 // FIXME: Implement. 1081 Records = 0; 1082 NumRecords = 0; 1083 } 1084 1085 virtual void getTargetDefines(const LangOptions &Opts, 1086 MacroBuilder &Builder) const; 1087 1088 virtual bool hasFeature(StringRef Feature) const { 1089 return Feature == "mblaze"; 1090 } 1091 1092 virtual const char *getVAListDeclaration() const { 1093 return "typedef char* __builtin_va_list;"; 1094 } 1095 virtual const char *getTargetPrefix() const { 1096 return "mblaze"; 1097 } 1098 virtual void getGCCRegNames(const char * const *&Names, 1099 unsigned &NumNames) const; 1100 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1101 unsigned &NumAliases) const; 1102 virtual bool validateAsmConstraint(const char *&Name, 1103 TargetInfo::ConstraintInfo &Info) const { 1104 switch (*Name) { 1105 default: return false; 1106 case 'O': // Zero 1107 return true; 1108 case 'b': // Base register 1109 case 'f': // Floating point register 1110 Info.setAllowsRegister(); 1111 return true; 1112 } 1113 } 1114 virtual const char *getClobbers() const { 1115 return ""; 1116 } 1117 }; 1118 1119 /// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific 1120 /// #defines that are not tied to a specific subtarget. 1121 void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts, 1122 MacroBuilder &Builder) const { 1123 // Target identification. 1124 Builder.defineMacro("__microblaze__"); 1125 Builder.defineMacro("_ARCH_MICROBLAZE"); 1126 Builder.defineMacro("__MICROBLAZE__"); 1127 1128 // Target properties. 1129 Builder.defineMacro("_BIG_ENDIAN"); 1130 Builder.defineMacro("__BIG_ENDIAN__"); 1131 1132 // Subtarget options. 1133 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1134 } 1135 1136 1137 const char * const MBlazeTargetInfo::GCCRegNames[] = { 1138 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1139 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1140 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1141 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1142 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 1143 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 1144 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 1145 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 1146 "hi", "lo", "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4", 1147 "$fcc5","$fcc6","$fcc7","$ap", "$rap", "$frp" 1148 }; 1149 1150 void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names, 1151 unsigned &NumNames) const { 1152 Names = GCCRegNames; 1153 NumNames = llvm::array_lengthof(GCCRegNames); 1154 } 1155 1156 const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = { 1157 { {"f0"}, "r0" }, 1158 { {"f1"}, "r1" }, 1159 { {"f2"}, "r2" }, 1160 { {"f3"}, "r3" }, 1161 { {"f4"}, "r4" }, 1162 { {"f5"}, "r5" }, 1163 { {"f6"}, "r6" }, 1164 { {"f7"}, "r7" }, 1165 { {"f8"}, "r8" }, 1166 { {"f9"}, "r9" }, 1167 { {"f10"}, "r10" }, 1168 { {"f11"}, "r11" }, 1169 { {"f12"}, "r12" }, 1170 { {"f13"}, "r13" }, 1171 { {"f14"}, "r14" }, 1172 { {"f15"}, "r15" }, 1173 { {"f16"}, "r16" }, 1174 { {"f17"}, "r17" }, 1175 { {"f18"}, "r18" }, 1176 { {"f19"}, "r19" }, 1177 { {"f20"}, "r20" }, 1178 { {"f21"}, "r21" }, 1179 { {"f22"}, "r22" }, 1180 { {"f23"}, "r23" }, 1181 { {"f24"}, "r24" }, 1182 { {"f25"}, "r25" }, 1183 { {"f26"}, "r26" }, 1184 { {"f27"}, "r27" }, 1185 { {"f28"}, "r28" }, 1186 { {"f29"}, "r29" }, 1187 { {"f30"}, "r30" }, 1188 { {"f31"}, "r31" }, 1189 }; 1190 1191 void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1192 unsigned &NumAliases) const { 1193 Aliases = GCCRegAliases; 1194 NumAliases = llvm::array_lengthof(GCCRegAliases); 1195 } 1196 } // end anonymous namespace. 1197 1198 namespace { 1199 // Namespace for x86 abstract base class 1200 const Builtin::Info BuiltinInfo[] = { 1201 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1202 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1203 ALL_LANGUAGES }, 1204 #include "clang/Basic/BuiltinsX86.def" 1205 }; 1206 1207 static const char* const GCCRegNames[] = { 1208 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1209 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1210 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1211 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1212 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1213 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1214 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1215 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1216 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1217 }; 1218 1219 const TargetInfo::AddlRegName AddlRegNames[] = { 1220 { { "al", "ah", "eax", "rax" }, 0 }, 1221 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1222 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1223 { { "dl", "dh", "edx", "rdx" }, 1 }, 1224 { { "esi", "rsi" }, 4 }, 1225 { { "edi", "rdi" }, 5 }, 1226 { { "esp", "rsp" }, 7 }, 1227 { { "ebp", "rbp" }, 6 }, 1228 }; 1229 1230 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1231 // most of the implementation can be shared. 1232 class X86TargetInfo : public TargetInfo { 1233 enum X86SSEEnum { 1234 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2 1235 } SSELevel; 1236 enum MMX3DNowEnum { 1237 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1238 } MMX3DNowLevel; 1239 1240 bool HasAES; 1241 bool HasLZCNT; 1242 bool HasBMI; 1243 bool HasBMI2; 1244 bool HasPOPCNT; 1245 bool HasFMA4; 1246 1247 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1248 /// 1249 /// Each enumeration represents a particular CPU supported by Clang. These 1250 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1251 enum CPUKind { 1252 CK_Generic, 1253 1254 /// \name i386 1255 /// i386-generation processors. 1256 //@{ 1257 CK_i386, 1258 //@} 1259 1260 /// \name i486 1261 /// i486-generation processors. 1262 //@{ 1263 CK_i486, 1264 CK_WinChipC6, 1265 CK_WinChip2, 1266 CK_C3, 1267 //@} 1268 1269 /// \name i586 1270 /// i586-generation processors, P5 microarchitecture based. 1271 //@{ 1272 CK_i586, 1273 CK_Pentium, 1274 CK_PentiumMMX, 1275 //@} 1276 1277 /// \name i686 1278 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1279 //@{ 1280 CK_i686, 1281 CK_PentiumPro, 1282 CK_Pentium2, 1283 CK_Pentium3, 1284 CK_Pentium3M, 1285 CK_PentiumM, 1286 CK_C3_2, 1287 1288 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1289 /// Clang however has some logic to suport this. 1290 // FIXME: Warn, deprecate, and potentially remove this. 1291 CK_Yonah, 1292 //@} 1293 1294 /// \name Netburst 1295 /// Netburst microarchitecture based processors. 1296 //@{ 1297 CK_Pentium4, 1298 CK_Pentium4M, 1299 CK_Prescott, 1300 CK_Nocona, 1301 //@} 1302 1303 /// \name Core 1304 /// Core microarchitecture based processors. 1305 //@{ 1306 CK_Core2, 1307 1308 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1309 /// codename which GCC no longer accepts as an option to -march, but Clang 1310 /// has some logic for recognizing it. 1311 // FIXME: Warn, deprecate, and potentially remove this. 1312 CK_Penryn, 1313 //@} 1314 1315 /// \name Atom 1316 /// Atom processors 1317 //@{ 1318 CK_Atom, 1319 //@} 1320 1321 /// \name Nehalem 1322 /// Nehalem microarchitecture based processors. 1323 //@{ 1324 CK_Corei7, 1325 CK_Corei7AVX, 1326 CK_CoreAVXi, 1327 CK_CoreAVX2, 1328 //@} 1329 1330 /// \name K6 1331 /// K6 architecture processors. 1332 //@{ 1333 CK_K6, 1334 CK_K6_2, 1335 CK_K6_3, 1336 //@} 1337 1338 /// \name K7 1339 /// K7 architecture processors. 1340 //@{ 1341 CK_Athlon, 1342 CK_AthlonThunderbird, 1343 CK_Athlon4, 1344 CK_AthlonXP, 1345 CK_AthlonMP, 1346 //@} 1347 1348 /// \name K8 1349 /// K8 architecture processors. 1350 //@{ 1351 CK_Athlon64, 1352 CK_Athlon64SSE3, 1353 CK_AthlonFX, 1354 CK_K8, 1355 CK_K8SSE3, 1356 CK_Opteron, 1357 CK_OpteronSSE3, 1358 CK_AMDFAM10, 1359 //@} 1360 1361 /// \name Bobcat 1362 /// Bobcat architecture processors. 1363 //@{ 1364 CK_BTVER1, 1365 //@} 1366 1367 /// \name Bulldozer 1368 /// Bulldozer architecture processors. 1369 //@{ 1370 CK_BDVER1, 1371 CK_BDVER2, 1372 //@} 1373 1374 /// This specification is deprecated and will be removed in the future. 1375 /// Users should prefer \see CK_K8. 1376 // FIXME: Warn on this when the CPU is set to it. 1377 CK_x86_64, 1378 //@} 1379 1380 /// \name Geode 1381 /// Geode processors. 1382 //@{ 1383 CK_Geode 1384 //@} 1385 } CPU; 1386 1387 public: 1388 X86TargetInfo(const std::string& triple) 1389 : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1390 HasAES(false), HasLZCNT(false), HasBMI(false), HasBMI2(false), 1391 HasPOPCNT(false), HasFMA4(false), CPU(CK_Generic) { 1392 BigEndian = false; 1393 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1394 } 1395 virtual unsigned getFloatEvalMethod() const { 1396 // X87 evaluates with 80 bits "long double" precision. 1397 return SSELevel == NoSSE ? 2 : 0; 1398 } 1399 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1400 unsigned &NumRecords) const { 1401 Records = BuiltinInfo; 1402 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1403 } 1404 virtual void getGCCRegNames(const char * const *&Names, 1405 unsigned &NumNames) const { 1406 Names = GCCRegNames; 1407 NumNames = llvm::array_lengthof(GCCRegNames); 1408 } 1409 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1410 unsigned &NumAliases) const { 1411 Aliases = 0; 1412 NumAliases = 0; 1413 } 1414 virtual void getGCCAddlRegNames(const AddlRegName *&Names, 1415 unsigned &NumNames) const { 1416 Names = AddlRegNames; 1417 NumNames = llvm::array_lengthof(AddlRegNames); 1418 } 1419 virtual bool validateAsmConstraint(const char *&Name, 1420 TargetInfo::ConstraintInfo &info) const; 1421 virtual std::string convertConstraint(const char *&Constraint) const; 1422 virtual const char *getClobbers() const { 1423 return "~{dirflag},~{fpsr},~{flags}"; 1424 } 1425 virtual void getTargetDefines(const LangOptions &Opts, 1426 MacroBuilder &Builder) const; 1427 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 1428 StringRef Name, 1429 bool Enabled) const; 1430 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 1431 virtual bool hasFeature(StringRef Feature) const; 1432 virtual void HandleTargetFeatures(std::vector<std::string> &Features); 1433 virtual const char* getABI() const { 1434 if (PointerWidth == 64 && SSELevel >= AVX) 1435 return "avx"; 1436 else if (PointerWidth == 32 && MMX3DNowLevel == NoMMX3DNow) 1437 return "no-mmx"; 1438 return ""; 1439 } 1440 virtual bool setCPU(const std::string &Name) { 1441 CPU = llvm::StringSwitch<CPUKind>(Name) 1442 .Case("i386", CK_i386) 1443 .Case("i486", CK_i486) 1444 .Case("winchip-c6", CK_WinChipC6) 1445 .Case("winchip2", CK_WinChip2) 1446 .Case("c3", CK_C3) 1447 .Case("i586", CK_i586) 1448 .Case("pentium", CK_Pentium) 1449 .Case("pentium-mmx", CK_PentiumMMX) 1450 .Case("i686", CK_i686) 1451 .Case("pentiumpro", CK_PentiumPro) 1452 .Case("pentium2", CK_Pentium2) 1453 .Case("pentium3", CK_Pentium3) 1454 .Case("pentium3m", CK_Pentium3M) 1455 .Case("pentium-m", CK_PentiumM) 1456 .Case("c3-2", CK_C3_2) 1457 .Case("yonah", CK_Yonah) 1458 .Case("pentium4", CK_Pentium4) 1459 .Case("pentium4m", CK_Pentium4M) 1460 .Case("prescott", CK_Prescott) 1461 .Case("nocona", CK_Nocona) 1462 .Case("core2", CK_Core2) 1463 .Case("penryn", CK_Penryn) 1464 .Case("atom", CK_Atom) 1465 .Case("corei7", CK_Corei7) 1466 .Case("corei7-avx", CK_Corei7AVX) 1467 .Case("core-avx-i", CK_CoreAVXi) 1468 .Case("core-avx2", CK_CoreAVX2) 1469 .Case("k6", CK_K6) 1470 .Case("k6-2", CK_K6_2) 1471 .Case("k6-3", CK_K6_3) 1472 .Case("athlon", CK_Athlon) 1473 .Case("athlon-tbird", CK_AthlonThunderbird) 1474 .Case("athlon-4", CK_Athlon4) 1475 .Case("athlon-xp", CK_AthlonXP) 1476 .Case("athlon-mp", CK_AthlonMP) 1477 .Case("athlon64", CK_Athlon64) 1478 .Case("athlon64-sse3", CK_Athlon64SSE3) 1479 .Case("athlon-fx", CK_AthlonFX) 1480 .Case("k8", CK_K8) 1481 .Case("k8-sse3", CK_K8SSE3) 1482 .Case("opteron", CK_Opteron) 1483 .Case("opteron-sse3", CK_OpteronSSE3) 1484 .Case("amdfam10", CK_AMDFAM10) 1485 .Case("btver1", CK_BTVER1) 1486 .Case("bdver1", CK_BDVER1) 1487 .Case("bdver2", CK_BDVER2) 1488 .Case("x86-64", CK_x86_64) 1489 .Case("geode", CK_Geode) 1490 .Default(CK_Generic); 1491 1492 // Perform any per-CPU checks necessary to determine if this CPU is 1493 // acceptable. 1494 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1495 // invalid without explaining *why*. 1496 switch (CPU) { 1497 case CK_Generic: 1498 // No processor selected! 1499 return false; 1500 1501 case CK_i386: 1502 case CK_i486: 1503 case CK_WinChipC6: 1504 case CK_WinChip2: 1505 case CK_C3: 1506 case CK_i586: 1507 case CK_Pentium: 1508 case CK_PentiumMMX: 1509 case CK_i686: 1510 case CK_PentiumPro: 1511 case CK_Pentium2: 1512 case CK_Pentium3: 1513 case CK_Pentium3M: 1514 case CK_PentiumM: 1515 case CK_Yonah: 1516 case CK_C3_2: 1517 case CK_Pentium4: 1518 case CK_Pentium4M: 1519 case CK_Prescott: 1520 case CK_K6: 1521 case CK_K6_2: 1522 case CK_K6_3: 1523 case CK_Athlon: 1524 case CK_AthlonThunderbird: 1525 case CK_Athlon4: 1526 case CK_AthlonXP: 1527 case CK_AthlonMP: 1528 case CK_Geode: 1529 // Only accept certain architectures when compiling in 32-bit mode. 1530 if (PointerWidth != 32) 1531 return false; 1532 1533 // Fallthrough 1534 case CK_Nocona: 1535 case CK_Core2: 1536 case CK_Penryn: 1537 case CK_Atom: 1538 case CK_Corei7: 1539 case CK_Corei7AVX: 1540 case CK_CoreAVXi: 1541 case CK_CoreAVX2: 1542 case CK_Athlon64: 1543 case CK_Athlon64SSE3: 1544 case CK_AthlonFX: 1545 case CK_K8: 1546 case CK_K8SSE3: 1547 case CK_Opteron: 1548 case CK_OpteronSSE3: 1549 case CK_AMDFAM10: 1550 case CK_BTVER1: 1551 case CK_BDVER1: 1552 case CK_BDVER2: 1553 case CK_x86_64: 1554 return true; 1555 } 1556 llvm_unreachable("Unhandled CPU kind"); 1557 } 1558 }; 1559 1560 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1561 // FIXME: This should not be here. 1562 Features["3dnow"] = false; 1563 Features["3dnowa"] = false; 1564 Features["mmx"] = false; 1565 Features["sse"] = false; 1566 Features["sse2"] = false; 1567 Features["sse3"] = false; 1568 Features["ssse3"] = false; 1569 Features["sse41"] = false; 1570 Features["sse42"] = false; 1571 Features["sse4a"] = false; 1572 Features["aes"] = false; 1573 Features["avx"] = false; 1574 Features["avx2"] = false; 1575 Features["lzcnt"] = false; 1576 Features["bmi"] = false; 1577 Features["bmi2"] = false; 1578 Features["popcnt"] = false; 1579 Features["fma4"] = false; 1580 1581 // FIXME: This *really* should not be here. 1582 1583 // X86_64 always has SSE2. 1584 if (PointerWidth == 64) 1585 Features["sse2"] = Features["sse"] = Features["mmx"] = true; 1586 1587 switch (CPU) { 1588 case CK_Generic: 1589 case CK_i386: 1590 case CK_i486: 1591 case CK_i586: 1592 case CK_Pentium: 1593 case CK_i686: 1594 case CK_PentiumPro: 1595 break; 1596 case CK_PentiumMMX: 1597 case CK_Pentium2: 1598 setFeatureEnabled(Features, "mmx", true); 1599 break; 1600 case CK_Pentium3: 1601 case CK_Pentium3M: 1602 setFeatureEnabled(Features, "mmx", true); 1603 setFeatureEnabled(Features, "sse", true); 1604 break; 1605 case CK_PentiumM: 1606 case CK_Pentium4: 1607 case CK_Pentium4M: 1608 case CK_x86_64: 1609 setFeatureEnabled(Features, "mmx", true); 1610 setFeatureEnabled(Features, "sse2", true); 1611 break; 1612 case CK_Yonah: 1613 case CK_Prescott: 1614 case CK_Nocona: 1615 setFeatureEnabled(Features, "mmx", true); 1616 setFeatureEnabled(Features, "sse3", true); 1617 break; 1618 case CK_Core2: 1619 setFeatureEnabled(Features, "mmx", true); 1620 setFeatureEnabled(Features, "ssse3", true); 1621 break; 1622 case CK_Penryn: 1623 setFeatureEnabled(Features, "mmx", true); 1624 setFeatureEnabled(Features, "sse4.1", true); 1625 break; 1626 case CK_Atom: 1627 setFeatureEnabled(Features, "mmx", true); 1628 setFeatureEnabled(Features, "ssse3", true); 1629 break; 1630 case CK_Corei7: 1631 setFeatureEnabled(Features, "mmx", true); 1632 setFeatureEnabled(Features, "sse4", true); 1633 setFeatureEnabled(Features, "aes", true); 1634 break; 1635 case CK_Corei7AVX: 1636 case CK_CoreAVXi: 1637 setFeatureEnabled(Features, "mmx", true); 1638 setFeatureEnabled(Features, "avx", true); 1639 setFeatureEnabled(Features, "aes", true); 1640 break; 1641 case CK_CoreAVX2: 1642 setFeatureEnabled(Features, "mmx", true); 1643 setFeatureEnabled(Features, "avx2", true); 1644 setFeatureEnabled(Features, "aes", true); 1645 setFeatureEnabled(Features, "lzcnt", true); 1646 setFeatureEnabled(Features, "bmi", true); 1647 setFeatureEnabled(Features, "bmi2", true); 1648 break; 1649 case CK_K6: 1650 case CK_WinChipC6: 1651 setFeatureEnabled(Features, "mmx", true); 1652 break; 1653 case CK_K6_2: 1654 case CK_K6_3: 1655 case CK_WinChip2: 1656 case CK_C3: 1657 setFeatureEnabled(Features, "3dnow", true); 1658 break; 1659 case CK_Athlon: 1660 case CK_AthlonThunderbird: 1661 case CK_Geode: 1662 setFeatureEnabled(Features, "3dnowa", true); 1663 break; 1664 case CK_Athlon4: 1665 case CK_AthlonXP: 1666 case CK_AthlonMP: 1667 setFeatureEnabled(Features, "sse", true); 1668 setFeatureEnabled(Features, "3dnowa", true); 1669 break; 1670 case CK_K8: 1671 case CK_Opteron: 1672 case CK_Athlon64: 1673 case CK_AthlonFX: 1674 setFeatureEnabled(Features, "sse2", true); 1675 setFeatureEnabled(Features, "3dnowa", true); 1676 break; 1677 case CK_K8SSE3: 1678 case CK_OpteronSSE3: 1679 case CK_Athlon64SSE3: 1680 setFeatureEnabled(Features, "sse3", true); 1681 setFeatureEnabled(Features, "3dnowa", true); 1682 break; 1683 case CK_AMDFAM10: 1684 setFeatureEnabled(Features, "sse3", true); 1685 setFeatureEnabled(Features, "sse4a", true); 1686 setFeatureEnabled(Features, "3dnowa", true); 1687 break; 1688 case CK_BTVER1: 1689 setFeatureEnabled(Features, "ssse3", true); 1690 setFeatureEnabled(Features, "sse4a", true); 1691 case CK_BDVER1: 1692 case CK_BDVER2: 1693 setFeatureEnabled(Features, "avx", true); 1694 setFeatureEnabled(Features, "sse4a", true); 1695 setFeatureEnabled(Features, "aes", true); 1696 break; 1697 case CK_C3_2: 1698 setFeatureEnabled(Features, "mmx", true); 1699 setFeatureEnabled(Features, "sse", true); 1700 break; 1701 } 1702 } 1703 1704 bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1705 StringRef Name, 1706 bool Enabled) const { 1707 // FIXME: This *really* should not be here. We need some way of translating 1708 // options into llvm subtarget features. 1709 if (!Features.count(Name) && 1710 (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1")) 1711 return false; 1712 1713 // FIXME: this should probably use a switch with fall through. 1714 1715 if (Enabled) { 1716 if (Name == "mmx") 1717 Features["mmx"] = true; 1718 else if (Name == "sse") 1719 Features["mmx"] = Features["sse"] = true; 1720 else if (Name == "sse2") 1721 Features["mmx"] = Features["sse"] = Features["sse2"] = true; 1722 else if (Name == "sse3") 1723 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1724 true; 1725 else if (Name == "ssse3") 1726 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1727 Features["ssse3"] = true; 1728 else if (Name == "sse4" || Name == "sse4.2") 1729 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1730 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1731 Features["popcnt"] = true; 1732 else if (Name == "sse4.1") 1733 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1734 Features["ssse3"] = Features["sse41"] = true; 1735 else if (Name == "3dnow") 1736 Features["mmx"] = Features["3dnow"] = true; 1737 else if (Name == "3dnowa") 1738 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true; 1739 else if (Name == "aes") 1740 Features["aes"] = true; 1741 else if (Name == "avx") 1742 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1743 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1744 Features["popcnt"] = Features["avx"] = true; 1745 else if (Name == "avx2") 1746 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1747 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1748 Features["popcnt"] = Features["avx"] = Features["avx2"] = true; 1749 else if (Name == "fma4") 1750 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1751 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1752 Features["popcnt"] = Features["avx"] = Features["fma4"] = true; 1753 else if (Name == "sse4a") 1754 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1755 Features["lzcnt"] = Features["popcnt"] = Features["sse4a"] = true; 1756 else if (Name == "lzcnt") 1757 Features["lzcnt"] = true; 1758 else if (Name == "bmi") 1759 Features["bmi"] = true; 1760 else if (Name == "bmi2") 1761 Features["bmi2"] = true; 1762 else if (Name == "popcnt") 1763 Features["popcnt"] = true; 1764 } else { 1765 if (Name == "mmx") 1766 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false; 1767 else if (Name == "sse") 1768 Features["sse"] = Features["sse2"] = Features["sse3"] = 1769 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1770 Features["sse4a"] = false; 1771 else if (Name == "sse2") 1772 Features["sse2"] = Features["sse3"] = Features["ssse3"] = 1773 Features["sse41"] = Features["sse42"] = Features["sse4a"] = false; 1774 else if (Name == "sse3") 1775 Features["sse3"] = Features["ssse3"] = Features["sse41"] = 1776 Features["sse42"] = Features["sse4a"] = false; 1777 else if (Name == "ssse3") 1778 Features["ssse3"] = Features["sse41"] = Features["sse42"] = false; 1779 else if (Name == "sse4" || Name == "sse4.1") 1780 Features["sse41"] = Features["sse42"] = false; 1781 else if (Name == "sse4.2") 1782 Features["sse42"] = false; 1783 else if (Name == "3dnow") 1784 Features["3dnow"] = Features["3dnowa"] = false; 1785 else if (Name == "3dnowa") 1786 Features["3dnowa"] = false; 1787 else if (Name == "aes") 1788 Features["aes"] = false; 1789 else if (Name == "avx") 1790 Features["avx"] = Features["avx2"] = Features["fma4"] = false; 1791 else if (Name == "avx2") 1792 Features["avx2"] = false; 1793 else if (Name == "sse4a") 1794 Features["sse4a"] = false; 1795 else if (Name == "lzcnt") 1796 Features["lzcnt"] = false; 1797 else if (Name == "bmi") 1798 Features["bmi"] = false; 1799 else if (Name == "bmi2") 1800 Features["bmi2"] = false; 1801 else if (Name == "popcnt") 1802 Features["popcnt"] = false; 1803 else if (Name == "fma4") 1804 Features["fma4"] = false; 1805 } 1806 1807 return true; 1808 } 1809 1810 /// HandleTargetOptions - Perform initialization based on the user 1811 /// configured set of features. 1812 void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) { 1813 // Remember the maximum enabled sselevel. 1814 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 1815 // Ignore disabled features. 1816 if (Features[i][0] == '-') 1817 continue; 1818 1819 StringRef Feature = StringRef(Features[i]).substr(1); 1820 1821 if (Feature == "aes") { 1822 HasAES = true; 1823 continue; 1824 } 1825 1826 if (Feature == "lzcnt") { 1827 HasLZCNT = true; 1828 continue; 1829 } 1830 1831 if (Feature == "bmi") { 1832 HasBMI = true; 1833 continue; 1834 } 1835 1836 if (Feature == "bmi2") { 1837 HasBMI2 = true; 1838 continue; 1839 } 1840 1841 if (Feature == "popcnt") { 1842 HasPOPCNT = true; 1843 continue; 1844 } 1845 1846 if (Feature == "fma4") { 1847 HasFMA4 = true; 1848 continue; 1849 } 1850 1851 assert(Features[i][0] == '+' && "Invalid target feature!"); 1852 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 1853 .Case("avx2", AVX2) 1854 .Case("avx", AVX) 1855 .Case("sse42", SSE42) 1856 .Case("sse41", SSE41) 1857 .Case("ssse3", SSSE3) 1858 .Case("sse3", SSE3) 1859 .Case("sse2", SSE2) 1860 .Case("sse", SSE1) 1861 .Default(NoSSE); 1862 SSELevel = std::max(SSELevel, Level); 1863 1864 MMX3DNowEnum ThreeDNowLevel = 1865 llvm::StringSwitch<MMX3DNowEnum>(Feature) 1866 .Case("3dnowa", AMD3DNowAthlon) 1867 .Case("3dnow", AMD3DNow) 1868 .Case("mmx", MMX) 1869 .Default(NoMMX3DNow); 1870 1871 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 1872 } 1873 1874 // Don't tell the backend if we're turning off mmx; it will end up disabling 1875 // SSE, which we don't want. 1876 std::vector<std::string>::iterator it; 1877 it = std::find(Features.begin(), Features.end(), "-mmx"); 1878 if (it != Features.end()) 1879 Features.erase(it); 1880 } 1881 1882 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 1883 /// definitions for this particular subtarget. 1884 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 1885 MacroBuilder &Builder) const { 1886 // Target identification. 1887 if (PointerWidth == 64) { 1888 if (getLongWidth() == 64) { 1889 Builder.defineMacro("_LP64"); 1890 Builder.defineMacro("__LP64__"); 1891 } 1892 Builder.defineMacro("__amd64__"); 1893 Builder.defineMacro("__amd64"); 1894 Builder.defineMacro("__x86_64"); 1895 Builder.defineMacro("__x86_64__"); 1896 } else { 1897 DefineStd(Builder, "i386", Opts); 1898 } 1899 1900 // Subtarget options. 1901 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 1902 // truly should be based on -mtune options. 1903 switch (CPU) { 1904 case CK_Generic: 1905 break; 1906 case CK_i386: 1907 // The rest are coming from the i386 define above. 1908 Builder.defineMacro("__tune_i386__"); 1909 break; 1910 case CK_i486: 1911 case CK_WinChipC6: 1912 case CK_WinChip2: 1913 case CK_C3: 1914 defineCPUMacros(Builder, "i486"); 1915 break; 1916 case CK_PentiumMMX: 1917 Builder.defineMacro("__pentium_mmx__"); 1918 Builder.defineMacro("__tune_pentium_mmx__"); 1919 // Fallthrough 1920 case CK_i586: 1921 case CK_Pentium: 1922 defineCPUMacros(Builder, "i586"); 1923 defineCPUMacros(Builder, "pentium"); 1924 break; 1925 case CK_Pentium3: 1926 case CK_Pentium3M: 1927 case CK_PentiumM: 1928 Builder.defineMacro("__tune_pentium3__"); 1929 // Fallthrough 1930 case CK_Pentium2: 1931 case CK_C3_2: 1932 Builder.defineMacro("__tune_pentium2__"); 1933 // Fallthrough 1934 case CK_PentiumPro: 1935 Builder.defineMacro("__tune_i686__"); 1936 Builder.defineMacro("__tune_pentiumpro__"); 1937 // Fallthrough 1938 case CK_i686: 1939 Builder.defineMacro("__i686"); 1940 Builder.defineMacro("__i686__"); 1941 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 1942 Builder.defineMacro("__pentiumpro"); 1943 Builder.defineMacro("__pentiumpro__"); 1944 break; 1945 case CK_Pentium4: 1946 case CK_Pentium4M: 1947 defineCPUMacros(Builder, "pentium4"); 1948 break; 1949 case CK_Yonah: 1950 case CK_Prescott: 1951 case CK_Nocona: 1952 defineCPUMacros(Builder, "nocona"); 1953 break; 1954 case CK_Core2: 1955 case CK_Penryn: 1956 defineCPUMacros(Builder, "core2"); 1957 break; 1958 case CK_Atom: 1959 defineCPUMacros(Builder, "atom"); 1960 break; 1961 case CK_Corei7: 1962 case CK_Corei7AVX: 1963 case CK_CoreAVXi: 1964 case CK_CoreAVX2: 1965 defineCPUMacros(Builder, "corei7"); 1966 break; 1967 case CK_K6_2: 1968 Builder.defineMacro("__k6_2__"); 1969 Builder.defineMacro("__tune_k6_2__"); 1970 // Fallthrough 1971 case CK_K6_3: 1972 if (CPU != CK_K6_2) { // In case of fallthrough 1973 // FIXME: GCC may be enabling these in cases where some other k6 1974 // architecture is specified but -m3dnow is explicitly provided. The 1975 // exact semantics need to be determined and emulated here. 1976 Builder.defineMacro("__k6_3__"); 1977 Builder.defineMacro("__tune_k6_3__"); 1978 } 1979 // Fallthrough 1980 case CK_K6: 1981 defineCPUMacros(Builder, "k6"); 1982 break; 1983 case CK_Athlon: 1984 case CK_AthlonThunderbird: 1985 case CK_Athlon4: 1986 case CK_AthlonXP: 1987 case CK_AthlonMP: 1988 defineCPUMacros(Builder, "athlon"); 1989 if (SSELevel != NoSSE) { 1990 Builder.defineMacro("__athlon_sse__"); 1991 Builder.defineMacro("__tune_athlon_sse__"); 1992 } 1993 break; 1994 case CK_K8: 1995 case CK_K8SSE3: 1996 case CK_x86_64: 1997 case CK_Opteron: 1998 case CK_OpteronSSE3: 1999 case CK_Athlon64: 2000 case CK_Athlon64SSE3: 2001 case CK_AthlonFX: 2002 defineCPUMacros(Builder, "k8"); 2003 break; 2004 case CK_AMDFAM10: 2005 defineCPUMacros(Builder, "amdfam10"); 2006 break; 2007 case CK_BTVER1: 2008 defineCPUMacros(Builder, "btver1"); 2009 break; 2010 case CK_BDVER1: 2011 defineCPUMacros(Builder, "bdver1"); 2012 break; 2013 case CK_BDVER2: 2014 defineCPUMacros(Builder, "bdver2"); 2015 break; 2016 case CK_Geode: 2017 defineCPUMacros(Builder, "geode"); 2018 break; 2019 } 2020 2021 // Target properties. 2022 Builder.defineMacro("__LITTLE_ENDIAN__"); 2023 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2024 2025 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2026 // functions in glibc header files that use FP Stack inline asm which the 2027 // backend can't deal with (PR879). 2028 Builder.defineMacro("__NO_MATH_INLINES"); 2029 2030 if (HasAES) 2031 Builder.defineMacro("__AES__"); 2032 2033 if (HasLZCNT) 2034 Builder.defineMacro("__LZCNT__"); 2035 2036 if (HasBMI) 2037 Builder.defineMacro("__BMI__"); 2038 2039 if (HasBMI2) 2040 Builder.defineMacro("__BMI2__"); 2041 2042 if (HasPOPCNT) 2043 Builder.defineMacro("__POPCNT__"); 2044 2045 if (HasFMA4) 2046 Builder.defineMacro("__FMA4__"); 2047 2048 // Each case falls through to the previous one here. 2049 switch (SSELevel) { 2050 case AVX2: 2051 Builder.defineMacro("__AVX2__"); 2052 case AVX: 2053 Builder.defineMacro("__AVX__"); 2054 case SSE42: 2055 Builder.defineMacro("__SSE4_2__"); 2056 case SSE41: 2057 Builder.defineMacro("__SSE4_1__"); 2058 case SSSE3: 2059 Builder.defineMacro("__SSSE3__"); 2060 case SSE3: 2061 Builder.defineMacro("__SSE3__"); 2062 case SSE2: 2063 Builder.defineMacro("__SSE2__"); 2064 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2065 case SSE1: 2066 Builder.defineMacro("__SSE__"); 2067 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2068 case NoSSE: 2069 break; 2070 } 2071 2072 if (Opts.MicrosoftExt && PointerWidth == 32) { 2073 switch (SSELevel) { 2074 case AVX2: 2075 case AVX: 2076 case SSE42: 2077 case SSE41: 2078 case SSSE3: 2079 case SSE3: 2080 case SSE2: 2081 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2082 break; 2083 case SSE1: 2084 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2085 break; 2086 default: 2087 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2088 } 2089 } 2090 2091 // Each case falls through to the previous one here. 2092 switch (MMX3DNowLevel) { 2093 case AMD3DNowAthlon: 2094 Builder.defineMacro("__3dNOW_A__"); 2095 case AMD3DNow: 2096 Builder.defineMacro("__3dNOW__"); 2097 case MMX: 2098 Builder.defineMacro("__MMX__"); 2099 case NoMMX3DNow: 2100 break; 2101 } 2102 } 2103 2104 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2105 return llvm::StringSwitch<bool>(Feature) 2106 .Case("aes", HasAES) 2107 .Case("avx", SSELevel >= AVX) 2108 .Case("avx2", SSELevel >= AVX2) 2109 .Case("bmi", HasBMI) 2110 .Case("bmi2", HasBMI2) 2111 .Case("fma4", HasFMA4) 2112 .Case("lzcnt", HasLZCNT) 2113 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2114 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2115 .Case("mmx", MMX3DNowLevel >= MMX) 2116 .Case("popcnt", HasPOPCNT) 2117 .Case("sse", SSELevel >= SSE1) 2118 .Case("sse2", SSELevel >= SSE2) 2119 .Case("sse3", SSELevel >= SSE3) 2120 .Case("ssse3", SSELevel >= SSSE3) 2121 .Case("sse41", SSELevel >= SSE41) 2122 .Case("sse42", SSELevel >= SSE42) 2123 .Case("x86", true) 2124 .Case("x86_32", PointerWidth == 32) 2125 .Case("x86_64", PointerWidth == 64) 2126 .Default(false); 2127 } 2128 2129 bool 2130 X86TargetInfo::validateAsmConstraint(const char *&Name, 2131 TargetInfo::ConstraintInfo &Info) const { 2132 switch (*Name) { 2133 default: return false; 2134 case 'Y': // first letter of a pair: 2135 switch (*(Name+1)) { 2136 default: return false; 2137 case '0': // First SSE register. 2138 case 't': // Any SSE register, when SSE2 is enabled. 2139 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2140 case 'm': // any MMX register, when inter-unit moves enabled. 2141 break; // falls through to setAllowsRegister. 2142 } 2143 case 'a': // eax. 2144 case 'b': // ebx. 2145 case 'c': // ecx. 2146 case 'd': // edx. 2147 case 'S': // esi. 2148 case 'D': // edi. 2149 case 'A': // edx:eax. 2150 case 'f': // any x87 floating point stack register. 2151 case 't': // top of floating point stack. 2152 case 'u': // second from top of floating point stack. 2153 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2154 case 'y': // Any MMX register. 2155 case 'x': // Any SSE register. 2156 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2157 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2158 case 'l': // "Index" registers: any general register that can be used as an 2159 // index in a base+index memory access. 2160 Info.setAllowsRegister(); 2161 return true; 2162 case 'C': // SSE floating point constant. 2163 case 'G': // x87 floating point constant. 2164 case 'e': // 32-bit signed integer constant for use with zero-extending 2165 // x86_64 instructions. 2166 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2167 // x86_64 instructions. 2168 return true; 2169 } 2170 } 2171 2172 2173 std::string 2174 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2175 switch (*Constraint) { 2176 case 'a': return std::string("{ax}"); 2177 case 'b': return std::string("{bx}"); 2178 case 'c': return std::string("{cx}"); 2179 case 'd': return std::string("{dx}"); 2180 case 'S': return std::string("{si}"); 2181 case 'D': return std::string("{di}"); 2182 case 'p': // address 2183 return std::string("im"); 2184 case 't': // top of floating point stack. 2185 return std::string("{st}"); 2186 case 'u': // second from top of floating point stack. 2187 return std::string("{st(1)}"); // second from top of floating point stack. 2188 default: 2189 return std::string(1, *Constraint); 2190 } 2191 } 2192 } // end anonymous namespace 2193 2194 namespace { 2195 // X86-32 generic target 2196 class X86_32TargetInfo : public X86TargetInfo { 2197 public: 2198 X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) { 2199 DoubleAlign = LongLongAlign = 32; 2200 LongDoubleWidth = 96; 2201 LongDoubleAlign = 32; 2202 SuitableAlign = 128; 2203 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2204 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2205 "a0:0:64-f80:32:32-n8:16:32-S128"; 2206 SizeType = UnsignedInt; 2207 PtrDiffType = SignedInt; 2208 IntPtrType = SignedInt; 2209 RegParmMax = 3; 2210 2211 // Use fpret for all types. 2212 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2213 (1 << TargetInfo::Double) | 2214 (1 << TargetInfo::LongDouble)); 2215 2216 // x86-32 has atomics up to 8 bytes 2217 // FIXME: Check that we actually have cmpxchg8b before setting 2218 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2219 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2220 } 2221 virtual const char *getVAListDeclaration() const { 2222 return "typedef char* __builtin_va_list;"; 2223 } 2224 2225 int getEHDataRegisterNumber(unsigned RegNo) const { 2226 if (RegNo == 0) return 0; 2227 if (RegNo == 1) return 2; 2228 return -1; 2229 } 2230 }; 2231 } // end anonymous namespace 2232 2233 namespace { 2234 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2235 public: 2236 NetBSDI386TargetInfo(const std::string &triple) : 2237 NetBSDTargetInfo<X86_32TargetInfo>(triple) { 2238 } 2239 2240 virtual unsigned getFloatEvalMethod() const { 2241 // NetBSD defaults to "double" rounding 2242 return 1; 2243 } 2244 }; 2245 } // end anonymous namespace 2246 2247 namespace { 2248 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 2249 public: 2250 OpenBSDI386TargetInfo(const std::string& triple) : 2251 OpenBSDTargetInfo<X86_32TargetInfo>(triple) { 2252 SizeType = UnsignedLong; 2253 IntPtrType = SignedLong; 2254 PtrDiffType = SignedLong; 2255 } 2256 }; 2257 } // end anonymous namespace 2258 2259 namespace { 2260 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 2261 public: 2262 DarwinI386TargetInfo(const std::string& triple) : 2263 DarwinTargetInfo<X86_32TargetInfo>(triple) { 2264 LongDoubleWidth = 128; 2265 LongDoubleAlign = 128; 2266 SuitableAlign = 128; 2267 SizeType = UnsignedLong; 2268 IntPtrType = SignedLong; 2269 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2270 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2271 "a0:0:64-f80:128:128-n8:16:32-S128"; 2272 HasAlignMac68kSupport = true; 2273 } 2274 2275 }; 2276 } // end anonymous namespace 2277 2278 namespace { 2279 // x86-32 Windows target 2280 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 2281 public: 2282 WindowsX86_32TargetInfo(const std::string& triple) 2283 : WindowsTargetInfo<X86_32TargetInfo>(triple) { 2284 TLSSupported = false; 2285 WCharType = UnsignedShort; 2286 DoubleAlign = LongLongAlign = 64; 2287 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2288 "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-" 2289 "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"; 2290 } 2291 virtual void getTargetDefines(const LangOptions &Opts, 2292 MacroBuilder &Builder) const { 2293 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 2294 } 2295 }; 2296 } // end anonymous namespace 2297 2298 namespace { 2299 2300 // x86-32 Windows Visual Studio target 2301 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 2302 public: 2303 VisualStudioWindowsX86_32TargetInfo(const std::string& triple) 2304 : WindowsX86_32TargetInfo(triple) { 2305 LongDoubleWidth = LongDoubleAlign = 64; 2306 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 2307 } 2308 virtual void getTargetDefines(const LangOptions &Opts, 2309 MacroBuilder &Builder) const { 2310 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 2311 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 2312 // The value of the following reflects processor type. 2313 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 2314 // We lost the original triple, so we use the default. 2315 Builder.defineMacro("_M_IX86", "600"); 2316 } 2317 }; 2318 } // end anonymous namespace 2319 2320 namespace { 2321 // x86-32 MinGW target 2322 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 2323 public: 2324 MinGWX86_32TargetInfo(const std::string& triple) 2325 : WindowsX86_32TargetInfo(triple) { 2326 } 2327 virtual void getTargetDefines(const LangOptions &Opts, 2328 MacroBuilder &Builder) const { 2329 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 2330 DefineStd(Builder, "WIN32", Opts); 2331 DefineStd(Builder, "WINNT", Opts); 2332 Builder.defineMacro("_X86_"); 2333 Builder.defineMacro("__MSVCRT__"); 2334 Builder.defineMacro("__MINGW32__"); 2335 2336 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 2337 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 2338 if (Opts.MicrosoftExt) 2339 // Provide "as-is" __declspec. 2340 Builder.defineMacro("__declspec", "__declspec"); 2341 else 2342 // Provide alias of __attribute__ like mingw32-gcc. 2343 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 2344 } 2345 }; 2346 } // end anonymous namespace 2347 2348 namespace { 2349 // x86-32 Cygwin target 2350 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 2351 public: 2352 CygwinX86_32TargetInfo(const std::string& triple) 2353 : X86_32TargetInfo(triple) { 2354 TLSSupported = false; 2355 WCharType = UnsignedShort; 2356 DoubleAlign = LongLongAlign = 64; 2357 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2358 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 2359 "a0:0:64-f80:32:32-n8:16:32-S32"; 2360 } 2361 virtual void getTargetDefines(const LangOptions &Opts, 2362 MacroBuilder &Builder) const { 2363 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2364 Builder.defineMacro("__CYGWIN__"); 2365 Builder.defineMacro("__CYGWIN32__"); 2366 DefineStd(Builder, "unix", Opts); 2367 if (Opts.CPlusPlus) 2368 Builder.defineMacro("_GNU_SOURCE"); 2369 } 2370 }; 2371 } // end anonymous namespace 2372 2373 namespace { 2374 // x86-32 Haiku target 2375 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 2376 public: 2377 HaikuX86_32TargetInfo(const std::string& triple) 2378 : X86_32TargetInfo(triple) { 2379 SizeType = UnsignedLong; 2380 IntPtrType = SignedLong; 2381 PtrDiffType = SignedLong; 2382 this->UserLabelPrefix = ""; 2383 } 2384 virtual void getTargetDefines(const LangOptions &Opts, 2385 MacroBuilder &Builder) const { 2386 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2387 Builder.defineMacro("__INTEL__"); 2388 Builder.defineMacro("__HAIKU__"); 2389 } 2390 }; 2391 } // end anonymous namespace 2392 2393 // RTEMS Target 2394 template<typename Target> 2395 class RTEMSTargetInfo : public OSTargetInfo<Target> { 2396 protected: 2397 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 2398 MacroBuilder &Builder) const { 2399 // RTEMS defines; list based off of gcc output 2400 2401 Builder.defineMacro("__rtems__"); 2402 Builder.defineMacro("__ELF__"); 2403 } 2404 public: 2405 RTEMSTargetInfo(const std::string &triple) 2406 : OSTargetInfo<Target>(triple) { 2407 this->UserLabelPrefix = ""; 2408 2409 llvm::Triple Triple(triple); 2410 switch (Triple.getArch()) { 2411 default: 2412 case llvm::Triple::x86: 2413 // this->MCountName = ".mcount"; 2414 break; 2415 case llvm::Triple::mips: 2416 case llvm::Triple::mipsel: 2417 case llvm::Triple::ppc: 2418 case llvm::Triple::ppc64: 2419 // this->MCountName = "_mcount"; 2420 break; 2421 case llvm::Triple::arm: 2422 // this->MCountName = "__mcount"; 2423 break; 2424 } 2425 2426 } 2427 }; 2428 2429 namespace { 2430 // x86-32 RTEMS target 2431 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 2432 public: 2433 RTEMSX86_32TargetInfo(const std::string& triple) 2434 : X86_32TargetInfo(triple) { 2435 SizeType = UnsignedLong; 2436 IntPtrType = SignedLong; 2437 PtrDiffType = SignedLong; 2438 this->UserLabelPrefix = ""; 2439 } 2440 virtual void getTargetDefines(const LangOptions &Opts, 2441 MacroBuilder &Builder) const { 2442 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2443 Builder.defineMacro("__INTEL__"); 2444 Builder.defineMacro("__rtems__"); 2445 } 2446 }; 2447 } // end anonymous namespace 2448 2449 namespace { 2450 // x86-64 generic target 2451 class X86_64TargetInfo : public X86TargetInfo { 2452 public: 2453 X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) { 2454 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 2455 LongDoubleWidth = 128; 2456 LongDoubleAlign = 128; 2457 LargeArrayMinWidth = 128; 2458 LargeArrayAlign = 128; 2459 SuitableAlign = 128; 2460 IntMaxType = SignedLong; 2461 UIntMaxType = UnsignedLong; 2462 Int64Type = SignedLong; 2463 RegParmMax = 6; 2464 2465 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2466 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 2467 "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"; 2468 2469 // Use fpret only for long double. 2470 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 2471 2472 // Use fp2ret for _Complex long double. 2473 ComplexLongDoubleUsesFP2Ret = true; 2474 2475 // x86-64 has atomics up to 16 bytes. 2476 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 2477 // on CPUs with cmpxchg16b 2478 MaxAtomicPromoteWidth = 128; 2479 MaxAtomicInlineWidth = 64; 2480 } 2481 virtual const char *getVAListDeclaration() const { 2482 return "typedef struct __va_list_tag {" 2483 " unsigned gp_offset;" 2484 " unsigned fp_offset;" 2485 " void* overflow_arg_area;" 2486 " void* reg_save_area;" 2487 "} __va_list_tag;" 2488 "typedef __va_list_tag __builtin_va_list[1];"; 2489 } 2490 2491 int getEHDataRegisterNumber(unsigned RegNo) const { 2492 if (RegNo == 0) return 0; 2493 if (RegNo == 1) return 1; 2494 return -1; 2495 } 2496 }; 2497 } // end anonymous namespace 2498 2499 namespace { 2500 // x86-64 Windows target 2501 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 2502 public: 2503 WindowsX86_64TargetInfo(const std::string& triple) 2504 : WindowsTargetInfo<X86_64TargetInfo>(triple) { 2505 TLSSupported = false; 2506 WCharType = UnsignedShort; 2507 LongWidth = LongAlign = 32; 2508 DoubleAlign = LongLongAlign = 64; 2509 IntMaxType = SignedLongLong; 2510 UIntMaxType = UnsignedLongLong; 2511 Int64Type = SignedLongLong; 2512 SizeType = UnsignedLongLong; 2513 PtrDiffType = SignedLongLong; 2514 IntPtrType = SignedLongLong; 2515 this->UserLabelPrefix = ""; 2516 } 2517 virtual void getTargetDefines(const LangOptions &Opts, 2518 MacroBuilder &Builder) const { 2519 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 2520 Builder.defineMacro("_WIN64"); 2521 } 2522 virtual const char *getVAListDeclaration() const { 2523 return "typedef char* __builtin_va_list;"; 2524 } 2525 }; 2526 } // end anonymous namespace 2527 2528 namespace { 2529 // x86-64 Windows Visual Studio target 2530 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 2531 public: 2532 VisualStudioWindowsX86_64TargetInfo(const std::string& triple) 2533 : WindowsX86_64TargetInfo(triple) { 2534 LongDoubleWidth = LongDoubleAlign = 64; 2535 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 2536 } 2537 virtual void getTargetDefines(const LangOptions &Opts, 2538 MacroBuilder &Builder) const { 2539 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 2540 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 2541 Builder.defineMacro("_M_X64"); 2542 Builder.defineMacro("_M_AMD64"); 2543 } 2544 }; 2545 } // end anonymous namespace 2546 2547 namespace { 2548 // x86-64 MinGW target 2549 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 2550 public: 2551 MinGWX86_64TargetInfo(const std::string& triple) 2552 : WindowsX86_64TargetInfo(triple) { 2553 } 2554 virtual void getTargetDefines(const LangOptions &Opts, 2555 MacroBuilder &Builder) const { 2556 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 2557 DefineStd(Builder, "WIN64", Opts); 2558 Builder.defineMacro("__MSVCRT__"); 2559 Builder.defineMacro("__MINGW32__"); 2560 Builder.defineMacro("__MINGW64__"); 2561 2562 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 2563 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 2564 if (Opts.MicrosoftExt) 2565 // Provide "as-is" __declspec. 2566 Builder.defineMacro("__declspec", "__declspec"); 2567 else 2568 // Provide alias of __attribute__ like mingw32-gcc. 2569 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 2570 } 2571 }; 2572 } // end anonymous namespace 2573 2574 namespace { 2575 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 2576 public: 2577 DarwinX86_64TargetInfo(const std::string& triple) 2578 : DarwinTargetInfo<X86_64TargetInfo>(triple) { 2579 Int64Type = SignedLongLong; 2580 } 2581 }; 2582 } // end anonymous namespace 2583 2584 namespace { 2585 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 2586 public: 2587 OpenBSDX86_64TargetInfo(const std::string& triple) 2588 : OpenBSDTargetInfo<X86_64TargetInfo>(triple) { 2589 IntMaxType = SignedLongLong; 2590 UIntMaxType = UnsignedLongLong; 2591 Int64Type = SignedLongLong; 2592 } 2593 }; 2594 } // end anonymous namespace 2595 2596 namespace { 2597 class ARMTargetInfo : public TargetInfo { 2598 // Possible FPU choices. 2599 enum FPUMode { 2600 NoFPU, 2601 VFP2FPU, 2602 VFP3FPU, 2603 NeonFPU 2604 }; 2605 2606 static bool FPUModeIsVFP(FPUMode Mode) { 2607 return Mode >= VFP2FPU && Mode <= NeonFPU; 2608 } 2609 2610 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 2611 static const char * const GCCRegNames[]; 2612 2613 std::string ABI, CPU; 2614 2615 unsigned FPU : 3; 2616 2617 unsigned IsThumb : 1; 2618 2619 // Initialized via features. 2620 unsigned SoftFloat : 1; 2621 unsigned SoftFloatABI : 1; 2622 2623 static const Builtin::Info BuiltinInfo[]; 2624 2625 public: 2626 ARMTargetInfo(const std::string &TripleStr) 2627 : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s") 2628 { 2629 BigEndian = false; 2630 SizeType = UnsignedInt; 2631 PtrDiffType = SignedInt; 2632 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 2633 WCharType = UnsignedInt; 2634 2635 // {} in inline assembly are neon specifiers, not assembly variant 2636 // specifiers. 2637 NoAsmVariants = true; 2638 2639 // FIXME: Should we just treat this as a feature? 2640 IsThumb = getTriple().getArchName().startswith("thumb"); 2641 if (IsThumb) { 2642 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 2643 // so set preferred for small types to 32. 2644 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 2645 "i64:64:64-f32:32:32-f64:64:64-" 2646 "v64:64:64-v128:64:128-a0:0:32-n32-S64"); 2647 } else { 2648 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2649 "i64:64:64-f32:32:32-f64:64:64-" 2650 "v64:64:64-v128:64:128-a0:0:64-n32-S64"); 2651 } 2652 2653 // ARM targets default to using the ARM C++ ABI. 2654 CXXABI = CXXABI_ARM; 2655 2656 // ARM has atomics up to 8 bytes 2657 // FIXME: Set MaxAtomicInlineWidth if we have the feature v6e 2658 MaxAtomicPromoteWidth = 64; 2659 2660 // Do force alignment of members that follow zero length bitfields. If 2661 // the alignment of the zero-length bitfield is greater than the member 2662 // that follows it, `bar', `bar' will be aligned as the type of the 2663 // zero length bitfield. 2664 UseZeroLengthBitfieldAlignment = true; 2665 } 2666 virtual const char *getABI() const { return ABI.c_str(); } 2667 virtual bool setABI(const std::string &Name) { 2668 ABI = Name; 2669 2670 // The defaults (above) are for AAPCS, check if we need to change them. 2671 // 2672 // FIXME: We need support for -meabi... we could just mangle it into the 2673 // name. 2674 if (Name == "apcs-gnu") { 2675 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 2676 SizeType = UnsignedLong; 2677 2678 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 2679 WCharType = SignedInt; 2680 2681 // Do not respect the alignment of bit-field types when laying out 2682 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 2683 UseBitFieldTypeAlignment = false; 2684 2685 /// gcc forces the alignment to 4 bytes, regardless of the type of the 2686 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 2687 /// gcc. 2688 ZeroLengthBitfieldBoundary = 32; 2689 2690 if (IsThumb) { 2691 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 2692 // so set preferred for small types to 32. 2693 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 2694 "i64:32:64-f32:32:32-f64:32:64-" 2695 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 2696 } else { 2697 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2698 "i64:32:64-f32:32:32-f64:32:64-" 2699 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 2700 } 2701 2702 // FIXME: Override "preferred align" for double and long long. 2703 } else if (Name == "aapcs") { 2704 // FIXME: Enumerated types are variable width in straight AAPCS. 2705 } else if (Name == "aapcs-linux") { 2706 ; 2707 } else 2708 return false; 2709 2710 return true; 2711 } 2712 2713 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2714 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 2715 Features["vfp2"] = true; 2716 else if (CPU == "cortex-a8" || CPU == "cortex-a9") 2717 Features["neon"] = true; 2718 } 2719 2720 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 2721 StringRef Name, 2722 bool Enabled) const { 2723 if (Name == "soft-float" || Name == "soft-float-abi" || 2724 Name == "vfp2" || Name == "vfp3" || Name == "neon" || Name == "d16" || 2725 Name == "neonfp") { 2726 Features[Name] = Enabled; 2727 } else 2728 return false; 2729 2730 return true; 2731 } 2732 2733 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 2734 FPU = NoFPU; 2735 SoftFloat = SoftFloatABI = false; 2736 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 2737 if (Features[i] == "+soft-float") 2738 SoftFloat = true; 2739 else if (Features[i] == "+soft-float-abi") 2740 SoftFloatABI = true; 2741 else if (Features[i] == "+vfp2") 2742 FPU = VFP2FPU; 2743 else if (Features[i] == "+vfp3") 2744 FPU = VFP3FPU; 2745 else if (Features[i] == "+neon") 2746 FPU = NeonFPU; 2747 } 2748 2749 // Remove front-end specific options which the backend handles differently. 2750 std::vector<std::string>::iterator it; 2751 it = std::find(Features.begin(), Features.end(), "+soft-float"); 2752 if (it != Features.end()) 2753 Features.erase(it); 2754 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 2755 if (it != Features.end()) 2756 Features.erase(it); 2757 } 2758 2759 virtual bool hasFeature(StringRef Feature) const { 2760 return llvm::StringSwitch<bool>(Feature) 2761 .Case("arm", true) 2762 .Case("softfloat", SoftFloat) 2763 .Case("thumb", IsThumb) 2764 .Case("neon", FPU == NeonFPU && !SoftFloat && 2765 StringRef(getCPUDefineSuffix(CPU)).startswith("7")) 2766 .Default(false); 2767 } 2768 static const char *getCPUDefineSuffix(StringRef Name) { 2769 return llvm::StringSwitch<const char*>(Name) 2770 .Cases("arm8", "arm810", "4") 2771 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 2772 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 2773 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 2774 .Case("ep9312", "4T") 2775 .Cases("arm10tdmi", "arm1020t", "5T") 2776 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 2777 .Case("arm926ej-s", "5TEJ") 2778 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 2779 .Cases("xscale", "iwmmxt", "5TE") 2780 .Case("arm1136j-s", "6J") 2781 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 2782 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 2783 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 2784 .Cases("cortex-a8", "cortex-a9", "7A") 2785 .Case("cortex-m3", "7M") 2786 .Case("cortex-m4", "7M") 2787 .Case("cortex-m0", "6M") 2788 .Default(0); 2789 } 2790 virtual bool setCPU(const std::string &Name) { 2791 if (!getCPUDefineSuffix(Name)) 2792 return false; 2793 2794 CPU = Name; 2795 return true; 2796 } 2797 virtual void getTargetDefines(const LangOptions &Opts, 2798 MacroBuilder &Builder) const { 2799 // Target identification. 2800 Builder.defineMacro("__arm"); 2801 Builder.defineMacro("__arm__"); 2802 2803 // Target properties. 2804 Builder.defineMacro("__ARMEL__"); 2805 Builder.defineMacro("__LITTLE_ENDIAN__"); 2806 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2807 2808 StringRef CPUArch = getCPUDefineSuffix(CPU); 2809 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 2810 2811 // Subtarget options. 2812 2813 // FIXME: It's more complicated than this and we don't really support 2814 // interworking. 2815 if ('5' <= CPUArch[0] && CPUArch[0] <= '7') 2816 Builder.defineMacro("__THUMB_INTERWORK__"); 2817 2818 if (ABI == "aapcs" || ABI == "aapcs-linux") 2819 Builder.defineMacro("__ARM_EABI__"); 2820 2821 if (SoftFloat) 2822 Builder.defineMacro("__SOFTFP__"); 2823 2824 if (CPU == "xscale") 2825 Builder.defineMacro("__XSCALE__"); 2826 2827 bool IsARMv7 = CPUArch.startswith("7"); 2828 if (IsThumb) { 2829 Builder.defineMacro("__THUMBEL__"); 2830 Builder.defineMacro("__thumb__"); 2831 if (CPUArch == "6T2" || IsARMv7) 2832 Builder.defineMacro("__thumb2__"); 2833 } 2834 2835 // Note, this is always on in gcc, even though it doesn't make sense. 2836 Builder.defineMacro("__APCS_32__"); 2837 2838 if (FPUModeIsVFP((FPUMode) FPU)) 2839 Builder.defineMacro("__VFP_FP__"); 2840 2841 // This only gets set when Neon instructions are actually available, unlike 2842 // the VFP define, hence the soft float and arch check. This is subtly 2843 // different from gcc, we follow the intent which was that it should be set 2844 // when Neon instructions are actually available. 2845 if (FPU == NeonFPU && !SoftFloat && IsARMv7) 2846 Builder.defineMacro("__ARM_NEON__"); 2847 } 2848 virtual void getTargetBuiltins(const Builtin::Info *&Records, 2849 unsigned &NumRecords) const { 2850 Records = BuiltinInfo; 2851 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 2852 } 2853 virtual bool isCLZForZeroUndef() const { return false; } 2854 virtual const char *getVAListDeclaration() const { 2855 return "typedef void* __builtin_va_list;"; 2856 } 2857 virtual void getGCCRegNames(const char * const *&Names, 2858 unsigned &NumNames) const; 2859 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 2860 unsigned &NumAliases) const; 2861 virtual bool validateAsmConstraint(const char *&Name, 2862 TargetInfo::ConstraintInfo &Info) const { 2863 // FIXME: Check if this is complete 2864 switch (*Name) { 2865 default: 2866 case 'l': // r0-r7 2867 case 'h': // r8-r15 2868 case 'w': // VFP Floating point register single precision 2869 case 'P': // VFP Floating point register double precision 2870 Info.setAllowsRegister(); 2871 return true; 2872 case 'Q': // A memory address that is a single base register. 2873 Info.setAllowsMemory(); 2874 return true; 2875 case 'U': // a memory reference... 2876 switch (Name[1]) { 2877 case 'q': // ...ARMV4 ldrsb 2878 case 'v': // ...VFP load/store (reg+constant offset) 2879 case 'y': // ...iWMMXt load/store 2880 case 't': // address valid for load/store opaque types wider 2881 // than 128-bits 2882 case 'n': // valid address for Neon doubleword vector load/store 2883 case 'm': // valid address for Neon element and structure load/store 2884 case 's': // valid address for non-offset loads/stores of quad-word 2885 // values in four ARM registers 2886 Info.setAllowsMemory(); 2887 Name++; 2888 return true; 2889 } 2890 } 2891 return false; 2892 } 2893 virtual std::string convertConstraint(const char *&Constraint) const { 2894 std::string R; 2895 switch (*Constraint) { 2896 case 'U': // Two-character constraint; add "^" hint for later parsing. 2897 R = std::string("^") + std::string(Constraint, 2); 2898 Constraint++; 2899 break; 2900 case 'p': // 'p' should be translated to 'r' by default. 2901 R = std::string("r"); 2902 break; 2903 default: 2904 return std::string(1, *Constraint); 2905 } 2906 return R; 2907 } 2908 virtual const char *getClobbers() const { 2909 // FIXME: Is this really right? 2910 return ""; 2911 } 2912 }; 2913 2914 const char * const ARMTargetInfo::GCCRegNames[] = { 2915 // Integer registers 2916 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 2917 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 2918 2919 // Float registers 2920 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2921 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2922 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2923 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2924 2925 // Double registers 2926 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 2927 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 2928 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 2929 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 2930 2931 // Quad registers 2932 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 2933 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 2934 }; 2935 2936 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 2937 unsigned &NumNames) const { 2938 Names = GCCRegNames; 2939 NumNames = llvm::array_lengthof(GCCRegNames); 2940 } 2941 2942 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 2943 { { "a1" }, "r0" }, 2944 { { "a2" }, "r1" }, 2945 { { "a3" }, "r2" }, 2946 { { "a4" }, "r3" }, 2947 { { "v1" }, "r4" }, 2948 { { "v2" }, "r5" }, 2949 { { "v3" }, "r6" }, 2950 { { "v4" }, "r7" }, 2951 { { "v5" }, "r8" }, 2952 { { "v6", "rfp" }, "r9" }, 2953 { { "sl" }, "r10" }, 2954 { { "fp" }, "r11" }, 2955 { { "ip" }, "r12" }, 2956 { { "r13" }, "sp" }, 2957 { { "r14" }, "lr" }, 2958 { { "r15" }, "pc" }, 2959 // The S, D and Q registers overlap, but aren't really aliases; we 2960 // don't want to substitute one of these for a different-sized one. 2961 }; 2962 2963 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 2964 unsigned &NumAliases) const { 2965 Aliases = GCCRegAliases; 2966 NumAliases = llvm::array_lengthof(GCCRegAliases); 2967 } 2968 2969 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 2970 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 2971 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 2972 ALL_LANGUAGES }, 2973 #include "clang/Basic/BuiltinsARM.def" 2974 }; 2975 } // end anonymous namespace. 2976 2977 namespace { 2978 class DarwinARMTargetInfo : 2979 public DarwinTargetInfo<ARMTargetInfo> { 2980 protected: 2981 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 2982 MacroBuilder &Builder) const { 2983 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 2984 } 2985 2986 public: 2987 DarwinARMTargetInfo(const std::string& triple) 2988 : DarwinTargetInfo<ARMTargetInfo>(triple) { 2989 HasAlignMac68kSupport = true; 2990 // iOS always has 64-bit atomic instructions. 2991 // FIXME: This should be based off of the target features in ARMTargetInfo. 2992 MaxAtomicInlineWidth = 64; 2993 } 2994 }; 2995 } // end anonymous namespace. 2996 2997 2998 namespace { 2999 // Hexagon abstract base class 3000 class HexagonTargetInfo : public TargetInfo { 3001 static const Builtin::Info BuiltinInfo[]; 3002 static const char * const GCCRegNames[]; 3003 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3004 std::string CPU; 3005 public: 3006 HexagonTargetInfo(const std::string& triple) : TargetInfo(triple) { 3007 BigEndian = false; 3008 DescriptionString = ("e-p:32:32:32-" 3009 "i64:64:64-i32:32:32-i16:16:16-i1:32:32" 3010 "f64:64:64-f32:32:32-a0:0-n32"); 3011 3012 // {} in inline assembly are packet specifiers, not assembly variant 3013 // specifiers. 3014 NoAsmVariants = true; 3015 } 3016 3017 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3018 unsigned &NumRecords) const { 3019 Records = BuiltinInfo; 3020 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 3021 } 3022 3023 virtual bool validateAsmConstraint(const char *&Name, 3024 TargetInfo::ConstraintInfo &Info) const { 3025 return true; 3026 } 3027 3028 virtual void getTargetDefines(const LangOptions &Opts, 3029 MacroBuilder &Builder) const; 3030 3031 virtual bool hasFeature(StringRef Feature) const { 3032 return Feature == "hexagon"; 3033 } 3034 3035 virtual const char *getVAListDeclaration() const { 3036 return "typedef char* __builtin_va_list;"; 3037 } 3038 virtual void getGCCRegNames(const char * const *&Names, 3039 unsigned &NumNames) const; 3040 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3041 unsigned &NumAliases) const; 3042 virtual const char *getClobbers() const { 3043 return ""; 3044 } 3045 3046 static const char *getHexagonCPUSuffix(StringRef Name) { 3047 return llvm::StringSwitch<const char*>(Name) 3048 .Case("hexagonv2", "2") 3049 .Case("hexagonv3", "3") 3050 .Case("hexagonv4", "4") 3051 .Case("hexagonv5", "5") 3052 .Default(0); 3053 } 3054 3055 virtual bool setCPU(const std::string &Name) { 3056 if (!getHexagonCPUSuffix(Name)) 3057 return false; 3058 3059 CPU = Name; 3060 return true; 3061 } 3062 }; 3063 3064 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 3065 MacroBuilder &Builder) const { 3066 Builder.defineMacro("qdsp6"); 3067 Builder.defineMacro("__qdsp6", "1"); 3068 Builder.defineMacro("__qdsp6__", "1"); 3069 3070 Builder.defineMacro("hexagon"); 3071 Builder.defineMacro("__hexagon", "1"); 3072 Builder.defineMacro("__hexagon__", "1"); 3073 3074 if(CPU == "hexagonv1") { 3075 Builder.defineMacro("__HEXAGON_V1__"); 3076 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 3077 if(Opts.HexagonQdsp6Compat) { 3078 Builder.defineMacro("__QDSP6_V1__"); 3079 Builder.defineMacro("__QDSP6_ARCH__", "1"); 3080 } 3081 } 3082 else if(CPU == "hexagonv2") { 3083 Builder.defineMacro("__HEXAGON_V2__"); 3084 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 3085 if(Opts.HexagonQdsp6Compat) { 3086 Builder.defineMacro("__QDSP6_V2__"); 3087 Builder.defineMacro("__QDSP6_ARCH__", "2"); 3088 } 3089 } 3090 else if(CPU == "hexagonv3") { 3091 Builder.defineMacro("__HEXAGON_V3__"); 3092 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 3093 if(Opts.HexagonQdsp6Compat) { 3094 Builder.defineMacro("__QDSP6_V3__"); 3095 Builder.defineMacro("__QDSP6_ARCH__", "3"); 3096 } 3097 } 3098 else if(CPU == "hexagonv4") { 3099 Builder.defineMacro("__HEXAGON_V4__"); 3100 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 3101 if(Opts.HexagonQdsp6Compat) { 3102 Builder.defineMacro("__QDSP6_V4__"); 3103 Builder.defineMacro("__QDSP6_ARCH__", "4"); 3104 } 3105 } 3106 else if(CPU == "hexagonv5") { 3107 Builder.defineMacro("__HEXAGON_V5__"); 3108 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 3109 if(Opts.HexagonQdsp6Compat) { 3110 Builder.defineMacro("__QDSP6_V5__"); 3111 Builder.defineMacro("__QDSP6_ARCH__", "5"); 3112 } 3113 } 3114 } 3115 3116 const char * const HexagonTargetInfo::GCCRegNames[] = { 3117 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3118 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 3119 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 3120 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 3121 "p0", "p1", "p2", "p3", 3122 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 3123 }; 3124 3125 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 3126 unsigned &NumNames) const { 3127 Names = GCCRegNames; 3128 NumNames = llvm::array_lengthof(GCCRegNames); 3129 } 3130 3131 3132 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 3133 { { "sp" }, "r29" }, 3134 { { "fp" }, "r30" }, 3135 { { "lr" }, "r31" }, 3136 }; 3137 3138 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3139 unsigned &NumAliases) const { 3140 Aliases = GCCRegAliases; 3141 NumAliases = llvm::array_lengthof(GCCRegAliases); 3142 } 3143 3144 3145 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 3146 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3147 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3148 ALL_LANGUAGES }, 3149 #include "clang/Basic/BuiltinsHexagon.def" 3150 }; 3151 } 3152 3153 3154 namespace { 3155 class SparcV8TargetInfo : public TargetInfo { 3156 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3157 static const char * const GCCRegNames[]; 3158 bool SoftFloat; 3159 public: 3160 SparcV8TargetInfo(const std::string& triple) : TargetInfo(triple) { 3161 // FIXME: Support Sparc quad-precision long double? 3162 BigEndian = false; 3163 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3164 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"; 3165 } 3166 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 3167 StringRef Name, 3168 bool Enabled) const { 3169 if (Name == "soft-float") 3170 Features[Name] = Enabled; 3171 else 3172 return false; 3173 3174 return true; 3175 } 3176 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 3177 SoftFloat = false; 3178 for (unsigned i = 0, e = Features.size(); i != e; ++i) 3179 if (Features[i] == "+soft-float") 3180 SoftFloat = true; 3181 } 3182 virtual void getTargetDefines(const LangOptions &Opts, 3183 MacroBuilder &Builder) const { 3184 DefineStd(Builder, "sparc", Opts); 3185 Builder.defineMacro("__sparcv8"); 3186 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3187 3188 if (SoftFloat) 3189 Builder.defineMacro("SOFT_FLOAT", "1"); 3190 } 3191 3192 virtual bool hasFeature(StringRef Feature) const { 3193 return llvm::StringSwitch<bool>(Feature) 3194 .Case("softfloat", SoftFloat) 3195 .Case("sparc", true) 3196 .Default(false); 3197 } 3198 3199 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3200 unsigned &NumRecords) const { 3201 // FIXME: Implement! 3202 } 3203 virtual const char *getVAListDeclaration() const { 3204 return "typedef void* __builtin_va_list;"; 3205 } 3206 virtual void getGCCRegNames(const char * const *&Names, 3207 unsigned &NumNames) const; 3208 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3209 unsigned &NumAliases) const; 3210 virtual bool validateAsmConstraint(const char *&Name, 3211 TargetInfo::ConstraintInfo &info) const { 3212 // FIXME: Implement! 3213 return false; 3214 } 3215 virtual const char *getClobbers() const { 3216 // FIXME: Implement! 3217 return ""; 3218 } 3219 }; 3220 3221 const char * const SparcV8TargetInfo::GCCRegNames[] = { 3222 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3223 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 3224 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 3225 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 3226 }; 3227 3228 void SparcV8TargetInfo::getGCCRegNames(const char * const *&Names, 3229 unsigned &NumNames) const { 3230 Names = GCCRegNames; 3231 NumNames = llvm::array_lengthof(GCCRegNames); 3232 } 3233 3234 const TargetInfo::GCCRegAlias SparcV8TargetInfo::GCCRegAliases[] = { 3235 { { "g0" }, "r0" }, 3236 { { "g1" }, "r1" }, 3237 { { "g2" }, "r2" }, 3238 { { "g3" }, "r3" }, 3239 { { "g4" }, "r4" }, 3240 { { "g5" }, "r5" }, 3241 { { "g6" }, "r6" }, 3242 { { "g7" }, "r7" }, 3243 { { "o0" }, "r8" }, 3244 { { "o1" }, "r9" }, 3245 { { "o2" }, "r10" }, 3246 { { "o3" }, "r11" }, 3247 { { "o4" }, "r12" }, 3248 { { "o5" }, "r13" }, 3249 { { "o6", "sp" }, "r14" }, 3250 { { "o7" }, "r15" }, 3251 { { "l0" }, "r16" }, 3252 { { "l1" }, "r17" }, 3253 { { "l2" }, "r18" }, 3254 { { "l3" }, "r19" }, 3255 { { "l4" }, "r20" }, 3256 { { "l5" }, "r21" }, 3257 { { "l6" }, "r22" }, 3258 { { "l7" }, "r23" }, 3259 { { "i0" }, "r24" }, 3260 { { "i1" }, "r25" }, 3261 { { "i2" }, "r26" }, 3262 { { "i3" }, "r27" }, 3263 { { "i4" }, "r28" }, 3264 { { "i5" }, "r29" }, 3265 { { "i6", "fp" }, "r30" }, 3266 { { "i7" }, "r31" }, 3267 }; 3268 3269 void SparcV8TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3270 unsigned &NumAliases) const { 3271 Aliases = GCCRegAliases; 3272 NumAliases = llvm::array_lengthof(GCCRegAliases); 3273 } 3274 } // end anonymous namespace. 3275 3276 namespace { 3277 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 3278 public: 3279 AuroraUXSparcV8TargetInfo(const std::string& triple) : 3280 AuroraUXTargetInfo<SparcV8TargetInfo>(triple) { 3281 SizeType = UnsignedInt; 3282 PtrDiffType = SignedInt; 3283 } 3284 }; 3285 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 3286 public: 3287 SolarisSparcV8TargetInfo(const std::string& triple) : 3288 SolarisTargetInfo<SparcV8TargetInfo>(triple) { 3289 SizeType = UnsignedInt; 3290 PtrDiffType = SignedInt; 3291 } 3292 }; 3293 } // end anonymous namespace. 3294 3295 namespace { 3296 class MSP430TargetInfo : public TargetInfo { 3297 static const char * const GCCRegNames[]; 3298 public: 3299 MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) { 3300 BigEndian = false; 3301 TLSSupported = false; 3302 IntWidth = 16; IntAlign = 16; 3303 LongWidth = 32; LongLongWidth = 64; 3304 LongAlign = LongLongAlign = 16; 3305 PointerWidth = 16; PointerAlign = 16; 3306 SuitableAlign = 16; 3307 SizeType = UnsignedInt; 3308 IntMaxType = SignedLong; 3309 UIntMaxType = UnsignedLong; 3310 IntPtrType = SignedShort; 3311 PtrDiffType = SignedInt; 3312 SigAtomicType = SignedLong; 3313 DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"; 3314 } 3315 virtual void getTargetDefines(const LangOptions &Opts, 3316 MacroBuilder &Builder) const { 3317 Builder.defineMacro("MSP430"); 3318 Builder.defineMacro("__MSP430__"); 3319 // FIXME: defines for different 'flavours' of MCU 3320 } 3321 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3322 unsigned &NumRecords) const { 3323 // FIXME: Implement. 3324 Records = 0; 3325 NumRecords = 0; 3326 } 3327 virtual bool hasFeature(StringRef Feature) const { 3328 return Feature == "msp430"; 3329 } 3330 virtual void getGCCRegNames(const char * const *&Names, 3331 unsigned &NumNames) const; 3332 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3333 unsigned &NumAliases) const { 3334 // No aliases. 3335 Aliases = 0; 3336 NumAliases = 0; 3337 } 3338 virtual bool validateAsmConstraint(const char *&Name, 3339 TargetInfo::ConstraintInfo &info) const { 3340 // No target constraints for now. 3341 return false; 3342 } 3343 virtual const char *getClobbers() const { 3344 // FIXME: Is this really right? 3345 return ""; 3346 } 3347 virtual const char *getVAListDeclaration() const { 3348 // FIXME: implement 3349 return "typedef char* __builtin_va_list;"; 3350 } 3351 }; 3352 3353 const char * const MSP430TargetInfo::GCCRegNames[] = { 3354 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3355 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 3356 }; 3357 3358 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 3359 unsigned &NumNames) const { 3360 Names = GCCRegNames; 3361 NumNames = llvm::array_lengthof(GCCRegNames); 3362 } 3363 } 3364 3365 namespace { 3366 3367 // LLVM and Clang cannot be used directly to output native binaries for 3368 // target, but is used to compile C code to llvm bitcode with correct 3369 // type and alignment information. 3370 // 3371 // TCE uses the llvm bitcode as input and uses it for generating customized 3372 // target processor and program binary. TCE co-design environment is 3373 // publicly available in http://tce.cs.tut.fi 3374 3375 static const unsigned TCEOpenCLAddrSpaceMap[] = { 3376 3, // opencl_global 3377 4, // opencl_local 3378 5, // opencl_constant 3379 0, // cuda_device 3380 0, // cuda_constant 3381 0 // cuda_shared 3382 }; 3383 3384 class TCETargetInfo : public TargetInfo{ 3385 public: 3386 TCETargetInfo(const std::string& triple) : TargetInfo(triple) { 3387 TLSSupported = false; 3388 IntWidth = 32; 3389 LongWidth = LongLongWidth = 32; 3390 PointerWidth = 32; 3391 IntAlign = 32; 3392 LongAlign = LongLongAlign = 32; 3393 PointerAlign = 32; 3394 SuitableAlign = 32; 3395 SizeType = UnsignedInt; 3396 IntMaxType = SignedLong; 3397 UIntMaxType = UnsignedLong; 3398 IntPtrType = SignedInt; 3399 PtrDiffType = SignedInt; 3400 FloatWidth = 32; 3401 FloatAlign = 32; 3402 DoubleWidth = 32; 3403 DoubleAlign = 32; 3404 LongDoubleWidth = 32; 3405 LongDoubleAlign = 32; 3406 FloatFormat = &llvm::APFloat::IEEEsingle; 3407 DoubleFormat = &llvm::APFloat::IEEEsingle; 3408 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 3409 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-" 3410 "i16:16:32-i32:32:32-i64:32:32-" 3411 "f32:32:32-f64:32:32-v64:32:32-" 3412 "v128:32:32-a0:0:32-n32"; 3413 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 3414 } 3415 3416 virtual void getTargetDefines(const LangOptions &Opts, 3417 MacroBuilder &Builder) const { 3418 DefineStd(Builder, "tce", Opts); 3419 Builder.defineMacro("__TCE__"); 3420 Builder.defineMacro("__TCE_V1__"); 3421 } 3422 virtual bool hasFeature(StringRef Feature) const { 3423 return Feature == "tce"; 3424 } 3425 3426 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3427 unsigned &NumRecords) const {} 3428 virtual const char *getClobbers() const { 3429 return ""; 3430 } 3431 virtual const char *getVAListDeclaration() const { 3432 return "typedef void* __builtin_va_list;"; 3433 } 3434 virtual void getGCCRegNames(const char * const *&Names, 3435 unsigned &NumNames) const {} 3436 virtual bool validateAsmConstraint(const char *&Name, 3437 TargetInfo::ConstraintInfo &info) const { 3438 return true; 3439 } 3440 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3441 unsigned &NumAliases) const {} 3442 }; 3443 } 3444 3445 namespace { 3446 class MipsTargetInfoBase : public TargetInfo { 3447 std::string CPU; 3448 bool SoftFloat; 3449 bool SingleFloat; 3450 3451 protected: 3452 std::string ABI; 3453 3454 public: 3455 MipsTargetInfoBase(const std::string& triple, 3456 const std::string& ABIStr, 3457 const std::string& CPUStr) 3458 : TargetInfo(triple), 3459 CPU(CPUStr), 3460 SoftFloat(false), SingleFloat(false), 3461 ABI(ABIStr) 3462 {} 3463 3464 virtual const char *getABI() const { return ABI.c_str(); } 3465 virtual bool setABI(const std::string &Name) = 0; 3466 virtual bool setCPU(const std::string &Name) { 3467 CPU = Name; 3468 return true; 3469 } 3470 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3471 Features[ABI] = true; 3472 Features[CPU] = true; 3473 } 3474 3475 virtual void getArchDefines(const LangOptions &Opts, 3476 MacroBuilder &Builder) const { 3477 if (SoftFloat) 3478 Builder.defineMacro("__mips_soft_float", Twine(1)); 3479 else if (SingleFloat) 3480 Builder.defineMacro("__mips_single_float", Twine(1)); 3481 else if (!SoftFloat && !SingleFloat) 3482 Builder.defineMacro("__mips_hard_float", Twine(1)); 3483 else 3484 llvm_unreachable("Invalid float ABI for Mips."); 3485 3486 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 3487 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 3488 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 3489 } 3490 3491 virtual void getTargetDefines(const LangOptions &Opts, 3492 MacroBuilder &Builder) const = 0; 3493 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3494 unsigned &NumRecords) const { 3495 // FIXME: Implement! 3496 } 3497 virtual bool hasFeature(StringRef Feature) const { 3498 return Feature == "mips"; 3499 } 3500 virtual const char *getVAListDeclaration() const { 3501 return "typedef void* __builtin_va_list;"; 3502 } 3503 virtual void getGCCRegNames(const char * const *&Names, 3504 unsigned &NumNames) const { 3505 static const char * const GCCRegNames[] = { 3506 // CPU register names 3507 // Must match second column of GCCRegAliases 3508 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 3509 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 3510 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 3511 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 3512 // Floating point register names 3513 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 3514 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 3515 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 3516 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 3517 // Hi/lo and condition register names 3518 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 3519 "$fcc5","$fcc6","$fcc7" 3520 }; 3521 Names = GCCRegNames; 3522 NumNames = llvm::array_lengthof(GCCRegNames); 3523 } 3524 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3525 unsigned &NumAliases) const = 0; 3526 virtual bool validateAsmConstraint(const char *&Name, 3527 TargetInfo::ConstraintInfo &Info) const { 3528 switch (*Name) { 3529 default: 3530 return false; 3531 3532 case 'r': // CPU registers. 3533 case 'd': // Equivalent to "r" unless generating MIPS16 code. 3534 case 'y': // Equivalent to "r", backwards compatibility only. 3535 case 'f': // floating-point registers. 3536 case 'c': // $25 for indirect jumps 3537 case 'l': // lo register 3538 case 'x': // hilo register pair 3539 Info.setAllowsRegister(); 3540 return true; 3541 } 3542 } 3543 3544 virtual const char *getClobbers() const { 3545 // FIXME: Implement! 3546 return ""; 3547 } 3548 3549 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 3550 StringRef Name, 3551 bool Enabled) const { 3552 if (Name == "soft-float" || Name == "single-float" || 3553 Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" || 3554 Name == "mips32" || Name == "mips32r2" || 3555 Name == "mips64" || Name == "mips64r2") { 3556 Features[Name] = Enabled; 3557 return true; 3558 } 3559 return false; 3560 } 3561 3562 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 3563 SoftFloat = false; 3564 SingleFloat = false; 3565 3566 for (std::vector<std::string>::iterator it = Features.begin(), 3567 ie = Features.end(); it != ie; ++it) { 3568 if (*it == "+single-float") { 3569 SingleFloat = true; 3570 break; 3571 } 3572 3573 if (*it == "+soft-float") { 3574 SoftFloat = true; 3575 // This option is front-end specific. 3576 // Do not need to pass it to the backend. 3577 Features.erase(it); 3578 break; 3579 } 3580 } 3581 } 3582 }; 3583 3584 class Mips32TargetInfoBase : public MipsTargetInfoBase { 3585 public: 3586 Mips32TargetInfoBase(const std::string& triple) : 3587 MipsTargetInfoBase(triple, "o32", "mips32") { 3588 SizeType = UnsignedInt; 3589 PtrDiffType = SignedInt; 3590 } 3591 virtual bool setABI(const std::string &Name) { 3592 if ((Name == "o32") || (Name == "eabi")) { 3593 ABI = Name; 3594 return true; 3595 } else 3596 return false; 3597 } 3598 virtual void getArchDefines(const LangOptions &Opts, 3599 MacroBuilder &Builder) const { 3600 MipsTargetInfoBase::getArchDefines(Opts, Builder); 3601 3602 if (ABI == "o32") { 3603 Builder.defineMacro("__mips_o32"); 3604 Builder.defineMacro("_ABIO32", "1"); 3605 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 3606 } 3607 else if (ABI == "eabi") 3608 Builder.defineMacro("__mips_eabi"); 3609 else 3610 llvm_unreachable("Invalid ABI for Mips32."); 3611 } 3612 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3613 unsigned &NumAliases) const { 3614 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 3615 { { "at" }, "$1" }, 3616 { { "v0" }, "$2" }, 3617 { { "v1" }, "$3" }, 3618 { { "a0" }, "$4" }, 3619 { { "a1" }, "$5" }, 3620 { { "a2" }, "$6" }, 3621 { { "a3" }, "$7" }, 3622 { { "t0" }, "$8" }, 3623 { { "t1" }, "$9" }, 3624 { { "t2" }, "$10" }, 3625 { { "t3" }, "$11" }, 3626 { { "t4" }, "$12" }, 3627 { { "t5" }, "$13" }, 3628 { { "t6" }, "$14" }, 3629 { { "t7" }, "$15" }, 3630 { { "s0" }, "$16" }, 3631 { { "s1" }, "$17" }, 3632 { { "s2" }, "$18" }, 3633 { { "s3" }, "$19" }, 3634 { { "s4" }, "$20" }, 3635 { { "s5" }, "$21" }, 3636 { { "s6" }, "$22" }, 3637 { { "s7" }, "$23" }, 3638 { { "t8" }, "$24" }, 3639 { { "t9" }, "$25" }, 3640 { { "k0" }, "$26" }, 3641 { { "k1" }, "$27" }, 3642 { { "gp" }, "$28" }, 3643 { { "sp","$sp" }, "$29" }, 3644 { { "fp","$fp" }, "$30" }, 3645 { { "ra" }, "$31" } 3646 }; 3647 Aliases = GCCRegAliases; 3648 NumAliases = llvm::array_lengthof(GCCRegAliases); 3649 } 3650 }; 3651 3652 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 3653 public: 3654 Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) { 3655 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 3656 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"; 3657 } 3658 virtual void getTargetDefines(const LangOptions &Opts, 3659 MacroBuilder &Builder) const { 3660 DefineStd(Builder, "mips", Opts); 3661 Builder.defineMacro("_mips"); 3662 DefineStd(Builder, "MIPSEB", Opts); 3663 Builder.defineMacro("_MIPSEB"); 3664 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3665 getArchDefines(Opts, Builder); 3666 } 3667 }; 3668 3669 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 3670 public: 3671 Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) { 3672 BigEndian = false; 3673 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 3674 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"; 3675 } 3676 virtual void getTargetDefines(const LangOptions &Opts, 3677 MacroBuilder &Builder) const { 3678 DefineStd(Builder, "mips", Opts); 3679 Builder.defineMacro("_mips"); 3680 DefineStd(Builder, "MIPSEL", Opts); 3681 Builder.defineMacro("_MIPSEL"); 3682 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3683 getArchDefines(Opts, Builder); 3684 } 3685 }; 3686 3687 class Mips64TargetInfoBase : public MipsTargetInfoBase { 3688 virtual void SetDescriptionString(const std::string &Name) = 0; 3689 public: 3690 Mips64TargetInfoBase(const std::string& triple) : 3691 MipsTargetInfoBase(triple, "n64", "mips64") { 3692 LongWidth = LongAlign = 64; 3693 PointerWidth = PointerAlign = 64; 3694 LongDoubleWidth = LongDoubleAlign = 128; 3695 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3696 SuitableAlign = 128; 3697 } 3698 virtual bool setABI(const std::string &Name) { 3699 SetDescriptionString(Name); 3700 3701 if (Name != "n32" && Name != "n64") 3702 return false; 3703 3704 ABI = Name; 3705 3706 if (Name == "n32") { 3707 LongWidth = LongAlign = 32; 3708 PointerWidth = PointerAlign = 32; 3709 } 3710 3711 return true; 3712 } 3713 virtual void getArchDefines(const LangOptions &Opts, 3714 MacroBuilder &Builder) const { 3715 MipsTargetInfoBase::getArchDefines(Opts, Builder); 3716 3717 if (ABI == "n32") { 3718 Builder.defineMacro("__mips_n32"); 3719 Builder.defineMacro("_ABIN32", "2"); 3720 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 3721 } 3722 else if (ABI == "n64") { 3723 Builder.defineMacro("__mips_n64"); 3724 Builder.defineMacro("_ABI64", "3"); 3725 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 3726 } 3727 else 3728 llvm_unreachable("Invalid ABI for Mips64."); 3729 } 3730 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3731 unsigned &NumAliases) const { 3732 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 3733 { { "at" }, "$1" }, 3734 { { "v0" }, "$2" }, 3735 { { "v1" }, "$3" }, 3736 { { "a0" }, "$4" }, 3737 { { "a1" }, "$5" }, 3738 { { "a2" }, "$6" }, 3739 { { "a3" }, "$7" }, 3740 { { "a4" }, "$8" }, 3741 { { "a5" }, "$9" }, 3742 { { "a6" }, "$10" }, 3743 { { "a7" }, "$11" }, 3744 { { "t0" }, "$12" }, 3745 { { "t1" }, "$13" }, 3746 { { "t2" }, "$14" }, 3747 { { "t3" }, "$15" }, 3748 { { "s0" }, "$16" }, 3749 { { "s1" }, "$17" }, 3750 { { "s2" }, "$18" }, 3751 { { "s3" }, "$19" }, 3752 { { "s4" }, "$20" }, 3753 { { "s5" }, "$21" }, 3754 { { "s6" }, "$22" }, 3755 { { "s7" }, "$23" }, 3756 { { "t8" }, "$24" }, 3757 { { "t9" }, "$25" }, 3758 { { "k0" }, "$26" }, 3759 { { "k1" }, "$27" }, 3760 { { "gp" }, "$28" }, 3761 { { "sp","$sp" }, "$29" }, 3762 { { "fp","$fp" }, "$30" }, 3763 { { "ra" }, "$31" } 3764 }; 3765 Aliases = GCCRegAliases; 3766 NumAliases = llvm::array_lengthof(GCCRegAliases); 3767 } 3768 }; 3769 3770 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 3771 virtual void SetDescriptionString(const std::string &Name) { 3772 // Change DescriptionString only if ABI is n32. 3773 if (Name == "n32") 3774 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 3775 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 3776 "v64:64:64-n32"; 3777 } 3778 public: 3779 Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) { 3780 // Default ABI is n64. 3781 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 3782 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 3783 "v64:64:64-n32"; 3784 } 3785 virtual void getTargetDefines(const LangOptions &Opts, 3786 MacroBuilder &Builder) const { 3787 DefineStd(Builder, "mips", Opts); 3788 Builder.defineMacro("_mips"); 3789 DefineStd(Builder, "MIPSEB", Opts); 3790 Builder.defineMacro("_MIPSEB"); 3791 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3792 getArchDefines(Opts, Builder); 3793 } 3794 }; 3795 3796 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 3797 virtual void SetDescriptionString(const std::string &Name) { 3798 // Change DescriptionString only if ABI is n32. 3799 if (Name == "n32") 3800 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 3801 "i64:64:64-f32:32:32-f64:64:64-f128:128:128" 3802 "-v64:64:64-n32"; 3803 } 3804 public: 3805 Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) { 3806 // Default ABI is n64. 3807 BigEndian = false; 3808 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 3809 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 3810 "v64:64:64-n32"; 3811 } 3812 virtual void getTargetDefines(const LangOptions &Opts, 3813 MacroBuilder &Builder) const { 3814 DefineStd(Builder, "mips", Opts); 3815 Builder.defineMacro("_mips"); 3816 DefineStd(Builder, "MIPSEL", Opts); 3817 Builder.defineMacro("_MIPSEL"); 3818 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3819 getArchDefines(Opts, Builder); 3820 } 3821 }; 3822 } // end anonymous namespace. 3823 3824 namespace { 3825 class PNaClTargetInfo : public TargetInfo { 3826 public: 3827 PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) { 3828 BigEndian = false; 3829 this->UserLabelPrefix = ""; 3830 this->LongAlign = 32; 3831 this->LongWidth = 32; 3832 this->PointerAlign = 32; 3833 this->PointerWidth = 32; 3834 this->IntMaxType = TargetInfo::SignedLongLong; 3835 this->UIntMaxType = TargetInfo::UnsignedLongLong; 3836 this->Int64Type = TargetInfo::SignedLongLong; 3837 this->DoubleAlign = 64; 3838 this->LongDoubleWidth = 64; 3839 this->LongDoubleAlign = 64; 3840 this->SizeType = TargetInfo::UnsignedInt; 3841 this->PtrDiffType = TargetInfo::SignedInt; 3842 this->IntPtrType = TargetInfo::SignedInt; 3843 this->RegParmMax = 2; 3844 DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 3845 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 3846 } 3847 3848 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3849 } 3850 virtual void getArchDefines(const LangOptions &Opts, 3851 MacroBuilder &Builder) const { 3852 Builder.defineMacro("__le32__"); 3853 Builder.defineMacro("__pnacl__"); 3854 } 3855 virtual void getTargetDefines(const LangOptions &Opts, 3856 MacroBuilder &Builder) const { 3857 DefineStd(Builder, "unix", Opts); 3858 Builder.defineMacro("__ELF__"); 3859 if (Opts.POSIXThreads) 3860 Builder.defineMacro("_REENTRANT"); 3861 if (Opts.CPlusPlus) 3862 Builder.defineMacro("_GNU_SOURCE"); 3863 3864 Builder.defineMacro("__LITTLE_ENDIAN__"); 3865 Builder.defineMacro("__native_client__"); 3866 getArchDefines(Opts, Builder); 3867 } 3868 virtual bool hasFeature(StringRef Feature) const { 3869 return Feature == "pnacl"; 3870 } 3871 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3872 unsigned &NumRecords) const { 3873 } 3874 virtual const char *getVAListDeclaration() const { 3875 return "typedef int __builtin_va_list[4];"; 3876 } 3877 virtual void getGCCRegNames(const char * const *&Names, 3878 unsigned &NumNames) const; 3879 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3880 unsigned &NumAliases) const; 3881 virtual bool validateAsmConstraint(const char *&Name, 3882 TargetInfo::ConstraintInfo &Info) const { 3883 return false; 3884 } 3885 3886 virtual const char *getClobbers() const { 3887 return ""; 3888 } 3889 }; 3890 3891 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 3892 unsigned &NumNames) const { 3893 Names = NULL; 3894 NumNames = 0; 3895 } 3896 3897 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3898 unsigned &NumAliases) const { 3899 Aliases = NULL; 3900 NumAliases = 0; 3901 } 3902 } // end anonymous namespace. 3903 3904 3905 //===----------------------------------------------------------------------===// 3906 // Driver code 3907 //===----------------------------------------------------------------------===// 3908 3909 static TargetInfo *AllocateTarget(const std::string &T) { 3910 llvm::Triple Triple(T); 3911 llvm::Triple::OSType os = Triple.getOS(); 3912 3913 switch (Triple.getArch()) { 3914 default: 3915 return NULL; 3916 3917 case llvm::Triple::hexagon: 3918 return new HexagonTargetInfo(T); 3919 3920 case llvm::Triple::arm: 3921 case llvm::Triple::thumb: 3922 if (Triple.isOSDarwin()) 3923 return new DarwinARMTargetInfo(T); 3924 3925 switch (os) { 3926 case llvm::Triple::Linux: 3927 return new LinuxTargetInfo<ARMTargetInfo>(T); 3928 case llvm::Triple::FreeBSD: 3929 return new FreeBSDTargetInfo<ARMTargetInfo>(T); 3930 case llvm::Triple::NetBSD: 3931 return new NetBSDTargetInfo<ARMTargetInfo>(T); 3932 case llvm::Triple::RTEMS: 3933 return new RTEMSTargetInfo<ARMTargetInfo>(T); 3934 default: 3935 return new ARMTargetInfo(T); 3936 } 3937 3938 case llvm::Triple::msp430: 3939 return new MSP430TargetInfo(T); 3940 3941 case llvm::Triple::mips: 3942 switch (os) { 3943 case llvm::Triple::Linux: 3944 return new LinuxTargetInfo<Mips32EBTargetInfo>(T); 3945 case llvm::Triple::RTEMS: 3946 return new RTEMSTargetInfo<Mips32EBTargetInfo>(T); 3947 case llvm::Triple::FreeBSD: 3948 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T); 3949 case llvm::Triple::NetBSD: 3950 return new NetBSDTargetInfo<Mips32EBTargetInfo>(T); 3951 default: 3952 return new Mips32EBTargetInfo(T); 3953 } 3954 3955 case llvm::Triple::mipsel: 3956 switch (os) { 3957 case llvm::Triple::Linux: 3958 return new LinuxTargetInfo<Mips32ELTargetInfo>(T); 3959 case llvm::Triple::RTEMS: 3960 return new RTEMSTargetInfo<Mips32ELTargetInfo>(T); 3961 case llvm::Triple::FreeBSD: 3962 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T); 3963 case llvm::Triple::NetBSD: 3964 return new NetBSDTargetInfo<Mips32ELTargetInfo>(T); 3965 default: 3966 return new Mips32ELTargetInfo(T); 3967 } 3968 3969 case llvm::Triple::mips64: 3970 switch (os) { 3971 case llvm::Triple::Linux: 3972 return new LinuxTargetInfo<Mips64EBTargetInfo>(T); 3973 case llvm::Triple::RTEMS: 3974 return new RTEMSTargetInfo<Mips64EBTargetInfo>(T); 3975 case llvm::Triple::FreeBSD: 3976 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T); 3977 case llvm::Triple::NetBSD: 3978 return new NetBSDTargetInfo<Mips64EBTargetInfo>(T); 3979 default: 3980 return new Mips64EBTargetInfo(T); 3981 } 3982 3983 case llvm::Triple::mips64el: 3984 switch (os) { 3985 case llvm::Triple::Linux: 3986 return new LinuxTargetInfo<Mips64ELTargetInfo>(T); 3987 case llvm::Triple::RTEMS: 3988 return new RTEMSTargetInfo<Mips64ELTargetInfo>(T); 3989 case llvm::Triple::FreeBSD: 3990 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T); 3991 case llvm::Triple::NetBSD: 3992 return new NetBSDTargetInfo<Mips64ELTargetInfo>(T); 3993 default: 3994 return new Mips64ELTargetInfo(T); 3995 } 3996 3997 case llvm::Triple::le32: 3998 switch (os) { 3999 case llvm::Triple::NativeClient: 4000 return new PNaClTargetInfo(T); 4001 default: 4002 return NULL; 4003 } 4004 4005 case llvm::Triple::ppc: 4006 if (Triple.isOSDarwin()) 4007 return new DarwinPPC32TargetInfo(T); 4008 switch (os) { 4009 case llvm::Triple::Linux: 4010 return new LinuxTargetInfo<PPC32TargetInfo>(T); 4011 case llvm::Triple::FreeBSD: 4012 return new FreeBSDTargetInfo<PPC32TargetInfo>(T); 4013 case llvm::Triple::NetBSD: 4014 return new NetBSDTargetInfo<PPC32TargetInfo>(T); 4015 case llvm::Triple::RTEMS: 4016 return new RTEMSTargetInfo<PPC32TargetInfo>(T); 4017 default: 4018 return new PPC32TargetInfo(T); 4019 } 4020 4021 case llvm::Triple::ppc64: 4022 if (Triple.isOSDarwin()) 4023 return new DarwinPPC64TargetInfo(T); 4024 switch (os) { 4025 case llvm::Triple::Linux: 4026 return new LinuxTargetInfo<PPC64TargetInfo>(T); 4027 case llvm::Triple::Lv2: 4028 return new PS3PPUTargetInfo<PPC64TargetInfo>(T); 4029 case llvm::Triple::FreeBSD: 4030 return new FreeBSDTargetInfo<PPC64TargetInfo>(T); 4031 case llvm::Triple::NetBSD: 4032 return new NetBSDTargetInfo<PPC64TargetInfo>(T); 4033 default: 4034 return new PPC64TargetInfo(T); 4035 } 4036 4037 case llvm::Triple::nvptx: 4038 return new NVPTX32TargetInfo(T); 4039 case llvm::Triple::nvptx64: 4040 return new NVPTX64TargetInfo(T); 4041 4042 case llvm::Triple::mblaze: 4043 return new MBlazeTargetInfo(T); 4044 4045 case llvm::Triple::sparc: 4046 switch (os) { 4047 case llvm::Triple::Linux: 4048 return new LinuxTargetInfo<SparcV8TargetInfo>(T); 4049 case llvm::Triple::AuroraUX: 4050 return new AuroraUXSparcV8TargetInfo(T); 4051 case llvm::Triple::Solaris: 4052 return new SolarisSparcV8TargetInfo(T); 4053 case llvm::Triple::NetBSD: 4054 return new NetBSDTargetInfo<SparcV8TargetInfo>(T); 4055 case llvm::Triple::RTEMS: 4056 return new RTEMSTargetInfo<SparcV8TargetInfo>(T); 4057 default: 4058 return new SparcV8TargetInfo(T); 4059 } 4060 4061 // FIXME: Need a real SPU target. 4062 case llvm::Triple::cellspu: 4063 return new PS3SPUTargetInfo<PPC64TargetInfo>(T); 4064 4065 case llvm::Triple::tce: 4066 return new TCETargetInfo(T); 4067 4068 case llvm::Triple::x86: 4069 if (Triple.isOSDarwin()) 4070 return new DarwinI386TargetInfo(T); 4071 4072 switch (os) { 4073 case llvm::Triple::AuroraUX: 4074 return new AuroraUXTargetInfo<X86_32TargetInfo>(T); 4075 case llvm::Triple::Linux: 4076 return new LinuxTargetInfo<X86_32TargetInfo>(T); 4077 case llvm::Triple::DragonFly: 4078 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T); 4079 case llvm::Triple::NetBSD: 4080 return new NetBSDI386TargetInfo(T); 4081 case llvm::Triple::OpenBSD: 4082 return new OpenBSDI386TargetInfo(T); 4083 case llvm::Triple::FreeBSD: 4084 return new FreeBSDTargetInfo<X86_32TargetInfo>(T); 4085 case llvm::Triple::Minix: 4086 return new MinixTargetInfo<X86_32TargetInfo>(T); 4087 case llvm::Triple::Solaris: 4088 return new SolarisTargetInfo<X86_32TargetInfo>(T); 4089 case llvm::Triple::Cygwin: 4090 return new CygwinX86_32TargetInfo(T); 4091 case llvm::Triple::MinGW32: 4092 return new MinGWX86_32TargetInfo(T); 4093 case llvm::Triple::Win32: 4094 return new VisualStudioWindowsX86_32TargetInfo(T); 4095 case llvm::Triple::Haiku: 4096 return new HaikuX86_32TargetInfo(T); 4097 case llvm::Triple::RTEMS: 4098 return new RTEMSX86_32TargetInfo(T); 4099 default: 4100 return new X86_32TargetInfo(T); 4101 } 4102 4103 case llvm::Triple::x86_64: 4104 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO) 4105 return new DarwinX86_64TargetInfo(T); 4106 4107 switch (os) { 4108 case llvm::Triple::AuroraUX: 4109 return new AuroraUXTargetInfo<X86_64TargetInfo>(T); 4110 case llvm::Triple::Linux: 4111 return new LinuxTargetInfo<X86_64TargetInfo>(T); 4112 case llvm::Triple::DragonFly: 4113 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T); 4114 case llvm::Triple::NetBSD: 4115 return new NetBSDTargetInfo<X86_64TargetInfo>(T); 4116 case llvm::Triple::OpenBSD: 4117 return new OpenBSDX86_64TargetInfo(T); 4118 case llvm::Triple::FreeBSD: 4119 return new FreeBSDTargetInfo<X86_64TargetInfo>(T); 4120 case llvm::Triple::Solaris: 4121 return new SolarisTargetInfo<X86_64TargetInfo>(T); 4122 case llvm::Triple::MinGW32: 4123 return new MinGWX86_64TargetInfo(T); 4124 case llvm::Triple::Win32: // This is what Triple.h supports now. 4125 return new VisualStudioWindowsX86_64TargetInfo(T); 4126 default: 4127 return new X86_64TargetInfo(T); 4128 } 4129 } 4130 } 4131 4132 /// CreateTargetInfo - Return the target info object for the specified target 4133 /// triple. 4134 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 4135 TargetOptions &Opts) { 4136 llvm::Triple Triple(Opts.Triple); 4137 4138 // Construct the target 4139 OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str())); 4140 if (!Target) { 4141 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 4142 return 0; 4143 } 4144 4145 // Set the target CPU if specified. 4146 if (!Opts.CPU.empty() && !Target->setCPU(Opts.CPU)) { 4147 Diags.Report(diag::err_target_unknown_cpu) << Opts.CPU; 4148 return 0; 4149 } 4150 4151 // Set the target ABI if specified. 4152 if (!Opts.ABI.empty() && !Target->setABI(Opts.ABI)) { 4153 Diags.Report(diag::err_target_unknown_abi) << Opts.ABI; 4154 return 0; 4155 } 4156 4157 // Set the target C++ ABI. 4158 if (!Opts.CXXABI.empty() && !Target->setCXXABI(Opts.CXXABI)) { 4159 Diags.Report(diag::err_target_unknown_cxxabi) << Opts.CXXABI; 4160 return 0; 4161 } 4162 4163 // Compute the default target features, we need the target to handle this 4164 // because features may have dependencies on one another. 4165 llvm::StringMap<bool> Features; 4166 Target->getDefaultFeatures(Features); 4167 4168 // Apply the user specified deltas. 4169 // First the enables. 4170 for (std::vector<std::string>::const_iterator it = Opts.Features.begin(), 4171 ie = Opts.Features.end(); it != ie; ++it) { 4172 const char *Name = it->c_str(); 4173 4174 if (Name[0] != '+') 4175 continue; 4176 4177 // Apply the feature via the target. 4178 if (!Target->setFeatureEnabled(Features, Name + 1, true)) { 4179 Diags.Report(diag::err_target_invalid_feature) << Name; 4180 return 0; 4181 } 4182 } 4183 4184 // Then the disables. 4185 for (std::vector<std::string>::const_iterator it = Opts.Features.begin(), 4186 ie = Opts.Features.end(); it != ie; ++it) { 4187 const char *Name = it->c_str(); 4188 4189 if (Name[0] == '+') 4190 continue; 4191 4192 // Apply the feature via the target. 4193 if (Name[0] != '-' || 4194 !Target->setFeatureEnabled(Features, Name + 1, false)) { 4195 Diags.Report(diag::err_target_invalid_feature) << Name; 4196 return 0; 4197 } 4198 } 4199 4200 // Add the features to the compile options. 4201 // 4202 // FIXME: If we are completely confident that we have the right set, we only 4203 // need to pass the minuses. 4204 Opts.Features.clear(); 4205 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 4206 ie = Features.end(); it != ie; ++it) 4207 Opts.Features.push_back((it->second ? "+" : "-") + it->first().str()); 4208 Target->HandleTargetFeatures(Opts.Features); 4209 4210 return Target.take(); 4211 } 4212