1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include <algorithm> 31 #include <memory> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const override { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 94 // AddressSanitizer doesn't play well with source fortification, which is on 95 // by default on Darwin. 96 if (Opts.Sanitize.has(SanitizerKind::Address)) 97 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 98 99 if (!Opts.ObjCAutoRefCount) { 100 // __weak is always defined, for use in blocks and with objc pointers. 101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 102 103 // Darwin defines __strong even in C mode (just to nothing). 104 if (Opts.getGC() != LangOptions::NonGC) 105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 106 else 107 Builder.defineMacro("__strong", ""); 108 109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 110 // allow this in C, since one might have block pointers in structs that 111 // are used in pure C code and in Objective-C ARC. 112 Builder.defineMacro("__unsafe_unretained", ""); 113 } 114 115 if (Opts.Static) 116 Builder.defineMacro("__STATIC__"); 117 else 118 Builder.defineMacro("__DYNAMIC__"); 119 120 if (Opts.POSIXThreads) 121 Builder.defineMacro("_REENTRANT"); 122 123 // Get the platform type and version number from the triple. 124 unsigned Maj, Min, Rev; 125 if (Triple.isMacOSX()) { 126 Triple.getMacOSXVersion(Maj, Min, Rev); 127 PlatformName = "macosx"; 128 } else { 129 Triple.getOSVersion(Maj, Min, Rev); 130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 131 } 132 133 // If -target arch-pc-win32-macho option specified, we're 134 // generating code for Win32 ABI. No need to emit 135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 136 if (PlatformName == "win32") { 137 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 138 return; 139 } 140 141 // Set the appropriate OS version define. 142 if (Triple.isiOS()) { 143 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 144 char Str[6]; 145 Str[0] = '0' + Maj; 146 Str[1] = '0' + (Min / 10); 147 Str[2] = '0' + (Min % 10); 148 Str[3] = '0' + (Rev / 10); 149 Str[4] = '0' + (Rev % 10); 150 Str[5] = '\0'; 151 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 152 Str); 153 } else if (Triple.isMacOSX()) { 154 // Note that the Driver allows versions which aren't representable in the 155 // define (because we only get a single digit for the minor and micro 156 // revision numbers). So, we limit them to the maximum representable 157 // version. 158 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[7]; 160 if (Maj < 10 || (Maj == 10 && Min < 10)) { 161 Str[0] = '0' + (Maj / 10); 162 Str[1] = '0' + (Maj % 10); 163 Str[2] = '0' + std::min(Min, 9U); 164 Str[3] = '0' + std::min(Rev, 9U); 165 Str[4] = '\0'; 166 } else { 167 // Handle versions > 10.9. 168 Str[0] = '0' + (Maj / 10); 169 Str[1] = '0' + (Maj % 10); 170 Str[2] = '0' + (Min / 10); 171 Str[3] = '0' + (Min % 10); 172 Str[4] = '0' + (Rev / 10); 173 Str[5] = '0' + (Rev % 10); 174 Str[6] = '\0'; 175 } 176 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 177 } 178 179 // Tell users about the kernel if there is one. 180 if (Triple.isOSDarwin()) 181 Builder.defineMacro("__MACH__"); 182 183 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 184 } 185 186 namespace { 187 // CloudABI Target 188 template <typename Target> 189 class CloudABITargetInfo : public OSTargetInfo<Target> { 190 protected: 191 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 192 MacroBuilder &Builder) const override { 193 Builder.defineMacro("__CloudABI__"); 194 Builder.defineMacro("__ELF__"); 195 196 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 197 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 198 Builder.defineMacro("__STDC_UTF_16__"); 199 Builder.defineMacro("__STDC_UTF_32__"); 200 } 201 202 public: 203 CloudABITargetInfo(const llvm::Triple &Triple) 204 : OSTargetInfo<Target>(Triple) { 205 this->UserLabelPrefix = ""; 206 } 207 }; 208 209 template<typename Target> 210 class DarwinTargetInfo : public OSTargetInfo<Target> { 211 protected: 212 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 213 MacroBuilder &Builder) const override { 214 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 215 this->PlatformMinVersion); 216 } 217 218 public: 219 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 220 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 221 this->MCountName = "\01mcount"; 222 } 223 224 std::string isValidSectionSpecifier(StringRef SR) const override { 225 // Let MCSectionMachO validate this. 226 StringRef Segment, Section; 227 unsigned TAA, StubSize; 228 bool HasTAA; 229 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 230 TAA, HasTAA, StubSize); 231 } 232 233 const char *getStaticInitSectionSpecifier() const override { 234 // FIXME: We should return 0 when building kexts. 235 return "__TEXT,__StaticInit,regular,pure_instructions"; 236 } 237 238 /// Darwin does not support protected visibility. Darwin's "default" 239 /// is very similar to ELF's "protected"; Darwin requires a "weak" 240 /// attribute on declarations that can be dynamically replaced. 241 bool hasProtectedVisibility() const override { 242 return false; 243 } 244 }; 245 246 247 // DragonFlyBSD Target 248 template<typename Target> 249 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 250 protected: 251 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 252 MacroBuilder &Builder) const override { 253 // DragonFly defines; list based off of gcc output 254 Builder.defineMacro("__DragonFly__"); 255 Builder.defineMacro("__DragonFly_cc_version", "100001"); 256 Builder.defineMacro("__ELF__"); 257 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 258 Builder.defineMacro("__tune_i386__"); 259 DefineStd(Builder, "unix", Opts); 260 } 261 public: 262 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 263 : OSTargetInfo<Target>(Triple) { 264 this->UserLabelPrefix = ""; 265 266 switch (Triple.getArch()) { 267 default: 268 case llvm::Triple::x86: 269 case llvm::Triple::x86_64: 270 this->MCountName = ".mcount"; 271 break; 272 } 273 } 274 }; 275 276 // FreeBSD Target 277 template<typename Target> 278 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 279 protected: 280 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 281 MacroBuilder &Builder) const override { 282 // FreeBSD defines; list based off of gcc output 283 284 unsigned Release = Triple.getOSMajorVersion(); 285 if (Release == 0U) 286 Release = 8; 287 288 Builder.defineMacro("__FreeBSD__", Twine(Release)); 289 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 290 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 291 DefineStd(Builder, "unix", Opts); 292 Builder.defineMacro("__ELF__"); 293 294 // On FreeBSD, wchar_t contains the number of the code point as 295 // used by the character set of the locale. These character sets are 296 // not necessarily a superset of ASCII. 297 // 298 // FIXME: This is wrong; the macro refers to the numerical values 299 // of wchar_t *literals*, which are not locale-dependent. However, 300 // FreeBSD systems apparently depend on us getting this wrong, and 301 // setting this to 1 is conforming even if all the basic source 302 // character literals have the same encoding as char and wchar_t. 303 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 304 } 305 public: 306 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 307 this->UserLabelPrefix = ""; 308 309 switch (Triple.getArch()) { 310 default: 311 case llvm::Triple::x86: 312 case llvm::Triple::x86_64: 313 this->MCountName = ".mcount"; 314 break; 315 case llvm::Triple::mips: 316 case llvm::Triple::mipsel: 317 case llvm::Triple::ppc: 318 case llvm::Triple::ppc64: 319 case llvm::Triple::ppc64le: 320 this->MCountName = "_mcount"; 321 break; 322 case llvm::Triple::arm: 323 this->MCountName = "__mcount"; 324 break; 325 } 326 } 327 }; 328 329 // GNU/kFreeBSD Target 330 template<typename Target> 331 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 332 protected: 333 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 334 MacroBuilder &Builder) const override { 335 // GNU/kFreeBSD defines; list based off of gcc output 336 337 DefineStd(Builder, "unix", Opts); 338 Builder.defineMacro("__FreeBSD_kernel__"); 339 Builder.defineMacro("__GLIBC__"); 340 Builder.defineMacro("__ELF__"); 341 if (Opts.POSIXThreads) 342 Builder.defineMacro("_REENTRANT"); 343 if (Opts.CPlusPlus) 344 Builder.defineMacro("_GNU_SOURCE"); 345 } 346 public: 347 KFreeBSDTargetInfo(const llvm::Triple &Triple) 348 : OSTargetInfo<Target>(Triple) { 349 this->UserLabelPrefix = ""; 350 } 351 }; 352 353 // Minix Target 354 template<typename Target> 355 class MinixTargetInfo : public OSTargetInfo<Target> { 356 protected: 357 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 358 MacroBuilder &Builder) const override { 359 // Minix defines 360 361 Builder.defineMacro("__minix", "3"); 362 Builder.defineMacro("_EM_WSIZE", "4"); 363 Builder.defineMacro("_EM_PSIZE", "4"); 364 Builder.defineMacro("_EM_SSIZE", "2"); 365 Builder.defineMacro("_EM_LSIZE", "4"); 366 Builder.defineMacro("_EM_FSIZE", "4"); 367 Builder.defineMacro("_EM_DSIZE", "8"); 368 Builder.defineMacro("__ELF__"); 369 DefineStd(Builder, "unix", Opts); 370 } 371 public: 372 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 373 this->UserLabelPrefix = ""; 374 } 375 }; 376 377 // Linux target 378 template<typename Target> 379 class LinuxTargetInfo : public OSTargetInfo<Target> { 380 protected: 381 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 382 MacroBuilder &Builder) const override { 383 // Linux defines; list based off of gcc output 384 DefineStd(Builder, "unix", Opts); 385 DefineStd(Builder, "linux", Opts); 386 Builder.defineMacro("__gnu_linux__"); 387 Builder.defineMacro("__ELF__"); 388 if (Triple.getEnvironment() == llvm::Triple::Android) { 389 Builder.defineMacro("__ANDROID__", "1"); 390 unsigned Maj, Min, Rev; 391 Triple.getOSVersion(Maj, Min, Rev); 392 this->PlatformName = "android"; 393 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 394 } 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 402 this->UserLabelPrefix = ""; 403 this->WIntType = TargetInfo::UnsignedInt; 404 405 switch (Triple.getArch()) { 406 default: 407 break; 408 case llvm::Triple::ppc: 409 case llvm::Triple::ppc64: 410 case llvm::Triple::ppc64le: 411 this->MCountName = "_mcount"; 412 break; 413 } 414 } 415 416 const char *getStaticInitSectionSpecifier() const override { 417 return ".text.startup"; 418 } 419 }; 420 421 // NetBSD Target 422 template<typename Target> 423 class NetBSDTargetInfo : public OSTargetInfo<Target> { 424 protected: 425 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 426 MacroBuilder &Builder) const override { 427 // NetBSD defines; list based off of gcc output 428 Builder.defineMacro("__NetBSD__"); 429 Builder.defineMacro("__unix__"); 430 Builder.defineMacro("__ELF__"); 431 if (Opts.POSIXThreads) 432 Builder.defineMacro("_POSIX_THREADS"); 433 434 switch (Triple.getArch()) { 435 default: 436 break; 437 case llvm::Triple::arm: 438 case llvm::Triple::armeb: 439 case llvm::Triple::thumb: 440 case llvm::Triple::thumbeb: 441 Builder.defineMacro("__ARM_DWARF_EH__"); 442 break; 443 } 444 } 445 public: 446 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 447 this->UserLabelPrefix = ""; 448 this->MCountName = "_mcount"; 449 } 450 }; 451 452 // OpenBSD Target 453 template<typename Target> 454 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 455 protected: 456 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 457 MacroBuilder &Builder) const override { 458 // OpenBSD defines; list based off of gcc output 459 460 Builder.defineMacro("__OpenBSD__"); 461 DefineStd(Builder, "unix", Opts); 462 Builder.defineMacro("__ELF__"); 463 if (Opts.POSIXThreads) 464 Builder.defineMacro("_REENTRANT"); 465 } 466 public: 467 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 468 this->UserLabelPrefix = ""; 469 this->TLSSupported = false; 470 471 switch (Triple.getArch()) { 472 default: 473 case llvm::Triple::x86: 474 case llvm::Triple::x86_64: 475 case llvm::Triple::arm: 476 case llvm::Triple::sparc: 477 this->MCountName = "__mcount"; 478 break; 479 case llvm::Triple::mips64: 480 case llvm::Triple::mips64el: 481 case llvm::Triple::ppc: 482 case llvm::Triple::sparcv9: 483 this->MCountName = "_mcount"; 484 break; 485 } 486 } 487 }; 488 489 // Bitrig Target 490 template<typename Target> 491 class BitrigTargetInfo : public OSTargetInfo<Target> { 492 protected: 493 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 494 MacroBuilder &Builder) const override { 495 // Bitrig defines; list based off of gcc output 496 497 Builder.defineMacro("__Bitrig__"); 498 DefineStd(Builder, "unix", Opts); 499 Builder.defineMacro("__ELF__"); 500 if (Opts.POSIXThreads) 501 Builder.defineMacro("_REENTRANT"); 502 503 switch (Triple.getArch()) { 504 default: 505 break; 506 case llvm::Triple::arm: 507 case llvm::Triple::armeb: 508 case llvm::Triple::thumb: 509 case llvm::Triple::thumbeb: 510 Builder.defineMacro("__ARM_DWARF_EH__"); 511 break; 512 } 513 } 514 public: 515 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 516 this->UserLabelPrefix = ""; 517 this->MCountName = "__mcount"; 518 } 519 }; 520 521 // PSP Target 522 template<typename Target> 523 class PSPTargetInfo : public OSTargetInfo<Target> { 524 protected: 525 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 526 MacroBuilder &Builder) const override { 527 // PSP defines; list based on the output of the pspdev gcc toolchain. 528 Builder.defineMacro("PSP"); 529 Builder.defineMacro("_PSP"); 530 Builder.defineMacro("__psp__"); 531 Builder.defineMacro("__ELF__"); 532 } 533 public: 534 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 535 this->UserLabelPrefix = ""; 536 } 537 }; 538 539 // PS3 PPU Target 540 template<typename Target> 541 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 542 protected: 543 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 544 MacroBuilder &Builder) const override { 545 // PS3 PPU defines. 546 Builder.defineMacro("__PPC__"); 547 Builder.defineMacro("__PPU__"); 548 Builder.defineMacro("__CELLOS_LV2__"); 549 Builder.defineMacro("__ELF__"); 550 Builder.defineMacro("__LP32__"); 551 Builder.defineMacro("_ARCH_PPC64"); 552 Builder.defineMacro("__powerpc64__"); 553 } 554 public: 555 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 556 this->UserLabelPrefix = ""; 557 this->LongWidth = this->LongAlign = 32; 558 this->PointerWidth = this->PointerAlign = 32; 559 this->IntMaxType = TargetInfo::SignedLongLong; 560 this->Int64Type = TargetInfo::SignedLongLong; 561 this->SizeType = TargetInfo::UnsignedInt; 562 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 563 } 564 }; 565 566 template <typename Target> 567 class PS4OSTargetInfo : public OSTargetInfo<Target> { 568 protected: 569 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 570 MacroBuilder &Builder) const override { 571 Builder.defineMacro("__FreeBSD__", "9"); 572 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 573 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 574 DefineStd(Builder, "unix", Opts); 575 Builder.defineMacro("__ELF__"); 576 Builder.defineMacro("__PS4__"); 577 } 578 public: 579 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 580 this->WCharType = this->UnsignedShort; 581 582 this->UserLabelPrefix = ""; 583 584 switch (Triple.getArch()) { 585 default: 586 case llvm::Triple::x86_64: 587 this->MCountName = ".mcount"; 588 break; 589 } 590 } 591 }; 592 593 // Solaris target 594 template<typename Target> 595 class SolarisTargetInfo : public OSTargetInfo<Target> { 596 protected: 597 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 598 MacroBuilder &Builder) const override { 599 DefineStd(Builder, "sun", Opts); 600 DefineStd(Builder, "unix", Opts); 601 Builder.defineMacro("__ELF__"); 602 Builder.defineMacro("__svr4__"); 603 Builder.defineMacro("__SVR4"); 604 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 605 // newer, but to 500 for everything else. feature_test.h has a check to 606 // ensure that you are not using C99 with an old version of X/Open or C89 607 // with a new version. 608 if (Opts.C99) 609 Builder.defineMacro("_XOPEN_SOURCE", "600"); 610 else 611 Builder.defineMacro("_XOPEN_SOURCE", "500"); 612 if (Opts.CPlusPlus) 613 Builder.defineMacro("__C99FEATURES__"); 614 Builder.defineMacro("_LARGEFILE_SOURCE"); 615 Builder.defineMacro("_LARGEFILE64_SOURCE"); 616 Builder.defineMacro("__EXTENSIONS__"); 617 Builder.defineMacro("_REENTRANT"); 618 } 619 public: 620 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 621 this->UserLabelPrefix = ""; 622 this->WCharType = this->SignedInt; 623 // FIXME: WIntType should be SignedLong 624 } 625 }; 626 627 // Windows target 628 template<typename Target> 629 class WindowsTargetInfo : public OSTargetInfo<Target> { 630 protected: 631 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 632 MacroBuilder &Builder) const override { 633 Builder.defineMacro("_WIN32"); 634 } 635 void getVisualStudioDefines(const LangOptions &Opts, 636 MacroBuilder &Builder) const { 637 if (Opts.CPlusPlus) { 638 if (Opts.RTTIData) 639 Builder.defineMacro("_CPPRTTI"); 640 641 if (Opts.CXXExceptions) 642 Builder.defineMacro("_CPPUNWIND"); 643 } 644 645 if (!Opts.CharIsSigned) 646 Builder.defineMacro("_CHAR_UNSIGNED"); 647 648 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 649 // but it works for now. 650 if (Opts.POSIXThreads) 651 Builder.defineMacro("_MT"); 652 653 if (Opts.MSCompatibilityVersion) { 654 Builder.defineMacro("_MSC_VER", 655 Twine(Opts.MSCompatibilityVersion / 100000)); 656 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 657 // FIXME We cannot encode the revision information into 32-bits 658 Builder.defineMacro("_MSC_BUILD", Twine(1)); 659 660 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(19)) 661 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 662 } 663 664 if (Opts.MicrosoftExt) { 665 Builder.defineMacro("_MSC_EXTENSIONS"); 666 667 if (Opts.CPlusPlus11) { 668 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 669 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 670 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 671 } 672 } 673 674 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 675 } 676 677 public: 678 WindowsTargetInfo(const llvm::Triple &Triple) 679 : OSTargetInfo<Target>(Triple) {} 680 }; 681 682 template <typename Target> 683 class NaClTargetInfo : public OSTargetInfo<Target> { 684 protected: 685 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 686 MacroBuilder &Builder) const override { 687 if (Opts.POSIXThreads) 688 Builder.defineMacro("_REENTRANT"); 689 if (Opts.CPlusPlus) 690 Builder.defineMacro("_GNU_SOURCE"); 691 692 DefineStd(Builder, "unix", Opts); 693 Builder.defineMacro("__ELF__"); 694 Builder.defineMacro("__native_client__"); 695 } 696 697 public: 698 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 699 this->UserLabelPrefix = ""; 700 this->LongAlign = 32; 701 this->LongWidth = 32; 702 this->PointerAlign = 32; 703 this->PointerWidth = 32; 704 this->IntMaxType = TargetInfo::SignedLongLong; 705 this->Int64Type = TargetInfo::SignedLongLong; 706 this->DoubleAlign = 64; 707 this->LongDoubleWidth = 64; 708 this->LongDoubleAlign = 64; 709 this->LongLongWidth = 64; 710 this->LongLongAlign = 64; 711 this->SizeType = TargetInfo::UnsignedInt; 712 this->PtrDiffType = TargetInfo::SignedInt; 713 this->IntPtrType = TargetInfo::SignedInt; 714 // RegParmMax is inherited from the underlying architecture 715 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 716 if (Triple.getArch() == llvm::Triple::arm) { 717 // Handled in ARM's setABI(). 718 } else if (Triple.getArch() == llvm::Triple::x86) { 719 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 720 } else if (Triple.getArch() == llvm::Triple::x86_64) { 721 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 722 } else if (Triple.getArch() == llvm::Triple::mipsel) { 723 // Handled on mips' setDescriptionString. 724 } else { 725 assert(Triple.getArch() == llvm::Triple::le32); 726 this->DescriptionString = "e-p:32:32-i64:64"; 727 } 728 } 729 }; 730 731 //===----------------------------------------------------------------------===// 732 // Specific target implementations. 733 //===----------------------------------------------------------------------===// 734 735 // PPC abstract base class 736 class PPCTargetInfo : public TargetInfo { 737 static const Builtin::Info BuiltinInfo[]; 738 static const char * const GCCRegNames[]; 739 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 740 std::string CPU; 741 742 // Target cpu features. 743 bool HasVSX; 744 bool HasP8Vector; 745 bool HasP8Crypto; 746 bool HasDirectMove; 747 bool HasQPX; 748 bool HasHTM; 749 bool HasBPERMD; 750 bool HasExtDiv; 751 752 protected: 753 std::string ABI; 754 755 public: 756 PPCTargetInfo(const llvm::Triple &Triple) 757 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 758 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 759 HasBPERMD(false), HasExtDiv(false) { 760 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 761 LongDoubleWidth = LongDoubleAlign = 128; 762 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 763 } 764 765 /// \brief Flags for architecture specific defines. 766 typedef enum { 767 ArchDefineNone = 0, 768 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 769 ArchDefinePpcgr = 1 << 1, 770 ArchDefinePpcsq = 1 << 2, 771 ArchDefine440 = 1 << 3, 772 ArchDefine603 = 1 << 4, 773 ArchDefine604 = 1 << 5, 774 ArchDefinePwr4 = 1 << 6, 775 ArchDefinePwr5 = 1 << 7, 776 ArchDefinePwr5x = 1 << 8, 777 ArchDefinePwr6 = 1 << 9, 778 ArchDefinePwr6x = 1 << 10, 779 ArchDefinePwr7 = 1 << 11, 780 ArchDefinePwr8 = 1 << 12, 781 ArchDefineA2 = 1 << 13, 782 ArchDefineA2q = 1 << 14 783 } ArchDefineTypes; 784 785 // Note: GCC recognizes the following additional cpus: 786 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 787 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 788 // titan, rs64. 789 bool setCPU(const std::string &Name) override { 790 bool CPUKnown = llvm::StringSwitch<bool>(Name) 791 .Case("generic", true) 792 .Case("440", true) 793 .Case("450", true) 794 .Case("601", true) 795 .Case("602", true) 796 .Case("603", true) 797 .Case("603e", true) 798 .Case("603ev", true) 799 .Case("604", true) 800 .Case("604e", true) 801 .Case("620", true) 802 .Case("630", true) 803 .Case("g3", true) 804 .Case("7400", true) 805 .Case("g4", true) 806 .Case("7450", true) 807 .Case("g4+", true) 808 .Case("750", true) 809 .Case("970", true) 810 .Case("g5", true) 811 .Case("a2", true) 812 .Case("a2q", true) 813 .Case("e500mc", true) 814 .Case("e5500", true) 815 .Case("power3", true) 816 .Case("pwr3", true) 817 .Case("power4", true) 818 .Case("pwr4", true) 819 .Case("power5", true) 820 .Case("pwr5", true) 821 .Case("power5x", true) 822 .Case("pwr5x", true) 823 .Case("power6", true) 824 .Case("pwr6", true) 825 .Case("power6x", true) 826 .Case("pwr6x", true) 827 .Case("power7", true) 828 .Case("pwr7", true) 829 .Case("power8", true) 830 .Case("pwr8", true) 831 .Case("powerpc", true) 832 .Case("ppc", true) 833 .Case("powerpc64", true) 834 .Case("ppc64", true) 835 .Case("powerpc64le", true) 836 .Case("ppc64le", true) 837 .Default(false); 838 839 if (CPUKnown) 840 CPU = Name; 841 842 return CPUKnown; 843 } 844 845 846 StringRef getABI() const override { return ABI; } 847 848 void getTargetBuiltins(const Builtin::Info *&Records, 849 unsigned &NumRecords) const override { 850 Records = BuiltinInfo; 851 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 852 } 853 854 bool isCLZForZeroUndef() const override { return false; } 855 856 void getTargetDefines(const LangOptions &Opts, 857 MacroBuilder &Builder) const override; 858 859 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 860 861 bool handleTargetFeatures(std::vector<std::string> &Features, 862 DiagnosticsEngine &Diags) override; 863 bool hasFeature(StringRef Feature) const override; 864 865 void getGCCRegNames(const char * const *&Names, 866 unsigned &NumNames) const override; 867 void getGCCRegAliases(const GCCRegAlias *&Aliases, 868 unsigned &NumAliases) const override; 869 bool validateAsmConstraint(const char *&Name, 870 TargetInfo::ConstraintInfo &Info) const override { 871 switch (*Name) { 872 default: return false; 873 case 'O': // Zero 874 break; 875 case 'b': // Base register 876 case 'f': // Floating point register 877 Info.setAllowsRegister(); 878 break; 879 // FIXME: The following are added to allow parsing. 880 // I just took a guess at what the actions should be. 881 // Also, is more specific checking needed? I.e. specific registers? 882 case 'd': // Floating point register (containing 64-bit value) 883 case 'v': // Altivec vector register 884 Info.setAllowsRegister(); 885 break; 886 case 'w': 887 switch (Name[1]) { 888 case 'd':// VSX vector register to hold vector double data 889 case 'f':// VSX vector register to hold vector float data 890 case 's':// VSX vector register to hold scalar float data 891 case 'a':// Any VSX register 892 case 'c':// An individual CR bit 893 break; 894 default: 895 return false; 896 } 897 Info.setAllowsRegister(); 898 Name++; // Skip over 'w'. 899 break; 900 case 'h': // `MQ', `CTR', or `LINK' register 901 case 'q': // `MQ' register 902 case 'c': // `CTR' register 903 case 'l': // `LINK' register 904 case 'x': // `CR' register (condition register) number 0 905 case 'y': // `CR' register (condition register) 906 case 'z': // `XER[CA]' carry bit (part of the XER register) 907 Info.setAllowsRegister(); 908 break; 909 case 'I': // Signed 16-bit constant 910 case 'J': // Unsigned 16-bit constant shifted left 16 bits 911 // (use `L' instead for SImode constants) 912 case 'K': // Unsigned 16-bit constant 913 case 'L': // Signed 16-bit constant shifted left 16 bits 914 case 'M': // Constant larger than 31 915 case 'N': // Exact power of 2 916 case 'P': // Constant whose negation is a signed 16-bit constant 917 case 'G': // Floating point constant that can be loaded into a 918 // register with one instruction per word 919 case 'H': // Integer/Floating point constant that can be loaded 920 // into a register using three instructions 921 break; 922 case 'm': // Memory operand. Note that on PowerPC targets, m can 923 // include addresses that update the base register. It 924 // is therefore only safe to use `m' in an asm statement 925 // if that asm statement accesses the operand exactly once. 926 // The asm statement must also use `%U<opno>' as a 927 // placeholder for the "update" flag in the corresponding 928 // load or store instruction. For example: 929 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 930 // is correct but: 931 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 932 // is not. Use es rather than m if you don't want the base 933 // register to be updated. 934 case 'e': 935 if (Name[1] != 's') 936 return false; 937 // es: A "stable" memory operand; that is, one which does not 938 // include any automodification of the base register. Unlike 939 // `m', this constraint can be used in asm statements that 940 // might access the operand several times, or that might not 941 // access it at all. 942 Info.setAllowsMemory(); 943 Name++; // Skip over 'e'. 944 break; 945 case 'Q': // Memory operand that is an offset from a register (it is 946 // usually better to use `m' or `es' in asm statements) 947 case 'Z': // Memory operand that is an indexed or indirect from a 948 // register (it is usually better to use `m' or `es' in 949 // asm statements) 950 Info.setAllowsMemory(); 951 Info.setAllowsRegister(); 952 break; 953 case 'R': // AIX TOC entry 954 case 'a': // Address operand that is an indexed or indirect from a 955 // register (`p' is preferable for asm statements) 956 case 'S': // Constant suitable as a 64-bit mask operand 957 case 'T': // Constant suitable as a 32-bit mask operand 958 case 'U': // System V Release 4 small data area reference 959 case 't': // AND masks that can be performed by two rldic{l, r} 960 // instructions 961 case 'W': // Vector constant that does not require memory 962 case 'j': // Vector constant that is all zeros. 963 break; 964 // End FIXME. 965 } 966 return true; 967 } 968 std::string convertConstraint(const char *&Constraint) const override { 969 std::string R; 970 switch (*Constraint) { 971 case 'e': 972 case 'w': 973 // Two-character constraint; add "^" hint for later parsing. 974 R = std::string("^") + std::string(Constraint, 2); 975 Constraint++; 976 break; 977 default: 978 return TargetInfo::convertConstraint(Constraint); 979 } 980 return R; 981 } 982 const char *getClobbers() const override { 983 return ""; 984 } 985 int getEHDataRegisterNumber(unsigned RegNo) const override { 986 if (RegNo == 0) return 3; 987 if (RegNo == 1) return 4; 988 return -1; 989 } 990 991 bool hasSjLjLowering() const override { 992 return true; 993 } 994 }; 995 996 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 997 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 998 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 999 ALL_LANGUAGES }, 1000 #include "clang/Basic/BuiltinsPPC.def" 1001 }; 1002 1003 /// handleTargetFeatures - Perform initialization based on the user 1004 /// configured set of features. 1005 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1006 DiagnosticsEngine &Diags) { 1007 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 1008 // Ignore disabled features. 1009 if (Features[i][0] == '-') 1010 continue; 1011 1012 StringRef Feature = StringRef(Features[i]).substr(1); 1013 1014 if (Feature == "vsx") { 1015 HasVSX = true; 1016 continue; 1017 } 1018 1019 if (Feature == "bpermd") { 1020 HasBPERMD = true; 1021 continue; 1022 } 1023 1024 if (Feature == "extdiv") { 1025 HasExtDiv = true; 1026 continue; 1027 } 1028 1029 if (Feature == "power8-vector") { 1030 HasP8Vector = true; 1031 continue; 1032 } 1033 1034 if (Feature == "crypto") { 1035 HasP8Crypto = true; 1036 continue; 1037 } 1038 1039 if (Feature == "direct-move") { 1040 HasDirectMove = true; 1041 continue; 1042 } 1043 1044 if (Feature == "qpx") { 1045 HasQPX = true; 1046 continue; 1047 } 1048 1049 if (Feature == "htm") { 1050 HasHTM = true; 1051 continue; 1052 } 1053 1054 // TODO: Finish this list and add an assert that we've handled them 1055 // all. 1056 } 1057 1058 return true; 1059 } 1060 1061 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1062 /// #defines that are not tied to a specific subtarget. 1063 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1064 MacroBuilder &Builder) const { 1065 // Target identification. 1066 Builder.defineMacro("__ppc__"); 1067 Builder.defineMacro("__PPC__"); 1068 Builder.defineMacro("_ARCH_PPC"); 1069 Builder.defineMacro("__powerpc__"); 1070 Builder.defineMacro("__POWERPC__"); 1071 if (PointerWidth == 64) { 1072 Builder.defineMacro("_ARCH_PPC64"); 1073 Builder.defineMacro("__powerpc64__"); 1074 Builder.defineMacro("__ppc64__"); 1075 Builder.defineMacro("__PPC64__"); 1076 } 1077 1078 // Target properties. 1079 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1080 Builder.defineMacro("_LITTLE_ENDIAN"); 1081 } else { 1082 if (getTriple().getOS() != llvm::Triple::NetBSD && 1083 getTriple().getOS() != llvm::Triple::OpenBSD) 1084 Builder.defineMacro("_BIG_ENDIAN"); 1085 } 1086 1087 // ABI options. 1088 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1089 Builder.defineMacro("_CALL_ELF", "1"); 1090 if (ABI == "elfv2") 1091 Builder.defineMacro("_CALL_ELF", "2"); 1092 1093 // Subtarget options. 1094 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1095 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1096 1097 // FIXME: Should be controlled by command line option. 1098 if (LongDoubleWidth == 128) 1099 Builder.defineMacro("__LONG_DOUBLE_128__"); 1100 1101 if (Opts.AltiVec) { 1102 Builder.defineMacro("__VEC__", "10206"); 1103 Builder.defineMacro("__ALTIVEC__"); 1104 } 1105 1106 // CPU identification. 1107 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1108 .Case("440", ArchDefineName) 1109 .Case("450", ArchDefineName | ArchDefine440) 1110 .Case("601", ArchDefineName) 1111 .Case("602", ArchDefineName | ArchDefinePpcgr) 1112 .Case("603", ArchDefineName | ArchDefinePpcgr) 1113 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1114 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1115 .Case("604", ArchDefineName | ArchDefinePpcgr) 1116 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1117 .Case("620", ArchDefineName | ArchDefinePpcgr) 1118 .Case("630", ArchDefineName | ArchDefinePpcgr) 1119 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1120 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1121 .Case("750", ArchDefineName | ArchDefinePpcgr) 1122 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1123 | ArchDefinePpcsq) 1124 .Case("a2", ArchDefineA2) 1125 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1126 .Case("pwr3", ArchDefinePpcgr) 1127 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1128 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1129 | ArchDefinePpcsq) 1130 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1131 | ArchDefinePpcgr | ArchDefinePpcsq) 1132 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1133 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1134 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1135 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1136 | ArchDefinePpcsq) 1137 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1138 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1139 | ArchDefinePpcgr | ArchDefinePpcsq) 1140 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1141 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1142 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1143 .Case("power3", ArchDefinePpcgr) 1144 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1145 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1146 | ArchDefinePpcsq) 1147 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1148 | ArchDefinePpcgr | ArchDefinePpcsq) 1149 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1150 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1151 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1152 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1153 | ArchDefinePpcsq) 1154 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1155 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1156 | ArchDefinePpcgr | ArchDefinePpcsq) 1157 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1158 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1159 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1160 .Default(ArchDefineNone); 1161 1162 if (defs & ArchDefineName) 1163 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1164 if (defs & ArchDefinePpcgr) 1165 Builder.defineMacro("_ARCH_PPCGR"); 1166 if (defs & ArchDefinePpcsq) 1167 Builder.defineMacro("_ARCH_PPCSQ"); 1168 if (defs & ArchDefine440) 1169 Builder.defineMacro("_ARCH_440"); 1170 if (defs & ArchDefine603) 1171 Builder.defineMacro("_ARCH_603"); 1172 if (defs & ArchDefine604) 1173 Builder.defineMacro("_ARCH_604"); 1174 if (defs & ArchDefinePwr4) 1175 Builder.defineMacro("_ARCH_PWR4"); 1176 if (defs & ArchDefinePwr5) 1177 Builder.defineMacro("_ARCH_PWR5"); 1178 if (defs & ArchDefinePwr5x) 1179 Builder.defineMacro("_ARCH_PWR5X"); 1180 if (defs & ArchDefinePwr6) 1181 Builder.defineMacro("_ARCH_PWR6"); 1182 if (defs & ArchDefinePwr6x) 1183 Builder.defineMacro("_ARCH_PWR6X"); 1184 if (defs & ArchDefinePwr7) 1185 Builder.defineMacro("_ARCH_PWR7"); 1186 if (defs & ArchDefinePwr8) 1187 Builder.defineMacro("_ARCH_PWR8"); 1188 if (defs & ArchDefineA2) 1189 Builder.defineMacro("_ARCH_A2"); 1190 if (defs & ArchDefineA2q) { 1191 Builder.defineMacro("_ARCH_A2Q"); 1192 Builder.defineMacro("_ARCH_QP"); 1193 } 1194 1195 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1196 Builder.defineMacro("__bg__"); 1197 Builder.defineMacro("__THW_BLUEGENE__"); 1198 Builder.defineMacro("__bgq__"); 1199 Builder.defineMacro("__TOS_BGQ__"); 1200 } 1201 1202 if (HasVSX) 1203 Builder.defineMacro("__VSX__"); 1204 if (HasP8Vector) 1205 Builder.defineMacro("__POWER8_VECTOR__"); 1206 if (HasP8Crypto) 1207 Builder.defineMacro("__CRYPTO__"); 1208 if (HasHTM) 1209 Builder.defineMacro("__HTM__"); 1210 1211 // FIXME: The following are not yet generated here by Clang, but are 1212 // generated by GCC: 1213 // 1214 // _SOFT_FLOAT_ 1215 // __RECIP_PRECISION__ 1216 // __APPLE_ALTIVEC__ 1217 // __RECIP__ 1218 // __RECIPF__ 1219 // __RSQRTE__ 1220 // __RSQRTEF__ 1221 // _SOFT_DOUBLE_ 1222 // __NO_LWSYNC__ 1223 // __HAVE_BSWAP__ 1224 // __LONGDOUBLE128 1225 // __CMODEL_MEDIUM__ 1226 // __CMODEL_LARGE__ 1227 // _CALL_SYSV 1228 // _CALL_DARWIN 1229 // __NO_FPRS__ 1230 } 1231 1232 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1233 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1234 .Case("7400", true) 1235 .Case("g4", true) 1236 .Case("7450", true) 1237 .Case("g4+", true) 1238 .Case("970", true) 1239 .Case("g5", true) 1240 .Case("pwr6", true) 1241 .Case("pwr7", true) 1242 .Case("pwr8", true) 1243 .Case("ppc64", true) 1244 .Case("ppc64le", true) 1245 .Default(false); 1246 1247 Features["qpx"] = (CPU == "a2q"); 1248 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1249 .Case("ppc64le", true) 1250 .Case("pwr8", true) 1251 .Default(false); 1252 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1253 .Case("ppc64le", true) 1254 .Case("pwr8", true) 1255 .Default(false); 1256 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1257 .Case("ppc64le", true) 1258 .Case("pwr8", true) 1259 .Case("pwr7", true) 1260 .Default(false); 1261 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1262 .Case("ppc64le", true) 1263 .Case("pwr8", true) 1264 .Case("pwr7", true) 1265 .Default(false); 1266 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1267 .Case("ppc64le", true) 1268 .Case("pwr8", true) 1269 .Default(false); 1270 } 1271 1272 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1273 return llvm::StringSwitch<bool>(Feature) 1274 .Case("powerpc", true) 1275 .Case("vsx", HasVSX) 1276 .Case("power8-vector", HasP8Vector) 1277 .Case("crypto", HasP8Crypto) 1278 .Case("direct-move", HasDirectMove) 1279 .Case("qpx", HasQPX) 1280 .Case("htm", HasHTM) 1281 .Case("bpermd", HasBPERMD) 1282 .Case("extdiv", HasExtDiv) 1283 .Default(false); 1284 } 1285 1286 const char * const PPCTargetInfo::GCCRegNames[] = { 1287 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1288 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1289 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1290 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1291 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1292 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1293 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1294 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1295 "mq", "lr", "ctr", "ap", 1296 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1297 "xer", 1298 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1299 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1300 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1301 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1302 "vrsave", "vscr", 1303 "spe_acc", "spefscr", 1304 "sfp" 1305 }; 1306 1307 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1308 unsigned &NumNames) const { 1309 Names = GCCRegNames; 1310 NumNames = llvm::array_lengthof(GCCRegNames); 1311 } 1312 1313 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1314 // While some of these aliases do map to different registers 1315 // they still share the same register name. 1316 { { "0" }, "r0" }, 1317 { { "1"}, "r1" }, 1318 { { "2" }, "r2" }, 1319 { { "3" }, "r3" }, 1320 { { "4" }, "r4" }, 1321 { { "5" }, "r5" }, 1322 { { "6" }, "r6" }, 1323 { { "7" }, "r7" }, 1324 { { "8" }, "r8" }, 1325 { { "9" }, "r9" }, 1326 { { "10" }, "r10" }, 1327 { { "11" }, "r11" }, 1328 { { "12" }, "r12" }, 1329 { { "13" }, "r13" }, 1330 { { "14" }, "r14" }, 1331 { { "15" }, "r15" }, 1332 { { "16" }, "r16" }, 1333 { { "17" }, "r17" }, 1334 { { "18" }, "r18" }, 1335 { { "19" }, "r19" }, 1336 { { "20" }, "r20" }, 1337 { { "21" }, "r21" }, 1338 { { "22" }, "r22" }, 1339 { { "23" }, "r23" }, 1340 { { "24" }, "r24" }, 1341 { { "25" }, "r25" }, 1342 { { "26" }, "r26" }, 1343 { { "27" }, "r27" }, 1344 { { "28" }, "r28" }, 1345 { { "29" }, "r29" }, 1346 { { "30" }, "r30" }, 1347 { { "31" }, "r31" }, 1348 { { "fr0" }, "f0" }, 1349 { { "fr1" }, "f1" }, 1350 { { "fr2" }, "f2" }, 1351 { { "fr3" }, "f3" }, 1352 { { "fr4" }, "f4" }, 1353 { { "fr5" }, "f5" }, 1354 { { "fr6" }, "f6" }, 1355 { { "fr7" }, "f7" }, 1356 { { "fr8" }, "f8" }, 1357 { { "fr9" }, "f9" }, 1358 { { "fr10" }, "f10" }, 1359 { { "fr11" }, "f11" }, 1360 { { "fr12" }, "f12" }, 1361 { { "fr13" }, "f13" }, 1362 { { "fr14" }, "f14" }, 1363 { { "fr15" }, "f15" }, 1364 { { "fr16" }, "f16" }, 1365 { { "fr17" }, "f17" }, 1366 { { "fr18" }, "f18" }, 1367 { { "fr19" }, "f19" }, 1368 { { "fr20" }, "f20" }, 1369 { { "fr21" }, "f21" }, 1370 { { "fr22" }, "f22" }, 1371 { { "fr23" }, "f23" }, 1372 { { "fr24" }, "f24" }, 1373 { { "fr25" }, "f25" }, 1374 { { "fr26" }, "f26" }, 1375 { { "fr27" }, "f27" }, 1376 { { "fr28" }, "f28" }, 1377 { { "fr29" }, "f29" }, 1378 { { "fr30" }, "f30" }, 1379 { { "fr31" }, "f31" }, 1380 { { "cc" }, "cr0" }, 1381 }; 1382 1383 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1384 unsigned &NumAliases) const { 1385 Aliases = GCCRegAliases; 1386 NumAliases = llvm::array_lengthof(GCCRegAliases); 1387 } 1388 1389 class PPC32TargetInfo : public PPCTargetInfo { 1390 public: 1391 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1392 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1393 1394 switch (getTriple().getOS()) { 1395 case llvm::Triple::Linux: 1396 case llvm::Triple::FreeBSD: 1397 case llvm::Triple::NetBSD: 1398 SizeType = UnsignedInt; 1399 PtrDiffType = SignedInt; 1400 IntPtrType = SignedInt; 1401 break; 1402 default: 1403 break; 1404 } 1405 1406 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1407 LongDoubleWidth = LongDoubleAlign = 64; 1408 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1409 } 1410 1411 // PPC32 supports atomics up to 4 bytes. 1412 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1413 } 1414 1415 BuiltinVaListKind getBuiltinVaListKind() const override { 1416 // This is the ELF definition, and is overridden by the Darwin sub-target 1417 return TargetInfo::PowerABIBuiltinVaList; 1418 } 1419 }; 1420 1421 // Note: ABI differences may eventually require us to have a separate 1422 // TargetInfo for little endian. 1423 class PPC64TargetInfo : public PPCTargetInfo { 1424 public: 1425 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1426 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1427 IntMaxType = SignedLong; 1428 Int64Type = SignedLong; 1429 1430 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1431 DescriptionString = "e-m:e-i64:64-n32:64"; 1432 ABI = "elfv2"; 1433 } else { 1434 DescriptionString = "E-m:e-i64:64-n32:64"; 1435 ABI = "elfv1"; 1436 } 1437 1438 switch (getTriple().getOS()) { 1439 case llvm::Triple::FreeBSD: 1440 LongDoubleWidth = LongDoubleAlign = 64; 1441 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1442 break; 1443 case llvm::Triple::NetBSD: 1444 IntMaxType = SignedLongLong; 1445 Int64Type = SignedLongLong; 1446 break; 1447 default: 1448 break; 1449 } 1450 1451 // PPC64 supports atomics up to 8 bytes. 1452 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1453 } 1454 BuiltinVaListKind getBuiltinVaListKind() const override { 1455 return TargetInfo::CharPtrBuiltinVaList; 1456 } 1457 // PPC64 Linux-specifc ABI options. 1458 bool setABI(const std::string &Name) override { 1459 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1460 ABI = Name; 1461 return true; 1462 } 1463 return false; 1464 } 1465 }; 1466 1467 class DarwinPPC32TargetInfo : 1468 public DarwinTargetInfo<PPC32TargetInfo> { 1469 public: 1470 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1471 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1472 HasAlignMac68kSupport = true; 1473 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1474 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1475 LongLongAlign = 32; 1476 SuitableAlign = 128; 1477 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1478 } 1479 BuiltinVaListKind getBuiltinVaListKind() const override { 1480 return TargetInfo::CharPtrBuiltinVaList; 1481 } 1482 }; 1483 1484 class DarwinPPC64TargetInfo : 1485 public DarwinTargetInfo<PPC64TargetInfo> { 1486 public: 1487 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1488 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1489 HasAlignMac68kSupport = true; 1490 SuitableAlign = 128; 1491 DescriptionString = "E-m:o-i64:64-n32:64"; 1492 } 1493 }; 1494 1495 static const unsigned NVPTXAddrSpaceMap[] = { 1496 1, // opencl_global 1497 3, // opencl_local 1498 4, // opencl_constant 1499 // FIXME: generic has to be added to the target 1500 0, // opencl_generic 1501 1, // cuda_device 1502 4, // cuda_constant 1503 3, // cuda_shared 1504 }; 1505 class NVPTXTargetInfo : public TargetInfo { 1506 static const char * const GCCRegNames[]; 1507 static const Builtin::Info BuiltinInfo[]; 1508 1509 // The GPU profiles supported by the NVPTX backend 1510 enum GPUKind { 1511 GK_NONE, 1512 GK_SM20, 1513 GK_SM21, 1514 GK_SM30, 1515 GK_SM35, 1516 GK_SM37, 1517 } GPU; 1518 1519 public: 1520 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1521 BigEndian = false; 1522 TLSSupported = false; 1523 LongWidth = LongAlign = 64; 1524 AddrSpaceMap = &NVPTXAddrSpaceMap; 1525 UseAddrSpaceMapMangling = true; 1526 // Define available target features 1527 // These must be defined in sorted order! 1528 NoAsmVariants = true; 1529 // Set the default GPU to sm20 1530 GPU = GK_SM20; 1531 } 1532 void getTargetDefines(const LangOptions &Opts, 1533 MacroBuilder &Builder) const override { 1534 Builder.defineMacro("__PTX__"); 1535 Builder.defineMacro("__NVPTX__"); 1536 if (Opts.CUDAIsDevice) { 1537 // Set __CUDA_ARCH__ for the GPU specified. 1538 std::string CUDAArchCode; 1539 switch (GPU) { 1540 case GK_SM20: 1541 CUDAArchCode = "200"; 1542 break; 1543 case GK_SM21: 1544 CUDAArchCode = "210"; 1545 break; 1546 case GK_SM30: 1547 CUDAArchCode = "300"; 1548 break; 1549 case GK_SM35: 1550 CUDAArchCode = "350"; 1551 break; 1552 case GK_SM37: 1553 CUDAArchCode = "370"; 1554 break; 1555 default: 1556 llvm_unreachable("Unhandled target CPU"); 1557 } 1558 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1559 } 1560 } 1561 void getTargetBuiltins(const Builtin::Info *&Records, 1562 unsigned &NumRecords) const override { 1563 Records = BuiltinInfo; 1564 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1565 } 1566 bool hasFeature(StringRef Feature) const override { 1567 return Feature == "ptx" || Feature == "nvptx"; 1568 } 1569 1570 void getGCCRegNames(const char * const *&Names, 1571 unsigned &NumNames) const override; 1572 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1573 unsigned &NumAliases) const override { 1574 // No aliases. 1575 Aliases = nullptr; 1576 NumAliases = 0; 1577 } 1578 bool 1579 validateAsmConstraint(const char *&Name, 1580 TargetInfo::ConstraintInfo &Info) const override { 1581 switch (*Name) { 1582 default: return false; 1583 case 'c': 1584 case 'h': 1585 case 'r': 1586 case 'l': 1587 case 'f': 1588 case 'd': 1589 Info.setAllowsRegister(); 1590 return true; 1591 } 1592 } 1593 const char *getClobbers() const override { 1594 // FIXME: Is this really right? 1595 return ""; 1596 } 1597 BuiltinVaListKind getBuiltinVaListKind() const override { 1598 // FIXME: implement 1599 return TargetInfo::CharPtrBuiltinVaList; 1600 } 1601 bool setCPU(const std::string &Name) override { 1602 GPU = llvm::StringSwitch<GPUKind>(Name) 1603 .Case("sm_20", GK_SM20) 1604 .Case("sm_21", GK_SM21) 1605 .Case("sm_30", GK_SM30) 1606 .Case("sm_35", GK_SM35) 1607 .Case("sm_37", GK_SM37) 1608 .Default(GK_NONE); 1609 1610 return GPU != GK_NONE; 1611 } 1612 }; 1613 1614 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1615 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1616 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1617 ALL_LANGUAGES }, 1618 #include "clang/Basic/BuiltinsNVPTX.def" 1619 }; 1620 1621 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1622 "r0" 1623 }; 1624 1625 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1626 unsigned &NumNames) const { 1627 Names = GCCRegNames; 1628 NumNames = llvm::array_lengthof(GCCRegNames); 1629 } 1630 1631 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1632 public: 1633 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1634 PointerWidth = PointerAlign = 32; 1635 SizeType = TargetInfo::UnsignedInt; 1636 PtrDiffType = TargetInfo::SignedInt; 1637 IntPtrType = TargetInfo::SignedInt; 1638 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1639 } 1640 }; 1641 1642 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1643 public: 1644 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1645 PointerWidth = PointerAlign = 64; 1646 SizeType = TargetInfo::UnsignedLong; 1647 PtrDiffType = TargetInfo::SignedLong; 1648 IntPtrType = TargetInfo::SignedLong; 1649 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1650 } 1651 }; 1652 1653 static const unsigned R600AddrSpaceMap[] = { 1654 1, // opencl_global 1655 3, // opencl_local 1656 2, // opencl_constant 1657 4, // opencl_generic 1658 1, // cuda_device 1659 2, // cuda_constant 1660 3 // cuda_shared 1661 }; 1662 1663 // If you edit the description strings, make sure you update 1664 // getPointerWidthV(). 1665 1666 static const char *DescriptionStringR600 = 1667 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1668 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1669 1670 static const char *DescriptionStringR600DoubleOps = 1671 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1672 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1673 1674 static const char *DescriptionStringSI = 1675 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1676 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1677 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1678 1679 class R600TargetInfo : public TargetInfo { 1680 static const Builtin::Info BuiltinInfo[]; 1681 static const char * const GCCRegNames[]; 1682 1683 /// \brief The GPU profiles supported by the R600 target. 1684 enum GPUKind { 1685 GK_NONE, 1686 GK_R600, 1687 GK_R600_DOUBLE_OPS, 1688 GK_R700, 1689 GK_R700_DOUBLE_OPS, 1690 GK_EVERGREEN, 1691 GK_EVERGREEN_DOUBLE_OPS, 1692 GK_NORTHERN_ISLANDS, 1693 GK_CAYMAN, 1694 GK_SOUTHERN_ISLANDS, 1695 GK_SEA_ISLANDS 1696 } GPU; 1697 1698 bool hasFP64; 1699 1700 public: 1701 R600TargetInfo(const llvm::Triple &Triple) 1702 : TargetInfo(Triple) { 1703 1704 if (Triple.getArch() == llvm::Triple::amdgcn) { 1705 DescriptionString = DescriptionStringSI; 1706 GPU = GK_SOUTHERN_ISLANDS; 1707 hasFP64 = true; 1708 } else { 1709 DescriptionString = DescriptionStringR600; 1710 GPU = GK_R600; 1711 hasFP64 = false; 1712 } 1713 AddrSpaceMap = &R600AddrSpaceMap; 1714 UseAddrSpaceMapMangling = true; 1715 } 1716 1717 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1718 if (GPU <= GK_CAYMAN) 1719 return 32; 1720 1721 switch(AddrSpace) { 1722 default: 1723 return 64; 1724 case 0: 1725 case 3: 1726 case 5: 1727 return 32; 1728 } 1729 } 1730 1731 const char * getClobbers() const override { 1732 return ""; 1733 } 1734 1735 void getGCCRegNames(const char * const *&Names, 1736 unsigned &NumNames) const override; 1737 1738 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1739 unsigned &NumAliases) const override { 1740 Aliases = nullptr; 1741 NumAliases = 0; 1742 } 1743 1744 bool validateAsmConstraint(const char *&Name, 1745 TargetInfo::ConstraintInfo &info) const override { 1746 return true; 1747 } 1748 1749 void getTargetBuiltins(const Builtin::Info *&Records, 1750 unsigned &NumRecords) const override { 1751 Records = BuiltinInfo; 1752 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin; 1753 } 1754 1755 void getTargetDefines(const LangOptions &Opts, 1756 MacroBuilder &Builder) const override { 1757 Builder.defineMacro("__R600__"); 1758 if (hasFP64 && Opts.OpenCL) { 1759 Builder.defineMacro("cl_khr_fp64"); 1760 } 1761 } 1762 1763 BuiltinVaListKind getBuiltinVaListKind() const override { 1764 return TargetInfo::CharPtrBuiltinVaList; 1765 } 1766 1767 bool setCPU(const std::string &Name) override { 1768 GPU = llvm::StringSwitch<GPUKind>(Name) 1769 .Case("r600" , GK_R600) 1770 .Case("rv610", GK_R600) 1771 .Case("rv620", GK_R600) 1772 .Case("rv630", GK_R600) 1773 .Case("rv635", GK_R600) 1774 .Case("rs780", GK_R600) 1775 .Case("rs880", GK_R600) 1776 .Case("rv670", GK_R600_DOUBLE_OPS) 1777 .Case("rv710", GK_R700) 1778 .Case("rv730", GK_R700) 1779 .Case("rv740", GK_R700_DOUBLE_OPS) 1780 .Case("rv770", GK_R700_DOUBLE_OPS) 1781 .Case("palm", GK_EVERGREEN) 1782 .Case("cedar", GK_EVERGREEN) 1783 .Case("sumo", GK_EVERGREEN) 1784 .Case("sumo2", GK_EVERGREEN) 1785 .Case("redwood", GK_EVERGREEN) 1786 .Case("juniper", GK_EVERGREEN) 1787 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1788 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1789 .Case("barts", GK_NORTHERN_ISLANDS) 1790 .Case("turks", GK_NORTHERN_ISLANDS) 1791 .Case("caicos", GK_NORTHERN_ISLANDS) 1792 .Case("cayman", GK_CAYMAN) 1793 .Case("aruba", GK_CAYMAN) 1794 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1795 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1796 .Case("verde", GK_SOUTHERN_ISLANDS) 1797 .Case("oland", GK_SOUTHERN_ISLANDS) 1798 .Case("hainan", GK_SOUTHERN_ISLANDS) 1799 .Case("bonaire", GK_SEA_ISLANDS) 1800 .Case("kabini", GK_SEA_ISLANDS) 1801 .Case("kaveri", GK_SEA_ISLANDS) 1802 .Case("hawaii", GK_SEA_ISLANDS) 1803 .Case("mullins", GK_SEA_ISLANDS) 1804 .Default(GK_NONE); 1805 1806 if (GPU == GK_NONE) { 1807 return false; 1808 } 1809 1810 // Set the correct data layout 1811 switch (GPU) { 1812 case GK_NONE: 1813 case GK_R600: 1814 case GK_R700: 1815 case GK_EVERGREEN: 1816 case GK_NORTHERN_ISLANDS: 1817 DescriptionString = DescriptionStringR600; 1818 hasFP64 = false; 1819 break; 1820 case GK_R600_DOUBLE_OPS: 1821 case GK_R700_DOUBLE_OPS: 1822 case GK_EVERGREEN_DOUBLE_OPS: 1823 case GK_CAYMAN: 1824 DescriptionString = DescriptionStringR600DoubleOps; 1825 hasFP64 = true; 1826 break; 1827 case GK_SOUTHERN_ISLANDS: 1828 case GK_SEA_ISLANDS: 1829 DescriptionString = DescriptionStringSI; 1830 hasFP64 = true; 1831 break; 1832 } 1833 1834 return true; 1835 } 1836 }; 1837 1838 const Builtin::Info R600TargetInfo::BuiltinInfo[] = { 1839 #define BUILTIN(ID, TYPE, ATTRS) \ 1840 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1841 #include "clang/Basic/BuiltinsR600.def" 1842 }; 1843 const char * const R600TargetInfo::GCCRegNames[] = { 1844 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1845 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1846 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1847 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1848 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1849 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1850 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1851 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1852 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1853 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1854 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1855 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1856 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1857 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1858 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1859 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1860 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1861 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1862 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1863 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1864 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1865 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1866 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1867 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1868 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1869 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1870 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1871 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1872 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1873 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1874 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1875 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1876 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1877 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1878 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1879 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1880 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1881 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1882 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1883 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1884 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1885 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 1886 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 1887 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 1888 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 1889 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 1890 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 1891 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 1892 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 1893 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 1894 }; 1895 1896 void R600TargetInfo::getGCCRegNames(const char * const *&Names, 1897 unsigned &NumNames) const { 1898 Names = GCCRegNames; 1899 NumNames = llvm::array_lengthof(GCCRegNames); 1900 } 1901 1902 // Namespace for x86 abstract base class 1903 const Builtin::Info BuiltinInfo[] = { 1904 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1905 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1906 ALL_LANGUAGES }, 1907 #include "clang/Basic/BuiltinsX86.def" 1908 }; 1909 1910 static const char* const GCCRegNames[] = { 1911 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1912 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1913 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1914 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1915 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1916 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1917 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1918 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1919 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1920 }; 1921 1922 const TargetInfo::AddlRegName AddlRegNames[] = { 1923 { { "al", "ah", "eax", "rax" }, 0 }, 1924 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1925 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1926 { { "dl", "dh", "edx", "rdx" }, 1 }, 1927 { { "esi", "rsi" }, 4 }, 1928 { { "edi", "rdi" }, 5 }, 1929 { { "esp", "rsp" }, 7 }, 1930 { { "ebp", "rbp" }, 6 }, 1931 }; 1932 1933 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1934 // most of the implementation can be shared. 1935 class X86TargetInfo : public TargetInfo { 1936 enum X86SSEEnum { 1937 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1938 } SSELevel; 1939 enum MMX3DNowEnum { 1940 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1941 } MMX3DNowLevel; 1942 enum XOPEnum { 1943 NoXOP, 1944 SSE4A, 1945 FMA4, 1946 XOP 1947 } XOPLevel; 1948 1949 bool HasAES; 1950 bool HasPCLMUL; 1951 bool HasLZCNT; 1952 bool HasRDRND; 1953 bool HasFSGSBASE; 1954 bool HasBMI; 1955 bool HasBMI2; 1956 bool HasPOPCNT; 1957 bool HasRTM; 1958 bool HasPRFCHW; 1959 bool HasRDSEED; 1960 bool HasADX; 1961 bool HasTBM; 1962 bool HasFMA; 1963 bool HasF16C; 1964 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 1965 HasAVX512VL; 1966 bool HasSHA; 1967 bool HasCX16; 1968 1969 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1970 /// 1971 /// Each enumeration represents a particular CPU supported by Clang. These 1972 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1973 enum CPUKind { 1974 CK_Generic, 1975 1976 /// \name i386 1977 /// i386-generation processors. 1978 //@{ 1979 CK_i386, 1980 //@} 1981 1982 /// \name i486 1983 /// i486-generation processors. 1984 //@{ 1985 CK_i486, 1986 CK_WinChipC6, 1987 CK_WinChip2, 1988 CK_C3, 1989 //@} 1990 1991 /// \name i586 1992 /// i586-generation processors, P5 microarchitecture based. 1993 //@{ 1994 CK_i586, 1995 CK_Pentium, 1996 CK_PentiumMMX, 1997 //@} 1998 1999 /// \name i686 2000 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2001 //@{ 2002 CK_i686, 2003 CK_PentiumPro, 2004 CK_Pentium2, 2005 CK_Pentium3, 2006 CK_Pentium3M, 2007 CK_PentiumM, 2008 CK_C3_2, 2009 2010 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2011 /// Clang however has some logic to suport this. 2012 // FIXME: Warn, deprecate, and potentially remove this. 2013 CK_Yonah, 2014 //@} 2015 2016 /// \name Netburst 2017 /// Netburst microarchitecture based processors. 2018 //@{ 2019 CK_Pentium4, 2020 CK_Pentium4M, 2021 CK_Prescott, 2022 CK_Nocona, 2023 //@} 2024 2025 /// \name Core 2026 /// Core microarchitecture based processors. 2027 //@{ 2028 CK_Core2, 2029 2030 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2031 /// codename which GCC no longer accepts as an option to -march, but Clang 2032 /// has some logic for recognizing it. 2033 // FIXME: Warn, deprecate, and potentially remove this. 2034 CK_Penryn, 2035 //@} 2036 2037 /// \name Atom 2038 /// Atom processors 2039 //@{ 2040 CK_Bonnell, 2041 CK_Silvermont, 2042 //@} 2043 2044 /// \name Nehalem 2045 /// Nehalem microarchitecture based processors. 2046 CK_Nehalem, 2047 2048 /// \name Westmere 2049 /// Westmere microarchitecture based processors. 2050 CK_Westmere, 2051 2052 /// \name Sandy Bridge 2053 /// Sandy Bridge microarchitecture based processors. 2054 CK_SandyBridge, 2055 2056 /// \name Ivy Bridge 2057 /// Ivy Bridge microarchitecture based processors. 2058 CK_IvyBridge, 2059 2060 /// \name Haswell 2061 /// Haswell microarchitecture based processors. 2062 CK_Haswell, 2063 2064 /// \name Broadwell 2065 /// Broadwell microarchitecture based processors. 2066 CK_Broadwell, 2067 2068 /// \name Skylake 2069 /// Skylake microarchitecture based processors. 2070 CK_Skylake, 2071 2072 /// \name Knights Landing 2073 /// Knights Landing processor. 2074 CK_KNL, 2075 2076 /// \name K6 2077 /// K6 architecture processors. 2078 //@{ 2079 CK_K6, 2080 CK_K6_2, 2081 CK_K6_3, 2082 //@} 2083 2084 /// \name K7 2085 /// K7 architecture processors. 2086 //@{ 2087 CK_Athlon, 2088 CK_AthlonThunderbird, 2089 CK_Athlon4, 2090 CK_AthlonXP, 2091 CK_AthlonMP, 2092 //@} 2093 2094 /// \name K8 2095 /// K8 architecture processors. 2096 //@{ 2097 CK_Athlon64, 2098 CK_Athlon64SSE3, 2099 CK_AthlonFX, 2100 CK_K8, 2101 CK_K8SSE3, 2102 CK_Opteron, 2103 CK_OpteronSSE3, 2104 CK_AMDFAM10, 2105 //@} 2106 2107 /// \name Bobcat 2108 /// Bobcat architecture processors. 2109 //@{ 2110 CK_BTVER1, 2111 CK_BTVER2, 2112 //@} 2113 2114 /// \name Bulldozer 2115 /// Bulldozer architecture processors. 2116 //@{ 2117 CK_BDVER1, 2118 CK_BDVER2, 2119 CK_BDVER3, 2120 CK_BDVER4, 2121 //@} 2122 2123 /// This specification is deprecated and will be removed in the future. 2124 /// Users should prefer \see CK_K8. 2125 // FIXME: Warn on this when the CPU is set to it. 2126 //@{ 2127 CK_x86_64, 2128 //@} 2129 2130 /// \name Geode 2131 /// Geode processors. 2132 //@{ 2133 CK_Geode 2134 //@} 2135 } CPU; 2136 2137 enum FPMathKind { 2138 FP_Default, 2139 FP_SSE, 2140 FP_387 2141 } FPMath; 2142 2143 public: 2144 X86TargetInfo(const llvm::Triple &Triple) 2145 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 2146 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 2147 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 2148 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 2149 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 2150 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 2151 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 2152 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 2153 BigEndian = false; 2154 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2155 } 2156 unsigned getFloatEvalMethod() const override { 2157 // X87 evaluates with 80 bits "long double" precision. 2158 return SSELevel == NoSSE ? 2 : 0; 2159 } 2160 void getTargetBuiltins(const Builtin::Info *&Records, 2161 unsigned &NumRecords) const override { 2162 Records = BuiltinInfo; 2163 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 2164 } 2165 void getGCCRegNames(const char * const *&Names, 2166 unsigned &NumNames) const override { 2167 Names = GCCRegNames; 2168 NumNames = llvm::array_lengthof(GCCRegNames); 2169 } 2170 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2171 unsigned &NumAliases) const override { 2172 Aliases = nullptr; 2173 NumAliases = 0; 2174 } 2175 void getGCCAddlRegNames(const AddlRegName *&Names, 2176 unsigned &NumNames) const override { 2177 Names = AddlRegNames; 2178 NumNames = llvm::array_lengthof(AddlRegNames); 2179 } 2180 bool validateAsmConstraint(const char *&Name, 2181 TargetInfo::ConstraintInfo &info) const override; 2182 2183 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2184 2185 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2186 2187 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2188 2189 std::string convertConstraint(const char *&Constraint) const override; 2190 const char *getClobbers() const override { 2191 return "~{dirflag},~{fpsr},~{flags}"; 2192 } 2193 void getTargetDefines(const LangOptions &Opts, 2194 MacroBuilder &Builder) const override; 2195 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2196 bool Enabled); 2197 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2198 bool Enabled); 2199 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2200 bool Enabled); 2201 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2202 StringRef Name, bool Enabled) const override { 2203 setFeatureEnabledImpl(Features, Name, Enabled); 2204 } 2205 // This exists purely to cut down on the number of virtual calls in 2206 // getDefaultFeatures which calls this repeatedly. 2207 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2208 StringRef Name, bool Enabled); 2209 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 2210 bool hasFeature(StringRef Feature) const override; 2211 bool handleTargetFeatures(std::vector<std::string> &Features, 2212 DiagnosticsEngine &Diags) override; 2213 StringRef getABI() const override { 2214 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2215 return "avx"; 2216 else if (getTriple().getArch() == llvm::Triple::x86 && 2217 MMX3DNowLevel == NoMMX3DNow) 2218 return "no-mmx"; 2219 return ""; 2220 } 2221 bool setCPU(const std::string &Name) override { 2222 CPU = llvm::StringSwitch<CPUKind>(Name) 2223 .Case("i386", CK_i386) 2224 .Case("i486", CK_i486) 2225 .Case("winchip-c6", CK_WinChipC6) 2226 .Case("winchip2", CK_WinChip2) 2227 .Case("c3", CK_C3) 2228 .Case("i586", CK_i586) 2229 .Case("pentium", CK_Pentium) 2230 .Case("pentium-mmx", CK_PentiumMMX) 2231 .Case("i686", CK_i686) 2232 .Case("pentiumpro", CK_PentiumPro) 2233 .Case("pentium2", CK_Pentium2) 2234 .Case("pentium3", CK_Pentium3) 2235 .Case("pentium3m", CK_Pentium3M) 2236 .Case("pentium-m", CK_PentiumM) 2237 .Case("c3-2", CK_C3_2) 2238 .Case("yonah", CK_Yonah) 2239 .Case("pentium4", CK_Pentium4) 2240 .Case("pentium4m", CK_Pentium4M) 2241 .Case("prescott", CK_Prescott) 2242 .Case("nocona", CK_Nocona) 2243 .Case("core2", CK_Core2) 2244 .Case("penryn", CK_Penryn) 2245 .Case("bonnell", CK_Bonnell) 2246 .Case("atom", CK_Bonnell) // Legacy name. 2247 .Case("silvermont", CK_Silvermont) 2248 .Case("slm", CK_Silvermont) // Legacy name. 2249 .Case("nehalem", CK_Nehalem) 2250 .Case("corei7", CK_Nehalem) // Legacy name. 2251 .Case("westmere", CK_Westmere) 2252 .Case("sandybridge", CK_SandyBridge) 2253 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2254 .Case("ivybridge", CK_IvyBridge) 2255 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2256 .Case("haswell", CK_Haswell) 2257 .Case("core-avx2", CK_Haswell) // Legacy name. 2258 .Case("broadwell", CK_Broadwell) 2259 .Case("skylake", CK_Skylake) 2260 .Case("skx", CK_Skylake) // Legacy name. 2261 .Case("knl", CK_KNL) 2262 .Case("k6", CK_K6) 2263 .Case("k6-2", CK_K6_2) 2264 .Case("k6-3", CK_K6_3) 2265 .Case("athlon", CK_Athlon) 2266 .Case("athlon-tbird", CK_AthlonThunderbird) 2267 .Case("athlon-4", CK_Athlon4) 2268 .Case("athlon-xp", CK_AthlonXP) 2269 .Case("athlon-mp", CK_AthlonMP) 2270 .Case("athlon64", CK_Athlon64) 2271 .Case("athlon64-sse3", CK_Athlon64SSE3) 2272 .Case("athlon-fx", CK_AthlonFX) 2273 .Case("k8", CK_K8) 2274 .Case("k8-sse3", CK_K8SSE3) 2275 .Case("opteron", CK_Opteron) 2276 .Case("opteron-sse3", CK_OpteronSSE3) 2277 .Case("barcelona", CK_AMDFAM10) 2278 .Case("amdfam10", CK_AMDFAM10) 2279 .Case("btver1", CK_BTVER1) 2280 .Case("btver2", CK_BTVER2) 2281 .Case("bdver1", CK_BDVER1) 2282 .Case("bdver2", CK_BDVER2) 2283 .Case("bdver3", CK_BDVER3) 2284 .Case("bdver4", CK_BDVER4) 2285 .Case("x86-64", CK_x86_64) 2286 .Case("geode", CK_Geode) 2287 .Default(CK_Generic); 2288 2289 // Perform any per-CPU checks necessary to determine if this CPU is 2290 // acceptable. 2291 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2292 // invalid without explaining *why*. 2293 switch (CPU) { 2294 case CK_Generic: 2295 // No processor selected! 2296 return false; 2297 2298 case CK_i386: 2299 case CK_i486: 2300 case CK_WinChipC6: 2301 case CK_WinChip2: 2302 case CK_C3: 2303 case CK_i586: 2304 case CK_Pentium: 2305 case CK_PentiumMMX: 2306 case CK_i686: 2307 case CK_PentiumPro: 2308 case CK_Pentium2: 2309 case CK_Pentium3: 2310 case CK_Pentium3M: 2311 case CK_PentiumM: 2312 case CK_Yonah: 2313 case CK_C3_2: 2314 case CK_Pentium4: 2315 case CK_Pentium4M: 2316 case CK_Prescott: 2317 case CK_K6: 2318 case CK_K6_2: 2319 case CK_K6_3: 2320 case CK_Athlon: 2321 case CK_AthlonThunderbird: 2322 case CK_Athlon4: 2323 case CK_AthlonXP: 2324 case CK_AthlonMP: 2325 case CK_Geode: 2326 // Only accept certain architectures when compiling in 32-bit mode. 2327 if (getTriple().getArch() != llvm::Triple::x86) 2328 return false; 2329 2330 // Fallthrough 2331 case CK_Nocona: 2332 case CK_Core2: 2333 case CK_Penryn: 2334 case CK_Bonnell: 2335 case CK_Silvermont: 2336 case CK_Nehalem: 2337 case CK_Westmere: 2338 case CK_SandyBridge: 2339 case CK_IvyBridge: 2340 case CK_Haswell: 2341 case CK_Broadwell: 2342 case CK_Skylake: 2343 case CK_KNL: 2344 case CK_Athlon64: 2345 case CK_Athlon64SSE3: 2346 case CK_AthlonFX: 2347 case CK_K8: 2348 case CK_K8SSE3: 2349 case CK_Opteron: 2350 case CK_OpteronSSE3: 2351 case CK_AMDFAM10: 2352 case CK_BTVER1: 2353 case CK_BTVER2: 2354 case CK_BDVER1: 2355 case CK_BDVER2: 2356 case CK_BDVER3: 2357 case CK_BDVER4: 2358 case CK_x86_64: 2359 return true; 2360 } 2361 llvm_unreachable("Unhandled CPU kind"); 2362 } 2363 2364 bool setFPMath(StringRef Name) override; 2365 2366 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2367 // We accept all non-ARM calling conventions 2368 return (CC == CC_X86ThisCall || 2369 CC == CC_X86FastCall || 2370 CC == CC_X86StdCall || 2371 CC == CC_X86VectorCall || 2372 CC == CC_C || 2373 CC == CC_X86Pascal || 2374 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2375 } 2376 2377 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2378 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2379 } 2380 2381 bool hasSjLjLowering() const override { 2382 return true; 2383 } 2384 }; 2385 2386 bool X86TargetInfo::setFPMath(StringRef Name) { 2387 if (Name == "387") { 2388 FPMath = FP_387; 2389 return true; 2390 } 2391 if (Name == "sse") { 2392 FPMath = FP_SSE; 2393 return true; 2394 } 2395 return false; 2396 } 2397 2398 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2399 // FIXME: This *really* should not be here. 2400 2401 // X86_64 always has SSE2. 2402 if (getTriple().getArch() == llvm::Triple::x86_64) 2403 setFeatureEnabledImpl(Features, "sse2", true); 2404 2405 switch (CPU) { 2406 case CK_Generic: 2407 case CK_i386: 2408 case CK_i486: 2409 case CK_i586: 2410 case CK_Pentium: 2411 case CK_i686: 2412 case CK_PentiumPro: 2413 break; 2414 case CK_PentiumMMX: 2415 case CK_Pentium2: 2416 case CK_K6: 2417 case CK_WinChipC6: 2418 setFeatureEnabledImpl(Features, "mmx", true); 2419 break; 2420 case CK_Pentium3: 2421 case CK_Pentium3M: 2422 case CK_C3_2: 2423 setFeatureEnabledImpl(Features, "sse", true); 2424 break; 2425 case CK_PentiumM: 2426 case CK_Pentium4: 2427 case CK_Pentium4M: 2428 case CK_x86_64: 2429 setFeatureEnabledImpl(Features, "sse2", true); 2430 break; 2431 case CK_Yonah: 2432 case CK_Prescott: 2433 case CK_Nocona: 2434 setFeatureEnabledImpl(Features, "sse3", true); 2435 setFeatureEnabledImpl(Features, "cx16", true); 2436 break; 2437 case CK_Core2: 2438 case CK_Bonnell: 2439 setFeatureEnabledImpl(Features, "ssse3", true); 2440 setFeatureEnabledImpl(Features, "cx16", true); 2441 break; 2442 case CK_Penryn: 2443 setFeatureEnabledImpl(Features, "sse4.1", true); 2444 setFeatureEnabledImpl(Features, "cx16", true); 2445 break; 2446 case CK_Skylake: 2447 setFeatureEnabledImpl(Features, "avx512f", true); 2448 setFeatureEnabledImpl(Features, "avx512cd", true); 2449 setFeatureEnabledImpl(Features, "avx512dq", true); 2450 setFeatureEnabledImpl(Features, "avx512bw", true); 2451 setFeatureEnabledImpl(Features, "avx512vl", true); 2452 // FALLTHROUGH 2453 case CK_Broadwell: 2454 setFeatureEnabledImpl(Features, "rdseed", true); 2455 setFeatureEnabledImpl(Features, "adx", true); 2456 // FALLTHROUGH 2457 case CK_Haswell: 2458 setFeatureEnabledImpl(Features, "avx2", true); 2459 setFeatureEnabledImpl(Features, "lzcnt", true); 2460 setFeatureEnabledImpl(Features, "bmi", true); 2461 setFeatureEnabledImpl(Features, "bmi2", true); 2462 setFeatureEnabledImpl(Features, "rtm", true); 2463 setFeatureEnabledImpl(Features, "fma", true); 2464 // FALLTHROUGH 2465 case CK_IvyBridge: 2466 setFeatureEnabledImpl(Features, "rdrnd", true); 2467 setFeatureEnabledImpl(Features, "f16c", true); 2468 setFeatureEnabledImpl(Features, "fsgsbase", true); 2469 // FALLTHROUGH 2470 case CK_SandyBridge: 2471 setFeatureEnabledImpl(Features, "avx", true); 2472 // FALLTHROUGH 2473 case CK_Westmere: 2474 case CK_Silvermont: 2475 setFeatureEnabledImpl(Features, "aes", true); 2476 setFeatureEnabledImpl(Features, "pclmul", true); 2477 // FALLTHROUGH 2478 case CK_Nehalem: 2479 setFeatureEnabledImpl(Features, "sse4.2", true); 2480 setFeatureEnabledImpl(Features, "cx16", true); 2481 break; 2482 case CK_KNL: 2483 setFeatureEnabledImpl(Features, "avx512f", true); 2484 setFeatureEnabledImpl(Features, "avx512cd", true); 2485 setFeatureEnabledImpl(Features, "avx512er", true); 2486 setFeatureEnabledImpl(Features, "avx512pf", true); 2487 setFeatureEnabledImpl(Features, "rdseed", true); 2488 setFeatureEnabledImpl(Features, "adx", true); 2489 setFeatureEnabledImpl(Features, "lzcnt", true); 2490 setFeatureEnabledImpl(Features, "bmi", true); 2491 setFeatureEnabledImpl(Features, "bmi2", true); 2492 setFeatureEnabledImpl(Features, "rtm", true); 2493 setFeatureEnabledImpl(Features, "fma", true); 2494 setFeatureEnabledImpl(Features, "rdrnd", true); 2495 setFeatureEnabledImpl(Features, "f16c", true); 2496 setFeatureEnabledImpl(Features, "fsgsbase", true); 2497 setFeatureEnabledImpl(Features, "aes", true); 2498 setFeatureEnabledImpl(Features, "pclmul", true); 2499 setFeatureEnabledImpl(Features, "cx16", true); 2500 break; 2501 case CK_K6_2: 2502 case CK_K6_3: 2503 case CK_WinChip2: 2504 case CK_C3: 2505 setFeatureEnabledImpl(Features, "3dnow", true); 2506 break; 2507 case CK_Athlon: 2508 case CK_AthlonThunderbird: 2509 case CK_Geode: 2510 setFeatureEnabledImpl(Features, "3dnowa", true); 2511 break; 2512 case CK_Athlon4: 2513 case CK_AthlonXP: 2514 case CK_AthlonMP: 2515 setFeatureEnabledImpl(Features, "sse", true); 2516 setFeatureEnabledImpl(Features, "3dnowa", true); 2517 break; 2518 case CK_K8: 2519 case CK_Opteron: 2520 case CK_Athlon64: 2521 case CK_AthlonFX: 2522 setFeatureEnabledImpl(Features, "sse2", true); 2523 setFeatureEnabledImpl(Features, "3dnowa", true); 2524 break; 2525 case CK_AMDFAM10: 2526 setFeatureEnabledImpl(Features, "sse4a", true); 2527 setFeatureEnabledImpl(Features, "lzcnt", true); 2528 setFeatureEnabledImpl(Features, "popcnt", true); 2529 // FALLTHROUGH 2530 case CK_K8SSE3: 2531 case CK_OpteronSSE3: 2532 case CK_Athlon64SSE3: 2533 setFeatureEnabledImpl(Features, "sse3", true); 2534 setFeatureEnabledImpl(Features, "3dnowa", true); 2535 break; 2536 case CK_BTVER2: 2537 setFeatureEnabledImpl(Features, "avx", true); 2538 setFeatureEnabledImpl(Features, "aes", true); 2539 setFeatureEnabledImpl(Features, "pclmul", true); 2540 setFeatureEnabledImpl(Features, "bmi", true); 2541 setFeatureEnabledImpl(Features, "f16c", true); 2542 // FALLTHROUGH 2543 case CK_BTVER1: 2544 setFeatureEnabledImpl(Features, "ssse3", true); 2545 setFeatureEnabledImpl(Features, "sse4a", true); 2546 setFeatureEnabledImpl(Features, "lzcnt", true); 2547 setFeatureEnabledImpl(Features, "popcnt", true); 2548 setFeatureEnabledImpl(Features, "prfchw", true); 2549 setFeatureEnabledImpl(Features, "cx16", true); 2550 break; 2551 case CK_BDVER4: 2552 setFeatureEnabledImpl(Features, "avx2", true); 2553 setFeatureEnabledImpl(Features, "bmi2", true); 2554 // FALLTHROUGH 2555 case CK_BDVER3: 2556 setFeatureEnabledImpl(Features, "fsgsbase", true); 2557 // FALLTHROUGH 2558 case CK_BDVER2: 2559 setFeatureEnabledImpl(Features, "bmi", true); 2560 setFeatureEnabledImpl(Features, "fma", true); 2561 setFeatureEnabledImpl(Features, "f16c", true); 2562 setFeatureEnabledImpl(Features, "tbm", true); 2563 // FALLTHROUGH 2564 case CK_BDVER1: 2565 // xop implies avx, sse4a and fma4. 2566 setFeatureEnabledImpl(Features, "xop", true); 2567 setFeatureEnabledImpl(Features, "lzcnt", true); 2568 setFeatureEnabledImpl(Features, "aes", true); 2569 setFeatureEnabledImpl(Features, "pclmul", true); 2570 setFeatureEnabledImpl(Features, "prfchw", true); 2571 setFeatureEnabledImpl(Features, "cx16", true); 2572 break; 2573 } 2574 } 2575 2576 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2577 X86SSEEnum Level, bool Enabled) { 2578 if (Enabled) { 2579 switch (Level) { 2580 case AVX512F: 2581 Features["avx512f"] = true; 2582 case AVX2: 2583 Features["avx2"] = true; 2584 case AVX: 2585 Features["avx"] = true; 2586 case SSE42: 2587 Features["sse4.2"] = true; 2588 case SSE41: 2589 Features["sse4.1"] = true; 2590 case SSSE3: 2591 Features["ssse3"] = true; 2592 case SSE3: 2593 Features["sse3"] = true; 2594 case SSE2: 2595 Features["sse2"] = true; 2596 case SSE1: 2597 Features["sse"] = true; 2598 case NoSSE: 2599 break; 2600 } 2601 return; 2602 } 2603 2604 switch (Level) { 2605 case NoSSE: 2606 case SSE1: 2607 Features["sse"] = false; 2608 case SSE2: 2609 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2610 Features["sha"] = false; 2611 case SSE3: 2612 Features["sse3"] = false; 2613 setXOPLevel(Features, NoXOP, false); 2614 case SSSE3: 2615 Features["ssse3"] = false; 2616 case SSE41: 2617 Features["sse4.1"] = false; 2618 case SSE42: 2619 Features["sse4.2"] = false; 2620 case AVX: 2621 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2622 setXOPLevel(Features, FMA4, false); 2623 case AVX2: 2624 Features["avx2"] = false; 2625 case AVX512F: 2626 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2627 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2628 Features["avx512vl"] = false; 2629 } 2630 } 2631 2632 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2633 MMX3DNowEnum Level, bool Enabled) { 2634 if (Enabled) { 2635 switch (Level) { 2636 case AMD3DNowAthlon: 2637 Features["3dnowa"] = true; 2638 case AMD3DNow: 2639 Features["3dnow"] = true; 2640 case MMX: 2641 Features["mmx"] = true; 2642 case NoMMX3DNow: 2643 break; 2644 } 2645 return; 2646 } 2647 2648 switch (Level) { 2649 case NoMMX3DNow: 2650 case MMX: 2651 Features["mmx"] = false; 2652 case AMD3DNow: 2653 Features["3dnow"] = false; 2654 case AMD3DNowAthlon: 2655 Features["3dnowa"] = false; 2656 } 2657 } 2658 2659 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2660 bool Enabled) { 2661 if (Enabled) { 2662 switch (Level) { 2663 case XOP: 2664 Features["xop"] = true; 2665 case FMA4: 2666 Features["fma4"] = true; 2667 setSSELevel(Features, AVX, true); 2668 case SSE4A: 2669 Features["sse4a"] = true; 2670 setSSELevel(Features, SSE3, true); 2671 case NoXOP: 2672 break; 2673 } 2674 return; 2675 } 2676 2677 switch (Level) { 2678 case NoXOP: 2679 case SSE4A: 2680 Features["sse4a"] = false; 2681 case FMA4: 2682 Features["fma4"] = false; 2683 case XOP: 2684 Features["xop"] = false; 2685 } 2686 } 2687 2688 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2689 StringRef Name, bool Enabled) { 2690 Features[Name] = Enabled; 2691 2692 if (Name == "mmx") { 2693 setMMXLevel(Features, MMX, Enabled); 2694 } else if (Name == "sse") { 2695 setSSELevel(Features, SSE1, Enabled); 2696 } else if (Name == "sse2") { 2697 setSSELevel(Features, SSE2, Enabled); 2698 } else if (Name == "sse3") { 2699 setSSELevel(Features, SSE3, Enabled); 2700 } else if (Name == "ssse3") { 2701 setSSELevel(Features, SSSE3, Enabled); 2702 } else if (Name == "sse4.2") { 2703 setSSELevel(Features, SSE42, Enabled); 2704 } else if (Name == "sse4.1") { 2705 setSSELevel(Features, SSE41, Enabled); 2706 } else if (Name == "3dnow") { 2707 setMMXLevel(Features, AMD3DNow, Enabled); 2708 } else if (Name == "3dnowa") { 2709 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2710 } else if (Name == "aes") { 2711 if (Enabled) 2712 setSSELevel(Features, SSE2, Enabled); 2713 } else if (Name == "pclmul") { 2714 if (Enabled) 2715 setSSELevel(Features, SSE2, Enabled); 2716 } else if (Name == "avx") { 2717 setSSELevel(Features, AVX, Enabled); 2718 } else if (Name == "avx2") { 2719 setSSELevel(Features, AVX2, Enabled); 2720 } else if (Name == "avx512f") { 2721 setSSELevel(Features, AVX512F, Enabled); 2722 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2723 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2724 if (Enabled) 2725 setSSELevel(Features, AVX512F, Enabled); 2726 } else if (Name == "fma") { 2727 if (Enabled) 2728 setSSELevel(Features, AVX, Enabled); 2729 } else if (Name == "fma4") { 2730 setXOPLevel(Features, FMA4, Enabled); 2731 } else if (Name == "xop") { 2732 setXOPLevel(Features, XOP, Enabled); 2733 } else if (Name == "sse4a") { 2734 setXOPLevel(Features, SSE4A, Enabled); 2735 } else if (Name == "f16c") { 2736 if (Enabled) 2737 setSSELevel(Features, AVX, Enabled); 2738 } else if (Name == "sha") { 2739 if (Enabled) 2740 setSSELevel(Features, SSE2, Enabled); 2741 } 2742 } 2743 2744 /// handleTargetFeatures - Perform initialization based on the user 2745 /// configured set of features. 2746 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2747 DiagnosticsEngine &Diags) { 2748 // Remember the maximum enabled sselevel. 2749 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2750 // Ignore disabled features. 2751 if (Features[i][0] == '-') 2752 continue; 2753 2754 StringRef Feature = StringRef(Features[i]).substr(1); 2755 2756 if (Feature == "aes") { 2757 HasAES = true; 2758 continue; 2759 } 2760 2761 if (Feature == "pclmul") { 2762 HasPCLMUL = true; 2763 continue; 2764 } 2765 2766 if (Feature == "lzcnt") { 2767 HasLZCNT = true; 2768 continue; 2769 } 2770 2771 if (Feature == "rdrnd") { 2772 HasRDRND = true; 2773 continue; 2774 } 2775 2776 if (Feature == "fsgsbase") { 2777 HasFSGSBASE = true; 2778 continue; 2779 } 2780 2781 if (Feature == "bmi") { 2782 HasBMI = true; 2783 continue; 2784 } 2785 2786 if (Feature == "bmi2") { 2787 HasBMI2 = true; 2788 continue; 2789 } 2790 2791 if (Feature == "popcnt") { 2792 HasPOPCNT = true; 2793 continue; 2794 } 2795 2796 if (Feature == "rtm") { 2797 HasRTM = true; 2798 continue; 2799 } 2800 2801 if (Feature == "prfchw") { 2802 HasPRFCHW = true; 2803 continue; 2804 } 2805 2806 if (Feature == "rdseed") { 2807 HasRDSEED = true; 2808 continue; 2809 } 2810 2811 if (Feature == "adx") { 2812 HasADX = true; 2813 continue; 2814 } 2815 2816 if (Feature == "tbm") { 2817 HasTBM = true; 2818 continue; 2819 } 2820 2821 if (Feature == "fma") { 2822 HasFMA = true; 2823 continue; 2824 } 2825 2826 if (Feature == "f16c") { 2827 HasF16C = true; 2828 continue; 2829 } 2830 2831 if (Feature == "avx512cd") { 2832 HasAVX512CD = true; 2833 continue; 2834 } 2835 2836 if (Feature == "avx512er") { 2837 HasAVX512ER = true; 2838 continue; 2839 } 2840 2841 if (Feature == "avx512pf") { 2842 HasAVX512PF = true; 2843 continue; 2844 } 2845 2846 if (Feature == "avx512dq") { 2847 HasAVX512DQ = true; 2848 continue; 2849 } 2850 2851 if (Feature == "avx512bw") { 2852 HasAVX512BW = true; 2853 continue; 2854 } 2855 2856 if (Feature == "avx512vl") { 2857 HasAVX512VL = true; 2858 continue; 2859 } 2860 2861 if (Feature == "sha") { 2862 HasSHA = true; 2863 continue; 2864 } 2865 2866 if (Feature == "cx16") { 2867 HasCX16 = true; 2868 continue; 2869 } 2870 2871 assert(Features[i][0] == '+' && "Invalid target feature!"); 2872 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2873 .Case("avx512f", AVX512F) 2874 .Case("avx2", AVX2) 2875 .Case("avx", AVX) 2876 .Case("sse4.2", SSE42) 2877 .Case("sse4.1", SSE41) 2878 .Case("ssse3", SSSE3) 2879 .Case("sse3", SSE3) 2880 .Case("sse2", SSE2) 2881 .Case("sse", SSE1) 2882 .Default(NoSSE); 2883 SSELevel = std::max(SSELevel, Level); 2884 2885 MMX3DNowEnum ThreeDNowLevel = 2886 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2887 .Case("3dnowa", AMD3DNowAthlon) 2888 .Case("3dnow", AMD3DNow) 2889 .Case("mmx", MMX) 2890 .Default(NoMMX3DNow); 2891 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2892 2893 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2894 .Case("xop", XOP) 2895 .Case("fma4", FMA4) 2896 .Case("sse4a", SSE4A) 2897 .Default(NoXOP); 2898 XOPLevel = std::max(XOPLevel, XLevel); 2899 } 2900 2901 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2902 // Can't do this earlier because we need to be able to explicitly enable 2903 // popcnt and still disable sse4.2. 2904 if (!HasPOPCNT && SSELevel >= SSE42 && 2905 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2906 HasPOPCNT = true; 2907 Features.push_back("+popcnt"); 2908 } 2909 2910 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2911 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2912 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2913 HasPRFCHW = true; 2914 Features.push_back("+prfchw"); 2915 } 2916 2917 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2918 // matches the selected sse level. 2919 if (FPMath == FP_SSE && SSELevel < SSE1) { 2920 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2921 return false; 2922 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2923 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2924 return false; 2925 } 2926 2927 // Don't tell the backend if we're turning off mmx; it will end up disabling 2928 // SSE, which we don't want. 2929 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2930 // then enable MMX. 2931 std::vector<std::string>::iterator it; 2932 it = std::find(Features.begin(), Features.end(), "-mmx"); 2933 if (it != Features.end()) 2934 Features.erase(it); 2935 else if (SSELevel > NoSSE) 2936 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2937 return true; 2938 } 2939 2940 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2941 /// definitions for this particular subtarget. 2942 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2943 MacroBuilder &Builder) const { 2944 // Target identification. 2945 if (getTriple().getArch() == llvm::Triple::x86_64) { 2946 Builder.defineMacro("__amd64__"); 2947 Builder.defineMacro("__amd64"); 2948 Builder.defineMacro("__x86_64"); 2949 Builder.defineMacro("__x86_64__"); 2950 if (getTriple().getArchName() == "x86_64h") { 2951 Builder.defineMacro("__x86_64h"); 2952 Builder.defineMacro("__x86_64h__"); 2953 } 2954 } else { 2955 DefineStd(Builder, "i386", Opts); 2956 } 2957 2958 // Subtarget options. 2959 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2960 // truly should be based on -mtune options. 2961 switch (CPU) { 2962 case CK_Generic: 2963 break; 2964 case CK_i386: 2965 // The rest are coming from the i386 define above. 2966 Builder.defineMacro("__tune_i386__"); 2967 break; 2968 case CK_i486: 2969 case CK_WinChipC6: 2970 case CK_WinChip2: 2971 case CK_C3: 2972 defineCPUMacros(Builder, "i486"); 2973 break; 2974 case CK_PentiumMMX: 2975 Builder.defineMacro("__pentium_mmx__"); 2976 Builder.defineMacro("__tune_pentium_mmx__"); 2977 // Fallthrough 2978 case CK_i586: 2979 case CK_Pentium: 2980 defineCPUMacros(Builder, "i586"); 2981 defineCPUMacros(Builder, "pentium"); 2982 break; 2983 case CK_Pentium3: 2984 case CK_Pentium3M: 2985 case CK_PentiumM: 2986 Builder.defineMacro("__tune_pentium3__"); 2987 // Fallthrough 2988 case CK_Pentium2: 2989 case CK_C3_2: 2990 Builder.defineMacro("__tune_pentium2__"); 2991 // Fallthrough 2992 case CK_PentiumPro: 2993 Builder.defineMacro("__tune_i686__"); 2994 Builder.defineMacro("__tune_pentiumpro__"); 2995 // Fallthrough 2996 case CK_i686: 2997 Builder.defineMacro("__i686"); 2998 Builder.defineMacro("__i686__"); 2999 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3000 Builder.defineMacro("__pentiumpro"); 3001 Builder.defineMacro("__pentiumpro__"); 3002 break; 3003 case CK_Pentium4: 3004 case CK_Pentium4M: 3005 defineCPUMacros(Builder, "pentium4"); 3006 break; 3007 case CK_Yonah: 3008 case CK_Prescott: 3009 case CK_Nocona: 3010 defineCPUMacros(Builder, "nocona"); 3011 break; 3012 case CK_Core2: 3013 case CK_Penryn: 3014 defineCPUMacros(Builder, "core2"); 3015 break; 3016 case CK_Bonnell: 3017 defineCPUMacros(Builder, "atom"); 3018 break; 3019 case CK_Silvermont: 3020 defineCPUMacros(Builder, "slm"); 3021 break; 3022 case CK_Nehalem: 3023 case CK_Westmere: 3024 case CK_SandyBridge: 3025 case CK_IvyBridge: 3026 case CK_Haswell: 3027 case CK_Broadwell: 3028 // FIXME: Historically, we defined this legacy name, it would be nice to 3029 // remove it at some point. We've never exposed fine-grained names for 3030 // recent primary x86 CPUs, and we should keep it that way. 3031 defineCPUMacros(Builder, "corei7"); 3032 break; 3033 case CK_Skylake: 3034 // FIXME: Historically, we defined this legacy name, it would be nice to 3035 // remove it at some point. This is the only fine-grained CPU macro in the 3036 // main intel CPU line, and it would be better to not have these and force 3037 // people to use ISA macros. 3038 defineCPUMacros(Builder, "skx"); 3039 break; 3040 case CK_KNL: 3041 defineCPUMacros(Builder, "knl"); 3042 break; 3043 case CK_K6_2: 3044 Builder.defineMacro("__k6_2__"); 3045 Builder.defineMacro("__tune_k6_2__"); 3046 // Fallthrough 3047 case CK_K6_3: 3048 if (CPU != CK_K6_2) { // In case of fallthrough 3049 // FIXME: GCC may be enabling these in cases where some other k6 3050 // architecture is specified but -m3dnow is explicitly provided. The 3051 // exact semantics need to be determined and emulated here. 3052 Builder.defineMacro("__k6_3__"); 3053 Builder.defineMacro("__tune_k6_3__"); 3054 } 3055 // Fallthrough 3056 case CK_K6: 3057 defineCPUMacros(Builder, "k6"); 3058 break; 3059 case CK_Athlon: 3060 case CK_AthlonThunderbird: 3061 case CK_Athlon4: 3062 case CK_AthlonXP: 3063 case CK_AthlonMP: 3064 defineCPUMacros(Builder, "athlon"); 3065 if (SSELevel != NoSSE) { 3066 Builder.defineMacro("__athlon_sse__"); 3067 Builder.defineMacro("__tune_athlon_sse__"); 3068 } 3069 break; 3070 case CK_K8: 3071 case CK_K8SSE3: 3072 case CK_x86_64: 3073 case CK_Opteron: 3074 case CK_OpteronSSE3: 3075 case CK_Athlon64: 3076 case CK_Athlon64SSE3: 3077 case CK_AthlonFX: 3078 defineCPUMacros(Builder, "k8"); 3079 break; 3080 case CK_AMDFAM10: 3081 defineCPUMacros(Builder, "amdfam10"); 3082 break; 3083 case CK_BTVER1: 3084 defineCPUMacros(Builder, "btver1"); 3085 break; 3086 case CK_BTVER2: 3087 defineCPUMacros(Builder, "btver2"); 3088 break; 3089 case CK_BDVER1: 3090 defineCPUMacros(Builder, "bdver1"); 3091 break; 3092 case CK_BDVER2: 3093 defineCPUMacros(Builder, "bdver2"); 3094 break; 3095 case CK_BDVER3: 3096 defineCPUMacros(Builder, "bdver3"); 3097 break; 3098 case CK_BDVER4: 3099 defineCPUMacros(Builder, "bdver4"); 3100 break; 3101 case CK_Geode: 3102 defineCPUMacros(Builder, "geode"); 3103 break; 3104 } 3105 3106 // Target properties. 3107 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3108 3109 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3110 // functions in glibc header files that use FP Stack inline asm which the 3111 // backend can't deal with (PR879). 3112 Builder.defineMacro("__NO_MATH_INLINES"); 3113 3114 if (HasAES) 3115 Builder.defineMacro("__AES__"); 3116 3117 if (HasPCLMUL) 3118 Builder.defineMacro("__PCLMUL__"); 3119 3120 if (HasLZCNT) 3121 Builder.defineMacro("__LZCNT__"); 3122 3123 if (HasRDRND) 3124 Builder.defineMacro("__RDRND__"); 3125 3126 if (HasFSGSBASE) 3127 Builder.defineMacro("__FSGSBASE__"); 3128 3129 if (HasBMI) 3130 Builder.defineMacro("__BMI__"); 3131 3132 if (HasBMI2) 3133 Builder.defineMacro("__BMI2__"); 3134 3135 if (HasPOPCNT) 3136 Builder.defineMacro("__POPCNT__"); 3137 3138 if (HasRTM) 3139 Builder.defineMacro("__RTM__"); 3140 3141 if (HasPRFCHW) 3142 Builder.defineMacro("__PRFCHW__"); 3143 3144 if (HasRDSEED) 3145 Builder.defineMacro("__RDSEED__"); 3146 3147 if (HasADX) 3148 Builder.defineMacro("__ADX__"); 3149 3150 if (HasTBM) 3151 Builder.defineMacro("__TBM__"); 3152 3153 switch (XOPLevel) { 3154 case XOP: 3155 Builder.defineMacro("__XOP__"); 3156 case FMA4: 3157 Builder.defineMacro("__FMA4__"); 3158 case SSE4A: 3159 Builder.defineMacro("__SSE4A__"); 3160 case NoXOP: 3161 break; 3162 } 3163 3164 if (HasFMA) 3165 Builder.defineMacro("__FMA__"); 3166 3167 if (HasF16C) 3168 Builder.defineMacro("__F16C__"); 3169 3170 if (HasAVX512CD) 3171 Builder.defineMacro("__AVX512CD__"); 3172 if (HasAVX512ER) 3173 Builder.defineMacro("__AVX512ER__"); 3174 if (HasAVX512PF) 3175 Builder.defineMacro("__AVX512PF__"); 3176 if (HasAVX512DQ) 3177 Builder.defineMacro("__AVX512DQ__"); 3178 if (HasAVX512BW) 3179 Builder.defineMacro("__AVX512BW__"); 3180 if (HasAVX512VL) 3181 Builder.defineMacro("__AVX512VL__"); 3182 3183 if (HasSHA) 3184 Builder.defineMacro("__SHA__"); 3185 3186 if (HasCX16) 3187 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3188 3189 // Each case falls through to the previous one here. 3190 switch (SSELevel) { 3191 case AVX512F: 3192 Builder.defineMacro("__AVX512F__"); 3193 case AVX2: 3194 Builder.defineMacro("__AVX2__"); 3195 case AVX: 3196 Builder.defineMacro("__AVX__"); 3197 case SSE42: 3198 Builder.defineMacro("__SSE4_2__"); 3199 case SSE41: 3200 Builder.defineMacro("__SSE4_1__"); 3201 case SSSE3: 3202 Builder.defineMacro("__SSSE3__"); 3203 case SSE3: 3204 Builder.defineMacro("__SSE3__"); 3205 case SSE2: 3206 Builder.defineMacro("__SSE2__"); 3207 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3208 case SSE1: 3209 Builder.defineMacro("__SSE__"); 3210 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3211 case NoSSE: 3212 break; 3213 } 3214 3215 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3216 switch (SSELevel) { 3217 case AVX512F: 3218 case AVX2: 3219 case AVX: 3220 case SSE42: 3221 case SSE41: 3222 case SSSE3: 3223 case SSE3: 3224 case SSE2: 3225 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3226 break; 3227 case SSE1: 3228 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3229 break; 3230 default: 3231 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3232 } 3233 } 3234 3235 // Each case falls through to the previous one here. 3236 switch (MMX3DNowLevel) { 3237 case AMD3DNowAthlon: 3238 Builder.defineMacro("__3dNOW_A__"); 3239 case AMD3DNow: 3240 Builder.defineMacro("__3dNOW__"); 3241 case MMX: 3242 Builder.defineMacro("__MMX__"); 3243 case NoMMX3DNow: 3244 break; 3245 } 3246 3247 if (CPU >= CK_i486) { 3248 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3249 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3250 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3251 } 3252 if (CPU >= CK_i586) 3253 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3254 } 3255 3256 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3257 return llvm::StringSwitch<bool>(Feature) 3258 .Case("aes", HasAES) 3259 .Case("avx", SSELevel >= AVX) 3260 .Case("avx2", SSELevel >= AVX2) 3261 .Case("avx512f", SSELevel >= AVX512F) 3262 .Case("avx512cd", HasAVX512CD) 3263 .Case("avx512er", HasAVX512ER) 3264 .Case("avx512pf", HasAVX512PF) 3265 .Case("avx512dq", HasAVX512DQ) 3266 .Case("avx512bw", HasAVX512BW) 3267 .Case("avx512vl", HasAVX512VL) 3268 .Case("bmi", HasBMI) 3269 .Case("bmi2", HasBMI2) 3270 .Case("cx16", HasCX16) 3271 .Case("f16c", HasF16C) 3272 .Case("fma", HasFMA) 3273 .Case("fma4", XOPLevel >= FMA4) 3274 .Case("fsgsbase", HasFSGSBASE) 3275 .Case("lzcnt", HasLZCNT) 3276 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3277 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3278 .Case("mmx", MMX3DNowLevel >= MMX) 3279 .Case("pclmul", HasPCLMUL) 3280 .Case("popcnt", HasPOPCNT) 3281 .Case("prfchw", HasPRFCHW) 3282 .Case("rdrnd", HasRDRND) 3283 .Case("rdseed", HasRDSEED) 3284 .Case("rtm", HasRTM) 3285 .Case("sha", HasSHA) 3286 .Case("sse", SSELevel >= SSE1) 3287 .Case("sse2", SSELevel >= SSE2) 3288 .Case("sse3", SSELevel >= SSE3) 3289 .Case("ssse3", SSELevel >= SSSE3) 3290 .Case("sse4.1", SSELevel >= SSE41) 3291 .Case("sse4.2", SSELevel >= SSE42) 3292 .Case("sse4a", XOPLevel >= SSE4A) 3293 .Case("tbm", HasTBM) 3294 .Case("x86", true) 3295 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3296 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3297 .Case("xop", XOPLevel >= XOP) 3298 .Default(false); 3299 } 3300 3301 bool 3302 X86TargetInfo::validateAsmConstraint(const char *&Name, 3303 TargetInfo::ConstraintInfo &Info) const { 3304 switch (*Name) { 3305 default: return false; 3306 case 'I': 3307 Info.setRequiresImmediate(0, 31); 3308 return true; 3309 case 'J': 3310 Info.setRequiresImmediate(0, 63); 3311 return true; 3312 case 'K': 3313 Info.setRequiresImmediate(-128, 127); 3314 return true; 3315 case 'L': 3316 // FIXME: properly analyze this constraint: 3317 // must be one of 0xff, 0xffff, or 0xffffffff 3318 return true; 3319 case 'M': 3320 Info.setRequiresImmediate(0, 3); 3321 return true; 3322 case 'N': 3323 Info.setRequiresImmediate(0, 255); 3324 return true; 3325 case 'O': 3326 Info.setRequiresImmediate(0, 127); 3327 return true; 3328 case 'Y': // first letter of a pair: 3329 switch (*(Name+1)) { 3330 default: return false; 3331 case '0': // First SSE register. 3332 case 't': // Any SSE register, when SSE2 is enabled. 3333 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3334 case 'm': // any MMX register, when inter-unit moves enabled. 3335 break; // falls through to setAllowsRegister. 3336 } 3337 case 'f': // any x87 floating point stack register. 3338 // Constraint 'f' cannot be used for output operands. 3339 if (Info.ConstraintStr[0] == '=') 3340 return false; 3341 3342 Info.setAllowsRegister(); 3343 return true; 3344 case 'a': // eax. 3345 case 'b': // ebx. 3346 case 'c': // ecx. 3347 case 'd': // edx. 3348 case 'S': // esi. 3349 case 'D': // edi. 3350 case 'A': // edx:eax. 3351 case 't': // top of floating point stack. 3352 case 'u': // second from top of floating point stack. 3353 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3354 case 'y': // Any MMX register. 3355 case 'x': // Any SSE register. 3356 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3357 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3358 case 'l': // "Index" registers: any general register that can be used as an 3359 // index in a base+index memory access. 3360 Info.setAllowsRegister(); 3361 return true; 3362 case 'C': // SSE floating point constant. 3363 case 'G': // x87 floating point constant. 3364 case 'e': // 32-bit signed integer constant for use with zero-extending 3365 // x86_64 instructions. 3366 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3367 // x86_64 instructions. 3368 return true; 3369 } 3370 } 3371 3372 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3373 unsigned Size) const { 3374 // Strip off constraint modifiers. 3375 while (Constraint[0] == '=' || 3376 Constraint[0] == '+' || 3377 Constraint[0] == '&') 3378 Constraint = Constraint.substr(1); 3379 3380 return validateOperandSize(Constraint, Size); 3381 } 3382 3383 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3384 unsigned Size) const { 3385 return validateOperandSize(Constraint, Size); 3386 } 3387 3388 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3389 unsigned Size) const { 3390 switch (Constraint[0]) { 3391 default: break; 3392 case 'y': 3393 return Size <= 64; 3394 case 'f': 3395 case 't': 3396 case 'u': 3397 return Size <= 128; 3398 case 'x': 3399 // 256-bit ymm registers can be used if target supports AVX. 3400 return Size <= (SSELevel >= AVX ? 256U : 128U); 3401 } 3402 3403 return true; 3404 } 3405 3406 std::string 3407 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3408 switch (*Constraint) { 3409 case 'a': return std::string("{ax}"); 3410 case 'b': return std::string("{bx}"); 3411 case 'c': return std::string("{cx}"); 3412 case 'd': return std::string("{dx}"); 3413 case 'S': return std::string("{si}"); 3414 case 'D': return std::string("{di}"); 3415 case 'p': // address 3416 return std::string("im"); 3417 case 't': // top of floating point stack. 3418 return std::string("{st}"); 3419 case 'u': // second from top of floating point stack. 3420 return std::string("{st(1)}"); // second from top of floating point stack. 3421 default: 3422 return std::string(1, *Constraint); 3423 } 3424 } 3425 3426 // X86-32 generic target 3427 class X86_32TargetInfo : public X86TargetInfo { 3428 public: 3429 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3430 DoubleAlign = LongLongAlign = 32; 3431 LongDoubleWidth = 96; 3432 LongDoubleAlign = 32; 3433 SuitableAlign = 128; 3434 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3435 SizeType = UnsignedInt; 3436 PtrDiffType = SignedInt; 3437 IntPtrType = SignedInt; 3438 RegParmMax = 3; 3439 3440 // Use fpret for all types. 3441 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3442 (1 << TargetInfo::Double) | 3443 (1 << TargetInfo::LongDouble)); 3444 3445 // x86-32 has atomics up to 8 bytes 3446 // FIXME: Check that we actually have cmpxchg8b before setting 3447 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3448 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3449 } 3450 BuiltinVaListKind getBuiltinVaListKind() const override { 3451 return TargetInfo::CharPtrBuiltinVaList; 3452 } 3453 3454 int getEHDataRegisterNumber(unsigned RegNo) const override { 3455 if (RegNo == 0) return 0; 3456 if (RegNo == 1) return 2; 3457 return -1; 3458 } 3459 bool validateOperandSize(StringRef Constraint, 3460 unsigned Size) const override { 3461 switch (Constraint[0]) { 3462 default: break; 3463 case 'R': 3464 case 'q': 3465 case 'Q': 3466 case 'a': 3467 case 'b': 3468 case 'c': 3469 case 'd': 3470 case 'S': 3471 case 'D': 3472 return Size <= 32; 3473 case 'A': 3474 return Size <= 64; 3475 } 3476 3477 return X86TargetInfo::validateOperandSize(Constraint, Size); 3478 } 3479 }; 3480 3481 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3482 public: 3483 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3484 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3485 3486 unsigned getFloatEvalMethod() const override { 3487 unsigned Major, Minor, Micro; 3488 getTriple().getOSVersion(Major, Minor, Micro); 3489 // New NetBSD uses the default rounding mode. 3490 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3491 return X86_32TargetInfo::getFloatEvalMethod(); 3492 // NetBSD before 6.99.26 defaults to "double" rounding. 3493 return 1; 3494 } 3495 }; 3496 3497 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3498 public: 3499 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3500 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3501 SizeType = UnsignedLong; 3502 IntPtrType = SignedLong; 3503 PtrDiffType = SignedLong; 3504 } 3505 }; 3506 3507 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3508 public: 3509 BitrigI386TargetInfo(const llvm::Triple &Triple) 3510 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3511 SizeType = UnsignedLong; 3512 IntPtrType = SignedLong; 3513 PtrDiffType = SignedLong; 3514 } 3515 }; 3516 3517 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3518 public: 3519 DarwinI386TargetInfo(const llvm::Triple &Triple) 3520 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3521 LongDoubleWidth = 128; 3522 LongDoubleAlign = 128; 3523 SuitableAlign = 128; 3524 MaxVectorAlign = 256; 3525 SizeType = UnsignedLong; 3526 IntPtrType = SignedLong; 3527 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3528 HasAlignMac68kSupport = true; 3529 } 3530 3531 }; 3532 3533 // x86-32 Windows target 3534 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3535 public: 3536 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3537 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3538 WCharType = UnsignedShort; 3539 DoubleAlign = LongLongAlign = 64; 3540 bool IsWinCOFF = 3541 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3542 DescriptionString = IsWinCOFF 3543 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3544 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3545 } 3546 void getTargetDefines(const LangOptions &Opts, 3547 MacroBuilder &Builder) const override { 3548 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3549 } 3550 }; 3551 3552 // x86-32 Windows Visual Studio target 3553 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3554 public: 3555 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3556 : WindowsX86_32TargetInfo(Triple) { 3557 LongDoubleWidth = LongDoubleAlign = 64; 3558 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3559 } 3560 void getTargetDefines(const LangOptions &Opts, 3561 MacroBuilder &Builder) const override { 3562 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3563 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3564 // The value of the following reflects processor type. 3565 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3566 // We lost the original triple, so we use the default. 3567 Builder.defineMacro("_M_IX86", "600"); 3568 } 3569 }; 3570 } // end anonymous namespace 3571 3572 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3573 Builder.defineMacro("__MSVCRT__"); 3574 Builder.defineMacro("__MINGW32__"); 3575 3576 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports 3577 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3578 // macro anyway for pre-processor compatibility. 3579 if (Opts.MicrosoftExt) 3580 Builder.defineMacro("__declspec", "__declspec"); 3581 else 3582 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3583 3584 if (!Opts.MicrosoftExt) { 3585 // Provide macros for all the calling convention keywords. Provide both 3586 // single and double underscore prefixed variants. These are available on 3587 // x64 as well as x86, even though they have no effect. 3588 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3589 for (const char *CC : CCs) { 3590 std::string GCCSpelling = "__attribute__((__"; 3591 GCCSpelling += CC; 3592 GCCSpelling += "__))"; 3593 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3594 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3595 } 3596 } 3597 } 3598 3599 namespace { 3600 // x86-32 MinGW target 3601 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3602 public: 3603 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3604 : WindowsX86_32TargetInfo(Triple) {} 3605 void getTargetDefines(const LangOptions &Opts, 3606 MacroBuilder &Builder) const override { 3607 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3608 DefineStd(Builder, "WIN32", Opts); 3609 DefineStd(Builder, "WINNT", Opts); 3610 Builder.defineMacro("_X86_"); 3611 addMinGWDefines(Opts, Builder); 3612 } 3613 }; 3614 3615 // x86-32 Cygwin target 3616 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3617 public: 3618 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3619 : X86_32TargetInfo(Triple) { 3620 TLSSupported = false; 3621 WCharType = UnsignedShort; 3622 DoubleAlign = LongLongAlign = 64; 3623 DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3624 } 3625 void getTargetDefines(const LangOptions &Opts, 3626 MacroBuilder &Builder) const override { 3627 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3628 Builder.defineMacro("_X86_"); 3629 Builder.defineMacro("__CYGWIN__"); 3630 Builder.defineMacro("__CYGWIN32__"); 3631 DefineStd(Builder, "unix", Opts); 3632 if (Opts.CPlusPlus) 3633 Builder.defineMacro("_GNU_SOURCE"); 3634 } 3635 }; 3636 3637 // x86-32 Haiku target 3638 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3639 public: 3640 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3641 SizeType = UnsignedLong; 3642 IntPtrType = SignedLong; 3643 PtrDiffType = SignedLong; 3644 ProcessIDType = SignedLong; 3645 this->UserLabelPrefix = ""; 3646 this->TLSSupported = false; 3647 } 3648 void getTargetDefines(const LangOptions &Opts, 3649 MacroBuilder &Builder) const override { 3650 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3651 Builder.defineMacro("__INTEL__"); 3652 Builder.defineMacro("__HAIKU__"); 3653 } 3654 }; 3655 3656 // RTEMS Target 3657 template<typename Target> 3658 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3659 protected: 3660 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3661 MacroBuilder &Builder) const override { 3662 // RTEMS defines; list based off of gcc output 3663 3664 Builder.defineMacro("__rtems__"); 3665 Builder.defineMacro("__ELF__"); 3666 } 3667 3668 public: 3669 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3670 this->UserLabelPrefix = ""; 3671 3672 switch (Triple.getArch()) { 3673 default: 3674 case llvm::Triple::x86: 3675 // this->MCountName = ".mcount"; 3676 break; 3677 case llvm::Triple::mips: 3678 case llvm::Triple::mipsel: 3679 case llvm::Triple::ppc: 3680 case llvm::Triple::ppc64: 3681 case llvm::Triple::ppc64le: 3682 // this->MCountName = "_mcount"; 3683 break; 3684 case llvm::Triple::arm: 3685 // this->MCountName = "__mcount"; 3686 break; 3687 } 3688 } 3689 }; 3690 3691 // x86-32 RTEMS target 3692 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3693 public: 3694 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3695 SizeType = UnsignedLong; 3696 IntPtrType = SignedLong; 3697 PtrDiffType = SignedLong; 3698 this->UserLabelPrefix = ""; 3699 } 3700 void getTargetDefines(const LangOptions &Opts, 3701 MacroBuilder &Builder) const override { 3702 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3703 Builder.defineMacro("__INTEL__"); 3704 Builder.defineMacro("__rtems__"); 3705 } 3706 }; 3707 3708 // x86-64 generic target 3709 class X86_64TargetInfo : public X86TargetInfo { 3710 public: 3711 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3712 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3713 bool IsWinCOFF = 3714 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3715 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3716 LongDoubleWidth = 128; 3717 LongDoubleAlign = 128; 3718 LargeArrayMinWidth = 128; 3719 LargeArrayAlign = 128; 3720 SuitableAlign = 128; 3721 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3722 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3723 IntPtrType = IsX32 ? SignedInt : SignedLong; 3724 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3725 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3726 RegParmMax = 6; 3727 3728 // Pointers are 32-bit in x32. 3729 DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3730 : IsWinCOFF 3731 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3732 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3733 3734 // Use fpret only for long double. 3735 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3736 3737 // Use fp2ret for _Complex long double. 3738 ComplexLongDoubleUsesFP2Ret = true; 3739 3740 // x86-64 has atomics up to 16 bytes. 3741 MaxAtomicPromoteWidth = 128; 3742 MaxAtomicInlineWidth = 128; 3743 } 3744 BuiltinVaListKind getBuiltinVaListKind() const override { 3745 return TargetInfo::X86_64ABIBuiltinVaList; 3746 } 3747 3748 int getEHDataRegisterNumber(unsigned RegNo) const override { 3749 if (RegNo == 0) return 0; 3750 if (RegNo == 1) return 1; 3751 return -1; 3752 } 3753 3754 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3755 return (CC == CC_C || 3756 CC == CC_X86VectorCall || 3757 CC == CC_IntelOclBicc || 3758 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3759 } 3760 3761 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3762 return CC_C; 3763 } 3764 3765 // for x32 we need it here explicitly 3766 bool hasInt128Type() const override { return true; } 3767 }; 3768 3769 // x86-64 Windows target 3770 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3771 public: 3772 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3773 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3774 WCharType = UnsignedShort; 3775 LongWidth = LongAlign = 32; 3776 DoubleAlign = LongLongAlign = 64; 3777 IntMaxType = SignedLongLong; 3778 Int64Type = SignedLongLong; 3779 SizeType = UnsignedLongLong; 3780 PtrDiffType = SignedLongLong; 3781 IntPtrType = SignedLongLong; 3782 this->UserLabelPrefix = ""; 3783 } 3784 3785 void getTargetDefines(const LangOptions &Opts, 3786 MacroBuilder &Builder) const override { 3787 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3788 Builder.defineMacro("_WIN64"); 3789 } 3790 3791 BuiltinVaListKind getBuiltinVaListKind() const override { 3792 return TargetInfo::CharPtrBuiltinVaList; 3793 } 3794 3795 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3796 switch (CC) { 3797 case CC_X86StdCall: 3798 case CC_X86ThisCall: 3799 case CC_X86FastCall: 3800 return CCCR_Ignore; 3801 case CC_C: 3802 case CC_X86VectorCall: 3803 case CC_IntelOclBicc: 3804 case CC_X86_64SysV: 3805 return CCCR_OK; 3806 default: 3807 return CCCR_Warning; 3808 } 3809 } 3810 }; 3811 3812 // x86-64 Windows Visual Studio target 3813 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3814 public: 3815 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3816 : WindowsX86_64TargetInfo(Triple) { 3817 LongDoubleWidth = LongDoubleAlign = 64; 3818 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3819 } 3820 void getTargetDefines(const LangOptions &Opts, 3821 MacroBuilder &Builder) const override { 3822 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3823 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3824 Builder.defineMacro("_M_X64"); 3825 Builder.defineMacro("_M_AMD64"); 3826 } 3827 }; 3828 3829 // x86-64 MinGW target 3830 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3831 public: 3832 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3833 : WindowsX86_64TargetInfo(Triple) {} 3834 void getTargetDefines(const LangOptions &Opts, 3835 MacroBuilder &Builder) const override { 3836 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3837 DefineStd(Builder, "WIN64", Opts); 3838 Builder.defineMacro("__MINGW64__"); 3839 addMinGWDefines(Opts, Builder); 3840 3841 // GCC defines this macro when it is using __gxx_personality_seh0. 3842 if (!Opts.SjLjExceptions) 3843 Builder.defineMacro("__SEH__"); 3844 } 3845 }; 3846 3847 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3848 public: 3849 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3850 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3851 Int64Type = SignedLongLong; 3852 MaxVectorAlign = 256; 3853 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3854 llvm::Triple T = llvm::Triple(Triple); 3855 if (T.isiOS()) 3856 UseSignedCharForObjCBool = false; 3857 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3858 } 3859 }; 3860 3861 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3862 public: 3863 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3864 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3865 IntMaxType = SignedLongLong; 3866 Int64Type = SignedLongLong; 3867 } 3868 }; 3869 3870 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3871 public: 3872 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3873 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3874 IntMaxType = SignedLongLong; 3875 Int64Type = SignedLongLong; 3876 } 3877 }; 3878 3879 class ARMTargetInfo : public TargetInfo { 3880 // Possible FPU choices. 3881 enum FPUMode { 3882 VFP2FPU = (1 << 0), 3883 VFP3FPU = (1 << 1), 3884 VFP4FPU = (1 << 2), 3885 NeonFPU = (1 << 3), 3886 FPARMV8 = (1 << 4) 3887 }; 3888 3889 // Possible HWDiv features. 3890 enum HWDivMode { 3891 HWDivThumb = (1 << 0), 3892 HWDivARM = (1 << 1) 3893 }; 3894 3895 static bool FPUModeIsVFP(FPUMode Mode) { 3896 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3897 } 3898 3899 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3900 static const char * const GCCRegNames[]; 3901 3902 std::string ABI, CPU; 3903 3904 enum { 3905 FP_Default, 3906 FP_VFP, 3907 FP_Neon 3908 } FPMath; 3909 3910 unsigned FPU : 5; 3911 3912 unsigned IsAAPCS : 1; 3913 unsigned IsThumb : 1; 3914 unsigned HWDiv : 2; 3915 3916 // Initialized via features. 3917 unsigned SoftFloat : 1; 3918 unsigned SoftFloatABI : 1; 3919 3920 unsigned CRC : 1; 3921 unsigned Crypto : 1; 3922 3923 // ACLE 6.5.1 Hardware floating point 3924 enum { 3925 HW_FP_HP = (1 << 1), /// half (16-bit) 3926 HW_FP_SP = (1 << 2), /// single (32-bit) 3927 HW_FP_DP = (1 << 3), /// double (64-bit) 3928 }; 3929 uint32_t HW_FP; 3930 3931 static const Builtin::Info BuiltinInfo[]; 3932 3933 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3934 StringRef ArchName = T.getArchName(); 3935 if (T.getArch() == llvm::Triple::arm || 3936 T.getArch() == llvm::Triple::armeb) { 3937 StringRef VersionStr; 3938 if (ArchName.startswith("armv")) 3939 VersionStr = ArchName.substr(4, 1); 3940 else if (ArchName.startswith("armebv")) 3941 VersionStr = ArchName.substr(6, 1); 3942 else 3943 return false; 3944 unsigned Version; 3945 if (VersionStr.getAsInteger(10, Version)) 3946 return false; 3947 return Version >= 6; 3948 } 3949 assert(T.getArch() == llvm::Triple::thumb || 3950 T.getArch() == llvm::Triple::thumbeb); 3951 StringRef VersionStr; 3952 if (ArchName.startswith("thumbv")) 3953 VersionStr = ArchName.substr(6, 1); 3954 else if (ArchName.startswith("thumbebv")) 3955 VersionStr = ArchName.substr(8, 1); 3956 else 3957 return false; 3958 unsigned Version; 3959 if (VersionStr.getAsInteger(10, Version)) 3960 return false; 3961 return Version >= 7; 3962 } 3963 3964 void setABIAAPCS() { 3965 IsAAPCS = true; 3966 3967 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3968 const llvm::Triple &T = getTriple(); 3969 3970 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 3971 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 3972 T.getOS() == llvm::Triple::Bitrig) 3973 SizeType = UnsignedLong; 3974 else 3975 SizeType = UnsignedInt; 3976 3977 switch (T.getOS()) { 3978 case llvm::Triple::NetBSD: 3979 WCharType = SignedInt; 3980 break; 3981 case llvm::Triple::Win32: 3982 WCharType = UnsignedShort; 3983 break; 3984 case llvm::Triple::Linux: 3985 default: 3986 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3987 WCharType = UnsignedInt; 3988 break; 3989 } 3990 3991 UseBitFieldTypeAlignment = true; 3992 3993 ZeroLengthBitfieldBoundary = 0; 3994 3995 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3996 // so set preferred for small types to 32. 3997 if (T.isOSBinFormatMachO()) { 3998 DescriptionString = 3999 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4000 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4001 } else if (T.isOSWindows()) { 4002 assert(!BigEndian && "Windows on ARM does not support big endian"); 4003 DescriptionString = "e" 4004 "-m:w" 4005 "-p:32:32" 4006 "-i64:64" 4007 "-v128:64:128" 4008 "-a:0:32" 4009 "-n32" 4010 "-S64"; 4011 } else if (T.isOSNaCl()) { 4012 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4013 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4014 } else { 4015 DescriptionString = 4016 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4017 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4018 } 4019 4020 // FIXME: Enumerated types are variable width in straight AAPCS. 4021 } 4022 4023 void setABIAPCS() { 4024 const llvm::Triple &T = getTriple(); 4025 4026 IsAAPCS = false; 4027 4028 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4029 4030 // size_t is unsigned int on FreeBSD. 4031 if (T.getOS() == llvm::Triple::FreeBSD) 4032 SizeType = UnsignedInt; 4033 else 4034 SizeType = UnsignedLong; 4035 4036 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4037 WCharType = SignedInt; 4038 4039 // Do not respect the alignment of bit-field types when laying out 4040 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4041 UseBitFieldTypeAlignment = false; 4042 4043 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4044 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4045 /// gcc. 4046 ZeroLengthBitfieldBoundary = 32; 4047 4048 if (T.isOSBinFormatMachO()) 4049 DescriptionString = 4050 BigEndian 4051 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4052 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4053 else 4054 DescriptionString = 4055 BigEndian 4056 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4057 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4058 4059 // FIXME: Override "preferred align" for double and long long. 4060 } 4061 4062 public: 4063 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4064 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 4065 IsAAPCS(true), HW_FP(0) { 4066 BigEndian = IsBigEndian; 4067 4068 switch (getTriple().getOS()) { 4069 case llvm::Triple::NetBSD: 4070 PtrDiffType = SignedLong; 4071 break; 4072 default: 4073 PtrDiffType = SignedInt; 4074 break; 4075 } 4076 4077 // {} in inline assembly are neon specifiers, not assembly variant 4078 // specifiers. 4079 NoAsmVariants = true; 4080 4081 // FIXME: Should we just treat this as a feature? 4082 IsThumb = getTriple().getArchName().startswith("thumb"); 4083 4084 // FIXME: This duplicates code from the driver that sets the -target-abi 4085 // option - this code is used if -target-abi isn't passed and should 4086 // be unified in some way. 4087 if (Triple.isOSBinFormatMachO()) { 4088 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4089 // the frontend matches that. 4090 if (Triple.getEnvironment() == llvm::Triple::EABI || 4091 Triple.getOS() == llvm::Triple::UnknownOS || 4092 StringRef(CPU).startswith("cortex-m")) { 4093 setABI("aapcs"); 4094 } else { 4095 setABI("apcs-gnu"); 4096 } 4097 } else if (Triple.isOSWindows()) { 4098 // FIXME: this is invalid for WindowsCE 4099 setABI("aapcs"); 4100 } else { 4101 // Select the default based on the platform. 4102 switch (Triple.getEnvironment()) { 4103 case llvm::Triple::Android: 4104 case llvm::Triple::GNUEABI: 4105 case llvm::Triple::GNUEABIHF: 4106 setABI("aapcs-linux"); 4107 break; 4108 case llvm::Triple::EABIHF: 4109 case llvm::Triple::EABI: 4110 setABI("aapcs"); 4111 break; 4112 case llvm::Triple::GNU: 4113 setABI("apcs-gnu"); 4114 break; 4115 default: 4116 if (Triple.getOS() == llvm::Triple::NetBSD) 4117 setABI("apcs-gnu"); 4118 else 4119 setABI("aapcs"); 4120 break; 4121 } 4122 } 4123 4124 // ARM targets default to using the ARM C++ ABI. 4125 TheCXXABI.set(TargetCXXABI::GenericARM); 4126 4127 // ARM has atomics up to 8 bytes 4128 MaxAtomicPromoteWidth = 64; 4129 if (shouldUseInlineAtomic(getTriple())) 4130 MaxAtomicInlineWidth = 64; 4131 4132 // Do force alignment of members that follow zero length bitfields. If 4133 // the alignment of the zero-length bitfield is greater than the member 4134 // that follows it, `bar', `bar' will be aligned as the type of the 4135 // zero length bitfield. 4136 UseZeroLengthBitfieldAlignment = true; 4137 } 4138 StringRef getABI() const override { return ABI; } 4139 bool setABI(const std::string &Name) override { 4140 ABI = Name; 4141 4142 // The defaults (above) are for AAPCS, check if we need to change them. 4143 // 4144 // FIXME: We need support for -meabi... we could just mangle it into the 4145 // name. 4146 if (Name == "apcs-gnu") { 4147 setABIAPCS(); 4148 return true; 4149 } 4150 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4151 setABIAAPCS(); 4152 return true; 4153 } 4154 return false; 4155 } 4156 4157 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4158 StringRef ArchName = getTriple().getArchName(); 4159 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 4160 Features["vfp2"] = true; 4161 else if (CPU == "cortex-a8" || CPU == "cortex-a9") { 4162 Features["vfp3"] = true; 4163 Features["neon"] = true; 4164 } 4165 else if (CPU == "cortex-a5") { 4166 Features["vfp4"] = true; 4167 Features["neon"] = true; 4168 } else if (CPU == "swift" || CPU == "cortex-a7" || 4169 CPU == "cortex-a12" || CPU == "cortex-a15" || 4170 CPU == "cortex-a17" || CPU == "krait") { 4171 Features["vfp4"] = true; 4172 Features["neon"] = true; 4173 Features["hwdiv"] = true; 4174 Features["hwdiv-arm"] = true; 4175 } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" || 4176 CPU == "cortex-a72") { 4177 Features["fp-armv8"] = true; 4178 Features["neon"] = true; 4179 Features["hwdiv"] = true; 4180 Features["hwdiv-arm"] = true; 4181 Features["crc"] = true; 4182 Features["crypto"] = true; 4183 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || 4184 // Enable the hwdiv extension for all v8a AArch32 cores by 4185 // default. 4186 ArchName == "armv8a" || ArchName == "armv8" || 4187 ArchName == "armebv8a" || ArchName == "armebv8" || 4188 ArchName == "thumbv8a" || ArchName == "thumbv8" || 4189 ArchName == "thumbebv8a" || ArchName == "thumbebv8") { 4190 Features["hwdiv"] = true; 4191 Features["hwdiv-arm"] = true; 4192 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" || 4193 CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") { 4194 Features["hwdiv"] = true; 4195 } 4196 } 4197 4198 bool handleTargetFeatures(std::vector<std::string> &Features, 4199 DiagnosticsEngine &Diags) override { 4200 FPU = 0; 4201 CRC = 0; 4202 Crypto = 0; 4203 SoftFloat = SoftFloatABI = false; 4204 HWDiv = 0; 4205 4206 for (const auto &Feature : Features) { 4207 if (Feature == "+soft-float") { 4208 SoftFloat = true; 4209 } else if (Feature == "+soft-float-abi") { 4210 SoftFloatABI = true; 4211 } else if (Feature == "+vfp2") { 4212 FPU |= VFP2FPU; 4213 HW_FP = HW_FP_SP | HW_FP_DP; 4214 } else if (Feature == "+vfp3") { 4215 FPU |= VFP3FPU; 4216 HW_FP = HW_FP_SP | HW_FP_DP; 4217 } else if (Feature == "+vfp4") { 4218 FPU |= VFP4FPU; 4219 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 4220 } else if (Feature == "+fp-armv8") { 4221 FPU |= FPARMV8; 4222 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 4223 } else if (Feature == "+neon") { 4224 FPU |= NeonFPU; 4225 HW_FP = HW_FP_SP | HW_FP_DP; 4226 } else if (Feature == "+hwdiv") { 4227 HWDiv |= HWDivThumb; 4228 } else if (Feature == "+hwdiv-arm") { 4229 HWDiv |= HWDivARM; 4230 } else if (Feature == "+crc") { 4231 CRC = 1; 4232 } else if (Feature == "+crypto") { 4233 Crypto = 1; 4234 } else if (Feature == "+fp-only-sp") { 4235 HW_FP &= ~HW_FP_DP; 4236 } 4237 } 4238 4239 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4240 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4241 return false; 4242 } 4243 4244 if (FPMath == FP_Neon) 4245 Features.push_back("+neonfp"); 4246 else if (FPMath == FP_VFP) 4247 Features.push_back("-neonfp"); 4248 4249 // Remove front-end specific options which the backend handles differently. 4250 const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" }; 4251 for (const auto &FEFeature : FrontEndFeatures) { 4252 auto Feature = std::find(Features.begin(), Features.end(), FEFeature); 4253 if (Feature != Features.end()) 4254 Features.erase(Feature); 4255 } 4256 4257 return true; 4258 } 4259 4260 bool hasFeature(StringRef Feature) const override { 4261 return llvm::StringSwitch<bool>(Feature) 4262 .Case("arm", true) 4263 .Case("softfloat", SoftFloat) 4264 .Case("thumb", IsThumb) 4265 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4266 .Case("hwdiv", HWDiv & HWDivThumb) 4267 .Case("hwdiv-arm", HWDiv & HWDivARM) 4268 .Default(false); 4269 } 4270 // FIXME: Should we actually have some table instead of these switches? 4271 static const char *getCPUDefineSuffix(StringRef Name) { 4272 return llvm::StringSwitch<const char *>(Name) 4273 .Cases("arm8", "arm810", "4") 4274 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", 4275 "4") 4276 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 4277 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 4278 .Case("ep9312", "4T") 4279 .Cases("arm10tdmi", "arm1020t", "5T") 4280 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 4281 .Case("arm926ej-s", "5TEJ") 4282 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 4283 .Cases("xscale", "iwmmxt", "5TE") 4284 .Case("arm1136j-s", "6J") 4285 .Case("arm1136jf-s", "6") 4286 .Cases("mpcorenovfp", "mpcore", "6K") 4287 .Cases("arm1176jz-s", "arm1176jzf-s", "6K") 4288 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 4289 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A") 4290 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", 4291 "7A") 4292 .Cases("cortex-r4", "cortex-r4f", "cortex-r5", "cortex-r7", "7R") 4293 .Case("swift", "7S") 4294 .Case("cyclone", "8A") 4295 .Cases("sc300", "cortex-m3", "7M") 4296 .Cases("cortex-m4", "cortex-m7", "7EM") 4297 .Cases("sc000", "cortex-m0", "cortex-m0plus", "cortex-m1", "6M") 4298 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "8A") 4299 .Default(nullptr); 4300 } 4301 static const char *getCPUProfile(StringRef Name) { 4302 return llvm::StringSwitch<const char *>(Name) 4303 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 4304 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", 4305 "A") 4306 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "A") 4307 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m0plus", "M") 4308 .Cases("cortex-m1", "cortex-m7", "sc000", "sc300", "M") 4309 .Cases("cortex-r4", "cortex-r4f", "cortex-r5", "cortex-r7", "R") 4310 .Default(""); 4311 } 4312 bool setCPU(const std::string &Name) override { 4313 if (!getCPUDefineSuffix(Name)) 4314 return false; 4315 4316 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4317 StringRef Profile = getCPUProfile(Name); 4318 if (Profile == "M" && MaxAtomicInlineWidth) { 4319 MaxAtomicPromoteWidth = 32; 4320 MaxAtomicInlineWidth = 32; 4321 } 4322 4323 CPU = Name; 4324 return true; 4325 } 4326 bool setFPMath(StringRef Name) override; 4327 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 4328 unsigned CPUArchVer) const { 4329 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 4330 (CPUArch.find('M') != StringRef::npos); 4331 } 4332 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 4333 unsigned CPUArchVer) const { 4334 // We check both CPUArchVer and ArchName because when only triple is 4335 // specified, the default CPU is arm1136j-s. 4336 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 4337 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 4338 } 4339 void getTargetDefines(const LangOptions &Opts, 4340 MacroBuilder &Builder) const override { 4341 // Target identification. 4342 Builder.defineMacro("__arm"); 4343 Builder.defineMacro("__arm__"); 4344 4345 // Target properties. 4346 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4347 4348 StringRef CPUArch = getCPUDefineSuffix(CPU); 4349 unsigned int CPUArchVer; 4350 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) 4351 llvm_unreachable("Invalid char for architecture version number"); 4352 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4353 4354 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4355 StringRef CPUProfile = getCPUProfile(CPU); 4356 StringRef ArchName = getTriple().getArchName(); 4357 4358 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4359 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4360 if (CPUArch[0] >= '8') { 4361 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4362 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4363 } 4364 4365 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4366 // is not defined for the M-profile. 4367 // NOTE that the deffault profile is assumed to be 'A' 4368 if (CPUProfile.empty() || CPUProfile != "M") 4369 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4370 4371 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4372 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4373 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4374 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4375 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4376 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 4377 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4378 4379 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4380 // instruction set such as ARM or Thumb. 4381 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4382 4383 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4384 4385 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4386 if (!CPUProfile.empty()) 4387 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4388 4389 // ACLE 6.5.1 Hardware Floating Point 4390 if (HW_FP) 4391 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4392 4393 // ACLE predefines. 4394 Builder.defineMacro("__ARM_ACLE", "200"); 4395 4396 // Subtarget options. 4397 4398 // FIXME: It's more complicated than this and we don't really support 4399 // interworking. 4400 // Windows on ARM does not "support" interworking 4401 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 4402 Builder.defineMacro("__THUMB_INTERWORK__"); 4403 4404 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4405 // Embedded targets on Darwin follow AAPCS, but not EABI. 4406 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4407 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4408 Builder.defineMacro("__ARM_EABI__"); 4409 Builder.defineMacro("__ARM_PCS", "1"); 4410 4411 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4412 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4413 } 4414 4415 if (SoftFloat) 4416 Builder.defineMacro("__SOFTFP__"); 4417 4418 if (CPU == "xscale") 4419 Builder.defineMacro("__XSCALE__"); 4420 4421 if (IsThumb) { 4422 Builder.defineMacro("__THUMBEL__"); 4423 Builder.defineMacro("__thumb__"); 4424 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4425 Builder.defineMacro("__thumb2__"); 4426 } 4427 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4428 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4429 4430 // Note, this is always on in gcc, even though it doesn't make sense. 4431 Builder.defineMacro("__APCS_32__"); 4432 4433 if (FPUModeIsVFP((FPUMode) FPU)) { 4434 Builder.defineMacro("__VFP_FP__"); 4435 if (FPU & VFP2FPU) 4436 Builder.defineMacro("__ARM_VFPV2__"); 4437 if (FPU & VFP3FPU) 4438 Builder.defineMacro("__ARM_VFPV3__"); 4439 if (FPU & VFP4FPU) 4440 Builder.defineMacro("__ARM_VFPV4__"); 4441 } 4442 4443 // This only gets set when Neon instructions are actually available, unlike 4444 // the VFP define, hence the soft float and arch check. This is subtly 4445 // different from gcc, we follow the intent which was that it should be set 4446 // when Neon instructions are actually available. 4447 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4448 Builder.defineMacro("__ARM_NEON"); 4449 Builder.defineMacro("__ARM_NEON__"); 4450 } 4451 4452 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4453 Opts.ShortWChar ? "2" : "4"); 4454 4455 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4456 Opts.ShortEnums ? "1" : "4"); 4457 4458 if (CRC) 4459 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4460 4461 if (Crypto) 4462 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4463 4464 if (CPUArchVer >= 6 && CPUArch != "6M") { 4465 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4466 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4467 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4468 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4469 } 4470 4471 bool is5EOrAbove = (CPUArchVer >= 6 || 4472 (CPUArchVer == 5 && 4473 CPUArch.find('E') != StringRef::npos)); 4474 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer)); 4475 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM")) 4476 Builder.defineMacro("__ARM_FEATURE_DSP"); 4477 } 4478 void getTargetBuiltins(const Builtin::Info *&Records, 4479 unsigned &NumRecords) const override { 4480 Records = BuiltinInfo; 4481 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4482 } 4483 bool isCLZForZeroUndef() const override { return false; } 4484 BuiltinVaListKind getBuiltinVaListKind() const override { 4485 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4486 } 4487 void getGCCRegNames(const char * const *&Names, 4488 unsigned &NumNames) const override; 4489 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4490 unsigned &NumAliases) const override; 4491 bool validateAsmConstraint(const char *&Name, 4492 TargetInfo::ConstraintInfo &Info) const override { 4493 switch (*Name) { 4494 default: break; 4495 case 'l': // r0-r7 4496 case 'h': // r8-r15 4497 case 'w': // VFP Floating point register single precision 4498 case 'P': // VFP Floating point register double precision 4499 Info.setAllowsRegister(); 4500 return true; 4501 case 'I': 4502 case 'J': 4503 case 'K': 4504 case 'L': 4505 case 'M': 4506 // FIXME 4507 return true; 4508 case 'Q': // A memory address that is a single base register. 4509 Info.setAllowsMemory(); 4510 return true; 4511 case 'U': // a memory reference... 4512 switch (Name[1]) { 4513 case 'q': // ...ARMV4 ldrsb 4514 case 'v': // ...VFP load/store (reg+constant offset) 4515 case 'y': // ...iWMMXt load/store 4516 case 't': // address valid for load/store opaque types wider 4517 // than 128-bits 4518 case 'n': // valid address for Neon doubleword vector load/store 4519 case 'm': // valid address for Neon element and structure load/store 4520 case 's': // valid address for non-offset loads/stores of quad-word 4521 // values in four ARM registers 4522 Info.setAllowsMemory(); 4523 Name++; 4524 return true; 4525 } 4526 } 4527 return false; 4528 } 4529 std::string convertConstraint(const char *&Constraint) const override { 4530 std::string R; 4531 switch (*Constraint) { 4532 case 'U': // Two-character constraint; add "^" hint for later parsing. 4533 R = std::string("^") + std::string(Constraint, 2); 4534 Constraint++; 4535 break; 4536 case 'p': // 'p' should be translated to 'r' by default. 4537 R = std::string("r"); 4538 break; 4539 default: 4540 return std::string(1, *Constraint); 4541 } 4542 return R; 4543 } 4544 bool 4545 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4546 std::string &SuggestedModifier) const override { 4547 bool isOutput = (Constraint[0] == '='); 4548 bool isInOut = (Constraint[0] == '+'); 4549 4550 // Strip off constraint modifiers. 4551 while (Constraint[0] == '=' || 4552 Constraint[0] == '+' || 4553 Constraint[0] == '&') 4554 Constraint = Constraint.substr(1); 4555 4556 switch (Constraint[0]) { 4557 default: break; 4558 case 'r': { 4559 switch (Modifier) { 4560 default: 4561 return (isInOut || isOutput || Size <= 64); 4562 case 'q': 4563 // A register of size 32 cannot fit a vector type. 4564 return false; 4565 } 4566 } 4567 } 4568 4569 return true; 4570 } 4571 const char *getClobbers() const override { 4572 // FIXME: Is this really right? 4573 return ""; 4574 } 4575 4576 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4577 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4578 } 4579 4580 int getEHDataRegisterNumber(unsigned RegNo) const override { 4581 if (RegNo == 0) return 0; 4582 if (RegNo == 1) return 1; 4583 return -1; 4584 } 4585 }; 4586 4587 bool ARMTargetInfo::setFPMath(StringRef Name) { 4588 if (Name == "neon") { 4589 FPMath = FP_Neon; 4590 return true; 4591 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4592 Name == "vfp4") { 4593 FPMath = FP_VFP; 4594 return true; 4595 } 4596 return false; 4597 } 4598 4599 const char * const ARMTargetInfo::GCCRegNames[] = { 4600 // Integer registers 4601 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4602 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4603 4604 // Float registers 4605 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4606 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4607 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4608 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4609 4610 // Double registers 4611 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4612 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4613 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4614 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4615 4616 // Quad registers 4617 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4618 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4619 }; 4620 4621 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4622 unsigned &NumNames) const { 4623 Names = GCCRegNames; 4624 NumNames = llvm::array_lengthof(GCCRegNames); 4625 } 4626 4627 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4628 { { "a1" }, "r0" }, 4629 { { "a2" }, "r1" }, 4630 { { "a3" }, "r2" }, 4631 { { "a4" }, "r3" }, 4632 { { "v1" }, "r4" }, 4633 { { "v2" }, "r5" }, 4634 { { "v3" }, "r6" }, 4635 { { "v4" }, "r7" }, 4636 { { "v5" }, "r8" }, 4637 { { "v6", "rfp" }, "r9" }, 4638 { { "sl" }, "r10" }, 4639 { { "fp" }, "r11" }, 4640 { { "ip" }, "r12" }, 4641 { { "r13" }, "sp" }, 4642 { { "r14" }, "lr" }, 4643 { { "r15" }, "pc" }, 4644 // The S, D and Q registers overlap, but aren't really aliases; we 4645 // don't want to substitute one of these for a different-sized one. 4646 }; 4647 4648 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4649 unsigned &NumAliases) const { 4650 Aliases = GCCRegAliases; 4651 NumAliases = llvm::array_lengthof(GCCRegAliases); 4652 } 4653 4654 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4655 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4656 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4657 ALL_LANGUAGES }, 4658 #include "clang/Basic/BuiltinsNEON.def" 4659 4660 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4661 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG }, 4662 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4663 ALL_LANGUAGES }, 4664 #include "clang/Basic/BuiltinsARM.def" 4665 }; 4666 4667 class ARMleTargetInfo : public ARMTargetInfo { 4668 public: 4669 ARMleTargetInfo(const llvm::Triple &Triple) 4670 : ARMTargetInfo(Triple, false) { } 4671 void getTargetDefines(const LangOptions &Opts, 4672 MacroBuilder &Builder) const override { 4673 Builder.defineMacro("__ARMEL__"); 4674 ARMTargetInfo::getTargetDefines(Opts, Builder); 4675 } 4676 }; 4677 4678 class ARMbeTargetInfo : public ARMTargetInfo { 4679 public: 4680 ARMbeTargetInfo(const llvm::Triple &Triple) 4681 : ARMTargetInfo(Triple, true) { } 4682 void getTargetDefines(const LangOptions &Opts, 4683 MacroBuilder &Builder) const override { 4684 Builder.defineMacro("__ARMEB__"); 4685 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4686 ARMTargetInfo::getTargetDefines(Opts, Builder); 4687 } 4688 }; 4689 4690 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4691 const llvm::Triple Triple; 4692 public: 4693 WindowsARMTargetInfo(const llvm::Triple &Triple) 4694 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4695 TLSSupported = false; 4696 WCharType = UnsignedShort; 4697 SizeType = UnsignedInt; 4698 UserLabelPrefix = ""; 4699 } 4700 void getVisualStudioDefines(const LangOptions &Opts, 4701 MacroBuilder &Builder) const { 4702 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4703 4704 // FIXME: this is invalid for WindowsCE 4705 Builder.defineMacro("_M_ARM_NT", "1"); 4706 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4707 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4708 4709 assert((Triple.getArch() == llvm::Triple::arm || 4710 Triple.getArch() == llvm::Triple::thumb) && 4711 "invalid architecture for Windows ARM target info"); 4712 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4713 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4714 4715 // TODO map the complete set of values 4716 // 31: VFPv3 40: VFPv4 4717 Builder.defineMacro("_M_ARM_FP", "31"); 4718 } 4719 BuiltinVaListKind getBuiltinVaListKind() const override { 4720 return TargetInfo::CharPtrBuiltinVaList; 4721 } 4722 }; 4723 4724 // Windows ARM + Itanium C++ ABI Target 4725 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4726 public: 4727 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4728 : WindowsARMTargetInfo(Triple) { 4729 TheCXXABI.set(TargetCXXABI::GenericARM); 4730 } 4731 4732 void getTargetDefines(const LangOptions &Opts, 4733 MacroBuilder &Builder) const override { 4734 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4735 4736 if (Opts.MSVCCompat) 4737 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4738 } 4739 }; 4740 4741 // Windows ARM, MS (C++) ABI 4742 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4743 public: 4744 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4745 : WindowsARMTargetInfo(Triple) { 4746 TheCXXABI.set(TargetCXXABI::Microsoft); 4747 } 4748 4749 void getTargetDefines(const LangOptions &Opts, 4750 MacroBuilder &Builder) const override { 4751 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4752 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4753 } 4754 }; 4755 4756 class DarwinARMTargetInfo : 4757 public DarwinTargetInfo<ARMleTargetInfo> { 4758 protected: 4759 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4760 MacroBuilder &Builder) const override { 4761 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4762 } 4763 4764 public: 4765 DarwinARMTargetInfo(const llvm::Triple &Triple) 4766 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4767 HasAlignMac68kSupport = true; 4768 // iOS always has 64-bit atomic instructions. 4769 // FIXME: This should be based off of the target features in 4770 // ARMleTargetInfo. 4771 MaxAtomicInlineWidth = 64; 4772 4773 // Darwin on iOS uses a variant of the ARM C++ ABI. 4774 TheCXXABI.set(TargetCXXABI::iOS); 4775 } 4776 }; 4777 4778 class AArch64TargetInfo : public TargetInfo { 4779 virtual void setDescriptionString() = 0; 4780 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4781 static const char *const GCCRegNames[]; 4782 4783 enum FPUModeEnum { 4784 FPUMode, 4785 NeonMode 4786 }; 4787 4788 unsigned FPU; 4789 unsigned CRC; 4790 unsigned Crypto; 4791 4792 static const Builtin::Info BuiltinInfo[]; 4793 4794 std::string ABI; 4795 4796 public: 4797 AArch64TargetInfo(const llvm::Triple &Triple) 4798 : TargetInfo(Triple), ABI("aapcs") { 4799 4800 if (getTriple().getOS() == llvm::Triple::NetBSD) { 4801 WCharType = SignedInt; 4802 4803 // NetBSD apparently prefers consistency across ARM targets to consistency 4804 // across 64-bit targets. 4805 Int64Type = SignedLongLong; 4806 IntMaxType = SignedLongLong; 4807 } else { 4808 WCharType = UnsignedInt; 4809 Int64Type = SignedLong; 4810 IntMaxType = SignedLong; 4811 } 4812 4813 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4814 MaxVectorAlign = 128; 4815 RegParmMax = 8; 4816 MaxAtomicInlineWidth = 128; 4817 MaxAtomicPromoteWidth = 128; 4818 4819 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 4820 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4821 4822 // {} in inline assembly are neon specifiers, not assembly variant 4823 // specifiers. 4824 NoAsmVariants = true; 4825 4826 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 4827 // contributes to the alignment of the containing aggregate in the same way 4828 // a plain (non bit-field) member of that type would, without exception for 4829 // zero-sized or anonymous bit-fields." 4830 UseBitFieldTypeAlignment = true; 4831 UseZeroLengthBitfieldAlignment = true; 4832 4833 // AArch64 targets default to using the ARM C++ ABI. 4834 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4835 } 4836 4837 StringRef getABI() const override { return ABI; } 4838 bool setABI(const std::string &Name) override { 4839 if (Name != "aapcs" && Name != "darwinpcs") 4840 return false; 4841 4842 ABI = Name; 4843 return true; 4844 } 4845 4846 bool setCPU(const std::string &Name) override { 4847 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4848 .Case("generic", true) 4849 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 4850 .Case("cyclone", true) 4851 .Default(false); 4852 return CPUKnown; 4853 } 4854 4855 void getTargetDefines(const LangOptions &Opts, 4856 MacroBuilder &Builder) const override { 4857 // Target identification. 4858 Builder.defineMacro("__aarch64__"); 4859 4860 // Target properties. 4861 Builder.defineMacro("_LP64"); 4862 Builder.defineMacro("__LP64__"); 4863 4864 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4865 Builder.defineMacro("__ARM_ACLE", "200"); 4866 Builder.defineMacro("__ARM_ARCH", "8"); 4867 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4868 4869 Builder.defineMacro("__ARM_64BIT_STATE"); 4870 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4871 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4872 4873 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4874 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4875 Builder.defineMacro("__ARM_FEATURE_FMA"); 4876 Builder.defineMacro("__ARM_FEATURE_DIV"); 4877 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE 4878 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 4879 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4880 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4881 4882 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 4883 4884 // 0xe implies support for half, single and double precision operations. 4885 Builder.defineMacro("__ARM_FP", "0xe"); 4886 4887 // PCS specifies this for SysV variants, which is all we support. Other ABIs 4888 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 4889 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 4890 4891 if (Opts.FastMath || Opts.FiniteMathOnly) 4892 Builder.defineMacro("__ARM_FP_FAST"); 4893 4894 if (Opts.C99 && !Opts.Freestanding) 4895 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 4896 4897 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 4898 4899 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4900 Opts.ShortEnums ? "1" : "4"); 4901 4902 if (FPU == NeonMode) { 4903 Builder.defineMacro("__ARM_NEON"); 4904 // 64-bit NEON supports half, single and double precision operations. 4905 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 4906 } 4907 4908 if (CRC) 4909 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4910 4911 if (Crypto) 4912 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4913 } 4914 4915 void getTargetBuiltins(const Builtin::Info *&Records, 4916 unsigned &NumRecords) const override { 4917 Records = BuiltinInfo; 4918 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 4919 } 4920 4921 bool hasFeature(StringRef Feature) const override { 4922 return Feature == "aarch64" || 4923 Feature == "arm64" || 4924 (Feature == "neon" && FPU == NeonMode); 4925 } 4926 4927 bool handleTargetFeatures(std::vector<std::string> &Features, 4928 DiagnosticsEngine &Diags) override { 4929 FPU = FPUMode; 4930 CRC = 0; 4931 Crypto = 0; 4932 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 4933 if (Features[i] == "+neon") 4934 FPU = NeonMode; 4935 if (Features[i] == "+crc") 4936 CRC = 1; 4937 if (Features[i] == "+crypto") 4938 Crypto = 1; 4939 } 4940 4941 setDescriptionString(); 4942 4943 return true; 4944 } 4945 4946 bool isCLZForZeroUndef() const override { return false; } 4947 4948 BuiltinVaListKind getBuiltinVaListKind() const override { 4949 return TargetInfo::AArch64ABIBuiltinVaList; 4950 } 4951 4952 void getGCCRegNames(const char *const *&Names, 4953 unsigned &NumNames) const override; 4954 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4955 unsigned &NumAliases) const override; 4956 4957 bool validateAsmConstraint(const char *&Name, 4958 TargetInfo::ConstraintInfo &Info) const override { 4959 switch (*Name) { 4960 default: 4961 return false; 4962 case 'w': // Floating point and SIMD registers (V0-V31) 4963 Info.setAllowsRegister(); 4964 return true; 4965 case 'I': // Constant that can be used with an ADD instruction 4966 case 'J': // Constant that can be used with a SUB instruction 4967 case 'K': // Constant that can be used with a 32-bit logical instruction 4968 case 'L': // Constant that can be used with a 64-bit logical instruction 4969 case 'M': // Constant that can be used as a 32-bit MOV immediate 4970 case 'N': // Constant that can be used as a 64-bit MOV immediate 4971 case 'Y': // Floating point constant zero 4972 case 'Z': // Integer constant zero 4973 return true; 4974 case 'Q': // A memory reference with base register and no offset 4975 Info.setAllowsMemory(); 4976 return true; 4977 case 'S': // A symbolic address 4978 Info.setAllowsRegister(); 4979 return true; 4980 case 'U': 4981 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 4982 // Utf: A memory address suitable for ldp/stp in TF mode. 4983 // Usa: An absolute symbolic address. 4984 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 4985 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 4986 case 'z': // Zero register, wzr or xzr 4987 Info.setAllowsRegister(); 4988 return true; 4989 case 'x': // Floating point and SIMD registers (V0-V15) 4990 Info.setAllowsRegister(); 4991 return true; 4992 } 4993 return false; 4994 } 4995 4996 bool 4997 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4998 std::string &SuggestedModifier) const override { 4999 // Strip off constraint modifiers. 5000 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5001 Constraint = Constraint.substr(1); 5002 5003 switch (Constraint[0]) { 5004 default: 5005 return true; 5006 case 'z': 5007 case 'r': { 5008 switch (Modifier) { 5009 case 'x': 5010 case 'w': 5011 // For now assume that the person knows what they're 5012 // doing with the modifier. 5013 return true; 5014 default: 5015 // By default an 'r' constraint will be in the 'x' 5016 // registers. 5017 if (Size == 64) 5018 return true; 5019 5020 SuggestedModifier = "w"; 5021 return false; 5022 } 5023 } 5024 } 5025 } 5026 5027 const char *getClobbers() const override { return ""; } 5028 5029 int getEHDataRegisterNumber(unsigned RegNo) const override { 5030 if (RegNo == 0) 5031 return 0; 5032 if (RegNo == 1) 5033 return 1; 5034 return -1; 5035 } 5036 }; 5037 5038 const char *const AArch64TargetInfo::GCCRegNames[] = { 5039 // 32-bit Integer registers 5040 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5041 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5042 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5043 5044 // 64-bit Integer registers 5045 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5046 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5047 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5048 5049 // 32-bit floating point regsisters 5050 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5051 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5052 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5053 5054 // 64-bit floating point regsisters 5055 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5056 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5057 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5058 5059 // Vector registers 5060 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5061 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5062 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5063 }; 5064 5065 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 5066 unsigned &NumNames) const { 5067 Names = GCCRegNames; 5068 NumNames = llvm::array_lengthof(GCCRegNames); 5069 } 5070 5071 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5072 { { "w31" }, "wsp" }, 5073 { { "x29" }, "fp" }, 5074 { { "x30" }, "lr" }, 5075 { { "x31" }, "sp" }, 5076 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5077 // don't want to substitute one of these for a different-sized one. 5078 }; 5079 5080 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5081 unsigned &NumAliases) const { 5082 Aliases = GCCRegAliases; 5083 NumAliases = llvm::array_lengthof(GCCRegAliases); 5084 } 5085 5086 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5087 #define BUILTIN(ID, TYPE, ATTRS) \ 5088 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5089 #include "clang/Basic/BuiltinsNEON.def" 5090 5091 #define BUILTIN(ID, TYPE, ATTRS) \ 5092 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5093 #include "clang/Basic/BuiltinsAArch64.def" 5094 }; 5095 5096 class AArch64leTargetInfo : public AArch64TargetInfo { 5097 void setDescriptionString() override { 5098 if (getTriple().isOSBinFormatMachO()) 5099 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5100 else 5101 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5102 } 5103 5104 public: 5105 AArch64leTargetInfo(const llvm::Triple &Triple) 5106 : AArch64TargetInfo(Triple) { 5107 BigEndian = false; 5108 } 5109 void getTargetDefines(const LangOptions &Opts, 5110 MacroBuilder &Builder) const override { 5111 Builder.defineMacro("__AARCH64EL__"); 5112 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5113 } 5114 }; 5115 5116 class AArch64beTargetInfo : public AArch64TargetInfo { 5117 void setDescriptionString() override { 5118 assert(!getTriple().isOSBinFormatMachO()); 5119 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5120 } 5121 5122 public: 5123 AArch64beTargetInfo(const llvm::Triple &Triple) 5124 : AArch64TargetInfo(Triple) { } 5125 void getTargetDefines(const LangOptions &Opts, 5126 MacroBuilder &Builder) const override { 5127 Builder.defineMacro("__AARCH64EB__"); 5128 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5129 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5130 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5131 } 5132 }; 5133 5134 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5135 protected: 5136 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5137 MacroBuilder &Builder) const override { 5138 Builder.defineMacro("__AARCH64_SIMD__"); 5139 Builder.defineMacro("__ARM64_ARCH_8__"); 5140 Builder.defineMacro("__ARM_NEON__"); 5141 Builder.defineMacro("__LITTLE_ENDIAN__"); 5142 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5143 Builder.defineMacro("__arm64", "1"); 5144 Builder.defineMacro("__arm64__", "1"); 5145 5146 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5147 } 5148 5149 public: 5150 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5151 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5152 Int64Type = SignedLongLong; 5153 WCharType = SignedInt; 5154 UseSignedCharForObjCBool = false; 5155 5156 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5157 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5158 5159 TheCXXABI.set(TargetCXXABI::iOS64); 5160 } 5161 5162 BuiltinVaListKind getBuiltinVaListKind() const override { 5163 return TargetInfo::CharPtrBuiltinVaList; 5164 } 5165 }; 5166 5167 // Hexagon abstract base class 5168 class HexagonTargetInfo : public TargetInfo { 5169 static const Builtin::Info BuiltinInfo[]; 5170 static const char * const GCCRegNames[]; 5171 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5172 std::string CPU; 5173 public: 5174 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5175 BigEndian = false; 5176 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5177 5178 // {} in inline assembly are packet specifiers, not assembly variant 5179 // specifiers. 5180 NoAsmVariants = true; 5181 } 5182 5183 void getTargetBuiltins(const Builtin::Info *&Records, 5184 unsigned &NumRecords) const override { 5185 Records = BuiltinInfo; 5186 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5187 } 5188 5189 bool validateAsmConstraint(const char *&Name, 5190 TargetInfo::ConstraintInfo &Info) const override { 5191 return true; 5192 } 5193 5194 void getTargetDefines(const LangOptions &Opts, 5195 MacroBuilder &Builder) const override; 5196 5197 bool hasFeature(StringRef Feature) const override { 5198 return Feature == "hexagon"; 5199 } 5200 5201 BuiltinVaListKind getBuiltinVaListKind() const override { 5202 return TargetInfo::CharPtrBuiltinVaList; 5203 } 5204 void getGCCRegNames(const char * const *&Names, 5205 unsigned &NumNames) const override; 5206 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5207 unsigned &NumAliases) const override; 5208 const char *getClobbers() const override { 5209 return ""; 5210 } 5211 5212 static const char *getHexagonCPUSuffix(StringRef Name) { 5213 return llvm::StringSwitch<const char*>(Name) 5214 .Case("hexagonv4", "4") 5215 .Case("hexagonv5", "5") 5216 .Default(nullptr); 5217 } 5218 5219 bool setCPU(const std::string &Name) override { 5220 if (!getHexagonCPUSuffix(Name)) 5221 return false; 5222 5223 CPU = Name; 5224 return true; 5225 } 5226 }; 5227 5228 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5229 MacroBuilder &Builder) const { 5230 Builder.defineMacro("qdsp6"); 5231 Builder.defineMacro("__qdsp6", "1"); 5232 Builder.defineMacro("__qdsp6__", "1"); 5233 5234 Builder.defineMacro("hexagon"); 5235 Builder.defineMacro("__hexagon", "1"); 5236 Builder.defineMacro("__hexagon__", "1"); 5237 5238 if(CPU == "hexagonv1") { 5239 Builder.defineMacro("__HEXAGON_V1__"); 5240 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5241 if(Opts.HexagonQdsp6Compat) { 5242 Builder.defineMacro("__QDSP6_V1__"); 5243 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5244 } 5245 } 5246 else if(CPU == "hexagonv2") { 5247 Builder.defineMacro("__HEXAGON_V2__"); 5248 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5249 if(Opts.HexagonQdsp6Compat) { 5250 Builder.defineMacro("__QDSP6_V2__"); 5251 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5252 } 5253 } 5254 else if(CPU == "hexagonv3") { 5255 Builder.defineMacro("__HEXAGON_V3__"); 5256 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5257 if(Opts.HexagonQdsp6Compat) { 5258 Builder.defineMacro("__QDSP6_V3__"); 5259 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5260 } 5261 } 5262 else if(CPU == "hexagonv4") { 5263 Builder.defineMacro("__HEXAGON_V4__"); 5264 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5265 if(Opts.HexagonQdsp6Compat) { 5266 Builder.defineMacro("__QDSP6_V4__"); 5267 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5268 } 5269 } 5270 else if(CPU == "hexagonv5") { 5271 Builder.defineMacro("__HEXAGON_V5__"); 5272 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5273 if(Opts.HexagonQdsp6Compat) { 5274 Builder.defineMacro("__QDSP6_V5__"); 5275 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5276 } 5277 } 5278 } 5279 5280 const char * const HexagonTargetInfo::GCCRegNames[] = { 5281 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5282 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5283 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5284 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5285 "p0", "p1", "p2", "p3", 5286 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5287 }; 5288 5289 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5290 unsigned &NumNames) const { 5291 Names = GCCRegNames; 5292 NumNames = llvm::array_lengthof(GCCRegNames); 5293 } 5294 5295 5296 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5297 { { "sp" }, "r29" }, 5298 { { "fp" }, "r30" }, 5299 { { "lr" }, "r31" }, 5300 }; 5301 5302 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5303 unsigned &NumAliases) const { 5304 Aliases = GCCRegAliases; 5305 NumAliases = llvm::array_lengthof(GCCRegAliases); 5306 } 5307 5308 5309 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5310 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5311 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5312 ALL_LANGUAGES }, 5313 #include "clang/Basic/BuiltinsHexagon.def" 5314 }; 5315 5316 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5317 class SparcTargetInfo : public TargetInfo { 5318 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5319 static const char * const GCCRegNames[]; 5320 bool SoftFloat; 5321 public: 5322 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 5323 5324 bool handleTargetFeatures(std::vector<std::string> &Features, 5325 DiagnosticsEngine &Diags) override { 5326 SoftFloat = false; 5327 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5328 if (Feature != Features.end()) { 5329 SoftFloat = true; 5330 Features.erase(Feature); 5331 } 5332 return true; 5333 } 5334 void getTargetDefines(const LangOptions &Opts, 5335 MacroBuilder &Builder) const override { 5336 DefineStd(Builder, "sparc", Opts); 5337 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5338 5339 if (SoftFloat) 5340 Builder.defineMacro("SOFT_FLOAT", "1"); 5341 } 5342 5343 bool hasFeature(StringRef Feature) const override { 5344 return llvm::StringSwitch<bool>(Feature) 5345 .Case("softfloat", SoftFloat) 5346 .Case("sparc", true) 5347 .Default(false); 5348 } 5349 5350 void getTargetBuiltins(const Builtin::Info *&Records, 5351 unsigned &NumRecords) const override { 5352 // FIXME: Implement! 5353 } 5354 BuiltinVaListKind getBuiltinVaListKind() const override { 5355 return TargetInfo::VoidPtrBuiltinVaList; 5356 } 5357 void getGCCRegNames(const char * const *&Names, 5358 unsigned &NumNames) const override; 5359 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5360 unsigned &NumAliases) const override; 5361 bool validateAsmConstraint(const char *&Name, 5362 TargetInfo::ConstraintInfo &info) const override { 5363 // FIXME: Implement! 5364 switch (*Name) { 5365 case 'I': // Signed 13-bit constant 5366 case 'J': // Zero 5367 case 'K': // 32-bit constant with the low 12 bits clear 5368 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5369 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5370 case 'N': // Same as 'K' but zext (required for SIMode) 5371 case 'O': // The constant 4096 5372 return true; 5373 } 5374 return false; 5375 } 5376 const char *getClobbers() const override { 5377 // FIXME: Implement! 5378 return ""; 5379 } 5380 }; 5381 5382 const char * const SparcTargetInfo::GCCRegNames[] = { 5383 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5384 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5385 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5386 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5387 }; 5388 5389 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5390 unsigned &NumNames) const { 5391 Names = GCCRegNames; 5392 NumNames = llvm::array_lengthof(GCCRegNames); 5393 } 5394 5395 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5396 { { "g0" }, "r0" }, 5397 { { "g1" }, "r1" }, 5398 { { "g2" }, "r2" }, 5399 { { "g3" }, "r3" }, 5400 { { "g4" }, "r4" }, 5401 { { "g5" }, "r5" }, 5402 { { "g6" }, "r6" }, 5403 { { "g7" }, "r7" }, 5404 { { "o0" }, "r8" }, 5405 { { "o1" }, "r9" }, 5406 { { "o2" }, "r10" }, 5407 { { "o3" }, "r11" }, 5408 { { "o4" }, "r12" }, 5409 { { "o5" }, "r13" }, 5410 { { "o6", "sp" }, "r14" }, 5411 { { "o7" }, "r15" }, 5412 { { "l0" }, "r16" }, 5413 { { "l1" }, "r17" }, 5414 { { "l2" }, "r18" }, 5415 { { "l3" }, "r19" }, 5416 { { "l4" }, "r20" }, 5417 { { "l5" }, "r21" }, 5418 { { "l6" }, "r22" }, 5419 { { "l7" }, "r23" }, 5420 { { "i0" }, "r24" }, 5421 { { "i1" }, "r25" }, 5422 { { "i2" }, "r26" }, 5423 { { "i3" }, "r27" }, 5424 { { "i4" }, "r28" }, 5425 { { "i5" }, "r29" }, 5426 { { "i6", "fp" }, "r30" }, 5427 { { "i7" }, "r31" }, 5428 }; 5429 5430 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5431 unsigned &NumAliases) const { 5432 Aliases = GCCRegAliases; 5433 NumAliases = llvm::array_lengthof(GCCRegAliases); 5434 } 5435 5436 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5437 class SparcV8TargetInfo : public SparcTargetInfo { 5438 public: 5439 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5440 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5441 } 5442 5443 void getTargetDefines(const LangOptions &Opts, 5444 MacroBuilder &Builder) const override { 5445 SparcTargetInfo::getTargetDefines(Opts, Builder); 5446 Builder.defineMacro("__sparcv8"); 5447 } 5448 }; 5449 5450 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5451 class SparcV9TargetInfo : public SparcTargetInfo { 5452 public: 5453 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5454 // FIXME: Support Sparc quad-precision long double? 5455 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5456 // This is an LP64 platform. 5457 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5458 5459 // OpenBSD uses long long for int64_t and intmax_t. 5460 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5461 IntMaxType = SignedLongLong; 5462 else 5463 IntMaxType = SignedLong; 5464 Int64Type = IntMaxType; 5465 5466 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5467 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5468 LongDoubleWidth = 128; 5469 LongDoubleAlign = 128; 5470 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5471 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5472 } 5473 5474 void getTargetDefines(const LangOptions &Opts, 5475 MacroBuilder &Builder) const override { 5476 SparcTargetInfo::getTargetDefines(Opts, Builder); 5477 Builder.defineMacro("__sparcv9"); 5478 Builder.defineMacro("__arch64__"); 5479 // Solaris doesn't need these variants, but the BSDs do. 5480 if (getTriple().getOS() != llvm::Triple::Solaris) { 5481 Builder.defineMacro("__sparc64__"); 5482 Builder.defineMacro("__sparc_v9__"); 5483 Builder.defineMacro("__sparcv9__"); 5484 } 5485 } 5486 5487 bool setCPU(const std::string &Name) override { 5488 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5489 .Case("v9", true) 5490 .Case("ultrasparc", true) 5491 .Case("ultrasparc3", true) 5492 .Case("niagara", true) 5493 .Case("niagara2", true) 5494 .Case("niagara3", true) 5495 .Case("niagara4", true) 5496 .Default(false); 5497 5498 // No need to store the CPU yet. There aren't any CPU-specific 5499 // macros to define. 5500 return CPUKnown; 5501 } 5502 }; 5503 5504 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 5505 public: 5506 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 5507 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 5508 SizeType = UnsignedInt; 5509 PtrDiffType = SignedInt; 5510 } 5511 }; 5512 5513 class SystemZTargetInfo : public TargetInfo { 5514 static const Builtin::Info BuiltinInfo[]; 5515 static const char *const GCCRegNames[]; 5516 std::string CPU; 5517 bool HasTransactionalExecution; 5518 5519 public: 5520 SystemZTargetInfo(const llvm::Triple &Triple) 5521 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false) { 5522 IntMaxType = SignedLong; 5523 Int64Type = SignedLong; 5524 TLSSupported = true; 5525 IntWidth = IntAlign = 32; 5526 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5527 PointerWidth = PointerAlign = 64; 5528 LongDoubleWidth = 128; 5529 LongDoubleAlign = 64; 5530 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5531 DefaultAlignForAttributeAligned = 64; 5532 MinGlobalAlign = 16; 5533 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5534 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5535 } 5536 void getTargetDefines(const LangOptions &Opts, 5537 MacroBuilder &Builder) const override { 5538 Builder.defineMacro("__s390__"); 5539 Builder.defineMacro("__s390x__"); 5540 Builder.defineMacro("__zarch__"); 5541 Builder.defineMacro("__LONG_DOUBLE_128__"); 5542 if (HasTransactionalExecution) 5543 Builder.defineMacro("__HTM__"); 5544 } 5545 void getTargetBuiltins(const Builtin::Info *&Records, 5546 unsigned &NumRecords) const override { 5547 Records = BuiltinInfo; 5548 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin; 5549 } 5550 5551 void getGCCRegNames(const char *const *&Names, 5552 unsigned &NumNames) const override; 5553 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5554 unsigned &NumAliases) const override { 5555 // No aliases. 5556 Aliases = nullptr; 5557 NumAliases = 0; 5558 } 5559 bool validateAsmConstraint(const char *&Name, 5560 TargetInfo::ConstraintInfo &info) const override; 5561 const char *getClobbers() const override { 5562 // FIXME: Is this really right? 5563 return ""; 5564 } 5565 BuiltinVaListKind getBuiltinVaListKind() const override { 5566 return TargetInfo::SystemZBuiltinVaList; 5567 } 5568 bool setCPU(const std::string &Name) override { 5569 CPU = Name; 5570 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5571 .Case("z10", true) 5572 .Case("z196", true) 5573 .Case("zEC12", true) 5574 .Default(false); 5575 5576 return CPUKnown; 5577 } 5578 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5579 if (CPU == "zEC12") 5580 Features["transactional-execution"] = true; 5581 } 5582 5583 bool handleTargetFeatures(std::vector<std::string> &Features, 5584 DiagnosticsEngine &Diags) override { 5585 HasTransactionalExecution = false; 5586 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 5587 if (Features[i] == "+transactional-execution") 5588 HasTransactionalExecution = true; 5589 } 5590 return true; 5591 } 5592 5593 bool hasFeature(StringRef Feature) const override { 5594 return llvm::StringSwitch<bool>(Feature) 5595 .Case("systemz", true) 5596 .Case("htm", HasTransactionalExecution) 5597 .Default(false); 5598 } 5599 }; 5600 5601 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 5602 #define BUILTIN(ID, TYPE, ATTRS) \ 5603 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5604 #include "clang/Basic/BuiltinsSystemZ.def" 5605 }; 5606 5607 const char *const SystemZTargetInfo::GCCRegNames[] = { 5608 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5609 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5610 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5611 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5612 }; 5613 5614 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5615 unsigned &NumNames) const { 5616 Names = GCCRegNames; 5617 NumNames = llvm::array_lengthof(GCCRegNames); 5618 } 5619 5620 bool SystemZTargetInfo:: 5621 validateAsmConstraint(const char *&Name, 5622 TargetInfo::ConstraintInfo &Info) const { 5623 switch (*Name) { 5624 default: 5625 return false; 5626 5627 case 'a': // Address register 5628 case 'd': // Data register (equivalent to 'r') 5629 case 'f': // Floating-point register 5630 Info.setAllowsRegister(); 5631 return true; 5632 5633 case 'I': // Unsigned 8-bit constant 5634 case 'J': // Unsigned 12-bit constant 5635 case 'K': // Signed 16-bit constant 5636 case 'L': // Signed 20-bit displacement (on all targets we support) 5637 case 'M': // 0x7fffffff 5638 return true; 5639 5640 case 'Q': // Memory with base and unsigned 12-bit displacement 5641 case 'R': // Likewise, plus an index 5642 case 'S': // Memory with base and signed 20-bit displacement 5643 case 'T': // Likewise, plus an index 5644 Info.setAllowsMemory(); 5645 return true; 5646 } 5647 } 5648 5649 class MSP430TargetInfo : public TargetInfo { 5650 static const char * const GCCRegNames[]; 5651 public: 5652 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5653 BigEndian = false; 5654 TLSSupported = false; 5655 IntWidth = 16; IntAlign = 16; 5656 LongWidth = 32; LongLongWidth = 64; 5657 LongAlign = LongLongAlign = 16; 5658 PointerWidth = 16; PointerAlign = 16; 5659 SuitableAlign = 16; 5660 SizeType = UnsignedInt; 5661 IntMaxType = SignedLongLong; 5662 IntPtrType = SignedInt; 5663 PtrDiffType = SignedInt; 5664 SigAtomicType = SignedLong; 5665 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 5666 } 5667 void getTargetDefines(const LangOptions &Opts, 5668 MacroBuilder &Builder) const override { 5669 Builder.defineMacro("MSP430"); 5670 Builder.defineMacro("__MSP430__"); 5671 // FIXME: defines for different 'flavours' of MCU 5672 } 5673 void getTargetBuiltins(const Builtin::Info *&Records, 5674 unsigned &NumRecords) const override { 5675 // FIXME: Implement. 5676 Records = nullptr; 5677 NumRecords = 0; 5678 } 5679 bool hasFeature(StringRef Feature) const override { 5680 return Feature == "msp430"; 5681 } 5682 void getGCCRegNames(const char * const *&Names, 5683 unsigned &NumNames) const override; 5684 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5685 unsigned &NumAliases) const override { 5686 // No aliases. 5687 Aliases = nullptr; 5688 NumAliases = 0; 5689 } 5690 bool 5691 validateAsmConstraint(const char *&Name, 5692 TargetInfo::ConstraintInfo &info) const override { 5693 // FIXME: implement 5694 switch (*Name) { 5695 case 'K': // the constant 1 5696 case 'L': // constant -1^20 .. 1^19 5697 case 'M': // constant 1-4: 5698 return true; 5699 } 5700 // No target constraints for now. 5701 return false; 5702 } 5703 const char *getClobbers() const override { 5704 // FIXME: Is this really right? 5705 return ""; 5706 } 5707 BuiltinVaListKind getBuiltinVaListKind() const override { 5708 // FIXME: implement 5709 return TargetInfo::CharPtrBuiltinVaList; 5710 } 5711 }; 5712 5713 const char * const MSP430TargetInfo::GCCRegNames[] = { 5714 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5715 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5716 }; 5717 5718 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5719 unsigned &NumNames) const { 5720 Names = GCCRegNames; 5721 NumNames = llvm::array_lengthof(GCCRegNames); 5722 } 5723 5724 // LLVM and Clang cannot be used directly to output native binaries for 5725 // target, but is used to compile C code to llvm bitcode with correct 5726 // type and alignment information. 5727 // 5728 // TCE uses the llvm bitcode as input and uses it for generating customized 5729 // target processor and program binary. TCE co-design environment is 5730 // publicly available in http://tce.cs.tut.fi 5731 5732 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5733 3, // opencl_global 5734 4, // opencl_local 5735 5, // opencl_constant 5736 // FIXME: generic has to be added to the target 5737 0, // opencl_generic 5738 0, // cuda_device 5739 0, // cuda_constant 5740 0 // cuda_shared 5741 }; 5742 5743 class TCETargetInfo : public TargetInfo{ 5744 public: 5745 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5746 TLSSupported = false; 5747 IntWidth = 32; 5748 LongWidth = LongLongWidth = 32; 5749 PointerWidth = 32; 5750 IntAlign = 32; 5751 LongAlign = LongLongAlign = 32; 5752 PointerAlign = 32; 5753 SuitableAlign = 32; 5754 SizeType = UnsignedInt; 5755 IntMaxType = SignedLong; 5756 IntPtrType = SignedInt; 5757 PtrDiffType = SignedInt; 5758 FloatWidth = 32; 5759 FloatAlign = 32; 5760 DoubleWidth = 32; 5761 DoubleAlign = 32; 5762 LongDoubleWidth = 32; 5763 LongDoubleAlign = 32; 5764 FloatFormat = &llvm::APFloat::IEEEsingle; 5765 DoubleFormat = &llvm::APFloat::IEEEsingle; 5766 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5767 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5768 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5769 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5770 UseAddrSpaceMapMangling = true; 5771 } 5772 5773 void getTargetDefines(const LangOptions &Opts, 5774 MacroBuilder &Builder) const override { 5775 DefineStd(Builder, "tce", Opts); 5776 Builder.defineMacro("__TCE__"); 5777 Builder.defineMacro("__TCE_V1__"); 5778 } 5779 bool hasFeature(StringRef Feature) const override { 5780 return Feature == "tce"; 5781 } 5782 5783 void getTargetBuiltins(const Builtin::Info *&Records, 5784 unsigned &NumRecords) const override {} 5785 const char *getClobbers() const override { 5786 return ""; 5787 } 5788 BuiltinVaListKind getBuiltinVaListKind() const override { 5789 return TargetInfo::VoidPtrBuiltinVaList; 5790 } 5791 void getGCCRegNames(const char * const *&Names, 5792 unsigned &NumNames) const override {} 5793 bool validateAsmConstraint(const char *&Name, 5794 TargetInfo::ConstraintInfo &info) const override{ 5795 return true; 5796 } 5797 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5798 unsigned &NumAliases) const override {} 5799 }; 5800 5801 class MipsTargetInfoBase : public TargetInfo { 5802 virtual void setDescriptionString() = 0; 5803 5804 static const Builtin::Info BuiltinInfo[]; 5805 std::string CPU; 5806 bool IsMips16; 5807 bool IsMicromips; 5808 bool IsNan2008; 5809 bool IsSingleFloat; 5810 enum MipsFloatABI { 5811 HardFloat, SoftFloat 5812 } FloatABI; 5813 enum DspRevEnum { 5814 NoDSP, DSP1, DSP2 5815 } DspRev; 5816 bool HasMSA; 5817 5818 protected: 5819 bool HasFP64; 5820 std::string ABI; 5821 5822 public: 5823 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5824 const std::string &CPUStr) 5825 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5826 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5827 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 5828 TheCXXABI.set(TargetCXXABI::GenericMIPS); 5829 } 5830 5831 bool isNaN2008Default() const { 5832 return CPU == "mips32r6" || CPU == "mips64r6"; 5833 } 5834 5835 bool isFP64Default() const { 5836 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 5837 } 5838 5839 bool isNan2008() const override { 5840 return IsNan2008; 5841 } 5842 5843 StringRef getABI() const override { return ABI; } 5844 bool setCPU(const std::string &Name) override { 5845 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 5846 getTriple().getArch() == llvm::Triple::mipsel; 5847 CPU = Name; 5848 return llvm::StringSwitch<bool>(Name) 5849 .Case("mips1", IsMips32) 5850 .Case("mips2", IsMips32) 5851 .Case("mips3", true) 5852 .Case("mips4", true) 5853 .Case("mips5", true) 5854 .Case("mips32", IsMips32) 5855 .Case("mips32r2", IsMips32) 5856 .Case("mips32r3", IsMips32) 5857 .Case("mips32r5", IsMips32) 5858 .Case("mips32r6", IsMips32) 5859 .Case("mips64", true) 5860 .Case("mips64r2", true) 5861 .Case("mips64r3", true) 5862 .Case("mips64r5", true) 5863 .Case("mips64r6", true) 5864 .Case("octeon", true) 5865 .Default(false); 5866 } 5867 const std::string& getCPU() const { return CPU; } 5868 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5869 if (CPU == "octeon") 5870 Features["mips64r2"] = Features["cnmips"] = true; 5871 else 5872 Features[CPU] = true; 5873 } 5874 5875 void getTargetDefines(const LangOptions &Opts, 5876 MacroBuilder &Builder) const override { 5877 Builder.defineMacro("__mips__"); 5878 Builder.defineMacro("_mips"); 5879 if (Opts.GNUMode) 5880 Builder.defineMacro("mips"); 5881 5882 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5883 5884 switch (FloatABI) { 5885 case HardFloat: 5886 Builder.defineMacro("__mips_hard_float", Twine(1)); 5887 break; 5888 case SoftFloat: 5889 Builder.defineMacro("__mips_soft_float", Twine(1)); 5890 break; 5891 } 5892 5893 if (IsSingleFloat) 5894 Builder.defineMacro("__mips_single_float", Twine(1)); 5895 5896 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5897 Builder.defineMacro("_MIPS_FPSET", 5898 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5899 5900 if (IsMips16) 5901 Builder.defineMacro("__mips16", Twine(1)); 5902 5903 if (IsMicromips) 5904 Builder.defineMacro("__mips_micromips", Twine(1)); 5905 5906 if (IsNan2008) 5907 Builder.defineMacro("__mips_nan2008", Twine(1)); 5908 5909 switch (DspRev) { 5910 default: 5911 break; 5912 case DSP1: 5913 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5914 Builder.defineMacro("__mips_dsp", Twine(1)); 5915 break; 5916 case DSP2: 5917 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5918 Builder.defineMacro("__mips_dspr2", Twine(1)); 5919 Builder.defineMacro("__mips_dsp", Twine(1)); 5920 break; 5921 } 5922 5923 if (HasMSA) 5924 Builder.defineMacro("__mips_msa", Twine(1)); 5925 5926 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5927 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5928 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5929 5930 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5931 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5932 } 5933 5934 void getTargetBuiltins(const Builtin::Info *&Records, 5935 unsigned &NumRecords) const override { 5936 Records = BuiltinInfo; 5937 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5938 } 5939 bool hasFeature(StringRef Feature) const override { 5940 return llvm::StringSwitch<bool>(Feature) 5941 .Case("mips", true) 5942 .Case("fp64", HasFP64) 5943 .Default(false); 5944 } 5945 BuiltinVaListKind getBuiltinVaListKind() const override { 5946 return TargetInfo::VoidPtrBuiltinVaList; 5947 } 5948 void getGCCRegNames(const char * const *&Names, 5949 unsigned &NumNames) const override { 5950 static const char *const GCCRegNames[] = { 5951 // CPU register names 5952 // Must match second column of GCCRegAliases 5953 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5954 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5955 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5956 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5957 // Floating point register names 5958 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5959 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5960 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5961 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5962 // Hi/lo and condition register names 5963 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5964 "$fcc5","$fcc6","$fcc7", 5965 // MSA register names 5966 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5967 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5968 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5969 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5970 // MSA control register names 5971 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5972 "$msarequest", "$msamap", "$msaunmap" 5973 }; 5974 Names = GCCRegNames; 5975 NumNames = llvm::array_lengthof(GCCRegNames); 5976 } 5977 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5978 unsigned &NumAliases) const override = 0; 5979 bool validateAsmConstraint(const char *&Name, 5980 TargetInfo::ConstraintInfo &Info) const override { 5981 switch (*Name) { 5982 default: 5983 return false; 5984 case 'r': // CPU registers. 5985 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5986 case 'y': // Equivalent to "r", backward compatibility only. 5987 case 'f': // floating-point registers. 5988 case 'c': // $25 for indirect jumps 5989 case 'l': // lo register 5990 case 'x': // hilo register pair 5991 Info.setAllowsRegister(); 5992 return true; 5993 case 'I': // Signed 16-bit constant 5994 case 'J': // Integer 0 5995 case 'K': // Unsigned 16-bit constant 5996 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 5997 case 'M': // Constants not loadable via lui, addiu, or ori 5998 case 'N': // Constant -1 to -65535 5999 case 'O': // A signed 15-bit constant 6000 case 'P': // A constant between 1 go 65535 6001 return true; 6002 case 'R': // An address that can be used in a non-macro load or store 6003 Info.setAllowsMemory(); 6004 return true; 6005 case 'Z': 6006 if (Name[1] == 'C') { // An address usable by ll, and sc. 6007 Info.setAllowsMemory(); 6008 Name++; // Skip over 'Z'. 6009 return true; 6010 } 6011 return false; 6012 } 6013 } 6014 6015 std::string convertConstraint(const char *&Constraint) const override { 6016 std::string R; 6017 switch (*Constraint) { 6018 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6019 if (Constraint[1] == 'C') { 6020 R = std::string("^") + std::string(Constraint, 2); 6021 Constraint++; 6022 return R; 6023 } 6024 break; 6025 } 6026 return TargetInfo::convertConstraint(Constraint); 6027 } 6028 6029 const char *getClobbers() const override { 6030 // In GCC, $1 is not widely used in generated code (it's used only in a few 6031 // specific situations), so there is no real need for users to add it to 6032 // the clobbers list if they want to use it in their inline assembly code. 6033 // 6034 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6035 // code generation, so using it in inline assembly without adding it to the 6036 // clobbers list can cause conflicts between the inline assembly code and 6037 // the surrounding generated code. 6038 // 6039 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6040 // operands, which will conflict with the ".set at" assembler option (which 6041 // we use only for inline assembly, in order to maintain compatibility with 6042 // GCC) and will also conflict with the user's usage of $1. 6043 // 6044 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6045 // register for generated code is to automatically clobber $1 for all inline 6046 // assembly code. 6047 // 6048 // FIXME: We should automatically clobber $1 only for inline assembly code 6049 // which actually uses it. This would allow LLVM to use $1 for inline 6050 // assembly operands if the user's assembly code doesn't use it. 6051 return "~{$1}"; 6052 } 6053 6054 bool handleTargetFeatures(std::vector<std::string> &Features, 6055 DiagnosticsEngine &Diags) override { 6056 IsMips16 = false; 6057 IsMicromips = false; 6058 IsNan2008 = isNaN2008Default(); 6059 IsSingleFloat = false; 6060 FloatABI = HardFloat; 6061 DspRev = NoDSP; 6062 HasFP64 = isFP64Default(); 6063 6064 for (std::vector<std::string>::iterator it = Features.begin(), 6065 ie = Features.end(); it != ie; ++it) { 6066 if (*it == "+single-float") 6067 IsSingleFloat = true; 6068 else if (*it == "+soft-float") 6069 FloatABI = SoftFloat; 6070 else if (*it == "+mips16") 6071 IsMips16 = true; 6072 else if (*it == "+micromips") 6073 IsMicromips = true; 6074 else if (*it == "+dsp") 6075 DspRev = std::max(DspRev, DSP1); 6076 else if (*it == "+dspr2") 6077 DspRev = std::max(DspRev, DSP2); 6078 else if (*it == "+msa") 6079 HasMSA = true; 6080 else if (*it == "+fp64") 6081 HasFP64 = true; 6082 else if (*it == "-fp64") 6083 HasFP64 = false; 6084 else if (*it == "+nan2008") 6085 IsNan2008 = true; 6086 else if (*it == "-nan2008") 6087 IsNan2008 = false; 6088 } 6089 6090 // Remove front-end specific options. 6091 std::vector<std::string>::iterator it = 6092 std::find(Features.begin(), Features.end(), "+soft-float"); 6093 if (it != Features.end()) 6094 Features.erase(it); 6095 6096 setDescriptionString(); 6097 6098 return true; 6099 } 6100 6101 int getEHDataRegisterNumber(unsigned RegNo) const override { 6102 if (RegNo == 0) return 4; 6103 if (RegNo == 1) return 5; 6104 return -1; 6105 } 6106 6107 bool isCLZForZeroUndef() const override { return false; } 6108 }; 6109 6110 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6111 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6112 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6113 ALL_LANGUAGES }, 6114 #include "clang/Basic/BuiltinsMips.def" 6115 }; 6116 6117 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6118 public: 6119 Mips32TargetInfoBase(const llvm::Triple &Triple) 6120 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6121 SizeType = UnsignedInt; 6122 PtrDiffType = SignedInt; 6123 Int64Type = SignedLongLong; 6124 IntMaxType = Int64Type; 6125 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6126 } 6127 bool setABI(const std::string &Name) override { 6128 if (Name == "o32" || Name == "eabi") { 6129 ABI = Name; 6130 return true; 6131 } 6132 return false; 6133 } 6134 void getTargetDefines(const LangOptions &Opts, 6135 MacroBuilder &Builder) const override { 6136 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6137 6138 Builder.defineMacro("__mips", "32"); 6139 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6140 6141 const std::string& CPUStr = getCPU(); 6142 if (CPUStr == "mips32") 6143 Builder.defineMacro("__mips_isa_rev", "1"); 6144 else if (CPUStr == "mips32r2") 6145 Builder.defineMacro("__mips_isa_rev", "2"); 6146 else if (CPUStr == "mips32r3") 6147 Builder.defineMacro("__mips_isa_rev", "3"); 6148 else if (CPUStr == "mips32r5") 6149 Builder.defineMacro("__mips_isa_rev", "5"); 6150 else if (CPUStr == "mips32r6") 6151 Builder.defineMacro("__mips_isa_rev", "6"); 6152 6153 if (ABI == "o32") { 6154 Builder.defineMacro("__mips_o32"); 6155 Builder.defineMacro("_ABIO32", "1"); 6156 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6157 } 6158 else if (ABI == "eabi") 6159 Builder.defineMacro("__mips_eabi"); 6160 else 6161 llvm_unreachable("Invalid ABI for Mips32."); 6162 } 6163 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6164 unsigned &NumAliases) const override { 6165 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6166 { { "at" }, "$1" }, 6167 { { "v0" }, "$2" }, 6168 { { "v1" }, "$3" }, 6169 { { "a0" }, "$4" }, 6170 { { "a1" }, "$5" }, 6171 { { "a2" }, "$6" }, 6172 { { "a3" }, "$7" }, 6173 { { "t0" }, "$8" }, 6174 { { "t1" }, "$9" }, 6175 { { "t2" }, "$10" }, 6176 { { "t3" }, "$11" }, 6177 { { "t4" }, "$12" }, 6178 { { "t5" }, "$13" }, 6179 { { "t6" }, "$14" }, 6180 { { "t7" }, "$15" }, 6181 { { "s0" }, "$16" }, 6182 { { "s1" }, "$17" }, 6183 { { "s2" }, "$18" }, 6184 { { "s3" }, "$19" }, 6185 { { "s4" }, "$20" }, 6186 { { "s5" }, "$21" }, 6187 { { "s6" }, "$22" }, 6188 { { "s7" }, "$23" }, 6189 { { "t8" }, "$24" }, 6190 { { "t9" }, "$25" }, 6191 { { "k0" }, "$26" }, 6192 { { "k1" }, "$27" }, 6193 { { "gp" }, "$28" }, 6194 { { "sp","$sp" }, "$29" }, 6195 { { "fp","$fp" }, "$30" }, 6196 { { "ra" }, "$31" } 6197 }; 6198 Aliases = GCCRegAliases; 6199 NumAliases = llvm::array_lengthof(GCCRegAliases); 6200 } 6201 }; 6202 6203 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6204 void setDescriptionString() override { 6205 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6206 } 6207 6208 public: 6209 Mips32EBTargetInfo(const llvm::Triple &Triple) 6210 : Mips32TargetInfoBase(Triple) { 6211 } 6212 void getTargetDefines(const LangOptions &Opts, 6213 MacroBuilder &Builder) const override { 6214 DefineStd(Builder, "MIPSEB", Opts); 6215 Builder.defineMacro("_MIPSEB"); 6216 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6217 } 6218 }; 6219 6220 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6221 void setDescriptionString() override { 6222 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6223 } 6224 6225 public: 6226 Mips32ELTargetInfo(const llvm::Triple &Triple) 6227 : Mips32TargetInfoBase(Triple) { 6228 BigEndian = false; 6229 } 6230 void getTargetDefines(const LangOptions &Opts, 6231 MacroBuilder &Builder) const override { 6232 DefineStd(Builder, "MIPSEL", Opts); 6233 Builder.defineMacro("_MIPSEL"); 6234 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6235 } 6236 }; 6237 6238 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6239 public: 6240 Mips64TargetInfoBase(const llvm::Triple &Triple) 6241 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6242 LongDoubleWidth = LongDoubleAlign = 128; 6243 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6244 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6245 LongDoubleWidth = LongDoubleAlign = 64; 6246 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6247 } 6248 setN64ABITypes(); 6249 SuitableAlign = 128; 6250 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6251 } 6252 6253 void setN64ABITypes() { 6254 LongWidth = LongAlign = 64; 6255 PointerWidth = PointerAlign = 64; 6256 SizeType = UnsignedLong; 6257 PtrDiffType = SignedLong; 6258 Int64Type = SignedLong; 6259 IntMaxType = Int64Type; 6260 } 6261 6262 void setN32ABITypes() { 6263 LongWidth = LongAlign = 32; 6264 PointerWidth = PointerAlign = 32; 6265 SizeType = UnsignedInt; 6266 PtrDiffType = SignedInt; 6267 Int64Type = SignedLongLong; 6268 IntMaxType = Int64Type; 6269 } 6270 6271 bool setABI(const std::string &Name) override { 6272 if (Name == "n32") { 6273 setN32ABITypes(); 6274 ABI = Name; 6275 return true; 6276 } 6277 if (Name == "n64") { 6278 setN64ABITypes(); 6279 ABI = Name; 6280 return true; 6281 } 6282 return false; 6283 } 6284 6285 void getTargetDefines(const LangOptions &Opts, 6286 MacroBuilder &Builder) const override { 6287 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6288 6289 Builder.defineMacro("__mips", "64"); 6290 Builder.defineMacro("__mips64"); 6291 Builder.defineMacro("__mips64__"); 6292 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6293 6294 const std::string& CPUStr = getCPU(); 6295 if (CPUStr == "mips64") 6296 Builder.defineMacro("__mips_isa_rev", "1"); 6297 else if (CPUStr == "mips64r2") 6298 Builder.defineMacro("__mips_isa_rev", "2"); 6299 else if (CPUStr == "mips64r3") 6300 Builder.defineMacro("__mips_isa_rev", "3"); 6301 else if (CPUStr == "mips64r5") 6302 Builder.defineMacro("__mips_isa_rev", "5"); 6303 else if (CPUStr == "mips64r6") 6304 Builder.defineMacro("__mips_isa_rev", "6"); 6305 6306 if (ABI == "n32") { 6307 Builder.defineMacro("__mips_n32"); 6308 Builder.defineMacro("_ABIN32", "2"); 6309 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6310 } 6311 else if (ABI == "n64") { 6312 Builder.defineMacro("__mips_n64"); 6313 Builder.defineMacro("_ABI64", "3"); 6314 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6315 } 6316 else 6317 llvm_unreachable("Invalid ABI for Mips64."); 6318 } 6319 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6320 unsigned &NumAliases) const override { 6321 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6322 { { "at" }, "$1" }, 6323 { { "v0" }, "$2" }, 6324 { { "v1" }, "$3" }, 6325 { { "a0" }, "$4" }, 6326 { { "a1" }, "$5" }, 6327 { { "a2" }, "$6" }, 6328 { { "a3" }, "$7" }, 6329 { { "a4" }, "$8" }, 6330 { { "a5" }, "$9" }, 6331 { { "a6" }, "$10" }, 6332 { { "a7" }, "$11" }, 6333 { { "t0" }, "$12" }, 6334 { { "t1" }, "$13" }, 6335 { { "t2" }, "$14" }, 6336 { { "t3" }, "$15" }, 6337 { { "s0" }, "$16" }, 6338 { { "s1" }, "$17" }, 6339 { { "s2" }, "$18" }, 6340 { { "s3" }, "$19" }, 6341 { { "s4" }, "$20" }, 6342 { { "s5" }, "$21" }, 6343 { { "s6" }, "$22" }, 6344 { { "s7" }, "$23" }, 6345 { { "t8" }, "$24" }, 6346 { { "t9" }, "$25" }, 6347 { { "k0" }, "$26" }, 6348 { { "k1" }, "$27" }, 6349 { { "gp" }, "$28" }, 6350 { { "sp","$sp" }, "$29" }, 6351 { { "fp","$fp" }, "$30" }, 6352 { { "ra" }, "$31" } 6353 }; 6354 Aliases = GCCRegAliases; 6355 NumAliases = llvm::array_lengthof(GCCRegAliases); 6356 } 6357 6358 bool hasInt128Type() const override { return true; } 6359 }; 6360 6361 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6362 void setDescriptionString() override { 6363 if (ABI == "n32") 6364 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6365 else 6366 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6367 6368 } 6369 6370 public: 6371 Mips64EBTargetInfo(const llvm::Triple &Triple) 6372 : Mips64TargetInfoBase(Triple) {} 6373 void getTargetDefines(const LangOptions &Opts, 6374 MacroBuilder &Builder) const override { 6375 DefineStd(Builder, "MIPSEB", Opts); 6376 Builder.defineMacro("_MIPSEB"); 6377 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6378 } 6379 }; 6380 6381 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6382 void setDescriptionString() override { 6383 if (ABI == "n32") 6384 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6385 else 6386 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6387 } 6388 public: 6389 Mips64ELTargetInfo(const llvm::Triple &Triple) 6390 : Mips64TargetInfoBase(Triple) { 6391 // Default ABI is n64. 6392 BigEndian = false; 6393 } 6394 void getTargetDefines(const LangOptions &Opts, 6395 MacroBuilder &Builder) const override { 6396 DefineStd(Builder, "MIPSEL", Opts); 6397 Builder.defineMacro("_MIPSEL"); 6398 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6399 } 6400 }; 6401 6402 class PNaClTargetInfo : public TargetInfo { 6403 public: 6404 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6405 BigEndian = false; 6406 this->UserLabelPrefix = ""; 6407 this->LongAlign = 32; 6408 this->LongWidth = 32; 6409 this->PointerAlign = 32; 6410 this->PointerWidth = 32; 6411 this->IntMaxType = TargetInfo::SignedLongLong; 6412 this->Int64Type = TargetInfo::SignedLongLong; 6413 this->DoubleAlign = 64; 6414 this->LongDoubleWidth = 64; 6415 this->LongDoubleAlign = 64; 6416 this->SizeType = TargetInfo::UnsignedInt; 6417 this->PtrDiffType = TargetInfo::SignedInt; 6418 this->IntPtrType = TargetInfo::SignedInt; 6419 this->RegParmMax = 0; // Disallow regparm 6420 } 6421 6422 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6423 } 6424 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6425 Builder.defineMacro("__le32__"); 6426 Builder.defineMacro("__pnacl__"); 6427 } 6428 void getTargetDefines(const LangOptions &Opts, 6429 MacroBuilder &Builder) const override { 6430 getArchDefines(Opts, Builder); 6431 } 6432 bool hasFeature(StringRef Feature) const override { 6433 return Feature == "pnacl"; 6434 } 6435 void getTargetBuiltins(const Builtin::Info *&Records, 6436 unsigned &NumRecords) const override { 6437 } 6438 BuiltinVaListKind getBuiltinVaListKind() const override { 6439 return TargetInfo::PNaClABIBuiltinVaList; 6440 } 6441 void getGCCRegNames(const char * const *&Names, 6442 unsigned &NumNames) const override; 6443 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6444 unsigned &NumAliases) const override; 6445 bool validateAsmConstraint(const char *&Name, 6446 TargetInfo::ConstraintInfo &Info) const override { 6447 return false; 6448 } 6449 6450 const char *getClobbers() const override { 6451 return ""; 6452 } 6453 }; 6454 6455 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6456 unsigned &NumNames) const { 6457 Names = nullptr; 6458 NumNames = 0; 6459 } 6460 6461 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6462 unsigned &NumAliases) const { 6463 Aliases = nullptr; 6464 NumAliases = 0; 6465 } 6466 6467 class Le64TargetInfo : public TargetInfo { 6468 static const Builtin::Info BuiltinInfo[]; 6469 6470 public: 6471 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6472 BigEndian = false; 6473 NoAsmVariants = true; 6474 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6475 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6476 DescriptionString = 6477 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6478 } 6479 6480 void getTargetDefines(const LangOptions &Opts, 6481 MacroBuilder &Builder) const override { 6482 DefineStd(Builder, "unix", Opts); 6483 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6484 Builder.defineMacro("__ELF__"); 6485 } 6486 void getTargetBuiltins(const Builtin::Info *&Records, 6487 unsigned &NumRecords) const override { 6488 Records = BuiltinInfo; 6489 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6490 } 6491 BuiltinVaListKind getBuiltinVaListKind() const override { 6492 return TargetInfo::PNaClABIBuiltinVaList; 6493 } 6494 const char *getClobbers() const override { return ""; } 6495 void getGCCRegNames(const char *const *&Names, 6496 unsigned &NumNames) const override { 6497 Names = nullptr; 6498 NumNames = 0; 6499 } 6500 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6501 unsigned &NumAliases) const override { 6502 Aliases = nullptr; 6503 NumAliases = 0; 6504 } 6505 bool validateAsmConstraint(const char *&Name, 6506 TargetInfo::ConstraintInfo &Info) const override { 6507 return false; 6508 } 6509 6510 bool hasProtectedVisibility() const override { return false; } 6511 }; 6512 } // end anonymous namespace. 6513 6514 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 6515 #define BUILTIN(ID, TYPE, ATTRS) \ 6516 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6517 #include "clang/Basic/BuiltinsLe64.def" 6518 }; 6519 6520 namespace { 6521 static const unsigned SPIRAddrSpaceMap[] = { 6522 1, // opencl_global 6523 3, // opencl_local 6524 2, // opencl_constant 6525 4, // opencl_generic 6526 0, // cuda_device 6527 0, // cuda_constant 6528 0 // cuda_shared 6529 }; 6530 class SPIRTargetInfo : public TargetInfo { 6531 public: 6532 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6533 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 6534 "SPIR target must use unknown OS"); 6535 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 6536 "SPIR target must use unknown environment type"); 6537 BigEndian = false; 6538 TLSSupported = false; 6539 LongWidth = LongAlign = 64; 6540 AddrSpaceMap = &SPIRAddrSpaceMap; 6541 UseAddrSpaceMapMangling = true; 6542 // Define available target features 6543 // These must be defined in sorted order! 6544 NoAsmVariants = true; 6545 } 6546 void getTargetDefines(const LangOptions &Opts, 6547 MacroBuilder &Builder) const override { 6548 DefineStd(Builder, "SPIR", Opts); 6549 } 6550 bool hasFeature(StringRef Feature) const override { 6551 return Feature == "spir"; 6552 } 6553 6554 void getTargetBuiltins(const Builtin::Info *&Records, 6555 unsigned &NumRecords) const override {} 6556 const char *getClobbers() const override { 6557 return ""; 6558 } 6559 void getGCCRegNames(const char * const *&Names, 6560 unsigned &NumNames) const override {} 6561 bool 6562 validateAsmConstraint(const char *&Name, 6563 TargetInfo::ConstraintInfo &info) const override { 6564 return true; 6565 } 6566 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6567 unsigned &NumAliases) const override {} 6568 BuiltinVaListKind getBuiltinVaListKind() const override { 6569 return TargetInfo::VoidPtrBuiltinVaList; 6570 } 6571 6572 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6573 return (CC == CC_SpirFunction || 6574 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning; 6575 } 6576 6577 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 6578 return CC_SpirFunction; 6579 } 6580 }; 6581 6582 6583 class SPIR32TargetInfo : public SPIRTargetInfo { 6584 public: 6585 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6586 PointerWidth = PointerAlign = 32; 6587 SizeType = TargetInfo::UnsignedInt; 6588 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6589 DescriptionString 6590 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6591 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6592 } 6593 void getTargetDefines(const LangOptions &Opts, 6594 MacroBuilder &Builder) const override { 6595 DefineStd(Builder, "SPIR32", Opts); 6596 } 6597 }; 6598 6599 class SPIR64TargetInfo : public SPIRTargetInfo { 6600 public: 6601 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6602 PointerWidth = PointerAlign = 64; 6603 SizeType = TargetInfo::UnsignedLong; 6604 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6605 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6606 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6607 } 6608 void getTargetDefines(const LangOptions &Opts, 6609 MacroBuilder &Builder) const override { 6610 DefineStd(Builder, "SPIR64", Opts); 6611 } 6612 }; 6613 6614 class XCoreTargetInfo : public TargetInfo { 6615 static const Builtin::Info BuiltinInfo[]; 6616 public: 6617 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6618 BigEndian = false; 6619 NoAsmVariants = true; 6620 LongLongAlign = 32; 6621 SuitableAlign = 32; 6622 DoubleAlign = LongDoubleAlign = 32; 6623 SizeType = UnsignedInt; 6624 PtrDiffType = SignedInt; 6625 IntPtrType = SignedInt; 6626 WCharType = UnsignedChar; 6627 WIntType = UnsignedInt; 6628 UseZeroLengthBitfieldAlignment = true; 6629 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6630 "-f64:32-a:0:32-n32"; 6631 } 6632 void getTargetDefines(const LangOptions &Opts, 6633 MacroBuilder &Builder) const override { 6634 Builder.defineMacro("__XS1B__"); 6635 } 6636 void getTargetBuiltins(const Builtin::Info *&Records, 6637 unsigned &NumRecords) const override { 6638 Records = BuiltinInfo; 6639 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6640 } 6641 BuiltinVaListKind getBuiltinVaListKind() const override { 6642 return TargetInfo::VoidPtrBuiltinVaList; 6643 } 6644 const char *getClobbers() const override { 6645 return ""; 6646 } 6647 void getGCCRegNames(const char * const *&Names, 6648 unsigned &NumNames) const override { 6649 static const char * const GCCRegNames[] = { 6650 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6651 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6652 }; 6653 Names = GCCRegNames; 6654 NumNames = llvm::array_lengthof(GCCRegNames); 6655 } 6656 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6657 unsigned &NumAliases) const override { 6658 Aliases = nullptr; 6659 NumAliases = 0; 6660 } 6661 bool validateAsmConstraint(const char *&Name, 6662 TargetInfo::ConstraintInfo &Info) const override { 6663 return false; 6664 } 6665 int getEHDataRegisterNumber(unsigned RegNo) const override { 6666 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6667 return (RegNo < 2)? RegNo : -1; 6668 } 6669 }; 6670 6671 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6672 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6673 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6674 ALL_LANGUAGES }, 6675 #include "clang/Basic/BuiltinsXCore.def" 6676 }; 6677 } // end anonymous namespace. 6678 6679 namespace { 6680 // x86_32 Android target 6681 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 6682 public: 6683 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 6684 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 6685 SuitableAlign = 32; 6686 LongDoubleWidth = 64; 6687 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6688 } 6689 }; 6690 } // end anonymous namespace 6691 6692 namespace { 6693 // x86_64 Android target 6694 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 6695 public: 6696 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 6697 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 6698 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6699 } 6700 }; 6701 } // end anonymous namespace 6702 6703 6704 //===----------------------------------------------------------------------===// 6705 // Driver code 6706 //===----------------------------------------------------------------------===// 6707 6708 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 6709 llvm::Triple::OSType os = Triple.getOS(); 6710 6711 switch (Triple.getArch()) { 6712 default: 6713 return nullptr; 6714 6715 case llvm::Triple::xcore: 6716 return new XCoreTargetInfo(Triple); 6717 6718 case llvm::Triple::hexagon: 6719 return new HexagonTargetInfo(Triple); 6720 6721 case llvm::Triple::aarch64: 6722 if (Triple.isOSDarwin()) 6723 return new DarwinAArch64TargetInfo(Triple); 6724 6725 switch (os) { 6726 case llvm::Triple::FreeBSD: 6727 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 6728 case llvm::Triple::Linux: 6729 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6730 case llvm::Triple::NetBSD: 6731 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6732 default: 6733 return new AArch64leTargetInfo(Triple); 6734 } 6735 6736 case llvm::Triple::aarch64_be: 6737 switch (os) { 6738 case llvm::Triple::FreeBSD: 6739 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 6740 case llvm::Triple::Linux: 6741 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6742 case llvm::Triple::NetBSD: 6743 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6744 default: 6745 return new AArch64beTargetInfo(Triple); 6746 } 6747 6748 case llvm::Triple::arm: 6749 case llvm::Triple::thumb: 6750 if (Triple.isOSBinFormatMachO()) 6751 return new DarwinARMTargetInfo(Triple); 6752 6753 switch (os) { 6754 case llvm::Triple::Linux: 6755 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6756 case llvm::Triple::FreeBSD: 6757 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6758 case llvm::Triple::NetBSD: 6759 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6760 case llvm::Triple::OpenBSD: 6761 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6762 case llvm::Triple::Bitrig: 6763 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6764 case llvm::Triple::RTEMS: 6765 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6766 case llvm::Triple::NaCl: 6767 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6768 case llvm::Triple::Win32: 6769 switch (Triple.getEnvironment()) { 6770 default: 6771 return new ARMleTargetInfo(Triple); 6772 case llvm::Triple::Itanium: 6773 return new ItaniumWindowsARMleTargetInfo(Triple); 6774 case llvm::Triple::MSVC: 6775 return new MicrosoftARMleTargetInfo(Triple); 6776 } 6777 default: 6778 return new ARMleTargetInfo(Triple); 6779 } 6780 6781 case llvm::Triple::armeb: 6782 case llvm::Triple::thumbeb: 6783 if (Triple.isOSDarwin()) 6784 return new DarwinARMTargetInfo(Triple); 6785 6786 switch (os) { 6787 case llvm::Triple::Linux: 6788 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 6789 case llvm::Triple::FreeBSD: 6790 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 6791 case llvm::Triple::NetBSD: 6792 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 6793 case llvm::Triple::OpenBSD: 6794 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 6795 case llvm::Triple::Bitrig: 6796 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 6797 case llvm::Triple::RTEMS: 6798 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 6799 case llvm::Triple::NaCl: 6800 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 6801 default: 6802 return new ARMbeTargetInfo(Triple); 6803 } 6804 6805 case llvm::Triple::msp430: 6806 return new MSP430TargetInfo(Triple); 6807 6808 case llvm::Triple::mips: 6809 switch (os) { 6810 case llvm::Triple::Linux: 6811 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 6812 case llvm::Triple::RTEMS: 6813 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 6814 case llvm::Triple::FreeBSD: 6815 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6816 case llvm::Triple::NetBSD: 6817 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6818 default: 6819 return new Mips32EBTargetInfo(Triple); 6820 } 6821 6822 case llvm::Triple::mipsel: 6823 switch (os) { 6824 case llvm::Triple::Linux: 6825 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 6826 case llvm::Triple::RTEMS: 6827 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 6828 case llvm::Triple::FreeBSD: 6829 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6830 case llvm::Triple::NetBSD: 6831 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6832 case llvm::Triple::NaCl: 6833 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 6834 default: 6835 return new Mips32ELTargetInfo(Triple); 6836 } 6837 6838 case llvm::Triple::mips64: 6839 switch (os) { 6840 case llvm::Triple::Linux: 6841 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 6842 case llvm::Triple::RTEMS: 6843 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 6844 case llvm::Triple::FreeBSD: 6845 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6846 case llvm::Triple::NetBSD: 6847 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6848 case llvm::Triple::OpenBSD: 6849 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6850 default: 6851 return new Mips64EBTargetInfo(Triple); 6852 } 6853 6854 case llvm::Triple::mips64el: 6855 switch (os) { 6856 case llvm::Triple::Linux: 6857 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 6858 case llvm::Triple::RTEMS: 6859 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 6860 case llvm::Triple::FreeBSD: 6861 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6862 case llvm::Triple::NetBSD: 6863 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6864 case llvm::Triple::OpenBSD: 6865 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6866 default: 6867 return new Mips64ELTargetInfo(Triple); 6868 } 6869 6870 case llvm::Triple::le32: 6871 switch (os) { 6872 case llvm::Triple::NaCl: 6873 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 6874 default: 6875 return nullptr; 6876 } 6877 6878 case llvm::Triple::le64: 6879 return new Le64TargetInfo(Triple); 6880 6881 case llvm::Triple::ppc: 6882 if (Triple.isOSDarwin()) 6883 return new DarwinPPC32TargetInfo(Triple); 6884 switch (os) { 6885 case llvm::Triple::Linux: 6886 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 6887 case llvm::Triple::FreeBSD: 6888 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 6889 case llvm::Triple::NetBSD: 6890 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 6891 case llvm::Triple::OpenBSD: 6892 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 6893 case llvm::Triple::RTEMS: 6894 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 6895 default: 6896 return new PPC32TargetInfo(Triple); 6897 } 6898 6899 case llvm::Triple::ppc64: 6900 if (Triple.isOSDarwin()) 6901 return new DarwinPPC64TargetInfo(Triple); 6902 switch (os) { 6903 case llvm::Triple::Linux: 6904 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6905 case llvm::Triple::Lv2: 6906 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 6907 case llvm::Triple::FreeBSD: 6908 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 6909 case llvm::Triple::NetBSD: 6910 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6911 default: 6912 return new PPC64TargetInfo(Triple); 6913 } 6914 6915 case llvm::Triple::ppc64le: 6916 switch (os) { 6917 case llvm::Triple::Linux: 6918 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6919 case llvm::Triple::NetBSD: 6920 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6921 default: 6922 return new PPC64TargetInfo(Triple); 6923 } 6924 6925 case llvm::Triple::nvptx: 6926 return new NVPTX32TargetInfo(Triple); 6927 case llvm::Triple::nvptx64: 6928 return new NVPTX64TargetInfo(Triple); 6929 6930 case llvm::Triple::amdgcn: 6931 case llvm::Triple::r600: 6932 return new R600TargetInfo(Triple); 6933 6934 case llvm::Triple::sparc: 6935 switch (os) { 6936 case llvm::Triple::Linux: 6937 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 6938 case llvm::Triple::Solaris: 6939 return new SolarisSparcV8TargetInfo(Triple); 6940 case llvm::Triple::NetBSD: 6941 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 6942 case llvm::Triple::OpenBSD: 6943 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 6944 case llvm::Triple::RTEMS: 6945 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 6946 default: 6947 return new SparcV8TargetInfo(Triple); 6948 } 6949 6950 case llvm::Triple::sparcv9: 6951 switch (os) { 6952 case llvm::Triple::Linux: 6953 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 6954 case llvm::Triple::Solaris: 6955 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 6956 case llvm::Triple::NetBSD: 6957 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 6958 case llvm::Triple::OpenBSD: 6959 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 6960 case llvm::Triple::FreeBSD: 6961 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 6962 default: 6963 return new SparcV9TargetInfo(Triple); 6964 } 6965 6966 case llvm::Triple::systemz: 6967 switch (os) { 6968 case llvm::Triple::Linux: 6969 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 6970 default: 6971 return new SystemZTargetInfo(Triple); 6972 } 6973 6974 case llvm::Triple::tce: 6975 return new TCETargetInfo(Triple); 6976 6977 case llvm::Triple::x86: 6978 if (Triple.isOSDarwin()) 6979 return new DarwinI386TargetInfo(Triple); 6980 6981 switch (os) { 6982 case llvm::Triple::Linux: { 6983 switch (Triple.getEnvironment()) { 6984 default: 6985 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 6986 case llvm::Triple::Android: 6987 return new AndroidX86_32TargetInfo(Triple); 6988 } 6989 } 6990 case llvm::Triple::DragonFly: 6991 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 6992 case llvm::Triple::NetBSD: 6993 return new NetBSDI386TargetInfo(Triple); 6994 case llvm::Triple::OpenBSD: 6995 return new OpenBSDI386TargetInfo(Triple); 6996 case llvm::Triple::Bitrig: 6997 return new BitrigI386TargetInfo(Triple); 6998 case llvm::Triple::FreeBSD: 6999 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7000 case llvm::Triple::KFreeBSD: 7001 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7002 case llvm::Triple::Minix: 7003 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7004 case llvm::Triple::Solaris: 7005 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7006 case llvm::Triple::Win32: { 7007 switch (Triple.getEnvironment()) { 7008 default: 7009 return new X86_32TargetInfo(Triple); 7010 case llvm::Triple::Cygnus: 7011 return new CygwinX86_32TargetInfo(Triple); 7012 case llvm::Triple::GNU: 7013 return new MinGWX86_32TargetInfo(Triple); 7014 case llvm::Triple::Itanium: 7015 case llvm::Triple::MSVC: 7016 return new MicrosoftX86_32TargetInfo(Triple); 7017 } 7018 } 7019 case llvm::Triple::Haiku: 7020 return new HaikuX86_32TargetInfo(Triple); 7021 case llvm::Triple::RTEMS: 7022 return new RTEMSX86_32TargetInfo(Triple); 7023 case llvm::Triple::NaCl: 7024 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7025 default: 7026 return new X86_32TargetInfo(Triple); 7027 } 7028 7029 case llvm::Triple::x86_64: 7030 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7031 return new DarwinX86_64TargetInfo(Triple); 7032 7033 switch (os) { 7034 case llvm::Triple::CloudABI: 7035 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7036 case llvm::Triple::Linux: { 7037 switch (Triple.getEnvironment()) { 7038 default: 7039 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7040 case llvm::Triple::Android: 7041 return new AndroidX86_64TargetInfo(Triple); 7042 } 7043 } 7044 case llvm::Triple::DragonFly: 7045 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7046 case llvm::Triple::NetBSD: 7047 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7048 case llvm::Triple::OpenBSD: 7049 return new OpenBSDX86_64TargetInfo(Triple); 7050 case llvm::Triple::Bitrig: 7051 return new BitrigX86_64TargetInfo(Triple); 7052 case llvm::Triple::FreeBSD: 7053 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7054 case llvm::Triple::KFreeBSD: 7055 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7056 case llvm::Triple::Solaris: 7057 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7058 case llvm::Triple::Win32: { 7059 switch (Triple.getEnvironment()) { 7060 default: 7061 return new X86_64TargetInfo(Triple); 7062 case llvm::Triple::GNU: 7063 return new MinGWX86_64TargetInfo(Triple); 7064 case llvm::Triple::MSVC: 7065 return new MicrosoftX86_64TargetInfo(Triple); 7066 } 7067 } 7068 case llvm::Triple::NaCl: 7069 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7070 case llvm::Triple::PS4: 7071 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7072 default: 7073 return new X86_64TargetInfo(Triple); 7074 } 7075 7076 case llvm::Triple::spir: { 7077 if (Triple.getOS() != llvm::Triple::UnknownOS || 7078 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7079 return nullptr; 7080 return new SPIR32TargetInfo(Triple); 7081 } 7082 case llvm::Triple::spir64: { 7083 if (Triple.getOS() != llvm::Triple::UnknownOS || 7084 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7085 return nullptr; 7086 return new SPIR64TargetInfo(Triple); 7087 } 7088 } 7089 } 7090 7091 /// CreateTargetInfo - Return the target info object for the specified target 7092 /// triple. 7093 TargetInfo * 7094 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7095 const std::shared_ptr<TargetOptions> &Opts) { 7096 llvm::Triple Triple(Opts->Triple); 7097 7098 // Construct the target 7099 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7100 if (!Target) { 7101 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7102 return nullptr; 7103 } 7104 Target->TargetOpts = Opts; 7105 7106 // Set the target CPU if specified. 7107 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7108 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7109 return nullptr; 7110 } 7111 7112 // Set the target ABI if specified. 7113 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7114 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7115 return nullptr; 7116 } 7117 7118 // Set the fp math unit. 7119 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7120 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7121 return nullptr; 7122 } 7123 7124 // Compute the default target features, we need the target to handle this 7125 // because features may have dependencies on one another. 7126 llvm::StringMap<bool> Features; 7127 Target->getDefaultFeatures(Features); 7128 7129 // Apply the user specified deltas. 7130 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 7131 I < N; ++I) { 7132 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 7133 // Apply the feature via the target. 7134 bool Enabled = Name[0] == '+'; 7135 Target->setFeatureEnabled(Features, Name + 1, Enabled); 7136 } 7137 7138 // Add the features to the compile options. 7139 // 7140 // FIXME: If we are completely confident that we have the right set, we only 7141 // need to pass the minuses. 7142 Opts->Features.clear(); 7143 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 7144 ie = Features.end(); it != ie; ++it) 7145 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 7146 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7147 return nullptr; 7148 7149 return Target.release(); 7150 } 7151