1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "llvm/ADT/APFloat.h" 25 #include "llvm/ADT/STLExtras.h" 26 #include "llvm/ADT/StringExtras.h" 27 #include "llvm/ADT/StringRef.h" 28 #include "llvm/ADT/StringSwitch.h" 29 #include "llvm/ADT/Triple.h" 30 #include "llvm/MC/MCSectionMachO.h" 31 #include "llvm/Support/ErrorHandling.h" 32 #include "llvm/Support/TargetParser.h" 33 #include <algorithm> 34 #include <memory> 35 36 using namespace clang; 37 38 //===----------------------------------------------------------------------===// 39 // Common code shared among targets. 40 //===----------------------------------------------------------------------===// 41 42 /// DefineStd - Define a macro name and standard variants. For example if 43 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 44 /// when in GNU mode. 45 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 46 const LangOptions &Opts) { 47 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 48 49 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 50 // in the user's namespace. 51 if (Opts.GNUMode) 52 Builder.defineMacro(MacroName); 53 54 // Define __unix. 55 Builder.defineMacro("__" + MacroName); 56 57 // Define __unix__. 58 Builder.defineMacro("__" + MacroName + "__"); 59 } 60 61 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 62 bool Tuning = true) { 63 Builder.defineMacro("__" + CPUName); 64 Builder.defineMacro("__" + CPUName + "__"); 65 if (Tuning) 66 Builder.defineMacro("__tune_" + CPUName + "__"); 67 } 68 69 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 70 const TargetOptions &Opts); 71 72 //===----------------------------------------------------------------------===// 73 // Defines specific to certain operating systems. 74 //===----------------------------------------------------------------------===// 75 76 namespace { 77 template<typename TgtInfo> 78 class OSTargetInfo : public TgtInfo { 79 protected: 80 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 81 MacroBuilder &Builder) const=0; 82 public: 83 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 84 : TgtInfo(Triple, Opts) {} 85 void getTargetDefines(const LangOptions &Opts, 86 MacroBuilder &Builder) const override { 87 TgtInfo::getTargetDefines(Opts, Builder); 88 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 89 } 90 91 }; 92 93 // CloudABI Target 94 template <typename Target> 95 class CloudABITargetInfo : public OSTargetInfo<Target> { 96 protected: 97 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 98 MacroBuilder &Builder) const override { 99 Builder.defineMacro("__CloudABI__"); 100 Builder.defineMacro("__ELF__"); 101 102 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 103 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 104 Builder.defineMacro("__STDC_UTF_16__"); 105 Builder.defineMacro("__STDC_UTF_32__"); 106 } 107 108 public: 109 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 110 : OSTargetInfo<Target>(Triple, Opts) {} 111 }; 112 113 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 114 const llvm::Triple &Triple, 115 StringRef &PlatformName, 116 VersionTuple &PlatformMinVersion) { 117 Builder.defineMacro("__APPLE_CC__", "6000"); 118 Builder.defineMacro("__APPLE__"); 119 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 120 // AddressSanitizer doesn't play well with source fortification, which is on 121 // by default on Darwin. 122 if (Opts.Sanitize.has(SanitizerKind::Address)) 123 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 124 125 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 126 if (!Opts.ObjC1) { 127 // __weak is always defined, for use in blocks and with objc pointers. 128 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 129 Builder.defineMacro("__strong", ""); 130 Builder.defineMacro("__unsafe_unretained", ""); 131 } 132 133 if (Opts.Static) 134 Builder.defineMacro("__STATIC__"); 135 else 136 Builder.defineMacro("__DYNAMIC__"); 137 138 if (Opts.POSIXThreads) 139 Builder.defineMacro("_REENTRANT"); 140 141 // Get the platform type and version number from the triple. 142 unsigned Maj, Min, Rev; 143 if (Triple.isMacOSX()) { 144 Triple.getMacOSXVersion(Maj, Min, Rev); 145 PlatformName = "macos"; 146 } else { 147 Triple.getOSVersion(Maj, Min, Rev); 148 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 149 } 150 151 // If -target arch-pc-win32-macho option specified, we're 152 // generating code for Win32 ABI. No need to emit 153 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 154 if (PlatformName == "win32") { 155 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 156 return; 157 } 158 159 // Set the appropriate OS version define. 160 if (Triple.isiOS()) { 161 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 162 char Str[7]; 163 if (Maj < 10) { 164 Str[0] = '0' + Maj; 165 Str[1] = '0' + (Min / 10); 166 Str[2] = '0' + (Min % 10); 167 Str[3] = '0' + (Rev / 10); 168 Str[4] = '0' + (Rev % 10); 169 Str[5] = '\0'; 170 } else { 171 // Handle versions >= 10. 172 Str[0] = '0' + (Maj / 10); 173 Str[1] = '0' + (Maj % 10); 174 Str[2] = '0' + (Min / 10); 175 Str[3] = '0' + (Min % 10); 176 Str[4] = '0' + (Rev / 10); 177 Str[5] = '0' + (Rev % 10); 178 Str[6] = '\0'; 179 } 180 if (Triple.isTvOS()) 181 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 182 else 183 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 184 Str); 185 186 } else if (Triple.isWatchOS()) { 187 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 188 char Str[6]; 189 Str[0] = '0' + Maj; 190 Str[1] = '0' + (Min / 10); 191 Str[2] = '0' + (Min % 10); 192 Str[3] = '0' + (Rev / 10); 193 Str[4] = '0' + (Rev % 10); 194 Str[5] = '\0'; 195 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 196 } else if (Triple.isMacOSX()) { 197 // Note that the Driver allows versions which aren't representable in the 198 // define (because we only get a single digit for the minor and micro 199 // revision numbers). So, we limit them to the maximum representable 200 // version. 201 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 202 char Str[7]; 203 if (Maj < 10 || (Maj == 10 && Min < 10)) { 204 Str[0] = '0' + (Maj / 10); 205 Str[1] = '0' + (Maj % 10); 206 Str[2] = '0' + std::min(Min, 9U); 207 Str[3] = '0' + std::min(Rev, 9U); 208 Str[4] = '\0'; 209 } else { 210 // Handle versions > 10.9. 211 Str[0] = '0' + (Maj / 10); 212 Str[1] = '0' + (Maj % 10); 213 Str[2] = '0' + (Min / 10); 214 Str[3] = '0' + (Min % 10); 215 Str[4] = '0' + (Rev / 10); 216 Str[5] = '0' + (Rev % 10); 217 Str[6] = '\0'; 218 } 219 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 220 } 221 222 // Tell users about the kernel if there is one. 223 if (Triple.isOSDarwin()) 224 Builder.defineMacro("__MACH__"); 225 226 // The Watch ABI uses Dwarf EH. 227 if(Triple.isWatchABI()) 228 Builder.defineMacro("__ARM_DWARF_EH__"); 229 230 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 231 } 232 233 template<typename Target> 234 class DarwinTargetInfo : public OSTargetInfo<Target> { 235 protected: 236 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 237 MacroBuilder &Builder) const override { 238 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 239 this->PlatformMinVersion); 240 } 241 242 public: 243 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 244 : OSTargetInfo<Target>(Triple, Opts) { 245 // By default, no TLS, and we whitelist permitted architecture/OS 246 // combinations. 247 this->TLSSupported = false; 248 249 if (Triple.isMacOSX()) 250 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 251 else if (Triple.isiOS()) { 252 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 253 if (Triple.getArch() == llvm::Triple::x86_64 || 254 Triple.getArch() == llvm::Triple::aarch64) 255 this->TLSSupported = !Triple.isOSVersionLT(8); 256 else if (Triple.getArch() == llvm::Triple::x86 || 257 Triple.getArch() == llvm::Triple::arm || 258 Triple.getArch() == llvm::Triple::thumb) 259 this->TLSSupported = !Triple.isOSVersionLT(9); 260 } else if (Triple.isWatchOS()) 261 this->TLSSupported = !Triple.isOSVersionLT(2); 262 263 this->MCountName = "\01mcount"; 264 } 265 266 std::string isValidSectionSpecifier(StringRef SR) const override { 267 // Let MCSectionMachO validate this. 268 StringRef Segment, Section; 269 unsigned TAA, StubSize; 270 bool HasTAA; 271 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 272 TAA, HasTAA, StubSize); 273 } 274 275 const char *getStaticInitSectionSpecifier() const override { 276 // FIXME: We should return 0 when building kexts. 277 return "__TEXT,__StaticInit,regular,pure_instructions"; 278 } 279 280 /// Darwin does not support protected visibility. Darwin's "default" 281 /// is very similar to ELF's "protected"; Darwin requires a "weak" 282 /// attribute on declarations that can be dynamically replaced. 283 bool hasProtectedVisibility() const override { 284 return false; 285 } 286 287 unsigned getExnObjectAlignment() const override { 288 // The alignment of an exception object is 8-bytes for darwin since 289 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 290 // and therefore doesn't guarantee 16-byte alignment. 291 return 64; 292 } 293 }; 294 295 296 // DragonFlyBSD Target 297 template<typename Target> 298 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 299 protected: 300 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 301 MacroBuilder &Builder) const override { 302 // DragonFly defines; list based off of gcc output 303 Builder.defineMacro("__DragonFly__"); 304 Builder.defineMacro("__DragonFly_cc_version", "100001"); 305 Builder.defineMacro("__ELF__"); 306 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 307 Builder.defineMacro("__tune_i386__"); 308 DefineStd(Builder, "unix", Opts); 309 } 310 public: 311 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 312 : OSTargetInfo<Target>(Triple, Opts) { 313 switch (Triple.getArch()) { 314 default: 315 case llvm::Triple::x86: 316 case llvm::Triple::x86_64: 317 this->MCountName = ".mcount"; 318 break; 319 } 320 } 321 }; 322 323 #ifndef FREEBSD_CC_VERSION 324 #define FREEBSD_CC_VERSION 0U 325 #endif 326 327 // FreeBSD Target 328 template<typename Target> 329 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 330 protected: 331 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 332 MacroBuilder &Builder) const override { 333 // FreeBSD defines; list based off of gcc output 334 335 unsigned Release = Triple.getOSMajorVersion(); 336 if (Release == 0U) 337 Release = 8U; 338 unsigned CCVersion = FREEBSD_CC_VERSION; 339 if (CCVersion == 0U) 340 CCVersion = Release * 100000U + 1U; 341 342 Builder.defineMacro("__FreeBSD__", Twine(Release)); 343 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 344 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 345 DefineStd(Builder, "unix", Opts); 346 Builder.defineMacro("__ELF__"); 347 348 // On FreeBSD, wchar_t contains the number of the code point as 349 // used by the character set of the locale. These character sets are 350 // not necessarily a superset of ASCII. 351 // 352 // FIXME: This is wrong; the macro refers to the numerical values 353 // of wchar_t *literals*, which are not locale-dependent. However, 354 // FreeBSD systems apparently depend on us getting this wrong, and 355 // setting this to 1 is conforming even if all the basic source 356 // character literals have the same encoding as char and wchar_t. 357 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 358 } 359 public: 360 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 361 : OSTargetInfo<Target>(Triple, Opts) { 362 switch (Triple.getArch()) { 363 default: 364 case llvm::Triple::x86: 365 case llvm::Triple::x86_64: 366 this->MCountName = ".mcount"; 367 break; 368 case llvm::Triple::mips: 369 case llvm::Triple::mipsel: 370 case llvm::Triple::ppc: 371 case llvm::Triple::ppc64: 372 case llvm::Triple::ppc64le: 373 this->MCountName = "_mcount"; 374 break; 375 case llvm::Triple::arm: 376 this->MCountName = "__mcount"; 377 break; 378 } 379 } 380 }; 381 382 // GNU/kFreeBSD Target 383 template<typename Target> 384 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 385 protected: 386 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 387 MacroBuilder &Builder) const override { 388 // GNU/kFreeBSD defines; list based off of gcc output 389 390 DefineStd(Builder, "unix", Opts); 391 Builder.defineMacro("__FreeBSD_kernel__"); 392 Builder.defineMacro("__GLIBC__"); 393 Builder.defineMacro("__ELF__"); 394 if (Opts.POSIXThreads) 395 Builder.defineMacro("_REENTRANT"); 396 if (Opts.CPlusPlus) 397 Builder.defineMacro("_GNU_SOURCE"); 398 } 399 public: 400 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 401 : OSTargetInfo<Target>(Triple, Opts) {} 402 }; 403 404 // Haiku Target 405 template<typename Target> 406 class HaikuTargetInfo : public OSTargetInfo<Target> { 407 protected: 408 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 409 MacroBuilder &Builder) const override { 410 // Haiku defines; list based off of gcc output 411 Builder.defineMacro("__HAIKU__"); 412 Builder.defineMacro("__ELF__"); 413 DefineStd(Builder, "unix", Opts); 414 } 415 public: 416 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 417 : OSTargetInfo<Target>(Triple, Opts) { 418 this->SizeType = TargetInfo::UnsignedLong; 419 this->IntPtrType = TargetInfo::SignedLong; 420 this->PtrDiffType = TargetInfo::SignedLong; 421 this->ProcessIDType = TargetInfo::SignedLong; 422 this->TLSSupported = false; 423 424 } 425 }; 426 427 // Minix Target 428 template<typename Target> 429 class MinixTargetInfo : public OSTargetInfo<Target> { 430 protected: 431 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 432 MacroBuilder &Builder) const override { 433 // Minix defines 434 435 Builder.defineMacro("__minix", "3"); 436 Builder.defineMacro("_EM_WSIZE", "4"); 437 Builder.defineMacro("_EM_PSIZE", "4"); 438 Builder.defineMacro("_EM_SSIZE", "2"); 439 Builder.defineMacro("_EM_LSIZE", "4"); 440 Builder.defineMacro("_EM_FSIZE", "4"); 441 Builder.defineMacro("_EM_DSIZE", "8"); 442 Builder.defineMacro("__ELF__"); 443 DefineStd(Builder, "unix", Opts); 444 } 445 public: 446 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 447 : OSTargetInfo<Target>(Triple, Opts) {} 448 }; 449 450 // Linux target 451 template<typename Target> 452 class LinuxTargetInfo : public OSTargetInfo<Target> { 453 protected: 454 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 455 MacroBuilder &Builder) const override { 456 // Linux defines; list based off of gcc output 457 DefineStd(Builder, "unix", Opts); 458 DefineStd(Builder, "linux", Opts); 459 Builder.defineMacro("__gnu_linux__"); 460 Builder.defineMacro("__ELF__"); 461 if (Triple.isAndroid()) { 462 Builder.defineMacro("__ANDROID__", "1"); 463 unsigned Maj, Min, Rev; 464 Triple.getEnvironmentVersion(Maj, Min, Rev); 465 this->PlatformName = "android"; 466 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 467 } 468 if (Opts.POSIXThreads) 469 Builder.defineMacro("_REENTRANT"); 470 if (Opts.CPlusPlus) 471 Builder.defineMacro("_GNU_SOURCE"); 472 if (this->HasFloat128) 473 Builder.defineMacro("__FLOAT128__"); 474 } 475 public: 476 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 477 : OSTargetInfo<Target>(Triple, Opts) { 478 this->WIntType = TargetInfo::UnsignedInt; 479 480 switch (Triple.getArch()) { 481 default: 482 break; 483 case llvm::Triple::ppc: 484 case llvm::Triple::ppc64: 485 case llvm::Triple::ppc64le: 486 this->MCountName = "_mcount"; 487 break; 488 case llvm::Triple::x86: 489 case llvm::Triple::x86_64: 490 case llvm::Triple::systemz: 491 this->HasFloat128 = true; 492 break; 493 } 494 } 495 496 const char *getStaticInitSectionSpecifier() const override { 497 return ".text.startup"; 498 } 499 }; 500 501 // NetBSD Target 502 template<typename Target> 503 class NetBSDTargetInfo : public OSTargetInfo<Target> { 504 protected: 505 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 506 MacroBuilder &Builder) const override { 507 // NetBSD defines; list based off of gcc output 508 Builder.defineMacro("__NetBSD__"); 509 Builder.defineMacro("__unix__"); 510 Builder.defineMacro("__ELF__"); 511 if (Opts.POSIXThreads) 512 Builder.defineMacro("_POSIX_THREADS"); 513 514 switch (Triple.getArch()) { 515 default: 516 break; 517 case llvm::Triple::arm: 518 case llvm::Triple::armeb: 519 case llvm::Triple::thumb: 520 case llvm::Triple::thumbeb: 521 Builder.defineMacro("__ARM_DWARF_EH__"); 522 break; 523 } 524 } 525 public: 526 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 527 : OSTargetInfo<Target>(Triple, Opts) { 528 this->MCountName = "_mcount"; 529 } 530 }; 531 532 // OpenBSD Target 533 template<typename Target> 534 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 535 protected: 536 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 537 MacroBuilder &Builder) const override { 538 // OpenBSD defines; list based off of gcc output 539 540 Builder.defineMacro("__OpenBSD__"); 541 DefineStd(Builder, "unix", Opts); 542 Builder.defineMacro("__ELF__"); 543 if (Opts.POSIXThreads) 544 Builder.defineMacro("_REENTRANT"); 545 } 546 public: 547 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 548 : OSTargetInfo<Target>(Triple, Opts) { 549 this->TLSSupported = false; 550 551 switch (Triple.getArch()) { 552 default: 553 case llvm::Triple::x86: 554 case llvm::Triple::x86_64: 555 case llvm::Triple::arm: 556 case llvm::Triple::sparc: 557 this->MCountName = "__mcount"; 558 break; 559 case llvm::Triple::mips64: 560 case llvm::Triple::mips64el: 561 case llvm::Triple::ppc: 562 case llvm::Triple::sparcv9: 563 this->MCountName = "_mcount"; 564 break; 565 } 566 } 567 }; 568 569 // Bitrig Target 570 template<typename Target> 571 class BitrigTargetInfo : public OSTargetInfo<Target> { 572 protected: 573 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 574 MacroBuilder &Builder) const override { 575 // Bitrig defines; list based off of gcc output 576 577 Builder.defineMacro("__Bitrig__"); 578 DefineStd(Builder, "unix", Opts); 579 Builder.defineMacro("__ELF__"); 580 if (Opts.POSIXThreads) 581 Builder.defineMacro("_REENTRANT"); 582 583 switch (Triple.getArch()) { 584 default: 585 break; 586 case llvm::Triple::arm: 587 case llvm::Triple::armeb: 588 case llvm::Triple::thumb: 589 case llvm::Triple::thumbeb: 590 Builder.defineMacro("__ARM_DWARF_EH__"); 591 break; 592 } 593 } 594 public: 595 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 596 : OSTargetInfo<Target>(Triple, Opts) { 597 this->MCountName = "__mcount"; 598 } 599 }; 600 601 // PSP Target 602 template<typename Target> 603 class PSPTargetInfo : public OSTargetInfo<Target> { 604 protected: 605 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 606 MacroBuilder &Builder) const override { 607 // PSP defines; list based on the output of the pspdev gcc toolchain. 608 Builder.defineMacro("PSP"); 609 Builder.defineMacro("_PSP"); 610 Builder.defineMacro("__psp__"); 611 Builder.defineMacro("__ELF__"); 612 } 613 public: 614 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 615 }; 616 617 // PS3 PPU Target 618 template<typename Target> 619 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 620 protected: 621 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 622 MacroBuilder &Builder) const override { 623 // PS3 PPU defines. 624 Builder.defineMacro("__PPC__"); 625 Builder.defineMacro("__PPU__"); 626 Builder.defineMacro("__CELLOS_LV2__"); 627 Builder.defineMacro("__ELF__"); 628 Builder.defineMacro("__LP32__"); 629 Builder.defineMacro("_ARCH_PPC64"); 630 Builder.defineMacro("__powerpc64__"); 631 } 632 public: 633 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 634 : OSTargetInfo<Target>(Triple, Opts) { 635 this->LongWidth = this->LongAlign = 32; 636 this->PointerWidth = this->PointerAlign = 32; 637 this->IntMaxType = TargetInfo::SignedLongLong; 638 this->Int64Type = TargetInfo::SignedLongLong; 639 this->SizeType = TargetInfo::UnsignedInt; 640 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 641 } 642 }; 643 644 template <typename Target> 645 class PS4OSTargetInfo : public OSTargetInfo<Target> { 646 protected: 647 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 648 MacroBuilder &Builder) const override { 649 Builder.defineMacro("__FreeBSD__", "9"); 650 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 651 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 652 DefineStd(Builder, "unix", Opts); 653 Builder.defineMacro("__ELF__"); 654 Builder.defineMacro("__ORBIS__"); 655 } 656 public: 657 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 658 : OSTargetInfo<Target>(Triple, Opts) { 659 this->WCharType = this->UnsignedShort; 660 661 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 662 this->MaxTLSAlign = 256; 663 664 // On PS4, do not honor explicit bit field alignment, 665 // as in "__attribute__((aligned(2))) int b : 1;". 666 this->UseExplicitBitFieldAlignment = false; 667 668 switch (Triple.getArch()) { 669 default: 670 case llvm::Triple::x86_64: 671 this->MCountName = ".mcount"; 672 break; 673 } 674 } 675 }; 676 677 // Solaris target 678 template<typename Target> 679 class SolarisTargetInfo : public OSTargetInfo<Target> { 680 protected: 681 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 682 MacroBuilder &Builder) const override { 683 DefineStd(Builder, "sun", Opts); 684 DefineStd(Builder, "unix", Opts); 685 Builder.defineMacro("__ELF__"); 686 Builder.defineMacro("__svr4__"); 687 Builder.defineMacro("__SVR4"); 688 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 689 // newer, but to 500 for everything else. feature_test.h has a check to 690 // ensure that you are not using C99 with an old version of X/Open or C89 691 // with a new version. 692 if (Opts.C99) 693 Builder.defineMacro("_XOPEN_SOURCE", "600"); 694 else 695 Builder.defineMacro("_XOPEN_SOURCE", "500"); 696 if (Opts.CPlusPlus) 697 Builder.defineMacro("__C99FEATURES__"); 698 Builder.defineMacro("_LARGEFILE_SOURCE"); 699 Builder.defineMacro("_LARGEFILE64_SOURCE"); 700 Builder.defineMacro("__EXTENSIONS__"); 701 Builder.defineMacro("_REENTRANT"); 702 } 703 public: 704 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 705 : OSTargetInfo<Target>(Triple, Opts) { 706 this->WCharType = this->SignedInt; 707 // FIXME: WIntType should be SignedLong 708 } 709 }; 710 711 // Windows target 712 template<typename Target> 713 class WindowsTargetInfo : public OSTargetInfo<Target> { 714 protected: 715 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 716 MacroBuilder &Builder) const override { 717 Builder.defineMacro("_WIN32"); 718 } 719 void getVisualStudioDefines(const LangOptions &Opts, 720 MacroBuilder &Builder) const { 721 if (Opts.CPlusPlus) { 722 if (Opts.RTTIData) 723 Builder.defineMacro("_CPPRTTI"); 724 725 if (Opts.CXXExceptions) 726 Builder.defineMacro("_CPPUNWIND"); 727 } 728 729 if (Opts.Bool) 730 Builder.defineMacro("__BOOL_DEFINED"); 731 732 if (!Opts.CharIsSigned) 733 Builder.defineMacro("_CHAR_UNSIGNED"); 734 735 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 736 // but it works for now. 737 if (Opts.POSIXThreads) 738 Builder.defineMacro("_MT"); 739 740 if (Opts.MSCompatibilityVersion) { 741 Builder.defineMacro("_MSC_VER", 742 Twine(Opts.MSCompatibilityVersion / 100000)); 743 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 744 // FIXME We cannot encode the revision information into 32-bits 745 Builder.defineMacro("_MSC_BUILD", Twine(1)); 746 747 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 748 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 749 750 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 751 if (Opts.CPlusPlus1z) 752 Builder.defineMacro("_MSVC_LANG", "201403L"); 753 else if (Opts.CPlusPlus14) 754 Builder.defineMacro("_MSVC_LANG", "201402L"); 755 } 756 } 757 758 if (Opts.MicrosoftExt) { 759 Builder.defineMacro("_MSC_EXTENSIONS"); 760 761 if (Opts.CPlusPlus11) { 762 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 763 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 764 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 765 } 766 } 767 768 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 769 } 770 771 public: 772 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 773 : OSTargetInfo<Target>(Triple, Opts) {} 774 }; 775 776 template <typename Target> 777 class NaClTargetInfo : public OSTargetInfo<Target> { 778 protected: 779 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 780 MacroBuilder &Builder) const override { 781 if (Opts.POSIXThreads) 782 Builder.defineMacro("_REENTRANT"); 783 if (Opts.CPlusPlus) 784 Builder.defineMacro("_GNU_SOURCE"); 785 786 DefineStd(Builder, "unix", Opts); 787 Builder.defineMacro("__ELF__"); 788 Builder.defineMacro("__native_client__"); 789 } 790 791 public: 792 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 793 : OSTargetInfo<Target>(Triple, Opts) { 794 this->LongAlign = 32; 795 this->LongWidth = 32; 796 this->PointerAlign = 32; 797 this->PointerWidth = 32; 798 this->IntMaxType = TargetInfo::SignedLongLong; 799 this->Int64Type = TargetInfo::SignedLongLong; 800 this->DoubleAlign = 64; 801 this->LongDoubleWidth = 64; 802 this->LongDoubleAlign = 64; 803 this->LongLongWidth = 64; 804 this->LongLongAlign = 64; 805 this->SizeType = TargetInfo::UnsignedInt; 806 this->PtrDiffType = TargetInfo::SignedInt; 807 this->IntPtrType = TargetInfo::SignedInt; 808 // RegParmMax is inherited from the underlying architecture 809 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 810 if (Triple.getArch() == llvm::Triple::arm) { 811 // Handled in ARM's setABI(). 812 } else if (Triple.getArch() == llvm::Triple::x86) { 813 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 814 } else if (Triple.getArch() == llvm::Triple::x86_64) { 815 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 816 } else if (Triple.getArch() == llvm::Triple::mipsel) { 817 // Handled on mips' setDataLayout. 818 } else { 819 assert(Triple.getArch() == llvm::Triple::le32); 820 this->resetDataLayout("e-p:32:32-i64:64"); 821 } 822 } 823 }; 824 825 // WebAssembly target 826 template <typename Target> 827 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 828 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 829 MacroBuilder &Builder) const final { 830 // A common platform macro. 831 if (Opts.POSIXThreads) 832 Builder.defineMacro("_REENTRANT"); 833 // Follow g++ convention and predefine _GNU_SOURCE for C++. 834 if (Opts.CPlusPlus) 835 Builder.defineMacro("_GNU_SOURCE"); 836 } 837 838 // As an optimization, group static init code together in a section. 839 const char *getStaticInitSectionSpecifier() const final { 840 return ".text.__startup"; 841 } 842 843 public: 844 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 845 const TargetOptions &Opts) 846 : OSTargetInfo<Target>(Triple, Opts) { 847 this->MCountName = "__mcount"; 848 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 849 } 850 }; 851 852 //===----------------------------------------------------------------------===// 853 // Specific target implementations. 854 //===----------------------------------------------------------------------===// 855 856 // PPC abstract base class 857 class PPCTargetInfo : public TargetInfo { 858 static const Builtin::Info BuiltinInfo[]; 859 static const char * const GCCRegNames[]; 860 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 861 std::string CPU; 862 863 // Target cpu features. 864 bool HasVSX; 865 bool HasP8Vector; 866 bool HasP8Crypto; 867 bool HasDirectMove; 868 bool HasQPX; 869 bool HasHTM; 870 bool HasBPERMD; 871 bool HasExtDiv; 872 873 protected: 874 std::string ABI; 875 876 public: 877 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 878 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 879 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 880 HasBPERMD(false), HasExtDiv(false) { 881 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 882 SimdDefaultAlign = 128; 883 LongDoubleWidth = LongDoubleAlign = 128; 884 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 885 } 886 887 /// \brief Flags for architecture specific defines. 888 typedef enum { 889 ArchDefineNone = 0, 890 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 891 ArchDefinePpcgr = 1 << 1, 892 ArchDefinePpcsq = 1 << 2, 893 ArchDefine440 = 1 << 3, 894 ArchDefine603 = 1 << 4, 895 ArchDefine604 = 1 << 5, 896 ArchDefinePwr4 = 1 << 6, 897 ArchDefinePwr5 = 1 << 7, 898 ArchDefinePwr5x = 1 << 8, 899 ArchDefinePwr6 = 1 << 9, 900 ArchDefinePwr6x = 1 << 10, 901 ArchDefinePwr7 = 1 << 11, 902 ArchDefinePwr8 = 1 << 12, 903 ArchDefinePwr9 = 1 << 13, 904 ArchDefineA2 = 1 << 14, 905 ArchDefineA2q = 1 << 15 906 } ArchDefineTypes; 907 908 // Note: GCC recognizes the following additional cpus: 909 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 910 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 911 // titan, rs64. 912 bool setCPU(const std::string &Name) override { 913 bool CPUKnown = llvm::StringSwitch<bool>(Name) 914 .Case("generic", true) 915 .Case("440", true) 916 .Case("450", true) 917 .Case("601", true) 918 .Case("602", true) 919 .Case("603", true) 920 .Case("603e", true) 921 .Case("603ev", true) 922 .Case("604", true) 923 .Case("604e", true) 924 .Case("620", true) 925 .Case("630", true) 926 .Case("g3", true) 927 .Case("7400", true) 928 .Case("g4", true) 929 .Case("7450", true) 930 .Case("g4+", true) 931 .Case("750", true) 932 .Case("970", true) 933 .Case("g5", true) 934 .Case("a2", true) 935 .Case("a2q", true) 936 .Case("e500mc", true) 937 .Case("e5500", true) 938 .Case("power3", true) 939 .Case("pwr3", true) 940 .Case("power4", true) 941 .Case("pwr4", true) 942 .Case("power5", true) 943 .Case("pwr5", true) 944 .Case("power5x", true) 945 .Case("pwr5x", true) 946 .Case("power6", true) 947 .Case("pwr6", true) 948 .Case("power6x", true) 949 .Case("pwr6x", true) 950 .Case("power7", true) 951 .Case("pwr7", true) 952 .Case("power8", true) 953 .Case("pwr8", true) 954 .Case("power9", true) 955 .Case("pwr9", true) 956 .Case("powerpc", true) 957 .Case("ppc", true) 958 .Case("powerpc64", true) 959 .Case("ppc64", true) 960 .Case("powerpc64le", true) 961 .Case("ppc64le", true) 962 .Default(false); 963 964 if (CPUKnown) 965 CPU = Name; 966 967 return CPUKnown; 968 } 969 970 971 StringRef getABI() const override { return ABI; } 972 973 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 974 return llvm::makeArrayRef(BuiltinInfo, 975 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 976 } 977 978 bool isCLZForZeroUndef() const override { return false; } 979 980 void getTargetDefines(const LangOptions &Opts, 981 MacroBuilder &Builder) const override; 982 983 bool 984 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 985 StringRef CPU, 986 const std::vector<std::string> &FeaturesVec) const override; 987 988 bool handleTargetFeatures(std::vector<std::string> &Features, 989 DiagnosticsEngine &Diags) override; 990 bool hasFeature(StringRef Feature) const override; 991 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 992 bool Enabled) const override; 993 994 ArrayRef<const char *> getGCCRegNames() const override; 995 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 996 bool validateAsmConstraint(const char *&Name, 997 TargetInfo::ConstraintInfo &Info) const override { 998 switch (*Name) { 999 default: return false; 1000 case 'O': // Zero 1001 break; 1002 case 'b': // Base register 1003 case 'f': // Floating point register 1004 Info.setAllowsRegister(); 1005 break; 1006 // FIXME: The following are added to allow parsing. 1007 // I just took a guess at what the actions should be. 1008 // Also, is more specific checking needed? I.e. specific registers? 1009 case 'd': // Floating point register (containing 64-bit value) 1010 case 'v': // Altivec vector register 1011 Info.setAllowsRegister(); 1012 break; 1013 case 'w': 1014 switch (Name[1]) { 1015 case 'd':// VSX vector register to hold vector double data 1016 case 'f':// VSX vector register to hold vector float data 1017 case 's':// VSX vector register to hold scalar float data 1018 case 'a':// Any VSX register 1019 case 'c':// An individual CR bit 1020 break; 1021 default: 1022 return false; 1023 } 1024 Info.setAllowsRegister(); 1025 Name++; // Skip over 'w'. 1026 break; 1027 case 'h': // `MQ', `CTR', or `LINK' register 1028 case 'q': // `MQ' register 1029 case 'c': // `CTR' register 1030 case 'l': // `LINK' register 1031 case 'x': // `CR' register (condition register) number 0 1032 case 'y': // `CR' register (condition register) 1033 case 'z': // `XER[CA]' carry bit (part of the XER register) 1034 Info.setAllowsRegister(); 1035 break; 1036 case 'I': // Signed 16-bit constant 1037 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1038 // (use `L' instead for SImode constants) 1039 case 'K': // Unsigned 16-bit constant 1040 case 'L': // Signed 16-bit constant shifted left 16 bits 1041 case 'M': // Constant larger than 31 1042 case 'N': // Exact power of 2 1043 case 'P': // Constant whose negation is a signed 16-bit constant 1044 case 'G': // Floating point constant that can be loaded into a 1045 // register with one instruction per word 1046 case 'H': // Integer/Floating point constant that can be loaded 1047 // into a register using three instructions 1048 break; 1049 case 'm': // Memory operand. Note that on PowerPC targets, m can 1050 // include addresses that update the base register. It 1051 // is therefore only safe to use `m' in an asm statement 1052 // if that asm statement accesses the operand exactly once. 1053 // The asm statement must also use `%U<opno>' as a 1054 // placeholder for the "update" flag in the corresponding 1055 // load or store instruction. For example: 1056 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1057 // is correct but: 1058 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1059 // is not. Use es rather than m if you don't want the base 1060 // register to be updated. 1061 case 'e': 1062 if (Name[1] != 's') 1063 return false; 1064 // es: A "stable" memory operand; that is, one which does not 1065 // include any automodification of the base register. Unlike 1066 // `m', this constraint can be used in asm statements that 1067 // might access the operand several times, or that might not 1068 // access it at all. 1069 Info.setAllowsMemory(); 1070 Name++; // Skip over 'e'. 1071 break; 1072 case 'Q': // Memory operand that is an offset from a register (it is 1073 // usually better to use `m' or `es' in asm statements) 1074 case 'Z': // Memory operand that is an indexed or indirect from a 1075 // register (it is usually better to use `m' or `es' in 1076 // asm statements) 1077 Info.setAllowsMemory(); 1078 Info.setAllowsRegister(); 1079 break; 1080 case 'R': // AIX TOC entry 1081 case 'a': // Address operand that is an indexed or indirect from a 1082 // register (`p' is preferable for asm statements) 1083 case 'S': // Constant suitable as a 64-bit mask operand 1084 case 'T': // Constant suitable as a 32-bit mask operand 1085 case 'U': // System V Release 4 small data area reference 1086 case 't': // AND masks that can be performed by two rldic{l, r} 1087 // instructions 1088 case 'W': // Vector constant that does not require memory 1089 case 'j': // Vector constant that is all zeros. 1090 break; 1091 // End FIXME. 1092 } 1093 return true; 1094 } 1095 std::string convertConstraint(const char *&Constraint) const override { 1096 std::string R; 1097 switch (*Constraint) { 1098 case 'e': 1099 case 'w': 1100 // Two-character constraint; add "^" hint for later parsing. 1101 R = std::string("^") + std::string(Constraint, 2); 1102 Constraint++; 1103 break; 1104 default: 1105 return TargetInfo::convertConstraint(Constraint); 1106 } 1107 return R; 1108 } 1109 const char *getClobbers() const override { 1110 return ""; 1111 } 1112 int getEHDataRegisterNumber(unsigned RegNo) const override { 1113 if (RegNo == 0) return 3; 1114 if (RegNo == 1) return 4; 1115 return -1; 1116 } 1117 1118 bool hasSjLjLowering() const override { 1119 return true; 1120 } 1121 1122 bool useFloat128ManglingForLongDouble() const override { 1123 return LongDoubleWidth == 128 && 1124 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1125 getTriple().isOSBinFormatELF(); 1126 } 1127 }; 1128 1129 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1130 #define BUILTIN(ID, TYPE, ATTRS) \ 1131 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1132 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1133 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1134 #include "clang/Basic/BuiltinsPPC.def" 1135 }; 1136 1137 /// handleTargetFeatures - Perform initialization based on the user 1138 /// configured set of features. 1139 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1140 DiagnosticsEngine &Diags) { 1141 for (const auto &Feature : Features) { 1142 if (Feature == "+vsx") { 1143 HasVSX = true; 1144 } else if (Feature == "+bpermd") { 1145 HasBPERMD = true; 1146 } else if (Feature == "+extdiv") { 1147 HasExtDiv = true; 1148 } else if (Feature == "+power8-vector") { 1149 HasP8Vector = true; 1150 } else if (Feature == "+crypto") { 1151 HasP8Crypto = true; 1152 } else if (Feature == "+direct-move") { 1153 HasDirectMove = true; 1154 } else if (Feature == "+qpx") { 1155 HasQPX = true; 1156 } else if (Feature == "+htm") { 1157 HasHTM = true; 1158 } else if (Feature == "+float128") { 1159 HasFloat128 = true; 1160 } 1161 // TODO: Finish this list and add an assert that we've handled them 1162 // all. 1163 } 1164 1165 return true; 1166 } 1167 1168 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1169 /// #defines that are not tied to a specific subtarget. 1170 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1171 MacroBuilder &Builder) const { 1172 // Target identification. 1173 Builder.defineMacro("__ppc__"); 1174 Builder.defineMacro("__PPC__"); 1175 Builder.defineMacro("_ARCH_PPC"); 1176 Builder.defineMacro("__powerpc__"); 1177 Builder.defineMacro("__POWERPC__"); 1178 if (PointerWidth == 64) { 1179 Builder.defineMacro("_ARCH_PPC64"); 1180 Builder.defineMacro("__powerpc64__"); 1181 Builder.defineMacro("__ppc64__"); 1182 Builder.defineMacro("__PPC64__"); 1183 } 1184 1185 // Target properties. 1186 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1187 Builder.defineMacro("_LITTLE_ENDIAN"); 1188 } else { 1189 if (getTriple().getOS() != llvm::Triple::NetBSD && 1190 getTriple().getOS() != llvm::Triple::OpenBSD) 1191 Builder.defineMacro("_BIG_ENDIAN"); 1192 } 1193 1194 // ABI options. 1195 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1196 Builder.defineMacro("_CALL_ELF", "1"); 1197 if (ABI == "elfv2") 1198 Builder.defineMacro("_CALL_ELF", "2"); 1199 1200 // Subtarget options. 1201 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1202 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1203 1204 // FIXME: Should be controlled by command line option. 1205 if (LongDoubleWidth == 128) 1206 Builder.defineMacro("__LONG_DOUBLE_128__"); 1207 1208 if (Opts.AltiVec) { 1209 Builder.defineMacro("__VEC__", "10206"); 1210 Builder.defineMacro("__ALTIVEC__"); 1211 } 1212 1213 // CPU identification. 1214 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1215 .Case("440", ArchDefineName) 1216 .Case("450", ArchDefineName | ArchDefine440) 1217 .Case("601", ArchDefineName) 1218 .Case("602", ArchDefineName | ArchDefinePpcgr) 1219 .Case("603", ArchDefineName | ArchDefinePpcgr) 1220 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1221 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1222 .Case("604", ArchDefineName | ArchDefinePpcgr) 1223 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1224 .Case("620", ArchDefineName | ArchDefinePpcgr) 1225 .Case("630", ArchDefineName | ArchDefinePpcgr) 1226 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1227 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1228 .Case("750", ArchDefineName | ArchDefinePpcgr) 1229 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1230 | ArchDefinePpcsq) 1231 .Case("a2", ArchDefineA2) 1232 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1233 .Case("pwr3", ArchDefinePpcgr) 1234 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1235 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1236 | ArchDefinePpcsq) 1237 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1238 | ArchDefinePpcgr | ArchDefinePpcsq) 1239 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1240 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1241 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1242 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1243 | ArchDefinePpcsq) 1244 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1245 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1246 | ArchDefinePpcgr | ArchDefinePpcsq) 1247 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1248 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1249 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1250 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1251 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1252 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1253 | ArchDefinePpcsq) 1254 .Case("power3", ArchDefinePpcgr) 1255 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1256 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1257 | ArchDefinePpcsq) 1258 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1259 | ArchDefinePpcgr | ArchDefinePpcsq) 1260 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1261 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1262 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1263 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1264 | ArchDefinePpcsq) 1265 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1266 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1267 | ArchDefinePpcgr | ArchDefinePpcsq) 1268 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1269 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1270 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1271 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1272 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1273 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1274 | ArchDefinePpcsq) 1275 .Default(ArchDefineNone); 1276 1277 if (defs & ArchDefineName) 1278 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1279 if (defs & ArchDefinePpcgr) 1280 Builder.defineMacro("_ARCH_PPCGR"); 1281 if (defs & ArchDefinePpcsq) 1282 Builder.defineMacro("_ARCH_PPCSQ"); 1283 if (defs & ArchDefine440) 1284 Builder.defineMacro("_ARCH_440"); 1285 if (defs & ArchDefine603) 1286 Builder.defineMacro("_ARCH_603"); 1287 if (defs & ArchDefine604) 1288 Builder.defineMacro("_ARCH_604"); 1289 if (defs & ArchDefinePwr4) 1290 Builder.defineMacro("_ARCH_PWR4"); 1291 if (defs & ArchDefinePwr5) 1292 Builder.defineMacro("_ARCH_PWR5"); 1293 if (defs & ArchDefinePwr5x) 1294 Builder.defineMacro("_ARCH_PWR5X"); 1295 if (defs & ArchDefinePwr6) 1296 Builder.defineMacro("_ARCH_PWR6"); 1297 if (defs & ArchDefinePwr6x) 1298 Builder.defineMacro("_ARCH_PWR6X"); 1299 if (defs & ArchDefinePwr7) 1300 Builder.defineMacro("_ARCH_PWR7"); 1301 if (defs & ArchDefinePwr8) 1302 Builder.defineMacro("_ARCH_PWR8"); 1303 if (defs & ArchDefinePwr9) 1304 Builder.defineMacro("_ARCH_PWR9"); 1305 if (defs & ArchDefineA2) 1306 Builder.defineMacro("_ARCH_A2"); 1307 if (defs & ArchDefineA2q) { 1308 Builder.defineMacro("_ARCH_A2Q"); 1309 Builder.defineMacro("_ARCH_QP"); 1310 } 1311 1312 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1313 Builder.defineMacro("__bg__"); 1314 Builder.defineMacro("__THW_BLUEGENE__"); 1315 Builder.defineMacro("__bgq__"); 1316 Builder.defineMacro("__TOS_BGQ__"); 1317 } 1318 1319 if (HasVSX) 1320 Builder.defineMacro("__VSX__"); 1321 if (HasP8Vector) 1322 Builder.defineMacro("__POWER8_VECTOR__"); 1323 if (HasP8Crypto) 1324 Builder.defineMacro("__CRYPTO__"); 1325 if (HasHTM) 1326 Builder.defineMacro("__HTM__"); 1327 if (HasFloat128) 1328 Builder.defineMacro("__FLOAT128__"); 1329 1330 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1331 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1332 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1333 if (PointerWidth == 64) 1334 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1335 1336 // FIXME: The following are not yet generated here by Clang, but are 1337 // generated by GCC: 1338 // 1339 // _SOFT_FLOAT_ 1340 // __RECIP_PRECISION__ 1341 // __APPLE_ALTIVEC__ 1342 // __RECIP__ 1343 // __RECIPF__ 1344 // __RSQRTE__ 1345 // __RSQRTEF__ 1346 // _SOFT_DOUBLE_ 1347 // __NO_LWSYNC__ 1348 // __HAVE_BSWAP__ 1349 // __LONGDOUBLE128 1350 // __CMODEL_MEDIUM__ 1351 // __CMODEL_LARGE__ 1352 // _CALL_SYSV 1353 // _CALL_DARWIN 1354 // __NO_FPRS__ 1355 } 1356 1357 // Handle explicit options being passed to the compiler here: if we've 1358 // explicitly turned off vsx and turned on power8-vector or direct-move then 1359 // go ahead and error since the customer has expressed a somewhat incompatible 1360 // set of options. 1361 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1362 const std::vector<std::string> &FeaturesVec) { 1363 1364 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1365 FeaturesVec.end()) { 1366 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1367 FeaturesVec.end()) { 1368 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1369 << "-mno-vsx"; 1370 return false; 1371 } 1372 1373 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1374 FeaturesVec.end()) { 1375 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1376 << "-mno-vsx"; 1377 return false; 1378 } 1379 1380 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1381 FeaturesVec.end()) { 1382 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1383 << "-mno-vsx"; 1384 return false; 1385 } 1386 } 1387 1388 return true; 1389 } 1390 1391 bool PPCTargetInfo::initFeatureMap( 1392 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1393 const std::vector<std::string> &FeaturesVec) const { 1394 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1395 .Case("7400", true) 1396 .Case("g4", true) 1397 .Case("7450", true) 1398 .Case("g4+", true) 1399 .Case("970", true) 1400 .Case("g5", true) 1401 .Case("pwr6", true) 1402 .Case("pwr7", true) 1403 .Case("pwr8", true) 1404 .Case("pwr9", true) 1405 .Case("ppc64", true) 1406 .Case("ppc64le", true) 1407 .Default(false); 1408 1409 Features["qpx"] = (CPU == "a2q"); 1410 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1411 .Case("ppc64le", true) 1412 .Case("pwr9", true) 1413 .Case("pwr8", true) 1414 .Default(false); 1415 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1416 .Case("ppc64le", true) 1417 .Case("pwr9", true) 1418 .Case("pwr8", true) 1419 .Default(false); 1420 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1421 .Case("ppc64le", true) 1422 .Case("pwr9", true) 1423 .Case("pwr8", true) 1424 .Case("pwr7", true) 1425 .Default(false); 1426 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1427 .Case("ppc64le", true) 1428 .Case("pwr9", true) 1429 .Case("pwr8", true) 1430 .Case("pwr7", true) 1431 .Default(false); 1432 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1433 .Case("ppc64le", true) 1434 .Case("pwr9", true) 1435 .Case("pwr8", true) 1436 .Default(false); 1437 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1438 .Case("ppc64le", true) 1439 .Case("pwr9", true) 1440 .Case("pwr8", true) 1441 .Case("pwr7", true) 1442 .Default(false); 1443 1444 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1445 return false; 1446 1447 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1448 } 1449 1450 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1451 return llvm::StringSwitch<bool>(Feature) 1452 .Case("powerpc", true) 1453 .Case("vsx", HasVSX) 1454 .Case("power8-vector", HasP8Vector) 1455 .Case("crypto", HasP8Crypto) 1456 .Case("direct-move", HasDirectMove) 1457 .Case("qpx", HasQPX) 1458 .Case("htm", HasHTM) 1459 .Case("bpermd", HasBPERMD) 1460 .Case("extdiv", HasExtDiv) 1461 .Case("float128", HasFloat128) 1462 .Default(false); 1463 } 1464 1465 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1466 StringRef Name, bool Enabled) const { 1467 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1468 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1469 // incompatible options. 1470 if (Enabled) { 1471 if (Name == "direct-move") { 1472 Features[Name] = Features["vsx"] = true; 1473 } else if (Name == "power8-vector") { 1474 Features[Name] = Features["vsx"] = true; 1475 } else if (Name == "float128") { 1476 Features[Name] = Features["vsx"] = true; 1477 } else { 1478 Features[Name] = true; 1479 } 1480 } else { 1481 if (Name == "vsx") { 1482 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1483 Features["float128"] = false; 1484 } else { 1485 Features[Name] = false; 1486 } 1487 } 1488 } 1489 1490 const char * const PPCTargetInfo::GCCRegNames[] = { 1491 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1492 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1493 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1494 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1495 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1496 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1497 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1498 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1499 "mq", "lr", "ctr", "ap", 1500 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1501 "xer", 1502 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1503 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1504 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1505 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1506 "vrsave", "vscr", 1507 "spe_acc", "spefscr", 1508 "sfp" 1509 }; 1510 1511 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1512 return llvm::makeArrayRef(GCCRegNames); 1513 } 1514 1515 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1516 // While some of these aliases do map to different registers 1517 // they still share the same register name. 1518 { { "0" }, "r0" }, 1519 { { "1"}, "r1" }, 1520 { { "2" }, "r2" }, 1521 { { "3" }, "r3" }, 1522 { { "4" }, "r4" }, 1523 { { "5" }, "r5" }, 1524 { { "6" }, "r6" }, 1525 { { "7" }, "r7" }, 1526 { { "8" }, "r8" }, 1527 { { "9" }, "r9" }, 1528 { { "10" }, "r10" }, 1529 { { "11" }, "r11" }, 1530 { { "12" }, "r12" }, 1531 { { "13" }, "r13" }, 1532 { { "14" }, "r14" }, 1533 { { "15" }, "r15" }, 1534 { { "16" }, "r16" }, 1535 { { "17" }, "r17" }, 1536 { { "18" }, "r18" }, 1537 { { "19" }, "r19" }, 1538 { { "20" }, "r20" }, 1539 { { "21" }, "r21" }, 1540 { { "22" }, "r22" }, 1541 { { "23" }, "r23" }, 1542 { { "24" }, "r24" }, 1543 { { "25" }, "r25" }, 1544 { { "26" }, "r26" }, 1545 { { "27" }, "r27" }, 1546 { { "28" }, "r28" }, 1547 { { "29" }, "r29" }, 1548 { { "30" }, "r30" }, 1549 { { "31" }, "r31" }, 1550 { { "fr0" }, "f0" }, 1551 { { "fr1" }, "f1" }, 1552 { { "fr2" }, "f2" }, 1553 { { "fr3" }, "f3" }, 1554 { { "fr4" }, "f4" }, 1555 { { "fr5" }, "f5" }, 1556 { { "fr6" }, "f6" }, 1557 { { "fr7" }, "f7" }, 1558 { { "fr8" }, "f8" }, 1559 { { "fr9" }, "f9" }, 1560 { { "fr10" }, "f10" }, 1561 { { "fr11" }, "f11" }, 1562 { { "fr12" }, "f12" }, 1563 { { "fr13" }, "f13" }, 1564 { { "fr14" }, "f14" }, 1565 { { "fr15" }, "f15" }, 1566 { { "fr16" }, "f16" }, 1567 { { "fr17" }, "f17" }, 1568 { { "fr18" }, "f18" }, 1569 { { "fr19" }, "f19" }, 1570 { { "fr20" }, "f20" }, 1571 { { "fr21" }, "f21" }, 1572 { { "fr22" }, "f22" }, 1573 { { "fr23" }, "f23" }, 1574 { { "fr24" }, "f24" }, 1575 { { "fr25" }, "f25" }, 1576 { { "fr26" }, "f26" }, 1577 { { "fr27" }, "f27" }, 1578 { { "fr28" }, "f28" }, 1579 { { "fr29" }, "f29" }, 1580 { { "fr30" }, "f30" }, 1581 { { "fr31" }, "f31" }, 1582 { { "cc" }, "cr0" }, 1583 }; 1584 1585 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1586 return llvm::makeArrayRef(GCCRegAliases); 1587 } 1588 1589 class PPC32TargetInfo : public PPCTargetInfo { 1590 public: 1591 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1592 : PPCTargetInfo(Triple, Opts) { 1593 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1594 1595 switch (getTriple().getOS()) { 1596 case llvm::Triple::Linux: 1597 case llvm::Triple::FreeBSD: 1598 case llvm::Triple::NetBSD: 1599 SizeType = UnsignedInt; 1600 PtrDiffType = SignedInt; 1601 IntPtrType = SignedInt; 1602 break; 1603 default: 1604 break; 1605 } 1606 1607 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1608 LongDoubleWidth = LongDoubleAlign = 64; 1609 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1610 } 1611 1612 // PPC32 supports atomics up to 4 bytes. 1613 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1614 } 1615 1616 BuiltinVaListKind getBuiltinVaListKind() const override { 1617 // This is the ELF definition, and is overridden by the Darwin sub-target 1618 return TargetInfo::PowerABIBuiltinVaList; 1619 } 1620 }; 1621 1622 // Note: ABI differences may eventually require us to have a separate 1623 // TargetInfo for little endian. 1624 class PPC64TargetInfo : public PPCTargetInfo { 1625 public: 1626 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1627 : PPCTargetInfo(Triple, Opts) { 1628 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1629 IntMaxType = SignedLong; 1630 Int64Type = SignedLong; 1631 1632 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1633 resetDataLayout("e-m:e-i64:64-n32:64"); 1634 ABI = "elfv2"; 1635 } else { 1636 resetDataLayout("E-m:e-i64:64-n32:64"); 1637 ABI = "elfv1"; 1638 } 1639 1640 switch (getTriple().getOS()) { 1641 case llvm::Triple::FreeBSD: 1642 LongDoubleWidth = LongDoubleAlign = 64; 1643 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1644 break; 1645 case llvm::Triple::NetBSD: 1646 IntMaxType = SignedLongLong; 1647 Int64Type = SignedLongLong; 1648 break; 1649 default: 1650 break; 1651 } 1652 1653 // PPC64 supports atomics up to 8 bytes. 1654 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1655 } 1656 BuiltinVaListKind getBuiltinVaListKind() const override { 1657 return TargetInfo::CharPtrBuiltinVaList; 1658 } 1659 // PPC64 Linux-specific ABI options. 1660 bool setABI(const std::string &Name) override { 1661 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1662 ABI = Name; 1663 return true; 1664 } 1665 return false; 1666 } 1667 }; 1668 1669 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1670 public: 1671 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1672 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1673 HasAlignMac68kSupport = true; 1674 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1675 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1676 LongLongAlign = 32; 1677 SuitableAlign = 128; 1678 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1679 } 1680 BuiltinVaListKind getBuiltinVaListKind() const override { 1681 return TargetInfo::CharPtrBuiltinVaList; 1682 } 1683 }; 1684 1685 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1686 public: 1687 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1688 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1689 HasAlignMac68kSupport = true; 1690 SuitableAlign = 128; 1691 resetDataLayout("E-m:o-i64:64-n32:64"); 1692 } 1693 }; 1694 1695 static const unsigned NVPTXAddrSpaceMap[] = { 1696 1, // opencl_global 1697 3, // opencl_local 1698 4, // opencl_constant 1699 // FIXME: generic has to be added to the target 1700 0, // opencl_generic 1701 1, // cuda_device 1702 4, // cuda_constant 1703 3, // cuda_shared 1704 }; 1705 1706 class NVPTXTargetInfo : public TargetInfo { 1707 static const char *const GCCRegNames[]; 1708 static const Builtin::Info BuiltinInfo[]; 1709 CudaArch GPU; 1710 1711 public: 1712 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1713 : TargetInfo(Triple) { 1714 BigEndian = false; 1715 TLSSupported = false; 1716 LongWidth = LongAlign = 64; 1717 AddrSpaceMap = &NVPTXAddrSpaceMap; 1718 UseAddrSpaceMapMangling = true; 1719 // Define available target features 1720 // These must be defined in sorted order! 1721 NoAsmVariants = true; 1722 GPU = CudaArch::SM_20; 1723 1724 // If possible, get a TargetInfo for our host triple, so we can match its 1725 // types. 1726 llvm::Triple HostTriple(Opts.HostTriple); 1727 if (HostTriple.isNVPTX()) 1728 return; 1729 std::unique_ptr<TargetInfo> HostTarget( 1730 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1731 if (!HostTarget) { 1732 return; 1733 } 1734 1735 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1736 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1737 BoolWidth = HostTarget->getBoolWidth(); 1738 BoolAlign = HostTarget->getBoolAlign(); 1739 IntWidth = HostTarget->getIntWidth(); 1740 IntAlign = HostTarget->getIntAlign(); 1741 HalfWidth = HostTarget->getHalfWidth(); 1742 HalfAlign = HostTarget->getHalfAlign(); 1743 FloatWidth = HostTarget->getFloatWidth(); 1744 FloatAlign = HostTarget->getFloatAlign(); 1745 DoubleWidth = HostTarget->getDoubleWidth(); 1746 DoubleAlign = HostTarget->getDoubleAlign(); 1747 LongWidth = HostTarget->getLongWidth(); 1748 LongAlign = HostTarget->getLongAlign(); 1749 LongLongWidth = HostTarget->getLongLongWidth(); 1750 LongLongAlign = HostTarget->getLongLongAlign(); 1751 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1752 DefaultAlignForAttributeAligned = 1753 HostTarget->getDefaultAlignForAttributeAligned(); 1754 SizeType = HostTarget->getSizeType(); 1755 IntMaxType = HostTarget->getIntMaxType(); 1756 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1757 IntPtrType = HostTarget->getIntPtrType(); 1758 WCharType = HostTarget->getWCharType(); 1759 WIntType = HostTarget->getWIntType(); 1760 Char16Type = HostTarget->getChar16Type(); 1761 Char32Type = HostTarget->getChar32Type(); 1762 Int64Type = HostTarget->getInt64Type(); 1763 SigAtomicType = HostTarget->getSigAtomicType(); 1764 ProcessIDType = HostTarget->getProcessIDType(); 1765 1766 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1767 UseZeroLengthBitfieldAlignment = 1768 HostTarget->useZeroLengthBitfieldAlignment(); 1769 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1770 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1771 1772 // Properties intentionally not copied from host: 1773 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1774 // host/device boundary. 1775 // - SuitableAlign: Not visible across the host/device boundary, and may 1776 // correctly be different on host/device, e.g. if host has wider vector 1777 // types than device. 1778 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1779 // as its double type, but that's not necessarily true on the host. 1780 // TODO: nvcc emits a warning when using long double on device; we should 1781 // do the same. 1782 } 1783 void getTargetDefines(const LangOptions &Opts, 1784 MacroBuilder &Builder) const override { 1785 Builder.defineMacro("__PTX__"); 1786 Builder.defineMacro("__NVPTX__"); 1787 if (Opts.CUDAIsDevice) { 1788 // Set __CUDA_ARCH__ for the GPU specified. 1789 std::string CUDAArchCode = [this] { 1790 switch (GPU) { 1791 case CudaArch::UNKNOWN: 1792 assert(false && "No GPU arch when compiling CUDA device code."); 1793 return ""; 1794 case CudaArch::SM_20: 1795 return "200"; 1796 case CudaArch::SM_21: 1797 return "210"; 1798 case CudaArch::SM_30: 1799 return "300"; 1800 case CudaArch::SM_32: 1801 return "320"; 1802 case CudaArch::SM_35: 1803 return "350"; 1804 case CudaArch::SM_37: 1805 return "370"; 1806 case CudaArch::SM_50: 1807 return "500"; 1808 case CudaArch::SM_52: 1809 return "520"; 1810 case CudaArch::SM_53: 1811 return "530"; 1812 case CudaArch::SM_60: 1813 return "600"; 1814 case CudaArch::SM_61: 1815 return "610"; 1816 case CudaArch::SM_62: 1817 return "620"; 1818 } 1819 llvm_unreachable("unhandled CudaArch"); 1820 }(); 1821 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1822 } 1823 } 1824 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1825 return llvm::makeArrayRef(BuiltinInfo, 1826 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1827 } 1828 bool hasFeature(StringRef Feature) const override { 1829 return Feature == "ptx" || Feature == "nvptx"; 1830 } 1831 1832 ArrayRef<const char *> getGCCRegNames() const override; 1833 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1834 // No aliases. 1835 return None; 1836 } 1837 bool validateAsmConstraint(const char *&Name, 1838 TargetInfo::ConstraintInfo &Info) const override { 1839 switch (*Name) { 1840 default: 1841 return false; 1842 case 'c': 1843 case 'h': 1844 case 'r': 1845 case 'l': 1846 case 'f': 1847 case 'd': 1848 Info.setAllowsRegister(); 1849 return true; 1850 } 1851 } 1852 const char *getClobbers() const override { 1853 // FIXME: Is this really right? 1854 return ""; 1855 } 1856 BuiltinVaListKind getBuiltinVaListKind() const override { 1857 // FIXME: implement 1858 return TargetInfo::CharPtrBuiltinVaList; 1859 } 1860 bool setCPU(const std::string &Name) override { 1861 GPU = StringToCudaArch(Name); 1862 return GPU != CudaArch::UNKNOWN; 1863 } 1864 void setSupportedOpenCLOpts() override { 1865 auto &Opts = getSupportedOpenCLOpts(); 1866 Opts.cl_clang_storage_class_specifiers = 1; 1867 Opts.cl_khr_gl_sharing = 1; 1868 Opts.cl_khr_icd = 1; 1869 1870 Opts.cl_khr_fp64 = 1; 1871 Opts.cl_khr_byte_addressable_store = 1; 1872 Opts.cl_khr_global_int32_base_atomics = 1; 1873 Opts.cl_khr_global_int32_extended_atomics = 1; 1874 Opts.cl_khr_local_int32_base_atomics = 1; 1875 Opts.cl_khr_local_int32_extended_atomics = 1; 1876 } 1877 }; 1878 1879 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1880 #define BUILTIN(ID, TYPE, ATTRS) \ 1881 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1882 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1883 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1884 #include "clang/Basic/BuiltinsNVPTX.def" 1885 }; 1886 1887 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1888 1889 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1890 return llvm::makeArrayRef(GCCRegNames); 1891 } 1892 1893 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1894 public: 1895 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1896 : NVPTXTargetInfo(Triple, Opts) { 1897 LongWidth = LongAlign = 32; 1898 PointerWidth = PointerAlign = 32; 1899 SizeType = TargetInfo::UnsignedInt; 1900 PtrDiffType = TargetInfo::SignedInt; 1901 IntPtrType = TargetInfo::SignedInt; 1902 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1903 } 1904 }; 1905 1906 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1907 public: 1908 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1909 : NVPTXTargetInfo(Triple, Opts) { 1910 PointerWidth = PointerAlign = 64; 1911 SizeType = TargetInfo::UnsignedLong; 1912 PtrDiffType = TargetInfo::SignedLong; 1913 IntPtrType = TargetInfo::SignedLong; 1914 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1915 } 1916 }; 1917 1918 static const unsigned AMDGPUAddrSpaceMap[] = { 1919 1, // opencl_global 1920 3, // opencl_local 1921 2, // opencl_constant 1922 4, // opencl_generic 1923 1, // cuda_device 1924 2, // cuda_constant 1925 3 // cuda_shared 1926 }; 1927 1928 // If you edit the description strings, make sure you update 1929 // getPointerWidthV(). 1930 1931 static const char *const DataLayoutStringR600 = 1932 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1933 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1934 1935 static const char *const DataLayoutStringSI = 1936 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 1937 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1938 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1939 1940 class AMDGPUTargetInfo final : public TargetInfo { 1941 static const Builtin::Info BuiltinInfo[]; 1942 static const char * const GCCRegNames[]; 1943 1944 /// \brief The GPU profiles supported by the AMDGPU target. 1945 enum GPUKind { 1946 GK_NONE, 1947 GK_R600, 1948 GK_R600_DOUBLE_OPS, 1949 GK_R700, 1950 GK_R700_DOUBLE_OPS, 1951 GK_EVERGREEN, 1952 GK_EVERGREEN_DOUBLE_OPS, 1953 GK_NORTHERN_ISLANDS, 1954 GK_CAYMAN, 1955 GK_SOUTHERN_ISLANDS, 1956 GK_SEA_ISLANDS, 1957 GK_VOLCANIC_ISLANDS 1958 } GPU; 1959 1960 bool hasFP64:1; 1961 bool hasFMAF:1; 1962 bool hasLDEXPF:1; 1963 1964 static bool isAMDGCN(const llvm::Triple &TT) { 1965 return TT.getArch() == llvm::Triple::amdgcn; 1966 } 1967 1968 public: 1969 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 1970 : TargetInfo(Triple) , 1971 GPU(isAMDGCN(Triple) ? GK_SOUTHERN_ISLANDS : GK_R600), 1972 hasFP64(false), 1973 hasFMAF(false), 1974 hasLDEXPF(false) { 1975 if (getTriple().getArch() == llvm::Triple::amdgcn) { 1976 hasFP64 = true; 1977 hasFMAF = true; 1978 hasLDEXPF = true; 1979 } 1980 1981 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 1982 DataLayoutStringSI : DataLayoutStringR600); 1983 1984 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1985 UseAddrSpaceMapMangling = true; 1986 } 1987 1988 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1989 if (GPU <= GK_CAYMAN) 1990 return 32; 1991 1992 switch(AddrSpace) { 1993 default: 1994 return 64; 1995 case 0: 1996 case 3: 1997 case 5: 1998 return 32; 1999 } 2000 } 2001 2002 const char * getClobbers() const override { 2003 return ""; 2004 } 2005 2006 ArrayRef<const char *> getGCCRegNames() const override; 2007 2008 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2009 return None; 2010 } 2011 2012 bool validateAsmConstraint(const char *&Name, 2013 TargetInfo::ConstraintInfo &Info) const override { 2014 switch (*Name) { 2015 default: break; 2016 case 'v': // vgpr 2017 case 's': // sgpr 2018 Info.setAllowsRegister(); 2019 return true; 2020 } 2021 return false; 2022 } 2023 2024 bool initFeatureMap(llvm::StringMap<bool> &Features, 2025 DiagnosticsEngine &Diags, StringRef CPU, 2026 const std::vector<std::string> &FeatureVec) const override; 2027 2028 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2029 return llvm::makeArrayRef(BuiltinInfo, 2030 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2031 } 2032 2033 void getTargetDefines(const LangOptions &Opts, 2034 MacroBuilder &Builder) const override { 2035 if (getTriple().getArch() == llvm::Triple::amdgcn) 2036 Builder.defineMacro("__AMDGCN__"); 2037 else 2038 Builder.defineMacro("__R600__"); 2039 2040 if (hasFMAF) 2041 Builder.defineMacro("__HAS_FMAF__"); 2042 if (hasLDEXPF) 2043 Builder.defineMacro("__HAS_LDEXPF__"); 2044 if (hasFP64) 2045 Builder.defineMacro("__HAS_FP64__"); 2046 } 2047 2048 BuiltinVaListKind getBuiltinVaListKind() const override { 2049 return TargetInfo::CharPtrBuiltinVaList; 2050 } 2051 2052 static GPUKind parseR600Name(StringRef Name) { 2053 return llvm::StringSwitch<GPUKind>(Name) 2054 .Case("r600" , GK_R600) 2055 .Case("rv610", GK_R600) 2056 .Case("rv620", GK_R600) 2057 .Case("rv630", GK_R600) 2058 .Case("rv635", GK_R600) 2059 .Case("rs780", GK_R600) 2060 .Case("rs880", GK_R600) 2061 .Case("rv670", GK_R600_DOUBLE_OPS) 2062 .Case("rv710", GK_R700) 2063 .Case("rv730", GK_R700) 2064 .Case("rv740", GK_R700_DOUBLE_OPS) 2065 .Case("rv770", GK_R700_DOUBLE_OPS) 2066 .Case("palm", GK_EVERGREEN) 2067 .Case("cedar", GK_EVERGREEN) 2068 .Case("sumo", GK_EVERGREEN) 2069 .Case("sumo2", GK_EVERGREEN) 2070 .Case("redwood", GK_EVERGREEN) 2071 .Case("juniper", GK_EVERGREEN) 2072 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2073 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2074 .Case("barts", GK_NORTHERN_ISLANDS) 2075 .Case("turks", GK_NORTHERN_ISLANDS) 2076 .Case("caicos", GK_NORTHERN_ISLANDS) 2077 .Case("cayman", GK_CAYMAN) 2078 .Case("aruba", GK_CAYMAN) 2079 .Default(GK_NONE); 2080 } 2081 2082 static GPUKind parseAMDGCNName(StringRef Name) { 2083 return llvm::StringSwitch<GPUKind>(Name) 2084 .Case("tahiti", GK_SOUTHERN_ISLANDS) 2085 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 2086 .Case("verde", GK_SOUTHERN_ISLANDS) 2087 .Case("oland", GK_SOUTHERN_ISLANDS) 2088 .Case("hainan", GK_SOUTHERN_ISLANDS) 2089 .Case("bonaire", GK_SEA_ISLANDS) 2090 .Case("kabini", GK_SEA_ISLANDS) 2091 .Case("kaveri", GK_SEA_ISLANDS) 2092 .Case("hawaii", GK_SEA_ISLANDS) 2093 .Case("mullins", GK_SEA_ISLANDS) 2094 .Case("tonga", GK_VOLCANIC_ISLANDS) 2095 .Case("iceland", GK_VOLCANIC_ISLANDS) 2096 .Case("carrizo", GK_VOLCANIC_ISLANDS) 2097 .Case("fiji", GK_VOLCANIC_ISLANDS) 2098 .Case("stoney", GK_VOLCANIC_ISLANDS) 2099 .Default(GK_NONE); 2100 } 2101 2102 bool setCPU(const std::string &Name) override { 2103 if (getTriple().getArch() == llvm::Triple::amdgcn) 2104 GPU = parseAMDGCNName(Name); 2105 else 2106 GPU = parseR600Name(Name); 2107 2108 return GPU != GK_NONE; 2109 } 2110 2111 void setSupportedOpenCLOpts() override { 2112 auto &Opts = getSupportedOpenCLOpts(); 2113 Opts.cl_clang_storage_class_specifiers = 1; 2114 Opts.cl_khr_icd = 1; 2115 2116 if (hasFP64) 2117 Opts.cl_khr_fp64 = 1; 2118 if (GPU >= GK_EVERGREEN) { 2119 Opts.cl_khr_byte_addressable_store = 1; 2120 Opts.cl_khr_global_int32_base_atomics = 1; 2121 Opts.cl_khr_global_int32_extended_atomics = 1; 2122 Opts.cl_khr_local_int32_base_atomics = 1; 2123 Opts.cl_khr_local_int32_extended_atomics = 1; 2124 } 2125 if (GPU >= GK_SOUTHERN_ISLANDS) { 2126 Opts.cl_khr_fp16 = 1; 2127 Opts.cl_khr_int64_base_atomics = 1; 2128 Opts.cl_khr_int64_extended_atomics = 1; 2129 Opts.cl_khr_mipmap_image = 1; 2130 Opts.cl_khr_3d_image_writes = 1; 2131 } 2132 } 2133 2134 LangAS::ID getOpenCLImageAddrSpace() const override { 2135 return LangAS::opencl_constant; 2136 } 2137 2138 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2139 switch (CC) { 2140 default: 2141 return CCCR_Warning; 2142 case CC_C: 2143 case CC_OpenCLKernel: 2144 return CCCR_OK; 2145 } 2146 } 2147 }; 2148 2149 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2150 #define BUILTIN(ID, TYPE, ATTRS) \ 2151 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2152 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2153 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2154 #include "clang/Basic/BuiltinsAMDGPU.def" 2155 }; 2156 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2157 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2158 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2159 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2160 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2161 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2162 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2163 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2164 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2165 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2166 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2167 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2168 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2169 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2170 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2171 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2172 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2173 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2174 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2175 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2176 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2177 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2178 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2179 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2180 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2181 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2182 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2183 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2184 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2185 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2186 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2187 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2188 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2189 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2190 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2191 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2192 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2193 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2194 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2195 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2196 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2197 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2198 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2199 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2200 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2201 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2202 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2203 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2204 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2205 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2206 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2207 }; 2208 2209 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2210 return llvm::makeArrayRef(GCCRegNames); 2211 } 2212 2213 bool AMDGPUTargetInfo::initFeatureMap( 2214 llvm::StringMap<bool> &Features, 2215 DiagnosticsEngine &Diags, StringRef CPU, 2216 const std::vector<std::string> &FeatureVec) const { 2217 2218 // XXX - What does the member GPU mean if device name string passed here? 2219 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2220 if (CPU.empty()) 2221 CPU = "tahiti"; 2222 2223 switch (parseAMDGCNName(CPU)) { 2224 case GK_SOUTHERN_ISLANDS: 2225 case GK_SEA_ISLANDS: 2226 break; 2227 2228 case GK_VOLCANIC_ISLANDS: 2229 Features["s-memrealtime"] = true; 2230 Features["16-bit-insts"] = true; 2231 break; 2232 2233 case GK_NONE: 2234 return false; 2235 default: 2236 llvm_unreachable("unhandled subtarget"); 2237 } 2238 } else { 2239 if (CPU.empty()) 2240 CPU = "r600"; 2241 2242 switch (parseR600Name(CPU)) { 2243 case GK_R600: 2244 case GK_R700: 2245 case GK_EVERGREEN: 2246 case GK_NORTHERN_ISLANDS: 2247 break; 2248 case GK_R600_DOUBLE_OPS: 2249 case GK_R700_DOUBLE_OPS: 2250 case GK_EVERGREEN_DOUBLE_OPS: 2251 case GK_CAYMAN: 2252 Features["fp64"] = true; 2253 break; 2254 case GK_NONE: 2255 return false; 2256 default: 2257 llvm_unreachable("unhandled subtarget"); 2258 } 2259 } 2260 2261 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2262 } 2263 2264 // Namespace for x86 abstract base class 2265 const Builtin::Info BuiltinInfo[] = { 2266 #define BUILTIN(ID, TYPE, ATTRS) \ 2267 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2268 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2269 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2270 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2271 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2272 #include "clang/Basic/BuiltinsX86.def" 2273 }; 2274 2275 static const char* const GCCRegNames[] = { 2276 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2277 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2278 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2279 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2280 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2281 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2282 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2283 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2284 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2285 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2286 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2287 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2288 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2289 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2290 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2291 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2292 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2293 }; 2294 2295 const TargetInfo::AddlRegName AddlRegNames[] = { 2296 { { "al", "ah", "eax", "rax" }, 0 }, 2297 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2298 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2299 { { "dl", "dh", "edx", "rdx" }, 1 }, 2300 { { "esi", "rsi" }, 4 }, 2301 { { "edi", "rdi" }, 5 }, 2302 { { "esp", "rsp" }, 7 }, 2303 { { "ebp", "rbp" }, 6 }, 2304 { { "r8d", "r8w", "r8b" }, 38 }, 2305 { { "r9d", "r9w", "r9b" }, 39 }, 2306 { { "r10d", "r10w", "r10b" }, 40 }, 2307 { { "r11d", "r11w", "r11b" }, 41 }, 2308 { { "r12d", "r12w", "r12b" }, 42 }, 2309 { { "r13d", "r13w", "r13b" }, 43 }, 2310 { { "r14d", "r14w", "r14b" }, 44 }, 2311 { { "r15d", "r15w", "r15b" }, 45 }, 2312 }; 2313 2314 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2315 // most of the implementation can be shared. 2316 class X86TargetInfo : public TargetInfo { 2317 enum X86SSEEnum { 2318 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2319 } SSELevel = NoSSE; 2320 enum MMX3DNowEnum { 2321 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2322 } MMX3DNowLevel = NoMMX3DNow; 2323 enum XOPEnum { 2324 NoXOP, 2325 SSE4A, 2326 FMA4, 2327 XOP 2328 } XOPLevel = NoXOP; 2329 2330 bool HasAES = false; 2331 bool HasPCLMUL = false; 2332 bool HasLZCNT = false; 2333 bool HasRDRND = false; 2334 bool HasFSGSBASE = false; 2335 bool HasBMI = false; 2336 bool HasBMI2 = false; 2337 bool HasPOPCNT = false; 2338 bool HasRTM = false; 2339 bool HasPRFCHW = false; 2340 bool HasRDSEED = false; 2341 bool HasADX = false; 2342 bool HasTBM = false; 2343 bool HasFMA = false; 2344 bool HasF16C = false; 2345 bool HasAVX512CD = false; 2346 bool HasAVX512ER = false; 2347 bool HasAVX512PF = false; 2348 bool HasAVX512DQ = false; 2349 bool HasAVX512BW = false; 2350 bool HasAVX512VL = false; 2351 bool HasAVX512VBMI = false; 2352 bool HasAVX512IFMA = false; 2353 bool HasSHA = false; 2354 bool HasMPX = false; 2355 bool HasSGX = false; 2356 bool HasCX16 = false; 2357 bool HasFXSR = false; 2358 bool HasXSAVE = false; 2359 bool HasXSAVEOPT = false; 2360 bool HasXSAVEC = false; 2361 bool HasXSAVES = false; 2362 bool HasMWAITX = false; 2363 bool HasPKU = false; 2364 bool HasCLFLUSHOPT = false; 2365 bool HasPCOMMIT = false; 2366 bool HasCLWB = false; 2367 bool HasUMIP = false; 2368 bool HasMOVBE = false; 2369 bool HasPREFETCHWT1 = false; 2370 2371 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2372 /// 2373 /// Each enumeration represents a particular CPU supported by Clang. These 2374 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2375 enum CPUKind { 2376 CK_Generic, 2377 2378 /// \name i386 2379 /// i386-generation processors. 2380 //@{ 2381 CK_i386, 2382 //@} 2383 2384 /// \name i486 2385 /// i486-generation processors. 2386 //@{ 2387 CK_i486, 2388 CK_WinChipC6, 2389 CK_WinChip2, 2390 CK_C3, 2391 //@} 2392 2393 /// \name i586 2394 /// i586-generation processors, P5 microarchitecture based. 2395 //@{ 2396 CK_i586, 2397 CK_Pentium, 2398 CK_PentiumMMX, 2399 //@} 2400 2401 /// \name i686 2402 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2403 //@{ 2404 CK_i686, 2405 CK_PentiumPro, 2406 CK_Pentium2, 2407 CK_Pentium3, 2408 CK_Pentium3M, 2409 CK_PentiumM, 2410 CK_C3_2, 2411 2412 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2413 /// Clang however has some logic to suport this. 2414 // FIXME: Warn, deprecate, and potentially remove this. 2415 CK_Yonah, 2416 //@} 2417 2418 /// \name Netburst 2419 /// Netburst microarchitecture based processors. 2420 //@{ 2421 CK_Pentium4, 2422 CK_Pentium4M, 2423 CK_Prescott, 2424 CK_Nocona, 2425 //@} 2426 2427 /// \name Core 2428 /// Core microarchitecture based processors. 2429 //@{ 2430 CK_Core2, 2431 2432 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2433 /// codename which GCC no longer accepts as an option to -march, but Clang 2434 /// has some logic for recognizing it. 2435 // FIXME: Warn, deprecate, and potentially remove this. 2436 CK_Penryn, 2437 //@} 2438 2439 /// \name Atom 2440 /// Atom processors 2441 //@{ 2442 CK_Bonnell, 2443 CK_Silvermont, 2444 //@} 2445 2446 /// \name Nehalem 2447 /// Nehalem microarchitecture based processors. 2448 CK_Nehalem, 2449 2450 /// \name Westmere 2451 /// Westmere microarchitecture based processors. 2452 CK_Westmere, 2453 2454 /// \name Sandy Bridge 2455 /// Sandy Bridge microarchitecture based processors. 2456 CK_SandyBridge, 2457 2458 /// \name Ivy Bridge 2459 /// Ivy Bridge microarchitecture based processors. 2460 CK_IvyBridge, 2461 2462 /// \name Haswell 2463 /// Haswell microarchitecture based processors. 2464 CK_Haswell, 2465 2466 /// \name Broadwell 2467 /// Broadwell microarchitecture based processors. 2468 CK_Broadwell, 2469 2470 /// \name Skylake Client 2471 /// Skylake client microarchitecture based processors. 2472 CK_SkylakeClient, 2473 2474 /// \name Skylake Server 2475 /// Skylake server microarchitecture based processors. 2476 CK_SkylakeServer, 2477 2478 /// \name Cannonlake Client 2479 /// Cannonlake client microarchitecture based processors. 2480 CK_Cannonlake, 2481 2482 /// \name Knights Landing 2483 /// Knights Landing processor. 2484 CK_KNL, 2485 2486 /// \name Lakemont 2487 /// Lakemont microarchitecture based processors. 2488 CK_Lakemont, 2489 2490 /// \name K6 2491 /// K6 architecture processors. 2492 //@{ 2493 CK_K6, 2494 CK_K6_2, 2495 CK_K6_3, 2496 //@} 2497 2498 /// \name K7 2499 /// K7 architecture processors. 2500 //@{ 2501 CK_Athlon, 2502 CK_AthlonThunderbird, 2503 CK_Athlon4, 2504 CK_AthlonXP, 2505 CK_AthlonMP, 2506 //@} 2507 2508 /// \name K8 2509 /// K8 architecture processors. 2510 //@{ 2511 CK_Athlon64, 2512 CK_Athlon64SSE3, 2513 CK_AthlonFX, 2514 CK_K8, 2515 CK_K8SSE3, 2516 CK_Opteron, 2517 CK_OpteronSSE3, 2518 CK_AMDFAM10, 2519 //@} 2520 2521 /// \name Bobcat 2522 /// Bobcat architecture processors. 2523 //@{ 2524 CK_BTVER1, 2525 CK_BTVER2, 2526 //@} 2527 2528 /// \name Bulldozer 2529 /// Bulldozer architecture processors. 2530 //@{ 2531 CK_BDVER1, 2532 CK_BDVER2, 2533 CK_BDVER3, 2534 CK_BDVER4, 2535 //@} 2536 2537 /// This specification is deprecated and will be removed in the future. 2538 /// Users should prefer \see CK_K8. 2539 // FIXME: Warn on this when the CPU is set to it. 2540 //@{ 2541 CK_x86_64, 2542 //@} 2543 2544 /// \name Geode 2545 /// Geode processors. 2546 //@{ 2547 CK_Geode 2548 //@} 2549 } CPU = CK_Generic; 2550 2551 CPUKind getCPUKind(StringRef CPU) const { 2552 return llvm::StringSwitch<CPUKind>(CPU) 2553 .Case("i386", CK_i386) 2554 .Case("i486", CK_i486) 2555 .Case("winchip-c6", CK_WinChipC6) 2556 .Case("winchip2", CK_WinChip2) 2557 .Case("c3", CK_C3) 2558 .Case("i586", CK_i586) 2559 .Case("pentium", CK_Pentium) 2560 .Case("pentium-mmx", CK_PentiumMMX) 2561 .Case("i686", CK_i686) 2562 .Case("pentiumpro", CK_PentiumPro) 2563 .Case("pentium2", CK_Pentium2) 2564 .Case("pentium3", CK_Pentium3) 2565 .Case("pentium3m", CK_Pentium3M) 2566 .Case("pentium-m", CK_PentiumM) 2567 .Case("c3-2", CK_C3_2) 2568 .Case("yonah", CK_Yonah) 2569 .Case("pentium4", CK_Pentium4) 2570 .Case("pentium4m", CK_Pentium4M) 2571 .Case("prescott", CK_Prescott) 2572 .Case("nocona", CK_Nocona) 2573 .Case("core2", CK_Core2) 2574 .Case("penryn", CK_Penryn) 2575 .Case("bonnell", CK_Bonnell) 2576 .Case("atom", CK_Bonnell) // Legacy name. 2577 .Case("silvermont", CK_Silvermont) 2578 .Case("slm", CK_Silvermont) // Legacy name. 2579 .Case("nehalem", CK_Nehalem) 2580 .Case("corei7", CK_Nehalem) // Legacy name. 2581 .Case("westmere", CK_Westmere) 2582 .Case("sandybridge", CK_SandyBridge) 2583 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2584 .Case("ivybridge", CK_IvyBridge) 2585 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2586 .Case("haswell", CK_Haswell) 2587 .Case("core-avx2", CK_Haswell) // Legacy name. 2588 .Case("broadwell", CK_Broadwell) 2589 .Case("skylake", CK_SkylakeClient) 2590 .Case("skylake-avx512", CK_SkylakeServer) 2591 .Case("skx", CK_SkylakeServer) // Legacy name. 2592 .Case("cannonlake", CK_Cannonlake) 2593 .Case("knl", CK_KNL) 2594 .Case("lakemont", CK_Lakemont) 2595 .Case("k6", CK_K6) 2596 .Case("k6-2", CK_K6_2) 2597 .Case("k6-3", CK_K6_3) 2598 .Case("athlon", CK_Athlon) 2599 .Case("athlon-tbird", CK_AthlonThunderbird) 2600 .Case("athlon-4", CK_Athlon4) 2601 .Case("athlon-xp", CK_AthlonXP) 2602 .Case("athlon-mp", CK_AthlonMP) 2603 .Case("athlon64", CK_Athlon64) 2604 .Case("athlon64-sse3", CK_Athlon64SSE3) 2605 .Case("athlon-fx", CK_AthlonFX) 2606 .Case("k8", CK_K8) 2607 .Case("k8-sse3", CK_K8SSE3) 2608 .Case("opteron", CK_Opteron) 2609 .Case("opteron-sse3", CK_OpteronSSE3) 2610 .Case("barcelona", CK_AMDFAM10) 2611 .Case("amdfam10", CK_AMDFAM10) 2612 .Case("btver1", CK_BTVER1) 2613 .Case("btver2", CK_BTVER2) 2614 .Case("bdver1", CK_BDVER1) 2615 .Case("bdver2", CK_BDVER2) 2616 .Case("bdver3", CK_BDVER3) 2617 .Case("bdver4", CK_BDVER4) 2618 .Case("x86-64", CK_x86_64) 2619 .Case("geode", CK_Geode) 2620 .Default(CK_Generic); 2621 } 2622 2623 enum FPMathKind { 2624 FP_Default, 2625 FP_SSE, 2626 FP_387 2627 } FPMath = FP_Default; 2628 2629 public: 2630 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2631 : TargetInfo(Triple) { 2632 BigEndian = false; 2633 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2634 } 2635 unsigned getFloatEvalMethod() const override { 2636 // X87 evaluates with 80 bits "long double" precision. 2637 return SSELevel == NoSSE ? 2 : 0; 2638 } 2639 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2640 return llvm::makeArrayRef(BuiltinInfo, 2641 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2642 } 2643 ArrayRef<const char *> getGCCRegNames() const override { 2644 return llvm::makeArrayRef(GCCRegNames); 2645 } 2646 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2647 return None; 2648 } 2649 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2650 return llvm::makeArrayRef(AddlRegNames); 2651 } 2652 bool validateCpuSupports(StringRef Name) const override; 2653 bool validateAsmConstraint(const char *&Name, 2654 TargetInfo::ConstraintInfo &info) const override; 2655 2656 bool validateGlobalRegisterVariable(StringRef RegName, 2657 unsigned RegSize, 2658 bool &HasSizeMismatch) const override { 2659 // esp and ebp are the only 32-bit registers the x86 backend can currently 2660 // handle. 2661 if (RegName.equals("esp") || RegName.equals("ebp")) { 2662 // Check that the register size is 32-bit. 2663 HasSizeMismatch = RegSize != 32; 2664 return true; 2665 } 2666 2667 return false; 2668 } 2669 2670 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2671 2672 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2673 2674 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2675 2676 std::string convertConstraint(const char *&Constraint) const override; 2677 const char *getClobbers() const override { 2678 return "~{dirflag},~{fpsr},~{flags}"; 2679 } 2680 void getTargetDefines(const LangOptions &Opts, 2681 MacroBuilder &Builder) const override; 2682 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2683 bool Enabled); 2684 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2685 bool Enabled); 2686 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2687 bool Enabled); 2688 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2689 StringRef Name, bool Enabled) const override { 2690 setFeatureEnabledImpl(Features, Name, Enabled); 2691 } 2692 // This exists purely to cut down on the number of virtual calls in 2693 // initFeatureMap which calls this repeatedly. 2694 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2695 StringRef Name, bool Enabled); 2696 bool 2697 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2698 StringRef CPU, 2699 const std::vector<std::string> &FeaturesVec) const override; 2700 bool hasFeature(StringRef Feature) const override; 2701 bool handleTargetFeatures(std::vector<std::string> &Features, 2702 DiagnosticsEngine &Diags) override; 2703 StringRef getABI() const override { 2704 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2705 return "avx512"; 2706 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2707 return "avx"; 2708 if (getTriple().getArch() == llvm::Triple::x86 && 2709 MMX3DNowLevel == NoMMX3DNow) 2710 return "no-mmx"; 2711 return ""; 2712 } 2713 bool setCPU(const std::string &Name) override { 2714 CPU = getCPUKind(Name); 2715 2716 // Perform any per-CPU checks necessary to determine if this CPU is 2717 // acceptable. 2718 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2719 // invalid without explaining *why*. 2720 switch (CPU) { 2721 case CK_Generic: 2722 // No processor selected! 2723 return false; 2724 2725 case CK_i386: 2726 case CK_i486: 2727 case CK_WinChipC6: 2728 case CK_WinChip2: 2729 case CK_C3: 2730 case CK_i586: 2731 case CK_Pentium: 2732 case CK_PentiumMMX: 2733 case CK_i686: 2734 case CK_PentiumPro: 2735 case CK_Pentium2: 2736 case CK_Pentium3: 2737 case CK_Pentium3M: 2738 case CK_PentiumM: 2739 case CK_Yonah: 2740 case CK_C3_2: 2741 case CK_Pentium4: 2742 case CK_Pentium4M: 2743 case CK_Lakemont: 2744 case CK_Prescott: 2745 case CK_K6: 2746 case CK_K6_2: 2747 case CK_K6_3: 2748 case CK_Athlon: 2749 case CK_AthlonThunderbird: 2750 case CK_Athlon4: 2751 case CK_AthlonXP: 2752 case CK_AthlonMP: 2753 case CK_Geode: 2754 // Only accept certain architectures when compiling in 32-bit mode. 2755 if (getTriple().getArch() != llvm::Triple::x86) 2756 return false; 2757 2758 // Fallthrough 2759 case CK_Nocona: 2760 case CK_Core2: 2761 case CK_Penryn: 2762 case CK_Bonnell: 2763 case CK_Silvermont: 2764 case CK_Nehalem: 2765 case CK_Westmere: 2766 case CK_SandyBridge: 2767 case CK_IvyBridge: 2768 case CK_Haswell: 2769 case CK_Broadwell: 2770 case CK_SkylakeClient: 2771 case CK_SkylakeServer: 2772 case CK_Cannonlake: 2773 case CK_KNL: 2774 case CK_Athlon64: 2775 case CK_Athlon64SSE3: 2776 case CK_AthlonFX: 2777 case CK_K8: 2778 case CK_K8SSE3: 2779 case CK_Opteron: 2780 case CK_OpteronSSE3: 2781 case CK_AMDFAM10: 2782 case CK_BTVER1: 2783 case CK_BTVER2: 2784 case CK_BDVER1: 2785 case CK_BDVER2: 2786 case CK_BDVER3: 2787 case CK_BDVER4: 2788 case CK_x86_64: 2789 return true; 2790 } 2791 llvm_unreachable("Unhandled CPU kind"); 2792 } 2793 2794 bool setFPMath(StringRef Name) override; 2795 2796 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2797 // Most of the non-ARM calling conventions are i386 conventions. 2798 switch (CC) { 2799 case CC_X86ThisCall: 2800 case CC_X86FastCall: 2801 case CC_X86StdCall: 2802 case CC_X86VectorCall: 2803 case CC_C: 2804 case CC_Swift: 2805 case CC_X86Pascal: 2806 case CC_IntelOclBicc: 2807 return CCCR_OK; 2808 default: 2809 return CCCR_Warning; 2810 } 2811 } 2812 2813 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2814 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2815 } 2816 2817 bool hasSjLjLowering() const override { 2818 return true; 2819 } 2820 2821 void setSupportedOpenCLOpts() override { 2822 getSupportedOpenCLOpts().setAll(); 2823 } 2824 }; 2825 2826 bool X86TargetInfo::setFPMath(StringRef Name) { 2827 if (Name == "387") { 2828 FPMath = FP_387; 2829 return true; 2830 } 2831 if (Name == "sse") { 2832 FPMath = FP_SSE; 2833 return true; 2834 } 2835 return false; 2836 } 2837 2838 bool X86TargetInfo::initFeatureMap( 2839 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2840 const std::vector<std::string> &FeaturesVec) const { 2841 // FIXME: This *really* should not be here. 2842 // X86_64 always has SSE2. 2843 if (getTriple().getArch() == llvm::Triple::x86_64) 2844 setFeatureEnabledImpl(Features, "sse2", true); 2845 2846 const CPUKind Kind = getCPUKind(CPU); 2847 2848 // Enable X87 for all X86 processors but Lakemont. 2849 if (Kind != CK_Lakemont) 2850 setFeatureEnabledImpl(Features, "x87", true); 2851 2852 switch (Kind) { 2853 case CK_Generic: 2854 case CK_i386: 2855 case CK_i486: 2856 case CK_i586: 2857 case CK_Pentium: 2858 case CK_i686: 2859 case CK_PentiumPro: 2860 case CK_Lakemont: 2861 break; 2862 case CK_PentiumMMX: 2863 case CK_Pentium2: 2864 case CK_K6: 2865 case CK_WinChipC6: 2866 setFeatureEnabledImpl(Features, "mmx", true); 2867 break; 2868 case CK_Pentium3: 2869 case CK_Pentium3M: 2870 case CK_C3_2: 2871 setFeatureEnabledImpl(Features, "sse", true); 2872 setFeatureEnabledImpl(Features, "fxsr", true); 2873 break; 2874 case CK_PentiumM: 2875 case CK_Pentium4: 2876 case CK_Pentium4M: 2877 case CK_x86_64: 2878 setFeatureEnabledImpl(Features, "sse2", true); 2879 setFeatureEnabledImpl(Features, "fxsr", true); 2880 break; 2881 case CK_Yonah: 2882 case CK_Prescott: 2883 case CK_Nocona: 2884 setFeatureEnabledImpl(Features, "sse3", true); 2885 setFeatureEnabledImpl(Features, "fxsr", true); 2886 setFeatureEnabledImpl(Features, "cx16", true); 2887 break; 2888 case CK_Core2: 2889 case CK_Bonnell: 2890 setFeatureEnabledImpl(Features, "ssse3", true); 2891 setFeatureEnabledImpl(Features, "fxsr", true); 2892 setFeatureEnabledImpl(Features, "cx16", true); 2893 break; 2894 case CK_Penryn: 2895 setFeatureEnabledImpl(Features, "sse4.1", true); 2896 setFeatureEnabledImpl(Features, "fxsr", true); 2897 setFeatureEnabledImpl(Features, "cx16", true); 2898 break; 2899 case CK_Cannonlake: 2900 setFeatureEnabledImpl(Features, "avx512ifma", true); 2901 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2902 setFeatureEnabledImpl(Features, "sha", true); 2903 setFeatureEnabledImpl(Features, "umip", true); 2904 // FALLTHROUGH 2905 case CK_SkylakeServer: 2906 setFeatureEnabledImpl(Features, "avx512f", true); 2907 setFeatureEnabledImpl(Features, "avx512cd", true); 2908 setFeatureEnabledImpl(Features, "avx512dq", true); 2909 setFeatureEnabledImpl(Features, "avx512bw", true); 2910 setFeatureEnabledImpl(Features, "avx512vl", true); 2911 setFeatureEnabledImpl(Features, "pku", true); 2912 setFeatureEnabledImpl(Features, "pcommit", true); 2913 setFeatureEnabledImpl(Features, "clwb", true); 2914 // FALLTHROUGH 2915 case CK_SkylakeClient: 2916 setFeatureEnabledImpl(Features, "xsavec", true); 2917 setFeatureEnabledImpl(Features, "xsaves", true); 2918 setFeatureEnabledImpl(Features, "mpx", true); 2919 setFeatureEnabledImpl(Features, "sgx", true); 2920 setFeatureEnabledImpl(Features, "clflushopt", true); 2921 // FALLTHROUGH 2922 case CK_Broadwell: 2923 setFeatureEnabledImpl(Features, "rdseed", true); 2924 setFeatureEnabledImpl(Features, "adx", true); 2925 // FALLTHROUGH 2926 case CK_Haswell: 2927 setFeatureEnabledImpl(Features, "avx2", true); 2928 setFeatureEnabledImpl(Features, "lzcnt", true); 2929 setFeatureEnabledImpl(Features, "bmi", true); 2930 setFeatureEnabledImpl(Features, "bmi2", true); 2931 setFeatureEnabledImpl(Features, "rtm", true); 2932 setFeatureEnabledImpl(Features, "fma", true); 2933 setFeatureEnabledImpl(Features, "movbe", true); 2934 // FALLTHROUGH 2935 case CK_IvyBridge: 2936 setFeatureEnabledImpl(Features, "rdrnd", true); 2937 setFeatureEnabledImpl(Features, "f16c", true); 2938 setFeatureEnabledImpl(Features, "fsgsbase", true); 2939 // FALLTHROUGH 2940 case CK_SandyBridge: 2941 setFeatureEnabledImpl(Features, "avx", true); 2942 setFeatureEnabledImpl(Features, "xsave", true); 2943 setFeatureEnabledImpl(Features, "xsaveopt", true); 2944 // FALLTHROUGH 2945 case CK_Westmere: 2946 case CK_Silvermont: 2947 setFeatureEnabledImpl(Features, "aes", true); 2948 setFeatureEnabledImpl(Features, "pclmul", true); 2949 // FALLTHROUGH 2950 case CK_Nehalem: 2951 setFeatureEnabledImpl(Features, "sse4.2", true); 2952 setFeatureEnabledImpl(Features, "fxsr", true); 2953 setFeatureEnabledImpl(Features, "cx16", true); 2954 break; 2955 case CK_KNL: 2956 setFeatureEnabledImpl(Features, "avx512f", true); 2957 setFeatureEnabledImpl(Features, "avx512cd", true); 2958 setFeatureEnabledImpl(Features, "avx512er", true); 2959 setFeatureEnabledImpl(Features, "avx512pf", true); 2960 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2961 setFeatureEnabledImpl(Features, "fxsr", true); 2962 setFeatureEnabledImpl(Features, "rdseed", true); 2963 setFeatureEnabledImpl(Features, "adx", true); 2964 setFeatureEnabledImpl(Features, "lzcnt", true); 2965 setFeatureEnabledImpl(Features, "bmi", true); 2966 setFeatureEnabledImpl(Features, "bmi2", true); 2967 setFeatureEnabledImpl(Features, "rtm", true); 2968 setFeatureEnabledImpl(Features, "fma", true); 2969 setFeatureEnabledImpl(Features, "rdrnd", true); 2970 setFeatureEnabledImpl(Features, "f16c", true); 2971 setFeatureEnabledImpl(Features, "fsgsbase", true); 2972 setFeatureEnabledImpl(Features, "aes", true); 2973 setFeatureEnabledImpl(Features, "pclmul", true); 2974 setFeatureEnabledImpl(Features, "cx16", true); 2975 setFeatureEnabledImpl(Features, "xsaveopt", true); 2976 setFeatureEnabledImpl(Features, "xsave", true); 2977 setFeatureEnabledImpl(Features, "movbe", true); 2978 break; 2979 case CK_K6_2: 2980 case CK_K6_3: 2981 case CK_WinChip2: 2982 case CK_C3: 2983 setFeatureEnabledImpl(Features, "3dnow", true); 2984 break; 2985 case CK_Athlon: 2986 case CK_AthlonThunderbird: 2987 case CK_Geode: 2988 setFeatureEnabledImpl(Features, "3dnowa", true); 2989 break; 2990 case CK_Athlon4: 2991 case CK_AthlonXP: 2992 case CK_AthlonMP: 2993 setFeatureEnabledImpl(Features, "sse", true); 2994 setFeatureEnabledImpl(Features, "3dnowa", true); 2995 setFeatureEnabledImpl(Features, "fxsr", true); 2996 break; 2997 case CK_K8: 2998 case CK_Opteron: 2999 case CK_Athlon64: 3000 case CK_AthlonFX: 3001 setFeatureEnabledImpl(Features, "sse2", true); 3002 setFeatureEnabledImpl(Features, "3dnowa", true); 3003 setFeatureEnabledImpl(Features, "fxsr", true); 3004 break; 3005 case CK_AMDFAM10: 3006 setFeatureEnabledImpl(Features, "sse4a", true); 3007 setFeatureEnabledImpl(Features, "lzcnt", true); 3008 setFeatureEnabledImpl(Features, "popcnt", true); 3009 // FALLTHROUGH 3010 case CK_K8SSE3: 3011 case CK_OpteronSSE3: 3012 case CK_Athlon64SSE3: 3013 setFeatureEnabledImpl(Features, "sse3", true); 3014 setFeatureEnabledImpl(Features, "3dnowa", true); 3015 setFeatureEnabledImpl(Features, "fxsr", true); 3016 break; 3017 case CK_BTVER2: 3018 setFeatureEnabledImpl(Features, "avx", true); 3019 setFeatureEnabledImpl(Features, "aes", true); 3020 setFeatureEnabledImpl(Features, "pclmul", true); 3021 setFeatureEnabledImpl(Features, "bmi", true); 3022 setFeatureEnabledImpl(Features, "f16c", true); 3023 setFeatureEnabledImpl(Features, "xsaveopt", true); 3024 // FALLTHROUGH 3025 case CK_BTVER1: 3026 setFeatureEnabledImpl(Features, "ssse3", true); 3027 setFeatureEnabledImpl(Features, "sse4a", true); 3028 setFeatureEnabledImpl(Features, "lzcnt", true); 3029 setFeatureEnabledImpl(Features, "popcnt", true); 3030 setFeatureEnabledImpl(Features, "prfchw", true); 3031 setFeatureEnabledImpl(Features, "cx16", true); 3032 setFeatureEnabledImpl(Features, "fxsr", true); 3033 break; 3034 case CK_BDVER4: 3035 setFeatureEnabledImpl(Features, "avx2", true); 3036 setFeatureEnabledImpl(Features, "bmi2", true); 3037 setFeatureEnabledImpl(Features, "mwaitx", true); 3038 // FALLTHROUGH 3039 case CK_BDVER3: 3040 setFeatureEnabledImpl(Features, "fsgsbase", true); 3041 setFeatureEnabledImpl(Features, "xsaveopt", true); 3042 // FALLTHROUGH 3043 case CK_BDVER2: 3044 setFeatureEnabledImpl(Features, "bmi", true); 3045 setFeatureEnabledImpl(Features, "fma", true); 3046 setFeatureEnabledImpl(Features, "f16c", true); 3047 setFeatureEnabledImpl(Features, "tbm", true); 3048 // FALLTHROUGH 3049 case CK_BDVER1: 3050 // xop implies avx, sse4a and fma4. 3051 setFeatureEnabledImpl(Features, "xop", true); 3052 setFeatureEnabledImpl(Features, "lzcnt", true); 3053 setFeatureEnabledImpl(Features, "aes", true); 3054 setFeatureEnabledImpl(Features, "pclmul", true); 3055 setFeatureEnabledImpl(Features, "prfchw", true); 3056 setFeatureEnabledImpl(Features, "cx16", true); 3057 setFeatureEnabledImpl(Features, "fxsr", true); 3058 setFeatureEnabledImpl(Features, "xsave", true); 3059 break; 3060 } 3061 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3062 return false; 3063 3064 // Can't do this earlier because we need to be able to explicitly enable 3065 // or disable these features and the things that they depend upon. 3066 3067 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3068 auto I = Features.find("sse4.2"); 3069 if (I != Features.end() && I->getValue() && 3070 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3071 FeaturesVec.end()) 3072 Features["popcnt"] = true; 3073 3074 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3075 I = Features.find("3dnow"); 3076 if (I != Features.end() && I->getValue() && 3077 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3078 FeaturesVec.end()) 3079 Features["prfchw"] = true; 3080 3081 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3082 // then enable MMX. 3083 I = Features.find("sse"); 3084 if (I != Features.end() && I->getValue() && 3085 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3086 FeaturesVec.end()) 3087 Features["mmx"] = true; 3088 3089 return true; 3090 } 3091 3092 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3093 X86SSEEnum Level, bool Enabled) { 3094 if (Enabled) { 3095 switch (Level) { 3096 case AVX512F: 3097 Features["avx512f"] = true; 3098 case AVX2: 3099 Features["avx2"] = true; 3100 case AVX: 3101 Features["avx"] = true; 3102 Features["xsave"] = true; 3103 case SSE42: 3104 Features["sse4.2"] = true; 3105 case SSE41: 3106 Features["sse4.1"] = true; 3107 case SSSE3: 3108 Features["ssse3"] = true; 3109 case SSE3: 3110 Features["sse3"] = true; 3111 case SSE2: 3112 Features["sse2"] = true; 3113 case SSE1: 3114 Features["sse"] = true; 3115 case NoSSE: 3116 break; 3117 } 3118 return; 3119 } 3120 3121 switch (Level) { 3122 case NoSSE: 3123 case SSE1: 3124 Features["sse"] = false; 3125 case SSE2: 3126 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3127 Features["sha"] = false; 3128 case SSE3: 3129 Features["sse3"] = false; 3130 setXOPLevel(Features, NoXOP, false); 3131 case SSSE3: 3132 Features["ssse3"] = false; 3133 case SSE41: 3134 Features["sse4.1"] = false; 3135 case SSE42: 3136 Features["sse4.2"] = false; 3137 case AVX: 3138 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3139 Features["xsaveopt"] = false; 3140 setXOPLevel(Features, FMA4, false); 3141 case AVX2: 3142 Features["avx2"] = false; 3143 case AVX512F: 3144 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3145 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3146 Features["avx512vl"] = Features["avx512vbmi"] = 3147 Features["avx512ifma"] = false; 3148 } 3149 } 3150 3151 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3152 MMX3DNowEnum Level, bool Enabled) { 3153 if (Enabled) { 3154 switch (Level) { 3155 case AMD3DNowAthlon: 3156 Features["3dnowa"] = true; 3157 case AMD3DNow: 3158 Features["3dnow"] = true; 3159 case MMX: 3160 Features["mmx"] = true; 3161 case NoMMX3DNow: 3162 break; 3163 } 3164 return; 3165 } 3166 3167 switch (Level) { 3168 case NoMMX3DNow: 3169 case MMX: 3170 Features["mmx"] = false; 3171 case AMD3DNow: 3172 Features["3dnow"] = false; 3173 case AMD3DNowAthlon: 3174 Features["3dnowa"] = false; 3175 } 3176 } 3177 3178 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3179 bool Enabled) { 3180 if (Enabled) { 3181 switch (Level) { 3182 case XOP: 3183 Features["xop"] = true; 3184 case FMA4: 3185 Features["fma4"] = true; 3186 setSSELevel(Features, AVX, true); 3187 case SSE4A: 3188 Features["sse4a"] = true; 3189 setSSELevel(Features, SSE3, true); 3190 case NoXOP: 3191 break; 3192 } 3193 return; 3194 } 3195 3196 switch (Level) { 3197 case NoXOP: 3198 case SSE4A: 3199 Features["sse4a"] = false; 3200 case FMA4: 3201 Features["fma4"] = false; 3202 case XOP: 3203 Features["xop"] = false; 3204 } 3205 } 3206 3207 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3208 StringRef Name, bool Enabled) { 3209 // This is a bit of a hack to deal with the sse4 target feature when used 3210 // as part of the target attribute. We handle sse4 correctly everywhere 3211 // else. See below for more information on how we handle the sse4 options. 3212 if (Name != "sse4") 3213 Features[Name] = Enabled; 3214 3215 if (Name == "mmx") { 3216 setMMXLevel(Features, MMX, Enabled); 3217 } else if (Name == "sse") { 3218 setSSELevel(Features, SSE1, Enabled); 3219 } else if (Name == "sse2") { 3220 setSSELevel(Features, SSE2, Enabled); 3221 } else if (Name == "sse3") { 3222 setSSELevel(Features, SSE3, Enabled); 3223 } else if (Name == "ssse3") { 3224 setSSELevel(Features, SSSE3, Enabled); 3225 } else if (Name == "sse4.2") { 3226 setSSELevel(Features, SSE42, Enabled); 3227 } else if (Name == "sse4.1") { 3228 setSSELevel(Features, SSE41, Enabled); 3229 } else if (Name == "3dnow") { 3230 setMMXLevel(Features, AMD3DNow, Enabled); 3231 } else if (Name == "3dnowa") { 3232 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3233 } else if (Name == "aes") { 3234 if (Enabled) 3235 setSSELevel(Features, SSE2, Enabled); 3236 } else if (Name == "pclmul") { 3237 if (Enabled) 3238 setSSELevel(Features, SSE2, Enabled); 3239 } else if (Name == "avx") { 3240 setSSELevel(Features, AVX, Enabled); 3241 } else if (Name == "avx2") { 3242 setSSELevel(Features, AVX2, Enabled); 3243 } else if (Name == "avx512f") { 3244 setSSELevel(Features, AVX512F, Enabled); 3245 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3246 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3247 Name == "avx512vbmi" || Name == "avx512ifma") { 3248 if (Enabled) 3249 setSSELevel(Features, AVX512F, Enabled); 3250 } else if (Name == "fma") { 3251 if (Enabled) 3252 setSSELevel(Features, AVX, Enabled); 3253 } else if (Name == "fma4") { 3254 setXOPLevel(Features, FMA4, Enabled); 3255 } else if (Name == "xop") { 3256 setXOPLevel(Features, XOP, Enabled); 3257 } else if (Name == "sse4a") { 3258 setXOPLevel(Features, SSE4A, Enabled); 3259 } else if (Name == "f16c") { 3260 if (Enabled) 3261 setSSELevel(Features, AVX, Enabled); 3262 } else if (Name == "sha") { 3263 if (Enabled) 3264 setSSELevel(Features, SSE2, Enabled); 3265 } else if (Name == "sse4") { 3266 // We can get here via the __target__ attribute since that's not controlled 3267 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3268 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3269 // disabled. 3270 if (Enabled) 3271 setSSELevel(Features, SSE42, Enabled); 3272 else 3273 setSSELevel(Features, SSE41, Enabled); 3274 } else if (Name == "xsave") { 3275 if (!Enabled) 3276 Features["xsaveopt"] = false; 3277 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3278 if (Enabled) 3279 Features["xsave"] = true; 3280 } 3281 } 3282 3283 /// handleTargetFeatures - Perform initialization based on the user 3284 /// configured set of features. 3285 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3286 DiagnosticsEngine &Diags) { 3287 for (const auto &Feature : Features) { 3288 if (Feature[0] != '+') 3289 continue; 3290 3291 if (Feature == "+aes") { 3292 HasAES = true; 3293 } else if (Feature == "+pclmul") { 3294 HasPCLMUL = true; 3295 } else if (Feature == "+lzcnt") { 3296 HasLZCNT = true; 3297 } else if (Feature == "+rdrnd") { 3298 HasRDRND = true; 3299 } else if (Feature == "+fsgsbase") { 3300 HasFSGSBASE = true; 3301 } else if (Feature == "+bmi") { 3302 HasBMI = true; 3303 } else if (Feature == "+bmi2") { 3304 HasBMI2 = true; 3305 } else if (Feature == "+popcnt") { 3306 HasPOPCNT = true; 3307 } else if (Feature == "+rtm") { 3308 HasRTM = true; 3309 } else if (Feature == "+prfchw") { 3310 HasPRFCHW = true; 3311 } else if (Feature == "+rdseed") { 3312 HasRDSEED = true; 3313 } else if (Feature == "+adx") { 3314 HasADX = true; 3315 } else if (Feature == "+tbm") { 3316 HasTBM = true; 3317 } else if (Feature == "+fma") { 3318 HasFMA = true; 3319 } else if (Feature == "+f16c") { 3320 HasF16C = true; 3321 } else if (Feature == "+avx512cd") { 3322 HasAVX512CD = true; 3323 } else if (Feature == "+avx512er") { 3324 HasAVX512ER = true; 3325 } else if (Feature == "+avx512pf") { 3326 HasAVX512PF = true; 3327 } else if (Feature == "+avx512dq") { 3328 HasAVX512DQ = true; 3329 } else if (Feature == "+avx512bw") { 3330 HasAVX512BW = true; 3331 } else if (Feature == "+avx512vl") { 3332 HasAVX512VL = true; 3333 } else if (Feature == "+avx512vbmi") { 3334 HasAVX512VBMI = true; 3335 } else if (Feature == "+avx512ifma") { 3336 HasAVX512IFMA = true; 3337 } else if (Feature == "+sha") { 3338 HasSHA = true; 3339 } else if (Feature == "+mpx") { 3340 HasMPX = true; 3341 } else if (Feature == "+movbe") { 3342 HasMOVBE = true; 3343 } else if (Feature == "+sgx") { 3344 HasSGX = true; 3345 } else if (Feature == "+cx16") { 3346 HasCX16 = true; 3347 } else if (Feature == "+fxsr") { 3348 HasFXSR = true; 3349 } else if (Feature == "+xsave") { 3350 HasXSAVE = true; 3351 } else if (Feature == "+xsaveopt") { 3352 HasXSAVEOPT = true; 3353 } else if (Feature == "+xsavec") { 3354 HasXSAVEC = true; 3355 } else if (Feature == "+xsaves") { 3356 HasXSAVES = true; 3357 } else if (Feature == "+mwaitx") { 3358 HasMWAITX = true; 3359 } else if (Feature == "+pku") { 3360 HasPKU = true; 3361 } else if (Feature == "+clflushopt") { 3362 HasCLFLUSHOPT = true; 3363 } else if (Feature == "+pcommit") { 3364 HasPCOMMIT = true; 3365 } else if (Feature == "+clwb") { 3366 HasCLWB = true; 3367 } else if (Feature == "+umip") { 3368 HasUMIP = true; 3369 } else if (Feature == "+prefetchwt1") { 3370 HasPREFETCHWT1 = true; 3371 } 3372 3373 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3374 .Case("+avx512f", AVX512F) 3375 .Case("+avx2", AVX2) 3376 .Case("+avx", AVX) 3377 .Case("+sse4.2", SSE42) 3378 .Case("+sse4.1", SSE41) 3379 .Case("+ssse3", SSSE3) 3380 .Case("+sse3", SSE3) 3381 .Case("+sse2", SSE2) 3382 .Case("+sse", SSE1) 3383 .Default(NoSSE); 3384 SSELevel = std::max(SSELevel, Level); 3385 3386 MMX3DNowEnum ThreeDNowLevel = 3387 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3388 .Case("+3dnowa", AMD3DNowAthlon) 3389 .Case("+3dnow", AMD3DNow) 3390 .Case("+mmx", MMX) 3391 .Default(NoMMX3DNow); 3392 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3393 3394 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3395 .Case("+xop", XOP) 3396 .Case("+fma4", FMA4) 3397 .Case("+sse4a", SSE4A) 3398 .Default(NoXOP); 3399 XOPLevel = std::max(XOPLevel, XLevel); 3400 } 3401 3402 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3403 // matches the selected sse level. 3404 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3405 (FPMath == FP_387 && SSELevel >= SSE1)) { 3406 Diags.Report(diag::err_target_unsupported_fpmath) << 3407 (FPMath == FP_SSE ? "sse" : "387"); 3408 return false; 3409 } 3410 3411 SimdDefaultAlign = 3412 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3413 return true; 3414 } 3415 3416 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3417 /// definitions for this particular subtarget. 3418 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3419 MacroBuilder &Builder) const { 3420 // Target identification. 3421 if (getTriple().getArch() == llvm::Triple::x86_64) { 3422 Builder.defineMacro("__amd64__"); 3423 Builder.defineMacro("__amd64"); 3424 Builder.defineMacro("__x86_64"); 3425 Builder.defineMacro("__x86_64__"); 3426 if (getTriple().getArchName() == "x86_64h") { 3427 Builder.defineMacro("__x86_64h"); 3428 Builder.defineMacro("__x86_64h__"); 3429 } 3430 } else { 3431 DefineStd(Builder, "i386", Opts); 3432 } 3433 3434 // Subtarget options. 3435 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3436 // truly should be based on -mtune options. 3437 switch (CPU) { 3438 case CK_Generic: 3439 break; 3440 case CK_i386: 3441 // The rest are coming from the i386 define above. 3442 Builder.defineMacro("__tune_i386__"); 3443 break; 3444 case CK_i486: 3445 case CK_WinChipC6: 3446 case CK_WinChip2: 3447 case CK_C3: 3448 defineCPUMacros(Builder, "i486"); 3449 break; 3450 case CK_PentiumMMX: 3451 Builder.defineMacro("__pentium_mmx__"); 3452 Builder.defineMacro("__tune_pentium_mmx__"); 3453 // Fallthrough 3454 case CK_i586: 3455 case CK_Pentium: 3456 defineCPUMacros(Builder, "i586"); 3457 defineCPUMacros(Builder, "pentium"); 3458 break; 3459 case CK_Pentium3: 3460 case CK_Pentium3M: 3461 case CK_PentiumM: 3462 Builder.defineMacro("__tune_pentium3__"); 3463 // Fallthrough 3464 case CK_Pentium2: 3465 case CK_C3_2: 3466 Builder.defineMacro("__tune_pentium2__"); 3467 // Fallthrough 3468 case CK_PentiumPro: 3469 Builder.defineMacro("__tune_i686__"); 3470 Builder.defineMacro("__tune_pentiumpro__"); 3471 // Fallthrough 3472 case CK_i686: 3473 Builder.defineMacro("__i686"); 3474 Builder.defineMacro("__i686__"); 3475 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3476 Builder.defineMacro("__pentiumpro"); 3477 Builder.defineMacro("__pentiumpro__"); 3478 break; 3479 case CK_Pentium4: 3480 case CK_Pentium4M: 3481 defineCPUMacros(Builder, "pentium4"); 3482 break; 3483 case CK_Yonah: 3484 case CK_Prescott: 3485 case CK_Nocona: 3486 defineCPUMacros(Builder, "nocona"); 3487 break; 3488 case CK_Core2: 3489 case CK_Penryn: 3490 defineCPUMacros(Builder, "core2"); 3491 break; 3492 case CK_Bonnell: 3493 defineCPUMacros(Builder, "atom"); 3494 break; 3495 case CK_Silvermont: 3496 defineCPUMacros(Builder, "slm"); 3497 break; 3498 case CK_Nehalem: 3499 case CK_Westmere: 3500 case CK_SandyBridge: 3501 case CK_IvyBridge: 3502 case CK_Haswell: 3503 case CK_Broadwell: 3504 case CK_SkylakeClient: 3505 // FIXME: Historically, we defined this legacy name, it would be nice to 3506 // remove it at some point. We've never exposed fine-grained names for 3507 // recent primary x86 CPUs, and we should keep it that way. 3508 defineCPUMacros(Builder, "corei7"); 3509 break; 3510 case CK_SkylakeServer: 3511 defineCPUMacros(Builder, "skx"); 3512 break; 3513 case CK_Cannonlake: 3514 break; 3515 case CK_KNL: 3516 defineCPUMacros(Builder, "knl"); 3517 break; 3518 case CK_Lakemont: 3519 Builder.defineMacro("__tune_lakemont__"); 3520 break; 3521 case CK_K6_2: 3522 Builder.defineMacro("__k6_2__"); 3523 Builder.defineMacro("__tune_k6_2__"); 3524 // Fallthrough 3525 case CK_K6_3: 3526 if (CPU != CK_K6_2) { // In case of fallthrough 3527 // FIXME: GCC may be enabling these in cases where some other k6 3528 // architecture is specified but -m3dnow is explicitly provided. The 3529 // exact semantics need to be determined and emulated here. 3530 Builder.defineMacro("__k6_3__"); 3531 Builder.defineMacro("__tune_k6_3__"); 3532 } 3533 // Fallthrough 3534 case CK_K6: 3535 defineCPUMacros(Builder, "k6"); 3536 break; 3537 case CK_Athlon: 3538 case CK_AthlonThunderbird: 3539 case CK_Athlon4: 3540 case CK_AthlonXP: 3541 case CK_AthlonMP: 3542 defineCPUMacros(Builder, "athlon"); 3543 if (SSELevel != NoSSE) { 3544 Builder.defineMacro("__athlon_sse__"); 3545 Builder.defineMacro("__tune_athlon_sse__"); 3546 } 3547 break; 3548 case CK_K8: 3549 case CK_K8SSE3: 3550 case CK_x86_64: 3551 case CK_Opteron: 3552 case CK_OpteronSSE3: 3553 case CK_Athlon64: 3554 case CK_Athlon64SSE3: 3555 case CK_AthlonFX: 3556 defineCPUMacros(Builder, "k8"); 3557 break; 3558 case CK_AMDFAM10: 3559 defineCPUMacros(Builder, "amdfam10"); 3560 break; 3561 case CK_BTVER1: 3562 defineCPUMacros(Builder, "btver1"); 3563 break; 3564 case CK_BTVER2: 3565 defineCPUMacros(Builder, "btver2"); 3566 break; 3567 case CK_BDVER1: 3568 defineCPUMacros(Builder, "bdver1"); 3569 break; 3570 case CK_BDVER2: 3571 defineCPUMacros(Builder, "bdver2"); 3572 break; 3573 case CK_BDVER3: 3574 defineCPUMacros(Builder, "bdver3"); 3575 break; 3576 case CK_BDVER4: 3577 defineCPUMacros(Builder, "bdver4"); 3578 break; 3579 case CK_Geode: 3580 defineCPUMacros(Builder, "geode"); 3581 break; 3582 } 3583 3584 // Target properties. 3585 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3586 3587 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3588 // functions in glibc header files that use FP Stack inline asm which the 3589 // backend can't deal with (PR879). 3590 Builder.defineMacro("__NO_MATH_INLINES"); 3591 3592 if (HasAES) 3593 Builder.defineMacro("__AES__"); 3594 3595 if (HasPCLMUL) 3596 Builder.defineMacro("__PCLMUL__"); 3597 3598 if (HasLZCNT) 3599 Builder.defineMacro("__LZCNT__"); 3600 3601 if (HasRDRND) 3602 Builder.defineMacro("__RDRND__"); 3603 3604 if (HasFSGSBASE) 3605 Builder.defineMacro("__FSGSBASE__"); 3606 3607 if (HasBMI) 3608 Builder.defineMacro("__BMI__"); 3609 3610 if (HasBMI2) 3611 Builder.defineMacro("__BMI2__"); 3612 3613 if (HasPOPCNT) 3614 Builder.defineMacro("__POPCNT__"); 3615 3616 if (HasRTM) 3617 Builder.defineMacro("__RTM__"); 3618 3619 if (HasPRFCHW) 3620 Builder.defineMacro("__PRFCHW__"); 3621 3622 if (HasRDSEED) 3623 Builder.defineMacro("__RDSEED__"); 3624 3625 if (HasADX) 3626 Builder.defineMacro("__ADX__"); 3627 3628 if (HasTBM) 3629 Builder.defineMacro("__TBM__"); 3630 3631 if (HasMWAITX) 3632 Builder.defineMacro("__MWAITX__"); 3633 3634 switch (XOPLevel) { 3635 case XOP: 3636 Builder.defineMacro("__XOP__"); 3637 case FMA4: 3638 Builder.defineMacro("__FMA4__"); 3639 case SSE4A: 3640 Builder.defineMacro("__SSE4A__"); 3641 case NoXOP: 3642 break; 3643 } 3644 3645 if (HasFMA) 3646 Builder.defineMacro("__FMA__"); 3647 3648 if (HasF16C) 3649 Builder.defineMacro("__F16C__"); 3650 3651 if (HasAVX512CD) 3652 Builder.defineMacro("__AVX512CD__"); 3653 if (HasAVX512ER) 3654 Builder.defineMacro("__AVX512ER__"); 3655 if (HasAVX512PF) 3656 Builder.defineMacro("__AVX512PF__"); 3657 if (HasAVX512DQ) 3658 Builder.defineMacro("__AVX512DQ__"); 3659 if (HasAVX512BW) 3660 Builder.defineMacro("__AVX512BW__"); 3661 if (HasAVX512VL) 3662 Builder.defineMacro("__AVX512VL__"); 3663 if (HasAVX512VBMI) 3664 Builder.defineMacro("__AVX512VBMI__"); 3665 if (HasAVX512IFMA) 3666 Builder.defineMacro("__AVX512IFMA__"); 3667 3668 if (HasSHA) 3669 Builder.defineMacro("__SHA__"); 3670 3671 if (HasFXSR) 3672 Builder.defineMacro("__FXSR__"); 3673 if (HasXSAVE) 3674 Builder.defineMacro("__XSAVE__"); 3675 if (HasXSAVEOPT) 3676 Builder.defineMacro("__XSAVEOPT__"); 3677 if (HasXSAVEC) 3678 Builder.defineMacro("__XSAVEC__"); 3679 if (HasXSAVES) 3680 Builder.defineMacro("__XSAVES__"); 3681 if (HasPKU) 3682 Builder.defineMacro("__PKU__"); 3683 if (HasCX16) 3684 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3685 3686 // Each case falls through to the previous one here. 3687 switch (SSELevel) { 3688 case AVX512F: 3689 Builder.defineMacro("__AVX512F__"); 3690 case AVX2: 3691 Builder.defineMacro("__AVX2__"); 3692 case AVX: 3693 Builder.defineMacro("__AVX__"); 3694 case SSE42: 3695 Builder.defineMacro("__SSE4_2__"); 3696 case SSE41: 3697 Builder.defineMacro("__SSE4_1__"); 3698 case SSSE3: 3699 Builder.defineMacro("__SSSE3__"); 3700 case SSE3: 3701 Builder.defineMacro("__SSE3__"); 3702 case SSE2: 3703 Builder.defineMacro("__SSE2__"); 3704 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3705 case SSE1: 3706 Builder.defineMacro("__SSE__"); 3707 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3708 case NoSSE: 3709 break; 3710 } 3711 3712 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3713 switch (SSELevel) { 3714 case AVX512F: 3715 case AVX2: 3716 case AVX: 3717 case SSE42: 3718 case SSE41: 3719 case SSSE3: 3720 case SSE3: 3721 case SSE2: 3722 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3723 break; 3724 case SSE1: 3725 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3726 break; 3727 default: 3728 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3729 } 3730 } 3731 3732 // Each case falls through to the previous one here. 3733 switch (MMX3DNowLevel) { 3734 case AMD3DNowAthlon: 3735 Builder.defineMacro("__3dNOW_A__"); 3736 case AMD3DNow: 3737 Builder.defineMacro("__3dNOW__"); 3738 case MMX: 3739 Builder.defineMacro("__MMX__"); 3740 case NoMMX3DNow: 3741 break; 3742 } 3743 3744 if (CPU >= CK_i486) { 3745 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3746 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3747 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3748 } 3749 if (CPU >= CK_i586) 3750 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3751 } 3752 3753 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3754 return llvm::StringSwitch<bool>(Feature) 3755 .Case("aes", HasAES) 3756 .Case("avx", SSELevel >= AVX) 3757 .Case("avx2", SSELevel >= AVX2) 3758 .Case("avx512f", SSELevel >= AVX512F) 3759 .Case("avx512cd", HasAVX512CD) 3760 .Case("avx512er", HasAVX512ER) 3761 .Case("avx512pf", HasAVX512PF) 3762 .Case("avx512dq", HasAVX512DQ) 3763 .Case("avx512bw", HasAVX512BW) 3764 .Case("avx512vl", HasAVX512VL) 3765 .Case("avx512vbmi", HasAVX512VBMI) 3766 .Case("avx512ifma", HasAVX512IFMA) 3767 .Case("bmi", HasBMI) 3768 .Case("bmi2", HasBMI2) 3769 .Case("clflushopt", HasCLFLUSHOPT) 3770 .Case("clwb", HasCLWB) 3771 .Case("cx16", HasCX16) 3772 .Case("f16c", HasF16C) 3773 .Case("fma", HasFMA) 3774 .Case("fma4", XOPLevel >= FMA4) 3775 .Case("fsgsbase", HasFSGSBASE) 3776 .Case("fxsr", HasFXSR) 3777 .Case("lzcnt", HasLZCNT) 3778 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3779 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3780 .Case("mmx", MMX3DNowLevel >= MMX) 3781 .Case("movbe", HasMOVBE) 3782 .Case("mpx", HasMPX) 3783 .Case("pclmul", HasPCLMUL) 3784 .Case("pcommit", HasPCOMMIT) 3785 .Case("pku", HasPKU) 3786 .Case("popcnt", HasPOPCNT) 3787 .Case("prefetchwt1", HasPREFETCHWT1) 3788 .Case("prfchw", HasPRFCHW) 3789 .Case("rdrnd", HasRDRND) 3790 .Case("rdseed", HasRDSEED) 3791 .Case("rtm", HasRTM) 3792 .Case("sgx", HasSGX) 3793 .Case("sha", HasSHA) 3794 .Case("sse", SSELevel >= SSE1) 3795 .Case("sse2", SSELevel >= SSE2) 3796 .Case("sse3", SSELevel >= SSE3) 3797 .Case("ssse3", SSELevel >= SSSE3) 3798 .Case("sse4.1", SSELevel >= SSE41) 3799 .Case("sse4.2", SSELevel >= SSE42) 3800 .Case("sse4a", XOPLevel >= SSE4A) 3801 .Case("tbm", HasTBM) 3802 .Case("umip", HasUMIP) 3803 .Case("x86", true) 3804 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3805 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3806 .Case("xop", XOPLevel >= XOP) 3807 .Case("xsave", HasXSAVE) 3808 .Case("xsavec", HasXSAVEC) 3809 .Case("xsaves", HasXSAVES) 3810 .Case("xsaveopt", HasXSAVEOPT) 3811 .Default(false); 3812 } 3813 3814 // We can't use a generic validation scheme for the features accepted here 3815 // versus subtarget features accepted in the target attribute because the 3816 // bitfield structure that's initialized in the runtime only supports the 3817 // below currently rather than the full range of subtarget features. (See 3818 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3819 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3820 return llvm::StringSwitch<bool>(FeatureStr) 3821 .Case("cmov", true) 3822 .Case("mmx", true) 3823 .Case("popcnt", true) 3824 .Case("sse", true) 3825 .Case("sse2", true) 3826 .Case("sse3", true) 3827 .Case("ssse3", true) 3828 .Case("sse4.1", true) 3829 .Case("sse4.2", true) 3830 .Case("avx", true) 3831 .Case("avx2", true) 3832 .Case("sse4a", true) 3833 .Case("fma4", true) 3834 .Case("xop", true) 3835 .Case("fma", true) 3836 .Case("avx512f", true) 3837 .Case("bmi", true) 3838 .Case("bmi2", true) 3839 .Case("aes", true) 3840 .Case("pclmul", true) 3841 .Case("avx512vl", true) 3842 .Case("avx512bw", true) 3843 .Case("avx512dq", true) 3844 .Case("avx512cd", true) 3845 .Case("avx512er", true) 3846 .Case("avx512pf", true) 3847 .Case("avx512vbmi", true) 3848 .Case("avx512ifma", true) 3849 .Default(false); 3850 } 3851 3852 bool 3853 X86TargetInfo::validateAsmConstraint(const char *&Name, 3854 TargetInfo::ConstraintInfo &Info) const { 3855 switch (*Name) { 3856 default: return false; 3857 // Constant constraints. 3858 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3859 // instructions. 3860 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3861 // x86_64 instructions. 3862 case 's': 3863 Info.setRequiresImmediate(); 3864 return true; 3865 case 'I': 3866 Info.setRequiresImmediate(0, 31); 3867 return true; 3868 case 'J': 3869 Info.setRequiresImmediate(0, 63); 3870 return true; 3871 case 'K': 3872 Info.setRequiresImmediate(-128, 127); 3873 return true; 3874 case 'L': 3875 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3876 return true; 3877 case 'M': 3878 Info.setRequiresImmediate(0, 3); 3879 return true; 3880 case 'N': 3881 Info.setRequiresImmediate(0, 255); 3882 return true; 3883 case 'O': 3884 Info.setRequiresImmediate(0, 127); 3885 return true; 3886 // Register constraints. 3887 case 'Y': // 'Y' is the first character for several 2-character constraints. 3888 // Shift the pointer to the second character of the constraint. 3889 Name++; 3890 switch (*Name) { 3891 default: 3892 return false; 3893 case '0': // First SSE register. 3894 case 't': // Any SSE register, when SSE2 is enabled. 3895 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3896 case 'm': // Any MMX register, when inter-unit moves enabled. 3897 Info.setAllowsRegister(); 3898 return true; 3899 } 3900 case 'f': // Any x87 floating point stack register. 3901 // Constraint 'f' cannot be used for output operands. 3902 if (Info.ConstraintStr[0] == '=') 3903 return false; 3904 Info.setAllowsRegister(); 3905 return true; 3906 case 'a': // eax. 3907 case 'b': // ebx. 3908 case 'c': // ecx. 3909 case 'd': // edx. 3910 case 'S': // esi. 3911 case 'D': // edi. 3912 case 'A': // edx:eax. 3913 case 't': // Top of floating point stack. 3914 case 'u': // Second from top of floating point stack. 3915 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3916 case 'y': // Any MMX register. 3917 case 'x': // Any SSE register. 3918 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3919 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3920 case 'l': // "Index" registers: any general register that can be used as an 3921 // index in a base+index memory access. 3922 Info.setAllowsRegister(); 3923 return true; 3924 // Floating point constant constraints. 3925 case 'C': // SSE floating point constant. 3926 case 'G': // x87 floating point constant. 3927 return true; 3928 } 3929 } 3930 3931 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3932 unsigned Size) const { 3933 // Strip off constraint modifiers. 3934 while (Constraint[0] == '=' || 3935 Constraint[0] == '+' || 3936 Constraint[0] == '&') 3937 Constraint = Constraint.substr(1); 3938 3939 return validateOperandSize(Constraint, Size); 3940 } 3941 3942 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3943 unsigned Size) const { 3944 return validateOperandSize(Constraint, Size); 3945 } 3946 3947 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3948 unsigned Size) const { 3949 switch (Constraint[0]) { 3950 default: break; 3951 case 'y': 3952 return Size <= 64; 3953 case 'f': 3954 case 't': 3955 case 'u': 3956 return Size <= 128; 3957 case 'x': 3958 if (SSELevel >= AVX512F) 3959 // 512-bit zmm registers can be used if target supports AVX512F. 3960 return Size <= 512U; 3961 else if (SSELevel >= AVX) 3962 // 256-bit ymm registers can be used if target supports AVX. 3963 return Size <= 256U; 3964 return Size <= 128U; 3965 case 'Y': 3966 // 'Y' is the first character for several 2-character constraints. 3967 switch (Constraint[1]) { 3968 default: break; 3969 case 'm': 3970 // 'Ym' is synonymous with 'y'. 3971 return Size <= 64; 3972 case 'i': 3973 case 't': 3974 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3975 if (SSELevel >= AVX512F) 3976 return Size <= 512U; 3977 else if (SSELevel >= AVX) 3978 return Size <= 256U; 3979 return SSELevel >= SSE2 && Size <= 128U; 3980 } 3981 3982 } 3983 3984 return true; 3985 } 3986 3987 std::string 3988 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3989 switch (*Constraint) { 3990 case 'a': return std::string("{ax}"); 3991 case 'b': return std::string("{bx}"); 3992 case 'c': return std::string("{cx}"); 3993 case 'd': return std::string("{dx}"); 3994 case 'S': return std::string("{si}"); 3995 case 'D': return std::string("{di}"); 3996 case 'p': // address 3997 return std::string("im"); 3998 case 't': // top of floating point stack. 3999 return std::string("{st}"); 4000 case 'u': // second from top of floating point stack. 4001 return std::string("{st(1)}"); // second from top of floating point stack. 4002 default: 4003 return std::string(1, *Constraint); 4004 } 4005 } 4006 4007 // X86-32 generic target 4008 class X86_32TargetInfo : public X86TargetInfo { 4009 public: 4010 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4011 : X86TargetInfo(Triple, Opts) { 4012 DoubleAlign = LongLongAlign = 32; 4013 LongDoubleWidth = 96; 4014 LongDoubleAlign = 32; 4015 SuitableAlign = 128; 4016 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4017 SizeType = UnsignedInt; 4018 PtrDiffType = SignedInt; 4019 IntPtrType = SignedInt; 4020 RegParmMax = 3; 4021 4022 // Use fpret for all types. 4023 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4024 (1 << TargetInfo::Double) | 4025 (1 << TargetInfo::LongDouble)); 4026 4027 // x86-32 has atomics up to 8 bytes 4028 // FIXME: Check that we actually have cmpxchg8b before setting 4029 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4030 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4031 } 4032 BuiltinVaListKind getBuiltinVaListKind() const override { 4033 return TargetInfo::CharPtrBuiltinVaList; 4034 } 4035 4036 int getEHDataRegisterNumber(unsigned RegNo) const override { 4037 if (RegNo == 0) return 0; 4038 if (RegNo == 1) return 2; 4039 return -1; 4040 } 4041 bool validateOperandSize(StringRef Constraint, 4042 unsigned Size) const override { 4043 switch (Constraint[0]) { 4044 default: break; 4045 case 'R': 4046 case 'q': 4047 case 'Q': 4048 case 'a': 4049 case 'b': 4050 case 'c': 4051 case 'd': 4052 case 'S': 4053 case 'D': 4054 return Size <= 32; 4055 case 'A': 4056 return Size <= 64; 4057 } 4058 4059 return X86TargetInfo::validateOperandSize(Constraint, Size); 4060 } 4061 }; 4062 4063 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4064 public: 4065 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4066 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4067 4068 unsigned getFloatEvalMethod() const override { 4069 unsigned Major, Minor, Micro; 4070 getTriple().getOSVersion(Major, Minor, Micro); 4071 // New NetBSD uses the default rounding mode. 4072 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4073 return X86_32TargetInfo::getFloatEvalMethod(); 4074 // NetBSD before 6.99.26 defaults to "double" rounding. 4075 return 1; 4076 } 4077 }; 4078 4079 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4080 public: 4081 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4082 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4083 SizeType = UnsignedLong; 4084 IntPtrType = SignedLong; 4085 PtrDiffType = SignedLong; 4086 } 4087 }; 4088 4089 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4090 public: 4091 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4092 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4093 SizeType = UnsignedLong; 4094 IntPtrType = SignedLong; 4095 PtrDiffType = SignedLong; 4096 } 4097 }; 4098 4099 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4100 public: 4101 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4102 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4103 LongDoubleWidth = 128; 4104 LongDoubleAlign = 128; 4105 SuitableAlign = 128; 4106 MaxVectorAlign = 256; 4107 // The watchOS simulator uses the builtin bool type for Objective-C. 4108 llvm::Triple T = llvm::Triple(Triple); 4109 if (T.isWatchOS()) 4110 UseSignedCharForObjCBool = false; 4111 SizeType = UnsignedLong; 4112 IntPtrType = SignedLong; 4113 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4114 HasAlignMac68kSupport = true; 4115 } 4116 4117 bool handleTargetFeatures(std::vector<std::string> &Features, 4118 DiagnosticsEngine &Diags) override { 4119 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4120 Diags)) 4121 return false; 4122 // We now know the features we have: we can decide how to align vectors. 4123 MaxVectorAlign = 4124 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4125 return true; 4126 } 4127 }; 4128 4129 // x86-32 Windows target 4130 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4131 public: 4132 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4133 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4134 WCharType = UnsignedShort; 4135 DoubleAlign = LongLongAlign = 64; 4136 bool IsWinCOFF = 4137 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4138 resetDataLayout(IsWinCOFF 4139 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4140 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4141 } 4142 void getTargetDefines(const LangOptions &Opts, 4143 MacroBuilder &Builder) const override { 4144 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4145 } 4146 }; 4147 4148 // x86-32 Windows Visual Studio target 4149 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4150 public: 4151 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4152 const TargetOptions &Opts) 4153 : WindowsX86_32TargetInfo(Triple, Opts) { 4154 LongDoubleWidth = LongDoubleAlign = 64; 4155 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4156 } 4157 void getTargetDefines(const LangOptions &Opts, 4158 MacroBuilder &Builder) const override { 4159 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4160 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4161 // The value of the following reflects processor type. 4162 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4163 // We lost the original triple, so we use the default. 4164 Builder.defineMacro("_M_IX86", "600"); 4165 } 4166 }; 4167 4168 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4169 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4170 // supports __declspec natively under -fms-extensions, but we define a no-op 4171 // __declspec macro anyway for pre-processor compatibility. 4172 if (Opts.MicrosoftExt) 4173 Builder.defineMacro("__declspec", "__declspec"); 4174 else 4175 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4176 4177 if (!Opts.MicrosoftExt) { 4178 // Provide macros for all the calling convention keywords. Provide both 4179 // single and double underscore prefixed variants. These are available on 4180 // x64 as well as x86, even though they have no effect. 4181 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4182 for (const char *CC : CCs) { 4183 std::string GCCSpelling = "__attribute__((__"; 4184 GCCSpelling += CC; 4185 GCCSpelling += "__))"; 4186 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4187 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4188 } 4189 } 4190 } 4191 4192 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4193 Builder.defineMacro("__MSVCRT__"); 4194 Builder.defineMacro("__MINGW32__"); 4195 addCygMingDefines(Opts, Builder); 4196 } 4197 4198 // x86-32 MinGW target 4199 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4200 public: 4201 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4202 : WindowsX86_32TargetInfo(Triple, Opts) {} 4203 void getTargetDefines(const LangOptions &Opts, 4204 MacroBuilder &Builder) const override { 4205 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4206 DefineStd(Builder, "WIN32", Opts); 4207 DefineStd(Builder, "WINNT", Opts); 4208 Builder.defineMacro("_X86_"); 4209 addMinGWDefines(Opts, Builder); 4210 } 4211 }; 4212 4213 // x86-32 Cygwin target 4214 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4215 public: 4216 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4217 : X86_32TargetInfo(Triple, Opts) { 4218 WCharType = UnsignedShort; 4219 DoubleAlign = LongLongAlign = 64; 4220 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4221 } 4222 void getTargetDefines(const LangOptions &Opts, 4223 MacroBuilder &Builder) const override { 4224 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4225 Builder.defineMacro("_X86_"); 4226 Builder.defineMacro("__CYGWIN__"); 4227 Builder.defineMacro("__CYGWIN32__"); 4228 addCygMingDefines(Opts, Builder); 4229 DefineStd(Builder, "unix", Opts); 4230 if (Opts.CPlusPlus) 4231 Builder.defineMacro("_GNU_SOURCE"); 4232 } 4233 }; 4234 4235 // x86-32 Haiku target 4236 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4237 public: 4238 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4239 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4240 } 4241 void getTargetDefines(const LangOptions &Opts, 4242 MacroBuilder &Builder) const override { 4243 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4244 Builder.defineMacro("__INTEL__"); 4245 } 4246 }; 4247 4248 // X86-32 MCU target 4249 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4250 public: 4251 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4252 : X86_32TargetInfo(Triple, Opts) { 4253 LongDoubleWidth = 64; 4254 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4255 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4256 WIntType = UnsignedInt; 4257 } 4258 4259 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4260 // On MCU we support only C calling convention. 4261 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4262 } 4263 4264 void getTargetDefines(const LangOptions &Opts, 4265 MacroBuilder &Builder) const override { 4266 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4267 Builder.defineMacro("__iamcu"); 4268 Builder.defineMacro("__iamcu__"); 4269 } 4270 4271 bool allowsLargerPreferedTypeAlignment() const override { 4272 return false; 4273 } 4274 }; 4275 4276 // RTEMS Target 4277 template<typename Target> 4278 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4279 protected: 4280 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4281 MacroBuilder &Builder) const override { 4282 // RTEMS defines; list based off of gcc output 4283 4284 Builder.defineMacro("__rtems__"); 4285 Builder.defineMacro("__ELF__"); 4286 } 4287 4288 public: 4289 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4290 : OSTargetInfo<Target>(Triple, Opts) { 4291 switch (Triple.getArch()) { 4292 default: 4293 case llvm::Triple::x86: 4294 // this->MCountName = ".mcount"; 4295 break; 4296 case llvm::Triple::mips: 4297 case llvm::Triple::mipsel: 4298 case llvm::Triple::ppc: 4299 case llvm::Triple::ppc64: 4300 case llvm::Triple::ppc64le: 4301 // this->MCountName = "_mcount"; 4302 break; 4303 case llvm::Triple::arm: 4304 // this->MCountName = "__mcount"; 4305 break; 4306 } 4307 } 4308 }; 4309 4310 // x86-32 RTEMS target 4311 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4312 public: 4313 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4314 : X86_32TargetInfo(Triple, Opts) { 4315 SizeType = UnsignedLong; 4316 IntPtrType = SignedLong; 4317 PtrDiffType = SignedLong; 4318 } 4319 void getTargetDefines(const LangOptions &Opts, 4320 MacroBuilder &Builder) const override { 4321 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4322 Builder.defineMacro("__INTEL__"); 4323 Builder.defineMacro("__rtems__"); 4324 } 4325 }; 4326 4327 // x86-64 generic target 4328 class X86_64TargetInfo : public X86TargetInfo { 4329 public: 4330 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4331 : X86TargetInfo(Triple, Opts) { 4332 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4333 bool IsWinCOFF = 4334 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4335 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4336 LongDoubleWidth = 128; 4337 LongDoubleAlign = 128; 4338 LargeArrayMinWidth = 128; 4339 LargeArrayAlign = 128; 4340 SuitableAlign = 128; 4341 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4342 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4343 IntPtrType = IsX32 ? SignedInt : SignedLong; 4344 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4345 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4346 RegParmMax = 6; 4347 4348 // Pointers are 32-bit in x32. 4349 resetDataLayout(IsX32 4350 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4351 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4352 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4353 4354 // Use fpret only for long double. 4355 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4356 4357 // Use fp2ret for _Complex long double. 4358 ComplexLongDoubleUsesFP2Ret = true; 4359 4360 // Make __builtin_ms_va_list available. 4361 HasBuiltinMSVaList = true; 4362 4363 // x86-64 has atomics up to 16 bytes. 4364 MaxAtomicPromoteWidth = 128; 4365 MaxAtomicInlineWidth = 128; 4366 } 4367 BuiltinVaListKind getBuiltinVaListKind() const override { 4368 return TargetInfo::X86_64ABIBuiltinVaList; 4369 } 4370 4371 int getEHDataRegisterNumber(unsigned RegNo) const override { 4372 if (RegNo == 0) return 0; 4373 if (RegNo == 1) return 1; 4374 return -1; 4375 } 4376 4377 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4378 switch (CC) { 4379 case CC_C: 4380 case CC_Swift: 4381 case CC_X86VectorCall: 4382 case CC_IntelOclBicc: 4383 case CC_X86_64Win64: 4384 case CC_PreserveMost: 4385 case CC_PreserveAll: 4386 return CCCR_OK; 4387 default: 4388 return CCCR_Warning; 4389 } 4390 } 4391 4392 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4393 return CC_C; 4394 } 4395 4396 // for x32 we need it here explicitly 4397 bool hasInt128Type() const override { return true; } 4398 unsigned getUnwindWordWidth() const override { return 64; } 4399 unsigned getRegisterWidth() const override { return 64; } 4400 4401 bool validateGlobalRegisterVariable(StringRef RegName, 4402 unsigned RegSize, 4403 bool &HasSizeMismatch) const override { 4404 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4405 // handle. 4406 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4407 // Check that the register size is 64-bit. 4408 HasSizeMismatch = RegSize != 64; 4409 return true; 4410 } 4411 4412 // Check if the register is a 32-bit register the backend can handle. 4413 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4414 HasSizeMismatch); 4415 } 4416 }; 4417 4418 // x86-64 Windows target 4419 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4420 public: 4421 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4422 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4423 WCharType = UnsignedShort; 4424 LongWidth = LongAlign = 32; 4425 DoubleAlign = LongLongAlign = 64; 4426 IntMaxType = SignedLongLong; 4427 Int64Type = SignedLongLong; 4428 SizeType = UnsignedLongLong; 4429 PtrDiffType = SignedLongLong; 4430 IntPtrType = SignedLongLong; 4431 } 4432 4433 void getTargetDefines(const LangOptions &Opts, 4434 MacroBuilder &Builder) const override { 4435 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4436 Builder.defineMacro("_WIN64"); 4437 } 4438 4439 BuiltinVaListKind getBuiltinVaListKind() const override { 4440 return TargetInfo::CharPtrBuiltinVaList; 4441 } 4442 4443 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4444 switch (CC) { 4445 case CC_X86StdCall: 4446 case CC_X86ThisCall: 4447 case CC_X86FastCall: 4448 return CCCR_Ignore; 4449 case CC_C: 4450 case CC_X86VectorCall: 4451 case CC_IntelOclBicc: 4452 case CC_X86_64SysV: 4453 return CCCR_OK; 4454 default: 4455 return CCCR_Warning; 4456 } 4457 } 4458 }; 4459 4460 // x86-64 Windows Visual Studio target 4461 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4462 public: 4463 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4464 const TargetOptions &Opts) 4465 : WindowsX86_64TargetInfo(Triple, Opts) { 4466 LongDoubleWidth = LongDoubleAlign = 64; 4467 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4468 } 4469 void getTargetDefines(const LangOptions &Opts, 4470 MacroBuilder &Builder) const override { 4471 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4472 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4473 Builder.defineMacro("_M_X64", "100"); 4474 Builder.defineMacro("_M_AMD64", "100"); 4475 } 4476 }; 4477 4478 // x86-64 MinGW target 4479 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4480 public: 4481 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4482 : WindowsX86_64TargetInfo(Triple, Opts) { 4483 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4484 // with x86 FP ops. Weird. 4485 LongDoubleWidth = LongDoubleAlign = 128; 4486 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4487 } 4488 4489 void getTargetDefines(const LangOptions &Opts, 4490 MacroBuilder &Builder) const override { 4491 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4492 DefineStd(Builder, "WIN64", Opts); 4493 Builder.defineMacro("__MINGW64__"); 4494 addMinGWDefines(Opts, Builder); 4495 4496 // GCC defines this macro when it is using __gxx_personality_seh0. 4497 if (!Opts.SjLjExceptions) 4498 Builder.defineMacro("__SEH__"); 4499 } 4500 }; 4501 4502 // x86-64 Cygwin target 4503 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4504 public: 4505 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4506 : X86_64TargetInfo(Triple, Opts) { 4507 TLSSupported = false; 4508 WCharType = UnsignedShort; 4509 } 4510 void getTargetDefines(const LangOptions &Opts, 4511 MacroBuilder &Builder) const override { 4512 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4513 Builder.defineMacro("__x86_64__"); 4514 Builder.defineMacro("__CYGWIN__"); 4515 Builder.defineMacro("__CYGWIN64__"); 4516 addCygMingDefines(Opts, Builder); 4517 DefineStd(Builder, "unix", Opts); 4518 if (Opts.CPlusPlus) 4519 Builder.defineMacro("_GNU_SOURCE"); 4520 4521 // GCC defines this macro when it is using __gxx_personality_seh0. 4522 if (!Opts.SjLjExceptions) 4523 Builder.defineMacro("__SEH__"); 4524 } 4525 }; 4526 4527 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4528 public: 4529 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4530 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4531 Int64Type = SignedLongLong; 4532 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4533 llvm::Triple T = llvm::Triple(Triple); 4534 if (T.isiOS()) 4535 UseSignedCharForObjCBool = false; 4536 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4537 } 4538 4539 bool handleTargetFeatures(std::vector<std::string> &Features, 4540 DiagnosticsEngine &Diags) override { 4541 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4542 Diags)) 4543 return false; 4544 // We now know the features we have: we can decide how to align vectors. 4545 MaxVectorAlign = 4546 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4547 return true; 4548 } 4549 }; 4550 4551 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4552 public: 4553 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4554 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4555 IntMaxType = SignedLongLong; 4556 Int64Type = SignedLongLong; 4557 } 4558 }; 4559 4560 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4561 public: 4562 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4563 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4564 IntMaxType = SignedLongLong; 4565 Int64Type = SignedLongLong; 4566 } 4567 }; 4568 4569 class ARMTargetInfo : public TargetInfo { 4570 // Possible FPU choices. 4571 enum FPUMode { 4572 VFP2FPU = (1 << 0), 4573 VFP3FPU = (1 << 1), 4574 VFP4FPU = (1 << 2), 4575 NeonFPU = (1 << 3), 4576 FPARMV8 = (1 << 4) 4577 }; 4578 4579 // Possible HWDiv features. 4580 enum HWDivMode { 4581 HWDivThumb = (1 << 0), 4582 HWDivARM = (1 << 1) 4583 }; 4584 4585 static bool FPUModeIsVFP(FPUMode Mode) { 4586 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4587 } 4588 4589 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4590 static const char * const GCCRegNames[]; 4591 4592 std::string ABI, CPU; 4593 4594 StringRef CPUProfile; 4595 StringRef CPUAttr; 4596 4597 enum { 4598 FP_Default, 4599 FP_VFP, 4600 FP_Neon 4601 } FPMath; 4602 4603 unsigned ArchISA; 4604 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4605 unsigned ArchProfile; 4606 unsigned ArchVersion; 4607 4608 unsigned FPU : 5; 4609 4610 unsigned IsAAPCS : 1; 4611 unsigned HWDiv : 2; 4612 4613 // Initialized via features. 4614 unsigned SoftFloat : 1; 4615 unsigned SoftFloatABI : 1; 4616 4617 unsigned CRC : 1; 4618 unsigned Crypto : 1; 4619 unsigned DSP : 1; 4620 unsigned Unaligned : 1; 4621 4622 enum { 4623 LDREX_B = (1 << 0), /// byte (8-bit) 4624 LDREX_H = (1 << 1), /// half (16-bit) 4625 LDREX_W = (1 << 2), /// word (32-bit) 4626 LDREX_D = (1 << 3), /// double (64-bit) 4627 }; 4628 4629 uint32_t LDREX; 4630 4631 // ACLE 6.5.1 Hardware floating point 4632 enum { 4633 HW_FP_HP = (1 << 1), /// half (16-bit) 4634 HW_FP_SP = (1 << 2), /// single (32-bit) 4635 HW_FP_DP = (1 << 3), /// double (64-bit) 4636 }; 4637 uint32_t HW_FP; 4638 4639 static const Builtin::Info BuiltinInfo[]; 4640 4641 void setABIAAPCS() { 4642 IsAAPCS = true; 4643 4644 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4645 const llvm::Triple &T = getTriple(); 4646 4647 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4648 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4649 T.getOS() == llvm::Triple::Bitrig) 4650 SizeType = UnsignedLong; 4651 else 4652 SizeType = UnsignedInt; 4653 4654 switch (T.getOS()) { 4655 case llvm::Triple::NetBSD: 4656 WCharType = SignedInt; 4657 break; 4658 case llvm::Triple::Win32: 4659 WCharType = UnsignedShort; 4660 break; 4661 case llvm::Triple::Linux: 4662 default: 4663 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4664 WCharType = UnsignedInt; 4665 break; 4666 } 4667 4668 UseBitFieldTypeAlignment = true; 4669 4670 ZeroLengthBitfieldBoundary = 0; 4671 4672 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4673 // so set preferred for small types to 32. 4674 if (T.isOSBinFormatMachO()) { 4675 resetDataLayout(BigEndian 4676 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4677 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4678 } else if (T.isOSWindows()) { 4679 assert(!BigEndian && "Windows on ARM does not support big endian"); 4680 resetDataLayout("e" 4681 "-m:w" 4682 "-p:32:32" 4683 "-i64:64" 4684 "-v128:64:128" 4685 "-a:0:32" 4686 "-n32" 4687 "-S64"); 4688 } else if (T.isOSNaCl()) { 4689 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4690 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4691 } else { 4692 resetDataLayout(BigEndian 4693 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4694 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4695 } 4696 4697 // FIXME: Enumerated types are variable width in straight AAPCS. 4698 } 4699 4700 void setABIAPCS(bool IsAAPCS16) { 4701 const llvm::Triple &T = getTriple(); 4702 4703 IsAAPCS = false; 4704 4705 if (IsAAPCS16) 4706 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4707 else 4708 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4709 4710 // size_t is unsigned int on FreeBSD. 4711 if (T.getOS() == llvm::Triple::FreeBSD) 4712 SizeType = UnsignedInt; 4713 else 4714 SizeType = UnsignedLong; 4715 4716 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4717 WCharType = SignedInt; 4718 4719 // Do not respect the alignment of bit-field types when laying out 4720 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4721 UseBitFieldTypeAlignment = false; 4722 4723 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4724 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4725 /// gcc. 4726 ZeroLengthBitfieldBoundary = 32; 4727 4728 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4729 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4730 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4731 } else if (T.isOSBinFormatMachO()) 4732 resetDataLayout( 4733 BigEndian 4734 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4735 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4736 else 4737 resetDataLayout( 4738 BigEndian 4739 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4740 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4741 4742 // FIXME: Override "preferred align" for double and long long. 4743 } 4744 4745 void setArchInfo() { 4746 StringRef ArchName = getTriple().getArchName(); 4747 4748 ArchISA = llvm::ARM::parseArchISA(ArchName); 4749 CPU = llvm::ARM::getDefaultCPU(ArchName); 4750 unsigned AK = llvm::ARM::parseArch(ArchName); 4751 if (AK != llvm::ARM::AK_INVALID) 4752 ArchKind = AK; 4753 setArchInfo(ArchKind); 4754 } 4755 4756 void setArchInfo(unsigned Kind) { 4757 StringRef SubArch; 4758 4759 // cache TargetParser info 4760 ArchKind = Kind; 4761 SubArch = llvm::ARM::getSubArch(ArchKind); 4762 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4763 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4764 4765 // cache CPU related strings 4766 CPUAttr = getCPUAttr(); 4767 CPUProfile = getCPUProfile(); 4768 } 4769 4770 void setAtomic() { 4771 // when triple does not specify a sub arch, 4772 // then we are not using inline atomics 4773 bool ShouldUseInlineAtomic = 4774 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4775 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4776 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4777 if (ArchProfile == llvm::ARM::PK_M) { 4778 MaxAtomicPromoteWidth = 32; 4779 if (ShouldUseInlineAtomic) 4780 MaxAtomicInlineWidth = 32; 4781 } 4782 else { 4783 MaxAtomicPromoteWidth = 64; 4784 if (ShouldUseInlineAtomic) 4785 MaxAtomicInlineWidth = 64; 4786 } 4787 } 4788 4789 bool isThumb() const { 4790 return (ArchISA == llvm::ARM::IK_THUMB); 4791 } 4792 4793 bool supportsThumb() const { 4794 return CPUAttr.count('T') || ArchVersion >= 6; 4795 } 4796 4797 bool supportsThumb2() const { 4798 return CPUAttr.equals("6T2") || 4799 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4800 } 4801 4802 StringRef getCPUAttr() const { 4803 // For most sub-arches, the build attribute CPU name is enough. 4804 // For Cortex variants, it's slightly different. 4805 switch(ArchKind) { 4806 default: 4807 return llvm::ARM::getCPUAttr(ArchKind); 4808 case llvm::ARM::AK_ARMV6M: 4809 return "6M"; 4810 case llvm::ARM::AK_ARMV7S: 4811 return "7S"; 4812 case llvm::ARM::AK_ARMV7A: 4813 return "7A"; 4814 case llvm::ARM::AK_ARMV7R: 4815 return "7R"; 4816 case llvm::ARM::AK_ARMV7M: 4817 return "7M"; 4818 case llvm::ARM::AK_ARMV7EM: 4819 return "7EM"; 4820 case llvm::ARM::AK_ARMV8A: 4821 return "8A"; 4822 case llvm::ARM::AK_ARMV8_1A: 4823 return "8_1A"; 4824 case llvm::ARM::AK_ARMV8_2A: 4825 return "8_2A"; 4826 case llvm::ARM::AK_ARMV8MBaseline: 4827 return "8M_BASE"; 4828 case llvm::ARM::AK_ARMV8MMainline: 4829 return "8M_MAIN"; 4830 } 4831 } 4832 4833 StringRef getCPUProfile() const { 4834 switch(ArchProfile) { 4835 case llvm::ARM::PK_A: 4836 return "A"; 4837 case llvm::ARM::PK_R: 4838 return "R"; 4839 case llvm::ARM::PK_M: 4840 return "M"; 4841 default: 4842 return ""; 4843 } 4844 } 4845 4846 public: 4847 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 4848 bool IsBigEndian) 4849 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4850 HW_FP(0) { 4851 BigEndian = IsBigEndian; 4852 4853 switch (getTriple().getOS()) { 4854 case llvm::Triple::NetBSD: 4855 PtrDiffType = SignedLong; 4856 break; 4857 default: 4858 PtrDiffType = SignedInt; 4859 break; 4860 } 4861 4862 // Cache arch related info. 4863 setArchInfo(); 4864 4865 // {} in inline assembly are neon specifiers, not assembly variant 4866 // specifiers. 4867 NoAsmVariants = true; 4868 4869 // FIXME: This duplicates code from the driver that sets the -target-abi 4870 // option - this code is used if -target-abi isn't passed and should 4871 // be unified in some way. 4872 if (Triple.isOSBinFormatMachO()) { 4873 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4874 // the frontend matches that. 4875 if (Triple.getEnvironment() == llvm::Triple::EABI || 4876 Triple.getOS() == llvm::Triple::UnknownOS || 4877 StringRef(CPU).startswith("cortex-m")) { 4878 setABI("aapcs"); 4879 } else if (Triple.isWatchABI()) { 4880 setABI("aapcs16"); 4881 } else { 4882 setABI("apcs-gnu"); 4883 } 4884 } else if (Triple.isOSWindows()) { 4885 // FIXME: this is invalid for WindowsCE 4886 setABI("aapcs"); 4887 } else { 4888 // Select the default based on the platform. 4889 switch (Triple.getEnvironment()) { 4890 case llvm::Triple::Android: 4891 case llvm::Triple::GNUEABI: 4892 case llvm::Triple::GNUEABIHF: 4893 case llvm::Triple::MuslEABI: 4894 case llvm::Triple::MuslEABIHF: 4895 setABI("aapcs-linux"); 4896 break; 4897 case llvm::Triple::EABIHF: 4898 case llvm::Triple::EABI: 4899 setABI("aapcs"); 4900 break; 4901 case llvm::Triple::GNU: 4902 setABI("apcs-gnu"); 4903 break; 4904 default: 4905 if (Triple.getOS() == llvm::Triple::NetBSD) 4906 setABI("apcs-gnu"); 4907 else 4908 setABI("aapcs"); 4909 break; 4910 } 4911 } 4912 4913 // ARM targets default to using the ARM C++ ABI. 4914 TheCXXABI.set(TargetCXXABI::GenericARM); 4915 4916 // ARM has atomics up to 8 bytes 4917 setAtomic(); 4918 4919 // Do force alignment of members that follow zero length bitfields. If 4920 // the alignment of the zero-length bitfield is greater than the member 4921 // that follows it, `bar', `bar' will be aligned as the type of the 4922 // zero length bitfield. 4923 UseZeroLengthBitfieldAlignment = true; 4924 4925 if (Triple.getOS() == llvm::Triple::Linux || 4926 Triple.getOS() == llvm::Triple::UnknownOS) 4927 this->MCountName = 4928 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 4929 } 4930 4931 StringRef getABI() const override { return ABI; } 4932 4933 bool setABI(const std::string &Name) override { 4934 ABI = Name; 4935 4936 // The defaults (above) are for AAPCS, check if we need to change them. 4937 // 4938 // FIXME: We need support for -meabi... we could just mangle it into the 4939 // name. 4940 if (Name == "apcs-gnu" || Name == "aapcs16") { 4941 setABIAPCS(Name == "aapcs16"); 4942 return true; 4943 } 4944 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4945 setABIAAPCS(); 4946 return true; 4947 } 4948 return false; 4949 } 4950 4951 // FIXME: This should be based on Arch attributes, not CPU names. 4952 bool 4953 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4954 StringRef CPU, 4955 const std::vector<std::string> &FeaturesVec) const override { 4956 4957 std::vector<const char*> TargetFeatures; 4958 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4959 4960 // get default FPU features 4961 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4962 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4963 4964 // get default Extension features 4965 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4966 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4967 4968 for (const char *Feature : TargetFeatures) 4969 if (Feature[0] == '+') 4970 Features[Feature+1] = true; 4971 4972 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4973 } 4974 4975 bool handleTargetFeatures(std::vector<std::string> &Features, 4976 DiagnosticsEngine &Diags) override { 4977 FPU = 0; 4978 CRC = 0; 4979 Crypto = 0; 4980 DSP = 0; 4981 Unaligned = 1; 4982 SoftFloat = SoftFloatABI = false; 4983 HWDiv = 0; 4984 4985 // This does not diagnose illegal cases like having both 4986 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4987 uint32_t HW_FP_remove = 0; 4988 for (const auto &Feature : Features) { 4989 if (Feature == "+soft-float") { 4990 SoftFloat = true; 4991 } else if (Feature == "+soft-float-abi") { 4992 SoftFloatABI = true; 4993 } else if (Feature == "+vfp2") { 4994 FPU |= VFP2FPU; 4995 HW_FP |= HW_FP_SP | HW_FP_DP; 4996 } else if (Feature == "+vfp3") { 4997 FPU |= VFP3FPU; 4998 HW_FP |= HW_FP_SP | HW_FP_DP; 4999 } else if (Feature == "+vfp4") { 5000 FPU |= VFP4FPU; 5001 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5002 } else if (Feature == "+fp-armv8") { 5003 FPU |= FPARMV8; 5004 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5005 } else if (Feature == "+neon") { 5006 FPU |= NeonFPU; 5007 HW_FP |= HW_FP_SP | HW_FP_DP; 5008 } else if (Feature == "+hwdiv") { 5009 HWDiv |= HWDivThumb; 5010 } else if (Feature == "+hwdiv-arm") { 5011 HWDiv |= HWDivARM; 5012 } else if (Feature == "+crc") { 5013 CRC = 1; 5014 } else if (Feature == "+crypto") { 5015 Crypto = 1; 5016 } else if (Feature == "+dsp") { 5017 DSP = 1; 5018 } else if (Feature == "+fp-only-sp") { 5019 HW_FP_remove |= HW_FP_DP; 5020 } else if (Feature == "+strict-align") { 5021 Unaligned = 0; 5022 } else if (Feature == "+fp16") { 5023 HW_FP |= HW_FP_HP; 5024 } 5025 } 5026 HW_FP &= ~HW_FP_remove; 5027 5028 switch (ArchVersion) { 5029 case 6: 5030 if (ArchProfile == llvm::ARM::PK_M) 5031 LDREX = 0; 5032 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5033 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5034 else 5035 LDREX = LDREX_W; 5036 break; 5037 case 7: 5038 if (ArchProfile == llvm::ARM::PK_M) 5039 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5040 else 5041 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5042 break; 5043 case 8: 5044 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5045 } 5046 5047 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5048 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5049 return false; 5050 } 5051 5052 if (FPMath == FP_Neon) 5053 Features.push_back("+neonfp"); 5054 else if (FPMath == FP_VFP) 5055 Features.push_back("-neonfp"); 5056 5057 // Remove front-end specific options which the backend handles differently. 5058 auto Feature = 5059 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5060 if (Feature != Features.end()) 5061 Features.erase(Feature); 5062 5063 return true; 5064 } 5065 5066 bool hasFeature(StringRef Feature) const override { 5067 return llvm::StringSwitch<bool>(Feature) 5068 .Case("arm", true) 5069 .Case("aarch32", true) 5070 .Case("softfloat", SoftFloat) 5071 .Case("thumb", isThumb()) 5072 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5073 .Case("hwdiv", HWDiv & HWDivThumb) 5074 .Case("hwdiv-arm", HWDiv & HWDivARM) 5075 .Default(false); 5076 } 5077 5078 bool setCPU(const std::string &Name) override { 5079 if (Name != "generic") 5080 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5081 5082 if (ArchKind == llvm::ARM::AK_INVALID) 5083 return false; 5084 setAtomic(); 5085 CPU = Name; 5086 return true; 5087 } 5088 5089 bool setFPMath(StringRef Name) override; 5090 5091 void getTargetDefines(const LangOptions &Opts, 5092 MacroBuilder &Builder) const override { 5093 // Target identification. 5094 Builder.defineMacro("__arm"); 5095 Builder.defineMacro("__arm__"); 5096 // For bare-metal none-eabi. 5097 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5098 getTriple().getEnvironment() == llvm::Triple::EABI) 5099 Builder.defineMacro("__ELF__"); 5100 5101 // Target properties. 5102 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5103 5104 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5105 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5106 if (getTriple().isWatchABI()) 5107 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5108 5109 if (!CPUAttr.empty()) 5110 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5111 5112 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5113 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5114 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5115 5116 if (ArchVersion >= 8) { 5117 // ACLE 6.5.7 Crypto Extension 5118 if (Crypto) 5119 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5120 // ACLE 6.5.8 CRC32 Extension 5121 if (CRC) 5122 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5123 // ACLE 6.5.10 Numeric Maximum and Minimum 5124 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5125 // ACLE 6.5.9 Directed Rounding 5126 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5127 } 5128 5129 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5130 // is not defined for the M-profile. 5131 // NOTE that the default profile is assumed to be 'A' 5132 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5133 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5134 5135 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5136 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5137 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5138 // v7 and v8 architectures excluding v8-M Baseline. 5139 if (supportsThumb2()) 5140 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5141 else if (supportsThumb()) 5142 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5143 5144 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5145 // instruction set such as ARM or Thumb. 5146 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5147 5148 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5149 5150 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5151 if (!CPUProfile.empty()) 5152 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5153 5154 // ACLE 6.4.3 Unaligned access supported in hardware 5155 if (Unaligned) 5156 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5157 5158 // ACLE 6.4.4 LDREX/STREX 5159 if (LDREX) 5160 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5161 5162 // ACLE 6.4.5 CLZ 5163 if (ArchVersion == 5 || 5164 (ArchVersion == 6 && CPUProfile != "M") || 5165 ArchVersion > 6) 5166 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5167 5168 // ACLE 6.5.1 Hardware Floating Point 5169 if (HW_FP) 5170 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5171 5172 // ACLE predefines. 5173 Builder.defineMacro("__ARM_ACLE", "200"); 5174 5175 // FP16 support (we currently only support IEEE format). 5176 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5177 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5178 5179 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5180 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5181 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5182 5183 // Subtarget options. 5184 5185 // FIXME: It's more complicated than this and we don't really support 5186 // interworking. 5187 // Windows on ARM does not "support" interworking 5188 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5189 Builder.defineMacro("__THUMB_INTERWORK__"); 5190 5191 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5192 // Embedded targets on Darwin follow AAPCS, but not EABI. 5193 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5194 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5195 Builder.defineMacro("__ARM_EABI__"); 5196 Builder.defineMacro("__ARM_PCS", "1"); 5197 } 5198 5199 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5200 ABI == "aapcs16") 5201 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5202 5203 if (SoftFloat) 5204 Builder.defineMacro("__SOFTFP__"); 5205 5206 if (CPU == "xscale") 5207 Builder.defineMacro("__XSCALE__"); 5208 5209 if (isThumb()) { 5210 Builder.defineMacro("__THUMBEL__"); 5211 Builder.defineMacro("__thumb__"); 5212 if (supportsThumb2()) 5213 Builder.defineMacro("__thumb2__"); 5214 } 5215 5216 // ACLE 6.4.9 32-bit SIMD instructions 5217 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5218 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5219 5220 // ACLE 6.4.10 Hardware Integer Divide 5221 if (((HWDiv & HWDivThumb) && isThumb()) || 5222 ((HWDiv & HWDivARM) && !isThumb())) { 5223 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5224 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5225 } 5226 5227 // Note, this is always on in gcc, even though it doesn't make sense. 5228 Builder.defineMacro("__APCS_32__"); 5229 5230 if (FPUModeIsVFP((FPUMode) FPU)) { 5231 Builder.defineMacro("__VFP_FP__"); 5232 if (FPU & VFP2FPU) 5233 Builder.defineMacro("__ARM_VFPV2__"); 5234 if (FPU & VFP3FPU) 5235 Builder.defineMacro("__ARM_VFPV3__"); 5236 if (FPU & VFP4FPU) 5237 Builder.defineMacro("__ARM_VFPV4__"); 5238 } 5239 5240 // This only gets set when Neon instructions are actually available, unlike 5241 // the VFP define, hence the soft float and arch check. This is subtly 5242 // different from gcc, we follow the intent which was that it should be set 5243 // when Neon instructions are actually available. 5244 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5245 Builder.defineMacro("__ARM_NEON", "1"); 5246 Builder.defineMacro("__ARM_NEON__"); 5247 // current AArch32 NEON implementations do not support double-precision 5248 // floating-point even when it is present in VFP. 5249 Builder.defineMacro("__ARM_NEON_FP", 5250 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5251 } 5252 5253 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5254 Opts.ShortWChar ? "2" : "4"); 5255 5256 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5257 Opts.ShortEnums ? "1" : "4"); 5258 5259 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5260 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5261 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5262 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5263 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5264 } 5265 5266 // ACLE 6.4.7 DSP instructions 5267 if (DSP) { 5268 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5269 } 5270 5271 // ACLE 6.4.8 Saturation instructions 5272 bool SAT = false; 5273 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5274 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5275 SAT = true; 5276 } 5277 5278 // ACLE 6.4.6 Q (saturation) flag 5279 if (DSP || SAT) 5280 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5281 5282 if (Opts.UnsafeFPMath) 5283 Builder.defineMacro("__ARM_FP_FAST", "1"); 5284 5285 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5286 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5287 } 5288 5289 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5290 return llvm::makeArrayRef(BuiltinInfo, 5291 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5292 } 5293 bool isCLZForZeroUndef() const override { return false; } 5294 BuiltinVaListKind getBuiltinVaListKind() const override { 5295 return IsAAPCS 5296 ? AAPCSABIBuiltinVaList 5297 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5298 : TargetInfo::VoidPtrBuiltinVaList); 5299 } 5300 ArrayRef<const char *> getGCCRegNames() const override; 5301 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5302 bool validateAsmConstraint(const char *&Name, 5303 TargetInfo::ConstraintInfo &Info) const override { 5304 switch (*Name) { 5305 default: break; 5306 case 'l': // r0-r7 5307 case 'h': // r8-r15 5308 case 't': // VFP Floating point register single precision 5309 case 'w': // VFP Floating point register double precision 5310 Info.setAllowsRegister(); 5311 return true; 5312 case 'I': 5313 case 'J': 5314 case 'K': 5315 case 'L': 5316 case 'M': 5317 // FIXME 5318 return true; 5319 case 'Q': // A memory address that is a single base register. 5320 Info.setAllowsMemory(); 5321 return true; 5322 case 'U': // a memory reference... 5323 switch (Name[1]) { 5324 case 'q': // ...ARMV4 ldrsb 5325 case 'v': // ...VFP load/store (reg+constant offset) 5326 case 'y': // ...iWMMXt load/store 5327 case 't': // address valid for load/store opaque types wider 5328 // than 128-bits 5329 case 'n': // valid address for Neon doubleword vector load/store 5330 case 'm': // valid address for Neon element and structure load/store 5331 case 's': // valid address for non-offset loads/stores of quad-word 5332 // values in four ARM registers 5333 Info.setAllowsMemory(); 5334 Name++; 5335 return true; 5336 } 5337 } 5338 return false; 5339 } 5340 std::string convertConstraint(const char *&Constraint) const override { 5341 std::string R; 5342 switch (*Constraint) { 5343 case 'U': // Two-character constraint; add "^" hint for later parsing. 5344 R = std::string("^") + std::string(Constraint, 2); 5345 Constraint++; 5346 break; 5347 case 'p': // 'p' should be translated to 'r' by default. 5348 R = std::string("r"); 5349 break; 5350 default: 5351 return std::string(1, *Constraint); 5352 } 5353 return R; 5354 } 5355 bool 5356 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5357 std::string &SuggestedModifier) const override { 5358 bool isOutput = (Constraint[0] == '='); 5359 bool isInOut = (Constraint[0] == '+'); 5360 5361 // Strip off constraint modifiers. 5362 while (Constraint[0] == '=' || 5363 Constraint[0] == '+' || 5364 Constraint[0] == '&') 5365 Constraint = Constraint.substr(1); 5366 5367 switch (Constraint[0]) { 5368 default: break; 5369 case 'r': { 5370 switch (Modifier) { 5371 default: 5372 return (isInOut || isOutput || Size <= 64); 5373 case 'q': 5374 // A register of size 32 cannot fit a vector type. 5375 return false; 5376 } 5377 } 5378 } 5379 5380 return true; 5381 } 5382 const char *getClobbers() const override { 5383 // FIXME: Is this really right? 5384 return ""; 5385 } 5386 5387 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5388 switch (CC) { 5389 case CC_AAPCS: 5390 case CC_AAPCS_VFP: 5391 case CC_Swift: 5392 return CCCR_OK; 5393 default: 5394 return CCCR_Warning; 5395 } 5396 } 5397 5398 int getEHDataRegisterNumber(unsigned RegNo) const override { 5399 if (RegNo == 0) return 0; 5400 if (RegNo == 1) return 1; 5401 return -1; 5402 } 5403 5404 bool hasSjLjLowering() const override { 5405 return true; 5406 } 5407 }; 5408 5409 bool ARMTargetInfo::setFPMath(StringRef Name) { 5410 if (Name == "neon") { 5411 FPMath = FP_Neon; 5412 return true; 5413 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5414 Name == "vfp4") { 5415 FPMath = FP_VFP; 5416 return true; 5417 } 5418 return false; 5419 } 5420 5421 const char * const ARMTargetInfo::GCCRegNames[] = { 5422 // Integer registers 5423 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5424 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5425 5426 // Float registers 5427 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5428 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5429 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5430 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5431 5432 // Double registers 5433 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5434 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5435 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5436 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5437 5438 // Quad registers 5439 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5440 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5441 }; 5442 5443 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5444 return llvm::makeArrayRef(GCCRegNames); 5445 } 5446 5447 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5448 { { "a1" }, "r0" }, 5449 { { "a2" }, "r1" }, 5450 { { "a3" }, "r2" }, 5451 { { "a4" }, "r3" }, 5452 { { "v1" }, "r4" }, 5453 { { "v2" }, "r5" }, 5454 { { "v3" }, "r6" }, 5455 { { "v4" }, "r7" }, 5456 { { "v5" }, "r8" }, 5457 { { "v6", "rfp" }, "r9" }, 5458 { { "sl" }, "r10" }, 5459 { { "fp" }, "r11" }, 5460 { { "ip" }, "r12" }, 5461 { { "r13" }, "sp" }, 5462 { { "r14" }, "lr" }, 5463 { { "r15" }, "pc" }, 5464 // The S, D and Q registers overlap, but aren't really aliases; we 5465 // don't want to substitute one of these for a different-sized one. 5466 }; 5467 5468 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5469 return llvm::makeArrayRef(GCCRegAliases); 5470 } 5471 5472 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5473 #define BUILTIN(ID, TYPE, ATTRS) \ 5474 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5475 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5476 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5477 #include "clang/Basic/BuiltinsNEON.def" 5478 5479 #define BUILTIN(ID, TYPE, ATTRS) \ 5480 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5481 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5482 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5483 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5484 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5485 #include "clang/Basic/BuiltinsARM.def" 5486 }; 5487 5488 class ARMleTargetInfo : public ARMTargetInfo { 5489 public: 5490 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5491 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/false) {} 5492 void getTargetDefines(const LangOptions &Opts, 5493 MacroBuilder &Builder) const override { 5494 Builder.defineMacro("__ARMEL__"); 5495 ARMTargetInfo::getTargetDefines(Opts, Builder); 5496 } 5497 }; 5498 5499 class ARMbeTargetInfo : public ARMTargetInfo { 5500 public: 5501 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5502 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/true) {} 5503 void getTargetDefines(const LangOptions &Opts, 5504 MacroBuilder &Builder) const override { 5505 Builder.defineMacro("__ARMEB__"); 5506 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5507 ARMTargetInfo::getTargetDefines(Opts, Builder); 5508 } 5509 }; 5510 5511 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5512 const llvm::Triple Triple; 5513 public: 5514 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5515 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5516 WCharType = UnsignedShort; 5517 SizeType = UnsignedInt; 5518 } 5519 void getVisualStudioDefines(const LangOptions &Opts, 5520 MacroBuilder &Builder) const { 5521 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5522 5523 // FIXME: this is invalid for WindowsCE 5524 Builder.defineMacro("_M_ARM_NT", "1"); 5525 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5526 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5527 5528 assert((Triple.getArch() == llvm::Triple::arm || 5529 Triple.getArch() == llvm::Triple::thumb) && 5530 "invalid architecture for Windows ARM target info"); 5531 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5532 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5533 5534 // TODO map the complete set of values 5535 // 31: VFPv3 40: VFPv4 5536 Builder.defineMacro("_M_ARM_FP", "31"); 5537 } 5538 BuiltinVaListKind getBuiltinVaListKind() const override { 5539 return TargetInfo::CharPtrBuiltinVaList; 5540 } 5541 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5542 switch (CC) { 5543 case CC_X86StdCall: 5544 case CC_X86ThisCall: 5545 case CC_X86FastCall: 5546 case CC_X86VectorCall: 5547 return CCCR_Ignore; 5548 case CC_C: 5549 return CCCR_OK; 5550 default: 5551 return CCCR_Warning; 5552 } 5553 } 5554 }; 5555 5556 // Windows ARM + Itanium C++ ABI Target 5557 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5558 public: 5559 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5560 const TargetOptions &Opts) 5561 : WindowsARMTargetInfo(Triple, Opts) { 5562 TheCXXABI.set(TargetCXXABI::GenericARM); 5563 } 5564 5565 void getTargetDefines(const LangOptions &Opts, 5566 MacroBuilder &Builder) const override { 5567 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5568 5569 if (Opts.MSVCCompat) 5570 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5571 } 5572 }; 5573 5574 // Windows ARM, MS (C++) ABI 5575 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5576 public: 5577 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5578 const TargetOptions &Opts) 5579 : WindowsARMTargetInfo(Triple, Opts) { 5580 TheCXXABI.set(TargetCXXABI::Microsoft); 5581 } 5582 5583 void getTargetDefines(const LangOptions &Opts, 5584 MacroBuilder &Builder) const override { 5585 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5586 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5587 } 5588 }; 5589 5590 // ARM MinGW target 5591 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5592 public: 5593 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5594 : WindowsARMTargetInfo(Triple, Opts) { 5595 TheCXXABI.set(TargetCXXABI::GenericARM); 5596 } 5597 5598 void getTargetDefines(const LangOptions &Opts, 5599 MacroBuilder &Builder) const override { 5600 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5601 DefineStd(Builder, "WIN32", Opts); 5602 DefineStd(Builder, "WINNT", Opts); 5603 Builder.defineMacro("_ARM_"); 5604 addMinGWDefines(Opts, Builder); 5605 } 5606 }; 5607 5608 // ARM Cygwin target 5609 class CygwinARMTargetInfo : public ARMleTargetInfo { 5610 public: 5611 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5612 : ARMleTargetInfo(Triple, Opts) { 5613 TLSSupported = false; 5614 WCharType = UnsignedShort; 5615 DoubleAlign = LongLongAlign = 64; 5616 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5617 } 5618 void getTargetDefines(const LangOptions &Opts, 5619 MacroBuilder &Builder) const override { 5620 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5621 Builder.defineMacro("_ARM_"); 5622 Builder.defineMacro("__CYGWIN__"); 5623 Builder.defineMacro("__CYGWIN32__"); 5624 DefineStd(Builder, "unix", Opts); 5625 if (Opts.CPlusPlus) 5626 Builder.defineMacro("_GNU_SOURCE"); 5627 } 5628 }; 5629 5630 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5631 protected: 5632 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5633 MacroBuilder &Builder) const override { 5634 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5635 } 5636 5637 public: 5638 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5639 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5640 HasAlignMac68kSupport = true; 5641 // iOS always has 64-bit atomic instructions. 5642 // FIXME: This should be based off of the target features in 5643 // ARMleTargetInfo. 5644 MaxAtomicInlineWidth = 64; 5645 5646 if (Triple.isWatchABI()) { 5647 // Darwin on iOS uses a variant of the ARM C++ ABI. 5648 TheCXXABI.set(TargetCXXABI::WatchOS); 5649 5650 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5651 // size_t is long, it's a bit weird for it to be int. 5652 PtrDiffType = SignedLong; 5653 5654 // BOOL should be a real boolean on the new ABI 5655 UseSignedCharForObjCBool = false; 5656 } else 5657 TheCXXABI.set(TargetCXXABI::iOS); 5658 } 5659 }; 5660 5661 class AArch64TargetInfo : public TargetInfo { 5662 virtual void setDataLayout() = 0; 5663 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5664 static const char *const GCCRegNames[]; 5665 5666 enum FPUModeEnum { 5667 FPUMode, 5668 NeonMode 5669 }; 5670 5671 unsigned FPU; 5672 unsigned CRC; 5673 unsigned Crypto; 5674 unsigned Unaligned; 5675 unsigned V8_1A; 5676 5677 static const Builtin::Info BuiltinInfo[]; 5678 5679 std::string ABI; 5680 5681 public: 5682 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5683 : TargetInfo(Triple), ABI("aapcs") { 5684 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5685 WCharType = SignedInt; 5686 5687 // NetBSD apparently prefers consistency across ARM targets to consistency 5688 // across 64-bit targets. 5689 Int64Type = SignedLongLong; 5690 IntMaxType = SignedLongLong; 5691 } else { 5692 WCharType = UnsignedInt; 5693 Int64Type = SignedLong; 5694 IntMaxType = SignedLong; 5695 } 5696 5697 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5698 MaxVectorAlign = 128; 5699 MaxAtomicInlineWidth = 128; 5700 MaxAtomicPromoteWidth = 128; 5701 5702 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5703 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5704 5705 // {} in inline assembly are neon specifiers, not assembly variant 5706 // specifiers. 5707 NoAsmVariants = true; 5708 5709 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5710 // contributes to the alignment of the containing aggregate in the same way 5711 // a plain (non bit-field) member of that type would, without exception for 5712 // zero-sized or anonymous bit-fields." 5713 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5714 UseZeroLengthBitfieldAlignment = true; 5715 5716 // AArch64 targets default to using the ARM C++ ABI. 5717 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5718 5719 if (Triple.getOS() == llvm::Triple::Linux || 5720 Triple.getOS() == llvm::Triple::UnknownOS) 5721 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5722 } 5723 5724 StringRef getABI() const override { return ABI; } 5725 bool setABI(const std::string &Name) override { 5726 if (Name != "aapcs" && Name != "darwinpcs") 5727 return false; 5728 5729 ABI = Name; 5730 return true; 5731 } 5732 5733 bool setCPU(const std::string &Name) override { 5734 return Name == "generic" || 5735 llvm::AArch64::parseCPUArch(Name) != 5736 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 5737 } 5738 5739 void getTargetDefines(const LangOptions &Opts, 5740 MacroBuilder &Builder) const override { 5741 // Target identification. 5742 Builder.defineMacro("__aarch64__"); 5743 5744 // Target properties. 5745 Builder.defineMacro("_LP64"); 5746 Builder.defineMacro("__LP64__"); 5747 5748 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5749 Builder.defineMacro("__ARM_ACLE", "200"); 5750 Builder.defineMacro("__ARM_ARCH", "8"); 5751 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5752 5753 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5754 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5755 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5756 5757 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5758 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5759 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5760 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5761 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5762 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5763 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5764 5765 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5766 5767 // 0xe implies support for half, single and double precision operations. 5768 Builder.defineMacro("__ARM_FP", "0xE"); 5769 5770 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5771 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5772 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5773 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5774 5775 if (Opts.UnsafeFPMath) 5776 Builder.defineMacro("__ARM_FP_FAST", "1"); 5777 5778 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5779 5780 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5781 Opts.ShortEnums ? "1" : "4"); 5782 5783 if (FPU == NeonMode) { 5784 Builder.defineMacro("__ARM_NEON", "1"); 5785 // 64-bit NEON supports half, single and double precision operations. 5786 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5787 } 5788 5789 if (CRC) 5790 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5791 5792 if (Crypto) 5793 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5794 5795 if (Unaligned) 5796 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5797 5798 if (V8_1A) 5799 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5800 5801 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5802 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5803 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5804 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5805 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5806 } 5807 5808 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5809 return llvm::makeArrayRef(BuiltinInfo, 5810 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5811 } 5812 5813 bool hasFeature(StringRef Feature) const override { 5814 return Feature == "aarch64" || 5815 Feature == "arm64" || 5816 Feature == "arm" || 5817 (Feature == "neon" && FPU == NeonMode); 5818 } 5819 5820 bool handleTargetFeatures(std::vector<std::string> &Features, 5821 DiagnosticsEngine &Diags) override { 5822 FPU = FPUMode; 5823 CRC = 0; 5824 Crypto = 0; 5825 Unaligned = 1; 5826 V8_1A = 0; 5827 5828 for (const auto &Feature : Features) { 5829 if (Feature == "+neon") 5830 FPU = NeonMode; 5831 if (Feature == "+crc") 5832 CRC = 1; 5833 if (Feature == "+crypto") 5834 Crypto = 1; 5835 if (Feature == "+strict-align") 5836 Unaligned = 0; 5837 if (Feature == "+v8.1a") 5838 V8_1A = 1; 5839 } 5840 5841 setDataLayout(); 5842 5843 return true; 5844 } 5845 5846 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5847 switch (CC) { 5848 case CC_C: 5849 case CC_Swift: 5850 case CC_PreserveMost: 5851 case CC_PreserveAll: 5852 return CCCR_OK; 5853 default: 5854 return CCCR_Warning; 5855 } 5856 } 5857 5858 bool isCLZForZeroUndef() const override { return false; } 5859 5860 BuiltinVaListKind getBuiltinVaListKind() const override { 5861 return TargetInfo::AArch64ABIBuiltinVaList; 5862 } 5863 5864 ArrayRef<const char *> getGCCRegNames() const override; 5865 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5866 5867 bool validateAsmConstraint(const char *&Name, 5868 TargetInfo::ConstraintInfo &Info) const override { 5869 switch (*Name) { 5870 default: 5871 return false; 5872 case 'w': // Floating point and SIMD registers (V0-V31) 5873 Info.setAllowsRegister(); 5874 return true; 5875 case 'I': // Constant that can be used with an ADD instruction 5876 case 'J': // Constant that can be used with a SUB instruction 5877 case 'K': // Constant that can be used with a 32-bit logical instruction 5878 case 'L': // Constant that can be used with a 64-bit logical instruction 5879 case 'M': // Constant that can be used as a 32-bit MOV immediate 5880 case 'N': // Constant that can be used as a 64-bit MOV immediate 5881 case 'Y': // Floating point constant zero 5882 case 'Z': // Integer constant zero 5883 return true; 5884 case 'Q': // A memory reference with base register and no offset 5885 Info.setAllowsMemory(); 5886 return true; 5887 case 'S': // A symbolic address 5888 Info.setAllowsRegister(); 5889 return true; 5890 case 'U': 5891 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5892 // Utf: A memory address suitable for ldp/stp in TF mode. 5893 // Usa: An absolute symbolic address. 5894 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5895 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5896 case 'z': // Zero register, wzr or xzr 5897 Info.setAllowsRegister(); 5898 return true; 5899 case 'x': // Floating point and SIMD registers (V0-V15) 5900 Info.setAllowsRegister(); 5901 return true; 5902 } 5903 return false; 5904 } 5905 5906 bool 5907 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5908 std::string &SuggestedModifier) const override { 5909 // Strip off constraint modifiers. 5910 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5911 Constraint = Constraint.substr(1); 5912 5913 switch (Constraint[0]) { 5914 default: 5915 return true; 5916 case 'z': 5917 case 'r': { 5918 switch (Modifier) { 5919 case 'x': 5920 case 'w': 5921 // For now assume that the person knows what they're 5922 // doing with the modifier. 5923 return true; 5924 default: 5925 // By default an 'r' constraint will be in the 'x' 5926 // registers. 5927 if (Size == 64) 5928 return true; 5929 5930 SuggestedModifier = "w"; 5931 return false; 5932 } 5933 } 5934 } 5935 } 5936 5937 const char *getClobbers() const override { return ""; } 5938 5939 int getEHDataRegisterNumber(unsigned RegNo) const override { 5940 if (RegNo == 0) 5941 return 0; 5942 if (RegNo == 1) 5943 return 1; 5944 return -1; 5945 } 5946 }; 5947 5948 const char *const AArch64TargetInfo::GCCRegNames[] = { 5949 // 32-bit Integer registers 5950 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5951 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5952 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5953 5954 // 64-bit Integer registers 5955 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5956 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5957 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5958 5959 // 32-bit floating point regsisters 5960 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5961 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5962 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5963 5964 // 64-bit floating point regsisters 5965 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5966 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5967 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5968 5969 // Vector registers 5970 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5971 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5972 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5973 }; 5974 5975 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5976 return llvm::makeArrayRef(GCCRegNames); 5977 } 5978 5979 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5980 { { "w31" }, "wsp" }, 5981 { { "x29" }, "fp" }, 5982 { { "x30" }, "lr" }, 5983 { { "x31" }, "sp" }, 5984 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5985 // don't want to substitute one of these for a different-sized one. 5986 }; 5987 5988 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5989 return llvm::makeArrayRef(GCCRegAliases); 5990 } 5991 5992 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5993 #define BUILTIN(ID, TYPE, ATTRS) \ 5994 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5995 #include "clang/Basic/BuiltinsNEON.def" 5996 5997 #define BUILTIN(ID, TYPE, ATTRS) \ 5998 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5999 #include "clang/Basic/BuiltinsAArch64.def" 6000 }; 6001 6002 class AArch64leTargetInfo : public AArch64TargetInfo { 6003 void setDataLayout() override { 6004 if (getTriple().isOSBinFormatMachO()) 6005 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6006 else 6007 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6008 } 6009 6010 public: 6011 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6012 : AArch64TargetInfo(Triple, Opts) { 6013 BigEndian = false; 6014 } 6015 void getTargetDefines(const LangOptions &Opts, 6016 MacroBuilder &Builder) const override { 6017 Builder.defineMacro("__AARCH64EL__"); 6018 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6019 } 6020 }; 6021 6022 class AArch64beTargetInfo : public AArch64TargetInfo { 6023 void setDataLayout() override { 6024 assert(!getTriple().isOSBinFormatMachO()); 6025 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6026 } 6027 6028 public: 6029 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6030 : AArch64TargetInfo(Triple, Opts) {} 6031 void getTargetDefines(const LangOptions &Opts, 6032 MacroBuilder &Builder) const override { 6033 Builder.defineMacro("__AARCH64EB__"); 6034 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6035 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6036 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6037 } 6038 }; 6039 6040 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6041 protected: 6042 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6043 MacroBuilder &Builder) const override { 6044 Builder.defineMacro("__AARCH64_SIMD__"); 6045 Builder.defineMacro("__ARM64_ARCH_8__"); 6046 Builder.defineMacro("__ARM_NEON__"); 6047 Builder.defineMacro("__LITTLE_ENDIAN__"); 6048 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6049 Builder.defineMacro("__arm64", "1"); 6050 Builder.defineMacro("__arm64__", "1"); 6051 6052 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6053 } 6054 6055 public: 6056 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6057 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6058 Int64Type = SignedLongLong; 6059 WCharType = SignedInt; 6060 UseSignedCharForObjCBool = false; 6061 6062 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6063 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6064 6065 TheCXXABI.set(TargetCXXABI::iOS64); 6066 } 6067 6068 BuiltinVaListKind getBuiltinVaListKind() const override { 6069 return TargetInfo::CharPtrBuiltinVaList; 6070 } 6071 }; 6072 6073 // Hexagon abstract base class 6074 class HexagonTargetInfo : public TargetInfo { 6075 static const Builtin::Info BuiltinInfo[]; 6076 static const char * const GCCRegNames[]; 6077 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6078 std::string CPU; 6079 bool HasHVX, HasHVXDouble; 6080 6081 public: 6082 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6083 : TargetInfo(Triple) { 6084 BigEndian = false; 6085 // Specify the vector alignment explicitly. For v512x1, the calculated 6086 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6087 // the required minimum of 64 bytes. 6088 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6089 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6090 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6091 SizeType = UnsignedInt; 6092 PtrDiffType = SignedInt; 6093 IntPtrType = SignedInt; 6094 6095 // {} in inline assembly are packet specifiers, not assembly variant 6096 // specifiers. 6097 NoAsmVariants = true; 6098 6099 LargeArrayMinWidth = 64; 6100 LargeArrayAlign = 64; 6101 UseBitFieldTypeAlignment = true; 6102 ZeroLengthBitfieldBoundary = 32; 6103 HasHVX = HasHVXDouble = false; 6104 } 6105 6106 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6107 return llvm::makeArrayRef(BuiltinInfo, 6108 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6109 } 6110 6111 bool validateAsmConstraint(const char *&Name, 6112 TargetInfo::ConstraintInfo &Info) const override { 6113 switch (*Name) { 6114 case 'v': 6115 case 'q': 6116 if (HasHVX) { 6117 Info.setAllowsRegister(); 6118 return true; 6119 } 6120 break; 6121 case 's': 6122 // Relocatable constant. 6123 return true; 6124 } 6125 return false; 6126 } 6127 6128 void getTargetDefines(const LangOptions &Opts, 6129 MacroBuilder &Builder) const override; 6130 6131 bool isCLZForZeroUndef() const override { return false; } 6132 6133 bool hasFeature(StringRef Feature) const override { 6134 return llvm::StringSwitch<bool>(Feature) 6135 .Case("hexagon", true) 6136 .Case("hvx", HasHVX) 6137 .Case("hvx-double", HasHVXDouble) 6138 .Default(false); 6139 } 6140 6141 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6142 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6143 const override; 6144 6145 bool handleTargetFeatures(std::vector<std::string> &Features, 6146 DiagnosticsEngine &Diags) override; 6147 6148 BuiltinVaListKind getBuiltinVaListKind() const override { 6149 return TargetInfo::CharPtrBuiltinVaList; 6150 } 6151 ArrayRef<const char *> getGCCRegNames() const override; 6152 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6153 const char *getClobbers() const override { 6154 return ""; 6155 } 6156 6157 static const char *getHexagonCPUSuffix(StringRef Name) { 6158 return llvm::StringSwitch<const char*>(Name) 6159 .Case("hexagonv4", "4") 6160 .Case("hexagonv5", "5") 6161 .Case("hexagonv55", "55") 6162 .Case("hexagonv60", "60") 6163 .Default(nullptr); 6164 } 6165 6166 bool setCPU(const std::string &Name) override { 6167 if (!getHexagonCPUSuffix(Name)) 6168 return false; 6169 CPU = Name; 6170 return true; 6171 } 6172 6173 int getEHDataRegisterNumber(unsigned RegNo) const override { 6174 return RegNo < 2 ? RegNo : -1; 6175 } 6176 }; 6177 6178 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6179 MacroBuilder &Builder) const { 6180 Builder.defineMacro("__qdsp6__", "1"); 6181 Builder.defineMacro("__hexagon__", "1"); 6182 6183 if (CPU == "hexagonv4") { 6184 Builder.defineMacro("__HEXAGON_V4__"); 6185 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6186 if (Opts.HexagonQdsp6Compat) { 6187 Builder.defineMacro("__QDSP6_V4__"); 6188 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6189 } 6190 } else if (CPU == "hexagonv5") { 6191 Builder.defineMacro("__HEXAGON_V5__"); 6192 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6193 if(Opts.HexagonQdsp6Compat) { 6194 Builder.defineMacro("__QDSP6_V5__"); 6195 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6196 } 6197 } else if (CPU == "hexagonv55") { 6198 Builder.defineMacro("__HEXAGON_V55__"); 6199 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6200 Builder.defineMacro("__QDSP6_V55__"); 6201 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6202 } else if (CPU == "hexagonv60") { 6203 Builder.defineMacro("__HEXAGON_V60__"); 6204 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6205 Builder.defineMacro("__QDSP6_V60__"); 6206 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6207 } 6208 6209 if (hasFeature("hvx")) { 6210 Builder.defineMacro("__HVX__"); 6211 if (hasFeature("hvx-double")) 6212 Builder.defineMacro("__HVXDBL__"); 6213 } 6214 } 6215 6216 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6217 DiagnosticsEngine &Diags) { 6218 for (auto &F : Features) { 6219 if (F == "+hvx") 6220 HasHVX = true; 6221 else if (F == "-hvx") 6222 HasHVX = HasHVXDouble = false; 6223 else if (F == "+hvx-double") 6224 HasHVX = HasHVXDouble = true; 6225 else if (F == "-hvx-double") 6226 HasHVXDouble = false; 6227 } 6228 return true; 6229 } 6230 6231 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6232 DiagnosticsEngine &Diags, StringRef CPU, 6233 const std::vector<std::string> &FeaturesVec) const { 6234 // Default for v60: -hvx, -hvx-double. 6235 Features["hvx"] = false; 6236 Features["hvx-double"] = false; 6237 6238 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6239 } 6240 6241 6242 const char *const HexagonTargetInfo::GCCRegNames[] = { 6243 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6244 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6245 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6246 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6247 "p0", "p1", "p2", "p3", 6248 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6249 }; 6250 6251 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6252 return llvm::makeArrayRef(GCCRegNames); 6253 } 6254 6255 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6256 { { "sp" }, "r29" }, 6257 { { "fp" }, "r30" }, 6258 { { "lr" }, "r31" }, 6259 }; 6260 6261 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6262 return llvm::makeArrayRef(GCCRegAliases); 6263 } 6264 6265 6266 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6267 #define BUILTIN(ID, TYPE, ATTRS) \ 6268 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6269 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6270 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6271 #include "clang/Basic/BuiltinsHexagon.def" 6272 }; 6273 6274 class LanaiTargetInfo : public TargetInfo { 6275 // Class for Lanai (32-bit). 6276 // The CPU profiles supported by the Lanai backend 6277 enum CPUKind { 6278 CK_NONE, 6279 CK_V11, 6280 } CPU; 6281 6282 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6283 static const char *const GCCRegNames[]; 6284 6285 public: 6286 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6287 : TargetInfo(Triple) { 6288 // Description string has to be kept in sync with backend. 6289 resetDataLayout("E" // Big endian 6290 "-m:e" // ELF name manging 6291 "-p:32:32" // 32 bit pointers, 32 bit aligned 6292 "-i64:64" // 64 bit integers, 64 bit aligned 6293 "-a:0:32" // 32 bit alignment of objects of aggregate type 6294 "-n32" // 32 bit native integer width 6295 "-S64" // 64 bit natural stack alignment 6296 ); 6297 6298 // Setting RegParmMax equal to what mregparm was set to in the old 6299 // toolchain 6300 RegParmMax = 4; 6301 6302 // Set the default CPU to V11 6303 CPU = CK_V11; 6304 6305 // Temporary approach to make everything at least word-aligned and allow for 6306 // safely casting between pointers with different alignment requirements. 6307 // TODO: Remove this when there are no more cast align warnings on the 6308 // firmware. 6309 MinGlobalAlign = 32; 6310 } 6311 6312 void getTargetDefines(const LangOptions &Opts, 6313 MacroBuilder &Builder) const override { 6314 // Define __lanai__ when building for target lanai. 6315 Builder.defineMacro("__lanai__"); 6316 6317 // Set define for the CPU specified. 6318 switch (CPU) { 6319 case CK_V11: 6320 Builder.defineMacro("__LANAI_V11__"); 6321 break; 6322 case CK_NONE: 6323 llvm_unreachable("Unhandled target CPU"); 6324 } 6325 } 6326 6327 bool setCPU(const std::string &Name) override { 6328 CPU = llvm::StringSwitch<CPUKind>(Name) 6329 .Case("v11", CK_V11) 6330 .Default(CK_NONE); 6331 6332 return CPU != CK_NONE; 6333 } 6334 6335 bool hasFeature(StringRef Feature) const override { 6336 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6337 } 6338 6339 ArrayRef<const char *> getGCCRegNames() const override; 6340 6341 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6342 6343 BuiltinVaListKind getBuiltinVaListKind() const override { 6344 return TargetInfo::VoidPtrBuiltinVaList; 6345 } 6346 6347 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6348 6349 bool validateAsmConstraint(const char *&Name, 6350 TargetInfo::ConstraintInfo &info) const override { 6351 return false; 6352 } 6353 6354 const char *getClobbers() const override { return ""; } 6355 }; 6356 6357 const char *const LanaiTargetInfo::GCCRegNames[] = { 6358 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6359 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6360 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6361 6362 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6363 return llvm::makeArrayRef(GCCRegNames); 6364 } 6365 6366 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6367 {{"pc"}, "r2"}, 6368 {{"sp"}, "r4"}, 6369 {{"fp"}, "r5"}, 6370 {{"rv"}, "r8"}, 6371 {{"rr1"}, "r10"}, 6372 {{"rr2"}, "r11"}, 6373 {{"rca"}, "r15"}, 6374 }; 6375 6376 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6377 return llvm::makeArrayRef(GCCRegAliases); 6378 } 6379 6380 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6381 class SparcTargetInfo : public TargetInfo { 6382 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6383 static const char * const GCCRegNames[]; 6384 bool SoftFloat; 6385 public: 6386 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6387 : TargetInfo(Triple), SoftFloat(false) {} 6388 6389 int getEHDataRegisterNumber(unsigned RegNo) const override { 6390 if (RegNo == 0) return 24; 6391 if (RegNo == 1) return 25; 6392 return -1; 6393 } 6394 6395 bool handleTargetFeatures(std::vector<std::string> &Features, 6396 DiagnosticsEngine &Diags) override { 6397 // Check if software floating point is enabled 6398 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6399 if (Feature != Features.end()) { 6400 SoftFloat = true; 6401 } 6402 return true; 6403 } 6404 void getTargetDefines(const LangOptions &Opts, 6405 MacroBuilder &Builder) const override { 6406 DefineStd(Builder, "sparc", Opts); 6407 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6408 6409 if (SoftFloat) 6410 Builder.defineMacro("SOFT_FLOAT", "1"); 6411 } 6412 6413 bool hasFeature(StringRef Feature) const override { 6414 return llvm::StringSwitch<bool>(Feature) 6415 .Case("softfloat", SoftFloat) 6416 .Case("sparc", true) 6417 .Default(false); 6418 } 6419 6420 bool hasSjLjLowering() const override { 6421 return true; 6422 } 6423 6424 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6425 // FIXME: Implement! 6426 return None; 6427 } 6428 BuiltinVaListKind getBuiltinVaListKind() const override { 6429 return TargetInfo::VoidPtrBuiltinVaList; 6430 } 6431 ArrayRef<const char *> getGCCRegNames() const override; 6432 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6433 bool validateAsmConstraint(const char *&Name, 6434 TargetInfo::ConstraintInfo &info) const override { 6435 // FIXME: Implement! 6436 switch (*Name) { 6437 case 'I': // Signed 13-bit constant 6438 case 'J': // Zero 6439 case 'K': // 32-bit constant with the low 12 bits clear 6440 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6441 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6442 case 'N': // Same as 'K' but zext (required for SIMode) 6443 case 'O': // The constant 4096 6444 return true; 6445 } 6446 return false; 6447 } 6448 const char *getClobbers() const override { 6449 // FIXME: Implement! 6450 return ""; 6451 } 6452 6453 // No Sparc V7 for now, the backend doesn't support it anyway. 6454 enum CPUKind { 6455 CK_GENERIC, 6456 CK_V8, 6457 CK_SUPERSPARC, 6458 CK_SPARCLITE, 6459 CK_F934, 6460 CK_HYPERSPARC, 6461 CK_SPARCLITE86X, 6462 CK_SPARCLET, 6463 CK_TSC701, 6464 CK_V9, 6465 CK_ULTRASPARC, 6466 CK_ULTRASPARC3, 6467 CK_NIAGARA, 6468 CK_NIAGARA2, 6469 CK_NIAGARA3, 6470 CK_NIAGARA4, 6471 CK_MYRIAD2100, 6472 CK_MYRIAD2150, 6473 CK_MYRIAD2450, 6474 CK_LEON2, 6475 CK_LEON2_AT697E, 6476 CK_LEON2_AT697F, 6477 CK_LEON3, 6478 CK_LEON3_UT699, 6479 CK_LEON3_GR712RC, 6480 CK_LEON4, 6481 CK_LEON4_GR740 6482 } CPU = CK_GENERIC; 6483 6484 enum CPUGeneration { 6485 CG_V8, 6486 CG_V9, 6487 }; 6488 6489 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6490 switch (Kind) { 6491 case CK_GENERIC: 6492 case CK_V8: 6493 case CK_SUPERSPARC: 6494 case CK_SPARCLITE: 6495 case CK_F934: 6496 case CK_HYPERSPARC: 6497 case CK_SPARCLITE86X: 6498 case CK_SPARCLET: 6499 case CK_TSC701: 6500 case CK_MYRIAD2100: 6501 case CK_MYRIAD2150: 6502 case CK_MYRIAD2450: 6503 case CK_LEON2: 6504 case CK_LEON2_AT697E: 6505 case CK_LEON2_AT697F: 6506 case CK_LEON3: 6507 case CK_LEON3_UT699: 6508 case CK_LEON3_GR712RC: 6509 case CK_LEON4: 6510 case CK_LEON4_GR740: 6511 return CG_V8; 6512 case CK_V9: 6513 case CK_ULTRASPARC: 6514 case CK_ULTRASPARC3: 6515 case CK_NIAGARA: 6516 case CK_NIAGARA2: 6517 case CK_NIAGARA3: 6518 case CK_NIAGARA4: 6519 return CG_V9; 6520 } 6521 llvm_unreachable("Unexpected CPU kind"); 6522 } 6523 6524 CPUKind getCPUKind(StringRef Name) const { 6525 return llvm::StringSwitch<CPUKind>(Name) 6526 .Case("v8", CK_V8) 6527 .Case("supersparc", CK_SUPERSPARC) 6528 .Case("sparclite", CK_SPARCLITE) 6529 .Case("f934", CK_F934) 6530 .Case("hypersparc", CK_HYPERSPARC) 6531 .Case("sparclite86x", CK_SPARCLITE86X) 6532 .Case("sparclet", CK_SPARCLET) 6533 .Case("tsc701", CK_TSC701) 6534 .Case("v9", CK_V9) 6535 .Case("ultrasparc", CK_ULTRASPARC) 6536 .Case("ultrasparc3", CK_ULTRASPARC3) 6537 .Case("niagara", CK_NIAGARA) 6538 .Case("niagara2", CK_NIAGARA2) 6539 .Case("niagara3", CK_NIAGARA3) 6540 .Case("niagara4", CK_NIAGARA4) 6541 .Case("ma2100", CK_MYRIAD2100) 6542 .Case("ma2150", CK_MYRIAD2150) 6543 .Case("ma2450", CK_MYRIAD2450) 6544 // FIXME: the myriad2[.n] spellings are obsolete, 6545 // but a grace period is needed to allow updating dependent builds. 6546 .Case("myriad2", CK_MYRIAD2100) 6547 .Case("myriad2.1", CK_MYRIAD2100) 6548 .Case("myriad2.2", CK_MYRIAD2150) 6549 .Case("leon2", CK_LEON2) 6550 .Case("at697e", CK_LEON2_AT697E) 6551 .Case("at697f", CK_LEON2_AT697F) 6552 .Case("leon3", CK_LEON3) 6553 .Case("ut699", CK_LEON3_UT699) 6554 .Case("gr712rc", CK_LEON3_GR712RC) 6555 .Case("leon4", CK_LEON4) 6556 .Case("gr740", CK_LEON4_GR740) 6557 .Default(CK_GENERIC); 6558 } 6559 6560 bool setCPU(const std::string &Name) override { 6561 CPU = getCPUKind(Name); 6562 return CPU != CK_GENERIC; 6563 } 6564 }; 6565 6566 const char * const SparcTargetInfo::GCCRegNames[] = { 6567 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6568 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6569 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6570 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6571 }; 6572 6573 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6574 return llvm::makeArrayRef(GCCRegNames); 6575 } 6576 6577 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6578 { { "g0" }, "r0" }, 6579 { { "g1" }, "r1" }, 6580 { { "g2" }, "r2" }, 6581 { { "g3" }, "r3" }, 6582 { { "g4" }, "r4" }, 6583 { { "g5" }, "r5" }, 6584 { { "g6" }, "r6" }, 6585 { { "g7" }, "r7" }, 6586 { { "o0" }, "r8" }, 6587 { { "o1" }, "r9" }, 6588 { { "o2" }, "r10" }, 6589 { { "o3" }, "r11" }, 6590 { { "o4" }, "r12" }, 6591 { { "o5" }, "r13" }, 6592 { { "o6", "sp" }, "r14" }, 6593 { { "o7" }, "r15" }, 6594 { { "l0" }, "r16" }, 6595 { { "l1" }, "r17" }, 6596 { { "l2" }, "r18" }, 6597 { { "l3" }, "r19" }, 6598 { { "l4" }, "r20" }, 6599 { { "l5" }, "r21" }, 6600 { { "l6" }, "r22" }, 6601 { { "l7" }, "r23" }, 6602 { { "i0" }, "r24" }, 6603 { { "i1" }, "r25" }, 6604 { { "i2" }, "r26" }, 6605 { { "i3" }, "r27" }, 6606 { { "i4" }, "r28" }, 6607 { { "i5" }, "r29" }, 6608 { { "i6", "fp" }, "r30" }, 6609 { { "i7" }, "r31" }, 6610 }; 6611 6612 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6613 return llvm::makeArrayRef(GCCRegAliases); 6614 } 6615 6616 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6617 class SparcV8TargetInfo : public SparcTargetInfo { 6618 public: 6619 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6620 : SparcTargetInfo(Triple, Opts) { 6621 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6622 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6623 switch (getTriple().getOS()) { 6624 default: 6625 SizeType = UnsignedInt; 6626 IntPtrType = SignedInt; 6627 PtrDiffType = SignedInt; 6628 break; 6629 case llvm::Triple::NetBSD: 6630 case llvm::Triple::OpenBSD: 6631 SizeType = UnsignedLong; 6632 IntPtrType = SignedLong; 6633 PtrDiffType = SignedLong; 6634 break; 6635 } 6636 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6637 } 6638 6639 void getTargetDefines(const LangOptions &Opts, 6640 MacroBuilder &Builder) const override { 6641 SparcTargetInfo::getTargetDefines(Opts, Builder); 6642 switch (getCPUGeneration(CPU)) { 6643 case CG_V8: 6644 Builder.defineMacro("__sparcv8"); 6645 if (getTriple().getOS() != llvm::Triple::Solaris) 6646 Builder.defineMacro("__sparcv8__"); 6647 break; 6648 case CG_V9: 6649 Builder.defineMacro("__sparcv9"); 6650 if (getTriple().getOS() != llvm::Triple::Solaris) { 6651 Builder.defineMacro("__sparcv9__"); 6652 Builder.defineMacro("__sparc_v9__"); 6653 } 6654 break; 6655 } 6656 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6657 std::string MyriadArchValue, Myriad2Value; 6658 Builder.defineMacro("__sparc_v8__"); 6659 Builder.defineMacro("__leon__"); 6660 switch (CPU) { 6661 case CK_MYRIAD2150: 6662 MyriadArchValue = "__ma2150"; 6663 Myriad2Value = "2"; 6664 break; 6665 case CK_MYRIAD2450: 6666 MyriadArchValue = "__ma2450"; 6667 Myriad2Value = "2"; 6668 break; 6669 default: 6670 MyriadArchValue = "__ma2100"; 6671 Myriad2Value = "1"; 6672 break; 6673 } 6674 Builder.defineMacro(MyriadArchValue, "1"); 6675 Builder.defineMacro(MyriadArchValue+"__", "1"); 6676 Builder.defineMacro("__myriad2__", Myriad2Value); 6677 Builder.defineMacro("__myriad2", Myriad2Value); 6678 } 6679 } 6680 6681 bool hasSjLjLowering() const override { 6682 return true; 6683 } 6684 }; 6685 6686 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6687 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6688 public: 6689 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6690 : SparcV8TargetInfo(Triple, Opts) { 6691 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6692 BigEndian = false; 6693 } 6694 }; 6695 6696 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6697 class SparcV9TargetInfo : public SparcTargetInfo { 6698 public: 6699 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6700 : SparcTargetInfo(Triple, Opts) { 6701 // FIXME: Support Sparc quad-precision long double? 6702 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6703 // This is an LP64 platform. 6704 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6705 6706 // OpenBSD uses long long for int64_t and intmax_t. 6707 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6708 IntMaxType = SignedLongLong; 6709 else 6710 IntMaxType = SignedLong; 6711 Int64Type = IntMaxType; 6712 6713 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6714 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6715 LongDoubleWidth = 128; 6716 LongDoubleAlign = 128; 6717 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6718 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6719 } 6720 6721 void getTargetDefines(const LangOptions &Opts, 6722 MacroBuilder &Builder) const override { 6723 SparcTargetInfo::getTargetDefines(Opts, Builder); 6724 Builder.defineMacro("__sparcv9"); 6725 Builder.defineMacro("__arch64__"); 6726 // Solaris doesn't need these variants, but the BSDs do. 6727 if (getTriple().getOS() != llvm::Triple::Solaris) { 6728 Builder.defineMacro("__sparc64__"); 6729 Builder.defineMacro("__sparc_v9__"); 6730 Builder.defineMacro("__sparcv9__"); 6731 } 6732 } 6733 6734 bool setCPU(const std::string &Name) override { 6735 if (!SparcTargetInfo::setCPU(Name)) 6736 return false; 6737 return getCPUGeneration(CPU) == CG_V9; 6738 } 6739 }; 6740 6741 class SystemZTargetInfo : public TargetInfo { 6742 static const Builtin::Info BuiltinInfo[]; 6743 static const char *const GCCRegNames[]; 6744 std::string CPU; 6745 bool HasTransactionalExecution; 6746 bool HasVector; 6747 6748 public: 6749 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6750 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6751 HasVector(false) { 6752 IntMaxType = SignedLong; 6753 Int64Type = SignedLong; 6754 TLSSupported = true; 6755 IntWidth = IntAlign = 32; 6756 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6757 PointerWidth = PointerAlign = 64; 6758 LongDoubleWidth = 128; 6759 LongDoubleAlign = 64; 6760 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6761 DefaultAlignForAttributeAligned = 64; 6762 MinGlobalAlign = 16; 6763 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6764 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6765 } 6766 void getTargetDefines(const LangOptions &Opts, 6767 MacroBuilder &Builder) const override { 6768 Builder.defineMacro("__s390__"); 6769 Builder.defineMacro("__s390x__"); 6770 Builder.defineMacro("__zarch__"); 6771 Builder.defineMacro("__LONG_DOUBLE_128__"); 6772 6773 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6774 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6775 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6776 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6777 6778 if (HasTransactionalExecution) 6779 Builder.defineMacro("__HTM__"); 6780 if (Opts.ZVector) 6781 Builder.defineMacro("__VEC__", "10301"); 6782 } 6783 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6784 return llvm::makeArrayRef(BuiltinInfo, 6785 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6786 } 6787 6788 ArrayRef<const char *> getGCCRegNames() const override; 6789 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6790 // No aliases. 6791 return None; 6792 } 6793 bool validateAsmConstraint(const char *&Name, 6794 TargetInfo::ConstraintInfo &info) const override; 6795 const char *getClobbers() const override { 6796 // FIXME: Is this really right? 6797 return ""; 6798 } 6799 BuiltinVaListKind getBuiltinVaListKind() const override { 6800 return TargetInfo::SystemZBuiltinVaList; 6801 } 6802 bool setCPU(const std::string &Name) override { 6803 CPU = Name; 6804 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6805 .Case("z10", true) 6806 .Case("z196", true) 6807 .Case("zEC12", true) 6808 .Case("z13", true) 6809 .Default(false); 6810 6811 return CPUKnown; 6812 } 6813 bool 6814 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6815 StringRef CPU, 6816 const std::vector<std::string> &FeaturesVec) const override { 6817 if (CPU == "zEC12") 6818 Features["transactional-execution"] = true; 6819 if (CPU == "z13") { 6820 Features["transactional-execution"] = true; 6821 Features["vector"] = true; 6822 } 6823 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6824 } 6825 6826 bool handleTargetFeatures(std::vector<std::string> &Features, 6827 DiagnosticsEngine &Diags) override { 6828 HasTransactionalExecution = false; 6829 for (const auto &Feature : Features) { 6830 if (Feature == "+transactional-execution") 6831 HasTransactionalExecution = true; 6832 else if (Feature == "+vector") 6833 HasVector = true; 6834 } 6835 // If we use the vector ABI, vector types are 64-bit aligned. 6836 if (HasVector) { 6837 MaxVectorAlign = 64; 6838 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6839 "-v128:64-a:8:16-n32:64"); 6840 } 6841 return true; 6842 } 6843 6844 bool hasFeature(StringRef Feature) const override { 6845 return llvm::StringSwitch<bool>(Feature) 6846 .Case("systemz", true) 6847 .Case("htm", HasTransactionalExecution) 6848 .Case("vx", HasVector) 6849 .Default(false); 6850 } 6851 6852 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6853 switch (CC) { 6854 case CC_C: 6855 case CC_Swift: 6856 return CCCR_OK; 6857 default: 6858 return CCCR_Warning; 6859 } 6860 } 6861 6862 StringRef getABI() const override { 6863 if (HasVector) 6864 return "vector"; 6865 return ""; 6866 } 6867 6868 bool useFloat128ManglingForLongDouble() const override { 6869 return true; 6870 } 6871 }; 6872 6873 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6874 #define BUILTIN(ID, TYPE, ATTRS) \ 6875 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6876 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6877 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6878 #include "clang/Basic/BuiltinsSystemZ.def" 6879 }; 6880 6881 const char *const SystemZTargetInfo::GCCRegNames[] = { 6882 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6883 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6884 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6885 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6886 }; 6887 6888 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6889 return llvm::makeArrayRef(GCCRegNames); 6890 } 6891 6892 bool SystemZTargetInfo:: 6893 validateAsmConstraint(const char *&Name, 6894 TargetInfo::ConstraintInfo &Info) const { 6895 switch (*Name) { 6896 default: 6897 return false; 6898 6899 case 'a': // Address register 6900 case 'd': // Data register (equivalent to 'r') 6901 case 'f': // Floating-point register 6902 Info.setAllowsRegister(); 6903 return true; 6904 6905 case 'I': // Unsigned 8-bit constant 6906 case 'J': // Unsigned 12-bit constant 6907 case 'K': // Signed 16-bit constant 6908 case 'L': // Signed 20-bit displacement (on all targets we support) 6909 case 'M': // 0x7fffffff 6910 return true; 6911 6912 case 'Q': // Memory with base and unsigned 12-bit displacement 6913 case 'R': // Likewise, plus an index 6914 case 'S': // Memory with base and signed 20-bit displacement 6915 case 'T': // Likewise, plus an index 6916 Info.setAllowsMemory(); 6917 return true; 6918 } 6919 } 6920 6921 class MSP430TargetInfo : public TargetInfo { 6922 static const char *const GCCRegNames[]; 6923 6924 public: 6925 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6926 : TargetInfo(Triple) { 6927 BigEndian = false; 6928 TLSSupported = false; 6929 IntWidth = 16; 6930 IntAlign = 16; 6931 LongWidth = 32; 6932 LongLongWidth = 64; 6933 LongAlign = LongLongAlign = 16; 6934 PointerWidth = 16; 6935 PointerAlign = 16; 6936 SuitableAlign = 16; 6937 SizeType = UnsignedInt; 6938 IntMaxType = SignedLongLong; 6939 IntPtrType = SignedInt; 6940 PtrDiffType = SignedInt; 6941 SigAtomicType = SignedLong; 6942 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6943 } 6944 void getTargetDefines(const LangOptions &Opts, 6945 MacroBuilder &Builder) const override { 6946 Builder.defineMacro("MSP430"); 6947 Builder.defineMacro("__MSP430__"); 6948 // FIXME: defines for different 'flavours' of MCU 6949 } 6950 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6951 // FIXME: Implement. 6952 return None; 6953 } 6954 bool hasFeature(StringRef Feature) const override { 6955 return Feature == "msp430"; 6956 } 6957 ArrayRef<const char *> getGCCRegNames() const override; 6958 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6959 // No aliases. 6960 return None; 6961 } 6962 bool validateAsmConstraint(const char *&Name, 6963 TargetInfo::ConstraintInfo &info) const override { 6964 // FIXME: implement 6965 switch (*Name) { 6966 case 'K': // the constant 1 6967 case 'L': // constant -1^20 .. 1^19 6968 case 'M': // constant 1-4: 6969 return true; 6970 } 6971 // No target constraints for now. 6972 return false; 6973 } 6974 const char *getClobbers() const override { 6975 // FIXME: Is this really right? 6976 return ""; 6977 } 6978 BuiltinVaListKind getBuiltinVaListKind() const override { 6979 // FIXME: implement 6980 return TargetInfo::CharPtrBuiltinVaList; 6981 } 6982 }; 6983 6984 const char *const MSP430TargetInfo::GCCRegNames[] = { 6985 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6986 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6987 6988 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6989 return llvm::makeArrayRef(GCCRegNames); 6990 } 6991 6992 // LLVM and Clang cannot be used directly to output native binaries for 6993 // target, but is used to compile C code to llvm bitcode with correct 6994 // type and alignment information. 6995 // 6996 // TCE uses the llvm bitcode as input and uses it for generating customized 6997 // target processor and program binary. TCE co-design environment is 6998 // publicly available in http://tce.cs.tut.fi 6999 7000 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7001 3, // opencl_global 7002 4, // opencl_local 7003 5, // opencl_constant 7004 // FIXME: generic has to be added to the target 7005 0, // opencl_generic 7006 0, // cuda_device 7007 0, // cuda_constant 7008 0 // cuda_shared 7009 }; 7010 7011 class TCETargetInfo : public TargetInfo { 7012 public: 7013 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7014 : TargetInfo(Triple) { 7015 TLSSupported = false; 7016 IntWidth = 32; 7017 LongWidth = LongLongWidth = 32; 7018 PointerWidth = 32; 7019 IntAlign = 32; 7020 LongAlign = LongLongAlign = 32; 7021 PointerAlign = 32; 7022 SuitableAlign = 32; 7023 SizeType = UnsignedInt; 7024 IntMaxType = SignedLong; 7025 IntPtrType = SignedInt; 7026 PtrDiffType = SignedInt; 7027 FloatWidth = 32; 7028 FloatAlign = 32; 7029 DoubleWidth = 32; 7030 DoubleAlign = 32; 7031 LongDoubleWidth = 32; 7032 LongDoubleAlign = 32; 7033 FloatFormat = &llvm::APFloat::IEEEsingle; 7034 DoubleFormat = &llvm::APFloat::IEEEsingle; 7035 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 7036 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 7037 "-f64:32-v64:32-v128:32-a:0:32-n32"); 7038 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7039 UseAddrSpaceMapMangling = true; 7040 } 7041 7042 void getTargetDefines(const LangOptions &Opts, 7043 MacroBuilder &Builder) const override { 7044 DefineStd(Builder, "tce", Opts); 7045 Builder.defineMacro("__TCE__"); 7046 Builder.defineMacro("__TCE_V1__"); 7047 } 7048 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7049 7050 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7051 const char *getClobbers() const override { return ""; } 7052 BuiltinVaListKind getBuiltinVaListKind() const override { 7053 return TargetInfo::VoidPtrBuiltinVaList; 7054 } 7055 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7056 bool validateAsmConstraint(const char *&Name, 7057 TargetInfo::ConstraintInfo &info) const override { 7058 return true; 7059 } 7060 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7061 return None; 7062 } 7063 }; 7064 7065 class BPFTargetInfo : public TargetInfo { 7066 public: 7067 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7068 : TargetInfo(Triple) { 7069 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7070 SizeType = UnsignedLong; 7071 PtrDiffType = SignedLong; 7072 IntPtrType = SignedLong; 7073 IntMaxType = SignedLong; 7074 Int64Type = SignedLong; 7075 RegParmMax = 5; 7076 if (Triple.getArch() == llvm::Triple::bpfeb) { 7077 BigEndian = true; 7078 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7079 } else { 7080 BigEndian = false; 7081 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7082 } 7083 MaxAtomicPromoteWidth = 64; 7084 MaxAtomicInlineWidth = 64; 7085 TLSSupported = false; 7086 } 7087 void getTargetDefines(const LangOptions &Opts, 7088 MacroBuilder &Builder) const override { 7089 DefineStd(Builder, "bpf", Opts); 7090 Builder.defineMacro("__BPF__"); 7091 } 7092 bool hasFeature(StringRef Feature) const override { 7093 return Feature == "bpf"; 7094 } 7095 7096 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7097 const char *getClobbers() const override { 7098 return ""; 7099 } 7100 BuiltinVaListKind getBuiltinVaListKind() const override { 7101 return TargetInfo::VoidPtrBuiltinVaList; 7102 } 7103 ArrayRef<const char *> getGCCRegNames() const override { 7104 return None; 7105 } 7106 bool validateAsmConstraint(const char *&Name, 7107 TargetInfo::ConstraintInfo &info) const override { 7108 return true; 7109 } 7110 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7111 return None; 7112 } 7113 }; 7114 7115 class MipsTargetInfo : public TargetInfo { 7116 void setDataLayout() { 7117 StringRef Layout; 7118 7119 if (ABI == "o32") 7120 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7121 else if (ABI == "n32") 7122 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7123 else if (ABI == "n64") 7124 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7125 else 7126 llvm_unreachable("Invalid ABI"); 7127 7128 if (BigEndian) 7129 resetDataLayout(("E-" + Layout).str()); 7130 else 7131 resetDataLayout(("e-" + Layout).str()); 7132 } 7133 7134 7135 static const Builtin::Info BuiltinInfo[]; 7136 std::string CPU; 7137 bool IsMips16; 7138 bool IsMicromips; 7139 bool IsNan2008; 7140 bool IsSingleFloat; 7141 enum MipsFloatABI { 7142 HardFloat, SoftFloat 7143 } FloatABI; 7144 enum DspRevEnum { 7145 NoDSP, DSP1, DSP2 7146 } DspRev; 7147 bool HasMSA; 7148 7149 protected: 7150 bool HasFP64; 7151 std::string ABI; 7152 7153 public: 7154 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7155 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7156 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7157 DspRev(NoDSP), HasMSA(false), HasFP64(false) { 7158 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7159 BigEndian = getTriple().getArch() == llvm::Triple::mips || 7160 getTriple().getArch() == llvm::Triple::mips64; 7161 7162 setABI((getTriple().getArch() == llvm::Triple::mips || 7163 getTriple().getArch() == llvm::Triple::mipsel) 7164 ? "o32" 7165 : "n64"); 7166 7167 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7168 } 7169 7170 bool isNaN2008Default() const { 7171 return CPU == "mips32r6" || CPU == "mips64r6"; 7172 } 7173 7174 bool isFP64Default() const { 7175 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7176 } 7177 7178 bool isNan2008() const override { 7179 return IsNan2008; 7180 } 7181 7182 bool processorSupportsGPR64() const { 7183 return llvm::StringSwitch<bool>(CPU) 7184 .Case("mips3", true) 7185 .Case("mips4", true) 7186 .Case("mips5", true) 7187 .Case("mips64", true) 7188 .Case("mips64r2", true) 7189 .Case("mips64r3", true) 7190 .Case("mips64r5", true) 7191 .Case("mips64r6", true) 7192 .Case("octeon", true) 7193 .Default(false); 7194 return false; 7195 } 7196 7197 StringRef getABI() const override { return ABI; } 7198 bool setABI(const std::string &Name) override { 7199 if (Name == "o32") { 7200 setO32ABITypes(); 7201 ABI = Name; 7202 return true; 7203 } 7204 7205 if (Name == "n32") { 7206 setN32ABITypes(); 7207 ABI = Name; 7208 return true; 7209 } 7210 if (Name == "n64") { 7211 setN64ABITypes(); 7212 ABI = Name; 7213 return true; 7214 } 7215 return false; 7216 } 7217 7218 void setO32ABITypes() { 7219 Int64Type = SignedLongLong; 7220 IntMaxType = Int64Type; 7221 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7222 LongDoubleWidth = LongDoubleAlign = 64; 7223 LongWidth = LongAlign = 32; 7224 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7225 PointerWidth = PointerAlign = 32; 7226 PtrDiffType = SignedInt; 7227 SizeType = UnsignedInt; 7228 SuitableAlign = 64; 7229 } 7230 7231 void setN32N64ABITypes() { 7232 LongDoubleWidth = LongDoubleAlign = 128; 7233 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7234 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7235 LongDoubleWidth = LongDoubleAlign = 64; 7236 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7237 } 7238 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7239 SuitableAlign = 128; 7240 } 7241 7242 void setN64ABITypes() { 7243 setN32N64ABITypes(); 7244 Int64Type = SignedLong; 7245 IntMaxType = Int64Type; 7246 LongWidth = LongAlign = 64; 7247 PointerWidth = PointerAlign = 64; 7248 PtrDiffType = SignedLong; 7249 SizeType = UnsignedLong; 7250 } 7251 7252 void setN32ABITypes() { 7253 setN32N64ABITypes(); 7254 Int64Type = SignedLongLong; 7255 IntMaxType = Int64Type; 7256 LongWidth = LongAlign = 32; 7257 PointerWidth = PointerAlign = 32; 7258 PtrDiffType = SignedInt; 7259 SizeType = UnsignedInt; 7260 } 7261 7262 bool setCPU(const std::string &Name) override { 7263 CPU = Name; 7264 return llvm::StringSwitch<bool>(Name) 7265 .Case("mips1", true) 7266 .Case("mips2", true) 7267 .Case("mips3", true) 7268 .Case("mips4", true) 7269 .Case("mips5", true) 7270 .Case("mips32", true) 7271 .Case("mips32r2", true) 7272 .Case("mips32r3", true) 7273 .Case("mips32r5", true) 7274 .Case("mips32r6", true) 7275 .Case("mips64", true) 7276 .Case("mips64r2", true) 7277 .Case("mips64r3", true) 7278 .Case("mips64r5", true) 7279 .Case("mips64r6", true) 7280 .Case("octeon", true) 7281 .Case("p5600", true) 7282 .Default(false); 7283 } 7284 const std::string& getCPU() const { return CPU; } 7285 bool 7286 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7287 StringRef CPU, 7288 const std::vector<std::string> &FeaturesVec) const override { 7289 if (CPU.empty()) 7290 CPU = getCPU(); 7291 if (CPU == "octeon") 7292 Features["mips64r2"] = Features["cnmips"] = true; 7293 else 7294 Features[CPU] = true; 7295 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7296 } 7297 7298 void getTargetDefines(const LangOptions &Opts, 7299 MacroBuilder &Builder) const override { 7300 if (BigEndian) { 7301 DefineStd(Builder, "MIPSEB", Opts); 7302 Builder.defineMacro("_MIPSEB"); 7303 } else { 7304 DefineStd(Builder, "MIPSEL", Opts); 7305 Builder.defineMacro("_MIPSEL"); 7306 } 7307 7308 Builder.defineMacro("__mips__"); 7309 Builder.defineMacro("_mips"); 7310 if (Opts.GNUMode) 7311 Builder.defineMacro("mips"); 7312 7313 if (ABI == "o32") { 7314 Builder.defineMacro("__mips", "32"); 7315 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7316 } else { 7317 Builder.defineMacro("__mips", "64"); 7318 Builder.defineMacro("__mips64"); 7319 Builder.defineMacro("__mips64__"); 7320 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7321 } 7322 7323 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7324 .Cases("mips32", "mips64", "1") 7325 .Cases("mips32r2", "mips64r2", "2") 7326 .Cases("mips32r3", "mips64r3", "3") 7327 .Cases("mips32r5", "mips64r5", "5") 7328 .Cases("mips32r6", "mips64r6", "6") 7329 .Default(""); 7330 if (!ISARev.empty()) 7331 Builder.defineMacro("__mips_isa_rev", ISARev); 7332 7333 if (ABI == "o32") { 7334 Builder.defineMacro("__mips_o32"); 7335 Builder.defineMacro("_ABIO32", "1"); 7336 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7337 } else if (ABI == "n32") { 7338 Builder.defineMacro("__mips_n32"); 7339 Builder.defineMacro("_ABIN32", "2"); 7340 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7341 } else if (ABI == "n64") { 7342 Builder.defineMacro("__mips_n64"); 7343 Builder.defineMacro("_ABI64", "3"); 7344 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7345 } else 7346 llvm_unreachable("Invalid ABI."); 7347 7348 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7349 7350 switch (FloatABI) { 7351 case HardFloat: 7352 Builder.defineMacro("__mips_hard_float", Twine(1)); 7353 break; 7354 case SoftFloat: 7355 Builder.defineMacro("__mips_soft_float", Twine(1)); 7356 break; 7357 } 7358 7359 if (IsSingleFloat) 7360 Builder.defineMacro("__mips_single_float", Twine(1)); 7361 7362 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7363 Builder.defineMacro("_MIPS_FPSET", 7364 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7365 7366 if (IsMips16) 7367 Builder.defineMacro("__mips16", Twine(1)); 7368 7369 if (IsMicromips) 7370 Builder.defineMacro("__mips_micromips", Twine(1)); 7371 7372 if (IsNan2008) 7373 Builder.defineMacro("__mips_nan2008", Twine(1)); 7374 7375 switch (DspRev) { 7376 default: 7377 break; 7378 case DSP1: 7379 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7380 Builder.defineMacro("__mips_dsp", Twine(1)); 7381 break; 7382 case DSP2: 7383 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7384 Builder.defineMacro("__mips_dspr2", Twine(1)); 7385 Builder.defineMacro("__mips_dsp", Twine(1)); 7386 break; 7387 } 7388 7389 if (HasMSA) 7390 Builder.defineMacro("__mips_msa", Twine(1)); 7391 7392 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7393 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7394 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7395 7396 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7397 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7398 7399 // These shouldn't be defined for MIPS-I but there's no need to check 7400 // for that since MIPS-I isn't supported. 7401 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7402 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7403 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7404 7405 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7406 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7407 // the instructions exist but using them violates the ABI since they 7408 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7409 if (ABI == "n32" || ABI == "n64") 7410 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7411 } 7412 7413 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7414 return llvm::makeArrayRef(BuiltinInfo, 7415 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7416 } 7417 bool hasFeature(StringRef Feature) const override { 7418 return llvm::StringSwitch<bool>(Feature) 7419 .Case("mips", true) 7420 .Case("fp64", HasFP64) 7421 .Default(false); 7422 } 7423 BuiltinVaListKind getBuiltinVaListKind() const override { 7424 return TargetInfo::VoidPtrBuiltinVaList; 7425 } 7426 ArrayRef<const char *> getGCCRegNames() const override { 7427 static const char *const GCCRegNames[] = { 7428 // CPU register names 7429 // Must match second column of GCCRegAliases 7430 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7431 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7432 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7433 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7434 // Floating point register names 7435 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7436 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7437 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7438 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7439 // Hi/lo and condition register names 7440 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7441 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7442 "$ac3hi","$ac3lo", 7443 // MSA register names 7444 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7445 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7446 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7447 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7448 // MSA control register names 7449 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7450 "$msarequest", "$msamap", "$msaunmap" 7451 }; 7452 return llvm::makeArrayRef(GCCRegNames); 7453 } 7454 bool validateAsmConstraint(const char *&Name, 7455 TargetInfo::ConstraintInfo &Info) const override { 7456 switch (*Name) { 7457 default: 7458 return false; 7459 case 'r': // CPU registers. 7460 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7461 case 'y': // Equivalent to "r", backward compatibility only. 7462 case 'f': // floating-point registers. 7463 case 'c': // $25 for indirect jumps 7464 case 'l': // lo register 7465 case 'x': // hilo register pair 7466 Info.setAllowsRegister(); 7467 return true; 7468 case 'I': // Signed 16-bit constant 7469 case 'J': // Integer 0 7470 case 'K': // Unsigned 16-bit constant 7471 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7472 case 'M': // Constants not loadable via lui, addiu, or ori 7473 case 'N': // Constant -1 to -65535 7474 case 'O': // A signed 15-bit constant 7475 case 'P': // A constant between 1 go 65535 7476 return true; 7477 case 'R': // An address that can be used in a non-macro load or store 7478 Info.setAllowsMemory(); 7479 return true; 7480 case 'Z': 7481 if (Name[1] == 'C') { // An address usable by ll, and sc. 7482 Info.setAllowsMemory(); 7483 Name++; // Skip over 'Z'. 7484 return true; 7485 } 7486 return false; 7487 } 7488 } 7489 7490 std::string convertConstraint(const char *&Constraint) const override { 7491 std::string R; 7492 switch (*Constraint) { 7493 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7494 if (Constraint[1] == 'C') { 7495 R = std::string("^") + std::string(Constraint, 2); 7496 Constraint++; 7497 return R; 7498 } 7499 break; 7500 } 7501 return TargetInfo::convertConstraint(Constraint); 7502 } 7503 7504 const char *getClobbers() const override { 7505 // In GCC, $1 is not widely used in generated code (it's used only in a few 7506 // specific situations), so there is no real need for users to add it to 7507 // the clobbers list if they want to use it in their inline assembly code. 7508 // 7509 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7510 // code generation, so using it in inline assembly without adding it to the 7511 // clobbers list can cause conflicts between the inline assembly code and 7512 // the surrounding generated code. 7513 // 7514 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7515 // operands, which will conflict with the ".set at" assembler option (which 7516 // we use only for inline assembly, in order to maintain compatibility with 7517 // GCC) and will also conflict with the user's usage of $1. 7518 // 7519 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7520 // register for generated code is to automatically clobber $1 for all inline 7521 // assembly code. 7522 // 7523 // FIXME: We should automatically clobber $1 only for inline assembly code 7524 // which actually uses it. This would allow LLVM to use $1 for inline 7525 // assembly operands if the user's assembly code doesn't use it. 7526 return "~{$1}"; 7527 } 7528 7529 bool handleTargetFeatures(std::vector<std::string> &Features, 7530 DiagnosticsEngine &Diags) override { 7531 IsMips16 = false; 7532 IsMicromips = false; 7533 IsNan2008 = isNaN2008Default(); 7534 IsSingleFloat = false; 7535 FloatABI = HardFloat; 7536 DspRev = NoDSP; 7537 HasFP64 = isFP64Default(); 7538 7539 for (const auto &Feature : Features) { 7540 if (Feature == "+single-float") 7541 IsSingleFloat = true; 7542 else if (Feature == "+soft-float") 7543 FloatABI = SoftFloat; 7544 else if (Feature == "+mips16") 7545 IsMips16 = true; 7546 else if (Feature == "+micromips") 7547 IsMicromips = true; 7548 else if (Feature == "+dsp") 7549 DspRev = std::max(DspRev, DSP1); 7550 else if (Feature == "+dspr2") 7551 DspRev = std::max(DspRev, DSP2); 7552 else if (Feature == "+msa") 7553 HasMSA = true; 7554 else if (Feature == "+fp64") 7555 HasFP64 = true; 7556 else if (Feature == "-fp64") 7557 HasFP64 = false; 7558 else if (Feature == "+nan2008") 7559 IsNan2008 = true; 7560 else if (Feature == "-nan2008") 7561 IsNan2008 = false; 7562 } 7563 7564 setDataLayout(); 7565 7566 return true; 7567 } 7568 7569 int getEHDataRegisterNumber(unsigned RegNo) const override { 7570 if (RegNo == 0) return 4; 7571 if (RegNo == 1) return 5; 7572 return -1; 7573 } 7574 7575 bool isCLZForZeroUndef() const override { return false; } 7576 7577 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7578 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7579 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7580 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7581 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7582 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7583 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7584 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7585 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7586 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7587 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7588 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7589 {{"ra"}, "$31"}}; 7590 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7591 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7592 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7593 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7594 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7595 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7596 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7597 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7598 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7599 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7600 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7601 {{"ra"}, "$31"}}; 7602 if (ABI == "o32") 7603 return llvm::makeArrayRef(O32RegAliases); 7604 return llvm::makeArrayRef(NewABIRegAliases); 7605 } 7606 7607 bool hasInt128Type() const override { 7608 return ABI == "n32" || ABI == "n64"; 7609 } 7610 7611 bool validateTarget(DiagnosticsEngine &Diags) const override { 7612 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7613 // this yet. It's better to fail here than on the backend assertion. 7614 if (processorSupportsGPR64() && ABI == "o32") { 7615 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7616 return false; 7617 } 7618 7619 // 64-bit ABI's require 64-bit CPU's. 7620 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 7621 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7622 return false; 7623 } 7624 7625 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 7626 // can't handle this yet. It's better to fail here than on the 7627 // backend assertion. 7628 if ((getTriple().getArch() == llvm::Triple::mips64 || 7629 getTriple().getArch() == llvm::Triple::mips64el) && 7630 ABI == "o32") { 7631 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7632 << ABI << getTriple().str(); 7633 return false; 7634 } 7635 7636 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 7637 // can't handle this yet. It's better to fail here than on the 7638 // backend assertion. 7639 if ((getTriple().getArch() == llvm::Triple::mips || 7640 getTriple().getArch() == llvm::Triple::mipsel) && 7641 (ABI == "n32" || ABI == "n64")) { 7642 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7643 << ABI << getTriple().str(); 7644 return false; 7645 } 7646 7647 return true; 7648 } 7649 }; 7650 7651 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7652 #define BUILTIN(ID, TYPE, ATTRS) \ 7653 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7654 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7655 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7656 #include "clang/Basic/BuiltinsMips.def" 7657 }; 7658 7659 class PNaClTargetInfo : public TargetInfo { 7660 public: 7661 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7662 : TargetInfo(Triple) { 7663 BigEndian = false; 7664 this->LongAlign = 32; 7665 this->LongWidth = 32; 7666 this->PointerAlign = 32; 7667 this->PointerWidth = 32; 7668 this->IntMaxType = TargetInfo::SignedLongLong; 7669 this->Int64Type = TargetInfo::SignedLongLong; 7670 this->DoubleAlign = 64; 7671 this->LongDoubleWidth = 64; 7672 this->LongDoubleAlign = 64; 7673 this->SizeType = TargetInfo::UnsignedInt; 7674 this->PtrDiffType = TargetInfo::SignedInt; 7675 this->IntPtrType = TargetInfo::SignedInt; 7676 this->RegParmMax = 0; // Disallow regparm 7677 } 7678 7679 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7680 Builder.defineMacro("__le32__"); 7681 Builder.defineMacro("__pnacl__"); 7682 } 7683 void getTargetDefines(const LangOptions &Opts, 7684 MacroBuilder &Builder) const override { 7685 getArchDefines(Opts, Builder); 7686 } 7687 bool hasFeature(StringRef Feature) const override { 7688 return Feature == "pnacl"; 7689 } 7690 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7691 BuiltinVaListKind getBuiltinVaListKind() const override { 7692 return TargetInfo::PNaClABIBuiltinVaList; 7693 } 7694 ArrayRef<const char *> getGCCRegNames() const override; 7695 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7696 bool validateAsmConstraint(const char *&Name, 7697 TargetInfo::ConstraintInfo &Info) const override { 7698 return false; 7699 } 7700 7701 const char *getClobbers() const override { 7702 return ""; 7703 } 7704 }; 7705 7706 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7707 return None; 7708 } 7709 7710 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7711 return None; 7712 } 7713 7714 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7715 class NaClMips32TargetInfo : public MipsTargetInfo { 7716 public: 7717 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7718 : MipsTargetInfo(Triple, Opts) {} 7719 7720 BuiltinVaListKind getBuiltinVaListKind() const override { 7721 return TargetInfo::PNaClABIBuiltinVaList; 7722 } 7723 }; 7724 7725 class Le64TargetInfo : public TargetInfo { 7726 static const Builtin::Info BuiltinInfo[]; 7727 7728 public: 7729 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7730 : TargetInfo(Triple) { 7731 BigEndian = false; 7732 NoAsmVariants = true; 7733 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7734 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7735 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7736 } 7737 7738 void getTargetDefines(const LangOptions &Opts, 7739 MacroBuilder &Builder) const override { 7740 DefineStd(Builder, "unix", Opts); 7741 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7742 Builder.defineMacro("__ELF__"); 7743 } 7744 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7745 return llvm::makeArrayRef(BuiltinInfo, 7746 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7747 } 7748 BuiltinVaListKind getBuiltinVaListKind() const override { 7749 return TargetInfo::PNaClABIBuiltinVaList; 7750 } 7751 const char *getClobbers() const override { return ""; } 7752 ArrayRef<const char *> getGCCRegNames() const override { 7753 return None; 7754 } 7755 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7756 return None; 7757 } 7758 bool validateAsmConstraint(const char *&Name, 7759 TargetInfo::ConstraintInfo &Info) const override { 7760 return false; 7761 } 7762 7763 bool hasProtectedVisibility() const override { return false; } 7764 }; 7765 7766 class WebAssemblyTargetInfo : public TargetInfo { 7767 static const Builtin::Info BuiltinInfo[]; 7768 7769 enum SIMDEnum { 7770 NoSIMD, 7771 SIMD128, 7772 } SIMDLevel; 7773 7774 public: 7775 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7776 : TargetInfo(T), SIMDLevel(NoSIMD) { 7777 BigEndian = false; 7778 NoAsmVariants = true; 7779 SuitableAlign = 128; 7780 LargeArrayMinWidth = 128; 7781 LargeArrayAlign = 128; 7782 SimdDefaultAlign = 128; 7783 SigAtomicType = SignedLong; 7784 LongDoubleWidth = LongDoubleAlign = 128; 7785 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7786 } 7787 7788 protected: 7789 void getTargetDefines(const LangOptions &Opts, 7790 MacroBuilder &Builder) const override { 7791 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7792 if (SIMDLevel >= SIMD128) 7793 Builder.defineMacro("__wasm_simd128__"); 7794 } 7795 7796 private: 7797 bool 7798 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7799 StringRef CPU, 7800 const std::vector<std::string> &FeaturesVec) const override { 7801 if (CPU == "bleeding-edge") 7802 Features["simd128"] = true; 7803 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7804 } 7805 bool hasFeature(StringRef Feature) const final { 7806 return llvm::StringSwitch<bool>(Feature) 7807 .Case("simd128", SIMDLevel >= SIMD128) 7808 .Default(false); 7809 } 7810 bool handleTargetFeatures(std::vector<std::string> &Features, 7811 DiagnosticsEngine &Diags) final { 7812 for (const auto &Feature : Features) { 7813 if (Feature == "+simd128") { 7814 SIMDLevel = std::max(SIMDLevel, SIMD128); 7815 continue; 7816 } 7817 if (Feature == "-simd128") { 7818 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7819 continue; 7820 } 7821 7822 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7823 << "-target-feature"; 7824 return false; 7825 } 7826 return true; 7827 } 7828 bool setCPU(const std::string &Name) final { 7829 return llvm::StringSwitch<bool>(Name) 7830 .Case("mvp", true) 7831 .Case("bleeding-edge", true) 7832 .Case("generic", true) 7833 .Default(false); 7834 } 7835 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7836 return llvm::makeArrayRef(BuiltinInfo, 7837 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7838 } 7839 BuiltinVaListKind getBuiltinVaListKind() const final { 7840 return VoidPtrBuiltinVaList; 7841 } 7842 ArrayRef<const char *> getGCCRegNames() const final { 7843 return None; 7844 } 7845 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7846 return None; 7847 } 7848 bool 7849 validateAsmConstraint(const char *&Name, 7850 TargetInfo::ConstraintInfo &Info) const final { 7851 return false; 7852 } 7853 const char *getClobbers() const final { return ""; } 7854 bool isCLZForZeroUndef() const final { return false; } 7855 bool hasInt128Type() const final { return true; } 7856 IntType getIntTypeByWidth(unsigned BitWidth, 7857 bool IsSigned) const final { 7858 // WebAssembly prefers long long for explicitly 64-bit integers. 7859 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7860 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7861 } 7862 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7863 bool IsSigned) const final { 7864 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7865 return BitWidth == 64 7866 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7867 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7868 } 7869 }; 7870 7871 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7872 #define BUILTIN(ID, TYPE, ATTRS) \ 7873 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7874 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7875 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7876 #include "clang/Basic/BuiltinsWebAssembly.def" 7877 }; 7878 7879 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7880 public: 7881 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 7882 const TargetOptions &Opts) 7883 : WebAssemblyTargetInfo(T, Opts) { 7884 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7885 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7886 } 7887 7888 protected: 7889 void getTargetDefines(const LangOptions &Opts, 7890 MacroBuilder &Builder) const override { 7891 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7892 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7893 } 7894 }; 7895 7896 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7897 public: 7898 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 7899 const TargetOptions &Opts) 7900 : WebAssemblyTargetInfo(T, Opts) { 7901 LongAlign = LongWidth = 64; 7902 PointerAlign = PointerWidth = 64; 7903 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7904 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7905 } 7906 7907 protected: 7908 void getTargetDefines(const LangOptions &Opts, 7909 MacroBuilder &Builder) const override { 7910 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7911 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7912 } 7913 }; 7914 7915 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7916 #define BUILTIN(ID, TYPE, ATTRS) \ 7917 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7918 #include "clang/Basic/BuiltinsLe64.def" 7919 }; 7920 7921 static const unsigned SPIRAddrSpaceMap[] = { 7922 1, // opencl_global 7923 3, // opencl_local 7924 2, // opencl_constant 7925 4, // opencl_generic 7926 0, // cuda_device 7927 0, // cuda_constant 7928 0 // cuda_shared 7929 }; 7930 class SPIRTargetInfo : public TargetInfo { 7931 public: 7932 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7933 : TargetInfo(Triple) { 7934 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7935 "SPIR target must use unknown OS"); 7936 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7937 "SPIR target must use unknown environment type"); 7938 BigEndian = false; 7939 TLSSupported = false; 7940 LongWidth = LongAlign = 64; 7941 AddrSpaceMap = &SPIRAddrSpaceMap; 7942 UseAddrSpaceMapMangling = true; 7943 // Define available target features 7944 // These must be defined in sorted order! 7945 NoAsmVariants = true; 7946 } 7947 void getTargetDefines(const LangOptions &Opts, 7948 MacroBuilder &Builder) const override { 7949 DefineStd(Builder, "SPIR", Opts); 7950 } 7951 bool hasFeature(StringRef Feature) const override { 7952 return Feature == "spir"; 7953 } 7954 7955 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7956 const char *getClobbers() const override { return ""; } 7957 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7958 bool validateAsmConstraint(const char *&Name, 7959 TargetInfo::ConstraintInfo &info) const override { 7960 return true; 7961 } 7962 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7963 return None; 7964 } 7965 BuiltinVaListKind getBuiltinVaListKind() const override { 7966 return TargetInfo::VoidPtrBuiltinVaList; 7967 } 7968 7969 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7970 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 7971 : CCCR_Warning; 7972 } 7973 7974 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7975 return CC_SpirFunction; 7976 } 7977 7978 void setSupportedOpenCLOpts() override { 7979 // Assume all OpenCL extensions and optional core features are supported 7980 // for SPIR since it is a generic target. 7981 getSupportedOpenCLOpts().setAll(); 7982 } 7983 }; 7984 7985 class SPIR32TargetInfo : public SPIRTargetInfo { 7986 public: 7987 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7988 : SPIRTargetInfo(Triple, Opts) { 7989 PointerWidth = PointerAlign = 32; 7990 SizeType = TargetInfo::UnsignedInt; 7991 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7992 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7993 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7994 } 7995 void getTargetDefines(const LangOptions &Opts, 7996 MacroBuilder &Builder) const override { 7997 DefineStd(Builder, "SPIR32", Opts); 7998 } 7999 }; 8000 8001 class SPIR64TargetInfo : public SPIRTargetInfo { 8002 public: 8003 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8004 : SPIRTargetInfo(Triple, Opts) { 8005 PointerWidth = PointerAlign = 64; 8006 SizeType = TargetInfo::UnsignedLong; 8007 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8008 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8009 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8010 } 8011 void getTargetDefines(const LangOptions &Opts, 8012 MacroBuilder &Builder) const override { 8013 DefineStd(Builder, "SPIR64", Opts); 8014 } 8015 }; 8016 8017 class XCoreTargetInfo : public TargetInfo { 8018 static const Builtin::Info BuiltinInfo[]; 8019 public: 8020 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8021 : TargetInfo(Triple) { 8022 BigEndian = false; 8023 NoAsmVariants = true; 8024 LongLongAlign = 32; 8025 SuitableAlign = 32; 8026 DoubleAlign = LongDoubleAlign = 32; 8027 SizeType = UnsignedInt; 8028 PtrDiffType = SignedInt; 8029 IntPtrType = SignedInt; 8030 WCharType = UnsignedChar; 8031 WIntType = UnsignedInt; 8032 UseZeroLengthBitfieldAlignment = true; 8033 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8034 "-f64:32-a:0:32-n32"); 8035 } 8036 void getTargetDefines(const LangOptions &Opts, 8037 MacroBuilder &Builder) const override { 8038 Builder.defineMacro("__XS1B__"); 8039 } 8040 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8041 return llvm::makeArrayRef(BuiltinInfo, 8042 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8043 } 8044 BuiltinVaListKind getBuiltinVaListKind() const override { 8045 return TargetInfo::VoidPtrBuiltinVaList; 8046 } 8047 const char *getClobbers() const override { 8048 return ""; 8049 } 8050 ArrayRef<const char *> getGCCRegNames() const override { 8051 static const char * const GCCRegNames[] = { 8052 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8053 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8054 }; 8055 return llvm::makeArrayRef(GCCRegNames); 8056 } 8057 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8058 return None; 8059 } 8060 bool validateAsmConstraint(const char *&Name, 8061 TargetInfo::ConstraintInfo &Info) const override { 8062 return false; 8063 } 8064 int getEHDataRegisterNumber(unsigned RegNo) const override { 8065 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8066 return (RegNo < 2)? RegNo : -1; 8067 } 8068 bool allowsLargerPreferedTypeAlignment() const override { 8069 return false; 8070 } 8071 }; 8072 8073 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8074 #define BUILTIN(ID, TYPE, ATTRS) \ 8075 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8076 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8077 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8078 #include "clang/Basic/BuiltinsXCore.def" 8079 }; 8080 8081 // x86_32 Android target 8082 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8083 public: 8084 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8085 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8086 SuitableAlign = 32; 8087 LongDoubleWidth = 64; 8088 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 8089 } 8090 }; 8091 8092 // x86_64 Android target 8093 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8094 public: 8095 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8096 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8097 LongDoubleFormat = &llvm::APFloat::IEEEquad; 8098 } 8099 8100 bool useFloat128ManglingForLongDouble() const override { 8101 return true; 8102 } 8103 }; 8104 8105 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8106 class RenderScript32TargetInfo : public ARMleTargetInfo { 8107 public: 8108 RenderScript32TargetInfo(const llvm::Triple &Triple, 8109 const TargetOptions &Opts) 8110 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8111 Triple.getOSName(), 8112 Triple.getEnvironmentName()), 8113 Opts) { 8114 IsRenderScriptTarget = true; 8115 LongWidth = LongAlign = 64; 8116 } 8117 void getTargetDefines(const LangOptions &Opts, 8118 MacroBuilder &Builder) const override { 8119 Builder.defineMacro("__RENDERSCRIPT__"); 8120 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8121 } 8122 }; 8123 8124 // 64-bit RenderScript is aarch64 8125 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8126 public: 8127 RenderScript64TargetInfo(const llvm::Triple &Triple, 8128 const TargetOptions &Opts) 8129 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8130 Triple.getOSName(), 8131 Triple.getEnvironmentName()), 8132 Opts) { 8133 IsRenderScriptTarget = true; 8134 } 8135 8136 void getTargetDefines(const LangOptions &Opts, 8137 MacroBuilder &Builder) const override { 8138 Builder.defineMacro("__RENDERSCRIPT__"); 8139 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8140 } 8141 }; 8142 8143 } // end anonymous namespace 8144 8145 //===----------------------------------------------------------------------===// 8146 // Driver code 8147 //===----------------------------------------------------------------------===// 8148 8149 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8150 const TargetOptions &Opts) { 8151 llvm::Triple::OSType os = Triple.getOS(); 8152 8153 switch (Triple.getArch()) { 8154 default: 8155 return nullptr; 8156 8157 case llvm::Triple::xcore: 8158 return new XCoreTargetInfo(Triple, Opts); 8159 8160 case llvm::Triple::hexagon: 8161 return new HexagonTargetInfo(Triple, Opts); 8162 8163 case llvm::Triple::lanai: 8164 return new LanaiTargetInfo(Triple, Opts); 8165 8166 case llvm::Triple::aarch64: 8167 if (Triple.isOSDarwin()) 8168 return new DarwinAArch64TargetInfo(Triple, Opts); 8169 8170 switch (os) { 8171 case llvm::Triple::CloudABI: 8172 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8173 case llvm::Triple::FreeBSD: 8174 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8175 case llvm::Triple::Linux: 8176 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8177 case llvm::Triple::NetBSD: 8178 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8179 default: 8180 return new AArch64leTargetInfo(Triple, Opts); 8181 } 8182 8183 case llvm::Triple::aarch64_be: 8184 switch (os) { 8185 case llvm::Triple::FreeBSD: 8186 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8187 case llvm::Triple::Linux: 8188 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8189 case llvm::Triple::NetBSD: 8190 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8191 default: 8192 return new AArch64beTargetInfo(Triple, Opts); 8193 } 8194 8195 case llvm::Triple::arm: 8196 case llvm::Triple::thumb: 8197 if (Triple.isOSBinFormatMachO()) 8198 return new DarwinARMTargetInfo(Triple, Opts); 8199 8200 switch (os) { 8201 case llvm::Triple::Linux: 8202 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8203 case llvm::Triple::FreeBSD: 8204 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8205 case llvm::Triple::NetBSD: 8206 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8207 case llvm::Triple::OpenBSD: 8208 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8209 case llvm::Triple::Bitrig: 8210 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8211 case llvm::Triple::RTEMS: 8212 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8213 case llvm::Triple::NaCl: 8214 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8215 case llvm::Triple::Win32: 8216 switch (Triple.getEnvironment()) { 8217 case llvm::Triple::Cygnus: 8218 return new CygwinARMTargetInfo(Triple, Opts); 8219 case llvm::Triple::GNU: 8220 return new MinGWARMTargetInfo(Triple, Opts); 8221 case llvm::Triple::Itanium: 8222 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8223 case llvm::Triple::MSVC: 8224 default: // Assume MSVC for unknown environments 8225 return new MicrosoftARMleTargetInfo(Triple, Opts); 8226 } 8227 default: 8228 return new ARMleTargetInfo(Triple, Opts); 8229 } 8230 8231 case llvm::Triple::armeb: 8232 case llvm::Triple::thumbeb: 8233 if (Triple.isOSDarwin()) 8234 return new DarwinARMTargetInfo(Triple, Opts); 8235 8236 switch (os) { 8237 case llvm::Triple::Linux: 8238 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8239 case llvm::Triple::FreeBSD: 8240 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8241 case llvm::Triple::NetBSD: 8242 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8243 case llvm::Triple::OpenBSD: 8244 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8245 case llvm::Triple::Bitrig: 8246 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8247 case llvm::Triple::RTEMS: 8248 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8249 case llvm::Triple::NaCl: 8250 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8251 default: 8252 return new ARMbeTargetInfo(Triple, Opts); 8253 } 8254 8255 case llvm::Triple::bpfeb: 8256 case llvm::Triple::bpfel: 8257 return new BPFTargetInfo(Triple, Opts); 8258 8259 case llvm::Triple::msp430: 8260 return new MSP430TargetInfo(Triple, Opts); 8261 8262 case llvm::Triple::mips: 8263 switch (os) { 8264 case llvm::Triple::Linux: 8265 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8266 case llvm::Triple::RTEMS: 8267 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8268 case llvm::Triple::FreeBSD: 8269 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8270 case llvm::Triple::NetBSD: 8271 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8272 default: 8273 return new MipsTargetInfo(Triple, Opts); 8274 } 8275 8276 case llvm::Triple::mipsel: 8277 switch (os) { 8278 case llvm::Triple::Linux: 8279 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8280 case llvm::Triple::RTEMS: 8281 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8282 case llvm::Triple::FreeBSD: 8283 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8284 case llvm::Triple::NetBSD: 8285 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8286 case llvm::Triple::NaCl: 8287 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 8288 default: 8289 return new MipsTargetInfo(Triple, Opts); 8290 } 8291 8292 case llvm::Triple::mips64: 8293 switch (os) { 8294 case llvm::Triple::Linux: 8295 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8296 case llvm::Triple::RTEMS: 8297 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8298 case llvm::Triple::FreeBSD: 8299 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8300 case llvm::Triple::NetBSD: 8301 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8302 case llvm::Triple::OpenBSD: 8303 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8304 default: 8305 return new MipsTargetInfo(Triple, Opts); 8306 } 8307 8308 case llvm::Triple::mips64el: 8309 switch (os) { 8310 case llvm::Triple::Linux: 8311 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8312 case llvm::Triple::RTEMS: 8313 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8314 case llvm::Triple::FreeBSD: 8315 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8316 case llvm::Triple::NetBSD: 8317 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8318 case llvm::Triple::OpenBSD: 8319 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8320 default: 8321 return new MipsTargetInfo(Triple, Opts); 8322 } 8323 8324 case llvm::Triple::le32: 8325 switch (os) { 8326 case llvm::Triple::NaCl: 8327 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8328 default: 8329 return nullptr; 8330 } 8331 8332 case llvm::Triple::le64: 8333 return new Le64TargetInfo(Triple, Opts); 8334 8335 case llvm::Triple::ppc: 8336 if (Triple.isOSDarwin()) 8337 return new DarwinPPC32TargetInfo(Triple, Opts); 8338 switch (os) { 8339 case llvm::Triple::Linux: 8340 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8341 case llvm::Triple::FreeBSD: 8342 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8343 case llvm::Triple::NetBSD: 8344 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8345 case llvm::Triple::OpenBSD: 8346 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8347 case llvm::Triple::RTEMS: 8348 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8349 default: 8350 return new PPC32TargetInfo(Triple, Opts); 8351 } 8352 8353 case llvm::Triple::ppc64: 8354 if (Triple.isOSDarwin()) 8355 return new DarwinPPC64TargetInfo(Triple, Opts); 8356 switch (os) { 8357 case llvm::Triple::Linux: 8358 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8359 case llvm::Triple::Lv2: 8360 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8361 case llvm::Triple::FreeBSD: 8362 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8363 case llvm::Triple::NetBSD: 8364 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8365 default: 8366 return new PPC64TargetInfo(Triple, Opts); 8367 } 8368 8369 case llvm::Triple::ppc64le: 8370 switch (os) { 8371 case llvm::Triple::Linux: 8372 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8373 case llvm::Triple::NetBSD: 8374 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8375 default: 8376 return new PPC64TargetInfo(Triple, Opts); 8377 } 8378 8379 case llvm::Triple::nvptx: 8380 return new NVPTX32TargetInfo(Triple, Opts); 8381 case llvm::Triple::nvptx64: 8382 return new NVPTX64TargetInfo(Triple, Opts); 8383 8384 case llvm::Triple::amdgcn: 8385 case llvm::Triple::r600: 8386 return new AMDGPUTargetInfo(Triple, Opts); 8387 8388 case llvm::Triple::sparc: 8389 switch (os) { 8390 case llvm::Triple::Linux: 8391 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8392 case llvm::Triple::Solaris: 8393 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8394 case llvm::Triple::NetBSD: 8395 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8396 case llvm::Triple::OpenBSD: 8397 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8398 case llvm::Triple::RTEMS: 8399 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8400 default: 8401 return new SparcV8TargetInfo(Triple, Opts); 8402 } 8403 8404 // The 'sparcel' architecture copies all the above cases except for Solaris. 8405 case llvm::Triple::sparcel: 8406 switch (os) { 8407 case llvm::Triple::Linux: 8408 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8409 case llvm::Triple::NetBSD: 8410 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8411 case llvm::Triple::OpenBSD: 8412 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8413 case llvm::Triple::RTEMS: 8414 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8415 default: 8416 return new SparcV8elTargetInfo(Triple, Opts); 8417 } 8418 8419 case llvm::Triple::sparcv9: 8420 switch (os) { 8421 case llvm::Triple::Linux: 8422 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8423 case llvm::Triple::Solaris: 8424 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8425 case llvm::Triple::NetBSD: 8426 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8427 case llvm::Triple::OpenBSD: 8428 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8429 case llvm::Triple::FreeBSD: 8430 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8431 default: 8432 return new SparcV9TargetInfo(Triple, Opts); 8433 } 8434 8435 case llvm::Triple::systemz: 8436 switch (os) { 8437 case llvm::Triple::Linux: 8438 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8439 default: 8440 return new SystemZTargetInfo(Triple, Opts); 8441 } 8442 8443 case llvm::Triple::tce: 8444 return new TCETargetInfo(Triple, Opts); 8445 8446 case llvm::Triple::x86: 8447 if (Triple.isOSDarwin()) 8448 return new DarwinI386TargetInfo(Triple, Opts); 8449 8450 switch (os) { 8451 case llvm::Triple::CloudABI: 8452 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8453 case llvm::Triple::Linux: { 8454 switch (Triple.getEnvironment()) { 8455 default: 8456 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8457 case llvm::Triple::Android: 8458 return new AndroidX86_32TargetInfo(Triple, Opts); 8459 } 8460 } 8461 case llvm::Triple::DragonFly: 8462 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8463 case llvm::Triple::NetBSD: 8464 return new NetBSDI386TargetInfo(Triple, Opts); 8465 case llvm::Triple::OpenBSD: 8466 return new OpenBSDI386TargetInfo(Triple, Opts); 8467 case llvm::Triple::Bitrig: 8468 return new BitrigI386TargetInfo(Triple, Opts); 8469 case llvm::Triple::FreeBSD: 8470 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8471 case llvm::Triple::KFreeBSD: 8472 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8473 case llvm::Triple::Minix: 8474 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8475 case llvm::Triple::Solaris: 8476 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8477 case llvm::Triple::Win32: { 8478 switch (Triple.getEnvironment()) { 8479 case llvm::Triple::Cygnus: 8480 return new CygwinX86_32TargetInfo(Triple, Opts); 8481 case llvm::Triple::GNU: 8482 return new MinGWX86_32TargetInfo(Triple, Opts); 8483 case llvm::Triple::Itanium: 8484 case llvm::Triple::MSVC: 8485 default: // Assume MSVC for unknown environments 8486 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8487 } 8488 } 8489 case llvm::Triple::Haiku: 8490 return new HaikuX86_32TargetInfo(Triple, Opts); 8491 case llvm::Triple::RTEMS: 8492 return new RTEMSX86_32TargetInfo(Triple, Opts); 8493 case llvm::Triple::NaCl: 8494 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8495 case llvm::Triple::ELFIAMCU: 8496 return new MCUX86_32TargetInfo(Triple, Opts); 8497 default: 8498 return new X86_32TargetInfo(Triple, Opts); 8499 } 8500 8501 case llvm::Triple::x86_64: 8502 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8503 return new DarwinX86_64TargetInfo(Triple, Opts); 8504 8505 switch (os) { 8506 case llvm::Triple::CloudABI: 8507 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8508 case llvm::Triple::Linux: { 8509 switch (Triple.getEnvironment()) { 8510 default: 8511 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8512 case llvm::Triple::Android: 8513 return new AndroidX86_64TargetInfo(Triple, Opts); 8514 } 8515 } 8516 case llvm::Triple::DragonFly: 8517 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8518 case llvm::Triple::NetBSD: 8519 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8520 case llvm::Triple::OpenBSD: 8521 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8522 case llvm::Triple::Bitrig: 8523 return new BitrigX86_64TargetInfo(Triple, Opts); 8524 case llvm::Triple::FreeBSD: 8525 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8526 case llvm::Triple::KFreeBSD: 8527 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8528 case llvm::Triple::Solaris: 8529 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8530 case llvm::Triple::Win32: { 8531 switch (Triple.getEnvironment()) { 8532 case llvm::Triple::Cygnus: 8533 return new CygwinX86_64TargetInfo(Triple, Opts); 8534 case llvm::Triple::GNU: 8535 return new MinGWX86_64TargetInfo(Triple, Opts); 8536 case llvm::Triple::MSVC: 8537 default: // Assume MSVC for unknown environments 8538 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8539 } 8540 } 8541 case llvm::Triple::Haiku: 8542 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8543 case llvm::Triple::NaCl: 8544 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8545 case llvm::Triple::PS4: 8546 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8547 default: 8548 return new X86_64TargetInfo(Triple, Opts); 8549 } 8550 8551 case llvm::Triple::spir: { 8552 if (Triple.getOS() != llvm::Triple::UnknownOS || 8553 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8554 return nullptr; 8555 return new SPIR32TargetInfo(Triple, Opts); 8556 } 8557 case llvm::Triple::spir64: { 8558 if (Triple.getOS() != llvm::Triple::UnknownOS || 8559 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8560 return nullptr; 8561 return new SPIR64TargetInfo(Triple, Opts); 8562 } 8563 case llvm::Triple::wasm32: 8564 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8565 return nullptr; 8566 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8567 case llvm::Triple::wasm64: 8568 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8569 return nullptr; 8570 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8571 8572 case llvm::Triple::renderscript32: 8573 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 8574 case llvm::Triple::renderscript64: 8575 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 8576 } 8577 } 8578 8579 /// CreateTargetInfo - Return the target info object for the specified target 8580 /// options. 8581 TargetInfo * 8582 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8583 const std::shared_ptr<TargetOptions> &Opts) { 8584 llvm::Triple Triple(Opts->Triple); 8585 8586 // Construct the target 8587 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8588 if (!Target) { 8589 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8590 return nullptr; 8591 } 8592 Target->TargetOpts = Opts; 8593 8594 // Set the target CPU if specified. 8595 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8596 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8597 return nullptr; 8598 } 8599 8600 // Set the target ABI if specified. 8601 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8602 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8603 return nullptr; 8604 } 8605 8606 // Set the fp math unit. 8607 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8608 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8609 return nullptr; 8610 } 8611 8612 // Compute the default target features, we need the target to handle this 8613 // because features may have dependencies on one another. 8614 llvm::StringMap<bool> Features; 8615 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8616 Opts->FeaturesAsWritten)) 8617 return nullptr; 8618 8619 // Add the features to the compile options. 8620 Opts->Features.clear(); 8621 for (const auto &F : Features) 8622 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8623 8624 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8625 return nullptr; 8626 8627 Target->setSupportedOpenCLOpts(); 8628 8629 if (!Target->validateTarget(Diags)) 8630 return nullptr; 8631 8632 return Target.release(); 8633 } 8634