1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/TargetParser.h" 31 #include <algorithm> 32 #include <memory> 33 using namespace clang; 34 35 //===----------------------------------------------------------------------===// 36 // Common code shared among targets. 37 //===----------------------------------------------------------------------===// 38 39 /// DefineStd - Define a macro name and standard variants. For example if 40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 41 /// when in GNU mode. 42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 43 const LangOptions &Opts) { 44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 45 46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 47 // in the user's namespace. 48 if (Opts.GNUMode) 49 Builder.defineMacro(MacroName); 50 51 // Define __unix. 52 Builder.defineMacro("__" + MacroName); 53 54 // Define __unix__. 55 Builder.defineMacro("__" + MacroName + "__"); 56 } 57 58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 59 bool Tuning = true) { 60 Builder.defineMacro("__" + CPUName); 61 Builder.defineMacro("__" + CPUName + "__"); 62 if (Tuning) 63 Builder.defineMacro("__tune_" + CPUName + "__"); 64 } 65 66 //===----------------------------------------------------------------------===// 67 // Defines specific to certain operating systems. 68 //===----------------------------------------------------------------------===// 69 70 namespace { 71 template<typename TgtInfo> 72 class OSTargetInfo : public TgtInfo { 73 protected: 74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 75 MacroBuilder &Builder) const=0; 76 public: 77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 78 void getTargetDefines(const LangOptions &Opts, 79 MacroBuilder &Builder) const override { 80 TgtInfo::getTargetDefines(Opts, Builder); 81 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 82 } 83 84 }; 85 } // end anonymous namespace 86 87 88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 89 const llvm::Triple &Triple, 90 StringRef &PlatformName, 91 VersionTuple &PlatformMinVersion) { 92 Builder.defineMacro("__APPLE_CC__", "6000"); 93 Builder.defineMacro("__APPLE__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.has(SanitizerKind::Address)) 98 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 99 100 if (!Opts.ObjCAutoRefCount) { 101 // __weak is always defined, for use in blocks and with objc pointers. 102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 103 104 // Darwin defines __strong even in C mode (just to nothing). 105 if (Opts.getGC() != LangOptions::NonGC) 106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 107 else 108 Builder.defineMacro("__strong", ""); 109 110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 111 // allow this in C, since one might have block pointers in structs that 112 // are used in pure C code and in Objective-C ARC. 113 Builder.defineMacro("__unsafe_unretained", ""); 114 } 115 116 if (Opts.Static) 117 Builder.defineMacro("__STATIC__"); 118 else 119 Builder.defineMacro("__DYNAMIC__"); 120 121 if (Opts.POSIXThreads) 122 Builder.defineMacro("_REENTRANT"); 123 124 // Get the platform type and version number from the triple. 125 unsigned Maj, Min, Rev; 126 if (Triple.isMacOSX()) { 127 Triple.getMacOSXVersion(Maj, Min, Rev); 128 PlatformName = "macosx"; 129 } else { 130 Triple.getOSVersion(Maj, Min, Rev); 131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 132 } 133 134 // If -target arch-pc-win32-macho option specified, we're 135 // generating code for Win32 ABI. No need to emit 136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 137 if (PlatformName == "win32") { 138 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 139 return; 140 } 141 142 // Set the appropriate OS version define. 143 if (Triple.isiOS()) { 144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 145 char Str[6]; 146 Str[0] = '0' + Maj; 147 Str[1] = '0' + (Min / 10); 148 Str[2] = '0' + (Min % 10); 149 Str[3] = '0' + (Rev / 10); 150 Str[4] = '0' + (Rev % 10); 151 Str[5] = '\0'; 152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 153 Str); 154 } else if (Triple.isMacOSX()) { 155 // Note that the Driver allows versions which aren't representable in the 156 // define (because we only get a single digit for the minor and micro 157 // revision numbers). So, we limit them to the maximum representable 158 // version. 159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 160 char Str[7]; 161 if (Maj < 10 || (Maj == 10 && Min < 10)) { 162 Str[0] = '0' + (Maj / 10); 163 Str[1] = '0' + (Maj % 10); 164 Str[2] = '0' + std::min(Min, 9U); 165 Str[3] = '0' + std::min(Rev, 9U); 166 Str[4] = '\0'; 167 } else { 168 // Handle versions > 10.9. 169 Str[0] = '0' + (Maj / 10); 170 Str[1] = '0' + (Maj % 10); 171 Str[2] = '0' + (Min / 10); 172 Str[3] = '0' + (Min % 10); 173 Str[4] = '0' + (Rev / 10); 174 Str[5] = '0' + (Rev % 10); 175 Str[6] = '\0'; 176 } 177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 178 } 179 180 // Tell users about the kernel if there is one. 181 if (Triple.isOSDarwin()) 182 Builder.defineMacro("__MACH__"); 183 184 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 185 } 186 187 namespace { 188 // CloudABI Target 189 template <typename Target> 190 class CloudABITargetInfo : public OSTargetInfo<Target> { 191 protected: 192 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 193 MacroBuilder &Builder) const override { 194 Builder.defineMacro("__CloudABI__"); 195 Builder.defineMacro("__ELF__"); 196 197 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 198 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 199 Builder.defineMacro("__STDC_UTF_16__"); 200 Builder.defineMacro("__STDC_UTF_32__"); 201 } 202 203 public: 204 CloudABITargetInfo(const llvm::Triple &Triple) 205 : OSTargetInfo<Target>(Triple) { 206 this->UserLabelPrefix = ""; 207 } 208 }; 209 210 template<typename Target> 211 class DarwinTargetInfo : public OSTargetInfo<Target> { 212 protected: 213 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 214 MacroBuilder &Builder) const override { 215 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 216 this->PlatformMinVersion); 217 } 218 219 public: 220 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 221 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 222 this->MCountName = "\01mcount"; 223 } 224 225 std::string isValidSectionSpecifier(StringRef SR) const override { 226 // Let MCSectionMachO validate this. 227 StringRef Segment, Section; 228 unsigned TAA, StubSize; 229 bool HasTAA; 230 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 231 TAA, HasTAA, StubSize); 232 } 233 234 const char *getStaticInitSectionSpecifier() const override { 235 // FIXME: We should return 0 when building kexts. 236 return "__TEXT,__StaticInit,regular,pure_instructions"; 237 } 238 239 /// Darwin does not support protected visibility. Darwin's "default" 240 /// is very similar to ELF's "protected"; Darwin requires a "weak" 241 /// attribute on declarations that can be dynamically replaced. 242 bool hasProtectedVisibility() const override { 243 return false; 244 } 245 }; 246 247 248 // DragonFlyBSD Target 249 template<typename Target> 250 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 251 protected: 252 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 253 MacroBuilder &Builder) const override { 254 // DragonFly defines; list based off of gcc output 255 Builder.defineMacro("__DragonFly__"); 256 Builder.defineMacro("__DragonFly_cc_version", "100001"); 257 Builder.defineMacro("__ELF__"); 258 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 259 Builder.defineMacro("__tune_i386__"); 260 DefineStd(Builder, "unix", Opts); 261 } 262 public: 263 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 264 : OSTargetInfo<Target>(Triple) { 265 this->UserLabelPrefix = ""; 266 267 switch (Triple.getArch()) { 268 default: 269 case llvm::Triple::x86: 270 case llvm::Triple::x86_64: 271 this->MCountName = ".mcount"; 272 break; 273 } 274 } 275 }; 276 277 // FreeBSD Target 278 template<typename Target> 279 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 280 protected: 281 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 282 MacroBuilder &Builder) const override { 283 // FreeBSD defines; list based off of gcc output 284 285 unsigned Release = Triple.getOSMajorVersion(); 286 if (Release == 0U) 287 Release = 8; 288 289 Builder.defineMacro("__FreeBSD__", Twine(Release)); 290 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 291 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 292 DefineStd(Builder, "unix", Opts); 293 Builder.defineMacro("__ELF__"); 294 295 // On FreeBSD, wchar_t contains the number of the code point as 296 // used by the character set of the locale. These character sets are 297 // not necessarily a superset of ASCII. 298 // 299 // FIXME: This is wrong; the macro refers to the numerical values 300 // of wchar_t *literals*, which are not locale-dependent. However, 301 // FreeBSD systems apparently depend on us getting this wrong, and 302 // setting this to 1 is conforming even if all the basic source 303 // character literals have the same encoding as char and wchar_t. 304 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 305 } 306 public: 307 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 310 switch (Triple.getArch()) { 311 default: 312 case llvm::Triple::x86: 313 case llvm::Triple::x86_64: 314 this->MCountName = ".mcount"; 315 break; 316 case llvm::Triple::mips: 317 case llvm::Triple::mipsel: 318 case llvm::Triple::ppc: 319 case llvm::Triple::ppc64: 320 case llvm::Triple::ppc64le: 321 this->MCountName = "_mcount"; 322 break; 323 case llvm::Triple::arm: 324 this->MCountName = "__mcount"; 325 break; 326 } 327 } 328 }; 329 330 // GNU/kFreeBSD Target 331 template<typename Target> 332 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 333 protected: 334 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 335 MacroBuilder &Builder) const override { 336 // GNU/kFreeBSD defines; list based off of gcc output 337 338 DefineStd(Builder, "unix", Opts); 339 Builder.defineMacro("__FreeBSD_kernel__"); 340 Builder.defineMacro("__GLIBC__"); 341 Builder.defineMacro("__ELF__"); 342 if (Opts.POSIXThreads) 343 Builder.defineMacro("_REENTRANT"); 344 if (Opts.CPlusPlus) 345 Builder.defineMacro("_GNU_SOURCE"); 346 } 347 public: 348 KFreeBSDTargetInfo(const llvm::Triple &Triple) 349 : OSTargetInfo<Target>(Triple) { 350 this->UserLabelPrefix = ""; 351 } 352 }; 353 354 // Minix Target 355 template<typename Target> 356 class MinixTargetInfo : public OSTargetInfo<Target> { 357 protected: 358 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 359 MacroBuilder &Builder) const override { 360 // Minix defines 361 362 Builder.defineMacro("__minix", "3"); 363 Builder.defineMacro("_EM_WSIZE", "4"); 364 Builder.defineMacro("_EM_PSIZE", "4"); 365 Builder.defineMacro("_EM_SSIZE", "2"); 366 Builder.defineMacro("_EM_LSIZE", "4"); 367 Builder.defineMacro("_EM_FSIZE", "4"); 368 Builder.defineMacro("_EM_DSIZE", "8"); 369 Builder.defineMacro("__ELF__"); 370 DefineStd(Builder, "unix", Opts); 371 } 372 public: 373 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 374 this->UserLabelPrefix = ""; 375 } 376 }; 377 378 // Linux target 379 template<typename Target> 380 class LinuxTargetInfo : public OSTargetInfo<Target> { 381 protected: 382 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 383 MacroBuilder &Builder) const override { 384 // Linux defines; list based off of gcc output 385 DefineStd(Builder, "unix", Opts); 386 DefineStd(Builder, "linux", Opts); 387 Builder.defineMacro("__gnu_linux__"); 388 Builder.defineMacro("__ELF__"); 389 if (Triple.getEnvironment() == llvm::Triple::Android) { 390 Builder.defineMacro("__ANDROID__", "1"); 391 unsigned Maj, Min, Rev; 392 Triple.getEnvironmentVersion(Maj, Min, Rev); 393 this->PlatformName = "android"; 394 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 395 } 396 if (Opts.POSIXThreads) 397 Builder.defineMacro("_REENTRANT"); 398 if (Opts.CPlusPlus) 399 Builder.defineMacro("_GNU_SOURCE"); 400 } 401 public: 402 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 403 this->UserLabelPrefix = ""; 404 this->WIntType = TargetInfo::UnsignedInt; 405 406 switch (Triple.getArch()) { 407 default: 408 break; 409 case llvm::Triple::ppc: 410 case llvm::Triple::ppc64: 411 case llvm::Triple::ppc64le: 412 this->MCountName = "_mcount"; 413 break; 414 } 415 } 416 417 const char *getStaticInitSectionSpecifier() const override { 418 return ".text.startup"; 419 } 420 }; 421 422 // NetBSD Target 423 template<typename Target> 424 class NetBSDTargetInfo : public OSTargetInfo<Target> { 425 protected: 426 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 427 MacroBuilder &Builder) const override { 428 // NetBSD defines; list based off of gcc output 429 Builder.defineMacro("__NetBSD__"); 430 Builder.defineMacro("__unix__"); 431 Builder.defineMacro("__ELF__"); 432 if (Opts.POSIXThreads) 433 Builder.defineMacro("_POSIX_THREADS"); 434 435 switch (Triple.getArch()) { 436 default: 437 break; 438 case llvm::Triple::arm: 439 case llvm::Triple::armeb: 440 case llvm::Triple::thumb: 441 case llvm::Triple::thumbeb: 442 Builder.defineMacro("__ARM_DWARF_EH__"); 443 break; 444 } 445 } 446 public: 447 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 448 this->UserLabelPrefix = ""; 449 this->MCountName = "_mcount"; 450 } 451 }; 452 453 // OpenBSD Target 454 template<typename Target> 455 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 456 protected: 457 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 458 MacroBuilder &Builder) const override { 459 // OpenBSD defines; list based off of gcc output 460 461 Builder.defineMacro("__OpenBSD__"); 462 DefineStd(Builder, "unix", Opts); 463 Builder.defineMacro("__ELF__"); 464 if (Opts.POSIXThreads) 465 Builder.defineMacro("_REENTRANT"); 466 } 467 public: 468 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 469 this->UserLabelPrefix = ""; 470 this->TLSSupported = false; 471 472 switch (Triple.getArch()) { 473 default: 474 case llvm::Triple::x86: 475 case llvm::Triple::x86_64: 476 case llvm::Triple::arm: 477 case llvm::Triple::sparc: 478 this->MCountName = "__mcount"; 479 break; 480 case llvm::Triple::mips64: 481 case llvm::Triple::mips64el: 482 case llvm::Triple::ppc: 483 case llvm::Triple::sparcv9: 484 this->MCountName = "_mcount"; 485 break; 486 } 487 } 488 }; 489 490 // Bitrig Target 491 template<typename Target> 492 class BitrigTargetInfo : public OSTargetInfo<Target> { 493 protected: 494 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 495 MacroBuilder &Builder) const override { 496 // Bitrig defines; list based off of gcc output 497 498 Builder.defineMacro("__Bitrig__"); 499 DefineStd(Builder, "unix", Opts); 500 Builder.defineMacro("__ELF__"); 501 if (Opts.POSIXThreads) 502 Builder.defineMacro("_REENTRANT"); 503 504 switch (Triple.getArch()) { 505 default: 506 break; 507 case llvm::Triple::arm: 508 case llvm::Triple::armeb: 509 case llvm::Triple::thumb: 510 case llvm::Triple::thumbeb: 511 Builder.defineMacro("__ARM_DWARF_EH__"); 512 break; 513 } 514 } 515 public: 516 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 517 this->UserLabelPrefix = ""; 518 this->MCountName = "__mcount"; 519 } 520 }; 521 522 // PSP Target 523 template<typename Target> 524 class PSPTargetInfo : public OSTargetInfo<Target> { 525 protected: 526 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 527 MacroBuilder &Builder) const override { 528 // PSP defines; list based on the output of the pspdev gcc toolchain. 529 Builder.defineMacro("PSP"); 530 Builder.defineMacro("_PSP"); 531 Builder.defineMacro("__psp__"); 532 Builder.defineMacro("__ELF__"); 533 } 534 public: 535 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 536 this->UserLabelPrefix = ""; 537 } 538 }; 539 540 // PS3 PPU Target 541 template<typename Target> 542 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 543 protected: 544 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 545 MacroBuilder &Builder) const override { 546 // PS3 PPU defines. 547 Builder.defineMacro("__PPC__"); 548 Builder.defineMacro("__PPU__"); 549 Builder.defineMacro("__CELLOS_LV2__"); 550 Builder.defineMacro("__ELF__"); 551 Builder.defineMacro("__LP32__"); 552 Builder.defineMacro("_ARCH_PPC64"); 553 Builder.defineMacro("__powerpc64__"); 554 } 555 public: 556 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 557 this->UserLabelPrefix = ""; 558 this->LongWidth = this->LongAlign = 32; 559 this->PointerWidth = this->PointerAlign = 32; 560 this->IntMaxType = TargetInfo::SignedLongLong; 561 this->Int64Type = TargetInfo::SignedLongLong; 562 this->SizeType = TargetInfo::UnsignedInt; 563 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 564 } 565 }; 566 567 template <typename Target> 568 class PS4OSTargetInfo : public OSTargetInfo<Target> { 569 protected: 570 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 571 MacroBuilder &Builder) const override { 572 Builder.defineMacro("__FreeBSD__", "9"); 573 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 574 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 575 DefineStd(Builder, "unix", Opts); 576 Builder.defineMacro("__ELF__"); 577 Builder.defineMacro("__PS4__"); 578 } 579 public: 580 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 581 this->WCharType = this->UnsignedShort; 582 583 this->UserLabelPrefix = ""; 584 585 switch (Triple.getArch()) { 586 default: 587 case llvm::Triple::x86_64: 588 this->MCountName = ".mcount"; 589 break; 590 } 591 } 592 }; 593 594 // Solaris target 595 template<typename Target> 596 class SolarisTargetInfo : public OSTargetInfo<Target> { 597 protected: 598 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 599 MacroBuilder &Builder) const override { 600 DefineStd(Builder, "sun", Opts); 601 DefineStd(Builder, "unix", Opts); 602 Builder.defineMacro("__ELF__"); 603 Builder.defineMacro("__svr4__"); 604 Builder.defineMacro("__SVR4"); 605 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 606 // newer, but to 500 for everything else. feature_test.h has a check to 607 // ensure that you are not using C99 with an old version of X/Open or C89 608 // with a new version. 609 if (Opts.C99) 610 Builder.defineMacro("_XOPEN_SOURCE", "600"); 611 else 612 Builder.defineMacro("_XOPEN_SOURCE", "500"); 613 if (Opts.CPlusPlus) 614 Builder.defineMacro("__C99FEATURES__"); 615 Builder.defineMacro("_LARGEFILE_SOURCE"); 616 Builder.defineMacro("_LARGEFILE64_SOURCE"); 617 Builder.defineMacro("__EXTENSIONS__"); 618 Builder.defineMacro("_REENTRANT"); 619 } 620 public: 621 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 622 this->UserLabelPrefix = ""; 623 this->WCharType = this->SignedInt; 624 // FIXME: WIntType should be SignedLong 625 } 626 }; 627 628 // Windows target 629 template<typename Target> 630 class WindowsTargetInfo : public OSTargetInfo<Target> { 631 protected: 632 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 633 MacroBuilder &Builder) const override { 634 Builder.defineMacro("_WIN32"); 635 } 636 void getVisualStudioDefines(const LangOptions &Opts, 637 MacroBuilder &Builder) const { 638 if (Opts.CPlusPlus) { 639 if (Opts.RTTIData) 640 Builder.defineMacro("_CPPRTTI"); 641 642 if (Opts.CXXExceptions) 643 Builder.defineMacro("_CPPUNWIND"); 644 } 645 646 if (!Opts.CharIsSigned) 647 Builder.defineMacro("_CHAR_UNSIGNED"); 648 649 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 650 // but it works for now. 651 if (Opts.POSIXThreads) 652 Builder.defineMacro("_MT"); 653 654 if (Opts.MSCompatibilityVersion) { 655 Builder.defineMacro("_MSC_VER", 656 Twine(Opts.MSCompatibilityVersion / 100000)); 657 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 658 // FIXME We cannot encode the revision information into 32-bits 659 Builder.defineMacro("_MSC_BUILD", Twine(1)); 660 661 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 662 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 663 } 664 665 if (Opts.MicrosoftExt) { 666 Builder.defineMacro("_MSC_EXTENSIONS"); 667 668 if (Opts.CPlusPlus11) { 669 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 670 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 671 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 672 } 673 } 674 675 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 676 } 677 678 public: 679 WindowsTargetInfo(const llvm::Triple &Triple) 680 : OSTargetInfo<Target>(Triple) {} 681 }; 682 683 template <typename Target> 684 class NaClTargetInfo : public OSTargetInfo<Target> { 685 protected: 686 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 687 MacroBuilder &Builder) const override { 688 if (Opts.POSIXThreads) 689 Builder.defineMacro("_REENTRANT"); 690 if (Opts.CPlusPlus) 691 Builder.defineMacro("_GNU_SOURCE"); 692 693 DefineStd(Builder, "unix", Opts); 694 Builder.defineMacro("__ELF__"); 695 Builder.defineMacro("__native_client__"); 696 } 697 698 public: 699 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 700 this->UserLabelPrefix = ""; 701 this->LongAlign = 32; 702 this->LongWidth = 32; 703 this->PointerAlign = 32; 704 this->PointerWidth = 32; 705 this->IntMaxType = TargetInfo::SignedLongLong; 706 this->Int64Type = TargetInfo::SignedLongLong; 707 this->DoubleAlign = 64; 708 this->LongDoubleWidth = 64; 709 this->LongDoubleAlign = 64; 710 this->LongLongWidth = 64; 711 this->LongLongAlign = 64; 712 this->SizeType = TargetInfo::UnsignedInt; 713 this->PtrDiffType = TargetInfo::SignedInt; 714 this->IntPtrType = TargetInfo::SignedInt; 715 // RegParmMax is inherited from the underlying architecture 716 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 717 if (Triple.getArch() == llvm::Triple::arm) { 718 // Handled in ARM's setABI(). 719 } else if (Triple.getArch() == llvm::Triple::x86) { 720 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 721 } else if (Triple.getArch() == llvm::Triple::x86_64) { 722 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 723 } else if (Triple.getArch() == llvm::Triple::mipsel) { 724 // Handled on mips' setDescriptionString. 725 } else { 726 assert(Triple.getArch() == llvm::Triple::le32); 727 this->DescriptionString = "e-p:32:32-i64:64"; 728 } 729 } 730 }; 731 732 //===----------------------------------------------------------------------===// 733 // Specific target implementations. 734 //===----------------------------------------------------------------------===// 735 736 // PPC abstract base class 737 class PPCTargetInfo : public TargetInfo { 738 static const Builtin::Info BuiltinInfo[]; 739 static const char * const GCCRegNames[]; 740 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 741 std::string CPU; 742 743 // Target cpu features. 744 bool HasVSX; 745 bool HasP8Vector; 746 bool HasP8Crypto; 747 bool HasDirectMove; 748 bool HasQPX; 749 bool HasHTM; 750 bool HasBPERMD; 751 bool HasExtDiv; 752 753 protected: 754 std::string ABI; 755 756 public: 757 PPCTargetInfo(const llvm::Triple &Triple) 758 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 759 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 760 HasBPERMD(false), HasExtDiv(false) { 761 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 762 LongDoubleWidth = LongDoubleAlign = 128; 763 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 764 } 765 766 /// \brief Flags for architecture specific defines. 767 typedef enum { 768 ArchDefineNone = 0, 769 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 770 ArchDefinePpcgr = 1 << 1, 771 ArchDefinePpcsq = 1 << 2, 772 ArchDefine440 = 1 << 3, 773 ArchDefine603 = 1 << 4, 774 ArchDefine604 = 1 << 5, 775 ArchDefinePwr4 = 1 << 6, 776 ArchDefinePwr5 = 1 << 7, 777 ArchDefinePwr5x = 1 << 8, 778 ArchDefinePwr6 = 1 << 9, 779 ArchDefinePwr6x = 1 << 10, 780 ArchDefinePwr7 = 1 << 11, 781 ArchDefinePwr8 = 1 << 12, 782 ArchDefineA2 = 1 << 13, 783 ArchDefineA2q = 1 << 14 784 } ArchDefineTypes; 785 786 // Note: GCC recognizes the following additional cpus: 787 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 788 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 789 // titan, rs64. 790 bool setCPU(const std::string &Name) override { 791 bool CPUKnown = llvm::StringSwitch<bool>(Name) 792 .Case("generic", true) 793 .Case("440", true) 794 .Case("450", true) 795 .Case("601", true) 796 .Case("602", true) 797 .Case("603", true) 798 .Case("603e", true) 799 .Case("603ev", true) 800 .Case("604", true) 801 .Case("604e", true) 802 .Case("620", true) 803 .Case("630", true) 804 .Case("g3", true) 805 .Case("7400", true) 806 .Case("g4", true) 807 .Case("7450", true) 808 .Case("g4+", true) 809 .Case("750", true) 810 .Case("970", true) 811 .Case("g5", true) 812 .Case("a2", true) 813 .Case("a2q", true) 814 .Case("e500mc", true) 815 .Case("e5500", true) 816 .Case("power3", true) 817 .Case("pwr3", true) 818 .Case("power4", true) 819 .Case("pwr4", true) 820 .Case("power5", true) 821 .Case("pwr5", true) 822 .Case("power5x", true) 823 .Case("pwr5x", true) 824 .Case("power6", true) 825 .Case("pwr6", true) 826 .Case("power6x", true) 827 .Case("pwr6x", true) 828 .Case("power7", true) 829 .Case("pwr7", true) 830 .Case("power8", true) 831 .Case("pwr8", true) 832 .Case("powerpc", true) 833 .Case("ppc", true) 834 .Case("powerpc64", true) 835 .Case("ppc64", true) 836 .Case("powerpc64le", true) 837 .Case("ppc64le", true) 838 .Default(false); 839 840 if (CPUKnown) 841 CPU = Name; 842 843 return CPUKnown; 844 } 845 846 847 StringRef getABI() const override { return ABI; } 848 849 void getTargetBuiltins(const Builtin::Info *&Records, 850 unsigned &NumRecords) const override { 851 Records = BuiltinInfo; 852 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 853 } 854 855 bool isCLZForZeroUndef() const override { return false; } 856 857 void getTargetDefines(const LangOptions &Opts, 858 MacroBuilder &Builder) const override; 859 860 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 861 862 bool handleTargetFeatures(std::vector<std::string> &Features, 863 DiagnosticsEngine &Diags) override; 864 bool hasFeature(StringRef Feature) const override; 865 866 void getGCCRegNames(const char * const *&Names, 867 unsigned &NumNames) const override; 868 void getGCCRegAliases(const GCCRegAlias *&Aliases, 869 unsigned &NumAliases) const override; 870 bool validateAsmConstraint(const char *&Name, 871 TargetInfo::ConstraintInfo &Info) const override { 872 switch (*Name) { 873 default: return false; 874 case 'O': // Zero 875 break; 876 case 'b': // Base register 877 case 'f': // Floating point register 878 Info.setAllowsRegister(); 879 break; 880 // FIXME: The following are added to allow parsing. 881 // I just took a guess at what the actions should be. 882 // Also, is more specific checking needed? I.e. specific registers? 883 case 'd': // Floating point register (containing 64-bit value) 884 case 'v': // Altivec vector register 885 Info.setAllowsRegister(); 886 break; 887 case 'w': 888 switch (Name[1]) { 889 case 'd':// VSX vector register to hold vector double data 890 case 'f':// VSX vector register to hold vector float data 891 case 's':// VSX vector register to hold scalar float data 892 case 'a':// Any VSX register 893 case 'c':// An individual CR bit 894 break; 895 default: 896 return false; 897 } 898 Info.setAllowsRegister(); 899 Name++; // Skip over 'w'. 900 break; 901 case 'h': // `MQ', `CTR', or `LINK' register 902 case 'q': // `MQ' register 903 case 'c': // `CTR' register 904 case 'l': // `LINK' register 905 case 'x': // `CR' register (condition register) number 0 906 case 'y': // `CR' register (condition register) 907 case 'z': // `XER[CA]' carry bit (part of the XER register) 908 Info.setAllowsRegister(); 909 break; 910 case 'I': // Signed 16-bit constant 911 case 'J': // Unsigned 16-bit constant shifted left 16 bits 912 // (use `L' instead for SImode constants) 913 case 'K': // Unsigned 16-bit constant 914 case 'L': // Signed 16-bit constant shifted left 16 bits 915 case 'M': // Constant larger than 31 916 case 'N': // Exact power of 2 917 case 'P': // Constant whose negation is a signed 16-bit constant 918 case 'G': // Floating point constant that can be loaded into a 919 // register with one instruction per word 920 case 'H': // Integer/Floating point constant that can be loaded 921 // into a register using three instructions 922 break; 923 case 'm': // Memory operand. Note that on PowerPC targets, m can 924 // include addresses that update the base register. It 925 // is therefore only safe to use `m' in an asm statement 926 // if that asm statement accesses the operand exactly once. 927 // The asm statement must also use `%U<opno>' as a 928 // placeholder for the "update" flag in the corresponding 929 // load or store instruction. For example: 930 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 931 // is correct but: 932 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 933 // is not. Use es rather than m if you don't want the base 934 // register to be updated. 935 case 'e': 936 if (Name[1] != 's') 937 return false; 938 // es: A "stable" memory operand; that is, one which does not 939 // include any automodification of the base register. Unlike 940 // `m', this constraint can be used in asm statements that 941 // might access the operand several times, or that might not 942 // access it at all. 943 Info.setAllowsMemory(); 944 Name++; // Skip over 'e'. 945 break; 946 case 'Q': // Memory operand that is an offset from a register (it is 947 // usually better to use `m' or `es' in asm statements) 948 case 'Z': // Memory operand that is an indexed or indirect from a 949 // register (it is usually better to use `m' or `es' in 950 // asm statements) 951 Info.setAllowsMemory(); 952 Info.setAllowsRegister(); 953 break; 954 case 'R': // AIX TOC entry 955 case 'a': // Address operand that is an indexed or indirect from a 956 // register (`p' is preferable for asm statements) 957 case 'S': // Constant suitable as a 64-bit mask operand 958 case 'T': // Constant suitable as a 32-bit mask operand 959 case 'U': // System V Release 4 small data area reference 960 case 't': // AND masks that can be performed by two rldic{l, r} 961 // instructions 962 case 'W': // Vector constant that does not require memory 963 case 'j': // Vector constant that is all zeros. 964 break; 965 // End FIXME. 966 } 967 return true; 968 } 969 std::string convertConstraint(const char *&Constraint) const override { 970 std::string R; 971 switch (*Constraint) { 972 case 'e': 973 case 'w': 974 // Two-character constraint; add "^" hint for later parsing. 975 R = std::string("^") + std::string(Constraint, 2); 976 Constraint++; 977 break; 978 default: 979 return TargetInfo::convertConstraint(Constraint); 980 } 981 return R; 982 } 983 const char *getClobbers() const override { 984 return ""; 985 } 986 int getEHDataRegisterNumber(unsigned RegNo) const override { 987 if (RegNo == 0) return 3; 988 if (RegNo == 1) return 4; 989 return -1; 990 } 991 992 bool hasSjLjLowering() const override { 993 return true; 994 } 995 996 bool useFloat128ManglingForLongDouble() const override { 997 return LongDoubleWidth == 128 && 998 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 999 getTriple().isOSBinFormatELF(); 1000 } 1001 }; 1002 1003 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1004 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1005 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1006 ALL_LANGUAGES }, 1007 #include "clang/Basic/BuiltinsPPC.def" 1008 }; 1009 1010 /// handleTargetFeatures - Perform initialization based on the user 1011 /// configured set of features. 1012 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1013 DiagnosticsEngine &Diags) { 1014 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 1015 // Ignore disabled features. 1016 if (Features[i][0] == '-') 1017 continue; 1018 1019 StringRef Feature = StringRef(Features[i]).substr(1); 1020 1021 if (Feature == "vsx") { 1022 HasVSX = true; 1023 continue; 1024 } 1025 1026 if (Feature == "bpermd") { 1027 HasBPERMD = true; 1028 continue; 1029 } 1030 1031 if (Feature == "extdiv") { 1032 HasExtDiv = true; 1033 continue; 1034 } 1035 1036 if (Feature == "power8-vector") { 1037 HasP8Vector = true; 1038 HasVSX = true; 1039 continue; 1040 } 1041 1042 if (Feature == "crypto") { 1043 HasP8Crypto = true; 1044 continue; 1045 } 1046 1047 if (Feature == "direct-move") { 1048 HasDirectMove = true; 1049 HasVSX = true; 1050 continue; 1051 } 1052 1053 if (Feature == "qpx") { 1054 HasQPX = true; 1055 continue; 1056 } 1057 1058 if (Feature == "htm") { 1059 HasHTM = true; 1060 continue; 1061 } 1062 1063 // TODO: Finish this list and add an assert that we've handled them 1064 // all. 1065 } 1066 1067 return true; 1068 } 1069 1070 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1071 /// #defines that are not tied to a specific subtarget. 1072 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1073 MacroBuilder &Builder) const { 1074 // Target identification. 1075 Builder.defineMacro("__ppc__"); 1076 Builder.defineMacro("__PPC__"); 1077 Builder.defineMacro("_ARCH_PPC"); 1078 Builder.defineMacro("__powerpc__"); 1079 Builder.defineMacro("__POWERPC__"); 1080 if (PointerWidth == 64) { 1081 Builder.defineMacro("_ARCH_PPC64"); 1082 Builder.defineMacro("__powerpc64__"); 1083 Builder.defineMacro("__ppc64__"); 1084 Builder.defineMacro("__PPC64__"); 1085 } 1086 1087 // Target properties. 1088 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1089 Builder.defineMacro("_LITTLE_ENDIAN"); 1090 } else { 1091 if (getTriple().getOS() != llvm::Triple::NetBSD && 1092 getTriple().getOS() != llvm::Triple::OpenBSD) 1093 Builder.defineMacro("_BIG_ENDIAN"); 1094 } 1095 1096 // ABI options. 1097 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1098 Builder.defineMacro("_CALL_ELF", "1"); 1099 if (ABI == "elfv2") 1100 Builder.defineMacro("_CALL_ELF", "2"); 1101 1102 // Subtarget options. 1103 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1104 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1105 1106 // FIXME: Should be controlled by command line option. 1107 if (LongDoubleWidth == 128) 1108 Builder.defineMacro("__LONG_DOUBLE_128__"); 1109 1110 if (Opts.AltiVec) { 1111 Builder.defineMacro("__VEC__", "10206"); 1112 Builder.defineMacro("__ALTIVEC__"); 1113 } 1114 1115 // CPU identification. 1116 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1117 .Case("440", ArchDefineName) 1118 .Case("450", ArchDefineName | ArchDefine440) 1119 .Case("601", ArchDefineName) 1120 .Case("602", ArchDefineName | ArchDefinePpcgr) 1121 .Case("603", ArchDefineName | ArchDefinePpcgr) 1122 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1123 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1124 .Case("604", ArchDefineName | ArchDefinePpcgr) 1125 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1126 .Case("620", ArchDefineName | ArchDefinePpcgr) 1127 .Case("630", ArchDefineName | ArchDefinePpcgr) 1128 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1129 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1130 .Case("750", ArchDefineName | ArchDefinePpcgr) 1131 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1132 | ArchDefinePpcsq) 1133 .Case("a2", ArchDefineA2) 1134 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1135 .Case("pwr3", ArchDefinePpcgr) 1136 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1137 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1138 | ArchDefinePpcsq) 1139 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1140 | ArchDefinePpcgr | ArchDefinePpcsq) 1141 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1142 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1143 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1144 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1145 | ArchDefinePpcsq) 1146 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1147 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1148 | ArchDefinePpcgr | ArchDefinePpcsq) 1149 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1150 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1151 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1152 .Case("power3", ArchDefinePpcgr) 1153 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1154 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1155 | ArchDefinePpcsq) 1156 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1157 | ArchDefinePpcgr | ArchDefinePpcsq) 1158 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1159 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1160 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1161 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1162 | ArchDefinePpcsq) 1163 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1164 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1165 | ArchDefinePpcgr | ArchDefinePpcsq) 1166 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1167 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1168 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1169 .Default(ArchDefineNone); 1170 1171 if (defs & ArchDefineName) 1172 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1173 if (defs & ArchDefinePpcgr) 1174 Builder.defineMacro("_ARCH_PPCGR"); 1175 if (defs & ArchDefinePpcsq) 1176 Builder.defineMacro("_ARCH_PPCSQ"); 1177 if (defs & ArchDefine440) 1178 Builder.defineMacro("_ARCH_440"); 1179 if (defs & ArchDefine603) 1180 Builder.defineMacro("_ARCH_603"); 1181 if (defs & ArchDefine604) 1182 Builder.defineMacro("_ARCH_604"); 1183 if (defs & ArchDefinePwr4) 1184 Builder.defineMacro("_ARCH_PWR4"); 1185 if (defs & ArchDefinePwr5) 1186 Builder.defineMacro("_ARCH_PWR5"); 1187 if (defs & ArchDefinePwr5x) 1188 Builder.defineMacro("_ARCH_PWR5X"); 1189 if (defs & ArchDefinePwr6) 1190 Builder.defineMacro("_ARCH_PWR6"); 1191 if (defs & ArchDefinePwr6x) 1192 Builder.defineMacro("_ARCH_PWR6X"); 1193 if (defs & ArchDefinePwr7) 1194 Builder.defineMacro("_ARCH_PWR7"); 1195 if (defs & ArchDefinePwr8) 1196 Builder.defineMacro("_ARCH_PWR8"); 1197 if (defs & ArchDefineA2) 1198 Builder.defineMacro("_ARCH_A2"); 1199 if (defs & ArchDefineA2q) { 1200 Builder.defineMacro("_ARCH_A2Q"); 1201 Builder.defineMacro("_ARCH_QP"); 1202 } 1203 1204 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1205 Builder.defineMacro("__bg__"); 1206 Builder.defineMacro("__THW_BLUEGENE__"); 1207 Builder.defineMacro("__bgq__"); 1208 Builder.defineMacro("__TOS_BGQ__"); 1209 } 1210 1211 if (HasVSX) 1212 Builder.defineMacro("__VSX__"); 1213 if (HasP8Vector) 1214 Builder.defineMacro("__POWER8_VECTOR__"); 1215 if (HasP8Crypto) 1216 Builder.defineMacro("__CRYPTO__"); 1217 if (HasHTM) 1218 Builder.defineMacro("__HTM__"); 1219 if (getTriple().getArch() == llvm::Triple::ppc64le || 1220 (defs & ArchDefinePwr8) || (CPU == "pwr8")) { 1221 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1222 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1223 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1224 if (PointerWidth == 64) 1225 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1226 } 1227 1228 // FIXME: The following are not yet generated here by Clang, but are 1229 // generated by GCC: 1230 // 1231 // _SOFT_FLOAT_ 1232 // __RECIP_PRECISION__ 1233 // __APPLE_ALTIVEC__ 1234 // __RECIP__ 1235 // __RECIPF__ 1236 // __RSQRTE__ 1237 // __RSQRTEF__ 1238 // _SOFT_DOUBLE_ 1239 // __NO_LWSYNC__ 1240 // __HAVE_BSWAP__ 1241 // __LONGDOUBLE128 1242 // __CMODEL_MEDIUM__ 1243 // __CMODEL_LARGE__ 1244 // _CALL_SYSV 1245 // _CALL_DARWIN 1246 // __NO_FPRS__ 1247 } 1248 1249 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1250 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1251 .Case("7400", true) 1252 .Case("g4", true) 1253 .Case("7450", true) 1254 .Case("g4+", true) 1255 .Case("970", true) 1256 .Case("g5", true) 1257 .Case("pwr6", true) 1258 .Case("pwr7", true) 1259 .Case("pwr8", true) 1260 .Case("ppc64", true) 1261 .Case("ppc64le", true) 1262 .Default(false); 1263 1264 Features["qpx"] = (CPU == "a2q"); 1265 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1266 .Case("ppc64le", true) 1267 .Case("pwr8", true) 1268 .Default(false); 1269 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1270 .Case("ppc64le", true) 1271 .Case("pwr8", true) 1272 .Default(false); 1273 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1274 .Case("ppc64le", true) 1275 .Case("pwr8", true) 1276 .Case("pwr7", true) 1277 .Default(false); 1278 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1279 .Case("ppc64le", true) 1280 .Case("pwr8", true) 1281 .Case("pwr7", true) 1282 .Default(false); 1283 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1284 .Case("ppc64le", true) 1285 .Case("pwr8", true) 1286 .Default(false); 1287 } 1288 1289 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1290 return llvm::StringSwitch<bool>(Feature) 1291 .Case("powerpc", true) 1292 .Case("vsx", HasVSX) 1293 .Case("power8-vector", HasP8Vector) 1294 .Case("crypto", HasP8Crypto) 1295 .Case("direct-move", HasDirectMove) 1296 .Case("qpx", HasQPX) 1297 .Case("htm", HasHTM) 1298 .Case("bpermd", HasBPERMD) 1299 .Case("extdiv", HasExtDiv) 1300 .Default(false); 1301 } 1302 1303 const char * const PPCTargetInfo::GCCRegNames[] = { 1304 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1305 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1306 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1307 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1308 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1309 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1310 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1311 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1312 "mq", "lr", "ctr", "ap", 1313 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1314 "xer", 1315 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1316 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1317 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1318 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1319 "vrsave", "vscr", 1320 "spe_acc", "spefscr", 1321 "sfp" 1322 }; 1323 1324 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1325 unsigned &NumNames) const { 1326 Names = GCCRegNames; 1327 NumNames = llvm::array_lengthof(GCCRegNames); 1328 } 1329 1330 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1331 // While some of these aliases do map to different registers 1332 // they still share the same register name. 1333 { { "0" }, "r0" }, 1334 { { "1"}, "r1" }, 1335 { { "2" }, "r2" }, 1336 { { "3" }, "r3" }, 1337 { { "4" }, "r4" }, 1338 { { "5" }, "r5" }, 1339 { { "6" }, "r6" }, 1340 { { "7" }, "r7" }, 1341 { { "8" }, "r8" }, 1342 { { "9" }, "r9" }, 1343 { { "10" }, "r10" }, 1344 { { "11" }, "r11" }, 1345 { { "12" }, "r12" }, 1346 { { "13" }, "r13" }, 1347 { { "14" }, "r14" }, 1348 { { "15" }, "r15" }, 1349 { { "16" }, "r16" }, 1350 { { "17" }, "r17" }, 1351 { { "18" }, "r18" }, 1352 { { "19" }, "r19" }, 1353 { { "20" }, "r20" }, 1354 { { "21" }, "r21" }, 1355 { { "22" }, "r22" }, 1356 { { "23" }, "r23" }, 1357 { { "24" }, "r24" }, 1358 { { "25" }, "r25" }, 1359 { { "26" }, "r26" }, 1360 { { "27" }, "r27" }, 1361 { { "28" }, "r28" }, 1362 { { "29" }, "r29" }, 1363 { { "30" }, "r30" }, 1364 { { "31" }, "r31" }, 1365 { { "fr0" }, "f0" }, 1366 { { "fr1" }, "f1" }, 1367 { { "fr2" }, "f2" }, 1368 { { "fr3" }, "f3" }, 1369 { { "fr4" }, "f4" }, 1370 { { "fr5" }, "f5" }, 1371 { { "fr6" }, "f6" }, 1372 { { "fr7" }, "f7" }, 1373 { { "fr8" }, "f8" }, 1374 { { "fr9" }, "f9" }, 1375 { { "fr10" }, "f10" }, 1376 { { "fr11" }, "f11" }, 1377 { { "fr12" }, "f12" }, 1378 { { "fr13" }, "f13" }, 1379 { { "fr14" }, "f14" }, 1380 { { "fr15" }, "f15" }, 1381 { { "fr16" }, "f16" }, 1382 { { "fr17" }, "f17" }, 1383 { { "fr18" }, "f18" }, 1384 { { "fr19" }, "f19" }, 1385 { { "fr20" }, "f20" }, 1386 { { "fr21" }, "f21" }, 1387 { { "fr22" }, "f22" }, 1388 { { "fr23" }, "f23" }, 1389 { { "fr24" }, "f24" }, 1390 { { "fr25" }, "f25" }, 1391 { { "fr26" }, "f26" }, 1392 { { "fr27" }, "f27" }, 1393 { { "fr28" }, "f28" }, 1394 { { "fr29" }, "f29" }, 1395 { { "fr30" }, "f30" }, 1396 { { "fr31" }, "f31" }, 1397 { { "cc" }, "cr0" }, 1398 }; 1399 1400 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1401 unsigned &NumAliases) const { 1402 Aliases = GCCRegAliases; 1403 NumAliases = llvm::array_lengthof(GCCRegAliases); 1404 } 1405 1406 class PPC32TargetInfo : public PPCTargetInfo { 1407 public: 1408 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1409 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1410 1411 switch (getTriple().getOS()) { 1412 case llvm::Triple::Linux: 1413 case llvm::Triple::FreeBSD: 1414 case llvm::Triple::NetBSD: 1415 SizeType = UnsignedInt; 1416 PtrDiffType = SignedInt; 1417 IntPtrType = SignedInt; 1418 break; 1419 default: 1420 break; 1421 } 1422 1423 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1424 LongDoubleWidth = LongDoubleAlign = 64; 1425 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1426 } 1427 1428 // PPC32 supports atomics up to 4 bytes. 1429 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1430 } 1431 1432 BuiltinVaListKind getBuiltinVaListKind() const override { 1433 // This is the ELF definition, and is overridden by the Darwin sub-target 1434 return TargetInfo::PowerABIBuiltinVaList; 1435 } 1436 }; 1437 1438 // Note: ABI differences may eventually require us to have a separate 1439 // TargetInfo for little endian. 1440 class PPC64TargetInfo : public PPCTargetInfo { 1441 public: 1442 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1443 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1444 IntMaxType = SignedLong; 1445 Int64Type = SignedLong; 1446 1447 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1448 DescriptionString = "e-m:e-i64:64-n32:64"; 1449 ABI = "elfv2"; 1450 } else { 1451 DescriptionString = "E-m:e-i64:64-n32:64"; 1452 ABI = "elfv1"; 1453 } 1454 1455 switch (getTriple().getOS()) { 1456 case llvm::Triple::FreeBSD: 1457 LongDoubleWidth = LongDoubleAlign = 64; 1458 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1459 break; 1460 case llvm::Triple::NetBSD: 1461 IntMaxType = SignedLongLong; 1462 Int64Type = SignedLongLong; 1463 break; 1464 default: 1465 break; 1466 } 1467 1468 // PPC64 supports atomics up to 8 bytes. 1469 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1470 } 1471 BuiltinVaListKind getBuiltinVaListKind() const override { 1472 return TargetInfo::CharPtrBuiltinVaList; 1473 } 1474 // PPC64 Linux-specifc ABI options. 1475 bool setABI(const std::string &Name) override { 1476 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1477 ABI = Name; 1478 return true; 1479 } 1480 return false; 1481 } 1482 }; 1483 1484 class DarwinPPC32TargetInfo : 1485 public DarwinTargetInfo<PPC32TargetInfo> { 1486 public: 1487 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1488 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1489 HasAlignMac68kSupport = true; 1490 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1491 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1492 LongLongAlign = 32; 1493 SuitableAlign = 128; 1494 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1495 } 1496 BuiltinVaListKind getBuiltinVaListKind() const override { 1497 return TargetInfo::CharPtrBuiltinVaList; 1498 } 1499 }; 1500 1501 class DarwinPPC64TargetInfo : 1502 public DarwinTargetInfo<PPC64TargetInfo> { 1503 public: 1504 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1505 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1506 HasAlignMac68kSupport = true; 1507 SuitableAlign = 128; 1508 DescriptionString = "E-m:o-i64:64-n32:64"; 1509 } 1510 }; 1511 1512 static const unsigned NVPTXAddrSpaceMap[] = { 1513 1, // opencl_global 1514 3, // opencl_local 1515 4, // opencl_constant 1516 // FIXME: generic has to be added to the target 1517 0, // opencl_generic 1518 1, // cuda_device 1519 4, // cuda_constant 1520 3, // cuda_shared 1521 }; 1522 class NVPTXTargetInfo : public TargetInfo { 1523 static const char * const GCCRegNames[]; 1524 static const Builtin::Info BuiltinInfo[]; 1525 1526 // The GPU profiles supported by the NVPTX backend 1527 enum GPUKind { 1528 GK_NONE, 1529 GK_SM20, 1530 GK_SM21, 1531 GK_SM30, 1532 GK_SM35, 1533 GK_SM37, 1534 } GPU; 1535 1536 public: 1537 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1538 BigEndian = false; 1539 TLSSupported = false; 1540 LongWidth = LongAlign = 64; 1541 AddrSpaceMap = &NVPTXAddrSpaceMap; 1542 UseAddrSpaceMapMangling = true; 1543 // Define available target features 1544 // These must be defined in sorted order! 1545 NoAsmVariants = true; 1546 // Set the default GPU to sm20 1547 GPU = GK_SM20; 1548 } 1549 void getTargetDefines(const LangOptions &Opts, 1550 MacroBuilder &Builder) const override { 1551 Builder.defineMacro("__PTX__"); 1552 Builder.defineMacro("__NVPTX__"); 1553 if (Opts.CUDAIsDevice) { 1554 // Set __CUDA_ARCH__ for the GPU specified. 1555 std::string CUDAArchCode; 1556 switch (GPU) { 1557 case GK_SM20: 1558 CUDAArchCode = "200"; 1559 break; 1560 case GK_SM21: 1561 CUDAArchCode = "210"; 1562 break; 1563 case GK_SM30: 1564 CUDAArchCode = "300"; 1565 break; 1566 case GK_SM35: 1567 CUDAArchCode = "350"; 1568 break; 1569 case GK_SM37: 1570 CUDAArchCode = "370"; 1571 break; 1572 default: 1573 llvm_unreachable("Unhandled target CPU"); 1574 } 1575 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1576 } 1577 } 1578 void getTargetBuiltins(const Builtin::Info *&Records, 1579 unsigned &NumRecords) const override { 1580 Records = BuiltinInfo; 1581 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1582 } 1583 bool hasFeature(StringRef Feature) const override { 1584 return Feature == "ptx" || Feature == "nvptx"; 1585 } 1586 1587 void getGCCRegNames(const char * const *&Names, 1588 unsigned &NumNames) const override; 1589 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1590 unsigned &NumAliases) const override { 1591 // No aliases. 1592 Aliases = nullptr; 1593 NumAliases = 0; 1594 } 1595 bool 1596 validateAsmConstraint(const char *&Name, 1597 TargetInfo::ConstraintInfo &Info) const override { 1598 switch (*Name) { 1599 default: return false; 1600 case 'c': 1601 case 'h': 1602 case 'r': 1603 case 'l': 1604 case 'f': 1605 case 'd': 1606 Info.setAllowsRegister(); 1607 return true; 1608 } 1609 } 1610 const char *getClobbers() const override { 1611 // FIXME: Is this really right? 1612 return ""; 1613 } 1614 BuiltinVaListKind getBuiltinVaListKind() const override { 1615 // FIXME: implement 1616 return TargetInfo::CharPtrBuiltinVaList; 1617 } 1618 bool setCPU(const std::string &Name) override { 1619 GPU = llvm::StringSwitch<GPUKind>(Name) 1620 .Case("sm_20", GK_SM20) 1621 .Case("sm_21", GK_SM21) 1622 .Case("sm_30", GK_SM30) 1623 .Case("sm_35", GK_SM35) 1624 .Case("sm_37", GK_SM37) 1625 .Default(GK_NONE); 1626 1627 return GPU != GK_NONE; 1628 } 1629 }; 1630 1631 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1632 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1633 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1634 ALL_LANGUAGES }, 1635 #include "clang/Basic/BuiltinsNVPTX.def" 1636 }; 1637 1638 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1639 "r0" 1640 }; 1641 1642 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1643 unsigned &NumNames) const { 1644 Names = GCCRegNames; 1645 NumNames = llvm::array_lengthof(GCCRegNames); 1646 } 1647 1648 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1649 public: 1650 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1651 PointerWidth = PointerAlign = 32; 1652 SizeType = TargetInfo::UnsignedInt; 1653 PtrDiffType = TargetInfo::SignedInt; 1654 IntPtrType = TargetInfo::SignedInt; 1655 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1656 } 1657 }; 1658 1659 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1660 public: 1661 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1662 PointerWidth = PointerAlign = 64; 1663 SizeType = TargetInfo::UnsignedLong; 1664 PtrDiffType = TargetInfo::SignedLong; 1665 IntPtrType = TargetInfo::SignedLong; 1666 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1667 } 1668 }; 1669 1670 static const unsigned AMDGPUAddrSpaceMap[] = { 1671 1, // opencl_global 1672 3, // opencl_local 1673 2, // opencl_constant 1674 4, // opencl_generic 1675 1, // cuda_device 1676 2, // cuda_constant 1677 3 // cuda_shared 1678 }; 1679 1680 // If you edit the description strings, make sure you update 1681 // getPointerWidthV(). 1682 1683 static const char *DescriptionStringR600 = 1684 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1685 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1686 1687 static const char *DescriptionStringR600DoubleOps = 1688 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1689 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1690 1691 static const char *DescriptionStringSI = 1692 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1693 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1694 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1695 1696 class AMDGPUTargetInfo : public TargetInfo { 1697 static const Builtin::Info BuiltinInfo[]; 1698 static const char * const GCCRegNames[]; 1699 1700 /// \brief The GPU profiles supported by the AMDGPU target. 1701 enum GPUKind { 1702 GK_NONE, 1703 GK_R600, 1704 GK_R600_DOUBLE_OPS, 1705 GK_R700, 1706 GK_R700_DOUBLE_OPS, 1707 GK_EVERGREEN, 1708 GK_EVERGREEN_DOUBLE_OPS, 1709 GK_NORTHERN_ISLANDS, 1710 GK_CAYMAN, 1711 GK_SOUTHERN_ISLANDS, 1712 GK_SEA_ISLANDS, 1713 GK_VOLCANIC_ISLANDS 1714 } GPU; 1715 1716 bool hasFP64:1; 1717 bool hasFMAF:1; 1718 bool hasLDEXPF:1; 1719 1720 public: 1721 AMDGPUTargetInfo(const llvm::Triple &Triple) 1722 : TargetInfo(Triple) { 1723 1724 if (Triple.getArch() == llvm::Triple::amdgcn) { 1725 DescriptionString = DescriptionStringSI; 1726 GPU = GK_SOUTHERN_ISLANDS; 1727 hasFP64 = true; 1728 hasFMAF = true; 1729 hasLDEXPF = true; 1730 } else { 1731 DescriptionString = DescriptionStringR600; 1732 GPU = GK_R600; 1733 hasFP64 = false; 1734 hasFMAF = false; 1735 hasLDEXPF = false; 1736 } 1737 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1738 UseAddrSpaceMapMangling = true; 1739 } 1740 1741 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1742 if (GPU <= GK_CAYMAN) 1743 return 32; 1744 1745 switch(AddrSpace) { 1746 default: 1747 return 64; 1748 case 0: 1749 case 3: 1750 case 5: 1751 return 32; 1752 } 1753 } 1754 1755 const char * getClobbers() const override { 1756 return ""; 1757 } 1758 1759 void getGCCRegNames(const char * const *&Names, 1760 unsigned &NumNames) const override; 1761 1762 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1763 unsigned &NumAliases) const override { 1764 Aliases = nullptr; 1765 NumAliases = 0; 1766 } 1767 1768 bool validateAsmConstraint(const char *&Name, 1769 TargetInfo::ConstraintInfo &info) const override { 1770 return true; 1771 } 1772 1773 void getTargetBuiltins(const Builtin::Info *&Records, 1774 unsigned &NumRecords) const override { 1775 Records = BuiltinInfo; 1776 NumRecords = clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin; 1777 } 1778 1779 void getTargetDefines(const LangOptions &Opts, 1780 MacroBuilder &Builder) const override { 1781 Builder.defineMacro("__R600__"); 1782 if (hasFMAF) 1783 Builder.defineMacro("__HAS_FMAF__"); 1784 if (hasLDEXPF) 1785 Builder.defineMacro("__HAS_LDEXPF__"); 1786 if (hasFP64 && Opts.OpenCL) { 1787 Builder.defineMacro("cl_khr_fp64"); 1788 } 1789 } 1790 1791 BuiltinVaListKind getBuiltinVaListKind() const override { 1792 return TargetInfo::CharPtrBuiltinVaList; 1793 } 1794 1795 bool setCPU(const std::string &Name) override { 1796 GPU = llvm::StringSwitch<GPUKind>(Name) 1797 .Case("r600" , GK_R600) 1798 .Case("rv610", GK_R600) 1799 .Case("rv620", GK_R600) 1800 .Case("rv630", GK_R600) 1801 .Case("rv635", GK_R600) 1802 .Case("rs780", GK_R600) 1803 .Case("rs880", GK_R600) 1804 .Case("rv670", GK_R600_DOUBLE_OPS) 1805 .Case("rv710", GK_R700) 1806 .Case("rv730", GK_R700) 1807 .Case("rv740", GK_R700_DOUBLE_OPS) 1808 .Case("rv770", GK_R700_DOUBLE_OPS) 1809 .Case("palm", GK_EVERGREEN) 1810 .Case("cedar", GK_EVERGREEN) 1811 .Case("sumo", GK_EVERGREEN) 1812 .Case("sumo2", GK_EVERGREEN) 1813 .Case("redwood", GK_EVERGREEN) 1814 .Case("juniper", GK_EVERGREEN) 1815 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1816 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1817 .Case("barts", GK_NORTHERN_ISLANDS) 1818 .Case("turks", GK_NORTHERN_ISLANDS) 1819 .Case("caicos", GK_NORTHERN_ISLANDS) 1820 .Case("cayman", GK_CAYMAN) 1821 .Case("aruba", GK_CAYMAN) 1822 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1823 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1824 .Case("verde", GK_SOUTHERN_ISLANDS) 1825 .Case("oland", GK_SOUTHERN_ISLANDS) 1826 .Case("hainan", GK_SOUTHERN_ISLANDS) 1827 .Case("bonaire", GK_SEA_ISLANDS) 1828 .Case("kabini", GK_SEA_ISLANDS) 1829 .Case("kaveri", GK_SEA_ISLANDS) 1830 .Case("hawaii", GK_SEA_ISLANDS) 1831 .Case("mullins", GK_SEA_ISLANDS) 1832 .Case("tonga", GK_VOLCANIC_ISLANDS) 1833 .Case("iceland", GK_VOLCANIC_ISLANDS) 1834 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1835 .Default(GK_NONE); 1836 1837 if (GPU == GK_NONE) { 1838 return false; 1839 } 1840 1841 // Set the correct data layout 1842 switch (GPU) { 1843 case GK_NONE: 1844 case GK_R600: 1845 case GK_R700: 1846 case GK_EVERGREEN: 1847 case GK_NORTHERN_ISLANDS: 1848 DescriptionString = DescriptionStringR600; 1849 hasFP64 = false; 1850 hasFMAF = false; 1851 hasLDEXPF = false; 1852 break; 1853 case GK_R600_DOUBLE_OPS: 1854 case GK_R700_DOUBLE_OPS: 1855 case GK_EVERGREEN_DOUBLE_OPS: 1856 case GK_CAYMAN: 1857 DescriptionString = DescriptionStringR600DoubleOps; 1858 hasFP64 = true; 1859 hasFMAF = true; 1860 hasLDEXPF = false; 1861 break; 1862 case GK_SOUTHERN_ISLANDS: 1863 case GK_SEA_ISLANDS: 1864 case GK_VOLCANIC_ISLANDS: 1865 DescriptionString = DescriptionStringSI; 1866 hasFP64 = true; 1867 hasFMAF = true; 1868 hasLDEXPF = true; 1869 break; 1870 } 1871 1872 return true; 1873 } 1874 }; 1875 1876 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1877 #define BUILTIN(ID, TYPE, ATTRS) \ 1878 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1879 #include "clang/Basic/BuiltinsAMDGPU.def" 1880 }; 1881 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1882 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1883 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1884 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1885 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1886 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1887 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1888 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1889 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1890 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1891 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1892 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1893 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1894 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1895 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1896 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1897 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1898 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1899 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1900 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1901 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1902 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1903 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1904 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1905 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1906 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1907 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1908 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1909 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1910 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1911 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1912 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1913 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1914 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1915 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1916 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1917 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1918 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1919 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1920 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1921 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1922 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1923 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 1924 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 1925 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 1926 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 1927 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 1928 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 1929 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 1930 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 1931 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 1932 }; 1933 1934 void AMDGPUTargetInfo::getGCCRegNames(const char * const *&Names, 1935 unsigned &NumNames) const { 1936 Names = GCCRegNames; 1937 NumNames = llvm::array_lengthof(GCCRegNames); 1938 } 1939 1940 // Namespace for x86 abstract base class 1941 const Builtin::Info BuiltinInfo[] = { 1942 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1943 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1944 ALL_LANGUAGES }, 1945 #include "clang/Basic/BuiltinsX86.def" 1946 }; 1947 1948 static const char* const GCCRegNames[] = { 1949 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1950 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1951 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1952 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1953 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1954 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1955 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1956 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1957 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1958 }; 1959 1960 const TargetInfo::AddlRegName AddlRegNames[] = { 1961 { { "al", "ah", "eax", "rax" }, 0 }, 1962 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1963 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1964 { { "dl", "dh", "edx", "rdx" }, 1 }, 1965 { { "esi", "rsi" }, 4 }, 1966 { { "edi", "rdi" }, 5 }, 1967 { { "esp", "rsp" }, 7 }, 1968 { { "ebp", "rbp" }, 6 }, 1969 }; 1970 1971 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1972 // most of the implementation can be shared. 1973 class X86TargetInfo : public TargetInfo { 1974 enum X86SSEEnum { 1975 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1976 } SSELevel; 1977 enum MMX3DNowEnum { 1978 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1979 } MMX3DNowLevel; 1980 enum XOPEnum { 1981 NoXOP, 1982 SSE4A, 1983 FMA4, 1984 XOP 1985 } XOPLevel; 1986 1987 bool HasAES; 1988 bool HasPCLMUL; 1989 bool HasLZCNT; 1990 bool HasRDRND; 1991 bool HasFSGSBASE; 1992 bool HasBMI; 1993 bool HasBMI2; 1994 bool HasPOPCNT; 1995 bool HasRTM; 1996 bool HasPRFCHW; 1997 bool HasRDSEED; 1998 bool HasADX; 1999 bool HasTBM; 2000 bool HasFMA; 2001 bool HasF16C; 2002 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 2003 HasAVX512VL; 2004 bool HasSHA; 2005 bool HasCX16; 2006 2007 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2008 /// 2009 /// Each enumeration represents a particular CPU supported by Clang. These 2010 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2011 enum CPUKind { 2012 CK_Generic, 2013 2014 /// \name i386 2015 /// i386-generation processors. 2016 //@{ 2017 CK_i386, 2018 //@} 2019 2020 /// \name i486 2021 /// i486-generation processors. 2022 //@{ 2023 CK_i486, 2024 CK_WinChipC6, 2025 CK_WinChip2, 2026 CK_C3, 2027 //@} 2028 2029 /// \name i586 2030 /// i586-generation processors, P5 microarchitecture based. 2031 //@{ 2032 CK_i586, 2033 CK_Pentium, 2034 CK_PentiumMMX, 2035 //@} 2036 2037 /// \name i686 2038 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2039 //@{ 2040 CK_i686, 2041 CK_PentiumPro, 2042 CK_Pentium2, 2043 CK_Pentium3, 2044 CK_Pentium3M, 2045 CK_PentiumM, 2046 CK_C3_2, 2047 2048 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2049 /// Clang however has some logic to suport this. 2050 // FIXME: Warn, deprecate, and potentially remove this. 2051 CK_Yonah, 2052 //@} 2053 2054 /// \name Netburst 2055 /// Netburst microarchitecture based processors. 2056 //@{ 2057 CK_Pentium4, 2058 CK_Pentium4M, 2059 CK_Prescott, 2060 CK_Nocona, 2061 //@} 2062 2063 /// \name Core 2064 /// Core microarchitecture based processors. 2065 //@{ 2066 CK_Core2, 2067 2068 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2069 /// codename which GCC no longer accepts as an option to -march, but Clang 2070 /// has some logic for recognizing it. 2071 // FIXME: Warn, deprecate, and potentially remove this. 2072 CK_Penryn, 2073 //@} 2074 2075 /// \name Atom 2076 /// Atom processors 2077 //@{ 2078 CK_Bonnell, 2079 CK_Silvermont, 2080 //@} 2081 2082 /// \name Nehalem 2083 /// Nehalem microarchitecture based processors. 2084 CK_Nehalem, 2085 2086 /// \name Westmere 2087 /// Westmere microarchitecture based processors. 2088 CK_Westmere, 2089 2090 /// \name Sandy Bridge 2091 /// Sandy Bridge microarchitecture based processors. 2092 CK_SandyBridge, 2093 2094 /// \name Ivy Bridge 2095 /// Ivy Bridge microarchitecture based processors. 2096 CK_IvyBridge, 2097 2098 /// \name Haswell 2099 /// Haswell microarchitecture based processors. 2100 CK_Haswell, 2101 2102 /// \name Broadwell 2103 /// Broadwell microarchitecture based processors. 2104 CK_Broadwell, 2105 2106 /// \name Skylake 2107 /// Skylake microarchitecture based processors. 2108 CK_Skylake, 2109 2110 /// \name Knights Landing 2111 /// Knights Landing processor. 2112 CK_KNL, 2113 2114 /// \name K6 2115 /// K6 architecture processors. 2116 //@{ 2117 CK_K6, 2118 CK_K6_2, 2119 CK_K6_3, 2120 //@} 2121 2122 /// \name K7 2123 /// K7 architecture processors. 2124 //@{ 2125 CK_Athlon, 2126 CK_AthlonThunderbird, 2127 CK_Athlon4, 2128 CK_AthlonXP, 2129 CK_AthlonMP, 2130 //@} 2131 2132 /// \name K8 2133 /// K8 architecture processors. 2134 //@{ 2135 CK_Athlon64, 2136 CK_Athlon64SSE3, 2137 CK_AthlonFX, 2138 CK_K8, 2139 CK_K8SSE3, 2140 CK_Opteron, 2141 CK_OpteronSSE3, 2142 CK_AMDFAM10, 2143 //@} 2144 2145 /// \name Bobcat 2146 /// Bobcat architecture processors. 2147 //@{ 2148 CK_BTVER1, 2149 CK_BTVER2, 2150 //@} 2151 2152 /// \name Bulldozer 2153 /// Bulldozer architecture processors. 2154 //@{ 2155 CK_BDVER1, 2156 CK_BDVER2, 2157 CK_BDVER3, 2158 CK_BDVER4, 2159 //@} 2160 2161 /// This specification is deprecated and will be removed in the future. 2162 /// Users should prefer \see CK_K8. 2163 // FIXME: Warn on this when the CPU is set to it. 2164 //@{ 2165 CK_x86_64, 2166 //@} 2167 2168 /// \name Geode 2169 /// Geode processors. 2170 //@{ 2171 CK_Geode 2172 //@} 2173 } CPU; 2174 2175 enum FPMathKind { 2176 FP_Default, 2177 FP_SSE, 2178 FP_387 2179 } FPMath; 2180 2181 public: 2182 X86TargetInfo(const llvm::Triple &Triple) 2183 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 2184 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 2185 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 2186 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 2187 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 2188 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 2189 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 2190 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 2191 BigEndian = false; 2192 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2193 } 2194 unsigned getFloatEvalMethod() const override { 2195 // X87 evaluates with 80 bits "long double" precision. 2196 return SSELevel == NoSSE ? 2 : 0; 2197 } 2198 void getTargetBuiltins(const Builtin::Info *&Records, 2199 unsigned &NumRecords) const override { 2200 Records = BuiltinInfo; 2201 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 2202 } 2203 void getGCCRegNames(const char * const *&Names, 2204 unsigned &NumNames) const override { 2205 Names = GCCRegNames; 2206 NumNames = llvm::array_lengthof(GCCRegNames); 2207 } 2208 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2209 unsigned &NumAliases) const override { 2210 Aliases = nullptr; 2211 NumAliases = 0; 2212 } 2213 void getGCCAddlRegNames(const AddlRegName *&Names, 2214 unsigned &NumNames) const override { 2215 Names = AddlRegNames; 2216 NumNames = llvm::array_lengthof(AddlRegNames); 2217 } 2218 bool validateAsmConstraint(const char *&Name, 2219 TargetInfo::ConstraintInfo &info) const override; 2220 2221 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2222 2223 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2224 2225 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2226 2227 std::string convertConstraint(const char *&Constraint) const override; 2228 const char *getClobbers() const override { 2229 return "~{dirflag},~{fpsr},~{flags}"; 2230 } 2231 void getTargetDefines(const LangOptions &Opts, 2232 MacroBuilder &Builder) const override; 2233 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2234 bool Enabled); 2235 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2236 bool Enabled); 2237 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2238 bool Enabled); 2239 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2240 StringRef Name, bool Enabled) const override { 2241 setFeatureEnabledImpl(Features, Name, Enabled); 2242 } 2243 // This exists purely to cut down on the number of virtual calls in 2244 // getDefaultFeatures which calls this repeatedly. 2245 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2246 StringRef Name, bool Enabled); 2247 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 2248 bool hasFeature(StringRef Feature) const override; 2249 bool handleTargetFeatures(std::vector<std::string> &Features, 2250 DiagnosticsEngine &Diags) override; 2251 StringRef getABI() const override { 2252 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2253 return "avx512"; 2254 else if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2255 return "avx"; 2256 else if (getTriple().getArch() == llvm::Triple::x86 && 2257 MMX3DNowLevel == NoMMX3DNow) 2258 return "no-mmx"; 2259 return ""; 2260 } 2261 bool setCPU(const std::string &Name) override { 2262 CPU = llvm::StringSwitch<CPUKind>(Name) 2263 .Case("i386", CK_i386) 2264 .Case("i486", CK_i486) 2265 .Case("winchip-c6", CK_WinChipC6) 2266 .Case("winchip2", CK_WinChip2) 2267 .Case("c3", CK_C3) 2268 .Case("i586", CK_i586) 2269 .Case("pentium", CK_Pentium) 2270 .Case("pentium-mmx", CK_PentiumMMX) 2271 .Case("i686", CK_i686) 2272 .Case("pentiumpro", CK_PentiumPro) 2273 .Case("pentium2", CK_Pentium2) 2274 .Case("pentium3", CK_Pentium3) 2275 .Case("pentium3m", CK_Pentium3M) 2276 .Case("pentium-m", CK_PentiumM) 2277 .Case("c3-2", CK_C3_2) 2278 .Case("yonah", CK_Yonah) 2279 .Case("pentium4", CK_Pentium4) 2280 .Case("pentium4m", CK_Pentium4M) 2281 .Case("prescott", CK_Prescott) 2282 .Case("nocona", CK_Nocona) 2283 .Case("core2", CK_Core2) 2284 .Case("penryn", CK_Penryn) 2285 .Case("bonnell", CK_Bonnell) 2286 .Case("atom", CK_Bonnell) // Legacy name. 2287 .Case("silvermont", CK_Silvermont) 2288 .Case("slm", CK_Silvermont) // Legacy name. 2289 .Case("nehalem", CK_Nehalem) 2290 .Case("corei7", CK_Nehalem) // Legacy name. 2291 .Case("westmere", CK_Westmere) 2292 .Case("sandybridge", CK_SandyBridge) 2293 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2294 .Case("ivybridge", CK_IvyBridge) 2295 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2296 .Case("haswell", CK_Haswell) 2297 .Case("core-avx2", CK_Haswell) // Legacy name. 2298 .Case("broadwell", CK_Broadwell) 2299 .Case("skylake", CK_Skylake) 2300 .Case("skx", CK_Skylake) // Legacy name. 2301 .Case("knl", CK_KNL) 2302 .Case("k6", CK_K6) 2303 .Case("k6-2", CK_K6_2) 2304 .Case("k6-3", CK_K6_3) 2305 .Case("athlon", CK_Athlon) 2306 .Case("athlon-tbird", CK_AthlonThunderbird) 2307 .Case("athlon-4", CK_Athlon4) 2308 .Case("athlon-xp", CK_AthlonXP) 2309 .Case("athlon-mp", CK_AthlonMP) 2310 .Case("athlon64", CK_Athlon64) 2311 .Case("athlon64-sse3", CK_Athlon64SSE3) 2312 .Case("athlon-fx", CK_AthlonFX) 2313 .Case("k8", CK_K8) 2314 .Case("k8-sse3", CK_K8SSE3) 2315 .Case("opteron", CK_Opteron) 2316 .Case("opteron-sse3", CK_OpteronSSE3) 2317 .Case("barcelona", CK_AMDFAM10) 2318 .Case("amdfam10", CK_AMDFAM10) 2319 .Case("btver1", CK_BTVER1) 2320 .Case("btver2", CK_BTVER2) 2321 .Case("bdver1", CK_BDVER1) 2322 .Case("bdver2", CK_BDVER2) 2323 .Case("bdver3", CK_BDVER3) 2324 .Case("bdver4", CK_BDVER4) 2325 .Case("x86-64", CK_x86_64) 2326 .Case("geode", CK_Geode) 2327 .Default(CK_Generic); 2328 2329 // Perform any per-CPU checks necessary to determine if this CPU is 2330 // acceptable. 2331 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2332 // invalid without explaining *why*. 2333 switch (CPU) { 2334 case CK_Generic: 2335 // No processor selected! 2336 return false; 2337 2338 case CK_i386: 2339 case CK_i486: 2340 case CK_WinChipC6: 2341 case CK_WinChip2: 2342 case CK_C3: 2343 case CK_i586: 2344 case CK_Pentium: 2345 case CK_PentiumMMX: 2346 case CK_i686: 2347 case CK_PentiumPro: 2348 case CK_Pentium2: 2349 case CK_Pentium3: 2350 case CK_Pentium3M: 2351 case CK_PentiumM: 2352 case CK_Yonah: 2353 case CK_C3_2: 2354 case CK_Pentium4: 2355 case CK_Pentium4M: 2356 case CK_Prescott: 2357 case CK_K6: 2358 case CK_K6_2: 2359 case CK_K6_3: 2360 case CK_Athlon: 2361 case CK_AthlonThunderbird: 2362 case CK_Athlon4: 2363 case CK_AthlonXP: 2364 case CK_AthlonMP: 2365 case CK_Geode: 2366 // Only accept certain architectures when compiling in 32-bit mode. 2367 if (getTriple().getArch() != llvm::Triple::x86) 2368 return false; 2369 2370 // Fallthrough 2371 case CK_Nocona: 2372 case CK_Core2: 2373 case CK_Penryn: 2374 case CK_Bonnell: 2375 case CK_Silvermont: 2376 case CK_Nehalem: 2377 case CK_Westmere: 2378 case CK_SandyBridge: 2379 case CK_IvyBridge: 2380 case CK_Haswell: 2381 case CK_Broadwell: 2382 case CK_Skylake: 2383 case CK_KNL: 2384 case CK_Athlon64: 2385 case CK_Athlon64SSE3: 2386 case CK_AthlonFX: 2387 case CK_K8: 2388 case CK_K8SSE3: 2389 case CK_Opteron: 2390 case CK_OpteronSSE3: 2391 case CK_AMDFAM10: 2392 case CK_BTVER1: 2393 case CK_BTVER2: 2394 case CK_BDVER1: 2395 case CK_BDVER2: 2396 case CK_BDVER3: 2397 case CK_BDVER4: 2398 case CK_x86_64: 2399 return true; 2400 } 2401 llvm_unreachable("Unhandled CPU kind"); 2402 } 2403 2404 bool setFPMath(StringRef Name) override; 2405 2406 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2407 // We accept all non-ARM calling conventions 2408 return (CC == CC_X86ThisCall || 2409 CC == CC_X86FastCall || 2410 CC == CC_X86StdCall || 2411 CC == CC_X86VectorCall || 2412 CC == CC_C || 2413 CC == CC_X86Pascal || 2414 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2415 } 2416 2417 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2418 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2419 } 2420 2421 bool hasSjLjLowering() const override { 2422 return true; 2423 } 2424 }; 2425 2426 bool X86TargetInfo::setFPMath(StringRef Name) { 2427 if (Name == "387") { 2428 FPMath = FP_387; 2429 return true; 2430 } 2431 if (Name == "sse") { 2432 FPMath = FP_SSE; 2433 return true; 2434 } 2435 return false; 2436 } 2437 2438 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2439 // FIXME: This *really* should not be here. 2440 2441 // X86_64 always has SSE2. 2442 if (getTriple().getArch() == llvm::Triple::x86_64) 2443 setFeatureEnabledImpl(Features, "sse2", true); 2444 2445 switch (CPU) { 2446 case CK_Generic: 2447 case CK_i386: 2448 case CK_i486: 2449 case CK_i586: 2450 case CK_Pentium: 2451 case CK_i686: 2452 case CK_PentiumPro: 2453 break; 2454 case CK_PentiumMMX: 2455 case CK_Pentium2: 2456 case CK_K6: 2457 case CK_WinChipC6: 2458 setFeatureEnabledImpl(Features, "mmx", true); 2459 break; 2460 case CK_Pentium3: 2461 case CK_Pentium3M: 2462 case CK_C3_2: 2463 setFeatureEnabledImpl(Features, "sse", true); 2464 break; 2465 case CK_PentiumM: 2466 case CK_Pentium4: 2467 case CK_Pentium4M: 2468 case CK_x86_64: 2469 setFeatureEnabledImpl(Features, "sse2", true); 2470 break; 2471 case CK_Yonah: 2472 case CK_Prescott: 2473 case CK_Nocona: 2474 setFeatureEnabledImpl(Features, "sse3", true); 2475 setFeatureEnabledImpl(Features, "cx16", true); 2476 break; 2477 case CK_Core2: 2478 case CK_Bonnell: 2479 setFeatureEnabledImpl(Features, "ssse3", true); 2480 setFeatureEnabledImpl(Features, "cx16", true); 2481 break; 2482 case CK_Penryn: 2483 setFeatureEnabledImpl(Features, "sse4.1", true); 2484 setFeatureEnabledImpl(Features, "cx16", true); 2485 break; 2486 case CK_Skylake: 2487 setFeatureEnabledImpl(Features, "avx512f", true); 2488 setFeatureEnabledImpl(Features, "avx512cd", true); 2489 setFeatureEnabledImpl(Features, "avx512dq", true); 2490 setFeatureEnabledImpl(Features, "avx512bw", true); 2491 setFeatureEnabledImpl(Features, "avx512vl", true); 2492 // FALLTHROUGH 2493 case CK_Broadwell: 2494 setFeatureEnabledImpl(Features, "rdseed", true); 2495 setFeatureEnabledImpl(Features, "adx", true); 2496 // FALLTHROUGH 2497 case CK_Haswell: 2498 setFeatureEnabledImpl(Features, "avx2", true); 2499 setFeatureEnabledImpl(Features, "lzcnt", true); 2500 setFeatureEnabledImpl(Features, "bmi", true); 2501 setFeatureEnabledImpl(Features, "bmi2", true); 2502 setFeatureEnabledImpl(Features, "rtm", true); 2503 setFeatureEnabledImpl(Features, "fma", true); 2504 // FALLTHROUGH 2505 case CK_IvyBridge: 2506 setFeatureEnabledImpl(Features, "rdrnd", true); 2507 setFeatureEnabledImpl(Features, "f16c", true); 2508 setFeatureEnabledImpl(Features, "fsgsbase", true); 2509 // FALLTHROUGH 2510 case CK_SandyBridge: 2511 setFeatureEnabledImpl(Features, "avx", true); 2512 // FALLTHROUGH 2513 case CK_Westmere: 2514 case CK_Silvermont: 2515 setFeatureEnabledImpl(Features, "aes", true); 2516 setFeatureEnabledImpl(Features, "pclmul", true); 2517 // FALLTHROUGH 2518 case CK_Nehalem: 2519 setFeatureEnabledImpl(Features, "sse4.2", true); 2520 setFeatureEnabledImpl(Features, "cx16", true); 2521 break; 2522 case CK_KNL: 2523 setFeatureEnabledImpl(Features, "avx512f", true); 2524 setFeatureEnabledImpl(Features, "avx512cd", true); 2525 setFeatureEnabledImpl(Features, "avx512er", true); 2526 setFeatureEnabledImpl(Features, "avx512pf", true); 2527 setFeatureEnabledImpl(Features, "rdseed", true); 2528 setFeatureEnabledImpl(Features, "adx", true); 2529 setFeatureEnabledImpl(Features, "lzcnt", true); 2530 setFeatureEnabledImpl(Features, "bmi", true); 2531 setFeatureEnabledImpl(Features, "bmi2", true); 2532 setFeatureEnabledImpl(Features, "rtm", true); 2533 setFeatureEnabledImpl(Features, "fma", true); 2534 setFeatureEnabledImpl(Features, "rdrnd", true); 2535 setFeatureEnabledImpl(Features, "f16c", true); 2536 setFeatureEnabledImpl(Features, "fsgsbase", true); 2537 setFeatureEnabledImpl(Features, "aes", true); 2538 setFeatureEnabledImpl(Features, "pclmul", true); 2539 setFeatureEnabledImpl(Features, "cx16", true); 2540 break; 2541 case CK_K6_2: 2542 case CK_K6_3: 2543 case CK_WinChip2: 2544 case CK_C3: 2545 setFeatureEnabledImpl(Features, "3dnow", true); 2546 break; 2547 case CK_Athlon: 2548 case CK_AthlonThunderbird: 2549 case CK_Geode: 2550 setFeatureEnabledImpl(Features, "3dnowa", true); 2551 break; 2552 case CK_Athlon4: 2553 case CK_AthlonXP: 2554 case CK_AthlonMP: 2555 setFeatureEnabledImpl(Features, "sse", true); 2556 setFeatureEnabledImpl(Features, "3dnowa", true); 2557 break; 2558 case CK_K8: 2559 case CK_Opteron: 2560 case CK_Athlon64: 2561 case CK_AthlonFX: 2562 setFeatureEnabledImpl(Features, "sse2", true); 2563 setFeatureEnabledImpl(Features, "3dnowa", true); 2564 break; 2565 case CK_AMDFAM10: 2566 setFeatureEnabledImpl(Features, "sse4a", true); 2567 setFeatureEnabledImpl(Features, "lzcnt", true); 2568 setFeatureEnabledImpl(Features, "popcnt", true); 2569 // FALLTHROUGH 2570 case CK_K8SSE3: 2571 case CK_OpteronSSE3: 2572 case CK_Athlon64SSE3: 2573 setFeatureEnabledImpl(Features, "sse3", true); 2574 setFeatureEnabledImpl(Features, "3dnowa", true); 2575 break; 2576 case CK_BTVER2: 2577 setFeatureEnabledImpl(Features, "avx", true); 2578 setFeatureEnabledImpl(Features, "aes", true); 2579 setFeatureEnabledImpl(Features, "pclmul", true); 2580 setFeatureEnabledImpl(Features, "bmi", true); 2581 setFeatureEnabledImpl(Features, "f16c", true); 2582 // FALLTHROUGH 2583 case CK_BTVER1: 2584 setFeatureEnabledImpl(Features, "ssse3", true); 2585 setFeatureEnabledImpl(Features, "sse4a", true); 2586 setFeatureEnabledImpl(Features, "lzcnt", true); 2587 setFeatureEnabledImpl(Features, "popcnt", true); 2588 setFeatureEnabledImpl(Features, "prfchw", true); 2589 setFeatureEnabledImpl(Features, "cx16", true); 2590 break; 2591 case CK_BDVER4: 2592 setFeatureEnabledImpl(Features, "avx2", true); 2593 setFeatureEnabledImpl(Features, "bmi2", true); 2594 // FALLTHROUGH 2595 case CK_BDVER3: 2596 setFeatureEnabledImpl(Features, "fsgsbase", true); 2597 // FALLTHROUGH 2598 case CK_BDVER2: 2599 setFeatureEnabledImpl(Features, "bmi", true); 2600 setFeatureEnabledImpl(Features, "fma", true); 2601 setFeatureEnabledImpl(Features, "f16c", true); 2602 setFeatureEnabledImpl(Features, "tbm", true); 2603 // FALLTHROUGH 2604 case CK_BDVER1: 2605 // xop implies avx, sse4a and fma4. 2606 setFeatureEnabledImpl(Features, "xop", true); 2607 setFeatureEnabledImpl(Features, "lzcnt", true); 2608 setFeatureEnabledImpl(Features, "aes", true); 2609 setFeatureEnabledImpl(Features, "pclmul", true); 2610 setFeatureEnabledImpl(Features, "prfchw", true); 2611 setFeatureEnabledImpl(Features, "cx16", true); 2612 break; 2613 } 2614 } 2615 2616 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2617 X86SSEEnum Level, bool Enabled) { 2618 if (Enabled) { 2619 switch (Level) { 2620 case AVX512F: 2621 Features["avx512f"] = true; 2622 case AVX2: 2623 Features["avx2"] = true; 2624 case AVX: 2625 Features["avx"] = true; 2626 case SSE42: 2627 Features["sse4.2"] = true; 2628 case SSE41: 2629 Features["sse4.1"] = true; 2630 case SSSE3: 2631 Features["ssse3"] = true; 2632 case SSE3: 2633 Features["sse3"] = true; 2634 case SSE2: 2635 Features["sse2"] = true; 2636 case SSE1: 2637 Features["sse"] = true; 2638 case NoSSE: 2639 break; 2640 } 2641 return; 2642 } 2643 2644 switch (Level) { 2645 case NoSSE: 2646 case SSE1: 2647 Features["sse"] = false; 2648 case SSE2: 2649 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2650 Features["sha"] = false; 2651 case SSE3: 2652 Features["sse3"] = false; 2653 setXOPLevel(Features, NoXOP, false); 2654 case SSSE3: 2655 Features["ssse3"] = false; 2656 case SSE41: 2657 Features["sse4.1"] = false; 2658 case SSE42: 2659 Features["sse4.2"] = false; 2660 case AVX: 2661 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2662 setXOPLevel(Features, FMA4, false); 2663 case AVX2: 2664 Features["avx2"] = false; 2665 case AVX512F: 2666 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2667 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2668 Features["avx512vl"] = false; 2669 } 2670 } 2671 2672 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2673 MMX3DNowEnum Level, bool Enabled) { 2674 if (Enabled) { 2675 switch (Level) { 2676 case AMD3DNowAthlon: 2677 Features["3dnowa"] = true; 2678 case AMD3DNow: 2679 Features["3dnow"] = true; 2680 case MMX: 2681 Features["mmx"] = true; 2682 case NoMMX3DNow: 2683 break; 2684 } 2685 return; 2686 } 2687 2688 switch (Level) { 2689 case NoMMX3DNow: 2690 case MMX: 2691 Features["mmx"] = false; 2692 case AMD3DNow: 2693 Features["3dnow"] = false; 2694 case AMD3DNowAthlon: 2695 Features["3dnowa"] = false; 2696 } 2697 } 2698 2699 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2700 bool Enabled) { 2701 if (Enabled) { 2702 switch (Level) { 2703 case XOP: 2704 Features["xop"] = true; 2705 case FMA4: 2706 Features["fma4"] = true; 2707 setSSELevel(Features, AVX, true); 2708 case SSE4A: 2709 Features["sse4a"] = true; 2710 setSSELevel(Features, SSE3, true); 2711 case NoXOP: 2712 break; 2713 } 2714 return; 2715 } 2716 2717 switch (Level) { 2718 case NoXOP: 2719 case SSE4A: 2720 Features["sse4a"] = false; 2721 case FMA4: 2722 Features["fma4"] = false; 2723 case XOP: 2724 Features["xop"] = false; 2725 } 2726 } 2727 2728 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2729 StringRef Name, bool Enabled) { 2730 Features[Name] = Enabled; 2731 2732 if (Name == "mmx") { 2733 setMMXLevel(Features, MMX, Enabled); 2734 } else if (Name == "sse") { 2735 setSSELevel(Features, SSE1, Enabled); 2736 } else if (Name == "sse2") { 2737 setSSELevel(Features, SSE2, Enabled); 2738 } else if (Name == "sse3") { 2739 setSSELevel(Features, SSE3, Enabled); 2740 } else if (Name == "ssse3") { 2741 setSSELevel(Features, SSSE3, Enabled); 2742 } else if (Name == "sse4.2") { 2743 setSSELevel(Features, SSE42, Enabled); 2744 } else if (Name == "sse4.1") { 2745 setSSELevel(Features, SSE41, Enabled); 2746 } else if (Name == "3dnow") { 2747 setMMXLevel(Features, AMD3DNow, Enabled); 2748 } else if (Name == "3dnowa") { 2749 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2750 } else if (Name == "aes") { 2751 if (Enabled) 2752 setSSELevel(Features, SSE2, Enabled); 2753 } else if (Name == "pclmul") { 2754 if (Enabled) 2755 setSSELevel(Features, SSE2, Enabled); 2756 } else if (Name == "avx") { 2757 setSSELevel(Features, AVX, Enabled); 2758 } else if (Name == "avx2") { 2759 setSSELevel(Features, AVX2, Enabled); 2760 } else if (Name == "avx512f") { 2761 setSSELevel(Features, AVX512F, Enabled); 2762 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2763 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2764 if (Enabled) 2765 setSSELevel(Features, AVX512F, Enabled); 2766 } else if (Name == "fma") { 2767 if (Enabled) 2768 setSSELevel(Features, AVX, Enabled); 2769 } else if (Name == "fma4") { 2770 setXOPLevel(Features, FMA4, Enabled); 2771 } else if (Name == "xop") { 2772 setXOPLevel(Features, XOP, Enabled); 2773 } else if (Name == "sse4a") { 2774 setXOPLevel(Features, SSE4A, Enabled); 2775 } else if (Name == "f16c") { 2776 if (Enabled) 2777 setSSELevel(Features, AVX, Enabled); 2778 } else if (Name == "sha") { 2779 if (Enabled) 2780 setSSELevel(Features, SSE2, Enabled); 2781 } 2782 } 2783 2784 /// handleTargetFeatures - Perform initialization based on the user 2785 /// configured set of features. 2786 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2787 DiagnosticsEngine &Diags) { 2788 // Remember the maximum enabled sselevel. 2789 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2790 // Ignore disabled features. 2791 if (Features[i][0] == '-') 2792 continue; 2793 2794 StringRef Feature = StringRef(Features[i]).substr(1); 2795 2796 if (Feature == "aes") { 2797 HasAES = true; 2798 continue; 2799 } 2800 2801 if (Feature == "pclmul") { 2802 HasPCLMUL = true; 2803 continue; 2804 } 2805 2806 if (Feature == "lzcnt") { 2807 HasLZCNT = true; 2808 continue; 2809 } 2810 2811 if (Feature == "rdrnd") { 2812 HasRDRND = true; 2813 continue; 2814 } 2815 2816 if (Feature == "fsgsbase") { 2817 HasFSGSBASE = true; 2818 continue; 2819 } 2820 2821 if (Feature == "bmi") { 2822 HasBMI = true; 2823 continue; 2824 } 2825 2826 if (Feature == "bmi2") { 2827 HasBMI2 = true; 2828 continue; 2829 } 2830 2831 if (Feature == "popcnt") { 2832 HasPOPCNT = true; 2833 continue; 2834 } 2835 2836 if (Feature == "rtm") { 2837 HasRTM = true; 2838 continue; 2839 } 2840 2841 if (Feature == "prfchw") { 2842 HasPRFCHW = true; 2843 continue; 2844 } 2845 2846 if (Feature == "rdseed") { 2847 HasRDSEED = true; 2848 continue; 2849 } 2850 2851 if (Feature == "adx") { 2852 HasADX = true; 2853 continue; 2854 } 2855 2856 if (Feature == "tbm") { 2857 HasTBM = true; 2858 continue; 2859 } 2860 2861 if (Feature == "fma") { 2862 HasFMA = true; 2863 continue; 2864 } 2865 2866 if (Feature == "f16c") { 2867 HasF16C = true; 2868 continue; 2869 } 2870 2871 if (Feature == "avx512cd") { 2872 HasAVX512CD = true; 2873 continue; 2874 } 2875 2876 if (Feature == "avx512er") { 2877 HasAVX512ER = true; 2878 continue; 2879 } 2880 2881 if (Feature == "avx512pf") { 2882 HasAVX512PF = true; 2883 continue; 2884 } 2885 2886 if (Feature == "avx512dq") { 2887 HasAVX512DQ = true; 2888 continue; 2889 } 2890 2891 if (Feature == "avx512bw") { 2892 HasAVX512BW = true; 2893 continue; 2894 } 2895 2896 if (Feature == "avx512vl") { 2897 HasAVX512VL = true; 2898 continue; 2899 } 2900 2901 if (Feature == "sha") { 2902 HasSHA = true; 2903 continue; 2904 } 2905 2906 if (Feature == "cx16") { 2907 HasCX16 = true; 2908 continue; 2909 } 2910 2911 assert(Features[i][0] == '+' && "Invalid target feature!"); 2912 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2913 .Case("avx512f", AVX512F) 2914 .Case("avx2", AVX2) 2915 .Case("avx", AVX) 2916 .Case("sse4.2", SSE42) 2917 .Case("sse4.1", SSE41) 2918 .Case("ssse3", SSSE3) 2919 .Case("sse3", SSE3) 2920 .Case("sse2", SSE2) 2921 .Case("sse", SSE1) 2922 .Default(NoSSE); 2923 SSELevel = std::max(SSELevel, Level); 2924 2925 MMX3DNowEnum ThreeDNowLevel = 2926 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2927 .Case("3dnowa", AMD3DNowAthlon) 2928 .Case("3dnow", AMD3DNow) 2929 .Case("mmx", MMX) 2930 .Default(NoMMX3DNow); 2931 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2932 2933 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2934 .Case("xop", XOP) 2935 .Case("fma4", FMA4) 2936 .Case("sse4a", SSE4A) 2937 .Default(NoXOP); 2938 XOPLevel = std::max(XOPLevel, XLevel); 2939 } 2940 2941 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2942 // Can't do this earlier because we need to be able to explicitly enable 2943 // popcnt and still disable sse4.2. 2944 if (!HasPOPCNT && SSELevel >= SSE42 && 2945 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2946 HasPOPCNT = true; 2947 Features.push_back("+popcnt"); 2948 } 2949 2950 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2951 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2952 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2953 HasPRFCHW = true; 2954 Features.push_back("+prfchw"); 2955 } 2956 2957 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2958 // matches the selected sse level. 2959 if (FPMath == FP_SSE && SSELevel < SSE1) { 2960 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2961 return false; 2962 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2963 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2964 return false; 2965 } 2966 2967 // Don't tell the backend if we're turning off mmx; it will end up disabling 2968 // SSE, which we don't want. 2969 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2970 // then enable MMX. 2971 std::vector<std::string>::iterator it; 2972 it = std::find(Features.begin(), Features.end(), "-mmx"); 2973 if (it != Features.end()) 2974 Features.erase(it); 2975 else if (SSELevel > NoSSE) 2976 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2977 return true; 2978 } 2979 2980 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2981 /// definitions for this particular subtarget. 2982 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2983 MacroBuilder &Builder) const { 2984 // Target identification. 2985 if (getTriple().getArch() == llvm::Triple::x86_64) { 2986 Builder.defineMacro("__amd64__"); 2987 Builder.defineMacro("__amd64"); 2988 Builder.defineMacro("__x86_64"); 2989 Builder.defineMacro("__x86_64__"); 2990 if (getTriple().getArchName() == "x86_64h") { 2991 Builder.defineMacro("__x86_64h"); 2992 Builder.defineMacro("__x86_64h__"); 2993 } 2994 } else { 2995 DefineStd(Builder, "i386", Opts); 2996 } 2997 2998 // Subtarget options. 2999 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3000 // truly should be based on -mtune options. 3001 switch (CPU) { 3002 case CK_Generic: 3003 break; 3004 case CK_i386: 3005 // The rest are coming from the i386 define above. 3006 Builder.defineMacro("__tune_i386__"); 3007 break; 3008 case CK_i486: 3009 case CK_WinChipC6: 3010 case CK_WinChip2: 3011 case CK_C3: 3012 defineCPUMacros(Builder, "i486"); 3013 break; 3014 case CK_PentiumMMX: 3015 Builder.defineMacro("__pentium_mmx__"); 3016 Builder.defineMacro("__tune_pentium_mmx__"); 3017 // Fallthrough 3018 case CK_i586: 3019 case CK_Pentium: 3020 defineCPUMacros(Builder, "i586"); 3021 defineCPUMacros(Builder, "pentium"); 3022 break; 3023 case CK_Pentium3: 3024 case CK_Pentium3M: 3025 case CK_PentiumM: 3026 Builder.defineMacro("__tune_pentium3__"); 3027 // Fallthrough 3028 case CK_Pentium2: 3029 case CK_C3_2: 3030 Builder.defineMacro("__tune_pentium2__"); 3031 // Fallthrough 3032 case CK_PentiumPro: 3033 Builder.defineMacro("__tune_i686__"); 3034 Builder.defineMacro("__tune_pentiumpro__"); 3035 // Fallthrough 3036 case CK_i686: 3037 Builder.defineMacro("__i686"); 3038 Builder.defineMacro("__i686__"); 3039 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3040 Builder.defineMacro("__pentiumpro"); 3041 Builder.defineMacro("__pentiumpro__"); 3042 break; 3043 case CK_Pentium4: 3044 case CK_Pentium4M: 3045 defineCPUMacros(Builder, "pentium4"); 3046 break; 3047 case CK_Yonah: 3048 case CK_Prescott: 3049 case CK_Nocona: 3050 defineCPUMacros(Builder, "nocona"); 3051 break; 3052 case CK_Core2: 3053 case CK_Penryn: 3054 defineCPUMacros(Builder, "core2"); 3055 break; 3056 case CK_Bonnell: 3057 defineCPUMacros(Builder, "atom"); 3058 break; 3059 case CK_Silvermont: 3060 defineCPUMacros(Builder, "slm"); 3061 break; 3062 case CK_Nehalem: 3063 case CK_Westmere: 3064 case CK_SandyBridge: 3065 case CK_IvyBridge: 3066 case CK_Haswell: 3067 case CK_Broadwell: 3068 // FIXME: Historically, we defined this legacy name, it would be nice to 3069 // remove it at some point. We've never exposed fine-grained names for 3070 // recent primary x86 CPUs, and we should keep it that way. 3071 defineCPUMacros(Builder, "corei7"); 3072 break; 3073 case CK_Skylake: 3074 // FIXME: Historically, we defined this legacy name, it would be nice to 3075 // remove it at some point. This is the only fine-grained CPU macro in the 3076 // main intel CPU line, and it would be better to not have these and force 3077 // people to use ISA macros. 3078 defineCPUMacros(Builder, "skx"); 3079 break; 3080 case CK_KNL: 3081 defineCPUMacros(Builder, "knl"); 3082 break; 3083 case CK_K6_2: 3084 Builder.defineMacro("__k6_2__"); 3085 Builder.defineMacro("__tune_k6_2__"); 3086 // Fallthrough 3087 case CK_K6_3: 3088 if (CPU != CK_K6_2) { // In case of fallthrough 3089 // FIXME: GCC may be enabling these in cases where some other k6 3090 // architecture is specified but -m3dnow is explicitly provided. The 3091 // exact semantics need to be determined and emulated here. 3092 Builder.defineMacro("__k6_3__"); 3093 Builder.defineMacro("__tune_k6_3__"); 3094 } 3095 // Fallthrough 3096 case CK_K6: 3097 defineCPUMacros(Builder, "k6"); 3098 break; 3099 case CK_Athlon: 3100 case CK_AthlonThunderbird: 3101 case CK_Athlon4: 3102 case CK_AthlonXP: 3103 case CK_AthlonMP: 3104 defineCPUMacros(Builder, "athlon"); 3105 if (SSELevel != NoSSE) { 3106 Builder.defineMacro("__athlon_sse__"); 3107 Builder.defineMacro("__tune_athlon_sse__"); 3108 } 3109 break; 3110 case CK_K8: 3111 case CK_K8SSE3: 3112 case CK_x86_64: 3113 case CK_Opteron: 3114 case CK_OpteronSSE3: 3115 case CK_Athlon64: 3116 case CK_Athlon64SSE3: 3117 case CK_AthlonFX: 3118 defineCPUMacros(Builder, "k8"); 3119 break; 3120 case CK_AMDFAM10: 3121 defineCPUMacros(Builder, "amdfam10"); 3122 break; 3123 case CK_BTVER1: 3124 defineCPUMacros(Builder, "btver1"); 3125 break; 3126 case CK_BTVER2: 3127 defineCPUMacros(Builder, "btver2"); 3128 break; 3129 case CK_BDVER1: 3130 defineCPUMacros(Builder, "bdver1"); 3131 break; 3132 case CK_BDVER2: 3133 defineCPUMacros(Builder, "bdver2"); 3134 break; 3135 case CK_BDVER3: 3136 defineCPUMacros(Builder, "bdver3"); 3137 break; 3138 case CK_BDVER4: 3139 defineCPUMacros(Builder, "bdver4"); 3140 break; 3141 case CK_Geode: 3142 defineCPUMacros(Builder, "geode"); 3143 break; 3144 } 3145 3146 // Target properties. 3147 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3148 3149 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3150 // functions in glibc header files that use FP Stack inline asm which the 3151 // backend can't deal with (PR879). 3152 Builder.defineMacro("__NO_MATH_INLINES"); 3153 3154 if (HasAES) 3155 Builder.defineMacro("__AES__"); 3156 3157 if (HasPCLMUL) 3158 Builder.defineMacro("__PCLMUL__"); 3159 3160 if (HasLZCNT) 3161 Builder.defineMacro("__LZCNT__"); 3162 3163 if (HasRDRND) 3164 Builder.defineMacro("__RDRND__"); 3165 3166 if (HasFSGSBASE) 3167 Builder.defineMacro("__FSGSBASE__"); 3168 3169 if (HasBMI) 3170 Builder.defineMacro("__BMI__"); 3171 3172 if (HasBMI2) 3173 Builder.defineMacro("__BMI2__"); 3174 3175 if (HasPOPCNT) 3176 Builder.defineMacro("__POPCNT__"); 3177 3178 if (HasRTM) 3179 Builder.defineMacro("__RTM__"); 3180 3181 if (HasPRFCHW) 3182 Builder.defineMacro("__PRFCHW__"); 3183 3184 if (HasRDSEED) 3185 Builder.defineMacro("__RDSEED__"); 3186 3187 if (HasADX) 3188 Builder.defineMacro("__ADX__"); 3189 3190 if (HasTBM) 3191 Builder.defineMacro("__TBM__"); 3192 3193 switch (XOPLevel) { 3194 case XOP: 3195 Builder.defineMacro("__XOP__"); 3196 case FMA4: 3197 Builder.defineMacro("__FMA4__"); 3198 case SSE4A: 3199 Builder.defineMacro("__SSE4A__"); 3200 case NoXOP: 3201 break; 3202 } 3203 3204 if (HasFMA) 3205 Builder.defineMacro("__FMA__"); 3206 3207 if (HasF16C) 3208 Builder.defineMacro("__F16C__"); 3209 3210 if (HasAVX512CD) 3211 Builder.defineMacro("__AVX512CD__"); 3212 if (HasAVX512ER) 3213 Builder.defineMacro("__AVX512ER__"); 3214 if (HasAVX512PF) 3215 Builder.defineMacro("__AVX512PF__"); 3216 if (HasAVX512DQ) 3217 Builder.defineMacro("__AVX512DQ__"); 3218 if (HasAVX512BW) 3219 Builder.defineMacro("__AVX512BW__"); 3220 if (HasAVX512VL) 3221 Builder.defineMacro("__AVX512VL__"); 3222 3223 if (HasSHA) 3224 Builder.defineMacro("__SHA__"); 3225 3226 if (HasCX16) 3227 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3228 3229 // Each case falls through to the previous one here. 3230 switch (SSELevel) { 3231 case AVX512F: 3232 Builder.defineMacro("__AVX512F__"); 3233 case AVX2: 3234 Builder.defineMacro("__AVX2__"); 3235 case AVX: 3236 Builder.defineMacro("__AVX__"); 3237 case SSE42: 3238 Builder.defineMacro("__SSE4_2__"); 3239 case SSE41: 3240 Builder.defineMacro("__SSE4_1__"); 3241 case SSSE3: 3242 Builder.defineMacro("__SSSE3__"); 3243 case SSE3: 3244 Builder.defineMacro("__SSE3__"); 3245 case SSE2: 3246 Builder.defineMacro("__SSE2__"); 3247 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3248 case SSE1: 3249 Builder.defineMacro("__SSE__"); 3250 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3251 case NoSSE: 3252 break; 3253 } 3254 3255 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3256 switch (SSELevel) { 3257 case AVX512F: 3258 case AVX2: 3259 case AVX: 3260 case SSE42: 3261 case SSE41: 3262 case SSSE3: 3263 case SSE3: 3264 case SSE2: 3265 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3266 break; 3267 case SSE1: 3268 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3269 break; 3270 default: 3271 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3272 } 3273 } 3274 3275 // Each case falls through to the previous one here. 3276 switch (MMX3DNowLevel) { 3277 case AMD3DNowAthlon: 3278 Builder.defineMacro("__3dNOW_A__"); 3279 case AMD3DNow: 3280 Builder.defineMacro("__3dNOW__"); 3281 case MMX: 3282 Builder.defineMacro("__MMX__"); 3283 case NoMMX3DNow: 3284 break; 3285 } 3286 3287 if (CPU >= CK_i486) { 3288 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3289 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3290 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3291 } 3292 if (CPU >= CK_i586) 3293 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3294 } 3295 3296 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3297 return llvm::StringSwitch<bool>(Feature) 3298 .Case("aes", HasAES) 3299 .Case("avx", SSELevel >= AVX) 3300 .Case("avx2", SSELevel >= AVX2) 3301 .Case("avx512f", SSELevel >= AVX512F) 3302 .Case("avx512cd", HasAVX512CD) 3303 .Case("avx512er", HasAVX512ER) 3304 .Case("avx512pf", HasAVX512PF) 3305 .Case("avx512dq", HasAVX512DQ) 3306 .Case("avx512bw", HasAVX512BW) 3307 .Case("avx512vl", HasAVX512VL) 3308 .Case("bmi", HasBMI) 3309 .Case("bmi2", HasBMI2) 3310 .Case("cx16", HasCX16) 3311 .Case("f16c", HasF16C) 3312 .Case("fma", HasFMA) 3313 .Case("fma4", XOPLevel >= FMA4) 3314 .Case("fsgsbase", HasFSGSBASE) 3315 .Case("lzcnt", HasLZCNT) 3316 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3317 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3318 .Case("mmx", MMX3DNowLevel >= MMX) 3319 .Case("pclmul", HasPCLMUL) 3320 .Case("popcnt", HasPOPCNT) 3321 .Case("prfchw", HasPRFCHW) 3322 .Case("rdrnd", HasRDRND) 3323 .Case("rdseed", HasRDSEED) 3324 .Case("rtm", HasRTM) 3325 .Case("sha", HasSHA) 3326 .Case("sse", SSELevel >= SSE1) 3327 .Case("sse2", SSELevel >= SSE2) 3328 .Case("sse3", SSELevel >= SSE3) 3329 .Case("ssse3", SSELevel >= SSSE3) 3330 .Case("sse4.1", SSELevel >= SSE41) 3331 .Case("sse4.2", SSELevel >= SSE42) 3332 .Case("sse4a", XOPLevel >= SSE4A) 3333 .Case("tbm", HasTBM) 3334 .Case("x86", true) 3335 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3336 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3337 .Case("xop", XOPLevel >= XOP) 3338 .Default(false); 3339 } 3340 3341 bool 3342 X86TargetInfo::validateAsmConstraint(const char *&Name, 3343 TargetInfo::ConstraintInfo &Info) const { 3344 switch (*Name) { 3345 default: return false; 3346 case 'I': 3347 Info.setRequiresImmediate(0, 31); 3348 return true; 3349 case 'J': 3350 Info.setRequiresImmediate(0, 63); 3351 return true; 3352 case 'K': 3353 Info.setRequiresImmediate(-128, 127); 3354 return true; 3355 case 'L': 3356 // FIXME: properly analyze this constraint: 3357 // must be one of 0xff, 0xffff, or 0xffffffff 3358 return true; 3359 case 'M': 3360 Info.setRequiresImmediate(0, 3); 3361 return true; 3362 case 'N': 3363 Info.setRequiresImmediate(0, 255); 3364 return true; 3365 case 'O': 3366 Info.setRequiresImmediate(0, 127); 3367 return true; 3368 case 'Y': // first letter of a pair: 3369 switch (*(Name+1)) { 3370 default: return false; 3371 case '0': // First SSE register. 3372 case 't': // Any SSE register, when SSE2 is enabled. 3373 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3374 case 'm': // any MMX register, when inter-unit moves enabled. 3375 break; // falls through to setAllowsRegister. 3376 } 3377 case 'f': // any x87 floating point stack register. 3378 // Constraint 'f' cannot be used for output operands. 3379 if (Info.ConstraintStr[0] == '=') 3380 return false; 3381 3382 Info.setAllowsRegister(); 3383 return true; 3384 case 'a': // eax. 3385 case 'b': // ebx. 3386 case 'c': // ecx. 3387 case 'd': // edx. 3388 case 'S': // esi. 3389 case 'D': // edi. 3390 case 'A': // edx:eax. 3391 case 't': // top of floating point stack. 3392 case 'u': // second from top of floating point stack. 3393 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3394 case 'y': // Any MMX register. 3395 case 'x': // Any SSE register. 3396 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3397 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3398 case 'l': // "Index" registers: any general register that can be used as an 3399 // index in a base+index memory access. 3400 Info.setAllowsRegister(); 3401 return true; 3402 case 'C': // SSE floating point constant. 3403 case 'G': // x87 floating point constant. 3404 case 'e': // 32-bit signed integer constant for use with zero-extending 3405 // x86_64 instructions. 3406 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3407 // x86_64 instructions. 3408 return true; 3409 } 3410 } 3411 3412 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3413 unsigned Size) const { 3414 // Strip off constraint modifiers. 3415 while (Constraint[0] == '=' || 3416 Constraint[0] == '+' || 3417 Constraint[0] == '&') 3418 Constraint = Constraint.substr(1); 3419 3420 return validateOperandSize(Constraint, Size); 3421 } 3422 3423 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3424 unsigned Size) const { 3425 return validateOperandSize(Constraint, Size); 3426 } 3427 3428 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3429 unsigned Size) const { 3430 switch (Constraint[0]) { 3431 default: break; 3432 case 'y': 3433 return Size <= 64; 3434 case 'f': 3435 case 't': 3436 case 'u': 3437 return Size <= 128; 3438 case 'x': 3439 // 256-bit ymm registers can be used if target supports AVX. 3440 return Size <= (SSELevel >= AVX ? 256U : 128U); 3441 } 3442 3443 return true; 3444 } 3445 3446 std::string 3447 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3448 switch (*Constraint) { 3449 case 'a': return std::string("{ax}"); 3450 case 'b': return std::string("{bx}"); 3451 case 'c': return std::string("{cx}"); 3452 case 'd': return std::string("{dx}"); 3453 case 'S': return std::string("{si}"); 3454 case 'D': return std::string("{di}"); 3455 case 'p': // address 3456 return std::string("im"); 3457 case 't': // top of floating point stack. 3458 return std::string("{st}"); 3459 case 'u': // second from top of floating point stack. 3460 return std::string("{st(1)}"); // second from top of floating point stack. 3461 default: 3462 return std::string(1, *Constraint); 3463 } 3464 } 3465 3466 // X86-32 generic target 3467 class X86_32TargetInfo : public X86TargetInfo { 3468 public: 3469 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3470 DoubleAlign = LongLongAlign = 32; 3471 LongDoubleWidth = 96; 3472 LongDoubleAlign = 32; 3473 SuitableAlign = 128; 3474 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3475 SizeType = UnsignedInt; 3476 PtrDiffType = SignedInt; 3477 IntPtrType = SignedInt; 3478 RegParmMax = 3; 3479 3480 // Use fpret for all types. 3481 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3482 (1 << TargetInfo::Double) | 3483 (1 << TargetInfo::LongDouble)); 3484 3485 // x86-32 has atomics up to 8 bytes 3486 // FIXME: Check that we actually have cmpxchg8b before setting 3487 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3488 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3489 } 3490 BuiltinVaListKind getBuiltinVaListKind() const override { 3491 return TargetInfo::CharPtrBuiltinVaList; 3492 } 3493 3494 int getEHDataRegisterNumber(unsigned RegNo) const override { 3495 if (RegNo == 0) return 0; 3496 if (RegNo == 1) return 2; 3497 return -1; 3498 } 3499 bool validateOperandSize(StringRef Constraint, 3500 unsigned Size) const override { 3501 switch (Constraint[0]) { 3502 default: break; 3503 case 'R': 3504 case 'q': 3505 case 'Q': 3506 case 'a': 3507 case 'b': 3508 case 'c': 3509 case 'd': 3510 case 'S': 3511 case 'D': 3512 return Size <= 32; 3513 case 'A': 3514 return Size <= 64; 3515 } 3516 3517 return X86TargetInfo::validateOperandSize(Constraint, Size); 3518 } 3519 }; 3520 3521 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3522 public: 3523 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3524 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3525 3526 unsigned getFloatEvalMethod() const override { 3527 unsigned Major, Minor, Micro; 3528 getTriple().getOSVersion(Major, Minor, Micro); 3529 // New NetBSD uses the default rounding mode. 3530 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3531 return X86_32TargetInfo::getFloatEvalMethod(); 3532 // NetBSD before 6.99.26 defaults to "double" rounding. 3533 return 1; 3534 } 3535 }; 3536 3537 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3538 public: 3539 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3540 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3541 SizeType = UnsignedLong; 3542 IntPtrType = SignedLong; 3543 PtrDiffType = SignedLong; 3544 } 3545 }; 3546 3547 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3548 public: 3549 BitrigI386TargetInfo(const llvm::Triple &Triple) 3550 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3551 SizeType = UnsignedLong; 3552 IntPtrType = SignedLong; 3553 PtrDiffType = SignedLong; 3554 } 3555 }; 3556 3557 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3558 public: 3559 DarwinI386TargetInfo(const llvm::Triple &Triple) 3560 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3561 LongDoubleWidth = 128; 3562 LongDoubleAlign = 128; 3563 SuitableAlign = 128; 3564 MaxVectorAlign = 256; 3565 SizeType = UnsignedLong; 3566 IntPtrType = SignedLong; 3567 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3568 HasAlignMac68kSupport = true; 3569 } 3570 3571 }; 3572 3573 // x86-32 Windows target 3574 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3575 public: 3576 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3577 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3578 WCharType = UnsignedShort; 3579 DoubleAlign = LongLongAlign = 64; 3580 bool IsWinCOFF = 3581 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3582 DescriptionString = IsWinCOFF 3583 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3584 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3585 } 3586 void getTargetDefines(const LangOptions &Opts, 3587 MacroBuilder &Builder) const override { 3588 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3589 } 3590 }; 3591 3592 // x86-32 Windows Visual Studio target 3593 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3594 public: 3595 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3596 : WindowsX86_32TargetInfo(Triple) { 3597 LongDoubleWidth = LongDoubleAlign = 64; 3598 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3599 } 3600 void getTargetDefines(const LangOptions &Opts, 3601 MacroBuilder &Builder) const override { 3602 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3603 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3604 // The value of the following reflects processor type. 3605 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3606 // We lost the original triple, so we use the default. 3607 Builder.defineMacro("_M_IX86", "600"); 3608 } 3609 }; 3610 } // end anonymous namespace 3611 3612 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3613 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang supports 3614 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3615 // macro anyway for pre-processor compatibility. 3616 if (Opts.MicrosoftExt) 3617 Builder.defineMacro("__declspec", "__declspec"); 3618 else 3619 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3620 3621 if (!Opts.MicrosoftExt) { 3622 // Provide macros for all the calling convention keywords. Provide both 3623 // single and double underscore prefixed variants. These are available on 3624 // x64 as well as x86, even though they have no effect. 3625 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3626 for (const char *CC : CCs) { 3627 std::string GCCSpelling = "__attribute__((__"; 3628 GCCSpelling += CC; 3629 GCCSpelling += "__))"; 3630 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3631 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3632 } 3633 } 3634 } 3635 3636 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3637 Builder.defineMacro("__MSVCRT__"); 3638 Builder.defineMacro("__MINGW32__"); 3639 addCygMingDefines(Opts, Builder); 3640 } 3641 3642 namespace { 3643 // x86-32 MinGW target 3644 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3645 public: 3646 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3647 : WindowsX86_32TargetInfo(Triple) {} 3648 void getTargetDefines(const LangOptions &Opts, 3649 MacroBuilder &Builder) const override { 3650 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3651 DefineStd(Builder, "WIN32", Opts); 3652 DefineStd(Builder, "WINNT", Opts); 3653 Builder.defineMacro("_X86_"); 3654 addMinGWDefines(Opts, Builder); 3655 } 3656 }; 3657 3658 // x86-32 Cygwin target 3659 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3660 public: 3661 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3662 : X86_32TargetInfo(Triple) { 3663 TLSSupported = false; 3664 WCharType = UnsignedShort; 3665 DoubleAlign = LongLongAlign = 64; 3666 DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3667 } 3668 void getTargetDefines(const LangOptions &Opts, 3669 MacroBuilder &Builder) const override { 3670 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3671 Builder.defineMacro("_X86_"); 3672 Builder.defineMacro("__CYGWIN__"); 3673 Builder.defineMacro("__CYGWIN32__"); 3674 addCygMingDefines(Opts, Builder); 3675 DefineStd(Builder, "unix", Opts); 3676 if (Opts.CPlusPlus) 3677 Builder.defineMacro("_GNU_SOURCE"); 3678 } 3679 }; 3680 3681 // x86-32 Haiku target 3682 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3683 public: 3684 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3685 SizeType = UnsignedLong; 3686 IntPtrType = SignedLong; 3687 PtrDiffType = SignedLong; 3688 ProcessIDType = SignedLong; 3689 this->UserLabelPrefix = ""; 3690 this->TLSSupported = false; 3691 } 3692 void getTargetDefines(const LangOptions &Opts, 3693 MacroBuilder &Builder) const override { 3694 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3695 Builder.defineMacro("__INTEL__"); 3696 Builder.defineMacro("__HAIKU__"); 3697 } 3698 }; 3699 3700 // RTEMS Target 3701 template<typename Target> 3702 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3703 protected: 3704 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3705 MacroBuilder &Builder) const override { 3706 // RTEMS defines; list based off of gcc output 3707 3708 Builder.defineMacro("__rtems__"); 3709 Builder.defineMacro("__ELF__"); 3710 } 3711 3712 public: 3713 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3714 this->UserLabelPrefix = ""; 3715 3716 switch (Triple.getArch()) { 3717 default: 3718 case llvm::Triple::x86: 3719 // this->MCountName = ".mcount"; 3720 break; 3721 case llvm::Triple::mips: 3722 case llvm::Triple::mipsel: 3723 case llvm::Triple::ppc: 3724 case llvm::Triple::ppc64: 3725 case llvm::Triple::ppc64le: 3726 // this->MCountName = "_mcount"; 3727 break; 3728 case llvm::Triple::arm: 3729 // this->MCountName = "__mcount"; 3730 break; 3731 } 3732 } 3733 }; 3734 3735 // x86-32 RTEMS target 3736 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3737 public: 3738 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3739 SizeType = UnsignedLong; 3740 IntPtrType = SignedLong; 3741 PtrDiffType = SignedLong; 3742 this->UserLabelPrefix = ""; 3743 } 3744 void getTargetDefines(const LangOptions &Opts, 3745 MacroBuilder &Builder) const override { 3746 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3747 Builder.defineMacro("__INTEL__"); 3748 Builder.defineMacro("__rtems__"); 3749 } 3750 }; 3751 3752 // x86-64 generic target 3753 class X86_64TargetInfo : public X86TargetInfo { 3754 public: 3755 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3756 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3757 bool IsWinCOFF = 3758 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3759 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3760 LongDoubleWidth = 128; 3761 LongDoubleAlign = 128; 3762 LargeArrayMinWidth = 128; 3763 LargeArrayAlign = 128; 3764 SuitableAlign = 128; 3765 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3766 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3767 IntPtrType = IsX32 ? SignedInt : SignedLong; 3768 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3769 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3770 RegParmMax = 6; 3771 3772 // Pointers are 32-bit in x32. 3773 DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3774 : IsWinCOFF 3775 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3776 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3777 3778 // Use fpret only for long double. 3779 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3780 3781 // Use fp2ret for _Complex long double. 3782 ComplexLongDoubleUsesFP2Ret = true; 3783 3784 // x86-64 has atomics up to 16 bytes. 3785 MaxAtomicPromoteWidth = 128; 3786 MaxAtomicInlineWidth = 128; 3787 } 3788 BuiltinVaListKind getBuiltinVaListKind() const override { 3789 return TargetInfo::X86_64ABIBuiltinVaList; 3790 } 3791 3792 int getEHDataRegisterNumber(unsigned RegNo) const override { 3793 if (RegNo == 0) return 0; 3794 if (RegNo == 1) return 1; 3795 return -1; 3796 } 3797 3798 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3799 return (CC == CC_C || 3800 CC == CC_X86VectorCall || 3801 CC == CC_IntelOclBicc || 3802 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3803 } 3804 3805 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3806 return CC_C; 3807 } 3808 3809 // for x32 we need it here explicitly 3810 bool hasInt128Type() const override { return true; } 3811 }; 3812 3813 // x86-64 Windows target 3814 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3815 public: 3816 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3817 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3818 WCharType = UnsignedShort; 3819 LongWidth = LongAlign = 32; 3820 DoubleAlign = LongLongAlign = 64; 3821 IntMaxType = SignedLongLong; 3822 Int64Type = SignedLongLong; 3823 SizeType = UnsignedLongLong; 3824 PtrDiffType = SignedLongLong; 3825 IntPtrType = SignedLongLong; 3826 this->UserLabelPrefix = ""; 3827 } 3828 3829 void getTargetDefines(const LangOptions &Opts, 3830 MacroBuilder &Builder) const override { 3831 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3832 Builder.defineMacro("_WIN64"); 3833 } 3834 3835 BuiltinVaListKind getBuiltinVaListKind() const override { 3836 return TargetInfo::CharPtrBuiltinVaList; 3837 } 3838 3839 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3840 switch (CC) { 3841 case CC_X86StdCall: 3842 case CC_X86ThisCall: 3843 case CC_X86FastCall: 3844 return CCCR_Ignore; 3845 case CC_C: 3846 case CC_X86VectorCall: 3847 case CC_IntelOclBicc: 3848 case CC_X86_64SysV: 3849 return CCCR_OK; 3850 default: 3851 return CCCR_Warning; 3852 } 3853 } 3854 }; 3855 3856 // x86-64 Windows Visual Studio target 3857 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3858 public: 3859 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3860 : WindowsX86_64TargetInfo(Triple) { 3861 LongDoubleWidth = LongDoubleAlign = 64; 3862 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3863 } 3864 void getTargetDefines(const LangOptions &Opts, 3865 MacroBuilder &Builder) const override { 3866 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3867 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3868 Builder.defineMacro("_M_X64"); 3869 Builder.defineMacro("_M_AMD64"); 3870 } 3871 }; 3872 3873 // x86-64 MinGW target 3874 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3875 public: 3876 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3877 : WindowsX86_64TargetInfo(Triple) {} 3878 void getTargetDefines(const LangOptions &Opts, 3879 MacroBuilder &Builder) const override { 3880 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3881 DefineStd(Builder, "WIN64", Opts); 3882 Builder.defineMacro("__MINGW64__"); 3883 addMinGWDefines(Opts, Builder); 3884 3885 // GCC defines this macro when it is using __gxx_personality_seh0. 3886 if (!Opts.SjLjExceptions) 3887 Builder.defineMacro("__SEH__"); 3888 } 3889 }; 3890 3891 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3892 public: 3893 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3894 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3895 Int64Type = SignedLongLong; 3896 MaxVectorAlign = 256; 3897 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3898 llvm::Triple T = llvm::Triple(Triple); 3899 if (T.isiOS()) 3900 UseSignedCharForObjCBool = false; 3901 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3902 } 3903 }; 3904 3905 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3906 public: 3907 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3908 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3909 IntMaxType = SignedLongLong; 3910 Int64Type = SignedLongLong; 3911 } 3912 }; 3913 3914 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3915 public: 3916 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3917 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3918 IntMaxType = SignedLongLong; 3919 Int64Type = SignedLongLong; 3920 } 3921 }; 3922 3923 class ARMTargetInfo : public TargetInfo { 3924 // Possible FPU choices. 3925 enum FPUMode { 3926 VFP2FPU = (1 << 0), 3927 VFP3FPU = (1 << 1), 3928 VFP4FPU = (1 << 2), 3929 NeonFPU = (1 << 3), 3930 FPARMV8 = (1 << 4) 3931 }; 3932 3933 // Possible HWDiv features. 3934 enum HWDivMode { 3935 HWDivThumb = (1 << 0), 3936 HWDivARM = (1 << 1) 3937 }; 3938 3939 static bool FPUModeIsVFP(FPUMode Mode) { 3940 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3941 } 3942 3943 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3944 static const char * const GCCRegNames[]; 3945 3946 std::string ABI, CPU; 3947 3948 enum { 3949 FP_Default, 3950 FP_VFP, 3951 FP_Neon 3952 } FPMath; 3953 3954 unsigned FPU : 5; 3955 3956 unsigned IsAAPCS : 1; 3957 unsigned IsThumb : 1; 3958 unsigned HWDiv : 2; 3959 3960 // Initialized via features. 3961 unsigned SoftFloat : 1; 3962 unsigned SoftFloatABI : 1; 3963 3964 unsigned CRC : 1; 3965 unsigned Crypto : 1; 3966 3967 // ACLE 6.5.1 Hardware floating point 3968 enum { 3969 HW_FP_HP = (1 << 1), /// half (16-bit) 3970 HW_FP_SP = (1 << 2), /// single (32-bit) 3971 HW_FP_DP = (1 << 3), /// double (64-bit) 3972 }; 3973 uint32_t HW_FP; 3974 3975 static const Builtin::Info BuiltinInfo[]; 3976 3977 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3978 StringRef ArchName = T.getArchName(); 3979 if (T.getArch() == llvm::Triple::arm || 3980 T.getArch() == llvm::Triple::armeb) { 3981 StringRef VersionStr; 3982 if (ArchName.startswith("armv")) 3983 VersionStr = ArchName.substr(4, 1); 3984 else if (ArchName.startswith("armebv")) 3985 VersionStr = ArchName.substr(6, 1); 3986 else 3987 return false; 3988 unsigned Version; 3989 if (VersionStr.getAsInteger(10, Version)) 3990 return false; 3991 return Version >= 6; 3992 } 3993 assert(T.getArch() == llvm::Triple::thumb || 3994 T.getArch() == llvm::Triple::thumbeb); 3995 StringRef VersionStr; 3996 if (ArchName.startswith("thumbv")) 3997 VersionStr = ArchName.substr(6, 1); 3998 else if (ArchName.startswith("thumbebv")) 3999 VersionStr = ArchName.substr(8, 1); 4000 else 4001 return false; 4002 unsigned Version; 4003 if (VersionStr.getAsInteger(10, Version)) 4004 return false; 4005 return Version >= 7; 4006 } 4007 4008 void setABIAAPCS() { 4009 IsAAPCS = true; 4010 4011 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4012 const llvm::Triple &T = getTriple(); 4013 4014 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4015 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4016 T.getOS() == llvm::Triple::Bitrig) 4017 SizeType = UnsignedLong; 4018 else 4019 SizeType = UnsignedInt; 4020 4021 switch (T.getOS()) { 4022 case llvm::Triple::NetBSD: 4023 WCharType = SignedInt; 4024 break; 4025 case llvm::Triple::Win32: 4026 WCharType = UnsignedShort; 4027 break; 4028 case llvm::Triple::Linux: 4029 default: 4030 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4031 WCharType = UnsignedInt; 4032 break; 4033 } 4034 4035 UseBitFieldTypeAlignment = true; 4036 4037 ZeroLengthBitfieldBoundary = 0; 4038 4039 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4040 // so set preferred for small types to 32. 4041 if (T.isOSBinFormatMachO()) { 4042 DescriptionString = 4043 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4044 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4045 } else if (T.isOSWindows()) { 4046 assert(!BigEndian && "Windows on ARM does not support big endian"); 4047 DescriptionString = "e" 4048 "-m:w" 4049 "-p:32:32" 4050 "-i64:64" 4051 "-v128:64:128" 4052 "-a:0:32" 4053 "-n32" 4054 "-S64"; 4055 } else if (T.isOSNaCl()) { 4056 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4057 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4058 } else { 4059 DescriptionString = 4060 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4061 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4062 } 4063 4064 // FIXME: Enumerated types are variable width in straight AAPCS. 4065 } 4066 4067 void setABIAPCS() { 4068 const llvm::Triple &T = getTriple(); 4069 4070 IsAAPCS = false; 4071 4072 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4073 4074 // size_t is unsigned int on FreeBSD. 4075 if (T.getOS() == llvm::Triple::FreeBSD) 4076 SizeType = UnsignedInt; 4077 else 4078 SizeType = UnsignedLong; 4079 4080 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4081 WCharType = SignedInt; 4082 4083 // Do not respect the alignment of bit-field types when laying out 4084 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4085 UseBitFieldTypeAlignment = false; 4086 4087 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4088 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4089 /// gcc. 4090 ZeroLengthBitfieldBoundary = 32; 4091 4092 if (T.isOSBinFormatMachO()) 4093 DescriptionString = 4094 BigEndian 4095 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4096 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4097 else 4098 DescriptionString = 4099 BigEndian 4100 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4101 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4102 4103 // FIXME: Override "preferred align" for double and long long. 4104 } 4105 4106 public: 4107 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4108 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 4109 IsAAPCS(true), HW_FP(0) { 4110 BigEndian = IsBigEndian; 4111 4112 switch (getTriple().getOS()) { 4113 case llvm::Triple::NetBSD: 4114 PtrDiffType = SignedLong; 4115 break; 4116 default: 4117 PtrDiffType = SignedInt; 4118 break; 4119 } 4120 4121 // {} in inline assembly are neon specifiers, not assembly variant 4122 // specifiers. 4123 NoAsmVariants = true; 4124 4125 // FIXME: Should we just treat this as a feature? 4126 IsThumb = getTriple().getArchName().startswith("thumb"); 4127 4128 // FIXME: This duplicates code from the driver that sets the -target-abi 4129 // option - this code is used if -target-abi isn't passed and should 4130 // be unified in some way. 4131 if (Triple.isOSBinFormatMachO()) { 4132 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4133 // the frontend matches that. 4134 if (Triple.getEnvironment() == llvm::Triple::EABI || 4135 Triple.getOS() == llvm::Triple::UnknownOS || 4136 StringRef(CPU).startswith("cortex-m")) { 4137 setABI("aapcs"); 4138 } else { 4139 setABI("apcs-gnu"); 4140 } 4141 } else if (Triple.isOSWindows()) { 4142 // FIXME: this is invalid for WindowsCE 4143 setABI("aapcs"); 4144 } else { 4145 // Select the default based on the platform. 4146 switch (Triple.getEnvironment()) { 4147 case llvm::Triple::Android: 4148 case llvm::Triple::GNUEABI: 4149 case llvm::Triple::GNUEABIHF: 4150 setABI("aapcs-linux"); 4151 break; 4152 case llvm::Triple::EABIHF: 4153 case llvm::Triple::EABI: 4154 setABI("aapcs"); 4155 break; 4156 case llvm::Triple::GNU: 4157 setABI("apcs-gnu"); 4158 break; 4159 default: 4160 if (Triple.getOS() == llvm::Triple::NetBSD) 4161 setABI("apcs-gnu"); 4162 else 4163 setABI("aapcs"); 4164 break; 4165 } 4166 } 4167 4168 // ARM targets default to using the ARM C++ ABI. 4169 TheCXXABI.set(TargetCXXABI::GenericARM); 4170 4171 // ARM has atomics up to 8 bytes 4172 MaxAtomicPromoteWidth = 64; 4173 if (shouldUseInlineAtomic(getTriple())) 4174 MaxAtomicInlineWidth = 64; 4175 4176 // Do force alignment of members that follow zero length bitfields. If 4177 // the alignment of the zero-length bitfield is greater than the member 4178 // that follows it, `bar', `bar' will be aligned as the type of the 4179 // zero length bitfield. 4180 UseZeroLengthBitfieldAlignment = true; 4181 } 4182 StringRef getABI() const override { return ABI; } 4183 bool setABI(const std::string &Name) override { 4184 ABI = Name; 4185 4186 // The defaults (above) are for AAPCS, check if we need to change them. 4187 // 4188 // FIXME: We need support for -meabi... we could just mangle it into the 4189 // name. 4190 if (Name == "apcs-gnu") { 4191 setABIAPCS(); 4192 return true; 4193 } 4194 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4195 setABIAAPCS(); 4196 return true; 4197 } 4198 return false; 4199 } 4200 4201 // FIXME: This should be based on Arch attributes, not CPU names. 4202 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4203 StringRef ArchName = getTriple().getArchName(); 4204 unsigned ArchKind = llvm::ARMTargetParser::parseArch(ArchName); 4205 bool IsV8 = (ArchKind == llvm::ARM::AK_ARMV8A || 4206 ArchKind == llvm::ARM::AK_ARMV8_1A); 4207 4208 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 4209 Features["vfp2"] = true; 4210 else if (CPU == "cortex-a8" || CPU == "cortex-a9") { 4211 Features["vfp3"] = true; 4212 Features["neon"] = true; 4213 } 4214 else if (CPU == "cortex-a5") { 4215 Features["vfp4"] = true; 4216 Features["neon"] = true; 4217 } else if (CPU == "swift" || CPU == "cortex-a7" || 4218 CPU == "cortex-a12" || CPU == "cortex-a15" || 4219 CPU == "cortex-a17" || CPU == "krait") { 4220 Features["vfp4"] = true; 4221 Features["neon"] = true; 4222 Features["hwdiv"] = true; 4223 Features["hwdiv-arm"] = true; 4224 } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" || 4225 CPU == "cortex-a72") { 4226 Features["fp-armv8"] = true; 4227 Features["neon"] = true; 4228 Features["hwdiv"] = true; 4229 Features["hwdiv-arm"] = true; 4230 Features["crc"] = true; 4231 Features["crypto"] = true; 4232 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || IsV8) { 4233 Features["hwdiv"] = true; 4234 Features["hwdiv-arm"] = true; 4235 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" || 4236 CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") { 4237 Features["hwdiv"] = true; 4238 } 4239 } 4240 4241 bool handleTargetFeatures(std::vector<std::string> &Features, 4242 DiagnosticsEngine &Diags) override { 4243 FPU = 0; 4244 CRC = 0; 4245 Crypto = 0; 4246 SoftFloat = SoftFloatABI = false; 4247 HWDiv = 0; 4248 4249 for (const auto &Feature : Features) { 4250 if (Feature == "+soft-float") { 4251 SoftFloat = true; 4252 } else if (Feature == "+soft-float-abi") { 4253 SoftFloatABI = true; 4254 } else if (Feature == "+vfp2") { 4255 FPU |= VFP2FPU; 4256 HW_FP = HW_FP_SP | HW_FP_DP; 4257 } else if (Feature == "+vfp3") { 4258 FPU |= VFP3FPU; 4259 HW_FP = HW_FP_SP | HW_FP_DP; 4260 } else if (Feature == "+vfp4") { 4261 FPU |= VFP4FPU; 4262 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 4263 } else if (Feature == "+fp-armv8") { 4264 FPU |= FPARMV8; 4265 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 4266 } else if (Feature == "+neon") { 4267 FPU |= NeonFPU; 4268 HW_FP = HW_FP_SP | HW_FP_DP; 4269 } else if (Feature == "+hwdiv") { 4270 HWDiv |= HWDivThumb; 4271 } else if (Feature == "+hwdiv-arm") { 4272 HWDiv |= HWDivARM; 4273 } else if (Feature == "+crc") { 4274 CRC = 1; 4275 } else if (Feature == "+crypto") { 4276 Crypto = 1; 4277 } else if (Feature == "+fp-only-sp") { 4278 HW_FP &= ~HW_FP_DP; 4279 } 4280 } 4281 4282 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4283 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4284 return false; 4285 } 4286 4287 if (FPMath == FP_Neon) 4288 Features.push_back("+neonfp"); 4289 else if (FPMath == FP_VFP) 4290 Features.push_back("-neonfp"); 4291 4292 // Remove front-end specific options which the backend handles differently. 4293 auto Feature = 4294 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4295 if (Feature != Features.end()) 4296 Features.erase(Feature); 4297 4298 return true; 4299 } 4300 4301 bool hasFeature(StringRef Feature) const override { 4302 return llvm::StringSwitch<bool>(Feature) 4303 .Case("arm", true) 4304 .Case("softfloat", SoftFloat) 4305 .Case("thumb", IsThumb) 4306 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4307 .Case("hwdiv", HWDiv & HWDivThumb) 4308 .Case("hwdiv-arm", HWDiv & HWDivARM) 4309 .Default(false); 4310 } 4311 const char *getCPUDefineSuffix(StringRef Name) const { 4312 if(Name == "generic") { 4313 auto subarch = getTriple().getSubArch(); 4314 switch (subarch) { 4315 case llvm::Triple::SubArchType::ARMSubArch_v8_1a: 4316 return "8_1A"; 4317 default: 4318 break; 4319 } 4320 } 4321 4322 unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(Name); 4323 if (ArchKind == llvm::ARM::AK_INVALID) 4324 return ""; 4325 4326 // For most sub-arches, the build attribute CPU name is enough. 4327 // For Cortex variants, it's slightly different. 4328 switch(ArchKind) { 4329 default: 4330 return llvm::ARMTargetParser::getCPUAttr(ArchKind); 4331 case llvm::ARM::AK_ARMV6M: 4332 case llvm::ARM::AK_ARMV6SM: 4333 return "6M"; 4334 case llvm::ARM::AK_ARMV7: 4335 case llvm::ARM::AK_ARMV7A: 4336 case llvm::ARM::AK_ARMV7S: 4337 return "7A"; 4338 case llvm::ARM::AK_ARMV7R: 4339 return "7R"; 4340 case llvm::ARM::AK_ARMV7M: 4341 return "7M"; 4342 case llvm::ARM::AK_ARMV7EM: 4343 return "7EM"; 4344 case llvm::ARM::AK_ARMV8A: 4345 return "8A"; 4346 case llvm::ARM::AK_ARMV8_1A: 4347 return "8_1A"; 4348 } 4349 } 4350 const char *getCPUProfile(StringRef Name) const { 4351 if(Name == "generic") { 4352 auto subarch = getTriple().getSubArch(); 4353 switch (subarch) { 4354 case llvm::Triple::SubArchType::ARMSubArch_v8_1a: 4355 return "A"; 4356 default: 4357 break; 4358 } 4359 } 4360 4361 unsigned CPUArch = llvm::ARMTargetParser::parseCPUArch(Name); 4362 if (CPUArch == llvm::ARM::AK_INVALID) 4363 return ""; 4364 4365 StringRef ArchName = llvm::ARMTargetParser::getArchName(CPUArch); 4366 switch(llvm::ARMTargetParser::parseArchProfile(ArchName)) { 4367 case llvm::ARM::PK_A: 4368 return "A"; 4369 case llvm::ARM::PK_R: 4370 return "R"; 4371 case llvm::ARM::PK_M: 4372 return "M"; 4373 default: 4374 return ""; 4375 } 4376 } 4377 bool setCPU(const std::string &Name) override { 4378 if (!getCPUDefineSuffix(Name)) 4379 return false; 4380 4381 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4382 StringRef Profile = getCPUProfile(Name); 4383 if (Profile == "M" && MaxAtomicInlineWidth) { 4384 MaxAtomicPromoteWidth = 32; 4385 MaxAtomicInlineWidth = 32; 4386 } 4387 4388 CPU = Name; 4389 return true; 4390 } 4391 bool setFPMath(StringRef Name) override; 4392 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 4393 unsigned CPUArchVer) const { 4394 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 4395 (CPUArch.find('M') != StringRef::npos); 4396 } 4397 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 4398 unsigned CPUArchVer) const { 4399 // We check both CPUArchVer and ArchName because when only triple is 4400 // specified, the default CPU is arm1136j-s. 4401 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 4402 ArchName.endswith("v8.1a") || 4403 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 4404 } 4405 void getTargetDefines(const LangOptions &Opts, 4406 MacroBuilder &Builder) const override { 4407 // Target identification. 4408 Builder.defineMacro("__arm"); 4409 Builder.defineMacro("__arm__"); 4410 4411 // Target properties. 4412 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4413 4414 StringRef CPUArch = getCPUDefineSuffix(CPU); 4415 unsigned int CPUArchVer; 4416 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) 4417 llvm_unreachable("Invalid char for architecture version number"); 4418 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4419 4420 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4421 StringRef CPUProfile = getCPUProfile(CPU); 4422 StringRef ArchName = getTriple().getArchName(); 4423 4424 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4425 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4426 if (CPUArch[0] >= '8') { 4427 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4428 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4429 } 4430 4431 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4432 // is not defined for the M-profile. 4433 // NOTE that the deffault profile is assumed to be 'A' 4434 if (CPUProfile.empty() || CPUProfile != "M") 4435 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4436 4437 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4438 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4439 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4440 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4441 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4442 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 4443 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4444 4445 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4446 // instruction set such as ARM or Thumb. 4447 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4448 4449 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4450 4451 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4452 if (!CPUProfile.empty()) 4453 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4454 4455 // ACLE 6.5.1 Hardware Floating Point 4456 if (HW_FP) 4457 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4458 4459 // ACLE predefines. 4460 Builder.defineMacro("__ARM_ACLE", "200"); 4461 4462 // Subtarget options. 4463 4464 // FIXME: It's more complicated than this and we don't really support 4465 // interworking. 4466 // Windows on ARM does not "support" interworking 4467 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 4468 Builder.defineMacro("__THUMB_INTERWORK__"); 4469 4470 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4471 // Embedded targets on Darwin follow AAPCS, but not EABI. 4472 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4473 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4474 Builder.defineMacro("__ARM_EABI__"); 4475 Builder.defineMacro("__ARM_PCS", "1"); 4476 4477 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4478 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4479 } 4480 4481 if (SoftFloat) 4482 Builder.defineMacro("__SOFTFP__"); 4483 4484 if (CPU == "xscale") 4485 Builder.defineMacro("__XSCALE__"); 4486 4487 if (IsThumb) { 4488 Builder.defineMacro("__THUMBEL__"); 4489 Builder.defineMacro("__thumb__"); 4490 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4491 Builder.defineMacro("__thumb2__"); 4492 } 4493 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4494 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4495 4496 // Note, this is always on in gcc, even though it doesn't make sense. 4497 Builder.defineMacro("__APCS_32__"); 4498 4499 if (FPUModeIsVFP((FPUMode) FPU)) { 4500 Builder.defineMacro("__VFP_FP__"); 4501 if (FPU & VFP2FPU) 4502 Builder.defineMacro("__ARM_VFPV2__"); 4503 if (FPU & VFP3FPU) 4504 Builder.defineMacro("__ARM_VFPV3__"); 4505 if (FPU & VFP4FPU) 4506 Builder.defineMacro("__ARM_VFPV4__"); 4507 } 4508 4509 // This only gets set when Neon instructions are actually available, unlike 4510 // the VFP define, hence the soft float and arch check. This is subtly 4511 // different from gcc, we follow the intent which was that it should be set 4512 // when Neon instructions are actually available. 4513 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4514 Builder.defineMacro("__ARM_NEON"); 4515 Builder.defineMacro("__ARM_NEON__"); 4516 } 4517 4518 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4519 Opts.ShortWChar ? "2" : "4"); 4520 4521 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4522 Opts.ShortEnums ? "1" : "4"); 4523 4524 if (CRC) 4525 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4526 4527 if (Crypto) 4528 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4529 4530 if (CPUArchVer >= 6 && CPUArch != "6M") { 4531 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4532 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4533 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4534 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4535 } 4536 4537 bool is5EOrAbove = (CPUArchVer >= 6 || 4538 (CPUArchVer == 5 && 4539 CPUArch.find('E') != StringRef::npos)); 4540 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer)); 4541 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM")) 4542 Builder.defineMacro("__ARM_FEATURE_DSP"); 4543 } 4544 void getTargetBuiltins(const Builtin::Info *&Records, 4545 unsigned &NumRecords) const override { 4546 Records = BuiltinInfo; 4547 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4548 } 4549 bool isCLZForZeroUndef() const override { return false; } 4550 BuiltinVaListKind getBuiltinVaListKind() const override { 4551 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4552 } 4553 void getGCCRegNames(const char * const *&Names, 4554 unsigned &NumNames) const override; 4555 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4556 unsigned &NumAliases) const override; 4557 bool validateAsmConstraint(const char *&Name, 4558 TargetInfo::ConstraintInfo &Info) const override { 4559 switch (*Name) { 4560 default: break; 4561 case 'l': // r0-r7 4562 case 'h': // r8-r15 4563 case 'w': // VFP Floating point register single precision 4564 case 'P': // VFP Floating point register double precision 4565 Info.setAllowsRegister(); 4566 return true; 4567 case 'I': 4568 case 'J': 4569 case 'K': 4570 case 'L': 4571 case 'M': 4572 // FIXME 4573 return true; 4574 case 'Q': // A memory address that is a single base register. 4575 Info.setAllowsMemory(); 4576 return true; 4577 case 'U': // a memory reference... 4578 switch (Name[1]) { 4579 case 'q': // ...ARMV4 ldrsb 4580 case 'v': // ...VFP load/store (reg+constant offset) 4581 case 'y': // ...iWMMXt load/store 4582 case 't': // address valid for load/store opaque types wider 4583 // than 128-bits 4584 case 'n': // valid address for Neon doubleword vector load/store 4585 case 'm': // valid address for Neon element and structure load/store 4586 case 's': // valid address for non-offset loads/stores of quad-word 4587 // values in four ARM registers 4588 Info.setAllowsMemory(); 4589 Name++; 4590 return true; 4591 } 4592 } 4593 return false; 4594 } 4595 std::string convertConstraint(const char *&Constraint) const override { 4596 std::string R; 4597 switch (*Constraint) { 4598 case 'U': // Two-character constraint; add "^" hint for later parsing. 4599 R = std::string("^") + std::string(Constraint, 2); 4600 Constraint++; 4601 break; 4602 case 'p': // 'p' should be translated to 'r' by default. 4603 R = std::string("r"); 4604 break; 4605 default: 4606 return std::string(1, *Constraint); 4607 } 4608 return R; 4609 } 4610 bool 4611 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4612 std::string &SuggestedModifier) const override { 4613 bool isOutput = (Constraint[0] == '='); 4614 bool isInOut = (Constraint[0] == '+'); 4615 4616 // Strip off constraint modifiers. 4617 while (Constraint[0] == '=' || 4618 Constraint[0] == '+' || 4619 Constraint[0] == '&') 4620 Constraint = Constraint.substr(1); 4621 4622 switch (Constraint[0]) { 4623 default: break; 4624 case 'r': { 4625 switch (Modifier) { 4626 default: 4627 return (isInOut || isOutput || Size <= 64); 4628 case 'q': 4629 // A register of size 32 cannot fit a vector type. 4630 return false; 4631 } 4632 } 4633 } 4634 4635 return true; 4636 } 4637 const char *getClobbers() const override { 4638 // FIXME: Is this really right? 4639 return ""; 4640 } 4641 4642 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4643 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4644 } 4645 4646 int getEHDataRegisterNumber(unsigned RegNo) const override { 4647 if (RegNo == 0) return 0; 4648 if (RegNo == 1) return 1; 4649 return -1; 4650 } 4651 }; 4652 4653 bool ARMTargetInfo::setFPMath(StringRef Name) { 4654 if (Name == "neon") { 4655 FPMath = FP_Neon; 4656 return true; 4657 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4658 Name == "vfp4") { 4659 FPMath = FP_VFP; 4660 return true; 4661 } 4662 return false; 4663 } 4664 4665 const char * const ARMTargetInfo::GCCRegNames[] = { 4666 // Integer registers 4667 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4668 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4669 4670 // Float registers 4671 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4672 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4673 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4674 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4675 4676 // Double registers 4677 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4678 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4679 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4680 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4681 4682 // Quad registers 4683 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4684 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4685 }; 4686 4687 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4688 unsigned &NumNames) const { 4689 Names = GCCRegNames; 4690 NumNames = llvm::array_lengthof(GCCRegNames); 4691 } 4692 4693 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4694 { { "a1" }, "r0" }, 4695 { { "a2" }, "r1" }, 4696 { { "a3" }, "r2" }, 4697 { { "a4" }, "r3" }, 4698 { { "v1" }, "r4" }, 4699 { { "v2" }, "r5" }, 4700 { { "v3" }, "r6" }, 4701 { { "v4" }, "r7" }, 4702 { { "v5" }, "r8" }, 4703 { { "v6", "rfp" }, "r9" }, 4704 { { "sl" }, "r10" }, 4705 { { "fp" }, "r11" }, 4706 { { "ip" }, "r12" }, 4707 { { "r13" }, "sp" }, 4708 { { "r14" }, "lr" }, 4709 { { "r15" }, "pc" }, 4710 // The S, D and Q registers overlap, but aren't really aliases; we 4711 // don't want to substitute one of these for a different-sized one. 4712 }; 4713 4714 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4715 unsigned &NumAliases) const { 4716 Aliases = GCCRegAliases; 4717 NumAliases = llvm::array_lengthof(GCCRegAliases); 4718 } 4719 4720 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4721 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4722 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4723 ALL_LANGUAGES }, 4724 #include "clang/Basic/BuiltinsNEON.def" 4725 4726 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4727 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG }, 4728 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4729 ALL_LANGUAGES }, 4730 #include "clang/Basic/BuiltinsARM.def" 4731 }; 4732 4733 class ARMleTargetInfo : public ARMTargetInfo { 4734 public: 4735 ARMleTargetInfo(const llvm::Triple &Triple) 4736 : ARMTargetInfo(Triple, false) { } 4737 void getTargetDefines(const LangOptions &Opts, 4738 MacroBuilder &Builder) const override { 4739 Builder.defineMacro("__ARMEL__"); 4740 ARMTargetInfo::getTargetDefines(Opts, Builder); 4741 } 4742 }; 4743 4744 class ARMbeTargetInfo : public ARMTargetInfo { 4745 public: 4746 ARMbeTargetInfo(const llvm::Triple &Triple) 4747 : ARMTargetInfo(Triple, true) { } 4748 void getTargetDefines(const LangOptions &Opts, 4749 MacroBuilder &Builder) const override { 4750 Builder.defineMacro("__ARMEB__"); 4751 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4752 ARMTargetInfo::getTargetDefines(Opts, Builder); 4753 } 4754 }; 4755 4756 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4757 const llvm::Triple Triple; 4758 public: 4759 WindowsARMTargetInfo(const llvm::Triple &Triple) 4760 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4761 TLSSupported = false; 4762 WCharType = UnsignedShort; 4763 SizeType = UnsignedInt; 4764 UserLabelPrefix = ""; 4765 } 4766 void getVisualStudioDefines(const LangOptions &Opts, 4767 MacroBuilder &Builder) const { 4768 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4769 4770 // FIXME: this is invalid for WindowsCE 4771 Builder.defineMacro("_M_ARM_NT", "1"); 4772 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4773 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4774 4775 assert((Triple.getArch() == llvm::Triple::arm || 4776 Triple.getArch() == llvm::Triple::thumb) && 4777 "invalid architecture for Windows ARM target info"); 4778 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4779 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4780 4781 // TODO map the complete set of values 4782 // 31: VFPv3 40: VFPv4 4783 Builder.defineMacro("_M_ARM_FP", "31"); 4784 } 4785 BuiltinVaListKind getBuiltinVaListKind() const override { 4786 return TargetInfo::CharPtrBuiltinVaList; 4787 } 4788 }; 4789 4790 // Windows ARM + Itanium C++ ABI Target 4791 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4792 public: 4793 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4794 : WindowsARMTargetInfo(Triple) { 4795 TheCXXABI.set(TargetCXXABI::GenericARM); 4796 } 4797 4798 void getTargetDefines(const LangOptions &Opts, 4799 MacroBuilder &Builder) const override { 4800 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4801 4802 if (Opts.MSVCCompat) 4803 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4804 } 4805 }; 4806 4807 // Windows ARM, MS (C++) ABI 4808 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4809 public: 4810 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4811 : WindowsARMTargetInfo(Triple) { 4812 TheCXXABI.set(TargetCXXABI::Microsoft); 4813 } 4814 4815 void getTargetDefines(const LangOptions &Opts, 4816 MacroBuilder &Builder) const override { 4817 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4818 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4819 } 4820 }; 4821 4822 class DarwinARMTargetInfo : 4823 public DarwinTargetInfo<ARMleTargetInfo> { 4824 protected: 4825 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4826 MacroBuilder &Builder) const override { 4827 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4828 } 4829 4830 public: 4831 DarwinARMTargetInfo(const llvm::Triple &Triple) 4832 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4833 HasAlignMac68kSupport = true; 4834 // iOS always has 64-bit atomic instructions. 4835 // FIXME: This should be based off of the target features in 4836 // ARMleTargetInfo. 4837 MaxAtomicInlineWidth = 64; 4838 4839 // Darwin on iOS uses a variant of the ARM C++ ABI. 4840 TheCXXABI.set(TargetCXXABI::iOS); 4841 } 4842 }; 4843 4844 class AArch64TargetInfo : public TargetInfo { 4845 virtual void setDescriptionString() = 0; 4846 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4847 static const char *const GCCRegNames[]; 4848 4849 enum FPUModeEnum { 4850 FPUMode, 4851 NeonMode 4852 }; 4853 4854 unsigned FPU; 4855 unsigned CRC; 4856 unsigned Crypto; 4857 4858 static const Builtin::Info BuiltinInfo[]; 4859 4860 std::string ABI; 4861 4862 public: 4863 AArch64TargetInfo(const llvm::Triple &Triple) 4864 : TargetInfo(Triple), ABI("aapcs") { 4865 4866 if (getTriple().getOS() == llvm::Triple::NetBSD) { 4867 WCharType = SignedInt; 4868 4869 // NetBSD apparently prefers consistency across ARM targets to consistency 4870 // across 64-bit targets. 4871 Int64Type = SignedLongLong; 4872 IntMaxType = SignedLongLong; 4873 } else { 4874 WCharType = UnsignedInt; 4875 Int64Type = SignedLong; 4876 IntMaxType = SignedLong; 4877 } 4878 4879 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4880 MaxVectorAlign = 128; 4881 RegParmMax = 8; 4882 MaxAtomicInlineWidth = 128; 4883 MaxAtomicPromoteWidth = 128; 4884 4885 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 4886 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4887 4888 // {} in inline assembly are neon specifiers, not assembly variant 4889 // specifiers. 4890 NoAsmVariants = true; 4891 4892 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 4893 // contributes to the alignment of the containing aggregate in the same way 4894 // a plain (non bit-field) member of that type would, without exception for 4895 // zero-sized or anonymous bit-fields." 4896 UseBitFieldTypeAlignment = true; 4897 UseZeroLengthBitfieldAlignment = true; 4898 4899 // AArch64 targets default to using the ARM C++ ABI. 4900 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4901 } 4902 4903 StringRef getABI() const override { return ABI; } 4904 bool setABI(const std::string &Name) override { 4905 if (Name != "aapcs" && Name != "darwinpcs") 4906 return false; 4907 4908 ABI = Name; 4909 return true; 4910 } 4911 4912 bool setCPU(const std::string &Name) override { 4913 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4914 .Case("generic", true) 4915 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 4916 .Case("cyclone", true) 4917 .Default(false); 4918 return CPUKnown; 4919 } 4920 4921 void getTargetDefines(const LangOptions &Opts, 4922 MacroBuilder &Builder) const override { 4923 // Target identification. 4924 Builder.defineMacro("__aarch64__"); 4925 4926 // Target properties. 4927 Builder.defineMacro("_LP64"); 4928 Builder.defineMacro("__LP64__"); 4929 4930 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4931 Builder.defineMacro("__ARM_ACLE", "200"); 4932 Builder.defineMacro("__ARM_ARCH", "8"); 4933 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4934 4935 Builder.defineMacro("__ARM_64BIT_STATE"); 4936 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4937 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4938 4939 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4940 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4941 Builder.defineMacro("__ARM_FEATURE_FMA"); 4942 Builder.defineMacro("__ARM_FEATURE_DIV"); 4943 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE 4944 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 4945 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4946 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4947 4948 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 4949 4950 // 0xe implies support for half, single and double precision operations. 4951 Builder.defineMacro("__ARM_FP", "0xe"); 4952 4953 // PCS specifies this for SysV variants, which is all we support. Other ABIs 4954 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 4955 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 4956 4957 if (Opts.FastMath || Opts.FiniteMathOnly) 4958 Builder.defineMacro("__ARM_FP_FAST"); 4959 4960 if (Opts.C99 && !Opts.Freestanding) 4961 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 4962 4963 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 4964 4965 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4966 Opts.ShortEnums ? "1" : "4"); 4967 4968 if (FPU == NeonMode) { 4969 Builder.defineMacro("__ARM_NEON"); 4970 // 64-bit NEON supports half, single and double precision operations. 4971 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 4972 } 4973 4974 if (CRC) 4975 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4976 4977 if (Crypto) 4978 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4979 4980 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 4981 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4982 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4983 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4984 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4985 } 4986 4987 void getTargetBuiltins(const Builtin::Info *&Records, 4988 unsigned &NumRecords) const override { 4989 Records = BuiltinInfo; 4990 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 4991 } 4992 4993 bool hasFeature(StringRef Feature) const override { 4994 return Feature == "aarch64" || 4995 Feature == "arm64" || 4996 (Feature == "neon" && FPU == NeonMode); 4997 } 4998 4999 bool handleTargetFeatures(std::vector<std::string> &Features, 5000 DiagnosticsEngine &Diags) override { 5001 FPU = FPUMode; 5002 CRC = 0; 5003 Crypto = 0; 5004 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 5005 if (Features[i] == "+neon") 5006 FPU = NeonMode; 5007 if (Features[i] == "+crc") 5008 CRC = 1; 5009 if (Features[i] == "+crypto") 5010 Crypto = 1; 5011 } 5012 5013 setDescriptionString(); 5014 5015 return true; 5016 } 5017 5018 bool isCLZForZeroUndef() const override { return false; } 5019 5020 BuiltinVaListKind getBuiltinVaListKind() const override { 5021 return TargetInfo::AArch64ABIBuiltinVaList; 5022 } 5023 5024 void getGCCRegNames(const char *const *&Names, 5025 unsigned &NumNames) const override; 5026 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5027 unsigned &NumAliases) const override; 5028 5029 bool validateAsmConstraint(const char *&Name, 5030 TargetInfo::ConstraintInfo &Info) const override { 5031 switch (*Name) { 5032 default: 5033 return false; 5034 case 'w': // Floating point and SIMD registers (V0-V31) 5035 Info.setAllowsRegister(); 5036 return true; 5037 case 'I': // Constant that can be used with an ADD instruction 5038 case 'J': // Constant that can be used with a SUB instruction 5039 case 'K': // Constant that can be used with a 32-bit logical instruction 5040 case 'L': // Constant that can be used with a 64-bit logical instruction 5041 case 'M': // Constant that can be used as a 32-bit MOV immediate 5042 case 'N': // Constant that can be used as a 64-bit MOV immediate 5043 case 'Y': // Floating point constant zero 5044 case 'Z': // Integer constant zero 5045 return true; 5046 case 'Q': // A memory reference with base register and no offset 5047 Info.setAllowsMemory(); 5048 return true; 5049 case 'S': // A symbolic address 5050 Info.setAllowsRegister(); 5051 return true; 5052 case 'U': 5053 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5054 // Utf: A memory address suitable for ldp/stp in TF mode. 5055 // Usa: An absolute symbolic address. 5056 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5057 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5058 case 'z': // Zero register, wzr or xzr 5059 Info.setAllowsRegister(); 5060 return true; 5061 case 'x': // Floating point and SIMD registers (V0-V15) 5062 Info.setAllowsRegister(); 5063 return true; 5064 } 5065 return false; 5066 } 5067 5068 bool 5069 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5070 std::string &SuggestedModifier) const override { 5071 // Strip off constraint modifiers. 5072 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5073 Constraint = Constraint.substr(1); 5074 5075 switch (Constraint[0]) { 5076 default: 5077 return true; 5078 case 'z': 5079 case 'r': { 5080 switch (Modifier) { 5081 case 'x': 5082 case 'w': 5083 // For now assume that the person knows what they're 5084 // doing with the modifier. 5085 return true; 5086 default: 5087 // By default an 'r' constraint will be in the 'x' 5088 // registers. 5089 if (Size == 64) 5090 return true; 5091 5092 SuggestedModifier = "w"; 5093 return false; 5094 } 5095 } 5096 } 5097 } 5098 5099 const char *getClobbers() const override { return ""; } 5100 5101 int getEHDataRegisterNumber(unsigned RegNo) const override { 5102 if (RegNo == 0) 5103 return 0; 5104 if (RegNo == 1) 5105 return 1; 5106 return -1; 5107 } 5108 }; 5109 5110 const char *const AArch64TargetInfo::GCCRegNames[] = { 5111 // 32-bit Integer registers 5112 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5113 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5114 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5115 5116 // 64-bit Integer registers 5117 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5118 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5119 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5120 5121 // 32-bit floating point regsisters 5122 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5123 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5124 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5125 5126 // 64-bit floating point regsisters 5127 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5128 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5129 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5130 5131 // Vector registers 5132 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5133 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5134 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5135 }; 5136 5137 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 5138 unsigned &NumNames) const { 5139 Names = GCCRegNames; 5140 NumNames = llvm::array_lengthof(GCCRegNames); 5141 } 5142 5143 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5144 { { "w31" }, "wsp" }, 5145 { { "x29" }, "fp" }, 5146 { { "x30" }, "lr" }, 5147 { { "x31" }, "sp" }, 5148 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5149 // don't want to substitute one of these for a different-sized one. 5150 }; 5151 5152 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5153 unsigned &NumAliases) const { 5154 Aliases = GCCRegAliases; 5155 NumAliases = llvm::array_lengthof(GCCRegAliases); 5156 } 5157 5158 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5159 #define BUILTIN(ID, TYPE, ATTRS) \ 5160 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5161 #include "clang/Basic/BuiltinsNEON.def" 5162 5163 #define BUILTIN(ID, TYPE, ATTRS) \ 5164 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5165 #include "clang/Basic/BuiltinsAArch64.def" 5166 }; 5167 5168 class AArch64leTargetInfo : public AArch64TargetInfo { 5169 void setDescriptionString() override { 5170 if (getTriple().isOSBinFormatMachO()) 5171 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5172 else 5173 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5174 } 5175 5176 public: 5177 AArch64leTargetInfo(const llvm::Triple &Triple) 5178 : AArch64TargetInfo(Triple) { 5179 BigEndian = false; 5180 } 5181 void getTargetDefines(const LangOptions &Opts, 5182 MacroBuilder &Builder) const override { 5183 Builder.defineMacro("__AARCH64EL__"); 5184 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5185 } 5186 }; 5187 5188 class AArch64beTargetInfo : public AArch64TargetInfo { 5189 void setDescriptionString() override { 5190 assert(!getTriple().isOSBinFormatMachO()); 5191 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5192 } 5193 5194 public: 5195 AArch64beTargetInfo(const llvm::Triple &Triple) 5196 : AArch64TargetInfo(Triple) { } 5197 void getTargetDefines(const LangOptions &Opts, 5198 MacroBuilder &Builder) const override { 5199 Builder.defineMacro("__AARCH64EB__"); 5200 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5201 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5202 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5203 } 5204 }; 5205 5206 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5207 protected: 5208 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5209 MacroBuilder &Builder) const override { 5210 Builder.defineMacro("__AARCH64_SIMD__"); 5211 Builder.defineMacro("__ARM64_ARCH_8__"); 5212 Builder.defineMacro("__ARM_NEON__"); 5213 Builder.defineMacro("__LITTLE_ENDIAN__"); 5214 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5215 Builder.defineMacro("__arm64", "1"); 5216 Builder.defineMacro("__arm64__", "1"); 5217 5218 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5219 } 5220 5221 public: 5222 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5223 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5224 Int64Type = SignedLongLong; 5225 WCharType = SignedInt; 5226 UseSignedCharForObjCBool = false; 5227 5228 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5229 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5230 5231 TheCXXABI.set(TargetCXXABI::iOS64); 5232 } 5233 5234 BuiltinVaListKind getBuiltinVaListKind() const override { 5235 return TargetInfo::CharPtrBuiltinVaList; 5236 } 5237 }; 5238 5239 // Hexagon abstract base class 5240 class HexagonTargetInfo : public TargetInfo { 5241 static const Builtin::Info BuiltinInfo[]; 5242 static const char * const GCCRegNames[]; 5243 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5244 std::string CPU; 5245 public: 5246 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5247 BigEndian = false; 5248 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5249 5250 // {} in inline assembly are packet specifiers, not assembly variant 5251 // specifiers. 5252 NoAsmVariants = true; 5253 } 5254 5255 void getTargetBuiltins(const Builtin::Info *&Records, 5256 unsigned &NumRecords) const override { 5257 Records = BuiltinInfo; 5258 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5259 } 5260 5261 bool validateAsmConstraint(const char *&Name, 5262 TargetInfo::ConstraintInfo &Info) const override { 5263 return true; 5264 } 5265 5266 void getTargetDefines(const LangOptions &Opts, 5267 MacroBuilder &Builder) const override; 5268 5269 bool hasFeature(StringRef Feature) const override { 5270 return Feature == "hexagon"; 5271 } 5272 5273 BuiltinVaListKind getBuiltinVaListKind() const override { 5274 return TargetInfo::CharPtrBuiltinVaList; 5275 } 5276 void getGCCRegNames(const char * const *&Names, 5277 unsigned &NumNames) const override; 5278 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5279 unsigned &NumAliases) const override; 5280 const char *getClobbers() const override { 5281 return ""; 5282 } 5283 5284 static const char *getHexagonCPUSuffix(StringRef Name) { 5285 return llvm::StringSwitch<const char*>(Name) 5286 .Case("hexagonv4", "4") 5287 .Case("hexagonv5", "5") 5288 .Default(nullptr); 5289 } 5290 5291 bool setCPU(const std::string &Name) override { 5292 if (!getHexagonCPUSuffix(Name)) 5293 return false; 5294 5295 CPU = Name; 5296 return true; 5297 } 5298 }; 5299 5300 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5301 MacroBuilder &Builder) const { 5302 Builder.defineMacro("qdsp6"); 5303 Builder.defineMacro("__qdsp6", "1"); 5304 Builder.defineMacro("__qdsp6__", "1"); 5305 5306 Builder.defineMacro("hexagon"); 5307 Builder.defineMacro("__hexagon", "1"); 5308 Builder.defineMacro("__hexagon__", "1"); 5309 5310 if(CPU == "hexagonv1") { 5311 Builder.defineMacro("__HEXAGON_V1__"); 5312 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5313 if(Opts.HexagonQdsp6Compat) { 5314 Builder.defineMacro("__QDSP6_V1__"); 5315 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5316 } 5317 } 5318 else if(CPU == "hexagonv2") { 5319 Builder.defineMacro("__HEXAGON_V2__"); 5320 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5321 if(Opts.HexagonQdsp6Compat) { 5322 Builder.defineMacro("__QDSP6_V2__"); 5323 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5324 } 5325 } 5326 else if(CPU == "hexagonv3") { 5327 Builder.defineMacro("__HEXAGON_V3__"); 5328 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5329 if(Opts.HexagonQdsp6Compat) { 5330 Builder.defineMacro("__QDSP6_V3__"); 5331 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5332 } 5333 } 5334 else if(CPU == "hexagonv4") { 5335 Builder.defineMacro("__HEXAGON_V4__"); 5336 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5337 if(Opts.HexagonQdsp6Compat) { 5338 Builder.defineMacro("__QDSP6_V4__"); 5339 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5340 } 5341 } 5342 else if(CPU == "hexagonv5") { 5343 Builder.defineMacro("__HEXAGON_V5__"); 5344 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5345 if(Opts.HexagonQdsp6Compat) { 5346 Builder.defineMacro("__QDSP6_V5__"); 5347 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5348 } 5349 } 5350 } 5351 5352 const char * const HexagonTargetInfo::GCCRegNames[] = { 5353 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5354 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5355 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5356 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5357 "p0", "p1", "p2", "p3", 5358 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5359 }; 5360 5361 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5362 unsigned &NumNames) const { 5363 Names = GCCRegNames; 5364 NumNames = llvm::array_lengthof(GCCRegNames); 5365 } 5366 5367 5368 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5369 { { "sp" }, "r29" }, 5370 { { "fp" }, "r30" }, 5371 { { "lr" }, "r31" }, 5372 }; 5373 5374 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5375 unsigned &NumAliases) const { 5376 Aliases = GCCRegAliases; 5377 NumAliases = llvm::array_lengthof(GCCRegAliases); 5378 } 5379 5380 5381 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5382 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5383 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5384 ALL_LANGUAGES }, 5385 #include "clang/Basic/BuiltinsHexagon.def" 5386 }; 5387 5388 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5389 class SparcTargetInfo : public TargetInfo { 5390 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5391 static const char * const GCCRegNames[]; 5392 bool SoftFloat; 5393 public: 5394 SparcTargetInfo(const llvm::Triple &Triple) 5395 : TargetInfo(Triple), SoftFloat(false) {} 5396 5397 bool handleTargetFeatures(std::vector<std::string> &Features, 5398 DiagnosticsEngine &Diags) override { 5399 // The backend doesn't actually handle soft float yet, but in case someone 5400 // is using the support for the front end continue to support it. 5401 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5402 if (Feature != Features.end()) { 5403 SoftFloat = true; 5404 Features.erase(Feature); 5405 } 5406 return true; 5407 } 5408 void getTargetDefines(const LangOptions &Opts, 5409 MacroBuilder &Builder) const override { 5410 DefineStd(Builder, "sparc", Opts); 5411 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5412 5413 if (SoftFloat) 5414 Builder.defineMacro("SOFT_FLOAT", "1"); 5415 } 5416 5417 bool hasFeature(StringRef Feature) const override { 5418 return llvm::StringSwitch<bool>(Feature) 5419 .Case("softfloat", SoftFloat) 5420 .Case("sparc", true) 5421 .Default(false); 5422 } 5423 5424 void getTargetBuiltins(const Builtin::Info *&Records, 5425 unsigned &NumRecords) const override { 5426 // FIXME: Implement! 5427 } 5428 BuiltinVaListKind getBuiltinVaListKind() const override { 5429 return TargetInfo::VoidPtrBuiltinVaList; 5430 } 5431 void getGCCRegNames(const char * const *&Names, 5432 unsigned &NumNames) const override; 5433 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5434 unsigned &NumAliases) const override; 5435 bool validateAsmConstraint(const char *&Name, 5436 TargetInfo::ConstraintInfo &info) const override { 5437 // FIXME: Implement! 5438 switch (*Name) { 5439 case 'I': // Signed 13-bit constant 5440 case 'J': // Zero 5441 case 'K': // 32-bit constant with the low 12 bits clear 5442 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5443 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5444 case 'N': // Same as 'K' but zext (required for SIMode) 5445 case 'O': // The constant 4096 5446 return true; 5447 } 5448 return false; 5449 } 5450 const char *getClobbers() const override { 5451 // FIXME: Implement! 5452 return ""; 5453 } 5454 }; 5455 5456 const char * const SparcTargetInfo::GCCRegNames[] = { 5457 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5458 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5459 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5460 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5461 }; 5462 5463 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5464 unsigned &NumNames) const { 5465 Names = GCCRegNames; 5466 NumNames = llvm::array_lengthof(GCCRegNames); 5467 } 5468 5469 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5470 { { "g0" }, "r0" }, 5471 { { "g1" }, "r1" }, 5472 { { "g2" }, "r2" }, 5473 { { "g3" }, "r3" }, 5474 { { "g4" }, "r4" }, 5475 { { "g5" }, "r5" }, 5476 { { "g6" }, "r6" }, 5477 { { "g7" }, "r7" }, 5478 { { "o0" }, "r8" }, 5479 { { "o1" }, "r9" }, 5480 { { "o2" }, "r10" }, 5481 { { "o3" }, "r11" }, 5482 { { "o4" }, "r12" }, 5483 { { "o5" }, "r13" }, 5484 { { "o6", "sp" }, "r14" }, 5485 { { "o7" }, "r15" }, 5486 { { "l0" }, "r16" }, 5487 { { "l1" }, "r17" }, 5488 { { "l2" }, "r18" }, 5489 { { "l3" }, "r19" }, 5490 { { "l4" }, "r20" }, 5491 { { "l5" }, "r21" }, 5492 { { "l6" }, "r22" }, 5493 { { "l7" }, "r23" }, 5494 { { "i0" }, "r24" }, 5495 { { "i1" }, "r25" }, 5496 { { "i2" }, "r26" }, 5497 { { "i3" }, "r27" }, 5498 { { "i4" }, "r28" }, 5499 { { "i5" }, "r29" }, 5500 { { "i6", "fp" }, "r30" }, 5501 { { "i7" }, "r31" }, 5502 }; 5503 5504 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5505 unsigned &NumAliases) const { 5506 Aliases = GCCRegAliases; 5507 NumAliases = llvm::array_lengthof(GCCRegAliases); 5508 } 5509 5510 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5511 class SparcV8TargetInfo : public SparcTargetInfo { 5512 public: 5513 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5514 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5515 // NetBSD uses long (same as llvm default); everyone else uses int. 5516 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5517 SizeType = UnsignedLong; 5518 IntPtrType = SignedLong; 5519 PtrDiffType = SignedLong; 5520 } else { 5521 SizeType = UnsignedInt; 5522 IntPtrType = SignedInt; 5523 PtrDiffType = SignedInt; 5524 } 5525 } 5526 5527 void getTargetDefines(const LangOptions &Opts, 5528 MacroBuilder &Builder) const override { 5529 SparcTargetInfo::getTargetDefines(Opts, Builder); 5530 Builder.defineMacro("__sparcv8"); 5531 } 5532 }; 5533 5534 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 5535 class SparcV8elTargetInfo : public SparcV8TargetInfo { 5536 public: 5537 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 5538 DescriptionString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5539 BigEndian = false; 5540 } 5541 }; 5542 5543 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5544 class SparcV9TargetInfo : public SparcTargetInfo { 5545 public: 5546 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5547 // FIXME: Support Sparc quad-precision long double? 5548 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5549 // This is an LP64 platform. 5550 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5551 5552 // OpenBSD uses long long for int64_t and intmax_t. 5553 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5554 IntMaxType = SignedLongLong; 5555 else 5556 IntMaxType = SignedLong; 5557 Int64Type = IntMaxType; 5558 5559 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5560 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5561 LongDoubleWidth = 128; 5562 LongDoubleAlign = 128; 5563 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5564 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5565 } 5566 5567 void getTargetDefines(const LangOptions &Opts, 5568 MacroBuilder &Builder) const override { 5569 SparcTargetInfo::getTargetDefines(Opts, Builder); 5570 Builder.defineMacro("__sparcv9"); 5571 Builder.defineMacro("__arch64__"); 5572 // Solaris doesn't need these variants, but the BSDs do. 5573 if (getTriple().getOS() != llvm::Triple::Solaris) { 5574 Builder.defineMacro("__sparc64__"); 5575 Builder.defineMacro("__sparc_v9__"); 5576 Builder.defineMacro("__sparcv9__"); 5577 } 5578 } 5579 5580 bool setCPU(const std::string &Name) override { 5581 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5582 .Case("v9", true) 5583 .Case("ultrasparc", true) 5584 .Case("ultrasparc3", true) 5585 .Case("niagara", true) 5586 .Case("niagara2", true) 5587 .Case("niagara3", true) 5588 .Case("niagara4", true) 5589 .Default(false); 5590 5591 // No need to store the CPU yet. There aren't any CPU-specific 5592 // macros to define. 5593 return CPUKnown; 5594 } 5595 }; 5596 5597 class SystemZTargetInfo : public TargetInfo { 5598 static const Builtin::Info BuiltinInfo[]; 5599 static const char *const GCCRegNames[]; 5600 std::string CPU; 5601 bool HasTransactionalExecution; 5602 bool HasVector; 5603 5604 public: 5605 SystemZTargetInfo(const llvm::Triple &Triple) 5606 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) { 5607 IntMaxType = SignedLong; 5608 Int64Type = SignedLong; 5609 TLSSupported = true; 5610 IntWidth = IntAlign = 32; 5611 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5612 PointerWidth = PointerAlign = 64; 5613 LongDoubleWidth = 128; 5614 LongDoubleAlign = 64; 5615 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5616 DefaultAlignForAttributeAligned = 64; 5617 MinGlobalAlign = 16; 5618 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5619 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5620 } 5621 void getTargetDefines(const LangOptions &Opts, 5622 MacroBuilder &Builder) const override { 5623 Builder.defineMacro("__s390__"); 5624 Builder.defineMacro("__s390x__"); 5625 Builder.defineMacro("__zarch__"); 5626 Builder.defineMacro("__LONG_DOUBLE_128__"); 5627 if (HasTransactionalExecution) 5628 Builder.defineMacro("__HTM__"); 5629 } 5630 void getTargetBuiltins(const Builtin::Info *&Records, 5631 unsigned &NumRecords) const override { 5632 Records = BuiltinInfo; 5633 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin; 5634 } 5635 5636 void getGCCRegNames(const char *const *&Names, 5637 unsigned &NumNames) const override; 5638 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5639 unsigned &NumAliases) const override { 5640 // No aliases. 5641 Aliases = nullptr; 5642 NumAliases = 0; 5643 } 5644 bool validateAsmConstraint(const char *&Name, 5645 TargetInfo::ConstraintInfo &info) const override; 5646 const char *getClobbers() const override { 5647 // FIXME: Is this really right? 5648 return ""; 5649 } 5650 BuiltinVaListKind getBuiltinVaListKind() const override { 5651 return TargetInfo::SystemZBuiltinVaList; 5652 } 5653 bool setCPU(const std::string &Name) override { 5654 CPU = Name; 5655 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5656 .Case("z10", true) 5657 .Case("z196", true) 5658 .Case("zEC12", true) 5659 .Case("z13", true) 5660 .Default(false); 5661 5662 return CPUKnown; 5663 } 5664 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5665 if (CPU == "zEC12") 5666 Features["transactional-execution"] = true; 5667 if (CPU == "z13") { 5668 Features["transactional-execution"] = true; 5669 Features["vector"] = true; 5670 } 5671 } 5672 5673 bool handleTargetFeatures(std::vector<std::string> &Features, 5674 DiagnosticsEngine &Diags) override { 5675 HasTransactionalExecution = false; 5676 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 5677 if (Features[i] == "+transactional-execution") 5678 HasTransactionalExecution = true; 5679 if (Features[i] == "+vector") 5680 HasVector = true; 5681 } 5682 // If we use the vector ABI, vector types are 64-bit aligned. 5683 if (HasVector) { 5684 MaxVectorAlign = 64; 5685 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 5686 "-v128:64-a:8:16-n32:64"; 5687 } 5688 return true; 5689 } 5690 5691 bool hasFeature(StringRef Feature) const override { 5692 return llvm::StringSwitch<bool>(Feature) 5693 .Case("systemz", true) 5694 .Case("htm", HasTransactionalExecution) 5695 .Case("vx", HasVector) 5696 .Default(false); 5697 } 5698 5699 StringRef getABI() const override { 5700 if (HasVector) 5701 return "vector"; 5702 return ""; 5703 } 5704 5705 bool useFloat128ManglingForLongDouble() const override { 5706 return true; 5707 } 5708 }; 5709 5710 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 5711 #define BUILTIN(ID, TYPE, ATTRS) \ 5712 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5713 #include "clang/Basic/BuiltinsSystemZ.def" 5714 }; 5715 5716 const char *const SystemZTargetInfo::GCCRegNames[] = { 5717 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5718 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5719 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5720 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5721 }; 5722 5723 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5724 unsigned &NumNames) const { 5725 Names = GCCRegNames; 5726 NumNames = llvm::array_lengthof(GCCRegNames); 5727 } 5728 5729 bool SystemZTargetInfo:: 5730 validateAsmConstraint(const char *&Name, 5731 TargetInfo::ConstraintInfo &Info) const { 5732 switch (*Name) { 5733 default: 5734 return false; 5735 5736 case 'a': // Address register 5737 case 'd': // Data register (equivalent to 'r') 5738 case 'f': // Floating-point register 5739 Info.setAllowsRegister(); 5740 return true; 5741 5742 case 'I': // Unsigned 8-bit constant 5743 case 'J': // Unsigned 12-bit constant 5744 case 'K': // Signed 16-bit constant 5745 case 'L': // Signed 20-bit displacement (on all targets we support) 5746 case 'M': // 0x7fffffff 5747 return true; 5748 5749 case 'Q': // Memory with base and unsigned 12-bit displacement 5750 case 'R': // Likewise, plus an index 5751 case 'S': // Memory with base and signed 20-bit displacement 5752 case 'T': // Likewise, plus an index 5753 Info.setAllowsMemory(); 5754 return true; 5755 } 5756 } 5757 5758 class MSP430TargetInfo : public TargetInfo { 5759 static const char * const GCCRegNames[]; 5760 public: 5761 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5762 BigEndian = false; 5763 TLSSupported = false; 5764 IntWidth = 16; IntAlign = 16; 5765 LongWidth = 32; LongLongWidth = 64; 5766 LongAlign = LongLongAlign = 16; 5767 PointerWidth = 16; PointerAlign = 16; 5768 SuitableAlign = 16; 5769 SizeType = UnsignedInt; 5770 IntMaxType = SignedLongLong; 5771 IntPtrType = SignedInt; 5772 PtrDiffType = SignedInt; 5773 SigAtomicType = SignedLong; 5774 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 5775 } 5776 void getTargetDefines(const LangOptions &Opts, 5777 MacroBuilder &Builder) const override { 5778 Builder.defineMacro("MSP430"); 5779 Builder.defineMacro("__MSP430__"); 5780 // FIXME: defines for different 'flavours' of MCU 5781 } 5782 void getTargetBuiltins(const Builtin::Info *&Records, 5783 unsigned &NumRecords) const override { 5784 // FIXME: Implement. 5785 Records = nullptr; 5786 NumRecords = 0; 5787 } 5788 bool hasFeature(StringRef Feature) const override { 5789 return Feature == "msp430"; 5790 } 5791 void getGCCRegNames(const char * const *&Names, 5792 unsigned &NumNames) const override; 5793 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5794 unsigned &NumAliases) const override { 5795 // No aliases. 5796 Aliases = nullptr; 5797 NumAliases = 0; 5798 } 5799 bool 5800 validateAsmConstraint(const char *&Name, 5801 TargetInfo::ConstraintInfo &info) const override { 5802 // FIXME: implement 5803 switch (*Name) { 5804 case 'K': // the constant 1 5805 case 'L': // constant -1^20 .. 1^19 5806 case 'M': // constant 1-4: 5807 return true; 5808 } 5809 // No target constraints for now. 5810 return false; 5811 } 5812 const char *getClobbers() const override { 5813 // FIXME: Is this really right? 5814 return ""; 5815 } 5816 BuiltinVaListKind getBuiltinVaListKind() const override { 5817 // FIXME: implement 5818 return TargetInfo::CharPtrBuiltinVaList; 5819 } 5820 }; 5821 5822 const char * const MSP430TargetInfo::GCCRegNames[] = { 5823 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5824 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5825 }; 5826 5827 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5828 unsigned &NumNames) const { 5829 Names = GCCRegNames; 5830 NumNames = llvm::array_lengthof(GCCRegNames); 5831 } 5832 5833 // LLVM and Clang cannot be used directly to output native binaries for 5834 // target, but is used to compile C code to llvm bitcode with correct 5835 // type and alignment information. 5836 // 5837 // TCE uses the llvm bitcode as input and uses it for generating customized 5838 // target processor and program binary. TCE co-design environment is 5839 // publicly available in http://tce.cs.tut.fi 5840 5841 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5842 3, // opencl_global 5843 4, // opencl_local 5844 5, // opencl_constant 5845 // FIXME: generic has to be added to the target 5846 0, // opencl_generic 5847 0, // cuda_device 5848 0, // cuda_constant 5849 0 // cuda_shared 5850 }; 5851 5852 class TCETargetInfo : public TargetInfo{ 5853 public: 5854 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5855 TLSSupported = false; 5856 IntWidth = 32; 5857 LongWidth = LongLongWidth = 32; 5858 PointerWidth = 32; 5859 IntAlign = 32; 5860 LongAlign = LongLongAlign = 32; 5861 PointerAlign = 32; 5862 SuitableAlign = 32; 5863 SizeType = UnsignedInt; 5864 IntMaxType = SignedLong; 5865 IntPtrType = SignedInt; 5866 PtrDiffType = SignedInt; 5867 FloatWidth = 32; 5868 FloatAlign = 32; 5869 DoubleWidth = 32; 5870 DoubleAlign = 32; 5871 LongDoubleWidth = 32; 5872 LongDoubleAlign = 32; 5873 FloatFormat = &llvm::APFloat::IEEEsingle; 5874 DoubleFormat = &llvm::APFloat::IEEEsingle; 5875 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5876 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5877 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5878 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5879 UseAddrSpaceMapMangling = true; 5880 } 5881 5882 void getTargetDefines(const LangOptions &Opts, 5883 MacroBuilder &Builder) const override { 5884 DefineStd(Builder, "tce", Opts); 5885 Builder.defineMacro("__TCE__"); 5886 Builder.defineMacro("__TCE_V1__"); 5887 } 5888 bool hasFeature(StringRef Feature) const override { 5889 return Feature == "tce"; 5890 } 5891 5892 void getTargetBuiltins(const Builtin::Info *&Records, 5893 unsigned &NumRecords) const override {} 5894 const char *getClobbers() const override { 5895 return ""; 5896 } 5897 BuiltinVaListKind getBuiltinVaListKind() const override { 5898 return TargetInfo::VoidPtrBuiltinVaList; 5899 } 5900 void getGCCRegNames(const char * const *&Names, 5901 unsigned &NumNames) const override {} 5902 bool validateAsmConstraint(const char *&Name, 5903 TargetInfo::ConstraintInfo &info) const override{ 5904 return true; 5905 } 5906 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5907 unsigned &NumAliases) const override {} 5908 }; 5909 5910 class BPFTargetInfo : public TargetInfo { 5911 public: 5912 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5913 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5914 SizeType = UnsignedLong; 5915 PtrDiffType = SignedLong; 5916 IntPtrType = SignedLong; 5917 IntMaxType = SignedLong; 5918 Int64Type = SignedLong; 5919 RegParmMax = 5; 5920 if (Triple.getArch() == llvm::Triple::bpfeb) { 5921 BigEndian = true; 5922 DescriptionString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 5923 } else { 5924 BigEndian = false; 5925 DescriptionString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 5926 } 5927 MaxAtomicPromoteWidth = 64; 5928 MaxAtomicInlineWidth = 64; 5929 TLSSupported = false; 5930 } 5931 void getTargetDefines(const LangOptions &Opts, 5932 MacroBuilder &Builder) const override { 5933 DefineStd(Builder, "bpf", Opts); 5934 Builder.defineMacro("__BPF__"); 5935 } 5936 bool hasFeature(StringRef Feature) const override { 5937 return Feature == "bpf"; 5938 } 5939 5940 void getTargetBuiltins(const Builtin::Info *&Records, 5941 unsigned &NumRecords) const override {} 5942 const char *getClobbers() const override { 5943 return ""; 5944 } 5945 BuiltinVaListKind getBuiltinVaListKind() const override { 5946 return TargetInfo::VoidPtrBuiltinVaList; 5947 } 5948 void getGCCRegNames(const char * const *&Names, 5949 unsigned &NumNames) const override { 5950 Names = nullptr; 5951 NumNames = 0; 5952 } 5953 bool validateAsmConstraint(const char *&Name, 5954 TargetInfo::ConstraintInfo &info) const override { 5955 return true; 5956 } 5957 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5958 unsigned &NumAliases) const override { 5959 Aliases = nullptr; 5960 NumAliases = 0; 5961 } 5962 }; 5963 5964 class MipsTargetInfoBase : public TargetInfo { 5965 virtual void setDescriptionString() = 0; 5966 5967 static const Builtin::Info BuiltinInfo[]; 5968 std::string CPU; 5969 bool IsMips16; 5970 bool IsMicromips; 5971 bool IsNan2008; 5972 bool IsSingleFloat; 5973 enum MipsFloatABI { 5974 HardFloat, SoftFloat 5975 } FloatABI; 5976 enum DspRevEnum { 5977 NoDSP, DSP1, DSP2 5978 } DspRev; 5979 bool HasMSA; 5980 5981 protected: 5982 bool HasFP64; 5983 std::string ABI; 5984 5985 public: 5986 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5987 const std::string &CPUStr) 5988 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5989 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5990 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 5991 TheCXXABI.set(TargetCXXABI::GenericMIPS); 5992 } 5993 5994 bool isNaN2008Default() const { 5995 return CPU == "mips32r6" || CPU == "mips64r6"; 5996 } 5997 5998 bool isFP64Default() const { 5999 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6000 } 6001 6002 bool isNan2008() const override { 6003 return IsNan2008; 6004 } 6005 6006 StringRef getABI() const override { return ABI; } 6007 bool setCPU(const std::string &Name) override { 6008 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6009 getTriple().getArch() == llvm::Triple::mipsel; 6010 CPU = Name; 6011 return llvm::StringSwitch<bool>(Name) 6012 .Case("mips1", IsMips32) 6013 .Case("mips2", IsMips32) 6014 .Case("mips3", true) 6015 .Case("mips4", true) 6016 .Case("mips5", true) 6017 .Case("mips32", IsMips32) 6018 .Case("mips32r2", IsMips32) 6019 .Case("mips32r3", IsMips32) 6020 .Case("mips32r5", IsMips32) 6021 .Case("mips32r6", IsMips32) 6022 .Case("mips64", true) 6023 .Case("mips64r2", true) 6024 .Case("mips64r3", true) 6025 .Case("mips64r5", true) 6026 .Case("mips64r6", true) 6027 .Case("octeon", true) 6028 .Default(false); 6029 } 6030 const std::string& getCPU() const { return CPU; } 6031 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6032 if (CPU == "octeon") 6033 Features["mips64r2"] = Features["cnmips"] = true; 6034 else 6035 Features[CPU] = true; 6036 } 6037 6038 void getTargetDefines(const LangOptions &Opts, 6039 MacroBuilder &Builder) const override { 6040 Builder.defineMacro("__mips__"); 6041 Builder.defineMacro("_mips"); 6042 if (Opts.GNUMode) 6043 Builder.defineMacro("mips"); 6044 6045 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6046 6047 switch (FloatABI) { 6048 case HardFloat: 6049 Builder.defineMacro("__mips_hard_float", Twine(1)); 6050 break; 6051 case SoftFloat: 6052 Builder.defineMacro("__mips_soft_float", Twine(1)); 6053 break; 6054 } 6055 6056 if (IsSingleFloat) 6057 Builder.defineMacro("__mips_single_float", Twine(1)); 6058 6059 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6060 Builder.defineMacro("_MIPS_FPSET", 6061 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6062 6063 if (IsMips16) 6064 Builder.defineMacro("__mips16", Twine(1)); 6065 6066 if (IsMicromips) 6067 Builder.defineMacro("__mips_micromips", Twine(1)); 6068 6069 if (IsNan2008) 6070 Builder.defineMacro("__mips_nan2008", Twine(1)); 6071 6072 switch (DspRev) { 6073 default: 6074 break; 6075 case DSP1: 6076 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6077 Builder.defineMacro("__mips_dsp", Twine(1)); 6078 break; 6079 case DSP2: 6080 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6081 Builder.defineMacro("__mips_dspr2", Twine(1)); 6082 Builder.defineMacro("__mips_dsp", Twine(1)); 6083 break; 6084 } 6085 6086 if (HasMSA) 6087 Builder.defineMacro("__mips_msa", Twine(1)); 6088 6089 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6090 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6091 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6092 6093 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6094 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6095 } 6096 6097 void getTargetBuiltins(const Builtin::Info *&Records, 6098 unsigned &NumRecords) const override { 6099 Records = BuiltinInfo; 6100 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 6101 } 6102 bool hasFeature(StringRef Feature) const override { 6103 return llvm::StringSwitch<bool>(Feature) 6104 .Case("mips", true) 6105 .Case("fp64", HasFP64) 6106 .Default(false); 6107 } 6108 BuiltinVaListKind getBuiltinVaListKind() const override { 6109 return TargetInfo::VoidPtrBuiltinVaList; 6110 } 6111 void getGCCRegNames(const char * const *&Names, 6112 unsigned &NumNames) const override { 6113 static const char *const GCCRegNames[] = { 6114 // CPU register names 6115 // Must match second column of GCCRegAliases 6116 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6117 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6118 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6119 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6120 // Floating point register names 6121 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6122 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6123 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6124 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6125 // Hi/lo and condition register names 6126 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6127 "$fcc5","$fcc6","$fcc7", 6128 // MSA register names 6129 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6130 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6131 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6132 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6133 // MSA control register names 6134 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6135 "$msarequest", "$msamap", "$msaunmap" 6136 }; 6137 Names = GCCRegNames; 6138 NumNames = llvm::array_lengthof(GCCRegNames); 6139 } 6140 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6141 unsigned &NumAliases) const override = 0; 6142 bool validateAsmConstraint(const char *&Name, 6143 TargetInfo::ConstraintInfo &Info) const override { 6144 switch (*Name) { 6145 default: 6146 return false; 6147 case 'r': // CPU registers. 6148 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6149 case 'y': // Equivalent to "r", backward compatibility only. 6150 case 'f': // floating-point registers. 6151 case 'c': // $25 for indirect jumps 6152 case 'l': // lo register 6153 case 'x': // hilo register pair 6154 Info.setAllowsRegister(); 6155 return true; 6156 case 'I': // Signed 16-bit constant 6157 case 'J': // Integer 0 6158 case 'K': // Unsigned 16-bit constant 6159 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6160 case 'M': // Constants not loadable via lui, addiu, or ori 6161 case 'N': // Constant -1 to -65535 6162 case 'O': // A signed 15-bit constant 6163 case 'P': // A constant between 1 go 65535 6164 return true; 6165 case 'R': // An address that can be used in a non-macro load or store 6166 Info.setAllowsMemory(); 6167 return true; 6168 case 'Z': 6169 if (Name[1] == 'C') { // An address usable by ll, and sc. 6170 Info.setAllowsMemory(); 6171 Name++; // Skip over 'Z'. 6172 return true; 6173 } 6174 return false; 6175 } 6176 } 6177 6178 std::string convertConstraint(const char *&Constraint) const override { 6179 std::string R; 6180 switch (*Constraint) { 6181 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6182 if (Constraint[1] == 'C') { 6183 R = std::string("^") + std::string(Constraint, 2); 6184 Constraint++; 6185 return R; 6186 } 6187 break; 6188 } 6189 return TargetInfo::convertConstraint(Constraint); 6190 } 6191 6192 const char *getClobbers() const override { 6193 // In GCC, $1 is not widely used in generated code (it's used only in a few 6194 // specific situations), so there is no real need for users to add it to 6195 // the clobbers list if they want to use it in their inline assembly code. 6196 // 6197 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6198 // code generation, so using it in inline assembly without adding it to the 6199 // clobbers list can cause conflicts between the inline assembly code and 6200 // the surrounding generated code. 6201 // 6202 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6203 // operands, which will conflict with the ".set at" assembler option (which 6204 // we use only for inline assembly, in order to maintain compatibility with 6205 // GCC) and will also conflict with the user's usage of $1. 6206 // 6207 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6208 // register for generated code is to automatically clobber $1 for all inline 6209 // assembly code. 6210 // 6211 // FIXME: We should automatically clobber $1 only for inline assembly code 6212 // which actually uses it. This would allow LLVM to use $1 for inline 6213 // assembly operands if the user's assembly code doesn't use it. 6214 return "~{$1}"; 6215 } 6216 6217 bool handleTargetFeatures(std::vector<std::string> &Features, 6218 DiagnosticsEngine &Diags) override { 6219 IsMips16 = false; 6220 IsMicromips = false; 6221 IsNan2008 = isNaN2008Default(); 6222 IsSingleFloat = false; 6223 FloatABI = HardFloat; 6224 DspRev = NoDSP; 6225 HasFP64 = isFP64Default(); 6226 6227 for (std::vector<std::string>::iterator it = Features.begin(), 6228 ie = Features.end(); it != ie; ++it) { 6229 if (*it == "+single-float") 6230 IsSingleFloat = true; 6231 else if (*it == "+soft-float") 6232 FloatABI = SoftFloat; 6233 else if (*it == "+mips16") 6234 IsMips16 = true; 6235 else if (*it == "+micromips") 6236 IsMicromips = true; 6237 else if (*it == "+dsp") 6238 DspRev = std::max(DspRev, DSP1); 6239 else if (*it == "+dspr2") 6240 DspRev = std::max(DspRev, DSP2); 6241 else if (*it == "+msa") 6242 HasMSA = true; 6243 else if (*it == "+fp64") 6244 HasFP64 = true; 6245 else if (*it == "-fp64") 6246 HasFP64 = false; 6247 else if (*it == "+nan2008") 6248 IsNan2008 = true; 6249 else if (*it == "-nan2008") 6250 IsNan2008 = false; 6251 } 6252 6253 setDescriptionString(); 6254 6255 return true; 6256 } 6257 6258 int getEHDataRegisterNumber(unsigned RegNo) const override { 6259 if (RegNo == 0) return 4; 6260 if (RegNo == 1) return 5; 6261 return -1; 6262 } 6263 6264 bool isCLZForZeroUndef() const override { return false; } 6265 }; 6266 6267 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6268 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6269 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6270 ALL_LANGUAGES }, 6271 #include "clang/Basic/BuiltinsMips.def" 6272 }; 6273 6274 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6275 public: 6276 Mips32TargetInfoBase(const llvm::Triple &Triple) 6277 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6278 SizeType = UnsignedInt; 6279 PtrDiffType = SignedInt; 6280 Int64Type = SignedLongLong; 6281 IntMaxType = Int64Type; 6282 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6283 } 6284 bool setABI(const std::string &Name) override { 6285 if (Name == "o32" || Name == "eabi") { 6286 ABI = Name; 6287 return true; 6288 } 6289 return false; 6290 } 6291 void getTargetDefines(const LangOptions &Opts, 6292 MacroBuilder &Builder) const override { 6293 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6294 6295 Builder.defineMacro("__mips", "32"); 6296 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6297 6298 const std::string& CPUStr = getCPU(); 6299 if (CPUStr == "mips32") 6300 Builder.defineMacro("__mips_isa_rev", "1"); 6301 else if (CPUStr == "mips32r2") 6302 Builder.defineMacro("__mips_isa_rev", "2"); 6303 else if (CPUStr == "mips32r3") 6304 Builder.defineMacro("__mips_isa_rev", "3"); 6305 else if (CPUStr == "mips32r5") 6306 Builder.defineMacro("__mips_isa_rev", "5"); 6307 else if (CPUStr == "mips32r6") 6308 Builder.defineMacro("__mips_isa_rev", "6"); 6309 6310 if (ABI == "o32") { 6311 Builder.defineMacro("__mips_o32"); 6312 Builder.defineMacro("_ABIO32", "1"); 6313 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6314 } 6315 else if (ABI == "eabi") 6316 Builder.defineMacro("__mips_eabi"); 6317 else 6318 llvm_unreachable("Invalid ABI for Mips32."); 6319 } 6320 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6321 unsigned &NumAliases) const override { 6322 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6323 { { "at" }, "$1" }, 6324 { { "v0" }, "$2" }, 6325 { { "v1" }, "$3" }, 6326 { { "a0" }, "$4" }, 6327 { { "a1" }, "$5" }, 6328 { { "a2" }, "$6" }, 6329 { { "a3" }, "$7" }, 6330 { { "t0" }, "$8" }, 6331 { { "t1" }, "$9" }, 6332 { { "t2" }, "$10" }, 6333 { { "t3" }, "$11" }, 6334 { { "t4" }, "$12" }, 6335 { { "t5" }, "$13" }, 6336 { { "t6" }, "$14" }, 6337 { { "t7" }, "$15" }, 6338 { { "s0" }, "$16" }, 6339 { { "s1" }, "$17" }, 6340 { { "s2" }, "$18" }, 6341 { { "s3" }, "$19" }, 6342 { { "s4" }, "$20" }, 6343 { { "s5" }, "$21" }, 6344 { { "s6" }, "$22" }, 6345 { { "s7" }, "$23" }, 6346 { { "t8" }, "$24" }, 6347 { { "t9" }, "$25" }, 6348 { { "k0" }, "$26" }, 6349 { { "k1" }, "$27" }, 6350 { { "gp" }, "$28" }, 6351 { { "sp","$sp" }, "$29" }, 6352 { { "fp","$fp" }, "$30" }, 6353 { { "ra" }, "$31" } 6354 }; 6355 Aliases = GCCRegAliases; 6356 NumAliases = llvm::array_lengthof(GCCRegAliases); 6357 } 6358 }; 6359 6360 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6361 void setDescriptionString() override { 6362 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6363 } 6364 6365 public: 6366 Mips32EBTargetInfo(const llvm::Triple &Triple) 6367 : Mips32TargetInfoBase(Triple) { 6368 } 6369 void getTargetDefines(const LangOptions &Opts, 6370 MacroBuilder &Builder) const override { 6371 DefineStd(Builder, "MIPSEB", Opts); 6372 Builder.defineMacro("_MIPSEB"); 6373 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6374 } 6375 }; 6376 6377 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6378 void setDescriptionString() override { 6379 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6380 } 6381 6382 public: 6383 Mips32ELTargetInfo(const llvm::Triple &Triple) 6384 : Mips32TargetInfoBase(Triple) { 6385 BigEndian = false; 6386 } 6387 void getTargetDefines(const LangOptions &Opts, 6388 MacroBuilder &Builder) const override { 6389 DefineStd(Builder, "MIPSEL", Opts); 6390 Builder.defineMacro("_MIPSEL"); 6391 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6392 } 6393 }; 6394 6395 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6396 public: 6397 Mips64TargetInfoBase(const llvm::Triple &Triple) 6398 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6399 LongDoubleWidth = LongDoubleAlign = 128; 6400 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6401 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6402 LongDoubleWidth = LongDoubleAlign = 64; 6403 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6404 } 6405 setN64ABITypes(); 6406 SuitableAlign = 128; 6407 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6408 } 6409 6410 void setN64ABITypes() { 6411 LongWidth = LongAlign = 64; 6412 PointerWidth = PointerAlign = 64; 6413 SizeType = UnsignedLong; 6414 PtrDiffType = SignedLong; 6415 Int64Type = SignedLong; 6416 IntMaxType = Int64Type; 6417 } 6418 6419 void setN32ABITypes() { 6420 LongWidth = LongAlign = 32; 6421 PointerWidth = PointerAlign = 32; 6422 SizeType = UnsignedInt; 6423 PtrDiffType = SignedInt; 6424 Int64Type = SignedLongLong; 6425 IntMaxType = Int64Type; 6426 } 6427 6428 bool setABI(const std::string &Name) override { 6429 if (Name == "n32") { 6430 setN32ABITypes(); 6431 ABI = Name; 6432 return true; 6433 } 6434 if (Name == "n64") { 6435 setN64ABITypes(); 6436 ABI = Name; 6437 return true; 6438 } 6439 return false; 6440 } 6441 6442 void getTargetDefines(const LangOptions &Opts, 6443 MacroBuilder &Builder) const override { 6444 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6445 6446 Builder.defineMacro("__mips", "64"); 6447 Builder.defineMacro("__mips64"); 6448 Builder.defineMacro("__mips64__"); 6449 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6450 6451 const std::string& CPUStr = getCPU(); 6452 if (CPUStr == "mips64") 6453 Builder.defineMacro("__mips_isa_rev", "1"); 6454 else if (CPUStr == "mips64r2") 6455 Builder.defineMacro("__mips_isa_rev", "2"); 6456 else if (CPUStr == "mips64r3") 6457 Builder.defineMacro("__mips_isa_rev", "3"); 6458 else if (CPUStr == "mips64r5") 6459 Builder.defineMacro("__mips_isa_rev", "5"); 6460 else if (CPUStr == "mips64r6") 6461 Builder.defineMacro("__mips_isa_rev", "6"); 6462 6463 if (ABI == "n32") { 6464 Builder.defineMacro("__mips_n32"); 6465 Builder.defineMacro("_ABIN32", "2"); 6466 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6467 } 6468 else if (ABI == "n64") { 6469 Builder.defineMacro("__mips_n64"); 6470 Builder.defineMacro("_ABI64", "3"); 6471 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6472 } 6473 else 6474 llvm_unreachable("Invalid ABI for Mips64."); 6475 } 6476 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6477 unsigned &NumAliases) const override { 6478 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6479 { { "at" }, "$1" }, 6480 { { "v0" }, "$2" }, 6481 { { "v1" }, "$3" }, 6482 { { "a0" }, "$4" }, 6483 { { "a1" }, "$5" }, 6484 { { "a2" }, "$6" }, 6485 { { "a3" }, "$7" }, 6486 { { "a4" }, "$8" }, 6487 { { "a5" }, "$9" }, 6488 { { "a6" }, "$10" }, 6489 { { "a7" }, "$11" }, 6490 { { "t0" }, "$12" }, 6491 { { "t1" }, "$13" }, 6492 { { "t2" }, "$14" }, 6493 { { "t3" }, "$15" }, 6494 { { "s0" }, "$16" }, 6495 { { "s1" }, "$17" }, 6496 { { "s2" }, "$18" }, 6497 { { "s3" }, "$19" }, 6498 { { "s4" }, "$20" }, 6499 { { "s5" }, "$21" }, 6500 { { "s6" }, "$22" }, 6501 { { "s7" }, "$23" }, 6502 { { "t8" }, "$24" }, 6503 { { "t9" }, "$25" }, 6504 { { "k0" }, "$26" }, 6505 { { "k1" }, "$27" }, 6506 { { "gp" }, "$28" }, 6507 { { "sp","$sp" }, "$29" }, 6508 { { "fp","$fp" }, "$30" }, 6509 { { "ra" }, "$31" } 6510 }; 6511 Aliases = GCCRegAliases; 6512 NumAliases = llvm::array_lengthof(GCCRegAliases); 6513 } 6514 6515 bool hasInt128Type() const override { return true; } 6516 }; 6517 6518 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6519 void setDescriptionString() override { 6520 if (ABI == "n32") 6521 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6522 else 6523 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6524 6525 } 6526 6527 public: 6528 Mips64EBTargetInfo(const llvm::Triple &Triple) 6529 : Mips64TargetInfoBase(Triple) {} 6530 void getTargetDefines(const LangOptions &Opts, 6531 MacroBuilder &Builder) const override { 6532 DefineStd(Builder, "MIPSEB", Opts); 6533 Builder.defineMacro("_MIPSEB"); 6534 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6535 } 6536 }; 6537 6538 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6539 void setDescriptionString() override { 6540 if (ABI == "n32") 6541 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6542 else 6543 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6544 } 6545 public: 6546 Mips64ELTargetInfo(const llvm::Triple &Triple) 6547 : Mips64TargetInfoBase(Triple) { 6548 // Default ABI is n64. 6549 BigEndian = false; 6550 } 6551 void getTargetDefines(const LangOptions &Opts, 6552 MacroBuilder &Builder) const override { 6553 DefineStd(Builder, "MIPSEL", Opts); 6554 Builder.defineMacro("_MIPSEL"); 6555 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6556 } 6557 }; 6558 6559 class PNaClTargetInfo : public TargetInfo { 6560 public: 6561 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6562 BigEndian = false; 6563 this->UserLabelPrefix = ""; 6564 this->LongAlign = 32; 6565 this->LongWidth = 32; 6566 this->PointerAlign = 32; 6567 this->PointerWidth = 32; 6568 this->IntMaxType = TargetInfo::SignedLongLong; 6569 this->Int64Type = TargetInfo::SignedLongLong; 6570 this->DoubleAlign = 64; 6571 this->LongDoubleWidth = 64; 6572 this->LongDoubleAlign = 64; 6573 this->SizeType = TargetInfo::UnsignedInt; 6574 this->PtrDiffType = TargetInfo::SignedInt; 6575 this->IntPtrType = TargetInfo::SignedInt; 6576 this->RegParmMax = 0; // Disallow regparm 6577 } 6578 6579 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6580 } 6581 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6582 Builder.defineMacro("__le32__"); 6583 Builder.defineMacro("__pnacl__"); 6584 } 6585 void getTargetDefines(const LangOptions &Opts, 6586 MacroBuilder &Builder) const override { 6587 getArchDefines(Opts, Builder); 6588 } 6589 bool hasFeature(StringRef Feature) const override { 6590 return Feature == "pnacl"; 6591 } 6592 void getTargetBuiltins(const Builtin::Info *&Records, 6593 unsigned &NumRecords) const override { 6594 } 6595 BuiltinVaListKind getBuiltinVaListKind() const override { 6596 return TargetInfo::PNaClABIBuiltinVaList; 6597 } 6598 void getGCCRegNames(const char * const *&Names, 6599 unsigned &NumNames) const override; 6600 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6601 unsigned &NumAliases) const override; 6602 bool validateAsmConstraint(const char *&Name, 6603 TargetInfo::ConstraintInfo &Info) const override { 6604 return false; 6605 } 6606 6607 const char *getClobbers() const override { 6608 return ""; 6609 } 6610 }; 6611 6612 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6613 unsigned &NumNames) const { 6614 Names = nullptr; 6615 NumNames = 0; 6616 } 6617 6618 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6619 unsigned &NumAliases) const { 6620 Aliases = nullptr; 6621 NumAliases = 0; 6622 } 6623 6624 class Le64TargetInfo : public TargetInfo { 6625 static const Builtin::Info BuiltinInfo[]; 6626 6627 public: 6628 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6629 BigEndian = false; 6630 NoAsmVariants = true; 6631 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6632 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6633 DescriptionString = 6634 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6635 } 6636 6637 void getTargetDefines(const LangOptions &Opts, 6638 MacroBuilder &Builder) const override { 6639 DefineStd(Builder, "unix", Opts); 6640 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6641 Builder.defineMacro("__ELF__"); 6642 } 6643 void getTargetBuiltins(const Builtin::Info *&Records, 6644 unsigned &NumRecords) const override { 6645 Records = BuiltinInfo; 6646 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6647 } 6648 BuiltinVaListKind getBuiltinVaListKind() const override { 6649 return TargetInfo::PNaClABIBuiltinVaList; 6650 } 6651 const char *getClobbers() const override { return ""; } 6652 void getGCCRegNames(const char *const *&Names, 6653 unsigned &NumNames) const override { 6654 Names = nullptr; 6655 NumNames = 0; 6656 } 6657 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6658 unsigned &NumAliases) const override { 6659 Aliases = nullptr; 6660 NumAliases = 0; 6661 } 6662 bool validateAsmConstraint(const char *&Name, 6663 TargetInfo::ConstraintInfo &Info) const override { 6664 return false; 6665 } 6666 6667 bool hasProtectedVisibility() const override { return false; } 6668 }; 6669 } // end anonymous namespace. 6670 6671 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 6672 #define BUILTIN(ID, TYPE, ATTRS) \ 6673 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6674 #include "clang/Basic/BuiltinsLe64.def" 6675 }; 6676 6677 namespace { 6678 static const unsigned SPIRAddrSpaceMap[] = { 6679 1, // opencl_global 6680 3, // opencl_local 6681 2, // opencl_constant 6682 4, // opencl_generic 6683 0, // cuda_device 6684 0, // cuda_constant 6685 0 // cuda_shared 6686 }; 6687 class SPIRTargetInfo : public TargetInfo { 6688 public: 6689 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6690 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 6691 "SPIR target must use unknown OS"); 6692 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 6693 "SPIR target must use unknown environment type"); 6694 BigEndian = false; 6695 TLSSupported = false; 6696 LongWidth = LongAlign = 64; 6697 AddrSpaceMap = &SPIRAddrSpaceMap; 6698 UseAddrSpaceMapMangling = true; 6699 // Define available target features 6700 // These must be defined in sorted order! 6701 NoAsmVariants = true; 6702 } 6703 void getTargetDefines(const LangOptions &Opts, 6704 MacroBuilder &Builder) const override { 6705 DefineStd(Builder, "SPIR", Opts); 6706 } 6707 bool hasFeature(StringRef Feature) const override { 6708 return Feature == "spir"; 6709 } 6710 6711 void getTargetBuiltins(const Builtin::Info *&Records, 6712 unsigned &NumRecords) const override {} 6713 const char *getClobbers() const override { 6714 return ""; 6715 } 6716 void getGCCRegNames(const char * const *&Names, 6717 unsigned &NumNames) const override {} 6718 bool 6719 validateAsmConstraint(const char *&Name, 6720 TargetInfo::ConstraintInfo &info) const override { 6721 return true; 6722 } 6723 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6724 unsigned &NumAliases) const override {} 6725 BuiltinVaListKind getBuiltinVaListKind() const override { 6726 return TargetInfo::VoidPtrBuiltinVaList; 6727 } 6728 6729 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6730 return (CC == CC_SpirFunction || 6731 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning; 6732 } 6733 6734 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 6735 return CC_SpirFunction; 6736 } 6737 }; 6738 6739 6740 class SPIR32TargetInfo : public SPIRTargetInfo { 6741 public: 6742 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6743 PointerWidth = PointerAlign = 32; 6744 SizeType = TargetInfo::UnsignedInt; 6745 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6746 DescriptionString 6747 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6748 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6749 } 6750 void getTargetDefines(const LangOptions &Opts, 6751 MacroBuilder &Builder) const override { 6752 DefineStd(Builder, "SPIR32", Opts); 6753 } 6754 }; 6755 6756 class SPIR64TargetInfo : public SPIRTargetInfo { 6757 public: 6758 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6759 PointerWidth = PointerAlign = 64; 6760 SizeType = TargetInfo::UnsignedLong; 6761 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6762 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6763 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6764 } 6765 void getTargetDefines(const LangOptions &Opts, 6766 MacroBuilder &Builder) const override { 6767 DefineStd(Builder, "SPIR64", Opts); 6768 } 6769 }; 6770 6771 class XCoreTargetInfo : public TargetInfo { 6772 static const Builtin::Info BuiltinInfo[]; 6773 public: 6774 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6775 BigEndian = false; 6776 NoAsmVariants = true; 6777 LongLongAlign = 32; 6778 SuitableAlign = 32; 6779 DoubleAlign = LongDoubleAlign = 32; 6780 SizeType = UnsignedInt; 6781 PtrDiffType = SignedInt; 6782 IntPtrType = SignedInt; 6783 WCharType = UnsignedChar; 6784 WIntType = UnsignedInt; 6785 UseZeroLengthBitfieldAlignment = true; 6786 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6787 "-f64:32-a:0:32-n32"; 6788 } 6789 void getTargetDefines(const LangOptions &Opts, 6790 MacroBuilder &Builder) const override { 6791 Builder.defineMacro("__XS1B__"); 6792 } 6793 void getTargetBuiltins(const Builtin::Info *&Records, 6794 unsigned &NumRecords) const override { 6795 Records = BuiltinInfo; 6796 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6797 } 6798 BuiltinVaListKind getBuiltinVaListKind() const override { 6799 return TargetInfo::VoidPtrBuiltinVaList; 6800 } 6801 const char *getClobbers() const override { 6802 return ""; 6803 } 6804 void getGCCRegNames(const char * const *&Names, 6805 unsigned &NumNames) const override { 6806 static const char * const GCCRegNames[] = { 6807 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6808 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6809 }; 6810 Names = GCCRegNames; 6811 NumNames = llvm::array_lengthof(GCCRegNames); 6812 } 6813 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6814 unsigned &NumAliases) const override { 6815 Aliases = nullptr; 6816 NumAliases = 0; 6817 } 6818 bool validateAsmConstraint(const char *&Name, 6819 TargetInfo::ConstraintInfo &Info) const override { 6820 return false; 6821 } 6822 int getEHDataRegisterNumber(unsigned RegNo) const override { 6823 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6824 return (RegNo < 2)? RegNo : -1; 6825 } 6826 }; 6827 6828 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6829 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6830 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6831 ALL_LANGUAGES }, 6832 #include "clang/Basic/BuiltinsXCore.def" 6833 }; 6834 } // end anonymous namespace. 6835 6836 namespace { 6837 // x86_32 Android target 6838 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 6839 public: 6840 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 6841 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 6842 SuitableAlign = 32; 6843 LongDoubleWidth = 64; 6844 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6845 } 6846 }; 6847 } // end anonymous namespace 6848 6849 namespace { 6850 // x86_64 Android target 6851 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 6852 public: 6853 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 6854 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 6855 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6856 } 6857 }; 6858 } // end anonymous namespace 6859 6860 6861 //===----------------------------------------------------------------------===// 6862 // Driver code 6863 //===----------------------------------------------------------------------===// 6864 6865 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 6866 llvm::Triple::OSType os = Triple.getOS(); 6867 6868 switch (Triple.getArch()) { 6869 default: 6870 return nullptr; 6871 6872 case llvm::Triple::xcore: 6873 return new XCoreTargetInfo(Triple); 6874 6875 case llvm::Triple::hexagon: 6876 return new HexagonTargetInfo(Triple); 6877 6878 case llvm::Triple::aarch64: 6879 if (Triple.isOSDarwin()) 6880 return new DarwinAArch64TargetInfo(Triple); 6881 6882 switch (os) { 6883 case llvm::Triple::FreeBSD: 6884 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 6885 case llvm::Triple::Linux: 6886 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6887 case llvm::Triple::NetBSD: 6888 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6889 default: 6890 return new AArch64leTargetInfo(Triple); 6891 } 6892 6893 case llvm::Triple::aarch64_be: 6894 switch (os) { 6895 case llvm::Triple::FreeBSD: 6896 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 6897 case llvm::Triple::Linux: 6898 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6899 case llvm::Triple::NetBSD: 6900 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6901 default: 6902 return new AArch64beTargetInfo(Triple); 6903 } 6904 6905 case llvm::Triple::arm: 6906 case llvm::Triple::thumb: 6907 if (Triple.isOSBinFormatMachO()) 6908 return new DarwinARMTargetInfo(Triple); 6909 6910 switch (os) { 6911 case llvm::Triple::Linux: 6912 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6913 case llvm::Triple::FreeBSD: 6914 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6915 case llvm::Triple::NetBSD: 6916 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6917 case llvm::Triple::OpenBSD: 6918 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6919 case llvm::Triple::Bitrig: 6920 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6921 case llvm::Triple::RTEMS: 6922 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6923 case llvm::Triple::NaCl: 6924 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6925 case llvm::Triple::Win32: 6926 switch (Triple.getEnvironment()) { 6927 default: 6928 return new ARMleTargetInfo(Triple); 6929 case llvm::Triple::Itanium: 6930 return new ItaniumWindowsARMleTargetInfo(Triple); 6931 case llvm::Triple::MSVC: 6932 return new MicrosoftARMleTargetInfo(Triple); 6933 } 6934 default: 6935 return new ARMleTargetInfo(Triple); 6936 } 6937 6938 case llvm::Triple::armeb: 6939 case llvm::Triple::thumbeb: 6940 if (Triple.isOSDarwin()) 6941 return new DarwinARMTargetInfo(Triple); 6942 6943 switch (os) { 6944 case llvm::Triple::Linux: 6945 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 6946 case llvm::Triple::FreeBSD: 6947 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 6948 case llvm::Triple::NetBSD: 6949 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 6950 case llvm::Triple::OpenBSD: 6951 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 6952 case llvm::Triple::Bitrig: 6953 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 6954 case llvm::Triple::RTEMS: 6955 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 6956 case llvm::Triple::NaCl: 6957 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 6958 default: 6959 return new ARMbeTargetInfo(Triple); 6960 } 6961 6962 case llvm::Triple::bpfeb: 6963 case llvm::Triple::bpfel: 6964 return new BPFTargetInfo(Triple); 6965 6966 case llvm::Triple::msp430: 6967 return new MSP430TargetInfo(Triple); 6968 6969 case llvm::Triple::mips: 6970 switch (os) { 6971 case llvm::Triple::Linux: 6972 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 6973 case llvm::Triple::RTEMS: 6974 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 6975 case llvm::Triple::FreeBSD: 6976 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6977 case llvm::Triple::NetBSD: 6978 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6979 default: 6980 return new Mips32EBTargetInfo(Triple); 6981 } 6982 6983 case llvm::Triple::mipsel: 6984 switch (os) { 6985 case llvm::Triple::Linux: 6986 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 6987 case llvm::Triple::RTEMS: 6988 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 6989 case llvm::Triple::FreeBSD: 6990 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6991 case llvm::Triple::NetBSD: 6992 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6993 case llvm::Triple::NaCl: 6994 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 6995 default: 6996 return new Mips32ELTargetInfo(Triple); 6997 } 6998 6999 case llvm::Triple::mips64: 7000 switch (os) { 7001 case llvm::Triple::Linux: 7002 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7003 case llvm::Triple::RTEMS: 7004 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7005 case llvm::Triple::FreeBSD: 7006 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7007 case llvm::Triple::NetBSD: 7008 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7009 case llvm::Triple::OpenBSD: 7010 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7011 default: 7012 return new Mips64EBTargetInfo(Triple); 7013 } 7014 7015 case llvm::Triple::mips64el: 7016 switch (os) { 7017 case llvm::Triple::Linux: 7018 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7019 case llvm::Triple::RTEMS: 7020 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7021 case llvm::Triple::FreeBSD: 7022 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7023 case llvm::Triple::NetBSD: 7024 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7025 case llvm::Triple::OpenBSD: 7026 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7027 default: 7028 return new Mips64ELTargetInfo(Triple); 7029 } 7030 7031 case llvm::Triple::le32: 7032 switch (os) { 7033 case llvm::Triple::NaCl: 7034 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7035 default: 7036 return nullptr; 7037 } 7038 7039 case llvm::Triple::le64: 7040 return new Le64TargetInfo(Triple); 7041 7042 case llvm::Triple::ppc: 7043 if (Triple.isOSDarwin()) 7044 return new DarwinPPC32TargetInfo(Triple); 7045 switch (os) { 7046 case llvm::Triple::Linux: 7047 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7048 case llvm::Triple::FreeBSD: 7049 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7050 case llvm::Triple::NetBSD: 7051 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7052 case llvm::Triple::OpenBSD: 7053 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7054 case llvm::Triple::RTEMS: 7055 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7056 default: 7057 return new PPC32TargetInfo(Triple); 7058 } 7059 7060 case llvm::Triple::ppc64: 7061 if (Triple.isOSDarwin()) 7062 return new DarwinPPC64TargetInfo(Triple); 7063 switch (os) { 7064 case llvm::Triple::Linux: 7065 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7066 case llvm::Triple::Lv2: 7067 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7068 case llvm::Triple::FreeBSD: 7069 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7070 case llvm::Triple::NetBSD: 7071 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7072 default: 7073 return new PPC64TargetInfo(Triple); 7074 } 7075 7076 case llvm::Triple::ppc64le: 7077 switch (os) { 7078 case llvm::Triple::Linux: 7079 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7080 case llvm::Triple::NetBSD: 7081 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7082 default: 7083 return new PPC64TargetInfo(Triple); 7084 } 7085 7086 case llvm::Triple::nvptx: 7087 return new NVPTX32TargetInfo(Triple); 7088 case llvm::Triple::nvptx64: 7089 return new NVPTX64TargetInfo(Triple); 7090 7091 case llvm::Triple::amdgcn: 7092 case llvm::Triple::r600: 7093 return new AMDGPUTargetInfo(Triple); 7094 7095 case llvm::Triple::sparc: 7096 switch (os) { 7097 case llvm::Triple::Linux: 7098 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7099 case llvm::Triple::Solaris: 7100 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7101 case llvm::Triple::NetBSD: 7102 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7103 case llvm::Triple::OpenBSD: 7104 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7105 case llvm::Triple::RTEMS: 7106 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7107 default: 7108 return new SparcV8TargetInfo(Triple); 7109 } 7110 7111 // The 'sparcel' architecture copies all the above cases except for Solaris. 7112 case llvm::Triple::sparcel: 7113 switch (os) { 7114 case llvm::Triple::Linux: 7115 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7116 case llvm::Triple::NetBSD: 7117 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7118 case llvm::Triple::OpenBSD: 7119 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7120 case llvm::Triple::RTEMS: 7121 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7122 default: 7123 return new SparcV8elTargetInfo(Triple); 7124 } 7125 7126 case llvm::Triple::sparcv9: 7127 switch (os) { 7128 case llvm::Triple::Linux: 7129 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7130 case llvm::Triple::Solaris: 7131 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7132 case llvm::Triple::NetBSD: 7133 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7134 case llvm::Triple::OpenBSD: 7135 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7136 case llvm::Triple::FreeBSD: 7137 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7138 default: 7139 return new SparcV9TargetInfo(Triple); 7140 } 7141 7142 case llvm::Triple::systemz: 7143 switch (os) { 7144 case llvm::Triple::Linux: 7145 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7146 default: 7147 return new SystemZTargetInfo(Triple); 7148 } 7149 7150 case llvm::Triple::tce: 7151 return new TCETargetInfo(Triple); 7152 7153 case llvm::Triple::x86: 7154 if (Triple.isOSDarwin()) 7155 return new DarwinI386TargetInfo(Triple); 7156 7157 switch (os) { 7158 case llvm::Triple::CloudABI: 7159 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7160 case llvm::Triple::Linux: { 7161 switch (Triple.getEnvironment()) { 7162 default: 7163 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7164 case llvm::Triple::Android: 7165 return new AndroidX86_32TargetInfo(Triple); 7166 } 7167 } 7168 case llvm::Triple::DragonFly: 7169 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7170 case llvm::Triple::NetBSD: 7171 return new NetBSDI386TargetInfo(Triple); 7172 case llvm::Triple::OpenBSD: 7173 return new OpenBSDI386TargetInfo(Triple); 7174 case llvm::Triple::Bitrig: 7175 return new BitrigI386TargetInfo(Triple); 7176 case llvm::Triple::FreeBSD: 7177 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7178 case llvm::Triple::KFreeBSD: 7179 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7180 case llvm::Triple::Minix: 7181 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7182 case llvm::Triple::Solaris: 7183 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7184 case llvm::Triple::Win32: { 7185 switch (Triple.getEnvironment()) { 7186 default: 7187 return new X86_32TargetInfo(Triple); 7188 case llvm::Triple::Cygnus: 7189 return new CygwinX86_32TargetInfo(Triple); 7190 case llvm::Triple::GNU: 7191 return new MinGWX86_32TargetInfo(Triple); 7192 case llvm::Triple::Itanium: 7193 case llvm::Triple::MSVC: 7194 return new MicrosoftX86_32TargetInfo(Triple); 7195 } 7196 } 7197 case llvm::Triple::Haiku: 7198 return new HaikuX86_32TargetInfo(Triple); 7199 case llvm::Triple::RTEMS: 7200 return new RTEMSX86_32TargetInfo(Triple); 7201 case llvm::Triple::NaCl: 7202 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7203 default: 7204 return new X86_32TargetInfo(Triple); 7205 } 7206 7207 case llvm::Triple::x86_64: 7208 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7209 return new DarwinX86_64TargetInfo(Triple); 7210 7211 switch (os) { 7212 case llvm::Triple::CloudABI: 7213 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7214 case llvm::Triple::Linux: { 7215 switch (Triple.getEnvironment()) { 7216 default: 7217 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7218 case llvm::Triple::Android: 7219 return new AndroidX86_64TargetInfo(Triple); 7220 } 7221 } 7222 case llvm::Triple::DragonFly: 7223 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7224 case llvm::Triple::NetBSD: 7225 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7226 case llvm::Triple::OpenBSD: 7227 return new OpenBSDX86_64TargetInfo(Triple); 7228 case llvm::Triple::Bitrig: 7229 return new BitrigX86_64TargetInfo(Triple); 7230 case llvm::Triple::FreeBSD: 7231 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7232 case llvm::Triple::KFreeBSD: 7233 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7234 case llvm::Triple::Solaris: 7235 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7236 case llvm::Triple::Win32: { 7237 switch (Triple.getEnvironment()) { 7238 default: 7239 return new X86_64TargetInfo(Triple); 7240 case llvm::Triple::GNU: 7241 return new MinGWX86_64TargetInfo(Triple); 7242 case llvm::Triple::MSVC: 7243 return new MicrosoftX86_64TargetInfo(Triple); 7244 } 7245 } 7246 case llvm::Triple::NaCl: 7247 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7248 case llvm::Triple::PS4: 7249 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7250 default: 7251 return new X86_64TargetInfo(Triple); 7252 } 7253 7254 case llvm::Triple::spir: { 7255 if (Triple.getOS() != llvm::Triple::UnknownOS || 7256 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7257 return nullptr; 7258 return new SPIR32TargetInfo(Triple); 7259 } 7260 case llvm::Triple::spir64: { 7261 if (Triple.getOS() != llvm::Triple::UnknownOS || 7262 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7263 return nullptr; 7264 return new SPIR64TargetInfo(Triple); 7265 } 7266 } 7267 } 7268 7269 /// CreateTargetInfo - Return the target info object for the specified target 7270 /// triple. 7271 TargetInfo * 7272 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7273 const std::shared_ptr<TargetOptions> &Opts) { 7274 llvm::Triple Triple(Opts->Triple); 7275 7276 // Construct the target 7277 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7278 if (!Target) { 7279 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7280 return nullptr; 7281 } 7282 Target->TargetOpts = Opts; 7283 7284 // Set the target CPU if specified. 7285 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7286 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7287 return nullptr; 7288 } 7289 7290 // Set the target ABI if specified. 7291 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7292 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7293 return nullptr; 7294 } 7295 7296 // Set the fp math unit. 7297 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7298 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7299 return nullptr; 7300 } 7301 7302 // Compute the default target features, we need the target to handle this 7303 // because features may have dependencies on one another. 7304 llvm::StringMap<bool> Features; 7305 Target->getDefaultFeatures(Features); 7306 7307 // Apply the user specified deltas. 7308 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 7309 I < N; ++I) { 7310 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 7311 // Apply the feature via the target. 7312 bool Enabled = Name[0] == '+'; 7313 Target->setFeatureEnabled(Features, Name + 1, Enabled); 7314 } 7315 7316 // Add the features to the compile options. 7317 // 7318 // FIXME: If we are completely confident that we have the right set, we only 7319 // need to pass the minuses. 7320 Opts->Features.clear(); 7321 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 7322 ie = Features.end(); it != ie; ++it) 7323 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 7324 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7325 return nullptr; 7326 7327 return Target.release(); 7328 } 7329