1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 //===----------------------------------------------------------------------===// 69 // Defines specific to certain operating systems. 70 //===----------------------------------------------------------------------===// 71 72 namespace { 73 template<typename TgtInfo> 74 class OSTargetInfo : public TgtInfo { 75 protected: 76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 77 MacroBuilder &Builder) const=0; 78 public: 79 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 80 void getTargetDefines(const LangOptions &Opts, 81 MacroBuilder &Builder) const override { 82 TgtInfo::getTargetDefines(Opts, Builder); 83 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 84 } 85 86 }; 87 88 // CloudABI Target 89 template <typename Target> 90 class CloudABITargetInfo : public OSTargetInfo<Target> { 91 protected: 92 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 93 MacroBuilder &Builder) const override { 94 Builder.defineMacro("__CloudABI__"); 95 Builder.defineMacro("__ELF__"); 96 97 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 98 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 99 Builder.defineMacro("__STDC_UTF_16__"); 100 Builder.defineMacro("__STDC_UTF_32__"); 101 } 102 103 public: 104 CloudABITargetInfo(const llvm::Triple &Triple) 105 : OSTargetInfo<Target>(Triple) {} 106 }; 107 108 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 109 const llvm::Triple &Triple, 110 StringRef &PlatformName, 111 VersionTuple &PlatformMinVersion) { 112 Builder.defineMacro("__APPLE_CC__", "6000"); 113 Builder.defineMacro("__APPLE__"); 114 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 115 // AddressSanitizer doesn't play well with source fortification, which is on 116 // by default on Darwin. 117 if (Opts.Sanitize.has(SanitizerKind::Address)) 118 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 119 120 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 121 if (!Opts.ObjC1) { 122 // __weak is always defined, for use in blocks and with objc pointers. 123 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 124 Builder.defineMacro("__strong", ""); 125 Builder.defineMacro("__unsafe_unretained", ""); 126 } 127 128 if (Opts.Static) 129 Builder.defineMacro("__STATIC__"); 130 else 131 Builder.defineMacro("__DYNAMIC__"); 132 133 if (Opts.POSIXThreads) 134 Builder.defineMacro("_REENTRANT"); 135 136 // Get the platform type and version number from the triple. 137 unsigned Maj, Min, Rev; 138 if (Triple.isMacOSX()) { 139 Triple.getMacOSXVersion(Maj, Min, Rev); 140 PlatformName = "macosx"; 141 } else { 142 Triple.getOSVersion(Maj, Min, Rev); 143 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 144 } 145 146 // If -target arch-pc-win32-macho option specified, we're 147 // generating code for Win32 ABI. No need to emit 148 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 149 if (PlatformName == "win32") { 150 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 151 return; 152 } 153 154 // Set the appropriate OS version define. 155 if (Triple.isiOS()) { 156 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 157 char Str[6]; 158 Str[0] = '0' + Maj; 159 Str[1] = '0' + (Min / 10); 160 Str[2] = '0' + (Min % 10); 161 Str[3] = '0' + (Rev / 10); 162 Str[4] = '0' + (Rev % 10); 163 Str[5] = '\0'; 164 if (Triple.isTvOS()) 165 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 166 else 167 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 168 Str); 169 170 } else if (Triple.isWatchOS()) { 171 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 172 char Str[6]; 173 Str[0] = '0' + Maj; 174 Str[1] = '0' + (Min / 10); 175 Str[2] = '0' + (Min % 10); 176 Str[3] = '0' + (Rev / 10); 177 Str[4] = '0' + (Rev % 10); 178 Str[5] = '\0'; 179 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 180 } else if (Triple.isMacOSX()) { 181 // Note that the Driver allows versions which aren't representable in the 182 // define (because we only get a single digit for the minor and micro 183 // revision numbers). So, we limit them to the maximum representable 184 // version. 185 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 186 char Str[7]; 187 if (Maj < 10 || (Maj == 10 && Min < 10)) { 188 Str[0] = '0' + (Maj / 10); 189 Str[1] = '0' + (Maj % 10); 190 Str[2] = '0' + std::min(Min, 9U); 191 Str[3] = '0' + std::min(Rev, 9U); 192 Str[4] = '\0'; 193 } else { 194 // Handle versions > 10.9. 195 Str[0] = '0' + (Maj / 10); 196 Str[1] = '0' + (Maj % 10); 197 Str[2] = '0' + (Min / 10); 198 Str[3] = '0' + (Min % 10); 199 Str[4] = '0' + (Rev / 10); 200 Str[5] = '0' + (Rev % 10); 201 Str[6] = '\0'; 202 } 203 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 204 } 205 206 // Tell users about the kernel if there is one. 207 if (Triple.isOSDarwin()) 208 Builder.defineMacro("__MACH__"); 209 210 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 211 } 212 213 template<typename Target> 214 class DarwinTargetInfo : public OSTargetInfo<Target> { 215 protected: 216 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 217 MacroBuilder &Builder) const override { 218 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 219 this->PlatformMinVersion); 220 } 221 222 public: 223 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 224 // By default, no TLS, and we whitelist permitted architecture/OS 225 // combinations. 226 this->TLSSupported = false; 227 228 if (Triple.isMacOSX()) 229 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 230 else if (Triple.isiOS()) { 231 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 232 if (Triple.getArch() == llvm::Triple::x86_64 || 233 Triple.getArch() == llvm::Triple::aarch64) 234 this->TLSSupported = !Triple.isOSVersionLT(8); 235 else if (Triple.getArch() == llvm::Triple::x86 || 236 Triple.getArch() == llvm::Triple::arm || 237 Triple.getArch() == llvm::Triple::thumb) 238 this->TLSSupported = !Triple.isOSVersionLT(9); 239 } else if (Triple.isWatchOS()) 240 this->TLSSupported = !Triple.isOSVersionLT(2); 241 242 this->MCountName = "\01mcount"; 243 this->UserLabelPrefix = "_"; 244 } 245 246 std::string isValidSectionSpecifier(StringRef SR) const override { 247 // Let MCSectionMachO validate this. 248 StringRef Segment, Section; 249 unsigned TAA, StubSize; 250 bool HasTAA; 251 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 252 TAA, HasTAA, StubSize); 253 } 254 255 const char *getStaticInitSectionSpecifier() const override { 256 // FIXME: We should return 0 when building kexts. 257 return "__TEXT,__StaticInit,regular,pure_instructions"; 258 } 259 260 /// Darwin does not support protected visibility. Darwin's "default" 261 /// is very similar to ELF's "protected"; Darwin requires a "weak" 262 /// attribute on declarations that can be dynamically replaced. 263 bool hasProtectedVisibility() const override { 264 return false; 265 } 266 }; 267 268 269 // DragonFlyBSD Target 270 template<typename Target> 271 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 272 protected: 273 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 274 MacroBuilder &Builder) const override { 275 // DragonFly defines; list based off of gcc output 276 Builder.defineMacro("__DragonFly__"); 277 Builder.defineMacro("__DragonFly_cc_version", "100001"); 278 Builder.defineMacro("__ELF__"); 279 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 280 Builder.defineMacro("__tune_i386__"); 281 DefineStd(Builder, "unix", Opts); 282 } 283 public: 284 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 285 : OSTargetInfo<Target>(Triple) { 286 switch (Triple.getArch()) { 287 default: 288 case llvm::Triple::x86: 289 case llvm::Triple::x86_64: 290 this->MCountName = ".mcount"; 291 break; 292 } 293 } 294 }; 295 296 // FreeBSD Target 297 template<typename Target> 298 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 299 protected: 300 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 301 MacroBuilder &Builder) const override { 302 // FreeBSD defines; list based off of gcc output 303 304 unsigned Release = Triple.getOSMajorVersion(); 305 if (Release == 0U) 306 Release = 8; 307 308 Builder.defineMacro("__FreeBSD__", Twine(Release)); 309 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 310 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 311 DefineStd(Builder, "unix", Opts); 312 Builder.defineMacro("__ELF__"); 313 314 // On FreeBSD, wchar_t contains the number of the code point as 315 // used by the character set of the locale. These character sets are 316 // not necessarily a superset of ASCII. 317 // 318 // FIXME: This is wrong; the macro refers to the numerical values 319 // of wchar_t *literals*, which are not locale-dependent. However, 320 // FreeBSD systems apparently depend on us getting this wrong, and 321 // setting this to 1 is conforming even if all the basic source 322 // character literals have the same encoding as char and wchar_t. 323 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 324 } 325 public: 326 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 327 switch (Triple.getArch()) { 328 default: 329 case llvm::Triple::x86: 330 case llvm::Triple::x86_64: 331 this->MCountName = ".mcount"; 332 break; 333 case llvm::Triple::mips: 334 case llvm::Triple::mipsel: 335 case llvm::Triple::ppc: 336 case llvm::Triple::ppc64: 337 case llvm::Triple::ppc64le: 338 this->MCountName = "_mcount"; 339 break; 340 case llvm::Triple::arm: 341 this->MCountName = "__mcount"; 342 break; 343 } 344 } 345 }; 346 347 // GNU/kFreeBSD Target 348 template<typename Target> 349 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 350 protected: 351 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 352 MacroBuilder &Builder) const override { 353 // GNU/kFreeBSD defines; list based off of gcc output 354 355 DefineStd(Builder, "unix", Opts); 356 Builder.defineMacro("__FreeBSD_kernel__"); 357 Builder.defineMacro("__GLIBC__"); 358 Builder.defineMacro("__ELF__"); 359 if (Opts.POSIXThreads) 360 Builder.defineMacro("_REENTRANT"); 361 if (Opts.CPlusPlus) 362 Builder.defineMacro("_GNU_SOURCE"); 363 } 364 public: 365 KFreeBSDTargetInfo(const llvm::Triple &Triple) 366 : OSTargetInfo<Target>(Triple) {} 367 }; 368 369 // Minix Target 370 template<typename Target> 371 class MinixTargetInfo : public OSTargetInfo<Target> { 372 protected: 373 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 374 MacroBuilder &Builder) const override { 375 // Minix defines 376 377 Builder.defineMacro("__minix", "3"); 378 Builder.defineMacro("_EM_WSIZE", "4"); 379 Builder.defineMacro("_EM_PSIZE", "4"); 380 Builder.defineMacro("_EM_SSIZE", "2"); 381 Builder.defineMacro("_EM_LSIZE", "4"); 382 Builder.defineMacro("_EM_FSIZE", "4"); 383 Builder.defineMacro("_EM_DSIZE", "8"); 384 Builder.defineMacro("__ELF__"); 385 DefineStd(Builder, "unix", Opts); 386 } 387 public: 388 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 389 }; 390 391 // Linux target 392 template<typename Target> 393 class LinuxTargetInfo : public OSTargetInfo<Target> { 394 protected: 395 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 396 MacroBuilder &Builder) const override { 397 // Linux defines; list based off of gcc output 398 DefineStd(Builder, "unix", Opts); 399 DefineStd(Builder, "linux", Opts); 400 Builder.defineMacro("__gnu_linux__"); 401 Builder.defineMacro("__ELF__"); 402 if (Triple.isAndroid()) { 403 Builder.defineMacro("__ANDROID__", "1"); 404 unsigned Maj, Min, Rev; 405 Triple.getEnvironmentVersion(Maj, Min, Rev); 406 this->PlatformName = "android"; 407 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 408 } 409 if (Opts.POSIXThreads) 410 Builder.defineMacro("_REENTRANT"); 411 if (Opts.CPlusPlus) 412 Builder.defineMacro("_GNU_SOURCE"); 413 } 414 public: 415 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 416 this->UserLabelPrefix = ""; 417 this->WIntType = TargetInfo::UnsignedInt; 418 419 switch (Triple.getArch()) { 420 default: 421 break; 422 case llvm::Triple::ppc: 423 case llvm::Triple::ppc64: 424 case llvm::Triple::ppc64le: 425 this->MCountName = "_mcount"; 426 break; 427 } 428 } 429 430 const char *getStaticInitSectionSpecifier() const override { 431 return ".text.startup"; 432 } 433 }; 434 435 // NetBSD Target 436 template<typename Target> 437 class NetBSDTargetInfo : public OSTargetInfo<Target> { 438 protected: 439 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 440 MacroBuilder &Builder) const override { 441 // NetBSD defines; list based off of gcc output 442 Builder.defineMacro("__NetBSD__"); 443 Builder.defineMacro("__unix__"); 444 Builder.defineMacro("__ELF__"); 445 if (Opts.POSIXThreads) 446 Builder.defineMacro("_POSIX_THREADS"); 447 448 switch (Triple.getArch()) { 449 default: 450 break; 451 case llvm::Triple::arm: 452 case llvm::Triple::armeb: 453 case llvm::Triple::thumb: 454 case llvm::Triple::thumbeb: 455 Builder.defineMacro("__ARM_DWARF_EH__"); 456 break; 457 } 458 } 459 public: 460 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 461 this->MCountName = "_mcount"; 462 } 463 }; 464 465 // OpenBSD Target 466 template<typename Target> 467 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 468 protected: 469 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 470 MacroBuilder &Builder) const override { 471 // OpenBSD defines; list based off of gcc output 472 473 Builder.defineMacro("__OpenBSD__"); 474 DefineStd(Builder, "unix", Opts); 475 Builder.defineMacro("__ELF__"); 476 if (Opts.POSIXThreads) 477 Builder.defineMacro("_REENTRANT"); 478 } 479 public: 480 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 481 this->TLSSupported = false; 482 483 switch (Triple.getArch()) { 484 default: 485 case llvm::Triple::x86: 486 case llvm::Triple::x86_64: 487 case llvm::Triple::arm: 488 case llvm::Triple::sparc: 489 this->MCountName = "__mcount"; 490 break; 491 case llvm::Triple::mips64: 492 case llvm::Triple::mips64el: 493 case llvm::Triple::ppc: 494 case llvm::Triple::sparcv9: 495 this->MCountName = "_mcount"; 496 break; 497 } 498 } 499 }; 500 501 // Bitrig Target 502 template<typename Target> 503 class BitrigTargetInfo : public OSTargetInfo<Target> { 504 protected: 505 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 506 MacroBuilder &Builder) const override { 507 // Bitrig defines; list based off of gcc output 508 509 Builder.defineMacro("__Bitrig__"); 510 DefineStd(Builder, "unix", Opts); 511 Builder.defineMacro("__ELF__"); 512 if (Opts.POSIXThreads) 513 Builder.defineMacro("_REENTRANT"); 514 515 switch (Triple.getArch()) { 516 default: 517 break; 518 case llvm::Triple::arm: 519 case llvm::Triple::armeb: 520 case llvm::Triple::thumb: 521 case llvm::Triple::thumbeb: 522 Builder.defineMacro("__ARM_DWARF_EH__"); 523 break; 524 } 525 } 526 public: 527 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 528 this->MCountName = "__mcount"; 529 } 530 }; 531 532 // PSP Target 533 template<typename Target> 534 class PSPTargetInfo : public OSTargetInfo<Target> { 535 protected: 536 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 537 MacroBuilder &Builder) const override { 538 // PSP defines; list based on the output of the pspdev gcc toolchain. 539 Builder.defineMacro("PSP"); 540 Builder.defineMacro("_PSP"); 541 Builder.defineMacro("__psp__"); 542 Builder.defineMacro("__ELF__"); 543 } 544 public: 545 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 546 }; 547 548 // PS3 PPU Target 549 template<typename Target> 550 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 551 protected: 552 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 553 MacroBuilder &Builder) const override { 554 // PS3 PPU defines. 555 Builder.defineMacro("__PPC__"); 556 Builder.defineMacro("__PPU__"); 557 Builder.defineMacro("__CELLOS_LV2__"); 558 Builder.defineMacro("__ELF__"); 559 Builder.defineMacro("__LP32__"); 560 Builder.defineMacro("_ARCH_PPC64"); 561 Builder.defineMacro("__powerpc64__"); 562 } 563 public: 564 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 565 this->LongWidth = this->LongAlign = 32; 566 this->PointerWidth = this->PointerAlign = 32; 567 this->IntMaxType = TargetInfo::SignedLongLong; 568 this->Int64Type = TargetInfo::SignedLongLong; 569 this->SizeType = TargetInfo::UnsignedInt; 570 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64"; 571 } 572 }; 573 574 template <typename Target> 575 class PS4OSTargetInfo : public OSTargetInfo<Target> { 576 protected: 577 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 578 MacroBuilder &Builder) const override { 579 Builder.defineMacro("__FreeBSD__", "9"); 580 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 581 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 582 DefineStd(Builder, "unix", Opts); 583 Builder.defineMacro("__ELF__"); 584 Builder.defineMacro("__PS4__"); 585 } 586 public: 587 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 588 this->WCharType = this->UnsignedShort; 589 590 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 591 this->MaxTLSAlign = 256; 592 593 switch (Triple.getArch()) { 594 default: 595 case llvm::Triple::x86_64: 596 this->MCountName = ".mcount"; 597 break; 598 } 599 } 600 }; 601 602 // Solaris target 603 template<typename Target> 604 class SolarisTargetInfo : public OSTargetInfo<Target> { 605 protected: 606 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 607 MacroBuilder &Builder) const override { 608 DefineStd(Builder, "sun", Opts); 609 DefineStd(Builder, "unix", Opts); 610 Builder.defineMacro("__ELF__"); 611 Builder.defineMacro("__svr4__"); 612 Builder.defineMacro("__SVR4"); 613 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 614 // newer, but to 500 for everything else. feature_test.h has a check to 615 // ensure that you are not using C99 with an old version of X/Open or C89 616 // with a new version. 617 if (Opts.C99) 618 Builder.defineMacro("_XOPEN_SOURCE", "600"); 619 else 620 Builder.defineMacro("_XOPEN_SOURCE", "500"); 621 if (Opts.CPlusPlus) 622 Builder.defineMacro("__C99FEATURES__"); 623 Builder.defineMacro("_LARGEFILE_SOURCE"); 624 Builder.defineMacro("_LARGEFILE64_SOURCE"); 625 Builder.defineMacro("__EXTENSIONS__"); 626 Builder.defineMacro("_REENTRANT"); 627 } 628 public: 629 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 630 this->UserLabelPrefix = ""; 631 this->WCharType = this->SignedInt; 632 // FIXME: WIntType should be SignedLong 633 } 634 }; 635 636 // Windows target 637 template<typename Target> 638 class WindowsTargetInfo : public OSTargetInfo<Target> { 639 protected: 640 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 641 MacroBuilder &Builder) const override { 642 Builder.defineMacro("_WIN32"); 643 } 644 void getVisualStudioDefines(const LangOptions &Opts, 645 MacroBuilder &Builder) const { 646 if (Opts.CPlusPlus) { 647 if (Opts.RTTIData) 648 Builder.defineMacro("_CPPRTTI"); 649 650 if (Opts.CXXExceptions) 651 Builder.defineMacro("_CPPUNWIND"); 652 } 653 654 if (Opts.Bool) 655 Builder.defineMacro("__BOOL_DEFINED"); 656 657 if (!Opts.CharIsSigned) 658 Builder.defineMacro("_CHAR_UNSIGNED"); 659 660 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 661 // but it works for now. 662 if (Opts.POSIXThreads) 663 Builder.defineMacro("_MT"); 664 665 if (Opts.MSCompatibilityVersion) { 666 Builder.defineMacro("_MSC_VER", 667 Twine(Opts.MSCompatibilityVersion / 100000)); 668 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 669 // FIXME We cannot encode the revision information into 32-bits 670 Builder.defineMacro("_MSC_BUILD", Twine(1)); 671 672 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 673 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 674 } 675 676 if (Opts.MicrosoftExt) { 677 Builder.defineMacro("_MSC_EXTENSIONS"); 678 679 if (Opts.CPlusPlus11) { 680 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 681 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 682 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 683 } 684 } 685 686 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 687 } 688 689 public: 690 WindowsTargetInfo(const llvm::Triple &Triple) 691 : OSTargetInfo<Target>(Triple) {} 692 }; 693 694 template <typename Target> 695 class NaClTargetInfo : public OSTargetInfo<Target> { 696 protected: 697 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 698 MacroBuilder &Builder) const override { 699 if (Opts.POSIXThreads) 700 Builder.defineMacro("_REENTRANT"); 701 if (Opts.CPlusPlus) 702 Builder.defineMacro("_GNU_SOURCE"); 703 704 DefineStd(Builder, "unix", Opts); 705 Builder.defineMacro("__ELF__"); 706 Builder.defineMacro("__native_client__"); 707 } 708 709 public: 710 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 711 this->LongAlign = 32; 712 this->LongWidth = 32; 713 this->PointerAlign = 32; 714 this->PointerWidth = 32; 715 this->IntMaxType = TargetInfo::SignedLongLong; 716 this->Int64Type = TargetInfo::SignedLongLong; 717 this->DoubleAlign = 64; 718 this->LongDoubleWidth = 64; 719 this->LongDoubleAlign = 64; 720 this->LongLongWidth = 64; 721 this->LongLongAlign = 64; 722 this->SizeType = TargetInfo::UnsignedInt; 723 this->PtrDiffType = TargetInfo::SignedInt; 724 this->IntPtrType = TargetInfo::SignedInt; 725 // RegParmMax is inherited from the underlying architecture 726 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 727 if (Triple.getArch() == llvm::Triple::arm) { 728 // Handled in ARM's setABI(). 729 } else if (Triple.getArch() == llvm::Triple::x86) { 730 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 731 } else if (Triple.getArch() == llvm::Triple::x86_64) { 732 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 733 } else if (Triple.getArch() == llvm::Triple::mipsel) { 734 // Handled on mips' setDataLayoutString. 735 } else { 736 assert(Triple.getArch() == llvm::Triple::le32); 737 this->DataLayoutString = "e-p:32:32-i64:64"; 738 } 739 } 740 }; 741 742 // WebAssembly target 743 template <typename Target> 744 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 745 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 746 MacroBuilder &Builder) const final { 747 // A common platform macro. 748 if (Opts.POSIXThreads) 749 Builder.defineMacro("_REENTRANT"); 750 // Follow g++ convention and predefine _GNU_SOURCE for C++. 751 if (Opts.CPlusPlus) 752 Builder.defineMacro("_GNU_SOURCE"); 753 } 754 755 // As an optimization, group static init code together in a section. 756 const char *getStaticInitSectionSpecifier() const final { 757 return ".text.__startup"; 758 } 759 760 public: 761 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 762 : OSTargetInfo<Target>(Triple) { 763 this->MCountName = "__mcount"; 764 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 765 } 766 }; 767 768 //===----------------------------------------------------------------------===// 769 // Specific target implementations. 770 //===----------------------------------------------------------------------===// 771 772 // PPC abstract base class 773 class PPCTargetInfo : public TargetInfo { 774 static const Builtin::Info BuiltinInfo[]; 775 static const char * const GCCRegNames[]; 776 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 777 std::string CPU; 778 779 // Target cpu features. 780 bool HasVSX; 781 bool HasP8Vector; 782 bool HasP8Crypto; 783 bool HasDirectMove; 784 bool HasQPX; 785 bool HasHTM; 786 bool HasBPERMD; 787 bool HasExtDiv; 788 789 protected: 790 std::string ABI; 791 792 public: 793 PPCTargetInfo(const llvm::Triple &Triple) 794 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 795 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 796 HasBPERMD(false), HasExtDiv(false) { 797 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 798 SimdDefaultAlign = 128; 799 LongDoubleWidth = LongDoubleAlign = 128; 800 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 801 UserLabelPrefix = "_"; 802 } 803 804 /// \brief Flags for architecture specific defines. 805 typedef enum { 806 ArchDefineNone = 0, 807 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 808 ArchDefinePpcgr = 1 << 1, 809 ArchDefinePpcsq = 1 << 2, 810 ArchDefine440 = 1 << 3, 811 ArchDefine603 = 1 << 4, 812 ArchDefine604 = 1 << 5, 813 ArchDefinePwr4 = 1 << 6, 814 ArchDefinePwr5 = 1 << 7, 815 ArchDefinePwr5x = 1 << 8, 816 ArchDefinePwr6 = 1 << 9, 817 ArchDefinePwr6x = 1 << 10, 818 ArchDefinePwr7 = 1 << 11, 819 ArchDefinePwr8 = 1 << 12, 820 ArchDefineA2 = 1 << 13, 821 ArchDefineA2q = 1 << 14 822 } ArchDefineTypes; 823 824 // Note: GCC recognizes the following additional cpus: 825 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 826 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 827 // titan, rs64. 828 bool setCPU(const std::string &Name) override { 829 bool CPUKnown = llvm::StringSwitch<bool>(Name) 830 .Case("generic", true) 831 .Case("440", true) 832 .Case("450", true) 833 .Case("601", true) 834 .Case("602", true) 835 .Case("603", true) 836 .Case("603e", true) 837 .Case("603ev", true) 838 .Case("604", true) 839 .Case("604e", true) 840 .Case("620", true) 841 .Case("630", true) 842 .Case("g3", true) 843 .Case("7400", true) 844 .Case("g4", true) 845 .Case("7450", true) 846 .Case("g4+", true) 847 .Case("750", true) 848 .Case("970", true) 849 .Case("g5", true) 850 .Case("a2", true) 851 .Case("a2q", true) 852 .Case("e500mc", true) 853 .Case("e5500", true) 854 .Case("power3", true) 855 .Case("pwr3", true) 856 .Case("power4", true) 857 .Case("pwr4", true) 858 .Case("power5", true) 859 .Case("pwr5", true) 860 .Case("power5x", true) 861 .Case("pwr5x", true) 862 .Case("power6", true) 863 .Case("pwr6", true) 864 .Case("power6x", true) 865 .Case("pwr6x", true) 866 .Case("power7", true) 867 .Case("pwr7", true) 868 .Case("power8", true) 869 .Case("pwr8", true) 870 .Case("powerpc", true) 871 .Case("ppc", true) 872 .Case("powerpc64", true) 873 .Case("ppc64", true) 874 .Case("powerpc64le", true) 875 .Case("ppc64le", true) 876 .Default(false); 877 878 if (CPUKnown) 879 CPU = Name; 880 881 return CPUKnown; 882 } 883 884 885 StringRef getABI() const override { return ABI; } 886 887 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 888 return llvm::makeArrayRef(BuiltinInfo, 889 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 890 } 891 892 bool isCLZForZeroUndef() const override { return false; } 893 894 void getTargetDefines(const LangOptions &Opts, 895 MacroBuilder &Builder) const override; 896 897 bool 898 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 899 StringRef CPU, 900 const std::vector<std::string> &FeaturesVec) const override; 901 902 bool handleTargetFeatures(std::vector<std::string> &Features, 903 DiagnosticsEngine &Diags) override; 904 bool hasFeature(StringRef Feature) const override; 905 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 906 bool Enabled) const override; 907 908 ArrayRef<const char *> getGCCRegNames() const override; 909 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 910 bool validateAsmConstraint(const char *&Name, 911 TargetInfo::ConstraintInfo &Info) const override { 912 switch (*Name) { 913 default: return false; 914 case 'O': // Zero 915 break; 916 case 'b': // Base register 917 case 'f': // Floating point register 918 Info.setAllowsRegister(); 919 break; 920 // FIXME: The following are added to allow parsing. 921 // I just took a guess at what the actions should be. 922 // Also, is more specific checking needed? I.e. specific registers? 923 case 'd': // Floating point register (containing 64-bit value) 924 case 'v': // Altivec vector register 925 Info.setAllowsRegister(); 926 break; 927 case 'w': 928 switch (Name[1]) { 929 case 'd':// VSX vector register to hold vector double data 930 case 'f':// VSX vector register to hold vector float data 931 case 's':// VSX vector register to hold scalar float data 932 case 'a':// Any VSX register 933 case 'c':// An individual CR bit 934 break; 935 default: 936 return false; 937 } 938 Info.setAllowsRegister(); 939 Name++; // Skip over 'w'. 940 break; 941 case 'h': // `MQ', `CTR', or `LINK' register 942 case 'q': // `MQ' register 943 case 'c': // `CTR' register 944 case 'l': // `LINK' register 945 case 'x': // `CR' register (condition register) number 0 946 case 'y': // `CR' register (condition register) 947 case 'z': // `XER[CA]' carry bit (part of the XER register) 948 Info.setAllowsRegister(); 949 break; 950 case 'I': // Signed 16-bit constant 951 case 'J': // Unsigned 16-bit constant shifted left 16 bits 952 // (use `L' instead for SImode constants) 953 case 'K': // Unsigned 16-bit constant 954 case 'L': // Signed 16-bit constant shifted left 16 bits 955 case 'M': // Constant larger than 31 956 case 'N': // Exact power of 2 957 case 'P': // Constant whose negation is a signed 16-bit constant 958 case 'G': // Floating point constant that can be loaded into a 959 // register with one instruction per word 960 case 'H': // Integer/Floating point constant that can be loaded 961 // into a register using three instructions 962 break; 963 case 'm': // Memory operand. Note that on PowerPC targets, m can 964 // include addresses that update the base register. It 965 // is therefore only safe to use `m' in an asm statement 966 // if that asm statement accesses the operand exactly once. 967 // The asm statement must also use `%U<opno>' as a 968 // placeholder for the "update" flag in the corresponding 969 // load or store instruction. For example: 970 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 971 // is correct but: 972 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 973 // is not. Use es rather than m if you don't want the base 974 // register to be updated. 975 case 'e': 976 if (Name[1] != 's') 977 return false; 978 // es: A "stable" memory operand; that is, one which does not 979 // include any automodification of the base register. Unlike 980 // `m', this constraint can be used in asm statements that 981 // might access the operand several times, or that might not 982 // access it at all. 983 Info.setAllowsMemory(); 984 Name++; // Skip over 'e'. 985 break; 986 case 'Q': // Memory operand that is an offset from a register (it is 987 // usually better to use `m' or `es' in asm statements) 988 case 'Z': // Memory operand that is an indexed or indirect from a 989 // register (it is usually better to use `m' or `es' in 990 // asm statements) 991 Info.setAllowsMemory(); 992 Info.setAllowsRegister(); 993 break; 994 case 'R': // AIX TOC entry 995 case 'a': // Address operand that is an indexed or indirect from a 996 // register (`p' is preferable for asm statements) 997 case 'S': // Constant suitable as a 64-bit mask operand 998 case 'T': // Constant suitable as a 32-bit mask operand 999 case 'U': // System V Release 4 small data area reference 1000 case 't': // AND masks that can be performed by two rldic{l, r} 1001 // instructions 1002 case 'W': // Vector constant that does not require memory 1003 case 'j': // Vector constant that is all zeros. 1004 break; 1005 // End FIXME. 1006 } 1007 return true; 1008 } 1009 std::string convertConstraint(const char *&Constraint) const override { 1010 std::string R; 1011 switch (*Constraint) { 1012 case 'e': 1013 case 'w': 1014 // Two-character constraint; add "^" hint for later parsing. 1015 R = std::string("^") + std::string(Constraint, 2); 1016 Constraint++; 1017 break; 1018 default: 1019 return TargetInfo::convertConstraint(Constraint); 1020 } 1021 return R; 1022 } 1023 const char *getClobbers() const override { 1024 return ""; 1025 } 1026 int getEHDataRegisterNumber(unsigned RegNo) const override { 1027 if (RegNo == 0) return 3; 1028 if (RegNo == 1) return 4; 1029 return -1; 1030 } 1031 1032 bool hasSjLjLowering() const override { 1033 return true; 1034 } 1035 1036 bool useFloat128ManglingForLongDouble() const override { 1037 return LongDoubleWidth == 128 && 1038 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1039 getTriple().isOSBinFormatELF(); 1040 } 1041 }; 1042 1043 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1044 #define BUILTIN(ID, TYPE, ATTRS) \ 1045 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1046 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1047 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1048 #include "clang/Basic/BuiltinsPPC.def" 1049 }; 1050 1051 /// handleTargetFeatures - Perform initialization based on the user 1052 /// configured set of features. 1053 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1054 DiagnosticsEngine &Diags) { 1055 for (const auto &Feature : Features) { 1056 if (Feature == "+vsx") { 1057 HasVSX = true; 1058 } else if (Feature == "+bpermd") { 1059 HasBPERMD = true; 1060 } else if (Feature == "+extdiv") { 1061 HasExtDiv = true; 1062 } else if (Feature == "+power8-vector") { 1063 HasP8Vector = true; 1064 } else if (Feature == "+crypto") { 1065 HasP8Crypto = true; 1066 } else if (Feature == "+direct-move") { 1067 HasDirectMove = true; 1068 } else if (Feature == "+qpx") { 1069 HasQPX = true; 1070 } else if (Feature == "+htm") { 1071 HasHTM = true; 1072 } 1073 // TODO: Finish this list and add an assert that we've handled them 1074 // all. 1075 } 1076 1077 return true; 1078 } 1079 1080 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1081 /// #defines that are not tied to a specific subtarget. 1082 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1083 MacroBuilder &Builder) const { 1084 // Target identification. 1085 Builder.defineMacro("__ppc__"); 1086 Builder.defineMacro("__PPC__"); 1087 Builder.defineMacro("_ARCH_PPC"); 1088 Builder.defineMacro("__powerpc__"); 1089 Builder.defineMacro("__POWERPC__"); 1090 if (PointerWidth == 64) { 1091 Builder.defineMacro("_ARCH_PPC64"); 1092 Builder.defineMacro("__powerpc64__"); 1093 Builder.defineMacro("__ppc64__"); 1094 Builder.defineMacro("__PPC64__"); 1095 } 1096 1097 // Target properties. 1098 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1099 Builder.defineMacro("_LITTLE_ENDIAN"); 1100 } else { 1101 if (getTriple().getOS() != llvm::Triple::NetBSD && 1102 getTriple().getOS() != llvm::Triple::OpenBSD) 1103 Builder.defineMacro("_BIG_ENDIAN"); 1104 } 1105 1106 // ABI options. 1107 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1108 Builder.defineMacro("_CALL_ELF", "1"); 1109 if (ABI == "elfv2") 1110 Builder.defineMacro("_CALL_ELF", "2"); 1111 1112 // Subtarget options. 1113 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1114 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1115 1116 // FIXME: Should be controlled by command line option. 1117 if (LongDoubleWidth == 128) 1118 Builder.defineMacro("__LONG_DOUBLE_128__"); 1119 1120 if (Opts.AltiVec) { 1121 Builder.defineMacro("__VEC__", "10206"); 1122 Builder.defineMacro("__ALTIVEC__"); 1123 } 1124 1125 // CPU identification. 1126 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1127 .Case("440", ArchDefineName) 1128 .Case("450", ArchDefineName | ArchDefine440) 1129 .Case("601", ArchDefineName) 1130 .Case("602", ArchDefineName | ArchDefinePpcgr) 1131 .Case("603", ArchDefineName | ArchDefinePpcgr) 1132 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1133 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1134 .Case("604", ArchDefineName | ArchDefinePpcgr) 1135 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1136 .Case("620", ArchDefineName | ArchDefinePpcgr) 1137 .Case("630", ArchDefineName | ArchDefinePpcgr) 1138 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1139 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1140 .Case("750", ArchDefineName | ArchDefinePpcgr) 1141 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1142 | ArchDefinePpcsq) 1143 .Case("a2", ArchDefineA2) 1144 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1145 .Case("pwr3", ArchDefinePpcgr) 1146 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1147 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1148 | ArchDefinePpcsq) 1149 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1150 | ArchDefinePpcgr | ArchDefinePpcsq) 1151 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1152 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1153 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1154 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1155 | ArchDefinePpcsq) 1156 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1157 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1158 | ArchDefinePpcgr | ArchDefinePpcsq) 1159 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1160 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1161 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1162 .Case("power3", ArchDefinePpcgr) 1163 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1164 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1165 | ArchDefinePpcsq) 1166 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1167 | ArchDefinePpcgr | ArchDefinePpcsq) 1168 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1169 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1170 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1171 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1172 | ArchDefinePpcsq) 1173 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1174 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1175 | ArchDefinePpcgr | ArchDefinePpcsq) 1176 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1177 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1178 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1179 .Default(ArchDefineNone); 1180 1181 if (defs & ArchDefineName) 1182 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1183 if (defs & ArchDefinePpcgr) 1184 Builder.defineMacro("_ARCH_PPCGR"); 1185 if (defs & ArchDefinePpcsq) 1186 Builder.defineMacro("_ARCH_PPCSQ"); 1187 if (defs & ArchDefine440) 1188 Builder.defineMacro("_ARCH_440"); 1189 if (defs & ArchDefine603) 1190 Builder.defineMacro("_ARCH_603"); 1191 if (defs & ArchDefine604) 1192 Builder.defineMacro("_ARCH_604"); 1193 if (defs & ArchDefinePwr4) 1194 Builder.defineMacro("_ARCH_PWR4"); 1195 if (defs & ArchDefinePwr5) 1196 Builder.defineMacro("_ARCH_PWR5"); 1197 if (defs & ArchDefinePwr5x) 1198 Builder.defineMacro("_ARCH_PWR5X"); 1199 if (defs & ArchDefinePwr6) 1200 Builder.defineMacro("_ARCH_PWR6"); 1201 if (defs & ArchDefinePwr6x) 1202 Builder.defineMacro("_ARCH_PWR6X"); 1203 if (defs & ArchDefinePwr7) 1204 Builder.defineMacro("_ARCH_PWR7"); 1205 if (defs & ArchDefinePwr8) 1206 Builder.defineMacro("_ARCH_PWR8"); 1207 if (defs & ArchDefineA2) 1208 Builder.defineMacro("_ARCH_A2"); 1209 if (defs & ArchDefineA2q) { 1210 Builder.defineMacro("_ARCH_A2Q"); 1211 Builder.defineMacro("_ARCH_QP"); 1212 } 1213 1214 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1215 Builder.defineMacro("__bg__"); 1216 Builder.defineMacro("__THW_BLUEGENE__"); 1217 Builder.defineMacro("__bgq__"); 1218 Builder.defineMacro("__TOS_BGQ__"); 1219 } 1220 1221 if (HasVSX) 1222 Builder.defineMacro("__VSX__"); 1223 if (HasP8Vector) 1224 Builder.defineMacro("__POWER8_VECTOR__"); 1225 if (HasP8Crypto) 1226 Builder.defineMacro("__CRYPTO__"); 1227 if (HasHTM) 1228 Builder.defineMacro("__HTM__"); 1229 1230 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1231 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1232 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1233 if (PointerWidth == 64) 1234 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1235 1236 // FIXME: The following are not yet generated here by Clang, but are 1237 // generated by GCC: 1238 // 1239 // _SOFT_FLOAT_ 1240 // __RECIP_PRECISION__ 1241 // __APPLE_ALTIVEC__ 1242 // __RECIP__ 1243 // __RECIPF__ 1244 // __RSQRTE__ 1245 // __RSQRTEF__ 1246 // _SOFT_DOUBLE_ 1247 // __NO_LWSYNC__ 1248 // __HAVE_BSWAP__ 1249 // __LONGDOUBLE128 1250 // __CMODEL_MEDIUM__ 1251 // __CMODEL_LARGE__ 1252 // _CALL_SYSV 1253 // _CALL_DARWIN 1254 // __NO_FPRS__ 1255 } 1256 1257 // Handle explicit options being passed to the compiler here: if we've 1258 // explicitly turned off vsx and turned on power8-vector or direct-move then 1259 // go ahead and error since the customer has expressed a somewhat incompatible 1260 // set of options. 1261 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1262 const std::vector<std::string> &FeaturesVec) { 1263 1264 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1265 FeaturesVec.end()) { 1266 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1267 FeaturesVec.end()) { 1268 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1269 << "-mno-vsx"; 1270 return false; 1271 } 1272 1273 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1274 FeaturesVec.end()) { 1275 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1276 << "-mno-vsx"; 1277 return false; 1278 } 1279 } 1280 1281 return true; 1282 } 1283 1284 bool PPCTargetInfo::initFeatureMap( 1285 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1286 const std::vector<std::string> &FeaturesVec) const { 1287 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1288 .Case("7400", true) 1289 .Case("g4", true) 1290 .Case("7450", true) 1291 .Case("g4+", true) 1292 .Case("970", true) 1293 .Case("g5", true) 1294 .Case("pwr6", true) 1295 .Case("pwr7", true) 1296 .Case("pwr8", true) 1297 .Case("ppc64", true) 1298 .Case("ppc64le", true) 1299 .Default(false); 1300 1301 Features["qpx"] = (CPU == "a2q"); 1302 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1303 .Case("ppc64le", true) 1304 .Case("pwr8", true) 1305 .Default(false); 1306 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1307 .Case("ppc64le", true) 1308 .Case("pwr8", true) 1309 .Default(false); 1310 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1311 .Case("ppc64le", true) 1312 .Case("pwr8", true) 1313 .Case("pwr7", true) 1314 .Default(false); 1315 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1316 .Case("ppc64le", true) 1317 .Case("pwr8", true) 1318 .Case("pwr7", true) 1319 .Default(false); 1320 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1321 .Case("ppc64le", true) 1322 .Case("pwr8", true) 1323 .Default(false); 1324 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1325 .Case("ppc64le", true) 1326 .Case("pwr8", true) 1327 .Case("pwr7", true) 1328 .Default(false); 1329 1330 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1331 return false; 1332 1333 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1334 } 1335 1336 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1337 return llvm::StringSwitch<bool>(Feature) 1338 .Case("powerpc", true) 1339 .Case("vsx", HasVSX) 1340 .Case("power8-vector", HasP8Vector) 1341 .Case("crypto", HasP8Crypto) 1342 .Case("direct-move", HasDirectMove) 1343 .Case("qpx", HasQPX) 1344 .Case("htm", HasHTM) 1345 .Case("bpermd", HasBPERMD) 1346 .Case("extdiv", HasExtDiv) 1347 .Default(false); 1348 } 1349 1350 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1351 StringRef Name, bool Enabled) const { 1352 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1353 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1354 // incompatible options. 1355 if (Enabled) { 1356 if (Name == "vsx") { 1357 Features[Name] = true; 1358 } else if (Name == "direct-move") { 1359 Features[Name] = Features["vsx"] = true; 1360 } else if (Name == "power8-vector") { 1361 Features[Name] = Features["vsx"] = true; 1362 } else { 1363 Features[Name] = true; 1364 } 1365 } else { 1366 if (Name == "vsx") { 1367 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1368 false; 1369 } else { 1370 Features[Name] = false; 1371 } 1372 } 1373 } 1374 1375 const char * const PPCTargetInfo::GCCRegNames[] = { 1376 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1377 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1378 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1379 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1380 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1381 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1382 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1383 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1384 "mq", "lr", "ctr", "ap", 1385 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1386 "xer", 1387 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1388 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1389 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1390 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1391 "vrsave", "vscr", 1392 "spe_acc", "spefscr", 1393 "sfp" 1394 }; 1395 1396 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1397 return llvm::makeArrayRef(GCCRegNames); 1398 } 1399 1400 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1401 // While some of these aliases do map to different registers 1402 // they still share the same register name. 1403 { { "0" }, "r0" }, 1404 { { "1"}, "r1" }, 1405 { { "2" }, "r2" }, 1406 { { "3" }, "r3" }, 1407 { { "4" }, "r4" }, 1408 { { "5" }, "r5" }, 1409 { { "6" }, "r6" }, 1410 { { "7" }, "r7" }, 1411 { { "8" }, "r8" }, 1412 { { "9" }, "r9" }, 1413 { { "10" }, "r10" }, 1414 { { "11" }, "r11" }, 1415 { { "12" }, "r12" }, 1416 { { "13" }, "r13" }, 1417 { { "14" }, "r14" }, 1418 { { "15" }, "r15" }, 1419 { { "16" }, "r16" }, 1420 { { "17" }, "r17" }, 1421 { { "18" }, "r18" }, 1422 { { "19" }, "r19" }, 1423 { { "20" }, "r20" }, 1424 { { "21" }, "r21" }, 1425 { { "22" }, "r22" }, 1426 { { "23" }, "r23" }, 1427 { { "24" }, "r24" }, 1428 { { "25" }, "r25" }, 1429 { { "26" }, "r26" }, 1430 { { "27" }, "r27" }, 1431 { { "28" }, "r28" }, 1432 { { "29" }, "r29" }, 1433 { { "30" }, "r30" }, 1434 { { "31" }, "r31" }, 1435 { { "fr0" }, "f0" }, 1436 { { "fr1" }, "f1" }, 1437 { { "fr2" }, "f2" }, 1438 { { "fr3" }, "f3" }, 1439 { { "fr4" }, "f4" }, 1440 { { "fr5" }, "f5" }, 1441 { { "fr6" }, "f6" }, 1442 { { "fr7" }, "f7" }, 1443 { { "fr8" }, "f8" }, 1444 { { "fr9" }, "f9" }, 1445 { { "fr10" }, "f10" }, 1446 { { "fr11" }, "f11" }, 1447 { { "fr12" }, "f12" }, 1448 { { "fr13" }, "f13" }, 1449 { { "fr14" }, "f14" }, 1450 { { "fr15" }, "f15" }, 1451 { { "fr16" }, "f16" }, 1452 { { "fr17" }, "f17" }, 1453 { { "fr18" }, "f18" }, 1454 { { "fr19" }, "f19" }, 1455 { { "fr20" }, "f20" }, 1456 { { "fr21" }, "f21" }, 1457 { { "fr22" }, "f22" }, 1458 { { "fr23" }, "f23" }, 1459 { { "fr24" }, "f24" }, 1460 { { "fr25" }, "f25" }, 1461 { { "fr26" }, "f26" }, 1462 { { "fr27" }, "f27" }, 1463 { { "fr28" }, "f28" }, 1464 { { "fr29" }, "f29" }, 1465 { { "fr30" }, "f30" }, 1466 { { "fr31" }, "f31" }, 1467 { { "cc" }, "cr0" }, 1468 }; 1469 1470 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1471 return llvm::makeArrayRef(GCCRegAliases); 1472 } 1473 1474 class PPC32TargetInfo : public PPCTargetInfo { 1475 public: 1476 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1477 DataLayoutString = "E-m:e-p:32:32-i64:64-n32"; 1478 1479 switch (getTriple().getOS()) { 1480 case llvm::Triple::Linux: 1481 case llvm::Triple::FreeBSD: 1482 case llvm::Triple::NetBSD: 1483 SizeType = UnsignedInt; 1484 PtrDiffType = SignedInt; 1485 IntPtrType = SignedInt; 1486 break; 1487 default: 1488 break; 1489 } 1490 1491 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1492 LongDoubleWidth = LongDoubleAlign = 64; 1493 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1494 } 1495 1496 // PPC32 supports atomics up to 4 bytes. 1497 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1498 } 1499 1500 BuiltinVaListKind getBuiltinVaListKind() const override { 1501 // This is the ELF definition, and is overridden by the Darwin sub-target 1502 return TargetInfo::PowerABIBuiltinVaList; 1503 } 1504 }; 1505 1506 // Note: ABI differences may eventually require us to have a separate 1507 // TargetInfo for little endian. 1508 class PPC64TargetInfo : public PPCTargetInfo { 1509 public: 1510 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1511 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1512 IntMaxType = SignedLong; 1513 Int64Type = SignedLong; 1514 1515 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1516 DataLayoutString = "e-m:e-i64:64-n32:64"; 1517 ABI = "elfv2"; 1518 } else { 1519 DataLayoutString = "E-m:e-i64:64-n32:64"; 1520 ABI = "elfv1"; 1521 } 1522 1523 switch (getTriple().getOS()) { 1524 case llvm::Triple::FreeBSD: 1525 LongDoubleWidth = LongDoubleAlign = 64; 1526 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1527 break; 1528 case llvm::Triple::NetBSD: 1529 IntMaxType = SignedLongLong; 1530 Int64Type = SignedLongLong; 1531 break; 1532 default: 1533 break; 1534 } 1535 1536 // PPC64 supports atomics up to 8 bytes. 1537 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1538 } 1539 BuiltinVaListKind getBuiltinVaListKind() const override { 1540 return TargetInfo::CharPtrBuiltinVaList; 1541 } 1542 // PPC64 Linux-specific ABI options. 1543 bool setABI(const std::string &Name) override { 1544 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1545 ABI = Name; 1546 return true; 1547 } 1548 return false; 1549 } 1550 }; 1551 1552 class DarwinPPC32TargetInfo : 1553 public DarwinTargetInfo<PPC32TargetInfo> { 1554 public: 1555 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1556 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1557 HasAlignMac68kSupport = true; 1558 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1559 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1560 LongLongAlign = 32; 1561 SuitableAlign = 128; 1562 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32"; 1563 } 1564 BuiltinVaListKind getBuiltinVaListKind() const override { 1565 return TargetInfo::CharPtrBuiltinVaList; 1566 } 1567 }; 1568 1569 class DarwinPPC64TargetInfo : 1570 public DarwinTargetInfo<PPC64TargetInfo> { 1571 public: 1572 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1573 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1574 HasAlignMac68kSupport = true; 1575 SuitableAlign = 128; 1576 DataLayoutString = "E-m:o-i64:64-n32:64"; 1577 } 1578 }; 1579 1580 static const unsigned NVPTXAddrSpaceMap[] = { 1581 1, // opencl_global 1582 3, // opencl_local 1583 4, // opencl_constant 1584 // FIXME: generic has to be added to the target 1585 0, // opencl_generic 1586 1, // cuda_device 1587 4, // cuda_constant 1588 3, // cuda_shared 1589 }; 1590 1591 class NVPTXTargetInfo : public TargetInfo { 1592 static const char *const GCCRegNames[]; 1593 static const Builtin::Info BuiltinInfo[]; 1594 1595 // The GPU profiles supported by the NVPTX backend 1596 enum GPUKind { 1597 GK_NONE, 1598 GK_SM20, 1599 GK_SM21, 1600 GK_SM30, 1601 GK_SM35, 1602 GK_SM37, 1603 } GPU; 1604 1605 public: 1606 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1607 BigEndian = false; 1608 TLSSupported = false; 1609 LongWidth = LongAlign = 64; 1610 AddrSpaceMap = &NVPTXAddrSpaceMap; 1611 UseAddrSpaceMapMangling = true; 1612 // Define available target features 1613 // These must be defined in sorted order! 1614 NoAsmVariants = true; 1615 // Set the default GPU to sm20 1616 GPU = GK_SM20; 1617 UserLabelPrefix = "_"; 1618 } 1619 void getTargetDefines(const LangOptions &Opts, 1620 MacroBuilder &Builder) const override { 1621 Builder.defineMacro("__PTX__"); 1622 Builder.defineMacro("__NVPTX__"); 1623 if (Opts.CUDAIsDevice) { 1624 // Set __CUDA_ARCH__ for the GPU specified. 1625 std::string CUDAArchCode; 1626 switch (GPU) { 1627 case GK_SM20: 1628 CUDAArchCode = "200"; 1629 break; 1630 case GK_SM21: 1631 CUDAArchCode = "210"; 1632 break; 1633 case GK_SM30: 1634 CUDAArchCode = "300"; 1635 break; 1636 case GK_SM35: 1637 CUDAArchCode = "350"; 1638 break; 1639 case GK_SM37: 1640 CUDAArchCode = "370"; 1641 break; 1642 default: 1643 llvm_unreachable("Unhandled target CPU"); 1644 } 1645 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1646 } 1647 } 1648 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1649 return llvm::makeArrayRef(BuiltinInfo, 1650 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1651 } 1652 bool hasFeature(StringRef Feature) const override { 1653 return Feature == "ptx" || Feature == "nvptx"; 1654 } 1655 1656 ArrayRef<const char *> getGCCRegNames() const override; 1657 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1658 // No aliases. 1659 return None; 1660 } 1661 bool validateAsmConstraint(const char *&Name, 1662 TargetInfo::ConstraintInfo &Info) const override { 1663 switch (*Name) { 1664 default: 1665 return false; 1666 case 'c': 1667 case 'h': 1668 case 'r': 1669 case 'l': 1670 case 'f': 1671 case 'd': 1672 Info.setAllowsRegister(); 1673 return true; 1674 } 1675 } 1676 const char *getClobbers() const override { 1677 // FIXME: Is this really right? 1678 return ""; 1679 } 1680 BuiltinVaListKind getBuiltinVaListKind() const override { 1681 // FIXME: implement 1682 return TargetInfo::CharPtrBuiltinVaList; 1683 } 1684 bool setCPU(const std::string &Name) override { 1685 GPU = llvm::StringSwitch<GPUKind>(Name) 1686 .Case("sm_20", GK_SM20) 1687 .Case("sm_21", GK_SM21) 1688 .Case("sm_30", GK_SM30) 1689 .Case("sm_35", GK_SM35) 1690 .Case("sm_37", GK_SM37) 1691 .Default(GK_NONE); 1692 1693 return GPU != GK_NONE; 1694 } 1695 }; 1696 1697 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1698 #define BUILTIN(ID, TYPE, ATTRS) \ 1699 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1700 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1701 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1702 #include "clang/Basic/BuiltinsNVPTX.def" 1703 }; 1704 1705 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1706 1707 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1708 return llvm::makeArrayRef(GCCRegNames); 1709 } 1710 1711 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1712 public: 1713 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1714 LongWidth = LongAlign = 32; 1715 PointerWidth = PointerAlign = 32; 1716 SizeType = TargetInfo::UnsignedInt; 1717 PtrDiffType = TargetInfo::SignedInt; 1718 IntPtrType = TargetInfo::SignedInt; 1719 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1720 } 1721 }; 1722 1723 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1724 public: 1725 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1726 PointerWidth = PointerAlign = 64; 1727 SizeType = TargetInfo::UnsignedLong; 1728 PtrDiffType = TargetInfo::SignedLong; 1729 IntPtrType = TargetInfo::SignedLong; 1730 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1731 } 1732 }; 1733 1734 static const unsigned AMDGPUAddrSpaceMap[] = { 1735 1, // opencl_global 1736 3, // opencl_local 1737 2, // opencl_constant 1738 4, // opencl_generic 1739 1, // cuda_device 1740 2, // cuda_constant 1741 3 // cuda_shared 1742 }; 1743 1744 // If you edit the description strings, make sure you update 1745 // getPointerWidthV(). 1746 1747 static const char *const DataLayoutStringR600 = 1748 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1749 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1750 1751 static const char *const DataLayoutStringR600DoubleOps = 1752 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1753 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1754 1755 static const char *const DataLayoutStringSI = 1756 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1757 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1758 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1759 1760 class AMDGPUTargetInfo : public TargetInfo { 1761 static const Builtin::Info BuiltinInfo[]; 1762 static const char * const GCCRegNames[]; 1763 1764 /// \brief The GPU profiles supported by the AMDGPU target. 1765 enum GPUKind { 1766 GK_NONE, 1767 GK_R600, 1768 GK_R600_DOUBLE_OPS, 1769 GK_R700, 1770 GK_R700_DOUBLE_OPS, 1771 GK_EVERGREEN, 1772 GK_EVERGREEN_DOUBLE_OPS, 1773 GK_NORTHERN_ISLANDS, 1774 GK_CAYMAN, 1775 GK_SOUTHERN_ISLANDS, 1776 GK_SEA_ISLANDS, 1777 GK_VOLCANIC_ISLANDS 1778 } GPU; 1779 1780 bool hasFP64:1; 1781 bool hasFMAF:1; 1782 bool hasLDEXPF:1; 1783 1784 public: 1785 AMDGPUTargetInfo(const llvm::Triple &Triple) 1786 : TargetInfo(Triple) { 1787 1788 if (Triple.getArch() == llvm::Triple::amdgcn) { 1789 DataLayoutString = DataLayoutStringSI; 1790 GPU = GK_SOUTHERN_ISLANDS; 1791 hasFP64 = true; 1792 hasFMAF = true; 1793 hasLDEXPF = true; 1794 } else { 1795 DataLayoutString = DataLayoutStringR600; 1796 GPU = GK_R600; 1797 hasFP64 = false; 1798 hasFMAF = false; 1799 hasLDEXPF = false; 1800 } 1801 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1802 UseAddrSpaceMapMangling = true; 1803 } 1804 1805 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1806 if (GPU <= GK_CAYMAN) 1807 return 32; 1808 1809 switch(AddrSpace) { 1810 default: 1811 return 64; 1812 case 0: 1813 case 3: 1814 case 5: 1815 return 32; 1816 } 1817 } 1818 1819 const char * getClobbers() const override { 1820 return ""; 1821 } 1822 1823 ArrayRef<const char *> getGCCRegNames() const override; 1824 1825 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1826 return None; 1827 } 1828 1829 bool validateAsmConstraint(const char *&Name, 1830 TargetInfo::ConstraintInfo &Info) const override { 1831 switch (*Name) { 1832 default: break; 1833 case 'v': // vgpr 1834 case 's': // sgpr 1835 Info.setAllowsRegister(); 1836 return true; 1837 } 1838 return false; 1839 } 1840 1841 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1842 return llvm::makeArrayRef(BuiltinInfo, 1843 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1844 } 1845 1846 void getTargetDefines(const LangOptions &Opts, 1847 MacroBuilder &Builder) const override { 1848 Builder.defineMacro("__R600__"); 1849 if (hasFMAF) 1850 Builder.defineMacro("__HAS_FMAF__"); 1851 if (hasLDEXPF) 1852 Builder.defineMacro("__HAS_LDEXPF__"); 1853 if (hasFP64 && Opts.OpenCL) 1854 Builder.defineMacro("cl_khr_fp64"); 1855 if (Opts.OpenCL) { 1856 if (GPU >= GK_NORTHERN_ISLANDS) { 1857 Builder.defineMacro("cl_khr_byte_addressable_store"); 1858 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1859 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1860 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1861 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1862 } 1863 } 1864 } 1865 1866 BuiltinVaListKind getBuiltinVaListKind() const override { 1867 return TargetInfo::CharPtrBuiltinVaList; 1868 } 1869 1870 bool setCPU(const std::string &Name) override { 1871 GPU = llvm::StringSwitch<GPUKind>(Name) 1872 .Case("r600" , GK_R600) 1873 .Case("rv610", GK_R600) 1874 .Case("rv620", GK_R600) 1875 .Case("rv630", GK_R600) 1876 .Case("rv635", GK_R600) 1877 .Case("rs780", GK_R600) 1878 .Case("rs880", GK_R600) 1879 .Case("rv670", GK_R600_DOUBLE_OPS) 1880 .Case("rv710", GK_R700) 1881 .Case("rv730", GK_R700) 1882 .Case("rv740", GK_R700_DOUBLE_OPS) 1883 .Case("rv770", GK_R700_DOUBLE_OPS) 1884 .Case("palm", GK_EVERGREEN) 1885 .Case("cedar", GK_EVERGREEN) 1886 .Case("sumo", GK_EVERGREEN) 1887 .Case("sumo2", GK_EVERGREEN) 1888 .Case("redwood", GK_EVERGREEN) 1889 .Case("juniper", GK_EVERGREEN) 1890 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1891 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1892 .Case("barts", GK_NORTHERN_ISLANDS) 1893 .Case("turks", GK_NORTHERN_ISLANDS) 1894 .Case("caicos", GK_NORTHERN_ISLANDS) 1895 .Case("cayman", GK_CAYMAN) 1896 .Case("aruba", GK_CAYMAN) 1897 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1898 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1899 .Case("verde", GK_SOUTHERN_ISLANDS) 1900 .Case("oland", GK_SOUTHERN_ISLANDS) 1901 .Case("hainan", GK_SOUTHERN_ISLANDS) 1902 .Case("bonaire", GK_SEA_ISLANDS) 1903 .Case("kabini", GK_SEA_ISLANDS) 1904 .Case("kaveri", GK_SEA_ISLANDS) 1905 .Case("hawaii", GK_SEA_ISLANDS) 1906 .Case("mullins", GK_SEA_ISLANDS) 1907 .Case("tonga", GK_VOLCANIC_ISLANDS) 1908 .Case("iceland", GK_VOLCANIC_ISLANDS) 1909 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1910 .Default(GK_NONE); 1911 1912 if (GPU == GK_NONE) { 1913 return false; 1914 } 1915 1916 // Set the correct data layout 1917 switch (GPU) { 1918 case GK_NONE: 1919 case GK_R600: 1920 case GK_R700: 1921 case GK_EVERGREEN: 1922 case GK_NORTHERN_ISLANDS: 1923 DataLayoutString = DataLayoutStringR600; 1924 hasFP64 = false; 1925 hasFMAF = false; 1926 hasLDEXPF = false; 1927 break; 1928 case GK_R600_DOUBLE_OPS: 1929 case GK_R700_DOUBLE_OPS: 1930 case GK_EVERGREEN_DOUBLE_OPS: 1931 case GK_CAYMAN: 1932 DataLayoutString = DataLayoutStringR600DoubleOps; 1933 hasFP64 = true; 1934 hasFMAF = true; 1935 hasLDEXPF = false; 1936 break; 1937 case GK_SOUTHERN_ISLANDS: 1938 case GK_SEA_ISLANDS: 1939 case GK_VOLCANIC_ISLANDS: 1940 DataLayoutString = DataLayoutStringSI; 1941 hasFP64 = true; 1942 hasFMAF = true; 1943 hasLDEXPF = true; 1944 break; 1945 } 1946 1947 return true; 1948 } 1949 }; 1950 1951 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1952 #define BUILTIN(ID, TYPE, ATTRS) \ 1953 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1954 #include "clang/Basic/BuiltinsAMDGPU.def" 1955 }; 1956 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1957 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1958 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1959 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1960 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1961 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1962 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1963 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1964 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1965 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1966 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1967 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1968 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1969 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1970 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1971 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1972 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1973 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1974 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1975 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1976 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1977 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1978 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1979 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1980 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1981 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1982 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1983 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1984 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1985 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1986 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1987 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1988 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1989 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1990 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1991 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1992 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1993 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1994 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1995 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1996 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1997 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1998 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 1999 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2000 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2001 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2002 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2003 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2004 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 2005 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 2006 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 2007 }; 2008 2009 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2010 return llvm::makeArrayRef(GCCRegNames); 2011 } 2012 2013 // Namespace for x86 abstract base class 2014 const Builtin::Info BuiltinInfo[] = { 2015 #define BUILTIN(ID, TYPE, ATTRS) \ 2016 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2017 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2018 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2019 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2020 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2021 #include "clang/Basic/BuiltinsX86.def" 2022 }; 2023 2024 static const char* const GCCRegNames[] = { 2025 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2026 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2027 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2028 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2029 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2030 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2031 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2032 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2033 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2034 }; 2035 2036 const TargetInfo::AddlRegName AddlRegNames[] = { 2037 { { "al", "ah", "eax", "rax" }, 0 }, 2038 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2039 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2040 { { "dl", "dh", "edx", "rdx" }, 1 }, 2041 { { "esi", "rsi" }, 4 }, 2042 { { "edi", "rdi" }, 5 }, 2043 { { "esp", "rsp" }, 7 }, 2044 { { "ebp", "rbp" }, 6 }, 2045 { { "r8d", "r8w", "r8b" }, 38 }, 2046 { { "r9d", "r9w", "r9b" }, 39 }, 2047 { { "r10d", "r10w", "r10b" }, 40 }, 2048 { { "r11d", "r11w", "r11b" }, 41 }, 2049 { { "r12d", "r12w", "r12b" }, 42 }, 2050 { { "r13d", "r13w", "r13b" }, 43 }, 2051 { { "r14d", "r14w", "r14b" }, 44 }, 2052 { { "r15d", "r15w", "r15b" }, 45 }, 2053 }; 2054 2055 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2056 // most of the implementation can be shared. 2057 class X86TargetInfo : public TargetInfo { 2058 enum X86SSEEnum { 2059 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2060 } SSELevel = NoSSE; 2061 enum MMX3DNowEnum { 2062 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2063 } MMX3DNowLevel = NoMMX3DNow; 2064 enum XOPEnum { 2065 NoXOP, 2066 SSE4A, 2067 FMA4, 2068 XOP 2069 } XOPLevel = NoXOP; 2070 2071 bool HasAES = false; 2072 bool HasPCLMUL = false; 2073 bool HasLZCNT = false; 2074 bool HasRDRND = false; 2075 bool HasFSGSBASE = false; 2076 bool HasBMI = false; 2077 bool HasBMI2 = false; 2078 bool HasPOPCNT = false; 2079 bool HasRTM = false; 2080 bool HasPRFCHW = false; 2081 bool HasRDSEED = false; 2082 bool HasADX = false; 2083 bool HasTBM = false; 2084 bool HasFMA = false; 2085 bool HasF16C = false; 2086 bool HasAVX512CD = false; 2087 bool HasAVX512ER = false; 2088 bool HasAVX512PF = false; 2089 bool HasAVX512DQ = false; 2090 bool HasAVX512BW = false; 2091 bool HasAVX512VL = false; 2092 bool HasSHA = false; 2093 bool HasCX16 = false; 2094 bool HasFXSR = false; 2095 bool HasXSAVE = false; 2096 bool HasXSAVEOPT = false; 2097 bool HasXSAVEC = false; 2098 bool HasXSAVES = false; 2099 bool HasPKU = false; 2100 2101 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2102 /// 2103 /// Each enumeration represents a particular CPU supported by Clang. These 2104 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2105 enum CPUKind { 2106 CK_Generic, 2107 2108 /// \name i386 2109 /// i386-generation processors. 2110 //@{ 2111 CK_i386, 2112 //@} 2113 2114 /// \name i486 2115 /// i486-generation processors. 2116 //@{ 2117 CK_i486, 2118 CK_WinChipC6, 2119 CK_WinChip2, 2120 CK_C3, 2121 //@} 2122 2123 /// \name i586 2124 /// i586-generation processors, P5 microarchitecture based. 2125 //@{ 2126 CK_i586, 2127 CK_Pentium, 2128 CK_PentiumMMX, 2129 //@} 2130 2131 /// \name i686 2132 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2133 //@{ 2134 CK_i686, 2135 CK_PentiumPro, 2136 CK_Pentium2, 2137 CK_Pentium3, 2138 CK_Pentium3M, 2139 CK_PentiumM, 2140 CK_C3_2, 2141 2142 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2143 /// Clang however has some logic to suport this. 2144 // FIXME: Warn, deprecate, and potentially remove this. 2145 CK_Yonah, 2146 //@} 2147 2148 /// \name Netburst 2149 /// Netburst microarchitecture based processors. 2150 //@{ 2151 CK_Pentium4, 2152 CK_Pentium4M, 2153 CK_Prescott, 2154 CK_Nocona, 2155 //@} 2156 2157 /// \name Core 2158 /// Core microarchitecture based processors. 2159 //@{ 2160 CK_Core2, 2161 2162 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2163 /// codename which GCC no longer accepts as an option to -march, but Clang 2164 /// has some logic for recognizing it. 2165 // FIXME: Warn, deprecate, and potentially remove this. 2166 CK_Penryn, 2167 //@} 2168 2169 /// \name Atom 2170 /// Atom processors 2171 //@{ 2172 CK_Bonnell, 2173 CK_Silvermont, 2174 //@} 2175 2176 /// \name Nehalem 2177 /// Nehalem microarchitecture based processors. 2178 CK_Nehalem, 2179 2180 /// \name Westmere 2181 /// Westmere microarchitecture based processors. 2182 CK_Westmere, 2183 2184 /// \name Sandy Bridge 2185 /// Sandy Bridge microarchitecture based processors. 2186 CK_SandyBridge, 2187 2188 /// \name Ivy Bridge 2189 /// Ivy Bridge microarchitecture based processors. 2190 CK_IvyBridge, 2191 2192 /// \name Haswell 2193 /// Haswell microarchitecture based processors. 2194 CK_Haswell, 2195 2196 /// \name Broadwell 2197 /// Broadwell microarchitecture based processors. 2198 CK_Broadwell, 2199 2200 /// \name Skylake 2201 /// Skylake microarchitecture based processors. 2202 CK_Skylake, 2203 2204 /// \name Knights Landing 2205 /// Knights Landing processor. 2206 CK_KNL, 2207 2208 /// \name K6 2209 /// K6 architecture processors. 2210 //@{ 2211 CK_K6, 2212 CK_K6_2, 2213 CK_K6_3, 2214 //@} 2215 2216 /// \name K7 2217 /// K7 architecture processors. 2218 //@{ 2219 CK_Athlon, 2220 CK_AthlonThunderbird, 2221 CK_Athlon4, 2222 CK_AthlonXP, 2223 CK_AthlonMP, 2224 //@} 2225 2226 /// \name K8 2227 /// K8 architecture processors. 2228 //@{ 2229 CK_Athlon64, 2230 CK_Athlon64SSE3, 2231 CK_AthlonFX, 2232 CK_K8, 2233 CK_K8SSE3, 2234 CK_Opteron, 2235 CK_OpteronSSE3, 2236 CK_AMDFAM10, 2237 //@} 2238 2239 /// \name Bobcat 2240 /// Bobcat architecture processors. 2241 //@{ 2242 CK_BTVER1, 2243 CK_BTVER2, 2244 //@} 2245 2246 /// \name Bulldozer 2247 /// Bulldozer architecture processors. 2248 //@{ 2249 CK_BDVER1, 2250 CK_BDVER2, 2251 CK_BDVER3, 2252 CK_BDVER4, 2253 //@} 2254 2255 /// This specification is deprecated and will be removed in the future. 2256 /// Users should prefer \see CK_K8. 2257 // FIXME: Warn on this when the CPU is set to it. 2258 //@{ 2259 CK_x86_64, 2260 //@} 2261 2262 /// \name Geode 2263 /// Geode processors. 2264 //@{ 2265 CK_Geode 2266 //@} 2267 } CPU = CK_Generic; 2268 2269 CPUKind getCPUKind(StringRef CPU) const { 2270 return llvm::StringSwitch<CPUKind>(CPU) 2271 .Case("i386", CK_i386) 2272 .Case("i486", CK_i486) 2273 .Case("winchip-c6", CK_WinChipC6) 2274 .Case("winchip2", CK_WinChip2) 2275 .Case("c3", CK_C3) 2276 .Case("i586", CK_i586) 2277 .Case("pentium", CK_Pentium) 2278 .Case("pentium-mmx", CK_PentiumMMX) 2279 .Case("i686", CK_i686) 2280 .Case("pentiumpro", CK_PentiumPro) 2281 .Case("pentium2", CK_Pentium2) 2282 .Case("pentium3", CK_Pentium3) 2283 .Case("pentium3m", CK_Pentium3M) 2284 .Case("pentium-m", CK_PentiumM) 2285 .Case("c3-2", CK_C3_2) 2286 .Case("yonah", CK_Yonah) 2287 .Case("pentium4", CK_Pentium4) 2288 .Case("pentium4m", CK_Pentium4M) 2289 .Case("prescott", CK_Prescott) 2290 .Case("nocona", CK_Nocona) 2291 .Case("core2", CK_Core2) 2292 .Case("penryn", CK_Penryn) 2293 .Case("bonnell", CK_Bonnell) 2294 .Case("atom", CK_Bonnell) // Legacy name. 2295 .Case("silvermont", CK_Silvermont) 2296 .Case("slm", CK_Silvermont) // Legacy name. 2297 .Case("nehalem", CK_Nehalem) 2298 .Case("corei7", CK_Nehalem) // Legacy name. 2299 .Case("westmere", CK_Westmere) 2300 .Case("sandybridge", CK_SandyBridge) 2301 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2302 .Case("ivybridge", CK_IvyBridge) 2303 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2304 .Case("haswell", CK_Haswell) 2305 .Case("core-avx2", CK_Haswell) // Legacy name. 2306 .Case("broadwell", CK_Broadwell) 2307 .Case("skylake", CK_Skylake) 2308 .Case("skx", CK_Skylake) // Legacy name. 2309 .Case("knl", CK_KNL) 2310 .Case("k6", CK_K6) 2311 .Case("k6-2", CK_K6_2) 2312 .Case("k6-3", CK_K6_3) 2313 .Case("athlon", CK_Athlon) 2314 .Case("athlon-tbird", CK_AthlonThunderbird) 2315 .Case("athlon-4", CK_Athlon4) 2316 .Case("athlon-xp", CK_AthlonXP) 2317 .Case("athlon-mp", CK_AthlonMP) 2318 .Case("athlon64", CK_Athlon64) 2319 .Case("athlon64-sse3", CK_Athlon64SSE3) 2320 .Case("athlon-fx", CK_AthlonFX) 2321 .Case("k8", CK_K8) 2322 .Case("k8-sse3", CK_K8SSE3) 2323 .Case("opteron", CK_Opteron) 2324 .Case("opteron-sse3", CK_OpteronSSE3) 2325 .Case("barcelona", CK_AMDFAM10) 2326 .Case("amdfam10", CK_AMDFAM10) 2327 .Case("btver1", CK_BTVER1) 2328 .Case("btver2", CK_BTVER2) 2329 .Case("bdver1", CK_BDVER1) 2330 .Case("bdver2", CK_BDVER2) 2331 .Case("bdver3", CK_BDVER3) 2332 .Case("bdver4", CK_BDVER4) 2333 .Case("x86-64", CK_x86_64) 2334 .Case("geode", CK_Geode) 2335 .Default(CK_Generic); 2336 } 2337 2338 enum FPMathKind { 2339 FP_Default, 2340 FP_SSE, 2341 FP_387 2342 } FPMath = FP_Default; 2343 2344 public: 2345 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 2346 BigEndian = false; 2347 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2348 } 2349 unsigned getFloatEvalMethod() const override { 2350 // X87 evaluates with 80 bits "long double" precision. 2351 return SSELevel == NoSSE ? 2 : 0; 2352 } 2353 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2354 return llvm::makeArrayRef(BuiltinInfo, 2355 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2356 } 2357 ArrayRef<const char *> getGCCRegNames() const override { 2358 return llvm::makeArrayRef(GCCRegNames); 2359 } 2360 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2361 return None; 2362 } 2363 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2364 return llvm::makeArrayRef(AddlRegNames); 2365 } 2366 bool validateCpuSupports(StringRef Name) const override; 2367 bool validateAsmConstraint(const char *&Name, 2368 TargetInfo::ConstraintInfo &info) const override; 2369 2370 bool validateGlobalRegisterVariable(StringRef RegName, 2371 unsigned RegSize, 2372 bool &HasSizeMismatch) const override { 2373 // esp and ebp are the only 32-bit registers the x86 backend can currently 2374 // handle. 2375 if (RegName.equals("esp") || RegName.equals("ebp")) { 2376 // Check that the register size is 32-bit. 2377 HasSizeMismatch = RegSize != 32; 2378 return true; 2379 } 2380 2381 return false; 2382 } 2383 2384 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2385 2386 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2387 2388 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2389 2390 std::string convertConstraint(const char *&Constraint) const override; 2391 const char *getClobbers() const override { 2392 return "~{dirflag},~{fpsr},~{flags}"; 2393 } 2394 void getTargetDefines(const LangOptions &Opts, 2395 MacroBuilder &Builder) const override; 2396 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2397 bool Enabled); 2398 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2399 bool Enabled); 2400 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2401 bool Enabled); 2402 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2403 StringRef Name, bool Enabled) const override { 2404 setFeatureEnabledImpl(Features, Name, Enabled); 2405 } 2406 // This exists purely to cut down on the number of virtual calls in 2407 // initFeatureMap which calls this repeatedly. 2408 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2409 StringRef Name, bool Enabled); 2410 bool 2411 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2412 StringRef CPU, 2413 const std::vector<std::string> &FeaturesVec) const override; 2414 bool hasFeature(StringRef Feature) const override; 2415 bool handleTargetFeatures(std::vector<std::string> &Features, 2416 DiagnosticsEngine &Diags) override; 2417 StringRef getABI() const override { 2418 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2419 return "avx512"; 2420 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2421 return "avx"; 2422 if (getTriple().getArch() == llvm::Triple::x86 && 2423 MMX3DNowLevel == NoMMX3DNow) 2424 return "no-mmx"; 2425 return ""; 2426 } 2427 bool setCPU(const std::string &Name) override { 2428 CPU = getCPUKind(Name); 2429 2430 // Perform any per-CPU checks necessary to determine if this CPU is 2431 // acceptable. 2432 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2433 // invalid without explaining *why*. 2434 switch (CPU) { 2435 case CK_Generic: 2436 // No processor selected! 2437 return false; 2438 2439 case CK_i386: 2440 case CK_i486: 2441 case CK_WinChipC6: 2442 case CK_WinChip2: 2443 case CK_C3: 2444 case CK_i586: 2445 case CK_Pentium: 2446 case CK_PentiumMMX: 2447 case CK_i686: 2448 case CK_PentiumPro: 2449 case CK_Pentium2: 2450 case CK_Pentium3: 2451 case CK_Pentium3M: 2452 case CK_PentiumM: 2453 case CK_Yonah: 2454 case CK_C3_2: 2455 case CK_Pentium4: 2456 case CK_Pentium4M: 2457 case CK_Prescott: 2458 case CK_K6: 2459 case CK_K6_2: 2460 case CK_K6_3: 2461 case CK_Athlon: 2462 case CK_AthlonThunderbird: 2463 case CK_Athlon4: 2464 case CK_AthlonXP: 2465 case CK_AthlonMP: 2466 case CK_Geode: 2467 // Only accept certain architectures when compiling in 32-bit mode. 2468 if (getTriple().getArch() != llvm::Triple::x86) 2469 return false; 2470 2471 // Fallthrough 2472 case CK_Nocona: 2473 case CK_Core2: 2474 case CK_Penryn: 2475 case CK_Bonnell: 2476 case CK_Silvermont: 2477 case CK_Nehalem: 2478 case CK_Westmere: 2479 case CK_SandyBridge: 2480 case CK_IvyBridge: 2481 case CK_Haswell: 2482 case CK_Broadwell: 2483 case CK_Skylake: 2484 case CK_KNL: 2485 case CK_Athlon64: 2486 case CK_Athlon64SSE3: 2487 case CK_AthlonFX: 2488 case CK_K8: 2489 case CK_K8SSE3: 2490 case CK_Opteron: 2491 case CK_OpteronSSE3: 2492 case CK_AMDFAM10: 2493 case CK_BTVER1: 2494 case CK_BTVER2: 2495 case CK_BDVER1: 2496 case CK_BDVER2: 2497 case CK_BDVER3: 2498 case CK_BDVER4: 2499 case CK_x86_64: 2500 return true; 2501 } 2502 llvm_unreachable("Unhandled CPU kind"); 2503 } 2504 2505 bool setFPMath(StringRef Name) override; 2506 2507 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2508 // We accept all non-ARM calling conventions 2509 return (CC == CC_X86ThisCall || 2510 CC == CC_X86FastCall || 2511 CC == CC_X86StdCall || 2512 CC == CC_X86VectorCall || 2513 CC == CC_C || 2514 CC == CC_X86Pascal || 2515 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2516 } 2517 2518 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2519 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2520 } 2521 2522 bool hasSjLjLowering() const override { 2523 return true; 2524 } 2525 }; 2526 2527 bool X86TargetInfo::setFPMath(StringRef Name) { 2528 if (Name == "387") { 2529 FPMath = FP_387; 2530 return true; 2531 } 2532 if (Name == "sse") { 2533 FPMath = FP_SSE; 2534 return true; 2535 } 2536 return false; 2537 } 2538 2539 bool X86TargetInfo::initFeatureMap( 2540 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2541 const std::vector<std::string> &FeaturesVec) const { 2542 // FIXME: This *really* should not be here. 2543 // X86_64 always has SSE2. 2544 if (getTriple().getArch() == llvm::Triple::x86_64) 2545 setFeatureEnabledImpl(Features, "sse2", true); 2546 2547 switch (getCPUKind(CPU)) { 2548 case CK_Generic: 2549 case CK_i386: 2550 case CK_i486: 2551 case CK_i586: 2552 case CK_Pentium: 2553 case CK_i686: 2554 case CK_PentiumPro: 2555 break; 2556 case CK_PentiumMMX: 2557 case CK_Pentium2: 2558 case CK_K6: 2559 case CK_WinChipC6: 2560 setFeatureEnabledImpl(Features, "mmx", true); 2561 break; 2562 case CK_Pentium3: 2563 case CK_Pentium3M: 2564 case CK_C3_2: 2565 setFeatureEnabledImpl(Features, "sse", true); 2566 setFeatureEnabledImpl(Features, "fxsr", true); 2567 break; 2568 case CK_PentiumM: 2569 case CK_Pentium4: 2570 case CK_Pentium4M: 2571 case CK_x86_64: 2572 setFeatureEnabledImpl(Features, "sse2", true); 2573 setFeatureEnabledImpl(Features, "fxsr", true); 2574 break; 2575 case CK_Yonah: 2576 case CK_Prescott: 2577 case CK_Nocona: 2578 setFeatureEnabledImpl(Features, "sse3", true); 2579 setFeatureEnabledImpl(Features, "fxsr", true); 2580 setFeatureEnabledImpl(Features, "cx16", true); 2581 break; 2582 case CK_Core2: 2583 case CK_Bonnell: 2584 setFeatureEnabledImpl(Features, "ssse3", true); 2585 setFeatureEnabledImpl(Features, "fxsr", true); 2586 setFeatureEnabledImpl(Features, "cx16", true); 2587 break; 2588 case CK_Penryn: 2589 setFeatureEnabledImpl(Features, "sse4.1", true); 2590 setFeatureEnabledImpl(Features, "fxsr", true); 2591 setFeatureEnabledImpl(Features, "cx16", true); 2592 break; 2593 case CK_Skylake: 2594 setFeatureEnabledImpl(Features, "avx512f", true); 2595 setFeatureEnabledImpl(Features, "avx512cd", true); 2596 setFeatureEnabledImpl(Features, "avx512dq", true); 2597 setFeatureEnabledImpl(Features, "avx512bw", true); 2598 setFeatureEnabledImpl(Features, "avx512vl", true); 2599 setFeatureEnabledImpl(Features, "xsavec", true); 2600 setFeatureEnabledImpl(Features, "xsaves", true); 2601 setFeatureEnabledImpl(Features, "pku", true); 2602 // FALLTHROUGH 2603 case CK_Broadwell: 2604 setFeatureEnabledImpl(Features, "rdseed", true); 2605 setFeatureEnabledImpl(Features, "adx", true); 2606 // FALLTHROUGH 2607 case CK_Haswell: 2608 setFeatureEnabledImpl(Features, "avx2", true); 2609 setFeatureEnabledImpl(Features, "lzcnt", true); 2610 setFeatureEnabledImpl(Features, "bmi", true); 2611 setFeatureEnabledImpl(Features, "bmi2", true); 2612 setFeatureEnabledImpl(Features, "rtm", true); 2613 setFeatureEnabledImpl(Features, "fma", true); 2614 // FALLTHROUGH 2615 case CK_IvyBridge: 2616 setFeatureEnabledImpl(Features, "rdrnd", true); 2617 setFeatureEnabledImpl(Features, "f16c", true); 2618 setFeatureEnabledImpl(Features, "fsgsbase", true); 2619 // FALLTHROUGH 2620 case CK_SandyBridge: 2621 setFeatureEnabledImpl(Features, "avx", true); 2622 setFeatureEnabledImpl(Features, "xsave", true); 2623 setFeatureEnabledImpl(Features, "xsaveopt", true); 2624 // FALLTHROUGH 2625 case CK_Westmere: 2626 case CK_Silvermont: 2627 setFeatureEnabledImpl(Features, "aes", true); 2628 setFeatureEnabledImpl(Features, "pclmul", true); 2629 // FALLTHROUGH 2630 case CK_Nehalem: 2631 setFeatureEnabledImpl(Features, "sse4.2", true); 2632 setFeatureEnabledImpl(Features, "fxsr", true); 2633 setFeatureEnabledImpl(Features, "cx16", true); 2634 break; 2635 case CK_KNL: 2636 setFeatureEnabledImpl(Features, "avx512f", true); 2637 setFeatureEnabledImpl(Features, "avx512cd", true); 2638 setFeatureEnabledImpl(Features, "avx512er", true); 2639 setFeatureEnabledImpl(Features, "avx512pf", true); 2640 setFeatureEnabledImpl(Features, "fxsr", true); 2641 setFeatureEnabledImpl(Features, "rdseed", true); 2642 setFeatureEnabledImpl(Features, "adx", true); 2643 setFeatureEnabledImpl(Features, "lzcnt", true); 2644 setFeatureEnabledImpl(Features, "bmi", true); 2645 setFeatureEnabledImpl(Features, "bmi2", true); 2646 setFeatureEnabledImpl(Features, "rtm", true); 2647 setFeatureEnabledImpl(Features, "fma", true); 2648 setFeatureEnabledImpl(Features, "rdrnd", true); 2649 setFeatureEnabledImpl(Features, "f16c", true); 2650 setFeatureEnabledImpl(Features, "fsgsbase", true); 2651 setFeatureEnabledImpl(Features, "aes", true); 2652 setFeatureEnabledImpl(Features, "pclmul", true); 2653 setFeatureEnabledImpl(Features, "cx16", true); 2654 setFeatureEnabledImpl(Features, "xsaveopt", true); 2655 setFeatureEnabledImpl(Features, "xsave", true); 2656 break; 2657 case CK_K6_2: 2658 case CK_K6_3: 2659 case CK_WinChip2: 2660 case CK_C3: 2661 setFeatureEnabledImpl(Features, "3dnow", true); 2662 break; 2663 case CK_Athlon: 2664 case CK_AthlonThunderbird: 2665 case CK_Geode: 2666 setFeatureEnabledImpl(Features, "3dnowa", true); 2667 break; 2668 case CK_Athlon4: 2669 case CK_AthlonXP: 2670 case CK_AthlonMP: 2671 setFeatureEnabledImpl(Features, "sse", true); 2672 setFeatureEnabledImpl(Features, "3dnowa", true); 2673 setFeatureEnabledImpl(Features, "fxsr", true); 2674 break; 2675 case CK_K8: 2676 case CK_Opteron: 2677 case CK_Athlon64: 2678 case CK_AthlonFX: 2679 setFeatureEnabledImpl(Features, "sse2", true); 2680 setFeatureEnabledImpl(Features, "3dnowa", true); 2681 setFeatureEnabledImpl(Features, "fxsr", true); 2682 break; 2683 case CK_AMDFAM10: 2684 setFeatureEnabledImpl(Features, "sse4a", true); 2685 setFeatureEnabledImpl(Features, "lzcnt", true); 2686 setFeatureEnabledImpl(Features, "popcnt", true); 2687 // FALLTHROUGH 2688 case CK_K8SSE3: 2689 case CK_OpteronSSE3: 2690 case CK_Athlon64SSE3: 2691 setFeatureEnabledImpl(Features, "sse3", true); 2692 setFeatureEnabledImpl(Features, "3dnowa", true); 2693 setFeatureEnabledImpl(Features, "fxsr", true); 2694 break; 2695 case CK_BTVER2: 2696 setFeatureEnabledImpl(Features, "avx", true); 2697 setFeatureEnabledImpl(Features, "aes", true); 2698 setFeatureEnabledImpl(Features, "pclmul", true); 2699 setFeatureEnabledImpl(Features, "bmi", true); 2700 setFeatureEnabledImpl(Features, "f16c", true); 2701 setFeatureEnabledImpl(Features, "xsaveopt", true); 2702 // FALLTHROUGH 2703 case CK_BTVER1: 2704 setFeatureEnabledImpl(Features, "ssse3", true); 2705 setFeatureEnabledImpl(Features, "sse4a", true); 2706 setFeatureEnabledImpl(Features, "lzcnt", true); 2707 setFeatureEnabledImpl(Features, "popcnt", true); 2708 setFeatureEnabledImpl(Features, "prfchw", true); 2709 setFeatureEnabledImpl(Features, "cx16", true); 2710 setFeatureEnabledImpl(Features, "fxsr", true); 2711 setFeatureEnabledImpl(Features, "xsave", true); 2712 break; 2713 case CK_BDVER4: 2714 setFeatureEnabledImpl(Features, "avx2", true); 2715 setFeatureEnabledImpl(Features, "bmi2", true); 2716 // FALLTHROUGH 2717 case CK_BDVER3: 2718 setFeatureEnabledImpl(Features, "fsgsbase", true); 2719 setFeatureEnabledImpl(Features, "xsaveopt", true); 2720 // FALLTHROUGH 2721 case CK_BDVER2: 2722 setFeatureEnabledImpl(Features, "bmi", true); 2723 setFeatureEnabledImpl(Features, "fma", true); 2724 setFeatureEnabledImpl(Features, "f16c", true); 2725 setFeatureEnabledImpl(Features, "tbm", true); 2726 // FALLTHROUGH 2727 case CK_BDVER1: 2728 // xop implies avx, sse4a and fma4. 2729 setFeatureEnabledImpl(Features, "xop", true); 2730 setFeatureEnabledImpl(Features, "lzcnt", true); 2731 setFeatureEnabledImpl(Features, "aes", true); 2732 setFeatureEnabledImpl(Features, "pclmul", true); 2733 setFeatureEnabledImpl(Features, "prfchw", true); 2734 setFeatureEnabledImpl(Features, "cx16", true); 2735 setFeatureEnabledImpl(Features, "fxsr", true); 2736 setFeatureEnabledImpl(Features, "xsave", true); 2737 break; 2738 } 2739 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2740 return false; 2741 2742 // Can't do this earlier because we need to be able to explicitly enable 2743 // or disable these features and the things that they depend upon. 2744 2745 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2746 auto I = Features.find("sse4.2"); 2747 if (I != Features.end() && I->getValue() && 2748 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2749 FeaturesVec.end()) 2750 Features["popcnt"] = true; 2751 2752 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2753 I = Features.find("3dnow"); 2754 if (I != Features.end() && I->getValue() && 2755 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2756 FeaturesVec.end()) 2757 Features["prfchw"] = true; 2758 2759 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2760 // then enable MMX. 2761 I = Features.find("sse"); 2762 if (I != Features.end() && I->getValue() && 2763 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2764 FeaturesVec.end()) 2765 Features["mmx"] = true; 2766 2767 return true; 2768 } 2769 2770 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2771 X86SSEEnum Level, bool Enabled) { 2772 if (Enabled) { 2773 switch (Level) { 2774 case AVX512F: 2775 Features["avx512f"] = true; 2776 case AVX2: 2777 Features["avx2"] = true; 2778 case AVX: 2779 Features["avx"] = true; 2780 Features["xsave"] = true; 2781 case SSE42: 2782 Features["sse4.2"] = true; 2783 case SSE41: 2784 Features["sse4.1"] = true; 2785 case SSSE3: 2786 Features["ssse3"] = true; 2787 case SSE3: 2788 Features["sse3"] = true; 2789 case SSE2: 2790 Features["sse2"] = true; 2791 case SSE1: 2792 Features["sse"] = true; 2793 case NoSSE: 2794 break; 2795 } 2796 return; 2797 } 2798 2799 switch (Level) { 2800 case NoSSE: 2801 case SSE1: 2802 Features["sse"] = false; 2803 case SSE2: 2804 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2805 Features["sha"] = false; 2806 case SSE3: 2807 Features["sse3"] = false; 2808 setXOPLevel(Features, NoXOP, false); 2809 case SSSE3: 2810 Features["ssse3"] = false; 2811 case SSE41: 2812 Features["sse4.1"] = false; 2813 case SSE42: 2814 Features["sse4.2"] = false; 2815 case AVX: 2816 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2817 Features["xsaveopt"] = false; 2818 setXOPLevel(Features, FMA4, false); 2819 case AVX2: 2820 Features["avx2"] = false; 2821 case AVX512F: 2822 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2823 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2824 Features["avx512vl"] = false; 2825 } 2826 } 2827 2828 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2829 MMX3DNowEnum Level, bool Enabled) { 2830 if (Enabled) { 2831 switch (Level) { 2832 case AMD3DNowAthlon: 2833 Features["3dnowa"] = true; 2834 case AMD3DNow: 2835 Features["3dnow"] = true; 2836 case MMX: 2837 Features["mmx"] = true; 2838 case NoMMX3DNow: 2839 break; 2840 } 2841 return; 2842 } 2843 2844 switch (Level) { 2845 case NoMMX3DNow: 2846 case MMX: 2847 Features["mmx"] = false; 2848 case AMD3DNow: 2849 Features["3dnow"] = false; 2850 case AMD3DNowAthlon: 2851 Features["3dnowa"] = false; 2852 } 2853 } 2854 2855 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2856 bool Enabled) { 2857 if (Enabled) { 2858 switch (Level) { 2859 case XOP: 2860 Features["xop"] = true; 2861 case FMA4: 2862 Features["fma4"] = true; 2863 setSSELevel(Features, AVX, true); 2864 case SSE4A: 2865 Features["sse4a"] = true; 2866 setSSELevel(Features, SSE3, true); 2867 case NoXOP: 2868 break; 2869 } 2870 return; 2871 } 2872 2873 switch (Level) { 2874 case NoXOP: 2875 case SSE4A: 2876 Features["sse4a"] = false; 2877 case FMA4: 2878 Features["fma4"] = false; 2879 case XOP: 2880 Features["xop"] = false; 2881 } 2882 } 2883 2884 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2885 StringRef Name, bool Enabled) { 2886 // This is a bit of a hack to deal with the sse4 target feature when used 2887 // as part of the target attribute. We handle sse4 correctly everywhere 2888 // else. See below for more information on how we handle the sse4 options. 2889 if (Name != "sse4") 2890 Features[Name] = Enabled; 2891 2892 if (Name == "mmx") { 2893 setMMXLevel(Features, MMX, Enabled); 2894 } else if (Name == "sse") { 2895 setSSELevel(Features, SSE1, Enabled); 2896 } else if (Name == "sse2") { 2897 setSSELevel(Features, SSE2, Enabled); 2898 } else if (Name == "sse3") { 2899 setSSELevel(Features, SSE3, Enabled); 2900 } else if (Name == "ssse3") { 2901 setSSELevel(Features, SSSE3, Enabled); 2902 } else if (Name == "sse4.2") { 2903 setSSELevel(Features, SSE42, Enabled); 2904 } else if (Name == "sse4.1") { 2905 setSSELevel(Features, SSE41, Enabled); 2906 } else if (Name == "3dnow") { 2907 setMMXLevel(Features, AMD3DNow, Enabled); 2908 } else if (Name == "3dnowa") { 2909 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2910 } else if (Name == "aes") { 2911 if (Enabled) 2912 setSSELevel(Features, SSE2, Enabled); 2913 } else if (Name == "pclmul") { 2914 if (Enabled) 2915 setSSELevel(Features, SSE2, Enabled); 2916 } else if (Name == "avx") { 2917 setSSELevel(Features, AVX, Enabled); 2918 } else if (Name == "avx2") { 2919 setSSELevel(Features, AVX2, Enabled); 2920 } else if (Name == "avx512f") { 2921 setSSELevel(Features, AVX512F, Enabled); 2922 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2923 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2924 if (Enabled) 2925 setSSELevel(Features, AVX512F, Enabled); 2926 } else if (Name == "fma") { 2927 if (Enabled) 2928 setSSELevel(Features, AVX, Enabled); 2929 } else if (Name == "fma4") { 2930 setXOPLevel(Features, FMA4, Enabled); 2931 } else if (Name == "xop") { 2932 setXOPLevel(Features, XOP, Enabled); 2933 } else if (Name == "sse4a") { 2934 setXOPLevel(Features, SSE4A, Enabled); 2935 } else if (Name == "f16c") { 2936 if (Enabled) 2937 setSSELevel(Features, AVX, Enabled); 2938 } else if (Name == "sha") { 2939 if (Enabled) 2940 setSSELevel(Features, SSE2, Enabled); 2941 } else if (Name == "sse4") { 2942 // We can get here via the __target__ attribute since that's not controlled 2943 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2944 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2945 // disabled. 2946 if (Enabled) 2947 setSSELevel(Features, SSE42, Enabled); 2948 else 2949 setSSELevel(Features, SSE41, Enabled); 2950 } else if (Name == "xsave") { 2951 if (Enabled) 2952 setSSELevel(Features, AVX, Enabled); 2953 else 2954 Features["xsaveopt"] = false; 2955 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 2956 if (Enabled) { 2957 Features["xsave"] = true; 2958 setSSELevel(Features, AVX, Enabled); 2959 } 2960 } 2961 } 2962 2963 /// handleTargetFeatures - Perform initialization based on the user 2964 /// configured set of features. 2965 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2966 DiagnosticsEngine &Diags) { 2967 for (const auto &Feature : Features) { 2968 if (Feature[0] != '+') 2969 continue; 2970 2971 if (Feature == "+aes") { 2972 HasAES = true; 2973 } else if (Feature == "+pclmul") { 2974 HasPCLMUL = true; 2975 } else if (Feature == "+lzcnt") { 2976 HasLZCNT = true; 2977 } else if (Feature == "+rdrnd") { 2978 HasRDRND = true; 2979 } else if (Feature == "+fsgsbase") { 2980 HasFSGSBASE = true; 2981 } else if (Feature == "+bmi") { 2982 HasBMI = true; 2983 } else if (Feature == "+bmi2") { 2984 HasBMI2 = true; 2985 } else if (Feature == "+popcnt") { 2986 HasPOPCNT = true; 2987 } else if (Feature == "+rtm") { 2988 HasRTM = true; 2989 } else if (Feature == "+prfchw") { 2990 HasPRFCHW = true; 2991 } else if (Feature == "+rdseed") { 2992 HasRDSEED = true; 2993 } else if (Feature == "+adx") { 2994 HasADX = true; 2995 } else if (Feature == "+tbm") { 2996 HasTBM = true; 2997 } else if (Feature == "+fma") { 2998 HasFMA = true; 2999 } else if (Feature == "+f16c") { 3000 HasF16C = true; 3001 } else if (Feature == "+avx512cd") { 3002 HasAVX512CD = true; 3003 } else if (Feature == "+avx512er") { 3004 HasAVX512ER = true; 3005 } else if (Feature == "+avx512pf") { 3006 HasAVX512PF = true; 3007 } else if (Feature == "+avx512dq") { 3008 HasAVX512DQ = true; 3009 } else if (Feature == "+avx512bw") { 3010 HasAVX512BW = true; 3011 } else if (Feature == "+avx512vl") { 3012 HasAVX512VL = true; 3013 } else if (Feature == "+sha") { 3014 HasSHA = true; 3015 } else if (Feature == "+cx16") { 3016 HasCX16 = true; 3017 } else if (Feature == "+fxsr") { 3018 HasFXSR = true; 3019 } else if (Feature == "+xsave") { 3020 HasXSAVE = true; 3021 } else if (Feature == "+xsaveopt") { 3022 HasXSAVEOPT = true; 3023 } else if (Feature == "+xsavec") { 3024 HasXSAVEC = true; 3025 } else if (Feature == "+xsaves") { 3026 HasXSAVES = true; 3027 } else if (Feature == "+pku") { 3028 HasPKU = true; 3029 } 3030 3031 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3032 .Case("+avx512f", AVX512F) 3033 .Case("+avx2", AVX2) 3034 .Case("+avx", AVX) 3035 .Case("+sse4.2", SSE42) 3036 .Case("+sse4.1", SSE41) 3037 .Case("+ssse3", SSSE3) 3038 .Case("+sse3", SSE3) 3039 .Case("+sse2", SSE2) 3040 .Case("+sse", SSE1) 3041 .Default(NoSSE); 3042 SSELevel = std::max(SSELevel, Level); 3043 3044 MMX3DNowEnum ThreeDNowLevel = 3045 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3046 .Case("+3dnowa", AMD3DNowAthlon) 3047 .Case("+3dnow", AMD3DNow) 3048 .Case("+mmx", MMX) 3049 .Default(NoMMX3DNow); 3050 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3051 3052 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3053 .Case("+xop", XOP) 3054 .Case("+fma4", FMA4) 3055 .Case("+sse4a", SSE4A) 3056 .Default(NoXOP); 3057 XOPLevel = std::max(XOPLevel, XLevel); 3058 } 3059 3060 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3061 // matches the selected sse level. 3062 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3063 (FPMath == FP_387 && SSELevel >= SSE1)) { 3064 Diags.Report(diag::err_target_unsupported_fpmath) << 3065 (FPMath == FP_SSE ? "sse" : "387"); 3066 return false; 3067 } 3068 3069 SimdDefaultAlign = 3070 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3071 return true; 3072 } 3073 3074 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3075 /// definitions for this particular subtarget. 3076 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3077 MacroBuilder &Builder) const { 3078 // Target identification. 3079 if (getTriple().getArch() == llvm::Triple::x86_64) { 3080 Builder.defineMacro("__amd64__"); 3081 Builder.defineMacro("__amd64"); 3082 Builder.defineMacro("__x86_64"); 3083 Builder.defineMacro("__x86_64__"); 3084 if (getTriple().getArchName() == "x86_64h") { 3085 Builder.defineMacro("__x86_64h"); 3086 Builder.defineMacro("__x86_64h__"); 3087 } 3088 } else { 3089 DefineStd(Builder, "i386", Opts); 3090 } 3091 3092 // Subtarget options. 3093 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3094 // truly should be based on -mtune options. 3095 switch (CPU) { 3096 case CK_Generic: 3097 break; 3098 case CK_i386: 3099 // The rest are coming from the i386 define above. 3100 Builder.defineMacro("__tune_i386__"); 3101 break; 3102 case CK_i486: 3103 case CK_WinChipC6: 3104 case CK_WinChip2: 3105 case CK_C3: 3106 defineCPUMacros(Builder, "i486"); 3107 break; 3108 case CK_PentiumMMX: 3109 Builder.defineMacro("__pentium_mmx__"); 3110 Builder.defineMacro("__tune_pentium_mmx__"); 3111 // Fallthrough 3112 case CK_i586: 3113 case CK_Pentium: 3114 defineCPUMacros(Builder, "i586"); 3115 defineCPUMacros(Builder, "pentium"); 3116 break; 3117 case CK_Pentium3: 3118 case CK_Pentium3M: 3119 case CK_PentiumM: 3120 Builder.defineMacro("__tune_pentium3__"); 3121 // Fallthrough 3122 case CK_Pentium2: 3123 case CK_C3_2: 3124 Builder.defineMacro("__tune_pentium2__"); 3125 // Fallthrough 3126 case CK_PentiumPro: 3127 Builder.defineMacro("__tune_i686__"); 3128 Builder.defineMacro("__tune_pentiumpro__"); 3129 // Fallthrough 3130 case CK_i686: 3131 Builder.defineMacro("__i686"); 3132 Builder.defineMacro("__i686__"); 3133 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3134 Builder.defineMacro("__pentiumpro"); 3135 Builder.defineMacro("__pentiumpro__"); 3136 break; 3137 case CK_Pentium4: 3138 case CK_Pentium4M: 3139 defineCPUMacros(Builder, "pentium4"); 3140 break; 3141 case CK_Yonah: 3142 case CK_Prescott: 3143 case CK_Nocona: 3144 defineCPUMacros(Builder, "nocona"); 3145 break; 3146 case CK_Core2: 3147 case CK_Penryn: 3148 defineCPUMacros(Builder, "core2"); 3149 break; 3150 case CK_Bonnell: 3151 defineCPUMacros(Builder, "atom"); 3152 break; 3153 case CK_Silvermont: 3154 defineCPUMacros(Builder, "slm"); 3155 break; 3156 case CK_Nehalem: 3157 case CK_Westmere: 3158 case CK_SandyBridge: 3159 case CK_IvyBridge: 3160 case CK_Haswell: 3161 case CK_Broadwell: 3162 // FIXME: Historically, we defined this legacy name, it would be nice to 3163 // remove it at some point. We've never exposed fine-grained names for 3164 // recent primary x86 CPUs, and we should keep it that way. 3165 defineCPUMacros(Builder, "corei7"); 3166 break; 3167 case CK_Skylake: 3168 // FIXME: Historically, we defined this legacy name, it would be nice to 3169 // remove it at some point. This is the only fine-grained CPU macro in the 3170 // main intel CPU line, and it would be better to not have these and force 3171 // people to use ISA macros. 3172 defineCPUMacros(Builder, "skx"); 3173 break; 3174 case CK_KNL: 3175 defineCPUMacros(Builder, "knl"); 3176 break; 3177 case CK_K6_2: 3178 Builder.defineMacro("__k6_2__"); 3179 Builder.defineMacro("__tune_k6_2__"); 3180 // Fallthrough 3181 case CK_K6_3: 3182 if (CPU != CK_K6_2) { // In case of fallthrough 3183 // FIXME: GCC may be enabling these in cases where some other k6 3184 // architecture is specified but -m3dnow is explicitly provided. The 3185 // exact semantics need to be determined and emulated here. 3186 Builder.defineMacro("__k6_3__"); 3187 Builder.defineMacro("__tune_k6_3__"); 3188 } 3189 // Fallthrough 3190 case CK_K6: 3191 defineCPUMacros(Builder, "k6"); 3192 break; 3193 case CK_Athlon: 3194 case CK_AthlonThunderbird: 3195 case CK_Athlon4: 3196 case CK_AthlonXP: 3197 case CK_AthlonMP: 3198 defineCPUMacros(Builder, "athlon"); 3199 if (SSELevel != NoSSE) { 3200 Builder.defineMacro("__athlon_sse__"); 3201 Builder.defineMacro("__tune_athlon_sse__"); 3202 } 3203 break; 3204 case CK_K8: 3205 case CK_K8SSE3: 3206 case CK_x86_64: 3207 case CK_Opteron: 3208 case CK_OpteronSSE3: 3209 case CK_Athlon64: 3210 case CK_Athlon64SSE3: 3211 case CK_AthlonFX: 3212 defineCPUMacros(Builder, "k8"); 3213 break; 3214 case CK_AMDFAM10: 3215 defineCPUMacros(Builder, "amdfam10"); 3216 break; 3217 case CK_BTVER1: 3218 defineCPUMacros(Builder, "btver1"); 3219 break; 3220 case CK_BTVER2: 3221 defineCPUMacros(Builder, "btver2"); 3222 break; 3223 case CK_BDVER1: 3224 defineCPUMacros(Builder, "bdver1"); 3225 break; 3226 case CK_BDVER2: 3227 defineCPUMacros(Builder, "bdver2"); 3228 break; 3229 case CK_BDVER3: 3230 defineCPUMacros(Builder, "bdver3"); 3231 break; 3232 case CK_BDVER4: 3233 defineCPUMacros(Builder, "bdver4"); 3234 break; 3235 case CK_Geode: 3236 defineCPUMacros(Builder, "geode"); 3237 break; 3238 } 3239 3240 // Target properties. 3241 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3242 3243 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3244 // functions in glibc header files that use FP Stack inline asm which the 3245 // backend can't deal with (PR879). 3246 Builder.defineMacro("__NO_MATH_INLINES"); 3247 3248 if (HasAES) 3249 Builder.defineMacro("__AES__"); 3250 3251 if (HasPCLMUL) 3252 Builder.defineMacro("__PCLMUL__"); 3253 3254 if (HasLZCNT) 3255 Builder.defineMacro("__LZCNT__"); 3256 3257 if (HasRDRND) 3258 Builder.defineMacro("__RDRND__"); 3259 3260 if (HasFSGSBASE) 3261 Builder.defineMacro("__FSGSBASE__"); 3262 3263 if (HasBMI) 3264 Builder.defineMacro("__BMI__"); 3265 3266 if (HasBMI2) 3267 Builder.defineMacro("__BMI2__"); 3268 3269 if (HasPOPCNT) 3270 Builder.defineMacro("__POPCNT__"); 3271 3272 if (HasRTM) 3273 Builder.defineMacro("__RTM__"); 3274 3275 if (HasPRFCHW) 3276 Builder.defineMacro("__PRFCHW__"); 3277 3278 if (HasRDSEED) 3279 Builder.defineMacro("__RDSEED__"); 3280 3281 if (HasADX) 3282 Builder.defineMacro("__ADX__"); 3283 3284 if (HasTBM) 3285 Builder.defineMacro("__TBM__"); 3286 3287 switch (XOPLevel) { 3288 case XOP: 3289 Builder.defineMacro("__XOP__"); 3290 case FMA4: 3291 Builder.defineMacro("__FMA4__"); 3292 case SSE4A: 3293 Builder.defineMacro("__SSE4A__"); 3294 case NoXOP: 3295 break; 3296 } 3297 3298 if (HasFMA) 3299 Builder.defineMacro("__FMA__"); 3300 3301 if (HasF16C) 3302 Builder.defineMacro("__F16C__"); 3303 3304 if (HasAVX512CD) 3305 Builder.defineMacro("__AVX512CD__"); 3306 if (HasAVX512ER) 3307 Builder.defineMacro("__AVX512ER__"); 3308 if (HasAVX512PF) 3309 Builder.defineMacro("__AVX512PF__"); 3310 if (HasAVX512DQ) 3311 Builder.defineMacro("__AVX512DQ__"); 3312 if (HasAVX512BW) 3313 Builder.defineMacro("__AVX512BW__"); 3314 if (HasAVX512VL) 3315 Builder.defineMacro("__AVX512VL__"); 3316 3317 if (HasSHA) 3318 Builder.defineMacro("__SHA__"); 3319 3320 if (HasFXSR) 3321 Builder.defineMacro("__FXSR__"); 3322 if (HasXSAVE) 3323 Builder.defineMacro("__XSAVE__"); 3324 if (HasXSAVEOPT) 3325 Builder.defineMacro("__XSAVEOPT__"); 3326 if (HasXSAVEC) 3327 Builder.defineMacro("__XSAVEC__"); 3328 if (HasXSAVES) 3329 Builder.defineMacro("__XSAVES__"); 3330 if (HasPKU) 3331 Builder.defineMacro("__PKU__"); 3332 if (HasCX16) 3333 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3334 3335 // Each case falls through to the previous one here. 3336 switch (SSELevel) { 3337 case AVX512F: 3338 Builder.defineMacro("__AVX512F__"); 3339 case AVX2: 3340 Builder.defineMacro("__AVX2__"); 3341 case AVX: 3342 Builder.defineMacro("__AVX__"); 3343 case SSE42: 3344 Builder.defineMacro("__SSE4_2__"); 3345 case SSE41: 3346 Builder.defineMacro("__SSE4_1__"); 3347 case SSSE3: 3348 Builder.defineMacro("__SSSE3__"); 3349 case SSE3: 3350 Builder.defineMacro("__SSE3__"); 3351 case SSE2: 3352 Builder.defineMacro("__SSE2__"); 3353 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3354 case SSE1: 3355 Builder.defineMacro("__SSE__"); 3356 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3357 case NoSSE: 3358 break; 3359 } 3360 3361 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3362 switch (SSELevel) { 3363 case AVX512F: 3364 case AVX2: 3365 case AVX: 3366 case SSE42: 3367 case SSE41: 3368 case SSSE3: 3369 case SSE3: 3370 case SSE2: 3371 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3372 break; 3373 case SSE1: 3374 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3375 break; 3376 default: 3377 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3378 } 3379 } 3380 3381 // Each case falls through to the previous one here. 3382 switch (MMX3DNowLevel) { 3383 case AMD3DNowAthlon: 3384 Builder.defineMacro("__3dNOW_A__"); 3385 case AMD3DNow: 3386 Builder.defineMacro("__3dNOW__"); 3387 case MMX: 3388 Builder.defineMacro("__MMX__"); 3389 case NoMMX3DNow: 3390 break; 3391 } 3392 3393 if (CPU >= CK_i486) { 3394 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3395 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3397 } 3398 if (CPU >= CK_i586) 3399 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3400 } 3401 3402 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3403 return llvm::StringSwitch<bool>(Feature) 3404 .Case("aes", HasAES) 3405 .Case("avx", SSELevel >= AVX) 3406 .Case("avx2", SSELevel >= AVX2) 3407 .Case("avx512f", SSELevel >= AVX512F) 3408 .Case("avx512cd", HasAVX512CD) 3409 .Case("avx512er", HasAVX512ER) 3410 .Case("avx512pf", HasAVX512PF) 3411 .Case("avx512dq", HasAVX512DQ) 3412 .Case("avx512bw", HasAVX512BW) 3413 .Case("avx512vl", HasAVX512VL) 3414 .Case("bmi", HasBMI) 3415 .Case("bmi2", HasBMI2) 3416 .Case("cx16", HasCX16) 3417 .Case("f16c", HasF16C) 3418 .Case("fma", HasFMA) 3419 .Case("fma4", XOPLevel >= FMA4) 3420 .Case("fsgsbase", HasFSGSBASE) 3421 .Case("fxsr", HasFXSR) 3422 .Case("lzcnt", HasLZCNT) 3423 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3424 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3425 .Case("mmx", MMX3DNowLevel >= MMX) 3426 .Case("pclmul", HasPCLMUL) 3427 .Case("popcnt", HasPOPCNT) 3428 .Case("prfchw", HasPRFCHW) 3429 .Case("rdrnd", HasRDRND) 3430 .Case("rdseed", HasRDSEED) 3431 .Case("rtm", HasRTM) 3432 .Case("sha", HasSHA) 3433 .Case("sse", SSELevel >= SSE1) 3434 .Case("sse2", SSELevel >= SSE2) 3435 .Case("sse3", SSELevel >= SSE3) 3436 .Case("ssse3", SSELevel >= SSSE3) 3437 .Case("sse4.1", SSELevel >= SSE41) 3438 .Case("sse4.2", SSELevel >= SSE42) 3439 .Case("sse4a", XOPLevel >= SSE4A) 3440 .Case("tbm", HasTBM) 3441 .Case("x86", true) 3442 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3443 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3444 .Case("xop", XOPLevel >= XOP) 3445 .Case("xsave", HasXSAVE) 3446 .Case("xsavec", HasXSAVEC) 3447 .Case("xsaves", HasXSAVES) 3448 .Case("xsaveopt", HasXSAVEOPT) 3449 .Case("pku", HasPKU) 3450 .Default(false); 3451 } 3452 3453 // We can't use a generic validation scheme for the features accepted here 3454 // versus subtarget features accepted in the target attribute because the 3455 // bitfield structure that's initialized in the runtime only supports the 3456 // below currently rather than the full range of subtarget features. (See 3457 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3458 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3459 return llvm::StringSwitch<bool>(FeatureStr) 3460 .Case("cmov", true) 3461 .Case("mmx", true) 3462 .Case("popcnt", true) 3463 .Case("sse", true) 3464 .Case("sse2", true) 3465 .Case("sse3", true) 3466 .Case("sse4.1", true) 3467 .Case("sse4.2", true) 3468 .Case("avx", true) 3469 .Case("avx2", true) 3470 .Case("sse4a", true) 3471 .Case("fma4", true) 3472 .Case("xop", true) 3473 .Case("fma", true) 3474 .Case("avx512f", true) 3475 .Case("bmi", true) 3476 .Case("bmi2", true) 3477 .Default(false); 3478 } 3479 3480 bool 3481 X86TargetInfo::validateAsmConstraint(const char *&Name, 3482 TargetInfo::ConstraintInfo &Info) const { 3483 switch (*Name) { 3484 default: return false; 3485 // Constant constraints. 3486 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3487 // instructions. 3488 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3489 // x86_64 instructions. 3490 case 's': 3491 Info.setRequiresImmediate(); 3492 return true; 3493 case 'I': 3494 Info.setRequiresImmediate(0, 31); 3495 return true; 3496 case 'J': 3497 Info.setRequiresImmediate(0, 63); 3498 return true; 3499 case 'K': 3500 Info.setRequiresImmediate(-128, 127); 3501 return true; 3502 case 'L': 3503 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3504 return true; 3505 case 'M': 3506 Info.setRequiresImmediate(0, 3); 3507 return true; 3508 case 'N': 3509 Info.setRequiresImmediate(0, 255); 3510 return true; 3511 case 'O': 3512 Info.setRequiresImmediate(0, 127); 3513 return true; 3514 // Register constraints. 3515 case 'Y': // 'Y' is the first character for several 2-character constraints. 3516 // Shift the pointer to the second character of the constraint. 3517 Name++; 3518 switch (*Name) { 3519 default: 3520 return false; 3521 case '0': // First SSE register. 3522 case 't': // Any SSE register, when SSE2 is enabled. 3523 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3524 case 'm': // Any MMX register, when inter-unit moves enabled. 3525 Info.setAllowsRegister(); 3526 return true; 3527 } 3528 case 'f': // Any x87 floating point stack register. 3529 // Constraint 'f' cannot be used for output operands. 3530 if (Info.ConstraintStr[0] == '=') 3531 return false; 3532 Info.setAllowsRegister(); 3533 return true; 3534 case 'a': // eax. 3535 case 'b': // ebx. 3536 case 'c': // ecx. 3537 case 'd': // edx. 3538 case 'S': // esi. 3539 case 'D': // edi. 3540 case 'A': // edx:eax. 3541 case 't': // Top of floating point stack. 3542 case 'u': // Second from top of floating point stack. 3543 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3544 case 'y': // Any MMX register. 3545 case 'x': // Any SSE register. 3546 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3547 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3548 case 'l': // "Index" registers: any general register that can be used as an 3549 // index in a base+index memory access. 3550 Info.setAllowsRegister(); 3551 return true; 3552 // Floating point constant constraints. 3553 case 'C': // SSE floating point constant. 3554 case 'G': // x87 floating point constant. 3555 return true; 3556 } 3557 } 3558 3559 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3560 unsigned Size) const { 3561 // Strip off constraint modifiers. 3562 while (Constraint[0] == '=' || 3563 Constraint[0] == '+' || 3564 Constraint[0] == '&') 3565 Constraint = Constraint.substr(1); 3566 3567 return validateOperandSize(Constraint, Size); 3568 } 3569 3570 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3571 unsigned Size) const { 3572 return validateOperandSize(Constraint, Size); 3573 } 3574 3575 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3576 unsigned Size) const { 3577 switch (Constraint[0]) { 3578 default: break; 3579 case 'y': 3580 return Size <= 64; 3581 case 'f': 3582 case 't': 3583 case 'u': 3584 return Size <= 128; 3585 case 'x': 3586 if (SSELevel >= AVX512F) 3587 // 512-bit zmm registers can be used if target supports AVX512F. 3588 return Size <= 512U; 3589 else if (SSELevel >= AVX) 3590 // 256-bit ymm registers can be used if target supports AVX. 3591 return Size <= 256U; 3592 return Size <= 128U; 3593 case 'Y': 3594 // 'Y' is the first character for several 2-character constraints. 3595 switch (Constraint[1]) { 3596 default: break; 3597 case 'm': 3598 // 'Ym' is synonymous with 'y'. 3599 return Size <= 64; 3600 case 'i': 3601 case 't': 3602 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3603 if (SSELevel >= AVX512F) 3604 return Size <= 512U; 3605 else if (SSELevel >= AVX) 3606 return Size <= 256U; 3607 return SSELevel >= SSE2 && Size <= 128U; 3608 } 3609 3610 } 3611 3612 return true; 3613 } 3614 3615 std::string 3616 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3617 switch (*Constraint) { 3618 case 'a': return std::string("{ax}"); 3619 case 'b': return std::string("{bx}"); 3620 case 'c': return std::string("{cx}"); 3621 case 'd': return std::string("{dx}"); 3622 case 'S': return std::string("{si}"); 3623 case 'D': return std::string("{di}"); 3624 case 'p': // address 3625 return std::string("im"); 3626 case 't': // top of floating point stack. 3627 return std::string("{st}"); 3628 case 'u': // second from top of floating point stack. 3629 return std::string("{st(1)}"); // second from top of floating point stack. 3630 default: 3631 return std::string(1, *Constraint); 3632 } 3633 } 3634 3635 // X86-32 generic target 3636 class X86_32TargetInfo : public X86TargetInfo { 3637 public: 3638 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3639 DoubleAlign = LongLongAlign = 32; 3640 LongDoubleWidth = 96; 3641 LongDoubleAlign = 32; 3642 SuitableAlign = 128; 3643 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3644 SizeType = UnsignedInt; 3645 PtrDiffType = SignedInt; 3646 IntPtrType = SignedInt; 3647 RegParmMax = 3; 3648 3649 // Use fpret for all types. 3650 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3651 (1 << TargetInfo::Double) | 3652 (1 << TargetInfo::LongDouble)); 3653 3654 // x86-32 has atomics up to 8 bytes 3655 // FIXME: Check that we actually have cmpxchg8b before setting 3656 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3657 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3658 3659 UserLabelPrefix = "_"; 3660 } 3661 BuiltinVaListKind getBuiltinVaListKind() const override { 3662 return TargetInfo::CharPtrBuiltinVaList; 3663 } 3664 3665 int getEHDataRegisterNumber(unsigned RegNo) const override { 3666 if (RegNo == 0) return 0; 3667 if (RegNo == 1) return 2; 3668 return -1; 3669 } 3670 bool validateOperandSize(StringRef Constraint, 3671 unsigned Size) const override { 3672 switch (Constraint[0]) { 3673 default: break; 3674 case 'R': 3675 case 'q': 3676 case 'Q': 3677 case 'a': 3678 case 'b': 3679 case 'c': 3680 case 'd': 3681 case 'S': 3682 case 'D': 3683 return Size <= 32; 3684 case 'A': 3685 return Size <= 64; 3686 } 3687 3688 return X86TargetInfo::validateOperandSize(Constraint, Size); 3689 } 3690 }; 3691 3692 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3693 public: 3694 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3695 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3696 3697 unsigned getFloatEvalMethod() const override { 3698 unsigned Major, Minor, Micro; 3699 getTriple().getOSVersion(Major, Minor, Micro); 3700 // New NetBSD uses the default rounding mode. 3701 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3702 return X86_32TargetInfo::getFloatEvalMethod(); 3703 // NetBSD before 6.99.26 defaults to "double" rounding. 3704 return 1; 3705 } 3706 }; 3707 3708 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3709 public: 3710 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3711 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3712 SizeType = UnsignedLong; 3713 IntPtrType = SignedLong; 3714 PtrDiffType = SignedLong; 3715 } 3716 }; 3717 3718 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3719 public: 3720 BitrigI386TargetInfo(const llvm::Triple &Triple) 3721 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3722 SizeType = UnsignedLong; 3723 IntPtrType = SignedLong; 3724 PtrDiffType = SignedLong; 3725 } 3726 }; 3727 3728 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3729 public: 3730 DarwinI386TargetInfo(const llvm::Triple &Triple) 3731 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3732 LongDoubleWidth = 128; 3733 LongDoubleAlign = 128; 3734 SuitableAlign = 128; 3735 MaxVectorAlign = 256; 3736 // The watchOS simulator uses the builtin bool type for Objective-C. 3737 llvm::Triple T = llvm::Triple(Triple); 3738 if (T.isWatchOS()) 3739 UseSignedCharForObjCBool = false; 3740 SizeType = UnsignedLong; 3741 IntPtrType = SignedLong; 3742 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3743 HasAlignMac68kSupport = true; 3744 } 3745 3746 bool handleTargetFeatures(std::vector<std::string> &Features, 3747 DiagnosticsEngine &Diags) override { 3748 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3749 Diags)) 3750 return false; 3751 // We now know the features we have: we can decide how to align vectors. 3752 MaxVectorAlign = 3753 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3754 return true; 3755 } 3756 }; 3757 3758 // x86-32 Windows target 3759 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3760 public: 3761 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3762 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3763 WCharType = UnsignedShort; 3764 DoubleAlign = LongLongAlign = 64; 3765 bool IsWinCOFF = 3766 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3767 DataLayoutString = IsWinCOFF 3768 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3769 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3770 } 3771 void getTargetDefines(const LangOptions &Opts, 3772 MacroBuilder &Builder) const override { 3773 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3774 } 3775 }; 3776 3777 // x86-32 Windows Visual Studio target 3778 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3779 public: 3780 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3781 : WindowsX86_32TargetInfo(Triple) { 3782 LongDoubleWidth = LongDoubleAlign = 64; 3783 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3784 } 3785 void getTargetDefines(const LangOptions &Opts, 3786 MacroBuilder &Builder) const override { 3787 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3788 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3789 // The value of the following reflects processor type. 3790 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3791 // We lost the original triple, so we use the default. 3792 Builder.defineMacro("_M_IX86", "600"); 3793 } 3794 }; 3795 3796 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3797 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3798 // supports __declspec natively under -fms-extensions, but we define a no-op 3799 // __declspec macro anyway for pre-processor compatibility. 3800 if (Opts.MicrosoftExt) 3801 Builder.defineMacro("__declspec", "__declspec"); 3802 else 3803 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3804 3805 if (!Opts.MicrosoftExt) { 3806 // Provide macros for all the calling convention keywords. Provide both 3807 // single and double underscore prefixed variants. These are available on 3808 // x64 as well as x86, even though they have no effect. 3809 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3810 for (const char *CC : CCs) { 3811 std::string GCCSpelling = "__attribute__((__"; 3812 GCCSpelling += CC; 3813 GCCSpelling += "__))"; 3814 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3815 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3816 } 3817 } 3818 } 3819 3820 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3821 Builder.defineMacro("__MSVCRT__"); 3822 Builder.defineMacro("__MINGW32__"); 3823 addCygMingDefines(Opts, Builder); 3824 } 3825 3826 // x86-32 MinGW target 3827 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3828 public: 3829 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3830 : WindowsX86_32TargetInfo(Triple) {} 3831 void getTargetDefines(const LangOptions &Opts, 3832 MacroBuilder &Builder) const override { 3833 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3834 DefineStd(Builder, "WIN32", Opts); 3835 DefineStd(Builder, "WINNT", Opts); 3836 Builder.defineMacro("_X86_"); 3837 addMinGWDefines(Opts, Builder); 3838 } 3839 }; 3840 3841 // x86-32 Cygwin target 3842 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3843 public: 3844 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3845 : X86_32TargetInfo(Triple) { 3846 WCharType = UnsignedShort; 3847 DoubleAlign = LongLongAlign = 64; 3848 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3849 } 3850 void getTargetDefines(const LangOptions &Opts, 3851 MacroBuilder &Builder) const override { 3852 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3853 Builder.defineMacro("_X86_"); 3854 Builder.defineMacro("__CYGWIN__"); 3855 Builder.defineMacro("__CYGWIN32__"); 3856 addCygMingDefines(Opts, Builder); 3857 DefineStd(Builder, "unix", Opts); 3858 if (Opts.CPlusPlus) 3859 Builder.defineMacro("_GNU_SOURCE"); 3860 } 3861 }; 3862 3863 // x86-32 Haiku target 3864 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3865 public: 3866 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3867 SizeType = UnsignedLong; 3868 IntPtrType = SignedLong; 3869 PtrDiffType = SignedLong; 3870 ProcessIDType = SignedLong; 3871 this->TLSSupported = false; 3872 } 3873 void getTargetDefines(const LangOptions &Opts, 3874 MacroBuilder &Builder) const override { 3875 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3876 Builder.defineMacro("__INTEL__"); 3877 Builder.defineMacro("__HAIKU__"); 3878 } 3879 }; 3880 3881 // X86-32 MCU target 3882 class MCUX86_32TargetInfo : public X86_32TargetInfo { 3883 public: 3884 MCUX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3885 LongDoubleWidth = 64; 3886 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3887 UserLabelPrefix = ""; 3888 } 3889 3890 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3891 // On MCU we support only C calling convention. 3892 return CC == CC_C ? CCCR_OK : CCCR_Warning; 3893 } 3894 3895 void getTargetDefines(const LangOptions &Opts, 3896 MacroBuilder &Builder) const override { 3897 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3898 Builder.defineMacro("__iamcu"); 3899 Builder.defineMacro("__iamcu__"); 3900 } 3901 }; 3902 3903 // RTEMS Target 3904 template<typename Target> 3905 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3906 protected: 3907 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3908 MacroBuilder &Builder) const override { 3909 // RTEMS defines; list based off of gcc output 3910 3911 Builder.defineMacro("__rtems__"); 3912 Builder.defineMacro("__ELF__"); 3913 } 3914 3915 public: 3916 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3917 switch (Triple.getArch()) { 3918 default: 3919 case llvm::Triple::x86: 3920 // this->MCountName = ".mcount"; 3921 break; 3922 case llvm::Triple::mips: 3923 case llvm::Triple::mipsel: 3924 case llvm::Triple::ppc: 3925 case llvm::Triple::ppc64: 3926 case llvm::Triple::ppc64le: 3927 // this->MCountName = "_mcount"; 3928 break; 3929 case llvm::Triple::arm: 3930 // this->MCountName = "__mcount"; 3931 break; 3932 } 3933 } 3934 }; 3935 3936 // x86-32 RTEMS target 3937 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3938 public: 3939 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3940 SizeType = UnsignedLong; 3941 IntPtrType = SignedLong; 3942 PtrDiffType = SignedLong; 3943 } 3944 void getTargetDefines(const LangOptions &Opts, 3945 MacroBuilder &Builder) const override { 3946 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3947 Builder.defineMacro("__INTEL__"); 3948 Builder.defineMacro("__rtems__"); 3949 } 3950 }; 3951 3952 // x86-64 generic target 3953 class X86_64TargetInfo : public X86TargetInfo { 3954 public: 3955 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3956 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3957 bool IsWinCOFF = 3958 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3959 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3960 LongDoubleWidth = 128; 3961 LongDoubleAlign = 128; 3962 LargeArrayMinWidth = 128; 3963 LargeArrayAlign = 128; 3964 SuitableAlign = 128; 3965 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3966 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3967 IntPtrType = IsX32 ? SignedInt : SignedLong; 3968 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3969 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3970 RegParmMax = 6; 3971 3972 // Pointers are 32-bit in x32. 3973 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3974 : IsWinCOFF 3975 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3976 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3977 3978 // Use fpret only for long double. 3979 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3980 3981 // Use fp2ret for _Complex long double. 3982 ComplexLongDoubleUsesFP2Ret = true; 3983 3984 // Make __builtin_ms_va_list available. 3985 HasBuiltinMSVaList = true; 3986 3987 // x86-64 has atomics up to 16 bytes. 3988 MaxAtomicPromoteWidth = 128; 3989 MaxAtomicInlineWidth = 128; 3990 3991 UserLabelPrefix = "_"; 3992 } 3993 BuiltinVaListKind getBuiltinVaListKind() const override { 3994 return TargetInfo::X86_64ABIBuiltinVaList; 3995 } 3996 3997 int getEHDataRegisterNumber(unsigned RegNo) const override { 3998 if (RegNo == 0) return 0; 3999 if (RegNo == 1) return 1; 4000 return -1; 4001 } 4002 4003 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4004 return (CC == CC_C || 4005 CC == CC_X86VectorCall || 4006 CC == CC_IntelOclBicc || 4007 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 4008 } 4009 4010 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4011 return CC_C; 4012 } 4013 4014 // for x32 we need it here explicitly 4015 bool hasInt128Type() const override { return true; } 4016 4017 bool validateGlobalRegisterVariable(StringRef RegName, 4018 unsigned RegSize, 4019 bool &HasSizeMismatch) const override { 4020 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4021 // handle. 4022 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4023 // Check that the register size is 64-bit. 4024 HasSizeMismatch = RegSize != 64; 4025 return true; 4026 } 4027 4028 // Check if the register is a 32-bit register the backend can handle. 4029 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4030 HasSizeMismatch); 4031 } 4032 }; 4033 4034 // x86-64 Windows target 4035 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4036 public: 4037 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 4038 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 4039 WCharType = UnsignedShort; 4040 LongWidth = LongAlign = 32; 4041 DoubleAlign = LongLongAlign = 64; 4042 IntMaxType = SignedLongLong; 4043 Int64Type = SignedLongLong; 4044 SizeType = UnsignedLongLong; 4045 PtrDiffType = SignedLongLong; 4046 IntPtrType = SignedLongLong; 4047 } 4048 4049 void getTargetDefines(const LangOptions &Opts, 4050 MacroBuilder &Builder) const override { 4051 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4052 Builder.defineMacro("_WIN64"); 4053 } 4054 4055 BuiltinVaListKind getBuiltinVaListKind() const override { 4056 return TargetInfo::CharPtrBuiltinVaList; 4057 } 4058 4059 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4060 switch (CC) { 4061 case CC_X86StdCall: 4062 case CC_X86ThisCall: 4063 case CC_X86FastCall: 4064 return CCCR_Ignore; 4065 case CC_C: 4066 case CC_X86VectorCall: 4067 case CC_IntelOclBicc: 4068 case CC_X86_64SysV: 4069 return CCCR_OK; 4070 default: 4071 return CCCR_Warning; 4072 } 4073 } 4074 }; 4075 4076 // x86-64 Windows Visual Studio target 4077 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4078 public: 4079 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 4080 : WindowsX86_64TargetInfo(Triple) { 4081 LongDoubleWidth = LongDoubleAlign = 64; 4082 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4083 } 4084 void getTargetDefines(const LangOptions &Opts, 4085 MacroBuilder &Builder) const override { 4086 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4087 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4088 Builder.defineMacro("_M_X64", "100"); 4089 Builder.defineMacro("_M_AMD64", "100"); 4090 } 4091 }; 4092 4093 // x86-64 MinGW target 4094 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4095 public: 4096 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4097 : WindowsX86_64TargetInfo(Triple) { 4098 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4099 // with x86 FP ops. Weird. 4100 LongDoubleWidth = LongDoubleAlign = 128; 4101 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4102 } 4103 4104 void getTargetDefines(const LangOptions &Opts, 4105 MacroBuilder &Builder) const override { 4106 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4107 DefineStd(Builder, "WIN64", Opts); 4108 Builder.defineMacro("__MINGW64__"); 4109 addMinGWDefines(Opts, Builder); 4110 4111 // GCC defines this macro when it is using __gxx_personality_seh0. 4112 if (!Opts.SjLjExceptions) 4113 Builder.defineMacro("__SEH__"); 4114 } 4115 }; 4116 4117 // x86-64 Cygwin target 4118 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4119 public: 4120 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4121 : X86_64TargetInfo(Triple) { 4122 TLSSupported = false; 4123 WCharType = UnsignedShort; 4124 } 4125 void getTargetDefines(const LangOptions &Opts, 4126 MacroBuilder &Builder) const override { 4127 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4128 Builder.defineMacro("__x86_64__"); 4129 Builder.defineMacro("__CYGWIN__"); 4130 Builder.defineMacro("__CYGWIN64__"); 4131 addCygMingDefines(Opts, Builder); 4132 DefineStd(Builder, "unix", Opts); 4133 if (Opts.CPlusPlus) 4134 Builder.defineMacro("_GNU_SOURCE"); 4135 4136 // GCC defines this macro when it is using __gxx_personality_seh0. 4137 if (!Opts.SjLjExceptions) 4138 Builder.defineMacro("__SEH__"); 4139 } 4140 }; 4141 4142 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4143 public: 4144 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4145 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4146 Int64Type = SignedLongLong; 4147 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4148 llvm::Triple T = llvm::Triple(Triple); 4149 if (T.isiOS()) 4150 UseSignedCharForObjCBool = false; 4151 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 4152 } 4153 4154 bool handleTargetFeatures(std::vector<std::string> &Features, 4155 DiagnosticsEngine &Diags) override { 4156 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4157 Diags)) 4158 return false; 4159 // We now know the features we have: we can decide how to align vectors. 4160 MaxVectorAlign = 4161 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4162 return true; 4163 } 4164 }; 4165 4166 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4167 public: 4168 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4169 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4170 IntMaxType = SignedLongLong; 4171 Int64Type = SignedLongLong; 4172 } 4173 }; 4174 4175 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4176 public: 4177 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4178 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4179 IntMaxType = SignedLongLong; 4180 Int64Type = SignedLongLong; 4181 } 4182 }; 4183 4184 class ARMTargetInfo : public TargetInfo { 4185 // Possible FPU choices. 4186 enum FPUMode { 4187 VFP2FPU = (1 << 0), 4188 VFP3FPU = (1 << 1), 4189 VFP4FPU = (1 << 2), 4190 NeonFPU = (1 << 3), 4191 FPARMV8 = (1 << 4) 4192 }; 4193 4194 // Possible HWDiv features. 4195 enum HWDivMode { 4196 HWDivThumb = (1 << 0), 4197 HWDivARM = (1 << 1) 4198 }; 4199 4200 static bool FPUModeIsVFP(FPUMode Mode) { 4201 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4202 } 4203 4204 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4205 static const char * const GCCRegNames[]; 4206 4207 std::string ABI, CPU; 4208 4209 StringRef CPUProfile; 4210 StringRef CPUAttr; 4211 4212 enum { 4213 FP_Default, 4214 FP_VFP, 4215 FP_Neon 4216 } FPMath; 4217 4218 unsigned ArchISA; 4219 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4220 unsigned ArchProfile; 4221 unsigned ArchVersion; 4222 4223 unsigned FPU : 5; 4224 4225 unsigned IsAAPCS : 1; 4226 unsigned HWDiv : 2; 4227 4228 // Initialized via features. 4229 unsigned SoftFloat : 1; 4230 unsigned SoftFloatABI : 1; 4231 4232 unsigned CRC : 1; 4233 unsigned Crypto : 1; 4234 unsigned DSP : 1; 4235 unsigned Unaligned : 1; 4236 4237 enum { 4238 LDREX_B = (1 << 0), /// byte (8-bit) 4239 LDREX_H = (1 << 1), /// half (16-bit) 4240 LDREX_W = (1 << 2), /// word (32-bit) 4241 LDREX_D = (1 << 3), /// double (64-bit) 4242 }; 4243 4244 uint32_t LDREX; 4245 4246 // ACLE 6.5.1 Hardware floating point 4247 enum { 4248 HW_FP_HP = (1 << 1), /// half (16-bit) 4249 HW_FP_SP = (1 << 2), /// single (32-bit) 4250 HW_FP_DP = (1 << 3), /// double (64-bit) 4251 }; 4252 uint32_t HW_FP; 4253 4254 static const Builtin::Info BuiltinInfo[]; 4255 4256 void setABIAAPCS() { 4257 IsAAPCS = true; 4258 4259 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4260 const llvm::Triple &T = getTriple(); 4261 4262 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4263 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4264 T.getOS() == llvm::Triple::Bitrig) 4265 SizeType = UnsignedLong; 4266 else 4267 SizeType = UnsignedInt; 4268 4269 switch (T.getOS()) { 4270 case llvm::Triple::NetBSD: 4271 WCharType = SignedInt; 4272 break; 4273 case llvm::Triple::Win32: 4274 WCharType = UnsignedShort; 4275 break; 4276 case llvm::Triple::Linux: 4277 default: 4278 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4279 WCharType = UnsignedInt; 4280 break; 4281 } 4282 4283 UseBitFieldTypeAlignment = true; 4284 4285 ZeroLengthBitfieldBoundary = 0; 4286 4287 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4288 // so set preferred for small types to 32. 4289 if (T.isOSBinFormatMachO()) { 4290 DataLayoutString = 4291 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4292 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4293 } else if (T.isOSWindows()) { 4294 assert(!BigEndian && "Windows on ARM does not support big endian"); 4295 DataLayoutString = "e" 4296 "-m:w" 4297 "-p:32:32" 4298 "-i64:64" 4299 "-v128:64:128" 4300 "-a:0:32" 4301 "-n32" 4302 "-S64"; 4303 } else if (T.isOSNaCl()) { 4304 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4305 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4306 } else { 4307 DataLayoutString = 4308 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4309 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4310 } 4311 4312 // FIXME: Enumerated types are variable width in straight AAPCS. 4313 } 4314 4315 void setABIAPCS(bool IsAAPCS16) { 4316 const llvm::Triple &T = getTriple(); 4317 4318 IsAAPCS = false; 4319 4320 if (IsAAPCS16) 4321 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4322 else 4323 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4324 4325 // size_t is unsigned int on FreeBSD. 4326 if (T.getOS() == llvm::Triple::FreeBSD) 4327 SizeType = UnsignedInt; 4328 else 4329 SizeType = UnsignedLong; 4330 4331 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4332 WCharType = SignedInt; 4333 4334 // Do not respect the alignment of bit-field types when laying out 4335 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4336 UseBitFieldTypeAlignment = false; 4337 4338 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4339 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4340 /// gcc. 4341 ZeroLengthBitfieldBoundary = 32; 4342 4343 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4344 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4345 DataLayoutString = "e-m:o-p:32:32-i64:64-a:0:32-n32-S128"; 4346 } else if (T.isOSBinFormatMachO()) 4347 DataLayoutString = 4348 BigEndian 4349 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4350 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4351 else 4352 DataLayoutString = 4353 BigEndian 4354 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4355 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4356 4357 // FIXME: Override "preferred align" for double and long long. 4358 } 4359 4360 void setArchInfo() { 4361 StringRef ArchName = getTriple().getArchName(); 4362 4363 ArchISA = llvm::ARM::parseArchISA(ArchName); 4364 CPU = llvm::ARM::getDefaultCPU(ArchName); 4365 unsigned AK = llvm::ARM::parseArch(ArchName); 4366 if (AK != llvm::ARM::AK_INVALID) 4367 ArchKind = AK; 4368 setArchInfo(ArchKind); 4369 } 4370 4371 void setArchInfo(unsigned Kind) { 4372 StringRef SubArch; 4373 4374 // cache TargetParser info 4375 ArchKind = Kind; 4376 SubArch = llvm::ARM::getSubArch(ArchKind); 4377 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4378 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4379 4380 // cache CPU related strings 4381 CPUAttr = getCPUAttr(); 4382 CPUProfile = getCPUProfile(); 4383 } 4384 4385 void setAtomic() { 4386 // when triple does not specify a sub arch, 4387 // then we are not using inline atomics 4388 bool ShouldUseInlineAtomic = 4389 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4390 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4391 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4392 if (ArchProfile == llvm::ARM::PK_M) { 4393 MaxAtomicPromoteWidth = 32; 4394 if (ShouldUseInlineAtomic) 4395 MaxAtomicInlineWidth = 32; 4396 } 4397 else { 4398 MaxAtomicPromoteWidth = 64; 4399 if (ShouldUseInlineAtomic) 4400 MaxAtomicInlineWidth = 64; 4401 } 4402 } 4403 4404 bool isThumb() const { 4405 return (ArchISA == llvm::ARM::IK_THUMB); 4406 } 4407 4408 bool supportsThumb() const { 4409 return CPUAttr.count('T') || ArchVersion >= 6; 4410 } 4411 4412 bool supportsThumb2() const { 4413 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4414 } 4415 4416 StringRef getCPUAttr() const { 4417 // For most sub-arches, the build attribute CPU name is enough. 4418 // For Cortex variants, it's slightly different. 4419 switch(ArchKind) { 4420 default: 4421 return llvm::ARM::getCPUAttr(ArchKind); 4422 case llvm::ARM::AK_ARMV6M: 4423 return "6M"; 4424 case llvm::ARM::AK_ARMV7S: 4425 return "7S"; 4426 case llvm::ARM::AK_ARMV7A: 4427 return "7A"; 4428 case llvm::ARM::AK_ARMV7R: 4429 return "7R"; 4430 case llvm::ARM::AK_ARMV7M: 4431 return "7M"; 4432 case llvm::ARM::AK_ARMV7EM: 4433 return "7EM"; 4434 case llvm::ARM::AK_ARMV8A: 4435 return "8A"; 4436 case llvm::ARM::AK_ARMV8_1A: 4437 return "8_1A"; 4438 } 4439 } 4440 4441 StringRef getCPUProfile() const { 4442 switch(ArchProfile) { 4443 case llvm::ARM::PK_A: 4444 return "A"; 4445 case llvm::ARM::PK_R: 4446 return "R"; 4447 case llvm::ARM::PK_M: 4448 return "M"; 4449 default: 4450 return ""; 4451 } 4452 } 4453 4454 public: 4455 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4456 : TargetInfo(Triple), FPMath(FP_Default), 4457 IsAAPCS(true), LDREX(0), HW_FP(0) { 4458 BigEndian = IsBigEndian; 4459 4460 switch (getTriple().getOS()) { 4461 case llvm::Triple::NetBSD: 4462 PtrDiffType = SignedLong; 4463 break; 4464 default: 4465 PtrDiffType = SignedInt; 4466 break; 4467 } 4468 4469 // Cache arch related info. 4470 setArchInfo(); 4471 4472 // {} in inline assembly are neon specifiers, not assembly variant 4473 // specifiers. 4474 NoAsmVariants = true; 4475 4476 // FIXME: This duplicates code from the driver that sets the -target-abi 4477 // option - this code is used if -target-abi isn't passed and should 4478 // be unified in some way. 4479 if (Triple.isOSBinFormatMachO()) { 4480 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4481 // the frontend matches that. 4482 if (Triple.getEnvironment() == llvm::Triple::EABI || 4483 Triple.getOS() == llvm::Triple::UnknownOS || 4484 StringRef(CPU).startswith("cortex-m")) { 4485 setABI("aapcs"); 4486 } else if (Triple.isWatchOS()) { 4487 setABI("aapcs16"); 4488 } else { 4489 setABI("apcs-gnu"); 4490 } 4491 } else if (Triple.isOSWindows()) { 4492 // FIXME: this is invalid for WindowsCE 4493 setABI("aapcs"); 4494 } else { 4495 // Select the default based on the platform. 4496 switch (Triple.getEnvironment()) { 4497 case llvm::Triple::Android: 4498 case llvm::Triple::GNUEABI: 4499 case llvm::Triple::GNUEABIHF: 4500 setABI("aapcs-linux"); 4501 break; 4502 case llvm::Triple::EABIHF: 4503 case llvm::Triple::EABI: 4504 setABI("aapcs"); 4505 break; 4506 case llvm::Triple::GNU: 4507 setABI("apcs-gnu"); 4508 break; 4509 default: 4510 if (Triple.getOS() == llvm::Triple::NetBSD) 4511 setABI("apcs-gnu"); 4512 else 4513 setABI("aapcs"); 4514 break; 4515 } 4516 } 4517 4518 // ARM targets default to using the ARM C++ ABI. 4519 TheCXXABI.set(TargetCXXABI::GenericARM); 4520 4521 // ARM has atomics up to 8 bytes 4522 setAtomic(); 4523 4524 // Do force alignment of members that follow zero length bitfields. If 4525 // the alignment of the zero-length bitfield is greater than the member 4526 // that follows it, `bar', `bar' will be aligned as the type of the 4527 // zero length bitfield. 4528 UseZeroLengthBitfieldAlignment = true; 4529 4530 UserLabelPrefix = "_"; 4531 } 4532 4533 StringRef getABI() const override { return ABI; } 4534 4535 bool setABI(const std::string &Name) override { 4536 ABI = Name; 4537 4538 // The defaults (above) are for AAPCS, check if we need to change them. 4539 // 4540 // FIXME: We need support for -meabi... we could just mangle it into the 4541 // name. 4542 if (Name == "apcs-gnu" || Name == "aapcs16") { 4543 setABIAPCS(Name == "aapcs16"); 4544 return true; 4545 } 4546 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4547 setABIAAPCS(); 4548 return true; 4549 } 4550 return false; 4551 } 4552 4553 // FIXME: This should be based on Arch attributes, not CPU names. 4554 bool 4555 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4556 StringRef CPU, 4557 const std::vector<std::string> &FeaturesVec) const override { 4558 4559 std::vector<const char*> TargetFeatures; 4560 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4561 4562 // get default FPU features 4563 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4564 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4565 4566 // get default Extension features 4567 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4568 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4569 4570 for (const char *Feature : TargetFeatures) 4571 if (Feature[0] == '+') 4572 Features[Feature+1] = true; 4573 4574 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4575 } 4576 4577 bool handleTargetFeatures(std::vector<std::string> &Features, 4578 DiagnosticsEngine &Diags) override { 4579 FPU = 0; 4580 CRC = 0; 4581 Crypto = 0; 4582 DSP = 0; 4583 Unaligned = 1; 4584 SoftFloat = SoftFloatABI = false; 4585 HWDiv = 0; 4586 4587 // This does not diagnose illegal cases like having both 4588 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4589 uint32_t HW_FP_remove = 0; 4590 for (const auto &Feature : Features) { 4591 if (Feature == "+soft-float") { 4592 SoftFloat = true; 4593 } else if (Feature == "+soft-float-abi") { 4594 SoftFloatABI = true; 4595 } else if (Feature == "+vfp2") { 4596 FPU |= VFP2FPU; 4597 HW_FP |= HW_FP_SP | HW_FP_DP; 4598 } else if (Feature == "+vfp3") { 4599 FPU |= VFP3FPU; 4600 HW_FP |= HW_FP_SP | HW_FP_DP; 4601 } else if (Feature == "+vfp4") { 4602 FPU |= VFP4FPU; 4603 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4604 } else if (Feature == "+fp-armv8") { 4605 FPU |= FPARMV8; 4606 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4607 } else if (Feature == "+neon") { 4608 FPU |= NeonFPU; 4609 HW_FP |= HW_FP_SP | HW_FP_DP; 4610 } else if (Feature == "+hwdiv") { 4611 HWDiv |= HWDivThumb; 4612 } else if (Feature == "+hwdiv-arm") { 4613 HWDiv |= HWDivARM; 4614 } else if (Feature == "+crc") { 4615 CRC = 1; 4616 } else if (Feature == "+crypto") { 4617 Crypto = 1; 4618 } else if (Feature == "+dsp") { 4619 DSP = 1; 4620 } else if (Feature == "+fp-only-sp") { 4621 HW_FP_remove |= HW_FP_DP; 4622 } else if (Feature == "+strict-align") { 4623 Unaligned = 0; 4624 } else if (Feature == "+fp16") { 4625 HW_FP |= HW_FP_HP; 4626 } 4627 } 4628 HW_FP &= ~HW_FP_remove; 4629 4630 switch (ArchVersion) { 4631 case 6: 4632 if (ArchProfile == llvm::ARM::PK_M) 4633 LDREX = 0; 4634 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4635 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4636 else 4637 LDREX = LDREX_W; 4638 break; 4639 case 7: 4640 if (ArchProfile == llvm::ARM::PK_M) 4641 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4642 else 4643 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4644 break; 4645 case 8: 4646 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4647 } 4648 4649 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4650 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4651 return false; 4652 } 4653 4654 if (FPMath == FP_Neon) 4655 Features.push_back("+neonfp"); 4656 else if (FPMath == FP_VFP) 4657 Features.push_back("-neonfp"); 4658 4659 // Remove front-end specific options which the backend handles differently. 4660 auto Feature = 4661 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4662 if (Feature != Features.end()) 4663 Features.erase(Feature); 4664 4665 return true; 4666 } 4667 4668 bool hasFeature(StringRef Feature) const override { 4669 return llvm::StringSwitch<bool>(Feature) 4670 .Case("arm", true) 4671 .Case("aarch32", true) 4672 .Case("softfloat", SoftFloat) 4673 .Case("thumb", isThumb()) 4674 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4675 .Case("hwdiv", HWDiv & HWDivThumb) 4676 .Case("hwdiv-arm", HWDiv & HWDivARM) 4677 .Default(false); 4678 } 4679 4680 bool setCPU(const std::string &Name) override { 4681 if (Name != "generic") 4682 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4683 4684 if (ArchKind == llvm::ARM::AK_INVALID) 4685 return false; 4686 setAtomic(); 4687 CPU = Name; 4688 return true; 4689 } 4690 4691 bool setFPMath(StringRef Name) override; 4692 4693 void getTargetDefines(const LangOptions &Opts, 4694 MacroBuilder &Builder) const override { 4695 // Target identification. 4696 Builder.defineMacro("__arm"); 4697 Builder.defineMacro("__arm__"); 4698 4699 // Target properties. 4700 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4701 4702 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4703 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 4704 if (getTriple().isWatchOS()) 4705 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 4706 4707 if (!CPUAttr.empty()) 4708 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4709 4710 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4711 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4712 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 4713 4714 if (ArchVersion >= 8) { 4715 // ACLE 6.5.7 Crypto Extension 4716 if (Crypto) 4717 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4718 // ACLE 6.5.8 CRC32 Extension 4719 if (CRC) 4720 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4721 // ACLE 6.5.10 Numeric Maximum and Minimum 4722 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4723 // ACLE 6.5.9 Directed Rounding 4724 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4725 } 4726 4727 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4728 // is not defined for the M-profile. 4729 // NOTE that the deffault profile is assumed to be 'A' 4730 if (CPUProfile.empty() || CPUProfile != "M") 4731 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4732 4733 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4734 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4735 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4736 if (supportsThumb2()) 4737 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4738 else if (supportsThumb()) 4739 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4740 4741 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4742 // instruction set such as ARM or Thumb. 4743 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4744 4745 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4746 4747 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4748 if (!CPUProfile.empty()) 4749 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4750 4751 // ACLE 6.4.3 Unaligned access supported in hardware 4752 if (Unaligned) 4753 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4754 4755 // ACLE 6.4.4 LDREX/STREX 4756 if (LDREX) 4757 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4758 4759 // ACLE 6.4.5 CLZ 4760 if (ArchVersion == 5 || 4761 (ArchVersion == 6 && CPUProfile != "M") || 4762 ArchVersion > 6) 4763 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4764 4765 // ACLE 6.5.1 Hardware Floating Point 4766 if (HW_FP) 4767 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4768 4769 // ACLE predefines. 4770 Builder.defineMacro("__ARM_ACLE", "200"); 4771 4772 // FP16 support (we currently only support IEEE format). 4773 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4774 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4775 4776 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4777 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4778 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4779 4780 // Subtarget options. 4781 4782 // FIXME: It's more complicated than this and we don't really support 4783 // interworking. 4784 // Windows on ARM does not "support" interworking 4785 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4786 Builder.defineMacro("__THUMB_INTERWORK__"); 4787 4788 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4789 // Embedded targets on Darwin follow AAPCS, but not EABI. 4790 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4791 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4792 Builder.defineMacro("__ARM_EABI__"); 4793 Builder.defineMacro("__ARM_PCS", "1"); 4794 4795 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4796 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4797 } 4798 4799 if (SoftFloat) 4800 Builder.defineMacro("__SOFTFP__"); 4801 4802 if (CPU == "xscale") 4803 Builder.defineMacro("__XSCALE__"); 4804 4805 if (isThumb()) { 4806 Builder.defineMacro("__THUMBEL__"); 4807 Builder.defineMacro("__thumb__"); 4808 if (supportsThumb2()) 4809 Builder.defineMacro("__thumb2__"); 4810 } 4811 4812 // ACLE 6.4.9 32-bit SIMD instructions 4813 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4814 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4815 4816 // ACLE 6.4.10 Hardware Integer Divide 4817 if (((HWDiv & HWDivThumb) && isThumb()) || 4818 ((HWDiv & HWDivARM) && !isThumb())) { 4819 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4820 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4821 } 4822 4823 // Note, this is always on in gcc, even though it doesn't make sense. 4824 Builder.defineMacro("__APCS_32__"); 4825 4826 if (FPUModeIsVFP((FPUMode) FPU)) { 4827 Builder.defineMacro("__VFP_FP__"); 4828 if (FPU & VFP2FPU) 4829 Builder.defineMacro("__ARM_VFPV2__"); 4830 if (FPU & VFP3FPU) 4831 Builder.defineMacro("__ARM_VFPV3__"); 4832 if (FPU & VFP4FPU) 4833 Builder.defineMacro("__ARM_VFPV4__"); 4834 } 4835 4836 // This only gets set when Neon instructions are actually available, unlike 4837 // the VFP define, hence the soft float and arch check. This is subtly 4838 // different from gcc, we follow the intent which was that it should be set 4839 // when Neon instructions are actually available. 4840 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4841 Builder.defineMacro("__ARM_NEON", "1"); 4842 Builder.defineMacro("__ARM_NEON__"); 4843 // current AArch32 NEON implementations do not support double-precision 4844 // floating-point even when it is present in VFP. 4845 Builder.defineMacro("__ARM_NEON_FP", 4846 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4847 } 4848 4849 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4850 Opts.ShortWChar ? "2" : "4"); 4851 4852 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4853 Opts.ShortEnums ? "1" : "4"); 4854 4855 if (ArchVersion >= 6 && CPUAttr != "6M") { 4856 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4857 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4858 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4859 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4860 } 4861 4862 // ACLE 6.4.7 DSP instructions 4863 if (DSP) { 4864 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4865 } 4866 4867 // ACLE 6.4.8 Saturation instructions 4868 bool SAT = false; 4869 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4870 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4871 SAT = true; 4872 } 4873 4874 // ACLE 6.4.6 Q (saturation) flag 4875 if (DSP || SAT) 4876 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 4877 4878 if (Opts.UnsafeFPMath) 4879 Builder.defineMacro("__ARM_FP_FAST", "1"); 4880 4881 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 4882 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 4883 } 4884 4885 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4886 return llvm::makeArrayRef(BuiltinInfo, 4887 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 4888 } 4889 bool isCLZForZeroUndef() const override { return false; } 4890 BuiltinVaListKind getBuiltinVaListKind() const override { 4891 return IsAAPCS 4892 ? AAPCSABIBuiltinVaList 4893 : (getTriple().isWatchOS() ? TargetInfo::CharPtrBuiltinVaList 4894 : TargetInfo::VoidPtrBuiltinVaList); 4895 } 4896 ArrayRef<const char *> getGCCRegNames() const override; 4897 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 4898 bool validateAsmConstraint(const char *&Name, 4899 TargetInfo::ConstraintInfo &Info) const override { 4900 switch (*Name) { 4901 default: break; 4902 case 'l': // r0-r7 4903 case 'h': // r8-r15 4904 case 'w': // VFP Floating point register single precision 4905 case 'P': // VFP Floating point register double precision 4906 Info.setAllowsRegister(); 4907 return true; 4908 case 'I': 4909 case 'J': 4910 case 'K': 4911 case 'L': 4912 case 'M': 4913 // FIXME 4914 return true; 4915 case 'Q': // A memory address that is a single base register. 4916 Info.setAllowsMemory(); 4917 return true; 4918 case 'U': // a memory reference... 4919 switch (Name[1]) { 4920 case 'q': // ...ARMV4 ldrsb 4921 case 'v': // ...VFP load/store (reg+constant offset) 4922 case 'y': // ...iWMMXt load/store 4923 case 't': // address valid for load/store opaque types wider 4924 // than 128-bits 4925 case 'n': // valid address for Neon doubleword vector load/store 4926 case 'm': // valid address for Neon element and structure load/store 4927 case 's': // valid address for non-offset loads/stores of quad-word 4928 // values in four ARM registers 4929 Info.setAllowsMemory(); 4930 Name++; 4931 return true; 4932 } 4933 } 4934 return false; 4935 } 4936 std::string convertConstraint(const char *&Constraint) const override { 4937 std::string R; 4938 switch (*Constraint) { 4939 case 'U': // Two-character constraint; add "^" hint for later parsing. 4940 R = std::string("^") + std::string(Constraint, 2); 4941 Constraint++; 4942 break; 4943 case 'p': // 'p' should be translated to 'r' by default. 4944 R = std::string("r"); 4945 break; 4946 default: 4947 return std::string(1, *Constraint); 4948 } 4949 return R; 4950 } 4951 bool 4952 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4953 std::string &SuggestedModifier) const override { 4954 bool isOutput = (Constraint[0] == '='); 4955 bool isInOut = (Constraint[0] == '+'); 4956 4957 // Strip off constraint modifiers. 4958 while (Constraint[0] == '=' || 4959 Constraint[0] == '+' || 4960 Constraint[0] == '&') 4961 Constraint = Constraint.substr(1); 4962 4963 switch (Constraint[0]) { 4964 default: break; 4965 case 'r': { 4966 switch (Modifier) { 4967 default: 4968 return (isInOut || isOutput || Size <= 64); 4969 case 'q': 4970 // A register of size 32 cannot fit a vector type. 4971 return false; 4972 } 4973 } 4974 } 4975 4976 return true; 4977 } 4978 const char *getClobbers() const override { 4979 // FIXME: Is this really right? 4980 return ""; 4981 } 4982 4983 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4984 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4985 } 4986 4987 int getEHDataRegisterNumber(unsigned RegNo) const override { 4988 if (RegNo == 0) return 0; 4989 if (RegNo == 1) return 1; 4990 return -1; 4991 } 4992 4993 bool hasSjLjLowering() const override { 4994 return true; 4995 } 4996 }; 4997 4998 bool ARMTargetInfo::setFPMath(StringRef Name) { 4999 if (Name == "neon") { 5000 FPMath = FP_Neon; 5001 return true; 5002 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5003 Name == "vfp4") { 5004 FPMath = FP_VFP; 5005 return true; 5006 } 5007 return false; 5008 } 5009 5010 const char * const ARMTargetInfo::GCCRegNames[] = { 5011 // Integer registers 5012 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5013 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5014 5015 // Float registers 5016 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5017 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5018 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5019 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5020 5021 // Double registers 5022 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5023 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5024 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5025 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5026 5027 // Quad registers 5028 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5029 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5030 }; 5031 5032 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5033 return llvm::makeArrayRef(GCCRegNames); 5034 } 5035 5036 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5037 { { "a1" }, "r0" }, 5038 { { "a2" }, "r1" }, 5039 { { "a3" }, "r2" }, 5040 { { "a4" }, "r3" }, 5041 { { "v1" }, "r4" }, 5042 { { "v2" }, "r5" }, 5043 { { "v3" }, "r6" }, 5044 { { "v4" }, "r7" }, 5045 { { "v5" }, "r8" }, 5046 { { "v6", "rfp" }, "r9" }, 5047 { { "sl" }, "r10" }, 5048 { { "fp" }, "r11" }, 5049 { { "ip" }, "r12" }, 5050 { { "r13" }, "sp" }, 5051 { { "r14" }, "lr" }, 5052 { { "r15" }, "pc" }, 5053 // The S, D and Q registers overlap, but aren't really aliases; we 5054 // don't want to substitute one of these for a different-sized one. 5055 }; 5056 5057 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5058 return llvm::makeArrayRef(GCCRegAliases); 5059 } 5060 5061 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5062 #define BUILTIN(ID, TYPE, ATTRS) \ 5063 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5064 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5065 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5066 #include "clang/Basic/BuiltinsNEON.def" 5067 5068 #define BUILTIN(ID, TYPE, ATTRS) \ 5069 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5070 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5071 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5072 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5073 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5074 #include "clang/Basic/BuiltinsARM.def" 5075 }; 5076 5077 class ARMleTargetInfo : public ARMTargetInfo { 5078 public: 5079 ARMleTargetInfo(const llvm::Triple &Triple) 5080 : ARMTargetInfo(Triple, false) { } 5081 void getTargetDefines(const LangOptions &Opts, 5082 MacroBuilder &Builder) const override { 5083 Builder.defineMacro("__ARMEL__"); 5084 ARMTargetInfo::getTargetDefines(Opts, Builder); 5085 } 5086 }; 5087 5088 class ARMbeTargetInfo : public ARMTargetInfo { 5089 public: 5090 ARMbeTargetInfo(const llvm::Triple &Triple) 5091 : ARMTargetInfo(Triple, true) { } 5092 void getTargetDefines(const LangOptions &Opts, 5093 MacroBuilder &Builder) const override { 5094 Builder.defineMacro("__ARMEB__"); 5095 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5096 ARMTargetInfo::getTargetDefines(Opts, Builder); 5097 } 5098 }; 5099 5100 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5101 const llvm::Triple Triple; 5102 public: 5103 WindowsARMTargetInfo(const llvm::Triple &Triple) 5104 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 5105 TLSSupported = false; 5106 WCharType = UnsignedShort; 5107 SizeType = UnsignedInt; 5108 } 5109 void getVisualStudioDefines(const LangOptions &Opts, 5110 MacroBuilder &Builder) const { 5111 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5112 5113 // FIXME: this is invalid for WindowsCE 5114 Builder.defineMacro("_M_ARM_NT", "1"); 5115 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5116 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5117 5118 assert((Triple.getArch() == llvm::Triple::arm || 5119 Triple.getArch() == llvm::Triple::thumb) && 5120 "invalid architecture for Windows ARM target info"); 5121 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5122 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5123 5124 // TODO map the complete set of values 5125 // 31: VFPv3 40: VFPv4 5126 Builder.defineMacro("_M_ARM_FP", "31"); 5127 } 5128 BuiltinVaListKind getBuiltinVaListKind() const override { 5129 return TargetInfo::CharPtrBuiltinVaList; 5130 } 5131 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5132 switch (CC) { 5133 case CC_X86StdCall: 5134 case CC_X86ThisCall: 5135 case CC_X86FastCall: 5136 case CC_X86VectorCall: 5137 return CCCR_Ignore; 5138 case CC_C: 5139 return CCCR_OK; 5140 default: 5141 return CCCR_Warning; 5142 } 5143 } 5144 }; 5145 5146 // Windows ARM + Itanium C++ ABI Target 5147 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5148 public: 5149 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5150 : WindowsARMTargetInfo(Triple) { 5151 TheCXXABI.set(TargetCXXABI::GenericARM); 5152 } 5153 5154 void getTargetDefines(const LangOptions &Opts, 5155 MacroBuilder &Builder) const override { 5156 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5157 5158 if (Opts.MSVCCompat) 5159 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5160 } 5161 }; 5162 5163 // Windows ARM, MS (C++) ABI 5164 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5165 public: 5166 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5167 : WindowsARMTargetInfo(Triple) { 5168 TheCXXABI.set(TargetCXXABI::Microsoft); 5169 } 5170 5171 void getTargetDefines(const LangOptions &Opts, 5172 MacroBuilder &Builder) const override { 5173 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5174 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5175 } 5176 }; 5177 5178 // ARM MinGW target 5179 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5180 public: 5181 MinGWARMTargetInfo(const llvm::Triple &Triple) 5182 : WindowsARMTargetInfo(Triple) { 5183 TheCXXABI.set(TargetCXXABI::GenericARM); 5184 } 5185 5186 void getTargetDefines(const LangOptions &Opts, 5187 MacroBuilder &Builder) const override { 5188 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5189 DefineStd(Builder, "WIN32", Opts); 5190 DefineStd(Builder, "WINNT", Opts); 5191 Builder.defineMacro("_ARM_"); 5192 addMinGWDefines(Opts, Builder); 5193 } 5194 }; 5195 5196 // ARM Cygwin target 5197 class CygwinARMTargetInfo : public ARMleTargetInfo { 5198 public: 5199 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5200 TLSSupported = false; 5201 WCharType = UnsignedShort; 5202 DoubleAlign = LongLongAlign = 64; 5203 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 5204 } 5205 void getTargetDefines(const LangOptions &Opts, 5206 MacroBuilder &Builder) const override { 5207 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5208 Builder.defineMacro("_ARM_"); 5209 Builder.defineMacro("__CYGWIN__"); 5210 Builder.defineMacro("__CYGWIN32__"); 5211 DefineStd(Builder, "unix", Opts); 5212 if (Opts.CPlusPlus) 5213 Builder.defineMacro("_GNU_SOURCE"); 5214 } 5215 }; 5216 5217 class DarwinARMTargetInfo : 5218 public DarwinTargetInfo<ARMleTargetInfo> { 5219 protected: 5220 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5221 MacroBuilder &Builder) const override { 5222 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5223 } 5224 5225 public: 5226 DarwinARMTargetInfo(const llvm::Triple &Triple) 5227 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5228 HasAlignMac68kSupport = true; 5229 // iOS always has 64-bit atomic instructions. 5230 // FIXME: This should be based off of the target features in 5231 // ARMleTargetInfo. 5232 MaxAtomicInlineWidth = 64; 5233 5234 if (Triple.isWatchOS()) { 5235 // Darwin on iOS uses a variant of the ARM C++ ABI. 5236 TheCXXABI.set(TargetCXXABI::WatchOS); 5237 5238 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5239 // size_t is long, it's a bit weird for it to be int. 5240 PtrDiffType = SignedLong; 5241 5242 // BOOL should be a real boolean on the new ABI 5243 UseSignedCharForObjCBool = false; 5244 } else 5245 TheCXXABI.set(TargetCXXABI::iOS); 5246 } 5247 }; 5248 5249 class AArch64TargetInfo : public TargetInfo { 5250 virtual void setDataLayoutString() = 0; 5251 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5252 static const char *const GCCRegNames[]; 5253 5254 enum FPUModeEnum { 5255 FPUMode, 5256 NeonMode 5257 }; 5258 5259 unsigned FPU; 5260 unsigned CRC; 5261 unsigned Crypto; 5262 unsigned Unaligned; 5263 unsigned V8_1A; 5264 5265 static const Builtin::Info BuiltinInfo[]; 5266 5267 std::string ABI; 5268 5269 public: 5270 AArch64TargetInfo(const llvm::Triple &Triple) 5271 : TargetInfo(Triple), ABI("aapcs") { 5272 5273 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5274 WCharType = SignedInt; 5275 5276 // NetBSD apparently prefers consistency across ARM targets to consistency 5277 // across 64-bit targets. 5278 Int64Type = SignedLongLong; 5279 IntMaxType = SignedLongLong; 5280 } else { 5281 WCharType = UnsignedInt; 5282 Int64Type = SignedLong; 5283 IntMaxType = SignedLong; 5284 } 5285 5286 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5287 MaxVectorAlign = 128; 5288 MaxAtomicInlineWidth = 128; 5289 MaxAtomicPromoteWidth = 128; 5290 5291 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5292 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5293 5294 // {} in inline assembly are neon specifiers, not assembly variant 5295 // specifiers. 5296 NoAsmVariants = true; 5297 5298 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5299 // contributes to the alignment of the containing aggregate in the same way 5300 // a plain (non bit-field) member of that type would, without exception for 5301 // zero-sized or anonymous bit-fields." 5302 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5303 UseZeroLengthBitfieldAlignment = true; 5304 5305 // AArch64 targets default to using the ARM C++ ABI. 5306 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5307 5308 UserLabelPrefix = "_"; 5309 } 5310 5311 StringRef getABI() const override { return ABI; } 5312 bool setABI(const std::string &Name) override { 5313 if (Name != "aapcs" && Name != "darwinpcs") 5314 return false; 5315 5316 ABI = Name; 5317 return true; 5318 } 5319 5320 bool setCPU(const std::string &Name) override { 5321 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5322 .Case("generic", true) 5323 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5324 "cortex-a35", "exynos-m1", true) 5325 .Case("cyclone", true) 5326 .Default(false); 5327 return CPUKnown; 5328 } 5329 5330 void getTargetDefines(const LangOptions &Opts, 5331 MacroBuilder &Builder) const override { 5332 // Target identification. 5333 Builder.defineMacro("__aarch64__"); 5334 5335 // Target properties. 5336 Builder.defineMacro("_LP64"); 5337 Builder.defineMacro("__LP64__"); 5338 5339 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5340 Builder.defineMacro("__ARM_ACLE", "200"); 5341 Builder.defineMacro("__ARM_ARCH", "8"); 5342 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5343 5344 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5345 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5346 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5347 5348 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5349 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5350 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5351 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5352 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5353 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5354 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5355 5356 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5357 5358 // 0xe implies support for half, single and double precision operations. 5359 Builder.defineMacro("__ARM_FP", "0xE"); 5360 5361 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5362 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5363 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5364 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5365 5366 if (Opts.UnsafeFPMath) 5367 Builder.defineMacro("__ARM_FP_FAST", "1"); 5368 5369 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5370 5371 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5372 Opts.ShortEnums ? "1" : "4"); 5373 5374 if (FPU == NeonMode) { 5375 Builder.defineMacro("__ARM_NEON", "1"); 5376 // 64-bit NEON supports half, single and double precision operations. 5377 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5378 } 5379 5380 if (CRC) 5381 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5382 5383 if (Crypto) 5384 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5385 5386 if (Unaligned) 5387 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5388 5389 if (V8_1A) 5390 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5391 5392 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5393 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5394 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5395 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5397 } 5398 5399 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5400 return llvm::makeArrayRef(BuiltinInfo, 5401 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5402 } 5403 5404 bool hasFeature(StringRef Feature) const override { 5405 return Feature == "aarch64" || 5406 Feature == "arm64" || 5407 Feature == "arm" || 5408 (Feature == "neon" && FPU == NeonMode); 5409 } 5410 5411 bool handleTargetFeatures(std::vector<std::string> &Features, 5412 DiagnosticsEngine &Diags) override { 5413 FPU = FPUMode; 5414 CRC = 0; 5415 Crypto = 0; 5416 Unaligned = 1; 5417 V8_1A = 0; 5418 5419 for (const auto &Feature : Features) { 5420 if (Feature == "+neon") 5421 FPU = NeonMode; 5422 if (Feature == "+crc") 5423 CRC = 1; 5424 if (Feature == "+crypto") 5425 Crypto = 1; 5426 if (Feature == "+strict-align") 5427 Unaligned = 0; 5428 if (Feature == "+v8.1a") 5429 V8_1A = 1; 5430 } 5431 5432 setDataLayoutString(); 5433 5434 return true; 5435 } 5436 5437 bool isCLZForZeroUndef() const override { return false; } 5438 5439 BuiltinVaListKind getBuiltinVaListKind() const override { 5440 return TargetInfo::AArch64ABIBuiltinVaList; 5441 } 5442 5443 ArrayRef<const char *> getGCCRegNames() const override; 5444 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5445 5446 bool validateAsmConstraint(const char *&Name, 5447 TargetInfo::ConstraintInfo &Info) const override { 5448 switch (*Name) { 5449 default: 5450 return false; 5451 case 'w': // Floating point and SIMD registers (V0-V31) 5452 Info.setAllowsRegister(); 5453 return true; 5454 case 'I': // Constant that can be used with an ADD instruction 5455 case 'J': // Constant that can be used with a SUB instruction 5456 case 'K': // Constant that can be used with a 32-bit logical instruction 5457 case 'L': // Constant that can be used with a 64-bit logical instruction 5458 case 'M': // Constant that can be used as a 32-bit MOV immediate 5459 case 'N': // Constant that can be used as a 64-bit MOV immediate 5460 case 'Y': // Floating point constant zero 5461 case 'Z': // Integer constant zero 5462 return true; 5463 case 'Q': // A memory reference with base register and no offset 5464 Info.setAllowsMemory(); 5465 return true; 5466 case 'S': // A symbolic address 5467 Info.setAllowsRegister(); 5468 return true; 5469 case 'U': 5470 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5471 // Utf: A memory address suitable for ldp/stp in TF mode. 5472 // Usa: An absolute symbolic address. 5473 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5474 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5475 case 'z': // Zero register, wzr or xzr 5476 Info.setAllowsRegister(); 5477 return true; 5478 case 'x': // Floating point and SIMD registers (V0-V15) 5479 Info.setAllowsRegister(); 5480 return true; 5481 } 5482 return false; 5483 } 5484 5485 bool 5486 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5487 std::string &SuggestedModifier) const override { 5488 // Strip off constraint modifiers. 5489 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5490 Constraint = Constraint.substr(1); 5491 5492 switch (Constraint[0]) { 5493 default: 5494 return true; 5495 case 'z': 5496 case 'r': { 5497 switch (Modifier) { 5498 case 'x': 5499 case 'w': 5500 // For now assume that the person knows what they're 5501 // doing with the modifier. 5502 return true; 5503 default: 5504 // By default an 'r' constraint will be in the 'x' 5505 // registers. 5506 if (Size == 64) 5507 return true; 5508 5509 SuggestedModifier = "w"; 5510 return false; 5511 } 5512 } 5513 } 5514 } 5515 5516 const char *getClobbers() const override { return ""; } 5517 5518 int getEHDataRegisterNumber(unsigned RegNo) const override { 5519 if (RegNo == 0) 5520 return 0; 5521 if (RegNo == 1) 5522 return 1; 5523 return -1; 5524 } 5525 }; 5526 5527 const char *const AArch64TargetInfo::GCCRegNames[] = { 5528 // 32-bit Integer registers 5529 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5530 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5531 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5532 5533 // 64-bit Integer registers 5534 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5535 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5536 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5537 5538 // 32-bit floating point regsisters 5539 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5540 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5541 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5542 5543 // 64-bit floating point regsisters 5544 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5545 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5546 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5547 5548 // Vector registers 5549 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5550 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5551 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5552 }; 5553 5554 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5555 return llvm::makeArrayRef(GCCRegNames); 5556 } 5557 5558 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5559 { { "w31" }, "wsp" }, 5560 { { "x29" }, "fp" }, 5561 { { "x30" }, "lr" }, 5562 { { "x31" }, "sp" }, 5563 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5564 // don't want to substitute one of these for a different-sized one. 5565 }; 5566 5567 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5568 return llvm::makeArrayRef(GCCRegAliases); 5569 } 5570 5571 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5572 #define BUILTIN(ID, TYPE, ATTRS) \ 5573 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5574 #include "clang/Basic/BuiltinsNEON.def" 5575 5576 #define BUILTIN(ID, TYPE, ATTRS) \ 5577 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5578 #include "clang/Basic/BuiltinsAArch64.def" 5579 }; 5580 5581 class AArch64leTargetInfo : public AArch64TargetInfo { 5582 void setDataLayoutString() override { 5583 if (getTriple().isOSBinFormatMachO()) 5584 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5585 else 5586 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5587 } 5588 5589 public: 5590 AArch64leTargetInfo(const llvm::Triple &Triple) 5591 : AArch64TargetInfo(Triple) { 5592 BigEndian = false; 5593 } 5594 void getTargetDefines(const LangOptions &Opts, 5595 MacroBuilder &Builder) const override { 5596 Builder.defineMacro("__AARCH64EL__"); 5597 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5598 } 5599 }; 5600 5601 class AArch64beTargetInfo : public AArch64TargetInfo { 5602 void setDataLayoutString() override { 5603 assert(!getTriple().isOSBinFormatMachO()); 5604 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5605 } 5606 5607 public: 5608 AArch64beTargetInfo(const llvm::Triple &Triple) 5609 : AArch64TargetInfo(Triple) { } 5610 void getTargetDefines(const LangOptions &Opts, 5611 MacroBuilder &Builder) const override { 5612 Builder.defineMacro("__AARCH64EB__"); 5613 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5614 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5615 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5616 } 5617 }; 5618 5619 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5620 protected: 5621 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5622 MacroBuilder &Builder) const override { 5623 Builder.defineMacro("__AARCH64_SIMD__"); 5624 Builder.defineMacro("__ARM64_ARCH_8__"); 5625 Builder.defineMacro("__ARM_NEON__"); 5626 Builder.defineMacro("__LITTLE_ENDIAN__"); 5627 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5628 Builder.defineMacro("__arm64", "1"); 5629 Builder.defineMacro("__arm64__", "1"); 5630 5631 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5632 } 5633 5634 public: 5635 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5636 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5637 Int64Type = SignedLongLong; 5638 WCharType = SignedInt; 5639 UseSignedCharForObjCBool = false; 5640 5641 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5642 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5643 5644 TheCXXABI.set(TargetCXXABI::iOS64); 5645 } 5646 5647 BuiltinVaListKind getBuiltinVaListKind() const override { 5648 return TargetInfo::CharPtrBuiltinVaList; 5649 } 5650 }; 5651 5652 // Hexagon abstract base class 5653 class HexagonTargetInfo : public TargetInfo { 5654 static const Builtin::Info BuiltinInfo[]; 5655 static const char * const GCCRegNames[]; 5656 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5657 std::string CPU; 5658 bool HasHVX, HasHVXDouble; 5659 5660 public: 5661 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5662 BigEndian = false; 5663 DataLayoutString = "e-m:e-p:32:32:32-" 5664 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-" 5665 "f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"; 5666 SizeType = UnsignedInt; 5667 PtrDiffType = SignedInt; 5668 IntPtrType = SignedInt; 5669 5670 // {} in inline assembly are packet specifiers, not assembly variant 5671 // specifiers. 5672 NoAsmVariants = true; 5673 5674 LargeArrayMinWidth = 64; 5675 LargeArrayAlign = 64; 5676 UseBitFieldTypeAlignment = true; 5677 ZeroLengthBitfieldBoundary = 32; 5678 HasHVX = HasHVXDouble = false; 5679 } 5680 5681 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5682 return llvm::makeArrayRef(BuiltinInfo, 5683 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5684 } 5685 5686 bool validateAsmConstraint(const char *&Name, 5687 TargetInfo::ConstraintInfo &Info) const override { 5688 return true; 5689 } 5690 5691 void getTargetDefines(const LangOptions &Opts, 5692 MacroBuilder &Builder) const override; 5693 5694 bool isCLZForZeroUndef() const override { return false; } 5695 5696 bool hasFeature(StringRef Feature) const override { 5697 return llvm::StringSwitch<bool>(Feature) 5698 .Case("hexagon", true) 5699 .Case("hvx", HasHVX) 5700 .Case("hvx-double", HasHVXDouble) 5701 .Default(false); 5702 } 5703 5704 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5705 StringRef CPU, const std::vector<std::string> &FeaturesVec) 5706 const override; 5707 5708 bool handleTargetFeatures(std::vector<std::string> &Features, 5709 DiagnosticsEngine &Diags) override; 5710 5711 BuiltinVaListKind getBuiltinVaListKind() const override { 5712 return TargetInfo::CharPtrBuiltinVaList; 5713 } 5714 ArrayRef<const char *> getGCCRegNames() const override; 5715 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5716 const char *getClobbers() const override { 5717 return ""; 5718 } 5719 5720 static const char *getHexagonCPUSuffix(StringRef Name) { 5721 return llvm::StringSwitch<const char*>(Name) 5722 .Case("hexagonv4", "4") 5723 .Case("hexagonv5", "5") 5724 .Case("hexagonv55", "55") 5725 .Case("hexagonv60", "60") 5726 .Default(nullptr); 5727 } 5728 5729 bool setCPU(const std::string &Name) override { 5730 if (!getHexagonCPUSuffix(Name)) 5731 return false; 5732 CPU = Name; 5733 return true; 5734 } 5735 5736 int getEHDataRegisterNumber(unsigned RegNo) const override { 5737 return RegNo < 2 ? RegNo : -1; 5738 } 5739 }; 5740 5741 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5742 MacroBuilder &Builder) const { 5743 Builder.defineMacro("__qdsp6__", "1"); 5744 Builder.defineMacro("__hexagon__", "1"); 5745 5746 if (CPU == "hexagonv4") { 5747 Builder.defineMacro("__HEXAGON_V4__"); 5748 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5749 if (Opts.HexagonQdsp6Compat) { 5750 Builder.defineMacro("__QDSP6_V4__"); 5751 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5752 } 5753 } else if (CPU == "hexagonv5") { 5754 Builder.defineMacro("__HEXAGON_V5__"); 5755 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5756 if(Opts.HexagonQdsp6Compat) { 5757 Builder.defineMacro("__QDSP6_V5__"); 5758 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5759 } 5760 } else if (CPU == "hexagonv60") { 5761 Builder.defineMacro("__HEXAGON_V60__"); 5762 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 5763 Builder.defineMacro("__QDSP6_V60__"); 5764 Builder.defineMacro("__QDSP6_ARCH__", "60"); 5765 } 5766 } 5767 5768 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 5769 DiagnosticsEngine &Diags) { 5770 for (auto &F : Features) { 5771 if (F == "+hvx") 5772 HasHVX = true; 5773 else if (F == "-hvx") 5774 HasHVX = HasHVXDouble = false; 5775 else if (F == "+hvx-double") 5776 HasHVX = HasHVXDouble = true; 5777 else if (F == "-hvx-double") 5778 HasHVXDouble = false; 5779 } 5780 return true; 5781 } 5782 5783 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 5784 DiagnosticsEngine &Diags, StringRef CPU, 5785 const std::vector<std::string> &FeaturesVec) const { 5786 // Default for v60: -hvx, -hvx-double. 5787 Features["hvx"] = false; 5788 Features["hvx-double"] = false; 5789 5790 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5791 } 5792 5793 5794 const char *const HexagonTargetInfo::GCCRegNames[] = { 5795 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5796 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5797 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5798 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5799 "p0", "p1", "p2", "p3", 5800 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5801 }; 5802 5803 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 5804 return llvm::makeArrayRef(GCCRegNames); 5805 } 5806 5807 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5808 { { "sp" }, "r29" }, 5809 { { "fp" }, "r30" }, 5810 { { "lr" }, "r31" }, 5811 }; 5812 5813 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 5814 return llvm::makeArrayRef(GCCRegAliases); 5815 } 5816 5817 5818 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5819 #define BUILTIN(ID, TYPE, ATTRS) \ 5820 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5821 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5822 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5823 #include "clang/Basic/BuiltinsHexagon.def" 5824 }; 5825 5826 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5827 class SparcTargetInfo : public TargetInfo { 5828 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5829 static const char * const GCCRegNames[]; 5830 bool SoftFloat; 5831 public: 5832 SparcTargetInfo(const llvm::Triple &Triple) 5833 : TargetInfo(Triple), SoftFloat(false) { 5834 UserLabelPrefix = "_"; 5835 } 5836 5837 bool handleTargetFeatures(std::vector<std::string> &Features, 5838 DiagnosticsEngine &Diags) override { 5839 // The backend doesn't actually handle soft float yet, but in case someone 5840 // is using the support for the front end continue to support it. 5841 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5842 if (Feature != Features.end()) { 5843 SoftFloat = true; 5844 Features.erase(Feature); 5845 } 5846 return true; 5847 } 5848 void getTargetDefines(const LangOptions &Opts, 5849 MacroBuilder &Builder) const override { 5850 DefineStd(Builder, "sparc", Opts); 5851 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5852 5853 if (SoftFloat) 5854 Builder.defineMacro("SOFT_FLOAT", "1"); 5855 } 5856 5857 bool hasFeature(StringRef Feature) const override { 5858 return llvm::StringSwitch<bool>(Feature) 5859 .Case("softfloat", SoftFloat) 5860 .Case("sparc", true) 5861 .Default(false); 5862 } 5863 5864 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5865 // FIXME: Implement! 5866 return None; 5867 } 5868 BuiltinVaListKind getBuiltinVaListKind() const override { 5869 return TargetInfo::VoidPtrBuiltinVaList; 5870 } 5871 ArrayRef<const char *> getGCCRegNames() const override; 5872 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5873 bool validateAsmConstraint(const char *&Name, 5874 TargetInfo::ConstraintInfo &info) const override { 5875 // FIXME: Implement! 5876 switch (*Name) { 5877 case 'I': // Signed 13-bit constant 5878 case 'J': // Zero 5879 case 'K': // 32-bit constant with the low 12 bits clear 5880 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5881 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5882 case 'N': // Same as 'K' but zext (required for SIMode) 5883 case 'O': // The constant 4096 5884 return true; 5885 } 5886 return false; 5887 } 5888 const char *getClobbers() const override { 5889 // FIXME: Implement! 5890 return ""; 5891 } 5892 5893 // No Sparc V7 for now, the backend doesn't support it anyway. 5894 enum CPUKind { 5895 CK_GENERIC, 5896 CK_V8, 5897 CK_SUPERSPARC, 5898 CK_SPARCLITE, 5899 CK_F934, 5900 CK_HYPERSPARC, 5901 CK_SPARCLITE86X, 5902 CK_SPARCLET, 5903 CK_TSC701, 5904 CK_V9, 5905 CK_ULTRASPARC, 5906 CK_ULTRASPARC3, 5907 CK_NIAGARA, 5908 CK_NIAGARA2, 5909 CK_NIAGARA3, 5910 CK_NIAGARA4 5911 } CPU = CK_GENERIC; 5912 5913 enum CPUGeneration { 5914 CG_V8, 5915 CG_V9, 5916 }; 5917 5918 CPUGeneration getCPUGeneration(CPUKind Kind) const { 5919 switch (Kind) { 5920 case CK_GENERIC: 5921 case CK_V8: 5922 case CK_SUPERSPARC: 5923 case CK_SPARCLITE: 5924 case CK_F934: 5925 case CK_HYPERSPARC: 5926 case CK_SPARCLITE86X: 5927 case CK_SPARCLET: 5928 case CK_TSC701: 5929 return CG_V8; 5930 case CK_V9: 5931 case CK_ULTRASPARC: 5932 case CK_ULTRASPARC3: 5933 case CK_NIAGARA: 5934 case CK_NIAGARA2: 5935 case CK_NIAGARA3: 5936 case CK_NIAGARA4: 5937 return CG_V9; 5938 } 5939 llvm_unreachable("Unexpected CPU kind"); 5940 } 5941 5942 CPUKind getCPUKind(StringRef Name) const { 5943 return llvm::StringSwitch<CPUKind>(Name) 5944 .Case("v8", CK_V8) 5945 .Case("supersparc", CK_SUPERSPARC) 5946 .Case("sparclite", CK_SPARCLITE) 5947 .Case("f934", CK_F934) 5948 .Case("hypersparc", CK_HYPERSPARC) 5949 .Case("sparclite86x", CK_SPARCLITE86X) 5950 .Case("sparclet", CK_SPARCLET) 5951 .Case("tsc701", CK_TSC701) 5952 .Case("v9", CK_V9) 5953 .Case("ultrasparc", CK_ULTRASPARC) 5954 .Case("ultrasparc3", CK_ULTRASPARC3) 5955 .Case("niagara", CK_NIAGARA) 5956 .Case("niagara2", CK_NIAGARA2) 5957 .Case("niagara3", CK_NIAGARA3) 5958 .Case("niagara4", CK_NIAGARA4) 5959 .Default(CK_GENERIC); 5960 } 5961 5962 bool setCPU(const std::string &Name) override { 5963 CPU = getCPUKind(Name); 5964 return CPU != CK_GENERIC; 5965 } 5966 }; 5967 5968 const char * const SparcTargetInfo::GCCRegNames[] = { 5969 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5970 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5971 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5972 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5973 }; 5974 5975 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 5976 return llvm::makeArrayRef(GCCRegNames); 5977 } 5978 5979 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5980 { { "g0" }, "r0" }, 5981 { { "g1" }, "r1" }, 5982 { { "g2" }, "r2" }, 5983 { { "g3" }, "r3" }, 5984 { { "g4" }, "r4" }, 5985 { { "g5" }, "r5" }, 5986 { { "g6" }, "r6" }, 5987 { { "g7" }, "r7" }, 5988 { { "o0" }, "r8" }, 5989 { { "o1" }, "r9" }, 5990 { { "o2" }, "r10" }, 5991 { { "o3" }, "r11" }, 5992 { { "o4" }, "r12" }, 5993 { { "o5" }, "r13" }, 5994 { { "o6", "sp" }, "r14" }, 5995 { { "o7" }, "r15" }, 5996 { { "l0" }, "r16" }, 5997 { { "l1" }, "r17" }, 5998 { { "l2" }, "r18" }, 5999 { { "l3" }, "r19" }, 6000 { { "l4" }, "r20" }, 6001 { { "l5" }, "r21" }, 6002 { { "l6" }, "r22" }, 6003 { { "l7" }, "r23" }, 6004 { { "i0" }, "r24" }, 6005 { { "i1" }, "r25" }, 6006 { { "i2" }, "r26" }, 6007 { { "i3" }, "r27" }, 6008 { { "i4" }, "r28" }, 6009 { { "i5" }, "r29" }, 6010 { { "i6", "fp" }, "r30" }, 6011 { { "i7" }, "r31" }, 6012 }; 6013 6014 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6015 return llvm::makeArrayRef(GCCRegAliases); 6016 } 6017 6018 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6019 class SparcV8TargetInfo : public SparcTargetInfo { 6020 public: 6021 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6022 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 6023 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6024 switch (getTriple().getOS()) { 6025 default: 6026 SizeType = UnsignedInt; 6027 IntPtrType = SignedInt; 6028 PtrDiffType = SignedInt; 6029 break; 6030 case llvm::Triple::NetBSD: 6031 case llvm::Triple::OpenBSD: 6032 SizeType = UnsignedLong; 6033 IntPtrType = SignedLong; 6034 PtrDiffType = SignedLong; 6035 break; 6036 } 6037 } 6038 6039 void getTargetDefines(const LangOptions &Opts, 6040 MacroBuilder &Builder) const override { 6041 SparcTargetInfo::getTargetDefines(Opts, Builder); 6042 switch (getCPUGeneration(CPU)) { 6043 case CG_V8: 6044 Builder.defineMacro("__sparcv8"); 6045 if (getTriple().getOS() != llvm::Triple::Solaris) 6046 Builder.defineMacro("__sparcv8__"); 6047 break; 6048 case CG_V9: 6049 Builder.defineMacro("__sparcv9"); 6050 if (getTriple().getOS() != llvm::Triple::Solaris) { 6051 Builder.defineMacro("__sparcv9__"); 6052 Builder.defineMacro("__sparc_v9__"); 6053 } 6054 break; 6055 } 6056 } 6057 }; 6058 6059 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6060 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6061 public: 6062 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 6063 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 6064 BigEndian = false; 6065 } 6066 }; 6067 6068 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6069 class SparcV9TargetInfo : public SparcTargetInfo { 6070 public: 6071 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6072 // FIXME: Support Sparc quad-precision long double? 6073 DataLayoutString = "E-m:e-i64:64-n32:64-S128"; 6074 // This is an LP64 platform. 6075 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6076 6077 // OpenBSD uses long long for int64_t and intmax_t. 6078 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6079 IntMaxType = SignedLongLong; 6080 else 6081 IntMaxType = SignedLong; 6082 Int64Type = IntMaxType; 6083 6084 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6085 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6086 LongDoubleWidth = 128; 6087 LongDoubleAlign = 128; 6088 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6089 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6090 } 6091 6092 void getTargetDefines(const LangOptions &Opts, 6093 MacroBuilder &Builder) const override { 6094 SparcTargetInfo::getTargetDefines(Opts, Builder); 6095 Builder.defineMacro("__sparcv9"); 6096 Builder.defineMacro("__arch64__"); 6097 // Solaris doesn't need these variants, but the BSDs do. 6098 if (getTriple().getOS() != llvm::Triple::Solaris) { 6099 Builder.defineMacro("__sparc64__"); 6100 Builder.defineMacro("__sparc_v9__"); 6101 Builder.defineMacro("__sparcv9__"); 6102 } 6103 } 6104 6105 bool setCPU(const std::string &Name) override { 6106 if (!SparcTargetInfo::setCPU(Name)) 6107 return false; 6108 return getCPUGeneration(CPU) == CG_V9; 6109 } 6110 }; 6111 6112 class SystemZTargetInfo : public TargetInfo { 6113 static const Builtin::Info BuiltinInfo[]; 6114 static const char *const GCCRegNames[]; 6115 std::string CPU; 6116 bool HasTransactionalExecution; 6117 bool HasVector; 6118 6119 public: 6120 SystemZTargetInfo(const llvm::Triple &Triple) 6121 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6122 HasVector(false) { 6123 IntMaxType = SignedLong; 6124 Int64Type = SignedLong; 6125 TLSSupported = true; 6126 IntWidth = IntAlign = 32; 6127 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6128 PointerWidth = PointerAlign = 64; 6129 LongDoubleWidth = 128; 6130 LongDoubleAlign = 64; 6131 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6132 DefaultAlignForAttributeAligned = 64; 6133 MinGlobalAlign = 16; 6134 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 6135 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6136 UserLabelPrefix = "_"; 6137 } 6138 void getTargetDefines(const LangOptions &Opts, 6139 MacroBuilder &Builder) const override { 6140 Builder.defineMacro("__s390__"); 6141 Builder.defineMacro("__s390x__"); 6142 Builder.defineMacro("__zarch__"); 6143 Builder.defineMacro("__LONG_DOUBLE_128__"); 6144 if (HasTransactionalExecution) 6145 Builder.defineMacro("__HTM__"); 6146 if (Opts.ZVector) 6147 Builder.defineMacro("__VEC__", "10301"); 6148 } 6149 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6150 return llvm::makeArrayRef(BuiltinInfo, 6151 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6152 } 6153 6154 ArrayRef<const char *> getGCCRegNames() const override; 6155 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6156 // No aliases. 6157 return None; 6158 } 6159 bool validateAsmConstraint(const char *&Name, 6160 TargetInfo::ConstraintInfo &info) const override; 6161 const char *getClobbers() const override { 6162 // FIXME: Is this really right? 6163 return ""; 6164 } 6165 BuiltinVaListKind getBuiltinVaListKind() const override { 6166 return TargetInfo::SystemZBuiltinVaList; 6167 } 6168 bool setCPU(const std::string &Name) override { 6169 CPU = Name; 6170 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6171 .Case("z10", true) 6172 .Case("z196", true) 6173 .Case("zEC12", true) 6174 .Case("z13", true) 6175 .Default(false); 6176 6177 return CPUKnown; 6178 } 6179 bool 6180 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6181 StringRef CPU, 6182 const std::vector<std::string> &FeaturesVec) const override { 6183 if (CPU == "zEC12") 6184 Features["transactional-execution"] = true; 6185 if (CPU == "z13") { 6186 Features["transactional-execution"] = true; 6187 Features["vector"] = true; 6188 } 6189 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6190 } 6191 6192 bool handleTargetFeatures(std::vector<std::string> &Features, 6193 DiagnosticsEngine &Diags) override { 6194 HasTransactionalExecution = false; 6195 for (const auto &Feature : Features) { 6196 if (Feature == "+transactional-execution") 6197 HasTransactionalExecution = true; 6198 else if (Feature == "+vector") 6199 HasVector = true; 6200 } 6201 // If we use the vector ABI, vector types are 64-bit aligned. 6202 if (HasVector) { 6203 MaxVectorAlign = 64; 6204 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6205 "-v128:64-a:8:16-n32:64"; 6206 } 6207 return true; 6208 } 6209 6210 bool hasFeature(StringRef Feature) const override { 6211 return llvm::StringSwitch<bool>(Feature) 6212 .Case("systemz", true) 6213 .Case("htm", HasTransactionalExecution) 6214 .Case("vx", HasVector) 6215 .Default(false); 6216 } 6217 6218 StringRef getABI() const override { 6219 if (HasVector) 6220 return "vector"; 6221 return ""; 6222 } 6223 6224 bool useFloat128ManglingForLongDouble() const override { 6225 return true; 6226 } 6227 }; 6228 6229 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6230 #define BUILTIN(ID, TYPE, ATTRS) \ 6231 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6232 #include "clang/Basic/BuiltinsSystemZ.def" 6233 }; 6234 6235 const char *const SystemZTargetInfo::GCCRegNames[] = { 6236 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6237 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6238 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6239 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6240 }; 6241 6242 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6243 return llvm::makeArrayRef(GCCRegNames); 6244 } 6245 6246 bool SystemZTargetInfo:: 6247 validateAsmConstraint(const char *&Name, 6248 TargetInfo::ConstraintInfo &Info) const { 6249 switch (*Name) { 6250 default: 6251 return false; 6252 6253 case 'a': // Address register 6254 case 'd': // Data register (equivalent to 'r') 6255 case 'f': // Floating-point register 6256 Info.setAllowsRegister(); 6257 return true; 6258 6259 case 'I': // Unsigned 8-bit constant 6260 case 'J': // Unsigned 12-bit constant 6261 case 'K': // Signed 16-bit constant 6262 case 'L': // Signed 20-bit displacement (on all targets we support) 6263 case 'M': // 0x7fffffff 6264 return true; 6265 6266 case 'Q': // Memory with base and unsigned 12-bit displacement 6267 case 'R': // Likewise, plus an index 6268 case 'S': // Memory with base and signed 20-bit displacement 6269 case 'T': // Likewise, plus an index 6270 Info.setAllowsMemory(); 6271 return true; 6272 } 6273 } 6274 6275 class MSP430TargetInfo : public TargetInfo { 6276 static const char *const GCCRegNames[]; 6277 6278 public: 6279 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6280 BigEndian = false; 6281 TLSSupported = false; 6282 IntWidth = 16; 6283 IntAlign = 16; 6284 LongWidth = 32; 6285 LongLongWidth = 64; 6286 LongAlign = LongLongAlign = 16; 6287 PointerWidth = 16; 6288 PointerAlign = 16; 6289 SuitableAlign = 16; 6290 SizeType = UnsignedInt; 6291 IntMaxType = SignedLongLong; 6292 IntPtrType = SignedInt; 6293 PtrDiffType = SignedInt; 6294 SigAtomicType = SignedLong; 6295 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 6296 UserLabelPrefix = "_"; 6297 } 6298 void getTargetDefines(const LangOptions &Opts, 6299 MacroBuilder &Builder) const override { 6300 Builder.defineMacro("MSP430"); 6301 Builder.defineMacro("__MSP430__"); 6302 // FIXME: defines for different 'flavours' of MCU 6303 } 6304 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6305 // FIXME: Implement. 6306 return None; 6307 } 6308 bool hasFeature(StringRef Feature) const override { 6309 return Feature == "msp430"; 6310 } 6311 ArrayRef<const char *> getGCCRegNames() const override; 6312 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6313 // No aliases. 6314 return None; 6315 } 6316 bool validateAsmConstraint(const char *&Name, 6317 TargetInfo::ConstraintInfo &info) const override { 6318 // FIXME: implement 6319 switch (*Name) { 6320 case 'K': // the constant 1 6321 case 'L': // constant -1^20 .. 1^19 6322 case 'M': // constant 1-4: 6323 return true; 6324 } 6325 // No target constraints for now. 6326 return false; 6327 } 6328 const char *getClobbers() const override { 6329 // FIXME: Is this really right? 6330 return ""; 6331 } 6332 BuiltinVaListKind getBuiltinVaListKind() const override { 6333 // FIXME: implement 6334 return TargetInfo::CharPtrBuiltinVaList; 6335 } 6336 }; 6337 6338 const char *const MSP430TargetInfo::GCCRegNames[] = { 6339 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6340 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6341 6342 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6343 return llvm::makeArrayRef(GCCRegNames); 6344 } 6345 6346 // LLVM and Clang cannot be used directly to output native binaries for 6347 // target, but is used to compile C code to llvm bitcode with correct 6348 // type and alignment information. 6349 // 6350 // TCE uses the llvm bitcode as input and uses it for generating customized 6351 // target processor and program binary. TCE co-design environment is 6352 // publicly available in http://tce.cs.tut.fi 6353 6354 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6355 3, // opencl_global 6356 4, // opencl_local 6357 5, // opencl_constant 6358 // FIXME: generic has to be added to the target 6359 0, // opencl_generic 6360 0, // cuda_device 6361 0, // cuda_constant 6362 0 // cuda_shared 6363 }; 6364 6365 class TCETargetInfo : public TargetInfo { 6366 public: 6367 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6368 TLSSupported = false; 6369 IntWidth = 32; 6370 LongWidth = LongLongWidth = 32; 6371 PointerWidth = 32; 6372 IntAlign = 32; 6373 LongAlign = LongLongAlign = 32; 6374 PointerAlign = 32; 6375 SuitableAlign = 32; 6376 SizeType = UnsignedInt; 6377 IntMaxType = SignedLong; 6378 IntPtrType = SignedInt; 6379 PtrDiffType = SignedInt; 6380 FloatWidth = 32; 6381 FloatAlign = 32; 6382 DoubleWidth = 32; 6383 DoubleAlign = 32; 6384 LongDoubleWidth = 32; 6385 LongDoubleAlign = 32; 6386 FloatFormat = &llvm::APFloat::IEEEsingle; 6387 DoubleFormat = &llvm::APFloat::IEEEsingle; 6388 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6389 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6390 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6391 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6392 UseAddrSpaceMapMangling = true; 6393 UserLabelPrefix = "_"; 6394 } 6395 6396 void getTargetDefines(const LangOptions &Opts, 6397 MacroBuilder &Builder) const override { 6398 DefineStd(Builder, "tce", Opts); 6399 Builder.defineMacro("__TCE__"); 6400 Builder.defineMacro("__TCE_V1__"); 6401 } 6402 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6403 6404 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6405 const char *getClobbers() const override { return ""; } 6406 BuiltinVaListKind getBuiltinVaListKind() const override { 6407 return TargetInfo::VoidPtrBuiltinVaList; 6408 } 6409 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6410 bool validateAsmConstraint(const char *&Name, 6411 TargetInfo::ConstraintInfo &info) const override { 6412 return true; 6413 } 6414 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6415 return None; 6416 } 6417 }; 6418 6419 class BPFTargetInfo : public TargetInfo { 6420 public: 6421 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6422 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6423 SizeType = UnsignedLong; 6424 PtrDiffType = SignedLong; 6425 IntPtrType = SignedLong; 6426 IntMaxType = SignedLong; 6427 Int64Type = SignedLong; 6428 RegParmMax = 5; 6429 if (Triple.getArch() == llvm::Triple::bpfeb) { 6430 BigEndian = true; 6431 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6432 } else { 6433 BigEndian = false; 6434 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6435 } 6436 MaxAtomicPromoteWidth = 64; 6437 MaxAtomicInlineWidth = 64; 6438 TLSSupported = false; 6439 } 6440 void getTargetDefines(const LangOptions &Opts, 6441 MacroBuilder &Builder) const override { 6442 DefineStd(Builder, "bpf", Opts); 6443 Builder.defineMacro("__BPF__"); 6444 } 6445 bool hasFeature(StringRef Feature) const override { 6446 return Feature == "bpf"; 6447 } 6448 6449 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6450 const char *getClobbers() const override { 6451 return ""; 6452 } 6453 BuiltinVaListKind getBuiltinVaListKind() const override { 6454 return TargetInfo::VoidPtrBuiltinVaList; 6455 } 6456 ArrayRef<const char *> getGCCRegNames() const override { 6457 return None; 6458 } 6459 bool validateAsmConstraint(const char *&Name, 6460 TargetInfo::ConstraintInfo &info) const override { 6461 return true; 6462 } 6463 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6464 return None; 6465 } 6466 }; 6467 6468 class MipsTargetInfoBase : public TargetInfo { 6469 virtual void setDataLayoutString() = 0; 6470 6471 static const Builtin::Info BuiltinInfo[]; 6472 std::string CPU; 6473 bool IsMips16; 6474 bool IsMicromips; 6475 bool IsNan2008; 6476 bool IsSingleFloat; 6477 enum MipsFloatABI { 6478 HardFloat, SoftFloat 6479 } FloatABI; 6480 enum DspRevEnum { 6481 NoDSP, DSP1, DSP2 6482 } DspRev; 6483 bool HasMSA; 6484 6485 protected: 6486 bool HasFP64; 6487 std::string ABI; 6488 6489 public: 6490 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6491 const std::string &CPUStr) 6492 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6493 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6494 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6495 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6496 UserLabelPrefix = "_"; 6497 } 6498 6499 bool isNaN2008Default() const { 6500 return CPU == "mips32r6" || CPU == "mips64r6"; 6501 } 6502 6503 bool isFP64Default() const { 6504 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6505 } 6506 6507 bool isNan2008() const override { 6508 return IsNan2008; 6509 } 6510 6511 StringRef getABI() const override { return ABI; } 6512 bool setCPU(const std::string &Name) override { 6513 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6514 getTriple().getArch() == llvm::Triple::mipsel; 6515 CPU = Name; 6516 return llvm::StringSwitch<bool>(Name) 6517 .Case("mips1", IsMips32) 6518 .Case("mips2", IsMips32) 6519 .Case("mips3", true) 6520 .Case("mips4", true) 6521 .Case("mips5", true) 6522 .Case("mips32", IsMips32) 6523 .Case("mips32r2", IsMips32) 6524 .Case("mips32r3", IsMips32) 6525 .Case("mips32r5", IsMips32) 6526 .Case("mips32r6", IsMips32) 6527 .Case("mips64", true) 6528 .Case("mips64r2", true) 6529 .Case("mips64r3", true) 6530 .Case("mips64r5", true) 6531 .Case("mips64r6", true) 6532 .Case("octeon", true) 6533 .Case("p5600", true) 6534 .Default(false); 6535 } 6536 const std::string& getCPU() const { return CPU; } 6537 bool 6538 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6539 StringRef CPU, 6540 const std::vector<std::string> &FeaturesVec) const override { 6541 if (CPU == "octeon") 6542 Features["mips64r2"] = Features["cnmips"] = true; 6543 else 6544 Features[CPU] = true; 6545 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6546 } 6547 6548 void getTargetDefines(const LangOptions &Opts, 6549 MacroBuilder &Builder) const override { 6550 Builder.defineMacro("__mips__"); 6551 Builder.defineMacro("_mips"); 6552 if (Opts.GNUMode) 6553 Builder.defineMacro("mips"); 6554 6555 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6556 6557 switch (FloatABI) { 6558 case HardFloat: 6559 Builder.defineMacro("__mips_hard_float", Twine(1)); 6560 break; 6561 case SoftFloat: 6562 Builder.defineMacro("__mips_soft_float", Twine(1)); 6563 break; 6564 } 6565 6566 if (IsSingleFloat) 6567 Builder.defineMacro("__mips_single_float", Twine(1)); 6568 6569 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6570 Builder.defineMacro("_MIPS_FPSET", 6571 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6572 6573 if (IsMips16) 6574 Builder.defineMacro("__mips16", Twine(1)); 6575 6576 if (IsMicromips) 6577 Builder.defineMacro("__mips_micromips", Twine(1)); 6578 6579 if (IsNan2008) 6580 Builder.defineMacro("__mips_nan2008", Twine(1)); 6581 6582 switch (DspRev) { 6583 default: 6584 break; 6585 case DSP1: 6586 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6587 Builder.defineMacro("__mips_dsp", Twine(1)); 6588 break; 6589 case DSP2: 6590 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6591 Builder.defineMacro("__mips_dspr2", Twine(1)); 6592 Builder.defineMacro("__mips_dsp", Twine(1)); 6593 break; 6594 } 6595 6596 if (HasMSA) 6597 Builder.defineMacro("__mips_msa", Twine(1)); 6598 6599 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6600 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6601 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6602 6603 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6604 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6605 6606 // These shouldn't be defined for MIPS-I but there's no need to check 6607 // for that since MIPS-I isn't supported. 6608 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6609 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6610 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6611 } 6612 6613 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6614 return llvm::makeArrayRef(BuiltinInfo, 6615 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 6616 } 6617 bool hasFeature(StringRef Feature) const override { 6618 return llvm::StringSwitch<bool>(Feature) 6619 .Case("mips", true) 6620 .Case("fp64", HasFP64) 6621 .Default(false); 6622 } 6623 BuiltinVaListKind getBuiltinVaListKind() const override { 6624 return TargetInfo::VoidPtrBuiltinVaList; 6625 } 6626 ArrayRef<const char *> getGCCRegNames() const override { 6627 static const char *const GCCRegNames[] = { 6628 // CPU register names 6629 // Must match second column of GCCRegAliases 6630 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6631 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6632 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6633 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6634 // Floating point register names 6635 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6636 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6637 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6638 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6639 // Hi/lo and condition register names 6640 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6641 "$fcc5","$fcc6","$fcc7", 6642 // MSA register names 6643 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6644 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6645 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6646 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6647 // MSA control register names 6648 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6649 "$msarequest", "$msamap", "$msaunmap" 6650 }; 6651 return llvm::makeArrayRef(GCCRegNames); 6652 } 6653 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 6654 bool validateAsmConstraint(const char *&Name, 6655 TargetInfo::ConstraintInfo &Info) const override { 6656 switch (*Name) { 6657 default: 6658 return false; 6659 case 'r': // CPU registers. 6660 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6661 case 'y': // Equivalent to "r", backward compatibility only. 6662 case 'f': // floating-point registers. 6663 case 'c': // $25 for indirect jumps 6664 case 'l': // lo register 6665 case 'x': // hilo register pair 6666 Info.setAllowsRegister(); 6667 return true; 6668 case 'I': // Signed 16-bit constant 6669 case 'J': // Integer 0 6670 case 'K': // Unsigned 16-bit constant 6671 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6672 case 'M': // Constants not loadable via lui, addiu, or ori 6673 case 'N': // Constant -1 to -65535 6674 case 'O': // A signed 15-bit constant 6675 case 'P': // A constant between 1 go 65535 6676 return true; 6677 case 'R': // An address that can be used in a non-macro load or store 6678 Info.setAllowsMemory(); 6679 return true; 6680 case 'Z': 6681 if (Name[1] == 'C') { // An address usable by ll, and sc. 6682 Info.setAllowsMemory(); 6683 Name++; // Skip over 'Z'. 6684 return true; 6685 } 6686 return false; 6687 } 6688 } 6689 6690 std::string convertConstraint(const char *&Constraint) const override { 6691 std::string R; 6692 switch (*Constraint) { 6693 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6694 if (Constraint[1] == 'C') { 6695 R = std::string("^") + std::string(Constraint, 2); 6696 Constraint++; 6697 return R; 6698 } 6699 break; 6700 } 6701 return TargetInfo::convertConstraint(Constraint); 6702 } 6703 6704 const char *getClobbers() const override { 6705 // In GCC, $1 is not widely used in generated code (it's used only in a few 6706 // specific situations), so there is no real need for users to add it to 6707 // the clobbers list if they want to use it in their inline assembly code. 6708 // 6709 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6710 // code generation, so using it in inline assembly without adding it to the 6711 // clobbers list can cause conflicts between the inline assembly code and 6712 // the surrounding generated code. 6713 // 6714 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6715 // operands, which will conflict with the ".set at" assembler option (which 6716 // we use only for inline assembly, in order to maintain compatibility with 6717 // GCC) and will also conflict with the user's usage of $1. 6718 // 6719 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6720 // register for generated code is to automatically clobber $1 for all inline 6721 // assembly code. 6722 // 6723 // FIXME: We should automatically clobber $1 only for inline assembly code 6724 // which actually uses it. This would allow LLVM to use $1 for inline 6725 // assembly operands if the user's assembly code doesn't use it. 6726 return "~{$1}"; 6727 } 6728 6729 bool handleTargetFeatures(std::vector<std::string> &Features, 6730 DiagnosticsEngine &Diags) override { 6731 IsMips16 = false; 6732 IsMicromips = false; 6733 IsNan2008 = isNaN2008Default(); 6734 IsSingleFloat = false; 6735 FloatABI = HardFloat; 6736 DspRev = NoDSP; 6737 HasFP64 = isFP64Default(); 6738 6739 for (const auto &Feature : Features) { 6740 if (Feature == "+single-float") 6741 IsSingleFloat = true; 6742 else if (Feature == "+soft-float") 6743 FloatABI = SoftFloat; 6744 else if (Feature == "+mips16") 6745 IsMips16 = true; 6746 else if (Feature == "+micromips") 6747 IsMicromips = true; 6748 else if (Feature == "+dsp") 6749 DspRev = std::max(DspRev, DSP1); 6750 else if (Feature == "+dspr2") 6751 DspRev = std::max(DspRev, DSP2); 6752 else if (Feature == "+msa") 6753 HasMSA = true; 6754 else if (Feature == "+fp64") 6755 HasFP64 = true; 6756 else if (Feature == "-fp64") 6757 HasFP64 = false; 6758 else if (Feature == "+nan2008") 6759 IsNan2008 = true; 6760 else if (Feature == "-nan2008") 6761 IsNan2008 = false; 6762 } 6763 6764 setDataLayoutString(); 6765 6766 return true; 6767 } 6768 6769 int getEHDataRegisterNumber(unsigned RegNo) const override { 6770 if (RegNo == 0) return 4; 6771 if (RegNo == 1) return 5; 6772 return -1; 6773 } 6774 6775 bool isCLZForZeroUndef() const override { return false; } 6776 }; 6777 6778 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6779 #define BUILTIN(ID, TYPE, ATTRS) \ 6780 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6781 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6782 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6783 #include "clang/Basic/BuiltinsMips.def" 6784 }; 6785 6786 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6787 public: 6788 Mips32TargetInfoBase(const llvm::Triple &Triple) 6789 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6790 SizeType = UnsignedInt; 6791 PtrDiffType = SignedInt; 6792 Int64Type = SignedLongLong; 6793 IntMaxType = Int64Type; 6794 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6795 } 6796 bool setABI(const std::string &Name) override { 6797 if (Name == "o32" || Name == "eabi") { 6798 ABI = Name; 6799 return true; 6800 } 6801 return false; 6802 } 6803 void getTargetDefines(const LangOptions &Opts, 6804 MacroBuilder &Builder) const override { 6805 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6806 6807 Builder.defineMacro("__mips", "32"); 6808 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6809 6810 const std::string& CPUStr = getCPU(); 6811 if (CPUStr == "mips32") 6812 Builder.defineMacro("__mips_isa_rev", "1"); 6813 else if (CPUStr == "mips32r2") 6814 Builder.defineMacro("__mips_isa_rev", "2"); 6815 else if (CPUStr == "mips32r3") 6816 Builder.defineMacro("__mips_isa_rev", "3"); 6817 else if (CPUStr == "mips32r5") 6818 Builder.defineMacro("__mips_isa_rev", "5"); 6819 else if (CPUStr == "mips32r6") 6820 Builder.defineMacro("__mips_isa_rev", "6"); 6821 6822 if (ABI == "o32") { 6823 Builder.defineMacro("__mips_o32"); 6824 Builder.defineMacro("_ABIO32", "1"); 6825 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6826 } 6827 else if (ABI == "eabi") 6828 Builder.defineMacro("__mips_eabi"); 6829 else 6830 llvm_unreachable("Invalid ABI for Mips32."); 6831 } 6832 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6833 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6834 { { "at" }, "$1" }, 6835 { { "v0" }, "$2" }, 6836 { { "v1" }, "$3" }, 6837 { { "a0" }, "$4" }, 6838 { { "a1" }, "$5" }, 6839 { { "a2" }, "$6" }, 6840 { { "a3" }, "$7" }, 6841 { { "t0" }, "$8" }, 6842 { { "t1" }, "$9" }, 6843 { { "t2" }, "$10" }, 6844 { { "t3" }, "$11" }, 6845 { { "t4" }, "$12" }, 6846 { { "t5" }, "$13" }, 6847 { { "t6" }, "$14" }, 6848 { { "t7" }, "$15" }, 6849 { { "s0" }, "$16" }, 6850 { { "s1" }, "$17" }, 6851 { { "s2" }, "$18" }, 6852 { { "s3" }, "$19" }, 6853 { { "s4" }, "$20" }, 6854 { { "s5" }, "$21" }, 6855 { { "s6" }, "$22" }, 6856 { { "s7" }, "$23" }, 6857 { { "t8" }, "$24" }, 6858 { { "t9" }, "$25" }, 6859 { { "k0" }, "$26" }, 6860 { { "k1" }, "$27" }, 6861 { { "gp" }, "$28" }, 6862 { { "sp","$sp" }, "$29" }, 6863 { { "fp","$fp" }, "$30" }, 6864 { { "ra" }, "$31" } 6865 }; 6866 return llvm::makeArrayRef(GCCRegAliases); 6867 } 6868 }; 6869 6870 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6871 void setDataLayoutString() override { 6872 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6873 } 6874 6875 public: 6876 Mips32EBTargetInfo(const llvm::Triple &Triple) 6877 : Mips32TargetInfoBase(Triple) { 6878 } 6879 void getTargetDefines(const LangOptions &Opts, 6880 MacroBuilder &Builder) const override { 6881 DefineStd(Builder, "MIPSEB", Opts); 6882 Builder.defineMacro("_MIPSEB"); 6883 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6884 } 6885 }; 6886 6887 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6888 void setDataLayoutString() override { 6889 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6890 } 6891 6892 public: 6893 Mips32ELTargetInfo(const llvm::Triple &Triple) 6894 : Mips32TargetInfoBase(Triple) { 6895 BigEndian = false; 6896 } 6897 void getTargetDefines(const LangOptions &Opts, 6898 MacroBuilder &Builder) const override { 6899 DefineStd(Builder, "MIPSEL", Opts); 6900 Builder.defineMacro("_MIPSEL"); 6901 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6902 } 6903 }; 6904 6905 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6906 public: 6907 Mips64TargetInfoBase(const llvm::Triple &Triple) 6908 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6909 LongDoubleWidth = LongDoubleAlign = 128; 6910 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6911 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6912 LongDoubleWidth = LongDoubleAlign = 64; 6913 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6914 } 6915 setN64ABITypes(); 6916 SuitableAlign = 128; 6917 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6918 } 6919 6920 void setN64ABITypes() { 6921 LongWidth = LongAlign = 64; 6922 PointerWidth = PointerAlign = 64; 6923 SizeType = UnsignedLong; 6924 PtrDiffType = SignedLong; 6925 Int64Type = SignedLong; 6926 IntMaxType = Int64Type; 6927 } 6928 6929 void setN32ABITypes() { 6930 LongWidth = LongAlign = 32; 6931 PointerWidth = PointerAlign = 32; 6932 SizeType = UnsignedInt; 6933 PtrDiffType = SignedInt; 6934 Int64Type = SignedLongLong; 6935 IntMaxType = Int64Type; 6936 } 6937 6938 bool setABI(const std::string &Name) override { 6939 if (Name == "n32") { 6940 setN32ABITypes(); 6941 ABI = Name; 6942 return true; 6943 } 6944 if (Name == "n64") { 6945 setN64ABITypes(); 6946 ABI = Name; 6947 return true; 6948 } 6949 return false; 6950 } 6951 6952 void getTargetDefines(const LangOptions &Opts, 6953 MacroBuilder &Builder) const override { 6954 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6955 6956 Builder.defineMacro("__mips", "64"); 6957 Builder.defineMacro("__mips64"); 6958 Builder.defineMacro("__mips64__"); 6959 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6960 6961 const std::string& CPUStr = getCPU(); 6962 if (CPUStr == "mips64") 6963 Builder.defineMacro("__mips_isa_rev", "1"); 6964 else if (CPUStr == "mips64r2") 6965 Builder.defineMacro("__mips_isa_rev", "2"); 6966 else if (CPUStr == "mips64r3") 6967 Builder.defineMacro("__mips_isa_rev", "3"); 6968 else if (CPUStr == "mips64r5") 6969 Builder.defineMacro("__mips_isa_rev", "5"); 6970 else if (CPUStr == "mips64r6") 6971 Builder.defineMacro("__mips_isa_rev", "6"); 6972 6973 if (ABI == "n32") { 6974 Builder.defineMacro("__mips_n32"); 6975 Builder.defineMacro("_ABIN32", "2"); 6976 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6977 } 6978 else if (ABI == "n64") { 6979 Builder.defineMacro("__mips_n64"); 6980 Builder.defineMacro("_ABI64", "3"); 6981 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6982 } 6983 else 6984 llvm_unreachable("Invalid ABI for Mips64."); 6985 6986 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6987 } 6988 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6989 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6990 { { "at" }, "$1" }, 6991 { { "v0" }, "$2" }, 6992 { { "v1" }, "$3" }, 6993 { { "a0" }, "$4" }, 6994 { { "a1" }, "$5" }, 6995 { { "a2" }, "$6" }, 6996 { { "a3" }, "$7" }, 6997 { { "a4" }, "$8" }, 6998 { { "a5" }, "$9" }, 6999 { { "a6" }, "$10" }, 7000 { { "a7" }, "$11" }, 7001 { { "t0" }, "$12" }, 7002 { { "t1" }, "$13" }, 7003 { { "t2" }, "$14" }, 7004 { { "t3" }, "$15" }, 7005 { { "s0" }, "$16" }, 7006 { { "s1" }, "$17" }, 7007 { { "s2" }, "$18" }, 7008 { { "s3" }, "$19" }, 7009 { { "s4" }, "$20" }, 7010 { { "s5" }, "$21" }, 7011 { { "s6" }, "$22" }, 7012 { { "s7" }, "$23" }, 7013 { { "t8" }, "$24" }, 7014 { { "t9" }, "$25" }, 7015 { { "k0" }, "$26" }, 7016 { { "k1" }, "$27" }, 7017 { { "gp" }, "$28" }, 7018 { { "sp","$sp" }, "$29" }, 7019 { { "fp","$fp" }, "$30" }, 7020 { { "ra" }, "$31" } 7021 }; 7022 return llvm::makeArrayRef(GCCRegAliases); 7023 } 7024 7025 bool hasInt128Type() const override { return true; } 7026 }; 7027 7028 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 7029 void setDataLayoutString() override { 7030 if (ABI == "n32") 7031 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7032 else 7033 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7034 7035 } 7036 7037 public: 7038 Mips64EBTargetInfo(const llvm::Triple &Triple) 7039 : Mips64TargetInfoBase(Triple) {} 7040 void getTargetDefines(const LangOptions &Opts, 7041 MacroBuilder &Builder) const override { 7042 DefineStd(Builder, "MIPSEB", Opts); 7043 Builder.defineMacro("_MIPSEB"); 7044 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7045 } 7046 }; 7047 7048 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 7049 void setDataLayoutString() override { 7050 if (ABI == "n32") 7051 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7052 else 7053 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7054 } 7055 public: 7056 Mips64ELTargetInfo(const llvm::Triple &Triple) 7057 : Mips64TargetInfoBase(Triple) { 7058 // Default ABI is n64. 7059 BigEndian = false; 7060 } 7061 void getTargetDefines(const LangOptions &Opts, 7062 MacroBuilder &Builder) const override { 7063 DefineStd(Builder, "MIPSEL", Opts); 7064 Builder.defineMacro("_MIPSEL"); 7065 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7066 } 7067 }; 7068 7069 class PNaClTargetInfo : public TargetInfo { 7070 public: 7071 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7072 BigEndian = false; 7073 this->LongAlign = 32; 7074 this->LongWidth = 32; 7075 this->PointerAlign = 32; 7076 this->PointerWidth = 32; 7077 this->IntMaxType = TargetInfo::SignedLongLong; 7078 this->Int64Type = TargetInfo::SignedLongLong; 7079 this->DoubleAlign = 64; 7080 this->LongDoubleWidth = 64; 7081 this->LongDoubleAlign = 64; 7082 this->SizeType = TargetInfo::UnsignedInt; 7083 this->PtrDiffType = TargetInfo::SignedInt; 7084 this->IntPtrType = TargetInfo::SignedInt; 7085 this->RegParmMax = 0; // Disallow regparm 7086 } 7087 7088 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7089 Builder.defineMacro("__le32__"); 7090 Builder.defineMacro("__pnacl__"); 7091 } 7092 void getTargetDefines(const LangOptions &Opts, 7093 MacroBuilder &Builder) const override { 7094 getArchDefines(Opts, Builder); 7095 } 7096 bool hasFeature(StringRef Feature) const override { 7097 return Feature == "pnacl"; 7098 } 7099 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7100 BuiltinVaListKind getBuiltinVaListKind() const override { 7101 return TargetInfo::PNaClABIBuiltinVaList; 7102 } 7103 ArrayRef<const char *> getGCCRegNames() const override; 7104 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7105 bool validateAsmConstraint(const char *&Name, 7106 TargetInfo::ConstraintInfo &Info) const override { 7107 return false; 7108 } 7109 7110 const char *getClobbers() const override { 7111 return ""; 7112 } 7113 }; 7114 7115 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7116 return None; 7117 } 7118 7119 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7120 return None; 7121 } 7122 7123 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7124 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7125 public: 7126 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 7127 Mips32ELTargetInfo(Triple) { 7128 } 7129 7130 BuiltinVaListKind getBuiltinVaListKind() const override { 7131 return TargetInfo::PNaClABIBuiltinVaList; 7132 } 7133 }; 7134 7135 class Le64TargetInfo : public TargetInfo { 7136 static const Builtin::Info BuiltinInfo[]; 7137 7138 public: 7139 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7140 BigEndian = false; 7141 NoAsmVariants = true; 7142 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7143 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7144 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 7145 } 7146 7147 void getTargetDefines(const LangOptions &Opts, 7148 MacroBuilder &Builder) const override { 7149 DefineStd(Builder, "unix", Opts); 7150 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7151 Builder.defineMacro("__ELF__"); 7152 } 7153 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7154 return llvm::makeArrayRef(BuiltinInfo, 7155 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7156 } 7157 BuiltinVaListKind getBuiltinVaListKind() const override { 7158 return TargetInfo::PNaClABIBuiltinVaList; 7159 } 7160 const char *getClobbers() const override { return ""; } 7161 ArrayRef<const char *> getGCCRegNames() const override { 7162 return None; 7163 } 7164 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7165 return None; 7166 } 7167 bool validateAsmConstraint(const char *&Name, 7168 TargetInfo::ConstraintInfo &Info) const override { 7169 return false; 7170 } 7171 7172 bool hasProtectedVisibility() const override { return false; } 7173 }; 7174 7175 class WebAssemblyTargetInfo : public TargetInfo { 7176 static const Builtin::Info BuiltinInfo[]; 7177 7178 enum SIMDEnum { 7179 NoSIMD, 7180 SIMD128, 7181 } SIMDLevel; 7182 7183 public: 7184 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 7185 : TargetInfo(T), SIMDLevel(NoSIMD) { 7186 BigEndian = false; 7187 NoAsmVariants = true; 7188 SuitableAlign = 128; 7189 LargeArrayMinWidth = 128; 7190 LargeArrayAlign = 128; 7191 SimdDefaultAlign = 128; 7192 SigAtomicType = SignedLong; 7193 LongDoubleWidth = LongDoubleAlign = 128; 7194 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7195 } 7196 7197 protected: 7198 void getTargetDefines(const LangOptions &Opts, 7199 MacroBuilder &Builder) const override { 7200 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7201 if (SIMDLevel >= SIMD128) 7202 Builder.defineMacro("__wasm_simd128__"); 7203 } 7204 7205 private: 7206 bool 7207 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7208 StringRef CPU, 7209 const std::vector<std::string> &FeaturesVec) const override { 7210 if (CPU == "bleeding-edge") 7211 Features["simd128"] = true; 7212 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7213 } 7214 bool hasFeature(StringRef Feature) const final { 7215 return llvm::StringSwitch<bool>(Feature) 7216 .Case("simd128", SIMDLevel >= SIMD128) 7217 .Default(false); 7218 } 7219 bool handleTargetFeatures(std::vector<std::string> &Features, 7220 DiagnosticsEngine &Diags) final { 7221 for (const auto &Feature : Features) { 7222 if (Feature == "+simd128") { 7223 SIMDLevel = std::max(SIMDLevel, SIMD128); 7224 continue; 7225 } 7226 if (Feature == "-simd128") { 7227 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7228 continue; 7229 } 7230 7231 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7232 << "-target-feature"; 7233 return false; 7234 } 7235 return true; 7236 } 7237 bool setCPU(const std::string &Name) final { 7238 return llvm::StringSwitch<bool>(Name) 7239 .Case("mvp", true) 7240 .Case("bleeding-edge", true) 7241 .Case("generic", true) 7242 .Default(false); 7243 } 7244 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7245 return llvm::makeArrayRef(BuiltinInfo, 7246 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7247 } 7248 BuiltinVaListKind getBuiltinVaListKind() const final { 7249 return VoidPtrBuiltinVaList; 7250 } 7251 ArrayRef<const char *> getGCCRegNames() const final { 7252 return None; 7253 } 7254 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7255 return None; 7256 } 7257 bool 7258 validateAsmConstraint(const char *&Name, 7259 TargetInfo::ConstraintInfo &Info) const final { 7260 return false; 7261 } 7262 const char *getClobbers() const final { return ""; } 7263 bool isCLZForZeroUndef() const final { return false; } 7264 bool hasInt128Type() const final { return true; } 7265 IntType getIntTypeByWidth(unsigned BitWidth, 7266 bool IsSigned) const final { 7267 // WebAssembly prefers long long for explicitly 64-bit integers. 7268 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7269 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7270 } 7271 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7272 bool IsSigned) const final { 7273 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7274 return BitWidth == 64 7275 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7276 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7277 } 7278 }; 7279 7280 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7281 #define BUILTIN(ID, TYPE, ATTRS) \ 7282 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7283 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7284 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7285 #include "clang/Basic/BuiltinsWebAssembly.def" 7286 }; 7287 7288 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7289 public: 7290 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7291 : WebAssemblyTargetInfo(T) { 7292 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7293 DataLayoutString = "e-m:e-p:32:32-i64:64-n32:64-S128"; 7294 } 7295 7296 protected: 7297 void getTargetDefines(const LangOptions &Opts, 7298 MacroBuilder &Builder) const override { 7299 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7300 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7301 } 7302 }; 7303 7304 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7305 public: 7306 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7307 : WebAssemblyTargetInfo(T) { 7308 LongAlign = LongWidth = 64; 7309 PointerAlign = PointerWidth = 64; 7310 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7311 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 7312 } 7313 7314 protected: 7315 void getTargetDefines(const LangOptions &Opts, 7316 MacroBuilder &Builder) const override { 7317 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7318 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7319 } 7320 }; 7321 7322 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7323 #define BUILTIN(ID, TYPE, ATTRS) \ 7324 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7325 #include "clang/Basic/BuiltinsLe64.def" 7326 }; 7327 7328 static const unsigned SPIRAddrSpaceMap[] = { 7329 1, // opencl_global 7330 3, // opencl_local 7331 2, // opencl_constant 7332 4, // opencl_generic 7333 0, // cuda_device 7334 0, // cuda_constant 7335 0 // cuda_shared 7336 }; 7337 class SPIRTargetInfo : public TargetInfo { 7338 public: 7339 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7340 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7341 "SPIR target must use unknown OS"); 7342 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7343 "SPIR target must use unknown environment type"); 7344 BigEndian = false; 7345 TLSSupported = false; 7346 LongWidth = LongAlign = 64; 7347 AddrSpaceMap = &SPIRAddrSpaceMap; 7348 UseAddrSpaceMapMangling = true; 7349 // Define available target features 7350 // These must be defined in sorted order! 7351 NoAsmVariants = true; 7352 } 7353 void getTargetDefines(const LangOptions &Opts, 7354 MacroBuilder &Builder) const override { 7355 DefineStd(Builder, "SPIR", Opts); 7356 } 7357 bool hasFeature(StringRef Feature) const override { 7358 return Feature == "spir"; 7359 } 7360 7361 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7362 const char *getClobbers() const override { return ""; } 7363 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7364 bool validateAsmConstraint(const char *&Name, 7365 TargetInfo::ConstraintInfo &info) const override { 7366 return true; 7367 } 7368 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7369 return None; 7370 } 7371 BuiltinVaListKind getBuiltinVaListKind() const override { 7372 return TargetInfo::VoidPtrBuiltinVaList; 7373 } 7374 7375 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7376 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7377 : CCCR_Warning; 7378 } 7379 7380 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7381 return CC_SpirFunction; 7382 } 7383 }; 7384 7385 class SPIR32TargetInfo : public SPIRTargetInfo { 7386 public: 7387 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7388 PointerWidth = PointerAlign = 32; 7389 SizeType = TargetInfo::UnsignedInt; 7390 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7391 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7392 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7393 } 7394 void getTargetDefines(const LangOptions &Opts, 7395 MacroBuilder &Builder) const override { 7396 DefineStd(Builder, "SPIR32", Opts); 7397 } 7398 }; 7399 7400 class SPIR64TargetInfo : public SPIRTargetInfo { 7401 public: 7402 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7403 PointerWidth = PointerAlign = 64; 7404 SizeType = TargetInfo::UnsignedLong; 7405 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7406 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7407 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7408 } 7409 void getTargetDefines(const LangOptions &Opts, 7410 MacroBuilder &Builder) const override { 7411 DefineStd(Builder, "SPIR64", Opts); 7412 } 7413 }; 7414 7415 class XCoreTargetInfo : public TargetInfo { 7416 static const Builtin::Info BuiltinInfo[]; 7417 public: 7418 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7419 BigEndian = false; 7420 NoAsmVariants = true; 7421 LongLongAlign = 32; 7422 SuitableAlign = 32; 7423 DoubleAlign = LongDoubleAlign = 32; 7424 SizeType = UnsignedInt; 7425 PtrDiffType = SignedInt; 7426 IntPtrType = SignedInt; 7427 WCharType = UnsignedChar; 7428 WIntType = UnsignedInt; 7429 UseZeroLengthBitfieldAlignment = true; 7430 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7431 "-f64:32-a:0:32-n32"; 7432 } 7433 void getTargetDefines(const LangOptions &Opts, 7434 MacroBuilder &Builder) const override { 7435 Builder.defineMacro("__XS1B__"); 7436 } 7437 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7438 return llvm::makeArrayRef(BuiltinInfo, 7439 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7440 } 7441 BuiltinVaListKind getBuiltinVaListKind() const override { 7442 return TargetInfo::VoidPtrBuiltinVaList; 7443 } 7444 const char *getClobbers() const override { 7445 return ""; 7446 } 7447 ArrayRef<const char *> getGCCRegNames() const override { 7448 static const char * const GCCRegNames[] = { 7449 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7450 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7451 }; 7452 return llvm::makeArrayRef(GCCRegNames); 7453 } 7454 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7455 return None; 7456 } 7457 bool validateAsmConstraint(const char *&Name, 7458 TargetInfo::ConstraintInfo &Info) const override { 7459 return false; 7460 } 7461 int getEHDataRegisterNumber(unsigned RegNo) const override { 7462 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7463 return (RegNo < 2)? RegNo : -1; 7464 } 7465 }; 7466 7467 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7468 #define BUILTIN(ID, TYPE, ATTRS) \ 7469 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7470 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7471 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7472 #include "clang/Basic/BuiltinsXCore.def" 7473 }; 7474 7475 // x86_32 Android target 7476 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7477 public: 7478 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7479 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7480 SuitableAlign = 32; 7481 LongDoubleWidth = 64; 7482 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7483 } 7484 }; 7485 7486 // x86_64 Android target 7487 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7488 public: 7489 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7490 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7491 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7492 } 7493 7494 bool useFloat128ManglingForLongDouble() const override { 7495 return true; 7496 } 7497 }; 7498 } // end anonymous namespace 7499 7500 //===----------------------------------------------------------------------===// 7501 // Driver code 7502 //===----------------------------------------------------------------------===// 7503 7504 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7505 llvm::Triple::OSType os = Triple.getOS(); 7506 7507 switch (Triple.getArch()) { 7508 default: 7509 return nullptr; 7510 7511 case llvm::Triple::xcore: 7512 return new XCoreTargetInfo(Triple); 7513 7514 case llvm::Triple::hexagon: 7515 return new HexagonTargetInfo(Triple); 7516 7517 case llvm::Triple::aarch64: 7518 if (Triple.isOSDarwin()) 7519 return new DarwinAArch64TargetInfo(Triple); 7520 7521 switch (os) { 7522 case llvm::Triple::CloudABI: 7523 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple); 7524 case llvm::Triple::FreeBSD: 7525 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7526 case llvm::Triple::Linux: 7527 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7528 case llvm::Triple::NetBSD: 7529 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7530 default: 7531 return new AArch64leTargetInfo(Triple); 7532 } 7533 7534 case llvm::Triple::aarch64_be: 7535 switch (os) { 7536 case llvm::Triple::FreeBSD: 7537 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7538 case llvm::Triple::Linux: 7539 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7540 case llvm::Triple::NetBSD: 7541 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7542 default: 7543 return new AArch64beTargetInfo(Triple); 7544 } 7545 7546 case llvm::Triple::arm: 7547 case llvm::Triple::thumb: 7548 if (Triple.isOSBinFormatMachO()) 7549 return new DarwinARMTargetInfo(Triple); 7550 7551 switch (os) { 7552 case llvm::Triple::Linux: 7553 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7554 case llvm::Triple::FreeBSD: 7555 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7556 case llvm::Triple::NetBSD: 7557 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7558 case llvm::Triple::OpenBSD: 7559 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7560 case llvm::Triple::Bitrig: 7561 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7562 case llvm::Triple::RTEMS: 7563 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7564 case llvm::Triple::NaCl: 7565 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7566 case llvm::Triple::Win32: 7567 switch (Triple.getEnvironment()) { 7568 case llvm::Triple::Cygnus: 7569 return new CygwinARMTargetInfo(Triple); 7570 case llvm::Triple::GNU: 7571 return new MinGWARMTargetInfo(Triple); 7572 case llvm::Triple::Itanium: 7573 return new ItaniumWindowsARMleTargetInfo(Triple); 7574 case llvm::Triple::MSVC: 7575 default: // Assume MSVC for unknown environments 7576 return new MicrosoftARMleTargetInfo(Triple); 7577 } 7578 default: 7579 return new ARMleTargetInfo(Triple); 7580 } 7581 7582 case llvm::Triple::armeb: 7583 case llvm::Triple::thumbeb: 7584 if (Triple.isOSDarwin()) 7585 return new DarwinARMTargetInfo(Triple); 7586 7587 switch (os) { 7588 case llvm::Triple::Linux: 7589 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7590 case llvm::Triple::FreeBSD: 7591 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7592 case llvm::Triple::NetBSD: 7593 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7594 case llvm::Triple::OpenBSD: 7595 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7596 case llvm::Triple::Bitrig: 7597 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7598 case llvm::Triple::RTEMS: 7599 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7600 case llvm::Triple::NaCl: 7601 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7602 default: 7603 return new ARMbeTargetInfo(Triple); 7604 } 7605 7606 case llvm::Triple::bpfeb: 7607 case llvm::Triple::bpfel: 7608 return new BPFTargetInfo(Triple); 7609 7610 case llvm::Triple::msp430: 7611 return new MSP430TargetInfo(Triple); 7612 7613 case llvm::Triple::mips: 7614 switch (os) { 7615 case llvm::Triple::Linux: 7616 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7617 case llvm::Triple::RTEMS: 7618 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7619 case llvm::Triple::FreeBSD: 7620 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7621 case llvm::Triple::NetBSD: 7622 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7623 default: 7624 return new Mips32EBTargetInfo(Triple); 7625 } 7626 7627 case llvm::Triple::mipsel: 7628 switch (os) { 7629 case llvm::Triple::Linux: 7630 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7631 case llvm::Triple::RTEMS: 7632 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7633 case llvm::Triple::FreeBSD: 7634 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7635 case llvm::Triple::NetBSD: 7636 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7637 case llvm::Triple::NaCl: 7638 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7639 default: 7640 return new Mips32ELTargetInfo(Triple); 7641 } 7642 7643 case llvm::Triple::mips64: 7644 switch (os) { 7645 case llvm::Triple::Linux: 7646 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7647 case llvm::Triple::RTEMS: 7648 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7649 case llvm::Triple::FreeBSD: 7650 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7651 case llvm::Triple::NetBSD: 7652 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7653 case llvm::Triple::OpenBSD: 7654 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7655 default: 7656 return new Mips64EBTargetInfo(Triple); 7657 } 7658 7659 case llvm::Triple::mips64el: 7660 switch (os) { 7661 case llvm::Triple::Linux: 7662 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7663 case llvm::Triple::RTEMS: 7664 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7665 case llvm::Triple::FreeBSD: 7666 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7667 case llvm::Triple::NetBSD: 7668 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7669 case llvm::Triple::OpenBSD: 7670 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7671 default: 7672 return new Mips64ELTargetInfo(Triple); 7673 } 7674 7675 case llvm::Triple::le32: 7676 switch (os) { 7677 case llvm::Triple::NaCl: 7678 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7679 default: 7680 return nullptr; 7681 } 7682 7683 case llvm::Triple::le64: 7684 return new Le64TargetInfo(Triple); 7685 7686 case llvm::Triple::ppc: 7687 if (Triple.isOSDarwin()) 7688 return new DarwinPPC32TargetInfo(Triple); 7689 switch (os) { 7690 case llvm::Triple::Linux: 7691 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7692 case llvm::Triple::FreeBSD: 7693 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7694 case llvm::Triple::NetBSD: 7695 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7696 case llvm::Triple::OpenBSD: 7697 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7698 case llvm::Triple::RTEMS: 7699 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7700 default: 7701 return new PPC32TargetInfo(Triple); 7702 } 7703 7704 case llvm::Triple::ppc64: 7705 if (Triple.isOSDarwin()) 7706 return new DarwinPPC64TargetInfo(Triple); 7707 switch (os) { 7708 case llvm::Triple::Linux: 7709 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7710 case llvm::Triple::Lv2: 7711 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7712 case llvm::Triple::FreeBSD: 7713 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7714 case llvm::Triple::NetBSD: 7715 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7716 default: 7717 return new PPC64TargetInfo(Triple); 7718 } 7719 7720 case llvm::Triple::ppc64le: 7721 switch (os) { 7722 case llvm::Triple::Linux: 7723 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7724 case llvm::Triple::NetBSD: 7725 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7726 default: 7727 return new PPC64TargetInfo(Triple); 7728 } 7729 7730 case llvm::Triple::nvptx: 7731 return new NVPTX32TargetInfo(Triple); 7732 case llvm::Triple::nvptx64: 7733 return new NVPTX64TargetInfo(Triple); 7734 7735 case llvm::Triple::amdgcn: 7736 case llvm::Triple::r600: 7737 return new AMDGPUTargetInfo(Triple); 7738 7739 case llvm::Triple::sparc: 7740 switch (os) { 7741 case llvm::Triple::Linux: 7742 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7743 case llvm::Triple::Solaris: 7744 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7745 case llvm::Triple::NetBSD: 7746 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7747 case llvm::Triple::OpenBSD: 7748 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7749 case llvm::Triple::RTEMS: 7750 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7751 default: 7752 return new SparcV8TargetInfo(Triple); 7753 } 7754 7755 // The 'sparcel' architecture copies all the above cases except for Solaris. 7756 case llvm::Triple::sparcel: 7757 switch (os) { 7758 case llvm::Triple::Linux: 7759 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7760 case llvm::Triple::NetBSD: 7761 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7762 case llvm::Triple::OpenBSD: 7763 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7764 case llvm::Triple::RTEMS: 7765 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7766 default: 7767 return new SparcV8elTargetInfo(Triple); 7768 } 7769 7770 case llvm::Triple::sparcv9: 7771 switch (os) { 7772 case llvm::Triple::Linux: 7773 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7774 case llvm::Triple::Solaris: 7775 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7776 case llvm::Triple::NetBSD: 7777 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7778 case llvm::Triple::OpenBSD: 7779 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7780 case llvm::Triple::FreeBSD: 7781 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7782 default: 7783 return new SparcV9TargetInfo(Triple); 7784 } 7785 7786 case llvm::Triple::systemz: 7787 switch (os) { 7788 case llvm::Triple::Linux: 7789 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7790 default: 7791 return new SystemZTargetInfo(Triple); 7792 } 7793 7794 case llvm::Triple::tce: 7795 return new TCETargetInfo(Triple); 7796 7797 case llvm::Triple::x86: 7798 if (Triple.isOSDarwin()) 7799 return new DarwinI386TargetInfo(Triple); 7800 7801 switch (os) { 7802 case llvm::Triple::CloudABI: 7803 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7804 case llvm::Triple::Linux: { 7805 switch (Triple.getEnvironment()) { 7806 default: 7807 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7808 case llvm::Triple::Android: 7809 return new AndroidX86_32TargetInfo(Triple); 7810 } 7811 } 7812 case llvm::Triple::DragonFly: 7813 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7814 case llvm::Triple::NetBSD: 7815 return new NetBSDI386TargetInfo(Triple); 7816 case llvm::Triple::OpenBSD: 7817 return new OpenBSDI386TargetInfo(Triple); 7818 case llvm::Triple::Bitrig: 7819 return new BitrigI386TargetInfo(Triple); 7820 case llvm::Triple::FreeBSD: 7821 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7822 case llvm::Triple::KFreeBSD: 7823 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7824 case llvm::Triple::Minix: 7825 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7826 case llvm::Triple::Solaris: 7827 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7828 case llvm::Triple::Win32: { 7829 switch (Triple.getEnvironment()) { 7830 case llvm::Triple::Cygnus: 7831 return new CygwinX86_32TargetInfo(Triple); 7832 case llvm::Triple::GNU: 7833 return new MinGWX86_32TargetInfo(Triple); 7834 case llvm::Triple::Itanium: 7835 case llvm::Triple::MSVC: 7836 default: // Assume MSVC for unknown environments 7837 return new MicrosoftX86_32TargetInfo(Triple); 7838 } 7839 } 7840 case llvm::Triple::Haiku: 7841 return new HaikuX86_32TargetInfo(Triple); 7842 case llvm::Triple::RTEMS: 7843 return new RTEMSX86_32TargetInfo(Triple); 7844 case llvm::Triple::NaCl: 7845 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7846 case llvm::Triple::ELFIAMCU: 7847 return new MCUX86_32TargetInfo(Triple); 7848 default: 7849 return new X86_32TargetInfo(Triple); 7850 } 7851 7852 case llvm::Triple::x86_64: 7853 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7854 return new DarwinX86_64TargetInfo(Triple); 7855 7856 switch (os) { 7857 case llvm::Triple::CloudABI: 7858 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7859 case llvm::Triple::Linux: { 7860 switch (Triple.getEnvironment()) { 7861 default: 7862 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7863 case llvm::Triple::Android: 7864 return new AndroidX86_64TargetInfo(Triple); 7865 } 7866 } 7867 case llvm::Triple::DragonFly: 7868 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7869 case llvm::Triple::NetBSD: 7870 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7871 case llvm::Triple::OpenBSD: 7872 return new OpenBSDX86_64TargetInfo(Triple); 7873 case llvm::Triple::Bitrig: 7874 return new BitrigX86_64TargetInfo(Triple); 7875 case llvm::Triple::FreeBSD: 7876 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7877 case llvm::Triple::KFreeBSD: 7878 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7879 case llvm::Triple::Solaris: 7880 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7881 case llvm::Triple::Win32: { 7882 switch (Triple.getEnvironment()) { 7883 case llvm::Triple::Cygnus: 7884 return new CygwinX86_64TargetInfo(Triple); 7885 case llvm::Triple::GNU: 7886 return new MinGWX86_64TargetInfo(Triple); 7887 case llvm::Triple::MSVC: 7888 default: // Assume MSVC for unknown environments 7889 return new MicrosoftX86_64TargetInfo(Triple); 7890 } 7891 } 7892 case llvm::Triple::NaCl: 7893 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7894 case llvm::Triple::PS4: 7895 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7896 default: 7897 return new X86_64TargetInfo(Triple); 7898 } 7899 7900 case llvm::Triple::spir: { 7901 if (Triple.getOS() != llvm::Triple::UnknownOS || 7902 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7903 return nullptr; 7904 return new SPIR32TargetInfo(Triple); 7905 } 7906 case llvm::Triple::spir64: { 7907 if (Triple.getOS() != llvm::Triple::UnknownOS || 7908 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7909 return nullptr; 7910 return new SPIR64TargetInfo(Triple); 7911 } 7912 case llvm::Triple::wasm32: 7913 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 7914 return nullptr; 7915 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 7916 case llvm::Triple::wasm64: 7917 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 7918 return nullptr; 7919 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 7920 } 7921 } 7922 7923 /// CreateTargetInfo - Return the target info object for the specified target 7924 /// options. 7925 TargetInfo * 7926 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7927 const std::shared_ptr<TargetOptions> &Opts) { 7928 llvm::Triple Triple(Opts->Triple); 7929 7930 // Construct the target 7931 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7932 if (!Target) { 7933 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7934 return nullptr; 7935 } 7936 Target->TargetOpts = Opts; 7937 7938 // Set the target CPU if specified. 7939 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7940 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7941 return nullptr; 7942 } 7943 7944 // Set the target ABI if specified. 7945 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7946 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7947 return nullptr; 7948 } 7949 7950 // Set the fp math unit. 7951 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7952 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7953 return nullptr; 7954 } 7955 7956 // Compute the default target features, we need the target to handle this 7957 // because features may have dependencies on one another. 7958 llvm::StringMap<bool> Features; 7959 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 7960 Opts->FeaturesAsWritten)) 7961 return nullptr; 7962 7963 // Add the features to the compile options. 7964 Opts->Features.clear(); 7965 for (const auto &F : Features) 7966 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 7967 7968 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7969 return nullptr; 7970 7971 return Target.release(); 7972 } 7973