1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 // Ananas target 115 template<typename Target> 116 class AnanasTargetInfo : public OSTargetInfo<Target> { 117 protected: 118 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 119 MacroBuilder &Builder) const override { 120 // Ananas defines 121 Builder.defineMacro("__Ananas__"); 122 Builder.defineMacro("__ELF__"); 123 } 124 public: 125 AnanasTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 126 : OSTargetInfo<Target>(Triple, Opts) {} 127 }; 128 129 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 130 const llvm::Triple &Triple, 131 StringRef &PlatformName, 132 VersionTuple &PlatformMinVersion) { 133 Builder.defineMacro("__APPLE_CC__", "6000"); 134 Builder.defineMacro("__APPLE__"); 135 Builder.defineMacro("__STDC_NO_THREADS__"); 136 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 137 // AddressSanitizer doesn't play well with source fortification, which is on 138 // by default on Darwin. 139 if (Opts.Sanitize.has(SanitizerKind::Address)) 140 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 141 142 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 143 if (!Opts.ObjC1) { 144 // __weak is always defined, for use in blocks and with objc pointers. 145 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 146 Builder.defineMacro("__strong", ""); 147 Builder.defineMacro("__unsafe_unretained", ""); 148 } 149 150 if (Opts.Static) 151 Builder.defineMacro("__STATIC__"); 152 else 153 Builder.defineMacro("__DYNAMIC__"); 154 155 if (Opts.POSIXThreads) 156 Builder.defineMacro("_REENTRANT"); 157 158 // Get the platform type and version number from the triple. 159 unsigned Maj, Min, Rev; 160 if (Triple.isMacOSX()) { 161 Triple.getMacOSXVersion(Maj, Min, Rev); 162 PlatformName = "macos"; 163 } else { 164 Triple.getOSVersion(Maj, Min, Rev); 165 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 166 } 167 168 // If -target arch-pc-win32-macho option specified, we're 169 // generating code for Win32 ABI. No need to emit 170 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 171 if (PlatformName == "win32") { 172 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 173 return; 174 } 175 176 // Set the appropriate OS version define. 177 if (Triple.isiOS()) { 178 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 179 char Str[7]; 180 if (Maj < 10) { 181 Str[0] = '0' + Maj; 182 Str[1] = '0' + (Min / 10); 183 Str[2] = '0' + (Min % 10); 184 Str[3] = '0' + (Rev / 10); 185 Str[4] = '0' + (Rev % 10); 186 Str[5] = '\0'; 187 } else { 188 // Handle versions >= 10. 189 Str[0] = '0' + (Maj / 10); 190 Str[1] = '0' + (Maj % 10); 191 Str[2] = '0' + (Min / 10); 192 Str[3] = '0' + (Min % 10); 193 Str[4] = '0' + (Rev / 10); 194 Str[5] = '0' + (Rev % 10); 195 Str[6] = '\0'; 196 } 197 if (Triple.isTvOS()) 198 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 199 else 200 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 201 Str); 202 203 } else if (Triple.isWatchOS()) { 204 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 205 char Str[6]; 206 Str[0] = '0' + Maj; 207 Str[1] = '0' + (Min / 10); 208 Str[2] = '0' + (Min % 10); 209 Str[3] = '0' + (Rev / 10); 210 Str[4] = '0' + (Rev % 10); 211 Str[5] = '\0'; 212 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 213 } else if (Triple.isMacOSX()) { 214 // Note that the Driver allows versions which aren't representable in the 215 // define (because we only get a single digit for the minor and micro 216 // revision numbers). So, we limit them to the maximum representable 217 // version. 218 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 219 char Str[7]; 220 if (Maj < 10 || (Maj == 10 && Min < 10)) { 221 Str[0] = '0' + (Maj / 10); 222 Str[1] = '0' + (Maj % 10); 223 Str[2] = '0' + std::min(Min, 9U); 224 Str[3] = '0' + std::min(Rev, 9U); 225 Str[4] = '\0'; 226 } else { 227 // Handle versions > 10.9. 228 Str[0] = '0' + (Maj / 10); 229 Str[1] = '0' + (Maj % 10); 230 Str[2] = '0' + (Min / 10); 231 Str[3] = '0' + (Min % 10); 232 Str[4] = '0' + (Rev / 10); 233 Str[5] = '0' + (Rev % 10); 234 Str[6] = '\0'; 235 } 236 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 237 } 238 239 // Tell users about the kernel if there is one. 240 if (Triple.isOSDarwin()) 241 Builder.defineMacro("__MACH__"); 242 243 // The Watch ABI uses Dwarf EH. 244 if(Triple.isWatchABI()) 245 Builder.defineMacro("__ARM_DWARF_EH__"); 246 247 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 248 } 249 250 template<typename Target> 251 class DarwinTargetInfo : public OSTargetInfo<Target> { 252 protected: 253 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 254 MacroBuilder &Builder) const override { 255 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 256 this->PlatformMinVersion); 257 } 258 259 public: 260 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 261 : OSTargetInfo<Target>(Triple, Opts) { 262 // By default, no TLS, and we whitelist permitted architecture/OS 263 // combinations. 264 this->TLSSupported = false; 265 266 if (Triple.isMacOSX()) 267 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 268 else if (Triple.isiOS()) { 269 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 270 if (Triple.getArch() == llvm::Triple::x86_64 || 271 Triple.getArch() == llvm::Triple::aarch64) 272 this->TLSSupported = !Triple.isOSVersionLT(8); 273 else if (Triple.getArch() == llvm::Triple::x86 || 274 Triple.getArch() == llvm::Triple::arm || 275 Triple.getArch() == llvm::Triple::thumb) 276 this->TLSSupported = !Triple.isOSVersionLT(9); 277 } else if (Triple.isWatchOS()) 278 this->TLSSupported = !Triple.isOSVersionLT(2); 279 280 this->MCountName = "\01mcount"; 281 } 282 283 std::string isValidSectionSpecifier(StringRef SR) const override { 284 // Let MCSectionMachO validate this. 285 StringRef Segment, Section; 286 unsigned TAA, StubSize; 287 bool HasTAA; 288 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 289 TAA, HasTAA, StubSize); 290 } 291 292 const char *getStaticInitSectionSpecifier() const override { 293 // FIXME: We should return 0 when building kexts. 294 return "__TEXT,__StaticInit,regular,pure_instructions"; 295 } 296 297 /// Darwin does not support protected visibility. Darwin's "default" 298 /// is very similar to ELF's "protected"; Darwin requires a "weak" 299 /// attribute on declarations that can be dynamically replaced. 300 bool hasProtectedVisibility() const override { 301 return false; 302 } 303 304 unsigned getExnObjectAlignment() const override { 305 // The alignment of an exception object is 8-bytes for darwin since 306 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 307 // and therefore doesn't guarantee 16-byte alignment. 308 return 64; 309 } 310 }; 311 312 313 // DragonFlyBSD Target 314 template<typename Target> 315 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 316 protected: 317 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 318 MacroBuilder &Builder) const override { 319 // DragonFly defines; list based off of gcc output 320 Builder.defineMacro("__DragonFly__"); 321 Builder.defineMacro("__DragonFly_cc_version", "100001"); 322 Builder.defineMacro("__ELF__"); 323 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 324 Builder.defineMacro("__tune_i386__"); 325 DefineStd(Builder, "unix", Opts); 326 } 327 public: 328 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 329 : OSTargetInfo<Target>(Triple, Opts) { 330 switch (Triple.getArch()) { 331 default: 332 case llvm::Triple::x86: 333 case llvm::Triple::x86_64: 334 this->MCountName = ".mcount"; 335 break; 336 } 337 } 338 }; 339 340 #ifndef FREEBSD_CC_VERSION 341 #define FREEBSD_CC_VERSION 0U 342 #endif 343 344 // FreeBSD Target 345 template<typename Target> 346 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 347 protected: 348 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 349 MacroBuilder &Builder) const override { 350 // FreeBSD defines; list based off of gcc output 351 352 unsigned Release = Triple.getOSMajorVersion(); 353 if (Release == 0U) 354 Release = 8U; 355 unsigned CCVersion = FREEBSD_CC_VERSION; 356 if (CCVersion == 0U) 357 CCVersion = Release * 100000U + 1U; 358 359 Builder.defineMacro("__FreeBSD__", Twine(Release)); 360 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 361 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 362 DefineStd(Builder, "unix", Opts); 363 Builder.defineMacro("__ELF__"); 364 365 // On FreeBSD, wchar_t contains the number of the code point as 366 // used by the character set of the locale. These character sets are 367 // not necessarily a superset of ASCII. 368 // 369 // FIXME: This is wrong; the macro refers to the numerical values 370 // of wchar_t *literals*, which are not locale-dependent. However, 371 // FreeBSD systems apparently depend on us getting this wrong, and 372 // setting this to 1 is conforming even if all the basic source 373 // character literals have the same encoding as char and wchar_t. 374 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 375 } 376 public: 377 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 378 : OSTargetInfo<Target>(Triple, Opts) { 379 switch (Triple.getArch()) { 380 default: 381 case llvm::Triple::x86: 382 case llvm::Triple::x86_64: 383 this->MCountName = ".mcount"; 384 break; 385 case llvm::Triple::mips: 386 case llvm::Triple::mipsel: 387 case llvm::Triple::ppc: 388 case llvm::Triple::ppc64: 389 case llvm::Triple::ppc64le: 390 this->MCountName = "_mcount"; 391 break; 392 case llvm::Triple::arm: 393 this->MCountName = "__mcount"; 394 break; 395 } 396 } 397 }; 398 399 // GNU/kFreeBSD Target 400 template<typename Target> 401 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 402 protected: 403 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 404 MacroBuilder &Builder) const override { 405 // GNU/kFreeBSD defines; list based off of gcc output 406 407 DefineStd(Builder, "unix", Opts); 408 Builder.defineMacro("__FreeBSD_kernel__"); 409 Builder.defineMacro("__GLIBC__"); 410 Builder.defineMacro("__ELF__"); 411 if (Opts.POSIXThreads) 412 Builder.defineMacro("_REENTRANT"); 413 if (Opts.CPlusPlus) 414 Builder.defineMacro("_GNU_SOURCE"); 415 } 416 public: 417 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) {} 419 }; 420 421 // Haiku Target 422 template<typename Target> 423 class HaikuTargetInfo : public OSTargetInfo<Target> { 424 protected: 425 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 426 MacroBuilder &Builder) const override { 427 // Haiku defines; list based off of gcc output 428 Builder.defineMacro("__HAIKU__"); 429 Builder.defineMacro("__ELF__"); 430 DefineStd(Builder, "unix", Opts); 431 } 432 public: 433 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 434 : OSTargetInfo<Target>(Triple, Opts) { 435 this->SizeType = TargetInfo::UnsignedLong; 436 this->IntPtrType = TargetInfo::SignedLong; 437 this->PtrDiffType = TargetInfo::SignedLong; 438 this->ProcessIDType = TargetInfo::SignedLong; 439 this->TLSSupported = false; 440 441 } 442 }; 443 444 // Minix Target 445 template<typename Target> 446 class MinixTargetInfo : public OSTargetInfo<Target> { 447 protected: 448 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 449 MacroBuilder &Builder) const override { 450 // Minix defines 451 452 Builder.defineMacro("__minix", "3"); 453 Builder.defineMacro("_EM_WSIZE", "4"); 454 Builder.defineMacro("_EM_PSIZE", "4"); 455 Builder.defineMacro("_EM_SSIZE", "2"); 456 Builder.defineMacro("_EM_LSIZE", "4"); 457 Builder.defineMacro("_EM_FSIZE", "4"); 458 Builder.defineMacro("_EM_DSIZE", "8"); 459 Builder.defineMacro("__ELF__"); 460 DefineStd(Builder, "unix", Opts); 461 } 462 public: 463 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 464 : OSTargetInfo<Target>(Triple, Opts) {} 465 }; 466 467 // Linux target 468 template<typename Target> 469 class LinuxTargetInfo : public OSTargetInfo<Target> { 470 protected: 471 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 472 MacroBuilder &Builder) const override { 473 // Linux defines; list based off of gcc output 474 DefineStd(Builder, "unix", Opts); 475 DefineStd(Builder, "linux", Opts); 476 Builder.defineMacro("__gnu_linux__"); 477 Builder.defineMacro("__ELF__"); 478 if (Triple.isAndroid()) { 479 Builder.defineMacro("__ANDROID__", "1"); 480 unsigned Maj, Min, Rev; 481 Triple.getEnvironmentVersion(Maj, Min, Rev); 482 this->PlatformName = "android"; 483 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 484 if (Maj) 485 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 486 } 487 if (Opts.POSIXThreads) 488 Builder.defineMacro("_REENTRANT"); 489 if (Opts.CPlusPlus) 490 Builder.defineMacro("_GNU_SOURCE"); 491 if (this->HasFloat128) 492 Builder.defineMacro("__FLOAT128__"); 493 } 494 public: 495 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 496 : OSTargetInfo<Target>(Triple, Opts) { 497 this->WIntType = TargetInfo::UnsignedInt; 498 499 switch (Triple.getArch()) { 500 default: 501 break; 502 case llvm::Triple::ppc: 503 case llvm::Triple::ppc64: 504 case llvm::Triple::ppc64le: 505 this->MCountName = "_mcount"; 506 break; 507 case llvm::Triple::x86: 508 case llvm::Triple::x86_64: 509 case llvm::Triple::systemz: 510 this->HasFloat128 = true; 511 break; 512 } 513 } 514 515 const char *getStaticInitSectionSpecifier() const override { 516 return ".text.startup"; 517 } 518 }; 519 520 // NetBSD Target 521 template<typename Target> 522 class NetBSDTargetInfo : public OSTargetInfo<Target> { 523 protected: 524 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 525 MacroBuilder &Builder) const override { 526 // NetBSD defines; list based off of gcc output 527 Builder.defineMacro("__NetBSD__"); 528 Builder.defineMacro("__unix__"); 529 Builder.defineMacro("__ELF__"); 530 if (Opts.POSIXThreads) 531 Builder.defineMacro("_REENTRANT"); 532 533 switch (Triple.getArch()) { 534 default: 535 break; 536 case llvm::Triple::arm: 537 case llvm::Triple::armeb: 538 case llvm::Triple::thumb: 539 case llvm::Triple::thumbeb: 540 Builder.defineMacro("__ARM_DWARF_EH__"); 541 break; 542 } 543 } 544 public: 545 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 546 : OSTargetInfo<Target>(Triple, Opts) { 547 this->MCountName = "_mcount"; 548 } 549 }; 550 551 // OpenBSD Target 552 template<typename Target> 553 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 554 protected: 555 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 556 MacroBuilder &Builder) const override { 557 // OpenBSD defines; list based off of gcc output 558 559 Builder.defineMacro("__OpenBSD__"); 560 DefineStd(Builder, "unix", Opts); 561 Builder.defineMacro("__ELF__"); 562 if (Opts.POSIXThreads) 563 Builder.defineMacro("_REENTRANT"); 564 if (this->HasFloat128) 565 Builder.defineMacro("__FLOAT128__"); 566 } 567 public: 568 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 569 : OSTargetInfo<Target>(Triple, Opts) { 570 this->TLSSupported = false; 571 572 switch (Triple.getArch()) { 573 case llvm::Triple::x86: 574 case llvm::Triple::x86_64: 575 this->HasFloat128 = true; 576 // FALLTHROUGH 577 default: 578 this->MCountName = "__mcount"; 579 break; 580 case llvm::Triple::mips64: 581 case llvm::Triple::mips64el: 582 case llvm::Triple::ppc: 583 case llvm::Triple::sparcv9: 584 this->MCountName = "_mcount"; 585 break; 586 } 587 } 588 }; 589 590 // Bitrig Target 591 template<typename Target> 592 class BitrigTargetInfo : public OSTargetInfo<Target> { 593 protected: 594 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 595 MacroBuilder &Builder) const override { 596 // Bitrig defines; list based off of gcc output 597 598 Builder.defineMacro("__Bitrig__"); 599 DefineStd(Builder, "unix", Opts); 600 Builder.defineMacro("__ELF__"); 601 if (Opts.POSIXThreads) 602 Builder.defineMacro("_REENTRANT"); 603 604 switch (Triple.getArch()) { 605 default: 606 break; 607 case llvm::Triple::arm: 608 case llvm::Triple::armeb: 609 case llvm::Triple::thumb: 610 case llvm::Triple::thumbeb: 611 Builder.defineMacro("__ARM_DWARF_EH__"); 612 break; 613 } 614 } 615 public: 616 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 617 : OSTargetInfo<Target>(Triple, Opts) { 618 this->MCountName = "__mcount"; 619 } 620 }; 621 622 // PSP Target 623 template<typename Target> 624 class PSPTargetInfo : public OSTargetInfo<Target> { 625 protected: 626 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 627 MacroBuilder &Builder) const override { 628 // PSP defines; list based on the output of the pspdev gcc toolchain. 629 Builder.defineMacro("PSP"); 630 Builder.defineMacro("_PSP"); 631 Builder.defineMacro("__psp__"); 632 Builder.defineMacro("__ELF__"); 633 } 634 public: 635 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 636 }; 637 638 // PS3 PPU Target 639 template<typename Target> 640 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 641 protected: 642 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 643 MacroBuilder &Builder) const override { 644 // PS3 PPU defines. 645 Builder.defineMacro("__PPC__"); 646 Builder.defineMacro("__PPU__"); 647 Builder.defineMacro("__CELLOS_LV2__"); 648 Builder.defineMacro("__ELF__"); 649 Builder.defineMacro("__LP32__"); 650 Builder.defineMacro("_ARCH_PPC64"); 651 Builder.defineMacro("__powerpc64__"); 652 } 653 public: 654 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 655 : OSTargetInfo<Target>(Triple, Opts) { 656 this->LongWidth = this->LongAlign = 32; 657 this->PointerWidth = this->PointerAlign = 32; 658 this->IntMaxType = TargetInfo::SignedLongLong; 659 this->Int64Type = TargetInfo::SignedLongLong; 660 this->SizeType = TargetInfo::UnsignedInt; 661 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 662 } 663 }; 664 665 template <typename Target> 666 class PS4OSTargetInfo : public OSTargetInfo<Target> { 667 protected: 668 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 669 MacroBuilder &Builder) const override { 670 Builder.defineMacro("__FreeBSD__", "9"); 671 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 672 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 673 DefineStd(Builder, "unix", Opts); 674 Builder.defineMacro("__ELF__"); 675 Builder.defineMacro("__ORBIS__"); 676 } 677 public: 678 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 679 : OSTargetInfo<Target>(Triple, Opts) { 680 this->WCharType = this->UnsignedShort; 681 682 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 683 this->MaxTLSAlign = 256; 684 685 // On PS4, do not honor explicit bit field alignment, 686 // as in "__attribute__((aligned(2))) int b : 1;". 687 this->UseExplicitBitFieldAlignment = false; 688 689 switch (Triple.getArch()) { 690 default: 691 case llvm::Triple::x86_64: 692 this->MCountName = ".mcount"; 693 break; 694 } 695 } 696 }; 697 698 // Solaris target 699 template<typename Target> 700 class SolarisTargetInfo : public OSTargetInfo<Target> { 701 protected: 702 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 703 MacroBuilder &Builder) const override { 704 DefineStd(Builder, "sun", Opts); 705 DefineStd(Builder, "unix", Opts); 706 Builder.defineMacro("__ELF__"); 707 Builder.defineMacro("__svr4__"); 708 Builder.defineMacro("__SVR4"); 709 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 710 // newer, but to 500 for everything else. feature_test.h has a check to 711 // ensure that you are not using C99 with an old version of X/Open or C89 712 // with a new version. 713 if (Opts.C99) 714 Builder.defineMacro("_XOPEN_SOURCE", "600"); 715 else 716 Builder.defineMacro("_XOPEN_SOURCE", "500"); 717 if (Opts.CPlusPlus) 718 Builder.defineMacro("__C99FEATURES__"); 719 Builder.defineMacro("_LARGEFILE_SOURCE"); 720 Builder.defineMacro("_LARGEFILE64_SOURCE"); 721 Builder.defineMacro("__EXTENSIONS__"); 722 Builder.defineMacro("_REENTRANT"); 723 } 724 public: 725 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 726 : OSTargetInfo<Target>(Triple, Opts) { 727 this->WCharType = this->SignedInt; 728 // FIXME: WIntType should be SignedLong 729 } 730 }; 731 732 // Windows target 733 template<typename Target> 734 class WindowsTargetInfo : public OSTargetInfo<Target> { 735 protected: 736 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 737 MacroBuilder &Builder) const override { 738 Builder.defineMacro("_WIN32"); 739 } 740 void getVisualStudioDefines(const LangOptions &Opts, 741 MacroBuilder &Builder) const { 742 if (Opts.CPlusPlus) { 743 if (Opts.RTTIData) 744 Builder.defineMacro("_CPPRTTI"); 745 746 if (Opts.CXXExceptions) 747 Builder.defineMacro("_CPPUNWIND"); 748 } 749 750 if (Opts.Bool) 751 Builder.defineMacro("__BOOL_DEFINED"); 752 753 if (!Opts.CharIsSigned) 754 Builder.defineMacro("_CHAR_UNSIGNED"); 755 756 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 757 // but it works for now. 758 if (Opts.POSIXThreads) 759 Builder.defineMacro("_MT"); 760 761 if (Opts.MSCompatibilityVersion) { 762 Builder.defineMacro("_MSC_VER", 763 Twine(Opts.MSCompatibilityVersion / 100000)); 764 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 765 // FIXME We cannot encode the revision information into 32-bits 766 Builder.defineMacro("_MSC_BUILD", Twine(1)); 767 768 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 769 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 770 771 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 772 if (Opts.CPlusPlus1z) 773 Builder.defineMacro("_MSVC_LANG", "201403L"); 774 else if (Opts.CPlusPlus14) 775 Builder.defineMacro("_MSVC_LANG", "201402L"); 776 } 777 } 778 779 if (Opts.MicrosoftExt) { 780 Builder.defineMacro("_MSC_EXTENSIONS"); 781 782 if (Opts.CPlusPlus11) { 783 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 784 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 785 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 786 } 787 } 788 789 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 790 } 791 792 public: 793 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 794 : OSTargetInfo<Target>(Triple, Opts) {} 795 }; 796 797 template <typename Target> 798 class NaClTargetInfo : public OSTargetInfo<Target> { 799 protected: 800 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 801 MacroBuilder &Builder) const override { 802 if (Opts.POSIXThreads) 803 Builder.defineMacro("_REENTRANT"); 804 if (Opts.CPlusPlus) 805 Builder.defineMacro("_GNU_SOURCE"); 806 807 DefineStd(Builder, "unix", Opts); 808 Builder.defineMacro("__ELF__"); 809 Builder.defineMacro("__native_client__"); 810 } 811 812 public: 813 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 814 : OSTargetInfo<Target>(Triple, Opts) { 815 this->LongAlign = 32; 816 this->LongWidth = 32; 817 this->PointerAlign = 32; 818 this->PointerWidth = 32; 819 this->IntMaxType = TargetInfo::SignedLongLong; 820 this->Int64Type = TargetInfo::SignedLongLong; 821 this->DoubleAlign = 64; 822 this->LongDoubleWidth = 64; 823 this->LongDoubleAlign = 64; 824 this->LongLongWidth = 64; 825 this->LongLongAlign = 64; 826 this->SizeType = TargetInfo::UnsignedInt; 827 this->PtrDiffType = TargetInfo::SignedInt; 828 this->IntPtrType = TargetInfo::SignedInt; 829 // RegParmMax is inherited from the underlying architecture. 830 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 831 if (Triple.getArch() == llvm::Triple::arm) { 832 // Handled in ARM's setABI(). 833 } else if (Triple.getArch() == llvm::Triple::x86) { 834 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 835 } else if (Triple.getArch() == llvm::Triple::x86_64) { 836 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 837 } else if (Triple.getArch() == llvm::Triple::mipsel) { 838 // Handled on mips' setDataLayout. 839 } else { 840 assert(Triple.getArch() == llvm::Triple::le32); 841 this->resetDataLayout("e-p:32:32-i64:64"); 842 } 843 } 844 }; 845 846 // Fuchsia Target 847 template<typename Target> 848 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 849 protected: 850 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 851 MacroBuilder &Builder) const override { 852 Builder.defineMacro("__Fuchsia__"); 853 Builder.defineMacro("__ELF__"); 854 if (Opts.POSIXThreads) 855 Builder.defineMacro("_REENTRANT"); 856 // Required by the libc++ locale support. 857 if (Opts.CPlusPlus) 858 Builder.defineMacro("_GNU_SOURCE"); 859 } 860 public: 861 FuchsiaTargetInfo(const llvm::Triple &Triple, 862 const TargetOptions &Opts) 863 : OSTargetInfo<Target>(Triple, Opts) { 864 this->MCountName = "__mcount"; 865 } 866 }; 867 868 // WebAssembly target 869 template <typename Target> 870 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 871 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 872 MacroBuilder &Builder) const final { 873 // A common platform macro. 874 if (Opts.POSIXThreads) 875 Builder.defineMacro("_REENTRANT"); 876 // Follow g++ convention and predefine _GNU_SOURCE for C++. 877 if (Opts.CPlusPlus) 878 Builder.defineMacro("_GNU_SOURCE"); 879 } 880 881 // As an optimization, group static init code together in a section. 882 const char *getStaticInitSectionSpecifier() const final { 883 return ".text.__startup"; 884 } 885 886 public: 887 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 888 const TargetOptions &Opts) 889 : OSTargetInfo<Target>(Triple, Opts) { 890 this->MCountName = "__mcount"; 891 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 892 } 893 }; 894 895 //===----------------------------------------------------------------------===// 896 // Specific target implementations. 897 //===----------------------------------------------------------------------===// 898 899 // PPC abstract base class 900 class PPCTargetInfo : public TargetInfo { 901 static const Builtin::Info BuiltinInfo[]; 902 static const char * const GCCRegNames[]; 903 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 904 std::string CPU; 905 906 // Target cpu features. 907 bool HasAltivec; 908 bool HasVSX; 909 bool HasP8Vector; 910 bool HasP8Crypto; 911 bool HasDirectMove; 912 bool HasQPX; 913 bool HasHTM; 914 bool HasBPERMD; 915 bool HasExtDiv; 916 bool HasP9Vector; 917 918 protected: 919 std::string ABI; 920 921 public: 922 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 923 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false), 924 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 925 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 926 SuitableAlign = 128; 927 SimdDefaultAlign = 128; 928 LongDoubleWidth = LongDoubleAlign = 128; 929 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 930 } 931 932 /// \brief Flags for architecture specific defines. 933 typedef enum { 934 ArchDefineNone = 0, 935 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 936 ArchDefinePpcgr = 1 << 1, 937 ArchDefinePpcsq = 1 << 2, 938 ArchDefine440 = 1 << 3, 939 ArchDefine603 = 1 << 4, 940 ArchDefine604 = 1 << 5, 941 ArchDefinePwr4 = 1 << 6, 942 ArchDefinePwr5 = 1 << 7, 943 ArchDefinePwr5x = 1 << 8, 944 ArchDefinePwr6 = 1 << 9, 945 ArchDefinePwr6x = 1 << 10, 946 ArchDefinePwr7 = 1 << 11, 947 ArchDefinePwr8 = 1 << 12, 948 ArchDefinePwr9 = 1 << 13, 949 ArchDefineA2 = 1 << 14, 950 ArchDefineA2q = 1 << 15 951 } ArchDefineTypes; 952 953 // Set the language option for altivec based on our value. 954 void adjust(LangOptions &Opts) override { 955 if (HasAltivec) 956 Opts.AltiVec = 1; 957 TargetInfo::adjust(Opts); 958 } 959 960 // Note: GCC recognizes the following additional cpus: 961 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 962 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 963 // titan, rs64. 964 bool setCPU(const std::string &Name) override { 965 bool CPUKnown = llvm::StringSwitch<bool>(Name) 966 .Case("generic", true) 967 .Case("440", true) 968 .Case("450", true) 969 .Case("601", true) 970 .Case("602", true) 971 .Case("603", true) 972 .Case("603e", true) 973 .Case("603ev", true) 974 .Case("604", true) 975 .Case("604e", true) 976 .Case("620", true) 977 .Case("630", true) 978 .Case("g3", true) 979 .Case("7400", true) 980 .Case("g4", true) 981 .Case("7450", true) 982 .Case("g4+", true) 983 .Case("750", true) 984 .Case("970", true) 985 .Case("g5", true) 986 .Case("a2", true) 987 .Case("a2q", true) 988 .Case("e500mc", true) 989 .Case("e5500", true) 990 .Case("power3", true) 991 .Case("pwr3", true) 992 .Case("power4", true) 993 .Case("pwr4", true) 994 .Case("power5", true) 995 .Case("pwr5", true) 996 .Case("power5x", true) 997 .Case("pwr5x", true) 998 .Case("power6", true) 999 .Case("pwr6", true) 1000 .Case("power6x", true) 1001 .Case("pwr6x", true) 1002 .Case("power7", true) 1003 .Case("pwr7", true) 1004 .Case("power8", true) 1005 .Case("pwr8", true) 1006 .Case("power9", true) 1007 .Case("pwr9", true) 1008 .Case("powerpc", true) 1009 .Case("ppc", true) 1010 .Case("powerpc64", true) 1011 .Case("ppc64", true) 1012 .Case("powerpc64le", true) 1013 .Case("ppc64le", true) 1014 .Default(false); 1015 1016 if (CPUKnown) 1017 CPU = Name; 1018 1019 return CPUKnown; 1020 } 1021 1022 1023 StringRef getABI() const override { return ABI; } 1024 1025 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1026 return llvm::makeArrayRef(BuiltinInfo, 1027 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1028 } 1029 1030 bool isCLZForZeroUndef() const override { return false; } 1031 1032 void getTargetDefines(const LangOptions &Opts, 1033 MacroBuilder &Builder) const override; 1034 1035 bool 1036 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1037 StringRef CPU, 1038 const std::vector<std::string> &FeaturesVec) const override; 1039 1040 bool handleTargetFeatures(std::vector<std::string> &Features, 1041 DiagnosticsEngine &Diags) override; 1042 bool hasFeature(StringRef Feature) const override; 1043 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1044 bool Enabled) const override; 1045 1046 ArrayRef<const char *> getGCCRegNames() const override; 1047 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1048 bool validateAsmConstraint(const char *&Name, 1049 TargetInfo::ConstraintInfo &Info) const override { 1050 switch (*Name) { 1051 default: return false; 1052 case 'O': // Zero 1053 break; 1054 case 'b': // Base register 1055 case 'f': // Floating point register 1056 Info.setAllowsRegister(); 1057 break; 1058 // FIXME: The following are added to allow parsing. 1059 // I just took a guess at what the actions should be. 1060 // Also, is more specific checking needed? I.e. specific registers? 1061 case 'd': // Floating point register (containing 64-bit value) 1062 case 'v': // Altivec vector register 1063 Info.setAllowsRegister(); 1064 break; 1065 case 'w': 1066 switch (Name[1]) { 1067 case 'd':// VSX vector register to hold vector double data 1068 case 'f':// VSX vector register to hold vector float data 1069 case 's':// VSX vector register to hold scalar float data 1070 case 'a':// Any VSX register 1071 case 'c':// An individual CR bit 1072 break; 1073 default: 1074 return false; 1075 } 1076 Info.setAllowsRegister(); 1077 Name++; // Skip over 'w'. 1078 break; 1079 case 'h': // `MQ', `CTR', or `LINK' register 1080 case 'q': // `MQ' register 1081 case 'c': // `CTR' register 1082 case 'l': // `LINK' register 1083 case 'x': // `CR' register (condition register) number 0 1084 case 'y': // `CR' register (condition register) 1085 case 'z': // `XER[CA]' carry bit (part of the XER register) 1086 Info.setAllowsRegister(); 1087 break; 1088 case 'I': // Signed 16-bit constant 1089 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1090 // (use `L' instead for SImode constants) 1091 case 'K': // Unsigned 16-bit constant 1092 case 'L': // Signed 16-bit constant shifted left 16 bits 1093 case 'M': // Constant larger than 31 1094 case 'N': // Exact power of 2 1095 case 'P': // Constant whose negation is a signed 16-bit constant 1096 case 'G': // Floating point constant that can be loaded into a 1097 // register with one instruction per word 1098 case 'H': // Integer/Floating point constant that can be loaded 1099 // into a register using three instructions 1100 break; 1101 case 'm': // Memory operand. Note that on PowerPC targets, m can 1102 // include addresses that update the base register. It 1103 // is therefore only safe to use `m' in an asm statement 1104 // if that asm statement accesses the operand exactly once. 1105 // The asm statement must also use `%U<opno>' as a 1106 // placeholder for the "update" flag in the corresponding 1107 // load or store instruction. For example: 1108 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1109 // is correct but: 1110 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1111 // is not. Use es rather than m if you don't want the base 1112 // register to be updated. 1113 case 'e': 1114 if (Name[1] != 's') 1115 return false; 1116 // es: A "stable" memory operand; that is, one which does not 1117 // include any automodification of the base register. Unlike 1118 // `m', this constraint can be used in asm statements that 1119 // might access the operand several times, or that might not 1120 // access it at all. 1121 Info.setAllowsMemory(); 1122 Name++; // Skip over 'e'. 1123 break; 1124 case 'Q': // Memory operand that is an offset from a register (it is 1125 // usually better to use `m' or `es' in asm statements) 1126 case 'Z': // Memory operand that is an indexed or indirect from a 1127 // register (it is usually better to use `m' or `es' in 1128 // asm statements) 1129 Info.setAllowsMemory(); 1130 Info.setAllowsRegister(); 1131 break; 1132 case 'R': // AIX TOC entry 1133 case 'a': // Address operand that is an indexed or indirect from a 1134 // register (`p' is preferable for asm statements) 1135 case 'S': // Constant suitable as a 64-bit mask operand 1136 case 'T': // Constant suitable as a 32-bit mask operand 1137 case 'U': // System V Release 4 small data area reference 1138 case 't': // AND masks that can be performed by two rldic{l, r} 1139 // instructions 1140 case 'W': // Vector constant that does not require memory 1141 case 'j': // Vector constant that is all zeros. 1142 break; 1143 // End FIXME. 1144 } 1145 return true; 1146 } 1147 std::string convertConstraint(const char *&Constraint) const override { 1148 std::string R; 1149 switch (*Constraint) { 1150 case 'e': 1151 case 'w': 1152 // Two-character constraint; add "^" hint for later parsing. 1153 R = std::string("^") + std::string(Constraint, 2); 1154 Constraint++; 1155 break; 1156 default: 1157 return TargetInfo::convertConstraint(Constraint); 1158 } 1159 return R; 1160 } 1161 const char *getClobbers() const override { 1162 return ""; 1163 } 1164 int getEHDataRegisterNumber(unsigned RegNo) const override { 1165 if (RegNo == 0) return 3; 1166 if (RegNo == 1) return 4; 1167 return -1; 1168 } 1169 1170 bool hasSjLjLowering() const override { 1171 return true; 1172 } 1173 1174 bool useFloat128ManglingForLongDouble() const override { 1175 return LongDoubleWidth == 128 && 1176 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1177 getTriple().isOSBinFormatELF(); 1178 } 1179 }; 1180 1181 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1182 #define BUILTIN(ID, TYPE, ATTRS) \ 1183 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1184 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1185 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1186 #include "clang/Basic/BuiltinsPPC.def" 1187 }; 1188 1189 /// handleTargetFeatures - Perform initialization based on the user 1190 /// configured set of features. 1191 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1192 DiagnosticsEngine &Diags) { 1193 for (const auto &Feature : Features) { 1194 if (Feature == "+altivec") { 1195 HasAltivec = true; 1196 } else if (Feature == "+vsx") { 1197 HasVSX = true; 1198 } else if (Feature == "+bpermd") { 1199 HasBPERMD = true; 1200 } else if (Feature == "+extdiv") { 1201 HasExtDiv = true; 1202 } else if (Feature == "+power8-vector") { 1203 HasP8Vector = true; 1204 } else if (Feature == "+crypto") { 1205 HasP8Crypto = true; 1206 } else if (Feature == "+direct-move") { 1207 HasDirectMove = true; 1208 } else if (Feature == "+qpx") { 1209 HasQPX = true; 1210 } else if (Feature == "+htm") { 1211 HasHTM = true; 1212 } else if (Feature == "+float128") { 1213 HasFloat128 = true; 1214 } else if (Feature == "+power9-vector") { 1215 HasP9Vector = true; 1216 } 1217 // TODO: Finish this list and add an assert that we've handled them 1218 // all. 1219 } 1220 1221 return true; 1222 } 1223 1224 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1225 /// #defines that are not tied to a specific subtarget. 1226 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1227 MacroBuilder &Builder) const { 1228 // Target identification. 1229 Builder.defineMacro("__ppc__"); 1230 Builder.defineMacro("__PPC__"); 1231 Builder.defineMacro("_ARCH_PPC"); 1232 Builder.defineMacro("__powerpc__"); 1233 Builder.defineMacro("__POWERPC__"); 1234 if (PointerWidth == 64) { 1235 Builder.defineMacro("_ARCH_PPC64"); 1236 Builder.defineMacro("__powerpc64__"); 1237 Builder.defineMacro("__ppc64__"); 1238 Builder.defineMacro("__PPC64__"); 1239 } 1240 1241 // Target properties. 1242 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1243 Builder.defineMacro("_LITTLE_ENDIAN"); 1244 } else { 1245 if (getTriple().getOS() != llvm::Triple::NetBSD && 1246 getTriple().getOS() != llvm::Triple::OpenBSD) 1247 Builder.defineMacro("_BIG_ENDIAN"); 1248 } 1249 1250 // ABI options. 1251 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1252 Builder.defineMacro("_CALL_ELF", "1"); 1253 if (ABI == "elfv2") 1254 Builder.defineMacro("_CALL_ELF", "2"); 1255 1256 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 1257 // our suppport post-dates this and it should work on all 64-bit ppc linux 1258 // platforms. It is guaranteed to work on all elfv2 platforms. 1259 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 1260 Builder.defineMacro("_CALL_LINUX", "1"); 1261 1262 // Subtarget options. 1263 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1264 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1265 1266 // FIXME: Should be controlled by command line option. 1267 if (LongDoubleWidth == 128) { 1268 Builder.defineMacro("__LONG_DOUBLE_128__"); 1269 Builder.defineMacro("__LONGDOUBLE128"); 1270 } 1271 1272 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1273 if (ABI == "elfv2" || 1274 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1275 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1276 1277 // CPU identification. 1278 ArchDefineTypes defs = 1279 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1280 .Case("440", ArchDefineName) 1281 .Case("450", ArchDefineName | ArchDefine440) 1282 .Case("601", ArchDefineName) 1283 .Case("602", ArchDefineName | ArchDefinePpcgr) 1284 .Case("603", ArchDefineName | ArchDefinePpcgr) 1285 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1286 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1287 .Case("604", ArchDefineName | ArchDefinePpcgr) 1288 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1289 .Case("620", ArchDefineName | ArchDefinePpcgr) 1290 .Case("630", ArchDefineName | ArchDefinePpcgr) 1291 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1292 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1293 .Case("750", ArchDefineName | ArchDefinePpcgr) 1294 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1295 ArchDefinePpcsq) 1296 .Case("a2", ArchDefineA2) 1297 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1298 .Case("pwr3", ArchDefinePpcgr) 1299 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1300 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1301 ArchDefinePpcsq) 1302 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 | 1303 ArchDefinePpcgr | ArchDefinePpcsq) 1304 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 | 1305 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1306 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x | 1307 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1308 ArchDefinePpcsq) 1309 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 | 1310 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1311 ArchDefinePpcgr | ArchDefinePpcsq) 1312 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x | 1313 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1314 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1315 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 | 1316 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1317 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1318 ArchDefinePpcsq) 1319 .Case("power3", ArchDefinePpcgr) 1320 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1321 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1322 ArchDefinePpcsq) 1323 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1324 ArchDefinePpcgr | ArchDefinePpcsq) 1325 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1326 ArchDefinePwr4 | ArchDefinePpcgr | 1327 ArchDefinePpcsq) 1328 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1329 ArchDefinePwr5 | ArchDefinePwr4 | 1330 ArchDefinePpcgr | ArchDefinePpcsq) 1331 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | 1332 ArchDefinePwr5x | ArchDefinePwr5 | 1333 ArchDefinePwr4 | ArchDefinePpcgr | 1334 ArchDefinePpcsq) 1335 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1336 ArchDefinePwr6 | ArchDefinePwr5x | 1337 ArchDefinePwr5 | ArchDefinePwr4 | 1338 ArchDefinePpcgr | ArchDefinePpcsq) 1339 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 1340 ArchDefinePwr6x | ArchDefinePwr6 | 1341 ArchDefinePwr5x | ArchDefinePwr5 | 1342 ArchDefinePwr4 | ArchDefinePpcgr | 1343 ArchDefinePpcsq) 1344 // powerpc64le automatically defaults to at least power8. 1345 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1346 ArchDefinePwr6 | ArchDefinePwr5x | 1347 ArchDefinePwr5 | ArchDefinePwr4 | 1348 ArchDefinePpcgr | ArchDefinePpcsq) 1349 .Default(ArchDefineNone); 1350 1351 if (defs & ArchDefineName) 1352 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1353 if (defs & ArchDefinePpcgr) 1354 Builder.defineMacro("_ARCH_PPCGR"); 1355 if (defs & ArchDefinePpcsq) 1356 Builder.defineMacro("_ARCH_PPCSQ"); 1357 if (defs & ArchDefine440) 1358 Builder.defineMacro("_ARCH_440"); 1359 if (defs & ArchDefine603) 1360 Builder.defineMacro("_ARCH_603"); 1361 if (defs & ArchDefine604) 1362 Builder.defineMacro("_ARCH_604"); 1363 if (defs & ArchDefinePwr4) 1364 Builder.defineMacro("_ARCH_PWR4"); 1365 if (defs & ArchDefinePwr5) 1366 Builder.defineMacro("_ARCH_PWR5"); 1367 if (defs & ArchDefinePwr5x) 1368 Builder.defineMacro("_ARCH_PWR5X"); 1369 if (defs & ArchDefinePwr6) 1370 Builder.defineMacro("_ARCH_PWR6"); 1371 if (defs & ArchDefinePwr6x) 1372 Builder.defineMacro("_ARCH_PWR6X"); 1373 if (defs & ArchDefinePwr7) 1374 Builder.defineMacro("_ARCH_PWR7"); 1375 if (defs & ArchDefinePwr8) 1376 Builder.defineMacro("_ARCH_PWR8"); 1377 if (defs & ArchDefinePwr9) 1378 Builder.defineMacro("_ARCH_PWR9"); 1379 if (defs & ArchDefineA2) 1380 Builder.defineMacro("_ARCH_A2"); 1381 if (defs & ArchDefineA2q) { 1382 Builder.defineMacro("_ARCH_A2Q"); 1383 Builder.defineMacro("_ARCH_QP"); 1384 } 1385 1386 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1387 Builder.defineMacro("__bg__"); 1388 Builder.defineMacro("__THW_BLUEGENE__"); 1389 Builder.defineMacro("__bgq__"); 1390 Builder.defineMacro("__TOS_BGQ__"); 1391 } 1392 1393 if (HasAltivec) { 1394 Builder.defineMacro("__VEC__", "10206"); 1395 Builder.defineMacro("__ALTIVEC__"); 1396 } 1397 if (HasVSX) 1398 Builder.defineMacro("__VSX__"); 1399 if (HasP8Vector) 1400 Builder.defineMacro("__POWER8_VECTOR__"); 1401 if (HasP8Crypto) 1402 Builder.defineMacro("__CRYPTO__"); 1403 if (HasHTM) 1404 Builder.defineMacro("__HTM__"); 1405 if (HasFloat128) 1406 Builder.defineMacro("__FLOAT128__"); 1407 if (HasP9Vector) 1408 Builder.defineMacro("__POWER9_VECTOR__"); 1409 1410 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1411 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1412 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1413 if (PointerWidth == 64) 1414 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1415 1416 // We have support for the bswap intrinsics so we can define this. 1417 Builder.defineMacro("__HAVE_BSWAP__", "1"); 1418 1419 // FIXME: The following are not yet generated here by Clang, but are 1420 // generated by GCC: 1421 // 1422 // _SOFT_FLOAT_ 1423 // __RECIP_PRECISION__ 1424 // __APPLE_ALTIVEC__ 1425 // __RECIP__ 1426 // __RECIPF__ 1427 // __RSQRTE__ 1428 // __RSQRTEF__ 1429 // _SOFT_DOUBLE_ 1430 // __NO_LWSYNC__ 1431 // __CMODEL_MEDIUM__ 1432 // __CMODEL_LARGE__ 1433 // _CALL_SYSV 1434 // _CALL_DARWIN 1435 // __NO_FPRS__ 1436 } 1437 1438 // Handle explicit options being passed to the compiler here: if we've 1439 // explicitly turned off vsx and turned on any of: 1440 // - power8-vector 1441 // - direct-move 1442 // - float128 1443 // - power9-vector 1444 // then go ahead and error since the customer has expressed an incompatible 1445 // set of options. 1446 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1447 const std::vector<std::string> &FeaturesVec) { 1448 1449 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1450 FeaturesVec.end()) { 1451 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1452 FeaturesVec.end()) { 1453 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1454 << "-mno-vsx"; 1455 return false; 1456 } 1457 1458 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1459 FeaturesVec.end()) { 1460 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1461 << "-mno-vsx"; 1462 return false; 1463 } 1464 1465 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1466 FeaturesVec.end()) { 1467 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1468 << "-mno-vsx"; 1469 return false; 1470 } 1471 1472 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1473 FeaturesVec.end()) { 1474 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1475 << "-mno-vsx"; 1476 return false; 1477 } 1478 } 1479 1480 return true; 1481 } 1482 1483 bool PPCTargetInfo::initFeatureMap( 1484 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1485 const std::vector<std::string> &FeaturesVec) const { 1486 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1487 .Case("7400", true) 1488 .Case("g4", true) 1489 .Case("7450", true) 1490 .Case("g4+", true) 1491 .Case("970", true) 1492 .Case("g5", true) 1493 .Case("pwr6", true) 1494 .Case("pwr7", true) 1495 .Case("pwr8", true) 1496 .Case("pwr9", true) 1497 .Case("ppc64", true) 1498 .Case("ppc64le", true) 1499 .Default(false); 1500 1501 Features["qpx"] = (CPU == "a2q"); 1502 Features["power9-vector"] = (CPU == "pwr9"); 1503 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1504 .Case("ppc64le", true) 1505 .Case("pwr9", true) 1506 .Case("pwr8", true) 1507 .Default(false); 1508 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1509 .Case("ppc64le", true) 1510 .Case("pwr9", true) 1511 .Case("pwr8", true) 1512 .Default(false); 1513 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1514 .Case("ppc64le", true) 1515 .Case("pwr9", true) 1516 .Case("pwr8", true) 1517 .Case("pwr7", true) 1518 .Default(false); 1519 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1520 .Case("ppc64le", true) 1521 .Case("pwr9", true) 1522 .Case("pwr8", true) 1523 .Case("pwr7", true) 1524 .Default(false); 1525 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1526 .Case("ppc64le", true) 1527 .Case("pwr9", true) 1528 .Case("pwr8", true) 1529 .Default(false); 1530 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1531 .Case("ppc64le", true) 1532 .Case("pwr9", true) 1533 .Case("pwr8", true) 1534 .Case("pwr7", true) 1535 .Default(false); 1536 Features["htm"] = llvm::StringSwitch<bool>(CPU) 1537 .Case("ppc64le", true) 1538 .Case("pwr9", true) 1539 .Case("pwr8", true) 1540 .Default(false); 1541 1542 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1543 return false; 1544 1545 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1546 } 1547 1548 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1549 return llvm::StringSwitch<bool>(Feature) 1550 .Case("powerpc", true) 1551 .Case("altivec", HasAltivec) 1552 .Case("vsx", HasVSX) 1553 .Case("power8-vector", HasP8Vector) 1554 .Case("crypto", HasP8Crypto) 1555 .Case("direct-move", HasDirectMove) 1556 .Case("qpx", HasQPX) 1557 .Case("htm", HasHTM) 1558 .Case("bpermd", HasBPERMD) 1559 .Case("extdiv", HasExtDiv) 1560 .Case("float128", HasFloat128) 1561 .Case("power9-vector", HasP9Vector) 1562 .Default(false); 1563 } 1564 1565 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1566 StringRef Name, bool Enabled) const { 1567 if (Enabled) { 1568 // If we're enabling any of the vsx based features then enable vsx and 1569 // altivec. We'll diagnose any problems later. 1570 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name) 1571 .Case("vsx", true) 1572 .Case("direct-move", true) 1573 .Case("power8-vector", true) 1574 .Case("power9-vector", true) 1575 .Case("float128", true) 1576 .Default(false); 1577 if (FeatureHasVSX) 1578 Features["vsx"] = Features["altivec"] = true; 1579 if (Name == "power9-vector") 1580 Features["power8-vector"] = true; 1581 Features[Name] = true; 1582 } else { 1583 // If we're disabling altivec or vsx go ahead and disable all of the vsx 1584 // features. 1585 if ((Name == "altivec") || (Name == "vsx")) 1586 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] = 1587 Features["float128"] = Features["power9-vector"] = false; 1588 if (Name == "power8-vector") 1589 Features["power9-vector"] = false; 1590 Features[Name] = false; 1591 } 1592 } 1593 1594 const char * const PPCTargetInfo::GCCRegNames[] = { 1595 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1596 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1597 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1598 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1599 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1600 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1601 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1602 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1603 "mq", "lr", "ctr", "ap", 1604 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1605 "xer", 1606 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1607 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1608 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1609 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1610 "vrsave", "vscr", 1611 "spe_acc", "spefscr", 1612 "sfp" 1613 }; 1614 1615 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1616 return llvm::makeArrayRef(GCCRegNames); 1617 } 1618 1619 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1620 // While some of these aliases do map to different registers 1621 // they still share the same register name. 1622 { { "0" }, "r0" }, 1623 { { "1"}, "r1" }, 1624 { { "2" }, "r2" }, 1625 { { "3" }, "r3" }, 1626 { { "4" }, "r4" }, 1627 { { "5" }, "r5" }, 1628 { { "6" }, "r6" }, 1629 { { "7" }, "r7" }, 1630 { { "8" }, "r8" }, 1631 { { "9" }, "r9" }, 1632 { { "10" }, "r10" }, 1633 { { "11" }, "r11" }, 1634 { { "12" }, "r12" }, 1635 { { "13" }, "r13" }, 1636 { { "14" }, "r14" }, 1637 { { "15" }, "r15" }, 1638 { { "16" }, "r16" }, 1639 { { "17" }, "r17" }, 1640 { { "18" }, "r18" }, 1641 { { "19" }, "r19" }, 1642 { { "20" }, "r20" }, 1643 { { "21" }, "r21" }, 1644 { { "22" }, "r22" }, 1645 { { "23" }, "r23" }, 1646 { { "24" }, "r24" }, 1647 { { "25" }, "r25" }, 1648 { { "26" }, "r26" }, 1649 { { "27" }, "r27" }, 1650 { { "28" }, "r28" }, 1651 { { "29" }, "r29" }, 1652 { { "30" }, "r30" }, 1653 { { "31" }, "r31" }, 1654 { { "fr0" }, "f0" }, 1655 { { "fr1" }, "f1" }, 1656 { { "fr2" }, "f2" }, 1657 { { "fr3" }, "f3" }, 1658 { { "fr4" }, "f4" }, 1659 { { "fr5" }, "f5" }, 1660 { { "fr6" }, "f6" }, 1661 { { "fr7" }, "f7" }, 1662 { { "fr8" }, "f8" }, 1663 { { "fr9" }, "f9" }, 1664 { { "fr10" }, "f10" }, 1665 { { "fr11" }, "f11" }, 1666 { { "fr12" }, "f12" }, 1667 { { "fr13" }, "f13" }, 1668 { { "fr14" }, "f14" }, 1669 { { "fr15" }, "f15" }, 1670 { { "fr16" }, "f16" }, 1671 { { "fr17" }, "f17" }, 1672 { { "fr18" }, "f18" }, 1673 { { "fr19" }, "f19" }, 1674 { { "fr20" }, "f20" }, 1675 { { "fr21" }, "f21" }, 1676 { { "fr22" }, "f22" }, 1677 { { "fr23" }, "f23" }, 1678 { { "fr24" }, "f24" }, 1679 { { "fr25" }, "f25" }, 1680 { { "fr26" }, "f26" }, 1681 { { "fr27" }, "f27" }, 1682 { { "fr28" }, "f28" }, 1683 { { "fr29" }, "f29" }, 1684 { { "fr30" }, "f30" }, 1685 { { "fr31" }, "f31" }, 1686 { { "cc" }, "cr0" }, 1687 }; 1688 1689 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1690 return llvm::makeArrayRef(GCCRegAliases); 1691 } 1692 1693 class PPC32TargetInfo : public PPCTargetInfo { 1694 public: 1695 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1696 : PPCTargetInfo(Triple, Opts) { 1697 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1698 1699 switch (getTriple().getOS()) { 1700 case llvm::Triple::Linux: 1701 case llvm::Triple::FreeBSD: 1702 case llvm::Triple::NetBSD: 1703 SizeType = UnsignedInt; 1704 PtrDiffType = SignedInt; 1705 IntPtrType = SignedInt; 1706 break; 1707 default: 1708 break; 1709 } 1710 1711 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1712 LongDoubleWidth = LongDoubleAlign = 64; 1713 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1714 } 1715 1716 // PPC32 supports atomics up to 4 bytes. 1717 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1718 } 1719 1720 BuiltinVaListKind getBuiltinVaListKind() const override { 1721 // This is the ELF definition, and is overridden by the Darwin sub-target 1722 return TargetInfo::PowerABIBuiltinVaList; 1723 } 1724 }; 1725 1726 // Note: ABI differences may eventually require us to have a separate 1727 // TargetInfo for little endian. 1728 class PPC64TargetInfo : public PPCTargetInfo { 1729 public: 1730 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1731 : PPCTargetInfo(Triple, Opts) { 1732 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1733 IntMaxType = SignedLong; 1734 Int64Type = SignedLong; 1735 1736 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1737 resetDataLayout("e-m:e-i64:64-n32:64"); 1738 ABI = "elfv2"; 1739 } else { 1740 resetDataLayout("E-m:e-i64:64-n32:64"); 1741 ABI = "elfv1"; 1742 } 1743 1744 switch (getTriple().getOS()) { 1745 case llvm::Triple::FreeBSD: 1746 LongDoubleWidth = LongDoubleAlign = 64; 1747 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1748 break; 1749 case llvm::Triple::NetBSD: 1750 IntMaxType = SignedLongLong; 1751 Int64Type = SignedLongLong; 1752 break; 1753 default: 1754 break; 1755 } 1756 1757 // PPC64 supports atomics up to 8 bytes. 1758 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1759 } 1760 BuiltinVaListKind getBuiltinVaListKind() const override { 1761 return TargetInfo::CharPtrBuiltinVaList; 1762 } 1763 // PPC64 Linux-specific ABI options. 1764 bool setABI(const std::string &Name) override { 1765 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1766 ABI = Name; 1767 return true; 1768 } 1769 return false; 1770 } 1771 }; 1772 1773 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1774 public: 1775 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1776 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1777 HasAlignMac68kSupport = true; 1778 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1779 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1780 LongLongAlign = 32; 1781 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1782 } 1783 BuiltinVaListKind getBuiltinVaListKind() const override { 1784 return TargetInfo::CharPtrBuiltinVaList; 1785 } 1786 }; 1787 1788 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1789 public: 1790 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1791 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1792 HasAlignMac68kSupport = true; 1793 resetDataLayout("E-m:o-i64:64-n32:64"); 1794 } 1795 }; 1796 1797 static const unsigned NVPTXAddrSpaceMap[] = { 1798 0, // Default 1799 1, // opencl_global 1800 3, // opencl_local 1801 4, // opencl_constant 1802 // FIXME: generic has to be added to the target 1803 0, // opencl_generic 1804 1, // cuda_device 1805 4, // cuda_constant 1806 3, // cuda_shared 1807 }; 1808 1809 class NVPTXTargetInfo : public TargetInfo { 1810 static const char *const GCCRegNames[]; 1811 static const Builtin::Info BuiltinInfo[]; 1812 CudaArch GPU; 1813 std::unique_ptr<TargetInfo> HostTarget; 1814 1815 public: 1816 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1817 unsigned TargetPointerWidth) 1818 : TargetInfo(Triple) { 1819 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1820 "NVPTX only supports 32- and 64-bit modes."); 1821 1822 TLSSupported = false; 1823 AddrSpaceMap = &NVPTXAddrSpaceMap; 1824 UseAddrSpaceMapMangling = true; 1825 1826 // Define available target features 1827 // These must be defined in sorted order! 1828 NoAsmVariants = true; 1829 GPU = CudaArch::SM_20; 1830 1831 if (TargetPointerWidth == 32) 1832 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1833 else 1834 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1835 1836 // If possible, get a TargetInfo for our host triple, so we can match its 1837 // types. 1838 llvm::Triple HostTriple(Opts.HostTriple); 1839 if (!HostTriple.isNVPTX()) 1840 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1841 1842 // If no host target, make some guesses about the data layout and return. 1843 if (!HostTarget) { 1844 LongWidth = LongAlign = TargetPointerWidth; 1845 PointerWidth = PointerAlign = TargetPointerWidth; 1846 switch (TargetPointerWidth) { 1847 case 32: 1848 SizeType = TargetInfo::UnsignedInt; 1849 PtrDiffType = TargetInfo::SignedInt; 1850 IntPtrType = TargetInfo::SignedInt; 1851 break; 1852 case 64: 1853 SizeType = TargetInfo::UnsignedLong; 1854 PtrDiffType = TargetInfo::SignedLong; 1855 IntPtrType = TargetInfo::SignedLong; 1856 break; 1857 default: 1858 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1859 } 1860 return; 1861 } 1862 1863 // Copy properties from host target. 1864 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1865 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1866 BoolWidth = HostTarget->getBoolWidth(); 1867 BoolAlign = HostTarget->getBoolAlign(); 1868 IntWidth = HostTarget->getIntWidth(); 1869 IntAlign = HostTarget->getIntAlign(); 1870 HalfWidth = HostTarget->getHalfWidth(); 1871 HalfAlign = HostTarget->getHalfAlign(); 1872 FloatWidth = HostTarget->getFloatWidth(); 1873 FloatAlign = HostTarget->getFloatAlign(); 1874 DoubleWidth = HostTarget->getDoubleWidth(); 1875 DoubleAlign = HostTarget->getDoubleAlign(); 1876 LongWidth = HostTarget->getLongWidth(); 1877 LongAlign = HostTarget->getLongAlign(); 1878 LongLongWidth = HostTarget->getLongLongWidth(); 1879 LongLongAlign = HostTarget->getLongLongAlign(); 1880 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1881 NewAlign = HostTarget->getNewAlign(); 1882 DefaultAlignForAttributeAligned = 1883 HostTarget->getDefaultAlignForAttributeAligned(); 1884 SizeType = HostTarget->getSizeType(); 1885 IntMaxType = HostTarget->getIntMaxType(); 1886 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1887 IntPtrType = HostTarget->getIntPtrType(); 1888 WCharType = HostTarget->getWCharType(); 1889 WIntType = HostTarget->getWIntType(); 1890 Char16Type = HostTarget->getChar16Type(); 1891 Char32Type = HostTarget->getChar32Type(); 1892 Int64Type = HostTarget->getInt64Type(); 1893 SigAtomicType = HostTarget->getSigAtomicType(); 1894 ProcessIDType = HostTarget->getProcessIDType(); 1895 1896 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1897 UseZeroLengthBitfieldAlignment = 1898 HostTarget->useZeroLengthBitfieldAlignment(); 1899 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1900 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1901 1902 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1903 // we need those macros to be identical on host and device, because (among 1904 // other things) they affect which standard library classes are defined, and 1905 // we need all classes to be defined on both the host and device. 1906 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1907 1908 // Properties intentionally not copied from host: 1909 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1910 // host/device boundary. 1911 // - SuitableAlign: Not visible across the host/device boundary, and may 1912 // correctly be different on host/device, e.g. if host has wider vector 1913 // types than device. 1914 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1915 // as its double type, but that's not necessarily true on the host. 1916 // TODO: nvcc emits a warning when using long double on device; we should 1917 // do the same. 1918 } 1919 void getTargetDefines(const LangOptions &Opts, 1920 MacroBuilder &Builder) const override { 1921 Builder.defineMacro("__PTX__"); 1922 Builder.defineMacro("__NVPTX__"); 1923 if (Opts.CUDAIsDevice) { 1924 // Set __CUDA_ARCH__ for the GPU specified. 1925 std::string CUDAArchCode = [this] { 1926 switch (GPU) { 1927 case CudaArch::UNKNOWN: 1928 assert(false && "No GPU arch when compiling CUDA device code."); 1929 return ""; 1930 case CudaArch::SM_20: 1931 return "200"; 1932 case CudaArch::SM_21: 1933 return "210"; 1934 case CudaArch::SM_30: 1935 return "300"; 1936 case CudaArch::SM_32: 1937 return "320"; 1938 case CudaArch::SM_35: 1939 return "350"; 1940 case CudaArch::SM_37: 1941 return "370"; 1942 case CudaArch::SM_50: 1943 return "500"; 1944 case CudaArch::SM_52: 1945 return "520"; 1946 case CudaArch::SM_53: 1947 return "530"; 1948 case CudaArch::SM_60: 1949 return "600"; 1950 case CudaArch::SM_61: 1951 return "610"; 1952 case CudaArch::SM_62: 1953 return "620"; 1954 } 1955 llvm_unreachable("unhandled CudaArch"); 1956 }(); 1957 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1958 } 1959 } 1960 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1961 return llvm::makeArrayRef(BuiltinInfo, 1962 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1963 } 1964 bool 1965 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1966 StringRef CPU, 1967 const std::vector<std::string> &FeaturesVec) const override { 1968 Features["satom"] = GPU >= CudaArch::SM_60; 1969 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1970 } 1971 1972 bool hasFeature(StringRef Feature) const override { 1973 return llvm::StringSwitch<bool>(Feature) 1974 .Cases("ptx", "nvptx", true) 1975 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1976 .Default(false); 1977 } 1978 1979 ArrayRef<const char *> getGCCRegNames() const override; 1980 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1981 // No aliases. 1982 return None; 1983 } 1984 bool validateAsmConstraint(const char *&Name, 1985 TargetInfo::ConstraintInfo &Info) const override { 1986 switch (*Name) { 1987 default: 1988 return false; 1989 case 'c': 1990 case 'h': 1991 case 'r': 1992 case 'l': 1993 case 'f': 1994 case 'd': 1995 Info.setAllowsRegister(); 1996 return true; 1997 } 1998 } 1999 const char *getClobbers() const override { 2000 // FIXME: Is this really right? 2001 return ""; 2002 } 2003 BuiltinVaListKind getBuiltinVaListKind() const override { 2004 // FIXME: implement 2005 return TargetInfo::CharPtrBuiltinVaList; 2006 } 2007 bool setCPU(const std::string &Name) override { 2008 GPU = StringToCudaArch(Name); 2009 return GPU != CudaArch::UNKNOWN; 2010 } 2011 void setSupportedOpenCLOpts() override { 2012 auto &Opts = getSupportedOpenCLOpts(); 2013 Opts.support("cl_clang_storage_class_specifiers"); 2014 Opts.support("cl_khr_gl_sharing"); 2015 Opts.support("cl_khr_icd"); 2016 2017 Opts.support("cl_khr_fp64"); 2018 Opts.support("cl_khr_byte_addressable_store"); 2019 Opts.support("cl_khr_global_int32_base_atomics"); 2020 Opts.support("cl_khr_global_int32_extended_atomics"); 2021 Opts.support("cl_khr_local_int32_base_atomics"); 2022 Opts.support("cl_khr_local_int32_extended_atomics"); 2023 } 2024 2025 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2026 // CUDA compilations support all of the host's calling conventions. 2027 // 2028 // TODO: We should warn if you apply a non-default CC to anything other than 2029 // a host function. 2030 if (HostTarget) 2031 return HostTarget->checkCallingConvention(CC); 2032 return CCCR_Warning; 2033 } 2034 }; 2035 2036 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 2037 #define BUILTIN(ID, TYPE, ATTRS) \ 2038 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2039 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2040 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2041 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2042 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2043 #include "clang/Basic/BuiltinsNVPTX.def" 2044 }; 2045 2046 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 2047 2048 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 2049 return llvm::makeArrayRef(GCCRegNames); 2050 } 2051 2052 static const LangAS::Map AMDGPUNonOpenCLPrivateIsZeroMap = { 2053 4, // Default 2054 1, // opencl_global 2055 3, // opencl_local 2056 2, // opencl_constant 2057 4, // opencl_generic 2058 1, // cuda_device 2059 2, // cuda_constant 2060 3 // cuda_shared 2061 }; 2062 static const LangAS::Map AMDGPUNonOpenCLGenericIsZeroMap = { 2063 0, // Default 2064 1, // opencl_global 2065 3, // opencl_local 2066 2, // opencl_constant 2067 0, // opencl_generic 2068 1, // cuda_device 2069 2, // cuda_constant 2070 3 // cuda_shared 2071 }; 2072 static const LangAS::Map AMDGPUOpenCLPrivateIsZeroMap = { 2073 0, // Default 2074 1, // opencl_global 2075 3, // opencl_local 2076 2, // opencl_constant 2077 4, // opencl_generic 2078 1, // cuda_device 2079 2, // cuda_constant 2080 3 // cuda_shared 2081 }; 2082 static const LangAS::Map AMDGPUOpenCLGenericIsZeroMap = { 2083 5, // Default 2084 1, // opencl_global 2085 3, // opencl_local 2086 2, // opencl_constant 2087 0, // opencl_generic 2088 1, // cuda_device 2089 2, // cuda_constant 2090 3 // cuda_shared 2091 }; 2092 2093 // If you edit the description strings, make sure you update 2094 // getPointerWidthV(). 2095 2096 static const char *const DataLayoutStringR600 = 2097 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2098 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2099 2100 static const char *const DataLayoutStringSIPrivateIsZero = 2101 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2102 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2103 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2104 2105 static const char *const DataLayoutStringSIGenericIsZero = 2106 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" 2107 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2108 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; 2109 2110 class AMDGPUTargetInfo final : public TargetInfo { 2111 static const Builtin::Info BuiltinInfo[]; 2112 static const char * const GCCRegNames[]; 2113 2114 struct AddrSpace { 2115 unsigned Generic, Global, Local, Constant, Private; 2116 AddrSpace(bool IsGenericZero_ = false){ 2117 if (IsGenericZero_) { 2118 Generic = 0; 2119 Global = 1; 2120 Local = 3; 2121 Constant = 2; 2122 Private = 5; 2123 } else { 2124 Generic = 4; 2125 Global = 1; 2126 Local = 3; 2127 Constant = 2; 2128 Private = 0; 2129 } 2130 } 2131 }; 2132 2133 /// \brief The GPU profiles supported by the AMDGPU target. 2134 enum GPUKind { 2135 GK_NONE, 2136 GK_R600, 2137 GK_R600_DOUBLE_OPS, 2138 GK_R700, 2139 GK_R700_DOUBLE_OPS, 2140 GK_EVERGREEN, 2141 GK_EVERGREEN_DOUBLE_OPS, 2142 GK_NORTHERN_ISLANDS, 2143 GK_CAYMAN, 2144 GK_GFX6, 2145 GK_GFX7, 2146 GK_GFX8, 2147 GK_GFX9 2148 } GPU; 2149 2150 bool hasFP64:1; 2151 bool hasFMAF:1; 2152 bool hasLDEXPF:1; 2153 const AddrSpace AS; 2154 2155 static bool hasFullSpeedFMAF32(StringRef GPUName) { 2156 return parseAMDGCNName(GPUName) >= GK_GFX9; 2157 } 2158 2159 static bool isAMDGCN(const llvm::Triple &TT) { 2160 return TT.getArch() == llvm::Triple::amdgcn; 2161 } 2162 2163 static bool isGenericZero(const llvm::Triple &TT) { 2164 return TT.getEnvironmentName() == "amdgiz" || 2165 TT.getEnvironmentName() == "amdgizcl"; 2166 } 2167 public: 2168 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2169 : TargetInfo(Triple) , 2170 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2171 hasFP64(false), 2172 hasFMAF(false), 2173 hasLDEXPF(false), 2174 AS(isGenericZero(Triple)){ 2175 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2176 hasFP64 = true; 2177 hasFMAF = true; 2178 hasLDEXPF = true; 2179 } 2180 auto IsGenericZero = isGenericZero(Triple); 2181 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2182 (IsGenericZero ? DataLayoutStringSIGenericIsZero : 2183 DataLayoutStringSIPrivateIsZero) 2184 : DataLayoutStringR600); 2185 assert(DataLayout->getAllocaAddrSpace() == AS.Private); 2186 2187 UseAddrSpaceMapMangling = true; 2188 } 2189 2190 void adjust(LangOptions &Opts) override { 2191 TargetInfo::adjust(Opts); 2192 if (isGenericZero(getTriple())) { 2193 AddrSpaceMap = Opts.OpenCL ? &AMDGPUOpenCLGenericIsZeroMap 2194 : &AMDGPUNonOpenCLGenericIsZeroMap; 2195 } else { 2196 AddrSpaceMap = Opts.OpenCL ? &AMDGPUOpenCLPrivateIsZeroMap 2197 : &AMDGPUNonOpenCLPrivateIsZeroMap; 2198 } 2199 } 2200 2201 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2202 if (GPU <= GK_CAYMAN) 2203 return 32; 2204 2205 if (AddrSpace == AS.Private || AddrSpace == AS.Local) { 2206 return 32; 2207 } 2208 return 64; 2209 } 2210 2211 uint64_t getMaxPointerWidth() const override { 2212 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2213 } 2214 2215 const char * getClobbers() const override { 2216 return ""; 2217 } 2218 2219 ArrayRef<const char *> getGCCRegNames() const override; 2220 2221 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2222 return None; 2223 } 2224 2225 bool validateAsmConstraint(const char *&Name, 2226 TargetInfo::ConstraintInfo &Info) const override { 2227 switch (*Name) { 2228 default: break; 2229 case 'v': // vgpr 2230 case 's': // sgpr 2231 Info.setAllowsRegister(); 2232 return true; 2233 } 2234 return false; 2235 } 2236 2237 bool initFeatureMap(llvm::StringMap<bool> &Features, 2238 DiagnosticsEngine &Diags, StringRef CPU, 2239 const std::vector<std::string> &FeatureVec) const override; 2240 2241 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2242 TargetOptions &TargetOpts) const override { 2243 bool hasFP32Denormals = false; 2244 bool hasFP64Denormals = false; 2245 for (auto &I : TargetOpts.FeaturesAsWritten) { 2246 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2247 hasFP32Denormals = true; 2248 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2249 hasFP64Denormals = true; 2250 } 2251 if (!hasFP32Denormals) 2252 TargetOpts.Features.push_back( 2253 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) && 2254 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2255 // Always do not flush fp64 or fp16 denorms. 2256 if (!hasFP64Denormals && hasFP64) 2257 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2258 } 2259 2260 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2261 return llvm::makeArrayRef(BuiltinInfo, 2262 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2263 } 2264 2265 void getTargetDefines(const LangOptions &Opts, 2266 MacroBuilder &Builder) const override { 2267 if (getTriple().getArch() == llvm::Triple::amdgcn) 2268 Builder.defineMacro("__AMDGCN__"); 2269 else 2270 Builder.defineMacro("__R600__"); 2271 2272 if (hasFMAF) 2273 Builder.defineMacro("__HAS_FMAF__"); 2274 if (hasLDEXPF) 2275 Builder.defineMacro("__HAS_LDEXPF__"); 2276 if (hasFP64) 2277 Builder.defineMacro("__HAS_FP64__"); 2278 } 2279 2280 BuiltinVaListKind getBuiltinVaListKind() const override { 2281 return TargetInfo::CharPtrBuiltinVaList; 2282 } 2283 2284 static GPUKind parseR600Name(StringRef Name) { 2285 return llvm::StringSwitch<GPUKind>(Name) 2286 .Case("r600" , GK_R600) 2287 .Case("rv610", GK_R600) 2288 .Case("rv620", GK_R600) 2289 .Case("rv630", GK_R600) 2290 .Case("rv635", GK_R600) 2291 .Case("rs780", GK_R600) 2292 .Case("rs880", GK_R600) 2293 .Case("rv670", GK_R600_DOUBLE_OPS) 2294 .Case("rv710", GK_R700) 2295 .Case("rv730", GK_R700) 2296 .Case("rv740", GK_R700_DOUBLE_OPS) 2297 .Case("rv770", GK_R700_DOUBLE_OPS) 2298 .Case("palm", GK_EVERGREEN) 2299 .Case("cedar", GK_EVERGREEN) 2300 .Case("sumo", GK_EVERGREEN) 2301 .Case("sumo2", GK_EVERGREEN) 2302 .Case("redwood", GK_EVERGREEN) 2303 .Case("juniper", GK_EVERGREEN) 2304 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2305 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2306 .Case("barts", GK_NORTHERN_ISLANDS) 2307 .Case("turks", GK_NORTHERN_ISLANDS) 2308 .Case("caicos", GK_NORTHERN_ISLANDS) 2309 .Case("cayman", GK_CAYMAN) 2310 .Case("aruba", GK_CAYMAN) 2311 .Default(GK_NONE); 2312 } 2313 2314 static GPUKind parseAMDGCNName(StringRef Name) { 2315 return llvm::StringSwitch<GPUKind>(Name) 2316 .Case("tahiti", GK_GFX6) 2317 .Case("pitcairn", GK_GFX6) 2318 .Case("verde", GK_GFX6) 2319 .Case("oland", GK_GFX6) 2320 .Case("hainan", GK_GFX6) 2321 .Case("bonaire", GK_GFX7) 2322 .Case("kabini", GK_GFX7) 2323 .Case("kaveri", GK_GFX7) 2324 .Case("hawaii", GK_GFX7) 2325 .Case("mullins", GK_GFX7) 2326 .Case("gfx700", GK_GFX7) 2327 .Case("gfx701", GK_GFX7) 2328 .Case("gfx702", GK_GFX7) 2329 .Case("tonga", GK_GFX8) 2330 .Case("iceland", GK_GFX8) 2331 .Case("carrizo", GK_GFX8) 2332 .Case("fiji", GK_GFX8) 2333 .Case("stoney", GK_GFX8) 2334 .Case("polaris10", GK_GFX8) 2335 .Case("polaris11", GK_GFX8) 2336 .Case("gfx800", GK_GFX8) 2337 .Case("gfx801", GK_GFX8) 2338 .Case("gfx802", GK_GFX8) 2339 .Case("gfx803", GK_GFX8) 2340 .Case("gfx804", GK_GFX8) 2341 .Case("gfx810", GK_GFX8) 2342 .Case("gfx900", GK_GFX9) 2343 .Case("gfx901", GK_GFX9) 2344 .Default(GK_NONE); 2345 } 2346 2347 bool setCPU(const std::string &Name) override { 2348 if (getTriple().getArch() == llvm::Triple::amdgcn) 2349 GPU = parseAMDGCNName(Name); 2350 else 2351 GPU = parseR600Name(Name); 2352 2353 return GPU != GK_NONE; 2354 } 2355 2356 void setSupportedOpenCLOpts() override { 2357 auto &Opts = getSupportedOpenCLOpts(); 2358 Opts.support("cl_clang_storage_class_specifiers"); 2359 Opts.support("cl_khr_icd"); 2360 2361 if (hasFP64) 2362 Opts.support("cl_khr_fp64"); 2363 if (GPU >= GK_EVERGREEN) { 2364 Opts.support("cl_khr_byte_addressable_store"); 2365 Opts.support("cl_khr_global_int32_base_atomics"); 2366 Opts.support("cl_khr_global_int32_extended_atomics"); 2367 Opts.support("cl_khr_local_int32_base_atomics"); 2368 Opts.support("cl_khr_local_int32_extended_atomics"); 2369 } 2370 if (GPU >= GK_GFX6) { 2371 Opts.support("cl_khr_fp16"); 2372 Opts.support("cl_khr_int64_base_atomics"); 2373 Opts.support("cl_khr_int64_extended_atomics"); 2374 Opts.support("cl_khr_mipmap_image"); 2375 Opts.support("cl_khr_subgroups"); 2376 Opts.support("cl_khr_3d_image_writes"); 2377 Opts.support("cl_amd_media_ops"); 2378 Opts.support("cl_amd_media_ops2"); 2379 } 2380 } 2381 2382 LangAS::ID getOpenCLImageAddrSpace() const override { 2383 return LangAS::opencl_constant; 2384 } 2385 2386 /// \returns Target specific vtbl ptr address space. 2387 unsigned getVtblPtrAddressSpace() const override { 2388 // \todo: We currently have address spaces defined in AMDGPU Backend. It 2389 // would be nice if we could use it here instead of using bare numbers (same 2390 // applies to getDWARFAddressSpace). 2391 return 2; // constant. 2392 } 2393 2394 /// \returns If a target requires an address within a target specific address 2395 /// space \p AddressSpace to be converted in order to be used, then return the 2396 /// corresponding target specific DWARF address space. 2397 /// 2398 /// \returns Otherwise return None and no conversion will be emitted in the 2399 /// DWARF. 2400 Optional<unsigned> getDWARFAddressSpace( 2401 unsigned AddressSpace) const override { 2402 const unsigned DWARF_Private = 1; 2403 const unsigned DWARF_Local = 2; 2404 if (AddressSpace == AS.Private) { 2405 return DWARF_Private; 2406 } else if (AddressSpace == AS.Local) { 2407 return DWARF_Local; 2408 } else { 2409 return None; 2410 } 2411 } 2412 2413 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2414 switch (CC) { 2415 default: 2416 return CCCR_Warning; 2417 case CC_C: 2418 case CC_OpenCLKernel: 2419 return CCCR_OK; 2420 } 2421 } 2422 2423 // In amdgcn target the null pointer in global, constant, and generic 2424 // address space has value 0 but in private and local address space has 2425 // value ~0. 2426 uint64_t getNullPointerValue(unsigned AS) const override { 2427 return AS == LangAS::opencl_local ? ~0 : 0; 2428 } 2429 }; 2430 2431 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2432 #define BUILTIN(ID, TYPE, ATTRS) \ 2433 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2434 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2435 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2436 #include "clang/Basic/BuiltinsAMDGPU.def" 2437 }; 2438 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2439 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2440 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2441 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2442 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2443 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2444 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2445 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2446 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2447 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2448 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2449 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2450 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2451 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2452 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2453 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2454 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2455 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2456 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2457 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2458 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2459 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2460 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2461 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2462 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2463 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2464 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2465 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2466 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2467 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2468 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2469 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2470 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2471 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2472 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2473 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2474 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2475 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2476 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2477 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2478 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2479 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2480 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2481 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2482 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2483 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2484 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2485 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2486 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2487 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2488 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2489 }; 2490 2491 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2492 return llvm::makeArrayRef(GCCRegNames); 2493 } 2494 2495 bool AMDGPUTargetInfo::initFeatureMap( 2496 llvm::StringMap<bool> &Features, 2497 DiagnosticsEngine &Diags, StringRef CPU, 2498 const std::vector<std::string> &FeatureVec) const { 2499 2500 // XXX - What does the member GPU mean if device name string passed here? 2501 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2502 if (CPU.empty()) 2503 CPU = "tahiti"; 2504 2505 switch (parseAMDGCNName(CPU)) { 2506 case GK_GFX6: 2507 case GK_GFX7: 2508 break; 2509 2510 case GK_GFX9: 2511 Features["gfx9-insts"] = true; 2512 LLVM_FALLTHROUGH; 2513 case GK_GFX8: 2514 Features["s-memrealtime"] = true; 2515 Features["16-bit-insts"] = true; 2516 Features["dpp"] = true; 2517 break; 2518 2519 case GK_NONE: 2520 return false; 2521 default: 2522 llvm_unreachable("unhandled subtarget"); 2523 } 2524 } else { 2525 if (CPU.empty()) 2526 CPU = "r600"; 2527 2528 switch (parseR600Name(CPU)) { 2529 case GK_R600: 2530 case GK_R700: 2531 case GK_EVERGREEN: 2532 case GK_NORTHERN_ISLANDS: 2533 break; 2534 case GK_R600_DOUBLE_OPS: 2535 case GK_R700_DOUBLE_OPS: 2536 case GK_EVERGREEN_DOUBLE_OPS: 2537 case GK_CAYMAN: 2538 Features["fp64"] = true; 2539 break; 2540 case GK_NONE: 2541 return false; 2542 default: 2543 llvm_unreachable("unhandled subtarget"); 2544 } 2545 } 2546 2547 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2548 } 2549 2550 const Builtin::Info BuiltinInfoX86[] = { 2551 #define BUILTIN(ID, TYPE, ATTRS) \ 2552 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2553 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2554 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2555 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2556 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2557 #include "clang/Basic/BuiltinsX86.def" 2558 2559 #define BUILTIN(ID, TYPE, ATTRS) \ 2560 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2561 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2562 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2563 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2564 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2565 #include "clang/Basic/BuiltinsX86_64.def" 2566 }; 2567 2568 2569 static const char* const GCCRegNames[] = { 2570 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2571 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2572 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2573 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2574 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2575 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2576 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2577 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2578 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2579 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2580 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2581 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2582 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2583 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2584 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2585 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2586 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2587 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2588 }; 2589 2590 const TargetInfo::AddlRegName AddlRegNames[] = { 2591 { { "al", "ah", "eax", "rax" }, 0 }, 2592 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2593 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2594 { { "dl", "dh", "edx", "rdx" }, 1 }, 2595 { { "esi", "rsi" }, 4 }, 2596 { { "edi", "rdi" }, 5 }, 2597 { { "esp", "rsp" }, 7 }, 2598 { { "ebp", "rbp" }, 6 }, 2599 { { "r8d", "r8w", "r8b" }, 38 }, 2600 { { "r9d", "r9w", "r9b" }, 39 }, 2601 { { "r10d", "r10w", "r10b" }, 40 }, 2602 { { "r11d", "r11w", "r11b" }, 41 }, 2603 { { "r12d", "r12w", "r12b" }, 42 }, 2604 { { "r13d", "r13w", "r13b" }, 43 }, 2605 { { "r14d", "r14w", "r14b" }, 44 }, 2606 { { "r15d", "r15w", "r15b" }, 45 }, 2607 }; 2608 2609 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2610 // most of the implementation can be shared. 2611 class X86TargetInfo : public TargetInfo { 2612 enum X86SSEEnum { 2613 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2614 } SSELevel = NoSSE; 2615 enum MMX3DNowEnum { 2616 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2617 } MMX3DNowLevel = NoMMX3DNow; 2618 enum XOPEnum { 2619 NoXOP, 2620 SSE4A, 2621 FMA4, 2622 XOP 2623 } XOPLevel = NoXOP; 2624 2625 bool HasAES = false; 2626 bool HasPCLMUL = false; 2627 bool HasLZCNT = false; 2628 bool HasRDRND = false; 2629 bool HasFSGSBASE = false; 2630 bool HasBMI = false; 2631 bool HasBMI2 = false; 2632 bool HasPOPCNT = false; 2633 bool HasRTM = false; 2634 bool HasPRFCHW = false; 2635 bool HasRDSEED = false; 2636 bool HasADX = false; 2637 bool HasTBM = false; 2638 bool HasLWP = false; 2639 bool HasFMA = false; 2640 bool HasF16C = false; 2641 bool HasAVX512CD = false; 2642 bool HasAVX512VPOPCNTDQ = false; 2643 bool HasAVX512ER = false; 2644 bool HasAVX512PF = false; 2645 bool HasAVX512DQ = false; 2646 bool HasAVX512BW = false; 2647 bool HasAVX512VL = false; 2648 bool HasAVX512VBMI = false; 2649 bool HasAVX512IFMA = false; 2650 bool HasSHA = false; 2651 bool HasMPX = false; 2652 bool HasSGX = false; 2653 bool HasCX16 = false; 2654 bool HasFXSR = false; 2655 bool HasXSAVE = false; 2656 bool HasXSAVEOPT = false; 2657 bool HasXSAVEC = false; 2658 bool HasXSAVES = false; 2659 bool HasMWAITX = false; 2660 bool HasCLZERO = false; 2661 bool HasPKU = false; 2662 bool HasCLFLUSHOPT = false; 2663 bool HasCLWB = false; 2664 bool HasMOVBE = false; 2665 bool HasPREFETCHWT1 = false; 2666 2667 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2668 /// 2669 /// Each enumeration represents a particular CPU supported by Clang. These 2670 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2671 enum CPUKind { 2672 CK_Generic, 2673 2674 /// \name i386 2675 /// i386-generation processors. 2676 //@{ 2677 CK_i386, 2678 //@} 2679 2680 /// \name i486 2681 /// i486-generation processors. 2682 //@{ 2683 CK_i486, 2684 CK_WinChipC6, 2685 CK_WinChip2, 2686 CK_C3, 2687 //@} 2688 2689 /// \name i586 2690 /// i586-generation processors, P5 microarchitecture based. 2691 //@{ 2692 CK_i586, 2693 CK_Pentium, 2694 CK_PentiumMMX, 2695 //@} 2696 2697 /// \name i686 2698 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2699 //@{ 2700 CK_i686, 2701 CK_PentiumPro, 2702 CK_Pentium2, 2703 CK_Pentium3, 2704 CK_Pentium3M, 2705 CK_PentiumM, 2706 CK_C3_2, 2707 2708 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2709 /// Clang however has some logic to suport this. 2710 // FIXME: Warn, deprecate, and potentially remove this. 2711 CK_Yonah, 2712 //@} 2713 2714 /// \name Netburst 2715 /// Netburst microarchitecture based processors. 2716 //@{ 2717 CK_Pentium4, 2718 CK_Pentium4M, 2719 CK_Prescott, 2720 CK_Nocona, 2721 //@} 2722 2723 /// \name Core 2724 /// Core microarchitecture based processors. 2725 //@{ 2726 CK_Core2, 2727 2728 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2729 /// codename which GCC no longer accepts as an option to -march, but Clang 2730 /// has some logic for recognizing it. 2731 // FIXME: Warn, deprecate, and potentially remove this. 2732 CK_Penryn, 2733 //@} 2734 2735 /// \name Atom 2736 /// Atom processors 2737 //@{ 2738 CK_Bonnell, 2739 CK_Silvermont, 2740 //@} 2741 2742 /// \name Nehalem 2743 /// Nehalem microarchitecture based processors. 2744 CK_Nehalem, 2745 2746 /// \name Westmere 2747 /// Westmere microarchitecture based processors. 2748 CK_Westmere, 2749 2750 /// \name Sandy Bridge 2751 /// Sandy Bridge microarchitecture based processors. 2752 CK_SandyBridge, 2753 2754 /// \name Ivy Bridge 2755 /// Ivy Bridge microarchitecture based processors. 2756 CK_IvyBridge, 2757 2758 /// \name Haswell 2759 /// Haswell microarchitecture based processors. 2760 CK_Haswell, 2761 2762 /// \name Broadwell 2763 /// Broadwell microarchitecture based processors. 2764 CK_Broadwell, 2765 2766 /// \name Skylake Client 2767 /// Skylake client microarchitecture based processors. 2768 CK_SkylakeClient, 2769 2770 /// \name Skylake Server 2771 /// Skylake server microarchitecture based processors. 2772 CK_SkylakeServer, 2773 2774 /// \name Cannonlake Client 2775 /// Cannonlake client microarchitecture based processors. 2776 CK_Cannonlake, 2777 2778 /// \name Knights Landing 2779 /// Knights Landing processor. 2780 CK_KNL, 2781 2782 /// \name Lakemont 2783 /// Lakemont microarchitecture based processors. 2784 CK_Lakemont, 2785 2786 /// \name K6 2787 /// K6 architecture processors. 2788 //@{ 2789 CK_K6, 2790 CK_K6_2, 2791 CK_K6_3, 2792 //@} 2793 2794 /// \name K7 2795 /// K7 architecture processors. 2796 //@{ 2797 CK_Athlon, 2798 CK_AthlonThunderbird, 2799 CK_Athlon4, 2800 CK_AthlonXP, 2801 CK_AthlonMP, 2802 //@} 2803 2804 /// \name K8 2805 /// K8 architecture processors. 2806 //@{ 2807 CK_Athlon64, 2808 CK_Athlon64SSE3, 2809 CK_AthlonFX, 2810 CK_K8, 2811 CK_K8SSE3, 2812 CK_Opteron, 2813 CK_OpteronSSE3, 2814 CK_AMDFAM10, 2815 //@} 2816 2817 /// \name Bobcat 2818 /// Bobcat architecture processors. 2819 //@{ 2820 CK_BTVER1, 2821 CK_BTVER2, 2822 //@} 2823 2824 /// \name Bulldozer 2825 /// Bulldozer architecture processors. 2826 //@{ 2827 CK_BDVER1, 2828 CK_BDVER2, 2829 CK_BDVER3, 2830 CK_BDVER4, 2831 //@} 2832 2833 /// \name zen 2834 /// Zen architecture processors. 2835 //@{ 2836 CK_ZNVER1, 2837 //@} 2838 2839 /// This specification is deprecated and will be removed in the future. 2840 /// Users should prefer \see CK_K8. 2841 // FIXME: Warn on this when the CPU is set to it. 2842 //@{ 2843 CK_x86_64, 2844 //@} 2845 2846 /// \name Geode 2847 /// Geode processors. 2848 //@{ 2849 CK_Geode 2850 //@} 2851 } CPU = CK_Generic; 2852 2853 CPUKind getCPUKind(StringRef CPU) const { 2854 return llvm::StringSwitch<CPUKind>(CPU) 2855 .Case("i386", CK_i386) 2856 .Case("i486", CK_i486) 2857 .Case("winchip-c6", CK_WinChipC6) 2858 .Case("winchip2", CK_WinChip2) 2859 .Case("c3", CK_C3) 2860 .Case("i586", CK_i586) 2861 .Case("pentium", CK_Pentium) 2862 .Case("pentium-mmx", CK_PentiumMMX) 2863 .Case("i686", CK_i686) 2864 .Case("pentiumpro", CK_PentiumPro) 2865 .Case("pentium2", CK_Pentium2) 2866 .Case("pentium3", CK_Pentium3) 2867 .Case("pentium3m", CK_Pentium3M) 2868 .Case("pentium-m", CK_PentiumM) 2869 .Case("c3-2", CK_C3_2) 2870 .Case("yonah", CK_Yonah) 2871 .Case("pentium4", CK_Pentium4) 2872 .Case("pentium4m", CK_Pentium4M) 2873 .Case("prescott", CK_Prescott) 2874 .Case("nocona", CK_Nocona) 2875 .Case("core2", CK_Core2) 2876 .Case("penryn", CK_Penryn) 2877 .Case("bonnell", CK_Bonnell) 2878 .Case("atom", CK_Bonnell) // Legacy name. 2879 .Case("silvermont", CK_Silvermont) 2880 .Case("slm", CK_Silvermont) // Legacy name. 2881 .Case("nehalem", CK_Nehalem) 2882 .Case("corei7", CK_Nehalem) // Legacy name. 2883 .Case("westmere", CK_Westmere) 2884 .Case("sandybridge", CK_SandyBridge) 2885 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2886 .Case("ivybridge", CK_IvyBridge) 2887 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2888 .Case("haswell", CK_Haswell) 2889 .Case("core-avx2", CK_Haswell) // Legacy name. 2890 .Case("broadwell", CK_Broadwell) 2891 .Case("skylake", CK_SkylakeClient) 2892 .Case("skylake-avx512", CK_SkylakeServer) 2893 .Case("skx", CK_SkylakeServer) // Legacy name. 2894 .Case("cannonlake", CK_Cannonlake) 2895 .Case("knl", CK_KNL) 2896 .Case("lakemont", CK_Lakemont) 2897 .Case("k6", CK_K6) 2898 .Case("k6-2", CK_K6_2) 2899 .Case("k6-3", CK_K6_3) 2900 .Case("athlon", CK_Athlon) 2901 .Case("athlon-tbird", CK_AthlonThunderbird) 2902 .Case("athlon-4", CK_Athlon4) 2903 .Case("athlon-xp", CK_AthlonXP) 2904 .Case("athlon-mp", CK_AthlonMP) 2905 .Case("athlon64", CK_Athlon64) 2906 .Case("athlon64-sse3", CK_Athlon64SSE3) 2907 .Case("athlon-fx", CK_AthlonFX) 2908 .Case("k8", CK_K8) 2909 .Case("k8-sse3", CK_K8SSE3) 2910 .Case("opteron", CK_Opteron) 2911 .Case("opteron-sse3", CK_OpteronSSE3) 2912 .Case("barcelona", CK_AMDFAM10) 2913 .Case("amdfam10", CK_AMDFAM10) 2914 .Case("btver1", CK_BTVER1) 2915 .Case("btver2", CK_BTVER2) 2916 .Case("bdver1", CK_BDVER1) 2917 .Case("bdver2", CK_BDVER2) 2918 .Case("bdver3", CK_BDVER3) 2919 .Case("bdver4", CK_BDVER4) 2920 .Case("znver1", CK_ZNVER1) 2921 .Case("x86-64", CK_x86_64) 2922 .Case("geode", CK_Geode) 2923 .Default(CK_Generic); 2924 } 2925 2926 enum FPMathKind { 2927 FP_Default, 2928 FP_SSE, 2929 FP_387 2930 } FPMath = FP_Default; 2931 2932 public: 2933 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2934 : TargetInfo(Triple) { 2935 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2936 } 2937 unsigned getFloatEvalMethod() const override { 2938 // X87 evaluates with 80 bits "long double" precision. 2939 return SSELevel == NoSSE ? 2 : 0; 2940 } 2941 ArrayRef<const char *> getGCCRegNames() const override { 2942 return llvm::makeArrayRef(GCCRegNames); 2943 } 2944 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2945 return None; 2946 } 2947 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2948 return llvm::makeArrayRef(AddlRegNames); 2949 } 2950 bool validateCpuSupports(StringRef Name) const override; 2951 bool validateAsmConstraint(const char *&Name, 2952 TargetInfo::ConstraintInfo &info) const override; 2953 2954 bool validateGlobalRegisterVariable(StringRef RegName, 2955 unsigned RegSize, 2956 bool &HasSizeMismatch) const override { 2957 // esp and ebp are the only 32-bit registers the x86 backend can currently 2958 // handle. 2959 if (RegName.equals("esp") || RegName.equals("ebp")) { 2960 // Check that the register size is 32-bit. 2961 HasSizeMismatch = RegSize != 32; 2962 return true; 2963 } 2964 2965 return false; 2966 } 2967 2968 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2969 2970 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2971 2972 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2973 2974 std::string convertConstraint(const char *&Constraint) const override; 2975 const char *getClobbers() const override { 2976 return "~{dirflag},~{fpsr},~{flags}"; 2977 } 2978 2979 StringRef getConstraintRegister(const StringRef &Constraint, 2980 const StringRef &Expression) const override { 2981 StringRef::iterator I, E; 2982 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 2983 if (isalpha(*I)) 2984 break; 2985 } 2986 if (I == E) 2987 return ""; 2988 switch (*I) { 2989 // For the register constraints, return the matching register name 2990 case 'a': 2991 return "ax"; 2992 case 'b': 2993 return "bx"; 2994 case 'c': 2995 return "cx"; 2996 case 'd': 2997 return "dx"; 2998 case 'S': 2999 return "si"; 3000 case 'D': 3001 return "di"; 3002 // In case the constraint is 'r' we need to return Expression 3003 case 'r': 3004 return Expression; 3005 default: 3006 // Default value if there is no constraint for the register 3007 return ""; 3008 } 3009 return ""; 3010 } 3011 3012 void getTargetDefines(const LangOptions &Opts, 3013 MacroBuilder &Builder) const override; 3014 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 3015 bool Enabled); 3016 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 3017 bool Enabled); 3018 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3019 bool Enabled); 3020 void setFeatureEnabled(llvm::StringMap<bool> &Features, 3021 StringRef Name, bool Enabled) const override { 3022 setFeatureEnabledImpl(Features, Name, Enabled); 3023 } 3024 // This exists purely to cut down on the number of virtual calls in 3025 // initFeatureMap which calls this repeatedly. 3026 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3027 StringRef Name, bool Enabled); 3028 bool 3029 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 3030 StringRef CPU, 3031 const std::vector<std::string> &FeaturesVec) const override; 3032 bool hasFeature(StringRef Feature) const override; 3033 bool handleTargetFeatures(std::vector<std::string> &Features, 3034 DiagnosticsEngine &Diags) override; 3035 StringRef getABI() const override { 3036 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 3037 return "avx512"; 3038 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 3039 return "avx"; 3040 if (getTriple().getArch() == llvm::Triple::x86 && 3041 MMX3DNowLevel == NoMMX3DNow) 3042 return "no-mmx"; 3043 return ""; 3044 } 3045 bool setCPU(const std::string &Name) override { 3046 CPU = getCPUKind(Name); 3047 3048 // Perform any per-CPU checks necessary to determine if this CPU is 3049 // acceptable. 3050 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 3051 // invalid without explaining *why*. 3052 switch (CPU) { 3053 case CK_Generic: 3054 // No processor selected! 3055 return false; 3056 3057 case CK_i386: 3058 case CK_i486: 3059 case CK_WinChipC6: 3060 case CK_WinChip2: 3061 case CK_C3: 3062 case CK_i586: 3063 case CK_Pentium: 3064 case CK_PentiumMMX: 3065 case CK_i686: 3066 case CK_PentiumPro: 3067 case CK_Pentium2: 3068 case CK_Pentium3: 3069 case CK_Pentium3M: 3070 case CK_PentiumM: 3071 case CK_Yonah: 3072 case CK_C3_2: 3073 case CK_Pentium4: 3074 case CK_Pentium4M: 3075 case CK_Lakemont: 3076 case CK_Prescott: 3077 case CK_K6: 3078 case CK_K6_2: 3079 case CK_K6_3: 3080 case CK_Athlon: 3081 case CK_AthlonThunderbird: 3082 case CK_Athlon4: 3083 case CK_AthlonXP: 3084 case CK_AthlonMP: 3085 case CK_Geode: 3086 // Only accept certain architectures when compiling in 32-bit mode. 3087 if (getTriple().getArch() != llvm::Triple::x86) 3088 return false; 3089 3090 // Fallthrough 3091 case CK_Nocona: 3092 case CK_Core2: 3093 case CK_Penryn: 3094 case CK_Bonnell: 3095 case CK_Silvermont: 3096 case CK_Nehalem: 3097 case CK_Westmere: 3098 case CK_SandyBridge: 3099 case CK_IvyBridge: 3100 case CK_Haswell: 3101 case CK_Broadwell: 3102 case CK_SkylakeClient: 3103 case CK_SkylakeServer: 3104 case CK_Cannonlake: 3105 case CK_KNL: 3106 case CK_Athlon64: 3107 case CK_Athlon64SSE3: 3108 case CK_AthlonFX: 3109 case CK_K8: 3110 case CK_K8SSE3: 3111 case CK_Opteron: 3112 case CK_OpteronSSE3: 3113 case CK_AMDFAM10: 3114 case CK_BTVER1: 3115 case CK_BTVER2: 3116 case CK_BDVER1: 3117 case CK_BDVER2: 3118 case CK_BDVER3: 3119 case CK_BDVER4: 3120 case CK_ZNVER1: 3121 case CK_x86_64: 3122 return true; 3123 } 3124 llvm_unreachable("Unhandled CPU kind"); 3125 } 3126 3127 bool setFPMath(StringRef Name) override; 3128 3129 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3130 // Most of the non-ARM calling conventions are i386 conventions. 3131 switch (CC) { 3132 case CC_X86ThisCall: 3133 case CC_X86FastCall: 3134 case CC_X86StdCall: 3135 case CC_X86VectorCall: 3136 case CC_X86RegCall: 3137 case CC_C: 3138 case CC_Swift: 3139 case CC_X86Pascal: 3140 case CC_IntelOclBicc: 3141 case CC_OpenCLKernel: 3142 return CCCR_OK; 3143 default: 3144 return CCCR_Warning; 3145 } 3146 } 3147 3148 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3149 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 3150 } 3151 3152 bool hasSjLjLowering() const override { 3153 return true; 3154 } 3155 3156 void setSupportedOpenCLOpts() override { 3157 getSupportedOpenCLOpts().supportAll(); 3158 } 3159 }; 3160 3161 bool X86TargetInfo::setFPMath(StringRef Name) { 3162 if (Name == "387") { 3163 FPMath = FP_387; 3164 return true; 3165 } 3166 if (Name == "sse") { 3167 FPMath = FP_SSE; 3168 return true; 3169 } 3170 return false; 3171 } 3172 3173 bool X86TargetInfo::initFeatureMap( 3174 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3175 const std::vector<std::string> &FeaturesVec) const { 3176 // FIXME: This *really* should not be here. 3177 // X86_64 always has SSE2. 3178 if (getTriple().getArch() == llvm::Triple::x86_64) 3179 setFeatureEnabledImpl(Features, "sse2", true); 3180 3181 const CPUKind Kind = getCPUKind(CPU); 3182 3183 // Enable X87 for all X86 processors but Lakemont. 3184 if (Kind != CK_Lakemont) 3185 setFeatureEnabledImpl(Features, "x87", true); 3186 3187 switch (Kind) { 3188 case CK_Generic: 3189 case CK_i386: 3190 case CK_i486: 3191 case CK_i586: 3192 case CK_Pentium: 3193 case CK_i686: 3194 case CK_PentiumPro: 3195 case CK_Lakemont: 3196 break; 3197 case CK_PentiumMMX: 3198 case CK_Pentium2: 3199 case CK_K6: 3200 case CK_WinChipC6: 3201 setFeatureEnabledImpl(Features, "mmx", true); 3202 break; 3203 case CK_Pentium3: 3204 case CK_Pentium3M: 3205 case CK_C3_2: 3206 setFeatureEnabledImpl(Features, "sse", true); 3207 setFeatureEnabledImpl(Features, "fxsr", true); 3208 break; 3209 case CK_PentiumM: 3210 case CK_Pentium4: 3211 case CK_Pentium4M: 3212 case CK_x86_64: 3213 setFeatureEnabledImpl(Features, "sse2", true); 3214 setFeatureEnabledImpl(Features, "fxsr", true); 3215 break; 3216 case CK_Yonah: 3217 case CK_Prescott: 3218 case CK_Nocona: 3219 setFeatureEnabledImpl(Features, "sse3", true); 3220 setFeatureEnabledImpl(Features, "fxsr", true); 3221 setFeatureEnabledImpl(Features, "cx16", true); 3222 break; 3223 case CK_Core2: 3224 case CK_Bonnell: 3225 setFeatureEnabledImpl(Features, "ssse3", true); 3226 setFeatureEnabledImpl(Features, "fxsr", true); 3227 setFeatureEnabledImpl(Features, "cx16", true); 3228 break; 3229 case CK_Penryn: 3230 setFeatureEnabledImpl(Features, "sse4.1", true); 3231 setFeatureEnabledImpl(Features, "fxsr", true); 3232 setFeatureEnabledImpl(Features, "cx16", true); 3233 break; 3234 case CK_Cannonlake: 3235 setFeatureEnabledImpl(Features, "avx512ifma", true); 3236 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3237 setFeatureEnabledImpl(Features, "sha", true); 3238 LLVM_FALLTHROUGH; 3239 case CK_SkylakeServer: 3240 setFeatureEnabledImpl(Features, "avx512f", true); 3241 setFeatureEnabledImpl(Features, "avx512cd", true); 3242 setFeatureEnabledImpl(Features, "avx512dq", true); 3243 setFeatureEnabledImpl(Features, "avx512bw", true); 3244 setFeatureEnabledImpl(Features, "avx512vl", true); 3245 setFeatureEnabledImpl(Features, "pku", true); 3246 setFeatureEnabledImpl(Features, "clwb", true); 3247 LLVM_FALLTHROUGH; 3248 case CK_SkylakeClient: 3249 setFeatureEnabledImpl(Features, "xsavec", true); 3250 setFeatureEnabledImpl(Features, "xsaves", true); 3251 setFeatureEnabledImpl(Features, "mpx", true); 3252 setFeatureEnabledImpl(Features, "sgx", true); 3253 setFeatureEnabledImpl(Features, "clflushopt", true); 3254 setFeatureEnabledImpl(Features, "rtm", true); 3255 LLVM_FALLTHROUGH; 3256 case CK_Broadwell: 3257 setFeatureEnabledImpl(Features, "rdseed", true); 3258 setFeatureEnabledImpl(Features, "adx", true); 3259 LLVM_FALLTHROUGH; 3260 case CK_Haswell: 3261 setFeatureEnabledImpl(Features, "avx2", true); 3262 setFeatureEnabledImpl(Features, "lzcnt", true); 3263 setFeatureEnabledImpl(Features, "bmi", true); 3264 setFeatureEnabledImpl(Features, "bmi2", true); 3265 setFeatureEnabledImpl(Features, "fma", true); 3266 setFeatureEnabledImpl(Features, "movbe", true); 3267 LLVM_FALLTHROUGH; 3268 case CK_IvyBridge: 3269 setFeatureEnabledImpl(Features, "rdrnd", true); 3270 setFeatureEnabledImpl(Features, "f16c", true); 3271 setFeatureEnabledImpl(Features, "fsgsbase", true); 3272 LLVM_FALLTHROUGH; 3273 case CK_SandyBridge: 3274 setFeatureEnabledImpl(Features, "avx", true); 3275 setFeatureEnabledImpl(Features, "xsave", true); 3276 setFeatureEnabledImpl(Features, "xsaveopt", true); 3277 LLVM_FALLTHROUGH; 3278 case CK_Westmere: 3279 case CK_Silvermont: 3280 setFeatureEnabledImpl(Features, "aes", true); 3281 setFeatureEnabledImpl(Features, "pclmul", true); 3282 LLVM_FALLTHROUGH; 3283 case CK_Nehalem: 3284 setFeatureEnabledImpl(Features, "sse4.2", true); 3285 setFeatureEnabledImpl(Features, "fxsr", true); 3286 setFeatureEnabledImpl(Features, "cx16", true); 3287 break; 3288 case CK_KNL: 3289 setFeatureEnabledImpl(Features, "avx512f", true); 3290 setFeatureEnabledImpl(Features, "avx512cd", true); 3291 setFeatureEnabledImpl(Features, "avx512er", true); 3292 setFeatureEnabledImpl(Features, "avx512pf", true); 3293 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3294 setFeatureEnabledImpl(Features, "fxsr", true); 3295 setFeatureEnabledImpl(Features, "rdseed", true); 3296 setFeatureEnabledImpl(Features, "adx", true); 3297 setFeatureEnabledImpl(Features, "lzcnt", true); 3298 setFeatureEnabledImpl(Features, "bmi", true); 3299 setFeatureEnabledImpl(Features, "bmi2", true); 3300 setFeatureEnabledImpl(Features, "rtm", true); 3301 setFeatureEnabledImpl(Features, "fma", true); 3302 setFeatureEnabledImpl(Features, "rdrnd", true); 3303 setFeatureEnabledImpl(Features, "f16c", true); 3304 setFeatureEnabledImpl(Features, "fsgsbase", true); 3305 setFeatureEnabledImpl(Features, "aes", true); 3306 setFeatureEnabledImpl(Features, "pclmul", true); 3307 setFeatureEnabledImpl(Features, "cx16", true); 3308 setFeatureEnabledImpl(Features, "xsaveopt", true); 3309 setFeatureEnabledImpl(Features, "xsave", true); 3310 setFeatureEnabledImpl(Features, "movbe", true); 3311 break; 3312 case CK_K6_2: 3313 case CK_K6_3: 3314 case CK_WinChip2: 3315 case CK_C3: 3316 setFeatureEnabledImpl(Features, "3dnow", true); 3317 break; 3318 case CK_Athlon: 3319 case CK_AthlonThunderbird: 3320 case CK_Geode: 3321 setFeatureEnabledImpl(Features, "3dnowa", true); 3322 break; 3323 case CK_Athlon4: 3324 case CK_AthlonXP: 3325 case CK_AthlonMP: 3326 setFeatureEnabledImpl(Features, "sse", true); 3327 setFeatureEnabledImpl(Features, "3dnowa", true); 3328 setFeatureEnabledImpl(Features, "fxsr", true); 3329 break; 3330 case CK_K8: 3331 case CK_Opteron: 3332 case CK_Athlon64: 3333 case CK_AthlonFX: 3334 setFeatureEnabledImpl(Features, "sse2", true); 3335 setFeatureEnabledImpl(Features, "3dnowa", true); 3336 setFeatureEnabledImpl(Features, "fxsr", true); 3337 break; 3338 case CK_AMDFAM10: 3339 setFeatureEnabledImpl(Features, "sse4a", true); 3340 setFeatureEnabledImpl(Features, "lzcnt", true); 3341 setFeatureEnabledImpl(Features, "popcnt", true); 3342 LLVM_FALLTHROUGH; 3343 case CK_K8SSE3: 3344 case CK_OpteronSSE3: 3345 case CK_Athlon64SSE3: 3346 setFeatureEnabledImpl(Features, "sse3", true); 3347 setFeatureEnabledImpl(Features, "3dnowa", true); 3348 setFeatureEnabledImpl(Features, "fxsr", true); 3349 break; 3350 case CK_BTVER2: 3351 setFeatureEnabledImpl(Features, "avx", true); 3352 setFeatureEnabledImpl(Features, "aes", true); 3353 setFeatureEnabledImpl(Features, "pclmul", true); 3354 setFeatureEnabledImpl(Features, "bmi", true); 3355 setFeatureEnabledImpl(Features, "f16c", true); 3356 setFeatureEnabledImpl(Features, "xsaveopt", true); 3357 LLVM_FALLTHROUGH; 3358 case CK_BTVER1: 3359 setFeatureEnabledImpl(Features, "ssse3", true); 3360 setFeatureEnabledImpl(Features, "sse4a", true); 3361 setFeatureEnabledImpl(Features, "lzcnt", true); 3362 setFeatureEnabledImpl(Features, "popcnt", true); 3363 setFeatureEnabledImpl(Features, "prfchw", true); 3364 setFeatureEnabledImpl(Features, "cx16", true); 3365 setFeatureEnabledImpl(Features, "fxsr", true); 3366 break; 3367 case CK_ZNVER1: 3368 setFeatureEnabledImpl(Features, "adx", true); 3369 setFeatureEnabledImpl(Features, "aes", true); 3370 setFeatureEnabledImpl(Features, "avx2", true); 3371 setFeatureEnabledImpl(Features, "bmi", true); 3372 setFeatureEnabledImpl(Features, "bmi2", true); 3373 setFeatureEnabledImpl(Features, "clflushopt", true); 3374 setFeatureEnabledImpl(Features, "clzero", true); 3375 setFeatureEnabledImpl(Features, "cx16", true); 3376 setFeatureEnabledImpl(Features, "f16c", true); 3377 setFeatureEnabledImpl(Features, "fma", true); 3378 setFeatureEnabledImpl(Features, "fsgsbase", true); 3379 setFeatureEnabledImpl(Features, "fxsr", true); 3380 setFeatureEnabledImpl(Features, "lzcnt", true); 3381 setFeatureEnabledImpl(Features, "mwaitx", true); 3382 setFeatureEnabledImpl(Features, "movbe", true); 3383 setFeatureEnabledImpl(Features, "pclmul", true); 3384 setFeatureEnabledImpl(Features, "popcnt", true); 3385 setFeatureEnabledImpl(Features, "prfchw", true); 3386 setFeatureEnabledImpl(Features, "rdrnd", true); 3387 setFeatureEnabledImpl(Features, "rdseed", true); 3388 setFeatureEnabledImpl(Features, "sha", true); 3389 setFeatureEnabledImpl(Features, "sse4a", true); 3390 setFeatureEnabledImpl(Features, "xsave", true); 3391 setFeatureEnabledImpl(Features, "xsavec", true); 3392 setFeatureEnabledImpl(Features, "xsaveopt", true); 3393 setFeatureEnabledImpl(Features, "xsaves", true); 3394 break; 3395 case CK_BDVER4: 3396 setFeatureEnabledImpl(Features, "avx2", true); 3397 setFeatureEnabledImpl(Features, "bmi2", true); 3398 setFeatureEnabledImpl(Features, "mwaitx", true); 3399 LLVM_FALLTHROUGH; 3400 case CK_BDVER3: 3401 setFeatureEnabledImpl(Features, "fsgsbase", true); 3402 setFeatureEnabledImpl(Features, "xsaveopt", true); 3403 LLVM_FALLTHROUGH; 3404 case CK_BDVER2: 3405 setFeatureEnabledImpl(Features, "bmi", true); 3406 setFeatureEnabledImpl(Features, "fma", true); 3407 setFeatureEnabledImpl(Features, "f16c", true); 3408 setFeatureEnabledImpl(Features, "tbm", true); 3409 LLVM_FALLTHROUGH; 3410 case CK_BDVER1: 3411 // xop implies avx, sse4a and fma4. 3412 setFeatureEnabledImpl(Features, "xop", true); 3413 setFeatureEnabledImpl(Features, "lwp", true); 3414 setFeatureEnabledImpl(Features, "lzcnt", true); 3415 setFeatureEnabledImpl(Features, "aes", true); 3416 setFeatureEnabledImpl(Features, "pclmul", true); 3417 setFeatureEnabledImpl(Features, "prfchw", true); 3418 setFeatureEnabledImpl(Features, "cx16", true); 3419 setFeatureEnabledImpl(Features, "fxsr", true); 3420 setFeatureEnabledImpl(Features, "xsave", true); 3421 break; 3422 } 3423 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3424 return false; 3425 3426 // Can't do this earlier because we need to be able to explicitly enable 3427 // or disable these features and the things that they depend upon. 3428 3429 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3430 auto I = Features.find("sse4.2"); 3431 if (I != Features.end() && I->getValue() && 3432 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3433 FeaturesVec.end()) 3434 Features["popcnt"] = true; 3435 3436 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3437 I = Features.find("3dnow"); 3438 if (I != Features.end() && I->getValue() && 3439 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3440 FeaturesVec.end()) 3441 Features["prfchw"] = true; 3442 3443 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3444 // then enable MMX. 3445 I = Features.find("sse"); 3446 if (I != Features.end() && I->getValue() && 3447 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3448 FeaturesVec.end()) 3449 Features["mmx"] = true; 3450 3451 return true; 3452 } 3453 3454 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3455 X86SSEEnum Level, bool Enabled) { 3456 if (Enabled) { 3457 switch (Level) { 3458 case AVX512F: 3459 Features["avx512f"] = true; 3460 LLVM_FALLTHROUGH; 3461 case AVX2: 3462 Features["avx2"] = true; 3463 LLVM_FALLTHROUGH; 3464 case AVX: 3465 Features["avx"] = true; 3466 Features["xsave"] = true; 3467 LLVM_FALLTHROUGH; 3468 case SSE42: 3469 Features["sse4.2"] = true; 3470 LLVM_FALLTHROUGH; 3471 case SSE41: 3472 Features["sse4.1"] = true; 3473 LLVM_FALLTHROUGH; 3474 case SSSE3: 3475 Features["ssse3"] = true; 3476 LLVM_FALLTHROUGH; 3477 case SSE3: 3478 Features["sse3"] = true; 3479 LLVM_FALLTHROUGH; 3480 case SSE2: 3481 Features["sse2"] = true; 3482 LLVM_FALLTHROUGH; 3483 case SSE1: 3484 Features["sse"] = true; 3485 LLVM_FALLTHROUGH; 3486 case NoSSE: 3487 break; 3488 } 3489 return; 3490 } 3491 3492 switch (Level) { 3493 case NoSSE: 3494 case SSE1: 3495 Features["sse"] = false; 3496 LLVM_FALLTHROUGH; 3497 case SSE2: 3498 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3499 Features["sha"] = false; 3500 LLVM_FALLTHROUGH; 3501 case SSE3: 3502 Features["sse3"] = false; 3503 setXOPLevel(Features, NoXOP, false); 3504 LLVM_FALLTHROUGH; 3505 case SSSE3: 3506 Features["ssse3"] = false; 3507 LLVM_FALLTHROUGH; 3508 case SSE41: 3509 Features["sse4.1"] = false; 3510 LLVM_FALLTHROUGH; 3511 case SSE42: 3512 Features["sse4.2"] = false; 3513 LLVM_FALLTHROUGH; 3514 case AVX: 3515 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3516 Features["xsaveopt"] = false; 3517 setXOPLevel(Features, FMA4, false); 3518 LLVM_FALLTHROUGH; 3519 case AVX2: 3520 Features["avx2"] = false; 3521 LLVM_FALLTHROUGH; 3522 case AVX512F: 3523 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3524 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3525 Features["avx512vl"] = Features["avx512vbmi"] = 3526 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 3527 } 3528 } 3529 3530 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3531 MMX3DNowEnum Level, bool Enabled) { 3532 if (Enabled) { 3533 switch (Level) { 3534 case AMD3DNowAthlon: 3535 Features["3dnowa"] = true; 3536 LLVM_FALLTHROUGH; 3537 case AMD3DNow: 3538 Features["3dnow"] = true; 3539 LLVM_FALLTHROUGH; 3540 case MMX: 3541 Features["mmx"] = true; 3542 LLVM_FALLTHROUGH; 3543 case NoMMX3DNow: 3544 break; 3545 } 3546 return; 3547 } 3548 3549 switch (Level) { 3550 case NoMMX3DNow: 3551 case MMX: 3552 Features["mmx"] = false; 3553 LLVM_FALLTHROUGH; 3554 case AMD3DNow: 3555 Features["3dnow"] = false; 3556 LLVM_FALLTHROUGH; 3557 case AMD3DNowAthlon: 3558 Features["3dnowa"] = false; 3559 } 3560 } 3561 3562 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3563 bool Enabled) { 3564 if (Enabled) { 3565 switch (Level) { 3566 case XOP: 3567 Features["xop"] = true; 3568 LLVM_FALLTHROUGH; 3569 case FMA4: 3570 Features["fma4"] = true; 3571 setSSELevel(Features, AVX, true); 3572 LLVM_FALLTHROUGH; 3573 case SSE4A: 3574 Features["sse4a"] = true; 3575 setSSELevel(Features, SSE3, true); 3576 LLVM_FALLTHROUGH; 3577 case NoXOP: 3578 break; 3579 } 3580 return; 3581 } 3582 3583 switch (Level) { 3584 case NoXOP: 3585 case SSE4A: 3586 Features["sse4a"] = false; 3587 LLVM_FALLTHROUGH; 3588 case FMA4: 3589 Features["fma4"] = false; 3590 LLVM_FALLTHROUGH; 3591 case XOP: 3592 Features["xop"] = false; 3593 } 3594 } 3595 3596 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3597 StringRef Name, bool Enabled) { 3598 // This is a bit of a hack to deal with the sse4 target feature when used 3599 // as part of the target attribute. We handle sse4 correctly everywhere 3600 // else. See below for more information on how we handle the sse4 options. 3601 if (Name != "sse4") 3602 Features[Name] = Enabled; 3603 3604 if (Name == "mmx") { 3605 setMMXLevel(Features, MMX, Enabled); 3606 } else if (Name == "sse") { 3607 setSSELevel(Features, SSE1, Enabled); 3608 } else if (Name == "sse2") { 3609 setSSELevel(Features, SSE2, Enabled); 3610 } else if (Name == "sse3") { 3611 setSSELevel(Features, SSE3, Enabled); 3612 } else if (Name == "ssse3") { 3613 setSSELevel(Features, SSSE3, Enabled); 3614 } else if (Name == "sse4.2") { 3615 setSSELevel(Features, SSE42, Enabled); 3616 } else if (Name == "sse4.1") { 3617 setSSELevel(Features, SSE41, Enabled); 3618 } else if (Name == "3dnow") { 3619 setMMXLevel(Features, AMD3DNow, Enabled); 3620 } else if (Name == "3dnowa") { 3621 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3622 } else if (Name == "aes") { 3623 if (Enabled) 3624 setSSELevel(Features, SSE2, Enabled); 3625 } else if (Name == "pclmul") { 3626 if (Enabled) 3627 setSSELevel(Features, SSE2, Enabled); 3628 } else if (Name == "avx") { 3629 setSSELevel(Features, AVX, Enabled); 3630 } else if (Name == "avx2") { 3631 setSSELevel(Features, AVX2, Enabled); 3632 } else if (Name == "avx512f") { 3633 setSSELevel(Features, AVX512F, Enabled); 3634 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3635 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3636 Name == "avx512vbmi" || Name == "avx512ifma" || 3637 Name == "avx512vpopcntdq") { 3638 if (Enabled) 3639 setSSELevel(Features, AVX512F, Enabled); 3640 // Enable BWI instruction if VBMI is being enabled. 3641 if (Name == "avx512vbmi" && Enabled) 3642 Features["avx512bw"] = true; 3643 // Also disable VBMI if BWI is being disabled. 3644 if (Name == "avx512bw" && !Enabled) 3645 Features["avx512vbmi"] = false; 3646 } else if (Name == "fma") { 3647 if (Enabled) 3648 setSSELevel(Features, AVX, Enabled); 3649 } else if (Name == "fma4") { 3650 setXOPLevel(Features, FMA4, Enabled); 3651 } else if (Name == "xop") { 3652 setXOPLevel(Features, XOP, Enabled); 3653 } else if (Name == "sse4a") { 3654 setXOPLevel(Features, SSE4A, Enabled); 3655 } else if (Name == "f16c") { 3656 if (Enabled) 3657 setSSELevel(Features, AVX, Enabled); 3658 } else if (Name == "sha") { 3659 if (Enabled) 3660 setSSELevel(Features, SSE2, Enabled); 3661 } else if (Name == "sse4") { 3662 // We can get here via the __target__ attribute since that's not controlled 3663 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3664 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3665 // disabled. 3666 if (Enabled) 3667 setSSELevel(Features, SSE42, Enabled); 3668 else 3669 setSSELevel(Features, SSE41, Enabled); 3670 } else if (Name == "xsave") { 3671 if (!Enabled) 3672 Features["xsaveopt"] = false; 3673 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3674 if (Enabled) 3675 Features["xsave"] = true; 3676 } 3677 } 3678 3679 /// handleTargetFeatures - Perform initialization based on the user 3680 /// configured set of features. 3681 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3682 DiagnosticsEngine &Diags) { 3683 for (const auto &Feature : Features) { 3684 if (Feature[0] != '+') 3685 continue; 3686 3687 if (Feature == "+aes") { 3688 HasAES = true; 3689 } else if (Feature == "+pclmul") { 3690 HasPCLMUL = true; 3691 } else if (Feature == "+lzcnt") { 3692 HasLZCNT = true; 3693 } else if (Feature == "+rdrnd") { 3694 HasRDRND = true; 3695 } else if (Feature == "+fsgsbase") { 3696 HasFSGSBASE = true; 3697 } else if (Feature == "+bmi") { 3698 HasBMI = true; 3699 } else if (Feature == "+bmi2") { 3700 HasBMI2 = true; 3701 } else if (Feature == "+popcnt") { 3702 HasPOPCNT = true; 3703 } else if (Feature == "+rtm") { 3704 HasRTM = true; 3705 } else if (Feature == "+prfchw") { 3706 HasPRFCHW = true; 3707 } else if (Feature == "+rdseed") { 3708 HasRDSEED = true; 3709 } else if (Feature == "+adx") { 3710 HasADX = true; 3711 } else if (Feature == "+tbm") { 3712 HasTBM = true; 3713 } else if (Feature == "+lwp") { 3714 HasLWP = true; 3715 } else if (Feature == "+fma") { 3716 HasFMA = true; 3717 } else if (Feature == "+f16c") { 3718 HasF16C = true; 3719 } else if (Feature == "+avx512cd") { 3720 HasAVX512CD = true; 3721 } else if (Feature == "+avx512vpopcntdq") { 3722 HasAVX512VPOPCNTDQ = true; 3723 } else if (Feature == "+avx512er") { 3724 HasAVX512ER = true; 3725 } else if (Feature == "+avx512pf") { 3726 HasAVX512PF = true; 3727 } else if (Feature == "+avx512dq") { 3728 HasAVX512DQ = true; 3729 } else if (Feature == "+avx512bw") { 3730 HasAVX512BW = true; 3731 } else if (Feature == "+avx512vl") { 3732 HasAVX512VL = true; 3733 } else if (Feature == "+avx512vbmi") { 3734 HasAVX512VBMI = true; 3735 } else if (Feature == "+avx512ifma") { 3736 HasAVX512IFMA = true; 3737 } else if (Feature == "+sha") { 3738 HasSHA = true; 3739 } else if (Feature == "+mpx") { 3740 HasMPX = true; 3741 } else if (Feature == "+movbe") { 3742 HasMOVBE = true; 3743 } else if (Feature == "+sgx") { 3744 HasSGX = true; 3745 } else if (Feature == "+cx16") { 3746 HasCX16 = true; 3747 } else if (Feature == "+fxsr") { 3748 HasFXSR = true; 3749 } else if (Feature == "+xsave") { 3750 HasXSAVE = true; 3751 } else if (Feature == "+xsaveopt") { 3752 HasXSAVEOPT = true; 3753 } else if (Feature == "+xsavec") { 3754 HasXSAVEC = true; 3755 } else if (Feature == "+xsaves") { 3756 HasXSAVES = true; 3757 } else if (Feature == "+mwaitx") { 3758 HasMWAITX = true; 3759 } else if (Feature == "+pku") { 3760 HasPKU = true; 3761 } else if (Feature == "+clflushopt") { 3762 HasCLFLUSHOPT = true; 3763 } else if (Feature == "+clwb") { 3764 HasCLWB = true; 3765 } else if (Feature == "+prefetchwt1") { 3766 HasPREFETCHWT1 = true; 3767 } else if (Feature == "+clzero") { 3768 HasCLZERO = true; 3769 } 3770 3771 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3772 .Case("+avx512f", AVX512F) 3773 .Case("+avx2", AVX2) 3774 .Case("+avx", AVX) 3775 .Case("+sse4.2", SSE42) 3776 .Case("+sse4.1", SSE41) 3777 .Case("+ssse3", SSSE3) 3778 .Case("+sse3", SSE3) 3779 .Case("+sse2", SSE2) 3780 .Case("+sse", SSE1) 3781 .Default(NoSSE); 3782 SSELevel = std::max(SSELevel, Level); 3783 3784 MMX3DNowEnum ThreeDNowLevel = 3785 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3786 .Case("+3dnowa", AMD3DNowAthlon) 3787 .Case("+3dnow", AMD3DNow) 3788 .Case("+mmx", MMX) 3789 .Default(NoMMX3DNow); 3790 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3791 3792 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3793 .Case("+xop", XOP) 3794 .Case("+fma4", FMA4) 3795 .Case("+sse4a", SSE4A) 3796 .Default(NoXOP); 3797 XOPLevel = std::max(XOPLevel, XLevel); 3798 } 3799 3800 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3801 // matches the selected sse level. 3802 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3803 (FPMath == FP_387 && SSELevel >= SSE1)) { 3804 Diags.Report(diag::err_target_unsupported_fpmath) << 3805 (FPMath == FP_SSE ? "sse" : "387"); 3806 return false; 3807 } 3808 3809 SimdDefaultAlign = 3810 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3811 return true; 3812 } 3813 3814 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3815 /// definitions for this particular subtarget. 3816 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3817 MacroBuilder &Builder) const { 3818 // Target identification. 3819 if (getTriple().getArch() == llvm::Triple::x86_64) { 3820 Builder.defineMacro("__amd64__"); 3821 Builder.defineMacro("__amd64"); 3822 Builder.defineMacro("__x86_64"); 3823 Builder.defineMacro("__x86_64__"); 3824 if (getTriple().getArchName() == "x86_64h") { 3825 Builder.defineMacro("__x86_64h"); 3826 Builder.defineMacro("__x86_64h__"); 3827 } 3828 } else { 3829 DefineStd(Builder, "i386", Opts); 3830 } 3831 3832 // Subtarget options. 3833 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3834 // truly should be based on -mtune options. 3835 switch (CPU) { 3836 case CK_Generic: 3837 break; 3838 case CK_i386: 3839 // The rest are coming from the i386 define above. 3840 Builder.defineMacro("__tune_i386__"); 3841 break; 3842 case CK_i486: 3843 case CK_WinChipC6: 3844 case CK_WinChip2: 3845 case CK_C3: 3846 defineCPUMacros(Builder, "i486"); 3847 break; 3848 case CK_PentiumMMX: 3849 Builder.defineMacro("__pentium_mmx__"); 3850 Builder.defineMacro("__tune_pentium_mmx__"); 3851 // Fallthrough 3852 case CK_i586: 3853 case CK_Pentium: 3854 defineCPUMacros(Builder, "i586"); 3855 defineCPUMacros(Builder, "pentium"); 3856 break; 3857 case CK_Pentium3: 3858 case CK_Pentium3M: 3859 case CK_PentiumM: 3860 Builder.defineMacro("__tune_pentium3__"); 3861 // Fallthrough 3862 case CK_Pentium2: 3863 case CK_C3_2: 3864 Builder.defineMacro("__tune_pentium2__"); 3865 // Fallthrough 3866 case CK_PentiumPro: 3867 Builder.defineMacro("__tune_i686__"); 3868 Builder.defineMacro("__tune_pentiumpro__"); 3869 // Fallthrough 3870 case CK_i686: 3871 Builder.defineMacro("__i686"); 3872 Builder.defineMacro("__i686__"); 3873 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3874 Builder.defineMacro("__pentiumpro"); 3875 Builder.defineMacro("__pentiumpro__"); 3876 break; 3877 case CK_Pentium4: 3878 case CK_Pentium4M: 3879 defineCPUMacros(Builder, "pentium4"); 3880 break; 3881 case CK_Yonah: 3882 case CK_Prescott: 3883 case CK_Nocona: 3884 defineCPUMacros(Builder, "nocona"); 3885 break; 3886 case CK_Core2: 3887 case CK_Penryn: 3888 defineCPUMacros(Builder, "core2"); 3889 break; 3890 case CK_Bonnell: 3891 defineCPUMacros(Builder, "atom"); 3892 break; 3893 case CK_Silvermont: 3894 defineCPUMacros(Builder, "slm"); 3895 break; 3896 case CK_Nehalem: 3897 case CK_Westmere: 3898 case CK_SandyBridge: 3899 case CK_IvyBridge: 3900 case CK_Haswell: 3901 case CK_Broadwell: 3902 case CK_SkylakeClient: 3903 // FIXME: Historically, we defined this legacy name, it would be nice to 3904 // remove it at some point. We've never exposed fine-grained names for 3905 // recent primary x86 CPUs, and we should keep it that way. 3906 defineCPUMacros(Builder, "corei7"); 3907 break; 3908 case CK_SkylakeServer: 3909 defineCPUMacros(Builder, "skx"); 3910 break; 3911 case CK_Cannonlake: 3912 break; 3913 case CK_KNL: 3914 defineCPUMacros(Builder, "knl"); 3915 break; 3916 case CK_Lakemont: 3917 Builder.defineMacro("__tune_lakemont__"); 3918 break; 3919 case CK_K6_2: 3920 Builder.defineMacro("__k6_2__"); 3921 Builder.defineMacro("__tune_k6_2__"); 3922 // Fallthrough 3923 case CK_K6_3: 3924 if (CPU != CK_K6_2) { // In case of fallthrough 3925 // FIXME: GCC may be enabling these in cases where some other k6 3926 // architecture is specified but -m3dnow is explicitly provided. The 3927 // exact semantics need to be determined and emulated here. 3928 Builder.defineMacro("__k6_3__"); 3929 Builder.defineMacro("__tune_k6_3__"); 3930 } 3931 // Fallthrough 3932 case CK_K6: 3933 defineCPUMacros(Builder, "k6"); 3934 break; 3935 case CK_Athlon: 3936 case CK_AthlonThunderbird: 3937 case CK_Athlon4: 3938 case CK_AthlonXP: 3939 case CK_AthlonMP: 3940 defineCPUMacros(Builder, "athlon"); 3941 if (SSELevel != NoSSE) { 3942 Builder.defineMacro("__athlon_sse__"); 3943 Builder.defineMacro("__tune_athlon_sse__"); 3944 } 3945 break; 3946 case CK_K8: 3947 case CK_K8SSE3: 3948 case CK_x86_64: 3949 case CK_Opteron: 3950 case CK_OpteronSSE3: 3951 case CK_Athlon64: 3952 case CK_Athlon64SSE3: 3953 case CK_AthlonFX: 3954 defineCPUMacros(Builder, "k8"); 3955 break; 3956 case CK_AMDFAM10: 3957 defineCPUMacros(Builder, "amdfam10"); 3958 break; 3959 case CK_BTVER1: 3960 defineCPUMacros(Builder, "btver1"); 3961 break; 3962 case CK_BTVER2: 3963 defineCPUMacros(Builder, "btver2"); 3964 break; 3965 case CK_BDVER1: 3966 defineCPUMacros(Builder, "bdver1"); 3967 break; 3968 case CK_BDVER2: 3969 defineCPUMacros(Builder, "bdver2"); 3970 break; 3971 case CK_BDVER3: 3972 defineCPUMacros(Builder, "bdver3"); 3973 break; 3974 case CK_BDVER4: 3975 defineCPUMacros(Builder, "bdver4"); 3976 break; 3977 case CK_ZNVER1: 3978 defineCPUMacros(Builder, "znver1"); 3979 break; 3980 case CK_Geode: 3981 defineCPUMacros(Builder, "geode"); 3982 break; 3983 } 3984 3985 // Target properties. 3986 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3987 3988 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3989 // functions in glibc header files that use FP Stack inline asm which the 3990 // backend can't deal with (PR879). 3991 Builder.defineMacro("__NO_MATH_INLINES"); 3992 3993 if (HasAES) 3994 Builder.defineMacro("__AES__"); 3995 3996 if (HasPCLMUL) 3997 Builder.defineMacro("__PCLMUL__"); 3998 3999 if (HasLZCNT) 4000 Builder.defineMacro("__LZCNT__"); 4001 4002 if (HasRDRND) 4003 Builder.defineMacro("__RDRND__"); 4004 4005 if (HasFSGSBASE) 4006 Builder.defineMacro("__FSGSBASE__"); 4007 4008 if (HasBMI) 4009 Builder.defineMacro("__BMI__"); 4010 4011 if (HasBMI2) 4012 Builder.defineMacro("__BMI2__"); 4013 4014 if (HasPOPCNT) 4015 Builder.defineMacro("__POPCNT__"); 4016 4017 if (HasRTM) 4018 Builder.defineMacro("__RTM__"); 4019 4020 if (HasPRFCHW) 4021 Builder.defineMacro("__PRFCHW__"); 4022 4023 if (HasRDSEED) 4024 Builder.defineMacro("__RDSEED__"); 4025 4026 if (HasADX) 4027 Builder.defineMacro("__ADX__"); 4028 4029 if (HasTBM) 4030 Builder.defineMacro("__TBM__"); 4031 4032 if (HasLWP) 4033 Builder.defineMacro("__LWP__"); 4034 4035 if (HasMWAITX) 4036 Builder.defineMacro("__MWAITX__"); 4037 4038 switch (XOPLevel) { 4039 case XOP: 4040 Builder.defineMacro("__XOP__"); 4041 LLVM_FALLTHROUGH; 4042 case FMA4: 4043 Builder.defineMacro("__FMA4__"); 4044 LLVM_FALLTHROUGH; 4045 case SSE4A: 4046 Builder.defineMacro("__SSE4A__"); 4047 LLVM_FALLTHROUGH; 4048 case NoXOP: 4049 break; 4050 } 4051 4052 if (HasFMA) 4053 Builder.defineMacro("__FMA__"); 4054 4055 if (HasF16C) 4056 Builder.defineMacro("__F16C__"); 4057 4058 if (HasAVX512CD) 4059 Builder.defineMacro("__AVX512CD__"); 4060 if (HasAVX512VPOPCNTDQ) 4061 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 4062 if (HasAVX512ER) 4063 Builder.defineMacro("__AVX512ER__"); 4064 if (HasAVX512PF) 4065 Builder.defineMacro("__AVX512PF__"); 4066 if (HasAVX512DQ) 4067 Builder.defineMacro("__AVX512DQ__"); 4068 if (HasAVX512BW) 4069 Builder.defineMacro("__AVX512BW__"); 4070 if (HasAVX512VL) 4071 Builder.defineMacro("__AVX512VL__"); 4072 if (HasAVX512VBMI) 4073 Builder.defineMacro("__AVX512VBMI__"); 4074 if (HasAVX512IFMA) 4075 Builder.defineMacro("__AVX512IFMA__"); 4076 4077 if (HasSHA) 4078 Builder.defineMacro("__SHA__"); 4079 4080 if (HasFXSR) 4081 Builder.defineMacro("__FXSR__"); 4082 if (HasXSAVE) 4083 Builder.defineMacro("__XSAVE__"); 4084 if (HasXSAVEOPT) 4085 Builder.defineMacro("__XSAVEOPT__"); 4086 if (HasXSAVEC) 4087 Builder.defineMacro("__XSAVEC__"); 4088 if (HasXSAVES) 4089 Builder.defineMacro("__XSAVES__"); 4090 if (HasPKU) 4091 Builder.defineMacro("__PKU__"); 4092 if (HasCX16) 4093 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 4094 if (HasCLFLUSHOPT) 4095 Builder.defineMacro("__CLFLUSHOPT__"); 4096 if (HasCLWB) 4097 Builder.defineMacro("__CLWB__"); 4098 if (HasMPX) 4099 Builder.defineMacro("__MPX__"); 4100 if (HasSGX) 4101 Builder.defineMacro("__SGX__"); 4102 if (HasPREFETCHWT1) 4103 Builder.defineMacro("__PREFETCHWT1__"); 4104 if (HasCLZERO) 4105 Builder.defineMacro("__CLZERO__"); 4106 4107 // Each case falls through to the previous one here. 4108 switch (SSELevel) { 4109 case AVX512F: 4110 Builder.defineMacro("__AVX512F__"); 4111 LLVM_FALLTHROUGH; 4112 case AVX2: 4113 Builder.defineMacro("__AVX2__"); 4114 LLVM_FALLTHROUGH; 4115 case AVX: 4116 Builder.defineMacro("__AVX__"); 4117 LLVM_FALLTHROUGH; 4118 case SSE42: 4119 Builder.defineMacro("__SSE4_2__"); 4120 LLVM_FALLTHROUGH; 4121 case SSE41: 4122 Builder.defineMacro("__SSE4_1__"); 4123 LLVM_FALLTHROUGH; 4124 case SSSE3: 4125 Builder.defineMacro("__SSSE3__"); 4126 LLVM_FALLTHROUGH; 4127 case SSE3: 4128 Builder.defineMacro("__SSE3__"); 4129 LLVM_FALLTHROUGH; 4130 case SSE2: 4131 Builder.defineMacro("__SSE2__"); 4132 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 4133 LLVM_FALLTHROUGH; 4134 case SSE1: 4135 Builder.defineMacro("__SSE__"); 4136 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 4137 LLVM_FALLTHROUGH; 4138 case NoSSE: 4139 break; 4140 } 4141 4142 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 4143 switch (SSELevel) { 4144 case AVX512F: 4145 case AVX2: 4146 case AVX: 4147 case SSE42: 4148 case SSE41: 4149 case SSSE3: 4150 case SSE3: 4151 case SSE2: 4152 Builder.defineMacro("_M_IX86_FP", Twine(2)); 4153 break; 4154 case SSE1: 4155 Builder.defineMacro("_M_IX86_FP", Twine(1)); 4156 break; 4157 default: 4158 Builder.defineMacro("_M_IX86_FP", Twine(0)); 4159 } 4160 } 4161 4162 // Each case falls through to the previous one here. 4163 switch (MMX3DNowLevel) { 4164 case AMD3DNowAthlon: 4165 Builder.defineMacro("__3dNOW_A__"); 4166 LLVM_FALLTHROUGH; 4167 case AMD3DNow: 4168 Builder.defineMacro("__3dNOW__"); 4169 LLVM_FALLTHROUGH; 4170 case MMX: 4171 Builder.defineMacro("__MMX__"); 4172 LLVM_FALLTHROUGH; 4173 case NoMMX3DNow: 4174 break; 4175 } 4176 4177 if (CPU >= CK_i486) { 4178 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4179 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4180 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4181 } 4182 if (CPU >= CK_i586) 4183 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4184 4185 if (HasFloat128) 4186 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 4187 } 4188 4189 bool X86TargetInfo::hasFeature(StringRef Feature) const { 4190 return llvm::StringSwitch<bool>(Feature) 4191 .Case("aes", HasAES) 4192 .Case("avx", SSELevel >= AVX) 4193 .Case("avx2", SSELevel >= AVX2) 4194 .Case("avx512f", SSELevel >= AVX512F) 4195 .Case("avx512cd", HasAVX512CD) 4196 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 4197 .Case("avx512er", HasAVX512ER) 4198 .Case("avx512pf", HasAVX512PF) 4199 .Case("avx512dq", HasAVX512DQ) 4200 .Case("avx512bw", HasAVX512BW) 4201 .Case("avx512vl", HasAVX512VL) 4202 .Case("avx512vbmi", HasAVX512VBMI) 4203 .Case("avx512ifma", HasAVX512IFMA) 4204 .Case("bmi", HasBMI) 4205 .Case("bmi2", HasBMI2) 4206 .Case("clflushopt", HasCLFLUSHOPT) 4207 .Case("clwb", HasCLWB) 4208 .Case("clzero", HasCLZERO) 4209 .Case("cx16", HasCX16) 4210 .Case("f16c", HasF16C) 4211 .Case("fma", HasFMA) 4212 .Case("fma4", XOPLevel >= FMA4) 4213 .Case("fsgsbase", HasFSGSBASE) 4214 .Case("fxsr", HasFXSR) 4215 .Case("lzcnt", HasLZCNT) 4216 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4217 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4218 .Case("mmx", MMX3DNowLevel >= MMX) 4219 .Case("movbe", HasMOVBE) 4220 .Case("mpx", HasMPX) 4221 .Case("pclmul", HasPCLMUL) 4222 .Case("pku", HasPKU) 4223 .Case("popcnt", HasPOPCNT) 4224 .Case("prefetchwt1", HasPREFETCHWT1) 4225 .Case("prfchw", HasPRFCHW) 4226 .Case("rdrnd", HasRDRND) 4227 .Case("rdseed", HasRDSEED) 4228 .Case("rtm", HasRTM) 4229 .Case("sgx", HasSGX) 4230 .Case("sha", HasSHA) 4231 .Case("sse", SSELevel >= SSE1) 4232 .Case("sse2", SSELevel >= SSE2) 4233 .Case("sse3", SSELevel >= SSE3) 4234 .Case("ssse3", SSELevel >= SSSE3) 4235 .Case("sse4.1", SSELevel >= SSE41) 4236 .Case("sse4.2", SSELevel >= SSE42) 4237 .Case("sse4a", XOPLevel >= SSE4A) 4238 .Case("tbm", HasTBM) 4239 .Case("lwp", HasLWP) 4240 .Case("x86", true) 4241 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4242 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4243 .Case("xop", XOPLevel >= XOP) 4244 .Case("xsave", HasXSAVE) 4245 .Case("xsavec", HasXSAVEC) 4246 .Case("xsaves", HasXSAVES) 4247 .Case("xsaveopt", HasXSAVEOPT) 4248 .Default(false); 4249 } 4250 4251 // We can't use a generic validation scheme for the features accepted here 4252 // versus subtarget features accepted in the target attribute because the 4253 // bitfield structure that's initialized in the runtime only supports the 4254 // below currently rather than the full range of subtarget features. (See 4255 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4256 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4257 return llvm::StringSwitch<bool>(FeatureStr) 4258 .Case("cmov", true) 4259 .Case("mmx", true) 4260 .Case("popcnt", true) 4261 .Case("sse", true) 4262 .Case("sse2", true) 4263 .Case("sse3", true) 4264 .Case("ssse3", true) 4265 .Case("sse4.1", true) 4266 .Case("sse4.2", true) 4267 .Case("avx", true) 4268 .Case("avx2", true) 4269 .Case("sse4a", true) 4270 .Case("fma4", true) 4271 .Case("xop", true) 4272 .Case("fma", true) 4273 .Case("avx512f", true) 4274 .Case("bmi", true) 4275 .Case("bmi2", true) 4276 .Case("aes", true) 4277 .Case("pclmul", true) 4278 .Case("avx512vl", true) 4279 .Case("avx512bw", true) 4280 .Case("avx512dq", true) 4281 .Case("avx512cd", true) 4282 .Case("avx512vpopcntdq", true) 4283 .Case("avx512er", true) 4284 .Case("avx512pf", true) 4285 .Case("avx512vbmi", true) 4286 .Case("avx512ifma", true) 4287 .Default(false); 4288 } 4289 4290 bool 4291 X86TargetInfo::validateAsmConstraint(const char *&Name, 4292 TargetInfo::ConstraintInfo &Info) const { 4293 switch (*Name) { 4294 default: return false; 4295 // Constant constraints. 4296 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4297 // instructions. 4298 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4299 // x86_64 instructions. 4300 case 's': 4301 Info.setRequiresImmediate(); 4302 return true; 4303 case 'I': 4304 Info.setRequiresImmediate(0, 31); 4305 return true; 4306 case 'J': 4307 Info.setRequiresImmediate(0, 63); 4308 return true; 4309 case 'K': 4310 Info.setRequiresImmediate(-128, 127); 4311 return true; 4312 case 'L': 4313 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4314 return true; 4315 case 'M': 4316 Info.setRequiresImmediate(0, 3); 4317 return true; 4318 case 'N': 4319 Info.setRequiresImmediate(0, 255); 4320 return true; 4321 case 'O': 4322 Info.setRequiresImmediate(0, 127); 4323 return true; 4324 // Register constraints. 4325 case 'Y': // 'Y' is the first character for several 2-character constraints. 4326 // Shift the pointer to the second character of the constraint. 4327 Name++; 4328 switch (*Name) { 4329 default: 4330 return false; 4331 case '0': // First SSE register. 4332 case 't': // Any SSE register, when SSE2 is enabled. 4333 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4334 case 'm': // Any MMX register, when inter-unit moves enabled. 4335 case 'k': // AVX512 arch mask registers: k1-k7. 4336 Info.setAllowsRegister(); 4337 return true; 4338 } 4339 case 'f': // Any x87 floating point stack register. 4340 // Constraint 'f' cannot be used for output operands. 4341 if (Info.ConstraintStr[0] == '=') 4342 return false; 4343 Info.setAllowsRegister(); 4344 return true; 4345 case 'a': // eax. 4346 case 'b': // ebx. 4347 case 'c': // ecx. 4348 case 'd': // edx. 4349 case 'S': // esi. 4350 case 'D': // edi. 4351 case 'A': // edx:eax. 4352 case 't': // Top of floating point stack. 4353 case 'u': // Second from top of floating point stack. 4354 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4355 case 'y': // Any MMX register. 4356 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4357 case 'x': // Any SSE register. 4358 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4359 // for intermideate k reg operations). 4360 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4361 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4362 case 'l': // "Index" registers: any general register that can be used as an 4363 // index in a base+index memory access. 4364 Info.setAllowsRegister(); 4365 return true; 4366 // Floating point constant constraints. 4367 case 'C': // SSE floating point constant. 4368 case 'G': // x87 floating point constant. 4369 return true; 4370 } 4371 } 4372 4373 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4374 unsigned Size) const { 4375 // Strip off constraint modifiers. 4376 while (Constraint[0] == '=' || 4377 Constraint[0] == '+' || 4378 Constraint[0] == '&') 4379 Constraint = Constraint.substr(1); 4380 4381 return validateOperandSize(Constraint, Size); 4382 } 4383 4384 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4385 unsigned Size) const { 4386 return validateOperandSize(Constraint, Size); 4387 } 4388 4389 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4390 unsigned Size) const { 4391 switch (Constraint[0]) { 4392 default: break; 4393 case 'k': 4394 // Registers k0-k7 (AVX512) size limit is 64 bit. 4395 case 'y': 4396 return Size <= 64; 4397 case 'f': 4398 case 't': 4399 case 'u': 4400 return Size <= 128; 4401 case 'v': 4402 case 'x': 4403 if (SSELevel >= AVX512F) 4404 // 512-bit zmm registers can be used if target supports AVX512F. 4405 return Size <= 512U; 4406 else if (SSELevel >= AVX) 4407 // 256-bit ymm registers can be used if target supports AVX. 4408 return Size <= 256U; 4409 return Size <= 128U; 4410 case 'Y': 4411 // 'Y' is the first character for several 2-character constraints. 4412 switch (Constraint[1]) { 4413 default: break; 4414 case 'm': 4415 // 'Ym' is synonymous with 'y'. 4416 case 'k': 4417 return Size <= 64; 4418 case 'i': 4419 case 't': 4420 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4421 if (SSELevel >= AVX512F) 4422 return Size <= 512U; 4423 else if (SSELevel >= AVX) 4424 return Size <= 256U; 4425 return SSELevel >= SSE2 && Size <= 128U; 4426 } 4427 4428 } 4429 4430 return true; 4431 } 4432 4433 std::string 4434 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4435 switch (*Constraint) { 4436 case 'a': return std::string("{ax}"); 4437 case 'b': return std::string("{bx}"); 4438 case 'c': return std::string("{cx}"); 4439 case 'd': return std::string("{dx}"); 4440 case 'S': return std::string("{si}"); 4441 case 'D': return std::string("{di}"); 4442 case 'p': // address 4443 return std::string("im"); 4444 case 't': // top of floating point stack. 4445 return std::string("{st}"); 4446 case 'u': // second from top of floating point stack. 4447 return std::string("{st(1)}"); // second from top of floating point stack. 4448 case 'Y': 4449 switch (Constraint[1]) { 4450 default: 4451 // Break from inner switch and fall through (copy single char), 4452 // continue parsing after copying the current constraint into 4453 // the return string. 4454 break; 4455 case 'k': 4456 // "^" hints llvm that this is a 2 letter constraint. 4457 // "Constraint++" is used to promote the string iterator 4458 // to the next constraint. 4459 return std::string("^") + std::string(Constraint++, 2); 4460 } 4461 LLVM_FALLTHROUGH; 4462 default: 4463 return std::string(1, *Constraint); 4464 } 4465 } 4466 4467 // X86-32 generic target 4468 class X86_32TargetInfo : public X86TargetInfo { 4469 public: 4470 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4471 : X86TargetInfo(Triple, Opts) { 4472 DoubleAlign = LongLongAlign = 32; 4473 LongDoubleWidth = 96; 4474 LongDoubleAlign = 32; 4475 SuitableAlign = 128; 4476 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4477 SizeType = UnsignedInt; 4478 PtrDiffType = SignedInt; 4479 IntPtrType = SignedInt; 4480 RegParmMax = 3; 4481 4482 // Use fpret for all types. 4483 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4484 (1 << TargetInfo::Double) | 4485 (1 << TargetInfo::LongDouble)); 4486 4487 // x86-32 has atomics up to 8 bytes 4488 // FIXME: Check that we actually have cmpxchg8b before setting 4489 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4490 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4491 } 4492 BuiltinVaListKind getBuiltinVaListKind() const override { 4493 return TargetInfo::CharPtrBuiltinVaList; 4494 } 4495 4496 int getEHDataRegisterNumber(unsigned RegNo) const override { 4497 if (RegNo == 0) return 0; 4498 if (RegNo == 1) return 2; 4499 return -1; 4500 } 4501 bool validateOperandSize(StringRef Constraint, 4502 unsigned Size) const override { 4503 switch (Constraint[0]) { 4504 default: break; 4505 case 'R': 4506 case 'q': 4507 case 'Q': 4508 case 'a': 4509 case 'b': 4510 case 'c': 4511 case 'd': 4512 case 'S': 4513 case 'D': 4514 return Size <= 32; 4515 case 'A': 4516 return Size <= 64; 4517 } 4518 4519 return X86TargetInfo::validateOperandSize(Constraint, Size); 4520 } 4521 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4522 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4523 Builtin::FirstTSBuiltin + 1); 4524 } 4525 }; 4526 4527 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4528 public: 4529 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4530 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4531 4532 unsigned getFloatEvalMethod() const override { 4533 unsigned Major, Minor, Micro; 4534 getTriple().getOSVersion(Major, Minor, Micro); 4535 // New NetBSD uses the default rounding mode. 4536 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4537 return X86_32TargetInfo::getFloatEvalMethod(); 4538 // NetBSD before 6.99.26 defaults to "double" rounding. 4539 return 1; 4540 } 4541 }; 4542 4543 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4544 public: 4545 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4546 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4547 SizeType = UnsignedLong; 4548 IntPtrType = SignedLong; 4549 PtrDiffType = SignedLong; 4550 } 4551 }; 4552 4553 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4554 public: 4555 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4556 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4557 SizeType = UnsignedLong; 4558 IntPtrType = SignedLong; 4559 PtrDiffType = SignedLong; 4560 } 4561 }; 4562 4563 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4564 public: 4565 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4566 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4567 LongDoubleWidth = 128; 4568 LongDoubleAlign = 128; 4569 SuitableAlign = 128; 4570 MaxVectorAlign = 256; 4571 // The watchOS simulator uses the builtin bool type for Objective-C. 4572 llvm::Triple T = llvm::Triple(Triple); 4573 if (T.isWatchOS()) 4574 UseSignedCharForObjCBool = false; 4575 SizeType = UnsignedLong; 4576 IntPtrType = SignedLong; 4577 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4578 HasAlignMac68kSupport = true; 4579 } 4580 4581 bool handleTargetFeatures(std::vector<std::string> &Features, 4582 DiagnosticsEngine &Diags) override { 4583 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4584 Diags)) 4585 return false; 4586 // We now know the features we have: we can decide how to align vectors. 4587 MaxVectorAlign = 4588 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4589 return true; 4590 } 4591 }; 4592 4593 // x86-32 Windows target 4594 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4595 public: 4596 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4597 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4598 WCharType = UnsignedShort; 4599 DoubleAlign = LongLongAlign = 64; 4600 bool IsWinCOFF = 4601 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4602 resetDataLayout(IsWinCOFF 4603 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4604 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4605 } 4606 void getTargetDefines(const LangOptions &Opts, 4607 MacroBuilder &Builder) const override { 4608 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4609 } 4610 }; 4611 4612 // x86-32 Windows Visual Studio target 4613 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4614 public: 4615 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4616 const TargetOptions &Opts) 4617 : WindowsX86_32TargetInfo(Triple, Opts) { 4618 LongDoubleWidth = LongDoubleAlign = 64; 4619 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4620 } 4621 void getTargetDefines(const LangOptions &Opts, 4622 MacroBuilder &Builder) const override { 4623 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4624 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4625 // The value of the following reflects processor type. 4626 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4627 // We lost the original triple, so we use the default. 4628 Builder.defineMacro("_M_IX86", "600"); 4629 } 4630 }; 4631 4632 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4633 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4634 // supports __declspec natively under -fms-extensions, but we define a no-op 4635 // __declspec macro anyway for pre-processor compatibility. 4636 if (Opts.MicrosoftExt) 4637 Builder.defineMacro("__declspec", "__declspec"); 4638 else 4639 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4640 4641 if (!Opts.MicrosoftExt) { 4642 // Provide macros for all the calling convention keywords. Provide both 4643 // single and double underscore prefixed variants. These are available on 4644 // x64 as well as x86, even though they have no effect. 4645 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4646 for (const char *CC : CCs) { 4647 std::string GCCSpelling = "__attribute__((__"; 4648 GCCSpelling += CC; 4649 GCCSpelling += "__))"; 4650 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4651 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4652 } 4653 } 4654 } 4655 4656 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4657 Builder.defineMacro("__MSVCRT__"); 4658 Builder.defineMacro("__MINGW32__"); 4659 addCygMingDefines(Opts, Builder); 4660 } 4661 4662 // x86-32 MinGW target 4663 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4664 public: 4665 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4666 : WindowsX86_32TargetInfo(Triple, Opts) { 4667 HasFloat128 = true; 4668 } 4669 void getTargetDefines(const LangOptions &Opts, 4670 MacroBuilder &Builder) const override { 4671 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4672 DefineStd(Builder, "WIN32", Opts); 4673 DefineStd(Builder, "WINNT", Opts); 4674 Builder.defineMacro("_X86_"); 4675 addMinGWDefines(Opts, Builder); 4676 } 4677 }; 4678 4679 // x86-32 Cygwin target 4680 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4681 public: 4682 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4683 : X86_32TargetInfo(Triple, Opts) { 4684 WCharType = UnsignedShort; 4685 DoubleAlign = LongLongAlign = 64; 4686 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4687 } 4688 void getTargetDefines(const LangOptions &Opts, 4689 MacroBuilder &Builder) const override { 4690 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4691 Builder.defineMacro("_X86_"); 4692 Builder.defineMacro("__CYGWIN__"); 4693 Builder.defineMacro("__CYGWIN32__"); 4694 addCygMingDefines(Opts, Builder); 4695 DefineStd(Builder, "unix", Opts); 4696 if (Opts.CPlusPlus) 4697 Builder.defineMacro("_GNU_SOURCE"); 4698 } 4699 }; 4700 4701 // x86-32 Haiku target 4702 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4703 public: 4704 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4705 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4706 } 4707 void getTargetDefines(const LangOptions &Opts, 4708 MacroBuilder &Builder) const override { 4709 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4710 Builder.defineMacro("__INTEL__"); 4711 } 4712 }; 4713 4714 // X86-32 MCU target 4715 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4716 public: 4717 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4718 : X86_32TargetInfo(Triple, Opts) { 4719 LongDoubleWidth = 64; 4720 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4721 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4722 WIntType = UnsignedInt; 4723 } 4724 4725 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4726 // On MCU we support only C calling convention. 4727 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4728 } 4729 4730 void getTargetDefines(const LangOptions &Opts, 4731 MacroBuilder &Builder) const override { 4732 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4733 Builder.defineMacro("__iamcu"); 4734 Builder.defineMacro("__iamcu__"); 4735 } 4736 4737 bool allowsLargerPreferedTypeAlignment() const override { 4738 return false; 4739 } 4740 }; 4741 4742 // RTEMS Target 4743 template<typename Target> 4744 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4745 protected: 4746 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4747 MacroBuilder &Builder) const override { 4748 // RTEMS defines; list based off of gcc output 4749 4750 Builder.defineMacro("__rtems__"); 4751 Builder.defineMacro("__ELF__"); 4752 } 4753 4754 public: 4755 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4756 : OSTargetInfo<Target>(Triple, Opts) { 4757 switch (Triple.getArch()) { 4758 default: 4759 case llvm::Triple::x86: 4760 // this->MCountName = ".mcount"; 4761 break; 4762 case llvm::Triple::mips: 4763 case llvm::Triple::mipsel: 4764 case llvm::Triple::ppc: 4765 case llvm::Triple::ppc64: 4766 case llvm::Triple::ppc64le: 4767 // this->MCountName = "_mcount"; 4768 break; 4769 case llvm::Triple::arm: 4770 // this->MCountName = "__mcount"; 4771 break; 4772 } 4773 } 4774 }; 4775 4776 // x86-32 RTEMS target 4777 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4778 public: 4779 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4780 : X86_32TargetInfo(Triple, Opts) { 4781 SizeType = UnsignedLong; 4782 IntPtrType = SignedLong; 4783 PtrDiffType = SignedLong; 4784 } 4785 void getTargetDefines(const LangOptions &Opts, 4786 MacroBuilder &Builder) const override { 4787 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4788 Builder.defineMacro("__INTEL__"); 4789 Builder.defineMacro("__rtems__"); 4790 } 4791 }; 4792 4793 // x86-64 generic target 4794 class X86_64TargetInfo : public X86TargetInfo { 4795 public: 4796 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4797 : X86TargetInfo(Triple, Opts) { 4798 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4799 bool IsWinCOFF = 4800 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4801 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4802 LongDoubleWidth = 128; 4803 LongDoubleAlign = 128; 4804 LargeArrayMinWidth = 128; 4805 LargeArrayAlign = 128; 4806 SuitableAlign = 128; 4807 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4808 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4809 IntPtrType = IsX32 ? SignedInt : SignedLong; 4810 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4811 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4812 RegParmMax = 6; 4813 4814 // Pointers are 32-bit in x32. 4815 resetDataLayout(IsX32 4816 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4817 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4818 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4819 4820 // Use fpret only for long double. 4821 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4822 4823 // Use fp2ret for _Complex long double. 4824 ComplexLongDoubleUsesFP2Ret = true; 4825 4826 // Make __builtin_ms_va_list available. 4827 HasBuiltinMSVaList = true; 4828 4829 // x86-64 has atomics up to 16 bytes. 4830 MaxAtomicPromoteWidth = 128; 4831 MaxAtomicInlineWidth = 128; 4832 } 4833 BuiltinVaListKind getBuiltinVaListKind() const override { 4834 return TargetInfo::X86_64ABIBuiltinVaList; 4835 } 4836 4837 int getEHDataRegisterNumber(unsigned RegNo) const override { 4838 if (RegNo == 0) return 0; 4839 if (RegNo == 1) return 1; 4840 return -1; 4841 } 4842 4843 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4844 switch (CC) { 4845 case CC_C: 4846 case CC_Swift: 4847 case CC_X86VectorCall: 4848 case CC_IntelOclBicc: 4849 case CC_X86_64Win64: 4850 case CC_PreserveMost: 4851 case CC_PreserveAll: 4852 case CC_X86RegCall: 4853 case CC_OpenCLKernel: 4854 return CCCR_OK; 4855 default: 4856 return CCCR_Warning; 4857 } 4858 } 4859 4860 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4861 return CC_C; 4862 } 4863 4864 // for x32 we need it here explicitly 4865 bool hasInt128Type() const override { return true; } 4866 unsigned getUnwindWordWidth() const override { return 64; } 4867 unsigned getRegisterWidth() const override { return 64; } 4868 4869 bool validateGlobalRegisterVariable(StringRef RegName, 4870 unsigned RegSize, 4871 bool &HasSizeMismatch) const override { 4872 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4873 // handle. 4874 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4875 // Check that the register size is 64-bit. 4876 HasSizeMismatch = RegSize != 64; 4877 return true; 4878 } 4879 4880 // Check if the register is a 32-bit register the backend can handle. 4881 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4882 HasSizeMismatch); 4883 } 4884 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4885 return llvm::makeArrayRef(BuiltinInfoX86, 4886 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4887 } 4888 }; 4889 4890 // x86-64 Windows target 4891 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4892 public: 4893 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4894 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4895 WCharType = UnsignedShort; 4896 LongWidth = LongAlign = 32; 4897 DoubleAlign = LongLongAlign = 64; 4898 IntMaxType = SignedLongLong; 4899 Int64Type = SignedLongLong; 4900 SizeType = UnsignedLongLong; 4901 PtrDiffType = SignedLongLong; 4902 IntPtrType = SignedLongLong; 4903 } 4904 4905 void getTargetDefines(const LangOptions &Opts, 4906 MacroBuilder &Builder) const override { 4907 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4908 Builder.defineMacro("_WIN64"); 4909 } 4910 4911 BuiltinVaListKind getBuiltinVaListKind() const override { 4912 return TargetInfo::CharPtrBuiltinVaList; 4913 } 4914 4915 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4916 switch (CC) { 4917 case CC_X86StdCall: 4918 case CC_X86ThisCall: 4919 case CC_X86FastCall: 4920 return CCCR_Ignore; 4921 case CC_C: 4922 case CC_X86VectorCall: 4923 case CC_IntelOclBicc: 4924 case CC_X86_64SysV: 4925 case CC_Swift: 4926 case CC_X86RegCall: 4927 case CC_OpenCLKernel: 4928 return CCCR_OK; 4929 default: 4930 return CCCR_Warning; 4931 } 4932 } 4933 }; 4934 4935 // x86-64 Windows Visual Studio target 4936 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4937 public: 4938 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4939 const TargetOptions &Opts) 4940 : WindowsX86_64TargetInfo(Triple, Opts) { 4941 LongDoubleWidth = LongDoubleAlign = 64; 4942 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4943 } 4944 void getTargetDefines(const LangOptions &Opts, 4945 MacroBuilder &Builder) const override { 4946 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4947 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4948 Builder.defineMacro("_M_X64", "100"); 4949 Builder.defineMacro("_M_AMD64", "100"); 4950 } 4951 }; 4952 4953 // x86-64 MinGW target 4954 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4955 public: 4956 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4957 : WindowsX86_64TargetInfo(Triple, Opts) { 4958 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4959 // with x86 FP ops. Weird. 4960 LongDoubleWidth = LongDoubleAlign = 128; 4961 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 4962 HasFloat128 = true; 4963 } 4964 4965 void getTargetDefines(const LangOptions &Opts, 4966 MacroBuilder &Builder) const override { 4967 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4968 DefineStd(Builder, "WIN64", Opts); 4969 Builder.defineMacro("__MINGW64__"); 4970 addMinGWDefines(Opts, Builder); 4971 4972 // GCC defines this macro when it is using __gxx_personality_seh0. 4973 if (!Opts.SjLjExceptions) 4974 Builder.defineMacro("__SEH__"); 4975 } 4976 }; 4977 4978 // x86-64 Cygwin target 4979 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4980 public: 4981 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4982 : X86_64TargetInfo(Triple, Opts) { 4983 TLSSupported = false; 4984 WCharType = UnsignedShort; 4985 } 4986 void getTargetDefines(const LangOptions &Opts, 4987 MacroBuilder &Builder) const override { 4988 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4989 Builder.defineMacro("__x86_64__"); 4990 Builder.defineMacro("__CYGWIN__"); 4991 Builder.defineMacro("__CYGWIN64__"); 4992 addCygMingDefines(Opts, Builder); 4993 DefineStd(Builder, "unix", Opts); 4994 if (Opts.CPlusPlus) 4995 Builder.defineMacro("_GNU_SOURCE"); 4996 4997 // GCC defines this macro when it is using __gxx_personality_seh0. 4998 if (!Opts.SjLjExceptions) 4999 Builder.defineMacro("__SEH__"); 5000 } 5001 }; 5002 5003 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 5004 public: 5005 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5006 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5007 Int64Type = SignedLongLong; 5008 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 5009 llvm::Triple T = llvm::Triple(Triple); 5010 if (T.isiOS()) 5011 UseSignedCharForObjCBool = false; 5012 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 5013 } 5014 5015 bool handleTargetFeatures(std::vector<std::string> &Features, 5016 DiagnosticsEngine &Diags) override { 5017 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 5018 Diags)) 5019 return false; 5020 // We now know the features we have: we can decide how to align vectors. 5021 MaxVectorAlign = 5022 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 5023 return true; 5024 } 5025 }; 5026 5027 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 5028 public: 5029 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5030 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5031 IntMaxType = SignedLongLong; 5032 Int64Type = SignedLongLong; 5033 } 5034 }; 5035 5036 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 5037 public: 5038 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5039 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5040 IntMaxType = SignedLongLong; 5041 Int64Type = SignedLongLong; 5042 } 5043 }; 5044 5045 class ARMTargetInfo : public TargetInfo { 5046 // Possible FPU choices. 5047 enum FPUMode { 5048 VFP2FPU = (1 << 0), 5049 VFP3FPU = (1 << 1), 5050 VFP4FPU = (1 << 2), 5051 NeonFPU = (1 << 3), 5052 FPARMV8 = (1 << 4) 5053 }; 5054 5055 // Possible HWDiv features. 5056 enum HWDivMode { 5057 HWDivThumb = (1 << 0), 5058 HWDivARM = (1 << 1) 5059 }; 5060 5061 static bool FPUModeIsVFP(FPUMode Mode) { 5062 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 5063 } 5064 5065 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5066 static const char * const GCCRegNames[]; 5067 5068 std::string ABI, CPU; 5069 5070 StringRef CPUProfile; 5071 StringRef CPUAttr; 5072 5073 enum { 5074 FP_Default, 5075 FP_VFP, 5076 FP_Neon 5077 } FPMath; 5078 5079 unsigned ArchISA; 5080 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 5081 unsigned ArchProfile; 5082 unsigned ArchVersion; 5083 5084 unsigned FPU : 5; 5085 5086 unsigned IsAAPCS : 1; 5087 unsigned HWDiv : 2; 5088 5089 // Initialized via features. 5090 unsigned SoftFloat : 1; 5091 unsigned SoftFloatABI : 1; 5092 5093 unsigned CRC : 1; 5094 unsigned Crypto : 1; 5095 unsigned DSP : 1; 5096 unsigned Unaligned : 1; 5097 5098 enum { 5099 LDREX_B = (1 << 0), /// byte (8-bit) 5100 LDREX_H = (1 << 1), /// half (16-bit) 5101 LDREX_W = (1 << 2), /// word (32-bit) 5102 LDREX_D = (1 << 3), /// double (64-bit) 5103 }; 5104 5105 uint32_t LDREX; 5106 5107 // ACLE 6.5.1 Hardware floating point 5108 enum { 5109 HW_FP_HP = (1 << 1), /// half (16-bit) 5110 HW_FP_SP = (1 << 2), /// single (32-bit) 5111 HW_FP_DP = (1 << 3), /// double (64-bit) 5112 }; 5113 uint32_t HW_FP; 5114 5115 static const Builtin::Info BuiltinInfo[]; 5116 5117 void setABIAAPCS() { 5118 IsAAPCS = true; 5119 5120 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5121 const llvm::Triple &T = getTriple(); 5122 5123 // size_t is unsigned long on MachO-derived environments, NetBSD, 5124 // OpenBSD and Bitrig. 5125 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 5126 T.getOS() == llvm::Triple::OpenBSD || 5127 T.getOS() == llvm::Triple::Bitrig) 5128 SizeType = UnsignedLong; 5129 else 5130 SizeType = UnsignedInt; 5131 5132 switch (T.getOS()) { 5133 case llvm::Triple::NetBSD: 5134 case llvm::Triple::OpenBSD: 5135 WCharType = SignedInt; 5136 break; 5137 case llvm::Triple::Win32: 5138 WCharType = UnsignedShort; 5139 break; 5140 case llvm::Triple::Linux: 5141 default: 5142 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 5143 WCharType = UnsignedInt; 5144 break; 5145 } 5146 5147 UseBitFieldTypeAlignment = true; 5148 5149 ZeroLengthBitfieldBoundary = 0; 5150 5151 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 5152 // so set preferred for small types to 32. 5153 if (T.isOSBinFormatMachO()) { 5154 resetDataLayout(BigEndian 5155 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5156 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5157 } else if (T.isOSWindows()) { 5158 assert(!BigEndian && "Windows on ARM does not support big endian"); 5159 resetDataLayout("e" 5160 "-m:w" 5161 "-p:32:32" 5162 "-i64:64" 5163 "-v128:64:128" 5164 "-a:0:32" 5165 "-n32" 5166 "-S64"); 5167 } else if (T.isOSNaCl()) { 5168 assert(!BigEndian && "NaCl on ARM does not support big endian"); 5169 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 5170 } else { 5171 resetDataLayout(BigEndian 5172 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5173 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5174 } 5175 5176 // FIXME: Enumerated types are variable width in straight AAPCS. 5177 } 5178 5179 void setABIAPCS(bool IsAAPCS16) { 5180 const llvm::Triple &T = getTriple(); 5181 5182 IsAAPCS = false; 5183 5184 if (IsAAPCS16) 5185 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5186 else 5187 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 5188 5189 // size_t is unsigned int on FreeBSD. 5190 if (T.getOS() == llvm::Triple::FreeBSD) 5191 SizeType = UnsignedInt; 5192 else 5193 SizeType = UnsignedLong; 5194 5195 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 5196 WCharType = SignedInt; 5197 5198 // Do not respect the alignment of bit-field types when laying out 5199 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 5200 UseBitFieldTypeAlignment = false; 5201 5202 /// gcc forces the alignment to 4 bytes, regardless of the type of the 5203 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 5204 /// gcc. 5205 ZeroLengthBitfieldBoundary = 32; 5206 5207 if (T.isOSBinFormatMachO() && IsAAPCS16) { 5208 assert(!BigEndian && "AAPCS16 does not support big-endian"); 5209 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 5210 } else if (T.isOSBinFormatMachO()) 5211 resetDataLayout( 5212 BigEndian 5213 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5214 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5215 else 5216 resetDataLayout( 5217 BigEndian 5218 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5219 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5220 5221 // FIXME: Override "preferred align" for double and long long. 5222 } 5223 5224 void setArchInfo() { 5225 StringRef ArchName = getTriple().getArchName(); 5226 5227 ArchISA = llvm::ARM::parseArchISA(ArchName); 5228 CPU = llvm::ARM::getDefaultCPU(ArchName); 5229 unsigned AK = llvm::ARM::parseArch(ArchName); 5230 if (AK != llvm::ARM::AK_INVALID) 5231 ArchKind = AK; 5232 setArchInfo(ArchKind); 5233 } 5234 5235 void setArchInfo(unsigned Kind) { 5236 StringRef SubArch; 5237 5238 // cache TargetParser info 5239 ArchKind = Kind; 5240 SubArch = llvm::ARM::getSubArch(ArchKind); 5241 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5242 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5243 5244 // cache CPU related strings 5245 CPUAttr = getCPUAttr(); 5246 CPUProfile = getCPUProfile(); 5247 } 5248 5249 void setAtomic() { 5250 // when triple does not specify a sub arch, 5251 // then we are not using inline atomics 5252 bool ShouldUseInlineAtomic = 5253 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5254 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5255 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5256 if (ArchProfile == llvm::ARM::PK_M) { 5257 MaxAtomicPromoteWidth = 32; 5258 if (ShouldUseInlineAtomic) 5259 MaxAtomicInlineWidth = 32; 5260 } 5261 else { 5262 MaxAtomicPromoteWidth = 64; 5263 if (ShouldUseInlineAtomic) 5264 MaxAtomicInlineWidth = 64; 5265 } 5266 } 5267 5268 bool isThumb() const { 5269 return (ArchISA == llvm::ARM::IK_THUMB); 5270 } 5271 5272 bool supportsThumb() const { 5273 return CPUAttr.count('T') || ArchVersion >= 6; 5274 } 5275 5276 bool supportsThumb2() const { 5277 return CPUAttr.equals("6T2") || 5278 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5279 } 5280 5281 StringRef getCPUAttr() const { 5282 // For most sub-arches, the build attribute CPU name is enough. 5283 // For Cortex variants, it's slightly different. 5284 switch(ArchKind) { 5285 default: 5286 return llvm::ARM::getCPUAttr(ArchKind); 5287 case llvm::ARM::AK_ARMV6M: 5288 return "6M"; 5289 case llvm::ARM::AK_ARMV7S: 5290 return "7S"; 5291 case llvm::ARM::AK_ARMV7A: 5292 return "7A"; 5293 case llvm::ARM::AK_ARMV7R: 5294 return "7R"; 5295 case llvm::ARM::AK_ARMV7M: 5296 return "7M"; 5297 case llvm::ARM::AK_ARMV7EM: 5298 return "7EM"; 5299 case llvm::ARM::AK_ARMV7VE: 5300 return "7VE"; 5301 case llvm::ARM::AK_ARMV8A: 5302 return "8A"; 5303 case llvm::ARM::AK_ARMV8_1A: 5304 return "8_1A"; 5305 case llvm::ARM::AK_ARMV8_2A: 5306 return "8_2A"; 5307 case llvm::ARM::AK_ARMV8MBaseline: 5308 return "8M_BASE"; 5309 case llvm::ARM::AK_ARMV8MMainline: 5310 return "8M_MAIN"; 5311 case llvm::ARM::AK_ARMV8R: 5312 return "8R"; 5313 } 5314 } 5315 5316 StringRef getCPUProfile() const { 5317 switch(ArchProfile) { 5318 case llvm::ARM::PK_A: 5319 return "A"; 5320 case llvm::ARM::PK_R: 5321 return "R"; 5322 case llvm::ARM::PK_M: 5323 return "M"; 5324 default: 5325 return ""; 5326 } 5327 } 5328 5329 public: 5330 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5331 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5332 HW_FP(0) { 5333 5334 switch (getTriple().getOS()) { 5335 case llvm::Triple::NetBSD: 5336 case llvm::Triple::OpenBSD: 5337 PtrDiffType = SignedLong; 5338 break; 5339 default: 5340 PtrDiffType = SignedInt; 5341 break; 5342 } 5343 5344 // Cache arch related info. 5345 setArchInfo(); 5346 5347 // {} in inline assembly are neon specifiers, not assembly variant 5348 // specifiers. 5349 NoAsmVariants = true; 5350 5351 // FIXME: This duplicates code from the driver that sets the -target-abi 5352 // option - this code is used if -target-abi isn't passed and should 5353 // be unified in some way. 5354 if (Triple.isOSBinFormatMachO()) { 5355 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5356 // the frontend matches that. 5357 if (Triple.getEnvironment() == llvm::Triple::EABI || 5358 Triple.getOS() == llvm::Triple::UnknownOS || 5359 ArchProfile == llvm::ARM::PK_M) { 5360 setABI("aapcs"); 5361 } else if (Triple.isWatchABI()) { 5362 setABI("aapcs16"); 5363 } else { 5364 setABI("apcs-gnu"); 5365 } 5366 } else if (Triple.isOSWindows()) { 5367 // FIXME: this is invalid for WindowsCE 5368 setABI("aapcs"); 5369 } else { 5370 // Select the default based on the platform. 5371 switch (Triple.getEnvironment()) { 5372 case llvm::Triple::Android: 5373 case llvm::Triple::GNUEABI: 5374 case llvm::Triple::GNUEABIHF: 5375 case llvm::Triple::MuslEABI: 5376 case llvm::Triple::MuslEABIHF: 5377 setABI("aapcs-linux"); 5378 break; 5379 case llvm::Triple::EABIHF: 5380 case llvm::Triple::EABI: 5381 setABI("aapcs"); 5382 break; 5383 case llvm::Triple::GNU: 5384 setABI("apcs-gnu"); 5385 break; 5386 default: 5387 if (Triple.getOS() == llvm::Triple::NetBSD) 5388 setABI("apcs-gnu"); 5389 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5390 setABI("aapcs-linux"); 5391 else 5392 setABI("aapcs"); 5393 break; 5394 } 5395 } 5396 5397 // ARM targets default to using the ARM C++ ABI. 5398 TheCXXABI.set(TargetCXXABI::GenericARM); 5399 5400 // ARM has atomics up to 8 bytes 5401 setAtomic(); 5402 5403 // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS) 5404 if (IsAAPCS && (Triple.getEnvironment() != llvm::Triple::Android)) 5405 MaxVectorAlign = 64; 5406 5407 // Do force alignment of members that follow zero length bitfields. If 5408 // the alignment of the zero-length bitfield is greater than the member 5409 // that follows it, `bar', `bar' will be aligned as the type of the 5410 // zero length bitfield. 5411 UseZeroLengthBitfieldAlignment = true; 5412 5413 if (Triple.getOS() == llvm::Triple::Linux || 5414 Triple.getOS() == llvm::Triple::UnknownOS) 5415 this->MCountName = 5416 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5417 } 5418 5419 StringRef getABI() const override { return ABI; } 5420 5421 bool setABI(const std::string &Name) override { 5422 ABI = Name; 5423 5424 // The defaults (above) are for AAPCS, check if we need to change them. 5425 // 5426 // FIXME: We need support for -meabi... we could just mangle it into the 5427 // name. 5428 if (Name == "apcs-gnu" || Name == "aapcs16") { 5429 setABIAPCS(Name == "aapcs16"); 5430 return true; 5431 } 5432 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5433 setABIAAPCS(); 5434 return true; 5435 } 5436 return false; 5437 } 5438 5439 // FIXME: This should be based on Arch attributes, not CPU names. 5440 bool 5441 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5442 StringRef CPU, 5443 const std::vector<std::string> &FeaturesVec) const override { 5444 5445 std::vector<StringRef> TargetFeatures; 5446 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5447 5448 // get default FPU features 5449 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5450 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5451 5452 // get default Extension features 5453 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5454 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5455 5456 for (auto Feature : TargetFeatures) 5457 if (Feature[0] == '+') 5458 Features[Feature.drop_front(1)] = true; 5459 5460 // Enable or disable thumb-mode explicitly per function to enable mixed 5461 // ARM and Thumb code generation. 5462 if (isThumb()) 5463 Features["thumb-mode"] = true; 5464 else 5465 Features["thumb-mode"] = false; 5466 5467 // Convert user-provided arm and thumb GNU target attributes to 5468 // [-|+]thumb-mode target features respectively. 5469 std::vector<std::string> UpdatedFeaturesVec(FeaturesVec); 5470 for (auto &Feature : UpdatedFeaturesVec) { 5471 if (Feature.compare("+arm") == 0) 5472 Feature = "-thumb-mode"; 5473 else if (Feature.compare("+thumb") == 0) 5474 Feature = "+thumb-mode"; 5475 } 5476 5477 return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec); 5478 } 5479 5480 bool handleTargetFeatures(std::vector<std::string> &Features, 5481 DiagnosticsEngine &Diags) override { 5482 FPU = 0; 5483 CRC = 0; 5484 Crypto = 0; 5485 DSP = 0; 5486 Unaligned = 1; 5487 SoftFloat = SoftFloatABI = false; 5488 HWDiv = 0; 5489 5490 // This does not diagnose illegal cases like having both 5491 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5492 uint32_t HW_FP_remove = 0; 5493 for (const auto &Feature : Features) { 5494 if (Feature == "+soft-float") { 5495 SoftFloat = true; 5496 } else if (Feature == "+soft-float-abi") { 5497 SoftFloatABI = true; 5498 } else if (Feature == "+vfp2") { 5499 FPU |= VFP2FPU; 5500 HW_FP |= HW_FP_SP | HW_FP_DP; 5501 } else if (Feature == "+vfp3") { 5502 FPU |= VFP3FPU; 5503 HW_FP |= HW_FP_SP | HW_FP_DP; 5504 } else if (Feature == "+vfp4") { 5505 FPU |= VFP4FPU; 5506 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5507 } else if (Feature == "+fp-armv8") { 5508 FPU |= FPARMV8; 5509 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5510 } else if (Feature == "+neon") { 5511 FPU |= NeonFPU; 5512 HW_FP |= HW_FP_SP | HW_FP_DP; 5513 } else if (Feature == "+hwdiv") { 5514 HWDiv |= HWDivThumb; 5515 } else if (Feature == "+hwdiv-arm") { 5516 HWDiv |= HWDivARM; 5517 } else if (Feature == "+crc") { 5518 CRC = 1; 5519 } else if (Feature == "+crypto") { 5520 Crypto = 1; 5521 } else if (Feature == "+dsp") { 5522 DSP = 1; 5523 } else if (Feature == "+fp-only-sp") { 5524 HW_FP_remove |= HW_FP_DP; 5525 } else if (Feature == "+strict-align") { 5526 Unaligned = 0; 5527 } else if (Feature == "+fp16") { 5528 HW_FP |= HW_FP_HP; 5529 } 5530 } 5531 HW_FP &= ~HW_FP_remove; 5532 5533 switch (ArchVersion) { 5534 case 6: 5535 if (ArchProfile == llvm::ARM::PK_M) 5536 LDREX = 0; 5537 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5538 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5539 else 5540 LDREX = LDREX_W; 5541 break; 5542 case 7: 5543 if (ArchProfile == llvm::ARM::PK_M) 5544 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5545 else 5546 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5547 break; 5548 case 8: 5549 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5550 } 5551 5552 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5553 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5554 return false; 5555 } 5556 5557 if (FPMath == FP_Neon) 5558 Features.push_back("+neonfp"); 5559 else if (FPMath == FP_VFP) 5560 Features.push_back("-neonfp"); 5561 5562 // Remove front-end specific options which the backend handles differently. 5563 auto Feature = 5564 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5565 if (Feature != Features.end()) 5566 Features.erase(Feature); 5567 5568 return true; 5569 } 5570 5571 bool hasFeature(StringRef Feature) const override { 5572 return llvm::StringSwitch<bool>(Feature) 5573 .Case("arm", true) 5574 .Case("aarch32", true) 5575 .Case("softfloat", SoftFloat) 5576 .Case("thumb", isThumb()) 5577 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5578 .Case("vfp", FPU && !SoftFloat) 5579 .Case("hwdiv", HWDiv & HWDivThumb) 5580 .Case("hwdiv-arm", HWDiv & HWDivARM) 5581 .Default(false); 5582 } 5583 5584 bool setCPU(const std::string &Name) override { 5585 if (Name != "generic") 5586 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5587 5588 if (ArchKind == llvm::ARM::AK_INVALID) 5589 return false; 5590 setAtomic(); 5591 CPU = Name; 5592 return true; 5593 } 5594 5595 bool setFPMath(StringRef Name) override; 5596 5597 void getTargetDefines(const LangOptions &Opts, 5598 MacroBuilder &Builder) const override { 5599 // Target identification. 5600 Builder.defineMacro("__arm"); 5601 Builder.defineMacro("__arm__"); 5602 // For bare-metal none-eabi. 5603 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5604 (getTriple().getEnvironment() == llvm::Triple::EABI || 5605 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 5606 Builder.defineMacro("__ELF__"); 5607 5608 5609 // Target properties. 5610 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5611 5612 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5613 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5614 if (getTriple().isWatchABI()) 5615 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5616 5617 if (!CPUAttr.empty()) 5618 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5619 5620 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5621 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5622 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5623 5624 if (ArchVersion >= 8) { 5625 // ACLE 6.5.7 Crypto Extension 5626 if (Crypto) 5627 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5628 // ACLE 6.5.8 CRC32 Extension 5629 if (CRC) 5630 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5631 // ACLE 6.5.10 Numeric Maximum and Minimum 5632 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5633 // ACLE 6.5.9 Directed Rounding 5634 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5635 } 5636 5637 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5638 // is not defined for the M-profile. 5639 // NOTE that the default profile is assumed to be 'A' 5640 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5641 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5642 5643 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5644 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5645 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5646 // v7 and v8 architectures excluding v8-M Baseline. 5647 if (supportsThumb2()) 5648 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5649 else if (supportsThumb()) 5650 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5651 5652 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5653 // instruction set such as ARM or Thumb. 5654 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5655 5656 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5657 5658 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5659 if (!CPUProfile.empty()) 5660 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5661 5662 // ACLE 6.4.3 Unaligned access supported in hardware 5663 if (Unaligned) 5664 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5665 5666 // ACLE 6.4.4 LDREX/STREX 5667 if (LDREX) 5668 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5669 5670 // ACLE 6.4.5 CLZ 5671 if (ArchVersion == 5 || 5672 (ArchVersion == 6 && CPUProfile != "M") || 5673 ArchVersion > 6) 5674 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5675 5676 // ACLE 6.5.1 Hardware Floating Point 5677 if (HW_FP) 5678 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5679 5680 // ACLE predefines. 5681 Builder.defineMacro("__ARM_ACLE", "200"); 5682 5683 // FP16 support (we currently only support IEEE format). 5684 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5685 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5686 5687 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5688 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5689 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5690 5691 // Subtarget options. 5692 5693 // FIXME: It's more complicated than this and we don't really support 5694 // interworking. 5695 // Windows on ARM does not "support" interworking 5696 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5697 Builder.defineMacro("__THUMB_INTERWORK__"); 5698 5699 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5700 // Embedded targets on Darwin follow AAPCS, but not EABI. 5701 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5702 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5703 Builder.defineMacro("__ARM_EABI__"); 5704 Builder.defineMacro("__ARM_PCS", "1"); 5705 } 5706 5707 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5708 ABI == "aapcs16") 5709 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5710 5711 if (SoftFloat) 5712 Builder.defineMacro("__SOFTFP__"); 5713 5714 if (ArchKind == llvm::ARM::AK_XSCALE) 5715 Builder.defineMacro("__XSCALE__"); 5716 5717 if (isThumb()) { 5718 Builder.defineMacro("__THUMBEL__"); 5719 Builder.defineMacro("__thumb__"); 5720 if (supportsThumb2()) 5721 Builder.defineMacro("__thumb2__"); 5722 } 5723 5724 // ACLE 6.4.9 32-bit SIMD instructions 5725 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5726 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5727 5728 // ACLE 6.4.10 Hardware Integer Divide 5729 if (((HWDiv & HWDivThumb) && isThumb()) || 5730 ((HWDiv & HWDivARM) && !isThumb())) { 5731 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5732 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5733 } 5734 5735 // Note, this is always on in gcc, even though it doesn't make sense. 5736 Builder.defineMacro("__APCS_32__"); 5737 5738 if (FPUModeIsVFP((FPUMode) FPU)) { 5739 Builder.defineMacro("__VFP_FP__"); 5740 if (FPU & VFP2FPU) 5741 Builder.defineMacro("__ARM_VFPV2__"); 5742 if (FPU & VFP3FPU) 5743 Builder.defineMacro("__ARM_VFPV3__"); 5744 if (FPU & VFP4FPU) 5745 Builder.defineMacro("__ARM_VFPV4__"); 5746 if (FPU & FPARMV8) 5747 Builder.defineMacro("__ARM_FPV5__"); 5748 } 5749 5750 // This only gets set when Neon instructions are actually available, unlike 5751 // the VFP define, hence the soft float and arch check. This is subtly 5752 // different from gcc, we follow the intent which was that it should be set 5753 // when Neon instructions are actually available. 5754 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5755 Builder.defineMacro("__ARM_NEON", "1"); 5756 Builder.defineMacro("__ARM_NEON__"); 5757 // current AArch32 NEON implementations do not support double-precision 5758 // floating-point even when it is present in VFP. 5759 Builder.defineMacro("__ARM_NEON_FP", 5760 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5761 } 5762 5763 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5764 Opts.ShortWChar ? "2" : "4"); 5765 5766 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5767 Opts.ShortEnums ? "1" : "4"); 5768 5769 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5770 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5771 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5772 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5773 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5774 } 5775 5776 // ACLE 6.4.7 DSP instructions 5777 if (DSP) { 5778 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5779 } 5780 5781 // ACLE 6.4.8 Saturation instructions 5782 bool SAT = false; 5783 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5784 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5785 SAT = true; 5786 } 5787 5788 // ACLE 6.4.6 Q (saturation) flag 5789 if (DSP || SAT) 5790 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5791 5792 if (Opts.UnsafeFPMath) 5793 Builder.defineMacro("__ARM_FP_FAST", "1"); 5794 5795 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5796 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5797 } 5798 5799 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5800 return llvm::makeArrayRef(BuiltinInfo, 5801 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5802 } 5803 bool isCLZForZeroUndef() const override { return false; } 5804 BuiltinVaListKind getBuiltinVaListKind() const override { 5805 return IsAAPCS 5806 ? AAPCSABIBuiltinVaList 5807 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5808 : TargetInfo::VoidPtrBuiltinVaList); 5809 } 5810 ArrayRef<const char *> getGCCRegNames() const override; 5811 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5812 bool validateAsmConstraint(const char *&Name, 5813 TargetInfo::ConstraintInfo &Info) const override { 5814 switch (*Name) { 5815 default: break; 5816 case 'l': // r0-r7 5817 case 'h': // r8-r15 5818 case 't': // VFP Floating point register single precision 5819 case 'w': // VFP Floating point register double precision 5820 Info.setAllowsRegister(); 5821 return true; 5822 case 'I': 5823 case 'J': 5824 case 'K': 5825 case 'L': 5826 case 'M': 5827 // FIXME 5828 return true; 5829 case 'Q': // A memory address that is a single base register. 5830 Info.setAllowsMemory(); 5831 return true; 5832 case 'U': // a memory reference... 5833 switch (Name[1]) { 5834 case 'q': // ...ARMV4 ldrsb 5835 case 'v': // ...VFP load/store (reg+constant offset) 5836 case 'y': // ...iWMMXt load/store 5837 case 't': // address valid for load/store opaque types wider 5838 // than 128-bits 5839 case 'n': // valid address for Neon doubleword vector load/store 5840 case 'm': // valid address for Neon element and structure load/store 5841 case 's': // valid address for non-offset loads/stores of quad-word 5842 // values in four ARM registers 5843 Info.setAllowsMemory(); 5844 Name++; 5845 return true; 5846 } 5847 } 5848 return false; 5849 } 5850 std::string convertConstraint(const char *&Constraint) const override { 5851 std::string R; 5852 switch (*Constraint) { 5853 case 'U': // Two-character constraint; add "^" hint for later parsing. 5854 R = std::string("^") + std::string(Constraint, 2); 5855 Constraint++; 5856 break; 5857 case 'p': // 'p' should be translated to 'r' by default. 5858 R = std::string("r"); 5859 break; 5860 default: 5861 return std::string(1, *Constraint); 5862 } 5863 return R; 5864 } 5865 bool 5866 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5867 std::string &SuggestedModifier) const override { 5868 bool isOutput = (Constraint[0] == '='); 5869 bool isInOut = (Constraint[0] == '+'); 5870 5871 // Strip off constraint modifiers. 5872 while (Constraint[0] == '=' || 5873 Constraint[0] == '+' || 5874 Constraint[0] == '&') 5875 Constraint = Constraint.substr(1); 5876 5877 switch (Constraint[0]) { 5878 default: break; 5879 case 'r': { 5880 switch (Modifier) { 5881 default: 5882 return (isInOut || isOutput || Size <= 64); 5883 case 'q': 5884 // A register of size 32 cannot fit a vector type. 5885 return false; 5886 } 5887 } 5888 } 5889 5890 return true; 5891 } 5892 const char *getClobbers() const override { 5893 // FIXME: Is this really right? 5894 return ""; 5895 } 5896 5897 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5898 switch (CC) { 5899 case CC_AAPCS: 5900 case CC_AAPCS_VFP: 5901 case CC_Swift: 5902 case CC_OpenCLKernel: 5903 return CCCR_OK; 5904 default: 5905 return CCCR_Warning; 5906 } 5907 } 5908 5909 int getEHDataRegisterNumber(unsigned RegNo) const override { 5910 if (RegNo == 0) return 0; 5911 if (RegNo == 1) return 1; 5912 return -1; 5913 } 5914 5915 bool hasSjLjLowering() const override { 5916 return true; 5917 } 5918 }; 5919 5920 bool ARMTargetInfo::setFPMath(StringRef Name) { 5921 if (Name == "neon") { 5922 FPMath = FP_Neon; 5923 return true; 5924 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5925 Name == "vfp4") { 5926 FPMath = FP_VFP; 5927 return true; 5928 } 5929 return false; 5930 } 5931 5932 const char * const ARMTargetInfo::GCCRegNames[] = { 5933 // Integer registers 5934 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5935 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5936 5937 // Float registers 5938 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5939 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5940 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5941 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5942 5943 // Double registers 5944 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5945 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5946 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5947 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5948 5949 // Quad registers 5950 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5951 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5952 }; 5953 5954 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5955 return llvm::makeArrayRef(GCCRegNames); 5956 } 5957 5958 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5959 { { "a1" }, "r0" }, 5960 { { "a2" }, "r1" }, 5961 { { "a3" }, "r2" }, 5962 { { "a4" }, "r3" }, 5963 { { "v1" }, "r4" }, 5964 { { "v2" }, "r5" }, 5965 { { "v3" }, "r6" }, 5966 { { "v4" }, "r7" }, 5967 { { "v5" }, "r8" }, 5968 { { "v6", "rfp" }, "r9" }, 5969 { { "sl" }, "r10" }, 5970 { { "fp" }, "r11" }, 5971 { { "ip" }, "r12" }, 5972 { { "r13" }, "sp" }, 5973 { { "r14" }, "lr" }, 5974 { { "r15" }, "pc" }, 5975 // The S, D and Q registers overlap, but aren't really aliases; we 5976 // don't want to substitute one of these for a different-sized one. 5977 }; 5978 5979 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5980 return llvm::makeArrayRef(GCCRegAliases); 5981 } 5982 5983 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5984 #define BUILTIN(ID, TYPE, ATTRS) \ 5985 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5986 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5987 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5988 #include "clang/Basic/BuiltinsNEON.def" 5989 5990 #define BUILTIN(ID, TYPE, ATTRS) \ 5991 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5992 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5993 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5994 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5995 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5996 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5997 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5998 #include "clang/Basic/BuiltinsARM.def" 5999 }; 6000 6001 class ARMleTargetInfo : public ARMTargetInfo { 6002 public: 6003 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6004 : ARMTargetInfo(Triple, Opts) {} 6005 void getTargetDefines(const LangOptions &Opts, 6006 MacroBuilder &Builder) const override { 6007 Builder.defineMacro("__ARMEL__"); 6008 ARMTargetInfo::getTargetDefines(Opts, Builder); 6009 } 6010 }; 6011 6012 class ARMbeTargetInfo : public ARMTargetInfo { 6013 public: 6014 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6015 : ARMTargetInfo(Triple, Opts) {} 6016 void getTargetDefines(const LangOptions &Opts, 6017 MacroBuilder &Builder) const override { 6018 Builder.defineMacro("__ARMEB__"); 6019 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6020 ARMTargetInfo::getTargetDefines(Opts, Builder); 6021 } 6022 }; 6023 6024 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 6025 const llvm::Triple Triple; 6026 public: 6027 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6028 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 6029 WCharType = UnsignedShort; 6030 SizeType = UnsignedInt; 6031 } 6032 void getVisualStudioDefines(const LangOptions &Opts, 6033 MacroBuilder &Builder) const { 6034 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 6035 6036 // FIXME: this is invalid for WindowsCE 6037 Builder.defineMacro("_M_ARM_NT", "1"); 6038 Builder.defineMacro("_M_ARMT", "_M_ARM"); 6039 Builder.defineMacro("_M_THUMB", "_M_ARM"); 6040 6041 assert((Triple.getArch() == llvm::Triple::arm || 6042 Triple.getArch() == llvm::Triple::thumb) && 6043 "invalid architecture for Windows ARM target info"); 6044 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 6045 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 6046 6047 // TODO map the complete set of values 6048 // 31: VFPv3 40: VFPv4 6049 Builder.defineMacro("_M_ARM_FP", "31"); 6050 } 6051 BuiltinVaListKind getBuiltinVaListKind() const override { 6052 return TargetInfo::CharPtrBuiltinVaList; 6053 } 6054 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6055 switch (CC) { 6056 case CC_X86StdCall: 6057 case CC_X86ThisCall: 6058 case CC_X86FastCall: 6059 case CC_X86VectorCall: 6060 return CCCR_Ignore; 6061 case CC_C: 6062 case CC_OpenCLKernel: 6063 return CCCR_OK; 6064 default: 6065 return CCCR_Warning; 6066 } 6067 } 6068 }; 6069 6070 // Windows ARM + Itanium C++ ABI Target 6071 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 6072 public: 6073 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 6074 const TargetOptions &Opts) 6075 : WindowsARMTargetInfo(Triple, Opts) { 6076 TheCXXABI.set(TargetCXXABI::GenericARM); 6077 } 6078 6079 void getTargetDefines(const LangOptions &Opts, 6080 MacroBuilder &Builder) const override { 6081 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6082 6083 if (Opts.MSVCCompat) 6084 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6085 } 6086 }; 6087 6088 // Windows ARM, MS (C++) ABI 6089 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 6090 public: 6091 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 6092 const TargetOptions &Opts) 6093 : WindowsARMTargetInfo(Triple, Opts) { 6094 TheCXXABI.set(TargetCXXABI::Microsoft); 6095 } 6096 6097 void getTargetDefines(const LangOptions &Opts, 6098 MacroBuilder &Builder) const override { 6099 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6100 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6101 } 6102 }; 6103 6104 // ARM MinGW target 6105 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 6106 public: 6107 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6108 : WindowsARMTargetInfo(Triple, Opts) { 6109 TheCXXABI.set(TargetCXXABI::GenericARM); 6110 } 6111 6112 void getTargetDefines(const LangOptions &Opts, 6113 MacroBuilder &Builder) const override { 6114 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6115 DefineStd(Builder, "WIN32", Opts); 6116 DefineStd(Builder, "WINNT", Opts); 6117 Builder.defineMacro("_ARM_"); 6118 addMinGWDefines(Opts, Builder); 6119 } 6120 }; 6121 6122 // ARM Cygwin target 6123 class CygwinARMTargetInfo : public ARMleTargetInfo { 6124 public: 6125 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6126 : ARMleTargetInfo(Triple, Opts) { 6127 TLSSupported = false; 6128 WCharType = UnsignedShort; 6129 DoubleAlign = LongLongAlign = 64; 6130 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 6131 } 6132 void getTargetDefines(const LangOptions &Opts, 6133 MacroBuilder &Builder) const override { 6134 ARMleTargetInfo::getTargetDefines(Opts, Builder); 6135 Builder.defineMacro("_ARM_"); 6136 Builder.defineMacro("__CYGWIN__"); 6137 Builder.defineMacro("__CYGWIN32__"); 6138 DefineStd(Builder, "unix", Opts); 6139 if (Opts.CPlusPlus) 6140 Builder.defineMacro("_GNU_SOURCE"); 6141 } 6142 }; 6143 6144 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 6145 protected: 6146 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6147 MacroBuilder &Builder) const override { 6148 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6149 } 6150 6151 public: 6152 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6153 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 6154 HasAlignMac68kSupport = true; 6155 // iOS always has 64-bit atomic instructions. 6156 // FIXME: This should be based off of the target features in 6157 // ARMleTargetInfo. 6158 MaxAtomicInlineWidth = 64; 6159 6160 if (Triple.isWatchABI()) { 6161 // Darwin on iOS uses a variant of the ARM C++ ABI. 6162 TheCXXABI.set(TargetCXXABI::WatchOS); 6163 6164 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 6165 // size_t is long, it's a bit weird for it to be int. 6166 PtrDiffType = SignedLong; 6167 6168 // BOOL should be a real boolean on the new ABI 6169 UseSignedCharForObjCBool = false; 6170 } else 6171 TheCXXABI.set(TargetCXXABI::iOS); 6172 } 6173 }; 6174 6175 class AArch64TargetInfo : public TargetInfo { 6176 virtual void setDataLayout() = 0; 6177 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6178 static const char *const GCCRegNames[]; 6179 6180 enum FPUModeEnum { 6181 FPUMode, 6182 NeonMode 6183 }; 6184 6185 unsigned FPU; 6186 unsigned CRC; 6187 unsigned Crypto; 6188 unsigned Unaligned; 6189 unsigned V8_1A; 6190 unsigned V8_2A; 6191 unsigned HasFullFP16; 6192 6193 static const Builtin::Info BuiltinInfo[]; 6194 6195 std::string ABI; 6196 6197 public: 6198 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6199 : TargetInfo(Triple), ABI("aapcs") { 6200 if (getTriple().getOS() == llvm::Triple::NetBSD || 6201 getTriple().getOS() == llvm::Triple::OpenBSD) { 6202 WCharType = SignedInt; 6203 6204 // NetBSD apparently prefers consistency across ARM targets to consistency 6205 // across 64-bit targets. 6206 Int64Type = SignedLongLong; 6207 IntMaxType = SignedLongLong; 6208 } else { 6209 WCharType = UnsignedInt; 6210 Int64Type = SignedLong; 6211 IntMaxType = SignedLong; 6212 } 6213 6214 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6215 MaxVectorAlign = 128; 6216 MaxAtomicInlineWidth = 128; 6217 MaxAtomicPromoteWidth = 128; 6218 6219 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 6220 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6221 6222 // {} in inline assembly are neon specifiers, not assembly variant 6223 // specifiers. 6224 NoAsmVariants = true; 6225 6226 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 6227 // contributes to the alignment of the containing aggregate in the same way 6228 // a plain (non bit-field) member of that type would, without exception for 6229 // zero-sized or anonymous bit-fields." 6230 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 6231 UseZeroLengthBitfieldAlignment = true; 6232 6233 // AArch64 targets default to using the ARM C++ ABI. 6234 TheCXXABI.set(TargetCXXABI::GenericAArch64); 6235 6236 if (Triple.getOS() == llvm::Triple::Linux) 6237 this->MCountName = "\01_mcount"; 6238 else if (Triple.getOS() == llvm::Triple::UnknownOS) 6239 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 6240 } 6241 6242 StringRef getABI() const override { return ABI; } 6243 bool setABI(const std::string &Name) override { 6244 if (Name != "aapcs" && Name != "darwinpcs") 6245 return false; 6246 6247 ABI = Name; 6248 return true; 6249 } 6250 6251 bool setCPU(const std::string &Name) override { 6252 return Name == "generic" || 6253 llvm::AArch64::parseCPUArch(Name) != 6254 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6255 } 6256 6257 void getTargetDefines(const LangOptions &Opts, 6258 MacroBuilder &Builder) const override { 6259 // Target identification. 6260 Builder.defineMacro("__aarch64__"); 6261 // For bare-metal none-eabi. 6262 if (getTriple().getOS() == llvm::Triple::UnknownOS && 6263 (getTriple().getEnvironment() == llvm::Triple::EABI || 6264 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 6265 Builder.defineMacro("__ELF__"); 6266 6267 // Target properties. 6268 Builder.defineMacro("_LP64"); 6269 Builder.defineMacro("__LP64__"); 6270 6271 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6272 Builder.defineMacro("__ARM_ACLE", "200"); 6273 Builder.defineMacro("__ARM_ARCH", "8"); 6274 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6275 6276 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6277 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6278 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6279 6280 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6281 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6282 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6283 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6284 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6285 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6286 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6287 6288 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6289 6290 // 0xe implies support for half, single and double precision operations. 6291 Builder.defineMacro("__ARM_FP", "0xE"); 6292 6293 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6294 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6295 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6296 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6297 6298 if (Opts.UnsafeFPMath) 6299 Builder.defineMacro("__ARM_FP_FAST", "1"); 6300 6301 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6302 6303 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6304 Opts.ShortEnums ? "1" : "4"); 6305 6306 if (FPU == NeonMode) { 6307 Builder.defineMacro("__ARM_NEON", "1"); 6308 // 64-bit NEON supports half, single and double precision operations. 6309 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6310 } 6311 6312 if (CRC) 6313 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6314 6315 if (Crypto) 6316 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6317 6318 if (Unaligned) 6319 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6320 6321 if (V8_1A) 6322 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6323 if (V8_2A && FPU == NeonMode && HasFullFP16) 6324 Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1"); 6325 6326 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6327 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6328 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6329 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6330 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6331 } 6332 6333 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6334 return llvm::makeArrayRef(BuiltinInfo, 6335 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6336 } 6337 6338 bool hasFeature(StringRef Feature) const override { 6339 return Feature == "aarch64" || 6340 Feature == "arm64" || 6341 Feature == "arm" || 6342 (Feature == "neon" && FPU == NeonMode); 6343 } 6344 6345 bool handleTargetFeatures(std::vector<std::string> &Features, 6346 DiagnosticsEngine &Diags) override { 6347 FPU = FPUMode; 6348 CRC = 0; 6349 Crypto = 0; 6350 Unaligned = 1; 6351 V8_1A = 0; 6352 V8_2A = 0; 6353 HasFullFP16 = 0; 6354 6355 for (const auto &Feature : Features) { 6356 if (Feature == "+neon") 6357 FPU = NeonMode; 6358 if (Feature == "+crc") 6359 CRC = 1; 6360 if (Feature == "+crypto") 6361 Crypto = 1; 6362 if (Feature == "+strict-align") 6363 Unaligned = 0; 6364 if (Feature == "+v8.1a") 6365 V8_1A = 1; 6366 if (Feature == "+v8.2a") 6367 V8_2A = 1; 6368 if (Feature == "+fullfp16") 6369 HasFullFP16 = 1; 6370 } 6371 6372 setDataLayout(); 6373 6374 return true; 6375 } 6376 6377 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6378 switch (CC) { 6379 case CC_C: 6380 case CC_Swift: 6381 case CC_PreserveMost: 6382 case CC_PreserveAll: 6383 case CC_OpenCLKernel: 6384 return CCCR_OK; 6385 default: 6386 return CCCR_Warning; 6387 } 6388 } 6389 6390 bool isCLZForZeroUndef() const override { return false; } 6391 6392 BuiltinVaListKind getBuiltinVaListKind() const override { 6393 return TargetInfo::AArch64ABIBuiltinVaList; 6394 } 6395 6396 ArrayRef<const char *> getGCCRegNames() const override; 6397 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6398 6399 bool validateAsmConstraint(const char *&Name, 6400 TargetInfo::ConstraintInfo &Info) const override { 6401 switch (*Name) { 6402 default: 6403 return false; 6404 case 'w': // Floating point and SIMD registers (V0-V31) 6405 Info.setAllowsRegister(); 6406 return true; 6407 case 'I': // Constant that can be used with an ADD instruction 6408 case 'J': // Constant that can be used with a SUB instruction 6409 case 'K': // Constant that can be used with a 32-bit logical instruction 6410 case 'L': // Constant that can be used with a 64-bit logical instruction 6411 case 'M': // Constant that can be used as a 32-bit MOV immediate 6412 case 'N': // Constant that can be used as a 64-bit MOV immediate 6413 case 'Y': // Floating point constant zero 6414 case 'Z': // Integer constant zero 6415 return true; 6416 case 'Q': // A memory reference with base register and no offset 6417 Info.setAllowsMemory(); 6418 return true; 6419 case 'S': // A symbolic address 6420 Info.setAllowsRegister(); 6421 return true; 6422 case 'U': 6423 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6424 // Utf: A memory address suitable for ldp/stp in TF mode. 6425 // Usa: An absolute symbolic address. 6426 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6427 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6428 case 'z': // Zero register, wzr or xzr 6429 Info.setAllowsRegister(); 6430 return true; 6431 case 'x': // Floating point and SIMD registers (V0-V15) 6432 Info.setAllowsRegister(); 6433 return true; 6434 } 6435 return false; 6436 } 6437 6438 bool 6439 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6440 std::string &SuggestedModifier) const override { 6441 // Strip off constraint modifiers. 6442 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6443 Constraint = Constraint.substr(1); 6444 6445 switch (Constraint[0]) { 6446 default: 6447 return true; 6448 case 'z': 6449 case 'r': { 6450 switch (Modifier) { 6451 case 'x': 6452 case 'w': 6453 // For now assume that the person knows what they're 6454 // doing with the modifier. 6455 return true; 6456 default: 6457 // By default an 'r' constraint will be in the 'x' 6458 // registers. 6459 if (Size == 64) 6460 return true; 6461 6462 SuggestedModifier = "w"; 6463 return false; 6464 } 6465 } 6466 } 6467 } 6468 6469 const char *getClobbers() const override { return ""; } 6470 6471 int getEHDataRegisterNumber(unsigned RegNo) const override { 6472 if (RegNo == 0) 6473 return 0; 6474 if (RegNo == 1) 6475 return 1; 6476 return -1; 6477 } 6478 }; 6479 6480 const char *const AArch64TargetInfo::GCCRegNames[] = { 6481 // 32-bit Integer registers 6482 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6483 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6484 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6485 6486 // 64-bit Integer registers 6487 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6488 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6489 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6490 6491 // 32-bit floating point regsisters 6492 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6493 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6494 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6495 6496 // 64-bit floating point regsisters 6497 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6498 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6499 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6500 6501 // Vector registers 6502 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6503 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6504 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6505 }; 6506 6507 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6508 return llvm::makeArrayRef(GCCRegNames); 6509 } 6510 6511 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6512 { { "w31" }, "wsp" }, 6513 { { "x29" }, "fp" }, 6514 { { "x30" }, "lr" }, 6515 { { "x31" }, "sp" }, 6516 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6517 // don't want to substitute one of these for a different-sized one. 6518 }; 6519 6520 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6521 return llvm::makeArrayRef(GCCRegAliases); 6522 } 6523 6524 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6525 #define BUILTIN(ID, TYPE, ATTRS) \ 6526 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6527 #include "clang/Basic/BuiltinsNEON.def" 6528 6529 #define BUILTIN(ID, TYPE, ATTRS) \ 6530 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6531 #include "clang/Basic/BuiltinsAArch64.def" 6532 }; 6533 6534 class AArch64leTargetInfo : public AArch64TargetInfo { 6535 void setDataLayout() override { 6536 if (getTriple().isOSBinFormatMachO()) 6537 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6538 else 6539 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6540 } 6541 6542 public: 6543 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6544 : AArch64TargetInfo(Triple, Opts) { 6545 } 6546 void getTargetDefines(const LangOptions &Opts, 6547 MacroBuilder &Builder) const override { 6548 Builder.defineMacro("__AARCH64EL__"); 6549 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6550 } 6551 }; 6552 6553 class AArch64beTargetInfo : public AArch64TargetInfo { 6554 void setDataLayout() override { 6555 assert(!getTriple().isOSBinFormatMachO()); 6556 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6557 } 6558 6559 public: 6560 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6561 : AArch64TargetInfo(Triple, Opts) {} 6562 void getTargetDefines(const LangOptions &Opts, 6563 MacroBuilder &Builder) const override { 6564 Builder.defineMacro("__AARCH64EB__"); 6565 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6566 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6567 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6568 } 6569 }; 6570 6571 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6572 protected: 6573 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6574 MacroBuilder &Builder) const override { 6575 Builder.defineMacro("__AARCH64_SIMD__"); 6576 Builder.defineMacro("__ARM64_ARCH_8__"); 6577 Builder.defineMacro("__ARM_NEON__"); 6578 Builder.defineMacro("__LITTLE_ENDIAN__"); 6579 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6580 Builder.defineMacro("__arm64", "1"); 6581 Builder.defineMacro("__arm64__", "1"); 6582 6583 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6584 } 6585 6586 public: 6587 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6588 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6589 Int64Type = SignedLongLong; 6590 WCharType = SignedInt; 6591 UseSignedCharForObjCBool = false; 6592 6593 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6594 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6595 6596 TheCXXABI.set(TargetCXXABI::iOS64); 6597 } 6598 6599 BuiltinVaListKind getBuiltinVaListKind() const override { 6600 return TargetInfo::CharPtrBuiltinVaList; 6601 } 6602 }; 6603 6604 // Hexagon abstract base class 6605 class HexagonTargetInfo : public TargetInfo { 6606 static const Builtin::Info BuiltinInfo[]; 6607 static const char * const GCCRegNames[]; 6608 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6609 std::string CPU; 6610 bool HasHVX, HasHVXDouble; 6611 bool UseLongCalls; 6612 6613 public: 6614 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6615 : TargetInfo(Triple) { 6616 // Specify the vector alignment explicitly. For v512x1, the calculated 6617 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6618 // the required minimum of 64 bytes. 6619 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6620 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6621 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6622 SizeType = UnsignedInt; 6623 PtrDiffType = SignedInt; 6624 IntPtrType = SignedInt; 6625 6626 // {} in inline assembly are packet specifiers, not assembly variant 6627 // specifiers. 6628 NoAsmVariants = true; 6629 6630 LargeArrayMinWidth = 64; 6631 LargeArrayAlign = 64; 6632 UseBitFieldTypeAlignment = true; 6633 ZeroLengthBitfieldBoundary = 32; 6634 HasHVX = HasHVXDouble = false; 6635 UseLongCalls = false; 6636 } 6637 6638 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6639 return llvm::makeArrayRef(BuiltinInfo, 6640 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6641 } 6642 6643 bool validateAsmConstraint(const char *&Name, 6644 TargetInfo::ConstraintInfo &Info) const override { 6645 switch (*Name) { 6646 case 'v': 6647 case 'q': 6648 if (HasHVX) { 6649 Info.setAllowsRegister(); 6650 return true; 6651 } 6652 break; 6653 case 's': 6654 // Relocatable constant. 6655 return true; 6656 } 6657 return false; 6658 } 6659 6660 void getTargetDefines(const LangOptions &Opts, 6661 MacroBuilder &Builder) const override; 6662 6663 bool isCLZForZeroUndef() const override { return false; } 6664 6665 bool hasFeature(StringRef Feature) const override { 6666 return llvm::StringSwitch<bool>(Feature) 6667 .Case("hexagon", true) 6668 .Case("hvx", HasHVX) 6669 .Case("hvx-double", HasHVXDouble) 6670 .Case("long-calls", UseLongCalls) 6671 .Default(false); 6672 } 6673 6674 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6675 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6676 const override; 6677 6678 bool handleTargetFeatures(std::vector<std::string> &Features, 6679 DiagnosticsEngine &Diags) override; 6680 6681 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6682 bool Enabled) const override; 6683 6684 BuiltinVaListKind getBuiltinVaListKind() const override { 6685 return TargetInfo::CharPtrBuiltinVaList; 6686 } 6687 ArrayRef<const char *> getGCCRegNames() const override; 6688 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6689 const char *getClobbers() const override { 6690 return ""; 6691 } 6692 6693 static const char *getHexagonCPUSuffix(StringRef Name) { 6694 return llvm::StringSwitch<const char*>(Name) 6695 .Case("hexagonv4", "4") 6696 .Case("hexagonv5", "5") 6697 .Case("hexagonv55", "55") 6698 .Case("hexagonv60", "60") 6699 .Case("hexagonv62", "62") 6700 .Default(nullptr); 6701 } 6702 6703 bool setCPU(const std::string &Name) override { 6704 if (!getHexagonCPUSuffix(Name)) 6705 return false; 6706 CPU = Name; 6707 return true; 6708 } 6709 6710 int getEHDataRegisterNumber(unsigned RegNo) const override { 6711 return RegNo < 2 ? RegNo : -1; 6712 } 6713 }; 6714 6715 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6716 MacroBuilder &Builder) const { 6717 Builder.defineMacro("__qdsp6__", "1"); 6718 Builder.defineMacro("__hexagon__", "1"); 6719 6720 if (CPU == "hexagonv4") { 6721 Builder.defineMacro("__HEXAGON_V4__"); 6722 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6723 if (Opts.HexagonQdsp6Compat) { 6724 Builder.defineMacro("__QDSP6_V4__"); 6725 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6726 } 6727 } else if (CPU == "hexagonv5") { 6728 Builder.defineMacro("__HEXAGON_V5__"); 6729 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6730 if(Opts.HexagonQdsp6Compat) { 6731 Builder.defineMacro("__QDSP6_V5__"); 6732 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6733 } 6734 } else if (CPU == "hexagonv55") { 6735 Builder.defineMacro("__HEXAGON_V55__"); 6736 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6737 Builder.defineMacro("__QDSP6_V55__"); 6738 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6739 } else if (CPU == "hexagonv60") { 6740 Builder.defineMacro("__HEXAGON_V60__"); 6741 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6742 Builder.defineMacro("__QDSP6_V60__"); 6743 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6744 } else if (CPU == "hexagonv62") { 6745 Builder.defineMacro("__HEXAGON_V62__"); 6746 Builder.defineMacro("__HEXAGON_ARCH__", "62"); 6747 } 6748 6749 if (hasFeature("hvx")) { 6750 Builder.defineMacro("__HVX__"); 6751 if (hasFeature("hvx-double")) 6752 Builder.defineMacro("__HVXDBL__"); 6753 } 6754 } 6755 6756 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6757 DiagnosticsEngine &Diags, StringRef CPU, 6758 const std::vector<std::string> &FeaturesVec) const { 6759 // Default for v60: -hvx, -hvx-double. 6760 Features["hvx"] = false; 6761 Features["hvx-double"] = false; 6762 Features["long-calls"] = false; 6763 6764 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6765 } 6766 6767 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6768 DiagnosticsEngine &Diags) { 6769 for (auto &F : Features) { 6770 if (F == "+hvx") 6771 HasHVX = true; 6772 else if (F == "-hvx") 6773 HasHVX = HasHVXDouble = false; 6774 else if (F == "+hvx-double") 6775 HasHVX = HasHVXDouble = true; 6776 else if (F == "-hvx-double") 6777 HasHVXDouble = false; 6778 6779 if (F == "+long-calls") 6780 UseLongCalls = true; 6781 else if (F == "-long-calls") 6782 UseLongCalls = false; 6783 } 6784 return true; 6785 } 6786 6787 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6788 StringRef Name, bool Enabled) const { 6789 if (Enabled) { 6790 if (Name == "hvx-double") 6791 Features["hvx"] = true; 6792 } else { 6793 if (Name == "hvx") 6794 Features["hvx-double"] = false; 6795 } 6796 Features[Name] = Enabled; 6797 } 6798 6799 const char *const HexagonTargetInfo::GCCRegNames[] = { 6800 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6801 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6802 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6803 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6804 "p0", "p1", "p2", "p3", 6805 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6806 }; 6807 6808 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6809 return llvm::makeArrayRef(GCCRegNames); 6810 } 6811 6812 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6813 { { "sp" }, "r29" }, 6814 { { "fp" }, "r30" }, 6815 { { "lr" }, "r31" }, 6816 }; 6817 6818 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6819 return llvm::makeArrayRef(GCCRegAliases); 6820 } 6821 6822 6823 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6824 #define BUILTIN(ID, TYPE, ATTRS) \ 6825 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6826 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6827 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6828 #include "clang/Basic/BuiltinsHexagon.def" 6829 }; 6830 6831 class LanaiTargetInfo : public TargetInfo { 6832 // Class for Lanai (32-bit). 6833 // The CPU profiles supported by the Lanai backend 6834 enum CPUKind { 6835 CK_NONE, 6836 CK_V11, 6837 } CPU; 6838 6839 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6840 static const char *const GCCRegNames[]; 6841 6842 public: 6843 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6844 : TargetInfo(Triple) { 6845 // Description string has to be kept in sync with backend. 6846 resetDataLayout("E" // Big endian 6847 "-m:e" // ELF name manging 6848 "-p:32:32" // 32 bit pointers, 32 bit aligned 6849 "-i64:64" // 64 bit integers, 64 bit aligned 6850 "-a:0:32" // 32 bit alignment of objects of aggregate type 6851 "-n32" // 32 bit native integer width 6852 "-S64" // 64 bit natural stack alignment 6853 ); 6854 6855 // Setting RegParmMax equal to what mregparm was set to in the old 6856 // toolchain 6857 RegParmMax = 4; 6858 6859 // Set the default CPU to V11 6860 CPU = CK_V11; 6861 6862 // Temporary approach to make everything at least word-aligned and allow for 6863 // safely casting between pointers with different alignment requirements. 6864 // TODO: Remove this when there are no more cast align warnings on the 6865 // firmware. 6866 MinGlobalAlign = 32; 6867 } 6868 6869 void getTargetDefines(const LangOptions &Opts, 6870 MacroBuilder &Builder) const override { 6871 // Define __lanai__ when building for target lanai. 6872 Builder.defineMacro("__lanai__"); 6873 6874 // Set define for the CPU specified. 6875 switch (CPU) { 6876 case CK_V11: 6877 Builder.defineMacro("__LANAI_V11__"); 6878 break; 6879 case CK_NONE: 6880 llvm_unreachable("Unhandled target CPU"); 6881 } 6882 } 6883 6884 bool setCPU(const std::string &Name) override { 6885 CPU = llvm::StringSwitch<CPUKind>(Name) 6886 .Case("v11", CK_V11) 6887 .Default(CK_NONE); 6888 6889 return CPU != CK_NONE; 6890 } 6891 6892 bool hasFeature(StringRef Feature) const override { 6893 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6894 } 6895 6896 ArrayRef<const char *> getGCCRegNames() const override; 6897 6898 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6899 6900 BuiltinVaListKind getBuiltinVaListKind() const override { 6901 return TargetInfo::VoidPtrBuiltinVaList; 6902 } 6903 6904 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6905 6906 bool validateAsmConstraint(const char *&Name, 6907 TargetInfo::ConstraintInfo &info) const override { 6908 return false; 6909 } 6910 6911 const char *getClobbers() const override { return ""; } 6912 }; 6913 6914 const char *const LanaiTargetInfo::GCCRegNames[] = { 6915 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6916 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6917 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6918 6919 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6920 return llvm::makeArrayRef(GCCRegNames); 6921 } 6922 6923 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6924 {{"pc"}, "r2"}, 6925 {{"sp"}, "r4"}, 6926 {{"fp"}, "r5"}, 6927 {{"rv"}, "r8"}, 6928 {{"rr1"}, "r10"}, 6929 {{"rr2"}, "r11"}, 6930 {{"rca"}, "r15"}, 6931 }; 6932 6933 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6934 return llvm::makeArrayRef(GCCRegAliases); 6935 } 6936 6937 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6938 class SparcTargetInfo : public TargetInfo { 6939 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6940 static const char * const GCCRegNames[]; 6941 bool SoftFloat; 6942 public: 6943 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6944 : TargetInfo(Triple), SoftFloat(false) {} 6945 6946 int getEHDataRegisterNumber(unsigned RegNo) const override { 6947 if (RegNo == 0) return 24; 6948 if (RegNo == 1) return 25; 6949 return -1; 6950 } 6951 6952 bool handleTargetFeatures(std::vector<std::string> &Features, 6953 DiagnosticsEngine &Diags) override { 6954 // Check if software floating point is enabled 6955 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6956 if (Feature != Features.end()) { 6957 SoftFloat = true; 6958 } 6959 return true; 6960 } 6961 void getTargetDefines(const LangOptions &Opts, 6962 MacroBuilder &Builder) const override { 6963 DefineStd(Builder, "sparc", Opts); 6964 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6965 6966 if (SoftFloat) 6967 Builder.defineMacro("SOFT_FLOAT", "1"); 6968 } 6969 6970 bool hasFeature(StringRef Feature) const override { 6971 return llvm::StringSwitch<bool>(Feature) 6972 .Case("softfloat", SoftFloat) 6973 .Case("sparc", true) 6974 .Default(false); 6975 } 6976 6977 bool hasSjLjLowering() const override { 6978 return true; 6979 } 6980 6981 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6982 // FIXME: Implement! 6983 return None; 6984 } 6985 BuiltinVaListKind getBuiltinVaListKind() const override { 6986 return TargetInfo::VoidPtrBuiltinVaList; 6987 } 6988 ArrayRef<const char *> getGCCRegNames() const override; 6989 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6990 bool validateAsmConstraint(const char *&Name, 6991 TargetInfo::ConstraintInfo &info) const override { 6992 // FIXME: Implement! 6993 switch (*Name) { 6994 case 'I': // Signed 13-bit constant 6995 case 'J': // Zero 6996 case 'K': // 32-bit constant with the low 12 bits clear 6997 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6998 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6999 case 'N': // Same as 'K' but zext (required for SIMode) 7000 case 'O': // The constant 4096 7001 return true; 7002 7003 case 'f': 7004 case 'e': 7005 info.setAllowsRegister(); 7006 return true; 7007 } 7008 return false; 7009 } 7010 const char *getClobbers() const override { 7011 // FIXME: Implement! 7012 return ""; 7013 } 7014 7015 // No Sparc V7 for now, the backend doesn't support it anyway. 7016 enum CPUKind { 7017 CK_GENERIC, 7018 CK_V8, 7019 CK_SUPERSPARC, 7020 CK_SPARCLITE, 7021 CK_F934, 7022 CK_HYPERSPARC, 7023 CK_SPARCLITE86X, 7024 CK_SPARCLET, 7025 CK_TSC701, 7026 CK_V9, 7027 CK_ULTRASPARC, 7028 CK_ULTRASPARC3, 7029 CK_NIAGARA, 7030 CK_NIAGARA2, 7031 CK_NIAGARA3, 7032 CK_NIAGARA4, 7033 CK_MYRIAD2100, 7034 CK_MYRIAD2150, 7035 CK_MYRIAD2450, 7036 CK_LEON2, 7037 CK_LEON2_AT697E, 7038 CK_LEON2_AT697F, 7039 CK_LEON3, 7040 CK_LEON3_UT699, 7041 CK_LEON3_GR712RC, 7042 CK_LEON4, 7043 CK_LEON4_GR740 7044 } CPU = CK_GENERIC; 7045 7046 enum CPUGeneration { 7047 CG_V8, 7048 CG_V9, 7049 }; 7050 7051 CPUGeneration getCPUGeneration(CPUKind Kind) const { 7052 switch (Kind) { 7053 case CK_GENERIC: 7054 case CK_V8: 7055 case CK_SUPERSPARC: 7056 case CK_SPARCLITE: 7057 case CK_F934: 7058 case CK_HYPERSPARC: 7059 case CK_SPARCLITE86X: 7060 case CK_SPARCLET: 7061 case CK_TSC701: 7062 case CK_MYRIAD2100: 7063 case CK_MYRIAD2150: 7064 case CK_MYRIAD2450: 7065 case CK_LEON2: 7066 case CK_LEON2_AT697E: 7067 case CK_LEON2_AT697F: 7068 case CK_LEON3: 7069 case CK_LEON3_UT699: 7070 case CK_LEON3_GR712RC: 7071 case CK_LEON4: 7072 case CK_LEON4_GR740: 7073 return CG_V8; 7074 case CK_V9: 7075 case CK_ULTRASPARC: 7076 case CK_ULTRASPARC3: 7077 case CK_NIAGARA: 7078 case CK_NIAGARA2: 7079 case CK_NIAGARA3: 7080 case CK_NIAGARA4: 7081 return CG_V9; 7082 } 7083 llvm_unreachable("Unexpected CPU kind"); 7084 } 7085 7086 CPUKind getCPUKind(StringRef Name) const { 7087 return llvm::StringSwitch<CPUKind>(Name) 7088 .Case("v8", CK_V8) 7089 .Case("supersparc", CK_SUPERSPARC) 7090 .Case("sparclite", CK_SPARCLITE) 7091 .Case("f934", CK_F934) 7092 .Case("hypersparc", CK_HYPERSPARC) 7093 .Case("sparclite86x", CK_SPARCLITE86X) 7094 .Case("sparclet", CK_SPARCLET) 7095 .Case("tsc701", CK_TSC701) 7096 .Case("v9", CK_V9) 7097 .Case("ultrasparc", CK_ULTRASPARC) 7098 .Case("ultrasparc3", CK_ULTRASPARC3) 7099 .Case("niagara", CK_NIAGARA) 7100 .Case("niagara2", CK_NIAGARA2) 7101 .Case("niagara3", CK_NIAGARA3) 7102 .Case("niagara4", CK_NIAGARA4) 7103 .Case("ma2100", CK_MYRIAD2100) 7104 .Case("ma2150", CK_MYRIAD2150) 7105 .Case("ma2450", CK_MYRIAD2450) 7106 // FIXME: the myriad2[.n] spellings are obsolete, 7107 // but a grace period is needed to allow updating dependent builds. 7108 .Case("myriad2", CK_MYRIAD2100) 7109 .Case("myriad2.1", CK_MYRIAD2100) 7110 .Case("myriad2.2", CK_MYRIAD2150) 7111 .Case("leon2", CK_LEON2) 7112 .Case("at697e", CK_LEON2_AT697E) 7113 .Case("at697f", CK_LEON2_AT697F) 7114 .Case("leon3", CK_LEON3) 7115 .Case("ut699", CK_LEON3_UT699) 7116 .Case("gr712rc", CK_LEON3_GR712RC) 7117 .Case("leon4", CK_LEON4) 7118 .Case("gr740", CK_LEON4_GR740) 7119 .Default(CK_GENERIC); 7120 } 7121 7122 bool setCPU(const std::string &Name) override { 7123 CPU = getCPUKind(Name); 7124 return CPU != CK_GENERIC; 7125 } 7126 }; 7127 7128 const char * const SparcTargetInfo::GCCRegNames[] = { 7129 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7130 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7131 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 7132 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 7133 }; 7134 7135 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 7136 return llvm::makeArrayRef(GCCRegNames); 7137 } 7138 7139 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 7140 { { "g0" }, "r0" }, 7141 { { "g1" }, "r1" }, 7142 { { "g2" }, "r2" }, 7143 { { "g3" }, "r3" }, 7144 { { "g4" }, "r4" }, 7145 { { "g5" }, "r5" }, 7146 { { "g6" }, "r6" }, 7147 { { "g7" }, "r7" }, 7148 { { "o0" }, "r8" }, 7149 { { "o1" }, "r9" }, 7150 { { "o2" }, "r10" }, 7151 { { "o3" }, "r11" }, 7152 { { "o4" }, "r12" }, 7153 { { "o5" }, "r13" }, 7154 { { "o6", "sp" }, "r14" }, 7155 { { "o7" }, "r15" }, 7156 { { "l0" }, "r16" }, 7157 { { "l1" }, "r17" }, 7158 { { "l2" }, "r18" }, 7159 { { "l3" }, "r19" }, 7160 { { "l4" }, "r20" }, 7161 { { "l5" }, "r21" }, 7162 { { "l6" }, "r22" }, 7163 { { "l7" }, "r23" }, 7164 { { "i0" }, "r24" }, 7165 { { "i1" }, "r25" }, 7166 { { "i2" }, "r26" }, 7167 { { "i3" }, "r27" }, 7168 { { "i4" }, "r28" }, 7169 { { "i5" }, "r29" }, 7170 { { "i6", "fp" }, "r30" }, 7171 { { "i7" }, "r31" }, 7172 }; 7173 7174 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 7175 return llvm::makeArrayRef(GCCRegAliases); 7176 } 7177 7178 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 7179 class SparcV8TargetInfo : public SparcTargetInfo { 7180 public: 7181 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7182 : SparcTargetInfo(Triple, Opts) { 7183 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7184 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 7185 switch (getTriple().getOS()) { 7186 default: 7187 SizeType = UnsignedInt; 7188 IntPtrType = SignedInt; 7189 PtrDiffType = SignedInt; 7190 break; 7191 case llvm::Triple::NetBSD: 7192 case llvm::Triple::OpenBSD: 7193 SizeType = UnsignedLong; 7194 IntPtrType = SignedLong; 7195 PtrDiffType = SignedLong; 7196 break; 7197 } 7198 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 7199 // on up to 64 bits. 7200 MaxAtomicPromoteWidth = 64; 7201 MaxAtomicInlineWidth = 32; 7202 } 7203 7204 void getTargetDefines(const LangOptions &Opts, 7205 MacroBuilder &Builder) const override { 7206 SparcTargetInfo::getTargetDefines(Opts, Builder); 7207 switch (getCPUGeneration(CPU)) { 7208 case CG_V8: 7209 Builder.defineMacro("__sparcv8"); 7210 if (getTriple().getOS() != llvm::Triple::Solaris) 7211 Builder.defineMacro("__sparcv8__"); 7212 break; 7213 case CG_V9: 7214 Builder.defineMacro("__sparcv9"); 7215 if (getTriple().getOS() != llvm::Triple::Solaris) { 7216 Builder.defineMacro("__sparcv9__"); 7217 Builder.defineMacro("__sparc_v9__"); 7218 } 7219 break; 7220 } 7221 if (getTriple().getVendor() == llvm::Triple::Myriad) { 7222 std::string MyriadArchValue, Myriad2Value; 7223 Builder.defineMacro("__sparc_v8__"); 7224 Builder.defineMacro("__leon__"); 7225 switch (CPU) { 7226 case CK_MYRIAD2150: 7227 MyriadArchValue = "__ma2150"; 7228 Myriad2Value = "2"; 7229 break; 7230 case CK_MYRIAD2450: 7231 MyriadArchValue = "__ma2450"; 7232 Myriad2Value = "2"; 7233 break; 7234 default: 7235 MyriadArchValue = "__ma2100"; 7236 Myriad2Value = "1"; 7237 break; 7238 } 7239 Builder.defineMacro(MyriadArchValue, "1"); 7240 Builder.defineMacro(MyriadArchValue+"__", "1"); 7241 Builder.defineMacro("__myriad2__", Myriad2Value); 7242 Builder.defineMacro("__myriad2", Myriad2Value); 7243 } 7244 } 7245 7246 bool hasSjLjLowering() const override { 7247 return true; 7248 } 7249 }; 7250 7251 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 7252 class SparcV8elTargetInfo : public SparcV8TargetInfo { 7253 public: 7254 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7255 : SparcV8TargetInfo(Triple, Opts) { 7256 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7257 } 7258 }; 7259 7260 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 7261 class SparcV9TargetInfo : public SparcTargetInfo { 7262 public: 7263 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7264 : SparcTargetInfo(Triple, Opts) { 7265 // FIXME: Support Sparc quad-precision long double? 7266 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 7267 // This is an LP64 platform. 7268 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7269 7270 // OpenBSD uses long long for int64_t and intmax_t. 7271 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7272 IntMaxType = SignedLongLong; 7273 else 7274 IntMaxType = SignedLong; 7275 Int64Type = IntMaxType; 7276 7277 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7278 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7279 LongDoubleWidth = 128; 7280 LongDoubleAlign = 128; 7281 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7282 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7283 } 7284 7285 void getTargetDefines(const LangOptions &Opts, 7286 MacroBuilder &Builder) const override { 7287 SparcTargetInfo::getTargetDefines(Opts, Builder); 7288 Builder.defineMacro("__sparcv9"); 7289 Builder.defineMacro("__arch64__"); 7290 // Solaris doesn't need these variants, but the BSDs do. 7291 if (getTriple().getOS() != llvm::Triple::Solaris) { 7292 Builder.defineMacro("__sparc64__"); 7293 Builder.defineMacro("__sparc_v9__"); 7294 Builder.defineMacro("__sparcv9__"); 7295 } 7296 } 7297 7298 bool setCPU(const std::string &Name) override { 7299 if (!SparcTargetInfo::setCPU(Name)) 7300 return false; 7301 return getCPUGeneration(CPU) == CG_V9; 7302 } 7303 }; 7304 7305 class SystemZTargetInfo : public TargetInfo { 7306 static const Builtin::Info BuiltinInfo[]; 7307 static const char *const GCCRegNames[]; 7308 std::string CPU; 7309 bool HasTransactionalExecution; 7310 bool HasVector; 7311 7312 public: 7313 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7314 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 7315 HasVector(false) { 7316 IntMaxType = SignedLong; 7317 Int64Type = SignedLong; 7318 TLSSupported = true; 7319 IntWidth = IntAlign = 32; 7320 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7321 PointerWidth = PointerAlign = 64; 7322 LongDoubleWidth = 128; 7323 LongDoubleAlign = 64; 7324 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7325 DefaultAlignForAttributeAligned = 64; 7326 MinGlobalAlign = 16; 7327 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7328 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7329 } 7330 void getTargetDefines(const LangOptions &Opts, 7331 MacroBuilder &Builder) const override { 7332 Builder.defineMacro("__s390__"); 7333 Builder.defineMacro("__s390x__"); 7334 Builder.defineMacro("__zarch__"); 7335 Builder.defineMacro("__LONG_DOUBLE_128__"); 7336 7337 const std::string ISARev = llvm::StringSwitch<std::string>(CPU) 7338 .Cases("arch8", "z10", "8") 7339 .Cases("arch9", "z196", "9") 7340 .Cases("arch10", "zEC12", "10") 7341 .Cases("arch11", "z13", "11") 7342 .Default(""); 7343 if (!ISARev.empty()) 7344 Builder.defineMacro("__ARCH__", ISARev); 7345 7346 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7347 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7348 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7349 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7350 7351 if (HasTransactionalExecution) 7352 Builder.defineMacro("__HTM__"); 7353 if (HasVector) 7354 Builder.defineMacro("__VX__"); 7355 if (Opts.ZVector) 7356 Builder.defineMacro("__VEC__", "10301"); 7357 } 7358 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7359 return llvm::makeArrayRef(BuiltinInfo, 7360 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7361 } 7362 7363 ArrayRef<const char *> getGCCRegNames() const override; 7364 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7365 // No aliases. 7366 return None; 7367 } 7368 bool validateAsmConstraint(const char *&Name, 7369 TargetInfo::ConstraintInfo &info) const override; 7370 const char *getClobbers() const override { 7371 // FIXME: Is this really right? 7372 return ""; 7373 } 7374 BuiltinVaListKind getBuiltinVaListKind() const override { 7375 return TargetInfo::SystemZBuiltinVaList; 7376 } 7377 bool setCPU(const std::string &Name) override { 7378 CPU = Name; 7379 bool CPUKnown = llvm::StringSwitch<bool>(Name) 7380 .Case("z10", true) 7381 .Case("arch8", true) 7382 .Case("z196", true) 7383 .Case("arch9", true) 7384 .Case("zEC12", true) 7385 .Case("arch10", true) 7386 .Case("z13", true) 7387 .Case("arch11", true) 7388 .Default(false); 7389 7390 return CPUKnown; 7391 } 7392 bool 7393 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7394 StringRef CPU, 7395 const std::vector<std::string> &FeaturesVec) const override { 7396 if (CPU == "zEC12" || CPU == "arch10") 7397 Features["transactional-execution"] = true; 7398 if (CPU == "z13" || CPU == "arch11") { 7399 Features["transactional-execution"] = true; 7400 Features["vector"] = true; 7401 } 7402 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7403 } 7404 7405 bool handleTargetFeatures(std::vector<std::string> &Features, 7406 DiagnosticsEngine &Diags) override { 7407 HasTransactionalExecution = false; 7408 for (const auto &Feature : Features) { 7409 if (Feature == "+transactional-execution") 7410 HasTransactionalExecution = true; 7411 else if (Feature == "+vector") 7412 HasVector = true; 7413 } 7414 // If we use the vector ABI, vector types are 64-bit aligned. 7415 if (HasVector) { 7416 MaxVectorAlign = 64; 7417 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7418 "-v128:64-a:8:16-n32:64"); 7419 } 7420 return true; 7421 } 7422 7423 bool hasFeature(StringRef Feature) const override { 7424 return llvm::StringSwitch<bool>(Feature) 7425 .Case("systemz", true) 7426 .Case("htm", HasTransactionalExecution) 7427 .Case("vx", HasVector) 7428 .Default(false); 7429 } 7430 7431 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7432 switch (CC) { 7433 case CC_C: 7434 case CC_Swift: 7435 case CC_OpenCLKernel: 7436 return CCCR_OK; 7437 default: 7438 return CCCR_Warning; 7439 } 7440 } 7441 7442 StringRef getABI() const override { 7443 if (HasVector) 7444 return "vector"; 7445 return ""; 7446 } 7447 7448 bool useFloat128ManglingForLongDouble() const override { 7449 return true; 7450 } 7451 }; 7452 7453 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7454 #define BUILTIN(ID, TYPE, ATTRS) \ 7455 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7456 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7457 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7458 #include "clang/Basic/BuiltinsSystemZ.def" 7459 }; 7460 7461 const char *const SystemZTargetInfo::GCCRegNames[] = { 7462 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7463 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7464 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7465 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7466 }; 7467 7468 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7469 return llvm::makeArrayRef(GCCRegNames); 7470 } 7471 7472 bool SystemZTargetInfo:: 7473 validateAsmConstraint(const char *&Name, 7474 TargetInfo::ConstraintInfo &Info) const { 7475 switch (*Name) { 7476 default: 7477 return false; 7478 7479 case 'a': // Address register 7480 case 'd': // Data register (equivalent to 'r') 7481 case 'f': // Floating-point register 7482 Info.setAllowsRegister(); 7483 return true; 7484 7485 case 'I': // Unsigned 8-bit constant 7486 case 'J': // Unsigned 12-bit constant 7487 case 'K': // Signed 16-bit constant 7488 case 'L': // Signed 20-bit displacement (on all targets we support) 7489 case 'M': // 0x7fffffff 7490 return true; 7491 7492 case 'Q': // Memory with base and unsigned 12-bit displacement 7493 case 'R': // Likewise, plus an index 7494 case 'S': // Memory with base and signed 20-bit displacement 7495 case 'T': // Likewise, plus an index 7496 Info.setAllowsMemory(); 7497 return true; 7498 } 7499 } 7500 7501 class MSP430TargetInfo : public TargetInfo { 7502 static const char *const GCCRegNames[]; 7503 7504 public: 7505 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7506 : TargetInfo(Triple) { 7507 TLSSupported = false; 7508 IntWidth = 16; 7509 IntAlign = 16; 7510 LongWidth = 32; 7511 LongLongWidth = 64; 7512 LongAlign = LongLongAlign = 16; 7513 PointerWidth = 16; 7514 PointerAlign = 16; 7515 SuitableAlign = 16; 7516 SizeType = UnsignedInt; 7517 IntMaxType = SignedLongLong; 7518 IntPtrType = SignedInt; 7519 PtrDiffType = SignedInt; 7520 SigAtomicType = SignedLong; 7521 resetDataLayout("e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16"); 7522 } 7523 void getTargetDefines(const LangOptions &Opts, 7524 MacroBuilder &Builder) const override { 7525 Builder.defineMacro("MSP430"); 7526 Builder.defineMacro("__MSP430__"); 7527 // FIXME: defines for different 'flavours' of MCU 7528 } 7529 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7530 // FIXME: Implement. 7531 return None; 7532 } 7533 bool hasFeature(StringRef Feature) const override { 7534 return Feature == "msp430"; 7535 } 7536 ArrayRef<const char *> getGCCRegNames() const override; 7537 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7538 // No aliases. 7539 return None; 7540 } 7541 bool validateAsmConstraint(const char *&Name, 7542 TargetInfo::ConstraintInfo &info) const override { 7543 // FIXME: implement 7544 switch (*Name) { 7545 case 'K': // the constant 1 7546 case 'L': // constant -1^20 .. 1^19 7547 case 'M': // constant 1-4: 7548 return true; 7549 } 7550 // No target constraints for now. 7551 return false; 7552 } 7553 const char *getClobbers() const override { 7554 // FIXME: Is this really right? 7555 return ""; 7556 } 7557 BuiltinVaListKind getBuiltinVaListKind() const override { 7558 // FIXME: implement 7559 return TargetInfo::CharPtrBuiltinVaList; 7560 } 7561 }; 7562 7563 const char *const MSP430TargetInfo::GCCRegNames[] = { 7564 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7565 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7566 7567 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7568 return llvm::makeArrayRef(GCCRegNames); 7569 } 7570 7571 // LLVM and Clang cannot be used directly to output native binaries for 7572 // target, but is used to compile C code to llvm bitcode with correct 7573 // type and alignment information. 7574 // 7575 // TCE uses the llvm bitcode as input and uses it for generating customized 7576 // target processor and program binary. TCE co-design environment is 7577 // publicly available in http://tce.cs.tut.fi 7578 7579 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7580 0, // Default 7581 3, // opencl_global 7582 4, // opencl_local 7583 5, // opencl_constant 7584 // FIXME: generic has to be added to the target 7585 0, // opencl_generic 7586 0, // cuda_device 7587 0, // cuda_constant 7588 0 // cuda_shared 7589 }; 7590 7591 class TCETargetInfo : public TargetInfo { 7592 public: 7593 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7594 : TargetInfo(Triple) { 7595 TLSSupported = false; 7596 IntWidth = 32; 7597 LongWidth = LongLongWidth = 32; 7598 PointerWidth = 32; 7599 IntAlign = 32; 7600 LongAlign = LongLongAlign = 32; 7601 PointerAlign = 32; 7602 SuitableAlign = 32; 7603 SizeType = UnsignedInt; 7604 IntMaxType = SignedLong; 7605 IntPtrType = SignedInt; 7606 PtrDiffType = SignedInt; 7607 FloatWidth = 32; 7608 FloatAlign = 32; 7609 DoubleWidth = 32; 7610 DoubleAlign = 32; 7611 LongDoubleWidth = 32; 7612 LongDoubleAlign = 32; 7613 FloatFormat = &llvm::APFloat::IEEEsingle(); 7614 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7615 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7616 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7617 "i16:16:32-i32:32:32-i64:32:32-" 7618 "f32:32:32-f64:32:32-v64:32:32-" 7619 "v128:32:32-v256:32:32-v512:32:32-" 7620 "v1024:32:32-a0:0:32-n32"); 7621 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7622 UseAddrSpaceMapMangling = true; 7623 } 7624 7625 void getTargetDefines(const LangOptions &Opts, 7626 MacroBuilder &Builder) const override { 7627 DefineStd(Builder, "tce", Opts); 7628 Builder.defineMacro("__TCE__"); 7629 Builder.defineMacro("__TCE_V1__"); 7630 } 7631 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7632 7633 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7634 const char *getClobbers() const override { return ""; } 7635 BuiltinVaListKind getBuiltinVaListKind() const override { 7636 return TargetInfo::VoidPtrBuiltinVaList; 7637 } 7638 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7639 bool validateAsmConstraint(const char *&Name, 7640 TargetInfo::ConstraintInfo &info) const override { 7641 return true; 7642 } 7643 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7644 return None; 7645 } 7646 }; 7647 7648 class TCELETargetInfo : public TCETargetInfo { 7649 public: 7650 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7651 : TCETargetInfo(Triple, Opts) { 7652 BigEndian = false; 7653 7654 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7655 "i16:16:32-i32:32:32-i64:32:32-" 7656 "f32:32:32-f64:32:32-v64:32:32-" 7657 "v128:32:32-v256:32:32-v512:32:32-" 7658 "v1024:32:32-a0:0:32-n32"); 7659 7660 } 7661 7662 virtual void getTargetDefines(const LangOptions &Opts, 7663 MacroBuilder &Builder) const { 7664 DefineStd(Builder, "tcele", Opts); 7665 Builder.defineMacro("__TCE__"); 7666 Builder.defineMacro("__TCE_V1__"); 7667 Builder.defineMacro("__TCELE__"); 7668 Builder.defineMacro("__TCELE_V1__"); 7669 } 7670 7671 }; 7672 7673 class BPFTargetInfo : public TargetInfo { 7674 public: 7675 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7676 : TargetInfo(Triple) { 7677 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7678 SizeType = UnsignedLong; 7679 PtrDiffType = SignedLong; 7680 IntPtrType = SignedLong; 7681 IntMaxType = SignedLong; 7682 Int64Type = SignedLong; 7683 RegParmMax = 5; 7684 if (Triple.getArch() == llvm::Triple::bpfeb) { 7685 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7686 } else { 7687 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7688 } 7689 MaxAtomicPromoteWidth = 64; 7690 MaxAtomicInlineWidth = 64; 7691 TLSSupported = false; 7692 } 7693 void getTargetDefines(const LangOptions &Opts, 7694 MacroBuilder &Builder) const override { 7695 DefineStd(Builder, "bpf", Opts); 7696 Builder.defineMacro("__BPF__"); 7697 } 7698 bool hasFeature(StringRef Feature) const override { 7699 return Feature == "bpf"; 7700 } 7701 7702 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7703 const char *getClobbers() const override { 7704 return ""; 7705 } 7706 BuiltinVaListKind getBuiltinVaListKind() const override { 7707 return TargetInfo::VoidPtrBuiltinVaList; 7708 } 7709 ArrayRef<const char *> getGCCRegNames() const override { 7710 return None; 7711 } 7712 bool validateAsmConstraint(const char *&Name, 7713 TargetInfo::ConstraintInfo &info) const override { 7714 return true; 7715 } 7716 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7717 return None; 7718 } 7719 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7720 switch (CC) { 7721 default: 7722 return CCCR_Warning; 7723 case CC_C: 7724 case CC_OpenCLKernel: 7725 return CCCR_OK; 7726 } 7727 } 7728 }; 7729 7730 class MipsTargetInfo : public TargetInfo { 7731 void setDataLayout() { 7732 StringRef Layout; 7733 7734 if (ABI == "o32") 7735 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7736 else if (ABI == "n32") 7737 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7738 else if (ABI == "n64") 7739 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7740 else 7741 llvm_unreachable("Invalid ABI"); 7742 7743 if (BigEndian) 7744 resetDataLayout(("E-" + Layout).str()); 7745 else 7746 resetDataLayout(("e-" + Layout).str()); 7747 } 7748 7749 7750 static const Builtin::Info BuiltinInfo[]; 7751 std::string CPU; 7752 bool IsMips16; 7753 bool IsMicromips; 7754 bool IsNan2008; 7755 bool IsSingleFloat; 7756 bool IsNoABICalls; 7757 bool CanUseBSDABICalls; 7758 enum MipsFloatABI { 7759 HardFloat, SoftFloat 7760 } FloatABI; 7761 enum DspRevEnum { 7762 NoDSP, DSP1, DSP2 7763 } DspRev; 7764 bool HasMSA; 7765 bool DisableMadd4; 7766 7767 protected: 7768 bool HasFP64; 7769 std::string ABI; 7770 7771 public: 7772 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7773 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7774 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 7775 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 7776 HasMSA(false), DisableMadd4(false), HasFP64(false) { 7777 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7778 7779 setABI((getTriple().getArch() == llvm::Triple::mips || 7780 getTriple().getArch() == llvm::Triple::mipsel) 7781 ? "o32" 7782 : "n64"); 7783 7784 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7785 7786 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 7787 Triple.getOS() == llvm::Triple::OpenBSD; 7788 } 7789 7790 bool isNaN2008Default() const { 7791 return CPU == "mips32r6" || CPU == "mips64r6"; 7792 } 7793 7794 bool isFP64Default() const { 7795 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7796 } 7797 7798 bool isNan2008() const override { 7799 return IsNan2008; 7800 } 7801 7802 bool processorSupportsGPR64() const { 7803 return llvm::StringSwitch<bool>(CPU) 7804 .Case("mips3", true) 7805 .Case("mips4", true) 7806 .Case("mips5", true) 7807 .Case("mips64", true) 7808 .Case("mips64r2", true) 7809 .Case("mips64r3", true) 7810 .Case("mips64r5", true) 7811 .Case("mips64r6", true) 7812 .Case("octeon", true) 7813 .Default(false); 7814 return false; 7815 } 7816 7817 StringRef getABI() const override { return ABI; } 7818 bool setABI(const std::string &Name) override { 7819 if (Name == "o32") { 7820 setO32ABITypes(); 7821 ABI = Name; 7822 return true; 7823 } 7824 7825 if (Name == "n32") { 7826 setN32ABITypes(); 7827 ABI = Name; 7828 return true; 7829 } 7830 if (Name == "n64") { 7831 setN64ABITypes(); 7832 ABI = Name; 7833 return true; 7834 } 7835 return false; 7836 } 7837 7838 void setO32ABITypes() { 7839 Int64Type = SignedLongLong; 7840 IntMaxType = Int64Type; 7841 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7842 LongDoubleWidth = LongDoubleAlign = 64; 7843 LongWidth = LongAlign = 32; 7844 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7845 PointerWidth = PointerAlign = 32; 7846 PtrDiffType = SignedInt; 7847 SizeType = UnsignedInt; 7848 SuitableAlign = 64; 7849 } 7850 7851 void setN32N64ABITypes() { 7852 LongDoubleWidth = LongDoubleAlign = 128; 7853 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7854 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7855 LongDoubleWidth = LongDoubleAlign = 64; 7856 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7857 } 7858 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7859 SuitableAlign = 128; 7860 } 7861 7862 void setN64ABITypes() { 7863 setN32N64ABITypes(); 7864 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 7865 Int64Type = SignedLongLong; 7866 } else { 7867 Int64Type = SignedLong; 7868 } 7869 IntMaxType = Int64Type; 7870 LongWidth = LongAlign = 64; 7871 PointerWidth = PointerAlign = 64; 7872 PtrDiffType = SignedLong; 7873 SizeType = UnsignedLong; 7874 } 7875 7876 void setN32ABITypes() { 7877 setN32N64ABITypes(); 7878 Int64Type = SignedLongLong; 7879 IntMaxType = Int64Type; 7880 LongWidth = LongAlign = 32; 7881 PointerWidth = PointerAlign = 32; 7882 PtrDiffType = SignedInt; 7883 SizeType = UnsignedInt; 7884 } 7885 7886 bool setCPU(const std::string &Name) override { 7887 CPU = Name; 7888 return llvm::StringSwitch<bool>(Name) 7889 .Case("mips1", true) 7890 .Case("mips2", true) 7891 .Case("mips3", true) 7892 .Case("mips4", true) 7893 .Case("mips5", true) 7894 .Case("mips32", true) 7895 .Case("mips32r2", true) 7896 .Case("mips32r3", true) 7897 .Case("mips32r5", true) 7898 .Case("mips32r6", true) 7899 .Case("mips64", true) 7900 .Case("mips64r2", true) 7901 .Case("mips64r3", true) 7902 .Case("mips64r5", true) 7903 .Case("mips64r6", true) 7904 .Case("octeon", true) 7905 .Case("p5600", true) 7906 .Default(false); 7907 } 7908 const std::string& getCPU() const { return CPU; } 7909 bool 7910 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7911 StringRef CPU, 7912 const std::vector<std::string> &FeaturesVec) const override { 7913 if (CPU.empty()) 7914 CPU = getCPU(); 7915 if (CPU == "octeon") 7916 Features["mips64r2"] = Features["cnmips"] = true; 7917 else 7918 Features[CPU] = true; 7919 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7920 } 7921 7922 void getTargetDefines(const LangOptions &Opts, 7923 MacroBuilder &Builder) const override { 7924 if (BigEndian) { 7925 DefineStd(Builder, "MIPSEB", Opts); 7926 Builder.defineMacro("_MIPSEB"); 7927 } else { 7928 DefineStd(Builder, "MIPSEL", Opts); 7929 Builder.defineMacro("_MIPSEL"); 7930 } 7931 7932 Builder.defineMacro("__mips__"); 7933 Builder.defineMacro("_mips"); 7934 if (Opts.GNUMode) 7935 Builder.defineMacro("mips"); 7936 7937 if (ABI == "o32") { 7938 Builder.defineMacro("__mips", "32"); 7939 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7940 } else { 7941 Builder.defineMacro("__mips", "64"); 7942 Builder.defineMacro("__mips64"); 7943 Builder.defineMacro("__mips64__"); 7944 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7945 } 7946 7947 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7948 .Cases("mips32", "mips64", "1") 7949 .Cases("mips32r2", "mips64r2", "2") 7950 .Cases("mips32r3", "mips64r3", "3") 7951 .Cases("mips32r5", "mips64r5", "5") 7952 .Cases("mips32r6", "mips64r6", "6") 7953 .Default(""); 7954 if (!ISARev.empty()) 7955 Builder.defineMacro("__mips_isa_rev", ISARev); 7956 7957 if (ABI == "o32") { 7958 Builder.defineMacro("__mips_o32"); 7959 Builder.defineMacro("_ABIO32", "1"); 7960 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7961 } else if (ABI == "n32") { 7962 Builder.defineMacro("__mips_n32"); 7963 Builder.defineMacro("_ABIN32", "2"); 7964 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7965 } else if (ABI == "n64") { 7966 Builder.defineMacro("__mips_n64"); 7967 Builder.defineMacro("_ABI64", "3"); 7968 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7969 } else 7970 llvm_unreachable("Invalid ABI."); 7971 7972 if (!IsNoABICalls) { 7973 Builder.defineMacro("__mips_abicalls"); 7974 if (CanUseBSDABICalls) 7975 Builder.defineMacro("__ABICALLS__"); 7976 } 7977 7978 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7979 7980 switch (FloatABI) { 7981 case HardFloat: 7982 Builder.defineMacro("__mips_hard_float", Twine(1)); 7983 break; 7984 case SoftFloat: 7985 Builder.defineMacro("__mips_soft_float", Twine(1)); 7986 break; 7987 } 7988 7989 if (IsSingleFloat) 7990 Builder.defineMacro("__mips_single_float", Twine(1)); 7991 7992 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7993 Builder.defineMacro("_MIPS_FPSET", 7994 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7995 7996 if (IsMips16) 7997 Builder.defineMacro("__mips16", Twine(1)); 7998 7999 if (IsMicromips) 8000 Builder.defineMacro("__mips_micromips", Twine(1)); 8001 8002 if (IsNan2008) 8003 Builder.defineMacro("__mips_nan2008", Twine(1)); 8004 8005 switch (DspRev) { 8006 default: 8007 break; 8008 case DSP1: 8009 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 8010 Builder.defineMacro("__mips_dsp", Twine(1)); 8011 break; 8012 case DSP2: 8013 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 8014 Builder.defineMacro("__mips_dspr2", Twine(1)); 8015 Builder.defineMacro("__mips_dsp", Twine(1)); 8016 break; 8017 } 8018 8019 if (HasMSA) 8020 Builder.defineMacro("__mips_msa", Twine(1)); 8021 8022 if (DisableMadd4) 8023 Builder.defineMacro("__mips_no_madd4", Twine(1)); 8024 8025 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 8026 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 8027 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 8028 8029 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 8030 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 8031 8032 // These shouldn't be defined for MIPS-I but there's no need to check 8033 // for that since MIPS-I isn't supported. 8034 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 8035 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 8036 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 8037 8038 // 32-bit MIPS processors don't have the necessary lld/scd instructions 8039 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 8040 // the instructions exist but using them violates the ABI since they 8041 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 8042 if (ABI == "n32" || ABI == "n64") 8043 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 8044 } 8045 8046 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8047 return llvm::makeArrayRef(BuiltinInfo, 8048 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 8049 } 8050 bool hasFeature(StringRef Feature) const override { 8051 return llvm::StringSwitch<bool>(Feature) 8052 .Case("mips", true) 8053 .Case("fp64", HasFP64) 8054 .Default(false); 8055 } 8056 BuiltinVaListKind getBuiltinVaListKind() const override { 8057 return TargetInfo::VoidPtrBuiltinVaList; 8058 } 8059 ArrayRef<const char *> getGCCRegNames() const override { 8060 static const char *const GCCRegNames[] = { 8061 // CPU register names 8062 // Must match second column of GCCRegAliases 8063 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 8064 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 8065 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 8066 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 8067 // Floating point register names 8068 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 8069 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 8070 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 8071 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 8072 // Hi/lo and condition register names 8073 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 8074 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 8075 "$ac3hi","$ac3lo", 8076 // MSA register names 8077 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 8078 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 8079 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 8080 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 8081 // MSA control register names 8082 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 8083 "$msarequest", "$msamap", "$msaunmap" 8084 }; 8085 return llvm::makeArrayRef(GCCRegNames); 8086 } 8087 bool validateAsmConstraint(const char *&Name, 8088 TargetInfo::ConstraintInfo &Info) const override { 8089 switch (*Name) { 8090 default: 8091 return false; 8092 case 'r': // CPU registers. 8093 case 'd': // Equivalent to "r" unless generating MIPS16 code. 8094 case 'y': // Equivalent to "r", backward compatibility only. 8095 case 'f': // floating-point registers. 8096 case 'c': // $25 for indirect jumps 8097 case 'l': // lo register 8098 case 'x': // hilo register pair 8099 Info.setAllowsRegister(); 8100 return true; 8101 case 'I': // Signed 16-bit constant 8102 case 'J': // Integer 0 8103 case 'K': // Unsigned 16-bit constant 8104 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 8105 case 'M': // Constants not loadable via lui, addiu, or ori 8106 case 'N': // Constant -1 to -65535 8107 case 'O': // A signed 15-bit constant 8108 case 'P': // A constant between 1 go 65535 8109 return true; 8110 case 'R': // An address that can be used in a non-macro load or store 8111 Info.setAllowsMemory(); 8112 return true; 8113 case 'Z': 8114 if (Name[1] == 'C') { // An address usable by ll, and sc. 8115 Info.setAllowsMemory(); 8116 Name++; // Skip over 'Z'. 8117 return true; 8118 } 8119 return false; 8120 } 8121 } 8122 8123 std::string convertConstraint(const char *&Constraint) const override { 8124 std::string R; 8125 switch (*Constraint) { 8126 case 'Z': // Two-character constraint; add "^" hint for later parsing. 8127 if (Constraint[1] == 'C') { 8128 R = std::string("^") + std::string(Constraint, 2); 8129 Constraint++; 8130 return R; 8131 } 8132 break; 8133 } 8134 return TargetInfo::convertConstraint(Constraint); 8135 } 8136 8137 const char *getClobbers() const override { 8138 // In GCC, $1 is not widely used in generated code (it's used only in a few 8139 // specific situations), so there is no real need for users to add it to 8140 // the clobbers list if they want to use it in their inline assembly code. 8141 // 8142 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 8143 // code generation, so using it in inline assembly without adding it to the 8144 // clobbers list can cause conflicts between the inline assembly code and 8145 // the surrounding generated code. 8146 // 8147 // Another problem is that LLVM is allowed to choose $1 for inline assembly 8148 // operands, which will conflict with the ".set at" assembler option (which 8149 // we use only for inline assembly, in order to maintain compatibility with 8150 // GCC) and will also conflict with the user's usage of $1. 8151 // 8152 // The easiest way to avoid these conflicts and keep $1 as an allocatable 8153 // register for generated code is to automatically clobber $1 for all inline 8154 // assembly code. 8155 // 8156 // FIXME: We should automatically clobber $1 only for inline assembly code 8157 // which actually uses it. This would allow LLVM to use $1 for inline 8158 // assembly operands if the user's assembly code doesn't use it. 8159 return "~{$1}"; 8160 } 8161 8162 bool handleTargetFeatures(std::vector<std::string> &Features, 8163 DiagnosticsEngine &Diags) override { 8164 IsMips16 = false; 8165 IsMicromips = false; 8166 IsNan2008 = isNaN2008Default(); 8167 IsSingleFloat = false; 8168 FloatABI = HardFloat; 8169 DspRev = NoDSP; 8170 HasFP64 = isFP64Default(); 8171 8172 for (const auto &Feature : Features) { 8173 if (Feature == "+single-float") 8174 IsSingleFloat = true; 8175 else if (Feature == "+soft-float") 8176 FloatABI = SoftFloat; 8177 else if (Feature == "+mips16") 8178 IsMips16 = true; 8179 else if (Feature == "+micromips") 8180 IsMicromips = true; 8181 else if (Feature == "+dsp") 8182 DspRev = std::max(DspRev, DSP1); 8183 else if (Feature == "+dspr2") 8184 DspRev = std::max(DspRev, DSP2); 8185 else if (Feature == "+msa") 8186 HasMSA = true; 8187 else if (Feature == "+nomadd4") 8188 DisableMadd4 = true; 8189 else if (Feature == "+fp64") 8190 HasFP64 = true; 8191 else if (Feature == "-fp64") 8192 HasFP64 = false; 8193 else if (Feature == "+nan2008") 8194 IsNan2008 = true; 8195 else if (Feature == "-nan2008") 8196 IsNan2008 = false; 8197 else if (Feature == "+noabicalls") 8198 IsNoABICalls = true; 8199 } 8200 8201 setDataLayout(); 8202 8203 return true; 8204 } 8205 8206 int getEHDataRegisterNumber(unsigned RegNo) const override { 8207 if (RegNo == 0) return 4; 8208 if (RegNo == 1) return 5; 8209 return -1; 8210 } 8211 8212 bool isCLZForZeroUndef() const override { return false; } 8213 8214 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8215 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 8216 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8217 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8218 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 8219 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 8220 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 8221 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8222 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8223 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8224 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8225 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8226 {{"ra"}, "$31"}}; 8227 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 8228 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8229 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8230 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 8231 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 8232 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 8233 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8234 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8235 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8236 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8237 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8238 {{"ra"}, "$31"}}; 8239 if (ABI == "o32") 8240 return llvm::makeArrayRef(O32RegAliases); 8241 return llvm::makeArrayRef(NewABIRegAliases); 8242 } 8243 8244 bool hasInt128Type() const override { 8245 return ABI == "n32" || ABI == "n64"; 8246 } 8247 8248 bool validateTarget(DiagnosticsEngine &Diags) const override { 8249 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 8250 // this yet. It's better to fail here than on the backend assertion. 8251 if (processorSupportsGPR64() && ABI == "o32") { 8252 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8253 return false; 8254 } 8255 8256 // 64-bit ABI's require 64-bit CPU's. 8257 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 8258 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8259 return false; 8260 } 8261 8262 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 8263 // can't handle this yet. It's better to fail here than on the 8264 // backend assertion. 8265 if ((getTriple().getArch() == llvm::Triple::mips64 || 8266 getTriple().getArch() == llvm::Triple::mips64el) && 8267 ABI == "o32") { 8268 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8269 << ABI << getTriple().str(); 8270 return false; 8271 } 8272 8273 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 8274 // can't handle this yet. It's better to fail here than on the 8275 // backend assertion. 8276 if ((getTriple().getArch() == llvm::Triple::mips || 8277 getTriple().getArch() == llvm::Triple::mipsel) && 8278 (ABI == "n32" || ABI == "n64")) { 8279 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8280 << ABI << getTriple().str(); 8281 return false; 8282 } 8283 8284 return true; 8285 } 8286 }; 8287 8288 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 8289 #define BUILTIN(ID, TYPE, ATTRS) \ 8290 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8291 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8292 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8293 #include "clang/Basic/BuiltinsMips.def" 8294 }; 8295 8296 class PNaClTargetInfo : public TargetInfo { 8297 public: 8298 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8299 : TargetInfo(Triple) { 8300 this->LongAlign = 32; 8301 this->LongWidth = 32; 8302 this->PointerAlign = 32; 8303 this->PointerWidth = 32; 8304 this->IntMaxType = TargetInfo::SignedLongLong; 8305 this->Int64Type = TargetInfo::SignedLongLong; 8306 this->DoubleAlign = 64; 8307 this->LongDoubleWidth = 64; 8308 this->LongDoubleAlign = 64; 8309 this->SizeType = TargetInfo::UnsignedInt; 8310 this->PtrDiffType = TargetInfo::SignedInt; 8311 this->IntPtrType = TargetInfo::SignedInt; 8312 this->RegParmMax = 0; // Disallow regparm 8313 } 8314 8315 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8316 Builder.defineMacro("__le32__"); 8317 Builder.defineMacro("__pnacl__"); 8318 } 8319 void getTargetDefines(const LangOptions &Opts, 8320 MacroBuilder &Builder) const override { 8321 getArchDefines(Opts, Builder); 8322 } 8323 bool hasFeature(StringRef Feature) const override { 8324 return Feature == "pnacl"; 8325 } 8326 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8327 BuiltinVaListKind getBuiltinVaListKind() const override { 8328 return TargetInfo::PNaClABIBuiltinVaList; 8329 } 8330 ArrayRef<const char *> getGCCRegNames() const override; 8331 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8332 bool validateAsmConstraint(const char *&Name, 8333 TargetInfo::ConstraintInfo &Info) const override { 8334 return false; 8335 } 8336 8337 const char *getClobbers() const override { 8338 return ""; 8339 } 8340 }; 8341 8342 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8343 return None; 8344 } 8345 8346 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8347 return None; 8348 } 8349 8350 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8351 class NaClMips32TargetInfo : public MipsTargetInfo { 8352 public: 8353 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8354 : MipsTargetInfo(Triple, Opts) {} 8355 8356 BuiltinVaListKind getBuiltinVaListKind() const override { 8357 return TargetInfo::PNaClABIBuiltinVaList; 8358 } 8359 }; 8360 8361 class Le64TargetInfo : public TargetInfo { 8362 static const Builtin::Info BuiltinInfo[]; 8363 8364 public: 8365 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8366 : TargetInfo(Triple) { 8367 NoAsmVariants = true; 8368 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8369 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8370 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8371 } 8372 8373 void getTargetDefines(const LangOptions &Opts, 8374 MacroBuilder &Builder) const override { 8375 DefineStd(Builder, "unix", Opts); 8376 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8377 Builder.defineMacro("__ELF__"); 8378 } 8379 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8380 return llvm::makeArrayRef(BuiltinInfo, 8381 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8382 } 8383 BuiltinVaListKind getBuiltinVaListKind() const override { 8384 return TargetInfo::PNaClABIBuiltinVaList; 8385 } 8386 const char *getClobbers() const override { return ""; } 8387 ArrayRef<const char *> getGCCRegNames() const override { 8388 return None; 8389 } 8390 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8391 return None; 8392 } 8393 bool validateAsmConstraint(const char *&Name, 8394 TargetInfo::ConstraintInfo &Info) const override { 8395 return false; 8396 } 8397 8398 bool hasProtectedVisibility() const override { return false; } 8399 }; 8400 8401 class WebAssemblyTargetInfo : public TargetInfo { 8402 static const Builtin::Info BuiltinInfo[]; 8403 8404 enum SIMDEnum { 8405 NoSIMD, 8406 SIMD128, 8407 } SIMDLevel; 8408 8409 public: 8410 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8411 : TargetInfo(T), SIMDLevel(NoSIMD) { 8412 NoAsmVariants = true; 8413 SuitableAlign = 128; 8414 LargeArrayMinWidth = 128; 8415 LargeArrayAlign = 128; 8416 SimdDefaultAlign = 128; 8417 SigAtomicType = SignedLong; 8418 LongDoubleWidth = LongDoubleAlign = 128; 8419 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8420 SizeType = UnsignedInt; 8421 PtrDiffType = SignedInt; 8422 IntPtrType = SignedInt; 8423 } 8424 8425 protected: 8426 void getTargetDefines(const LangOptions &Opts, 8427 MacroBuilder &Builder) const override { 8428 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8429 if (SIMDLevel >= SIMD128) 8430 Builder.defineMacro("__wasm_simd128__"); 8431 } 8432 8433 private: 8434 bool 8435 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8436 StringRef CPU, 8437 const std::vector<std::string> &FeaturesVec) const override { 8438 if (CPU == "bleeding-edge") 8439 Features["simd128"] = true; 8440 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8441 } 8442 bool hasFeature(StringRef Feature) const final { 8443 return llvm::StringSwitch<bool>(Feature) 8444 .Case("simd128", SIMDLevel >= SIMD128) 8445 .Default(false); 8446 } 8447 bool handleTargetFeatures(std::vector<std::string> &Features, 8448 DiagnosticsEngine &Diags) final { 8449 for (const auto &Feature : Features) { 8450 if (Feature == "+simd128") { 8451 SIMDLevel = std::max(SIMDLevel, SIMD128); 8452 continue; 8453 } 8454 if (Feature == "-simd128") { 8455 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8456 continue; 8457 } 8458 8459 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8460 << "-target-feature"; 8461 return false; 8462 } 8463 return true; 8464 } 8465 bool setCPU(const std::string &Name) final { 8466 return llvm::StringSwitch<bool>(Name) 8467 .Case("mvp", true) 8468 .Case("bleeding-edge", true) 8469 .Case("generic", true) 8470 .Default(false); 8471 } 8472 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8473 return llvm::makeArrayRef(BuiltinInfo, 8474 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8475 } 8476 BuiltinVaListKind getBuiltinVaListKind() const final { 8477 return VoidPtrBuiltinVaList; 8478 } 8479 ArrayRef<const char *> getGCCRegNames() const final { 8480 return None; 8481 } 8482 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8483 return None; 8484 } 8485 bool 8486 validateAsmConstraint(const char *&Name, 8487 TargetInfo::ConstraintInfo &Info) const final { 8488 return false; 8489 } 8490 const char *getClobbers() const final { return ""; } 8491 bool isCLZForZeroUndef() const final { return false; } 8492 bool hasInt128Type() const final { return true; } 8493 IntType getIntTypeByWidth(unsigned BitWidth, 8494 bool IsSigned) const final { 8495 // WebAssembly prefers long long for explicitly 64-bit integers. 8496 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8497 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8498 } 8499 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8500 bool IsSigned) const final { 8501 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8502 return BitWidth == 64 8503 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8504 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8505 } 8506 }; 8507 8508 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8509 #define BUILTIN(ID, TYPE, ATTRS) \ 8510 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8511 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8512 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8513 #include "clang/Basic/BuiltinsWebAssembly.def" 8514 }; 8515 8516 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8517 public: 8518 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8519 const TargetOptions &Opts) 8520 : WebAssemblyTargetInfo(T, Opts) { 8521 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8522 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8523 } 8524 8525 protected: 8526 void getTargetDefines(const LangOptions &Opts, 8527 MacroBuilder &Builder) const override { 8528 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8529 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8530 } 8531 }; 8532 8533 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8534 public: 8535 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8536 const TargetOptions &Opts) 8537 : WebAssemblyTargetInfo(T, Opts) { 8538 LongAlign = LongWidth = 64; 8539 PointerAlign = PointerWidth = 64; 8540 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8541 SizeType = UnsignedLong; 8542 PtrDiffType = SignedLong; 8543 IntPtrType = SignedLong; 8544 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8545 } 8546 8547 protected: 8548 void getTargetDefines(const LangOptions &Opts, 8549 MacroBuilder &Builder) const override { 8550 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8551 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8552 } 8553 }; 8554 8555 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8556 #define BUILTIN(ID, TYPE, ATTRS) \ 8557 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8558 #include "clang/Basic/BuiltinsLe64.def" 8559 }; 8560 8561 static const unsigned SPIRAddrSpaceMap[] = { 8562 0, // Default 8563 1, // opencl_global 8564 3, // opencl_local 8565 2, // opencl_constant 8566 4, // opencl_generic 8567 0, // cuda_device 8568 0, // cuda_constant 8569 0 // cuda_shared 8570 }; 8571 class SPIRTargetInfo : public TargetInfo { 8572 public: 8573 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8574 : TargetInfo(Triple) { 8575 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8576 "SPIR target must use unknown OS"); 8577 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8578 "SPIR target must use unknown environment type"); 8579 TLSSupported = false; 8580 LongWidth = LongAlign = 64; 8581 AddrSpaceMap = &SPIRAddrSpaceMap; 8582 UseAddrSpaceMapMangling = true; 8583 // Define available target features 8584 // These must be defined in sorted order! 8585 NoAsmVariants = true; 8586 } 8587 void getTargetDefines(const LangOptions &Opts, 8588 MacroBuilder &Builder) const override { 8589 DefineStd(Builder, "SPIR", Opts); 8590 } 8591 bool hasFeature(StringRef Feature) const override { 8592 return Feature == "spir"; 8593 } 8594 8595 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8596 const char *getClobbers() const override { return ""; } 8597 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8598 bool validateAsmConstraint(const char *&Name, 8599 TargetInfo::ConstraintInfo &info) const override { 8600 return true; 8601 } 8602 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8603 return None; 8604 } 8605 BuiltinVaListKind getBuiltinVaListKind() const override { 8606 return TargetInfo::VoidPtrBuiltinVaList; 8607 } 8608 8609 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8610 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8611 : CCCR_Warning; 8612 } 8613 8614 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8615 return CC_SpirFunction; 8616 } 8617 8618 void setSupportedOpenCLOpts() override { 8619 // Assume all OpenCL extensions and optional core features are supported 8620 // for SPIR since it is a generic target. 8621 getSupportedOpenCLOpts().supportAll(); 8622 } 8623 }; 8624 8625 class SPIR32TargetInfo : public SPIRTargetInfo { 8626 public: 8627 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8628 : SPIRTargetInfo(Triple, Opts) { 8629 PointerWidth = PointerAlign = 32; 8630 SizeType = TargetInfo::UnsignedInt; 8631 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8632 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8633 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8634 } 8635 void getTargetDefines(const LangOptions &Opts, 8636 MacroBuilder &Builder) const override { 8637 DefineStd(Builder, "SPIR32", Opts); 8638 } 8639 }; 8640 8641 class SPIR64TargetInfo : public SPIRTargetInfo { 8642 public: 8643 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8644 : SPIRTargetInfo(Triple, Opts) { 8645 PointerWidth = PointerAlign = 64; 8646 SizeType = TargetInfo::UnsignedLong; 8647 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8648 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8649 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8650 } 8651 void getTargetDefines(const LangOptions &Opts, 8652 MacroBuilder &Builder) const override { 8653 DefineStd(Builder, "SPIR64", Opts); 8654 } 8655 }; 8656 8657 class XCoreTargetInfo : public TargetInfo { 8658 static const Builtin::Info BuiltinInfo[]; 8659 public: 8660 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8661 : TargetInfo(Triple) { 8662 NoAsmVariants = true; 8663 LongLongAlign = 32; 8664 SuitableAlign = 32; 8665 DoubleAlign = LongDoubleAlign = 32; 8666 SizeType = UnsignedInt; 8667 PtrDiffType = SignedInt; 8668 IntPtrType = SignedInt; 8669 WCharType = UnsignedChar; 8670 WIntType = UnsignedInt; 8671 UseZeroLengthBitfieldAlignment = true; 8672 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8673 "-f64:32-a:0:32-n32"); 8674 } 8675 void getTargetDefines(const LangOptions &Opts, 8676 MacroBuilder &Builder) const override { 8677 Builder.defineMacro("__XS1B__"); 8678 } 8679 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8680 return llvm::makeArrayRef(BuiltinInfo, 8681 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8682 } 8683 BuiltinVaListKind getBuiltinVaListKind() const override { 8684 return TargetInfo::VoidPtrBuiltinVaList; 8685 } 8686 const char *getClobbers() const override { 8687 return ""; 8688 } 8689 ArrayRef<const char *> getGCCRegNames() const override { 8690 static const char * const GCCRegNames[] = { 8691 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8692 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8693 }; 8694 return llvm::makeArrayRef(GCCRegNames); 8695 } 8696 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8697 return None; 8698 } 8699 bool validateAsmConstraint(const char *&Name, 8700 TargetInfo::ConstraintInfo &Info) const override { 8701 return false; 8702 } 8703 int getEHDataRegisterNumber(unsigned RegNo) const override { 8704 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8705 return (RegNo < 2)? RegNo : -1; 8706 } 8707 bool allowsLargerPreferedTypeAlignment() const override { 8708 return false; 8709 } 8710 }; 8711 8712 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8713 #define BUILTIN(ID, TYPE, ATTRS) \ 8714 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8715 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8716 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8717 #include "clang/Basic/BuiltinsXCore.def" 8718 }; 8719 8720 // x86_32 Android target 8721 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8722 public: 8723 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8724 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8725 SuitableAlign = 32; 8726 LongDoubleWidth = 64; 8727 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8728 } 8729 }; 8730 8731 // x86_64 Android target 8732 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8733 public: 8734 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8735 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8736 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8737 } 8738 8739 bool useFloat128ManglingForLongDouble() const override { 8740 return true; 8741 } 8742 }; 8743 8744 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8745 class RenderScript32TargetInfo : public ARMleTargetInfo { 8746 public: 8747 RenderScript32TargetInfo(const llvm::Triple &Triple, 8748 const TargetOptions &Opts) 8749 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8750 Triple.getOSName(), 8751 Triple.getEnvironmentName()), 8752 Opts) { 8753 IsRenderScriptTarget = true; 8754 LongWidth = LongAlign = 64; 8755 } 8756 void getTargetDefines(const LangOptions &Opts, 8757 MacroBuilder &Builder) const override { 8758 Builder.defineMacro("__RENDERSCRIPT__"); 8759 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8760 } 8761 }; 8762 8763 // 64-bit RenderScript is aarch64 8764 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8765 public: 8766 RenderScript64TargetInfo(const llvm::Triple &Triple, 8767 const TargetOptions &Opts) 8768 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8769 Triple.getOSName(), 8770 Triple.getEnvironmentName()), 8771 Opts) { 8772 IsRenderScriptTarget = true; 8773 } 8774 8775 void getTargetDefines(const LangOptions &Opts, 8776 MacroBuilder &Builder) const override { 8777 Builder.defineMacro("__RENDERSCRIPT__"); 8778 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8779 } 8780 }; 8781 8782 /// Information about a specific microcontroller. 8783 struct MCUInfo { 8784 const char *Name; 8785 const char *DefineName; 8786 }; 8787 8788 // This list should be kept up-to-date with AVRDevices.td in LLVM. 8789 static ArrayRef<MCUInfo> AVRMcus = { 8790 { "at90s1200", "__AVR_AT90S1200__" }, 8791 { "attiny11", "__AVR_ATtiny11__" }, 8792 { "attiny12", "__AVR_ATtiny12__" }, 8793 { "attiny15", "__AVR_ATtiny15__" }, 8794 { "attiny28", "__AVR_ATtiny28__" }, 8795 { "at90s2313", "__AVR_AT90S2313__" }, 8796 { "at90s2323", "__AVR_AT90S2323__" }, 8797 { "at90s2333", "__AVR_AT90S2333__" }, 8798 { "at90s2343", "__AVR_AT90S2343__" }, 8799 { "attiny22", "__AVR_ATtiny22__" }, 8800 { "attiny26", "__AVR_ATtiny26__" }, 8801 { "at86rf401", "__AVR_AT86RF401__" }, 8802 { "at90s4414", "__AVR_AT90S4414__" }, 8803 { "at90s4433", "__AVR_AT90S4433__" }, 8804 { "at90s4434", "__AVR_AT90S4434__" }, 8805 { "at90s8515", "__AVR_AT90S8515__" }, 8806 { "at90c8534", "__AVR_AT90c8534__" }, 8807 { "at90s8535", "__AVR_AT90S8535__" }, 8808 { "ata5272", "__AVR_ATA5272__" }, 8809 { "attiny13", "__AVR_ATtiny13__" }, 8810 { "attiny13a", "__AVR_ATtiny13A__" }, 8811 { "attiny2313", "__AVR_ATtiny2313__" }, 8812 { "attiny2313a", "__AVR_ATtiny2313A__" }, 8813 { "attiny24", "__AVR_ATtiny24__" }, 8814 { "attiny24a", "__AVR_ATtiny24A__" }, 8815 { "attiny4313", "__AVR_ATtiny4313__" }, 8816 { "attiny44", "__AVR_ATtiny44__" }, 8817 { "attiny44a", "__AVR_ATtiny44A__" }, 8818 { "attiny84", "__AVR_ATtiny84__" }, 8819 { "attiny84a", "__AVR_ATtiny84A__" }, 8820 { "attiny25", "__AVR_ATtiny25__" }, 8821 { "attiny45", "__AVR_ATtiny45__" }, 8822 { "attiny85", "__AVR_ATtiny85__" }, 8823 { "attiny261", "__AVR_ATtiny261__" }, 8824 { "attiny261a", "__AVR_ATtiny261A__" }, 8825 { "attiny461", "__AVR_ATtiny461__" }, 8826 { "attiny461a", "__AVR_ATtiny461A__" }, 8827 { "attiny861", "__AVR_ATtiny861__" }, 8828 { "attiny861a", "__AVR_ATtiny861A__" }, 8829 { "attiny87", "__AVR_ATtiny87__" }, 8830 { "attiny43u", "__AVR_ATtiny43U__" }, 8831 { "attiny48", "__AVR_ATtiny48__" }, 8832 { "attiny88", "__AVR_ATtiny88__" }, 8833 { "attiny828", "__AVR_ATtiny828__" }, 8834 { "at43usb355", "__AVR_AT43USB355__" }, 8835 { "at76c711", "__AVR_AT76C711__" }, 8836 { "atmega103", "__AVR_ATmega103__" }, 8837 { "at43usb320", "__AVR_AT43USB320__" }, 8838 { "attiny167", "__AVR_ATtiny167__" }, 8839 { "at90usb82", "__AVR_AT90USB82__" }, 8840 { "at90usb162", "__AVR_AT90USB162__" }, 8841 { "ata5505", "__AVR_ATA5505__" }, 8842 { "atmega8u2", "__AVR_ATmega8U2__" }, 8843 { "atmega16u2", "__AVR_ATmega16U2__" }, 8844 { "atmega32u2", "__AVR_ATmega32U2__" }, 8845 { "attiny1634", "__AVR_ATtiny1634__" }, 8846 { "atmega8", "__AVR_ATmega8__" }, 8847 { "ata6289", "__AVR_ATA6289__" }, 8848 { "atmega8a", "__AVR_ATmega8A__" }, 8849 { "ata6285", "__AVR_ATA6285__" }, 8850 { "ata6286", "__AVR_ATA6286__" }, 8851 { "atmega48", "__AVR_ATmega48__" }, 8852 { "atmega48a", "__AVR_ATmega48A__" }, 8853 { "atmega48pa", "__AVR_ATmega48PA__" }, 8854 { "atmega48p", "__AVR_ATmega48P__" }, 8855 { "atmega88", "__AVR_ATmega88__" }, 8856 { "atmega88a", "__AVR_ATmega88A__" }, 8857 { "atmega88p", "__AVR_ATmega88P__" }, 8858 { "atmega88pa", "__AVR_ATmega88PA__" }, 8859 { "atmega8515", "__AVR_ATmega8515__" }, 8860 { "atmega8535", "__AVR_ATmega8535__" }, 8861 { "atmega8hva", "__AVR_ATmega8HVA__" }, 8862 { "at90pwm1", "__AVR_AT90PWM1__" }, 8863 { "at90pwm2", "__AVR_AT90PWM2__" }, 8864 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 8865 { "at90pwm3", "__AVR_AT90PWM3__" }, 8866 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 8867 { "at90pwm81", "__AVR_AT90PWM81__" }, 8868 { "ata5790", "__AVR_ATA5790__" }, 8869 { "ata5795", "__AVR_ATA5795__" }, 8870 { "atmega16", "__AVR_ATmega16__" }, 8871 { "atmega16a", "__AVR_ATmega16A__" }, 8872 { "atmega161", "__AVR_ATmega161__" }, 8873 { "atmega162", "__AVR_ATmega162__" }, 8874 { "atmega163", "__AVR_ATmega163__" }, 8875 { "atmega164a", "__AVR_ATmega164A__" }, 8876 { "atmega164p", "__AVR_ATmega164P__" }, 8877 { "atmega164pa", "__AVR_ATmega164PA__" }, 8878 { "atmega165", "__AVR_ATmega165__" }, 8879 { "atmega165a", "__AVR_ATmega165A__" }, 8880 { "atmega165p", "__AVR_ATmega165P__" }, 8881 { "atmega165pa", "__AVR_ATmega165PA__" }, 8882 { "atmega168", "__AVR_ATmega168__" }, 8883 { "atmega168a", "__AVR_ATmega168A__" }, 8884 { "atmega168p", "__AVR_ATmega168P__" }, 8885 { "atmega168pa", "__AVR_ATmega168PA__" }, 8886 { "atmega169", "__AVR_ATmega169__" }, 8887 { "atmega169a", "__AVR_ATmega169A__" }, 8888 { "atmega169p", "__AVR_ATmega169P__" }, 8889 { "atmega169pa", "__AVR_ATmega169PA__" }, 8890 { "atmega32", "__AVR_ATmega32__" }, 8891 { "atmega32a", "__AVR_ATmega32A__" }, 8892 { "atmega323", "__AVR_ATmega323__" }, 8893 { "atmega324a", "__AVR_ATmega324A__" }, 8894 { "atmega324p", "__AVR_ATmega324P__" }, 8895 { "atmega324pa", "__AVR_ATmega324PA__" }, 8896 { "atmega325", "__AVR_ATmega325__" }, 8897 { "atmega325a", "__AVR_ATmega325A__" }, 8898 { "atmega325p", "__AVR_ATmega325P__" }, 8899 { "atmega325pa", "__AVR_ATmega325PA__" }, 8900 { "atmega3250", "__AVR_ATmega3250__" }, 8901 { "atmega3250a", "__AVR_ATmega3250A__" }, 8902 { "atmega3250p", "__AVR_ATmega3250P__" }, 8903 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 8904 { "atmega328", "__AVR_ATmega328__" }, 8905 { "atmega328p", "__AVR_ATmega328P__" }, 8906 { "atmega329", "__AVR_ATmega329__" }, 8907 { "atmega329a", "__AVR_ATmega329A__" }, 8908 { "atmega329p", "__AVR_ATmega329P__" }, 8909 { "atmega329pa", "__AVR_ATmega329PA__" }, 8910 { "atmega3290", "__AVR_ATmega3290__" }, 8911 { "atmega3290a", "__AVR_ATmega3290A__" }, 8912 { "atmega3290p", "__AVR_ATmega3290P__" }, 8913 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 8914 { "atmega406", "__AVR_ATmega406__" }, 8915 { "atmega64", "__AVR_ATmega64__" }, 8916 { "atmega64a", "__AVR_ATmega64A__" }, 8917 { "atmega640", "__AVR_ATmega640__" }, 8918 { "atmega644", "__AVR_ATmega644__" }, 8919 { "atmega644a", "__AVR_ATmega644A__" }, 8920 { "atmega644p", "__AVR_ATmega644P__" }, 8921 { "atmega644pa", "__AVR_ATmega644PA__" }, 8922 { "atmega645", "__AVR_ATmega645__" }, 8923 { "atmega645a", "__AVR_ATmega645A__" }, 8924 { "atmega645p", "__AVR_ATmega645P__" }, 8925 { "atmega649", "__AVR_ATmega649__" }, 8926 { "atmega649a", "__AVR_ATmega649A__" }, 8927 { "atmega649p", "__AVR_ATmega649P__" }, 8928 { "atmega6450", "__AVR_ATmega6450__" }, 8929 { "atmega6450a", "__AVR_ATmega6450A__" }, 8930 { "atmega6450p", "__AVR_ATmega6450P__" }, 8931 { "atmega6490", "__AVR_ATmega6490__" }, 8932 { "atmega6490a", "__AVR_ATmega6490A__" }, 8933 { "atmega6490p", "__AVR_ATmega6490P__" }, 8934 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 8935 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 8936 { "atmega16hva", "__AVR_ATmega16HVA__" }, 8937 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 8938 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 8939 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 8940 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 8941 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 8942 { "atmega64hve", "__AVR_ATmega64HVE__" }, 8943 { "at90can32", "__AVR_AT90CAN32__" }, 8944 { "at90can64", "__AVR_AT90CAN64__" }, 8945 { "at90pwm161", "__AVR_AT90PWM161__" }, 8946 { "at90pwm216", "__AVR_AT90PWM216__" }, 8947 { "at90pwm316", "__AVR_AT90PWM316__" }, 8948 { "atmega32c1", "__AVR_ATmega32C1__" }, 8949 { "atmega64c1", "__AVR_ATmega64C1__" }, 8950 { "atmega16m1", "__AVR_ATmega16M1__" }, 8951 { "atmega32m1", "__AVR_ATmega32M1__" }, 8952 { "atmega64m1", "__AVR_ATmega64M1__" }, 8953 { "atmega16u4", "__AVR_ATmega16U4__" }, 8954 { "atmega32u4", "__AVR_ATmega32U4__" }, 8955 { "atmega32u6", "__AVR_ATmega32U6__" }, 8956 { "at90usb646", "__AVR_AT90USB646__" }, 8957 { "at90usb647", "__AVR_AT90USB647__" }, 8958 { "at90scr100", "__AVR_AT90SCR100__" }, 8959 { "at94k", "__AVR_AT94K__" }, 8960 { "m3000", "__AVR_AT000__" }, 8961 { "atmega128", "__AVR_ATmega128__" }, 8962 { "atmega128a", "__AVR_ATmega128A__" }, 8963 { "atmega1280", "__AVR_ATmega1280__" }, 8964 { "atmega1281", "__AVR_ATmega1281__" }, 8965 { "atmega1284", "__AVR_ATmega1284__" }, 8966 { "atmega1284p", "__AVR_ATmega1284P__" }, 8967 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 8968 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 8969 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 8970 { "at90can128", "__AVR_AT90CAN128__" }, 8971 { "at90usb1286", "__AVR_AT90USB1286__" }, 8972 { "at90usb1287", "__AVR_AT90USB1287__" }, 8973 { "atmega2560", "__AVR_ATmega2560__" }, 8974 { "atmega2561", "__AVR_ATmega2561__" }, 8975 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 8976 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 8977 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 8978 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 8979 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 8980 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 8981 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 8982 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 8983 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 8984 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 8985 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 8986 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 8987 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 8988 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 8989 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 8990 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 8991 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 8992 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 8993 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 8994 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 8995 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 8996 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 8997 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 8998 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 8999 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 9000 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 9001 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 9002 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 9003 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 9004 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 9005 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 9006 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 9007 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 9008 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 9009 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 9010 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 9011 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 9012 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 9013 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 9014 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 9015 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 9016 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 9017 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 9018 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 9019 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 9020 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 9021 { "attiny4", "__AVR_ATtiny4__" }, 9022 { "attiny5", "__AVR_ATtiny5__" }, 9023 { "attiny9", "__AVR_ATtiny9__" }, 9024 { "attiny10", "__AVR_ATtiny10__" }, 9025 { "attiny20", "__AVR_ATtiny20__" }, 9026 { "attiny40", "__AVR_ATtiny40__" }, 9027 { "attiny102", "__AVR_ATtiny102__" }, 9028 { "attiny104", "__AVR_ATtiny104__" }, 9029 }; 9030 9031 // AVR Target 9032 class AVRTargetInfo : public TargetInfo { 9033 public: 9034 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 9035 : TargetInfo(Triple) { 9036 TLSSupported = false; 9037 PointerWidth = 16; 9038 PointerAlign = 8; 9039 IntWidth = 16; 9040 IntAlign = 8; 9041 LongWidth = 32; 9042 LongAlign = 8; 9043 LongLongWidth = 64; 9044 LongLongAlign = 8; 9045 SuitableAlign = 8; 9046 DefaultAlignForAttributeAligned = 8; 9047 HalfWidth = 16; 9048 HalfAlign = 8; 9049 FloatWidth = 32; 9050 FloatAlign = 8; 9051 DoubleWidth = 32; 9052 DoubleAlign = 8; 9053 DoubleFormat = &llvm::APFloat::IEEEsingle(); 9054 LongDoubleWidth = 32; 9055 LongDoubleAlign = 8; 9056 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 9057 SizeType = UnsignedInt; 9058 PtrDiffType = SignedInt; 9059 IntPtrType = SignedInt; 9060 Char16Type = UnsignedInt; 9061 WCharType = SignedInt; 9062 WIntType = SignedInt; 9063 Char32Type = UnsignedLong; 9064 SigAtomicType = SignedChar; 9065 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 9066 "-f32:32:32-f64:64:64-n8"); 9067 } 9068 9069 void getTargetDefines(const LangOptions &Opts, 9070 MacroBuilder &Builder) const override { 9071 Builder.defineMacro("AVR"); 9072 Builder.defineMacro("__AVR"); 9073 Builder.defineMacro("__AVR__"); 9074 9075 if (!this->CPU.empty()) { 9076 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9077 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 9078 9079 if (It != AVRMcus.end()) 9080 Builder.defineMacro(It->DefineName); 9081 } 9082 } 9083 9084 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 9085 return None; 9086 } 9087 9088 BuiltinVaListKind getBuiltinVaListKind() const override { 9089 return TargetInfo::VoidPtrBuiltinVaList; 9090 } 9091 9092 const char *getClobbers() const override { 9093 return ""; 9094 } 9095 9096 ArrayRef<const char *> getGCCRegNames() const override { 9097 static const char * const GCCRegNames[] = { 9098 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 9099 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 9100 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 9101 "r24", "r25", "X", "Y", "Z", "SP" 9102 }; 9103 return llvm::makeArrayRef(GCCRegNames); 9104 } 9105 9106 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 9107 return None; 9108 } 9109 9110 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 9111 static const TargetInfo::AddlRegName AddlRegNames[] = { 9112 { { "r26", "r27"}, 26 }, 9113 { { "r28", "r29"}, 27 }, 9114 { { "r30", "r31"}, 28 }, 9115 { { "SPL", "SPH"}, 29 }, 9116 }; 9117 return llvm::makeArrayRef(AddlRegNames); 9118 } 9119 9120 bool validateAsmConstraint(const char *&Name, 9121 TargetInfo::ConstraintInfo &Info) const override { 9122 // There aren't any multi-character AVR specific constraints. 9123 if (StringRef(Name).size() > 1) return false; 9124 9125 switch (*Name) { 9126 default: return false; 9127 case 'a': // Simple upper registers 9128 case 'b': // Base pointer registers pairs 9129 case 'd': // Upper register 9130 case 'l': // Lower registers 9131 case 'e': // Pointer register pairs 9132 case 'q': // Stack pointer register 9133 case 'r': // Any register 9134 case 'w': // Special upper register pairs 9135 case 't': // Temporary register 9136 case 'x': case 'X': // Pointer register pair X 9137 case 'y': case 'Y': // Pointer register pair Y 9138 case 'z': case 'Z': // Pointer register pair Z 9139 Info.setAllowsRegister(); 9140 return true; 9141 case 'I': // 6-bit positive integer constant 9142 Info.setRequiresImmediate(0, 63); 9143 return true; 9144 case 'J': // 6-bit negative integer constant 9145 Info.setRequiresImmediate(-63, 0); 9146 return true; 9147 case 'K': // Integer constant (Range: 2) 9148 Info.setRequiresImmediate(2); 9149 return true; 9150 case 'L': // Integer constant (Range: 0) 9151 Info.setRequiresImmediate(0); 9152 return true; 9153 case 'M': // 8-bit integer constant 9154 Info.setRequiresImmediate(0, 0xff); 9155 return true; 9156 case 'N': // Integer constant (Range: -1) 9157 Info.setRequiresImmediate(-1); 9158 return true; 9159 case 'O': // Integer constant (Range: 8, 16, 24) 9160 Info.setRequiresImmediate({8, 16, 24}); 9161 return true; 9162 case 'P': // Integer constant (Range: 1) 9163 Info.setRequiresImmediate(1); 9164 return true; 9165 case 'R': // Integer constant (Range: -6 to 5) 9166 Info.setRequiresImmediate(-6, 5); 9167 return true; 9168 case 'G': // Floating point constant 9169 case 'Q': // A memory address based on Y or Z pointer with displacement. 9170 return true; 9171 } 9172 9173 return false; 9174 } 9175 9176 IntType getIntTypeByWidth(unsigned BitWidth, 9177 bool IsSigned) const final { 9178 // AVR prefers int for 16-bit integers. 9179 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 9180 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 9181 } 9182 9183 IntType getLeastIntTypeByWidth(unsigned BitWidth, 9184 bool IsSigned) const final { 9185 // AVR uses int for int_least16_t and int_fast16_t. 9186 return BitWidth == 16 9187 ? (IsSigned ? SignedInt : UnsignedInt) 9188 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 9189 } 9190 9191 bool setCPU(const std::string &Name) override { 9192 bool IsFamily = llvm::StringSwitch<bool>(Name) 9193 .Case("avr1", true) 9194 .Case("avr2", true) 9195 .Case("avr25", true) 9196 .Case("avr3", true) 9197 .Case("avr31", true) 9198 .Case("avr35", true) 9199 .Case("avr4", true) 9200 .Case("avr5", true) 9201 .Case("avr51", true) 9202 .Case("avr6", true) 9203 .Case("avrxmega1", true) 9204 .Case("avrxmega2", true) 9205 .Case("avrxmega3", true) 9206 .Case("avrxmega4", true) 9207 .Case("avrxmega5", true) 9208 .Case("avrxmega6", true) 9209 .Case("avrxmega7", true) 9210 .Case("avrtiny", true) 9211 .Default(false); 9212 9213 if (IsFamily) this->CPU = Name; 9214 9215 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9216 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 9217 9218 if (IsMCU) this->CPU = Name; 9219 9220 return IsFamily || IsMCU; 9221 } 9222 9223 protected: 9224 std::string CPU; 9225 }; 9226 9227 } // end anonymous namespace 9228 9229 //===----------------------------------------------------------------------===// 9230 // Driver code 9231 //===----------------------------------------------------------------------===// 9232 9233 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 9234 const TargetOptions &Opts) { 9235 llvm::Triple::OSType os = Triple.getOS(); 9236 9237 switch (Triple.getArch()) { 9238 default: 9239 return nullptr; 9240 9241 case llvm::Triple::xcore: 9242 return new XCoreTargetInfo(Triple, Opts); 9243 9244 case llvm::Triple::hexagon: 9245 return new HexagonTargetInfo(Triple, Opts); 9246 9247 case llvm::Triple::lanai: 9248 return new LanaiTargetInfo(Triple, Opts); 9249 9250 case llvm::Triple::aarch64: 9251 if (Triple.isOSDarwin()) 9252 return new DarwinAArch64TargetInfo(Triple, Opts); 9253 9254 switch (os) { 9255 case llvm::Triple::CloudABI: 9256 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 9257 case llvm::Triple::FreeBSD: 9258 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9259 case llvm::Triple::Fuchsia: 9260 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9261 case llvm::Triple::Linux: 9262 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9263 case llvm::Triple::NetBSD: 9264 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9265 case llvm::Triple::OpenBSD: 9266 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9267 default: 9268 return new AArch64leTargetInfo(Triple, Opts); 9269 } 9270 9271 case llvm::Triple::aarch64_be: 9272 switch (os) { 9273 case llvm::Triple::FreeBSD: 9274 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9275 case llvm::Triple::Fuchsia: 9276 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9277 case llvm::Triple::Linux: 9278 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9279 case llvm::Triple::NetBSD: 9280 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9281 default: 9282 return new AArch64beTargetInfo(Triple, Opts); 9283 } 9284 9285 case llvm::Triple::arm: 9286 case llvm::Triple::thumb: 9287 if (Triple.isOSBinFormatMachO()) 9288 return new DarwinARMTargetInfo(Triple, Opts); 9289 9290 switch (os) { 9291 case llvm::Triple::CloudABI: 9292 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9293 case llvm::Triple::Linux: 9294 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9295 case llvm::Triple::FreeBSD: 9296 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9297 case llvm::Triple::NetBSD: 9298 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9299 case llvm::Triple::OpenBSD: 9300 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9301 case llvm::Triple::Bitrig: 9302 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9303 case llvm::Triple::RTEMS: 9304 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9305 case llvm::Triple::NaCl: 9306 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9307 case llvm::Triple::Win32: 9308 switch (Triple.getEnvironment()) { 9309 case llvm::Triple::Cygnus: 9310 return new CygwinARMTargetInfo(Triple, Opts); 9311 case llvm::Triple::GNU: 9312 return new MinGWARMTargetInfo(Triple, Opts); 9313 case llvm::Triple::Itanium: 9314 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9315 case llvm::Triple::MSVC: 9316 default: // Assume MSVC for unknown environments 9317 return new MicrosoftARMleTargetInfo(Triple, Opts); 9318 } 9319 default: 9320 return new ARMleTargetInfo(Triple, Opts); 9321 } 9322 9323 case llvm::Triple::armeb: 9324 case llvm::Triple::thumbeb: 9325 if (Triple.isOSDarwin()) 9326 return new DarwinARMTargetInfo(Triple, Opts); 9327 9328 switch (os) { 9329 case llvm::Triple::Linux: 9330 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9331 case llvm::Triple::FreeBSD: 9332 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9333 case llvm::Triple::NetBSD: 9334 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9335 case llvm::Triple::OpenBSD: 9336 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9337 case llvm::Triple::Bitrig: 9338 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9339 case llvm::Triple::RTEMS: 9340 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9341 case llvm::Triple::NaCl: 9342 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9343 default: 9344 return new ARMbeTargetInfo(Triple, Opts); 9345 } 9346 9347 case llvm::Triple::avr: 9348 return new AVRTargetInfo(Triple, Opts); 9349 case llvm::Triple::bpfeb: 9350 case llvm::Triple::bpfel: 9351 return new BPFTargetInfo(Triple, Opts); 9352 9353 case llvm::Triple::msp430: 9354 return new MSP430TargetInfo(Triple, Opts); 9355 9356 case llvm::Triple::mips: 9357 switch (os) { 9358 case llvm::Triple::Linux: 9359 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9360 case llvm::Triple::RTEMS: 9361 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9362 case llvm::Triple::FreeBSD: 9363 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9364 case llvm::Triple::NetBSD: 9365 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9366 default: 9367 return new MipsTargetInfo(Triple, Opts); 9368 } 9369 9370 case llvm::Triple::mipsel: 9371 switch (os) { 9372 case llvm::Triple::Linux: 9373 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9374 case llvm::Triple::RTEMS: 9375 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9376 case llvm::Triple::FreeBSD: 9377 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9378 case llvm::Triple::NetBSD: 9379 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9380 case llvm::Triple::NaCl: 9381 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9382 default: 9383 return new MipsTargetInfo(Triple, Opts); 9384 } 9385 9386 case llvm::Triple::mips64: 9387 switch (os) { 9388 case llvm::Triple::Linux: 9389 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9390 case llvm::Triple::RTEMS: 9391 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9392 case llvm::Triple::FreeBSD: 9393 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9394 case llvm::Triple::NetBSD: 9395 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9396 case llvm::Triple::OpenBSD: 9397 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9398 default: 9399 return new MipsTargetInfo(Triple, Opts); 9400 } 9401 9402 case llvm::Triple::mips64el: 9403 switch (os) { 9404 case llvm::Triple::Linux: 9405 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9406 case llvm::Triple::RTEMS: 9407 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9408 case llvm::Triple::FreeBSD: 9409 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9410 case llvm::Triple::NetBSD: 9411 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9412 case llvm::Triple::OpenBSD: 9413 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9414 default: 9415 return new MipsTargetInfo(Triple, Opts); 9416 } 9417 9418 case llvm::Triple::le32: 9419 switch (os) { 9420 case llvm::Triple::NaCl: 9421 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9422 default: 9423 return nullptr; 9424 } 9425 9426 case llvm::Triple::le64: 9427 return new Le64TargetInfo(Triple, Opts); 9428 9429 case llvm::Triple::ppc: 9430 if (Triple.isOSDarwin()) 9431 return new DarwinPPC32TargetInfo(Triple, Opts); 9432 switch (os) { 9433 case llvm::Triple::Linux: 9434 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9435 case llvm::Triple::FreeBSD: 9436 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9437 case llvm::Triple::NetBSD: 9438 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9439 case llvm::Triple::OpenBSD: 9440 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9441 case llvm::Triple::RTEMS: 9442 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9443 default: 9444 return new PPC32TargetInfo(Triple, Opts); 9445 } 9446 9447 case llvm::Triple::ppc64: 9448 if (Triple.isOSDarwin()) 9449 return new DarwinPPC64TargetInfo(Triple, Opts); 9450 switch (os) { 9451 case llvm::Triple::Linux: 9452 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9453 case llvm::Triple::Lv2: 9454 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9455 case llvm::Triple::FreeBSD: 9456 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9457 case llvm::Triple::NetBSD: 9458 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9459 default: 9460 return new PPC64TargetInfo(Triple, Opts); 9461 } 9462 9463 case llvm::Triple::ppc64le: 9464 switch (os) { 9465 case llvm::Triple::Linux: 9466 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9467 case llvm::Triple::NetBSD: 9468 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9469 default: 9470 return new PPC64TargetInfo(Triple, Opts); 9471 } 9472 9473 case llvm::Triple::nvptx: 9474 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9475 case llvm::Triple::nvptx64: 9476 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9477 9478 case llvm::Triple::amdgcn: 9479 case llvm::Triple::r600: 9480 return new AMDGPUTargetInfo(Triple, Opts); 9481 9482 case llvm::Triple::sparc: 9483 switch (os) { 9484 case llvm::Triple::Linux: 9485 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9486 case llvm::Triple::Solaris: 9487 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9488 case llvm::Triple::NetBSD: 9489 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9490 case llvm::Triple::OpenBSD: 9491 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9492 case llvm::Triple::RTEMS: 9493 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9494 default: 9495 return new SparcV8TargetInfo(Triple, Opts); 9496 } 9497 9498 // The 'sparcel' architecture copies all the above cases except for Solaris. 9499 case llvm::Triple::sparcel: 9500 switch (os) { 9501 case llvm::Triple::Linux: 9502 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9503 case llvm::Triple::NetBSD: 9504 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9505 case llvm::Triple::OpenBSD: 9506 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9507 case llvm::Triple::RTEMS: 9508 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9509 default: 9510 return new SparcV8elTargetInfo(Triple, Opts); 9511 } 9512 9513 case llvm::Triple::sparcv9: 9514 switch (os) { 9515 case llvm::Triple::Linux: 9516 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9517 case llvm::Triple::Solaris: 9518 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9519 case llvm::Triple::NetBSD: 9520 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9521 case llvm::Triple::OpenBSD: 9522 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9523 case llvm::Triple::FreeBSD: 9524 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9525 default: 9526 return new SparcV9TargetInfo(Triple, Opts); 9527 } 9528 9529 case llvm::Triple::systemz: 9530 switch (os) { 9531 case llvm::Triple::Linux: 9532 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9533 default: 9534 return new SystemZTargetInfo(Triple, Opts); 9535 } 9536 9537 case llvm::Triple::tce: 9538 return new TCETargetInfo(Triple, Opts); 9539 9540 case llvm::Triple::tcele: 9541 return new TCELETargetInfo(Triple, Opts); 9542 9543 case llvm::Triple::x86: 9544 if (Triple.isOSDarwin()) 9545 return new DarwinI386TargetInfo(Triple, Opts); 9546 9547 switch (os) { 9548 case llvm::Triple::Ananas: 9549 return new AnanasTargetInfo<X86_32TargetInfo>(Triple, Opts); 9550 case llvm::Triple::CloudABI: 9551 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9552 case llvm::Triple::Linux: { 9553 switch (Triple.getEnvironment()) { 9554 default: 9555 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9556 case llvm::Triple::Android: 9557 return new AndroidX86_32TargetInfo(Triple, Opts); 9558 } 9559 } 9560 case llvm::Triple::DragonFly: 9561 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9562 case llvm::Triple::NetBSD: 9563 return new NetBSDI386TargetInfo(Triple, Opts); 9564 case llvm::Triple::OpenBSD: 9565 return new OpenBSDI386TargetInfo(Triple, Opts); 9566 case llvm::Triple::Bitrig: 9567 return new BitrigI386TargetInfo(Triple, Opts); 9568 case llvm::Triple::FreeBSD: 9569 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9570 case llvm::Triple::KFreeBSD: 9571 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9572 case llvm::Triple::Minix: 9573 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9574 case llvm::Triple::Solaris: 9575 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9576 case llvm::Triple::Win32: { 9577 switch (Triple.getEnvironment()) { 9578 case llvm::Triple::Cygnus: 9579 return new CygwinX86_32TargetInfo(Triple, Opts); 9580 case llvm::Triple::GNU: 9581 return new MinGWX86_32TargetInfo(Triple, Opts); 9582 case llvm::Triple::Itanium: 9583 case llvm::Triple::MSVC: 9584 default: // Assume MSVC for unknown environments 9585 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9586 } 9587 } 9588 case llvm::Triple::Haiku: 9589 return new HaikuX86_32TargetInfo(Triple, Opts); 9590 case llvm::Triple::RTEMS: 9591 return new RTEMSX86_32TargetInfo(Triple, Opts); 9592 case llvm::Triple::NaCl: 9593 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9594 case llvm::Triple::ELFIAMCU: 9595 return new MCUX86_32TargetInfo(Triple, Opts); 9596 default: 9597 return new X86_32TargetInfo(Triple, Opts); 9598 } 9599 9600 case llvm::Triple::x86_64: 9601 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9602 return new DarwinX86_64TargetInfo(Triple, Opts); 9603 9604 switch (os) { 9605 case llvm::Triple::Ananas: 9606 return new AnanasTargetInfo<X86_64TargetInfo>(Triple, Opts); 9607 case llvm::Triple::CloudABI: 9608 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9609 case llvm::Triple::Linux: { 9610 switch (Triple.getEnvironment()) { 9611 default: 9612 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9613 case llvm::Triple::Android: 9614 return new AndroidX86_64TargetInfo(Triple, Opts); 9615 } 9616 } 9617 case llvm::Triple::DragonFly: 9618 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9619 case llvm::Triple::NetBSD: 9620 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9621 case llvm::Triple::OpenBSD: 9622 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9623 case llvm::Triple::Bitrig: 9624 return new BitrigX86_64TargetInfo(Triple, Opts); 9625 case llvm::Triple::FreeBSD: 9626 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9627 case llvm::Triple::Fuchsia: 9628 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9629 case llvm::Triple::KFreeBSD: 9630 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9631 case llvm::Triple::Solaris: 9632 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9633 case llvm::Triple::Win32: { 9634 switch (Triple.getEnvironment()) { 9635 case llvm::Triple::Cygnus: 9636 return new CygwinX86_64TargetInfo(Triple, Opts); 9637 case llvm::Triple::GNU: 9638 return new MinGWX86_64TargetInfo(Triple, Opts); 9639 case llvm::Triple::MSVC: 9640 default: // Assume MSVC for unknown environments 9641 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9642 } 9643 } 9644 case llvm::Triple::Haiku: 9645 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9646 case llvm::Triple::NaCl: 9647 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9648 case llvm::Triple::PS4: 9649 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9650 default: 9651 return new X86_64TargetInfo(Triple, Opts); 9652 } 9653 9654 case llvm::Triple::spir: { 9655 if (Triple.getOS() != llvm::Triple::UnknownOS || 9656 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9657 return nullptr; 9658 return new SPIR32TargetInfo(Triple, Opts); 9659 } 9660 case llvm::Triple::spir64: { 9661 if (Triple.getOS() != llvm::Triple::UnknownOS || 9662 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9663 return nullptr; 9664 return new SPIR64TargetInfo(Triple, Opts); 9665 } 9666 case llvm::Triple::wasm32: 9667 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9668 Triple.getVendor() != llvm::Triple::UnknownVendor || 9669 Triple.getOS() != llvm::Triple::UnknownOS || 9670 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9671 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9672 return nullptr; 9673 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9674 case llvm::Triple::wasm64: 9675 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9676 Triple.getVendor() != llvm::Triple::UnknownVendor || 9677 Triple.getOS() != llvm::Triple::UnknownOS || 9678 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9679 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9680 return nullptr; 9681 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9682 9683 case llvm::Triple::renderscript32: 9684 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9685 case llvm::Triple::renderscript64: 9686 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9687 } 9688 } 9689 9690 /// CreateTargetInfo - Return the target info object for the specified target 9691 /// options. 9692 TargetInfo * 9693 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9694 const std::shared_ptr<TargetOptions> &Opts) { 9695 llvm::Triple Triple(Opts->Triple); 9696 9697 // Construct the target 9698 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9699 if (!Target) { 9700 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9701 return nullptr; 9702 } 9703 Target->TargetOpts = Opts; 9704 9705 // Set the target CPU if specified. 9706 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9707 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9708 return nullptr; 9709 } 9710 9711 // Set the target ABI if specified. 9712 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 9713 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 9714 return nullptr; 9715 } 9716 9717 // Set the fp math unit. 9718 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 9719 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 9720 return nullptr; 9721 } 9722 9723 // Compute the default target features, we need the target to handle this 9724 // because features may have dependencies on one another. 9725 llvm::StringMap<bool> Features; 9726 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 9727 Opts->FeaturesAsWritten)) 9728 return nullptr; 9729 9730 // Add the features to the compile options. 9731 Opts->Features.clear(); 9732 for (const auto &F : Features) 9733 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 9734 9735 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 9736 return nullptr; 9737 9738 Target->setSupportedOpenCLOpts(); 9739 Target->setOpenCLExtensionOpts(); 9740 9741 if (!Target->validateTarget(Diags)) 9742 return nullptr; 9743 9744 return Target.release(); 9745 } 9746