1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 69 const TargetOptions &Opts); 70 71 //===----------------------------------------------------------------------===// 72 // Defines specific to certain operating systems. 73 //===----------------------------------------------------------------------===// 74 75 namespace { 76 template<typename TgtInfo> 77 class OSTargetInfo : public TgtInfo { 78 protected: 79 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 80 MacroBuilder &Builder) const=0; 81 public: 82 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 83 : TgtInfo(Triple, Opts) {} 84 void getTargetDefines(const LangOptions &Opts, 85 MacroBuilder &Builder) const override { 86 TgtInfo::getTargetDefines(Opts, Builder); 87 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 88 } 89 90 }; 91 92 // CloudABI Target 93 template <typename Target> 94 class CloudABITargetInfo : public OSTargetInfo<Target> { 95 protected: 96 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 97 MacroBuilder &Builder) const override { 98 Builder.defineMacro("__CloudABI__"); 99 Builder.defineMacro("__ELF__"); 100 101 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 102 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 103 Builder.defineMacro("__STDC_UTF_16__"); 104 Builder.defineMacro("__STDC_UTF_32__"); 105 } 106 107 public: 108 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 109 : OSTargetInfo<Target>(Triple, Opts) {} 110 }; 111 112 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 113 const llvm::Triple &Triple, 114 StringRef &PlatformName, 115 VersionTuple &PlatformMinVersion) { 116 Builder.defineMacro("__APPLE_CC__", "6000"); 117 Builder.defineMacro("__APPLE__"); 118 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 119 // AddressSanitizer doesn't play well with source fortification, which is on 120 // by default on Darwin. 121 if (Opts.Sanitize.has(SanitizerKind::Address)) 122 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 123 124 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 125 if (!Opts.ObjC1) { 126 // __weak is always defined, for use in blocks and with objc pointers. 127 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 128 Builder.defineMacro("__strong", ""); 129 Builder.defineMacro("__unsafe_unretained", ""); 130 } 131 132 if (Opts.Static) 133 Builder.defineMacro("__STATIC__"); 134 else 135 Builder.defineMacro("__DYNAMIC__"); 136 137 if (Opts.POSIXThreads) 138 Builder.defineMacro("_REENTRANT"); 139 140 // Get the platform type and version number from the triple. 141 unsigned Maj, Min, Rev; 142 if (Triple.isMacOSX()) { 143 Triple.getMacOSXVersion(Maj, Min, Rev); 144 PlatformName = "macos"; 145 } else { 146 Triple.getOSVersion(Maj, Min, Rev); 147 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 148 } 149 150 // If -target arch-pc-win32-macho option specified, we're 151 // generating code for Win32 ABI. No need to emit 152 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 153 if (PlatformName == "win32") { 154 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 155 return; 156 } 157 158 // Set the appropriate OS version define. 159 if (Triple.isiOS()) { 160 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 161 char Str[6]; 162 Str[0] = '0' + Maj; 163 Str[1] = '0' + (Min / 10); 164 Str[2] = '0' + (Min % 10); 165 Str[3] = '0' + (Rev / 10); 166 Str[4] = '0' + (Rev % 10); 167 Str[5] = '\0'; 168 if (Triple.isTvOS()) 169 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 170 else 171 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 172 Str); 173 174 } else if (Triple.isWatchOS()) { 175 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 176 char Str[6]; 177 Str[0] = '0' + Maj; 178 Str[1] = '0' + (Min / 10); 179 Str[2] = '0' + (Min % 10); 180 Str[3] = '0' + (Rev / 10); 181 Str[4] = '0' + (Rev % 10); 182 Str[5] = '\0'; 183 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 184 } else if (Triple.isMacOSX()) { 185 // Note that the Driver allows versions which aren't representable in the 186 // define (because we only get a single digit for the minor and micro 187 // revision numbers). So, we limit them to the maximum representable 188 // version. 189 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 190 char Str[7]; 191 if (Maj < 10 || (Maj == 10 && Min < 10)) { 192 Str[0] = '0' + (Maj / 10); 193 Str[1] = '0' + (Maj % 10); 194 Str[2] = '0' + std::min(Min, 9U); 195 Str[3] = '0' + std::min(Rev, 9U); 196 Str[4] = '\0'; 197 } else { 198 // Handle versions > 10.9. 199 Str[0] = '0' + (Maj / 10); 200 Str[1] = '0' + (Maj % 10); 201 Str[2] = '0' + (Min / 10); 202 Str[3] = '0' + (Min % 10); 203 Str[4] = '0' + (Rev / 10); 204 Str[5] = '0' + (Rev % 10); 205 Str[6] = '\0'; 206 } 207 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 208 } 209 210 // Tell users about the kernel if there is one. 211 if (Triple.isOSDarwin()) 212 Builder.defineMacro("__MACH__"); 213 214 // The Watch ABI uses Dwarf EH. 215 if(Triple.isWatchABI()) 216 Builder.defineMacro("__ARM_DWARF_EH__"); 217 218 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 219 } 220 221 template<typename Target> 222 class DarwinTargetInfo : public OSTargetInfo<Target> { 223 protected: 224 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 225 MacroBuilder &Builder) const override { 226 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 227 this->PlatformMinVersion); 228 } 229 230 public: 231 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 232 : OSTargetInfo<Target>(Triple, Opts) { 233 // By default, no TLS, and we whitelist permitted architecture/OS 234 // combinations. 235 this->TLSSupported = false; 236 237 if (Triple.isMacOSX()) 238 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 239 else if (Triple.isiOS()) { 240 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 241 if (Triple.getArch() == llvm::Triple::x86_64 || 242 Triple.getArch() == llvm::Triple::aarch64) 243 this->TLSSupported = !Triple.isOSVersionLT(8); 244 else if (Triple.getArch() == llvm::Triple::x86 || 245 Triple.getArch() == llvm::Triple::arm || 246 Triple.getArch() == llvm::Triple::thumb) 247 this->TLSSupported = !Triple.isOSVersionLT(9); 248 } else if (Triple.isWatchOS()) 249 this->TLSSupported = !Triple.isOSVersionLT(2); 250 251 this->MCountName = "\01mcount"; 252 } 253 254 std::string isValidSectionSpecifier(StringRef SR) const override { 255 // Let MCSectionMachO validate this. 256 StringRef Segment, Section; 257 unsigned TAA, StubSize; 258 bool HasTAA; 259 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 260 TAA, HasTAA, StubSize); 261 } 262 263 const char *getStaticInitSectionSpecifier() const override { 264 // FIXME: We should return 0 when building kexts. 265 return "__TEXT,__StaticInit,regular,pure_instructions"; 266 } 267 268 /// Darwin does not support protected visibility. Darwin's "default" 269 /// is very similar to ELF's "protected"; Darwin requires a "weak" 270 /// attribute on declarations that can be dynamically replaced. 271 bool hasProtectedVisibility() const override { 272 return false; 273 } 274 275 unsigned getExnObjectAlignment() const override { 276 // The alignment of an exception object is 8-bytes for darwin since 277 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 278 // and therefore doesn't guarantee 16-byte alignment. 279 return 64; 280 } 281 }; 282 283 284 // DragonFlyBSD Target 285 template<typename Target> 286 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 287 protected: 288 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 289 MacroBuilder &Builder) const override { 290 // DragonFly defines; list based off of gcc output 291 Builder.defineMacro("__DragonFly__"); 292 Builder.defineMacro("__DragonFly_cc_version", "100001"); 293 Builder.defineMacro("__ELF__"); 294 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 295 Builder.defineMacro("__tune_i386__"); 296 DefineStd(Builder, "unix", Opts); 297 } 298 public: 299 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 300 : OSTargetInfo<Target>(Triple, Opts) { 301 switch (Triple.getArch()) { 302 default: 303 case llvm::Triple::x86: 304 case llvm::Triple::x86_64: 305 this->MCountName = ".mcount"; 306 break; 307 } 308 } 309 }; 310 311 #ifndef FREEBSD_CC_VERSION 312 #define FREEBSD_CC_VERSION 0U 313 #endif 314 315 // FreeBSD Target 316 template<typename Target> 317 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 318 protected: 319 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 320 MacroBuilder &Builder) const override { 321 // FreeBSD defines; list based off of gcc output 322 323 unsigned Release = Triple.getOSMajorVersion(); 324 if (Release == 0U) 325 Release = 8U; 326 unsigned CCVersion = FREEBSD_CC_VERSION; 327 if (CCVersion == 0U) 328 CCVersion = Release * 100000U + 1U; 329 330 Builder.defineMacro("__FreeBSD__", Twine(Release)); 331 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 332 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 333 DefineStd(Builder, "unix", Opts); 334 Builder.defineMacro("__ELF__"); 335 336 // On FreeBSD, wchar_t contains the number of the code point as 337 // used by the character set of the locale. These character sets are 338 // not necessarily a superset of ASCII. 339 // 340 // FIXME: This is wrong; the macro refers to the numerical values 341 // of wchar_t *literals*, which are not locale-dependent. However, 342 // FreeBSD systems apparently depend on us getting this wrong, and 343 // setting this to 1 is conforming even if all the basic source 344 // character literals have the same encoding as char and wchar_t. 345 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 346 } 347 public: 348 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 349 : OSTargetInfo<Target>(Triple, Opts) { 350 switch (Triple.getArch()) { 351 default: 352 case llvm::Triple::x86: 353 case llvm::Triple::x86_64: 354 this->MCountName = ".mcount"; 355 break; 356 case llvm::Triple::mips: 357 case llvm::Triple::mipsel: 358 case llvm::Triple::ppc: 359 case llvm::Triple::ppc64: 360 case llvm::Triple::ppc64le: 361 this->MCountName = "_mcount"; 362 break; 363 case llvm::Triple::arm: 364 this->MCountName = "__mcount"; 365 break; 366 } 367 } 368 }; 369 370 // GNU/kFreeBSD Target 371 template<typename Target> 372 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 373 protected: 374 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 375 MacroBuilder &Builder) const override { 376 // GNU/kFreeBSD defines; list based off of gcc output 377 378 DefineStd(Builder, "unix", Opts); 379 Builder.defineMacro("__FreeBSD_kernel__"); 380 Builder.defineMacro("__GLIBC__"); 381 Builder.defineMacro("__ELF__"); 382 if (Opts.POSIXThreads) 383 Builder.defineMacro("_REENTRANT"); 384 if (Opts.CPlusPlus) 385 Builder.defineMacro("_GNU_SOURCE"); 386 } 387 public: 388 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 389 : OSTargetInfo<Target>(Triple, Opts) {} 390 }; 391 392 // Haiku Target 393 template<typename Target> 394 class HaikuTargetInfo : public OSTargetInfo<Target> { 395 protected: 396 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 397 MacroBuilder &Builder) const override { 398 // Haiku defines; list based off of gcc output 399 Builder.defineMacro("__HAIKU__"); 400 Builder.defineMacro("__ELF__"); 401 DefineStd(Builder, "unix", Opts); 402 } 403 public: 404 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 405 : OSTargetInfo<Target>(Triple, Opts) { 406 this->SizeType = TargetInfo::UnsignedLong; 407 this->IntPtrType = TargetInfo::SignedLong; 408 this->PtrDiffType = TargetInfo::SignedLong; 409 this->ProcessIDType = TargetInfo::SignedLong; 410 this->TLSSupported = false; 411 412 } 413 }; 414 415 // Minix Target 416 template<typename Target> 417 class MinixTargetInfo : public OSTargetInfo<Target> { 418 protected: 419 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 420 MacroBuilder &Builder) const override { 421 // Minix defines 422 423 Builder.defineMacro("__minix", "3"); 424 Builder.defineMacro("_EM_WSIZE", "4"); 425 Builder.defineMacro("_EM_PSIZE", "4"); 426 Builder.defineMacro("_EM_SSIZE", "2"); 427 Builder.defineMacro("_EM_LSIZE", "4"); 428 Builder.defineMacro("_EM_FSIZE", "4"); 429 Builder.defineMacro("_EM_DSIZE", "8"); 430 Builder.defineMacro("__ELF__"); 431 DefineStd(Builder, "unix", Opts); 432 } 433 public: 434 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 435 : OSTargetInfo<Target>(Triple, Opts) {} 436 }; 437 438 // Linux target 439 template<typename Target> 440 class LinuxTargetInfo : public OSTargetInfo<Target> { 441 protected: 442 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 443 MacroBuilder &Builder) const override { 444 // Linux defines; list based off of gcc output 445 DefineStd(Builder, "unix", Opts); 446 DefineStd(Builder, "linux", Opts); 447 Builder.defineMacro("__gnu_linux__"); 448 Builder.defineMacro("__ELF__"); 449 if (Triple.isAndroid()) { 450 Builder.defineMacro("__ANDROID__", "1"); 451 unsigned Maj, Min, Rev; 452 Triple.getEnvironmentVersion(Maj, Min, Rev); 453 this->PlatformName = "android"; 454 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 455 } 456 if (Opts.POSIXThreads) 457 Builder.defineMacro("_REENTRANT"); 458 if (Opts.CPlusPlus) 459 Builder.defineMacro("_GNU_SOURCE"); 460 if (this->HasFloat128) 461 Builder.defineMacro("__FLOAT128__"); 462 } 463 public: 464 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 465 : OSTargetInfo<Target>(Triple, Opts) { 466 this->WIntType = TargetInfo::UnsignedInt; 467 468 switch (Triple.getArch()) { 469 default: 470 break; 471 case llvm::Triple::ppc: 472 case llvm::Triple::ppc64: 473 case llvm::Triple::ppc64le: 474 this->MCountName = "_mcount"; 475 break; 476 case llvm::Triple::x86: 477 case llvm::Triple::x86_64: 478 case llvm::Triple::systemz: 479 this->HasFloat128 = true; 480 break; 481 } 482 } 483 484 const char *getStaticInitSectionSpecifier() const override { 485 return ".text.startup"; 486 } 487 }; 488 489 // NetBSD Target 490 template<typename Target> 491 class NetBSDTargetInfo : public OSTargetInfo<Target> { 492 protected: 493 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 494 MacroBuilder &Builder) const override { 495 // NetBSD defines; list based off of gcc output 496 Builder.defineMacro("__NetBSD__"); 497 Builder.defineMacro("__unix__"); 498 Builder.defineMacro("__ELF__"); 499 if (Opts.POSIXThreads) 500 Builder.defineMacro("_POSIX_THREADS"); 501 502 switch (Triple.getArch()) { 503 default: 504 break; 505 case llvm::Triple::arm: 506 case llvm::Triple::armeb: 507 case llvm::Triple::thumb: 508 case llvm::Triple::thumbeb: 509 Builder.defineMacro("__ARM_DWARF_EH__"); 510 break; 511 } 512 } 513 public: 514 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 515 : OSTargetInfo<Target>(Triple, Opts) { 516 this->MCountName = "_mcount"; 517 } 518 }; 519 520 // OpenBSD Target 521 template<typename Target> 522 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 523 protected: 524 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 525 MacroBuilder &Builder) const override { 526 // OpenBSD defines; list based off of gcc output 527 528 Builder.defineMacro("__OpenBSD__"); 529 DefineStd(Builder, "unix", Opts); 530 Builder.defineMacro("__ELF__"); 531 if (Opts.POSIXThreads) 532 Builder.defineMacro("_REENTRANT"); 533 } 534 public: 535 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 536 : OSTargetInfo<Target>(Triple, Opts) { 537 this->TLSSupported = false; 538 539 switch (Triple.getArch()) { 540 default: 541 case llvm::Triple::x86: 542 case llvm::Triple::x86_64: 543 case llvm::Triple::arm: 544 case llvm::Triple::sparc: 545 this->MCountName = "__mcount"; 546 break; 547 case llvm::Triple::mips64: 548 case llvm::Triple::mips64el: 549 case llvm::Triple::ppc: 550 case llvm::Triple::sparcv9: 551 this->MCountName = "_mcount"; 552 break; 553 } 554 } 555 }; 556 557 // Bitrig Target 558 template<typename Target> 559 class BitrigTargetInfo : public OSTargetInfo<Target> { 560 protected: 561 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 562 MacroBuilder &Builder) const override { 563 // Bitrig defines; list based off of gcc output 564 565 Builder.defineMacro("__Bitrig__"); 566 DefineStd(Builder, "unix", Opts); 567 Builder.defineMacro("__ELF__"); 568 if (Opts.POSIXThreads) 569 Builder.defineMacro("_REENTRANT"); 570 571 switch (Triple.getArch()) { 572 default: 573 break; 574 case llvm::Triple::arm: 575 case llvm::Triple::armeb: 576 case llvm::Triple::thumb: 577 case llvm::Triple::thumbeb: 578 Builder.defineMacro("__ARM_DWARF_EH__"); 579 break; 580 } 581 } 582 public: 583 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 584 : OSTargetInfo<Target>(Triple, Opts) { 585 this->MCountName = "__mcount"; 586 } 587 }; 588 589 // PSP Target 590 template<typename Target> 591 class PSPTargetInfo : public OSTargetInfo<Target> { 592 protected: 593 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 594 MacroBuilder &Builder) const override { 595 // PSP defines; list based on the output of the pspdev gcc toolchain. 596 Builder.defineMacro("PSP"); 597 Builder.defineMacro("_PSP"); 598 Builder.defineMacro("__psp__"); 599 Builder.defineMacro("__ELF__"); 600 } 601 public: 602 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 603 }; 604 605 // PS3 PPU Target 606 template<typename Target> 607 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 608 protected: 609 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 610 MacroBuilder &Builder) const override { 611 // PS3 PPU defines. 612 Builder.defineMacro("__PPC__"); 613 Builder.defineMacro("__PPU__"); 614 Builder.defineMacro("__CELLOS_LV2__"); 615 Builder.defineMacro("__ELF__"); 616 Builder.defineMacro("__LP32__"); 617 Builder.defineMacro("_ARCH_PPC64"); 618 Builder.defineMacro("__powerpc64__"); 619 } 620 public: 621 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 622 : OSTargetInfo<Target>(Triple, Opts) { 623 this->LongWidth = this->LongAlign = 32; 624 this->PointerWidth = this->PointerAlign = 32; 625 this->IntMaxType = TargetInfo::SignedLongLong; 626 this->Int64Type = TargetInfo::SignedLongLong; 627 this->SizeType = TargetInfo::UnsignedInt; 628 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 629 } 630 }; 631 632 template <typename Target> 633 class PS4OSTargetInfo : public OSTargetInfo<Target> { 634 protected: 635 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 636 MacroBuilder &Builder) const override { 637 Builder.defineMacro("__FreeBSD__", "9"); 638 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 639 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 640 DefineStd(Builder, "unix", Opts); 641 Builder.defineMacro("__ELF__"); 642 Builder.defineMacro("__ORBIS__"); 643 } 644 public: 645 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 646 : OSTargetInfo<Target>(Triple, Opts) { 647 this->WCharType = this->UnsignedShort; 648 649 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 650 this->MaxTLSAlign = 256; 651 652 // On PS4, do not honor explicit bit field alignment, 653 // as in "__attribute__((aligned(2))) int b : 1;". 654 this->UseExplicitBitFieldAlignment = false; 655 656 switch (Triple.getArch()) { 657 default: 658 case llvm::Triple::x86_64: 659 this->MCountName = ".mcount"; 660 break; 661 } 662 } 663 }; 664 665 // Solaris target 666 template<typename Target> 667 class SolarisTargetInfo : public OSTargetInfo<Target> { 668 protected: 669 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 670 MacroBuilder &Builder) const override { 671 DefineStd(Builder, "sun", Opts); 672 DefineStd(Builder, "unix", Opts); 673 Builder.defineMacro("__ELF__"); 674 Builder.defineMacro("__svr4__"); 675 Builder.defineMacro("__SVR4"); 676 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 677 // newer, but to 500 for everything else. feature_test.h has a check to 678 // ensure that you are not using C99 with an old version of X/Open or C89 679 // with a new version. 680 if (Opts.C99) 681 Builder.defineMacro("_XOPEN_SOURCE", "600"); 682 else 683 Builder.defineMacro("_XOPEN_SOURCE", "500"); 684 if (Opts.CPlusPlus) 685 Builder.defineMacro("__C99FEATURES__"); 686 Builder.defineMacro("_LARGEFILE_SOURCE"); 687 Builder.defineMacro("_LARGEFILE64_SOURCE"); 688 Builder.defineMacro("__EXTENSIONS__"); 689 Builder.defineMacro("_REENTRANT"); 690 } 691 public: 692 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 693 : OSTargetInfo<Target>(Triple, Opts) { 694 this->WCharType = this->SignedInt; 695 // FIXME: WIntType should be SignedLong 696 } 697 }; 698 699 // Windows target 700 template<typename Target> 701 class WindowsTargetInfo : public OSTargetInfo<Target> { 702 protected: 703 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 704 MacroBuilder &Builder) const override { 705 Builder.defineMacro("_WIN32"); 706 } 707 void getVisualStudioDefines(const LangOptions &Opts, 708 MacroBuilder &Builder) const { 709 if (Opts.CPlusPlus) { 710 if (Opts.RTTIData) 711 Builder.defineMacro("_CPPRTTI"); 712 713 if (Opts.CXXExceptions) 714 Builder.defineMacro("_CPPUNWIND"); 715 } 716 717 if (Opts.Bool) 718 Builder.defineMacro("__BOOL_DEFINED"); 719 720 if (!Opts.CharIsSigned) 721 Builder.defineMacro("_CHAR_UNSIGNED"); 722 723 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 724 // but it works for now. 725 if (Opts.POSIXThreads) 726 Builder.defineMacro("_MT"); 727 728 if (Opts.MSCompatibilityVersion) { 729 Builder.defineMacro("_MSC_VER", 730 Twine(Opts.MSCompatibilityVersion / 100000)); 731 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 732 // FIXME We cannot encode the revision information into 32-bits 733 Builder.defineMacro("_MSC_BUILD", Twine(1)); 734 735 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 736 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 737 738 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 739 if (Opts.CPlusPlus1z) 740 Builder.defineMacro("_MSVC_LANG", "201403L"); 741 else if (Opts.CPlusPlus14) 742 Builder.defineMacro("_MSVC_LANG", "201402L"); 743 } 744 } 745 746 if (Opts.MicrosoftExt) { 747 Builder.defineMacro("_MSC_EXTENSIONS"); 748 749 if (Opts.CPlusPlus11) { 750 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 751 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 752 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 753 } 754 } 755 756 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 757 } 758 759 public: 760 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 761 : OSTargetInfo<Target>(Triple, Opts) {} 762 }; 763 764 template <typename Target> 765 class NaClTargetInfo : public OSTargetInfo<Target> { 766 protected: 767 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 768 MacroBuilder &Builder) const override { 769 if (Opts.POSIXThreads) 770 Builder.defineMacro("_REENTRANT"); 771 if (Opts.CPlusPlus) 772 Builder.defineMacro("_GNU_SOURCE"); 773 774 DefineStd(Builder, "unix", Opts); 775 Builder.defineMacro("__ELF__"); 776 Builder.defineMacro("__native_client__"); 777 } 778 779 public: 780 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 781 : OSTargetInfo<Target>(Triple, Opts) { 782 this->LongAlign = 32; 783 this->LongWidth = 32; 784 this->PointerAlign = 32; 785 this->PointerWidth = 32; 786 this->IntMaxType = TargetInfo::SignedLongLong; 787 this->Int64Type = TargetInfo::SignedLongLong; 788 this->DoubleAlign = 64; 789 this->LongDoubleWidth = 64; 790 this->LongDoubleAlign = 64; 791 this->LongLongWidth = 64; 792 this->LongLongAlign = 64; 793 this->SizeType = TargetInfo::UnsignedInt; 794 this->PtrDiffType = TargetInfo::SignedInt; 795 this->IntPtrType = TargetInfo::SignedInt; 796 // RegParmMax is inherited from the underlying architecture 797 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 798 if (Triple.getArch() == llvm::Triple::arm) { 799 // Handled in ARM's setABI(). 800 } else if (Triple.getArch() == llvm::Triple::x86) { 801 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 802 } else if (Triple.getArch() == llvm::Triple::x86_64) { 803 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 804 } else if (Triple.getArch() == llvm::Triple::mipsel) { 805 // Handled on mips' setDataLayout. 806 } else { 807 assert(Triple.getArch() == llvm::Triple::le32); 808 this->resetDataLayout("e-p:32:32-i64:64"); 809 } 810 } 811 }; 812 813 // WebAssembly target 814 template <typename Target> 815 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 816 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 817 MacroBuilder &Builder) const final { 818 // A common platform macro. 819 if (Opts.POSIXThreads) 820 Builder.defineMacro("_REENTRANT"); 821 // Follow g++ convention and predefine _GNU_SOURCE for C++. 822 if (Opts.CPlusPlus) 823 Builder.defineMacro("_GNU_SOURCE"); 824 } 825 826 // As an optimization, group static init code together in a section. 827 const char *getStaticInitSectionSpecifier() const final { 828 return ".text.__startup"; 829 } 830 831 public: 832 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 833 const TargetOptions &Opts) 834 : OSTargetInfo<Target>(Triple, Opts) { 835 this->MCountName = "__mcount"; 836 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 837 } 838 }; 839 840 //===----------------------------------------------------------------------===// 841 // Specific target implementations. 842 //===----------------------------------------------------------------------===// 843 844 // PPC abstract base class 845 class PPCTargetInfo : public TargetInfo { 846 static const Builtin::Info BuiltinInfo[]; 847 static const char * const GCCRegNames[]; 848 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 849 std::string CPU; 850 851 // Target cpu features. 852 bool HasVSX; 853 bool HasP8Vector; 854 bool HasP8Crypto; 855 bool HasDirectMove; 856 bool HasQPX; 857 bool HasHTM; 858 bool HasBPERMD; 859 bool HasExtDiv; 860 861 protected: 862 std::string ABI; 863 864 public: 865 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 866 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 867 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 868 HasBPERMD(false), HasExtDiv(false) { 869 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 870 SimdDefaultAlign = 128; 871 LongDoubleWidth = LongDoubleAlign = 128; 872 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 873 } 874 875 /// \brief Flags for architecture specific defines. 876 typedef enum { 877 ArchDefineNone = 0, 878 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 879 ArchDefinePpcgr = 1 << 1, 880 ArchDefinePpcsq = 1 << 2, 881 ArchDefine440 = 1 << 3, 882 ArchDefine603 = 1 << 4, 883 ArchDefine604 = 1 << 5, 884 ArchDefinePwr4 = 1 << 6, 885 ArchDefinePwr5 = 1 << 7, 886 ArchDefinePwr5x = 1 << 8, 887 ArchDefinePwr6 = 1 << 9, 888 ArchDefinePwr6x = 1 << 10, 889 ArchDefinePwr7 = 1 << 11, 890 ArchDefinePwr8 = 1 << 12, 891 ArchDefinePwr9 = 1 << 13, 892 ArchDefineA2 = 1 << 14, 893 ArchDefineA2q = 1 << 15 894 } ArchDefineTypes; 895 896 // Note: GCC recognizes the following additional cpus: 897 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 898 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 899 // titan, rs64. 900 bool setCPU(const std::string &Name) override { 901 bool CPUKnown = llvm::StringSwitch<bool>(Name) 902 .Case("generic", true) 903 .Case("440", true) 904 .Case("450", true) 905 .Case("601", true) 906 .Case("602", true) 907 .Case("603", true) 908 .Case("603e", true) 909 .Case("603ev", true) 910 .Case("604", true) 911 .Case("604e", true) 912 .Case("620", true) 913 .Case("630", true) 914 .Case("g3", true) 915 .Case("7400", true) 916 .Case("g4", true) 917 .Case("7450", true) 918 .Case("g4+", true) 919 .Case("750", true) 920 .Case("970", true) 921 .Case("g5", true) 922 .Case("a2", true) 923 .Case("a2q", true) 924 .Case("e500mc", true) 925 .Case("e5500", true) 926 .Case("power3", true) 927 .Case("pwr3", true) 928 .Case("power4", true) 929 .Case("pwr4", true) 930 .Case("power5", true) 931 .Case("pwr5", true) 932 .Case("power5x", true) 933 .Case("pwr5x", true) 934 .Case("power6", true) 935 .Case("pwr6", true) 936 .Case("power6x", true) 937 .Case("pwr6x", true) 938 .Case("power7", true) 939 .Case("pwr7", true) 940 .Case("power8", true) 941 .Case("pwr8", true) 942 .Case("power9", true) 943 .Case("pwr9", true) 944 .Case("powerpc", true) 945 .Case("ppc", true) 946 .Case("powerpc64", true) 947 .Case("ppc64", true) 948 .Case("powerpc64le", true) 949 .Case("ppc64le", true) 950 .Default(false); 951 952 if (CPUKnown) 953 CPU = Name; 954 955 return CPUKnown; 956 } 957 958 959 StringRef getABI() const override { return ABI; } 960 961 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 962 return llvm::makeArrayRef(BuiltinInfo, 963 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 964 } 965 966 bool isCLZForZeroUndef() const override { return false; } 967 968 void getTargetDefines(const LangOptions &Opts, 969 MacroBuilder &Builder) const override; 970 971 bool 972 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 973 StringRef CPU, 974 const std::vector<std::string> &FeaturesVec) const override; 975 976 bool handleTargetFeatures(std::vector<std::string> &Features, 977 DiagnosticsEngine &Diags) override; 978 bool hasFeature(StringRef Feature) const override; 979 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 980 bool Enabled) const override; 981 982 ArrayRef<const char *> getGCCRegNames() const override; 983 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 984 bool validateAsmConstraint(const char *&Name, 985 TargetInfo::ConstraintInfo &Info) const override { 986 switch (*Name) { 987 default: return false; 988 case 'O': // Zero 989 break; 990 case 'b': // Base register 991 case 'f': // Floating point register 992 Info.setAllowsRegister(); 993 break; 994 // FIXME: The following are added to allow parsing. 995 // I just took a guess at what the actions should be. 996 // Also, is more specific checking needed? I.e. specific registers? 997 case 'd': // Floating point register (containing 64-bit value) 998 case 'v': // Altivec vector register 999 Info.setAllowsRegister(); 1000 break; 1001 case 'w': 1002 switch (Name[1]) { 1003 case 'd':// VSX vector register to hold vector double data 1004 case 'f':// VSX vector register to hold vector float data 1005 case 's':// VSX vector register to hold scalar float data 1006 case 'a':// Any VSX register 1007 case 'c':// An individual CR bit 1008 break; 1009 default: 1010 return false; 1011 } 1012 Info.setAllowsRegister(); 1013 Name++; // Skip over 'w'. 1014 break; 1015 case 'h': // `MQ', `CTR', or `LINK' register 1016 case 'q': // `MQ' register 1017 case 'c': // `CTR' register 1018 case 'l': // `LINK' register 1019 case 'x': // `CR' register (condition register) number 0 1020 case 'y': // `CR' register (condition register) 1021 case 'z': // `XER[CA]' carry bit (part of the XER register) 1022 Info.setAllowsRegister(); 1023 break; 1024 case 'I': // Signed 16-bit constant 1025 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1026 // (use `L' instead for SImode constants) 1027 case 'K': // Unsigned 16-bit constant 1028 case 'L': // Signed 16-bit constant shifted left 16 bits 1029 case 'M': // Constant larger than 31 1030 case 'N': // Exact power of 2 1031 case 'P': // Constant whose negation is a signed 16-bit constant 1032 case 'G': // Floating point constant that can be loaded into a 1033 // register with one instruction per word 1034 case 'H': // Integer/Floating point constant that can be loaded 1035 // into a register using three instructions 1036 break; 1037 case 'm': // Memory operand. Note that on PowerPC targets, m can 1038 // include addresses that update the base register. It 1039 // is therefore only safe to use `m' in an asm statement 1040 // if that asm statement accesses the operand exactly once. 1041 // The asm statement must also use `%U<opno>' as a 1042 // placeholder for the "update" flag in the corresponding 1043 // load or store instruction. For example: 1044 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1045 // is correct but: 1046 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1047 // is not. Use es rather than m if you don't want the base 1048 // register to be updated. 1049 case 'e': 1050 if (Name[1] != 's') 1051 return false; 1052 // es: A "stable" memory operand; that is, one which does not 1053 // include any automodification of the base register. Unlike 1054 // `m', this constraint can be used in asm statements that 1055 // might access the operand several times, or that might not 1056 // access it at all. 1057 Info.setAllowsMemory(); 1058 Name++; // Skip over 'e'. 1059 break; 1060 case 'Q': // Memory operand that is an offset from a register (it is 1061 // usually better to use `m' or `es' in asm statements) 1062 case 'Z': // Memory operand that is an indexed or indirect from a 1063 // register (it is usually better to use `m' or `es' in 1064 // asm statements) 1065 Info.setAllowsMemory(); 1066 Info.setAllowsRegister(); 1067 break; 1068 case 'R': // AIX TOC entry 1069 case 'a': // Address operand that is an indexed or indirect from a 1070 // register (`p' is preferable for asm statements) 1071 case 'S': // Constant suitable as a 64-bit mask operand 1072 case 'T': // Constant suitable as a 32-bit mask operand 1073 case 'U': // System V Release 4 small data area reference 1074 case 't': // AND masks that can be performed by two rldic{l, r} 1075 // instructions 1076 case 'W': // Vector constant that does not require memory 1077 case 'j': // Vector constant that is all zeros. 1078 break; 1079 // End FIXME. 1080 } 1081 return true; 1082 } 1083 std::string convertConstraint(const char *&Constraint) const override { 1084 std::string R; 1085 switch (*Constraint) { 1086 case 'e': 1087 case 'w': 1088 // Two-character constraint; add "^" hint for later parsing. 1089 R = std::string("^") + std::string(Constraint, 2); 1090 Constraint++; 1091 break; 1092 default: 1093 return TargetInfo::convertConstraint(Constraint); 1094 } 1095 return R; 1096 } 1097 const char *getClobbers() const override { 1098 return ""; 1099 } 1100 int getEHDataRegisterNumber(unsigned RegNo) const override { 1101 if (RegNo == 0) return 3; 1102 if (RegNo == 1) return 4; 1103 return -1; 1104 } 1105 1106 bool hasSjLjLowering() const override { 1107 return true; 1108 } 1109 1110 bool useFloat128ManglingForLongDouble() const override { 1111 return LongDoubleWidth == 128 && 1112 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1113 getTriple().isOSBinFormatELF(); 1114 } 1115 }; 1116 1117 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1118 #define BUILTIN(ID, TYPE, ATTRS) \ 1119 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1120 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1121 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1122 #include "clang/Basic/BuiltinsPPC.def" 1123 }; 1124 1125 /// handleTargetFeatures - Perform initialization based on the user 1126 /// configured set of features. 1127 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1128 DiagnosticsEngine &Diags) { 1129 for (const auto &Feature : Features) { 1130 if (Feature == "+vsx") { 1131 HasVSX = true; 1132 } else if (Feature == "+bpermd") { 1133 HasBPERMD = true; 1134 } else if (Feature == "+extdiv") { 1135 HasExtDiv = true; 1136 } else if (Feature == "+power8-vector") { 1137 HasP8Vector = true; 1138 } else if (Feature == "+crypto") { 1139 HasP8Crypto = true; 1140 } else if (Feature == "+direct-move") { 1141 HasDirectMove = true; 1142 } else if (Feature == "+qpx") { 1143 HasQPX = true; 1144 } else if (Feature == "+htm") { 1145 HasHTM = true; 1146 } else if (Feature == "+float128") { 1147 HasFloat128 = true; 1148 } 1149 // TODO: Finish this list and add an assert that we've handled them 1150 // all. 1151 } 1152 1153 return true; 1154 } 1155 1156 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1157 /// #defines that are not tied to a specific subtarget. 1158 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1159 MacroBuilder &Builder) const { 1160 // Target identification. 1161 Builder.defineMacro("__ppc__"); 1162 Builder.defineMacro("__PPC__"); 1163 Builder.defineMacro("_ARCH_PPC"); 1164 Builder.defineMacro("__powerpc__"); 1165 Builder.defineMacro("__POWERPC__"); 1166 if (PointerWidth == 64) { 1167 Builder.defineMacro("_ARCH_PPC64"); 1168 Builder.defineMacro("__powerpc64__"); 1169 Builder.defineMacro("__ppc64__"); 1170 Builder.defineMacro("__PPC64__"); 1171 } 1172 1173 // Target properties. 1174 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1175 Builder.defineMacro("_LITTLE_ENDIAN"); 1176 } else { 1177 if (getTriple().getOS() != llvm::Triple::NetBSD && 1178 getTriple().getOS() != llvm::Triple::OpenBSD) 1179 Builder.defineMacro("_BIG_ENDIAN"); 1180 } 1181 1182 // ABI options. 1183 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1184 Builder.defineMacro("_CALL_ELF", "1"); 1185 if (ABI == "elfv2") 1186 Builder.defineMacro("_CALL_ELF", "2"); 1187 1188 // Subtarget options. 1189 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1190 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1191 1192 // FIXME: Should be controlled by command line option. 1193 if (LongDoubleWidth == 128) 1194 Builder.defineMacro("__LONG_DOUBLE_128__"); 1195 1196 if (Opts.AltiVec) { 1197 Builder.defineMacro("__VEC__", "10206"); 1198 Builder.defineMacro("__ALTIVEC__"); 1199 } 1200 1201 // CPU identification. 1202 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1203 .Case("440", ArchDefineName) 1204 .Case("450", ArchDefineName | ArchDefine440) 1205 .Case("601", ArchDefineName) 1206 .Case("602", ArchDefineName | ArchDefinePpcgr) 1207 .Case("603", ArchDefineName | ArchDefinePpcgr) 1208 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1209 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1210 .Case("604", ArchDefineName | ArchDefinePpcgr) 1211 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1212 .Case("620", ArchDefineName | ArchDefinePpcgr) 1213 .Case("630", ArchDefineName | ArchDefinePpcgr) 1214 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1215 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1216 .Case("750", ArchDefineName | ArchDefinePpcgr) 1217 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1218 | ArchDefinePpcsq) 1219 .Case("a2", ArchDefineA2) 1220 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1221 .Case("pwr3", ArchDefinePpcgr) 1222 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1223 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1224 | ArchDefinePpcsq) 1225 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1226 | ArchDefinePpcgr | ArchDefinePpcsq) 1227 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1228 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1229 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1230 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1231 | ArchDefinePpcsq) 1232 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1233 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1234 | ArchDefinePpcgr | ArchDefinePpcsq) 1235 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1236 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1237 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1238 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1239 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1240 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1241 | ArchDefinePpcsq) 1242 .Case("power3", ArchDefinePpcgr) 1243 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1244 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1245 | ArchDefinePpcsq) 1246 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1247 | ArchDefinePpcgr | ArchDefinePpcsq) 1248 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1249 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1250 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1251 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1252 | ArchDefinePpcsq) 1253 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1254 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1255 | ArchDefinePpcgr | ArchDefinePpcsq) 1256 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1257 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1258 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1259 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1260 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1261 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1262 | ArchDefinePpcsq) 1263 .Default(ArchDefineNone); 1264 1265 if (defs & ArchDefineName) 1266 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1267 if (defs & ArchDefinePpcgr) 1268 Builder.defineMacro("_ARCH_PPCGR"); 1269 if (defs & ArchDefinePpcsq) 1270 Builder.defineMacro("_ARCH_PPCSQ"); 1271 if (defs & ArchDefine440) 1272 Builder.defineMacro("_ARCH_440"); 1273 if (defs & ArchDefine603) 1274 Builder.defineMacro("_ARCH_603"); 1275 if (defs & ArchDefine604) 1276 Builder.defineMacro("_ARCH_604"); 1277 if (defs & ArchDefinePwr4) 1278 Builder.defineMacro("_ARCH_PWR4"); 1279 if (defs & ArchDefinePwr5) 1280 Builder.defineMacro("_ARCH_PWR5"); 1281 if (defs & ArchDefinePwr5x) 1282 Builder.defineMacro("_ARCH_PWR5X"); 1283 if (defs & ArchDefinePwr6) 1284 Builder.defineMacro("_ARCH_PWR6"); 1285 if (defs & ArchDefinePwr6x) 1286 Builder.defineMacro("_ARCH_PWR6X"); 1287 if (defs & ArchDefinePwr7) 1288 Builder.defineMacro("_ARCH_PWR7"); 1289 if (defs & ArchDefinePwr8) 1290 Builder.defineMacro("_ARCH_PWR8"); 1291 if (defs & ArchDefinePwr9) 1292 Builder.defineMacro("_ARCH_PWR9"); 1293 if (defs & ArchDefineA2) 1294 Builder.defineMacro("_ARCH_A2"); 1295 if (defs & ArchDefineA2q) { 1296 Builder.defineMacro("_ARCH_A2Q"); 1297 Builder.defineMacro("_ARCH_QP"); 1298 } 1299 1300 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1301 Builder.defineMacro("__bg__"); 1302 Builder.defineMacro("__THW_BLUEGENE__"); 1303 Builder.defineMacro("__bgq__"); 1304 Builder.defineMacro("__TOS_BGQ__"); 1305 } 1306 1307 if (HasVSX) 1308 Builder.defineMacro("__VSX__"); 1309 if (HasP8Vector) 1310 Builder.defineMacro("__POWER8_VECTOR__"); 1311 if (HasP8Crypto) 1312 Builder.defineMacro("__CRYPTO__"); 1313 if (HasHTM) 1314 Builder.defineMacro("__HTM__"); 1315 if (HasFloat128) 1316 Builder.defineMacro("__FLOAT128__"); 1317 1318 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1319 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1320 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1321 if (PointerWidth == 64) 1322 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1323 1324 // FIXME: The following are not yet generated here by Clang, but are 1325 // generated by GCC: 1326 // 1327 // _SOFT_FLOAT_ 1328 // __RECIP_PRECISION__ 1329 // __APPLE_ALTIVEC__ 1330 // __RECIP__ 1331 // __RECIPF__ 1332 // __RSQRTE__ 1333 // __RSQRTEF__ 1334 // _SOFT_DOUBLE_ 1335 // __NO_LWSYNC__ 1336 // __HAVE_BSWAP__ 1337 // __LONGDOUBLE128 1338 // __CMODEL_MEDIUM__ 1339 // __CMODEL_LARGE__ 1340 // _CALL_SYSV 1341 // _CALL_DARWIN 1342 // __NO_FPRS__ 1343 } 1344 1345 // Handle explicit options being passed to the compiler here: if we've 1346 // explicitly turned off vsx and turned on power8-vector or direct-move then 1347 // go ahead and error since the customer has expressed a somewhat incompatible 1348 // set of options. 1349 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1350 const std::vector<std::string> &FeaturesVec) { 1351 1352 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1353 FeaturesVec.end()) { 1354 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1355 FeaturesVec.end()) { 1356 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1357 << "-mno-vsx"; 1358 return false; 1359 } 1360 1361 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1362 FeaturesVec.end()) { 1363 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1364 << "-mno-vsx"; 1365 return false; 1366 } 1367 1368 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1369 FeaturesVec.end()) { 1370 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1371 << "-mno-vsx"; 1372 return false; 1373 } 1374 } 1375 1376 return true; 1377 } 1378 1379 bool PPCTargetInfo::initFeatureMap( 1380 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1381 const std::vector<std::string> &FeaturesVec) const { 1382 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1383 .Case("7400", true) 1384 .Case("g4", true) 1385 .Case("7450", true) 1386 .Case("g4+", true) 1387 .Case("970", true) 1388 .Case("g5", true) 1389 .Case("pwr6", true) 1390 .Case("pwr7", true) 1391 .Case("pwr8", true) 1392 .Case("pwr9", true) 1393 .Case("ppc64", true) 1394 .Case("ppc64le", true) 1395 .Default(false); 1396 1397 Features["qpx"] = (CPU == "a2q"); 1398 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1399 .Case("ppc64le", true) 1400 .Case("pwr9", true) 1401 .Case("pwr8", true) 1402 .Default(false); 1403 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1404 .Case("ppc64le", true) 1405 .Case("pwr9", true) 1406 .Case("pwr8", true) 1407 .Default(false); 1408 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1409 .Case("ppc64le", true) 1410 .Case("pwr9", true) 1411 .Case("pwr8", true) 1412 .Case("pwr7", true) 1413 .Default(false); 1414 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1415 .Case("ppc64le", true) 1416 .Case("pwr9", true) 1417 .Case("pwr8", true) 1418 .Case("pwr7", true) 1419 .Default(false); 1420 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1421 .Case("ppc64le", true) 1422 .Case("pwr9", true) 1423 .Case("pwr8", true) 1424 .Default(false); 1425 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1426 .Case("ppc64le", true) 1427 .Case("pwr9", true) 1428 .Case("pwr8", true) 1429 .Case("pwr7", true) 1430 .Default(false); 1431 1432 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1433 return false; 1434 1435 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1436 } 1437 1438 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1439 return llvm::StringSwitch<bool>(Feature) 1440 .Case("powerpc", true) 1441 .Case("vsx", HasVSX) 1442 .Case("power8-vector", HasP8Vector) 1443 .Case("crypto", HasP8Crypto) 1444 .Case("direct-move", HasDirectMove) 1445 .Case("qpx", HasQPX) 1446 .Case("htm", HasHTM) 1447 .Case("bpermd", HasBPERMD) 1448 .Case("extdiv", HasExtDiv) 1449 .Case("float128", HasFloat128) 1450 .Default(false); 1451 } 1452 1453 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1454 StringRef Name, bool Enabled) const { 1455 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1456 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1457 // incompatible options. 1458 if (Enabled) { 1459 if (Name == "direct-move") { 1460 Features[Name] = Features["vsx"] = true; 1461 } else if (Name == "power8-vector") { 1462 Features[Name] = Features["vsx"] = true; 1463 } else if (Name == "float128") { 1464 Features[Name] = Features["vsx"] = true; 1465 } else { 1466 Features[Name] = true; 1467 } 1468 } else { 1469 if (Name == "vsx") { 1470 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1471 Features["float128"] = false; 1472 } else { 1473 Features[Name] = false; 1474 } 1475 } 1476 } 1477 1478 const char * const PPCTargetInfo::GCCRegNames[] = { 1479 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1480 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1481 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1482 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1483 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1484 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1485 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1486 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1487 "mq", "lr", "ctr", "ap", 1488 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1489 "xer", 1490 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1491 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1492 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1493 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1494 "vrsave", "vscr", 1495 "spe_acc", "spefscr", 1496 "sfp" 1497 }; 1498 1499 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1500 return llvm::makeArrayRef(GCCRegNames); 1501 } 1502 1503 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1504 // While some of these aliases do map to different registers 1505 // they still share the same register name. 1506 { { "0" }, "r0" }, 1507 { { "1"}, "r1" }, 1508 { { "2" }, "r2" }, 1509 { { "3" }, "r3" }, 1510 { { "4" }, "r4" }, 1511 { { "5" }, "r5" }, 1512 { { "6" }, "r6" }, 1513 { { "7" }, "r7" }, 1514 { { "8" }, "r8" }, 1515 { { "9" }, "r9" }, 1516 { { "10" }, "r10" }, 1517 { { "11" }, "r11" }, 1518 { { "12" }, "r12" }, 1519 { { "13" }, "r13" }, 1520 { { "14" }, "r14" }, 1521 { { "15" }, "r15" }, 1522 { { "16" }, "r16" }, 1523 { { "17" }, "r17" }, 1524 { { "18" }, "r18" }, 1525 { { "19" }, "r19" }, 1526 { { "20" }, "r20" }, 1527 { { "21" }, "r21" }, 1528 { { "22" }, "r22" }, 1529 { { "23" }, "r23" }, 1530 { { "24" }, "r24" }, 1531 { { "25" }, "r25" }, 1532 { { "26" }, "r26" }, 1533 { { "27" }, "r27" }, 1534 { { "28" }, "r28" }, 1535 { { "29" }, "r29" }, 1536 { { "30" }, "r30" }, 1537 { { "31" }, "r31" }, 1538 { { "fr0" }, "f0" }, 1539 { { "fr1" }, "f1" }, 1540 { { "fr2" }, "f2" }, 1541 { { "fr3" }, "f3" }, 1542 { { "fr4" }, "f4" }, 1543 { { "fr5" }, "f5" }, 1544 { { "fr6" }, "f6" }, 1545 { { "fr7" }, "f7" }, 1546 { { "fr8" }, "f8" }, 1547 { { "fr9" }, "f9" }, 1548 { { "fr10" }, "f10" }, 1549 { { "fr11" }, "f11" }, 1550 { { "fr12" }, "f12" }, 1551 { { "fr13" }, "f13" }, 1552 { { "fr14" }, "f14" }, 1553 { { "fr15" }, "f15" }, 1554 { { "fr16" }, "f16" }, 1555 { { "fr17" }, "f17" }, 1556 { { "fr18" }, "f18" }, 1557 { { "fr19" }, "f19" }, 1558 { { "fr20" }, "f20" }, 1559 { { "fr21" }, "f21" }, 1560 { { "fr22" }, "f22" }, 1561 { { "fr23" }, "f23" }, 1562 { { "fr24" }, "f24" }, 1563 { { "fr25" }, "f25" }, 1564 { { "fr26" }, "f26" }, 1565 { { "fr27" }, "f27" }, 1566 { { "fr28" }, "f28" }, 1567 { { "fr29" }, "f29" }, 1568 { { "fr30" }, "f30" }, 1569 { { "fr31" }, "f31" }, 1570 { { "cc" }, "cr0" }, 1571 }; 1572 1573 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1574 return llvm::makeArrayRef(GCCRegAliases); 1575 } 1576 1577 class PPC32TargetInfo : public PPCTargetInfo { 1578 public: 1579 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1580 : PPCTargetInfo(Triple, Opts) { 1581 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1582 1583 switch (getTriple().getOS()) { 1584 case llvm::Triple::Linux: 1585 case llvm::Triple::FreeBSD: 1586 case llvm::Triple::NetBSD: 1587 SizeType = UnsignedInt; 1588 PtrDiffType = SignedInt; 1589 IntPtrType = SignedInt; 1590 break; 1591 default: 1592 break; 1593 } 1594 1595 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1596 LongDoubleWidth = LongDoubleAlign = 64; 1597 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1598 } 1599 1600 // PPC32 supports atomics up to 4 bytes. 1601 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1602 } 1603 1604 BuiltinVaListKind getBuiltinVaListKind() const override { 1605 // This is the ELF definition, and is overridden by the Darwin sub-target 1606 return TargetInfo::PowerABIBuiltinVaList; 1607 } 1608 }; 1609 1610 // Note: ABI differences may eventually require us to have a separate 1611 // TargetInfo for little endian. 1612 class PPC64TargetInfo : public PPCTargetInfo { 1613 public: 1614 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1615 : PPCTargetInfo(Triple, Opts) { 1616 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1617 IntMaxType = SignedLong; 1618 Int64Type = SignedLong; 1619 1620 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1621 resetDataLayout("e-m:e-i64:64-n32:64"); 1622 ABI = "elfv2"; 1623 } else { 1624 resetDataLayout("E-m:e-i64:64-n32:64"); 1625 ABI = "elfv1"; 1626 } 1627 1628 switch (getTriple().getOS()) { 1629 case llvm::Triple::FreeBSD: 1630 LongDoubleWidth = LongDoubleAlign = 64; 1631 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1632 break; 1633 case llvm::Triple::NetBSD: 1634 IntMaxType = SignedLongLong; 1635 Int64Type = SignedLongLong; 1636 break; 1637 default: 1638 break; 1639 } 1640 1641 // PPC64 supports atomics up to 8 bytes. 1642 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1643 } 1644 BuiltinVaListKind getBuiltinVaListKind() const override { 1645 return TargetInfo::CharPtrBuiltinVaList; 1646 } 1647 // PPC64 Linux-specific ABI options. 1648 bool setABI(const std::string &Name) override { 1649 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1650 ABI = Name; 1651 return true; 1652 } 1653 return false; 1654 } 1655 }; 1656 1657 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1658 public: 1659 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1660 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1661 HasAlignMac68kSupport = true; 1662 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1663 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1664 LongLongAlign = 32; 1665 SuitableAlign = 128; 1666 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1667 } 1668 BuiltinVaListKind getBuiltinVaListKind() const override { 1669 return TargetInfo::CharPtrBuiltinVaList; 1670 } 1671 }; 1672 1673 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1674 public: 1675 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1676 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1677 HasAlignMac68kSupport = true; 1678 SuitableAlign = 128; 1679 resetDataLayout("E-m:o-i64:64-n32:64"); 1680 } 1681 }; 1682 1683 static const unsigned NVPTXAddrSpaceMap[] = { 1684 1, // opencl_global 1685 3, // opencl_local 1686 4, // opencl_constant 1687 // FIXME: generic has to be added to the target 1688 0, // opencl_generic 1689 1, // cuda_device 1690 4, // cuda_constant 1691 3, // cuda_shared 1692 }; 1693 1694 class NVPTXTargetInfo : public TargetInfo { 1695 static const char *const GCCRegNames[]; 1696 static const Builtin::Info BuiltinInfo[]; 1697 1698 // The GPU profiles supported by the NVPTX backend 1699 enum GPUKind { 1700 GK_NONE, 1701 GK_SM20, 1702 GK_SM21, 1703 GK_SM30, 1704 GK_SM35, 1705 GK_SM37, 1706 GK_SM50, 1707 GK_SM52, 1708 GK_SM53, 1709 } GPU; 1710 1711 public: 1712 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1713 : TargetInfo(Triple) { 1714 BigEndian = false; 1715 TLSSupported = false; 1716 LongWidth = LongAlign = 64; 1717 AddrSpaceMap = &NVPTXAddrSpaceMap; 1718 UseAddrSpaceMapMangling = true; 1719 // Define available target features 1720 // These must be defined in sorted order! 1721 NoAsmVariants = true; 1722 // Set the default GPU to sm20 1723 GPU = GK_SM20; 1724 1725 // If possible, get a TargetInfo for our host triple, so we can match its 1726 // types. 1727 llvm::Triple HostTriple(Opts.HostTriple); 1728 if (HostTriple.isNVPTX()) 1729 return; 1730 std::unique_ptr<TargetInfo> HostTarget( 1731 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1732 if (!HostTarget) { 1733 return; 1734 } 1735 1736 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1737 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1738 BoolWidth = HostTarget->getBoolWidth(); 1739 BoolAlign = HostTarget->getBoolAlign(); 1740 IntWidth = HostTarget->getIntWidth(); 1741 IntAlign = HostTarget->getIntAlign(); 1742 HalfWidth = HostTarget->getHalfWidth(); 1743 HalfAlign = HostTarget->getHalfAlign(); 1744 FloatWidth = HostTarget->getFloatWidth(); 1745 FloatAlign = HostTarget->getFloatAlign(); 1746 DoubleWidth = HostTarget->getDoubleWidth(); 1747 DoubleAlign = HostTarget->getDoubleAlign(); 1748 LongWidth = HostTarget->getLongWidth(); 1749 LongAlign = HostTarget->getLongAlign(); 1750 LongLongWidth = HostTarget->getLongLongWidth(); 1751 LongLongAlign = HostTarget->getLongLongAlign(); 1752 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1753 DefaultAlignForAttributeAligned = 1754 HostTarget->getDefaultAlignForAttributeAligned(); 1755 SizeType = HostTarget->getSizeType(); 1756 IntMaxType = HostTarget->getIntMaxType(); 1757 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1758 IntPtrType = HostTarget->getIntPtrType(); 1759 WCharType = HostTarget->getWCharType(); 1760 WIntType = HostTarget->getWIntType(); 1761 Char16Type = HostTarget->getChar16Type(); 1762 Char32Type = HostTarget->getChar32Type(); 1763 Int64Type = HostTarget->getInt64Type(); 1764 SigAtomicType = HostTarget->getSigAtomicType(); 1765 ProcessIDType = HostTarget->getProcessIDType(); 1766 1767 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1768 UseZeroLengthBitfieldAlignment = 1769 HostTarget->useZeroLengthBitfieldAlignment(); 1770 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1771 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1772 1773 // Properties intentionally not copied from host: 1774 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1775 // host/device boundary. 1776 // - SuitableAlign: Not visible across the host/device boundary, and may 1777 // correctly be different on host/device, e.g. if host has wider vector 1778 // types than device. 1779 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1780 // as its double type, but that's not necessarily true on the host. 1781 // TODO: nvcc emits a warning when using long double on device; we should 1782 // do the same. 1783 } 1784 void getTargetDefines(const LangOptions &Opts, 1785 MacroBuilder &Builder) const override { 1786 Builder.defineMacro("__PTX__"); 1787 Builder.defineMacro("__NVPTX__"); 1788 if (Opts.CUDAIsDevice) { 1789 // Set __CUDA_ARCH__ for the GPU specified. 1790 std::string CUDAArchCode; 1791 switch (GPU) { 1792 case GK_SM20: 1793 CUDAArchCode = "200"; 1794 break; 1795 case GK_SM21: 1796 CUDAArchCode = "210"; 1797 break; 1798 case GK_SM30: 1799 CUDAArchCode = "300"; 1800 break; 1801 case GK_SM35: 1802 CUDAArchCode = "350"; 1803 break; 1804 case GK_SM37: 1805 CUDAArchCode = "370"; 1806 break; 1807 case GK_SM50: 1808 CUDAArchCode = "500"; 1809 break; 1810 case GK_SM52: 1811 CUDAArchCode = "520"; 1812 break; 1813 case GK_SM53: 1814 CUDAArchCode = "530"; 1815 break; 1816 default: 1817 llvm_unreachable("Unhandled target CPU"); 1818 } 1819 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1820 } 1821 } 1822 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1823 return llvm::makeArrayRef(BuiltinInfo, 1824 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1825 } 1826 bool hasFeature(StringRef Feature) const override { 1827 return Feature == "ptx" || Feature == "nvptx"; 1828 } 1829 1830 ArrayRef<const char *> getGCCRegNames() const override; 1831 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1832 // No aliases. 1833 return None; 1834 } 1835 bool validateAsmConstraint(const char *&Name, 1836 TargetInfo::ConstraintInfo &Info) const override { 1837 switch (*Name) { 1838 default: 1839 return false; 1840 case 'c': 1841 case 'h': 1842 case 'r': 1843 case 'l': 1844 case 'f': 1845 case 'd': 1846 Info.setAllowsRegister(); 1847 return true; 1848 } 1849 } 1850 const char *getClobbers() const override { 1851 // FIXME: Is this really right? 1852 return ""; 1853 } 1854 BuiltinVaListKind getBuiltinVaListKind() const override { 1855 // FIXME: implement 1856 return TargetInfo::CharPtrBuiltinVaList; 1857 } 1858 bool setCPU(const std::string &Name) override { 1859 GPU = llvm::StringSwitch<GPUKind>(Name) 1860 .Case("sm_20", GK_SM20) 1861 .Case("sm_21", GK_SM21) 1862 .Case("sm_30", GK_SM30) 1863 .Case("sm_35", GK_SM35) 1864 .Case("sm_37", GK_SM37) 1865 .Case("sm_50", GK_SM50) 1866 .Case("sm_52", GK_SM52) 1867 .Case("sm_53", GK_SM53) 1868 .Default(GK_NONE); 1869 1870 return GPU != GK_NONE; 1871 } 1872 void setSupportedOpenCLOpts() override { 1873 auto &Opts = getSupportedOpenCLOpts(); 1874 Opts.cl_clang_storage_class_specifiers = 1; 1875 Opts.cl_khr_gl_sharing = 1; 1876 Opts.cl_khr_icd = 1; 1877 1878 Opts.cl_khr_fp64 = 1; 1879 Opts.cl_khr_byte_addressable_store = 1; 1880 Opts.cl_khr_global_int32_base_atomics = 1; 1881 Opts.cl_khr_global_int32_extended_atomics = 1; 1882 Opts.cl_khr_local_int32_base_atomics = 1; 1883 Opts.cl_khr_local_int32_extended_atomics = 1; 1884 } 1885 }; 1886 1887 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1888 #define BUILTIN(ID, TYPE, ATTRS) \ 1889 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1890 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1891 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1892 #include "clang/Basic/BuiltinsNVPTX.def" 1893 }; 1894 1895 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1896 1897 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1898 return llvm::makeArrayRef(GCCRegNames); 1899 } 1900 1901 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1902 public: 1903 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1904 : NVPTXTargetInfo(Triple, Opts) { 1905 LongWidth = LongAlign = 32; 1906 PointerWidth = PointerAlign = 32; 1907 SizeType = TargetInfo::UnsignedInt; 1908 PtrDiffType = TargetInfo::SignedInt; 1909 IntPtrType = TargetInfo::SignedInt; 1910 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1911 } 1912 }; 1913 1914 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1915 public: 1916 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1917 : NVPTXTargetInfo(Triple, Opts) { 1918 PointerWidth = PointerAlign = 64; 1919 SizeType = TargetInfo::UnsignedLong; 1920 PtrDiffType = TargetInfo::SignedLong; 1921 IntPtrType = TargetInfo::SignedLong; 1922 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1923 } 1924 }; 1925 1926 static const unsigned AMDGPUAddrSpaceMap[] = { 1927 1, // opencl_global 1928 3, // opencl_local 1929 2, // opencl_constant 1930 4, // opencl_generic 1931 1, // cuda_device 1932 2, // cuda_constant 1933 3 // cuda_shared 1934 }; 1935 1936 // If you edit the description strings, make sure you update 1937 // getPointerWidthV(). 1938 1939 static const char *const DataLayoutStringR600 = 1940 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1941 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1942 1943 static const char *const DataLayoutStringSI = 1944 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 1945 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1946 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1947 1948 class AMDGPUTargetInfo final : public TargetInfo { 1949 static const Builtin::Info BuiltinInfo[]; 1950 static const char * const GCCRegNames[]; 1951 1952 /// \brief The GPU profiles supported by the AMDGPU target. 1953 enum GPUKind { 1954 GK_NONE, 1955 GK_R600, 1956 GK_R600_DOUBLE_OPS, 1957 GK_R700, 1958 GK_R700_DOUBLE_OPS, 1959 GK_EVERGREEN, 1960 GK_EVERGREEN_DOUBLE_OPS, 1961 GK_NORTHERN_ISLANDS, 1962 GK_CAYMAN, 1963 GK_SOUTHERN_ISLANDS, 1964 GK_SEA_ISLANDS, 1965 GK_VOLCANIC_ISLANDS 1966 } GPU; 1967 1968 bool hasFP64:1; 1969 bool hasFMAF:1; 1970 bool hasLDEXPF:1; 1971 1972 static bool isAMDGCN(const llvm::Triple &TT) { 1973 return TT.getArch() == llvm::Triple::amdgcn; 1974 } 1975 1976 public: 1977 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 1978 : TargetInfo(Triple) , 1979 GPU(isAMDGCN(Triple) ? GK_SOUTHERN_ISLANDS : GK_R600), 1980 hasFP64(false), 1981 hasFMAF(false), 1982 hasLDEXPF(false) { 1983 if (getTriple().getArch() == llvm::Triple::amdgcn) { 1984 hasFP64 = true; 1985 hasFMAF = true; 1986 hasLDEXPF = true; 1987 } 1988 1989 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 1990 DataLayoutStringSI : DataLayoutStringR600); 1991 1992 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1993 UseAddrSpaceMapMangling = true; 1994 } 1995 1996 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1997 if (GPU <= GK_CAYMAN) 1998 return 32; 1999 2000 switch(AddrSpace) { 2001 default: 2002 return 64; 2003 case 0: 2004 case 3: 2005 case 5: 2006 return 32; 2007 } 2008 } 2009 2010 const char * getClobbers() const override { 2011 return ""; 2012 } 2013 2014 ArrayRef<const char *> getGCCRegNames() const override; 2015 2016 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2017 return None; 2018 } 2019 2020 bool validateAsmConstraint(const char *&Name, 2021 TargetInfo::ConstraintInfo &Info) const override { 2022 switch (*Name) { 2023 default: break; 2024 case 'v': // vgpr 2025 case 's': // sgpr 2026 Info.setAllowsRegister(); 2027 return true; 2028 } 2029 return false; 2030 } 2031 2032 bool initFeatureMap(llvm::StringMap<bool> &Features, 2033 DiagnosticsEngine &Diags, StringRef CPU, 2034 const std::vector<std::string> &FeatureVec) const override; 2035 2036 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2037 return llvm::makeArrayRef(BuiltinInfo, 2038 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2039 } 2040 2041 void getTargetDefines(const LangOptions &Opts, 2042 MacroBuilder &Builder) const override { 2043 if (getTriple().getArch() == llvm::Triple::amdgcn) 2044 Builder.defineMacro("__AMDGCN__"); 2045 else 2046 Builder.defineMacro("__R600__"); 2047 2048 if (hasFMAF) 2049 Builder.defineMacro("__HAS_FMAF__"); 2050 if (hasLDEXPF) 2051 Builder.defineMacro("__HAS_LDEXPF__"); 2052 if (hasFP64) 2053 Builder.defineMacro("__HAS_FP64__"); 2054 } 2055 2056 BuiltinVaListKind getBuiltinVaListKind() const override { 2057 return TargetInfo::CharPtrBuiltinVaList; 2058 } 2059 2060 static GPUKind parseR600Name(StringRef Name) { 2061 return llvm::StringSwitch<GPUKind>(Name) 2062 .Case("r600" , GK_R600) 2063 .Case("rv610", GK_R600) 2064 .Case("rv620", GK_R600) 2065 .Case("rv630", GK_R600) 2066 .Case("rv635", GK_R600) 2067 .Case("rs780", GK_R600) 2068 .Case("rs880", GK_R600) 2069 .Case("rv670", GK_R600_DOUBLE_OPS) 2070 .Case("rv710", GK_R700) 2071 .Case("rv730", GK_R700) 2072 .Case("rv740", GK_R700_DOUBLE_OPS) 2073 .Case("rv770", GK_R700_DOUBLE_OPS) 2074 .Case("palm", GK_EVERGREEN) 2075 .Case("cedar", GK_EVERGREEN) 2076 .Case("sumo", GK_EVERGREEN) 2077 .Case("sumo2", GK_EVERGREEN) 2078 .Case("redwood", GK_EVERGREEN) 2079 .Case("juniper", GK_EVERGREEN) 2080 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2081 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2082 .Case("barts", GK_NORTHERN_ISLANDS) 2083 .Case("turks", GK_NORTHERN_ISLANDS) 2084 .Case("caicos", GK_NORTHERN_ISLANDS) 2085 .Case("cayman", GK_CAYMAN) 2086 .Case("aruba", GK_CAYMAN) 2087 .Default(GK_NONE); 2088 } 2089 2090 static GPUKind parseAMDGCNName(StringRef Name) { 2091 return llvm::StringSwitch<GPUKind>(Name) 2092 .Case("tahiti", GK_SOUTHERN_ISLANDS) 2093 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 2094 .Case("verde", GK_SOUTHERN_ISLANDS) 2095 .Case("oland", GK_SOUTHERN_ISLANDS) 2096 .Case("hainan", GK_SOUTHERN_ISLANDS) 2097 .Case("bonaire", GK_SEA_ISLANDS) 2098 .Case("kabini", GK_SEA_ISLANDS) 2099 .Case("kaveri", GK_SEA_ISLANDS) 2100 .Case("hawaii", GK_SEA_ISLANDS) 2101 .Case("mullins", GK_SEA_ISLANDS) 2102 .Case("tonga", GK_VOLCANIC_ISLANDS) 2103 .Case("iceland", GK_VOLCANIC_ISLANDS) 2104 .Case("carrizo", GK_VOLCANIC_ISLANDS) 2105 .Case("fiji", GK_VOLCANIC_ISLANDS) 2106 .Case("stoney", GK_VOLCANIC_ISLANDS) 2107 .Default(GK_NONE); 2108 } 2109 2110 bool setCPU(const std::string &Name) override { 2111 if (getTriple().getArch() == llvm::Triple::amdgcn) 2112 GPU = parseAMDGCNName(Name); 2113 else 2114 GPU = parseR600Name(Name); 2115 2116 return GPU != GK_NONE; 2117 } 2118 2119 void setSupportedOpenCLOpts() override { 2120 auto &Opts = getSupportedOpenCLOpts(); 2121 Opts.cl_clang_storage_class_specifiers = 1; 2122 Opts.cl_khr_icd = 1; 2123 2124 if (hasFP64) 2125 Opts.cl_khr_fp64 = 1; 2126 if (GPU >= GK_EVERGREEN) { 2127 Opts.cl_khr_byte_addressable_store = 1; 2128 Opts.cl_khr_global_int32_base_atomics = 1; 2129 Opts.cl_khr_global_int32_extended_atomics = 1; 2130 Opts.cl_khr_local_int32_base_atomics = 1; 2131 Opts.cl_khr_local_int32_extended_atomics = 1; 2132 } 2133 if (GPU >= GK_SOUTHERN_ISLANDS) { 2134 Opts.cl_khr_fp16 = 1; 2135 Opts.cl_khr_int64_base_atomics = 1; 2136 Opts.cl_khr_int64_extended_atomics = 1; 2137 Opts.cl_khr_3d_image_writes = 1; 2138 } 2139 } 2140 2141 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2142 switch (CC) { 2143 default: 2144 return CCCR_Warning; 2145 case CC_C: 2146 case CC_OpenCLKernel: 2147 return CCCR_OK; 2148 } 2149 } 2150 }; 2151 2152 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2153 #define BUILTIN(ID, TYPE, ATTRS) \ 2154 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2155 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2156 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2157 #include "clang/Basic/BuiltinsAMDGPU.def" 2158 }; 2159 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2160 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2161 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2162 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2163 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2164 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2165 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2166 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2167 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2168 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2169 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2170 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2171 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2172 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2173 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2174 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2175 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2176 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2177 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2178 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2179 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2180 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2181 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2182 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2183 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2184 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2185 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2186 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2187 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2188 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2189 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2190 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2191 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2192 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2193 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2194 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2195 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2196 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2197 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2198 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2199 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2200 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2201 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2202 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2203 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2204 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2205 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2206 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2207 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2208 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2209 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2210 }; 2211 2212 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2213 return llvm::makeArrayRef(GCCRegNames); 2214 } 2215 2216 bool AMDGPUTargetInfo::initFeatureMap( 2217 llvm::StringMap<bool> &Features, 2218 DiagnosticsEngine &Diags, StringRef CPU, 2219 const std::vector<std::string> &FeatureVec) const { 2220 2221 // XXX - What does the member GPU mean if device name string passed here? 2222 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2223 if (CPU.empty()) 2224 CPU = "tahiti"; 2225 2226 switch (parseAMDGCNName(CPU)) { 2227 case GK_SOUTHERN_ISLANDS: 2228 case GK_SEA_ISLANDS: 2229 break; 2230 2231 case GK_VOLCANIC_ISLANDS: 2232 Features["s-memrealtime"] = true; 2233 Features["16-bit-insts"] = true; 2234 break; 2235 2236 case GK_NONE: 2237 return false; 2238 default: 2239 llvm_unreachable("unhandled subtarget"); 2240 } 2241 } else { 2242 if (CPU.empty()) 2243 CPU = "r600"; 2244 2245 switch (parseR600Name(CPU)) { 2246 case GK_R600: 2247 case GK_R700: 2248 case GK_EVERGREEN: 2249 case GK_NORTHERN_ISLANDS: 2250 break; 2251 case GK_R600_DOUBLE_OPS: 2252 case GK_R700_DOUBLE_OPS: 2253 case GK_EVERGREEN_DOUBLE_OPS: 2254 case GK_CAYMAN: 2255 Features["fp64"] = true; 2256 break; 2257 case GK_NONE: 2258 return false; 2259 default: 2260 llvm_unreachable("unhandled subtarget"); 2261 } 2262 } 2263 2264 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2265 } 2266 2267 // Namespace for x86 abstract base class 2268 const Builtin::Info BuiltinInfo[] = { 2269 #define BUILTIN(ID, TYPE, ATTRS) \ 2270 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2271 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2272 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2273 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2274 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2275 #include "clang/Basic/BuiltinsX86.def" 2276 }; 2277 2278 static const char* const GCCRegNames[] = { 2279 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2280 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2281 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2282 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2283 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2284 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2285 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2286 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2287 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2288 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2289 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2290 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2291 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2292 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2293 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2294 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2295 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2296 }; 2297 2298 const TargetInfo::AddlRegName AddlRegNames[] = { 2299 { { "al", "ah", "eax", "rax" }, 0 }, 2300 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2301 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2302 { { "dl", "dh", "edx", "rdx" }, 1 }, 2303 { { "esi", "rsi" }, 4 }, 2304 { { "edi", "rdi" }, 5 }, 2305 { { "esp", "rsp" }, 7 }, 2306 { { "ebp", "rbp" }, 6 }, 2307 { { "r8d", "r8w", "r8b" }, 38 }, 2308 { { "r9d", "r9w", "r9b" }, 39 }, 2309 { { "r10d", "r10w", "r10b" }, 40 }, 2310 { { "r11d", "r11w", "r11b" }, 41 }, 2311 { { "r12d", "r12w", "r12b" }, 42 }, 2312 { { "r13d", "r13w", "r13b" }, 43 }, 2313 { { "r14d", "r14w", "r14b" }, 44 }, 2314 { { "r15d", "r15w", "r15b" }, 45 }, 2315 }; 2316 2317 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2318 // most of the implementation can be shared. 2319 class X86TargetInfo : public TargetInfo { 2320 enum X86SSEEnum { 2321 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2322 } SSELevel = NoSSE; 2323 enum MMX3DNowEnum { 2324 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2325 } MMX3DNowLevel = NoMMX3DNow; 2326 enum XOPEnum { 2327 NoXOP, 2328 SSE4A, 2329 FMA4, 2330 XOP 2331 } XOPLevel = NoXOP; 2332 2333 bool HasAES = false; 2334 bool HasPCLMUL = false; 2335 bool HasLZCNT = false; 2336 bool HasRDRND = false; 2337 bool HasFSGSBASE = false; 2338 bool HasBMI = false; 2339 bool HasBMI2 = false; 2340 bool HasPOPCNT = false; 2341 bool HasRTM = false; 2342 bool HasPRFCHW = false; 2343 bool HasRDSEED = false; 2344 bool HasADX = false; 2345 bool HasTBM = false; 2346 bool HasFMA = false; 2347 bool HasF16C = false; 2348 bool HasAVX512CD = false; 2349 bool HasAVX512ER = false; 2350 bool HasAVX512PF = false; 2351 bool HasAVX512DQ = false; 2352 bool HasAVX512BW = false; 2353 bool HasAVX512VL = false; 2354 bool HasAVX512VBMI = false; 2355 bool HasAVX512IFMA = false; 2356 bool HasSHA = false; 2357 bool HasMPX = false; 2358 bool HasSGX = false; 2359 bool HasCX16 = false; 2360 bool HasFXSR = false; 2361 bool HasXSAVE = false; 2362 bool HasXSAVEOPT = false; 2363 bool HasXSAVEC = false; 2364 bool HasXSAVES = false; 2365 bool HasMWAITX = false; 2366 bool HasPKU = false; 2367 bool HasCLFLUSHOPT = false; 2368 bool HasPCOMMIT = false; 2369 bool HasCLWB = false; 2370 bool HasUMIP = false; 2371 bool HasMOVBE = false; 2372 bool HasPREFETCHWT1 = false; 2373 2374 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2375 /// 2376 /// Each enumeration represents a particular CPU supported by Clang. These 2377 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2378 enum CPUKind { 2379 CK_Generic, 2380 2381 /// \name i386 2382 /// i386-generation processors. 2383 //@{ 2384 CK_i386, 2385 //@} 2386 2387 /// \name i486 2388 /// i486-generation processors. 2389 //@{ 2390 CK_i486, 2391 CK_WinChipC6, 2392 CK_WinChip2, 2393 CK_C3, 2394 //@} 2395 2396 /// \name i586 2397 /// i586-generation processors, P5 microarchitecture based. 2398 //@{ 2399 CK_i586, 2400 CK_Pentium, 2401 CK_PentiumMMX, 2402 //@} 2403 2404 /// \name i686 2405 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2406 //@{ 2407 CK_i686, 2408 CK_PentiumPro, 2409 CK_Pentium2, 2410 CK_Pentium3, 2411 CK_Pentium3M, 2412 CK_PentiumM, 2413 CK_C3_2, 2414 2415 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2416 /// Clang however has some logic to suport this. 2417 // FIXME: Warn, deprecate, and potentially remove this. 2418 CK_Yonah, 2419 //@} 2420 2421 /// \name Netburst 2422 /// Netburst microarchitecture based processors. 2423 //@{ 2424 CK_Pentium4, 2425 CK_Pentium4M, 2426 CK_Prescott, 2427 CK_Nocona, 2428 //@} 2429 2430 /// \name Core 2431 /// Core microarchitecture based processors. 2432 //@{ 2433 CK_Core2, 2434 2435 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2436 /// codename which GCC no longer accepts as an option to -march, but Clang 2437 /// has some logic for recognizing it. 2438 // FIXME: Warn, deprecate, and potentially remove this. 2439 CK_Penryn, 2440 //@} 2441 2442 /// \name Atom 2443 /// Atom processors 2444 //@{ 2445 CK_Bonnell, 2446 CK_Silvermont, 2447 //@} 2448 2449 /// \name Nehalem 2450 /// Nehalem microarchitecture based processors. 2451 CK_Nehalem, 2452 2453 /// \name Westmere 2454 /// Westmere microarchitecture based processors. 2455 CK_Westmere, 2456 2457 /// \name Sandy Bridge 2458 /// Sandy Bridge microarchitecture based processors. 2459 CK_SandyBridge, 2460 2461 /// \name Ivy Bridge 2462 /// Ivy Bridge microarchitecture based processors. 2463 CK_IvyBridge, 2464 2465 /// \name Haswell 2466 /// Haswell microarchitecture based processors. 2467 CK_Haswell, 2468 2469 /// \name Broadwell 2470 /// Broadwell microarchitecture based processors. 2471 CK_Broadwell, 2472 2473 /// \name Skylake Client 2474 /// Skylake client microarchitecture based processors. 2475 CK_SkylakeClient, 2476 2477 /// \name Skylake Server 2478 /// Skylake server microarchitecture based processors. 2479 CK_SkylakeServer, 2480 2481 /// \name Cannonlake Client 2482 /// Cannonlake client microarchitecture based processors. 2483 CK_Cannonlake, 2484 2485 /// \name Knights Landing 2486 /// Knights Landing processor. 2487 CK_KNL, 2488 2489 /// \name Lakemont 2490 /// Lakemont microarchitecture based processors. 2491 CK_Lakemont, 2492 2493 /// \name K6 2494 /// K6 architecture processors. 2495 //@{ 2496 CK_K6, 2497 CK_K6_2, 2498 CK_K6_3, 2499 //@} 2500 2501 /// \name K7 2502 /// K7 architecture processors. 2503 //@{ 2504 CK_Athlon, 2505 CK_AthlonThunderbird, 2506 CK_Athlon4, 2507 CK_AthlonXP, 2508 CK_AthlonMP, 2509 //@} 2510 2511 /// \name K8 2512 /// K8 architecture processors. 2513 //@{ 2514 CK_Athlon64, 2515 CK_Athlon64SSE3, 2516 CK_AthlonFX, 2517 CK_K8, 2518 CK_K8SSE3, 2519 CK_Opteron, 2520 CK_OpteronSSE3, 2521 CK_AMDFAM10, 2522 //@} 2523 2524 /// \name Bobcat 2525 /// Bobcat architecture processors. 2526 //@{ 2527 CK_BTVER1, 2528 CK_BTVER2, 2529 //@} 2530 2531 /// \name Bulldozer 2532 /// Bulldozer architecture processors. 2533 //@{ 2534 CK_BDVER1, 2535 CK_BDVER2, 2536 CK_BDVER3, 2537 CK_BDVER4, 2538 //@} 2539 2540 /// This specification is deprecated and will be removed in the future. 2541 /// Users should prefer \see CK_K8. 2542 // FIXME: Warn on this when the CPU is set to it. 2543 //@{ 2544 CK_x86_64, 2545 //@} 2546 2547 /// \name Geode 2548 /// Geode processors. 2549 //@{ 2550 CK_Geode 2551 //@} 2552 } CPU = CK_Generic; 2553 2554 CPUKind getCPUKind(StringRef CPU) const { 2555 return llvm::StringSwitch<CPUKind>(CPU) 2556 .Case("i386", CK_i386) 2557 .Case("i486", CK_i486) 2558 .Case("winchip-c6", CK_WinChipC6) 2559 .Case("winchip2", CK_WinChip2) 2560 .Case("c3", CK_C3) 2561 .Case("i586", CK_i586) 2562 .Case("pentium", CK_Pentium) 2563 .Case("pentium-mmx", CK_PentiumMMX) 2564 .Case("i686", CK_i686) 2565 .Case("pentiumpro", CK_PentiumPro) 2566 .Case("pentium2", CK_Pentium2) 2567 .Case("pentium3", CK_Pentium3) 2568 .Case("pentium3m", CK_Pentium3M) 2569 .Case("pentium-m", CK_PentiumM) 2570 .Case("c3-2", CK_C3_2) 2571 .Case("yonah", CK_Yonah) 2572 .Case("pentium4", CK_Pentium4) 2573 .Case("pentium4m", CK_Pentium4M) 2574 .Case("prescott", CK_Prescott) 2575 .Case("nocona", CK_Nocona) 2576 .Case("core2", CK_Core2) 2577 .Case("penryn", CK_Penryn) 2578 .Case("bonnell", CK_Bonnell) 2579 .Case("atom", CK_Bonnell) // Legacy name. 2580 .Case("silvermont", CK_Silvermont) 2581 .Case("slm", CK_Silvermont) // Legacy name. 2582 .Case("nehalem", CK_Nehalem) 2583 .Case("corei7", CK_Nehalem) // Legacy name. 2584 .Case("westmere", CK_Westmere) 2585 .Case("sandybridge", CK_SandyBridge) 2586 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2587 .Case("ivybridge", CK_IvyBridge) 2588 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2589 .Case("haswell", CK_Haswell) 2590 .Case("core-avx2", CK_Haswell) // Legacy name. 2591 .Case("broadwell", CK_Broadwell) 2592 .Case("skylake", CK_SkylakeClient) 2593 .Case("skylake-avx512", CK_SkylakeServer) 2594 .Case("skx", CK_SkylakeServer) // Legacy name. 2595 .Case("cannonlake", CK_Cannonlake) 2596 .Case("knl", CK_KNL) 2597 .Case("lakemont", CK_Lakemont) 2598 .Case("k6", CK_K6) 2599 .Case("k6-2", CK_K6_2) 2600 .Case("k6-3", CK_K6_3) 2601 .Case("athlon", CK_Athlon) 2602 .Case("athlon-tbird", CK_AthlonThunderbird) 2603 .Case("athlon-4", CK_Athlon4) 2604 .Case("athlon-xp", CK_AthlonXP) 2605 .Case("athlon-mp", CK_AthlonMP) 2606 .Case("athlon64", CK_Athlon64) 2607 .Case("athlon64-sse3", CK_Athlon64SSE3) 2608 .Case("athlon-fx", CK_AthlonFX) 2609 .Case("k8", CK_K8) 2610 .Case("k8-sse3", CK_K8SSE3) 2611 .Case("opteron", CK_Opteron) 2612 .Case("opteron-sse3", CK_OpteronSSE3) 2613 .Case("barcelona", CK_AMDFAM10) 2614 .Case("amdfam10", CK_AMDFAM10) 2615 .Case("btver1", CK_BTVER1) 2616 .Case("btver2", CK_BTVER2) 2617 .Case("bdver1", CK_BDVER1) 2618 .Case("bdver2", CK_BDVER2) 2619 .Case("bdver3", CK_BDVER3) 2620 .Case("bdver4", CK_BDVER4) 2621 .Case("x86-64", CK_x86_64) 2622 .Case("geode", CK_Geode) 2623 .Default(CK_Generic); 2624 } 2625 2626 enum FPMathKind { 2627 FP_Default, 2628 FP_SSE, 2629 FP_387 2630 } FPMath = FP_Default; 2631 2632 public: 2633 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2634 : TargetInfo(Triple) { 2635 BigEndian = false; 2636 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2637 } 2638 unsigned getFloatEvalMethod() const override { 2639 // X87 evaluates with 80 bits "long double" precision. 2640 return SSELevel == NoSSE ? 2 : 0; 2641 } 2642 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2643 return llvm::makeArrayRef(BuiltinInfo, 2644 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2645 } 2646 ArrayRef<const char *> getGCCRegNames() const override { 2647 return llvm::makeArrayRef(GCCRegNames); 2648 } 2649 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2650 return None; 2651 } 2652 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2653 return llvm::makeArrayRef(AddlRegNames); 2654 } 2655 bool validateCpuSupports(StringRef Name) const override; 2656 bool validateAsmConstraint(const char *&Name, 2657 TargetInfo::ConstraintInfo &info) const override; 2658 2659 bool validateGlobalRegisterVariable(StringRef RegName, 2660 unsigned RegSize, 2661 bool &HasSizeMismatch) const override { 2662 // esp and ebp are the only 32-bit registers the x86 backend can currently 2663 // handle. 2664 if (RegName.equals("esp") || RegName.equals("ebp")) { 2665 // Check that the register size is 32-bit. 2666 HasSizeMismatch = RegSize != 32; 2667 return true; 2668 } 2669 2670 return false; 2671 } 2672 2673 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2674 2675 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2676 2677 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2678 2679 std::string convertConstraint(const char *&Constraint) const override; 2680 const char *getClobbers() const override { 2681 return "~{dirflag},~{fpsr},~{flags}"; 2682 } 2683 void getTargetDefines(const LangOptions &Opts, 2684 MacroBuilder &Builder) const override; 2685 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2686 bool Enabled); 2687 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2688 bool Enabled); 2689 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2690 bool Enabled); 2691 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2692 StringRef Name, bool Enabled) const override { 2693 setFeatureEnabledImpl(Features, Name, Enabled); 2694 } 2695 // This exists purely to cut down on the number of virtual calls in 2696 // initFeatureMap which calls this repeatedly. 2697 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2698 StringRef Name, bool Enabled); 2699 bool 2700 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2701 StringRef CPU, 2702 const std::vector<std::string> &FeaturesVec) const override; 2703 bool hasFeature(StringRef Feature) const override; 2704 bool handleTargetFeatures(std::vector<std::string> &Features, 2705 DiagnosticsEngine &Diags) override; 2706 StringRef getABI() const override { 2707 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2708 return "avx512"; 2709 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2710 return "avx"; 2711 if (getTriple().getArch() == llvm::Triple::x86 && 2712 MMX3DNowLevel == NoMMX3DNow) 2713 return "no-mmx"; 2714 return ""; 2715 } 2716 bool setCPU(const std::string &Name) override { 2717 CPU = getCPUKind(Name); 2718 2719 // Perform any per-CPU checks necessary to determine if this CPU is 2720 // acceptable. 2721 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2722 // invalid without explaining *why*. 2723 switch (CPU) { 2724 case CK_Generic: 2725 // No processor selected! 2726 return false; 2727 2728 case CK_i386: 2729 case CK_i486: 2730 case CK_WinChipC6: 2731 case CK_WinChip2: 2732 case CK_C3: 2733 case CK_i586: 2734 case CK_Pentium: 2735 case CK_PentiumMMX: 2736 case CK_i686: 2737 case CK_PentiumPro: 2738 case CK_Pentium2: 2739 case CK_Pentium3: 2740 case CK_Pentium3M: 2741 case CK_PentiumM: 2742 case CK_Yonah: 2743 case CK_C3_2: 2744 case CK_Pentium4: 2745 case CK_Pentium4M: 2746 case CK_Lakemont: 2747 case CK_Prescott: 2748 case CK_K6: 2749 case CK_K6_2: 2750 case CK_K6_3: 2751 case CK_Athlon: 2752 case CK_AthlonThunderbird: 2753 case CK_Athlon4: 2754 case CK_AthlonXP: 2755 case CK_AthlonMP: 2756 case CK_Geode: 2757 // Only accept certain architectures when compiling in 32-bit mode. 2758 if (getTriple().getArch() != llvm::Triple::x86) 2759 return false; 2760 2761 // Fallthrough 2762 case CK_Nocona: 2763 case CK_Core2: 2764 case CK_Penryn: 2765 case CK_Bonnell: 2766 case CK_Silvermont: 2767 case CK_Nehalem: 2768 case CK_Westmere: 2769 case CK_SandyBridge: 2770 case CK_IvyBridge: 2771 case CK_Haswell: 2772 case CK_Broadwell: 2773 case CK_SkylakeClient: 2774 case CK_SkylakeServer: 2775 case CK_Cannonlake: 2776 case CK_KNL: 2777 case CK_Athlon64: 2778 case CK_Athlon64SSE3: 2779 case CK_AthlonFX: 2780 case CK_K8: 2781 case CK_K8SSE3: 2782 case CK_Opteron: 2783 case CK_OpteronSSE3: 2784 case CK_AMDFAM10: 2785 case CK_BTVER1: 2786 case CK_BTVER2: 2787 case CK_BDVER1: 2788 case CK_BDVER2: 2789 case CK_BDVER3: 2790 case CK_BDVER4: 2791 case CK_x86_64: 2792 return true; 2793 } 2794 llvm_unreachable("Unhandled CPU kind"); 2795 } 2796 2797 bool setFPMath(StringRef Name) override; 2798 2799 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2800 // Most of the non-ARM calling conventions are i386 conventions. 2801 switch (CC) { 2802 case CC_X86ThisCall: 2803 case CC_X86FastCall: 2804 case CC_X86StdCall: 2805 case CC_X86VectorCall: 2806 case CC_C: 2807 case CC_Swift: 2808 case CC_X86Pascal: 2809 case CC_IntelOclBicc: 2810 return CCCR_OK; 2811 default: 2812 return CCCR_Warning; 2813 } 2814 } 2815 2816 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2817 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2818 } 2819 2820 bool hasSjLjLowering() const override { 2821 return true; 2822 } 2823 2824 void setSupportedOpenCLOpts() override { 2825 getSupportedOpenCLOpts().setAll(); 2826 } 2827 }; 2828 2829 bool X86TargetInfo::setFPMath(StringRef Name) { 2830 if (Name == "387") { 2831 FPMath = FP_387; 2832 return true; 2833 } 2834 if (Name == "sse") { 2835 FPMath = FP_SSE; 2836 return true; 2837 } 2838 return false; 2839 } 2840 2841 bool X86TargetInfo::initFeatureMap( 2842 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2843 const std::vector<std::string> &FeaturesVec) const { 2844 // FIXME: This *really* should not be here. 2845 // X86_64 always has SSE2. 2846 if (getTriple().getArch() == llvm::Triple::x86_64) 2847 setFeatureEnabledImpl(Features, "sse2", true); 2848 2849 const CPUKind Kind = getCPUKind(CPU); 2850 2851 // Enable X87 for all X86 processors but Lakemont. 2852 if (Kind != CK_Lakemont) 2853 setFeatureEnabledImpl(Features, "x87", true); 2854 2855 switch (Kind) { 2856 case CK_Generic: 2857 case CK_i386: 2858 case CK_i486: 2859 case CK_i586: 2860 case CK_Pentium: 2861 case CK_i686: 2862 case CK_PentiumPro: 2863 case CK_Lakemont: 2864 break; 2865 case CK_PentiumMMX: 2866 case CK_Pentium2: 2867 case CK_K6: 2868 case CK_WinChipC6: 2869 setFeatureEnabledImpl(Features, "mmx", true); 2870 break; 2871 case CK_Pentium3: 2872 case CK_Pentium3M: 2873 case CK_C3_2: 2874 setFeatureEnabledImpl(Features, "sse", true); 2875 setFeatureEnabledImpl(Features, "fxsr", true); 2876 break; 2877 case CK_PentiumM: 2878 case CK_Pentium4: 2879 case CK_Pentium4M: 2880 case CK_x86_64: 2881 setFeatureEnabledImpl(Features, "sse2", true); 2882 setFeatureEnabledImpl(Features, "fxsr", true); 2883 break; 2884 case CK_Yonah: 2885 case CK_Prescott: 2886 case CK_Nocona: 2887 setFeatureEnabledImpl(Features, "sse3", true); 2888 setFeatureEnabledImpl(Features, "fxsr", true); 2889 setFeatureEnabledImpl(Features, "cx16", true); 2890 break; 2891 case CK_Core2: 2892 case CK_Bonnell: 2893 setFeatureEnabledImpl(Features, "ssse3", true); 2894 setFeatureEnabledImpl(Features, "fxsr", true); 2895 setFeatureEnabledImpl(Features, "cx16", true); 2896 break; 2897 case CK_Penryn: 2898 setFeatureEnabledImpl(Features, "sse4.1", true); 2899 setFeatureEnabledImpl(Features, "fxsr", true); 2900 setFeatureEnabledImpl(Features, "cx16", true); 2901 break; 2902 case CK_Cannonlake: 2903 setFeatureEnabledImpl(Features, "avx512ifma", true); 2904 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2905 setFeatureEnabledImpl(Features, "sha", true); 2906 setFeatureEnabledImpl(Features, "umip", true); 2907 // FALLTHROUGH 2908 case CK_SkylakeServer: 2909 setFeatureEnabledImpl(Features, "avx512f", true); 2910 setFeatureEnabledImpl(Features, "avx512cd", true); 2911 setFeatureEnabledImpl(Features, "avx512dq", true); 2912 setFeatureEnabledImpl(Features, "avx512bw", true); 2913 setFeatureEnabledImpl(Features, "avx512vl", true); 2914 setFeatureEnabledImpl(Features, "pku", true); 2915 setFeatureEnabledImpl(Features, "pcommit", true); 2916 setFeatureEnabledImpl(Features, "clwb", true); 2917 // FALLTHROUGH 2918 case CK_SkylakeClient: 2919 setFeatureEnabledImpl(Features, "xsavec", true); 2920 setFeatureEnabledImpl(Features, "xsaves", true); 2921 setFeatureEnabledImpl(Features, "mpx", true); 2922 setFeatureEnabledImpl(Features, "sgx", true); 2923 setFeatureEnabledImpl(Features, "clflushopt", true); 2924 // FALLTHROUGH 2925 case CK_Broadwell: 2926 setFeatureEnabledImpl(Features, "rdseed", true); 2927 setFeatureEnabledImpl(Features, "adx", true); 2928 // FALLTHROUGH 2929 case CK_Haswell: 2930 setFeatureEnabledImpl(Features, "avx2", true); 2931 setFeatureEnabledImpl(Features, "lzcnt", true); 2932 setFeatureEnabledImpl(Features, "bmi", true); 2933 setFeatureEnabledImpl(Features, "bmi2", true); 2934 setFeatureEnabledImpl(Features, "rtm", true); 2935 setFeatureEnabledImpl(Features, "fma", true); 2936 setFeatureEnabledImpl(Features, "movbe", true); 2937 // FALLTHROUGH 2938 case CK_IvyBridge: 2939 setFeatureEnabledImpl(Features, "rdrnd", true); 2940 setFeatureEnabledImpl(Features, "f16c", true); 2941 setFeatureEnabledImpl(Features, "fsgsbase", true); 2942 // FALLTHROUGH 2943 case CK_SandyBridge: 2944 setFeatureEnabledImpl(Features, "avx", true); 2945 setFeatureEnabledImpl(Features, "xsave", true); 2946 setFeatureEnabledImpl(Features, "xsaveopt", true); 2947 // FALLTHROUGH 2948 case CK_Westmere: 2949 case CK_Silvermont: 2950 setFeatureEnabledImpl(Features, "aes", true); 2951 setFeatureEnabledImpl(Features, "pclmul", true); 2952 // FALLTHROUGH 2953 case CK_Nehalem: 2954 setFeatureEnabledImpl(Features, "sse4.2", true); 2955 setFeatureEnabledImpl(Features, "fxsr", true); 2956 setFeatureEnabledImpl(Features, "cx16", true); 2957 break; 2958 case CK_KNL: 2959 setFeatureEnabledImpl(Features, "avx512f", true); 2960 setFeatureEnabledImpl(Features, "avx512cd", true); 2961 setFeatureEnabledImpl(Features, "avx512er", true); 2962 setFeatureEnabledImpl(Features, "avx512pf", true); 2963 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2964 setFeatureEnabledImpl(Features, "fxsr", true); 2965 setFeatureEnabledImpl(Features, "rdseed", true); 2966 setFeatureEnabledImpl(Features, "adx", true); 2967 setFeatureEnabledImpl(Features, "lzcnt", true); 2968 setFeatureEnabledImpl(Features, "bmi", true); 2969 setFeatureEnabledImpl(Features, "bmi2", true); 2970 setFeatureEnabledImpl(Features, "rtm", true); 2971 setFeatureEnabledImpl(Features, "fma", true); 2972 setFeatureEnabledImpl(Features, "rdrnd", true); 2973 setFeatureEnabledImpl(Features, "f16c", true); 2974 setFeatureEnabledImpl(Features, "fsgsbase", true); 2975 setFeatureEnabledImpl(Features, "aes", true); 2976 setFeatureEnabledImpl(Features, "pclmul", true); 2977 setFeatureEnabledImpl(Features, "cx16", true); 2978 setFeatureEnabledImpl(Features, "xsaveopt", true); 2979 setFeatureEnabledImpl(Features, "xsave", true); 2980 setFeatureEnabledImpl(Features, "movbe", true); 2981 break; 2982 case CK_K6_2: 2983 case CK_K6_3: 2984 case CK_WinChip2: 2985 case CK_C3: 2986 setFeatureEnabledImpl(Features, "3dnow", true); 2987 break; 2988 case CK_Athlon: 2989 case CK_AthlonThunderbird: 2990 case CK_Geode: 2991 setFeatureEnabledImpl(Features, "3dnowa", true); 2992 break; 2993 case CK_Athlon4: 2994 case CK_AthlonXP: 2995 case CK_AthlonMP: 2996 setFeatureEnabledImpl(Features, "sse", true); 2997 setFeatureEnabledImpl(Features, "3dnowa", true); 2998 setFeatureEnabledImpl(Features, "fxsr", true); 2999 break; 3000 case CK_K8: 3001 case CK_Opteron: 3002 case CK_Athlon64: 3003 case CK_AthlonFX: 3004 setFeatureEnabledImpl(Features, "sse2", true); 3005 setFeatureEnabledImpl(Features, "3dnowa", true); 3006 setFeatureEnabledImpl(Features, "fxsr", true); 3007 break; 3008 case CK_AMDFAM10: 3009 setFeatureEnabledImpl(Features, "sse4a", true); 3010 setFeatureEnabledImpl(Features, "lzcnt", true); 3011 setFeatureEnabledImpl(Features, "popcnt", true); 3012 // FALLTHROUGH 3013 case CK_K8SSE3: 3014 case CK_OpteronSSE3: 3015 case CK_Athlon64SSE3: 3016 setFeatureEnabledImpl(Features, "sse3", true); 3017 setFeatureEnabledImpl(Features, "3dnowa", true); 3018 setFeatureEnabledImpl(Features, "fxsr", true); 3019 break; 3020 case CK_BTVER2: 3021 setFeatureEnabledImpl(Features, "avx", true); 3022 setFeatureEnabledImpl(Features, "aes", true); 3023 setFeatureEnabledImpl(Features, "pclmul", true); 3024 setFeatureEnabledImpl(Features, "bmi", true); 3025 setFeatureEnabledImpl(Features, "f16c", true); 3026 setFeatureEnabledImpl(Features, "xsaveopt", true); 3027 // FALLTHROUGH 3028 case CK_BTVER1: 3029 setFeatureEnabledImpl(Features, "ssse3", true); 3030 setFeatureEnabledImpl(Features, "sse4a", true); 3031 setFeatureEnabledImpl(Features, "lzcnt", true); 3032 setFeatureEnabledImpl(Features, "popcnt", true); 3033 setFeatureEnabledImpl(Features, "prfchw", true); 3034 setFeatureEnabledImpl(Features, "cx16", true); 3035 setFeatureEnabledImpl(Features, "fxsr", true); 3036 break; 3037 case CK_BDVER4: 3038 setFeatureEnabledImpl(Features, "avx2", true); 3039 setFeatureEnabledImpl(Features, "bmi2", true); 3040 setFeatureEnabledImpl(Features, "mwaitx", true); 3041 // FALLTHROUGH 3042 case CK_BDVER3: 3043 setFeatureEnabledImpl(Features, "fsgsbase", true); 3044 setFeatureEnabledImpl(Features, "xsaveopt", true); 3045 // FALLTHROUGH 3046 case CK_BDVER2: 3047 setFeatureEnabledImpl(Features, "bmi", true); 3048 setFeatureEnabledImpl(Features, "fma", true); 3049 setFeatureEnabledImpl(Features, "f16c", true); 3050 setFeatureEnabledImpl(Features, "tbm", true); 3051 // FALLTHROUGH 3052 case CK_BDVER1: 3053 // xop implies avx, sse4a and fma4. 3054 setFeatureEnabledImpl(Features, "xop", true); 3055 setFeatureEnabledImpl(Features, "lzcnt", true); 3056 setFeatureEnabledImpl(Features, "aes", true); 3057 setFeatureEnabledImpl(Features, "pclmul", true); 3058 setFeatureEnabledImpl(Features, "prfchw", true); 3059 setFeatureEnabledImpl(Features, "cx16", true); 3060 setFeatureEnabledImpl(Features, "fxsr", true); 3061 setFeatureEnabledImpl(Features, "xsave", true); 3062 break; 3063 } 3064 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3065 return false; 3066 3067 // Can't do this earlier because we need to be able to explicitly enable 3068 // or disable these features and the things that they depend upon. 3069 3070 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3071 auto I = Features.find("sse4.2"); 3072 if (I != Features.end() && I->getValue() && 3073 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3074 FeaturesVec.end()) 3075 Features["popcnt"] = true; 3076 3077 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3078 I = Features.find("3dnow"); 3079 if (I != Features.end() && I->getValue() && 3080 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3081 FeaturesVec.end()) 3082 Features["prfchw"] = true; 3083 3084 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3085 // then enable MMX. 3086 I = Features.find("sse"); 3087 if (I != Features.end() && I->getValue() && 3088 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3089 FeaturesVec.end()) 3090 Features["mmx"] = true; 3091 3092 return true; 3093 } 3094 3095 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3096 X86SSEEnum Level, bool Enabled) { 3097 if (Enabled) { 3098 switch (Level) { 3099 case AVX512F: 3100 Features["avx512f"] = true; 3101 case AVX2: 3102 Features["avx2"] = true; 3103 case AVX: 3104 Features["avx"] = true; 3105 Features["xsave"] = true; 3106 case SSE42: 3107 Features["sse4.2"] = true; 3108 case SSE41: 3109 Features["sse4.1"] = true; 3110 case SSSE3: 3111 Features["ssse3"] = true; 3112 case SSE3: 3113 Features["sse3"] = true; 3114 case SSE2: 3115 Features["sse2"] = true; 3116 case SSE1: 3117 Features["sse"] = true; 3118 case NoSSE: 3119 break; 3120 } 3121 return; 3122 } 3123 3124 switch (Level) { 3125 case NoSSE: 3126 case SSE1: 3127 Features["sse"] = false; 3128 case SSE2: 3129 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3130 Features["sha"] = false; 3131 case SSE3: 3132 Features["sse3"] = false; 3133 setXOPLevel(Features, NoXOP, false); 3134 case SSSE3: 3135 Features["ssse3"] = false; 3136 case SSE41: 3137 Features["sse4.1"] = false; 3138 case SSE42: 3139 Features["sse4.2"] = false; 3140 case AVX: 3141 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3142 Features["xsaveopt"] = false; 3143 setXOPLevel(Features, FMA4, false); 3144 case AVX2: 3145 Features["avx2"] = false; 3146 case AVX512F: 3147 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3148 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3149 Features["avx512vl"] = Features["avx512vbmi"] = 3150 Features["avx512ifma"] = false; 3151 } 3152 } 3153 3154 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3155 MMX3DNowEnum Level, bool Enabled) { 3156 if (Enabled) { 3157 switch (Level) { 3158 case AMD3DNowAthlon: 3159 Features["3dnowa"] = true; 3160 case AMD3DNow: 3161 Features["3dnow"] = true; 3162 case MMX: 3163 Features["mmx"] = true; 3164 case NoMMX3DNow: 3165 break; 3166 } 3167 return; 3168 } 3169 3170 switch (Level) { 3171 case NoMMX3DNow: 3172 case MMX: 3173 Features["mmx"] = false; 3174 case AMD3DNow: 3175 Features["3dnow"] = false; 3176 case AMD3DNowAthlon: 3177 Features["3dnowa"] = false; 3178 } 3179 } 3180 3181 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3182 bool Enabled) { 3183 if (Enabled) { 3184 switch (Level) { 3185 case XOP: 3186 Features["xop"] = true; 3187 case FMA4: 3188 Features["fma4"] = true; 3189 setSSELevel(Features, AVX, true); 3190 case SSE4A: 3191 Features["sse4a"] = true; 3192 setSSELevel(Features, SSE3, true); 3193 case NoXOP: 3194 break; 3195 } 3196 return; 3197 } 3198 3199 switch (Level) { 3200 case NoXOP: 3201 case SSE4A: 3202 Features["sse4a"] = false; 3203 case FMA4: 3204 Features["fma4"] = false; 3205 case XOP: 3206 Features["xop"] = false; 3207 } 3208 } 3209 3210 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3211 StringRef Name, bool Enabled) { 3212 // This is a bit of a hack to deal with the sse4 target feature when used 3213 // as part of the target attribute. We handle sse4 correctly everywhere 3214 // else. See below for more information on how we handle the sse4 options. 3215 if (Name != "sse4") 3216 Features[Name] = Enabled; 3217 3218 if (Name == "mmx") { 3219 setMMXLevel(Features, MMX, Enabled); 3220 } else if (Name == "sse") { 3221 setSSELevel(Features, SSE1, Enabled); 3222 } else if (Name == "sse2") { 3223 setSSELevel(Features, SSE2, Enabled); 3224 } else if (Name == "sse3") { 3225 setSSELevel(Features, SSE3, Enabled); 3226 } else if (Name == "ssse3") { 3227 setSSELevel(Features, SSSE3, Enabled); 3228 } else if (Name == "sse4.2") { 3229 setSSELevel(Features, SSE42, Enabled); 3230 } else if (Name == "sse4.1") { 3231 setSSELevel(Features, SSE41, Enabled); 3232 } else if (Name == "3dnow") { 3233 setMMXLevel(Features, AMD3DNow, Enabled); 3234 } else if (Name == "3dnowa") { 3235 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3236 } else if (Name == "aes") { 3237 if (Enabled) 3238 setSSELevel(Features, SSE2, Enabled); 3239 } else if (Name == "pclmul") { 3240 if (Enabled) 3241 setSSELevel(Features, SSE2, Enabled); 3242 } else if (Name == "avx") { 3243 setSSELevel(Features, AVX, Enabled); 3244 } else if (Name == "avx2") { 3245 setSSELevel(Features, AVX2, Enabled); 3246 } else if (Name == "avx512f") { 3247 setSSELevel(Features, AVX512F, Enabled); 3248 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3249 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3250 Name == "avx512vbmi" || Name == "avx512ifma") { 3251 if (Enabled) 3252 setSSELevel(Features, AVX512F, Enabled); 3253 } else if (Name == "fma") { 3254 if (Enabled) 3255 setSSELevel(Features, AVX, Enabled); 3256 } else if (Name == "fma4") { 3257 setXOPLevel(Features, FMA4, Enabled); 3258 } else if (Name == "xop") { 3259 setXOPLevel(Features, XOP, Enabled); 3260 } else if (Name == "sse4a") { 3261 setXOPLevel(Features, SSE4A, Enabled); 3262 } else if (Name == "f16c") { 3263 if (Enabled) 3264 setSSELevel(Features, AVX, Enabled); 3265 } else if (Name == "sha") { 3266 if (Enabled) 3267 setSSELevel(Features, SSE2, Enabled); 3268 } else if (Name == "sse4") { 3269 // We can get here via the __target__ attribute since that's not controlled 3270 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3271 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3272 // disabled. 3273 if (Enabled) 3274 setSSELevel(Features, SSE42, Enabled); 3275 else 3276 setSSELevel(Features, SSE41, Enabled); 3277 } else if (Name == "xsave") { 3278 if (!Enabled) 3279 Features["xsaveopt"] = false; 3280 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3281 if (Enabled) 3282 Features["xsave"] = true; 3283 } 3284 } 3285 3286 /// handleTargetFeatures - Perform initialization based on the user 3287 /// configured set of features. 3288 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3289 DiagnosticsEngine &Diags) { 3290 for (const auto &Feature : Features) { 3291 if (Feature[0] != '+') 3292 continue; 3293 3294 if (Feature == "+aes") { 3295 HasAES = true; 3296 } else if (Feature == "+pclmul") { 3297 HasPCLMUL = true; 3298 } else if (Feature == "+lzcnt") { 3299 HasLZCNT = true; 3300 } else if (Feature == "+rdrnd") { 3301 HasRDRND = true; 3302 } else if (Feature == "+fsgsbase") { 3303 HasFSGSBASE = true; 3304 } else if (Feature == "+bmi") { 3305 HasBMI = true; 3306 } else if (Feature == "+bmi2") { 3307 HasBMI2 = true; 3308 } else if (Feature == "+popcnt") { 3309 HasPOPCNT = true; 3310 } else if (Feature == "+rtm") { 3311 HasRTM = true; 3312 } else if (Feature == "+prfchw") { 3313 HasPRFCHW = true; 3314 } else if (Feature == "+rdseed") { 3315 HasRDSEED = true; 3316 } else if (Feature == "+adx") { 3317 HasADX = true; 3318 } else if (Feature == "+tbm") { 3319 HasTBM = true; 3320 } else if (Feature == "+fma") { 3321 HasFMA = true; 3322 } else if (Feature == "+f16c") { 3323 HasF16C = true; 3324 } else if (Feature == "+avx512cd") { 3325 HasAVX512CD = true; 3326 } else if (Feature == "+avx512er") { 3327 HasAVX512ER = true; 3328 } else if (Feature == "+avx512pf") { 3329 HasAVX512PF = true; 3330 } else if (Feature == "+avx512dq") { 3331 HasAVX512DQ = true; 3332 } else if (Feature == "+avx512bw") { 3333 HasAVX512BW = true; 3334 } else if (Feature == "+avx512vl") { 3335 HasAVX512VL = true; 3336 } else if (Feature == "+avx512vbmi") { 3337 HasAVX512VBMI = true; 3338 } else if (Feature == "+avx512ifma") { 3339 HasAVX512IFMA = true; 3340 } else if (Feature == "+sha") { 3341 HasSHA = true; 3342 } else if (Feature == "+mpx") { 3343 HasMPX = true; 3344 } else if (Feature == "+movbe") { 3345 HasMOVBE = true; 3346 } else if (Feature == "+sgx") { 3347 HasSGX = true; 3348 } else if (Feature == "+cx16") { 3349 HasCX16 = true; 3350 } else if (Feature == "+fxsr") { 3351 HasFXSR = true; 3352 } else if (Feature == "+xsave") { 3353 HasXSAVE = true; 3354 } else if (Feature == "+xsaveopt") { 3355 HasXSAVEOPT = true; 3356 } else if (Feature == "+xsavec") { 3357 HasXSAVEC = true; 3358 } else if (Feature == "+xsaves") { 3359 HasXSAVES = true; 3360 } else if (Feature == "+mwaitx") { 3361 HasMWAITX = true; 3362 } else if (Feature == "+pku") { 3363 HasPKU = true; 3364 } else if (Feature == "+clflushopt") { 3365 HasCLFLUSHOPT = true; 3366 } else if (Feature == "+pcommit") { 3367 HasPCOMMIT = true; 3368 } else if (Feature == "+clwb") { 3369 HasCLWB = true; 3370 } else if (Feature == "+umip") { 3371 HasUMIP = true; 3372 } else if (Feature == "+prefetchwt1") { 3373 HasPREFETCHWT1 = true; 3374 } 3375 3376 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3377 .Case("+avx512f", AVX512F) 3378 .Case("+avx2", AVX2) 3379 .Case("+avx", AVX) 3380 .Case("+sse4.2", SSE42) 3381 .Case("+sse4.1", SSE41) 3382 .Case("+ssse3", SSSE3) 3383 .Case("+sse3", SSE3) 3384 .Case("+sse2", SSE2) 3385 .Case("+sse", SSE1) 3386 .Default(NoSSE); 3387 SSELevel = std::max(SSELevel, Level); 3388 3389 MMX3DNowEnum ThreeDNowLevel = 3390 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3391 .Case("+3dnowa", AMD3DNowAthlon) 3392 .Case("+3dnow", AMD3DNow) 3393 .Case("+mmx", MMX) 3394 .Default(NoMMX3DNow); 3395 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3396 3397 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3398 .Case("+xop", XOP) 3399 .Case("+fma4", FMA4) 3400 .Case("+sse4a", SSE4A) 3401 .Default(NoXOP); 3402 XOPLevel = std::max(XOPLevel, XLevel); 3403 } 3404 3405 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3406 // matches the selected sse level. 3407 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3408 (FPMath == FP_387 && SSELevel >= SSE1)) { 3409 Diags.Report(diag::err_target_unsupported_fpmath) << 3410 (FPMath == FP_SSE ? "sse" : "387"); 3411 return false; 3412 } 3413 3414 SimdDefaultAlign = 3415 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3416 return true; 3417 } 3418 3419 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3420 /// definitions for this particular subtarget. 3421 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3422 MacroBuilder &Builder) const { 3423 // Target identification. 3424 if (getTriple().getArch() == llvm::Triple::x86_64) { 3425 Builder.defineMacro("__amd64__"); 3426 Builder.defineMacro("__amd64"); 3427 Builder.defineMacro("__x86_64"); 3428 Builder.defineMacro("__x86_64__"); 3429 if (getTriple().getArchName() == "x86_64h") { 3430 Builder.defineMacro("__x86_64h"); 3431 Builder.defineMacro("__x86_64h__"); 3432 } 3433 } else { 3434 DefineStd(Builder, "i386", Opts); 3435 } 3436 3437 // Subtarget options. 3438 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3439 // truly should be based on -mtune options. 3440 switch (CPU) { 3441 case CK_Generic: 3442 break; 3443 case CK_i386: 3444 // The rest are coming from the i386 define above. 3445 Builder.defineMacro("__tune_i386__"); 3446 break; 3447 case CK_i486: 3448 case CK_WinChipC6: 3449 case CK_WinChip2: 3450 case CK_C3: 3451 defineCPUMacros(Builder, "i486"); 3452 break; 3453 case CK_PentiumMMX: 3454 Builder.defineMacro("__pentium_mmx__"); 3455 Builder.defineMacro("__tune_pentium_mmx__"); 3456 // Fallthrough 3457 case CK_i586: 3458 case CK_Pentium: 3459 defineCPUMacros(Builder, "i586"); 3460 defineCPUMacros(Builder, "pentium"); 3461 break; 3462 case CK_Pentium3: 3463 case CK_Pentium3M: 3464 case CK_PentiumM: 3465 Builder.defineMacro("__tune_pentium3__"); 3466 // Fallthrough 3467 case CK_Pentium2: 3468 case CK_C3_2: 3469 Builder.defineMacro("__tune_pentium2__"); 3470 // Fallthrough 3471 case CK_PentiumPro: 3472 Builder.defineMacro("__tune_i686__"); 3473 Builder.defineMacro("__tune_pentiumpro__"); 3474 // Fallthrough 3475 case CK_i686: 3476 Builder.defineMacro("__i686"); 3477 Builder.defineMacro("__i686__"); 3478 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3479 Builder.defineMacro("__pentiumpro"); 3480 Builder.defineMacro("__pentiumpro__"); 3481 break; 3482 case CK_Pentium4: 3483 case CK_Pentium4M: 3484 defineCPUMacros(Builder, "pentium4"); 3485 break; 3486 case CK_Yonah: 3487 case CK_Prescott: 3488 case CK_Nocona: 3489 defineCPUMacros(Builder, "nocona"); 3490 break; 3491 case CK_Core2: 3492 case CK_Penryn: 3493 defineCPUMacros(Builder, "core2"); 3494 break; 3495 case CK_Bonnell: 3496 defineCPUMacros(Builder, "atom"); 3497 break; 3498 case CK_Silvermont: 3499 defineCPUMacros(Builder, "slm"); 3500 break; 3501 case CK_Nehalem: 3502 case CK_Westmere: 3503 case CK_SandyBridge: 3504 case CK_IvyBridge: 3505 case CK_Haswell: 3506 case CK_Broadwell: 3507 case CK_SkylakeClient: 3508 // FIXME: Historically, we defined this legacy name, it would be nice to 3509 // remove it at some point. We've never exposed fine-grained names for 3510 // recent primary x86 CPUs, and we should keep it that way. 3511 defineCPUMacros(Builder, "corei7"); 3512 break; 3513 case CK_SkylakeServer: 3514 defineCPUMacros(Builder, "skx"); 3515 break; 3516 case CK_Cannonlake: 3517 break; 3518 case CK_KNL: 3519 defineCPUMacros(Builder, "knl"); 3520 break; 3521 case CK_Lakemont: 3522 Builder.defineMacro("__tune_lakemont__"); 3523 break; 3524 case CK_K6_2: 3525 Builder.defineMacro("__k6_2__"); 3526 Builder.defineMacro("__tune_k6_2__"); 3527 // Fallthrough 3528 case CK_K6_3: 3529 if (CPU != CK_K6_2) { // In case of fallthrough 3530 // FIXME: GCC may be enabling these in cases where some other k6 3531 // architecture is specified but -m3dnow is explicitly provided. The 3532 // exact semantics need to be determined and emulated here. 3533 Builder.defineMacro("__k6_3__"); 3534 Builder.defineMacro("__tune_k6_3__"); 3535 } 3536 // Fallthrough 3537 case CK_K6: 3538 defineCPUMacros(Builder, "k6"); 3539 break; 3540 case CK_Athlon: 3541 case CK_AthlonThunderbird: 3542 case CK_Athlon4: 3543 case CK_AthlonXP: 3544 case CK_AthlonMP: 3545 defineCPUMacros(Builder, "athlon"); 3546 if (SSELevel != NoSSE) { 3547 Builder.defineMacro("__athlon_sse__"); 3548 Builder.defineMacro("__tune_athlon_sse__"); 3549 } 3550 break; 3551 case CK_K8: 3552 case CK_K8SSE3: 3553 case CK_x86_64: 3554 case CK_Opteron: 3555 case CK_OpteronSSE3: 3556 case CK_Athlon64: 3557 case CK_Athlon64SSE3: 3558 case CK_AthlonFX: 3559 defineCPUMacros(Builder, "k8"); 3560 break; 3561 case CK_AMDFAM10: 3562 defineCPUMacros(Builder, "amdfam10"); 3563 break; 3564 case CK_BTVER1: 3565 defineCPUMacros(Builder, "btver1"); 3566 break; 3567 case CK_BTVER2: 3568 defineCPUMacros(Builder, "btver2"); 3569 break; 3570 case CK_BDVER1: 3571 defineCPUMacros(Builder, "bdver1"); 3572 break; 3573 case CK_BDVER2: 3574 defineCPUMacros(Builder, "bdver2"); 3575 break; 3576 case CK_BDVER3: 3577 defineCPUMacros(Builder, "bdver3"); 3578 break; 3579 case CK_BDVER4: 3580 defineCPUMacros(Builder, "bdver4"); 3581 break; 3582 case CK_Geode: 3583 defineCPUMacros(Builder, "geode"); 3584 break; 3585 } 3586 3587 // Target properties. 3588 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3589 3590 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3591 // functions in glibc header files that use FP Stack inline asm which the 3592 // backend can't deal with (PR879). 3593 Builder.defineMacro("__NO_MATH_INLINES"); 3594 3595 if (HasAES) 3596 Builder.defineMacro("__AES__"); 3597 3598 if (HasPCLMUL) 3599 Builder.defineMacro("__PCLMUL__"); 3600 3601 if (HasLZCNT) 3602 Builder.defineMacro("__LZCNT__"); 3603 3604 if (HasRDRND) 3605 Builder.defineMacro("__RDRND__"); 3606 3607 if (HasFSGSBASE) 3608 Builder.defineMacro("__FSGSBASE__"); 3609 3610 if (HasBMI) 3611 Builder.defineMacro("__BMI__"); 3612 3613 if (HasBMI2) 3614 Builder.defineMacro("__BMI2__"); 3615 3616 if (HasPOPCNT) 3617 Builder.defineMacro("__POPCNT__"); 3618 3619 if (HasRTM) 3620 Builder.defineMacro("__RTM__"); 3621 3622 if (HasPRFCHW) 3623 Builder.defineMacro("__PRFCHW__"); 3624 3625 if (HasRDSEED) 3626 Builder.defineMacro("__RDSEED__"); 3627 3628 if (HasADX) 3629 Builder.defineMacro("__ADX__"); 3630 3631 if (HasTBM) 3632 Builder.defineMacro("__TBM__"); 3633 3634 if (HasMWAITX) 3635 Builder.defineMacro("__MWAITX__"); 3636 3637 switch (XOPLevel) { 3638 case XOP: 3639 Builder.defineMacro("__XOP__"); 3640 case FMA4: 3641 Builder.defineMacro("__FMA4__"); 3642 case SSE4A: 3643 Builder.defineMacro("__SSE4A__"); 3644 case NoXOP: 3645 break; 3646 } 3647 3648 if (HasFMA) 3649 Builder.defineMacro("__FMA__"); 3650 3651 if (HasF16C) 3652 Builder.defineMacro("__F16C__"); 3653 3654 if (HasAVX512CD) 3655 Builder.defineMacro("__AVX512CD__"); 3656 if (HasAVX512ER) 3657 Builder.defineMacro("__AVX512ER__"); 3658 if (HasAVX512PF) 3659 Builder.defineMacro("__AVX512PF__"); 3660 if (HasAVX512DQ) 3661 Builder.defineMacro("__AVX512DQ__"); 3662 if (HasAVX512BW) 3663 Builder.defineMacro("__AVX512BW__"); 3664 if (HasAVX512VL) 3665 Builder.defineMacro("__AVX512VL__"); 3666 if (HasAVX512VBMI) 3667 Builder.defineMacro("__AVX512VBMI__"); 3668 if (HasAVX512IFMA) 3669 Builder.defineMacro("__AVX512IFMA__"); 3670 3671 if (HasSHA) 3672 Builder.defineMacro("__SHA__"); 3673 3674 if (HasFXSR) 3675 Builder.defineMacro("__FXSR__"); 3676 if (HasXSAVE) 3677 Builder.defineMacro("__XSAVE__"); 3678 if (HasXSAVEOPT) 3679 Builder.defineMacro("__XSAVEOPT__"); 3680 if (HasXSAVEC) 3681 Builder.defineMacro("__XSAVEC__"); 3682 if (HasXSAVES) 3683 Builder.defineMacro("__XSAVES__"); 3684 if (HasPKU) 3685 Builder.defineMacro("__PKU__"); 3686 if (HasCX16) 3687 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3688 3689 // Each case falls through to the previous one here. 3690 switch (SSELevel) { 3691 case AVX512F: 3692 Builder.defineMacro("__AVX512F__"); 3693 case AVX2: 3694 Builder.defineMacro("__AVX2__"); 3695 case AVX: 3696 Builder.defineMacro("__AVX__"); 3697 case SSE42: 3698 Builder.defineMacro("__SSE4_2__"); 3699 case SSE41: 3700 Builder.defineMacro("__SSE4_1__"); 3701 case SSSE3: 3702 Builder.defineMacro("__SSSE3__"); 3703 case SSE3: 3704 Builder.defineMacro("__SSE3__"); 3705 case SSE2: 3706 Builder.defineMacro("__SSE2__"); 3707 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3708 case SSE1: 3709 Builder.defineMacro("__SSE__"); 3710 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3711 case NoSSE: 3712 break; 3713 } 3714 3715 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3716 switch (SSELevel) { 3717 case AVX512F: 3718 case AVX2: 3719 case AVX: 3720 case SSE42: 3721 case SSE41: 3722 case SSSE3: 3723 case SSE3: 3724 case SSE2: 3725 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3726 break; 3727 case SSE1: 3728 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3729 break; 3730 default: 3731 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3732 } 3733 } 3734 3735 // Each case falls through to the previous one here. 3736 switch (MMX3DNowLevel) { 3737 case AMD3DNowAthlon: 3738 Builder.defineMacro("__3dNOW_A__"); 3739 case AMD3DNow: 3740 Builder.defineMacro("__3dNOW__"); 3741 case MMX: 3742 Builder.defineMacro("__MMX__"); 3743 case NoMMX3DNow: 3744 break; 3745 } 3746 3747 if (CPU >= CK_i486) { 3748 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3749 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3750 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3751 } 3752 if (CPU >= CK_i586) 3753 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3754 } 3755 3756 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3757 return llvm::StringSwitch<bool>(Feature) 3758 .Case("aes", HasAES) 3759 .Case("avx", SSELevel >= AVX) 3760 .Case("avx2", SSELevel >= AVX2) 3761 .Case("avx512f", SSELevel >= AVX512F) 3762 .Case("avx512cd", HasAVX512CD) 3763 .Case("avx512er", HasAVX512ER) 3764 .Case("avx512pf", HasAVX512PF) 3765 .Case("avx512dq", HasAVX512DQ) 3766 .Case("avx512bw", HasAVX512BW) 3767 .Case("avx512vl", HasAVX512VL) 3768 .Case("avx512vbmi", HasAVX512VBMI) 3769 .Case("avx512ifma", HasAVX512IFMA) 3770 .Case("bmi", HasBMI) 3771 .Case("bmi2", HasBMI2) 3772 .Case("clflushopt", HasCLFLUSHOPT) 3773 .Case("clwb", HasCLWB) 3774 .Case("cx16", HasCX16) 3775 .Case("f16c", HasF16C) 3776 .Case("fma", HasFMA) 3777 .Case("fma4", XOPLevel >= FMA4) 3778 .Case("fsgsbase", HasFSGSBASE) 3779 .Case("fxsr", HasFXSR) 3780 .Case("lzcnt", HasLZCNT) 3781 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3782 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3783 .Case("mmx", MMX3DNowLevel >= MMX) 3784 .Case("movbe", HasMOVBE) 3785 .Case("mpx", HasMPX) 3786 .Case("pclmul", HasPCLMUL) 3787 .Case("pcommit", HasPCOMMIT) 3788 .Case("pku", HasPKU) 3789 .Case("popcnt", HasPOPCNT) 3790 .Case("prefetchwt1", HasPREFETCHWT1) 3791 .Case("prfchw", HasPRFCHW) 3792 .Case("rdrnd", HasRDRND) 3793 .Case("rdseed", HasRDSEED) 3794 .Case("rtm", HasRTM) 3795 .Case("sgx", HasSGX) 3796 .Case("sha", HasSHA) 3797 .Case("sse", SSELevel >= SSE1) 3798 .Case("sse2", SSELevel >= SSE2) 3799 .Case("sse3", SSELevel >= SSE3) 3800 .Case("ssse3", SSELevel >= SSSE3) 3801 .Case("sse4.1", SSELevel >= SSE41) 3802 .Case("sse4.2", SSELevel >= SSE42) 3803 .Case("sse4a", XOPLevel >= SSE4A) 3804 .Case("tbm", HasTBM) 3805 .Case("umip", HasUMIP) 3806 .Case("x86", true) 3807 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3808 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3809 .Case("xop", XOPLevel >= XOP) 3810 .Case("xsave", HasXSAVE) 3811 .Case("xsavec", HasXSAVEC) 3812 .Case("xsaves", HasXSAVES) 3813 .Case("xsaveopt", HasXSAVEOPT) 3814 .Default(false); 3815 } 3816 3817 // We can't use a generic validation scheme for the features accepted here 3818 // versus subtarget features accepted in the target attribute because the 3819 // bitfield structure that's initialized in the runtime only supports the 3820 // below currently rather than the full range of subtarget features. (See 3821 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3822 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3823 return llvm::StringSwitch<bool>(FeatureStr) 3824 .Case("cmov", true) 3825 .Case("mmx", true) 3826 .Case("popcnt", true) 3827 .Case("sse", true) 3828 .Case("sse2", true) 3829 .Case("sse3", true) 3830 .Case("ssse3", true) 3831 .Case("sse4.1", true) 3832 .Case("sse4.2", true) 3833 .Case("avx", true) 3834 .Case("avx2", true) 3835 .Case("sse4a", true) 3836 .Case("fma4", true) 3837 .Case("xop", true) 3838 .Case("fma", true) 3839 .Case("avx512f", true) 3840 .Case("bmi", true) 3841 .Case("bmi2", true) 3842 .Case("aes", true) 3843 .Case("pclmul", true) 3844 .Case("avx512vl", true) 3845 .Case("avx512bw", true) 3846 .Case("avx512dq", true) 3847 .Case("avx512cd", true) 3848 .Case("avx512er", true) 3849 .Case("avx512pf", true) 3850 .Case("avx512vbmi", true) 3851 .Case("avx512ifma", true) 3852 .Default(false); 3853 } 3854 3855 bool 3856 X86TargetInfo::validateAsmConstraint(const char *&Name, 3857 TargetInfo::ConstraintInfo &Info) const { 3858 switch (*Name) { 3859 default: return false; 3860 // Constant constraints. 3861 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3862 // instructions. 3863 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3864 // x86_64 instructions. 3865 case 's': 3866 Info.setRequiresImmediate(); 3867 return true; 3868 case 'I': 3869 Info.setRequiresImmediate(0, 31); 3870 return true; 3871 case 'J': 3872 Info.setRequiresImmediate(0, 63); 3873 return true; 3874 case 'K': 3875 Info.setRequiresImmediate(-128, 127); 3876 return true; 3877 case 'L': 3878 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3879 return true; 3880 case 'M': 3881 Info.setRequiresImmediate(0, 3); 3882 return true; 3883 case 'N': 3884 Info.setRequiresImmediate(0, 255); 3885 return true; 3886 case 'O': 3887 Info.setRequiresImmediate(0, 127); 3888 return true; 3889 // Register constraints. 3890 case 'Y': // 'Y' is the first character for several 2-character constraints. 3891 // Shift the pointer to the second character of the constraint. 3892 Name++; 3893 switch (*Name) { 3894 default: 3895 return false; 3896 case '0': // First SSE register. 3897 case 't': // Any SSE register, when SSE2 is enabled. 3898 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3899 case 'm': // Any MMX register, when inter-unit moves enabled. 3900 Info.setAllowsRegister(); 3901 return true; 3902 } 3903 case 'f': // Any x87 floating point stack register. 3904 // Constraint 'f' cannot be used for output operands. 3905 if (Info.ConstraintStr[0] == '=') 3906 return false; 3907 Info.setAllowsRegister(); 3908 return true; 3909 case 'a': // eax. 3910 case 'b': // ebx. 3911 case 'c': // ecx. 3912 case 'd': // edx. 3913 case 'S': // esi. 3914 case 'D': // edi. 3915 case 'A': // edx:eax. 3916 case 't': // Top of floating point stack. 3917 case 'u': // Second from top of floating point stack. 3918 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3919 case 'y': // Any MMX register. 3920 case 'x': // Any SSE register. 3921 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3922 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3923 case 'l': // "Index" registers: any general register that can be used as an 3924 // index in a base+index memory access. 3925 Info.setAllowsRegister(); 3926 return true; 3927 // Floating point constant constraints. 3928 case 'C': // SSE floating point constant. 3929 case 'G': // x87 floating point constant. 3930 return true; 3931 } 3932 } 3933 3934 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3935 unsigned Size) const { 3936 // Strip off constraint modifiers. 3937 while (Constraint[0] == '=' || 3938 Constraint[0] == '+' || 3939 Constraint[0] == '&') 3940 Constraint = Constraint.substr(1); 3941 3942 return validateOperandSize(Constraint, Size); 3943 } 3944 3945 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3946 unsigned Size) const { 3947 return validateOperandSize(Constraint, Size); 3948 } 3949 3950 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3951 unsigned Size) const { 3952 switch (Constraint[0]) { 3953 default: break; 3954 case 'y': 3955 return Size <= 64; 3956 case 'f': 3957 case 't': 3958 case 'u': 3959 return Size <= 128; 3960 case 'x': 3961 if (SSELevel >= AVX512F) 3962 // 512-bit zmm registers can be used if target supports AVX512F. 3963 return Size <= 512U; 3964 else if (SSELevel >= AVX) 3965 // 256-bit ymm registers can be used if target supports AVX. 3966 return Size <= 256U; 3967 return Size <= 128U; 3968 case 'Y': 3969 // 'Y' is the first character for several 2-character constraints. 3970 switch (Constraint[1]) { 3971 default: break; 3972 case 'm': 3973 // 'Ym' is synonymous with 'y'. 3974 return Size <= 64; 3975 case 'i': 3976 case 't': 3977 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3978 if (SSELevel >= AVX512F) 3979 return Size <= 512U; 3980 else if (SSELevel >= AVX) 3981 return Size <= 256U; 3982 return SSELevel >= SSE2 && Size <= 128U; 3983 } 3984 3985 } 3986 3987 return true; 3988 } 3989 3990 std::string 3991 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3992 switch (*Constraint) { 3993 case 'a': return std::string("{ax}"); 3994 case 'b': return std::string("{bx}"); 3995 case 'c': return std::string("{cx}"); 3996 case 'd': return std::string("{dx}"); 3997 case 'S': return std::string("{si}"); 3998 case 'D': return std::string("{di}"); 3999 case 'p': // address 4000 return std::string("im"); 4001 case 't': // top of floating point stack. 4002 return std::string("{st}"); 4003 case 'u': // second from top of floating point stack. 4004 return std::string("{st(1)}"); // second from top of floating point stack. 4005 default: 4006 return std::string(1, *Constraint); 4007 } 4008 } 4009 4010 // X86-32 generic target 4011 class X86_32TargetInfo : public X86TargetInfo { 4012 public: 4013 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4014 : X86TargetInfo(Triple, Opts) { 4015 DoubleAlign = LongLongAlign = 32; 4016 LongDoubleWidth = 96; 4017 LongDoubleAlign = 32; 4018 SuitableAlign = 128; 4019 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4020 SizeType = UnsignedInt; 4021 PtrDiffType = SignedInt; 4022 IntPtrType = SignedInt; 4023 RegParmMax = 3; 4024 4025 // Use fpret for all types. 4026 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4027 (1 << TargetInfo::Double) | 4028 (1 << TargetInfo::LongDouble)); 4029 4030 // x86-32 has atomics up to 8 bytes 4031 // FIXME: Check that we actually have cmpxchg8b before setting 4032 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4033 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4034 } 4035 BuiltinVaListKind getBuiltinVaListKind() const override { 4036 return TargetInfo::CharPtrBuiltinVaList; 4037 } 4038 4039 int getEHDataRegisterNumber(unsigned RegNo) const override { 4040 if (RegNo == 0) return 0; 4041 if (RegNo == 1) return 2; 4042 return -1; 4043 } 4044 bool validateOperandSize(StringRef Constraint, 4045 unsigned Size) const override { 4046 switch (Constraint[0]) { 4047 default: break; 4048 case 'R': 4049 case 'q': 4050 case 'Q': 4051 case 'a': 4052 case 'b': 4053 case 'c': 4054 case 'd': 4055 case 'S': 4056 case 'D': 4057 return Size <= 32; 4058 case 'A': 4059 return Size <= 64; 4060 } 4061 4062 return X86TargetInfo::validateOperandSize(Constraint, Size); 4063 } 4064 }; 4065 4066 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4067 public: 4068 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4069 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4070 4071 unsigned getFloatEvalMethod() const override { 4072 unsigned Major, Minor, Micro; 4073 getTriple().getOSVersion(Major, Minor, Micro); 4074 // New NetBSD uses the default rounding mode. 4075 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4076 return X86_32TargetInfo::getFloatEvalMethod(); 4077 // NetBSD before 6.99.26 defaults to "double" rounding. 4078 return 1; 4079 } 4080 }; 4081 4082 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4083 public: 4084 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4085 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4086 SizeType = UnsignedLong; 4087 IntPtrType = SignedLong; 4088 PtrDiffType = SignedLong; 4089 } 4090 }; 4091 4092 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4093 public: 4094 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4095 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4096 SizeType = UnsignedLong; 4097 IntPtrType = SignedLong; 4098 PtrDiffType = SignedLong; 4099 } 4100 }; 4101 4102 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4103 public: 4104 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4105 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4106 LongDoubleWidth = 128; 4107 LongDoubleAlign = 128; 4108 SuitableAlign = 128; 4109 MaxVectorAlign = 256; 4110 // The watchOS simulator uses the builtin bool type for Objective-C. 4111 llvm::Triple T = llvm::Triple(Triple); 4112 if (T.isWatchOS()) 4113 UseSignedCharForObjCBool = false; 4114 SizeType = UnsignedLong; 4115 IntPtrType = SignedLong; 4116 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4117 HasAlignMac68kSupport = true; 4118 } 4119 4120 bool handleTargetFeatures(std::vector<std::string> &Features, 4121 DiagnosticsEngine &Diags) override { 4122 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4123 Diags)) 4124 return false; 4125 // We now know the features we have: we can decide how to align vectors. 4126 MaxVectorAlign = 4127 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4128 return true; 4129 } 4130 }; 4131 4132 // x86-32 Windows target 4133 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4134 public: 4135 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4136 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4137 WCharType = UnsignedShort; 4138 DoubleAlign = LongLongAlign = 64; 4139 bool IsWinCOFF = 4140 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4141 resetDataLayout(IsWinCOFF 4142 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4143 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4144 } 4145 void getTargetDefines(const LangOptions &Opts, 4146 MacroBuilder &Builder) const override { 4147 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4148 } 4149 }; 4150 4151 // x86-32 Windows Visual Studio target 4152 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4153 public: 4154 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4155 const TargetOptions &Opts) 4156 : WindowsX86_32TargetInfo(Triple, Opts) { 4157 LongDoubleWidth = LongDoubleAlign = 64; 4158 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4159 } 4160 void getTargetDefines(const LangOptions &Opts, 4161 MacroBuilder &Builder) const override { 4162 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4163 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4164 // The value of the following reflects processor type. 4165 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4166 // We lost the original triple, so we use the default. 4167 Builder.defineMacro("_M_IX86", "600"); 4168 } 4169 }; 4170 4171 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4172 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4173 // supports __declspec natively under -fms-extensions, but we define a no-op 4174 // __declspec macro anyway for pre-processor compatibility. 4175 if (Opts.MicrosoftExt) 4176 Builder.defineMacro("__declspec", "__declspec"); 4177 else 4178 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4179 4180 if (!Opts.MicrosoftExt) { 4181 // Provide macros for all the calling convention keywords. Provide both 4182 // single and double underscore prefixed variants. These are available on 4183 // x64 as well as x86, even though they have no effect. 4184 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4185 for (const char *CC : CCs) { 4186 std::string GCCSpelling = "__attribute__((__"; 4187 GCCSpelling += CC; 4188 GCCSpelling += "__))"; 4189 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4190 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4191 } 4192 } 4193 } 4194 4195 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4196 Builder.defineMacro("__MSVCRT__"); 4197 Builder.defineMacro("__MINGW32__"); 4198 addCygMingDefines(Opts, Builder); 4199 } 4200 4201 // x86-32 MinGW target 4202 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4203 public: 4204 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4205 : WindowsX86_32TargetInfo(Triple, Opts) {} 4206 void getTargetDefines(const LangOptions &Opts, 4207 MacroBuilder &Builder) const override { 4208 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4209 DefineStd(Builder, "WIN32", Opts); 4210 DefineStd(Builder, "WINNT", Opts); 4211 Builder.defineMacro("_X86_"); 4212 addMinGWDefines(Opts, Builder); 4213 } 4214 }; 4215 4216 // x86-32 Cygwin target 4217 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4218 public: 4219 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4220 : X86_32TargetInfo(Triple, Opts) { 4221 WCharType = UnsignedShort; 4222 DoubleAlign = LongLongAlign = 64; 4223 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4224 } 4225 void getTargetDefines(const LangOptions &Opts, 4226 MacroBuilder &Builder) const override { 4227 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4228 Builder.defineMacro("_X86_"); 4229 Builder.defineMacro("__CYGWIN__"); 4230 Builder.defineMacro("__CYGWIN32__"); 4231 addCygMingDefines(Opts, Builder); 4232 DefineStd(Builder, "unix", Opts); 4233 if (Opts.CPlusPlus) 4234 Builder.defineMacro("_GNU_SOURCE"); 4235 } 4236 }; 4237 4238 // x86-32 Haiku target 4239 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4240 public: 4241 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4242 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4243 } 4244 void getTargetDefines(const LangOptions &Opts, 4245 MacroBuilder &Builder) const override { 4246 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4247 Builder.defineMacro("__INTEL__"); 4248 } 4249 }; 4250 4251 // X86-32 MCU target 4252 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4253 public: 4254 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4255 : X86_32TargetInfo(Triple, Opts) { 4256 LongDoubleWidth = 64; 4257 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4258 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4259 WIntType = UnsignedInt; 4260 } 4261 4262 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4263 // On MCU we support only C calling convention. 4264 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4265 } 4266 4267 void getTargetDefines(const LangOptions &Opts, 4268 MacroBuilder &Builder) const override { 4269 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4270 Builder.defineMacro("__iamcu"); 4271 Builder.defineMacro("__iamcu__"); 4272 } 4273 4274 bool allowsLargerPreferedTypeAlignment() const override { 4275 return false; 4276 } 4277 }; 4278 4279 // RTEMS Target 4280 template<typename Target> 4281 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4282 protected: 4283 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4284 MacroBuilder &Builder) const override { 4285 // RTEMS defines; list based off of gcc output 4286 4287 Builder.defineMacro("__rtems__"); 4288 Builder.defineMacro("__ELF__"); 4289 } 4290 4291 public: 4292 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4293 : OSTargetInfo<Target>(Triple, Opts) { 4294 switch (Triple.getArch()) { 4295 default: 4296 case llvm::Triple::x86: 4297 // this->MCountName = ".mcount"; 4298 break; 4299 case llvm::Triple::mips: 4300 case llvm::Triple::mipsel: 4301 case llvm::Triple::ppc: 4302 case llvm::Triple::ppc64: 4303 case llvm::Triple::ppc64le: 4304 // this->MCountName = "_mcount"; 4305 break; 4306 case llvm::Triple::arm: 4307 // this->MCountName = "__mcount"; 4308 break; 4309 } 4310 } 4311 }; 4312 4313 // x86-32 RTEMS target 4314 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4315 public: 4316 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4317 : X86_32TargetInfo(Triple, Opts) { 4318 SizeType = UnsignedLong; 4319 IntPtrType = SignedLong; 4320 PtrDiffType = SignedLong; 4321 } 4322 void getTargetDefines(const LangOptions &Opts, 4323 MacroBuilder &Builder) const override { 4324 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4325 Builder.defineMacro("__INTEL__"); 4326 Builder.defineMacro("__rtems__"); 4327 } 4328 }; 4329 4330 // x86-64 generic target 4331 class X86_64TargetInfo : public X86TargetInfo { 4332 public: 4333 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4334 : X86TargetInfo(Triple, Opts) { 4335 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4336 bool IsWinCOFF = 4337 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4338 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4339 LongDoubleWidth = 128; 4340 LongDoubleAlign = 128; 4341 LargeArrayMinWidth = 128; 4342 LargeArrayAlign = 128; 4343 SuitableAlign = 128; 4344 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4345 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4346 IntPtrType = IsX32 ? SignedInt : SignedLong; 4347 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4348 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4349 RegParmMax = 6; 4350 4351 // Pointers are 32-bit in x32. 4352 resetDataLayout(IsX32 4353 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4354 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4355 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4356 4357 // Use fpret only for long double. 4358 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4359 4360 // Use fp2ret for _Complex long double. 4361 ComplexLongDoubleUsesFP2Ret = true; 4362 4363 // Make __builtin_ms_va_list available. 4364 HasBuiltinMSVaList = true; 4365 4366 // x86-64 has atomics up to 16 bytes. 4367 MaxAtomicPromoteWidth = 128; 4368 MaxAtomicInlineWidth = 128; 4369 } 4370 BuiltinVaListKind getBuiltinVaListKind() const override { 4371 return TargetInfo::X86_64ABIBuiltinVaList; 4372 } 4373 4374 int getEHDataRegisterNumber(unsigned RegNo) const override { 4375 if (RegNo == 0) return 0; 4376 if (RegNo == 1) return 1; 4377 return -1; 4378 } 4379 4380 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4381 switch (CC) { 4382 case CC_C: 4383 case CC_Swift: 4384 case CC_X86VectorCall: 4385 case CC_IntelOclBicc: 4386 case CC_X86_64Win64: 4387 case CC_PreserveMost: 4388 case CC_PreserveAll: 4389 return CCCR_OK; 4390 default: 4391 return CCCR_Warning; 4392 } 4393 } 4394 4395 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4396 return CC_C; 4397 } 4398 4399 // for x32 we need it here explicitly 4400 bool hasInt128Type() const override { return true; } 4401 unsigned getUnwindWordWidth() const override { return 64; } 4402 unsigned getRegisterWidth() const override { return 64; } 4403 4404 bool validateGlobalRegisterVariable(StringRef RegName, 4405 unsigned RegSize, 4406 bool &HasSizeMismatch) const override { 4407 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4408 // handle. 4409 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4410 // Check that the register size is 64-bit. 4411 HasSizeMismatch = RegSize != 64; 4412 return true; 4413 } 4414 4415 // Check if the register is a 32-bit register the backend can handle. 4416 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4417 HasSizeMismatch); 4418 } 4419 }; 4420 4421 // x86-64 Windows target 4422 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4423 public: 4424 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4425 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4426 WCharType = UnsignedShort; 4427 LongWidth = LongAlign = 32; 4428 DoubleAlign = LongLongAlign = 64; 4429 IntMaxType = SignedLongLong; 4430 Int64Type = SignedLongLong; 4431 SizeType = UnsignedLongLong; 4432 PtrDiffType = SignedLongLong; 4433 IntPtrType = SignedLongLong; 4434 } 4435 4436 void getTargetDefines(const LangOptions &Opts, 4437 MacroBuilder &Builder) const override { 4438 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4439 Builder.defineMacro("_WIN64"); 4440 } 4441 4442 BuiltinVaListKind getBuiltinVaListKind() const override { 4443 return TargetInfo::CharPtrBuiltinVaList; 4444 } 4445 4446 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4447 switch (CC) { 4448 case CC_X86StdCall: 4449 case CC_X86ThisCall: 4450 case CC_X86FastCall: 4451 return CCCR_Ignore; 4452 case CC_C: 4453 case CC_X86VectorCall: 4454 case CC_IntelOclBicc: 4455 case CC_X86_64SysV: 4456 return CCCR_OK; 4457 default: 4458 return CCCR_Warning; 4459 } 4460 } 4461 }; 4462 4463 // x86-64 Windows Visual Studio target 4464 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4465 public: 4466 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4467 const TargetOptions &Opts) 4468 : WindowsX86_64TargetInfo(Triple, Opts) { 4469 LongDoubleWidth = LongDoubleAlign = 64; 4470 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4471 } 4472 void getTargetDefines(const LangOptions &Opts, 4473 MacroBuilder &Builder) const override { 4474 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4475 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4476 Builder.defineMacro("_M_X64", "100"); 4477 Builder.defineMacro("_M_AMD64", "100"); 4478 } 4479 }; 4480 4481 // x86-64 MinGW target 4482 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4483 public: 4484 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4485 : WindowsX86_64TargetInfo(Triple, Opts) { 4486 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4487 // with x86 FP ops. Weird. 4488 LongDoubleWidth = LongDoubleAlign = 128; 4489 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4490 } 4491 4492 void getTargetDefines(const LangOptions &Opts, 4493 MacroBuilder &Builder) const override { 4494 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4495 DefineStd(Builder, "WIN64", Opts); 4496 Builder.defineMacro("__MINGW64__"); 4497 addMinGWDefines(Opts, Builder); 4498 4499 // GCC defines this macro when it is using __gxx_personality_seh0. 4500 if (!Opts.SjLjExceptions) 4501 Builder.defineMacro("__SEH__"); 4502 } 4503 }; 4504 4505 // x86-64 Cygwin target 4506 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4507 public: 4508 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4509 : X86_64TargetInfo(Triple, Opts) { 4510 TLSSupported = false; 4511 WCharType = UnsignedShort; 4512 } 4513 void getTargetDefines(const LangOptions &Opts, 4514 MacroBuilder &Builder) const override { 4515 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4516 Builder.defineMacro("__x86_64__"); 4517 Builder.defineMacro("__CYGWIN__"); 4518 Builder.defineMacro("__CYGWIN64__"); 4519 addCygMingDefines(Opts, Builder); 4520 DefineStd(Builder, "unix", Opts); 4521 if (Opts.CPlusPlus) 4522 Builder.defineMacro("_GNU_SOURCE"); 4523 4524 // GCC defines this macro when it is using __gxx_personality_seh0. 4525 if (!Opts.SjLjExceptions) 4526 Builder.defineMacro("__SEH__"); 4527 } 4528 }; 4529 4530 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4531 public: 4532 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4533 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4534 Int64Type = SignedLongLong; 4535 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4536 llvm::Triple T = llvm::Triple(Triple); 4537 if (T.isiOS()) 4538 UseSignedCharForObjCBool = false; 4539 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4540 } 4541 4542 bool handleTargetFeatures(std::vector<std::string> &Features, 4543 DiagnosticsEngine &Diags) override { 4544 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4545 Diags)) 4546 return false; 4547 // We now know the features we have: we can decide how to align vectors. 4548 MaxVectorAlign = 4549 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4550 return true; 4551 } 4552 }; 4553 4554 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4555 public: 4556 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4557 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4558 IntMaxType = SignedLongLong; 4559 Int64Type = SignedLongLong; 4560 } 4561 }; 4562 4563 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4564 public: 4565 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4566 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4567 IntMaxType = SignedLongLong; 4568 Int64Type = SignedLongLong; 4569 } 4570 }; 4571 4572 class ARMTargetInfo : public TargetInfo { 4573 // Possible FPU choices. 4574 enum FPUMode { 4575 VFP2FPU = (1 << 0), 4576 VFP3FPU = (1 << 1), 4577 VFP4FPU = (1 << 2), 4578 NeonFPU = (1 << 3), 4579 FPARMV8 = (1 << 4) 4580 }; 4581 4582 // Possible HWDiv features. 4583 enum HWDivMode { 4584 HWDivThumb = (1 << 0), 4585 HWDivARM = (1 << 1) 4586 }; 4587 4588 static bool FPUModeIsVFP(FPUMode Mode) { 4589 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4590 } 4591 4592 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4593 static const char * const GCCRegNames[]; 4594 4595 std::string ABI, CPU; 4596 4597 StringRef CPUProfile; 4598 StringRef CPUAttr; 4599 4600 enum { 4601 FP_Default, 4602 FP_VFP, 4603 FP_Neon 4604 } FPMath; 4605 4606 unsigned ArchISA; 4607 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4608 unsigned ArchProfile; 4609 unsigned ArchVersion; 4610 4611 unsigned FPU : 5; 4612 4613 unsigned IsAAPCS : 1; 4614 unsigned HWDiv : 2; 4615 4616 // Initialized via features. 4617 unsigned SoftFloat : 1; 4618 unsigned SoftFloatABI : 1; 4619 4620 unsigned CRC : 1; 4621 unsigned Crypto : 1; 4622 unsigned DSP : 1; 4623 unsigned Unaligned : 1; 4624 4625 enum { 4626 LDREX_B = (1 << 0), /// byte (8-bit) 4627 LDREX_H = (1 << 1), /// half (16-bit) 4628 LDREX_W = (1 << 2), /// word (32-bit) 4629 LDREX_D = (1 << 3), /// double (64-bit) 4630 }; 4631 4632 uint32_t LDREX; 4633 4634 // ACLE 6.5.1 Hardware floating point 4635 enum { 4636 HW_FP_HP = (1 << 1), /// half (16-bit) 4637 HW_FP_SP = (1 << 2), /// single (32-bit) 4638 HW_FP_DP = (1 << 3), /// double (64-bit) 4639 }; 4640 uint32_t HW_FP; 4641 4642 static const Builtin::Info BuiltinInfo[]; 4643 4644 void setABIAAPCS() { 4645 IsAAPCS = true; 4646 4647 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4648 const llvm::Triple &T = getTriple(); 4649 4650 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4651 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4652 T.getOS() == llvm::Triple::Bitrig) 4653 SizeType = UnsignedLong; 4654 else 4655 SizeType = UnsignedInt; 4656 4657 switch (T.getOS()) { 4658 case llvm::Triple::NetBSD: 4659 WCharType = SignedInt; 4660 break; 4661 case llvm::Triple::Win32: 4662 WCharType = UnsignedShort; 4663 break; 4664 case llvm::Triple::Linux: 4665 default: 4666 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4667 WCharType = UnsignedInt; 4668 break; 4669 } 4670 4671 UseBitFieldTypeAlignment = true; 4672 4673 ZeroLengthBitfieldBoundary = 0; 4674 4675 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4676 // so set preferred for small types to 32. 4677 if (T.isOSBinFormatMachO()) { 4678 resetDataLayout(BigEndian 4679 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4680 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4681 } else if (T.isOSWindows()) { 4682 assert(!BigEndian && "Windows on ARM does not support big endian"); 4683 resetDataLayout("e" 4684 "-m:w" 4685 "-p:32:32" 4686 "-i64:64" 4687 "-v128:64:128" 4688 "-a:0:32" 4689 "-n32" 4690 "-S64"); 4691 } else if (T.isOSNaCl()) { 4692 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4693 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4694 } else { 4695 resetDataLayout(BigEndian 4696 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4697 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4698 } 4699 4700 // FIXME: Enumerated types are variable width in straight AAPCS. 4701 } 4702 4703 void setABIAPCS(bool IsAAPCS16) { 4704 const llvm::Triple &T = getTriple(); 4705 4706 IsAAPCS = false; 4707 4708 if (IsAAPCS16) 4709 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4710 else 4711 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4712 4713 // size_t is unsigned int on FreeBSD. 4714 if (T.getOS() == llvm::Triple::FreeBSD) 4715 SizeType = UnsignedInt; 4716 else 4717 SizeType = UnsignedLong; 4718 4719 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4720 WCharType = SignedInt; 4721 4722 // Do not respect the alignment of bit-field types when laying out 4723 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4724 UseBitFieldTypeAlignment = false; 4725 4726 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4727 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4728 /// gcc. 4729 ZeroLengthBitfieldBoundary = 32; 4730 4731 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4732 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4733 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4734 } else if (T.isOSBinFormatMachO()) 4735 resetDataLayout( 4736 BigEndian 4737 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4738 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4739 else 4740 resetDataLayout( 4741 BigEndian 4742 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4743 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4744 4745 // FIXME: Override "preferred align" for double and long long. 4746 } 4747 4748 void setArchInfo() { 4749 StringRef ArchName = getTriple().getArchName(); 4750 4751 ArchISA = llvm::ARM::parseArchISA(ArchName); 4752 CPU = llvm::ARM::getDefaultCPU(ArchName); 4753 unsigned AK = llvm::ARM::parseArch(ArchName); 4754 if (AK != llvm::ARM::AK_INVALID) 4755 ArchKind = AK; 4756 setArchInfo(ArchKind); 4757 } 4758 4759 void setArchInfo(unsigned Kind) { 4760 StringRef SubArch; 4761 4762 // cache TargetParser info 4763 ArchKind = Kind; 4764 SubArch = llvm::ARM::getSubArch(ArchKind); 4765 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4766 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4767 4768 // cache CPU related strings 4769 CPUAttr = getCPUAttr(); 4770 CPUProfile = getCPUProfile(); 4771 } 4772 4773 void setAtomic() { 4774 // when triple does not specify a sub arch, 4775 // then we are not using inline atomics 4776 bool ShouldUseInlineAtomic = 4777 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4778 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4779 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4780 if (ArchProfile == llvm::ARM::PK_M) { 4781 MaxAtomicPromoteWidth = 32; 4782 if (ShouldUseInlineAtomic) 4783 MaxAtomicInlineWidth = 32; 4784 } 4785 else { 4786 MaxAtomicPromoteWidth = 64; 4787 if (ShouldUseInlineAtomic) 4788 MaxAtomicInlineWidth = 64; 4789 } 4790 } 4791 4792 bool isThumb() const { 4793 return (ArchISA == llvm::ARM::IK_THUMB); 4794 } 4795 4796 bool supportsThumb() const { 4797 return CPUAttr.count('T') || ArchVersion >= 6; 4798 } 4799 4800 bool supportsThumb2() const { 4801 return CPUAttr.equals("6T2") || 4802 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4803 } 4804 4805 StringRef getCPUAttr() const { 4806 // For most sub-arches, the build attribute CPU name is enough. 4807 // For Cortex variants, it's slightly different. 4808 switch(ArchKind) { 4809 default: 4810 return llvm::ARM::getCPUAttr(ArchKind); 4811 case llvm::ARM::AK_ARMV6M: 4812 return "6M"; 4813 case llvm::ARM::AK_ARMV7S: 4814 return "7S"; 4815 case llvm::ARM::AK_ARMV7A: 4816 return "7A"; 4817 case llvm::ARM::AK_ARMV7R: 4818 return "7R"; 4819 case llvm::ARM::AK_ARMV7M: 4820 return "7M"; 4821 case llvm::ARM::AK_ARMV7EM: 4822 return "7EM"; 4823 case llvm::ARM::AK_ARMV8A: 4824 return "8A"; 4825 case llvm::ARM::AK_ARMV8_1A: 4826 return "8_1A"; 4827 case llvm::ARM::AK_ARMV8_2A: 4828 return "8_2A"; 4829 case llvm::ARM::AK_ARMV8MBaseline: 4830 return "8M_BASE"; 4831 case llvm::ARM::AK_ARMV8MMainline: 4832 return "8M_MAIN"; 4833 } 4834 } 4835 4836 StringRef getCPUProfile() const { 4837 switch(ArchProfile) { 4838 case llvm::ARM::PK_A: 4839 return "A"; 4840 case llvm::ARM::PK_R: 4841 return "R"; 4842 case llvm::ARM::PK_M: 4843 return "M"; 4844 default: 4845 return ""; 4846 } 4847 } 4848 4849 public: 4850 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 4851 bool IsBigEndian) 4852 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4853 HW_FP(0) { 4854 BigEndian = IsBigEndian; 4855 4856 switch (getTriple().getOS()) { 4857 case llvm::Triple::NetBSD: 4858 PtrDiffType = SignedLong; 4859 break; 4860 default: 4861 PtrDiffType = SignedInt; 4862 break; 4863 } 4864 4865 // Cache arch related info. 4866 setArchInfo(); 4867 4868 // {} in inline assembly are neon specifiers, not assembly variant 4869 // specifiers. 4870 NoAsmVariants = true; 4871 4872 // FIXME: This duplicates code from the driver that sets the -target-abi 4873 // option - this code is used if -target-abi isn't passed and should 4874 // be unified in some way. 4875 if (Triple.isOSBinFormatMachO()) { 4876 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4877 // the frontend matches that. 4878 if (Triple.getEnvironment() == llvm::Triple::EABI || 4879 Triple.getOS() == llvm::Triple::UnknownOS || 4880 StringRef(CPU).startswith("cortex-m")) { 4881 setABI("aapcs"); 4882 } else if (Triple.isWatchABI()) { 4883 setABI("aapcs16"); 4884 } else { 4885 setABI("apcs-gnu"); 4886 } 4887 } else if (Triple.isOSWindows()) { 4888 // FIXME: this is invalid for WindowsCE 4889 setABI("aapcs"); 4890 } else { 4891 // Select the default based on the platform. 4892 switch (Triple.getEnvironment()) { 4893 case llvm::Triple::Android: 4894 case llvm::Triple::GNUEABI: 4895 case llvm::Triple::GNUEABIHF: 4896 case llvm::Triple::MuslEABI: 4897 case llvm::Triple::MuslEABIHF: 4898 setABI("aapcs-linux"); 4899 break; 4900 case llvm::Triple::EABIHF: 4901 case llvm::Triple::EABI: 4902 setABI("aapcs"); 4903 break; 4904 case llvm::Triple::GNU: 4905 setABI("apcs-gnu"); 4906 break; 4907 default: 4908 if (Triple.getOS() == llvm::Triple::NetBSD) 4909 setABI("apcs-gnu"); 4910 else 4911 setABI("aapcs"); 4912 break; 4913 } 4914 } 4915 4916 // ARM targets default to using the ARM C++ ABI. 4917 TheCXXABI.set(TargetCXXABI::GenericARM); 4918 4919 // ARM has atomics up to 8 bytes 4920 setAtomic(); 4921 4922 // Do force alignment of members that follow zero length bitfields. If 4923 // the alignment of the zero-length bitfield is greater than the member 4924 // that follows it, `bar', `bar' will be aligned as the type of the 4925 // zero length bitfield. 4926 UseZeroLengthBitfieldAlignment = true; 4927 4928 if (Triple.getOS() == llvm::Triple::Linux || 4929 Triple.getOS() == llvm::Triple::UnknownOS) 4930 this->MCountName = 4931 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 4932 } 4933 4934 StringRef getABI() const override { return ABI; } 4935 4936 bool setABI(const std::string &Name) override { 4937 ABI = Name; 4938 4939 // The defaults (above) are for AAPCS, check if we need to change them. 4940 // 4941 // FIXME: We need support for -meabi... we could just mangle it into the 4942 // name. 4943 if (Name == "apcs-gnu" || Name == "aapcs16") { 4944 setABIAPCS(Name == "aapcs16"); 4945 return true; 4946 } 4947 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4948 setABIAAPCS(); 4949 return true; 4950 } 4951 return false; 4952 } 4953 4954 // FIXME: This should be based on Arch attributes, not CPU names. 4955 bool 4956 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4957 StringRef CPU, 4958 const std::vector<std::string> &FeaturesVec) const override { 4959 4960 std::vector<const char*> TargetFeatures; 4961 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4962 4963 // get default FPU features 4964 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4965 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4966 4967 // get default Extension features 4968 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4969 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4970 4971 for (const char *Feature : TargetFeatures) 4972 if (Feature[0] == '+') 4973 Features[Feature+1] = true; 4974 4975 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4976 } 4977 4978 bool handleTargetFeatures(std::vector<std::string> &Features, 4979 DiagnosticsEngine &Diags) override { 4980 FPU = 0; 4981 CRC = 0; 4982 Crypto = 0; 4983 DSP = 0; 4984 Unaligned = 1; 4985 SoftFloat = SoftFloatABI = false; 4986 HWDiv = 0; 4987 4988 // This does not diagnose illegal cases like having both 4989 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4990 uint32_t HW_FP_remove = 0; 4991 for (const auto &Feature : Features) { 4992 if (Feature == "+soft-float") { 4993 SoftFloat = true; 4994 } else if (Feature == "+soft-float-abi") { 4995 SoftFloatABI = true; 4996 } else if (Feature == "+vfp2") { 4997 FPU |= VFP2FPU; 4998 HW_FP |= HW_FP_SP | HW_FP_DP; 4999 } else if (Feature == "+vfp3") { 5000 FPU |= VFP3FPU; 5001 HW_FP |= HW_FP_SP | HW_FP_DP; 5002 } else if (Feature == "+vfp4") { 5003 FPU |= VFP4FPU; 5004 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5005 } else if (Feature == "+fp-armv8") { 5006 FPU |= FPARMV8; 5007 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5008 } else if (Feature == "+neon") { 5009 FPU |= NeonFPU; 5010 HW_FP |= HW_FP_SP | HW_FP_DP; 5011 } else if (Feature == "+hwdiv") { 5012 HWDiv |= HWDivThumb; 5013 } else if (Feature == "+hwdiv-arm") { 5014 HWDiv |= HWDivARM; 5015 } else if (Feature == "+crc") { 5016 CRC = 1; 5017 } else if (Feature == "+crypto") { 5018 Crypto = 1; 5019 } else if (Feature == "+dsp") { 5020 DSP = 1; 5021 } else if (Feature == "+fp-only-sp") { 5022 HW_FP_remove |= HW_FP_DP; 5023 } else if (Feature == "+strict-align") { 5024 Unaligned = 0; 5025 } else if (Feature == "+fp16") { 5026 HW_FP |= HW_FP_HP; 5027 } 5028 } 5029 HW_FP &= ~HW_FP_remove; 5030 5031 switch (ArchVersion) { 5032 case 6: 5033 if (ArchProfile == llvm::ARM::PK_M) 5034 LDREX = 0; 5035 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5036 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5037 else 5038 LDREX = LDREX_W; 5039 break; 5040 case 7: 5041 if (ArchProfile == llvm::ARM::PK_M) 5042 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5043 else 5044 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5045 break; 5046 case 8: 5047 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5048 } 5049 5050 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5051 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5052 return false; 5053 } 5054 5055 if (FPMath == FP_Neon) 5056 Features.push_back("+neonfp"); 5057 else if (FPMath == FP_VFP) 5058 Features.push_back("-neonfp"); 5059 5060 // Remove front-end specific options which the backend handles differently. 5061 auto Feature = 5062 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5063 if (Feature != Features.end()) 5064 Features.erase(Feature); 5065 5066 return true; 5067 } 5068 5069 bool hasFeature(StringRef Feature) const override { 5070 return llvm::StringSwitch<bool>(Feature) 5071 .Case("arm", true) 5072 .Case("aarch32", true) 5073 .Case("softfloat", SoftFloat) 5074 .Case("thumb", isThumb()) 5075 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5076 .Case("hwdiv", HWDiv & HWDivThumb) 5077 .Case("hwdiv-arm", HWDiv & HWDivARM) 5078 .Default(false); 5079 } 5080 5081 bool setCPU(const std::string &Name) override { 5082 if (Name != "generic") 5083 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5084 5085 if (ArchKind == llvm::ARM::AK_INVALID) 5086 return false; 5087 setAtomic(); 5088 CPU = Name; 5089 return true; 5090 } 5091 5092 bool setFPMath(StringRef Name) override; 5093 5094 void getTargetDefines(const LangOptions &Opts, 5095 MacroBuilder &Builder) const override { 5096 // Target identification. 5097 Builder.defineMacro("__arm"); 5098 Builder.defineMacro("__arm__"); 5099 // For bare-metal none-eabi. 5100 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5101 getTriple().getEnvironment() == llvm::Triple::EABI) 5102 Builder.defineMacro("__ELF__"); 5103 5104 // Target properties. 5105 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5106 5107 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5108 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5109 if (getTriple().isWatchABI()) 5110 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5111 5112 if (!CPUAttr.empty()) 5113 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5114 5115 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5116 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5117 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5118 5119 if (ArchVersion >= 8) { 5120 // ACLE 6.5.7 Crypto Extension 5121 if (Crypto) 5122 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5123 // ACLE 6.5.8 CRC32 Extension 5124 if (CRC) 5125 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5126 // ACLE 6.5.10 Numeric Maximum and Minimum 5127 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5128 // ACLE 6.5.9 Directed Rounding 5129 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5130 } 5131 5132 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5133 // is not defined for the M-profile. 5134 // NOTE that the default profile is assumed to be 'A' 5135 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5136 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5137 5138 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5139 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5140 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5141 // v7 and v8 architectures excluding v8-M Baseline. 5142 if (supportsThumb2()) 5143 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5144 else if (supportsThumb()) 5145 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5146 5147 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5148 // instruction set such as ARM or Thumb. 5149 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5150 5151 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5152 5153 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5154 if (!CPUProfile.empty()) 5155 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5156 5157 // ACLE 6.4.3 Unaligned access supported in hardware 5158 if (Unaligned) 5159 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5160 5161 // ACLE 6.4.4 LDREX/STREX 5162 if (LDREX) 5163 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5164 5165 // ACLE 6.4.5 CLZ 5166 if (ArchVersion == 5 || 5167 (ArchVersion == 6 && CPUProfile != "M") || 5168 ArchVersion > 6) 5169 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5170 5171 // ACLE 6.5.1 Hardware Floating Point 5172 if (HW_FP) 5173 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5174 5175 // ACLE predefines. 5176 Builder.defineMacro("__ARM_ACLE", "200"); 5177 5178 // FP16 support (we currently only support IEEE format). 5179 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5180 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5181 5182 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5183 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5184 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5185 5186 // Subtarget options. 5187 5188 // FIXME: It's more complicated than this and we don't really support 5189 // interworking. 5190 // Windows on ARM does not "support" interworking 5191 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5192 Builder.defineMacro("__THUMB_INTERWORK__"); 5193 5194 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5195 // Embedded targets on Darwin follow AAPCS, but not EABI. 5196 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5197 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5198 Builder.defineMacro("__ARM_EABI__"); 5199 Builder.defineMacro("__ARM_PCS", "1"); 5200 } 5201 5202 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5203 ABI == "aapcs16") 5204 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5205 5206 if (SoftFloat) 5207 Builder.defineMacro("__SOFTFP__"); 5208 5209 if (CPU == "xscale") 5210 Builder.defineMacro("__XSCALE__"); 5211 5212 if (isThumb()) { 5213 Builder.defineMacro("__THUMBEL__"); 5214 Builder.defineMacro("__thumb__"); 5215 if (supportsThumb2()) 5216 Builder.defineMacro("__thumb2__"); 5217 } 5218 5219 // ACLE 6.4.9 32-bit SIMD instructions 5220 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5221 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5222 5223 // ACLE 6.4.10 Hardware Integer Divide 5224 if (((HWDiv & HWDivThumb) && isThumb()) || 5225 ((HWDiv & HWDivARM) && !isThumb())) { 5226 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5227 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5228 } 5229 5230 // Note, this is always on in gcc, even though it doesn't make sense. 5231 Builder.defineMacro("__APCS_32__"); 5232 5233 if (FPUModeIsVFP((FPUMode) FPU)) { 5234 Builder.defineMacro("__VFP_FP__"); 5235 if (FPU & VFP2FPU) 5236 Builder.defineMacro("__ARM_VFPV2__"); 5237 if (FPU & VFP3FPU) 5238 Builder.defineMacro("__ARM_VFPV3__"); 5239 if (FPU & VFP4FPU) 5240 Builder.defineMacro("__ARM_VFPV4__"); 5241 } 5242 5243 // This only gets set when Neon instructions are actually available, unlike 5244 // the VFP define, hence the soft float and arch check. This is subtly 5245 // different from gcc, we follow the intent which was that it should be set 5246 // when Neon instructions are actually available. 5247 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5248 Builder.defineMacro("__ARM_NEON", "1"); 5249 Builder.defineMacro("__ARM_NEON__"); 5250 // current AArch32 NEON implementations do not support double-precision 5251 // floating-point even when it is present in VFP. 5252 Builder.defineMacro("__ARM_NEON_FP", 5253 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5254 } 5255 5256 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5257 Opts.ShortWChar ? "2" : "4"); 5258 5259 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5260 Opts.ShortEnums ? "1" : "4"); 5261 5262 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5263 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5264 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5265 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5266 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5267 } 5268 5269 // ACLE 6.4.7 DSP instructions 5270 if (DSP) { 5271 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5272 } 5273 5274 // ACLE 6.4.8 Saturation instructions 5275 bool SAT = false; 5276 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5277 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5278 SAT = true; 5279 } 5280 5281 // ACLE 6.4.6 Q (saturation) flag 5282 if (DSP || SAT) 5283 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5284 5285 if (Opts.UnsafeFPMath) 5286 Builder.defineMacro("__ARM_FP_FAST", "1"); 5287 5288 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5289 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5290 } 5291 5292 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5293 return llvm::makeArrayRef(BuiltinInfo, 5294 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5295 } 5296 bool isCLZForZeroUndef() const override { return false; } 5297 BuiltinVaListKind getBuiltinVaListKind() const override { 5298 return IsAAPCS 5299 ? AAPCSABIBuiltinVaList 5300 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5301 : TargetInfo::VoidPtrBuiltinVaList); 5302 } 5303 ArrayRef<const char *> getGCCRegNames() const override; 5304 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5305 bool validateAsmConstraint(const char *&Name, 5306 TargetInfo::ConstraintInfo &Info) const override { 5307 switch (*Name) { 5308 default: break; 5309 case 'l': // r0-r7 5310 case 'h': // r8-r15 5311 case 't': // VFP Floating point register single precision 5312 case 'w': // VFP Floating point register double precision 5313 Info.setAllowsRegister(); 5314 return true; 5315 case 'I': 5316 case 'J': 5317 case 'K': 5318 case 'L': 5319 case 'M': 5320 // FIXME 5321 return true; 5322 case 'Q': // A memory address that is a single base register. 5323 Info.setAllowsMemory(); 5324 return true; 5325 case 'U': // a memory reference... 5326 switch (Name[1]) { 5327 case 'q': // ...ARMV4 ldrsb 5328 case 'v': // ...VFP load/store (reg+constant offset) 5329 case 'y': // ...iWMMXt load/store 5330 case 't': // address valid for load/store opaque types wider 5331 // than 128-bits 5332 case 'n': // valid address for Neon doubleword vector load/store 5333 case 'm': // valid address for Neon element and structure load/store 5334 case 's': // valid address for non-offset loads/stores of quad-word 5335 // values in four ARM registers 5336 Info.setAllowsMemory(); 5337 Name++; 5338 return true; 5339 } 5340 } 5341 return false; 5342 } 5343 std::string convertConstraint(const char *&Constraint) const override { 5344 std::string R; 5345 switch (*Constraint) { 5346 case 'U': // Two-character constraint; add "^" hint for later parsing. 5347 R = std::string("^") + std::string(Constraint, 2); 5348 Constraint++; 5349 break; 5350 case 'p': // 'p' should be translated to 'r' by default. 5351 R = std::string("r"); 5352 break; 5353 default: 5354 return std::string(1, *Constraint); 5355 } 5356 return R; 5357 } 5358 bool 5359 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5360 std::string &SuggestedModifier) const override { 5361 bool isOutput = (Constraint[0] == '='); 5362 bool isInOut = (Constraint[0] == '+'); 5363 5364 // Strip off constraint modifiers. 5365 while (Constraint[0] == '=' || 5366 Constraint[0] == '+' || 5367 Constraint[0] == '&') 5368 Constraint = Constraint.substr(1); 5369 5370 switch (Constraint[0]) { 5371 default: break; 5372 case 'r': { 5373 switch (Modifier) { 5374 default: 5375 return (isInOut || isOutput || Size <= 64); 5376 case 'q': 5377 // A register of size 32 cannot fit a vector type. 5378 return false; 5379 } 5380 } 5381 } 5382 5383 return true; 5384 } 5385 const char *getClobbers() const override { 5386 // FIXME: Is this really right? 5387 return ""; 5388 } 5389 5390 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5391 switch (CC) { 5392 case CC_AAPCS: 5393 case CC_AAPCS_VFP: 5394 case CC_Swift: 5395 return CCCR_OK; 5396 default: 5397 return CCCR_Warning; 5398 } 5399 } 5400 5401 int getEHDataRegisterNumber(unsigned RegNo) const override { 5402 if (RegNo == 0) return 0; 5403 if (RegNo == 1) return 1; 5404 return -1; 5405 } 5406 5407 bool hasSjLjLowering() const override { 5408 return true; 5409 } 5410 }; 5411 5412 bool ARMTargetInfo::setFPMath(StringRef Name) { 5413 if (Name == "neon") { 5414 FPMath = FP_Neon; 5415 return true; 5416 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5417 Name == "vfp4") { 5418 FPMath = FP_VFP; 5419 return true; 5420 } 5421 return false; 5422 } 5423 5424 const char * const ARMTargetInfo::GCCRegNames[] = { 5425 // Integer registers 5426 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5427 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5428 5429 // Float registers 5430 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5431 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5432 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5433 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5434 5435 // Double registers 5436 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5437 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5438 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5439 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5440 5441 // Quad registers 5442 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5443 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5444 }; 5445 5446 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5447 return llvm::makeArrayRef(GCCRegNames); 5448 } 5449 5450 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5451 { { "a1" }, "r0" }, 5452 { { "a2" }, "r1" }, 5453 { { "a3" }, "r2" }, 5454 { { "a4" }, "r3" }, 5455 { { "v1" }, "r4" }, 5456 { { "v2" }, "r5" }, 5457 { { "v3" }, "r6" }, 5458 { { "v4" }, "r7" }, 5459 { { "v5" }, "r8" }, 5460 { { "v6", "rfp" }, "r9" }, 5461 { { "sl" }, "r10" }, 5462 { { "fp" }, "r11" }, 5463 { { "ip" }, "r12" }, 5464 { { "r13" }, "sp" }, 5465 { { "r14" }, "lr" }, 5466 { { "r15" }, "pc" }, 5467 // The S, D and Q registers overlap, but aren't really aliases; we 5468 // don't want to substitute one of these for a different-sized one. 5469 }; 5470 5471 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5472 return llvm::makeArrayRef(GCCRegAliases); 5473 } 5474 5475 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5476 #define BUILTIN(ID, TYPE, ATTRS) \ 5477 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5478 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5479 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5480 #include "clang/Basic/BuiltinsNEON.def" 5481 5482 #define BUILTIN(ID, TYPE, ATTRS) \ 5483 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5484 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5485 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5486 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5487 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5488 #include "clang/Basic/BuiltinsARM.def" 5489 }; 5490 5491 class ARMleTargetInfo : public ARMTargetInfo { 5492 public: 5493 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5494 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/false) {} 5495 void getTargetDefines(const LangOptions &Opts, 5496 MacroBuilder &Builder) const override { 5497 Builder.defineMacro("__ARMEL__"); 5498 ARMTargetInfo::getTargetDefines(Opts, Builder); 5499 } 5500 }; 5501 5502 class ARMbeTargetInfo : public ARMTargetInfo { 5503 public: 5504 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5505 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/true) {} 5506 void getTargetDefines(const LangOptions &Opts, 5507 MacroBuilder &Builder) const override { 5508 Builder.defineMacro("__ARMEB__"); 5509 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5510 ARMTargetInfo::getTargetDefines(Opts, Builder); 5511 } 5512 }; 5513 5514 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5515 const llvm::Triple Triple; 5516 public: 5517 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5518 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5519 WCharType = UnsignedShort; 5520 SizeType = UnsignedInt; 5521 } 5522 void getVisualStudioDefines(const LangOptions &Opts, 5523 MacroBuilder &Builder) const { 5524 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5525 5526 // FIXME: this is invalid for WindowsCE 5527 Builder.defineMacro("_M_ARM_NT", "1"); 5528 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5529 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5530 5531 assert((Triple.getArch() == llvm::Triple::arm || 5532 Triple.getArch() == llvm::Triple::thumb) && 5533 "invalid architecture for Windows ARM target info"); 5534 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5535 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5536 5537 // TODO map the complete set of values 5538 // 31: VFPv3 40: VFPv4 5539 Builder.defineMacro("_M_ARM_FP", "31"); 5540 } 5541 BuiltinVaListKind getBuiltinVaListKind() const override { 5542 return TargetInfo::CharPtrBuiltinVaList; 5543 } 5544 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5545 switch (CC) { 5546 case CC_X86StdCall: 5547 case CC_X86ThisCall: 5548 case CC_X86FastCall: 5549 case CC_X86VectorCall: 5550 return CCCR_Ignore; 5551 case CC_C: 5552 return CCCR_OK; 5553 default: 5554 return CCCR_Warning; 5555 } 5556 } 5557 }; 5558 5559 // Windows ARM + Itanium C++ ABI Target 5560 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5561 public: 5562 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5563 const TargetOptions &Opts) 5564 : WindowsARMTargetInfo(Triple, Opts) { 5565 TheCXXABI.set(TargetCXXABI::GenericARM); 5566 } 5567 5568 void getTargetDefines(const LangOptions &Opts, 5569 MacroBuilder &Builder) const override { 5570 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5571 5572 if (Opts.MSVCCompat) 5573 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5574 } 5575 }; 5576 5577 // Windows ARM, MS (C++) ABI 5578 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5579 public: 5580 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5581 const TargetOptions &Opts) 5582 : WindowsARMTargetInfo(Triple, Opts) { 5583 TheCXXABI.set(TargetCXXABI::Microsoft); 5584 } 5585 5586 void getTargetDefines(const LangOptions &Opts, 5587 MacroBuilder &Builder) const override { 5588 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5589 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5590 } 5591 }; 5592 5593 // ARM MinGW target 5594 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5595 public: 5596 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5597 : WindowsARMTargetInfo(Triple, Opts) { 5598 TheCXXABI.set(TargetCXXABI::GenericARM); 5599 } 5600 5601 void getTargetDefines(const LangOptions &Opts, 5602 MacroBuilder &Builder) const override { 5603 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5604 DefineStd(Builder, "WIN32", Opts); 5605 DefineStd(Builder, "WINNT", Opts); 5606 Builder.defineMacro("_ARM_"); 5607 addMinGWDefines(Opts, Builder); 5608 } 5609 }; 5610 5611 // ARM Cygwin target 5612 class CygwinARMTargetInfo : public ARMleTargetInfo { 5613 public: 5614 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5615 : ARMleTargetInfo(Triple, Opts) { 5616 TLSSupported = false; 5617 WCharType = UnsignedShort; 5618 DoubleAlign = LongLongAlign = 64; 5619 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5620 } 5621 void getTargetDefines(const LangOptions &Opts, 5622 MacroBuilder &Builder) const override { 5623 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5624 Builder.defineMacro("_ARM_"); 5625 Builder.defineMacro("__CYGWIN__"); 5626 Builder.defineMacro("__CYGWIN32__"); 5627 DefineStd(Builder, "unix", Opts); 5628 if (Opts.CPlusPlus) 5629 Builder.defineMacro("_GNU_SOURCE"); 5630 } 5631 }; 5632 5633 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5634 protected: 5635 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5636 MacroBuilder &Builder) const override { 5637 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5638 } 5639 5640 public: 5641 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5642 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5643 HasAlignMac68kSupport = true; 5644 // iOS always has 64-bit atomic instructions. 5645 // FIXME: This should be based off of the target features in 5646 // ARMleTargetInfo. 5647 MaxAtomicInlineWidth = 64; 5648 5649 if (Triple.isWatchABI()) { 5650 // Darwin on iOS uses a variant of the ARM C++ ABI. 5651 TheCXXABI.set(TargetCXXABI::WatchOS); 5652 5653 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5654 // size_t is long, it's a bit weird for it to be int. 5655 PtrDiffType = SignedLong; 5656 5657 // BOOL should be a real boolean on the new ABI 5658 UseSignedCharForObjCBool = false; 5659 } else 5660 TheCXXABI.set(TargetCXXABI::iOS); 5661 } 5662 }; 5663 5664 class AArch64TargetInfo : public TargetInfo { 5665 virtual void setDataLayout() = 0; 5666 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5667 static const char *const GCCRegNames[]; 5668 5669 enum FPUModeEnum { 5670 FPUMode, 5671 NeonMode 5672 }; 5673 5674 unsigned FPU; 5675 unsigned CRC; 5676 unsigned Crypto; 5677 unsigned Unaligned; 5678 unsigned V8_1A; 5679 5680 static const Builtin::Info BuiltinInfo[]; 5681 5682 std::string ABI; 5683 5684 public: 5685 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5686 : TargetInfo(Triple), ABI("aapcs") { 5687 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5688 WCharType = SignedInt; 5689 5690 // NetBSD apparently prefers consistency across ARM targets to consistency 5691 // across 64-bit targets. 5692 Int64Type = SignedLongLong; 5693 IntMaxType = SignedLongLong; 5694 } else { 5695 WCharType = UnsignedInt; 5696 Int64Type = SignedLong; 5697 IntMaxType = SignedLong; 5698 } 5699 5700 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5701 MaxVectorAlign = 128; 5702 MaxAtomicInlineWidth = 128; 5703 MaxAtomicPromoteWidth = 128; 5704 5705 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5706 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5707 5708 // {} in inline assembly are neon specifiers, not assembly variant 5709 // specifiers. 5710 NoAsmVariants = true; 5711 5712 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5713 // contributes to the alignment of the containing aggregate in the same way 5714 // a plain (non bit-field) member of that type would, without exception for 5715 // zero-sized or anonymous bit-fields." 5716 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5717 UseZeroLengthBitfieldAlignment = true; 5718 5719 // AArch64 targets default to using the ARM C++ ABI. 5720 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5721 5722 if (Triple.getOS() == llvm::Triple::Linux || 5723 Triple.getOS() == llvm::Triple::UnknownOS) 5724 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5725 } 5726 5727 StringRef getABI() const override { return ABI; } 5728 bool setABI(const std::string &Name) override { 5729 if (Name != "aapcs" && Name != "darwinpcs") 5730 return false; 5731 5732 ABI = Name; 5733 return true; 5734 } 5735 5736 bool setCPU(const std::string &Name) override { 5737 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5738 .Case("generic", true) 5739 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5740 "cortex-a35", "exynos-m1", true) 5741 .Case("cortex-a73", true) 5742 .Case("cyclone", true) 5743 .Case("kryo", true) 5744 .Case("vulcan", true) 5745 .Default(false); 5746 return CPUKnown; 5747 } 5748 5749 void getTargetDefines(const LangOptions &Opts, 5750 MacroBuilder &Builder) const override { 5751 // Target identification. 5752 Builder.defineMacro("__aarch64__"); 5753 5754 // Target properties. 5755 Builder.defineMacro("_LP64"); 5756 Builder.defineMacro("__LP64__"); 5757 5758 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5759 Builder.defineMacro("__ARM_ACLE", "200"); 5760 Builder.defineMacro("__ARM_ARCH", "8"); 5761 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5762 5763 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5764 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5765 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5766 5767 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5768 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5769 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5770 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5771 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5772 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5773 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5774 5775 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5776 5777 // 0xe implies support for half, single and double precision operations. 5778 Builder.defineMacro("__ARM_FP", "0xE"); 5779 5780 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5781 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5782 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5783 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5784 5785 if (Opts.UnsafeFPMath) 5786 Builder.defineMacro("__ARM_FP_FAST", "1"); 5787 5788 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5789 5790 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5791 Opts.ShortEnums ? "1" : "4"); 5792 5793 if (FPU == NeonMode) { 5794 Builder.defineMacro("__ARM_NEON", "1"); 5795 // 64-bit NEON supports half, single and double precision operations. 5796 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5797 } 5798 5799 if (CRC) 5800 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5801 5802 if (Crypto) 5803 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5804 5805 if (Unaligned) 5806 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5807 5808 if (V8_1A) 5809 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5810 5811 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5812 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5813 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5814 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5815 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5816 } 5817 5818 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5819 return llvm::makeArrayRef(BuiltinInfo, 5820 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5821 } 5822 5823 bool hasFeature(StringRef Feature) const override { 5824 return Feature == "aarch64" || 5825 Feature == "arm64" || 5826 Feature == "arm" || 5827 (Feature == "neon" && FPU == NeonMode); 5828 } 5829 5830 bool handleTargetFeatures(std::vector<std::string> &Features, 5831 DiagnosticsEngine &Diags) override { 5832 FPU = FPUMode; 5833 CRC = 0; 5834 Crypto = 0; 5835 Unaligned = 1; 5836 V8_1A = 0; 5837 5838 for (const auto &Feature : Features) { 5839 if (Feature == "+neon") 5840 FPU = NeonMode; 5841 if (Feature == "+crc") 5842 CRC = 1; 5843 if (Feature == "+crypto") 5844 Crypto = 1; 5845 if (Feature == "+strict-align") 5846 Unaligned = 0; 5847 if (Feature == "+v8.1a") 5848 V8_1A = 1; 5849 } 5850 5851 setDataLayout(); 5852 5853 return true; 5854 } 5855 5856 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5857 switch (CC) { 5858 case CC_C: 5859 case CC_Swift: 5860 case CC_PreserveMost: 5861 case CC_PreserveAll: 5862 return CCCR_OK; 5863 default: 5864 return CCCR_Warning; 5865 } 5866 } 5867 5868 bool isCLZForZeroUndef() const override { return false; } 5869 5870 BuiltinVaListKind getBuiltinVaListKind() const override { 5871 return TargetInfo::AArch64ABIBuiltinVaList; 5872 } 5873 5874 ArrayRef<const char *> getGCCRegNames() const override; 5875 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5876 5877 bool validateAsmConstraint(const char *&Name, 5878 TargetInfo::ConstraintInfo &Info) const override { 5879 switch (*Name) { 5880 default: 5881 return false; 5882 case 'w': // Floating point and SIMD registers (V0-V31) 5883 Info.setAllowsRegister(); 5884 return true; 5885 case 'I': // Constant that can be used with an ADD instruction 5886 case 'J': // Constant that can be used with a SUB instruction 5887 case 'K': // Constant that can be used with a 32-bit logical instruction 5888 case 'L': // Constant that can be used with a 64-bit logical instruction 5889 case 'M': // Constant that can be used as a 32-bit MOV immediate 5890 case 'N': // Constant that can be used as a 64-bit MOV immediate 5891 case 'Y': // Floating point constant zero 5892 case 'Z': // Integer constant zero 5893 return true; 5894 case 'Q': // A memory reference with base register and no offset 5895 Info.setAllowsMemory(); 5896 return true; 5897 case 'S': // A symbolic address 5898 Info.setAllowsRegister(); 5899 return true; 5900 case 'U': 5901 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5902 // Utf: A memory address suitable for ldp/stp in TF mode. 5903 // Usa: An absolute symbolic address. 5904 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5905 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5906 case 'z': // Zero register, wzr or xzr 5907 Info.setAllowsRegister(); 5908 return true; 5909 case 'x': // Floating point and SIMD registers (V0-V15) 5910 Info.setAllowsRegister(); 5911 return true; 5912 } 5913 return false; 5914 } 5915 5916 bool 5917 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5918 std::string &SuggestedModifier) const override { 5919 // Strip off constraint modifiers. 5920 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5921 Constraint = Constraint.substr(1); 5922 5923 switch (Constraint[0]) { 5924 default: 5925 return true; 5926 case 'z': 5927 case 'r': { 5928 switch (Modifier) { 5929 case 'x': 5930 case 'w': 5931 // For now assume that the person knows what they're 5932 // doing with the modifier. 5933 return true; 5934 default: 5935 // By default an 'r' constraint will be in the 'x' 5936 // registers. 5937 if (Size == 64) 5938 return true; 5939 5940 SuggestedModifier = "w"; 5941 return false; 5942 } 5943 } 5944 } 5945 } 5946 5947 const char *getClobbers() const override { return ""; } 5948 5949 int getEHDataRegisterNumber(unsigned RegNo) const override { 5950 if (RegNo == 0) 5951 return 0; 5952 if (RegNo == 1) 5953 return 1; 5954 return -1; 5955 } 5956 }; 5957 5958 const char *const AArch64TargetInfo::GCCRegNames[] = { 5959 // 32-bit Integer registers 5960 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5961 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5962 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5963 5964 // 64-bit Integer registers 5965 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5966 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5967 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5968 5969 // 32-bit floating point regsisters 5970 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5971 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5972 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5973 5974 // 64-bit floating point regsisters 5975 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5976 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5977 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5978 5979 // Vector registers 5980 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5981 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5982 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5983 }; 5984 5985 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5986 return llvm::makeArrayRef(GCCRegNames); 5987 } 5988 5989 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5990 { { "w31" }, "wsp" }, 5991 { { "x29" }, "fp" }, 5992 { { "x30" }, "lr" }, 5993 { { "x31" }, "sp" }, 5994 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5995 // don't want to substitute one of these for a different-sized one. 5996 }; 5997 5998 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5999 return llvm::makeArrayRef(GCCRegAliases); 6000 } 6001 6002 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6003 #define BUILTIN(ID, TYPE, ATTRS) \ 6004 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6005 #include "clang/Basic/BuiltinsNEON.def" 6006 6007 #define BUILTIN(ID, TYPE, ATTRS) \ 6008 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6009 #include "clang/Basic/BuiltinsAArch64.def" 6010 }; 6011 6012 class AArch64leTargetInfo : public AArch64TargetInfo { 6013 void setDataLayout() override { 6014 if (getTriple().isOSBinFormatMachO()) 6015 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6016 else 6017 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6018 } 6019 6020 public: 6021 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6022 : AArch64TargetInfo(Triple, Opts) { 6023 BigEndian = false; 6024 } 6025 void getTargetDefines(const LangOptions &Opts, 6026 MacroBuilder &Builder) const override { 6027 Builder.defineMacro("__AARCH64EL__"); 6028 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6029 } 6030 }; 6031 6032 class AArch64beTargetInfo : public AArch64TargetInfo { 6033 void setDataLayout() override { 6034 assert(!getTriple().isOSBinFormatMachO()); 6035 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6036 } 6037 6038 public: 6039 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6040 : AArch64TargetInfo(Triple, Opts) {} 6041 void getTargetDefines(const LangOptions &Opts, 6042 MacroBuilder &Builder) const override { 6043 Builder.defineMacro("__AARCH64EB__"); 6044 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6045 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6046 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6047 } 6048 }; 6049 6050 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6051 protected: 6052 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6053 MacroBuilder &Builder) const override { 6054 Builder.defineMacro("__AARCH64_SIMD__"); 6055 Builder.defineMacro("__ARM64_ARCH_8__"); 6056 Builder.defineMacro("__ARM_NEON__"); 6057 Builder.defineMacro("__LITTLE_ENDIAN__"); 6058 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6059 Builder.defineMacro("__arm64", "1"); 6060 Builder.defineMacro("__arm64__", "1"); 6061 6062 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6063 } 6064 6065 public: 6066 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6067 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6068 Int64Type = SignedLongLong; 6069 WCharType = SignedInt; 6070 UseSignedCharForObjCBool = false; 6071 6072 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6073 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6074 6075 TheCXXABI.set(TargetCXXABI::iOS64); 6076 } 6077 6078 BuiltinVaListKind getBuiltinVaListKind() const override { 6079 return TargetInfo::CharPtrBuiltinVaList; 6080 } 6081 }; 6082 6083 // Hexagon abstract base class 6084 class HexagonTargetInfo : public TargetInfo { 6085 static const Builtin::Info BuiltinInfo[]; 6086 static const char * const GCCRegNames[]; 6087 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6088 std::string CPU; 6089 bool HasHVX, HasHVXDouble; 6090 6091 public: 6092 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6093 : TargetInfo(Triple) { 6094 BigEndian = false; 6095 // Specify the vector alignment explicitly. For v512x1, the calculated 6096 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6097 // the required minimum of 64 bytes. 6098 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6099 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6100 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6101 SizeType = UnsignedInt; 6102 PtrDiffType = SignedInt; 6103 IntPtrType = SignedInt; 6104 6105 // {} in inline assembly are packet specifiers, not assembly variant 6106 // specifiers. 6107 NoAsmVariants = true; 6108 6109 LargeArrayMinWidth = 64; 6110 LargeArrayAlign = 64; 6111 UseBitFieldTypeAlignment = true; 6112 ZeroLengthBitfieldBoundary = 32; 6113 HasHVX = HasHVXDouble = false; 6114 } 6115 6116 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6117 return llvm::makeArrayRef(BuiltinInfo, 6118 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6119 } 6120 6121 bool validateAsmConstraint(const char *&Name, 6122 TargetInfo::ConstraintInfo &Info) const override { 6123 switch (*Name) { 6124 case 'v': 6125 case 'q': 6126 if (HasHVX) { 6127 Info.setAllowsRegister(); 6128 return true; 6129 } 6130 break; 6131 case 's': 6132 // Relocatable constant. 6133 return true; 6134 } 6135 return false; 6136 } 6137 6138 void getTargetDefines(const LangOptions &Opts, 6139 MacroBuilder &Builder) const override; 6140 6141 bool isCLZForZeroUndef() const override { return false; } 6142 6143 bool hasFeature(StringRef Feature) const override { 6144 return llvm::StringSwitch<bool>(Feature) 6145 .Case("hexagon", true) 6146 .Case("hvx", HasHVX) 6147 .Case("hvx-double", HasHVXDouble) 6148 .Default(false); 6149 } 6150 6151 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6152 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6153 const override; 6154 6155 bool handleTargetFeatures(std::vector<std::string> &Features, 6156 DiagnosticsEngine &Diags) override; 6157 6158 BuiltinVaListKind getBuiltinVaListKind() const override { 6159 return TargetInfo::CharPtrBuiltinVaList; 6160 } 6161 ArrayRef<const char *> getGCCRegNames() const override; 6162 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6163 const char *getClobbers() const override { 6164 return ""; 6165 } 6166 6167 static const char *getHexagonCPUSuffix(StringRef Name) { 6168 return llvm::StringSwitch<const char*>(Name) 6169 .Case("hexagonv4", "4") 6170 .Case("hexagonv5", "5") 6171 .Case("hexagonv55", "55") 6172 .Case("hexagonv60", "60") 6173 .Default(nullptr); 6174 } 6175 6176 bool setCPU(const std::string &Name) override { 6177 if (!getHexagonCPUSuffix(Name)) 6178 return false; 6179 CPU = Name; 6180 return true; 6181 } 6182 6183 int getEHDataRegisterNumber(unsigned RegNo) const override { 6184 return RegNo < 2 ? RegNo : -1; 6185 } 6186 }; 6187 6188 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6189 MacroBuilder &Builder) const { 6190 Builder.defineMacro("__qdsp6__", "1"); 6191 Builder.defineMacro("__hexagon__", "1"); 6192 6193 if (CPU == "hexagonv4") { 6194 Builder.defineMacro("__HEXAGON_V4__"); 6195 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6196 if (Opts.HexagonQdsp6Compat) { 6197 Builder.defineMacro("__QDSP6_V4__"); 6198 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6199 } 6200 } else if (CPU == "hexagonv5") { 6201 Builder.defineMacro("__HEXAGON_V5__"); 6202 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6203 if(Opts.HexagonQdsp6Compat) { 6204 Builder.defineMacro("__QDSP6_V5__"); 6205 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6206 } 6207 } else if (CPU == "hexagonv55") { 6208 Builder.defineMacro("__HEXAGON_V55__"); 6209 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6210 Builder.defineMacro("__QDSP6_V55__"); 6211 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6212 } else if (CPU == "hexagonv60") { 6213 Builder.defineMacro("__HEXAGON_V60__"); 6214 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6215 Builder.defineMacro("__QDSP6_V60__"); 6216 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6217 } 6218 6219 if (hasFeature("hvx")) { 6220 Builder.defineMacro("__HVX__"); 6221 if (hasFeature("hvx-double")) 6222 Builder.defineMacro("__HVXDBL__"); 6223 } 6224 } 6225 6226 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6227 DiagnosticsEngine &Diags) { 6228 for (auto &F : Features) { 6229 if (F == "+hvx") 6230 HasHVX = true; 6231 else if (F == "-hvx") 6232 HasHVX = HasHVXDouble = false; 6233 else if (F == "+hvx-double") 6234 HasHVX = HasHVXDouble = true; 6235 else if (F == "-hvx-double") 6236 HasHVXDouble = false; 6237 } 6238 return true; 6239 } 6240 6241 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6242 DiagnosticsEngine &Diags, StringRef CPU, 6243 const std::vector<std::string> &FeaturesVec) const { 6244 // Default for v60: -hvx, -hvx-double. 6245 Features["hvx"] = false; 6246 Features["hvx-double"] = false; 6247 6248 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6249 } 6250 6251 6252 const char *const HexagonTargetInfo::GCCRegNames[] = { 6253 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6254 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6255 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6256 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6257 "p0", "p1", "p2", "p3", 6258 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6259 }; 6260 6261 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6262 return llvm::makeArrayRef(GCCRegNames); 6263 } 6264 6265 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6266 { { "sp" }, "r29" }, 6267 { { "fp" }, "r30" }, 6268 { { "lr" }, "r31" }, 6269 }; 6270 6271 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6272 return llvm::makeArrayRef(GCCRegAliases); 6273 } 6274 6275 6276 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6277 #define BUILTIN(ID, TYPE, ATTRS) \ 6278 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6279 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6280 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6281 #include "clang/Basic/BuiltinsHexagon.def" 6282 }; 6283 6284 class LanaiTargetInfo : public TargetInfo { 6285 // Class for Lanai (32-bit). 6286 // The CPU profiles supported by the Lanai backend 6287 enum CPUKind { 6288 CK_NONE, 6289 CK_V11, 6290 } CPU; 6291 6292 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6293 static const char *const GCCRegNames[]; 6294 6295 public: 6296 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6297 : TargetInfo(Triple) { 6298 // Description string has to be kept in sync with backend. 6299 resetDataLayout("E" // Big endian 6300 "-m:e" // ELF name manging 6301 "-p:32:32" // 32 bit pointers, 32 bit aligned 6302 "-i64:64" // 64 bit integers, 64 bit aligned 6303 "-a:0:32" // 32 bit alignment of objects of aggregate type 6304 "-n32" // 32 bit native integer width 6305 "-S64" // 64 bit natural stack alignment 6306 ); 6307 6308 // Setting RegParmMax equal to what mregparm was set to in the old 6309 // toolchain 6310 RegParmMax = 4; 6311 6312 // Set the default CPU to V11 6313 CPU = CK_V11; 6314 6315 // Temporary approach to make everything at least word-aligned and allow for 6316 // safely casting between pointers with different alignment requirements. 6317 // TODO: Remove this when there are no more cast align warnings on the 6318 // firmware. 6319 MinGlobalAlign = 32; 6320 } 6321 6322 void getTargetDefines(const LangOptions &Opts, 6323 MacroBuilder &Builder) const override { 6324 // Define __lanai__ when building for target lanai. 6325 Builder.defineMacro("__lanai__"); 6326 6327 // Set define for the CPU specified. 6328 switch (CPU) { 6329 case CK_V11: 6330 Builder.defineMacro("__LANAI_V11__"); 6331 break; 6332 case CK_NONE: 6333 llvm_unreachable("Unhandled target CPU"); 6334 } 6335 } 6336 6337 bool setCPU(const std::string &Name) override { 6338 CPU = llvm::StringSwitch<CPUKind>(Name) 6339 .Case("v11", CK_V11) 6340 .Default(CK_NONE); 6341 6342 return CPU != CK_NONE; 6343 } 6344 6345 bool hasFeature(StringRef Feature) const override { 6346 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6347 } 6348 6349 ArrayRef<const char *> getGCCRegNames() const override; 6350 6351 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6352 6353 BuiltinVaListKind getBuiltinVaListKind() const override { 6354 return TargetInfo::VoidPtrBuiltinVaList; 6355 } 6356 6357 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6358 6359 bool validateAsmConstraint(const char *&Name, 6360 TargetInfo::ConstraintInfo &info) const override { 6361 return false; 6362 } 6363 6364 const char *getClobbers() const override { return ""; } 6365 }; 6366 6367 const char *const LanaiTargetInfo::GCCRegNames[] = { 6368 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6369 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6370 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6371 6372 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6373 return llvm::makeArrayRef(GCCRegNames); 6374 } 6375 6376 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6377 {{"pc"}, "r2"}, 6378 {{"sp"}, "r4"}, 6379 {{"fp"}, "r5"}, 6380 {{"rv"}, "r8"}, 6381 {{"rr1"}, "r10"}, 6382 {{"rr2"}, "r11"}, 6383 {{"rca"}, "r15"}, 6384 }; 6385 6386 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6387 return llvm::makeArrayRef(GCCRegAliases); 6388 } 6389 6390 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6391 class SparcTargetInfo : public TargetInfo { 6392 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6393 static const char * const GCCRegNames[]; 6394 bool SoftFloat; 6395 public: 6396 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6397 : TargetInfo(Triple), SoftFloat(false) {} 6398 6399 int getEHDataRegisterNumber(unsigned RegNo) const override { 6400 if (RegNo == 0) return 24; 6401 if (RegNo == 1) return 25; 6402 return -1; 6403 } 6404 6405 bool handleTargetFeatures(std::vector<std::string> &Features, 6406 DiagnosticsEngine &Diags) override { 6407 // Check if software floating point is enabled 6408 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6409 if (Feature != Features.end()) { 6410 SoftFloat = true; 6411 } 6412 return true; 6413 } 6414 void getTargetDefines(const LangOptions &Opts, 6415 MacroBuilder &Builder) const override { 6416 DefineStd(Builder, "sparc", Opts); 6417 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6418 6419 if (SoftFloat) 6420 Builder.defineMacro("SOFT_FLOAT", "1"); 6421 } 6422 6423 bool hasFeature(StringRef Feature) const override { 6424 return llvm::StringSwitch<bool>(Feature) 6425 .Case("softfloat", SoftFloat) 6426 .Case("sparc", true) 6427 .Default(false); 6428 } 6429 6430 bool hasSjLjLowering() const override { 6431 return true; 6432 } 6433 6434 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6435 // FIXME: Implement! 6436 return None; 6437 } 6438 BuiltinVaListKind getBuiltinVaListKind() const override { 6439 return TargetInfo::VoidPtrBuiltinVaList; 6440 } 6441 ArrayRef<const char *> getGCCRegNames() const override; 6442 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6443 bool validateAsmConstraint(const char *&Name, 6444 TargetInfo::ConstraintInfo &info) const override { 6445 // FIXME: Implement! 6446 switch (*Name) { 6447 case 'I': // Signed 13-bit constant 6448 case 'J': // Zero 6449 case 'K': // 32-bit constant with the low 12 bits clear 6450 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6451 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6452 case 'N': // Same as 'K' but zext (required for SIMode) 6453 case 'O': // The constant 4096 6454 return true; 6455 } 6456 return false; 6457 } 6458 const char *getClobbers() const override { 6459 // FIXME: Implement! 6460 return ""; 6461 } 6462 6463 // No Sparc V7 for now, the backend doesn't support it anyway. 6464 enum CPUKind { 6465 CK_GENERIC, 6466 CK_V8, 6467 CK_SUPERSPARC, 6468 CK_SPARCLITE, 6469 CK_F934, 6470 CK_HYPERSPARC, 6471 CK_SPARCLITE86X, 6472 CK_SPARCLET, 6473 CK_TSC701, 6474 CK_V9, 6475 CK_ULTRASPARC, 6476 CK_ULTRASPARC3, 6477 CK_NIAGARA, 6478 CK_NIAGARA2, 6479 CK_NIAGARA3, 6480 CK_NIAGARA4, 6481 CK_MYRIAD2_1, 6482 CK_MYRIAD2_2, 6483 CK_LEON2, 6484 CK_LEON2_AT697E, 6485 CK_LEON2_AT697F, 6486 CK_LEON3, 6487 CK_LEON3_UT699, 6488 CK_LEON3_GR712RC, 6489 CK_LEON4, 6490 CK_LEON4_GR740 6491 } CPU = CK_GENERIC; 6492 6493 enum CPUGeneration { 6494 CG_V8, 6495 CG_V9, 6496 }; 6497 6498 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6499 switch (Kind) { 6500 case CK_GENERIC: 6501 case CK_V8: 6502 case CK_SUPERSPARC: 6503 case CK_SPARCLITE: 6504 case CK_F934: 6505 case CK_HYPERSPARC: 6506 case CK_SPARCLITE86X: 6507 case CK_SPARCLET: 6508 case CK_TSC701: 6509 case CK_MYRIAD2_1: 6510 case CK_MYRIAD2_2: 6511 case CK_LEON2: 6512 case CK_LEON2_AT697E: 6513 case CK_LEON2_AT697F: 6514 case CK_LEON3: 6515 case CK_LEON3_UT699: 6516 case CK_LEON3_GR712RC: 6517 case CK_LEON4: 6518 case CK_LEON4_GR740: 6519 return CG_V8; 6520 case CK_V9: 6521 case CK_ULTRASPARC: 6522 case CK_ULTRASPARC3: 6523 case CK_NIAGARA: 6524 case CK_NIAGARA2: 6525 case CK_NIAGARA3: 6526 case CK_NIAGARA4: 6527 return CG_V9; 6528 } 6529 llvm_unreachable("Unexpected CPU kind"); 6530 } 6531 6532 CPUKind getCPUKind(StringRef Name) const { 6533 return llvm::StringSwitch<CPUKind>(Name) 6534 .Case("v8", CK_V8) 6535 .Case("supersparc", CK_SUPERSPARC) 6536 .Case("sparclite", CK_SPARCLITE) 6537 .Case("f934", CK_F934) 6538 .Case("hypersparc", CK_HYPERSPARC) 6539 .Case("sparclite86x", CK_SPARCLITE86X) 6540 .Case("sparclet", CK_SPARCLET) 6541 .Case("tsc701", CK_TSC701) 6542 .Case("v9", CK_V9) 6543 .Case("ultrasparc", CK_ULTRASPARC) 6544 .Case("ultrasparc3", CK_ULTRASPARC3) 6545 .Case("niagara", CK_NIAGARA) 6546 .Case("niagara2", CK_NIAGARA2) 6547 .Case("niagara3", CK_NIAGARA3) 6548 .Case("niagara4", CK_NIAGARA4) 6549 .Case("myriad2", CK_MYRIAD2_1) 6550 .Case("myriad2.1", CK_MYRIAD2_1) 6551 .Case("myriad2.2", CK_MYRIAD2_2) 6552 .Case("leon2", CK_LEON2) 6553 .Case("at697e", CK_LEON2_AT697E) 6554 .Case("at697f", CK_LEON2_AT697F) 6555 .Case("leon3", CK_LEON3) 6556 .Case("ut699", CK_LEON3_UT699) 6557 .Case("gr712rc", CK_LEON3_GR712RC) 6558 .Case("leon4", CK_LEON4) 6559 .Case("gr740", CK_LEON4_GR740) 6560 .Default(CK_GENERIC); 6561 } 6562 6563 bool setCPU(const std::string &Name) override { 6564 CPU = getCPUKind(Name); 6565 return CPU != CK_GENERIC; 6566 } 6567 }; 6568 6569 const char * const SparcTargetInfo::GCCRegNames[] = { 6570 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6571 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6572 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6573 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6574 }; 6575 6576 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6577 return llvm::makeArrayRef(GCCRegNames); 6578 } 6579 6580 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6581 { { "g0" }, "r0" }, 6582 { { "g1" }, "r1" }, 6583 { { "g2" }, "r2" }, 6584 { { "g3" }, "r3" }, 6585 { { "g4" }, "r4" }, 6586 { { "g5" }, "r5" }, 6587 { { "g6" }, "r6" }, 6588 { { "g7" }, "r7" }, 6589 { { "o0" }, "r8" }, 6590 { { "o1" }, "r9" }, 6591 { { "o2" }, "r10" }, 6592 { { "o3" }, "r11" }, 6593 { { "o4" }, "r12" }, 6594 { { "o5" }, "r13" }, 6595 { { "o6", "sp" }, "r14" }, 6596 { { "o7" }, "r15" }, 6597 { { "l0" }, "r16" }, 6598 { { "l1" }, "r17" }, 6599 { { "l2" }, "r18" }, 6600 { { "l3" }, "r19" }, 6601 { { "l4" }, "r20" }, 6602 { { "l5" }, "r21" }, 6603 { { "l6" }, "r22" }, 6604 { { "l7" }, "r23" }, 6605 { { "i0" }, "r24" }, 6606 { { "i1" }, "r25" }, 6607 { { "i2" }, "r26" }, 6608 { { "i3" }, "r27" }, 6609 { { "i4" }, "r28" }, 6610 { { "i5" }, "r29" }, 6611 { { "i6", "fp" }, "r30" }, 6612 { { "i7" }, "r31" }, 6613 }; 6614 6615 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6616 return llvm::makeArrayRef(GCCRegAliases); 6617 } 6618 6619 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6620 class SparcV8TargetInfo : public SparcTargetInfo { 6621 public: 6622 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6623 : SparcTargetInfo(Triple, Opts) { 6624 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6625 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6626 switch (getTriple().getOS()) { 6627 default: 6628 SizeType = UnsignedInt; 6629 IntPtrType = SignedInt; 6630 PtrDiffType = SignedInt; 6631 break; 6632 case llvm::Triple::NetBSD: 6633 case llvm::Triple::OpenBSD: 6634 SizeType = UnsignedLong; 6635 IntPtrType = SignedLong; 6636 PtrDiffType = SignedLong; 6637 break; 6638 } 6639 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6640 } 6641 6642 void getTargetDefines(const LangOptions &Opts, 6643 MacroBuilder &Builder) const override { 6644 SparcTargetInfo::getTargetDefines(Opts, Builder); 6645 switch (getCPUGeneration(CPU)) { 6646 case CG_V8: 6647 Builder.defineMacro("__sparcv8"); 6648 if (getTriple().getOS() != llvm::Triple::Solaris) 6649 Builder.defineMacro("__sparcv8__"); 6650 break; 6651 case CG_V9: 6652 Builder.defineMacro("__sparcv9"); 6653 if (getTriple().getOS() != llvm::Triple::Solaris) { 6654 Builder.defineMacro("__sparcv9__"); 6655 Builder.defineMacro("__sparc_v9__"); 6656 } 6657 break; 6658 } 6659 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6660 switch (CPU) { 6661 case CK_MYRIAD2_1: 6662 Builder.defineMacro("__myriad2", "1"); 6663 Builder.defineMacro("__myriad2__", "1"); 6664 break; 6665 case CK_MYRIAD2_2: 6666 Builder.defineMacro("__myriad2", "2"); 6667 Builder.defineMacro("__myriad2__", "2"); 6668 break; 6669 default: 6670 break; 6671 } 6672 } 6673 } 6674 6675 bool hasSjLjLowering() const override { 6676 return true; 6677 } 6678 }; 6679 6680 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6681 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6682 public: 6683 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6684 : SparcV8TargetInfo(Triple, Opts) { 6685 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6686 BigEndian = false; 6687 } 6688 }; 6689 6690 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6691 class SparcV9TargetInfo : public SparcTargetInfo { 6692 public: 6693 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6694 : SparcTargetInfo(Triple, Opts) { 6695 // FIXME: Support Sparc quad-precision long double? 6696 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6697 // This is an LP64 platform. 6698 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6699 6700 // OpenBSD uses long long for int64_t and intmax_t. 6701 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6702 IntMaxType = SignedLongLong; 6703 else 6704 IntMaxType = SignedLong; 6705 Int64Type = IntMaxType; 6706 6707 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6708 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6709 LongDoubleWidth = 128; 6710 LongDoubleAlign = 128; 6711 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6712 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6713 } 6714 6715 void getTargetDefines(const LangOptions &Opts, 6716 MacroBuilder &Builder) const override { 6717 SparcTargetInfo::getTargetDefines(Opts, Builder); 6718 Builder.defineMacro("__sparcv9"); 6719 Builder.defineMacro("__arch64__"); 6720 // Solaris doesn't need these variants, but the BSDs do. 6721 if (getTriple().getOS() != llvm::Triple::Solaris) { 6722 Builder.defineMacro("__sparc64__"); 6723 Builder.defineMacro("__sparc_v9__"); 6724 Builder.defineMacro("__sparcv9__"); 6725 } 6726 } 6727 6728 bool setCPU(const std::string &Name) override { 6729 if (!SparcTargetInfo::setCPU(Name)) 6730 return false; 6731 return getCPUGeneration(CPU) == CG_V9; 6732 } 6733 }; 6734 6735 class SystemZTargetInfo : public TargetInfo { 6736 static const Builtin::Info BuiltinInfo[]; 6737 static const char *const GCCRegNames[]; 6738 std::string CPU; 6739 bool HasTransactionalExecution; 6740 bool HasVector; 6741 6742 public: 6743 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6744 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6745 HasVector(false) { 6746 IntMaxType = SignedLong; 6747 Int64Type = SignedLong; 6748 TLSSupported = true; 6749 IntWidth = IntAlign = 32; 6750 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6751 PointerWidth = PointerAlign = 64; 6752 LongDoubleWidth = 128; 6753 LongDoubleAlign = 64; 6754 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6755 DefaultAlignForAttributeAligned = 64; 6756 MinGlobalAlign = 16; 6757 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6758 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6759 } 6760 void getTargetDefines(const LangOptions &Opts, 6761 MacroBuilder &Builder) const override { 6762 Builder.defineMacro("__s390__"); 6763 Builder.defineMacro("__s390x__"); 6764 Builder.defineMacro("__zarch__"); 6765 Builder.defineMacro("__LONG_DOUBLE_128__"); 6766 6767 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6768 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6769 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6770 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6771 6772 if (HasTransactionalExecution) 6773 Builder.defineMacro("__HTM__"); 6774 if (Opts.ZVector) 6775 Builder.defineMacro("__VEC__", "10301"); 6776 } 6777 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6778 return llvm::makeArrayRef(BuiltinInfo, 6779 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6780 } 6781 6782 ArrayRef<const char *> getGCCRegNames() const override; 6783 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6784 // No aliases. 6785 return None; 6786 } 6787 bool validateAsmConstraint(const char *&Name, 6788 TargetInfo::ConstraintInfo &info) const override; 6789 const char *getClobbers() const override { 6790 // FIXME: Is this really right? 6791 return ""; 6792 } 6793 BuiltinVaListKind getBuiltinVaListKind() const override { 6794 return TargetInfo::SystemZBuiltinVaList; 6795 } 6796 bool setCPU(const std::string &Name) override { 6797 CPU = Name; 6798 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6799 .Case("z10", true) 6800 .Case("z196", true) 6801 .Case("zEC12", true) 6802 .Case("z13", true) 6803 .Default(false); 6804 6805 return CPUKnown; 6806 } 6807 bool 6808 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6809 StringRef CPU, 6810 const std::vector<std::string> &FeaturesVec) const override { 6811 if (CPU == "zEC12") 6812 Features["transactional-execution"] = true; 6813 if (CPU == "z13") { 6814 Features["transactional-execution"] = true; 6815 Features["vector"] = true; 6816 } 6817 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6818 } 6819 6820 bool handleTargetFeatures(std::vector<std::string> &Features, 6821 DiagnosticsEngine &Diags) override { 6822 HasTransactionalExecution = false; 6823 for (const auto &Feature : Features) { 6824 if (Feature == "+transactional-execution") 6825 HasTransactionalExecution = true; 6826 else if (Feature == "+vector") 6827 HasVector = true; 6828 } 6829 // If we use the vector ABI, vector types are 64-bit aligned. 6830 if (HasVector) { 6831 MaxVectorAlign = 64; 6832 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6833 "-v128:64-a:8:16-n32:64"); 6834 } 6835 return true; 6836 } 6837 6838 bool hasFeature(StringRef Feature) const override { 6839 return llvm::StringSwitch<bool>(Feature) 6840 .Case("systemz", true) 6841 .Case("htm", HasTransactionalExecution) 6842 .Case("vx", HasVector) 6843 .Default(false); 6844 } 6845 6846 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6847 switch (CC) { 6848 case CC_C: 6849 case CC_Swift: 6850 return CCCR_OK; 6851 default: 6852 return CCCR_Warning; 6853 } 6854 } 6855 6856 StringRef getABI() const override { 6857 if (HasVector) 6858 return "vector"; 6859 return ""; 6860 } 6861 6862 bool useFloat128ManglingForLongDouble() const override { 6863 return true; 6864 } 6865 }; 6866 6867 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6868 #define BUILTIN(ID, TYPE, ATTRS) \ 6869 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6870 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6871 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6872 #include "clang/Basic/BuiltinsSystemZ.def" 6873 }; 6874 6875 const char *const SystemZTargetInfo::GCCRegNames[] = { 6876 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6877 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6878 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6879 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6880 }; 6881 6882 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6883 return llvm::makeArrayRef(GCCRegNames); 6884 } 6885 6886 bool SystemZTargetInfo:: 6887 validateAsmConstraint(const char *&Name, 6888 TargetInfo::ConstraintInfo &Info) const { 6889 switch (*Name) { 6890 default: 6891 return false; 6892 6893 case 'a': // Address register 6894 case 'd': // Data register (equivalent to 'r') 6895 case 'f': // Floating-point register 6896 Info.setAllowsRegister(); 6897 return true; 6898 6899 case 'I': // Unsigned 8-bit constant 6900 case 'J': // Unsigned 12-bit constant 6901 case 'K': // Signed 16-bit constant 6902 case 'L': // Signed 20-bit displacement (on all targets we support) 6903 case 'M': // 0x7fffffff 6904 return true; 6905 6906 case 'Q': // Memory with base and unsigned 12-bit displacement 6907 case 'R': // Likewise, plus an index 6908 case 'S': // Memory with base and signed 20-bit displacement 6909 case 'T': // Likewise, plus an index 6910 Info.setAllowsMemory(); 6911 return true; 6912 } 6913 } 6914 6915 class MSP430TargetInfo : public TargetInfo { 6916 static const char *const GCCRegNames[]; 6917 6918 public: 6919 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6920 : TargetInfo(Triple) { 6921 BigEndian = false; 6922 TLSSupported = false; 6923 IntWidth = 16; 6924 IntAlign = 16; 6925 LongWidth = 32; 6926 LongLongWidth = 64; 6927 LongAlign = LongLongAlign = 16; 6928 PointerWidth = 16; 6929 PointerAlign = 16; 6930 SuitableAlign = 16; 6931 SizeType = UnsignedInt; 6932 IntMaxType = SignedLongLong; 6933 IntPtrType = SignedInt; 6934 PtrDiffType = SignedInt; 6935 SigAtomicType = SignedLong; 6936 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6937 } 6938 void getTargetDefines(const LangOptions &Opts, 6939 MacroBuilder &Builder) const override { 6940 Builder.defineMacro("MSP430"); 6941 Builder.defineMacro("__MSP430__"); 6942 // FIXME: defines for different 'flavours' of MCU 6943 } 6944 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6945 // FIXME: Implement. 6946 return None; 6947 } 6948 bool hasFeature(StringRef Feature) const override { 6949 return Feature == "msp430"; 6950 } 6951 ArrayRef<const char *> getGCCRegNames() const override; 6952 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6953 // No aliases. 6954 return None; 6955 } 6956 bool validateAsmConstraint(const char *&Name, 6957 TargetInfo::ConstraintInfo &info) const override { 6958 // FIXME: implement 6959 switch (*Name) { 6960 case 'K': // the constant 1 6961 case 'L': // constant -1^20 .. 1^19 6962 case 'M': // constant 1-4: 6963 return true; 6964 } 6965 // No target constraints for now. 6966 return false; 6967 } 6968 const char *getClobbers() const override { 6969 // FIXME: Is this really right? 6970 return ""; 6971 } 6972 BuiltinVaListKind getBuiltinVaListKind() const override { 6973 // FIXME: implement 6974 return TargetInfo::CharPtrBuiltinVaList; 6975 } 6976 }; 6977 6978 const char *const MSP430TargetInfo::GCCRegNames[] = { 6979 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6980 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6981 6982 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6983 return llvm::makeArrayRef(GCCRegNames); 6984 } 6985 6986 // LLVM and Clang cannot be used directly to output native binaries for 6987 // target, but is used to compile C code to llvm bitcode with correct 6988 // type and alignment information. 6989 // 6990 // TCE uses the llvm bitcode as input and uses it for generating customized 6991 // target processor and program binary. TCE co-design environment is 6992 // publicly available in http://tce.cs.tut.fi 6993 6994 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6995 3, // opencl_global 6996 4, // opencl_local 6997 5, // opencl_constant 6998 // FIXME: generic has to be added to the target 6999 0, // opencl_generic 7000 0, // cuda_device 7001 0, // cuda_constant 7002 0 // cuda_shared 7003 }; 7004 7005 class TCETargetInfo : public TargetInfo { 7006 public: 7007 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7008 : TargetInfo(Triple) { 7009 TLSSupported = false; 7010 IntWidth = 32; 7011 LongWidth = LongLongWidth = 32; 7012 PointerWidth = 32; 7013 IntAlign = 32; 7014 LongAlign = LongLongAlign = 32; 7015 PointerAlign = 32; 7016 SuitableAlign = 32; 7017 SizeType = UnsignedInt; 7018 IntMaxType = SignedLong; 7019 IntPtrType = SignedInt; 7020 PtrDiffType = SignedInt; 7021 FloatWidth = 32; 7022 FloatAlign = 32; 7023 DoubleWidth = 32; 7024 DoubleAlign = 32; 7025 LongDoubleWidth = 32; 7026 LongDoubleAlign = 32; 7027 FloatFormat = &llvm::APFloat::IEEEsingle; 7028 DoubleFormat = &llvm::APFloat::IEEEsingle; 7029 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 7030 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 7031 "-f64:32-v64:32-v128:32-a:0:32-n32"); 7032 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7033 UseAddrSpaceMapMangling = true; 7034 } 7035 7036 void getTargetDefines(const LangOptions &Opts, 7037 MacroBuilder &Builder) const override { 7038 DefineStd(Builder, "tce", Opts); 7039 Builder.defineMacro("__TCE__"); 7040 Builder.defineMacro("__TCE_V1__"); 7041 } 7042 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7043 7044 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7045 const char *getClobbers() const override { return ""; } 7046 BuiltinVaListKind getBuiltinVaListKind() const override { 7047 return TargetInfo::VoidPtrBuiltinVaList; 7048 } 7049 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7050 bool validateAsmConstraint(const char *&Name, 7051 TargetInfo::ConstraintInfo &info) const override { 7052 return true; 7053 } 7054 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7055 return None; 7056 } 7057 }; 7058 7059 class BPFTargetInfo : public TargetInfo { 7060 public: 7061 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7062 : TargetInfo(Triple) { 7063 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7064 SizeType = UnsignedLong; 7065 PtrDiffType = SignedLong; 7066 IntPtrType = SignedLong; 7067 IntMaxType = SignedLong; 7068 Int64Type = SignedLong; 7069 RegParmMax = 5; 7070 if (Triple.getArch() == llvm::Triple::bpfeb) { 7071 BigEndian = true; 7072 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7073 } else { 7074 BigEndian = false; 7075 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7076 } 7077 MaxAtomicPromoteWidth = 64; 7078 MaxAtomicInlineWidth = 64; 7079 TLSSupported = false; 7080 } 7081 void getTargetDefines(const LangOptions &Opts, 7082 MacroBuilder &Builder) const override { 7083 DefineStd(Builder, "bpf", Opts); 7084 Builder.defineMacro("__BPF__"); 7085 } 7086 bool hasFeature(StringRef Feature) const override { 7087 return Feature == "bpf"; 7088 } 7089 7090 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7091 const char *getClobbers() const override { 7092 return ""; 7093 } 7094 BuiltinVaListKind getBuiltinVaListKind() const override { 7095 return TargetInfo::VoidPtrBuiltinVaList; 7096 } 7097 ArrayRef<const char *> getGCCRegNames() const override { 7098 return None; 7099 } 7100 bool validateAsmConstraint(const char *&Name, 7101 TargetInfo::ConstraintInfo &info) const override { 7102 return true; 7103 } 7104 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7105 return None; 7106 } 7107 }; 7108 7109 class MipsTargetInfo : public TargetInfo { 7110 void setDataLayout() { 7111 StringRef Layout; 7112 7113 if (ABI == "o32") 7114 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7115 else if (ABI == "n32") 7116 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7117 else if (ABI == "n64") 7118 Layout = "m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7119 else 7120 llvm_unreachable("Invalid ABI"); 7121 7122 if (BigEndian) 7123 resetDataLayout(("E-" + Layout).str()); 7124 else 7125 resetDataLayout(("e-" + Layout).str()); 7126 } 7127 7128 7129 static const Builtin::Info BuiltinInfo[]; 7130 std::string CPU; 7131 bool IsMips16; 7132 bool IsMicromips; 7133 bool IsNan2008; 7134 bool IsSingleFloat; 7135 enum MipsFloatABI { 7136 HardFloat, SoftFloat 7137 } FloatABI; 7138 enum DspRevEnum { 7139 NoDSP, DSP1, DSP2 7140 } DspRev; 7141 bool HasMSA; 7142 7143 protected: 7144 bool HasFP64; 7145 std::string ABI; 7146 7147 public: 7148 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7149 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7150 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7151 DspRev(NoDSP), HasMSA(false), HasFP64(false) { 7152 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7153 BigEndian = getTriple().getArch() == llvm::Triple::mips || 7154 getTriple().getArch() == llvm::Triple::mips64; 7155 7156 setABI((getTriple().getArch() == llvm::Triple::mips || 7157 getTriple().getArch() == llvm::Triple::mipsel) 7158 ? "o32" 7159 : "n64"); 7160 7161 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7162 } 7163 7164 bool isNaN2008Default() const { 7165 return CPU == "mips32r6" || CPU == "mips64r6"; 7166 } 7167 7168 bool isFP64Default() const { 7169 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7170 } 7171 7172 bool isNan2008() const override { 7173 return IsNan2008; 7174 } 7175 7176 bool processorSupportsGPR64() const { 7177 return llvm::StringSwitch<bool>(CPU) 7178 .Case("mips3", true) 7179 .Case("mips4", true) 7180 .Case("mips5", true) 7181 .Case("mips64", true) 7182 .Case("mips64r2", true) 7183 .Case("mips64r3", true) 7184 .Case("mips64r5", true) 7185 .Case("mips64r6", true) 7186 .Case("octeon", true) 7187 .Default(false); 7188 return false; 7189 } 7190 7191 StringRef getABI() const override { return ABI; } 7192 bool setABI(const std::string &Name) override { 7193 if (Name == "o32") { 7194 setO32ABITypes(); 7195 ABI = Name; 7196 return true; 7197 } 7198 7199 if (Name == "n32") { 7200 setN32ABITypes(); 7201 ABI = Name; 7202 return true; 7203 } 7204 if (Name == "n64") { 7205 setN64ABITypes(); 7206 ABI = Name; 7207 return true; 7208 } 7209 return false; 7210 } 7211 7212 void setO32ABITypes() { 7213 Int64Type = SignedLongLong; 7214 IntMaxType = Int64Type; 7215 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7216 LongDoubleWidth = LongDoubleAlign = 64; 7217 LongWidth = LongAlign = 32; 7218 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7219 PointerWidth = PointerAlign = 32; 7220 PtrDiffType = SignedInt; 7221 SizeType = UnsignedInt; 7222 SuitableAlign = 64; 7223 } 7224 7225 void setN32N64ABITypes() { 7226 LongDoubleWidth = LongDoubleAlign = 128; 7227 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7228 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7229 LongDoubleWidth = LongDoubleAlign = 64; 7230 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7231 } 7232 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7233 SuitableAlign = 128; 7234 } 7235 7236 void setN64ABITypes() { 7237 setN32N64ABITypes(); 7238 Int64Type = SignedLong; 7239 IntMaxType = Int64Type; 7240 LongWidth = LongAlign = 64; 7241 PointerWidth = PointerAlign = 64; 7242 PtrDiffType = SignedLong; 7243 SizeType = UnsignedLong; 7244 } 7245 7246 void setN32ABITypes() { 7247 setN32N64ABITypes(); 7248 Int64Type = SignedLongLong; 7249 IntMaxType = Int64Type; 7250 LongWidth = LongAlign = 32; 7251 PointerWidth = PointerAlign = 32; 7252 PtrDiffType = SignedInt; 7253 SizeType = UnsignedInt; 7254 } 7255 7256 bool setCPU(const std::string &Name) override { 7257 CPU = Name; 7258 return llvm::StringSwitch<bool>(Name) 7259 .Case("mips1", true) 7260 .Case("mips2", true) 7261 .Case("mips3", true) 7262 .Case("mips4", true) 7263 .Case("mips5", true) 7264 .Case("mips32", true) 7265 .Case("mips32r2", true) 7266 .Case("mips32r3", true) 7267 .Case("mips32r5", true) 7268 .Case("mips32r6", true) 7269 .Case("mips64", true) 7270 .Case("mips64r2", true) 7271 .Case("mips64r3", true) 7272 .Case("mips64r5", true) 7273 .Case("mips64r6", true) 7274 .Case("octeon", true) 7275 .Case("p5600", true) 7276 .Default(false); 7277 } 7278 const std::string& getCPU() const { return CPU; } 7279 bool 7280 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7281 StringRef CPU, 7282 const std::vector<std::string> &FeaturesVec) const override { 7283 if (CPU.empty()) 7284 CPU = getCPU(); 7285 if (CPU == "octeon") 7286 Features["mips64r2"] = Features["cnmips"] = true; 7287 else 7288 Features[CPU] = true; 7289 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7290 } 7291 7292 void getTargetDefines(const LangOptions &Opts, 7293 MacroBuilder &Builder) const override { 7294 if (BigEndian) { 7295 DefineStd(Builder, "MIPSEB", Opts); 7296 Builder.defineMacro("_MIPSEB"); 7297 } else { 7298 DefineStd(Builder, "MIPSEL", Opts); 7299 Builder.defineMacro("_MIPSEL"); 7300 } 7301 7302 Builder.defineMacro("__mips__"); 7303 Builder.defineMacro("_mips"); 7304 if (Opts.GNUMode) 7305 Builder.defineMacro("mips"); 7306 7307 if (ABI == "o32") { 7308 Builder.defineMacro("__mips", "32"); 7309 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7310 } else { 7311 Builder.defineMacro("__mips", "64"); 7312 Builder.defineMacro("__mips64"); 7313 Builder.defineMacro("__mips64__"); 7314 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7315 } 7316 7317 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7318 .Cases("mips32", "mips64", "1") 7319 .Cases("mips32r2", "mips64r2", "2") 7320 .Cases("mips32r3", "mips64r3", "3") 7321 .Cases("mips32r5", "mips64r5", "5") 7322 .Cases("mips32r6", "mips64r6", "6") 7323 .Default(""); 7324 if (!ISARev.empty()) 7325 Builder.defineMacro("__mips_isa_rev", ISARev); 7326 7327 if (ABI == "o32") { 7328 Builder.defineMacro("__mips_o32"); 7329 Builder.defineMacro("_ABIO32", "1"); 7330 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7331 } else if (ABI == "n32") { 7332 Builder.defineMacro("__mips_n32"); 7333 Builder.defineMacro("_ABIN32", "2"); 7334 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7335 } else if (ABI == "n64") { 7336 Builder.defineMacro("__mips_n64"); 7337 Builder.defineMacro("_ABI64", "3"); 7338 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7339 } else 7340 llvm_unreachable("Invalid ABI."); 7341 7342 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7343 7344 switch (FloatABI) { 7345 case HardFloat: 7346 Builder.defineMacro("__mips_hard_float", Twine(1)); 7347 break; 7348 case SoftFloat: 7349 Builder.defineMacro("__mips_soft_float", Twine(1)); 7350 break; 7351 } 7352 7353 if (IsSingleFloat) 7354 Builder.defineMacro("__mips_single_float", Twine(1)); 7355 7356 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7357 Builder.defineMacro("_MIPS_FPSET", 7358 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7359 7360 if (IsMips16) 7361 Builder.defineMacro("__mips16", Twine(1)); 7362 7363 if (IsMicromips) 7364 Builder.defineMacro("__mips_micromips", Twine(1)); 7365 7366 if (IsNan2008) 7367 Builder.defineMacro("__mips_nan2008", Twine(1)); 7368 7369 switch (DspRev) { 7370 default: 7371 break; 7372 case DSP1: 7373 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7374 Builder.defineMacro("__mips_dsp", Twine(1)); 7375 break; 7376 case DSP2: 7377 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7378 Builder.defineMacro("__mips_dspr2", Twine(1)); 7379 Builder.defineMacro("__mips_dsp", Twine(1)); 7380 break; 7381 } 7382 7383 if (HasMSA) 7384 Builder.defineMacro("__mips_msa", Twine(1)); 7385 7386 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7387 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7388 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7389 7390 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7391 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7392 7393 // These shouldn't be defined for MIPS-I but there's no need to check 7394 // for that since MIPS-I isn't supported. 7395 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7397 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7398 7399 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7400 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7401 // the instructions exist but using them violates the ABI since they 7402 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7403 if (ABI == "n32" || ABI == "n64") 7404 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7405 } 7406 7407 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7408 return llvm::makeArrayRef(BuiltinInfo, 7409 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7410 } 7411 bool hasFeature(StringRef Feature) const override { 7412 return llvm::StringSwitch<bool>(Feature) 7413 .Case("mips", true) 7414 .Case("fp64", HasFP64) 7415 .Default(false); 7416 } 7417 BuiltinVaListKind getBuiltinVaListKind() const override { 7418 return TargetInfo::VoidPtrBuiltinVaList; 7419 } 7420 ArrayRef<const char *> getGCCRegNames() const override { 7421 static const char *const GCCRegNames[] = { 7422 // CPU register names 7423 // Must match second column of GCCRegAliases 7424 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7425 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7426 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7427 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7428 // Floating point register names 7429 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7430 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7431 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7432 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7433 // Hi/lo and condition register names 7434 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7435 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7436 "$ac3hi","$ac3lo", 7437 // MSA register names 7438 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7439 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7440 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7441 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7442 // MSA control register names 7443 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7444 "$msarequest", "$msamap", "$msaunmap" 7445 }; 7446 return llvm::makeArrayRef(GCCRegNames); 7447 } 7448 bool validateAsmConstraint(const char *&Name, 7449 TargetInfo::ConstraintInfo &Info) const override { 7450 switch (*Name) { 7451 default: 7452 return false; 7453 case 'r': // CPU registers. 7454 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7455 case 'y': // Equivalent to "r", backward compatibility only. 7456 case 'f': // floating-point registers. 7457 case 'c': // $25 for indirect jumps 7458 case 'l': // lo register 7459 case 'x': // hilo register pair 7460 Info.setAllowsRegister(); 7461 return true; 7462 case 'I': // Signed 16-bit constant 7463 case 'J': // Integer 0 7464 case 'K': // Unsigned 16-bit constant 7465 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7466 case 'M': // Constants not loadable via lui, addiu, or ori 7467 case 'N': // Constant -1 to -65535 7468 case 'O': // A signed 15-bit constant 7469 case 'P': // A constant between 1 go 65535 7470 return true; 7471 case 'R': // An address that can be used in a non-macro load or store 7472 Info.setAllowsMemory(); 7473 return true; 7474 case 'Z': 7475 if (Name[1] == 'C') { // An address usable by ll, and sc. 7476 Info.setAllowsMemory(); 7477 Name++; // Skip over 'Z'. 7478 return true; 7479 } 7480 return false; 7481 } 7482 } 7483 7484 std::string convertConstraint(const char *&Constraint) const override { 7485 std::string R; 7486 switch (*Constraint) { 7487 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7488 if (Constraint[1] == 'C') { 7489 R = std::string("^") + std::string(Constraint, 2); 7490 Constraint++; 7491 return R; 7492 } 7493 break; 7494 } 7495 return TargetInfo::convertConstraint(Constraint); 7496 } 7497 7498 const char *getClobbers() const override { 7499 // In GCC, $1 is not widely used in generated code (it's used only in a few 7500 // specific situations), so there is no real need for users to add it to 7501 // the clobbers list if they want to use it in their inline assembly code. 7502 // 7503 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7504 // code generation, so using it in inline assembly without adding it to the 7505 // clobbers list can cause conflicts between the inline assembly code and 7506 // the surrounding generated code. 7507 // 7508 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7509 // operands, which will conflict with the ".set at" assembler option (which 7510 // we use only for inline assembly, in order to maintain compatibility with 7511 // GCC) and will also conflict with the user's usage of $1. 7512 // 7513 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7514 // register for generated code is to automatically clobber $1 for all inline 7515 // assembly code. 7516 // 7517 // FIXME: We should automatically clobber $1 only for inline assembly code 7518 // which actually uses it. This would allow LLVM to use $1 for inline 7519 // assembly operands if the user's assembly code doesn't use it. 7520 return "~{$1}"; 7521 } 7522 7523 bool handleTargetFeatures(std::vector<std::string> &Features, 7524 DiagnosticsEngine &Diags) override { 7525 IsMips16 = false; 7526 IsMicromips = false; 7527 IsNan2008 = isNaN2008Default(); 7528 IsSingleFloat = false; 7529 FloatABI = HardFloat; 7530 DspRev = NoDSP; 7531 HasFP64 = isFP64Default(); 7532 7533 for (const auto &Feature : Features) { 7534 if (Feature == "+single-float") 7535 IsSingleFloat = true; 7536 else if (Feature == "+soft-float") 7537 FloatABI = SoftFloat; 7538 else if (Feature == "+mips16") 7539 IsMips16 = true; 7540 else if (Feature == "+micromips") 7541 IsMicromips = true; 7542 else if (Feature == "+dsp") 7543 DspRev = std::max(DspRev, DSP1); 7544 else if (Feature == "+dspr2") 7545 DspRev = std::max(DspRev, DSP2); 7546 else if (Feature == "+msa") 7547 HasMSA = true; 7548 else if (Feature == "+fp64") 7549 HasFP64 = true; 7550 else if (Feature == "-fp64") 7551 HasFP64 = false; 7552 else if (Feature == "+nan2008") 7553 IsNan2008 = true; 7554 else if (Feature == "-nan2008") 7555 IsNan2008 = false; 7556 } 7557 7558 setDataLayout(); 7559 7560 return true; 7561 } 7562 7563 int getEHDataRegisterNumber(unsigned RegNo) const override { 7564 if (RegNo == 0) return 4; 7565 if (RegNo == 1) return 5; 7566 return -1; 7567 } 7568 7569 bool isCLZForZeroUndef() const override { return false; } 7570 7571 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7572 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7573 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7574 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7575 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7576 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7577 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7578 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7579 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7580 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7581 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7582 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7583 {{"ra"}, "$31"}}; 7584 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7585 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7586 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7587 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7588 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7589 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7590 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7591 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7592 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7593 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7594 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7595 {{"ra"}, "$31"}}; 7596 if (ABI == "o32") 7597 return llvm::makeArrayRef(O32RegAliases); 7598 return llvm::makeArrayRef(NewABIRegAliases); 7599 } 7600 7601 bool hasInt128Type() const override { 7602 return ABI == "n32" || ABI == "n64"; 7603 } 7604 7605 bool validateTarget(DiagnosticsEngine &Diags) const override { 7606 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7607 // this yet. It's better to fail here than on the backend assertion. 7608 if (processorSupportsGPR64() && ABI == "o32") { 7609 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7610 return false; 7611 } 7612 7613 // 64-bit ABI's require 64-bit CPU's. 7614 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 7615 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7616 return false; 7617 } 7618 7619 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 7620 // can't handle this yet. It's better to fail here than on the 7621 // backend assertion. 7622 if ((getTriple().getArch() == llvm::Triple::mips64 || 7623 getTriple().getArch() == llvm::Triple::mips64el) && 7624 ABI == "o32") { 7625 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7626 << ABI << getTriple().str(); 7627 return false; 7628 } 7629 7630 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 7631 // can't handle this yet. It's better to fail here than on the 7632 // backend assertion. 7633 if ((getTriple().getArch() == llvm::Triple::mips || 7634 getTriple().getArch() == llvm::Triple::mipsel) && 7635 (ABI == "n32" || ABI == "n64")) { 7636 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7637 << ABI << getTriple().str(); 7638 return false; 7639 } 7640 7641 return true; 7642 } 7643 }; 7644 7645 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7646 #define BUILTIN(ID, TYPE, ATTRS) \ 7647 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7648 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7649 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7650 #include "clang/Basic/BuiltinsMips.def" 7651 }; 7652 7653 class PNaClTargetInfo : public TargetInfo { 7654 public: 7655 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7656 : TargetInfo(Triple) { 7657 BigEndian = false; 7658 this->LongAlign = 32; 7659 this->LongWidth = 32; 7660 this->PointerAlign = 32; 7661 this->PointerWidth = 32; 7662 this->IntMaxType = TargetInfo::SignedLongLong; 7663 this->Int64Type = TargetInfo::SignedLongLong; 7664 this->DoubleAlign = 64; 7665 this->LongDoubleWidth = 64; 7666 this->LongDoubleAlign = 64; 7667 this->SizeType = TargetInfo::UnsignedInt; 7668 this->PtrDiffType = TargetInfo::SignedInt; 7669 this->IntPtrType = TargetInfo::SignedInt; 7670 this->RegParmMax = 0; // Disallow regparm 7671 } 7672 7673 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7674 Builder.defineMacro("__le32__"); 7675 Builder.defineMacro("__pnacl__"); 7676 } 7677 void getTargetDefines(const LangOptions &Opts, 7678 MacroBuilder &Builder) const override { 7679 getArchDefines(Opts, Builder); 7680 } 7681 bool hasFeature(StringRef Feature) const override { 7682 return Feature == "pnacl"; 7683 } 7684 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7685 BuiltinVaListKind getBuiltinVaListKind() const override { 7686 return TargetInfo::PNaClABIBuiltinVaList; 7687 } 7688 ArrayRef<const char *> getGCCRegNames() const override; 7689 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7690 bool validateAsmConstraint(const char *&Name, 7691 TargetInfo::ConstraintInfo &Info) const override { 7692 return false; 7693 } 7694 7695 const char *getClobbers() const override { 7696 return ""; 7697 } 7698 }; 7699 7700 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7701 return None; 7702 } 7703 7704 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7705 return None; 7706 } 7707 7708 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7709 class NaClMips32TargetInfo : public MipsTargetInfo { 7710 public: 7711 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7712 : MipsTargetInfo(Triple, Opts) {} 7713 7714 BuiltinVaListKind getBuiltinVaListKind() const override { 7715 return TargetInfo::PNaClABIBuiltinVaList; 7716 } 7717 }; 7718 7719 class Le64TargetInfo : public TargetInfo { 7720 static const Builtin::Info BuiltinInfo[]; 7721 7722 public: 7723 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7724 : TargetInfo(Triple) { 7725 BigEndian = false; 7726 NoAsmVariants = true; 7727 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7728 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7729 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7730 } 7731 7732 void getTargetDefines(const LangOptions &Opts, 7733 MacroBuilder &Builder) const override { 7734 DefineStd(Builder, "unix", Opts); 7735 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7736 Builder.defineMacro("__ELF__"); 7737 } 7738 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7739 return llvm::makeArrayRef(BuiltinInfo, 7740 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7741 } 7742 BuiltinVaListKind getBuiltinVaListKind() const override { 7743 return TargetInfo::PNaClABIBuiltinVaList; 7744 } 7745 const char *getClobbers() const override { return ""; } 7746 ArrayRef<const char *> getGCCRegNames() const override { 7747 return None; 7748 } 7749 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7750 return None; 7751 } 7752 bool validateAsmConstraint(const char *&Name, 7753 TargetInfo::ConstraintInfo &Info) const override { 7754 return false; 7755 } 7756 7757 bool hasProtectedVisibility() const override { return false; } 7758 }; 7759 7760 class WebAssemblyTargetInfo : public TargetInfo { 7761 static const Builtin::Info BuiltinInfo[]; 7762 7763 enum SIMDEnum { 7764 NoSIMD, 7765 SIMD128, 7766 } SIMDLevel; 7767 7768 public: 7769 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7770 : TargetInfo(T), SIMDLevel(NoSIMD) { 7771 BigEndian = false; 7772 NoAsmVariants = true; 7773 SuitableAlign = 128; 7774 LargeArrayMinWidth = 128; 7775 LargeArrayAlign = 128; 7776 SimdDefaultAlign = 128; 7777 SigAtomicType = SignedLong; 7778 LongDoubleWidth = LongDoubleAlign = 128; 7779 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7780 } 7781 7782 protected: 7783 void getTargetDefines(const LangOptions &Opts, 7784 MacroBuilder &Builder) const override { 7785 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7786 if (SIMDLevel >= SIMD128) 7787 Builder.defineMacro("__wasm_simd128__"); 7788 } 7789 7790 private: 7791 bool 7792 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7793 StringRef CPU, 7794 const std::vector<std::string> &FeaturesVec) const override { 7795 if (CPU == "bleeding-edge") 7796 Features["simd128"] = true; 7797 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7798 } 7799 bool hasFeature(StringRef Feature) const final { 7800 return llvm::StringSwitch<bool>(Feature) 7801 .Case("simd128", SIMDLevel >= SIMD128) 7802 .Default(false); 7803 } 7804 bool handleTargetFeatures(std::vector<std::string> &Features, 7805 DiagnosticsEngine &Diags) final { 7806 for (const auto &Feature : Features) { 7807 if (Feature == "+simd128") { 7808 SIMDLevel = std::max(SIMDLevel, SIMD128); 7809 continue; 7810 } 7811 if (Feature == "-simd128") { 7812 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7813 continue; 7814 } 7815 7816 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7817 << "-target-feature"; 7818 return false; 7819 } 7820 return true; 7821 } 7822 bool setCPU(const std::string &Name) final { 7823 return llvm::StringSwitch<bool>(Name) 7824 .Case("mvp", true) 7825 .Case("bleeding-edge", true) 7826 .Case("generic", true) 7827 .Default(false); 7828 } 7829 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7830 return llvm::makeArrayRef(BuiltinInfo, 7831 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7832 } 7833 BuiltinVaListKind getBuiltinVaListKind() const final { 7834 return VoidPtrBuiltinVaList; 7835 } 7836 ArrayRef<const char *> getGCCRegNames() const final { 7837 return None; 7838 } 7839 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7840 return None; 7841 } 7842 bool 7843 validateAsmConstraint(const char *&Name, 7844 TargetInfo::ConstraintInfo &Info) const final { 7845 return false; 7846 } 7847 const char *getClobbers() const final { return ""; } 7848 bool isCLZForZeroUndef() const final { return false; } 7849 bool hasInt128Type() const final { return true; } 7850 IntType getIntTypeByWidth(unsigned BitWidth, 7851 bool IsSigned) const final { 7852 // WebAssembly prefers long long for explicitly 64-bit integers. 7853 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7854 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7855 } 7856 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7857 bool IsSigned) const final { 7858 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7859 return BitWidth == 64 7860 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7861 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7862 } 7863 }; 7864 7865 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7866 #define BUILTIN(ID, TYPE, ATTRS) \ 7867 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7868 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7869 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7870 #include "clang/Basic/BuiltinsWebAssembly.def" 7871 }; 7872 7873 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7874 public: 7875 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 7876 const TargetOptions &Opts) 7877 : WebAssemblyTargetInfo(T, Opts) { 7878 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7879 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7880 } 7881 7882 protected: 7883 void getTargetDefines(const LangOptions &Opts, 7884 MacroBuilder &Builder) const override { 7885 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7886 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7887 } 7888 }; 7889 7890 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7891 public: 7892 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 7893 const TargetOptions &Opts) 7894 : WebAssemblyTargetInfo(T, Opts) { 7895 LongAlign = LongWidth = 64; 7896 PointerAlign = PointerWidth = 64; 7897 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7898 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7899 } 7900 7901 protected: 7902 void getTargetDefines(const LangOptions &Opts, 7903 MacroBuilder &Builder) const override { 7904 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7905 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7906 } 7907 }; 7908 7909 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7910 #define BUILTIN(ID, TYPE, ATTRS) \ 7911 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7912 #include "clang/Basic/BuiltinsLe64.def" 7913 }; 7914 7915 static const unsigned SPIRAddrSpaceMap[] = { 7916 1, // opencl_global 7917 3, // opencl_local 7918 2, // opencl_constant 7919 4, // opencl_generic 7920 0, // cuda_device 7921 0, // cuda_constant 7922 0 // cuda_shared 7923 }; 7924 class SPIRTargetInfo : public TargetInfo { 7925 public: 7926 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7927 : TargetInfo(Triple) { 7928 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7929 "SPIR target must use unknown OS"); 7930 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7931 "SPIR target must use unknown environment type"); 7932 BigEndian = false; 7933 TLSSupported = false; 7934 LongWidth = LongAlign = 64; 7935 AddrSpaceMap = &SPIRAddrSpaceMap; 7936 UseAddrSpaceMapMangling = true; 7937 // Define available target features 7938 // These must be defined in sorted order! 7939 NoAsmVariants = true; 7940 } 7941 void getTargetDefines(const LangOptions &Opts, 7942 MacroBuilder &Builder) const override { 7943 DefineStd(Builder, "SPIR", Opts); 7944 } 7945 bool hasFeature(StringRef Feature) const override { 7946 return Feature == "spir"; 7947 } 7948 7949 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7950 const char *getClobbers() const override { return ""; } 7951 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7952 bool validateAsmConstraint(const char *&Name, 7953 TargetInfo::ConstraintInfo &info) const override { 7954 return true; 7955 } 7956 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7957 return None; 7958 } 7959 BuiltinVaListKind getBuiltinVaListKind() const override { 7960 return TargetInfo::VoidPtrBuiltinVaList; 7961 } 7962 7963 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7964 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 7965 : CCCR_Warning; 7966 } 7967 7968 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7969 return CC_SpirFunction; 7970 } 7971 7972 void setSupportedOpenCLOpts() override { 7973 // Assume all OpenCL extensions and optional core features are supported 7974 // for SPIR since it is a generic target. 7975 getSupportedOpenCLOpts().setAll(); 7976 } 7977 }; 7978 7979 class SPIR32TargetInfo : public SPIRTargetInfo { 7980 public: 7981 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7982 : SPIRTargetInfo(Triple, Opts) { 7983 PointerWidth = PointerAlign = 32; 7984 SizeType = TargetInfo::UnsignedInt; 7985 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7986 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7987 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7988 } 7989 void getTargetDefines(const LangOptions &Opts, 7990 MacroBuilder &Builder) const override { 7991 DefineStd(Builder, "SPIR32", Opts); 7992 } 7993 }; 7994 7995 class SPIR64TargetInfo : public SPIRTargetInfo { 7996 public: 7997 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7998 : SPIRTargetInfo(Triple, Opts) { 7999 PointerWidth = PointerAlign = 64; 8000 SizeType = TargetInfo::UnsignedLong; 8001 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8002 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8003 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8004 } 8005 void getTargetDefines(const LangOptions &Opts, 8006 MacroBuilder &Builder) const override { 8007 DefineStd(Builder, "SPIR64", Opts); 8008 } 8009 }; 8010 8011 class XCoreTargetInfo : public TargetInfo { 8012 static const Builtin::Info BuiltinInfo[]; 8013 public: 8014 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8015 : TargetInfo(Triple) { 8016 BigEndian = false; 8017 NoAsmVariants = true; 8018 LongLongAlign = 32; 8019 SuitableAlign = 32; 8020 DoubleAlign = LongDoubleAlign = 32; 8021 SizeType = UnsignedInt; 8022 PtrDiffType = SignedInt; 8023 IntPtrType = SignedInt; 8024 WCharType = UnsignedChar; 8025 WIntType = UnsignedInt; 8026 UseZeroLengthBitfieldAlignment = true; 8027 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8028 "-f64:32-a:0:32-n32"); 8029 } 8030 void getTargetDefines(const LangOptions &Opts, 8031 MacroBuilder &Builder) const override { 8032 Builder.defineMacro("__XS1B__"); 8033 } 8034 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8035 return llvm::makeArrayRef(BuiltinInfo, 8036 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8037 } 8038 BuiltinVaListKind getBuiltinVaListKind() const override { 8039 return TargetInfo::VoidPtrBuiltinVaList; 8040 } 8041 const char *getClobbers() const override { 8042 return ""; 8043 } 8044 ArrayRef<const char *> getGCCRegNames() const override { 8045 static const char * const GCCRegNames[] = { 8046 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8047 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8048 }; 8049 return llvm::makeArrayRef(GCCRegNames); 8050 } 8051 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8052 return None; 8053 } 8054 bool validateAsmConstraint(const char *&Name, 8055 TargetInfo::ConstraintInfo &Info) const override { 8056 return false; 8057 } 8058 int getEHDataRegisterNumber(unsigned RegNo) const override { 8059 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8060 return (RegNo < 2)? RegNo : -1; 8061 } 8062 bool allowsLargerPreferedTypeAlignment() const override { 8063 return false; 8064 } 8065 }; 8066 8067 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8068 #define BUILTIN(ID, TYPE, ATTRS) \ 8069 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8070 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8071 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8072 #include "clang/Basic/BuiltinsXCore.def" 8073 }; 8074 8075 // x86_32 Android target 8076 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8077 public: 8078 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8079 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8080 SuitableAlign = 32; 8081 LongDoubleWidth = 64; 8082 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 8083 } 8084 }; 8085 8086 // x86_64 Android target 8087 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8088 public: 8089 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8090 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8091 LongDoubleFormat = &llvm::APFloat::IEEEquad; 8092 } 8093 8094 bool useFloat128ManglingForLongDouble() const override { 8095 return true; 8096 } 8097 }; 8098 8099 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8100 class RenderScript32TargetInfo : public ARMleTargetInfo { 8101 public: 8102 RenderScript32TargetInfo(const llvm::Triple &Triple, 8103 const TargetOptions &Opts) 8104 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8105 Triple.getOSName(), 8106 Triple.getEnvironmentName()), 8107 Opts) { 8108 LongWidth = LongAlign = 64; 8109 } 8110 void getTargetDefines(const LangOptions &Opts, 8111 MacroBuilder &Builder) const override { 8112 Builder.defineMacro("__RENDERSCRIPT__"); 8113 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8114 } 8115 }; 8116 8117 // 64-bit RenderScript is aarch64 8118 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8119 public: 8120 RenderScript64TargetInfo(const llvm::Triple &Triple, 8121 const TargetOptions &Opts) 8122 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8123 Triple.getOSName(), 8124 Triple.getEnvironmentName()), 8125 Opts) {} 8126 8127 void getTargetDefines(const LangOptions &Opts, 8128 MacroBuilder &Builder) const override { 8129 Builder.defineMacro("__RENDERSCRIPT__"); 8130 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8131 } 8132 }; 8133 8134 } // end anonymous namespace 8135 8136 //===----------------------------------------------------------------------===// 8137 // Driver code 8138 //===----------------------------------------------------------------------===// 8139 8140 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8141 const TargetOptions &Opts) { 8142 llvm::Triple::OSType os = Triple.getOS(); 8143 8144 switch (Triple.getArch()) { 8145 default: 8146 return nullptr; 8147 8148 case llvm::Triple::xcore: 8149 return new XCoreTargetInfo(Triple, Opts); 8150 8151 case llvm::Triple::hexagon: 8152 return new HexagonTargetInfo(Triple, Opts); 8153 8154 case llvm::Triple::lanai: 8155 return new LanaiTargetInfo(Triple, Opts); 8156 8157 case llvm::Triple::aarch64: 8158 if (Triple.isOSDarwin()) 8159 return new DarwinAArch64TargetInfo(Triple, Opts); 8160 8161 switch (os) { 8162 case llvm::Triple::CloudABI: 8163 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8164 case llvm::Triple::FreeBSD: 8165 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8166 case llvm::Triple::Linux: 8167 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8168 case llvm::Triple::NetBSD: 8169 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8170 default: 8171 return new AArch64leTargetInfo(Triple, Opts); 8172 } 8173 8174 case llvm::Triple::aarch64_be: 8175 switch (os) { 8176 case llvm::Triple::FreeBSD: 8177 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8178 case llvm::Triple::Linux: 8179 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8180 case llvm::Triple::NetBSD: 8181 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8182 default: 8183 return new AArch64beTargetInfo(Triple, Opts); 8184 } 8185 8186 case llvm::Triple::arm: 8187 case llvm::Triple::thumb: 8188 if (Triple.isOSBinFormatMachO()) 8189 return new DarwinARMTargetInfo(Triple, Opts); 8190 8191 switch (os) { 8192 case llvm::Triple::Linux: 8193 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8194 case llvm::Triple::FreeBSD: 8195 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8196 case llvm::Triple::NetBSD: 8197 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8198 case llvm::Triple::OpenBSD: 8199 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8200 case llvm::Triple::Bitrig: 8201 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8202 case llvm::Triple::RTEMS: 8203 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8204 case llvm::Triple::NaCl: 8205 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8206 case llvm::Triple::Win32: 8207 switch (Triple.getEnvironment()) { 8208 case llvm::Triple::Cygnus: 8209 return new CygwinARMTargetInfo(Triple, Opts); 8210 case llvm::Triple::GNU: 8211 return new MinGWARMTargetInfo(Triple, Opts); 8212 case llvm::Triple::Itanium: 8213 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8214 case llvm::Triple::MSVC: 8215 default: // Assume MSVC for unknown environments 8216 return new MicrosoftARMleTargetInfo(Triple, Opts); 8217 } 8218 default: 8219 return new ARMleTargetInfo(Triple, Opts); 8220 } 8221 8222 case llvm::Triple::armeb: 8223 case llvm::Triple::thumbeb: 8224 if (Triple.isOSDarwin()) 8225 return new DarwinARMTargetInfo(Triple, Opts); 8226 8227 switch (os) { 8228 case llvm::Triple::Linux: 8229 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8230 case llvm::Triple::FreeBSD: 8231 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8232 case llvm::Triple::NetBSD: 8233 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8234 case llvm::Triple::OpenBSD: 8235 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8236 case llvm::Triple::Bitrig: 8237 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8238 case llvm::Triple::RTEMS: 8239 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8240 case llvm::Triple::NaCl: 8241 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8242 default: 8243 return new ARMbeTargetInfo(Triple, Opts); 8244 } 8245 8246 case llvm::Triple::bpfeb: 8247 case llvm::Triple::bpfel: 8248 return new BPFTargetInfo(Triple, Opts); 8249 8250 case llvm::Triple::msp430: 8251 return new MSP430TargetInfo(Triple, Opts); 8252 8253 case llvm::Triple::mips: 8254 switch (os) { 8255 case llvm::Triple::Linux: 8256 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8257 case llvm::Triple::RTEMS: 8258 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8259 case llvm::Triple::FreeBSD: 8260 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8261 case llvm::Triple::NetBSD: 8262 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8263 default: 8264 return new MipsTargetInfo(Triple, Opts); 8265 } 8266 8267 case llvm::Triple::mipsel: 8268 switch (os) { 8269 case llvm::Triple::Linux: 8270 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8271 case llvm::Triple::RTEMS: 8272 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8273 case llvm::Triple::FreeBSD: 8274 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8275 case llvm::Triple::NetBSD: 8276 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8277 case llvm::Triple::NaCl: 8278 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 8279 default: 8280 return new MipsTargetInfo(Triple, Opts); 8281 } 8282 8283 case llvm::Triple::mips64: 8284 switch (os) { 8285 case llvm::Triple::Linux: 8286 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8287 case llvm::Triple::RTEMS: 8288 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8289 case llvm::Triple::FreeBSD: 8290 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8291 case llvm::Triple::NetBSD: 8292 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8293 case llvm::Triple::OpenBSD: 8294 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8295 default: 8296 return new MipsTargetInfo(Triple, Opts); 8297 } 8298 8299 case llvm::Triple::mips64el: 8300 switch (os) { 8301 case llvm::Triple::Linux: 8302 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8303 case llvm::Triple::RTEMS: 8304 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8305 case llvm::Triple::FreeBSD: 8306 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8307 case llvm::Triple::NetBSD: 8308 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8309 case llvm::Triple::OpenBSD: 8310 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8311 default: 8312 return new MipsTargetInfo(Triple, Opts); 8313 } 8314 8315 case llvm::Triple::le32: 8316 switch (os) { 8317 case llvm::Triple::NaCl: 8318 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8319 default: 8320 return nullptr; 8321 } 8322 8323 case llvm::Triple::le64: 8324 return new Le64TargetInfo(Triple, Opts); 8325 8326 case llvm::Triple::ppc: 8327 if (Triple.isOSDarwin()) 8328 return new DarwinPPC32TargetInfo(Triple, Opts); 8329 switch (os) { 8330 case llvm::Triple::Linux: 8331 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8332 case llvm::Triple::FreeBSD: 8333 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8334 case llvm::Triple::NetBSD: 8335 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8336 case llvm::Triple::OpenBSD: 8337 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8338 case llvm::Triple::RTEMS: 8339 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8340 default: 8341 return new PPC32TargetInfo(Triple, Opts); 8342 } 8343 8344 case llvm::Triple::ppc64: 8345 if (Triple.isOSDarwin()) 8346 return new DarwinPPC64TargetInfo(Triple, Opts); 8347 switch (os) { 8348 case llvm::Triple::Linux: 8349 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8350 case llvm::Triple::Lv2: 8351 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8352 case llvm::Triple::FreeBSD: 8353 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8354 case llvm::Triple::NetBSD: 8355 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8356 default: 8357 return new PPC64TargetInfo(Triple, Opts); 8358 } 8359 8360 case llvm::Triple::ppc64le: 8361 switch (os) { 8362 case llvm::Triple::Linux: 8363 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8364 case llvm::Triple::NetBSD: 8365 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8366 default: 8367 return new PPC64TargetInfo(Triple, Opts); 8368 } 8369 8370 case llvm::Triple::nvptx: 8371 return new NVPTX32TargetInfo(Triple, Opts); 8372 case llvm::Triple::nvptx64: 8373 return new NVPTX64TargetInfo(Triple, Opts); 8374 8375 case llvm::Triple::amdgcn: 8376 case llvm::Triple::r600: 8377 return new AMDGPUTargetInfo(Triple, Opts); 8378 8379 case llvm::Triple::sparc: 8380 switch (os) { 8381 case llvm::Triple::Linux: 8382 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8383 case llvm::Triple::Solaris: 8384 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8385 case llvm::Triple::NetBSD: 8386 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8387 case llvm::Triple::OpenBSD: 8388 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8389 case llvm::Triple::RTEMS: 8390 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8391 default: 8392 return new SparcV8TargetInfo(Triple, Opts); 8393 } 8394 8395 // The 'sparcel' architecture copies all the above cases except for Solaris. 8396 case llvm::Triple::sparcel: 8397 switch (os) { 8398 case llvm::Triple::Linux: 8399 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8400 case llvm::Triple::NetBSD: 8401 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8402 case llvm::Triple::OpenBSD: 8403 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8404 case llvm::Triple::RTEMS: 8405 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8406 default: 8407 return new SparcV8elTargetInfo(Triple, Opts); 8408 } 8409 8410 case llvm::Triple::sparcv9: 8411 switch (os) { 8412 case llvm::Triple::Linux: 8413 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8414 case llvm::Triple::Solaris: 8415 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8416 case llvm::Triple::NetBSD: 8417 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8418 case llvm::Triple::OpenBSD: 8419 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8420 case llvm::Triple::FreeBSD: 8421 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8422 default: 8423 return new SparcV9TargetInfo(Triple, Opts); 8424 } 8425 8426 case llvm::Triple::systemz: 8427 switch (os) { 8428 case llvm::Triple::Linux: 8429 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8430 default: 8431 return new SystemZTargetInfo(Triple, Opts); 8432 } 8433 8434 case llvm::Triple::tce: 8435 return new TCETargetInfo(Triple, Opts); 8436 8437 case llvm::Triple::x86: 8438 if (Triple.isOSDarwin()) 8439 return new DarwinI386TargetInfo(Triple, Opts); 8440 8441 switch (os) { 8442 case llvm::Triple::CloudABI: 8443 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8444 case llvm::Triple::Linux: { 8445 switch (Triple.getEnvironment()) { 8446 default: 8447 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8448 case llvm::Triple::Android: 8449 return new AndroidX86_32TargetInfo(Triple, Opts); 8450 } 8451 } 8452 case llvm::Triple::DragonFly: 8453 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8454 case llvm::Triple::NetBSD: 8455 return new NetBSDI386TargetInfo(Triple, Opts); 8456 case llvm::Triple::OpenBSD: 8457 return new OpenBSDI386TargetInfo(Triple, Opts); 8458 case llvm::Triple::Bitrig: 8459 return new BitrigI386TargetInfo(Triple, Opts); 8460 case llvm::Triple::FreeBSD: 8461 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8462 case llvm::Triple::KFreeBSD: 8463 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8464 case llvm::Triple::Minix: 8465 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8466 case llvm::Triple::Solaris: 8467 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8468 case llvm::Triple::Win32: { 8469 switch (Triple.getEnvironment()) { 8470 case llvm::Triple::Cygnus: 8471 return new CygwinX86_32TargetInfo(Triple, Opts); 8472 case llvm::Triple::GNU: 8473 return new MinGWX86_32TargetInfo(Triple, Opts); 8474 case llvm::Triple::Itanium: 8475 case llvm::Triple::MSVC: 8476 default: // Assume MSVC for unknown environments 8477 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8478 } 8479 } 8480 case llvm::Triple::Haiku: 8481 return new HaikuX86_32TargetInfo(Triple, Opts); 8482 case llvm::Triple::RTEMS: 8483 return new RTEMSX86_32TargetInfo(Triple, Opts); 8484 case llvm::Triple::NaCl: 8485 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8486 case llvm::Triple::ELFIAMCU: 8487 return new MCUX86_32TargetInfo(Triple, Opts); 8488 default: 8489 return new X86_32TargetInfo(Triple, Opts); 8490 } 8491 8492 case llvm::Triple::x86_64: 8493 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8494 return new DarwinX86_64TargetInfo(Triple, Opts); 8495 8496 switch (os) { 8497 case llvm::Triple::CloudABI: 8498 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8499 case llvm::Triple::Linux: { 8500 switch (Triple.getEnvironment()) { 8501 default: 8502 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8503 case llvm::Triple::Android: 8504 return new AndroidX86_64TargetInfo(Triple, Opts); 8505 } 8506 } 8507 case llvm::Triple::DragonFly: 8508 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8509 case llvm::Triple::NetBSD: 8510 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8511 case llvm::Triple::OpenBSD: 8512 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8513 case llvm::Triple::Bitrig: 8514 return new BitrigX86_64TargetInfo(Triple, Opts); 8515 case llvm::Triple::FreeBSD: 8516 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8517 case llvm::Triple::KFreeBSD: 8518 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8519 case llvm::Triple::Solaris: 8520 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8521 case llvm::Triple::Win32: { 8522 switch (Triple.getEnvironment()) { 8523 case llvm::Triple::Cygnus: 8524 return new CygwinX86_64TargetInfo(Triple, Opts); 8525 case llvm::Triple::GNU: 8526 return new MinGWX86_64TargetInfo(Triple, Opts); 8527 case llvm::Triple::MSVC: 8528 default: // Assume MSVC for unknown environments 8529 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8530 } 8531 } 8532 case llvm::Triple::Haiku: 8533 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8534 case llvm::Triple::NaCl: 8535 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8536 case llvm::Triple::PS4: 8537 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8538 default: 8539 return new X86_64TargetInfo(Triple, Opts); 8540 } 8541 8542 case llvm::Triple::spir: { 8543 if (Triple.getOS() != llvm::Triple::UnknownOS || 8544 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8545 return nullptr; 8546 return new SPIR32TargetInfo(Triple, Opts); 8547 } 8548 case llvm::Triple::spir64: { 8549 if (Triple.getOS() != llvm::Triple::UnknownOS || 8550 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8551 return nullptr; 8552 return new SPIR64TargetInfo(Triple, Opts); 8553 } 8554 case llvm::Triple::wasm32: 8555 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8556 return nullptr; 8557 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8558 case llvm::Triple::wasm64: 8559 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8560 return nullptr; 8561 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8562 8563 case llvm::Triple::renderscript32: 8564 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 8565 case llvm::Triple::renderscript64: 8566 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 8567 } 8568 } 8569 8570 /// CreateTargetInfo - Return the target info object for the specified target 8571 /// options. 8572 TargetInfo * 8573 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8574 const std::shared_ptr<TargetOptions> &Opts) { 8575 llvm::Triple Triple(Opts->Triple); 8576 8577 // Construct the target 8578 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8579 if (!Target) { 8580 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8581 return nullptr; 8582 } 8583 Target->TargetOpts = Opts; 8584 8585 // Set the target CPU if specified. 8586 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8587 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8588 return nullptr; 8589 } 8590 8591 // Set the target ABI if specified. 8592 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8593 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8594 return nullptr; 8595 } 8596 8597 // Set the fp math unit. 8598 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8599 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8600 return nullptr; 8601 } 8602 8603 // Compute the default target features, we need the target to handle this 8604 // because features may have dependencies on one another. 8605 llvm::StringMap<bool> Features; 8606 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8607 Opts->FeaturesAsWritten)) 8608 return nullptr; 8609 8610 // Add the features to the compile options. 8611 Opts->Features.clear(); 8612 for (const auto &F : Features) 8613 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8614 8615 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8616 return nullptr; 8617 8618 Target->setSupportedOpenCLOpts(); 8619 8620 if (!Target->validateTarget(Diags)) 8621 return nullptr; 8622 8623 return Target.release(); 8624 } 8625