1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringRef.h" 25 #include "llvm/ADT/StringSwitch.h" 26 #include "llvm/ADT/Triple.h" 27 #include "llvm/IR/Type.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include <algorithm> 31 #include <memory> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const override { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 94 // AddressSanitizer doesn't play well with source fortification, which is on 95 // by default on Darwin. 96 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 97 98 if (!Opts.ObjCAutoRefCount) { 99 // __weak is always defined, for use in blocks and with objc pointers. 100 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 101 102 // Darwin defines __strong even in C mode (just to nothing). 103 if (Opts.getGC() != LangOptions::NonGC) 104 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 105 else 106 Builder.defineMacro("__strong", ""); 107 108 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 109 // allow this in C, since one might have block pointers in structs that 110 // are used in pure C code and in Objective-C ARC. 111 Builder.defineMacro("__unsafe_unretained", ""); 112 } 113 114 if (Opts.Static) 115 Builder.defineMacro("__STATIC__"); 116 else 117 Builder.defineMacro("__DYNAMIC__"); 118 119 if (Opts.POSIXThreads) 120 Builder.defineMacro("_REENTRANT"); 121 122 // Get the platform type and version number from the triple. 123 unsigned Maj, Min, Rev; 124 if (Triple.isMacOSX()) { 125 Triple.getMacOSXVersion(Maj, Min, Rev); 126 PlatformName = "macosx"; 127 } else { 128 Triple.getOSVersion(Maj, Min, Rev); 129 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 130 } 131 132 // If -target arch-pc-win32-macho option specified, we're 133 // generating code for Win32 ABI. No need to emit 134 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 135 if (PlatformName == "win32") { 136 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 137 return; 138 } 139 140 // Set the appropriate OS version define. 141 if (Triple.isiOS()) { 142 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 143 char Str[6]; 144 Str[0] = '0' + Maj; 145 Str[1] = '0' + (Min / 10); 146 Str[2] = '0' + (Min % 10); 147 Str[3] = '0' + (Rev / 10); 148 Str[4] = '0' + (Rev % 10); 149 Str[5] = '\0'; 150 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 151 Str); 152 } else if (Triple.isMacOSX()) { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 158 char Str[5]; 159 Str[0] = '0' + (Maj / 10); 160 Str[1] = '0' + (Maj % 10); 161 Str[2] = '0' + std::min(Min, 9U); 162 Str[3] = '0' + std::min(Rev, 9U); 163 Str[4] = '\0'; 164 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 165 } 166 167 // Tell users about the kernel if there is one. 168 if (Triple.isOSDarwin()) 169 Builder.defineMacro("__MACH__"); 170 171 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 172 } 173 174 namespace { 175 template<typename Target> 176 class DarwinTargetInfo : public OSTargetInfo<Target> { 177 protected: 178 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 179 MacroBuilder &Builder) const override { 180 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 181 this->PlatformMinVersion); 182 } 183 184 public: 185 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 186 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 187 this->MCountName = "\01mcount"; 188 } 189 190 std::string isValidSectionSpecifier(StringRef SR) const override { 191 // Let MCSectionMachO validate this. 192 StringRef Segment, Section; 193 unsigned TAA, StubSize; 194 bool HasTAA; 195 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 196 TAA, HasTAA, StubSize); 197 } 198 199 const char *getStaticInitSectionSpecifier() const override { 200 // FIXME: We should return 0 when building kexts. 201 return "__TEXT,__StaticInit,regular,pure_instructions"; 202 } 203 204 /// Darwin does not support protected visibility. Darwin's "default" 205 /// is very similar to ELF's "protected"; Darwin requires a "weak" 206 /// attribute on declarations that can be dynamically replaced. 207 bool hasProtectedVisibility() const override { 208 return false; 209 } 210 }; 211 212 213 // DragonFlyBSD Target 214 template<typename Target> 215 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 216 protected: 217 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 218 MacroBuilder &Builder) const override { 219 // DragonFly defines; list based off of gcc output 220 Builder.defineMacro("__DragonFly__"); 221 Builder.defineMacro("__DragonFly_cc_version", "100001"); 222 Builder.defineMacro("__ELF__"); 223 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 224 Builder.defineMacro("__tune_i386__"); 225 DefineStd(Builder, "unix", Opts); 226 } 227 public: 228 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 229 : OSTargetInfo<Target>(Triple) { 230 this->UserLabelPrefix = ""; 231 232 switch (Triple.getArch()) { 233 default: 234 case llvm::Triple::x86: 235 case llvm::Triple::x86_64: 236 this->MCountName = ".mcount"; 237 break; 238 } 239 } 240 }; 241 242 // FreeBSD Target 243 template<typename Target> 244 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 245 protected: 246 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 247 MacroBuilder &Builder) const override { 248 // FreeBSD defines; list based off of gcc output 249 250 unsigned Release = Triple.getOSMajorVersion(); 251 if (Release == 0U) 252 Release = 8; 253 254 Builder.defineMacro("__FreeBSD__", Twine(Release)); 255 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 256 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 257 DefineStd(Builder, "unix", Opts); 258 Builder.defineMacro("__ELF__"); 259 260 // On FreeBSD, wchar_t contains the number of the code point as 261 // used by the character set of the locale. These character sets are 262 // not necessarily a superset of ASCII. 263 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 264 } 265 public: 266 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 267 this->UserLabelPrefix = ""; 268 269 switch (Triple.getArch()) { 270 default: 271 case llvm::Triple::x86: 272 case llvm::Triple::x86_64: 273 this->MCountName = ".mcount"; 274 break; 275 case llvm::Triple::mips: 276 case llvm::Triple::mipsel: 277 case llvm::Triple::ppc: 278 case llvm::Triple::ppc64: 279 case llvm::Triple::ppc64le: 280 this->MCountName = "_mcount"; 281 break; 282 case llvm::Triple::arm: 283 this->MCountName = "__mcount"; 284 break; 285 } 286 } 287 }; 288 289 // GNU/kFreeBSD Target 290 template<typename Target> 291 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 292 protected: 293 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 294 MacroBuilder &Builder) const override { 295 // GNU/kFreeBSD defines; list based off of gcc output 296 297 DefineStd(Builder, "unix", Opts); 298 Builder.defineMacro("__FreeBSD_kernel__"); 299 Builder.defineMacro("__GLIBC__"); 300 Builder.defineMacro("__ELF__"); 301 if (Opts.POSIXThreads) 302 Builder.defineMacro("_REENTRANT"); 303 if (Opts.CPlusPlus) 304 Builder.defineMacro("_GNU_SOURCE"); 305 } 306 public: 307 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 } 310 }; 311 312 // Minix Target 313 template<typename Target> 314 class MinixTargetInfo : public OSTargetInfo<Target> { 315 protected: 316 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 317 MacroBuilder &Builder) const override { 318 // Minix defines 319 320 Builder.defineMacro("__minix", "3"); 321 Builder.defineMacro("_EM_WSIZE", "4"); 322 Builder.defineMacro("_EM_PSIZE", "4"); 323 Builder.defineMacro("_EM_SSIZE", "2"); 324 Builder.defineMacro("_EM_LSIZE", "4"); 325 Builder.defineMacro("_EM_FSIZE", "4"); 326 Builder.defineMacro("_EM_DSIZE", "8"); 327 Builder.defineMacro("__ELF__"); 328 DefineStd(Builder, "unix", Opts); 329 } 330 public: 331 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 332 this->UserLabelPrefix = ""; 333 } 334 }; 335 336 // Linux target 337 template<typename Target> 338 class LinuxTargetInfo : public OSTargetInfo<Target> { 339 protected: 340 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 341 MacroBuilder &Builder) const override { 342 // Linux defines; list based off of gcc output 343 DefineStd(Builder, "unix", Opts); 344 DefineStd(Builder, "linux", Opts); 345 Builder.defineMacro("__gnu_linux__"); 346 Builder.defineMacro("__ELF__"); 347 if (Triple.getEnvironment() == llvm::Triple::Android) 348 Builder.defineMacro("__ANDROID__", "1"); 349 if (Opts.POSIXThreads) 350 Builder.defineMacro("_REENTRANT"); 351 if (Opts.CPlusPlus) 352 Builder.defineMacro("_GNU_SOURCE"); 353 } 354 public: 355 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 356 this->UserLabelPrefix = ""; 357 this->WIntType = TargetInfo::UnsignedInt; 358 359 switch (Triple.getArch()) { 360 default: 361 break; 362 case llvm::Triple::ppc: 363 case llvm::Triple::ppc64: 364 case llvm::Triple::ppc64le: 365 this->MCountName = "_mcount"; 366 break; 367 } 368 } 369 370 const char *getStaticInitSectionSpecifier() const override { 371 return ".text.startup"; 372 } 373 }; 374 375 // NetBSD Target 376 template<typename Target> 377 class NetBSDTargetInfo : public OSTargetInfo<Target> { 378 protected: 379 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 380 MacroBuilder &Builder) const override { 381 // NetBSD defines; list based off of gcc output 382 Builder.defineMacro("__NetBSD__"); 383 Builder.defineMacro("__unix__"); 384 Builder.defineMacro("__ELF__"); 385 if (Opts.POSIXThreads) 386 Builder.defineMacro("_POSIX_THREADS"); 387 } 388 public: 389 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 390 this->UserLabelPrefix = ""; 391 } 392 }; 393 394 // OpenBSD Target 395 template<typename Target> 396 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 397 protected: 398 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 399 MacroBuilder &Builder) const override { 400 // OpenBSD defines; list based off of gcc output 401 402 Builder.defineMacro("__OpenBSD__"); 403 DefineStd(Builder, "unix", Opts); 404 Builder.defineMacro("__ELF__"); 405 if (Opts.POSIXThreads) 406 Builder.defineMacro("_REENTRANT"); 407 } 408 public: 409 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 410 this->UserLabelPrefix = ""; 411 this->TLSSupported = false; 412 413 switch (Triple.getArch()) { 414 default: 415 case llvm::Triple::x86: 416 case llvm::Triple::x86_64: 417 case llvm::Triple::arm: 418 case llvm::Triple::sparc: 419 this->MCountName = "__mcount"; 420 break; 421 case llvm::Triple::mips64: 422 case llvm::Triple::mips64el: 423 case llvm::Triple::ppc: 424 case llvm::Triple::sparcv9: 425 this->MCountName = "_mcount"; 426 break; 427 } 428 } 429 }; 430 431 // Bitrig Target 432 template<typename Target> 433 class BitrigTargetInfo : public OSTargetInfo<Target> { 434 protected: 435 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 436 MacroBuilder &Builder) const override { 437 // Bitrig defines; list based off of gcc output 438 439 Builder.defineMacro("__Bitrig__"); 440 DefineStd(Builder, "unix", Opts); 441 Builder.defineMacro("__ELF__"); 442 if (Opts.POSIXThreads) 443 Builder.defineMacro("_REENTRANT"); 444 } 445 public: 446 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 447 this->UserLabelPrefix = ""; 448 this->TLSSupported = false; 449 this->MCountName = "__mcount"; 450 } 451 }; 452 453 // PSP Target 454 template<typename Target> 455 class PSPTargetInfo : public OSTargetInfo<Target> { 456 protected: 457 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 458 MacroBuilder &Builder) const override { 459 // PSP defines; list based on the output of the pspdev gcc toolchain. 460 Builder.defineMacro("PSP"); 461 Builder.defineMacro("_PSP"); 462 Builder.defineMacro("__psp__"); 463 Builder.defineMacro("__ELF__"); 464 } 465 public: 466 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 467 this->UserLabelPrefix = ""; 468 } 469 }; 470 471 // PS3 PPU Target 472 template<typename Target> 473 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 474 protected: 475 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 476 MacroBuilder &Builder) const override { 477 // PS3 PPU defines. 478 Builder.defineMacro("__PPC__"); 479 Builder.defineMacro("__PPU__"); 480 Builder.defineMacro("__CELLOS_LV2__"); 481 Builder.defineMacro("__ELF__"); 482 Builder.defineMacro("__LP32__"); 483 Builder.defineMacro("_ARCH_PPC64"); 484 Builder.defineMacro("__powerpc64__"); 485 } 486 public: 487 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 488 this->UserLabelPrefix = ""; 489 this->LongWidth = this->LongAlign = 32; 490 this->PointerWidth = this->PointerAlign = 32; 491 this->IntMaxType = TargetInfo::SignedLongLong; 492 this->UIntMaxType = TargetInfo::UnsignedLongLong; 493 this->Int64Type = TargetInfo::SignedLongLong; 494 this->SizeType = TargetInfo::UnsignedInt; 495 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 496 } 497 }; 498 499 // AuroraUX target 500 template<typename Target> 501 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 502 protected: 503 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 504 MacroBuilder &Builder) const override { 505 DefineStd(Builder, "sun", Opts); 506 DefineStd(Builder, "unix", Opts); 507 Builder.defineMacro("__ELF__"); 508 Builder.defineMacro("__svr4__"); 509 Builder.defineMacro("__SVR4"); 510 } 511 public: 512 AuroraUXTargetInfo(const llvm::Triple &Triple) 513 : OSTargetInfo<Target>(Triple) { 514 this->UserLabelPrefix = ""; 515 this->WCharType = this->SignedLong; 516 // FIXME: WIntType should be SignedLong 517 } 518 }; 519 520 // Solaris target 521 template<typename Target> 522 class SolarisTargetInfo : public OSTargetInfo<Target> { 523 protected: 524 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 525 MacroBuilder &Builder) const override { 526 DefineStd(Builder, "sun", Opts); 527 DefineStd(Builder, "unix", Opts); 528 Builder.defineMacro("__ELF__"); 529 Builder.defineMacro("__svr4__"); 530 Builder.defineMacro("__SVR4"); 531 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 532 // newer, but to 500 for everything else. feature_test.h has a check to 533 // ensure that you are not using C99 with an old version of X/Open or C89 534 // with a new version. 535 if (Opts.C99 || Opts.C11) 536 Builder.defineMacro("_XOPEN_SOURCE", "600"); 537 else 538 Builder.defineMacro("_XOPEN_SOURCE", "500"); 539 if (Opts.CPlusPlus) 540 Builder.defineMacro("__C99FEATURES__"); 541 Builder.defineMacro("_LARGEFILE_SOURCE"); 542 Builder.defineMacro("_LARGEFILE64_SOURCE"); 543 Builder.defineMacro("__EXTENSIONS__"); 544 Builder.defineMacro("_REENTRANT"); 545 } 546 public: 547 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 548 this->UserLabelPrefix = ""; 549 this->WCharType = this->SignedInt; 550 // FIXME: WIntType should be SignedLong 551 } 552 }; 553 554 // Windows target 555 template<typename Target> 556 class WindowsTargetInfo : public OSTargetInfo<Target> { 557 protected: 558 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 559 MacroBuilder &Builder) const override { 560 Builder.defineMacro("_WIN32"); 561 } 562 void getVisualStudioDefines(const LangOptions &Opts, 563 MacroBuilder &Builder) const { 564 if (Opts.CPlusPlus) { 565 if (Opts.RTTI) 566 Builder.defineMacro("_CPPRTTI"); 567 568 if (Opts.Exceptions) 569 Builder.defineMacro("_CPPUNWIND"); 570 } 571 572 if (!Opts.CharIsSigned) 573 Builder.defineMacro("_CHAR_UNSIGNED"); 574 575 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 576 // but it works for now. 577 if (Opts.POSIXThreads) 578 Builder.defineMacro("_MT"); 579 580 if (Opts.MSCVersion != 0) 581 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 582 583 if (Opts.MicrosoftExt) { 584 Builder.defineMacro("_MSC_EXTENSIONS"); 585 586 if (Opts.CPlusPlus11) { 587 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 588 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 589 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 590 } 591 } 592 593 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 594 } 595 596 public: 597 WindowsTargetInfo(const llvm::Triple &Triple) 598 : OSTargetInfo<Target>(Triple) {} 599 }; 600 601 template <typename Target> 602 class NaClTargetInfo : public OSTargetInfo<Target> { 603 protected: 604 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 605 MacroBuilder &Builder) const override { 606 if (Opts.POSIXThreads) 607 Builder.defineMacro("_REENTRANT"); 608 if (Opts.CPlusPlus) 609 Builder.defineMacro("_GNU_SOURCE"); 610 611 DefineStd(Builder, "unix", Opts); 612 Builder.defineMacro("__ELF__"); 613 Builder.defineMacro("__native_client__"); 614 } 615 616 public: 617 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 618 this->UserLabelPrefix = ""; 619 this->LongAlign = 32; 620 this->LongWidth = 32; 621 this->PointerAlign = 32; 622 this->PointerWidth = 32; 623 this->IntMaxType = TargetInfo::SignedLongLong; 624 this->UIntMaxType = TargetInfo::UnsignedLongLong; 625 this->Int64Type = TargetInfo::SignedLongLong; 626 this->DoubleAlign = 64; 627 this->LongDoubleWidth = 64; 628 this->LongDoubleAlign = 64; 629 this->LongLongWidth = 64; 630 this->LongLongAlign = 64; 631 this->SizeType = TargetInfo::UnsignedInt; 632 this->PtrDiffType = TargetInfo::SignedInt; 633 this->IntPtrType = TargetInfo::SignedInt; 634 // RegParmMax is inherited from the underlying architecture 635 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 636 if (Triple.getArch() == llvm::Triple::arm) { 637 this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S128"; 638 } else if (Triple.getArch() == llvm::Triple::x86) { 639 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 640 } else if (Triple.getArch() == llvm::Triple::x86_64) { 641 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 642 } else if (Triple.getArch() == llvm::Triple::mipsel) { 643 // Handled on mips' setDescriptionString. 644 } else { 645 assert(Triple.getArch() == llvm::Triple::le32); 646 this->DescriptionString = "e-p:32:32-i64:64"; 647 } 648 } 649 typename Target::CallingConvCheckResult checkCallingConvention( 650 CallingConv CC) const override { 651 return CC == CC_PnaclCall ? Target::CCCR_OK : 652 Target::checkCallingConvention(CC); 653 } 654 }; 655 } // end anonymous namespace. 656 657 //===----------------------------------------------------------------------===// 658 // Specific target implementations. 659 //===----------------------------------------------------------------------===// 660 661 namespace { 662 // PPC abstract base class 663 class PPCTargetInfo : public TargetInfo { 664 static const Builtin::Info BuiltinInfo[]; 665 static const char * const GCCRegNames[]; 666 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 667 std::string CPU; 668 669 // Target cpu features. 670 bool HasVSX; 671 672 public: 673 PPCTargetInfo(const llvm::Triple &Triple) 674 : TargetInfo(Triple), HasVSX(false) { 675 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 676 LongDoubleWidth = LongDoubleAlign = 128; 677 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 678 } 679 680 /// \brief Flags for architecture specific defines. 681 typedef enum { 682 ArchDefineNone = 0, 683 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 684 ArchDefinePpcgr = 1 << 1, 685 ArchDefinePpcsq = 1 << 2, 686 ArchDefine440 = 1 << 3, 687 ArchDefine603 = 1 << 4, 688 ArchDefine604 = 1 << 5, 689 ArchDefinePwr4 = 1 << 6, 690 ArchDefinePwr5 = 1 << 7, 691 ArchDefinePwr5x = 1 << 8, 692 ArchDefinePwr6 = 1 << 9, 693 ArchDefinePwr6x = 1 << 10, 694 ArchDefinePwr7 = 1 << 11, 695 ArchDefineA2 = 1 << 12, 696 ArchDefineA2q = 1 << 13 697 } ArchDefineTypes; 698 699 // Note: GCC recognizes the following additional cpus: 700 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 701 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 702 // titan, rs64. 703 bool setCPU(const std::string &Name) override { 704 bool CPUKnown = llvm::StringSwitch<bool>(Name) 705 .Case("generic", true) 706 .Case("440", true) 707 .Case("450", true) 708 .Case("601", true) 709 .Case("602", true) 710 .Case("603", true) 711 .Case("603e", true) 712 .Case("603ev", true) 713 .Case("604", true) 714 .Case("604e", true) 715 .Case("620", true) 716 .Case("630", true) 717 .Case("g3", true) 718 .Case("7400", true) 719 .Case("g4", true) 720 .Case("7450", true) 721 .Case("g4+", true) 722 .Case("750", true) 723 .Case("970", true) 724 .Case("g5", true) 725 .Case("a2", true) 726 .Case("a2q", true) 727 .Case("e500mc", true) 728 .Case("e5500", true) 729 .Case("power3", true) 730 .Case("pwr3", true) 731 .Case("power4", true) 732 .Case("pwr4", true) 733 .Case("power5", true) 734 .Case("pwr5", true) 735 .Case("power5x", true) 736 .Case("pwr5x", true) 737 .Case("power6", true) 738 .Case("pwr6", true) 739 .Case("power6x", true) 740 .Case("pwr6x", true) 741 .Case("power7", true) 742 .Case("pwr7", true) 743 .Case("powerpc", true) 744 .Case("ppc", true) 745 .Case("powerpc64", true) 746 .Case("ppc64", true) 747 .Case("powerpc64le", true) 748 .Case("ppc64le", true) 749 .Default(false); 750 751 if (CPUKnown) 752 CPU = Name; 753 754 return CPUKnown; 755 } 756 757 void getTargetBuiltins(const Builtin::Info *&Records, 758 unsigned &NumRecords) const override { 759 Records = BuiltinInfo; 760 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 761 } 762 763 bool isCLZForZeroUndef() const override { return false; } 764 765 void getTargetDefines(const LangOptions &Opts, 766 MacroBuilder &Builder) const override; 767 768 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 769 770 bool handleTargetFeatures(std::vector<std::string> &Features, 771 DiagnosticsEngine &Diags) override; 772 bool hasFeature(StringRef Feature) const override; 773 774 void getGCCRegNames(const char * const *&Names, 775 unsigned &NumNames) const override; 776 void getGCCRegAliases(const GCCRegAlias *&Aliases, 777 unsigned &NumAliases) const override; 778 bool validateAsmConstraint(const char *&Name, 779 TargetInfo::ConstraintInfo &Info) const override { 780 switch (*Name) { 781 default: return false; 782 case 'O': // Zero 783 break; 784 case 'b': // Base register 785 case 'f': // Floating point register 786 Info.setAllowsRegister(); 787 break; 788 // FIXME: The following are added to allow parsing. 789 // I just took a guess at what the actions should be. 790 // Also, is more specific checking needed? I.e. specific registers? 791 case 'd': // Floating point register (containing 64-bit value) 792 case 'v': // Altivec vector register 793 Info.setAllowsRegister(); 794 break; 795 case 'w': 796 switch (Name[1]) { 797 case 'd':// VSX vector register to hold vector double data 798 case 'f':// VSX vector register to hold vector float data 799 case 's':// VSX vector register to hold scalar float data 800 case 'a':// Any VSX register 801 case 'c':// An individual CR bit 802 break; 803 default: 804 return false; 805 } 806 Info.setAllowsRegister(); 807 Name++; // Skip over 'w'. 808 break; 809 case 'h': // `MQ', `CTR', or `LINK' register 810 case 'q': // `MQ' register 811 case 'c': // `CTR' register 812 case 'l': // `LINK' register 813 case 'x': // `CR' register (condition register) number 0 814 case 'y': // `CR' register (condition register) 815 case 'z': // `XER[CA]' carry bit (part of the XER register) 816 Info.setAllowsRegister(); 817 break; 818 case 'I': // Signed 16-bit constant 819 case 'J': // Unsigned 16-bit constant shifted left 16 bits 820 // (use `L' instead for SImode constants) 821 case 'K': // Unsigned 16-bit constant 822 case 'L': // Signed 16-bit constant shifted left 16 bits 823 case 'M': // Constant larger than 31 824 case 'N': // Exact power of 2 825 case 'P': // Constant whose negation is a signed 16-bit constant 826 case 'G': // Floating point constant that can be loaded into a 827 // register with one instruction per word 828 case 'H': // Integer/Floating point constant that can be loaded 829 // into a register using three instructions 830 break; 831 case 'm': // Memory operand. Note that on PowerPC targets, m can 832 // include addresses that update the base register. It 833 // is therefore only safe to use `m' in an asm statement 834 // if that asm statement accesses the operand exactly once. 835 // The asm statement must also use `%U<opno>' as a 836 // placeholder for the "update" flag in the corresponding 837 // load or store instruction. For example: 838 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 839 // is correct but: 840 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 841 // is not. Use es rather than m if you don't want the base 842 // register to be updated. 843 case 'e': 844 if (Name[1] != 's') 845 return false; 846 // es: A "stable" memory operand; that is, one which does not 847 // include any automodification of the base register. Unlike 848 // `m', this constraint can be used in asm statements that 849 // might access the operand several times, or that might not 850 // access it at all. 851 Info.setAllowsMemory(); 852 Name++; // Skip over 'e'. 853 break; 854 case 'Q': // Memory operand that is an offset from a register (it is 855 // usually better to use `m' or `es' in asm statements) 856 case 'Z': // Memory operand that is an indexed or indirect from a 857 // register (it is usually better to use `m' or `es' in 858 // asm statements) 859 Info.setAllowsMemory(); 860 Info.setAllowsRegister(); 861 break; 862 case 'R': // AIX TOC entry 863 case 'a': // Address operand that is an indexed or indirect from a 864 // register (`p' is preferable for asm statements) 865 case 'S': // Constant suitable as a 64-bit mask operand 866 case 'T': // Constant suitable as a 32-bit mask operand 867 case 'U': // System V Release 4 small data area reference 868 case 't': // AND masks that can be performed by two rldic{l, r} 869 // instructions 870 case 'W': // Vector constant that does not require memory 871 case 'j': // Vector constant that is all zeros. 872 break; 873 // End FIXME. 874 } 875 return true; 876 } 877 std::string convertConstraint(const char *&Constraint) const override { 878 std::string R; 879 switch (*Constraint) { 880 case 'e': 881 case 'w': 882 // Two-character constraint; add "^" hint for later parsing. 883 R = std::string("^") + std::string(Constraint, 2); 884 Constraint++; 885 break; 886 default: 887 return TargetInfo::convertConstraint(Constraint); 888 } 889 return R; 890 } 891 const char *getClobbers() const override { 892 return ""; 893 } 894 int getEHDataRegisterNumber(unsigned RegNo) const override { 895 if (RegNo == 0) return 3; 896 if (RegNo == 1) return 4; 897 return -1; 898 } 899 }; 900 901 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 902 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 903 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 904 ALL_LANGUAGES }, 905 #include "clang/Basic/BuiltinsPPC.def" 906 }; 907 908 /// handleTargetFeatures - Perform initialization based on the user 909 /// configured set of features. 910 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 911 DiagnosticsEngine &Diags) { 912 // Remember the maximum enabled sselevel. 913 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 914 // Ignore disabled features. 915 if (Features[i][0] == '-') 916 continue; 917 918 StringRef Feature = StringRef(Features[i]).substr(1); 919 920 if (Feature == "vsx") { 921 HasVSX = true; 922 continue; 923 } 924 925 // TODO: Finish this list and add an assert that we've handled them 926 // all. 927 } 928 929 return true; 930 } 931 932 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 933 /// #defines that are not tied to a specific subtarget. 934 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 935 MacroBuilder &Builder) const { 936 // Target identification. 937 Builder.defineMacro("__ppc__"); 938 Builder.defineMacro("__PPC__"); 939 Builder.defineMacro("_ARCH_PPC"); 940 Builder.defineMacro("__powerpc__"); 941 Builder.defineMacro("__POWERPC__"); 942 if (PointerWidth == 64) { 943 Builder.defineMacro("_ARCH_PPC64"); 944 Builder.defineMacro("__powerpc64__"); 945 Builder.defineMacro("__ppc64__"); 946 Builder.defineMacro("__PPC64__"); 947 } 948 949 // Target properties. 950 if (getTriple().getArch() == llvm::Triple::ppc64le) { 951 Builder.defineMacro("_LITTLE_ENDIAN"); 952 Builder.defineMacro("_CALL_ELF","2"); 953 } else { 954 if (getTriple().getOS() != llvm::Triple::NetBSD && 955 getTriple().getOS() != llvm::Triple::OpenBSD) 956 Builder.defineMacro("_BIG_ENDIAN"); 957 } 958 959 // Subtarget options. 960 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 961 Builder.defineMacro("__REGISTER_PREFIX__", ""); 962 963 // FIXME: Should be controlled by command line option. 964 if (LongDoubleWidth == 128) 965 Builder.defineMacro("__LONG_DOUBLE_128__"); 966 967 if (Opts.AltiVec) { 968 Builder.defineMacro("__VEC__", "10206"); 969 Builder.defineMacro("__ALTIVEC__"); 970 } 971 972 // CPU identification. 973 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 974 .Case("440", ArchDefineName) 975 .Case("450", ArchDefineName | ArchDefine440) 976 .Case("601", ArchDefineName) 977 .Case("602", ArchDefineName | ArchDefinePpcgr) 978 .Case("603", ArchDefineName | ArchDefinePpcgr) 979 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 980 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 981 .Case("604", ArchDefineName | ArchDefinePpcgr) 982 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 983 .Case("620", ArchDefineName | ArchDefinePpcgr) 984 .Case("630", ArchDefineName | ArchDefinePpcgr) 985 .Case("7400", ArchDefineName | ArchDefinePpcgr) 986 .Case("7450", ArchDefineName | ArchDefinePpcgr) 987 .Case("750", ArchDefineName | ArchDefinePpcgr) 988 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 989 | ArchDefinePpcsq) 990 .Case("a2", ArchDefineA2) 991 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 992 .Case("pwr3", ArchDefinePpcgr) 993 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 994 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 995 | ArchDefinePpcsq) 996 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 997 | ArchDefinePpcgr | ArchDefinePpcsq) 998 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 999 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1000 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1001 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1002 | ArchDefinePpcsq) 1003 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1004 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1005 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 1006 .Case("power3", ArchDefinePpcgr) 1007 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1008 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1009 | ArchDefinePpcsq) 1010 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1011 | ArchDefinePpcgr | ArchDefinePpcsq) 1012 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1013 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1014 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1015 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1016 | ArchDefinePpcsq) 1017 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1018 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1019 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 1020 .Default(ArchDefineNone); 1021 1022 if (defs & ArchDefineName) 1023 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1024 if (defs & ArchDefinePpcgr) 1025 Builder.defineMacro("_ARCH_PPCGR"); 1026 if (defs & ArchDefinePpcsq) 1027 Builder.defineMacro("_ARCH_PPCSQ"); 1028 if (defs & ArchDefine440) 1029 Builder.defineMacro("_ARCH_440"); 1030 if (defs & ArchDefine603) 1031 Builder.defineMacro("_ARCH_603"); 1032 if (defs & ArchDefine604) 1033 Builder.defineMacro("_ARCH_604"); 1034 if (defs & ArchDefinePwr4) 1035 Builder.defineMacro("_ARCH_PWR4"); 1036 if (defs & ArchDefinePwr5) 1037 Builder.defineMacro("_ARCH_PWR5"); 1038 if (defs & ArchDefinePwr5x) 1039 Builder.defineMacro("_ARCH_PWR5X"); 1040 if (defs & ArchDefinePwr6) 1041 Builder.defineMacro("_ARCH_PWR6"); 1042 if (defs & ArchDefinePwr6x) 1043 Builder.defineMacro("_ARCH_PWR6X"); 1044 if (defs & ArchDefinePwr7) 1045 Builder.defineMacro("_ARCH_PWR7"); 1046 if (defs & ArchDefineA2) 1047 Builder.defineMacro("_ARCH_A2"); 1048 if (defs & ArchDefineA2q) { 1049 Builder.defineMacro("_ARCH_A2Q"); 1050 Builder.defineMacro("_ARCH_QP"); 1051 } 1052 1053 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1054 Builder.defineMacro("__bg__"); 1055 Builder.defineMacro("__THW_BLUEGENE__"); 1056 Builder.defineMacro("__bgq__"); 1057 Builder.defineMacro("__TOS_BGQ__"); 1058 } 1059 1060 if (HasVSX) 1061 Builder.defineMacro("__VSX__"); 1062 1063 // FIXME: The following are not yet generated here by Clang, but are 1064 // generated by GCC: 1065 // 1066 // _SOFT_FLOAT_ 1067 // __RECIP_PRECISION__ 1068 // __APPLE_ALTIVEC__ 1069 // __RECIP__ 1070 // __RECIPF__ 1071 // __RSQRTE__ 1072 // __RSQRTEF__ 1073 // _SOFT_DOUBLE_ 1074 // __NO_LWSYNC__ 1075 // __HAVE_BSWAP__ 1076 // __LONGDOUBLE128 1077 // __CMODEL_MEDIUM__ 1078 // __CMODEL_LARGE__ 1079 // _CALL_SYSV 1080 // _CALL_DARWIN 1081 // __NO_FPRS__ 1082 } 1083 1084 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1085 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1086 .Case("7400", true) 1087 .Case("g4", true) 1088 .Case("7450", true) 1089 .Case("g4+", true) 1090 .Case("970", true) 1091 .Case("g5", true) 1092 .Case("pwr6", true) 1093 .Case("pwr7", true) 1094 .Case("ppc64", true) 1095 .Case("ppc64le", true) 1096 .Default(false); 1097 1098 Features["qpx"] = (CPU == "a2q"); 1099 } 1100 1101 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1102 return Feature == "powerpc"; 1103 } 1104 1105 1106 const char * const PPCTargetInfo::GCCRegNames[] = { 1107 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1108 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1109 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1110 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1111 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1112 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1113 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1114 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1115 "mq", "lr", "ctr", "ap", 1116 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1117 "xer", 1118 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1119 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1120 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1121 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1122 "vrsave", "vscr", 1123 "spe_acc", "spefscr", 1124 "sfp" 1125 }; 1126 1127 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1128 unsigned &NumNames) const { 1129 Names = GCCRegNames; 1130 NumNames = llvm::array_lengthof(GCCRegNames); 1131 } 1132 1133 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1134 // While some of these aliases do map to different registers 1135 // they still share the same register name. 1136 { { "0" }, "r0" }, 1137 { { "1"}, "r1" }, 1138 { { "2" }, "r2" }, 1139 { { "3" }, "r3" }, 1140 { { "4" }, "r4" }, 1141 { { "5" }, "r5" }, 1142 { { "6" }, "r6" }, 1143 { { "7" }, "r7" }, 1144 { { "8" }, "r8" }, 1145 { { "9" }, "r9" }, 1146 { { "10" }, "r10" }, 1147 { { "11" }, "r11" }, 1148 { { "12" }, "r12" }, 1149 { { "13" }, "r13" }, 1150 { { "14" }, "r14" }, 1151 { { "15" }, "r15" }, 1152 { { "16" }, "r16" }, 1153 { { "17" }, "r17" }, 1154 { { "18" }, "r18" }, 1155 { { "19" }, "r19" }, 1156 { { "20" }, "r20" }, 1157 { { "21" }, "r21" }, 1158 { { "22" }, "r22" }, 1159 { { "23" }, "r23" }, 1160 { { "24" }, "r24" }, 1161 { { "25" }, "r25" }, 1162 { { "26" }, "r26" }, 1163 { { "27" }, "r27" }, 1164 { { "28" }, "r28" }, 1165 { { "29" }, "r29" }, 1166 { { "30" }, "r30" }, 1167 { { "31" }, "r31" }, 1168 { { "fr0" }, "f0" }, 1169 { { "fr1" }, "f1" }, 1170 { { "fr2" }, "f2" }, 1171 { { "fr3" }, "f3" }, 1172 { { "fr4" }, "f4" }, 1173 { { "fr5" }, "f5" }, 1174 { { "fr6" }, "f6" }, 1175 { { "fr7" }, "f7" }, 1176 { { "fr8" }, "f8" }, 1177 { { "fr9" }, "f9" }, 1178 { { "fr10" }, "f10" }, 1179 { { "fr11" }, "f11" }, 1180 { { "fr12" }, "f12" }, 1181 { { "fr13" }, "f13" }, 1182 { { "fr14" }, "f14" }, 1183 { { "fr15" }, "f15" }, 1184 { { "fr16" }, "f16" }, 1185 { { "fr17" }, "f17" }, 1186 { { "fr18" }, "f18" }, 1187 { { "fr19" }, "f19" }, 1188 { { "fr20" }, "f20" }, 1189 { { "fr21" }, "f21" }, 1190 { { "fr22" }, "f22" }, 1191 { { "fr23" }, "f23" }, 1192 { { "fr24" }, "f24" }, 1193 { { "fr25" }, "f25" }, 1194 { { "fr26" }, "f26" }, 1195 { { "fr27" }, "f27" }, 1196 { { "fr28" }, "f28" }, 1197 { { "fr29" }, "f29" }, 1198 { { "fr30" }, "f30" }, 1199 { { "fr31" }, "f31" }, 1200 { { "cc" }, "cr0" }, 1201 }; 1202 1203 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1204 unsigned &NumAliases) const { 1205 Aliases = GCCRegAliases; 1206 NumAliases = llvm::array_lengthof(GCCRegAliases); 1207 } 1208 } // end anonymous namespace. 1209 1210 namespace { 1211 class PPC32TargetInfo : public PPCTargetInfo { 1212 public: 1213 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1214 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1215 1216 switch (getTriple().getOS()) { 1217 case llvm::Triple::Linux: 1218 case llvm::Triple::FreeBSD: 1219 case llvm::Triple::NetBSD: 1220 SizeType = UnsignedInt; 1221 PtrDiffType = SignedInt; 1222 IntPtrType = SignedInt; 1223 break; 1224 default: 1225 break; 1226 } 1227 1228 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1229 LongDoubleWidth = LongDoubleAlign = 64; 1230 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1231 } 1232 1233 // PPC32 supports atomics up to 4 bytes. 1234 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1235 } 1236 1237 BuiltinVaListKind getBuiltinVaListKind() const override { 1238 // This is the ELF definition, and is overridden by the Darwin sub-target 1239 return TargetInfo::PowerABIBuiltinVaList; 1240 } 1241 }; 1242 } // end anonymous namespace. 1243 1244 // Note: ABI differences may eventually require us to have a separate 1245 // TargetInfo for little endian. 1246 namespace { 1247 class PPC64TargetInfo : public PPCTargetInfo { 1248 public: 1249 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1250 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1251 IntMaxType = SignedLong; 1252 UIntMaxType = UnsignedLong; 1253 Int64Type = SignedLong; 1254 1255 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1256 LongDoubleWidth = LongDoubleAlign = 64; 1257 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1258 DescriptionString = "E-m:e-i64:64-n32:64"; 1259 } else { 1260 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1261 DescriptionString = "e-m:e-i64:64-n32:64"; 1262 } else { 1263 DescriptionString = "E-m:e-i64:64-n32:64"; 1264 } 1265 } 1266 1267 // PPC64 supports atomics up to 8 bytes. 1268 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1269 } 1270 BuiltinVaListKind getBuiltinVaListKind() const override { 1271 return TargetInfo::CharPtrBuiltinVaList; 1272 } 1273 }; 1274 } // end anonymous namespace. 1275 1276 1277 namespace { 1278 class DarwinPPC32TargetInfo : 1279 public DarwinTargetInfo<PPC32TargetInfo> { 1280 public: 1281 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1282 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1283 HasAlignMac68kSupport = true; 1284 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1285 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1286 LongLongAlign = 32; 1287 SuitableAlign = 128; 1288 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1289 } 1290 BuiltinVaListKind getBuiltinVaListKind() const override { 1291 return TargetInfo::CharPtrBuiltinVaList; 1292 } 1293 }; 1294 1295 class DarwinPPC64TargetInfo : 1296 public DarwinTargetInfo<PPC64TargetInfo> { 1297 public: 1298 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1299 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1300 HasAlignMac68kSupport = true; 1301 SuitableAlign = 128; 1302 DescriptionString = "E-m:o-i64:64-n32:64"; 1303 } 1304 }; 1305 } // end anonymous namespace. 1306 1307 namespace { 1308 static const unsigned NVPTXAddrSpaceMap[] = { 1309 1, // opencl_global 1310 3, // opencl_local 1311 4, // opencl_constant 1312 1, // cuda_device 1313 4, // cuda_constant 1314 3, // cuda_shared 1315 }; 1316 class NVPTXTargetInfo : public TargetInfo { 1317 static const char * const GCCRegNames[]; 1318 static const Builtin::Info BuiltinInfo[]; 1319 public: 1320 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1321 BigEndian = false; 1322 TLSSupported = false; 1323 LongWidth = LongAlign = 64; 1324 AddrSpaceMap = &NVPTXAddrSpaceMap; 1325 UseAddrSpaceMapMangling = true; 1326 // Define available target features 1327 // These must be defined in sorted order! 1328 NoAsmVariants = true; 1329 } 1330 void getTargetDefines(const LangOptions &Opts, 1331 MacroBuilder &Builder) const override { 1332 Builder.defineMacro("__PTX__"); 1333 Builder.defineMacro("__NVPTX__"); 1334 } 1335 void getTargetBuiltins(const Builtin::Info *&Records, 1336 unsigned &NumRecords) const override { 1337 Records = BuiltinInfo; 1338 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1339 } 1340 bool hasFeature(StringRef Feature) const override { 1341 return Feature == "ptx" || Feature == "nvptx"; 1342 } 1343 1344 void getGCCRegNames(const char * const *&Names, 1345 unsigned &NumNames) const override; 1346 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1347 unsigned &NumAliases) const override { 1348 // No aliases. 1349 Aliases = 0; 1350 NumAliases = 0; 1351 } 1352 bool validateAsmConstraint(const char *&Name, 1353 TargetInfo::ConstraintInfo &Info) const override { 1354 switch (*Name) { 1355 default: return false; 1356 case 'c': 1357 case 'h': 1358 case 'r': 1359 case 'l': 1360 case 'f': 1361 case 'd': 1362 Info.setAllowsRegister(); 1363 return true; 1364 } 1365 } 1366 const char *getClobbers() const override { 1367 // FIXME: Is this really right? 1368 return ""; 1369 } 1370 BuiltinVaListKind getBuiltinVaListKind() const override { 1371 // FIXME: implement 1372 return TargetInfo::CharPtrBuiltinVaList; 1373 } 1374 bool setCPU(const std::string &Name) override { 1375 bool Valid = llvm::StringSwitch<bool>(Name) 1376 .Case("sm_20", true) 1377 .Case("sm_21", true) 1378 .Case("sm_30", true) 1379 .Case("sm_35", true) 1380 .Default(false); 1381 1382 return Valid; 1383 } 1384 }; 1385 1386 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1387 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1388 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1389 ALL_LANGUAGES }, 1390 #include "clang/Basic/BuiltinsNVPTX.def" 1391 }; 1392 1393 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1394 "r0" 1395 }; 1396 1397 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1398 unsigned &NumNames) const { 1399 Names = GCCRegNames; 1400 NumNames = llvm::array_lengthof(GCCRegNames); 1401 } 1402 1403 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1404 public: 1405 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1406 PointerWidth = PointerAlign = 32; 1407 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1408 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1409 } 1410 }; 1411 1412 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1413 public: 1414 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1415 PointerWidth = PointerAlign = 64; 1416 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1417 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1418 } 1419 }; 1420 } 1421 1422 namespace { 1423 1424 static const unsigned R600AddrSpaceMap[] = { 1425 1, // opencl_global 1426 3, // opencl_local 1427 2, // opencl_constant 1428 1, // cuda_device 1429 2, // cuda_constant 1430 3 // cuda_shared 1431 }; 1432 1433 static const char *DescriptionStringR600 = 1434 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1435 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1436 1437 static const char *DescriptionStringR600DoubleOps = 1438 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1439 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1440 1441 static const char *DescriptionStringSI = 1442 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64" 1443 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1444 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1445 1446 class R600TargetInfo : public TargetInfo { 1447 /// \brief The GPU profiles supported by the R600 target. 1448 enum GPUKind { 1449 GK_NONE, 1450 GK_R600, 1451 GK_R600_DOUBLE_OPS, 1452 GK_R700, 1453 GK_R700_DOUBLE_OPS, 1454 GK_EVERGREEN, 1455 GK_EVERGREEN_DOUBLE_OPS, 1456 GK_NORTHERN_ISLANDS, 1457 GK_CAYMAN, 1458 GK_SOUTHERN_ISLANDS, 1459 GK_SEA_ISLANDS 1460 } GPU; 1461 1462 public: 1463 R600TargetInfo(const llvm::Triple &Triple) 1464 : TargetInfo(Triple), GPU(GK_R600) { 1465 DescriptionString = DescriptionStringR600; 1466 AddrSpaceMap = &R600AddrSpaceMap; 1467 UseAddrSpaceMapMangling = true; 1468 } 1469 1470 const char * getClobbers() const override { 1471 return ""; 1472 } 1473 1474 void getGCCRegNames(const char * const *&Names, 1475 unsigned &numNames) const override { 1476 Names = NULL; 1477 numNames = 0; 1478 } 1479 1480 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1481 unsigned &NumAliases) const override { 1482 Aliases = NULL; 1483 NumAliases = 0; 1484 } 1485 1486 bool validateAsmConstraint(const char *&Name, 1487 TargetInfo::ConstraintInfo &info) const override { 1488 return true; 1489 } 1490 1491 void getTargetBuiltins(const Builtin::Info *&Records, 1492 unsigned &NumRecords) const override { 1493 Records = NULL; 1494 NumRecords = 0; 1495 } 1496 1497 1498 void getTargetDefines(const LangOptions &Opts, 1499 MacroBuilder &Builder) const override { 1500 Builder.defineMacro("__R600__"); 1501 } 1502 1503 BuiltinVaListKind getBuiltinVaListKind() const override { 1504 return TargetInfo::CharPtrBuiltinVaList; 1505 } 1506 1507 bool setCPU(const std::string &Name) override { 1508 GPU = llvm::StringSwitch<GPUKind>(Name) 1509 .Case("r600" , GK_R600) 1510 .Case("rv610", GK_R600) 1511 .Case("rv620", GK_R600) 1512 .Case("rv630", GK_R600) 1513 .Case("rv635", GK_R600) 1514 .Case("rs780", GK_R600) 1515 .Case("rs880", GK_R600) 1516 .Case("rv670", GK_R600_DOUBLE_OPS) 1517 .Case("rv710", GK_R700) 1518 .Case("rv730", GK_R700) 1519 .Case("rv740", GK_R700_DOUBLE_OPS) 1520 .Case("rv770", GK_R700_DOUBLE_OPS) 1521 .Case("palm", GK_EVERGREEN) 1522 .Case("cedar", GK_EVERGREEN) 1523 .Case("sumo", GK_EVERGREEN) 1524 .Case("sumo2", GK_EVERGREEN) 1525 .Case("redwood", GK_EVERGREEN) 1526 .Case("juniper", GK_EVERGREEN) 1527 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1528 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1529 .Case("barts", GK_NORTHERN_ISLANDS) 1530 .Case("turks", GK_NORTHERN_ISLANDS) 1531 .Case("caicos", GK_NORTHERN_ISLANDS) 1532 .Case("cayman", GK_CAYMAN) 1533 .Case("aruba", GK_CAYMAN) 1534 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1535 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1536 .Case("verde", GK_SOUTHERN_ISLANDS) 1537 .Case("oland", GK_SOUTHERN_ISLANDS) 1538 .Case("bonaire", GK_SEA_ISLANDS) 1539 .Case("kabini", GK_SEA_ISLANDS) 1540 .Case("kaveri", GK_SEA_ISLANDS) 1541 .Case("hawaii", GK_SEA_ISLANDS) 1542 .Default(GK_NONE); 1543 1544 if (GPU == GK_NONE) { 1545 return false; 1546 } 1547 1548 // Set the correct data layout 1549 switch (GPU) { 1550 case GK_NONE: 1551 case GK_R600: 1552 case GK_R700: 1553 case GK_EVERGREEN: 1554 case GK_NORTHERN_ISLANDS: 1555 DescriptionString = DescriptionStringR600; 1556 break; 1557 case GK_R600_DOUBLE_OPS: 1558 case GK_R700_DOUBLE_OPS: 1559 case GK_EVERGREEN_DOUBLE_OPS: 1560 case GK_CAYMAN: 1561 DescriptionString = DescriptionStringR600DoubleOps; 1562 break; 1563 case GK_SOUTHERN_ISLANDS: 1564 case GK_SEA_ISLANDS: 1565 DescriptionString = DescriptionStringSI; 1566 break; 1567 } 1568 1569 return true; 1570 } 1571 }; 1572 1573 } // end anonymous namespace 1574 1575 namespace { 1576 // Namespace for x86 abstract base class 1577 const Builtin::Info BuiltinInfo[] = { 1578 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1579 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1580 ALL_LANGUAGES }, 1581 #include "clang/Basic/BuiltinsX86.def" 1582 }; 1583 1584 static const char* const GCCRegNames[] = { 1585 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1586 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1587 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1588 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1589 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1590 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1591 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1592 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1593 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1594 }; 1595 1596 const TargetInfo::AddlRegName AddlRegNames[] = { 1597 { { "al", "ah", "eax", "rax" }, 0 }, 1598 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1599 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1600 { { "dl", "dh", "edx", "rdx" }, 1 }, 1601 { { "esi", "rsi" }, 4 }, 1602 { { "edi", "rdi" }, 5 }, 1603 { { "esp", "rsp" }, 7 }, 1604 { { "ebp", "rbp" }, 6 }, 1605 }; 1606 1607 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1608 // most of the implementation can be shared. 1609 class X86TargetInfo : public TargetInfo { 1610 enum X86SSEEnum { 1611 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1612 } SSELevel; 1613 enum MMX3DNowEnum { 1614 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1615 } MMX3DNowLevel; 1616 enum XOPEnum { 1617 NoXOP, 1618 SSE4A, 1619 FMA4, 1620 XOP 1621 } XOPLevel; 1622 1623 bool HasAES; 1624 bool HasPCLMUL; 1625 bool HasLZCNT; 1626 bool HasRDRND; 1627 bool HasBMI; 1628 bool HasBMI2; 1629 bool HasPOPCNT; 1630 bool HasRTM; 1631 bool HasPRFCHW; 1632 bool HasRDSEED; 1633 bool HasTBM; 1634 bool HasFMA; 1635 bool HasF16C; 1636 bool HasAVX512CD, HasAVX512ER, HasAVX512PF; 1637 bool HasSHA; 1638 bool HasCX16; 1639 1640 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1641 /// 1642 /// Each enumeration represents a particular CPU supported by Clang. These 1643 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1644 enum CPUKind { 1645 CK_Generic, 1646 1647 /// \name i386 1648 /// i386-generation processors. 1649 //@{ 1650 CK_i386, 1651 //@} 1652 1653 /// \name i486 1654 /// i486-generation processors. 1655 //@{ 1656 CK_i486, 1657 CK_WinChipC6, 1658 CK_WinChip2, 1659 CK_C3, 1660 //@} 1661 1662 /// \name i586 1663 /// i586-generation processors, P5 microarchitecture based. 1664 //@{ 1665 CK_i586, 1666 CK_Pentium, 1667 CK_PentiumMMX, 1668 //@} 1669 1670 /// \name i686 1671 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1672 //@{ 1673 CK_i686, 1674 CK_PentiumPro, 1675 CK_Pentium2, 1676 CK_Pentium3, 1677 CK_Pentium3M, 1678 CK_PentiumM, 1679 CK_C3_2, 1680 1681 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1682 /// Clang however has some logic to suport this. 1683 // FIXME: Warn, deprecate, and potentially remove this. 1684 CK_Yonah, 1685 //@} 1686 1687 /// \name Netburst 1688 /// Netburst microarchitecture based processors. 1689 //@{ 1690 CK_Pentium4, 1691 CK_Pentium4M, 1692 CK_Prescott, 1693 CK_Nocona, 1694 //@} 1695 1696 /// \name Core 1697 /// Core microarchitecture based processors. 1698 //@{ 1699 CK_Core2, 1700 1701 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1702 /// codename which GCC no longer accepts as an option to -march, but Clang 1703 /// has some logic for recognizing it. 1704 // FIXME: Warn, deprecate, and potentially remove this. 1705 CK_Penryn, 1706 //@} 1707 1708 /// \name Atom 1709 /// Atom processors 1710 //@{ 1711 CK_Atom, 1712 CK_Silvermont, 1713 //@} 1714 1715 /// \name Nehalem 1716 /// Nehalem microarchitecture based processors. 1717 //@{ 1718 CK_Corei7, 1719 CK_Corei7AVX, 1720 CK_CoreAVXi, 1721 CK_CoreAVX2, 1722 //@} 1723 1724 /// \name Knights Landing 1725 /// Knights Landing processor. 1726 CK_KNL, 1727 1728 /// \name K6 1729 /// K6 architecture processors. 1730 //@{ 1731 CK_K6, 1732 CK_K6_2, 1733 CK_K6_3, 1734 //@} 1735 1736 /// \name K7 1737 /// K7 architecture processors. 1738 //@{ 1739 CK_Athlon, 1740 CK_AthlonThunderbird, 1741 CK_Athlon4, 1742 CK_AthlonXP, 1743 CK_AthlonMP, 1744 //@} 1745 1746 /// \name K8 1747 /// K8 architecture processors. 1748 //@{ 1749 CK_Athlon64, 1750 CK_Athlon64SSE3, 1751 CK_AthlonFX, 1752 CK_K8, 1753 CK_K8SSE3, 1754 CK_Opteron, 1755 CK_OpteronSSE3, 1756 CK_AMDFAM10, 1757 //@} 1758 1759 /// \name Bobcat 1760 /// Bobcat architecture processors. 1761 //@{ 1762 CK_BTVER1, 1763 CK_BTVER2, 1764 //@} 1765 1766 /// \name Bulldozer 1767 /// Bulldozer architecture processors. 1768 //@{ 1769 CK_BDVER1, 1770 CK_BDVER2, 1771 CK_BDVER3, 1772 //@} 1773 1774 /// This specification is deprecated and will be removed in the future. 1775 /// Users should prefer \see CK_K8. 1776 // FIXME: Warn on this when the CPU is set to it. 1777 CK_x86_64, 1778 //@} 1779 1780 /// \name Geode 1781 /// Geode processors. 1782 //@{ 1783 CK_Geode 1784 //@} 1785 } CPU; 1786 1787 enum FPMathKind { 1788 FP_Default, 1789 FP_SSE, 1790 FP_387 1791 } FPMath; 1792 1793 public: 1794 X86TargetInfo(const llvm::Triple &Triple) 1795 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1796 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1797 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1798 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), 1799 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1800 HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic), 1801 FPMath(FP_Default) { 1802 BigEndian = false; 1803 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1804 } 1805 unsigned getFloatEvalMethod() const override { 1806 // X87 evaluates with 80 bits "long double" precision. 1807 return SSELevel == NoSSE ? 2 : 0; 1808 } 1809 void getTargetBuiltins(const Builtin::Info *&Records, 1810 unsigned &NumRecords) const override { 1811 Records = BuiltinInfo; 1812 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1813 } 1814 void getGCCRegNames(const char * const *&Names, 1815 unsigned &NumNames) const override { 1816 Names = GCCRegNames; 1817 NumNames = llvm::array_lengthof(GCCRegNames); 1818 } 1819 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1820 unsigned &NumAliases) const override { 1821 Aliases = 0; 1822 NumAliases = 0; 1823 } 1824 void getGCCAddlRegNames(const AddlRegName *&Names, 1825 unsigned &NumNames) const override { 1826 Names = AddlRegNames; 1827 NumNames = llvm::array_lengthof(AddlRegNames); 1828 } 1829 bool validateAsmConstraint(const char *&Name, 1830 TargetInfo::ConstraintInfo &info) const override; 1831 std::string convertConstraint(const char *&Constraint) const override; 1832 const char *getClobbers() const override { 1833 return "~{dirflag},~{fpsr},~{flags}"; 1834 } 1835 void getTargetDefines(const LangOptions &Opts, 1836 MacroBuilder &Builder) const override; 1837 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1838 bool Enabled); 1839 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1840 bool Enabled); 1841 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1842 bool Enabled); 1843 void setFeatureEnabled(llvm::StringMap<bool> &Features, 1844 StringRef Name, bool Enabled) const override { 1845 setFeatureEnabledImpl(Features, Name, Enabled); 1846 } 1847 // This exists purely to cut down on the number of virtual calls in 1848 // getDefaultFeatures which calls this repeatedly. 1849 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1850 StringRef Name, bool Enabled); 1851 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 1852 bool hasFeature(StringRef Feature) const override; 1853 bool handleTargetFeatures(std::vector<std::string> &Features, 1854 DiagnosticsEngine &Diags) override; 1855 const char* getABI() const override { 1856 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1857 return "avx"; 1858 else if (getTriple().getArch() == llvm::Triple::x86 && 1859 MMX3DNowLevel == NoMMX3DNow) 1860 return "no-mmx"; 1861 return ""; 1862 } 1863 bool setCPU(const std::string &Name) override { 1864 CPU = llvm::StringSwitch<CPUKind>(Name) 1865 .Case("i386", CK_i386) 1866 .Case("i486", CK_i486) 1867 .Case("winchip-c6", CK_WinChipC6) 1868 .Case("winchip2", CK_WinChip2) 1869 .Case("c3", CK_C3) 1870 .Case("i586", CK_i586) 1871 .Case("pentium", CK_Pentium) 1872 .Case("pentium-mmx", CK_PentiumMMX) 1873 .Case("i686", CK_i686) 1874 .Case("pentiumpro", CK_PentiumPro) 1875 .Case("pentium2", CK_Pentium2) 1876 .Case("pentium3", CK_Pentium3) 1877 .Case("pentium3m", CK_Pentium3M) 1878 .Case("pentium-m", CK_PentiumM) 1879 .Case("c3-2", CK_C3_2) 1880 .Case("yonah", CK_Yonah) 1881 .Case("pentium4", CK_Pentium4) 1882 .Case("pentium4m", CK_Pentium4M) 1883 .Case("prescott", CK_Prescott) 1884 .Case("nocona", CK_Nocona) 1885 .Case("core2", CK_Core2) 1886 .Case("penryn", CK_Penryn) 1887 .Case("atom", CK_Atom) 1888 .Case("slm", CK_Silvermont) 1889 .Case("corei7", CK_Corei7) 1890 .Case("corei7-avx", CK_Corei7AVX) 1891 .Case("core-avx-i", CK_CoreAVXi) 1892 .Case("core-avx2", CK_CoreAVX2) 1893 .Case("knl", CK_KNL) 1894 .Case("k6", CK_K6) 1895 .Case("k6-2", CK_K6_2) 1896 .Case("k6-3", CK_K6_3) 1897 .Case("athlon", CK_Athlon) 1898 .Case("athlon-tbird", CK_AthlonThunderbird) 1899 .Case("athlon-4", CK_Athlon4) 1900 .Case("athlon-xp", CK_AthlonXP) 1901 .Case("athlon-mp", CK_AthlonMP) 1902 .Case("athlon64", CK_Athlon64) 1903 .Case("athlon64-sse3", CK_Athlon64SSE3) 1904 .Case("athlon-fx", CK_AthlonFX) 1905 .Case("k8", CK_K8) 1906 .Case("k8-sse3", CK_K8SSE3) 1907 .Case("opteron", CK_Opteron) 1908 .Case("opteron-sse3", CK_OpteronSSE3) 1909 .Case("amdfam10", CK_AMDFAM10) 1910 .Case("btver1", CK_BTVER1) 1911 .Case("btver2", CK_BTVER2) 1912 .Case("bdver1", CK_BDVER1) 1913 .Case("bdver2", CK_BDVER2) 1914 .Case("bdver3", CK_BDVER3) 1915 .Case("x86-64", CK_x86_64) 1916 .Case("geode", CK_Geode) 1917 .Default(CK_Generic); 1918 1919 // Perform any per-CPU checks necessary to determine if this CPU is 1920 // acceptable. 1921 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1922 // invalid without explaining *why*. 1923 switch (CPU) { 1924 case CK_Generic: 1925 // No processor selected! 1926 return false; 1927 1928 case CK_i386: 1929 case CK_i486: 1930 case CK_WinChipC6: 1931 case CK_WinChip2: 1932 case CK_C3: 1933 case CK_i586: 1934 case CK_Pentium: 1935 case CK_PentiumMMX: 1936 case CK_i686: 1937 case CK_PentiumPro: 1938 case CK_Pentium2: 1939 case CK_Pentium3: 1940 case CK_Pentium3M: 1941 case CK_PentiumM: 1942 case CK_Yonah: 1943 case CK_C3_2: 1944 case CK_Pentium4: 1945 case CK_Pentium4M: 1946 case CK_Prescott: 1947 case CK_K6: 1948 case CK_K6_2: 1949 case CK_K6_3: 1950 case CK_Athlon: 1951 case CK_AthlonThunderbird: 1952 case CK_Athlon4: 1953 case CK_AthlonXP: 1954 case CK_AthlonMP: 1955 case CK_Geode: 1956 // Only accept certain architectures when compiling in 32-bit mode. 1957 if (getTriple().getArch() != llvm::Triple::x86) 1958 return false; 1959 1960 // Fallthrough 1961 case CK_Nocona: 1962 case CK_Core2: 1963 case CK_Penryn: 1964 case CK_Atom: 1965 case CK_Silvermont: 1966 case CK_Corei7: 1967 case CK_Corei7AVX: 1968 case CK_CoreAVXi: 1969 case CK_CoreAVX2: 1970 case CK_KNL: 1971 case CK_Athlon64: 1972 case CK_Athlon64SSE3: 1973 case CK_AthlonFX: 1974 case CK_K8: 1975 case CK_K8SSE3: 1976 case CK_Opteron: 1977 case CK_OpteronSSE3: 1978 case CK_AMDFAM10: 1979 case CK_BTVER1: 1980 case CK_BTVER2: 1981 case CK_BDVER1: 1982 case CK_BDVER2: 1983 case CK_BDVER3: 1984 case CK_x86_64: 1985 return true; 1986 } 1987 llvm_unreachable("Unhandled CPU kind"); 1988 } 1989 1990 bool setFPMath(StringRef Name) override; 1991 1992 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 1993 // We accept all non-ARM calling conventions 1994 return (CC == CC_X86ThisCall || 1995 CC == CC_X86FastCall || 1996 CC == CC_X86StdCall || 1997 CC == CC_C || 1998 CC == CC_X86Pascal || 1999 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2000 } 2001 2002 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2003 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2004 } 2005 }; 2006 2007 bool X86TargetInfo::setFPMath(StringRef Name) { 2008 if (Name == "387") { 2009 FPMath = FP_387; 2010 return true; 2011 } 2012 if (Name == "sse") { 2013 FPMath = FP_SSE; 2014 return true; 2015 } 2016 return false; 2017 } 2018 2019 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2020 // FIXME: This *really* should not be here. 2021 2022 // X86_64 always has SSE2. 2023 if (getTriple().getArch() == llvm::Triple::x86_64) 2024 setFeatureEnabledImpl(Features, "sse2", true); 2025 2026 switch (CPU) { 2027 case CK_Generic: 2028 case CK_i386: 2029 case CK_i486: 2030 case CK_i586: 2031 case CK_Pentium: 2032 case CK_i686: 2033 case CK_PentiumPro: 2034 break; 2035 case CK_PentiumMMX: 2036 case CK_Pentium2: 2037 setFeatureEnabledImpl(Features, "mmx", true); 2038 break; 2039 case CK_Pentium3: 2040 case CK_Pentium3M: 2041 setFeatureEnabledImpl(Features, "sse", true); 2042 break; 2043 case CK_PentiumM: 2044 case CK_Pentium4: 2045 case CK_Pentium4M: 2046 case CK_x86_64: 2047 setFeatureEnabledImpl(Features, "sse2", true); 2048 break; 2049 case CK_Yonah: 2050 case CK_Prescott: 2051 case CK_Nocona: 2052 setFeatureEnabledImpl(Features, "sse3", true); 2053 setFeatureEnabledImpl(Features, "cx16", true); 2054 break; 2055 case CK_Core2: 2056 setFeatureEnabledImpl(Features, "ssse3", true); 2057 setFeatureEnabledImpl(Features, "cx16", true); 2058 break; 2059 case CK_Penryn: 2060 setFeatureEnabledImpl(Features, "sse4.1", true); 2061 setFeatureEnabledImpl(Features, "cx16", true); 2062 break; 2063 case CK_Atom: 2064 setFeatureEnabledImpl(Features, "ssse3", true); 2065 setFeatureEnabledImpl(Features, "cx16", true); 2066 break; 2067 case CK_Silvermont: 2068 setFeatureEnabledImpl(Features, "sse4.2", true); 2069 setFeatureEnabledImpl(Features, "aes", true); 2070 setFeatureEnabledImpl(Features, "cx16", true); 2071 setFeatureEnabledImpl(Features, "pclmul", true); 2072 break; 2073 case CK_Corei7: 2074 setFeatureEnabledImpl(Features, "sse4.2", true); 2075 setFeatureEnabledImpl(Features, "cx16", true); 2076 break; 2077 case CK_Corei7AVX: 2078 setFeatureEnabledImpl(Features, "avx", true); 2079 setFeatureEnabledImpl(Features, "aes", true); 2080 setFeatureEnabledImpl(Features, "cx16", true); 2081 setFeatureEnabledImpl(Features, "pclmul", true); 2082 break; 2083 case CK_CoreAVXi: 2084 setFeatureEnabledImpl(Features, "avx", true); 2085 setFeatureEnabledImpl(Features, "aes", true); 2086 setFeatureEnabledImpl(Features, "pclmul", true); 2087 setFeatureEnabledImpl(Features, "rdrnd", true); 2088 setFeatureEnabledImpl(Features, "f16c", true); 2089 break; 2090 case CK_CoreAVX2: 2091 setFeatureEnabledImpl(Features, "avx2", true); 2092 setFeatureEnabledImpl(Features, "aes", true); 2093 setFeatureEnabledImpl(Features, "pclmul", true); 2094 setFeatureEnabledImpl(Features, "lzcnt", true); 2095 setFeatureEnabledImpl(Features, "rdrnd", true); 2096 setFeatureEnabledImpl(Features, "f16c", true); 2097 setFeatureEnabledImpl(Features, "bmi", true); 2098 setFeatureEnabledImpl(Features, "bmi2", true); 2099 setFeatureEnabledImpl(Features, "rtm", true); 2100 setFeatureEnabledImpl(Features, "fma", true); 2101 setFeatureEnabledImpl(Features, "cx16", true); 2102 break; 2103 case CK_KNL: 2104 setFeatureEnabledImpl(Features, "avx512f", true); 2105 setFeatureEnabledImpl(Features, "avx512cd", true); 2106 setFeatureEnabledImpl(Features, "avx512er", true); 2107 setFeatureEnabledImpl(Features, "avx512pf", true); 2108 setFeatureEnabledImpl(Features, "aes", true); 2109 setFeatureEnabledImpl(Features, "pclmul", true); 2110 setFeatureEnabledImpl(Features, "lzcnt", true); 2111 setFeatureEnabledImpl(Features, "rdrnd", true); 2112 setFeatureEnabledImpl(Features, "f16c", true); 2113 setFeatureEnabledImpl(Features, "bmi", true); 2114 setFeatureEnabledImpl(Features, "bmi2", true); 2115 setFeatureEnabledImpl(Features, "rtm", true); 2116 setFeatureEnabledImpl(Features, "fma", true); 2117 break; 2118 case CK_K6: 2119 case CK_WinChipC6: 2120 setFeatureEnabledImpl(Features, "mmx", true); 2121 break; 2122 case CK_K6_2: 2123 case CK_K6_3: 2124 case CK_WinChip2: 2125 case CK_C3: 2126 setFeatureEnabledImpl(Features, "3dnow", true); 2127 break; 2128 case CK_Athlon: 2129 case CK_AthlonThunderbird: 2130 case CK_Geode: 2131 setFeatureEnabledImpl(Features, "3dnowa", true); 2132 break; 2133 case CK_Athlon4: 2134 case CK_AthlonXP: 2135 case CK_AthlonMP: 2136 setFeatureEnabledImpl(Features, "sse", true); 2137 setFeatureEnabledImpl(Features, "3dnowa", true); 2138 break; 2139 case CK_K8: 2140 case CK_Opteron: 2141 case CK_Athlon64: 2142 case CK_AthlonFX: 2143 setFeatureEnabledImpl(Features, "sse2", true); 2144 setFeatureEnabledImpl(Features, "3dnowa", true); 2145 break; 2146 case CK_K8SSE3: 2147 case CK_OpteronSSE3: 2148 case CK_Athlon64SSE3: 2149 setFeatureEnabledImpl(Features, "sse3", true); 2150 setFeatureEnabledImpl(Features, "3dnowa", true); 2151 break; 2152 case CK_AMDFAM10: 2153 setFeatureEnabledImpl(Features, "sse3", true); 2154 setFeatureEnabledImpl(Features, "sse4a", true); 2155 setFeatureEnabledImpl(Features, "3dnowa", true); 2156 setFeatureEnabledImpl(Features, "lzcnt", true); 2157 setFeatureEnabledImpl(Features, "popcnt", true); 2158 break; 2159 case CK_BTVER1: 2160 setFeatureEnabledImpl(Features, "ssse3", true); 2161 setFeatureEnabledImpl(Features, "sse4a", true); 2162 setFeatureEnabledImpl(Features, "cx16", true); 2163 setFeatureEnabledImpl(Features, "lzcnt", true); 2164 setFeatureEnabledImpl(Features, "popcnt", true); 2165 setFeatureEnabledImpl(Features, "prfchw", true); 2166 break; 2167 case CK_BTVER2: 2168 setFeatureEnabledImpl(Features, "avx", true); 2169 setFeatureEnabledImpl(Features, "sse4a", true); 2170 setFeatureEnabledImpl(Features, "lzcnt", true); 2171 setFeatureEnabledImpl(Features, "aes", true); 2172 setFeatureEnabledImpl(Features, "pclmul", true); 2173 setFeatureEnabledImpl(Features, "prfchw", true); 2174 setFeatureEnabledImpl(Features, "bmi", true); 2175 setFeatureEnabledImpl(Features, "f16c", true); 2176 setFeatureEnabledImpl(Features, "cx16", true); 2177 break; 2178 case CK_BDVER1: 2179 setFeatureEnabledImpl(Features, "xop", true); 2180 setFeatureEnabledImpl(Features, "lzcnt", true); 2181 setFeatureEnabledImpl(Features, "aes", true); 2182 setFeatureEnabledImpl(Features, "pclmul", true); 2183 setFeatureEnabledImpl(Features, "prfchw", true); 2184 setFeatureEnabledImpl(Features, "cx16", true); 2185 break; 2186 case CK_BDVER2: 2187 case CK_BDVER3: 2188 setFeatureEnabledImpl(Features, "xop", true); 2189 setFeatureEnabledImpl(Features, "lzcnt", true); 2190 setFeatureEnabledImpl(Features, "aes", true); 2191 setFeatureEnabledImpl(Features, "pclmul", true); 2192 setFeatureEnabledImpl(Features, "prfchw", true); 2193 setFeatureEnabledImpl(Features, "bmi", true); 2194 setFeatureEnabledImpl(Features, "fma", true); 2195 setFeatureEnabledImpl(Features, "f16c", true); 2196 setFeatureEnabledImpl(Features, "tbm", true); 2197 setFeatureEnabledImpl(Features, "cx16", true); 2198 break; 2199 case CK_C3_2: 2200 setFeatureEnabledImpl(Features, "sse", true); 2201 break; 2202 } 2203 } 2204 2205 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2206 X86SSEEnum Level, bool Enabled) { 2207 if (Enabled) { 2208 switch (Level) { 2209 case AVX512F: 2210 Features["avx512f"] = true; 2211 case AVX2: 2212 Features["avx2"] = true; 2213 case AVX: 2214 Features["avx"] = true; 2215 case SSE42: 2216 Features["sse4.2"] = true; 2217 case SSE41: 2218 Features["sse4.1"] = true; 2219 case SSSE3: 2220 Features["ssse3"] = true; 2221 case SSE3: 2222 Features["sse3"] = true; 2223 case SSE2: 2224 Features["sse2"] = true; 2225 case SSE1: 2226 Features["sse"] = true; 2227 case NoSSE: 2228 break; 2229 } 2230 return; 2231 } 2232 2233 switch (Level) { 2234 case NoSSE: 2235 case SSE1: 2236 Features["sse"] = false; 2237 case SSE2: 2238 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2239 Features["sha"] = false; 2240 case SSE3: 2241 Features["sse3"] = false; 2242 setXOPLevel(Features, NoXOP, false); 2243 case SSSE3: 2244 Features["ssse3"] = false; 2245 case SSE41: 2246 Features["sse4.1"] = false; 2247 case SSE42: 2248 Features["sse4.2"] = false; 2249 case AVX: 2250 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2251 setXOPLevel(Features, FMA4, false); 2252 case AVX2: 2253 Features["avx2"] = false; 2254 case AVX512F: 2255 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2256 Features["avx512pf"] = false; 2257 } 2258 } 2259 2260 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2261 MMX3DNowEnum Level, bool Enabled) { 2262 if (Enabled) { 2263 switch (Level) { 2264 case AMD3DNowAthlon: 2265 Features["3dnowa"] = true; 2266 case AMD3DNow: 2267 Features["3dnow"] = true; 2268 case MMX: 2269 Features["mmx"] = true; 2270 case NoMMX3DNow: 2271 break; 2272 } 2273 return; 2274 } 2275 2276 switch (Level) { 2277 case NoMMX3DNow: 2278 case MMX: 2279 Features["mmx"] = false; 2280 case AMD3DNow: 2281 Features["3dnow"] = false; 2282 case AMD3DNowAthlon: 2283 Features["3dnowa"] = false; 2284 } 2285 } 2286 2287 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2288 bool Enabled) { 2289 if (Enabled) { 2290 switch (Level) { 2291 case XOP: 2292 Features["xop"] = true; 2293 case FMA4: 2294 Features["fma4"] = true; 2295 setSSELevel(Features, AVX, true); 2296 case SSE4A: 2297 Features["sse4a"] = true; 2298 setSSELevel(Features, SSE3, true); 2299 case NoXOP: 2300 break; 2301 } 2302 return; 2303 } 2304 2305 switch (Level) { 2306 case NoXOP: 2307 case SSE4A: 2308 Features["sse4a"] = false; 2309 case FMA4: 2310 Features["fma4"] = false; 2311 case XOP: 2312 Features["xop"] = false; 2313 } 2314 } 2315 2316 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2317 StringRef Name, bool Enabled) { 2318 // FIXME: This *really* should not be here. We need some way of translating 2319 // options into llvm subtarget features. 2320 if (Name == "sse4") 2321 Name = "sse4.2"; 2322 2323 Features[Name] = Enabled; 2324 2325 if (Name == "mmx") { 2326 setMMXLevel(Features, MMX, Enabled); 2327 } else if (Name == "sse") { 2328 setSSELevel(Features, SSE1, Enabled); 2329 } else if (Name == "sse2") { 2330 setSSELevel(Features, SSE2, Enabled); 2331 } else if (Name == "sse3") { 2332 setSSELevel(Features, SSE3, Enabled); 2333 } else if (Name == "ssse3") { 2334 setSSELevel(Features, SSSE3, Enabled); 2335 } else if (Name == "sse4.2") { 2336 setSSELevel(Features, SSE42, Enabled); 2337 } else if (Name == "sse4.1") { 2338 setSSELevel(Features, SSE41, Enabled); 2339 } else if (Name == "3dnow") { 2340 setMMXLevel(Features, AMD3DNow, Enabled); 2341 } else if (Name == "3dnowa") { 2342 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2343 } else if (Name == "aes") { 2344 if (Enabled) 2345 setSSELevel(Features, SSE2, Enabled); 2346 } else if (Name == "pclmul") { 2347 if (Enabled) 2348 setSSELevel(Features, SSE2, Enabled); 2349 } else if (Name == "avx") { 2350 setSSELevel(Features, AVX, Enabled); 2351 } else if (Name == "avx2") { 2352 setSSELevel(Features, AVX2, Enabled); 2353 } else if (Name == "avx512f") { 2354 setSSELevel(Features, AVX512F, Enabled); 2355 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") { 2356 if (Enabled) 2357 setSSELevel(Features, AVX512F, Enabled); 2358 } else if (Name == "fma") { 2359 if (Enabled) 2360 setSSELevel(Features, AVX, Enabled); 2361 } else if (Name == "fma4") { 2362 setXOPLevel(Features, FMA4, Enabled); 2363 } else if (Name == "xop") { 2364 setXOPLevel(Features, XOP, Enabled); 2365 } else if (Name == "sse4a") { 2366 setXOPLevel(Features, SSE4A, Enabled); 2367 } else if (Name == "f16c") { 2368 if (Enabled) 2369 setSSELevel(Features, AVX, Enabled); 2370 } else if (Name == "sha") { 2371 if (Enabled) 2372 setSSELevel(Features, SSE2, Enabled); 2373 } 2374 } 2375 2376 /// handleTargetFeatures - Perform initialization based on the user 2377 /// configured set of features. 2378 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2379 DiagnosticsEngine &Diags) { 2380 // Remember the maximum enabled sselevel. 2381 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2382 // Ignore disabled features. 2383 if (Features[i][0] == '-') 2384 continue; 2385 2386 StringRef Feature = StringRef(Features[i]).substr(1); 2387 2388 if (Feature == "aes") { 2389 HasAES = true; 2390 continue; 2391 } 2392 2393 if (Feature == "pclmul") { 2394 HasPCLMUL = true; 2395 continue; 2396 } 2397 2398 if (Feature == "lzcnt") { 2399 HasLZCNT = true; 2400 continue; 2401 } 2402 2403 if (Feature == "rdrnd") { 2404 HasRDRND = true; 2405 continue; 2406 } 2407 2408 if (Feature == "bmi") { 2409 HasBMI = true; 2410 continue; 2411 } 2412 2413 if (Feature == "bmi2") { 2414 HasBMI2 = true; 2415 continue; 2416 } 2417 2418 if (Feature == "popcnt") { 2419 HasPOPCNT = true; 2420 continue; 2421 } 2422 2423 if (Feature == "rtm") { 2424 HasRTM = true; 2425 continue; 2426 } 2427 2428 if (Feature == "prfchw") { 2429 HasPRFCHW = true; 2430 continue; 2431 } 2432 2433 if (Feature == "rdseed") { 2434 HasRDSEED = true; 2435 continue; 2436 } 2437 2438 if (Feature == "tbm") { 2439 HasTBM = true; 2440 continue; 2441 } 2442 2443 if (Feature == "fma") { 2444 HasFMA = true; 2445 continue; 2446 } 2447 2448 if (Feature == "f16c") { 2449 HasF16C = true; 2450 continue; 2451 } 2452 2453 if (Feature == "avx512cd") { 2454 HasAVX512CD = true; 2455 continue; 2456 } 2457 2458 if (Feature == "avx512er") { 2459 HasAVX512ER = true; 2460 continue; 2461 } 2462 2463 if (Feature == "avx512pf") { 2464 HasAVX512PF = true; 2465 continue; 2466 } 2467 2468 if (Feature == "sha") { 2469 HasSHA = true; 2470 continue; 2471 } 2472 2473 if (Feature == "cx16") { 2474 HasCX16 = true; 2475 continue; 2476 } 2477 2478 assert(Features[i][0] == '+' && "Invalid target feature!"); 2479 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2480 .Case("avx512f", AVX512F) 2481 .Case("avx2", AVX2) 2482 .Case("avx", AVX) 2483 .Case("sse4.2", SSE42) 2484 .Case("sse4.1", SSE41) 2485 .Case("ssse3", SSSE3) 2486 .Case("sse3", SSE3) 2487 .Case("sse2", SSE2) 2488 .Case("sse", SSE1) 2489 .Default(NoSSE); 2490 SSELevel = std::max(SSELevel, Level); 2491 2492 MMX3DNowEnum ThreeDNowLevel = 2493 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2494 .Case("3dnowa", AMD3DNowAthlon) 2495 .Case("3dnow", AMD3DNow) 2496 .Case("mmx", MMX) 2497 .Default(NoMMX3DNow); 2498 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2499 2500 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2501 .Case("xop", XOP) 2502 .Case("fma4", FMA4) 2503 .Case("sse4a", SSE4A) 2504 .Default(NoXOP); 2505 XOPLevel = std::max(XOPLevel, XLevel); 2506 } 2507 2508 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2509 // Can't do this earlier because we need to be able to explicitly enable 2510 // popcnt and still disable sse4.2. 2511 if (!HasPOPCNT && SSELevel >= SSE42 && 2512 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2513 HasPOPCNT = true; 2514 Features.push_back("+popcnt"); 2515 } 2516 2517 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2518 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2519 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2520 HasPRFCHW = true; 2521 Features.push_back("+prfchw"); 2522 } 2523 2524 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2525 // matches the selected sse level. 2526 if (FPMath == FP_SSE && SSELevel < SSE1) { 2527 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2528 return false; 2529 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2530 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2531 return false; 2532 } 2533 2534 // Don't tell the backend if we're turning off mmx; it will end up disabling 2535 // SSE, which we don't want. 2536 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2537 // then enable MMX. 2538 std::vector<std::string>::iterator it; 2539 it = std::find(Features.begin(), Features.end(), "-mmx"); 2540 if (it != Features.end()) 2541 Features.erase(it); 2542 else if (SSELevel > NoSSE) 2543 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2544 return true; 2545 } 2546 2547 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2548 /// definitions for this particular subtarget. 2549 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2550 MacroBuilder &Builder) const { 2551 // Target identification. 2552 if (getTriple().getArch() == llvm::Triple::x86_64) { 2553 Builder.defineMacro("__amd64__"); 2554 Builder.defineMacro("__amd64"); 2555 Builder.defineMacro("__x86_64"); 2556 Builder.defineMacro("__x86_64__"); 2557 } else { 2558 DefineStd(Builder, "i386", Opts); 2559 } 2560 2561 // Subtarget options. 2562 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2563 // truly should be based on -mtune options. 2564 switch (CPU) { 2565 case CK_Generic: 2566 break; 2567 case CK_i386: 2568 // The rest are coming from the i386 define above. 2569 Builder.defineMacro("__tune_i386__"); 2570 break; 2571 case CK_i486: 2572 case CK_WinChipC6: 2573 case CK_WinChip2: 2574 case CK_C3: 2575 defineCPUMacros(Builder, "i486"); 2576 break; 2577 case CK_PentiumMMX: 2578 Builder.defineMacro("__pentium_mmx__"); 2579 Builder.defineMacro("__tune_pentium_mmx__"); 2580 // Fallthrough 2581 case CK_i586: 2582 case CK_Pentium: 2583 defineCPUMacros(Builder, "i586"); 2584 defineCPUMacros(Builder, "pentium"); 2585 break; 2586 case CK_Pentium3: 2587 case CK_Pentium3M: 2588 case CK_PentiumM: 2589 Builder.defineMacro("__tune_pentium3__"); 2590 // Fallthrough 2591 case CK_Pentium2: 2592 case CK_C3_2: 2593 Builder.defineMacro("__tune_pentium2__"); 2594 // Fallthrough 2595 case CK_PentiumPro: 2596 Builder.defineMacro("__tune_i686__"); 2597 Builder.defineMacro("__tune_pentiumpro__"); 2598 // Fallthrough 2599 case CK_i686: 2600 Builder.defineMacro("__i686"); 2601 Builder.defineMacro("__i686__"); 2602 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2603 Builder.defineMacro("__pentiumpro"); 2604 Builder.defineMacro("__pentiumpro__"); 2605 break; 2606 case CK_Pentium4: 2607 case CK_Pentium4M: 2608 defineCPUMacros(Builder, "pentium4"); 2609 break; 2610 case CK_Yonah: 2611 case CK_Prescott: 2612 case CK_Nocona: 2613 defineCPUMacros(Builder, "nocona"); 2614 break; 2615 case CK_Core2: 2616 case CK_Penryn: 2617 defineCPUMacros(Builder, "core2"); 2618 break; 2619 case CK_Atom: 2620 defineCPUMacros(Builder, "atom"); 2621 break; 2622 case CK_Silvermont: 2623 defineCPUMacros(Builder, "slm"); 2624 break; 2625 case CK_Corei7: 2626 case CK_Corei7AVX: 2627 case CK_CoreAVXi: 2628 case CK_CoreAVX2: 2629 defineCPUMacros(Builder, "corei7"); 2630 break; 2631 case CK_KNL: 2632 defineCPUMacros(Builder, "knl"); 2633 break; 2634 case CK_K6_2: 2635 Builder.defineMacro("__k6_2__"); 2636 Builder.defineMacro("__tune_k6_2__"); 2637 // Fallthrough 2638 case CK_K6_3: 2639 if (CPU != CK_K6_2) { // In case of fallthrough 2640 // FIXME: GCC may be enabling these in cases where some other k6 2641 // architecture is specified but -m3dnow is explicitly provided. The 2642 // exact semantics need to be determined and emulated here. 2643 Builder.defineMacro("__k6_3__"); 2644 Builder.defineMacro("__tune_k6_3__"); 2645 } 2646 // Fallthrough 2647 case CK_K6: 2648 defineCPUMacros(Builder, "k6"); 2649 break; 2650 case CK_Athlon: 2651 case CK_AthlonThunderbird: 2652 case CK_Athlon4: 2653 case CK_AthlonXP: 2654 case CK_AthlonMP: 2655 defineCPUMacros(Builder, "athlon"); 2656 if (SSELevel != NoSSE) { 2657 Builder.defineMacro("__athlon_sse__"); 2658 Builder.defineMacro("__tune_athlon_sse__"); 2659 } 2660 break; 2661 case CK_K8: 2662 case CK_K8SSE3: 2663 case CK_x86_64: 2664 case CK_Opteron: 2665 case CK_OpteronSSE3: 2666 case CK_Athlon64: 2667 case CK_Athlon64SSE3: 2668 case CK_AthlonFX: 2669 defineCPUMacros(Builder, "k8"); 2670 break; 2671 case CK_AMDFAM10: 2672 defineCPUMacros(Builder, "amdfam10"); 2673 break; 2674 case CK_BTVER1: 2675 defineCPUMacros(Builder, "btver1"); 2676 break; 2677 case CK_BTVER2: 2678 defineCPUMacros(Builder, "btver2"); 2679 break; 2680 case CK_BDVER1: 2681 defineCPUMacros(Builder, "bdver1"); 2682 break; 2683 case CK_BDVER2: 2684 defineCPUMacros(Builder, "bdver2"); 2685 break; 2686 case CK_BDVER3: 2687 defineCPUMacros(Builder, "bdver3"); 2688 break; 2689 case CK_Geode: 2690 defineCPUMacros(Builder, "geode"); 2691 break; 2692 } 2693 2694 // Target properties. 2695 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2696 2697 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2698 // functions in glibc header files that use FP Stack inline asm which the 2699 // backend can't deal with (PR879). 2700 Builder.defineMacro("__NO_MATH_INLINES"); 2701 2702 if (HasAES) 2703 Builder.defineMacro("__AES__"); 2704 2705 if (HasPCLMUL) 2706 Builder.defineMacro("__PCLMUL__"); 2707 2708 if (HasLZCNT) 2709 Builder.defineMacro("__LZCNT__"); 2710 2711 if (HasRDRND) 2712 Builder.defineMacro("__RDRND__"); 2713 2714 if (HasBMI) 2715 Builder.defineMacro("__BMI__"); 2716 2717 if (HasBMI2) 2718 Builder.defineMacro("__BMI2__"); 2719 2720 if (HasPOPCNT) 2721 Builder.defineMacro("__POPCNT__"); 2722 2723 if (HasRTM) 2724 Builder.defineMacro("__RTM__"); 2725 2726 if (HasPRFCHW) 2727 Builder.defineMacro("__PRFCHW__"); 2728 2729 if (HasRDSEED) 2730 Builder.defineMacro("__RDSEED__"); 2731 2732 if (HasTBM) 2733 Builder.defineMacro("__TBM__"); 2734 2735 switch (XOPLevel) { 2736 case XOP: 2737 Builder.defineMacro("__XOP__"); 2738 case FMA4: 2739 Builder.defineMacro("__FMA4__"); 2740 case SSE4A: 2741 Builder.defineMacro("__SSE4A__"); 2742 case NoXOP: 2743 break; 2744 } 2745 2746 if (HasFMA) 2747 Builder.defineMacro("__FMA__"); 2748 2749 if (HasF16C) 2750 Builder.defineMacro("__F16C__"); 2751 2752 if (HasAVX512CD) 2753 Builder.defineMacro("__AVX512CD__"); 2754 if (HasAVX512ER) 2755 Builder.defineMacro("__AVX512ER__"); 2756 if (HasAVX512PF) 2757 Builder.defineMacro("__AVX512PF__"); 2758 2759 if (HasSHA) 2760 Builder.defineMacro("__SHA__"); 2761 2762 if (HasCX16) 2763 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2764 2765 // Each case falls through to the previous one here. 2766 switch (SSELevel) { 2767 case AVX512F: 2768 Builder.defineMacro("__AVX512F__"); 2769 case AVX2: 2770 Builder.defineMacro("__AVX2__"); 2771 case AVX: 2772 Builder.defineMacro("__AVX__"); 2773 case SSE42: 2774 Builder.defineMacro("__SSE4_2__"); 2775 case SSE41: 2776 Builder.defineMacro("__SSE4_1__"); 2777 case SSSE3: 2778 Builder.defineMacro("__SSSE3__"); 2779 case SSE3: 2780 Builder.defineMacro("__SSE3__"); 2781 case SSE2: 2782 Builder.defineMacro("__SSE2__"); 2783 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2784 case SSE1: 2785 Builder.defineMacro("__SSE__"); 2786 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2787 case NoSSE: 2788 break; 2789 } 2790 2791 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2792 switch (SSELevel) { 2793 case AVX512F: 2794 case AVX2: 2795 case AVX: 2796 case SSE42: 2797 case SSE41: 2798 case SSSE3: 2799 case SSE3: 2800 case SSE2: 2801 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2802 break; 2803 case SSE1: 2804 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2805 break; 2806 default: 2807 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2808 } 2809 } 2810 2811 // Each case falls through to the previous one here. 2812 switch (MMX3DNowLevel) { 2813 case AMD3DNowAthlon: 2814 Builder.defineMacro("__3dNOW_A__"); 2815 case AMD3DNow: 2816 Builder.defineMacro("__3dNOW__"); 2817 case MMX: 2818 Builder.defineMacro("__MMX__"); 2819 case NoMMX3DNow: 2820 break; 2821 } 2822 2823 if (CPU >= CK_i486) { 2824 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2825 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2826 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2827 } 2828 if (CPU >= CK_i586) 2829 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2830 } 2831 2832 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2833 return llvm::StringSwitch<bool>(Feature) 2834 .Case("aes", HasAES) 2835 .Case("avx", SSELevel >= AVX) 2836 .Case("avx2", SSELevel >= AVX2) 2837 .Case("avx512f", SSELevel >= AVX512F) 2838 .Case("avx512cd", HasAVX512CD) 2839 .Case("avx512er", HasAVX512ER) 2840 .Case("avx512pf", HasAVX512PF) 2841 .Case("bmi", HasBMI) 2842 .Case("bmi2", HasBMI2) 2843 .Case("cx16", HasCX16) 2844 .Case("f16c", HasF16C) 2845 .Case("fma", HasFMA) 2846 .Case("fma4", XOPLevel >= FMA4) 2847 .Case("tbm", HasTBM) 2848 .Case("lzcnt", HasLZCNT) 2849 .Case("rdrnd", HasRDRND) 2850 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2851 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2852 .Case("mmx", MMX3DNowLevel >= MMX) 2853 .Case("pclmul", HasPCLMUL) 2854 .Case("popcnt", HasPOPCNT) 2855 .Case("rtm", HasRTM) 2856 .Case("prfchw", HasPRFCHW) 2857 .Case("rdseed", HasRDSEED) 2858 .Case("sha", HasSHA) 2859 .Case("sse", SSELevel >= SSE1) 2860 .Case("sse2", SSELevel >= SSE2) 2861 .Case("sse3", SSELevel >= SSE3) 2862 .Case("ssse3", SSELevel >= SSSE3) 2863 .Case("sse4.1", SSELevel >= SSE41) 2864 .Case("sse4.2", SSELevel >= SSE42) 2865 .Case("sse4a", XOPLevel >= SSE4A) 2866 .Case("x86", true) 2867 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2868 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2869 .Case("xop", XOPLevel >= XOP) 2870 .Default(false); 2871 } 2872 2873 bool 2874 X86TargetInfo::validateAsmConstraint(const char *&Name, 2875 TargetInfo::ConstraintInfo &Info) const { 2876 switch (*Name) { 2877 default: return false; 2878 case 'Y': // first letter of a pair: 2879 switch (*(Name+1)) { 2880 default: return false; 2881 case '0': // First SSE register. 2882 case 't': // Any SSE register, when SSE2 is enabled. 2883 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2884 case 'm': // any MMX register, when inter-unit moves enabled. 2885 break; // falls through to setAllowsRegister. 2886 } 2887 case 'a': // eax. 2888 case 'b': // ebx. 2889 case 'c': // ecx. 2890 case 'd': // edx. 2891 case 'S': // esi. 2892 case 'D': // edi. 2893 case 'A': // edx:eax. 2894 case 'f': // any x87 floating point stack register. 2895 case 't': // top of floating point stack. 2896 case 'u': // second from top of floating point stack. 2897 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2898 case 'y': // Any MMX register. 2899 case 'x': // Any SSE register. 2900 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2901 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2902 case 'l': // "Index" registers: any general register that can be used as an 2903 // index in a base+index memory access. 2904 Info.setAllowsRegister(); 2905 return true; 2906 case 'C': // SSE floating point constant. 2907 case 'G': // x87 floating point constant. 2908 case 'e': // 32-bit signed integer constant for use with zero-extending 2909 // x86_64 instructions. 2910 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2911 // x86_64 instructions. 2912 return true; 2913 } 2914 } 2915 2916 2917 std::string 2918 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2919 switch (*Constraint) { 2920 case 'a': return std::string("{ax}"); 2921 case 'b': return std::string("{bx}"); 2922 case 'c': return std::string("{cx}"); 2923 case 'd': return std::string("{dx}"); 2924 case 'S': return std::string("{si}"); 2925 case 'D': return std::string("{di}"); 2926 case 'p': // address 2927 return std::string("im"); 2928 case 't': // top of floating point stack. 2929 return std::string("{st}"); 2930 case 'u': // second from top of floating point stack. 2931 return std::string("{st(1)}"); // second from top of floating point stack. 2932 default: 2933 return std::string(1, *Constraint); 2934 } 2935 } 2936 } // end anonymous namespace 2937 2938 namespace { 2939 // X86-32 generic target 2940 class X86_32TargetInfo : public X86TargetInfo { 2941 public: 2942 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 2943 DoubleAlign = LongLongAlign = 32; 2944 LongDoubleWidth = 96; 2945 LongDoubleAlign = 32; 2946 SuitableAlign = 128; 2947 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 2948 SizeType = UnsignedInt; 2949 PtrDiffType = SignedInt; 2950 IntPtrType = SignedInt; 2951 RegParmMax = 3; 2952 2953 // Use fpret for all types. 2954 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2955 (1 << TargetInfo::Double) | 2956 (1 << TargetInfo::LongDouble)); 2957 2958 // x86-32 has atomics up to 8 bytes 2959 // FIXME: Check that we actually have cmpxchg8b before setting 2960 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2961 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2962 } 2963 BuiltinVaListKind getBuiltinVaListKind() const override { 2964 return TargetInfo::CharPtrBuiltinVaList; 2965 } 2966 2967 int getEHDataRegisterNumber(unsigned RegNo) const override { 2968 if (RegNo == 0) return 0; 2969 if (RegNo == 1) return 2; 2970 return -1; 2971 } 2972 bool validateInputSize(StringRef Constraint, 2973 unsigned Size) const override { 2974 switch (Constraint[0]) { 2975 default: break; 2976 case 'a': 2977 case 'b': 2978 case 'c': 2979 case 'd': 2980 return Size <= 32; 2981 } 2982 2983 return true; 2984 } 2985 }; 2986 } // end anonymous namespace 2987 2988 namespace { 2989 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2990 public: 2991 NetBSDI386TargetInfo(const llvm::Triple &Triple) 2992 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 2993 2994 unsigned getFloatEvalMethod() const override { 2995 unsigned Major, Minor, Micro; 2996 getTriple().getOSVersion(Major, Minor, Micro); 2997 // New NetBSD uses the default rounding mode. 2998 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 2999 return X86_32TargetInfo::getFloatEvalMethod(); 3000 // NetBSD before 6.99.26 defaults to "double" rounding. 3001 return 1; 3002 } 3003 }; 3004 } // end anonymous namespace 3005 3006 namespace { 3007 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3008 public: 3009 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3010 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3011 SizeType = UnsignedLong; 3012 IntPtrType = SignedLong; 3013 PtrDiffType = SignedLong; 3014 } 3015 }; 3016 } // end anonymous namespace 3017 3018 namespace { 3019 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3020 public: 3021 BitrigI386TargetInfo(const llvm::Triple &Triple) 3022 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3023 SizeType = UnsignedLong; 3024 IntPtrType = SignedLong; 3025 PtrDiffType = SignedLong; 3026 } 3027 }; 3028 } // end anonymous namespace 3029 3030 namespace { 3031 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3032 public: 3033 DarwinI386TargetInfo(const llvm::Triple &Triple) 3034 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3035 LongDoubleWidth = 128; 3036 LongDoubleAlign = 128; 3037 SuitableAlign = 128; 3038 MaxVectorAlign = 256; 3039 SizeType = UnsignedLong; 3040 IntPtrType = SignedLong; 3041 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3042 HasAlignMac68kSupport = true; 3043 } 3044 3045 }; 3046 } // end anonymous namespace 3047 3048 namespace { 3049 // x86-32 Windows target 3050 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3051 public: 3052 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3053 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3054 TLSSupported = false; 3055 WCharType = UnsignedShort; 3056 DoubleAlign = LongLongAlign = 64; 3057 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3058 } 3059 void getTargetDefines(const LangOptions &Opts, 3060 MacroBuilder &Builder) const override { 3061 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3062 } 3063 }; 3064 } // end anonymous namespace 3065 3066 namespace { 3067 3068 // x86-32 Windows Visual Studio target 3069 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3070 public: 3071 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3072 : WindowsX86_32TargetInfo(Triple) { 3073 LongDoubleWidth = LongDoubleAlign = 64; 3074 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3075 } 3076 void getTargetDefines(const LangOptions &Opts, 3077 MacroBuilder &Builder) const override { 3078 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3079 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3080 // The value of the following reflects processor type. 3081 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3082 // We lost the original triple, so we use the default. 3083 Builder.defineMacro("_M_IX86", "600"); 3084 } 3085 }; 3086 } // end anonymous namespace 3087 3088 namespace { 3089 // x86-32 MinGW target 3090 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3091 public: 3092 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3093 : WindowsX86_32TargetInfo(Triple) {} 3094 void getTargetDefines(const LangOptions &Opts, 3095 MacroBuilder &Builder) const override { 3096 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3097 DefineStd(Builder, "WIN32", Opts); 3098 DefineStd(Builder, "WINNT", Opts); 3099 Builder.defineMacro("_X86_"); 3100 Builder.defineMacro("__MSVCRT__"); 3101 Builder.defineMacro("__MINGW32__"); 3102 3103 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3104 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3105 if (Opts.MicrosoftExt) 3106 // Provide "as-is" __declspec. 3107 Builder.defineMacro("__declspec", "__declspec"); 3108 else 3109 // Provide alias of __attribute__ like mingw32-gcc. 3110 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3111 } 3112 }; 3113 } // end anonymous namespace 3114 3115 namespace { 3116 // x86-32 Cygwin target 3117 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3118 public: 3119 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3120 : X86_32TargetInfo(Triple) { 3121 TLSSupported = false; 3122 WCharType = UnsignedShort; 3123 DoubleAlign = LongLongAlign = 64; 3124 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3125 } 3126 void getTargetDefines(const LangOptions &Opts, 3127 MacroBuilder &Builder) const override { 3128 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3129 Builder.defineMacro("_X86_"); 3130 Builder.defineMacro("__CYGWIN__"); 3131 Builder.defineMacro("__CYGWIN32__"); 3132 DefineStd(Builder, "unix", Opts); 3133 if (Opts.CPlusPlus) 3134 Builder.defineMacro("_GNU_SOURCE"); 3135 } 3136 }; 3137 } // end anonymous namespace 3138 3139 namespace { 3140 // x86-32 Haiku target 3141 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3142 public: 3143 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3144 SizeType = UnsignedLong; 3145 IntPtrType = SignedLong; 3146 PtrDiffType = SignedLong; 3147 ProcessIDType = SignedLong; 3148 this->UserLabelPrefix = ""; 3149 this->TLSSupported = false; 3150 } 3151 void getTargetDefines(const LangOptions &Opts, 3152 MacroBuilder &Builder) const override { 3153 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3154 Builder.defineMacro("__INTEL__"); 3155 Builder.defineMacro("__HAIKU__"); 3156 } 3157 }; 3158 } // end anonymous namespace 3159 3160 // RTEMS Target 3161 template<typename Target> 3162 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3163 protected: 3164 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3165 MacroBuilder &Builder) const override { 3166 // RTEMS defines; list based off of gcc output 3167 3168 Builder.defineMacro("__rtems__"); 3169 Builder.defineMacro("__ELF__"); 3170 } 3171 3172 public: 3173 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3174 this->UserLabelPrefix = ""; 3175 3176 switch (Triple.getArch()) { 3177 default: 3178 case llvm::Triple::x86: 3179 // this->MCountName = ".mcount"; 3180 break; 3181 case llvm::Triple::mips: 3182 case llvm::Triple::mipsel: 3183 case llvm::Triple::ppc: 3184 case llvm::Triple::ppc64: 3185 case llvm::Triple::ppc64le: 3186 // this->MCountName = "_mcount"; 3187 break; 3188 case llvm::Triple::arm: 3189 // this->MCountName = "__mcount"; 3190 break; 3191 } 3192 } 3193 }; 3194 3195 namespace { 3196 // x86-32 RTEMS target 3197 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3198 public: 3199 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3200 SizeType = UnsignedLong; 3201 IntPtrType = SignedLong; 3202 PtrDiffType = SignedLong; 3203 this->UserLabelPrefix = ""; 3204 } 3205 void getTargetDefines(const LangOptions &Opts, 3206 MacroBuilder &Builder) const override { 3207 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3208 Builder.defineMacro("__INTEL__"); 3209 Builder.defineMacro("__rtems__"); 3210 } 3211 }; 3212 } // end anonymous namespace 3213 3214 namespace { 3215 // x86-64 generic target 3216 class X86_64TargetInfo : public X86TargetInfo { 3217 public: 3218 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3219 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 3220 LongDoubleWidth = 128; 3221 LongDoubleAlign = 128; 3222 LargeArrayMinWidth = 128; 3223 LargeArrayAlign = 128; 3224 SuitableAlign = 128; 3225 IntMaxType = SignedLong; 3226 UIntMaxType = UnsignedLong; 3227 Int64Type = SignedLong; 3228 RegParmMax = 6; 3229 3230 DescriptionString = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3231 3232 // Use fpret only for long double. 3233 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3234 3235 // Use fp2ret for _Complex long double. 3236 ComplexLongDoubleUsesFP2Ret = true; 3237 3238 // x86-64 has atomics up to 16 bytes. 3239 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 3240 // on CPUs with cmpxchg16b 3241 MaxAtomicPromoteWidth = 128; 3242 MaxAtomicInlineWidth = 64; 3243 } 3244 BuiltinVaListKind getBuiltinVaListKind() const override { 3245 return TargetInfo::X86_64ABIBuiltinVaList; 3246 } 3247 3248 int getEHDataRegisterNumber(unsigned RegNo) const override { 3249 if (RegNo == 0) return 0; 3250 if (RegNo == 1) return 1; 3251 return -1; 3252 } 3253 3254 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3255 return (CC == CC_C || 3256 CC == CC_IntelOclBicc || 3257 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3258 } 3259 3260 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3261 return CC_C; 3262 } 3263 3264 }; 3265 } // end anonymous namespace 3266 3267 namespace { 3268 // x86-64 Windows target 3269 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3270 public: 3271 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3272 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3273 TLSSupported = false; 3274 WCharType = UnsignedShort; 3275 LongWidth = LongAlign = 32; 3276 DoubleAlign = LongLongAlign = 64; 3277 IntMaxType = SignedLongLong; 3278 UIntMaxType = UnsignedLongLong; 3279 Int64Type = SignedLongLong; 3280 SizeType = UnsignedLongLong; 3281 PtrDiffType = SignedLongLong; 3282 IntPtrType = SignedLongLong; 3283 this->UserLabelPrefix = ""; 3284 } 3285 void getTargetDefines(const LangOptions &Opts, 3286 MacroBuilder &Builder) const override { 3287 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3288 Builder.defineMacro("_WIN64"); 3289 } 3290 BuiltinVaListKind getBuiltinVaListKind() const override { 3291 return TargetInfo::CharPtrBuiltinVaList; 3292 } 3293 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3294 return (CC == CC_C || 3295 CC == CC_IntelOclBicc || 3296 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3297 } 3298 }; 3299 } // end anonymous namespace 3300 3301 namespace { 3302 // x86-64 Windows Visual Studio target 3303 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3304 public: 3305 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3306 : WindowsX86_64TargetInfo(Triple) { 3307 LongDoubleWidth = LongDoubleAlign = 64; 3308 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3309 } 3310 void getTargetDefines(const LangOptions &Opts, 3311 MacroBuilder &Builder) const override { 3312 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3313 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3314 Builder.defineMacro("_M_X64"); 3315 Builder.defineMacro("_M_AMD64"); 3316 } 3317 }; 3318 } // end anonymous namespace 3319 3320 namespace { 3321 // x86-64 MinGW target 3322 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3323 public: 3324 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3325 : WindowsX86_64TargetInfo(Triple) {} 3326 void getTargetDefines(const LangOptions &Opts, 3327 MacroBuilder &Builder) const override { 3328 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3329 DefineStd(Builder, "WIN64", Opts); 3330 Builder.defineMacro("__MSVCRT__"); 3331 Builder.defineMacro("__MINGW32__"); 3332 Builder.defineMacro("__MINGW64__"); 3333 3334 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3335 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3336 if (Opts.MicrosoftExt) 3337 // Provide "as-is" __declspec. 3338 Builder.defineMacro("__declspec", "__declspec"); 3339 else 3340 // Provide alias of __attribute__ like mingw32-gcc. 3341 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3342 } 3343 }; 3344 } // end anonymous namespace 3345 3346 namespace { 3347 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3348 public: 3349 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3350 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3351 Int64Type = SignedLongLong; 3352 MaxVectorAlign = 256; 3353 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3354 llvm::Triple T = llvm::Triple(Triple); 3355 if (T.getOS() == llvm::Triple::IOS) 3356 UseSignedCharForObjCBool = false; 3357 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3358 } 3359 }; 3360 } // end anonymous namespace 3361 3362 namespace { 3363 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3364 public: 3365 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3366 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3367 IntMaxType = SignedLongLong; 3368 UIntMaxType = UnsignedLongLong; 3369 Int64Type = SignedLongLong; 3370 } 3371 }; 3372 } // end anonymous namespace 3373 3374 namespace { 3375 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3376 public: 3377 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3378 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3379 IntMaxType = SignedLongLong; 3380 UIntMaxType = UnsignedLongLong; 3381 Int64Type = SignedLongLong; 3382 } 3383 }; 3384 } 3385 3386 namespace { 3387 class AArch64TargetInfo : public TargetInfo { 3388 virtual void setDescriptionString() = 0; 3389 static const char * const GCCRegNames[]; 3390 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3391 3392 enum FPUModeEnum { 3393 FPUMode, 3394 NeonMode 3395 }; 3396 3397 unsigned FPU; 3398 unsigned Crypto; 3399 static const Builtin::Info BuiltinInfo[]; 3400 3401 public: 3402 AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 3403 LongWidth = LongAlign = 64; 3404 LongDoubleWidth = LongDoubleAlign = 128; 3405 PointerWidth = PointerAlign = 64; 3406 SuitableAlign = 128; 3407 3408 WCharType = UnsignedInt; 3409 if (getTriple().getOS() == llvm::Triple::NetBSD) { 3410 WCharType = SignedInt; 3411 Int64Type = SignedLongLong; 3412 IntMaxType = SignedLongLong; 3413 UIntMaxType = UnsignedLongLong; 3414 } else { 3415 WCharType = UnsignedInt; 3416 Int64Type = SignedLong; 3417 IntMaxType = SignedLong; 3418 UIntMaxType = UnsignedLong; 3419 } 3420 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3421 3422 // AArch64 backend supports 64-bit operations at the moment. In principle 3423 // 128-bit is possible if register-pairs are used. 3424 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3425 3426 TheCXXABI.set(TargetCXXABI::GenericAArch64); 3427 } 3428 void getTargetDefines(const LangOptions &Opts, 3429 MacroBuilder &Builder) const override { 3430 // GCC defines theses currently 3431 Builder.defineMacro("__aarch64__"); 3432 3433 // ACLE predefines. Many can only have one possible value on v8 AArch64. 3434 Builder.defineMacro("__ARM_ACLE", "200"); 3435 Builder.defineMacro("__ARM_ARCH", "8"); 3436 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 3437 3438 Builder.defineMacro("__ARM_64BIT_STATE"); 3439 Builder.defineMacro("__ARM_PCS_AAPCS64"); 3440 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 3441 3442 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 3443 Builder.defineMacro("__ARM_FEATURE_CLZ"); 3444 Builder.defineMacro("__ARM_FEATURE_FMA"); 3445 Builder.defineMacro("__ARM_FEATURE_DIV"); 3446 3447 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 3448 3449 // 0xe implies support for half, single and double precision operations. 3450 Builder.defineMacro("__ARM_FP", "0xe"); 3451 3452 // PCS specifies this for SysV variants, which is all we support. Other ABIs 3453 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 3454 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 3455 3456 if (Opts.FastMath || Opts.FiniteMathOnly) 3457 Builder.defineMacro("__ARM_FP_FAST"); 3458 3459 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 3460 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 3461 3462 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3463 Opts.ShortWChar ? "2" : "4"); 3464 3465 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3466 Opts.ShortEnums ? "1" : "4"); 3467 3468 if (FPU == NeonMode) { 3469 Builder.defineMacro("__ARM_NEON"); 3470 // 64-bit NEON supports half, single and double precision operations. 3471 Builder.defineMacro("__ARM_NEON_FP", "7"); 3472 } 3473 3474 if (Crypto) { 3475 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 3476 } 3477 } 3478 void getTargetBuiltins(const Builtin::Info *&Records, 3479 unsigned &NumRecords) const override { 3480 Records = BuiltinInfo; 3481 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin; 3482 } 3483 bool hasFeature(StringRef Feature) const override { 3484 return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode); 3485 } 3486 3487 bool setCPU(const std::string &Name) override { 3488 return llvm::StringSwitch<bool>(Name) 3489 .Case("generic", true) 3490 .Cases("cortex-a53", "cortex-a57", true) 3491 .Default(false); 3492 } 3493 3494 bool handleTargetFeatures(std::vector<std::string> &Features, 3495 DiagnosticsEngine &Diags) override { 3496 FPU = FPUMode; 3497 Crypto = 0; 3498 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3499 if (Features[i] == "+neon") 3500 FPU = NeonMode; 3501 if (Features[i] == "+crypto") 3502 Crypto = 1; 3503 } 3504 3505 setDescriptionString(); 3506 3507 return true; 3508 } 3509 3510 void getGCCRegNames(const char *const *&Names, 3511 unsigned &NumNames) const override; 3512 void getGCCRegAliases(const GCCRegAlias *&Aliases, 3513 unsigned &NumAliases) const override; 3514 3515 bool isCLZForZeroUndef() const override { return false; } 3516 3517 bool validateAsmConstraint(const char *&Name, 3518 TargetInfo::ConstraintInfo &Info) const override { 3519 switch (*Name) { 3520 default: return false; 3521 case 'w': // An FP/SIMD vector register 3522 Info.setAllowsRegister(); 3523 return true; 3524 case 'I': // Constant that can be used with an ADD instruction 3525 case 'J': // Constant that can be used with a SUB instruction 3526 case 'K': // Constant that can be used with a 32-bit logical instruction 3527 case 'L': // Constant that can be used with a 64-bit logical instruction 3528 case 'M': // Constant that can be used as a 32-bit MOV immediate 3529 case 'N': // Constant that can be used as a 64-bit MOV immediate 3530 case 'Y': // Floating point constant zero 3531 case 'Z': // Integer constant zero 3532 return true; 3533 case 'Q': // A memory reference with base register and no offset 3534 Info.setAllowsMemory(); 3535 return true; 3536 case 'S': // A symbolic address 3537 Info.setAllowsRegister(); 3538 return true; 3539 case 'U': 3540 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 3541 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 3542 // Usa: An absolute symbolic address 3543 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 3544 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 3545 } 3546 } 3547 3548 const char *getClobbers() const override { 3549 // There are no AArch64 clobbers shared by all asm statements. 3550 return ""; 3551 } 3552 3553 BuiltinVaListKind getBuiltinVaListKind() const override { 3554 return TargetInfo::AArch64ABIBuiltinVaList; 3555 } 3556 }; 3557 3558 const char * const AArch64TargetInfo::GCCRegNames[] = { 3559 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", 3560 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", 3561 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", 3562 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr", 3563 3564 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 3565 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 3566 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 3567 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr", 3568 3569 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", 3570 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", 3571 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", 3572 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31", 3573 3574 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", 3575 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", 3576 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", 3577 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", 3578 3579 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3580 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3581 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3582 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3583 3584 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3585 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3586 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3587 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3588 3589 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3590 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", 3591 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", 3592 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" 3593 }; 3594 3595 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names, 3596 unsigned &NumNames) const { 3597 Names = GCCRegNames; 3598 NumNames = llvm::array_lengthof(GCCRegNames); 3599 } 3600 3601 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 3602 { { "x16" }, "ip0"}, 3603 { { "x17" }, "ip1"}, 3604 { { "x29" }, "fp" }, 3605 { { "x30" }, "lr" } 3606 }; 3607 3608 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3609 unsigned &NumAliases) const { 3610 Aliases = GCCRegAliases; 3611 NumAliases = llvm::array_lengthof(GCCRegAliases); 3612 3613 } 3614 3615 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 3616 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3617 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3618 ALL_LANGUAGES }, 3619 #include "clang/Basic/BuiltinsNEON.def" 3620 3621 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3622 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3623 ALL_LANGUAGES }, 3624 #include "clang/Basic/BuiltinsAArch64.def" 3625 }; 3626 3627 class AArch64leTargetInfo : public AArch64TargetInfo { 3628 void setDescriptionString() override { 3629 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 3630 } 3631 3632 public: 3633 AArch64leTargetInfo(const llvm::Triple &Triple) 3634 : AArch64TargetInfo(Triple) { 3635 BigEndian = false; 3636 } 3637 void getTargetDefines(const LangOptions &Opts, 3638 MacroBuilder &Builder) const override { 3639 Builder.defineMacro("__AARCH64EL__"); 3640 AArch64TargetInfo::getTargetDefines(Opts, Builder); 3641 } 3642 }; 3643 3644 class AArch64beTargetInfo : public AArch64TargetInfo { 3645 void setDescriptionString() override { 3646 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 3647 } 3648 3649 public: 3650 AArch64beTargetInfo(const llvm::Triple &Triple) 3651 : AArch64TargetInfo(Triple) { } 3652 void getTargetDefines(const LangOptions &Opts, 3653 MacroBuilder &Builder) const override { 3654 Builder.defineMacro("__AARCH64EB__"); 3655 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 3656 Builder.defineMacro("__ARM_BIG_ENDIAN"); 3657 AArch64TargetInfo::getTargetDefines(Opts, Builder); 3658 } 3659 }; 3660 3661 } // end anonymous namespace 3662 3663 namespace { 3664 class ARMTargetInfo : public TargetInfo { 3665 // Possible FPU choices. 3666 enum FPUMode { 3667 VFP2FPU = (1 << 0), 3668 VFP3FPU = (1 << 1), 3669 VFP4FPU = (1 << 2), 3670 NeonFPU = (1 << 3), 3671 FPARMV8 = (1 << 4) 3672 }; 3673 3674 // Possible HWDiv features. 3675 enum HWDivMode { 3676 HWDivThumb = (1 << 0), 3677 HWDivARM = (1 << 1) 3678 }; 3679 3680 static bool FPUModeIsVFP(FPUMode Mode) { 3681 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3682 } 3683 3684 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3685 static const char * const GCCRegNames[]; 3686 3687 std::string ABI, CPU; 3688 3689 enum { 3690 FP_Default, 3691 FP_VFP, 3692 FP_Neon 3693 } FPMath; 3694 3695 unsigned FPU : 5; 3696 3697 unsigned IsAAPCS : 1; 3698 unsigned IsThumb : 1; 3699 unsigned HWDiv : 2; 3700 3701 // Initialized via features. 3702 unsigned SoftFloat : 1; 3703 unsigned SoftFloatABI : 1; 3704 3705 unsigned CRC : 1; 3706 unsigned Crypto : 1; 3707 3708 static const Builtin::Info BuiltinInfo[]; 3709 3710 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3711 if (T.isOSWindows()) 3712 return true; 3713 3714 // On linux, binaries targeting old cpus call functions in libgcc to 3715 // perform atomic operations. The implementation in libgcc then calls into 3716 // the kernel which on armv6 and newer uses ldrex and strex. The net result 3717 // is that if we assume the kernel is at least as recent as the hardware, 3718 // it is safe to use atomic instructions on armv6 and newer. 3719 if (!T.isOSLinux() && 3720 T.getOS() != llvm::Triple::FreeBSD && 3721 T.getOS() != llvm::Triple::NetBSD && 3722 T.getOS() != llvm::Triple::Bitrig) 3723 return false; 3724 StringRef ArchName = T.getArchName(); 3725 if (T.getArch() == llvm::Triple::arm || 3726 T.getArch() == llvm::Triple::armeb) { 3727 StringRef VersionStr; 3728 if (ArchName.startswith("armv")) 3729 VersionStr = ArchName.substr(4); 3730 else if (ArchName.startswith("armebv")) 3731 VersionStr = ArchName.substr(6); 3732 else 3733 return false; 3734 unsigned Version; 3735 if (VersionStr.getAsInteger(10, Version)) 3736 return false; 3737 return Version >= 6; 3738 } 3739 assert(T.getArch() == llvm::Triple::thumb || 3740 T.getArch() == llvm::Triple::thumbeb); 3741 StringRef VersionStr; 3742 if (ArchName.startswith("thumbv")) 3743 VersionStr = ArchName.substr(6); 3744 else if (ArchName.startswith("thumbebv")) 3745 VersionStr = ArchName.substr(8); 3746 else 3747 return false; 3748 unsigned Version; 3749 if (VersionStr.getAsInteger(10, Version)) 3750 return false; 3751 return Version >= 7; 3752 } 3753 3754 void setABIAAPCS() { 3755 IsAAPCS = true; 3756 3757 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3758 const llvm::Triple &T = getTriple(); 3759 3760 // size_t is unsigned long on Darwin and NetBSD. 3761 if (T.isOSDarwin() || T.getOS() == llvm::Triple::NetBSD) 3762 SizeType = UnsignedLong; 3763 else 3764 SizeType = UnsignedInt; 3765 3766 if (T.getOS() == llvm::Triple::NetBSD) { 3767 WCharType = SignedInt; 3768 } else { 3769 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3770 WCharType = UnsignedInt; 3771 } 3772 3773 UseBitFieldTypeAlignment = true; 3774 3775 ZeroLengthBitfieldBoundary = 0; 3776 3777 if (IsThumb) { 3778 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3779 // so set preferred for small types to 32. 3780 if (T.isOSBinFormatMachO()) { 3781 DescriptionString = BigEndian ? 3782 "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3783 "v128:64:128-a:0:32-n32-S64" : 3784 "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3785 "v128:64:128-a:0:32-n32-S64"; 3786 } else if (T.isOSWindows()) { 3787 // FIXME: this is invalid for WindowsCE 3788 assert(!BigEndian && "Windows on ARM does not support big endian"); 3789 DescriptionString = "e" 3790 "-m:e" 3791 "-p:32:32" 3792 "-i1:8:32-i8:8:32-i16:16:32-i64:64" 3793 "-v128:64:128" 3794 "-a:0:32" 3795 "-n32" 3796 "-S64"; 3797 } else { 3798 DescriptionString = BigEndian ? 3799 "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3800 "v128:64:128-a:0:32-n32-S64" : 3801 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3802 "v128:64:128-a:0:32-n32-S64"; 3803 } 3804 } else { 3805 if (T.isOSBinFormatMachO()) 3806 DescriptionString = BigEndian ? 3807 "E-m:o-p:32:32-i64:64-v128:64:128-n32-S64" : 3808 "e-m:o-p:32:32-i64:64-v128:64:128-n32-S64"; 3809 else 3810 DescriptionString = BigEndian ? 3811 "E-m:e-p:32:32-i64:64-v128:64:128-n32-S64" : 3812 "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"; 3813 } 3814 3815 // FIXME: Enumerated types are variable width in straight AAPCS. 3816 } 3817 3818 void setABIAPCS() { 3819 const llvm::Triple &T = getTriple(); 3820 3821 IsAAPCS = false; 3822 3823 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3824 3825 // size_t is unsigned int on FreeBSD. 3826 if (T.getOS() == llvm::Triple::FreeBSD) 3827 SizeType = UnsignedInt; 3828 else 3829 SizeType = UnsignedLong; 3830 3831 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3832 WCharType = SignedInt; 3833 3834 // Do not respect the alignment of bit-field types when laying out 3835 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3836 UseBitFieldTypeAlignment = false; 3837 3838 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3839 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3840 /// gcc. 3841 ZeroLengthBitfieldBoundary = 32; 3842 3843 if (IsThumb) { 3844 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3845 // so set preferred for small types to 32. 3846 if (T.isOSBinFormatMachO()) 3847 DescriptionString = BigEndian ? 3848 "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3849 "-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3850 "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3851 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3852 else 3853 DescriptionString = BigEndian ? 3854 "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3855 "-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3856 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3857 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3858 } else { 3859 if (T.isOSBinFormatMachO()) 3860 DescriptionString = BigEndian ? 3861 "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3862 "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3863 else 3864 DescriptionString = BigEndian ? 3865 "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3866 "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3867 } 3868 3869 // FIXME: Override "preferred align" for double and long long. 3870 } 3871 3872 public: 3873 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 3874 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3875 IsAAPCS(true) { 3876 BigEndian = IsBigEndian; 3877 3878 switch (getTriple().getOS()) { 3879 case llvm::Triple::NetBSD: 3880 PtrDiffType = SignedLong; 3881 break; 3882 default: 3883 PtrDiffType = SignedInt; 3884 break; 3885 } 3886 3887 // {} in inline assembly are neon specifiers, not assembly variant 3888 // specifiers. 3889 NoAsmVariants = true; 3890 3891 // FIXME: Should we just treat this as a feature? 3892 IsThumb = getTriple().getArchName().startswith("thumb"); 3893 3894 setABI("aapcs-linux"); 3895 3896 // ARM targets default to using the ARM C++ ABI. 3897 TheCXXABI.set(TargetCXXABI::GenericARM); 3898 3899 // ARM has atomics up to 8 bytes 3900 MaxAtomicPromoteWidth = 64; 3901 if (shouldUseInlineAtomic(getTriple())) 3902 MaxAtomicInlineWidth = 64; 3903 3904 // Do force alignment of members that follow zero length bitfields. If 3905 // the alignment of the zero-length bitfield is greater than the member 3906 // that follows it, `bar', `bar' will be aligned as the type of the 3907 // zero length bitfield. 3908 UseZeroLengthBitfieldAlignment = true; 3909 } 3910 const char *getABI() const override { return ABI.c_str(); } 3911 bool setABI(const std::string &Name) override { 3912 ABI = Name; 3913 3914 // The defaults (above) are for AAPCS, check if we need to change them. 3915 // 3916 // FIXME: We need support for -meabi... we could just mangle it into the 3917 // name. 3918 if (Name == "apcs-gnu") { 3919 setABIAPCS(); 3920 return true; 3921 } 3922 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 3923 setABIAAPCS(); 3924 return true; 3925 } 3926 return false; 3927 } 3928 3929 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 3930 if (IsAAPCS) 3931 Features["aapcs"] = true; 3932 else 3933 Features["apcs"] = true; 3934 3935 StringRef ArchName = getTriple().getArchName(); 3936 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3937 Features["vfp2"] = true; 3938 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3939 CPU == "cortex-a9-mp") { 3940 Features["vfp3"] = true; 3941 Features["neon"] = true; 3942 } 3943 else if (CPU == "cortex-a5") { 3944 Features["vfp4"] = true; 3945 Features["neon"] = true; 3946 } else if (CPU == "swift" || CPU == "cortex-a7" || 3947 CPU == "cortex-a12" || CPU == "cortex-a15" || 3948 CPU == "krait") { 3949 Features["vfp4"] = true; 3950 Features["neon"] = true; 3951 Features["hwdiv"] = true; 3952 Features["hwdiv-arm"] = true; 3953 } else if (CPU == "cyclone") { 3954 Features["v8fp"] = true; 3955 Features["neon"] = true; 3956 Features["hwdiv"] = true; 3957 Features["hwdiv-arm"] = true; 3958 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 3959 Features["fp-armv8"] = true; 3960 Features["neon"] = true; 3961 Features["hwdiv"] = true; 3962 Features["hwdiv-arm"] = true; 3963 Features["crc"] = true; 3964 Features["crypto"] = true; 3965 } else if (CPU == "cortex-r5" || 3966 // Enable the hwdiv extension for all v8a AArch32 cores by 3967 // default. 3968 ArchName == "armv8a" || ArchName == "armv8" || 3969 ArchName == "armebv8a" || ArchName == "armebv8" || 3970 ArchName == "thumbv8a" || ArchName == "thumbv8" || 3971 ArchName == "thumbebv8a" || ArchName == "thumbebv8") { 3972 Features["hwdiv"] = true; 3973 Features["hwdiv-arm"] = true; 3974 } else if (CPU == "cortex-m3" || CPU == "cortex-m4") { 3975 Features["hwdiv"] = true; 3976 } 3977 } 3978 3979 bool handleTargetFeatures(std::vector<std::string> &Features, 3980 DiagnosticsEngine &Diags) override { 3981 FPU = 0; 3982 CRC = 0; 3983 Crypto = 0; 3984 SoftFloat = SoftFloatABI = false; 3985 HWDiv = 0; 3986 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3987 if (Features[i] == "+soft-float") 3988 SoftFloat = true; 3989 else if (Features[i] == "+soft-float-abi") 3990 SoftFloatABI = true; 3991 else if (Features[i] == "+vfp2") 3992 FPU |= VFP2FPU; 3993 else if (Features[i] == "+vfp3") 3994 FPU |= VFP3FPU; 3995 else if (Features[i] == "+vfp4") 3996 FPU |= VFP4FPU; 3997 else if (Features[i] == "+fp-armv8") 3998 FPU |= FPARMV8; 3999 else if (Features[i] == "+neon") 4000 FPU |= NeonFPU; 4001 else if (Features[i] == "+hwdiv") 4002 HWDiv |= HWDivThumb; 4003 else if (Features[i] == "+hwdiv-arm") 4004 HWDiv |= HWDivARM; 4005 else if (Features[i] == "+crc") 4006 CRC = 1; 4007 else if (Features[i] == "+crypto") 4008 Crypto = 1; 4009 } 4010 4011 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4012 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4013 return false; 4014 } 4015 4016 if (FPMath == FP_Neon) 4017 Features.push_back("+neonfp"); 4018 else if (FPMath == FP_VFP) 4019 Features.push_back("-neonfp"); 4020 4021 // Remove front-end specific options which the backend handles differently. 4022 std::vector<std::string>::iterator it; 4023 it = std::find(Features.begin(), Features.end(), "+soft-float"); 4024 if (it != Features.end()) 4025 Features.erase(it); 4026 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4027 if (it != Features.end()) 4028 Features.erase(it); 4029 return true; 4030 } 4031 4032 bool hasFeature(StringRef Feature) const override { 4033 return llvm::StringSwitch<bool>(Feature) 4034 .Case("arm", true) 4035 .Case("softfloat", SoftFloat) 4036 .Case("thumb", IsThumb) 4037 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4038 .Case("hwdiv", HWDiv & HWDivThumb) 4039 .Case("hwdiv-arm", HWDiv & HWDivARM) 4040 .Default(false); 4041 } 4042 // FIXME: Should we actually have some table instead of these switches? 4043 static const char *getCPUDefineSuffix(StringRef Name) { 4044 return llvm::StringSwitch<const char*>(Name) 4045 .Cases("arm8", "arm810", "4") 4046 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 4047 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 4048 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 4049 .Case("ep9312", "4T") 4050 .Cases("arm10tdmi", "arm1020t", "5T") 4051 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 4052 .Case("arm926ej-s", "5TEJ") 4053 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 4054 .Cases("xscale", "iwmmxt", "5TE") 4055 .Case("arm1136j-s", "6J") 4056 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 4057 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 4058 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 4059 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A") 4060 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "7A") 4061 .Cases("cortex-r4", "cortex-r5", "7R") 4062 .Case("swift", "7S") 4063 .Case("cyclone", "8A") 4064 .Cases("cortex-m3", "cortex-m4", "7M") 4065 .Case("cortex-m0", "6M") 4066 .Cases("cortex-a53", "cortex-a57", "8A") 4067 .Default(0); 4068 } 4069 static const char *getCPUProfile(StringRef Name) { 4070 return llvm::StringSwitch<const char*>(Name) 4071 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 4072 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "A") 4073 .Cases("cortex-a53", "cortex-a57", "A") 4074 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 4075 .Cases("cortex-r4", "cortex-r5", "R") 4076 .Default(""); 4077 } 4078 bool setCPU(const std::string &Name) override { 4079 if (!getCPUDefineSuffix(Name)) 4080 return false; 4081 4082 CPU = Name; 4083 return true; 4084 } 4085 bool setFPMath(StringRef Name) override; 4086 void getTargetDefines(const LangOptions &Opts, 4087 MacroBuilder &Builder) const override { 4088 // Target identification. 4089 Builder.defineMacro("__arm"); 4090 Builder.defineMacro("__arm__"); 4091 4092 // Target properties. 4093 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4094 4095 StringRef CPUArch = getCPUDefineSuffix(CPU); 4096 unsigned int CPUArchVer; 4097 if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) { 4098 llvm_unreachable("Invalid char for architecture version number"); 4099 } 4100 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4101 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4102 StringRef CPUProfile = getCPUProfile(CPU); 4103 if (!CPUProfile.empty()) 4104 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 4105 4106 // Subtarget options. 4107 4108 // FIXME: It's more complicated than this and we don't really support 4109 // interworking. 4110 // Windows on ARM does not "support" interworking 4111 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 4112 Builder.defineMacro("__THUMB_INTERWORK__"); 4113 4114 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4115 // Embedded targets on Darwin follow AAPCS, but not EABI. 4116 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4117 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4118 Builder.defineMacro("__ARM_EABI__"); 4119 Builder.defineMacro("__ARM_PCS", "1"); 4120 4121 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4122 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4123 } 4124 4125 if (SoftFloat) 4126 Builder.defineMacro("__SOFTFP__"); 4127 4128 if (CPU == "xscale") 4129 Builder.defineMacro("__XSCALE__"); 4130 4131 if (IsThumb) { 4132 Builder.defineMacro("__THUMBEL__"); 4133 Builder.defineMacro("__thumb__"); 4134 // We check both CPUArchVer and ArchName because when only triple is 4135 // specified, the default CPU is arm1136j-s. 4136 StringRef ArchName = getTriple().getArchName(); 4137 if (CPUArch == "6T2" || CPUArchVer >= 7 || ArchName.endswith("v6t2") || 4138 ArchName.endswith("v7") || ArchName.endswith("v8")) 4139 Builder.defineMacro("__thumb2__"); 4140 } 4141 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4142 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4143 4144 // Note, this is always on in gcc, even though it doesn't make sense. 4145 Builder.defineMacro("__APCS_32__"); 4146 4147 if (FPUModeIsVFP((FPUMode) FPU)) { 4148 Builder.defineMacro("__VFP_FP__"); 4149 if (FPU & VFP2FPU) 4150 Builder.defineMacro("__ARM_VFPV2__"); 4151 if (FPU & VFP3FPU) 4152 Builder.defineMacro("__ARM_VFPV3__"); 4153 if (FPU & VFP4FPU) 4154 Builder.defineMacro("__ARM_VFPV4__"); 4155 } 4156 4157 // This only gets set when Neon instructions are actually available, unlike 4158 // the VFP define, hence the soft float and arch check. This is subtly 4159 // different from gcc, we follow the intent which was that it should be set 4160 // when Neon instructions are actually available. 4161 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4162 Builder.defineMacro("__ARM_NEON"); 4163 Builder.defineMacro("__ARM_NEON__"); 4164 } 4165 4166 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4167 Opts.ShortWChar ? "2" : "4"); 4168 4169 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4170 Opts.ShortEnums ? "1" : "4"); 4171 4172 if (CRC) 4173 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4174 4175 if (Crypto) 4176 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4177 4178 if (CPUArchVer >= 6 && CPUArch != "6M") { 4179 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4180 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4181 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4182 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4183 } 4184 } 4185 void getTargetBuiltins(const Builtin::Info *&Records, 4186 unsigned &NumRecords) const override { 4187 Records = BuiltinInfo; 4188 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4189 } 4190 bool isCLZForZeroUndef() const override { return false; } 4191 BuiltinVaListKind getBuiltinVaListKind() const override { 4192 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4193 } 4194 void getGCCRegNames(const char * const *&Names, 4195 unsigned &NumNames) const override; 4196 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4197 unsigned &NumAliases) const override; 4198 bool validateAsmConstraint(const char *&Name, 4199 TargetInfo::ConstraintInfo &Info) const override { 4200 switch (*Name) { 4201 default: break; 4202 case 'l': // r0-r7 4203 case 'h': // r8-r15 4204 case 'w': // VFP Floating point register single precision 4205 case 'P': // VFP Floating point register double precision 4206 Info.setAllowsRegister(); 4207 return true; 4208 case 'Q': // A memory address that is a single base register. 4209 Info.setAllowsMemory(); 4210 return true; 4211 case 'U': // a memory reference... 4212 switch (Name[1]) { 4213 case 'q': // ...ARMV4 ldrsb 4214 case 'v': // ...VFP load/store (reg+constant offset) 4215 case 'y': // ...iWMMXt load/store 4216 case 't': // address valid for load/store opaque types wider 4217 // than 128-bits 4218 case 'n': // valid address for Neon doubleword vector load/store 4219 case 'm': // valid address for Neon element and structure load/store 4220 case 's': // valid address for non-offset loads/stores of quad-word 4221 // values in four ARM registers 4222 Info.setAllowsMemory(); 4223 Name++; 4224 return true; 4225 } 4226 } 4227 return false; 4228 } 4229 std::string convertConstraint(const char *&Constraint) const override { 4230 std::string R; 4231 switch (*Constraint) { 4232 case 'U': // Two-character constraint; add "^" hint for later parsing. 4233 R = std::string("^") + std::string(Constraint, 2); 4234 Constraint++; 4235 break; 4236 case 'p': // 'p' should be translated to 'r' by default. 4237 R = std::string("r"); 4238 break; 4239 default: 4240 return std::string(1, *Constraint); 4241 } 4242 return R; 4243 } 4244 bool validateConstraintModifier(StringRef Constraint, const char Modifier, 4245 unsigned Size) const override { 4246 bool isOutput = (Constraint[0] == '='); 4247 bool isInOut = (Constraint[0] == '+'); 4248 4249 // Strip off constraint modifiers. 4250 while (Constraint[0] == '=' || 4251 Constraint[0] == '+' || 4252 Constraint[0] == '&') 4253 Constraint = Constraint.substr(1); 4254 4255 switch (Constraint[0]) { 4256 default: break; 4257 case 'r': { 4258 switch (Modifier) { 4259 default: 4260 return (isInOut || isOutput || Size <= 64); 4261 case 'q': 4262 // A register of size 32 cannot fit a vector type. 4263 return false; 4264 } 4265 } 4266 } 4267 4268 return true; 4269 } 4270 const char *getClobbers() const override { 4271 // FIXME: Is this really right? 4272 return ""; 4273 } 4274 4275 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4276 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4277 } 4278 4279 int getEHDataRegisterNumber(unsigned RegNo) const override { 4280 if (RegNo == 0) return 0; 4281 if (RegNo == 1) return 1; 4282 return -1; 4283 } 4284 }; 4285 4286 bool ARMTargetInfo::setFPMath(StringRef Name) { 4287 if (Name == "neon") { 4288 FPMath = FP_Neon; 4289 return true; 4290 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4291 Name == "vfp4") { 4292 FPMath = FP_VFP; 4293 return true; 4294 } 4295 return false; 4296 } 4297 4298 const char * const ARMTargetInfo::GCCRegNames[] = { 4299 // Integer registers 4300 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4301 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4302 4303 // Float registers 4304 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4305 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4306 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4307 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4308 4309 // Double registers 4310 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4311 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4312 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4313 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4314 4315 // Quad registers 4316 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4317 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4318 }; 4319 4320 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4321 unsigned &NumNames) const { 4322 Names = GCCRegNames; 4323 NumNames = llvm::array_lengthof(GCCRegNames); 4324 } 4325 4326 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4327 { { "a1" }, "r0" }, 4328 { { "a2" }, "r1" }, 4329 { { "a3" }, "r2" }, 4330 { { "a4" }, "r3" }, 4331 { { "v1" }, "r4" }, 4332 { { "v2" }, "r5" }, 4333 { { "v3" }, "r6" }, 4334 { { "v4" }, "r7" }, 4335 { { "v5" }, "r8" }, 4336 { { "v6", "rfp" }, "r9" }, 4337 { { "sl" }, "r10" }, 4338 { { "fp" }, "r11" }, 4339 { { "ip" }, "r12" }, 4340 { { "r13" }, "sp" }, 4341 { { "r14" }, "lr" }, 4342 { { "r15" }, "pc" }, 4343 // The S, D and Q registers overlap, but aren't really aliases; we 4344 // don't want to substitute one of these for a different-sized one. 4345 }; 4346 4347 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4348 unsigned &NumAliases) const { 4349 Aliases = GCCRegAliases; 4350 NumAliases = llvm::array_lengthof(GCCRegAliases); 4351 } 4352 4353 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4354 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4355 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4356 ALL_LANGUAGES }, 4357 #include "clang/Basic/BuiltinsNEON.def" 4358 4359 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4360 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4361 ALL_LANGUAGES }, 4362 #include "clang/Basic/BuiltinsARM.def" 4363 }; 4364 4365 class ARMleTargetInfo : public ARMTargetInfo { 4366 public: 4367 ARMleTargetInfo(const llvm::Triple &Triple) 4368 : ARMTargetInfo(Triple, false) { } 4369 virtual void getTargetDefines(const LangOptions &Opts, 4370 MacroBuilder &Builder) const { 4371 Builder.defineMacro("__ARMEL__"); 4372 ARMTargetInfo::getTargetDefines(Opts, Builder); 4373 } 4374 }; 4375 4376 class ARMbeTargetInfo : public ARMTargetInfo { 4377 public: 4378 ARMbeTargetInfo(const llvm::Triple &Triple) 4379 : ARMTargetInfo(Triple, true) { } 4380 virtual void getTargetDefines(const LangOptions &Opts, 4381 MacroBuilder &Builder) const { 4382 Builder.defineMacro("__ARMEB__"); 4383 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4384 ARMTargetInfo::getTargetDefines(Opts, Builder); 4385 } 4386 }; 4387 } // end anonymous namespace. 4388 4389 namespace { 4390 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4391 const llvm::Triple Triple; 4392 public: 4393 WindowsARMTargetInfo(const llvm::Triple &Triple) 4394 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4395 TLSSupported = false; 4396 WCharType = UnsignedShort; 4397 SizeType = UnsignedInt; 4398 UserLabelPrefix = ""; 4399 } 4400 void getVisualStudioDefines(const LangOptions &Opts, 4401 MacroBuilder &Builder) const { 4402 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4403 4404 // FIXME: this is invalid for WindowsCE 4405 Builder.defineMacro("_M_ARM_NT", "1"); 4406 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4407 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4408 4409 assert((Triple.getArch() == llvm::Triple::arm || 4410 Triple.getArch() == llvm::Triple::thumb) && 4411 "invalid architecture for Windows ARM target info"); 4412 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4413 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4414 4415 // TODO map the complete set of values 4416 // 31: VFPv3 40: VFPv4 4417 Builder.defineMacro("_M_ARM_FP", "31"); 4418 } 4419 }; 4420 4421 // Windows ARM + Itanium C++ ABI Target 4422 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4423 public: 4424 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4425 : WindowsARMTargetInfo(Triple) { 4426 TheCXXABI.set(TargetCXXABI::GenericARM); 4427 } 4428 4429 void getTargetDefines(const LangOptions &Opts, 4430 MacroBuilder &Builder) const override { 4431 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4432 4433 if (Opts.MSVCCompat) 4434 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4435 } 4436 }; 4437 4438 // Windows ARM, MS (C++) ABI 4439 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4440 public: 4441 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4442 : WindowsARMTargetInfo(Triple) { 4443 TheCXXABI.set(TargetCXXABI::Microsoft); 4444 } 4445 4446 void getTargetDefines(const LangOptions &Opts, 4447 MacroBuilder &Builder) const override { 4448 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4449 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4450 } 4451 }; 4452 } 4453 4454 4455 namespace { 4456 class DarwinARMTargetInfo : 4457 public DarwinTargetInfo<ARMleTargetInfo> { 4458 protected: 4459 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4460 MacroBuilder &Builder) const override { 4461 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4462 } 4463 4464 public: 4465 DarwinARMTargetInfo(const llvm::Triple &Triple) 4466 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4467 HasAlignMac68kSupport = true; 4468 // iOS always has 64-bit atomic instructions. 4469 // FIXME: This should be based off of the target features in ARMleTargetInfo. 4470 MaxAtomicInlineWidth = 64; 4471 4472 // Darwin on iOS uses a variant of the ARM C++ ABI. 4473 TheCXXABI.set(TargetCXXABI::iOS); 4474 } 4475 }; 4476 } // end anonymous namespace. 4477 4478 4479 namespace { 4480 class ARM64TargetInfo : public TargetInfo { 4481 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4482 static const char *const GCCRegNames[]; 4483 4484 static const Builtin::Info BuiltinInfo[]; 4485 4486 std::string ABI; 4487 4488 public: 4489 ARM64TargetInfo(const llvm::Triple &Triple) 4490 : TargetInfo(Triple), ABI("aapcs") { 4491 BigEndian = false; 4492 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4493 IntMaxType = SignedLong; 4494 UIntMaxType = UnsignedLong; 4495 Int64Type = SignedLong; 4496 WCharType = UnsignedInt; 4497 MaxVectorAlign = 128; 4498 RegParmMax = 8; 4499 MaxAtomicInlineWidth = 128; 4500 MaxAtomicPromoteWidth = 128; 4501 4502 LongDoubleWidth = LongDoubleAlign = 128; 4503 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4504 4505 if (Triple.isOSBinFormatMachO()) 4506 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 4507 else 4508 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 4509 4510 // {} in inline assembly are neon specifiers, not assembly variant 4511 // specifiers. 4512 NoAsmVariants = true; 4513 4514 // ARM64 targets default to using the ARM C++ ABI. 4515 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4516 } 4517 4518 virtual const char *getABI() const { return ABI.c_str(); } 4519 virtual bool setABI(const std::string &Name) { 4520 if (Name != "aapcs" && Name != "darwinpcs") 4521 return false; 4522 4523 ABI = Name; 4524 return true; 4525 } 4526 4527 virtual bool setCPU(const std::string &Name) { 4528 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4529 .Case("arm64-generic", true) 4530 .Case("cyclone", true) 4531 .Default(false); 4532 return CPUKnown; 4533 } 4534 4535 virtual void getTargetDefines(const LangOptions &Opts, 4536 MacroBuilder &Builder) const { 4537 // Target identification. 4538 Builder.defineMacro("__arm64"); 4539 Builder.defineMacro("__arm64__"); 4540 Builder.defineMacro("__aarch64__"); 4541 Builder.defineMacro("__ARM64_ARCH_8__"); 4542 Builder.defineMacro("__AARCH64_SIMD__"); 4543 Builder.defineMacro("__ARM_NEON__"); 4544 4545 // Target properties. 4546 Builder.defineMacro("_LP64"); 4547 Builder.defineMacro("__LP64__"); 4548 Builder.defineMacro("__LITTLE_ENDIAN__"); 4549 4550 // Subtarget options. 4551 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4552 4553 Builder.defineMacro("__aarch64__"); 4554 Builder.defineMacro("__AARCH64EL__"); 4555 4556 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4557 Builder.defineMacro("__ARM_ACLE", "200"); 4558 Builder.defineMacro("__ARM_ARCH", "8"); 4559 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4560 4561 Builder.defineMacro("__ARM_64BIT_STATE"); 4562 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4563 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4564 4565 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4566 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4567 Builder.defineMacro("__ARM_FEATURE_FMA"); 4568 Builder.defineMacro("__ARM_FEATURE_DIV"); 4569 4570 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 4571 4572 // 0xe implies support for half, single and double precision operations. 4573 Builder.defineMacro("__ARM_FP", "0xe"); 4574 4575 // PCS specifies this for SysV variants, which is all we support. Other ABIs 4576 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 4577 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 4578 4579 if (Opts.FastMath || Opts.FiniteMathOnly) 4580 Builder.defineMacro("__ARM_FP_FAST"); 4581 4582 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 4583 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 4584 4585 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 4586 4587 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4588 Opts.ShortEnums ? "1" : "4"); 4589 4590 if (BigEndian) 4591 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4592 4593 // FIXME: the target should support NEON as an optional extension, like 4594 // the OSS AArch64. 4595 Builder.defineMacro("__ARM_NEON"); 4596 // 64-bit NEON supports half, single and double precision operations. 4597 Builder.defineMacro("__ARM_NEON_FP", "7"); 4598 4599 // FIXME: the target should support crypto as an optional extension, like 4600 // the OSS AArch64 4601 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4602 } 4603 4604 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4605 unsigned &NumRecords) const { 4606 Records = BuiltinInfo; 4607 NumRecords = clang::ARM64::LastTSBuiltin - Builtin::FirstTSBuiltin; 4608 } 4609 4610 virtual bool hasFeature(StringRef Feature) const { 4611 return llvm::StringSwitch<bool>(Feature) 4612 .Case("arm64", true) 4613 .Case("neon", true) 4614 .Default(false); 4615 } 4616 4617 virtual bool isCLZForZeroUndef() const { return false; } 4618 4619 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4620 return TargetInfo::AArch64ABIBuiltinVaList; 4621 } 4622 4623 virtual void getGCCRegNames(const char *const *&Names, 4624 unsigned &NumNames) const; 4625 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4626 unsigned &NumAliases) const; 4627 4628 virtual bool validateAsmConstraint(const char *&Name, 4629 TargetInfo::ConstraintInfo &Info) const { 4630 switch (*Name) { 4631 default: 4632 return false; 4633 case 'w': // Floating point and SIMD registers (V0-V31) 4634 Info.setAllowsRegister(); 4635 return true; 4636 case 'z': // Zero register, wzr or xzr 4637 Info.setAllowsRegister(); 4638 return true; 4639 case 'x': // Floating point and SIMD registers (V0-V15) 4640 Info.setAllowsRegister(); 4641 return true; 4642 case 'Q': // A memory address that is a single base register. 4643 Info.setAllowsMemory(); 4644 return true; 4645 } 4646 return false; 4647 } 4648 4649 virtual bool validateConstraintModifier(StringRef Constraint, 4650 const char Modifier, 4651 unsigned Size) const { 4652 // Strip off constraint modifiers. 4653 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 4654 Constraint = Constraint.substr(1); 4655 4656 switch (Constraint[0]) { 4657 default: 4658 return true; 4659 case 'z': 4660 case 'r': { 4661 switch (Modifier) { 4662 case 'x': 4663 case 'w': 4664 // For now assume that the person knows what they're 4665 // doing with the modifier. 4666 return true; 4667 default: 4668 // By default an 'r' constraint will be in the 'x' 4669 // registers. 4670 return (Size == 64); 4671 } 4672 } 4673 } 4674 } 4675 4676 virtual const char *getClobbers() const { return ""; } 4677 4678 int getEHDataRegisterNumber(unsigned RegNo) const { 4679 if (RegNo == 0) 4680 return 0; 4681 if (RegNo == 1) 4682 return 1; 4683 return -1; 4684 } 4685 }; 4686 4687 const char *const ARM64TargetInfo::GCCRegNames[] = { 4688 // 32-bit Integer registers 4689 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 4690 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 4691 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 4692 4693 // 64-bit Integer registers 4694 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 4695 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 4696 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 4697 4698 // 32-bit floating point regsisters 4699 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 4700 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 4701 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4702 4703 // 64-bit floating point regsisters 4704 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 4705 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 4706 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4707 4708 // Vector registers 4709 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 4710 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 4711 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 4712 }; 4713 4714 void ARM64TargetInfo::getGCCRegNames(const char *const *&Names, 4715 unsigned &NumNames) const { 4716 Names = GCCRegNames; 4717 NumNames = llvm::array_lengthof(GCCRegNames); 4718 } 4719 4720 const TargetInfo::GCCRegAlias ARM64TargetInfo::GCCRegAliases[] = { 4721 { { "w31" }, "wsp" }, 4722 { { "x29" }, "fp" }, 4723 { { "x30" }, "lr" }, 4724 { { "x31" }, "sp" }, 4725 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 4726 // don't want to substitute one of these for a different-sized one. 4727 }; 4728 4729 void ARM64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4730 unsigned &NumAliases) const { 4731 Aliases = GCCRegAliases; 4732 NumAliases = llvm::array_lengthof(GCCRegAliases); 4733 } 4734 4735 const Builtin::Info ARM64TargetInfo::BuiltinInfo[] = { 4736 #define BUILTIN(ID, TYPE, ATTRS) \ 4737 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4738 #include "clang/Basic/BuiltinsNEON.def" 4739 4740 #define BUILTIN(ID, TYPE, ATTRS) \ 4741 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4742 #include "clang/Basic/BuiltinsARM64.def" 4743 }; 4744 } // end anonymous namespace. 4745 4746 namespace { 4747 class DarwinARM64TargetInfo : public DarwinTargetInfo<ARM64TargetInfo> { 4748 public: 4749 DarwinARM64TargetInfo(const llvm::Triple &Triple) 4750 : DarwinTargetInfo<ARM64TargetInfo>(Triple) { 4751 Int64Type = SignedLongLong; 4752 WCharType = SignedInt; 4753 UseSignedCharForObjCBool = false; 4754 4755 LongDoubleWidth = LongDoubleAlign = 64; 4756 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4757 4758 TheCXXABI.set(TargetCXXABI::iOS64); 4759 } 4760 4761 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4762 return TargetInfo::CharPtrBuiltinVaList; 4763 } 4764 }; 4765 } // end anonymous namespace 4766 4767 namespace { 4768 // Hexagon abstract base class 4769 class HexagonTargetInfo : public TargetInfo { 4770 static const Builtin::Info BuiltinInfo[]; 4771 static const char * const GCCRegNames[]; 4772 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4773 std::string CPU; 4774 public: 4775 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4776 BigEndian = false; 4777 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 4778 4779 // {} in inline assembly are packet specifiers, not assembly variant 4780 // specifiers. 4781 NoAsmVariants = true; 4782 } 4783 4784 void getTargetBuiltins(const Builtin::Info *&Records, 4785 unsigned &NumRecords) const override { 4786 Records = BuiltinInfo; 4787 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4788 } 4789 4790 bool validateAsmConstraint(const char *&Name, 4791 TargetInfo::ConstraintInfo &Info) const override { 4792 return true; 4793 } 4794 4795 void getTargetDefines(const LangOptions &Opts, 4796 MacroBuilder &Builder) const override; 4797 4798 bool hasFeature(StringRef Feature) const override { 4799 return Feature == "hexagon"; 4800 } 4801 4802 BuiltinVaListKind getBuiltinVaListKind() const override { 4803 return TargetInfo::CharPtrBuiltinVaList; 4804 } 4805 void getGCCRegNames(const char * const *&Names, 4806 unsigned &NumNames) const override; 4807 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4808 unsigned &NumAliases) const override; 4809 const char *getClobbers() const override { 4810 return ""; 4811 } 4812 4813 static const char *getHexagonCPUSuffix(StringRef Name) { 4814 return llvm::StringSwitch<const char*>(Name) 4815 .Case("hexagonv4", "4") 4816 .Case("hexagonv5", "5") 4817 .Default(0); 4818 } 4819 4820 bool setCPU(const std::string &Name) override { 4821 if (!getHexagonCPUSuffix(Name)) 4822 return false; 4823 4824 CPU = Name; 4825 return true; 4826 } 4827 }; 4828 4829 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4830 MacroBuilder &Builder) const { 4831 Builder.defineMacro("qdsp6"); 4832 Builder.defineMacro("__qdsp6", "1"); 4833 Builder.defineMacro("__qdsp6__", "1"); 4834 4835 Builder.defineMacro("hexagon"); 4836 Builder.defineMacro("__hexagon", "1"); 4837 Builder.defineMacro("__hexagon__", "1"); 4838 4839 if(CPU == "hexagonv1") { 4840 Builder.defineMacro("__HEXAGON_V1__"); 4841 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4842 if(Opts.HexagonQdsp6Compat) { 4843 Builder.defineMacro("__QDSP6_V1__"); 4844 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4845 } 4846 } 4847 else if(CPU == "hexagonv2") { 4848 Builder.defineMacro("__HEXAGON_V2__"); 4849 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4850 if(Opts.HexagonQdsp6Compat) { 4851 Builder.defineMacro("__QDSP6_V2__"); 4852 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4853 } 4854 } 4855 else if(CPU == "hexagonv3") { 4856 Builder.defineMacro("__HEXAGON_V3__"); 4857 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4858 if(Opts.HexagonQdsp6Compat) { 4859 Builder.defineMacro("__QDSP6_V3__"); 4860 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4861 } 4862 } 4863 else if(CPU == "hexagonv4") { 4864 Builder.defineMacro("__HEXAGON_V4__"); 4865 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4866 if(Opts.HexagonQdsp6Compat) { 4867 Builder.defineMacro("__QDSP6_V4__"); 4868 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4869 } 4870 } 4871 else if(CPU == "hexagonv5") { 4872 Builder.defineMacro("__HEXAGON_V5__"); 4873 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4874 if(Opts.HexagonQdsp6Compat) { 4875 Builder.defineMacro("__QDSP6_V5__"); 4876 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4877 } 4878 } 4879 } 4880 4881 const char * const HexagonTargetInfo::GCCRegNames[] = { 4882 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4883 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4884 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4885 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4886 "p0", "p1", "p2", "p3", 4887 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4888 }; 4889 4890 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4891 unsigned &NumNames) const { 4892 Names = GCCRegNames; 4893 NumNames = llvm::array_lengthof(GCCRegNames); 4894 } 4895 4896 4897 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4898 { { "sp" }, "r29" }, 4899 { { "fp" }, "r30" }, 4900 { { "lr" }, "r31" }, 4901 }; 4902 4903 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4904 unsigned &NumAliases) const { 4905 Aliases = GCCRegAliases; 4906 NumAliases = llvm::array_lengthof(GCCRegAliases); 4907 } 4908 4909 4910 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4911 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4912 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4913 ALL_LANGUAGES }, 4914 #include "clang/Basic/BuiltinsHexagon.def" 4915 }; 4916 } 4917 4918 4919 namespace { 4920 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4921 class SparcTargetInfo : public TargetInfo { 4922 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4923 static const char * const GCCRegNames[]; 4924 bool SoftFloat; 4925 public: 4926 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4927 4928 bool handleTargetFeatures(std::vector<std::string> &Features, 4929 DiagnosticsEngine &Diags) override { 4930 SoftFloat = false; 4931 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4932 if (Features[i] == "+soft-float") 4933 SoftFloat = true; 4934 return true; 4935 } 4936 void getTargetDefines(const LangOptions &Opts, 4937 MacroBuilder &Builder) const override { 4938 DefineStd(Builder, "sparc", Opts); 4939 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4940 4941 if (SoftFloat) 4942 Builder.defineMacro("SOFT_FLOAT", "1"); 4943 } 4944 4945 bool hasFeature(StringRef Feature) const override { 4946 return llvm::StringSwitch<bool>(Feature) 4947 .Case("softfloat", SoftFloat) 4948 .Case("sparc", true) 4949 .Default(false); 4950 } 4951 4952 void getTargetBuiltins(const Builtin::Info *&Records, 4953 unsigned &NumRecords) const override { 4954 // FIXME: Implement! 4955 } 4956 BuiltinVaListKind getBuiltinVaListKind() const override { 4957 return TargetInfo::VoidPtrBuiltinVaList; 4958 } 4959 void getGCCRegNames(const char * const *&Names, 4960 unsigned &NumNames) const override; 4961 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4962 unsigned &NumAliases) const override; 4963 bool validateAsmConstraint(const char *&Name, 4964 TargetInfo::ConstraintInfo &info) const override { 4965 // FIXME: Implement! 4966 return false; 4967 } 4968 const char *getClobbers() const override { 4969 // FIXME: Implement! 4970 return ""; 4971 } 4972 }; 4973 4974 const char * const SparcTargetInfo::GCCRegNames[] = { 4975 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4976 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4977 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4978 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4979 }; 4980 4981 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4982 unsigned &NumNames) const { 4983 Names = GCCRegNames; 4984 NumNames = llvm::array_lengthof(GCCRegNames); 4985 } 4986 4987 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4988 { { "g0" }, "r0" }, 4989 { { "g1" }, "r1" }, 4990 { { "g2" }, "r2" }, 4991 { { "g3" }, "r3" }, 4992 { { "g4" }, "r4" }, 4993 { { "g5" }, "r5" }, 4994 { { "g6" }, "r6" }, 4995 { { "g7" }, "r7" }, 4996 { { "o0" }, "r8" }, 4997 { { "o1" }, "r9" }, 4998 { { "o2" }, "r10" }, 4999 { { "o3" }, "r11" }, 5000 { { "o4" }, "r12" }, 5001 { { "o5" }, "r13" }, 5002 { { "o6", "sp" }, "r14" }, 5003 { { "o7" }, "r15" }, 5004 { { "l0" }, "r16" }, 5005 { { "l1" }, "r17" }, 5006 { { "l2" }, "r18" }, 5007 { { "l3" }, "r19" }, 5008 { { "l4" }, "r20" }, 5009 { { "l5" }, "r21" }, 5010 { { "l6" }, "r22" }, 5011 { { "l7" }, "r23" }, 5012 { { "i0" }, "r24" }, 5013 { { "i1" }, "r25" }, 5014 { { "i2" }, "r26" }, 5015 { { "i3" }, "r27" }, 5016 { { "i4" }, "r28" }, 5017 { { "i5" }, "r29" }, 5018 { { "i6", "fp" }, "r30" }, 5019 { { "i7" }, "r31" }, 5020 }; 5021 5022 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5023 unsigned &NumAliases) const { 5024 Aliases = GCCRegAliases; 5025 NumAliases = llvm::array_lengthof(GCCRegAliases); 5026 } 5027 5028 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5029 class SparcV8TargetInfo : public SparcTargetInfo { 5030 public: 5031 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5032 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5033 } 5034 5035 void getTargetDefines(const LangOptions &Opts, 5036 MacroBuilder &Builder) const override { 5037 SparcTargetInfo::getTargetDefines(Opts, Builder); 5038 Builder.defineMacro("__sparcv8"); 5039 } 5040 }; 5041 5042 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5043 class SparcV9TargetInfo : public SparcTargetInfo { 5044 public: 5045 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5046 // FIXME: Support Sparc quad-precision long double? 5047 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5048 // This is an LP64 platform. 5049 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5050 5051 // OpenBSD uses long long for int64_t and intmax_t. 5052 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 5053 IntMaxType = SignedLongLong; 5054 UIntMaxType = UnsignedLongLong; 5055 } else { 5056 IntMaxType = SignedLong; 5057 UIntMaxType = UnsignedLong; 5058 } 5059 Int64Type = IntMaxType; 5060 5061 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5062 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5063 LongDoubleWidth = 128; 5064 LongDoubleAlign = 128; 5065 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5066 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5067 } 5068 5069 void getTargetDefines(const LangOptions &Opts, 5070 MacroBuilder &Builder) const override { 5071 SparcTargetInfo::getTargetDefines(Opts, Builder); 5072 Builder.defineMacro("__sparcv9"); 5073 Builder.defineMacro("__arch64__"); 5074 // Solaris and its derivative AuroraUX don't need these variants, but the 5075 // BSDs do. 5076 if (getTriple().getOS() != llvm::Triple::Solaris && 5077 getTriple().getOS() != llvm::Triple::AuroraUX) { 5078 Builder.defineMacro("__sparc64__"); 5079 Builder.defineMacro("__sparc_v9__"); 5080 Builder.defineMacro("__sparcv9__"); 5081 } 5082 } 5083 5084 bool setCPU(const std::string &Name) override { 5085 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5086 .Case("v9", true) 5087 .Case("ultrasparc", true) 5088 .Case("ultrasparc3", true) 5089 .Case("niagara", true) 5090 .Case("niagara2", true) 5091 .Case("niagara3", true) 5092 .Case("niagara4", true) 5093 .Default(false); 5094 5095 // No need to store the CPU yet. There aren't any CPU-specific 5096 // macros to define. 5097 return CPUKnown; 5098 } 5099 }; 5100 5101 } // end anonymous namespace. 5102 5103 namespace { 5104 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 5105 public: 5106 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 5107 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 5108 SizeType = UnsignedInt; 5109 PtrDiffType = SignedInt; 5110 } 5111 }; 5112 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 5113 public: 5114 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 5115 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 5116 SizeType = UnsignedInt; 5117 PtrDiffType = SignedInt; 5118 } 5119 }; 5120 } // end anonymous namespace. 5121 5122 namespace { 5123 class SystemZTargetInfo : public TargetInfo { 5124 static const char *const GCCRegNames[]; 5125 5126 public: 5127 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5128 TLSSupported = true; 5129 IntWidth = IntAlign = 32; 5130 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5131 PointerWidth = PointerAlign = 64; 5132 LongDoubleWidth = 128; 5133 LongDoubleAlign = 64; 5134 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5135 MinGlobalAlign = 16; 5136 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5137 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5138 } 5139 void getTargetDefines(const LangOptions &Opts, 5140 MacroBuilder &Builder) const override { 5141 Builder.defineMacro("__s390__"); 5142 Builder.defineMacro("__s390x__"); 5143 Builder.defineMacro("__zarch__"); 5144 Builder.defineMacro("__LONG_DOUBLE_128__"); 5145 } 5146 void getTargetBuiltins(const Builtin::Info *&Records, 5147 unsigned &NumRecords) const override { 5148 // FIXME: Implement. 5149 Records = 0; 5150 NumRecords = 0; 5151 } 5152 5153 void getGCCRegNames(const char *const *&Names, 5154 unsigned &NumNames) const override; 5155 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5156 unsigned &NumAliases) const override { 5157 // No aliases. 5158 Aliases = 0; 5159 NumAliases = 0; 5160 } 5161 bool validateAsmConstraint(const char *&Name, 5162 TargetInfo::ConstraintInfo &info) const override; 5163 const char *getClobbers() const override { 5164 // FIXME: Is this really right? 5165 return ""; 5166 } 5167 BuiltinVaListKind getBuiltinVaListKind() const override { 5168 return TargetInfo::SystemZBuiltinVaList; 5169 } 5170 bool setCPU(const std::string &Name) override { 5171 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5172 .Case("z10", true) 5173 .Case("z196", true) 5174 .Case("zEC12", true) 5175 .Default(false); 5176 5177 // No need to store the CPU yet. There aren't any CPU-specific 5178 // macros to define. 5179 return CPUKnown; 5180 } 5181 }; 5182 5183 const char *const SystemZTargetInfo::GCCRegNames[] = { 5184 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5185 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5186 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5187 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5188 }; 5189 5190 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5191 unsigned &NumNames) const { 5192 Names = GCCRegNames; 5193 NumNames = llvm::array_lengthof(GCCRegNames); 5194 } 5195 5196 bool SystemZTargetInfo:: 5197 validateAsmConstraint(const char *&Name, 5198 TargetInfo::ConstraintInfo &Info) const { 5199 switch (*Name) { 5200 default: 5201 return false; 5202 5203 case 'a': // Address register 5204 case 'd': // Data register (equivalent to 'r') 5205 case 'f': // Floating-point register 5206 Info.setAllowsRegister(); 5207 return true; 5208 5209 case 'I': // Unsigned 8-bit constant 5210 case 'J': // Unsigned 12-bit constant 5211 case 'K': // Signed 16-bit constant 5212 case 'L': // Signed 20-bit displacement (on all targets we support) 5213 case 'M': // 0x7fffffff 5214 return true; 5215 5216 case 'Q': // Memory with base and unsigned 12-bit displacement 5217 case 'R': // Likewise, plus an index 5218 case 'S': // Memory with base and signed 20-bit displacement 5219 case 'T': // Likewise, plus an index 5220 Info.setAllowsMemory(); 5221 return true; 5222 } 5223 } 5224 } 5225 5226 namespace { 5227 class MSP430TargetInfo : public TargetInfo { 5228 static const char * const GCCRegNames[]; 5229 public: 5230 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5231 BigEndian = false; 5232 TLSSupported = false; 5233 IntWidth = 16; IntAlign = 16; 5234 LongWidth = 32; LongLongWidth = 64; 5235 LongAlign = LongLongAlign = 16; 5236 PointerWidth = 16; PointerAlign = 16; 5237 SuitableAlign = 16; 5238 SizeType = UnsignedInt; 5239 IntMaxType = SignedLongLong; 5240 UIntMaxType = UnsignedLongLong; 5241 IntPtrType = SignedInt; 5242 PtrDiffType = SignedInt; 5243 SigAtomicType = SignedLong; 5244 DescriptionString = "e-m:e-p:16:16-i32:16:32-n8:16"; 5245 } 5246 void getTargetDefines(const LangOptions &Opts, 5247 MacroBuilder &Builder) const override { 5248 Builder.defineMacro("MSP430"); 5249 Builder.defineMacro("__MSP430__"); 5250 // FIXME: defines for different 'flavours' of MCU 5251 } 5252 void getTargetBuiltins(const Builtin::Info *&Records, 5253 unsigned &NumRecords) const override { 5254 // FIXME: Implement. 5255 Records = 0; 5256 NumRecords = 0; 5257 } 5258 bool hasFeature(StringRef Feature) const override { 5259 return Feature == "msp430"; 5260 } 5261 void getGCCRegNames(const char * const *&Names, 5262 unsigned &NumNames) const override; 5263 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5264 unsigned &NumAliases) const override { 5265 // No aliases. 5266 Aliases = 0; 5267 NumAliases = 0; 5268 } 5269 bool validateAsmConstraint(const char *&Name, 5270 TargetInfo::ConstraintInfo &info) const override { 5271 // No target constraints for now. 5272 return false; 5273 } 5274 const char *getClobbers() const override { 5275 // FIXME: Is this really right? 5276 return ""; 5277 } 5278 BuiltinVaListKind getBuiltinVaListKind() const override { 5279 // FIXME: implement 5280 return TargetInfo::CharPtrBuiltinVaList; 5281 } 5282 }; 5283 5284 const char * const MSP430TargetInfo::GCCRegNames[] = { 5285 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5286 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5287 }; 5288 5289 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5290 unsigned &NumNames) const { 5291 Names = GCCRegNames; 5292 NumNames = llvm::array_lengthof(GCCRegNames); 5293 } 5294 } 5295 5296 namespace { 5297 5298 // LLVM and Clang cannot be used directly to output native binaries for 5299 // target, but is used to compile C code to llvm bitcode with correct 5300 // type and alignment information. 5301 // 5302 // TCE uses the llvm bitcode as input and uses it for generating customized 5303 // target processor and program binary. TCE co-design environment is 5304 // publicly available in http://tce.cs.tut.fi 5305 5306 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5307 3, // opencl_global 5308 4, // opencl_local 5309 5, // opencl_constant 5310 0, // cuda_device 5311 0, // cuda_constant 5312 0 // cuda_shared 5313 }; 5314 5315 class TCETargetInfo : public TargetInfo{ 5316 public: 5317 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5318 TLSSupported = false; 5319 IntWidth = 32; 5320 LongWidth = LongLongWidth = 32; 5321 PointerWidth = 32; 5322 IntAlign = 32; 5323 LongAlign = LongLongAlign = 32; 5324 PointerAlign = 32; 5325 SuitableAlign = 32; 5326 SizeType = UnsignedInt; 5327 IntMaxType = SignedLong; 5328 UIntMaxType = UnsignedLong; 5329 IntPtrType = SignedInt; 5330 PtrDiffType = SignedInt; 5331 FloatWidth = 32; 5332 FloatAlign = 32; 5333 DoubleWidth = 32; 5334 DoubleAlign = 32; 5335 LongDoubleWidth = 32; 5336 LongDoubleAlign = 32; 5337 FloatFormat = &llvm::APFloat::IEEEsingle; 5338 DoubleFormat = &llvm::APFloat::IEEEsingle; 5339 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5340 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5341 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5342 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5343 UseAddrSpaceMapMangling = true; 5344 } 5345 5346 void getTargetDefines(const LangOptions &Opts, 5347 MacroBuilder &Builder) const override { 5348 DefineStd(Builder, "tce", Opts); 5349 Builder.defineMacro("__TCE__"); 5350 Builder.defineMacro("__TCE_V1__"); 5351 } 5352 bool hasFeature(StringRef Feature) const override { 5353 return Feature == "tce"; 5354 } 5355 5356 void getTargetBuiltins(const Builtin::Info *&Records, 5357 unsigned &NumRecords) const override {} 5358 const char *getClobbers() const override { 5359 return ""; 5360 } 5361 BuiltinVaListKind getBuiltinVaListKind() const override { 5362 return TargetInfo::VoidPtrBuiltinVaList; 5363 } 5364 void getGCCRegNames(const char * const *&Names, 5365 unsigned &NumNames) const override {} 5366 bool validateAsmConstraint(const char *&Name, 5367 TargetInfo::ConstraintInfo &info) const override{ 5368 return true; 5369 } 5370 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5371 unsigned &NumAliases) const override {} 5372 }; 5373 } 5374 5375 namespace { 5376 class MipsTargetInfoBase : public TargetInfo { 5377 virtual void setDescriptionString() = 0; 5378 5379 static const Builtin::Info BuiltinInfo[]; 5380 std::string CPU; 5381 bool IsMips16; 5382 bool IsMicromips; 5383 bool IsNan2008; 5384 bool IsSingleFloat; 5385 enum MipsFloatABI { 5386 HardFloat, SoftFloat 5387 } FloatABI; 5388 enum DspRevEnum { 5389 NoDSP, DSP1, DSP2 5390 } DspRev; 5391 bool HasMSA; 5392 5393 protected: 5394 bool HasFP64; 5395 std::string ABI; 5396 5397 public: 5398 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5399 const std::string &CPUStr) 5400 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5401 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5402 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 5403 5404 const char *getABI() const override { return ABI.c_str(); } 5405 bool setABI(const std::string &Name) override = 0; 5406 bool setCPU(const std::string &Name) override { 5407 CPU = Name; 5408 return true; 5409 } 5410 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5411 // The backend enables certain ABI's by default according to the 5412 // architecture. 5413 // Disable both possible defaults so that we don't end up with multiple 5414 // ABI's selected and trigger an assertion. 5415 Features["o32"] = false; 5416 Features["n64"] = false; 5417 5418 Features[ABI] = true; 5419 Features[CPU] = true; 5420 } 5421 5422 void getTargetDefines(const LangOptions &Opts, 5423 MacroBuilder &Builder) const override { 5424 Builder.defineMacro("__mips__"); 5425 Builder.defineMacro("_mips"); 5426 if (Opts.GNUMode) 5427 Builder.defineMacro("mips"); 5428 5429 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5430 5431 switch (FloatABI) { 5432 case HardFloat: 5433 Builder.defineMacro("__mips_hard_float", Twine(1)); 5434 break; 5435 case SoftFloat: 5436 Builder.defineMacro("__mips_soft_float", Twine(1)); 5437 break; 5438 } 5439 5440 if (IsSingleFloat) 5441 Builder.defineMacro("__mips_single_float", Twine(1)); 5442 5443 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5444 Builder.defineMacro("_MIPS_FPSET", 5445 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5446 5447 if (IsMips16) 5448 Builder.defineMacro("__mips16", Twine(1)); 5449 5450 if (IsMicromips) 5451 Builder.defineMacro("__mips_micromips", Twine(1)); 5452 5453 if (IsNan2008) 5454 Builder.defineMacro("__mips_nan2008", Twine(1)); 5455 5456 switch (DspRev) { 5457 default: 5458 break; 5459 case DSP1: 5460 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5461 Builder.defineMacro("__mips_dsp", Twine(1)); 5462 break; 5463 case DSP2: 5464 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5465 Builder.defineMacro("__mips_dspr2", Twine(1)); 5466 Builder.defineMacro("__mips_dsp", Twine(1)); 5467 break; 5468 } 5469 5470 if (HasMSA) 5471 Builder.defineMacro("__mips_msa", Twine(1)); 5472 5473 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5474 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5475 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5476 5477 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5478 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5479 } 5480 5481 void getTargetBuiltins(const Builtin::Info *&Records, 5482 unsigned &NumRecords) const override { 5483 Records = BuiltinInfo; 5484 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5485 } 5486 bool hasFeature(StringRef Feature) const override { 5487 return llvm::StringSwitch<bool>(Feature) 5488 .Case("mips", true) 5489 .Case("fp64", HasFP64) 5490 .Default(false); 5491 } 5492 BuiltinVaListKind getBuiltinVaListKind() const override { 5493 return TargetInfo::VoidPtrBuiltinVaList; 5494 } 5495 void getGCCRegNames(const char * const *&Names, 5496 unsigned &NumNames) const override { 5497 static const char *const GCCRegNames[] = { 5498 // CPU register names 5499 // Must match second column of GCCRegAliases 5500 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5501 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5502 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5503 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5504 // Floating point register names 5505 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5506 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5507 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5508 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5509 // Hi/lo and condition register names 5510 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5511 "$fcc5","$fcc6","$fcc7", 5512 // MSA register names 5513 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5514 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5515 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5516 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5517 // MSA control register names 5518 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5519 "$msarequest", "$msamap", "$msaunmap" 5520 }; 5521 Names = GCCRegNames; 5522 NumNames = llvm::array_lengthof(GCCRegNames); 5523 } 5524 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5525 unsigned &NumAliases) const override = 0; 5526 bool validateAsmConstraint(const char *&Name, 5527 TargetInfo::ConstraintInfo &Info) const override { 5528 switch (*Name) { 5529 default: 5530 return false; 5531 5532 case 'r': // CPU registers. 5533 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5534 case 'y': // Equivalent to "r", backwards compatibility only. 5535 case 'f': // floating-point registers. 5536 case 'c': // $25 for indirect jumps 5537 case 'l': // lo register 5538 case 'x': // hilo register pair 5539 Info.setAllowsRegister(); 5540 return true; 5541 case 'R': // An address that can be used in a non-macro load or store 5542 Info.setAllowsMemory(); 5543 return true; 5544 } 5545 } 5546 5547 const char *getClobbers() const override { 5548 // FIXME: Implement! 5549 return ""; 5550 } 5551 5552 bool handleTargetFeatures(std::vector<std::string> &Features, 5553 DiagnosticsEngine &Diags) override { 5554 IsMips16 = false; 5555 IsMicromips = false; 5556 IsNan2008 = false; 5557 IsSingleFloat = false; 5558 FloatABI = HardFloat; 5559 DspRev = NoDSP; 5560 HasFP64 = ABI == "n32" || ABI == "n64" || ABI == "64"; 5561 5562 for (std::vector<std::string>::iterator it = Features.begin(), 5563 ie = Features.end(); it != ie; ++it) { 5564 if (*it == "+single-float") 5565 IsSingleFloat = true; 5566 else if (*it == "+soft-float") 5567 FloatABI = SoftFloat; 5568 else if (*it == "+mips16") 5569 IsMips16 = true; 5570 else if (*it == "+micromips") 5571 IsMicromips = true; 5572 else if (*it == "+dsp") 5573 DspRev = std::max(DspRev, DSP1); 5574 else if (*it == "+dspr2") 5575 DspRev = std::max(DspRev, DSP2); 5576 else if (*it == "+msa") 5577 HasMSA = true; 5578 else if (*it == "+fp64") 5579 HasFP64 = true; 5580 else if (*it == "-fp64") 5581 HasFP64 = false; 5582 else if (*it == "+nan2008") 5583 IsNan2008 = true; 5584 } 5585 5586 // Remove front-end specific options. 5587 std::vector<std::string>::iterator it = 5588 std::find(Features.begin(), Features.end(), "+soft-float"); 5589 if (it != Features.end()) 5590 Features.erase(it); 5591 it = std::find(Features.begin(), Features.end(), "+nan2008"); 5592 if (it != Features.end()) 5593 Features.erase(it); 5594 5595 setDescriptionString(); 5596 5597 return true; 5598 } 5599 5600 int getEHDataRegisterNumber(unsigned RegNo) const override { 5601 if (RegNo == 0) return 4; 5602 if (RegNo == 1) return 5; 5603 return -1; 5604 } 5605 }; 5606 5607 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5608 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5609 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5610 ALL_LANGUAGES }, 5611 #include "clang/Basic/BuiltinsMips.def" 5612 }; 5613 5614 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5615 public: 5616 Mips32TargetInfoBase(const llvm::Triple &Triple) 5617 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 5618 SizeType = UnsignedInt; 5619 PtrDiffType = SignedInt; 5620 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5621 } 5622 bool setABI(const std::string &Name) override { 5623 if ((Name == "o32") || (Name == "eabi")) { 5624 ABI = Name; 5625 return true; 5626 } else if (Name == "32") { 5627 ABI = "o32"; 5628 return true; 5629 } else 5630 return false; 5631 } 5632 void getTargetDefines(const LangOptions &Opts, 5633 MacroBuilder &Builder) const override { 5634 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5635 5636 Builder.defineMacro("__mips", "32"); 5637 5638 if (ABI == "o32") { 5639 Builder.defineMacro("__mips_o32"); 5640 Builder.defineMacro("_ABIO32", "1"); 5641 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5642 } 5643 else if (ABI == "eabi") 5644 Builder.defineMacro("__mips_eabi"); 5645 else 5646 llvm_unreachable("Invalid ABI for Mips32."); 5647 } 5648 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5649 unsigned &NumAliases) const override { 5650 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5651 { { "at" }, "$1" }, 5652 { { "v0" }, "$2" }, 5653 { { "v1" }, "$3" }, 5654 { { "a0" }, "$4" }, 5655 { { "a1" }, "$5" }, 5656 { { "a2" }, "$6" }, 5657 { { "a3" }, "$7" }, 5658 { { "t0" }, "$8" }, 5659 { { "t1" }, "$9" }, 5660 { { "t2" }, "$10" }, 5661 { { "t3" }, "$11" }, 5662 { { "t4" }, "$12" }, 5663 { { "t5" }, "$13" }, 5664 { { "t6" }, "$14" }, 5665 { { "t7" }, "$15" }, 5666 { { "s0" }, "$16" }, 5667 { { "s1" }, "$17" }, 5668 { { "s2" }, "$18" }, 5669 { { "s3" }, "$19" }, 5670 { { "s4" }, "$20" }, 5671 { { "s5" }, "$21" }, 5672 { { "s6" }, "$22" }, 5673 { { "s7" }, "$23" }, 5674 { { "t8" }, "$24" }, 5675 { { "t9" }, "$25" }, 5676 { { "k0" }, "$26" }, 5677 { { "k1" }, "$27" }, 5678 { { "gp" }, "$28" }, 5679 { { "sp","$sp" }, "$29" }, 5680 { { "fp","$fp" }, "$30" }, 5681 { { "ra" }, "$31" } 5682 }; 5683 Aliases = GCCRegAliases; 5684 NumAliases = llvm::array_lengthof(GCCRegAliases); 5685 } 5686 }; 5687 5688 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5689 void setDescriptionString() override { 5690 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5691 } 5692 5693 public: 5694 Mips32EBTargetInfo(const llvm::Triple &Triple) 5695 : Mips32TargetInfoBase(Triple) { 5696 } 5697 void getTargetDefines(const LangOptions &Opts, 5698 MacroBuilder &Builder) const override { 5699 DefineStd(Builder, "MIPSEB", Opts); 5700 Builder.defineMacro("_MIPSEB"); 5701 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5702 } 5703 }; 5704 5705 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5706 void setDescriptionString() override { 5707 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5708 } 5709 5710 public: 5711 Mips32ELTargetInfo(const llvm::Triple &Triple) 5712 : Mips32TargetInfoBase(Triple) { 5713 BigEndian = false; 5714 } 5715 void getTargetDefines(const LangOptions &Opts, 5716 MacroBuilder &Builder) const override { 5717 DefineStd(Builder, "MIPSEL", Opts); 5718 Builder.defineMacro("_MIPSEL"); 5719 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5720 } 5721 }; 5722 5723 class Mips64TargetInfoBase : public MipsTargetInfoBase { 5724 public: 5725 Mips64TargetInfoBase(const llvm::Triple &Triple) 5726 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 5727 LongWidth = LongAlign = 64; 5728 PointerWidth = PointerAlign = 64; 5729 LongDoubleWidth = LongDoubleAlign = 128; 5730 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5731 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5732 LongDoubleWidth = LongDoubleAlign = 64; 5733 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5734 } 5735 SuitableAlign = 128; 5736 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5737 } 5738 bool setABI(const std::string &Name) override { 5739 if (Name == "n32") { 5740 LongWidth = LongAlign = 32; 5741 PointerWidth = PointerAlign = 32; 5742 ABI = Name; 5743 return true; 5744 } else if (Name == "n64") { 5745 ABI = Name; 5746 return true; 5747 } else if (Name == "64") { 5748 ABI = "n64"; 5749 return true; 5750 } else 5751 return false; 5752 } 5753 void getTargetDefines(const LangOptions &Opts, 5754 MacroBuilder &Builder) const override { 5755 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5756 5757 Builder.defineMacro("__mips", "64"); 5758 Builder.defineMacro("__mips64"); 5759 Builder.defineMacro("__mips64__"); 5760 5761 if (ABI == "n32") { 5762 Builder.defineMacro("__mips_n32"); 5763 Builder.defineMacro("_ABIN32", "2"); 5764 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5765 } 5766 else if (ABI == "n64") { 5767 Builder.defineMacro("__mips_n64"); 5768 Builder.defineMacro("_ABI64", "3"); 5769 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5770 } 5771 else 5772 llvm_unreachable("Invalid ABI for Mips64."); 5773 } 5774 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5775 unsigned &NumAliases) const override { 5776 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5777 { { "at" }, "$1" }, 5778 { { "v0" }, "$2" }, 5779 { { "v1" }, "$3" }, 5780 { { "a0" }, "$4" }, 5781 { { "a1" }, "$5" }, 5782 { { "a2" }, "$6" }, 5783 { { "a3" }, "$7" }, 5784 { { "a4" }, "$8" }, 5785 { { "a5" }, "$9" }, 5786 { { "a6" }, "$10" }, 5787 { { "a7" }, "$11" }, 5788 { { "t0" }, "$12" }, 5789 { { "t1" }, "$13" }, 5790 { { "t2" }, "$14" }, 5791 { { "t3" }, "$15" }, 5792 { { "s0" }, "$16" }, 5793 { { "s1" }, "$17" }, 5794 { { "s2" }, "$18" }, 5795 { { "s3" }, "$19" }, 5796 { { "s4" }, "$20" }, 5797 { { "s5" }, "$21" }, 5798 { { "s6" }, "$22" }, 5799 { { "s7" }, "$23" }, 5800 { { "t8" }, "$24" }, 5801 { { "t9" }, "$25" }, 5802 { { "k0" }, "$26" }, 5803 { { "k1" }, "$27" }, 5804 { { "gp" }, "$28" }, 5805 { { "sp","$sp" }, "$29" }, 5806 { { "fp","$fp" }, "$30" }, 5807 { { "ra" }, "$31" } 5808 }; 5809 Aliases = GCCRegAliases; 5810 NumAliases = llvm::array_lengthof(GCCRegAliases); 5811 } 5812 }; 5813 5814 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5815 void setDescriptionString() override { 5816 if (ABI == "n32") 5817 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5818 else 5819 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5820 5821 } 5822 5823 public: 5824 Mips64EBTargetInfo(const llvm::Triple &Triple) 5825 : Mips64TargetInfoBase(Triple) {} 5826 void getTargetDefines(const LangOptions &Opts, 5827 MacroBuilder &Builder) const override { 5828 DefineStd(Builder, "MIPSEB", Opts); 5829 Builder.defineMacro("_MIPSEB"); 5830 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5831 } 5832 }; 5833 5834 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5835 void setDescriptionString() override { 5836 if (ABI == "n32") 5837 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5838 else 5839 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5840 } 5841 public: 5842 Mips64ELTargetInfo(const llvm::Triple &Triple) 5843 : Mips64TargetInfoBase(Triple) { 5844 // Default ABI is n64. 5845 BigEndian = false; 5846 } 5847 void getTargetDefines(const LangOptions &Opts, 5848 MacroBuilder &Builder) const override { 5849 DefineStd(Builder, "MIPSEL", Opts); 5850 Builder.defineMacro("_MIPSEL"); 5851 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5852 } 5853 }; 5854 } // end anonymous namespace. 5855 5856 namespace { 5857 class PNaClTargetInfo : public TargetInfo { 5858 public: 5859 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5860 BigEndian = false; 5861 this->UserLabelPrefix = ""; 5862 this->LongAlign = 32; 5863 this->LongWidth = 32; 5864 this->PointerAlign = 32; 5865 this->PointerWidth = 32; 5866 this->IntMaxType = TargetInfo::SignedLongLong; 5867 this->UIntMaxType = TargetInfo::UnsignedLongLong; 5868 this->Int64Type = TargetInfo::SignedLongLong; 5869 this->DoubleAlign = 64; 5870 this->LongDoubleWidth = 64; 5871 this->LongDoubleAlign = 64; 5872 this->SizeType = TargetInfo::UnsignedInt; 5873 this->PtrDiffType = TargetInfo::SignedInt; 5874 this->IntPtrType = TargetInfo::SignedInt; 5875 this->RegParmMax = 0; // Disallow regparm 5876 } 5877 5878 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5879 } 5880 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 5881 Builder.defineMacro("__le32__"); 5882 Builder.defineMacro("__pnacl__"); 5883 } 5884 void getTargetDefines(const LangOptions &Opts, 5885 MacroBuilder &Builder) const override { 5886 getArchDefines(Opts, Builder); 5887 } 5888 bool hasFeature(StringRef Feature) const override { 5889 return Feature == "pnacl"; 5890 } 5891 void getTargetBuiltins(const Builtin::Info *&Records, 5892 unsigned &NumRecords) const override { 5893 } 5894 BuiltinVaListKind getBuiltinVaListKind() const override { 5895 return TargetInfo::PNaClABIBuiltinVaList; 5896 } 5897 void getGCCRegNames(const char * const *&Names, 5898 unsigned &NumNames) const override; 5899 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5900 unsigned &NumAliases) const override; 5901 bool validateAsmConstraint(const char *&Name, 5902 TargetInfo::ConstraintInfo &Info) const override { 5903 return false; 5904 } 5905 5906 const char *getClobbers() const override { 5907 return ""; 5908 } 5909 }; 5910 5911 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5912 unsigned &NumNames) const { 5913 Names = NULL; 5914 NumNames = 0; 5915 } 5916 5917 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5918 unsigned &NumAliases) const { 5919 Aliases = NULL; 5920 NumAliases = 0; 5921 } 5922 } // end anonymous namespace. 5923 5924 namespace { 5925 static const unsigned SPIRAddrSpaceMap[] = { 5926 1, // opencl_global 5927 3, // opencl_local 5928 2, // opencl_constant 5929 0, // cuda_device 5930 0, // cuda_constant 5931 0 // cuda_shared 5932 }; 5933 class SPIRTargetInfo : public TargetInfo { 5934 public: 5935 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5936 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5937 "SPIR target must use unknown OS"); 5938 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5939 "SPIR target must use unknown environment type"); 5940 BigEndian = false; 5941 TLSSupported = false; 5942 LongWidth = LongAlign = 64; 5943 AddrSpaceMap = &SPIRAddrSpaceMap; 5944 UseAddrSpaceMapMangling = true; 5945 // Define available target features 5946 // These must be defined in sorted order! 5947 NoAsmVariants = true; 5948 } 5949 void getTargetDefines(const LangOptions &Opts, 5950 MacroBuilder &Builder) const override { 5951 DefineStd(Builder, "SPIR", Opts); 5952 } 5953 bool hasFeature(StringRef Feature) const override { 5954 return Feature == "spir"; 5955 } 5956 5957 void getTargetBuiltins(const Builtin::Info *&Records, 5958 unsigned &NumRecords) const override {} 5959 const char *getClobbers() const override { 5960 return ""; 5961 } 5962 void getGCCRegNames(const char * const *&Names, 5963 unsigned &NumNames) const override {} 5964 bool validateAsmConstraint(const char *&Name, 5965 TargetInfo::ConstraintInfo &info) const override { 5966 return true; 5967 } 5968 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5969 unsigned &NumAliases) const override {} 5970 BuiltinVaListKind getBuiltinVaListKind() const override { 5971 return TargetInfo::VoidPtrBuiltinVaList; 5972 } 5973 }; 5974 5975 5976 class SPIR32TargetInfo : public SPIRTargetInfo { 5977 public: 5978 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5979 PointerWidth = PointerAlign = 32; 5980 SizeType = TargetInfo::UnsignedInt; 5981 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 5982 DescriptionString 5983 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 5984 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5985 } 5986 void getTargetDefines(const LangOptions &Opts, 5987 MacroBuilder &Builder) const override { 5988 DefineStd(Builder, "SPIR32", Opts); 5989 } 5990 }; 5991 5992 class SPIR64TargetInfo : public SPIRTargetInfo { 5993 public: 5994 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5995 PointerWidth = PointerAlign = 64; 5996 SizeType = TargetInfo::UnsignedLong; 5997 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 5998 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 5999 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6000 } 6001 void getTargetDefines(const LangOptions &Opts, 6002 MacroBuilder &Builder) const override { 6003 DefineStd(Builder, "SPIR64", Opts); 6004 } 6005 }; 6006 } 6007 6008 namespace { 6009 class XCoreTargetInfo : public TargetInfo { 6010 static const Builtin::Info BuiltinInfo[]; 6011 public: 6012 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6013 BigEndian = false; 6014 NoAsmVariants = true; 6015 LongLongAlign = 32; 6016 SuitableAlign = 32; 6017 DoubleAlign = LongDoubleAlign = 32; 6018 SizeType = UnsignedInt; 6019 PtrDiffType = SignedInt; 6020 IntPtrType = SignedInt; 6021 WCharType = UnsignedChar; 6022 WIntType = UnsignedInt; 6023 UseZeroLengthBitfieldAlignment = true; 6024 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6025 "-f64:32-a:0:32-n32"; 6026 } 6027 void getTargetDefines(const LangOptions &Opts, 6028 MacroBuilder &Builder) const override { 6029 Builder.defineMacro("__XS1B__"); 6030 } 6031 void getTargetBuiltins(const Builtin::Info *&Records, 6032 unsigned &NumRecords) const override { 6033 Records = BuiltinInfo; 6034 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6035 } 6036 BuiltinVaListKind getBuiltinVaListKind() const override { 6037 return TargetInfo::VoidPtrBuiltinVaList; 6038 } 6039 const char *getClobbers() const override { 6040 return ""; 6041 } 6042 void getGCCRegNames(const char * const *&Names, 6043 unsigned &NumNames) const override { 6044 static const char * const GCCRegNames[] = { 6045 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6046 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6047 }; 6048 Names = GCCRegNames; 6049 NumNames = llvm::array_lengthof(GCCRegNames); 6050 } 6051 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6052 unsigned &NumAliases) const override { 6053 Aliases = NULL; 6054 NumAliases = 0; 6055 } 6056 bool validateAsmConstraint(const char *&Name, 6057 TargetInfo::ConstraintInfo &Info) const override { 6058 return false; 6059 } 6060 int getEHDataRegisterNumber(unsigned RegNo) const override { 6061 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6062 return (RegNo < 2)? RegNo : -1; 6063 } 6064 }; 6065 6066 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6067 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6068 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6069 ALL_LANGUAGES }, 6070 #include "clang/Basic/BuiltinsXCore.def" 6071 }; 6072 } // end anonymous namespace. 6073 6074 6075 //===----------------------------------------------------------------------===// 6076 // Driver code 6077 //===----------------------------------------------------------------------===// 6078 6079 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 6080 llvm::Triple::OSType os = Triple.getOS(); 6081 6082 switch (Triple.getArch()) { 6083 default: 6084 return NULL; 6085 6086 case llvm::Triple::arm64: 6087 if (Triple.isOSDarwin()) 6088 return new DarwinARM64TargetInfo(Triple); 6089 6090 switch (os) { 6091 case llvm::Triple::Linux: 6092 return new LinuxTargetInfo<ARM64TargetInfo>(Triple); 6093 default: 6094 return new ARM64TargetInfo(Triple); 6095 } 6096 6097 case llvm::Triple::xcore: 6098 return new XCoreTargetInfo(Triple); 6099 6100 case llvm::Triple::hexagon: 6101 return new HexagonTargetInfo(Triple); 6102 6103 case llvm::Triple::aarch64: 6104 switch (os) { 6105 case llvm::Triple::Linux: 6106 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6107 case llvm::Triple::NetBSD: 6108 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6109 default: 6110 return new AArch64leTargetInfo(Triple); 6111 } 6112 6113 case llvm::Triple::aarch64_be: 6114 switch (os) { 6115 case llvm::Triple::Linux: 6116 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6117 case llvm::Triple::NetBSD: 6118 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6119 default: 6120 return new AArch64beTargetInfo(Triple); 6121 } 6122 6123 case llvm::Triple::arm: 6124 case llvm::Triple::thumb: 6125 if (Triple.isOSBinFormatMachO()) 6126 return new DarwinARMTargetInfo(Triple); 6127 6128 switch (os) { 6129 case llvm::Triple::Linux: 6130 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6131 case llvm::Triple::FreeBSD: 6132 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6133 case llvm::Triple::NetBSD: 6134 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6135 case llvm::Triple::OpenBSD: 6136 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6137 case llvm::Triple::Bitrig: 6138 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6139 case llvm::Triple::RTEMS: 6140 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6141 case llvm::Triple::NaCl: 6142 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6143 case llvm::Triple::Win32: 6144 switch (Triple.getEnvironment()) { 6145 default: 6146 return new ARMleTargetInfo(Triple); 6147 case llvm::Triple::Itanium: 6148 return new ItaniumWindowsARMleTargetInfo(Triple); 6149 case llvm::Triple::MSVC: 6150 return new MicrosoftARMleTargetInfo(Triple); 6151 } 6152 default: 6153 return new ARMleTargetInfo(Triple); 6154 } 6155 6156 case llvm::Triple::armeb: 6157 case llvm::Triple::thumbeb: 6158 if (Triple.isOSDarwin()) 6159 return new DarwinARMTargetInfo(Triple); 6160 6161 switch (os) { 6162 case llvm::Triple::Linux: 6163 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 6164 case llvm::Triple::FreeBSD: 6165 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 6166 case llvm::Triple::NetBSD: 6167 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 6168 case llvm::Triple::OpenBSD: 6169 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 6170 case llvm::Triple::Bitrig: 6171 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 6172 case llvm::Triple::RTEMS: 6173 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 6174 case llvm::Triple::NaCl: 6175 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 6176 default: 6177 return new ARMbeTargetInfo(Triple); 6178 } 6179 6180 case llvm::Triple::msp430: 6181 return new MSP430TargetInfo(Triple); 6182 6183 case llvm::Triple::mips: 6184 switch (os) { 6185 case llvm::Triple::Linux: 6186 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 6187 case llvm::Triple::RTEMS: 6188 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 6189 case llvm::Triple::FreeBSD: 6190 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6191 case llvm::Triple::NetBSD: 6192 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6193 default: 6194 return new Mips32EBTargetInfo(Triple); 6195 } 6196 6197 case llvm::Triple::mipsel: 6198 switch (os) { 6199 case llvm::Triple::Linux: 6200 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 6201 case llvm::Triple::RTEMS: 6202 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 6203 case llvm::Triple::FreeBSD: 6204 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6205 case llvm::Triple::NetBSD: 6206 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6207 case llvm::Triple::NaCl: 6208 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 6209 default: 6210 return new Mips32ELTargetInfo(Triple); 6211 } 6212 6213 case llvm::Triple::mips64: 6214 switch (os) { 6215 case llvm::Triple::Linux: 6216 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 6217 case llvm::Triple::RTEMS: 6218 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 6219 case llvm::Triple::FreeBSD: 6220 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6221 case llvm::Triple::NetBSD: 6222 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6223 case llvm::Triple::OpenBSD: 6224 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6225 default: 6226 return new Mips64EBTargetInfo(Triple); 6227 } 6228 6229 case llvm::Triple::mips64el: 6230 switch (os) { 6231 case llvm::Triple::Linux: 6232 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 6233 case llvm::Triple::RTEMS: 6234 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 6235 case llvm::Triple::FreeBSD: 6236 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6237 case llvm::Triple::NetBSD: 6238 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6239 case llvm::Triple::OpenBSD: 6240 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6241 default: 6242 return new Mips64ELTargetInfo(Triple); 6243 } 6244 6245 case llvm::Triple::le32: 6246 switch (os) { 6247 case llvm::Triple::NaCl: 6248 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 6249 default: 6250 return NULL; 6251 } 6252 6253 case llvm::Triple::ppc: 6254 if (Triple.isOSDarwin()) 6255 return new DarwinPPC32TargetInfo(Triple); 6256 switch (os) { 6257 case llvm::Triple::Linux: 6258 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 6259 case llvm::Triple::FreeBSD: 6260 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 6261 case llvm::Triple::NetBSD: 6262 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 6263 case llvm::Triple::OpenBSD: 6264 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 6265 case llvm::Triple::RTEMS: 6266 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 6267 default: 6268 return new PPC32TargetInfo(Triple); 6269 } 6270 6271 case llvm::Triple::ppc64: 6272 if (Triple.isOSDarwin()) 6273 return new DarwinPPC64TargetInfo(Triple); 6274 switch (os) { 6275 case llvm::Triple::Linux: 6276 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6277 case llvm::Triple::Lv2: 6278 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 6279 case llvm::Triple::FreeBSD: 6280 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 6281 case llvm::Triple::NetBSD: 6282 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6283 default: 6284 return new PPC64TargetInfo(Triple); 6285 } 6286 6287 case llvm::Triple::ppc64le: 6288 switch (os) { 6289 case llvm::Triple::Linux: 6290 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6291 default: 6292 return new PPC64TargetInfo(Triple); 6293 } 6294 6295 case llvm::Triple::nvptx: 6296 return new NVPTX32TargetInfo(Triple); 6297 case llvm::Triple::nvptx64: 6298 return new NVPTX64TargetInfo(Triple); 6299 6300 case llvm::Triple::r600: 6301 return new R600TargetInfo(Triple); 6302 6303 case llvm::Triple::sparc: 6304 switch (os) { 6305 case llvm::Triple::Linux: 6306 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 6307 case llvm::Triple::AuroraUX: 6308 return new AuroraUXSparcV8TargetInfo(Triple); 6309 case llvm::Triple::Solaris: 6310 return new SolarisSparcV8TargetInfo(Triple); 6311 case llvm::Triple::NetBSD: 6312 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 6313 case llvm::Triple::OpenBSD: 6314 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 6315 case llvm::Triple::RTEMS: 6316 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 6317 default: 6318 return new SparcV8TargetInfo(Triple); 6319 } 6320 6321 case llvm::Triple::sparcv9: 6322 switch (os) { 6323 case llvm::Triple::Linux: 6324 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 6325 case llvm::Triple::AuroraUX: 6326 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 6327 case llvm::Triple::Solaris: 6328 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 6329 case llvm::Triple::NetBSD: 6330 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 6331 case llvm::Triple::OpenBSD: 6332 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 6333 case llvm::Triple::FreeBSD: 6334 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 6335 default: 6336 return new SparcV9TargetInfo(Triple); 6337 } 6338 6339 case llvm::Triple::systemz: 6340 switch (os) { 6341 case llvm::Triple::Linux: 6342 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 6343 default: 6344 return new SystemZTargetInfo(Triple); 6345 } 6346 6347 case llvm::Triple::tce: 6348 return new TCETargetInfo(Triple); 6349 6350 case llvm::Triple::x86: 6351 if (Triple.isOSDarwin()) 6352 return new DarwinI386TargetInfo(Triple); 6353 6354 switch (os) { 6355 case llvm::Triple::AuroraUX: 6356 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 6357 case llvm::Triple::Linux: 6358 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 6359 case llvm::Triple::DragonFly: 6360 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 6361 case llvm::Triple::NetBSD: 6362 return new NetBSDI386TargetInfo(Triple); 6363 case llvm::Triple::OpenBSD: 6364 return new OpenBSDI386TargetInfo(Triple); 6365 case llvm::Triple::Bitrig: 6366 return new BitrigI386TargetInfo(Triple); 6367 case llvm::Triple::FreeBSD: 6368 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6369 case llvm::Triple::KFreeBSD: 6370 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6371 case llvm::Triple::Minix: 6372 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 6373 case llvm::Triple::Solaris: 6374 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 6375 case llvm::Triple::Win32: { 6376 switch (Triple.getEnvironment()) { 6377 default: 6378 return new X86_32TargetInfo(Triple); 6379 case llvm::Triple::Cygnus: 6380 return new CygwinX86_32TargetInfo(Triple); 6381 case llvm::Triple::GNU: 6382 return new MinGWX86_32TargetInfo(Triple); 6383 case llvm::Triple::MSVC: 6384 return new MicrosoftX86_32TargetInfo(Triple); 6385 } 6386 } 6387 case llvm::Triple::Haiku: 6388 return new HaikuX86_32TargetInfo(Triple); 6389 case llvm::Triple::RTEMS: 6390 return new RTEMSX86_32TargetInfo(Triple); 6391 case llvm::Triple::NaCl: 6392 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 6393 default: 6394 return new X86_32TargetInfo(Triple); 6395 } 6396 6397 case llvm::Triple::x86_64: 6398 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 6399 return new DarwinX86_64TargetInfo(Triple); 6400 6401 switch (os) { 6402 case llvm::Triple::AuroraUX: 6403 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 6404 case llvm::Triple::Linux: 6405 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 6406 case llvm::Triple::DragonFly: 6407 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 6408 case llvm::Triple::NetBSD: 6409 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 6410 case llvm::Triple::OpenBSD: 6411 return new OpenBSDX86_64TargetInfo(Triple); 6412 case llvm::Triple::Bitrig: 6413 return new BitrigX86_64TargetInfo(Triple); 6414 case llvm::Triple::FreeBSD: 6415 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6416 case llvm::Triple::KFreeBSD: 6417 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6418 case llvm::Triple::Solaris: 6419 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 6420 case llvm::Triple::Win32: { 6421 switch (Triple.getEnvironment()) { 6422 default: 6423 return new X86_64TargetInfo(Triple); 6424 case llvm::Triple::GNU: 6425 return new MinGWX86_64TargetInfo(Triple); 6426 case llvm::Triple::MSVC: 6427 return new MicrosoftX86_64TargetInfo(Triple); 6428 } 6429 } 6430 case llvm::Triple::NaCl: 6431 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 6432 default: 6433 return new X86_64TargetInfo(Triple); 6434 } 6435 6436 case llvm::Triple::spir: { 6437 if (Triple.getOS() != llvm::Triple::UnknownOS || 6438 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6439 return NULL; 6440 return new SPIR32TargetInfo(Triple); 6441 } 6442 case llvm::Triple::spir64: { 6443 if (Triple.getOS() != llvm::Triple::UnknownOS || 6444 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6445 return NULL; 6446 return new SPIR64TargetInfo(Triple); 6447 } 6448 } 6449 } 6450 6451 /// CreateTargetInfo - Return the target info object for the specified target 6452 /// triple. 6453 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 6454 TargetOptions *Opts) { 6455 llvm::Triple Triple(Opts->Triple); 6456 6457 // Construct the target 6458 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 6459 if (!Target) { 6460 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 6461 return 0; 6462 } 6463 Target->setTargetOpts(Opts); 6464 6465 // Set the target CPU if specified. 6466 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 6467 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 6468 return 0; 6469 } 6470 6471 // Set the target ABI if specified. 6472 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 6473 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 6474 return 0; 6475 } 6476 6477 // Set the fp math unit. 6478 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 6479 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 6480 return 0; 6481 } 6482 6483 // Compute the default target features, we need the target to handle this 6484 // because features may have dependencies on one another. 6485 llvm::StringMap<bool> Features; 6486 Target->getDefaultFeatures(Features); 6487 6488 // Apply the user specified deltas. 6489 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 6490 I < N; ++I) { 6491 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 6492 // Apply the feature via the target. 6493 bool Enabled = Name[0] == '+'; 6494 Target->setFeatureEnabled(Features, Name + 1, Enabled); 6495 } 6496 6497 // Add the features to the compile options. 6498 // 6499 // FIXME: If we are completely confident that we have the right set, we only 6500 // need to pass the minuses. 6501 Opts->Features.clear(); 6502 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 6503 ie = Features.end(); it != ie; ++it) 6504 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 6505 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 6506 return 0; 6507 6508 return Target.release(); 6509 } 6510