1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/OwningPtr.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/IR/Type.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include <algorithm> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 virtual void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("__MACH__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 98 99 if (!Opts.ObjCAutoRefCount) { 100 // __weak is always defined, for use in blocks and with objc pointers. 101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 102 103 // Darwin defines __strong even in C mode (just to nothing). 104 if (Opts.getGC() != LangOptions::NonGC) 105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 106 else 107 Builder.defineMacro("__strong", ""); 108 109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 110 // allow this in C, since one might have block pointers in structs that 111 // are used in pure C code and in Objective-C ARC. 112 Builder.defineMacro("__unsafe_unretained", ""); 113 } 114 115 if (Opts.Static) 116 Builder.defineMacro("__STATIC__"); 117 else 118 Builder.defineMacro("__DYNAMIC__"); 119 120 if (Opts.POSIXThreads) 121 Builder.defineMacro("_REENTRANT"); 122 123 // Get the platform type and version number from the triple. 124 unsigned Maj, Min, Rev; 125 if (Triple.isMacOSX()) { 126 Triple.getMacOSXVersion(Maj, Min, Rev); 127 PlatformName = "macosx"; 128 } else { 129 Triple.getOSVersion(Maj, Min, Rev); 130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 131 } 132 133 // If -target arch-pc-win32-macho option specified, we're 134 // generating code for Win32 ABI. No need to emit 135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 136 if (PlatformName == "win32") { 137 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 138 return; 139 } 140 141 // Set the appropriate OS version define. 142 if (Triple.getOS() == llvm::Triple::IOS) { 143 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 144 char Str[6]; 145 Str[0] = '0' + Maj; 146 Str[1] = '0' + (Min / 10); 147 Str[2] = '0' + (Min % 10); 148 Str[3] = '0' + (Rev / 10); 149 Str[4] = '0' + (Rev % 10); 150 Str[5] = '\0'; 151 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str); 152 } else { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Triple.getEnvironmentName().empty() && "Invalid environment!"); 158 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[5]; 160 Str[0] = '0' + (Maj / 10); 161 Str[1] = '0' + (Maj % 10); 162 Str[2] = '0' + std::min(Min, 9U); 163 Str[3] = '0' + std::min(Rev, 9U); 164 Str[4] = '\0'; 165 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 166 } 167 168 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 169 } 170 171 namespace { 172 template<typename Target> 173 class DarwinTargetInfo : public OSTargetInfo<Target> { 174 protected: 175 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 176 MacroBuilder &Builder) const { 177 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 178 this->PlatformMinVersion); 179 } 180 181 public: 182 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 183 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 184 this->MCountName = "\01mcount"; 185 } 186 187 virtual std::string isValidSectionSpecifier(StringRef SR) const { 188 // Let MCSectionMachO validate this. 189 StringRef Segment, Section; 190 unsigned TAA, StubSize; 191 bool HasTAA; 192 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 193 TAA, HasTAA, StubSize); 194 } 195 196 virtual const char *getStaticInitSectionSpecifier() const { 197 // FIXME: We should return 0 when building kexts. 198 return "__TEXT,__StaticInit,regular,pure_instructions"; 199 } 200 201 /// Darwin does not support protected visibility. Darwin's "default" 202 /// is very similar to ELF's "protected"; Darwin requires a "weak" 203 /// attribute on declarations that can be dynamically replaced. 204 virtual bool hasProtectedVisibility() const { 205 return false; 206 } 207 }; 208 209 210 // DragonFlyBSD Target 211 template<typename Target> 212 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 213 protected: 214 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 215 MacroBuilder &Builder) const { 216 // DragonFly defines; list based off of gcc output 217 Builder.defineMacro("__DragonFly__"); 218 Builder.defineMacro("__DragonFly_cc_version", "100001"); 219 Builder.defineMacro("__ELF__"); 220 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 221 Builder.defineMacro("__tune_i386__"); 222 DefineStd(Builder, "unix", Opts); 223 } 224 public: 225 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 226 : OSTargetInfo<Target>(Triple) { 227 this->UserLabelPrefix = ""; 228 229 switch (Triple.getArch()) { 230 default: 231 case llvm::Triple::x86: 232 case llvm::Triple::x86_64: 233 this->MCountName = ".mcount"; 234 break; 235 } 236 } 237 }; 238 239 // FreeBSD Target 240 template<typename Target> 241 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 242 protected: 243 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 244 MacroBuilder &Builder) const { 245 // FreeBSD defines; list based off of gcc output 246 247 unsigned Release = Triple.getOSMajorVersion(); 248 if (Release == 0U) 249 Release = 8; 250 251 Builder.defineMacro("__FreeBSD__", Twine(Release)); 252 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 253 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 254 DefineStd(Builder, "unix", Opts); 255 Builder.defineMacro("__ELF__"); 256 } 257 public: 258 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 259 this->UserLabelPrefix = ""; 260 261 switch (Triple.getArch()) { 262 default: 263 case llvm::Triple::x86: 264 case llvm::Triple::x86_64: 265 this->MCountName = ".mcount"; 266 break; 267 case llvm::Triple::mips: 268 case llvm::Triple::mipsel: 269 case llvm::Triple::ppc: 270 case llvm::Triple::ppc64: 271 case llvm::Triple::ppc64le: 272 this->MCountName = "_mcount"; 273 break; 274 case llvm::Triple::arm: 275 this->MCountName = "__mcount"; 276 break; 277 } 278 } 279 }; 280 281 // Minix Target 282 template<typename Target> 283 class MinixTargetInfo : public OSTargetInfo<Target> { 284 protected: 285 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 286 MacroBuilder &Builder) const { 287 // Minix defines 288 289 Builder.defineMacro("__minix", "3"); 290 Builder.defineMacro("_EM_WSIZE", "4"); 291 Builder.defineMacro("_EM_PSIZE", "4"); 292 Builder.defineMacro("_EM_SSIZE", "2"); 293 Builder.defineMacro("_EM_LSIZE", "4"); 294 Builder.defineMacro("_EM_FSIZE", "4"); 295 Builder.defineMacro("_EM_DSIZE", "8"); 296 Builder.defineMacro("__ELF__"); 297 DefineStd(Builder, "unix", Opts); 298 } 299 public: 300 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 301 this->UserLabelPrefix = ""; 302 } 303 }; 304 305 // Linux target 306 template<typename Target> 307 class LinuxTargetInfo : public OSTargetInfo<Target> { 308 protected: 309 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 310 MacroBuilder &Builder) const { 311 // Linux defines; list based off of gcc output 312 DefineStd(Builder, "unix", Opts); 313 DefineStd(Builder, "linux", Opts); 314 Builder.defineMacro("__gnu_linux__"); 315 Builder.defineMacro("__ELF__"); 316 if (Triple.getEnvironment() == llvm::Triple::Android) 317 Builder.defineMacro("__ANDROID__", "1"); 318 if (Opts.POSIXThreads) 319 Builder.defineMacro("_REENTRANT"); 320 if (Opts.CPlusPlus) 321 Builder.defineMacro("_GNU_SOURCE"); 322 } 323 public: 324 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 325 this->UserLabelPrefix = ""; 326 this->WIntType = TargetInfo::UnsignedInt; 327 } 328 329 virtual const char *getStaticInitSectionSpecifier() const { 330 return ".text.startup"; 331 } 332 }; 333 334 // NetBSD Target 335 template<typename Target> 336 class NetBSDTargetInfo : public OSTargetInfo<Target> { 337 protected: 338 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 339 MacroBuilder &Builder) const { 340 // NetBSD defines; list based off of gcc output 341 Builder.defineMacro("__NetBSD__"); 342 Builder.defineMacro("__unix__"); 343 Builder.defineMacro("__ELF__"); 344 if (Opts.POSIXThreads) 345 Builder.defineMacro("_POSIX_THREADS"); 346 } 347 public: 348 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 349 this->UserLabelPrefix = ""; 350 } 351 }; 352 353 // OpenBSD Target 354 template<typename Target> 355 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 356 protected: 357 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 358 MacroBuilder &Builder) const { 359 // OpenBSD defines; list based off of gcc output 360 361 Builder.defineMacro("__OpenBSD__"); 362 DefineStd(Builder, "unix", Opts); 363 Builder.defineMacro("__ELF__"); 364 if (Opts.POSIXThreads) 365 Builder.defineMacro("_REENTRANT"); 366 } 367 public: 368 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 369 this->UserLabelPrefix = ""; 370 this->TLSSupported = false; 371 372 switch (Triple.getArch()) { 373 default: 374 case llvm::Triple::x86: 375 case llvm::Triple::x86_64: 376 case llvm::Triple::arm: 377 case llvm::Triple::sparc: 378 this->MCountName = "__mcount"; 379 break; 380 case llvm::Triple::mips64: 381 case llvm::Triple::mips64el: 382 case llvm::Triple::ppc: 383 case llvm::Triple::sparcv9: 384 this->MCountName = "_mcount"; 385 break; 386 } 387 } 388 }; 389 390 // Bitrig Target 391 template<typename Target> 392 class BitrigTargetInfo : public OSTargetInfo<Target> { 393 protected: 394 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 395 MacroBuilder &Builder) const { 396 // Bitrig defines; list based off of gcc output 397 398 Builder.defineMacro("__Bitrig__"); 399 DefineStd(Builder, "unix", Opts); 400 Builder.defineMacro("__ELF__"); 401 if (Opts.POSIXThreads) 402 Builder.defineMacro("_REENTRANT"); 403 } 404 public: 405 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 406 this->UserLabelPrefix = ""; 407 this->TLSSupported = false; 408 this->MCountName = "__mcount"; 409 } 410 }; 411 412 // PSP Target 413 template<typename Target> 414 class PSPTargetInfo : public OSTargetInfo<Target> { 415 protected: 416 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 417 MacroBuilder &Builder) const { 418 // PSP defines; list based on the output of the pspdev gcc toolchain. 419 Builder.defineMacro("PSP"); 420 Builder.defineMacro("_PSP"); 421 Builder.defineMacro("__psp__"); 422 Builder.defineMacro("__ELF__"); 423 } 424 public: 425 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 426 this->UserLabelPrefix = ""; 427 } 428 }; 429 430 // PS3 PPU Target 431 template<typename Target> 432 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 433 protected: 434 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 435 MacroBuilder &Builder) const { 436 // PS3 PPU defines. 437 Builder.defineMacro("__PPC__"); 438 Builder.defineMacro("__PPU__"); 439 Builder.defineMacro("__CELLOS_LV2__"); 440 Builder.defineMacro("__ELF__"); 441 Builder.defineMacro("__LP32__"); 442 Builder.defineMacro("_ARCH_PPC64"); 443 Builder.defineMacro("__powerpc64__"); 444 } 445 public: 446 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 447 this->UserLabelPrefix = ""; 448 this->LongWidth = this->LongAlign = 32; 449 this->PointerWidth = this->PointerAlign = 32; 450 this->IntMaxType = TargetInfo::SignedLongLong; 451 this->UIntMaxType = TargetInfo::UnsignedLongLong; 452 this->Int64Type = TargetInfo::SignedLongLong; 453 this->SizeType = TargetInfo::UnsignedInt; 454 this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 455 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 456 } 457 }; 458 459 // FIXME: Need a real SPU target. 460 // PS3 SPU Target 461 template<typename Target> 462 class PS3SPUTargetInfo : public OSTargetInfo<Target> { 463 protected: 464 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 465 MacroBuilder &Builder) const { 466 // PS3 PPU defines. 467 Builder.defineMacro("__SPU__"); 468 Builder.defineMacro("__ELF__"); 469 } 470 public: 471 PS3SPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 472 this->UserLabelPrefix = ""; 473 } 474 }; 475 476 // AuroraUX target 477 template<typename Target> 478 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 479 protected: 480 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 481 MacroBuilder &Builder) const { 482 DefineStd(Builder, "sun", Opts); 483 DefineStd(Builder, "unix", Opts); 484 Builder.defineMacro("__ELF__"); 485 Builder.defineMacro("__svr4__"); 486 Builder.defineMacro("__SVR4"); 487 } 488 public: 489 AuroraUXTargetInfo(const llvm::Triple &Triple) 490 : OSTargetInfo<Target>(Triple) { 491 this->UserLabelPrefix = ""; 492 this->WCharType = this->SignedLong; 493 // FIXME: WIntType should be SignedLong 494 } 495 }; 496 497 // Solaris target 498 template<typename Target> 499 class SolarisTargetInfo : public OSTargetInfo<Target> { 500 protected: 501 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 502 MacroBuilder &Builder) const { 503 DefineStd(Builder, "sun", Opts); 504 DefineStd(Builder, "unix", Opts); 505 Builder.defineMacro("__ELF__"); 506 Builder.defineMacro("__svr4__"); 507 Builder.defineMacro("__SVR4"); 508 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 509 // newer, but to 500 for everything else. feature_test.h has a check to 510 // ensure that you are not using C99 with an old version of X/Open or C89 511 // with a new version. 512 if (Opts.C99 || Opts.C11) 513 Builder.defineMacro("_XOPEN_SOURCE", "600"); 514 else 515 Builder.defineMacro("_XOPEN_SOURCE", "500"); 516 if (Opts.CPlusPlus) 517 Builder.defineMacro("__C99FEATURES__"); 518 Builder.defineMacro("_LARGEFILE_SOURCE"); 519 Builder.defineMacro("_LARGEFILE64_SOURCE"); 520 Builder.defineMacro("__EXTENSIONS__"); 521 Builder.defineMacro("_REENTRANT"); 522 } 523 public: 524 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 525 this->UserLabelPrefix = ""; 526 this->WCharType = this->SignedInt; 527 // FIXME: WIntType should be SignedLong 528 } 529 }; 530 531 // Windows target 532 template<typename Target> 533 class WindowsTargetInfo : public OSTargetInfo<Target> { 534 protected: 535 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 536 MacroBuilder &Builder) const { 537 Builder.defineMacro("_WIN32"); 538 } 539 void getVisualStudioDefines(const LangOptions &Opts, 540 MacroBuilder &Builder) const { 541 if (Opts.CPlusPlus) { 542 if (Opts.RTTI) 543 Builder.defineMacro("_CPPRTTI"); 544 545 if (Opts.Exceptions) 546 Builder.defineMacro("_CPPUNWIND"); 547 } 548 549 if (!Opts.CharIsSigned) 550 Builder.defineMacro("_CHAR_UNSIGNED"); 551 552 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 553 // but it works for now. 554 if (Opts.POSIXThreads) 555 Builder.defineMacro("_MT"); 556 557 if (Opts.MSCVersion != 0) 558 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 559 560 if (Opts.MicrosoftExt) { 561 Builder.defineMacro("_MSC_EXTENSIONS"); 562 563 if (Opts.CPlusPlus11) { 564 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 565 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 566 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 567 } 568 } 569 570 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 571 } 572 573 public: 574 WindowsTargetInfo(const llvm::Triple &Triple) 575 : OSTargetInfo<Target>(Triple) {} 576 }; 577 578 template <typename Target> 579 class NaClTargetInfo : public OSTargetInfo<Target> { 580 protected: 581 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 582 MacroBuilder &Builder) const { 583 if (Opts.POSIXThreads) 584 Builder.defineMacro("_REENTRANT"); 585 if (Opts.CPlusPlus) 586 Builder.defineMacro("_GNU_SOURCE"); 587 588 DefineStd(Builder, "unix", Opts); 589 Builder.defineMacro("__ELF__"); 590 Builder.defineMacro("__native_client__"); 591 } 592 593 public: 594 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 595 this->UserLabelPrefix = ""; 596 this->LongAlign = 32; 597 this->LongWidth = 32; 598 this->PointerAlign = 32; 599 this->PointerWidth = 32; 600 this->IntMaxType = TargetInfo::SignedLongLong; 601 this->UIntMaxType = TargetInfo::UnsignedLongLong; 602 this->Int64Type = TargetInfo::SignedLongLong; 603 this->DoubleAlign = 64; 604 this->LongDoubleWidth = 64; 605 this->LongDoubleAlign = 64; 606 this->SizeType = TargetInfo::UnsignedInt; 607 this->PtrDiffType = TargetInfo::SignedInt; 608 this->IntPtrType = TargetInfo::SignedInt; 609 // RegParmMax is inherited from the underlying architecture 610 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 611 this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 612 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 613 } 614 virtual typename Target::CallingConvCheckResult checkCallingConvention( 615 CallingConv CC) const { 616 return CC == CC_PnaclCall ? Target::CCCR_OK : 617 Target::checkCallingConvention(CC); 618 } 619 }; 620 } // end anonymous namespace. 621 622 //===----------------------------------------------------------------------===// 623 // Specific target implementations. 624 //===----------------------------------------------------------------------===// 625 626 namespace { 627 // PPC abstract base class 628 class PPCTargetInfo : public TargetInfo { 629 static const Builtin::Info BuiltinInfo[]; 630 static const char * const GCCRegNames[]; 631 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 632 std::string CPU; 633 public: 634 PPCTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 635 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 636 LongDoubleWidth = LongDoubleAlign = 128; 637 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 638 } 639 640 /// \brief Flags for architecture specific defines. 641 typedef enum { 642 ArchDefineNone = 0, 643 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 644 ArchDefinePpcgr = 1 << 1, 645 ArchDefinePpcsq = 1 << 2, 646 ArchDefine440 = 1 << 3, 647 ArchDefine603 = 1 << 4, 648 ArchDefine604 = 1 << 5, 649 ArchDefinePwr4 = 1 << 6, 650 ArchDefinePwr5 = 1 << 7, 651 ArchDefinePwr5x = 1 << 8, 652 ArchDefinePwr6 = 1 << 9, 653 ArchDefinePwr6x = 1 << 10, 654 ArchDefinePwr7 = 1 << 11, 655 ArchDefineA2 = 1 << 12, 656 ArchDefineA2q = 1 << 13 657 } ArchDefineTypes; 658 659 // Note: GCC recognizes the following additional cpus: 660 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 661 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 662 // titan, rs64. 663 virtual bool setCPU(const std::string &Name) { 664 bool CPUKnown = llvm::StringSwitch<bool>(Name) 665 .Case("generic", true) 666 .Case("440", true) 667 .Case("450", true) 668 .Case("601", true) 669 .Case("602", true) 670 .Case("603", true) 671 .Case("603e", true) 672 .Case("603ev", true) 673 .Case("604", true) 674 .Case("604e", true) 675 .Case("620", true) 676 .Case("630", true) 677 .Case("g3", true) 678 .Case("7400", true) 679 .Case("g4", true) 680 .Case("7450", true) 681 .Case("g4+", true) 682 .Case("750", true) 683 .Case("970", true) 684 .Case("g5", true) 685 .Case("a2", true) 686 .Case("a2q", true) 687 .Case("e500mc", true) 688 .Case("e5500", true) 689 .Case("power3", true) 690 .Case("pwr3", true) 691 .Case("power4", true) 692 .Case("pwr4", true) 693 .Case("power5", true) 694 .Case("pwr5", true) 695 .Case("power5x", true) 696 .Case("pwr5x", true) 697 .Case("power6", true) 698 .Case("pwr6", true) 699 .Case("power6x", true) 700 .Case("pwr6x", true) 701 .Case("power7", true) 702 .Case("pwr7", true) 703 .Case("powerpc", true) 704 .Case("ppc", true) 705 .Case("powerpc64", true) 706 .Case("ppc64", true) 707 .Case("powerpc64le", true) 708 .Case("ppc64le", true) 709 .Default(false); 710 711 if (CPUKnown) 712 CPU = Name; 713 714 return CPUKnown; 715 } 716 717 virtual void getTargetBuiltins(const Builtin::Info *&Records, 718 unsigned &NumRecords) const { 719 Records = BuiltinInfo; 720 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 721 } 722 723 virtual bool isCLZForZeroUndef() const { return false; } 724 725 virtual void getTargetDefines(const LangOptions &Opts, 726 MacroBuilder &Builder) const; 727 728 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 729 730 virtual bool hasFeature(StringRef Feature) const; 731 732 virtual void getGCCRegNames(const char * const *&Names, 733 unsigned &NumNames) const; 734 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 735 unsigned &NumAliases) const; 736 virtual bool validateAsmConstraint(const char *&Name, 737 TargetInfo::ConstraintInfo &Info) const { 738 switch (*Name) { 739 default: return false; 740 case 'O': // Zero 741 break; 742 case 'b': // Base register 743 case 'f': // Floating point register 744 Info.setAllowsRegister(); 745 break; 746 // FIXME: The following are added to allow parsing. 747 // I just took a guess at what the actions should be. 748 // Also, is more specific checking needed? I.e. specific registers? 749 case 'd': // Floating point register (containing 64-bit value) 750 case 'v': // Altivec vector register 751 Info.setAllowsRegister(); 752 break; 753 case 'w': 754 switch (Name[1]) { 755 case 'd':// VSX vector register to hold vector double data 756 case 'f':// VSX vector register to hold vector float data 757 case 's':// VSX vector register to hold scalar float data 758 case 'a':// Any VSX register 759 break; 760 default: 761 return false; 762 } 763 Info.setAllowsRegister(); 764 Name++; // Skip over 'w'. 765 break; 766 case 'h': // `MQ', `CTR', or `LINK' register 767 case 'q': // `MQ' register 768 case 'c': // `CTR' register 769 case 'l': // `LINK' register 770 case 'x': // `CR' register (condition register) number 0 771 case 'y': // `CR' register (condition register) 772 case 'z': // `XER[CA]' carry bit (part of the XER register) 773 Info.setAllowsRegister(); 774 break; 775 case 'I': // Signed 16-bit constant 776 case 'J': // Unsigned 16-bit constant shifted left 16 bits 777 // (use `L' instead for SImode constants) 778 case 'K': // Unsigned 16-bit constant 779 case 'L': // Signed 16-bit constant shifted left 16 bits 780 case 'M': // Constant larger than 31 781 case 'N': // Exact power of 2 782 case 'P': // Constant whose negation is a signed 16-bit constant 783 case 'G': // Floating point constant that can be loaded into a 784 // register with one instruction per word 785 case 'H': // Integer/Floating point constant that can be loaded 786 // into a register using three instructions 787 break; 788 case 'm': // Memory operand. Note that on PowerPC targets, m can 789 // include addresses that update the base register. It 790 // is therefore only safe to use `m' in an asm statement 791 // if that asm statement accesses the operand exactly once. 792 // The asm statement must also use `%U<opno>' as a 793 // placeholder for the "update" flag in the corresponding 794 // load or store instruction. For example: 795 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 796 // is correct but: 797 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 798 // is not. Use es rather than m if you don't want the base 799 // register to be updated. 800 case 'e': 801 if (Name[1] != 's') 802 return false; 803 // es: A "stable" memory operand; that is, one which does not 804 // include any automodification of the base register. Unlike 805 // `m', this constraint can be used in asm statements that 806 // might access the operand several times, or that might not 807 // access it at all. 808 Info.setAllowsMemory(); 809 Name++; // Skip over 'e'. 810 break; 811 case 'Q': // Memory operand that is an offset from a register (it is 812 // usually better to use `m' or `es' in asm statements) 813 case 'Z': // Memory operand that is an indexed or indirect from a 814 // register (it is usually better to use `m' or `es' in 815 // asm statements) 816 Info.setAllowsMemory(); 817 Info.setAllowsRegister(); 818 break; 819 case 'R': // AIX TOC entry 820 case 'a': // Address operand that is an indexed or indirect from a 821 // register (`p' is preferable for asm statements) 822 case 'S': // Constant suitable as a 64-bit mask operand 823 case 'T': // Constant suitable as a 32-bit mask operand 824 case 'U': // System V Release 4 small data area reference 825 case 't': // AND masks that can be performed by two rldic{l, r} 826 // instructions 827 case 'W': // Vector constant that does not require memory 828 case 'j': // Vector constant that is all zeros. 829 break; 830 // End FIXME. 831 } 832 return true; 833 } 834 virtual const char *getClobbers() const { 835 return ""; 836 } 837 int getEHDataRegisterNumber(unsigned RegNo) const { 838 if (RegNo == 0) return 3; 839 if (RegNo == 1) return 4; 840 return -1; 841 } 842 }; 843 844 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 845 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 846 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 847 ALL_LANGUAGES }, 848 #include "clang/Basic/BuiltinsPPC.def" 849 }; 850 851 852 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 853 /// #defines that are not tied to a specific subtarget. 854 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 855 MacroBuilder &Builder) const { 856 // Target identification. 857 Builder.defineMacro("__ppc__"); 858 Builder.defineMacro("__PPC__"); 859 Builder.defineMacro("_ARCH_PPC"); 860 Builder.defineMacro("__powerpc__"); 861 Builder.defineMacro("__POWERPC__"); 862 if (PointerWidth == 64) { 863 Builder.defineMacro("_ARCH_PPC64"); 864 Builder.defineMacro("__powerpc64__"); 865 Builder.defineMacro("__ppc64__"); 866 Builder.defineMacro("__PPC64__"); 867 } 868 869 // Target properties. 870 if (getTriple().getArch() == llvm::Triple::ppc64le) { 871 Builder.defineMacro("_LITTLE_ENDIAN"); 872 Builder.defineMacro("__LITTLE_ENDIAN__"); 873 } else { 874 if (getTriple().getOS() != llvm::Triple::NetBSD && 875 getTriple().getOS() != llvm::Triple::OpenBSD) 876 Builder.defineMacro("_BIG_ENDIAN"); 877 Builder.defineMacro("__BIG_ENDIAN__"); 878 } 879 880 // Subtarget options. 881 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 882 Builder.defineMacro("__REGISTER_PREFIX__", ""); 883 884 // FIXME: Should be controlled by command line option. 885 if (LongDoubleWidth == 128) 886 Builder.defineMacro("__LONG_DOUBLE_128__"); 887 888 if (Opts.AltiVec) { 889 Builder.defineMacro("__VEC__", "10206"); 890 Builder.defineMacro("__ALTIVEC__"); 891 } 892 893 // CPU identification. 894 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 895 .Case("440", ArchDefineName) 896 .Case("450", ArchDefineName | ArchDefine440) 897 .Case("601", ArchDefineName) 898 .Case("602", ArchDefineName | ArchDefinePpcgr) 899 .Case("603", ArchDefineName | ArchDefinePpcgr) 900 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 901 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 902 .Case("604", ArchDefineName | ArchDefinePpcgr) 903 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 904 .Case("620", ArchDefineName | ArchDefinePpcgr) 905 .Case("630", ArchDefineName | ArchDefinePpcgr) 906 .Case("7400", ArchDefineName | ArchDefinePpcgr) 907 .Case("7450", ArchDefineName | ArchDefinePpcgr) 908 .Case("750", ArchDefineName | ArchDefinePpcgr) 909 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 910 | ArchDefinePpcsq) 911 .Case("a2", ArchDefineA2) 912 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 913 .Case("pwr3", ArchDefinePpcgr) 914 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 915 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 916 | ArchDefinePpcsq) 917 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 918 | ArchDefinePpcgr | ArchDefinePpcsq) 919 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 920 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 921 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 922 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 923 | ArchDefinePpcsq) 924 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 925 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 926 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 927 .Case("power3", ArchDefinePpcgr) 928 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 929 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 930 | ArchDefinePpcsq) 931 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 932 | ArchDefinePpcgr | ArchDefinePpcsq) 933 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 934 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 935 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 936 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 937 | ArchDefinePpcsq) 938 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 939 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 940 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 941 .Default(ArchDefineNone); 942 943 if (defs & ArchDefineName) 944 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 945 if (defs & ArchDefinePpcgr) 946 Builder.defineMacro("_ARCH_PPCGR"); 947 if (defs & ArchDefinePpcsq) 948 Builder.defineMacro("_ARCH_PPCSQ"); 949 if (defs & ArchDefine440) 950 Builder.defineMacro("_ARCH_440"); 951 if (defs & ArchDefine603) 952 Builder.defineMacro("_ARCH_603"); 953 if (defs & ArchDefine604) 954 Builder.defineMacro("_ARCH_604"); 955 if (defs & ArchDefinePwr4) 956 Builder.defineMacro("_ARCH_PWR4"); 957 if (defs & ArchDefinePwr5) 958 Builder.defineMacro("_ARCH_PWR5"); 959 if (defs & ArchDefinePwr5x) 960 Builder.defineMacro("_ARCH_PWR5X"); 961 if (defs & ArchDefinePwr6) 962 Builder.defineMacro("_ARCH_PWR6"); 963 if (defs & ArchDefinePwr6x) 964 Builder.defineMacro("_ARCH_PWR6X"); 965 if (defs & ArchDefinePwr7) 966 Builder.defineMacro("_ARCH_PWR7"); 967 if (defs & ArchDefineA2) 968 Builder.defineMacro("_ARCH_A2"); 969 if (defs & ArchDefineA2q) { 970 Builder.defineMacro("_ARCH_A2Q"); 971 Builder.defineMacro("_ARCH_QP"); 972 } 973 974 if (getTriple().getVendor() == llvm::Triple::BGQ) { 975 Builder.defineMacro("__bg__"); 976 Builder.defineMacro("__THW_BLUEGENE__"); 977 Builder.defineMacro("__bgq__"); 978 Builder.defineMacro("__TOS_BGQ__"); 979 } 980 981 // FIXME: The following are not yet generated here by Clang, but are 982 // generated by GCC: 983 // 984 // _SOFT_FLOAT_ 985 // __RECIP_PRECISION__ 986 // __APPLE_ALTIVEC__ 987 // __VSX__ 988 // __RECIP__ 989 // __RECIPF__ 990 // __RSQRTE__ 991 // __RSQRTEF__ 992 // _SOFT_DOUBLE_ 993 // __NO_LWSYNC__ 994 // __HAVE_BSWAP__ 995 // __LONGDOUBLE128 996 // __CMODEL_MEDIUM__ 997 // __CMODEL_LARGE__ 998 // _CALL_SYSV 999 // _CALL_DARWIN 1000 // __NO_FPRS__ 1001 } 1002 1003 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1004 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1005 .Case("7400", true) 1006 .Case("g4", true) 1007 .Case("7450", true) 1008 .Case("g4+", true) 1009 .Case("970", true) 1010 .Case("g5", true) 1011 .Case("pwr6", true) 1012 .Case("pwr7", true) 1013 .Case("ppc64", true) 1014 .Case("ppc64le", true) 1015 .Default(false); 1016 1017 Features["qpx"] = (CPU == "a2q"); 1018 } 1019 1020 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1021 return Feature == "powerpc"; 1022 } 1023 1024 1025 const char * const PPCTargetInfo::GCCRegNames[] = { 1026 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1027 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1028 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1029 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1030 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1031 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1032 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1033 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1034 "mq", "lr", "ctr", "ap", 1035 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1036 "xer", 1037 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1038 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1039 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1040 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1041 "vrsave", "vscr", 1042 "spe_acc", "spefscr", 1043 "sfp" 1044 }; 1045 1046 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1047 unsigned &NumNames) const { 1048 Names = GCCRegNames; 1049 NumNames = llvm::array_lengthof(GCCRegNames); 1050 } 1051 1052 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1053 // While some of these aliases do map to different registers 1054 // they still share the same register name. 1055 { { "0" }, "r0" }, 1056 { { "1"}, "r1" }, 1057 { { "2" }, "r2" }, 1058 { { "3" }, "r3" }, 1059 { { "4" }, "r4" }, 1060 { { "5" }, "r5" }, 1061 { { "6" }, "r6" }, 1062 { { "7" }, "r7" }, 1063 { { "8" }, "r8" }, 1064 { { "9" }, "r9" }, 1065 { { "10" }, "r10" }, 1066 { { "11" }, "r11" }, 1067 { { "12" }, "r12" }, 1068 { { "13" }, "r13" }, 1069 { { "14" }, "r14" }, 1070 { { "15" }, "r15" }, 1071 { { "16" }, "r16" }, 1072 { { "17" }, "r17" }, 1073 { { "18" }, "r18" }, 1074 { { "19" }, "r19" }, 1075 { { "20" }, "r20" }, 1076 { { "21" }, "r21" }, 1077 { { "22" }, "r22" }, 1078 { { "23" }, "r23" }, 1079 { { "24" }, "r24" }, 1080 { { "25" }, "r25" }, 1081 { { "26" }, "r26" }, 1082 { { "27" }, "r27" }, 1083 { { "28" }, "r28" }, 1084 { { "29" }, "r29" }, 1085 { { "30" }, "r30" }, 1086 { { "31" }, "r31" }, 1087 { { "fr0" }, "f0" }, 1088 { { "fr1" }, "f1" }, 1089 { { "fr2" }, "f2" }, 1090 { { "fr3" }, "f3" }, 1091 { { "fr4" }, "f4" }, 1092 { { "fr5" }, "f5" }, 1093 { { "fr6" }, "f6" }, 1094 { { "fr7" }, "f7" }, 1095 { { "fr8" }, "f8" }, 1096 { { "fr9" }, "f9" }, 1097 { { "fr10" }, "f10" }, 1098 { { "fr11" }, "f11" }, 1099 { { "fr12" }, "f12" }, 1100 { { "fr13" }, "f13" }, 1101 { { "fr14" }, "f14" }, 1102 { { "fr15" }, "f15" }, 1103 { { "fr16" }, "f16" }, 1104 { { "fr17" }, "f17" }, 1105 { { "fr18" }, "f18" }, 1106 { { "fr19" }, "f19" }, 1107 { { "fr20" }, "f20" }, 1108 { { "fr21" }, "f21" }, 1109 { { "fr22" }, "f22" }, 1110 { { "fr23" }, "f23" }, 1111 { { "fr24" }, "f24" }, 1112 { { "fr25" }, "f25" }, 1113 { { "fr26" }, "f26" }, 1114 { { "fr27" }, "f27" }, 1115 { { "fr28" }, "f28" }, 1116 { { "fr29" }, "f29" }, 1117 { { "fr30" }, "f30" }, 1118 { { "fr31" }, "f31" }, 1119 { { "cc" }, "cr0" }, 1120 }; 1121 1122 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1123 unsigned &NumAliases) const { 1124 Aliases = GCCRegAliases; 1125 NumAliases = llvm::array_lengthof(GCCRegAliases); 1126 } 1127 } // end anonymous namespace. 1128 1129 namespace { 1130 class PPC32TargetInfo : public PPCTargetInfo { 1131 public: 1132 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1133 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1134 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1135 1136 switch (getTriple().getOS()) { 1137 case llvm::Triple::Linux: 1138 case llvm::Triple::FreeBSD: 1139 case llvm::Triple::NetBSD: 1140 SizeType = UnsignedInt; 1141 PtrDiffType = SignedInt; 1142 IntPtrType = SignedInt; 1143 break; 1144 default: 1145 break; 1146 } 1147 1148 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1149 LongDoubleWidth = LongDoubleAlign = 64; 1150 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1151 } 1152 1153 // PPC32 supports atomics up to 4 bytes. 1154 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1155 } 1156 1157 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1158 // This is the ELF definition, and is overridden by the Darwin sub-target 1159 return TargetInfo::PowerABIBuiltinVaList; 1160 } 1161 }; 1162 } // end anonymous namespace. 1163 1164 // Note: ABI differences may eventually require us to have a separate 1165 // TargetInfo for little endian. 1166 namespace { 1167 class PPC64TargetInfo : public PPCTargetInfo { 1168 public: 1169 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1170 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1171 IntMaxType = SignedLong; 1172 UIntMaxType = UnsignedLong; 1173 Int64Type = SignedLong; 1174 1175 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1176 LongDoubleWidth = LongDoubleAlign = 64; 1177 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1178 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1179 "i64:64:64-f32:32:32-f64:64:64-" 1180 "v128:128:128-n32:64"; 1181 } else 1182 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1183 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 1184 "v128:128:128-n32:64"; 1185 1186 // PPC64 supports atomics up to 8 bytes. 1187 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1188 } 1189 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1190 return TargetInfo::CharPtrBuiltinVaList; 1191 } 1192 }; 1193 } // end anonymous namespace. 1194 1195 1196 namespace { 1197 class DarwinPPC32TargetInfo : 1198 public DarwinTargetInfo<PPC32TargetInfo> { 1199 public: 1200 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1201 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1202 HasAlignMac68kSupport = true; 1203 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1204 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1205 LongLongAlign = 32; 1206 SuitableAlign = 128; 1207 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1208 "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1209 } 1210 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1211 return TargetInfo::CharPtrBuiltinVaList; 1212 } 1213 }; 1214 1215 class DarwinPPC64TargetInfo : 1216 public DarwinTargetInfo<PPC64TargetInfo> { 1217 public: 1218 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1219 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1220 HasAlignMac68kSupport = true; 1221 SuitableAlign = 128; 1222 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1223 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"; 1224 } 1225 }; 1226 } // end anonymous namespace. 1227 1228 namespace { 1229 static const unsigned NVPTXAddrSpaceMap[] = { 1230 1, // opencl_global 1231 3, // opencl_local 1232 4, // opencl_constant 1233 1, // cuda_device 1234 4, // cuda_constant 1235 3, // cuda_shared 1236 }; 1237 class NVPTXTargetInfo : public TargetInfo { 1238 static const char * const GCCRegNames[]; 1239 static const Builtin::Info BuiltinInfo[]; 1240 public: 1241 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1242 BigEndian = false; 1243 TLSSupported = false; 1244 LongWidth = LongAlign = 64; 1245 AddrSpaceMap = &NVPTXAddrSpaceMap; 1246 // Define available target features 1247 // These must be defined in sorted order! 1248 NoAsmVariants = true; 1249 } 1250 virtual void getTargetDefines(const LangOptions &Opts, 1251 MacroBuilder &Builder) const { 1252 Builder.defineMacro("__PTX__"); 1253 Builder.defineMacro("__NVPTX__"); 1254 } 1255 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1256 unsigned &NumRecords) const { 1257 Records = BuiltinInfo; 1258 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1259 } 1260 virtual bool hasFeature(StringRef Feature) const { 1261 return Feature == "ptx" || Feature == "nvptx"; 1262 } 1263 1264 virtual void getGCCRegNames(const char * const *&Names, 1265 unsigned &NumNames) const; 1266 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1267 unsigned &NumAliases) const { 1268 // No aliases. 1269 Aliases = 0; 1270 NumAliases = 0; 1271 } 1272 virtual bool validateAsmConstraint(const char *&Name, 1273 TargetInfo::ConstraintInfo &Info) const { 1274 switch (*Name) { 1275 default: return false; 1276 case 'c': 1277 case 'h': 1278 case 'r': 1279 case 'l': 1280 case 'f': 1281 case 'd': 1282 Info.setAllowsRegister(); 1283 return true; 1284 } 1285 } 1286 virtual const char *getClobbers() const { 1287 // FIXME: Is this really right? 1288 return ""; 1289 } 1290 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1291 // FIXME: implement 1292 return TargetInfo::CharPtrBuiltinVaList; 1293 } 1294 virtual bool setCPU(const std::string &Name) { 1295 bool Valid = llvm::StringSwitch<bool>(Name) 1296 .Case("sm_20", true) 1297 .Case("sm_21", true) 1298 .Case("sm_30", true) 1299 .Case("sm_35", true) 1300 .Default(false); 1301 1302 return Valid; 1303 } 1304 }; 1305 1306 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1307 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1308 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1309 ALL_LANGUAGES }, 1310 #include "clang/Basic/BuiltinsNVPTX.def" 1311 }; 1312 1313 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1314 "r0" 1315 }; 1316 1317 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1318 unsigned &NumNames) const { 1319 Names = GCCRegNames; 1320 NumNames = llvm::array_lengthof(GCCRegNames); 1321 } 1322 1323 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1324 public: 1325 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1326 PointerWidth = PointerAlign = 32; 1327 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1328 DescriptionString 1329 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1330 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1331 "n16:32:64"; 1332 } 1333 }; 1334 1335 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1336 public: 1337 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1338 PointerWidth = PointerAlign = 64; 1339 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1340 DescriptionString 1341 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1342 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1343 "n16:32:64"; 1344 } 1345 }; 1346 } 1347 1348 namespace { 1349 1350 static const unsigned R600AddrSpaceMap[] = { 1351 1, // opencl_global 1352 3, // opencl_local 1353 2, // opencl_constant 1354 1, // cuda_device 1355 2, // cuda_constant 1356 3 // cuda_shared 1357 }; 1358 1359 static const char *DescriptionStringR600 = 1360 "e" 1361 "-p:32:32:32" 1362 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32" 1363 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1364 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1365 "-n32:64"; 1366 1367 static const char *DescriptionStringR600DoubleOps = 1368 "e" 1369 "-p:32:32:32" 1370 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64" 1371 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1372 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1373 "-n32:64"; 1374 1375 static const char *DescriptionStringSI = 1376 "e" 1377 "-p:64:64:64" 1378 "-p3:32:32:32" 1379 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64" 1380 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1381 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1382 "-n32:64"; 1383 1384 class R600TargetInfo : public TargetInfo { 1385 /// \brief The GPU profiles supported by the R600 target. 1386 enum GPUKind { 1387 GK_NONE, 1388 GK_R600, 1389 GK_R600_DOUBLE_OPS, 1390 GK_R700, 1391 GK_R700_DOUBLE_OPS, 1392 GK_EVERGREEN, 1393 GK_EVERGREEN_DOUBLE_OPS, 1394 GK_NORTHERN_ISLANDS, 1395 GK_CAYMAN, 1396 GK_SOUTHERN_ISLANDS 1397 } GPU; 1398 1399 public: 1400 R600TargetInfo(const llvm::Triple &Triple) 1401 : TargetInfo(Triple), GPU(GK_R600) { 1402 DescriptionString = DescriptionStringR600; 1403 AddrSpaceMap = &R600AddrSpaceMap; 1404 } 1405 1406 virtual const char * getClobbers() const { 1407 return ""; 1408 } 1409 1410 virtual void getGCCRegNames(const char * const *&Names, 1411 unsigned &numNames) const { 1412 Names = NULL; 1413 numNames = 0; 1414 } 1415 1416 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1417 unsigned &NumAliases) const { 1418 Aliases = NULL; 1419 NumAliases = 0; 1420 } 1421 1422 virtual bool validateAsmConstraint(const char *&Name, 1423 TargetInfo::ConstraintInfo &info) const { 1424 return true; 1425 } 1426 1427 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1428 unsigned &NumRecords) const { 1429 Records = NULL; 1430 NumRecords = 0; 1431 } 1432 1433 1434 virtual void getTargetDefines(const LangOptions &Opts, 1435 MacroBuilder &Builder) const { 1436 Builder.defineMacro("__R600__"); 1437 } 1438 1439 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1440 return TargetInfo::CharPtrBuiltinVaList; 1441 } 1442 1443 virtual bool setCPU(const std::string &Name) { 1444 GPU = llvm::StringSwitch<GPUKind>(Name) 1445 .Case("r600" , GK_R600) 1446 .Case("rv610", GK_R600) 1447 .Case("rv620", GK_R600) 1448 .Case("rv630", GK_R600) 1449 .Case("rv635", GK_R600) 1450 .Case("rs780", GK_R600) 1451 .Case("rs880", GK_R600) 1452 .Case("rv670", GK_R600_DOUBLE_OPS) 1453 .Case("rv710", GK_R700) 1454 .Case("rv730", GK_R700) 1455 .Case("rv740", GK_R700_DOUBLE_OPS) 1456 .Case("rv770", GK_R700_DOUBLE_OPS) 1457 .Case("palm", GK_EVERGREEN) 1458 .Case("cedar", GK_EVERGREEN) 1459 .Case("sumo", GK_EVERGREEN) 1460 .Case("sumo2", GK_EVERGREEN) 1461 .Case("redwood", GK_EVERGREEN) 1462 .Case("juniper", GK_EVERGREEN) 1463 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1464 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1465 .Case("barts", GK_NORTHERN_ISLANDS) 1466 .Case("turks", GK_NORTHERN_ISLANDS) 1467 .Case("caicos", GK_NORTHERN_ISLANDS) 1468 .Case("cayman", GK_CAYMAN) 1469 .Case("aruba", GK_CAYMAN) 1470 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1471 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1472 .Case("verde", GK_SOUTHERN_ISLANDS) 1473 .Case("oland", GK_SOUTHERN_ISLANDS) 1474 .Default(GK_NONE); 1475 1476 if (GPU == GK_NONE) { 1477 return false; 1478 } 1479 1480 // Set the correct data layout 1481 switch (GPU) { 1482 case GK_NONE: 1483 case GK_R600: 1484 case GK_R700: 1485 case GK_EVERGREEN: 1486 case GK_NORTHERN_ISLANDS: 1487 DescriptionString = DescriptionStringR600; 1488 break; 1489 case GK_R600_DOUBLE_OPS: 1490 case GK_R700_DOUBLE_OPS: 1491 case GK_EVERGREEN_DOUBLE_OPS: 1492 case GK_CAYMAN: 1493 DescriptionString = DescriptionStringR600DoubleOps; 1494 break; 1495 case GK_SOUTHERN_ISLANDS: 1496 DescriptionString = DescriptionStringSI; 1497 break; 1498 } 1499 1500 return true; 1501 } 1502 }; 1503 1504 } // end anonymous namespace 1505 1506 namespace { 1507 // Namespace for x86 abstract base class 1508 const Builtin::Info BuiltinInfo[] = { 1509 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1510 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1511 ALL_LANGUAGES }, 1512 #include "clang/Basic/BuiltinsX86.def" 1513 }; 1514 1515 static const char* const GCCRegNames[] = { 1516 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1517 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1518 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1519 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1520 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1521 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1522 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1523 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1524 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1525 }; 1526 1527 const TargetInfo::AddlRegName AddlRegNames[] = { 1528 { { "al", "ah", "eax", "rax" }, 0 }, 1529 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1530 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1531 { { "dl", "dh", "edx", "rdx" }, 1 }, 1532 { { "esi", "rsi" }, 4 }, 1533 { { "edi", "rdi" }, 5 }, 1534 { { "esp", "rsp" }, 7 }, 1535 { { "ebp", "rbp" }, 6 }, 1536 }; 1537 1538 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1539 // most of the implementation can be shared. 1540 class X86TargetInfo : public TargetInfo { 1541 enum X86SSEEnum { 1542 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1543 } SSELevel; 1544 enum MMX3DNowEnum { 1545 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1546 } MMX3DNowLevel; 1547 enum XOPEnum { 1548 NoXOP, 1549 SSE4A, 1550 FMA4, 1551 XOP 1552 } XOPLevel; 1553 1554 bool HasAES; 1555 bool HasPCLMUL; 1556 bool HasLZCNT; 1557 bool HasRDRND; 1558 bool HasBMI; 1559 bool HasBMI2; 1560 bool HasPOPCNT; 1561 bool HasRTM; 1562 bool HasPRFCHW; 1563 bool HasRDSEED; 1564 bool HasFMA; 1565 bool HasF16C; 1566 bool HasAVX512CD, HasAVX512ER, HasAVX512PF; 1567 1568 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1569 /// 1570 /// Each enumeration represents a particular CPU supported by Clang. These 1571 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1572 enum CPUKind { 1573 CK_Generic, 1574 1575 /// \name i386 1576 /// i386-generation processors. 1577 //@{ 1578 CK_i386, 1579 //@} 1580 1581 /// \name i486 1582 /// i486-generation processors. 1583 //@{ 1584 CK_i486, 1585 CK_WinChipC6, 1586 CK_WinChip2, 1587 CK_C3, 1588 //@} 1589 1590 /// \name i586 1591 /// i586-generation processors, P5 microarchitecture based. 1592 //@{ 1593 CK_i586, 1594 CK_Pentium, 1595 CK_PentiumMMX, 1596 //@} 1597 1598 /// \name i686 1599 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1600 //@{ 1601 CK_i686, 1602 CK_PentiumPro, 1603 CK_Pentium2, 1604 CK_Pentium3, 1605 CK_Pentium3M, 1606 CK_PentiumM, 1607 CK_C3_2, 1608 1609 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1610 /// Clang however has some logic to suport this. 1611 // FIXME: Warn, deprecate, and potentially remove this. 1612 CK_Yonah, 1613 //@} 1614 1615 /// \name Netburst 1616 /// Netburst microarchitecture based processors. 1617 //@{ 1618 CK_Pentium4, 1619 CK_Pentium4M, 1620 CK_Prescott, 1621 CK_Nocona, 1622 //@} 1623 1624 /// \name Core 1625 /// Core microarchitecture based processors. 1626 //@{ 1627 CK_Core2, 1628 1629 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1630 /// codename which GCC no longer accepts as an option to -march, but Clang 1631 /// has some logic for recognizing it. 1632 // FIXME: Warn, deprecate, and potentially remove this. 1633 CK_Penryn, 1634 //@} 1635 1636 /// \name Atom 1637 /// Atom processors 1638 //@{ 1639 CK_Atom, 1640 CK_SLM, 1641 //@} 1642 1643 /// \name Nehalem 1644 /// Nehalem microarchitecture based processors. 1645 //@{ 1646 CK_Corei7, 1647 CK_Corei7AVX, 1648 CK_CoreAVXi, 1649 CK_CoreAVX2, 1650 //@} 1651 1652 /// \name Knights Landing 1653 /// Knights Landing processor. 1654 CK_KNL, 1655 1656 /// \name K6 1657 /// K6 architecture processors. 1658 //@{ 1659 CK_K6, 1660 CK_K6_2, 1661 CK_K6_3, 1662 //@} 1663 1664 /// \name K7 1665 /// K7 architecture processors. 1666 //@{ 1667 CK_Athlon, 1668 CK_AthlonThunderbird, 1669 CK_Athlon4, 1670 CK_AthlonXP, 1671 CK_AthlonMP, 1672 //@} 1673 1674 /// \name K8 1675 /// K8 architecture processors. 1676 //@{ 1677 CK_Athlon64, 1678 CK_Athlon64SSE3, 1679 CK_AthlonFX, 1680 CK_K8, 1681 CK_K8SSE3, 1682 CK_Opteron, 1683 CK_OpteronSSE3, 1684 CK_AMDFAM10, 1685 //@} 1686 1687 /// \name Bobcat 1688 /// Bobcat architecture processors. 1689 //@{ 1690 CK_BTVER1, 1691 CK_BTVER2, 1692 //@} 1693 1694 /// \name Bulldozer 1695 /// Bulldozer architecture processors. 1696 //@{ 1697 CK_BDVER1, 1698 CK_BDVER2, 1699 //@} 1700 1701 /// This specification is deprecated and will be removed in the future. 1702 /// Users should prefer \see CK_K8. 1703 // FIXME: Warn on this when the CPU is set to it. 1704 CK_x86_64, 1705 //@} 1706 1707 /// \name Geode 1708 /// Geode processors. 1709 //@{ 1710 CK_Geode 1711 //@} 1712 } CPU; 1713 1714 enum FPMathKind { 1715 FP_Default, 1716 FP_SSE, 1717 FP_387 1718 } FPMath; 1719 1720 public: 1721 X86TargetInfo(const llvm::Triple &Triple) 1722 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1723 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1724 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1725 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasFMA(false), 1726 HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1727 HasAVX512PF(false), CPU(CK_Generic), FPMath(FP_Default) { 1728 BigEndian = false; 1729 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1730 } 1731 virtual unsigned getFloatEvalMethod() const { 1732 // X87 evaluates with 80 bits "long double" precision. 1733 return SSELevel == NoSSE ? 2 : 0; 1734 } 1735 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1736 unsigned &NumRecords) const { 1737 Records = BuiltinInfo; 1738 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1739 } 1740 virtual void getGCCRegNames(const char * const *&Names, 1741 unsigned &NumNames) const { 1742 Names = GCCRegNames; 1743 NumNames = llvm::array_lengthof(GCCRegNames); 1744 } 1745 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1746 unsigned &NumAliases) const { 1747 Aliases = 0; 1748 NumAliases = 0; 1749 } 1750 virtual void getGCCAddlRegNames(const AddlRegName *&Names, 1751 unsigned &NumNames) const { 1752 Names = AddlRegNames; 1753 NumNames = llvm::array_lengthof(AddlRegNames); 1754 } 1755 virtual bool validateAsmConstraint(const char *&Name, 1756 TargetInfo::ConstraintInfo &info) const; 1757 virtual std::string convertConstraint(const char *&Constraint) const; 1758 virtual const char *getClobbers() const { 1759 return "~{dirflag},~{fpsr},~{flags}"; 1760 } 1761 virtual void getTargetDefines(const LangOptions &Opts, 1762 MacroBuilder &Builder) const; 1763 void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1764 bool Enabled) const; 1765 void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1766 bool Enabled) const; 1767 void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1768 bool Enabled) const; 1769 virtual void setFeatureEnabled(llvm::StringMap<bool> &Features, 1770 StringRef Name, 1771 bool Enabled) const; 1772 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 1773 virtual bool hasFeature(StringRef Feature) const; 1774 virtual bool HandleTargetFeatures(std::vector<std::string> &Features, 1775 DiagnosticsEngine &Diags); 1776 virtual const char* getABI() const { 1777 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1778 return "avx"; 1779 else if (getTriple().getArch() == llvm::Triple::x86 && 1780 MMX3DNowLevel == NoMMX3DNow) 1781 return "no-mmx"; 1782 return ""; 1783 } 1784 virtual bool setCPU(const std::string &Name) { 1785 CPU = llvm::StringSwitch<CPUKind>(Name) 1786 .Case("i386", CK_i386) 1787 .Case("i486", CK_i486) 1788 .Case("winchip-c6", CK_WinChipC6) 1789 .Case("winchip2", CK_WinChip2) 1790 .Case("c3", CK_C3) 1791 .Case("i586", CK_i586) 1792 .Case("pentium", CK_Pentium) 1793 .Case("pentium-mmx", CK_PentiumMMX) 1794 .Case("i686", CK_i686) 1795 .Case("pentiumpro", CK_PentiumPro) 1796 .Case("pentium2", CK_Pentium2) 1797 .Case("pentium3", CK_Pentium3) 1798 .Case("pentium3m", CK_Pentium3M) 1799 .Case("pentium-m", CK_PentiumM) 1800 .Case("c3-2", CK_C3_2) 1801 .Case("yonah", CK_Yonah) 1802 .Case("pentium4", CK_Pentium4) 1803 .Case("pentium4m", CK_Pentium4M) 1804 .Case("prescott", CK_Prescott) 1805 .Case("nocona", CK_Nocona) 1806 .Case("core2", CK_Core2) 1807 .Case("penryn", CK_Penryn) 1808 .Case("atom", CK_Atom) 1809 .Case("slm", CK_SLM) 1810 .Case("corei7", CK_Corei7) 1811 .Case("corei7-avx", CK_Corei7AVX) 1812 .Case("core-avx-i", CK_CoreAVXi) 1813 .Case("core-avx2", CK_CoreAVX2) 1814 .Case("knl", CK_KNL) 1815 .Case("k6", CK_K6) 1816 .Case("k6-2", CK_K6_2) 1817 .Case("k6-3", CK_K6_3) 1818 .Case("athlon", CK_Athlon) 1819 .Case("athlon-tbird", CK_AthlonThunderbird) 1820 .Case("athlon-4", CK_Athlon4) 1821 .Case("athlon-xp", CK_AthlonXP) 1822 .Case("athlon-mp", CK_AthlonMP) 1823 .Case("athlon64", CK_Athlon64) 1824 .Case("athlon64-sse3", CK_Athlon64SSE3) 1825 .Case("athlon-fx", CK_AthlonFX) 1826 .Case("k8", CK_K8) 1827 .Case("k8-sse3", CK_K8SSE3) 1828 .Case("opteron", CK_Opteron) 1829 .Case("opteron-sse3", CK_OpteronSSE3) 1830 .Case("amdfam10", CK_AMDFAM10) 1831 .Case("btver1", CK_BTVER1) 1832 .Case("btver2", CK_BTVER2) 1833 .Case("bdver1", CK_BDVER1) 1834 .Case("bdver2", CK_BDVER2) 1835 .Case("x86-64", CK_x86_64) 1836 .Case("geode", CK_Geode) 1837 .Default(CK_Generic); 1838 1839 // Perform any per-CPU checks necessary to determine if this CPU is 1840 // acceptable. 1841 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1842 // invalid without explaining *why*. 1843 switch (CPU) { 1844 case CK_Generic: 1845 // No processor selected! 1846 return false; 1847 1848 case CK_i386: 1849 case CK_i486: 1850 case CK_WinChipC6: 1851 case CK_WinChip2: 1852 case CK_C3: 1853 case CK_i586: 1854 case CK_Pentium: 1855 case CK_PentiumMMX: 1856 case CK_i686: 1857 case CK_PentiumPro: 1858 case CK_Pentium2: 1859 case CK_Pentium3: 1860 case CK_Pentium3M: 1861 case CK_PentiumM: 1862 case CK_Yonah: 1863 case CK_C3_2: 1864 case CK_Pentium4: 1865 case CK_Pentium4M: 1866 case CK_Prescott: 1867 case CK_K6: 1868 case CK_K6_2: 1869 case CK_K6_3: 1870 case CK_Athlon: 1871 case CK_AthlonThunderbird: 1872 case CK_Athlon4: 1873 case CK_AthlonXP: 1874 case CK_AthlonMP: 1875 case CK_Geode: 1876 // Only accept certain architectures when compiling in 32-bit mode. 1877 if (getTriple().getArch() != llvm::Triple::x86) 1878 return false; 1879 1880 // Fallthrough 1881 case CK_Nocona: 1882 case CK_Core2: 1883 case CK_Penryn: 1884 case CK_Atom: 1885 case CK_SLM: 1886 case CK_Corei7: 1887 case CK_Corei7AVX: 1888 case CK_CoreAVXi: 1889 case CK_CoreAVX2: 1890 case CK_KNL: 1891 case CK_Athlon64: 1892 case CK_Athlon64SSE3: 1893 case CK_AthlonFX: 1894 case CK_K8: 1895 case CK_K8SSE3: 1896 case CK_Opteron: 1897 case CK_OpteronSSE3: 1898 case CK_AMDFAM10: 1899 case CK_BTVER1: 1900 case CK_BTVER2: 1901 case CK_BDVER1: 1902 case CK_BDVER2: 1903 case CK_x86_64: 1904 return true; 1905 } 1906 llvm_unreachable("Unhandled CPU kind"); 1907 } 1908 1909 virtual bool setFPMath(StringRef Name); 1910 1911 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 1912 // We accept all non-ARM calling conventions 1913 return (CC == CC_X86ThisCall || 1914 CC == CC_X86FastCall || 1915 CC == CC_X86StdCall || 1916 CC == CC_C || 1917 CC == CC_X86Pascal || 1918 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 1919 } 1920 1921 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 1922 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 1923 } 1924 }; 1925 1926 bool X86TargetInfo::setFPMath(StringRef Name) { 1927 if (Name == "387") { 1928 FPMath = FP_387; 1929 return true; 1930 } 1931 if (Name == "sse") { 1932 FPMath = FP_SSE; 1933 return true; 1934 } 1935 return false; 1936 } 1937 1938 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1939 // FIXME: This *really* should not be here. 1940 1941 // X86_64 always has SSE2. 1942 if (getTriple().getArch() == llvm::Triple::x86_64) 1943 setFeatureEnabled(Features, "sse2", true); 1944 1945 switch (CPU) { 1946 case CK_Generic: 1947 case CK_i386: 1948 case CK_i486: 1949 case CK_i586: 1950 case CK_Pentium: 1951 case CK_i686: 1952 case CK_PentiumPro: 1953 break; 1954 case CK_PentiumMMX: 1955 case CK_Pentium2: 1956 setFeatureEnabled(Features, "mmx", true); 1957 break; 1958 case CK_Pentium3: 1959 case CK_Pentium3M: 1960 setFeatureEnabled(Features, "sse", true); 1961 break; 1962 case CK_PentiumM: 1963 case CK_Pentium4: 1964 case CK_Pentium4M: 1965 case CK_x86_64: 1966 setFeatureEnabled(Features, "sse2", true); 1967 break; 1968 case CK_Yonah: 1969 case CK_Prescott: 1970 case CK_Nocona: 1971 setFeatureEnabled(Features, "sse3", true); 1972 break; 1973 case CK_Core2: 1974 setFeatureEnabled(Features, "ssse3", true); 1975 break; 1976 case CK_Penryn: 1977 setFeatureEnabled(Features, "sse4.1", true); 1978 break; 1979 case CK_Atom: 1980 setFeatureEnabled(Features, "ssse3", true); 1981 break; 1982 case CK_Corei7: 1983 case CK_SLM: 1984 setFeatureEnabled(Features, "sse4.2", true); 1985 break; 1986 case CK_Corei7AVX: 1987 setFeatureEnabled(Features, "avx", true); 1988 setFeatureEnabled(Features, "aes", true); 1989 setFeatureEnabled(Features, "pclmul", true); 1990 break; 1991 case CK_CoreAVXi: 1992 setFeatureEnabled(Features, "avx", true); 1993 setFeatureEnabled(Features, "aes", true); 1994 setFeatureEnabled(Features, "pclmul", true); 1995 setFeatureEnabled(Features, "rdrnd", true); 1996 setFeatureEnabled(Features, "f16c", true); 1997 break; 1998 case CK_CoreAVX2: 1999 setFeatureEnabled(Features, "avx2", true); 2000 setFeatureEnabled(Features, "aes", true); 2001 setFeatureEnabled(Features, "pclmul", true); 2002 setFeatureEnabled(Features, "lzcnt", true); 2003 setFeatureEnabled(Features, "rdrnd", true); 2004 setFeatureEnabled(Features, "f16c", true); 2005 setFeatureEnabled(Features, "bmi", true); 2006 setFeatureEnabled(Features, "bmi2", true); 2007 setFeatureEnabled(Features, "rtm", true); 2008 setFeatureEnabled(Features, "fma", true); 2009 break; 2010 case CK_KNL: 2011 setFeatureEnabled(Features, "avx512f", true); 2012 setFeatureEnabled(Features, "avx512cd", true); 2013 setFeatureEnabled(Features, "avx512er", true); 2014 setFeatureEnabled(Features, "avx512pf", true); 2015 setFeatureEnabled(Features, "aes", true); 2016 setFeatureEnabled(Features, "pclmul", true); 2017 setFeatureEnabled(Features, "lzcnt", true); 2018 setFeatureEnabled(Features, "rdrnd", true); 2019 setFeatureEnabled(Features, "f16c", true); 2020 setFeatureEnabled(Features, "bmi", true); 2021 setFeatureEnabled(Features, "bmi2", true); 2022 setFeatureEnabled(Features, "rtm", true); 2023 setFeatureEnabled(Features, "fma", true); 2024 break; 2025 case CK_K6: 2026 case CK_WinChipC6: 2027 setFeatureEnabled(Features, "mmx", true); 2028 break; 2029 case CK_K6_2: 2030 case CK_K6_3: 2031 case CK_WinChip2: 2032 case CK_C3: 2033 setFeatureEnabled(Features, "3dnow", true); 2034 break; 2035 case CK_Athlon: 2036 case CK_AthlonThunderbird: 2037 case CK_Geode: 2038 setFeatureEnabled(Features, "3dnowa", true); 2039 break; 2040 case CK_Athlon4: 2041 case CK_AthlonXP: 2042 case CK_AthlonMP: 2043 setFeatureEnabled(Features, "sse", true); 2044 setFeatureEnabled(Features, "3dnowa", true); 2045 break; 2046 case CK_K8: 2047 case CK_Opteron: 2048 case CK_Athlon64: 2049 case CK_AthlonFX: 2050 setFeatureEnabled(Features, "sse2", true); 2051 setFeatureEnabled(Features, "3dnowa", true); 2052 break; 2053 case CK_K8SSE3: 2054 case CK_OpteronSSE3: 2055 case CK_Athlon64SSE3: 2056 setFeatureEnabled(Features, "sse3", true); 2057 setFeatureEnabled(Features, "3dnowa", true); 2058 break; 2059 case CK_AMDFAM10: 2060 setFeatureEnabled(Features, "sse3", true); 2061 setFeatureEnabled(Features, "sse4a", true); 2062 setFeatureEnabled(Features, "3dnowa", true); 2063 setFeatureEnabled(Features, "lzcnt", true); 2064 setFeatureEnabled(Features, "popcnt", true); 2065 break; 2066 case CK_BTVER1: 2067 setFeatureEnabled(Features, "ssse3", true); 2068 setFeatureEnabled(Features, "sse4a", true); 2069 setFeatureEnabled(Features, "lzcnt", true); 2070 setFeatureEnabled(Features, "popcnt", true); 2071 break; 2072 case CK_BTVER2: 2073 setFeatureEnabled(Features, "avx", true); 2074 setFeatureEnabled(Features, "sse4a", true); 2075 setFeatureEnabled(Features, "lzcnt", true); 2076 setFeatureEnabled(Features, "aes", true); 2077 setFeatureEnabled(Features, "pclmul", true); 2078 setFeatureEnabled(Features, "bmi", true); 2079 setFeatureEnabled(Features, "f16c", true); 2080 break; 2081 case CK_BDVER1: 2082 setFeatureEnabled(Features, "xop", true); 2083 setFeatureEnabled(Features, "lzcnt", true); 2084 setFeatureEnabled(Features, "aes", true); 2085 setFeatureEnabled(Features, "pclmul", true); 2086 break; 2087 case CK_BDVER2: 2088 setFeatureEnabled(Features, "xop", true); 2089 setFeatureEnabled(Features, "lzcnt", true); 2090 setFeatureEnabled(Features, "aes", true); 2091 setFeatureEnabled(Features, "pclmul", true); 2092 setFeatureEnabled(Features, "bmi", true); 2093 setFeatureEnabled(Features, "fma", true); 2094 setFeatureEnabled(Features, "f16c", true); 2095 break; 2096 case CK_C3_2: 2097 setFeatureEnabled(Features, "sse", true); 2098 break; 2099 } 2100 } 2101 2102 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2103 X86SSEEnum Level, bool Enabled) const { 2104 if (Enabled) { 2105 switch (Level) { 2106 case AVX512F: 2107 Features["avx512f"] = true; 2108 case AVX2: 2109 Features["avx2"] = true; 2110 case AVX: 2111 Features["avx"] = true; 2112 case SSE42: 2113 Features["popcnt"] = Features["sse4.2"] = true; 2114 case SSE41: 2115 Features["sse4.1"] = true; 2116 case SSSE3: 2117 Features["ssse3"] = true; 2118 case SSE3: 2119 Features["sse3"] = true; 2120 case SSE2: 2121 Features["sse2"] = true; 2122 case SSE1: 2123 if (!Features.count("mmx")) 2124 setMMXLevel(Features, MMX, Enabled); 2125 Features["sse"] = true; 2126 case NoSSE: 2127 break; 2128 } 2129 return; 2130 } 2131 2132 switch (Level) { 2133 case NoSSE: 2134 case SSE1: 2135 Features["sse"] = false; 2136 case SSE2: 2137 Features["sse2"] = false; 2138 case SSE3: 2139 Features["sse3"] = false; 2140 setXOPLevel(Features, NoXOP, false); 2141 case SSSE3: 2142 Features["ssse3"] = false; 2143 case SSE41: 2144 Features["sse4.1"] = false; 2145 case SSE42: 2146 Features["popcnt"] = Features["sse4.2"] = false; 2147 case AVX: 2148 Features["fma"] = Features["avx"] = false; 2149 setXOPLevel(Features, FMA4, false); 2150 case AVX2: 2151 Features["avx2"] = false; 2152 case AVX512F: 2153 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2154 Features["avx512pf"] = false; 2155 } 2156 } 2157 2158 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2159 MMX3DNowEnum Level, bool Enabled) const { 2160 if (Enabled) { 2161 switch (Level) { 2162 case AMD3DNowAthlon: 2163 Features["3dnowa"] = true; 2164 case AMD3DNow: 2165 Features["3dnow"] = true; 2166 case MMX: 2167 Features["mmx"] = true; 2168 case NoMMX3DNow: 2169 break; 2170 } 2171 return; 2172 } 2173 2174 switch (Level) { 2175 case NoMMX3DNow: 2176 case MMX: 2177 Features["mmx"] = false; 2178 case AMD3DNow: 2179 Features["3dnow"] = false; 2180 case AMD3DNowAthlon: 2181 Features["3dnowa"] = false; 2182 } 2183 } 2184 2185 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2186 bool Enabled) const { 2187 if (Enabled) { 2188 switch (Level) { 2189 case XOP: 2190 Features["xop"] = true; 2191 case FMA4: 2192 Features["fma4"] = true; 2193 setSSELevel(Features, AVX, true); 2194 case SSE4A: 2195 Features["sse4a"] = true; 2196 setSSELevel(Features, SSE3, true); 2197 case NoXOP: 2198 break; 2199 } 2200 return; 2201 } 2202 2203 switch (Level) { 2204 case NoXOP: 2205 case SSE4A: 2206 Features["sse4a"] = false; 2207 case FMA4: 2208 Features["fma4"] = false; 2209 case XOP: 2210 Features["xop"] = false; 2211 } 2212 } 2213 2214 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 2215 StringRef Name, 2216 bool Enabled) const { 2217 // FIXME: This *really* should not be here. We need some way of translating 2218 // options into llvm subtarget features. 2219 if (Name == "sse4") 2220 Name = "sse4.2"; 2221 2222 Features[Name] = Enabled; 2223 2224 if (Name == "mmx") 2225 setMMXLevel(Features, MMX, Enabled); 2226 else if (Name == "sse") 2227 setSSELevel(Features, SSE1, Enabled); 2228 else if (Name == "sse2") 2229 setSSELevel(Features, SSE2, Enabled); 2230 else if (Name == "sse3") 2231 setSSELevel(Features, SSE3, Enabled); 2232 else if (Name == "ssse3") 2233 setSSELevel(Features, SSSE3, Enabled); 2234 else if (Name == "sse4.2") 2235 setSSELevel(Features, SSE42, Enabled); 2236 else if (Name == "sse4.1") 2237 setSSELevel(Features, SSE41, Enabled); 2238 else if (Name == "3dnow") 2239 setMMXLevel(Features, AMD3DNow, Enabled); 2240 else if (Name == "3dnowa") 2241 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2242 else if (Name == "aes") { 2243 if (Enabled) 2244 setSSELevel(Features, SSE2, Enabled); 2245 } else if (Name == "pclmul") { 2246 if (Enabled) 2247 setSSELevel(Features, SSE2, Enabled); 2248 } else if (Name == "avx") 2249 setSSELevel(Features, AVX, Enabled); 2250 else if (Name == "avx2") 2251 setSSELevel(Features, AVX2, Enabled); 2252 else if (Name == "avx512f") 2253 setSSELevel(Features, AVX512F, Enabled); 2254 else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") { 2255 if (Enabled) 2256 setSSELevel(Features, AVX512F, Enabled); 2257 } else if (Name == "fma") { 2258 if (Enabled) 2259 setSSELevel(Features, AVX, Enabled); 2260 } else if (Name == "fma4") { 2261 setXOPLevel(Features, FMA4, Enabled); 2262 } else if (Name == "xop") { 2263 setXOPLevel(Features, XOP, Enabled); 2264 } else if (Name == "sse4a") { 2265 setXOPLevel(Features, SSE4A, Enabled); 2266 } 2267 } 2268 2269 /// HandleTargetOptions - Perform initialization based on the user 2270 /// configured set of features. 2271 bool X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features, 2272 DiagnosticsEngine &Diags) { 2273 // Remember the maximum enabled sselevel. 2274 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2275 // Ignore disabled features. 2276 if (Features[i][0] == '-') 2277 continue; 2278 2279 StringRef Feature = StringRef(Features[i]).substr(1); 2280 2281 if (Feature == "aes") { 2282 HasAES = true; 2283 continue; 2284 } 2285 2286 if (Feature == "pclmul") { 2287 HasPCLMUL = true; 2288 continue; 2289 } 2290 2291 if (Feature == "lzcnt") { 2292 HasLZCNT = true; 2293 continue; 2294 } 2295 2296 if (Feature == "rdrnd") { 2297 HasRDRND = true; 2298 continue; 2299 } 2300 2301 if (Feature == "bmi") { 2302 HasBMI = true; 2303 continue; 2304 } 2305 2306 if (Feature == "bmi2") { 2307 HasBMI2 = true; 2308 continue; 2309 } 2310 2311 if (Feature == "popcnt") { 2312 HasPOPCNT = true; 2313 continue; 2314 } 2315 2316 if (Feature == "rtm") { 2317 HasRTM = true; 2318 continue; 2319 } 2320 2321 if (Feature == "prfchw") { 2322 HasPRFCHW = true; 2323 continue; 2324 } 2325 2326 if (Feature == "rdseed") { 2327 HasRDSEED = true; 2328 continue; 2329 } 2330 2331 if (Feature == "fma") { 2332 HasFMA = true; 2333 continue; 2334 } 2335 2336 if (Feature == "f16c") { 2337 HasF16C = true; 2338 continue; 2339 } 2340 2341 if (Feature == "avx512cd") { 2342 HasAVX512CD = true; 2343 continue; 2344 } 2345 2346 if (Feature == "avx512er") { 2347 HasAVX512ER = true; 2348 continue; 2349 } 2350 2351 if (Feature == "avx512pf") { 2352 HasAVX512PF = true; 2353 continue; 2354 } 2355 2356 assert(Features[i][0] == '+' && "Invalid target feature!"); 2357 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2358 .Case("avx512f", AVX512F) 2359 .Case("avx2", AVX2) 2360 .Case("avx", AVX) 2361 .Case("sse4.2", SSE42) 2362 .Case("sse4.1", SSE41) 2363 .Case("ssse3", SSSE3) 2364 .Case("sse3", SSE3) 2365 .Case("sse2", SSE2) 2366 .Case("sse", SSE1) 2367 .Default(NoSSE); 2368 SSELevel = std::max(SSELevel, Level); 2369 2370 MMX3DNowEnum ThreeDNowLevel = 2371 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2372 .Case("3dnowa", AMD3DNowAthlon) 2373 .Case("3dnow", AMD3DNow) 2374 .Case("mmx", MMX) 2375 .Default(NoMMX3DNow); 2376 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2377 2378 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2379 .Case("xop", XOP) 2380 .Case("fma4", FMA4) 2381 .Case("sse4a", SSE4A) 2382 .Default(NoXOP); 2383 XOPLevel = std::max(XOPLevel, XLevel); 2384 } 2385 2386 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2387 // matches the selected sse level. 2388 if (FPMath == FP_SSE && SSELevel < SSE1) { 2389 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2390 return false; 2391 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2392 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2393 return false; 2394 } 2395 2396 // Don't tell the backend if we're turning off mmx; it will end up disabling 2397 // SSE, which we don't want. 2398 std::vector<std::string>::iterator it; 2399 it = std::find(Features.begin(), Features.end(), "-mmx"); 2400 if (it != Features.end()) 2401 Features.erase(it); 2402 return true; 2403 } 2404 2405 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2406 /// definitions for this particular subtarget. 2407 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2408 MacroBuilder &Builder) const { 2409 // Target identification. 2410 if (getTriple().getArch() == llvm::Triple::x86_64) { 2411 Builder.defineMacro("__amd64__"); 2412 Builder.defineMacro("__amd64"); 2413 Builder.defineMacro("__x86_64"); 2414 Builder.defineMacro("__x86_64__"); 2415 } else { 2416 DefineStd(Builder, "i386", Opts); 2417 } 2418 2419 // Subtarget options. 2420 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2421 // truly should be based on -mtune options. 2422 switch (CPU) { 2423 case CK_Generic: 2424 break; 2425 case CK_i386: 2426 // The rest are coming from the i386 define above. 2427 Builder.defineMacro("__tune_i386__"); 2428 break; 2429 case CK_i486: 2430 case CK_WinChipC6: 2431 case CK_WinChip2: 2432 case CK_C3: 2433 defineCPUMacros(Builder, "i486"); 2434 break; 2435 case CK_PentiumMMX: 2436 Builder.defineMacro("__pentium_mmx__"); 2437 Builder.defineMacro("__tune_pentium_mmx__"); 2438 // Fallthrough 2439 case CK_i586: 2440 case CK_Pentium: 2441 defineCPUMacros(Builder, "i586"); 2442 defineCPUMacros(Builder, "pentium"); 2443 break; 2444 case CK_Pentium3: 2445 case CK_Pentium3M: 2446 case CK_PentiumM: 2447 Builder.defineMacro("__tune_pentium3__"); 2448 // Fallthrough 2449 case CK_Pentium2: 2450 case CK_C3_2: 2451 Builder.defineMacro("__tune_pentium2__"); 2452 // Fallthrough 2453 case CK_PentiumPro: 2454 Builder.defineMacro("__tune_i686__"); 2455 Builder.defineMacro("__tune_pentiumpro__"); 2456 // Fallthrough 2457 case CK_i686: 2458 Builder.defineMacro("__i686"); 2459 Builder.defineMacro("__i686__"); 2460 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2461 Builder.defineMacro("__pentiumpro"); 2462 Builder.defineMacro("__pentiumpro__"); 2463 break; 2464 case CK_Pentium4: 2465 case CK_Pentium4M: 2466 defineCPUMacros(Builder, "pentium4"); 2467 break; 2468 case CK_Yonah: 2469 case CK_Prescott: 2470 case CK_Nocona: 2471 defineCPUMacros(Builder, "nocona"); 2472 break; 2473 case CK_Core2: 2474 case CK_Penryn: 2475 defineCPUMacros(Builder, "core2"); 2476 break; 2477 case CK_Atom: 2478 defineCPUMacros(Builder, "atom"); 2479 break; 2480 case CK_SLM: 2481 defineCPUMacros(Builder, "slm"); 2482 break; 2483 case CK_Corei7: 2484 case CK_Corei7AVX: 2485 case CK_CoreAVXi: 2486 case CK_CoreAVX2: 2487 defineCPUMacros(Builder, "corei7"); 2488 break; 2489 case CK_KNL: 2490 defineCPUMacros(Builder, "knl"); 2491 break; 2492 case CK_K6_2: 2493 Builder.defineMacro("__k6_2__"); 2494 Builder.defineMacro("__tune_k6_2__"); 2495 // Fallthrough 2496 case CK_K6_3: 2497 if (CPU != CK_K6_2) { // In case of fallthrough 2498 // FIXME: GCC may be enabling these in cases where some other k6 2499 // architecture is specified but -m3dnow is explicitly provided. The 2500 // exact semantics need to be determined and emulated here. 2501 Builder.defineMacro("__k6_3__"); 2502 Builder.defineMacro("__tune_k6_3__"); 2503 } 2504 // Fallthrough 2505 case CK_K6: 2506 defineCPUMacros(Builder, "k6"); 2507 break; 2508 case CK_Athlon: 2509 case CK_AthlonThunderbird: 2510 case CK_Athlon4: 2511 case CK_AthlonXP: 2512 case CK_AthlonMP: 2513 defineCPUMacros(Builder, "athlon"); 2514 if (SSELevel != NoSSE) { 2515 Builder.defineMacro("__athlon_sse__"); 2516 Builder.defineMacro("__tune_athlon_sse__"); 2517 } 2518 break; 2519 case CK_K8: 2520 case CK_K8SSE3: 2521 case CK_x86_64: 2522 case CK_Opteron: 2523 case CK_OpteronSSE3: 2524 case CK_Athlon64: 2525 case CK_Athlon64SSE3: 2526 case CK_AthlonFX: 2527 defineCPUMacros(Builder, "k8"); 2528 break; 2529 case CK_AMDFAM10: 2530 defineCPUMacros(Builder, "amdfam10"); 2531 break; 2532 case CK_BTVER1: 2533 defineCPUMacros(Builder, "btver1"); 2534 break; 2535 case CK_BTVER2: 2536 defineCPUMacros(Builder, "btver2"); 2537 break; 2538 case CK_BDVER1: 2539 defineCPUMacros(Builder, "bdver1"); 2540 break; 2541 case CK_BDVER2: 2542 defineCPUMacros(Builder, "bdver2"); 2543 break; 2544 case CK_Geode: 2545 defineCPUMacros(Builder, "geode"); 2546 break; 2547 } 2548 2549 // Target properties. 2550 Builder.defineMacro("__LITTLE_ENDIAN__"); 2551 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2552 2553 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2554 // functions in glibc header files that use FP Stack inline asm which the 2555 // backend can't deal with (PR879). 2556 Builder.defineMacro("__NO_MATH_INLINES"); 2557 2558 if (HasAES) 2559 Builder.defineMacro("__AES__"); 2560 2561 if (HasPCLMUL) 2562 Builder.defineMacro("__PCLMUL__"); 2563 2564 if (HasLZCNT) 2565 Builder.defineMacro("__LZCNT__"); 2566 2567 if (HasRDRND) 2568 Builder.defineMacro("__RDRND__"); 2569 2570 if (HasBMI) 2571 Builder.defineMacro("__BMI__"); 2572 2573 if (HasBMI2) 2574 Builder.defineMacro("__BMI2__"); 2575 2576 if (HasPOPCNT) 2577 Builder.defineMacro("__POPCNT__"); 2578 2579 if (HasRTM) 2580 Builder.defineMacro("__RTM__"); 2581 2582 if (HasPRFCHW) 2583 Builder.defineMacro("__PRFCHW__"); 2584 2585 if (HasRDSEED) 2586 Builder.defineMacro("__RDSEED__"); 2587 2588 switch (XOPLevel) { 2589 case XOP: 2590 Builder.defineMacro("__XOP__"); 2591 case FMA4: 2592 Builder.defineMacro("__FMA4__"); 2593 case SSE4A: 2594 Builder.defineMacro("__SSE4A__"); 2595 case NoXOP: 2596 break; 2597 } 2598 2599 if (HasFMA) 2600 Builder.defineMacro("__FMA__"); 2601 2602 if (HasF16C) 2603 Builder.defineMacro("__F16C__"); 2604 2605 if (HasAVX512CD) 2606 Builder.defineMacro("__AVX512CD__"); 2607 if (HasAVX512ER) 2608 Builder.defineMacro("__AVX512ER__"); 2609 if (HasAVX512PF) 2610 Builder.defineMacro("__AVX512PF__"); 2611 2612 // Each case falls through to the previous one here. 2613 switch (SSELevel) { 2614 case AVX512F: 2615 Builder.defineMacro("__AVX512F__"); 2616 case AVX2: 2617 Builder.defineMacro("__AVX2__"); 2618 case AVX: 2619 Builder.defineMacro("__AVX__"); 2620 case SSE42: 2621 Builder.defineMacro("__SSE4_2__"); 2622 case SSE41: 2623 Builder.defineMacro("__SSE4_1__"); 2624 case SSSE3: 2625 Builder.defineMacro("__SSSE3__"); 2626 case SSE3: 2627 Builder.defineMacro("__SSE3__"); 2628 case SSE2: 2629 Builder.defineMacro("__SSE2__"); 2630 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2631 case SSE1: 2632 Builder.defineMacro("__SSE__"); 2633 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2634 case NoSSE: 2635 break; 2636 } 2637 2638 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2639 switch (SSELevel) { 2640 case AVX512F: 2641 case AVX2: 2642 case AVX: 2643 case SSE42: 2644 case SSE41: 2645 case SSSE3: 2646 case SSE3: 2647 case SSE2: 2648 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2649 break; 2650 case SSE1: 2651 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2652 break; 2653 default: 2654 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2655 } 2656 } 2657 2658 // Each case falls through to the previous one here. 2659 switch (MMX3DNowLevel) { 2660 case AMD3DNowAthlon: 2661 Builder.defineMacro("__3dNOW_A__"); 2662 case AMD3DNow: 2663 Builder.defineMacro("__3dNOW__"); 2664 case MMX: 2665 Builder.defineMacro("__MMX__"); 2666 case NoMMX3DNow: 2667 break; 2668 } 2669 2670 if (CPU >= CK_i486) { 2671 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2672 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2673 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2674 } 2675 if (CPU >= CK_i586) 2676 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2677 } 2678 2679 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2680 return llvm::StringSwitch<bool>(Feature) 2681 .Case("aes", HasAES) 2682 .Case("avx", SSELevel >= AVX) 2683 .Case("avx2", SSELevel >= AVX2) 2684 .Case("avx512f", SSELevel >= AVX512F) 2685 .Case("avx512cd", HasAVX512CD) 2686 .Case("avx512er", HasAVX512ER) 2687 .Case("avx512pf", HasAVX512PF) 2688 .Case("bmi", HasBMI) 2689 .Case("bmi2", HasBMI2) 2690 .Case("fma", HasFMA) 2691 .Case("fma4", XOPLevel >= FMA4) 2692 .Case("lzcnt", HasLZCNT) 2693 .Case("rdrnd", HasRDRND) 2694 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2695 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2696 .Case("mmx", MMX3DNowLevel >= MMX) 2697 .Case("pclmul", HasPCLMUL) 2698 .Case("popcnt", HasPOPCNT) 2699 .Case("rtm", HasRTM) 2700 .Case("prfchw", HasPRFCHW) 2701 .Case("rdseed", HasRDSEED) 2702 .Case("sse", SSELevel >= SSE1) 2703 .Case("sse2", SSELevel >= SSE2) 2704 .Case("sse3", SSELevel >= SSE3) 2705 .Case("ssse3", SSELevel >= SSSE3) 2706 .Case("sse4.1", SSELevel >= SSE41) 2707 .Case("sse4.2", SSELevel >= SSE42) 2708 .Case("sse4a", XOPLevel >= SSE4A) 2709 .Case("x86", true) 2710 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2711 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2712 .Case("xop", XOPLevel >= XOP) 2713 .Case("f16c", HasF16C) 2714 .Default(false); 2715 } 2716 2717 bool 2718 X86TargetInfo::validateAsmConstraint(const char *&Name, 2719 TargetInfo::ConstraintInfo &Info) const { 2720 switch (*Name) { 2721 default: return false; 2722 case 'Y': // first letter of a pair: 2723 switch (*(Name+1)) { 2724 default: return false; 2725 case '0': // First SSE register. 2726 case 't': // Any SSE register, when SSE2 is enabled. 2727 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2728 case 'm': // any MMX register, when inter-unit moves enabled. 2729 break; // falls through to setAllowsRegister. 2730 } 2731 case 'a': // eax. 2732 case 'b': // ebx. 2733 case 'c': // ecx. 2734 case 'd': // edx. 2735 case 'S': // esi. 2736 case 'D': // edi. 2737 case 'A': // edx:eax. 2738 case 'f': // any x87 floating point stack register. 2739 case 't': // top of floating point stack. 2740 case 'u': // second from top of floating point stack. 2741 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2742 case 'y': // Any MMX register. 2743 case 'x': // Any SSE register. 2744 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2745 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2746 case 'l': // "Index" registers: any general register that can be used as an 2747 // index in a base+index memory access. 2748 Info.setAllowsRegister(); 2749 return true; 2750 case 'C': // SSE floating point constant. 2751 case 'G': // x87 floating point constant. 2752 case 'e': // 32-bit signed integer constant for use with zero-extending 2753 // x86_64 instructions. 2754 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2755 // x86_64 instructions. 2756 return true; 2757 } 2758 } 2759 2760 2761 std::string 2762 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2763 switch (*Constraint) { 2764 case 'a': return std::string("{ax}"); 2765 case 'b': return std::string("{bx}"); 2766 case 'c': return std::string("{cx}"); 2767 case 'd': return std::string("{dx}"); 2768 case 'S': return std::string("{si}"); 2769 case 'D': return std::string("{di}"); 2770 case 'p': // address 2771 return std::string("im"); 2772 case 't': // top of floating point stack. 2773 return std::string("{st}"); 2774 case 'u': // second from top of floating point stack. 2775 return std::string("{st(1)}"); // second from top of floating point stack. 2776 default: 2777 return std::string(1, *Constraint); 2778 } 2779 } 2780 } // end anonymous namespace 2781 2782 namespace { 2783 // X86-32 generic target 2784 class X86_32TargetInfo : public X86TargetInfo { 2785 public: 2786 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 2787 DoubleAlign = LongLongAlign = 32; 2788 LongDoubleWidth = 96; 2789 LongDoubleAlign = 32; 2790 SuitableAlign = 128; 2791 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2792 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2793 "a0:0:64-f80:32:32-n8:16:32-S128"; 2794 SizeType = UnsignedInt; 2795 PtrDiffType = SignedInt; 2796 IntPtrType = SignedInt; 2797 RegParmMax = 3; 2798 2799 // Use fpret for all types. 2800 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2801 (1 << TargetInfo::Double) | 2802 (1 << TargetInfo::LongDouble)); 2803 2804 // x86-32 has atomics up to 8 bytes 2805 // FIXME: Check that we actually have cmpxchg8b before setting 2806 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2807 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2808 } 2809 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2810 return TargetInfo::CharPtrBuiltinVaList; 2811 } 2812 2813 int getEHDataRegisterNumber(unsigned RegNo) const { 2814 if (RegNo == 0) return 0; 2815 if (RegNo == 1) return 2; 2816 return -1; 2817 } 2818 virtual bool validateInputSize(StringRef Constraint, 2819 unsigned Size) const { 2820 switch (Constraint[0]) { 2821 default: break; 2822 case 'a': 2823 case 'b': 2824 case 'c': 2825 case 'd': 2826 return Size <= 32; 2827 } 2828 2829 return true; 2830 } 2831 }; 2832 } // end anonymous namespace 2833 2834 namespace { 2835 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2836 public: 2837 NetBSDI386TargetInfo(const llvm::Triple &Triple) 2838 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 2839 2840 virtual unsigned getFloatEvalMethod() const { 2841 // NetBSD defaults to "double" rounding 2842 return 1; 2843 } 2844 }; 2845 } // end anonymous namespace 2846 2847 namespace { 2848 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 2849 public: 2850 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 2851 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 2852 SizeType = UnsignedLong; 2853 IntPtrType = SignedLong; 2854 PtrDiffType = SignedLong; 2855 } 2856 }; 2857 } // end anonymous namespace 2858 2859 namespace { 2860 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 2861 public: 2862 BitrigI386TargetInfo(const llvm::Triple &Triple) 2863 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 2864 SizeType = UnsignedLong; 2865 IntPtrType = SignedLong; 2866 PtrDiffType = SignedLong; 2867 } 2868 }; 2869 } // end anonymous namespace 2870 2871 namespace { 2872 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 2873 public: 2874 DarwinI386TargetInfo(const llvm::Triple &Triple) 2875 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 2876 LongDoubleWidth = 128; 2877 LongDoubleAlign = 128; 2878 SuitableAlign = 128; 2879 MaxVectorAlign = 256; 2880 SizeType = UnsignedLong; 2881 IntPtrType = SignedLong; 2882 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2883 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2884 "a0:0:64-f80:128:128-n8:16:32-S128"; 2885 HasAlignMac68kSupport = true; 2886 } 2887 2888 }; 2889 } // end anonymous namespace 2890 2891 namespace { 2892 // x86-32 Windows target 2893 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 2894 public: 2895 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 2896 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 2897 TLSSupported = false; 2898 WCharType = UnsignedShort; 2899 DoubleAlign = LongLongAlign = 64; 2900 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2901 "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-" 2902 "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"; 2903 } 2904 virtual void getTargetDefines(const LangOptions &Opts, 2905 MacroBuilder &Builder) const { 2906 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 2907 } 2908 }; 2909 } // end anonymous namespace 2910 2911 namespace { 2912 2913 // x86-32 Windows Visual Studio target 2914 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 2915 public: 2916 VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple) 2917 : WindowsX86_32TargetInfo(Triple) { 2918 LongDoubleWidth = LongDoubleAlign = 64; 2919 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 2920 } 2921 virtual void getTargetDefines(const LangOptions &Opts, 2922 MacroBuilder &Builder) const { 2923 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 2924 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 2925 // The value of the following reflects processor type. 2926 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 2927 // We lost the original triple, so we use the default. 2928 Builder.defineMacro("_M_IX86", "600"); 2929 } 2930 }; 2931 } // end anonymous namespace 2932 2933 namespace { 2934 // x86-32 MinGW target 2935 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 2936 public: 2937 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 2938 : WindowsX86_32TargetInfo(Triple) {} 2939 virtual void getTargetDefines(const LangOptions &Opts, 2940 MacroBuilder &Builder) const { 2941 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 2942 DefineStd(Builder, "WIN32", Opts); 2943 DefineStd(Builder, "WINNT", Opts); 2944 Builder.defineMacro("_X86_"); 2945 Builder.defineMacro("__MSVCRT__"); 2946 Builder.defineMacro("__MINGW32__"); 2947 2948 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 2949 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 2950 if (Opts.MicrosoftExt) 2951 // Provide "as-is" __declspec. 2952 Builder.defineMacro("__declspec", "__declspec"); 2953 else 2954 // Provide alias of __attribute__ like mingw32-gcc. 2955 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 2956 } 2957 }; 2958 } // end anonymous namespace 2959 2960 namespace { 2961 // x86-32 Cygwin target 2962 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 2963 public: 2964 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 2965 : X86_32TargetInfo(Triple) { 2966 TLSSupported = false; 2967 WCharType = UnsignedShort; 2968 DoubleAlign = LongLongAlign = 64; 2969 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2970 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 2971 "a0:0:64-f80:32:32-n8:16:32-S32"; 2972 } 2973 virtual void getTargetDefines(const LangOptions &Opts, 2974 MacroBuilder &Builder) const { 2975 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2976 Builder.defineMacro("_X86_"); 2977 Builder.defineMacro("__CYGWIN__"); 2978 Builder.defineMacro("__CYGWIN32__"); 2979 DefineStd(Builder, "unix", Opts); 2980 if (Opts.CPlusPlus) 2981 Builder.defineMacro("_GNU_SOURCE"); 2982 } 2983 }; 2984 } // end anonymous namespace 2985 2986 namespace { 2987 // x86-32 Haiku target 2988 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 2989 public: 2990 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 2991 SizeType = UnsignedLong; 2992 IntPtrType = SignedLong; 2993 PtrDiffType = SignedLong; 2994 ProcessIDType = SignedLong; 2995 this->UserLabelPrefix = ""; 2996 this->TLSSupported = false; 2997 } 2998 virtual void getTargetDefines(const LangOptions &Opts, 2999 MacroBuilder &Builder) const { 3000 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3001 Builder.defineMacro("__INTEL__"); 3002 Builder.defineMacro("__HAIKU__"); 3003 } 3004 }; 3005 } // end anonymous namespace 3006 3007 // RTEMS Target 3008 template<typename Target> 3009 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3010 protected: 3011 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3012 MacroBuilder &Builder) const { 3013 // RTEMS defines; list based off of gcc output 3014 3015 Builder.defineMacro("__rtems__"); 3016 Builder.defineMacro("__ELF__"); 3017 } 3018 3019 public: 3020 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3021 this->UserLabelPrefix = ""; 3022 3023 switch (Triple.getArch()) { 3024 default: 3025 case llvm::Triple::x86: 3026 // this->MCountName = ".mcount"; 3027 break; 3028 case llvm::Triple::mips: 3029 case llvm::Triple::mipsel: 3030 case llvm::Triple::ppc: 3031 case llvm::Triple::ppc64: 3032 case llvm::Triple::ppc64le: 3033 // this->MCountName = "_mcount"; 3034 break; 3035 case llvm::Triple::arm: 3036 // this->MCountName = "__mcount"; 3037 break; 3038 } 3039 } 3040 }; 3041 3042 namespace { 3043 // x86-32 RTEMS target 3044 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3045 public: 3046 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3047 SizeType = UnsignedLong; 3048 IntPtrType = SignedLong; 3049 PtrDiffType = SignedLong; 3050 this->UserLabelPrefix = ""; 3051 } 3052 virtual void getTargetDefines(const LangOptions &Opts, 3053 MacroBuilder &Builder) const { 3054 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3055 Builder.defineMacro("__INTEL__"); 3056 Builder.defineMacro("__rtems__"); 3057 } 3058 }; 3059 } // end anonymous namespace 3060 3061 namespace { 3062 // x86-64 generic target 3063 class X86_64TargetInfo : public X86TargetInfo { 3064 public: 3065 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3066 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 3067 LongDoubleWidth = 128; 3068 LongDoubleAlign = 128; 3069 LargeArrayMinWidth = 128; 3070 LargeArrayAlign = 128; 3071 SuitableAlign = 128; 3072 IntMaxType = SignedLong; 3073 UIntMaxType = UnsignedLong; 3074 Int64Type = SignedLong; 3075 RegParmMax = 6; 3076 3077 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3078 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 3079 "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"; 3080 3081 // Use fpret only for long double. 3082 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3083 3084 // Use fp2ret for _Complex long double. 3085 ComplexLongDoubleUsesFP2Ret = true; 3086 3087 // x86-64 has atomics up to 16 bytes. 3088 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 3089 // on CPUs with cmpxchg16b 3090 MaxAtomicPromoteWidth = 128; 3091 MaxAtomicInlineWidth = 64; 3092 } 3093 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3094 return TargetInfo::X86_64ABIBuiltinVaList; 3095 } 3096 3097 int getEHDataRegisterNumber(unsigned RegNo) const { 3098 if (RegNo == 0) return 0; 3099 if (RegNo == 1) return 1; 3100 return -1; 3101 } 3102 3103 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3104 return (CC == CC_C || 3105 CC == CC_IntelOclBicc || 3106 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3107 } 3108 3109 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 3110 return CC_C; 3111 } 3112 3113 }; 3114 } // end anonymous namespace 3115 3116 namespace { 3117 // x86-64 Windows target 3118 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3119 public: 3120 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3121 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3122 TLSSupported = false; 3123 WCharType = UnsignedShort; 3124 LongWidth = LongAlign = 32; 3125 DoubleAlign = LongLongAlign = 64; 3126 IntMaxType = SignedLongLong; 3127 UIntMaxType = UnsignedLongLong; 3128 Int64Type = SignedLongLong; 3129 SizeType = UnsignedLongLong; 3130 PtrDiffType = SignedLongLong; 3131 IntPtrType = SignedLongLong; 3132 this->UserLabelPrefix = ""; 3133 } 3134 virtual void getTargetDefines(const LangOptions &Opts, 3135 MacroBuilder &Builder) const { 3136 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3137 Builder.defineMacro("_WIN64"); 3138 } 3139 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3140 return TargetInfo::CharPtrBuiltinVaList; 3141 } 3142 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3143 return (CC == CC_C || 3144 CC == CC_IntelOclBicc || 3145 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3146 } 3147 }; 3148 } // end anonymous namespace 3149 3150 namespace { 3151 // x86-64 Windows Visual Studio target 3152 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 3153 public: 3154 VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple) 3155 : WindowsX86_64TargetInfo(Triple) { 3156 LongDoubleWidth = LongDoubleAlign = 64; 3157 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3158 } 3159 virtual void getTargetDefines(const LangOptions &Opts, 3160 MacroBuilder &Builder) const { 3161 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3162 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3163 Builder.defineMacro("_M_X64"); 3164 Builder.defineMacro("_M_AMD64"); 3165 } 3166 }; 3167 } // end anonymous namespace 3168 3169 namespace { 3170 // x86-64 MinGW target 3171 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3172 public: 3173 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3174 : WindowsX86_64TargetInfo(Triple) {} 3175 virtual void getTargetDefines(const LangOptions &Opts, 3176 MacroBuilder &Builder) const { 3177 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3178 DefineStd(Builder, "WIN64", Opts); 3179 Builder.defineMacro("__MSVCRT__"); 3180 Builder.defineMacro("__MINGW32__"); 3181 Builder.defineMacro("__MINGW64__"); 3182 3183 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3184 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3185 if (Opts.MicrosoftExt) 3186 // Provide "as-is" __declspec. 3187 Builder.defineMacro("__declspec", "__declspec"); 3188 else 3189 // Provide alias of __attribute__ like mingw32-gcc. 3190 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3191 } 3192 }; 3193 } // end anonymous namespace 3194 3195 namespace { 3196 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3197 public: 3198 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3199 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3200 Int64Type = SignedLongLong; 3201 MaxVectorAlign = 256; 3202 } 3203 }; 3204 } // end anonymous namespace 3205 3206 namespace { 3207 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3208 public: 3209 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3210 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3211 IntMaxType = SignedLongLong; 3212 UIntMaxType = UnsignedLongLong; 3213 Int64Type = SignedLongLong; 3214 } 3215 }; 3216 } // end anonymous namespace 3217 3218 namespace { 3219 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3220 public: 3221 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3222 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3223 IntMaxType = SignedLongLong; 3224 UIntMaxType = UnsignedLongLong; 3225 Int64Type = SignedLongLong; 3226 } 3227 }; 3228 } 3229 3230 namespace { 3231 class AArch64TargetInfo : public TargetInfo { 3232 static const char * const GCCRegNames[]; 3233 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3234 3235 enum FPUModeEnum { 3236 FPUMode, 3237 NeonMode 3238 }; 3239 3240 unsigned FPU; 3241 static const Builtin::Info BuiltinInfo[]; 3242 3243 public: 3244 AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 3245 BigEndian = false; 3246 LongWidth = LongAlign = 64; 3247 LongDoubleWidth = LongDoubleAlign = 128; 3248 PointerWidth = PointerAlign = 64; 3249 SuitableAlign = 128; 3250 DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3251 "i64:64:64-i128:128:128-f32:32:32-f64:64:64-" 3252 "f128:128:128-n32:64-S128"; 3253 3254 WCharType = UnsignedInt; 3255 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3256 3257 // AArch64 backend supports 64-bit operations at the moment. In principle 3258 // 128-bit is possible if register-pairs are used. 3259 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3260 3261 TheCXXABI.set(TargetCXXABI::GenericAArch64); 3262 } 3263 virtual void getTargetDefines(const LangOptions &Opts, 3264 MacroBuilder &Builder) const { 3265 // GCC defines theses currently 3266 Builder.defineMacro("__aarch64__"); 3267 Builder.defineMacro("__AARCH64EL__"); 3268 3269 // ACLE predefines. Many can only have one possible value on v8 AArch64. 3270 3271 // FIXME: these were written based on an unreleased version of a 32-bit ACLE 3272 // which was intended to be compatible with a 64-bit implementation. They 3273 // will need updating when a real 64-bit ACLE exists. Particularly pressing 3274 // instances are: __ARM_ARCH_ISA_ARM, __ARM_ARCH_ISA_THUMB, __ARM_PCS. 3275 Builder.defineMacro("__ARM_ACLE", "101"); 3276 Builder.defineMacro("__ARM_ARCH", "8"); 3277 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 3278 3279 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 3280 Builder.defineMacro("__ARM_FEATURE_CLZ"); 3281 Builder.defineMacro("__ARM_FEATURE_FMA"); 3282 3283 // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean 3284 // 128-bit LDXP present, at which point this becomes 0x1f. 3285 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xf"); 3286 3287 // 0xe implies support for half, single and double precision operations. 3288 Builder.defineMacro("__ARM_FP", "0xe"); 3289 3290 // PCS specifies this for SysV variants, which is all we support. Other ABIs 3291 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 3292 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 3293 3294 if (Opts.FastMath || Opts.FiniteMathOnly) 3295 Builder.defineMacro("__ARM_FP_FAST"); 3296 3297 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 3298 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 3299 3300 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3301 Opts.ShortWChar ? "2" : "4"); 3302 3303 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3304 Opts.ShortEnums ? "1" : "4"); 3305 3306 if (BigEndian) 3307 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 3308 3309 if (FPU == NeonMode) { 3310 Builder.defineMacro("__AARCH_FEATURE_ADVSIMD"); 3311 3312 // 64-bit NEON supports half, single and double precision operations. 3313 Builder.defineMacro("__AARCH_ADVSIMD_FP", "0xe"); 3314 } 3315 } 3316 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3317 unsigned &NumRecords) const { 3318 Records = BuiltinInfo; 3319 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin; 3320 } 3321 virtual bool hasFeature(StringRef Feature) const { 3322 return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode); 3323 } 3324 3325 virtual bool HandleTargetFeatures(std::vector<std::string> &Features, 3326 DiagnosticsEngine &Diags) { 3327 FPU = FPUMode; 3328 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3329 if (Features[i] == "+neon") 3330 FPU = NeonMode; 3331 } 3332 return true; 3333 } 3334 3335 virtual void getGCCRegNames(const char *const *&Names, 3336 unsigned &NumNames) const; 3337 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3338 unsigned &NumAliases) const; 3339 3340 virtual bool isCLZForZeroUndef() const { return false; } 3341 3342 virtual bool validateAsmConstraint(const char *&Name, 3343 TargetInfo::ConstraintInfo &Info) const { 3344 switch (*Name) { 3345 default: return false; 3346 case 'w': // An FP/SIMD vector register 3347 Info.setAllowsRegister(); 3348 return true; 3349 case 'I': // Constant that can be used with an ADD instruction 3350 case 'J': // Constant that can be used with a SUB instruction 3351 case 'K': // Constant that can be used with a 32-bit logical instruction 3352 case 'L': // Constant that can be used with a 64-bit logical instruction 3353 case 'M': // Constant that can be used as a 32-bit MOV immediate 3354 case 'N': // Constant that can be used as a 64-bit MOV immediate 3355 case 'Y': // Floating point constant zero 3356 case 'Z': // Integer constant zero 3357 return true; 3358 case 'Q': // A memory reference with base register and no offset 3359 Info.setAllowsMemory(); 3360 return true; 3361 case 'S': // A symbolic address 3362 Info.setAllowsRegister(); 3363 return true; 3364 case 'U': 3365 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 3366 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 3367 // Usa: An absolute symbolic address 3368 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 3369 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 3370 } 3371 } 3372 3373 virtual const char *getClobbers() const { 3374 // There are no AArch64 clobbers shared by all asm statements. 3375 return ""; 3376 } 3377 3378 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3379 return TargetInfo::AArch64ABIBuiltinVaList; 3380 } 3381 }; 3382 3383 const char * const AArch64TargetInfo::GCCRegNames[] = { 3384 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", 3385 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", 3386 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", 3387 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr", 3388 3389 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 3390 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 3391 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 3392 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr", 3393 3394 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", 3395 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", 3396 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", 3397 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31", 3398 3399 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", 3400 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", 3401 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", 3402 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", 3403 3404 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3405 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3406 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3407 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3408 3409 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3410 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3411 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3412 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3413 3414 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3415 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", 3416 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", 3417 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" 3418 }; 3419 3420 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names, 3421 unsigned &NumNames) const { 3422 Names = GCCRegNames; 3423 NumNames = llvm::array_lengthof(GCCRegNames); 3424 } 3425 3426 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 3427 { { "x16" }, "ip0"}, 3428 { { "x17" }, "ip1"}, 3429 { { "x29" }, "fp" }, 3430 { { "x30" }, "lr" } 3431 }; 3432 3433 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3434 unsigned &NumAliases) const { 3435 Aliases = GCCRegAliases; 3436 NumAliases = llvm::array_lengthof(GCCRegAliases); 3437 3438 } 3439 3440 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 3441 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3442 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3443 ALL_LANGUAGES }, 3444 #include "clang/Basic/BuiltinsAArch64.def" 3445 }; 3446 3447 } // end anonymous namespace 3448 3449 namespace { 3450 class ARMTargetInfo : public TargetInfo { 3451 // Possible FPU choices. 3452 enum FPUMode { 3453 VFP2FPU = (1 << 0), 3454 VFP3FPU = (1 << 1), 3455 VFP4FPU = (1 << 2), 3456 NeonFPU = (1 << 3) 3457 }; 3458 3459 static bool FPUModeIsVFP(FPUMode Mode) { 3460 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU); 3461 } 3462 3463 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3464 static const char * const GCCRegNames[]; 3465 3466 std::string ABI, CPU; 3467 3468 enum { 3469 FP_Default, 3470 FP_VFP, 3471 FP_Neon 3472 } FPMath; 3473 3474 unsigned FPU : 4; 3475 3476 unsigned IsAAPCS : 1; 3477 unsigned IsThumb : 1; 3478 3479 // Initialized via features. 3480 unsigned SoftFloat : 1; 3481 unsigned SoftFloatABI : 1; 3482 3483 static const Builtin::Info BuiltinInfo[]; 3484 3485 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3486 // On linux, binaries targeting old cpus call functions in libgcc to 3487 // perform atomic operations. The implementation in libgcc then calls into 3488 // the kernel which on armv6 and newer uses ldrex and strex. The net result 3489 // is that if we assume the kernel is at least as recent as the hardware, 3490 // it is safe to use atomic instructions on armv6 and newer. 3491 if (T.getOS() != llvm::Triple::Linux && 3492 T.getOS() != llvm::Triple::FreeBSD && 3493 T.getOS() != llvm::Triple::Bitrig) 3494 return false; 3495 StringRef ArchName = T.getArchName(); 3496 if (T.getArch() == llvm::Triple::arm) { 3497 if (!ArchName.startswith("armv")) 3498 return false; 3499 StringRef VersionStr = ArchName.substr(4); 3500 unsigned Version; 3501 if (VersionStr.getAsInteger(10, Version)) 3502 return false; 3503 return Version >= 6; 3504 } 3505 assert(T.getArch() == llvm::Triple::thumb); 3506 if (!ArchName.startswith("thumbv")) 3507 return false; 3508 StringRef VersionStr = ArchName.substr(6); 3509 unsigned Version; 3510 if (VersionStr.getAsInteger(10, Version)) 3511 return false; 3512 return Version >= 7; 3513 } 3514 3515 public: 3516 ARMTargetInfo(const llvm::Triple &Triple) 3517 : TargetInfo(Triple), ABI("aapcs-linux"), CPU("arm1136j-s"), 3518 FPMath(FP_Default), IsAAPCS(true) { 3519 BigEndian = false; 3520 SizeType = UnsignedInt; 3521 PtrDiffType = SignedInt; 3522 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3523 WCharType = UnsignedInt; 3524 3525 // {} in inline assembly are neon specifiers, not assembly variant 3526 // specifiers. 3527 NoAsmVariants = true; 3528 3529 // FIXME: Should we just treat this as a feature? 3530 IsThumb = getTriple().getArchName().startswith("thumb"); 3531 if (IsThumb) { 3532 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3533 // so set preferred for small types to 32. 3534 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3535 "i64:64:64-f32:32:32-f64:64:64-" 3536 "v64:64:64-v128:64:128-a0:0:32-n32-S64"); 3537 } else { 3538 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3539 "i64:64:64-f32:32:32-f64:64:64-" 3540 "v64:64:64-v128:64:128-a0:0:64-n32-S64"); 3541 } 3542 3543 // ARM targets default to using the ARM C++ ABI. 3544 TheCXXABI.set(TargetCXXABI::GenericARM); 3545 3546 // ARM has atomics up to 8 bytes 3547 MaxAtomicPromoteWidth = 64; 3548 if (shouldUseInlineAtomic(getTriple())) 3549 MaxAtomicInlineWidth = 64; 3550 3551 // Do force alignment of members that follow zero length bitfields. If 3552 // the alignment of the zero-length bitfield is greater than the member 3553 // that follows it, `bar', `bar' will be aligned as the type of the 3554 // zero length bitfield. 3555 UseZeroLengthBitfieldAlignment = true; 3556 } 3557 virtual const char *getABI() const { return ABI.c_str(); } 3558 virtual bool setABI(const std::string &Name) { 3559 ABI = Name; 3560 3561 // The defaults (above) are for AAPCS, check if we need to change them. 3562 // 3563 // FIXME: We need support for -meabi... we could just mangle it into the 3564 // name. 3565 if (Name == "apcs-gnu") { 3566 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3567 // size_t is unsigned int on FreeBSD. 3568 if (getTriple().getOS() != llvm::Triple::FreeBSD) 3569 SizeType = UnsignedLong; 3570 3571 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3572 WCharType = SignedInt; 3573 3574 // Do not respect the alignment of bit-field types when laying out 3575 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3576 UseBitFieldTypeAlignment = false; 3577 3578 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3579 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3580 /// gcc. 3581 ZeroLengthBitfieldBoundary = 32; 3582 3583 IsAAPCS = false; 3584 3585 if (IsThumb) { 3586 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3587 // so set preferred for small types to 32. 3588 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3589 "i64:32:64-f32:32:32-f64:32:64-" 3590 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3591 } else { 3592 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3593 "i64:32:64-f32:32:32-f64:32:64-" 3594 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3595 } 3596 3597 // FIXME: Override "preferred align" for double and long long. 3598 } else if (Name == "aapcs" || Name == "aapcs-vfp") { 3599 // size_t is unsigned long on Darwin. 3600 if (getTriple().isOSDarwin()) 3601 SizeType = UnsignedLong; 3602 IsAAPCS = true; 3603 // FIXME: Enumerated types are variable width in straight AAPCS. 3604 } else if (Name == "aapcs-linux") { 3605 IsAAPCS = true; 3606 } else 3607 return false; 3608 3609 return true; 3610 } 3611 3612 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3613 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3614 Features["vfp2"] = true; 3615 else if (CPU == "cortex-a8" || CPU == "cortex-a15" || 3616 CPU == "cortex-a9" || CPU == "cortex-a9-mp") 3617 Features["neon"] = true; 3618 else if (CPU == "swift" || CPU == "cortex-a7") { 3619 Features["vfp4"] = true; 3620 Features["neon"] = true; 3621 } 3622 } 3623 3624 virtual bool HandleTargetFeatures(std::vector<std::string> &Features, 3625 DiagnosticsEngine &Diags) { 3626 FPU = 0; 3627 SoftFloat = SoftFloatABI = false; 3628 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3629 if (Features[i] == "+soft-float") 3630 SoftFloat = true; 3631 else if (Features[i] == "+soft-float-abi") 3632 SoftFloatABI = true; 3633 else if (Features[i] == "+vfp2") 3634 FPU |= VFP2FPU; 3635 else if (Features[i] == "+vfp3") 3636 FPU |= VFP3FPU; 3637 else if (Features[i] == "+vfp4") 3638 FPU |= VFP4FPU; 3639 else if (Features[i] == "+neon") 3640 FPU |= NeonFPU; 3641 } 3642 3643 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 3644 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 3645 return false; 3646 } 3647 3648 if (FPMath == FP_Neon) 3649 Features.push_back("+neonfp"); 3650 else if (FPMath == FP_VFP) 3651 Features.push_back("-neonfp"); 3652 3653 // Remove front-end specific options which the backend handles differently. 3654 std::vector<std::string>::iterator it; 3655 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3656 if (it != Features.end()) 3657 Features.erase(it); 3658 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3659 if (it != Features.end()) 3660 Features.erase(it); 3661 return true; 3662 } 3663 3664 virtual bool hasFeature(StringRef Feature) const { 3665 return llvm::StringSwitch<bool>(Feature) 3666 .Case("arm", true) 3667 .Case("softfloat", SoftFloat) 3668 .Case("thumb", IsThumb) 3669 .Case("neon", FPU == NeonFPU && !SoftFloat && 3670 StringRef(getCPUDefineSuffix(CPU)).startswith("7")) 3671 .Default(false); 3672 } 3673 // FIXME: Should we actually have some table instead of these switches? 3674 static const char *getCPUDefineSuffix(StringRef Name) { 3675 return llvm::StringSwitch<const char*>(Name) 3676 .Cases("arm8", "arm810", "4") 3677 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3678 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3679 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3680 .Case("ep9312", "4T") 3681 .Cases("arm10tdmi", "arm1020t", "5T") 3682 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3683 .Case("arm926ej-s", "5TEJ") 3684 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3685 .Cases("xscale", "iwmmxt", "5TE") 3686 .Case("arm1136j-s", "6J") 3687 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3688 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3689 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3690 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A") 3691 .Cases("cortex-a9", "cortex-a15", "7A") 3692 .Case("cortex-r5", "7R") 3693 .Case("cortex-a9-mp", "7F") 3694 .Case("swift", "7S") 3695 .Cases("cortex-m3", "cortex-m4", "7M") 3696 .Case("cortex-m0", "6M") 3697 .Case("cortex-a53", "8A") 3698 .Default(0); 3699 } 3700 static const char *getCPUProfile(StringRef Name) { 3701 return llvm::StringSwitch<const char*>(Name) 3702 .Cases("cortex-a8", "cortex-a9", "A") 3703 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 3704 .Case("cortex-r5", "R") 3705 .Default(""); 3706 } 3707 virtual bool setCPU(const std::string &Name) { 3708 if (!getCPUDefineSuffix(Name)) 3709 return false; 3710 3711 CPU = Name; 3712 return true; 3713 } 3714 virtual bool setFPMath(StringRef Name); 3715 virtual void getTargetDefines(const LangOptions &Opts, 3716 MacroBuilder &Builder) const { 3717 // Target identification. 3718 Builder.defineMacro("__arm"); 3719 Builder.defineMacro("__arm__"); 3720 3721 // Target properties. 3722 Builder.defineMacro("__ARMEL__"); 3723 Builder.defineMacro("__LITTLE_ENDIAN__"); 3724 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3725 3726 StringRef CPUArch = getCPUDefineSuffix(CPU); 3727 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 3728 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 3729 StringRef CPUProfile = getCPUProfile(CPU); 3730 if (!CPUProfile.empty()) 3731 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 3732 3733 // Subtarget options. 3734 3735 // FIXME: It's more complicated than this and we don't really support 3736 // interworking. 3737 if ('5' <= CPUArch[0] && CPUArch[0] <= '7') 3738 Builder.defineMacro("__THUMB_INTERWORK__"); 3739 3740 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 3741 // M-class CPUs on Darwin follow AAPCS, but not EABI. 3742 if (!(getTriple().isOSDarwin() && CPUProfile == "M")) 3743 Builder.defineMacro("__ARM_EABI__"); 3744 Builder.defineMacro("__ARM_PCS", "1"); 3745 3746 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 3747 Builder.defineMacro("__ARM_PCS_VFP", "1"); 3748 } 3749 3750 if (SoftFloat) 3751 Builder.defineMacro("__SOFTFP__"); 3752 3753 if (CPU == "xscale") 3754 Builder.defineMacro("__XSCALE__"); 3755 3756 bool IsARMv7 = CPUArch.startswith("7"); 3757 if (IsThumb) { 3758 Builder.defineMacro("__THUMBEL__"); 3759 Builder.defineMacro("__thumb__"); 3760 if (CPUArch == "6T2" || IsARMv7) 3761 Builder.defineMacro("__thumb2__"); 3762 } 3763 3764 // Note, this is always on in gcc, even though it doesn't make sense. 3765 Builder.defineMacro("__APCS_32__"); 3766 3767 if (FPUModeIsVFP((FPUMode) FPU)) { 3768 Builder.defineMacro("__VFP_FP__"); 3769 if (FPU & VFP2FPU) 3770 Builder.defineMacro("__ARM_VFPV2__"); 3771 if (FPU & VFP3FPU) 3772 Builder.defineMacro("__ARM_VFPV3__"); 3773 if (FPU & VFP4FPU) 3774 Builder.defineMacro("__ARM_VFPV4__"); 3775 } 3776 3777 // This only gets set when Neon instructions are actually available, unlike 3778 // the VFP define, hence the soft float and arch check. This is subtly 3779 // different from gcc, we follow the intent which was that it should be set 3780 // when Neon instructions are actually available. 3781 if ((FPU & NeonFPU) && !SoftFloat && IsARMv7) 3782 Builder.defineMacro("__ARM_NEON__"); 3783 } 3784 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3785 unsigned &NumRecords) const { 3786 Records = BuiltinInfo; 3787 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 3788 } 3789 virtual bool isCLZForZeroUndef() const { return false; } 3790 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3791 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 3792 } 3793 virtual void getGCCRegNames(const char * const *&Names, 3794 unsigned &NumNames) const; 3795 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3796 unsigned &NumAliases) const; 3797 virtual bool validateAsmConstraint(const char *&Name, 3798 TargetInfo::ConstraintInfo &Info) const { 3799 switch (*Name) { 3800 default: break; 3801 case 'l': // r0-r7 3802 case 'h': // r8-r15 3803 case 'w': // VFP Floating point register single precision 3804 case 'P': // VFP Floating point register double precision 3805 Info.setAllowsRegister(); 3806 return true; 3807 case 'Q': // A memory address that is a single base register. 3808 Info.setAllowsMemory(); 3809 return true; 3810 case 'U': // a memory reference... 3811 switch (Name[1]) { 3812 case 'q': // ...ARMV4 ldrsb 3813 case 'v': // ...VFP load/store (reg+constant offset) 3814 case 'y': // ...iWMMXt load/store 3815 case 't': // address valid for load/store opaque types wider 3816 // than 128-bits 3817 case 'n': // valid address for Neon doubleword vector load/store 3818 case 'm': // valid address for Neon element and structure load/store 3819 case 's': // valid address for non-offset loads/stores of quad-word 3820 // values in four ARM registers 3821 Info.setAllowsMemory(); 3822 Name++; 3823 return true; 3824 } 3825 } 3826 return false; 3827 } 3828 virtual std::string convertConstraint(const char *&Constraint) const { 3829 std::string R; 3830 switch (*Constraint) { 3831 case 'U': // Two-character constraint; add "^" hint for later parsing. 3832 R = std::string("^") + std::string(Constraint, 2); 3833 Constraint++; 3834 break; 3835 case 'p': // 'p' should be translated to 'r' by default. 3836 R = std::string("r"); 3837 break; 3838 default: 3839 return std::string(1, *Constraint); 3840 } 3841 return R; 3842 } 3843 virtual bool validateConstraintModifier(StringRef Constraint, 3844 const char Modifier, 3845 unsigned Size) const { 3846 bool isOutput = (Constraint[0] == '='); 3847 bool isInOut = (Constraint[0] == '+'); 3848 3849 // Strip off constraint modifiers. 3850 while (Constraint[0] == '=' || 3851 Constraint[0] == '+' || 3852 Constraint[0] == '&') 3853 Constraint = Constraint.substr(1); 3854 3855 switch (Constraint[0]) { 3856 default: break; 3857 case 'r': { 3858 switch (Modifier) { 3859 default: 3860 return (isInOut || isOutput || Size <= 32); 3861 case 'q': 3862 // A register of size 32 cannot fit a vector type. 3863 return false; 3864 } 3865 } 3866 } 3867 3868 return true; 3869 } 3870 virtual const char *getClobbers() const { 3871 // FIXME: Is this really right? 3872 return ""; 3873 } 3874 3875 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3876 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 3877 } 3878 3879 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 3880 if (RegNo == 0) return 0; 3881 if (RegNo == 1) return 1; 3882 return -1; 3883 } 3884 }; 3885 3886 bool ARMTargetInfo::setFPMath(StringRef Name) { 3887 if (Name == "neon") { 3888 FPMath = FP_Neon; 3889 return true; 3890 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 3891 Name == "vfp4") { 3892 FPMath = FP_VFP; 3893 return true; 3894 } 3895 return false; 3896 } 3897 3898 const char * const ARMTargetInfo::GCCRegNames[] = { 3899 // Integer registers 3900 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3901 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 3902 3903 // Float registers 3904 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3905 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3906 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3907 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3908 3909 // Double registers 3910 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3911 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3912 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3913 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3914 3915 // Quad registers 3916 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3917 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 3918 }; 3919 3920 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 3921 unsigned &NumNames) const { 3922 Names = GCCRegNames; 3923 NumNames = llvm::array_lengthof(GCCRegNames); 3924 } 3925 3926 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 3927 { { "a1" }, "r0" }, 3928 { { "a2" }, "r1" }, 3929 { { "a3" }, "r2" }, 3930 { { "a4" }, "r3" }, 3931 { { "v1" }, "r4" }, 3932 { { "v2" }, "r5" }, 3933 { { "v3" }, "r6" }, 3934 { { "v4" }, "r7" }, 3935 { { "v5" }, "r8" }, 3936 { { "v6", "rfp" }, "r9" }, 3937 { { "sl" }, "r10" }, 3938 { { "fp" }, "r11" }, 3939 { { "ip" }, "r12" }, 3940 { { "r13" }, "sp" }, 3941 { { "r14" }, "lr" }, 3942 { { "r15" }, "pc" }, 3943 // The S, D and Q registers overlap, but aren't really aliases; we 3944 // don't want to substitute one of these for a different-sized one. 3945 }; 3946 3947 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3948 unsigned &NumAliases) const { 3949 Aliases = GCCRegAliases; 3950 NumAliases = llvm::array_lengthof(GCCRegAliases); 3951 } 3952 3953 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 3954 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3955 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3956 ALL_LANGUAGES }, 3957 #include "clang/Basic/BuiltinsARM.def" 3958 }; 3959 } // end anonymous namespace. 3960 3961 namespace { 3962 class DarwinARMTargetInfo : 3963 public DarwinTargetInfo<ARMTargetInfo> { 3964 protected: 3965 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3966 MacroBuilder &Builder) const { 3967 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 3968 } 3969 3970 public: 3971 DarwinARMTargetInfo(const llvm::Triple &Triple) 3972 : DarwinTargetInfo<ARMTargetInfo>(Triple) { 3973 HasAlignMac68kSupport = true; 3974 // iOS always has 64-bit atomic instructions. 3975 // FIXME: This should be based off of the target features in ARMTargetInfo. 3976 MaxAtomicInlineWidth = 64; 3977 3978 // Darwin on iOS uses a variant of the ARM C++ ABI. 3979 TheCXXABI.set(TargetCXXABI::iOS); 3980 } 3981 }; 3982 } // end anonymous namespace. 3983 3984 3985 namespace { 3986 // Hexagon abstract base class 3987 class HexagonTargetInfo : public TargetInfo { 3988 static const Builtin::Info BuiltinInfo[]; 3989 static const char * const GCCRegNames[]; 3990 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3991 std::string CPU; 3992 public: 3993 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 3994 BigEndian = false; 3995 DescriptionString = ("e-p:32:32:32-" 3996 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-" 3997 "f64:64:64-f32:32:32-a0:0-n32"); 3998 3999 // {} in inline assembly are packet specifiers, not assembly variant 4000 // specifiers. 4001 NoAsmVariants = true; 4002 } 4003 4004 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4005 unsigned &NumRecords) const { 4006 Records = BuiltinInfo; 4007 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4008 } 4009 4010 virtual bool validateAsmConstraint(const char *&Name, 4011 TargetInfo::ConstraintInfo &Info) const { 4012 return true; 4013 } 4014 4015 virtual void getTargetDefines(const LangOptions &Opts, 4016 MacroBuilder &Builder) const; 4017 4018 virtual bool hasFeature(StringRef Feature) const { 4019 return Feature == "hexagon"; 4020 } 4021 4022 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4023 return TargetInfo::CharPtrBuiltinVaList; 4024 } 4025 virtual void getGCCRegNames(const char * const *&Names, 4026 unsigned &NumNames) const; 4027 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4028 unsigned &NumAliases) const; 4029 virtual const char *getClobbers() const { 4030 return ""; 4031 } 4032 4033 static const char *getHexagonCPUSuffix(StringRef Name) { 4034 return llvm::StringSwitch<const char*>(Name) 4035 .Case("hexagonv4", "4") 4036 .Case("hexagonv5", "5") 4037 .Default(0); 4038 } 4039 4040 virtual bool setCPU(const std::string &Name) { 4041 if (!getHexagonCPUSuffix(Name)) 4042 return false; 4043 4044 CPU = Name; 4045 return true; 4046 } 4047 }; 4048 4049 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4050 MacroBuilder &Builder) const { 4051 Builder.defineMacro("qdsp6"); 4052 Builder.defineMacro("__qdsp6", "1"); 4053 Builder.defineMacro("__qdsp6__", "1"); 4054 4055 Builder.defineMacro("hexagon"); 4056 Builder.defineMacro("__hexagon", "1"); 4057 Builder.defineMacro("__hexagon__", "1"); 4058 4059 if(CPU == "hexagonv1") { 4060 Builder.defineMacro("__HEXAGON_V1__"); 4061 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4062 if(Opts.HexagonQdsp6Compat) { 4063 Builder.defineMacro("__QDSP6_V1__"); 4064 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4065 } 4066 } 4067 else if(CPU == "hexagonv2") { 4068 Builder.defineMacro("__HEXAGON_V2__"); 4069 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4070 if(Opts.HexagonQdsp6Compat) { 4071 Builder.defineMacro("__QDSP6_V2__"); 4072 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4073 } 4074 } 4075 else if(CPU == "hexagonv3") { 4076 Builder.defineMacro("__HEXAGON_V3__"); 4077 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4078 if(Opts.HexagonQdsp6Compat) { 4079 Builder.defineMacro("__QDSP6_V3__"); 4080 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4081 } 4082 } 4083 else if(CPU == "hexagonv4") { 4084 Builder.defineMacro("__HEXAGON_V4__"); 4085 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4086 if(Opts.HexagonQdsp6Compat) { 4087 Builder.defineMacro("__QDSP6_V4__"); 4088 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4089 } 4090 } 4091 else if(CPU == "hexagonv5") { 4092 Builder.defineMacro("__HEXAGON_V5__"); 4093 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4094 if(Opts.HexagonQdsp6Compat) { 4095 Builder.defineMacro("__QDSP6_V5__"); 4096 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4097 } 4098 } 4099 } 4100 4101 const char * const HexagonTargetInfo::GCCRegNames[] = { 4102 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4103 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4104 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4105 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4106 "p0", "p1", "p2", "p3", 4107 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4108 }; 4109 4110 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4111 unsigned &NumNames) const { 4112 Names = GCCRegNames; 4113 NumNames = llvm::array_lengthof(GCCRegNames); 4114 } 4115 4116 4117 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4118 { { "sp" }, "r29" }, 4119 { { "fp" }, "r30" }, 4120 { { "lr" }, "r31" }, 4121 }; 4122 4123 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4124 unsigned &NumAliases) const { 4125 Aliases = GCCRegAliases; 4126 NumAliases = llvm::array_lengthof(GCCRegAliases); 4127 } 4128 4129 4130 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4131 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4132 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4133 ALL_LANGUAGES }, 4134 #include "clang/Basic/BuiltinsHexagon.def" 4135 }; 4136 } 4137 4138 4139 namespace { 4140 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4141 class SparcTargetInfo : public TargetInfo { 4142 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4143 static const char * const GCCRegNames[]; 4144 bool SoftFloat; 4145 public: 4146 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4147 4148 virtual bool HandleTargetFeatures(std::vector<std::string> &Features, 4149 DiagnosticsEngine &Diags) { 4150 SoftFloat = false; 4151 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4152 if (Features[i] == "+soft-float") 4153 SoftFloat = true; 4154 return true; 4155 } 4156 virtual void getTargetDefines(const LangOptions &Opts, 4157 MacroBuilder &Builder) const { 4158 DefineStd(Builder, "sparc", Opts); 4159 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4160 4161 if (SoftFloat) 4162 Builder.defineMacro("SOFT_FLOAT", "1"); 4163 } 4164 4165 virtual bool hasFeature(StringRef Feature) const { 4166 return llvm::StringSwitch<bool>(Feature) 4167 .Case("softfloat", SoftFloat) 4168 .Case("sparc", true) 4169 .Default(false); 4170 } 4171 4172 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4173 unsigned &NumRecords) const { 4174 // FIXME: Implement! 4175 } 4176 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4177 return TargetInfo::VoidPtrBuiltinVaList; 4178 } 4179 virtual void getGCCRegNames(const char * const *&Names, 4180 unsigned &NumNames) const; 4181 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4182 unsigned &NumAliases) const; 4183 virtual bool validateAsmConstraint(const char *&Name, 4184 TargetInfo::ConstraintInfo &info) const { 4185 // FIXME: Implement! 4186 return false; 4187 } 4188 virtual const char *getClobbers() const { 4189 // FIXME: Implement! 4190 return ""; 4191 } 4192 }; 4193 4194 const char * const SparcTargetInfo::GCCRegNames[] = { 4195 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4196 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4197 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4198 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4199 }; 4200 4201 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4202 unsigned &NumNames) const { 4203 Names = GCCRegNames; 4204 NumNames = llvm::array_lengthof(GCCRegNames); 4205 } 4206 4207 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4208 { { "g0" }, "r0" }, 4209 { { "g1" }, "r1" }, 4210 { { "g2" }, "r2" }, 4211 { { "g3" }, "r3" }, 4212 { { "g4" }, "r4" }, 4213 { { "g5" }, "r5" }, 4214 { { "g6" }, "r6" }, 4215 { { "g7" }, "r7" }, 4216 { { "o0" }, "r8" }, 4217 { { "o1" }, "r9" }, 4218 { { "o2" }, "r10" }, 4219 { { "o3" }, "r11" }, 4220 { { "o4" }, "r12" }, 4221 { { "o5" }, "r13" }, 4222 { { "o6", "sp" }, "r14" }, 4223 { { "o7" }, "r15" }, 4224 { { "l0" }, "r16" }, 4225 { { "l1" }, "r17" }, 4226 { { "l2" }, "r18" }, 4227 { { "l3" }, "r19" }, 4228 { { "l4" }, "r20" }, 4229 { { "l5" }, "r21" }, 4230 { { "l6" }, "r22" }, 4231 { { "l7" }, "r23" }, 4232 { { "i0" }, "r24" }, 4233 { { "i1" }, "r25" }, 4234 { { "i2" }, "r26" }, 4235 { { "i3" }, "r27" }, 4236 { { "i4" }, "r28" }, 4237 { { "i5" }, "r29" }, 4238 { { "i6", "fp" }, "r30" }, 4239 { { "i7" }, "r31" }, 4240 }; 4241 4242 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4243 unsigned &NumAliases) const { 4244 Aliases = GCCRegAliases; 4245 NumAliases = llvm::array_lengthof(GCCRegAliases); 4246 } 4247 4248 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 4249 class SparcV8TargetInfo : public SparcTargetInfo { 4250 public: 4251 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4252 // FIXME: Support Sparc quad-precision long double? 4253 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 4254 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 4255 } 4256 4257 virtual void getTargetDefines(const LangOptions &Opts, 4258 MacroBuilder &Builder) const { 4259 SparcTargetInfo::getTargetDefines(Opts, Builder); 4260 Builder.defineMacro("__sparcv8"); 4261 } 4262 }; 4263 4264 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 4265 class SparcV9TargetInfo : public SparcTargetInfo { 4266 public: 4267 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4268 // FIXME: Support Sparc quad-precision long double? 4269 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 4270 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128"; 4271 // This is an LP64 platform. 4272 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4273 4274 // OpenBSD uses long long for int64_t and intmax_t. 4275 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 4276 IntMaxType = SignedLongLong; 4277 UIntMaxType = UnsignedLongLong; 4278 } else { 4279 IntMaxType = SignedLong; 4280 UIntMaxType = UnsignedLong; 4281 } 4282 Int64Type = IntMaxType; 4283 } 4284 4285 virtual void getTargetDefines(const LangOptions &Opts, 4286 MacroBuilder &Builder) const { 4287 SparcTargetInfo::getTargetDefines(Opts, Builder); 4288 Builder.defineMacro("__sparcv9"); 4289 Builder.defineMacro("__arch64__"); 4290 // Solaris and its derivative AuroraUX don't need these variants, but the 4291 // BSDs do. 4292 if (getTriple().getOS() != llvm::Triple::Solaris && 4293 getTriple().getOS() != llvm::Triple::AuroraUX) { 4294 Builder.defineMacro("__sparc64__"); 4295 Builder.defineMacro("__sparc_v9__"); 4296 Builder.defineMacro("__sparcv9__"); 4297 } 4298 } 4299 }; 4300 4301 } // end anonymous namespace. 4302 4303 namespace { 4304 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 4305 public: 4306 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 4307 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 4308 SizeType = UnsignedInt; 4309 PtrDiffType = SignedInt; 4310 } 4311 }; 4312 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 4313 public: 4314 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 4315 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 4316 SizeType = UnsignedInt; 4317 PtrDiffType = SignedInt; 4318 } 4319 }; 4320 } // end anonymous namespace. 4321 4322 namespace { 4323 class SystemZTargetInfo : public TargetInfo { 4324 static const char *const GCCRegNames[]; 4325 4326 public: 4327 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4328 TLSSupported = true; 4329 IntWidth = IntAlign = 32; 4330 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 4331 PointerWidth = PointerAlign = 64; 4332 LongDoubleWidth = 128; 4333 LongDoubleAlign = 64; 4334 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4335 MinGlobalAlign = 16; 4336 DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64" 4337 "-f32:32-f64:64-f128:64-a0:8:16-n32:64"; 4338 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4339 } 4340 virtual void getTargetDefines(const LangOptions &Opts, 4341 MacroBuilder &Builder) const { 4342 Builder.defineMacro("__s390__"); 4343 Builder.defineMacro("__s390x__"); 4344 Builder.defineMacro("__zarch__"); 4345 Builder.defineMacro("__LONG_DOUBLE_128__"); 4346 } 4347 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4348 unsigned &NumRecords) const { 4349 // FIXME: Implement. 4350 Records = 0; 4351 NumRecords = 0; 4352 } 4353 4354 virtual void getGCCRegNames(const char *const *&Names, 4355 unsigned &NumNames) const; 4356 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4357 unsigned &NumAliases) const { 4358 // No aliases. 4359 Aliases = 0; 4360 NumAliases = 0; 4361 } 4362 virtual bool validateAsmConstraint(const char *&Name, 4363 TargetInfo::ConstraintInfo &info) const; 4364 virtual const char *getClobbers() const { 4365 // FIXME: Is this really right? 4366 return ""; 4367 } 4368 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4369 return TargetInfo::SystemZBuiltinVaList; 4370 } 4371 virtual bool setCPU(const std::string &Name) { 4372 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4373 .Case("z10", true) 4374 .Case("z196", true) 4375 .Case("zEC12", true) 4376 .Default(false); 4377 4378 // No need to store the CPU yet. There aren't any CPU-specific 4379 // macros to define. 4380 return CPUKnown; 4381 } 4382 }; 4383 4384 const char *const SystemZTargetInfo::GCCRegNames[] = { 4385 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4386 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4387 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 4388 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 4389 }; 4390 4391 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 4392 unsigned &NumNames) const { 4393 Names = GCCRegNames; 4394 NumNames = llvm::array_lengthof(GCCRegNames); 4395 } 4396 4397 bool SystemZTargetInfo:: 4398 validateAsmConstraint(const char *&Name, 4399 TargetInfo::ConstraintInfo &Info) const { 4400 switch (*Name) { 4401 default: 4402 return false; 4403 4404 case 'a': // Address register 4405 case 'd': // Data register (equivalent to 'r') 4406 case 'f': // Floating-point register 4407 Info.setAllowsRegister(); 4408 return true; 4409 4410 case 'I': // Unsigned 8-bit constant 4411 case 'J': // Unsigned 12-bit constant 4412 case 'K': // Signed 16-bit constant 4413 case 'L': // Signed 20-bit displacement (on all targets we support) 4414 case 'M': // 0x7fffffff 4415 return true; 4416 4417 case 'Q': // Memory with base and unsigned 12-bit displacement 4418 case 'R': // Likewise, plus an index 4419 case 'S': // Memory with base and signed 20-bit displacement 4420 case 'T': // Likewise, plus an index 4421 Info.setAllowsMemory(); 4422 return true; 4423 } 4424 } 4425 } 4426 4427 namespace { 4428 class MSP430TargetInfo : public TargetInfo { 4429 static const char * const GCCRegNames[]; 4430 public: 4431 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4432 BigEndian = false; 4433 TLSSupported = false; 4434 IntWidth = 16; IntAlign = 16; 4435 LongWidth = 32; LongLongWidth = 64; 4436 LongAlign = LongLongAlign = 16; 4437 PointerWidth = 16; PointerAlign = 16; 4438 SuitableAlign = 16; 4439 SizeType = UnsignedInt; 4440 IntMaxType = SignedLongLong; 4441 UIntMaxType = UnsignedLongLong; 4442 IntPtrType = SignedInt; 4443 PtrDiffType = SignedInt; 4444 SigAtomicType = SignedLong; 4445 DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"; 4446 } 4447 virtual void getTargetDefines(const LangOptions &Opts, 4448 MacroBuilder &Builder) const { 4449 Builder.defineMacro("MSP430"); 4450 Builder.defineMacro("__MSP430__"); 4451 // FIXME: defines for different 'flavours' of MCU 4452 } 4453 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4454 unsigned &NumRecords) const { 4455 // FIXME: Implement. 4456 Records = 0; 4457 NumRecords = 0; 4458 } 4459 virtual bool hasFeature(StringRef Feature) const { 4460 return Feature == "msp430"; 4461 } 4462 virtual void getGCCRegNames(const char * const *&Names, 4463 unsigned &NumNames) const; 4464 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4465 unsigned &NumAliases) const { 4466 // No aliases. 4467 Aliases = 0; 4468 NumAliases = 0; 4469 } 4470 virtual bool validateAsmConstraint(const char *&Name, 4471 TargetInfo::ConstraintInfo &info) const { 4472 // No target constraints for now. 4473 return false; 4474 } 4475 virtual const char *getClobbers() const { 4476 // FIXME: Is this really right? 4477 return ""; 4478 } 4479 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4480 // FIXME: implement 4481 return TargetInfo::CharPtrBuiltinVaList; 4482 } 4483 }; 4484 4485 const char * const MSP430TargetInfo::GCCRegNames[] = { 4486 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4487 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 4488 }; 4489 4490 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 4491 unsigned &NumNames) const { 4492 Names = GCCRegNames; 4493 NumNames = llvm::array_lengthof(GCCRegNames); 4494 } 4495 } 4496 4497 namespace { 4498 4499 // LLVM and Clang cannot be used directly to output native binaries for 4500 // target, but is used to compile C code to llvm bitcode with correct 4501 // type and alignment information. 4502 // 4503 // TCE uses the llvm bitcode as input and uses it for generating customized 4504 // target processor and program binary. TCE co-design environment is 4505 // publicly available in http://tce.cs.tut.fi 4506 4507 static const unsigned TCEOpenCLAddrSpaceMap[] = { 4508 3, // opencl_global 4509 4, // opencl_local 4510 5, // opencl_constant 4511 0, // cuda_device 4512 0, // cuda_constant 4513 0 // cuda_shared 4514 }; 4515 4516 class TCETargetInfo : public TargetInfo{ 4517 public: 4518 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4519 TLSSupported = false; 4520 IntWidth = 32; 4521 LongWidth = LongLongWidth = 32; 4522 PointerWidth = 32; 4523 IntAlign = 32; 4524 LongAlign = LongLongAlign = 32; 4525 PointerAlign = 32; 4526 SuitableAlign = 32; 4527 SizeType = UnsignedInt; 4528 IntMaxType = SignedLong; 4529 UIntMaxType = UnsignedLong; 4530 IntPtrType = SignedInt; 4531 PtrDiffType = SignedInt; 4532 FloatWidth = 32; 4533 FloatAlign = 32; 4534 DoubleWidth = 32; 4535 DoubleAlign = 32; 4536 LongDoubleWidth = 32; 4537 LongDoubleAlign = 32; 4538 FloatFormat = &llvm::APFloat::IEEEsingle; 4539 DoubleFormat = &llvm::APFloat::IEEEsingle; 4540 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 4541 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-" 4542 "i16:16:32-i32:32:32-i64:32:32-" 4543 "f32:32:32-f64:32:32-v64:32:32-" 4544 "v128:32:32-a0:0:32-n32"; 4545 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 4546 } 4547 4548 virtual void getTargetDefines(const LangOptions &Opts, 4549 MacroBuilder &Builder) const { 4550 DefineStd(Builder, "tce", Opts); 4551 Builder.defineMacro("__TCE__"); 4552 Builder.defineMacro("__TCE_V1__"); 4553 } 4554 virtual bool hasFeature(StringRef Feature) const { 4555 return Feature == "tce"; 4556 } 4557 4558 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4559 unsigned &NumRecords) const {} 4560 virtual const char *getClobbers() const { 4561 return ""; 4562 } 4563 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4564 return TargetInfo::VoidPtrBuiltinVaList; 4565 } 4566 virtual void getGCCRegNames(const char * const *&Names, 4567 unsigned &NumNames) const {} 4568 virtual bool validateAsmConstraint(const char *&Name, 4569 TargetInfo::ConstraintInfo &info) const { 4570 return true; 4571 } 4572 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4573 unsigned &NumAliases) const {} 4574 }; 4575 } 4576 4577 namespace { 4578 class MipsTargetInfoBase : public TargetInfo { 4579 static const Builtin::Info BuiltinInfo[]; 4580 std::string CPU; 4581 bool IsMips16; 4582 bool IsMicromips; 4583 bool IsSingleFloat; 4584 enum MipsFloatABI { 4585 HardFloat, SoftFloat 4586 } FloatABI; 4587 enum DspRevEnum { 4588 NoDSP, DSP1, DSP2 4589 } DspRev; 4590 bool HasMSA; 4591 4592 protected: 4593 std::string ABI; 4594 4595 public: 4596 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 4597 const std::string &CPUStr) 4598 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 4599 IsSingleFloat(false), FloatABI(HardFloat), DspRev(NoDSP), 4600 HasMSA(false), ABI(ABIStr) {} 4601 4602 virtual const char *getABI() const { return ABI.c_str(); } 4603 virtual bool setABI(const std::string &Name) = 0; 4604 virtual bool setCPU(const std::string &Name) { 4605 CPU = Name; 4606 return true; 4607 } 4608 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 4609 Features[ABI] = true; 4610 Features[CPU] = true; 4611 } 4612 4613 virtual void getTargetDefines(const LangOptions &Opts, 4614 MacroBuilder &Builder) const { 4615 DefineStd(Builder, "mips", Opts); 4616 Builder.defineMacro("_mips"); 4617 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4618 4619 switch (FloatABI) { 4620 case HardFloat: 4621 Builder.defineMacro("__mips_hard_float", Twine(1)); 4622 break; 4623 case SoftFloat: 4624 Builder.defineMacro("__mips_soft_float", Twine(1)); 4625 break; 4626 } 4627 4628 if (IsSingleFloat) 4629 Builder.defineMacro("__mips_single_float", Twine(1)); 4630 4631 if (IsMips16) 4632 Builder.defineMacro("__mips16", Twine(1)); 4633 4634 if (IsMicromips) 4635 Builder.defineMacro("__mips_micromips", Twine(1)); 4636 4637 switch (DspRev) { 4638 default: 4639 break; 4640 case DSP1: 4641 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 4642 Builder.defineMacro("__mips_dsp", Twine(1)); 4643 break; 4644 case DSP2: 4645 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 4646 Builder.defineMacro("__mips_dspr2", Twine(1)); 4647 Builder.defineMacro("__mips_dsp", Twine(1)); 4648 break; 4649 } 4650 4651 if (HasMSA) 4652 Builder.defineMacro("__mips_msa", Twine(1)); 4653 4654 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 4655 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 4656 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 4657 4658 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 4659 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 4660 } 4661 4662 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4663 unsigned &NumRecords) const { 4664 Records = BuiltinInfo; 4665 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 4666 } 4667 virtual bool hasFeature(StringRef Feature) const { 4668 return Feature == "mips"; 4669 } 4670 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4671 return TargetInfo::VoidPtrBuiltinVaList; 4672 } 4673 virtual void getGCCRegNames(const char * const *&Names, 4674 unsigned &NumNames) const { 4675 static const char * const GCCRegNames[] = { 4676 // CPU register names 4677 // Must match second column of GCCRegAliases 4678 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 4679 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 4680 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 4681 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 4682 // Floating point register names 4683 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 4684 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 4685 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 4686 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 4687 // Hi/lo and condition register names 4688 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 4689 "$fcc5","$fcc6","$fcc7" 4690 }; 4691 Names = GCCRegNames; 4692 NumNames = llvm::array_lengthof(GCCRegNames); 4693 } 4694 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4695 unsigned &NumAliases) const = 0; 4696 virtual bool validateAsmConstraint(const char *&Name, 4697 TargetInfo::ConstraintInfo &Info) const { 4698 switch (*Name) { 4699 default: 4700 return false; 4701 4702 case 'r': // CPU registers. 4703 case 'd': // Equivalent to "r" unless generating MIPS16 code. 4704 case 'y': // Equivalent to "r", backwards compatibility only. 4705 case 'f': // floating-point registers. 4706 case 'c': // $25 for indirect jumps 4707 case 'l': // lo register 4708 case 'x': // hilo register pair 4709 Info.setAllowsRegister(); 4710 return true; 4711 case 'R': // An address that can be used in a non-macro load or store 4712 Info.setAllowsMemory(); 4713 return true; 4714 } 4715 } 4716 4717 virtual const char *getClobbers() const { 4718 // FIXME: Implement! 4719 return ""; 4720 } 4721 4722 virtual bool HandleTargetFeatures(std::vector<std::string> &Features, 4723 DiagnosticsEngine &Diags) { 4724 IsMips16 = false; 4725 IsMicromips = false; 4726 IsSingleFloat = false; 4727 FloatABI = HardFloat; 4728 DspRev = NoDSP; 4729 4730 for (std::vector<std::string>::iterator it = Features.begin(), 4731 ie = Features.end(); it != ie; ++it) { 4732 if (*it == "+single-float") 4733 IsSingleFloat = true; 4734 else if (*it == "+soft-float") 4735 FloatABI = SoftFloat; 4736 else if (*it == "+mips16") 4737 IsMips16 = true; 4738 else if (*it == "+micromips") 4739 IsMicromips = true; 4740 else if (*it == "+dsp") 4741 DspRev = std::max(DspRev, DSP1); 4742 else if (*it == "+dspr2") 4743 DspRev = std::max(DspRev, DSP2); 4744 else if (*it == "+msa") 4745 HasMSA = true; 4746 } 4747 4748 // Remove front-end specific option. 4749 std::vector<std::string>::iterator it = 4750 std::find(Features.begin(), Features.end(), "+soft-float"); 4751 if (it != Features.end()) 4752 Features.erase(it); 4753 4754 return true; 4755 } 4756 4757 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 4758 if (RegNo == 0) return 4; 4759 if (RegNo == 1) return 5; 4760 return -1; 4761 } 4762 }; 4763 4764 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 4765 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4766 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4767 ALL_LANGUAGES }, 4768 #include "clang/Basic/BuiltinsMips.def" 4769 }; 4770 4771 class Mips32TargetInfoBase : public MipsTargetInfoBase { 4772 public: 4773 Mips32TargetInfoBase(const llvm::Triple &Triple) 4774 : MipsTargetInfoBase(Triple, "o32", "mips32") { 4775 SizeType = UnsignedInt; 4776 PtrDiffType = SignedInt; 4777 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 4778 } 4779 virtual bool setABI(const std::string &Name) { 4780 if ((Name == "o32") || (Name == "eabi")) { 4781 ABI = Name; 4782 return true; 4783 } else if (Name == "32") { 4784 ABI = "o32"; 4785 return true; 4786 } else 4787 return false; 4788 } 4789 virtual void getTargetDefines(const LangOptions &Opts, 4790 MacroBuilder &Builder) const { 4791 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 4792 4793 if (ABI == "o32") { 4794 Builder.defineMacro("__mips_o32"); 4795 Builder.defineMacro("_ABIO32", "1"); 4796 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 4797 } 4798 else if (ABI == "eabi") 4799 Builder.defineMacro("__mips_eabi"); 4800 else 4801 llvm_unreachable("Invalid ABI for Mips32."); 4802 } 4803 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4804 unsigned &NumAliases) const { 4805 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 4806 { { "at" }, "$1" }, 4807 { { "v0" }, "$2" }, 4808 { { "v1" }, "$3" }, 4809 { { "a0" }, "$4" }, 4810 { { "a1" }, "$5" }, 4811 { { "a2" }, "$6" }, 4812 { { "a3" }, "$7" }, 4813 { { "t0" }, "$8" }, 4814 { { "t1" }, "$9" }, 4815 { { "t2" }, "$10" }, 4816 { { "t3" }, "$11" }, 4817 { { "t4" }, "$12" }, 4818 { { "t5" }, "$13" }, 4819 { { "t6" }, "$14" }, 4820 { { "t7" }, "$15" }, 4821 { { "s0" }, "$16" }, 4822 { { "s1" }, "$17" }, 4823 { { "s2" }, "$18" }, 4824 { { "s3" }, "$19" }, 4825 { { "s4" }, "$20" }, 4826 { { "s5" }, "$21" }, 4827 { { "s6" }, "$22" }, 4828 { { "s7" }, "$23" }, 4829 { { "t8" }, "$24" }, 4830 { { "t9" }, "$25" }, 4831 { { "k0" }, "$26" }, 4832 { { "k1" }, "$27" }, 4833 { { "gp" }, "$28" }, 4834 { { "sp","$sp" }, "$29" }, 4835 { { "fp","$fp" }, "$30" }, 4836 { { "ra" }, "$31" } 4837 }; 4838 Aliases = GCCRegAliases; 4839 NumAliases = llvm::array_lengthof(GCCRegAliases); 4840 } 4841 }; 4842 4843 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 4844 public: 4845 Mips32EBTargetInfo(const llvm::Triple &Triple) 4846 : Mips32TargetInfoBase(Triple) { 4847 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4848 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 4849 } 4850 virtual void getTargetDefines(const LangOptions &Opts, 4851 MacroBuilder &Builder) const { 4852 DefineStd(Builder, "MIPSEB", Opts); 4853 Builder.defineMacro("_MIPSEB"); 4854 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 4855 } 4856 }; 4857 4858 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 4859 public: 4860 Mips32ELTargetInfo(const llvm::Triple &Triple) 4861 : Mips32TargetInfoBase(Triple) { 4862 BigEndian = false; 4863 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4864 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 4865 } 4866 virtual void getTargetDefines(const LangOptions &Opts, 4867 MacroBuilder &Builder) const { 4868 DefineStd(Builder, "MIPSEL", Opts); 4869 Builder.defineMacro("_MIPSEL"); 4870 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 4871 } 4872 }; 4873 4874 class Mips64TargetInfoBase : public MipsTargetInfoBase { 4875 virtual void SetDescriptionString(const std::string &Name) = 0; 4876 public: 4877 Mips64TargetInfoBase(const llvm::Triple &Triple) 4878 : MipsTargetInfoBase(Triple, "n64", "mips64") { 4879 LongWidth = LongAlign = 64; 4880 PointerWidth = PointerAlign = 64; 4881 LongDoubleWidth = LongDoubleAlign = 128; 4882 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4883 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 4884 LongDoubleWidth = LongDoubleAlign = 64; 4885 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4886 } 4887 SuitableAlign = 128; 4888 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4889 } 4890 virtual bool setABI(const std::string &Name) { 4891 SetDescriptionString(Name); 4892 if (Name == "n32") { 4893 LongWidth = LongAlign = 32; 4894 PointerWidth = PointerAlign = 32; 4895 ABI = Name; 4896 return true; 4897 } else if (Name == "n64") { 4898 ABI = Name; 4899 return true; 4900 } else if (Name == "64") { 4901 ABI = "n64"; 4902 return true; 4903 } else 4904 return false; 4905 } 4906 virtual void getTargetDefines(const LangOptions &Opts, 4907 MacroBuilder &Builder) const { 4908 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 4909 4910 Builder.defineMacro("__mips64"); 4911 Builder.defineMacro("__mips64__"); 4912 4913 if (ABI == "n32") { 4914 Builder.defineMacro("__mips_n32"); 4915 Builder.defineMacro("_ABIN32", "2"); 4916 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 4917 } 4918 else if (ABI == "n64") { 4919 Builder.defineMacro("__mips_n64"); 4920 Builder.defineMacro("_ABI64", "3"); 4921 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 4922 } 4923 else 4924 llvm_unreachable("Invalid ABI for Mips64."); 4925 } 4926 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4927 unsigned &NumAliases) const { 4928 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 4929 { { "at" }, "$1" }, 4930 { { "v0" }, "$2" }, 4931 { { "v1" }, "$3" }, 4932 { { "a0" }, "$4" }, 4933 { { "a1" }, "$5" }, 4934 { { "a2" }, "$6" }, 4935 { { "a3" }, "$7" }, 4936 { { "a4" }, "$8" }, 4937 { { "a5" }, "$9" }, 4938 { { "a6" }, "$10" }, 4939 { { "a7" }, "$11" }, 4940 { { "t0" }, "$12" }, 4941 { { "t1" }, "$13" }, 4942 { { "t2" }, "$14" }, 4943 { { "t3" }, "$15" }, 4944 { { "s0" }, "$16" }, 4945 { { "s1" }, "$17" }, 4946 { { "s2" }, "$18" }, 4947 { { "s3" }, "$19" }, 4948 { { "s4" }, "$20" }, 4949 { { "s5" }, "$21" }, 4950 { { "s6" }, "$22" }, 4951 { { "s7" }, "$23" }, 4952 { { "t8" }, "$24" }, 4953 { { "t9" }, "$25" }, 4954 { { "k0" }, "$26" }, 4955 { { "k1" }, "$27" }, 4956 { { "gp" }, "$28" }, 4957 { { "sp","$sp" }, "$29" }, 4958 { { "fp","$fp" }, "$30" }, 4959 { { "ra" }, "$31" } 4960 }; 4961 Aliases = GCCRegAliases; 4962 NumAliases = llvm::array_lengthof(GCCRegAliases); 4963 } 4964 }; 4965 4966 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 4967 virtual void SetDescriptionString(const std::string &Name) { 4968 // Change DescriptionString only if ABI is n32. 4969 if (Name == "n32") 4970 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4971 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 4972 "v64:64:64-n32:64-S128"; 4973 } 4974 public: 4975 Mips64EBTargetInfo(const llvm::Triple &Triple) 4976 : Mips64TargetInfoBase(Triple) { 4977 // Default ABI is n64. 4978 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4979 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 4980 "v64:64:64-n32:64-S128"; 4981 } 4982 virtual void getTargetDefines(const LangOptions &Opts, 4983 MacroBuilder &Builder) const { 4984 DefineStd(Builder, "MIPSEB", Opts); 4985 Builder.defineMacro("_MIPSEB"); 4986 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 4987 } 4988 }; 4989 4990 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 4991 virtual void SetDescriptionString(const std::string &Name) { 4992 // Change DescriptionString only if ABI is n32. 4993 if (Name == "n32") 4994 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4995 "i64:64:64-f32:32:32-f64:64:64-f128:128:128" 4996 "-v64:64:64-n32:64-S128"; 4997 } 4998 public: 4999 Mips64ELTargetInfo(const llvm::Triple &Triple) 5000 : Mips64TargetInfoBase(Triple) { 5001 // Default ABI is n64. 5002 BigEndian = false; 5003 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5004 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5005 "v64:64:64-n32:64-S128"; 5006 } 5007 virtual void getTargetDefines(const LangOptions &Opts, 5008 MacroBuilder &Builder) const { 5009 DefineStd(Builder, "MIPSEL", Opts); 5010 Builder.defineMacro("_MIPSEL"); 5011 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5012 } 5013 }; 5014 } // end anonymous namespace. 5015 5016 namespace { 5017 class PNaClTargetInfo : public TargetInfo { 5018 public: 5019 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5020 BigEndian = false; 5021 this->UserLabelPrefix = ""; 5022 this->LongAlign = 32; 5023 this->LongWidth = 32; 5024 this->PointerAlign = 32; 5025 this->PointerWidth = 32; 5026 this->IntMaxType = TargetInfo::SignedLongLong; 5027 this->UIntMaxType = TargetInfo::UnsignedLongLong; 5028 this->Int64Type = TargetInfo::SignedLongLong; 5029 this->DoubleAlign = 64; 5030 this->LongDoubleWidth = 64; 5031 this->LongDoubleAlign = 64; 5032 this->SizeType = TargetInfo::UnsignedInt; 5033 this->PtrDiffType = TargetInfo::SignedInt; 5034 this->IntPtrType = TargetInfo::SignedInt; 5035 this->RegParmMax = 0; // Disallow regparm 5036 DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5037 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 5038 } 5039 5040 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 5041 } 5042 virtual void getArchDefines(const LangOptions &Opts, 5043 MacroBuilder &Builder) const { 5044 Builder.defineMacro("__le32__"); 5045 Builder.defineMacro("__pnacl__"); 5046 } 5047 virtual void getTargetDefines(const LangOptions &Opts, 5048 MacroBuilder &Builder) const { 5049 Builder.defineMacro("__LITTLE_ENDIAN__"); 5050 getArchDefines(Opts, Builder); 5051 } 5052 virtual bool hasFeature(StringRef Feature) const { 5053 return Feature == "pnacl"; 5054 } 5055 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5056 unsigned &NumRecords) const { 5057 } 5058 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5059 return TargetInfo::PNaClABIBuiltinVaList; 5060 } 5061 virtual void getGCCRegNames(const char * const *&Names, 5062 unsigned &NumNames) const; 5063 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5064 unsigned &NumAliases) const; 5065 virtual bool validateAsmConstraint(const char *&Name, 5066 TargetInfo::ConstraintInfo &Info) const { 5067 return false; 5068 } 5069 5070 virtual const char *getClobbers() const { 5071 return ""; 5072 } 5073 }; 5074 5075 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5076 unsigned &NumNames) const { 5077 Names = NULL; 5078 NumNames = 0; 5079 } 5080 5081 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5082 unsigned &NumAliases) const { 5083 Aliases = NULL; 5084 NumAliases = 0; 5085 } 5086 } // end anonymous namespace. 5087 5088 namespace { 5089 static const unsigned SPIRAddrSpaceMap[] = { 5090 1, // opencl_global 5091 3, // opencl_local 5092 2, // opencl_constant 5093 0, // cuda_device 5094 0, // cuda_constant 5095 0 // cuda_shared 5096 }; 5097 class SPIRTargetInfo : public TargetInfo { 5098 static const char * const GCCRegNames[]; 5099 static const Builtin::Info BuiltinInfo[]; 5100 public: 5101 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5102 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5103 "SPIR target must use unknown OS"); 5104 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5105 "SPIR target must use unknown environment type"); 5106 BigEndian = false; 5107 TLSSupported = false; 5108 LongWidth = LongAlign = 64; 5109 AddrSpaceMap = &SPIRAddrSpaceMap; 5110 // Define available target features 5111 // These must be defined in sorted order! 5112 NoAsmVariants = true; 5113 } 5114 virtual void getTargetDefines(const LangOptions &Opts, 5115 MacroBuilder &Builder) const { 5116 DefineStd(Builder, "SPIR", Opts); 5117 } 5118 virtual bool hasFeature(StringRef Feature) const { 5119 return Feature == "spir"; 5120 } 5121 5122 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5123 unsigned &NumRecords) const {} 5124 virtual const char *getClobbers() const { 5125 return ""; 5126 } 5127 virtual void getGCCRegNames(const char * const *&Names, 5128 unsigned &NumNames) const {} 5129 virtual bool validateAsmConstraint(const char *&Name, 5130 TargetInfo::ConstraintInfo &info) const { 5131 return true; 5132 } 5133 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5134 unsigned &NumAliases) const {} 5135 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5136 return TargetInfo::VoidPtrBuiltinVaList; 5137 } 5138 }; 5139 5140 5141 class SPIR32TargetInfo : public SPIRTargetInfo { 5142 public: 5143 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5144 PointerWidth = PointerAlign = 32; 5145 SizeType = TargetInfo::UnsignedInt; 5146 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 5147 DescriptionString 5148 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5149 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-" 5150 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-" 5151 "v512:512:512-v1024:1024:1024"; 5152 } 5153 virtual void getTargetDefines(const LangOptions &Opts, 5154 MacroBuilder &Builder) const { 5155 DefineStd(Builder, "SPIR32", Opts); 5156 } 5157 }; 5158 5159 class SPIR64TargetInfo : public SPIRTargetInfo { 5160 public: 5161 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5162 PointerWidth = PointerAlign = 64; 5163 SizeType = TargetInfo::UnsignedLong; 5164 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 5165 DescriptionString 5166 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5167 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-" 5168 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-" 5169 "v512:512:512-v1024:1024:1024"; 5170 } 5171 virtual void getTargetDefines(const LangOptions &Opts, 5172 MacroBuilder &Builder) const { 5173 DefineStd(Builder, "SPIR64", Opts); 5174 } 5175 }; 5176 } 5177 5178 namespace { 5179 class XCoreTargetInfo : public TargetInfo { 5180 static const Builtin::Info BuiltinInfo[]; 5181 public: 5182 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5183 BigEndian = false; 5184 NoAsmVariants = true; 5185 LongLongAlign = 32; 5186 SuitableAlign = 32; 5187 DoubleAlign = LongDoubleAlign = 32; 5188 UseZeroLengthBitfieldAlignment = true; 5189 DescriptionString = "e-p:32:32:32-a0:0:32-n32" 5190 "-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32" 5191 "-f16:16:32-f32:32:32-f64:32:32"; 5192 } 5193 virtual void getTargetDefines(const LangOptions &Opts, 5194 MacroBuilder &Builder) const { 5195 Builder.defineMacro("__XS1B__"); 5196 } 5197 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5198 unsigned &NumRecords) const { 5199 Records = BuiltinInfo; 5200 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 5201 } 5202 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5203 return TargetInfo::VoidPtrBuiltinVaList; 5204 } 5205 virtual const char *getClobbers() const { 5206 return ""; 5207 } 5208 virtual void getGCCRegNames(const char * const *&Names, 5209 unsigned &NumNames) const { 5210 static const char * const GCCRegNames[] = { 5211 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5212 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 5213 }; 5214 Names = GCCRegNames; 5215 NumNames = llvm::array_lengthof(GCCRegNames); 5216 } 5217 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5218 unsigned &NumAliases) const { 5219 Aliases = NULL; 5220 NumAliases = 0; 5221 } 5222 virtual bool validateAsmConstraint(const char *&Name, 5223 TargetInfo::ConstraintInfo &Info) const { 5224 return false; 5225 } 5226 }; 5227 5228 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 5229 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5230 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5231 ALL_LANGUAGES }, 5232 #include "clang/Basic/BuiltinsXCore.def" 5233 }; 5234 } // end anonymous namespace. 5235 5236 5237 //===----------------------------------------------------------------------===// 5238 // Driver code 5239 //===----------------------------------------------------------------------===// 5240 5241 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 5242 llvm::Triple::OSType os = Triple.getOS(); 5243 5244 switch (Triple.getArch()) { 5245 default: 5246 return NULL; 5247 5248 case llvm::Triple::xcore: 5249 return new XCoreTargetInfo(Triple); 5250 5251 case llvm::Triple::hexagon: 5252 return new HexagonTargetInfo(Triple); 5253 5254 case llvm::Triple::aarch64: 5255 switch (os) { 5256 case llvm::Triple::Linux: 5257 return new LinuxTargetInfo<AArch64TargetInfo>(Triple); 5258 default: 5259 return new AArch64TargetInfo(Triple); 5260 } 5261 5262 case llvm::Triple::arm: 5263 case llvm::Triple::thumb: 5264 if (Triple.isOSDarwin()) 5265 return new DarwinARMTargetInfo(Triple); 5266 5267 switch (os) { 5268 case llvm::Triple::Linux: 5269 return new LinuxTargetInfo<ARMTargetInfo>(Triple); 5270 case llvm::Triple::FreeBSD: 5271 return new FreeBSDTargetInfo<ARMTargetInfo>(Triple); 5272 case llvm::Triple::NetBSD: 5273 return new NetBSDTargetInfo<ARMTargetInfo>(Triple); 5274 case llvm::Triple::OpenBSD: 5275 return new OpenBSDTargetInfo<ARMTargetInfo>(Triple); 5276 case llvm::Triple::Bitrig: 5277 return new BitrigTargetInfo<ARMTargetInfo>(Triple); 5278 case llvm::Triple::RTEMS: 5279 return new RTEMSTargetInfo<ARMTargetInfo>(Triple); 5280 case llvm::Triple::NaCl: 5281 return new NaClTargetInfo<ARMTargetInfo>(Triple); 5282 default: 5283 return new ARMTargetInfo(Triple); 5284 } 5285 5286 case llvm::Triple::msp430: 5287 return new MSP430TargetInfo(Triple); 5288 5289 case llvm::Triple::mips: 5290 switch (os) { 5291 case llvm::Triple::Linux: 5292 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 5293 case llvm::Triple::RTEMS: 5294 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 5295 case llvm::Triple::FreeBSD: 5296 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5297 case llvm::Triple::NetBSD: 5298 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5299 default: 5300 return new Mips32EBTargetInfo(Triple); 5301 } 5302 5303 case llvm::Triple::mipsel: 5304 switch (os) { 5305 case llvm::Triple::Linux: 5306 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 5307 case llvm::Triple::RTEMS: 5308 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 5309 case llvm::Triple::FreeBSD: 5310 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5311 case llvm::Triple::NetBSD: 5312 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5313 default: 5314 return new Mips32ELTargetInfo(Triple); 5315 } 5316 5317 case llvm::Triple::mips64: 5318 switch (os) { 5319 case llvm::Triple::Linux: 5320 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 5321 case llvm::Triple::RTEMS: 5322 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 5323 case llvm::Triple::FreeBSD: 5324 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5325 case llvm::Triple::NetBSD: 5326 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5327 case llvm::Triple::OpenBSD: 5328 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5329 default: 5330 return new Mips64EBTargetInfo(Triple); 5331 } 5332 5333 case llvm::Triple::mips64el: 5334 switch (os) { 5335 case llvm::Triple::Linux: 5336 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 5337 case llvm::Triple::RTEMS: 5338 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 5339 case llvm::Triple::FreeBSD: 5340 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5341 case llvm::Triple::NetBSD: 5342 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5343 case llvm::Triple::OpenBSD: 5344 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5345 default: 5346 return new Mips64ELTargetInfo(Triple); 5347 } 5348 5349 case llvm::Triple::le32: 5350 switch (os) { 5351 case llvm::Triple::NaCl: 5352 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 5353 default: 5354 return NULL; 5355 } 5356 5357 case llvm::Triple::ppc: 5358 if (Triple.isOSDarwin()) 5359 return new DarwinPPC32TargetInfo(Triple); 5360 switch (os) { 5361 case llvm::Triple::Linux: 5362 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 5363 case llvm::Triple::FreeBSD: 5364 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 5365 case llvm::Triple::NetBSD: 5366 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 5367 case llvm::Triple::OpenBSD: 5368 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 5369 case llvm::Triple::RTEMS: 5370 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 5371 default: 5372 return new PPC32TargetInfo(Triple); 5373 } 5374 5375 case llvm::Triple::ppc64: 5376 if (Triple.isOSDarwin()) 5377 return new DarwinPPC64TargetInfo(Triple); 5378 switch (os) { 5379 case llvm::Triple::Linux: 5380 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5381 case llvm::Triple::Lv2: 5382 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 5383 case llvm::Triple::FreeBSD: 5384 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 5385 case llvm::Triple::NetBSD: 5386 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 5387 default: 5388 return new PPC64TargetInfo(Triple); 5389 } 5390 5391 case llvm::Triple::ppc64le: 5392 switch (os) { 5393 case llvm::Triple::Linux: 5394 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5395 default: 5396 return new PPC64TargetInfo(Triple); 5397 } 5398 5399 case llvm::Triple::nvptx: 5400 return new NVPTX32TargetInfo(Triple); 5401 case llvm::Triple::nvptx64: 5402 return new NVPTX64TargetInfo(Triple); 5403 5404 case llvm::Triple::r600: 5405 return new R600TargetInfo(Triple); 5406 5407 case llvm::Triple::sparc: 5408 switch (os) { 5409 case llvm::Triple::Linux: 5410 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 5411 case llvm::Triple::AuroraUX: 5412 return new AuroraUXSparcV8TargetInfo(Triple); 5413 case llvm::Triple::Solaris: 5414 return new SolarisSparcV8TargetInfo(Triple); 5415 case llvm::Triple::NetBSD: 5416 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 5417 case llvm::Triple::OpenBSD: 5418 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 5419 case llvm::Triple::RTEMS: 5420 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 5421 default: 5422 return new SparcV8TargetInfo(Triple); 5423 } 5424 5425 case llvm::Triple::sparcv9: 5426 switch (os) { 5427 case llvm::Triple::Linux: 5428 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 5429 case llvm::Triple::AuroraUX: 5430 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 5431 case llvm::Triple::Solaris: 5432 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 5433 case llvm::Triple::NetBSD: 5434 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 5435 case llvm::Triple::OpenBSD: 5436 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 5437 case llvm::Triple::FreeBSD: 5438 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 5439 default: 5440 return new SparcV9TargetInfo(Triple); 5441 } 5442 5443 case llvm::Triple::systemz: 5444 switch (os) { 5445 case llvm::Triple::Linux: 5446 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 5447 default: 5448 return new SystemZTargetInfo(Triple); 5449 } 5450 5451 case llvm::Triple::tce: 5452 return new TCETargetInfo(Triple); 5453 5454 case llvm::Triple::x86: 5455 if (Triple.isOSDarwin()) 5456 return new DarwinI386TargetInfo(Triple); 5457 5458 switch (os) { 5459 case llvm::Triple::AuroraUX: 5460 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 5461 case llvm::Triple::Linux: 5462 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 5463 case llvm::Triple::DragonFly: 5464 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 5465 case llvm::Triple::NetBSD: 5466 return new NetBSDI386TargetInfo(Triple); 5467 case llvm::Triple::OpenBSD: 5468 return new OpenBSDI386TargetInfo(Triple); 5469 case llvm::Triple::Bitrig: 5470 return new BitrigI386TargetInfo(Triple); 5471 case llvm::Triple::FreeBSD: 5472 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5473 case llvm::Triple::Minix: 5474 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 5475 case llvm::Triple::Solaris: 5476 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 5477 case llvm::Triple::Cygwin: 5478 return new CygwinX86_32TargetInfo(Triple); 5479 case llvm::Triple::MinGW32: 5480 return new MinGWX86_32TargetInfo(Triple); 5481 case llvm::Triple::Win32: 5482 return new VisualStudioWindowsX86_32TargetInfo(Triple); 5483 case llvm::Triple::Haiku: 5484 return new HaikuX86_32TargetInfo(Triple); 5485 case llvm::Triple::RTEMS: 5486 return new RTEMSX86_32TargetInfo(Triple); 5487 case llvm::Triple::NaCl: 5488 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 5489 default: 5490 return new X86_32TargetInfo(Triple); 5491 } 5492 5493 case llvm::Triple::x86_64: 5494 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO) 5495 return new DarwinX86_64TargetInfo(Triple); 5496 5497 switch (os) { 5498 case llvm::Triple::AuroraUX: 5499 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 5500 case llvm::Triple::Linux: 5501 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 5502 case llvm::Triple::DragonFly: 5503 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 5504 case llvm::Triple::NetBSD: 5505 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 5506 case llvm::Triple::OpenBSD: 5507 return new OpenBSDX86_64TargetInfo(Triple); 5508 case llvm::Triple::Bitrig: 5509 return new BitrigX86_64TargetInfo(Triple); 5510 case llvm::Triple::FreeBSD: 5511 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5512 case llvm::Triple::Solaris: 5513 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 5514 case llvm::Triple::MinGW32: 5515 return new MinGWX86_64TargetInfo(Triple); 5516 case llvm::Triple::Win32: // This is what Triple.h supports now. 5517 return new VisualStudioWindowsX86_64TargetInfo(Triple); 5518 case llvm::Triple::NaCl: 5519 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 5520 default: 5521 return new X86_64TargetInfo(Triple); 5522 } 5523 5524 case llvm::Triple::spir: { 5525 if (Triple.getOS() != llvm::Triple::UnknownOS || 5526 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5527 return NULL; 5528 return new SPIR32TargetInfo(Triple); 5529 } 5530 case llvm::Triple::spir64: { 5531 if (Triple.getOS() != llvm::Triple::UnknownOS || 5532 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5533 return NULL; 5534 return new SPIR64TargetInfo(Triple); 5535 } 5536 } 5537 } 5538 5539 /// CreateTargetInfo - Return the target info object for the specified target 5540 /// triple. 5541 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 5542 TargetOptions *Opts) { 5543 llvm::Triple Triple(Opts->Triple); 5544 5545 // Construct the target 5546 OwningPtr<TargetInfo> Target(AllocateTarget(Triple)); 5547 if (!Target) { 5548 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 5549 return 0; 5550 } 5551 Target->setTargetOpts(Opts); 5552 5553 // Set the target CPU if specified. 5554 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 5555 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 5556 return 0; 5557 } 5558 5559 // Set the target ABI if specified. 5560 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 5561 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 5562 return 0; 5563 } 5564 5565 // Set the target C++ ABI. 5566 if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) { 5567 Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI; 5568 return 0; 5569 } 5570 5571 // Set the fp math unit. 5572 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 5573 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 5574 return 0; 5575 } 5576 5577 // Compute the default target features, we need the target to handle this 5578 // because features may have dependencies on one another. 5579 llvm::StringMap<bool> Features; 5580 Target->getDefaultFeatures(Features); 5581 5582 // Apply the user specified deltas. 5583 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 5584 I < N; ++I) { 5585 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 5586 // Apply the feature via the target. 5587 bool Enabled = Name[0] == '+'; 5588 Target->setFeatureEnabled(Features, Name + 1, Enabled); 5589 } 5590 5591 // Add the features to the compile options. 5592 // 5593 // FIXME: If we are completely confident that we have the right set, we only 5594 // need to pass the minuses. 5595 Opts->Features.clear(); 5596 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 5597 ie = Features.end(); it != ie; ++it) 5598 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 5599 if (!Target->HandleTargetFeatures(Opts->Features, Diags)) 5600 return 0; 5601 5602 return Target.take(); 5603 } 5604