1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include <algorithm>
32 #include <memory>
33 using namespace clang;
34 
35 //===----------------------------------------------------------------------===//
36 //  Common code shared among targets.
37 //===----------------------------------------------------------------------===//
38 
39 /// DefineStd - Define a macro name and standard variants.  For example if
40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
41 /// when in GNU mode.
42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
43                       const LangOptions &Opts) {
44   assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
45 
46   // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
47   // in the user's namespace.
48   if (Opts.GNUMode)
49     Builder.defineMacro(MacroName);
50 
51   // Define __unix.
52   Builder.defineMacro("__" + MacroName);
53 
54   // Define __unix__.
55   Builder.defineMacro("__" + MacroName + "__");
56 }
57 
58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
59                             bool Tuning = true) {
60   Builder.defineMacro("__" + CPUName);
61   Builder.defineMacro("__" + CPUName + "__");
62   if (Tuning)
63     Builder.defineMacro("__tune_" + CPUName + "__");
64 }
65 
66 //===----------------------------------------------------------------------===//
67 // Defines specific to certain operating systems.
68 //===----------------------------------------------------------------------===//
69 
70 namespace {
71 template<typename TgtInfo>
72 class OSTargetInfo : public TgtInfo {
73 protected:
74   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
75                             MacroBuilder &Builder) const=0;
76 public:
77   OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
78   void getTargetDefines(const LangOptions &Opts,
79                         MacroBuilder &Builder) const override {
80     TgtInfo::getTargetDefines(Opts, Builder);
81     getOSDefines(Opts, TgtInfo::getTriple(), Builder);
82   }
83 
84 };
85 } // end anonymous namespace
86 
87 
88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
89                              const llvm::Triple &Triple,
90                              StringRef &PlatformName,
91                              VersionTuple &PlatformMinVersion) {
92   Builder.defineMacro("__APPLE_CC__", "6000");
93   Builder.defineMacro("__APPLE__");
94   Builder.defineMacro("OBJC_NEW_PROPERTIES");
95   // AddressSanitizer doesn't play well with source fortification, which is on
96   // by default on Darwin.
97   if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98 
99   if (!Opts.ObjCAutoRefCount) {
100     // __weak is always defined, for use in blocks and with objc pointers.
101     Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102 
103     // Darwin defines __strong even in C mode (just to nothing).
104     if (Opts.getGC() != LangOptions::NonGC)
105       Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106     else
107       Builder.defineMacro("__strong", "");
108 
109     // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110     // allow this in C, since one might have block pointers in structs that
111     // are used in pure C code and in Objective-C ARC.
112     Builder.defineMacro("__unsafe_unretained", "");
113   }
114 
115   if (Opts.Static)
116     Builder.defineMacro("__STATIC__");
117   else
118     Builder.defineMacro("__DYNAMIC__");
119 
120   if (Opts.POSIXThreads)
121     Builder.defineMacro("_REENTRANT");
122 
123   // Get the platform type and version number from the triple.
124   unsigned Maj, Min, Rev;
125   if (Triple.isMacOSX()) {
126     Triple.getMacOSXVersion(Maj, Min, Rev);
127     PlatformName = "macosx";
128   } else {
129     Triple.getOSVersion(Maj, Min, Rev);
130     PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131   }
132 
133   // If -target arch-pc-win32-macho option specified, we're
134   // generating code for Win32 ABI. No need to emit
135   // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136   if (PlatformName == "win32") {
137     PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138     return;
139   }
140 
141   // Set the appropriate OS version define.
142   if (Triple.isiOS()) {
143     assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144     char Str[6];
145     Str[0] = '0' + Maj;
146     Str[1] = '0' + (Min / 10);
147     Str[2] = '0' + (Min % 10);
148     Str[3] = '0' + (Rev / 10);
149     Str[4] = '0' + (Rev % 10);
150     Str[5] = '\0';
151     Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
152                         Str);
153   } else if (Triple.isMacOSX()) {
154     // Note that the Driver allows versions which aren't representable in the
155     // define (because we only get a single digit for the minor and micro
156     // revision numbers). So, we limit them to the maximum representable
157     // version.
158     assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159     char Str[7];
160     if (Maj < 10 || (Maj == 10 && Min < 10)) {
161       Str[0] = '0' + (Maj / 10);
162       Str[1] = '0' + (Maj % 10);
163       Str[2] = '0' + std::min(Min, 9U);
164       Str[3] = '0' + std::min(Rev, 9U);
165       Str[4] = '\0';
166     } else {
167       // Handle versions > 10.9.
168       Str[0] = '0' + (Maj / 10);
169       Str[1] = '0' + (Maj % 10);
170       Str[2] = '0' + (Min / 10);
171       Str[3] = '0' + (Min % 10);
172       Str[4] = '0' + (Rev / 10);
173       Str[5] = '0' + (Rev % 10);
174       Str[6] = '\0';
175     }
176     Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
177   }
178 
179   // Tell users about the kernel if there is one.
180   if (Triple.isOSDarwin())
181     Builder.defineMacro("__MACH__");
182 
183   PlatformMinVersion = VersionTuple(Maj, Min, Rev);
184 }
185 
186 namespace {
187 template<typename Target>
188 class DarwinTargetInfo : public OSTargetInfo<Target> {
189 protected:
190   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
191                     MacroBuilder &Builder) const override {
192     getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
193                      this->PlatformMinVersion);
194   }
195 
196 public:
197   DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
198     this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
199     this->MCountName = "\01mcount";
200   }
201 
202   std::string isValidSectionSpecifier(StringRef SR) const override {
203     // Let MCSectionMachO validate this.
204     StringRef Segment, Section;
205     unsigned TAA, StubSize;
206     bool HasTAA;
207     return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
208                                                        TAA, HasTAA, StubSize);
209   }
210 
211   const char *getStaticInitSectionSpecifier() const override {
212     // FIXME: We should return 0 when building kexts.
213     return "__TEXT,__StaticInit,regular,pure_instructions";
214   }
215 
216   /// Darwin does not support protected visibility.  Darwin's "default"
217   /// is very similar to ELF's "protected";  Darwin requires a "weak"
218   /// attribute on declarations that can be dynamically replaced.
219   bool hasProtectedVisibility() const override {
220     return false;
221   }
222 };
223 
224 
225 // DragonFlyBSD Target
226 template<typename Target>
227 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
228 protected:
229   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
230                     MacroBuilder &Builder) const override {
231     // DragonFly defines; list based off of gcc output
232     Builder.defineMacro("__DragonFly__");
233     Builder.defineMacro("__DragonFly_cc_version", "100001");
234     Builder.defineMacro("__ELF__");
235     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
236     Builder.defineMacro("__tune_i386__");
237     DefineStd(Builder, "unix", Opts);
238   }
239 public:
240   DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
241       : OSTargetInfo<Target>(Triple) {
242     this->UserLabelPrefix = "";
243 
244     switch (Triple.getArch()) {
245     default:
246     case llvm::Triple::x86:
247     case llvm::Triple::x86_64:
248       this->MCountName = ".mcount";
249       break;
250     }
251   }
252 };
253 
254 // FreeBSD Target
255 template<typename Target>
256 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
257 protected:
258   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
259                     MacroBuilder &Builder) const override {
260     // FreeBSD defines; list based off of gcc output
261 
262     unsigned Release = Triple.getOSMajorVersion();
263     if (Release == 0U)
264       Release = 8;
265 
266     Builder.defineMacro("__FreeBSD__", Twine(Release));
267     Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
268     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
269     DefineStd(Builder, "unix", Opts);
270     Builder.defineMacro("__ELF__");
271 
272     // On FreeBSD, wchar_t contains the number of the code point as
273     // used by the character set of the locale. These character sets are
274     // not necessarily a superset of ASCII.
275     Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
276   }
277 public:
278   FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
279     this->UserLabelPrefix = "";
280 
281     switch (Triple.getArch()) {
282     default:
283     case llvm::Triple::x86:
284     case llvm::Triple::x86_64:
285       this->MCountName = ".mcount";
286       break;
287     case llvm::Triple::mips:
288     case llvm::Triple::mipsel:
289     case llvm::Triple::ppc:
290     case llvm::Triple::ppc64:
291     case llvm::Triple::ppc64le:
292       this->MCountName = "_mcount";
293       break;
294     case llvm::Triple::arm:
295       this->MCountName = "__mcount";
296       break;
297     }
298   }
299 };
300 
301 // GNU/kFreeBSD Target
302 template<typename Target>
303 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
304 protected:
305   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
306                     MacroBuilder &Builder) const override {
307     // GNU/kFreeBSD defines; list based off of gcc output
308 
309     DefineStd(Builder, "unix", Opts);
310     Builder.defineMacro("__FreeBSD_kernel__");
311     Builder.defineMacro("__GLIBC__");
312     Builder.defineMacro("__ELF__");
313     if (Opts.POSIXThreads)
314       Builder.defineMacro("_REENTRANT");
315     if (Opts.CPlusPlus)
316       Builder.defineMacro("_GNU_SOURCE");
317   }
318 public:
319   KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
320     this->UserLabelPrefix = "";
321   }
322 };
323 
324 // Minix Target
325 template<typename Target>
326 class MinixTargetInfo : public OSTargetInfo<Target> {
327 protected:
328   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
329                     MacroBuilder &Builder) const override {
330     // Minix defines
331 
332     Builder.defineMacro("__minix", "3");
333     Builder.defineMacro("_EM_WSIZE", "4");
334     Builder.defineMacro("_EM_PSIZE", "4");
335     Builder.defineMacro("_EM_SSIZE", "2");
336     Builder.defineMacro("_EM_LSIZE", "4");
337     Builder.defineMacro("_EM_FSIZE", "4");
338     Builder.defineMacro("_EM_DSIZE", "8");
339     Builder.defineMacro("__ELF__");
340     DefineStd(Builder, "unix", Opts);
341   }
342 public:
343   MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
344     this->UserLabelPrefix = "";
345   }
346 };
347 
348 // Linux target
349 template<typename Target>
350 class LinuxTargetInfo : public OSTargetInfo<Target> {
351 protected:
352   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
353                     MacroBuilder &Builder) const override {
354     // Linux defines; list based off of gcc output
355     DefineStd(Builder, "unix", Opts);
356     DefineStd(Builder, "linux", Opts);
357     Builder.defineMacro("__gnu_linux__");
358     Builder.defineMacro("__ELF__");
359     if (Triple.getEnvironment() == llvm::Triple::Android)
360       Builder.defineMacro("__ANDROID__", "1");
361     if (Opts.POSIXThreads)
362       Builder.defineMacro("_REENTRANT");
363     if (Opts.CPlusPlus)
364       Builder.defineMacro("_GNU_SOURCE");
365   }
366 public:
367   LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
368     this->UserLabelPrefix = "";
369     this->WIntType = TargetInfo::UnsignedInt;
370 
371     switch (Triple.getArch()) {
372     default:
373       break;
374     case llvm::Triple::ppc:
375     case llvm::Triple::ppc64:
376     case llvm::Triple::ppc64le:
377       this->MCountName = "_mcount";
378       break;
379     }
380   }
381 
382   const char *getStaticInitSectionSpecifier() const override {
383     return ".text.startup";
384   }
385 };
386 
387 // NetBSD Target
388 template<typename Target>
389 class NetBSDTargetInfo : public OSTargetInfo<Target> {
390 protected:
391   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
392                     MacroBuilder &Builder) const override {
393     // NetBSD defines; list based off of gcc output
394     Builder.defineMacro("__NetBSD__");
395     Builder.defineMacro("__unix__");
396     Builder.defineMacro("__ELF__");
397     if (Opts.POSIXThreads)
398       Builder.defineMacro("_POSIX_THREADS");
399 
400     switch (Triple.getArch()) {
401     default:
402       break;
403     case llvm::Triple::arm:
404     case llvm::Triple::armeb:
405     case llvm::Triple::thumb:
406     case llvm::Triple::thumbeb:
407       Builder.defineMacro("__ARM_DWARF_EH__");
408       break;
409     }
410   }
411 public:
412   NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
413     this->UserLabelPrefix = "";
414   }
415 };
416 
417 // OpenBSD Target
418 template<typename Target>
419 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
420 protected:
421   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
422                     MacroBuilder &Builder) const override {
423     // OpenBSD defines; list based off of gcc output
424 
425     Builder.defineMacro("__OpenBSD__");
426     DefineStd(Builder, "unix", Opts);
427     Builder.defineMacro("__ELF__");
428     if (Opts.POSIXThreads)
429       Builder.defineMacro("_REENTRANT");
430   }
431 public:
432   OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
433     this->UserLabelPrefix = "";
434     this->TLSSupported = false;
435 
436       switch (Triple.getArch()) {
437         default:
438         case llvm::Triple::x86:
439         case llvm::Triple::x86_64:
440         case llvm::Triple::arm:
441         case llvm::Triple::sparc:
442           this->MCountName = "__mcount";
443           break;
444         case llvm::Triple::mips64:
445         case llvm::Triple::mips64el:
446         case llvm::Triple::ppc:
447         case llvm::Triple::sparcv9:
448           this->MCountName = "_mcount";
449           break;
450       }
451   }
452 };
453 
454 // Bitrig Target
455 template<typename Target>
456 class BitrigTargetInfo : public OSTargetInfo<Target> {
457 protected:
458   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
459                     MacroBuilder &Builder) const override {
460     // Bitrig defines; list based off of gcc output
461 
462     Builder.defineMacro("__Bitrig__");
463     DefineStd(Builder, "unix", Opts);
464     Builder.defineMacro("__ELF__");
465     if (Opts.POSIXThreads)
466       Builder.defineMacro("_REENTRANT");
467   }
468 public:
469   BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
470     this->UserLabelPrefix = "";
471     this->MCountName = "__mcount";
472   }
473 };
474 
475 // PSP Target
476 template<typename Target>
477 class PSPTargetInfo : public OSTargetInfo<Target> {
478 protected:
479   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
480                     MacroBuilder &Builder) const override {
481     // PSP defines; list based on the output of the pspdev gcc toolchain.
482     Builder.defineMacro("PSP");
483     Builder.defineMacro("_PSP");
484     Builder.defineMacro("__psp__");
485     Builder.defineMacro("__ELF__");
486   }
487 public:
488   PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
489     this->UserLabelPrefix = "";
490   }
491 };
492 
493 // PS3 PPU Target
494 template<typename Target>
495 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
496 protected:
497   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
498                     MacroBuilder &Builder) const override {
499     // PS3 PPU defines.
500     Builder.defineMacro("__PPC__");
501     Builder.defineMacro("__PPU__");
502     Builder.defineMacro("__CELLOS_LV2__");
503     Builder.defineMacro("__ELF__");
504     Builder.defineMacro("__LP32__");
505     Builder.defineMacro("_ARCH_PPC64");
506     Builder.defineMacro("__powerpc64__");
507   }
508 public:
509   PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
510     this->UserLabelPrefix = "";
511     this->LongWidth = this->LongAlign = 32;
512     this->PointerWidth = this->PointerAlign = 32;
513     this->IntMaxType = TargetInfo::SignedLongLong;
514     this->Int64Type = TargetInfo::SignedLongLong;
515     this->SizeType = TargetInfo::UnsignedInt;
516     this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
517   }
518 };
519 
520 // Solaris target
521 template<typename Target>
522 class SolarisTargetInfo : public OSTargetInfo<Target> {
523 protected:
524   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
525                     MacroBuilder &Builder) const override {
526     DefineStd(Builder, "sun", Opts);
527     DefineStd(Builder, "unix", Opts);
528     Builder.defineMacro("__ELF__");
529     Builder.defineMacro("__svr4__");
530     Builder.defineMacro("__SVR4");
531     // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
532     // newer, but to 500 for everything else.  feature_test.h has a check to
533     // ensure that you are not using C99 with an old version of X/Open or C89
534     // with a new version.
535     if (Opts.C99 || Opts.C11)
536       Builder.defineMacro("_XOPEN_SOURCE", "600");
537     else
538       Builder.defineMacro("_XOPEN_SOURCE", "500");
539     if (Opts.CPlusPlus)
540       Builder.defineMacro("__C99FEATURES__");
541     Builder.defineMacro("_LARGEFILE_SOURCE");
542     Builder.defineMacro("_LARGEFILE64_SOURCE");
543     Builder.defineMacro("__EXTENSIONS__");
544     Builder.defineMacro("_REENTRANT");
545   }
546 public:
547   SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
548     this->UserLabelPrefix = "";
549     this->WCharType = this->SignedInt;
550     // FIXME: WIntType should be SignedLong
551   }
552 };
553 
554 // Windows target
555 template<typename Target>
556 class WindowsTargetInfo : public OSTargetInfo<Target> {
557 protected:
558   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
559                     MacroBuilder &Builder) const override {
560     Builder.defineMacro("_WIN32");
561   }
562   void getVisualStudioDefines(const LangOptions &Opts,
563                               MacroBuilder &Builder) const {
564     if (Opts.CPlusPlus) {
565       if (Opts.RTTIData)
566         Builder.defineMacro("_CPPRTTI");
567 
568       if (Opts.Exceptions)
569         Builder.defineMacro("_CPPUNWIND");
570     }
571 
572     if (!Opts.CharIsSigned)
573       Builder.defineMacro("_CHAR_UNSIGNED");
574 
575     // FIXME: POSIXThreads isn't exactly the option this should be defined for,
576     //        but it works for now.
577     if (Opts.POSIXThreads)
578       Builder.defineMacro("_MT");
579 
580     if (Opts.MSCompatibilityVersion) {
581       Builder.defineMacro("_MSC_VER",
582                           Twine(Opts.MSCompatibilityVersion / 100000));
583       Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
584       // FIXME We cannot encode the revision information into 32-bits
585       Builder.defineMacro("_MSC_BUILD", Twine(1));
586     }
587 
588     if (Opts.MicrosoftExt) {
589       Builder.defineMacro("_MSC_EXTENSIONS");
590 
591       if (Opts.CPlusPlus11) {
592         Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
593         Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
594         Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
595       }
596     }
597 
598     Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
599   }
600 
601 public:
602   WindowsTargetInfo(const llvm::Triple &Triple)
603       : OSTargetInfo<Target>(Triple) {}
604 };
605 
606 template <typename Target>
607 class NaClTargetInfo : public OSTargetInfo<Target> {
608 protected:
609   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
610                     MacroBuilder &Builder) const override {
611     if (Opts.POSIXThreads)
612       Builder.defineMacro("_REENTRANT");
613     if (Opts.CPlusPlus)
614       Builder.defineMacro("_GNU_SOURCE");
615 
616     DefineStd(Builder, "unix", Opts);
617     Builder.defineMacro("__ELF__");
618     Builder.defineMacro("__native_client__");
619   }
620 
621 public:
622   NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
623     this->UserLabelPrefix = "";
624     this->LongAlign = 32;
625     this->LongWidth = 32;
626     this->PointerAlign = 32;
627     this->PointerWidth = 32;
628     this->IntMaxType = TargetInfo::SignedLongLong;
629     this->Int64Type = TargetInfo::SignedLongLong;
630     this->DoubleAlign = 64;
631     this->LongDoubleWidth = 64;
632     this->LongDoubleAlign = 64;
633     this->LongLongWidth = 64;
634     this->LongLongAlign = 64;
635     this->SizeType = TargetInfo::UnsignedInt;
636     this->PtrDiffType = TargetInfo::SignedInt;
637     this->IntPtrType = TargetInfo::SignedInt;
638     // RegParmMax is inherited from the underlying architecture
639     this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
640     if (Triple.getArch() == llvm::Triple::arm) {
641       this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
642     } else if (Triple.getArch() == llvm::Triple::x86) {
643       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
644     } else if (Triple.getArch() == llvm::Triple::x86_64) {
645       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
646     } else if (Triple.getArch() == llvm::Triple::mipsel) {
647       // Handled on mips' setDescriptionString.
648     } else {
649       assert(Triple.getArch() == llvm::Triple::le32);
650       this->DescriptionString = "e-p:32:32-i64:64";
651     }
652   }
653   typename Target::CallingConvCheckResult checkCallingConvention(
654       CallingConv CC) const override {
655     return CC == CC_PnaclCall ? Target::CCCR_OK :
656         Target::checkCallingConvention(CC);
657   }
658 };
659 } // end anonymous namespace.
660 
661 //===----------------------------------------------------------------------===//
662 // Specific target implementations.
663 //===----------------------------------------------------------------------===//
664 
665 namespace {
666 // PPC abstract base class
667 class PPCTargetInfo : public TargetInfo {
668   static const Builtin::Info BuiltinInfo[];
669   static const char * const GCCRegNames[];
670   static const TargetInfo::GCCRegAlias GCCRegAliases[];
671   std::string CPU;
672 
673   // Target cpu features.
674   bool HasVSX;
675   bool HasP8Vector;
676 
677 protected:
678   std::string ABI;
679 
680 public:
681   PPCTargetInfo(const llvm::Triple &Triple)
682     : TargetInfo(Triple), HasVSX(false), HasP8Vector(false) {
683     BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
684     LongDoubleWidth = LongDoubleAlign = 128;
685     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
686   }
687 
688   /// \brief Flags for architecture specific defines.
689   typedef enum {
690     ArchDefineNone  = 0,
691     ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
692     ArchDefinePpcgr = 1 << 1,
693     ArchDefinePpcsq = 1 << 2,
694     ArchDefine440   = 1 << 3,
695     ArchDefine603   = 1 << 4,
696     ArchDefine604   = 1 << 5,
697     ArchDefinePwr4  = 1 << 6,
698     ArchDefinePwr5  = 1 << 7,
699     ArchDefinePwr5x = 1 << 8,
700     ArchDefinePwr6  = 1 << 9,
701     ArchDefinePwr6x = 1 << 10,
702     ArchDefinePwr7  = 1 << 11,
703     ArchDefinePwr8  = 1 << 12,
704     ArchDefineA2    = 1 << 13,
705     ArchDefineA2q   = 1 << 14
706   } ArchDefineTypes;
707 
708   // Note: GCC recognizes the following additional cpus:
709   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
710   //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
711   //  titan, rs64.
712   bool setCPU(const std::string &Name) override {
713     bool CPUKnown = llvm::StringSwitch<bool>(Name)
714       .Case("generic", true)
715       .Case("440", true)
716       .Case("450", true)
717       .Case("601", true)
718       .Case("602", true)
719       .Case("603", true)
720       .Case("603e", true)
721       .Case("603ev", true)
722       .Case("604", true)
723       .Case("604e", true)
724       .Case("620", true)
725       .Case("630", true)
726       .Case("g3", true)
727       .Case("7400", true)
728       .Case("g4", true)
729       .Case("7450", true)
730       .Case("g4+", true)
731       .Case("750", true)
732       .Case("970", true)
733       .Case("g5", true)
734       .Case("a2", true)
735       .Case("a2q", true)
736       .Case("e500mc", true)
737       .Case("e5500", true)
738       .Case("power3", true)
739       .Case("pwr3", true)
740       .Case("power4", true)
741       .Case("pwr4", true)
742       .Case("power5", true)
743       .Case("pwr5", true)
744       .Case("power5x", true)
745       .Case("pwr5x", true)
746       .Case("power6", true)
747       .Case("pwr6", true)
748       .Case("power6x", true)
749       .Case("pwr6x", true)
750       .Case("power7", true)
751       .Case("pwr7", true)
752       .Case("power8", true)
753       .Case("pwr8", true)
754       .Case("powerpc", true)
755       .Case("ppc", true)
756       .Case("powerpc64", true)
757       .Case("ppc64", true)
758       .Case("powerpc64le", true)
759       .Case("ppc64le", true)
760       .Default(false);
761 
762     if (CPUKnown)
763       CPU = Name;
764 
765     return CPUKnown;
766   }
767 
768 
769   StringRef getABI() const override { return ABI; }
770 
771   void getTargetBuiltins(const Builtin::Info *&Records,
772                          unsigned &NumRecords) const override {
773     Records = BuiltinInfo;
774     NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
775   }
776 
777   bool isCLZForZeroUndef() const override { return false; }
778 
779   void getTargetDefines(const LangOptions &Opts,
780                         MacroBuilder &Builder) const override;
781 
782   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
783 
784   bool handleTargetFeatures(std::vector<std::string> &Features,
785                             DiagnosticsEngine &Diags) override;
786   bool hasFeature(StringRef Feature) const override;
787 
788   void getGCCRegNames(const char * const *&Names,
789                       unsigned &NumNames) const override;
790   void getGCCRegAliases(const GCCRegAlias *&Aliases,
791                         unsigned &NumAliases) const override;
792   bool validateAsmConstraint(const char *&Name,
793                              TargetInfo::ConstraintInfo &Info) const override {
794     switch (*Name) {
795     default: return false;
796     case 'O': // Zero
797       break;
798     case 'b': // Base register
799     case 'f': // Floating point register
800       Info.setAllowsRegister();
801       break;
802     // FIXME: The following are added to allow parsing.
803     // I just took a guess at what the actions should be.
804     // Also, is more specific checking needed?  I.e. specific registers?
805     case 'd': // Floating point register (containing 64-bit value)
806     case 'v': // Altivec vector register
807       Info.setAllowsRegister();
808       break;
809     case 'w':
810       switch (Name[1]) {
811         case 'd':// VSX vector register to hold vector double data
812         case 'f':// VSX vector register to hold vector float data
813         case 's':// VSX vector register to hold scalar float data
814         case 'a':// Any VSX register
815         case 'c':// An individual CR bit
816           break;
817         default:
818           return false;
819       }
820       Info.setAllowsRegister();
821       Name++; // Skip over 'w'.
822       break;
823     case 'h': // `MQ', `CTR', or `LINK' register
824     case 'q': // `MQ' register
825     case 'c': // `CTR' register
826     case 'l': // `LINK' register
827     case 'x': // `CR' register (condition register) number 0
828     case 'y': // `CR' register (condition register)
829     case 'z': // `XER[CA]' carry bit (part of the XER register)
830       Info.setAllowsRegister();
831       break;
832     case 'I': // Signed 16-bit constant
833     case 'J': // Unsigned 16-bit constant shifted left 16 bits
834               //  (use `L' instead for SImode constants)
835     case 'K': // Unsigned 16-bit constant
836     case 'L': // Signed 16-bit constant shifted left 16 bits
837     case 'M': // Constant larger than 31
838     case 'N': // Exact power of 2
839     case 'P': // Constant whose negation is a signed 16-bit constant
840     case 'G': // Floating point constant that can be loaded into a
841               // register with one instruction per word
842     case 'H': // Integer/Floating point constant that can be loaded
843               // into a register using three instructions
844       break;
845     case 'm': // Memory operand. Note that on PowerPC targets, m can
846               // include addresses that update the base register. It
847               // is therefore only safe to use `m' in an asm statement
848               // if that asm statement accesses the operand exactly once.
849               // The asm statement must also use `%U<opno>' as a
850               // placeholder for the "update" flag in the corresponding
851               // load or store instruction. For example:
852               // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
853               // is correct but:
854               // asm ("st %1,%0" : "=m" (mem) : "r" (val));
855               // is not. Use es rather than m if you don't want the base
856               // register to be updated.
857     case 'e':
858       if (Name[1] != 's')
859           return false;
860               // es: A "stable" memory operand; that is, one which does not
861               // include any automodification of the base register. Unlike
862               // `m', this constraint can be used in asm statements that
863               // might access the operand several times, or that might not
864               // access it at all.
865       Info.setAllowsMemory();
866       Name++; // Skip over 'e'.
867       break;
868     case 'Q': // Memory operand that is an offset from a register (it is
869               // usually better to use `m' or `es' in asm statements)
870     case 'Z': // Memory operand that is an indexed or indirect from a
871               // register (it is usually better to use `m' or `es' in
872               // asm statements)
873       Info.setAllowsMemory();
874       Info.setAllowsRegister();
875       break;
876     case 'R': // AIX TOC entry
877     case 'a': // Address operand that is an indexed or indirect from a
878               // register (`p' is preferable for asm statements)
879     case 'S': // Constant suitable as a 64-bit mask operand
880     case 'T': // Constant suitable as a 32-bit mask operand
881     case 'U': // System V Release 4 small data area reference
882     case 't': // AND masks that can be performed by two rldic{l, r}
883               // instructions
884     case 'W': // Vector constant that does not require memory
885     case 'j': // Vector constant that is all zeros.
886       break;
887     // End FIXME.
888     }
889     return true;
890   }
891   std::string convertConstraint(const char *&Constraint) const override {
892     std::string R;
893     switch (*Constraint) {
894     case 'e':
895     case 'w':
896       // Two-character constraint; add "^" hint for later parsing.
897       R = std::string("^") + std::string(Constraint, 2);
898       Constraint++;
899       break;
900     default:
901       return TargetInfo::convertConstraint(Constraint);
902     }
903     return R;
904   }
905   const char *getClobbers() const override {
906     return "";
907   }
908   int getEHDataRegisterNumber(unsigned RegNo) const override {
909     if (RegNo == 0) return 3;
910     if (RegNo == 1) return 4;
911     return -1;
912   }
913 };
914 
915 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
916 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
917 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
918                                               ALL_LANGUAGES },
919 #include "clang/Basic/BuiltinsPPC.def"
920 };
921 
922   /// handleTargetFeatures - Perform initialization based on the user
923 /// configured set of features.
924 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
925                                          DiagnosticsEngine &Diags) {
926   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
927     // Ignore disabled features.
928     if (Features[i][0] == '-')
929       continue;
930 
931     StringRef Feature = StringRef(Features[i]).substr(1);
932 
933     if (Feature == "vsx") {
934       HasVSX = true;
935       continue;
936     }
937 
938     if (Feature == "power8-vector") {
939       HasP8Vector = true;
940       continue;
941     }
942 
943     // TODO: Finish this list and add an assert that we've handled them
944     // all.
945   }
946 
947   return true;
948 }
949 
950 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
951 /// #defines that are not tied to a specific subtarget.
952 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
953                                      MacroBuilder &Builder) const {
954   // Target identification.
955   Builder.defineMacro("__ppc__");
956   Builder.defineMacro("__PPC__");
957   Builder.defineMacro("_ARCH_PPC");
958   Builder.defineMacro("__powerpc__");
959   Builder.defineMacro("__POWERPC__");
960   if (PointerWidth == 64) {
961     Builder.defineMacro("_ARCH_PPC64");
962     Builder.defineMacro("__powerpc64__");
963     Builder.defineMacro("__ppc64__");
964     Builder.defineMacro("__PPC64__");
965   }
966 
967   // Target properties.
968   if (getTriple().getArch() == llvm::Triple::ppc64le) {
969     Builder.defineMacro("_LITTLE_ENDIAN");
970   } else {
971     if (getTriple().getOS() != llvm::Triple::NetBSD &&
972         getTriple().getOS() != llvm::Triple::OpenBSD)
973       Builder.defineMacro("_BIG_ENDIAN");
974   }
975 
976   // ABI options.
977   if (ABI == "elfv1")
978     Builder.defineMacro("_CALL_ELF", "1");
979   if (ABI == "elfv2")
980     Builder.defineMacro("_CALL_ELF", "2");
981 
982   // Subtarget options.
983   Builder.defineMacro("__NATURAL_ALIGNMENT__");
984   Builder.defineMacro("__REGISTER_PREFIX__", "");
985 
986   // FIXME: Should be controlled by command line option.
987   if (LongDoubleWidth == 128)
988     Builder.defineMacro("__LONG_DOUBLE_128__");
989 
990   if (Opts.AltiVec) {
991     Builder.defineMacro("__VEC__", "10206");
992     Builder.defineMacro("__ALTIVEC__");
993   }
994 
995   // CPU identification.
996   ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
997     .Case("440",   ArchDefineName)
998     .Case("450",   ArchDefineName | ArchDefine440)
999     .Case("601",   ArchDefineName)
1000     .Case("602",   ArchDefineName | ArchDefinePpcgr)
1001     .Case("603",   ArchDefineName | ArchDefinePpcgr)
1002     .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1003     .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1004     .Case("604",   ArchDefineName | ArchDefinePpcgr)
1005     .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1006     .Case("620",   ArchDefineName | ArchDefinePpcgr)
1007     .Case("630",   ArchDefineName | ArchDefinePpcgr)
1008     .Case("7400",  ArchDefineName | ArchDefinePpcgr)
1009     .Case("7450",  ArchDefineName | ArchDefinePpcgr)
1010     .Case("750",   ArchDefineName | ArchDefinePpcgr)
1011     .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1012                      | ArchDefinePpcsq)
1013     .Case("a2",    ArchDefineA2)
1014     .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1015     .Case("pwr3",  ArchDefinePpcgr)
1016     .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1017     .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1018                      | ArchDefinePpcsq)
1019     .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1020                      | ArchDefinePpcgr | ArchDefinePpcsq)
1021     .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1022                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1023     .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1024                      | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1025                      | ArchDefinePpcsq)
1026     .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1027                      | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1028                      | ArchDefinePpcgr | ArchDefinePpcsq)
1029     .Case("pwr8",  ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1030                      | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1031                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1032     .Case("power3",  ArchDefinePpcgr)
1033     .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1034     .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1035                        | ArchDefinePpcsq)
1036     .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1037                        | ArchDefinePpcgr | ArchDefinePpcsq)
1038     .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1039                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1040     .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1041                        | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1042                        | ArchDefinePpcsq)
1043     .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1044                        | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1045                        | ArchDefinePpcgr | ArchDefinePpcsq)
1046     .Case("power8",  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1047                        | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1048                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1049     .Default(ArchDefineNone);
1050 
1051   if (defs & ArchDefineName)
1052     Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1053   if (defs & ArchDefinePpcgr)
1054     Builder.defineMacro("_ARCH_PPCGR");
1055   if (defs & ArchDefinePpcsq)
1056     Builder.defineMacro("_ARCH_PPCSQ");
1057   if (defs & ArchDefine440)
1058     Builder.defineMacro("_ARCH_440");
1059   if (defs & ArchDefine603)
1060     Builder.defineMacro("_ARCH_603");
1061   if (defs & ArchDefine604)
1062     Builder.defineMacro("_ARCH_604");
1063   if (defs & ArchDefinePwr4)
1064     Builder.defineMacro("_ARCH_PWR4");
1065   if (defs & ArchDefinePwr5)
1066     Builder.defineMacro("_ARCH_PWR5");
1067   if (defs & ArchDefinePwr5x)
1068     Builder.defineMacro("_ARCH_PWR5X");
1069   if (defs & ArchDefinePwr6)
1070     Builder.defineMacro("_ARCH_PWR6");
1071   if (defs & ArchDefinePwr6x)
1072     Builder.defineMacro("_ARCH_PWR6X");
1073   if (defs & ArchDefinePwr7)
1074     Builder.defineMacro("_ARCH_PWR7");
1075   if (defs & ArchDefinePwr8)
1076     Builder.defineMacro("_ARCH_PWR8");
1077   if (defs & ArchDefineA2)
1078     Builder.defineMacro("_ARCH_A2");
1079   if (defs & ArchDefineA2q) {
1080     Builder.defineMacro("_ARCH_A2Q");
1081     Builder.defineMacro("_ARCH_QP");
1082   }
1083 
1084   if (getTriple().getVendor() == llvm::Triple::BGQ) {
1085     Builder.defineMacro("__bg__");
1086     Builder.defineMacro("__THW_BLUEGENE__");
1087     Builder.defineMacro("__bgq__");
1088     Builder.defineMacro("__TOS_BGQ__");
1089   }
1090 
1091   if (HasVSX)
1092     Builder.defineMacro("__VSX__");
1093   if (HasP8Vector)
1094     Builder.defineMacro("__POWER8_VECTOR__");
1095 
1096   // FIXME: The following are not yet generated here by Clang, but are
1097   //        generated by GCC:
1098   //
1099   //   _SOFT_FLOAT_
1100   //   __RECIP_PRECISION__
1101   //   __APPLE_ALTIVEC__
1102   //   __RECIP__
1103   //   __RECIPF__
1104   //   __RSQRTE__
1105   //   __RSQRTEF__
1106   //   _SOFT_DOUBLE_
1107   //   __NO_LWSYNC__
1108   //   __HAVE_BSWAP__
1109   //   __LONGDOUBLE128
1110   //   __CMODEL_MEDIUM__
1111   //   __CMODEL_LARGE__
1112   //   _CALL_SYSV
1113   //   _CALL_DARWIN
1114   //   __NO_FPRS__
1115 }
1116 
1117 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1118   Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1119     .Case("7400", true)
1120     .Case("g4", true)
1121     .Case("7450", true)
1122     .Case("g4+", true)
1123     .Case("970", true)
1124     .Case("g5", true)
1125     .Case("pwr6", true)
1126     .Case("pwr7", true)
1127     .Case("pwr8", true)
1128     .Case("ppc64", true)
1129     .Case("ppc64le", true)
1130     .Default(false);
1131 
1132   Features["qpx"] = (CPU == "a2q");
1133 
1134   if (!ABI.empty())
1135     Features[ABI] = true;
1136 }
1137 
1138 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1139   return Feature == "powerpc";
1140 }
1141 
1142 
1143 const char * const PPCTargetInfo::GCCRegNames[] = {
1144   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1145   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1146   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1147   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1148   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1149   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1150   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1151   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1152   "mq", "lr", "ctr", "ap",
1153   "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1154   "xer",
1155   "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1156   "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1157   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1158   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1159   "vrsave", "vscr",
1160   "spe_acc", "spefscr",
1161   "sfp"
1162 };
1163 
1164 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1165                                    unsigned &NumNames) const {
1166   Names = GCCRegNames;
1167   NumNames = llvm::array_lengthof(GCCRegNames);
1168 }
1169 
1170 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1171   // While some of these aliases do map to different registers
1172   // they still share the same register name.
1173   { { "0" }, "r0" },
1174   { { "1"}, "r1" },
1175   { { "2" }, "r2" },
1176   { { "3" }, "r3" },
1177   { { "4" }, "r4" },
1178   { { "5" }, "r5" },
1179   { { "6" }, "r6" },
1180   { { "7" }, "r7" },
1181   { { "8" }, "r8" },
1182   { { "9" }, "r9" },
1183   { { "10" }, "r10" },
1184   { { "11" }, "r11" },
1185   { { "12" }, "r12" },
1186   { { "13" }, "r13" },
1187   { { "14" }, "r14" },
1188   { { "15" }, "r15" },
1189   { { "16" }, "r16" },
1190   { { "17" }, "r17" },
1191   { { "18" }, "r18" },
1192   { { "19" }, "r19" },
1193   { { "20" }, "r20" },
1194   { { "21" }, "r21" },
1195   { { "22" }, "r22" },
1196   { { "23" }, "r23" },
1197   { { "24" }, "r24" },
1198   { { "25" }, "r25" },
1199   { { "26" }, "r26" },
1200   { { "27" }, "r27" },
1201   { { "28" }, "r28" },
1202   { { "29" }, "r29" },
1203   { { "30" }, "r30" },
1204   { { "31" }, "r31" },
1205   { { "fr0" }, "f0" },
1206   { { "fr1" }, "f1" },
1207   { { "fr2" }, "f2" },
1208   { { "fr3" }, "f3" },
1209   { { "fr4" }, "f4" },
1210   { { "fr5" }, "f5" },
1211   { { "fr6" }, "f6" },
1212   { { "fr7" }, "f7" },
1213   { { "fr8" }, "f8" },
1214   { { "fr9" }, "f9" },
1215   { { "fr10" }, "f10" },
1216   { { "fr11" }, "f11" },
1217   { { "fr12" }, "f12" },
1218   { { "fr13" }, "f13" },
1219   { { "fr14" }, "f14" },
1220   { { "fr15" }, "f15" },
1221   { { "fr16" }, "f16" },
1222   { { "fr17" }, "f17" },
1223   { { "fr18" }, "f18" },
1224   { { "fr19" }, "f19" },
1225   { { "fr20" }, "f20" },
1226   { { "fr21" }, "f21" },
1227   { { "fr22" }, "f22" },
1228   { { "fr23" }, "f23" },
1229   { { "fr24" }, "f24" },
1230   { { "fr25" }, "f25" },
1231   { { "fr26" }, "f26" },
1232   { { "fr27" }, "f27" },
1233   { { "fr28" }, "f28" },
1234   { { "fr29" }, "f29" },
1235   { { "fr30" }, "f30" },
1236   { { "fr31" }, "f31" },
1237   { { "cc" }, "cr0" },
1238 };
1239 
1240 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1241                                      unsigned &NumAliases) const {
1242   Aliases = GCCRegAliases;
1243   NumAliases = llvm::array_lengthof(GCCRegAliases);
1244 }
1245 } // end anonymous namespace.
1246 
1247 namespace {
1248 class PPC32TargetInfo : public PPCTargetInfo {
1249 public:
1250   PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1251     DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1252 
1253     switch (getTriple().getOS()) {
1254     case llvm::Triple::Linux:
1255     case llvm::Triple::FreeBSD:
1256     case llvm::Triple::NetBSD:
1257       SizeType = UnsignedInt;
1258       PtrDiffType = SignedInt;
1259       IntPtrType = SignedInt;
1260       break;
1261     default:
1262       break;
1263     }
1264 
1265     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1266       LongDoubleWidth = LongDoubleAlign = 64;
1267       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1268     }
1269 
1270     // PPC32 supports atomics up to 4 bytes.
1271     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1272   }
1273 
1274   BuiltinVaListKind getBuiltinVaListKind() const override {
1275     // This is the ELF definition, and is overridden by the Darwin sub-target
1276     return TargetInfo::PowerABIBuiltinVaList;
1277   }
1278 };
1279 } // end anonymous namespace.
1280 
1281 // Note: ABI differences may eventually require us to have a separate
1282 // TargetInfo for little endian.
1283 namespace {
1284 class PPC64TargetInfo : public PPCTargetInfo {
1285 public:
1286   PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1287     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1288     IntMaxType = SignedLong;
1289     Int64Type = SignedLong;
1290 
1291     if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1292       DescriptionString = "e-m:e-i64:64-n32:64";
1293       ABI = "elfv2";
1294     } else {
1295       DescriptionString = "E-m:e-i64:64-n32:64";
1296       ABI = "elfv1";
1297     }
1298 
1299     switch (getTriple().getOS()) {
1300     case llvm::Triple::FreeBSD:
1301       LongDoubleWidth = LongDoubleAlign = 64;
1302       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1303       break;
1304     case llvm::Triple::NetBSD:
1305       IntMaxType = SignedLongLong;
1306       Int64Type = SignedLongLong;
1307       break;
1308     default:
1309       break;
1310     }
1311 
1312     // PPC64 supports atomics up to 8 bytes.
1313     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1314   }
1315   BuiltinVaListKind getBuiltinVaListKind() const override {
1316     return TargetInfo::CharPtrBuiltinVaList;
1317   }
1318   // PPC64 Linux-specifc ABI options.
1319   bool setABI(const std::string &Name) override {
1320     if (Name == "elfv1" || Name == "elfv2") {
1321       ABI = Name;
1322       return true;
1323     }
1324     return false;
1325   }
1326 };
1327 } // end anonymous namespace.
1328 
1329 
1330 namespace {
1331 class DarwinPPC32TargetInfo :
1332   public DarwinTargetInfo<PPC32TargetInfo> {
1333 public:
1334   DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1335       : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1336     HasAlignMac68kSupport = true;
1337     BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1338     PtrDiffType = SignedInt;    // for http://llvm.org/bugs/show_bug.cgi?id=15726
1339     LongLongAlign = 32;
1340     SuitableAlign = 128;
1341     DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1342   }
1343   BuiltinVaListKind getBuiltinVaListKind() const override {
1344     return TargetInfo::CharPtrBuiltinVaList;
1345   }
1346 };
1347 
1348 class DarwinPPC64TargetInfo :
1349   public DarwinTargetInfo<PPC64TargetInfo> {
1350 public:
1351   DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1352       : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1353     HasAlignMac68kSupport = true;
1354     SuitableAlign = 128;
1355     DescriptionString = "E-m:o-i64:64-n32:64";
1356   }
1357 };
1358 } // end anonymous namespace.
1359 
1360 namespace {
1361   static const unsigned NVPTXAddrSpaceMap[] = {
1362     1,    // opencl_global
1363     3,    // opencl_local
1364     4,    // opencl_constant
1365     1,    // cuda_device
1366     4,    // cuda_constant
1367     3,    // cuda_shared
1368   };
1369   class NVPTXTargetInfo : public TargetInfo {
1370     static const char * const GCCRegNames[];
1371     static const Builtin::Info BuiltinInfo[];
1372   public:
1373     NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1374       BigEndian = false;
1375       TLSSupported = false;
1376       LongWidth = LongAlign = 64;
1377       AddrSpaceMap = &NVPTXAddrSpaceMap;
1378       UseAddrSpaceMapMangling = true;
1379       // Define available target features
1380       // These must be defined in sorted order!
1381       NoAsmVariants = true;
1382     }
1383     void getTargetDefines(const LangOptions &Opts,
1384                           MacroBuilder &Builder) const override {
1385       Builder.defineMacro("__PTX__");
1386       Builder.defineMacro("__NVPTX__");
1387     }
1388     void getTargetBuiltins(const Builtin::Info *&Records,
1389                            unsigned &NumRecords) const override {
1390       Records = BuiltinInfo;
1391       NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1392     }
1393     bool hasFeature(StringRef Feature) const override {
1394       return Feature == "ptx" || Feature == "nvptx";
1395     }
1396 
1397     void getGCCRegNames(const char * const *&Names,
1398                         unsigned &NumNames) const override;
1399     void getGCCRegAliases(const GCCRegAlias *&Aliases,
1400                                   unsigned &NumAliases) const override {
1401       // No aliases.
1402       Aliases = nullptr;
1403       NumAliases = 0;
1404     }
1405     bool validateAsmConstraint(const char *&Name,
1406                                TargetInfo::ConstraintInfo &Info) const override {
1407       switch (*Name) {
1408       default: return false;
1409       case 'c':
1410       case 'h':
1411       case 'r':
1412       case 'l':
1413       case 'f':
1414       case 'd':
1415         Info.setAllowsRegister();
1416         return true;
1417       }
1418     }
1419     const char *getClobbers() const override {
1420       // FIXME: Is this really right?
1421       return "";
1422     }
1423     BuiltinVaListKind getBuiltinVaListKind() const override {
1424       // FIXME: implement
1425       return TargetInfo::CharPtrBuiltinVaList;
1426     }
1427     bool setCPU(const std::string &Name) override {
1428       bool Valid = llvm::StringSwitch<bool>(Name)
1429         .Case("sm_20", true)
1430         .Case("sm_21", true)
1431         .Case("sm_30", true)
1432         .Case("sm_35", true)
1433         .Default(false);
1434 
1435       return Valid;
1436     }
1437   };
1438 
1439   const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1440 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1441 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1442                                               ALL_LANGUAGES },
1443 #include "clang/Basic/BuiltinsNVPTX.def"
1444   };
1445 
1446   const char * const NVPTXTargetInfo::GCCRegNames[] = {
1447     "r0"
1448   };
1449 
1450   void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1451                                      unsigned &NumNames) const {
1452     Names = GCCRegNames;
1453     NumNames = llvm::array_lengthof(GCCRegNames);
1454   }
1455 
1456   class NVPTX32TargetInfo : public NVPTXTargetInfo {
1457   public:
1458     NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1459       PointerWidth = PointerAlign = 32;
1460       SizeType     = PtrDiffType = TargetInfo::UnsignedInt;
1461       IntPtrType = TargetInfo::SignedInt;
1462       DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1463   }
1464   };
1465 
1466   class NVPTX64TargetInfo : public NVPTXTargetInfo {
1467   public:
1468     NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1469       PointerWidth = PointerAlign = 64;
1470       SizeType     = PtrDiffType = TargetInfo::UnsignedLongLong;
1471       IntPtrType = TargetInfo::SignedLongLong;
1472       DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1473   }
1474   };
1475 }
1476 
1477 namespace {
1478 
1479 static const unsigned R600AddrSpaceMap[] = {
1480   1,    // opencl_global
1481   3,    // opencl_local
1482   2,    // opencl_constant
1483   1,    // cuda_device
1484   2,    // cuda_constant
1485   3     // cuda_shared
1486 };
1487 
1488 // If you edit the description strings, make sure you update
1489 // getPointerWidthV().
1490 
1491 static const char *DescriptionStringR600 =
1492   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1493   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1494 
1495 static const char *DescriptionStringR600DoubleOps =
1496   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1497   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1498 
1499 static const char *DescriptionStringSI =
1500   "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1501   "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1502   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1503 
1504 class R600TargetInfo : public TargetInfo {
1505   static const Builtin::Info BuiltinInfo[];
1506 
1507   /// \brief The GPU profiles supported by the R600 target.
1508   enum GPUKind {
1509     GK_NONE,
1510     GK_R600,
1511     GK_R600_DOUBLE_OPS,
1512     GK_R700,
1513     GK_R700_DOUBLE_OPS,
1514     GK_EVERGREEN,
1515     GK_EVERGREEN_DOUBLE_OPS,
1516     GK_NORTHERN_ISLANDS,
1517     GK_CAYMAN,
1518     GK_SOUTHERN_ISLANDS,
1519     GK_SEA_ISLANDS
1520   } GPU;
1521 
1522 public:
1523   R600TargetInfo(const llvm::Triple &Triple)
1524       : TargetInfo(Triple), GPU(GK_R600) {
1525     DescriptionString = DescriptionStringR600;
1526     AddrSpaceMap = &R600AddrSpaceMap;
1527     UseAddrSpaceMapMangling = true;
1528   }
1529 
1530   uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1531     if (GPU <= GK_CAYMAN)
1532       return 32;
1533 
1534     switch(AddrSpace) {
1535       default:
1536         return 64;
1537       case 0:
1538       case 3:
1539       case 5:
1540         return 32;
1541     }
1542   }
1543 
1544   const char * getClobbers() const override {
1545     return "";
1546   }
1547 
1548   void getGCCRegNames(const char * const *&Names,
1549                       unsigned &numNames) const override {
1550     Names = nullptr;
1551     numNames = 0;
1552   }
1553 
1554   void getGCCRegAliases(const GCCRegAlias *&Aliases,
1555                         unsigned &NumAliases) const override {
1556     Aliases = nullptr;
1557     NumAliases = 0;
1558   }
1559 
1560   bool validateAsmConstraint(const char *&Name,
1561                              TargetInfo::ConstraintInfo &info) const override {
1562     return true;
1563   }
1564 
1565   void getTargetBuiltins(const Builtin::Info *&Records,
1566                          unsigned &NumRecords) const override {
1567     Records = BuiltinInfo;
1568     NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
1569   }
1570 
1571   void getTargetDefines(const LangOptions &Opts,
1572                         MacroBuilder &Builder) const override {
1573     Builder.defineMacro("__R600__");
1574   }
1575 
1576   BuiltinVaListKind getBuiltinVaListKind() const override {
1577     return TargetInfo::CharPtrBuiltinVaList;
1578   }
1579 
1580   bool setCPU(const std::string &Name) override {
1581     GPU = llvm::StringSwitch<GPUKind>(Name)
1582       .Case("r600" ,    GK_R600)
1583       .Case("rv610",    GK_R600)
1584       .Case("rv620",    GK_R600)
1585       .Case("rv630",    GK_R600)
1586       .Case("rv635",    GK_R600)
1587       .Case("rs780",    GK_R600)
1588       .Case("rs880",    GK_R600)
1589       .Case("rv670",    GK_R600_DOUBLE_OPS)
1590       .Case("rv710",    GK_R700)
1591       .Case("rv730",    GK_R700)
1592       .Case("rv740",    GK_R700_DOUBLE_OPS)
1593       .Case("rv770",    GK_R700_DOUBLE_OPS)
1594       .Case("palm",     GK_EVERGREEN)
1595       .Case("cedar",    GK_EVERGREEN)
1596       .Case("sumo",     GK_EVERGREEN)
1597       .Case("sumo2",    GK_EVERGREEN)
1598       .Case("redwood",  GK_EVERGREEN)
1599       .Case("juniper",  GK_EVERGREEN)
1600       .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1601       .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1602       .Case("barts",    GK_NORTHERN_ISLANDS)
1603       .Case("turks",    GK_NORTHERN_ISLANDS)
1604       .Case("caicos",   GK_NORTHERN_ISLANDS)
1605       .Case("cayman",   GK_CAYMAN)
1606       .Case("aruba",    GK_CAYMAN)
1607       .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1608       .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1609       .Case("verde",    GK_SOUTHERN_ISLANDS)
1610       .Case("oland",    GK_SOUTHERN_ISLANDS)
1611       .Case("hainan",   GK_SOUTHERN_ISLANDS)
1612       .Case("bonaire",  GK_SEA_ISLANDS)
1613       .Case("kabini",   GK_SEA_ISLANDS)
1614       .Case("kaveri",   GK_SEA_ISLANDS)
1615       .Case("hawaii",   GK_SEA_ISLANDS)
1616       .Case("mullins",  GK_SEA_ISLANDS)
1617       .Default(GK_NONE);
1618 
1619     if (GPU == GK_NONE) {
1620       return false;
1621     }
1622 
1623     // Set the correct data layout
1624     switch (GPU) {
1625     case GK_NONE:
1626     case GK_R600:
1627     case GK_R700:
1628     case GK_EVERGREEN:
1629     case GK_NORTHERN_ISLANDS:
1630       DescriptionString = DescriptionStringR600;
1631       break;
1632     case GK_R600_DOUBLE_OPS:
1633     case GK_R700_DOUBLE_OPS:
1634     case GK_EVERGREEN_DOUBLE_OPS:
1635     case GK_CAYMAN:
1636       DescriptionString = DescriptionStringR600DoubleOps;
1637       break;
1638     case GK_SOUTHERN_ISLANDS:
1639     case GK_SEA_ISLANDS:
1640       DescriptionString = DescriptionStringSI;
1641       break;
1642     }
1643 
1644     return true;
1645   }
1646 };
1647 
1648 const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
1649 #define BUILTIN(ID, TYPE, ATTRS)                \
1650   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1651 #include "clang/Basic/BuiltinsR600.def"
1652 };
1653 
1654 } // end anonymous namespace
1655 
1656 namespace {
1657 // Namespace for x86 abstract base class
1658 const Builtin::Info BuiltinInfo[] = {
1659 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1660 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1661                                               ALL_LANGUAGES },
1662 #include "clang/Basic/BuiltinsX86.def"
1663 };
1664 
1665 static const char* const GCCRegNames[] = {
1666   "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1667   "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1668   "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1669   "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1670   "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1671   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1672   "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1673   "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1674   "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1675 };
1676 
1677 const TargetInfo::AddlRegName AddlRegNames[] = {
1678   { { "al", "ah", "eax", "rax" }, 0 },
1679   { { "bl", "bh", "ebx", "rbx" }, 3 },
1680   { { "cl", "ch", "ecx", "rcx" }, 2 },
1681   { { "dl", "dh", "edx", "rdx" }, 1 },
1682   { { "esi", "rsi" }, 4 },
1683   { { "edi", "rdi" }, 5 },
1684   { { "esp", "rsp" }, 7 },
1685   { { "ebp", "rbp" }, 6 },
1686 };
1687 
1688 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1689 // most of the implementation can be shared.
1690 class X86TargetInfo : public TargetInfo {
1691   enum X86SSEEnum {
1692     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1693   } SSELevel;
1694   enum MMX3DNowEnum {
1695     NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1696   } MMX3DNowLevel;
1697   enum XOPEnum {
1698     NoXOP,
1699     SSE4A,
1700     FMA4,
1701     XOP
1702   } XOPLevel;
1703 
1704   bool HasAES;
1705   bool HasPCLMUL;
1706   bool HasLZCNT;
1707   bool HasRDRND;
1708   bool HasBMI;
1709   bool HasBMI2;
1710   bool HasPOPCNT;
1711   bool HasRTM;
1712   bool HasPRFCHW;
1713   bool HasRDSEED;
1714   bool HasADX;
1715   bool HasTBM;
1716   bool HasFMA;
1717   bool HasF16C;
1718   bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, HasAVX512VL;
1719   bool HasSHA;
1720   bool HasCX16;
1721 
1722   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1723   ///
1724   /// Each enumeration represents a particular CPU supported by Clang. These
1725   /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1726   enum CPUKind {
1727     CK_Generic,
1728 
1729     /// \name i386
1730     /// i386-generation processors.
1731     //@{
1732     CK_i386,
1733     //@}
1734 
1735     /// \name i486
1736     /// i486-generation processors.
1737     //@{
1738     CK_i486,
1739     CK_WinChipC6,
1740     CK_WinChip2,
1741     CK_C3,
1742     //@}
1743 
1744     /// \name i586
1745     /// i586-generation processors, P5 microarchitecture based.
1746     //@{
1747     CK_i586,
1748     CK_Pentium,
1749     CK_PentiumMMX,
1750     //@}
1751 
1752     /// \name i686
1753     /// i686-generation processors, P6 / Pentium M microarchitecture based.
1754     //@{
1755     CK_i686,
1756     CK_PentiumPro,
1757     CK_Pentium2,
1758     CK_Pentium3,
1759     CK_Pentium3M,
1760     CK_PentiumM,
1761     CK_C3_2,
1762 
1763     /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1764     /// Clang however has some logic to suport this.
1765     // FIXME: Warn, deprecate, and potentially remove this.
1766     CK_Yonah,
1767     //@}
1768 
1769     /// \name Netburst
1770     /// Netburst microarchitecture based processors.
1771     //@{
1772     CK_Pentium4,
1773     CK_Pentium4M,
1774     CK_Prescott,
1775     CK_Nocona,
1776     //@}
1777 
1778     /// \name Core
1779     /// Core microarchitecture based processors.
1780     //@{
1781     CK_Core2,
1782 
1783     /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1784     /// codename which GCC no longer accepts as an option to -march, but Clang
1785     /// has some logic for recognizing it.
1786     // FIXME: Warn, deprecate, and potentially remove this.
1787     CK_Penryn,
1788     //@}
1789 
1790     /// \name Atom
1791     /// Atom processors
1792     //@{
1793     CK_Atom,
1794     CK_Silvermont,
1795     //@}
1796 
1797     /// \name Nehalem
1798     /// Nehalem microarchitecture based processors.
1799     //@{
1800     CK_Corei7,
1801     CK_Corei7AVX,
1802     CK_CoreAVXi,
1803     CK_CoreAVX2,
1804     CK_Broadwell,
1805     //@}
1806 
1807     /// \name Knights Landing
1808     /// Knights Landing processor.
1809     CK_KNL,
1810 
1811     /// \name Skylake Server
1812     /// Skylake server processor.
1813     CK_SKX,
1814 
1815     /// \name K6
1816     /// K6 architecture processors.
1817     //@{
1818     CK_K6,
1819     CK_K6_2,
1820     CK_K6_3,
1821     //@}
1822 
1823     /// \name K7
1824     /// K7 architecture processors.
1825     //@{
1826     CK_Athlon,
1827     CK_AthlonThunderbird,
1828     CK_Athlon4,
1829     CK_AthlonXP,
1830     CK_AthlonMP,
1831     //@}
1832 
1833     /// \name K8
1834     /// K8 architecture processors.
1835     //@{
1836     CK_Athlon64,
1837     CK_Athlon64SSE3,
1838     CK_AthlonFX,
1839     CK_K8,
1840     CK_K8SSE3,
1841     CK_Opteron,
1842     CK_OpteronSSE3,
1843     CK_AMDFAM10,
1844     //@}
1845 
1846     /// \name Bobcat
1847     /// Bobcat architecture processors.
1848     //@{
1849     CK_BTVER1,
1850     CK_BTVER2,
1851     //@}
1852 
1853     /// \name Bulldozer
1854     /// Bulldozer architecture processors.
1855     //@{
1856     CK_BDVER1,
1857     CK_BDVER2,
1858     CK_BDVER3,
1859     CK_BDVER4,
1860     //@}
1861 
1862     /// This specification is deprecated and will be removed in the future.
1863     /// Users should prefer \see CK_K8.
1864     // FIXME: Warn on this when the CPU is set to it.
1865     CK_x86_64,
1866     //@}
1867 
1868     /// \name Geode
1869     /// Geode processors.
1870     //@{
1871     CK_Geode
1872     //@}
1873   } CPU;
1874 
1875   enum FPMathKind {
1876     FP_Default,
1877     FP_SSE,
1878     FP_387
1879   } FPMath;
1880 
1881 public:
1882   X86TargetInfo(const llvm::Triple &Triple)
1883       : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1884         XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
1885         HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false),
1886         HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasADX(false),
1887         HasTBM(false), HasFMA(false), HasF16C(false), HasAVX512CD(false),
1888         HasAVX512ER(false), HasAVX512PF(false), HasAVX512DQ(false),
1889         HasAVX512BW(false), HasAVX512VL(false), HasSHA(false), HasCX16(false),
1890         CPU(CK_Generic), FPMath(FP_Default) {
1891     BigEndian = false;
1892     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1893   }
1894   unsigned getFloatEvalMethod() const override {
1895     // X87 evaluates with 80 bits "long double" precision.
1896     return SSELevel == NoSSE ? 2 : 0;
1897   }
1898   void getTargetBuiltins(const Builtin::Info *&Records,
1899                                  unsigned &NumRecords) const override {
1900     Records = BuiltinInfo;
1901     NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1902   }
1903   void getGCCRegNames(const char * const *&Names,
1904                       unsigned &NumNames) const override {
1905     Names = GCCRegNames;
1906     NumNames = llvm::array_lengthof(GCCRegNames);
1907   }
1908   void getGCCRegAliases(const GCCRegAlias *&Aliases,
1909                         unsigned &NumAliases) const override {
1910     Aliases = nullptr;
1911     NumAliases = 0;
1912   }
1913   void getGCCAddlRegNames(const AddlRegName *&Names,
1914                           unsigned &NumNames) const override {
1915     Names = AddlRegNames;
1916     NumNames = llvm::array_lengthof(AddlRegNames);
1917   }
1918   bool validateAsmConstraint(const char *&Name,
1919                                      TargetInfo::ConstraintInfo &info) const override;
1920 
1921   bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
1922 
1923   bool validateInputSize(StringRef Constraint, unsigned Size) const override;
1924 
1925   virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
1926 
1927   std::string convertConstraint(const char *&Constraint) const override;
1928   const char *getClobbers() const override {
1929     return "~{dirflag},~{fpsr},~{flags}";
1930   }
1931   void getTargetDefines(const LangOptions &Opts,
1932                         MacroBuilder &Builder) const override;
1933   static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
1934                           bool Enabled);
1935   static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
1936                           bool Enabled);
1937   static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
1938                           bool Enabled);
1939   void setFeatureEnabled(llvm::StringMap<bool> &Features,
1940                          StringRef Name, bool Enabled) const override {
1941     setFeatureEnabledImpl(Features, Name, Enabled);
1942   }
1943   // This exists purely to cut down on the number of virtual calls in
1944   // getDefaultFeatures which calls this repeatedly.
1945   static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
1946                                     StringRef Name, bool Enabled);
1947   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
1948   bool hasFeature(StringRef Feature) const override;
1949   bool handleTargetFeatures(std::vector<std::string> &Features,
1950                             DiagnosticsEngine &Diags) override;
1951   StringRef getABI() const override {
1952     if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1953       return "avx";
1954     else if (getTriple().getArch() == llvm::Triple::x86 &&
1955              MMX3DNowLevel == NoMMX3DNow)
1956       return "no-mmx";
1957     return "";
1958   }
1959   bool setCPU(const std::string &Name) override {
1960     CPU = llvm::StringSwitch<CPUKind>(Name)
1961       .Case("i386", CK_i386)
1962       .Case("i486", CK_i486)
1963       .Case("winchip-c6", CK_WinChipC6)
1964       .Case("winchip2", CK_WinChip2)
1965       .Case("c3", CK_C3)
1966       .Case("i586", CK_i586)
1967       .Case("pentium", CK_Pentium)
1968       .Case("pentium-mmx", CK_PentiumMMX)
1969       .Case("i686", CK_i686)
1970       .Case("pentiumpro", CK_PentiumPro)
1971       .Case("pentium2", CK_Pentium2)
1972       .Case("pentium3", CK_Pentium3)
1973       .Case("pentium3m", CK_Pentium3M)
1974       .Case("pentium-m", CK_PentiumM)
1975       .Case("c3-2", CK_C3_2)
1976       .Case("yonah", CK_Yonah)
1977       .Case("pentium4", CK_Pentium4)
1978       .Case("pentium4m", CK_Pentium4M)
1979       .Case("prescott", CK_Prescott)
1980       .Case("nocona", CK_Nocona)
1981       .Case("core2", CK_Core2)
1982       .Case("penryn", CK_Penryn)
1983       .Case("atom", CK_Atom)
1984       .Case("slm", CK_Silvermont)
1985       .Case("corei7", CK_Corei7)
1986       .Case("corei7-avx", CK_Corei7AVX)
1987       .Case("core-avx-i", CK_CoreAVXi)
1988       .Case("core-avx2", CK_CoreAVX2)
1989       .Case("broadwell", CK_Broadwell)
1990       .Case("knl", CK_KNL)
1991       .Case("skx", CK_SKX)
1992       .Case("k6", CK_K6)
1993       .Case("k6-2", CK_K6_2)
1994       .Case("k6-3", CK_K6_3)
1995       .Case("athlon", CK_Athlon)
1996       .Case("athlon-tbird", CK_AthlonThunderbird)
1997       .Case("athlon-4", CK_Athlon4)
1998       .Case("athlon-xp", CK_AthlonXP)
1999       .Case("athlon-mp", CK_AthlonMP)
2000       .Case("athlon64", CK_Athlon64)
2001       .Case("athlon64-sse3", CK_Athlon64SSE3)
2002       .Case("athlon-fx", CK_AthlonFX)
2003       .Case("k8", CK_K8)
2004       .Case("k8-sse3", CK_K8SSE3)
2005       .Case("opteron", CK_Opteron)
2006       .Case("opteron-sse3", CK_OpteronSSE3)
2007       .Case("amdfam10", CK_AMDFAM10)
2008       .Case("btver1", CK_BTVER1)
2009       .Case("btver2", CK_BTVER2)
2010       .Case("bdver1", CK_BDVER1)
2011       .Case("bdver2", CK_BDVER2)
2012       .Case("bdver3", CK_BDVER3)
2013       .Case("bdver4", CK_BDVER4)
2014       .Case("x86-64", CK_x86_64)
2015       .Case("geode", CK_Geode)
2016       .Default(CK_Generic);
2017 
2018     // Perform any per-CPU checks necessary to determine if this CPU is
2019     // acceptable.
2020     // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2021     // invalid without explaining *why*.
2022     switch (CPU) {
2023     case CK_Generic:
2024       // No processor selected!
2025       return false;
2026 
2027     case CK_i386:
2028     case CK_i486:
2029     case CK_WinChipC6:
2030     case CK_WinChip2:
2031     case CK_C3:
2032     case CK_i586:
2033     case CK_Pentium:
2034     case CK_PentiumMMX:
2035     case CK_i686:
2036     case CK_PentiumPro:
2037     case CK_Pentium2:
2038     case CK_Pentium3:
2039     case CK_Pentium3M:
2040     case CK_PentiumM:
2041     case CK_Yonah:
2042     case CK_C3_2:
2043     case CK_Pentium4:
2044     case CK_Pentium4M:
2045     case CK_Prescott:
2046     case CK_K6:
2047     case CK_K6_2:
2048     case CK_K6_3:
2049     case CK_Athlon:
2050     case CK_AthlonThunderbird:
2051     case CK_Athlon4:
2052     case CK_AthlonXP:
2053     case CK_AthlonMP:
2054     case CK_Geode:
2055       // Only accept certain architectures when compiling in 32-bit mode.
2056       if (getTriple().getArch() != llvm::Triple::x86)
2057         return false;
2058 
2059       // Fallthrough
2060     case CK_Nocona:
2061     case CK_Core2:
2062     case CK_Penryn:
2063     case CK_Atom:
2064     case CK_Silvermont:
2065     case CK_Corei7:
2066     case CK_Corei7AVX:
2067     case CK_CoreAVXi:
2068     case CK_CoreAVX2:
2069     case CK_Broadwell:
2070     case CK_KNL:
2071     case CK_SKX:
2072     case CK_Athlon64:
2073     case CK_Athlon64SSE3:
2074     case CK_AthlonFX:
2075     case CK_K8:
2076     case CK_K8SSE3:
2077     case CK_Opteron:
2078     case CK_OpteronSSE3:
2079     case CK_AMDFAM10:
2080     case CK_BTVER1:
2081     case CK_BTVER2:
2082     case CK_BDVER1:
2083     case CK_BDVER2:
2084     case CK_BDVER3:
2085     case CK_BDVER4:
2086     case CK_x86_64:
2087       return true;
2088     }
2089     llvm_unreachable("Unhandled CPU kind");
2090   }
2091 
2092   bool setFPMath(StringRef Name) override;
2093 
2094   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2095     // We accept all non-ARM calling conventions
2096     return (CC == CC_X86ThisCall ||
2097             CC == CC_X86FastCall ||
2098             CC == CC_X86StdCall ||
2099             CC == CC_C ||
2100             CC == CC_X86Pascal ||
2101             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2102   }
2103 
2104   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2105     return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2106   }
2107 };
2108 
2109 bool X86TargetInfo::setFPMath(StringRef Name) {
2110   if (Name == "387") {
2111     FPMath = FP_387;
2112     return true;
2113   }
2114   if (Name == "sse") {
2115     FPMath = FP_SSE;
2116     return true;
2117   }
2118   return false;
2119 }
2120 
2121 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2122   // FIXME: This *really* should not be here.
2123 
2124   // X86_64 always has SSE2.
2125   if (getTriple().getArch() == llvm::Triple::x86_64)
2126     setFeatureEnabledImpl(Features, "sse2", true);
2127 
2128   switch (CPU) {
2129   case CK_Generic:
2130   case CK_i386:
2131   case CK_i486:
2132   case CK_i586:
2133   case CK_Pentium:
2134   case CK_i686:
2135   case CK_PentiumPro:
2136     break;
2137   case CK_PentiumMMX:
2138   case CK_Pentium2:
2139     setFeatureEnabledImpl(Features, "mmx", true);
2140     break;
2141   case CK_Pentium3:
2142   case CK_Pentium3M:
2143     setFeatureEnabledImpl(Features, "sse", true);
2144     break;
2145   case CK_PentiumM:
2146   case CK_Pentium4:
2147   case CK_Pentium4M:
2148   case CK_x86_64:
2149     setFeatureEnabledImpl(Features, "sse2", true);
2150     break;
2151   case CK_Yonah:
2152   case CK_Prescott:
2153   case CK_Nocona:
2154     setFeatureEnabledImpl(Features, "sse3", true);
2155     setFeatureEnabledImpl(Features, "cx16", true);
2156     break;
2157   case CK_Core2:
2158     setFeatureEnabledImpl(Features, "ssse3", true);
2159     setFeatureEnabledImpl(Features, "cx16", true);
2160     break;
2161   case CK_Penryn:
2162     setFeatureEnabledImpl(Features, "sse4.1", true);
2163     setFeatureEnabledImpl(Features, "cx16", true);
2164     break;
2165   case CK_Atom:
2166     setFeatureEnabledImpl(Features, "ssse3", true);
2167     setFeatureEnabledImpl(Features, "cx16", true);
2168     break;
2169   case CK_Silvermont:
2170     setFeatureEnabledImpl(Features, "sse4.2", true);
2171     setFeatureEnabledImpl(Features, "aes", true);
2172     setFeatureEnabledImpl(Features, "cx16", true);
2173     setFeatureEnabledImpl(Features, "pclmul", true);
2174     break;
2175   case CK_Corei7:
2176     setFeatureEnabledImpl(Features, "sse4.2", true);
2177     setFeatureEnabledImpl(Features, "cx16", true);
2178     break;
2179   case CK_Corei7AVX:
2180     setFeatureEnabledImpl(Features, "avx", true);
2181     setFeatureEnabledImpl(Features, "aes", true);
2182     setFeatureEnabledImpl(Features, "cx16", true);
2183     setFeatureEnabledImpl(Features, "pclmul", true);
2184     break;
2185   case CK_CoreAVXi:
2186     setFeatureEnabledImpl(Features, "avx", true);
2187     setFeatureEnabledImpl(Features, "aes", true);
2188     setFeatureEnabledImpl(Features, "pclmul", true);
2189     setFeatureEnabledImpl(Features, "rdrnd", true);
2190     setFeatureEnabledImpl(Features, "f16c", true);
2191     break;
2192   case CK_CoreAVX2:
2193     setFeatureEnabledImpl(Features, "avx2", true);
2194     setFeatureEnabledImpl(Features, "aes", true);
2195     setFeatureEnabledImpl(Features, "pclmul", true);
2196     setFeatureEnabledImpl(Features, "lzcnt", true);
2197     setFeatureEnabledImpl(Features, "rdrnd", true);
2198     setFeatureEnabledImpl(Features, "f16c", true);
2199     setFeatureEnabledImpl(Features, "bmi", true);
2200     setFeatureEnabledImpl(Features, "bmi2", true);
2201     setFeatureEnabledImpl(Features, "rtm", true);
2202     setFeatureEnabledImpl(Features, "fma", true);
2203     setFeatureEnabledImpl(Features, "cx16", true);
2204     break;
2205   case CK_Broadwell:
2206     setFeatureEnabledImpl(Features, "avx2", true);
2207     setFeatureEnabledImpl(Features, "aes", true);
2208     setFeatureEnabledImpl(Features, "pclmul", true);
2209     setFeatureEnabledImpl(Features, "lzcnt", true);
2210     setFeatureEnabledImpl(Features, "rdrnd", true);
2211     setFeatureEnabledImpl(Features, "f16c", true);
2212     setFeatureEnabledImpl(Features, "bmi", true);
2213     setFeatureEnabledImpl(Features, "bmi2", true);
2214     setFeatureEnabledImpl(Features, "rtm", true);
2215     setFeatureEnabledImpl(Features, "fma", true);
2216     setFeatureEnabledImpl(Features, "cx16", true);
2217     setFeatureEnabledImpl(Features, "rdseed", true);
2218     setFeatureEnabledImpl(Features, "adx", true);
2219     break;
2220   case CK_KNL:
2221     setFeatureEnabledImpl(Features, "avx512f", true);
2222     setFeatureEnabledImpl(Features, "avx512cd", true);
2223     setFeatureEnabledImpl(Features, "avx512er", true);
2224     setFeatureEnabledImpl(Features, "avx512pf", true);
2225     setFeatureEnabledImpl(Features, "aes", true);
2226     setFeatureEnabledImpl(Features, "pclmul", true);
2227     setFeatureEnabledImpl(Features, "lzcnt", true);
2228     setFeatureEnabledImpl(Features, "rdrnd", true);
2229     setFeatureEnabledImpl(Features, "f16c", true);
2230     setFeatureEnabledImpl(Features, "bmi", true);
2231     setFeatureEnabledImpl(Features, "bmi2", true);
2232     setFeatureEnabledImpl(Features, "rtm", true);
2233     setFeatureEnabledImpl(Features, "fma", true);
2234     setFeatureEnabledImpl(Features, "rdseed", true);
2235     setFeatureEnabledImpl(Features, "adx", true);
2236     break;
2237   case CK_SKX:
2238     setFeatureEnabledImpl(Features, "avx512f", true);
2239     setFeatureEnabledImpl(Features, "avx512cd", true);
2240     setFeatureEnabledImpl(Features, "avx512dq", true);
2241     setFeatureEnabledImpl(Features, "avx512bw", true);
2242     setFeatureEnabledImpl(Features, "avx512vl", true);
2243     setFeatureEnabledImpl(Features, "aes", true);
2244     setFeatureEnabledImpl(Features, "pclmul", true);
2245     setFeatureEnabledImpl(Features, "lzcnt", true);
2246     setFeatureEnabledImpl(Features, "rdrnd", true);
2247     setFeatureEnabledImpl(Features, "f16c", true);
2248     setFeatureEnabledImpl(Features, "bmi", true);
2249     setFeatureEnabledImpl(Features, "bmi2", true);
2250     setFeatureEnabledImpl(Features, "rtm", true);
2251     setFeatureEnabledImpl(Features, "fma", true);
2252     setFeatureEnabledImpl(Features, "rdseed", true);
2253     setFeatureEnabledImpl(Features, "adx", true);
2254     break;
2255   case CK_K6:
2256   case CK_WinChipC6:
2257     setFeatureEnabledImpl(Features, "mmx", true);
2258     break;
2259   case CK_K6_2:
2260   case CK_K6_3:
2261   case CK_WinChip2:
2262   case CK_C3:
2263     setFeatureEnabledImpl(Features, "3dnow", true);
2264     break;
2265   case CK_Athlon:
2266   case CK_AthlonThunderbird:
2267   case CK_Geode:
2268     setFeatureEnabledImpl(Features, "3dnowa", true);
2269     break;
2270   case CK_Athlon4:
2271   case CK_AthlonXP:
2272   case CK_AthlonMP:
2273     setFeatureEnabledImpl(Features, "sse", true);
2274     setFeatureEnabledImpl(Features, "3dnowa", true);
2275     break;
2276   case CK_K8:
2277   case CK_Opteron:
2278   case CK_Athlon64:
2279   case CK_AthlonFX:
2280     setFeatureEnabledImpl(Features, "sse2", true);
2281     setFeatureEnabledImpl(Features, "3dnowa", true);
2282     break;
2283   case CK_K8SSE3:
2284   case CK_OpteronSSE3:
2285   case CK_Athlon64SSE3:
2286     setFeatureEnabledImpl(Features, "sse3", true);
2287     setFeatureEnabledImpl(Features, "3dnowa", true);
2288     break;
2289   case CK_AMDFAM10:
2290     setFeatureEnabledImpl(Features, "sse3", true);
2291     setFeatureEnabledImpl(Features, "sse4a", true);
2292     setFeatureEnabledImpl(Features, "3dnowa", true);
2293     setFeatureEnabledImpl(Features, "lzcnt", true);
2294     setFeatureEnabledImpl(Features, "popcnt", true);
2295     break;
2296   case CK_BTVER1:
2297     setFeatureEnabledImpl(Features, "ssse3", true);
2298     setFeatureEnabledImpl(Features, "sse4a", true);
2299     setFeatureEnabledImpl(Features, "cx16", true);
2300     setFeatureEnabledImpl(Features, "lzcnt", true);
2301     setFeatureEnabledImpl(Features, "popcnt", true);
2302     setFeatureEnabledImpl(Features, "prfchw", true);
2303     break;
2304   case CK_BTVER2:
2305     setFeatureEnabledImpl(Features, "avx", true);
2306     setFeatureEnabledImpl(Features, "sse4a", true);
2307     setFeatureEnabledImpl(Features, "lzcnt", true);
2308     setFeatureEnabledImpl(Features, "aes", true);
2309     setFeatureEnabledImpl(Features, "pclmul", true);
2310     setFeatureEnabledImpl(Features, "prfchw", true);
2311     setFeatureEnabledImpl(Features, "bmi", true);
2312     setFeatureEnabledImpl(Features, "f16c", true);
2313     setFeatureEnabledImpl(Features, "cx16", true);
2314     break;
2315   case CK_BDVER1:
2316     setFeatureEnabledImpl(Features, "xop", true);
2317     setFeatureEnabledImpl(Features, "lzcnt", true);
2318     setFeatureEnabledImpl(Features, "aes", true);
2319     setFeatureEnabledImpl(Features, "pclmul", true);
2320     setFeatureEnabledImpl(Features, "prfchw", true);
2321     setFeatureEnabledImpl(Features, "cx16", true);
2322     break;
2323   case CK_BDVER4:
2324     setFeatureEnabledImpl(Features, "avx2", true);
2325     setFeatureEnabledImpl(Features, "bmi2", true);
2326     // FALLTHROUGH
2327   case CK_BDVER2:
2328   case CK_BDVER3:
2329     setFeatureEnabledImpl(Features, "xop", true);
2330     setFeatureEnabledImpl(Features, "lzcnt", true);
2331     setFeatureEnabledImpl(Features, "aes", true);
2332     setFeatureEnabledImpl(Features, "pclmul", true);
2333     setFeatureEnabledImpl(Features, "prfchw", true);
2334     setFeatureEnabledImpl(Features, "bmi", true);
2335     setFeatureEnabledImpl(Features, "fma", true);
2336     setFeatureEnabledImpl(Features, "f16c", true);
2337     setFeatureEnabledImpl(Features, "tbm", true);
2338     setFeatureEnabledImpl(Features, "cx16", true);
2339     break;
2340   case CK_C3_2:
2341     setFeatureEnabledImpl(Features, "sse", true);
2342     break;
2343   }
2344 }
2345 
2346 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2347                                 X86SSEEnum Level, bool Enabled) {
2348   if (Enabled) {
2349     switch (Level) {
2350     case AVX512F:
2351       Features["avx512f"] = true;
2352     case AVX2:
2353       Features["avx2"] = true;
2354     case AVX:
2355       Features["avx"] = true;
2356     case SSE42:
2357       Features["sse4.2"] = true;
2358     case SSE41:
2359       Features["sse4.1"] = true;
2360     case SSSE3:
2361       Features["ssse3"] = true;
2362     case SSE3:
2363       Features["sse3"] = true;
2364     case SSE2:
2365       Features["sse2"] = true;
2366     case SSE1:
2367       Features["sse"] = true;
2368     case NoSSE:
2369       break;
2370     }
2371     return;
2372   }
2373 
2374   switch (Level) {
2375   case NoSSE:
2376   case SSE1:
2377     Features["sse"] = false;
2378   case SSE2:
2379     Features["sse2"] = Features["pclmul"] = Features["aes"] =
2380       Features["sha"] = false;
2381   case SSE3:
2382     Features["sse3"] = false;
2383     setXOPLevel(Features, NoXOP, false);
2384   case SSSE3:
2385     Features["ssse3"] = false;
2386   case SSE41:
2387     Features["sse4.1"] = false;
2388   case SSE42:
2389     Features["sse4.2"] = false;
2390   case AVX:
2391     Features["fma"] = Features["avx"] = Features["f16c"] = false;
2392     setXOPLevel(Features, FMA4, false);
2393   case AVX2:
2394     Features["avx2"] = false;
2395   case AVX512F:
2396     Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = Features["avx512pf"] =
2397     Features["avx512dq"] = Features["avx512bw"] = Features["avx512vl"] = false;
2398   }
2399 }
2400 
2401 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2402                                 MMX3DNowEnum Level, bool Enabled) {
2403   if (Enabled) {
2404     switch (Level) {
2405     case AMD3DNowAthlon:
2406       Features["3dnowa"] = true;
2407     case AMD3DNow:
2408       Features["3dnow"] = true;
2409     case MMX:
2410       Features["mmx"] = true;
2411     case NoMMX3DNow:
2412       break;
2413     }
2414     return;
2415   }
2416 
2417   switch (Level) {
2418   case NoMMX3DNow:
2419   case MMX:
2420     Features["mmx"] = false;
2421   case AMD3DNow:
2422     Features["3dnow"] = false;
2423   case AMD3DNowAthlon:
2424     Features["3dnowa"] = false;
2425   }
2426 }
2427 
2428 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2429                                 bool Enabled) {
2430   if (Enabled) {
2431     switch (Level) {
2432     case XOP:
2433       Features["xop"] = true;
2434     case FMA4:
2435       Features["fma4"] = true;
2436       setSSELevel(Features, AVX, true);
2437     case SSE4A:
2438       Features["sse4a"] = true;
2439       setSSELevel(Features, SSE3, true);
2440     case NoXOP:
2441       break;
2442     }
2443     return;
2444   }
2445 
2446   switch (Level) {
2447   case NoXOP:
2448   case SSE4A:
2449     Features["sse4a"] = false;
2450   case FMA4:
2451     Features["fma4"] = false;
2452   case XOP:
2453     Features["xop"] = false;
2454   }
2455 }
2456 
2457 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2458                                           StringRef Name, bool Enabled) {
2459   // FIXME: This *really* should not be here.  We need some way of translating
2460   // options into llvm subtarget features.
2461   if (Name == "sse4")
2462     Name = "sse4.2";
2463 
2464   Features[Name] = Enabled;
2465 
2466   if (Name == "mmx") {
2467     setMMXLevel(Features, MMX, Enabled);
2468   } else if (Name == "sse") {
2469     setSSELevel(Features, SSE1, Enabled);
2470   } else if (Name == "sse2") {
2471     setSSELevel(Features, SSE2, Enabled);
2472   } else if (Name == "sse3") {
2473     setSSELevel(Features, SSE3, Enabled);
2474   } else if (Name == "ssse3") {
2475     setSSELevel(Features, SSSE3, Enabled);
2476   } else if (Name == "sse4.2") {
2477     setSSELevel(Features, SSE42, Enabled);
2478   } else if (Name == "sse4.1") {
2479     setSSELevel(Features, SSE41, Enabled);
2480   } else if (Name == "3dnow") {
2481     setMMXLevel(Features, AMD3DNow, Enabled);
2482   } else if (Name == "3dnowa") {
2483     setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2484   } else if (Name == "aes") {
2485     if (Enabled)
2486       setSSELevel(Features, SSE2, Enabled);
2487   } else if (Name == "pclmul") {
2488     if (Enabled)
2489       setSSELevel(Features, SSE2, Enabled);
2490   } else if (Name == "avx") {
2491     setSSELevel(Features, AVX, Enabled);
2492   } else if (Name == "avx2") {
2493     setSSELevel(Features, AVX2, Enabled);
2494   } else if (Name == "avx512f") {
2495     setSSELevel(Features, AVX512F, Enabled);
2496   } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2497           || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2498     if (Enabled)
2499       setSSELevel(Features, AVX512F, Enabled);
2500   } else if (Name == "fma") {
2501     if (Enabled)
2502       setSSELevel(Features, AVX, Enabled);
2503   } else if (Name == "fma4") {
2504     setXOPLevel(Features, FMA4, Enabled);
2505   } else if (Name == "xop") {
2506     setXOPLevel(Features, XOP, Enabled);
2507   } else if (Name == "sse4a") {
2508     setXOPLevel(Features, SSE4A, Enabled);
2509   } else if (Name == "f16c") {
2510     if (Enabled)
2511       setSSELevel(Features, AVX, Enabled);
2512   } else if (Name == "sha") {
2513     if (Enabled)
2514       setSSELevel(Features, SSE2, Enabled);
2515   }
2516 }
2517 
2518 /// handleTargetFeatures - Perform initialization based on the user
2519 /// configured set of features.
2520 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2521                                          DiagnosticsEngine &Diags) {
2522   // Remember the maximum enabled sselevel.
2523   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2524     // Ignore disabled features.
2525     if (Features[i][0] == '-')
2526       continue;
2527 
2528     StringRef Feature = StringRef(Features[i]).substr(1);
2529 
2530     if (Feature == "aes") {
2531       HasAES = true;
2532       continue;
2533     }
2534 
2535     if (Feature == "pclmul") {
2536       HasPCLMUL = true;
2537       continue;
2538     }
2539 
2540     if (Feature == "lzcnt") {
2541       HasLZCNT = true;
2542       continue;
2543     }
2544 
2545     if (Feature == "rdrnd") {
2546       HasRDRND = true;
2547       continue;
2548     }
2549 
2550     if (Feature == "bmi") {
2551       HasBMI = true;
2552       continue;
2553     }
2554 
2555     if (Feature == "bmi2") {
2556       HasBMI2 = true;
2557       continue;
2558     }
2559 
2560     if (Feature == "popcnt") {
2561       HasPOPCNT = true;
2562       continue;
2563     }
2564 
2565     if (Feature == "rtm") {
2566       HasRTM = true;
2567       continue;
2568     }
2569 
2570     if (Feature == "prfchw") {
2571       HasPRFCHW = true;
2572       continue;
2573     }
2574 
2575     if (Feature == "rdseed") {
2576       HasRDSEED = true;
2577       continue;
2578     }
2579 
2580     if (Feature == "adx") {
2581       HasADX = true;
2582       continue;
2583     }
2584 
2585     if (Feature == "tbm") {
2586       HasTBM = true;
2587       continue;
2588     }
2589 
2590     if (Feature == "fma") {
2591       HasFMA = true;
2592       continue;
2593     }
2594 
2595     if (Feature == "f16c") {
2596       HasF16C = true;
2597       continue;
2598     }
2599 
2600     if (Feature == "avx512cd") {
2601       HasAVX512CD = true;
2602       continue;
2603     }
2604 
2605     if (Feature == "avx512er") {
2606       HasAVX512ER = true;
2607       continue;
2608     }
2609 
2610     if (Feature == "avx512pf") {
2611       HasAVX512PF = true;
2612       continue;
2613     }
2614 
2615     if (Feature == "avx512dq") {
2616       HasAVX512DQ = true;
2617       continue;
2618     }
2619 
2620     if (Feature == "avx512bw") {
2621       HasAVX512BW = true;
2622       continue;
2623     }
2624 
2625     if (Feature == "avx512vl") {
2626       HasAVX512VL = true;
2627       continue;
2628     }
2629 
2630     if (Feature == "sha") {
2631       HasSHA = true;
2632       continue;
2633     }
2634 
2635     if (Feature == "cx16") {
2636       HasCX16 = true;
2637       continue;
2638     }
2639 
2640     assert(Features[i][0] == '+' && "Invalid target feature!");
2641     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2642       .Case("avx512f", AVX512F)
2643       .Case("avx2", AVX2)
2644       .Case("avx", AVX)
2645       .Case("sse4.2", SSE42)
2646       .Case("sse4.1", SSE41)
2647       .Case("ssse3", SSSE3)
2648       .Case("sse3", SSE3)
2649       .Case("sse2", SSE2)
2650       .Case("sse", SSE1)
2651       .Default(NoSSE);
2652     SSELevel = std::max(SSELevel, Level);
2653 
2654     MMX3DNowEnum ThreeDNowLevel =
2655       llvm::StringSwitch<MMX3DNowEnum>(Feature)
2656         .Case("3dnowa", AMD3DNowAthlon)
2657         .Case("3dnow", AMD3DNow)
2658         .Case("mmx", MMX)
2659         .Default(NoMMX3DNow);
2660     MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2661 
2662     XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2663         .Case("xop", XOP)
2664         .Case("fma4", FMA4)
2665         .Case("sse4a", SSE4A)
2666         .Default(NoXOP);
2667     XOPLevel = std::max(XOPLevel, XLevel);
2668   }
2669 
2670   // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2671   // Can't do this earlier because we need to be able to explicitly enable
2672   // popcnt and still disable sse4.2.
2673   if (!HasPOPCNT && SSELevel >= SSE42 &&
2674       std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2675     HasPOPCNT = true;
2676     Features.push_back("+popcnt");
2677   }
2678 
2679   // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2680   if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2681       std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2682     HasPRFCHW = true;
2683     Features.push_back("+prfchw");
2684   }
2685 
2686   // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2687   // matches the selected sse level.
2688   if (FPMath == FP_SSE && SSELevel < SSE1) {
2689     Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2690     return false;
2691   } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2692     Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2693     return false;
2694   }
2695 
2696   // Don't tell the backend if we're turning off mmx; it will end up disabling
2697   // SSE, which we don't want.
2698   // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2699   // then enable MMX.
2700   std::vector<std::string>::iterator it;
2701   it = std::find(Features.begin(), Features.end(), "-mmx");
2702   if (it != Features.end())
2703     Features.erase(it);
2704   else if (SSELevel > NoSSE)
2705     MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2706   return true;
2707 }
2708 
2709 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2710 /// definitions for this particular subtarget.
2711 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2712                                      MacroBuilder &Builder) const {
2713   // Target identification.
2714   if (getTriple().getArch() == llvm::Triple::x86_64) {
2715     Builder.defineMacro("__amd64__");
2716     Builder.defineMacro("__amd64");
2717     Builder.defineMacro("__x86_64");
2718     Builder.defineMacro("__x86_64__");
2719     if (getTriple().getArchName() == "x86_64h") {
2720       Builder.defineMacro("__x86_64h");
2721       Builder.defineMacro("__x86_64h__");
2722     }
2723   } else {
2724     DefineStd(Builder, "i386", Opts);
2725   }
2726 
2727   // Subtarget options.
2728   // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2729   // truly should be based on -mtune options.
2730   switch (CPU) {
2731   case CK_Generic:
2732     break;
2733   case CK_i386:
2734     // The rest are coming from the i386 define above.
2735     Builder.defineMacro("__tune_i386__");
2736     break;
2737   case CK_i486:
2738   case CK_WinChipC6:
2739   case CK_WinChip2:
2740   case CK_C3:
2741     defineCPUMacros(Builder, "i486");
2742     break;
2743   case CK_PentiumMMX:
2744     Builder.defineMacro("__pentium_mmx__");
2745     Builder.defineMacro("__tune_pentium_mmx__");
2746     // Fallthrough
2747   case CK_i586:
2748   case CK_Pentium:
2749     defineCPUMacros(Builder, "i586");
2750     defineCPUMacros(Builder, "pentium");
2751     break;
2752   case CK_Pentium3:
2753   case CK_Pentium3M:
2754   case CK_PentiumM:
2755     Builder.defineMacro("__tune_pentium3__");
2756     // Fallthrough
2757   case CK_Pentium2:
2758   case CK_C3_2:
2759     Builder.defineMacro("__tune_pentium2__");
2760     // Fallthrough
2761   case CK_PentiumPro:
2762     Builder.defineMacro("__tune_i686__");
2763     Builder.defineMacro("__tune_pentiumpro__");
2764     // Fallthrough
2765   case CK_i686:
2766     Builder.defineMacro("__i686");
2767     Builder.defineMacro("__i686__");
2768     // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2769     Builder.defineMacro("__pentiumpro");
2770     Builder.defineMacro("__pentiumpro__");
2771     break;
2772   case CK_Pentium4:
2773   case CK_Pentium4M:
2774     defineCPUMacros(Builder, "pentium4");
2775     break;
2776   case CK_Yonah:
2777   case CK_Prescott:
2778   case CK_Nocona:
2779     defineCPUMacros(Builder, "nocona");
2780     break;
2781   case CK_Core2:
2782   case CK_Penryn:
2783     defineCPUMacros(Builder, "core2");
2784     break;
2785   case CK_Atom:
2786     defineCPUMacros(Builder, "atom");
2787     break;
2788   case CK_Silvermont:
2789     defineCPUMacros(Builder, "slm");
2790     break;
2791   case CK_Corei7:
2792   case CK_Corei7AVX:
2793   case CK_CoreAVXi:
2794   case CK_CoreAVX2:
2795   case CK_Broadwell:
2796     defineCPUMacros(Builder, "corei7");
2797     break;
2798   case CK_KNL:
2799     defineCPUMacros(Builder, "knl");
2800     break;
2801   case CK_SKX:
2802     defineCPUMacros(Builder, "skx");
2803     break;
2804   case CK_K6_2:
2805     Builder.defineMacro("__k6_2__");
2806     Builder.defineMacro("__tune_k6_2__");
2807     // Fallthrough
2808   case CK_K6_3:
2809     if (CPU != CK_K6_2) {  // In case of fallthrough
2810       // FIXME: GCC may be enabling these in cases where some other k6
2811       // architecture is specified but -m3dnow is explicitly provided. The
2812       // exact semantics need to be determined and emulated here.
2813       Builder.defineMacro("__k6_3__");
2814       Builder.defineMacro("__tune_k6_3__");
2815     }
2816     // Fallthrough
2817   case CK_K6:
2818     defineCPUMacros(Builder, "k6");
2819     break;
2820   case CK_Athlon:
2821   case CK_AthlonThunderbird:
2822   case CK_Athlon4:
2823   case CK_AthlonXP:
2824   case CK_AthlonMP:
2825     defineCPUMacros(Builder, "athlon");
2826     if (SSELevel != NoSSE) {
2827       Builder.defineMacro("__athlon_sse__");
2828       Builder.defineMacro("__tune_athlon_sse__");
2829     }
2830     break;
2831   case CK_K8:
2832   case CK_K8SSE3:
2833   case CK_x86_64:
2834   case CK_Opteron:
2835   case CK_OpteronSSE3:
2836   case CK_Athlon64:
2837   case CK_Athlon64SSE3:
2838   case CK_AthlonFX:
2839     defineCPUMacros(Builder, "k8");
2840     break;
2841   case CK_AMDFAM10:
2842     defineCPUMacros(Builder, "amdfam10");
2843     break;
2844   case CK_BTVER1:
2845     defineCPUMacros(Builder, "btver1");
2846     break;
2847   case CK_BTVER2:
2848     defineCPUMacros(Builder, "btver2");
2849     break;
2850   case CK_BDVER1:
2851     defineCPUMacros(Builder, "bdver1");
2852     break;
2853   case CK_BDVER2:
2854     defineCPUMacros(Builder, "bdver2");
2855     break;
2856   case CK_BDVER3:
2857     defineCPUMacros(Builder, "bdver3");
2858     break;
2859   case CK_BDVER4:
2860     defineCPUMacros(Builder, "bdver4");
2861     break;
2862   case CK_Geode:
2863     defineCPUMacros(Builder, "geode");
2864     break;
2865   }
2866 
2867   // Target properties.
2868   Builder.defineMacro("__REGISTER_PREFIX__", "");
2869 
2870   // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2871   // functions in glibc header files that use FP Stack inline asm which the
2872   // backend can't deal with (PR879).
2873   Builder.defineMacro("__NO_MATH_INLINES");
2874 
2875   if (HasAES)
2876     Builder.defineMacro("__AES__");
2877 
2878   if (HasPCLMUL)
2879     Builder.defineMacro("__PCLMUL__");
2880 
2881   if (HasLZCNT)
2882     Builder.defineMacro("__LZCNT__");
2883 
2884   if (HasRDRND)
2885     Builder.defineMacro("__RDRND__");
2886 
2887   if (HasBMI)
2888     Builder.defineMacro("__BMI__");
2889 
2890   if (HasBMI2)
2891     Builder.defineMacro("__BMI2__");
2892 
2893   if (HasPOPCNT)
2894     Builder.defineMacro("__POPCNT__");
2895 
2896   if (HasRTM)
2897     Builder.defineMacro("__RTM__");
2898 
2899   if (HasPRFCHW)
2900     Builder.defineMacro("__PRFCHW__");
2901 
2902   if (HasRDSEED)
2903     Builder.defineMacro("__RDSEED__");
2904 
2905   if (HasADX)
2906     Builder.defineMacro("__ADX__");
2907 
2908   if (HasTBM)
2909     Builder.defineMacro("__TBM__");
2910 
2911   switch (XOPLevel) {
2912   case XOP:
2913     Builder.defineMacro("__XOP__");
2914   case FMA4:
2915     Builder.defineMacro("__FMA4__");
2916   case SSE4A:
2917     Builder.defineMacro("__SSE4A__");
2918   case NoXOP:
2919     break;
2920   }
2921 
2922   if (HasFMA)
2923     Builder.defineMacro("__FMA__");
2924 
2925   if (HasF16C)
2926     Builder.defineMacro("__F16C__");
2927 
2928   if (HasAVX512CD)
2929     Builder.defineMacro("__AVX512CD__");
2930   if (HasAVX512ER)
2931     Builder.defineMacro("__AVX512ER__");
2932   if (HasAVX512PF)
2933     Builder.defineMacro("__AVX512PF__");
2934   if (HasAVX512DQ)
2935     Builder.defineMacro("__AVX512DQ__");
2936   if (HasAVX512BW)
2937     Builder.defineMacro("__AVX512BW__");
2938   if (HasAVX512VL)
2939     Builder.defineMacro("__AVX512VL__");
2940 
2941   if (HasSHA)
2942     Builder.defineMacro("__SHA__");
2943 
2944   if (HasCX16)
2945     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
2946 
2947   // Each case falls through to the previous one here.
2948   switch (SSELevel) {
2949   case AVX512F:
2950     Builder.defineMacro("__AVX512F__");
2951   case AVX2:
2952     Builder.defineMacro("__AVX2__");
2953   case AVX:
2954     Builder.defineMacro("__AVX__");
2955   case SSE42:
2956     Builder.defineMacro("__SSE4_2__");
2957   case SSE41:
2958     Builder.defineMacro("__SSE4_1__");
2959   case SSSE3:
2960     Builder.defineMacro("__SSSE3__");
2961   case SSE3:
2962     Builder.defineMacro("__SSE3__");
2963   case SSE2:
2964     Builder.defineMacro("__SSE2__");
2965     Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2966   case SSE1:
2967     Builder.defineMacro("__SSE__");
2968     Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2969   case NoSSE:
2970     break;
2971   }
2972 
2973   if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2974     switch (SSELevel) {
2975     case AVX512F:
2976     case AVX2:
2977     case AVX:
2978     case SSE42:
2979     case SSE41:
2980     case SSSE3:
2981     case SSE3:
2982     case SSE2:
2983       Builder.defineMacro("_M_IX86_FP", Twine(2));
2984       break;
2985     case SSE1:
2986       Builder.defineMacro("_M_IX86_FP", Twine(1));
2987       break;
2988     default:
2989       Builder.defineMacro("_M_IX86_FP", Twine(0));
2990     }
2991   }
2992 
2993   // Each case falls through to the previous one here.
2994   switch (MMX3DNowLevel) {
2995   case AMD3DNowAthlon:
2996     Builder.defineMacro("__3dNOW_A__");
2997   case AMD3DNow:
2998     Builder.defineMacro("__3dNOW__");
2999   case MMX:
3000     Builder.defineMacro("__MMX__");
3001   case NoMMX3DNow:
3002     break;
3003   }
3004 
3005   if (CPU >= CK_i486) {
3006     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3007     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3008     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3009   }
3010   if (CPU >= CK_i586)
3011     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3012 }
3013 
3014 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3015   return llvm::StringSwitch<bool>(Feature)
3016       .Case("aes", HasAES)
3017       .Case("avx", SSELevel >= AVX)
3018       .Case("avx2", SSELevel >= AVX2)
3019       .Case("avx512f", SSELevel >= AVX512F)
3020       .Case("avx512cd", HasAVX512CD)
3021       .Case("avx512er", HasAVX512ER)
3022       .Case("avx512pf", HasAVX512PF)
3023       .Case("avx512dq", HasAVX512DQ)
3024       .Case("avx512bw", HasAVX512BW)
3025       .Case("avx512vl", HasAVX512VL)
3026       .Case("bmi", HasBMI)
3027       .Case("bmi2", HasBMI2)
3028       .Case("cx16", HasCX16)
3029       .Case("f16c", HasF16C)
3030       .Case("fma", HasFMA)
3031       .Case("fma4", XOPLevel >= FMA4)
3032       .Case("tbm", HasTBM)
3033       .Case("lzcnt", HasLZCNT)
3034       .Case("rdrnd", HasRDRND)
3035       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3036       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3037       .Case("mmx", MMX3DNowLevel >= MMX)
3038       .Case("pclmul", HasPCLMUL)
3039       .Case("popcnt", HasPOPCNT)
3040       .Case("rtm", HasRTM)
3041       .Case("prfchw", HasPRFCHW)
3042       .Case("rdseed", HasRDSEED)
3043       .Case("sha", HasSHA)
3044       .Case("sse", SSELevel >= SSE1)
3045       .Case("sse2", SSELevel >= SSE2)
3046       .Case("sse3", SSELevel >= SSE3)
3047       .Case("ssse3", SSELevel >= SSSE3)
3048       .Case("sse4.1", SSELevel >= SSE41)
3049       .Case("sse4.2", SSELevel >= SSE42)
3050       .Case("sse4a", XOPLevel >= SSE4A)
3051       .Case("x86", true)
3052       .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3053       .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3054       .Case("xop", XOPLevel >= XOP)
3055       .Default(false);
3056 }
3057 
3058 bool
3059 X86TargetInfo::validateAsmConstraint(const char *&Name,
3060                                      TargetInfo::ConstraintInfo &Info) const {
3061   switch (*Name) {
3062   default: return false;
3063   case 'Y': // first letter of a pair:
3064     switch (*(Name+1)) {
3065     default: return false;
3066     case '0':  // First SSE register.
3067     case 't':  // Any SSE register, when SSE2 is enabled.
3068     case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
3069     case 'm':  // any MMX register, when inter-unit moves enabled.
3070       break;   // falls through to setAllowsRegister.
3071   }
3072   case 'f': // any x87 floating point stack register.
3073     // Constraint 'f' cannot be used for output operands.
3074     if (Info.ConstraintStr[0] == '=')
3075       return false;
3076 
3077     Info.setAllowsRegister();
3078     return true;
3079   case 'a': // eax.
3080   case 'b': // ebx.
3081   case 'c': // ecx.
3082   case 'd': // edx.
3083   case 'S': // esi.
3084   case 'D': // edi.
3085   case 'A': // edx:eax.
3086   case 't': // top of floating point stack.
3087   case 'u': // second from top of floating point stack.
3088   case 'q': // Any register accessible as [r]l: a, b, c, and d.
3089   case 'y': // Any MMX register.
3090   case 'x': // Any SSE register.
3091   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3092   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3093   case 'l': // "Index" registers: any general register that can be used as an
3094             // index in a base+index memory access.
3095     Info.setAllowsRegister();
3096     return true;
3097   case 'C': // SSE floating point constant.
3098   case 'G': // x87 floating point constant.
3099   case 'e': // 32-bit signed integer constant for use with zero-extending
3100             // x86_64 instructions.
3101   case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3102             // x86_64 instructions.
3103     return true;
3104   }
3105 }
3106 
3107 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3108                                        unsigned Size) const {
3109   // Strip off constraint modifiers.
3110   while (Constraint[0] == '=' ||
3111          Constraint[0] == '+' ||
3112          Constraint[0] == '&')
3113     Constraint = Constraint.substr(1);
3114 
3115   return validateOperandSize(Constraint, Size);
3116 }
3117 
3118 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3119                                       unsigned Size) const {
3120   return validateOperandSize(Constraint, Size);
3121 }
3122 
3123 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3124                                         unsigned Size) const {
3125   switch (Constraint[0]) {
3126   default: break;
3127   case 'y':
3128     return Size <= 64;
3129   case 'f':
3130   case 't':
3131   case 'u':
3132     return Size <= 128;
3133   case 'x':
3134     // 256-bit ymm registers can be used if target supports AVX.
3135     return Size <= (SSELevel >= AVX ? 256U : 128U);
3136   }
3137 
3138   return true;
3139 }
3140 
3141 std::string
3142 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3143   switch (*Constraint) {
3144   case 'a': return std::string("{ax}");
3145   case 'b': return std::string("{bx}");
3146   case 'c': return std::string("{cx}");
3147   case 'd': return std::string("{dx}");
3148   case 'S': return std::string("{si}");
3149   case 'D': return std::string("{di}");
3150   case 'p': // address
3151     return std::string("im");
3152   case 't': // top of floating point stack.
3153     return std::string("{st}");
3154   case 'u': // second from top of floating point stack.
3155     return std::string("{st(1)}"); // second from top of floating point stack.
3156   default:
3157     return std::string(1, *Constraint);
3158   }
3159 }
3160 } // end anonymous namespace
3161 
3162 namespace {
3163 // X86-32 generic target
3164 class X86_32TargetInfo : public X86TargetInfo {
3165 public:
3166   X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3167     DoubleAlign = LongLongAlign = 32;
3168     LongDoubleWidth = 96;
3169     LongDoubleAlign = 32;
3170     SuitableAlign = 128;
3171     DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3172     SizeType = UnsignedInt;
3173     PtrDiffType = SignedInt;
3174     IntPtrType = SignedInt;
3175     RegParmMax = 3;
3176 
3177     // Use fpret for all types.
3178     RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3179                              (1 << TargetInfo::Double) |
3180                              (1 << TargetInfo::LongDouble));
3181 
3182     // x86-32 has atomics up to 8 bytes
3183     // FIXME: Check that we actually have cmpxchg8b before setting
3184     // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3185     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3186   }
3187   BuiltinVaListKind getBuiltinVaListKind() const override {
3188     return TargetInfo::CharPtrBuiltinVaList;
3189   }
3190 
3191   int getEHDataRegisterNumber(unsigned RegNo) const override {
3192     if (RegNo == 0) return 0;
3193     if (RegNo == 1) return 2;
3194     return -1;
3195   }
3196   bool validateOperandSize(StringRef Constraint,
3197                            unsigned Size) const override {
3198     switch (Constraint[0]) {
3199     default: break;
3200     case 'R':
3201     case 'q':
3202     case 'Q':
3203     case 'a':
3204     case 'b':
3205     case 'c':
3206     case 'd':
3207     case 'S':
3208     case 'D':
3209       return Size <= 32;
3210     case 'A':
3211       return Size <= 64;
3212     }
3213 
3214     return X86TargetInfo::validateOperandSize(Constraint, Size);
3215   }
3216 };
3217 } // end anonymous namespace
3218 
3219 namespace {
3220 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3221 public:
3222   NetBSDI386TargetInfo(const llvm::Triple &Triple)
3223       : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3224 
3225   unsigned getFloatEvalMethod() const override {
3226     unsigned Major, Minor, Micro;
3227     getTriple().getOSVersion(Major, Minor, Micro);
3228     // New NetBSD uses the default rounding mode.
3229     if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3230       return X86_32TargetInfo::getFloatEvalMethod();
3231     // NetBSD before 6.99.26 defaults to "double" rounding.
3232     return 1;
3233   }
3234 };
3235 } // end anonymous namespace
3236 
3237 namespace {
3238 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3239 public:
3240   OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3241       : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3242     SizeType = UnsignedLong;
3243     IntPtrType = SignedLong;
3244     PtrDiffType = SignedLong;
3245   }
3246 };
3247 } // end anonymous namespace
3248 
3249 namespace {
3250 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3251 public:
3252   BitrigI386TargetInfo(const llvm::Triple &Triple)
3253       : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3254     SizeType = UnsignedLong;
3255     IntPtrType = SignedLong;
3256     PtrDiffType = SignedLong;
3257   }
3258 };
3259 } // end anonymous namespace
3260 
3261 namespace {
3262 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3263 public:
3264   DarwinI386TargetInfo(const llvm::Triple &Triple)
3265       : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3266     LongDoubleWidth = 128;
3267     LongDoubleAlign = 128;
3268     SuitableAlign = 128;
3269     MaxVectorAlign = 256;
3270     SizeType = UnsignedLong;
3271     IntPtrType = SignedLong;
3272     DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3273     HasAlignMac68kSupport = true;
3274   }
3275 
3276 };
3277 } // end anonymous namespace
3278 
3279 namespace {
3280 // x86-32 Windows target
3281 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3282 public:
3283   WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3284       : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3285     WCharType = UnsignedShort;
3286     DoubleAlign = LongLongAlign = 64;
3287     DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3288   }
3289   void getTargetDefines(const LangOptions &Opts,
3290                         MacroBuilder &Builder) const override {
3291     WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3292   }
3293 };
3294 
3295 // x86-32 Windows Visual Studio target
3296 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3297 public:
3298   MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3299       : WindowsX86_32TargetInfo(Triple) {
3300     LongDoubleWidth = LongDoubleAlign = 64;
3301     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3302   }
3303   void getTargetDefines(const LangOptions &Opts,
3304                         MacroBuilder &Builder) const override {
3305     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3306     WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3307     // The value of the following reflects processor type.
3308     // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3309     // We lost the original triple, so we use the default.
3310     Builder.defineMacro("_M_IX86", "600");
3311   }
3312 };
3313 } // end anonymous namespace
3314 
3315 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3316   Builder.defineMacro("__MSVCRT__");
3317   Builder.defineMacro("__MINGW32__");
3318 
3319   // Mingw defines __declspec(a) to __attribute__((a)).  Clang supports
3320   // __declspec natively under -fms-extensions, but we define a no-op __declspec
3321   // macro anyway for pre-processor compatibility.
3322   if (Opts.MicrosoftExt)
3323     Builder.defineMacro("__declspec", "__declspec");
3324   else
3325     Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3326 
3327   if (!Opts.MicrosoftExt) {
3328     // Provide macros for all the calling convention keywords.  Provide both
3329     // single and double underscore prefixed variants.  These are available on
3330     // x64 as well as x86, even though they have no effect.
3331     const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3332     for (const char *CC : CCs) {
3333       std::string GCCSpelling = "__attribute__((__";
3334       GCCSpelling += CC;
3335       GCCSpelling += "__))";
3336       Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3337       Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3338     }
3339   }
3340 }
3341 
3342 namespace {
3343 // x86-32 MinGW target
3344 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3345 public:
3346   MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3347       : WindowsX86_32TargetInfo(Triple) {}
3348   void getTargetDefines(const LangOptions &Opts,
3349                         MacroBuilder &Builder) const override {
3350     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3351     DefineStd(Builder, "WIN32", Opts);
3352     DefineStd(Builder, "WINNT", Opts);
3353     Builder.defineMacro("_X86_");
3354     addMinGWDefines(Opts, Builder);
3355   }
3356 };
3357 } // end anonymous namespace
3358 
3359 namespace {
3360 // x86-32 Cygwin target
3361 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3362 public:
3363   CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3364       : X86_32TargetInfo(Triple) {
3365     TLSSupported = false;
3366     WCharType = UnsignedShort;
3367     DoubleAlign = LongLongAlign = 64;
3368     DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3369   }
3370   void getTargetDefines(const LangOptions &Opts,
3371                         MacroBuilder &Builder) const override {
3372     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3373     Builder.defineMacro("_X86_");
3374     Builder.defineMacro("__CYGWIN__");
3375     Builder.defineMacro("__CYGWIN32__");
3376     DefineStd(Builder, "unix", Opts);
3377     if (Opts.CPlusPlus)
3378       Builder.defineMacro("_GNU_SOURCE");
3379   }
3380 };
3381 } // end anonymous namespace
3382 
3383 namespace {
3384 // x86-32 Haiku target
3385 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3386 public:
3387   HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3388     SizeType = UnsignedLong;
3389     IntPtrType = SignedLong;
3390     PtrDiffType = SignedLong;
3391     ProcessIDType = SignedLong;
3392     this->UserLabelPrefix = "";
3393     this->TLSSupported = false;
3394   }
3395   void getTargetDefines(const LangOptions &Opts,
3396                         MacroBuilder &Builder) const override {
3397     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3398     Builder.defineMacro("__INTEL__");
3399     Builder.defineMacro("__HAIKU__");
3400   }
3401 };
3402 } // end anonymous namespace
3403 
3404 // RTEMS Target
3405 template<typename Target>
3406 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3407 protected:
3408   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3409                     MacroBuilder &Builder) const override {
3410     // RTEMS defines; list based off of gcc output
3411 
3412     Builder.defineMacro("__rtems__");
3413     Builder.defineMacro("__ELF__");
3414   }
3415 
3416 public:
3417   RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3418     this->UserLabelPrefix = "";
3419 
3420     switch (Triple.getArch()) {
3421     default:
3422     case llvm::Triple::x86:
3423       // this->MCountName = ".mcount";
3424       break;
3425     case llvm::Triple::mips:
3426     case llvm::Triple::mipsel:
3427     case llvm::Triple::ppc:
3428     case llvm::Triple::ppc64:
3429     case llvm::Triple::ppc64le:
3430       // this->MCountName = "_mcount";
3431       break;
3432     case llvm::Triple::arm:
3433       // this->MCountName = "__mcount";
3434       break;
3435     }
3436   }
3437 };
3438 
3439 namespace {
3440 // x86-32 RTEMS target
3441 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3442 public:
3443   RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3444     SizeType = UnsignedLong;
3445     IntPtrType = SignedLong;
3446     PtrDiffType = SignedLong;
3447     this->UserLabelPrefix = "";
3448   }
3449   void getTargetDefines(const LangOptions &Opts,
3450                         MacroBuilder &Builder) const override {
3451     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3452     Builder.defineMacro("__INTEL__");
3453     Builder.defineMacro("__rtems__");
3454   }
3455 };
3456 } // end anonymous namespace
3457 
3458 namespace {
3459 // x86-64 generic target
3460 class X86_64TargetInfo : public X86TargetInfo {
3461 public:
3462   X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3463     const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3464     LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3465     LongDoubleWidth = 128;
3466     LongDoubleAlign = 128;
3467     LargeArrayMinWidth = 128;
3468     LargeArrayAlign = 128;
3469     SuitableAlign = 128;
3470     SizeType    = IsX32 ? UnsignedInt      : UnsignedLong;
3471     PtrDiffType = IsX32 ? SignedInt        : SignedLong;
3472     IntPtrType  = IsX32 ? SignedInt        : SignedLong;
3473     IntMaxType  = IsX32 ? SignedLongLong   : SignedLong;
3474     Int64Type   = IsX32 ? SignedLongLong   : SignedLong;
3475     RegParmMax = 6;
3476 
3477     DescriptionString = (IsX32)
3478                             ? "e-m:e-" "p:32:32-" "i64:64-f80:128-n8:16:32:64-S128"
3479                             : "e-m:e-"            "i64:64-f80:128-n8:16:32:64-S128";
3480 
3481     // Use fpret only for long double.
3482     RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3483 
3484     // Use fp2ret for _Complex long double.
3485     ComplexLongDoubleUsesFP2Ret = true;
3486 
3487     // x86-64 has atomics up to 16 bytes.
3488     MaxAtomicPromoteWidth = 128;
3489     MaxAtomicInlineWidth = 128;
3490   }
3491   BuiltinVaListKind getBuiltinVaListKind() const override {
3492     return TargetInfo::X86_64ABIBuiltinVaList;
3493   }
3494 
3495   int getEHDataRegisterNumber(unsigned RegNo) const override {
3496     if (RegNo == 0) return 0;
3497     if (RegNo == 1) return 1;
3498     return -1;
3499   }
3500 
3501   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3502     return (CC == CC_C ||
3503             CC == CC_IntelOclBicc ||
3504             CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3505   }
3506 
3507   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3508     return CC_C;
3509   }
3510 
3511   // for x32 we need it here explicitly
3512   bool hasInt128Type() const override { return true; }
3513 };
3514 } // end anonymous namespace
3515 
3516 namespace {
3517 // x86-64 Windows target
3518 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3519 public:
3520   WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3521       : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3522     WCharType = UnsignedShort;
3523     LongWidth = LongAlign = 32;
3524     DoubleAlign = LongLongAlign = 64;
3525     IntMaxType = SignedLongLong;
3526     Int64Type = SignedLongLong;
3527     SizeType = UnsignedLongLong;
3528     PtrDiffType = SignedLongLong;
3529     IntPtrType = SignedLongLong;
3530     this->UserLabelPrefix = "";
3531   }
3532   void getTargetDefines(const LangOptions &Opts,
3533                                 MacroBuilder &Builder) const override {
3534     WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3535     Builder.defineMacro("_WIN64");
3536   }
3537   BuiltinVaListKind getBuiltinVaListKind() const override {
3538     return TargetInfo::CharPtrBuiltinVaList;
3539   }
3540   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3541     return (CC == CC_C ||
3542             CC == CC_IntelOclBicc ||
3543             CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
3544   }
3545 };
3546 } // end anonymous namespace
3547 
3548 namespace {
3549 // x86-64 Windows Visual Studio target
3550 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3551 public:
3552   MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3553       : WindowsX86_64TargetInfo(Triple) {
3554     LongDoubleWidth = LongDoubleAlign = 64;
3555     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3556   }
3557   void getTargetDefines(const LangOptions &Opts,
3558                         MacroBuilder &Builder) const override {
3559     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3560     WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3561     Builder.defineMacro("_M_X64");
3562     Builder.defineMacro("_M_AMD64");
3563   }
3564 };
3565 } // end anonymous namespace
3566 
3567 namespace {
3568 // x86-64 MinGW target
3569 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3570 public:
3571   MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3572       : WindowsX86_64TargetInfo(Triple) {}
3573   void getTargetDefines(const LangOptions &Opts,
3574                         MacroBuilder &Builder) const override {
3575     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3576     DefineStd(Builder, "WIN64", Opts);
3577     Builder.defineMacro("__MINGW64__");
3578     addMinGWDefines(Opts, Builder);
3579   }
3580 };
3581 } // end anonymous namespace
3582 
3583 namespace {
3584 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3585 public:
3586   DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3587       : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3588     Int64Type = SignedLongLong;
3589     MaxVectorAlign = 256;
3590     // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3591     llvm::Triple T = llvm::Triple(Triple);
3592     if (T.isiOS())
3593       UseSignedCharForObjCBool = false;
3594     DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3595   }
3596 };
3597 } // end anonymous namespace
3598 
3599 namespace {
3600 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3601 public:
3602   OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3603       : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3604     IntMaxType = SignedLongLong;
3605     Int64Type = SignedLongLong;
3606   }
3607 };
3608 } // end anonymous namespace
3609 
3610 namespace {
3611 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3612 public:
3613   BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3614       : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3615     IntMaxType = SignedLongLong;
3616     Int64Type = SignedLongLong;
3617   }
3618 };
3619 }
3620 
3621 
3622 namespace {
3623 class ARMTargetInfo : public TargetInfo {
3624   // Possible FPU choices.
3625   enum FPUMode {
3626     VFP2FPU = (1 << 0),
3627     VFP3FPU = (1 << 1),
3628     VFP4FPU = (1 << 2),
3629     NeonFPU = (1 << 3),
3630     FPARMV8 = (1 << 4)
3631   };
3632 
3633   // Possible HWDiv features.
3634   enum HWDivMode {
3635     HWDivThumb = (1 << 0),
3636     HWDivARM = (1 << 1)
3637   };
3638 
3639   static bool FPUModeIsVFP(FPUMode Mode) {
3640     return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3641   }
3642 
3643   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3644   static const char * const GCCRegNames[];
3645 
3646   std::string ABI, CPU;
3647 
3648   enum {
3649     FP_Default,
3650     FP_VFP,
3651     FP_Neon
3652   } FPMath;
3653 
3654   unsigned FPU : 5;
3655 
3656   unsigned IsAAPCS : 1;
3657   unsigned IsThumb : 1;
3658   unsigned HWDiv : 2;
3659 
3660   // Initialized via features.
3661   unsigned SoftFloat : 1;
3662   unsigned SoftFloatABI : 1;
3663 
3664   unsigned CRC : 1;
3665   unsigned Crypto : 1;
3666 
3667   // ACLE 6.5.1 Hardware floating point
3668   enum {
3669     HW_FP_HP = (1 << 1), /// half (16-bit)
3670     HW_FP_SP = (1 << 2), /// single (32-bit)
3671     HW_FP_DP = (1 << 3), /// double (64-bit)
3672   };
3673   uint32_t HW_FP;
3674 
3675   static const Builtin::Info BuiltinInfo[];
3676 
3677   static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3678     StringRef ArchName = T.getArchName();
3679     if (T.getArch() == llvm::Triple::arm ||
3680         T.getArch() == llvm::Triple::armeb) {
3681       StringRef VersionStr;
3682       if (ArchName.startswith("armv"))
3683         VersionStr = ArchName.substr(4, 1);
3684       else if (ArchName.startswith("armebv"))
3685         VersionStr = ArchName.substr(6, 1);
3686       else
3687         return false;
3688       unsigned Version;
3689       if (VersionStr.getAsInteger(10, Version))
3690         return false;
3691       return Version >= 6;
3692     }
3693     assert(T.getArch() == llvm::Triple::thumb ||
3694            T.getArch() == llvm::Triple::thumbeb);
3695     StringRef VersionStr;
3696     if (ArchName.startswith("thumbv"))
3697       VersionStr = ArchName.substr(6, 1);
3698     else if (ArchName.startswith("thumbebv"))
3699       VersionStr = ArchName.substr(8, 1);
3700     else
3701       return false;
3702     unsigned Version;
3703     if (VersionStr.getAsInteger(10, Version))
3704       return false;
3705     return Version >= 7;
3706   }
3707 
3708   void setABIAAPCS() {
3709     IsAAPCS = true;
3710 
3711     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
3712     const llvm::Triple &T = getTriple();
3713 
3714     // size_t is unsigned long on MachO-derived environments and NetBSD.
3715     if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD)
3716       SizeType = UnsignedLong;
3717     else
3718       SizeType = UnsignedInt;
3719 
3720     switch (T.getOS()) {
3721     case llvm::Triple::NetBSD:
3722       WCharType = SignedInt;
3723       break;
3724     case llvm::Triple::Win32:
3725       WCharType = UnsignedShort;
3726       break;
3727     case llvm::Triple::Linux:
3728     default:
3729       // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3730       WCharType = UnsignedInt;
3731       break;
3732     }
3733 
3734     UseBitFieldTypeAlignment = true;
3735 
3736     ZeroLengthBitfieldBoundary = 0;
3737 
3738     // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3739     // so set preferred for small types to 32.
3740     if (T.isOSBinFormatMachO()) {
3741       DescriptionString =
3742           BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3743                     : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3744     } else if (T.isOSWindows()) {
3745       // FIXME: this is invalid for WindowsCE
3746       assert(!BigEndian && "Windows on ARM does not support big endian");
3747       DescriptionString = "e"
3748                           "-m:e"
3749                           "-p:32:32"
3750                           "-i64:64"
3751                           "-v128:64:128"
3752                           "-a:0:32"
3753                           "-n32"
3754                           "-S64";
3755     } else {
3756       DescriptionString =
3757           BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3758                     : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3759     }
3760 
3761     // FIXME: Enumerated types are variable width in straight AAPCS.
3762   }
3763 
3764   void setABIAPCS() {
3765     const llvm::Triple &T = getTriple();
3766 
3767     IsAAPCS = false;
3768 
3769     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3770 
3771     // size_t is unsigned int on FreeBSD.
3772     if (T.getOS() == llvm::Triple::FreeBSD)
3773       SizeType = UnsignedInt;
3774     else
3775       SizeType = UnsignedLong;
3776 
3777     // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3778     WCharType = SignedInt;
3779 
3780     // Do not respect the alignment of bit-field types when laying out
3781     // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3782     UseBitFieldTypeAlignment = false;
3783 
3784     /// gcc forces the alignment to 4 bytes, regardless of the type of the
3785     /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3786     /// gcc.
3787     ZeroLengthBitfieldBoundary = 32;
3788 
3789     if (T.isOSBinFormatMachO())
3790       DescriptionString =
3791           BigEndian
3792               ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3793               : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3794     else
3795       DescriptionString =
3796           BigEndian
3797               ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3798               : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3799 
3800     // FIXME: Override "preferred align" for double and long long.
3801   }
3802 
3803 public:
3804   ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
3805       : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
3806         IsAAPCS(true), HW_FP(0) {
3807     BigEndian = IsBigEndian;
3808 
3809     switch (getTriple().getOS()) {
3810     case llvm::Triple::NetBSD:
3811       PtrDiffType = SignedLong;
3812       break;
3813     default:
3814       PtrDiffType = SignedInt;
3815       break;
3816     }
3817 
3818     // {} in inline assembly are neon specifiers, not assembly variant
3819     // specifiers.
3820     NoAsmVariants = true;
3821 
3822     // FIXME: Should we just treat this as a feature?
3823     IsThumb = getTriple().getArchName().startswith("thumb");
3824 
3825     setABI("aapcs-linux");
3826 
3827     // ARM targets default to using the ARM C++ ABI.
3828     TheCXXABI.set(TargetCXXABI::GenericARM);
3829 
3830     // ARM has atomics up to 8 bytes
3831     MaxAtomicPromoteWidth = 64;
3832     if (shouldUseInlineAtomic(getTriple()))
3833       MaxAtomicInlineWidth = 64;
3834 
3835     // Do force alignment of members that follow zero length bitfields.  If
3836     // the alignment of the zero-length bitfield is greater than the member
3837     // that follows it, `bar', `bar' will be aligned as the  type of the
3838     // zero length bitfield.
3839     UseZeroLengthBitfieldAlignment = true;
3840   }
3841   StringRef getABI() const override { return ABI; }
3842   bool setABI(const std::string &Name) override {
3843     ABI = Name;
3844 
3845     // The defaults (above) are for AAPCS, check if we need to change them.
3846     //
3847     // FIXME: We need support for -meabi... we could just mangle it into the
3848     // name.
3849     if (Name == "apcs-gnu") {
3850       setABIAPCS();
3851       return true;
3852     }
3853     if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
3854       setABIAAPCS();
3855       return true;
3856     }
3857     return false;
3858   }
3859 
3860   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
3861     if (IsAAPCS)
3862       Features["aapcs"] = true;
3863     else
3864       Features["apcs"] = true;
3865 
3866     StringRef ArchName = getTriple().getArchName();
3867     if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3868       Features["vfp2"] = true;
3869     else if (CPU == "cortex-a8" || CPU == "cortex-a9" ||
3870              CPU == "cortex-a9-mp") {
3871       Features["vfp3"] = true;
3872       Features["neon"] = true;
3873     }
3874     else if (CPU == "cortex-a5") {
3875       Features["vfp4"] = true;
3876       Features["neon"] = true;
3877     } else if (CPU == "swift" || CPU == "cortex-a7" ||
3878                CPU == "cortex-a12" || CPU == "cortex-a15" ||
3879                CPU == "cortex-a17" || CPU == "krait") {
3880       Features["vfp4"] = true;
3881       Features["neon"] = true;
3882       Features["hwdiv"] = true;
3883       Features["hwdiv-arm"] = true;
3884     } else if (CPU == "cyclone") {
3885       Features["v8fp"] = true;
3886       Features["neon"] = true;
3887       Features["hwdiv"] = true;
3888       Features["hwdiv-arm"] = true;
3889     } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
3890       Features["fp-armv8"] = true;
3891       Features["neon"] = true;
3892       Features["hwdiv"] = true;
3893       Features["hwdiv-arm"] = true;
3894       Features["crc"] = true;
3895       Features["crypto"] = true;
3896     } else if (CPU == "cortex-r5" ||
3897                // Enable the hwdiv extension for all v8a AArch32 cores by
3898                // default.
3899                ArchName == "armv8a" || ArchName == "armv8" ||
3900                ArchName == "armebv8a" || ArchName == "armebv8" ||
3901                ArchName == "thumbv8a" || ArchName == "thumbv8" ||
3902                ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
3903       Features["hwdiv"] = true;
3904       Features["hwdiv-arm"] = true;
3905     } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7") {
3906       Features["hwdiv"] = true;
3907     }
3908   }
3909 
3910   bool handleTargetFeatures(std::vector<std::string> &Features,
3911                             DiagnosticsEngine &Diags) override {
3912     FPU = 0;
3913     CRC = 0;
3914     Crypto = 0;
3915     SoftFloat = SoftFloatABI = false;
3916     HWDiv = 0;
3917 
3918     for (const auto &Feature : Features) {
3919       if (Feature == "+soft-float") {
3920         SoftFloat = true;
3921       } else if (Feature == "+soft-float-abi") {
3922         SoftFloatABI = true;
3923       } else if (Feature == "+vfp2") {
3924         FPU |= VFP2FPU;
3925         HW_FP = HW_FP_SP | HW_FP_DP;
3926       } else if (Feature == "+vfp3") {
3927         FPU |= VFP3FPU;
3928         HW_FP = HW_FP_SP | HW_FP_DP;
3929       } else if (Feature == "+vfp4") {
3930         FPU |= VFP4FPU;
3931         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
3932       } else if (Feature == "+fp-armv8") {
3933         FPU |= FPARMV8;
3934         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
3935       } else if (Feature == "+neon") {
3936         FPU |= NeonFPU;
3937         HW_FP = HW_FP_SP | HW_FP_DP;
3938       } else if (Feature == "+hwdiv") {
3939         HWDiv |= HWDivThumb;
3940       } else if (Feature == "+hwdiv-arm") {
3941         HWDiv |= HWDivARM;
3942       } else if (Feature == "+crc") {
3943         CRC = 1;
3944       } else if (Feature == "+crypto") {
3945         Crypto = 1;
3946       } else if (Feature == "+fp-only-sp") {
3947         HW_FP &= ~HW_FP_DP;
3948       }
3949     }
3950 
3951     if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
3952       Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
3953       return false;
3954     }
3955 
3956     if (FPMath == FP_Neon)
3957       Features.push_back("+neonfp");
3958     else if (FPMath == FP_VFP)
3959       Features.push_back("-neonfp");
3960 
3961     // Remove front-end specific options which the backend handles differently.
3962     const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" };
3963     for (const auto &FEFeature : FrontEndFeatures) {
3964       auto Feature = std::find(Features.begin(), Features.end(), FEFeature);
3965       if (Feature != Features.end())
3966         Features.erase(Feature);
3967     }
3968 
3969     return true;
3970   }
3971 
3972   bool hasFeature(StringRef Feature) const override {
3973     return llvm::StringSwitch<bool>(Feature)
3974         .Case("arm", true)
3975         .Case("softfloat", SoftFloat)
3976         .Case("thumb", IsThumb)
3977         .Case("neon", (FPU & NeonFPU) && !SoftFloat)
3978         .Case("hwdiv", HWDiv & HWDivThumb)
3979         .Case("hwdiv-arm", HWDiv & HWDivARM)
3980         .Default(false);
3981   }
3982   // FIXME: Should we actually have some table instead of these switches?
3983   static const char *getCPUDefineSuffix(StringRef Name) {
3984     return llvm::StringSwitch<const char*>(Name)
3985       .Cases("arm8", "arm810", "4")
3986       .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3987       .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3988       .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3989       .Case("ep9312", "4T")
3990       .Cases("arm10tdmi", "arm1020t", "5T")
3991       .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3992       .Case("arm926ej-s", "5TEJ")
3993       .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3994       .Cases("xscale", "iwmmxt", "5TE")
3995       .Case("arm1136j-s", "6J")
3996       .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3997       .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3998       .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3999       .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A")
4000       .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", "7A")
4001       .Cases("cortex-r4", "cortex-r5", "7R")
4002       .Case("swift", "7S")
4003       .Case("cyclone", "8A")
4004       .Case("cortex-m3", "7M")
4005       .Cases("cortex-m4", "cortex-m7", "7EM")
4006       .Case("cortex-m0", "6M")
4007       .Cases("cortex-a53", "cortex-a57", "8A")
4008       .Default(nullptr);
4009   }
4010   static const char *getCPUProfile(StringRef Name) {
4011     return llvm::StringSwitch<const char*>(Name)
4012       .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
4013       .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", "A")
4014       .Cases("cortex-a53", "cortex-a57", "A")
4015       .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M")
4016       .Cases("cortex-r4", "cortex-r5", "R")
4017       .Default("");
4018   }
4019   bool setCPU(const std::string &Name) override {
4020     if (!getCPUDefineSuffix(Name))
4021       return false;
4022 
4023     // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4024     StringRef Profile = getCPUProfile(Name);
4025     if (Profile == "M" && MaxAtomicInlineWidth) {
4026       MaxAtomicPromoteWidth = 32;
4027       MaxAtomicInlineWidth = 32;
4028     }
4029 
4030     CPU = Name;
4031     return true;
4032   }
4033   bool setFPMath(StringRef Name) override;
4034   bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4035                      unsigned CPUArchVer) const {
4036     return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4037            (CPUArch.find('M') != StringRef::npos);
4038   }
4039   bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4040                       unsigned CPUArchVer) const {
4041     // We check both CPUArchVer and ArchName because when only triple is
4042     // specified, the default CPU is arm1136j-s.
4043     return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4044            ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4045   }
4046   void getTargetDefines(const LangOptions &Opts,
4047                         MacroBuilder &Builder) const override {
4048     // Target identification.
4049     Builder.defineMacro("__arm");
4050     Builder.defineMacro("__arm__");
4051 
4052     // Target properties.
4053     Builder.defineMacro("__REGISTER_PREFIX__", "");
4054 
4055     StringRef CPUArch = getCPUDefineSuffix(CPU);
4056     unsigned int CPUArchVer;
4057     if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4058       llvm_unreachable("Invalid char for architecture version number");
4059     Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4060 
4061     // ACLE 6.4.1 ARM/Thumb instruction set architecture
4062     StringRef CPUProfile = getCPUProfile(CPU);
4063     StringRef ArchName = getTriple().getArchName();
4064 
4065     // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4066     Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4067     if (CPUArch[0] >= '8') {
4068       Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4069       Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4070     }
4071 
4072     // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
4073     // is not defined for the M-profile.
4074     // NOTE that the deffault profile is assumed to be 'A'
4075     if (CPUProfile.empty() || CPUProfile != "M")
4076       Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4077 
4078     // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4079     // Thumb ISA (including v6-M).  It is set to 2 if the core supports the
4080     // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4081     if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4082       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4083     else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4084       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4085 
4086     // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4087     // instruction set such as ARM or Thumb.
4088     Builder.defineMacro("__ARM_32BIT_STATE", "1");
4089 
4090     // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4091 
4092     // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4093     if (!CPUProfile.empty())
4094       Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4095 
4096     // ACLE 6.5.1 Hardware Floating Point
4097     if (HW_FP)
4098       Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4099 
4100     // ACLE predefines.
4101     Builder.defineMacro("__ARM_ACLE", "200");
4102 
4103     // Subtarget options.
4104 
4105     // FIXME: It's more complicated than this and we don't really support
4106     // interworking.
4107     // Windows on ARM does not "support" interworking
4108     if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4109       Builder.defineMacro("__THUMB_INTERWORK__");
4110 
4111     if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4112       // Embedded targets on Darwin follow AAPCS, but not EABI.
4113       // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4114       if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4115         Builder.defineMacro("__ARM_EABI__");
4116       Builder.defineMacro("__ARM_PCS", "1");
4117 
4118       if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4119         Builder.defineMacro("__ARM_PCS_VFP", "1");
4120     }
4121 
4122     if (SoftFloat)
4123       Builder.defineMacro("__SOFTFP__");
4124 
4125     if (CPU == "xscale")
4126       Builder.defineMacro("__XSCALE__");
4127 
4128     if (IsThumb) {
4129       Builder.defineMacro("__THUMBEL__");
4130       Builder.defineMacro("__thumb__");
4131       if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4132         Builder.defineMacro("__thumb2__");
4133     }
4134     if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4135       Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4136 
4137     // Note, this is always on in gcc, even though it doesn't make sense.
4138     Builder.defineMacro("__APCS_32__");
4139 
4140     if (FPUModeIsVFP((FPUMode) FPU)) {
4141       Builder.defineMacro("__VFP_FP__");
4142       if (FPU & VFP2FPU)
4143         Builder.defineMacro("__ARM_VFPV2__");
4144       if (FPU & VFP3FPU)
4145         Builder.defineMacro("__ARM_VFPV3__");
4146       if (FPU & VFP4FPU)
4147         Builder.defineMacro("__ARM_VFPV4__");
4148     }
4149 
4150     // This only gets set when Neon instructions are actually available, unlike
4151     // the VFP define, hence the soft float and arch check. This is subtly
4152     // different from gcc, we follow the intent which was that it should be set
4153     // when Neon instructions are actually available.
4154     if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4155       Builder.defineMacro("__ARM_NEON");
4156       Builder.defineMacro("__ARM_NEON__");
4157     }
4158 
4159     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4160                         Opts.ShortWChar ? "2" : "4");
4161 
4162     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4163                         Opts.ShortEnums ? "1" : "4");
4164 
4165     if (CRC)
4166       Builder.defineMacro("__ARM_FEATURE_CRC32");
4167 
4168     if (Crypto)
4169       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4170 
4171     if (CPUArchVer >= 6 && CPUArch != "6M") {
4172       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4173       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4174       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4175       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4176     }
4177   }
4178   void getTargetBuiltins(const Builtin::Info *&Records,
4179                          unsigned &NumRecords) const override {
4180     Records = BuiltinInfo;
4181     NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4182   }
4183   bool isCLZForZeroUndef() const override { return false; }
4184   BuiltinVaListKind getBuiltinVaListKind() const override {
4185     return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4186   }
4187   void getGCCRegNames(const char * const *&Names,
4188                       unsigned &NumNames) const override;
4189   void getGCCRegAliases(const GCCRegAlias *&Aliases,
4190                         unsigned &NumAliases) const override;
4191   bool validateAsmConstraint(const char *&Name,
4192                              TargetInfo::ConstraintInfo &Info) const override {
4193     switch (*Name) {
4194     default: break;
4195     case 'l': // r0-r7
4196     case 'h': // r8-r15
4197     case 'w': // VFP Floating point register single precision
4198     case 'P': // VFP Floating point register double precision
4199       Info.setAllowsRegister();
4200       return true;
4201     case 'Q': // A memory address that is a single base register.
4202       Info.setAllowsMemory();
4203       return true;
4204     case 'U': // a memory reference...
4205       switch (Name[1]) {
4206       case 'q': // ...ARMV4 ldrsb
4207       case 'v': // ...VFP load/store (reg+constant offset)
4208       case 'y': // ...iWMMXt load/store
4209       case 't': // address valid for load/store opaque types wider
4210                 // than 128-bits
4211       case 'n': // valid address for Neon doubleword vector load/store
4212       case 'm': // valid address for Neon element and structure load/store
4213       case 's': // valid address for non-offset loads/stores of quad-word
4214                 // values in four ARM registers
4215         Info.setAllowsMemory();
4216         Name++;
4217         return true;
4218       }
4219     }
4220     return false;
4221   }
4222   std::string convertConstraint(const char *&Constraint) const override {
4223     std::string R;
4224     switch (*Constraint) {
4225     case 'U':   // Two-character constraint; add "^" hint for later parsing.
4226       R = std::string("^") + std::string(Constraint, 2);
4227       Constraint++;
4228       break;
4229     case 'p': // 'p' should be translated to 'r' by default.
4230       R = std::string("r");
4231       break;
4232     default:
4233       return std::string(1, *Constraint);
4234     }
4235     return R;
4236   }
4237   bool
4238   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4239                              std::string &SuggestedModifier) const override {
4240     bool isOutput = (Constraint[0] == '=');
4241     bool isInOut = (Constraint[0] == '+');
4242 
4243     // Strip off constraint modifiers.
4244     while (Constraint[0] == '=' ||
4245            Constraint[0] == '+' ||
4246            Constraint[0] == '&')
4247       Constraint = Constraint.substr(1);
4248 
4249     switch (Constraint[0]) {
4250     default: break;
4251     case 'r': {
4252       switch (Modifier) {
4253       default:
4254         return (isInOut || isOutput || Size <= 64);
4255       case 'q':
4256         // A register of size 32 cannot fit a vector type.
4257         return false;
4258       }
4259     }
4260     }
4261 
4262     return true;
4263   }
4264   const char *getClobbers() const override {
4265     // FIXME: Is this really right?
4266     return "";
4267   }
4268 
4269   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4270     return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4271   }
4272 
4273   int getEHDataRegisterNumber(unsigned RegNo) const override {
4274     if (RegNo == 0) return 0;
4275     if (RegNo == 1) return 1;
4276     return -1;
4277   }
4278 };
4279 
4280 bool ARMTargetInfo::setFPMath(StringRef Name) {
4281   if (Name == "neon") {
4282     FPMath = FP_Neon;
4283     return true;
4284   } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4285              Name == "vfp4") {
4286     FPMath = FP_VFP;
4287     return true;
4288   }
4289   return false;
4290 }
4291 
4292 const char * const ARMTargetInfo::GCCRegNames[] = {
4293   // Integer registers
4294   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4295   "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4296 
4297   // Float registers
4298   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4299   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4300   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4301   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4302 
4303   // Double registers
4304   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4305   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4306   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4307   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4308 
4309   // Quad registers
4310   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4311   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4312 };
4313 
4314 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4315                                    unsigned &NumNames) const {
4316   Names = GCCRegNames;
4317   NumNames = llvm::array_lengthof(GCCRegNames);
4318 }
4319 
4320 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4321   { { "a1" }, "r0" },
4322   { { "a2" }, "r1" },
4323   { { "a3" }, "r2" },
4324   { { "a4" }, "r3" },
4325   { { "v1" }, "r4" },
4326   { { "v2" }, "r5" },
4327   { { "v3" }, "r6" },
4328   { { "v4" }, "r7" },
4329   { { "v5" }, "r8" },
4330   { { "v6", "rfp" }, "r9" },
4331   { { "sl" }, "r10" },
4332   { { "fp" }, "r11" },
4333   { { "ip" }, "r12" },
4334   { { "r13" }, "sp" },
4335   { { "r14" }, "lr" },
4336   { { "r15" }, "pc" },
4337   // The S, D and Q registers overlap, but aren't really aliases; we
4338   // don't want to substitute one of these for a different-sized one.
4339 };
4340 
4341 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4342                                        unsigned &NumAliases) const {
4343   Aliases = GCCRegAliases;
4344   NumAliases = llvm::array_lengthof(GCCRegAliases);
4345 }
4346 
4347 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4348 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4349 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4350                                               ALL_LANGUAGES },
4351 #include "clang/Basic/BuiltinsNEON.def"
4352 
4353 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4354 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4355 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4356                                               ALL_LANGUAGES },
4357 #include "clang/Basic/BuiltinsARM.def"
4358 };
4359 
4360 class ARMleTargetInfo : public ARMTargetInfo {
4361 public:
4362   ARMleTargetInfo(const llvm::Triple &Triple)
4363     : ARMTargetInfo(Triple, false) { }
4364   virtual void getTargetDefines(const LangOptions &Opts,
4365                                 MacroBuilder &Builder) const {
4366     Builder.defineMacro("__ARMEL__");
4367     ARMTargetInfo::getTargetDefines(Opts, Builder);
4368   }
4369 };
4370 
4371 class ARMbeTargetInfo : public ARMTargetInfo {
4372 public:
4373   ARMbeTargetInfo(const llvm::Triple &Triple)
4374     : ARMTargetInfo(Triple, true) { }
4375   virtual void getTargetDefines(const LangOptions &Opts,
4376                                 MacroBuilder &Builder) const {
4377     Builder.defineMacro("__ARMEB__");
4378     Builder.defineMacro("__ARM_BIG_ENDIAN");
4379     ARMTargetInfo::getTargetDefines(Opts, Builder);
4380   }
4381 };
4382 } // end anonymous namespace.
4383 
4384 namespace {
4385 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4386   const llvm::Triple Triple;
4387 public:
4388   WindowsARMTargetInfo(const llvm::Triple &Triple)
4389     : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4390     TLSSupported = false;
4391     WCharType = UnsignedShort;
4392     SizeType = UnsignedInt;
4393     UserLabelPrefix = "";
4394   }
4395   void getVisualStudioDefines(const LangOptions &Opts,
4396                               MacroBuilder &Builder) const {
4397     WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4398 
4399     // FIXME: this is invalid for WindowsCE
4400     Builder.defineMacro("_M_ARM_NT", "1");
4401     Builder.defineMacro("_M_ARMT", "_M_ARM");
4402     Builder.defineMacro("_M_THUMB", "_M_ARM");
4403 
4404     assert((Triple.getArch() == llvm::Triple::arm ||
4405             Triple.getArch() == llvm::Triple::thumb) &&
4406            "invalid architecture for Windows ARM target info");
4407     unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4408     Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4409 
4410     // TODO map the complete set of values
4411     // 31: VFPv3 40: VFPv4
4412     Builder.defineMacro("_M_ARM_FP", "31");
4413   }
4414   BuiltinVaListKind getBuiltinVaListKind() const override {
4415     return TargetInfo::CharPtrBuiltinVaList;
4416   }
4417 };
4418 
4419 // Windows ARM + Itanium C++ ABI Target
4420 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4421 public:
4422   ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4423     : WindowsARMTargetInfo(Triple) {
4424     TheCXXABI.set(TargetCXXABI::GenericARM);
4425   }
4426 
4427   void getTargetDefines(const LangOptions &Opts,
4428                         MacroBuilder &Builder) const override {
4429     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4430 
4431     if (Opts.MSVCCompat)
4432       WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4433   }
4434 };
4435 
4436 // Windows ARM, MS (C++) ABI
4437 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4438 public:
4439   MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4440     : WindowsARMTargetInfo(Triple) {
4441     TheCXXABI.set(TargetCXXABI::Microsoft);
4442   }
4443 
4444   void getTargetDefines(const LangOptions &Opts,
4445                         MacroBuilder &Builder) const override {
4446     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4447     WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4448   }
4449 };
4450 }
4451 
4452 
4453 namespace {
4454 class DarwinARMTargetInfo :
4455   public DarwinTargetInfo<ARMleTargetInfo> {
4456 protected:
4457   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4458                     MacroBuilder &Builder) const override {
4459     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4460   }
4461 
4462 public:
4463   DarwinARMTargetInfo(const llvm::Triple &Triple)
4464       : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4465     HasAlignMac68kSupport = true;
4466     // iOS always has 64-bit atomic instructions.
4467     // FIXME: This should be based off of the target features in ARMleTargetInfo.
4468     MaxAtomicInlineWidth = 64;
4469 
4470     // Darwin on iOS uses a variant of the ARM C++ ABI.
4471     TheCXXABI.set(TargetCXXABI::iOS);
4472   }
4473 };
4474 } // end anonymous namespace.
4475 
4476 
4477 namespace {
4478 class AArch64TargetInfo : public TargetInfo {
4479   virtual void setDescriptionString() = 0;
4480   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4481   static const char *const GCCRegNames[];
4482 
4483   enum FPUModeEnum {
4484     FPUMode,
4485     NeonMode
4486   };
4487 
4488   unsigned FPU;
4489   unsigned CRC;
4490   unsigned Crypto;
4491 
4492   static const Builtin::Info BuiltinInfo[];
4493 
4494   std::string ABI;
4495 
4496 public:
4497   AArch64TargetInfo(const llvm::Triple &Triple)
4498       : TargetInfo(Triple), ABI("aapcs") {
4499 
4500     if (getTriple().getOS() == llvm::Triple::NetBSD) {
4501       WCharType = SignedInt;
4502 
4503       // NetBSD apparently prefers consistency across ARM targets to consistency
4504       // across 64-bit targets.
4505       Int64Type = SignedLongLong;
4506       IntMaxType = SignedLongLong;
4507     } else {
4508       WCharType = UnsignedInt;
4509       Int64Type = SignedLong;
4510       IntMaxType = SignedLong;
4511     }
4512 
4513     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4514     MaxVectorAlign = 128;
4515     RegParmMax = 8;
4516     MaxAtomicInlineWidth = 128;
4517     MaxAtomicPromoteWidth = 128;
4518 
4519     LongDoubleWidth = LongDoubleAlign = 128;
4520     LongDoubleFormat = &llvm::APFloat::IEEEquad;
4521 
4522     // {} in inline assembly are neon specifiers, not assembly variant
4523     // specifiers.
4524     NoAsmVariants = true;
4525 
4526     // AArch64 targets default to using the ARM C++ ABI.
4527     TheCXXABI.set(TargetCXXABI::GenericAArch64);
4528   }
4529 
4530   StringRef getABI() const override { return ABI; }
4531   virtual bool setABI(const std::string &Name) override {
4532     if (Name != "aapcs" && Name != "darwinpcs")
4533       return false;
4534 
4535     ABI = Name;
4536     return true;
4537   }
4538 
4539   virtual bool setCPU(const std::string &Name) override {
4540     bool CPUKnown = llvm::StringSwitch<bool>(Name)
4541                         .Case("generic", true)
4542                         .Cases("cortex-a53", "cortex-a57", true)
4543                         .Case("cyclone", true)
4544                         .Default(false);
4545     return CPUKnown;
4546   }
4547 
4548   virtual void getTargetDefines(const LangOptions &Opts,
4549                                 MacroBuilder &Builder) const  override {
4550     // Target identification.
4551     Builder.defineMacro("__aarch64__");
4552 
4553     // Target properties.
4554     Builder.defineMacro("_LP64");
4555     Builder.defineMacro("__LP64__");
4556 
4557     // ACLE predefines. Many can only have one possible value on v8 AArch64.
4558     Builder.defineMacro("__ARM_ACLE", "200");
4559     Builder.defineMacro("__ARM_ARCH", "8");
4560     Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4561 
4562     Builder.defineMacro("__ARM_64BIT_STATE");
4563     Builder.defineMacro("__ARM_PCS_AAPCS64");
4564     Builder.defineMacro("__ARM_ARCH_ISA_A64");
4565 
4566     Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4567     Builder.defineMacro("__ARM_FEATURE_CLZ");
4568     Builder.defineMacro("__ARM_FEATURE_FMA");
4569     Builder.defineMacro("__ARM_FEATURE_DIV");
4570     Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
4571     Builder.defineMacro("__ARM_FEATURE_DIV");  // For backwards compatibility
4572     Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4573     Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4574 
4575     Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4576 
4577     // 0xe implies support for half, single and double precision operations.
4578     Builder.defineMacro("__ARM_FP", "0xe");
4579 
4580     // PCS specifies this for SysV variants, which is all we support. Other ABIs
4581     // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4582     Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4583 
4584     if (Opts.FastMath || Opts.FiniteMathOnly)
4585       Builder.defineMacro("__ARM_FP_FAST");
4586 
4587     if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
4588       Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4589 
4590     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4591 
4592     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4593                         Opts.ShortEnums ? "1" : "4");
4594 
4595     if (FPU == NeonMode) {
4596       Builder.defineMacro("__ARM_NEON");
4597       // 64-bit NEON supports half, single and double precision operations.
4598       Builder.defineMacro("__ARM_NEON_FP", "0xe");
4599     }
4600 
4601     if (CRC)
4602       Builder.defineMacro("__ARM_FEATURE_CRC32");
4603 
4604     if (Crypto)
4605       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4606   }
4607 
4608   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4609                                  unsigned &NumRecords) const override {
4610     Records = BuiltinInfo;
4611     NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4612   }
4613 
4614   virtual bool hasFeature(StringRef Feature) const override {
4615     return Feature == "aarch64" ||
4616       Feature == "arm64" ||
4617       (Feature == "neon" && FPU == NeonMode);
4618   }
4619 
4620   bool handleTargetFeatures(std::vector<std::string> &Features,
4621                             DiagnosticsEngine &Diags) override {
4622     FPU = FPUMode;
4623     CRC = 0;
4624     Crypto = 0;
4625     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
4626       if (Features[i] == "+neon")
4627         FPU = NeonMode;
4628       if (Features[i] == "+crc")
4629         CRC = 1;
4630       if (Features[i] == "+crypto")
4631         Crypto = 1;
4632     }
4633 
4634     setDescriptionString();
4635 
4636     return true;
4637   }
4638 
4639   virtual bool isCLZForZeroUndef() const override { return false; }
4640 
4641   virtual BuiltinVaListKind getBuiltinVaListKind() const override {
4642     return TargetInfo::AArch64ABIBuiltinVaList;
4643   }
4644 
4645   virtual void getGCCRegNames(const char *const *&Names,
4646                               unsigned &NumNames) const override;
4647   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4648                                 unsigned &NumAliases) const override;
4649 
4650   virtual bool validateAsmConstraint(const char *&Name,
4651                                      TargetInfo::ConstraintInfo &Info) const override {
4652     switch (*Name) {
4653     default:
4654       return false;
4655     case 'w': // Floating point and SIMD registers (V0-V31)
4656       Info.setAllowsRegister();
4657       return true;
4658     case 'I': // Constant that can be used with an ADD instruction
4659     case 'J': // Constant that can be used with a SUB instruction
4660     case 'K': // Constant that can be used with a 32-bit logical instruction
4661     case 'L': // Constant that can be used with a 64-bit logical instruction
4662     case 'M': // Constant that can be used as a 32-bit MOV immediate
4663     case 'N': // Constant that can be used as a 64-bit MOV immediate
4664     case 'Y': // Floating point constant zero
4665     case 'Z': // Integer constant zero
4666       return true;
4667     case 'Q': // A memory reference with base register and no offset
4668       Info.setAllowsMemory();
4669       return true;
4670     case 'S': // A symbolic address
4671       Info.setAllowsRegister();
4672       return true;
4673     case 'U':
4674       // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
4675       // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
4676       // Usa: An absolute symbolic address
4677       // Ush: The high part (bits 32:12) of a pc-relative symbolic address
4678       llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
4679     case 'z': // Zero register, wzr or xzr
4680       Info.setAllowsRegister();
4681       return true;
4682     case 'x': // Floating point and SIMD registers (V0-V15)
4683       Info.setAllowsRegister();
4684       return true;
4685     }
4686     return false;
4687   }
4688 
4689   bool
4690   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4691                              std::string &SuggestedModifier) const override {
4692     // Strip off constraint modifiers.
4693     while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
4694       Constraint = Constraint.substr(1);
4695 
4696     switch (Constraint[0]) {
4697     default:
4698       return true;
4699     case 'z':
4700     case 'r': {
4701       switch (Modifier) {
4702       case 'x':
4703       case 'w':
4704         // For now assume that the person knows what they're
4705         // doing with the modifier.
4706         return true;
4707       default:
4708         // By default an 'r' constraint will be in the 'x'
4709         // registers.
4710         if (Size == 64)
4711           return true;
4712 
4713         SuggestedModifier = "w";
4714         return false;
4715       }
4716     }
4717     }
4718   }
4719 
4720   virtual const char *getClobbers() const override { return ""; }
4721 
4722   int getEHDataRegisterNumber(unsigned RegNo) const override {
4723     if (RegNo == 0)
4724       return 0;
4725     if (RegNo == 1)
4726       return 1;
4727     return -1;
4728   }
4729 };
4730 
4731 const char *const AArch64TargetInfo::GCCRegNames[] = {
4732   // 32-bit Integer registers
4733   "w0",  "w1",  "w2",  "w3",  "w4",  "w5",  "w6",  "w7",  "w8",  "w9",  "w10",
4734   "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
4735   "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
4736 
4737   // 64-bit Integer registers
4738   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",  "x8",  "x9",  "x10",
4739   "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
4740   "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp",  "lr",  "sp",
4741 
4742   // 32-bit floating point regsisters
4743   "s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",  "s8",  "s9",  "s10",
4744   "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
4745   "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4746 
4747   // 64-bit floating point regsisters
4748   "d0",  "d1",  "d2",  "d3",  "d4",  "d5",  "d6",  "d7",  "d8",  "d9",  "d10",
4749   "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
4750   "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4751 
4752   // Vector registers
4753   "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",  "v8",  "v9",  "v10",
4754   "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
4755   "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
4756 };
4757 
4758 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
4759                                      unsigned &NumNames) const {
4760   Names = GCCRegNames;
4761   NumNames = llvm::array_lengthof(GCCRegNames);
4762 }
4763 
4764 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
4765   { { "w31" }, "wsp" },
4766   { { "x29" }, "fp" },
4767   { { "x30" }, "lr" },
4768   { { "x31" }, "sp" },
4769   // The S/D/Q and W/X registers overlap, but aren't really aliases; we
4770   // don't want to substitute one of these for a different-sized one.
4771 };
4772 
4773 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4774                                        unsigned &NumAliases) const {
4775   Aliases = GCCRegAliases;
4776   NumAliases = llvm::array_lengthof(GCCRegAliases);
4777 }
4778 
4779 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
4780 #define BUILTIN(ID, TYPE, ATTRS)                                               \
4781   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4782 #include "clang/Basic/BuiltinsNEON.def"
4783 
4784 #define BUILTIN(ID, TYPE, ATTRS)                                               \
4785   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4786 #include "clang/Basic/BuiltinsAArch64.def"
4787 };
4788 
4789 class AArch64leTargetInfo : public AArch64TargetInfo {
4790   void setDescriptionString() override {
4791     if (getTriple().isOSBinFormatMachO())
4792       DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
4793     else
4794       DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
4795   }
4796 
4797 public:
4798   AArch64leTargetInfo(const llvm::Triple &Triple)
4799     : AArch64TargetInfo(Triple) {
4800     BigEndian = false;
4801     }
4802   void getTargetDefines(const LangOptions &Opts,
4803                         MacroBuilder &Builder) const override {
4804     Builder.defineMacro("__AARCH64EL__");
4805     AArch64TargetInfo::getTargetDefines(Opts, Builder);
4806   }
4807 };
4808 
4809 class AArch64beTargetInfo : public AArch64TargetInfo {
4810   void setDescriptionString() override {
4811     assert(!getTriple().isOSBinFormatMachO());
4812     DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
4813   }
4814 
4815 public:
4816   AArch64beTargetInfo(const llvm::Triple &Triple)
4817     : AArch64TargetInfo(Triple) { }
4818   void getTargetDefines(const LangOptions &Opts,
4819                         MacroBuilder &Builder) const override {
4820     Builder.defineMacro("__AARCH64EB__");
4821     Builder.defineMacro("__AARCH_BIG_ENDIAN");
4822     Builder.defineMacro("__ARM_BIG_ENDIAN");
4823     AArch64TargetInfo::getTargetDefines(Opts, Builder);
4824   }
4825 };
4826 } // end anonymous namespace.
4827 
4828 namespace {
4829 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
4830 protected:
4831   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4832                     MacroBuilder &Builder) const override {
4833     Builder.defineMacro("__AARCH64_SIMD__");
4834     Builder.defineMacro("__ARM64_ARCH_8__");
4835     Builder.defineMacro("__ARM_NEON__");
4836     Builder.defineMacro("__LITTLE_ENDIAN__");
4837     Builder.defineMacro("__REGISTER_PREFIX__", "");
4838     Builder.defineMacro("__arm64", "1");
4839     Builder.defineMacro("__arm64__", "1");
4840 
4841     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4842   }
4843 
4844 public:
4845   DarwinAArch64TargetInfo(const llvm::Triple &Triple)
4846       : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
4847     Int64Type = SignedLongLong;
4848     WCharType = SignedInt;
4849     UseSignedCharForObjCBool = false;
4850 
4851     LongDoubleWidth = LongDoubleAlign = 64;
4852     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4853 
4854     TheCXXABI.set(TargetCXXABI::iOS64);
4855   }
4856 
4857   virtual BuiltinVaListKind getBuiltinVaListKind() const override {
4858     return TargetInfo::CharPtrBuiltinVaList;
4859   }
4860 };
4861 } // end anonymous namespace
4862 
4863 namespace {
4864 // Hexagon abstract base class
4865 class HexagonTargetInfo : public TargetInfo {
4866   static const Builtin::Info BuiltinInfo[];
4867   static const char * const GCCRegNames[];
4868   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4869   std::string CPU;
4870 public:
4871   HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4872     BigEndian = false;
4873     DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
4874 
4875     // {} in inline assembly are packet specifiers, not assembly variant
4876     // specifiers.
4877     NoAsmVariants = true;
4878   }
4879 
4880   void getTargetBuiltins(const Builtin::Info *&Records,
4881                          unsigned &NumRecords) const override {
4882     Records = BuiltinInfo;
4883     NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
4884   }
4885 
4886   bool validateAsmConstraint(const char *&Name,
4887                              TargetInfo::ConstraintInfo &Info) const override {
4888     return true;
4889   }
4890 
4891   void getTargetDefines(const LangOptions &Opts,
4892                         MacroBuilder &Builder) const override;
4893 
4894   bool hasFeature(StringRef Feature) const override {
4895     return Feature == "hexagon";
4896   }
4897 
4898   BuiltinVaListKind getBuiltinVaListKind() const override {
4899     return TargetInfo::CharPtrBuiltinVaList;
4900   }
4901   void getGCCRegNames(const char * const *&Names,
4902                       unsigned &NumNames) const override;
4903   void getGCCRegAliases(const GCCRegAlias *&Aliases,
4904                         unsigned &NumAliases) const override;
4905   const char *getClobbers() const override {
4906     return "";
4907   }
4908 
4909   static const char *getHexagonCPUSuffix(StringRef Name) {
4910     return llvm::StringSwitch<const char*>(Name)
4911       .Case("hexagonv4", "4")
4912       .Case("hexagonv5", "5")
4913       .Default(nullptr);
4914   }
4915 
4916   bool setCPU(const std::string &Name) override {
4917     if (!getHexagonCPUSuffix(Name))
4918       return false;
4919 
4920     CPU = Name;
4921     return true;
4922   }
4923 };
4924 
4925 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4926                                 MacroBuilder &Builder) const {
4927   Builder.defineMacro("qdsp6");
4928   Builder.defineMacro("__qdsp6", "1");
4929   Builder.defineMacro("__qdsp6__", "1");
4930 
4931   Builder.defineMacro("hexagon");
4932   Builder.defineMacro("__hexagon", "1");
4933   Builder.defineMacro("__hexagon__", "1");
4934 
4935   if(CPU == "hexagonv1") {
4936     Builder.defineMacro("__HEXAGON_V1__");
4937     Builder.defineMacro("__HEXAGON_ARCH__", "1");
4938     if(Opts.HexagonQdsp6Compat) {
4939       Builder.defineMacro("__QDSP6_V1__");
4940       Builder.defineMacro("__QDSP6_ARCH__", "1");
4941     }
4942   }
4943   else if(CPU == "hexagonv2") {
4944     Builder.defineMacro("__HEXAGON_V2__");
4945     Builder.defineMacro("__HEXAGON_ARCH__", "2");
4946     if(Opts.HexagonQdsp6Compat) {
4947       Builder.defineMacro("__QDSP6_V2__");
4948       Builder.defineMacro("__QDSP6_ARCH__", "2");
4949     }
4950   }
4951   else if(CPU == "hexagonv3") {
4952     Builder.defineMacro("__HEXAGON_V3__");
4953     Builder.defineMacro("__HEXAGON_ARCH__", "3");
4954     if(Opts.HexagonQdsp6Compat) {
4955       Builder.defineMacro("__QDSP6_V3__");
4956       Builder.defineMacro("__QDSP6_ARCH__", "3");
4957     }
4958   }
4959   else if(CPU == "hexagonv4") {
4960     Builder.defineMacro("__HEXAGON_V4__");
4961     Builder.defineMacro("__HEXAGON_ARCH__", "4");
4962     if(Opts.HexagonQdsp6Compat) {
4963       Builder.defineMacro("__QDSP6_V4__");
4964       Builder.defineMacro("__QDSP6_ARCH__", "4");
4965     }
4966   }
4967   else if(CPU == "hexagonv5") {
4968     Builder.defineMacro("__HEXAGON_V5__");
4969     Builder.defineMacro("__HEXAGON_ARCH__", "5");
4970     if(Opts.HexagonQdsp6Compat) {
4971       Builder.defineMacro("__QDSP6_V5__");
4972       Builder.defineMacro("__QDSP6_ARCH__", "5");
4973     }
4974   }
4975 }
4976 
4977 const char * const HexagonTargetInfo::GCCRegNames[] = {
4978   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4979   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4980   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4981   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4982   "p0", "p1", "p2", "p3",
4983   "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4984 };
4985 
4986 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4987                                    unsigned &NumNames) const {
4988   Names = GCCRegNames;
4989   NumNames = llvm::array_lengthof(GCCRegNames);
4990 }
4991 
4992 
4993 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4994   { { "sp" }, "r29" },
4995   { { "fp" }, "r30" },
4996   { { "lr" }, "r31" },
4997  };
4998 
4999 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5000                                      unsigned &NumAliases) const {
5001   Aliases = GCCRegAliases;
5002   NumAliases = llvm::array_lengthof(GCCRegAliases);
5003 }
5004 
5005 
5006 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5007 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5008 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5009                                               ALL_LANGUAGES },
5010 #include "clang/Basic/BuiltinsHexagon.def"
5011 };
5012 }
5013 
5014 
5015 namespace {
5016 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5017 class SparcTargetInfo : public TargetInfo {
5018   static const TargetInfo::GCCRegAlias GCCRegAliases[];
5019   static const char * const GCCRegNames[];
5020   bool SoftFloat;
5021 public:
5022   SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
5023 
5024   bool handleTargetFeatures(std::vector<std::string> &Features,
5025                             DiagnosticsEngine &Diags) override {
5026     SoftFloat = false;
5027     for (unsigned i = 0, e = Features.size(); i != e; ++i)
5028       if (Features[i] == "+soft-float")
5029         SoftFloat = true;
5030     return true;
5031   }
5032   void getTargetDefines(const LangOptions &Opts,
5033                         MacroBuilder &Builder) const override {
5034     DefineStd(Builder, "sparc", Opts);
5035     Builder.defineMacro("__REGISTER_PREFIX__", "");
5036 
5037     if (SoftFloat)
5038       Builder.defineMacro("SOFT_FLOAT", "1");
5039   }
5040 
5041   bool hasFeature(StringRef Feature) const override {
5042     return llvm::StringSwitch<bool>(Feature)
5043              .Case("softfloat", SoftFloat)
5044              .Case("sparc", true)
5045              .Default(false);
5046   }
5047 
5048   void getTargetBuiltins(const Builtin::Info *&Records,
5049                          unsigned &NumRecords) const override {
5050     // FIXME: Implement!
5051   }
5052   BuiltinVaListKind getBuiltinVaListKind() const override {
5053     return TargetInfo::VoidPtrBuiltinVaList;
5054   }
5055   void getGCCRegNames(const char * const *&Names,
5056                       unsigned &NumNames) const override;
5057   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5058                         unsigned &NumAliases) const override;
5059   bool validateAsmConstraint(const char *&Name,
5060                              TargetInfo::ConstraintInfo &info) const override {
5061     // FIXME: Implement!
5062     return false;
5063   }
5064   const char *getClobbers() const override {
5065     // FIXME: Implement!
5066     return "";
5067   }
5068 };
5069 
5070 const char * const SparcTargetInfo::GCCRegNames[] = {
5071   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5072   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5073   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5074   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5075 };
5076 
5077 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5078                                      unsigned &NumNames) const {
5079   Names = GCCRegNames;
5080   NumNames = llvm::array_lengthof(GCCRegNames);
5081 }
5082 
5083 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5084   { { "g0" }, "r0" },
5085   { { "g1" }, "r1" },
5086   { { "g2" }, "r2" },
5087   { { "g3" }, "r3" },
5088   { { "g4" }, "r4" },
5089   { { "g5" }, "r5" },
5090   { { "g6" }, "r6" },
5091   { { "g7" }, "r7" },
5092   { { "o0" }, "r8" },
5093   { { "o1" }, "r9" },
5094   { { "o2" }, "r10" },
5095   { { "o3" }, "r11" },
5096   { { "o4" }, "r12" },
5097   { { "o5" }, "r13" },
5098   { { "o6", "sp" }, "r14" },
5099   { { "o7" }, "r15" },
5100   { { "l0" }, "r16" },
5101   { { "l1" }, "r17" },
5102   { { "l2" }, "r18" },
5103   { { "l3" }, "r19" },
5104   { { "l4" }, "r20" },
5105   { { "l5" }, "r21" },
5106   { { "l6" }, "r22" },
5107   { { "l7" }, "r23" },
5108   { { "i0" }, "r24" },
5109   { { "i1" }, "r25" },
5110   { { "i2" }, "r26" },
5111   { { "i3" }, "r27" },
5112   { { "i4" }, "r28" },
5113   { { "i5" }, "r29" },
5114   { { "i6", "fp" }, "r30" },
5115   { { "i7" }, "r31" },
5116 };
5117 
5118 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5119                                        unsigned &NumAliases) const {
5120   Aliases = GCCRegAliases;
5121   NumAliases = llvm::array_lengthof(GCCRegAliases);
5122 }
5123 
5124 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5125 class SparcV8TargetInfo : public SparcTargetInfo {
5126 public:
5127   SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5128     DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5129   }
5130 
5131   void getTargetDefines(const LangOptions &Opts,
5132                         MacroBuilder &Builder) const override {
5133     SparcTargetInfo::getTargetDefines(Opts, Builder);
5134     Builder.defineMacro("__sparcv8");
5135   }
5136 };
5137 
5138 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5139 class SparcV9TargetInfo : public SparcTargetInfo {
5140 public:
5141   SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5142     // FIXME: Support Sparc quad-precision long double?
5143     DescriptionString = "E-m:e-i64:64-n32:64-S128";
5144     // This is an LP64 platform.
5145     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5146 
5147     // OpenBSD uses long long for int64_t and intmax_t.
5148     if (getTriple().getOS() == llvm::Triple::OpenBSD)
5149       IntMaxType = SignedLongLong;
5150     else
5151       IntMaxType = SignedLong;
5152     Int64Type = IntMaxType;
5153 
5154     // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5155     // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5156     LongDoubleWidth = 128;
5157     LongDoubleAlign = 128;
5158     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5159     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5160   }
5161 
5162   void getTargetDefines(const LangOptions &Opts,
5163                         MacroBuilder &Builder) const override {
5164     SparcTargetInfo::getTargetDefines(Opts, Builder);
5165     Builder.defineMacro("__sparcv9");
5166     Builder.defineMacro("__arch64__");
5167     // Solaris doesn't need these variants, but the BSDs do.
5168     if (getTriple().getOS() != llvm::Triple::Solaris) {
5169       Builder.defineMacro("__sparc64__");
5170       Builder.defineMacro("__sparc_v9__");
5171       Builder.defineMacro("__sparcv9__");
5172     }
5173   }
5174 
5175   bool setCPU(const std::string &Name) override {
5176     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5177       .Case("v9", true)
5178       .Case("ultrasparc", true)
5179       .Case("ultrasparc3", true)
5180       .Case("niagara", true)
5181       .Case("niagara2", true)
5182       .Case("niagara3", true)
5183       .Case("niagara4", true)
5184       .Default(false);
5185 
5186     // No need to store the CPU yet.  There aren't any CPU-specific
5187     // macros to define.
5188     return CPUKnown;
5189   }
5190 };
5191 
5192 } // end anonymous namespace.
5193 
5194 namespace {
5195 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
5196 public:
5197   SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
5198       : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
5199     SizeType = UnsignedInt;
5200     PtrDiffType = SignedInt;
5201   }
5202 };
5203 } // end anonymous namespace.
5204 
5205 namespace {
5206 class SystemZTargetInfo : public TargetInfo {
5207   static const char *const GCCRegNames[];
5208 
5209 public:
5210   SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5211     TLSSupported = true;
5212     IntWidth = IntAlign = 32;
5213     LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5214     PointerWidth = PointerAlign = 64;
5215     LongDoubleWidth = 128;
5216     LongDoubleAlign = 64;
5217     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5218     MinGlobalAlign = 16;
5219     DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5220     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5221   }
5222   void getTargetDefines(const LangOptions &Opts,
5223                         MacroBuilder &Builder) const override {
5224     Builder.defineMacro("__s390__");
5225     Builder.defineMacro("__s390x__");
5226     Builder.defineMacro("__zarch__");
5227     Builder.defineMacro("__LONG_DOUBLE_128__");
5228   }
5229   void getTargetBuiltins(const Builtin::Info *&Records,
5230                          unsigned &NumRecords) const override {
5231     // FIXME: Implement.
5232     Records = nullptr;
5233     NumRecords = 0;
5234   }
5235 
5236   void getGCCRegNames(const char *const *&Names,
5237                       unsigned &NumNames) const override;
5238   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5239                         unsigned &NumAliases) const override {
5240     // No aliases.
5241     Aliases = nullptr;
5242     NumAliases = 0;
5243   }
5244   bool validateAsmConstraint(const char *&Name,
5245                              TargetInfo::ConstraintInfo &info) const override;
5246   const char *getClobbers() const override {
5247     // FIXME: Is this really right?
5248     return "";
5249   }
5250   BuiltinVaListKind getBuiltinVaListKind() const override {
5251     return TargetInfo::SystemZBuiltinVaList;
5252   }
5253   bool setCPU(const std::string &Name) override {
5254     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5255       .Case("z10", true)
5256       .Case("z196", true)
5257       .Case("zEC12", true)
5258       .Default(false);
5259 
5260     // No need to store the CPU yet.  There aren't any CPU-specific
5261     // macros to define.
5262     return CPUKnown;
5263   }
5264 };
5265 
5266 const char *const SystemZTargetInfo::GCCRegNames[] = {
5267   "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
5268   "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
5269   "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
5270   "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
5271 };
5272 
5273 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5274                                        unsigned &NumNames) const {
5275   Names = GCCRegNames;
5276   NumNames = llvm::array_lengthof(GCCRegNames);
5277 }
5278 
5279 bool SystemZTargetInfo::
5280 validateAsmConstraint(const char *&Name,
5281                       TargetInfo::ConstraintInfo &Info) const {
5282   switch (*Name) {
5283   default:
5284     return false;
5285 
5286   case 'a': // Address register
5287   case 'd': // Data register (equivalent to 'r')
5288   case 'f': // Floating-point register
5289     Info.setAllowsRegister();
5290     return true;
5291 
5292   case 'I': // Unsigned 8-bit constant
5293   case 'J': // Unsigned 12-bit constant
5294   case 'K': // Signed 16-bit constant
5295   case 'L': // Signed 20-bit displacement (on all targets we support)
5296   case 'M': // 0x7fffffff
5297     return true;
5298 
5299   case 'Q': // Memory with base and unsigned 12-bit displacement
5300   case 'R': // Likewise, plus an index
5301   case 'S': // Memory with base and signed 20-bit displacement
5302   case 'T': // Likewise, plus an index
5303     Info.setAllowsMemory();
5304     return true;
5305   }
5306 }
5307 }
5308 
5309 namespace {
5310   class MSP430TargetInfo : public TargetInfo {
5311     static const char * const GCCRegNames[];
5312   public:
5313     MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5314       BigEndian = false;
5315       TLSSupported = false;
5316       IntWidth = 16; IntAlign = 16;
5317       LongWidth = 32; LongLongWidth = 64;
5318       LongAlign = LongLongAlign = 16;
5319       PointerWidth = 16; PointerAlign = 16;
5320       SuitableAlign = 16;
5321       SizeType = UnsignedInt;
5322       IntMaxType = SignedLongLong;
5323       IntPtrType = SignedInt;
5324       PtrDiffType = SignedInt;
5325       SigAtomicType = SignedLong;
5326       DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5327     }
5328     void getTargetDefines(const LangOptions &Opts,
5329                           MacroBuilder &Builder) const override {
5330       Builder.defineMacro("MSP430");
5331       Builder.defineMacro("__MSP430__");
5332       // FIXME: defines for different 'flavours' of MCU
5333     }
5334     void getTargetBuiltins(const Builtin::Info *&Records,
5335                            unsigned &NumRecords) const override {
5336       // FIXME: Implement.
5337       Records = nullptr;
5338       NumRecords = 0;
5339     }
5340     bool hasFeature(StringRef Feature) const override {
5341       return Feature == "msp430";
5342     }
5343     void getGCCRegNames(const char * const *&Names,
5344                         unsigned &NumNames) const override;
5345     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5346                           unsigned &NumAliases) const override {
5347       // No aliases.
5348       Aliases = nullptr;
5349       NumAliases = 0;
5350     }
5351     bool validateAsmConstraint(const char *&Name,
5352                                TargetInfo::ConstraintInfo &info) const override {
5353       // No target constraints for now.
5354       return false;
5355     }
5356     const char *getClobbers() const override {
5357       // FIXME: Is this really right?
5358       return "";
5359     }
5360     BuiltinVaListKind getBuiltinVaListKind() const override {
5361       // FIXME: implement
5362       return TargetInfo::CharPtrBuiltinVaList;
5363    }
5364   };
5365 
5366   const char * const MSP430TargetInfo::GCCRegNames[] = {
5367     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5368     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5369   };
5370 
5371   void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5372                                         unsigned &NumNames) const {
5373     Names = GCCRegNames;
5374     NumNames = llvm::array_lengthof(GCCRegNames);
5375   }
5376 }
5377 
5378 namespace {
5379 
5380   // LLVM and Clang cannot be used directly to output native binaries for
5381   // target, but is used to compile C code to llvm bitcode with correct
5382   // type and alignment information.
5383   //
5384   // TCE uses the llvm bitcode as input and uses it for generating customized
5385   // target processor and program binary. TCE co-design environment is
5386   // publicly available in http://tce.cs.tut.fi
5387 
5388   static const unsigned TCEOpenCLAddrSpaceMap[] = {
5389       3, // opencl_global
5390       4, // opencl_local
5391       5, // opencl_constant
5392       0, // cuda_device
5393       0, // cuda_constant
5394       0  // cuda_shared
5395   };
5396 
5397   class TCETargetInfo : public TargetInfo{
5398   public:
5399     TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5400       TLSSupported = false;
5401       IntWidth = 32;
5402       LongWidth = LongLongWidth = 32;
5403       PointerWidth = 32;
5404       IntAlign = 32;
5405       LongAlign = LongLongAlign = 32;
5406       PointerAlign = 32;
5407       SuitableAlign = 32;
5408       SizeType = UnsignedInt;
5409       IntMaxType = SignedLong;
5410       IntPtrType = SignedInt;
5411       PtrDiffType = SignedInt;
5412       FloatWidth = 32;
5413       FloatAlign = 32;
5414       DoubleWidth = 32;
5415       DoubleAlign = 32;
5416       LongDoubleWidth = 32;
5417       LongDoubleAlign = 32;
5418       FloatFormat = &llvm::APFloat::IEEEsingle;
5419       DoubleFormat = &llvm::APFloat::IEEEsingle;
5420       LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5421       DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5422                           "-f64:32-v64:32-v128:32-a:0:32-n32";
5423       AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5424       UseAddrSpaceMapMangling = true;
5425     }
5426 
5427     void getTargetDefines(const LangOptions &Opts,
5428                           MacroBuilder &Builder) const override {
5429       DefineStd(Builder, "tce", Opts);
5430       Builder.defineMacro("__TCE__");
5431       Builder.defineMacro("__TCE_V1__");
5432     }
5433     bool hasFeature(StringRef Feature) const override {
5434       return Feature == "tce";
5435     }
5436 
5437     void getTargetBuiltins(const Builtin::Info *&Records,
5438                            unsigned &NumRecords) const override {}
5439     const char *getClobbers() const override {
5440       return "";
5441     }
5442     BuiltinVaListKind getBuiltinVaListKind() const override {
5443       return TargetInfo::VoidPtrBuiltinVaList;
5444     }
5445     void getGCCRegNames(const char * const *&Names,
5446                         unsigned &NumNames) const override {}
5447     bool validateAsmConstraint(const char *&Name,
5448                                TargetInfo::ConstraintInfo &info) const override{
5449       return true;
5450     }
5451     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5452                           unsigned &NumAliases) const override {}
5453   };
5454 }
5455 
5456 namespace {
5457 class MipsTargetInfoBase : public TargetInfo {
5458   virtual void setDescriptionString() = 0;
5459 
5460   static const Builtin::Info BuiltinInfo[];
5461   std::string CPU;
5462   bool IsMips16;
5463   bool IsMicromips;
5464   bool IsNan2008;
5465   bool IsSingleFloat;
5466   enum MipsFloatABI {
5467     HardFloat, SoftFloat
5468   } FloatABI;
5469   enum DspRevEnum {
5470     NoDSP, DSP1, DSP2
5471   } DspRev;
5472   bool HasMSA;
5473 
5474 protected:
5475   bool HasFP64;
5476   std::string ABI;
5477 
5478 public:
5479   MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5480                      const std::string &CPUStr)
5481       : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5482         IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
5483         DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {}
5484 
5485   bool isNaN2008Default() const {
5486     return CPU == "mips32r6" || CPU == "mips64r6";
5487   }
5488 
5489   bool isFP64Default() const {
5490     return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
5491   }
5492 
5493   StringRef getABI() const override { return ABI; }
5494   bool setCPU(const std::string &Name) override {
5495     bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
5496                     getTriple().getArch() == llvm::Triple::mipsel;
5497     CPU = Name;
5498     return llvm::StringSwitch<bool>(Name)
5499         .Case("mips1", IsMips32)
5500         .Case("mips2", IsMips32)
5501         .Case("mips3", true)
5502         .Case("mips4", true)
5503         .Case("mips5", true)
5504         .Case("mips32", IsMips32)
5505         .Case("mips32r2", IsMips32)
5506         .Case("mips32r6", IsMips32)
5507         .Case("mips64", true)
5508         .Case("mips64r2", true)
5509         .Case("mips64r6", true)
5510         .Case("octeon", true)
5511         .Default(false);
5512   }
5513   const std::string& getCPU() const { return CPU; }
5514   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5515     // The backend enables certain ABI's by default according to the
5516     // architecture.
5517     // Disable both possible defaults so that we don't end up with multiple
5518     // ABI's selected and trigger an assertion.
5519     Features["o32"] = false;
5520     Features["n64"] = false;
5521 
5522     Features[ABI] = true;
5523     if (CPU == "octeon")
5524       Features["mips64r2"] = Features["cnmips"] = true;
5525     else
5526       Features[CPU] = true;
5527   }
5528 
5529   void getTargetDefines(const LangOptions &Opts,
5530                         MacroBuilder &Builder) const override {
5531     Builder.defineMacro("__mips__");
5532     Builder.defineMacro("_mips");
5533     if (Opts.GNUMode)
5534       Builder.defineMacro("mips");
5535 
5536     Builder.defineMacro("__REGISTER_PREFIX__", "");
5537 
5538     switch (FloatABI) {
5539     case HardFloat:
5540       Builder.defineMacro("__mips_hard_float", Twine(1));
5541       break;
5542     case SoftFloat:
5543       Builder.defineMacro("__mips_soft_float", Twine(1));
5544       break;
5545     }
5546 
5547     if (IsSingleFloat)
5548       Builder.defineMacro("__mips_single_float", Twine(1));
5549 
5550     Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
5551     Builder.defineMacro("_MIPS_FPSET",
5552                         Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
5553 
5554     if (IsMips16)
5555       Builder.defineMacro("__mips16", Twine(1));
5556 
5557     if (IsMicromips)
5558       Builder.defineMacro("__mips_micromips", Twine(1));
5559 
5560     if (IsNan2008)
5561       Builder.defineMacro("__mips_nan2008", Twine(1));
5562 
5563     switch (DspRev) {
5564     default:
5565       break;
5566     case DSP1:
5567       Builder.defineMacro("__mips_dsp_rev", Twine(1));
5568       Builder.defineMacro("__mips_dsp", Twine(1));
5569       break;
5570     case DSP2:
5571       Builder.defineMacro("__mips_dsp_rev", Twine(2));
5572       Builder.defineMacro("__mips_dspr2", Twine(1));
5573       Builder.defineMacro("__mips_dsp", Twine(1));
5574       break;
5575     }
5576 
5577     if (HasMSA)
5578       Builder.defineMacro("__mips_msa", Twine(1));
5579 
5580     Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
5581     Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
5582     Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
5583 
5584     Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
5585     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
5586   }
5587 
5588   void getTargetBuiltins(const Builtin::Info *&Records,
5589                          unsigned &NumRecords) const override {
5590     Records = BuiltinInfo;
5591     NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
5592   }
5593   bool hasFeature(StringRef Feature) const override {
5594     return llvm::StringSwitch<bool>(Feature)
5595       .Case("mips", true)
5596       .Case("fp64", HasFP64)
5597       .Default(false);
5598   }
5599   BuiltinVaListKind getBuiltinVaListKind() const override {
5600     return TargetInfo::VoidPtrBuiltinVaList;
5601   }
5602   void getGCCRegNames(const char * const *&Names,
5603                       unsigned &NumNames) const override {
5604     static const char *const GCCRegNames[] = {
5605       // CPU register names
5606       // Must match second column of GCCRegAliases
5607       "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
5608       "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
5609       "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
5610       "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
5611       // Floating point register names
5612       "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
5613       "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
5614       "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
5615       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
5616       // Hi/lo and condition register names
5617       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
5618       "$fcc5","$fcc6","$fcc7",
5619       // MSA register names
5620       "$w0",  "$w1",  "$w2",  "$w3",  "$w4",  "$w5",  "$w6",  "$w7",
5621       "$w8",  "$w9",  "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
5622       "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
5623       "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
5624       // MSA control register names
5625       "$msair",      "$msacsr", "$msaaccess", "$msasave", "$msamodify",
5626       "$msarequest", "$msamap", "$msaunmap"
5627     };
5628     Names = GCCRegNames;
5629     NumNames = llvm::array_lengthof(GCCRegNames);
5630   }
5631   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5632                         unsigned &NumAliases) const override = 0;
5633   bool validateAsmConstraint(const char *&Name,
5634                              TargetInfo::ConstraintInfo &Info) const override {
5635     switch (*Name) {
5636     default:
5637       return false;
5638 
5639     case 'r': // CPU registers.
5640     case 'd': // Equivalent to "r" unless generating MIPS16 code.
5641     case 'y': // Equivalent to "r", backward compatibility only.
5642     case 'f': // floating-point registers.
5643     case 'c': // $25 for indirect jumps
5644     case 'l': // lo register
5645     case 'x': // hilo register pair
5646       Info.setAllowsRegister();
5647       return true;
5648     case 'R': // An address that can be used in a non-macro load or store
5649       Info.setAllowsMemory();
5650       return true;
5651     }
5652   }
5653 
5654   const char *getClobbers() const override {
5655     // FIXME: Implement!
5656     return "";
5657   }
5658 
5659   bool handleTargetFeatures(std::vector<std::string> &Features,
5660                             DiagnosticsEngine &Diags) override {
5661     IsMips16 = false;
5662     IsMicromips = false;
5663     IsNan2008 = isNaN2008Default();
5664     IsSingleFloat = false;
5665     FloatABI = HardFloat;
5666     DspRev = NoDSP;
5667     HasFP64 = isFP64Default();
5668 
5669     for (std::vector<std::string>::iterator it = Features.begin(),
5670          ie = Features.end(); it != ie; ++it) {
5671       if (*it == "+single-float")
5672         IsSingleFloat = true;
5673       else if (*it == "+soft-float")
5674         FloatABI = SoftFloat;
5675       else if (*it == "+mips16")
5676         IsMips16 = true;
5677       else if (*it == "+micromips")
5678         IsMicromips = true;
5679       else if (*it == "+dsp")
5680         DspRev = std::max(DspRev, DSP1);
5681       else if (*it == "+dspr2")
5682         DspRev = std::max(DspRev, DSP2);
5683       else if (*it == "+msa")
5684         HasMSA = true;
5685       else if (*it == "+fp64")
5686         HasFP64 = true;
5687       else if (*it == "-fp64")
5688         HasFP64 = false;
5689       else if (*it == "+nan2008")
5690         IsNan2008 = true;
5691       else if (*it == "-nan2008")
5692         IsNan2008 = false;
5693     }
5694 
5695     // Remove front-end specific options.
5696     std::vector<std::string>::iterator it =
5697       std::find(Features.begin(), Features.end(), "+soft-float");
5698     if (it != Features.end())
5699       Features.erase(it);
5700 
5701     setDescriptionString();
5702 
5703     return true;
5704   }
5705 
5706   int getEHDataRegisterNumber(unsigned RegNo) const override {
5707     if (RegNo == 0) return 4;
5708     if (RegNo == 1) return 5;
5709     return -1;
5710   }
5711 
5712   bool isCLZForZeroUndef() const override { return false; }
5713 };
5714 
5715 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
5716 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5717 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5718                                               ALL_LANGUAGES },
5719 #include "clang/Basic/BuiltinsMips.def"
5720 };
5721 
5722 class Mips32TargetInfoBase : public MipsTargetInfoBase {
5723 public:
5724   Mips32TargetInfoBase(const llvm::Triple &Triple)
5725       : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
5726     SizeType = UnsignedInt;
5727     PtrDiffType = SignedInt;
5728     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
5729   }
5730   bool setABI(const std::string &Name) override {
5731     if (Name == "o32" || Name == "eabi") {
5732       ABI = Name;
5733       return true;
5734     }
5735     return false;
5736   }
5737   void getTargetDefines(const LangOptions &Opts,
5738                         MacroBuilder &Builder) const override {
5739     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5740 
5741     Builder.defineMacro("__mips", "32");
5742     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
5743 
5744     const std::string& CPUStr = getCPU();
5745     if (CPUStr == "mips32")
5746       Builder.defineMacro("__mips_isa_rev", "1");
5747     else if (CPUStr == "mips32r2")
5748       Builder.defineMacro("__mips_isa_rev", "2");
5749 
5750     if (ABI == "o32") {
5751       Builder.defineMacro("__mips_o32");
5752       Builder.defineMacro("_ABIO32", "1");
5753       Builder.defineMacro("_MIPS_SIM", "_ABIO32");
5754     }
5755     else if (ABI == "eabi")
5756       Builder.defineMacro("__mips_eabi");
5757     else
5758       llvm_unreachable("Invalid ABI for Mips32.");
5759   }
5760   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5761                         unsigned &NumAliases) const override {
5762     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5763       { { "at" },  "$1" },
5764       { { "v0" },  "$2" },
5765       { { "v1" },  "$3" },
5766       { { "a0" },  "$4" },
5767       { { "a1" },  "$5" },
5768       { { "a2" },  "$6" },
5769       { { "a3" },  "$7" },
5770       { { "t0" },  "$8" },
5771       { { "t1" },  "$9" },
5772       { { "t2" }, "$10" },
5773       { { "t3" }, "$11" },
5774       { { "t4" }, "$12" },
5775       { { "t5" }, "$13" },
5776       { { "t6" }, "$14" },
5777       { { "t7" }, "$15" },
5778       { { "s0" }, "$16" },
5779       { { "s1" }, "$17" },
5780       { { "s2" }, "$18" },
5781       { { "s3" }, "$19" },
5782       { { "s4" }, "$20" },
5783       { { "s5" }, "$21" },
5784       { { "s6" }, "$22" },
5785       { { "s7" }, "$23" },
5786       { { "t8" }, "$24" },
5787       { { "t9" }, "$25" },
5788       { { "k0" }, "$26" },
5789       { { "k1" }, "$27" },
5790       { { "gp" }, "$28" },
5791       { { "sp","$sp" }, "$29" },
5792       { { "fp","$fp" }, "$30" },
5793       { { "ra" }, "$31" }
5794     };
5795     Aliases = GCCRegAliases;
5796     NumAliases = llvm::array_lengthof(GCCRegAliases);
5797   }
5798 };
5799 
5800 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
5801   void setDescriptionString() override {
5802     DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
5803   }
5804 
5805 public:
5806   Mips32EBTargetInfo(const llvm::Triple &Triple)
5807       : Mips32TargetInfoBase(Triple) {
5808   }
5809   void getTargetDefines(const LangOptions &Opts,
5810                         MacroBuilder &Builder) const override {
5811     DefineStd(Builder, "MIPSEB", Opts);
5812     Builder.defineMacro("_MIPSEB");
5813     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5814   }
5815 };
5816 
5817 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
5818   void setDescriptionString() override {
5819     DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
5820   }
5821 
5822 public:
5823   Mips32ELTargetInfo(const llvm::Triple &Triple)
5824       : Mips32TargetInfoBase(Triple) {
5825     BigEndian = false;
5826   }
5827   void getTargetDefines(const LangOptions &Opts,
5828                         MacroBuilder &Builder) const override {
5829     DefineStd(Builder, "MIPSEL", Opts);
5830     Builder.defineMacro("_MIPSEL");
5831     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5832   }
5833 };
5834 
5835 class Mips64TargetInfoBase : public MipsTargetInfoBase {
5836 public:
5837   Mips64TargetInfoBase(const llvm::Triple &Triple)
5838       : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
5839     LongDoubleWidth = LongDoubleAlign = 128;
5840     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5841     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
5842       LongDoubleWidth = LongDoubleAlign = 64;
5843       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5844     }
5845     setN64ABITypes();
5846     SuitableAlign = 128;
5847     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5848   }
5849 
5850   void setN64ABITypes() {
5851     LongWidth = LongAlign = 64;
5852     PointerWidth = PointerAlign = 64;
5853     SizeType = UnsignedLong;
5854     PtrDiffType = SignedLong;
5855   }
5856 
5857   void setN32ABITypes() {
5858     LongWidth = LongAlign = 32;
5859     PointerWidth = PointerAlign = 32;
5860     SizeType = UnsignedInt;
5861     PtrDiffType = SignedInt;
5862   }
5863 
5864   bool setABI(const std::string &Name) override {
5865     if (Name == "n32") {
5866       setN32ABITypes();
5867       ABI = Name;
5868       return true;
5869     }
5870     if (Name == "n64") {
5871       setN64ABITypes();
5872       ABI = Name;
5873       return true;
5874     }
5875     return false;
5876   }
5877 
5878   void getTargetDefines(const LangOptions &Opts,
5879                         MacroBuilder &Builder) const override {
5880     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5881 
5882     Builder.defineMacro("__mips", "64");
5883     Builder.defineMacro("__mips64");
5884     Builder.defineMacro("__mips64__");
5885     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
5886 
5887     const std::string& CPUStr = getCPU();
5888     if (CPUStr == "mips64")
5889       Builder.defineMacro("__mips_isa_rev", "1");
5890     else if (CPUStr == "mips64r2")
5891       Builder.defineMacro("__mips_isa_rev", "2");
5892 
5893     if (ABI == "n32") {
5894       Builder.defineMacro("__mips_n32");
5895       Builder.defineMacro("_ABIN32", "2");
5896       Builder.defineMacro("_MIPS_SIM", "_ABIN32");
5897     }
5898     else if (ABI == "n64") {
5899       Builder.defineMacro("__mips_n64");
5900       Builder.defineMacro("_ABI64", "3");
5901       Builder.defineMacro("_MIPS_SIM", "_ABI64");
5902     }
5903     else
5904       llvm_unreachable("Invalid ABI for Mips64.");
5905   }
5906   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5907                         unsigned &NumAliases) const override {
5908     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5909       { { "at" },  "$1" },
5910       { { "v0" },  "$2" },
5911       { { "v1" },  "$3" },
5912       { { "a0" },  "$4" },
5913       { { "a1" },  "$5" },
5914       { { "a2" },  "$6" },
5915       { { "a3" },  "$7" },
5916       { { "a4" },  "$8" },
5917       { { "a5" },  "$9" },
5918       { { "a6" }, "$10" },
5919       { { "a7" }, "$11" },
5920       { { "t0" }, "$12" },
5921       { { "t1" }, "$13" },
5922       { { "t2" }, "$14" },
5923       { { "t3" }, "$15" },
5924       { { "s0" }, "$16" },
5925       { { "s1" }, "$17" },
5926       { { "s2" }, "$18" },
5927       { { "s3" }, "$19" },
5928       { { "s4" }, "$20" },
5929       { { "s5" }, "$21" },
5930       { { "s6" }, "$22" },
5931       { { "s7" }, "$23" },
5932       { { "t8" }, "$24" },
5933       { { "t9" }, "$25" },
5934       { { "k0" }, "$26" },
5935       { { "k1" }, "$27" },
5936       { { "gp" }, "$28" },
5937       { { "sp","$sp" }, "$29" },
5938       { { "fp","$fp" }, "$30" },
5939       { { "ra" }, "$31" }
5940     };
5941     Aliases = GCCRegAliases;
5942     NumAliases = llvm::array_lengthof(GCCRegAliases);
5943   }
5944 
5945   bool hasInt128Type() const override { return true; }
5946 };
5947 
5948 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
5949   void setDescriptionString() override {
5950     if (ABI == "n32")
5951       DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5952     else
5953       DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5954 
5955   }
5956 
5957 public:
5958   Mips64EBTargetInfo(const llvm::Triple &Triple)
5959       : Mips64TargetInfoBase(Triple) {}
5960   void getTargetDefines(const LangOptions &Opts,
5961                         MacroBuilder &Builder) const override {
5962     DefineStd(Builder, "MIPSEB", Opts);
5963     Builder.defineMacro("_MIPSEB");
5964     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5965   }
5966 };
5967 
5968 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
5969   void setDescriptionString() override {
5970     if (ABI == "n32")
5971       DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5972     else
5973       DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5974   }
5975 public:
5976   Mips64ELTargetInfo(const llvm::Triple &Triple)
5977       : Mips64TargetInfoBase(Triple) {
5978     // Default ABI is n64.
5979     BigEndian = false;
5980   }
5981   void getTargetDefines(const LangOptions &Opts,
5982                         MacroBuilder &Builder) const override {
5983     DefineStd(Builder, "MIPSEL", Opts);
5984     Builder.defineMacro("_MIPSEL");
5985     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5986   }
5987 };
5988 } // end anonymous namespace.
5989 
5990 namespace {
5991 class PNaClTargetInfo : public TargetInfo {
5992 public:
5993   PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5994     BigEndian = false;
5995     this->UserLabelPrefix = "";
5996     this->LongAlign = 32;
5997     this->LongWidth = 32;
5998     this->PointerAlign = 32;
5999     this->PointerWidth = 32;
6000     this->IntMaxType = TargetInfo::SignedLongLong;
6001     this->Int64Type = TargetInfo::SignedLongLong;
6002     this->DoubleAlign = 64;
6003     this->LongDoubleWidth = 64;
6004     this->LongDoubleAlign = 64;
6005     this->SizeType = TargetInfo::UnsignedInt;
6006     this->PtrDiffType = TargetInfo::SignedInt;
6007     this->IntPtrType = TargetInfo::SignedInt;
6008     this->RegParmMax = 0; // Disallow regparm
6009   }
6010 
6011   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6012   }
6013   void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6014     Builder.defineMacro("__le32__");
6015     Builder.defineMacro("__pnacl__");
6016   }
6017   void getTargetDefines(const LangOptions &Opts,
6018                         MacroBuilder &Builder) const override {
6019     getArchDefines(Opts, Builder);
6020   }
6021   bool hasFeature(StringRef Feature) const override {
6022     return Feature == "pnacl";
6023   }
6024   void getTargetBuiltins(const Builtin::Info *&Records,
6025                          unsigned &NumRecords) const override {
6026   }
6027   BuiltinVaListKind getBuiltinVaListKind() const override {
6028     return TargetInfo::PNaClABIBuiltinVaList;
6029   }
6030   void getGCCRegNames(const char * const *&Names,
6031                       unsigned &NumNames) const override;
6032   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6033                         unsigned &NumAliases) const override;
6034   bool validateAsmConstraint(const char *&Name,
6035                              TargetInfo::ConstraintInfo &Info) const override {
6036     return false;
6037   }
6038 
6039   const char *getClobbers() const override {
6040     return "";
6041   }
6042 };
6043 
6044 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6045                                      unsigned &NumNames) const {
6046   Names = nullptr;
6047   NumNames = 0;
6048 }
6049 
6050 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6051                                        unsigned &NumAliases) const {
6052   Aliases = nullptr;
6053   NumAliases = 0;
6054 }
6055 } // end anonymous namespace.
6056 
6057 namespace {
6058 class Le64TargetInfo : public TargetInfo {
6059   static const Builtin::Info BuiltinInfo[];
6060 
6061 public:
6062   Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6063     BigEndian = false;
6064     NoAsmVariants = true;
6065     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6066     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6067     DescriptionString =
6068         "e-S128-p:64:64-v16:16-v32:32-v64:64-v96:32-v128:32-m:e-n8:16:32:64";
6069   }
6070 
6071   void getTargetDefines(const LangOptions &Opts,
6072                         MacroBuilder &Builder) const override {
6073     DefineStd(Builder, "unix", Opts);
6074     defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6075     Builder.defineMacro("__ELF__");
6076   }
6077   void getTargetBuiltins(const Builtin::Info *&Records,
6078                          unsigned &NumRecords) const override {
6079     Records = BuiltinInfo;
6080     NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6081   }
6082   BuiltinVaListKind getBuiltinVaListKind() const override {
6083     return TargetInfo::PNaClABIBuiltinVaList;
6084   }
6085   const char *getClobbers() const override { return ""; }
6086   void getGCCRegNames(const char *const *&Names,
6087                       unsigned &NumNames) const override {
6088     Names = nullptr;
6089     NumNames = 0;
6090   }
6091   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6092                         unsigned &NumAliases) const override {
6093     Aliases = nullptr;
6094     NumAliases = 0;
6095   }
6096   bool validateAsmConstraint(const char *&Name,
6097                              TargetInfo::ConstraintInfo &Info) const override {
6098     return false;
6099   }
6100 
6101   bool hasProtectedVisibility() const override { return false; }
6102 };
6103 } // end anonymous namespace.
6104 
6105 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6106 #define BUILTIN(ID, TYPE, ATTRS)                                               \
6107   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6108 #include "clang/Basic/BuiltinsLe64.def"
6109 };
6110 
6111 namespace {
6112   static const unsigned SPIRAddrSpaceMap[] = {
6113     1,    // opencl_global
6114     3,    // opencl_local
6115     2,    // opencl_constant
6116     0,    // cuda_device
6117     0,    // cuda_constant
6118     0     // cuda_shared
6119   };
6120   class SPIRTargetInfo : public TargetInfo {
6121   public:
6122     SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6123       assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6124         "SPIR target must use unknown OS");
6125       assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6126         "SPIR target must use unknown environment type");
6127       BigEndian = false;
6128       TLSSupported = false;
6129       LongWidth = LongAlign = 64;
6130       AddrSpaceMap = &SPIRAddrSpaceMap;
6131       UseAddrSpaceMapMangling = true;
6132       // Define available target features
6133       // These must be defined in sorted order!
6134       NoAsmVariants = true;
6135     }
6136     void getTargetDefines(const LangOptions &Opts,
6137                           MacroBuilder &Builder) const override {
6138       DefineStd(Builder, "SPIR", Opts);
6139     }
6140     bool hasFeature(StringRef Feature) const override {
6141       return Feature == "spir";
6142     }
6143 
6144     void getTargetBuiltins(const Builtin::Info *&Records,
6145                            unsigned &NumRecords) const override {}
6146     const char *getClobbers() const override {
6147       return "";
6148     }
6149     void getGCCRegNames(const char * const *&Names,
6150                         unsigned &NumNames) const override {}
6151     bool validateAsmConstraint(const char *&Name,
6152                                TargetInfo::ConstraintInfo &info) const override {
6153       return true;
6154     }
6155     void getGCCRegAliases(const GCCRegAlias *&Aliases,
6156                           unsigned &NumAliases) const override {}
6157     BuiltinVaListKind getBuiltinVaListKind() const override {
6158       return TargetInfo::VoidPtrBuiltinVaList;
6159     }
6160   };
6161 
6162 
6163   class SPIR32TargetInfo : public SPIRTargetInfo {
6164   public:
6165     SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6166       PointerWidth = PointerAlign = 32;
6167       SizeType     = TargetInfo::UnsignedInt;
6168       PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6169       DescriptionString
6170         = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6171           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6172     }
6173     void getTargetDefines(const LangOptions &Opts,
6174                           MacroBuilder &Builder) const override {
6175       DefineStd(Builder, "SPIR32", Opts);
6176     }
6177   };
6178 
6179   class SPIR64TargetInfo : public SPIRTargetInfo {
6180   public:
6181     SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6182       PointerWidth = PointerAlign = 64;
6183       SizeType     = TargetInfo::UnsignedLong;
6184       PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6185       DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6186                           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6187     }
6188     void getTargetDefines(const LangOptions &Opts,
6189                           MacroBuilder &Builder) const override {
6190       DefineStd(Builder, "SPIR64", Opts);
6191     }
6192   };
6193 }
6194 
6195 namespace {
6196 class XCoreTargetInfo : public TargetInfo {
6197   static const Builtin::Info BuiltinInfo[];
6198 public:
6199   XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6200     BigEndian = false;
6201     NoAsmVariants = true;
6202     LongLongAlign = 32;
6203     SuitableAlign = 32;
6204     DoubleAlign = LongDoubleAlign = 32;
6205     SizeType = UnsignedInt;
6206     PtrDiffType = SignedInt;
6207     IntPtrType = SignedInt;
6208     WCharType = UnsignedChar;
6209     WIntType = UnsignedInt;
6210     UseZeroLengthBitfieldAlignment = true;
6211     DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6212                         "-f64:32-a:0:32-n32";
6213   }
6214   void getTargetDefines(const LangOptions &Opts,
6215                         MacroBuilder &Builder) const override {
6216     Builder.defineMacro("__XS1B__");
6217   }
6218   void getTargetBuiltins(const Builtin::Info *&Records,
6219                          unsigned &NumRecords) const override {
6220     Records = BuiltinInfo;
6221     NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6222   }
6223   BuiltinVaListKind getBuiltinVaListKind() const override {
6224     return TargetInfo::VoidPtrBuiltinVaList;
6225   }
6226   const char *getClobbers() const override {
6227     return "";
6228   }
6229   void getGCCRegNames(const char * const *&Names,
6230                       unsigned &NumNames) const override {
6231     static const char * const GCCRegNames[] = {
6232       "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
6233       "r8",   "r9",   "r10",  "r11",  "cp",   "dp",   "sp",   "lr"
6234     };
6235     Names = GCCRegNames;
6236     NumNames = llvm::array_lengthof(GCCRegNames);
6237   }
6238   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6239                         unsigned &NumAliases) const override {
6240     Aliases = nullptr;
6241     NumAliases = 0;
6242   }
6243   bool validateAsmConstraint(const char *&Name,
6244                              TargetInfo::ConstraintInfo &Info) const override {
6245     return false;
6246   }
6247   int getEHDataRegisterNumber(unsigned RegNo) const override {
6248     // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6249     return (RegNo < 2)? RegNo : -1;
6250   }
6251 };
6252 
6253 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6254 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6255 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6256                                               ALL_LANGUAGES },
6257 #include "clang/Basic/BuiltinsXCore.def"
6258 };
6259 } // end anonymous namespace.
6260 
6261 
6262 //===----------------------------------------------------------------------===//
6263 // Driver code
6264 //===----------------------------------------------------------------------===//
6265 
6266 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6267   llvm::Triple::OSType os = Triple.getOS();
6268 
6269   switch (Triple.getArch()) {
6270   default:
6271     return nullptr;
6272 
6273   case llvm::Triple::xcore:
6274     return new XCoreTargetInfo(Triple);
6275 
6276   case llvm::Triple::hexagon:
6277     return new HexagonTargetInfo(Triple);
6278 
6279   case llvm::Triple::aarch64:
6280     if (Triple.isOSDarwin())
6281       return new DarwinAArch64TargetInfo(Triple);
6282 
6283     switch (os) {
6284     case llvm::Triple::Linux:
6285       return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6286     case llvm::Triple::NetBSD:
6287       return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6288     default:
6289       return new AArch64leTargetInfo(Triple);
6290     }
6291 
6292   case llvm::Triple::aarch64_be:
6293     switch (os) {
6294     case llvm::Triple::Linux:
6295       return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6296     case llvm::Triple::NetBSD:
6297       return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6298     default:
6299       return new AArch64beTargetInfo(Triple);
6300     }
6301 
6302   case llvm::Triple::arm:
6303   case llvm::Triple::thumb:
6304     if (Triple.isOSBinFormatMachO())
6305       return new DarwinARMTargetInfo(Triple);
6306 
6307     switch (os) {
6308     case llvm::Triple::Linux:
6309       return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6310     case llvm::Triple::FreeBSD:
6311       return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6312     case llvm::Triple::NetBSD:
6313       return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6314     case llvm::Triple::OpenBSD:
6315       return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6316     case llvm::Triple::Bitrig:
6317       return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6318     case llvm::Triple::RTEMS:
6319       return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6320     case llvm::Triple::NaCl:
6321       return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6322     case llvm::Triple::Win32:
6323       switch (Triple.getEnvironment()) {
6324       default:
6325         return new ARMleTargetInfo(Triple);
6326       case llvm::Triple::Itanium:
6327         return new ItaniumWindowsARMleTargetInfo(Triple);
6328       case llvm::Triple::MSVC:
6329         return new MicrosoftARMleTargetInfo(Triple);
6330       }
6331     default:
6332       return new ARMleTargetInfo(Triple);
6333     }
6334 
6335   case llvm::Triple::armeb:
6336   case llvm::Triple::thumbeb:
6337     if (Triple.isOSDarwin())
6338       return new DarwinARMTargetInfo(Triple);
6339 
6340     switch (os) {
6341     case llvm::Triple::Linux:
6342       return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6343     case llvm::Triple::FreeBSD:
6344       return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6345     case llvm::Triple::NetBSD:
6346       return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6347     case llvm::Triple::OpenBSD:
6348       return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6349     case llvm::Triple::Bitrig:
6350       return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6351     case llvm::Triple::RTEMS:
6352       return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6353     case llvm::Triple::NaCl:
6354       return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6355     default:
6356       return new ARMbeTargetInfo(Triple);
6357     }
6358 
6359   case llvm::Triple::msp430:
6360     return new MSP430TargetInfo(Triple);
6361 
6362   case llvm::Triple::mips:
6363     switch (os) {
6364     case llvm::Triple::Linux:
6365       return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6366     case llvm::Triple::RTEMS:
6367       return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6368     case llvm::Triple::FreeBSD:
6369       return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6370     case llvm::Triple::NetBSD:
6371       return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6372     default:
6373       return new Mips32EBTargetInfo(Triple);
6374     }
6375 
6376   case llvm::Triple::mipsel:
6377     switch (os) {
6378     case llvm::Triple::Linux:
6379       return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6380     case llvm::Triple::RTEMS:
6381       return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6382     case llvm::Triple::FreeBSD:
6383       return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6384     case llvm::Triple::NetBSD:
6385       return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6386     case llvm::Triple::NaCl:
6387       return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6388     default:
6389       return new Mips32ELTargetInfo(Triple);
6390     }
6391 
6392   case llvm::Triple::mips64:
6393     switch (os) {
6394     case llvm::Triple::Linux:
6395       return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
6396     case llvm::Triple::RTEMS:
6397       return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
6398     case llvm::Triple::FreeBSD:
6399       return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6400     case llvm::Triple::NetBSD:
6401       return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6402     case llvm::Triple::OpenBSD:
6403       return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6404     default:
6405       return new Mips64EBTargetInfo(Triple);
6406     }
6407 
6408   case llvm::Triple::mips64el:
6409     switch (os) {
6410     case llvm::Triple::Linux:
6411       return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
6412     case llvm::Triple::RTEMS:
6413       return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
6414     case llvm::Triple::FreeBSD:
6415       return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6416     case llvm::Triple::NetBSD:
6417       return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6418     case llvm::Triple::OpenBSD:
6419       return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6420     default:
6421       return new Mips64ELTargetInfo(Triple);
6422     }
6423 
6424   case llvm::Triple::le32:
6425     switch (os) {
6426       case llvm::Triple::NaCl:
6427         return new NaClTargetInfo<PNaClTargetInfo>(Triple);
6428       default:
6429         return nullptr;
6430     }
6431 
6432   case llvm::Triple::le64:
6433     return new Le64TargetInfo(Triple);
6434 
6435   case llvm::Triple::ppc:
6436     if (Triple.isOSDarwin())
6437       return new DarwinPPC32TargetInfo(Triple);
6438     switch (os) {
6439     case llvm::Triple::Linux:
6440       return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
6441     case llvm::Triple::FreeBSD:
6442       return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
6443     case llvm::Triple::NetBSD:
6444       return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
6445     case llvm::Triple::OpenBSD:
6446       return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
6447     case llvm::Triple::RTEMS:
6448       return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
6449     default:
6450       return new PPC32TargetInfo(Triple);
6451     }
6452 
6453   case llvm::Triple::ppc64:
6454     if (Triple.isOSDarwin())
6455       return new DarwinPPC64TargetInfo(Triple);
6456     switch (os) {
6457     case llvm::Triple::Linux:
6458       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6459     case llvm::Triple::Lv2:
6460       return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
6461     case llvm::Triple::FreeBSD:
6462       return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
6463     case llvm::Triple::NetBSD:
6464       return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6465     default:
6466       return new PPC64TargetInfo(Triple);
6467     }
6468 
6469   case llvm::Triple::ppc64le:
6470     switch (os) {
6471     case llvm::Triple::Linux:
6472       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6473     default:
6474       return new PPC64TargetInfo(Triple);
6475     }
6476 
6477   case llvm::Triple::nvptx:
6478     return new NVPTX32TargetInfo(Triple);
6479   case llvm::Triple::nvptx64:
6480     return new NVPTX64TargetInfo(Triple);
6481 
6482   case llvm::Triple::r600:
6483     return new R600TargetInfo(Triple);
6484 
6485   case llvm::Triple::sparc:
6486     switch (os) {
6487     case llvm::Triple::Linux:
6488       return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
6489     case llvm::Triple::Solaris:
6490       return new SolarisSparcV8TargetInfo(Triple);
6491     case llvm::Triple::NetBSD:
6492       return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
6493     case llvm::Triple::OpenBSD:
6494       return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
6495     case llvm::Triple::RTEMS:
6496       return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
6497     default:
6498       return new SparcV8TargetInfo(Triple);
6499     }
6500 
6501   case llvm::Triple::sparcv9:
6502     switch (os) {
6503     case llvm::Triple::Linux:
6504       return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
6505     case llvm::Triple::Solaris:
6506       return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
6507     case llvm::Triple::NetBSD:
6508       return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
6509     case llvm::Triple::OpenBSD:
6510       return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
6511     case llvm::Triple::FreeBSD:
6512       return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
6513     default:
6514       return new SparcV9TargetInfo(Triple);
6515     }
6516 
6517   case llvm::Triple::systemz:
6518     switch (os) {
6519     case llvm::Triple::Linux:
6520       return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
6521     default:
6522       return new SystemZTargetInfo(Triple);
6523     }
6524 
6525   case llvm::Triple::tce:
6526     return new TCETargetInfo(Triple);
6527 
6528   case llvm::Triple::x86:
6529     if (Triple.isOSDarwin())
6530       return new DarwinI386TargetInfo(Triple);
6531 
6532     switch (os) {
6533     case llvm::Triple::Linux:
6534       return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
6535     case llvm::Triple::DragonFly:
6536       return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
6537     case llvm::Triple::NetBSD:
6538       return new NetBSDI386TargetInfo(Triple);
6539     case llvm::Triple::OpenBSD:
6540       return new OpenBSDI386TargetInfo(Triple);
6541     case llvm::Triple::Bitrig:
6542       return new BitrigI386TargetInfo(Triple);
6543     case llvm::Triple::FreeBSD:
6544       return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6545     case llvm::Triple::KFreeBSD:
6546       return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6547     case llvm::Triple::Minix:
6548       return new MinixTargetInfo<X86_32TargetInfo>(Triple);
6549     case llvm::Triple::Solaris:
6550       return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
6551     case llvm::Triple::Win32: {
6552       switch (Triple.getEnvironment()) {
6553       default:
6554         return new X86_32TargetInfo(Triple);
6555       case llvm::Triple::Cygnus:
6556         return new CygwinX86_32TargetInfo(Triple);
6557       case llvm::Triple::GNU:
6558         return new MinGWX86_32TargetInfo(Triple);
6559       case llvm::Triple::Itanium:
6560       case llvm::Triple::MSVC:
6561         return new MicrosoftX86_32TargetInfo(Triple);
6562       }
6563     }
6564     case llvm::Triple::Haiku:
6565       return new HaikuX86_32TargetInfo(Triple);
6566     case llvm::Triple::RTEMS:
6567       return new RTEMSX86_32TargetInfo(Triple);
6568     case llvm::Triple::NaCl:
6569       return new NaClTargetInfo<X86_32TargetInfo>(Triple);
6570     default:
6571       return new X86_32TargetInfo(Triple);
6572     }
6573 
6574   case llvm::Triple::x86_64:
6575     if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
6576       return new DarwinX86_64TargetInfo(Triple);
6577 
6578     switch (os) {
6579     case llvm::Triple::Linux:
6580       return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
6581     case llvm::Triple::DragonFly:
6582       return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
6583     case llvm::Triple::NetBSD:
6584       return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
6585     case llvm::Triple::OpenBSD:
6586       return new OpenBSDX86_64TargetInfo(Triple);
6587     case llvm::Triple::Bitrig:
6588       return new BitrigX86_64TargetInfo(Triple);
6589     case llvm::Triple::FreeBSD:
6590       return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6591     case llvm::Triple::KFreeBSD:
6592       return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6593     case llvm::Triple::Solaris:
6594       return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
6595     case llvm::Triple::Win32: {
6596       switch (Triple.getEnvironment()) {
6597       default:
6598         return new X86_64TargetInfo(Triple);
6599       case llvm::Triple::GNU:
6600         return new MinGWX86_64TargetInfo(Triple);
6601       case llvm::Triple::MSVC:
6602         return new MicrosoftX86_64TargetInfo(Triple);
6603       }
6604     }
6605     case llvm::Triple::NaCl:
6606       return new NaClTargetInfo<X86_64TargetInfo>(Triple);
6607     default:
6608       return new X86_64TargetInfo(Triple);
6609     }
6610 
6611     case llvm::Triple::spir: {
6612       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6613           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6614         return nullptr;
6615       return new SPIR32TargetInfo(Triple);
6616     }
6617     case llvm::Triple::spir64: {
6618       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6619           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6620         return nullptr;
6621       return new SPIR64TargetInfo(Triple);
6622     }
6623   }
6624 }
6625 
6626 /// CreateTargetInfo - Return the target info object for the specified target
6627 /// triple.
6628 TargetInfo *
6629 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
6630                              const std::shared_ptr<TargetOptions> &Opts) {
6631   llvm::Triple Triple(Opts->Triple);
6632 
6633   // Construct the target
6634   std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
6635   if (!Target) {
6636     Diags.Report(diag::err_target_unknown_triple) << Triple.str();
6637     return nullptr;
6638   }
6639   Target->TargetOpts = Opts;
6640 
6641   // Set the target CPU if specified.
6642   if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
6643     Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
6644     return nullptr;
6645   }
6646 
6647   // Set the target ABI if specified.
6648   if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
6649     Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
6650     return nullptr;
6651   }
6652 
6653   // Set the fp math unit.
6654   if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
6655     Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
6656     return nullptr;
6657   }
6658 
6659   // Compute the default target features, we need the target to handle this
6660   // because features may have dependencies on one another.
6661   llvm::StringMap<bool> Features;
6662   Target->getDefaultFeatures(Features);
6663 
6664   // Apply the user specified deltas.
6665   for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
6666        I < N; ++I) {
6667     const char *Name = Opts->FeaturesAsWritten[I].c_str();
6668     // Apply the feature via the target.
6669     bool Enabled = Name[0] == '+';
6670     Target->setFeatureEnabled(Features, Name + 1, Enabled);
6671   }
6672 
6673   // Add the features to the compile options.
6674   //
6675   // FIXME: If we are completely confident that we have the right set, we only
6676   // need to pass the minuses.
6677   Opts->Features.clear();
6678   for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
6679          ie = Features.end(); it != ie; ++it)
6680     Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
6681   if (!Target->handleTargetFeatures(Opts->Features, Diags))
6682     return nullptr;
6683 
6684   return Target.release();
6685 }
6686