1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 if (Maj) 469 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 470 } 471 if (Opts.POSIXThreads) 472 Builder.defineMacro("_REENTRANT"); 473 if (Opts.CPlusPlus) 474 Builder.defineMacro("_GNU_SOURCE"); 475 if (this->HasFloat128) 476 Builder.defineMacro("__FLOAT128__"); 477 } 478 public: 479 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 480 : OSTargetInfo<Target>(Triple, Opts) { 481 this->WIntType = TargetInfo::UnsignedInt; 482 483 switch (Triple.getArch()) { 484 default: 485 break; 486 case llvm::Triple::ppc: 487 case llvm::Triple::ppc64: 488 case llvm::Triple::ppc64le: 489 this->MCountName = "_mcount"; 490 break; 491 case llvm::Triple::x86: 492 case llvm::Triple::x86_64: 493 case llvm::Triple::systemz: 494 this->HasFloat128 = true; 495 break; 496 } 497 } 498 499 const char *getStaticInitSectionSpecifier() const override { 500 return ".text.startup"; 501 } 502 }; 503 504 // NetBSD Target 505 template<typename Target> 506 class NetBSDTargetInfo : public OSTargetInfo<Target> { 507 protected: 508 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 509 MacroBuilder &Builder) const override { 510 // NetBSD defines; list based off of gcc output 511 Builder.defineMacro("__NetBSD__"); 512 Builder.defineMacro("__unix__"); 513 Builder.defineMacro("__ELF__"); 514 if (Opts.POSIXThreads) 515 Builder.defineMacro("_REENTRANT"); 516 517 switch (Triple.getArch()) { 518 default: 519 break; 520 case llvm::Triple::arm: 521 case llvm::Triple::armeb: 522 case llvm::Triple::thumb: 523 case llvm::Triple::thumbeb: 524 Builder.defineMacro("__ARM_DWARF_EH__"); 525 break; 526 } 527 } 528 public: 529 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 530 : OSTargetInfo<Target>(Triple, Opts) { 531 this->MCountName = "_mcount"; 532 } 533 }; 534 535 // OpenBSD Target 536 template<typename Target> 537 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 538 protected: 539 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 540 MacroBuilder &Builder) const override { 541 // OpenBSD defines; list based off of gcc output 542 543 Builder.defineMacro("__OpenBSD__"); 544 DefineStd(Builder, "unix", Opts); 545 Builder.defineMacro("__ELF__"); 546 if (Opts.POSIXThreads) 547 Builder.defineMacro("_REENTRANT"); 548 if (this->HasFloat128) 549 Builder.defineMacro("__FLOAT128__"); 550 } 551 public: 552 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 553 : OSTargetInfo<Target>(Triple, Opts) { 554 this->TLSSupported = false; 555 556 switch (Triple.getArch()) { 557 case llvm::Triple::x86: 558 case llvm::Triple::x86_64: 559 this->HasFloat128 = true; 560 // FALLTHROUGH 561 default: 562 this->MCountName = "__mcount"; 563 break; 564 case llvm::Triple::mips64: 565 case llvm::Triple::mips64el: 566 case llvm::Triple::ppc: 567 case llvm::Triple::sparcv9: 568 this->MCountName = "_mcount"; 569 break; 570 } 571 } 572 }; 573 574 // Bitrig Target 575 template<typename Target> 576 class BitrigTargetInfo : public OSTargetInfo<Target> { 577 protected: 578 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 579 MacroBuilder &Builder) const override { 580 // Bitrig defines; list based off of gcc output 581 582 Builder.defineMacro("__Bitrig__"); 583 DefineStd(Builder, "unix", Opts); 584 Builder.defineMacro("__ELF__"); 585 if (Opts.POSIXThreads) 586 Builder.defineMacro("_REENTRANT"); 587 588 switch (Triple.getArch()) { 589 default: 590 break; 591 case llvm::Triple::arm: 592 case llvm::Triple::armeb: 593 case llvm::Triple::thumb: 594 case llvm::Triple::thumbeb: 595 Builder.defineMacro("__ARM_DWARF_EH__"); 596 break; 597 } 598 } 599 public: 600 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 601 : OSTargetInfo<Target>(Triple, Opts) { 602 this->MCountName = "__mcount"; 603 } 604 }; 605 606 // PSP Target 607 template<typename Target> 608 class PSPTargetInfo : public OSTargetInfo<Target> { 609 protected: 610 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 611 MacroBuilder &Builder) const override { 612 // PSP defines; list based on the output of the pspdev gcc toolchain. 613 Builder.defineMacro("PSP"); 614 Builder.defineMacro("_PSP"); 615 Builder.defineMacro("__psp__"); 616 Builder.defineMacro("__ELF__"); 617 } 618 public: 619 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 620 }; 621 622 // PS3 PPU Target 623 template<typename Target> 624 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 625 protected: 626 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 627 MacroBuilder &Builder) const override { 628 // PS3 PPU defines. 629 Builder.defineMacro("__PPC__"); 630 Builder.defineMacro("__PPU__"); 631 Builder.defineMacro("__CELLOS_LV2__"); 632 Builder.defineMacro("__ELF__"); 633 Builder.defineMacro("__LP32__"); 634 Builder.defineMacro("_ARCH_PPC64"); 635 Builder.defineMacro("__powerpc64__"); 636 } 637 public: 638 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 639 : OSTargetInfo<Target>(Triple, Opts) { 640 this->LongWidth = this->LongAlign = 32; 641 this->PointerWidth = this->PointerAlign = 32; 642 this->IntMaxType = TargetInfo::SignedLongLong; 643 this->Int64Type = TargetInfo::SignedLongLong; 644 this->SizeType = TargetInfo::UnsignedInt; 645 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 646 } 647 }; 648 649 template <typename Target> 650 class PS4OSTargetInfo : public OSTargetInfo<Target> { 651 protected: 652 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 653 MacroBuilder &Builder) const override { 654 Builder.defineMacro("__FreeBSD__", "9"); 655 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 656 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 657 DefineStd(Builder, "unix", Opts); 658 Builder.defineMacro("__ELF__"); 659 Builder.defineMacro("__ORBIS__"); 660 } 661 public: 662 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 663 : OSTargetInfo<Target>(Triple, Opts) { 664 this->WCharType = this->UnsignedShort; 665 666 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 667 this->MaxTLSAlign = 256; 668 669 // On PS4, do not honor explicit bit field alignment, 670 // as in "__attribute__((aligned(2))) int b : 1;". 671 this->UseExplicitBitFieldAlignment = false; 672 673 switch (Triple.getArch()) { 674 default: 675 case llvm::Triple::x86_64: 676 this->MCountName = ".mcount"; 677 break; 678 } 679 } 680 }; 681 682 // Solaris target 683 template<typename Target> 684 class SolarisTargetInfo : public OSTargetInfo<Target> { 685 protected: 686 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 687 MacroBuilder &Builder) const override { 688 DefineStd(Builder, "sun", Opts); 689 DefineStd(Builder, "unix", Opts); 690 Builder.defineMacro("__ELF__"); 691 Builder.defineMacro("__svr4__"); 692 Builder.defineMacro("__SVR4"); 693 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 694 // newer, but to 500 for everything else. feature_test.h has a check to 695 // ensure that you are not using C99 with an old version of X/Open or C89 696 // with a new version. 697 if (Opts.C99) 698 Builder.defineMacro("_XOPEN_SOURCE", "600"); 699 else 700 Builder.defineMacro("_XOPEN_SOURCE", "500"); 701 if (Opts.CPlusPlus) 702 Builder.defineMacro("__C99FEATURES__"); 703 Builder.defineMacro("_LARGEFILE_SOURCE"); 704 Builder.defineMacro("_LARGEFILE64_SOURCE"); 705 Builder.defineMacro("__EXTENSIONS__"); 706 Builder.defineMacro("_REENTRANT"); 707 } 708 public: 709 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 710 : OSTargetInfo<Target>(Triple, Opts) { 711 this->WCharType = this->SignedInt; 712 // FIXME: WIntType should be SignedLong 713 } 714 }; 715 716 // Windows target 717 template<typename Target> 718 class WindowsTargetInfo : public OSTargetInfo<Target> { 719 protected: 720 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 721 MacroBuilder &Builder) const override { 722 Builder.defineMacro("_WIN32"); 723 } 724 void getVisualStudioDefines(const LangOptions &Opts, 725 MacroBuilder &Builder) const { 726 if (Opts.CPlusPlus) { 727 if (Opts.RTTIData) 728 Builder.defineMacro("_CPPRTTI"); 729 730 if (Opts.CXXExceptions) 731 Builder.defineMacro("_CPPUNWIND"); 732 } 733 734 if (Opts.Bool) 735 Builder.defineMacro("__BOOL_DEFINED"); 736 737 if (!Opts.CharIsSigned) 738 Builder.defineMacro("_CHAR_UNSIGNED"); 739 740 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 741 // but it works for now. 742 if (Opts.POSIXThreads) 743 Builder.defineMacro("_MT"); 744 745 if (Opts.MSCompatibilityVersion) { 746 Builder.defineMacro("_MSC_VER", 747 Twine(Opts.MSCompatibilityVersion / 100000)); 748 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 749 // FIXME We cannot encode the revision information into 32-bits 750 Builder.defineMacro("_MSC_BUILD", Twine(1)); 751 752 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 753 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 754 755 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 756 if (Opts.CPlusPlus1z) 757 Builder.defineMacro("_MSVC_LANG", "201403L"); 758 else if (Opts.CPlusPlus14) 759 Builder.defineMacro("_MSVC_LANG", "201402L"); 760 } 761 } 762 763 if (Opts.MicrosoftExt) { 764 Builder.defineMacro("_MSC_EXTENSIONS"); 765 766 if (Opts.CPlusPlus11) { 767 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 768 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 769 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 770 } 771 } 772 773 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 774 } 775 776 public: 777 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 778 : OSTargetInfo<Target>(Triple, Opts) {} 779 }; 780 781 template <typename Target> 782 class NaClTargetInfo : public OSTargetInfo<Target> { 783 protected: 784 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 785 MacroBuilder &Builder) const override { 786 if (Opts.POSIXThreads) 787 Builder.defineMacro("_REENTRANT"); 788 if (Opts.CPlusPlus) 789 Builder.defineMacro("_GNU_SOURCE"); 790 791 DefineStd(Builder, "unix", Opts); 792 Builder.defineMacro("__ELF__"); 793 Builder.defineMacro("__native_client__"); 794 } 795 796 public: 797 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 798 : OSTargetInfo<Target>(Triple, Opts) { 799 this->LongAlign = 32; 800 this->LongWidth = 32; 801 this->PointerAlign = 32; 802 this->PointerWidth = 32; 803 this->IntMaxType = TargetInfo::SignedLongLong; 804 this->Int64Type = TargetInfo::SignedLongLong; 805 this->DoubleAlign = 64; 806 this->LongDoubleWidth = 64; 807 this->LongDoubleAlign = 64; 808 this->LongLongWidth = 64; 809 this->LongLongAlign = 64; 810 this->SizeType = TargetInfo::UnsignedInt; 811 this->PtrDiffType = TargetInfo::SignedInt; 812 this->IntPtrType = TargetInfo::SignedInt; 813 // RegParmMax is inherited from the underlying architecture. 814 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 815 if (Triple.getArch() == llvm::Triple::arm) { 816 // Handled in ARM's setABI(). 817 } else if (Triple.getArch() == llvm::Triple::x86) { 818 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 819 } else if (Triple.getArch() == llvm::Triple::x86_64) { 820 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 821 } else if (Triple.getArch() == llvm::Triple::mipsel) { 822 // Handled on mips' setDataLayout. 823 } else { 824 assert(Triple.getArch() == llvm::Triple::le32); 825 this->resetDataLayout("e-p:32:32-i64:64"); 826 } 827 } 828 }; 829 830 // Fuchsia Target 831 template<typename Target> 832 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 833 protected: 834 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 835 MacroBuilder &Builder) const override { 836 Builder.defineMacro("__Fuchsia__"); 837 Builder.defineMacro("__ELF__"); 838 if (Opts.POSIXThreads) 839 Builder.defineMacro("_REENTRANT"); 840 // Required by the libc++ locale support. 841 if (Opts.CPlusPlus) 842 Builder.defineMacro("_GNU_SOURCE"); 843 } 844 public: 845 FuchsiaTargetInfo(const llvm::Triple &Triple, 846 const TargetOptions &Opts) 847 : OSTargetInfo<Target>(Triple, Opts) { 848 this->MCountName = "__mcount"; 849 } 850 }; 851 852 // WebAssembly target 853 template <typename Target> 854 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 855 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 856 MacroBuilder &Builder) const final { 857 // A common platform macro. 858 if (Opts.POSIXThreads) 859 Builder.defineMacro("_REENTRANT"); 860 // Follow g++ convention and predefine _GNU_SOURCE for C++. 861 if (Opts.CPlusPlus) 862 Builder.defineMacro("_GNU_SOURCE"); 863 } 864 865 // As an optimization, group static init code together in a section. 866 const char *getStaticInitSectionSpecifier() const final { 867 return ".text.__startup"; 868 } 869 870 public: 871 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 872 const TargetOptions &Opts) 873 : OSTargetInfo<Target>(Triple, Opts) { 874 this->MCountName = "__mcount"; 875 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 876 } 877 }; 878 879 //===----------------------------------------------------------------------===// 880 // Specific target implementations. 881 //===----------------------------------------------------------------------===// 882 883 // PPC abstract base class 884 class PPCTargetInfo : public TargetInfo { 885 static const Builtin::Info BuiltinInfo[]; 886 static const char * const GCCRegNames[]; 887 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 888 std::string CPU; 889 890 // Target cpu features. 891 bool HasAltivec; 892 bool HasVSX; 893 bool HasP8Vector; 894 bool HasP8Crypto; 895 bool HasDirectMove; 896 bool HasQPX; 897 bool HasHTM; 898 bool HasBPERMD; 899 bool HasExtDiv; 900 bool HasP9Vector; 901 902 protected: 903 std::string ABI; 904 905 public: 906 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 907 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false), 908 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 909 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 910 SuitableAlign = 128; 911 SimdDefaultAlign = 128; 912 LongDoubleWidth = LongDoubleAlign = 128; 913 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 914 } 915 916 /// \brief Flags for architecture specific defines. 917 typedef enum { 918 ArchDefineNone = 0, 919 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 920 ArchDefinePpcgr = 1 << 1, 921 ArchDefinePpcsq = 1 << 2, 922 ArchDefine440 = 1 << 3, 923 ArchDefine603 = 1 << 4, 924 ArchDefine604 = 1 << 5, 925 ArchDefinePwr4 = 1 << 6, 926 ArchDefinePwr5 = 1 << 7, 927 ArchDefinePwr5x = 1 << 8, 928 ArchDefinePwr6 = 1 << 9, 929 ArchDefinePwr6x = 1 << 10, 930 ArchDefinePwr7 = 1 << 11, 931 ArchDefinePwr8 = 1 << 12, 932 ArchDefinePwr9 = 1 << 13, 933 ArchDefineA2 = 1 << 14, 934 ArchDefineA2q = 1 << 15 935 } ArchDefineTypes; 936 937 // Set the language option for altivec based on our value. 938 void adjust(LangOptions &Opts) override { 939 if (HasAltivec) 940 Opts.AltiVec = 1; 941 TargetInfo::adjust(Opts); 942 } 943 944 // Note: GCC recognizes the following additional cpus: 945 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 946 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 947 // titan, rs64. 948 bool setCPU(const std::string &Name) override { 949 bool CPUKnown = llvm::StringSwitch<bool>(Name) 950 .Case("generic", true) 951 .Case("440", true) 952 .Case("450", true) 953 .Case("601", true) 954 .Case("602", true) 955 .Case("603", true) 956 .Case("603e", true) 957 .Case("603ev", true) 958 .Case("604", true) 959 .Case("604e", true) 960 .Case("620", true) 961 .Case("630", true) 962 .Case("g3", true) 963 .Case("7400", true) 964 .Case("g4", true) 965 .Case("7450", true) 966 .Case("g4+", true) 967 .Case("750", true) 968 .Case("970", true) 969 .Case("g5", true) 970 .Case("a2", true) 971 .Case("a2q", true) 972 .Case("e500mc", true) 973 .Case("e5500", true) 974 .Case("power3", true) 975 .Case("pwr3", true) 976 .Case("power4", true) 977 .Case("pwr4", true) 978 .Case("power5", true) 979 .Case("pwr5", true) 980 .Case("power5x", true) 981 .Case("pwr5x", true) 982 .Case("power6", true) 983 .Case("pwr6", true) 984 .Case("power6x", true) 985 .Case("pwr6x", true) 986 .Case("power7", true) 987 .Case("pwr7", true) 988 .Case("power8", true) 989 .Case("pwr8", true) 990 .Case("power9", true) 991 .Case("pwr9", true) 992 .Case("powerpc", true) 993 .Case("ppc", true) 994 .Case("powerpc64", true) 995 .Case("ppc64", true) 996 .Case("powerpc64le", true) 997 .Case("ppc64le", true) 998 .Default(false); 999 1000 if (CPUKnown) 1001 CPU = Name; 1002 1003 return CPUKnown; 1004 } 1005 1006 1007 StringRef getABI() const override { return ABI; } 1008 1009 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1010 return llvm::makeArrayRef(BuiltinInfo, 1011 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1012 } 1013 1014 bool isCLZForZeroUndef() const override { return false; } 1015 1016 void getTargetDefines(const LangOptions &Opts, 1017 MacroBuilder &Builder) const override; 1018 1019 bool 1020 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1021 StringRef CPU, 1022 const std::vector<std::string> &FeaturesVec) const override; 1023 1024 bool handleTargetFeatures(std::vector<std::string> &Features, 1025 DiagnosticsEngine &Diags) override; 1026 bool hasFeature(StringRef Feature) const override; 1027 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1028 bool Enabled) const override; 1029 1030 ArrayRef<const char *> getGCCRegNames() const override; 1031 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1032 bool validateAsmConstraint(const char *&Name, 1033 TargetInfo::ConstraintInfo &Info) const override { 1034 switch (*Name) { 1035 default: return false; 1036 case 'O': // Zero 1037 break; 1038 case 'b': // Base register 1039 case 'f': // Floating point register 1040 Info.setAllowsRegister(); 1041 break; 1042 // FIXME: The following are added to allow parsing. 1043 // I just took a guess at what the actions should be. 1044 // Also, is more specific checking needed? I.e. specific registers? 1045 case 'd': // Floating point register (containing 64-bit value) 1046 case 'v': // Altivec vector register 1047 Info.setAllowsRegister(); 1048 break; 1049 case 'w': 1050 switch (Name[1]) { 1051 case 'd':// VSX vector register to hold vector double data 1052 case 'f':// VSX vector register to hold vector float data 1053 case 's':// VSX vector register to hold scalar float data 1054 case 'a':// Any VSX register 1055 case 'c':// An individual CR bit 1056 break; 1057 default: 1058 return false; 1059 } 1060 Info.setAllowsRegister(); 1061 Name++; // Skip over 'w'. 1062 break; 1063 case 'h': // `MQ', `CTR', or `LINK' register 1064 case 'q': // `MQ' register 1065 case 'c': // `CTR' register 1066 case 'l': // `LINK' register 1067 case 'x': // `CR' register (condition register) number 0 1068 case 'y': // `CR' register (condition register) 1069 case 'z': // `XER[CA]' carry bit (part of the XER register) 1070 Info.setAllowsRegister(); 1071 break; 1072 case 'I': // Signed 16-bit constant 1073 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1074 // (use `L' instead for SImode constants) 1075 case 'K': // Unsigned 16-bit constant 1076 case 'L': // Signed 16-bit constant shifted left 16 bits 1077 case 'M': // Constant larger than 31 1078 case 'N': // Exact power of 2 1079 case 'P': // Constant whose negation is a signed 16-bit constant 1080 case 'G': // Floating point constant that can be loaded into a 1081 // register with one instruction per word 1082 case 'H': // Integer/Floating point constant that can be loaded 1083 // into a register using three instructions 1084 break; 1085 case 'm': // Memory operand. Note that on PowerPC targets, m can 1086 // include addresses that update the base register. It 1087 // is therefore only safe to use `m' in an asm statement 1088 // if that asm statement accesses the operand exactly once. 1089 // The asm statement must also use `%U<opno>' as a 1090 // placeholder for the "update" flag in the corresponding 1091 // load or store instruction. For example: 1092 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1093 // is correct but: 1094 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1095 // is not. Use es rather than m if you don't want the base 1096 // register to be updated. 1097 case 'e': 1098 if (Name[1] != 's') 1099 return false; 1100 // es: A "stable" memory operand; that is, one which does not 1101 // include any automodification of the base register. Unlike 1102 // `m', this constraint can be used in asm statements that 1103 // might access the operand several times, or that might not 1104 // access it at all. 1105 Info.setAllowsMemory(); 1106 Name++; // Skip over 'e'. 1107 break; 1108 case 'Q': // Memory operand that is an offset from a register (it is 1109 // usually better to use `m' or `es' in asm statements) 1110 case 'Z': // Memory operand that is an indexed or indirect from a 1111 // register (it is usually better to use `m' or `es' in 1112 // asm statements) 1113 Info.setAllowsMemory(); 1114 Info.setAllowsRegister(); 1115 break; 1116 case 'R': // AIX TOC entry 1117 case 'a': // Address operand that is an indexed or indirect from a 1118 // register (`p' is preferable for asm statements) 1119 case 'S': // Constant suitable as a 64-bit mask operand 1120 case 'T': // Constant suitable as a 32-bit mask operand 1121 case 'U': // System V Release 4 small data area reference 1122 case 't': // AND masks that can be performed by two rldic{l, r} 1123 // instructions 1124 case 'W': // Vector constant that does not require memory 1125 case 'j': // Vector constant that is all zeros. 1126 break; 1127 // End FIXME. 1128 } 1129 return true; 1130 } 1131 std::string convertConstraint(const char *&Constraint) const override { 1132 std::string R; 1133 switch (*Constraint) { 1134 case 'e': 1135 case 'w': 1136 // Two-character constraint; add "^" hint for later parsing. 1137 R = std::string("^") + std::string(Constraint, 2); 1138 Constraint++; 1139 break; 1140 default: 1141 return TargetInfo::convertConstraint(Constraint); 1142 } 1143 return R; 1144 } 1145 const char *getClobbers() const override { 1146 return ""; 1147 } 1148 int getEHDataRegisterNumber(unsigned RegNo) const override { 1149 if (RegNo == 0) return 3; 1150 if (RegNo == 1) return 4; 1151 return -1; 1152 } 1153 1154 bool hasSjLjLowering() const override { 1155 return true; 1156 } 1157 1158 bool useFloat128ManglingForLongDouble() const override { 1159 return LongDoubleWidth == 128 && 1160 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1161 getTriple().isOSBinFormatELF(); 1162 } 1163 }; 1164 1165 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1166 #define BUILTIN(ID, TYPE, ATTRS) \ 1167 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1168 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1169 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1170 #include "clang/Basic/BuiltinsPPC.def" 1171 }; 1172 1173 /// handleTargetFeatures - Perform initialization based on the user 1174 /// configured set of features. 1175 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1176 DiagnosticsEngine &Diags) { 1177 for (const auto &Feature : Features) { 1178 if (Feature == "+altivec") { 1179 HasAltivec = true; 1180 } else if (Feature == "+vsx") { 1181 HasVSX = true; 1182 } else if (Feature == "+bpermd") { 1183 HasBPERMD = true; 1184 } else if (Feature == "+extdiv") { 1185 HasExtDiv = true; 1186 } else if (Feature == "+power8-vector") { 1187 HasP8Vector = true; 1188 } else if (Feature == "+crypto") { 1189 HasP8Crypto = true; 1190 } else if (Feature == "+direct-move") { 1191 HasDirectMove = true; 1192 } else if (Feature == "+qpx") { 1193 HasQPX = true; 1194 } else if (Feature == "+htm") { 1195 HasHTM = true; 1196 } else if (Feature == "+float128") { 1197 HasFloat128 = true; 1198 } else if (Feature == "+power9-vector") { 1199 HasP9Vector = true; 1200 } 1201 // TODO: Finish this list and add an assert that we've handled them 1202 // all. 1203 } 1204 1205 return true; 1206 } 1207 1208 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1209 /// #defines that are not tied to a specific subtarget. 1210 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1211 MacroBuilder &Builder) const { 1212 // Target identification. 1213 Builder.defineMacro("__ppc__"); 1214 Builder.defineMacro("__PPC__"); 1215 Builder.defineMacro("_ARCH_PPC"); 1216 Builder.defineMacro("__powerpc__"); 1217 Builder.defineMacro("__POWERPC__"); 1218 if (PointerWidth == 64) { 1219 Builder.defineMacro("_ARCH_PPC64"); 1220 Builder.defineMacro("__powerpc64__"); 1221 Builder.defineMacro("__ppc64__"); 1222 Builder.defineMacro("__PPC64__"); 1223 } 1224 1225 // Target properties. 1226 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1227 Builder.defineMacro("_LITTLE_ENDIAN"); 1228 } else { 1229 if (getTriple().getOS() != llvm::Triple::NetBSD && 1230 getTriple().getOS() != llvm::Triple::OpenBSD) 1231 Builder.defineMacro("_BIG_ENDIAN"); 1232 } 1233 1234 // ABI options. 1235 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1236 Builder.defineMacro("_CALL_ELF", "1"); 1237 if (ABI == "elfv2") 1238 Builder.defineMacro("_CALL_ELF", "2"); 1239 1240 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 1241 // our suppport post-dates this and it should work on all 64-bit ppc linux 1242 // platforms. It is guaranteed to work on all elfv2 platforms. 1243 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 1244 Builder.defineMacro("_CALL_LINUX", "1"); 1245 1246 // Subtarget options. 1247 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1248 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1249 1250 // FIXME: Should be controlled by command line option. 1251 if (LongDoubleWidth == 128) { 1252 Builder.defineMacro("__LONG_DOUBLE_128__"); 1253 Builder.defineMacro("__LONGDOUBLE128"); 1254 } 1255 1256 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1257 if (ABI == "elfv2" || 1258 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1259 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1260 1261 // CPU identification. 1262 ArchDefineTypes defs = 1263 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1264 .Case("440", ArchDefineName) 1265 .Case("450", ArchDefineName | ArchDefine440) 1266 .Case("601", ArchDefineName) 1267 .Case("602", ArchDefineName | ArchDefinePpcgr) 1268 .Case("603", ArchDefineName | ArchDefinePpcgr) 1269 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1270 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1271 .Case("604", ArchDefineName | ArchDefinePpcgr) 1272 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1273 .Case("620", ArchDefineName | ArchDefinePpcgr) 1274 .Case("630", ArchDefineName | ArchDefinePpcgr) 1275 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1276 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1277 .Case("750", ArchDefineName | ArchDefinePpcgr) 1278 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1279 ArchDefinePpcsq) 1280 .Case("a2", ArchDefineA2) 1281 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1282 .Case("pwr3", ArchDefinePpcgr) 1283 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1284 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1285 ArchDefinePpcsq) 1286 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 | 1287 ArchDefinePpcgr | ArchDefinePpcsq) 1288 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 | 1289 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1290 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x | 1291 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1292 ArchDefinePpcsq) 1293 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 | 1294 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1295 ArchDefinePpcgr | ArchDefinePpcsq) 1296 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x | 1297 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1298 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1299 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 | 1300 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1301 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1302 ArchDefinePpcsq) 1303 .Case("power3", ArchDefinePpcgr) 1304 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1305 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1306 ArchDefinePpcsq) 1307 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1308 ArchDefinePpcgr | ArchDefinePpcsq) 1309 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1310 ArchDefinePwr4 | ArchDefinePpcgr | 1311 ArchDefinePpcsq) 1312 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1313 ArchDefinePwr5 | ArchDefinePwr4 | 1314 ArchDefinePpcgr | ArchDefinePpcsq) 1315 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | 1316 ArchDefinePwr5x | ArchDefinePwr5 | 1317 ArchDefinePwr4 | ArchDefinePpcgr | 1318 ArchDefinePpcsq) 1319 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1320 ArchDefinePwr6 | ArchDefinePwr5x | 1321 ArchDefinePwr5 | ArchDefinePwr4 | 1322 ArchDefinePpcgr | ArchDefinePpcsq) 1323 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 1324 ArchDefinePwr6x | ArchDefinePwr6 | 1325 ArchDefinePwr5x | ArchDefinePwr5 | 1326 ArchDefinePwr4 | ArchDefinePpcgr | 1327 ArchDefinePpcsq) 1328 // powerpc64le automatically defaults to at least power8. 1329 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1330 ArchDefinePwr6 | ArchDefinePwr5x | 1331 ArchDefinePwr5 | ArchDefinePwr4 | 1332 ArchDefinePpcgr | ArchDefinePpcsq) 1333 .Default(ArchDefineNone); 1334 1335 if (defs & ArchDefineName) 1336 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1337 if (defs & ArchDefinePpcgr) 1338 Builder.defineMacro("_ARCH_PPCGR"); 1339 if (defs & ArchDefinePpcsq) 1340 Builder.defineMacro("_ARCH_PPCSQ"); 1341 if (defs & ArchDefine440) 1342 Builder.defineMacro("_ARCH_440"); 1343 if (defs & ArchDefine603) 1344 Builder.defineMacro("_ARCH_603"); 1345 if (defs & ArchDefine604) 1346 Builder.defineMacro("_ARCH_604"); 1347 if (defs & ArchDefinePwr4) 1348 Builder.defineMacro("_ARCH_PWR4"); 1349 if (defs & ArchDefinePwr5) 1350 Builder.defineMacro("_ARCH_PWR5"); 1351 if (defs & ArchDefinePwr5x) 1352 Builder.defineMacro("_ARCH_PWR5X"); 1353 if (defs & ArchDefinePwr6) 1354 Builder.defineMacro("_ARCH_PWR6"); 1355 if (defs & ArchDefinePwr6x) 1356 Builder.defineMacro("_ARCH_PWR6X"); 1357 if (defs & ArchDefinePwr7) 1358 Builder.defineMacro("_ARCH_PWR7"); 1359 if (defs & ArchDefinePwr8) 1360 Builder.defineMacro("_ARCH_PWR8"); 1361 if (defs & ArchDefinePwr9) 1362 Builder.defineMacro("_ARCH_PWR9"); 1363 if (defs & ArchDefineA2) 1364 Builder.defineMacro("_ARCH_A2"); 1365 if (defs & ArchDefineA2q) { 1366 Builder.defineMacro("_ARCH_A2Q"); 1367 Builder.defineMacro("_ARCH_QP"); 1368 } 1369 1370 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1371 Builder.defineMacro("__bg__"); 1372 Builder.defineMacro("__THW_BLUEGENE__"); 1373 Builder.defineMacro("__bgq__"); 1374 Builder.defineMacro("__TOS_BGQ__"); 1375 } 1376 1377 if (HasAltivec) { 1378 Builder.defineMacro("__VEC__", "10206"); 1379 Builder.defineMacro("__ALTIVEC__"); 1380 } 1381 if (HasVSX) 1382 Builder.defineMacro("__VSX__"); 1383 if (HasP8Vector) 1384 Builder.defineMacro("__POWER8_VECTOR__"); 1385 if (HasP8Crypto) 1386 Builder.defineMacro("__CRYPTO__"); 1387 if (HasHTM) 1388 Builder.defineMacro("__HTM__"); 1389 if (HasFloat128) 1390 Builder.defineMacro("__FLOAT128__"); 1391 if (HasP9Vector) 1392 Builder.defineMacro("__POWER9_VECTOR__"); 1393 1394 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1395 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1397 if (PointerWidth == 64) 1398 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1399 1400 // We have support for the bswap intrinsics so we can define this. 1401 Builder.defineMacro("__HAVE_BSWAP__", "1"); 1402 1403 // FIXME: The following are not yet generated here by Clang, but are 1404 // generated by GCC: 1405 // 1406 // _SOFT_FLOAT_ 1407 // __RECIP_PRECISION__ 1408 // __APPLE_ALTIVEC__ 1409 // __RECIP__ 1410 // __RECIPF__ 1411 // __RSQRTE__ 1412 // __RSQRTEF__ 1413 // _SOFT_DOUBLE_ 1414 // __NO_LWSYNC__ 1415 // __CMODEL_MEDIUM__ 1416 // __CMODEL_LARGE__ 1417 // _CALL_SYSV 1418 // _CALL_DARWIN 1419 // __NO_FPRS__ 1420 } 1421 1422 // Handle explicit options being passed to the compiler here: if we've 1423 // explicitly turned off vsx and turned on any of: 1424 // - power8-vector 1425 // - direct-move 1426 // - float128 1427 // - power9-vector 1428 // then go ahead and error since the customer has expressed an incompatible 1429 // set of options. 1430 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1431 const std::vector<std::string> &FeaturesVec) { 1432 1433 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1434 FeaturesVec.end()) { 1435 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1436 FeaturesVec.end()) { 1437 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1438 << "-mno-vsx"; 1439 return false; 1440 } 1441 1442 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1443 FeaturesVec.end()) { 1444 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1445 << "-mno-vsx"; 1446 return false; 1447 } 1448 1449 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1450 FeaturesVec.end()) { 1451 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1452 << "-mno-vsx"; 1453 return false; 1454 } 1455 1456 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1457 FeaturesVec.end()) { 1458 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1459 << "-mno-vsx"; 1460 return false; 1461 } 1462 } 1463 1464 return true; 1465 } 1466 1467 bool PPCTargetInfo::initFeatureMap( 1468 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1469 const std::vector<std::string> &FeaturesVec) const { 1470 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1471 .Case("7400", true) 1472 .Case("g4", true) 1473 .Case("7450", true) 1474 .Case("g4+", true) 1475 .Case("970", true) 1476 .Case("g5", true) 1477 .Case("pwr6", true) 1478 .Case("pwr7", true) 1479 .Case("pwr8", true) 1480 .Case("pwr9", true) 1481 .Case("ppc64", true) 1482 .Case("ppc64le", true) 1483 .Default(false); 1484 1485 Features["qpx"] = (CPU == "a2q"); 1486 Features["power9-vector"] = (CPU == "pwr9"); 1487 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1488 .Case("ppc64le", true) 1489 .Case("pwr9", true) 1490 .Case("pwr8", true) 1491 .Default(false); 1492 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1493 .Case("ppc64le", true) 1494 .Case("pwr9", true) 1495 .Case("pwr8", true) 1496 .Default(false); 1497 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1498 .Case("ppc64le", true) 1499 .Case("pwr9", true) 1500 .Case("pwr8", true) 1501 .Case("pwr7", true) 1502 .Default(false); 1503 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1504 .Case("ppc64le", true) 1505 .Case("pwr9", true) 1506 .Case("pwr8", true) 1507 .Case("pwr7", true) 1508 .Default(false); 1509 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1510 .Case("ppc64le", true) 1511 .Case("pwr9", true) 1512 .Case("pwr8", true) 1513 .Default(false); 1514 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1515 .Case("ppc64le", true) 1516 .Case("pwr9", true) 1517 .Case("pwr8", true) 1518 .Case("pwr7", true) 1519 .Default(false); 1520 Features["htm"] = llvm::StringSwitch<bool>(CPU) 1521 .Case("ppc64le", true) 1522 .Case("pwr9", true) 1523 .Case("pwr8", true) 1524 .Default(false); 1525 1526 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1527 return false; 1528 1529 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1530 } 1531 1532 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1533 return llvm::StringSwitch<bool>(Feature) 1534 .Case("powerpc", true) 1535 .Case("altivec", HasAltivec) 1536 .Case("vsx", HasVSX) 1537 .Case("power8-vector", HasP8Vector) 1538 .Case("crypto", HasP8Crypto) 1539 .Case("direct-move", HasDirectMove) 1540 .Case("qpx", HasQPX) 1541 .Case("htm", HasHTM) 1542 .Case("bpermd", HasBPERMD) 1543 .Case("extdiv", HasExtDiv) 1544 .Case("float128", HasFloat128) 1545 .Case("power9-vector", HasP9Vector) 1546 .Default(false); 1547 } 1548 1549 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1550 StringRef Name, bool Enabled) const { 1551 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1552 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1553 // incompatible options. 1554 if (Enabled) { 1555 if (Name == "direct-move" || 1556 Name == "power8-vector" || 1557 Name == "float128" || 1558 Name == "power9-vector") { 1559 // power9-vector is really a superset of power8-vector so encode that. 1560 Features[Name] = Features["vsx"] = true; 1561 if (Name == "power9-vector") 1562 Features["power8-vector"] = true; 1563 } else { 1564 Features[Name] = true; 1565 } 1566 } else { 1567 if (Name == "vsx") { 1568 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1569 Features["float128"] = Features["power9-vector"] = false; 1570 } else { 1571 Features[Name] = false; 1572 } 1573 } 1574 } 1575 1576 const char * const PPCTargetInfo::GCCRegNames[] = { 1577 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1578 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1579 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1580 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1581 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1582 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1583 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1584 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1585 "mq", "lr", "ctr", "ap", 1586 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1587 "xer", 1588 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1589 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1590 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1591 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1592 "vrsave", "vscr", 1593 "spe_acc", "spefscr", 1594 "sfp" 1595 }; 1596 1597 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1598 return llvm::makeArrayRef(GCCRegNames); 1599 } 1600 1601 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1602 // While some of these aliases do map to different registers 1603 // they still share the same register name. 1604 { { "0" }, "r0" }, 1605 { { "1"}, "r1" }, 1606 { { "2" }, "r2" }, 1607 { { "3" }, "r3" }, 1608 { { "4" }, "r4" }, 1609 { { "5" }, "r5" }, 1610 { { "6" }, "r6" }, 1611 { { "7" }, "r7" }, 1612 { { "8" }, "r8" }, 1613 { { "9" }, "r9" }, 1614 { { "10" }, "r10" }, 1615 { { "11" }, "r11" }, 1616 { { "12" }, "r12" }, 1617 { { "13" }, "r13" }, 1618 { { "14" }, "r14" }, 1619 { { "15" }, "r15" }, 1620 { { "16" }, "r16" }, 1621 { { "17" }, "r17" }, 1622 { { "18" }, "r18" }, 1623 { { "19" }, "r19" }, 1624 { { "20" }, "r20" }, 1625 { { "21" }, "r21" }, 1626 { { "22" }, "r22" }, 1627 { { "23" }, "r23" }, 1628 { { "24" }, "r24" }, 1629 { { "25" }, "r25" }, 1630 { { "26" }, "r26" }, 1631 { { "27" }, "r27" }, 1632 { { "28" }, "r28" }, 1633 { { "29" }, "r29" }, 1634 { { "30" }, "r30" }, 1635 { { "31" }, "r31" }, 1636 { { "fr0" }, "f0" }, 1637 { { "fr1" }, "f1" }, 1638 { { "fr2" }, "f2" }, 1639 { { "fr3" }, "f3" }, 1640 { { "fr4" }, "f4" }, 1641 { { "fr5" }, "f5" }, 1642 { { "fr6" }, "f6" }, 1643 { { "fr7" }, "f7" }, 1644 { { "fr8" }, "f8" }, 1645 { { "fr9" }, "f9" }, 1646 { { "fr10" }, "f10" }, 1647 { { "fr11" }, "f11" }, 1648 { { "fr12" }, "f12" }, 1649 { { "fr13" }, "f13" }, 1650 { { "fr14" }, "f14" }, 1651 { { "fr15" }, "f15" }, 1652 { { "fr16" }, "f16" }, 1653 { { "fr17" }, "f17" }, 1654 { { "fr18" }, "f18" }, 1655 { { "fr19" }, "f19" }, 1656 { { "fr20" }, "f20" }, 1657 { { "fr21" }, "f21" }, 1658 { { "fr22" }, "f22" }, 1659 { { "fr23" }, "f23" }, 1660 { { "fr24" }, "f24" }, 1661 { { "fr25" }, "f25" }, 1662 { { "fr26" }, "f26" }, 1663 { { "fr27" }, "f27" }, 1664 { { "fr28" }, "f28" }, 1665 { { "fr29" }, "f29" }, 1666 { { "fr30" }, "f30" }, 1667 { { "fr31" }, "f31" }, 1668 { { "cc" }, "cr0" }, 1669 }; 1670 1671 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1672 return llvm::makeArrayRef(GCCRegAliases); 1673 } 1674 1675 class PPC32TargetInfo : public PPCTargetInfo { 1676 public: 1677 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1678 : PPCTargetInfo(Triple, Opts) { 1679 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1680 1681 switch (getTriple().getOS()) { 1682 case llvm::Triple::Linux: 1683 case llvm::Triple::FreeBSD: 1684 case llvm::Triple::NetBSD: 1685 SizeType = UnsignedInt; 1686 PtrDiffType = SignedInt; 1687 IntPtrType = SignedInt; 1688 break; 1689 default: 1690 break; 1691 } 1692 1693 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1694 LongDoubleWidth = LongDoubleAlign = 64; 1695 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1696 } 1697 1698 // PPC32 supports atomics up to 4 bytes. 1699 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1700 } 1701 1702 BuiltinVaListKind getBuiltinVaListKind() const override { 1703 // This is the ELF definition, and is overridden by the Darwin sub-target 1704 return TargetInfo::PowerABIBuiltinVaList; 1705 } 1706 }; 1707 1708 // Note: ABI differences may eventually require us to have a separate 1709 // TargetInfo for little endian. 1710 class PPC64TargetInfo : public PPCTargetInfo { 1711 public: 1712 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1713 : PPCTargetInfo(Triple, Opts) { 1714 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1715 IntMaxType = SignedLong; 1716 Int64Type = SignedLong; 1717 1718 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1719 resetDataLayout("e-m:e-i64:64-n32:64"); 1720 ABI = "elfv2"; 1721 } else { 1722 resetDataLayout("E-m:e-i64:64-n32:64"); 1723 ABI = "elfv1"; 1724 } 1725 1726 switch (getTriple().getOS()) { 1727 case llvm::Triple::FreeBSD: 1728 LongDoubleWidth = LongDoubleAlign = 64; 1729 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1730 break; 1731 case llvm::Triple::NetBSD: 1732 IntMaxType = SignedLongLong; 1733 Int64Type = SignedLongLong; 1734 break; 1735 default: 1736 break; 1737 } 1738 1739 // PPC64 supports atomics up to 8 bytes. 1740 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1741 } 1742 BuiltinVaListKind getBuiltinVaListKind() const override { 1743 return TargetInfo::CharPtrBuiltinVaList; 1744 } 1745 // PPC64 Linux-specific ABI options. 1746 bool setABI(const std::string &Name) override { 1747 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1748 ABI = Name; 1749 return true; 1750 } 1751 return false; 1752 } 1753 }; 1754 1755 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1756 public: 1757 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1758 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1759 HasAlignMac68kSupport = true; 1760 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1761 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1762 LongLongAlign = 32; 1763 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1764 } 1765 BuiltinVaListKind getBuiltinVaListKind() const override { 1766 return TargetInfo::CharPtrBuiltinVaList; 1767 } 1768 }; 1769 1770 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1771 public: 1772 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1773 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1774 HasAlignMac68kSupport = true; 1775 resetDataLayout("E-m:o-i64:64-n32:64"); 1776 } 1777 }; 1778 1779 static const unsigned NVPTXAddrSpaceMap[] = { 1780 0, // Default 1781 1, // opencl_global 1782 3, // opencl_local 1783 4, // opencl_constant 1784 // FIXME: generic has to be added to the target 1785 0, // opencl_generic 1786 1, // cuda_device 1787 4, // cuda_constant 1788 3, // cuda_shared 1789 }; 1790 1791 class NVPTXTargetInfo : public TargetInfo { 1792 static const char *const GCCRegNames[]; 1793 static const Builtin::Info BuiltinInfo[]; 1794 CudaArch GPU; 1795 std::unique_ptr<TargetInfo> HostTarget; 1796 1797 public: 1798 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1799 unsigned TargetPointerWidth) 1800 : TargetInfo(Triple) { 1801 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1802 "NVPTX only supports 32- and 64-bit modes."); 1803 1804 TLSSupported = false; 1805 AddrSpaceMap = &NVPTXAddrSpaceMap; 1806 UseAddrSpaceMapMangling = true; 1807 1808 // Define available target features 1809 // These must be defined in sorted order! 1810 NoAsmVariants = true; 1811 GPU = CudaArch::SM_20; 1812 1813 if (TargetPointerWidth == 32) 1814 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1815 else 1816 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1817 1818 // If possible, get a TargetInfo for our host triple, so we can match its 1819 // types. 1820 llvm::Triple HostTriple(Opts.HostTriple); 1821 if (!HostTriple.isNVPTX()) 1822 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1823 1824 // If no host target, make some guesses about the data layout and return. 1825 if (!HostTarget) { 1826 LongWidth = LongAlign = TargetPointerWidth; 1827 PointerWidth = PointerAlign = TargetPointerWidth; 1828 switch (TargetPointerWidth) { 1829 case 32: 1830 SizeType = TargetInfo::UnsignedInt; 1831 PtrDiffType = TargetInfo::SignedInt; 1832 IntPtrType = TargetInfo::SignedInt; 1833 break; 1834 case 64: 1835 SizeType = TargetInfo::UnsignedLong; 1836 PtrDiffType = TargetInfo::SignedLong; 1837 IntPtrType = TargetInfo::SignedLong; 1838 break; 1839 default: 1840 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1841 } 1842 return; 1843 } 1844 1845 // Copy properties from host target. 1846 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1847 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1848 BoolWidth = HostTarget->getBoolWidth(); 1849 BoolAlign = HostTarget->getBoolAlign(); 1850 IntWidth = HostTarget->getIntWidth(); 1851 IntAlign = HostTarget->getIntAlign(); 1852 HalfWidth = HostTarget->getHalfWidth(); 1853 HalfAlign = HostTarget->getHalfAlign(); 1854 FloatWidth = HostTarget->getFloatWidth(); 1855 FloatAlign = HostTarget->getFloatAlign(); 1856 DoubleWidth = HostTarget->getDoubleWidth(); 1857 DoubleAlign = HostTarget->getDoubleAlign(); 1858 LongWidth = HostTarget->getLongWidth(); 1859 LongAlign = HostTarget->getLongAlign(); 1860 LongLongWidth = HostTarget->getLongLongWidth(); 1861 LongLongAlign = HostTarget->getLongLongAlign(); 1862 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1863 NewAlign = HostTarget->getNewAlign(); 1864 DefaultAlignForAttributeAligned = 1865 HostTarget->getDefaultAlignForAttributeAligned(); 1866 SizeType = HostTarget->getSizeType(); 1867 IntMaxType = HostTarget->getIntMaxType(); 1868 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1869 IntPtrType = HostTarget->getIntPtrType(); 1870 WCharType = HostTarget->getWCharType(); 1871 WIntType = HostTarget->getWIntType(); 1872 Char16Type = HostTarget->getChar16Type(); 1873 Char32Type = HostTarget->getChar32Type(); 1874 Int64Type = HostTarget->getInt64Type(); 1875 SigAtomicType = HostTarget->getSigAtomicType(); 1876 ProcessIDType = HostTarget->getProcessIDType(); 1877 1878 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1879 UseZeroLengthBitfieldAlignment = 1880 HostTarget->useZeroLengthBitfieldAlignment(); 1881 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1882 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1883 1884 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1885 // we need those macros to be identical on host and device, because (among 1886 // other things) they affect which standard library classes are defined, and 1887 // we need all classes to be defined on both the host and device. 1888 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1889 1890 // Properties intentionally not copied from host: 1891 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1892 // host/device boundary. 1893 // - SuitableAlign: Not visible across the host/device boundary, and may 1894 // correctly be different on host/device, e.g. if host has wider vector 1895 // types than device. 1896 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1897 // as its double type, but that's not necessarily true on the host. 1898 // TODO: nvcc emits a warning when using long double on device; we should 1899 // do the same. 1900 } 1901 void getTargetDefines(const LangOptions &Opts, 1902 MacroBuilder &Builder) const override { 1903 Builder.defineMacro("__PTX__"); 1904 Builder.defineMacro("__NVPTX__"); 1905 if (Opts.CUDAIsDevice) { 1906 // Set __CUDA_ARCH__ for the GPU specified. 1907 std::string CUDAArchCode = [this] { 1908 switch (GPU) { 1909 case CudaArch::UNKNOWN: 1910 assert(false && "No GPU arch when compiling CUDA device code."); 1911 return ""; 1912 case CudaArch::SM_20: 1913 return "200"; 1914 case CudaArch::SM_21: 1915 return "210"; 1916 case CudaArch::SM_30: 1917 return "300"; 1918 case CudaArch::SM_32: 1919 return "320"; 1920 case CudaArch::SM_35: 1921 return "350"; 1922 case CudaArch::SM_37: 1923 return "370"; 1924 case CudaArch::SM_50: 1925 return "500"; 1926 case CudaArch::SM_52: 1927 return "520"; 1928 case CudaArch::SM_53: 1929 return "530"; 1930 case CudaArch::SM_60: 1931 return "600"; 1932 case CudaArch::SM_61: 1933 return "610"; 1934 case CudaArch::SM_62: 1935 return "620"; 1936 } 1937 llvm_unreachable("unhandled CudaArch"); 1938 }(); 1939 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1940 } 1941 } 1942 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1943 return llvm::makeArrayRef(BuiltinInfo, 1944 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1945 } 1946 bool 1947 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1948 StringRef CPU, 1949 const std::vector<std::string> &FeaturesVec) const override { 1950 Features["satom"] = GPU >= CudaArch::SM_60; 1951 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1952 } 1953 1954 bool hasFeature(StringRef Feature) const override { 1955 return llvm::StringSwitch<bool>(Feature) 1956 .Cases("ptx", "nvptx", true) 1957 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1958 .Default(false); 1959 } 1960 1961 ArrayRef<const char *> getGCCRegNames() const override; 1962 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1963 // No aliases. 1964 return None; 1965 } 1966 bool validateAsmConstraint(const char *&Name, 1967 TargetInfo::ConstraintInfo &Info) const override { 1968 switch (*Name) { 1969 default: 1970 return false; 1971 case 'c': 1972 case 'h': 1973 case 'r': 1974 case 'l': 1975 case 'f': 1976 case 'd': 1977 Info.setAllowsRegister(); 1978 return true; 1979 } 1980 } 1981 const char *getClobbers() const override { 1982 // FIXME: Is this really right? 1983 return ""; 1984 } 1985 BuiltinVaListKind getBuiltinVaListKind() const override { 1986 // FIXME: implement 1987 return TargetInfo::CharPtrBuiltinVaList; 1988 } 1989 bool setCPU(const std::string &Name) override { 1990 GPU = StringToCudaArch(Name); 1991 return GPU != CudaArch::UNKNOWN; 1992 } 1993 void setSupportedOpenCLOpts() override { 1994 auto &Opts = getSupportedOpenCLOpts(); 1995 Opts.support("cl_clang_storage_class_specifiers"); 1996 Opts.support("cl_khr_gl_sharing"); 1997 Opts.support("cl_khr_icd"); 1998 1999 Opts.support("cl_khr_fp64"); 2000 Opts.support("cl_khr_byte_addressable_store"); 2001 Opts.support("cl_khr_global_int32_base_atomics"); 2002 Opts.support("cl_khr_global_int32_extended_atomics"); 2003 Opts.support("cl_khr_local_int32_base_atomics"); 2004 Opts.support("cl_khr_local_int32_extended_atomics"); 2005 } 2006 2007 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2008 // CUDA compilations support all of the host's calling conventions. 2009 // 2010 // TODO: We should warn if you apply a non-default CC to anything other than 2011 // a host function. 2012 if (HostTarget) 2013 return HostTarget->checkCallingConvention(CC); 2014 return CCCR_Warning; 2015 } 2016 }; 2017 2018 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 2019 #define BUILTIN(ID, TYPE, ATTRS) \ 2020 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2021 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2022 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2023 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2024 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2025 #include "clang/Basic/BuiltinsNVPTX.def" 2026 }; 2027 2028 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 2029 2030 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 2031 return llvm::makeArrayRef(GCCRegNames); 2032 } 2033 2034 static const LangAS::Map AMDGPUPrivateIsZeroMap = { 2035 4, // Default 2036 1, // opencl_global 2037 3, // opencl_local 2038 2, // opencl_constant 2039 4, // opencl_generic 2040 1, // cuda_device 2041 2, // cuda_constant 2042 3 // cuda_shared 2043 }; 2044 static const LangAS::Map AMDGPUGenericIsZeroMap = { 2045 0, // Default 2046 1, // opencl_global 2047 3, // opencl_local 2048 2, // opencl_constant 2049 0, // opencl_generic 2050 1, // cuda_device 2051 2, // cuda_constant 2052 3 // cuda_shared 2053 }; 2054 2055 // If you edit the description strings, make sure you update 2056 // getPointerWidthV(). 2057 2058 static const char *const DataLayoutStringR600 = 2059 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2060 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2061 2062 static const char *const DataLayoutStringSIPrivateIsZero = 2063 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2064 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2065 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2066 2067 static const char *const DataLayoutStringSIGenericIsZero = 2068 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" 2069 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2070 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; 2071 2072 class AMDGPUTargetInfo final : public TargetInfo { 2073 static const Builtin::Info BuiltinInfo[]; 2074 static const char * const GCCRegNames[]; 2075 2076 struct AddrSpace { 2077 unsigned Generic, Global, Local, Constant, Private; 2078 AddrSpace(bool IsGenericZero_ = false){ 2079 if (IsGenericZero_) { 2080 Generic = 0; 2081 Global = 1; 2082 Local = 3; 2083 Constant = 2; 2084 Private = 5; 2085 } else { 2086 Generic = 4; 2087 Global = 1; 2088 Local = 3; 2089 Constant = 2; 2090 Private = 0; 2091 } 2092 } 2093 }; 2094 2095 /// \brief The GPU profiles supported by the AMDGPU target. 2096 enum GPUKind { 2097 GK_NONE, 2098 GK_R600, 2099 GK_R600_DOUBLE_OPS, 2100 GK_R700, 2101 GK_R700_DOUBLE_OPS, 2102 GK_EVERGREEN, 2103 GK_EVERGREEN_DOUBLE_OPS, 2104 GK_NORTHERN_ISLANDS, 2105 GK_CAYMAN, 2106 GK_GFX6, 2107 GK_GFX7, 2108 GK_GFX8, 2109 GK_GFX9 2110 } GPU; 2111 2112 bool hasFP64:1; 2113 bool hasFMAF:1; 2114 bool hasLDEXPF:1; 2115 const AddrSpace AS; 2116 2117 static bool hasFullSpeedFMAF32(StringRef GPUName) { 2118 return parseAMDGCNName(GPUName) >= GK_GFX9; 2119 } 2120 2121 static bool isAMDGCN(const llvm::Triple &TT) { 2122 return TT.getArch() == llvm::Triple::amdgcn; 2123 } 2124 2125 static bool isGenericZero(const llvm::Triple &TT) { 2126 return TT.getEnvironmentName() == "amdgiz" || 2127 TT.getEnvironmentName() == "amdgizcl"; 2128 } 2129 public: 2130 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2131 : TargetInfo(Triple) , 2132 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2133 hasFP64(false), 2134 hasFMAF(false), 2135 hasLDEXPF(false), 2136 AS(isGenericZero(Triple)){ 2137 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2138 hasFP64 = true; 2139 hasFMAF = true; 2140 hasLDEXPF = true; 2141 } 2142 auto IsGenericZero = isGenericZero(Triple); 2143 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2144 (IsGenericZero ? DataLayoutStringSIGenericIsZero : 2145 DataLayoutStringSIPrivateIsZero) 2146 : DataLayoutStringR600); 2147 assert(DataLayout->getAllocaAddrSpace() == AS.Private); 2148 2149 AddrSpaceMap = IsGenericZero ? &AMDGPUGenericIsZeroMap : 2150 &AMDGPUPrivateIsZeroMap; 2151 UseAddrSpaceMapMangling = true; 2152 } 2153 2154 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2155 if (GPU <= GK_CAYMAN) 2156 return 32; 2157 2158 if (AddrSpace == AS.Private || AddrSpace == AS.Local) { 2159 return 32; 2160 } 2161 return 64; 2162 } 2163 2164 uint64_t getMaxPointerWidth() const override { 2165 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2166 } 2167 2168 const char * getClobbers() const override { 2169 return ""; 2170 } 2171 2172 ArrayRef<const char *> getGCCRegNames() const override; 2173 2174 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2175 return None; 2176 } 2177 2178 bool validateAsmConstraint(const char *&Name, 2179 TargetInfo::ConstraintInfo &Info) const override { 2180 switch (*Name) { 2181 default: break; 2182 case 'v': // vgpr 2183 case 's': // sgpr 2184 Info.setAllowsRegister(); 2185 return true; 2186 } 2187 return false; 2188 } 2189 2190 bool initFeatureMap(llvm::StringMap<bool> &Features, 2191 DiagnosticsEngine &Diags, StringRef CPU, 2192 const std::vector<std::string> &FeatureVec) const override; 2193 2194 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2195 TargetOptions &TargetOpts) const override { 2196 bool hasFP32Denormals = false; 2197 bool hasFP64Denormals = false; 2198 for (auto &I : TargetOpts.FeaturesAsWritten) { 2199 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2200 hasFP32Denormals = true; 2201 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2202 hasFP64Denormals = true; 2203 } 2204 if (!hasFP32Denormals) 2205 TargetOpts.Features.push_back( 2206 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) && 2207 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2208 // Always do not flush fp64 or fp16 denorms. 2209 if (!hasFP64Denormals && hasFP64) 2210 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2211 } 2212 2213 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2214 return llvm::makeArrayRef(BuiltinInfo, 2215 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2216 } 2217 2218 void getTargetDefines(const LangOptions &Opts, 2219 MacroBuilder &Builder) const override { 2220 if (getTriple().getArch() == llvm::Triple::amdgcn) 2221 Builder.defineMacro("__AMDGCN__"); 2222 else 2223 Builder.defineMacro("__R600__"); 2224 2225 if (hasFMAF) 2226 Builder.defineMacro("__HAS_FMAF__"); 2227 if (hasLDEXPF) 2228 Builder.defineMacro("__HAS_LDEXPF__"); 2229 if (hasFP64) 2230 Builder.defineMacro("__HAS_FP64__"); 2231 } 2232 2233 BuiltinVaListKind getBuiltinVaListKind() const override { 2234 return TargetInfo::CharPtrBuiltinVaList; 2235 } 2236 2237 static GPUKind parseR600Name(StringRef Name) { 2238 return llvm::StringSwitch<GPUKind>(Name) 2239 .Case("r600" , GK_R600) 2240 .Case("rv610", GK_R600) 2241 .Case("rv620", GK_R600) 2242 .Case("rv630", GK_R600) 2243 .Case("rv635", GK_R600) 2244 .Case("rs780", GK_R600) 2245 .Case("rs880", GK_R600) 2246 .Case("rv670", GK_R600_DOUBLE_OPS) 2247 .Case("rv710", GK_R700) 2248 .Case("rv730", GK_R700) 2249 .Case("rv740", GK_R700_DOUBLE_OPS) 2250 .Case("rv770", GK_R700_DOUBLE_OPS) 2251 .Case("palm", GK_EVERGREEN) 2252 .Case("cedar", GK_EVERGREEN) 2253 .Case("sumo", GK_EVERGREEN) 2254 .Case("sumo2", GK_EVERGREEN) 2255 .Case("redwood", GK_EVERGREEN) 2256 .Case("juniper", GK_EVERGREEN) 2257 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2258 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2259 .Case("barts", GK_NORTHERN_ISLANDS) 2260 .Case("turks", GK_NORTHERN_ISLANDS) 2261 .Case("caicos", GK_NORTHERN_ISLANDS) 2262 .Case("cayman", GK_CAYMAN) 2263 .Case("aruba", GK_CAYMAN) 2264 .Default(GK_NONE); 2265 } 2266 2267 static GPUKind parseAMDGCNName(StringRef Name) { 2268 return llvm::StringSwitch<GPUKind>(Name) 2269 .Case("tahiti", GK_GFX6) 2270 .Case("pitcairn", GK_GFX6) 2271 .Case("verde", GK_GFX6) 2272 .Case("oland", GK_GFX6) 2273 .Case("hainan", GK_GFX6) 2274 .Case("bonaire", GK_GFX7) 2275 .Case("kabini", GK_GFX7) 2276 .Case("kaveri", GK_GFX7) 2277 .Case("hawaii", GK_GFX7) 2278 .Case("mullins", GK_GFX7) 2279 .Case("gfx700", GK_GFX7) 2280 .Case("gfx701", GK_GFX7) 2281 .Case("gfx702", GK_GFX7) 2282 .Case("tonga", GK_GFX8) 2283 .Case("iceland", GK_GFX8) 2284 .Case("carrizo", GK_GFX8) 2285 .Case("fiji", GK_GFX8) 2286 .Case("stoney", GK_GFX8) 2287 .Case("polaris10", GK_GFX8) 2288 .Case("polaris11", GK_GFX8) 2289 .Case("gfx800", GK_GFX8) 2290 .Case("gfx801", GK_GFX8) 2291 .Case("gfx802", GK_GFX8) 2292 .Case("gfx803", GK_GFX8) 2293 .Case("gfx804", GK_GFX8) 2294 .Case("gfx810", GK_GFX8) 2295 .Case("gfx900", GK_GFX9) 2296 .Case("gfx901", GK_GFX9) 2297 .Default(GK_NONE); 2298 } 2299 2300 bool setCPU(const std::string &Name) override { 2301 if (getTriple().getArch() == llvm::Triple::amdgcn) 2302 GPU = parseAMDGCNName(Name); 2303 else 2304 GPU = parseR600Name(Name); 2305 2306 return GPU != GK_NONE; 2307 } 2308 2309 void setSupportedOpenCLOpts() override { 2310 auto &Opts = getSupportedOpenCLOpts(); 2311 Opts.support("cl_clang_storage_class_specifiers"); 2312 Opts.support("cl_khr_icd"); 2313 2314 if (hasFP64) 2315 Opts.support("cl_khr_fp64"); 2316 if (GPU >= GK_EVERGREEN) { 2317 Opts.support("cl_khr_byte_addressable_store"); 2318 Opts.support("cl_khr_global_int32_base_atomics"); 2319 Opts.support("cl_khr_global_int32_extended_atomics"); 2320 Opts.support("cl_khr_local_int32_base_atomics"); 2321 Opts.support("cl_khr_local_int32_extended_atomics"); 2322 } 2323 if (GPU >= GK_GFX6) { 2324 Opts.support("cl_khr_fp16"); 2325 Opts.support("cl_khr_int64_base_atomics"); 2326 Opts.support("cl_khr_int64_extended_atomics"); 2327 Opts.support("cl_khr_mipmap_image"); 2328 Opts.support("cl_khr_subgroups"); 2329 Opts.support("cl_khr_3d_image_writes"); 2330 Opts.support("cl_amd_media_ops"); 2331 Opts.support("cl_amd_media_ops2"); 2332 } 2333 } 2334 2335 LangAS::ID getOpenCLImageAddrSpace() const override { 2336 return LangAS::opencl_constant; 2337 } 2338 2339 /// \returns Target specific vtbl ptr address space. 2340 unsigned getVtblPtrAddressSpace() const override { 2341 // \todo: We currently have address spaces defined in AMDGPU Backend. It 2342 // would be nice if we could use it here instead of using bare numbers (same 2343 // applies to getDWARFAddressSpace). 2344 return 2; // constant. 2345 } 2346 2347 /// \returns If a target requires an address within a target specific address 2348 /// space \p AddressSpace to be converted in order to be used, then return the 2349 /// corresponding target specific DWARF address space. 2350 /// 2351 /// \returns Otherwise return None and no conversion will be emitted in the 2352 /// DWARF. 2353 Optional<unsigned> getDWARFAddressSpace( 2354 unsigned AddressSpace) const override { 2355 const unsigned DWARF_Private = 1; 2356 const unsigned DWARF_Local = 2; 2357 if (AddressSpace == AS.Private) { 2358 return DWARF_Private; 2359 } else if (AddressSpace == AS.Local) { 2360 return DWARF_Local; 2361 } else { 2362 return None; 2363 } 2364 } 2365 2366 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2367 switch (CC) { 2368 default: 2369 return CCCR_Warning; 2370 case CC_C: 2371 case CC_OpenCLKernel: 2372 return CCCR_OK; 2373 } 2374 } 2375 2376 // In amdgcn target the null pointer in global, constant, and generic 2377 // address space has value 0 but in private and local address space has 2378 // value ~0. 2379 uint64_t getNullPointerValue(unsigned AS) const override { 2380 return AS == LangAS::opencl_local ? ~0 : 0; 2381 } 2382 }; 2383 2384 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2385 #define BUILTIN(ID, TYPE, ATTRS) \ 2386 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2387 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2388 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2389 #include "clang/Basic/BuiltinsAMDGPU.def" 2390 }; 2391 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2392 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2393 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2394 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2395 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2396 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2397 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2398 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2399 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2400 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2401 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2402 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2403 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2404 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2405 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2406 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2407 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2408 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2409 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2410 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2411 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2412 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2413 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2414 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2415 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2416 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2417 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2418 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2419 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2420 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2421 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2422 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2423 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2424 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2425 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2426 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2427 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2428 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2429 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2430 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2431 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2432 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2433 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2434 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2435 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2436 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2437 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2438 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2439 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2440 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2441 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2442 }; 2443 2444 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2445 return llvm::makeArrayRef(GCCRegNames); 2446 } 2447 2448 bool AMDGPUTargetInfo::initFeatureMap( 2449 llvm::StringMap<bool> &Features, 2450 DiagnosticsEngine &Diags, StringRef CPU, 2451 const std::vector<std::string> &FeatureVec) const { 2452 2453 // XXX - What does the member GPU mean if device name string passed here? 2454 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2455 if (CPU.empty()) 2456 CPU = "tahiti"; 2457 2458 switch (parseAMDGCNName(CPU)) { 2459 case GK_GFX6: 2460 case GK_GFX7: 2461 break; 2462 2463 case GK_GFX9: 2464 Features["gfx9-insts"] = true; 2465 LLVM_FALLTHROUGH; 2466 case GK_GFX8: 2467 Features["s-memrealtime"] = true; 2468 Features["16-bit-insts"] = true; 2469 Features["dpp"] = true; 2470 break; 2471 2472 case GK_NONE: 2473 return false; 2474 default: 2475 llvm_unreachable("unhandled subtarget"); 2476 } 2477 } else { 2478 if (CPU.empty()) 2479 CPU = "r600"; 2480 2481 switch (parseR600Name(CPU)) { 2482 case GK_R600: 2483 case GK_R700: 2484 case GK_EVERGREEN: 2485 case GK_NORTHERN_ISLANDS: 2486 break; 2487 case GK_R600_DOUBLE_OPS: 2488 case GK_R700_DOUBLE_OPS: 2489 case GK_EVERGREEN_DOUBLE_OPS: 2490 case GK_CAYMAN: 2491 Features["fp64"] = true; 2492 break; 2493 case GK_NONE: 2494 return false; 2495 default: 2496 llvm_unreachable("unhandled subtarget"); 2497 } 2498 } 2499 2500 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2501 } 2502 2503 const Builtin::Info BuiltinInfoX86[] = { 2504 #define BUILTIN(ID, TYPE, ATTRS) \ 2505 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2506 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2507 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2508 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2509 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2510 #include "clang/Basic/BuiltinsX86.def" 2511 2512 #define BUILTIN(ID, TYPE, ATTRS) \ 2513 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2514 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2515 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2516 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2517 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2518 #include "clang/Basic/BuiltinsX86_64.def" 2519 }; 2520 2521 2522 static const char* const GCCRegNames[] = { 2523 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2524 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2525 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2526 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2527 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2528 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2529 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2530 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2531 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2532 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2533 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2534 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2535 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2536 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2537 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2538 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2539 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2540 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2541 }; 2542 2543 const TargetInfo::AddlRegName AddlRegNames[] = { 2544 { { "al", "ah", "eax", "rax" }, 0 }, 2545 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2546 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2547 { { "dl", "dh", "edx", "rdx" }, 1 }, 2548 { { "esi", "rsi" }, 4 }, 2549 { { "edi", "rdi" }, 5 }, 2550 { { "esp", "rsp" }, 7 }, 2551 { { "ebp", "rbp" }, 6 }, 2552 { { "r8d", "r8w", "r8b" }, 38 }, 2553 { { "r9d", "r9w", "r9b" }, 39 }, 2554 { { "r10d", "r10w", "r10b" }, 40 }, 2555 { { "r11d", "r11w", "r11b" }, 41 }, 2556 { { "r12d", "r12w", "r12b" }, 42 }, 2557 { { "r13d", "r13w", "r13b" }, 43 }, 2558 { { "r14d", "r14w", "r14b" }, 44 }, 2559 { { "r15d", "r15w", "r15b" }, 45 }, 2560 }; 2561 2562 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2563 // most of the implementation can be shared. 2564 class X86TargetInfo : public TargetInfo { 2565 enum X86SSEEnum { 2566 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2567 } SSELevel = NoSSE; 2568 enum MMX3DNowEnum { 2569 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2570 } MMX3DNowLevel = NoMMX3DNow; 2571 enum XOPEnum { 2572 NoXOP, 2573 SSE4A, 2574 FMA4, 2575 XOP 2576 } XOPLevel = NoXOP; 2577 2578 bool HasAES = false; 2579 bool HasPCLMUL = false; 2580 bool HasLZCNT = false; 2581 bool HasRDRND = false; 2582 bool HasFSGSBASE = false; 2583 bool HasBMI = false; 2584 bool HasBMI2 = false; 2585 bool HasPOPCNT = false; 2586 bool HasRTM = false; 2587 bool HasPRFCHW = false; 2588 bool HasRDSEED = false; 2589 bool HasADX = false; 2590 bool HasTBM = false; 2591 bool HasFMA = false; 2592 bool HasF16C = false; 2593 bool HasAVX512CD = false; 2594 bool HasAVX512ER = false; 2595 bool HasAVX512PF = false; 2596 bool HasAVX512DQ = false; 2597 bool HasAVX512BW = false; 2598 bool HasAVX512VL = false; 2599 bool HasAVX512VBMI = false; 2600 bool HasAVX512IFMA = false; 2601 bool HasSHA = false; 2602 bool HasMPX = false; 2603 bool HasSGX = false; 2604 bool HasCX16 = false; 2605 bool HasFXSR = false; 2606 bool HasXSAVE = false; 2607 bool HasXSAVEOPT = false; 2608 bool HasXSAVEC = false; 2609 bool HasXSAVES = false; 2610 bool HasMWAITX = false; 2611 bool HasCLZERO = false; 2612 bool HasPKU = false; 2613 bool HasCLFLUSHOPT = false; 2614 bool HasCLWB = false; 2615 bool HasMOVBE = false; 2616 bool HasPREFETCHWT1 = false; 2617 2618 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2619 /// 2620 /// Each enumeration represents a particular CPU supported by Clang. These 2621 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2622 enum CPUKind { 2623 CK_Generic, 2624 2625 /// \name i386 2626 /// i386-generation processors. 2627 //@{ 2628 CK_i386, 2629 //@} 2630 2631 /// \name i486 2632 /// i486-generation processors. 2633 //@{ 2634 CK_i486, 2635 CK_WinChipC6, 2636 CK_WinChip2, 2637 CK_C3, 2638 //@} 2639 2640 /// \name i586 2641 /// i586-generation processors, P5 microarchitecture based. 2642 //@{ 2643 CK_i586, 2644 CK_Pentium, 2645 CK_PentiumMMX, 2646 //@} 2647 2648 /// \name i686 2649 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2650 //@{ 2651 CK_i686, 2652 CK_PentiumPro, 2653 CK_Pentium2, 2654 CK_Pentium3, 2655 CK_Pentium3M, 2656 CK_PentiumM, 2657 CK_C3_2, 2658 2659 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2660 /// Clang however has some logic to suport this. 2661 // FIXME: Warn, deprecate, and potentially remove this. 2662 CK_Yonah, 2663 //@} 2664 2665 /// \name Netburst 2666 /// Netburst microarchitecture based processors. 2667 //@{ 2668 CK_Pentium4, 2669 CK_Pentium4M, 2670 CK_Prescott, 2671 CK_Nocona, 2672 //@} 2673 2674 /// \name Core 2675 /// Core microarchitecture based processors. 2676 //@{ 2677 CK_Core2, 2678 2679 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2680 /// codename which GCC no longer accepts as an option to -march, but Clang 2681 /// has some logic for recognizing it. 2682 // FIXME: Warn, deprecate, and potentially remove this. 2683 CK_Penryn, 2684 //@} 2685 2686 /// \name Atom 2687 /// Atom processors 2688 //@{ 2689 CK_Bonnell, 2690 CK_Silvermont, 2691 //@} 2692 2693 /// \name Nehalem 2694 /// Nehalem microarchitecture based processors. 2695 CK_Nehalem, 2696 2697 /// \name Westmere 2698 /// Westmere microarchitecture based processors. 2699 CK_Westmere, 2700 2701 /// \name Sandy Bridge 2702 /// Sandy Bridge microarchitecture based processors. 2703 CK_SandyBridge, 2704 2705 /// \name Ivy Bridge 2706 /// Ivy Bridge microarchitecture based processors. 2707 CK_IvyBridge, 2708 2709 /// \name Haswell 2710 /// Haswell microarchitecture based processors. 2711 CK_Haswell, 2712 2713 /// \name Broadwell 2714 /// Broadwell microarchitecture based processors. 2715 CK_Broadwell, 2716 2717 /// \name Skylake Client 2718 /// Skylake client microarchitecture based processors. 2719 CK_SkylakeClient, 2720 2721 /// \name Skylake Server 2722 /// Skylake server microarchitecture based processors. 2723 CK_SkylakeServer, 2724 2725 /// \name Cannonlake Client 2726 /// Cannonlake client microarchitecture based processors. 2727 CK_Cannonlake, 2728 2729 /// \name Knights Landing 2730 /// Knights Landing processor. 2731 CK_KNL, 2732 2733 /// \name Lakemont 2734 /// Lakemont microarchitecture based processors. 2735 CK_Lakemont, 2736 2737 /// \name K6 2738 /// K6 architecture processors. 2739 //@{ 2740 CK_K6, 2741 CK_K6_2, 2742 CK_K6_3, 2743 //@} 2744 2745 /// \name K7 2746 /// K7 architecture processors. 2747 //@{ 2748 CK_Athlon, 2749 CK_AthlonThunderbird, 2750 CK_Athlon4, 2751 CK_AthlonXP, 2752 CK_AthlonMP, 2753 //@} 2754 2755 /// \name K8 2756 /// K8 architecture processors. 2757 //@{ 2758 CK_Athlon64, 2759 CK_Athlon64SSE3, 2760 CK_AthlonFX, 2761 CK_K8, 2762 CK_K8SSE3, 2763 CK_Opteron, 2764 CK_OpteronSSE3, 2765 CK_AMDFAM10, 2766 //@} 2767 2768 /// \name Bobcat 2769 /// Bobcat architecture processors. 2770 //@{ 2771 CK_BTVER1, 2772 CK_BTVER2, 2773 //@} 2774 2775 /// \name Bulldozer 2776 /// Bulldozer architecture processors. 2777 //@{ 2778 CK_BDVER1, 2779 CK_BDVER2, 2780 CK_BDVER3, 2781 CK_BDVER4, 2782 //@} 2783 2784 /// \name zen 2785 /// Zen architecture processors. 2786 //@{ 2787 CK_ZNVER1, 2788 //@} 2789 2790 /// This specification is deprecated and will be removed in the future. 2791 /// Users should prefer \see CK_K8. 2792 // FIXME: Warn on this when the CPU is set to it. 2793 //@{ 2794 CK_x86_64, 2795 //@} 2796 2797 /// \name Geode 2798 /// Geode processors. 2799 //@{ 2800 CK_Geode 2801 //@} 2802 } CPU = CK_Generic; 2803 2804 CPUKind getCPUKind(StringRef CPU) const { 2805 return llvm::StringSwitch<CPUKind>(CPU) 2806 .Case("i386", CK_i386) 2807 .Case("i486", CK_i486) 2808 .Case("winchip-c6", CK_WinChipC6) 2809 .Case("winchip2", CK_WinChip2) 2810 .Case("c3", CK_C3) 2811 .Case("i586", CK_i586) 2812 .Case("pentium", CK_Pentium) 2813 .Case("pentium-mmx", CK_PentiumMMX) 2814 .Case("i686", CK_i686) 2815 .Case("pentiumpro", CK_PentiumPro) 2816 .Case("pentium2", CK_Pentium2) 2817 .Case("pentium3", CK_Pentium3) 2818 .Case("pentium3m", CK_Pentium3M) 2819 .Case("pentium-m", CK_PentiumM) 2820 .Case("c3-2", CK_C3_2) 2821 .Case("yonah", CK_Yonah) 2822 .Case("pentium4", CK_Pentium4) 2823 .Case("pentium4m", CK_Pentium4M) 2824 .Case("prescott", CK_Prescott) 2825 .Case("nocona", CK_Nocona) 2826 .Case("core2", CK_Core2) 2827 .Case("penryn", CK_Penryn) 2828 .Case("bonnell", CK_Bonnell) 2829 .Case("atom", CK_Bonnell) // Legacy name. 2830 .Case("silvermont", CK_Silvermont) 2831 .Case("slm", CK_Silvermont) // Legacy name. 2832 .Case("nehalem", CK_Nehalem) 2833 .Case("corei7", CK_Nehalem) // Legacy name. 2834 .Case("westmere", CK_Westmere) 2835 .Case("sandybridge", CK_SandyBridge) 2836 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2837 .Case("ivybridge", CK_IvyBridge) 2838 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2839 .Case("haswell", CK_Haswell) 2840 .Case("core-avx2", CK_Haswell) // Legacy name. 2841 .Case("broadwell", CK_Broadwell) 2842 .Case("skylake", CK_SkylakeClient) 2843 .Case("skylake-avx512", CK_SkylakeServer) 2844 .Case("skx", CK_SkylakeServer) // Legacy name. 2845 .Case("cannonlake", CK_Cannonlake) 2846 .Case("knl", CK_KNL) 2847 .Case("lakemont", CK_Lakemont) 2848 .Case("k6", CK_K6) 2849 .Case("k6-2", CK_K6_2) 2850 .Case("k6-3", CK_K6_3) 2851 .Case("athlon", CK_Athlon) 2852 .Case("athlon-tbird", CK_AthlonThunderbird) 2853 .Case("athlon-4", CK_Athlon4) 2854 .Case("athlon-xp", CK_AthlonXP) 2855 .Case("athlon-mp", CK_AthlonMP) 2856 .Case("athlon64", CK_Athlon64) 2857 .Case("athlon64-sse3", CK_Athlon64SSE3) 2858 .Case("athlon-fx", CK_AthlonFX) 2859 .Case("k8", CK_K8) 2860 .Case("k8-sse3", CK_K8SSE3) 2861 .Case("opteron", CK_Opteron) 2862 .Case("opteron-sse3", CK_OpteronSSE3) 2863 .Case("barcelona", CK_AMDFAM10) 2864 .Case("amdfam10", CK_AMDFAM10) 2865 .Case("btver1", CK_BTVER1) 2866 .Case("btver2", CK_BTVER2) 2867 .Case("bdver1", CK_BDVER1) 2868 .Case("bdver2", CK_BDVER2) 2869 .Case("bdver3", CK_BDVER3) 2870 .Case("bdver4", CK_BDVER4) 2871 .Case("znver1", CK_ZNVER1) 2872 .Case("x86-64", CK_x86_64) 2873 .Case("geode", CK_Geode) 2874 .Default(CK_Generic); 2875 } 2876 2877 enum FPMathKind { 2878 FP_Default, 2879 FP_SSE, 2880 FP_387 2881 } FPMath = FP_Default; 2882 2883 public: 2884 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2885 : TargetInfo(Triple) { 2886 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2887 } 2888 unsigned getFloatEvalMethod() const override { 2889 // X87 evaluates with 80 bits "long double" precision. 2890 return SSELevel == NoSSE ? 2 : 0; 2891 } 2892 ArrayRef<const char *> getGCCRegNames() const override { 2893 return llvm::makeArrayRef(GCCRegNames); 2894 } 2895 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2896 return None; 2897 } 2898 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2899 return llvm::makeArrayRef(AddlRegNames); 2900 } 2901 bool validateCpuSupports(StringRef Name) const override; 2902 bool validateAsmConstraint(const char *&Name, 2903 TargetInfo::ConstraintInfo &info) const override; 2904 2905 bool validateGlobalRegisterVariable(StringRef RegName, 2906 unsigned RegSize, 2907 bool &HasSizeMismatch) const override { 2908 // esp and ebp are the only 32-bit registers the x86 backend can currently 2909 // handle. 2910 if (RegName.equals("esp") || RegName.equals("ebp")) { 2911 // Check that the register size is 32-bit. 2912 HasSizeMismatch = RegSize != 32; 2913 return true; 2914 } 2915 2916 return false; 2917 } 2918 2919 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2920 2921 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2922 2923 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2924 2925 std::string convertConstraint(const char *&Constraint) const override; 2926 const char *getClobbers() const override { 2927 return "~{dirflag},~{fpsr},~{flags}"; 2928 } 2929 2930 StringRef getConstraintRegister(const StringRef &Constraint, 2931 const StringRef &Expression) const override { 2932 StringRef::iterator I, E; 2933 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 2934 if (isalpha(*I)) 2935 break; 2936 } 2937 if (I == E) 2938 return ""; 2939 switch (*I) { 2940 // For the register constraints, return the matching register name 2941 case 'a': 2942 return "ax"; 2943 case 'b': 2944 return "bx"; 2945 case 'c': 2946 return "cx"; 2947 case 'd': 2948 return "dx"; 2949 case 'S': 2950 return "si"; 2951 case 'D': 2952 return "di"; 2953 // In case the constraint is 'r' we need to return Expression 2954 case 'r': 2955 return Expression; 2956 default: 2957 // Default value if there is no constraint for the register 2958 return ""; 2959 } 2960 return ""; 2961 } 2962 2963 void getTargetDefines(const LangOptions &Opts, 2964 MacroBuilder &Builder) const override; 2965 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2966 bool Enabled); 2967 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2968 bool Enabled); 2969 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2970 bool Enabled); 2971 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2972 StringRef Name, bool Enabled) const override { 2973 setFeatureEnabledImpl(Features, Name, Enabled); 2974 } 2975 // This exists purely to cut down on the number of virtual calls in 2976 // initFeatureMap which calls this repeatedly. 2977 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2978 StringRef Name, bool Enabled); 2979 bool 2980 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2981 StringRef CPU, 2982 const std::vector<std::string> &FeaturesVec) const override; 2983 bool hasFeature(StringRef Feature) const override; 2984 bool handleTargetFeatures(std::vector<std::string> &Features, 2985 DiagnosticsEngine &Diags) override; 2986 StringRef getABI() const override { 2987 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2988 return "avx512"; 2989 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2990 return "avx"; 2991 if (getTriple().getArch() == llvm::Triple::x86 && 2992 MMX3DNowLevel == NoMMX3DNow) 2993 return "no-mmx"; 2994 return ""; 2995 } 2996 bool setCPU(const std::string &Name) override { 2997 CPU = getCPUKind(Name); 2998 2999 // Perform any per-CPU checks necessary to determine if this CPU is 3000 // acceptable. 3001 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 3002 // invalid without explaining *why*. 3003 switch (CPU) { 3004 case CK_Generic: 3005 // No processor selected! 3006 return false; 3007 3008 case CK_i386: 3009 case CK_i486: 3010 case CK_WinChipC6: 3011 case CK_WinChip2: 3012 case CK_C3: 3013 case CK_i586: 3014 case CK_Pentium: 3015 case CK_PentiumMMX: 3016 case CK_i686: 3017 case CK_PentiumPro: 3018 case CK_Pentium2: 3019 case CK_Pentium3: 3020 case CK_Pentium3M: 3021 case CK_PentiumM: 3022 case CK_Yonah: 3023 case CK_C3_2: 3024 case CK_Pentium4: 3025 case CK_Pentium4M: 3026 case CK_Lakemont: 3027 case CK_Prescott: 3028 case CK_K6: 3029 case CK_K6_2: 3030 case CK_K6_3: 3031 case CK_Athlon: 3032 case CK_AthlonThunderbird: 3033 case CK_Athlon4: 3034 case CK_AthlonXP: 3035 case CK_AthlonMP: 3036 case CK_Geode: 3037 // Only accept certain architectures when compiling in 32-bit mode. 3038 if (getTriple().getArch() != llvm::Triple::x86) 3039 return false; 3040 3041 // Fallthrough 3042 case CK_Nocona: 3043 case CK_Core2: 3044 case CK_Penryn: 3045 case CK_Bonnell: 3046 case CK_Silvermont: 3047 case CK_Nehalem: 3048 case CK_Westmere: 3049 case CK_SandyBridge: 3050 case CK_IvyBridge: 3051 case CK_Haswell: 3052 case CK_Broadwell: 3053 case CK_SkylakeClient: 3054 case CK_SkylakeServer: 3055 case CK_Cannonlake: 3056 case CK_KNL: 3057 case CK_Athlon64: 3058 case CK_Athlon64SSE3: 3059 case CK_AthlonFX: 3060 case CK_K8: 3061 case CK_K8SSE3: 3062 case CK_Opteron: 3063 case CK_OpteronSSE3: 3064 case CK_AMDFAM10: 3065 case CK_BTVER1: 3066 case CK_BTVER2: 3067 case CK_BDVER1: 3068 case CK_BDVER2: 3069 case CK_BDVER3: 3070 case CK_BDVER4: 3071 case CK_ZNVER1: 3072 case CK_x86_64: 3073 return true; 3074 } 3075 llvm_unreachable("Unhandled CPU kind"); 3076 } 3077 3078 bool setFPMath(StringRef Name) override; 3079 3080 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3081 // Most of the non-ARM calling conventions are i386 conventions. 3082 switch (CC) { 3083 case CC_X86ThisCall: 3084 case CC_X86FastCall: 3085 case CC_X86StdCall: 3086 case CC_X86VectorCall: 3087 case CC_X86RegCall: 3088 case CC_C: 3089 case CC_Swift: 3090 case CC_X86Pascal: 3091 case CC_IntelOclBicc: 3092 return CCCR_OK; 3093 default: 3094 return CCCR_Warning; 3095 } 3096 } 3097 3098 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3099 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 3100 } 3101 3102 bool hasSjLjLowering() const override { 3103 return true; 3104 } 3105 3106 void setSupportedOpenCLOpts() override { 3107 getSupportedOpenCLOpts().supportAll(); 3108 } 3109 }; 3110 3111 bool X86TargetInfo::setFPMath(StringRef Name) { 3112 if (Name == "387") { 3113 FPMath = FP_387; 3114 return true; 3115 } 3116 if (Name == "sse") { 3117 FPMath = FP_SSE; 3118 return true; 3119 } 3120 return false; 3121 } 3122 3123 bool X86TargetInfo::initFeatureMap( 3124 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3125 const std::vector<std::string> &FeaturesVec) const { 3126 // FIXME: This *really* should not be here. 3127 // X86_64 always has SSE2. 3128 if (getTriple().getArch() == llvm::Triple::x86_64) 3129 setFeatureEnabledImpl(Features, "sse2", true); 3130 3131 const CPUKind Kind = getCPUKind(CPU); 3132 3133 // Enable X87 for all X86 processors but Lakemont. 3134 if (Kind != CK_Lakemont) 3135 setFeatureEnabledImpl(Features, "x87", true); 3136 3137 switch (Kind) { 3138 case CK_Generic: 3139 case CK_i386: 3140 case CK_i486: 3141 case CK_i586: 3142 case CK_Pentium: 3143 case CK_i686: 3144 case CK_PentiumPro: 3145 case CK_Lakemont: 3146 break; 3147 case CK_PentiumMMX: 3148 case CK_Pentium2: 3149 case CK_K6: 3150 case CK_WinChipC6: 3151 setFeatureEnabledImpl(Features, "mmx", true); 3152 break; 3153 case CK_Pentium3: 3154 case CK_Pentium3M: 3155 case CK_C3_2: 3156 setFeatureEnabledImpl(Features, "sse", true); 3157 setFeatureEnabledImpl(Features, "fxsr", true); 3158 break; 3159 case CK_PentiumM: 3160 case CK_Pentium4: 3161 case CK_Pentium4M: 3162 case CK_x86_64: 3163 setFeatureEnabledImpl(Features, "sse2", true); 3164 setFeatureEnabledImpl(Features, "fxsr", true); 3165 break; 3166 case CK_Yonah: 3167 case CK_Prescott: 3168 case CK_Nocona: 3169 setFeatureEnabledImpl(Features, "sse3", true); 3170 setFeatureEnabledImpl(Features, "fxsr", true); 3171 setFeatureEnabledImpl(Features, "cx16", true); 3172 break; 3173 case CK_Core2: 3174 case CK_Bonnell: 3175 setFeatureEnabledImpl(Features, "ssse3", true); 3176 setFeatureEnabledImpl(Features, "fxsr", true); 3177 setFeatureEnabledImpl(Features, "cx16", true); 3178 break; 3179 case CK_Penryn: 3180 setFeatureEnabledImpl(Features, "sse4.1", true); 3181 setFeatureEnabledImpl(Features, "fxsr", true); 3182 setFeatureEnabledImpl(Features, "cx16", true); 3183 break; 3184 case CK_Cannonlake: 3185 setFeatureEnabledImpl(Features, "avx512ifma", true); 3186 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3187 setFeatureEnabledImpl(Features, "sha", true); 3188 LLVM_FALLTHROUGH; 3189 case CK_SkylakeServer: 3190 setFeatureEnabledImpl(Features, "avx512f", true); 3191 setFeatureEnabledImpl(Features, "avx512cd", true); 3192 setFeatureEnabledImpl(Features, "avx512dq", true); 3193 setFeatureEnabledImpl(Features, "avx512bw", true); 3194 setFeatureEnabledImpl(Features, "avx512vl", true); 3195 setFeatureEnabledImpl(Features, "pku", true); 3196 setFeatureEnabledImpl(Features, "clwb", true); 3197 LLVM_FALLTHROUGH; 3198 case CK_SkylakeClient: 3199 setFeatureEnabledImpl(Features, "xsavec", true); 3200 setFeatureEnabledImpl(Features, "xsaves", true); 3201 setFeatureEnabledImpl(Features, "mpx", true); 3202 setFeatureEnabledImpl(Features, "sgx", true); 3203 setFeatureEnabledImpl(Features, "clflushopt", true); 3204 setFeatureEnabledImpl(Features, "rtm", true); 3205 LLVM_FALLTHROUGH; 3206 case CK_Broadwell: 3207 setFeatureEnabledImpl(Features, "rdseed", true); 3208 setFeatureEnabledImpl(Features, "adx", true); 3209 LLVM_FALLTHROUGH; 3210 case CK_Haswell: 3211 setFeatureEnabledImpl(Features, "avx2", true); 3212 setFeatureEnabledImpl(Features, "lzcnt", true); 3213 setFeatureEnabledImpl(Features, "bmi", true); 3214 setFeatureEnabledImpl(Features, "bmi2", true); 3215 setFeatureEnabledImpl(Features, "fma", true); 3216 setFeatureEnabledImpl(Features, "movbe", true); 3217 LLVM_FALLTHROUGH; 3218 case CK_IvyBridge: 3219 setFeatureEnabledImpl(Features, "rdrnd", true); 3220 setFeatureEnabledImpl(Features, "f16c", true); 3221 setFeatureEnabledImpl(Features, "fsgsbase", true); 3222 LLVM_FALLTHROUGH; 3223 case CK_SandyBridge: 3224 setFeatureEnabledImpl(Features, "avx", true); 3225 setFeatureEnabledImpl(Features, "xsave", true); 3226 setFeatureEnabledImpl(Features, "xsaveopt", true); 3227 LLVM_FALLTHROUGH; 3228 case CK_Westmere: 3229 case CK_Silvermont: 3230 setFeatureEnabledImpl(Features, "aes", true); 3231 setFeatureEnabledImpl(Features, "pclmul", true); 3232 LLVM_FALLTHROUGH; 3233 case CK_Nehalem: 3234 setFeatureEnabledImpl(Features, "sse4.2", true); 3235 setFeatureEnabledImpl(Features, "fxsr", true); 3236 setFeatureEnabledImpl(Features, "cx16", true); 3237 break; 3238 case CK_KNL: 3239 setFeatureEnabledImpl(Features, "avx512f", true); 3240 setFeatureEnabledImpl(Features, "avx512cd", true); 3241 setFeatureEnabledImpl(Features, "avx512er", true); 3242 setFeatureEnabledImpl(Features, "avx512pf", true); 3243 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3244 setFeatureEnabledImpl(Features, "fxsr", true); 3245 setFeatureEnabledImpl(Features, "rdseed", true); 3246 setFeatureEnabledImpl(Features, "adx", true); 3247 setFeatureEnabledImpl(Features, "lzcnt", true); 3248 setFeatureEnabledImpl(Features, "bmi", true); 3249 setFeatureEnabledImpl(Features, "bmi2", true); 3250 setFeatureEnabledImpl(Features, "rtm", true); 3251 setFeatureEnabledImpl(Features, "fma", true); 3252 setFeatureEnabledImpl(Features, "rdrnd", true); 3253 setFeatureEnabledImpl(Features, "f16c", true); 3254 setFeatureEnabledImpl(Features, "fsgsbase", true); 3255 setFeatureEnabledImpl(Features, "aes", true); 3256 setFeatureEnabledImpl(Features, "pclmul", true); 3257 setFeatureEnabledImpl(Features, "cx16", true); 3258 setFeatureEnabledImpl(Features, "xsaveopt", true); 3259 setFeatureEnabledImpl(Features, "xsave", true); 3260 setFeatureEnabledImpl(Features, "movbe", true); 3261 break; 3262 case CK_K6_2: 3263 case CK_K6_3: 3264 case CK_WinChip2: 3265 case CK_C3: 3266 setFeatureEnabledImpl(Features, "3dnow", true); 3267 break; 3268 case CK_Athlon: 3269 case CK_AthlonThunderbird: 3270 case CK_Geode: 3271 setFeatureEnabledImpl(Features, "3dnowa", true); 3272 break; 3273 case CK_Athlon4: 3274 case CK_AthlonXP: 3275 case CK_AthlonMP: 3276 setFeatureEnabledImpl(Features, "sse", true); 3277 setFeatureEnabledImpl(Features, "3dnowa", true); 3278 setFeatureEnabledImpl(Features, "fxsr", true); 3279 break; 3280 case CK_K8: 3281 case CK_Opteron: 3282 case CK_Athlon64: 3283 case CK_AthlonFX: 3284 setFeatureEnabledImpl(Features, "sse2", true); 3285 setFeatureEnabledImpl(Features, "3dnowa", true); 3286 setFeatureEnabledImpl(Features, "fxsr", true); 3287 break; 3288 case CK_AMDFAM10: 3289 setFeatureEnabledImpl(Features, "sse4a", true); 3290 setFeatureEnabledImpl(Features, "lzcnt", true); 3291 setFeatureEnabledImpl(Features, "popcnt", true); 3292 LLVM_FALLTHROUGH; 3293 case CK_K8SSE3: 3294 case CK_OpteronSSE3: 3295 case CK_Athlon64SSE3: 3296 setFeatureEnabledImpl(Features, "sse3", true); 3297 setFeatureEnabledImpl(Features, "3dnowa", true); 3298 setFeatureEnabledImpl(Features, "fxsr", true); 3299 break; 3300 case CK_BTVER2: 3301 setFeatureEnabledImpl(Features, "avx", true); 3302 setFeatureEnabledImpl(Features, "aes", true); 3303 setFeatureEnabledImpl(Features, "pclmul", true); 3304 setFeatureEnabledImpl(Features, "bmi", true); 3305 setFeatureEnabledImpl(Features, "f16c", true); 3306 setFeatureEnabledImpl(Features, "xsaveopt", true); 3307 LLVM_FALLTHROUGH; 3308 case CK_BTVER1: 3309 setFeatureEnabledImpl(Features, "ssse3", true); 3310 setFeatureEnabledImpl(Features, "sse4a", true); 3311 setFeatureEnabledImpl(Features, "lzcnt", true); 3312 setFeatureEnabledImpl(Features, "popcnt", true); 3313 setFeatureEnabledImpl(Features, "prfchw", true); 3314 setFeatureEnabledImpl(Features, "cx16", true); 3315 setFeatureEnabledImpl(Features, "fxsr", true); 3316 break; 3317 case CK_ZNVER1: 3318 setFeatureEnabledImpl(Features, "adx", true); 3319 setFeatureEnabledImpl(Features, "aes", true); 3320 setFeatureEnabledImpl(Features, "avx2", true); 3321 setFeatureEnabledImpl(Features, "bmi", true); 3322 setFeatureEnabledImpl(Features, "bmi2", true); 3323 setFeatureEnabledImpl(Features, "clflushopt", true); 3324 setFeatureEnabledImpl(Features, "clzero", true); 3325 setFeatureEnabledImpl(Features, "cx16", true); 3326 setFeatureEnabledImpl(Features, "f16c", true); 3327 setFeatureEnabledImpl(Features, "fma", true); 3328 setFeatureEnabledImpl(Features, "fsgsbase", true); 3329 setFeatureEnabledImpl(Features, "fxsr", true); 3330 setFeatureEnabledImpl(Features, "lzcnt", true); 3331 setFeatureEnabledImpl(Features, "mwaitx", true); 3332 setFeatureEnabledImpl(Features, "movbe", true); 3333 setFeatureEnabledImpl(Features, "pclmul", true); 3334 setFeatureEnabledImpl(Features, "popcnt", true); 3335 setFeatureEnabledImpl(Features, "prfchw", true); 3336 setFeatureEnabledImpl(Features, "rdrnd", true); 3337 setFeatureEnabledImpl(Features, "rdseed", true); 3338 setFeatureEnabledImpl(Features, "sha", true); 3339 setFeatureEnabledImpl(Features, "sse4a", true); 3340 setFeatureEnabledImpl(Features, "xsave", true); 3341 setFeatureEnabledImpl(Features, "xsavec", true); 3342 setFeatureEnabledImpl(Features, "xsaveopt", true); 3343 setFeatureEnabledImpl(Features, "xsaves", true); 3344 break; 3345 case CK_BDVER4: 3346 setFeatureEnabledImpl(Features, "avx2", true); 3347 setFeatureEnabledImpl(Features, "bmi2", true); 3348 setFeatureEnabledImpl(Features, "mwaitx", true); 3349 LLVM_FALLTHROUGH; 3350 case CK_BDVER3: 3351 setFeatureEnabledImpl(Features, "fsgsbase", true); 3352 setFeatureEnabledImpl(Features, "xsaveopt", true); 3353 LLVM_FALLTHROUGH; 3354 case CK_BDVER2: 3355 setFeatureEnabledImpl(Features, "bmi", true); 3356 setFeatureEnabledImpl(Features, "fma", true); 3357 setFeatureEnabledImpl(Features, "f16c", true); 3358 setFeatureEnabledImpl(Features, "tbm", true); 3359 LLVM_FALLTHROUGH; 3360 case CK_BDVER1: 3361 // xop implies avx, sse4a and fma4. 3362 setFeatureEnabledImpl(Features, "xop", true); 3363 setFeatureEnabledImpl(Features, "lzcnt", true); 3364 setFeatureEnabledImpl(Features, "aes", true); 3365 setFeatureEnabledImpl(Features, "pclmul", true); 3366 setFeatureEnabledImpl(Features, "prfchw", true); 3367 setFeatureEnabledImpl(Features, "cx16", true); 3368 setFeatureEnabledImpl(Features, "fxsr", true); 3369 setFeatureEnabledImpl(Features, "xsave", true); 3370 break; 3371 } 3372 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3373 return false; 3374 3375 // Can't do this earlier because we need to be able to explicitly enable 3376 // or disable these features and the things that they depend upon. 3377 3378 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3379 auto I = Features.find("sse4.2"); 3380 if (I != Features.end() && I->getValue() && 3381 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3382 FeaturesVec.end()) 3383 Features["popcnt"] = true; 3384 3385 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3386 I = Features.find("3dnow"); 3387 if (I != Features.end() && I->getValue() && 3388 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3389 FeaturesVec.end()) 3390 Features["prfchw"] = true; 3391 3392 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3393 // then enable MMX. 3394 I = Features.find("sse"); 3395 if (I != Features.end() && I->getValue() && 3396 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3397 FeaturesVec.end()) 3398 Features["mmx"] = true; 3399 3400 return true; 3401 } 3402 3403 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3404 X86SSEEnum Level, bool Enabled) { 3405 if (Enabled) { 3406 switch (Level) { 3407 case AVX512F: 3408 Features["avx512f"] = true; 3409 case AVX2: 3410 Features["avx2"] = true; 3411 case AVX: 3412 Features["avx"] = true; 3413 Features["xsave"] = true; 3414 case SSE42: 3415 Features["sse4.2"] = true; 3416 case SSE41: 3417 Features["sse4.1"] = true; 3418 case SSSE3: 3419 Features["ssse3"] = true; 3420 case SSE3: 3421 Features["sse3"] = true; 3422 case SSE2: 3423 Features["sse2"] = true; 3424 case SSE1: 3425 Features["sse"] = true; 3426 case NoSSE: 3427 break; 3428 } 3429 return; 3430 } 3431 3432 switch (Level) { 3433 case NoSSE: 3434 case SSE1: 3435 Features["sse"] = false; 3436 case SSE2: 3437 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3438 Features["sha"] = false; 3439 case SSE3: 3440 Features["sse3"] = false; 3441 setXOPLevel(Features, NoXOP, false); 3442 case SSSE3: 3443 Features["ssse3"] = false; 3444 case SSE41: 3445 Features["sse4.1"] = false; 3446 case SSE42: 3447 Features["sse4.2"] = false; 3448 case AVX: 3449 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3450 Features["xsaveopt"] = false; 3451 setXOPLevel(Features, FMA4, false); 3452 case AVX2: 3453 Features["avx2"] = false; 3454 case AVX512F: 3455 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3456 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3457 Features["avx512vl"] = Features["avx512vbmi"] = 3458 Features["avx512ifma"] = false; 3459 } 3460 } 3461 3462 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3463 MMX3DNowEnum Level, bool Enabled) { 3464 if (Enabled) { 3465 switch (Level) { 3466 case AMD3DNowAthlon: 3467 Features["3dnowa"] = true; 3468 case AMD3DNow: 3469 Features["3dnow"] = true; 3470 case MMX: 3471 Features["mmx"] = true; 3472 case NoMMX3DNow: 3473 break; 3474 } 3475 return; 3476 } 3477 3478 switch (Level) { 3479 case NoMMX3DNow: 3480 case MMX: 3481 Features["mmx"] = false; 3482 case AMD3DNow: 3483 Features["3dnow"] = false; 3484 case AMD3DNowAthlon: 3485 Features["3dnowa"] = false; 3486 } 3487 } 3488 3489 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3490 bool Enabled) { 3491 if (Enabled) { 3492 switch (Level) { 3493 case XOP: 3494 Features["xop"] = true; 3495 case FMA4: 3496 Features["fma4"] = true; 3497 setSSELevel(Features, AVX, true); 3498 case SSE4A: 3499 Features["sse4a"] = true; 3500 setSSELevel(Features, SSE3, true); 3501 case NoXOP: 3502 break; 3503 } 3504 return; 3505 } 3506 3507 switch (Level) { 3508 case NoXOP: 3509 case SSE4A: 3510 Features["sse4a"] = false; 3511 case FMA4: 3512 Features["fma4"] = false; 3513 case XOP: 3514 Features["xop"] = false; 3515 } 3516 } 3517 3518 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3519 StringRef Name, bool Enabled) { 3520 // This is a bit of a hack to deal with the sse4 target feature when used 3521 // as part of the target attribute. We handle sse4 correctly everywhere 3522 // else. See below for more information on how we handle the sse4 options. 3523 if (Name != "sse4") 3524 Features[Name] = Enabled; 3525 3526 if (Name == "mmx") { 3527 setMMXLevel(Features, MMX, Enabled); 3528 } else if (Name == "sse") { 3529 setSSELevel(Features, SSE1, Enabled); 3530 } else if (Name == "sse2") { 3531 setSSELevel(Features, SSE2, Enabled); 3532 } else if (Name == "sse3") { 3533 setSSELevel(Features, SSE3, Enabled); 3534 } else if (Name == "ssse3") { 3535 setSSELevel(Features, SSSE3, Enabled); 3536 } else if (Name == "sse4.2") { 3537 setSSELevel(Features, SSE42, Enabled); 3538 } else if (Name == "sse4.1") { 3539 setSSELevel(Features, SSE41, Enabled); 3540 } else if (Name == "3dnow") { 3541 setMMXLevel(Features, AMD3DNow, Enabled); 3542 } else if (Name == "3dnowa") { 3543 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3544 } else if (Name == "aes") { 3545 if (Enabled) 3546 setSSELevel(Features, SSE2, Enabled); 3547 } else if (Name == "pclmul") { 3548 if (Enabled) 3549 setSSELevel(Features, SSE2, Enabled); 3550 } else if (Name == "avx") { 3551 setSSELevel(Features, AVX, Enabled); 3552 } else if (Name == "avx2") { 3553 setSSELevel(Features, AVX2, Enabled); 3554 } else if (Name == "avx512f") { 3555 setSSELevel(Features, AVX512F, Enabled); 3556 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3557 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3558 Name == "avx512vbmi" || Name == "avx512ifma") { 3559 if (Enabled) 3560 setSSELevel(Features, AVX512F, Enabled); 3561 // Enable BWI instruction if VBMI is being enabled. 3562 if (Name == "avx512vbmi" && Enabled) 3563 Features["avx512bw"] = true; 3564 // Also disable VBMI if BWI is being disabled. 3565 if (Name == "avx512bw" && !Enabled) 3566 Features["avx512vbmi"] = false; 3567 } else if (Name == "fma") { 3568 if (Enabled) 3569 setSSELevel(Features, AVX, Enabled); 3570 } else if (Name == "fma4") { 3571 setXOPLevel(Features, FMA4, Enabled); 3572 } else if (Name == "xop") { 3573 setXOPLevel(Features, XOP, Enabled); 3574 } else if (Name == "sse4a") { 3575 setXOPLevel(Features, SSE4A, Enabled); 3576 } else if (Name == "f16c") { 3577 if (Enabled) 3578 setSSELevel(Features, AVX, Enabled); 3579 } else if (Name == "sha") { 3580 if (Enabled) 3581 setSSELevel(Features, SSE2, Enabled); 3582 } else if (Name == "sse4") { 3583 // We can get here via the __target__ attribute since that's not controlled 3584 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3585 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3586 // disabled. 3587 if (Enabled) 3588 setSSELevel(Features, SSE42, Enabled); 3589 else 3590 setSSELevel(Features, SSE41, Enabled); 3591 } else if (Name == "xsave") { 3592 if (!Enabled) 3593 Features["xsaveopt"] = false; 3594 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3595 if (Enabled) 3596 Features["xsave"] = true; 3597 } 3598 } 3599 3600 /// handleTargetFeatures - Perform initialization based on the user 3601 /// configured set of features. 3602 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3603 DiagnosticsEngine &Diags) { 3604 for (const auto &Feature : Features) { 3605 if (Feature[0] != '+') 3606 continue; 3607 3608 if (Feature == "+aes") { 3609 HasAES = true; 3610 } else if (Feature == "+pclmul") { 3611 HasPCLMUL = true; 3612 } else if (Feature == "+lzcnt") { 3613 HasLZCNT = true; 3614 } else if (Feature == "+rdrnd") { 3615 HasRDRND = true; 3616 } else if (Feature == "+fsgsbase") { 3617 HasFSGSBASE = true; 3618 } else if (Feature == "+bmi") { 3619 HasBMI = true; 3620 } else if (Feature == "+bmi2") { 3621 HasBMI2 = true; 3622 } else if (Feature == "+popcnt") { 3623 HasPOPCNT = true; 3624 } else if (Feature == "+rtm") { 3625 HasRTM = true; 3626 } else if (Feature == "+prfchw") { 3627 HasPRFCHW = true; 3628 } else if (Feature == "+rdseed") { 3629 HasRDSEED = true; 3630 } else if (Feature == "+adx") { 3631 HasADX = true; 3632 } else if (Feature == "+tbm") { 3633 HasTBM = true; 3634 } else if (Feature == "+fma") { 3635 HasFMA = true; 3636 } else if (Feature == "+f16c") { 3637 HasF16C = true; 3638 } else if (Feature == "+avx512cd") { 3639 HasAVX512CD = true; 3640 } else if (Feature == "+avx512er") { 3641 HasAVX512ER = true; 3642 } else if (Feature == "+avx512pf") { 3643 HasAVX512PF = true; 3644 } else if (Feature == "+avx512dq") { 3645 HasAVX512DQ = true; 3646 } else if (Feature == "+avx512bw") { 3647 HasAVX512BW = true; 3648 } else if (Feature == "+avx512vl") { 3649 HasAVX512VL = true; 3650 } else if (Feature == "+avx512vbmi") { 3651 HasAVX512VBMI = true; 3652 } else if (Feature == "+avx512ifma") { 3653 HasAVX512IFMA = true; 3654 } else if (Feature == "+sha") { 3655 HasSHA = true; 3656 } else if (Feature == "+mpx") { 3657 HasMPX = true; 3658 } else if (Feature == "+movbe") { 3659 HasMOVBE = true; 3660 } else if (Feature == "+sgx") { 3661 HasSGX = true; 3662 } else if (Feature == "+cx16") { 3663 HasCX16 = true; 3664 } else if (Feature == "+fxsr") { 3665 HasFXSR = true; 3666 } else if (Feature == "+xsave") { 3667 HasXSAVE = true; 3668 } else if (Feature == "+xsaveopt") { 3669 HasXSAVEOPT = true; 3670 } else if (Feature == "+xsavec") { 3671 HasXSAVEC = true; 3672 } else if (Feature == "+xsaves") { 3673 HasXSAVES = true; 3674 } else if (Feature == "+mwaitx") { 3675 HasMWAITX = true; 3676 } else if (Feature == "+pku") { 3677 HasPKU = true; 3678 } else if (Feature == "+clflushopt") { 3679 HasCLFLUSHOPT = true; 3680 } else if (Feature == "+clwb") { 3681 HasCLWB = true; 3682 } else if (Feature == "+prefetchwt1") { 3683 HasPREFETCHWT1 = true; 3684 } else if (Feature == "+clzero") { 3685 HasCLZERO = true; 3686 } 3687 3688 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3689 .Case("+avx512f", AVX512F) 3690 .Case("+avx2", AVX2) 3691 .Case("+avx", AVX) 3692 .Case("+sse4.2", SSE42) 3693 .Case("+sse4.1", SSE41) 3694 .Case("+ssse3", SSSE3) 3695 .Case("+sse3", SSE3) 3696 .Case("+sse2", SSE2) 3697 .Case("+sse", SSE1) 3698 .Default(NoSSE); 3699 SSELevel = std::max(SSELevel, Level); 3700 3701 MMX3DNowEnum ThreeDNowLevel = 3702 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3703 .Case("+3dnowa", AMD3DNowAthlon) 3704 .Case("+3dnow", AMD3DNow) 3705 .Case("+mmx", MMX) 3706 .Default(NoMMX3DNow); 3707 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3708 3709 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3710 .Case("+xop", XOP) 3711 .Case("+fma4", FMA4) 3712 .Case("+sse4a", SSE4A) 3713 .Default(NoXOP); 3714 XOPLevel = std::max(XOPLevel, XLevel); 3715 } 3716 3717 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3718 // matches the selected sse level. 3719 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3720 (FPMath == FP_387 && SSELevel >= SSE1)) { 3721 Diags.Report(diag::err_target_unsupported_fpmath) << 3722 (FPMath == FP_SSE ? "sse" : "387"); 3723 return false; 3724 } 3725 3726 SimdDefaultAlign = 3727 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3728 return true; 3729 } 3730 3731 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3732 /// definitions for this particular subtarget. 3733 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3734 MacroBuilder &Builder) const { 3735 // Target identification. 3736 if (getTriple().getArch() == llvm::Triple::x86_64) { 3737 Builder.defineMacro("__amd64__"); 3738 Builder.defineMacro("__amd64"); 3739 Builder.defineMacro("__x86_64"); 3740 Builder.defineMacro("__x86_64__"); 3741 if (getTriple().getArchName() == "x86_64h") { 3742 Builder.defineMacro("__x86_64h"); 3743 Builder.defineMacro("__x86_64h__"); 3744 } 3745 } else { 3746 DefineStd(Builder, "i386", Opts); 3747 } 3748 3749 // Subtarget options. 3750 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3751 // truly should be based on -mtune options. 3752 switch (CPU) { 3753 case CK_Generic: 3754 break; 3755 case CK_i386: 3756 // The rest are coming from the i386 define above. 3757 Builder.defineMacro("__tune_i386__"); 3758 break; 3759 case CK_i486: 3760 case CK_WinChipC6: 3761 case CK_WinChip2: 3762 case CK_C3: 3763 defineCPUMacros(Builder, "i486"); 3764 break; 3765 case CK_PentiumMMX: 3766 Builder.defineMacro("__pentium_mmx__"); 3767 Builder.defineMacro("__tune_pentium_mmx__"); 3768 // Fallthrough 3769 case CK_i586: 3770 case CK_Pentium: 3771 defineCPUMacros(Builder, "i586"); 3772 defineCPUMacros(Builder, "pentium"); 3773 break; 3774 case CK_Pentium3: 3775 case CK_Pentium3M: 3776 case CK_PentiumM: 3777 Builder.defineMacro("__tune_pentium3__"); 3778 // Fallthrough 3779 case CK_Pentium2: 3780 case CK_C3_2: 3781 Builder.defineMacro("__tune_pentium2__"); 3782 // Fallthrough 3783 case CK_PentiumPro: 3784 Builder.defineMacro("__tune_i686__"); 3785 Builder.defineMacro("__tune_pentiumpro__"); 3786 // Fallthrough 3787 case CK_i686: 3788 Builder.defineMacro("__i686"); 3789 Builder.defineMacro("__i686__"); 3790 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3791 Builder.defineMacro("__pentiumpro"); 3792 Builder.defineMacro("__pentiumpro__"); 3793 break; 3794 case CK_Pentium4: 3795 case CK_Pentium4M: 3796 defineCPUMacros(Builder, "pentium4"); 3797 break; 3798 case CK_Yonah: 3799 case CK_Prescott: 3800 case CK_Nocona: 3801 defineCPUMacros(Builder, "nocona"); 3802 break; 3803 case CK_Core2: 3804 case CK_Penryn: 3805 defineCPUMacros(Builder, "core2"); 3806 break; 3807 case CK_Bonnell: 3808 defineCPUMacros(Builder, "atom"); 3809 break; 3810 case CK_Silvermont: 3811 defineCPUMacros(Builder, "slm"); 3812 break; 3813 case CK_Nehalem: 3814 case CK_Westmere: 3815 case CK_SandyBridge: 3816 case CK_IvyBridge: 3817 case CK_Haswell: 3818 case CK_Broadwell: 3819 case CK_SkylakeClient: 3820 // FIXME: Historically, we defined this legacy name, it would be nice to 3821 // remove it at some point. We've never exposed fine-grained names for 3822 // recent primary x86 CPUs, and we should keep it that way. 3823 defineCPUMacros(Builder, "corei7"); 3824 break; 3825 case CK_SkylakeServer: 3826 defineCPUMacros(Builder, "skx"); 3827 break; 3828 case CK_Cannonlake: 3829 break; 3830 case CK_KNL: 3831 defineCPUMacros(Builder, "knl"); 3832 break; 3833 case CK_Lakemont: 3834 Builder.defineMacro("__tune_lakemont__"); 3835 break; 3836 case CK_K6_2: 3837 Builder.defineMacro("__k6_2__"); 3838 Builder.defineMacro("__tune_k6_2__"); 3839 // Fallthrough 3840 case CK_K6_3: 3841 if (CPU != CK_K6_2) { // In case of fallthrough 3842 // FIXME: GCC may be enabling these in cases where some other k6 3843 // architecture is specified but -m3dnow is explicitly provided. The 3844 // exact semantics need to be determined and emulated here. 3845 Builder.defineMacro("__k6_3__"); 3846 Builder.defineMacro("__tune_k6_3__"); 3847 } 3848 // Fallthrough 3849 case CK_K6: 3850 defineCPUMacros(Builder, "k6"); 3851 break; 3852 case CK_Athlon: 3853 case CK_AthlonThunderbird: 3854 case CK_Athlon4: 3855 case CK_AthlonXP: 3856 case CK_AthlonMP: 3857 defineCPUMacros(Builder, "athlon"); 3858 if (SSELevel != NoSSE) { 3859 Builder.defineMacro("__athlon_sse__"); 3860 Builder.defineMacro("__tune_athlon_sse__"); 3861 } 3862 break; 3863 case CK_K8: 3864 case CK_K8SSE3: 3865 case CK_x86_64: 3866 case CK_Opteron: 3867 case CK_OpteronSSE3: 3868 case CK_Athlon64: 3869 case CK_Athlon64SSE3: 3870 case CK_AthlonFX: 3871 defineCPUMacros(Builder, "k8"); 3872 break; 3873 case CK_AMDFAM10: 3874 defineCPUMacros(Builder, "amdfam10"); 3875 break; 3876 case CK_BTVER1: 3877 defineCPUMacros(Builder, "btver1"); 3878 break; 3879 case CK_BTVER2: 3880 defineCPUMacros(Builder, "btver2"); 3881 break; 3882 case CK_BDVER1: 3883 defineCPUMacros(Builder, "bdver1"); 3884 break; 3885 case CK_BDVER2: 3886 defineCPUMacros(Builder, "bdver2"); 3887 break; 3888 case CK_BDVER3: 3889 defineCPUMacros(Builder, "bdver3"); 3890 break; 3891 case CK_BDVER4: 3892 defineCPUMacros(Builder, "bdver4"); 3893 break; 3894 case CK_ZNVER1: 3895 defineCPUMacros(Builder, "znver1"); 3896 break; 3897 case CK_Geode: 3898 defineCPUMacros(Builder, "geode"); 3899 break; 3900 } 3901 3902 // Target properties. 3903 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3904 3905 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3906 // functions in glibc header files that use FP Stack inline asm which the 3907 // backend can't deal with (PR879). 3908 Builder.defineMacro("__NO_MATH_INLINES"); 3909 3910 if (HasAES) 3911 Builder.defineMacro("__AES__"); 3912 3913 if (HasPCLMUL) 3914 Builder.defineMacro("__PCLMUL__"); 3915 3916 if (HasLZCNT) 3917 Builder.defineMacro("__LZCNT__"); 3918 3919 if (HasRDRND) 3920 Builder.defineMacro("__RDRND__"); 3921 3922 if (HasFSGSBASE) 3923 Builder.defineMacro("__FSGSBASE__"); 3924 3925 if (HasBMI) 3926 Builder.defineMacro("__BMI__"); 3927 3928 if (HasBMI2) 3929 Builder.defineMacro("__BMI2__"); 3930 3931 if (HasPOPCNT) 3932 Builder.defineMacro("__POPCNT__"); 3933 3934 if (HasRTM) 3935 Builder.defineMacro("__RTM__"); 3936 3937 if (HasPRFCHW) 3938 Builder.defineMacro("__PRFCHW__"); 3939 3940 if (HasRDSEED) 3941 Builder.defineMacro("__RDSEED__"); 3942 3943 if (HasADX) 3944 Builder.defineMacro("__ADX__"); 3945 3946 if (HasTBM) 3947 Builder.defineMacro("__TBM__"); 3948 3949 if (HasMWAITX) 3950 Builder.defineMacro("__MWAITX__"); 3951 3952 switch (XOPLevel) { 3953 case XOP: 3954 Builder.defineMacro("__XOP__"); 3955 case FMA4: 3956 Builder.defineMacro("__FMA4__"); 3957 case SSE4A: 3958 Builder.defineMacro("__SSE4A__"); 3959 case NoXOP: 3960 break; 3961 } 3962 3963 if (HasFMA) 3964 Builder.defineMacro("__FMA__"); 3965 3966 if (HasF16C) 3967 Builder.defineMacro("__F16C__"); 3968 3969 if (HasAVX512CD) 3970 Builder.defineMacro("__AVX512CD__"); 3971 if (HasAVX512ER) 3972 Builder.defineMacro("__AVX512ER__"); 3973 if (HasAVX512PF) 3974 Builder.defineMacro("__AVX512PF__"); 3975 if (HasAVX512DQ) 3976 Builder.defineMacro("__AVX512DQ__"); 3977 if (HasAVX512BW) 3978 Builder.defineMacro("__AVX512BW__"); 3979 if (HasAVX512VL) 3980 Builder.defineMacro("__AVX512VL__"); 3981 if (HasAVX512VBMI) 3982 Builder.defineMacro("__AVX512VBMI__"); 3983 if (HasAVX512IFMA) 3984 Builder.defineMacro("__AVX512IFMA__"); 3985 3986 if (HasSHA) 3987 Builder.defineMacro("__SHA__"); 3988 3989 if (HasFXSR) 3990 Builder.defineMacro("__FXSR__"); 3991 if (HasXSAVE) 3992 Builder.defineMacro("__XSAVE__"); 3993 if (HasXSAVEOPT) 3994 Builder.defineMacro("__XSAVEOPT__"); 3995 if (HasXSAVEC) 3996 Builder.defineMacro("__XSAVEC__"); 3997 if (HasXSAVES) 3998 Builder.defineMacro("__XSAVES__"); 3999 if (HasPKU) 4000 Builder.defineMacro("__PKU__"); 4001 if (HasCX16) 4002 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 4003 if (HasCLFLUSHOPT) 4004 Builder.defineMacro("__CLFLUSHOPT__"); 4005 if (HasCLWB) 4006 Builder.defineMacro("__CLWB__"); 4007 if (HasMPX) 4008 Builder.defineMacro("__MPX__"); 4009 if (HasSGX) 4010 Builder.defineMacro("__SGX__"); 4011 if (HasPREFETCHWT1) 4012 Builder.defineMacro("__PREFETCHWT1__"); 4013 if (HasCLZERO) 4014 Builder.defineMacro("__CLZERO__"); 4015 4016 // Each case falls through to the previous one here. 4017 switch (SSELevel) { 4018 case AVX512F: 4019 Builder.defineMacro("__AVX512F__"); 4020 case AVX2: 4021 Builder.defineMacro("__AVX2__"); 4022 case AVX: 4023 Builder.defineMacro("__AVX__"); 4024 case SSE42: 4025 Builder.defineMacro("__SSE4_2__"); 4026 case SSE41: 4027 Builder.defineMacro("__SSE4_1__"); 4028 case SSSE3: 4029 Builder.defineMacro("__SSSE3__"); 4030 case SSE3: 4031 Builder.defineMacro("__SSE3__"); 4032 case SSE2: 4033 Builder.defineMacro("__SSE2__"); 4034 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 4035 case SSE1: 4036 Builder.defineMacro("__SSE__"); 4037 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 4038 case NoSSE: 4039 break; 4040 } 4041 4042 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 4043 switch (SSELevel) { 4044 case AVX512F: 4045 case AVX2: 4046 case AVX: 4047 case SSE42: 4048 case SSE41: 4049 case SSSE3: 4050 case SSE3: 4051 case SSE2: 4052 Builder.defineMacro("_M_IX86_FP", Twine(2)); 4053 break; 4054 case SSE1: 4055 Builder.defineMacro("_M_IX86_FP", Twine(1)); 4056 break; 4057 default: 4058 Builder.defineMacro("_M_IX86_FP", Twine(0)); 4059 } 4060 } 4061 4062 // Each case falls through to the previous one here. 4063 switch (MMX3DNowLevel) { 4064 case AMD3DNowAthlon: 4065 Builder.defineMacro("__3dNOW_A__"); 4066 case AMD3DNow: 4067 Builder.defineMacro("__3dNOW__"); 4068 case MMX: 4069 Builder.defineMacro("__MMX__"); 4070 case NoMMX3DNow: 4071 break; 4072 } 4073 4074 if (CPU >= CK_i486) { 4075 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4076 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4077 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4078 } 4079 if (CPU >= CK_i586) 4080 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4081 } 4082 4083 bool X86TargetInfo::hasFeature(StringRef Feature) const { 4084 return llvm::StringSwitch<bool>(Feature) 4085 .Case("aes", HasAES) 4086 .Case("avx", SSELevel >= AVX) 4087 .Case("avx2", SSELevel >= AVX2) 4088 .Case("avx512f", SSELevel >= AVX512F) 4089 .Case("avx512cd", HasAVX512CD) 4090 .Case("avx512er", HasAVX512ER) 4091 .Case("avx512pf", HasAVX512PF) 4092 .Case("avx512dq", HasAVX512DQ) 4093 .Case("avx512bw", HasAVX512BW) 4094 .Case("avx512vl", HasAVX512VL) 4095 .Case("avx512vbmi", HasAVX512VBMI) 4096 .Case("avx512ifma", HasAVX512IFMA) 4097 .Case("bmi", HasBMI) 4098 .Case("bmi2", HasBMI2) 4099 .Case("clflushopt", HasCLFLUSHOPT) 4100 .Case("clwb", HasCLWB) 4101 .Case("clzero", HasCLZERO) 4102 .Case("cx16", HasCX16) 4103 .Case("f16c", HasF16C) 4104 .Case("fma", HasFMA) 4105 .Case("fma4", XOPLevel >= FMA4) 4106 .Case("fsgsbase", HasFSGSBASE) 4107 .Case("fxsr", HasFXSR) 4108 .Case("lzcnt", HasLZCNT) 4109 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4110 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4111 .Case("mmx", MMX3DNowLevel >= MMX) 4112 .Case("movbe", HasMOVBE) 4113 .Case("mpx", HasMPX) 4114 .Case("pclmul", HasPCLMUL) 4115 .Case("pku", HasPKU) 4116 .Case("popcnt", HasPOPCNT) 4117 .Case("prefetchwt1", HasPREFETCHWT1) 4118 .Case("prfchw", HasPRFCHW) 4119 .Case("rdrnd", HasRDRND) 4120 .Case("rdseed", HasRDSEED) 4121 .Case("rtm", HasRTM) 4122 .Case("sgx", HasSGX) 4123 .Case("sha", HasSHA) 4124 .Case("sse", SSELevel >= SSE1) 4125 .Case("sse2", SSELevel >= SSE2) 4126 .Case("sse3", SSELevel >= SSE3) 4127 .Case("ssse3", SSELevel >= SSSE3) 4128 .Case("sse4.1", SSELevel >= SSE41) 4129 .Case("sse4.2", SSELevel >= SSE42) 4130 .Case("sse4a", XOPLevel >= SSE4A) 4131 .Case("tbm", HasTBM) 4132 .Case("x86", true) 4133 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4134 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4135 .Case("xop", XOPLevel >= XOP) 4136 .Case("xsave", HasXSAVE) 4137 .Case("xsavec", HasXSAVEC) 4138 .Case("xsaves", HasXSAVES) 4139 .Case("xsaveopt", HasXSAVEOPT) 4140 .Default(false); 4141 } 4142 4143 // We can't use a generic validation scheme for the features accepted here 4144 // versus subtarget features accepted in the target attribute because the 4145 // bitfield structure that's initialized in the runtime only supports the 4146 // below currently rather than the full range of subtarget features. (See 4147 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4148 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4149 return llvm::StringSwitch<bool>(FeatureStr) 4150 .Case("cmov", true) 4151 .Case("mmx", true) 4152 .Case("popcnt", true) 4153 .Case("sse", true) 4154 .Case("sse2", true) 4155 .Case("sse3", true) 4156 .Case("ssse3", true) 4157 .Case("sse4.1", true) 4158 .Case("sse4.2", true) 4159 .Case("avx", true) 4160 .Case("avx2", true) 4161 .Case("sse4a", true) 4162 .Case("fma4", true) 4163 .Case("xop", true) 4164 .Case("fma", true) 4165 .Case("avx512f", true) 4166 .Case("bmi", true) 4167 .Case("bmi2", true) 4168 .Case("aes", true) 4169 .Case("pclmul", true) 4170 .Case("avx512vl", true) 4171 .Case("avx512bw", true) 4172 .Case("avx512dq", true) 4173 .Case("avx512cd", true) 4174 .Case("avx512er", true) 4175 .Case("avx512pf", true) 4176 .Case("avx512vbmi", true) 4177 .Case("avx512ifma", true) 4178 .Default(false); 4179 } 4180 4181 bool 4182 X86TargetInfo::validateAsmConstraint(const char *&Name, 4183 TargetInfo::ConstraintInfo &Info) const { 4184 switch (*Name) { 4185 default: return false; 4186 // Constant constraints. 4187 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4188 // instructions. 4189 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4190 // x86_64 instructions. 4191 case 's': 4192 Info.setRequiresImmediate(); 4193 return true; 4194 case 'I': 4195 Info.setRequiresImmediate(0, 31); 4196 return true; 4197 case 'J': 4198 Info.setRequiresImmediate(0, 63); 4199 return true; 4200 case 'K': 4201 Info.setRequiresImmediate(-128, 127); 4202 return true; 4203 case 'L': 4204 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4205 return true; 4206 case 'M': 4207 Info.setRequiresImmediate(0, 3); 4208 return true; 4209 case 'N': 4210 Info.setRequiresImmediate(0, 255); 4211 return true; 4212 case 'O': 4213 Info.setRequiresImmediate(0, 127); 4214 return true; 4215 // Register constraints. 4216 case 'Y': // 'Y' is the first character for several 2-character constraints. 4217 // Shift the pointer to the second character of the constraint. 4218 Name++; 4219 switch (*Name) { 4220 default: 4221 return false; 4222 case '0': // First SSE register. 4223 case 't': // Any SSE register, when SSE2 is enabled. 4224 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4225 case 'm': // Any MMX register, when inter-unit moves enabled. 4226 case 'k': // AVX512 arch mask registers: k1-k7. 4227 Info.setAllowsRegister(); 4228 return true; 4229 } 4230 case 'f': // Any x87 floating point stack register. 4231 // Constraint 'f' cannot be used for output operands. 4232 if (Info.ConstraintStr[0] == '=') 4233 return false; 4234 Info.setAllowsRegister(); 4235 return true; 4236 case 'a': // eax. 4237 case 'b': // ebx. 4238 case 'c': // ecx. 4239 case 'd': // edx. 4240 case 'S': // esi. 4241 case 'D': // edi. 4242 case 'A': // edx:eax. 4243 case 't': // Top of floating point stack. 4244 case 'u': // Second from top of floating point stack. 4245 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4246 case 'y': // Any MMX register. 4247 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4248 case 'x': // Any SSE register. 4249 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4250 // for intermideate k reg operations). 4251 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4252 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4253 case 'l': // "Index" registers: any general register that can be used as an 4254 // index in a base+index memory access. 4255 Info.setAllowsRegister(); 4256 return true; 4257 // Floating point constant constraints. 4258 case 'C': // SSE floating point constant. 4259 case 'G': // x87 floating point constant. 4260 return true; 4261 } 4262 } 4263 4264 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4265 unsigned Size) const { 4266 // Strip off constraint modifiers. 4267 while (Constraint[0] == '=' || 4268 Constraint[0] == '+' || 4269 Constraint[0] == '&') 4270 Constraint = Constraint.substr(1); 4271 4272 return validateOperandSize(Constraint, Size); 4273 } 4274 4275 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4276 unsigned Size) const { 4277 return validateOperandSize(Constraint, Size); 4278 } 4279 4280 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4281 unsigned Size) const { 4282 switch (Constraint[0]) { 4283 default: break; 4284 case 'k': 4285 // Registers k0-k7 (AVX512) size limit is 64 bit. 4286 case 'y': 4287 return Size <= 64; 4288 case 'f': 4289 case 't': 4290 case 'u': 4291 return Size <= 128; 4292 case 'v': 4293 case 'x': 4294 if (SSELevel >= AVX512F) 4295 // 512-bit zmm registers can be used if target supports AVX512F. 4296 return Size <= 512U; 4297 else if (SSELevel >= AVX) 4298 // 256-bit ymm registers can be used if target supports AVX. 4299 return Size <= 256U; 4300 return Size <= 128U; 4301 case 'Y': 4302 // 'Y' is the first character for several 2-character constraints. 4303 switch (Constraint[1]) { 4304 default: break; 4305 case 'm': 4306 // 'Ym' is synonymous with 'y'. 4307 case 'k': 4308 return Size <= 64; 4309 case 'i': 4310 case 't': 4311 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4312 if (SSELevel >= AVX512F) 4313 return Size <= 512U; 4314 else if (SSELevel >= AVX) 4315 return Size <= 256U; 4316 return SSELevel >= SSE2 && Size <= 128U; 4317 } 4318 4319 } 4320 4321 return true; 4322 } 4323 4324 std::string 4325 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4326 switch (*Constraint) { 4327 case 'a': return std::string("{ax}"); 4328 case 'b': return std::string("{bx}"); 4329 case 'c': return std::string("{cx}"); 4330 case 'd': return std::string("{dx}"); 4331 case 'S': return std::string("{si}"); 4332 case 'D': return std::string("{di}"); 4333 case 'p': // address 4334 return std::string("im"); 4335 case 't': // top of floating point stack. 4336 return std::string("{st}"); 4337 case 'u': // second from top of floating point stack. 4338 return std::string("{st(1)}"); // second from top of floating point stack. 4339 case 'Y': 4340 switch (Constraint[1]) { 4341 default: 4342 // Break from inner switch and fall through (copy single char), 4343 // continue parsing after copying the current constraint into 4344 // the return string. 4345 break; 4346 case 'k': 4347 // "^" hints llvm that this is a 2 letter constraint. 4348 // "Constraint++" is used to promote the string iterator 4349 // to the next constraint. 4350 return std::string("^") + std::string(Constraint++, 2); 4351 } 4352 LLVM_FALLTHROUGH; 4353 default: 4354 return std::string(1, *Constraint); 4355 } 4356 } 4357 4358 // X86-32 generic target 4359 class X86_32TargetInfo : public X86TargetInfo { 4360 public: 4361 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4362 : X86TargetInfo(Triple, Opts) { 4363 DoubleAlign = LongLongAlign = 32; 4364 LongDoubleWidth = 96; 4365 LongDoubleAlign = 32; 4366 SuitableAlign = 128; 4367 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4368 SizeType = UnsignedInt; 4369 PtrDiffType = SignedInt; 4370 IntPtrType = SignedInt; 4371 RegParmMax = 3; 4372 4373 // Use fpret for all types. 4374 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4375 (1 << TargetInfo::Double) | 4376 (1 << TargetInfo::LongDouble)); 4377 4378 // x86-32 has atomics up to 8 bytes 4379 // FIXME: Check that we actually have cmpxchg8b before setting 4380 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4381 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4382 } 4383 BuiltinVaListKind getBuiltinVaListKind() const override { 4384 return TargetInfo::CharPtrBuiltinVaList; 4385 } 4386 4387 int getEHDataRegisterNumber(unsigned RegNo) const override { 4388 if (RegNo == 0) return 0; 4389 if (RegNo == 1) return 2; 4390 return -1; 4391 } 4392 bool validateOperandSize(StringRef Constraint, 4393 unsigned Size) const override { 4394 switch (Constraint[0]) { 4395 default: break; 4396 case 'R': 4397 case 'q': 4398 case 'Q': 4399 case 'a': 4400 case 'b': 4401 case 'c': 4402 case 'd': 4403 case 'S': 4404 case 'D': 4405 return Size <= 32; 4406 case 'A': 4407 return Size <= 64; 4408 } 4409 4410 return X86TargetInfo::validateOperandSize(Constraint, Size); 4411 } 4412 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4413 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4414 Builtin::FirstTSBuiltin + 1); 4415 } 4416 }; 4417 4418 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4419 public: 4420 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4421 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4422 4423 unsigned getFloatEvalMethod() const override { 4424 unsigned Major, Minor, Micro; 4425 getTriple().getOSVersion(Major, Minor, Micro); 4426 // New NetBSD uses the default rounding mode. 4427 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4428 return X86_32TargetInfo::getFloatEvalMethod(); 4429 // NetBSD before 6.99.26 defaults to "double" rounding. 4430 return 1; 4431 } 4432 }; 4433 4434 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4435 public: 4436 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4437 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4438 SizeType = UnsignedLong; 4439 IntPtrType = SignedLong; 4440 PtrDiffType = SignedLong; 4441 } 4442 }; 4443 4444 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4445 public: 4446 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4447 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4448 SizeType = UnsignedLong; 4449 IntPtrType = SignedLong; 4450 PtrDiffType = SignedLong; 4451 } 4452 }; 4453 4454 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4455 public: 4456 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4457 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4458 LongDoubleWidth = 128; 4459 LongDoubleAlign = 128; 4460 SuitableAlign = 128; 4461 MaxVectorAlign = 256; 4462 // The watchOS simulator uses the builtin bool type for Objective-C. 4463 llvm::Triple T = llvm::Triple(Triple); 4464 if (T.isWatchOS()) 4465 UseSignedCharForObjCBool = false; 4466 SizeType = UnsignedLong; 4467 IntPtrType = SignedLong; 4468 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4469 HasAlignMac68kSupport = true; 4470 } 4471 4472 bool handleTargetFeatures(std::vector<std::string> &Features, 4473 DiagnosticsEngine &Diags) override { 4474 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4475 Diags)) 4476 return false; 4477 // We now know the features we have: we can decide how to align vectors. 4478 MaxVectorAlign = 4479 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4480 return true; 4481 } 4482 }; 4483 4484 // x86-32 Windows target 4485 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4486 public: 4487 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4488 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4489 WCharType = UnsignedShort; 4490 DoubleAlign = LongLongAlign = 64; 4491 bool IsWinCOFF = 4492 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4493 resetDataLayout(IsWinCOFF 4494 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4495 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4496 } 4497 void getTargetDefines(const LangOptions &Opts, 4498 MacroBuilder &Builder) const override { 4499 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4500 } 4501 }; 4502 4503 // x86-32 Windows Visual Studio target 4504 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4505 public: 4506 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4507 const TargetOptions &Opts) 4508 : WindowsX86_32TargetInfo(Triple, Opts) { 4509 LongDoubleWidth = LongDoubleAlign = 64; 4510 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4511 } 4512 void getTargetDefines(const LangOptions &Opts, 4513 MacroBuilder &Builder) const override { 4514 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4515 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4516 // The value of the following reflects processor type. 4517 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4518 // We lost the original triple, so we use the default. 4519 Builder.defineMacro("_M_IX86", "600"); 4520 } 4521 }; 4522 4523 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4524 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4525 // supports __declspec natively under -fms-extensions, but we define a no-op 4526 // __declspec macro anyway for pre-processor compatibility. 4527 if (Opts.MicrosoftExt) 4528 Builder.defineMacro("__declspec", "__declspec"); 4529 else 4530 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4531 4532 if (!Opts.MicrosoftExt) { 4533 // Provide macros for all the calling convention keywords. Provide both 4534 // single and double underscore prefixed variants. These are available on 4535 // x64 as well as x86, even though they have no effect. 4536 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4537 for (const char *CC : CCs) { 4538 std::string GCCSpelling = "__attribute__((__"; 4539 GCCSpelling += CC; 4540 GCCSpelling += "__))"; 4541 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4542 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4543 } 4544 } 4545 } 4546 4547 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4548 Builder.defineMacro("__MSVCRT__"); 4549 Builder.defineMacro("__MINGW32__"); 4550 addCygMingDefines(Opts, Builder); 4551 } 4552 4553 // x86-32 MinGW target 4554 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4555 public: 4556 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4557 : WindowsX86_32TargetInfo(Triple, Opts) {} 4558 void getTargetDefines(const LangOptions &Opts, 4559 MacroBuilder &Builder) const override { 4560 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4561 DefineStd(Builder, "WIN32", Opts); 4562 DefineStd(Builder, "WINNT", Opts); 4563 Builder.defineMacro("_X86_"); 4564 addMinGWDefines(Opts, Builder); 4565 } 4566 }; 4567 4568 // x86-32 Cygwin target 4569 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4570 public: 4571 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4572 : X86_32TargetInfo(Triple, Opts) { 4573 WCharType = UnsignedShort; 4574 DoubleAlign = LongLongAlign = 64; 4575 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4576 } 4577 void getTargetDefines(const LangOptions &Opts, 4578 MacroBuilder &Builder) const override { 4579 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4580 Builder.defineMacro("_X86_"); 4581 Builder.defineMacro("__CYGWIN__"); 4582 Builder.defineMacro("__CYGWIN32__"); 4583 addCygMingDefines(Opts, Builder); 4584 DefineStd(Builder, "unix", Opts); 4585 if (Opts.CPlusPlus) 4586 Builder.defineMacro("_GNU_SOURCE"); 4587 } 4588 }; 4589 4590 // x86-32 Haiku target 4591 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4592 public: 4593 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4594 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4595 } 4596 void getTargetDefines(const LangOptions &Opts, 4597 MacroBuilder &Builder) const override { 4598 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4599 Builder.defineMacro("__INTEL__"); 4600 } 4601 }; 4602 4603 // X86-32 MCU target 4604 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4605 public: 4606 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4607 : X86_32TargetInfo(Triple, Opts) { 4608 LongDoubleWidth = 64; 4609 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4610 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4611 WIntType = UnsignedInt; 4612 } 4613 4614 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4615 // On MCU we support only C calling convention. 4616 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4617 } 4618 4619 void getTargetDefines(const LangOptions &Opts, 4620 MacroBuilder &Builder) const override { 4621 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4622 Builder.defineMacro("__iamcu"); 4623 Builder.defineMacro("__iamcu__"); 4624 } 4625 4626 bool allowsLargerPreferedTypeAlignment() const override { 4627 return false; 4628 } 4629 }; 4630 4631 // RTEMS Target 4632 template<typename Target> 4633 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4634 protected: 4635 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4636 MacroBuilder &Builder) const override { 4637 // RTEMS defines; list based off of gcc output 4638 4639 Builder.defineMacro("__rtems__"); 4640 Builder.defineMacro("__ELF__"); 4641 } 4642 4643 public: 4644 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4645 : OSTargetInfo<Target>(Triple, Opts) { 4646 switch (Triple.getArch()) { 4647 default: 4648 case llvm::Triple::x86: 4649 // this->MCountName = ".mcount"; 4650 break; 4651 case llvm::Triple::mips: 4652 case llvm::Triple::mipsel: 4653 case llvm::Triple::ppc: 4654 case llvm::Triple::ppc64: 4655 case llvm::Triple::ppc64le: 4656 // this->MCountName = "_mcount"; 4657 break; 4658 case llvm::Triple::arm: 4659 // this->MCountName = "__mcount"; 4660 break; 4661 } 4662 } 4663 }; 4664 4665 // x86-32 RTEMS target 4666 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4667 public: 4668 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4669 : X86_32TargetInfo(Triple, Opts) { 4670 SizeType = UnsignedLong; 4671 IntPtrType = SignedLong; 4672 PtrDiffType = SignedLong; 4673 } 4674 void getTargetDefines(const LangOptions &Opts, 4675 MacroBuilder &Builder) const override { 4676 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4677 Builder.defineMacro("__INTEL__"); 4678 Builder.defineMacro("__rtems__"); 4679 } 4680 }; 4681 4682 // x86-64 generic target 4683 class X86_64TargetInfo : public X86TargetInfo { 4684 public: 4685 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4686 : X86TargetInfo(Triple, Opts) { 4687 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4688 bool IsWinCOFF = 4689 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4690 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4691 LongDoubleWidth = 128; 4692 LongDoubleAlign = 128; 4693 LargeArrayMinWidth = 128; 4694 LargeArrayAlign = 128; 4695 SuitableAlign = 128; 4696 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4697 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4698 IntPtrType = IsX32 ? SignedInt : SignedLong; 4699 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4700 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4701 RegParmMax = 6; 4702 4703 // Pointers are 32-bit in x32. 4704 resetDataLayout(IsX32 4705 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4706 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4707 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4708 4709 // Use fpret only for long double. 4710 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4711 4712 // Use fp2ret for _Complex long double. 4713 ComplexLongDoubleUsesFP2Ret = true; 4714 4715 // Make __builtin_ms_va_list available. 4716 HasBuiltinMSVaList = true; 4717 4718 // x86-64 has atomics up to 16 bytes. 4719 MaxAtomicPromoteWidth = 128; 4720 MaxAtomicInlineWidth = 128; 4721 } 4722 BuiltinVaListKind getBuiltinVaListKind() const override { 4723 return TargetInfo::X86_64ABIBuiltinVaList; 4724 } 4725 4726 int getEHDataRegisterNumber(unsigned RegNo) const override { 4727 if (RegNo == 0) return 0; 4728 if (RegNo == 1) return 1; 4729 return -1; 4730 } 4731 4732 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4733 switch (CC) { 4734 case CC_C: 4735 case CC_Swift: 4736 case CC_X86VectorCall: 4737 case CC_IntelOclBicc: 4738 case CC_X86_64Win64: 4739 case CC_PreserveMost: 4740 case CC_PreserveAll: 4741 case CC_X86RegCall: 4742 return CCCR_OK; 4743 default: 4744 return CCCR_Warning; 4745 } 4746 } 4747 4748 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4749 return CC_C; 4750 } 4751 4752 // for x32 we need it here explicitly 4753 bool hasInt128Type() const override { return true; } 4754 unsigned getUnwindWordWidth() const override { return 64; } 4755 unsigned getRegisterWidth() const override { return 64; } 4756 4757 bool validateGlobalRegisterVariable(StringRef RegName, 4758 unsigned RegSize, 4759 bool &HasSizeMismatch) const override { 4760 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4761 // handle. 4762 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4763 // Check that the register size is 64-bit. 4764 HasSizeMismatch = RegSize != 64; 4765 return true; 4766 } 4767 4768 // Check if the register is a 32-bit register the backend can handle. 4769 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4770 HasSizeMismatch); 4771 } 4772 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4773 return llvm::makeArrayRef(BuiltinInfoX86, 4774 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4775 } 4776 }; 4777 4778 // x86-64 Windows target 4779 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4780 public: 4781 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4782 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4783 WCharType = UnsignedShort; 4784 LongWidth = LongAlign = 32; 4785 DoubleAlign = LongLongAlign = 64; 4786 IntMaxType = SignedLongLong; 4787 Int64Type = SignedLongLong; 4788 SizeType = UnsignedLongLong; 4789 PtrDiffType = SignedLongLong; 4790 IntPtrType = SignedLongLong; 4791 } 4792 4793 void getTargetDefines(const LangOptions &Opts, 4794 MacroBuilder &Builder) const override { 4795 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4796 Builder.defineMacro("_WIN64"); 4797 } 4798 4799 BuiltinVaListKind getBuiltinVaListKind() const override { 4800 return TargetInfo::CharPtrBuiltinVaList; 4801 } 4802 4803 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4804 switch (CC) { 4805 case CC_X86StdCall: 4806 case CC_X86ThisCall: 4807 case CC_X86FastCall: 4808 return CCCR_Ignore; 4809 case CC_C: 4810 case CC_X86VectorCall: 4811 case CC_IntelOclBicc: 4812 case CC_X86_64SysV: 4813 case CC_Swift: 4814 case CC_X86RegCall: 4815 return CCCR_OK; 4816 default: 4817 return CCCR_Warning; 4818 } 4819 } 4820 }; 4821 4822 // x86-64 Windows Visual Studio target 4823 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4824 public: 4825 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4826 const TargetOptions &Opts) 4827 : WindowsX86_64TargetInfo(Triple, Opts) { 4828 LongDoubleWidth = LongDoubleAlign = 64; 4829 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4830 } 4831 void getTargetDefines(const LangOptions &Opts, 4832 MacroBuilder &Builder) const override { 4833 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4834 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4835 Builder.defineMacro("_M_X64", "100"); 4836 Builder.defineMacro("_M_AMD64", "100"); 4837 } 4838 }; 4839 4840 // x86-64 MinGW target 4841 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4842 public: 4843 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4844 : WindowsX86_64TargetInfo(Triple, Opts) { 4845 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4846 // with x86 FP ops. Weird. 4847 LongDoubleWidth = LongDoubleAlign = 128; 4848 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 4849 } 4850 4851 void getTargetDefines(const LangOptions &Opts, 4852 MacroBuilder &Builder) const override { 4853 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4854 DefineStd(Builder, "WIN64", Opts); 4855 Builder.defineMacro("__MINGW64__"); 4856 addMinGWDefines(Opts, Builder); 4857 4858 // GCC defines this macro when it is using __gxx_personality_seh0. 4859 if (!Opts.SjLjExceptions) 4860 Builder.defineMacro("__SEH__"); 4861 } 4862 }; 4863 4864 // x86-64 Cygwin target 4865 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4866 public: 4867 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4868 : X86_64TargetInfo(Triple, Opts) { 4869 TLSSupported = false; 4870 WCharType = UnsignedShort; 4871 } 4872 void getTargetDefines(const LangOptions &Opts, 4873 MacroBuilder &Builder) const override { 4874 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4875 Builder.defineMacro("__x86_64__"); 4876 Builder.defineMacro("__CYGWIN__"); 4877 Builder.defineMacro("__CYGWIN64__"); 4878 addCygMingDefines(Opts, Builder); 4879 DefineStd(Builder, "unix", Opts); 4880 if (Opts.CPlusPlus) 4881 Builder.defineMacro("_GNU_SOURCE"); 4882 4883 // GCC defines this macro when it is using __gxx_personality_seh0. 4884 if (!Opts.SjLjExceptions) 4885 Builder.defineMacro("__SEH__"); 4886 } 4887 }; 4888 4889 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4890 public: 4891 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4892 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4893 Int64Type = SignedLongLong; 4894 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4895 llvm::Triple T = llvm::Triple(Triple); 4896 if (T.isiOS()) 4897 UseSignedCharForObjCBool = false; 4898 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4899 } 4900 4901 bool handleTargetFeatures(std::vector<std::string> &Features, 4902 DiagnosticsEngine &Diags) override { 4903 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4904 Diags)) 4905 return false; 4906 // We now know the features we have: we can decide how to align vectors. 4907 MaxVectorAlign = 4908 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4909 return true; 4910 } 4911 }; 4912 4913 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4914 public: 4915 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4916 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4917 IntMaxType = SignedLongLong; 4918 Int64Type = SignedLongLong; 4919 } 4920 }; 4921 4922 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4923 public: 4924 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4925 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4926 IntMaxType = SignedLongLong; 4927 Int64Type = SignedLongLong; 4928 } 4929 }; 4930 4931 class ARMTargetInfo : public TargetInfo { 4932 // Possible FPU choices. 4933 enum FPUMode { 4934 VFP2FPU = (1 << 0), 4935 VFP3FPU = (1 << 1), 4936 VFP4FPU = (1 << 2), 4937 NeonFPU = (1 << 3), 4938 FPARMV8 = (1 << 4) 4939 }; 4940 4941 // Possible HWDiv features. 4942 enum HWDivMode { 4943 HWDivThumb = (1 << 0), 4944 HWDivARM = (1 << 1) 4945 }; 4946 4947 static bool FPUModeIsVFP(FPUMode Mode) { 4948 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4949 } 4950 4951 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4952 static const char * const GCCRegNames[]; 4953 4954 std::string ABI, CPU; 4955 4956 StringRef CPUProfile; 4957 StringRef CPUAttr; 4958 4959 enum { 4960 FP_Default, 4961 FP_VFP, 4962 FP_Neon 4963 } FPMath; 4964 4965 unsigned ArchISA; 4966 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4967 unsigned ArchProfile; 4968 unsigned ArchVersion; 4969 4970 unsigned FPU : 5; 4971 4972 unsigned IsAAPCS : 1; 4973 unsigned HWDiv : 2; 4974 4975 // Initialized via features. 4976 unsigned SoftFloat : 1; 4977 unsigned SoftFloatABI : 1; 4978 4979 unsigned CRC : 1; 4980 unsigned Crypto : 1; 4981 unsigned DSP : 1; 4982 unsigned Unaligned : 1; 4983 4984 enum { 4985 LDREX_B = (1 << 0), /// byte (8-bit) 4986 LDREX_H = (1 << 1), /// half (16-bit) 4987 LDREX_W = (1 << 2), /// word (32-bit) 4988 LDREX_D = (1 << 3), /// double (64-bit) 4989 }; 4990 4991 uint32_t LDREX; 4992 4993 // ACLE 6.5.1 Hardware floating point 4994 enum { 4995 HW_FP_HP = (1 << 1), /// half (16-bit) 4996 HW_FP_SP = (1 << 2), /// single (32-bit) 4997 HW_FP_DP = (1 << 3), /// double (64-bit) 4998 }; 4999 uint32_t HW_FP; 5000 5001 static const Builtin::Info BuiltinInfo[]; 5002 5003 void setABIAAPCS() { 5004 IsAAPCS = true; 5005 5006 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5007 const llvm::Triple &T = getTriple(); 5008 5009 // size_t is unsigned long on MachO-derived environments, NetBSD, 5010 // OpenBSD and Bitrig. 5011 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 5012 T.getOS() == llvm::Triple::OpenBSD || 5013 T.getOS() == llvm::Triple::Bitrig) 5014 SizeType = UnsignedLong; 5015 else 5016 SizeType = UnsignedInt; 5017 5018 switch (T.getOS()) { 5019 case llvm::Triple::NetBSD: 5020 case llvm::Triple::OpenBSD: 5021 WCharType = SignedInt; 5022 break; 5023 case llvm::Triple::Win32: 5024 WCharType = UnsignedShort; 5025 break; 5026 case llvm::Triple::Linux: 5027 default: 5028 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 5029 WCharType = UnsignedInt; 5030 break; 5031 } 5032 5033 UseBitFieldTypeAlignment = true; 5034 5035 ZeroLengthBitfieldBoundary = 0; 5036 5037 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 5038 // so set preferred for small types to 32. 5039 if (T.isOSBinFormatMachO()) { 5040 resetDataLayout(BigEndian 5041 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5042 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5043 } else if (T.isOSWindows()) { 5044 assert(!BigEndian && "Windows on ARM does not support big endian"); 5045 resetDataLayout("e" 5046 "-m:w" 5047 "-p:32:32" 5048 "-i64:64" 5049 "-v128:64:128" 5050 "-a:0:32" 5051 "-n32" 5052 "-S64"); 5053 } else if (T.isOSNaCl()) { 5054 assert(!BigEndian && "NaCl on ARM does not support big endian"); 5055 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 5056 } else { 5057 resetDataLayout(BigEndian 5058 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5059 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5060 } 5061 5062 // FIXME: Enumerated types are variable width in straight AAPCS. 5063 } 5064 5065 void setABIAPCS(bool IsAAPCS16) { 5066 const llvm::Triple &T = getTriple(); 5067 5068 IsAAPCS = false; 5069 5070 if (IsAAPCS16) 5071 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5072 else 5073 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 5074 5075 // size_t is unsigned int on FreeBSD. 5076 if (T.getOS() == llvm::Triple::FreeBSD) 5077 SizeType = UnsignedInt; 5078 else 5079 SizeType = UnsignedLong; 5080 5081 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 5082 WCharType = SignedInt; 5083 5084 // Do not respect the alignment of bit-field types when laying out 5085 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 5086 UseBitFieldTypeAlignment = false; 5087 5088 /// gcc forces the alignment to 4 bytes, regardless of the type of the 5089 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 5090 /// gcc. 5091 ZeroLengthBitfieldBoundary = 32; 5092 5093 if (T.isOSBinFormatMachO() && IsAAPCS16) { 5094 assert(!BigEndian && "AAPCS16 does not support big-endian"); 5095 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 5096 } else if (T.isOSBinFormatMachO()) 5097 resetDataLayout( 5098 BigEndian 5099 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5100 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5101 else 5102 resetDataLayout( 5103 BigEndian 5104 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5105 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5106 5107 // FIXME: Override "preferred align" for double and long long. 5108 } 5109 5110 void setArchInfo() { 5111 StringRef ArchName = getTriple().getArchName(); 5112 5113 ArchISA = llvm::ARM::parseArchISA(ArchName); 5114 CPU = llvm::ARM::getDefaultCPU(ArchName); 5115 unsigned AK = llvm::ARM::parseArch(ArchName); 5116 if (AK != llvm::ARM::AK_INVALID) 5117 ArchKind = AK; 5118 setArchInfo(ArchKind); 5119 } 5120 5121 void setArchInfo(unsigned Kind) { 5122 StringRef SubArch; 5123 5124 // cache TargetParser info 5125 ArchKind = Kind; 5126 SubArch = llvm::ARM::getSubArch(ArchKind); 5127 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5128 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5129 5130 // cache CPU related strings 5131 CPUAttr = getCPUAttr(); 5132 CPUProfile = getCPUProfile(); 5133 } 5134 5135 void setAtomic() { 5136 // when triple does not specify a sub arch, 5137 // then we are not using inline atomics 5138 bool ShouldUseInlineAtomic = 5139 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5140 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5141 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5142 if (ArchProfile == llvm::ARM::PK_M) { 5143 MaxAtomicPromoteWidth = 32; 5144 if (ShouldUseInlineAtomic) 5145 MaxAtomicInlineWidth = 32; 5146 } 5147 else { 5148 MaxAtomicPromoteWidth = 64; 5149 if (ShouldUseInlineAtomic) 5150 MaxAtomicInlineWidth = 64; 5151 } 5152 } 5153 5154 bool isThumb() const { 5155 return (ArchISA == llvm::ARM::IK_THUMB); 5156 } 5157 5158 bool supportsThumb() const { 5159 return CPUAttr.count('T') || ArchVersion >= 6; 5160 } 5161 5162 bool supportsThumb2() const { 5163 return CPUAttr.equals("6T2") || 5164 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5165 } 5166 5167 StringRef getCPUAttr() const { 5168 // For most sub-arches, the build attribute CPU name is enough. 5169 // For Cortex variants, it's slightly different. 5170 switch(ArchKind) { 5171 default: 5172 return llvm::ARM::getCPUAttr(ArchKind); 5173 case llvm::ARM::AK_ARMV6M: 5174 return "6M"; 5175 case llvm::ARM::AK_ARMV7S: 5176 return "7S"; 5177 case llvm::ARM::AK_ARMV7A: 5178 return "7A"; 5179 case llvm::ARM::AK_ARMV7R: 5180 return "7R"; 5181 case llvm::ARM::AK_ARMV7M: 5182 return "7M"; 5183 case llvm::ARM::AK_ARMV7EM: 5184 return "7EM"; 5185 case llvm::ARM::AK_ARMV7VE: 5186 return "7VE"; 5187 case llvm::ARM::AK_ARMV8A: 5188 return "8A"; 5189 case llvm::ARM::AK_ARMV8_1A: 5190 return "8_1A"; 5191 case llvm::ARM::AK_ARMV8_2A: 5192 return "8_2A"; 5193 case llvm::ARM::AK_ARMV8MBaseline: 5194 return "8M_BASE"; 5195 case llvm::ARM::AK_ARMV8MMainline: 5196 return "8M_MAIN"; 5197 case llvm::ARM::AK_ARMV8R: 5198 return "8R"; 5199 } 5200 } 5201 5202 StringRef getCPUProfile() const { 5203 switch(ArchProfile) { 5204 case llvm::ARM::PK_A: 5205 return "A"; 5206 case llvm::ARM::PK_R: 5207 return "R"; 5208 case llvm::ARM::PK_M: 5209 return "M"; 5210 default: 5211 return ""; 5212 } 5213 } 5214 5215 public: 5216 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5217 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5218 HW_FP(0) { 5219 5220 switch (getTriple().getOS()) { 5221 case llvm::Triple::NetBSD: 5222 case llvm::Triple::OpenBSD: 5223 PtrDiffType = SignedLong; 5224 break; 5225 default: 5226 PtrDiffType = SignedInt; 5227 break; 5228 } 5229 5230 // Cache arch related info. 5231 setArchInfo(); 5232 5233 // {} in inline assembly are neon specifiers, not assembly variant 5234 // specifiers. 5235 NoAsmVariants = true; 5236 5237 // FIXME: This duplicates code from the driver that sets the -target-abi 5238 // option - this code is used if -target-abi isn't passed and should 5239 // be unified in some way. 5240 if (Triple.isOSBinFormatMachO()) { 5241 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5242 // the frontend matches that. 5243 if (Triple.getEnvironment() == llvm::Triple::EABI || 5244 Triple.getOS() == llvm::Triple::UnknownOS || 5245 ArchProfile == llvm::ARM::PK_M) { 5246 setABI("aapcs"); 5247 } else if (Triple.isWatchABI()) { 5248 setABI("aapcs16"); 5249 } else { 5250 setABI("apcs-gnu"); 5251 } 5252 } else if (Triple.isOSWindows()) { 5253 // FIXME: this is invalid for WindowsCE 5254 setABI("aapcs"); 5255 } else { 5256 // Select the default based on the platform. 5257 switch (Triple.getEnvironment()) { 5258 case llvm::Triple::Android: 5259 case llvm::Triple::GNUEABI: 5260 case llvm::Triple::GNUEABIHF: 5261 case llvm::Triple::MuslEABI: 5262 case llvm::Triple::MuslEABIHF: 5263 setABI("aapcs-linux"); 5264 break; 5265 case llvm::Triple::EABIHF: 5266 case llvm::Triple::EABI: 5267 setABI("aapcs"); 5268 break; 5269 case llvm::Triple::GNU: 5270 setABI("apcs-gnu"); 5271 break; 5272 default: 5273 if (Triple.getOS() == llvm::Triple::NetBSD) 5274 setABI("apcs-gnu"); 5275 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5276 setABI("aapcs-linux"); 5277 else 5278 setABI("aapcs"); 5279 break; 5280 } 5281 } 5282 5283 // ARM targets default to using the ARM C++ ABI. 5284 TheCXXABI.set(TargetCXXABI::GenericARM); 5285 5286 // ARM has atomics up to 8 bytes 5287 setAtomic(); 5288 5289 // Do force alignment of members that follow zero length bitfields. If 5290 // the alignment of the zero-length bitfield is greater than the member 5291 // that follows it, `bar', `bar' will be aligned as the type of the 5292 // zero length bitfield. 5293 UseZeroLengthBitfieldAlignment = true; 5294 5295 if (Triple.getOS() == llvm::Triple::Linux || 5296 Triple.getOS() == llvm::Triple::UnknownOS) 5297 this->MCountName = 5298 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5299 } 5300 5301 StringRef getABI() const override { return ABI; } 5302 5303 bool setABI(const std::string &Name) override { 5304 ABI = Name; 5305 5306 // The defaults (above) are for AAPCS, check if we need to change them. 5307 // 5308 // FIXME: We need support for -meabi... we could just mangle it into the 5309 // name. 5310 if (Name == "apcs-gnu" || Name == "aapcs16") { 5311 setABIAPCS(Name == "aapcs16"); 5312 return true; 5313 } 5314 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5315 setABIAAPCS(); 5316 return true; 5317 } 5318 return false; 5319 } 5320 5321 // FIXME: This should be based on Arch attributes, not CPU names. 5322 bool 5323 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5324 StringRef CPU, 5325 const std::vector<std::string> &FeaturesVec) const override { 5326 5327 std::vector<StringRef> TargetFeatures; 5328 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5329 5330 // get default FPU features 5331 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5332 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5333 5334 // get default Extension features 5335 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5336 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5337 5338 for (auto Feature : TargetFeatures) 5339 if (Feature[0] == '+') 5340 Features[Feature.drop_front(1)] = true; 5341 5342 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5343 } 5344 5345 bool handleTargetFeatures(std::vector<std::string> &Features, 5346 DiagnosticsEngine &Diags) override { 5347 FPU = 0; 5348 CRC = 0; 5349 Crypto = 0; 5350 DSP = 0; 5351 Unaligned = 1; 5352 SoftFloat = SoftFloatABI = false; 5353 HWDiv = 0; 5354 5355 // This does not diagnose illegal cases like having both 5356 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5357 uint32_t HW_FP_remove = 0; 5358 for (const auto &Feature : Features) { 5359 if (Feature == "+soft-float") { 5360 SoftFloat = true; 5361 } else if (Feature == "+soft-float-abi") { 5362 SoftFloatABI = true; 5363 } else if (Feature == "+vfp2") { 5364 FPU |= VFP2FPU; 5365 HW_FP |= HW_FP_SP | HW_FP_DP; 5366 } else if (Feature == "+vfp3") { 5367 FPU |= VFP3FPU; 5368 HW_FP |= HW_FP_SP | HW_FP_DP; 5369 } else if (Feature == "+vfp4") { 5370 FPU |= VFP4FPU; 5371 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5372 } else if (Feature == "+fp-armv8") { 5373 FPU |= FPARMV8; 5374 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5375 } else if (Feature == "+neon") { 5376 FPU |= NeonFPU; 5377 HW_FP |= HW_FP_SP | HW_FP_DP; 5378 } else if (Feature == "+hwdiv") { 5379 HWDiv |= HWDivThumb; 5380 } else if (Feature == "+hwdiv-arm") { 5381 HWDiv |= HWDivARM; 5382 } else if (Feature == "+crc") { 5383 CRC = 1; 5384 } else if (Feature == "+crypto") { 5385 Crypto = 1; 5386 } else if (Feature == "+dsp") { 5387 DSP = 1; 5388 } else if (Feature == "+fp-only-sp") { 5389 HW_FP_remove |= HW_FP_DP; 5390 } else if (Feature == "+strict-align") { 5391 Unaligned = 0; 5392 } else if (Feature == "+fp16") { 5393 HW_FP |= HW_FP_HP; 5394 } 5395 } 5396 HW_FP &= ~HW_FP_remove; 5397 5398 switch (ArchVersion) { 5399 case 6: 5400 if (ArchProfile == llvm::ARM::PK_M) 5401 LDREX = 0; 5402 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5403 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5404 else 5405 LDREX = LDREX_W; 5406 break; 5407 case 7: 5408 if (ArchProfile == llvm::ARM::PK_M) 5409 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5410 else 5411 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5412 break; 5413 case 8: 5414 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5415 } 5416 5417 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5418 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5419 return false; 5420 } 5421 5422 if (FPMath == FP_Neon) 5423 Features.push_back("+neonfp"); 5424 else if (FPMath == FP_VFP) 5425 Features.push_back("-neonfp"); 5426 5427 // Remove front-end specific options which the backend handles differently. 5428 auto Feature = 5429 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5430 if (Feature != Features.end()) 5431 Features.erase(Feature); 5432 5433 return true; 5434 } 5435 5436 bool hasFeature(StringRef Feature) const override { 5437 return llvm::StringSwitch<bool>(Feature) 5438 .Case("arm", true) 5439 .Case("aarch32", true) 5440 .Case("softfloat", SoftFloat) 5441 .Case("thumb", isThumb()) 5442 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5443 .Case("hwdiv", HWDiv & HWDivThumb) 5444 .Case("hwdiv-arm", HWDiv & HWDivARM) 5445 .Default(false); 5446 } 5447 5448 bool setCPU(const std::string &Name) override { 5449 if (Name != "generic") 5450 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5451 5452 if (ArchKind == llvm::ARM::AK_INVALID) 5453 return false; 5454 setAtomic(); 5455 CPU = Name; 5456 return true; 5457 } 5458 5459 bool setFPMath(StringRef Name) override; 5460 5461 void getTargetDefines(const LangOptions &Opts, 5462 MacroBuilder &Builder) const override { 5463 // Target identification. 5464 Builder.defineMacro("__arm"); 5465 Builder.defineMacro("__arm__"); 5466 // For bare-metal none-eabi. 5467 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5468 getTriple().getEnvironment() == llvm::Triple::EABI) 5469 Builder.defineMacro("__ELF__"); 5470 5471 // Target properties. 5472 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5473 5474 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5475 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5476 if (getTriple().isWatchABI()) 5477 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5478 5479 if (!CPUAttr.empty()) 5480 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5481 5482 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5483 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5484 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5485 5486 if (ArchVersion >= 8) { 5487 // ACLE 6.5.7 Crypto Extension 5488 if (Crypto) 5489 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5490 // ACLE 6.5.8 CRC32 Extension 5491 if (CRC) 5492 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5493 // ACLE 6.5.10 Numeric Maximum and Minimum 5494 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5495 // ACLE 6.5.9 Directed Rounding 5496 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5497 } 5498 5499 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5500 // is not defined for the M-profile. 5501 // NOTE that the default profile is assumed to be 'A' 5502 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5503 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5504 5505 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5506 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5507 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5508 // v7 and v8 architectures excluding v8-M Baseline. 5509 if (supportsThumb2()) 5510 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5511 else if (supportsThumb()) 5512 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5513 5514 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5515 // instruction set such as ARM or Thumb. 5516 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5517 5518 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5519 5520 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5521 if (!CPUProfile.empty()) 5522 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5523 5524 // ACLE 6.4.3 Unaligned access supported in hardware 5525 if (Unaligned) 5526 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5527 5528 // ACLE 6.4.4 LDREX/STREX 5529 if (LDREX) 5530 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5531 5532 // ACLE 6.4.5 CLZ 5533 if (ArchVersion == 5 || 5534 (ArchVersion == 6 && CPUProfile != "M") || 5535 ArchVersion > 6) 5536 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5537 5538 // ACLE 6.5.1 Hardware Floating Point 5539 if (HW_FP) 5540 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5541 5542 // ACLE predefines. 5543 Builder.defineMacro("__ARM_ACLE", "200"); 5544 5545 // FP16 support (we currently only support IEEE format). 5546 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5547 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5548 5549 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5550 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5551 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5552 5553 // Subtarget options. 5554 5555 // FIXME: It's more complicated than this and we don't really support 5556 // interworking. 5557 // Windows on ARM does not "support" interworking 5558 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5559 Builder.defineMacro("__THUMB_INTERWORK__"); 5560 5561 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5562 // Embedded targets on Darwin follow AAPCS, but not EABI. 5563 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5564 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5565 Builder.defineMacro("__ARM_EABI__"); 5566 Builder.defineMacro("__ARM_PCS", "1"); 5567 } 5568 5569 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5570 ABI == "aapcs16") 5571 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5572 5573 if (SoftFloat) 5574 Builder.defineMacro("__SOFTFP__"); 5575 5576 if (ArchKind == llvm::ARM::AK_XSCALE) 5577 Builder.defineMacro("__XSCALE__"); 5578 5579 if (isThumb()) { 5580 Builder.defineMacro("__THUMBEL__"); 5581 Builder.defineMacro("__thumb__"); 5582 if (supportsThumb2()) 5583 Builder.defineMacro("__thumb2__"); 5584 } 5585 5586 // ACLE 6.4.9 32-bit SIMD instructions 5587 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5588 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5589 5590 // ACLE 6.4.10 Hardware Integer Divide 5591 if (((HWDiv & HWDivThumb) && isThumb()) || 5592 ((HWDiv & HWDivARM) && !isThumb())) { 5593 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5594 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5595 } 5596 5597 // Note, this is always on in gcc, even though it doesn't make sense. 5598 Builder.defineMacro("__APCS_32__"); 5599 5600 if (FPUModeIsVFP((FPUMode) FPU)) { 5601 Builder.defineMacro("__VFP_FP__"); 5602 if (FPU & VFP2FPU) 5603 Builder.defineMacro("__ARM_VFPV2__"); 5604 if (FPU & VFP3FPU) 5605 Builder.defineMacro("__ARM_VFPV3__"); 5606 if (FPU & VFP4FPU) 5607 Builder.defineMacro("__ARM_VFPV4__"); 5608 if (FPU & FPARMV8) 5609 Builder.defineMacro("__ARM_FPV5__"); 5610 } 5611 5612 // This only gets set when Neon instructions are actually available, unlike 5613 // the VFP define, hence the soft float and arch check. This is subtly 5614 // different from gcc, we follow the intent which was that it should be set 5615 // when Neon instructions are actually available. 5616 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5617 Builder.defineMacro("__ARM_NEON", "1"); 5618 Builder.defineMacro("__ARM_NEON__"); 5619 // current AArch32 NEON implementations do not support double-precision 5620 // floating-point even when it is present in VFP. 5621 Builder.defineMacro("__ARM_NEON_FP", 5622 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5623 } 5624 5625 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5626 Opts.ShortWChar ? "2" : "4"); 5627 5628 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5629 Opts.ShortEnums ? "1" : "4"); 5630 5631 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5632 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5633 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5634 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5635 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5636 } 5637 5638 // ACLE 6.4.7 DSP instructions 5639 if (DSP) { 5640 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5641 } 5642 5643 // ACLE 6.4.8 Saturation instructions 5644 bool SAT = false; 5645 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5646 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5647 SAT = true; 5648 } 5649 5650 // ACLE 6.4.6 Q (saturation) flag 5651 if (DSP || SAT) 5652 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5653 5654 if (Opts.UnsafeFPMath) 5655 Builder.defineMacro("__ARM_FP_FAST", "1"); 5656 5657 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5658 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5659 } 5660 5661 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5662 return llvm::makeArrayRef(BuiltinInfo, 5663 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5664 } 5665 bool isCLZForZeroUndef() const override { return false; } 5666 BuiltinVaListKind getBuiltinVaListKind() const override { 5667 return IsAAPCS 5668 ? AAPCSABIBuiltinVaList 5669 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5670 : TargetInfo::VoidPtrBuiltinVaList); 5671 } 5672 ArrayRef<const char *> getGCCRegNames() const override; 5673 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5674 bool validateAsmConstraint(const char *&Name, 5675 TargetInfo::ConstraintInfo &Info) const override { 5676 switch (*Name) { 5677 default: break; 5678 case 'l': // r0-r7 5679 case 'h': // r8-r15 5680 case 't': // VFP Floating point register single precision 5681 case 'w': // VFP Floating point register double precision 5682 Info.setAllowsRegister(); 5683 return true; 5684 case 'I': 5685 case 'J': 5686 case 'K': 5687 case 'L': 5688 case 'M': 5689 // FIXME 5690 return true; 5691 case 'Q': // A memory address that is a single base register. 5692 Info.setAllowsMemory(); 5693 return true; 5694 case 'U': // a memory reference... 5695 switch (Name[1]) { 5696 case 'q': // ...ARMV4 ldrsb 5697 case 'v': // ...VFP load/store (reg+constant offset) 5698 case 'y': // ...iWMMXt load/store 5699 case 't': // address valid for load/store opaque types wider 5700 // than 128-bits 5701 case 'n': // valid address for Neon doubleword vector load/store 5702 case 'm': // valid address for Neon element and structure load/store 5703 case 's': // valid address for non-offset loads/stores of quad-word 5704 // values in four ARM registers 5705 Info.setAllowsMemory(); 5706 Name++; 5707 return true; 5708 } 5709 } 5710 return false; 5711 } 5712 std::string convertConstraint(const char *&Constraint) const override { 5713 std::string R; 5714 switch (*Constraint) { 5715 case 'U': // Two-character constraint; add "^" hint for later parsing. 5716 R = std::string("^") + std::string(Constraint, 2); 5717 Constraint++; 5718 break; 5719 case 'p': // 'p' should be translated to 'r' by default. 5720 R = std::string("r"); 5721 break; 5722 default: 5723 return std::string(1, *Constraint); 5724 } 5725 return R; 5726 } 5727 bool 5728 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5729 std::string &SuggestedModifier) const override { 5730 bool isOutput = (Constraint[0] == '='); 5731 bool isInOut = (Constraint[0] == '+'); 5732 5733 // Strip off constraint modifiers. 5734 while (Constraint[0] == '=' || 5735 Constraint[0] == '+' || 5736 Constraint[0] == '&') 5737 Constraint = Constraint.substr(1); 5738 5739 switch (Constraint[0]) { 5740 default: break; 5741 case 'r': { 5742 switch (Modifier) { 5743 default: 5744 return (isInOut || isOutput || Size <= 64); 5745 case 'q': 5746 // A register of size 32 cannot fit a vector type. 5747 return false; 5748 } 5749 } 5750 } 5751 5752 return true; 5753 } 5754 const char *getClobbers() const override { 5755 // FIXME: Is this really right? 5756 return ""; 5757 } 5758 5759 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5760 switch (CC) { 5761 case CC_AAPCS: 5762 case CC_AAPCS_VFP: 5763 case CC_Swift: 5764 return CCCR_OK; 5765 default: 5766 return CCCR_Warning; 5767 } 5768 } 5769 5770 int getEHDataRegisterNumber(unsigned RegNo) const override { 5771 if (RegNo == 0) return 0; 5772 if (RegNo == 1) return 1; 5773 return -1; 5774 } 5775 5776 bool hasSjLjLowering() const override { 5777 return true; 5778 } 5779 }; 5780 5781 bool ARMTargetInfo::setFPMath(StringRef Name) { 5782 if (Name == "neon") { 5783 FPMath = FP_Neon; 5784 return true; 5785 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5786 Name == "vfp4") { 5787 FPMath = FP_VFP; 5788 return true; 5789 } 5790 return false; 5791 } 5792 5793 const char * const ARMTargetInfo::GCCRegNames[] = { 5794 // Integer registers 5795 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5796 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5797 5798 // Float registers 5799 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5800 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5801 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5802 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5803 5804 // Double registers 5805 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5806 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5807 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5808 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5809 5810 // Quad registers 5811 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5812 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5813 }; 5814 5815 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5816 return llvm::makeArrayRef(GCCRegNames); 5817 } 5818 5819 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5820 { { "a1" }, "r0" }, 5821 { { "a2" }, "r1" }, 5822 { { "a3" }, "r2" }, 5823 { { "a4" }, "r3" }, 5824 { { "v1" }, "r4" }, 5825 { { "v2" }, "r5" }, 5826 { { "v3" }, "r6" }, 5827 { { "v4" }, "r7" }, 5828 { { "v5" }, "r8" }, 5829 { { "v6", "rfp" }, "r9" }, 5830 { { "sl" }, "r10" }, 5831 { { "fp" }, "r11" }, 5832 { { "ip" }, "r12" }, 5833 { { "r13" }, "sp" }, 5834 { { "r14" }, "lr" }, 5835 { { "r15" }, "pc" }, 5836 // The S, D and Q registers overlap, but aren't really aliases; we 5837 // don't want to substitute one of these for a different-sized one. 5838 }; 5839 5840 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5841 return llvm::makeArrayRef(GCCRegAliases); 5842 } 5843 5844 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5845 #define BUILTIN(ID, TYPE, ATTRS) \ 5846 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5847 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5848 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5849 #include "clang/Basic/BuiltinsNEON.def" 5850 5851 #define BUILTIN(ID, TYPE, ATTRS) \ 5852 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5853 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5854 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5855 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5856 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5857 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5858 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5859 #include "clang/Basic/BuiltinsARM.def" 5860 }; 5861 5862 class ARMleTargetInfo : public ARMTargetInfo { 5863 public: 5864 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5865 : ARMTargetInfo(Triple, Opts) {} 5866 void getTargetDefines(const LangOptions &Opts, 5867 MacroBuilder &Builder) const override { 5868 Builder.defineMacro("__ARMEL__"); 5869 ARMTargetInfo::getTargetDefines(Opts, Builder); 5870 } 5871 }; 5872 5873 class ARMbeTargetInfo : public ARMTargetInfo { 5874 public: 5875 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5876 : ARMTargetInfo(Triple, Opts) {} 5877 void getTargetDefines(const LangOptions &Opts, 5878 MacroBuilder &Builder) const override { 5879 Builder.defineMacro("__ARMEB__"); 5880 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5881 ARMTargetInfo::getTargetDefines(Opts, Builder); 5882 } 5883 }; 5884 5885 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5886 const llvm::Triple Triple; 5887 public: 5888 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5889 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5890 WCharType = UnsignedShort; 5891 SizeType = UnsignedInt; 5892 } 5893 void getVisualStudioDefines(const LangOptions &Opts, 5894 MacroBuilder &Builder) const { 5895 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5896 5897 // FIXME: this is invalid for WindowsCE 5898 Builder.defineMacro("_M_ARM_NT", "1"); 5899 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5900 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5901 5902 assert((Triple.getArch() == llvm::Triple::arm || 5903 Triple.getArch() == llvm::Triple::thumb) && 5904 "invalid architecture for Windows ARM target info"); 5905 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5906 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5907 5908 // TODO map the complete set of values 5909 // 31: VFPv3 40: VFPv4 5910 Builder.defineMacro("_M_ARM_FP", "31"); 5911 } 5912 BuiltinVaListKind getBuiltinVaListKind() const override { 5913 return TargetInfo::CharPtrBuiltinVaList; 5914 } 5915 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5916 switch (CC) { 5917 case CC_X86StdCall: 5918 case CC_X86ThisCall: 5919 case CC_X86FastCall: 5920 case CC_X86VectorCall: 5921 return CCCR_Ignore; 5922 case CC_C: 5923 return CCCR_OK; 5924 default: 5925 return CCCR_Warning; 5926 } 5927 } 5928 }; 5929 5930 // Windows ARM + Itanium C++ ABI Target 5931 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5932 public: 5933 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5934 const TargetOptions &Opts) 5935 : WindowsARMTargetInfo(Triple, Opts) { 5936 TheCXXABI.set(TargetCXXABI::GenericARM); 5937 } 5938 5939 void getTargetDefines(const LangOptions &Opts, 5940 MacroBuilder &Builder) const override { 5941 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5942 5943 if (Opts.MSVCCompat) 5944 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5945 } 5946 }; 5947 5948 // Windows ARM, MS (C++) ABI 5949 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5950 public: 5951 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5952 const TargetOptions &Opts) 5953 : WindowsARMTargetInfo(Triple, Opts) { 5954 TheCXXABI.set(TargetCXXABI::Microsoft); 5955 } 5956 5957 void getTargetDefines(const LangOptions &Opts, 5958 MacroBuilder &Builder) const override { 5959 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5960 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5961 } 5962 }; 5963 5964 // ARM MinGW target 5965 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5966 public: 5967 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5968 : WindowsARMTargetInfo(Triple, Opts) { 5969 TheCXXABI.set(TargetCXXABI::GenericARM); 5970 } 5971 5972 void getTargetDefines(const LangOptions &Opts, 5973 MacroBuilder &Builder) const override { 5974 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5975 DefineStd(Builder, "WIN32", Opts); 5976 DefineStd(Builder, "WINNT", Opts); 5977 Builder.defineMacro("_ARM_"); 5978 addMinGWDefines(Opts, Builder); 5979 } 5980 }; 5981 5982 // ARM Cygwin target 5983 class CygwinARMTargetInfo : public ARMleTargetInfo { 5984 public: 5985 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5986 : ARMleTargetInfo(Triple, Opts) { 5987 TLSSupported = false; 5988 WCharType = UnsignedShort; 5989 DoubleAlign = LongLongAlign = 64; 5990 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5991 } 5992 void getTargetDefines(const LangOptions &Opts, 5993 MacroBuilder &Builder) const override { 5994 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5995 Builder.defineMacro("_ARM_"); 5996 Builder.defineMacro("__CYGWIN__"); 5997 Builder.defineMacro("__CYGWIN32__"); 5998 DefineStd(Builder, "unix", Opts); 5999 if (Opts.CPlusPlus) 6000 Builder.defineMacro("_GNU_SOURCE"); 6001 } 6002 }; 6003 6004 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 6005 protected: 6006 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6007 MacroBuilder &Builder) const override { 6008 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6009 } 6010 6011 public: 6012 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6013 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 6014 HasAlignMac68kSupport = true; 6015 // iOS always has 64-bit atomic instructions. 6016 // FIXME: This should be based off of the target features in 6017 // ARMleTargetInfo. 6018 MaxAtomicInlineWidth = 64; 6019 6020 if (Triple.isWatchABI()) { 6021 // Darwin on iOS uses a variant of the ARM C++ ABI. 6022 TheCXXABI.set(TargetCXXABI::WatchOS); 6023 6024 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 6025 // size_t is long, it's a bit weird for it to be int. 6026 PtrDiffType = SignedLong; 6027 6028 // BOOL should be a real boolean on the new ABI 6029 UseSignedCharForObjCBool = false; 6030 } else 6031 TheCXXABI.set(TargetCXXABI::iOS); 6032 } 6033 }; 6034 6035 class AArch64TargetInfo : public TargetInfo { 6036 virtual void setDataLayout() = 0; 6037 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6038 static const char *const GCCRegNames[]; 6039 6040 enum FPUModeEnum { 6041 FPUMode, 6042 NeonMode 6043 }; 6044 6045 unsigned FPU; 6046 unsigned CRC; 6047 unsigned Crypto; 6048 unsigned Unaligned; 6049 unsigned V8_1A; 6050 6051 static const Builtin::Info BuiltinInfo[]; 6052 6053 std::string ABI; 6054 6055 public: 6056 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6057 : TargetInfo(Triple), ABI("aapcs") { 6058 if (getTriple().getOS() == llvm::Triple::NetBSD || 6059 getTriple().getOS() == llvm::Triple::OpenBSD) { 6060 WCharType = SignedInt; 6061 6062 // NetBSD apparently prefers consistency across ARM targets to consistency 6063 // across 64-bit targets. 6064 Int64Type = SignedLongLong; 6065 IntMaxType = SignedLongLong; 6066 } else { 6067 WCharType = UnsignedInt; 6068 Int64Type = SignedLong; 6069 IntMaxType = SignedLong; 6070 } 6071 6072 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6073 MaxVectorAlign = 128; 6074 MaxAtomicInlineWidth = 128; 6075 MaxAtomicPromoteWidth = 128; 6076 6077 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 6078 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6079 6080 // {} in inline assembly are neon specifiers, not assembly variant 6081 // specifiers. 6082 NoAsmVariants = true; 6083 6084 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 6085 // contributes to the alignment of the containing aggregate in the same way 6086 // a plain (non bit-field) member of that type would, without exception for 6087 // zero-sized or anonymous bit-fields." 6088 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 6089 UseZeroLengthBitfieldAlignment = true; 6090 6091 // AArch64 targets default to using the ARM C++ ABI. 6092 TheCXXABI.set(TargetCXXABI::GenericAArch64); 6093 6094 if (Triple.getOS() == llvm::Triple::Linux) 6095 this->MCountName = "\01_mcount"; 6096 else if (Triple.getOS() == llvm::Triple::UnknownOS) 6097 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 6098 } 6099 6100 StringRef getABI() const override { return ABI; } 6101 bool setABI(const std::string &Name) override { 6102 if (Name != "aapcs" && Name != "darwinpcs") 6103 return false; 6104 6105 ABI = Name; 6106 return true; 6107 } 6108 6109 bool setCPU(const std::string &Name) override { 6110 return Name == "generic" || 6111 llvm::AArch64::parseCPUArch(Name) != 6112 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6113 } 6114 6115 void getTargetDefines(const LangOptions &Opts, 6116 MacroBuilder &Builder) const override { 6117 // Target identification. 6118 Builder.defineMacro("__aarch64__"); 6119 6120 // Target properties. 6121 Builder.defineMacro("_LP64"); 6122 Builder.defineMacro("__LP64__"); 6123 6124 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6125 Builder.defineMacro("__ARM_ACLE", "200"); 6126 Builder.defineMacro("__ARM_ARCH", "8"); 6127 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6128 6129 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6130 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6131 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6132 6133 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6134 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6135 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6136 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6137 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6138 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6139 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6140 6141 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6142 6143 // 0xe implies support for half, single and double precision operations. 6144 Builder.defineMacro("__ARM_FP", "0xE"); 6145 6146 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6147 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6148 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6149 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6150 6151 if (Opts.UnsafeFPMath) 6152 Builder.defineMacro("__ARM_FP_FAST", "1"); 6153 6154 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6155 6156 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6157 Opts.ShortEnums ? "1" : "4"); 6158 6159 if (FPU == NeonMode) { 6160 Builder.defineMacro("__ARM_NEON", "1"); 6161 // 64-bit NEON supports half, single and double precision operations. 6162 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6163 } 6164 6165 if (CRC) 6166 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6167 6168 if (Crypto) 6169 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6170 6171 if (Unaligned) 6172 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6173 6174 if (V8_1A) 6175 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6176 6177 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6178 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6179 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6180 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6181 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6182 } 6183 6184 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6185 return llvm::makeArrayRef(BuiltinInfo, 6186 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6187 } 6188 6189 bool hasFeature(StringRef Feature) const override { 6190 return Feature == "aarch64" || 6191 Feature == "arm64" || 6192 Feature == "arm" || 6193 (Feature == "neon" && FPU == NeonMode); 6194 } 6195 6196 bool handleTargetFeatures(std::vector<std::string> &Features, 6197 DiagnosticsEngine &Diags) override { 6198 FPU = FPUMode; 6199 CRC = 0; 6200 Crypto = 0; 6201 Unaligned = 1; 6202 V8_1A = 0; 6203 6204 for (const auto &Feature : Features) { 6205 if (Feature == "+neon") 6206 FPU = NeonMode; 6207 if (Feature == "+crc") 6208 CRC = 1; 6209 if (Feature == "+crypto") 6210 Crypto = 1; 6211 if (Feature == "+strict-align") 6212 Unaligned = 0; 6213 if (Feature == "+v8.1a") 6214 V8_1A = 1; 6215 } 6216 6217 setDataLayout(); 6218 6219 return true; 6220 } 6221 6222 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6223 switch (CC) { 6224 case CC_C: 6225 case CC_Swift: 6226 case CC_PreserveMost: 6227 case CC_PreserveAll: 6228 return CCCR_OK; 6229 default: 6230 return CCCR_Warning; 6231 } 6232 } 6233 6234 bool isCLZForZeroUndef() const override { return false; } 6235 6236 BuiltinVaListKind getBuiltinVaListKind() const override { 6237 return TargetInfo::AArch64ABIBuiltinVaList; 6238 } 6239 6240 ArrayRef<const char *> getGCCRegNames() const override; 6241 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6242 6243 bool validateAsmConstraint(const char *&Name, 6244 TargetInfo::ConstraintInfo &Info) const override { 6245 switch (*Name) { 6246 default: 6247 return false; 6248 case 'w': // Floating point and SIMD registers (V0-V31) 6249 Info.setAllowsRegister(); 6250 return true; 6251 case 'I': // Constant that can be used with an ADD instruction 6252 case 'J': // Constant that can be used with a SUB instruction 6253 case 'K': // Constant that can be used with a 32-bit logical instruction 6254 case 'L': // Constant that can be used with a 64-bit logical instruction 6255 case 'M': // Constant that can be used as a 32-bit MOV immediate 6256 case 'N': // Constant that can be used as a 64-bit MOV immediate 6257 case 'Y': // Floating point constant zero 6258 case 'Z': // Integer constant zero 6259 return true; 6260 case 'Q': // A memory reference with base register and no offset 6261 Info.setAllowsMemory(); 6262 return true; 6263 case 'S': // A symbolic address 6264 Info.setAllowsRegister(); 6265 return true; 6266 case 'U': 6267 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6268 // Utf: A memory address suitable for ldp/stp in TF mode. 6269 // Usa: An absolute symbolic address. 6270 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6271 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6272 case 'z': // Zero register, wzr or xzr 6273 Info.setAllowsRegister(); 6274 return true; 6275 case 'x': // Floating point and SIMD registers (V0-V15) 6276 Info.setAllowsRegister(); 6277 return true; 6278 } 6279 return false; 6280 } 6281 6282 bool 6283 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6284 std::string &SuggestedModifier) const override { 6285 // Strip off constraint modifiers. 6286 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6287 Constraint = Constraint.substr(1); 6288 6289 switch (Constraint[0]) { 6290 default: 6291 return true; 6292 case 'z': 6293 case 'r': { 6294 switch (Modifier) { 6295 case 'x': 6296 case 'w': 6297 // For now assume that the person knows what they're 6298 // doing with the modifier. 6299 return true; 6300 default: 6301 // By default an 'r' constraint will be in the 'x' 6302 // registers. 6303 if (Size == 64) 6304 return true; 6305 6306 SuggestedModifier = "w"; 6307 return false; 6308 } 6309 } 6310 } 6311 } 6312 6313 const char *getClobbers() const override { return ""; } 6314 6315 int getEHDataRegisterNumber(unsigned RegNo) const override { 6316 if (RegNo == 0) 6317 return 0; 6318 if (RegNo == 1) 6319 return 1; 6320 return -1; 6321 } 6322 }; 6323 6324 const char *const AArch64TargetInfo::GCCRegNames[] = { 6325 // 32-bit Integer registers 6326 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6327 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6328 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6329 6330 // 64-bit Integer registers 6331 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6332 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6333 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6334 6335 // 32-bit floating point regsisters 6336 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6337 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6338 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6339 6340 // 64-bit floating point regsisters 6341 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6342 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6343 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6344 6345 // Vector registers 6346 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6347 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6348 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6349 }; 6350 6351 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6352 return llvm::makeArrayRef(GCCRegNames); 6353 } 6354 6355 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6356 { { "w31" }, "wsp" }, 6357 { { "x29" }, "fp" }, 6358 { { "x30" }, "lr" }, 6359 { { "x31" }, "sp" }, 6360 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6361 // don't want to substitute one of these for a different-sized one. 6362 }; 6363 6364 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6365 return llvm::makeArrayRef(GCCRegAliases); 6366 } 6367 6368 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6369 #define BUILTIN(ID, TYPE, ATTRS) \ 6370 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6371 #include "clang/Basic/BuiltinsNEON.def" 6372 6373 #define BUILTIN(ID, TYPE, ATTRS) \ 6374 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6375 #include "clang/Basic/BuiltinsAArch64.def" 6376 }; 6377 6378 class AArch64leTargetInfo : public AArch64TargetInfo { 6379 void setDataLayout() override { 6380 if (getTriple().isOSBinFormatMachO()) 6381 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6382 else 6383 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6384 } 6385 6386 public: 6387 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6388 : AArch64TargetInfo(Triple, Opts) { 6389 } 6390 void getTargetDefines(const LangOptions &Opts, 6391 MacroBuilder &Builder) const override { 6392 Builder.defineMacro("__AARCH64EL__"); 6393 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6394 } 6395 }; 6396 6397 class AArch64beTargetInfo : public AArch64TargetInfo { 6398 void setDataLayout() override { 6399 assert(!getTriple().isOSBinFormatMachO()); 6400 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6401 } 6402 6403 public: 6404 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6405 : AArch64TargetInfo(Triple, Opts) {} 6406 void getTargetDefines(const LangOptions &Opts, 6407 MacroBuilder &Builder) const override { 6408 Builder.defineMacro("__AARCH64EB__"); 6409 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6410 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6411 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6412 } 6413 }; 6414 6415 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6416 protected: 6417 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6418 MacroBuilder &Builder) const override { 6419 Builder.defineMacro("__AARCH64_SIMD__"); 6420 Builder.defineMacro("__ARM64_ARCH_8__"); 6421 Builder.defineMacro("__ARM_NEON__"); 6422 Builder.defineMacro("__LITTLE_ENDIAN__"); 6423 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6424 Builder.defineMacro("__arm64", "1"); 6425 Builder.defineMacro("__arm64__", "1"); 6426 6427 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6428 } 6429 6430 public: 6431 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6432 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6433 Int64Type = SignedLongLong; 6434 WCharType = SignedInt; 6435 UseSignedCharForObjCBool = false; 6436 6437 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6438 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6439 6440 TheCXXABI.set(TargetCXXABI::iOS64); 6441 } 6442 6443 BuiltinVaListKind getBuiltinVaListKind() const override { 6444 return TargetInfo::CharPtrBuiltinVaList; 6445 } 6446 }; 6447 6448 // Hexagon abstract base class 6449 class HexagonTargetInfo : public TargetInfo { 6450 static const Builtin::Info BuiltinInfo[]; 6451 static const char * const GCCRegNames[]; 6452 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6453 std::string CPU; 6454 bool HasHVX, HasHVXDouble; 6455 bool UseLongCalls; 6456 6457 public: 6458 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6459 : TargetInfo(Triple) { 6460 // Specify the vector alignment explicitly. For v512x1, the calculated 6461 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6462 // the required minimum of 64 bytes. 6463 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6464 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6465 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6466 SizeType = UnsignedInt; 6467 PtrDiffType = SignedInt; 6468 IntPtrType = SignedInt; 6469 6470 // {} in inline assembly are packet specifiers, not assembly variant 6471 // specifiers. 6472 NoAsmVariants = true; 6473 6474 LargeArrayMinWidth = 64; 6475 LargeArrayAlign = 64; 6476 UseBitFieldTypeAlignment = true; 6477 ZeroLengthBitfieldBoundary = 32; 6478 HasHVX = HasHVXDouble = false; 6479 UseLongCalls = false; 6480 } 6481 6482 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6483 return llvm::makeArrayRef(BuiltinInfo, 6484 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6485 } 6486 6487 bool validateAsmConstraint(const char *&Name, 6488 TargetInfo::ConstraintInfo &Info) const override { 6489 switch (*Name) { 6490 case 'v': 6491 case 'q': 6492 if (HasHVX) { 6493 Info.setAllowsRegister(); 6494 return true; 6495 } 6496 break; 6497 case 's': 6498 // Relocatable constant. 6499 return true; 6500 } 6501 return false; 6502 } 6503 6504 void getTargetDefines(const LangOptions &Opts, 6505 MacroBuilder &Builder) const override; 6506 6507 bool isCLZForZeroUndef() const override { return false; } 6508 6509 bool hasFeature(StringRef Feature) const override { 6510 return llvm::StringSwitch<bool>(Feature) 6511 .Case("hexagon", true) 6512 .Case("hvx", HasHVX) 6513 .Case("hvx-double", HasHVXDouble) 6514 .Case("long-calls", UseLongCalls) 6515 .Default(false); 6516 } 6517 6518 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6519 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6520 const override; 6521 6522 bool handleTargetFeatures(std::vector<std::string> &Features, 6523 DiagnosticsEngine &Diags) override; 6524 6525 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6526 bool Enabled) const override; 6527 6528 BuiltinVaListKind getBuiltinVaListKind() const override { 6529 return TargetInfo::CharPtrBuiltinVaList; 6530 } 6531 ArrayRef<const char *> getGCCRegNames() const override; 6532 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6533 const char *getClobbers() const override { 6534 return ""; 6535 } 6536 6537 static const char *getHexagonCPUSuffix(StringRef Name) { 6538 return llvm::StringSwitch<const char*>(Name) 6539 .Case("hexagonv4", "4") 6540 .Case("hexagonv5", "5") 6541 .Case("hexagonv55", "55") 6542 .Case("hexagonv60", "60") 6543 .Case("hexagonv62", "62") 6544 .Default(nullptr); 6545 } 6546 6547 bool setCPU(const std::string &Name) override { 6548 if (!getHexagonCPUSuffix(Name)) 6549 return false; 6550 CPU = Name; 6551 return true; 6552 } 6553 6554 int getEHDataRegisterNumber(unsigned RegNo) const override { 6555 return RegNo < 2 ? RegNo : -1; 6556 } 6557 }; 6558 6559 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6560 MacroBuilder &Builder) const { 6561 Builder.defineMacro("__qdsp6__", "1"); 6562 Builder.defineMacro("__hexagon__", "1"); 6563 6564 if (CPU == "hexagonv4") { 6565 Builder.defineMacro("__HEXAGON_V4__"); 6566 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6567 if (Opts.HexagonQdsp6Compat) { 6568 Builder.defineMacro("__QDSP6_V4__"); 6569 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6570 } 6571 } else if (CPU == "hexagonv5") { 6572 Builder.defineMacro("__HEXAGON_V5__"); 6573 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6574 if(Opts.HexagonQdsp6Compat) { 6575 Builder.defineMacro("__QDSP6_V5__"); 6576 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6577 } 6578 } else if (CPU == "hexagonv55") { 6579 Builder.defineMacro("__HEXAGON_V55__"); 6580 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6581 Builder.defineMacro("__QDSP6_V55__"); 6582 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6583 } else if (CPU == "hexagonv60") { 6584 Builder.defineMacro("__HEXAGON_V60__"); 6585 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6586 Builder.defineMacro("__QDSP6_V60__"); 6587 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6588 } else if (CPU == "hexagonv62") { 6589 Builder.defineMacro("__HEXAGON_V62__"); 6590 Builder.defineMacro("__HEXAGON_ARCH__", "62"); 6591 } 6592 6593 if (hasFeature("hvx")) { 6594 Builder.defineMacro("__HVX__"); 6595 if (hasFeature("hvx-double")) 6596 Builder.defineMacro("__HVXDBL__"); 6597 } 6598 } 6599 6600 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6601 DiagnosticsEngine &Diags, StringRef CPU, 6602 const std::vector<std::string> &FeaturesVec) const { 6603 // Default for v60: -hvx, -hvx-double. 6604 Features["hvx"] = false; 6605 Features["hvx-double"] = false; 6606 Features["long-calls"] = false; 6607 6608 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6609 } 6610 6611 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6612 DiagnosticsEngine &Diags) { 6613 for (auto &F : Features) { 6614 if (F == "+hvx") 6615 HasHVX = true; 6616 else if (F == "-hvx") 6617 HasHVX = HasHVXDouble = false; 6618 else if (F == "+hvx-double") 6619 HasHVX = HasHVXDouble = true; 6620 else if (F == "-hvx-double") 6621 HasHVXDouble = false; 6622 6623 if (F == "+long-calls") 6624 UseLongCalls = true; 6625 else if (F == "-long-calls") 6626 UseLongCalls = false; 6627 } 6628 return true; 6629 } 6630 6631 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6632 StringRef Name, bool Enabled) const { 6633 if (Enabled) { 6634 if (Name == "hvx-double") 6635 Features["hvx"] = true; 6636 } else { 6637 if (Name == "hvx") 6638 Features["hvx-double"] = false; 6639 } 6640 Features[Name] = Enabled; 6641 } 6642 6643 const char *const HexagonTargetInfo::GCCRegNames[] = { 6644 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6645 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6646 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6647 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6648 "p0", "p1", "p2", "p3", 6649 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6650 }; 6651 6652 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6653 return llvm::makeArrayRef(GCCRegNames); 6654 } 6655 6656 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6657 { { "sp" }, "r29" }, 6658 { { "fp" }, "r30" }, 6659 { { "lr" }, "r31" }, 6660 }; 6661 6662 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6663 return llvm::makeArrayRef(GCCRegAliases); 6664 } 6665 6666 6667 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6668 #define BUILTIN(ID, TYPE, ATTRS) \ 6669 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6670 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6671 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6672 #include "clang/Basic/BuiltinsHexagon.def" 6673 }; 6674 6675 class LanaiTargetInfo : public TargetInfo { 6676 // Class for Lanai (32-bit). 6677 // The CPU profiles supported by the Lanai backend 6678 enum CPUKind { 6679 CK_NONE, 6680 CK_V11, 6681 } CPU; 6682 6683 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6684 static const char *const GCCRegNames[]; 6685 6686 public: 6687 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6688 : TargetInfo(Triple) { 6689 // Description string has to be kept in sync with backend. 6690 resetDataLayout("E" // Big endian 6691 "-m:e" // ELF name manging 6692 "-p:32:32" // 32 bit pointers, 32 bit aligned 6693 "-i64:64" // 64 bit integers, 64 bit aligned 6694 "-a:0:32" // 32 bit alignment of objects of aggregate type 6695 "-n32" // 32 bit native integer width 6696 "-S64" // 64 bit natural stack alignment 6697 ); 6698 6699 // Setting RegParmMax equal to what mregparm was set to in the old 6700 // toolchain 6701 RegParmMax = 4; 6702 6703 // Set the default CPU to V11 6704 CPU = CK_V11; 6705 6706 // Temporary approach to make everything at least word-aligned and allow for 6707 // safely casting between pointers with different alignment requirements. 6708 // TODO: Remove this when there are no more cast align warnings on the 6709 // firmware. 6710 MinGlobalAlign = 32; 6711 } 6712 6713 void getTargetDefines(const LangOptions &Opts, 6714 MacroBuilder &Builder) const override { 6715 // Define __lanai__ when building for target lanai. 6716 Builder.defineMacro("__lanai__"); 6717 6718 // Set define for the CPU specified. 6719 switch (CPU) { 6720 case CK_V11: 6721 Builder.defineMacro("__LANAI_V11__"); 6722 break; 6723 case CK_NONE: 6724 llvm_unreachable("Unhandled target CPU"); 6725 } 6726 } 6727 6728 bool setCPU(const std::string &Name) override { 6729 CPU = llvm::StringSwitch<CPUKind>(Name) 6730 .Case("v11", CK_V11) 6731 .Default(CK_NONE); 6732 6733 return CPU != CK_NONE; 6734 } 6735 6736 bool hasFeature(StringRef Feature) const override { 6737 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6738 } 6739 6740 ArrayRef<const char *> getGCCRegNames() const override; 6741 6742 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6743 6744 BuiltinVaListKind getBuiltinVaListKind() const override { 6745 return TargetInfo::VoidPtrBuiltinVaList; 6746 } 6747 6748 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6749 6750 bool validateAsmConstraint(const char *&Name, 6751 TargetInfo::ConstraintInfo &info) const override { 6752 return false; 6753 } 6754 6755 const char *getClobbers() const override { return ""; } 6756 }; 6757 6758 const char *const LanaiTargetInfo::GCCRegNames[] = { 6759 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6760 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6761 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6762 6763 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6764 return llvm::makeArrayRef(GCCRegNames); 6765 } 6766 6767 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6768 {{"pc"}, "r2"}, 6769 {{"sp"}, "r4"}, 6770 {{"fp"}, "r5"}, 6771 {{"rv"}, "r8"}, 6772 {{"rr1"}, "r10"}, 6773 {{"rr2"}, "r11"}, 6774 {{"rca"}, "r15"}, 6775 }; 6776 6777 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6778 return llvm::makeArrayRef(GCCRegAliases); 6779 } 6780 6781 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6782 class SparcTargetInfo : public TargetInfo { 6783 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6784 static const char * const GCCRegNames[]; 6785 bool SoftFloat; 6786 public: 6787 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6788 : TargetInfo(Triple), SoftFloat(false) {} 6789 6790 int getEHDataRegisterNumber(unsigned RegNo) const override { 6791 if (RegNo == 0) return 24; 6792 if (RegNo == 1) return 25; 6793 return -1; 6794 } 6795 6796 bool handleTargetFeatures(std::vector<std::string> &Features, 6797 DiagnosticsEngine &Diags) override { 6798 // Check if software floating point is enabled 6799 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6800 if (Feature != Features.end()) { 6801 SoftFloat = true; 6802 } 6803 return true; 6804 } 6805 void getTargetDefines(const LangOptions &Opts, 6806 MacroBuilder &Builder) const override { 6807 DefineStd(Builder, "sparc", Opts); 6808 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6809 6810 if (SoftFloat) 6811 Builder.defineMacro("SOFT_FLOAT", "1"); 6812 } 6813 6814 bool hasFeature(StringRef Feature) const override { 6815 return llvm::StringSwitch<bool>(Feature) 6816 .Case("softfloat", SoftFloat) 6817 .Case("sparc", true) 6818 .Default(false); 6819 } 6820 6821 bool hasSjLjLowering() const override { 6822 return true; 6823 } 6824 6825 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6826 // FIXME: Implement! 6827 return None; 6828 } 6829 BuiltinVaListKind getBuiltinVaListKind() const override { 6830 return TargetInfo::VoidPtrBuiltinVaList; 6831 } 6832 ArrayRef<const char *> getGCCRegNames() const override; 6833 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6834 bool validateAsmConstraint(const char *&Name, 6835 TargetInfo::ConstraintInfo &info) const override { 6836 // FIXME: Implement! 6837 switch (*Name) { 6838 case 'I': // Signed 13-bit constant 6839 case 'J': // Zero 6840 case 'K': // 32-bit constant with the low 12 bits clear 6841 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6842 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6843 case 'N': // Same as 'K' but zext (required for SIMode) 6844 case 'O': // The constant 4096 6845 return true; 6846 } 6847 return false; 6848 } 6849 const char *getClobbers() const override { 6850 // FIXME: Implement! 6851 return ""; 6852 } 6853 6854 // No Sparc V7 for now, the backend doesn't support it anyway. 6855 enum CPUKind { 6856 CK_GENERIC, 6857 CK_V8, 6858 CK_SUPERSPARC, 6859 CK_SPARCLITE, 6860 CK_F934, 6861 CK_HYPERSPARC, 6862 CK_SPARCLITE86X, 6863 CK_SPARCLET, 6864 CK_TSC701, 6865 CK_V9, 6866 CK_ULTRASPARC, 6867 CK_ULTRASPARC3, 6868 CK_NIAGARA, 6869 CK_NIAGARA2, 6870 CK_NIAGARA3, 6871 CK_NIAGARA4, 6872 CK_MYRIAD2100, 6873 CK_MYRIAD2150, 6874 CK_MYRIAD2450, 6875 CK_LEON2, 6876 CK_LEON2_AT697E, 6877 CK_LEON2_AT697F, 6878 CK_LEON3, 6879 CK_LEON3_UT699, 6880 CK_LEON3_GR712RC, 6881 CK_LEON4, 6882 CK_LEON4_GR740 6883 } CPU = CK_GENERIC; 6884 6885 enum CPUGeneration { 6886 CG_V8, 6887 CG_V9, 6888 }; 6889 6890 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6891 switch (Kind) { 6892 case CK_GENERIC: 6893 case CK_V8: 6894 case CK_SUPERSPARC: 6895 case CK_SPARCLITE: 6896 case CK_F934: 6897 case CK_HYPERSPARC: 6898 case CK_SPARCLITE86X: 6899 case CK_SPARCLET: 6900 case CK_TSC701: 6901 case CK_MYRIAD2100: 6902 case CK_MYRIAD2150: 6903 case CK_MYRIAD2450: 6904 case CK_LEON2: 6905 case CK_LEON2_AT697E: 6906 case CK_LEON2_AT697F: 6907 case CK_LEON3: 6908 case CK_LEON3_UT699: 6909 case CK_LEON3_GR712RC: 6910 case CK_LEON4: 6911 case CK_LEON4_GR740: 6912 return CG_V8; 6913 case CK_V9: 6914 case CK_ULTRASPARC: 6915 case CK_ULTRASPARC3: 6916 case CK_NIAGARA: 6917 case CK_NIAGARA2: 6918 case CK_NIAGARA3: 6919 case CK_NIAGARA4: 6920 return CG_V9; 6921 } 6922 llvm_unreachable("Unexpected CPU kind"); 6923 } 6924 6925 CPUKind getCPUKind(StringRef Name) const { 6926 return llvm::StringSwitch<CPUKind>(Name) 6927 .Case("v8", CK_V8) 6928 .Case("supersparc", CK_SUPERSPARC) 6929 .Case("sparclite", CK_SPARCLITE) 6930 .Case("f934", CK_F934) 6931 .Case("hypersparc", CK_HYPERSPARC) 6932 .Case("sparclite86x", CK_SPARCLITE86X) 6933 .Case("sparclet", CK_SPARCLET) 6934 .Case("tsc701", CK_TSC701) 6935 .Case("v9", CK_V9) 6936 .Case("ultrasparc", CK_ULTRASPARC) 6937 .Case("ultrasparc3", CK_ULTRASPARC3) 6938 .Case("niagara", CK_NIAGARA) 6939 .Case("niagara2", CK_NIAGARA2) 6940 .Case("niagara3", CK_NIAGARA3) 6941 .Case("niagara4", CK_NIAGARA4) 6942 .Case("ma2100", CK_MYRIAD2100) 6943 .Case("ma2150", CK_MYRIAD2150) 6944 .Case("ma2450", CK_MYRIAD2450) 6945 // FIXME: the myriad2[.n] spellings are obsolete, 6946 // but a grace period is needed to allow updating dependent builds. 6947 .Case("myriad2", CK_MYRIAD2100) 6948 .Case("myriad2.1", CK_MYRIAD2100) 6949 .Case("myriad2.2", CK_MYRIAD2150) 6950 .Case("leon2", CK_LEON2) 6951 .Case("at697e", CK_LEON2_AT697E) 6952 .Case("at697f", CK_LEON2_AT697F) 6953 .Case("leon3", CK_LEON3) 6954 .Case("ut699", CK_LEON3_UT699) 6955 .Case("gr712rc", CK_LEON3_GR712RC) 6956 .Case("leon4", CK_LEON4) 6957 .Case("gr740", CK_LEON4_GR740) 6958 .Default(CK_GENERIC); 6959 } 6960 6961 bool setCPU(const std::string &Name) override { 6962 CPU = getCPUKind(Name); 6963 return CPU != CK_GENERIC; 6964 } 6965 }; 6966 6967 const char * const SparcTargetInfo::GCCRegNames[] = { 6968 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6969 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6970 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6971 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6972 }; 6973 6974 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6975 return llvm::makeArrayRef(GCCRegNames); 6976 } 6977 6978 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6979 { { "g0" }, "r0" }, 6980 { { "g1" }, "r1" }, 6981 { { "g2" }, "r2" }, 6982 { { "g3" }, "r3" }, 6983 { { "g4" }, "r4" }, 6984 { { "g5" }, "r5" }, 6985 { { "g6" }, "r6" }, 6986 { { "g7" }, "r7" }, 6987 { { "o0" }, "r8" }, 6988 { { "o1" }, "r9" }, 6989 { { "o2" }, "r10" }, 6990 { { "o3" }, "r11" }, 6991 { { "o4" }, "r12" }, 6992 { { "o5" }, "r13" }, 6993 { { "o6", "sp" }, "r14" }, 6994 { { "o7" }, "r15" }, 6995 { { "l0" }, "r16" }, 6996 { { "l1" }, "r17" }, 6997 { { "l2" }, "r18" }, 6998 { { "l3" }, "r19" }, 6999 { { "l4" }, "r20" }, 7000 { { "l5" }, "r21" }, 7001 { { "l6" }, "r22" }, 7002 { { "l7" }, "r23" }, 7003 { { "i0" }, "r24" }, 7004 { { "i1" }, "r25" }, 7005 { { "i2" }, "r26" }, 7006 { { "i3" }, "r27" }, 7007 { { "i4" }, "r28" }, 7008 { { "i5" }, "r29" }, 7009 { { "i6", "fp" }, "r30" }, 7010 { { "i7" }, "r31" }, 7011 }; 7012 7013 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 7014 return llvm::makeArrayRef(GCCRegAliases); 7015 } 7016 7017 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 7018 class SparcV8TargetInfo : public SparcTargetInfo { 7019 public: 7020 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7021 : SparcTargetInfo(Triple, Opts) { 7022 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7023 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 7024 switch (getTriple().getOS()) { 7025 default: 7026 SizeType = UnsignedInt; 7027 IntPtrType = SignedInt; 7028 PtrDiffType = SignedInt; 7029 break; 7030 case llvm::Triple::NetBSD: 7031 case llvm::Triple::OpenBSD: 7032 SizeType = UnsignedLong; 7033 IntPtrType = SignedLong; 7034 PtrDiffType = SignedLong; 7035 break; 7036 } 7037 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 7038 // on up to 64 bits. 7039 MaxAtomicPromoteWidth = 64; 7040 MaxAtomicInlineWidth = 32; 7041 } 7042 7043 void getTargetDefines(const LangOptions &Opts, 7044 MacroBuilder &Builder) const override { 7045 SparcTargetInfo::getTargetDefines(Opts, Builder); 7046 switch (getCPUGeneration(CPU)) { 7047 case CG_V8: 7048 Builder.defineMacro("__sparcv8"); 7049 if (getTriple().getOS() != llvm::Triple::Solaris) 7050 Builder.defineMacro("__sparcv8__"); 7051 break; 7052 case CG_V9: 7053 Builder.defineMacro("__sparcv9"); 7054 if (getTriple().getOS() != llvm::Triple::Solaris) { 7055 Builder.defineMacro("__sparcv9__"); 7056 Builder.defineMacro("__sparc_v9__"); 7057 } 7058 break; 7059 } 7060 if (getTriple().getVendor() == llvm::Triple::Myriad) { 7061 std::string MyriadArchValue, Myriad2Value; 7062 Builder.defineMacro("__sparc_v8__"); 7063 Builder.defineMacro("__leon__"); 7064 switch (CPU) { 7065 case CK_MYRIAD2150: 7066 MyriadArchValue = "__ma2150"; 7067 Myriad2Value = "2"; 7068 break; 7069 case CK_MYRIAD2450: 7070 MyriadArchValue = "__ma2450"; 7071 Myriad2Value = "2"; 7072 break; 7073 default: 7074 MyriadArchValue = "__ma2100"; 7075 Myriad2Value = "1"; 7076 break; 7077 } 7078 Builder.defineMacro(MyriadArchValue, "1"); 7079 Builder.defineMacro(MyriadArchValue+"__", "1"); 7080 Builder.defineMacro("__myriad2__", Myriad2Value); 7081 Builder.defineMacro("__myriad2", Myriad2Value); 7082 } 7083 } 7084 7085 bool hasSjLjLowering() const override { 7086 return true; 7087 } 7088 }; 7089 7090 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 7091 class SparcV8elTargetInfo : public SparcV8TargetInfo { 7092 public: 7093 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7094 : SparcV8TargetInfo(Triple, Opts) { 7095 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7096 } 7097 }; 7098 7099 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 7100 class SparcV9TargetInfo : public SparcTargetInfo { 7101 public: 7102 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7103 : SparcTargetInfo(Triple, Opts) { 7104 // FIXME: Support Sparc quad-precision long double? 7105 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 7106 // This is an LP64 platform. 7107 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7108 7109 // OpenBSD uses long long for int64_t and intmax_t. 7110 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7111 IntMaxType = SignedLongLong; 7112 else 7113 IntMaxType = SignedLong; 7114 Int64Type = IntMaxType; 7115 7116 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7117 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7118 LongDoubleWidth = 128; 7119 LongDoubleAlign = 128; 7120 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7121 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7122 } 7123 7124 void getTargetDefines(const LangOptions &Opts, 7125 MacroBuilder &Builder) const override { 7126 SparcTargetInfo::getTargetDefines(Opts, Builder); 7127 Builder.defineMacro("__sparcv9"); 7128 Builder.defineMacro("__arch64__"); 7129 // Solaris doesn't need these variants, but the BSDs do. 7130 if (getTriple().getOS() != llvm::Triple::Solaris) { 7131 Builder.defineMacro("__sparc64__"); 7132 Builder.defineMacro("__sparc_v9__"); 7133 Builder.defineMacro("__sparcv9__"); 7134 } 7135 } 7136 7137 bool setCPU(const std::string &Name) override { 7138 if (!SparcTargetInfo::setCPU(Name)) 7139 return false; 7140 return getCPUGeneration(CPU) == CG_V9; 7141 } 7142 }; 7143 7144 class SystemZTargetInfo : public TargetInfo { 7145 static const Builtin::Info BuiltinInfo[]; 7146 static const char *const GCCRegNames[]; 7147 std::string CPU; 7148 bool HasTransactionalExecution; 7149 bool HasVector; 7150 7151 public: 7152 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7153 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 7154 HasVector(false) { 7155 IntMaxType = SignedLong; 7156 Int64Type = SignedLong; 7157 TLSSupported = true; 7158 IntWidth = IntAlign = 32; 7159 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7160 PointerWidth = PointerAlign = 64; 7161 LongDoubleWidth = 128; 7162 LongDoubleAlign = 64; 7163 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7164 DefaultAlignForAttributeAligned = 64; 7165 MinGlobalAlign = 16; 7166 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7167 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7168 } 7169 void getTargetDefines(const LangOptions &Opts, 7170 MacroBuilder &Builder) const override { 7171 Builder.defineMacro("__s390__"); 7172 Builder.defineMacro("__s390x__"); 7173 Builder.defineMacro("__zarch__"); 7174 Builder.defineMacro("__LONG_DOUBLE_128__"); 7175 7176 const std::string ISARev = llvm::StringSwitch<std::string>(CPU) 7177 .Cases("arch8", "z10", "8") 7178 .Cases("arch9", "z196", "9") 7179 .Cases("arch10", "zEC12", "10") 7180 .Cases("arch11", "z13", "11") 7181 .Default(""); 7182 if (!ISARev.empty()) 7183 Builder.defineMacro("__ARCH__", ISARev); 7184 7185 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7186 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7187 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7188 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7189 7190 if (HasTransactionalExecution) 7191 Builder.defineMacro("__HTM__"); 7192 if (HasVector) 7193 Builder.defineMacro("__VX__"); 7194 if (Opts.ZVector) 7195 Builder.defineMacro("__VEC__", "10301"); 7196 } 7197 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7198 return llvm::makeArrayRef(BuiltinInfo, 7199 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7200 } 7201 7202 ArrayRef<const char *> getGCCRegNames() const override; 7203 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7204 // No aliases. 7205 return None; 7206 } 7207 bool validateAsmConstraint(const char *&Name, 7208 TargetInfo::ConstraintInfo &info) const override; 7209 const char *getClobbers() const override { 7210 // FIXME: Is this really right? 7211 return ""; 7212 } 7213 BuiltinVaListKind getBuiltinVaListKind() const override { 7214 return TargetInfo::SystemZBuiltinVaList; 7215 } 7216 bool setCPU(const std::string &Name) override { 7217 CPU = Name; 7218 bool CPUKnown = llvm::StringSwitch<bool>(Name) 7219 .Case("z10", true) 7220 .Case("arch8", true) 7221 .Case("z196", true) 7222 .Case("arch9", true) 7223 .Case("zEC12", true) 7224 .Case("arch10", true) 7225 .Case("z13", true) 7226 .Case("arch11", true) 7227 .Default(false); 7228 7229 return CPUKnown; 7230 } 7231 bool 7232 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7233 StringRef CPU, 7234 const std::vector<std::string> &FeaturesVec) const override { 7235 if (CPU == "zEC12" || CPU == "arch10") 7236 Features["transactional-execution"] = true; 7237 if (CPU == "z13" || CPU == "arch11") { 7238 Features["transactional-execution"] = true; 7239 Features["vector"] = true; 7240 } 7241 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7242 } 7243 7244 bool handleTargetFeatures(std::vector<std::string> &Features, 7245 DiagnosticsEngine &Diags) override { 7246 HasTransactionalExecution = false; 7247 for (const auto &Feature : Features) { 7248 if (Feature == "+transactional-execution") 7249 HasTransactionalExecution = true; 7250 else if (Feature == "+vector") 7251 HasVector = true; 7252 } 7253 // If we use the vector ABI, vector types are 64-bit aligned. 7254 if (HasVector) { 7255 MaxVectorAlign = 64; 7256 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7257 "-v128:64-a:8:16-n32:64"); 7258 } 7259 return true; 7260 } 7261 7262 bool hasFeature(StringRef Feature) const override { 7263 return llvm::StringSwitch<bool>(Feature) 7264 .Case("systemz", true) 7265 .Case("htm", HasTransactionalExecution) 7266 .Case("vx", HasVector) 7267 .Default(false); 7268 } 7269 7270 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7271 switch (CC) { 7272 case CC_C: 7273 case CC_Swift: 7274 return CCCR_OK; 7275 default: 7276 return CCCR_Warning; 7277 } 7278 } 7279 7280 StringRef getABI() const override { 7281 if (HasVector) 7282 return "vector"; 7283 return ""; 7284 } 7285 7286 bool useFloat128ManglingForLongDouble() const override { 7287 return true; 7288 } 7289 }; 7290 7291 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7292 #define BUILTIN(ID, TYPE, ATTRS) \ 7293 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7294 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7295 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7296 #include "clang/Basic/BuiltinsSystemZ.def" 7297 }; 7298 7299 const char *const SystemZTargetInfo::GCCRegNames[] = { 7300 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7301 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7302 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7303 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7304 }; 7305 7306 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7307 return llvm::makeArrayRef(GCCRegNames); 7308 } 7309 7310 bool SystemZTargetInfo:: 7311 validateAsmConstraint(const char *&Name, 7312 TargetInfo::ConstraintInfo &Info) const { 7313 switch (*Name) { 7314 default: 7315 return false; 7316 7317 case 'a': // Address register 7318 case 'd': // Data register (equivalent to 'r') 7319 case 'f': // Floating-point register 7320 Info.setAllowsRegister(); 7321 return true; 7322 7323 case 'I': // Unsigned 8-bit constant 7324 case 'J': // Unsigned 12-bit constant 7325 case 'K': // Signed 16-bit constant 7326 case 'L': // Signed 20-bit displacement (on all targets we support) 7327 case 'M': // 0x7fffffff 7328 return true; 7329 7330 case 'Q': // Memory with base and unsigned 12-bit displacement 7331 case 'R': // Likewise, plus an index 7332 case 'S': // Memory with base and signed 20-bit displacement 7333 case 'T': // Likewise, plus an index 7334 Info.setAllowsMemory(); 7335 return true; 7336 } 7337 } 7338 7339 class MSP430TargetInfo : public TargetInfo { 7340 static const char *const GCCRegNames[]; 7341 7342 public: 7343 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7344 : TargetInfo(Triple) { 7345 TLSSupported = false; 7346 IntWidth = 16; 7347 IntAlign = 16; 7348 LongWidth = 32; 7349 LongLongWidth = 64; 7350 LongAlign = LongLongAlign = 16; 7351 PointerWidth = 16; 7352 PointerAlign = 16; 7353 SuitableAlign = 16; 7354 SizeType = UnsignedInt; 7355 IntMaxType = SignedLongLong; 7356 IntPtrType = SignedInt; 7357 PtrDiffType = SignedInt; 7358 SigAtomicType = SignedLong; 7359 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7360 } 7361 void getTargetDefines(const LangOptions &Opts, 7362 MacroBuilder &Builder) const override { 7363 Builder.defineMacro("MSP430"); 7364 Builder.defineMacro("__MSP430__"); 7365 // FIXME: defines for different 'flavours' of MCU 7366 } 7367 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7368 // FIXME: Implement. 7369 return None; 7370 } 7371 bool hasFeature(StringRef Feature) const override { 7372 return Feature == "msp430"; 7373 } 7374 ArrayRef<const char *> getGCCRegNames() const override; 7375 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7376 // No aliases. 7377 return None; 7378 } 7379 bool validateAsmConstraint(const char *&Name, 7380 TargetInfo::ConstraintInfo &info) const override { 7381 // FIXME: implement 7382 switch (*Name) { 7383 case 'K': // the constant 1 7384 case 'L': // constant -1^20 .. 1^19 7385 case 'M': // constant 1-4: 7386 return true; 7387 } 7388 // No target constraints for now. 7389 return false; 7390 } 7391 const char *getClobbers() const override { 7392 // FIXME: Is this really right? 7393 return ""; 7394 } 7395 BuiltinVaListKind getBuiltinVaListKind() const override { 7396 // FIXME: implement 7397 return TargetInfo::CharPtrBuiltinVaList; 7398 } 7399 }; 7400 7401 const char *const MSP430TargetInfo::GCCRegNames[] = { 7402 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7403 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7404 7405 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7406 return llvm::makeArrayRef(GCCRegNames); 7407 } 7408 7409 // LLVM and Clang cannot be used directly to output native binaries for 7410 // target, but is used to compile C code to llvm bitcode with correct 7411 // type and alignment information. 7412 // 7413 // TCE uses the llvm bitcode as input and uses it for generating customized 7414 // target processor and program binary. TCE co-design environment is 7415 // publicly available in http://tce.cs.tut.fi 7416 7417 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7418 0, // Default 7419 3, // opencl_global 7420 4, // opencl_local 7421 5, // opencl_constant 7422 // FIXME: generic has to be added to the target 7423 0, // opencl_generic 7424 0, // cuda_device 7425 0, // cuda_constant 7426 0 // cuda_shared 7427 }; 7428 7429 class TCETargetInfo : public TargetInfo { 7430 public: 7431 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7432 : TargetInfo(Triple) { 7433 TLSSupported = false; 7434 IntWidth = 32; 7435 LongWidth = LongLongWidth = 32; 7436 PointerWidth = 32; 7437 IntAlign = 32; 7438 LongAlign = LongLongAlign = 32; 7439 PointerAlign = 32; 7440 SuitableAlign = 32; 7441 SizeType = UnsignedInt; 7442 IntMaxType = SignedLong; 7443 IntPtrType = SignedInt; 7444 PtrDiffType = SignedInt; 7445 FloatWidth = 32; 7446 FloatAlign = 32; 7447 DoubleWidth = 32; 7448 DoubleAlign = 32; 7449 LongDoubleWidth = 32; 7450 LongDoubleAlign = 32; 7451 FloatFormat = &llvm::APFloat::IEEEsingle(); 7452 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7453 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7454 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7455 "i16:16:32-i32:32:32-i64:32:32-" 7456 "f32:32:32-f64:32:32-v64:32:32-" 7457 "v128:32:32-v256:32:32-v512:32:32-" 7458 "v1024:32:32-a0:0:32-n32"); 7459 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7460 UseAddrSpaceMapMangling = true; 7461 } 7462 7463 void getTargetDefines(const LangOptions &Opts, 7464 MacroBuilder &Builder) const override { 7465 DefineStd(Builder, "tce", Opts); 7466 Builder.defineMacro("__TCE__"); 7467 Builder.defineMacro("__TCE_V1__"); 7468 } 7469 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7470 7471 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7472 const char *getClobbers() const override { return ""; } 7473 BuiltinVaListKind getBuiltinVaListKind() const override { 7474 return TargetInfo::VoidPtrBuiltinVaList; 7475 } 7476 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7477 bool validateAsmConstraint(const char *&Name, 7478 TargetInfo::ConstraintInfo &info) const override { 7479 return true; 7480 } 7481 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7482 return None; 7483 } 7484 }; 7485 7486 class TCELETargetInfo : public TCETargetInfo { 7487 public: 7488 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7489 : TCETargetInfo(Triple, Opts) { 7490 BigEndian = false; 7491 7492 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7493 "i16:16:32-i32:32:32-i64:32:32-" 7494 "f32:32:32-f64:32:32-v64:32:32-" 7495 "v128:32:32-v256:32:32-v512:32:32-" 7496 "v1024:32:32-a0:0:32-n32"); 7497 7498 } 7499 7500 virtual void getTargetDefines(const LangOptions &Opts, 7501 MacroBuilder &Builder) const { 7502 DefineStd(Builder, "tcele", Opts); 7503 Builder.defineMacro("__TCE__"); 7504 Builder.defineMacro("__TCE_V1__"); 7505 Builder.defineMacro("__TCELE__"); 7506 Builder.defineMacro("__TCELE_V1__"); 7507 } 7508 7509 }; 7510 7511 class BPFTargetInfo : public TargetInfo { 7512 public: 7513 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7514 : TargetInfo(Triple) { 7515 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7516 SizeType = UnsignedLong; 7517 PtrDiffType = SignedLong; 7518 IntPtrType = SignedLong; 7519 IntMaxType = SignedLong; 7520 Int64Type = SignedLong; 7521 RegParmMax = 5; 7522 if (Triple.getArch() == llvm::Triple::bpfeb) { 7523 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7524 } else { 7525 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7526 } 7527 MaxAtomicPromoteWidth = 64; 7528 MaxAtomicInlineWidth = 64; 7529 TLSSupported = false; 7530 } 7531 void getTargetDefines(const LangOptions &Opts, 7532 MacroBuilder &Builder) const override { 7533 DefineStd(Builder, "bpf", Opts); 7534 Builder.defineMacro("__BPF__"); 7535 } 7536 bool hasFeature(StringRef Feature) const override { 7537 return Feature == "bpf"; 7538 } 7539 7540 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7541 const char *getClobbers() const override { 7542 return ""; 7543 } 7544 BuiltinVaListKind getBuiltinVaListKind() const override { 7545 return TargetInfo::VoidPtrBuiltinVaList; 7546 } 7547 ArrayRef<const char *> getGCCRegNames() const override { 7548 return None; 7549 } 7550 bool validateAsmConstraint(const char *&Name, 7551 TargetInfo::ConstraintInfo &info) const override { 7552 return true; 7553 } 7554 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7555 return None; 7556 } 7557 }; 7558 7559 class MipsTargetInfo : public TargetInfo { 7560 void setDataLayout() { 7561 StringRef Layout; 7562 7563 if (ABI == "o32") 7564 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7565 else if (ABI == "n32") 7566 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7567 else if (ABI == "n64") 7568 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7569 else 7570 llvm_unreachable("Invalid ABI"); 7571 7572 if (BigEndian) 7573 resetDataLayout(("E-" + Layout).str()); 7574 else 7575 resetDataLayout(("e-" + Layout).str()); 7576 } 7577 7578 7579 static const Builtin::Info BuiltinInfo[]; 7580 std::string CPU; 7581 bool IsMips16; 7582 bool IsMicromips; 7583 bool IsNan2008; 7584 bool IsSingleFloat; 7585 bool IsNoABICalls; 7586 bool CanUseBSDABICalls; 7587 enum MipsFloatABI { 7588 HardFloat, SoftFloat 7589 } FloatABI; 7590 enum DspRevEnum { 7591 NoDSP, DSP1, DSP2 7592 } DspRev; 7593 bool HasMSA; 7594 7595 protected: 7596 bool HasFP64; 7597 std::string ABI; 7598 7599 public: 7600 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7601 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7602 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 7603 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 7604 HasMSA(false), HasFP64(false) { 7605 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7606 7607 setABI((getTriple().getArch() == llvm::Triple::mips || 7608 getTriple().getArch() == llvm::Triple::mipsel) 7609 ? "o32" 7610 : "n64"); 7611 7612 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7613 7614 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 7615 Triple.getOS() == llvm::Triple::OpenBSD; 7616 } 7617 7618 bool isNaN2008Default() const { 7619 return CPU == "mips32r6" || CPU == "mips64r6"; 7620 } 7621 7622 bool isFP64Default() const { 7623 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7624 } 7625 7626 bool isNan2008() const override { 7627 return IsNan2008; 7628 } 7629 7630 bool processorSupportsGPR64() const { 7631 return llvm::StringSwitch<bool>(CPU) 7632 .Case("mips3", true) 7633 .Case("mips4", true) 7634 .Case("mips5", true) 7635 .Case("mips64", true) 7636 .Case("mips64r2", true) 7637 .Case("mips64r3", true) 7638 .Case("mips64r5", true) 7639 .Case("mips64r6", true) 7640 .Case("octeon", true) 7641 .Default(false); 7642 return false; 7643 } 7644 7645 StringRef getABI() const override { return ABI; } 7646 bool setABI(const std::string &Name) override { 7647 if (Name == "o32") { 7648 setO32ABITypes(); 7649 ABI = Name; 7650 return true; 7651 } 7652 7653 if (Name == "n32") { 7654 setN32ABITypes(); 7655 ABI = Name; 7656 return true; 7657 } 7658 if (Name == "n64") { 7659 setN64ABITypes(); 7660 ABI = Name; 7661 return true; 7662 } 7663 return false; 7664 } 7665 7666 void setO32ABITypes() { 7667 Int64Type = SignedLongLong; 7668 IntMaxType = Int64Type; 7669 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7670 LongDoubleWidth = LongDoubleAlign = 64; 7671 LongWidth = LongAlign = 32; 7672 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7673 PointerWidth = PointerAlign = 32; 7674 PtrDiffType = SignedInt; 7675 SizeType = UnsignedInt; 7676 SuitableAlign = 64; 7677 } 7678 7679 void setN32N64ABITypes() { 7680 LongDoubleWidth = LongDoubleAlign = 128; 7681 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7682 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7683 LongDoubleWidth = LongDoubleAlign = 64; 7684 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7685 } 7686 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7687 SuitableAlign = 128; 7688 } 7689 7690 void setN64ABITypes() { 7691 setN32N64ABITypes(); 7692 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 7693 Int64Type = SignedLongLong; 7694 } else { 7695 Int64Type = SignedLong; 7696 } 7697 IntMaxType = Int64Type; 7698 LongWidth = LongAlign = 64; 7699 PointerWidth = PointerAlign = 64; 7700 PtrDiffType = SignedLong; 7701 SizeType = UnsignedLong; 7702 } 7703 7704 void setN32ABITypes() { 7705 setN32N64ABITypes(); 7706 Int64Type = SignedLongLong; 7707 IntMaxType = Int64Type; 7708 LongWidth = LongAlign = 32; 7709 PointerWidth = PointerAlign = 32; 7710 PtrDiffType = SignedInt; 7711 SizeType = UnsignedInt; 7712 } 7713 7714 bool setCPU(const std::string &Name) override { 7715 CPU = Name; 7716 return llvm::StringSwitch<bool>(Name) 7717 .Case("mips1", true) 7718 .Case("mips2", true) 7719 .Case("mips3", true) 7720 .Case("mips4", true) 7721 .Case("mips5", true) 7722 .Case("mips32", true) 7723 .Case("mips32r2", true) 7724 .Case("mips32r3", true) 7725 .Case("mips32r5", true) 7726 .Case("mips32r6", true) 7727 .Case("mips64", true) 7728 .Case("mips64r2", true) 7729 .Case("mips64r3", true) 7730 .Case("mips64r5", true) 7731 .Case("mips64r6", true) 7732 .Case("octeon", true) 7733 .Case("p5600", true) 7734 .Default(false); 7735 } 7736 const std::string& getCPU() const { return CPU; } 7737 bool 7738 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7739 StringRef CPU, 7740 const std::vector<std::string> &FeaturesVec) const override { 7741 if (CPU.empty()) 7742 CPU = getCPU(); 7743 if (CPU == "octeon") 7744 Features["mips64r2"] = Features["cnmips"] = true; 7745 else 7746 Features[CPU] = true; 7747 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7748 } 7749 7750 void getTargetDefines(const LangOptions &Opts, 7751 MacroBuilder &Builder) const override { 7752 if (BigEndian) { 7753 DefineStd(Builder, "MIPSEB", Opts); 7754 Builder.defineMacro("_MIPSEB"); 7755 } else { 7756 DefineStd(Builder, "MIPSEL", Opts); 7757 Builder.defineMacro("_MIPSEL"); 7758 } 7759 7760 Builder.defineMacro("__mips__"); 7761 Builder.defineMacro("_mips"); 7762 if (Opts.GNUMode) 7763 Builder.defineMacro("mips"); 7764 7765 if (ABI == "o32") { 7766 Builder.defineMacro("__mips", "32"); 7767 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7768 } else { 7769 Builder.defineMacro("__mips", "64"); 7770 Builder.defineMacro("__mips64"); 7771 Builder.defineMacro("__mips64__"); 7772 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7773 } 7774 7775 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7776 .Cases("mips32", "mips64", "1") 7777 .Cases("mips32r2", "mips64r2", "2") 7778 .Cases("mips32r3", "mips64r3", "3") 7779 .Cases("mips32r5", "mips64r5", "5") 7780 .Cases("mips32r6", "mips64r6", "6") 7781 .Default(""); 7782 if (!ISARev.empty()) 7783 Builder.defineMacro("__mips_isa_rev", ISARev); 7784 7785 if (ABI == "o32") { 7786 Builder.defineMacro("__mips_o32"); 7787 Builder.defineMacro("_ABIO32", "1"); 7788 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7789 } else if (ABI == "n32") { 7790 Builder.defineMacro("__mips_n32"); 7791 Builder.defineMacro("_ABIN32", "2"); 7792 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7793 } else if (ABI == "n64") { 7794 Builder.defineMacro("__mips_n64"); 7795 Builder.defineMacro("_ABI64", "3"); 7796 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7797 } else 7798 llvm_unreachable("Invalid ABI."); 7799 7800 if (!IsNoABICalls) { 7801 Builder.defineMacro("__mips_abicalls"); 7802 if (CanUseBSDABICalls) 7803 Builder.defineMacro("__ABICALLS__"); 7804 } 7805 7806 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7807 7808 switch (FloatABI) { 7809 case HardFloat: 7810 Builder.defineMacro("__mips_hard_float", Twine(1)); 7811 break; 7812 case SoftFloat: 7813 Builder.defineMacro("__mips_soft_float", Twine(1)); 7814 break; 7815 } 7816 7817 if (IsSingleFloat) 7818 Builder.defineMacro("__mips_single_float", Twine(1)); 7819 7820 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7821 Builder.defineMacro("_MIPS_FPSET", 7822 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7823 7824 if (IsMips16) 7825 Builder.defineMacro("__mips16", Twine(1)); 7826 7827 if (IsMicromips) 7828 Builder.defineMacro("__mips_micromips", Twine(1)); 7829 7830 if (IsNan2008) 7831 Builder.defineMacro("__mips_nan2008", Twine(1)); 7832 7833 switch (DspRev) { 7834 default: 7835 break; 7836 case DSP1: 7837 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7838 Builder.defineMacro("__mips_dsp", Twine(1)); 7839 break; 7840 case DSP2: 7841 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7842 Builder.defineMacro("__mips_dspr2", Twine(1)); 7843 Builder.defineMacro("__mips_dsp", Twine(1)); 7844 break; 7845 } 7846 7847 if (HasMSA) 7848 Builder.defineMacro("__mips_msa", Twine(1)); 7849 7850 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7851 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7852 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7853 7854 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7855 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7856 7857 // These shouldn't be defined for MIPS-I but there's no need to check 7858 // for that since MIPS-I isn't supported. 7859 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7860 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7861 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7862 7863 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7864 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7865 // the instructions exist but using them violates the ABI since they 7866 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7867 if (ABI == "n32" || ABI == "n64") 7868 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7869 } 7870 7871 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7872 return llvm::makeArrayRef(BuiltinInfo, 7873 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7874 } 7875 bool hasFeature(StringRef Feature) const override { 7876 return llvm::StringSwitch<bool>(Feature) 7877 .Case("mips", true) 7878 .Case("fp64", HasFP64) 7879 .Default(false); 7880 } 7881 BuiltinVaListKind getBuiltinVaListKind() const override { 7882 return TargetInfo::VoidPtrBuiltinVaList; 7883 } 7884 ArrayRef<const char *> getGCCRegNames() const override { 7885 static const char *const GCCRegNames[] = { 7886 // CPU register names 7887 // Must match second column of GCCRegAliases 7888 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7889 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7890 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7891 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7892 // Floating point register names 7893 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7894 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7895 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7896 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7897 // Hi/lo and condition register names 7898 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7899 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7900 "$ac3hi","$ac3lo", 7901 // MSA register names 7902 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7903 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7904 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7905 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7906 // MSA control register names 7907 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7908 "$msarequest", "$msamap", "$msaunmap" 7909 }; 7910 return llvm::makeArrayRef(GCCRegNames); 7911 } 7912 bool validateAsmConstraint(const char *&Name, 7913 TargetInfo::ConstraintInfo &Info) const override { 7914 switch (*Name) { 7915 default: 7916 return false; 7917 case 'r': // CPU registers. 7918 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7919 case 'y': // Equivalent to "r", backward compatibility only. 7920 case 'f': // floating-point registers. 7921 case 'c': // $25 for indirect jumps 7922 case 'l': // lo register 7923 case 'x': // hilo register pair 7924 Info.setAllowsRegister(); 7925 return true; 7926 case 'I': // Signed 16-bit constant 7927 case 'J': // Integer 0 7928 case 'K': // Unsigned 16-bit constant 7929 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7930 case 'M': // Constants not loadable via lui, addiu, or ori 7931 case 'N': // Constant -1 to -65535 7932 case 'O': // A signed 15-bit constant 7933 case 'P': // A constant between 1 go 65535 7934 return true; 7935 case 'R': // An address that can be used in a non-macro load or store 7936 Info.setAllowsMemory(); 7937 return true; 7938 case 'Z': 7939 if (Name[1] == 'C') { // An address usable by ll, and sc. 7940 Info.setAllowsMemory(); 7941 Name++; // Skip over 'Z'. 7942 return true; 7943 } 7944 return false; 7945 } 7946 } 7947 7948 std::string convertConstraint(const char *&Constraint) const override { 7949 std::string R; 7950 switch (*Constraint) { 7951 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7952 if (Constraint[1] == 'C') { 7953 R = std::string("^") + std::string(Constraint, 2); 7954 Constraint++; 7955 return R; 7956 } 7957 break; 7958 } 7959 return TargetInfo::convertConstraint(Constraint); 7960 } 7961 7962 const char *getClobbers() const override { 7963 // In GCC, $1 is not widely used in generated code (it's used only in a few 7964 // specific situations), so there is no real need for users to add it to 7965 // the clobbers list if they want to use it in their inline assembly code. 7966 // 7967 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7968 // code generation, so using it in inline assembly without adding it to the 7969 // clobbers list can cause conflicts between the inline assembly code and 7970 // the surrounding generated code. 7971 // 7972 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7973 // operands, which will conflict with the ".set at" assembler option (which 7974 // we use only for inline assembly, in order to maintain compatibility with 7975 // GCC) and will also conflict with the user's usage of $1. 7976 // 7977 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7978 // register for generated code is to automatically clobber $1 for all inline 7979 // assembly code. 7980 // 7981 // FIXME: We should automatically clobber $1 only for inline assembly code 7982 // which actually uses it. This would allow LLVM to use $1 for inline 7983 // assembly operands if the user's assembly code doesn't use it. 7984 return "~{$1}"; 7985 } 7986 7987 bool handleTargetFeatures(std::vector<std::string> &Features, 7988 DiagnosticsEngine &Diags) override { 7989 IsMips16 = false; 7990 IsMicromips = false; 7991 IsNan2008 = isNaN2008Default(); 7992 IsSingleFloat = false; 7993 FloatABI = HardFloat; 7994 DspRev = NoDSP; 7995 HasFP64 = isFP64Default(); 7996 7997 for (const auto &Feature : Features) { 7998 if (Feature == "+single-float") 7999 IsSingleFloat = true; 8000 else if (Feature == "+soft-float") 8001 FloatABI = SoftFloat; 8002 else if (Feature == "+mips16") 8003 IsMips16 = true; 8004 else if (Feature == "+micromips") 8005 IsMicromips = true; 8006 else if (Feature == "+dsp") 8007 DspRev = std::max(DspRev, DSP1); 8008 else if (Feature == "+dspr2") 8009 DspRev = std::max(DspRev, DSP2); 8010 else if (Feature == "+msa") 8011 HasMSA = true; 8012 else if (Feature == "+fp64") 8013 HasFP64 = true; 8014 else if (Feature == "-fp64") 8015 HasFP64 = false; 8016 else if (Feature == "+nan2008") 8017 IsNan2008 = true; 8018 else if (Feature == "-nan2008") 8019 IsNan2008 = false; 8020 else if (Feature == "+noabicalls") 8021 IsNoABICalls = true; 8022 } 8023 8024 setDataLayout(); 8025 8026 return true; 8027 } 8028 8029 int getEHDataRegisterNumber(unsigned RegNo) const override { 8030 if (RegNo == 0) return 4; 8031 if (RegNo == 1) return 5; 8032 return -1; 8033 } 8034 8035 bool isCLZForZeroUndef() const override { return false; } 8036 8037 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8038 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 8039 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8040 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8041 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 8042 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 8043 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 8044 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8045 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8046 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8047 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8048 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8049 {{"ra"}, "$31"}}; 8050 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 8051 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8052 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8053 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 8054 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 8055 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 8056 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8057 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8058 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8059 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8060 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8061 {{"ra"}, "$31"}}; 8062 if (ABI == "o32") 8063 return llvm::makeArrayRef(O32RegAliases); 8064 return llvm::makeArrayRef(NewABIRegAliases); 8065 } 8066 8067 bool hasInt128Type() const override { 8068 return ABI == "n32" || ABI == "n64"; 8069 } 8070 8071 bool validateTarget(DiagnosticsEngine &Diags) const override { 8072 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 8073 // this yet. It's better to fail here than on the backend assertion. 8074 if (processorSupportsGPR64() && ABI == "o32") { 8075 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8076 return false; 8077 } 8078 8079 // 64-bit ABI's require 64-bit CPU's. 8080 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 8081 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8082 return false; 8083 } 8084 8085 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 8086 // can't handle this yet. It's better to fail here than on the 8087 // backend assertion. 8088 if ((getTriple().getArch() == llvm::Triple::mips64 || 8089 getTriple().getArch() == llvm::Triple::mips64el) && 8090 ABI == "o32") { 8091 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8092 << ABI << getTriple().str(); 8093 return false; 8094 } 8095 8096 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 8097 // can't handle this yet. It's better to fail here than on the 8098 // backend assertion. 8099 if ((getTriple().getArch() == llvm::Triple::mips || 8100 getTriple().getArch() == llvm::Triple::mipsel) && 8101 (ABI == "n32" || ABI == "n64")) { 8102 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8103 << ABI << getTriple().str(); 8104 return false; 8105 } 8106 8107 return true; 8108 } 8109 }; 8110 8111 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 8112 #define BUILTIN(ID, TYPE, ATTRS) \ 8113 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8114 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8115 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8116 #include "clang/Basic/BuiltinsMips.def" 8117 }; 8118 8119 class PNaClTargetInfo : public TargetInfo { 8120 public: 8121 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8122 : TargetInfo(Triple) { 8123 this->LongAlign = 32; 8124 this->LongWidth = 32; 8125 this->PointerAlign = 32; 8126 this->PointerWidth = 32; 8127 this->IntMaxType = TargetInfo::SignedLongLong; 8128 this->Int64Type = TargetInfo::SignedLongLong; 8129 this->DoubleAlign = 64; 8130 this->LongDoubleWidth = 64; 8131 this->LongDoubleAlign = 64; 8132 this->SizeType = TargetInfo::UnsignedInt; 8133 this->PtrDiffType = TargetInfo::SignedInt; 8134 this->IntPtrType = TargetInfo::SignedInt; 8135 this->RegParmMax = 0; // Disallow regparm 8136 } 8137 8138 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8139 Builder.defineMacro("__le32__"); 8140 Builder.defineMacro("__pnacl__"); 8141 } 8142 void getTargetDefines(const LangOptions &Opts, 8143 MacroBuilder &Builder) const override { 8144 getArchDefines(Opts, Builder); 8145 } 8146 bool hasFeature(StringRef Feature) const override { 8147 return Feature == "pnacl"; 8148 } 8149 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8150 BuiltinVaListKind getBuiltinVaListKind() const override { 8151 return TargetInfo::PNaClABIBuiltinVaList; 8152 } 8153 ArrayRef<const char *> getGCCRegNames() const override; 8154 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8155 bool validateAsmConstraint(const char *&Name, 8156 TargetInfo::ConstraintInfo &Info) const override { 8157 return false; 8158 } 8159 8160 const char *getClobbers() const override { 8161 return ""; 8162 } 8163 }; 8164 8165 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8166 return None; 8167 } 8168 8169 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8170 return None; 8171 } 8172 8173 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8174 class NaClMips32TargetInfo : public MipsTargetInfo { 8175 public: 8176 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8177 : MipsTargetInfo(Triple, Opts) {} 8178 8179 BuiltinVaListKind getBuiltinVaListKind() const override { 8180 return TargetInfo::PNaClABIBuiltinVaList; 8181 } 8182 }; 8183 8184 class Le64TargetInfo : public TargetInfo { 8185 static const Builtin::Info BuiltinInfo[]; 8186 8187 public: 8188 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8189 : TargetInfo(Triple) { 8190 NoAsmVariants = true; 8191 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8192 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8193 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8194 } 8195 8196 void getTargetDefines(const LangOptions &Opts, 8197 MacroBuilder &Builder) const override { 8198 DefineStd(Builder, "unix", Opts); 8199 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8200 Builder.defineMacro("__ELF__"); 8201 } 8202 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8203 return llvm::makeArrayRef(BuiltinInfo, 8204 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8205 } 8206 BuiltinVaListKind getBuiltinVaListKind() const override { 8207 return TargetInfo::PNaClABIBuiltinVaList; 8208 } 8209 const char *getClobbers() const override { return ""; } 8210 ArrayRef<const char *> getGCCRegNames() const override { 8211 return None; 8212 } 8213 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8214 return None; 8215 } 8216 bool validateAsmConstraint(const char *&Name, 8217 TargetInfo::ConstraintInfo &Info) const override { 8218 return false; 8219 } 8220 8221 bool hasProtectedVisibility() const override { return false; } 8222 }; 8223 8224 class WebAssemblyTargetInfo : public TargetInfo { 8225 static const Builtin::Info BuiltinInfo[]; 8226 8227 enum SIMDEnum { 8228 NoSIMD, 8229 SIMD128, 8230 } SIMDLevel; 8231 8232 public: 8233 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8234 : TargetInfo(T), SIMDLevel(NoSIMD) { 8235 NoAsmVariants = true; 8236 SuitableAlign = 128; 8237 LargeArrayMinWidth = 128; 8238 LargeArrayAlign = 128; 8239 SimdDefaultAlign = 128; 8240 SigAtomicType = SignedLong; 8241 LongDoubleWidth = LongDoubleAlign = 128; 8242 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8243 SizeType = UnsignedInt; 8244 PtrDiffType = SignedInt; 8245 IntPtrType = SignedInt; 8246 } 8247 8248 protected: 8249 void getTargetDefines(const LangOptions &Opts, 8250 MacroBuilder &Builder) const override { 8251 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8252 if (SIMDLevel >= SIMD128) 8253 Builder.defineMacro("__wasm_simd128__"); 8254 } 8255 8256 private: 8257 bool 8258 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8259 StringRef CPU, 8260 const std::vector<std::string> &FeaturesVec) const override { 8261 if (CPU == "bleeding-edge") 8262 Features["simd128"] = true; 8263 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8264 } 8265 bool hasFeature(StringRef Feature) const final { 8266 return llvm::StringSwitch<bool>(Feature) 8267 .Case("simd128", SIMDLevel >= SIMD128) 8268 .Default(false); 8269 } 8270 bool handleTargetFeatures(std::vector<std::string> &Features, 8271 DiagnosticsEngine &Diags) final { 8272 for (const auto &Feature : Features) { 8273 if (Feature == "+simd128") { 8274 SIMDLevel = std::max(SIMDLevel, SIMD128); 8275 continue; 8276 } 8277 if (Feature == "-simd128") { 8278 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8279 continue; 8280 } 8281 8282 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8283 << "-target-feature"; 8284 return false; 8285 } 8286 return true; 8287 } 8288 bool setCPU(const std::string &Name) final { 8289 return llvm::StringSwitch<bool>(Name) 8290 .Case("mvp", true) 8291 .Case("bleeding-edge", true) 8292 .Case("generic", true) 8293 .Default(false); 8294 } 8295 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8296 return llvm::makeArrayRef(BuiltinInfo, 8297 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8298 } 8299 BuiltinVaListKind getBuiltinVaListKind() const final { 8300 return VoidPtrBuiltinVaList; 8301 } 8302 ArrayRef<const char *> getGCCRegNames() const final { 8303 return None; 8304 } 8305 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8306 return None; 8307 } 8308 bool 8309 validateAsmConstraint(const char *&Name, 8310 TargetInfo::ConstraintInfo &Info) const final { 8311 return false; 8312 } 8313 const char *getClobbers() const final { return ""; } 8314 bool isCLZForZeroUndef() const final { return false; } 8315 bool hasInt128Type() const final { return true; } 8316 IntType getIntTypeByWidth(unsigned BitWidth, 8317 bool IsSigned) const final { 8318 // WebAssembly prefers long long for explicitly 64-bit integers. 8319 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8320 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8321 } 8322 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8323 bool IsSigned) const final { 8324 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8325 return BitWidth == 64 8326 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8327 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8328 } 8329 }; 8330 8331 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8332 #define BUILTIN(ID, TYPE, ATTRS) \ 8333 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8334 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8335 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8336 #include "clang/Basic/BuiltinsWebAssembly.def" 8337 }; 8338 8339 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8340 public: 8341 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8342 const TargetOptions &Opts) 8343 : WebAssemblyTargetInfo(T, Opts) { 8344 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8345 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8346 } 8347 8348 protected: 8349 void getTargetDefines(const LangOptions &Opts, 8350 MacroBuilder &Builder) const override { 8351 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8352 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8353 } 8354 }; 8355 8356 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8357 public: 8358 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8359 const TargetOptions &Opts) 8360 : WebAssemblyTargetInfo(T, Opts) { 8361 LongAlign = LongWidth = 64; 8362 PointerAlign = PointerWidth = 64; 8363 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8364 SizeType = UnsignedLong; 8365 PtrDiffType = SignedLong; 8366 IntPtrType = SignedLong; 8367 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8368 } 8369 8370 protected: 8371 void getTargetDefines(const LangOptions &Opts, 8372 MacroBuilder &Builder) const override { 8373 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8374 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8375 } 8376 }; 8377 8378 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8379 #define BUILTIN(ID, TYPE, ATTRS) \ 8380 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8381 #include "clang/Basic/BuiltinsLe64.def" 8382 }; 8383 8384 static const unsigned SPIRAddrSpaceMap[] = { 8385 0, // Default 8386 1, // opencl_global 8387 3, // opencl_local 8388 2, // opencl_constant 8389 4, // opencl_generic 8390 0, // cuda_device 8391 0, // cuda_constant 8392 0 // cuda_shared 8393 }; 8394 class SPIRTargetInfo : public TargetInfo { 8395 public: 8396 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8397 : TargetInfo(Triple) { 8398 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8399 "SPIR target must use unknown OS"); 8400 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8401 "SPIR target must use unknown environment type"); 8402 TLSSupported = false; 8403 LongWidth = LongAlign = 64; 8404 AddrSpaceMap = &SPIRAddrSpaceMap; 8405 UseAddrSpaceMapMangling = true; 8406 // Define available target features 8407 // These must be defined in sorted order! 8408 NoAsmVariants = true; 8409 } 8410 void getTargetDefines(const LangOptions &Opts, 8411 MacroBuilder &Builder) const override { 8412 DefineStd(Builder, "SPIR", Opts); 8413 } 8414 bool hasFeature(StringRef Feature) const override { 8415 return Feature == "spir"; 8416 } 8417 8418 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8419 const char *getClobbers() const override { return ""; } 8420 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8421 bool validateAsmConstraint(const char *&Name, 8422 TargetInfo::ConstraintInfo &info) const override { 8423 return true; 8424 } 8425 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8426 return None; 8427 } 8428 BuiltinVaListKind getBuiltinVaListKind() const override { 8429 return TargetInfo::VoidPtrBuiltinVaList; 8430 } 8431 8432 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8433 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8434 : CCCR_Warning; 8435 } 8436 8437 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8438 return CC_SpirFunction; 8439 } 8440 8441 void setSupportedOpenCLOpts() override { 8442 // Assume all OpenCL extensions and optional core features are supported 8443 // for SPIR since it is a generic target. 8444 getSupportedOpenCLOpts().supportAll(); 8445 } 8446 }; 8447 8448 class SPIR32TargetInfo : public SPIRTargetInfo { 8449 public: 8450 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8451 : SPIRTargetInfo(Triple, Opts) { 8452 PointerWidth = PointerAlign = 32; 8453 SizeType = TargetInfo::UnsignedInt; 8454 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8455 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8456 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8457 } 8458 void getTargetDefines(const LangOptions &Opts, 8459 MacroBuilder &Builder) const override { 8460 DefineStd(Builder, "SPIR32", Opts); 8461 } 8462 }; 8463 8464 class SPIR64TargetInfo : public SPIRTargetInfo { 8465 public: 8466 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8467 : SPIRTargetInfo(Triple, Opts) { 8468 PointerWidth = PointerAlign = 64; 8469 SizeType = TargetInfo::UnsignedLong; 8470 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8471 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8472 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8473 } 8474 void getTargetDefines(const LangOptions &Opts, 8475 MacroBuilder &Builder) const override { 8476 DefineStd(Builder, "SPIR64", Opts); 8477 } 8478 }; 8479 8480 class XCoreTargetInfo : public TargetInfo { 8481 static const Builtin::Info BuiltinInfo[]; 8482 public: 8483 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8484 : TargetInfo(Triple) { 8485 NoAsmVariants = true; 8486 LongLongAlign = 32; 8487 SuitableAlign = 32; 8488 DoubleAlign = LongDoubleAlign = 32; 8489 SizeType = UnsignedInt; 8490 PtrDiffType = SignedInt; 8491 IntPtrType = SignedInt; 8492 WCharType = UnsignedChar; 8493 WIntType = UnsignedInt; 8494 UseZeroLengthBitfieldAlignment = true; 8495 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8496 "-f64:32-a:0:32-n32"); 8497 } 8498 void getTargetDefines(const LangOptions &Opts, 8499 MacroBuilder &Builder) const override { 8500 Builder.defineMacro("__XS1B__"); 8501 } 8502 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8503 return llvm::makeArrayRef(BuiltinInfo, 8504 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8505 } 8506 BuiltinVaListKind getBuiltinVaListKind() const override { 8507 return TargetInfo::VoidPtrBuiltinVaList; 8508 } 8509 const char *getClobbers() const override { 8510 return ""; 8511 } 8512 ArrayRef<const char *> getGCCRegNames() const override { 8513 static const char * const GCCRegNames[] = { 8514 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8515 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8516 }; 8517 return llvm::makeArrayRef(GCCRegNames); 8518 } 8519 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8520 return None; 8521 } 8522 bool validateAsmConstraint(const char *&Name, 8523 TargetInfo::ConstraintInfo &Info) const override { 8524 return false; 8525 } 8526 int getEHDataRegisterNumber(unsigned RegNo) const override { 8527 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8528 return (RegNo < 2)? RegNo : -1; 8529 } 8530 bool allowsLargerPreferedTypeAlignment() const override { 8531 return false; 8532 } 8533 }; 8534 8535 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8536 #define BUILTIN(ID, TYPE, ATTRS) \ 8537 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8538 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8539 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8540 #include "clang/Basic/BuiltinsXCore.def" 8541 }; 8542 8543 // x86_32 Android target 8544 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8545 public: 8546 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8547 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8548 SuitableAlign = 32; 8549 LongDoubleWidth = 64; 8550 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8551 } 8552 }; 8553 8554 // x86_64 Android target 8555 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8556 public: 8557 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8558 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8559 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8560 } 8561 8562 bool useFloat128ManglingForLongDouble() const override { 8563 return true; 8564 } 8565 }; 8566 8567 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8568 class RenderScript32TargetInfo : public ARMleTargetInfo { 8569 public: 8570 RenderScript32TargetInfo(const llvm::Triple &Triple, 8571 const TargetOptions &Opts) 8572 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8573 Triple.getOSName(), 8574 Triple.getEnvironmentName()), 8575 Opts) { 8576 IsRenderScriptTarget = true; 8577 LongWidth = LongAlign = 64; 8578 } 8579 void getTargetDefines(const LangOptions &Opts, 8580 MacroBuilder &Builder) const override { 8581 Builder.defineMacro("__RENDERSCRIPT__"); 8582 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8583 } 8584 }; 8585 8586 // 64-bit RenderScript is aarch64 8587 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8588 public: 8589 RenderScript64TargetInfo(const llvm::Triple &Triple, 8590 const TargetOptions &Opts) 8591 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8592 Triple.getOSName(), 8593 Triple.getEnvironmentName()), 8594 Opts) { 8595 IsRenderScriptTarget = true; 8596 } 8597 8598 void getTargetDefines(const LangOptions &Opts, 8599 MacroBuilder &Builder) const override { 8600 Builder.defineMacro("__RENDERSCRIPT__"); 8601 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8602 } 8603 }; 8604 8605 /// Information about a specific microcontroller. 8606 struct MCUInfo { 8607 const char *Name; 8608 const char *DefineName; 8609 }; 8610 8611 // This list should be kept up-to-date with AVRDevices.td in LLVM. 8612 static ArrayRef<MCUInfo> AVRMcus = { 8613 { "at90s1200", "__AVR_AT90S1200__" }, 8614 { "attiny11", "__AVR_ATtiny11__" }, 8615 { "attiny12", "__AVR_ATtiny12__" }, 8616 { "attiny15", "__AVR_ATtiny15__" }, 8617 { "attiny28", "__AVR_ATtiny28__" }, 8618 { "at90s2313", "__AVR_AT90S2313__" }, 8619 { "at90s2323", "__AVR_AT90S2323__" }, 8620 { "at90s2333", "__AVR_AT90S2333__" }, 8621 { "at90s2343", "__AVR_AT90S2343__" }, 8622 { "attiny22", "__AVR_ATtiny22__" }, 8623 { "attiny26", "__AVR_ATtiny26__" }, 8624 { "at86rf401", "__AVR_AT86RF401__" }, 8625 { "at90s4414", "__AVR_AT90S4414__" }, 8626 { "at90s4433", "__AVR_AT90S4433__" }, 8627 { "at90s4434", "__AVR_AT90S4434__" }, 8628 { "at90s8515", "__AVR_AT90S8515__" }, 8629 { "at90c8534", "__AVR_AT90c8534__" }, 8630 { "at90s8535", "__AVR_AT90S8535__" }, 8631 { "ata5272", "__AVR_ATA5272__" }, 8632 { "attiny13", "__AVR_ATtiny13__" }, 8633 { "attiny13a", "__AVR_ATtiny13A__" }, 8634 { "attiny2313", "__AVR_ATtiny2313__" }, 8635 { "attiny2313a", "__AVR_ATtiny2313A__" }, 8636 { "attiny24", "__AVR_ATtiny24__" }, 8637 { "attiny24a", "__AVR_ATtiny24A__" }, 8638 { "attiny4313", "__AVR_ATtiny4313__" }, 8639 { "attiny44", "__AVR_ATtiny44__" }, 8640 { "attiny44a", "__AVR_ATtiny44A__" }, 8641 { "attiny84", "__AVR_ATtiny84__" }, 8642 { "attiny84a", "__AVR_ATtiny84A__" }, 8643 { "attiny25", "__AVR_ATtiny25__" }, 8644 { "attiny45", "__AVR_ATtiny45__" }, 8645 { "attiny85", "__AVR_ATtiny85__" }, 8646 { "attiny261", "__AVR_ATtiny261__" }, 8647 { "attiny261a", "__AVR_ATtiny261A__" }, 8648 { "attiny461", "__AVR_ATtiny461__" }, 8649 { "attiny461a", "__AVR_ATtiny461A__" }, 8650 { "attiny861", "__AVR_ATtiny861__" }, 8651 { "attiny861a", "__AVR_ATtiny861A__" }, 8652 { "attiny87", "__AVR_ATtiny87__" }, 8653 { "attiny43u", "__AVR_ATtiny43U__" }, 8654 { "attiny48", "__AVR_ATtiny48__" }, 8655 { "attiny88", "__AVR_ATtiny88__" }, 8656 { "attiny828", "__AVR_ATtiny828__" }, 8657 { "at43usb355", "__AVR_AT43USB355__" }, 8658 { "at76c711", "__AVR_AT76C711__" }, 8659 { "atmega103", "__AVR_ATmega103__" }, 8660 { "at43usb320", "__AVR_AT43USB320__" }, 8661 { "attiny167", "__AVR_ATtiny167__" }, 8662 { "at90usb82", "__AVR_AT90USB82__" }, 8663 { "at90usb162", "__AVR_AT90USB162__" }, 8664 { "ata5505", "__AVR_ATA5505__" }, 8665 { "atmega8u2", "__AVR_ATmega8U2__" }, 8666 { "atmega16u2", "__AVR_ATmega16U2__" }, 8667 { "atmega32u2", "__AVR_ATmega32U2__" }, 8668 { "attiny1634", "__AVR_ATtiny1634__" }, 8669 { "atmega8", "__AVR_ATmega8__" }, 8670 { "ata6289", "__AVR_ATA6289__" }, 8671 { "atmega8a", "__AVR_ATmega8A__" }, 8672 { "ata6285", "__AVR_ATA6285__" }, 8673 { "ata6286", "__AVR_ATA6286__" }, 8674 { "atmega48", "__AVR_ATmega48__" }, 8675 { "atmega48a", "__AVR_ATmega48A__" }, 8676 { "atmega48pa", "__AVR_ATmega48PA__" }, 8677 { "atmega48p", "__AVR_ATmega48P__" }, 8678 { "atmega88", "__AVR_ATmega88__" }, 8679 { "atmega88a", "__AVR_ATmega88A__" }, 8680 { "atmega88p", "__AVR_ATmega88P__" }, 8681 { "atmega88pa", "__AVR_ATmega88PA__" }, 8682 { "atmega8515", "__AVR_ATmega8515__" }, 8683 { "atmega8535", "__AVR_ATmega8535__" }, 8684 { "atmega8hva", "__AVR_ATmega8HVA__" }, 8685 { "at90pwm1", "__AVR_AT90PWM1__" }, 8686 { "at90pwm2", "__AVR_AT90PWM2__" }, 8687 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 8688 { "at90pwm3", "__AVR_AT90PWM3__" }, 8689 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 8690 { "at90pwm81", "__AVR_AT90PWM81__" }, 8691 { "ata5790", "__AVR_ATA5790__" }, 8692 { "ata5795", "__AVR_ATA5795__" }, 8693 { "atmega16", "__AVR_ATmega16__" }, 8694 { "atmega16a", "__AVR_ATmega16A__" }, 8695 { "atmega161", "__AVR_ATmega161__" }, 8696 { "atmega162", "__AVR_ATmega162__" }, 8697 { "atmega163", "__AVR_ATmega163__" }, 8698 { "atmega164a", "__AVR_ATmega164A__" }, 8699 { "atmega164p", "__AVR_ATmega164P__" }, 8700 { "atmega164pa", "__AVR_ATmega164PA__" }, 8701 { "atmega165", "__AVR_ATmega165__" }, 8702 { "atmega165a", "__AVR_ATmega165A__" }, 8703 { "atmega165p", "__AVR_ATmega165P__" }, 8704 { "atmega165pa", "__AVR_ATmega165PA__" }, 8705 { "atmega168", "__AVR_ATmega168__" }, 8706 { "atmega168a", "__AVR_ATmega168A__" }, 8707 { "atmega168p", "__AVR_ATmega168P__" }, 8708 { "atmega168pa", "__AVR_ATmega168PA__" }, 8709 { "atmega169", "__AVR_ATmega169__" }, 8710 { "atmega169a", "__AVR_ATmega169A__" }, 8711 { "atmega169p", "__AVR_ATmega169P__" }, 8712 { "atmega169pa", "__AVR_ATmega169PA__" }, 8713 { "atmega32", "__AVR_ATmega32__" }, 8714 { "atmega32a", "__AVR_ATmega32A__" }, 8715 { "atmega323", "__AVR_ATmega323__" }, 8716 { "atmega324a", "__AVR_ATmega324A__" }, 8717 { "atmega324p", "__AVR_ATmega324P__" }, 8718 { "atmega324pa", "__AVR_ATmega324PA__" }, 8719 { "atmega325", "__AVR_ATmega325__" }, 8720 { "atmega325a", "__AVR_ATmega325A__" }, 8721 { "atmega325p", "__AVR_ATmega325P__" }, 8722 { "atmega325pa", "__AVR_ATmega325PA__" }, 8723 { "atmega3250", "__AVR_ATmega3250__" }, 8724 { "atmega3250a", "__AVR_ATmega3250A__" }, 8725 { "atmega3250p", "__AVR_ATmega3250P__" }, 8726 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 8727 { "atmega328", "__AVR_ATmega328__" }, 8728 { "atmega328p", "__AVR_ATmega328P__" }, 8729 { "atmega329", "__AVR_ATmega329__" }, 8730 { "atmega329a", "__AVR_ATmega329A__" }, 8731 { "atmega329p", "__AVR_ATmega329P__" }, 8732 { "atmega329pa", "__AVR_ATmega329PA__" }, 8733 { "atmega3290", "__AVR_ATmega3290__" }, 8734 { "atmega3290a", "__AVR_ATmega3290A__" }, 8735 { "atmega3290p", "__AVR_ATmega3290P__" }, 8736 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 8737 { "atmega406", "__AVR_ATmega406__" }, 8738 { "atmega64", "__AVR_ATmega64__" }, 8739 { "atmega64a", "__AVR_ATmega64A__" }, 8740 { "atmega640", "__AVR_ATmega640__" }, 8741 { "atmega644", "__AVR_ATmega644__" }, 8742 { "atmega644a", "__AVR_ATmega644A__" }, 8743 { "atmega644p", "__AVR_ATmega644P__" }, 8744 { "atmega644pa", "__AVR_ATmega644PA__" }, 8745 { "atmega645", "__AVR_ATmega645__" }, 8746 { "atmega645a", "__AVR_ATmega645A__" }, 8747 { "atmega645p", "__AVR_ATmega645P__" }, 8748 { "atmega649", "__AVR_ATmega649__" }, 8749 { "atmega649a", "__AVR_ATmega649A__" }, 8750 { "atmega649p", "__AVR_ATmega649P__" }, 8751 { "atmega6450", "__AVR_ATmega6450__" }, 8752 { "atmega6450a", "__AVR_ATmega6450A__" }, 8753 { "atmega6450p", "__AVR_ATmega6450P__" }, 8754 { "atmega6490", "__AVR_ATmega6490__" }, 8755 { "atmega6490a", "__AVR_ATmega6490A__" }, 8756 { "atmega6490p", "__AVR_ATmega6490P__" }, 8757 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 8758 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 8759 { "atmega16hva", "__AVR_ATmega16HVA__" }, 8760 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 8761 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 8762 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 8763 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 8764 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 8765 { "atmega64hve", "__AVR_ATmega64HVE__" }, 8766 { "at90can32", "__AVR_AT90CAN32__" }, 8767 { "at90can64", "__AVR_AT90CAN64__" }, 8768 { "at90pwm161", "__AVR_AT90PWM161__" }, 8769 { "at90pwm216", "__AVR_AT90PWM216__" }, 8770 { "at90pwm316", "__AVR_AT90PWM316__" }, 8771 { "atmega32c1", "__AVR_ATmega32C1__" }, 8772 { "atmega64c1", "__AVR_ATmega64C1__" }, 8773 { "atmega16m1", "__AVR_ATmega16M1__" }, 8774 { "atmega32m1", "__AVR_ATmega32M1__" }, 8775 { "atmega64m1", "__AVR_ATmega64M1__" }, 8776 { "atmega16u4", "__AVR_ATmega16U4__" }, 8777 { "atmega32u4", "__AVR_ATmega32U4__" }, 8778 { "atmega32u6", "__AVR_ATmega32U6__" }, 8779 { "at90usb646", "__AVR_AT90USB646__" }, 8780 { "at90usb647", "__AVR_AT90USB647__" }, 8781 { "at90scr100", "__AVR_AT90SCR100__" }, 8782 { "at94k", "__AVR_AT94K__" }, 8783 { "m3000", "__AVR_AT000__" }, 8784 { "atmega128", "__AVR_ATmega128__" }, 8785 { "atmega128a", "__AVR_ATmega128A__" }, 8786 { "atmega1280", "__AVR_ATmega1280__" }, 8787 { "atmega1281", "__AVR_ATmega1281__" }, 8788 { "atmega1284", "__AVR_ATmega1284__" }, 8789 { "atmega1284p", "__AVR_ATmega1284P__" }, 8790 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 8791 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 8792 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 8793 { "at90can128", "__AVR_AT90CAN128__" }, 8794 { "at90usb1286", "__AVR_AT90USB1286__" }, 8795 { "at90usb1287", "__AVR_AT90USB1287__" }, 8796 { "atmega2560", "__AVR_ATmega2560__" }, 8797 { "atmega2561", "__AVR_ATmega2561__" }, 8798 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 8799 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 8800 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 8801 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 8802 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 8803 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 8804 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 8805 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 8806 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 8807 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 8808 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 8809 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 8810 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 8811 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 8812 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 8813 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 8814 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 8815 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 8816 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 8817 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 8818 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 8819 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 8820 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 8821 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 8822 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 8823 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 8824 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 8825 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 8826 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 8827 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 8828 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 8829 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 8830 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 8831 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 8832 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 8833 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 8834 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 8835 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 8836 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 8837 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 8838 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 8839 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 8840 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 8841 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 8842 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 8843 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 8844 { "attiny4", "__AVR_ATtiny4__" }, 8845 { "attiny5", "__AVR_ATtiny5__" }, 8846 { "attiny9", "__AVR_ATtiny9__" }, 8847 { "attiny10", "__AVR_ATtiny10__" }, 8848 { "attiny20", "__AVR_ATtiny20__" }, 8849 { "attiny40", "__AVR_ATtiny40__" }, 8850 { "attiny102", "__AVR_ATtiny102__" }, 8851 { "attiny104", "__AVR_ATtiny104__" }, 8852 }; 8853 8854 // AVR Target 8855 class AVRTargetInfo : public TargetInfo { 8856 public: 8857 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8858 : TargetInfo(Triple) { 8859 TLSSupported = false; 8860 PointerWidth = 16; 8861 PointerAlign = 8; 8862 IntWidth = 16; 8863 IntAlign = 8; 8864 LongWidth = 32; 8865 LongAlign = 8; 8866 LongLongWidth = 64; 8867 LongLongAlign = 8; 8868 SuitableAlign = 8; 8869 DefaultAlignForAttributeAligned = 8; 8870 HalfWidth = 16; 8871 HalfAlign = 8; 8872 FloatWidth = 32; 8873 FloatAlign = 8; 8874 DoubleWidth = 32; 8875 DoubleAlign = 8; 8876 DoubleFormat = &llvm::APFloat::IEEEsingle(); 8877 LongDoubleWidth = 32; 8878 LongDoubleAlign = 8; 8879 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 8880 SizeType = UnsignedInt; 8881 PtrDiffType = SignedInt; 8882 IntPtrType = SignedInt; 8883 Char16Type = UnsignedInt; 8884 WCharType = SignedInt; 8885 WIntType = SignedInt; 8886 Char32Type = UnsignedLong; 8887 SigAtomicType = SignedChar; 8888 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 8889 "-f32:32:32-f64:64:64-n8"); 8890 } 8891 8892 void getTargetDefines(const LangOptions &Opts, 8893 MacroBuilder &Builder) const override { 8894 Builder.defineMacro("AVR"); 8895 Builder.defineMacro("__AVR"); 8896 Builder.defineMacro("__AVR__"); 8897 8898 if (!this->CPU.empty()) { 8899 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 8900 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 8901 8902 if (It != AVRMcus.end()) 8903 Builder.defineMacro(It->DefineName); 8904 } 8905 } 8906 8907 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8908 return None; 8909 } 8910 8911 BuiltinVaListKind getBuiltinVaListKind() const override { 8912 return TargetInfo::VoidPtrBuiltinVaList; 8913 } 8914 8915 const char *getClobbers() const override { 8916 return ""; 8917 } 8918 8919 ArrayRef<const char *> getGCCRegNames() const override { 8920 static const char * const GCCRegNames[] = { 8921 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8922 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 8923 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 8924 "r24", "r25", "X", "Y", "Z", "SP" 8925 }; 8926 return llvm::makeArrayRef(GCCRegNames); 8927 } 8928 8929 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8930 return None; 8931 } 8932 8933 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 8934 static const TargetInfo::AddlRegName AddlRegNames[] = { 8935 { { "r26", "r27"}, 26 }, 8936 { { "r28", "r29"}, 27 }, 8937 { { "r30", "r31"}, 28 }, 8938 { { "SPL", "SPH"}, 29 }, 8939 }; 8940 return llvm::makeArrayRef(AddlRegNames); 8941 } 8942 8943 bool validateAsmConstraint(const char *&Name, 8944 TargetInfo::ConstraintInfo &Info) const override { 8945 // There aren't any multi-character AVR specific constraints. 8946 if (StringRef(Name).size() > 1) return false; 8947 8948 switch (*Name) { 8949 default: return false; 8950 case 'a': // Simple upper registers 8951 case 'b': // Base pointer registers pairs 8952 case 'd': // Upper register 8953 case 'l': // Lower registers 8954 case 'e': // Pointer register pairs 8955 case 'q': // Stack pointer register 8956 case 'r': // Any register 8957 case 'w': // Special upper register pairs 8958 case 't': // Temporary register 8959 case 'x': case 'X': // Pointer register pair X 8960 case 'y': case 'Y': // Pointer register pair Y 8961 case 'z': case 'Z': // Pointer register pair Z 8962 Info.setAllowsRegister(); 8963 return true; 8964 case 'I': // 6-bit positive integer constant 8965 Info.setRequiresImmediate(0, 63); 8966 return true; 8967 case 'J': // 6-bit negative integer constant 8968 Info.setRequiresImmediate(-63, 0); 8969 return true; 8970 case 'K': // Integer constant (Range: 2) 8971 Info.setRequiresImmediate(2); 8972 return true; 8973 case 'L': // Integer constant (Range: 0) 8974 Info.setRequiresImmediate(0); 8975 return true; 8976 case 'M': // 8-bit integer constant 8977 Info.setRequiresImmediate(0, 0xff); 8978 return true; 8979 case 'N': // Integer constant (Range: -1) 8980 Info.setRequiresImmediate(-1); 8981 return true; 8982 case 'O': // Integer constant (Range: 8, 16, 24) 8983 Info.setRequiresImmediate({8, 16, 24}); 8984 return true; 8985 case 'P': // Integer constant (Range: 1) 8986 Info.setRequiresImmediate(1); 8987 return true; 8988 case 'R': // Integer constant (Range: -6 to 5) 8989 Info.setRequiresImmediate(-6, 5); 8990 return true; 8991 case 'G': // Floating point constant 8992 case 'Q': // A memory address based on Y or Z pointer with displacement. 8993 return true; 8994 } 8995 8996 return false; 8997 } 8998 8999 IntType getIntTypeByWidth(unsigned BitWidth, 9000 bool IsSigned) const final { 9001 // AVR prefers int for 16-bit integers. 9002 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 9003 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 9004 } 9005 9006 IntType getLeastIntTypeByWidth(unsigned BitWidth, 9007 bool IsSigned) const final { 9008 // AVR uses int for int_least16_t and int_fast16_t. 9009 return BitWidth == 16 9010 ? (IsSigned ? SignedInt : UnsignedInt) 9011 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 9012 } 9013 9014 bool setCPU(const std::string &Name) override { 9015 bool IsFamily = llvm::StringSwitch<bool>(Name) 9016 .Case("avr1", true) 9017 .Case("avr2", true) 9018 .Case("avr25", true) 9019 .Case("avr3", true) 9020 .Case("avr31", true) 9021 .Case("avr35", true) 9022 .Case("avr4", true) 9023 .Case("avr5", true) 9024 .Case("avr51", true) 9025 .Case("avr6", true) 9026 .Case("avrxmega1", true) 9027 .Case("avrxmega2", true) 9028 .Case("avrxmega3", true) 9029 .Case("avrxmega4", true) 9030 .Case("avrxmega5", true) 9031 .Case("avrxmega6", true) 9032 .Case("avrxmega7", true) 9033 .Case("avrtiny", true) 9034 .Default(false); 9035 9036 if (IsFamily) this->CPU = Name; 9037 9038 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9039 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 9040 9041 if (IsMCU) this->CPU = Name; 9042 9043 return IsFamily || IsMCU; 9044 } 9045 9046 protected: 9047 std::string CPU; 9048 }; 9049 9050 } // end anonymous namespace 9051 9052 //===----------------------------------------------------------------------===// 9053 // Driver code 9054 //===----------------------------------------------------------------------===// 9055 9056 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 9057 const TargetOptions &Opts) { 9058 llvm::Triple::OSType os = Triple.getOS(); 9059 9060 switch (Triple.getArch()) { 9061 default: 9062 return nullptr; 9063 9064 case llvm::Triple::xcore: 9065 return new XCoreTargetInfo(Triple, Opts); 9066 9067 case llvm::Triple::hexagon: 9068 return new HexagonTargetInfo(Triple, Opts); 9069 9070 case llvm::Triple::lanai: 9071 return new LanaiTargetInfo(Triple, Opts); 9072 9073 case llvm::Triple::aarch64: 9074 if (Triple.isOSDarwin()) 9075 return new DarwinAArch64TargetInfo(Triple, Opts); 9076 9077 switch (os) { 9078 case llvm::Triple::CloudABI: 9079 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 9080 case llvm::Triple::FreeBSD: 9081 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9082 case llvm::Triple::Fuchsia: 9083 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9084 case llvm::Triple::Linux: 9085 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9086 case llvm::Triple::NetBSD: 9087 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9088 case llvm::Triple::OpenBSD: 9089 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9090 default: 9091 return new AArch64leTargetInfo(Triple, Opts); 9092 } 9093 9094 case llvm::Triple::aarch64_be: 9095 switch (os) { 9096 case llvm::Triple::FreeBSD: 9097 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9098 case llvm::Triple::Fuchsia: 9099 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9100 case llvm::Triple::Linux: 9101 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9102 case llvm::Triple::NetBSD: 9103 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9104 default: 9105 return new AArch64beTargetInfo(Triple, Opts); 9106 } 9107 9108 case llvm::Triple::arm: 9109 case llvm::Triple::thumb: 9110 if (Triple.isOSBinFormatMachO()) 9111 return new DarwinARMTargetInfo(Triple, Opts); 9112 9113 switch (os) { 9114 case llvm::Triple::CloudABI: 9115 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9116 case llvm::Triple::Linux: 9117 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9118 case llvm::Triple::FreeBSD: 9119 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9120 case llvm::Triple::NetBSD: 9121 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9122 case llvm::Triple::OpenBSD: 9123 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9124 case llvm::Triple::Bitrig: 9125 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9126 case llvm::Triple::RTEMS: 9127 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9128 case llvm::Triple::NaCl: 9129 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9130 case llvm::Triple::Win32: 9131 switch (Triple.getEnvironment()) { 9132 case llvm::Triple::Cygnus: 9133 return new CygwinARMTargetInfo(Triple, Opts); 9134 case llvm::Triple::GNU: 9135 return new MinGWARMTargetInfo(Triple, Opts); 9136 case llvm::Triple::Itanium: 9137 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9138 case llvm::Triple::MSVC: 9139 default: // Assume MSVC for unknown environments 9140 return new MicrosoftARMleTargetInfo(Triple, Opts); 9141 } 9142 default: 9143 return new ARMleTargetInfo(Triple, Opts); 9144 } 9145 9146 case llvm::Triple::armeb: 9147 case llvm::Triple::thumbeb: 9148 if (Triple.isOSDarwin()) 9149 return new DarwinARMTargetInfo(Triple, Opts); 9150 9151 switch (os) { 9152 case llvm::Triple::Linux: 9153 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9154 case llvm::Triple::FreeBSD: 9155 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9156 case llvm::Triple::NetBSD: 9157 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9158 case llvm::Triple::OpenBSD: 9159 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9160 case llvm::Triple::Bitrig: 9161 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9162 case llvm::Triple::RTEMS: 9163 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9164 case llvm::Triple::NaCl: 9165 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9166 default: 9167 return new ARMbeTargetInfo(Triple, Opts); 9168 } 9169 9170 case llvm::Triple::avr: 9171 return new AVRTargetInfo(Triple, Opts); 9172 case llvm::Triple::bpfeb: 9173 case llvm::Triple::bpfel: 9174 return new BPFTargetInfo(Triple, Opts); 9175 9176 case llvm::Triple::msp430: 9177 return new MSP430TargetInfo(Triple, Opts); 9178 9179 case llvm::Triple::mips: 9180 switch (os) { 9181 case llvm::Triple::Linux: 9182 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9183 case llvm::Triple::RTEMS: 9184 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9185 case llvm::Triple::FreeBSD: 9186 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9187 case llvm::Triple::NetBSD: 9188 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9189 default: 9190 return new MipsTargetInfo(Triple, Opts); 9191 } 9192 9193 case llvm::Triple::mipsel: 9194 switch (os) { 9195 case llvm::Triple::Linux: 9196 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9197 case llvm::Triple::RTEMS: 9198 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9199 case llvm::Triple::FreeBSD: 9200 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9201 case llvm::Triple::NetBSD: 9202 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9203 case llvm::Triple::NaCl: 9204 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9205 default: 9206 return new MipsTargetInfo(Triple, Opts); 9207 } 9208 9209 case llvm::Triple::mips64: 9210 switch (os) { 9211 case llvm::Triple::Linux: 9212 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9213 case llvm::Triple::RTEMS: 9214 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9215 case llvm::Triple::FreeBSD: 9216 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9217 case llvm::Triple::NetBSD: 9218 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9219 case llvm::Triple::OpenBSD: 9220 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9221 default: 9222 return new MipsTargetInfo(Triple, Opts); 9223 } 9224 9225 case llvm::Triple::mips64el: 9226 switch (os) { 9227 case llvm::Triple::Linux: 9228 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9229 case llvm::Triple::RTEMS: 9230 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9231 case llvm::Triple::FreeBSD: 9232 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9233 case llvm::Triple::NetBSD: 9234 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9235 case llvm::Triple::OpenBSD: 9236 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9237 default: 9238 return new MipsTargetInfo(Triple, Opts); 9239 } 9240 9241 case llvm::Triple::le32: 9242 switch (os) { 9243 case llvm::Triple::NaCl: 9244 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9245 default: 9246 return nullptr; 9247 } 9248 9249 case llvm::Triple::le64: 9250 return new Le64TargetInfo(Triple, Opts); 9251 9252 case llvm::Triple::ppc: 9253 if (Triple.isOSDarwin()) 9254 return new DarwinPPC32TargetInfo(Triple, Opts); 9255 switch (os) { 9256 case llvm::Triple::Linux: 9257 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9258 case llvm::Triple::FreeBSD: 9259 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9260 case llvm::Triple::NetBSD: 9261 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9262 case llvm::Triple::OpenBSD: 9263 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9264 case llvm::Triple::RTEMS: 9265 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9266 default: 9267 return new PPC32TargetInfo(Triple, Opts); 9268 } 9269 9270 case llvm::Triple::ppc64: 9271 if (Triple.isOSDarwin()) 9272 return new DarwinPPC64TargetInfo(Triple, Opts); 9273 switch (os) { 9274 case llvm::Triple::Linux: 9275 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9276 case llvm::Triple::Lv2: 9277 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9278 case llvm::Triple::FreeBSD: 9279 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9280 case llvm::Triple::NetBSD: 9281 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9282 default: 9283 return new PPC64TargetInfo(Triple, Opts); 9284 } 9285 9286 case llvm::Triple::ppc64le: 9287 switch (os) { 9288 case llvm::Triple::Linux: 9289 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9290 case llvm::Triple::NetBSD: 9291 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9292 default: 9293 return new PPC64TargetInfo(Triple, Opts); 9294 } 9295 9296 case llvm::Triple::nvptx: 9297 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9298 case llvm::Triple::nvptx64: 9299 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9300 9301 case llvm::Triple::amdgcn: 9302 case llvm::Triple::r600: 9303 return new AMDGPUTargetInfo(Triple, Opts); 9304 9305 case llvm::Triple::sparc: 9306 switch (os) { 9307 case llvm::Triple::Linux: 9308 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9309 case llvm::Triple::Solaris: 9310 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9311 case llvm::Triple::NetBSD: 9312 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9313 case llvm::Triple::OpenBSD: 9314 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9315 case llvm::Triple::RTEMS: 9316 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9317 default: 9318 return new SparcV8TargetInfo(Triple, Opts); 9319 } 9320 9321 // The 'sparcel' architecture copies all the above cases except for Solaris. 9322 case llvm::Triple::sparcel: 9323 switch (os) { 9324 case llvm::Triple::Linux: 9325 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9326 case llvm::Triple::NetBSD: 9327 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9328 case llvm::Triple::OpenBSD: 9329 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9330 case llvm::Triple::RTEMS: 9331 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9332 default: 9333 return new SparcV8elTargetInfo(Triple, Opts); 9334 } 9335 9336 case llvm::Triple::sparcv9: 9337 switch (os) { 9338 case llvm::Triple::Linux: 9339 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9340 case llvm::Triple::Solaris: 9341 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9342 case llvm::Triple::NetBSD: 9343 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9344 case llvm::Triple::OpenBSD: 9345 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9346 case llvm::Triple::FreeBSD: 9347 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9348 default: 9349 return new SparcV9TargetInfo(Triple, Opts); 9350 } 9351 9352 case llvm::Triple::systemz: 9353 switch (os) { 9354 case llvm::Triple::Linux: 9355 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9356 default: 9357 return new SystemZTargetInfo(Triple, Opts); 9358 } 9359 9360 case llvm::Triple::tce: 9361 return new TCETargetInfo(Triple, Opts); 9362 9363 case llvm::Triple::tcele: 9364 return new TCELETargetInfo(Triple, Opts); 9365 9366 case llvm::Triple::x86: 9367 if (Triple.isOSDarwin()) 9368 return new DarwinI386TargetInfo(Triple, Opts); 9369 9370 switch (os) { 9371 case llvm::Triple::CloudABI: 9372 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9373 case llvm::Triple::Linux: { 9374 switch (Triple.getEnvironment()) { 9375 default: 9376 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9377 case llvm::Triple::Android: 9378 return new AndroidX86_32TargetInfo(Triple, Opts); 9379 } 9380 } 9381 case llvm::Triple::DragonFly: 9382 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9383 case llvm::Triple::NetBSD: 9384 return new NetBSDI386TargetInfo(Triple, Opts); 9385 case llvm::Triple::OpenBSD: 9386 return new OpenBSDI386TargetInfo(Triple, Opts); 9387 case llvm::Triple::Bitrig: 9388 return new BitrigI386TargetInfo(Triple, Opts); 9389 case llvm::Triple::FreeBSD: 9390 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9391 case llvm::Triple::KFreeBSD: 9392 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9393 case llvm::Triple::Minix: 9394 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9395 case llvm::Triple::Solaris: 9396 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9397 case llvm::Triple::Win32: { 9398 switch (Triple.getEnvironment()) { 9399 case llvm::Triple::Cygnus: 9400 return new CygwinX86_32TargetInfo(Triple, Opts); 9401 case llvm::Triple::GNU: 9402 return new MinGWX86_32TargetInfo(Triple, Opts); 9403 case llvm::Triple::Itanium: 9404 case llvm::Triple::MSVC: 9405 default: // Assume MSVC for unknown environments 9406 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9407 } 9408 } 9409 case llvm::Triple::Haiku: 9410 return new HaikuX86_32TargetInfo(Triple, Opts); 9411 case llvm::Triple::RTEMS: 9412 return new RTEMSX86_32TargetInfo(Triple, Opts); 9413 case llvm::Triple::NaCl: 9414 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9415 case llvm::Triple::ELFIAMCU: 9416 return new MCUX86_32TargetInfo(Triple, Opts); 9417 default: 9418 return new X86_32TargetInfo(Triple, Opts); 9419 } 9420 9421 case llvm::Triple::x86_64: 9422 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9423 return new DarwinX86_64TargetInfo(Triple, Opts); 9424 9425 switch (os) { 9426 case llvm::Triple::CloudABI: 9427 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9428 case llvm::Triple::Linux: { 9429 switch (Triple.getEnvironment()) { 9430 default: 9431 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9432 case llvm::Triple::Android: 9433 return new AndroidX86_64TargetInfo(Triple, Opts); 9434 } 9435 } 9436 case llvm::Triple::DragonFly: 9437 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9438 case llvm::Triple::NetBSD: 9439 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9440 case llvm::Triple::OpenBSD: 9441 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9442 case llvm::Triple::Bitrig: 9443 return new BitrigX86_64TargetInfo(Triple, Opts); 9444 case llvm::Triple::FreeBSD: 9445 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9446 case llvm::Triple::Fuchsia: 9447 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9448 case llvm::Triple::KFreeBSD: 9449 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9450 case llvm::Triple::Solaris: 9451 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9452 case llvm::Triple::Win32: { 9453 switch (Triple.getEnvironment()) { 9454 case llvm::Triple::Cygnus: 9455 return new CygwinX86_64TargetInfo(Triple, Opts); 9456 case llvm::Triple::GNU: 9457 return new MinGWX86_64TargetInfo(Triple, Opts); 9458 case llvm::Triple::MSVC: 9459 default: // Assume MSVC for unknown environments 9460 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9461 } 9462 } 9463 case llvm::Triple::Haiku: 9464 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9465 case llvm::Triple::NaCl: 9466 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9467 case llvm::Triple::PS4: 9468 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9469 default: 9470 return new X86_64TargetInfo(Triple, Opts); 9471 } 9472 9473 case llvm::Triple::spir: { 9474 if (Triple.getOS() != llvm::Triple::UnknownOS || 9475 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9476 return nullptr; 9477 return new SPIR32TargetInfo(Triple, Opts); 9478 } 9479 case llvm::Triple::spir64: { 9480 if (Triple.getOS() != llvm::Triple::UnknownOS || 9481 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9482 return nullptr; 9483 return new SPIR64TargetInfo(Triple, Opts); 9484 } 9485 case llvm::Triple::wasm32: 9486 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9487 Triple.getVendor() != llvm::Triple::UnknownVendor || 9488 Triple.getOS() != llvm::Triple::UnknownOS || 9489 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9490 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9491 return nullptr; 9492 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9493 case llvm::Triple::wasm64: 9494 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9495 Triple.getVendor() != llvm::Triple::UnknownVendor || 9496 Triple.getOS() != llvm::Triple::UnknownOS || 9497 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9498 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9499 return nullptr; 9500 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9501 9502 case llvm::Triple::renderscript32: 9503 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9504 case llvm::Triple::renderscript64: 9505 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9506 } 9507 } 9508 9509 /// CreateTargetInfo - Return the target info object for the specified target 9510 /// options. 9511 TargetInfo * 9512 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9513 const std::shared_ptr<TargetOptions> &Opts) { 9514 llvm::Triple Triple(Opts->Triple); 9515 9516 // Construct the target 9517 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9518 if (!Target) { 9519 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9520 return nullptr; 9521 } 9522 Target->TargetOpts = Opts; 9523 9524 // Set the target CPU if specified. 9525 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9526 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9527 return nullptr; 9528 } 9529 9530 // Set the target ABI if specified. 9531 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 9532 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 9533 return nullptr; 9534 } 9535 9536 // Set the fp math unit. 9537 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 9538 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 9539 return nullptr; 9540 } 9541 9542 // Compute the default target features, we need the target to handle this 9543 // because features may have dependencies on one another. 9544 llvm::StringMap<bool> Features; 9545 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 9546 Opts->FeaturesAsWritten)) 9547 return nullptr; 9548 9549 // Add the features to the compile options. 9550 Opts->Features.clear(); 9551 for (const auto &F : Features) 9552 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 9553 9554 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 9555 return nullptr; 9556 9557 Target->setSupportedOpenCLOpts(); 9558 Target->setOpenCLExtensionOpts(); 9559 9560 if (!Target->validateTarget(Diags)) 9561 return nullptr; 9562 9563 return Target.release(); 9564 } 9565