1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 //===----------------------------------------------------------------------===// 69 // Defines specific to certain operating systems. 70 //===----------------------------------------------------------------------===// 71 72 namespace { 73 template<typename TgtInfo> 74 class OSTargetInfo : public TgtInfo { 75 protected: 76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 77 MacroBuilder &Builder) const=0; 78 public: 79 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 80 void getTargetDefines(const LangOptions &Opts, 81 MacroBuilder &Builder) const override { 82 TgtInfo::getTargetDefines(Opts, Builder); 83 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 84 } 85 86 }; 87 88 // CloudABI Target 89 template <typename Target> 90 class CloudABITargetInfo : public OSTargetInfo<Target> { 91 protected: 92 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 93 MacroBuilder &Builder) const override { 94 Builder.defineMacro("__CloudABI__"); 95 Builder.defineMacro("__ELF__"); 96 97 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 98 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 99 Builder.defineMacro("__STDC_UTF_16__"); 100 Builder.defineMacro("__STDC_UTF_32__"); 101 } 102 103 public: 104 CloudABITargetInfo(const llvm::Triple &Triple) 105 : OSTargetInfo<Target>(Triple) {} 106 }; 107 108 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 109 const llvm::Triple &Triple, 110 StringRef &PlatformName, 111 VersionTuple &PlatformMinVersion) { 112 Builder.defineMacro("__APPLE_CC__", "6000"); 113 Builder.defineMacro("__APPLE__"); 114 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 115 // AddressSanitizer doesn't play well with source fortification, which is on 116 // by default on Darwin. 117 if (Opts.Sanitize.has(SanitizerKind::Address)) 118 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 119 120 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 121 if (!Opts.ObjC1) { 122 // __weak is always defined, for use in blocks and with objc pointers. 123 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 124 Builder.defineMacro("__strong", ""); 125 Builder.defineMacro("__unsafe_unretained", ""); 126 } 127 128 if (Opts.Static) 129 Builder.defineMacro("__STATIC__"); 130 else 131 Builder.defineMacro("__DYNAMIC__"); 132 133 if (Opts.POSIXThreads) 134 Builder.defineMacro("_REENTRANT"); 135 136 // Get the platform type and version number from the triple. 137 unsigned Maj, Min, Rev; 138 if (Triple.isMacOSX()) { 139 Triple.getMacOSXVersion(Maj, Min, Rev); 140 PlatformName = "macosx"; 141 } else { 142 Triple.getOSVersion(Maj, Min, Rev); 143 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 144 } 145 146 // If -target arch-pc-win32-macho option specified, we're 147 // generating code for Win32 ABI. No need to emit 148 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 149 if (PlatformName == "win32") { 150 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 151 return; 152 } 153 154 // Set the appropriate OS version define. 155 if (Triple.isiOS()) { 156 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 157 char Str[6]; 158 Str[0] = '0' + Maj; 159 Str[1] = '0' + (Min / 10); 160 Str[2] = '0' + (Min % 10); 161 Str[3] = '0' + (Rev / 10); 162 Str[4] = '0' + (Rev % 10); 163 Str[5] = '\0'; 164 if (Triple.isTvOS()) 165 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 166 else 167 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 168 Str); 169 170 } else if (Triple.isWatchOS()) { 171 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 172 char Str[6]; 173 Str[0] = '0' + Maj; 174 Str[1] = '0' + (Min / 10); 175 Str[2] = '0' + (Min % 10); 176 Str[3] = '0' + (Rev / 10); 177 Str[4] = '0' + (Rev % 10); 178 Str[5] = '\0'; 179 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 180 } else if (Triple.isMacOSX()) { 181 // Note that the Driver allows versions which aren't representable in the 182 // define (because we only get a single digit for the minor and micro 183 // revision numbers). So, we limit them to the maximum representable 184 // version. 185 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 186 char Str[7]; 187 if (Maj < 10 || (Maj == 10 && Min < 10)) { 188 Str[0] = '0' + (Maj / 10); 189 Str[1] = '0' + (Maj % 10); 190 Str[2] = '0' + std::min(Min, 9U); 191 Str[3] = '0' + std::min(Rev, 9U); 192 Str[4] = '\0'; 193 } else { 194 // Handle versions > 10.9. 195 Str[0] = '0' + (Maj / 10); 196 Str[1] = '0' + (Maj % 10); 197 Str[2] = '0' + (Min / 10); 198 Str[3] = '0' + (Min % 10); 199 Str[4] = '0' + (Rev / 10); 200 Str[5] = '0' + (Rev % 10); 201 Str[6] = '\0'; 202 } 203 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 204 } 205 206 // Tell users about the kernel if there is one. 207 if (Triple.isOSDarwin()) 208 Builder.defineMacro("__MACH__"); 209 210 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 211 } 212 213 template<typename Target> 214 class DarwinTargetInfo : public OSTargetInfo<Target> { 215 protected: 216 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 217 MacroBuilder &Builder) const override { 218 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 219 this->PlatformMinVersion); 220 } 221 222 public: 223 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 224 // By default, no TLS, and we whitelist permitted architecture/OS 225 // combinations. 226 this->TLSSupported = false; 227 228 if (Triple.isMacOSX()) 229 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 230 else if (Triple.isiOS()) { 231 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 232 if (Triple.getArch() == llvm::Triple::x86_64 || 233 Triple.getArch() == llvm::Triple::aarch64) 234 this->TLSSupported = !Triple.isOSVersionLT(8); 235 else if (Triple.getArch() == llvm::Triple::x86 || 236 Triple.getArch() == llvm::Triple::arm || 237 Triple.getArch() == llvm::Triple::thumb) 238 this->TLSSupported = !Triple.isOSVersionLT(9); 239 } else if (Triple.isWatchOS()) 240 this->TLSSupported = !Triple.isOSVersionLT(2); 241 242 this->MCountName = "\01mcount"; 243 } 244 245 std::string isValidSectionSpecifier(StringRef SR) const override { 246 // Let MCSectionMachO validate this. 247 StringRef Segment, Section; 248 unsigned TAA, StubSize; 249 bool HasTAA; 250 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 251 TAA, HasTAA, StubSize); 252 } 253 254 const char *getStaticInitSectionSpecifier() const override { 255 // FIXME: We should return 0 when building kexts. 256 return "__TEXT,__StaticInit,regular,pure_instructions"; 257 } 258 259 /// Darwin does not support protected visibility. Darwin's "default" 260 /// is very similar to ELF's "protected"; Darwin requires a "weak" 261 /// attribute on declarations that can be dynamically replaced. 262 bool hasProtectedVisibility() const override { 263 return false; 264 } 265 266 unsigned getExnObjectAlignment() const override { 267 // The alignment of an exception object is 8-bytes for darwin since 268 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 269 // and therefore doesn't guarantee 16-byte alignment. 270 return 64; 271 } 272 }; 273 274 275 // DragonFlyBSD Target 276 template<typename Target> 277 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 278 protected: 279 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 280 MacroBuilder &Builder) const override { 281 // DragonFly defines; list based off of gcc output 282 Builder.defineMacro("__DragonFly__"); 283 Builder.defineMacro("__DragonFly_cc_version", "100001"); 284 Builder.defineMacro("__ELF__"); 285 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 286 Builder.defineMacro("__tune_i386__"); 287 DefineStd(Builder, "unix", Opts); 288 } 289 public: 290 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 291 : OSTargetInfo<Target>(Triple) { 292 switch (Triple.getArch()) { 293 default: 294 case llvm::Triple::x86: 295 case llvm::Triple::x86_64: 296 this->MCountName = ".mcount"; 297 break; 298 } 299 } 300 }; 301 302 // FreeBSD Target 303 template<typename Target> 304 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 305 protected: 306 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 307 MacroBuilder &Builder) const override { 308 // FreeBSD defines; list based off of gcc output 309 310 unsigned Release = Triple.getOSMajorVersion(); 311 if (Release == 0U) 312 Release = 8; 313 314 Builder.defineMacro("__FreeBSD__", Twine(Release)); 315 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 316 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 317 DefineStd(Builder, "unix", Opts); 318 Builder.defineMacro("__ELF__"); 319 320 // On FreeBSD, wchar_t contains the number of the code point as 321 // used by the character set of the locale. These character sets are 322 // not necessarily a superset of ASCII. 323 // 324 // FIXME: This is wrong; the macro refers to the numerical values 325 // of wchar_t *literals*, which are not locale-dependent. However, 326 // FreeBSD systems apparently depend on us getting this wrong, and 327 // setting this to 1 is conforming even if all the basic source 328 // character literals have the same encoding as char and wchar_t. 329 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 330 } 331 public: 332 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 333 switch (Triple.getArch()) { 334 default: 335 case llvm::Triple::x86: 336 case llvm::Triple::x86_64: 337 this->MCountName = ".mcount"; 338 break; 339 case llvm::Triple::mips: 340 case llvm::Triple::mipsel: 341 case llvm::Triple::ppc: 342 case llvm::Triple::ppc64: 343 case llvm::Triple::ppc64le: 344 this->MCountName = "_mcount"; 345 break; 346 case llvm::Triple::arm: 347 this->MCountName = "__mcount"; 348 break; 349 } 350 } 351 }; 352 353 // GNU/kFreeBSD Target 354 template<typename Target> 355 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 356 protected: 357 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 358 MacroBuilder &Builder) const override { 359 // GNU/kFreeBSD defines; list based off of gcc output 360 361 DefineStd(Builder, "unix", Opts); 362 Builder.defineMacro("__FreeBSD_kernel__"); 363 Builder.defineMacro("__GLIBC__"); 364 Builder.defineMacro("__ELF__"); 365 if (Opts.POSIXThreads) 366 Builder.defineMacro("_REENTRANT"); 367 if (Opts.CPlusPlus) 368 Builder.defineMacro("_GNU_SOURCE"); 369 } 370 public: 371 KFreeBSDTargetInfo(const llvm::Triple &Triple) 372 : OSTargetInfo<Target>(Triple) {} 373 }; 374 375 // Minix Target 376 template<typename Target> 377 class MinixTargetInfo : public OSTargetInfo<Target> { 378 protected: 379 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 380 MacroBuilder &Builder) const override { 381 // Minix defines 382 383 Builder.defineMacro("__minix", "3"); 384 Builder.defineMacro("_EM_WSIZE", "4"); 385 Builder.defineMacro("_EM_PSIZE", "4"); 386 Builder.defineMacro("_EM_SSIZE", "2"); 387 Builder.defineMacro("_EM_LSIZE", "4"); 388 Builder.defineMacro("_EM_FSIZE", "4"); 389 Builder.defineMacro("_EM_DSIZE", "8"); 390 Builder.defineMacro("__ELF__"); 391 DefineStd(Builder, "unix", Opts); 392 } 393 public: 394 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 395 }; 396 397 // Linux target 398 template<typename Target> 399 class LinuxTargetInfo : public OSTargetInfo<Target> { 400 protected: 401 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 402 MacroBuilder &Builder) const override { 403 // Linux defines; list based off of gcc output 404 DefineStd(Builder, "unix", Opts); 405 DefineStd(Builder, "linux", Opts); 406 Builder.defineMacro("__gnu_linux__"); 407 Builder.defineMacro("__ELF__"); 408 if (Triple.isAndroid()) { 409 Builder.defineMacro("__ANDROID__", "1"); 410 unsigned Maj, Min, Rev; 411 Triple.getEnvironmentVersion(Maj, Min, Rev); 412 this->PlatformName = "android"; 413 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 414 } 415 if (Opts.POSIXThreads) 416 Builder.defineMacro("_REENTRANT"); 417 if (Opts.CPlusPlus) 418 Builder.defineMacro("_GNU_SOURCE"); 419 } 420 public: 421 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 422 this->WIntType = TargetInfo::UnsignedInt; 423 424 switch (Triple.getArch()) { 425 default: 426 break; 427 case llvm::Triple::ppc: 428 case llvm::Triple::ppc64: 429 case llvm::Triple::ppc64le: 430 this->MCountName = "_mcount"; 431 break; 432 } 433 } 434 435 const char *getStaticInitSectionSpecifier() const override { 436 return ".text.startup"; 437 } 438 }; 439 440 // NetBSD Target 441 template<typename Target> 442 class NetBSDTargetInfo : public OSTargetInfo<Target> { 443 protected: 444 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 445 MacroBuilder &Builder) const override { 446 // NetBSD defines; list based off of gcc output 447 Builder.defineMacro("__NetBSD__"); 448 Builder.defineMacro("__unix__"); 449 Builder.defineMacro("__ELF__"); 450 if (Opts.POSIXThreads) 451 Builder.defineMacro("_POSIX_THREADS"); 452 453 switch (Triple.getArch()) { 454 default: 455 break; 456 case llvm::Triple::arm: 457 case llvm::Triple::armeb: 458 case llvm::Triple::thumb: 459 case llvm::Triple::thumbeb: 460 Builder.defineMacro("__ARM_DWARF_EH__"); 461 break; 462 } 463 } 464 public: 465 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 466 this->MCountName = "_mcount"; 467 } 468 }; 469 470 // OpenBSD Target 471 template<typename Target> 472 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 473 protected: 474 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 475 MacroBuilder &Builder) const override { 476 // OpenBSD defines; list based off of gcc output 477 478 Builder.defineMacro("__OpenBSD__"); 479 DefineStd(Builder, "unix", Opts); 480 Builder.defineMacro("__ELF__"); 481 if (Opts.POSIXThreads) 482 Builder.defineMacro("_REENTRANT"); 483 } 484 public: 485 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 486 this->TLSSupported = false; 487 488 switch (Triple.getArch()) { 489 default: 490 case llvm::Triple::x86: 491 case llvm::Triple::x86_64: 492 case llvm::Triple::arm: 493 case llvm::Triple::sparc: 494 this->MCountName = "__mcount"; 495 break; 496 case llvm::Triple::mips64: 497 case llvm::Triple::mips64el: 498 case llvm::Triple::ppc: 499 case llvm::Triple::sparcv9: 500 this->MCountName = "_mcount"; 501 break; 502 } 503 } 504 }; 505 506 // Bitrig Target 507 template<typename Target> 508 class BitrigTargetInfo : public OSTargetInfo<Target> { 509 protected: 510 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 511 MacroBuilder &Builder) const override { 512 // Bitrig defines; list based off of gcc output 513 514 Builder.defineMacro("__Bitrig__"); 515 DefineStd(Builder, "unix", Opts); 516 Builder.defineMacro("__ELF__"); 517 if (Opts.POSIXThreads) 518 Builder.defineMacro("_REENTRANT"); 519 520 switch (Triple.getArch()) { 521 default: 522 break; 523 case llvm::Triple::arm: 524 case llvm::Triple::armeb: 525 case llvm::Triple::thumb: 526 case llvm::Triple::thumbeb: 527 Builder.defineMacro("__ARM_DWARF_EH__"); 528 break; 529 } 530 } 531 public: 532 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 533 this->MCountName = "__mcount"; 534 } 535 }; 536 537 // PSP Target 538 template<typename Target> 539 class PSPTargetInfo : public OSTargetInfo<Target> { 540 protected: 541 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 542 MacroBuilder &Builder) const override { 543 // PSP defines; list based on the output of the pspdev gcc toolchain. 544 Builder.defineMacro("PSP"); 545 Builder.defineMacro("_PSP"); 546 Builder.defineMacro("__psp__"); 547 Builder.defineMacro("__ELF__"); 548 } 549 public: 550 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 551 }; 552 553 // PS3 PPU Target 554 template<typename Target> 555 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 556 protected: 557 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 558 MacroBuilder &Builder) const override { 559 // PS3 PPU defines. 560 Builder.defineMacro("__PPC__"); 561 Builder.defineMacro("__PPU__"); 562 Builder.defineMacro("__CELLOS_LV2__"); 563 Builder.defineMacro("__ELF__"); 564 Builder.defineMacro("__LP32__"); 565 Builder.defineMacro("_ARCH_PPC64"); 566 Builder.defineMacro("__powerpc64__"); 567 } 568 public: 569 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 570 this->LongWidth = this->LongAlign = 32; 571 this->PointerWidth = this->PointerAlign = 32; 572 this->IntMaxType = TargetInfo::SignedLongLong; 573 this->Int64Type = TargetInfo::SignedLongLong; 574 this->SizeType = TargetInfo::UnsignedInt; 575 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 576 } 577 }; 578 579 template <typename Target> 580 class PS4OSTargetInfo : public OSTargetInfo<Target> { 581 protected: 582 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 583 MacroBuilder &Builder) const override { 584 Builder.defineMacro("__FreeBSD__", "9"); 585 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 586 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 587 DefineStd(Builder, "unix", Opts); 588 Builder.defineMacro("__ELF__"); 589 Builder.defineMacro("__PS4__"); 590 } 591 public: 592 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 593 this->WCharType = this->UnsignedShort; 594 595 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 596 this->MaxTLSAlign = 256; 597 598 // On PS4, do not honor explicit bit field alignment, 599 // as in "__attribute__((aligned(2))) int b : 1;". 600 this->UseExplicitBitFieldAlignment = false; 601 602 switch (Triple.getArch()) { 603 default: 604 case llvm::Triple::x86_64: 605 this->MCountName = ".mcount"; 606 break; 607 } 608 } 609 }; 610 611 // Solaris target 612 template<typename Target> 613 class SolarisTargetInfo : public OSTargetInfo<Target> { 614 protected: 615 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 616 MacroBuilder &Builder) const override { 617 DefineStd(Builder, "sun", Opts); 618 DefineStd(Builder, "unix", Opts); 619 Builder.defineMacro("__ELF__"); 620 Builder.defineMacro("__svr4__"); 621 Builder.defineMacro("__SVR4"); 622 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 623 // newer, but to 500 for everything else. feature_test.h has a check to 624 // ensure that you are not using C99 with an old version of X/Open or C89 625 // with a new version. 626 if (Opts.C99) 627 Builder.defineMacro("_XOPEN_SOURCE", "600"); 628 else 629 Builder.defineMacro("_XOPEN_SOURCE", "500"); 630 if (Opts.CPlusPlus) 631 Builder.defineMacro("__C99FEATURES__"); 632 Builder.defineMacro("_LARGEFILE_SOURCE"); 633 Builder.defineMacro("_LARGEFILE64_SOURCE"); 634 Builder.defineMacro("__EXTENSIONS__"); 635 Builder.defineMacro("_REENTRANT"); 636 } 637 public: 638 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 639 this->WCharType = this->SignedInt; 640 // FIXME: WIntType should be SignedLong 641 } 642 }; 643 644 // Windows target 645 template<typename Target> 646 class WindowsTargetInfo : public OSTargetInfo<Target> { 647 protected: 648 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 649 MacroBuilder &Builder) const override { 650 Builder.defineMacro("_WIN32"); 651 } 652 void getVisualStudioDefines(const LangOptions &Opts, 653 MacroBuilder &Builder) const { 654 if (Opts.CPlusPlus) { 655 if (Opts.RTTIData) 656 Builder.defineMacro("_CPPRTTI"); 657 658 if (Opts.CXXExceptions) 659 Builder.defineMacro("_CPPUNWIND"); 660 } 661 662 if (Opts.Bool) 663 Builder.defineMacro("__BOOL_DEFINED"); 664 665 if (!Opts.CharIsSigned) 666 Builder.defineMacro("_CHAR_UNSIGNED"); 667 668 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 669 // but it works for now. 670 if (Opts.POSIXThreads) 671 Builder.defineMacro("_MT"); 672 673 if (Opts.MSCompatibilityVersion) { 674 Builder.defineMacro("_MSC_VER", 675 Twine(Opts.MSCompatibilityVersion / 100000)); 676 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 677 // FIXME We cannot encode the revision information into 32-bits 678 Builder.defineMacro("_MSC_BUILD", Twine(1)); 679 680 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 681 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 682 } 683 684 if (Opts.MicrosoftExt) { 685 Builder.defineMacro("_MSC_EXTENSIONS"); 686 687 if (Opts.CPlusPlus11) { 688 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 689 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 690 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 691 } 692 } 693 694 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 695 } 696 697 public: 698 WindowsTargetInfo(const llvm::Triple &Triple) 699 : OSTargetInfo<Target>(Triple) {} 700 }; 701 702 template <typename Target> 703 class NaClTargetInfo : public OSTargetInfo<Target> { 704 protected: 705 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 706 MacroBuilder &Builder) const override { 707 if (Opts.POSIXThreads) 708 Builder.defineMacro("_REENTRANT"); 709 if (Opts.CPlusPlus) 710 Builder.defineMacro("_GNU_SOURCE"); 711 712 DefineStd(Builder, "unix", Opts); 713 Builder.defineMacro("__ELF__"); 714 Builder.defineMacro("__native_client__"); 715 } 716 717 public: 718 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 719 this->LongAlign = 32; 720 this->LongWidth = 32; 721 this->PointerAlign = 32; 722 this->PointerWidth = 32; 723 this->IntMaxType = TargetInfo::SignedLongLong; 724 this->Int64Type = TargetInfo::SignedLongLong; 725 this->DoubleAlign = 64; 726 this->LongDoubleWidth = 64; 727 this->LongDoubleAlign = 64; 728 this->LongLongWidth = 64; 729 this->LongLongAlign = 64; 730 this->SizeType = TargetInfo::UnsignedInt; 731 this->PtrDiffType = TargetInfo::SignedInt; 732 this->IntPtrType = TargetInfo::SignedInt; 733 // RegParmMax is inherited from the underlying architecture 734 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 735 if (Triple.getArch() == llvm::Triple::arm) { 736 // Handled in ARM's setABI(). 737 } else if (Triple.getArch() == llvm::Triple::x86) { 738 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 739 } else if (Triple.getArch() == llvm::Triple::x86_64) { 740 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 741 } else if (Triple.getArch() == llvm::Triple::mipsel) { 742 // Handled on mips' setDataLayout. 743 } else { 744 assert(Triple.getArch() == llvm::Triple::le32); 745 this->resetDataLayout("e-p:32:32-i64:64"); 746 } 747 } 748 }; 749 750 // WebAssembly target 751 template <typename Target> 752 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 753 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 754 MacroBuilder &Builder) const final { 755 // A common platform macro. 756 if (Opts.POSIXThreads) 757 Builder.defineMacro("_REENTRANT"); 758 // Follow g++ convention and predefine _GNU_SOURCE for C++. 759 if (Opts.CPlusPlus) 760 Builder.defineMacro("_GNU_SOURCE"); 761 } 762 763 // As an optimization, group static init code together in a section. 764 const char *getStaticInitSectionSpecifier() const final { 765 return ".text.__startup"; 766 } 767 768 public: 769 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 770 : OSTargetInfo<Target>(Triple) { 771 this->MCountName = "__mcount"; 772 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 773 } 774 }; 775 776 //===----------------------------------------------------------------------===// 777 // Specific target implementations. 778 //===----------------------------------------------------------------------===// 779 780 // PPC abstract base class 781 class PPCTargetInfo : public TargetInfo { 782 static const Builtin::Info BuiltinInfo[]; 783 static const char * const GCCRegNames[]; 784 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 785 std::string CPU; 786 787 // Target cpu features. 788 bool HasVSX; 789 bool HasP8Vector; 790 bool HasP8Crypto; 791 bool HasDirectMove; 792 bool HasQPX; 793 bool HasHTM; 794 bool HasBPERMD; 795 bool HasExtDiv; 796 797 protected: 798 std::string ABI; 799 800 public: 801 PPCTargetInfo(const llvm::Triple &Triple) 802 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 803 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 804 HasBPERMD(false), HasExtDiv(false) { 805 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 806 SimdDefaultAlign = 128; 807 LongDoubleWidth = LongDoubleAlign = 128; 808 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 809 } 810 811 /// \brief Flags for architecture specific defines. 812 typedef enum { 813 ArchDefineNone = 0, 814 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 815 ArchDefinePpcgr = 1 << 1, 816 ArchDefinePpcsq = 1 << 2, 817 ArchDefine440 = 1 << 3, 818 ArchDefine603 = 1 << 4, 819 ArchDefine604 = 1 << 5, 820 ArchDefinePwr4 = 1 << 6, 821 ArchDefinePwr5 = 1 << 7, 822 ArchDefinePwr5x = 1 << 8, 823 ArchDefinePwr6 = 1 << 9, 824 ArchDefinePwr6x = 1 << 10, 825 ArchDefinePwr7 = 1 << 11, 826 ArchDefinePwr8 = 1 << 12, 827 ArchDefineA2 = 1 << 13, 828 ArchDefineA2q = 1 << 14 829 } ArchDefineTypes; 830 831 // Note: GCC recognizes the following additional cpus: 832 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 833 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 834 // titan, rs64. 835 bool setCPU(const std::string &Name) override { 836 bool CPUKnown = llvm::StringSwitch<bool>(Name) 837 .Case("generic", true) 838 .Case("440", true) 839 .Case("450", true) 840 .Case("601", true) 841 .Case("602", true) 842 .Case("603", true) 843 .Case("603e", true) 844 .Case("603ev", true) 845 .Case("604", true) 846 .Case("604e", true) 847 .Case("620", true) 848 .Case("630", true) 849 .Case("g3", true) 850 .Case("7400", true) 851 .Case("g4", true) 852 .Case("7450", true) 853 .Case("g4+", true) 854 .Case("750", true) 855 .Case("970", true) 856 .Case("g5", true) 857 .Case("a2", true) 858 .Case("a2q", true) 859 .Case("e500mc", true) 860 .Case("e5500", true) 861 .Case("power3", true) 862 .Case("pwr3", true) 863 .Case("power4", true) 864 .Case("pwr4", true) 865 .Case("power5", true) 866 .Case("pwr5", true) 867 .Case("power5x", true) 868 .Case("pwr5x", true) 869 .Case("power6", true) 870 .Case("pwr6", true) 871 .Case("power6x", true) 872 .Case("pwr6x", true) 873 .Case("power7", true) 874 .Case("pwr7", true) 875 .Case("power8", true) 876 .Case("pwr8", true) 877 .Case("powerpc", true) 878 .Case("ppc", true) 879 .Case("powerpc64", true) 880 .Case("ppc64", true) 881 .Case("powerpc64le", true) 882 .Case("ppc64le", true) 883 .Default(false); 884 885 if (CPUKnown) 886 CPU = Name; 887 888 return CPUKnown; 889 } 890 891 892 StringRef getABI() const override { return ABI; } 893 894 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 895 return llvm::makeArrayRef(BuiltinInfo, 896 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 897 } 898 899 bool isCLZForZeroUndef() const override { return false; } 900 901 void getTargetDefines(const LangOptions &Opts, 902 MacroBuilder &Builder) const override; 903 904 bool 905 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 906 StringRef CPU, 907 const std::vector<std::string> &FeaturesVec) const override; 908 909 bool handleTargetFeatures(std::vector<std::string> &Features, 910 DiagnosticsEngine &Diags) override; 911 bool hasFeature(StringRef Feature) const override; 912 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 913 bool Enabled) const override; 914 915 ArrayRef<const char *> getGCCRegNames() const override; 916 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 917 bool validateAsmConstraint(const char *&Name, 918 TargetInfo::ConstraintInfo &Info) const override { 919 switch (*Name) { 920 default: return false; 921 case 'O': // Zero 922 break; 923 case 'b': // Base register 924 case 'f': // Floating point register 925 Info.setAllowsRegister(); 926 break; 927 // FIXME: The following are added to allow parsing. 928 // I just took a guess at what the actions should be. 929 // Also, is more specific checking needed? I.e. specific registers? 930 case 'd': // Floating point register (containing 64-bit value) 931 case 'v': // Altivec vector register 932 Info.setAllowsRegister(); 933 break; 934 case 'w': 935 switch (Name[1]) { 936 case 'd':// VSX vector register to hold vector double data 937 case 'f':// VSX vector register to hold vector float data 938 case 's':// VSX vector register to hold scalar float data 939 case 'a':// Any VSX register 940 case 'c':// An individual CR bit 941 break; 942 default: 943 return false; 944 } 945 Info.setAllowsRegister(); 946 Name++; // Skip over 'w'. 947 break; 948 case 'h': // `MQ', `CTR', or `LINK' register 949 case 'q': // `MQ' register 950 case 'c': // `CTR' register 951 case 'l': // `LINK' register 952 case 'x': // `CR' register (condition register) number 0 953 case 'y': // `CR' register (condition register) 954 case 'z': // `XER[CA]' carry bit (part of the XER register) 955 Info.setAllowsRegister(); 956 break; 957 case 'I': // Signed 16-bit constant 958 case 'J': // Unsigned 16-bit constant shifted left 16 bits 959 // (use `L' instead for SImode constants) 960 case 'K': // Unsigned 16-bit constant 961 case 'L': // Signed 16-bit constant shifted left 16 bits 962 case 'M': // Constant larger than 31 963 case 'N': // Exact power of 2 964 case 'P': // Constant whose negation is a signed 16-bit constant 965 case 'G': // Floating point constant that can be loaded into a 966 // register with one instruction per word 967 case 'H': // Integer/Floating point constant that can be loaded 968 // into a register using three instructions 969 break; 970 case 'm': // Memory operand. Note that on PowerPC targets, m can 971 // include addresses that update the base register. It 972 // is therefore only safe to use `m' in an asm statement 973 // if that asm statement accesses the operand exactly once. 974 // The asm statement must also use `%U<opno>' as a 975 // placeholder for the "update" flag in the corresponding 976 // load or store instruction. For example: 977 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 978 // is correct but: 979 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 980 // is not. Use es rather than m if you don't want the base 981 // register to be updated. 982 case 'e': 983 if (Name[1] != 's') 984 return false; 985 // es: A "stable" memory operand; that is, one which does not 986 // include any automodification of the base register. Unlike 987 // `m', this constraint can be used in asm statements that 988 // might access the operand several times, or that might not 989 // access it at all. 990 Info.setAllowsMemory(); 991 Name++; // Skip over 'e'. 992 break; 993 case 'Q': // Memory operand that is an offset from a register (it is 994 // usually better to use `m' or `es' in asm statements) 995 case 'Z': // Memory operand that is an indexed or indirect from a 996 // register (it is usually better to use `m' or `es' in 997 // asm statements) 998 Info.setAllowsMemory(); 999 Info.setAllowsRegister(); 1000 break; 1001 case 'R': // AIX TOC entry 1002 case 'a': // Address operand that is an indexed or indirect from a 1003 // register (`p' is preferable for asm statements) 1004 case 'S': // Constant suitable as a 64-bit mask operand 1005 case 'T': // Constant suitable as a 32-bit mask operand 1006 case 'U': // System V Release 4 small data area reference 1007 case 't': // AND masks that can be performed by two rldic{l, r} 1008 // instructions 1009 case 'W': // Vector constant that does not require memory 1010 case 'j': // Vector constant that is all zeros. 1011 break; 1012 // End FIXME. 1013 } 1014 return true; 1015 } 1016 std::string convertConstraint(const char *&Constraint) const override { 1017 std::string R; 1018 switch (*Constraint) { 1019 case 'e': 1020 case 'w': 1021 // Two-character constraint; add "^" hint for later parsing. 1022 R = std::string("^") + std::string(Constraint, 2); 1023 Constraint++; 1024 break; 1025 default: 1026 return TargetInfo::convertConstraint(Constraint); 1027 } 1028 return R; 1029 } 1030 const char *getClobbers() const override { 1031 return ""; 1032 } 1033 int getEHDataRegisterNumber(unsigned RegNo) const override { 1034 if (RegNo == 0) return 3; 1035 if (RegNo == 1) return 4; 1036 return -1; 1037 } 1038 1039 bool hasSjLjLowering() const override { 1040 return true; 1041 } 1042 1043 bool useFloat128ManglingForLongDouble() const override { 1044 return LongDoubleWidth == 128 && 1045 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1046 getTriple().isOSBinFormatELF(); 1047 } 1048 }; 1049 1050 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1051 #define BUILTIN(ID, TYPE, ATTRS) \ 1052 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1053 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1054 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1055 #include "clang/Basic/BuiltinsPPC.def" 1056 }; 1057 1058 /// handleTargetFeatures - Perform initialization based on the user 1059 /// configured set of features. 1060 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1061 DiagnosticsEngine &Diags) { 1062 for (const auto &Feature : Features) { 1063 if (Feature == "+vsx") { 1064 HasVSX = true; 1065 } else if (Feature == "+bpermd") { 1066 HasBPERMD = true; 1067 } else if (Feature == "+extdiv") { 1068 HasExtDiv = true; 1069 } else if (Feature == "+power8-vector") { 1070 HasP8Vector = true; 1071 } else if (Feature == "+crypto") { 1072 HasP8Crypto = true; 1073 } else if (Feature == "+direct-move") { 1074 HasDirectMove = true; 1075 } else if (Feature == "+qpx") { 1076 HasQPX = true; 1077 } else if (Feature == "+htm") { 1078 HasHTM = true; 1079 } 1080 // TODO: Finish this list and add an assert that we've handled them 1081 // all. 1082 } 1083 1084 return true; 1085 } 1086 1087 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1088 /// #defines that are not tied to a specific subtarget. 1089 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1090 MacroBuilder &Builder) const { 1091 // Target identification. 1092 Builder.defineMacro("__ppc__"); 1093 Builder.defineMacro("__PPC__"); 1094 Builder.defineMacro("_ARCH_PPC"); 1095 Builder.defineMacro("__powerpc__"); 1096 Builder.defineMacro("__POWERPC__"); 1097 if (PointerWidth == 64) { 1098 Builder.defineMacro("_ARCH_PPC64"); 1099 Builder.defineMacro("__powerpc64__"); 1100 Builder.defineMacro("__ppc64__"); 1101 Builder.defineMacro("__PPC64__"); 1102 } 1103 1104 // Target properties. 1105 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1106 Builder.defineMacro("_LITTLE_ENDIAN"); 1107 } else { 1108 if (getTriple().getOS() != llvm::Triple::NetBSD && 1109 getTriple().getOS() != llvm::Triple::OpenBSD) 1110 Builder.defineMacro("_BIG_ENDIAN"); 1111 } 1112 1113 // ABI options. 1114 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1115 Builder.defineMacro("_CALL_ELF", "1"); 1116 if (ABI == "elfv2") 1117 Builder.defineMacro("_CALL_ELF", "2"); 1118 1119 // Subtarget options. 1120 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1121 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1122 1123 // FIXME: Should be controlled by command line option. 1124 if (LongDoubleWidth == 128) 1125 Builder.defineMacro("__LONG_DOUBLE_128__"); 1126 1127 if (Opts.AltiVec) { 1128 Builder.defineMacro("__VEC__", "10206"); 1129 Builder.defineMacro("__ALTIVEC__"); 1130 } 1131 1132 // CPU identification. 1133 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1134 .Case("440", ArchDefineName) 1135 .Case("450", ArchDefineName | ArchDefine440) 1136 .Case("601", ArchDefineName) 1137 .Case("602", ArchDefineName | ArchDefinePpcgr) 1138 .Case("603", ArchDefineName | ArchDefinePpcgr) 1139 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1140 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1141 .Case("604", ArchDefineName | ArchDefinePpcgr) 1142 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1143 .Case("620", ArchDefineName | ArchDefinePpcgr) 1144 .Case("630", ArchDefineName | ArchDefinePpcgr) 1145 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1146 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1147 .Case("750", ArchDefineName | ArchDefinePpcgr) 1148 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1149 | ArchDefinePpcsq) 1150 .Case("a2", ArchDefineA2) 1151 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1152 .Case("pwr3", ArchDefinePpcgr) 1153 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1154 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1155 | ArchDefinePpcsq) 1156 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1157 | ArchDefinePpcgr | ArchDefinePpcsq) 1158 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1159 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1160 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1161 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1162 | ArchDefinePpcsq) 1163 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1164 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1165 | ArchDefinePpcgr | ArchDefinePpcsq) 1166 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1167 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1168 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1169 .Case("power3", ArchDefinePpcgr) 1170 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1171 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1172 | ArchDefinePpcsq) 1173 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1174 | ArchDefinePpcgr | ArchDefinePpcsq) 1175 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1176 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1177 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1178 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1179 | ArchDefinePpcsq) 1180 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1181 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1182 | ArchDefinePpcgr | ArchDefinePpcsq) 1183 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1184 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1185 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1186 .Default(ArchDefineNone); 1187 1188 if (defs & ArchDefineName) 1189 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1190 if (defs & ArchDefinePpcgr) 1191 Builder.defineMacro("_ARCH_PPCGR"); 1192 if (defs & ArchDefinePpcsq) 1193 Builder.defineMacro("_ARCH_PPCSQ"); 1194 if (defs & ArchDefine440) 1195 Builder.defineMacro("_ARCH_440"); 1196 if (defs & ArchDefine603) 1197 Builder.defineMacro("_ARCH_603"); 1198 if (defs & ArchDefine604) 1199 Builder.defineMacro("_ARCH_604"); 1200 if (defs & ArchDefinePwr4) 1201 Builder.defineMacro("_ARCH_PWR4"); 1202 if (defs & ArchDefinePwr5) 1203 Builder.defineMacro("_ARCH_PWR5"); 1204 if (defs & ArchDefinePwr5x) 1205 Builder.defineMacro("_ARCH_PWR5X"); 1206 if (defs & ArchDefinePwr6) 1207 Builder.defineMacro("_ARCH_PWR6"); 1208 if (defs & ArchDefinePwr6x) 1209 Builder.defineMacro("_ARCH_PWR6X"); 1210 if (defs & ArchDefinePwr7) 1211 Builder.defineMacro("_ARCH_PWR7"); 1212 if (defs & ArchDefinePwr8) 1213 Builder.defineMacro("_ARCH_PWR8"); 1214 if (defs & ArchDefineA2) 1215 Builder.defineMacro("_ARCH_A2"); 1216 if (defs & ArchDefineA2q) { 1217 Builder.defineMacro("_ARCH_A2Q"); 1218 Builder.defineMacro("_ARCH_QP"); 1219 } 1220 1221 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1222 Builder.defineMacro("__bg__"); 1223 Builder.defineMacro("__THW_BLUEGENE__"); 1224 Builder.defineMacro("__bgq__"); 1225 Builder.defineMacro("__TOS_BGQ__"); 1226 } 1227 1228 if (HasVSX) 1229 Builder.defineMacro("__VSX__"); 1230 if (HasP8Vector) 1231 Builder.defineMacro("__POWER8_VECTOR__"); 1232 if (HasP8Crypto) 1233 Builder.defineMacro("__CRYPTO__"); 1234 if (HasHTM) 1235 Builder.defineMacro("__HTM__"); 1236 1237 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1238 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1239 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1240 if (PointerWidth == 64) 1241 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1242 1243 // FIXME: The following are not yet generated here by Clang, but are 1244 // generated by GCC: 1245 // 1246 // _SOFT_FLOAT_ 1247 // __RECIP_PRECISION__ 1248 // __APPLE_ALTIVEC__ 1249 // __RECIP__ 1250 // __RECIPF__ 1251 // __RSQRTE__ 1252 // __RSQRTEF__ 1253 // _SOFT_DOUBLE_ 1254 // __NO_LWSYNC__ 1255 // __HAVE_BSWAP__ 1256 // __LONGDOUBLE128 1257 // __CMODEL_MEDIUM__ 1258 // __CMODEL_LARGE__ 1259 // _CALL_SYSV 1260 // _CALL_DARWIN 1261 // __NO_FPRS__ 1262 } 1263 1264 // Handle explicit options being passed to the compiler here: if we've 1265 // explicitly turned off vsx and turned on power8-vector or direct-move then 1266 // go ahead and error since the customer has expressed a somewhat incompatible 1267 // set of options. 1268 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1269 const std::vector<std::string> &FeaturesVec) { 1270 1271 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1272 FeaturesVec.end()) { 1273 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1274 FeaturesVec.end()) { 1275 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1276 << "-mno-vsx"; 1277 return false; 1278 } 1279 1280 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1281 FeaturesVec.end()) { 1282 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1283 << "-mno-vsx"; 1284 return false; 1285 } 1286 } 1287 1288 return true; 1289 } 1290 1291 bool PPCTargetInfo::initFeatureMap( 1292 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1293 const std::vector<std::string> &FeaturesVec) const { 1294 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1295 .Case("7400", true) 1296 .Case("g4", true) 1297 .Case("7450", true) 1298 .Case("g4+", true) 1299 .Case("970", true) 1300 .Case("g5", true) 1301 .Case("pwr6", true) 1302 .Case("pwr7", true) 1303 .Case("pwr8", true) 1304 .Case("ppc64", true) 1305 .Case("ppc64le", true) 1306 .Default(false); 1307 1308 Features["qpx"] = (CPU == "a2q"); 1309 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1310 .Case("ppc64le", true) 1311 .Case("pwr8", true) 1312 .Default(false); 1313 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1314 .Case("ppc64le", true) 1315 .Case("pwr8", true) 1316 .Default(false); 1317 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1318 .Case("ppc64le", true) 1319 .Case("pwr8", true) 1320 .Case("pwr7", true) 1321 .Default(false); 1322 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1323 .Case("ppc64le", true) 1324 .Case("pwr8", true) 1325 .Case("pwr7", true) 1326 .Default(false); 1327 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1328 .Case("ppc64le", true) 1329 .Case("pwr8", true) 1330 .Default(false); 1331 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1332 .Case("ppc64le", true) 1333 .Case("pwr8", true) 1334 .Case("pwr7", true) 1335 .Default(false); 1336 1337 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1338 return false; 1339 1340 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1341 } 1342 1343 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1344 return llvm::StringSwitch<bool>(Feature) 1345 .Case("powerpc", true) 1346 .Case("vsx", HasVSX) 1347 .Case("power8-vector", HasP8Vector) 1348 .Case("crypto", HasP8Crypto) 1349 .Case("direct-move", HasDirectMove) 1350 .Case("qpx", HasQPX) 1351 .Case("htm", HasHTM) 1352 .Case("bpermd", HasBPERMD) 1353 .Case("extdiv", HasExtDiv) 1354 .Default(false); 1355 } 1356 1357 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1358 StringRef Name, bool Enabled) const { 1359 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1360 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1361 // incompatible options. 1362 if (Enabled) { 1363 if (Name == "vsx") { 1364 Features[Name] = true; 1365 } else if (Name == "direct-move") { 1366 Features[Name] = Features["vsx"] = true; 1367 } else if (Name == "power8-vector") { 1368 Features[Name] = Features["vsx"] = true; 1369 } else { 1370 Features[Name] = true; 1371 } 1372 } else { 1373 if (Name == "vsx") { 1374 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1375 false; 1376 } else { 1377 Features[Name] = false; 1378 } 1379 } 1380 } 1381 1382 const char * const PPCTargetInfo::GCCRegNames[] = { 1383 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1384 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1385 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1386 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1387 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1388 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1389 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1390 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1391 "mq", "lr", "ctr", "ap", 1392 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1393 "xer", 1394 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1395 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1396 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1397 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1398 "vrsave", "vscr", 1399 "spe_acc", "spefscr", 1400 "sfp" 1401 }; 1402 1403 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1404 return llvm::makeArrayRef(GCCRegNames); 1405 } 1406 1407 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1408 // While some of these aliases do map to different registers 1409 // they still share the same register name. 1410 { { "0" }, "r0" }, 1411 { { "1"}, "r1" }, 1412 { { "2" }, "r2" }, 1413 { { "3" }, "r3" }, 1414 { { "4" }, "r4" }, 1415 { { "5" }, "r5" }, 1416 { { "6" }, "r6" }, 1417 { { "7" }, "r7" }, 1418 { { "8" }, "r8" }, 1419 { { "9" }, "r9" }, 1420 { { "10" }, "r10" }, 1421 { { "11" }, "r11" }, 1422 { { "12" }, "r12" }, 1423 { { "13" }, "r13" }, 1424 { { "14" }, "r14" }, 1425 { { "15" }, "r15" }, 1426 { { "16" }, "r16" }, 1427 { { "17" }, "r17" }, 1428 { { "18" }, "r18" }, 1429 { { "19" }, "r19" }, 1430 { { "20" }, "r20" }, 1431 { { "21" }, "r21" }, 1432 { { "22" }, "r22" }, 1433 { { "23" }, "r23" }, 1434 { { "24" }, "r24" }, 1435 { { "25" }, "r25" }, 1436 { { "26" }, "r26" }, 1437 { { "27" }, "r27" }, 1438 { { "28" }, "r28" }, 1439 { { "29" }, "r29" }, 1440 { { "30" }, "r30" }, 1441 { { "31" }, "r31" }, 1442 { { "fr0" }, "f0" }, 1443 { { "fr1" }, "f1" }, 1444 { { "fr2" }, "f2" }, 1445 { { "fr3" }, "f3" }, 1446 { { "fr4" }, "f4" }, 1447 { { "fr5" }, "f5" }, 1448 { { "fr6" }, "f6" }, 1449 { { "fr7" }, "f7" }, 1450 { { "fr8" }, "f8" }, 1451 { { "fr9" }, "f9" }, 1452 { { "fr10" }, "f10" }, 1453 { { "fr11" }, "f11" }, 1454 { { "fr12" }, "f12" }, 1455 { { "fr13" }, "f13" }, 1456 { { "fr14" }, "f14" }, 1457 { { "fr15" }, "f15" }, 1458 { { "fr16" }, "f16" }, 1459 { { "fr17" }, "f17" }, 1460 { { "fr18" }, "f18" }, 1461 { { "fr19" }, "f19" }, 1462 { { "fr20" }, "f20" }, 1463 { { "fr21" }, "f21" }, 1464 { { "fr22" }, "f22" }, 1465 { { "fr23" }, "f23" }, 1466 { { "fr24" }, "f24" }, 1467 { { "fr25" }, "f25" }, 1468 { { "fr26" }, "f26" }, 1469 { { "fr27" }, "f27" }, 1470 { { "fr28" }, "f28" }, 1471 { { "fr29" }, "f29" }, 1472 { { "fr30" }, "f30" }, 1473 { { "fr31" }, "f31" }, 1474 { { "cc" }, "cr0" }, 1475 }; 1476 1477 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1478 return llvm::makeArrayRef(GCCRegAliases); 1479 } 1480 1481 class PPC32TargetInfo : public PPCTargetInfo { 1482 public: 1483 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1484 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1485 1486 switch (getTriple().getOS()) { 1487 case llvm::Triple::Linux: 1488 case llvm::Triple::FreeBSD: 1489 case llvm::Triple::NetBSD: 1490 SizeType = UnsignedInt; 1491 PtrDiffType = SignedInt; 1492 IntPtrType = SignedInt; 1493 break; 1494 default: 1495 break; 1496 } 1497 1498 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1499 LongDoubleWidth = LongDoubleAlign = 64; 1500 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1501 } 1502 1503 // PPC32 supports atomics up to 4 bytes. 1504 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1505 } 1506 1507 BuiltinVaListKind getBuiltinVaListKind() const override { 1508 // This is the ELF definition, and is overridden by the Darwin sub-target 1509 return TargetInfo::PowerABIBuiltinVaList; 1510 } 1511 }; 1512 1513 // Note: ABI differences may eventually require us to have a separate 1514 // TargetInfo for little endian. 1515 class PPC64TargetInfo : public PPCTargetInfo { 1516 public: 1517 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1518 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1519 IntMaxType = SignedLong; 1520 Int64Type = SignedLong; 1521 1522 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1523 resetDataLayout("e-m:e-i64:64-n32:64"); 1524 ABI = "elfv2"; 1525 } else { 1526 resetDataLayout("E-m:e-i64:64-n32:64"); 1527 ABI = "elfv1"; 1528 } 1529 1530 switch (getTriple().getOS()) { 1531 case llvm::Triple::FreeBSD: 1532 LongDoubleWidth = LongDoubleAlign = 64; 1533 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1534 break; 1535 case llvm::Triple::NetBSD: 1536 IntMaxType = SignedLongLong; 1537 Int64Type = SignedLongLong; 1538 break; 1539 default: 1540 break; 1541 } 1542 1543 // PPC64 supports atomics up to 8 bytes. 1544 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1545 } 1546 BuiltinVaListKind getBuiltinVaListKind() const override { 1547 return TargetInfo::CharPtrBuiltinVaList; 1548 } 1549 // PPC64 Linux-specific ABI options. 1550 bool setABI(const std::string &Name) override { 1551 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1552 ABI = Name; 1553 return true; 1554 } 1555 return false; 1556 } 1557 }; 1558 1559 class DarwinPPC32TargetInfo : 1560 public DarwinTargetInfo<PPC32TargetInfo> { 1561 public: 1562 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1563 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1564 HasAlignMac68kSupport = true; 1565 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1566 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1567 LongLongAlign = 32; 1568 SuitableAlign = 128; 1569 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1570 } 1571 BuiltinVaListKind getBuiltinVaListKind() const override { 1572 return TargetInfo::CharPtrBuiltinVaList; 1573 } 1574 }; 1575 1576 class DarwinPPC64TargetInfo : 1577 public DarwinTargetInfo<PPC64TargetInfo> { 1578 public: 1579 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1580 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1581 HasAlignMac68kSupport = true; 1582 SuitableAlign = 128; 1583 resetDataLayout("E-m:o-i64:64-n32:64"); 1584 } 1585 }; 1586 1587 static const unsigned NVPTXAddrSpaceMap[] = { 1588 1, // opencl_global 1589 3, // opencl_local 1590 4, // opencl_constant 1591 // FIXME: generic has to be added to the target 1592 0, // opencl_generic 1593 1, // cuda_device 1594 4, // cuda_constant 1595 3, // cuda_shared 1596 }; 1597 1598 class NVPTXTargetInfo : public TargetInfo { 1599 static const char *const GCCRegNames[]; 1600 static const Builtin::Info BuiltinInfo[]; 1601 1602 // The GPU profiles supported by the NVPTX backend 1603 enum GPUKind { 1604 GK_NONE, 1605 GK_SM20, 1606 GK_SM21, 1607 GK_SM30, 1608 GK_SM35, 1609 GK_SM37, 1610 } GPU; 1611 1612 public: 1613 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1614 BigEndian = false; 1615 TLSSupported = false; 1616 LongWidth = LongAlign = 64; 1617 AddrSpaceMap = &NVPTXAddrSpaceMap; 1618 UseAddrSpaceMapMangling = true; 1619 // Define available target features 1620 // These must be defined in sorted order! 1621 NoAsmVariants = true; 1622 // Set the default GPU to sm20 1623 GPU = GK_SM20; 1624 } 1625 void getTargetDefines(const LangOptions &Opts, 1626 MacroBuilder &Builder) const override { 1627 Builder.defineMacro("__PTX__"); 1628 Builder.defineMacro("__NVPTX__"); 1629 if (Opts.CUDAIsDevice) { 1630 // Set __CUDA_ARCH__ for the GPU specified. 1631 std::string CUDAArchCode; 1632 switch (GPU) { 1633 case GK_SM20: 1634 CUDAArchCode = "200"; 1635 break; 1636 case GK_SM21: 1637 CUDAArchCode = "210"; 1638 break; 1639 case GK_SM30: 1640 CUDAArchCode = "300"; 1641 break; 1642 case GK_SM35: 1643 CUDAArchCode = "350"; 1644 break; 1645 case GK_SM37: 1646 CUDAArchCode = "370"; 1647 break; 1648 default: 1649 llvm_unreachable("Unhandled target CPU"); 1650 } 1651 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1652 } 1653 } 1654 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1655 return llvm::makeArrayRef(BuiltinInfo, 1656 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1657 } 1658 bool hasFeature(StringRef Feature) const override { 1659 return Feature == "ptx" || Feature == "nvptx"; 1660 } 1661 1662 ArrayRef<const char *> getGCCRegNames() const override; 1663 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1664 // No aliases. 1665 return None; 1666 } 1667 bool validateAsmConstraint(const char *&Name, 1668 TargetInfo::ConstraintInfo &Info) const override { 1669 switch (*Name) { 1670 default: 1671 return false; 1672 case 'c': 1673 case 'h': 1674 case 'r': 1675 case 'l': 1676 case 'f': 1677 case 'd': 1678 Info.setAllowsRegister(); 1679 return true; 1680 } 1681 } 1682 const char *getClobbers() const override { 1683 // FIXME: Is this really right? 1684 return ""; 1685 } 1686 BuiltinVaListKind getBuiltinVaListKind() const override { 1687 // FIXME: implement 1688 return TargetInfo::CharPtrBuiltinVaList; 1689 } 1690 bool setCPU(const std::string &Name) override { 1691 GPU = llvm::StringSwitch<GPUKind>(Name) 1692 .Case("sm_20", GK_SM20) 1693 .Case("sm_21", GK_SM21) 1694 .Case("sm_30", GK_SM30) 1695 .Case("sm_35", GK_SM35) 1696 .Case("sm_37", GK_SM37) 1697 .Default(GK_NONE); 1698 1699 return GPU != GK_NONE; 1700 } 1701 }; 1702 1703 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1704 #define BUILTIN(ID, TYPE, ATTRS) \ 1705 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1706 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1707 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1708 #include "clang/Basic/BuiltinsNVPTX.def" 1709 }; 1710 1711 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1712 1713 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1714 return llvm::makeArrayRef(GCCRegNames); 1715 } 1716 1717 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1718 public: 1719 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1720 LongWidth = LongAlign = 32; 1721 PointerWidth = PointerAlign = 32; 1722 SizeType = TargetInfo::UnsignedInt; 1723 PtrDiffType = TargetInfo::SignedInt; 1724 IntPtrType = TargetInfo::SignedInt; 1725 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1726 } 1727 }; 1728 1729 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1730 public: 1731 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1732 PointerWidth = PointerAlign = 64; 1733 SizeType = TargetInfo::UnsignedLong; 1734 PtrDiffType = TargetInfo::SignedLong; 1735 IntPtrType = TargetInfo::SignedLong; 1736 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1737 } 1738 }; 1739 1740 static const unsigned AMDGPUAddrSpaceMap[] = { 1741 1, // opencl_global 1742 3, // opencl_local 1743 2, // opencl_constant 1744 4, // opencl_generic 1745 1, // cuda_device 1746 2, // cuda_constant 1747 3 // cuda_shared 1748 }; 1749 1750 // If you edit the description strings, make sure you update 1751 // getPointerWidthV(). 1752 1753 static const char *const DataLayoutStringR600 = 1754 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1755 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1756 1757 static const char *const DataLayoutStringSI = 1758 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1759 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1760 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1761 1762 class AMDGPUTargetInfo : public TargetInfo { 1763 static const Builtin::Info BuiltinInfo[]; 1764 static const char * const GCCRegNames[]; 1765 1766 /// \brief The GPU profiles supported by the AMDGPU target. 1767 enum GPUKind { 1768 GK_NONE, 1769 GK_R600, 1770 GK_R600_DOUBLE_OPS, 1771 GK_R700, 1772 GK_R700_DOUBLE_OPS, 1773 GK_EVERGREEN, 1774 GK_EVERGREEN_DOUBLE_OPS, 1775 GK_NORTHERN_ISLANDS, 1776 GK_CAYMAN, 1777 GK_SOUTHERN_ISLANDS, 1778 GK_SEA_ISLANDS, 1779 GK_VOLCANIC_ISLANDS 1780 } GPU; 1781 1782 bool hasFP64:1; 1783 bool hasFMAF:1; 1784 bool hasLDEXPF:1; 1785 1786 public: 1787 AMDGPUTargetInfo(const llvm::Triple &Triple) 1788 : TargetInfo(Triple) { 1789 1790 if (Triple.getArch() == llvm::Triple::amdgcn) { 1791 resetDataLayout(DataLayoutStringSI); 1792 GPU = GK_SOUTHERN_ISLANDS; 1793 hasFP64 = true; 1794 hasFMAF = true; 1795 hasLDEXPF = true; 1796 } else { 1797 resetDataLayout(DataLayoutStringR600); 1798 GPU = GK_R600; 1799 hasFP64 = false; 1800 hasFMAF = false; 1801 hasLDEXPF = false; 1802 } 1803 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1804 UseAddrSpaceMapMangling = true; 1805 } 1806 1807 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1808 if (GPU <= GK_CAYMAN) 1809 return 32; 1810 1811 switch(AddrSpace) { 1812 default: 1813 return 64; 1814 case 0: 1815 case 3: 1816 case 5: 1817 return 32; 1818 } 1819 } 1820 1821 const char * getClobbers() const override { 1822 return ""; 1823 } 1824 1825 ArrayRef<const char *> getGCCRegNames() const override; 1826 1827 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1828 return None; 1829 } 1830 1831 bool validateAsmConstraint(const char *&Name, 1832 TargetInfo::ConstraintInfo &Info) const override { 1833 switch (*Name) { 1834 default: break; 1835 case 'v': // vgpr 1836 case 's': // sgpr 1837 Info.setAllowsRegister(); 1838 return true; 1839 } 1840 return false; 1841 } 1842 1843 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1844 return llvm::makeArrayRef(BuiltinInfo, 1845 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1846 } 1847 1848 void getTargetDefines(const LangOptions &Opts, 1849 MacroBuilder &Builder) const override { 1850 if (getTriple().getArch() == llvm::Triple::amdgcn) 1851 Builder.defineMacro("__AMDGCN__"); 1852 else 1853 Builder.defineMacro("__R600__"); 1854 1855 if (hasFMAF) 1856 Builder.defineMacro("__HAS_FMAF__"); 1857 if (hasLDEXPF) 1858 Builder.defineMacro("__HAS_LDEXPF__"); 1859 if (hasFP64 && Opts.OpenCL) 1860 Builder.defineMacro("cl_khr_fp64"); 1861 if (Opts.OpenCL) { 1862 if (GPU >= GK_NORTHERN_ISLANDS) { 1863 Builder.defineMacro("cl_khr_byte_addressable_store"); 1864 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1865 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1866 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1867 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1868 } 1869 } 1870 } 1871 1872 BuiltinVaListKind getBuiltinVaListKind() const override { 1873 return TargetInfo::CharPtrBuiltinVaList; 1874 } 1875 1876 bool setCPU(const std::string &Name) override { 1877 GPU = llvm::StringSwitch<GPUKind>(Name) 1878 .Case("r600" , GK_R600) 1879 .Case("rv610", GK_R600) 1880 .Case("rv620", GK_R600) 1881 .Case("rv630", GK_R600) 1882 .Case("rv635", GK_R600) 1883 .Case("rs780", GK_R600) 1884 .Case("rs880", GK_R600) 1885 .Case("rv670", GK_R600_DOUBLE_OPS) 1886 .Case("rv710", GK_R700) 1887 .Case("rv730", GK_R700) 1888 .Case("rv740", GK_R700_DOUBLE_OPS) 1889 .Case("rv770", GK_R700_DOUBLE_OPS) 1890 .Case("palm", GK_EVERGREEN) 1891 .Case("cedar", GK_EVERGREEN) 1892 .Case("sumo", GK_EVERGREEN) 1893 .Case("sumo2", GK_EVERGREEN) 1894 .Case("redwood", GK_EVERGREEN) 1895 .Case("juniper", GK_EVERGREEN) 1896 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1897 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1898 .Case("barts", GK_NORTHERN_ISLANDS) 1899 .Case("turks", GK_NORTHERN_ISLANDS) 1900 .Case("caicos", GK_NORTHERN_ISLANDS) 1901 .Case("cayman", GK_CAYMAN) 1902 .Case("aruba", GK_CAYMAN) 1903 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1904 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1905 .Case("verde", GK_SOUTHERN_ISLANDS) 1906 .Case("oland", GK_SOUTHERN_ISLANDS) 1907 .Case("hainan", GK_SOUTHERN_ISLANDS) 1908 .Case("bonaire", GK_SEA_ISLANDS) 1909 .Case("kabini", GK_SEA_ISLANDS) 1910 .Case("kaveri", GK_SEA_ISLANDS) 1911 .Case("hawaii", GK_SEA_ISLANDS) 1912 .Case("mullins", GK_SEA_ISLANDS) 1913 .Case("tonga", GK_VOLCANIC_ISLANDS) 1914 .Case("iceland", GK_VOLCANIC_ISLANDS) 1915 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1916 .Case("fiji", GK_VOLCANIC_ISLANDS) 1917 .Case("stoney", GK_VOLCANIC_ISLANDS) 1918 .Default(GK_NONE); 1919 1920 if (GPU == GK_NONE) { 1921 return false; 1922 } 1923 1924 // Set the correct data layout 1925 switch (GPU) { 1926 case GK_NONE: 1927 case GK_R600: 1928 case GK_R700: 1929 case GK_EVERGREEN: 1930 case GK_NORTHERN_ISLANDS: 1931 resetDataLayout(DataLayoutStringR600); 1932 hasFP64 = false; 1933 hasFMAF = false; 1934 hasLDEXPF = false; 1935 break; 1936 case GK_R600_DOUBLE_OPS: 1937 case GK_R700_DOUBLE_OPS: 1938 case GK_EVERGREEN_DOUBLE_OPS: 1939 case GK_CAYMAN: 1940 resetDataLayout(DataLayoutStringR600); 1941 hasFP64 = true; 1942 hasFMAF = true; 1943 hasLDEXPF = false; 1944 break; 1945 case GK_SOUTHERN_ISLANDS: 1946 case GK_SEA_ISLANDS: 1947 case GK_VOLCANIC_ISLANDS: 1948 resetDataLayout(DataLayoutStringSI); 1949 hasFP64 = true; 1950 hasFMAF = true; 1951 hasLDEXPF = true; 1952 break; 1953 } 1954 1955 return true; 1956 } 1957 }; 1958 1959 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1960 #define BUILTIN(ID, TYPE, ATTRS) \ 1961 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1962 #include "clang/Basic/BuiltinsAMDGPU.def" 1963 }; 1964 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1965 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1966 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1967 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1968 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1969 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1970 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1971 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1972 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1973 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1974 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1975 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1976 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1977 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1978 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1979 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1980 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1981 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1982 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1983 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1984 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1985 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1986 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1987 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1988 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1989 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1990 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1991 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1992 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1993 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1994 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1995 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1996 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1997 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1998 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1999 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2000 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2001 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2002 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2003 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2004 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2005 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2006 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2007 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2008 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2009 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2010 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2011 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2012 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2013 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2014 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2015 }; 2016 2017 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2018 return llvm::makeArrayRef(GCCRegNames); 2019 } 2020 2021 // Namespace for x86 abstract base class 2022 const Builtin::Info BuiltinInfo[] = { 2023 #define BUILTIN(ID, TYPE, ATTRS) \ 2024 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2025 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2026 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2027 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2028 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2029 #include "clang/Basic/BuiltinsX86.def" 2030 }; 2031 2032 static const char* const GCCRegNames[] = { 2033 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2034 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2035 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2036 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2037 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2038 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2039 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2040 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2041 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2042 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2043 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2044 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2045 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2046 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2047 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2048 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2049 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2050 }; 2051 2052 const TargetInfo::AddlRegName AddlRegNames[] = { 2053 { { "al", "ah", "eax", "rax" }, 0 }, 2054 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2055 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2056 { { "dl", "dh", "edx", "rdx" }, 1 }, 2057 { { "esi", "rsi" }, 4 }, 2058 { { "edi", "rdi" }, 5 }, 2059 { { "esp", "rsp" }, 7 }, 2060 { { "ebp", "rbp" }, 6 }, 2061 { { "r8d", "r8w", "r8b" }, 38 }, 2062 { { "r9d", "r9w", "r9b" }, 39 }, 2063 { { "r10d", "r10w", "r10b" }, 40 }, 2064 { { "r11d", "r11w", "r11b" }, 41 }, 2065 { { "r12d", "r12w", "r12b" }, 42 }, 2066 { { "r13d", "r13w", "r13b" }, 43 }, 2067 { { "r14d", "r14w", "r14b" }, 44 }, 2068 { { "r15d", "r15w", "r15b" }, 45 }, 2069 }; 2070 2071 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2072 // most of the implementation can be shared. 2073 class X86TargetInfo : public TargetInfo { 2074 enum X86SSEEnum { 2075 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2076 } SSELevel = NoSSE; 2077 enum MMX3DNowEnum { 2078 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2079 } MMX3DNowLevel = NoMMX3DNow; 2080 enum XOPEnum { 2081 NoXOP, 2082 SSE4A, 2083 FMA4, 2084 XOP 2085 } XOPLevel = NoXOP; 2086 2087 bool HasAES = false; 2088 bool HasPCLMUL = false; 2089 bool HasLZCNT = false; 2090 bool HasRDRND = false; 2091 bool HasFSGSBASE = false; 2092 bool HasBMI = false; 2093 bool HasBMI2 = false; 2094 bool HasPOPCNT = false; 2095 bool HasRTM = false; 2096 bool HasPRFCHW = false; 2097 bool HasRDSEED = false; 2098 bool HasADX = false; 2099 bool HasTBM = false; 2100 bool HasFMA = false; 2101 bool HasF16C = false; 2102 bool HasAVX512CD = false; 2103 bool HasAVX512ER = false; 2104 bool HasAVX512PF = false; 2105 bool HasAVX512DQ = false; 2106 bool HasAVX512BW = false; 2107 bool HasAVX512VL = false; 2108 bool HasAVX512VBMI = false; 2109 bool HasAVX512IFMA = false; 2110 bool HasSHA = false; 2111 bool HasMPX = false; 2112 bool HasSGX = false; 2113 bool HasCX16 = false; 2114 bool HasFXSR = false; 2115 bool HasXSAVE = false; 2116 bool HasXSAVEOPT = false; 2117 bool HasXSAVEC = false; 2118 bool HasXSAVES = false; 2119 bool HasPKU = false; 2120 bool HasCLFLUSHOPT = false; 2121 bool HasPCOMMIT = false; 2122 bool HasCLWB = false; 2123 bool HasUMIP = false; 2124 bool HasMOVBE = false; 2125 bool HasPREFETCHWT1 = false; 2126 2127 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2128 /// 2129 /// Each enumeration represents a particular CPU supported by Clang. These 2130 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2131 enum CPUKind { 2132 CK_Generic, 2133 2134 /// \name i386 2135 /// i386-generation processors. 2136 //@{ 2137 CK_i386, 2138 //@} 2139 2140 /// \name i486 2141 /// i486-generation processors. 2142 //@{ 2143 CK_i486, 2144 CK_WinChipC6, 2145 CK_WinChip2, 2146 CK_C3, 2147 //@} 2148 2149 /// \name i586 2150 /// i586-generation processors, P5 microarchitecture based. 2151 //@{ 2152 CK_i586, 2153 CK_Pentium, 2154 CK_PentiumMMX, 2155 //@} 2156 2157 /// \name i686 2158 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2159 //@{ 2160 CK_i686, 2161 CK_PentiumPro, 2162 CK_Pentium2, 2163 CK_Pentium3, 2164 CK_Pentium3M, 2165 CK_PentiumM, 2166 CK_C3_2, 2167 2168 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2169 /// Clang however has some logic to suport this. 2170 // FIXME: Warn, deprecate, and potentially remove this. 2171 CK_Yonah, 2172 //@} 2173 2174 /// \name Netburst 2175 /// Netburst microarchitecture based processors. 2176 //@{ 2177 CK_Pentium4, 2178 CK_Pentium4M, 2179 CK_Prescott, 2180 CK_Nocona, 2181 //@} 2182 2183 /// \name Core 2184 /// Core microarchitecture based processors. 2185 //@{ 2186 CK_Core2, 2187 2188 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2189 /// codename which GCC no longer accepts as an option to -march, but Clang 2190 /// has some logic for recognizing it. 2191 // FIXME: Warn, deprecate, and potentially remove this. 2192 CK_Penryn, 2193 //@} 2194 2195 /// \name Atom 2196 /// Atom processors 2197 //@{ 2198 CK_Bonnell, 2199 CK_Silvermont, 2200 //@} 2201 2202 /// \name Nehalem 2203 /// Nehalem microarchitecture based processors. 2204 CK_Nehalem, 2205 2206 /// \name Westmere 2207 /// Westmere microarchitecture based processors. 2208 CK_Westmere, 2209 2210 /// \name Sandy Bridge 2211 /// Sandy Bridge microarchitecture based processors. 2212 CK_SandyBridge, 2213 2214 /// \name Ivy Bridge 2215 /// Ivy Bridge microarchitecture based processors. 2216 CK_IvyBridge, 2217 2218 /// \name Haswell 2219 /// Haswell microarchitecture based processors. 2220 CK_Haswell, 2221 2222 /// \name Broadwell 2223 /// Broadwell microarchitecture based processors. 2224 CK_Broadwell, 2225 2226 /// \name Skylake Client 2227 /// Skylake client microarchitecture based processors. 2228 CK_SkylakeClient, 2229 2230 /// \name Skylake Server 2231 /// Skylake server microarchitecture based processors. 2232 CK_SkylakeServer, 2233 2234 /// \name Cannonlake Client 2235 /// Cannonlake client microarchitecture based processors. 2236 CK_Cannonlake, 2237 2238 /// \name Knights Landing 2239 /// Knights Landing processor. 2240 CK_KNL, 2241 2242 /// \name Lakemont 2243 /// Lakemont microarchitecture based processors. 2244 CK_Lakemont, 2245 2246 /// \name K6 2247 /// K6 architecture processors. 2248 //@{ 2249 CK_K6, 2250 CK_K6_2, 2251 CK_K6_3, 2252 //@} 2253 2254 /// \name K7 2255 /// K7 architecture processors. 2256 //@{ 2257 CK_Athlon, 2258 CK_AthlonThunderbird, 2259 CK_Athlon4, 2260 CK_AthlonXP, 2261 CK_AthlonMP, 2262 //@} 2263 2264 /// \name K8 2265 /// K8 architecture processors. 2266 //@{ 2267 CK_Athlon64, 2268 CK_Athlon64SSE3, 2269 CK_AthlonFX, 2270 CK_K8, 2271 CK_K8SSE3, 2272 CK_Opteron, 2273 CK_OpteronSSE3, 2274 CK_AMDFAM10, 2275 //@} 2276 2277 /// \name Bobcat 2278 /// Bobcat architecture processors. 2279 //@{ 2280 CK_BTVER1, 2281 CK_BTVER2, 2282 //@} 2283 2284 /// \name Bulldozer 2285 /// Bulldozer architecture processors. 2286 //@{ 2287 CK_BDVER1, 2288 CK_BDVER2, 2289 CK_BDVER3, 2290 CK_BDVER4, 2291 //@} 2292 2293 /// This specification is deprecated and will be removed in the future. 2294 /// Users should prefer \see CK_K8. 2295 // FIXME: Warn on this when the CPU is set to it. 2296 //@{ 2297 CK_x86_64, 2298 //@} 2299 2300 /// \name Geode 2301 /// Geode processors. 2302 //@{ 2303 CK_Geode 2304 //@} 2305 } CPU = CK_Generic; 2306 2307 CPUKind getCPUKind(StringRef CPU) const { 2308 return llvm::StringSwitch<CPUKind>(CPU) 2309 .Case("i386", CK_i386) 2310 .Case("i486", CK_i486) 2311 .Case("winchip-c6", CK_WinChipC6) 2312 .Case("winchip2", CK_WinChip2) 2313 .Case("c3", CK_C3) 2314 .Case("i586", CK_i586) 2315 .Case("pentium", CK_Pentium) 2316 .Case("pentium-mmx", CK_PentiumMMX) 2317 .Case("i686", CK_i686) 2318 .Case("pentiumpro", CK_PentiumPro) 2319 .Case("pentium2", CK_Pentium2) 2320 .Case("pentium3", CK_Pentium3) 2321 .Case("pentium3m", CK_Pentium3M) 2322 .Case("pentium-m", CK_PentiumM) 2323 .Case("c3-2", CK_C3_2) 2324 .Case("yonah", CK_Yonah) 2325 .Case("pentium4", CK_Pentium4) 2326 .Case("pentium4m", CK_Pentium4M) 2327 .Case("prescott", CK_Prescott) 2328 .Case("nocona", CK_Nocona) 2329 .Case("core2", CK_Core2) 2330 .Case("penryn", CK_Penryn) 2331 .Case("bonnell", CK_Bonnell) 2332 .Case("atom", CK_Bonnell) // Legacy name. 2333 .Case("silvermont", CK_Silvermont) 2334 .Case("slm", CK_Silvermont) // Legacy name. 2335 .Case("nehalem", CK_Nehalem) 2336 .Case("corei7", CK_Nehalem) // Legacy name. 2337 .Case("westmere", CK_Westmere) 2338 .Case("sandybridge", CK_SandyBridge) 2339 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2340 .Case("ivybridge", CK_IvyBridge) 2341 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2342 .Case("haswell", CK_Haswell) 2343 .Case("core-avx2", CK_Haswell) // Legacy name. 2344 .Case("broadwell", CK_Broadwell) 2345 .Case("skylake", CK_SkylakeClient) 2346 .Case("skylake-avx512", CK_SkylakeServer) 2347 .Case("skx", CK_SkylakeServer) // Legacy name. 2348 .Case("cannonlake", CK_Cannonlake) 2349 .Case("knl", CK_KNL) 2350 .Case("lakemont", CK_Lakemont) 2351 .Case("k6", CK_K6) 2352 .Case("k6-2", CK_K6_2) 2353 .Case("k6-3", CK_K6_3) 2354 .Case("athlon", CK_Athlon) 2355 .Case("athlon-tbird", CK_AthlonThunderbird) 2356 .Case("athlon-4", CK_Athlon4) 2357 .Case("athlon-xp", CK_AthlonXP) 2358 .Case("athlon-mp", CK_AthlonMP) 2359 .Case("athlon64", CK_Athlon64) 2360 .Case("athlon64-sse3", CK_Athlon64SSE3) 2361 .Case("athlon-fx", CK_AthlonFX) 2362 .Case("k8", CK_K8) 2363 .Case("k8-sse3", CK_K8SSE3) 2364 .Case("opteron", CK_Opteron) 2365 .Case("opteron-sse3", CK_OpteronSSE3) 2366 .Case("barcelona", CK_AMDFAM10) 2367 .Case("amdfam10", CK_AMDFAM10) 2368 .Case("btver1", CK_BTVER1) 2369 .Case("btver2", CK_BTVER2) 2370 .Case("bdver1", CK_BDVER1) 2371 .Case("bdver2", CK_BDVER2) 2372 .Case("bdver3", CK_BDVER3) 2373 .Case("bdver4", CK_BDVER4) 2374 .Case("x86-64", CK_x86_64) 2375 .Case("geode", CK_Geode) 2376 .Default(CK_Generic); 2377 } 2378 2379 enum FPMathKind { 2380 FP_Default, 2381 FP_SSE, 2382 FP_387 2383 } FPMath = FP_Default; 2384 2385 public: 2386 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 2387 BigEndian = false; 2388 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2389 } 2390 unsigned getFloatEvalMethod() const override { 2391 // X87 evaluates with 80 bits "long double" precision. 2392 return SSELevel == NoSSE ? 2 : 0; 2393 } 2394 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2395 return llvm::makeArrayRef(BuiltinInfo, 2396 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2397 } 2398 ArrayRef<const char *> getGCCRegNames() const override { 2399 return llvm::makeArrayRef(GCCRegNames); 2400 } 2401 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2402 return None; 2403 } 2404 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2405 return llvm::makeArrayRef(AddlRegNames); 2406 } 2407 bool validateCpuSupports(StringRef Name) const override; 2408 bool validateAsmConstraint(const char *&Name, 2409 TargetInfo::ConstraintInfo &info) const override; 2410 2411 bool validateGlobalRegisterVariable(StringRef RegName, 2412 unsigned RegSize, 2413 bool &HasSizeMismatch) const override { 2414 // esp and ebp are the only 32-bit registers the x86 backend can currently 2415 // handle. 2416 if (RegName.equals("esp") || RegName.equals("ebp")) { 2417 // Check that the register size is 32-bit. 2418 HasSizeMismatch = RegSize != 32; 2419 return true; 2420 } 2421 2422 return false; 2423 } 2424 2425 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2426 2427 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2428 2429 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2430 2431 std::string convertConstraint(const char *&Constraint) const override; 2432 const char *getClobbers() const override { 2433 return "~{dirflag},~{fpsr},~{flags}"; 2434 } 2435 void getTargetDefines(const LangOptions &Opts, 2436 MacroBuilder &Builder) const override; 2437 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2438 bool Enabled); 2439 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2440 bool Enabled); 2441 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2442 bool Enabled); 2443 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2444 StringRef Name, bool Enabled) const override { 2445 setFeatureEnabledImpl(Features, Name, Enabled); 2446 } 2447 // This exists purely to cut down on the number of virtual calls in 2448 // initFeatureMap which calls this repeatedly. 2449 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2450 StringRef Name, bool Enabled); 2451 bool 2452 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2453 StringRef CPU, 2454 const std::vector<std::string> &FeaturesVec) const override; 2455 bool hasFeature(StringRef Feature) const override; 2456 bool handleTargetFeatures(std::vector<std::string> &Features, 2457 DiagnosticsEngine &Diags) override; 2458 StringRef getABI() const override { 2459 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2460 return "avx512"; 2461 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2462 return "avx"; 2463 if (getTriple().getArch() == llvm::Triple::x86 && 2464 MMX3DNowLevel == NoMMX3DNow) 2465 return "no-mmx"; 2466 return ""; 2467 } 2468 bool setCPU(const std::string &Name) override { 2469 CPU = getCPUKind(Name); 2470 2471 // Perform any per-CPU checks necessary to determine if this CPU is 2472 // acceptable. 2473 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2474 // invalid without explaining *why*. 2475 switch (CPU) { 2476 case CK_Generic: 2477 // No processor selected! 2478 return false; 2479 2480 case CK_i386: 2481 case CK_i486: 2482 case CK_WinChipC6: 2483 case CK_WinChip2: 2484 case CK_C3: 2485 case CK_i586: 2486 case CK_Pentium: 2487 case CK_PentiumMMX: 2488 case CK_i686: 2489 case CK_PentiumPro: 2490 case CK_Pentium2: 2491 case CK_Pentium3: 2492 case CK_Pentium3M: 2493 case CK_PentiumM: 2494 case CK_Yonah: 2495 case CK_C3_2: 2496 case CK_Pentium4: 2497 case CK_Pentium4M: 2498 case CK_Lakemont: 2499 case CK_Prescott: 2500 case CK_K6: 2501 case CK_K6_2: 2502 case CK_K6_3: 2503 case CK_Athlon: 2504 case CK_AthlonThunderbird: 2505 case CK_Athlon4: 2506 case CK_AthlonXP: 2507 case CK_AthlonMP: 2508 case CK_Geode: 2509 // Only accept certain architectures when compiling in 32-bit mode. 2510 if (getTriple().getArch() != llvm::Triple::x86) 2511 return false; 2512 2513 // Fallthrough 2514 case CK_Nocona: 2515 case CK_Core2: 2516 case CK_Penryn: 2517 case CK_Bonnell: 2518 case CK_Silvermont: 2519 case CK_Nehalem: 2520 case CK_Westmere: 2521 case CK_SandyBridge: 2522 case CK_IvyBridge: 2523 case CK_Haswell: 2524 case CK_Broadwell: 2525 case CK_SkylakeClient: 2526 case CK_SkylakeServer: 2527 case CK_Cannonlake: 2528 case CK_KNL: 2529 case CK_Athlon64: 2530 case CK_Athlon64SSE3: 2531 case CK_AthlonFX: 2532 case CK_K8: 2533 case CK_K8SSE3: 2534 case CK_Opteron: 2535 case CK_OpteronSSE3: 2536 case CK_AMDFAM10: 2537 case CK_BTVER1: 2538 case CK_BTVER2: 2539 case CK_BDVER1: 2540 case CK_BDVER2: 2541 case CK_BDVER3: 2542 case CK_BDVER4: 2543 case CK_x86_64: 2544 return true; 2545 } 2546 llvm_unreachable("Unhandled CPU kind"); 2547 } 2548 2549 bool setFPMath(StringRef Name) override; 2550 2551 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2552 // Most of the non-ARM calling conventions are i386 conventions. 2553 switch (CC) { 2554 case CC_X86ThisCall: 2555 case CC_X86FastCall: 2556 case CC_X86StdCall: 2557 case CC_X86VectorCall: 2558 case CC_C: 2559 case CC_Swift: 2560 case CC_X86Pascal: 2561 case CC_IntelOclBicc: 2562 return CCCR_OK; 2563 default: 2564 return CCCR_Warning; 2565 } 2566 } 2567 2568 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2569 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2570 } 2571 2572 bool hasSjLjLowering() const override { 2573 return true; 2574 } 2575 }; 2576 2577 bool X86TargetInfo::setFPMath(StringRef Name) { 2578 if (Name == "387") { 2579 FPMath = FP_387; 2580 return true; 2581 } 2582 if (Name == "sse") { 2583 FPMath = FP_SSE; 2584 return true; 2585 } 2586 return false; 2587 } 2588 2589 bool X86TargetInfo::initFeatureMap( 2590 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2591 const std::vector<std::string> &FeaturesVec) const { 2592 // FIXME: This *really* should not be here. 2593 // X86_64 always has SSE2. 2594 if (getTriple().getArch() == llvm::Triple::x86_64) 2595 setFeatureEnabledImpl(Features, "sse2", true); 2596 2597 const CPUKind Kind = getCPUKind(CPU); 2598 2599 // Enable X87 for all X86 processors but Lakemont. 2600 if (Kind != CK_Lakemont) 2601 setFeatureEnabledImpl(Features, "x87", true); 2602 2603 switch (Kind) { 2604 case CK_Generic: 2605 case CK_i386: 2606 case CK_i486: 2607 case CK_i586: 2608 case CK_Pentium: 2609 case CK_i686: 2610 case CK_PentiumPro: 2611 case CK_Lakemont: 2612 break; 2613 case CK_PentiumMMX: 2614 case CK_Pentium2: 2615 case CK_K6: 2616 case CK_WinChipC6: 2617 setFeatureEnabledImpl(Features, "mmx", true); 2618 break; 2619 case CK_Pentium3: 2620 case CK_Pentium3M: 2621 case CK_C3_2: 2622 setFeatureEnabledImpl(Features, "sse", true); 2623 setFeatureEnabledImpl(Features, "fxsr", true); 2624 break; 2625 case CK_PentiumM: 2626 case CK_Pentium4: 2627 case CK_Pentium4M: 2628 case CK_x86_64: 2629 setFeatureEnabledImpl(Features, "sse2", true); 2630 setFeatureEnabledImpl(Features, "fxsr", true); 2631 break; 2632 case CK_Yonah: 2633 case CK_Prescott: 2634 case CK_Nocona: 2635 setFeatureEnabledImpl(Features, "sse3", true); 2636 setFeatureEnabledImpl(Features, "fxsr", true); 2637 setFeatureEnabledImpl(Features, "cx16", true); 2638 break; 2639 case CK_Core2: 2640 case CK_Bonnell: 2641 setFeatureEnabledImpl(Features, "ssse3", true); 2642 setFeatureEnabledImpl(Features, "fxsr", true); 2643 setFeatureEnabledImpl(Features, "cx16", true); 2644 break; 2645 case CK_Penryn: 2646 setFeatureEnabledImpl(Features, "sse4.1", true); 2647 setFeatureEnabledImpl(Features, "fxsr", true); 2648 setFeatureEnabledImpl(Features, "cx16", true); 2649 break; 2650 case CK_Cannonlake: 2651 setFeatureEnabledImpl(Features, "avx512ifma", true); 2652 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2653 setFeatureEnabledImpl(Features, "sha", true); 2654 setFeatureEnabledImpl(Features, "umip", true); 2655 // FALLTHROUGH 2656 case CK_SkylakeServer: 2657 setFeatureEnabledImpl(Features, "avx512f", true); 2658 setFeatureEnabledImpl(Features, "avx512cd", true); 2659 setFeatureEnabledImpl(Features, "avx512dq", true); 2660 setFeatureEnabledImpl(Features, "avx512bw", true); 2661 setFeatureEnabledImpl(Features, "avx512vl", true); 2662 setFeatureEnabledImpl(Features, "pku", true); 2663 setFeatureEnabledImpl(Features, "pcommit", true); 2664 setFeatureEnabledImpl(Features, "clwb", true); 2665 // FALLTHROUGH 2666 case CK_SkylakeClient: 2667 setFeatureEnabledImpl(Features, "xsavec", true); 2668 setFeatureEnabledImpl(Features, "xsaves", true); 2669 setFeatureEnabledImpl(Features, "mpx", true); 2670 setFeatureEnabledImpl(Features, "sgx", true); 2671 setFeatureEnabledImpl(Features, "clflushopt", true); 2672 // FALLTHROUGH 2673 case CK_Broadwell: 2674 setFeatureEnabledImpl(Features, "rdseed", true); 2675 setFeatureEnabledImpl(Features, "adx", true); 2676 // FALLTHROUGH 2677 case CK_Haswell: 2678 setFeatureEnabledImpl(Features, "avx2", true); 2679 setFeatureEnabledImpl(Features, "lzcnt", true); 2680 setFeatureEnabledImpl(Features, "bmi", true); 2681 setFeatureEnabledImpl(Features, "bmi2", true); 2682 setFeatureEnabledImpl(Features, "rtm", true); 2683 setFeatureEnabledImpl(Features, "fma", true); 2684 setFeatureEnabledImpl(Features, "movbe", true); 2685 // FALLTHROUGH 2686 case CK_IvyBridge: 2687 setFeatureEnabledImpl(Features, "rdrnd", true); 2688 setFeatureEnabledImpl(Features, "f16c", true); 2689 setFeatureEnabledImpl(Features, "fsgsbase", true); 2690 // FALLTHROUGH 2691 case CK_SandyBridge: 2692 setFeatureEnabledImpl(Features, "avx", true); 2693 setFeatureEnabledImpl(Features, "xsave", true); 2694 setFeatureEnabledImpl(Features, "xsaveopt", true); 2695 // FALLTHROUGH 2696 case CK_Westmere: 2697 case CK_Silvermont: 2698 setFeatureEnabledImpl(Features, "aes", true); 2699 setFeatureEnabledImpl(Features, "pclmul", true); 2700 // FALLTHROUGH 2701 case CK_Nehalem: 2702 setFeatureEnabledImpl(Features, "sse4.2", true); 2703 setFeatureEnabledImpl(Features, "fxsr", true); 2704 setFeatureEnabledImpl(Features, "cx16", true); 2705 break; 2706 case CK_KNL: 2707 setFeatureEnabledImpl(Features, "avx512f", true); 2708 setFeatureEnabledImpl(Features, "avx512cd", true); 2709 setFeatureEnabledImpl(Features, "avx512er", true); 2710 setFeatureEnabledImpl(Features, "avx512pf", true); 2711 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2712 setFeatureEnabledImpl(Features, "fxsr", true); 2713 setFeatureEnabledImpl(Features, "rdseed", true); 2714 setFeatureEnabledImpl(Features, "adx", true); 2715 setFeatureEnabledImpl(Features, "lzcnt", true); 2716 setFeatureEnabledImpl(Features, "bmi", true); 2717 setFeatureEnabledImpl(Features, "bmi2", true); 2718 setFeatureEnabledImpl(Features, "rtm", true); 2719 setFeatureEnabledImpl(Features, "fma", true); 2720 setFeatureEnabledImpl(Features, "rdrnd", true); 2721 setFeatureEnabledImpl(Features, "f16c", true); 2722 setFeatureEnabledImpl(Features, "fsgsbase", true); 2723 setFeatureEnabledImpl(Features, "aes", true); 2724 setFeatureEnabledImpl(Features, "pclmul", true); 2725 setFeatureEnabledImpl(Features, "cx16", true); 2726 setFeatureEnabledImpl(Features, "xsaveopt", true); 2727 setFeatureEnabledImpl(Features, "xsave", true); 2728 setFeatureEnabledImpl(Features, "movbe", true); 2729 break; 2730 case CK_K6_2: 2731 case CK_K6_3: 2732 case CK_WinChip2: 2733 case CK_C3: 2734 setFeatureEnabledImpl(Features, "3dnow", true); 2735 break; 2736 case CK_Athlon: 2737 case CK_AthlonThunderbird: 2738 case CK_Geode: 2739 setFeatureEnabledImpl(Features, "3dnowa", true); 2740 break; 2741 case CK_Athlon4: 2742 case CK_AthlonXP: 2743 case CK_AthlonMP: 2744 setFeatureEnabledImpl(Features, "sse", true); 2745 setFeatureEnabledImpl(Features, "3dnowa", true); 2746 setFeatureEnabledImpl(Features, "fxsr", true); 2747 break; 2748 case CK_K8: 2749 case CK_Opteron: 2750 case CK_Athlon64: 2751 case CK_AthlonFX: 2752 setFeatureEnabledImpl(Features, "sse2", true); 2753 setFeatureEnabledImpl(Features, "3dnowa", true); 2754 setFeatureEnabledImpl(Features, "fxsr", true); 2755 break; 2756 case CK_AMDFAM10: 2757 setFeatureEnabledImpl(Features, "sse4a", true); 2758 setFeatureEnabledImpl(Features, "lzcnt", true); 2759 setFeatureEnabledImpl(Features, "popcnt", true); 2760 // FALLTHROUGH 2761 case CK_K8SSE3: 2762 case CK_OpteronSSE3: 2763 case CK_Athlon64SSE3: 2764 setFeatureEnabledImpl(Features, "sse3", true); 2765 setFeatureEnabledImpl(Features, "3dnowa", true); 2766 setFeatureEnabledImpl(Features, "fxsr", true); 2767 break; 2768 case CK_BTVER2: 2769 setFeatureEnabledImpl(Features, "avx", true); 2770 setFeatureEnabledImpl(Features, "aes", true); 2771 setFeatureEnabledImpl(Features, "pclmul", true); 2772 setFeatureEnabledImpl(Features, "bmi", true); 2773 setFeatureEnabledImpl(Features, "f16c", true); 2774 setFeatureEnabledImpl(Features, "xsaveopt", true); 2775 // FALLTHROUGH 2776 case CK_BTVER1: 2777 setFeatureEnabledImpl(Features, "ssse3", true); 2778 setFeatureEnabledImpl(Features, "sse4a", true); 2779 setFeatureEnabledImpl(Features, "lzcnt", true); 2780 setFeatureEnabledImpl(Features, "popcnt", true); 2781 setFeatureEnabledImpl(Features, "prfchw", true); 2782 setFeatureEnabledImpl(Features, "cx16", true); 2783 setFeatureEnabledImpl(Features, "fxsr", true); 2784 break; 2785 case CK_BDVER4: 2786 setFeatureEnabledImpl(Features, "avx2", true); 2787 setFeatureEnabledImpl(Features, "bmi2", true); 2788 // FALLTHROUGH 2789 case CK_BDVER3: 2790 setFeatureEnabledImpl(Features, "fsgsbase", true); 2791 setFeatureEnabledImpl(Features, "xsaveopt", true); 2792 // FALLTHROUGH 2793 case CK_BDVER2: 2794 setFeatureEnabledImpl(Features, "bmi", true); 2795 setFeatureEnabledImpl(Features, "fma", true); 2796 setFeatureEnabledImpl(Features, "f16c", true); 2797 setFeatureEnabledImpl(Features, "tbm", true); 2798 // FALLTHROUGH 2799 case CK_BDVER1: 2800 // xop implies avx, sse4a and fma4. 2801 setFeatureEnabledImpl(Features, "xop", true); 2802 setFeatureEnabledImpl(Features, "lzcnt", true); 2803 setFeatureEnabledImpl(Features, "aes", true); 2804 setFeatureEnabledImpl(Features, "pclmul", true); 2805 setFeatureEnabledImpl(Features, "prfchw", true); 2806 setFeatureEnabledImpl(Features, "cx16", true); 2807 setFeatureEnabledImpl(Features, "fxsr", true); 2808 setFeatureEnabledImpl(Features, "xsave", true); 2809 break; 2810 } 2811 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2812 return false; 2813 2814 // Can't do this earlier because we need to be able to explicitly enable 2815 // or disable these features and the things that they depend upon. 2816 2817 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2818 auto I = Features.find("sse4.2"); 2819 if (I != Features.end() && I->getValue() && 2820 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2821 FeaturesVec.end()) 2822 Features["popcnt"] = true; 2823 2824 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2825 I = Features.find("3dnow"); 2826 if (I != Features.end() && I->getValue() && 2827 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2828 FeaturesVec.end()) 2829 Features["prfchw"] = true; 2830 2831 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2832 // then enable MMX. 2833 I = Features.find("sse"); 2834 if (I != Features.end() && I->getValue() && 2835 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2836 FeaturesVec.end()) 2837 Features["mmx"] = true; 2838 2839 return true; 2840 } 2841 2842 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2843 X86SSEEnum Level, bool Enabled) { 2844 if (Enabled) { 2845 switch (Level) { 2846 case AVX512F: 2847 Features["avx512f"] = true; 2848 case AVX2: 2849 Features["avx2"] = true; 2850 case AVX: 2851 Features["avx"] = true; 2852 Features["xsave"] = true; 2853 case SSE42: 2854 Features["sse4.2"] = true; 2855 case SSE41: 2856 Features["sse4.1"] = true; 2857 case SSSE3: 2858 Features["ssse3"] = true; 2859 case SSE3: 2860 Features["sse3"] = true; 2861 case SSE2: 2862 Features["sse2"] = true; 2863 case SSE1: 2864 Features["sse"] = true; 2865 case NoSSE: 2866 break; 2867 } 2868 return; 2869 } 2870 2871 switch (Level) { 2872 case NoSSE: 2873 case SSE1: 2874 Features["sse"] = false; 2875 case SSE2: 2876 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2877 Features["sha"] = false; 2878 case SSE3: 2879 Features["sse3"] = false; 2880 setXOPLevel(Features, NoXOP, false); 2881 case SSSE3: 2882 Features["ssse3"] = false; 2883 case SSE41: 2884 Features["sse4.1"] = false; 2885 case SSE42: 2886 Features["sse4.2"] = false; 2887 case AVX: 2888 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2889 Features["xsaveopt"] = false; 2890 setXOPLevel(Features, FMA4, false); 2891 case AVX2: 2892 Features["avx2"] = false; 2893 case AVX512F: 2894 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2895 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2896 Features["avx512vl"] = Features["avx512vbmi"] = 2897 Features["avx512ifma"] = false; 2898 } 2899 } 2900 2901 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2902 MMX3DNowEnum Level, bool Enabled) { 2903 if (Enabled) { 2904 switch (Level) { 2905 case AMD3DNowAthlon: 2906 Features["3dnowa"] = true; 2907 case AMD3DNow: 2908 Features["3dnow"] = true; 2909 case MMX: 2910 Features["mmx"] = true; 2911 case NoMMX3DNow: 2912 break; 2913 } 2914 return; 2915 } 2916 2917 switch (Level) { 2918 case NoMMX3DNow: 2919 case MMX: 2920 Features["mmx"] = false; 2921 case AMD3DNow: 2922 Features["3dnow"] = false; 2923 case AMD3DNowAthlon: 2924 Features["3dnowa"] = false; 2925 } 2926 } 2927 2928 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2929 bool Enabled) { 2930 if (Enabled) { 2931 switch (Level) { 2932 case XOP: 2933 Features["xop"] = true; 2934 case FMA4: 2935 Features["fma4"] = true; 2936 setSSELevel(Features, AVX, true); 2937 case SSE4A: 2938 Features["sse4a"] = true; 2939 setSSELevel(Features, SSE3, true); 2940 case NoXOP: 2941 break; 2942 } 2943 return; 2944 } 2945 2946 switch (Level) { 2947 case NoXOP: 2948 case SSE4A: 2949 Features["sse4a"] = false; 2950 case FMA4: 2951 Features["fma4"] = false; 2952 case XOP: 2953 Features["xop"] = false; 2954 } 2955 } 2956 2957 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2958 StringRef Name, bool Enabled) { 2959 // This is a bit of a hack to deal with the sse4 target feature when used 2960 // as part of the target attribute. We handle sse4 correctly everywhere 2961 // else. See below for more information on how we handle the sse4 options. 2962 if (Name != "sse4") 2963 Features[Name] = Enabled; 2964 2965 if (Name == "mmx") { 2966 setMMXLevel(Features, MMX, Enabled); 2967 } else if (Name == "sse") { 2968 setSSELevel(Features, SSE1, Enabled); 2969 } else if (Name == "sse2") { 2970 setSSELevel(Features, SSE2, Enabled); 2971 } else if (Name == "sse3") { 2972 setSSELevel(Features, SSE3, Enabled); 2973 } else if (Name == "ssse3") { 2974 setSSELevel(Features, SSSE3, Enabled); 2975 } else if (Name == "sse4.2") { 2976 setSSELevel(Features, SSE42, Enabled); 2977 } else if (Name == "sse4.1") { 2978 setSSELevel(Features, SSE41, Enabled); 2979 } else if (Name == "3dnow") { 2980 setMMXLevel(Features, AMD3DNow, Enabled); 2981 } else if (Name == "3dnowa") { 2982 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2983 } else if (Name == "aes") { 2984 if (Enabled) 2985 setSSELevel(Features, SSE2, Enabled); 2986 } else if (Name == "pclmul") { 2987 if (Enabled) 2988 setSSELevel(Features, SSE2, Enabled); 2989 } else if (Name == "avx") { 2990 setSSELevel(Features, AVX, Enabled); 2991 } else if (Name == "avx2") { 2992 setSSELevel(Features, AVX2, Enabled); 2993 } else if (Name == "avx512f") { 2994 setSSELevel(Features, AVX512F, Enabled); 2995 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 2996 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 2997 Name == "avx512vbmi" || Name == "avx512ifma") { 2998 if (Enabled) 2999 setSSELevel(Features, AVX512F, Enabled); 3000 } else if (Name == "fma") { 3001 if (Enabled) 3002 setSSELevel(Features, AVX, Enabled); 3003 } else if (Name == "fma4") { 3004 setXOPLevel(Features, FMA4, Enabled); 3005 } else if (Name == "xop") { 3006 setXOPLevel(Features, XOP, Enabled); 3007 } else if (Name == "sse4a") { 3008 setXOPLevel(Features, SSE4A, Enabled); 3009 } else if (Name == "f16c") { 3010 if (Enabled) 3011 setSSELevel(Features, AVX, Enabled); 3012 } else if (Name == "sha") { 3013 if (Enabled) 3014 setSSELevel(Features, SSE2, Enabled); 3015 } else if (Name == "sse4") { 3016 // We can get here via the __target__ attribute since that's not controlled 3017 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3018 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3019 // disabled. 3020 if (Enabled) 3021 setSSELevel(Features, SSE42, Enabled); 3022 else 3023 setSSELevel(Features, SSE41, Enabled); 3024 } else if (Name == "xsave") { 3025 if (!Enabled) 3026 Features["xsaveopt"] = false; 3027 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3028 if (Enabled) 3029 Features["xsave"] = true; 3030 } 3031 } 3032 3033 /// handleTargetFeatures - Perform initialization based on the user 3034 /// configured set of features. 3035 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3036 DiagnosticsEngine &Diags) { 3037 for (const auto &Feature : Features) { 3038 if (Feature[0] != '+') 3039 continue; 3040 3041 if (Feature == "+aes") { 3042 HasAES = true; 3043 } else if (Feature == "+pclmul") { 3044 HasPCLMUL = true; 3045 } else if (Feature == "+lzcnt") { 3046 HasLZCNT = true; 3047 } else if (Feature == "+rdrnd") { 3048 HasRDRND = true; 3049 } else if (Feature == "+fsgsbase") { 3050 HasFSGSBASE = true; 3051 } else if (Feature == "+bmi") { 3052 HasBMI = true; 3053 } else if (Feature == "+bmi2") { 3054 HasBMI2 = true; 3055 } else if (Feature == "+popcnt") { 3056 HasPOPCNT = true; 3057 } else if (Feature == "+rtm") { 3058 HasRTM = true; 3059 } else if (Feature == "+prfchw") { 3060 HasPRFCHW = true; 3061 } else if (Feature == "+rdseed") { 3062 HasRDSEED = true; 3063 } else if (Feature == "+adx") { 3064 HasADX = true; 3065 } else if (Feature == "+tbm") { 3066 HasTBM = true; 3067 } else if (Feature == "+fma") { 3068 HasFMA = true; 3069 } else if (Feature == "+f16c") { 3070 HasF16C = true; 3071 } else if (Feature == "+avx512cd") { 3072 HasAVX512CD = true; 3073 } else if (Feature == "+avx512er") { 3074 HasAVX512ER = true; 3075 } else if (Feature == "+avx512pf") { 3076 HasAVX512PF = true; 3077 } else if (Feature == "+avx512dq") { 3078 HasAVX512DQ = true; 3079 } else if (Feature == "+avx512bw") { 3080 HasAVX512BW = true; 3081 } else if (Feature == "+avx512vl") { 3082 HasAVX512VL = true; 3083 } else if (Feature == "+avx512vbmi") { 3084 HasAVX512VBMI = true; 3085 } else if (Feature == "+avx512ifma") { 3086 HasAVX512IFMA = true; 3087 } else if (Feature == "+sha") { 3088 HasSHA = true; 3089 } else if (Feature == "+mpx") { 3090 HasMPX = true; 3091 } else if (Feature == "+movbe") { 3092 HasMOVBE = true; 3093 } else if (Feature == "+sgx") { 3094 HasSGX = true; 3095 } else if (Feature == "+cx16") { 3096 HasCX16 = true; 3097 } else if (Feature == "+fxsr") { 3098 HasFXSR = true; 3099 } else if (Feature == "+xsave") { 3100 HasXSAVE = true; 3101 } else if (Feature == "+xsaveopt") { 3102 HasXSAVEOPT = true; 3103 } else if (Feature == "+xsavec") { 3104 HasXSAVEC = true; 3105 } else if (Feature == "+xsaves") { 3106 HasXSAVES = true; 3107 } else if (Feature == "+pku") { 3108 HasPKU = true; 3109 } else if (Feature == "+clflushopt") { 3110 HasCLFLUSHOPT = true; 3111 } else if (Feature == "+pcommit") { 3112 HasPCOMMIT = true; 3113 } else if (Feature == "+clwb") { 3114 HasCLWB = true; 3115 } else if (Feature == "+umip") { 3116 HasUMIP = true; 3117 } else if (Feature == "+prefetchwt1") { 3118 HasPREFETCHWT1 = true; 3119 } 3120 3121 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3122 .Case("+avx512f", AVX512F) 3123 .Case("+avx2", AVX2) 3124 .Case("+avx", AVX) 3125 .Case("+sse4.2", SSE42) 3126 .Case("+sse4.1", SSE41) 3127 .Case("+ssse3", SSSE3) 3128 .Case("+sse3", SSE3) 3129 .Case("+sse2", SSE2) 3130 .Case("+sse", SSE1) 3131 .Default(NoSSE); 3132 SSELevel = std::max(SSELevel, Level); 3133 3134 MMX3DNowEnum ThreeDNowLevel = 3135 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3136 .Case("+3dnowa", AMD3DNowAthlon) 3137 .Case("+3dnow", AMD3DNow) 3138 .Case("+mmx", MMX) 3139 .Default(NoMMX3DNow); 3140 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3141 3142 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3143 .Case("+xop", XOP) 3144 .Case("+fma4", FMA4) 3145 .Case("+sse4a", SSE4A) 3146 .Default(NoXOP); 3147 XOPLevel = std::max(XOPLevel, XLevel); 3148 } 3149 3150 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3151 // matches the selected sse level. 3152 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3153 (FPMath == FP_387 && SSELevel >= SSE1)) { 3154 Diags.Report(diag::err_target_unsupported_fpmath) << 3155 (FPMath == FP_SSE ? "sse" : "387"); 3156 return false; 3157 } 3158 3159 SimdDefaultAlign = 3160 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3161 return true; 3162 } 3163 3164 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3165 /// definitions for this particular subtarget. 3166 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3167 MacroBuilder &Builder) const { 3168 // Target identification. 3169 if (getTriple().getArch() == llvm::Triple::x86_64) { 3170 Builder.defineMacro("__amd64__"); 3171 Builder.defineMacro("__amd64"); 3172 Builder.defineMacro("__x86_64"); 3173 Builder.defineMacro("__x86_64__"); 3174 if (getTriple().getArchName() == "x86_64h") { 3175 Builder.defineMacro("__x86_64h"); 3176 Builder.defineMacro("__x86_64h__"); 3177 } 3178 } else { 3179 DefineStd(Builder, "i386", Opts); 3180 } 3181 3182 // Subtarget options. 3183 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3184 // truly should be based on -mtune options. 3185 switch (CPU) { 3186 case CK_Generic: 3187 break; 3188 case CK_i386: 3189 // The rest are coming from the i386 define above. 3190 Builder.defineMacro("__tune_i386__"); 3191 break; 3192 case CK_i486: 3193 case CK_WinChipC6: 3194 case CK_WinChip2: 3195 case CK_C3: 3196 defineCPUMacros(Builder, "i486"); 3197 break; 3198 case CK_PentiumMMX: 3199 Builder.defineMacro("__pentium_mmx__"); 3200 Builder.defineMacro("__tune_pentium_mmx__"); 3201 // Fallthrough 3202 case CK_i586: 3203 case CK_Pentium: 3204 defineCPUMacros(Builder, "i586"); 3205 defineCPUMacros(Builder, "pentium"); 3206 break; 3207 case CK_Pentium3: 3208 case CK_Pentium3M: 3209 case CK_PentiumM: 3210 Builder.defineMacro("__tune_pentium3__"); 3211 // Fallthrough 3212 case CK_Pentium2: 3213 case CK_C3_2: 3214 Builder.defineMacro("__tune_pentium2__"); 3215 // Fallthrough 3216 case CK_PentiumPro: 3217 Builder.defineMacro("__tune_i686__"); 3218 Builder.defineMacro("__tune_pentiumpro__"); 3219 // Fallthrough 3220 case CK_i686: 3221 Builder.defineMacro("__i686"); 3222 Builder.defineMacro("__i686__"); 3223 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3224 Builder.defineMacro("__pentiumpro"); 3225 Builder.defineMacro("__pentiumpro__"); 3226 break; 3227 case CK_Pentium4: 3228 case CK_Pentium4M: 3229 defineCPUMacros(Builder, "pentium4"); 3230 break; 3231 case CK_Yonah: 3232 case CK_Prescott: 3233 case CK_Nocona: 3234 defineCPUMacros(Builder, "nocona"); 3235 break; 3236 case CK_Core2: 3237 case CK_Penryn: 3238 defineCPUMacros(Builder, "core2"); 3239 break; 3240 case CK_Bonnell: 3241 defineCPUMacros(Builder, "atom"); 3242 break; 3243 case CK_Silvermont: 3244 defineCPUMacros(Builder, "slm"); 3245 break; 3246 case CK_Nehalem: 3247 case CK_Westmere: 3248 case CK_SandyBridge: 3249 case CK_IvyBridge: 3250 case CK_Haswell: 3251 case CK_Broadwell: 3252 case CK_SkylakeClient: 3253 // FIXME: Historically, we defined this legacy name, it would be nice to 3254 // remove it at some point. We've never exposed fine-grained names for 3255 // recent primary x86 CPUs, and we should keep it that way. 3256 defineCPUMacros(Builder, "corei7"); 3257 break; 3258 case CK_SkylakeServer: 3259 defineCPUMacros(Builder, "skx"); 3260 break; 3261 case CK_Cannonlake: 3262 break; 3263 case CK_KNL: 3264 defineCPUMacros(Builder, "knl"); 3265 break; 3266 case CK_Lakemont: 3267 Builder.defineMacro("__tune_lakemont__"); 3268 break; 3269 case CK_K6_2: 3270 Builder.defineMacro("__k6_2__"); 3271 Builder.defineMacro("__tune_k6_2__"); 3272 // Fallthrough 3273 case CK_K6_3: 3274 if (CPU != CK_K6_2) { // In case of fallthrough 3275 // FIXME: GCC may be enabling these in cases where some other k6 3276 // architecture is specified but -m3dnow is explicitly provided. The 3277 // exact semantics need to be determined and emulated here. 3278 Builder.defineMacro("__k6_3__"); 3279 Builder.defineMacro("__tune_k6_3__"); 3280 } 3281 // Fallthrough 3282 case CK_K6: 3283 defineCPUMacros(Builder, "k6"); 3284 break; 3285 case CK_Athlon: 3286 case CK_AthlonThunderbird: 3287 case CK_Athlon4: 3288 case CK_AthlonXP: 3289 case CK_AthlonMP: 3290 defineCPUMacros(Builder, "athlon"); 3291 if (SSELevel != NoSSE) { 3292 Builder.defineMacro("__athlon_sse__"); 3293 Builder.defineMacro("__tune_athlon_sse__"); 3294 } 3295 break; 3296 case CK_K8: 3297 case CK_K8SSE3: 3298 case CK_x86_64: 3299 case CK_Opteron: 3300 case CK_OpteronSSE3: 3301 case CK_Athlon64: 3302 case CK_Athlon64SSE3: 3303 case CK_AthlonFX: 3304 defineCPUMacros(Builder, "k8"); 3305 break; 3306 case CK_AMDFAM10: 3307 defineCPUMacros(Builder, "amdfam10"); 3308 break; 3309 case CK_BTVER1: 3310 defineCPUMacros(Builder, "btver1"); 3311 break; 3312 case CK_BTVER2: 3313 defineCPUMacros(Builder, "btver2"); 3314 break; 3315 case CK_BDVER1: 3316 defineCPUMacros(Builder, "bdver1"); 3317 break; 3318 case CK_BDVER2: 3319 defineCPUMacros(Builder, "bdver2"); 3320 break; 3321 case CK_BDVER3: 3322 defineCPUMacros(Builder, "bdver3"); 3323 break; 3324 case CK_BDVER4: 3325 defineCPUMacros(Builder, "bdver4"); 3326 break; 3327 case CK_Geode: 3328 defineCPUMacros(Builder, "geode"); 3329 break; 3330 } 3331 3332 // Target properties. 3333 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3334 3335 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3336 // functions in glibc header files that use FP Stack inline asm which the 3337 // backend can't deal with (PR879). 3338 Builder.defineMacro("__NO_MATH_INLINES"); 3339 3340 if (HasAES) 3341 Builder.defineMacro("__AES__"); 3342 3343 if (HasPCLMUL) 3344 Builder.defineMacro("__PCLMUL__"); 3345 3346 if (HasLZCNT) 3347 Builder.defineMacro("__LZCNT__"); 3348 3349 if (HasRDRND) 3350 Builder.defineMacro("__RDRND__"); 3351 3352 if (HasFSGSBASE) 3353 Builder.defineMacro("__FSGSBASE__"); 3354 3355 if (HasBMI) 3356 Builder.defineMacro("__BMI__"); 3357 3358 if (HasBMI2) 3359 Builder.defineMacro("__BMI2__"); 3360 3361 if (HasPOPCNT) 3362 Builder.defineMacro("__POPCNT__"); 3363 3364 if (HasRTM) 3365 Builder.defineMacro("__RTM__"); 3366 3367 if (HasPRFCHW) 3368 Builder.defineMacro("__PRFCHW__"); 3369 3370 if (HasRDSEED) 3371 Builder.defineMacro("__RDSEED__"); 3372 3373 if (HasADX) 3374 Builder.defineMacro("__ADX__"); 3375 3376 if (HasTBM) 3377 Builder.defineMacro("__TBM__"); 3378 3379 switch (XOPLevel) { 3380 case XOP: 3381 Builder.defineMacro("__XOP__"); 3382 case FMA4: 3383 Builder.defineMacro("__FMA4__"); 3384 case SSE4A: 3385 Builder.defineMacro("__SSE4A__"); 3386 case NoXOP: 3387 break; 3388 } 3389 3390 if (HasFMA) 3391 Builder.defineMacro("__FMA__"); 3392 3393 if (HasF16C) 3394 Builder.defineMacro("__F16C__"); 3395 3396 if (HasAVX512CD) 3397 Builder.defineMacro("__AVX512CD__"); 3398 if (HasAVX512ER) 3399 Builder.defineMacro("__AVX512ER__"); 3400 if (HasAVX512PF) 3401 Builder.defineMacro("__AVX512PF__"); 3402 if (HasAVX512DQ) 3403 Builder.defineMacro("__AVX512DQ__"); 3404 if (HasAVX512BW) 3405 Builder.defineMacro("__AVX512BW__"); 3406 if (HasAVX512VL) 3407 Builder.defineMacro("__AVX512VL__"); 3408 if (HasAVX512VBMI) 3409 Builder.defineMacro("__AVX512VBMI__"); 3410 if (HasAVX512IFMA) 3411 Builder.defineMacro("__AVX512IFMA__"); 3412 3413 if (HasSHA) 3414 Builder.defineMacro("__SHA__"); 3415 3416 if (HasFXSR) 3417 Builder.defineMacro("__FXSR__"); 3418 if (HasXSAVE) 3419 Builder.defineMacro("__XSAVE__"); 3420 if (HasXSAVEOPT) 3421 Builder.defineMacro("__XSAVEOPT__"); 3422 if (HasXSAVEC) 3423 Builder.defineMacro("__XSAVEC__"); 3424 if (HasXSAVES) 3425 Builder.defineMacro("__XSAVES__"); 3426 if (HasPKU) 3427 Builder.defineMacro("__PKU__"); 3428 if (HasCX16) 3429 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3430 3431 // Each case falls through to the previous one here. 3432 switch (SSELevel) { 3433 case AVX512F: 3434 Builder.defineMacro("__AVX512F__"); 3435 case AVX2: 3436 Builder.defineMacro("__AVX2__"); 3437 case AVX: 3438 Builder.defineMacro("__AVX__"); 3439 case SSE42: 3440 Builder.defineMacro("__SSE4_2__"); 3441 case SSE41: 3442 Builder.defineMacro("__SSE4_1__"); 3443 case SSSE3: 3444 Builder.defineMacro("__SSSE3__"); 3445 case SSE3: 3446 Builder.defineMacro("__SSE3__"); 3447 case SSE2: 3448 Builder.defineMacro("__SSE2__"); 3449 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3450 case SSE1: 3451 Builder.defineMacro("__SSE__"); 3452 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3453 case NoSSE: 3454 break; 3455 } 3456 3457 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3458 switch (SSELevel) { 3459 case AVX512F: 3460 case AVX2: 3461 case AVX: 3462 case SSE42: 3463 case SSE41: 3464 case SSSE3: 3465 case SSE3: 3466 case SSE2: 3467 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3468 break; 3469 case SSE1: 3470 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3471 break; 3472 default: 3473 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3474 } 3475 } 3476 3477 // Each case falls through to the previous one here. 3478 switch (MMX3DNowLevel) { 3479 case AMD3DNowAthlon: 3480 Builder.defineMacro("__3dNOW_A__"); 3481 case AMD3DNow: 3482 Builder.defineMacro("__3dNOW__"); 3483 case MMX: 3484 Builder.defineMacro("__MMX__"); 3485 case NoMMX3DNow: 3486 break; 3487 } 3488 3489 if (CPU >= CK_i486) { 3490 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3491 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3492 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3493 } 3494 if (CPU >= CK_i586) 3495 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3496 } 3497 3498 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3499 return llvm::StringSwitch<bool>(Feature) 3500 .Case("aes", HasAES) 3501 .Case("avx", SSELevel >= AVX) 3502 .Case("avx2", SSELevel >= AVX2) 3503 .Case("avx512f", SSELevel >= AVX512F) 3504 .Case("avx512cd", HasAVX512CD) 3505 .Case("avx512er", HasAVX512ER) 3506 .Case("avx512pf", HasAVX512PF) 3507 .Case("avx512dq", HasAVX512DQ) 3508 .Case("avx512bw", HasAVX512BW) 3509 .Case("avx512vl", HasAVX512VL) 3510 .Case("avx512vbmi", HasAVX512VBMI) 3511 .Case("avx512ifma", HasAVX512IFMA) 3512 .Case("bmi", HasBMI) 3513 .Case("bmi2", HasBMI2) 3514 .Case("clflushopt", HasCLFLUSHOPT) 3515 .Case("clwb", HasCLWB) 3516 .Case("cx16", HasCX16) 3517 .Case("f16c", HasF16C) 3518 .Case("fma", HasFMA) 3519 .Case("fma4", XOPLevel >= FMA4) 3520 .Case("fsgsbase", HasFSGSBASE) 3521 .Case("fxsr", HasFXSR) 3522 .Case("lzcnt", HasLZCNT) 3523 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3524 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3525 .Case("mmx", MMX3DNowLevel >= MMX) 3526 .Case("movbe", HasMOVBE) 3527 .Case("mpx", HasMPX) 3528 .Case("pclmul", HasPCLMUL) 3529 .Case("pcommit", HasPCOMMIT) 3530 .Case("pku", HasPKU) 3531 .Case("popcnt", HasPOPCNT) 3532 .Case("prefetchwt1", HasPREFETCHWT1) 3533 .Case("prfchw", HasPRFCHW) 3534 .Case("rdrnd", HasRDRND) 3535 .Case("rdseed", HasRDSEED) 3536 .Case("rtm", HasRTM) 3537 .Case("sgx", HasSGX) 3538 .Case("sha", HasSHA) 3539 .Case("sse", SSELevel >= SSE1) 3540 .Case("sse2", SSELevel >= SSE2) 3541 .Case("sse3", SSELevel >= SSE3) 3542 .Case("ssse3", SSELevel >= SSSE3) 3543 .Case("sse4.1", SSELevel >= SSE41) 3544 .Case("sse4.2", SSELevel >= SSE42) 3545 .Case("sse4a", XOPLevel >= SSE4A) 3546 .Case("tbm", HasTBM) 3547 .Case("umip", HasUMIP) 3548 .Case("x86", true) 3549 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3550 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3551 .Case("xop", XOPLevel >= XOP) 3552 .Case("xsave", HasXSAVE) 3553 .Case("xsavec", HasXSAVEC) 3554 .Case("xsaves", HasXSAVES) 3555 .Case("xsaveopt", HasXSAVEOPT) 3556 .Default(false); 3557 } 3558 3559 // We can't use a generic validation scheme for the features accepted here 3560 // versus subtarget features accepted in the target attribute because the 3561 // bitfield structure that's initialized in the runtime only supports the 3562 // below currently rather than the full range of subtarget features. (See 3563 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3564 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3565 return llvm::StringSwitch<bool>(FeatureStr) 3566 .Case("cmov", true) 3567 .Case("mmx", true) 3568 .Case("popcnt", true) 3569 .Case("sse", true) 3570 .Case("sse2", true) 3571 .Case("sse3", true) 3572 .Case("sse4.1", true) 3573 .Case("sse4.2", true) 3574 .Case("avx", true) 3575 .Case("avx2", true) 3576 .Case("sse4a", true) 3577 .Case("fma4", true) 3578 .Case("xop", true) 3579 .Case("fma", true) 3580 .Case("avx512f", true) 3581 .Case("bmi", true) 3582 .Case("bmi2", true) 3583 .Default(false); 3584 } 3585 3586 bool 3587 X86TargetInfo::validateAsmConstraint(const char *&Name, 3588 TargetInfo::ConstraintInfo &Info) const { 3589 switch (*Name) { 3590 default: return false; 3591 // Constant constraints. 3592 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3593 // instructions. 3594 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3595 // x86_64 instructions. 3596 case 's': 3597 Info.setRequiresImmediate(); 3598 return true; 3599 case 'I': 3600 Info.setRequiresImmediate(0, 31); 3601 return true; 3602 case 'J': 3603 Info.setRequiresImmediate(0, 63); 3604 return true; 3605 case 'K': 3606 Info.setRequiresImmediate(-128, 127); 3607 return true; 3608 case 'L': 3609 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3610 return true; 3611 case 'M': 3612 Info.setRequiresImmediate(0, 3); 3613 return true; 3614 case 'N': 3615 Info.setRequiresImmediate(0, 255); 3616 return true; 3617 case 'O': 3618 Info.setRequiresImmediate(0, 127); 3619 return true; 3620 // Register constraints. 3621 case 'Y': // 'Y' is the first character for several 2-character constraints. 3622 // Shift the pointer to the second character of the constraint. 3623 Name++; 3624 switch (*Name) { 3625 default: 3626 return false; 3627 case '0': // First SSE register. 3628 case 't': // Any SSE register, when SSE2 is enabled. 3629 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3630 case 'm': // Any MMX register, when inter-unit moves enabled. 3631 Info.setAllowsRegister(); 3632 return true; 3633 } 3634 case 'f': // Any x87 floating point stack register. 3635 // Constraint 'f' cannot be used for output operands. 3636 if (Info.ConstraintStr[0] == '=') 3637 return false; 3638 Info.setAllowsRegister(); 3639 return true; 3640 case 'a': // eax. 3641 case 'b': // ebx. 3642 case 'c': // ecx. 3643 case 'd': // edx. 3644 case 'S': // esi. 3645 case 'D': // edi. 3646 case 'A': // edx:eax. 3647 case 't': // Top of floating point stack. 3648 case 'u': // Second from top of floating point stack. 3649 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3650 case 'y': // Any MMX register. 3651 case 'x': // Any SSE register. 3652 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3653 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3654 case 'l': // "Index" registers: any general register that can be used as an 3655 // index in a base+index memory access. 3656 Info.setAllowsRegister(); 3657 return true; 3658 // Floating point constant constraints. 3659 case 'C': // SSE floating point constant. 3660 case 'G': // x87 floating point constant. 3661 return true; 3662 } 3663 } 3664 3665 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3666 unsigned Size) const { 3667 // Strip off constraint modifiers. 3668 while (Constraint[0] == '=' || 3669 Constraint[0] == '+' || 3670 Constraint[0] == '&') 3671 Constraint = Constraint.substr(1); 3672 3673 return validateOperandSize(Constraint, Size); 3674 } 3675 3676 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3677 unsigned Size) const { 3678 return validateOperandSize(Constraint, Size); 3679 } 3680 3681 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3682 unsigned Size) const { 3683 switch (Constraint[0]) { 3684 default: break; 3685 case 'y': 3686 return Size <= 64; 3687 case 'f': 3688 case 't': 3689 case 'u': 3690 return Size <= 128; 3691 case 'x': 3692 if (SSELevel >= AVX512F) 3693 // 512-bit zmm registers can be used if target supports AVX512F. 3694 return Size <= 512U; 3695 else if (SSELevel >= AVX) 3696 // 256-bit ymm registers can be used if target supports AVX. 3697 return Size <= 256U; 3698 return Size <= 128U; 3699 case 'Y': 3700 // 'Y' is the first character for several 2-character constraints. 3701 switch (Constraint[1]) { 3702 default: break; 3703 case 'm': 3704 // 'Ym' is synonymous with 'y'. 3705 return Size <= 64; 3706 case 'i': 3707 case 't': 3708 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3709 if (SSELevel >= AVX512F) 3710 return Size <= 512U; 3711 else if (SSELevel >= AVX) 3712 return Size <= 256U; 3713 return SSELevel >= SSE2 && Size <= 128U; 3714 } 3715 3716 } 3717 3718 return true; 3719 } 3720 3721 std::string 3722 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3723 switch (*Constraint) { 3724 case 'a': return std::string("{ax}"); 3725 case 'b': return std::string("{bx}"); 3726 case 'c': return std::string("{cx}"); 3727 case 'd': return std::string("{dx}"); 3728 case 'S': return std::string("{si}"); 3729 case 'D': return std::string("{di}"); 3730 case 'p': // address 3731 return std::string("im"); 3732 case 't': // top of floating point stack. 3733 return std::string("{st}"); 3734 case 'u': // second from top of floating point stack. 3735 return std::string("{st(1)}"); // second from top of floating point stack. 3736 default: 3737 return std::string(1, *Constraint); 3738 } 3739 } 3740 3741 // X86-32 generic target 3742 class X86_32TargetInfo : public X86TargetInfo { 3743 public: 3744 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3745 DoubleAlign = LongLongAlign = 32; 3746 LongDoubleWidth = 96; 3747 LongDoubleAlign = 32; 3748 SuitableAlign = 128; 3749 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 3750 SizeType = UnsignedInt; 3751 PtrDiffType = SignedInt; 3752 IntPtrType = SignedInt; 3753 RegParmMax = 3; 3754 3755 // Use fpret for all types. 3756 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3757 (1 << TargetInfo::Double) | 3758 (1 << TargetInfo::LongDouble)); 3759 3760 // x86-32 has atomics up to 8 bytes 3761 // FIXME: Check that we actually have cmpxchg8b before setting 3762 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3763 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3764 } 3765 BuiltinVaListKind getBuiltinVaListKind() const override { 3766 return TargetInfo::CharPtrBuiltinVaList; 3767 } 3768 3769 int getEHDataRegisterNumber(unsigned RegNo) const override { 3770 if (RegNo == 0) return 0; 3771 if (RegNo == 1) return 2; 3772 return -1; 3773 } 3774 bool validateOperandSize(StringRef Constraint, 3775 unsigned Size) const override { 3776 switch (Constraint[0]) { 3777 default: break; 3778 case 'R': 3779 case 'q': 3780 case 'Q': 3781 case 'a': 3782 case 'b': 3783 case 'c': 3784 case 'd': 3785 case 'S': 3786 case 'D': 3787 return Size <= 32; 3788 case 'A': 3789 return Size <= 64; 3790 } 3791 3792 return X86TargetInfo::validateOperandSize(Constraint, Size); 3793 } 3794 }; 3795 3796 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3797 public: 3798 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3799 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3800 3801 unsigned getFloatEvalMethod() const override { 3802 unsigned Major, Minor, Micro; 3803 getTriple().getOSVersion(Major, Minor, Micro); 3804 // New NetBSD uses the default rounding mode. 3805 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3806 return X86_32TargetInfo::getFloatEvalMethod(); 3807 // NetBSD before 6.99.26 defaults to "double" rounding. 3808 return 1; 3809 } 3810 }; 3811 3812 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3813 public: 3814 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3815 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3816 SizeType = UnsignedLong; 3817 IntPtrType = SignedLong; 3818 PtrDiffType = SignedLong; 3819 } 3820 }; 3821 3822 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3823 public: 3824 BitrigI386TargetInfo(const llvm::Triple &Triple) 3825 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3826 SizeType = UnsignedLong; 3827 IntPtrType = SignedLong; 3828 PtrDiffType = SignedLong; 3829 } 3830 }; 3831 3832 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3833 public: 3834 DarwinI386TargetInfo(const llvm::Triple &Triple) 3835 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3836 LongDoubleWidth = 128; 3837 LongDoubleAlign = 128; 3838 SuitableAlign = 128; 3839 MaxVectorAlign = 256; 3840 // The watchOS simulator uses the builtin bool type for Objective-C. 3841 llvm::Triple T = llvm::Triple(Triple); 3842 if (T.isWatchOS()) 3843 UseSignedCharForObjCBool = false; 3844 SizeType = UnsignedLong; 3845 IntPtrType = SignedLong; 3846 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 3847 HasAlignMac68kSupport = true; 3848 } 3849 3850 bool handleTargetFeatures(std::vector<std::string> &Features, 3851 DiagnosticsEngine &Diags) override { 3852 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3853 Diags)) 3854 return false; 3855 // We now know the features we have: we can decide how to align vectors. 3856 MaxVectorAlign = 3857 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3858 return true; 3859 } 3860 }; 3861 3862 // x86-32 Windows target 3863 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3864 public: 3865 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3866 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3867 WCharType = UnsignedShort; 3868 DoubleAlign = LongLongAlign = 64; 3869 bool IsWinCOFF = 3870 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3871 resetDataLayout(IsWinCOFF 3872 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3873 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 3874 } 3875 void getTargetDefines(const LangOptions &Opts, 3876 MacroBuilder &Builder) const override { 3877 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3878 } 3879 }; 3880 3881 // x86-32 Windows Visual Studio target 3882 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3883 public: 3884 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3885 : WindowsX86_32TargetInfo(Triple) { 3886 LongDoubleWidth = LongDoubleAlign = 64; 3887 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3888 } 3889 void getTargetDefines(const LangOptions &Opts, 3890 MacroBuilder &Builder) const override { 3891 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3892 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3893 // The value of the following reflects processor type. 3894 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3895 // We lost the original triple, so we use the default. 3896 Builder.defineMacro("_M_IX86", "600"); 3897 } 3898 }; 3899 3900 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3901 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3902 // supports __declspec natively under -fms-extensions, but we define a no-op 3903 // __declspec macro anyway for pre-processor compatibility. 3904 if (Opts.MicrosoftExt) 3905 Builder.defineMacro("__declspec", "__declspec"); 3906 else 3907 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3908 3909 if (!Opts.MicrosoftExt) { 3910 // Provide macros for all the calling convention keywords. Provide both 3911 // single and double underscore prefixed variants. These are available on 3912 // x64 as well as x86, even though they have no effect. 3913 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3914 for (const char *CC : CCs) { 3915 std::string GCCSpelling = "__attribute__((__"; 3916 GCCSpelling += CC; 3917 GCCSpelling += "__))"; 3918 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3919 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3920 } 3921 } 3922 } 3923 3924 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3925 Builder.defineMacro("__MSVCRT__"); 3926 Builder.defineMacro("__MINGW32__"); 3927 addCygMingDefines(Opts, Builder); 3928 } 3929 3930 // x86-32 MinGW target 3931 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3932 public: 3933 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3934 : WindowsX86_32TargetInfo(Triple) {} 3935 void getTargetDefines(const LangOptions &Opts, 3936 MacroBuilder &Builder) const override { 3937 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3938 DefineStd(Builder, "WIN32", Opts); 3939 DefineStd(Builder, "WINNT", Opts); 3940 Builder.defineMacro("_X86_"); 3941 addMinGWDefines(Opts, Builder); 3942 } 3943 }; 3944 3945 // x86-32 Cygwin target 3946 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3947 public: 3948 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3949 : X86_32TargetInfo(Triple) { 3950 WCharType = UnsignedShort; 3951 DoubleAlign = LongLongAlign = 64; 3952 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 3953 } 3954 void getTargetDefines(const LangOptions &Opts, 3955 MacroBuilder &Builder) const override { 3956 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3957 Builder.defineMacro("_X86_"); 3958 Builder.defineMacro("__CYGWIN__"); 3959 Builder.defineMacro("__CYGWIN32__"); 3960 addCygMingDefines(Opts, Builder); 3961 DefineStd(Builder, "unix", Opts); 3962 if (Opts.CPlusPlus) 3963 Builder.defineMacro("_GNU_SOURCE"); 3964 } 3965 }; 3966 3967 // x86-32 Haiku target 3968 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3969 public: 3970 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3971 SizeType = UnsignedLong; 3972 IntPtrType = SignedLong; 3973 PtrDiffType = SignedLong; 3974 ProcessIDType = SignedLong; 3975 this->TLSSupported = false; 3976 } 3977 void getTargetDefines(const LangOptions &Opts, 3978 MacroBuilder &Builder) const override { 3979 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3980 Builder.defineMacro("__INTEL__"); 3981 Builder.defineMacro("__HAIKU__"); 3982 } 3983 }; 3984 3985 // X86-32 MCU target 3986 class MCUX86_32TargetInfo : public X86_32TargetInfo { 3987 public: 3988 MCUX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3989 LongDoubleWidth = 64; 3990 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3991 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 3992 WIntType = UnsignedInt; 3993 } 3994 3995 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3996 // On MCU we support only C calling convention. 3997 return CC == CC_C ? CCCR_OK : CCCR_Warning; 3998 } 3999 4000 void getTargetDefines(const LangOptions &Opts, 4001 MacroBuilder &Builder) const override { 4002 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4003 Builder.defineMacro("__iamcu"); 4004 Builder.defineMacro("__iamcu__"); 4005 } 4006 4007 bool allowsLargerPreferedTypeAlignment() const override { 4008 return false; 4009 } 4010 }; 4011 4012 // RTEMS Target 4013 template<typename Target> 4014 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4015 protected: 4016 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4017 MacroBuilder &Builder) const override { 4018 // RTEMS defines; list based off of gcc output 4019 4020 Builder.defineMacro("__rtems__"); 4021 Builder.defineMacro("__ELF__"); 4022 } 4023 4024 public: 4025 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 4026 switch (Triple.getArch()) { 4027 default: 4028 case llvm::Triple::x86: 4029 // this->MCountName = ".mcount"; 4030 break; 4031 case llvm::Triple::mips: 4032 case llvm::Triple::mipsel: 4033 case llvm::Triple::ppc: 4034 case llvm::Triple::ppc64: 4035 case llvm::Triple::ppc64le: 4036 // this->MCountName = "_mcount"; 4037 break; 4038 case llvm::Triple::arm: 4039 // this->MCountName = "__mcount"; 4040 break; 4041 } 4042 } 4043 }; 4044 4045 // x86-32 RTEMS target 4046 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4047 public: 4048 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 4049 SizeType = UnsignedLong; 4050 IntPtrType = SignedLong; 4051 PtrDiffType = SignedLong; 4052 } 4053 void getTargetDefines(const LangOptions &Opts, 4054 MacroBuilder &Builder) const override { 4055 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4056 Builder.defineMacro("__INTEL__"); 4057 Builder.defineMacro("__rtems__"); 4058 } 4059 }; 4060 4061 // x86-64 generic target 4062 class X86_64TargetInfo : public X86TargetInfo { 4063 public: 4064 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 4065 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4066 bool IsWinCOFF = 4067 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4068 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4069 LongDoubleWidth = 128; 4070 LongDoubleAlign = 128; 4071 LargeArrayMinWidth = 128; 4072 LargeArrayAlign = 128; 4073 SuitableAlign = 128; 4074 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4075 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4076 IntPtrType = IsX32 ? SignedInt : SignedLong; 4077 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4078 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4079 RegParmMax = 6; 4080 4081 // Pointers are 32-bit in x32. 4082 resetDataLayout(IsX32 4083 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4084 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4085 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4086 4087 // Use fpret only for long double. 4088 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4089 4090 // Use fp2ret for _Complex long double. 4091 ComplexLongDoubleUsesFP2Ret = true; 4092 4093 // Make __builtin_ms_va_list available. 4094 HasBuiltinMSVaList = true; 4095 4096 // x86-64 has atomics up to 16 bytes. 4097 MaxAtomicPromoteWidth = 128; 4098 MaxAtomicInlineWidth = 128; 4099 } 4100 BuiltinVaListKind getBuiltinVaListKind() const override { 4101 return TargetInfo::X86_64ABIBuiltinVaList; 4102 } 4103 4104 int getEHDataRegisterNumber(unsigned RegNo) const override { 4105 if (RegNo == 0) return 0; 4106 if (RegNo == 1) return 1; 4107 return -1; 4108 } 4109 4110 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4111 switch (CC) { 4112 case CC_C: 4113 case CC_Swift: 4114 case CC_X86VectorCall: 4115 case CC_IntelOclBicc: 4116 case CC_X86_64Win64: 4117 case CC_PreserveMost: 4118 case CC_PreserveAll: 4119 return CCCR_OK; 4120 default: 4121 return CCCR_Warning; 4122 } 4123 } 4124 4125 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4126 return CC_C; 4127 } 4128 4129 // for x32 we need it here explicitly 4130 bool hasInt128Type() const override { return true; } 4131 unsigned getUnwindWordWidth() const override { return 64; } 4132 unsigned getRegisterWidth() const override { return 64; } 4133 4134 bool validateGlobalRegisterVariable(StringRef RegName, 4135 unsigned RegSize, 4136 bool &HasSizeMismatch) const override { 4137 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4138 // handle. 4139 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4140 // Check that the register size is 64-bit. 4141 HasSizeMismatch = RegSize != 64; 4142 return true; 4143 } 4144 4145 // Check if the register is a 32-bit register the backend can handle. 4146 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4147 HasSizeMismatch); 4148 } 4149 }; 4150 4151 // x86-64 Windows target 4152 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4153 public: 4154 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 4155 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 4156 WCharType = UnsignedShort; 4157 LongWidth = LongAlign = 32; 4158 DoubleAlign = LongLongAlign = 64; 4159 IntMaxType = SignedLongLong; 4160 Int64Type = SignedLongLong; 4161 SizeType = UnsignedLongLong; 4162 PtrDiffType = SignedLongLong; 4163 IntPtrType = SignedLongLong; 4164 } 4165 4166 void getTargetDefines(const LangOptions &Opts, 4167 MacroBuilder &Builder) const override { 4168 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4169 Builder.defineMacro("_WIN64"); 4170 } 4171 4172 BuiltinVaListKind getBuiltinVaListKind() const override { 4173 return TargetInfo::CharPtrBuiltinVaList; 4174 } 4175 4176 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4177 switch (CC) { 4178 case CC_X86StdCall: 4179 case CC_X86ThisCall: 4180 case CC_X86FastCall: 4181 return CCCR_Ignore; 4182 case CC_C: 4183 case CC_X86VectorCall: 4184 case CC_IntelOclBicc: 4185 case CC_X86_64SysV: 4186 return CCCR_OK; 4187 default: 4188 return CCCR_Warning; 4189 } 4190 } 4191 }; 4192 4193 // x86-64 Windows Visual Studio target 4194 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4195 public: 4196 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 4197 : WindowsX86_64TargetInfo(Triple) { 4198 LongDoubleWidth = LongDoubleAlign = 64; 4199 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4200 } 4201 void getTargetDefines(const LangOptions &Opts, 4202 MacroBuilder &Builder) const override { 4203 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4204 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4205 Builder.defineMacro("_M_X64", "100"); 4206 Builder.defineMacro("_M_AMD64", "100"); 4207 } 4208 }; 4209 4210 // x86-64 MinGW target 4211 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4212 public: 4213 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4214 : WindowsX86_64TargetInfo(Triple) { 4215 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4216 // with x86 FP ops. Weird. 4217 LongDoubleWidth = LongDoubleAlign = 128; 4218 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4219 } 4220 4221 void getTargetDefines(const LangOptions &Opts, 4222 MacroBuilder &Builder) const override { 4223 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4224 DefineStd(Builder, "WIN64", Opts); 4225 Builder.defineMacro("__MINGW64__"); 4226 addMinGWDefines(Opts, Builder); 4227 4228 // GCC defines this macro when it is using __gxx_personality_seh0. 4229 if (!Opts.SjLjExceptions) 4230 Builder.defineMacro("__SEH__"); 4231 } 4232 }; 4233 4234 // x86-64 Cygwin target 4235 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4236 public: 4237 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4238 : X86_64TargetInfo(Triple) { 4239 TLSSupported = false; 4240 WCharType = UnsignedShort; 4241 } 4242 void getTargetDefines(const LangOptions &Opts, 4243 MacroBuilder &Builder) const override { 4244 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4245 Builder.defineMacro("__x86_64__"); 4246 Builder.defineMacro("__CYGWIN__"); 4247 Builder.defineMacro("__CYGWIN64__"); 4248 addCygMingDefines(Opts, Builder); 4249 DefineStd(Builder, "unix", Opts); 4250 if (Opts.CPlusPlus) 4251 Builder.defineMacro("_GNU_SOURCE"); 4252 4253 // GCC defines this macro when it is using __gxx_personality_seh0. 4254 if (!Opts.SjLjExceptions) 4255 Builder.defineMacro("__SEH__"); 4256 } 4257 }; 4258 4259 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4260 public: 4261 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4262 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4263 Int64Type = SignedLongLong; 4264 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4265 llvm::Triple T = llvm::Triple(Triple); 4266 if (T.isiOS()) 4267 UseSignedCharForObjCBool = false; 4268 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4269 } 4270 4271 bool handleTargetFeatures(std::vector<std::string> &Features, 4272 DiagnosticsEngine &Diags) override { 4273 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4274 Diags)) 4275 return false; 4276 // We now know the features we have: we can decide how to align vectors. 4277 MaxVectorAlign = 4278 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4279 return true; 4280 } 4281 }; 4282 4283 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4284 public: 4285 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4286 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4287 IntMaxType = SignedLongLong; 4288 Int64Type = SignedLongLong; 4289 } 4290 }; 4291 4292 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4293 public: 4294 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4295 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4296 IntMaxType = SignedLongLong; 4297 Int64Type = SignedLongLong; 4298 } 4299 }; 4300 4301 class ARMTargetInfo : public TargetInfo { 4302 // Possible FPU choices. 4303 enum FPUMode { 4304 VFP2FPU = (1 << 0), 4305 VFP3FPU = (1 << 1), 4306 VFP4FPU = (1 << 2), 4307 NeonFPU = (1 << 3), 4308 FPARMV8 = (1 << 4) 4309 }; 4310 4311 // Possible HWDiv features. 4312 enum HWDivMode { 4313 HWDivThumb = (1 << 0), 4314 HWDivARM = (1 << 1) 4315 }; 4316 4317 static bool FPUModeIsVFP(FPUMode Mode) { 4318 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4319 } 4320 4321 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4322 static const char * const GCCRegNames[]; 4323 4324 std::string ABI, CPU; 4325 4326 StringRef CPUProfile; 4327 StringRef CPUAttr; 4328 4329 enum { 4330 FP_Default, 4331 FP_VFP, 4332 FP_Neon 4333 } FPMath; 4334 4335 unsigned ArchISA; 4336 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4337 unsigned ArchProfile; 4338 unsigned ArchVersion; 4339 4340 unsigned FPU : 5; 4341 4342 unsigned IsAAPCS : 1; 4343 unsigned HWDiv : 2; 4344 4345 // Initialized via features. 4346 unsigned SoftFloat : 1; 4347 unsigned SoftFloatABI : 1; 4348 4349 unsigned CRC : 1; 4350 unsigned Crypto : 1; 4351 unsigned DSP : 1; 4352 unsigned Unaligned : 1; 4353 4354 enum { 4355 LDREX_B = (1 << 0), /// byte (8-bit) 4356 LDREX_H = (1 << 1), /// half (16-bit) 4357 LDREX_W = (1 << 2), /// word (32-bit) 4358 LDREX_D = (1 << 3), /// double (64-bit) 4359 }; 4360 4361 uint32_t LDREX; 4362 4363 // ACLE 6.5.1 Hardware floating point 4364 enum { 4365 HW_FP_HP = (1 << 1), /// half (16-bit) 4366 HW_FP_SP = (1 << 2), /// single (32-bit) 4367 HW_FP_DP = (1 << 3), /// double (64-bit) 4368 }; 4369 uint32_t HW_FP; 4370 4371 static const Builtin::Info BuiltinInfo[]; 4372 4373 void setABIAAPCS() { 4374 IsAAPCS = true; 4375 4376 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4377 const llvm::Triple &T = getTriple(); 4378 4379 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4380 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4381 T.getOS() == llvm::Triple::Bitrig) 4382 SizeType = UnsignedLong; 4383 else 4384 SizeType = UnsignedInt; 4385 4386 switch (T.getOS()) { 4387 case llvm::Triple::NetBSD: 4388 WCharType = SignedInt; 4389 break; 4390 case llvm::Triple::Win32: 4391 WCharType = UnsignedShort; 4392 break; 4393 case llvm::Triple::Linux: 4394 default: 4395 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4396 WCharType = UnsignedInt; 4397 break; 4398 } 4399 4400 UseBitFieldTypeAlignment = true; 4401 4402 ZeroLengthBitfieldBoundary = 0; 4403 4404 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4405 // so set preferred for small types to 32. 4406 if (T.isOSBinFormatMachO()) { 4407 resetDataLayout(BigEndian 4408 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4409 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4410 } else if (T.isOSWindows()) { 4411 assert(!BigEndian && "Windows on ARM does not support big endian"); 4412 resetDataLayout("e" 4413 "-m:w" 4414 "-p:32:32" 4415 "-i64:64" 4416 "-v128:64:128" 4417 "-a:0:32" 4418 "-n32" 4419 "-S64"); 4420 } else if (T.isOSNaCl()) { 4421 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4422 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4423 } else { 4424 resetDataLayout(BigEndian 4425 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4426 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4427 } 4428 4429 // FIXME: Enumerated types are variable width in straight AAPCS. 4430 } 4431 4432 void setABIAPCS(bool IsAAPCS16) { 4433 const llvm::Triple &T = getTriple(); 4434 4435 IsAAPCS = false; 4436 4437 if (IsAAPCS16) 4438 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4439 else 4440 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4441 4442 // size_t is unsigned int on FreeBSD. 4443 if (T.getOS() == llvm::Triple::FreeBSD) 4444 SizeType = UnsignedInt; 4445 else 4446 SizeType = UnsignedLong; 4447 4448 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4449 WCharType = SignedInt; 4450 4451 // Do not respect the alignment of bit-field types when laying out 4452 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4453 UseBitFieldTypeAlignment = false; 4454 4455 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4456 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4457 /// gcc. 4458 ZeroLengthBitfieldBoundary = 32; 4459 4460 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4461 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4462 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4463 } else if (T.isOSBinFormatMachO()) 4464 resetDataLayout( 4465 BigEndian 4466 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4467 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4468 else 4469 resetDataLayout( 4470 BigEndian 4471 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4472 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4473 4474 // FIXME: Override "preferred align" for double and long long. 4475 } 4476 4477 void setArchInfo() { 4478 StringRef ArchName = getTriple().getArchName(); 4479 4480 ArchISA = llvm::ARM::parseArchISA(ArchName); 4481 CPU = llvm::ARM::getDefaultCPU(ArchName); 4482 unsigned AK = llvm::ARM::parseArch(ArchName); 4483 if (AK != llvm::ARM::AK_INVALID) 4484 ArchKind = AK; 4485 setArchInfo(ArchKind); 4486 } 4487 4488 void setArchInfo(unsigned Kind) { 4489 StringRef SubArch; 4490 4491 // cache TargetParser info 4492 ArchKind = Kind; 4493 SubArch = llvm::ARM::getSubArch(ArchKind); 4494 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4495 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4496 4497 // cache CPU related strings 4498 CPUAttr = getCPUAttr(); 4499 CPUProfile = getCPUProfile(); 4500 } 4501 4502 void setAtomic() { 4503 // when triple does not specify a sub arch, 4504 // then we are not using inline atomics 4505 bool ShouldUseInlineAtomic = 4506 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4507 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4508 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4509 if (ArchProfile == llvm::ARM::PK_M) { 4510 MaxAtomicPromoteWidth = 32; 4511 if (ShouldUseInlineAtomic) 4512 MaxAtomicInlineWidth = 32; 4513 } 4514 else { 4515 MaxAtomicPromoteWidth = 64; 4516 if (ShouldUseInlineAtomic) 4517 MaxAtomicInlineWidth = 64; 4518 } 4519 } 4520 4521 bool isThumb() const { 4522 return (ArchISA == llvm::ARM::IK_THUMB); 4523 } 4524 4525 bool supportsThumb() const { 4526 return CPUAttr.count('T') || ArchVersion >= 6; 4527 } 4528 4529 bool supportsThumb2() const { 4530 return CPUAttr.equals("6T2") || 4531 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4532 } 4533 4534 StringRef getCPUAttr() const { 4535 // For most sub-arches, the build attribute CPU name is enough. 4536 // For Cortex variants, it's slightly different. 4537 switch(ArchKind) { 4538 default: 4539 return llvm::ARM::getCPUAttr(ArchKind); 4540 case llvm::ARM::AK_ARMV6M: 4541 return "6M"; 4542 case llvm::ARM::AK_ARMV7S: 4543 return "7S"; 4544 case llvm::ARM::AK_ARMV7A: 4545 return "7A"; 4546 case llvm::ARM::AK_ARMV7R: 4547 return "7R"; 4548 case llvm::ARM::AK_ARMV7M: 4549 return "7M"; 4550 case llvm::ARM::AK_ARMV7EM: 4551 return "7EM"; 4552 case llvm::ARM::AK_ARMV8A: 4553 return "8A"; 4554 case llvm::ARM::AK_ARMV8_1A: 4555 return "8_1A"; 4556 case llvm::ARM::AK_ARMV8_2A: 4557 return "8_2A"; 4558 case llvm::ARM::AK_ARMV8MBaseline: 4559 return "8M_BASE"; 4560 case llvm::ARM::AK_ARMV8MMainline: 4561 return "8M_MAIN"; 4562 } 4563 } 4564 4565 StringRef getCPUProfile() const { 4566 switch(ArchProfile) { 4567 case llvm::ARM::PK_A: 4568 return "A"; 4569 case llvm::ARM::PK_R: 4570 return "R"; 4571 case llvm::ARM::PK_M: 4572 return "M"; 4573 default: 4574 return ""; 4575 } 4576 } 4577 4578 public: 4579 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4580 : TargetInfo(Triple), FPMath(FP_Default), 4581 IsAAPCS(true), LDREX(0), HW_FP(0) { 4582 BigEndian = IsBigEndian; 4583 4584 switch (getTriple().getOS()) { 4585 case llvm::Triple::NetBSD: 4586 PtrDiffType = SignedLong; 4587 break; 4588 default: 4589 PtrDiffType = SignedInt; 4590 break; 4591 } 4592 4593 // Cache arch related info. 4594 setArchInfo(); 4595 4596 // {} in inline assembly are neon specifiers, not assembly variant 4597 // specifiers. 4598 NoAsmVariants = true; 4599 4600 // FIXME: This duplicates code from the driver that sets the -target-abi 4601 // option - this code is used if -target-abi isn't passed and should 4602 // be unified in some way. 4603 if (Triple.isOSBinFormatMachO()) { 4604 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4605 // the frontend matches that. 4606 if (Triple.getEnvironment() == llvm::Triple::EABI || 4607 Triple.getOS() == llvm::Triple::UnknownOS || 4608 StringRef(CPU).startswith("cortex-m")) { 4609 setABI("aapcs"); 4610 } else if (Triple.isWatchABI()) { 4611 setABI("aapcs16"); 4612 } else { 4613 setABI("apcs-gnu"); 4614 } 4615 } else if (Triple.isOSWindows()) { 4616 // FIXME: this is invalid for WindowsCE 4617 setABI("aapcs"); 4618 } else { 4619 // Select the default based on the platform. 4620 switch (Triple.getEnvironment()) { 4621 case llvm::Triple::Android: 4622 case llvm::Triple::GNUEABI: 4623 case llvm::Triple::GNUEABIHF: 4624 setABI("aapcs-linux"); 4625 break; 4626 case llvm::Triple::EABIHF: 4627 case llvm::Triple::EABI: 4628 setABI("aapcs"); 4629 break; 4630 case llvm::Triple::GNU: 4631 setABI("apcs-gnu"); 4632 break; 4633 default: 4634 if (Triple.getOS() == llvm::Triple::NetBSD) 4635 setABI("apcs-gnu"); 4636 else 4637 setABI("aapcs"); 4638 break; 4639 } 4640 } 4641 4642 // ARM targets default to using the ARM C++ ABI. 4643 TheCXXABI.set(TargetCXXABI::GenericARM); 4644 4645 // ARM has atomics up to 8 bytes 4646 setAtomic(); 4647 4648 // Do force alignment of members that follow zero length bitfields. If 4649 // the alignment of the zero-length bitfield is greater than the member 4650 // that follows it, `bar', `bar' will be aligned as the type of the 4651 // zero length bitfield. 4652 UseZeroLengthBitfieldAlignment = true; 4653 } 4654 4655 StringRef getABI() const override { return ABI; } 4656 4657 bool setABI(const std::string &Name) override { 4658 ABI = Name; 4659 4660 // The defaults (above) are for AAPCS, check if we need to change them. 4661 // 4662 // FIXME: We need support for -meabi... we could just mangle it into the 4663 // name. 4664 if (Name == "apcs-gnu" || Name == "aapcs16") { 4665 setABIAPCS(Name == "aapcs16"); 4666 return true; 4667 } 4668 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4669 setABIAAPCS(); 4670 return true; 4671 } 4672 return false; 4673 } 4674 4675 // FIXME: This should be based on Arch attributes, not CPU names. 4676 bool 4677 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4678 StringRef CPU, 4679 const std::vector<std::string> &FeaturesVec) const override { 4680 4681 std::vector<const char*> TargetFeatures; 4682 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4683 4684 // get default FPU features 4685 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4686 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4687 4688 // get default Extension features 4689 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4690 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4691 4692 for (const char *Feature : TargetFeatures) 4693 if (Feature[0] == '+') 4694 Features[Feature+1] = true; 4695 4696 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4697 } 4698 4699 bool handleTargetFeatures(std::vector<std::string> &Features, 4700 DiagnosticsEngine &Diags) override { 4701 FPU = 0; 4702 CRC = 0; 4703 Crypto = 0; 4704 DSP = 0; 4705 Unaligned = 1; 4706 SoftFloat = SoftFloatABI = false; 4707 HWDiv = 0; 4708 4709 // This does not diagnose illegal cases like having both 4710 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4711 uint32_t HW_FP_remove = 0; 4712 for (const auto &Feature : Features) { 4713 if (Feature == "+soft-float") { 4714 SoftFloat = true; 4715 } else if (Feature == "+soft-float-abi") { 4716 SoftFloatABI = true; 4717 } else if (Feature == "+vfp2") { 4718 FPU |= VFP2FPU; 4719 HW_FP |= HW_FP_SP | HW_FP_DP; 4720 } else if (Feature == "+vfp3") { 4721 FPU |= VFP3FPU; 4722 HW_FP |= HW_FP_SP | HW_FP_DP; 4723 } else if (Feature == "+vfp4") { 4724 FPU |= VFP4FPU; 4725 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4726 } else if (Feature == "+fp-armv8") { 4727 FPU |= FPARMV8; 4728 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4729 } else if (Feature == "+neon") { 4730 FPU |= NeonFPU; 4731 HW_FP |= HW_FP_SP | HW_FP_DP; 4732 } else if (Feature == "+hwdiv") { 4733 HWDiv |= HWDivThumb; 4734 } else if (Feature == "+hwdiv-arm") { 4735 HWDiv |= HWDivARM; 4736 } else if (Feature == "+crc") { 4737 CRC = 1; 4738 } else if (Feature == "+crypto") { 4739 Crypto = 1; 4740 } else if (Feature == "+dsp") { 4741 DSP = 1; 4742 } else if (Feature == "+fp-only-sp") { 4743 HW_FP_remove |= HW_FP_DP; 4744 } else if (Feature == "+strict-align") { 4745 Unaligned = 0; 4746 } else if (Feature == "+fp16") { 4747 HW_FP |= HW_FP_HP; 4748 } 4749 } 4750 HW_FP &= ~HW_FP_remove; 4751 4752 switch (ArchVersion) { 4753 case 6: 4754 if (ArchProfile == llvm::ARM::PK_M) 4755 LDREX = 0; 4756 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4757 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4758 else 4759 LDREX = LDREX_W; 4760 break; 4761 case 7: 4762 if (ArchProfile == llvm::ARM::PK_M) 4763 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4764 else 4765 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4766 break; 4767 case 8: 4768 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4769 } 4770 4771 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4772 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4773 return false; 4774 } 4775 4776 if (FPMath == FP_Neon) 4777 Features.push_back("+neonfp"); 4778 else if (FPMath == FP_VFP) 4779 Features.push_back("-neonfp"); 4780 4781 // Remove front-end specific options which the backend handles differently. 4782 auto Feature = 4783 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4784 if (Feature != Features.end()) 4785 Features.erase(Feature); 4786 4787 return true; 4788 } 4789 4790 bool hasFeature(StringRef Feature) const override { 4791 return llvm::StringSwitch<bool>(Feature) 4792 .Case("arm", true) 4793 .Case("aarch32", true) 4794 .Case("softfloat", SoftFloat) 4795 .Case("thumb", isThumb()) 4796 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4797 .Case("hwdiv", HWDiv & HWDivThumb) 4798 .Case("hwdiv-arm", HWDiv & HWDivARM) 4799 .Default(false); 4800 } 4801 4802 bool setCPU(const std::string &Name) override { 4803 if (Name != "generic") 4804 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4805 4806 if (ArchKind == llvm::ARM::AK_INVALID) 4807 return false; 4808 setAtomic(); 4809 CPU = Name; 4810 return true; 4811 } 4812 4813 bool setFPMath(StringRef Name) override; 4814 4815 void getTargetDefines(const LangOptions &Opts, 4816 MacroBuilder &Builder) const override { 4817 // Target identification. 4818 Builder.defineMacro("__arm"); 4819 Builder.defineMacro("__arm__"); 4820 4821 // Target properties. 4822 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4823 4824 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4825 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 4826 if (getTriple().isWatchABI()) 4827 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 4828 4829 if (!CPUAttr.empty()) 4830 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4831 4832 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4833 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4834 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 4835 4836 if (ArchVersion >= 8) { 4837 // ACLE 6.5.7 Crypto Extension 4838 if (Crypto) 4839 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4840 // ACLE 6.5.8 CRC32 Extension 4841 if (CRC) 4842 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4843 // ACLE 6.5.10 Numeric Maximum and Minimum 4844 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4845 // ACLE 6.5.9 Directed Rounding 4846 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4847 } 4848 4849 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4850 // is not defined for the M-profile. 4851 // NOTE that the default profile is assumed to be 'A' 4852 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 4853 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4854 4855 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 4856 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 4857 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 4858 // v7 and v8 architectures excluding v8-M Baseline. 4859 if (supportsThumb2()) 4860 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4861 else if (supportsThumb()) 4862 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4863 4864 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4865 // instruction set such as ARM or Thumb. 4866 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4867 4868 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4869 4870 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4871 if (!CPUProfile.empty()) 4872 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4873 4874 // ACLE 6.4.3 Unaligned access supported in hardware 4875 if (Unaligned) 4876 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4877 4878 // ACLE 6.4.4 LDREX/STREX 4879 if (LDREX) 4880 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4881 4882 // ACLE 6.4.5 CLZ 4883 if (ArchVersion == 5 || 4884 (ArchVersion == 6 && CPUProfile != "M") || 4885 ArchVersion > 6) 4886 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4887 4888 // ACLE 6.5.1 Hardware Floating Point 4889 if (HW_FP) 4890 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4891 4892 // ACLE predefines. 4893 Builder.defineMacro("__ARM_ACLE", "200"); 4894 4895 // FP16 support (we currently only support IEEE format). 4896 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4897 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4898 4899 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4900 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4901 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4902 4903 // Subtarget options. 4904 4905 // FIXME: It's more complicated than this and we don't really support 4906 // interworking. 4907 // Windows on ARM does not "support" interworking 4908 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4909 Builder.defineMacro("__THUMB_INTERWORK__"); 4910 4911 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4912 // Embedded targets on Darwin follow AAPCS, but not EABI. 4913 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4914 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4915 Builder.defineMacro("__ARM_EABI__"); 4916 Builder.defineMacro("__ARM_PCS", "1"); 4917 4918 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4919 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4920 } 4921 4922 if (SoftFloat) 4923 Builder.defineMacro("__SOFTFP__"); 4924 4925 if (CPU == "xscale") 4926 Builder.defineMacro("__XSCALE__"); 4927 4928 if (isThumb()) { 4929 Builder.defineMacro("__THUMBEL__"); 4930 Builder.defineMacro("__thumb__"); 4931 if (supportsThumb2()) 4932 Builder.defineMacro("__thumb2__"); 4933 } 4934 4935 // ACLE 6.4.9 32-bit SIMD instructions 4936 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4937 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4938 4939 // ACLE 6.4.10 Hardware Integer Divide 4940 if (((HWDiv & HWDivThumb) && isThumb()) || 4941 ((HWDiv & HWDivARM) && !isThumb())) { 4942 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4943 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4944 } 4945 4946 // Note, this is always on in gcc, even though it doesn't make sense. 4947 Builder.defineMacro("__APCS_32__"); 4948 4949 if (FPUModeIsVFP((FPUMode) FPU)) { 4950 Builder.defineMacro("__VFP_FP__"); 4951 if (FPU & VFP2FPU) 4952 Builder.defineMacro("__ARM_VFPV2__"); 4953 if (FPU & VFP3FPU) 4954 Builder.defineMacro("__ARM_VFPV3__"); 4955 if (FPU & VFP4FPU) 4956 Builder.defineMacro("__ARM_VFPV4__"); 4957 } 4958 4959 // This only gets set when Neon instructions are actually available, unlike 4960 // the VFP define, hence the soft float and arch check. This is subtly 4961 // different from gcc, we follow the intent which was that it should be set 4962 // when Neon instructions are actually available. 4963 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4964 Builder.defineMacro("__ARM_NEON", "1"); 4965 Builder.defineMacro("__ARM_NEON__"); 4966 // current AArch32 NEON implementations do not support double-precision 4967 // floating-point even when it is present in VFP. 4968 Builder.defineMacro("__ARM_NEON_FP", 4969 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4970 } 4971 4972 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4973 Opts.ShortWChar ? "2" : "4"); 4974 4975 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4976 Opts.ShortEnums ? "1" : "4"); 4977 4978 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 4979 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4980 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4981 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4982 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4983 } 4984 4985 // ACLE 6.4.7 DSP instructions 4986 if (DSP) { 4987 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4988 } 4989 4990 // ACLE 6.4.8 Saturation instructions 4991 bool SAT = false; 4992 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4993 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4994 SAT = true; 4995 } 4996 4997 // ACLE 6.4.6 Q (saturation) flag 4998 if (DSP || SAT) 4999 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5000 5001 if (Opts.UnsafeFPMath) 5002 Builder.defineMacro("__ARM_FP_FAST", "1"); 5003 5004 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5005 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5006 } 5007 5008 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5009 return llvm::makeArrayRef(BuiltinInfo, 5010 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5011 } 5012 bool isCLZForZeroUndef() const override { return false; } 5013 BuiltinVaListKind getBuiltinVaListKind() const override { 5014 return IsAAPCS 5015 ? AAPCSABIBuiltinVaList 5016 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5017 : TargetInfo::VoidPtrBuiltinVaList); 5018 } 5019 ArrayRef<const char *> getGCCRegNames() const override; 5020 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5021 bool validateAsmConstraint(const char *&Name, 5022 TargetInfo::ConstraintInfo &Info) const override { 5023 switch (*Name) { 5024 default: break; 5025 case 'l': // r0-r7 5026 case 'h': // r8-r15 5027 case 't': // VFP Floating point register single precision 5028 case 'w': // VFP Floating point register double precision 5029 Info.setAllowsRegister(); 5030 return true; 5031 case 'I': 5032 case 'J': 5033 case 'K': 5034 case 'L': 5035 case 'M': 5036 // FIXME 5037 return true; 5038 case 'Q': // A memory address that is a single base register. 5039 Info.setAllowsMemory(); 5040 return true; 5041 case 'U': // a memory reference... 5042 switch (Name[1]) { 5043 case 'q': // ...ARMV4 ldrsb 5044 case 'v': // ...VFP load/store (reg+constant offset) 5045 case 'y': // ...iWMMXt load/store 5046 case 't': // address valid for load/store opaque types wider 5047 // than 128-bits 5048 case 'n': // valid address for Neon doubleword vector load/store 5049 case 'm': // valid address for Neon element and structure load/store 5050 case 's': // valid address for non-offset loads/stores of quad-word 5051 // values in four ARM registers 5052 Info.setAllowsMemory(); 5053 Name++; 5054 return true; 5055 } 5056 } 5057 return false; 5058 } 5059 std::string convertConstraint(const char *&Constraint) const override { 5060 std::string R; 5061 switch (*Constraint) { 5062 case 'U': // Two-character constraint; add "^" hint for later parsing. 5063 R = std::string("^") + std::string(Constraint, 2); 5064 Constraint++; 5065 break; 5066 case 'p': // 'p' should be translated to 'r' by default. 5067 R = std::string("r"); 5068 break; 5069 default: 5070 return std::string(1, *Constraint); 5071 } 5072 return R; 5073 } 5074 bool 5075 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5076 std::string &SuggestedModifier) const override { 5077 bool isOutput = (Constraint[0] == '='); 5078 bool isInOut = (Constraint[0] == '+'); 5079 5080 // Strip off constraint modifiers. 5081 while (Constraint[0] == '=' || 5082 Constraint[0] == '+' || 5083 Constraint[0] == '&') 5084 Constraint = Constraint.substr(1); 5085 5086 switch (Constraint[0]) { 5087 default: break; 5088 case 'r': { 5089 switch (Modifier) { 5090 default: 5091 return (isInOut || isOutput || Size <= 64); 5092 case 'q': 5093 // A register of size 32 cannot fit a vector type. 5094 return false; 5095 } 5096 } 5097 } 5098 5099 return true; 5100 } 5101 const char *getClobbers() const override { 5102 // FIXME: Is this really right? 5103 return ""; 5104 } 5105 5106 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5107 switch (CC) { 5108 case CC_AAPCS: 5109 case CC_AAPCS_VFP: 5110 case CC_Swift: 5111 return CCCR_OK; 5112 default: 5113 return CCCR_Warning; 5114 } 5115 } 5116 5117 int getEHDataRegisterNumber(unsigned RegNo) const override { 5118 if (RegNo == 0) return 0; 5119 if (RegNo == 1) return 1; 5120 return -1; 5121 } 5122 5123 bool hasSjLjLowering() const override { 5124 return true; 5125 } 5126 }; 5127 5128 bool ARMTargetInfo::setFPMath(StringRef Name) { 5129 if (Name == "neon") { 5130 FPMath = FP_Neon; 5131 return true; 5132 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5133 Name == "vfp4") { 5134 FPMath = FP_VFP; 5135 return true; 5136 } 5137 return false; 5138 } 5139 5140 const char * const ARMTargetInfo::GCCRegNames[] = { 5141 // Integer registers 5142 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5143 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5144 5145 // Float registers 5146 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5147 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5148 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5149 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5150 5151 // Double registers 5152 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5153 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5154 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5155 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5156 5157 // Quad registers 5158 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5159 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5160 }; 5161 5162 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5163 return llvm::makeArrayRef(GCCRegNames); 5164 } 5165 5166 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5167 { { "a1" }, "r0" }, 5168 { { "a2" }, "r1" }, 5169 { { "a3" }, "r2" }, 5170 { { "a4" }, "r3" }, 5171 { { "v1" }, "r4" }, 5172 { { "v2" }, "r5" }, 5173 { { "v3" }, "r6" }, 5174 { { "v4" }, "r7" }, 5175 { { "v5" }, "r8" }, 5176 { { "v6", "rfp" }, "r9" }, 5177 { { "sl" }, "r10" }, 5178 { { "fp" }, "r11" }, 5179 { { "ip" }, "r12" }, 5180 { { "r13" }, "sp" }, 5181 { { "r14" }, "lr" }, 5182 { { "r15" }, "pc" }, 5183 // The S, D and Q registers overlap, but aren't really aliases; we 5184 // don't want to substitute one of these for a different-sized one. 5185 }; 5186 5187 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5188 return llvm::makeArrayRef(GCCRegAliases); 5189 } 5190 5191 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5192 #define BUILTIN(ID, TYPE, ATTRS) \ 5193 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5194 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5195 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5196 #include "clang/Basic/BuiltinsNEON.def" 5197 5198 #define BUILTIN(ID, TYPE, ATTRS) \ 5199 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5200 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5201 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5202 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5203 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5204 #include "clang/Basic/BuiltinsARM.def" 5205 }; 5206 5207 class ARMleTargetInfo : public ARMTargetInfo { 5208 public: 5209 ARMleTargetInfo(const llvm::Triple &Triple) 5210 : ARMTargetInfo(Triple, false) { } 5211 void getTargetDefines(const LangOptions &Opts, 5212 MacroBuilder &Builder) const override { 5213 Builder.defineMacro("__ARMEL__"); 5214 ARMTargetInfo::getTargetDefines(Opts, Builder); 5215 } 5216 }; 5217 5218 class ARMbeTargetInfo : public ARMTargetInfo { 5219 public: 5220 ARMbeTargetInfo(const llvm::Triple &Triple) 5221 : ARMTargetInfo(Triple, true) { } 5222 void getTargetDefines(const LangOptions &Opts, 5223 MacroBuilder &Builder) const override { 5224 Builder.defineMacro("__ARMEB__"); 5225 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5226 ARMTargetInfo::getTargetDefines(Opts, Builder); 5227 } 5228 }; 5229 5230 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5231 const llvm::Triple Triple; 5232 public: 5233 WindowsARMTargetInfo(const llvm::Triple &Triple) 5234 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 5235 WCharType = UnsignedShort; 5236 SizeType = UnsignedInt; 5237 } 5238 void getVisualStudioDefines(const LangOptions &Opts, 5239 MacroBuilder &Builder) const { 5240 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5241 5242 // FIXME: this is invalid for WindowsCE 5243 Builder.defineMacro("_M_ARM_NT", "1"); 5244 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5245 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5246 5247 assert((Triple.getArch() == llvm::Triple::arm || 5248 Triple.getArch() == llvm::Triple::thumb) && 5249 "invalid architecture for Windows ARM target info"); 5250 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5251 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5252 5253 // TODO map the complete set of values 5254 // 31: VFPv3 40: VFPv4 5255 Builder.defineMacro("_M_ARM_FP", "31"); 5256 } 5257 BuiltinVaListKind getBuiltinVaListKind() const override { 5258 return TargetInfo::CharPtrBuiltinVaList; 5259 } 5260 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5261 switch (CC) { 5262 case CC_X86StdCall: 5263 case CC_X86ThisCall: 5264 case CC_X86FastCall: 5265 case CC_X86VectorCall: 5266 return CCCR_Ignore; 5267 case CC_C: 5268 return CCCR_OK; 5269 default: 5270 return CCCR_Warning; 5271 } 5272 } 5273 }; 5274 5275 // Windows ARM + Itanium C++ ABI Target 5276 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5277 public: 5278 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5279 : WindowsARMTargetInfo(Triple) { 5280 TheCXXABI.set(TargetCXXABI::GenericARM); 5281 } 5282 5283 void getTargetDefines(const LangOptions &Opts, 5284 MacroBuilder &Builder) const override { 5285 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5286 5287 if (Opts.MSVCCompat) 5288 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5289 } 5290 }; 5291 5292 // Windows ARM, MS (C++) ABI 5293 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5294 public: 5295 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5296 : WindowsARMTargetInfo(Triple) { 5297 TheCXXABI.set(TargetCXXABI::Microsoft); 5298 } 5299 5300 void getTargetDefines(const LangOptions &Opts, 5301 MacroBuilder &Builder) const override { 5302 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5303 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5304 } 5305 }; 5306 5307 // ARM MinGW target 5308 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5309 public: 5310 MinGWARMTargetInfo(const llvm::Triple &Triple) 5311 : WindowsARMTargetInfo(Triple) { 5312 TheCXXABI.set(TargetCXXABI::GenericARM); 5313 } 5314 5315 void getTargetDefines(const LangOptions &Opts, 5316 MacroBuilder &Builder) const override { 5317 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5318 DefineStd(Builder, "WIN32", Opts); 5319 DefineStd(Builder, "WINNT", Opts); 5320 Builder.defineMacro("_ARM_"); 5321 addMinGWDefines(Opts, Builder); 5322 } 5323 }; 5324 5325 // ARM Cygwin target 5326 class CygwinARMTargetInfo : public ARMleTargetInfo { 5327 public: 5328 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5329 TLSSupported = false; 5330 WCharType = UnsignedShort; 5331 DoubleAlign = LongLongAlign = 64; 5332 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5333 } 5334 void getTargetDefines(const LangOptions &Opts, 5335 MacroBuilder &Builder) const override { 5336 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5337 Builder.defineMacro("_ARM_"); 5338 Builder.defineMacro("__CYGWIN__"); 5339 Builder.defineMacro("__CYGWIN32__"); 5340 DefineStd(Builder, "unix", Opts); 5341 if (Opts.CPlusPlus) 5342 Builder.defineMacro("_GNU_SOURCE"); 5343 } 5344 }; 5345 5346 class DarwinARMTargetInfo : 5347 public DarwinTargetInfo<ARMleTargetInfo> { 5348 protected: 5349 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5350 MacroBuilder &Builder) const override { 5351 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5352 } 5353 5354 public: 5355 DarwinARMTargetInfo(const llvm::Triple &Triple) 5356 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5357 HasAlignMac68kSupport = true; 5358 // iOS always has 64-bit atomic instructions. 5359 // FIXME: This should be based off of the target features in 5360 // ARMleTargetInfo. 5361 MaxAtomicInlineWidth = 64; 5362 5363 if (Triple.isWatchABI()) { 5364 // Darwin on iOS uses a variant of the ARM C++ ABI. 5365 TheCXXABI.set(TargetCXXABI::WatchOS); 5366 5367 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5368 // size_t is long, it's a bit weird for it to be int. 5369 PtrDiffType = SignedLong; 5370 5371 // BOOL should be a real boolean on the new ABI 5372 UseSignedCharForObjCBool = false; 5373 } else 5374 TheCXXABI.set(TargetCXXABI::iOS); 5375 } 5376 }; 5377 5378 class AArch64TargetInfo : public TargetInfo { 5379 virtual void setDataLayout() = 0; 5380 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5381 static const char *const GCCRegNames[]; 5382 5383 enum FPUModeEnum { 5384 FPUMode, 5385 NeonMode 5386 }; 5387 5388 unsigned FPU; 5389 unsigned CRC; 5390 unsigned Crypto; 5391 unsigned Unaligned; 5392 unsigned V8_1A; 5393 5394 static const Builtin::Info BuiltinInfo[]; 5395 5396 std::string ABI; 5397 5398 public: 5399 AArch64TargetInfo(const llvm::Triple &Triple) 5400 : TargetInfo(Triple), ABI("aapcs") { 5401 5402 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5403 WCharType = SignedInt; 5404 5405 // NetBSD apparently prefers consistency across ARM targets to consistency 5406 // across 64-bit targets. 5407 Int64Type = SignedLongLong; 5408 IntMaxType = SignedLongLong; 5409 } else { 5410 WCharType = UnsignedInt; 5411 Int64Type = SignedLong; 5412 IntMaxType = SignedLong; 5413 } 5414 5415 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5416 MaxVectorAlign = 128; 5417 MaxAtomicInlineWidth = 128; 5418 MaxAtomicPromoteWidth = 128; 5419 5420 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5421 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5422 5423 // {} in inline assembly are neon specifiers, not assembly variant 5424 // specifiers. 5425 NoAsmVariants = true; 5426 5427 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5428 // contributes to the alignment of the containing aggregate in the same way 5429 // a plain (non bit-field) member of that type would, without exception for 5430 // zero-sized or anonymous bit-fields." 5431 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5432 UseZeroLengthBitfieldAlignment = true; 5433 5434 // AArch64 targets default to using the ARM C++ ABI. 5435 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5436 } 5437 5438 StringRef getABI() const override { return ABI; } 5439 bool setABI(const std::string &Name) override { 5440 if (Name != "aapcs" && Name != "darwinpcs") 5441 return false; 5442 5443 ABI = Name; 5444 return true; 5445 } 5446 5447 bool setCPU(const std::string &Name) override { 5448 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5449 .Case("generic", true) 5450 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5451 "cortex-a35", "exynos-m1", true) 5452 .Case("cyclone", true) 5453 .Case("kryo", true) 5454 .Default(false); 5455 return CPUKnown; 5456 } 5457 5458 void getTargetDefines(const LangOptions &Opts, 5459 MacroBuilder &Builder) const override { 5460 // Target identification. 5461 Builder.defineMacro("__aarch64__"); 5462 5463 // Target properties. 5464 Builder.defineMacro("_LP64"); 5465 Builder.defineMacro("__LP64__"); 5466 5467 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5468 Builder.defineMacro("__ARM_ACLE", "200"); 5469 Builder.defineMacro("__ARM_ARCH", "8"); 5470 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5471 5472 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5473 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5474 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5475 5476 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5477 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5478 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5479 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5480 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5481 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5482 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5483 5484 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5485 5486 // 0xe implies support for half, single and double precision operations. 5487 Builder.defineMacro("__ARM_FP", "0xE"); 5488 5489 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5490 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5491 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5492 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5493 5494 if (Opts.UnsafeFPMath) 5495 Builder.defineMacro("__ARM_FP_FAST", "1"); 5496 5497 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5498 5499 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5500 Opts.ShortEnums ? "1" : "4"); 5501 5502 if (FPU == NeonMode) { 5503 Builder.defineMacro("__ARM_NEON", "1"); 5504 // 64-bit NEON supports half, single and double precision operations. 5505 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5506 } 5507 5508 if (CRC) 5509 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5510 5511 if (Crypto) 5512 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5513 5514 if (Unaligned) 5515 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5516 5517 if (V8_1A) 5518 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5519 5520 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5521 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5522 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5523 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5524 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5525 } 5526 5527 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5528 return llvm::makeArrayRef(BuiltinInfo, 5529 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5530 } 5531 5532 bool hasFeature(StringRef Feature) const override { 5533 return Feature == "aarch64" || 5534 Feature == "arm64" || 5535 Feature == "arm" || 5536 (Feature == "neon" && FPU == NeonMode); 5537 } 5538 5539 bool handleTargetFeatures(std::vector<std::string> &Features, 5540 DiagnosticsEngine &Diags) override { 5541 FPU = FPUMode; 5542 CRC = 0; 5543 Crypto = 0; 5544 Unaligned = 1; 5545 V8_1A = 0; 5546 5547 for (const auto &Feature : Features) { 5548 if (Feature == "+neon") 5549 FPU = NeonMode; 5550 if (Feature == "+crc") 5551 CRC = 1; 5552 if (Feature == "+crypto") 5553 Crypto = 1; 5554 if (Feature == "+strict-align") 5555 Unaligned = 0; 5556 if (Feature == "+v8.1a") 5557 V8_1A = 1; 5558 } 5559 5560 setDataLayout(); 5561 5562 return true; 5563 } 5564 5565 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5566 switch (CC) { 5567 case CC_C: 5568 case CC_Swift: 5569 case CC_PreserveMost: 5570 case CC_PreserveAll: 5571 return CCCR_OK; 5572 default: 5573 return CCCR_Warning; 5574 } 5575 } 5576 5577 bool isCLZForZeroUndef() const override { return false; } 5578 5579 BuiltinVaListKind getBuiltinVaListKind() const override { 5580 return TargetInfo::AArch64ABIBuiltinVaList; 5581 } 5582 5583 ArrayRef<const char *> getGCCRegNames() const override; 5584 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5585 5586 bool validateAsmConstraint(const char *&Name, 5587 TargetInfo::ConstraintInfo &Info) const override { 5588 switch (*Name) { 5589 default: 5590 return false; 5591 case 'w': // Floating point and SIMD registers (V0-V31) 5592 Info.setAllowsRegister(); 5593 return true; 5594 case 'I': // Constant that can be used with an ADD instruction 5595 case 'J': // Constant that can be used with a SUB instruction 5596 case 'K': // Constant that can be used with a 32-bit logical instruction 5597 case 'L': // Constant that can be used with a 64-bit logical instruction 5598 case 'M': // Constant that can be used as a 32-bit MOV immediate 5599 case 'N': // Constant that can be used as a 64-bit MOV immediate 5600 case 'Y': // Floating point constant zero 5601 case 'Z': // Integer constant zero 5602 return true; 5603 case 'Q': // A memory reference with base register and no offset 5604 Info.setAllowsMemory(); 5605 return true; 5606 case 'S': // A symbolic address 5607 Info.setAllowsRegister(); 5608 return true; 5609 case 'U': 5610 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5611 // Utf: A memory address suitable for ldp/stp in TF mode. 5612 // Usa: An absolute symbolic address. 5613 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5614 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5615 case 'z': // Zero register, wzr or xzr 5616 Info.setAllowsRegister(); 5617 return true; 5618 case 'x': // Floating point and SIMD registers (V0-V15) 5619 Info.setAllowsRegister(); 5620 return true; 5621 } 5622 return false; 5623 } 5624 5625 bool 5626 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5627 std::string &SuggestedModifier) const override { 5628 // Strip off constraint modifiers. 5629 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5630 Constraint = Constraint.substr(1); 5631 5632 switch (Constraint[0]) { 5633 default: 5634 return true; 5635 case 'z': 5636 case 'r': { 5637 switch (Modifier) { 5638 case 'x': 5639 case 'w': 5640 // For now assume that the person knows what they're 5641 // doing with the modifier. 5642 return true; 5643 default: 5644 // By default an 'r' constraint will be in the 'x' 5645 // registers. 5646 if (Size == 64) 5647 return true; 5648 5649 SuggestedModifier = "w"; 5650 return false; 5651 } 5652 } 5653 } 5654 } 5655 5656 const char *getClobbers() const override { return ""; } 5657 5658 int getEHDataRegisterNumber(unsigned RegNo) const override { 5659 if (RegNo == 0) 5660 return 0; 5661 if (RegNo == 1) 5662 return 1; 5663 return -1; 5664 } 5665 }; 5666 5667 const char *const AArch64TargetInfo::GCCRegNames[] = { 5668 // 32-bit Integer registers 5669 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5670 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5671 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5672 5673 // 64-bit Integer registers 5674 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5675 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5676 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5677 5678 // 32-bit floating point regsisters 5679 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5680 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5681 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5682 5683 // 64-bit floating point regsisters 5684 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5685 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5686 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5687 5688 // Vector registers 5689 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5690 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5691 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5692 }; 5693 5694 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5695 return llvm::makeArrayRef(GCCRegNames); 5696 } 5697 5698 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5699 { { "w31" }, "wsp" }, 5700 { { "x29" }, "fp" }, 5701 { { "x30" }, "lr" }, 5702 { { "x31" }, "sp" }, 5703 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5704 // don't want to substitute one of these for a different-sized one. 5705 }; 5706 5707 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5708 return llvm::makeArrayRef(GCCRegAliases); 5709 } 5710 5711 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5712 #define BUILTIN(ID, TYPE, ATTRS) \ 5713 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5714 #include "clang/Basic/BuiltinsNEON.def" 5715 5716 #define BUILTIN(ID, TYPE, ATTRS) \ 5717 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5718 #include "clang/Basic/BuiltinsAArch64.def" 5719 }; 5720 5721 class AArch64leTargetInfo : public AArch64TargetInfo { 5722 void setDataLayout() override { 5723 if (getTriple().isOSBinFormatMachO()) 5724 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 5725 else 5726 resetDataLayout("e-m:e-i64:64-i128:128-n32:64-S128"); 5727 } 5728 5729 public: 5730 AArch64leTargetInfo(const llvm::Triple &Triple) 5731 : AArch64TargetInfo(Triple) { 5732 BigEndian = false; 5733 } 5734 void getTargetDefines(const LangOptions &Opts, 5735 MacroBuilder &Builder) const override { 5736 Builder.defineMacro("__AARCH64EL__"); 5737 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5738 } 5739 }; 5740 5741 class AArch64beTargetInfo : public AArch64TargetInfo { 5742 void setDataLayout() override { 5743 assert(!getTriple().isOSBinFormatMachO()); 5744 resetDataLayout("E-m:e-i64:64-i128:128-n32:64-S128"); 5745 } 5746 5747 public: 5748 AArch64beTargetInfo(const llvm::Triple &Triple) 5749 : AArch64TargetInfo(Triple) { } 5750 void getTargetDefines(const LangOptions &Opts, 5751 MacroBuilder &Builder) const override { 5752 Builder.defineMacro("__AARCH64EB__"); 5753 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5754 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5755 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5756 } 5757 }; 5758 5759 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5760 protected: 5761 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5762 MacroBuilder &Builder) const override { 5763 Builder.defineMacro("__AARCH64_SIMD__"); 5764 Builder.defineMacro("__ARM64_ARCH_8__"); 5765 Builder.defineMacro("__ARM_NEON__"); 5766 Builder.defineMacro("__LITTLE_ENDIAN__"); 5767 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5768 Builder.defineMacro("__arm64", "1"); 5769 Builder.defineMacro("__arm64__", "1"); 5770 5771 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5772 } 5773 5774 public: 5775 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5776 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5777 Int64Type = SignedLongLong; 5778 WCharType = SignedInt; 5779 UseSignedCharForObjCBool = false; 5780 5781 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5782 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5783 5784 TheCXXABI.set(TargetCXXABI::iOS64); 5785 } 5786 5787 BuiltinVaListKind getBuiltinVaListKind() const override { 5788 return TargetInfo::CharPtrBuiltinVaList; 5789 } 5790 }; 5791 5792 // Hexagon abstract base class 5793 class HexagonTargetInfo : public TargetInfo { 5794 static const Builtin::Info BuiltinInfo[]; 5795 static const char * const GCCRegNames[]; 5796 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5797 std::string CPU; 5798 bool HasHVX, HasHVXDouble; 5799 5800 public: 5801 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5802 BigEndian = false; 5803 // Specify the vector alignment explicitly. For v512x1, the calculated 5804 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 5805 // the required minimum of 64 bytes. 5806 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 5807 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 5808 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 5809 SizeType = UnsignedInt; 5810 PtrDiffType = SignedInt; 5811 IntPtrType = SignedInt; 5812 5813 // {} in inline assembly are packet specifiers, not assembly variant 5814 // specifiers. 5815 NoAsmVariants = true; 5816 5817 LargeArrayMinWidth = 64; 5818 LargeArrayAlign = 64; 5819 UseBitFieldTypeAlignment = true; 5820 ZeroLengthBitfieldBoundary = 32; 5821 HasHVX = HasHVXDouble = false; 5822 } 5823 5824 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5825 return llvm::makeArrayRef(BuiltinInfo, 5826 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5827 } 5828 5829 bool validateAsmConstraint(const char *&Name, 5830 TargetInfo::ConstraintInfo &Info) const override { 5831 return true; 5832 } 5833 5834 void getTargetDefines(const LangOptions &Opts, 5835 MacroBuilder &Builder) const override; 5836 5837 bool isCLZForZeroUndef() const override { return false; } 5838 5839 bool hasFeature(StringRef Feature) const override { 5840 return llvm::StringSwitch<bool>(Feature) 5841 .Case("hexagon", true) 5842 .Case("hvx", HasHVX) 5843 .Case("hvx-double", HasHVXDouble) 5844 .Default(false); 5845 } 5846 5847 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5848 StringRef CPU, const std::vector<std::string> &FeaturesVec) 5849 const override; 5850 5851 bool handleTargetFeatures(std::vector<std::string> &Features, 5852 DiagnosticsEngine &Diags) override; 5853 5854 BuiltinVaListKind getBuiltinVaListKind() const override { 5855 return TargetInfo::CharPtrBuiltinVaList; 5856 } 5857 ArrayRef<const char *> getGCCRegNames() const override; 5858 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5859 const char *getClobbers() const override { 5860 return ""; 5861 } 5862 5863 static const char *getHexagonCPUSuffix(StringRef Name) { 5864 return llvm::StringSwitch<const char*>(Name) 5865 .Case("hexagonv4", "4") 5866 .Case("hexagonv5", "5") 5867 .Case("hexagonv55", "55") 5868 .Case("hexagonv60", "60") 5869 .Default(nullptr); 5870 } 5871 5872 bool setCPU(const std::string &Name) override { 5873 if (!getHexagonCPUSuffix(Name)) 5874 return false; 5875 CPU = Name; 5876 return true; 5877 } 5878 5879 int getEHDataRegisterNumber(unsigned RegNo) const override { 5880 return RegNo < 2 ? RegNo : -1; 5881 } 5882 }; 5883 5884 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5885 MacroBuilder &Builder) const { 5886 Builder.defineMacro("__qdsp6__", "1"); 5887 Builder.defineMacro("__hexagon__", "1"); 5888 5889 if (CPU == "hexagonv4") { 5890 Builder.defineMacro("__HEXAGON_V4__"); 5891 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5892 if (Opts.HexagonQdsp6Compat) { 5893 Builder.defineMacro("__QDSP6_V4__"); 5894 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5895 } 5896 } else if (CPU == "hexagonv5") { 5897 Builder.defineMacro("__HEXAGON_V5__"); 5898 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5899 if(Opts.HexagonQdsp6Compat) { 5900 Builder.defineMacro("__QDSP6_V5__"); 5901 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5902 } 5903 } else if (CPU == "hexagonv60") { 5904 Builder.defineMacro("__HEXAGON_V60__"); 5905 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 5906 Builder.defineMacro("__QDSP6_V60__"); 5907 Builder.defineMacro("__QDSP6_ARCH__", "60"); 5908 } 5909 } 5910 5911 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 5912 DiagnosticsEngine &Diags) { 5913 for (auto &F : Features) { 5914 if (F == "+hvx") 5915 HasHVX = true; 5916 else if (F == "-hvx") 5917 HasHVX = HasHVXDouble = false; 5918 else if (F == "+hvx-double") 5919 HasHVX = HasHVXDouble = true; 5920 else if (F == "-hvx-double") 5921 HasHVXDouble = false; 5922 } 5923 return true; 5924 } 5925 5926 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 5927 DiagnosticsEngine &Diags, StringRef CPU, 5928 const std::vector<std::string> &FeaturesVec) const { 5929 // Default for v60: -hvx, -hvx-double. 5930 Features["hvx"] = false; 5931 Features["hvx-double"] = false; 5932 5933 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5934 } 5935 5936 5937 const char *const HexagonTargetInfo::GCCRegNames[] = { 5938 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5939 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5940 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5941 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5942 "p0", "p1", "p2", "p3", 5943 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5944 }; 5945 5946 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 5947 return llvm::makeArrayRef(GCCRegNames); 5948 } 5949 5950 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5951 { { "sp" }, "r29" }, 5952 { { "fp" }, "r30" }, 5953 { { "lr" }, "r31" }, 5954 }; 5955 5956 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 5957 return llvm::makeArrayRef(GCCRegAliases); 5958 } 5959 5960 5961 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5962 #define BUILTIN(ID, TYPE, ATTRS) \ 5963 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5964 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5965 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5966 #include "clang/Basic/BuiltinsHexagon.def" 5967 }; 5968 5969 class LanaiTargetInfo : public TargetInfo { 5970 // Class for Lanai (32-bit). 5971 // The CPU profiles supported by the Lanai backend 5972 enum CPUKind { 5973 CK_NONE, 5974 CK_V11, 5975 } CPU; 5976 5977 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5978 static const char *const GCCRegNames[]; 5979 5980 public: 5981 LanaiTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5982 // Description string has to be kept in sync with backend. 5983 resetDataLayout("E" // Big endian 5984 "-m:e" // ELF name manging 5985 "-p:32:32" // 32 bit pointers, 32 bit aligned 5986 "-i64:64" // 64 bit integers, 64 bit aligned 5987 "-a:0:32" // 32 bit alignment of objects of aggregate type 5988 "-n32" // 32 bit native integer width 5989 "-S64" // 64 bit natural stack alignment 5990 ); 5991 5992 // Setting RegParmMax equal to what mregparm was set to in the old 5993 // toolchain 5994 RegParmMax = 4; 5995 5996 // Set the default CPU to V11 5997 CPU = CK_V11; 5998 5999 // Temporary approach to make everything at least word-aligned and allow for 6000 // safely casting between pointers with different alignment requirements. 6001 // TODO: Remove this when there are no more cast align warnings on the 6002 // firmware. 6003 MinGlobalAlign = 32; 6004 } 6005 6006 void getTargetDefines(const LangOptions &Opts, 6007 MacroBuilder &Builder) const override { 6008 // Define __lanai__ when building for target lanai. 6009 Builder.defineMacro("__lanai__"); 6010 6011 // Set define for the CPU specified. 6012 switch (CPU) { 6013 case CK_V11: 6014 Builder.defineMacro("__LANAI_V11__"); 6015 break; 6016 case CK_NONE: 6017 llvm_unreachable("Unhandled target CPU"); 6018 } 6019 } 6020 6021 bool setCPU(const std::string &Name) override { 6022 CPU = llvm::StringSwitch<CPUKind>(Name) 6023 .Case("v11", CK_V11) 6024 .Default(CK_NONE); 6025 6026 return CPU != CK_NONE; 6027 } 6028 6029 bool hasFeature(StringRef Feature) const override { 6030 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6031 } 6032 6033 ArrayRef<const char *> getGCCRegNames() const override; 6034 6035 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6036 6037 BuiltinVaListKind getBuiltinVaListKind() const override { 6038 return TargetInfo::VoidPtrBuiltinVaList; 6039 } 6040 6041 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6042 6043 bool validateAsmConstraint(const char *&Name, 6044 TargetInfo::ConstraintInfo &info) const override { 6045 return false; 6046 } 6047 6048 const char *getClobbers() const override { return ""; } 6049 }; 6050 6051 const char *const LanaiTargetInfo::GCCRegNames[] = { 6052 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6053 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6054 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6055 6056 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6057 return llvm::makeArrayRef(GCCRegNames); 6058 } 6059 6060 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6061 {{"pc"}, "r2"}, 6062 {{"sp"}, "r4"}, 6063 {{"fp"}, "r5"}, 6064 {{"rv"}, "r8"}, 6065 {{"rr1"}, "r10"}, 6066 {{"rr2"}, "r11"}, 6067 {{"rca"}, "r15"}, 6068 }; 6069 6070 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6071 return llvm::makeArrayRef(GCCRegAliases); 6072 } 6073 6074 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6075 class SparcTargetInfo : public TargetInfo { 6076 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6077 static const char * const GCCRegNames[]; 6078 bool SoftFloat; 6079 public: 6080 SparcTargetInfo(const llvm::Triple &Triple) 6081 : TargetInfo(Triple), SoftFloat(false) {} 6082 6083 int getEHDataRegisterNumber(unsigned RegNo) const override { 6084 if (RegNo == 0) return 24; 6085 if (RegNo == 1) return 25; 6086 return -1; 6087 } 6088 6089 bool handleTargetFeatures(std::vector<std::string> &Features, 6090 DiagnosticsEngine &Diags) override { 6091 // The backend doesn't actually handle soft float yet, but in case someone 6092 // is using the support for the front end continue to support it. 6093 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6094 if (Feature != Features.end()) { 6095 SoftFloat = true; 6096 Features.erase(Feature); 6097 } 6098 return true; 6099 } 6100 void getTargetDefines(const LangOptions &Opts, 6101 MacroBuilder &Builder) const override { 6102 DefineStd(Builder, "sparc", Opts); 6103 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6104 6105 if (SoftFloat) 6106 Builder.defineMacro("SOFT_FLOAT", "1"); 6107 } 6108 6109 bool hasFeature(StringRef Feature) const override { 6110 return llvm::StringSwitch<bool>(Feature) 6111 .Case("softfloat", SoftFloat) 6112 .Case("sparc", true) 6113 .Default(false); 6114 } 6115 6116 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6117 // FIXME: Implement! 6118 return None; 6119 } 6120 BuiltinVaListKind getBuiltinVaListKind() const override { 6121 return TargetInfo::VoidPtrBuiltinVaList; 6122 } 6123 ArrayRef<const char *> getGCCRegNames() const override; 6124 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6125 bool validateAsmConstraint(const char *&Name, 6126 TargetInfo::ConstraintInfo &info) const override { 6127 // FIXME: Implement! 6128 switch (*Name) { 6129 case 'I': // Signed 13-bit constant 6130 case 'J': // Zero 6131 case 'K': // 32-bit constant with the low 12 bits clear 6132 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6133 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6134 case 'N': // Same as 'K' but zext (required for SIMode) 6135 case 'O': // The constant 4096 6136 return true; 6137 } 6138 return false; 6139 } 6140 const char *getClobbers() const override { 6141 // FIXME: Implement! 6142 return ""; 6143 } 6144 6145 // No Sparc V7 for now, the backend doesn't support it anyway. 6146 enum CPUKind { 6147 CK_GENERIC, 6148 CK_V8, 6149 CK_SUPERSPARC, 6150 CK_SPARCLITE, 6151 CK_F934, 6152 CK_HYPERSPARC, 6153 CK_SPARCLITE86X, 6154 CK_SPARCLET, 6155 CK_TSC701, 6156 CK_V9, 6157 CK_ULTRASPARC, 6158 CK_ULTRASPARC3, 6159 CK_NIAGARA, 6160 CK_NIAGARA2, 6161 CK_NIAGARA3, 6162 CK_NIAGARA4, 6163 CK_MYRIAD2_1, 6164 CK_MYRIAD2_2 6165 } CPU = CK_GENERIC; 6166 6167 enum CPUGeneration { 6168 CG_V8, 6169 CG_V9, 6170 }; 6171 6172 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6173 switch (Kind) { 6174 case CK_GENERIC: 6175 case CK_V8: 6176 case CK_SUPERSPARC: 6177 case CK_SPARCLITE: 6178 case CK_F934: 6179 case CK_HYPERSPARC: 6180 case CK_SPARCLITE86X: 6181 case CK_SPARCLET: 6182 case CK_TSC701: 6183 case CK_MYRIAD2_1: 6184 case CK_MYRIAD2_2: 6185 return CG_V8; 6186 case CK_V9: 6187 case CK_ULTRASPARC: 6188 case CK_ULTRASPARC3: 6189 case CK_NIAGARA: 6190 case CK_NIAGARA2: 6191 case CK_NIAGARA3: 6192 case CK_NIAGARA4: 6193 return CG_V9; 6194 } 6195 llvm_unreachable("Unexpected CPU kind"); 6196 } 6197 6198 CPUKind getCPUKind(StringRef Name) const { 6199 return llvm::StringSwitch<CPUKind>(Name) 6200 .Case("v8", CK_V8) 6201 .Case("supersparc", CK_SUPERSPARC) 6202 .Case("sparclite", CK_SPARCLITE) 6203 .Case("f934", CK_F934) 6204 .Case("hypersparc", CK_HYPERSPARC) 6205 .Case("sparclite86x", CK_SPARCLITE86X) 6206 .Case("sparclet", CK_SPARCLET) 6207 .Case("tsc701", CK_TSC701) 6208 .Case("v9", CK_V9) 6209 .Case("ultrasparc", CK_ULTRASPARC) 6210 .Case("ultrasparc3", CK_ULTRASPARC3) 6211 .Case("niagara", CK_NIAGARA) 6212 .Case("niagara2", CK_NIAGARA2) 6213 .Case("niagara3", CK_NIAGARA3) 6214 .Case("niagara4", CK_NIAGARA4) 6215 .Case("myriad2", CK_MYRIAD2_1) 6216 .Case("myriad2.1", CK_MYRIAD2_1) 6217 .Case("myriad2.2", CK_MYRIAD2_2) 6218 .Default(CK_GENERIC); 6219 } 6220 6221 bool setCPU(const std::string &Name) override { 6222 CPU = getCPUKind(Name); 6223 return CPU != CK_GENERIC; 6224 } 6225 }; 6226 6227 const char * const SparcTargetInfo::GCCRegNames[] = { 6228 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6229 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6230 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6231 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6232 }; 6233 6234 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6235 return llvm::makeArrayRef(GCCRegNames); 6236 } 6237 6238 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6239 { { "g0" }, "r0" }, 6240 { { "g1" }, "r1" }, 6241 { { "g2" }, "r2" }, 6242 { { "g3" }, "r3" }, 6243 { { "g4" }, "r4" }, 6244 { { "g5" }, "r5" }, 6245 { { "g6" }, "r6" }, 6246 { { "g7" }, "r7" }, 6247 { { "o0" }, "r8" }, 6248 { { "o1" }, "r9" }, 6249 { { "o2" }, "r10" }, 6250 { { "o3" }, "r11" }, 6251 { { "o4" }, "r12" }, 6252 { { "o5" }, "r13" }, 6253 { { "o6", "sp" }, "r14" }, 6254 { { "o7" }, "r15" }, 6255 { { "l0" }, "r16" }, 6256 { { "l1" }, "r17" }, 6257 { { "l2" }, "r18" }, 6258 { { "l3" }, "r19" }, 6259 { { "l4" }, "r20" }, 6260 { { "l5" }, "r21" }, 6261 { { "l6" }, "r22" }, 6262 { { "l7" }, "r23" }, 6263 { { "i0" }, "r24" }, 6264 { { "i1" }, "r25" }, 6265 { { "i2" }, "r26" }, 6266 { { "i3" }, "r27" }, 6267 { { "i4" }, "r28" }, 6268 { { "i5" }, "r29" }, 6269 { { "i6", "fp" }, "r30" }, 6270 { { "i7" }, "r31" }, 6271 }; 6272 6273 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6274 return llvm::makeArrayRef(GCCRegAliases); 6275 } 6276 6277 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6278 class SparcV8TargetInfo : public SparcTargetInfo { 6279 public: 6280 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6281 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6282 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6283 switch (getTriple().getOS()) { 6284 default: 6285 SizeType = UnsignedInt; 6286 IntPtrType = SignedInt; 6287 PtrDiffType = SignedInt; 6288 break; 6289 case llvm::Triple::NetBSD: 6290 case llvm::Triple::OpenBSD: 6291 SizeType = UnsignedLong; 6292 IntPtrType = SignedLong; 6293 PtrDiffType = SignedLong; 6294 break; 6295 } 6296 } 6297 6298 void getTargetDefines(const LangOptions &Opts, 6299 MacroBuilder &Builder) const override { 6300 SparcTargetInfo::getTargetDefines(Opts, Builder); 6301 switch (getCPUGeneration(CPU)) { 6302 case CG_V8: 6303 Builder.defineMacro("__sparcv8"); 6304 if (getTriple().getOS() != llvm::Triple::Solaris) 6305 Builder.defineMacro("__sparcv8__"); 6306 break; 6307 case CG_V9: 6308 Builder.defineMacro("__sparcv9"); 6309 if (getTriple().getOS() != llvm::Triple::Solaris) { 6310 Builder.defineMacro("__sparcv9__"); 6311 Builder.defineMacro("__sparc_v9__"); 6312 } 6313 break; 6314 } 6315 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6316 switch (CPU) { 6317 case CK_MYRIAD2_1: 6318 Builder.defineMacro("__myriad2", "1"); 6319 Builder.defineMacro("__myriad2__", "1"); 6320 break; 6321 case CK_MYRIAD2_2: 6322 Builder.defineMacro("__myriad2", "2"); 6323 Builder.defineMacro("__myriad2__", "2"); 6324 break; 6325 default: 6326 break; 6327 } 6328 } 6329 } 6330 }; 6331 6332 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6333 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6334 public: 6335 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 6336 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6337 BigEndian = false; 6338 } 6339 }; 6340 6341 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6342 class SparcV9TargetInfo : public SparcTargetInfo { 6343 public: 6344 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6345 // FIXME: Support Sparc quad-precision long double? 6346 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6347 // This is an LP64 platform. 6348 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6349 6350 // OpenBSD uses long long for int64_t and intmax_t. 6351 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6352 IntMaxType = SignedLongLong; 6353 else 6354 IntMaxType = SignedLong; 6355 Int64Type = IntMaxType; 6356 6357 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6358 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6359 LongDoubleWidth = 128; 6360 LongDoubleAlign = 128; 6361 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6362 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6363 } 6364 6365 void getTargetDefines(const LangOptions &Opts, 6366 MacroBuilder &Builder) const override { 6367 SparcTargetInfo::getTargetDefines(Opts, Builder); 6368 Builder.defineMacro("__sparcv9"); 6369 Builder.defineMacro("__arch64__"); 6370 // Solaris doesn't need these variants, but the BSDs do. 6371 if (getTriple().getOS() != llvm::Triple::Solaris) { 6372 Builder.defineMacro("__sparc64__"); 6373 Builder.defineMacro("__sparc_v9__"); 6374 Builder.defineMacro("__sparcv9__"); 6375 } 6376 } 6377 6378 bool setCPU(const std::string &Name) override { 6379 if (!SparcTargetInfo::setCPU(Name)) 6380 return false; 6381 return getCPUGeneration(CPU) == CG_V9; 6382 } 6383 }; 6384 6385 class SystemZTargetInfo : public TargetInfo { 6386 static const Builtin::Info BuiltinInfo[]; 6387 static const char *const GCCRegNames[]; 6388 std::string CPU; 6389 bool HasTransactionalExecution; 6390 bool HasVector; 6391 6392 public: 6393 SystemZTargetInfo(const llvm::Triple &Triple) 6394 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6395 HasVector(false) { 6396 IntMaxType = SignedLong; 6397 Int64Type = SignedLong; 6398 TLSSupported = true; 6399 IntWidth = IntAlign = 32; 6400 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6401 PointerWidth = PointerAlign = 64; 6402 LongDoubleWidth = 128; 6403 LongDoubleAlign = 64; 6404 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6405 DefaultAlignForAttributeAligned = 64; 6406 MinGlobalAlign = 16; 6407 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6408 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6409 } 6410 void getTargetDefines(const LangOptions &Opts, 6411 MacroBuilder &Builder) const override { 6412 Builder.defineMacro("__s390__"); 6413 Builder.defineMacro("__s390x__"); 6414 Builder.defineMacro("__zarch__"); 6415 Builder.defineMacro("__LONG_DOUBLE_128__"); 6416 6417 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6418 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6419 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6420 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6421 6422 if (HasTransactionalExecution) 6423 Builder.defineMacro("__HTM__"); 6424 if (Opts.ZVector) 6425 Builder.defineMacro("__VEC__", "10301"); 6426 } 6427 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6428 return llvm::makeArrayRef(BuiltinInfo, 6429 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6430 } 6431 6432 ArrayRef<const char *> getGCCRegNames() const override; 6433 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6434 // No aliases. 6435 return None; 6436 } 6437 bool validateAsmConstraint(const char *&Name, 6438 TargetInfo::ConstraintInfo &info) const override; 6439 const char *getClobbers() const override { 6440 // FIXME: Is this really right? 6441 return ""; 6442 } 6443 BuiltinVaListKind getBuiltinVaListKind() const override { 6444 return TargetInfo::SystemZBuiltinVaList; 6445 } 6446 bool setCPU(const std::string &Name) override { 6447 CPU = Name; 6448 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6449 .Case("z10", true) 6450 .Case("z196", true) 6451 .Case("zEC12", true) 6452 .Case("z13", true) 6453 .Default(false); 6454 6455 return CPUKnown; 6456 } 6457 bool 6458 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6459 StringRef CPU, 6460 const std::vector<std::string> &FeaturesVec) const override { 6461 if (CPU == "zEC12") 6462 Features["transactional-execution"] = true; 6463 if (CPU == "z13") { 6464 Features["transactional-execution"] = true; 6465 Features["vector"] = true; 6466 } 6467 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6468 } 6469 6470 bool handleTargetFeatures(std::vector<std::string> &Features, 6471 DiagnosticsEngine &Diags) override { 6472 HasTransactionalExecution = false; 6473 for (const auto &Feature : Features) { 6474 if (Feature == "+transactional-execution") 6475 HasTransactionalExecution = true; 6476 else if (Feature == "+vector") 6477 HasVector = true; 6478 } 6479 // If we use the vector ABI, vector types are 64-bit aligned. 6480 if (HasVector) { 6481 MaxVectorAlign = 64; 6482 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6483 "-v128:64-a:8:16-n32:64"); 6484 } 6485 return true; 6486 } 6487 6488 bool hasFeature(StringRef Feature) const override { 6489 return llvm::StringSwitch<bool>(Feature) 6490 .Case("systemz", true) 6491 .Case("htm", HasTransactionalExecution) 6492 .Case("vx", HasVector) 6493 .Default(false); 6494 } 6495 6496 StringRef getABI() const override { 6497 if (HasVector) 6498 return "vector"; 6499 return ""; 6500 } 6501 6502 bool useFloat128ManglingForLongDouble() const override { 6503 return true; 6504 } 6505 }; 6506 6507 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6508 #define BUILTIN(ID, TYPE, ATTRS) \ 6509 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6510 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6511 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6512 #include "clang/Basic/BuiltinsSystemZ.def" 6513 }; 6514 6515 const char *const SystemZTargetInfo::GCCRegNames[] = { 6516 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6517 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6518 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6519 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6520 }; 6521 6522 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6523 return llvm::makeArrayRef(GCCRegNames); 6524 } 6525 6526 bool SystemZTargetInfo:: 6527 validateAsmConstraint(const char *&Name, 6528 TargetInfo::ConstraintInfo &Info) const { 6529 switch (*Name) { 6530 default: 6531 return false; 6532 6533 case 'a': // Address register 6534 case 'd': // Data register (equivalent to 'r') 6535 case 'f': // Floating-point register 6536 Info.setAllowsRegister(); 6537 return true; 6538 6539 case 'I': // Unsigned 8-bit constant 6540 case 'J': // Unsigned 12-bit constant 6541 case 'K': // Signed 16-bit constant 6542 case 'L': // Signed 20-bit displacement (on all targets we support) 6543 case 'M': // 0x7fffffff 6544 return true; 6545 6546 case 'Q': // Memory with base and unsigned 12-bit displacement 6547 case 'R': // Likewise, plus an index 6548 case 'S': // Memory with base and signed 20-bit displacement 6549 case 'T': // Likewise, plus an index 6550 Info.setAllowsMemory(); 6551 return true; 6552 } 6553 } 6554 6555 class MSP430TargetInfo : public TargetInfo { 6556 static const char *const GCCRegNames[]; 6557 6558 public: 6559 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6560 BigEndian = false; 6561 TLSSupported = false; 6562 IntWidth = 16; 6563 IntAlign = 16; 6564 LongWidth = 32; 6565 LongLongWidth = 64; 6566 LongAlign = LongLongAlign = 16; 6567 PointerWidth = 16; 6568 PointerAlign = 16; 6569 SuitableAlign = 16; 6570 SizeType = UnsignedInt; 6571 IntMaxType = SignedLongLong; 6572 IntPtrType = SignedInt; 6573 PtrDiffType = SignedInt; 6574 SigAtomicType = SignedLong; 6575 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6576 } 6577 void getTargetDefines(const LangOptions &Opts, 6578 MacroBuilder &Builder) const override { 6579 Builder.defineMacro("MSP430"); 6580 Builder.defineMacro("__MSP430__"); 6581 // FIXME: defines for different 'flavours' of MCU 6582 } 6583 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6584 // FIXME: Implement. 6585 return None; 6586 } 6587 bool hasFeature(StringRef Feature) const override { 6588 return Feature == "msp430"; 6589 } 6590 ArrayRef<const char *> getGCCRegNames() const override; 6591 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6592 // No aliases. 6593 return None; 6594 } 6595 bool validateAsmConstraint(const char *&Name, 6596 TargetInfo::ConstraintInfo &info) const override { 6597 // FIXME: implement 6598 switch (*Name) { 6599 case 'K': // the constant 1 6600 case 'L': // constant -1^20 .. 1^19 6601 case 'M': // constant 1-4: 6602 return true; 6603 } 6604 // No target constraints for now. 6605 return false; 6606 } 6607 const char *getClobbers() const override { 6608 // FIXME: Is this really right? 6609 return ""; 6610 } 6611 BuiltinVaListKind getBuiltinVaListKind() const override { 6612 // FIXME: implement 6613 return TargetInfo::CharPtrBuiltinVaList; 6614 } 6615 }; 6616 6617 const char *const MSP430TargetInfo::GCCRegNames[] = { 6618 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6619 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6620 6621 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6622 return llvm::makeArrayRef(GCCRegNames); 6623 } 6624 6625 // LLVM and Clang cannot be used directly to output native binaries for 6626 // target, but is used to compile C code to llvm bitcode with correct 6627 // type and alignment information. 6628 // 6629 // TCE uses the llvm bitcode as input and uses it for generating customized 6630 // target processor and program binary. TCE co-design environment is 6631 // publicly available in http://tce.cs.tut.fi 6632 6633 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6634 3, // opencl_global 6635 4, // opencl_local 6636 5, // opencl_constant 6637 // FIXME: generic has to be added to the target 6638 0, // opencl_generic 6639 0, // cuda_device 6640 0, // cuda_constant 6641 0 // cuda_shared 6642 }; 6643 6644 class TCETargetInfo : public TargetInfo { 6645 public: 6646 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6647 TLSSupported = false; 6648 IntWidth = 32; 6649 LongWidth = LongLongWidth = 32; 6650 PointerWidth = 32; 6651 IntAlign = 32; 6652 LongAlign = LongLongAlign = 32; 6653 PointerAlign = 32; 6654 SuitableAlign = 32; 6655 SizeType = UnsignedInt; 6656 IntMaxType = SignedLong; 6657 IntPtrType = SignedInt; 6658 PtrDiffType = SignedInt; 6659 FloatWidth = 32; 6660 FloatAlign = 32; 6661 DoubleWidth = 32; 6662 DoubleAlign = 32; 6663 LongDoubleWidth = 32; 6664 LongDoubleAlign = 32; 6665 FloatFormat = &llvm::APFloat::IEEEsingle; 6666 DoubleFormat = &llvm::APFloat::IEEEsingle; 6667 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6668 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 6669 "-f64:32-v64:32-v128:32-a:0:32-n32"); 6670 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6671 UseAddrSpaceMapMangling = true; 6672 } 6673 6674 void getTargetDefines(const LangOptions &Opts, 6675 MacroBuilder &Builder) const override { 6676 DefineStd(Builder, "tce", Opts); 6677 Builder.defineMacro("__TCE__"); 6678 Builder.defineMacro("__TCE_V1__"); 6679 } 6680 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6681 6682 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6683 const char *getClobbers() const override { return ""; } 6684 BuiltinVaListKind getBuiltinVaListKind() const override { 6685 return TargetInfo::VoidPtrBuiltinVaList; 6686 } 6687 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6688 bool validateAsmConstraint(const char *&Name, 6689 TargetInfo::ConstraintInfo &info) const override { 6690 return true; 6691 } 6692 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6693 return None; 6694 } 6695 }; 6696 6697 class BPFTargetInfo : public TargetInfo { 6698 public: 6699 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6700 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6701 SizeType = UnsignedLong; 6702 PtrDiffType = SignedLong; 6703 IntPtrType = SignedLong; 6704 IntMaxType = SignedLong; 6705 Int64Type = SignedLong; 6706 RegParmMax = 5; 6707 if (Triple.getArch() == llvm::Triple::bpfeb) { 6708 BigEndian = true; 6709 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 6710 } else { 6711 BigEndian = false; 6712 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 6713 } 6714 MaxAtomicPromoteWidth = 64; 6715 MaxAtomicInlineWidth = 64; 6716 TLSSupported = false; 6717 } 6718 void getTargetDefines(const LangOptions &Opts, 6719 MacroBuilder &Builder) const override { 6720 DefineStd(Builder, "bpf", Opts); 6721 Builder.defineMacro("__BPF__"); 6722 } 6723 bool hasFeature(StringRef Feature) const override { 6724 return Feature == "bpf"; 6725 } 6726 6727 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6728 const char *getClobbers() const override { 6729 return ""; 6730 } 6731 BuiltinVaListKind getBuiltinVaListKind() const override { 6732 return TargetInfo::VoidPtrBuiltinVaList; 6733 } 6734 ArrayRef<const char *> getGCCRegNames() const override { 6735 return None; 6736 } 6737 bool validateAsmConstraint(const char *&Name, 6738 TargetInfo::ConstraintInfo &info) const override { 6739 return true; 6740 } 6741 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6742 return None; 6743 } 6744 }; 6745 6746 class MipsTargetInfoBase : public TargetInfo { 6747 virtual void setDataLayout() = 0; 6748 6749 static const Builtin::Info BuiltinInfo[]; 6750 std::string CPU; 6751 bool IsMips16; 6752 bool IsMicromips; 6753 bool IsNan2008; 6754 bool IsSingleFloat; 6755 enum MipsFloatABI { 6756 HardFloat, SoftFloat 6757 } FloatABI; 6758 enum DspRevEnum { 6759 NoDSP, DSP1, DSP2 6760 } DspRev; 6761 bool HasMSA; 6762 6763 protected: 6764 bool HasFP64; 6765 std::string ABI; 6766 6767 public: 6768 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6769 const std::string &CPUStr) 6770 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6771 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6772 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6773 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6774 } 6775 6776 bool isNaN2008Default() const { 6777 return CPU == "mips32r6" || CPU == "mips64r6"; 6778 } 6779 6780 bool isFP64Default() const { 6781 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6782 } 6783 6784 bool isNan2008() const override { 6785 return IsNan2008; 6786 } 6787 6788 StringRef getABI() const override { return ABI; } 6789 bool setCPU(const std::string &Name) override { 6790 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6791 getTriple().getArch() == llvm::Triple::mipsel; 6792 CPU = Name; 6793 return llvm::StringSwitch<bool>(Name) 6794 .Case("mips1", IsMips32) 6795 .Case("mips2", IsMips32) 6796 .Case("mips3", true) 6797 .Case("mips4", true) 6798 .Case("mips5", true) 6799 .Case("mips32", IsMips32) 6800 .Case("mips32r2", IsMips32) 6801 .Case("mips32r3", IsMips32) 6802 .Case("mips32r5", IsMips32) 6803 .Case("mips32r6", IsMips32) 6804 .Case("mips64", true) 6805 .Case("mips64r2", true) 6806 .Case("mips64r3", true) 6807 .Case("mips64r5", true) 6808 .Case("mips64r6", true) 6809 .Case("octeon", true) 6810 .Case("p5600", true) 6811 .Default(false); 6812 } 6813 const std::string& getCPU() const { return CPU; } 6814 bool 6815 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6816 StringRef CPU, 6817 const std::vector<std::string> &FeaturesVec) const override { 6818 if (CPU.empty()) 6819 CPU = getCPU(); 6820 if (CPU == "octeon") 6821 Features["mips64r2"] = Features["cnmips"] = true; 6822 else 6823 Features[CPU] = true; 6824 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6825 } 6826 6827 void getTargetDefines(const LangOptions &Opts, 6828 MacroBuilder &Builder) const override { 6829 Builder.defineMacro("__mips__"); 6830 Builder.defineMacro("_mips"); 6831 if (Opts.GNUMode) 6832 Builder.defineMacro("mips"); 6833 6834 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6835 6836 switch (FloatABI) { 6837 case HardFloat: 6838 Builder.defineMacro("__mips_hard_float", Twine(1)); 6839 break; 6840 case SoftFloat: 6841 Builder.defineMacro("__mips_soft_float", Twine(1)); 6842 break; 6843 } 6844 6845 if (IsSingleFloat) 6846 Builder.defineMacro("__mips_single_float", Twine(1)); 6847 6848 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6849 Builder.defineMacro("_MIPS_FPSET", 6850 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6851 6852 if (IsMips16) 6853 Builder.defineMacro("__mips16", Twine(1)); 6854 6855 if (IsMicromips) 6856 Builder.defineMacro("__mips_micromips", Twine(1)); 6857 6858 if (IsNan2008) 6859 Builder.defineMacro("__mips_nan2008", Twine(1)); 6860 6861 switch (DspRev) { 6862 default: 6863 break; 6864 case DSP1: 6865 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6866 Builder.defineMacro("__mips_dsp", Twine(1)); 6867 break; 6868 case DSP2: 6869 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6870 Builder.defineMacro("__mips_dspr2", Twine(1)); 6871 Builder.defineMacro("__mips_dsp", Twine(1)); 6872 break; 6873 } 6874 6875 if (HasMSA) 6876 Builder.defineMacro("__mips_msa", Twine(1)); 6877 6878 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6879 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6880 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6881 6882 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6883 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6884 6885 // These shouldn't be defined for MIPS-I but there's no need to check 6886 // for that since MIPS-I isn't supported. 6887 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6888 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6889 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6890 } 6891 6892 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6893 return llvm::makeArrayRef(BuiltinInfo, 6894 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 6895 } 6896 bool hasFeature(StringRef Feature) const override { 6897 return llvm::StringSwitch<bool>(Feature) 6898 .Case("mips", true) 6899 .Case("fp64", HasFP64) 6900 .Default(false); 6901 } 6902 BuiltinVaListKind getBuiltinVaListKind() const override { 6903 return TargetInfo::VoidPtrBuiltinVaList; 6904 } 6905 ArrayRef<const char *> getGCCRegNames() const override { 6906 static const char *const GCCRegNames[] = { 6907 // CPU register names 6908 // Must match second column of GCCRegAliases 6909 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6910 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6911 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6912 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6913 // Floating point register names 6914 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6915 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6916 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6917 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6918 // Hi/lo and condition register names 6919 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6920 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 6921 "$ac3hi","$ac3lo", 6922 // MSA register names 6923 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6924 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6925 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6926 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6927 // MSA control register names 6928 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6929 "$msarequest", "$msamap", "$msaunmap" 6930 }; 6931 return llvm::makeArrayRef(GCCRegNames); 6932 } 6933 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 6934 bool validateAsmConstraint(const char *&Name, 6935 TargetInfo::ConstraintInfo &Info) const override { 6936 switch (*Name) { 6937 default: 6938 return false; 6939 case 'r': // CPU registers. 6940 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6941 case 'y': // Equivalent to "r", backward compatibility only. 6942 case 'f': // floating-point registers. 6943 case 'c': // $25 for indirect jumps 6944 case 'l': // lo register 6945 case 'x': // hilo register pair 6946 Info.setAllowsRegister(); 6947 return true; 6948 case 'I': // Signed 16-bit constant 6949 case 'J': // Integer 0 6950 case 'K': // Unsigned 16-bit constant 6951 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6952 case 'M': // Constants not loadable via lui, addiu, or ori 6953 case 'N': // Constant -1 to -65535 6954 case 'O': // A signed 15-bit constant 6955 case 'P': // A constant between 1 go 65535 6956 return true; 6957 case 'R': // An address that can be used in a non-macro load or store 6958 Info.setAllowsMemory(); 6959 return true; 6960 case 'Z': 6961 if (Name[1] == 'C') { // An address usable by ll, and sc. 6962 Info.setAllowsMemory(); 6963 Name++; // Skip over 'Z'. 6964 return true; 6965 } 6966 return false; 6967 } 6968 } 6969 6970 std::string convertConstraint(const char *&Constraint) const override { 6971 std::string R; 6972 switch (*Constraint) { 6973 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6974 if (Constraint[1] == 'C') { 6975 R = std::string("^") + std::string(Constraint, 2); 6976 Constraint++; 6977 return R; 6978 } 6979 break; 6980 } 6981 return TargetInfo::convertConstraint(Constraint); 6982 } 6983 6984 const char *getClobbers() const override { 6985 // In GCC, $1 is not widely used in generated code (it's used only in a few 6986 // specific situations), so there is no real need for users to add it to 6987 // the clobbers list if they want to use it in their inline assembly code. 6988 // 6989 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6990 // code generation, so using it in inline assembly without adding it to the 6991 // clobbers list can cause conflicts between the inline assembly code and 6992 // the surrounding generated code. 6993 // 6994 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6995 // operands, which will conflict with the ".set at" assembler option (which 6996 // we use only for inline assembly, in order to maintain compatibility with 6997 // GCC) and will also conflict with the user's usage of $1. 6998 // 6999 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7000 // register for generated code is to automatically clobber $1 for all inline 7001 // assembly code. 7002 // 7003 // FIXME: We should automatically clobber $1 only for inline assembly code 7004 // which actually uses it. This would allow LLVM to use $1 for inline 7005 // assembly operands if the user's assembly code doesn't use it. 7006 return "~{$1}"; 7007 } 7008 7009 bool handleTargetFeatures(std::vector<std::string> &Features, 7010 DiagnosticsEngine &Diags) override { 7011 IsMips16 = false; 7012 IsMicromips = false; 7013 IsNan2008 = isNaN2008Default(); 7014 IsSingleFloat = false; 7015 FloatABI = HardFloat; 7016 DspRev = NoDSP; 7017 HasFP64 = isFP64Default(); 7018 7019 for (const auto &Feature : Features) { 7020 if (Feature == "+single-float") 7021 IsSingleFloat = true; 7022 else if (Feature == "+soft-float") 7023 FloatABI = SoftFloat; 7024 else if (Feature == "+mips16") 7025 IsMips16 = true; 7026 else if (Feature == "+micromips") 7027 IsMicromips = true; 7028 else if (Feature == "+dsp") 7029 DspRev = std::max(DspRev, DSP1); 7030 else if (Feature == "+dspr2") 7031 DspRev = std::max(DspRev, DSP2); 7032 else if (Feature == "+msa") 7033 HasMSA = true; 7034 else if (Feature == "+fp64") 7035 HasFP64 = true; 7036 else if (Feature == "-fp64") 7037 HasFP64 = false; 7038 else if (Feature == "+nan2008") 7039 IsNan2008 = true; 7040 else if (Feature == "-nan2008") 7041 IsNan2008 = false; 7042 } 7043 7044 setDataLayout(); 7045 7046 return true; 7047 } 7048 7049 int getEHDataRegisterNumber(unsigned RegNo) const override { 7050 if (RegNo == 0) return 4; 7051 if (RegNo == 1) return 5; 7052 return -1; 7053 } 7054 7055 bool isCLZForZeroUndef() const override { return false; } 7056 }; 7057 7058 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 7059 #define BUILTIN(ID, TYPE, ATTRS) \ 7060 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7061 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7062 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7063 #include "clang/Basic/BuiltinsMips.def" 7064 }; 7065 7066 class Mips32TargetInfoBase : public MipsTargetInfoBase { 7067 public: 7068 Mips32TargetInfoBase(const llvm::Triple &Triple) 7069 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 7070 SizeType = UnsignedInt; 7071 PtrDiffType = SignedInt; 7072 Int64Type = SignedLongLong; 7073 IntMaxType = Int64Type; 7074 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7075 } 7076 bool setABI(const std::string &Name) override { 7077 if (Name == "o32" || Name == "eabi") { 7078 ABI = Name; 7079 return true; 7080 } 7081 return false; 7082 } 7083 void getTargetDefines(const LangOptions &Opts, 7084 MacroBuilder &Builder) const override { 7085 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7086 7087 Builder.defineMacro("__mips", "32"); 7088 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7089 7090 const std::string& CPUStr = getCPU(); 7091 if (CPUStr == "mips32") 7092 Builder.defineMacro("__mips_isa_rev", "1"); 7093 else if (CPUStr == "mips32r2") 7094 Builder.defineMacro("__mips_isa_rev", "2"); 7095 else if (CPUStr == "mips32r3") 7096 Builder.defineMacro("__mips_isa_rev", "3"); 7097 else if (CPUStr == "mips32r5") 7098 Builder.defineMacro("__mips_isa_rev", "5"); 7099 else if (CPUStr == "mips32r6") 7100 Builder.defineMacro("__mips_isa_rev", "6"); 7101 7102 if (ABI == "o32") { 7103 Builder.defineMacro("__mips_o32"); 7104 Builder.defineMacro("_ABIO32", "1"); 7105 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7106 } 7107 else if (ABI == "eabi") 7108 Builder.defineMacro("__mips_eabi"); 7109 else 7110 llvm_unreachable("Invalid ABI for Mips32."); 7111 } 7112 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7113 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7114 { { "at" }, "$1" }, 7115 { { "v0" }, "$2" }, 7116 { { "v1" }, "$3" }, 7117 { { "a0" }, "$4" }, 7118 { { "a1" }, "$5" }, 7119 { { "a2" }, "$6" }, 7120 { { "a3" }, "$7" }, 7121 { { "t0" }, "$8" }, 7122 { { "t1" }, "$9" }, 7123 { { "t2" }, "$10" }, 7124 { { "t3" }, "$11" }, 7125 { { "t4" }, "$12" }, 7126 { { "t5" }, "$13" }, 7127 { { "t6" }, "$14" }, 7128 { { "t7" }, "$15" }, 7129 { { "s0" }, "$16" }, 7130 { { "s1" }, "$17" }, 7131 { { "s2" }, "$18" }, 7132 { { "s3" }, "$19" }, 7133 { { "s4" }, "$20" }, 7134 { { "s5" }, "$21" }, 7135 { { "s6" }, "$22" }, 7136 { { "s7" }, "$23" }, 7137 { { "t8" }, "$24" }, 7138 { { "t9" }, "$25" }, 7139 { { "k0" }, "$26" }, 7140 { { "k1" }, "$27" }, 7141 { { "gp" }, "$28" }, 7142 { { "sp","$sp" }, "$29" }, 7143 { { "fp","$fp" }, "$30" }, 7144 { { "ra" }, "$31" } 7145 }; 7146 return llvm::makeArrayRef(GCCRegAliases); 7147 } 7148 }; 7149 7150 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 7151 void setDataLayout() override { 7152 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7153 } 7154 7155 public: 7156 Mips32EBTargetInfo(const llvm::Triple &Triple) 7157 : Mips32TargetInfoBase(Triple) { 7158 } 7159 void getTargetDefines(const LangOptions &Opts, 7160 MacroBuilder &Builder) const override { 7161 DefineStd(Builder, "MIPSEB", Opts); 7162 Builder.defineMacro("_MIPSEB"); 7163 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7164 } 7165 }; 7166 7167 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 7168 void setDataLayout() override { 7169 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7170 } 7171 7172 public: 7173 Mips32ELTargetInfo(const llvm::Triple &Triple) 7174 : Mips32TargetInfoBase(Triple) { 7175 BigEndian = false; 7176 } 7177 void getTargetDefines(const LangOptions &Opts, 7178 MacroBuilder &Builder) const override { 7179 DefineStd(Builder, "MIPSEL", Opts); 7180 Builder.defineMacro("_MIPSEL"); 7181 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7182 } 7183 }; 7184 7185 class Mips64TargetInfoBase : public MipsTargetInfoBase { 7186 public: 7187 Mips64TargetInfoBase(const llvm::Triple &Triple) 7188 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 7189 LongDoubleWidth = LongDoubleAlign = 128; 7190 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7191 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7192 LongDoubleWidth = LongDoubleAlign = 64; 7193 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7194 } 7195 setN64ABITypes(); 7196 SuitableAlign = 128; 7197 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7198 } 7199 7200 void setN64ABITypes() { 7201 LongWidth = LongAlign = 64; 7202 PointerWidth = PointerAlign = 64; 7203 SizeType = UnsignedLong; 7204 PtrDiffType = SignedLong; 7205 Int64Type = SignedLong; 7206 IntMaxType = Int64Type; 7207 } 7208 7209 void setN32ABITypes() { 7210 LongWidth = LongAlign = 32; 7211 PointerWidth = PointerAlign = 32; 7212 SizeType = UnsignedInt; 7213 PtrDiffType = SignedInt; 7214 Int64Type = SignedLongLong; 7215 IntMaxType = Int64Type; 7216 } 7217 7218 bool setABI(const std::string &Name) override { 7219 if (Name == "n32") { 7220 setN32ABITypes(); 7221 ABI = Name; 7222 return true; 7223 } 7224 if (Name == "n64") { 7225 setN64ABITypes(); 7226 ABI = Name; 7227 return true; 7228 } 7229 return false; 7230 } 7231 7232 void getTargetDefines(const LangOptions &Opts, 7233 MacroBuilder &Builder) const override { 7234 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7235 7236 Builder.defineMacro("__mips", "64"); 7237 Builder.defineMacro("__mips64"); 7238 Builder.defineMacro("__mips64__"); 7239 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7240 7241 const std::string& CPUStr = getCPU(); 7242 if (CPUStr == "mips64") 7243 Builder.defineMacro("__mips_isa_rev", "1"); 7244 else if (CPUStr == "mips64r2") 7245 Builder.defineMacro("__mips_isa_rev", "2"); 7246 else if (CPUStr == "mips64r3") 7247 Builder.defineMacro("__mips_isa_rev", "3"); 7248 else if (CPUStr == "mips64r5") 7249 Builder.defineMacro("__mips_isa_rev", "5"); 7250 else if (CPUStr == "mips64r6") 7251 Builder.defineMacro("__mips_isa_rev", "6"); 7252 7253 if (ABI == "n32") { 7254 Builder.defineMacro("__mips_n32"); 7255 Builder.defineMacro("_ABIN32", "2"); 7256 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7257 } 7258 else if (ABI == "n64") { 7259 Builder.defineMacro("__mips_n64"); 7260 Builder.defineMacro("_ABI64", "3"); 7261 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7262 } 7263 else 7264 llvm_unreachable("Invalid ABI for Mips64."); 7265 7266 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7267 } 7268 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7269 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7270 { { "at" }, "$1" }, 7271 { { "v0" }, "$2" }, 7272 { { "v1" }, "$3" }, 7273 { { "a0" }, "$4" }, 7274 { { "a1" }, "$5" }, 7275 { { "a2" }, "$6" }, 7276 { { "a3" }, "$7" }, 7277 { { "a4" }, "$8" }, 7278 { { "a5" }, "$9" }, 7279 { { "a6" }, "$10" }, 7280 { { "a7" }, "$11" }, 7281 { { "t0" }, "$12" }, 7282 { { "t1" }, "$13" }, 7283 { { "t2" }, "$14" }, 7284 { { "t3" }, "$15" }, 7285 { { "s0" }, "$16" }, 7286 { { "s1" }, "$17" }, 7287 { { "s2" }, "$18" }, 7288 { { "s3" }, "$19" }, 7289 { { "s4" }, "$20" }, 7290 { { "s5" }, "$21" }, 7291 { { "s6" }, "$22" }, 7292 { { "s7" }, "$23" }, 7293 { { "t8" }, "$24" }, 7294 { { "t9" }, "$25" }, 7295 { { "k0" }, "$26" }, 7296 { { "k1" }, "$27" }, 7297 { { "gp" }, "$28" }, 7298 { { "sp","$sp" }, "$29" }, 7299 { { "fp","$fp" }, "$30" }, 7300 { { "ra" }, "$31" } 7301 }; 7302 return llvm::makeArrayRef(GCCRegAliases); 7303 } 7304 7305 bool hasInt128Type() const override { return true; } 7306 }; 7307 7308 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 7309 void setDataLayout() override { 7310 if (ABI == "n32") 7311 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7312 else 7313 resetDataLayout("E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7314 } 7315 7316 public: 7317 Mips64EBTargetInfo(const llvm::Triple &Triple) 7318 : Mips64TargetInfoBase(Triple) {} 7319 void getTargetDefines(const LangOptions &Opts, 7320 MacroBuilder &Builder) const override { 7321 DefineStd(Builder, "MIPSEB", Opts); 7322 Builder.defineMacro("_MIPSEB"); 7323 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7324 } 7325 }; 7326 7327 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 7328 void setDataLayout() override { 7329 if (ABI == "n32") 7330 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7331 else 7332 resetDataLayout("e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7333 } 7334 public: 7335 Mips64ELTargetInfo(const llvm::Triple &Triple) 7336 : Mips64TargetInfoBase(Triple) { 7337 // Default ABI is n64. 7338 BigEndian = false; 7339 } 7340 void getTargetDefines(const LangOptions &Opts, 7341 MacroBuilder &Builder) const override { 7342 DefineStd(Builder, "MIPSEL", Opts); 7343 Builder.defineMacro("_MIPSEL"); 7344 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7345 } 7346 }; 7347 7348 class PNaClTargetInfo : public TargetInfo { 7349 public: 7350 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7351 BigEndian = false; 7352 this->LongAlign = 32; 7353 this->LongWidth = 32; 7354 this->PointerAlign = 32; 7355 this->PointerWidth = 32; 7356 this->IntMaxType = TargetInfo::SignedLongLong; 7357 this->Int64Type = TargetInfo::SignedLongLong; 7358 this->DoubleAlign = 64; 7359 this->LongDoubleWidth = 64; 7360 this->LongDoubleAlign = 64; 7361 this->SizeType = TargetInfo::UnsignedInt; 7362 this->PtrDiffType = TargetInfo::SignedInt; 7363 this->IntPtrType = TargetInfo::SignedInt; 7364 this->RegParmMax = 0; // Disallow regparm 7365 } 7366 7367 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7368 Builder.defineMacro("__le32__"); 7369 Builder.defineMacro("__pnacl__"); 7370 } 7371 void getTargetDefines(const LangOptions &Opts, 7372 MacroBuilder &Builder) const override { 7373 getArchDefines(Opts, Builder); 7374 } 7375 bool hasFeature(StringRef Feature) const override { 7376 return Feature == "pnacl"; 7377 } 7378 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7379 BuiltinVaListKind getBuiltinVaListKind() const override { 7380 return TargetInfo::PNaClABIBuiltinVaList; 7381 } 7382 ArrayRef<const char *> getGCCRegNames() const override; 7383 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7384 bool validateAsmConstraint(const char *&Name, 7385 TargetInfo::ConstraintInfo &Info) const override { 7386 return false; 7387 } 7388 7389 const char *getClobbers() const override { 7390 return ""; 7391 } 7392 }; 7393 7394 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7395 return None; 7396 } 7397 7398 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7399 return None; 7400 } 7401 7402 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7403 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7404 public: 7405 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 7406 Mips32ELTargetInfo(Triple) { 7407 } 7408 7409 BuiltinVaListKind getBuiltinVaListKind() const override { 7410 return TargetInfo::PNaClABIBuiltinVaList; 7411 } 7412 }; 7413 7414 class Le64TargetInfo : public TargetInfo { 7415 static const Builtin::Info BuiltinInfo[]; 7416 7417 public: 7418 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7419 BigEndian = false; 7420 NoAsmVariants = true; 7421 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7422 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7423 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7424 } 7425 7426 void getTargetDefines(const LangOptions &Opts, 7427 MacroBuilder &Builder) const override { 7428 DefineStd(Builder, "unix", Opts); 7429 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7430 Builder.defineMacro("__ELF__"); 7431 } 7432 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7433 return llvm::makeArrayRef(BuiltinInfo, 7434 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7435 } 7436 BuiltinVaListKind getBuiltinVaListKind() const override { 7437 return TargetInfo::PNaClABIBuiltinVaList; 7438 } 7439 const char *getClobbers() const override { return ""; } 7440 ArrayRef<const char *> getGCCRegNames() const override { 7441 return None; 7442 } 7443 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7444 return None; 7445 } 7446 bool validateAsmConstraint(const char *&Name, 7447 TargetInfo::ConstraintInfo &Info) const override { 7448 return false; 7449 } 7450 7451 bool hasProtectedVisibility() const override { return false; } 7452 }; 7453 7454 class WebAssemblyTargetInfo : public TargetInfo { 7455 static const Builtin::Info BuiltinInfo[]; 7456 7457 enum SIMDEnum { 7458 NoSIMD, 7459 SIMD128, 7460 } SIMDLevel; 7461 7462 public: 7463 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 7464 : TargetInfo(T), SIMDLevel(NoSIMD) { 7465 BigEndian = false; 7466 NoAsmVariants = true; 7467 SuitableAlign = 128; 7468 LargeArrayMinWidth = 128; 7469 LargeArrayAlign = 128; 7470 SimdDefaultAlign = 128; 7471 SigAtomicType = SignedLong; 7472 LongDoubleWidth = LongDoubleAlign = 128; 7473 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7474 } 7475 7476 protected: 7477 void getTargetDefines(const LangOptions &Opts, 7478 MacroBuilder &Builder) const override { 7479 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7480 if (SIMDLevel >= SIMD128) 7481 Builder.defineMacro("__wasm_simd128__"); 7482 } 7483 7484 private: 7485 bool 7486 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7487 StringRef CPU, 7488 const std::vector<std::string> &FeaturesVec) const override { 7489 if (CPU == "bleeding-edge") 7490 Features["simd128"] = true; 7491 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7492 } 7493 bool hasFeature(StringRef Feature) const final { 7494 return llvm::StringSwitch<bool>(Feature) 7495 .Case("simd128", SIMDLevel >= SIMD128) 7496 .Default(false); 7497 } 7498 bool handleTargetFeatures(std::vector<std::string> &Features, 7499 DiagnosticsEngine &Diags) final { 7500 for (const auto &Feature : Features) { 7501 if (Feature == "+simd128") { 7502 SIMDLevel = std::max(SIMDLevel, SIMD128); 7503 continue; 7504 } 7505 if (Feature == "-simd128") { 7506 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7507 continue; 7508 } 7509 7510 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7511 << "-target-feature"; 7512 return false; 7513 } 7514 return true; 7515 } 7516 bool setCPU(const std::string &Name) final { 7517 return llvm::StringSwitch<bool>(Name) 7518 .Case("mvp", true) 7519 .Case("bleeding-edge", true) 7520 .Case("generic", true) 7521 .Default(false); 7522 } 7523 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7524 return llvm::makeArrayRef(BuiltinInfo, 7525 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7526 } 7527 BuiltinVaListKind getBuiltinVaListKind() const final { 7528 return VoidPtrBuiltinVaList; 7529 } 7530 ArrayRef<const char *> getGCCRegNames() const final { 7531 return None; 7532 } 7533 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7534 return None; 7535 } 7536 bool 7537 validateAsmConstraint(const char *&Name, 7538 TargetInfo::ConstraintInfo &Info) const final { 7539 return false; 7540 } 7541 const char *getClobbers() const final { return ""; } 7542 bool isCLZForZeroUndef() const final { return false; } 7543 bool hasInt128Type() const final { return true; } 7544 IntType getIntTypeByWidth(unsigned BitWidth, 7545 bool IsSigned) const final { 7546 // WebAssembly prefers long long for explicitly 64-bit integers. 7547 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7548 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7549 } 7550 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7551 bool IsSigned) const final { 7552 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7553 return BitWidth == 64 7554 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7555 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7556 } 7557 }; 7558 7559 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7560 #define BUILTIN(ID, TYPE, ATTRS) \ 7561 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7562 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7563 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7564 #include "clang/Basic/BuiltinsWebAssembly.def" 7565 }; 7566 7567 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7568 public: 7569 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7570 : WebAssemblyTargetInfo(T) { 7571 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7572 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7573 } 7574 7575 protected: 7576 void getTargetDefines(const LangOptions &Opts, 7577 MacroBuilder &Builder) const override { 7578 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7579 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7580 } 7581 }; 7582 7583 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7584 public: 7585 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7586 : WebAssemblyTargetInfo(T) { 7587 LongAlign = LongWidth = 64; 7588 PointerAlign = PointerWidth = 64; 7589 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7590 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7591 } 7592 7593 protected: 7594 void getTargetDefines(const LangOptions &Opts, 7595 MacroBuilder &Builder) const override { 7596 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7597 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7598 } 7599 }; 7600 7601 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7602 #define BUILTIN(ID, TYPE, ATTRS) \ 7603 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7604 #include "clang/Basic/BuiltinsLe64.def" 7605 }; 7606 7607 static const unsigned SPIRAddrSpaceMap[] = { 7608 1, // opencl_global 7609 3, // opencl_local 7610 2, // opencl_constant 7611 4, // opencl_generic 7612 0, // cuda_device 7613 0, // cuda_constant 7614 0 // cuda_shared 7615 }; 7616 class SPIRTargetInfo : public TargetInfo { 7617 public: 7618 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7619 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7620 "SPIR target must use unknown OS"); 7621 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7622 "SPIR target must use unknown environment type"); 7623 BigEndian = false; 7624 TLSSupported = false; 7625 LongWidth = LongAlign = 64; 7626 AddrSpaceMap = &SPIRAddrSpaceMap; 7627 UseAddrSpaceMapMangling = true; 7628 // Define available target features 7629 // These must be defined in sorted order! 7630 NoAsmVariants = true; 7631 } 7632 void getTargetDefines(const LangOptions &Opts, 7633 MacroBuilder &Builder) const override { 7634 DefineStd(Builder, "SPIR", Opts); 7635 } 7636 bool hasFeature(StringRef Feature) const override { 7637 return Feature == "spir"; 7638 } 7639 7640 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7641 const char *getClobbers() const override { return ""; } 7642 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7643 bool validateAsmConstraint(const char *&Name, 7644 TargetInfo::ConstraintInfo &info) const override { 7645 return true; 7646 } 7647 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7648 return None; 7649 } 7650 BuiltinVaListKind getBuiltinVaListKind() const override { 7651 return TargetInfo::VoidPtrBuiltinVaList; 7652 } 7653 7654 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7655 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7656 : CCCR_Warning; 7657 } 7658 7659 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7660 return CC_SpirFunction; 7661 } 7662 }; 7663 7664 class SPIR32TargetInfo : public SPIRTargetInfo { 7665 public: 7666 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7667 PointerWidth = PointerAlign = 32; 7668 SizeType = TargetInfo::UnsignedInt; 7669 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7670 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7671 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7672 } 7673 void getTargetDefines(const LangOptions &Opts, 7674 MacroBuilder &Builder) const override { 7675 DefineStd(Builder, "SPIR32", Opts); 7676 } 7677 }; 7678 7679 class SPIR64TargetInfo : public SPIRTargetInfo { 7680 public: 7681 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7682 PointerWidth = PointerAlign = 64; 7683 SizeType = TargetInfo::UnsignedLong; 7684 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7685 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7686 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7687 } 7688 void getTargetDefines(const LangOptions &Opts, 7689 MacroBuilder &Builder) const override { 7690 DefineStd(Builder, "SPIR64", Opts); 7691 } 7692 }; 7693 7694 class XCoreTargetInfo : public TargetInfo { 7695 static const Builtin::Info BuiltinInfo[]; 7696 public: 7697 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7698 BigEndian = false; 7699 NoAsmVariants = true; 7700 LongLongAlign = 32; 7701 SuitableAlign = 32; 7702 DoubleAlign = LongDoubleAlign = 32; 7703 SizeType = UnsignedInt; 7704 PtrDiffType = SignedInt; 7705 IntPtrType = SignedInt; 7706 WCharType = UnsignedChar; 7707 WIntType = UnsignedInt; 7708 UseZeroLengthBitfieldAlignment = true; 7709 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7710 "-f64:32-a:0:32-n32"); 7711 } 7712 void getTargetDefines(const LangOptions &Opts, 7713 MacroBuilder &Builder) const override { 7714 Builder.defineMacro("__XS1B__"); 7715 } 7716 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7717 return llvm::makeArrayRef(BuiltinInfo, 7718 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7719 } 7720 BuiltinVaListKind getBuiltinVaListKind() const override { 7721 return TargetInfo::VoidPtrBuiltinVaList; 7722 } 7723 const char *getClobbers() const override { 7724 return ""; 7725 } 7726 ArrayRef<const char *> getGCCRegNames() const override { 7727 static const char * const GCCRegNames[] = { 7728 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7729 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7730 }; 7731 return llvm::makeArrayRef(GCCRegNames); 7732 } 7733 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7734 return None; 7735 } 7736 bool validateAsmConstraint(const char *&Name, 7737 TargetInfo::ConstraintInfo &Info) const override { 7738 return false; 7739 } 7740 int getEHDataRegisterNumber(unsigned RegNo) const override { 7741 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7742 return (RegNo < 2)? RegNo : -1; 7743 } 7744 bool allowsLargerPreferedTypeAlignment() const override { 7745 return false; 7746 } 7747 }; 7748 7749 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7750 #define BUILTIN(ID, TYPE, ATTRS) \ 7751 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7752 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7753 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7754 #include "clang/Basic/BuiltinsXCore.def" 7755 }; 7756 7757 // x86_32 Android target 7758 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7759 public: 7760 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7761 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7762 SuitableAlign = 32; 7763 LongDoubleWidth = 64; 7764 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7765 } 7766 }; 7767 7768 // x86_64 Android target 7769 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7770 public: 7771 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7772 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7773 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7774 } 7775 7776 bool useFloat128ManglingForLongDouble() const override { 7777 return true; 7778 } 7779 }; 7780 } // end anonymous namespace 7781 7782 //===----------------------------------------------------------------------===// 7783 // Driver code 7784 //===----------------------------------------------------------------------===// 7785 7786 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7787 llvm::Triple::OSType os = Triple.getOS(); 7788 7789 switch (Triple.getArch()) { 7790 default: 7791 return nullptr; 7792 7793 case llvm::Triple::xcore: 7794 return new XCoreTargetInfo(Triple); 7795 7796 case llvm::Triple::hexagon: 7797 return new HexagonTargetInfo(Triple); 7798 7799 case llvm::Triple::lanai: 7800 return new LanaiTargetInfo(Triple); 7801 7802 case llvm::Triple::aarch64: 7803 if (Triple.isOSDarwin()) 7804 return new DarwinAArch64TargetInfo(Triple); 7805 7806 switch (os) { 7807 case llvm::Triple::CloudABI: 7808 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple); 7809 case llvm::Triple::FreeBSD: 7810 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7811 case llvm::Triple::Linux: 7812 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7813 case llvm::Triple::NetBSD: 7814 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7815 default: 7816 return new AArch64leTargetInfo(Triple); 7817 } 7818 7819 case llvm::Triple::aarch64_be: 7820 switch (os) { 7821 case llvm::Triple::FreeBSD: 7822 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7823 case llvm::Triple::Linux: 7824 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7825 case llvm::Triple::NetBSD: 7826 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7827 default: 7828 return new AArch64beTargetInfo(Triple); 7829 } 7830 7831 case llvm::Triple::arm: 7832 case llvm::Triple::thumb: 7833 if (Triple.isOSBinFormatMachO()) 7834 return new DarwinARMTargetInfo(Triple); 7835 7836 switch (os) { 7837 case llvm::Triple::Linux: 7838 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7839 case llvm::Triple::FreeBSD: 7840 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7841 case llvm::Triple::NetBSD: 7842 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7843 case llvm::Triple::OpenBSD: 7844 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7845 case llvm::Triple::Bitrig: 7846 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7847 case llvm::Triple::RTEMS: 7848 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7849 case llvm::Triple::NaCl: 7850 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7851 case llvm::Triple::Win32: 7852 switch (Triple.getEnvironment()) { 7853 case llvm::Triple::Cygnus: 7854 return new CygwinARMTargetInfo(Triple); 7855 case llvm::Triple::GNU: 7856 return new MinGWARMTargetInfo(Triple); 7857 case llvm::Triple::Itanium: 7858 return new ItaniumWindowsARMleTargetInfo(Triple); 7859 case llvm::Triple::MSVC: 7860 default: // Assume MSVC for unknown environments 7861 return new MicrosoftARMleTargetInfo(Triple); 7862 } 7863 default: 7864 return new ARMleTargetInfo(Triple); 7865 } 7866 7867 case llvm::Triple::armeb: 7868 case llvm::Triple::thumbeb: 7869 if (Triple.isOSDarwin()) 7870 return new DarwinARMTargetInfo(Triple); 7871 7872 switch (os) { 7873 case llvm::Triple::Linux: 7874 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7875 case llvm::Triple::FreeBSD: 7876 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7877 case llvm::Triple::NetBSD: 7878 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7879 case llvm::Triple::OpenBSD: 7880 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7881 case llvm::Triple::Bitrig: 7882 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7883 case llvm::Triple::RTEMS: 7884 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7885 case llvm::Triple::NaCl: 7886 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7887 default: 7888 return new ARMbeTargetInfo(Triple); 7889 } 7890 7891 case llvm::Triple::bpfeb: 7892 case llvm::Triple::bpfel: 7893 return new BPFTargetInfo(Triple); 7894 7895 case llvm::Triple::msp430: 7896 return new MSP430TargetInfo(Triple); 7897 7898 case llvm::Triple::mips: 7899 switch (os) { 7900 case llvm::Triple::Linux: 7901 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7902 case llvm::Triple::RTEMS: 7903 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7904 case llvm::Triple::FreeBSD: 7905 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7906 case llvm::Triple::NetBSD: 7907 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7908 default: 7909 return new Mips32EBTargetInfo(Triple); 7910 } 7911 7912 case llvm::Triple::mipsel: 7913 switch (os) { 7914 case llvm::Triple::Linux: 7915 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7916 case llvm::Triple::RTEMS: 7917 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7918 case llvm::Triple::FreeBSD: 7919 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7920 case llvm::Triple::NetBSD: 7921 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7922 case llvm::Triple::NaCl: 7923 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7924 default: 7925 return new Mips32ELTargetInfo(Triple); 7926 } 7927 7928 case llvm::Triple::mips64: 7929 switch (os) { 7930 case llvm::Triple::Linux: 7931 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7932 case llvm::Triple::RTEMS: 7933 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7934 case llvm::Triple::FreeBSD: 7935 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7936 case llvm::Triple::NetBSD: 7937 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7938 case llvm::Triple::OpenBSD: 7939 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7940 default: 7941 return new Mips64EBTargetInfo(Triple); 7942 } 7943 7944 case llvm::Triple::mips64el: 7945 switch (os) { 7946 case llvm::Triple::Linux: 7947 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7948 case llvm::Triple::RTEMS: 7949 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7950 case llvm::Triple::FreeBSD: 7951 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7952 case llvm::Triple::NetBSD: 7953 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7954 case llvm::Triple::OpenBSD: 7955 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7956 default: 7957 return new Mips64ELTargetInfo(Triple); 7958 } 7959 7960 case llvm::Triple::le32: 7961 switch (os) { 7962 case llvm::Triple::NaCl: 7963 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7964 default: 7965 return nullptr; 7966 } 7967 7968 case llvm::Triple::le64: 7969 return new Le64TargetInfo(Triple); 7970 7971 case llvm::Triple::ppc: 7972 if (Triple.isOSDarwin()) 7973 return new DarwinPPC32TargetInfo(Triple); 7974 switch (os) { 7975 case llvm::Triple::Linux: 7976 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7977 case llvm::Triple::FreeBSD: 7978 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7979 case llvm::Triple::NetBSD: 7980 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7981 case llvm::Triple::OpenBSD: 7982 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7983 case llvm::Triple::RTEMS: 7984 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7985 default: 7986 return new PPC32TargetInfo(Triple); 7987 } 7988 7989 case llvm::Triple::ppc64: 7990 if (Triple.isOSDarwin()) 7991 return new DarwinPPC64TargetInfo(Triple); 7992 switch (os) { 7993 case llvm::Triple::Linux: 7994 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7995 case llvm::Triple::Lv2: 7996 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7997 case llvm::Triple::FreeBSD: 7998 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7999 case llvm::Triple::NetBSD: 8000 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 8001 default: 8002 return new PPC64TargetInfo(Triple); 8003 } 8004 8005 case llvm::Triple::ppc64le: 8006 switch (os) { 8007 case llvm::Triple::Linux: 8008 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 8009 case llvm::Triple::NetBSD: 8010 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 8011 default: 8012 return new PPC64TargetInfo(Triple); 8013 } 8014 8015 case llvm::Triple::nvptx: 8016 return new NVPTX32TargetInfo(Triple); 8017 case llvm::Triple::nvptx64: 8018 return new NVPTX64TargetInfo(Triple); 8019 8020 case llvm::Triple::amdgcn: 8021 case llvm::Triple::r600: 8022 return new AMDGPUTargetInfo(Triple); 8023 8024 case llvm::Triple::sparc: 8025 switch (os) { 8026 case llvm::Triple::Linux: 8027 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 8028 case llvm::Triple::Solaris: 8029 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 8030 case llvm::Triple::NetBSD: 8031 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 8032 case llvm::Triple::OpenBSD: 8033 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 8034 case llvm::Triple::RTEMS: 8035 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 8036 default: 8037 return new SparcV8TargetInfo(Triple); 8038 } 8039 8040 // The 'sparcel' architecture copies all the above cases except for Solaris. 8041 case llvm::Triple::sparcel: 8042 switch (os) { 8043 case llvm::Triple::Linux: 8044 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 8045 case llvm::Triple::NetBSD: 8046 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 8047 case llvm::Triple::OpenBSD: 8048 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 8049 case llvm::Triple::RTEMS: 8050 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 8051 default: 8052 return new SparcV8elTargetInfo(Triple); 8053 } 8054 8055 case llvm::Triple::sparcv9: 8056 switch (os) { 8057 case llvm::Triple::Linux: 8058 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 8059 case llvm::Triple::Solaris: 8060 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 8061 case llvm::Triple::NetBSD: 8062 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 8063 case llvm::Triple::OpenBSD: 8064 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 8065 case llvm::Triple::FreeBSD: 8066 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 8067 default: 8068 return new SparcV9TargetInfo(Triple); 8069 } 8070 8071 case llvm::Triple::systemz: 8072 switch (os) { 8073 case llvm::Triple::Linux: 8074 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 8075 default: 8076 return new SystemZTargetInfo(Triple); 8077 } 8078 8079 case llvm::Triple::tce: 8080 return new TCETargetInfo(Triple); 8081 8082 case llvm::Triple::x86: 8083 if (Triple.isOSDarwin()) 8084 return new DarwinI386TargetInfo(Triple); 8085 8086 switch (os) { 8087 case llvm::Triple::CloudABI: 8088 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 8089 case llvm::Triple::Linux: { 8090 switch (Triple.getEnvironment()) { 8091 default: 8092 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 8093 case llvm::Triple::Android: 8094 return new AndroidX86_32TargetInfo(Triple); 8095 } 8096 } 8097 case llvm::Triple::DragonFly: 8098 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 8099 case llvm::Triple::NetBSD: 8100 return new NetBSDI386TargetInfo(Triple); 8101 case llvm::Triple::OpenBSD: 8102 return new OpenBSDI386TargetInfo(Triple); 8103 case llvm::Triple::Bitrig: 8104 return new BitrigI386TargetInfo(Triple); 8105 case llvm::Triple::FreeBSD: 8106 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 8107 case llvm::Triple::KFreeBSD: 8108 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 8109 case llvm::Triple::Minix: 8110 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 8111 case llvm::Triple::Solaris: 8112 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 8113 case llvm::Triple::Win32: { 8114 switch (Triple.getEnvironment()) { 8115 case llvm::Triple::Cygnus: 8116 return new CygwinX86_32TargetInfo(Triple); 8117 case llvm::Triple::GNU: 8118 return new MinGWX86_32TargetInfo(Triple); 8119 case llvm::Triple::Itanium: 8120 case llvm::Triple::MSVC: 8121 default: // Assume MSVC for unknown environments 8122 return new MicrosoftX86_32TargetInfo(Triple); 8123 } 8124 } 8125 case llvm::Triple::Haiku: 8126 return new HaikuX86_32TargetInfo(Triple); 8127 case llvm::Triple::RTEMS: 8128 return new RTEMSX86_32TargetInfo(Triple); 8129 case llvm::Triple::NaCl: 8130 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 8131 case llvm::Triple::ELFIAMCU: 8132 return new MCUX86_32TargetInfo(Triple); 8133 default: 8134 return new X86_32TargetInfo(Triple); 8135 } 8136 8137 case llvm::Triple::x86_64: 8138 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8139 return new DarwinX86_64TargetInfo(Triple); 8140 8141 switch (os) { 8142 case llvm::Triple::CloudABI: 8143 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 8144 case llvm::Triple::Linux: { 8145 switch (Triple.getEnvironment()) { 8146 default: 8147 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 8148 case llvm::Triple::Android: 8149 return new AndroidX86_64TargetInfo(Triple); 8150 } 8151 } 8152 case llvm::Triple::DragonFly: 8153 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 8154 case llvm::Triple::NetBSD: 8155 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 8156 case llvm::Triple::OpenBSD: 8157 return new OpenBSDX86_64TargetInfo(Triple); 8158 case llvm::Triple::Bitrig: 8159 return new BitrigX86_64TargetInfo(Triple); 8160 case llvm::Triple::FreeBSD: 8161 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 8162 case llvm::Triple::KFreeBSD: 8163 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 8164 case llvm::Triple::Solaris: 8165 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 8166 case llvm::Triple::Win32: { 8167 switch (Triple.getEnvironment()) { 8168 case llvm::Triple::Cygnus: 8169 return new CygwinX86_64TargetInfo(Triple); 8170 case llvm::Triple::GNU: 8171 return new MinGWX86_64TargetInfo(Triple); 8172 case llvm::Triple::MSVC: 8173 default: // Assume MSVC for unknown environments 8174 return new MicrosoftX86_64TargetInfo(Triple); 8175 } 8176 } 8177 case llvm::Triple::NaCl: 8178 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 8179 case llvm::Triple::PS4: 8180 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 8181 default: 8182 return new X86_64TargetInfo(Triple); 8183 } 8184 8185 case llvm::Triple::spir: { 8186 if (Triple.getOS() != llvm::Triple::UnknownOS || 8187 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8188 return nullptr; 8189 return new SPIR32TargetInfo(Triple); 8190 } 8191 case llvm::Triple::spir64: { 8192 if (Triple.getOS() != llvm::Triple::UnknownOS || 8193 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8194 return nullptr; 8195 return new SPIR64TargetInfo(Triple); 8196 } 8197 case llvm::Triple::wasm32: 8198 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8199 return nullptr; 8200 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 8201 case llvm::Triple::wasm64: 8202 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8203 return nullptr; 8204 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 8205 } 8206 } 8207 8208 /// CreateTargetInfo - Return the target info object for the specified target 8209 /// options. 8210 TargetInfo * 8211 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8212 const std::shared_ptr<TargetOptions> &Opts) { 8213 llvm::Triple Triple(Opts->Triple); 8214 8215 // Construct the target 8216 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 8217 if (!Target) { 8218 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8219 return nullptr; 8220 } 8221 Target->TargetOpts = Opts; 8222 8223 // Set the target CPU if specified. 8224 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8225 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8226 return nullptr; 8227 } 8228 8229 // Set the target ABI if specified. 8230 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8231 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8232 return nullptr; 8233 } 8234 8235 // Set the fp math unit. 8236 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8237 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8238 return nullptr; 8239 } 8240 8241 // Compute the default target features, we need the target to handle this 8242 // because features may have dependencies on one another. 8243 llvm::StringMap<bool> Features; 8244 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8245 Opts->FeaturesAsWritten)) 8246 return nullptr; 8247 8248 // Add the features to the compile options. 8249 Opts->Features.clear(); 8250 for (const auto &F : Features) 8251 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8252 8253 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8254 return nullptr; 8255 8256 return Target.release(); 8257 } 8258