1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 } 469 if (Opts.POSIXThreads) 470 Builder.defineMacro("_REENTRANT"); 471 if (Opts.CPlusPlus) 472 Builder.defineMacro("_GNU_SOURCE"); 473 if (this->HasFloat128) 474 Builder.defineMacro("__FLOAT128__"); 475 } 476 public: 477 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 478 : OSTargetInfo<Target>(Triple, Opts) { 479 this->WIntType = TargetInfo::UnsignedInt; 480 481 switch (Triple.getArch()) { 482 default: 483 break; 484 case llvm::Triple::ppc: 485 case llvm::Triple::ppc64: 486 case llvm::Triple::ppc64le: 487 this->MCountName = "_mcount"; 488 break; 489 case llvm::Triple::x86: 490 case llvm::Triple::x86_64: 491 case llvm::Triple::systemz: 492 this->HasFloat128 = true; 493 break; 494 } 495 } 496 497 const char *getStaticInitSectionSpecifier() const override { 498 return ".text.startup"; 499 } 500 }; 501 502 // NetBSD Target 503 template<typename Target> 504 class NetBSDTargetInfo : public OSTargetInfo<Target> { 505 protected: 506 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 507 MacroBuilder &Builder) const override { 508 // NetBSD defines; list based off of gcc output 509 Builder.defineMacro("__NetBSD__"); 510 Builder.defineMacro("__unix__"); 511 Builder.defineMacro("__ELF__"); 512 if (Opts.POSIXThreads) 513 Builder.defineMacro("_POSIX_THREADS"); 514 515 switch (Triple.getArch()) { 516 default: 517 break; 518 case llvm::Triple::arm: 519 case llvm::Triple::armeb: 520 case llvm::Triple::thumb: 521 case llvm::Triple::thumbeb: 522 Builder.defineMacro("__ARM_DWARF_EH__"); 523 break; 524 } 525 } 526 public: 527 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 528 : OSTargetInfo<Target>(Triple, Opts) { 529 this->MCountName = "_mcount"; 530 } 531 }; 532 533 // OpenBSD Target 534 template<typename Target> 535 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 536 protected: 537 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 538 MacroBuilder &Builder) const override { 539 // OpenBSD defines; list based off of gcc output 540 541 Builder.defineMacro("__OpenBSD__"); 542 DefineStd(Builder, "unix", Opts); 543 Builder.defineMacro("__ELF__"); 544 if (Opts.POSIXThreads) 545 Builder.defineMacro("_REENTRANT"); 546 } 547 public: 548 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 549 : OSTargetInfo<Target>(Triple, Opts) { 550 this->TLSSupported = false; 551 552 switch (Triple.getArch()) { 553 default: 554 case llvm::Triple::x86: 555 case llvm::Triple::x86_64: 556 case llvm::Triple::arm: 557 case llvm::Triple::sparc: 558 this->MCountName = "__mcount"; 559 break; 560 case llvm::Triple::mips64: 561 case llvm::Triple::mips64el: 562 case llvm::Triple::ppc: 563 case llvm::Triple::sparcv9: 564 this->MCountName = "_mcount"; 565 break; 566 } 567 } 568 }; 569 570 // Bitrig Target 571 template<typename Target> 572 class BitrigTargetInfo : public OSTargetInfo<Target> { 573 protected: 574 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 575 MacroBuilder &Builder) const override { 576 // Bitrig defines; list based off of gcc output 577 578 Builder.defineMacro("__Bitrig__"); 579 DefineStd(Builder, "unix", Opts); 580 Builder.defineMacro("__ELF__"); 581 if (Opts.POSIXThreads) 582 Builder.defineMacro("_REENTRANT"); 583 584 switch (Triple.getArch()) { 585 default: 586 break; 587 case llvm::Triple::arm: 588 case llvm::Triple::armeb: 589 case llvm::Triple::thumb: 590 case llvm::Triple::thumbeb: 591 Builder.defineMacro("__ARM_DWARF_EH__"); 592 break; 593 } 594 } 595 public: 596 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 597 : OSTargetInfo<Target>(Triple, Opts) { 598 this->MCountName = "__mcount"; 599 } 600 }; 601 602 // PSP Target 603 template<typename Target> 604 class PSPTargetInfo : public OSTargetInfo<Target> { 605 protected: 606 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 607 MacroBuilder &Builder) const override { 608 // PSP defines; list based on the output of the pspdev gcc toolchain. 609 Builder.defineMacro("PSP"); 610 Builder.defineMacro("_PSP"); 611 Builder.defineMacro("__psp__"); 612 Builder.defineMacro("__ELF__"); 613 } 614 public: 615 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 616 }; 617 618 // PS3 PPU Target 619 template<typename Target> 620 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 621 protected: 622 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 623 MacroBuilder &Builder) const override { 624 // PS3 PPU defines. 625 Builder.defineMacro("__PPC__"); 626 Builder.defineMacro("__PPU__"); 627 Builder.defineMacro("__CELLOS_LV2__"); 628 Builder.defineMacro("__ELF__"); 629 Builder.defineMacro("__LP32__"); 630 Builder.defineMacro("_ARCH_PPC64"); 631 Builder.defineMacro("__powerpc64__"); 632 } 633 public: 634 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 635 : OSTargetInfo<Target>(Triple, Opts) { 636 this->LongWidth = this->LongAlign = 32; 637 this->PointerWidth = this->PointerAlign = 32; 638 this->IntMaxType = TargetInfo::SignedLongLong; 639 this->Int64Type = TargetInfo::SignedLongLong; 640 this->SizeType = TargetInfo::UnsignedInt; 641 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 642 } 643 }; 644 645 template <typename Target> 646 class PS4OSTargetInfo : public OSTargetInfo<Target> { 647 protected: 648 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 649 MacroBuilder &Builder) const override { 650 Builder.defineMacro("__FreeBSD__", "9"); 651 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 652 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 653 DefineStd(Builder, "unix", Opts); 654 Builder.defineMacro("__ELF__"); 655 Builder.defineMacro("__ORBIS__"); 656 } 657 public: 658 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 659 : OSTargetInfo<Target>(Triple, Opts) { 660 this->WCharType = this->UnsignedShort; 661 662 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 663 this->MaxTLSAlign = 256; 664 665 // On PS4, do not honor explicit bit field alignment, 666 // as in "__attribute__((aligned(2))) int b : 1;". 667 this->UseExplicitBitFieldAlignment = false; 668 669 switch (Triple.getArch()) { 670 default: 671 case llvm::Triple::x86_64: 672 this->MCountName = ".mcount"; 673 break; 674 } 675 } 676 }; 677 678 // Solaris target 679 template<typename Target> 680 class SolarisTargetInfo : public OSTargetInfo<Target> { 681 protected: 682 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 683 MacroBuilder &Builder) const override { 684 DefineStd(Builder, "sun", Opts); 685 DefineStd(Builder, "unix", Opts); 686 Builder.defineMacro("__ELF__"); 687 Builder.defineMacro("__svr4__"); 688 Builder.defineMacro("__SVR4"); 689 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 690 // newer, but to 500 for everything else. feature_test.h has a check to 691 // ensure that you are not using C99 with an old version of X/Open or C89 692 // with a new version. 693 if (Opts.C99) 694 Builder.defineMacro("_XOPEN_SOURCE", "600"); 695 else 696 Builder.defineMacro("_XOPEN_SOURCE", "500"); 697 if (Opts.CPlusPlus) 698 Builder.defineMacro("__C99FEATURES__"); 699 Builder.defineMacro("_LARGEFILE_SOURCE"); 700 Builder.defineMacro("_LARGEFILE64_SOURCE"); 701 Builder.defineMacro("__EXTENSIONS__"); 702 Builder.defineMacro("_REENTRANT"); 703 } 704 public: 705 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 706 : OSTargetInfo<Target>(Triple, Opts) { 707 this->WCharType = this->SignedInt; 708 // FIXME: WIntType should be SignedLong 709 } 710 }; 711 712 // Windows target 713 template<typename Target> 714 class WindowsTargetInfo : public OSTargetInfo<Target> { 715 protected: 716 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 717 MacroBuilder &Builder) const override { 718 Builder.defineMacro("_WIN32"); 719 } 720 void getVisualStudioDefines(const LangOptions &Opts, 721 MacroBuilder &Builder) const { 722 if (Opts.CPlusPlus) { 723 if (Opts.RTTIData) 724 Builder.defineMacro("_CPPRTTI"); 725 726 if (Opts.CXXExceptions) 727 Builder.defineMacro("_CPPUNWIND"); 728 } 729 730 if (Opts.Bool) 731 Builder.defineMacro("__BOOL_DEFINED"); 732 733 if (!Opts.CharIsSigned) 734 Builder.defineMacro("_CHAR_UNSIGNED"); 735 736 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 737 // but it works for now. 738 if (Opts.POSIXThreads) 739 Builder.defineMacro("_MT"); 740 741 if (Opts.MSCompatibilityVersion) { 742 Builder.defineMacro("_MSC_VER", 743 Twine(Opts.MSCompatibilityVersion / 100000)); 744 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 745 // FIXME We cannot encode the revision information into 32-bits 746 Builder.defineMacro("_MSC_BUILD", Twine(1)); 747 748 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 749 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 750 751 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 752 if (Opts.CPlusPlus1z) 753 Builder.defineMacro("_MSVC_LANG", "201403L"); 754 else if (Opts.CPlusPlus14) 755 Builder.defineMacro("_MSVC_LANG", "201402L"); 756 } 757 } 758 759 if (Opts.MicrosoftExt) { 760 Builder.defineMacro("_MSC_EXTENSIONS"); 761 762 if (Opts.CPlusPlus11) { 763 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 764 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 765 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 766 } 767 } 768 769 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 770 } 771 772 public: 773 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 774 : OSTargetInfo<Target>(Triple, Opts) {} 775 }; 776 777 template <typename Target> 778 class NaClTargetInfo : public OSTargetInfo<Target> { 779 protected: 780 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 781 MacroBuilder &Builder) const override { 782 if (Opts.POSIXThreads) 783 Builder.defineMacro("_REENTRANT"); 784 if (Opts.CPlusPlus) 785 Builder.defineMacro("_GNU_SOURCE"); 786 787 DefineStd(Builder, "unix", Opts); 788 Builder.defineMacro("__ELF__"); 789 Builder.defineMacro("__native_client__"); 790 } 791 792 public: 793 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 794 : OSTargetInfo<Target>(Triple, Opts) { 795 this->LongAlign = 32; 796 this->LongWidth = 32; 797 this->PointerAlign = 32; 798 this->PointerWidth = 32; 799 this->IntMaxType = TargetInfo::SignedLongLong; 800 this->Int64Type = TargetInfo::SignedLongLong; 801 this->DoubleAlign = 64; 802 this->LongDoubleWidth = 64; 803 this->LongDoubleAlign = 64; 804 this->LongLongWidth = 64; 805 this->LongLongAlign = 64; 806 this->SizeType = TargetInfo::UnsignedInt; 807 this->PtrDiffType = TargetInfo::SignedInt; 808 this->IntPtrType = TargetInfo::SignedInt; 809 // RegParmMax is inherited from the underlying architecture 810 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 811 if (Triple.getArch() == llvm::Triple::arm) { 812 // Handled in ARM's setABI(). 813 } else if (Triple.getArch() == llvm::Triple::x86) { 814 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 815 } else if (Triple.getArch() == llvm::Triple::x86_64) { 816 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 817 } else if (Triple.getArch() == llvm::Triple::mipsel) { 818 // Handled on mips' setDataLayout. 819 } else { 820 assert(Triple.getArch() == llvm::Triple::le32); 821 this->resetDataLayout("e-p:32:32-i64:64"); 822 } 823 } 824 }; 825 826 // WebAssembly target 827 template <typename Target> 828 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 829 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 830 MacroBuilder &Builder) const final { 831 // A common platform macro. 832 if (Opts.POSIXThreads) 833 Builder.defineMacro("_REENTRANT"); 834 // Follow g++ convention and predefine _GNU_SOURCE for C++. 835 if (Opts.CPlusPlus) 836 Builder.defineMacro("_GNU_SOURCE"); 837 } 838 839 // As an optimization, group static init code together in a section. 840 const char *getStaticInitSectionSpecifier() const final { 841 return ".text.__startup"; 842 } 843 844 public: 845 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 846 const TargetOptions &Opts) 847 : OSTargetInfo<Target>(Triple, Opts) { 848 this->MCountName = "__mcount"; 849 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 850 } 851 }; 852 853 //===----------------------------------------------------------------------===// 854 // Specific target implementations. 855 //===----------------------------------------------------------------------===// 856 857 // PPC abstract base class 858 class PPCTargetInfo : public TargetInfo { 859 static const Builtin::Info BuiltinInfo[]; 860 static const char * const GCCRegNames[]; 861 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 862 std::string CPU; 863 864 // Target cpu features. 865 bool HasVSX; 866 bool HasP8Vector; 867 bool HasP8Crypto; 868 bool HasDirectMove; 869 bool HasQPX; 870 bool HasHTM; 871 bool HasBPERMD; 872 bool HasExtDiv; 873 874 protected: 875 std::string ABI; 876 877 public: 878 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 879 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 880 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 881 HasBPERMD(false), HasExtDiv(false) { 882 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 883 SimdDefaultAlign = 128; 884 LongDoubleWidth = LongDoubleAlign = 128; 885 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 886 } 887 888 /// \brief Flags for architecture specific defines. 889 typedef enum { 890 ArchDefineNone = 0, 891 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 892 ArchDefinePpcgr = 1 << 1, 893 ArchDefinePpcsq = 1 << 2, 894 ArchDefine440 = 1 << 3, 895 ArchDefine603 = 1 << 4, 896 ArchDefine604 = 1 << 5, 897 ArchDefinePwr4 = 1 << 6, 898 ArchDefinePwr5 = 1 << 7, 899 ArchDefinePwr5x = 1 << 8, 900 ArchDefinePwr6 = 1 << 9, 901 ArchDefinePwr6x = 1 << 10, 902 ArchDefinePwr7 = 1 << 11, 903 ArchDefinePwr8 = 1 << 12, 904 ArchDefinePwr9 = 1 << 13, 905 ArchDefineA2 = 1 << 14, 906 ArchDefineA2q = 1 << 15 907 } ArchDefineTypes; 908 909 // Note: GCC recognizes the following additional cpus: 910 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 911 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 912 // titan, rs64. 913 bool setCPU(const std::string &Name) override { 914 bool CPUKnown = llvm::StringSwitch<bool>(Name) 915 .Case("generic", true) 916 .Case("440", true) 917 .Case("450", true) 918 .Case("601", true) 919 .Case("602", true) 920 .Case("603", true) 921 .Case("603e", true) 922 .Case("603ev", true) 923 .Case("604", true) 924 .Case("604e", true) 925 .Case("620", true) 926 .Case("630", true) 927 .Case("g3", true) 928 .Case("7400", true) 929 .Case("g4", true) 930 .Case("7450", true) 931 .Case("g4+", true) 932 .Case("750", true) 933 .Case("970", true) 934 .Case("g5", true) 935 .Case("a2", true) 936 .Case("a2q", true) 937 .Case("e500mc", true) 938 .Case("e5500", true) 939 .Case("power3", true) 940 .Case("pwr3", true) 941 .Case("power4", true) 942 .Case("pwr4", true) 943 .Case("power5", true) 944 .Case("pwr5", true) 945 .Case("power5x", true) 946 .Case("pwr5x", true) 947 .Case("power6", true) 948 .Case("pwr6", true) 949 .Case("power6x", true) 950 .Case("pwr6x", true) 951 .Case("power7", true) 952 .Case("pwr7", true) 953 .Case("power8", true) 954 .Case("pwr8", true) 955 .Case("power9", true) 956 .Case("pwr9", true) 957 .Case("powerpc", true) 958 .Case("ppc", true) 959 .Case("powerpc64", true) 960 .Case("ppc64", true) 961 .Case("powerpc64le", true) 962 .Case("ppc64le", true) 963 .Default(false); 964 965 if (CPUKnown) 966 CPU = Name; 967 968 return CPUKnown; 969 } 970 971 972 StringRef getABI() const override { return ABI; } 973 974 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 975 return llvm::makeArrayRef(BuiltinInfo, 976 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 977 } 978 979 bool isCLZForZeroUndef() const override { return false; } 980 981 void getTargetDefines(const LangOptions &Opts, 982 MacroBuilder &Builder) const override; 983 984 bool 985 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 986 StringRef CPU, 987 const std::vector<std::string> &FeaturesVec) const override; 988 989 bool handleTargetFeatures(std::vector<std::string> &Features, 990 DiagnosticsEngine &Diags) override; 991 bool hasFeature(StringRef Feature) const override; 992 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 993 bool Enabled) const override; 994 995 ArrayRef<const char *> getGCCRegNames() const override; 996 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 997 bool validateAsmConstraint(const char *&Name, 998 TargetInfo::ConstraintInfo &Info) const override { 999 switch (*Name) { 1000 default: return false; 1001 case 'O': // Zero 1002 break; 1003 case 'b': // Base register 1004 case 'f': // Floating point register 1005 Info.setAllowsRegister(); 1006 break; 1007 // FIXME: The following are added to allow parsing. 1008 // I just took a guess at what the actions should be. 1009 // Also, is more specific checking needed? I.e. specific registers? 1010 case 'd': // Floating point register (containing 64-bit value) 1011 case 'v': // Altivec vector register 1012 Info.setAllowsRegister(); 1013 break; 1014 case 'w': 1015 switch (Name[1]) { 1016 case 'd':// VSX vector register to hold vector double data 1017 case 'f':// VSX vector register to hold vector float data 1018 case 's':// VSX vector register to hold scalar float data 1019 case 'a':// Any VSX register 1020 case 'c':// An individual CR bit 1021 break; 1022 default: 1023 return false; 1024 } 1025 Info.setAllowsRegister(); 1026 Name++; // Skip over 'w'. 1027 break; 1028 case 'h': // `MQ', `CTR', or `LINK' register 1029 case 'q': // `MQ' register 1030 case 'c': // `CTR' register 1031 case 'l': // `LINK' register 1032 case 'x': // `CR' register (condition register) number 0 1033 case 'y': // `CR' register (condition register) 1034 case 'z': // `XER[CA]' carry bit (part of the XER register) 1035 Info.setAllowsRegister(); 1036 break; 1037 case 'I': // Signed 16-bit constant 1038 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1039 // (use `L' instead for SImode constants) 1040 case 'K': // Unsigned 16-bit constant 1041 case 'L': // Signed 16-bit constant shifted left 16 bits 1042 case 'M': // Constant larger than 31 1043 case 'N': // Exact power of 2 1044 case 'P': // Constant whose negation is a signed 16-bit constant 1045 case 'G': // Floating point constant that can be loaded into a 1046 // register with one instruction per word 1047 case 'H': // Integer/Floating point constant that can be loaded 1048 // into a register using three instructions 1049 break; 1050 case 'm': // Memory operand. Note that on PowerPC targets, m can 1051 // include addresses that update the base register. It 1052 // is therefore only safe to use `m' in an asm statement 1053 // if that asm statement accesses the operand exactly once. 1054 // The asm statement must also use `%U<opno>' as a 1055 // placeholder for the "update" flag in the corresponding 1056 // load or store instruction. For example: 1057 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1058 // is correct but: 1059 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1060 // is not. Use es rather than m if you don't want the base 1061 // register to be updated. 1062 case 'e': 1063 if (Name[1] != 's') 1064 return false; 1065 // es: A "stable" memory operand; that is, one which does not 1066 // include any automodification of the base register. Unlike 1067 // `m', this constraint can be used in asm statements that 1068 // might access the operand several times, or that might not 1069 // access it at all. 1070 Info.setAllowsMemory(); 1071 Name++; // Skip over 'e'. 1072 break; 1073 case 'Q': // Memory operand that is an offset from a register (it is 1074 // usually better to use `m' or `es' in asm statements) 1075 case 'Z': // Memory operand that is an indexed or indirect from a 1076 // register (it is usually better to use `m' or `es' in 1077 // asm statements) 1078 Info.setAllowsMemory(); 1079 Info.setAllowsRegister(); 1080 break; 1081 case 'R': // AIX TOC entry 1082 case 'a': // Address operand that is an indexed or indirect from a 1083 // register (`p' is preferable for asm statements) 1084 case 'S': // Constant suitable as a 64-bit mask operand 1085 case 'T': // Constant suitable as a 32-bit mask operand 1086 case 'U': // System V Release 4 small data area reference 1087 case 't': // AND masks that can be performed by two rldic{l, r} 1088 // instructions 1089 case 'W': // Vector constant that does not require memory 1090 case 'j': // Vector constant that is all zeros. 1091 break; 1092 // End FIXME. 1093 } 1094 return true; 1095 } 1096 std::string convertConstraint(const char *&Constraint) const override { 1097 std::string R; 1098 switch (*Constraint) { 1099 case 'e': 1100 case 'w': 1101 // Two-character constraint; add "^" hint for later parsing. 1102 R = std::string("^") + std::string(Constraint, 2); 1103 Constraint++; 1104 break; 1105 default: 1106 return TargetInfo::convertConstraint(Constraint); 1107 } 1108 return R; 1109 } 1110 const char *getClobbers() const override { 1111 return ""; 1112 } 1113 int getEHDataRegisterNumber(unsigned RegNo) const override { 1114 if (RegNo == 0) return 3; 1115 if (RegNo == 1) return 4; 1116 return -1; 1117 } 1118 1119 bool hasSjLjLowering() const override { 1120 return true; 1121 } 1122 1123 bool useFloat128ManglingForLongDouble() const override { 1124 return LongDoubleWidth == 128 && 1125 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1126 getTriple().isOSBinFormatELF(); 1127 } 1128 }; 1129 1130 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1131 #define BUILTIN(ID, TYPE, ATTRS) \ 1132 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1133 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1134 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1135 #include "clang/Basic/BuiltinsPPC.def" 1136 }; 1137 1138 /// handleTargetFeatures - Perform initialization based on the user 1139 /// configured set of features. 1140 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1141 DiagnosticsEngine &Diags) { 1142 for (const auto &Feature : Features) { 1143 if (Feature == "+vsx") { 1144 HasVSX = true; 1145 } else if (Feature == "+bpermd") { 1146 HasBPERMD = true; 1147 } else if (Feature == "+extdiv") { 1148 HasExtDiv = true; 1149 } else if (Feature == "+power8-vector") { 1150 HasP8Vector = true; 1151 } else if (Feature == "+crypto") { 1152 HasP8Crypto = true; 1153 } else if (Feature == "+direct-move") { 1154 HasDirectMove = true; 1155 } else if (Feature == "+qpx") { 1156 HasQPX = true; 1157 } else if (Feature == "+htm") { 1158 HasHTM = true; 1159 } else if (Feature == "+float128") { 1160 HasFloat128 = true; 1161 } 1162 // TODO: Finish this list and add an assert that we've handled them 1163 // all. 1164 } 1165 1166 return true; 1167 } 1168 1169 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1170 /// #defines that are not tied to a specific subtarget. 1171 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1172 MacroBuilder &Builder) const { 1173 // Target identification. 1174 Builder.defineMacro("__ppc__"); 1175 Builder.defineMacro("__PPC__"); 1176 Builder.defineMacro("_ARCH_PPC"); 1177 Builder.defineMacro("__powerpc__"); 1178 Builder.defineMacro("__POWERPC__"); 1179 if (PointerWidth == 64) { 1180 Builder.defineMacro("_ARCH_PPC64"); 1181 Builder.defineMacro("__powerpc64__"); 1182 Builder.defineMacro("__ppc64__"); 1183 Builder.defineMacro("__PPC64__"); 1184 } 1185 1186 // Target properties. 1187 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1188 Builder.defineMacro("_LITTLE_ENDIAN"); 1189 } else { 1190 if (getTriple().getOS() != llvm::Triple::NetBSD && 1191 getTriple().getOS() != llvm::Triple::OpenBSD) 1192 Builder.defineMacro("_BIG_ENDIAN"); 1193 } 1194 1195 // ABI options. 1196 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1197 Builder.defineMacro("_CALL_ELF", "1"); 1198 if (ABI == "elfv2") 1199 Builder.defineMacro("_CALL_ELF", "2"); 1200 1201 // Subtarget options. 1202 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1203 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1204 1205 // FIXME: Should be controlled by command line option. 1206 if (LongDoubleWidth == 128) 1207 Builder.defineMacro("__LONG_DOUBLE_128__"); 1208 1209 if (Opts.AltiVec) { 1210 Builder.defineMacro("__VEC__", "10206"); 1211 Builder.defineMacro("__ALTIVEC__"); 1212 } 1213 1214 // CPU identification. 1215 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1216 .Case("440", ArchDefineName) 1217 .Case("450", ArchDefineName | ArchDefine440) 1218 .Case("601", ArchDefineName) 1219 .Case("602", ArchDefineName | ArchDefinePpcgr) 1220 .Case("603", ArchDefineName | ArchDefinePpcgr) 1221 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1222 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1223 .Case("604", ArchDefineName | ArchDefinePpcgr) 1224 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1225 .Case("620", ArchDefineName | ArchDefinePpcgr) 1226 .Case("630", ArchDefineName | ArchDefinePpcgr) 1227 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1228 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1229 .Case("750", ArchDefineName | ArchDefinePpcgr) 1230 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1231 | ArchDefinePpcsq) 1232 .Case("a2", ArchDefineA2) 1233 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1234 .Case("pwr3", ArchDefinePpcgr) 1235 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1236 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1237 | ArchDefinePpcsq) 1238 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1239 | ArchDefinePpcgr | ArchDefinePpcsq) 1240 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1241 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1242 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1243 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1244 | ArchDefinePpcsq) 1245 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1246 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1247 | ArchDefinePpcgr | ArchDefinePpcsq) 1248 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1249 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1250 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1251 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1252 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1253 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1254 | ArchDefinePpcsq) 1255 .Case("power3", ArchDefinePpcgr) 1256 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1257 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1258 | ArchDefinePpcsq) 1259 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1260 | ArchDefinePpcgr | ArchDefinePpcsq) 1261 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1262 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1263 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1264 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1265 | ArchDefinePpcsq) 1266 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1267 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1268 | ArchDefinePpcgr | ArchDefinePpcsq) 1269 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1270 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1271 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1272 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1273 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1274 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1275 | ArchDefinePpcsq) 1276 .Default(ArchDefineNone); 1277 1278 if (defs & ArchDefineName) 1279 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1280 if (defs & ArchDefinePpcgr) 1281 Builder.defineMacro("_ARCH_PPCGR"); 1282 if (defs & ArchDefinePpcsq) 1283 Builder.defineMacro("_ARCH_PPCSQ"); 1284 if (defs & ArchDefine440) 1285 Builder.defineMacro("_ARCH_440"); 1286 if (defs & ArchDefine603) 1287 Builder.defineMacro("_ARCH_603"); 1288 if (defs & ArchDefine604) 1289 Builder.defineMacro("_ARCH_604"); 1290 if (defs & ArchDefinePwr4) 1291 Builder.defineMacro("_ARCH_PWR4"); 1292 if (defs & ArchDefinePwr5) 1293 Builder.defineMacro("_ARCH_PWR5"); 1294 if (defs & ArchDefinePwr5x) 1295 Builder.defineMacro("_ARCH_PWR5X"); 1296 if (defs & ArchDefinePwr6) 1297 Builder.defineMacro("_ARCH_PWR6"); 1298 if (defs & ArchDefinePwr6x) 1299 Builder.defineMacro("_ARCH_PWR6X"); 1300 if (defs & ArchDefinePwr7) 1301 Builder.defineMacro("_ARCH_PWR7"); 1302 if (defs & ArchDefinePwr8) 1303 Builder.defineMacro("_ARCH_PWR8"); 1304 if (defs & ArchDefinePwr9) 1305 Builder.defineMacro("_ARCH_PWR9"); 1306 if (defs & ArchDefineA2) 1307 Builder.defineMacro("_ARCH_A2"); 1308 if (defs & ArchDefineA2q) { 1309 Builder.defineMacro("_ARCH_A2Q"); 1310 Builder.defineMacro("_ARCH_QP"); 1311 } 1312 1313 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1314 Builder.defineMacro("__bg__"); 1315 Builder.defineMacro("__THW_BLUEGENE__"); 1316 Builder.defineMacro("__bgq__"); 1317 Builder.defineMacro("__TOS_BGQ__"); 1318 } 1319 1320 if (HasVSX) 1321 Builder.defineMacro("__VSX__"); 1322 if (HasP8Vector) 1323 Builder.defineMacro("__POWER8_VECTOR__"); 1324 if (HasP8Crypto) 1325 Builder.defineMacro("__CRYPTO__"); 1326 if (HasHTM) 1327 Builder.defineMacro("__HTM__"); 1328 if (HasFloat128) 1329 Builder.defineMacro("__FLOAT128__"); 1330 1331 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1332 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1333 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1334 if (PointerWidth == 64) 1335 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1336 1337 // FIXME: The following are not yet generated here by Clang, but are 1338 // generated by GCC: 1339 // 1340 // _SOFT_FLOAT_ 1341 // __RECIP_PRECISION__ 1342 // __APPLE_ALTIVEC__ 1343 // __RECIP__ 1344 // __RECIPF__ 1345 // __RSQRTE__ 1346 // __RSQRTEF__ 1347 // _SOFT_DOUBLE_ 1348 // __NO_LWSYNC__ 1349 // __HAVE_BSWAP__ 1350 // __LONGDOUBLE128 1351 // __CMODEL_MEDIUM__ 1352 // __CMODEL_LARGE__ 1353 // _CALL_SYSV 1354 // _CALL_DARWIN 1355 // __NO_FPRS__ 1356 } 1357 1358 // Handle explicit options being passed to the compiler here: if we've 1359 // explicitly turned off vsx and turned on power8-vector or direct-move then 1360 // go ahead and error since the customer has expressed a somewhat incompatible 1361 // set of options. 1362 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1363 const std::vector<std::string> &FeaturesVec) { 1364 1365 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1366 FeaturesVec.end()) { 1367 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1368 FeaturesVec.end()) { 1369 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1370 << "-mno-vsx"; 1371 return false; 1372 } 1373 1374 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1375 FeaturesVec.end()) { 1376 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1377 << "-mno-vsx"; 1378 return false; 1379 } 1380 1381 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1382 FeaturesVec.end()) { 1383 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1384 << "-mno-vsx"; 1385 return false; 1386 } 1387 } 1388 1389 return true; 1390 } 1391 1392 bool PPCTargetInfo::initFeatureMap( 1393 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1394 const std::vector<std::string> &FeaturesVec) const { 1395 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1396 .Case("7400", true) 1397 .Case("g4", true) 1398 .Case("7450", true) 1399 .Case("g4+", true) 1400 .Case("970", true) 1401 .Case("g5", true) 1402 .Case("pwr6", true) 1403 .Case("pwr7", true) 1404 .Case("pwr8", true) 1405 .Case("pwr9", true) 1406 .Case("ppc64", true) 1407 .Case("ppc64le", true) 1408 .Default(false); 1409 1410 Features["qpx"] = (CPU == "a2q"); 1411 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1412 .Case("ppc64le", true) 1413 .Case("pwr9", true) 1414 .Case("pwr8", true) 1415 .Default(false); 1416 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1417 .Case("ppc64le", true) 1418 .Case("pwr9", true) 1419 .Case("pwr8", true) 1420 .Default(false); 1421 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1422 .Case("ppc64le", true) 1423 .Case("pwr9", true) 1424 .Case("pwr8", true) 1425 .Case("pwr7", true) 1426 .Default(false); 1427 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1428 .Case("ppc64le", true) 1429 .Case("pwr9", true) 1430 .Case("pwr8", true) 1431 .Case("pwr7", true) 1432 .Default(false); 1433 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1434 .Case("ppc64le", true) 1435 .Case("pwr9", true) 1436 .Case("pwr8", true) 1437 .Default(false); 1438 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1439 .Case("ppc64le", true) 1440 .Case("pwr9", true) 1441 .Case("pwr8", true) 1442 .Case("pwr7", true) 1443 .Default(false); 1444 1445 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1446 return false; 1447 1448 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1449 } 1450 1451 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1452 return llvm::StringSwitch<bool>(Feature) 1453 .Case("powerpc", true) 1454 .Case("vsx", HasVSX) 1455 .Case("power8-vector", HasP8Vector) 1456 .Case("crypto", HasP8Crypto) 1457 .Case("direct-move", HasDirectMove) 1458 .Case("qpx", HasQPX) 1459 .Case("htm", HasHTM) 1460 .Case("bpermd", HasBPERMD) 1461 .Case("extdiv", HasExtDiv) 1462 .Case("float128", HasFloat128) 1463 .Default(false); 1464 } 1465 1466 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1467 StringRef Name, bool Enabled) const { 1468 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1469 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1470 // incompatible options. 1471 if (Enabled) { 1472 if (Name == "direct-move") { 1473 Features[Name] = Features["vsx"] = true; 1474 } else if (Name == "power8-vector") { 1475 Features[Name] = Features["vsx"] = true; 1476 } else if (Name == "float128") { 1477 Features[Name] = Features["vsx"] = true; 1478 } else { 1479 Features[Name] = true; 1480 } 1481 } else { 1482 if (Name == "vsx") { 1483 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1484 Features["float128"] = false; 1485 } else { 1486 Features[Name] = false; 1487 } 1488 } 1489 } 1490 1491 const char * const PPCTargetInfo::GCCRegNames[] = { 1492 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1493 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1494 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1495 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1496 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1497 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1498 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1499 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1500 "mq", "lr", "ctr", "ap", 1501 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1502 "xer", 1503 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1504 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1505 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1506 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1507 "vrsave", "vscr", 1508 "spe_acc", "spefscr", 1509 "sfp" 1510 }; 1511 1512 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1513 return llvm::makeArrayRef(GCCRegNames); 1514 } 1515 1516 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1517 // While some of these aliases do map to different registers 1518 // they still share the same register name. 1519 { { "0" }, "r0" }, 1520 { { "1"}, "r1" }, 1521 { { "2" }, "r2" }, 1522 { { "3" }, "r3" }, 1523 { { "4" }, "r4" }, 1524 { { "5" }, "r5" }, 1525 { { "6" }, "r6" }, 1526 { { "7" }, "r7" }, 1527 { { "8" }, "r8" }, 1528 { { "9" }, "r9" }, 1529 { { "10" }, "r10" }, 1530 { { "11" }, "r11" }, 1531 { { "12" }, "r12" }, 1532 { { "13" }, "r13" }, 1533 { { "14" }, "r14" }, 1534 { { "15" }, "r15" }, 1535 { { "16" }, "r16" }, 1536 { { "17" }, "r17" }, 1537 { { "18" }, "r18" }, 1538 { { "19" }, "r19" }, 1539 { { "20" }, "r20" }, 1540 { { "21" }, "r21" }, 1541 { { "22" }, "r22" }, 1542 { { "23" }, "r23" }, 1543 { { "24" }, "r24" }, 1544 { { "25" }, "r25" }, 1545 { { "26" }, "r26" }, 1546 { { "27" }, "r27" }, 1547 { { "28" }, "r28" }, 1548 { { "29" }, "r29" }, 1549 { { "30" }, "r30" }, 1550 { { "31" }, "r31" }, 1551 { { "fr0" }, "f0" }, 1552 { { "fr1" }, "f1" }, 1553 { { "fr2" }, "f2" }, 1554 { { "fr3" }, "f3" }, 1555 { { "fr4" }, "f4" }, 1556 { { "fr5" }, "f5" }, 1557 { { "fr6" }, "f6" }, 1558 { { "fr7" }, "f7" }, 1559 { { "fr8" }, "f8" }, 1560 { { "fr9" }, "f9" }, 1561 { { "fr10" }, "f10" }, 1562 { { "fr11" }, "f11" }, 1563 { { "fr12" }, "f12" }, 1564 { { "fr13" }, "f13" }, 1565 { { "fr14" }, "f14" }, 1566 { { "fr15" }, "f15" }, 1567 { { "fr16" }, "f16" }, 1568 { { "fr17" }, "f17" }, 1569 { { "fr18" }, "f18" }, 1570 { { "fr19" }, "f19" }, 1571 { { "fr20" }, "f20" }, 1572 { { "fr21" }, "f21" }, 1573 { { "fr22" }, "f22" }, 1574 { { "fr23" }, "f23" }, 1575 { { "fr24" }, "f24" }, 1576 { { "fr25" }, "f25" }, 1577 { { "fr26" }, "f26" }, 1578 { { "fr27" }, "f27" }, 1579 { { "fr28" }, "f28" }, 1580 { { "fr29" }, "f29" }, 1581 { { "fr30" }, "f30" }, 1582 { { "fr31" }, "f31" }, 1583 { { "cc" }, "cr0" }, 1584 }; 1585 1586 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1587 return llvm::makeArrayRef(GCCRegAliases); 1588 } 1589 1590 class PPC32TargetInfo : public PPCTargetInfo { 1591 public: 1592 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1593 : PPCTargetInfo(Triple, Opts) { 1594 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1595 1596 switch (getTriple().getOS()) { 1597 case llvm::Triple::Linux: 1598 case llvm::Triple::FreeBSD: 1599 case llvm::Triple::NetBSD: 1600 SizeType = UnsignedInt; 1601 PtrDiffType = SignedInt; 1602 IntPtrType = SignedInt; 1603 break; 1604 default: 1605 break; 1606 } 1607 1608 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1609 LongDoubleWidth = LongDoubleAlign = 64; 1610 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1611 } 1612 1613 // PPC32 supports atomics up to 4 bytes. 1614 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1615 } 1616 1617 BuiltinVaListKind getBuiltinVaListKind() const override { 1618 // This is the ELF definition, and is overridden by the Darwin sub-target 1619 return TargetInfo::PowerABIBuiltinVaList; 1620 } 1621 }; 1622 1623 // Note: ABI differences may eventually require us to have a separate 1624 // TargetInfo for little endian. 1625 class PPC64TargetInfo : public PPCTargetInfo { 1626 public: 1627 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1628 : PPCTargetInfo(Triple, Opts) { 1629 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1630 IntMaxType = SignedLong; 1631 Int64Type = SignedLong; 1632 1633 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1634 resetDataLayout("e-m:e-i64:64-n32:64"); 1635 ABI = "elfv2"; 1636 } else { 1637 resetDataLayout("E-m:e-i64:64-n32:64"); 1638 ABI = "elfv1"; 1639 } 1640 1641 switch (getTriple().getOS()) { 1642 case llvm::Triple::FreeBSD: 1643 LongDoubleWidth = LongDoubleAlign = 64; 1644 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1645 break; 1646 case llvm::Triple::NetBSD: 1647 IntMaxType = SignedLongLong; 1648 Int64Type = SignedLongLong; 1649 break; 1650 default: 1651 break; 1652 } 1653 1654 // PPC64 supports atomics up to 8 bytes. 1655 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1656 } 1657 BuiltinVaListKind getBuiltinVaListKind() const override { 1658 return TargetInfo::CharPtrBuiltinVaList; 1659 } 1660 // PPC64 Linux-specific ABI options. 1661 bool setABI(const std::string &Name) override { 1662 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1663 ABI = Name; 1664 return true; 1665 } 1666 return false; 1667 } 1668 }; 1669 1670 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1671 public: 1672 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1673 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1674 HasAlignMac68kSupport = true; 1675 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1676 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1677 LongLongAlign = 32; 1678 SuitableAlign = 128; 1679 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1680 } 1681 BuiltinVaListKind getBuiltinVaListKind() const override { 1682 return TargetInfo::CharPtrBuiltinVaList; 1683 } 1684 }; 1685 1686 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1687 public: 1688 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1689 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1690 HasAlignMac68kSupport = true; 1691 SuitableAlign = 128; 1692 resetDataLayout("E-m:o-i64:64-n32:64"); 1693 } 1694 }; 1695 1696 static const unsigned NVPTXAddrSpaceMap[] = { 1697 1, // opencl_global 1698 3, // opencl_local 1699 4, // opencl_constant 1700 // FIXME: generic has to be added to the target 1701 0, // opencl_generic 1702 1, // cuda_device 1703 4, // cuda_constant 1704 3, // cuda_shared 1705 }; 1706 1707 class NVPTXTargetInfo : public TargetInfo { 1708 static const char *const GCCRegNames[]; 1709 static const Builtin::Info BuiltinInfo[]; 1710 CudaArch GPU; 1711 1712 public: 1713 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1714 : TargetInfo(Triple) { 1715 BigEndian = false; 1716 TLSSupported = false; 1717 LongWidth = LongAlign = 64; 1718 AddrSpaceMap = &NVPTXAddrSpaceMap; 1719 UseAddrSpaceMapMangling = true; 1720 // Define available target features 1721 // These must be defined in sorted order! 1722 NoAsmVariants = true; 1723 GPU = CudaArch::SM_20; 1724 1725 // If possible, get a TargetInfo for our host triple, so we can match its 1726 // types. 1727 llvm::Triple HostTriple(Opts.HostTriple); 1728 if (HostTriple.isNVPTX()) 1729 return; 1730 std::unique_ptr<TargetInfo> HostTarget( 1731 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1732 if (!HostTarget) { 1733 return; 1734 } 1735 1736 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1737 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1738 BoolWidth = HostTarget->getBoolWidth(); 1739 BoolAlign = HostTarget->getBoolAlign(); 1740 IntWidth = HostTarget->getIntWidth(); 1741 IntAlign = HostTarget->getIntAlign(); 1742 HalfWidth = HostTarget->getHalfWidth(); 1743 HalfAlign = HostTarget->getHalfAlign(); 1744 FloatWidth = HostTarget->getFloatWidth(); 1745 FloatAlign = HostTarget->getFloatAlign(); 1746 DoubleWidth = HostTarget->getDoubleWidth(); 1747 DoubleAlign = HostTarget->getDoubleAlign(); 1748 LongWidth = HostTarget->getLongWidth(); 1749 LongAlign = HostTarget->getLongAlign(); 1750 LongLongWidth = HostTarget->getLongLongWidth(); 1751 LongLongAlign = HostTarget->getLongLongAlign(); 1752 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1753 DefaultAlignForAttributeAligned = 1754 HostTarget->getDefaultAlignForAttributeAligned(); 1755 SizeType = HostTarget->getSizeType(); 1756 IntMaxType = HostTarget->getIntMaxType(); 1757 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1758 IntPtrType = HostTarget->getIntPtrType(); 1759 WCharType = HostTarget->getWCharType(); 1760 WIntType = HostTarget->getWIntType(); 1761 Char16Type = HostTarget->getChar16Type(); 1762 Char32Type = HostTarget->getChar32Type(); 1763 Int64Type = HostTarget->getInt64Type(); 1764 SigAtomicType = HostTarget->getSigAtomicType(); 1765 ProcessIDType = HostTarget->getProcessIDType(); 1766 1767 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1768 UseZeroLengthBitfieldAlignment = 1769 HostTarget->useZeroLengthBitfieldAlignment(); 1770 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1771 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1772 1773 // Properties intentionally not copied from host: 1774 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1775 // host/device boundary. 1776 // - SuitableAlign: Not visible across the host/device boundary, and may 1777 // correctly be different on host/device, e.g. if host has wider vector 1778 // types than device. 1779 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1780 // as its double type, but that's not necessarily true on the host. 1781 // TODO: nvcc emits a warning when using long double on device; we should 1782 // do the same. 1783 } 1784 void getTargetDefines(const LangOptions &Opts, 1785 MacroBuilder &Builder) const override { 1786 Builder.defineMacro("__PTX__"); 1787 Builder.defineMacro("__NVPTX__"); 1788 if (Opts.CUDAIsDevice) { 1789 // Set __CUDA_ARCH__ for the GPU specified. 1790 std::string CUDAArchCode = [this] { 1791 switch (GPU) { 1792 case CudaArch::UNKNOWN: 1793 assert(false && "No GPU arch when compiling CUDA device code."); 1794 return ""; 1795 case CudaArch::SM_20: 1796 return "200"; 1797 case CudaArch::SM_21: 1798 return "210"; 1799 case CudaArch::SM_30: 1800 return "300"; 1801 case CudaArch::SM_32: 1802 return "320"; 1803 case CudaArch::SM_35: 1804 return "350"; 1805 case CudaArch::SM_37: 1806 return "370"; 1807 case CudaArch::SM_50: 1808 return "500"; 1809 case CudaArch::SM_52: 1810 return "520"; 1811 case CudaArch::SM_53: 1812 return "530"; 1813 case CudaArch::SM_60: 1814 return "600"; 1815 case CudaArch::SM_61: 1816 return "610"; 1817 case CudaArch::SM_62: 1818 return "620"; 1819 } 1820 llvm_unreachable("unhandled CudaArch"); 1821 }(); 1822 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1823 } 1824 } 1825 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1826 return llvm::makeArrayRef(BuiltinInfo, 1827 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1828 } 1829 bool hasFeature(StringRef Feature) const override { 1830 return Feature == "ptx" || Feature == "nvptx"; 1831 } 1832 1833 ArrayRef<const char *> getGCCRegNames() const override; 1834 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1835 // No aliases. 1836 return None; 1837 } 1838 bool validateAsmConstraint(const char *&Name, 1839 TargetInfo::ConstraintInfo &Info) const override { 1840 switch (*Name) { 1841 default: 1842 return false; 1843 case 'c': 1844 case 'h': 1845 case 'r': 1846 case 'l': 1847 case 'f': 1848 case 'd': 1849 Info.setAllowsRegister(); 1850 return true; 1851 } 1852 } 1853 const char *getClobbers() const override { 1854 // FIXME: Is this really right? 1855 return ""; 1856 } 1857 BuiltinVaListKind getBuiltinVaListKind() const override { 1858 // FIXME: implement 1859 return TargetInfo::CharPtrBuiltinVaList; 1860 } 1861 bool setCPU(const std::string &Name) override { 1862 GPU = StringToCudaArch(Name); 1863 return GPU != CudaArch::UNKNOWN; 1864 } 1865 void setSupportedOpenCLOpts() override { 1866 auto &Opts = getSupportedOpenCLOpts(); 1867 Opts.cl_clang_storage_class_specifiers = 1; 1868 Opts.cl_khr_gl_sharing = 1; 1869 Opts.cl_khr_icd = 1; 1870 1871 Opts.cl_khr_fp64 = 1; 1872 Opts.cl_khr_byte_addressable_store = 1; 1873 Opts.cl_khr_global_int32_base_atomics = 1; 1874 Opts.cl_khr_global_int32_extended_atomics = 1; 1875 Opts.cl_khr_local_int32_base_atomics = 1; 1876 Opts.cl_khr_local_int32_extended_atomics = 1; 1877 } 1878 }; 1879 1880 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1881 #define BUILTIN(ID, TYPE, ATTRS) \ 1882 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1883 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1884 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1885 #include "clang/Basic/BuiltinsNVPTX.def" 1886 }; 1887 1888 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1889 1890 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1891 return llvm::makeArrayRef(GCCRegNames); 1892 } 1893 1894 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1895 public: 1896 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1897 : NVPTXTargetInfo(Triple, Opts) { 1898 LongWidth = LongAlign = 32; 1899 PointerWidth = PointerAlign = 32; 1900 SizeType = TargetInfo::UnsignedInt; 1901 PtrDiffType = TargetInfo::SignedInt; 1902 IntPtrType = TargetInfo::SignedInt; 1903 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1904 } 1905 }; 1906 1907 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1908 public: 1909 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1910 : NVPTXTargetInfo(Triple, Opts) { 1911 PointerWidth = PointerAlign = 64; 1912 SizeType = TargetInfo::UnsignedLong; 1913 PtrDiffType = TargetInfo::SignedLong; 1914 IntPtrType = TargetInfo::SignedLong; 1915 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1916 } 1917 }; 1918 1919 static const unsigned AMDGPUAddrSpaceMap[] = { 1920 1, // opencl_global 1921 3, // opencl_local 1922 2, // opencl_constant 1923 4, // opencl_generic 1924 1, // cuda_device 1925 2, // cuda_constant 1926 3 // cuda_shared 1927 }; 1928 1929 // If you edit the description strings, make sure you update 1930 // getPointerWidthV(). 1931 1932 static const char *const DataLayoutStringR600 = 1933 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1934 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1935 1936 static const char *const DataLayoutStringSI = 1937 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 1938 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1939 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1940 1941 class AMDGPUTargetInfo final : public TargetInfo { 1942 static const Builtin::Info BuiltinInfo[]; 1943 static const char * const GCCRegNames[]; 1944 1945 /// \brief The GPU profiles supported by the AMDGPU target. 1946 enum GPUKind { 1947 GK_NONE, 1948 GK_R600, 1949 GK_R600_DOUBLE_OPS, 1950 GK_R700, 1951 GK_R700_DOUBLE_OPS, 1952 GK_EVERGREEN, 1953 GK_EVERGREEN_DOUBLE_OPS, 1954 GK_NORTHERN_ISLANDS, 1955 GK_CAYMAN, 1956 GK_SOUTHERN_ISLANDS, 1957 GK_SEA_ISLANDS, 1958 GK_VOLCANIC_ISLANDS 1959 } GPU; 1960 1961 bool hasFP64:1; 1962 bool hasFMAF:1; 1963 bool hasLDEXPF:1; 1964 bool hasDenormSupport:1; 1965 1966 static bool isAMDGCN(const llvm::Triple &TT) { 1967 return TT.getArch() == llvm::Triple::amdgcn; 1968 } 1969 1970 public: 1971 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1972 : TargetInfo(Triple) , 1973 GPU(isAMDGCN(Triple) ? GK_SOUTHERN_ISLANDS : GK_R600), 1974 hasFP64(false), 1975 hasFMAF(false), 1976 hasLDEXPF(false), 1977 hasDenormSupport(false){ 1978 if (getTriple().getArch() == llvm::Triple::amdgcn) { 1979 hasFP64 = true; 1980 hasFMAF = true; 1981 hasLDEXPF = true; 1982 } 1983 if (Opts.CPU == "fiji") 1984 hasDenormSupport = true; 1985 1986 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 1987 DataLayoutStringSI : DataLayoutStringR600); 1988 1989 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1990 UseAddrSpaceMapMangling = true; 1991 } 1992 1993 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1994 if (GPU <= GK_CAYMAN) 1995 return 32; 1996 1997 switch(AddrSpace) { 1998 default: 1999 return 64; 2000 case 0: 2001 case 3: 2002 case 5: 2003 return 32; 2004 } 2005 } 2006 2007 const char * getClobbers() const override { 2008 return ""; 2009 } 2010 2011 ArrayRef<const char *> getGCCRegNames() const override; 2012 2013 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2014 return None; 2015 } 2016 2017 bool validateAsmConstraint(const char *&Name, 2018 TargetInfo::ConstraintInfo &Info) const override { 2019 switch (*Name) { 2020 default: break; 2021 case 'v': // vgpr 2022 case 's': // sgpr 2023 Info.setAllowsRegister(); 2024 return true; 2025 } 2026 return false; 2027 } 2028 2029 bool initFeatureMap(llvm::StringMap<bool> &Features, 2030 DiagnosticsEngine &Diags, StringRef CPU, 2031 const std::vector<std::string> &FeatureVec) const override; 2032 2033 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2034 TargetOptions &TargetOpts) const override { 2035 if (!hasDenormSupport) 2036 return; 2037 bool hasFP32Denormals = false; 2038 bool hasFP64Denormals = false; 2039 for (auto &I : TargetOpts.FeaturesAsWritten) { 2040 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2041 hasFP32Denormals = true; 2042 if (I == "+fp64-denormals" || I == "-fp64-denormals") 2043 hasFP64Denormals = true; 2044 } 2045 if (!hasFP32Denormals) 2046 TargetOpts.Features.push_back((Twine(CGOpts.FlushDenorm ? '-' : '+') + 2047 Twine("fp32-denormals")).str()); 2048 if (!hasFP64Denormals && hasFP64) 2049 TargetOpts.Features.push_back((Twine(CGOpts.FlushDenorm ? '-' : '+') + 2050 Twine("fp64-denormals")).str()); 2051 } 2052 2053 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2054 return llvm::makeArrayRef(BuiltinInfo, 2055 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2056 } 2057 2058 void getTargetDefines(const LangOptions &Opts, 2059 MacroBuilder &Builder) const override { 2060 if (getTriple().getArch() == llvm::Triple::amdgcn) 2061 Builder.defineMacro("__AMDGCN__"); 2062 else 2063 Builder.defineMacro("__R600__"); 2064 2065 if (hasFMAF) 2066 Builder.defineMacro("__HAS_FMAF__"); 2067 if (hasLDEXPF) 2068 Builder.defineMacro("__HAS_LDEXPF__"); 2069 if (hasFP64) 2070 Builder.defineMacro("__HAS_FP64__"); 2071 } 2072 2073 BuiltinVaListKind getBuiltinVaListKind() const override { 2074 return TargetInfo::CharPtrBuiltinVaList; 2075 } 2076 2077 static GPUKind parseR600Name(StringRef Name) { 2078 return llvm::StringSwitch<GPUKind>(Name) 2079 .Case("r600" , GK_R600) 2080 .Case("rv610", GK_R600) 2081 .Case("rv620", GK_R600) 2082 .Case("rv630", GK_R600) 2083 .Case("rv635", GK_R600) 2084 .Case("rs780", GK_R600) 2085 .Case("rs880", GK_R600) 2086 .Case("rv670", GK_R600_DOUBLE_OPS) 2087 .Case("rv710", GK_R700) 2088 .Case("rv730", GK_R700) 2089 .Case("rv740", GK_R700_DOUBLE_OPS) 2090 .Case("rv770", GK_R700_DOUBLE_OPS) 2091 .Case("palm", GK_EVERGREEN) 2092 .Case("cedar", GK_EVERGREEN) 2093 .Case("sumo", GK_EVERGREEN) 2094 .Case("sumo2", GK_EVERGREEN) 2095 .Case("redwood", GK_EVERGREEN) 2096 .Case("juniper", GK_EVERGREEN) 2097 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2098 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2099 .Case("barts", GK_NORTHERN_ISLANDS) 2100 .Case("turks", GK_NORTHERN_ISLANDS) 2101 .Case("caicos", GK_NORTHERN_ISLANDS) 2102 .Case("cayman", GK_CAYMAN) 2103 .Case("aruba", GK_CAYMAN) 2104 .Default(GK_NONE); 2105 } 2106 2107 static GPUKind parseAMDGCNName(StringRef Name) { 2108 return llvm::StringSwitch<GPUKind>(Name) 2109 .Case("tahiti", GK_SOUTHERN_ISLANDS) 2110 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 2111 .Case("verde", GK_SOUTHERN_ISLANDS) 2112 .Case("oland", GK_SOUTHERN_ISLANDS) 2113 .Case("hainan", GK_SOUTHERN_ISLANDS) 2114 .Case("bonaire", GK_SEA_ISLANDS) 2115 .Case("kabini", GK_SEA_ISLANDS) 2116 .Case("kaveri", GK_SEA_ISLANDS) 2117 .Case("hawaii", GK_SEA_ISLANDS) 2118 .Case("mullins", GK_SEA_ISLANDS) 2119 .Case("tonga", GK_VOLCANIC_ISLANDS) 2120 .Case("iceland", GK_VOLCANIC_ISLANDS) 2121 .Case("carrizo", GK_VOLCANIC_ISLANDS) 2122 .Case("fiji", GK_VOLCANIC_ISLANDS) 2123 .Case("stoney", GK_VOLCANIC_ISLANDS) 2124 .Default(GK_NONE); 2125 } 2126 2127 bool setCPU(const std::string &Name) override { 2128 if (getTriple().getArch() == llvm::Triple::amdgcn) 2129 GPU = parseAMDGCNName(Name); 2130 else 2131 GPU = parseR600Name(Name); 2132 2133 return GPU != GK_NONE; 2134 } 2135 2136 void setSupportedOpenCLOpts() override { 2137 auto &Opts = getSupportedOpenCLOpts(); 2138 Opts.cl_clang_storage_class_specifiers = 1; 2139 Opts.cl_khr_icd = 1; 2140 2141 if (hasFP64) 2142 Opts.cl_khr_fp64 = 1; 2143 if (GPU >= GK_EVERGREEN) { 2144 Opts.cl_khr_byte_addressable_store = 1; 2145 Opts.cl_khr_global_int32_base_atomics = 1; 2146 Opts.cl_khr_global_int32_extended_atomics = 1; 2147 Opts.cl_khr_local_int32_base_atomics = 1; 2148 Opts.cl_khr_local_int32_extended_atomics = 1; 2149 } 2150 if (GPU >= GK_SOUTHERN_ISLANDS) { 2151 Opts.cl_khr_fp16 = 1; 2152 Opts.cl_khr_int64_base_atomics = 1; 2153 Opts.cl_khr_int64_extended_atomics = 1; 2154 Opts.cl_khr_mipmap_image = 1; 2155 Opts.cl_khr_3d_image_writes = 1; 2156 } 2157 } 2158 2159 LangAS::ID getOpenCLImageAddrSpace() const override { 2160 return LangAS::opencl_constant; 2161 } 2162 2163 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2164 switch (CC) { 2165 default: 2166 return CCCR_Warning; 2167 case CC_C: 2168 case CC_OpenCLKernel: 2169 return CCCR_OK; 2170 } 2171 } 2172 }; 2173 2174 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2175 #define BUILTIN(ID, TYPE, ATTRS) \ 2176 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2177 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2178 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2179 #include "clang/Basic/BuiltinsAMDGPU.def" 2180 }; 2181 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2182 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2183 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2184 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2185 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2186 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2187 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2188 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2189 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2190 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2191 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2192 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2193 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2194 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2195 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2196 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2197 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2198 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2199 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2200 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2201 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2202 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2203 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2204 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2205 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2206 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2207 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2208 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2209 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2210 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2211 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2212 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2213 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2214 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2215 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2216 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2217 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2218 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2219 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2220 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2221 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2222 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2223 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2224 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2225 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2226 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2227 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2228 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2229 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2230 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2231 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2232 }; 2233 2234 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2235 return llvm::makeArrayRef(GCCRegNames); 2236 } 2237 2238 bool AMDGPUTargetInfo::initFeatureMap( 2239 llvm::StringMap<bool> &Features, 2240 DiagnosticsEngine &Diags, StringRef CPU, 2241 const std::vector<std::string> &FeatureVec) const { 2242 2243 // XXX - What does the member GPU mean if device name string passed here? 2244 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2245 if (CPU.empty()) 2246 CPU = "tahiti"; 2247 2248 switch (parseAMDGCNName(CPU)) { 2249 case GK_SOUTHERN_ISLANDS: 2250 case GK_SEA_ISLANDS: 2251 break; 2252 2253 case GK_VOLCANIC_ISLANDS: 2254 Features["s-memrealtime"] = true; 2255 Features["16-bit-insts"] = true; 2256 break; 2257 2258 case GK_NONE: 2259 return false; 2260 default: 2261 llvm_unreachable("unhandled subtarget"); 2262 } 2263 } else { 2264 if (CPU.empty()) 2265 CPU = "r600"; 2266 2267 switch (parseR600Name(CPU)) { 2268 case GK_R600: 2269 case GK_R700: 2270 case GK_EVERGREEN: 2271 case GK_NORTHERN_ISLANDS: 2272 break; 2273 case GK_R600_DOUBLE_OPS: 2274 case GK_R700_DOUBLE_OPS: 2275 case GK_EVERGREEN_DOUBLE_OPS: 2276 case GK_CAYMAN: 2277 Features["fp64"] = true; 2278 break; 2279 case GK_NONE: 2280 return false; 2281 default: 2282 llvm_unreachable("unhandled subtarget"); 2283 } 2284 } 2285 2286 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2287 } 2288 2289 // Namespace for x86 abstract base class 2290 const Builtin::Info BuiltinInfo[] = { 2291 #define BUILTIN(ID, TYPE, ATTRS) \ 2292 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2293 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2294 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2295 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2296 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2297 #include "clang/Basic/BuiltinsX86.def" 2298 }; 2299 2300 static const char* const GCCRegNames[] = { 2301 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2302 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2303 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2304 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2305 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2306 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2307 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2308 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2309 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2310 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2311 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2312 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2313 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2314 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2315 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2316 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2317 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2318 }; 2319 2320 const TargetInfo::AddlRegName AddlRegNames[] = { 2321 { { "al", "ah", "eax", "rax" }, 0 }, 2322 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2323 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2324 { { "dl", "dh", "edx", "rdx" }, 1 }, 2325 { { "esi", "rsi" }, 4 }, 2326 { { "edi", "rdi" }, 5 }, 2327 { { "esp", "rsp" }, 7 }, 2328 { { "ebp", "rbp" }, 6 }, 2329 { { "r8d", "r8w", "r8b" }, 38 }, 2330 { { "r9d", "r9w", "r9b" }, 39 }, 2331 { { "r10d", "r10w", "r10b" }, 40 }, 2332 { { "r11d", "r11w", "r11b" }, 41 }, 2333 { { "r12d", "r12w", "r12b" }, 42 }, 2334 { { "r13d", "r13w", "r13b" }, 43 }, 2335 { { "r14d", "r14w", "r14b" }, 44 }, 2336 { { "r15d", "r15w", "r15b" }, 45 }, 2337 }; 2338 2339 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2340 // most of the implementation can be shared. 2341 class X86TargetInfo : public TargetInfo { 2342 enum X86SSEEnum { 2343 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2344 } SSELevel = NoSSE; 2345 enum MMX3DNowEnum { 2346 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2347 } MMX3DNowLevel = NoMMX3DNow; 2348 enum XOPEnum { 2349 NoXOP, 2350 SSE4A, 2351 FMA4, 2352 XOP 2353 } XOPLevel = NoXOP; 2354 2355 bool HasAES = false; 2356 bool HasPCLMUL = false; 2357 bool HasLZCNT = false; 2358 bool HasRDRND = false; 2359 bool HasFSGSBASE = false; 2360 bool HasBMI = false; 2361 bool HasBMI2 = false; 2362 bool HasPOPCNT = false; 2363 bool HasRTM = false; 2364 bool HasPRFCHW = false; 2365 bool HasRDSEED = false; 2366 bool HasADX = false; 2367 bool HasTBM = false; 2368 bool HasFMA = false; 2369 bool HasF16C = false; 2370 bool HasAVX512CD = false; 2371 bool HasAVX512ER = false; 2372 bool HasAVX512PF = false; 2373 bool HasAVX512DQ = false; 2374 bool HasAVX512BW = false; 2375 bool HasAVX512VL = false; 2376 bool HasAVX512VBMI = false; 2377 bool HasAVX512IFMA = false; 2378 bool HasSHA = false; 2379 bool HasMPX = false; 2380 bool HasSGX = false; 2381 bool HasCX16 = false; 2382 bool HasFXSR = false; 2383 bool HasXSAVE = false; 2384 bool HasXSAVEOPT = false; 2385 bool HasXSAVEC = false; 2386 bool HasXSAVES = false; 2387 bool HasMWAITX = false; 2388 bool HasPKU = false; 2389 bool HasCLFLUSHOPT = false; 2390 bool HasPCOMMIT = false; 2391 bool HasCLWB = false; 2392 bool HasUMIP = false; 2393 bool HasMOVBE = false; 2394 bool HasPREFETCHWT1 = false; 2395 2396 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2397 /// 2398 /// Each enumeration represents a particular CPU supported by Clang. These 2399 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2400 enum CPUKind { 2401 CK_Generic, 2402 2403 /// \name i386 2404 /// i386-generation processors. 2405 //@{ 2406 CK_i386, 2407 //@} 2408 2409 /// \name i486 2410 /// i486-generation processors. 2411 //@{ 2412 CK_i486, 2413 CK_WinChipC6, 2414 CK_WinChip2, 2415 CK_C3, 2416 //@} 2417 2418 /// \name i586 2419 /// i586-generation processors, P5 microarchitecture based. 2420 //@{ 2421 CK_i586, 2422 CK_Pentium, 2423 CK_PentiumMMX, 2424 //@} 2425 2426 /// \name i686 2427 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2428 //@{ 2429 CK_i686, 2430 CK_PentiumPro, 2431 CK_Pentium2, 2432 CK_Pentium3, 2433 CK_Pentium3M, 2434 CK_PentiumM, 2435 CK_C3_2, 2436 2437 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2438 /// Clang however has some logic to suport this. 2439 // FIXME: Warn, deprecate, and potentially remove this. 2440 CK_Yonah, 2441 //@} 2442 2443 /// \name Netburst 2444 /// Netburst microarchitecture based processors. 2445 //@{ 2446 CK_Pentium4, 2447 CK_Pentium4M, 2448 CK_Prescott, 2449 CK_Nocona, 2450 //@} 2451 2452 /// \name Core 2453 /// Core microarchitecture based processors. 2454 //@{ 2455 CK_Core2, 2456 2457 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2458 /// codename which GCC no longer accepts as an option to -march, but Clang 2459 /// has some logic for recognizing it. 2460 // FIXME: Warn, deprecate, and potentially remove this. 2461 CK_Penryn, 2462 //@} 2463 2464 /// \name Atom 2465 /// Atom processors 2466 //@{ 2467 CK_Bonnell, 2468 CK_Silvermont, 2469 //@} 2470 2471 /// \name Nehalem 2472 /// Nehalem microarchitecture based processors. 2473 CK_Nehalem, 2474 2475 /// \name Westmere 2476 /// Westmere microarchitecture based processors. 2477 CK_Westmere, 2478 2479 /// \name Sandy Bridge 2480 /// Sandy Bridge microarchitecture based processors. 2481 CK_SandyBridge, 2482 2483 /// \name Ivy Bridge 2484 /// Ivy Bridge microarchitecture based processors. 2485 CK_IvyBridge, 2486 2487 /// \name Haswell 2488 /// Haswell microarchitecture based processors. 2489 CK_Haswell, 2490 2491 /// \name Broadwell 2492 /// Broadwell microarchitecture based processors. 2493 CK_Broadwell, 2494 2495 /// \name Skylake Client 2496 /// Skylake client microarchitecture based processors. 2497 CK_SkylakeClient, 2498 2499 /// \name Skylake Server 2500 /// Skylake server microarchitecture based processors. 2501 CK_SkylakeServer, 2502 2503 /// \name Cannonlake Client 2504 /// Cannonlake client microarchitecture based processors. 2505 CK_Cannonlake, 2506 2507 /// \name Knights Landing 2508 /// Knights Landing processor. 2509 CK_KNL, 2510 2511 /// \name Lakemont 2512 /// Lakemont microarchitecture based processors. 2513 CK_Lakemont, 2514 2515 /// \name K6 2516 /// K6 architecture processors. 2517 //@{ 2518 CK_K6, 2519 CK_K6_2, 2520 CK_K6_3, 2521 //@} 2522 2523 /// \name K7 2524 /// K7 architecture processors. 2525 //@{ 2526 CK_Athlon, 2527 CK_AthlonThunderbird, 2528 CK_Athlon4, 2529 CK_AthlonXP, 2530 CK_AthlonMP, 2531 //@} 2532 2533 /// \name K8 2534 /// K8 architecture processors. 2535 //@{ 2536 CK_Athlon64, 2537 CK_Athlon64SSE3, 2538 CK_AthlonFX, 2539 CK_K8, 2540 CK_K8SSE3, 2541 CK_Opteron, 2542 CK_OpteronSSE3, 2543 CK_AMDFAM10, 2544 //@} 2545 2546 /// \name Bobcat 2547 /// Bobcat architecture processors. 2548 //@{ 2549 CK_BTVER1, 2550 CK_BTVER2, 2551 //@} 2552 2553 /// \name Bulldozer 2554 /// Bulldozer architecture processors. 2555 //@{ 2556 CK_BDVER1, 2557 CK_BDVER2, 2558 CK_BDVER3, 2559 CK_BDVER4, 2560 //@} 2561 2562 /// This specification is deprecated and will be removed in the future. 2563 /// Users should prefer \see CK_K8. 2564 // FIXME: Warn on this when the CPU is set to it. 2565 //@{ 2566 CK_x86_64, 2567 //@} 2568 2569 /// \name Geode 2570 /// Geode processors. 2571 //@{ 2572 CK_Geode 2573 //@} 2574 } CPU = CK_Generic; 2575 2576 CPUKind getCPUKind(StringRef CPU) const { 2577 return llvm::StringSwitch<CPUKind>(CPU) 2578 .Case("i386", CK_i386) 2579 .Case("i486", CK_i486) 2580 .Case("winchip-c6", CK_WinChipC6) 2581 .Case("winchip2", CK_WinChip2) 2582 .Case("c3", CK_C3) 2583 .Case("i586", CK_i586) 2584 .Case("pentium", CK_Pentium) 2585 .Case("pentium-mmx", CK_PentiumMMX) 2586 .Case("i686", CK_i686) 2587 .Case("pentiumpro", CK_PentiumPro) 2588 .Case("pentium2", CK_Pentium2) 2589 .Case("pentium3", CK_Pentium3) 2590 .Case("pentium3m", CK_Pentium3M) 2591 .Case("pentium-m", CK_PentiumM) 2592 .Case("c3-2", CK_C3_2) 2593 .Case("yonah", CK_Yonah) 2594 .Case("pentium4", CK_Pentium4) 2595 .Case("pentium4m", CK_Pentium4M) 2596 .Case("prescott", CK_Prescott) 2597 .Case("nocona", CK_Nocona) 2598 .Case("core2", CK_Core2) 2599 .Case("penryn", CK_Penryn) 2600 .Case("bonnell", CK_Bonnell) 2601 .Case("atom", CK_Bonnell) // Legacy name. 2602 .Case("silvermont", CK_Silvermont) 2603 .Case("slm", CK_Silvermont) // Legacy name. 2604 .Case("nehalem", CK_Nehalem) 2605 .Case("corei7", CK_Nehalem) // Legacy name. 2606 .Case("westmere", CK_Westmere) 2607 .Case("sandybridge", CK_SandyBridge) 2608 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2609 .Case("ivybridge", CK_IvyBridge) 2610 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2611 .Case("haswell", CK_Haswell) 2612 .Case("core-avx2", CK_Haswell) // Legacy name. 2613 .Case("broadwell", CK_Broadwell) 2614 .Case("skylake", CK_SkylakeClient) 2615 .Case("skylake-avx512", CK_SkylakeServer) 2616 .Case("skx", CK_SkylakeServer) // Legacy name. 2617 .Case("cannonlake", CK_Cannonlake) 2618 .Case("knl", CK_KNL) 2619 .Case("lakemont", CK_Lakemont) 2620 .Case("k6", CK_K6) 2621 .Case("k6-2", CK_K6_2) 2622 .Case("k6-3", CK_K6_3) 2623 .Case("athlon", CK_Athlon) 2624 .Case("athlon-tbird", CK_AthlonThunderbird) 2625 .Case("athlon-4", CK_Athlon4) 2626 .Case("athlon-xp", CK_AthlonXP) 2627 .Case("athlon-mp", CK_AthlonMP) 2628 .Case("athlon64", CK_Athlon64) 2629 .Case("athlon64-sse3", CK_Athlon64SSE3) 2630 .Case("athlon-fx", CK_AthlonFX) 2631 .Case("k8", CK_K8) 2632 .Case("k8-sse3", CK_K8SSE3) 2633 .Case("opteron", CK_Opteron) 2634 .Case("opteron-sse3", CK_OpteronSSE3) 2635 .Case("barcelona", CK_AMDFAM10) 2636 .Case("amdfam10", CK_AMDFAM10) 2637 .Case("btver1", CK_BTVER1) 2638 .Case("btver2", CK_BTVER2) 2639 .Case("bdver1", CK_BDVER1) 2640 .Case("bdver2", CK_BDVER2) 2641 .Case("bdver3", CK_BDVER3) 2642 .Case("bdver4", CK_BDVER4) 2643 .Case("x86-64", CK_x86_64) 2644 .Case("geode", CK_Geode) 2645 .Default(CK_Generic); 2646 } 2647 2648 enum FPMathKind { 2649 FP_Default, 2650 FP_SSE, 2651 FP_387 2652 } FPMath = FP_Default; 2653 2654 public: 2655 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2656 : TargetInfo(Triple) { 2657 BigEndian = false; 2658 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2659 } 2660 unsigned getFloatEvalMethod() const override { 2661 // X87 evaluates with 80 bits "long double" precision. 2662 return SSELevel == NoSSE ? 2 : 0; 2663 } 2664 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2665 return llvm::makeArrayRef(BuiltinInfo, 2666 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2667 } 2668 ArrayRef<const char *> getGCCRegNames() const override { 2669 return llvm::makeArrayRef(GCCRegNames); 2670 } 2671 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2672 return None; 2673 } 2674 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2675 return llvm::makeArrayRef(AddlRegNames); 2676 } 2677 bool validateCpuSupports(StringRef Name) const override; 2678 bool validateAsmConstraint(const char *&Name, 2679 TargetInfo::ConstraintInfo &info) const override; 2680 2681 bool validateGlobalRegisterVariable(StringRef RegName, 2682 unsigned RegSize, 2683 bool &HasSizeMismatch) const override { 2684 // esp and ebp are the only 32-bit registers the x86 backend can currently 2685 // handle. 2686 if (RegName.equals("esp") || RegName.equals("ebp")) { 2687 // Check that the register size is 32-bit. 2688 HasSizeMismatch = RegSize != 32; 2689 return true; 2690 } 2691 2692 return false; 2693 } 2694 2695 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2696 2697 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2698 2699 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2700 2701 std::string convertConstraint(const char *&Constraint) const override; 2702 const char *getClobbers() const override { 2703 return "~{dirflag},~{fpsr},~{flags}"; 2704 } 2705 void getTargetDefines(const LangOptions &Opts, 2706 MacroBuilder &Builder) const override; 2707 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2708 bool Enabled); 2709 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2710 bool Enabled); 2711 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2712 bool Enabled); 2713 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2714 StringRef Name, bool Enabled) const override { 2715 setFeatureEnabledImpl(Features, Name, Enabled); 2716 } 2717 // This exists purely to cut down on the number of virtual calls in 2718 // initFeatureMap which calls this repeatedly. 2719 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2720 StringRef Name, bool Enabled); 2721 bool 2722 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2723 StringRef CPU, 2724 const std::vector<std::string> &FeaturesVec) const override; 2725 bool hasFeature(StringRef Feature) const override; 2726 bool handleTargetFeatures(std::vector<std::string> &Features, 2727 DiagnosticsEngine &Diags) override; 2728 StringRef getABI() const override { 2729 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2730 return "avx512"; 2731 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2732 return "avx"; 2733 if (getTriple().getArch() == llvm::Triple::x86 && 2734 MMX3DNowLevel == NoMMX3DNow) 2735 return "no-mmx"; 2736 return ""; 2737 } 2738 bool setCPU(const std::string &Name) override { 2739 CPU = getCPUKind(Name); 2740 2741 // Perform any per-CPU checks necessary to determine if this CPU is 2742 // acceptable. 2743 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2744 // invalid without explaining *why*. 2745 switch (CPU) { 2746 case CK_Generic: 2747 // No processor selected! 2748 return false; 2749 2750 case CK_i386: 2751 case CK_i486: 2752 case CK_WinChipC6: 2753 case CK_WinChip2: 2754 case CK_C3: 2755 case CK_i586: 2756 case CK_Pentium: 2757 case CK_PentiumMMX: 2758 case CK_i686: 2759 case CK_PentiumPro: 2760 case CK_Pentium2: 2761 case CK_Pentium3: 2762 case CK_Pentium3M: 2763 case CK_PentiumM: 2764 case CK_Yonah: 2765 case CK_C3_2: 2766 case CK_Pentium4: 2767 case CK_Pentium4M: 2768 case CK_Lakemont: 2769 case CK_Prescott: 2770 case CK_K6: 2771 case CK_K6_2: 2772 case CK_K6_3: 2773 case CK_Athlon: 2774 case CK_AthlonThunderbird: 2775 case CK_Athlon4: 2776 case CK_AthlonXP: 2777 case CK_AthlonMP: 2778 case CK_Geode: 2779 // Only accept certain architectures when compiling in 32-bit mode. 2780 if (getTriple().getArch() != llvm::Triple::x86) 2781 return false; 2782 2783 // Fallthrough 2784 case CK_Nocona: 2785 case CK_Core2: 2786 case CK_Penryn: 2787 case CK_Bonnell: 2788 case CK_Silvermont: 2789 case CK_Nehalem: 2790 case CK_Westmere: 2791 case CK_SandyBridge: 2792 case CK_IvyBridge: 2793 case CK_Haswell: 2794 case CK_Broadwell: 2795 case CK_SkylakeClient: 2796 case CK_SkylakeServer: 2797 case CK_Cannonlake: 2798 case CK_KNL: 2799 case CK_Athlon64: 2800 case CK_Athlon64SSE3: 2801 case CK_AthlonFX: 2802 case CK_K8: 2803 case CK_K8SSE3: 2804 case CK_Opteron: 2805 case CK_OpteronSSE3: 2806 case CK_AMDFAM10: 2807 case CK_BTVER1: 2808 case CK_BTVER2: 2809 case CK_BDVER1: 2810 case CK_BDVER2: 2811 case CK_BDVER3: 2812 case CK_BDVER4: 2813 case CK_x86_64: 2814 return true; 2815 } 2816 llvm_unreachable("Unhandled CPU kind"); 2817 } 2818 2819 bool setFPMath(StringRef Name) override; 2820 2821 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2822 // Most of the non-ARM calling conventions are i386 conventions. 2823 switch (CC) { 2824 case CC_X86ThisCall: 2825 case CC_X86FastCall: 2826 case CC_X86StdCall: 2827 case CC_X86VectorCall: 2828 case CC_C: 2829 case CC_Swift: 2830 case CC_X86Pascal: 2831 case CC_IntelOclBicc: 2832 return CCCR_OK; 2833 default: 2834 return CCCR_Warning; 2835 } 2836 } 2837 2838 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2839 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2840 } 2841 2842 bool hasSjLjLowering() const override { 2843 return true; 2844 } 2845 2846 void setSupportedOpenCLOpts() override { 2847 getSupportedOpenCLOpts().setAll(); 2848 } 2849 }; 2850 2851 bool X86TargetInfo::setFPMath(StringRef Name) { 2852 if (Name == "387") { 2853 FPMath = FP_387; 2854 return true; 2855 } 2856 if (Name == "sse") { 2857 FPMath = FP_SSE; 2858 return true; 2859 } 2860 return false; 2861 } 2862 2863 bool X86TargetInfo::initFeatureMap( 2864 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2865 const std::vector<std::string> &FeaturesVec) const { 2866 // FIXME: This *really* should not be here. 2867 // X86_64 always has SSE2. 2868 if (getTriple().getArch() == llvm::Triple::x86_64) 2869 setFeatureEnabledImpl(Features, "sse2", true); 2870 2871 const CPUKind Kind = getCPUKind(CPU); 2872 2873 // Enable X87 for all X86 processors but Lakemont. 2874 if (Kind != CK_Lakemont) 2875 setFeatureEnabledImpl(Features, "x87", true); 2876 2877 switch (Kind) { 2878 case CK_Generic: 2879 case CK_i386: 2880 case CK_i486: 2881 case CK_i586: 2882 case CK_Pentium: 2883 case CK_i686: 2884 case CK_PentiumPro: 2885 case CK_Lakemont: 2886 break; 2887 case CK_PentiumMMX: 2888 case CK_Pentium2: 2889 case CK_K6: 2890 case CK_WinChipC6: 2891 setFeatureEnabledImpl(Features, "mmx", true); 2892 break; 2893 case CK_Pentium3: 2894 case CK_Pentium3M: 2895 case CK_C3_2: 2896 setFeatureEnabledImpl(Features, "sse", true); 2897 setFeatureEnabledImpl(Features, "fxsr", true); 2898 break; 2899 case CK_PentiumM: 2900 case CK_Pentium4: 2901 case CK_Pentium4M: 2902 case CK_x86_64: 2903 setFeatureEnabledImpl(Features, "sse2", true); 2904 setFeatureEnabledImpl(Features, "fxsr", true); 2905 break; 2906 case CK_Yonah: 2907 case CK_Prescott: 2908 case CK_Nocona: 2909 setFeatureEnabledImpl(Features, "sse3", true); 2910 setFeatureEnabledImpl(Features, "fxsr", true); 2911 setFeatureEnabledImpl(Features, "cx16", true); 2912 break; 2913 case CK_Core2: 2914 case CK_Bonnell: 2915 setFeatureEnabledImpl(Features, "ssse3", true); 2916 setFeatureEnabledImpl(Features, "fxsr", true); 2917 setFeatureEnabledImpl(Features, "cx16", true); 2918 break; 2919 case CK_Penryn: 2920 setFeatureEnabledImpl(Features, "sse4.1", true); 2921 setFeatureEnabledImpl(Features, "fxsr", true); 2922 setFeatureEnabledImpl(Features, "cx16", true); 2923 break; 2924 case CK_Cannonlake: 2925 setFeatureEnabledImpl(Features, "avx512ifma", true); 2926 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2927 setFeatureEnabledImpl(Features, "sha", true); 2928 setFeatureEnabledImpl(Features, "umip", true); 2929 // FALLTHROUGH 2930 case CK_SkylakeServer: 2931 setFeatureEnabledImpl(Features, "avx512f", true); 2932 setFeatureEnabledImpl(Features, "avx512cd", true); 2933 setFeatureEnabledImpl(Features, "avx512dq", true); 2934 setFeatureEnabledImpl(Features, "avx512bw", true); 2935 setFeatureEnabledImpl(Features, "avx512vl", true); 2936 setFeatureEnabledImpl(Features, "pku", true); 2937 setFeatureEnabledImpl(Features, "pcommit", true); 2938 setFeatureEnabledImpl(Features, "clwb", true); 2939 // FALLTHROUGH 2940 case CK_SkylakeClient: 2941 setFeatureEnabledImpl(Features, "xsavec", true); 2942 setFeatureEnabledImpl(Features, "xsaves", true); 2943 setFeatureEnabledImpl(Features, "mpx", true); 2944 setFeatureEnabledImpl(Features, "sgx", true); 2945 setFeatureEnabledImpl(Features, "clflushopt", true); 2946 // FALLTHROUGH 2947 case CK_Broadwell: 2948 setFeatureEnabledImpl(Features, "rdseed", true); 2949 setFeatureEnabledImpl(Features, "adx", true); 2950 // FALLTHROUGH 2951 case CK_Haswell: 2952 setFeatureEnabledImpl(Features, "avx2", true); 2953 setFeatureEnabledImpl(Features, "lzcnt", true); 2954 setFeatureEnabledImpl(Features, "bmi", true); 2955 setFeatureEnabledImpl(Features, "bmi2", true); 2956 setFeatureEnabledImpl(Features, "rtm", true); 2957 setFeatureEnabledImpl(Features, "fma", true); 2958 setFeatureEnabledImpl(Features, "movbe", true); 2959 // FALLTHROUGH 2960 case CK_IvyBridge: 2961 setFeatureEnabledImpl(Features, "rdrnd", true); 2962 setFeatureEnabledImpl(Features, "f16c", true); 2963 setFeatureEnabledImpl(Features, "fsgsbase", true); 2964 // FALLTHROUGH 2965 case CK_SandyBridge: 2966 setFeatureEnabledImpl(Features, "avx", true); 2967 setFeatureEnabledImpl(Features, "xsave", true); 2968 setFeatureEnabledImpl(Features, "xsaveopt", true); 2969 // FALLTHROUGH 2970 case CK_Westmere: 2971 case CK_Silvermont: 2972 setFeatureEnabledImpl(Features, "aes", true); 2973 setFeatureEnabledImpl(Features, "pclmul", true); 2974 // FALLTHROUGH 2975 case CK_Nehalem: 2976 setFeatureEnabledImpl(Features, "sse4.2", true); 2977 setFeatureEnabledImpl(Features, "fxsr", true); 2978 setFeatureEnabledImpl(Features, "cx16", true); 2979 break; 2980 case CK_KNL: 2981 setFeatureEnabledImpl(Features, "avx512f", true); 2982 setFeatureEnabledImpl(Features, "avx512cd", true); 2983 setFeatureEnabledImpl(Features, "avx512er", true); 2984 setFeatureEnabledImpl(Features, "avx512pf", true); 2985 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2986 setFeatureEnabledImpl(Features, "fxsr", true); 2987 setFeatureEnabledImpl(Features, "rdseed", true); 2988 setFeatureEnabledImpl(Features, "adx", true); 2989 setFeatureEnabledImpl(Features, "lzcnt", true); 2990 setFeatureEnabledImpl(Features, "bmi", true); 2991 setFeatureEnabledImpl(Features, "bmi2", true); 2992 setFeatureEnabledImpl(Features, "rtm", true); 2993 setFeatureEnabledImpl(Features, "fma", true); 2994 setFeatureEnabledImpl(Features, "rdrnd", true); 2995 setFeatureEnabledImpl(Features, "f16c", true); 2996 setFeatureEnabledImpl(Features, "fsgsbase", true); 2997 setFeatureEnabledImpl(Features, "aes", true); 2998 setFeatureEnabledImpl(Features, "pclmul", true); 2999 setFeatureEnabledImpl(Features, "cx16", true); 3000 setFeatureEnabledImpl(Features, "xsaveopt", true); 3001 setFeatureEnabledImpl(Features, "xsave", true); 3002 setFeatureEnabledImpl(Features, "movbe", true); 3003 break; 3004 case CK_K6_2: 3005 case CK_K6_3: 3006 case CK_WinChip2: 3007 case CK_C3: 3008 setFeatureEnabledImpl(Features, "3dnow", true); 3009 break; 3010 case CK_Athlon: 3011 case CK_AthlonThunderbird: 3012 case CK_Geode: 3013 setFeatureEnabledImpl(Features, "3dnowa", true); 3014 break; 3015 case CK_Athlon4: 3016 case CK_AthlonXP: 3017 case CK_AthlonMP: 3018 setFeatureEnabledImpl(Features, "sse", true); 3019 setFeatureEnabledImpl(Features, "3dnowa", true); 3020 setFeatureEnabledImpl(Features, "fxsr", true); 3021 break; 3022 case CK_K8: 3023 case CK_Opteron: 3024 case CK_Athlon64: 3025 case CK_AthlonFX: 3026 setFeatureEnabledImpl(Features, "sse2", true); 3027 setFeatureEnabledImpl(Features, "3dnowa", true); 3028 setFeatureEnabledImpl(Features, "fxsr", true); 3029 break; 3030 case CK_AMDFAM10: 3031 setFeatureEnabledImpl(Features, "sse4a", true); 3032 setFeatureEnabledImpl(Features, "lzcnt", true); 3033 setFeatureEnabledImpl(Features, "popcnt", true); 3034 // FALLTHROUGH 3035 case CK_K8SSE3: 3036 case CK_OpteronSSE3: 3037 case CK_Athlon64SSE3: 3038 setFeatureEnabledImpl(Features, "sse3", true); 3039 setFeatureEnabledImpl(Features, "3dnowa", true); 3040 setFeatureEnabledImpl(Features, "fxsr", true); 3041 break; 3042 case CK_BTVER2: 3043 setFeatureEnabledImpl(Features, "avx", true); 3044 setFeatureEnabledImpl(Features, "aes", true); 3045 setFeatureEnabledImpl(Features, "pclmul", true); 3046 setFeatureEnabledImpl(Features, "bmi", true); 3047 setFeatureEnabledImpl(Features, "f16c", true); 3048 setFeatureEnabledImpl(Features, "xsaveopt", true); 3049 // FALLTHROUGH 3050 case CK_BTVER1: 3051 setFeatureEnabledImpl(Features, "ssse3", true); 3052 setFeatureEnabledImpl(Features, "sse4a", true); 3053 setFeatureEnabledImpl(Features, "lzcnt", true); 3054 setFeatureEnabledImpl(Features, "popcnt", true); 3055 setFeatureEnabledImpl(Features, "prfchw", true); 3056 setFeatureEnabledImpl(Features, "cx16", true); 3057 setFeatureEnabledImpl(Features, "fxsr", true); 3058 break; 3059 case CK_BDVER4: 3060 setFeatureEnabledImpl(Features, "avx2", true); 3061 setFeatureEnabledImpl(Features, "bmi2", true); 3062 setFeatureEnabledImpl(Features, "mwaitx", true); 3063 // FALLTHROUGH 3064 case CK_BDVER3: 3065 setFeatureEnabledImpl(Features, "fsgsbase", true); 3066 setFeatureEnabledImpl(Features, "xsaveopt", true); 3067 // FALLTHROUGH 3068 case CK_BDVER2: 3069 setFeatureEnabledImpl(Features, "bmi", true); 3070 setFeatureEnabledImpl(Features, "fma", true); 3071 setFeatureEnabledImpl(Features, "f16c", true); 3072 setFeatureEnabledImpl(Features, "tbm", true); 3073 // FALLTHROUGH 3074 case CK_BDVER1: 3075 // xop implies avx, sse4a and fma4. 3076 setFeatureEnabledImpl(Features, "xop", true); 3077 setFeatureEnabledImpl(Features, "lzcnt", true); 3078 setFeatureEnabledImpl(Features, "aes", true); 3079 setFeatureEnabledImpl(Features, "pclmul", true); 3080 setFeatureEnabledImpl(Features, "prfchw", true); 3081 setFeatureEnabledImpl(Features, "cx16", true); 3082 setFeatureEnabledImpl(Features, "fxsr", true); 3083 setFeatureEnabledImpl(Features, "xsave", true); 3084 break; 3085 } 3086 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3087 return false; 3088 3089 // Can't do this earlier because we need to be able to explicitly enable 3090 // or disable these features and the things that they depend upon. 3091 3092 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3093 auto I = Features.find("sse4.2"); 3094 if (I != Features.end() && I->getValue() && 3095 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3096 FeaturesVec.end()) 3097 Features["popcnt"] = true; 3098 3099 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3100 I = Features.find("3dnow"); 3101 if (I != Features.end() && I->getValue() && 3102 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3103 FeaturesVec.end()) 3104 Features["prfchw"] = true; 3105 3106 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3107 // then enable MMX. 3108 I = Features.find("sse"); 3109 if (I != Features.end() && I->getValue() && 3110 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3111 FeaturesVec.end()) 3112 Features["mmx"] = true; 3113 3114 return true; 3115 } 3116 3117 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3118 X86SSEEnum Level, bool Enabled) { 3119 if (Enabled) { 3120 switch (Level) { 3121 case AVX512F: 3122 Features["avx512f"] = true; 3123 case AVX2: 3124 Features["avx2"] = true; 3125 case AVX: 3126 Features["avx"] = true; 3127 Features["xsave"] = true; 3128 case SSE42: 3129 Features["sse4.2"] = true; 3130 case SSE41: 3131 Features["sse4.1"] = true; 3132 case SSSE3: 3133 Features["ssse3"] = true; 3134 case SSE3: 3135 Features["sse3"] = true; 3136 case SSE2: 3137 Features["sse2"] = true; 3138 case SSE1: 3139 Features["sse"] = true; 3140 case NoSSE: 3141 break; 3142 } 3143 return; 3144 } 3145 3146 switch (Level) { 3147 case NoSSE: 3148 case SSE1: 3149 Features["sse"] = false; 3150 case SSE2: 3151 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3152 Features["sha"] = false; 3153 case SSE3: 3154 Features["sse3"] = false; 3155 setXOPLevel(Features, NoXOP, false); 3156 case SSSE3: 3157 Features["ssse3"] = false; 3158 case SSE41: 3159 Features["sse4.1"] = false; 3160 case SSE42: 3161 Features["sse4.2"] = false; 3162 case AVX: 3163 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3164 Features["xsaveopt"] = false; 3165 setXOPLevel(Features, FMA4, false); 3166 case AVX2: 3167 Features["avx2"] = false; 3168 case AVX512F: 3169 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3170 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3171 Features["avx512vl"] = Features["avx512vbmi"] = 3172 Features["avx512ifma"] = false; 3173 } 3174 } 3175 3176 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3177 MMX3DNowEnum Level, bool Enabled) { 3178 if (Enabled) { 3179 switch (Level) { 3180 case AMD3DNowAthlon: 3181 Features["3dnowa"] = true; 3182 case AMD3DNow: 3183 Features["3dnow"] = true; 3184 case MMX: 3185 Features["mmx"] = true; 3186 case NoMMX3DNow: 3187 break; 3188 } 3189 return; 3190 } 3191 3192 switch (Level) { 3193 case NoMMX3DNow: 3194 case MMX: 3195 Features["mmx"] = false; 3196 case AMD3DNow: 3197 Features["3dnow"] = false; 3198 case AMD3DNowAthlon: 3199 Features["3dnowa"] = false; 3200 } 3201 } 3202 3203 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3204 bool Enabled) { 3205 if (Enabled) { 3206 switch (Level) { 3207 case XOP: 3208 Features["xop"] = true; 3209 case FMA4: 3210 Features["fma4"] = true; 3211 setSSELevel(Features, AVX, true); 3212 case SSE4A: 3213 Features["sse4a"] = true; 3214 setSSELevel(Features, SSE3, true); 3215 case NoXOP: 3216 break; 3217 } 3218 return; 3219 } 3220 3221 switch (Level) { 3222 case NoXOP: 3223 case SSE4A: 3224 Features["sse4a"] = false; 3225 case FMA4: 3226 Features["fma4"] = false; 3227 case XOP: 3228 Features["xop"] = false; 3229 } 3230 } 3231 3232 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3233 StringRef Name, bool Enabled) { 3234 // This is a bit of a hack to deal with the sse4 target feature when used 3235 // as part of the target attribute. We handle sse4 correctly everywhere 3236 // else. See below for more information on how we handle the sse4 options. 3237 if (Name != "sse4") 3238 Features[Name] = Enabled; 3239 3240 if (Name == "mmx") { 3241 setMMXLevel(Features, MMX, Enabled); 3242 } else if (Name == "sse") { 3243 setSSELevel(Features, SSE1, Enabled); 3244 } else if (Name == "sse2") { 3245 setSSELevel(Features, SSE2, Enabled); 3246 } else if (Name == "sse3") { 3247 setSSELevel(Features, SSE3, Enabled); 3248 } else if (Name == "ssse3") { 3249 setSSELevel(Features, SSSE3, Enabled); 3250 } else if (Name == "sse4.2") { 3251 setSSELevel(Features, SSE42, Enabled); 3252 } else if (Name == "sse4.1") { 3253 setSSELevel(Features, SSE41, Enabled); 3254 } else if (Name == "3dnow") { 3255 setMMXLevel(Features, AMD3DNow, Enabled); 3256 } else if (Name == "3dnowa") { 3257 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3258 } else if (Name == "aes") { 3259 if (Enabled) 3260 setSSELevel(Features, SSE2, Enabled); 3261 } else if (Name == "pclmul") { 3262 if (Enabled) 3263 setSSELevel(Features, SSE2, Enabled); 3264 } else if (Name == "avx") { 3265 setSSELevel(Features, AVX, Enabled); 3266 } else if (Name == "avx2") { 3267 setSSELevel(Features, AVX2, Enabled); 3268 } else if (Name == "avx512f") { 3269 setSSELevel(Features, AVX512F, Enabled); 3270 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3271 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3272 Name == "avx512vbmi" || Name == "avx512ifma") { 3273 if (Enabled) 3274 setSSELevel(Features, AVX512F, Enabled); 3275 } else if (Name == "fma") { 3276 if (Enabled) 3277 setSSELevel(Features, AVX, Enabled); 3278 } else if (Name == "fma4") { 3279 setXOPLevel(Features, FMA4, Enabled); 3280 } else if (Name == "xop") { 3281 setXOPLevel(Features, XOP, Enabled); 3282 } else if (Name == "sse4a") { 3283 setXOPLevel(Features, SSE4A, Enabled); 3284 } else if (Name == "f16c") { 3285 if (Enabled) 3286 setSSELevel(Features, AVX, Enabled); 3287 } else if (Name == "sha") { 3288 if (Enabled) 3289 setSSELevel(Features, SSE2, Enabled); 3290 } else if (Name == "sse4") { 3291 // We can get here via the __target__ attribute since that's not controlled 3292 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3293 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3294 // disabled. 3295 if (Enabled) 3296 setSSELevel(Features, SSE42, Enabled); 3297 else 3298 setSSELevel(Features, SSE41, Enabled); 3299 } else if (Name == "xsave") { 3300 if (!Enabled) 3301 Features["xsaveopt"] = false; 3302 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3303 if (Enabled) 3304 Features["xsave"] = true; 3305 } 3306 } 3307 3308 /// handleTargetFeatures - Perform initialization based on the user 3309 /// configured set of features. 3310 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3311 DiagnosticsEngine &Diags) { 3312 for (const auto &Feature : Features) { 3313 if (Feature[0] != '+') 3314 continue; 3315 3316 if (Feature == "+aes") { 3317 HasAES = true; 3318 } else if (Feature == "+pclmul") { 3319 HasPCLMUL = true; 3320 } else if (Feature == "+lzcnt") { 3321 HasLZCNT = true; 3322 } else if (Feature == "+rdrnd") { 3323 HasRDRND = true; 3324 } else if (Feature == "+fsgsbase") { 3325 HasFSGSBASE = true; 3326 } else if (Feature == "+bmi") { 3327 HasBMI = true; 3328 } else if (Feature == "+bmi2") { 3329 HasBMI2 = true; 3330 } else if (Feature == "+popcnt") { 3331 HasPOPCNT = true; 3332 } else if (Feature == "+rtm") { 3333 HasRTM = true; 3334 } else if (Feature == "+prfchw") { 3335 HasPRFCHW = true; 3336 } else if (Feature == "+rdseed") { 3337 HasRDSEED = true; 3338 } else if (Feature == "+adx") { 3339 HasADX = true; 3340 } else if (Feature == "+tbm") { 3341 HasTBM = true; 3342 } else if (Feature == "+fma") { 3343 HasFMA = true; 3344 } else if (Feature == "+f16c") { 3345 HasF16C = true; 3346 } else if (Feature == "+avx512cd") { 3347 HasAVX512CD = true; 3348 } else if (Feature == "+avx512er") { 3349 HasAVX512ER = true; 3350 } else if (Feature == "+avx512pf") { 3351 HasAVX512PF = true; 3352 } else if (Feature == "+avx512dq") { 3353 HasAVX512DQ = true; 3354 } else if (Feature == "+avx512bw") { 3355 HasAVX512BW = true; 3356 } else if (Feature == "+avx512vl") { 3357 HasAVX512VL = true; 3358 } else if (Feature == "+avx512vbmi") { 3359 HasAVX512VBMI = true; 3360 } else if (Feature == "+avx512ifma") { 3361 HasAVX512IFMA = true; 3362 } else if (Feature == "+sha") { 3363 HasSHA = true; 3364 } else if (Feature == "+mpx") { 3365 HasMPX = true; 3366 } else if (Feature == "+movbe") { 3367 HasMOVBE = true; 3368 } else if (Feature == "+sgx") { 3369 HasSGX = true; 3370 } else if (Feature == "+cx16") { 3371 HasCX16 = true; 3372 } else if (Feature == "+fxsr") { 3373 HasFXSR = true; 3374 } else if (Feature == "+xsave") { 3375 HasXSAVE = true; 3376 } else if (Feature == "+xsaveopt") { 3377 HasXSAVEOPT = true; 3378 } else if (Feature == "+xsavec") { 3379 HasXSAVEC = true; 3380 } else if (Feature == "+xsaves") { 3381 HasXSAVES = true; 3382 } else if (Feature == "+mwaitx") { 3383 HasMWAITX = true; 3384 } else if (Feature == "+pku") { 3385 HasPKU = true; 3386 } else if (Feature == "+clflushopt") { 3387 HasCLFLUSHOPT = true; 3388 } else if (Feature == "+pcommit") { 3389 HasPCOMMIT = true; 3390 } else if (Feature == "+clwb") { 3391 HasCLWB = true; 3392 } else if (Feature == "+umip") { 3393 HasUMIP = true; 3394 } else if (Feature == "+prefetchwt1") { 3395 HasPREFETCHWT1 = true; 3396 } 3397 3398 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3399 .Case("+avx512f", AVX512F) 3400 .Case("+avx2", AVX2) 3401 .Case("+avx", AVX) 3402 .Case("+sse4.2", SSE42) 3403 .Case("+sse4.1", SSE41) 3404 .Case("+ssse3", SSSE3) 3405 .Case("+sse3", SSE3) 3406 .Case("+sse2", SSE2) 3407 .Case("+sse", SSE1) 3408 .Default(NoSSE); 3409 SSELevel = std::max(SSELevel, Level); 3410 3411 MMX3DNowEnum ThreeDNowLevel = 3412 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3413 .Case("+3dnowa", AMD3DNowAthlon) 3414 .Case("+3dnow", AMD3DNow) 3415 .Case("+mmx", MMX) 3416 .Default(NoMMX3DNow); 3417 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3418 3419 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3420 .Case("+xop", XOP) 3421 .Case("+fma4", FMA4) 3422 .Case("+sse4a", SSE4A) 3423 .Default(NoXOP); 3424 XOPLevel = std::max(XOPLevel, XLevel); 3425 } 3426 3427 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3428 // matches the selected sse level. 3429 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3430 (FPMath == FP_387 && SSELevel >= SSE1)) { 3431 Diags.Report(diag::err_target_unsupported_fpmath) << 3432 (FPMath == FP_SSE ? "sse" : "387"); 3433 return false; 3434 } 3435 3436 SimdDefaultAlign = 3437 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3438 return true; 3439 } 3440 3441 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3442 /// definitions for this particular subtarget. 3443 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3444 MacroBuilder &Builder) const { 3445 // Target identification. 3446 if (getTriple().getArch() == llvm::Triple::x86_64) { 3447 Builder.defineMacro("__amd64__"); 3448 Builder.defineMacro("__amd64"); 3449 Builder.defineMacro("__x86_64"); 3450 Builder.defineMacro("__x86_64__"); 3451 if (getTriple().getArchName() == "x86_64h") { 3452 Builder.defineMacro("__x86_64h"); 3453 Builder.defineMacro("__x86_64h__"); 3454 } 3455 } else { 3456 DefineStd(Builder, "i386", Opts); 3457 } 3458 3459 // Subtarget options. 3460 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3461 // truly should be based on -mtune options. 3462 switch (CPU) { 3463 case CK_Generic: 3464 break; 3465 case CK_i386: 3466 // The rest are coming from the i386 define above. 3467 Builder.defineMacro("__tune_i386__"); 3468 break; 3469 case CK_i486: 3470 case CK_WinChipC6: 3471 case CK_WinChip2: 3472 case CK_C3: 3473 defineCPUMacros(Builder, "i486"); 3474 break; 3475 case CK_PentiumMMX: 3476 Builder.defineMacro("__pentium_mmx__"); 3477 Builder.defineMacro("__tune_pentium_mmx__"); 3478 // Fallthrough 3479 case CK_i586: 3480 case CK_Pentium: 3481 defineCPUMacros(Builder, "i586"); 3482 defineCPUMacros(Builder, "pentium"); 3483 break; 3484 case CK_Pentium3: 3485 case CK_Pentium3M: 3486 case CK_PentiumM: 3487 Builder.defineMacro("__tune_pentium3__"); 3488 // Fallthrough 3489 case CK_Pentium2: 3490 case CK_C3_2: 3491 Builder.defineMacro("__tune_pentium2__"); 3492 // Fallthrough 3493 case CK_PentiumPro: 3494 Builder.defineMacro("__tune_i686__"); 3495 Builder.defineMacro("__tune_pentiumpro__"); 3496 // Fallthrough 3497 case CK_i686: 3498 Builder.defineMacro("__i686"); 3499 Builder.defineMacro("__i686__"); 3500 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3501 Builder.defineMacro("__pentiumpro"); 3502 Builder.defineMacro("__pentiumpro__"); 3503 break; 3504 case CK_Pentium4: 3505 case CK_Pentium4M: 3506 defineCPUMacros(Builder, "pentium4"); 3507 break; 3508 case CK_Yonah: 3509 case CK_Prescott: 3510 case CK_Nocona: 3511 defineCPUMacros(Builder, "nocona"); 3512 break; 3513 case CK_Core2: 3514 case CK_Penryn: 3515 defineCPUMacros(Builder, "core2"); 3516 break; 3517 case CK_Bonnell: 3518 defineCPUMacros(Builder, "atom"); 3519 break; 3520 case CK_Silvermont: 3521 defineCPUMacros(Builder, "slm"); 3522 break; 3523 case CK_Nehalem: 3524 case CK_Westmere: 3525 case CK_SandyBridge: 3526 case CK_IvyBridge: 3527 case CK_Haswell: 3528 case CK_Broadwell: 3529 case CK_SkylakeClient: 3530 // FIXME: Historically, we defined this legacy name, it would be nice to 3531 // remove it at some point. We've never exposed fine-grained names for 3532 // recent primary x86 CPUs, and we should keep it that way. 3533 defineCPUMacros(Builder, "corei7"); 3534 break; 3535 case CK_SkylakeServer: 3536 defineCPUMacros(Builder, "skx"); 3537 break; 3538 case CK_Cannonlake: 3539 break; 3540 case CK_KNL: 3541 defineCPUMacros(Builder, "knl"); 3542 break; 3543 case CK_Lakemont: 3544 Builder.defineMacro("__tune_lakemont__"); 3545 break; 3546 case CK_K6_2: 3547 Builder.defineMacro("__k6_2__"); 3548 Builder.defineMacro("__tune_k6_2__"); 3549 // Fallthrough 3550 case CK_K6_3: 3551 if (CPU != CK_K6_2) { // In case of fallthrough 3552 // FIXME: GCC may be enabling these in cases where some other k6 3553 // architecture is specified but -m3dnow is explicitly provided. The 3554 // exact semantics need to be determined and emulated here. 3555 Builder.defineMacro("__k6_3__"); 3556 Builder.defineMacro("__tune_k6_3__"); 3557 } 3558 // Fallthrough 3559 case CK_K6: 3560 defineCPUMacros(Builder, "k6"); 3561 break; 3562 case CK_Athlon: 3563 case CK_AthlonThunderbird: 3564 case CK_Athlon4: 3565 case CK_AthlonXP: 3566 case CK_AthlonMP: 3567 defineCPUMacros(Builder, "athlon"); 3568 if (SSELevel != NoSSE) { 3569 Builder.defineMacro("__athlon_sse__"); 3570 Builder.defineMacro("__tune_athlon_sse__"); 3571 } 3572 break; 3573 case CK_K8: 3574 case CK_K8SSE3: 3575 case CK_x86_64: 3576 case CK_Opteron: 3577 case CK_OpteronSSE3: 3578 case CK_Athlon64: 3579 case CK_Athlon64SSE3: 3580 case CK_AthlonFX: 3581 defineCPUMacros(Builder, "k8"); 3582 break; 3583 case CK_AMDFAM10: 3584 defineCPUMacros(Builder, "amdfam10"); 3585 break; 3586 case CK_BTVER1: 3587 defineCPUMacros(Builder, "btver1"); 3588 break; 3589 case CK_BTVER2: 3590 defineCPUMacros(Builder, "btver2"); 3591 break; 3592 case CK_BDVER1: 3593 defineCPUMacros(Builder, "bdver1"); 3594 break; 3595 case CK_BDVER2: 3596 defineCPUMacros(Builder, "bdver2"); 3597 break; 3598 case CK_BDVER3: 3599 defineCPUMacros(Builder, "bdver3"); 3600 break; 3601 case CK_BDVER4: 3602 defineCPUMacros(Builder, "bdver4"); 3603 break; 3604 case CK_Geode: 3605 defineCPUMacros(Builder, "geode"); 3606 break; 3607 } 3608 3609 // Target properties. 3610 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3611 3612 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3613 // functions in glibc header files that use FP Stack inline asm which the 3614 // backend can't deal with (PR879). 3615 Builder.defineMacro("__NO_MATH_INLINES"); 3616 3617 if (HasAES) 3618 Builder.defineMacro("__AES__"); 3619 3620 if (HasPCLMUL) 3621 Builder.defineMacro("__PCLMUL__"); 3622 3623 if (HasLZCNT) 3624 Builder.defineMacro("__LZCNT__"); 3625 3626 if (HasRDRND) 3627 Builder.defineMacro("__RDRND__"); 3628 3629 if (HasFSGSBASE) 3630 Builder.defineMacro("__FSGSBASE__"); 3631 3632 if (HasBMI) 3633 Builder.defineMacro("__BMI__"); 3634 3635 if (HasBMI2) 3636 Builder.defineMacro("__BMI2__"); 3637 3638 if (HasPOPCNT) 3639 Builder.defineMacro("__POPCNT__"); 3640 3641 if (HasRTM) 3642 Builder.defineMacro("__RTM__"); 3643 3644 if (HasPRFCHW) 3645 Builder.defineMacro("__PRFCHW__"); 3646 3647 if (HasRDSEED) 3648 Builder.defineMacro("__RDSEED__"); 3649 3650 if (HasADX) 3651 Builder.defineMacro("__ADX__"); 3652 3653 if (HasTBM) 3654 Builder.defineMacro("__TBM__"); 3655 3656 if (HasMWAITX) 3657 Builder.defineMacro("__MWAITX__"); 3658 3659 switch (XOPLevel) { 3660 case XOP: 3661 Builder.defineMacro("__XOP__"); 3662 case FMA4: 3663 Builder.defineMacro("__FMA4__"); 3664 case SSE4A: 3665 Builder.defineMacro("__SSE4A__"); 3666 case NoXOP: 3667 break; 3668 } 3669 3670 if (HasFMA) 3671 Builder.defineMacro("__FMA__"); 3672 3673 if (HasF16C) 3674 Builder.defineMacro("__F16C__"); 3675 3676 if (HasAVX512CD) 3677 Builder.defineMacro("__AVX512CD__"); 3678 if (HasAVX512ER) 3679 Builder.defineMacro("__AVX512ER__"); 3680 if (HasAVX512PF) 3681 Builder.defineMacro("__AVX512PF__"); 3682 if (HasAVX512DQ) 3683 Builder.defineMacro("__AVX512DQ__"); 3684 if (HasAVX512BW) 3685 Builder.defineMacro("__AVX512BW__"); 3686 if (HasAVX512VL) 3687 Builder.defineMacro("__AVX512VL__"); 3688 if (HasAVX512VBMI) 3689 Builder.defineMacro("__AVX512VBMI__"); 3690 if (HasAVX512IFMA) 3691 Builder.defineMacro("__AVX512IFMA__"); 3692 3693 if (HasSHA) 3694 Builder.defineMacro("__SHA__"); 3695 3696 if (HasFXSR) 3697 Builder.defineMacro("__FXSR__"); 3698 if (HasXSAVE) 3699 Builder.defineMacro("__XSAVE__"); 3700 if (HasXSAVEOPT) 3701 Builder.defineMacro("__XSAVEOPT__"); 3702 if (HasXSAVEC) 3703 Builder.defineMacro("__XSAVEC__"); 3704 if (HasXSAVES) 3705 Builder.defineMacro("__XSAVES__"); 3706 if (HasPKU) 3707 Builder.defineMacro("__PKU__"); 3708 if (HasCX16) 3709 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3710 3711 // Each case falls through to the previous one here. 3712 switch (SSELevel) { 3713 case AVX512F: 3714 Builder.defineMacro("__AVX512F__"); 3715 case AVX2: 3716 Builder.defineMacro("__AVX2__"); 3717 case AVX: 3718 Builder.defineMacro("__AVX__"); 3719 case SSE42: 3720 Builder.defineMacro("__SSE4_2__"); 3721 case SSE41: 3722 Builder.defineMacro("__SSE4_1__"); 3723 case SSSE3: 3724 Builder.defineMacro("__SSSE3__"); 3725 case SSE3: 3726 Builder.defineMacro("__SSE3__"); 3727 case SSE2: 3728 Builder.defineMacro("__SSE2__"); 3729 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3730 case SSE1: 3731 Builder.defineMacro("__SSE__"); 3732 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3733 case NoSSE: 3734 break; 3735 } 3736 3737 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3738 switch (SSELevel) { 3739 case AVX512F: 3740 case AVX2: 3741 case AVX: 3742 case SSE42: 3743 case SSE41: 3744 case SSSE3: 3745 case SSE3: 3746 case SSE2: 3747 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3748 break; 3749 case SSE1: 3750 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3751 break; 3752 default: 3753 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3754 } 3755 } 3756 3757 // Each case falls through to the previous one here. 3758 switch (MMX3DNowLevel) { 3759 case AMD3DNowAthlon: 3760 Builder.defineMacro("__3dNOW_A__"); 3761 case AMD3DNow: 3762 Builder.defineMacro("__3dNOW__"); 3763 case MMX: 3764 Builder.defineMacro("__MMX__"); 3765 case NoMMX3DNow: 3766 break; 3767 } 3768 3769 if (CPU >= CK_i486) { 3770 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3771 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3772 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3773 } 3774 if (CPU >= CK_i586) 3775 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3776 } 3777 3778 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3779 return llvm::StringSwitch<bool>(Feature) 3780 .Case("aes", HasAES) 3781 .Case("avx", SSELevel >= AVX) 3782 .Case("avx2", SSELevel >= AVX2) 3783 .Case("avx512f", SSELevel >= AVX512F) 3784 .Case("avx512cd", HasAVX512CD) 3785 .Case("avx512er", HasAVX512ER) 3786 .Case("avx512pf", HasAVX512PF) 3787 .Case("avx512dq", HasAVX512DQ) 3788 .Case("avx512bw", HasAVX512BW) 3789 .Case("avx512vl", HasAVX512VL) 3790 .Case("avx512vbmi", HasAVX512VBMI) 3791 .Case("avx512ifma", HasAVX512IFMA) 3792 .Case("bmi", HasBMI) 3793 .Case("bmi2", HasBMI2) 3794 .Case("clflushopt", HasCLFLUSHOPT) 3795 .Case("clwb", HasCLWB) 3796 .Case("cx16", HasCX16) 3797 .Case("f16c", HasF16C) 3798 .Case("fma", HasFMA) 3799 .Case("fma4", XOPLevel >= FMA4) 3800 .Case("fsgsbase", HasFSGSBASE) 3801 .Case("fxsr", HasFXSR) 3802 .Case("lzcnt", HasLZCNT) 3803 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3804 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3805 .Case("mmx", MMX3DNowLevel >= MMX) 3806 .Case("movbe", HasMOVBE) 3807 .Case("mpx", HasMPX) 3808 .Case("pclmul", HasPCLMUL) 3809 .Case("pcommit", HasPCOMMIT) 3810 .Case("pku", HasPKU) 3811 .Case("popcnt", HasPOPCNT) 3812 .Case("prefetchwt1", HasPREFETCHWT1) 3813 .Case("prfchw", HasPRFCHW) 3814 .Case("rdrnd", HasRDRND) 3815 .Case("rdseed", HasRDSEED) 3816 .Case("rtm", HasRTM) 3817 .Case("sgx", HasSGX) 3818 .Case("sha", HasSHA) 3819 .Case("sse", SSELevel >= SSE1) 3820 .Case("sse2", SSELevel >= SSE2) 3821 .Case("sse3", SSELevel >= SSE3) 3822 .Case("ssse3", SSELevel >= SSSE3) 3823 .Case("sse4.1", SSELevel >= SSE41) 3824 .Case("sse4.2", SSELevel >= SSE42) 3825 .Case("sse4a", XOPLevel >= SSE4A) 3826 .Case("tbm", HasTBM) 3827 .Case("umip", HasUMIP) 3828 .Case("x86", true) 3829 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3830 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3831 .Case("xop", XOPLevel >= XOP) 3832 .Case("xsave", HasXSAVE) 3833 .Case("xsavec", HasXSAVEC) 3834 .Case("xsaves", HasXSAVES) 3835 .Case("xsaveopt", HasXSAVEOPT) 3836 .Default(false); 3837 } 3838 3839 // We can't use a generic validation scheme for the features accepted here 3840 // versus subtarget features accepted in the target attribute because the 3841 // bitfield structure that's initialized in the runtime only supports the 3842 // below currently rather than the full range of subtarget features. (See 3843 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3844 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3845 return llvm::StringSwitch<bool>(FeatureStr) 3846 .Case("cmov", true) 3847 .Case("mmx", true) 3848 .Case("popcnt", true) 3849 .Case("sse", true) 3850 .Case("sse2", true) 3851 .Case("sse3", true) 3852 .Case("ssse3", true) 3853 .Case("sse4.1", true) 3854 .Case("sse4.2", true) 3855 .Case("avx", true) 3856 .Case("avx2", true) 3857 .Case("sse4a", true) 3858 .Case("fma4", true) 3859 .Case("xop", true) 3860 .Case("fma", true) 3861 .Case("avx512f", true) 3862 .Case("bmi", true) 3863 .Case("bmi2", true) 3864 .Case("aes", true) 3865 .Case("pclmul", true) 3866 .Case("avx512vl", true) 3867 .Case("avx512bw", true) 3868 .Case("avx512dq", true) 3869 .Case("avx512cd", true) 3870 .Case("avx512er", true) 3871 .Case("avx512pf", true) 3872 .Case("avx512vbmi", true) 3873 .Case("avx512ifma", true) 3874 .Default(false); 3875 } 3876 3877 bool 3878 X86TargetInfo::validateAsmConstraint(const char *&Name, 3879 TargetInfo::ConstraintInfo &Info) const { 3880 switch (*Name) { 3881 default: return false; 3882 // Constant constraints. 3883 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3884 // instructions. 3885 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3886 // x86_64 instructions. 3887 case 's': 3888 Info.setRequiresImmediate(); 3889 return true; 3890 case 'I': 3891 Info.setRequiresImmediate(0, 31); 3892 return true; 3893 case 'J': 3894 Info.setRequiresImmediate(0, 63); 3895 return true; 3896 case 'K': 3897 Info.setRequiresImmediate(-128, 127); 3898 return true; 3899 case 'L': 3900 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3901 return true; 3902 case 'M': 3903 Info.setRequiresImmediate(0, 3); 3904 return true; 3905 case 'N': 3906 Info.setRequiresImmediate(0, 255); 3907 return true; 3908 case 'O': 3909 Info.setRequiresImmediate(0, 127); 3910 return true; 3911 // Register constraints. 3912 case 'Y': // 'Y' is the first character for several 2-character constraints. 3913 // Shift the pointer to the second character of the constraint. 3914 Name++; 3915 switch (*Name) { 3916 default: 3917 return false; 3918 case '0': // First SSE register. 3919 case 't': // Any SSE register, when SSE2 is enabled. 3920 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3921 case 'm': // Any MMX register, when inter-unit moves enabled. 3922 Info.setAllowsRegister(); 3923 return true; 3924 } 3925 case 'f': // Any x87 floating point stack register. 3926 // Constraint 'f' cannot be used for output operands. 3927 if (Info.ConstraintStr[0] == '=') 3928 return false; 3929 Info.setAllowsRegister(); 3930 return true; 3931 case 'a': // eax. 3932 case 'b': // ebx. 3933 case 'c': // ecx. 3934 case 'd': // edx. 3935 case 'S': // esi. 3936 case 'D': // edi. 3937 case 'A': // edx:eax. 3938 case 't': // Top of floating point stack. 3939 case 'u': // Second from top of floating point stack. 3940 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3941 case 'y': // Any MMX register. 3942 case 'x': // Any SSE register. 3943 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3944 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3945 case 'l': // "Index" registers: any general register that can be used as an 3946 // index in a base+index memory access. 3947 Info.setAllowsRegister(); 3948 return true; 3949 // Floating point constant constraints. 3950 case 'C': // SSE floating point constant. 3951 case 'G': // x87 floating point constant. 3952 return true; 3953 } 3954 } 3955 3956 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3957 unsigned Size) const { 3958 // Strip off constraint modifiers. 3959 while (Constraint[0] == '=' || 3960 Constraint[0] == '+' || 3961 Constraint[0] == '&') 3962 Constraint = Constraint.substr(1); 3963 3964 return validateOperandSize(Constraint, Size); 3965 } 3966 3967 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3968 unsigned Size) const { 3969 return validateOperandSize(Constraint, Size); 3970 } 3971 3972 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3973 unsigned Size) const { 3974 switch (Constraint[0]) { 3975 default: break; 3976 case 'y': 3977 return Size <= 64; 3978 case 'f': 3979 case 't': 3980 case 'u': 3981 return Size <= 128; 3982 case 'x': 3983 if (SSELevel >= AVX512F) 3984 // 512-bit zmm registers can be used if target supports AVX512F. 3985 return Size <= 512U; 3986 else if (SSELevel >= AVX) 3987 // 256-bit ymm registers can be used if target supports AVX. 3988 return Size <= 256U; 3989 return Size <= 128U; 3990 case 'Y': 3991 // 'Y' is the first character for several 2-character constraints. 3992 switch (Constraint[1]) { 3993 default: break; 3994 case 'm': 3995 // 'Ym' is synonymous with 'y'. 3996 return Size <= 64; 3997 case 'i': 3998 case 't': 3999 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4000 if (SSELevel >= AVX512F) 4001 return Size <= 512U; 4002 else if (SSELevel >= AVX) 4003 return Size <= 256U; 4004 return SSELevel >= SSE2 && Size <= 128U; 4005 } 4006 4007 } 4008 4009 return true; 4010 } 4011 4012 std::string 4013 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4014 switch (*Constraint) { 4015 case 'a': return std::string("{ax}"); 4016 case 'b': return std::string("{bx}"); 4017 case 'c': return std::string("{cx}"); 4018 case 'd': return std::string("{dx}"); 4019 case 'S': return std::string("{si}"); 4020 case 'D': return std::string("{di}"); 4021 case 'p': // address 4022 return std::string("im"); 4023 case 't': // top of floating point stack. 4024 return std::string("{st}"); 4025 case 'u': // second from top of floating point stack. 4026 return std::string("{st(1)}"); // second from top of floating point stack. 4027 default: 4028 return std::string(1, *Constraint); 4029 } 4030 } 4031 4032 // X86-32 generic target 4033 class X86_32TargetInfo : public X86TargetInfo { 4034 public: 4035 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4036 : X86TargetInfo(Triple, Opts) { 4037 DoubleAlign = LongLongAlign = 32; 4038 LongDoubleWidth = 96; 4039 LongDoubleAlign = 32; 4040 SuitableAlign = 128; 4041 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4042 SizeType = UnsignedInt; 4043 PtrDiffType = SignedInt; 4044 IntPtrType = SignedInt; 4045 RegParmMax = 3; 4046 4047 // Use fpret for all types. 4048 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4049 (1 << TargetInfo::Double) | 4050 (1 << TargetInfo::LongDouble)); 4051 4052 // x86-32 has atomics up to 8 bytes 4053 // FIXME: Check that we actually have cmpxchg8b before setting 4054 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4055 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4056 } 4057 BuiltinVaListKind getBuiltinVaListKind() const override { 4058 return TargetInfo::CharPtrBuiltinVaList; 4059 } 4060 4061 int getEHDataRegisterNumber(unsigned RegNo) const override { 4062 if (RegNo == 0) return 0; 4063 if (RegNo == 1) return 2; 4064 return -1; 4065 } 4066 bool validateOperandSize(StringRef Constraint, 4067 unsigned Size) const override { 4068 switch (Constraint[0]) { 4069 default: break; 4070 case 'R': 4071 case 'q': 4072 case 'Q': 4073 case 'a': 4074 case 'b': 4075 case 'c': 4076 case 'd': 4077 case 'S': 4078 case 'D': 4079 return Size <= 32; 4080 case 'A': 4081 return Size <= 64; 4082 } 4083 4084 return X86TargetInfo::validateOperandSize(Constraint, Size); 4085 } 4086 }; 4087 4088 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4089 public: 4090 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4091 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4092 4093 unsigned getFloatEvalMethod() const override { 4094 unsigned Major, Minor, Micro; 4095 getTriple().getOSVersion(Major, Minor, Micro); 4096 // New NetBSD uses the default rounding mode. 4097 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4098 return X86_32TargetInfo::getFloatEvalMethod(); 4099 // NetBSD before 6.99.26 defaults to "double" rounding. 4100 return 1; 4101 } 4102 }; 4103 4104 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4105 public: 4106 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4107 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4108 SizeType = UnsignedLong; 4109 IntPtrType = SignedLong; 4110 PtrDiffType = SignedLong; 4111 } 4112 }; 4113 4114 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4115 public: 4116 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4117 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4118 SizeType = UnsignedLong; 4119 IntPtrType = SignedLong; 4120 PtrDiffType = SignedLong; 4121 } 4122 }; 4123 4124 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4125 public: 4126 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4127 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4128 LongDoubleWidth = 128; 4129 LongDoubleAlign = 128; 4130 SuitableAlign = 128; 4131 MaxVectorAlign = 256; 4132 // The watchOS simulator uses the builtin bool type for Objective-C. 4133 llvm::Triple T = llvm::Triple(Triple); 4134 if (T.isWatchOS()) 4135 UseSignedCharForObjCBool = false; 4136 SizeType = UnsignedLong; 4137 IntPtrType = SignedLong; 4138 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4139 HasAlignMac68kSupport = true; 4140 } 4141 4142 bool handleTargetFeatures(std::vector<std::string> &Features, 4143 DiagnosticsEngine &Diags) override { 4144 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4145 Diags)) 4146 return false; 4147 // We now know the features we have: we can decide how to align vectors. 4148 MaxVectorAlign = 4149 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4150 return true; 4151 } 4152 }; 4153 4154 // x86-32 Windows target 4155 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4156 public: 4157 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4158 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4159 WCharType = UnsignedShort; 4160 DoubleAlign = LongLongAlign = 64; 4161 bool IsWinCOFF = 4162 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4163 resetDataLayout(IsWinCOFF 4164 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4165 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4166 } 4167 void getTargetDefines(const LangOptions &Opts, 4168 MacroBuilder &Builder) const override { 4169 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4170 } 4171 }; 4172 4173 // x86-32 Windows Visual Studio target 4174 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4175 public: 4176 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4177 const TargetOptions &Opts) 4178 : WindowsX86_32TargetInfo(Triple, Opts) { 4179 LongDoubleWidth = LongDoubleAlign = 64; 4180 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4181 } 4182 void getTargetDefines(const LangOptions &Opts, 4183 MacroBuilder &Builder) const override { 4184 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4185 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4186 // The value of the following reflects processor type. 4187 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4188 // We lost the original triple, so we use the default. 4189 Builder.defineMacro("_M_IX86", "600"); 4190 } 4191 }; 4192 4193 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4194 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4195 // supports __declspec natively under -fms-extensions, but we define a no-op 4196 // __declspec macro anyway for pre-processor compatibility. 4197 if (Opts.MicrosoftExt) 4198 Builder.defineMacro("__declspec", "__declspec"); 4199 else 4200 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4201 4202 if (!Opts.MicrosoftExt) { 4203 // Provide macros for all the calling convention keywords. Provide both 4204 // single and double underscore prefixed variants. These are available on 4205 // x64 as well as x86, even though they have no effect. 4206 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4207 for (const char *CC : CCs) { 4208 std::string GCCSpelling = "__attribute__((__"; 4209 GCCSpelling += CC; 4210 GCCSpelling += "__))"; 4211 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4212 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4213 } 4214 } 4215 } 4216 4217 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4218 Builder.defineMacro("__MSVCRT__"); 4219 Builder.defineMacro("__MINGW32__"); 4220 addCygMingDefines(Opts, Builder); 4221 } 4222 4223 // x86-32 MinGW target 4224 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4225 public: 4226 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4227 : WindowsX86_32TargetInfo(Triple, Opts) {} 4228 void getTargetDefines(const LangOptions &Opts, 4229 MacroBuilder &Builder) const override { 4230 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4231 DefineStd(Builder, "WIN32", Opts); 4232 DefineStd(Builder, "WINNT", Opts); 4233 Builder.defineMacro("_X86_"); 4234 addMinGWDefines(Opts, Builder); 4235 } 4236 }; 4237 4238 // x86-32 Cygwin target 4239 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4240 public: 4241 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4242 : X86_32TargetInfo(Triple, Opts) { 4243 WCharType = UnsignedShort; 4244 DoubleAlign = LongLongAlign = 64; 4245 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4246 } 4247 void getTargetDefines(const LangOptions &Opts, 4248 MacroBuilder &Builder) const override { 4249 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4250 Builder.defineMacro("_X86_"); 4251 Builder.defineMacro("__CYGWIN__"); 4252 Builder.defineMacro("__CYGWIN32__"); 4253 addCygMingDefines(Opts, Builder); 4254 DefineStd(Builder, "unix", Opts); 4255 if (Opts.CPlusPlus) 4256 Builder.defineMacro("_GNU_SOURCE"); 4257 } 4258 }; 4259 4260 // x86-32 Haiku target 4261 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4262 public: 4263 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4264 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4265 } 4266 void getTargetDefines(const LangOptions &Opts, 4267 MacroBuilder &Builder) const override { 4268 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4269 Builder.defineMacro("__INTEL__"); 4270 } 4271 }; 4272 4273 // X86-32 MCU target 4274 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4275 public: 4276 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4277 : X86_32TargetInfo(Triple, Opts) { 4278 LongDoubleWidth = 64; 4279 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4280 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4281 WIntType = UnsignedInt; 4282 } 4283 4284 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4285 // On MCU we support only C calling convention. 4286 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4287 } 4288 4289 void getTargetDefines(const LangOptions &Opts, 4290 MacroBuilder &Builder) const override { 4291 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4292 Builder.defineMacro("__iamcu"); 4293 Builder.defineMacro("__iamcu__"); 4294 } 4295 4296 bool allowsLargerPreferedTypeAlignment() const override { 4297 return false; 4298 } 4299 }; 4300 4301 // RTEMS Target 4302 template<typename Target> 4303 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4304 protected: 4305 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4306 MacroBuilder &Builder) const override { 4307 // RTEMS defines; list based off of gcc output 4308 4309 Builder.defineMacro("__rtems__"); 4310 Builder.defineMacro("__ELF__"); 4311 } 4312 4313 public: 4314 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4315 : OSTargetInfo<Target>(Triple, Opts) { 4316 switch (Triple.getArch()) { 4317 default: 4318 case llvm::Triple::x86: 4319 // this->MCountName = ".mcount"; 4320 break; 4321 case llvm::Triple::mips: 4322 case llvm::Triple::mipsel: 4323 case llvm::Triple::ppc: 4324 case llvm::Triple::ppc64: 4325 case llvm::Triple::ppc64le: 4326 // this->MCountName = "_mcount"; 4327 break; 4328 case llvm::Triple::arm: 4329 // this->MCountName = "__mcount"; 4330 break; 4331 } 4332 } 4333 }; 4334 4335 // x86-32 RTEMS target 4336 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4337 public: 4338 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4339 : X86_32TargetInfo(Triple, Opts) { 4340 SizeType = UnsignedLong; 4341 IntPtrType = SignedLong; 4342 PtrDiffType = SignedLong; 4343 } 4344 void getTargetDefines(const LangOptions &Opts, 4345 MacroBuilder &Builder) const override { 4346 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4347 Builder.defineMacro("__INTEL__"); 4348 Builder.defineMacro("__rtems__"); 4349 } 4350 }; 4351 4352 // x86-64 generic target 4353 class X86_64TargetInfo : public X86TargetInfo { 4354 public: 4355 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4356 : X86TargetInfo(Triple, Opts) { 4357 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4358 bool IsWinCOFF = 4359 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4360 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4361 LongDoubleWidth = 128; 4362 LongDoubleAlign = 128; 4363 LargeArrayMinWidth = 128; 4364 LargeArrayAlign = 128; 4365 SuitableAlign = 128; 4366 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4367 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4368 IntPtrType = IsX32 ? SignedInt : SignedLong; 4369 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4370 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4371 RegParmMax = 6; 4372 4373 // Pointers are 32-bit in x32. 4374 resetDataLayout(IsX32 4375 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4376 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4377 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4378 4379 // Use fpret only for long double. 4380 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4381 4382 // Use fp2ret for _Complex long double. 4383 ComplexLongDoubleUsesFP2Ret = true; 4384 4385 // Make __builtin_ms_va_list available. 4386 HasBuiltinMSVaList = true; 4387 4388 // x86-64 has atomics up to 16 bytes. 4389 MaxAtomicPromoteWidth = 128; 4390 MaxAtomicInlineWidth = 128; 4391 } 4392 BuiltinVaListKind getBuiltinVaListKind() const override { 4393 return TargetInfo::X86_64ABIBuiltinVaList; 4394 } 4395 4396 int getEHDataRegisterNumber(unsigned RegNo) const override { 4397 if (RegNo == 0) return 0; 4398 if (RegNo == 1) return 1; 4399 return -1; 4400 } 4401 4402 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4403 switch (CC) { 4404 case CC_C: 4405 case CC_Swift: 4406 case CC_X86VectorCall: 4407 case CC_IntelOclBicc: 4408 case CC_X86_64Win64: 4409 case CC_PreserveMost: 4410 case CC_PreserveAll: 4411 return CCCR_OK; 4412 default: 4413 return CCCR_Warning; 4414 } 4415 } 4416 4417 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4418 return CC_C; 4419 } 4420 4421 // for x32 we need it here explicitly 4422 bool hasInt128Type() const override { return true; } 4423 unsigned getUnwindWordWidth() const override { return 64; } 4424 unsigned getRegisterWidth() const override { return 64; } 4425 4426 bool validateGlobalRegisterVariable(StringRef RegName, 4427 unsigned RegSize, 4428 bool &HasSizeMismatch) const override { 4429 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4430 // handle. 4431 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4432 // Check that the register size is 64-bit. 4433 HasSizeMismatch = RegSize != 64; 4434 return true; 4435 } 4436 4437 // Check if the register is a 32-bit register the backend can handle. 4438 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4439 HasSizeMismatch); 4440 } 4441 }; 4442 4443 // x86-64 Windows target 4444 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4445 public: 4446 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4447 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4448 WCharType = UnsignedShort; 4449 LongWidth = LongAlign = 32; 4450 DoubleAlign = LongLongAlign = 64; 4451 IntMaxType = SignedLongLong; 4452 Int64Type = SignedLongLong; 4453 SizeType = UnsignedLongLong; 4454 PtrDiffType = SignedLongLong; 4455 IntPtrType = SignedLongLong; 4456 } 4457 4458 void getTargetDefines(const LangOptions &Opts, 4459 MacroBuilder &Builder) const override { 4460 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4461 Builder.defineMacro("_WIN64"); 4462 } 4463 4464 BuiltinVaListKind getBuiltinVaListKind() const override { 4465 return TargetInfo::CharPtrBuiltinVaList; 4466 } 4467 4468 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4469 switch (CC) { 4470 case CC_X86StdCall: 4471 case CC_X86ThisCall: 4472 case CC_X86FastCall: 4473 return CCCR_Ignore; 4474 case CC_C: 4475 case CC_X86VectorCall: 4476 case CC_IntelOclBicc: 4477 case CC_X86_64SysV: 4478 return CCCR_OK; 4479 default: 4480 return CCCR_Warning; 4481 } 4482 } 4483 }; 4484 4485 // x86-64 Windows Visual Studio target 4486 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4487 public: 4488 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4489 const TargetOptions &Opts) 4490 : WindowsX86_64TargetInfo(Triple, Opts) { 4491 LongDoubleWidth = LongDoubleAlign = 64; 4492 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4493 } 4494 void getTargetDefines(const LangOptions &Opts, 4495 MacroBuilder &Builder) const override { 4496 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4497 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4498 Builder.defineMacro("_M_X64", "100"); 4499 Builder.defineMacro("_M_AMD64", "100"); 4500 } 4501 }; 4502 4503 // x86-64 MinGW target 4504 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4505 public: 4506 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4507 : WindowsX86_64TargetInfo(Triple, Opts) { 4508 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4509 // with x86 FP ops. Weird. 4510 LongDoubleWidth = LongDoubleAlign = 128; 4511 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4512 } 4513 4514 void getTargetDefines(const LangOptions &Opts, 4515 MacroBuilder &Builder) const override { 4516 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4517 DefineStd(Builder, "WIN64", Opts); 4518 Builder.defineMacro("__MINGW64__"); 4519 addMinGWDefines(Opts, Builder); 4520 4521 // GCC defines this macro when it is using __gxx_personality_seh0. 4522 if (!Opts.SjLjExceptions) 4523 Builder.defineMacro("__SEH__"); 4524 } 4525 }; 4526 4527 // x86-64 Cygwin target 4528 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4529 public: 4530 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4531 : X86_64TargetInfo(Triple, Opts) { 4532 TLSSupported = false; 4533 WCharType = UnsignedShort; 4534 } 4535 void getTargetDefines(const LangOptions &Opts, 4536 MacroBuilder &Builder) const override { 4537 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4538 Builder.defineMacro("__x86_64__"); 4539 Builder.defineMacro("__CYGWIN__"); 4540 Builder.defineMacro("__CYGWIN64__"); 4541 addCygMingDefines(Opts, Builder); 4542 DefineStd(Builder, "unix", Opts); 4543 if (Opts.CPlusPlus) 4544 Builder.defineMacro("_GNU_SOURCE"); 4545 4546 // GCC defines this macro when it is using __gxx_personality_seh0. 4547 if (!Opts.SjLjExceptions) 4548 Builder.defineMacro("__SEH__"); 4549 } 4550 }; 4551 4552 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4553 public: 4554 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4555 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4556 Int64Type = SignedLongLong; 4557 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4558 llvm::Triple T = llvm::Triple(Triple); 4559 if (T.isiOS()) 4560 UseSignedCharForObjCBool = false; 4561 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4562 } 4563 4564 bool handleTargetFeatures(std::vector<std::string> &Features, 4565 DiagnosticsEngine &Diags) override { 4566 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4567 Diags)) 4568 return false; 4569 // We now know the features we have: we can decide how to align vectors. 4570 MaxVectorAlign = 4571 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4572 return true; 4573 } 4574 }; 4575 4576 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4577 public: 4578 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4579 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4580 IntMaxType = SignedLongLong; 4581 Int64Type = SignedLongLong; 4582 } 4583 }; 4584 4585 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4586 public: 4587 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4588 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4589 IntMaxType = SignedLongLong; 4590 Int64Type = SignedLongLong; 4591 } 4592 }; 4593 4594 class ARMTargetInfo : public TargetInfo { 4595 // Possible FPU choices. 4596 enum FPUMode { 4597 VFP2FPU = (1 << 0), 4598 VFP3FPU = (1 << 1), 4599 VFP4FPU = (1 << 2), 4600 NeonFPU = (1 << 3), 4601 FPARMV8 = (1 << 4) 4602 }; 4603 4604 // Possible HWDiv features. 4605 enum HWDivMode { 4606 HWDivThumb = (1 << 0), 4607 HWDivARM = (1 << 1) 4608 }; 4609 4610 static bool FPUModeIsVFP(FPUMode Mode) { 4611 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4612 } 4613 4614 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4615 static const char * const GCCRegNames[]; 4616 4617 std::string ABI, CPU; 4618 4619 StringRef CPUProfile; 4620 StringRef CPUAttr; 4621 4622 enum { 4623 FP_Default, 4624 FP_VFP, 4625 FP_Neon 4626 } FPMath; 4627 4628 unsigned ArchISA; 4629 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4630 unsigned ArchProfile; 4631 unsigned ArchVersion; 4632 4633 unsigned FPU : 5; 4634 4635 unsigned IsAAPCS : 1; 4636 unsigned HWDiv : 2; 4637 4638 // Initialized via features. 4639 unsigned SoftFloat : 1; 4640 unsigned SoftFloatABI : 1; 4641 4642 unsigned CRC : 1; 4643 unsigned Crypto : 1; 4644 unsigned DSP : 1; 4645 unsigned Unaligned : 1; 4646 4647 enum { 4648 LDREX_B = (1 << 0), /// byte (8-bit) 4649 LDREX_H = (1 << 1), /// half (16-bit) 4650 LDREX_W = (1 << 2), /// word (32-bit) 4651 LDREX_D = (1 << 3), /// double (64-bit) 4652 }; 4653 4654 uint32_t LDREX; 4655 4656 // ACLE 6.5.1 Hardware floating point 4657 enum { 4658 HW_FP_HP = (1 << 1), /// half (16-bit) 4659 HW_FP_SP = (1 << 2), /// single (32-bit) 4660 HW_FP_DP = (1 << 3), /// double (64-bit) 4661 }; 4662 uint32_t HW_FP; 4663 4664 static const Builtin::Info BuiltinInfo[]; 4665 4666 void setABIAAPCS() { 4667 IsAAPCS = true; 4668 4669 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4670 const llvm::Triple &T = getTriple(); 4671 4672 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4673 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4674 T.getOS() == llvm::Triple::Bitrig) 4675 SizeType = UnsignedLong; 4676 else 4677 SizeType = UnsignedInt; 4678 4679 switch (T.getOS()) { 4680 case llvm::Triple::NetBSD: 4681 WCharType = SignedInt; 4682 break; 4683 case llvm::Triple::Win32: 4684 WCharType = UnsignedShort; 4685 break; 4686 case llvm::Triple::Linux: 4687 default: 4688 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4689 WCharType = UnsignedInt; 4690 break; 4691 } 4692 4693 UseBitFieldTypeAlignment = true; 4694 4695 ZeroLengthBitfieldBoundary = 0; 4696 4697 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4698 // so set preferred for small types to 32. 4699 if (T.isOSBinFormatMachO()) { 4700 resetDataLayout(BigEndian 4701 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4702 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4703 } else if (T.isOSWindows()) { 4704 assert(!BigEndian && "Windows on ARM does not support big endian"); 4705 resetDataLayout("e" 4706 "-m:w" 4707 "-p:32:32" 4708 "-i64:64" 4709 "-v128:64:128" 4710 "-a:0:32" 4711 "-n32" 4712 "-S64"); 4713 } else if (T.isOSNaCl()) { 4714 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4715 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4716 } else { 4717 resetDataLayout(BigEndian 4718 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4719 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4720 } 4721 4722 // FIXME: Enumerated types are variable width in straight AAPCS. 4723 } 4724 4725 void setABIAPCS(bool IsAAPCS16) { 4726 const llvm::Triple &T = getTriple(); 4727 4728 IsAAPCS = false; 4729 4730 if (IsAAPCS16) 4731 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4732 else 4733 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4734 4735 // size_t is unsigned int on FreeBSD. 4736 if (T.getOS() == llvm::Triple::FreeBSD) 4737 SizeType = UnsignedInt; 4738 else 4739 SizeType = UnsignedLong; 4740 4741 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4742 WCharType = SignedInt; 4743 4744 // Do not respect the alignment of bit-field types when laying out 4745 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4746 UseBitFieldTypeAlignment = false; 4747 4748 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4749 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4750 /// gcc. 4751 ZeroLengthBitfieldBoundary = 32; 4752 4753 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4754 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4755 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4756 } else if (T.isOSBinFormatMachO()) 4757 resetDataLayout( 4758 BigEndian 4759 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4760 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4761 else 4762 resetDataLayout( 4763 BigEndian 4764 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4765 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4766 4767 // FIXME: Override "preferred align" for double and long long. 4768 } 4769 4770 void setArchInfo() { 4771 StringRef ArchName = getTriple().getArchName(); 4772 4773 ArchISA = llvm::ARM::parseArchISA(ArchName); 4774 CPU = llvm::ARM::getDefaultCPU(ArchName); 4775 unsigned AK = llvm::ARM::parseArch(ArchName); 4776 if (AK != llvm::ARM::AK_INVALID) 4777 ArchKind = AK; 4778 setArchInfo(ArchKind); 4779 } 4780 4781 void setArchInfo(unsigned Kind) { 4782 StringRef SubArch; 4783 4784 // cache TargetParser info 4785 ArchKind = Kind; 4786 SubArch = llvm::ARM::getSubArch(ArchKind); 4787 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4788 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4789 4790 // cache CPU related strings 4791 CPUAttr = getCPUAttr(); 4792 CPUProfile = getCPUProfile(); 4793 } 4794 4795 void setAtomic() { 4796 // when triple does not specify a sub arch, 4797 // then we are not using inline atomics 4798 bool ShouldUseInlineAtomic = 4799 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4800 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4801 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4802 if (ArchProfile == llvm::ARM::PK_M) { 4803 MaxAtomicPromoteWidth = 32; 4804 if (ShouldUseInlineAtomic) 4805 MaxAtomicInlineWidth = 32; 4806 } 4807 else { 4808 MaxAtomicPromoteWidth = 64; 4809 if (ShouldUseInlineAtomic) 4810 MaxAtomicInlineWidth = 64; 4811 } 4812 } 4813 4814 bool isThumb() const { 4815 return (ArchISA == llvm::ARM::IK_THUMB); 4816 } 4817 4818 bool supportsThumb() const { 4819 return CPUAttr.count('T') || ArchVersion >= 6; 4820 } 4821 4822 bool supportsThumb2() const { 4823 return CPUAttr.equals("6T2") || 4824 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4825 } 4826 4827 StringRef getCPUAttr() const { 4828 // For most sub-arches, the build attribute CPU name is enough. 4829 // For Cortex variants, it's slightly different. 4830 switch(ArchKind) { 4831 default: 4832 return llvm::ARM::getCPUAttr(ArchKind); 4833 case llvm::ARM::AK_ARMV6M: 4834 return "6M"; 4835 case llvm::ARM::AK_ARMV7S: 4836 return "7S"; 4837 case llvm::ARM::AK_ARMV7A: 4838 return "7A"; 4839 case llvm::ARM::AK_ARMV7R: 4840 return "7R"; 4841 case llvm::ARM::AK_ARMV7M: 4842 return "7M"; 4843 case llvm::ARM::AK_ARMV7EM: 4844 return "7EM"; 4845 case llvm::ARM::AK_ARMV8A: 4846 return "8A"; 4847 case llvm::ARM::AK_ARMV8_1A: 4848 return "8_1A"; 4849 case llvm::ARM::AK_ARMV8_2A: 4850 return "8_2A"; 4851 case llvm::ARM::AK_ARMV8MBaseline: 4852 return "8M_BASE"; 4853 case llvm::ARM::AK_ARMV8MMainline: 4854 return "8M_MAIN"; 4855 } 4856 } 4857 4858 StringRef getCPUProfile() const { 4859 switch(ArchProfile) { 4860 case llvm::ARM::PK_A: 4861 return "A"; 4862 case llvm::ARM::PK_R: 4863 return "R"; 4864 case llvm::ARM::PK_M: 4865 return "M"; 4866 default: 4867 return ""; 4868 } 4869 } 4870 4871 public: 4872 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 4873 bool IsBigEndian) 4874 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4875 HW_FP(0) { 4876 BigEndian = IsBigEndian; 4877 4878 switch (getTriple().getOS()) { 4879 case llvm::Triple::NetBSD: 4880 PtrDiffType = SignedLong; 4881 break; 4882 default: 4883 PtrDiffType = SignedInt; 4884 break; 4885 } 4886 4887 // Cache arch related info. 4888 setArchInfo(); 4889 4890 // {} in inline assembly are neon specifiers, not assembly variant 4891 // specifiers. 4892 NoAsmVariants = true; 4893 4894 // FIXME: This duplicates code from the driver that sets the -target-abi 4895 // option - this code is used if -target-abi isn't passed and should 4896 // be unified in some way. 4897 if (Triple.isOSBinFormatMachO()) { 4898 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4899 // the frontend matches that. 4900 if (Triple.getEnvironment() == llvm::Triple::EABI || 4901 Triple.getOS() == llvm::Triple::UnknownOS || 4902 StringRef(CPU).startswith("cortex-m")) { 4903 setABI("aapcs"); 4904 } else if (Triple.isWatchABI()) { 4905 setABI("aapcs16"); 4906 } else { 4907 setABI("apcs-gnu"); 4908 } 4909 } else if (Triple.isOSWindows()) { 4910 // FIXME: this is invalid for WindowsCE 4911 setABI("aapcs"); 4912 } else { 4913 // Select the default based on the platform. 4914 switch (Triple.getEnvironment()) { 4915 case llvm::Triple::Android: 4916 case llvm::Triple::GNUEABI: 4917 case llvm::Triple::GNUEABIHF: 4918 case llvm::Triple::MuslEABI: 4919 case llvm::Triple::MuslEABIHF: 4920 setABI("aapcs-linux"); 4921 break; 4922 case llvm::Triple::EABIHF: 4923 case llvm::Triple::EABI: 4924 setABI("aapcs"); 4925 break; 4926 case llvm::Triple::GNU: 4927 setABI("apcs-gnu"); 4928 break; 4929 default: 4930 if (Triple.getOS() == llvm::Triple::NetBSD) 4931 setABI("apcs-gnu"); 4932 else 4933 setABI("aapcs"); 4934 break; 4935 } 4936 } 4937 4938 // ARM targets default to using the ARM C++ ABI. 4939 TheCXXABI.set(TargetCXXABI::GenericARM); 4940 4941 // ARM has atomics up to 8 bytes 4942 setAtomic(); 4943 4944 // Do force alignment of members that follow zero length bitfields. If 4945 // the alignment of the zero-length bitfield is greater than the member 4946 // that follows it, `bar', `bar' will be aligned as the type of the 4947 // zero length bitfield. 4948 UseZeroLengthBitfieldAlignment = true; 4949 4950 if (Triple.getOS() == llvm::Triple::Linux || 4951 Triple.getOS() == llvm::Triple::UnknownOS) 4952 this->MCountName = 4953 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 4954 } 4955 4956 StringRef getABI() const override { return ABI; } 4957 4958 bool setABI(const std::string &Name) override { 4959 ABI = Name; 4960 4961 // The defaults (above) are for AAPCS, check if we need to change them. 4962 // 4963 // FIXME: We need support for -meabi... we could just mangle it into the 4964 // name. 4965 if (Name == "apcs-gnu" || Name == "aapcs16") { 4966 setABIAPCS(Name == "aapcs16"); 4967 return true; 4968 } 4969 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4970 setABIAAPCS(); 4971 return true; 4972 } 4973 return false; 4974 } 4975 4976 // FIXME: This should be based on Arch attributes, not CPU names. 4977 bool 4978 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4979 StringRef CPU, 4980 const std::vector<std::string> &FeaturesVec) const override { 4981 4982 std::vector<const char*> TargetFeatures; 4983 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4984 4985 // get default FPU features 4986 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4987 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4988 4989 // get default Extension features 4990 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4991 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4992 4993 for (const char *Feature : TargetFeatures) 4994 if (Feature[0] == '+') 4995 Features[Feature+1] = true; 4996 4997 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4998 } 4999 5000 bool handleTargetFeatures(std::vector<std::string> &Features, 5001 DiagnosticsEngine &Diags) override { 5002 FPU = 0; 5003 CRC = 0; 5004 Crypto = 0; 5005 DSP = 0; 5006 Unaligned = 1; 5007 SoftFloat = SoftFloatABI = false; 5008 HWDiv = 0; 5009 5010 // This does not diagnose illegal cases like having both 5011 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5012 uint32_t HW_FP_remove = 0; 5013 for (const auto &Feature : Features) { 5014 if (Feature == "+soft-float") { 5015 SoftFloat = true; 5016 } else if (Feature == "+soft-float-abi") { 5017 SoftFloatABI = true; 5018 } else if (Feature == "+vfp2") { 5019 FPU |= VFP2FPU; 5020 HW_FP |= HW_FP_SP | HW_FP_DP; 5021 } else if (Feature == "+vfp3") { 5022 FPU |= VFP3FPU; 5023 HW_FP |= HW_FP_SP | HW_FP_DP; 5024 } else if (Feature == "+vfp4") { 5025 FPU |= VFP4FPU; 5026 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5027 } else if (Feature == "+fp-armv8") { 5028 FPU |= FPARMV8; 5029 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5030 } else if (Feature == "+neon") { 5031 FPU |= NeonFPU; 5032 HW_FP |= HW_FP_SP | HW_FP_DP; 5033 } else if (Feature == "+hwdiv") { 5034 HWDiv |= HWDivThumb; 5035 } else if (Feature == "+hwdiv-arm") { 5036 HWDiv |= HWDivARM; 5037 } else if (Feature == "+crc") { 5038 CRC = 1; 5039 } else if (Feature == "+crypto") { 5040 Crypto = 1; 5041 } else if (Feature == "+dsp") { 5042 DSP = 1; 5043 } else if (Feature == "+fp-only-sp") { 5044 HW_FP_remove |= HW_FP_DP; 5045 } else if (Feature == "+strict-align") { 5046 Unaligned = 0; 5047 } else if (Feature == "+fp16") { 5048 HW_FP |= HW_FP_HP; 5049 } 5050 } 5051 HW_FP &= ~HW_FP_remove; 5052 5053 switch (ArchVersion) { 5054 case 6: 5055 if (ArchProfile == llvm::ARM::PK_M) 5056 LDREX = 0; 5057 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5058 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5059 else 5060 LDREX = LDREX_W; 5061 break; 5062 case 7: 5063 if (ArchProfile == llvm::ARM::PK_M) 5064 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5065 else 5066 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5067 break; 5068 case 8: 5069 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5070 } 5071 5072 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5073 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5074 return false; 5075 } 5076 5077 if (FPMath == FP_Neon) 5078 Features.push_back("+neonfp"); 5079 else if (FPMath == FP_VFP) 5080 Features.push_back("-neonfp"); 5081 5082 // Remove front-end specific options which the backend handles differently. 5083 auto Feature = 5084 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5085 if (Feature != Features.end()) 5086 Features.erase(Feature); 5087 5088 return true; 5089 } 5090 5091 bool hasFeature(StringRef Feature) const override { 5092 return llvm::StringSwitch<bool>(Feature) 5093 .Case("arm", true) 5094 .Case("aarch32", true) 5095 .Case("softfloat", SoftFloat) 5096 .Case("thumb", isThumb()) 5097 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5098 .Case("hwdiv", HWDiv & HWDivThumb) 5099 .Case("hwdiv-arm", HWDiv & HWDivARM) 5100 .Default(false); 5101 } 5102 5103 bool setCPU(const std::string &Name) override { 5104 if (Name != "generic") 5105 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5106 5107 if (ArchKind == llvm::ARM::AK_INVALID) 5108 return false; 5109 setAtomic(); 5110 CPU = Name; 5111 return true; 5112 } 5113 5114 bool setFPMath(StringRef Name) override; 5115 5116 void getTargetDefines(const LangOptions &Opts, 5117 MacroBuilder &Builder) const override { 5118 // Target identification. 5119 Builder.defineMacro("__arm"); 5120 Builder.defineMacro("__arm__"); 5121 // For bare-metal none-eabi. 5122 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5123 getTriple().getEnvironment() == llvm::Triple::EABI) 5124 Builder.defineMacro("__ELF__"); 5125 5126 // Target properties. 5127 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5128 5129 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5130 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5131 if (getTriple().isWatchABI()) 5132 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5133 5134 if (!CPUAttr.empty()) 5135 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5136 5137 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5138 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5139 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5140 5141 if (ArchVersion >= 8) { 5142 // ACLE 6.5.7 Crypto Extension 5143 if (Crypto) 5144 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5145 // ACLE 6.5.8 CRC32 Extension 5146 if (CRC) 5147 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5148 // ACLE 6.5.10 Numeric Maximum and Minimum 5149 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5150 // ACLE 6.5.9 Directed Rounding 5151 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5152 } 5153 5154 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5155 // is not defined for the M-profile. 5156 // NOTE that the default profile is assumed to be 'A' 5157 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5158 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5159 5160 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5161 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5162 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5163 // v7 and v8 architectures excluding v8-M Baseline. 5164 if (supportsThumb2()) 5165 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5166 else if (supportsThumb()) 5167 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5168 5169 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5170 // instruction set such as ARM or Thumb. 5171 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5172 5173 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5174 5175 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5176 if (!CPUProfile.empty()) 5177 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5178 5179 // ACLE 6.4.3 Unaligned access supported in hardware 5180 if (Unaligned) 5181 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5182 5183 // ACLE 6.4.4 LDREX/STREX 5184 if (LDREX) 5185 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5186 5187 // ACLE 6.4.5 CLZ 5188 if (ArchVersion == 5 || 5189 (ArchVersion == 6 && CPUProfile != "M") || 5190 ArchVersion > 6) 5191 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5192 5193 // ACLE 6.5.1 Hardware Floating Point 5194 if (HW_FP) 5195 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5196 5197 // ACLE predefines. 5198 Builder.defineMacro("__ARM_ACLE", "200"); 5199 5200 // FP16 support (we currently only support IEEE format). 5201 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5202 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5203 5204 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5205 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5206 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5207 5208 // Subtarget options. 5209 5210 // FIXME: It's more complicated than this and we don't really support 5211 // interworking. 5212 // Windows on ARM does not "support" interworking 5213 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5214 Builder.defineMacro("__THUMB_INTERWORK__"); 5215 5216 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5217 // Embedded targets on Darwin follow AAPCS, but not EABI. 5218 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5219 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5220 Builder.defineMacro("__ARM_EABI__"); 5221 Builder.defineMacro("__ARM_PCS", "1"); 5222 } 5223 5224 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5225 ABI == "aapcs16") 5226 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5227 5228 if (SoftFloat) 5229 Builder.defineMacro("__SOFTFP__"); 5230 5231 if (CPU == "xscale") 5232 Builder.defineMacro("__XSCALE__"); 5233 5234 if (isThumb()) { 5235 Builder.defineMacro("__THUMBEL__"); 5236 Builder.defineMacro("__thumb__"); 5237 if (supportsThumb2()) 5238 Builder.defineMacro("__thumb2__"); 5239 } 5240 5241 // ACLE 6.4.9 32-bit SIMD instructions 5242 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5243 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5244 5245 // ACLE 6.4.10 Hardware Integer Divide 5246 if (((HWDiv & HWDivThumb) && isThumb()) || 5247 ((HWDiv & HWDivARM) && !isThumb())) { 5248 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5249 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5250 } 5251 5252 // Note, this is always on in gcc, even though it doesn't make sense. 5253 Builder.defineMacro("__APCS_32__"); 5254 5255 if (FPUModeIsVFP((FPUMode) FPU)) { 5256 Builder.defineMacro("__VFP_FP__"); 5257 if (FPU & VFP2FPU) 5258 Builder.defineMacro("__ARM_VFPV2__"); 5259 if (FPU & VFP3FPU) 5260 Builder.defineMacro("__ARM_VFPV3__"); 5261 if (FPU & VFP4FPU) 5262 Builder.defineMacro("__ARM_VFPV4__"); 5263 } 5264 5265 // This only gets set when Neon instructions are actually available, unlike 5266 // the VFP define, hence the soft float and arch check. This is subtly 5267 // different from gcc, we follow the intent which was that it should be set 5268 // when Neon instructions are actually available. 5269 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5270 Builder.defineMacro("__ARM_NEON", "1"); 5271 Builder.defineMacro("__ARM_NEON__"); 5272 // current AArch32 NEON implementations do not support double-precision 5273 // floating-point even when it is present in VFP. 5274 Builder.defineMacro("__ARM_NEON_FP", 5275 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5276 } 5277 5278 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5279 Opts.ShortWChar ? "2" : "4"); 5280 5281 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5282 Opts.ShortEnums ? "1" : "4"); 5283 5284 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5285 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5286 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5287 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5288 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5289 } 5290 5291 // ACLE 6.4.7 DSP instructions 5292 if (DSP) { 5293 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5294 } 5295 5296 // ACLE 6.4.8 Saturation instructions 5297 bool SAT = false; 5298 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5299 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5300 SAT = true; 5301 } 5302 5303 // ACLE 6.4.6 Q (saturation) flag 5304 if (DSP || SAT) 5305 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5306 5307 if (Opts.UnsafeFPMath) 5308 Builder.defineMacro("__ARM_FP_FAST", "1"); 5309 5310 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5311 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5312 } 5313 5314 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5315 return llvm::makeArrayRef(BuiltinInfo, 5316 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5317 } 5318 bool isCLZForZeroUndef() const override { return false; } 5319 BuiltinVaListKind getBuiltinVaListKind() const override { 5320 return IsAAPCS 5321 ? AAPCSABIBuiltinVaList 5322 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5323 : TargetInfo::VoidPtrBuiltinVaList); 5324 } 5325 ArrayRef<const char *> getGCCRegNames() const override; 5326 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5327 bool validateAsmConstraint(const char *&Name, 5328 TargetInfo::ConstraintInfo &Info) const override { 5329 switch (*Name) { 5330 default: break; 5331 case 'l': // r0-r7 5332 case 'h': // r8-r15 5333 case 't': // VFP Floating point register single precision 5334 case 'w': // VFP Floating point register double precision 5335 Info.setAllowsRegister(); 5336 return true; 5337 case 'I': 5338 case 'J': 5339 case 'K': 5340 case 'L': 5341 case 'M': 5342 // FIXME 5343 return true; 5344 case 'Q': // A memory address that is a single base register. 5345 Info.setAllowsMemory(); 5346 return true; 5347 case 'U': // a memory reference... 5348 switch (Name[1]) { 5349 case 'q': // ...ARMV4 ldrsb 5350 case 'v': // ...VFP load/store (reg+constant offset) 5351 case 'y': // ...iWMMXt load/store 5352 case 't': // address valid for load/store opaque types wider 5353 // than 128-bits 5354 case 'n': // valid address for Neon doubleword vector load/store 5355 case 'm': // valid address for Neon element and structure load/store 5356 case 's': // valid address for non-offset loads/stores of quad-word 5357 // values in four ARM registers 5358 Info.setAllowsMemory(); 5359 Name++; 5360 return true; 5361 } 5362 } 5363 return false; 5364 } 5365 std::string convertConstraint(const char *&Constraint) const override { 5366 std::string R; 5367 switch (*Constraint) { 5368 case 'U': // Two-character constraint; add "^" hint for later parsing. 5369 R = std::string("^") + std::string(Constraint, 2); 5370 Constraint++; 5371 break; 5372 case 'p': // 'p' should be translated to 'r' by default. 5373 R = std::string("r"); 5374 break; 5375 default: 5376 return std::string(1, *Constraint); 5377 } 5378 return R; 5379 } 5380 bool 5381 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5382 std::string &SuggestedModifier) const override { 5383 bool isOutput = (Constraint[0] == '='); 5384 bool isInOut = (Constraint[0] == '+'); 5385 5386 // Strip off constraint modifiers. 5387 while (Constraint[0] == '=' || 5388 Constraint[0] == '+' || 5389 Constraint[0] == '&') 5390 Constraint = Constraint.substr(1); 5391 5392 switch (Constraint[0]) { 5393 default: break; 5394 case 'r': { 5395 switch (Modifier) { 5396 default: 5397 return (isInOut || isOutput || Size <= 64); 5398 case 'q': 5399 // A register of size 32 cannot fit a vector type. 5400 return false; 5401 } 5402 } 5403 } 5404 5405 return true; 5406 } 5407 const char *getClobbers() const override { 5408 // FIXME: Is this really right? 5409 return ""; 5410 } 5411 5412 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5413 switch (CC) { 5414 case CC_AAPCS: 5415 case CC_AAPCS_VFP: 5416 case CC_Swift: 5417 return CCCR_OK; 5418 default: 5419 return CCCR_Warning; 5420 } 5421 } 5422 5423 int getEHDataRegisterNumber(unsigned RegNo) const override { 5424 if (RegNo == 0) return 0; 5425 if (RegNo == 1) return 1; 5426 return -1; 5427 } 5428 5429 bool hasSjLjLowering() const override { 5430 return true; 5431 } 5432 }; 5433 5434 bool ARMTargetInfo::setFPMath(StringRef Name) { 5435 if (Name == "neon") { 5436 FPMath = FP_Neon; 5437 return true; 5438 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5439 Name == "vfp4") { 5440 FPMath = FP_VFP; 5441 return true; 5442 } 5443 return false; 5444 } 5445 5446 const char * const ARMTargetInfo::GCCRegNames[] = { 5447 // Integer registers 5448 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5449 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5450 5451 // Float registers 5452 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5453 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5454 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5455 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5456 5457 // Double registers 5458 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5459 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5460 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5461 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5462 5463 // Quad registers 5464 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5465 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5466 }; 5467 5468 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5469 return llvm::makeArrayRef(GCCRegNames); 5470 } 5471 5472 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5473 { { "a1" }, "r0" }, 5474 { { "a2" }, "r1" }, 5475 { { "a3" }, "r2" }, 5476 { { "a4" }, "r3" }, 5477 { { "v1" }, "r4" }, 5478 { { "v2" }, "r5" }, 5479 { { "v3" }, "r6" }, 5480 { { "v4" }, "r7" }, 5481 { { "v5" }, "r8" }, 5482 { { "v6", "rfp" }, "r9" }, 5483 { { "sl" }, "r10" }, 5484 { { "fp" }, "r11" }, 5485 { { "ip" }, "r12" }, 5486 { { "r13" }, "sp" }, 5487 { { "r14" }, "lr" }, 5488 { { "r15" }, "pc" }, 5489 // The S, D and Q registers overlap, but aren't really aliases; we 5490 // don't want to substitute one of these for a different-sized one. 5491 }; 5492 5493 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5494 return llvm::makeArrayRef(GCCRegAliases); 5495 } 5496 5497 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5498 #define BUILTIN(ID, TYPE, ATTRS) \ 5499 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5500 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5501 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5502 #include "clang/Basic/BuiltinsNEON.def" 5503 5504 #define BUILTIN(ID, TYPE, ATTRS) \ 5505 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5506 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5507 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5508 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5509 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5510 #include "clang/Basic/BuiltinsARM.def" 5511 }; 5512 5513 class ARMleTargetInfo : public ARMTargetInfo { 5514 public: 5515 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5516 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/false) {} 5517 void getTargetDefines(const LangOptions &Opts, 5518 MacroBuilder &Builder) const override { 5519 Builder.defineMacro("__ARMEL__"); 5520 ARMTargetInfo::getTargetDefines(Opts, Builder); 5521 } 5522 }; 5523 5524 class ARMbeTargetInfo : public ARMTargetInfo { 5525 public: 5526 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5527 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/true) {} 5528 void getTargetDefines(const LangOptions &Opts, 5529 MacroBuilder &Builder) const override { 5530 Builder.defineMacro("__ARMEB__"); 5531 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5532 ARMTargetInfo::getTargetDefines(Opts, Builder); 5533 } 5534 }; 5535 5536 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5537 const llvm::Triple Triple; 5538 public: 5539 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5540 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5541 WCharType = UnsignedShort; 5542 SizeType = UnsignedInt; 5543 } 5544 void getVisualStudioDefines(const LangOptions &Opts, 5545 MacroBuilder &Builder) const { 5546 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5547 5548 // FIXME: this is invalid for WindowsCE 5549 Builder.defineMacro("_M_ARM_NT", "1"); 5550 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5551 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5552 5553 assert((Triple.getArch() == llvm::Triple::arm || 5554 Triple.getArch() == llvm::Triple::thumb) && 5555 "invalid architecture for Windows ARM target info"); 5556 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5557 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5558 5559 // TODO map the complete set of values 5560 // 31: VFPv3 40: VFPv4 5561 Builder.defineMacro("_M_ARM_FP", "31"); 5562 } 5563 BuiltinVaListKind getBuiltinVaListKind() const override { 5564 return TargetInfo::CharPtrBuiltinVaList; 5565 } 5566 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5567 switch (CC) { 5568 case CC_X86StdCall: 5569 case CC_X86ThisCall: 5570 case CC_X86FastCall: 5571 case CC_X86VectorCall: 5572 return CCCR_Ignore; 5573 case CC_C: 5574 return CCCR_OK; 5575 default: 5576 return CCCR_Warning; 5577 } 5578 } 5579 }; 5580 5581 // Windows ARM + Itanium C++ ABI Target 5582 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5583 public: 5584 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5585 const TargetOptions &Opts) 5586 : WindowsARMTargetInfo(Triple, Opts) { 5587 TheCXXABI.set(TargetCXXABI::GenericARM); 5588 } 5589 5590 void getTargetDefines(const LangOptions &Opts, 5591 MacroBuilder &Builder) const override { 5592 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5593 5594 if (Opts.MSVCCompat) 5595 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5596 } 5597 }; 5598 5599 // Windows ARM, MS (C++) ABI 5600 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5601 public: 5602 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5603 const TargetOptions &Opts) 5604 : WindowsARMTargetInfo(Triple, Opts) { 5605 TheCXXABI.set(TargetCXXABI::Microsoft); 5606 } 5607 5608 void getTargetDefines(const LangOptions &Opts, 5609 MacroBuilder &Builder) const override { 5610 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5611 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5612 } 5613 }; 5614 5615 // ARM MinGW target 5616 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5617 public: 5618 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5619 : WindowsARMTargetInfo(Triple, Opts) { 5620 TheCXXABI.set(TargetCXXABI::GenericARM); 5621 } 5622 5623 void getTargetDefines(const LangOptions &Opts, 5624 MacroBuilder &Builder) const override { 5625 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5626 DefineStd(Builder, "WIN32", Opts); 5627 DefineStd(Builder, "WINNT", Opts); 5628 Builder.defineMacro("_ARM_"); 5629 addMinGWDefines(Opts, Builder); 5630 } 5631 }; 5632 5633 // ARM Cygwin target 5634 class CygwinARMTargetInfo : public ARMleTargetInfo { 5635 public: 5636 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5637 : ARMleTargetInfo(Triple, Opts) { 5638 TLSSupported = false; 5639 WCharType = UnsignedShort; 5640 DoubleAlign = LongLongAlign = 64; 5641 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5642 } 5643 void getTargetDefines(const LangOptions &Opts, 5644 MacroBuilder &Builder) const override { 5645 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5646 Builder.defineMacro("_ARM_"); 5647 Builder.defineMacro("__CYGWIN__"); 5648 Builder.defineMacro("__CYGWIN32__"); 5649 DefineStd(Builder, "unix", Opts); 5650 if (Opts.CPlusPlus) 5651 Builder.defineMacro("_GNU_SOURCE"); 5652 } 5653 }; 5654 5655 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5656 protected: 5657 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5658 MacroBuilder &Builder) const override { 5659 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5660 } 5661 5662 public: 5663 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5664 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5665 HasAlignMac68kSupport = true; 5666 // iOS always has 64-bit atomic instructions. 5667 // FIXME: This should be based off of the target features in 5668 // ARMleTargetInfo. 5669 MaxAtomicInlineWidth = 64; 5670 5671 if (Triple.isWatchABI()) { 5672 // Darwin on iOS uses a variant of the ARM C++ ABI. 5673 TheCXXABI.set(TargetCXXABI::WatchOS); 5674 5675 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5676 // size_t is long, it's a bit weird for it to be int. 5677 PtrDiffType = SignedLong; 5678 5679 // BOOL should be a real boolean on the new ABI 5680 UseSignedCharForObjCBool = false; 5681 } else 5682 TheCXXABI.set(TargetCXXABI::iOS); 5683 } 5684 }; 5685 5686 class AArch64TargetInfo : public TargetInfo { 5687 virtual void setDataLayout() = 0; 5688 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5689 static const char *const GCCRegNames[]; 5690 5691 enum FPUModeEnum { 5692 FPUMode, 5693 NeonMode 5694 }; 5695 5696 unsigned FPU; 5697 unsigned CRC; 5698 unsigned Crypto; 5699 unsigned Unaligned; 5700 unsigned V8_1A; 5701 5702 static const Builtin::Info BuiltinInfo[]; 5703 5704 std::string ABI; 5705 5706 public: 5707 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5708 : TargetInfo(Triple), ABI("aapcs") { 5709 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5710 WCharType = SignedInt; 5711 5712 // NetBSD apparently prefers consistency across ARM targets to consistency 5713 // across 64-bit targets. 5714 Int64Type = SignedLongLong; 5715 IntMaxType = SignedLongLong; 5716 } else { 5717 WCharType = UnsignedInt; 5718 Int64Type = SignedLong; 5719 IntMaxType = SignedLong; 5720 } 5721 5722 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5723 MaxVectorAlign = 128; 5724 MaxAtomicInlineWidth = 128; 5725 MaxAtomicPromoteWidth = 128; 5726 5727 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5728 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5729 5730 // {} in inline assembly are neon specifiers, not assembly variant 5731 // specifiers. 5732 NoAsmVariants = true; 5733 5734 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5735 // contributes to the alignment of the containing aggregate in the same way 5736 // a plain (non bit-field) member of that type would, without exception for 5737 // zero-sized or anonymous bit-fields." 5738 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5739 UseZeroLengthBitfieldAlignment = true; 5740 5741 // AArch64 targets default to using the ARM C++ ABI. 5742 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5743 5744 if (Triple.getOS() == llvm::Triple::Linux || 5745 Triple.getOS() == llvm::Triple::UnknownOS) 5746 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5747 } 5748 5749 StringRef getABI() const override { return ABI; } 5750 bool setABI(const std::string &Name) override { 5751 if (Name != "aapcs" && Name != "darwinpcs") 5752 return false; 5753 5754 ABI = Name; 5755 return true; 5756 } 5757 5758 bool setCPU(const std::string &Name) override { 5759 return Name == "generic" || 5760 llvm::AArch64::parseCPUArch(Name) != 5761 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 5762 } 5763 5764 void getTargetDefines(const LangOptions &Opts, 5765 MacroBuilder &Builder) const override { 5766 // Target identification. 5767 Builder.defineMacro("__aarch64__"); 5768 5769 // Target properties. 5770 Builder.defineMacro("_LP64"); 5771 Builder.defineMacro("__LP64__"); 5772 5773 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5774 Builder.defineMacro("__ARM_ACLE", "200"); 5775 Builder.defineMacro("__ARM_ARCH", "8"); 5776 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5777 5778 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5779 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5780 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5781 5782 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5783 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5784 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5785 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5786 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5787 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5788 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5789 5790 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5791 5792 // 0xe implies support for half, single and double precision operations. 5793 Builder.defineMacro("__ARM_FP", "0xE"); 5794 5795 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5796 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5797 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5798 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5799 5800 if (Opts.UnsafeFPMath) 5801 Builder.defineMacro("__ARM_FP_FAST", "1"); 5802 5803 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5804 5805 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5806 Opts.ShortEnums ? "1" : "4"); 5807 5808 if (FPU == NeonMode) { 5809 Builder.defineMacro("__ARM_NEON", "1"); 5810 // 64-bit NEON supports half, single and double precision operations. 5811 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5812 } 5813 5814 if (CRC) 5815 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5816 5817 if (Crypto) 5818 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5819 5820 if (Unaligned) 5821 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5822 5823 if (V8_1A) 5824 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5825 5826 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5827 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5828 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5829 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5830 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5831 } 5832 5833 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5834 return llvm::makeArrayRef(BuiltinInfo, 5835 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5836 } 5837 5838 bool hasFeature(StringRef Feature) const override { 5839 return Feature == "aarch64" || 5840 Feature == "arm64" || 5841 Feature == "arm" || 5842 (Feature == "neon" && FPU == NeonMode); 5843 } 5844 5845 bool handleTargetFeatures(std::vector<std::string> &Features, 5846 DiagnosticsEngine &Diags) override { 5847 FPU = FPUMode; 5848 CRC = 0; 5849 Crypto = 0; 5850 Unaligned = 1; 5851 V8_1A = 0; 5852 5853 for (const auto &Feature : Features) { 5854 if (Feature == "+neon") 5855 FPU = NeonMode; 5856 if (Feature == "+crc") 5857 CRC = 1; 5858 if (Feature == "+crypto") 5859 Crypto = 1; 5860 if (Feature == "+strict-align") 5861 Unaligned = 0; 5862 if (Feature == "+v8.1a") 5863 V8_1A = 1; 5864 } 5865 5866 setDataLayout(); 5867 5868 return true; 5869 } 5870 5871 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5872 switch (CC) { 5873 case CC_C: 5874 case CC_Swift: 5875 case CC_PreserveMost: 5876 case CC_PreserveAll: 5877 return CCCR_OK; 5878 default: 5879 return CCCR_Warning; 5880 } 5881 } 5882 5883 bool isCLZForZeroUndef() const override { return false; } 5884 5885 BuiltinVaListKind getBuiltinVaListKind() const override { 5886 return TargetInfo::AArch64ABIBuiltinVaList; 5887 } 5888 5889 ArrayRef<const char *> getGCCRegNames() const override; 5890 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5891 5892 bool validateAsmConstraint(const char *&Name, 5893 TargetInfo::ConstraintInfo &Info) const override { 5894 switch (*Name) { 5895 default: 5896 return false; 5897 case 'w': // Floating point and SIMD registers (V0-V31) 5898 Info.setAllowsRegister(); 5899 return true; 5900 case 'I': // Constant that can be used with an ADD instruction 5901 case 'J': // Constant that can be used with a SUB instruction 5902 case 'K': // Constant that can be used with a 32-bit logical instruction 5903 case 'L': // Constant that can be used with a 64-bit logical instruction 5904 case 'M': // Constant that can be used as a 32-bit MOV immediate 5905 case 'N': // Constant that can be used as a 64-bit MOV immediate 5906 case 'Y': // Floating point constant zero 5907 case 'Z': // Integer constant zero 5908 return true; 5909 case 'Q': // A memory reference with base register and no offset 5910 Info.setAllowsMemory(); 5911 return true; 5912 case 'S': // A symbolic address 5913 Info.setAllowsRegister(); 5914 return true; 5915 case 'U': 5916 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5917 // Utf: A memory address suitable for ldp/stp in TF mode. 5918 // Usa: An absolute symbolic address. 5919 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5920 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5921 case 'z': // Zero register, wzr or xzr 5922 Info.setAllowsRegister(); 5923 return true; 5924 case 'x': // Floating point and SIMD registers (V0-V15) 5925 Info.setAllowsRegister(); 5926 return true; 5927 } 5928 return false; 5929 } 5930 5931 bool 5932 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5933 std::string &SuggestedModifier) const override { 5934 // Strip off constraint modifiers. 5935 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5936 Constraint = Constraint.substr(1); 5937 5938 switch (Constraint[0]) { 5939 default: 5940 return true; 5941 case 'z': 5942 case 'r': { 5943 switch (Modifier) { 5944 case 'x': 5945 case 'w': 5946 // For now assume that the person knows what they're 5947 // doing with the modifier. 5948 return true; 5949 default: 5950 // By default an 'r' constraint will be in the 'x' 5951 // registers. 5952 if (Size == 64) 5953 return true; 5954 5955 SuggestedModifier = "w"; 5956 return false; 5957 } 5958 } 5959 } 5960 } 5961 5962 const char *getClobbers() const override { return ""; } 5963 5964 int getEHDataRegisterNumber(unsigned RegNo) const override { 5965 if (RegNo == 0) 5966 return 0; 5967 if (RegNo == 1) 5968 return 1; 5969 return -1; 5970 } 5971 }; 5972 5973 const char *const AArch64TargetInfo::GCCRegNames[] = { 5974 // 32-bit Integer registers 5975 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5976 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5977 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5978 5979 // 64-bit Integer registers 5980 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5981 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5982 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5983 5984 // 32-bit floating point regsisters 5985 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5986 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5987 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5988 5989 // 64-bit floating point regsisters 5990 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5991 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5992 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5993 5994 // Vector registers 5995 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5996 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5997 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5998 }; 5999 6000 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6001 return llvm::makeArrayRef(GCCRegNames); 6002 } 6003 6004 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6005 { { "w31" }, "wsp" }, 6006 { { "x29" }, "fp" }, 6007 { { "x30" }, "lr" }, 6008 { { "x31" }, "sp" }, 6009 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6010 // don't want to substitute one of these for a different-sized one. 6011 }; 6012 6013 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6014 return llvm::makeArrayRef(GCCRegAliases); 6015 } 6016 6017 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6018 #define BUILTIN(ID, TYPE, ATTRS) \ 6019 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6020 #include "clang/Basic/BuiltinsNEON.def" 6021 6022 #define BUILTIN(ID, TYPE, ATTRS) \ 6023 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6024 #include "clang/Basic/BuiltinsAArch64.def" 6025 }; 6026 6027 class AArch64leTargetInfo : public AArch64TargetInfo { 6028 void setDataLayout() override { 6029 if (getTriple().isOSBinFormatMachO()) 6030 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6031 else 6032 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6033 } 6034 6035 public: 6036 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6037 : AArch64TargetInfo(Triple, Opts) { 6038 BigEndian = false; 6039 } 6040 void getTargetDefines(const LangOptions &Opts, 6041 MacroBuilder &Builder) const override { 6042 Builder.defineMacro("__AARCH64EL__"); 6043 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6044 } 6045 }; 6046 6047 class AArch64beTargetInfo : public AArch64TargetInfo { 6048 void setDataLayout() override { 6049 assert(!getTriple().isOSBinFormatMachO()); 6050 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6051 } 6052 6053 public: 6054 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6055 : AArch64TargetInfo(Triple, Opts) {} 6056 void getTargetDefines(const LangOptions &Opts, 6057 MacroBuilder &Builder) const override { 6058 Builder.defineMacro("__AARCH64EB__"); 6059 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6060 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6061 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6062 } 6063 }; 6064 6065 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6066 protected: 6067 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6068 MacroBuilder &Builder) const override { 6069 Builder.defineMacro("__AARCH64_SIMD__"); 6070 Builder.defineMacro("__ARM64_ARCH_8__"); 6071 Builder.defineMacro("__ARM_NEON__"); 6072 Builder.defineMacro("__LITTLE_ENDIAN__"); 6073 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6074 Builder.defineMacro("__arm64", "1"); 6075 Builder.defineMacro("__arm64__", "1"); 6076 6077 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6078 } 6079 6080 public: 6081 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6082 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6083 Int64Type = SignedLongLong; 6084 WCharType = SignedInt; 6085 UseSignedCharForObjCBool = false; 6086 6087 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6088 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6089 6090 TheCXXABI.set(TargetCXXABI::iOS64); 6091 } 6092 6093 BuiltinVaListKind getBuiltinVaListKind() const override { 6094 return TargetInfo::CharPtrBuiltinVaList; 6095 } 6096 }; 6097 6098 // Hexagon abstract base class 6099 class HexagonTargetInfo : public TargetInfo { 6100 static const Builtin::Info BuiltinInfo[]; 6101 static const char * const GCCRegNames[]; 6102 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6103 std::string CPU; 6104 bool HasHVX, HasHVXDouble; 6105 6106 public: 6107 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6108 : TargetInfo(Triple) { 6109 BigEndian = false; 6110 // Specify the vector alignment explicitly. For v512x1, the calculated 6111 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6112 // the required minimum of 64 bytes. 6113 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6114 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6115 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6116 SizeType = UnsignedInt; 6117 PtrDiffType = SignedInt; 6118 IntPtrType = SignedInt; 6119 6120 // {} in inline assembly are packet specifiers, not assembly variant 6121 // specifiers. 6122 NoAsmVariants = true; 6123 6124 LargeArrayMinWidth = 64; 6125 LargeArrayAlign = 64; 6126 UseBitFieldTypeAlignment = true; 6127 ZeroLengthBitfieldBoundary = 32; 6128 HasHVX = HasHVXDouble = false; 6129 } 6130 6131 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6132 return llvm::makeArrayRef(BuiltinInfo, 6133 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6134 } 6135 6136 bool validateAsmConstraint(const char *&Name, 6137 TargetInfo::ConstraintInfo &Info) const override { 6138 switch (*Name) { 6139 case 'v': 6140 case 'q': 6141 if (HasHVX) { 6142 Info.setAllowsRegister(); 6143 return true; 6144 } 6145 break; 6146 case 's': 6147 // Relocatable constant. 6148 return true; 6149 } 6150 return false; 6151 } 6152 6153 void getTargetDefines(const LangOptions &Opts, 6154 MacroBuilder &Builder) const override; 6155 6156 bool isCLZForZeroUndef() const override { return false; } 6157 6158 bool hasFeature(StringRef Feature) const override { 6159 return llvm::StringSwitch<bool>(Feature) 6160 .Case("hexagon", true) 6161 .Case("hvx", HasHVX) 6162 .Case("hvx-double", HasHVXDouble) 6163 .Default(false); 6164 } 6165 6166 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6167 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6168 const override; 6169 6170 bool handleTargetFeatures(std::vector<std::string> &Features, 6171 DiagnosticsEngine &Diags) override; 6172 6173 BuiltinVaListKind getBuiltinVaListKind() const override { 6174 return TargetInfo::CharPtrBuiltinVaList; 6175 } 6176 ArrayRef<const char *> getGCCRegNames() const override; 6177 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6178 const char *getClobbers() const override { 6179 return ""; 6180 } 6181 6182 static const char *getHexagonCPUSuffix(StringRef Name) { 6183 return llvm::StringSwitch<const char*>(Name) 6184 .Case("hexagonv4", "4") 6185 .Case("hexagonv5", "5") 6186 .Case("hexagonv55", "55") 6187 .Case("hexagonv60", "60") 6188 .Default(nullptr); 6189 } 6190 6191 bool setCPU(const std::string &Name) override { 6192 if (!getHexagonCPUSuffix(Name)) 6193 return false; 6194 CPU = Name; 6195 return true; 6196 } 6197 6198 int getEHDataRegisterNumber(unsigned RegNo) const override { 6199 return RegNo < 2 ? RegNo : -1; 6200 } 6201 }; 6202 6203 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6204 MacroBuilder &Builder) const { 6205 Builder.defineMacro("__qdsp6__", "1"); 6206 Builder.defineMacro("__hexagon__", "1"); 6207 6208 if (CPU == "hexagonv4") { 6209 Builder.defineMacro("__HEXAGON_V4__"); 6210 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6211 if (Opts.HexagonQdsp6Compat) { 6212 Builder.defineMacro("__QDSP6_V4__"); 6213 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6214 } 6215 } else if (CPU == "hexagonv5") { 6216 Builder.defineMacro("__HEXAGON_V5__"); 6217 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6218 if(Opts.HexagonQdsp6Compat) { 6219 Builder.defineMacro("__QDSP6_V5__"); 6220 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6221 } 6222 } else if (CPU == "hexagonv55") { 6223 Builder.defineMacro("__HEXAGON_V55__"); 6224 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6225 Builder.defineMacro("__QDSP6_V55__"); 6226 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6227 } else if (CPU == "hexagonv60") { 6228 Builder.defineMacro("__HEXAGON_V60__"); 6229 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6230 Builder.defineMacro("__QDSP6_V60__"); 6231 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6232 } 6233 6234 if (hasFeature("hvx")) { 6235 Builder.defineMacro("__HVX__"); 6236 if (hasFeature("hvx-double")) 6237 Builder.defineMacro("__HVXDBL__"); 6238 } 6239 } 6240 6241 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6242 DiagnosticsEngine &Diags) { 6243 for (auto &F : Features) { 6244 if (F == "+hvx") 6245 HasHVX = true; 6246 else if (F == "-hvx") 6247 HasHVX = HasHVXDouble = false; 6248 else if (F == "+hvx-double") 6249 HasHVX = HasHVXDouble = true; 6250 else if (F == "-hvx-double") 6251 HasHVXDouble = false; 6252 } 6253 return true; 6254 } 6255 6256 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6257 DiagnosticsEngine &Diags, StringRef CPU, 6258 const std::vector<std::string> &FeaturesVec) const { 6259 // Default for v60: -hvx, -hvx-double. 6260 Features["hvx"] = false; 6261 Features["hvx-double"] = false; 6262 6263 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6264 } 6265 6266 6267 const char *const HexagonTargetInfo::GCCRegNames[] = { 6268 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6269 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6270 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6271 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6272 "p0", "p1", "p2", "p3", 6273 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6274 }; 6275 6276 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6277 return llvm::makeArrayRef(GCCRegNames); 6278 } 6279 6280 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6281 { { "sp" }, "r29" }, 6282 { { "fp" }, "r30" }, 6283 { { "lr" }, "r31" }, 6284 }; 6285 6286 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6287 return llvm::makeArrayRef(GCCRegAliases); 6288 } 6289 6290 6291 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6292 #define BUILTIN(ID, TYPE, ATTRS) \ 6293 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6294 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6295 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6296 #include "clang/Basic/BuiltinsHexagon.def" 6297 }; 6298 6299 class LanaiTargetInfo : public TargetInfo { 6300 // Class for Lanai (32-bit). 6301 // The CPU profiles supported by the Lanai backend 6302 enum CPUKind { 6303 CK_NONE, 6304 CK_V11, 6305 } CPU; 6306 6307 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6308 static const char *const GCCRegNames[]; 6309 6310 public: 6311 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6312 : TargetInfo(Triple) { 6313 // Description string has to be kept in sync with backend. 6314 resetDataLayout("E" // Big endian 6315 "-m:e" // ELF name manging 6316 "-p:32:32" // 32 bit pointers, 32 bit aligned 6317 "-i64:64" // 64 bit integers, 64 bit aligned 6318 "-a:0:32" // 32 bit alignment of objects of aggregate type 6319 "-n32" // 32 bit native integer width 6320 "-S64" // 64 bit natural stack alignment 6321 ); 6322 6323 // Setting RegParmMax equal to what mregparm was set to in the old 6324 // toolchain 6325 RegParmMax = 4; 6326 6327 // Set the default CPU to V11 6328 CPU = CK_V11; 6329 6330 // Temporary approach to make everything at least word-aligned and allow for 6331 // safely casting between pointers with different alignment requirements. 6332 // TODO: Remove this when there are no more cast align warnings on the 6333 // firmware. 6334 MinGlobalAlign = 32; 6335 } 6336 6337 void getTargetDefines(const LangOptions &Opts, 6338 MacroBuilder &Builder) const override { 6339 // Define __lanai__ when building for target lanai. 6340 Builder.defineMacro("__lanai__"); 6341 6342 // Set define for the CPU specified. 6343 switch (CPU) { 6344 case CK_V11: 6345 Builder.defineMacro("__LANAI_V11__"); 6346 break; 6347 case CK_NONE: 6348 llvm_unreachable("Unhandled target CPU"); 6349 } 6350 } 6351 6352 bool setCPU(const std::string &Name) override { 6353 CPU = llvm::StringSwitch<CPUKind>(Name) 6354 .Case("v11", CK_V11) 6355 .Default(CK_NONE); 6356 6357 return CPU != CK_NONE; 6358 } 6359 6360 bool hasFeature(StringRef Feature) const override { 6361 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6362 } 6363 6364 ArrayRef<const char *> getGCCRegNames() const override; 6365 6366 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6367 6368 BuiltinVaListKind getBuiltinVaListKind() const override { 6369 return TargetInfo::VoidPtrBuiltinVaList; 6370 } 6371 6372 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6373 6374 bool validateAsmConstraint(const char *&Name, 6375 TargetInfo::ConstraintInfo &info) const override { 6376 return false; 6377 } 6378 6379 const char *getClobbers() const override { return ""; } 6380 }; 6381 6382 const char *const LanaiTargetInfo::GCCRegNames[] = { 6383 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6384 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6385 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6386 6387 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6388 return llvm::makeArrayRef(GCCRegNames); 6389 } 6390 6391 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6392 {{"pc"}, "r2"}, 6393 {{"sp"}, "r4"}, 6394 {{"fp"}, "r5"}, 6395 {{"rv"}, "r8"}, 6396 {{"rr1"}, "r10"}, 6397 {{"rr2"}, "r11"}, 6398 {{"rca"}, "r15"}, 6399 }; 6400 6401 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6402 return llvm::makeArrayRef(GCCRegAliases); 6403 } 6404 6405 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6406 class SparcTargetInfo : public TargetInfo { 6407 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6408 static const char * const GCCRegNames[]; 6409 bool SoftFloat; 6410 public: 6411 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6412 : TargetInfo(Triple), SoftFloat(false) {} 6413 6414 int getEHDataRegisterNumber(unsigned RegNo) const override { 6415 if (RegNo == 0) return 24; 6416 if (RegNo == 1) return 25; 6417 return -1; 6418 } 6419 6420 bool handleTargetFeatures(std::vector<std::string> &Features, 6421 DiagnosticsEngine &Diags) override { 6422 // Check if software floating point is enabled 6423 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6424 if (Feature != Features.end()) { 6425 SoftFloat = true; 6426 } 6427 return true; 6428 } 6429 void getTargetDefines(const LangOptions &Opts, 6430 MacroBuilder &Builder) const override { 6431 DefineStd(Builder, "sparc", Opts); 6432 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6433 6434 if (SoftFloat) 6435 Builder.defineMacro("SOFT_FLOAT", "1"); 6436 } 6437 6438 bool hasFeature(StringRef Feature) const override { 6439 return llvm::StringSwitch<bool>(Feature) 6440 .Case("softfloat", SoftFloat) 6441 .Case("sparc", true) 6442 .Default(false); 6443 } 6444 6445 bool hasSjLjLowering() const override { 6446 return true; 6447 } 6448 6449 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6450 // FIXME: Implement! 6451 return None; 6452 } 6453 BuiltinVaListKind getBuiltinVaListKind() const override { 6454 return TargetInfo::VoidPtrBuiltinVaList; 6455 } 6456 ArrayRef<const char *> getGCCRegNames() const override; 6457 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6458 bool validateAsmConstraint(const char *&Name, 6459 TargetInfo::ConstraintInfo &info) const override { 6460 // FIXME: Implement! 6461 switch (*Name) { 6462 case 'I': // Signed 13-bit constant 6463 case 'J': // Zero 6464 case 'K': // 32-bit constant with the low 12 bits clear 6465 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6466 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6467 case 'N': // Same as 'K' but zext (required for SIMode) 6468 case 'O': // The constant 4096 6469 return true; 6470 } 6471 return false; 6472 } 6473 const char *getClobbers() const override { 6474 // FIXME: Implement! 6475 return ""; 6476 } 6477 6478 // No Sparc V7 for now, the backend doesn't support it anyway. 6479 enum CPUKind { 6480 CK_GENERIC, 6481 CK_V8, 6482 CK_SUPERSPARC, 6483 CK_SPARCLITE, 6484 CK_F934, 6485 CK_HYPERSPARC, 6486 CK_SPARCLITE86X, 6487 CK_SPARCLET, 6488 CK_TSC701, 6489 CK_V9, 6490 CK_ULTRASPARC, 6491 CK_ULTRASPARC3, 6492 CK_NIAGARA, 6493 CK_NIAGARA2, 6494 CK_NIAGARA3, 6495 CK_NIAGARA4, 6496 CK_MYRIAD2100, 6497 CK_MYRIAD2150, 6498 CK_MYRIAD2450, 6499 CK_LEON2, 6500 CK_LEON2_AT697E, 6501 CK_LEON2_AT697F, 6502 CK_LEON3, 6503 CK_LEON3_UT699, 6504 CK_LEON3_GR712RC, 6505 CK_LEON4, 6506 CK_LEON4_GR740 6507 } CPU = CK_GENERIC; 6508 6509 enum CPUGeneration { 6510 CG_V8, 6511 CG_V9, 6512 }; 6513 6514 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6515 switch (Kind) { 6516 case CK_GENERIC: 6517 case CK_V8: 6518 case CK_SUPERSPARC: 6519 case CK_SPARCLITE: 6520 case CK_F934: 6521 case CK_HYPERSPARC: 6522 case CK_SPARCLITE86X: 6523 case CK_SPARCLET: 6524 case CK_TSC701: 6525 case CK_MYRIAD2100: 6526 case CK_MYRIAD2150: 6527 case CK_MYRIAD2450: 6528 case CK_LEON2: 6529 case CK_LEON2_AT697E: 6530 case CK_LEON2_AT697F: 6531 case CK_LEON3: 6532 case CK_LEON3_UT699: 6533 case CK_LEON3_GR712RC: 6534 case CK_LEON4: 6535 case CK_LEON4_GR740: 6536 return CG_V8; 6537 case CK_V9: 6538 case CK_ULTRASPARC: 6539 case CK_ULTRASPARC3: 6540 case CK_NIAGARA: 6541 case CK_NIAGARA2: 6542 case CK_NIAGARA3: 6543 case CK_NIAGARA4: 6544 return CG_V9; 6545 } 6546 llvm_unreachable("Unexpected CPU kind"); 6547 } 6548 6549 CPUKind getCPUKind(StringRef Name) const { 6550 return llvm::StringSwitch<CPUKind>(Name) 6551 .Case("v8", CK_V8) 6552 .Case("supersparc", CK_SUPERSPARC) 6553 .Case("sparclite", CK_SPARCLITE) 6554 .Case("f934", CK_F934) 6555 .Case("hypersparc", CK_HYPERSPARC) 6556 .Case("sparclite86x", CK_SPARCLITE86X) 6557 .Case("sparclet", CK_SPARCLET) 6558 .Case("tsc701", CK_TSC701) 6559 .Case("v9", CK_V9) 6560 .Case("ultrasparc", CK_ULTRASPARC) 6561 .Case("ultrasparc3", CK_ULTRASPARC3) 6562 .Case("niagara", CK_NIAGARA) 6563 .Case("niagara2", CK_NIAGARA2) 6564 .Case("niagara3", CK_NIAGARA3) 6565 .Case("niagara4", CK_NIAGARA4) 6566 .Case("ma2100", CK_MYRIAD2100) 6567 .Case("ma2150", CK_MYRIAD2150) 6568 .Case("ma2450", CK_MYRIAD2450) 6569 // FIXME: the myriad2[.n] spellings are obsolete, 6570 // but a grace period is needed to allow updating dependent builds. 6571 .Case("myriad2", CK_MYRIAD2100) 6572 .Case("myriad2.1", CK_MYRIAD2100) 6573 .Case("myriad2.2", CK_MYRIAD2150) 6574 .Case("leon2", CK_LEON2) 6575 .Case("at697e", CK_LEON2_AT697E) 6576 .Case("at697f", CK_LEON2_AT697F) 6577 .Case("leon3", CK_LEON3) 6578 .Case("ut699", CK_LEON3_UT699) 6579 .Case("gr712rc", CK_LEON3_GR712RC) 6580 .Case("leon4", CK_LEON4) 6581 .Case("gr740", CK_LEON4_GR740) 6582 .Default(CK_GENERIC); 6583 } 6584 6585 bool setCPU(const std::string &Name) override { 6586 CPU = getCPUKind(Name); 6587 return CPU != CK_GENERIC; 6588 } 6589 }; 6590 6591 const char * const SparcTargetInfo::GCCRegNames[] = { 6592 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6593 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6594 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6595 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6596 }; 6597 6598 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6599 return llvm::makeArrayRef(GCCRegNames); 6600 } 6601 6602 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6603 { { "g0" }, "r0" }, 6604 { { "g1" }, "r1" }, 6605 { { "g2" }, "r2" }, 6606 { { "g3" }, "r3" }, 6607 { { "g4" }, "r4" }, 6608 { { "g5" }, "r5" }, 6609 { { "g6" }, "r6" }, 6610 { { "g7" }, "r7" }, 6611 { { "o0" }, "r8" }, 6612 { { "o1" }, "r9" }, 6613 { { "o2" }, "r10" }, 6614 { { "o3" }, "r11" }, 6615 { { "o4" }, "r12" }, 6616 { { "o5" }, "r13" }, 6617 { { "o6", "sp" }, "r14" }, 6618 { { "o7" }, "r15" }, 6619 { { "l0" }, "r16" }, 6620 { { "l1" }, "r17" }, 6621 { { "l2" }, "r18" }, 6622 { { "l3" }, "r19" }, 6623 { { "l4" }, "r20" }, 6624 { { "l5" }, "r21" }, 6625 { { "l6" }, "r22" }, 6626 { { "l7" }, "r23" }, 6627 { { "i0" }, "r24" }, 6628 { { "i1" }, "r25" }, 6629 { { "i2" }, "r26" }, 6630 { { "i3" }, "r27" }, 6631 { { "i4" }, "r28" }, 6632 { { "i5" }, "r29" }, 6633 { { "i6", "fp" }, "r30" }, 6634 { { "i7" }, "r31" }, 6635 }; 6636 6637 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6638 return llvm::makeArrayRef(GCCRegAliases); 6639 } 6640 6641 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6642 class SparcV8TargetInfo : public SparcTargetInfo { 6643 public: 6644 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6645 : SparcTargetInfo(Triple, Opts) { 6646 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6647 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6648 switch (getTriple().getOS()) { 6649 default: 6650 SizeType = UnsignedInt; 6651 IntPtrType = SignedInt; 6652 PtrDiffType = SignedInt; 6653 break; 6654 case llvm::Triple::NetBSD: 6655 case llvm::Triple::OpenBSD: 6656 SizeType = UnsignedLong; 6657 IntPtrType = SignedLong; 6658 PtrDiffType = SignedLong; 6659 break; 6660 } 6661 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6662 } 6663 6664 void getTargetDefines(const LangOptions &Opts, 6665 MacroBuilder &Builder) const override { 6666 SparcTargetInfo::getTargetDefines(Opts, Builder); 6667 switch (getCPUGeneration(CPU)) { 6668 case CG_V8: 6669 Builder.defineMacro("__sparcv8"); 6670 if (getTriple().getOS() != llvm::Triple::Solaris) 6671 Builder.defineMacro("__sparcv8__"); 6672 break; 6673 case CG_V9: 6674 Builder.defineMacro("__sparcv9"); 6675 if (getTriple().getOS() != llvm::Triple::Solaris) { 6676 Builder.defineMacro("__sparcv9__"); 6677 Builder.defineMacro("__sparc_v9__"); 6678 } 6679 break; 6680 } 6681 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6682 std::string MyriadArchValue, Myriad2Value; 6683 Builder.defineMacro("__sparc_v8__"); 6684 Builder.defineMacro("__leon__"); 6685 switch (CPU) { 6686 case CK_MYRIAD2150: 6687 MyriadArchValue = "__ma2150"; 6688 Myriad2Value = "2"; 6689 break; 6690 case CK_MYRIAD2450: 6691 MyriadArchValue = "__ma2450"; 6692 Myriad2Value = "2"; 6693 break; 6694 default: 6695 MyriadArchValue = "__ma2100"; 6696 Myriad2Value = "1"; 6697 break; 6698 } 6699 Builder.defineMacro(MyriadArchValue, "1"); 6700 Builder.defineMacro(MyriadArchValue+"__", "1"); 6701 Builder.defineMacro("__myriad2__", Myriad2Value); 6702 Builder.defineMacro("__myriad2", Myriad2Value); 6703 } 6704 } 6705 6706 bool hasSjLjLowering() const override { 6707 return true; 6708 } 6709 }; 6710 6711 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6712 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6713 public: 6714 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6715 : SparcV8TargetInfo(Triple, Opts) { 6716 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6717 BigEndian = false; 6718 } 6719 }; 6720 6721 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6722 class SparcV9TargetInfo : public SparcTargetInfo { 6723 public: 6724 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6725 : SparcTargetInfo(Triple, Opts) { 6726 // FIXME: Support Sparc quad-precision long double? 6727 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6728 // This is an LP64 platform. 6729 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6730 6731 // OpenBSD uses long long for int64_t and intmax_t. 6732 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6733 IntMaxType = SignedLongLong; 6734 else 6735 IntMaxType = SignedLong; 6736 Int64Type = IntMaxType; 6737 6738 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6739 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6740 LongDoubleWidth = 128; 6741 LongDoubleAlign = 128; 6742 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6743 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6744 } 6745 6746 void getTargetDefines(const LangOptions &Opts, 6747 MacroBuilder &Builder) const override { 6748 SparcTargetInfo::getTargetDefines(Opts, Builder); 6749 Builder.defineMacro("__sparcv9"); 6750 Builder.defineMacro("__arch64__"); 6751 // Solaris doesn't need these variants, but the BSDs do. 6752 if (getTriple().getOS() != llvm::Triple::Solaris) { 6753 Builder.defineMacro("__sparc64__"); 6754 Builder.defineMacro("__sparc_v9__"); 6755 Builder.defineMacro("__sparcv9__"); 6756 } 6757 } 6758 6759 bool setCPU(const std::string &Name) override { 6760 if (!SparcTargetInfo::setCPU(Name)) 6761 return false; 6762 return getCPUGeneration(CPU) == CG_V9; 6763 } 6764 }; 6765 6766 class SystemZTargetInfo : public TargetInfo { 6767 static const Builtin::Info BuiltinInfo[]; 6768 static const char *const GCCRegNames[]; 6769 std::string CPU; 6770 bool HasTransactionalExecution; 6771 bool HasVector; 6772 6773 public: 6774 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6775 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6776 HasVector(false) { 6777 IntMaxType = SignedLong; 6778 Int64Type = SignedLong; 6779 TLSSupported = true; 6780 IntWidth = IntAlign = 32; 6781 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6782 PointerWidth = PointerAlign = 64; 6783 LongDoubleWidth = 128; 6784 LongDoubleAlign = 64; 6785 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6786 DefaultAlignForAttributeAligned = 64; 6787 MinGlobalAlign = 16; 6788 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6789 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6790 } 6791 void getTargetDefines(const LangOptions &Opts, 6792 MacroBuilder &Builder) const override { 6793 Builder.defineMacro("__s390__"); 6794 Builder.defineMacro("__s390x__"); 6795 Builder.defineMacro("__zarch__"); 6796 Builder.defineMacro("__LONG_DOUBLE_128__"); 6797 6798 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6799 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6800 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6801 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6802 6803 if (HasTransactionalExecution) 6804 Builder.defineMacro("__HTM__"); 6805 if (Opts.ZVector) 6806 Builder.defineMacro("__VEC__", "10301"); 6807 } 6808 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6809 return llvm::makeArrayRef(BuiltinInfo, 6810 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6811 } 6812 6813 ArrayRef<const char *> getGCCRegNames() const override; 6814 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6815 // No aliases. 6816 return None; 6817 } 6818 bool validateAsmConstraint(const char *&Name, 6819 TargetInfo::ConstraintInfo &info) const override; 6820 const char *getClobbers() const override { 6821 // FIXME: Is this really right? 6822 return ""; 6823 } 6824 BuiltinVaListKind getBuiltinVaListKind() const override { 6825 return TargetInfo::SystemZBuiltinVaList; 6826 } 6827 bool setCPU(const std::string &Name) override { 6828 CPU = Name; 6829 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6830 .Case("z10", true) 6831 .Case("z196", true) 6832 .Case("zEC12", true) 6833 .Case("z13", true) 6834 .Default(false); 6835 6836 return CPUKnown; 6837 } 6838 bool 6839 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6840 StringRef CPU, 6841 const std::vector<std::string> &FeaturesVec) const override { 6842 if (CPU == "zEC12") 6843 Features["transactional-execution"] = true; 6844 if (CPU == "z13") { 6845 Features["transactional-execution"] = true; 6846 Features["vector"] = true; 6847 } 6848 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6849 } 6850 6851 bool handleTargetFeatures(std::vector<std::string> &Features, 6852 DiagnosticsEngine &Diags) override { 6853 HasTransactionalExecution = false; 6854 for (const auto &Feature : Features) { 6855 if (Feature == "+transactional-execution") 6856 HasTransactionalExecution = true; 6857 else if (Feature == "+vector") 6858 HasVector = true; 6859 } 6860 // If we use the vector ABI, vector types are 64-bit aligned. 6861 if (HasVector) { 6862 MaxVectorAlign = 64; 6863 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6864 "-v128:64-a:8:16-n32:64"); 6865 } 6866 return true; 6867 } 6868 6869 bool hasFeature(StringRef Feature) const override { 6870 return llvm::StringSwitch<bool>(Feature) 6871 .Case("systemz", true) 6872 .Case("htm", HasTransactionalExecution) 6873 .Case("vx", HasVector) 6874 .Default(false); 6875 } 6876 6877 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6878 switch (CC) { 6879 case CC_C: 6880 case CC_Swift: 6881 return CCCR_OK; 6882 default: 6883 return CCCR_Warning; 6884 } 6885 } 6886 6887 StringRef getABI() const override { 6888 if (HasVector) 6889 return "vector"; 6890 return ""; 6891 } 6892 6893 bool useFloat128ManglingForLongDouble() const override { 6894 return true; 6895 } 6896 }; 6897 6898 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6899 #define BUILTIN(ID, TYPE, ATTRS) \ 6900 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6901 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6902 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6903 #include "clang/Basic/BuiltinsSystemZ.def" 6904 }; 6905 6906 const char *const SystemZTargetInfo::GCCRegNames[] = { 6907 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6908 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6909 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6910 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6911 }; 6912 6913 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6914 return llvm::makeArrayRef(GCCRegNames); 6915 } 6916 6917 bool SystemZTargetInfo:: 6918 validateAsmConstraint(const char *&Name, 6919 TargetInfo::ConstraintInfo &Info) const { 6920 switch (*Name) { 6921 default: 6922 return false; 6923 6924 case 'a': // Address register 6925 case 'd': // Data register (equivalent to 'r') 6926 case 'f': // Floating-point register 6927 Info.setAllowsRegister(); 6928 return true; 6929 6930 case 'I': // Unsigned 8-bit constant 6931 case 'J': // Unsigned 12-bit constant 6932 case 'K': // Signed 16-bit constant 6933 case 'L': // Signed 20-bit displacement (on all targets we support) 6934 case 'M': // 0x7fffffff 6935 return true; 6936 6937 case 'Q': // Memory with base and unsigned 12-bit displacement 6938 case 'R': // Likewise, plus an index 6939 case 'S': // Memory with base and signed 20-bit displacement 6940 case 'T': // Likewise, plus an index 6941 Info.setAllowsMemory(); 6942 return true; 6943 } 6944 } 6945 6946 class MSP430TargetInfo : public TargetInfo { 6947 static const char *const GCCRegNames[]; 6948 6949 public: 6950 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6951 : TargetInfo(Triple) { 6952 BigEndian = false; 6953 TLSSupported = false; 6954 IntWidth = 16; 6955 IntAlign = 16; 6956 LongWidth = 32; 6957 LongLongWidth = 64; 6958 LongAlign = LongLongAlign = 16; 6959 PointerWidth = 16; 6960 PointerAlign = 16; 6961 SuitableAlign = 16; 6962 SizeType = UnsignedInt; 6963 IntMaxType = SignedLongLong; 6964 IntPtrType = SignedInt; 6965 PtrDiffType = SignedInt; 6966 SigAtomicType = SignedLong; 6967 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6968 } 6969 void getTargetDefines(const LangOptions &Opts, 6970 MacroBuilder &Builder) const override { 6971 Builder.defineMacro("MSP430"); 6972 Builder.defineMacro("__MSP430__"); 6973 // FIXME: defines for different 'flavours' of MCU 6974 } 6975 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6976 // FIXME: Implement. 6977 return None; 6978 } 6979 bool hasFeature(StringRef Feature) const override { 6980 return Feature == "msp430"; 6981 } 6982 ArrayRef<const char *> getGCCRegNames() const override; 6983 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6984 // No aliases. 6985 return None; 6986 } 6987 bool validateAsmConstraint(const char *&Name, 6988 TargetInfo::ConstraintInfo &info) const override { 6989 // FIXME: implement 6990 switch (*Name) { 6991 case 'K': // the constant 1 6992 case 'L': // constant -1^20 .. 1^19 6993 case 'M': // constant 1-4: 6994 return true; 6995 } 6996 // No target constraints for now. 6997 return false; 6998 } 6999 const char *getClobbers() const override { 7000 // FIXME: Is this really right? 7001 return ""; 7002 } 7003 BuiltinVaListKind getBuiltinVaListKind() const override { 7004 // FIXME: implement 7005 return TargetInfo::CharPtrBuiltinVaList; 7006 } 7007 }; 7008 7009 const char *const MSP430TargetInfo::GCCRegNames[] = { 7010 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7011 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7012 7013 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7014 return llvm::makeArrayRef(GCCRegNames); 7015 } 7016 7017 // LLVM and Clang cannot be used directly to output native binaries for 7018 // target, but is used to compile C code to llvm bitcode with correct 7019 // type and alignment information. 7020 // 7021 // TCE uses the llvm bitcode as input and uses it for generating customized 7022 // target processor and program binary. TCE co-design environment is 7023 // publicly available in http://tce.cs.tut.fi 7024 7025 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7026 3, // opencl_global 7027 4, // opencl_local 7028 5, // opencl_constant 7029 // FIXME: generic has to be added to the target 7030 0, // opencl_generic 7031 0, // cuda_device 7032 0, // cuda_constant 7033 0 // cuda_shared 7034 }; 7035 7036 class TCETargetInfo : public TargetInfo { 7037 public: 7038 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7039 : TargetInfo(Triple) { 7040 TLSSupported = false; 7041 IntWidth = 32; 7042 LongWidth = LongLongWidth = 32; 7043 PointerWidth = 32; 7044 IntAlign = 32; 7045 LongAlign = LongLongAlign = 32; 7046 PointerAlign = 32; 7047 SuitableAlign = 32; 7048 SizeType = UnsignedInt; 7049 IntMaxType = SignedLong; 7050 IntPtrType = SignedInt; 7051 PtrDiffType = SignedInt; 7052 FloatWidth = 32; 7053 FloatAlign = 32; 7054 DoubleWidth = 32; 7055 DoubleAlign = 32; 7056 LongDoubleWidth = 32; 7057 LongDoubleAlign = 32; 7058 FloatFormat = &llvm::APFloat::IEEEsingle; 7059 DoubleFormat = &llvm::APFloat::IEEEsingle; 7060 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 7061 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 7062 "-f64:32-v64:32-v128:32-a:0:32-n32"); 7063 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7064 UseAddrSpaceMapMangling = true; 7065 } 7066 7067 void getTargetDefines(const LangOptions &Opts, 7068 MacroBuilder &Builder) const override { 7069 DefineStd(Builder, "tce", Opts); 7070 Builder.defineMacro("__TCE__"); 7071 Builder.defineMacro("__TCE_V1__"); 7072 } 7073 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7074 7075 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7076 const char *getClobbers() const override { return ""; } 7077 BuiltinVaListKind getBuiltinVaListKind() const override { 7078 return TargetInfo::VoidPtrBuiltinVaList; 7079 } 7080 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7081 bool validateAsmConstraint(const char *&Name, 7082 TargetInfo::ConstraintInfo &info) const override { 7083 return true; 7084 } 7085 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7086 return None; 7087 } 7088 }; 7089 7090 class BPFTargetInfo : public TargetInfo { 7091 public: 7092 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7093 : TargetInfo(Triple) { 7094 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7095 SizeType = UnsignedLong; 7096 PtrDiffType = SignedLong; 7097 IntPtrType = SignedLong; 7098 IntMaxType = SignedLong; 7099 Int64Type = SignedLong; 7100 RegParmMax = 5; 7101 if (Triple.getArch() == llvm::Triple::bpfeb) { 7102 BigEndian = true; 7103 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7104 } else { 7105 BigEndian = false; 7106 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7107 } 7108 MaxAtomicPromoteWidth = 64; 7109 MaxAtomicInlineWidth = 64; 7110 TLSSupported = false; 7111 } 7112 void getTargetDefines(const LangOptions &Opts, 7113 MacroBuilder &Builder) const override { 7114 DefineStd(Builder, "bpf", Opts); 7115 Builder.defineMacro("__BPF__"); 7116 } 7117 bool hasFeature(StringRef Feature) const override { 7118 return Feature == "bpf"; 7119 } 7120 7121 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7122 const char *getClobbers() const override { 7123 return ""; 7124 } 7125 BuiltinVaListKind getBuiltinVaListKind() const override { 7126 return TargetInfo::VoidPtrBuiltinVaList; 7127 } 7128 ArrayRef<const char *> getGCCRegNames() const override { 7129 return None; 7130 } 7131 bool validateAsmConstraint(const char *&Name, 7132 TargetInfo::ConstraintInfo &info) const override { 7133 return true; 7134 } 7135 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7136 return None; 7137 } 7138 }; 7139 7140 class MipsTargetInfo : public TargetInfo { 7141 void setDataLayout() { 7142 StringRef Layout; 7143 7144 if (ABI == "o32") 7145 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7146 else if (ABI == "n32") 7147 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7148 else if (ABI == "n64") 7149 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7150 else 7151 llvm_unreachable("Invalid ABI"); 7152 7153 if (BigEndian) 7154 resetDataLayout(("E-" + Layout).str()); 7155 else 7156 resetDataLayout(("e-" + Layout).str()); 7157 } 7158 7159 7160 static const Builtin::Info BuiltinInfo[]; 7161 std::string CPU; 7162 bool IsMips16; 7163 bool IsMicromips; 7164 bool IsNan2008; 7165 bool IsSingleFloat; 7166 enum MipsFloatABI { 7167 HardFloat, SoftFloat 7168 } FloatABI; 7169 enum DspRevEnum { 7170 NoDSP, DSP1, DSP2 7171 } DspRev; 7172 bool HasMSA; 7173 7174 protected: 7175 bool HasFP64; 7176 std::string ABI; 7177 7178 public: 7179 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7180 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7181 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7182 DspRev(NoDSP), HasMSA(false), HasFP64(false) { 7183 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7184 BigEndian = getTriple().getArch() == llvm::Triple::mips || 7185 getTriple().getArch() == llvm::Triple::mips64; 7186 7187 setABI((getTriple().getArch() == llvm::Triple::mips || 7188 getTriple().getArch() == llvm::Triple::mipsel) 7189 ? "o32" 7190 : "n64"); 7191 7192 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7193 } 7194 7195 bool isNaN2008Default() const { 7196 return CPU == "mips32r6" || CPU == "mips64r6"; 7197 } 7198 7199 bool isFP64Default() const { 7200 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7201 } 7202 7203 bool isNan2008() const override { 7204 return IsNan2008; 7205 } 7206 7207 bool processorSupportsGPR64() const { 7208 return llvm::StringSwitch<bool>(CPU) 7209 .Case("mips3", true) 7210 .Case("mips4", true) 7211 .Case("mips5", true) 7212 .Case("mips64", true) 7213 .Case("mips64r2", true) 7214 .Case("mips64r3", true) 7215 .Case("mips64r5", true) 7216 .Case("mips64r6", true) 7217 .Case("octeon", true) 7218 .Default(false); 7219 return false; 7220 } 7221 7222 StringRef getABI() const override { return ABI; } 7223 bool setABI(const std::string &Name) override { 7224 if (Name == "o32") { 7225 setO32ABITypes(); 7226 ABI = Name; 7227 return true; 7228 } 7229 7230 if (Name == "n32") { 7231 setN32ABITypes(); 7232 ABI = Name; 7233 return true; 7234 } 7235 if (Name == "n64") { 7236 setN64ABITypes(); 7237 ABI = Name; 7238 return true; 7239 } 7240 return false; 7241 } 7242 7243 void setO32ABITypes() { 7244 Int64Type = SignedLongLong; 7245 IntMaxType = Int64Type; 7246 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7247 LongDoubleWidth = LongDoubleAlign = 64; 7248 LongWidth = LongAlign = 32; 7249 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7250 PointerWidth = PointerAlign = 32; 7251 PtrDiffType = SignedInt; 7252 SizeType = UnsignedInt; 7253 SuitableAlign = 64; 7254 } 7255 7256 void setN32N64ABITypes() { 7257 LongDoubleWidth = LongDoubleAlign = 128; 7258 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7259 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7260 LongDoubleWidth = LongDoubleAlign = 64; 7261 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7262 } 7263 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7264 SuitableAlign = 128; 7265 } 7266 7267 void setN64ABITypes() { 7268 setN32N64ABITypes(); 7269 Int64Type = SignedLong; 7270 IntMaxType = Int64Type; 7271 LongWidth = LongAlign = 64; 7272 PointerWidth = PointerAlign = 64; 7273 PtrDiffType = SignedLong; 7274 SizeType = UnsignedLong; 7275 } 7276 7277 void setN32ABITypes() { 7278 setN32N64ABITypes(); 7279 Int64Type = SignedLongLong; 7280 IntMaxType = Int64Type; 7281 LongWidth = LongAlign = 32; 7282 PointerWidth = PointerAlign = 32; 7283 PtrDiffType = SignedInt; 7284 SizeType = UnsignedInt; 7285 } 7286 7287 bool setCPU(const std::string &Name) override { 7288 CPU = Name; 7289 return llvm::StringSwitch<bool>(Name) 7290 .Case("mips1", true) 7291 .Case("mips2", true) 7292 .Case("mips3", true) 7293 .Case("mips4", true) 7294 .Case("mips5", true) 7295 .Case("mips32", true) 7296 .Case("mips32r2", true) 7297 .Case("mips32r3", true) 7298 .Case("mips32r5", true) 7299 .Case("mips32r6", true) 7300 .Case("mips64", true) 7301 .Case("mips64r2", true) 7302 .Case("mips64r3", true) 7303 .Case("mips64r5", true) 7304 .Case("mips64r6", true) 7305 .Case("octeon", true) 7306 .Case("p5600", true) 7307 .Default(false); 7308 } 7309 const std::string& getCPU() const { return CPU; } 7310 bool 7311 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7312 StringRef CPU, 7313 const std::vector<std::string> &FeaturesVec) const override { 7314 if (CPU.empty()) 7315 CPU = getCPU(); 7316 if (CPU == "octeon") 7317 Features["mips64r2"] = Features["cnmips"] = true; 7318 else 7319 Features[CPU] = true; 7320 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7321 } 7322 7323 void getTargetDefines(const LangOptions &Opts, 7324 MacroBuilder &Builder) const override { 7325 if (BigEndian) { 7326 DefineStd(Builder, "MIPSEB", Opts); 7327 Builder.defineMacro("_MIPSEB"); 7328 } else { 7329 DefineStd(Builder, "MIPSEL", Opts); 7330 Builder.defineMacro("_MIPSEL"); 7331 } 7332 7333 Builder.defineMacro("__mips__"); 7334 Builder.defineMacro("_mips"); 7335 if (Opts.GNUMode) 7336 Builder.defineMacro("mips"); 7337 7338 if (ABI == "o32") { 7339 Builder.defineMacro("__mips", "32"); 7340 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7341 } else { 7342 Builder.defineMacro("__mips", "64"); 7343 Builder.defineMacro("__mips64"); 7344 Builder.defineMacro("__mips64__"); 7345 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7346 } 7347 7348 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7349 .Cases("mips32", "mips64", "1") 7350 .Cases("mips32r2", "mips64r2", "2") 7351 .Cases("mips32r3", "mips64r3", "3") 7352 .Cases("mips32r5", "mips64r5", "5") 7353 .Cases("mips32r6", "mips64r6", "6") 7354 .Default(""); 7355 if (!ISARev.empty()) 7356 Builder.defineMacro("__mips_isa_rev", ISARev); 7357 7358 if (ABI == "o32") { 7359 Builder.defineMacro("__mips_o32"); 7360 Builder.defineMacro("_ABIO32", "1"); 7361 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7362 } else if (ABI == "n32") { 7363 Builder.defineMacro("__mips_n32"); 7364 Builder.defineMacro("_ABIN32", "2"); 7365 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7366 } else if (ABI == "n64") { 7367 Builder.defineMacro("__mips_n64"); 7368 Builder.defineMacro("_ABI64", "3"); 7369 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7370 } else 7371 llvm_unreachable("Invalid ABI."); 7372 7373 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7374 7375 switch (FloatABI) { 7376 case HardFloat: 7377 Builder.defineMacro("__mips_hard_float", Twine(1)); 7378 break; 7379 case SoftFloat: 7380 Builder.defineMacro("__mips_soft_float", Twine(1)); 7381 break; 7382 } 7383 7384 if (IsSingleFloat) 7385 Builder.defineMacro("__mips_single_float", Twine(1)); 7386 7387 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7388 Builder.defineMacro("_MIPS_FPSET", 7389 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7390 7391 if (IsMips16) 7392 Builder.defineMacro("__mips16", Twine(1)); 7393 7394 if (IsMicromips) 7395 Builder.defineMacro("__mips_micromips", Twine(1)); 7396 7397 if (IsNan2008) 7398 Builder.defineMacro("__mips_nan2008", Twine(1)); 7399 7400 switch (DspRev) { 7401 default: 7402 break; 7403 case DSP1: 7404 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7405 Builder.defineMacro("__mips_dsp", Twine(1)); 7406 break; 7407 case DSP2: 7408 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7409 Builder.defineMacro("__mips_dspr2", Twine(1)); 7410 Builder.defineMacro("__mips_dsp", Twine(1)); 7411 break; 7412 } 7413 7414 if (HasMSA) 7415 Builder.defineMacro("__mips_msa", Twine(1)); 7416 7417 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7418 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7419 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7420 7421 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7422 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7423 7424 // These shouldn't be defined for MIPS-I but there's no need to check 7425 // for that since MIPS-I isn't supported. 7426 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7427 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7428 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7429 7430 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7431 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7432 // the instructions exist but using them violates the ABI since they 7433 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7434 if (ABI == "n32" || ABI == "n64") 7435 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7436 } 7437 7438 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7439 return llvm::makeArrayRef(BuiltinInfo, 7440 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7441 } 7442 bool hasFeature(StringRef Feature) const override { 7443 return llvm::StringSwitch<bool>(Feature) 7444 .Case("mips", true) 7445 .Case("fp64", HasFP64) 7446 .Default(false); 7447 } 7448 BuiltinVaListKind getBuiltinVaListKind() const override { 7449 return TargetInfo::VoidPtrBuiltinVaList; 7450 } 7451 ArrayRef<const char *> getGCCRegNames() const override { 7452 static const char *const GCCRegNames[] = { 7453 // CPU register names 7454 // Must match second column of GCCRegAliases 7455 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7456 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7457 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7458 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7459 // Floating point register names 7460 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7461 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7462 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7463 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7464 // Hi/lo and condition register names 7465 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7466 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7467 "$ac3hi","$ac3lo", 7468 // MSA register names 7469 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7470 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7471 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7472 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7473 // MSA control register names 7474 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7475 "$msarequest", "$msamap", "$msaunmap" 7476 }; 7477 return llvm::makeArrayRef(GCCRegNames); 7478 } 7479 bool validateAsmConstraint(const char *&Name, 7480 TargetInfo::ConstraintInfo &Info) const override { 7481 switch (*Name) { 7482 default: 7483 return false; 7484 case 'r': // CPU registers. 7485 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7486 case 'y': // Equivalent to "r", backward compatibility only. 7487 case 'f': // floating-point registers. 7488 case 'c': // $25 for indirect jumps 7489 case 'l': // lo register 7490 case 'x': // hilo register pair 7491 Info.setAllowsRegister(); 7492 return true; 7493 case 'I': // Signed 16-bit constant 7494 case 'J': // Integer 0 7495 case 'K': // Unsigned 16-bit constant 7496 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7497 case 'M': // Constants not loadable via lui, addiu, or ori 7498 case 'N': // Constant -1 to -65535 7499 case 'O': // A signed 15-bit constant 7500 case 'P': // A constant between 1 go 65535 7501 return true; 7502 case 'R': // An address that can be used in a non-macro load or store 7503 Info.setAllowsMemory(); 7504 return true; 7505 case 'Z': 7506 if (Name[1] == 'C') { // An address usable by ll, and sc. 7507 Info.setAllowsMemory(); 7508 Name++; // Skip over 'Z'. 7509 return true; 7510 } 7511 return false; 7512 } 7513 } 7514 7515 std::string convertConstraint(const char *&Constraint) const override { 7516 std::string R; 7517 switch (*Constraint) { 7518 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7519 if (Constraint[1] == 'C') { 7520 R = std::string("^") + std::string(Constraint, 2); 7521 Constraint++; 7522 return R; 7523 } 7524 break; 7525 } 7526 return TargetInfo::convertConstraint(Constraint); 7527 } 7528 7529 const char *getClobbers() const override { 7530 // In GCC, $1 is not widely used in generated code (it's used only in a few 7531 // specific situations), so there is no real need for users to add it to 7532 // the clobbers list if they want to use it in their inline assembly code. 7533 // 7534 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7535 // code generation, so using it in inline assembly without adding it to the 7536 // clobbers list can cause conflicts between the inline assembly code and 7537 // the surrounding generated code. 7538 // 7539 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7540 // operands, which will conflict with the ".set at" assembler option (which 7541 // we use only for inline assembly, in order to maintain compatibility with 7542 // GCC) and will also conflict with the user's usage of $1. 7543 // 7544 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7545 // register for generated code is to automatically clobber $1 for all inline 7546 // assembly code. 7547 // 7548 // FIXME: We should automatically clobber $1 only for inline assembly code 7549 // which actually uses it. This would allow LLVM to use $1 for inline 7550 // assembly operands if the user's assembly code doesn't use it. 7551 return "~{$1}"; 7552 } 7553 7554 bool handleTargetFeatures(std::vector<std::string> &Features, 7555 DiagnosticsEngine &Diags) override { 7556 IsMips16 = false; 7557 IsMicromips = false; 7558 IsNan2008 = isNaN2008Default(); 7559 IsSingleFloat = false; 7560 FloatABI = HardFloat; 7561 DspRev = NoDSP; 7562 HasFP64 = isFP64Default(); 7563 7564 for (const auto &Feature : Features) { 7565 if (Feature == "+single-float") 7566 IsSingleFloat = true; 7567 else if (Feature == "+soft-float") 7568 FloatABI = SoftFloat; 7569 else if (Feature == "+mips16") 7570 IsMips16 = true; 7571 else if (Feature == "+micromips") 7572 IsMicromips = true; 7573 else if (Feature == "+dsp") 7574 DspRev = std::max(DspRev, DSP1); 7575 else if (Feature == "+dspr2") 7576 DspRev = std::max(DspRev, DSP2); 7577 else if (Feature == "+msa") 7578 HasMSA = true; 7579 else if (Feature == "+fp64") 7580 HasFP64 = true; 7581 else if (Feature == "-fp64") 7582 HasFP64 = false; 7583 else if (Feature == "+nan2008") 7584 IsNan2008 = true; 7585 else if (Feature == "-nan2008") 7586 IsNan2008 = false; 7587 } 7588 7589 setDataLayout(); 7590 7591 return true; 7592 } 7593 7594 int getEHDataRegisterNumber(unsigned RegNo) const override { 7595 if (RegNo == 0) return 4; 7596 if (RegNo == 1) return 5; 7597 return -1; 7598 } 7599 7600 bool isCLZForZeroUndef() const override { return false; } 7601 7602 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7603 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7604 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7605 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7606 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7607 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7608 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7609 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7610 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7611 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7612 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7613 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7614 {{"ra"}, "$31"}}; 7615 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7616 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7617 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7618 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7619 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7620 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7621 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7622 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7623 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7624 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7625 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7626 {{"ra"}, "$31"}}; 7627 if (ABI == "o32") 7628 return llvm::makeArrayRef(O32RegAliases); 7629 return llvm::makeArrayRef(NewABIRegAliases); 7630 } 7631 7632 bool hasInt128Type() const override { 7633 return ABI == "n32" || ABI == "n64"; 7634 } 7635 7636 bool validateTarget(DiagnosticsEngine &Diags) const override { 7637 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7638 // this yet. It's better to fail here than on the backend assertion. 7639 if (processorSupportsGPR64() && ABI == "o32") { 7640 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7641 return false; 7642 } 7643 7644 // 64-bit ABI's require 64-bit CPU's. 7645 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 7646 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7647 return false; 7648 } 7649 7650 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 7651 // can't handle this yet. It's better to fail here than on the 7652 // backend assertion. 7653 if ((getTriple().getArch() == llvm::Triple::mips64 || 7654 getTriple().getArch() == llvm::Triple::mips64el) && 7655 ABI == "o32") { 7656 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7657 << ABI << getTriple().str(); 7658 return false; 7659 } 7660 7661 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 7662 // can't handle this yet. It's better to fail here than on the 7663 // backend assertion. 7664 if ((getTriple().getArch() == llvm::Triple::mips || 7665 getTriple().getArch() == llvm::Triple::mipsel) && 7666 (ABI == "n32" || ABI == "n64")) { 7667 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7668 << ABI << getTriple().str(); 7669 return false; 7670 } 7671 7672 return true; 7673 } 7674 }; 7675 7676 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7677 #define BUILTIN(ID, TYPE, ATTRS) \ 7678 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7679 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7680 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7681 #include "clang/Basic/BuiltinsMips.def" 7682 }; 7683 7684 class PNaClTargetInfo : public TargetInfo { 7685 public: 7686 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7687 : TargetInfo(Triple) { 7688 BigEndian = false; 7689 this->LongAlign = 32; 7690 this->LongWidth = 32; 7691 this->PointerAlign = 32; 7692 this->PointerWidth = 32; 7693 this->IntMaxType = TargetInfo::SignedLongLong; 7694 this->Int64Type = TargetInfo::SignedLongLong; 7695 this->DoubleAlign = 64; 7696 this->LongDoubleWidth = 64; 7697 this->LongDoubleAlign = 64; 7698 this->SizeType = TargetInfo::UnsignedInt; 7699 this->PtrDiffType = TargetInfo::SignedInt; 7700 this->IntPtrType = TargetInfo::SignedInt; 7701 this->RegParmMax = 0; // Disallow regparm 7702 } 7703 7704 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7705 Builder.defineMacro("__le32__"); 7706 Builder.defineMacro("__pnacl__"); 7707 } 7708 void getTargetDefines(const LangOptions &Opts, 7709 MacroBuilder &Builder) const override { 7710 getArchDefines(Opts, Builder); 7711 } 7712 bool hasFeature(StringRef Feature) const override { 7713 return Feature == "pnacl"; 7714 } 7715 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7716 BuiltinVaListKind getBuiltinVaListKind() const override { 7717 return TargetInfo::PNaClABIBuiltinVaList; 7718 } 7719 ArrayRef<const char *> getGCCRegNames() const override; 7720 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7721 bool validateAsmConstraint(const char *&Name, 7722 TargetInfo::ConstraintInfo &Info) const override { 7723 return false; 7724 } 7725 7726 const char *getClobbers() const override { 7727 return ""; 7728 } 7729 }; 7730 7731 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7732 return None; 7733 } 7734 7735 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7736 return None; 7737 } 7738 7739 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7740 class NaClMips32TargetInfo : public MipsTargetInfo { 7741 public: 7742 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7743 : MipsTargetInfo(Triple, Opts) {} 7744 7745 BuiltinVaListKind getBuiltinVaListKind() const override { 7746 return TargetInfo::PNaClABIBuiltinVaList; 7747 } 7748 }; 7749 7750 class Le64TargetInfo : public TargetInfo { 7751 static const Builtin::Info BuiltinInfo[]; 7752 7753 public: 7754 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7755 : TargetInfo(Triple) { 7756 BigEndian = false; 7757 NoAsmVariants = true; 7758 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7759 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7760 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7761 } 7762 7763 void getTargetDefines(const LangOptions &Opts, 7764 MacroBuilder &Builder) const override { 7765 DefineStd(Builder, "unix", Opts); 7766 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7767 Builder.defineMacro("__ELF__"); 7768 } 7769 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7770 return llvm::makeArrayRef(BuiltinInfo, 7771 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7772 } 7773 BuiltinVaListKind getBuiltinVaListKind() const override { 7774 return TargetInfo::PNaClABIBuiltinVaList; 7775 } 7776 const char *getClobbers() const override { return ""; } 7777 ArrayRef<const char *> getGCCRegNames() const override { 7778 return None; 7779 } 7780 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7781 return None; 7782 } 7783 bool validateAsmConstraint(const char *&Name, 7784 TargetInfo::ConstraintInfo &Info) const override { 7785 return false; 7786 } 7787 7788 bool hasProtectedVisibility() const override { return false; } 7789 }; 7790 7791 class WebAssemblyTargetInfo : public TargetInfo { 7792 static const Builtin::Info BuiltinInfo[]; 7793 7794 enum SIMDEnum { 7795 NoSIMD, 7796 SIMD128, 7797 } SIMDLevel; 7798 7799 public: 7800 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7801 : TargetInfo(T), SIMDLevel(NoSIMD) { 7802 BigEndian = false; 7803 NoAsmVariants = true; 7804 SuitableAlign = 128; 7805 LargeArrayMinWidth = 128; 7806 LargeArrayAlign = 128; 7807 SimdDefaultAlign = 128; 7808 SigAtomicType = SignedLong; 7809 LongDoubleWidth = LongDoubleAlign = 128; 7810 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7811 } 7812 7813 protected: 7814 void getTargetDefines(const LangOptions &Opts, 7815 MacroBuilder &Builder) const override { 7816 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7817 if (SIMDLevel >= SIMD128) 7818 Builder.defineMacro("__wasm_simd128__"); 7819 } 7820 7821 private: 7822 bool 7823 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7824 StringRef CPU, 7825 const std::vector<std::string> &FeaturesVec) const override { 7826 if (CPU == "bleeding-edge") 7827 Features["simd128"] = true; 7828 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7829 } 7830 bool hasFeature(StringRef Feature) const final { 7831 return llvm::StringSwitch<bool>(Feature) 7832 .Case("simd128", SIMDLevel >= SIMD128) 7833 .Default(false); 7834 } 7835 bool handleTargetFeatures(std::vector<std::string> &Features, 7836 DiagnosticsEngine &Diags) final { 7837 for (const auto &Feature : Features) { 7838 if (Feature == "+simd128") { 7839 SIMDLevel = std::max(SIMDLevel, SIMD128); 7840 continue; 7841 } 7842 if (Feature == "-simd128") { 7843 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7844 continue; 7845 } 7846 7847 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7848 << "-target-feature"; 7849 return false; 7850 } 7851 return true; 7852 } 7853 bool setCPU(const std::string &Name) final { 7854 return llvm::StringSwitch<bool>(Name) 7855 .Case("mvp", true) 7856 .Case("bleeding-edge", true) 7857 .Case("generic", true) 7858 .Default(false); 7859 } 7860 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7861 return llvm::makeArrayRef(BuiltinInfo, 7862 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7863 } 7864 BuiltinVaListKind getBuiltinVaListKind() const final { 7865 return VoidPtrBuiltinVaList; 7866 } 7867 ArrayRef<const char *> getGCCRegNames() const final { 7868 return None; 7869 } 7870 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7871 return None; 7872 } 7873 bool 7874 validateAsmConstraint(const char *&Name, 7875 TargetInfo::ConstraintInfo &Info) const final { 7876 return false; 7877 } 7878 const char *getClobbers() const final { return ""; } 7879 bool isCLZForZeroUndef() const final { return false; } 7880 bool hasInt128Type() const final { return true; } 7881 IntType getIntTypeByWidth(unsigned BitWidth, 7882 bool IsSigned) const final { 7883 // WebAssembly prefers long long for explicitly 64-bit integers. 7884 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7885 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7886 } 7887 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7888 bool IsSigned) const final { 7889 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7890 return BitWidth == 64 7891 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7892 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7893 } 7894 }; 7895 7896 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7897 #define BUILTIN(ID, TYPE, ATTRS) \ 7898 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7899 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7900 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7901 #include "clang/Basic/BuiltinsWebAssembly.def" 7902 }; 7903 7904 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7905 public: 7906 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 7907 const TargetOptions &Opts) 7908 : WebAssemblyTargetInfo(T, Opts) { 7909 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7910 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7911 } 7912 7913 protected: 7914 void getTargetDefines(const LangOptions &Opts, 7915 MacroBuilder &Builder) const override { 7916 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7917 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7918 } 7919 }; 7920 7921 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7922 public: 7923 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 7924 const TargetOptions &Opts) 7925 : WebAssemblyTargetInfo(T, Opts) { 7926 LongAlign = LongWidth = 64; 7927 PointerAlign = PointerWidth = 64; 7928 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7929 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7930 } 7931 7932 protected: 7933 void getTargetDefines(const LangOptions &Opts, 7934 MacroBuilder &Builder) const override { 7935 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7936 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7937 } 7938 }; 7939 7940 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7941 #define BUILTIN(ID, TYPE, ATTRS) \ 7942 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7943 #include "clang/Basic/BuiltinsLe64.def" 7944 }; 7945 7946 static const unsigned SPIRAddrSpaceMap[] = { 7947 1, // opencl_global 7948 3, // opencl_local 7949 2, // opencl_constant 7950 4, // opencl_generic 7951 0, // cuda_device 7952 0, // cuda_constant 7953 0 // cuda_shared 7954 }; 7955 class SPIRTargetInfo : public TargetInfo { 7956 public: 7957 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7958 : TargetInfo(Triple) { 7959 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7960 "SPIR target must use unknown OS"); 7961 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7962 "SPIR target must use unknown environment type"); 7963 BigEndian = false; 7964 TLSSupported = false; 7965 LongWidth = LongAlign = 64; 7966 AddrSpaceMap = &SPIRAddrSpaceMap; 7967 UseAddrSpaceMapMangling = true; 7968 // Define available target features 7969 // These must be defined in sorted order! 7970 NoAsmVariants = true; 7971 } 7972 void getTargetDefines(const LangOptions &Opts, 7973 MacroBuilder &Builder) const override { 7974 DefineStd(Builder, "SPIR", Opts); 7975 } 7976 bool hasFeature(StringRef Feature) const override { 7977 return Feature == "spir"; 7978 } 7979 7980 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7981 const char *getClobbers() const override { return ""; } 7982 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7983 bool validateAsmConstraint(const char *&Name, 7984 TargetInfo::ConstraintInfo &info) const override { 7985 return true; 7986 } 7987 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7988 return None; 7989 } 7990 BuiltinVaListKind getBuiltinVaListKind() const override { 7991 return TargetInfo::VoidPtrBuiltinVaList; 7992 } 7993 7994 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7995 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 7996 : CCCR_Warning; 7997 } 7998 7999 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8000 return CC_SpirFunction; 8001 } 8002 8003 void setSupportedOpenCLOpts() override { 8004 // Assume all OpenCL extensions and optional core features are supported 8005 // for SPIR since it is a generic target. 8006 getSupportedOpenCLOpts().setAll(); 8007 } 8008 }; 8009 8010 class SPIR32TargetInfo : public SPIRTargetInfo { 8011 public: 8012 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8013 : SPIRTargetInfo(Triple, Opts) { 8014 PointerWidth = PointerAlign = 32; 8015 SizeType = TargetInfo::UnsignedInt; 8016 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8017 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8018 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8019 } 8020 void getTargetDefines(const LangOptions &Opts, 8021 MacroBuilder &Builder) const override { 8022 DefineStd(Builder, "SPIR32", Opts); 8023 } 8024 }; 8025 8026 class SPIR64TargetInfo : public SPIRTargetInfo { 8027 public: 8028 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8029 : SPIRTargetInfo(Triple, Opts) { 8030 PointerWidth = PointerAlign = 64; 8031 SizeType = TargetInfo::UnsignedLong; 8032 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8033 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8034 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8035 } 8036 void getTargetDefines(const LangOptions &Opts, 8037 MacroBuilder &Builder) const override { 8038 DefineStd(Builder, "SPIR64", Opts); 8039 } 8040 }; 8041 8042 class XCoreTargetInfo : public TargetInfo { 8043 static const Builtin::Info BuiltinInfo[]; 8044 public: 8045 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8046 : TargetInfo(Triple) { 8047 BigEndian = false; 8048 NoAsmVariants = true; 8049 LongLongAlign = 32; 8050 SuitableAlign = 32; 8051 DoubleAlign = LongDoubleAlign = 32; 8052 SizeType = UnsignedInt; 8053 PtrDiffType = SignedInt; 8054 IntPtrType = SignedInt; 8055 WCharType = UnsignedChar; 8056 WIntType = UnsignedInt; 8057 UseZeroLengthBitfieldAlignment = true; 8058 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8059 "-f64:32-a:0:32-n32"); 8060 } 8061 void getTargetDefines(const LangOptions &Opts, 8062 MacroBuilder &Builder) const override { 8063 Builder.defineMacro("__XS1B__"); 8064 } 8065 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8066 return llvm::makeArrayRef(BuiltinInfo, 8067 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8068 } 8069 BuiltinVaListKind getBuiltinVaListKind() const override { 8070 return TargetInfo::VoidPtrBuiltinVaList; 8071 } 8072 const char *getClobbers() const override { 8073 return ""; 8074 } 8075 ArrayRef<const char *> getGCCRegNames() const override { 8076 static const char * const GCCRegNames[] = { 8077 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8078 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8079 }; 8080 return llvm::makeArrayRef(GCCRegNames); 8081 } 8082 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8083 return None; 8084 } 8085 bool validateAsmConstraint(const char *&Name, 8086 TargetInfo::ConstraintInfo &Info) const override { 8087 return false; 8088 } 8089 int getEHDataRegisterNumber(unsigned RegNo) const override { 8090 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8091 return (RegNo < 2)? RegNo : -1; 8092 } 8093 bool allowsLargerPreferedTypeAlignment() const override { 8094 return false; 8095 } 8096 }; 8097 8098 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8099 #define BUILTIN(ID, TYPE, ATTRS) \ 8100 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8101 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8102 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8103 #include "clang/Basic/BuiltinsXCore.def" 8104 }; 8105 8106 // x86_32 Android target 8107 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8108 public: 8109 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8110 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8111 SuitableAlign = 32; 8112 LongDoubleWidth = 64; 8113 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 8114 } 8115 }; 8116 8117 // x86_64 Android target 8118 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8119 public: 8120 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8121 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8122 LongDoubleFormat = &llvm::APFloat::IEEEquad; 8123 } 8124 8125 bool useFloat128ManglingForLongDouble() const override { 8126 return true; 8127 } 8128 }; 8129 8130 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8131 class RenderScript32TargetInfo : public ARMleTargetInfo { 8132 public: 8133 RenderScript32TargetInfo(const llvm::Triple &Triple, 8134 const TargetOptions &Opts) 8135 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8136 Triple.getOSName(), 8137 Triple.getEnvironmentName()), 8138 Opts) { 8139 IsRenderScriptTarget = true; 8140 LongWidth = LongAlign = 64; 8141 } 8142 void getTargetDefines(const LangOptions &Opts, 8143 MacroBuilder &Builder) const override { 8144 Builder.defineMacro("__RENDERSCRIPT__"); 8145 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8146 } 8147 }; 8148 8149 // 64-bit RenderScript is aarch64 8150 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8151 public: 8152 RenderScript64TargetInfo(const llvm::Triple &Triple, 8153 const TargetOptions &Opts) 8154 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8155 Triple.getOSName(), 8156 Triple.getEnvironmentName()), 8157 Opts) { 8158 IsRenderScriptTarget = true; 8159 } 8160 8161 void getTargetDefines(const LangOptions &Opts, 8162 MacroBuilder &Builder) const override { 8163 Builder.defineMacro("__RENDERSCRIPT__"); 8164 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8165 } 8166 }; 8167 8168 } // end anonymous namespace 8169 8170 //===----------------------------------------------------------------------===// 8171 // Driver code 8172 //===----------------------------------------------------------------------===// 8173 8174 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8175 const TargetOptions &Opts) { 8176 llvm::Triple::OSType os = Triple.getOS(); 8177 8178 switch (Triple.getArch()) { 8179 default: 8180 return nullptr; 8181 8182 case llvm::Triple::xcore: 8183 return new XCoreTargetInfo(Triple, Opts); 8184 8185 case llvm::Triple::hexagon: 8186 return new HexagonTargetInfo(Triple, Opts); 8187 8188 case llvm::Triple::lanai: 8189 return new LanaiTargetInfo(Triple, Opts); 8190 8191 case llvm::Triple::aarch64: 8192 if (Triple.isOSDarwin()) 8193 return new DarwinAArch64TargetInfo(Triple, Opts); 8194 8195 switch (os) { 8196 case llvm::Triple::CloudABI: 8197 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8198 case llvm::Triple::FreeBSD: 8199 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8200 case llvm::Triple::Linux: 8201 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8202 case llvm::Triple::NetBSD: 8203 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8204 default: 8205 return new AArch64leTargetInfo(Triple, Opts); 8206 } 8207 8208 case llvm::Triple::aarch64_be: 8209 switch (os) { 8210 case llvm::Triple::FreeBSD: 8211 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8212 case llvm::Triple::Linux: 8213 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8214 case llvm::Triple::NetBSD: 8215 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8216 default: 8217 return new AArch64beTargetInfo(Triple, Opts); 8218 } 8219 8220 case llvm::Triple::arm: 8221 case llvm::Triple::thumb: 8222 if (Triple.isOSBinFormatMachO()) 8223 return new DarwinARMTargetInfo(Triple, Opts); 8224 8225 switch (os) { 8226 case llvm::Triple::Linux: 8227 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8228 case llvm::Triple::FreeBSD: 8229 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8230 case llvm::Triple::NetBSD: 8231 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8232 case llvm::Triple::OpenBSD: 8233 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8234 case llvm::Triple::Bitrig: 8235 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8236 case llvm::Triple::RTEMS: 8237 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8238 case llvm::Triple::NaCl: 8239 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8240 case llvm::Triple::Win32: 8241 switch (Triple.getEnvironment()) { 8242 case llvm::Triple::Cygnus: 8243 return new CygwinARMTargetInfo(Triple, Opts); 8244 case llvm::Triple::GNU: 8245 return new MinGWARMTargetInfo(Triple, Opts); 8246 case llvm::Triple::Itanium: 8247 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8248 case llvm::Triple::MSVC: 8249 default: // Assume MSVC for unknown environments 8250 return new MicrosoftARMleTargetInfo(Triple, Opts); 8251 } 8252 default: 8253 return new ARMleTargetInfo(Triple, Opts); 8254 } 8255 8256 case llvm::Triple::armeb: 8257 case llvm::Triple::thumbeb: 8258 if (Triple.isOSDarwin()) 8259 return new DarwinARMTargetInfo(Triple, Opts); 8260 8261 switch (os) { 8262 case llvm::Triple::Linux: 8263 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8264 case llvm::Triple::FreeBSD: 8265 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8266 case llvm::Triple::NetBSD: 8267 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8268 case llvm::Triple::OpenBSD: 8269 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8270 case llvm::Triple::Bitrig: 8271 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8272 case llvm::Triple::RTEMS: 8273 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8274 case llvm::Triple::NaCl: 8275 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8276 default: 8277 return new ARMbeTargetInfo(Triple, Opts); 8278 } 8279 8280 case llvm::Triple::bpfeb: 8281 case llvm::Triple::bpfel: 8282 return new BPFTargetInfo(Triple, Opts); 8283 8284 case llvm::Triple::msp430: 8285 return new MSP430TargetInfo(Triple, Opts); 8286 8287 case llvm::Triple::mips: 8288 switch (os) { 8289 case llvm::Triple::Linux: 8290 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8291 case llvm::Triple::RTEMS: 8292 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8293 case llvm::Triple::FreeBSD: 8294 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8295 case llvm::Triple::NetBSD: 8296 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8297 default: 8298 return new MipsTargetInfo(Triple, Opts); 8299 } 8300 8301 case llvm::Triple::mipsel: 8302 switch (os) { 8303 case llvm::Triple::Linux: 8304 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8305 case llvm::Triple::RTEMS: 8306 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8307 case llvm::Triple::FreeBSD: 8308 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8309 case llvm::Triple::NetBSD: 8310 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8311 case llvm::Triple::NaCl: 8312 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 8313 default: 8314 return new MipsTargetInfo(Triple, Opts); 8315 } 8316 8317 case llvm::Triple::mips64: 8318 switch (os) { 8319 case llvm::Triple::Linux: 8320 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8321 case llvm::Triple::RTEMS: 8322 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8323 case llvm::Triple::FreeBSD: 8324 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8325 case llvm::Triple::NetBSD: 8326 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8327 case llvm::Triple::OpenBSD: 8328 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8329 default: 8330 return new MipsTargetInfo(Triple, Opts); 8331 } 8332 8333 case llvm::Triple::mips64el: 8334 switch (os) { 8335 case llvm::Triple::Linux: 8336 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8337 case llvm::Triple::RTEMS: 8338 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8339 case llvm::Triple::FreeBSD: 8340 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8341 case llvm::Triple::NetBSD: 8342 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8343 case llvm::Triple::OpenBSD: 8344 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8345 default: 8346 return new MipsTargetInfo(Triple, Opts); 8347 } 8348 8349 case llvm::Triple::le32: 8350 switch (os) { 8351 case llvm::Triple::NaCl: 8352 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8353 default: 8354 return nullptr; 8355 } 8356 8357 case llvm::Triple::le64: 8358 return new Le64TargetInfo(Triple, Opts); 8359 8360 case llvm::Triple::ppc: 8361 if (Triple.isOSDarwin()) 8362 return new DarwinPPC32TargetInfo(Triple, Opts); 8363 switch (os) { 8364 case llvm::Triple::Linux: 8365 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8366 case llvm::Triple::FreeBSD: 8367 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8368 case llvm::Triple::NetBSD: 8369 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8370 case llvm::Triple::OpenBSD: 8371 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8372 case llvm::Triple::RTEMS: 8373 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8374 default: 8375 return new PPC32TargetInfo(Triple, Opts); 8376 } 8377 8378 case llvm::Triple::ppc64: 8379 if (Triple.isOSDarwin()) 8380 return new DarwinPPC64TargetInfo(Triple, Opts); 8381 switch (os) { 8382 case llvm::Triple::Linux: 8383 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8384 case llvm::Triple::Lv2: 8385 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8386 case llvm::Triple::FreeBSD: 8387 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8388 case llvm::Triple::NetBSD: 8389 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8390 default: 8391 return new PPC64TargetInfo(Triple, Opts); 8392 } 8393 8394 case llvm::Triple::ppc64le: 8395 switch (os) { 8396 case llvm::Triple::Linux: 8397 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8398 case llvm::Triple::NetBSD: 8399 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8400 default: 8401 return new PPC64TargetInfo(Triple, Opts); 8402 } 8403 8404 case llvm::Triple::nvptx: 8405 return new NVPTX32TargetInfo(Triple, Opts); 8406 case llvm::Triple::nvptx64: 8407 return new NVPTX64TargetInfo(Triple, Opts); 8408 8409 case llvm::Triple::amdgcn: 8410 case llvm::Triple::r600: 8411 return new AMDGPUTargetInfo(Triple, Opts); 8412 8413 case llvm::Triple::sparc: 8414 switch (os) { 8415 case llvm::Triple::Linux: 8416 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8417 case llvm::Triple::Solaris: 8418 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8419 case llvm::Triple::NetBSD: 8420 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8421 case llvm::Triple::OpenBSD: 8422 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8423 case llvm::Triple::RTEMS: 8424 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8425 default: 8426 return new SparcV8TargetInfo(Triple, Opts); 8427 } 8428 8429 // The 'sparcel' architecture copies all the above cases except for Solaris. 8430 case llvm::Triple::sparcel: 8431 switch (os) { 8432 case llvm::Triple::Linux: 8433 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8434 case llvm::Triple::NetBSD: 8435 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8436 case llvm::Triple::OpenBSD: 8437 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8438 case llvm::Triple::RTEMS: 8439 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8440 default: 8441 return new SparcV8elTargetInfo(Triple, Opts); 8442 } 8443 8444 case llvm::Triple::sparcv9: 8445 switch (os) { 8446 case llvm::Triple::Linux: 8447 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8448 case llvm::Triple::Solaris: 8449 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8450 case llvm::Triple::NetBSD: 8451 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8452 case llvm::Triple::OpenBSD: 8453 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8454 case llvm::Triple::FreeBSD: 8455 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8456 default: 8457 return new SparcV9TargetInfo(Triple, Opts); 8458 } 8459 8460 case llvm::Triple::systemz: 8461 switch (os) { 8462 case llvm::Triple::Linux: 8463 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8464 default: 8465 return new SystemZTargetInfo(Triple, Opts); 8466 } 8467 8468 case llvm::Triple::tce: 8469 return new TCETargetInfo(Triple, Opts); 8470 8471 case llvm::Triple::x86: 8472 if (Triple.isOSDarwin()) 8473 return new DarwinI386TargetInfo(Triple, Opts); 8474 8475 switch (os) { 8476 case llvm::Triple::CloudABI: 8477 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8478 case llvm::Triple::Linux: { 8479 switch (Triple.getEnvironment()) { 8480 default: 8481 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8482 case llvm::Triple::Android: 8483 return new AndroidX86_32TargetInfo(Triple, Opts); 8484 } 8485 } 8486 case llvm::Triple::DragonFly: 8487 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8488 case llvm::Triple::NetBSD: 8489 return new NetBSDI386TargetInfo(Triple, Opts); 8490 case llvm::Triple::OpenBSD: 8491 return new OpenBSDI386TargetInfo(Triple, Opts); 8492 case llvm::Triple::Bitrig: 8493 return new BitrigI386TargetInfo(Triple, Opts); 8494 case llvm::Triple::FreeBSD: 8495 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8496 case llvm::Triple::KFreeBSD: 8497 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8498 case llvm::Triple::Minix: 8499 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8500 case llvm::Triple::Solaris: 8501 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8502 case llvm::Triple::Win32: { 8503 switch (Triple.getEnvironment()) { 8504 case llvm::Triple::Cygnus: 8505 return new CygwinX86_32TargetInfo(Triple, Opts); 8506 case llvm::Triple::GNU: 8507 return new MinGWX86_32TargetInfo(Triple, Opts); 8508 case llvm::Triple::Itanium: 8509 case llvm::Triple::MSVC: 8510 default: // Assume MSVC for unknown environments 8511 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8512 } 8513 } 8514 case llvm::Triple::Haiku: 8515 return new HaikuX86_32TargetInfo(Triple, Opts); 8516 case llvm::Triple::RTEMS: 8517 return new RTEMSX86_32TargetInfo(Triple, Opts); 8518 case llvm::Triple::NaCl: 8519 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8520 case llvm::Triple::ELFIAMCU: 8521 return new MCUX86_32TargetInfo(Triple, Opts); 8522 default: 8523 return new X86_32TargetInfo(Triple, Opts); 8524 } 8525 8526 case llvm::Triple::x86_64: 8527 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8528 return new DarwinX86_64TargetInfo(Triple, Opts); 8529 8530 switch (os) { 8531 case llvm::Triple::CloudABI: 8532 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8533 case llvm::Triple::Linux: { 8534 switch (Triple.getEnvironment()) { 8535 default: 8536 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8537 case llvm::Triple::Android: 8538 return new AndroidX86_64TargetInfo(Triple, Opts); 8539 } 8540 } 8541 case llvm::Triple::DragonFly: 8542 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8543 case llvm::Triple::NetBSD: 8544 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8545 case llvm::Triple::OpenBSD: 8546 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8547 case llvm::Triple::Bitrig: 8548 return new BitrigX86_64TargetInfo(Triple, Opts); 8549 case llvm::Triple::FreeBSD: 8550 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8551 case llvm::Triple::KFreeBSD: 8552 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8553 case llvm::Triple::Solaris: 8554 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8555 case llvm::Triple::Win32: { 8556 switch (Triple.getEnvironment()) { 8557 case llvm::Triple::Cygnus: 8558 return new CygwinX86_64TargetInfo(Triple, Opts); 8559 case llvm::Triple::GNU: 8560 return new MinGWX86_64TargetInfo(Triple, Opts); 8561 case llvm::Triple::MSVC: 8562 default: // Assume MSVC for unknown environments 8563 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8564 } 8565 } 8566 case llvm::Triple::Haiku: 8567 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8568 case llvm::Triple::NaCl: 8569 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8570 case llvm::Triple::PS4: 8571 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8572 default: 8573 return new X86_64TargetInfo(Triple, Opts); 8574 } 8575 8576 case llvm::Triple::spir: { 8577 if (Triple.getOS() != llvm::Triple::UnknownOS || 8578 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8579 return nullptr; 8580 return new SPIR32TargetInfo(Triple, Opts); 8581 } 8582 case llvm::Triple::spir64: { 8583 if (Triple.getOS() != llvm::Triple::UnknownOS || 8584 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8585 return nullptr; 8586 return new SPIR64TargetInfo(Triple, Opts); 8587 } 8588 case llvm::Triple::wasm32: 8589 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8590 return nullptr; 8591 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8592 case llvm::Triple::wasm64: 8593 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8594 return nullptr; 8595 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8596 8597 case llvm::Triple::renderscript32: 8598 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 8599 case llvm::Triple::renderscript64: 8600 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 8601 } 8602 } 8603 8604 /// CreateTargetInfo - Return the target info object for the specified target 8605 /// options. 8606 TargetInfo * 8607 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8608 const std::shared_ptr<TargetOptions> &Opts) { 8609 llvm::Triple Triple(Opts->Triple); 8610 8611 // Construct the target 8612 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8613 if (!Target) { 8614 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8615 return nullptr; 8616 } 8617 Target->TargetOpts = Opts; 8618 8619 // Set the target CPU if specified. 8620 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8621 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8622 return nullptr; 8623 } 8624 8625 // Set the target ABI if specified. 8626 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8627 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8628 return nullptr; 8629 } 8630 8631 // Set the fp math unit. 8632 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8633 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8634 return nullptr; 8635 } 8636 8637 // Compute the default target features, we need the target to handle this 8638 // because features may have dependencies on one another. 8639 llvm::StringMap<bool> Features; 8640 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8641 Opts->FeaturesAsWritten)) 8642 return nullptr; 8643 8644 // Add the features to the compile options. 8645 Opts->Features.clear(); 8646 for (const auto &F : Features) 8647 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8648 8649 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8650 return nullptr; 8651 8652 Target->setSupportedOpenCLOpts(); 8653 8654 if (!Target->validateTarget(Diags)) 8655 return nullptr; 8656 8657 return Target.release(); 8658 } 8659