1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 if (Maj) 469 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 470 } 471 if (Opts.POSIXThreads) 472 Builder.defineMacro("_REENTRANT"); 473 if (Opts.CPlusPlus) 474 Builder.defineMacro("_GNU_SOURCE"); 475 if (this->HasFloat128) 476 Builder.defineMacro("__FLOAT128__"); 477 } 478 public: 479 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 480 : OSTargetInfo<Target>(Triple, Opts) { 481 this->WIntType = TargetInfo::UnsignedInt; 482 483 switch (Triple.getArch()) { 484 default: 485 break; 486 case llvm::Triple::ppc: 487 case llvm::Triple::ppc64: 488 case llvm::Triple::ppc64le: 489 this->MCountName = "_mcount"; 490 break; 491 case llvm::Triple::x86: 492 case llvm::Triple::x86_64: 493 case llvm::Triple::systemz: 494 this->HasFloat128 = true; 495 break; 496 } 497 } 498 499 const char *getStaticInitSectionSpecifier() const override { 500 return ".text.startup"; 501 } 502 }; 503 504 // NetBSD Target 505 template<typename Target> 506 class NetBSDTargetInfo : public OSTargetInfo<Target> { 507 protected: 508 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 509 MacroBuilder &Builder) const override { 510 // NetBSD defines; list based off of gcc output 511 Builder.defineMacro("__NetBSD__"); 512 Builder.defineMacro("__unix__"); 513 Builder.defineMacro("__ELF__"); 514 if (Opts.POSIXThreads) 515 Builder.defineMacro("_REENTRANT"); 516 517 switch (Triple.getArch()) { 518 default: 519 break; 520 case llvm::Triple::arm: 521 case llvm::Triple::armeb: 522 case llvm::Triple::thumb: 523 case llvm::Triple::thumbeb: 524 Builder.defineMacro("__ARM_DWARF_EH__"); 525 break; 526 } 527 } 528 public: 529 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 530 : OSTargetInfo<Target>(Triple, Opts) { 531 this->MCountName = "_mcount"; 532 } 533 }; 534 535 // OpenBSD Target 536 template<typename Target> 537 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 538 protected: 539 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 540 MacroBuilder &Builder) const override { 541 // OpenBSD defines; list based off of gcc output 542 543 Builder.defineMacro("__OpenBSD__"); 544 DefineStd(Builder, "unix", Opts); 545 Builder.defineMacro("__ELF__"); 546 if (Opts.POSIXThreads) 547 Builder.defineMacro("_REENTRANT"); 548 if (this->HasFloat128) 549 Builder.defineMacro("__FLOAT128__"); 550 } 551 public: 552 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 553 : OSTargetInfo<Target>(Triple, Opts) { 554 this->TLSSupported = false; 555 556 switch (Triple.getArch()) { 557 case llvm::Triple::x86: 558 case llvm::Triple::x86_64: 559 this->HasFloat128 = true; 560 // FALLTHROUGH 561 default: 562 this->MCountName = "__mcount"; 563 break; 564 case llvm::Triple::mips64: 565 case llvm::Triple::mips64el: 566 case llvm::Triple::ppc: 567 case llvm::Triple::sparcv9: 568 this->MCountName = "_mcount"; 569 break; 570 } 571 } 572 }; 573 574 // Bitrig Target 575 template<typename Target> 576 class BitrigTargetInfo : public OSTargetInfo<Target> { 577 protected: 578 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 579 MacroBuilder &Builder) const override { 580 // Bitrig defines; list based off of gcc output 581 582 Builder.defineMacro("__Bitrig__"); 583 DefineStd(Builder, "unix", Opts); 584 Builder.defineMacro("__ELF__"); 585 if (Opts.POSIXThreads) 586 Builder.defineMacro("_REENTRANT"); 587 588 switch (Triple.getArch()) { 589 default: 590 break; 591 case llvm::Triple::arm: 592 case llvm::Triple::armeb: 593 case llvm::Triple::thumb: 594 case llvm::Triple::thumbeb: 595 Builder.defineMacro("__ARM_DWARF_EH__"); 596 break; 597 } 598 } 599 public: 600 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 601 : OSTargetInfo<Target>(Triple, Opts) { 602 this->MCountName = "__mcount"; 603 } 604 }; 605 606 // PSP Target 607 template<typename Target> 608 class PSPTargetInfo : public OSTargetInfo<Target> { 609 protected: 610 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 611 MacroBuilder &Builder) const override { 612 // PSP defines; list based on the output of the pspdev gcc toolchain. 613 Builder.defineMacro("PSP"); 614 Builder.defineMacro("_PSP"); 615 Builder.defineMacro("__psp__"); 616 Builder.defineMacro("__ELF__"); 617 } 618 public: 619 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 620 }; 621 622 // PS3 PPU Target 623 template<typename Target> 624 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 625 protected: 626 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 627 MacroBuilder &Builder) const override { 628 // PS3 PPU defines. 629 Builder.defineMacro("__PPC__"); 630 Builder.defineMacro("__PPU__"); 631 Builder.defineMacro("__CELLOS_LV2__"); 632 Builder.defineMacro("__ELF__"); 633 Builder.defineMacro("__LP32__"); 634 Builder.defineMacro("_ARCH_PPC64"); 635 Builder.defineMacro("__powerpc64__"); 636 } 637 public: 638 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 639 : OSTargetInfo<Target>(Triple, Opts) { 640 this->LongWidth = this->LongAlign = 32; 641 this->PointerWidth = this->PointerAlign = 32; 642 this->IntMaxType = TargetInfo::SignedLongLong; 643 this->Int64Type = TargetInfo::SignedLongLong; 644 this->SizeType = TargetInfo::UnsignedInt; 645 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 646 } 647 }; 648 649 template <typename Target> 650 class PS4OSTargetInfo : public OSTargetInfo<Target> { 651 protected: 652 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 653 MacroBuilder &Builder) const override { 654 Builder.defineMacro("__FreeBSD__", "9"); 655 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 656 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 657 DefineStd(Builder, "unix", Opts); 658 Builder.defineMacro("__ELF__"); 659 Builder.defineMacro("__ORBIS__"); 660 } 661 public: 662 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 663 : OSTargetInfo<Target>(Triple, Opts) { 664 this->WCharType = this->UnsignedShort; 665 666 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 667 this->MaxTLSAlign = 256; 668 669 // On PS4, do not honor explicit bit field alignment, 670 // as in "__attribute__((aligned(2))) int b : 1;". 671 this->UseExplicitBitFieldAlignment = false; 672 673 switch (Triple.getArch()) { 674 default: 675 case llvm::Triple::x86_64: 676 this->MCountName = ".mcount"; 677 break; 678 } 679 } 680 }; 681 682 // Solaris target 683 template<typename Target> 684 class SolarisTargetInfo : public OSTargetInfo<Target> { 685 protected: 686 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 687 MacroBuilder &Builder) const override { 688 DefineStd(Builder, "sun", Opts); 689 DefineStd(Builder, "unix", Opts); 690 Builder.defineMacro("__ELF__"); 691 Builder.defineMacro("__svr4__"); 692 Builder.defineMacro("__SVR4"); 693 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 694 // newer, but to 500 for everything else. feature_test.h has a check to 695 // ensure that you are not using C99 with an old version of X/Open or C89 696 // with a new version. 697 if (Opts.C99) 698 Builder.defineMacro("_XOPEN_SOURCE", "600"); 699 else 700 Builder.defineMacro("_XOPEN_SOURCE", "500"); 701 if (Opts.CPlusPlus) 702 Builder.defineMacro("__C99FEATURES__"); 703 Builder.defineMacro("_LARGEFILE_SOURCE"); 704 Builder.defineMacro("_LARGEFILE64_SOURCE"); 705 Builder.defineMacro("__EXTENSIONS__"); 706 Builder.defineMacro("_REENTRANT"); 707 } 708 public: 709 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 710 : OSTargetInfo<Target>(Triple, Opts) { 711 this->WCharType = this->SignedInt; 712 // FIXME: WIntType should be SignedLong 713 } 714 }; 715 716 // Windows target 717 template<typename Target> 718 class WindowsTargetInfo : public OSTargetInfo<Target> { 719 protected: 720 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 721 MacroBuilder &Builder) const override { 722 Builder.defineMacro("_WIN32"); 723 } 724 void getVisualStudioDefines(const LangOptions &Opts, 725 MacroBuilder &Builder) const { 726 if (Opts.CPlusPlus) { 727 if (Opts.RTTIData) 728 Builder.defineMacro("_CPPRTTI"); 729 730 if (Opts.CXXExceptions) 731 Builder.defineMacro("_CPPUNWIND"); 732 } 733 734 if (Opts.Bool) 735 Builder.defineMacro("__BOOL_DEFINED"); 736 737 if (!Opts.CharIsSigned) 738 Builder.defineMacro("_CHAR_UNSIGNED"); 739 740 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 741 // but it works for now. 742 if (Opts.POSIXThreads) 743 Builder.defineMacro("_MT"); 744 745 if (Opts.MSCompatibilityVersion) { 746 Builder.defineMacro("_MSC_VER", 747 Twine(Opts.MSCompatibilityVersion / 100000)); 748 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 749 // FIXME We cannot encode the revision information into 32-bits 750 Builder.defineMacro("_MSC_BUILD", Twine(1)); 751 752 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 753 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 754 755 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 756 if (Opts.CPlusPlus1z) 757 Builder.defineMacro("_MSVC_LANG", "201403L"); 758 else if (Opts.CPlusPlus14) 759 Builder.defineMacro("_MSVC_LANG", "201402L"); 760 } 761 } 762 763 if (Opts.MicrosoftExt) { 764 Builder.defineMacro("_MSC_EXTENSIONS"); 765 766 if (Opts.CPlusPlus11) { 767 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 768 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 769 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 770 } 771 } 772 773 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 774 } 775 776 public: 777 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 778 : OSTargetInfo<Target>(Triple, Opts) {} 779 }; 780 781 template <typename Target> 782 class NaClTargetInfo : public OSTargetInfo<Target> { 783 protected: 784 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 785 MacroBuilder &Builder) const override { 786 if (Opts.POSIXThreads) 787 Builder.defineMacro("_REENTRANT"); 788 if (Opts.CPlusPlus) 789 Builder.defineMacro("_GNU_SOURCE"); 790 791 DefineStd(Builder, "unix", Opts); 792 Builder.defineMacro("__ELF__"); 793 Builder.defineMacro("__native_client__"); 794 } 795 796 public: 797 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 798 : OSTargetInfo<Target>(Triple, Opts) { 799 this->LongAlign = 32; 800 this->LongWidth = 32; 801 this->PointerAlign = 32; 802 this->PointerWidth = 32; 803 this->IntMaxType = TargetInfo::SignedLongLong; 804 this->Int64Type = TargetInfo::SignedLongLong; 805 this->DoubleAlign = 64; 806 this->LongDoubleWidth = 64; 807 this->LongDoubleAlign = 64; 808 this->LongLongWidth = 64; 809 this->LongLongAlign = 64; 810 this->SizeType = TargetInfo::UnsignedInt; 811 this->PtrDiffType = TargetInfo::SignedInt; 812 this->IntPtrType = TargetInfo::SignedInt; 813 // RegParmMax is inherited from the underlying architecture. 814 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 815 if (Triple.getArch() == llvm::Triple::arm) { 816 // Handled in ARM's setABI(). 817 } else if (Triple.getArch() == llvm::Triple::x86) { 818 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 819 } else if (Triple.getArch() == llvm::Triple::x86_64) { 820 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 821 } else if (Triple.getArch() == llvm::Triple::mipsel) { 822 // Handled on mips' setDataLayout. 823 } else { 824 assert(Triple.getArch() == llvm::Triple::le32); 825 this->resetDataLayout("e-p:32:32-i64:64"); 826 } 827 } 828 }; 829 830 // Fuchsia Target 831 template<typename Target> 832 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 833 protected: 834 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 835 MacroBuilder &Builder) const override { 836 Builder.defineMacro("__Fuchsia__"); 837 Builder.defineMacro("__ELF__"); 838 if (Opts.POSIXThreads) 839 Builder.defineMacro("_REENTRANT"); 840 // Required by the libc++ locale support. 841 if (Opts.CPlusPlus) 842 Builder.defineMacro("_GNU_SOURCE"); 843 } 844 public: 845 FuchsiaTargetInfo(const llvm::Triple &Triple, 846 const TargetOptions &Opts) 847 : OSTargetInfo<Target>(Triple, Opts) { 848 this->MCountName = "__mcount"; 849 } 850 }; 851 852 // WebAssembly target 853 template <typename Target> 854 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 855 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 856 MacroBuilder &Builder) const final { 857 // A common platform macro. 858 if (Opts.POSIXThreads) 859 Builder.defineMacro("_REENTRANT"); 860 // Follow g++ convention and predefine _GNU_SOURCE for C++. 861 if (Opts.CPlusPlus) 862 Builder.defineMacro("_GNU_SOURCE"); 863 } 864 865 // As an optimization, group static init code together in a section. 866 const char *getStaticInitSectionSpecifier() const final { 867 return ".text.__startup"; 868 } 869 870 public: 871 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 872 const TargetOptions &Opts) 873 : OSTargetInfo<Target>(Triple, Opts) { 874 this->MCountName = "__mcount"; 875 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 876 } 877 }; 878 879 //===----------------------------------------------------------------------===// 880 // Specific target implementations. 881 //===----------------------------------------------------------------------===// 882 883 // PPC abstract base class 884 class PPCTargetInfo : public TargetInfo { 885 static const Builtin::Info BuiltinInfo[]; 886 static const char * const GCCRegNames[]; 887 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 888 std::string CPU; 889 890 // Target cpu features. 891 bool HasVSX; 892 bool HasP8Vector; 893 bool HasP8Crypto; 894 bool HasDirectMove; 895 bool HasQPX; 896 bool HasHTM; 897 bool HasBPERMD; 898 bool HasExtDiv; 899 bool HasP9Vector; 900 901 protected: 902 std::string ABI; 903 904 public: 905 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 906 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 907 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 908 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 909 SimdDefaultAlign = 128; 910 LongDoubleWidth = LongDoubleAlign = 128; 911 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 912 } 913 914 /// \brief Flags for architecture specific defines. 915 typedef enum { 916 ArchDefineNone = 0, 917 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 918 ArchDefinePpcgr = 1 << 1, 919 ArchDefinePpcsq = 1 << 2, 920 ArchDefine440 = 1 << 3, 921 ArchDefine603 = 1 << 4, 922 ArchDefine604 = 1 << 5, 923 ArchDefinePwr4 = 1 << 6, 924 ArchDefinePwr5 = 1 << 7, 925 ArchDefinePwr5x = 1 << 8, 926 ArchDefinePwr6 = 1 << 9, 927 ArchDefinePwr6x = 1 << 10, 928 ArchDefinePwr7 = 1 << 11, 929 ArchDefinePwr8 = 1 << 12, 930 ArchDefinePwr9 = 1 << 13, 931 ArchDefineA2 = 1 << 14, 932 ArchDefineA2q = 1 << 15 933 } ArchDefineTypes; 934 935 // Note: GCC recognizes the following additional cpus: 936 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 937 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 938 // titan, rs64. 939 bool setCPU(const std::string &Name) override { 940 bool CPUKnown = llvm::StringSwitch<bool>(Name) 941 .Case("generic", true) 942 .Case("440", true) 943 .Case("450", true) 944 .Case("601", true) 945 .Case("602", true) 946 .Case("603", true) 947 .Case("603e", true) 948 .Case("603ev", true) 949 .Case("604", true) 950 .Case("604e", true) 951 .Case("620", true) 952 .Case("630", true) 953 .Case("g3", true) 954 .Case("7400", true) 955 .Case("g4", true) 956 .Case("7450", true) 957 .Case("g4+", true) 958 .Case("750", true) 959 .Case("970", true) 960 .Case("g5", true) 961 .Case("a2", true) 962 .Case("a2q", true) 963 .Case("e500mc", true) 964 .Case("e5500", true) 965 .Case("power3", true) 966 .Case("pwr3", true) 967 .Case("power4", true) 968 .Case("pwr4", true) 969 .Case("power5", true) 970 .Case("pwr5", true) 971 .Case("power5x", true) 972 .Case("pwr5x", true) 973 .Case("power6", true) 974 .Case("pwr6", true) 975 .Case("power6x", true) 976 .Case("pwr6x", true) 977 .Case("power7", true) 978 .Case("pwr7", true) 979 .Case("power8", true) 980 .Case("pwr8", true) 981 .Case("power9", true) 982 .Case("pwr9", true) 983 .Case("powerpc", true) 984 .Case("ppc", true) 985 .Case("powerpc64", true) 986 .Case("ppc64", true) 987 .Case("powerpc64le", true) 988 .Case("ppc64le", true) 989 .Default(false); 990 991 if (CPUKnown) 992 CPU = Name; 993 994 return CPUKnown; 995 } 996 997 998 StringRef getABI() const override { return ABI; } 999 1000 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1001 return llvm::makeArrayRef(BuiltinInfo, 1002 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1003 } 1004 1005 bool isCLZForZeroUndef() const override { return false; } 1006 1007 void getTargetDefines(const LangOptions &Opts, 1008 MacroBuilder &Builder) const override; 1009 1010 bool 1011 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1012 StringRef CPU, 1013 const std::vector<std::string> &FeaturesVec) const override; 1014 1015 bool handleTargetFeatures(std::vector<std::string> &Features, 1016 DiagnosticsEngine &Diags) override; 1017 bool hasFeature(StringRef Feature) const override; 1018 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1019 bool Enabled) const override; 1020 1021 ArrayRef<const char *> getGCCRegNames() const override; 1022 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1023 bool validateAsmConstraint(const char *&Name, 1024 TargetInfo::ConstraintInfo &Info) const override { 1025 switch (*Name) { 1026 default: return false; 1027 case 'O': // Zero 1028 break; 1029 case 'b': // Base register 1030 case 'f': // Floating point register 1031 Info.setAllowsRegister(); 1032 break; 1033 // FIXME: The following are added to allow parsing. 1034 // I just took a guess at what the actions should be. 1035 // Also, is more specific checking needed? I.e. specific registers? 1036 case 'd': // Floating point register (containing 64-bit value) 1037 case 'v': // Altivec vector register 1038 Info.setAllowsRegister(); 1039 break; 1040 case 'w': 1041 switch (Name[1]) { 1042 case 'd':// VSX vector register to hold vector double data 1043 case 'f':// VSX vector register to hold vector float data 1044 case 's':// VSX vector register to hold scalar float data 1045 case 'a':// Any VSX register 1046 case 'c':// An individual CR bit 1047 break; 1048 default: 1049 return false; 1050 } 1051 Info.setAllowsRegister(); 1052 Name++; // Skip over 'w'. 1053 break; 1054 case 'h': // `MQ', `CTR', or `LINK' register 1055 case 'q': // `MQ' register 1056 case 'c': // `CTR' register 1057 case 'l': // `LINK' register 1058 case 'x': // `CR' register (condition register) number 0 1059 case 'y': // `CR' register (condition register) 1060 case 'z': // `XER[CA]' carry bit (part of the XER register) 1061 Info.setAllowsRegister(); 1062 break; 1063 case 'I': // Signed 16-bit constant 1064 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1065 // (use `L' instead for SImode constants) 1066 case 'K': // Unsigned 16-bit constant 1067 case 'L': // Signed 16-bit constant shifted left 16 bits 1068 case 'M': // Constant larger than 31 1069 case 'N': // Exact power of 2 1070 case 'P': // Constant whose negation is a signed 16-bit constant 1071 case 'G': // Floating point constant that can be loaded into a 1072 // register with one instruction per word 1073 case 'H': // Integer/Floating point constant that can be loaded 1074 // into a register using three instructions 1075 break; 1076 case 'm': // Memory operand. Note that on PowerPC targets, m can 1077 // include addresses that update the base register. It 1078 // is therefore only safe to use `m' in an asm statement 1079 // if that asm statement accesses the operand exactly once. 1080 // The asm statement must also use `%U<opno>' as a 1081 // placeholder for the "update" flag in the corresponding 1082 // load or store instruction. For example: 1083 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1084 // is correct but: 1085 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1086 // is not. Use es rather than m if you don't want the base 1087 // register to be updated. 1088 case 'e': 1089 if (Name[1] != 's') 1090 return false; 1091 // es: A "stable" memory operand; that is, one which does not 1092 // include any automodification of the base register. Unlike 1093 // `m', this constraint can be used in asm statements that 1094 // might access the operand several times, or that might not 1095 // access it at all. 1096 Info.setAllowsMemory(); 1097 Name++; // Skip over 'e'. 1098 break; 1099 case 'Q': // Memory operand that is an offset from a register (it is 1100 // usually better to use `m' or `es' in asm statements) 1101 case 'Z': // Memory operand that is an indexed or indirect from a 1102 // register (it is usually better to use `m' or `es' in 1103 // asm statements) 1104 Info.setAllowsMemory(); 1105 Info.setAllowsRegister(); 1106 break; 1107 case 'R': // AIX TOC entry 1108 case 'a': // Address operand that is an indexed or indirect from a 1109 // register (`p' is preferable for asm statements) 1110 case 'S': // Constant suitable as a 64-bit mask operand 1111 case 'T': // Constant suitable as a 32-bit mask operand 1112 case 'U': // System V Release 4 small data area reference 1113 case 't': // AND masks that can be performed by two rldic{l, r} 1114 // instructions 1115 case 'W': // Vector constant that does not require memory 1116 case 'j': // Vector constant that is all zeros. 1117 break; 1118 // End FIXME. 1119 } 1120 return true; 1121 } 1122 std::string convertConstraint(const char *&Constraint) const override { 1123 std::string R; 1124 switch (*Constraint) { 1125 case 'e': 1126 case 'w': 1127 // Two-character constraint; add "^" hint for later parsing. 1128 R = std::string("^") + std::string(Constraint, 2); 1129 Constraint++; 1130 break; 1131 default: 1132 return TargetInfo::convertConstraint(Constraint); 1133 } 1134 return R; 1135 } 1136 const char *getClobbers() const override { 1137 return ""; 1138 } 1139 int getEHDataRegisterNumber(unsigned RegNo) const override { 1140 if (RegNo == 0) return 3; 1141 if (RegNo == 1) return 4; 1142 return -1; 1143 } 1144 1145 bool hasSjLjLowering() const override { 1146 return true; 1147 } 1148 1149 bool useFloat128ManglingForLongDouble() const override { 1150 return LongDoubleWidth == 128 && 1151 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1152 getTriple().isOSBinFormatELF(); 1153 } 1154 }; 1155 1156 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1157 #define BUILTIN(ID, TYPE, ATTRS) \ 1158 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1159 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1160 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1161 #include "clang/Basic/BuiltinsPPC.def" 1162 }; 1163 1164 /// handleTargetFeatures - Perform initialization based on the user 1165 /// configured set of features. 1166 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1167 DiagnosticsEngine &Diags) { 1168 for (const auto &Feature : Features) { 1169 if (Feature == "+vsx") { 1170 HasVSX = true; 1171 } else if (Feature == "+bpermd") { 1172 HasBPERMD = true; 1173 } else if (Feature == "+extdiv") { 1174 HasExtDiv = true; 1175 } else if (Feature == "+power8-vector") { 1176 HasP8Vector = true; 1177 } else if (Feature == "+crypto") { 1178 HasP8Crypto = true; 1179 } else if (Feature == "+direct-move") { 1180 HasDirectMove = true; 1181 } else if (Feature == "+qpx") { 1182 HasQPX = true; 1183 } else if (Feature == "+htm") { 1184 HasHTM = true; 1185 } else if (Feature == "+float128") { 1186 HasFloat128 = true; 1187 } else if (Feature == "+power9-vector") { 1188 HasP9Vector = true; 1189 } 1190 // TODO: Finish this list and add an assert that we've handled them 1191 // all. 1192 } 1193 1194 return true; 1195 } 1196 1197 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1198 /// #defines that are not tied to a specific subtarget. 1199 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1200 MacroBuilder &Builder) const { 1201 // Target identification. 1202 Builder.defineMacro("__ppc__"); 1203 Builder.defineMacro("__PPC__"); 1204 Builder.defineMacro("_ARCH_PPC"); 1205 Builder.defineMacro("__powerpc__"); 1206 Builder.defineMacro("__POWERPC__"); 1207 if (PointerWidth == 64) { 1208 Builder.defineMacro("_ARCH_PPC64"); 1209 Builder.defineMacro("__powerpc64__"); 1210 Builder.defineMacro("__ppc64__"); 1211 Builder.defineMacro("__PPC64__"); 1212 } 1213 1214 // Target properties. 1215 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1216 Builder.defineMacro("_LITTLE_ENDIAN"); 1217 } else { 1218 if (getTriple().getOS() != llvm::Triple::NetBSD && 1219 getTriple().getOS() != llvm::Triple::OpenBSD) 1220 Builder.defineMacro("_BIG_ENDIAN"); 1221 } 1222 1223 // ABI options. 1224 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1225 Builder.defineMacro("_CALL_ELF", "1"); 1226 if (ABI == "elfv2") 1227 Builder.defineMacro("_CALL_ELF", "2"); 1228 1229 // Subtarget options. 1230 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1231 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1232 1233 // FIXME: Should be controlled by command line option. 1234 if (LongDoubleWidth == 128) 1235 Builder.defineMacro("__LONG_DOUBLE_128__"); 1236 1237 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1238 if (ABI == "elfv2" || 1239 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1240 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1241 1242 if (Opts.AltiVec) { 1243 Builder.defineMacro("__VEC__", "10206"); 1244 Builder.defineMacro("__ALTIVEC__"); 1245 } 1246 1247 // CPU identification. 1248 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1249 .Case("440", ArchDefineName) 1250 .Case("450", ArchDefineName | ArchDefine440) 1251 .Case("601", ArchDefineName) 1252 .Case("602", ArchDefineName | ArchDefinePpcgr) 1253 .Case("603", ArchDefineName | ArchDefinePpcgr) 1254 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1255 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1256 .Case("604", ArchDefineName | ArchDefinePpcgr) 1257 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1258 .Case("620", ArchDefineName | ArchDefinePpcgr) 1259 .Case("630", ArchDefineName | ArchDefinePpcgr) 1260 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1261 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1262 .Case("750", ArchDefineName | ArchDefinePpcgr) 1263 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1264 | ArchDefinePpcsq) 1265 .Case("a2", ArchDefineA2) 1266 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1267 .Case("pwr3", ArchDefinePpcgr) 1268 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1269 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1270 | ArchDefinePpcsq) 1271 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1272 | ArchDefinePpcgr | ArchDefinePpcsq) 1273 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1274 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1275 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1276 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1277 | ArchDefinePpcsq) 1278 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1279 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1280 | ArchDefinePpcgr | ArchDefinePpcsq) 1281 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1282 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1283 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1284 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1285 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1286 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1287 | ArchDefinePpcsq) 1288 .Case("power3", ArchDefinePpcgr) 1289 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1290 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1291 | ArchDefinePpcsq) 1292 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1293 | ArchDefinePpcgr | ArchDefinePpcsq) 1294 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1295 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1296 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1297 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1298 | ArchDefinePpcsq) 1299 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1300 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1301 | ArchDefinePpcgr | ArchDefinePpcsq) 1302 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1303 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1304 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1305 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1306 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1307 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1308 | ArchDefinePpcsq) 1309 .Default(ArchDefineNone); 1310 1311 if (defs & ArchDefineName) 1312 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1313 if (defs & ArchDefinePpcgr) 1314 Builder.defineMacro("_ARCH_PPCGR"); 1315 if (defs & ArchDefinePpcsq) 1316 Builder.defineMacro("_ARCH_PPCSQ"); 1317 if (defs & ArchDefine440) 1318 Builder.defineMacro("_ARCH_440"); 1319 if (defs & ArchDefine603) 1320 Builder.defineMacro("_ARCH_603"); 1321 if (defs & ArchDefine604) 1322 Builder.defineMacro("_ARCH_604"); 1323 if (defs & ArchDefinePwr4) 1324 Builder.defineMacro("_ARCH_PWR4"); 1325 if (defs & ArchDefinePwr5) 1326 Builder.defineMacro("_ARCH_PWR5"); 1327 if (defs & ArchDefinePwr5x) 1328 Builder.defineMacro("_ARCH_PWR5X"); 1329 if (defs & ArchDefinePwr6) 1330 Builder.defineMacro("_ARCH_PWR6"); 1331 if (defs & ArchDefinePwr6x) 1332 Builder.defineMacro("_ARCH_PWR6X"); 1333 if (defs & ArchDefinePwr7) 1334 Builder.defineMacro("_ARCH_PWR7"); 1335 if (defs & ArchDefinePwr8) 1336 Builder.defineMacro("_ARCH_PWR8"); 1337 if (defs & ArchDefinePwr9) 1338 Builder.defineMacro("_ARCH_PWR9"); 1339 if (defs & ArchDefineA2) 1340 Builder.defineMacro("_ARCH_A2"); 1341 if (defs & ArchDefineA2q) { 1342 Builder.defineMacro("_ARCH_A2Q"); 1343 Builder.defineMacro("_ARCH_QP"); 1344 } 1345 1346 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1347 Builder.defineMacro("__bg__"); 1348 Builder.defineMacro("__THW_BLUEGENE__"); 1349 Builder.defineMacro("__bgq__"); 1350 Builder.defineMacro("__TOS_BGQ__"); 1351 } 1352 1353 if (HasVSX) 1354 Builder.defineMacro("__VSX__"); 1355 if (HasP8Vector) 1356 Builder.defineMacro("__POWER8_VECTOR__"); 1357 if (HasP8Crypto) 1358 Builder.defineMacro("__CRYPTO__"); 1359 if (HasHTM) 1360 Builder.defineMacro("__HTM__"); 1361 if (HasFloat128) 1362 Builder.defineMacro("__FLOAT128__"); 1363 if (HasP9Vector) 1364 Builder.defineMacro("__POWER9_VECTOR__"); 1365 1366 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1367 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1368 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1369 if (PointerWidth == 64) 1370 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1371 1372 // FIXME: The following are not yet generated here by Clang, but are 1373 // generated by GCC: 1374 // 1375 // _SOFT_FLOAT_ 1376 // __RECIP_PRECISION__ 1377 // __APPLE_ALTIVEC__ 1378 // __RECIP__ 1379 // __RECIPF__ 1380 // __RSQRTE__ 1381 // __RSQRTEF__ 1382 // _SOFT_DOUBLE_ 1383 // __NO_LWSYNC__ 1384 // __HAVE_BSWAP__ 1385 // __LONGDOUBLE128 1386 // __CMODEL_MEDIUM__ 1387 // __CMODEL_LARGE__ 1388 // _CALL_SYSV 1389 // _CALL_DARWIN 1390 // __NO_FPRS__ 1391 } 1392 1393 // Handle explicit options being passed to the compiler here: if we've 1394 // explicitly turned off vsx and turned on any of: 1395 // - power8-vector 1396 // - direct-move 1397 // - float128 1398 // - power9-vector 1399 // then go ahead and error since the customer has expressed an incompatible 1400 // set of options. 1401 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1402 const std::vector<std::string> &FeaturesVec) { 1403 1404 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1405 FeaturesVec.end()) { 1406 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1407 FeaturesVec.end()) { 1408 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1409 << "-mno-vsx"; 1410 return false; 1411 } 1412 1413 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1414 FeaturesVec.end()) { 1415 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1416 << "-mno-vsx"; 1417 return false; 1418 } 1419 1420 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1421 FeaturesVec.end()) { 1422 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1423 << "-mno-vsx"; 1424 return false; 1425 } 1426 1427 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1428 FeaturesVec.end()) { 1429 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1430 << "-mno-vsx"; 1431 return false; 1432 } 1433 } 1434 1435 return true; 1436 } 1437 1438 bool PPCTargetInfo::initFeatureMap( 1439 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1440 const std::vector<std::string> &FeaturesVec) const { 1441 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1442 .Case("7400", true) 1443 .Case("g4", true) 1444 .Case("7450", true) 1445 .Case("g4+", true) 1446 .Case("970", true) 1447 .Case("g5", true) 1448 .Case("pwr6", true) 1449 .Case("pwr7", true) 1450 .Case("pwr8", true) 1451 .Case("pwr9", true) 1452 .Case("ppc64", true) 1453 .Case("ppc64le", true) 1454 .Default(false); 1455 1456 Features["qpx"] = (CPU == "a2q"); 1457 Features["power9-vector"] = (CPU == "pwr9"); 1458 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1459 .Case("ppc64le", true) 1460 .Case("pwr9", true) 1461 .Case("pwr8", true) 1462 .Default(false); 1463 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1464 .Case("ppc64le", true) 1465 .Case("pwr9", true) 1466 .Case("pwr8", true) 1467 .Default(false); 1468 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1469 .Case("ppc64le", true) 1470 .Case("pwr9", true) 1471 .Case("pwr8", true) 1472 .Case("pwr7", true) 1473 .Default(false); 1474 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1475 .Case("ppc64le", true) 1476 .Case("pwr9", true) 1477 .Case("pwr8", true) 1478 .Case("pwr7", true) 1479 .Default(false); 1480 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1481 .Case("ppc64le", true) 1482 .Case("pwr9", true) 1483 .Case("pwr8", true) 1484 .Default(false); 1485 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1486 .Case("ppc64le", true) 1487 .Case("pwr9", true) 1488 .Case("pwr8", true) 1489 .Case("pwr7", true) 1490 .Default(false); 1491 1492 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1493 return false; 1494 1495 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1496 } 1497 1498 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1499 return llvm::StringSwitch<bool>(Feature) 1500 .Case("powerpc", true) 1501 .Case("vsx", HasVSX) 1502 .Case("power8-vector", HasP8Vector) 1503 .Case("crypto", HasP8Crypto) 1504 .Case("direct-move", HasDirectMove) 1505 .Case("qpx", HasQPX) 1506 .Case("htm", HasHTM) 1507 .Case("bpermd", HasBPERMD) 1508 .Case("extdiv", HasExtDiv) 1509 .Case("float128", HasFloat128) 1510 .Case("power9-vector", HasP9Vector) 1511 .Default(false); 1512 } 1513 1514 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1515 StringRef Name, bool Enabled) const { 1516 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1517 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1518 // incompatible options. 1519 if (Enabled) { 1520 if (Name == "direct-move" || 1521 Name == "power8-vector" || 1522 Name == "float128" || 1523 Name == "power9-vector") { 1524 // power9-vector is really a superset of power8-vector so encode that. 1525 Features[Name] = Features["vsx"] = true; 1526 if (Name == "power9-vector") 1527 Features["power8-vector"] = true; 1528 } else { 1529 Features[Name] = true; 1530 } 1531 } else { 1532 if (Name == "vsx") { 1533 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1534 Features["float128"] = Features["power9-vector"] = false; 1535 } else { 1536 Features[Name] = false; 1537 } 1538 } 1539 } 1540 1541 const char * const PPCTargetInfo::GCCRegNames[] = { 1542 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1543 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1544 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1545 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1546 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1547 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1548 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1549 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1550 "mq", "lr", "ctr", "ap", 1551 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1552 "xer", 1553 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1554 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1555 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1556 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1557 "vrsave", "vscr", 1558 "spe_acc", "spefscr", 1559 "sfp" 1560 }; 1561 1562 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1563 return llvm::makeArrayRef(GCCRegNames); 1564 } 1565 1566 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1567 // While some of these aliases do map to different registers 1568 // they still share the same register name. 1569 { { "0" }, "r0" }, 1570 { { "1"}, "r1" }, 1571 { { "2" }, "r2" }, 1572 { { "3" }, "r3" }, 1573 { { "4" }, "r4" }, 1574 { { "5" }, "r5" }, 1575 { { "6" }, "r6" }, 1576 { { "7" }, "r7" }, 1577 { { "8" }, "r8" }, 1578 { { "9" }, "r9" }, 1579 { { "10" }, "r10" }, 1580 { { "11" }, "r11" }, 1581 { { "12" }, "r12" }, 1582 { { "13" }, "r13" }, 1583 { { "14" }, "r14" }, 1584 { { "15" }, "r15" }, 1585 { { "16" }, "r16" }, 1586 { { "17" }, "r17" }, 1587 { { "18" }, "r18" }, 1588 { { "19" }, "r19" }, 1589 { { "20" }, "r20" }, 1590 { { "21" }, "r21" }, 1591 { { "22" }, "r22" }, 1592 { { "23" }, "r23" }, 1593 { { "24" }, "r24" }, 1594 { { "25" }, "r25" }, 1595 { { "26" }, "r26" }, 1596 { { "27" }, "r27" }, 1597 { { "28" }, "r28" }, 1598 { { "29" }, "r29" }, 1599 { { "30" }, "r30" }, 1600 { { "31" }, "r31" }, 1601 { { "fr0" }, "f0" }, 1602 { { "fr1" }, "f1" }, 1603 { { "fr2" }, "f2" }, 1604 { { "fr3" }, "f3" }, 1605 { { "fr4" }, "f4" }, 1606 { { "fr5" }, "f5" }, 1607 { { "fr6" }, "f6" }, 1608 { { "fr7" }, "f7" }, 1609 { { "fr8" }, "f8" }, 1610 { { "fr9" }, "f9" }, 1611 { { "fr10" }, "f10" }, 1612 { { "fr11" }, "f11" }, 1613 { { "fr12" }, "f12" }, 1614 { { "fr13" }, "f13" }, 1615 { { "fr14" }, "f14" }, 1616 { { "fr15" }, "f15" }, 1617 { { "fr16" }, "f16" }, 1618 { { "fr17" }, "f17" }, 1619 { { "fr18" }, "f18" }, 1620 { { "fr19" }, "f19" }, 1621 { { "fr20" }, "f20" }, 1622 { { "fr21" }, "f21" }, 1623 { { "fr22" }, "f22" }, 1624 { { "fr23" }, "f23" }, 1625 { { "fr24" }, "f24" }, 1626 { { "fr25" }, "f25" }, 1627 { { "fr26" }, "f26" }, 1628 { { "fr27" }, "f27" }, 1629 { { "fr28" }, "f28" }, 1630 { { "fr29" }, "f29" }, 1631 { { "fr30" }, "f30" }, 1632 { { "fr31" }, "f31" }, 1633 { { "cc" }, "cr0" }, 1634 }; 1635 1636 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1637 return llvm::makeArrayRef(GCCRegAliases); 1638 } 1639 1640 class PPC32TargetInfo : public PPCTargetInfo { 1641 public: 1642 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1643 : PPCTargetInfo(Triple, Opts) { 1644 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1645 1646 switch (getTriple().getOS()) { 1647 case llvm::Triple::Linux: 1648 case llvm::Triple::FreeBSD: 1649 case llvm::Triple::NetBSD: 1650 SizeType = UnsignedInt; 1651 PtrDiffType = SignedInt; 1652 IntPtrType = SignedInt; 1653 break; 1654 default: 1655 break; 1656 } 1657 1658 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1659 LongDoubleWidth = LongDoubleAlign = 64; 1660 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1661 } 1662 1663 // PPC32 supports atomics up to 4 bytes. 1664 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1665 } 1666 1667 BuiltinVaListKind getBuiltinVaListKind() const override { 1668 // This is the ELF definition, and is overridden by the Darwin sub-target 1669 return TargetInfo::PowerABIBuiltinVaList; 1670 } 1671 }; 1672 1673 // Note: ABI differences may eventually require us to have a separate 1674 // TargetInfo for little endian. 1675 class PPC64TargetInfo : public PPCTargetInfo { 1676 public: 1677 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1678 : PPCTargetInfo(Triple, Opts) { 1679 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1680 IntMaxType = SignedLong; 1681 Int64Type = SignedLong; 1682 1683 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1684 resetDataLayout("e-m:e-i64:64-n32:64"); 1685 ABI = "elfv2"; 1686 } else { 1687 resetDataLayout("E-m:e-i64:64-n32:64"); 1688 ABI = "elfv1"; 1689 } 1690 1691 switch (getTriple().getOS()) { 1692 case llvm::Triple::FreeBSD: 1693 LongDoubleWidth = LongDoubleAlign = 64; 1694 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1695 break; 1696 case llvm::Triple::NetBSD: 1697 IntMaxType = SignedLongLong; 1698 Int64Type = SignedLongLong; 1699 break; 1700 default: 1701 break; 1702 } 1703 1704 // PPC64 supports atomics up to 8 bytes. 1705 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1706 } 1707 BuiltinVaListKind getBuiltinVaListKind() const override { 1708 return TargetInfo::CharPtrBuiltinVaList; 1709 } 1710 // PPC64 Linux-specific ABI options. 1711 bool setABI(const std::string &Name) override { 1712 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1713 ABI = Name; 1714 return true; 1715 } 1716 return false; 1717 } 1718 }; 1719 1720 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1721 public: 1722 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1723 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1724 HasAlignMac68kSupport = true; 1725 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1726 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1727 LongLongAlign = 32; 1728 SuitableAlign = 128; 1729 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1730 } 1731 BuiltinVaListKind getBuiltinVaListKind() const override { 1732 return TargetInfo::CharPtrBuiltinVaList; 1733 } 1734 }; 1735 1736 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1737 public: 1738 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1739 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1740 HasAlignMac68kSupport = true; 1741 SuitableAlign = 128; 1742 resetDataLayout("E-m:o-i64:64-n32:64"); 1743 } 1744 }; 1745 1746 static const unsigned NVPTXAddrSpaceMap[] = { 1747 1, // opencl_global 1748 3, // opencl_local 1749 4, // opencl_constant 1750 // FIXME: generic has to be added to the target 1751 0, // opencl_generic 1752 1, // cuda_device 1753 4, // cuda_constant 1754 3, // cuda_shared 1755 }; 1756 1757 class NVPTXTargetInfo : public TargetInfo { 1758 static const char *const GCCRegNames[]; 1759 static const Builtin::Info BuiltinInfo[]; 1760 CudaArch GPU; 1761 std::unique_ptr<TargetInfo> HostTarget; 1762 1763 public: 1764 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1765 unsigned TargetPointerWidth) 1766 : TargetInfo(Triple) { 1767 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1768 "NVPTX only supports 32- and 64-bit modes."); 1769 1770 TLSSupported = false; 1771 AddrSpaceMap = &NVPTXAddrSpaceMap; 1772 UseAddrSpaceMapMangling = true; 1773 1774 // Define available target features 1775 // These must be defined in sorted order! 1776 NoAsmVariants = true; 1777 GPU = CudaArch::SM_20; 1778 1779 if (TargetPointerWidth == 32) 1780 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1781 else 1782 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1783 1784 // If possible, get a TargetInfo for our host triple, so we can match its 1785 // types. 1786 llvm::Triple HostTriple(Opts.HostTriple); 1787 if (!HostTriple.isNVPTX()) 1788 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1789 1790 // If no host target, make some guesses about the data layout and return. 1791 if (!HostTarget) { 1792 LongWidth = LongAlign = TargetPointerWidth; 1793 PointerWidth = PointerAlign = TargetPointerWidth; 1794 switch (TargetPointerWidth) { 1795 case 32: 1796 SizeType = TargetInfo::UnsignedInt; 1797 PtrDiffType = TargetInfo::SignedInt; 1798 IntPtrType = TargetInfo::SignedInt; 1799 break; 1800 case 64: 1801 SizeType = TargetInfo::UnsignedLong; 1802 PtrDiffType = TargetInfo::SignedLong; 1803 IntPtrType = TargetInfo::SignedLong; 1804 break; 1805 default: 1806 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1807 } 1808 return; 1809 } 1810 1811 // Copy properties from host target. 1812 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1813 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1814 BoolWidth = HostTarget->getBoolWidth(); 1815 BoolAlign = HostTarget->getBoolAlign(); 1816 IntWidth = HostTarget->getIntWidth(); 1817 IntAlign = HostTarget->getIntAlign(); 1818 HalfWidth = HostTarget->getHalfWidth(); 1819 HalfAlign = HostTarget->getHalfAlign(); 1820 FloatWidth = HostTarget->getFloatWidth(); 1821 FloatAlign = HostTarget->getFloatAlign(); 1822 DoubleWidth = HostTarget->getDoubleWidth(); 1823 DoubleAlign = HostTarget->getDoubleAlign(); 1824 LongWidth = HostTarget->getLongWidth(); 1825 LongAlign = HostTarget->getLongAlign(); 1826 LongLongWidth = HostTarget->getLongLongWidth(); 1827 LongLongAlign = HostTarget->getLongLongAlign(); 1828 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1829 NewAlign = HostTarget->getNewAlign(); 1830 DefaultAlignForAttributeAligned = 1831 HostTarget->getDefaultAlignForAttributeAligned(); 1832 SizeType = HostTarget->getSizeType(); 1833 IntMaxType = HostTarget->getIntMaxType(); 1834 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1835 IntPtrType = HostTarget->getIntPtrType(); 1836 WCharType = HostTarget->getWCharType(); 1837 WIntType = HostTarget->getWIntType(); 1838 Char16Type = HostTarget->getChar16Type(); 1839 Char32Type = HostTarget->getChar32Type(); 1840 Int64Type = HostTarget->getInt64Type(); 1841 SigAtomicType = HostTarget->getSigAtomicType(); 1842 ProcessIDType = HostTarget->getProcessIDType(); 1843 1844 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1845 UseZeroLengthBitfieldAlignment = 1846 HostTarget->useZeroLengthBitfieldAlignment(); 1847 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1848 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1849 1850 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1851 // we need those macros to be identical on host and device, because (among 1852 // other things) they affect which standard library classes are defined, and 1853 // we need all classes to be defined on both the host and device. 1854 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1855 1856 // Properties intentionally not copied from host: 1857 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1858 // host/device boundary. 1859 // - SuitableAlign: Not visible across the host/device boundary, and may 1860 // correctly be different on host/device, e.g. if host has wider vector 1861 // types than device. 1862 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1863 // as its double type, but that's not necessarily true on the host. 1864 // TODO: nvcc emits a warning when using long double on device; we should 1865 // do the same. 1866 } 1867 void getTargetDefines(const LangOptions &Opts, 1868 MacroBuilder &Builder) const override { 1869 Builder.defineMacro("__PTX__"); 1870 Builder.defineMacro("__NVPTX__"); 1871 if (Opts.CUDAIsDevice) { 1872 // Set __CUDA_ARCH__ for the GPU specified. 1873 std::string CUDAArchCode = [this] { 1874 switch (GPU) { 1875 case CudaArch::UNKNOWN: 1876 assert(false && "No GPU arch when compiling CUDA device code."); 1877 return ""; 1878 case CudaArch::SM_20: 1879 return "200"; 1880 case CudaArch::SM_21: 1881 return "210"; 1882 case CudaArch::SM_30: 1883 return "300"; 1884 case CudaArch::SM_32: 1885 return "320"; 1886 case CudaArch::SM_35: 1887 return "350"; 1888 case CudaArch::SM_37: 1889 return "370"; 1890 case CudaArch::SM_50: 1891 return "500"; 1892 case CudaArch::SM_52: 1893 return "520"; 1894 case CudaArch::SM_53: 1895 return "530"; 1896 case CudaArch::SM_60: 1897 return "600"; 1898 case CudaArch::SM_61: 1899 return "610"; 1900 case CudaArch::SM_62: 1901 return "620"; 1902 } 1903 llvm_unreachable("unhandled CudaArch"); 1904 }(); 1905 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1906 } 1907 } 1908 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1909 return llvm::makeArrayRef(BuiltinInfo, 1910 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1911 } 1912 bool 1913 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1914 StringRef CPU, 1915 const std::vector<std::string> &FeaturesVec) const override { 1916 Features["satom"] = GPU >= CudaArch::SM_60; 1917 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1918 } 1919 1920 bool hasFeature(StringRef Feature) const override { 1921 return llvm::StringSwitch<bool>(Feature) 1922 .Cases("ptx", "nvptx", true) 1923 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1924 .Default(false); 1925 } 1926 1927 ArrayRef<const char *> getGCCRegNames() const override; 1928 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1929 // No aliases. 1930 return None; 1931 } 1932 bool validateAsmConstraint(const char *&Name, 1933 TargetInfo::ConstraintInfo &Info) const override { 1934 switch (*Name) { 1935 default: 1936 return false; 1937 case 'c': 1938 case 'h': 1939 case 'r': 1940 case 'l': 1941 case 'f': 1942 case 'd': 1943 Info.setAllowsRegister(); 1944 return true; 1945 } 1946 } 1947 const char *getClobbers() const override { 1948 // FIXME: Is this really right? 1949 return ""; 1950 } 1951 BuiltinVaListKind getBuiltinVaListKind() const override { 1952 // FIXME: implement 1953 return TargetInfo::CharPtrBuiltinVaList; 1954 } 1955 bool setCPU(const std::string &Name) override { 1956 GPU = StringToCudaArch(Name); 1957 return GPU != CudaArch::UNKNOWN; 1958 } 1959 void setSupportedOpenCLOpts() override { 1960 auto &Opts = getSupportedOpenCLOpts(); 1961 Opts.support("cl_clang_storage_class_specifiers"); 1962 Opts.support("cl_khr_gl_sharing"); 1963 Opts.support("cl_khr_icd"); 1964 1965 Opts.support("cl_khr_fp64"); 1966 Opts.support("cl_khr_byte_addressable_store"); 1967 Opts.support("cl_khr_global_int32_base_atomics"); 1968 Opts.support("cl_khr_global_int32_extended_atomics"); 1969 Opts.support("cl_khr_local_int32_base_atomics"); 1970 Opts.support("cl_khr_local_int32_extended_atomics"); 1971 } 1972 1973 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 1974 // CUDA compilations support all of the host's calling conventions. 1975 // 1976 // TODO: We should warn if you apply a non-default CC to anything other than 1977 // a host function. 1978 if (HostTarget) 1979 return HostTarget->checkCallingConvention(CC); 1980 return CCCR_Warning; 1981 } 1982 }; 1983 1984 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1985 #define BUILTIN(ID, TYPE, ATTRS) \ 1986 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1987 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1988 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1989 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 1990 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 1991 #include "clang/Basic/BuiltinsNVPTX.def" 1992 }; 1993 1994 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1995 1996 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1997 return llvm::makeArrayRef(GCCRegNames); 1998 } 1999 2000 static const unsigned AMDGPUAddrSpaceMap[] = { 2001 1, // opencl_global 2002 3, // opencl_local 2003 2, // opencl_constant 2004 4, // opencl_generic 2005 1, // cuda_device 2006 2, // cuda_constant 2007 3 // cuda_shared 2008 }; 2009 2010 // If you edit the description strings, make sure you update 2011 // getPointerWidthV(). 2012 2013 static const char *const DataLayoutStringR600 = 2014 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2015 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2016 2017 static const char *const DataLayoutStringSI = 2018 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2019 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2020 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2021 2022 class AMDGPUTargetInfo final : public TargetInfo { 2023 static const Builtin::Info BuiltinInfo[]; 2024 static const char * const GCCRegNames[]; 2025 2026 /// \brief The GPU profiles supported by the AMDGPU target. 2027 enum GPUKind { 2028 GK_NONE, 2029 GK_R600, 2030 GK_R600_DOUBLE_OPS, 2031 GK_R700, 2032 GK_R700_DOUBLE_OPS, 2033 GK_EVERGREEN, 2034 GK_EVERGREEN_DOUBLE_OPS, 2035 GK_NORTHERN_ISLANDS, 2036 GK_CAYMAN, 2037 GK_GFX6, 2038 GK_GFX7, 2039 GK_GFX8, 2040 GK_GFX9 2041 } GPU; 2042 2043 bool hasFP64:1; 2044 bool hasFMAF:1; 2045 bool hasLDEXPF:1; 2046 bool hasFullSpeedFP32Denorms:1; 2047 2048 static bool isAMDGCN(const llvm::Triple &TT) { 2049 return TT.getArch() == llvm::Triple::amdgcn; 2050 } 2051 2052 public: 2053 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2054 : TargetInfo(Triple) , 2055 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2056 hasFP64(false), 2057 hasFMAF(false), 2058 hasLDEXPF(false), 2059 hasFullSpeedFP32Denorms(false){ 2060 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2061 hasFP64 = true; 2062 hasFMAF = true; 2063 hasLDEXPF = true; 2064 } 2065 2066 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2067 DataLayoutStringSI : DataLayoutStringR600); 2068 2069 AddrSpaceMap = &AMDGPUAddrSpaceMap; 2070 UseAddrSpaceMapMangling = true; 2071 } 2072 2073 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2074 if (GPU <= GK_CAYMAN) 2075 return 32; 2076 2077 switch(AddrSpace) { 2078 default: 2079 return 64; 2080 case 0: 2081 case 3: 2082 case 5: 2083 return 32; 2084 } 2085 } 2086 2087 uint64_t getMaxPointerWidth() const override { 2088 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2089 } 2090 2091 const char * getClobbers() const override { 2092 return ""; 2093 } 2094 2095 ArrayRef<const char *> getGCCRegNames() const override; 2096 2097 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2098 return None; 2099 } 2100 2101 bool validateAsmConstraint(const char *&Name, 2102 TargetInfo::ConstraintInfo &Info) const override { 2103 switch (*Name) { 2104 default: break; 2105 case 'v': // vgpr 2106 case 's': // sgpr 2107 Info.setAllowsRegister(); 2108 return true; 2109 } 2110 return false; 2111 } 2112 2113 bool initFeatureMap(llvm::StringMap<bool> &Features, 2114 DiagnosticsEngine &Diags, StringRef CPU, 2115 const std::vector<std::string> &FeatureVec) const override; 2116 2117 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2118 TargetOptions &TargetOpts) const override { 2119 bool hasFP32Denormals = false; 2120 bool hasFP64Denormals = false; 2121 for (auto &I : TargetOpts.FeaturesAsWritten) { 2122 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2123 hasFP32Denormals = true; 2124 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2125 hasFP64Denormals = true; 2126 } 2127 if (!hasFP32Denormals) 2128 TargetOpts.Features.push_back((Twine(hasFullSpeedFP32Denorms && 2129 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2130 // Always do not flush fp64 or fp16 denorms. 2131 if (!hasFP64Denormals && hasFP64) 2132 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2133 } 2134 2135 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2136 return llvm::makeArrayRef(BuiltinInfo, 2137 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2138 } 2139 2140 void getTargetDefines(const LangOptions &Opts, 2141 MacroBuilder &Builder) const override { 2142 if (getTriple().getArch() == llvm::Triple::amdgcn) 2143 Builder.defineMacro("__AMDGCN__"); 2144 else 2145 Builder.defineMacro("__R600__"); 2146 2147 if (hasFMAF) 2148 Builder.defineMacro("__HAS_FMAF__"); 2149 if (hasLDEXPF) 2150 Builder.defineMacro("__HAS_LDEXPF__"); 2151 if (hasFP64) 2152 Builder.defineMacro("__HAS_FP64__"); 2153 } 2154 2155 BuiltinVaListKind getBuiltinVaListKind() const override { 2156 return TargetInfo::CharPtrBuiltinVaList; 2157 } 2158 2159 static GPUKind parseR600Name(StringRef Name) { 2160 return llvm::StringSwitch<GPUKind>(Name) 2161 .Case("r600" , GK_R600) 2162 .Case("rv610", GK_R600) 2163 .Case("rv620", GK_R600) 2164 .Case("rv630", GK_R600) 2165 .Case("rv635", GK_R600) 2166 .Case("rs780", GK_R600) 2167 .Case("rs880", GK_R600) 2168 .Case("rv670", GK_R600_DOUBLE_OPS) 2169 .Case("rv710", GK_R700) 2170 .Case("rv730", GK_R700) 2171 .Case("rv740", GK_R700_DOUBLE_OPS) 2172 .Case("rv770", GK_R700_DOUBLE_OPS) 2173 .Case("palm", GK_EVERGREEN) 2174 .Case("cedar", GK_EVERGREEN) 2175 .Case("sumo", GK_EVERGREEN) 2176 .Case("sumo2", GK_EVERGREEN) 2177 .Case("redwood", GK_EVERGREEN) 2178 .Case("juniper", GK_EVERGREEN) 2179 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2180 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2181 .Case("barts", GK_NORTHERN_ISLANDS) 2182 .Case("turks", GK_NORTHERN_ISLANDS) 2183 .Case("caicos", GK_NORTHERN_ISLANDS) 2184 .Case("cayman", GK_CAYMAN) 2185 .Case("aruba", GK_CAYMAN) 2186 .Default(GK_NONE); 2187 } 2188 2189 static GPUKind parseAMDGCNName(StringRef Name) { 2190 return llvm::StringSwitch<GPUKind>(Name) 2191 .Case("tahiti", GK_GFX6) 2192 .Case("pitcairn", GK_GFX6) 2193 .Case("verde", GK_GFX6) 2194 .Case("oland", GK_GFX6) 2195 .Case("hainan", GK_GFX6) 2196 .Case("bonaire", GK_GFX7) 2197 .Case("kabini", GK_GFX7) 2198 .Case("kaveri", GK_GFX7) 2199 .Case("hawaii", GK_GFX7) 2200 .Case("mullins", GK_GFX7) 2201 .Case("gfx700", GK_GFX7) 2202 .Case("gfx701", GK_GFX7) 2203 .Case("gfx702", GK_GFX7) 2204 .Case("tonga", GK_GFX8) 2205 .Case("iceland", GK_GFX8) 2206 .Case("carrizo", GK_GFX8) 2207 .Case("fiji", GK_GFX8) 2208 .Case("stoney", GK_GFX8) 2209 .Case("polaris10", GK_GFX8) 2210 .Case("polaris11", GK_GFX8) 2211 .Case("gfx800", GK_GFX8) 2212 .Case("gfx801", GK_GFX8) 2213 .Case("gfx802", GK_GFX8) 2214 .Case("gfx803", GK_GFX8) 2215 .Case("gfx804", GK_GFX8) 2216 .Case("gfx810", GK_GFX8) 2217 .Case("gfx900", GK_GFX9) 2218 .Case("gfx901", GK_GFX9) 2219 .Default(GK_NONE); 2220 } 2221 2222 bool setCPU(const std::string &Name) override { 2223 if (getTriple().getArch() == llvm::Triple::amdgcn) 2224 GPU = parseAMDGCNName(Name); 2225 else 2226 GPU = parseR600Name(Name); 2227 2228 return GPU != GK_NONE; 2229 } 2230 2231 void setSupportedOpenCLOpts() override { 2232 auto &Opts = getSupportedOpenCLOpts(); 2233 Opts.support("cl_clang_storage_class_specifiers"); 2234 Opts.support("cl_khr_icd"); 2235 2236 if (hasFP64) 2237 Opts.support("cl_khr_fp64"); 2238 if (GPU >= GK_EVERGREEN) { 2239 Opts.support("cl_khr_byte_addressable_store"); 2240 Opts.support("cl_khr_global_int32_base_atomics"); 2241 Opts.support("cl_khr_global_int32_extended_atomics"); 2242 Opts.support("cl_khr_local_int32_base_atomics"); 2243 Opts.support("cl_khr_local_int32_extended_atomics"); 2244 } 2245 if (GPU >= GK_GFX6) { 2246 Opts.support("cl_khr_fp16"); 2247 Opts.support("cl_khr_int64_base_atomics"); 2248 Opts.support("cl_khr_int64_extended_atomics"); 2249 Opts.support("cl_khr_mipmap_image"); 2250 Opts.support("cl_khr_subgroups"); 2251 Opts.support("cl_khr_3d_image_writes"); 2252 Opts.support("cl_amd_media_ops"); 2253 Opts.support("cl_amd_media_ops2"); 2254 } 2255 } 2256 2257 LangAS::ID getOpenCLImageAddrSpace() const override { 2258 return LangAS::opencl_constant; 2259 } 2260 2261 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2262 switch (CC) { 2263 default: 2264 return CCCR_Warning; 2265 case CC_C: 2266 case CC_OpenCLKernel: 2267 return CCCR_OK; 2268 } 2269 } 2270 2271 // In amdgcn target the null pointer in global, constant, and generic 2272 // address space has value 0 but in private and local address space has 2273 // value ~0. 2274 uint64_t getNullPointerValue(unsigned AS) const override { 2275 return AS != LangAS::opencl_local && AS != 0 ? 0 : ~0; 2276 } 2277 }; 2278 2279 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2280 #define BUILTIN(ID, TYPE, ATTRS) \ 2281 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2282 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2283 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2284 #include "clang/Basic/BuiltinsAMDGPU.def" 2285 }; 2286 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2287 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2288 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2289 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2290 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2291 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2292 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2293 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2294 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2295 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2296 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2297 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2298 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2299 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2300 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2301 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2302 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2303 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2304 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2305 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2306 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2307 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2308 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2309 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2310 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2311 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2312 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2313 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2314 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2315 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2316 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2317 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2318 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2319 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2320 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2321 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2322 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2323 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2324 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2325 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2326 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2327 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2328 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2329 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2330 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2331 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2332 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2333 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2334 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2335 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2336 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2337 }; 2338 2339 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2340 return llvm::makeArrayRef(GCCRegNames); 2341 } 2342 2343 bool AMDGPUTargetInfo::initFeatureMap( 2344 llvm::StringMap<bool> &Features, 2345 DiagnosticsEngine &Diags, StringRef CPU, 2346 const std::vector<std::string> &FeatureVec) const { 2347 2348 // XXX - What does the member GPU mean if device name string passed here? 2349 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2350 if (CPU.empty()) 2351 CPU = "tahiti"; 2352 2353 switch (parseAMDGCNName(CPU)) { 2354 case GK_GFX6: 2355 case GK_GFX7: 2356 break; 2357 2358 case GK_GFX9: 2359 Features["gfx9-insts"] = true; 2360 LLVM_FALLTHROUGH; 2361 case GK_GFX8: 2362 Features["s-memrealtime"] = true; 2363 Features["16-bit-insts"] = true; 2364 break; 2365 2366 case GK_NONE: 2367 return false; 2368 default: 2369 llvm_unreachable("unhandled subtarget"); 2370 } 2371 } else { 2372 if (CPU.empty()) 2373 CPU = "r600"; 2374 2375 switch (parseR600Name(CPU)) { 2376 case GK_R600: 2377 case GK_R700: 2378 case GK_EVERGREEN: 2379 case GK_NORTHERN_ISLANDS: 2380 break; 2381 case GK_R600_DOUBLE_OPS: 2382 case GK_R700_DOUBLE_OPS: 2383 case GK_EVERGREEN_DOUBLE_OPS: 2384 case GK_CAYMAN: 2385 Features["fp64"] = true; 2386 break; 2387 case GK_NONE: 2388 return false; 2389 default: 2390 llvm_unreachable("unhandled subtarget"); 2391 } 2392 } 2393 2394 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2395 } 2396 2397 const Builtin::Info BuiltinInfoX86[] = { 2398 #define BUILTIN(ID, TYPE, ATTRS) \ 2399 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2400 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2401 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2402 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2403 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2404 #include "clang/Basic/BuiltinsX86.def" 2405 2406 #define BUILTIN(ID, TYPE, ATTRS) \ 2407 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2408 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2409 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2410 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2411 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2412 #include "clang/Basic/BuiltinsX86_64.def" 2413 }; 2414 2415 2416 static const char* const GCCRegNames[] = { 2417 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2418 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2419 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2420 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2421 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2422 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2423 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2424 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2425 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2426 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2427 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2428 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2429 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2430 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2431 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2432 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2433 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2434 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2435 }; 2436 2437 const TargetInfo::AddlRegName AddlRegNames[] = { 2438 { { "al", "ah", "eax", "rax" }, 0 }, 2439 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2440 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2441 { { "dl", "dh", "edx", "rdx" }, 1 }, 2442 { { "esi", "rsi" }, 4 }, 2443 { { "edi", "rdi" }, 5 }, 2444 { { "esp", "rsp" }, 7 }, 2445 { { "ebp", "rbp" }, 6 }, 2446 { { "r8d", "r8w", "r8b" }, 38 }, 2447 { { "r9d", "r9w", "r9b" }, 39 }, 2448 { { "r10d", "r10w", "r10b" }, 40 }, 2449 { { "r11d", "r11w", "r11b" }, 41 }, 2450 { { "r12d", "r12w", "r12b" }, 42 }, 2451 { { "r13d", "r13w", "r13b" }, 43 }, 2452 { { "r14d", "r14w", "r14b" }, 44 }, 2453 { { "r15d", "r15w", "r15b" }, 45 }, 2454 }; 2455 2456 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2457 // most of the implementation can be shared. 2458 class X86TargetInfo : public TargetInfo { 2459 enum X86SSEEnum { 2460 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2461 } SSELevel = NoSSE; 2462 enum MMX3DNowEnum { 2463 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2464 } MMX3DNowLevel = NoMMX3DNow; 2465 enum XOPEnum { 2466 NoXOP, 2467 SSE4A, 2468 FMA4, 2469 XOP 2470 } XOPLevel = NoXOP; 2471 2472 bool HasAES = false; 2473 bool HasPCLMUL = false; 2474 bool HasLZCNT = false; 2475 bool HasRDRND = false; 2476 bool HasFSGSBASE = false; 2477 bool HasBMI = false; 2478 bool HasBMI2 = false; 2479 bool HasPOPCNT = false; 2480 bool HasRTM = false; 2481 bool HasPRFCHW = false; 2482 bool HasRDSEED = false; 2483 bool HasADX = false; 2484 bool HasTBM = false; 2485 bool HasFMA = false; 2486 bool HasF16C = false; 2487 bool HasAVX512CD = false; 2488 bool HasAVX512ER = false; 2489 bool HasAVX512PF = false; 2490 bool HasAVX512DQ = false; 2491 bool HasAVX512BW = false; 2492 bool HasAVX512VL = false; 2493 bool HasAVX512VBMI = false; 2494 bool HasAVX512IFMA = false; 2495 bool HasSHA = false; 2496 bool HasMPX = false; 2497 bool HasSGX = false; 2498 bool HasCX16 = false; 2499 bool HasFXSR = false; 2500 bool HasXSAVE = false; 2501 bool HasXSAVEOPT = false; 2502 bool HasXSAVEC = false; 2503 bool HasXSAVES = false; 2504 bool HasMWAITX = false; 2505 bool HasCLZERO = false; 2506 bool HasPKU = false; 2507 bool HasCLFLUSHOPT = false; 2508 bool HasCLWB = false; 2509 bool HasMOVBE = false; 2510 bool HasPREFETCHWT1 = false; 2511 2512 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2513 /// 2514 /// Each enumeration represents a particular CPU supported by Clang. These 2515 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2516 enum CPUKind { 2517 CK_Generic, 2518 2519 /// \name i386 2520 /// i386-generation processors. 2521 //@{ 2522 CK_i386, 2523 //@} 2524 2525 /// \name i486 2526 /// i486-generation processors. 2527 //@{ 2528 CK_i486, 2529 CK_WinChipC6, 2530 CK_WinChip2, 2531 CK_C3, 2532 //@} 2533 2534 /// \name i586 2535 /// i586-generation processors, P5 microarchitecture based. 2536 //@{ 2537 CK_i586, 2538 CK_Pentium, 2539 CK_PentiumMMX, 2540 //@} 2541 2542 /// \name i686 2543 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2544 //@{ 2545 CK_i686, 2546 CK_PentiumPro, 2547 CK_Pentium2, 2548 CK_Pentium3, 2549 CK_Pentium3M, 2550 CK_PentiumM, 2551 CK_C3_2, 2552 2553 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2554 /// Clang however has some logic to suport this. 2555 // FIXME: Warn, deprecate, and potentially remove this. 2556 CK_Yonah, 2557 //@} 2558 2559 /// \name Netburst 2560 /// Netburst microarchitecture based processors. 2561 //@{ 2562 CK_Pentium4, 2563 CK_Pentium4M, 2564 CK_Prescott, 2565 CK_Nocona, 2566 //@} 2567 2568 /// \name Core 2569 /// Core microarchitecture based processors. 2570 //@{ 2571 CK_Core2, 2572 2573 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2574 /// codename which GCC no longer accepts as an option to -march, but Clang 2575 /// has some logic for recognizing it. 2576 // FIXME: Warn, deprecate, and potentially remove this. 2577 CK_Penryn, 2578 //@} 2579 2580 /// \name Atom 2581 /// Atom processors 2582 //@{ 2583 CK_Bonnell, 2584 CK_Silvermont, 2585 //@} 2586 2587 /// \name Nehalem 2588 /// Nehalem microarchitecture based processors. 2589 CK_Nehalem, 2590 2591 /// \name Westmere 2592 /// Westmere microarchitecture based processors. 2593 CK_Westmere, 2594 2595 /// \name Sandy Bridge 2596 /// Sandy Bridge microarchitecture based processors. 2597 CK_SandyBridge, 2598 2599 /// \name Ivy Bridge 2600 /// Ivy Bridge microarchitecture based processors. 2601 CK_IvyBridge, 2602 2603 /// \name Haswell 2604 /// Haswell microarchitecture based processors. 2605 CK_Haswell, 2606 2607 /// \name Broadwell 2608 /// Broadwell microarchitecture based processors. 2609 CK_Broadwell, 2610 2611 /// \name Skylake Client 2612 /// Skylake client microarchitecture based processors. 2613 CK_SkylakeClient, 2614 2615 /// \name Skylake Server 2616 /// Skylake server microarchitecture based processors. 2617 CK_SkylakeServer, 2618 2619 /// \name Cannonlake Client 2620 /// Cannonlake client microarchitecture based processors. 2621 CK_Cannonlake, 2622 2623 /// \name Knights Landing 2624 /// Knights Landing processor. 2625 CK_KNL, 2626 2627 /// \name Lakemont 2628 /// Lakemont microarchitecture based processors. 2629 CK_Lakemont, 2630 2631 /// \name K6 2632 /// K6 architecture processors. 2633 //@{ 2634 CK_K6, 2635 CK_K6_2, 2636 CK_K6_3, 2637 //@} 2638 2639 /// \name K7 2640 /// K7 architecture processors. 2641 //@{ 2642 CK_Athlon, 2643 CK_AthlonThunderbird, 2644 CK_Athlon4, 2645 CK_AthlonXP, 2646 CK_AthlonMP, 2647 //@} 2648 2649 /// \name K8 2650 /// K8 architecture processors. 2651 //@{ 2652 CK_Athlon64, 2653 CK_Athlon64SSE3, 2654 CK_AthlonFX, 2655 CK_K8, 2656 CK_K8SSE3, 2657 CK_Opteron, 2658 CK_OpteronSSE3, 2659 CK_AMDFAM10, 2660 //@} 2661 2662 /// \name Bobcat 2663 /// Bobcat architecture processors. 2664 //@{ 2665 CK_BTVER1, 2666 CK_BTVER2, 2667 //@} 2668 2669 /// \name Bulldozer 2670 /// Bulldozer architecture processors. 2671 //@{ 2672 CK_BDVER1, 2673 CK_BDVER2, 2674 CK_BDVER3, 2675 CK_BDVER4, 2676 //@} 2677 2678 /// \name zen 2679 /// Zen architecture processors. 2680 //@{ 2681 CK_ZNVER1, 2682 //@} 2683 2684 /// This specification is deprecated and will be removed in the future. 2685 /// Users should prefer \see CK_K8. 2686 // FIXME: Warn on this when the CPU is set to it. 2687 //@{ 2688 CK_x86_64, 2689 //@} 2690 2691 /// \name Geode 2692 /// Geode processors. 2693 //@{ 2694 CK_Geode 2695 //@} 2696 } CPU = CK_Generic; 2697 2698 CPUKind getCPUKind(StringRef CPU) const { 2699 return llvm::StringSwitch<CPUKind>(CPU) 2700 .Case("i386", CK_i386) 2701 .Case("i486", CK_i486) 2702 .Case("winchip-c6", CK_WinChipC6) 2703 .Case("winchip2", CK_WinChip2) 2704 .Case("c3", CK_C3) 2705 .Case("i586", CK_i586) 2706 .Case("pentium", CK_Pentium) 2707 .Case("pentium-mmx", CK_PentiumMMX) 2708 .Case("i686", CK_i686) 2709 .Case("pentiumpro", CK_PentiumPro) 2710 .Case("pentium2", CK_Pentium2) 2711 .Case("pentium3", CK_Pentium3) 2712 .Case("pentium3m", CK_Pentium3M) 2713 .Case("pentium-m", CK_PentiumM) 2714 .Case("c3-2", CK_C3_2) 2715 .Case("yonah", CK_Yonah) 2716 .Case("pentium4", CK_Pentium4) 2717 .Case("pentium4m", CK_Pentium4M) 2718 .Case("prescott", CK_Prescott) 2719 .Case("nocona", CK_Nocona) 2720 .Case("core2", CK_Core2) 2721 .Case("penryn", CK_Penryn) 2722 .Case("bonnell", CK_Bonnell) 2723 .Case("atom", CK_Bonnell) // Legacy name. 2724 .Case("silvermont", CK_Silvermont) 2725 .Case("slm", CK_Silvermont) // Legacy name. 2726 .Case("nehalem", CK_Nehalem) 2727 .Case("corei7", CK_Nehalem) // Legacy name. 2728 .Case("westmere", CK_Westmere) 2729 .Case("sandybridge", CK_SandyBridge) 2730 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2731 .Case("ivybridge", CK_IvyBridge) 2732 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2733 .Case("haswell", CK_Haswell) 2734 .Case("core-avx2", CK_Haswell) // Legacy name. 2735 .Case("broadwell", CK_Broadwell) 2736 .Case("skylake", CK_SkylakeClient) 2737 .Case("skylake-avx512", CK_SkylakeServer) 2738 .Case("skx", CK_SkylakeServer) // Legacy name. 2739 .Case("cannonlake", CK_Cannonlake) 2740 .Case("knl", CK_KNL) 2741 .Case("lakemont", CK_Lakemont) 2742 .Case("k6", CK_K6) 2743 .Case("k6-2", CK_K6_2) 2744 .Case("k6-3", CK_K6_3) 2745 .Case("athlon", CK_Athlon) 2746 .Case("athlon-tbird", CK_AthlonThunderbird) 2747 .Case("athlon-4", CK_Athlon4) 2748 .Case("athlon-xp", CK_AthlonXP) 2749 .Case("athlon-mp", CK_AthlonMP) 2750 .Case("athlon64", CK_Athlon64) 2751 .Case("athlon64-sse3", CK_Athlon64SSE3) 2752 .Case("athlon-fx", CK_AthlonFX) 2753 .Case("k8", CK_K8) 2754 .Case("k8-sse3", CK_K8SSE3) 2755 .Case("opteron", CK_Opteron) 2756 .Case("opteron-sse3", CK_OpteronSSE3) 2757 .Case("barcelona", CK_AMDFAM10) 2758 .Case("amdfam10", CK_AMDFAM10) 2759 .Case("btver1", CK_BTVER1) 2760 .Case("btver2", CK_BTVER2) 2761 .Case("bdver1", CK_BDVER1) 2762 .Case("bdver2", CK_BDVER2) 2763 .Case("bdver3", CK_BDVER3) 2764 .Case("bdver4", CK_BDVER4) 2765 .Case("znver1", CK_ZNVER1) 2766 .Case("x86-64", CK_x86_64) 2767 .Case("geode", CK_Geode) 2768 .Default(CK_Generic); 2769 } 2770 2771 enum FPMathKind { 2772 FP_Default, 2773 FP_SSE, 2774 FP_387 2775 } FPMath = FP_Default; 2776 2777 public: 2778 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2779 : TargetInfo(Triple) { 2780 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2781 } 2782 unsigned getFloatEvalMethod() const override { 2783 // X87 evaluates with 80 bits "long double" precision. 2784 return SSELevel == NoSSE ? 2 : 0; 2785 } 2786 ArrayRef<const char *> getGCCRegNames() const override { 2787 return llvm::makeArrayRef(GCCRegNames); 2788 } 2789 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2790 return None; 2791 } 2792 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2793 return llvm::makeArrayRef(AddlRegNames); 2794 } 2795 bool validateCpuSupports(StringRef Name) const override; 2796 bool validateAsmConstraint(const char *&Name, 2797 TargetInfo::ConstraintInfo &info) const override; 2798 2799 bool validateGlobalRegisterVariable(StringRef RegName, 2800 unsigned RegSize, 2801 bool &HasSizeMismatch) const override { 2802 // esp and ebp are the only 32-bit registers the x86 backend can currently 2803 // handle. 2804 if (RegName.equals("esp") || RegName.equals("ebp")) { 2805 // Check that the register size is 32-bit. 2806 HasSizeMismatch = RegSize != 32; 2807 return true; 2808 } 2809 2810 return false; 2811 } 2812 2813 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2814 2815 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2816 2817 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2818 2819 std::string convertConstraint(const char *&Constraint) const override; 2820 const char *getClobbers() const override { 2821 return "~{dirflag},~{fpsr},~{flags}"; 2822 } 2823 2824 StringRef getConstraintRegister(const StringRef &Constraint, 2825 const StringRef &Expression) const override { 2826 StringRef::iterator I, E; 2827 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 2828 if (isalpha(*I)) 2829 break; 2830 } 2831 if (I == E) 2832 return ""; 2833 switch (*I) { 2834 // For the register constraints, return the matching register name 2835 case 'a': 2836 return "ax"; 2837 case 'b': 2838 return "bx"; 2839 case 'c': 2840 return "cx"; 2841 case 'd': 2842 return "dx"; 2843 case 'S': 2844 return "si"; 2845 case 'D': 2846 return "di"; 2847 // In case the constraint is 'r' we need to return Expression 2848 case 'r': 2849 return Expression; 2850 default: 2851 // Default value if there is no constraint for the register 2852 return ""; 2853 } 2854 return ""; 2855 } 2856 2857 void getTargetDefines(const LangOptions &Opts, 2858 MacroBuilder &Builder) const override; 2859 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2860 bool Enabled); 2861 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2862 bool Enabled); 2863 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2864 bool Enabled); 2865 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2866 StringRef Name, bool Enabled) const override { 2867 setFeatureEnabledImpl(Features, Name, Enabled); 2868 } 2869 // This exists purely to cut down on the number of virtual calls in 2870 // initFeatureMap which calls this repeatedly. 2871 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2872 StringRef Name, bool Enabled); 2873 bool 2874 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2875 StringRef CPU, 2876 const std::vector<std::string> &FeaturesVec) const override; 2877 bool hasFeature(StringRef Feature) const override; 2878 bool handleTargetFeatures(std::vector<std::string> &Features, 2879 DiagnosticsEngine &Diags) override; 2880 StringRef getABI() const override { 2881 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2882 return "avx512"; 2883 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2884 return "avx"; 2885 if (getTriple().getArch() == llvm::Triple::x86 && 2886 MMX3DNowLevel == NoMMX3DNow) 2887 return "no-mmx"; 2888 return ""; 2889 } 2890 bool setCPU(const std::string &Name) override { 2891 CPU = getCPUKind(Name); 2892 2893 // Perform any per-CPU checks necessary to determine if this CPU is 2894 // acceptable. 2895 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2896 // invalid without explaining *why*. 2897 switch (CPU) { 2898 case CK_Generic: 2899 // No processor selected! 2900 return false; 2901 2902 case CK_i386: 2903 case CK_i486: 2904 case CK_WinChipC6: 2905 case CK_WinChip2: 2906 case CK_C3: 2907 case CK_i586: 2908 case CK_Pentium: 2909 case CK_PentiumMMX: 2910 case CK_i686: 2911 case CK_PentiumPro: 2912 case CK_Pentium2: 2913 case CK_Pentium3: 2914 case CK_Pentium3M: 2915 case CK_PentiumM: 2916 case CK_Yonah: 2917 case CK_C3_2: 2918 case CK_Pentium4: 2919 case CK_Pentium4M: 2920 case CK_Lakemont: 2921 case CK_Prescott: 2922 case CK_K6: 2923 case CK_K6_2: 2924 case CK_K6_3: 2925 case CK_Athlon: 2926 case CK_AthlonThunderbird: 2927 case CK_Athlon4: 2928 case CK_AthlonXP: 2929 case CK_AthlonMP: 2930 case CK_Geode: 2931 // Only accept certain architectures when compiling in 32-bit mode. 2932 if (getTriple().getArch() != llvm::Triple::x86) 2933 return false; 2934 2935 // Fallthrough 2936 case CK_Nocona: 2937 case CK_Core2: 2938 case CK_Penryn: 2939 case CK_Bonnell: 2940 case CK_Silvermont: 2941 case CK_Nehalem: 2942 case CK_Westmere: 2943 case CK_SandyBridge: 2944 case CK_IvyBridge: 2945 case CK_Haswell: 2946 case CK_Broadwell: 2947 case CK_SkylakeClient: 2948 case CK_SkylakeServer: 2949 case CK_Cannonlake: 2950 case CK_KNL: 2951 case CK_Athlon64: 2952 case CK_Athlon64SSE3: 2953 case CK_AthlonFX: 2954 case CK_K8: 2955 case CK_K8SSE3: 2956 case CK_Opteron: 2957 case CK_OpteronSSE3: 2958 case CK_AMDFAM10: 2959 case CK_BTVER1: 2960 case CK_BTVER2: 2961 case CK_BDVER1: 2962 case CK_BDVER2: 2963 case CK_BDVER3: 2964 case CK_BDVER4: 2965 case CK_ZNVER1: 2966 case CK_x86_64: 2967 return true; 2968 } 2969 llvm_unreachable("Unhandled CPU kind"); 2970 } 2971 2972 bool setFPMath(StringRef Name) override; 2973 2974 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2975 // Most of the non-ARM calling conventions are i386 conventions. 2976 switch (CC) { 2977 case CC_X86ThisCall: 2978 case CC_X86FastCall: 2979 case CC_X86StdCall: 2980 case CC_X86VectorCall: 2981 case CC_X86RegCall: 2982 case CC_C: 2983 case CC_Swift: 2984 case CC_X86Pascal: 2985 case CC_IntelOclBicc: 2986 return CCCR_OK; 2987 default: 2988 return CCCR_Warning; 2989 } 2990 } 2991 2992 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2993 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2994 } 2995 2996 bool hasSjLjLowering() const override { 2997 return true; 2998 } 2999 3000 void setSupportedOpenCLOpts() override { 3001 getSupportedOpenCLOpts().supportAll(); 3002 } 3003 }; 3004 3005 bool X86TargetInfo::setFPMath(StringRef Name) { 3006 if (Name == "387") { 3007 FPMath = FP_387; 3008 return true; 3009 } 3010 if (Name == "sse") { 3011 FPMath = FP_SSE; 3012 return true; 3013 } 3014 return false; 3015 } 3016 3017 bool X86TargetInfo::initFeatureMap( 3018 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3019 const std::vector<std::string> &FeaturesVec) const { 3020 // FIXME: This *really* should not be here. 3021 // X86_64 always has SSE2. 3022 if (getTriple().getArch() == llvm::Triple::x86_64) 3023 setFeatureEnabledImpl(Features, "sse2", true); 3024 3025 const CPUKind Kind = getCPUKind(CPU); 3026 3027 // Enable X87 for all X86 processors but Lakemont. 3028 if (Kind != CK_Lakemont) 3029 setFeatureEnabledImpl(Features, "x87", true); 3030 3031 switch (Kind) { 3032 case CK_Generic: 3033 case CK_i386: 3034 case CK_i486: 3035 case CK_i586: 3036 case CK_Pentium: 3037 case CK_i686: 3038 case CK_PentiumPro: 3039 case CK_Lakemont: 3040 break; 3041 case CK_PentiumMMX: 3042 case CK_Pentium2: 3043 case CK_K6: 3044 case CK_WinChipC6: 3045 setFeatureEnabledImpl(Features, "mmx", true); 3046 break; 3047 case CK_Pentium3: 3048 case CK_Pentium3M: 3049 case CK_C3_2: 3050 setFeatureEnabledImpl(Features, "sse", true); 3051 setFeatureEnabledImpl(Features, "fxsr", true); 3052 break; 3053 case CK_PentiumM: 3054 case CK_Pentium4: 3055 case CK_Pentium4M: 3056 case CK_x86_64: 3057 setFeatureEnabledImpl(Features, "sse2", true); 3058 setFeatureEnabledImpl(Features, "fxsr", true); 3059 break; 3060 case CK_Yonah: 3061 case CK_Prescott: 3062 case CK_Nocona: 3063 setFeatureEnabledImpl(Features, "sse3", true); 3064 setFeatureEnabledImpl(Features, "fxsr", true); 3065 setFeatureEnabledImpl(Features, "cx16", true); 3066 break; 3067 case CK_Core2: 3068 case CK_Bonnell: 3069 setFeatureEnabledImpl(Features, "ssse3", true); 3070 setFeatureEnabledImpl(Features, "fxsr", true); 3071 setFeatureEnabledImpl(Features, "cx16", true); 3072 break; 3073 case CK_Penryn: 3074 setFeatureEnabledImpl(Features, "sse4.1", true); 3075 setFeatureEnabledImpl(Features, "fxsr", true); 3076 setFeatureEnabledImpl(Features, "cx16", true); 3077 break; 3078 case CK_Cannonlake: 3079 setFeatureEnabledImpl(Features, "avx512ifma", true); 3080 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3081 setFeatureEnabledImpl(Features, "sha", true); 3082 LLVM_FALLTHROUGH; 3083 case CK_SkylakeServer: 3084 setFeatureEnabledImpl(Features, "avx512f", true); 3085 setFeatureEnabledImpl(Features, "avx512cd", true); 3086 setFeatureEnabledImpl(Features, "avx512dq", true); 3087 setFeatureEnabledImpl(Features, "avx512bw", true); 3088 setFeatureEnabledImpl(Features, "avx512vl", true); 3089 setFeatureEnabledImpl(Features, "pku", true); 3090 setFeatureEnabledImpl(Features, "clwb", true); 3091 LLVM_FALLTHROUGH; 3092 case CK_SkylakeClient: 3093 setFeatureEnabledImpl(Features, "xsavec", true); 3094 setFeatureEnabledImpl(Features, "xsaves", true); 3095 setFeatureEnabledImpl(Features, "mpx", true); 3096 setFeatureEnabledImpl(Features, "sgx", true); 3097 setFeatureEnabledImpl(Features, "clflushopt", true); 3098 LLVM_FALLTHROUGH; 3099 case CK_Broadwell: 3100 setFeatureEnabledImpl(Features, "rdseed", true); 3101 setFeatureEnabledImpl(Features, "adx", true); 3102 LLVM_FALLTHROUGH; 3103 case CK_Haswell: 3104 setFeatureEnabledImpl(Features, "avx2", true); 3105 setFeatureEnabledImpl(Features, "lzcnt", true); 3106 setFeatureEnabledImpl(Features, "bmi", true); 3107 setFeatureEnabledImpl(Features, "bmi2", true); 3108 setFeatureEnabledImpl(Features, "rtm", true); 3109 setFeatureEnabledImpl(Features, "fma", true); 3110 setFeatureEnabledImpl(Features, "movbe", true); 3111 LLVM_FALLTHROUGH; 3112 case CK_IvyBridge: 3113 setFeatureEnabledImpl(Features, "rdrnd", true); 3114 setFeatureEnabledImpl(Features, "f16c", true); 3115 setFeatureEnabledImpl(Features, "fsgsbase", true); 3116 LLVM_FALLTHROUGH; 3117 case CK_SandyBridge: 3118 setFeatureEnabledImpl(Features, "avx", true); 3119 setFeatureEnabledImpl(Features, "xsave", true); 3120 setFeatureEnabledImpl(Features, "xsaveopt", true); 3121 LLVM_FALLTHROUGH; 3122 case CK_Westmere: 3123 case CK_Silvermont: 3124 setFeatureEnabledImpl(Features, "aes", true); 3125 setFeatureEnabledImpl(Features, "pclmul", true); 3126 LLVM_FALLTHROUGH; 3127 case CK_Nehalem: 3128 setFeatureEnabledImpl(Features, "sse4.2", true); 3129 setFeatureEnabledImpl(Features, "fxsr", true); 3130 setFeatureEnabledImpl(Features, "cx16", true); 3131 break; 3132 case CK_KNL: 3133 setFeatureEnabledImpl(Features, "avx512f", true); 3134 setFeatureEnabledImpl(Features, "avx512cd", true); 3135 setFeatureEnabledImpl(Features, "avx512er", true); 3136 setFeatureEnabledImpl(Features, "avx512pf", true); 3137 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3138 setFeatureEnabledImpl(Features, "fxsr", true); 3139 setFeatureEnabledImpl(Features, "rdseed", true); 3140 setFeatureEnabledImpl(Features, "adx", true); 3141 setFeatureEnabledImpl(Features, "lzcnt", true); 3142 setFeatureEnabledImpl(Features, "bmi", true); 3143 setFeatureEnabledImpl(Features, "bmi2", true); 3144 setFeatureEnabledImpl(Features, "rtm", true); 3145 setFeatureEnabledImpl(Features, "fma", true); 3146 setFeatureEnabledImpl(Features, "rdrnd", true); 3147 setFeatureEnabledImpl(Features, "f16c", true); 3148 setFeatureEnabledImpl(Features, "fsgsbase", true); 3149 setFeatureEnabledImpl(Features, "aes", true); 3150 setFeatureEnabledImpl(Features, "pclmul", true); 3151 setFeatureEnabledImpl(Features, "cx16", true); 3152 setFeatureEnabledImpl(Features, "xsaveopt", true); 3153 setFeatureEnabledImpl(Features, "xsave", true); 3154 setFeatureEnabledImpl(Features, "movbe", true); 3155 break; 3156 case CK_K6_2: 3157 case CK_K6_3: 3158 case CK_WinChip2: 3159 case CK_C3: 3160 setFeatureEnabledImpl(Features, "3dnow", true); 3161 break; 3162 case CK_Athlon: 3163 case CK_AthlonThunderbird: 3164 case CK_Geode: 3165 setFeatureEnabledImpl(Features, "3dnowa", true); 3166 break; 3167 case CK_Athlon4: 3168 case CK_AthlonXP: 3169 case CK_AthlonMP: 3170 setFeatureEnabledImpl(Features, "sse", true); 3171 setFeatureEnabledImpl(Features, "3dnowa", true); 3172 setFeatureEnabledImpl(Features, "fxsr", true); 3173 break; 3174 case CK_K8: 3175 case CK_Opteron: 3176 case CK_Athlon64: 3177 case CK_AthlonFX: 3178 setFeatureEnabledImpl(Features, "sse2", true); 3179 setFeatureEnabledImpl(Features, "3dnowa", true); 3180 setFeatureEnabledImpl(Features, "fxsr", true); 3181 break; 3182 case CK_AMDFAM10: 3183 setFeatureEnabledImpl(Features, "sse4a", true); 3184 setFeatureEnabledImpl(Features, "lzcnt", true); 3185 setFeatureEnabledImpl(Features, "popcnt", true); 3186 LLVM_FALLTHROUGH; 3187 case CK_K8SSE3: 3188 case CK_OpteronSSE3: 3189 case CK_Athlon64SSE3: 3190 setFeatureEnabledImpl(Features, "sse3", true); 3191 setFeatureEnabledImpl(Features, "3dnowa", true); 3192 setFeatureEnabledImpl(Features, "fxsr", true); 3193 break; 3194 case CK_BTVER2: 3195 setFeatureEnabledImpl(Features, "avx", true); 3196 setFeatureEnabledImpl(Features, "aes", true); 3197 setFeatureEnabledImpl(Features, "pclmul", true); 3198 setFeatureEnabledImpl(Features, "bmi", true); 3199 setFeatureEnabledImpl(Features, "f16c", true); 3200 setFeatureEnabledImpl(Features, "xsaveopt", true); 3201 LLVM_FALLTHROUGH; 3202 case CK_BTVER1: 3203 setFeatureEnabledImpl(Features, "ssse3", true); 3204 setFeatureEnabledImpl(Features, "sse4a", true); 3205 setFeatureEnabledImpl(Features, "lzcnt", true); 3206 setFeatureEnabledImpl(Features, "popcnt", true); 3207 setFeatureEnabledImpl(Features, "prfchw", true); 3208 setFeatureEnabledImpl(Features, "cx16", true); 3209 setFeatureEnabledImpl(Features, "fxsr", true); 3210 break; 3211 case CK_ZNVER1: 3212 setFeatureEnabledImpl(Features, "adx", true); 3213 setFeatureEnabledImpl(Features, "aes", true); 3214 setFeatureEnabledImpl(Features, "avx2", true); 3215 setFeatureEnabledImpl(Features, "bmi", true); 3216 setFeatureEnabledImpl(Features, "bmi2", true); 3217 setFeatureEnabledImpl(Features, "clflushopt", true); 3218 setFeatureEnabledImpl(Features, "clzero", true); 3219 setFeatureEnabledImpl(Features, "cx16", true); 3220 setFeatureEnabledImpl(Features, "f16c", true); 3221 setFeatureEnabledImpl(Features, "fma", true); 3222 setFeatureEnabledImpl(Features, "fsgsbase", true); 3223 setFeatureEnabledImpl(Features, "fxsr", true); 3224 setFeatureEnabledImpl(Features, "lzcnt", true); 3225 setFeatureEnabledImpl(Features, "mwaitx", true); 3226 setFeatureEnabledImpl(Features, "movbe", true); 3227 setFeatureEnabledImpl(Features, "pclmul", true); 3228 setFeatureEnabledImpl(Features, "popcnt", true); 3229 setFeatureEnabledImpl(Features, "prfchw", true); 3230 setFeatureEnabledImpl(Features, "rdrnd", true); 3231 setFeatureEnabledImpl(Features, "rdseed", true); 3232 setFeatureEnabledImpl(Features, "sha", true); 3233 setFeatureEnabledImpl(Features, "sse4a", true); 3234 setFeatureEnabledImpl(Features, "xsave", true); 3235 setFeatureEnabledImpl(Features, "xsavec", true); 3236 setFeatureEnabledImpl(Features, "xsaveopt", true); 3237 setFeatureEnabledImpl(Features, "xsaves", true); 3238 break; 3239 case CK_BDVER4: 3240 setFeatureEnabledImpl(Features, "avx2", true); 3241 setFeatureEnabledImpl(Features, "bmi2", true); 3242 setFeatureEnabledImpl(Features, "mwaitx", true); 3243 LLVM_FALLTHROUGH; 3244 case CK_BDVER3: 3245 setFeatureEnabledImpl(Features, "fsgsbase", true); 3246 setFeatureEnabledImpl(Features, "xsaveopt", true); 3247 LLVM_FALLTHROUGH; 3248 case CK_BDVER2: 3249 setFeatureEnabledImpl(Features, "bmi", true); 3250 setFeatureEnabledImpl(Features, "fma", true); 3251 setFeatureEnabledImpl(Features, "f16c", true); 3252 setFeatureEnabledImpl(Features, "tbm", true); 3253 LLVM_FALLTHROUGH; 3254 case CK_BDVER1: 3255 // xop implies avx, sse4a and fma4. 3256 setFeatureEnabledImpl(Features, "xop", true); 3257 setFeatureEnabledImpl(Features, "lzcnt", true); 3258 setFeatureEnabledImpl(Features, "aes", true); 3259 setFeatureEnabledImpl(Features, "pclmul", true); 3260 setFeatureEnabledImpl(Features, "prfchw", true); 3261 setFeatureEnabledImpl(Features, "cx16", true); 3262 setFeatureEnabledImpl(Features, "fxsr", true); 3263 setFeatureEnabledImpl(Features, "xsave", true); 3264 break; 3265 } 3266 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3267 return false; 3268 3269 // Can't do this earlier because we need to be able to explicitly enable 3270 // or disable these features and the things that they depend upon. 3271 3272 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3273 auto I = Features.find("sse4.2"); 3274 if (I != Features.end() && I->getValue() && 3275 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3276 FeaturesVec.end()) 3277 Features["popcnt"] = true; 3278 3279 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3280 I = Features.find("3dnow"); 3281 if (I != Features.end() && I->getValue() && 3282 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3283 FeaturesVec.end()) 3284 Features["prfchw"] = true; 3285 3286 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3287 // then enable MMX. 3288 I = Features.find("sse"); 3289 if (I != Features.end() && I->getValue() && 3290 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3291 FeaturesVec.end()) 3292 Features["mmx"] = true; 3293 3294 return true; 3295 } 3296 3297 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3298 X86SSEEnum Level, bool Enabled) { 3299 if (Enabled) { 3300 switch (Level) { 3301 case AVX512F: 3302 Features["avx512f"] = true; 3303 case AVX2: 3304 Features["avx2"] = true; 3305 case AVX: 3306 Features["avx"] = true; 3307 Features["xsave"] = true; 3308 case SSE42: 3309 Features["sse4.2"] = true; 3310 case SSE41: 3311 Features["sse4.1"] = true; 3312 case SSSE3: 3313 Features["ssse3"] = true; 3314 case SSE3: 3315 Features["sse3"] = true; 3316 case SSE2: 3317 Features["sse2"] = true; 3318 case SSE1: 3319 Features["sse"] = true; 3320 case NoSSE: 3321 break; 3322 } 3323 return; 3324 } 3325 3326 switch (Level) { 3327 case NoSSE: 3328 case SSE1: 3329 Features["sse"] = false; 3330 case SSE2: 3331 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3332 Features["sha"] = false; 3333 case SSE3: 3334 Features["sse3"] = false; 3335 setXOPLevel(Features, NoXOP, false); 3336 case SSSE3: 3337 Features["ssse3"] = false; 3338 case SSE41: 3339 Features["sse4.1"] = false; 3340 case SSE42: 3341 Features["sse4.2"] = false; 3342 case AVX: 3343 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3344 Features["xsaveopt"] = false; 3345 setXOPLevel(Features, FMA4, false); 3346 case AVX2: 3347 Features["avx2"] = false; 3348 case AVX512F: 3349 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3350 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3351 Features["avx512vl"] = Features["avx512vbmi"] = 3352 Features["avx512ifma"] = false; 3353 } 3354 } 3355 3356 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3357 MMX3DNowEnum Level, bool Enabled) { 3358 if (Enabled) { 3359 switch (Level) { 3360 case AMD3DNowAthlon: 3361 Features["3dnowa"] = true; 3362 case AMD3DNow: 3363 Features["3dnow"] = true; 3364 case MMX: 3365 Features["mmx"] = true; 3366 case NoMMX3DNow: 3367 break; 3368 } 3369 return; 3370 } 3371 3372 switch (Level) { 3373 case NoMMX3DNow: 3374 case MMX: 3375 Features["mmx"] = false; 3376 case AMD3DNow: 3377 Features["3dnow"] = false; 3378 case AMD3DNowAthlon: 3379 Features["3dnowa"] = false; 3380 } 3381 } 3382 3383 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3384 bool Enabled) { 3385 if (Enabled) { 3386 switch (Level) { 3387 case XOP: 3388 Features["xop"] = true; 3389 case FMA4: 3390 Features["fma4"] = true; 3391 setSSELevel(Features, AVX, true); 3392 case SSE4A: 3393 Features["sse4a"] = true; 3394 setSSELevel(Features, SSE3, true); 3395 case NoXOP: 3396 break; 3397 } 3398 return; 3399 } 3400 3401 switch (Level) { 3402 case NoXOP: 3403 case SSE4A: 3404 Features["sse4a"] = false; 3405 case FMA4: 3406 Features["fma4"] = false; 3407 case XOP: 3408 Features["xop"] = false; 3409 } 3410 } 3411 3412 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3413 StringRef Name, bool Enabled) { 3414 // This is a bit of a hack to deal with the sse4 target feature when used 3415 // as part of the target attribute. We handle sse4 correctly everywhere 3416 // else. See below for more information on how we handle the sse4 options. 3417 if (Name != "sse4") 3418 Features[Name] = Enabled; 3419 3420 if (Name == "mmx") { 3421 setMMXLevel(Features, MMX, Enabled); 3422 } else if (Name == "sse") { 3423 setSSELevel(Features, SSE1, Enabled); 3424 } else if (Name == "sse2") { 3425 setSSELevel(Features, SSE2, Enabled); 3426 } else if (Name == "sse3") { 3427 setSSELevel(Features, SSE3, Enabled); 3428 } else if (Name == "ssse3") { 3429 setSSELevel(Features, SSSE3, Enabled); 3430 } else if (Name == "sse4.2") { 3431 setSSELevel(Features, SSE42, Enabled); 3432 } else if (Name == "sse4.1") { 3433 setSSELevel(Features, SSE41, Enabled); 3434 } else if (Name == "3dnow") { 3435 setMMXLevel(Features, AMD3DNow, Enabled); 3436 } else if (Name == "3dnowa") { 3437 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3438 } else if (Name == "aes") { 3439 if (Enabled) 3440 setSSELevel(Features, SSE2, Enabled); 3441 } else if (Name == "pclmul") { 3442 if (Enabled) 3443 setSSELevel(Features, SSE2, Enabled); 3444 } else if (Name == "avx") { 3445 setSSELevel(Features, AVX, Enabled); 3446 } else if (Name == "avx2") { 3447 setSSELevel(Features, AVX2, Enabled); 3448 } else if (Name == "avx512f") { 3449 setSSELevel(Features, AVX512F, Enabled); 3450 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3451 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3452 Name == "avx512vbmi" || Name == "avx512ifma") { 3453 if (Enabled) 3454 setSSELevel(Features, AVX512F, Enabled); 3455 // Enable BWI instruction if VBMI is being enabled. 3456 if (Name == "avx512vbmi" && Enabled) 3457 Features["avx512bw"] = true; 3458 // Also disable VBMI if BWI is being disabled. 3459 if (Name == "avx512bw" && !Enabled) 3460 Features["avx512vbmi"] = false; 3461 } else if (Name == "fma") { 3462 if (Enabled) 3463 setSSELevel(Features, AVX, Enabled); 3464 } else if (Name == "fma4") { 3465 setXOPLevel(Features, FMA4, Enabled); 3466 } else if (Name == "xop") { 3467 setXOPLevel(Features, XOP, Enabled); 3468 } else if (Name == "sse4a") { 3469 setXOPLevel(Features, SSE4A, Enabled); 3470 } else if (Name == "f16c") { 3471 if (Enabled) 3472 setSSELevel(Features, AVX, Enabled); 3473 } else if (Name == "sha") { 3474 if (Enabled) 3475 setSSELevel(Features, SSE2, Enabled); 3476 } else if (Name == "sse4") { 3477 // We can get here via the __target__ attribute since that's not controlled 3478 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3479 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3480 // disabled. 3481 if (Enabled) 3482 setSSELevel(Features, SSE42, Enabled); 3483 else 3484 setSSELevel(Features, SSE41, Enabled); 3485 } else if (Name == "xsave") { 3486 if (!Enabled) 3487 Features["xsaveopt"] = false; 3488 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3489 if (Enabled) 3490 Features["xsave"] = true; 3491 } 3492 } 3493 3494 /// handleTargetFeatures - Perform initialization based on the user 3495 /// configured set of features. 3496 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3497 DiagnosticsEngine &Diags) { 3498 for (const auto &Feature : Features) { 3499 if (Feature[0] != '+') 3500 continue; 3501 3502 if (Feature == "+aes") { 3503 HasAES = true; 3504 } else if (Feature == "+pclmul") { 3505 HasPCLMUL = true; 3506 } else if (Feature == "+lzcnt") { 3507 HasLZCNT = true; 3508 } else if (Feature == "+rdrnd") { 3509 HasRDRND = true; 3510 } else if (Feature == "+fsgsbase") { 3511 HasFSGSBASE = true; 3512 } else if (Feature == "+bmi") { 3513 HasBMI = true; 3514 } else if (Feature == "+bmi2") { 3515 HasBMI2 = true; 3516 } else if (Feature == "+popcnt") { 3517 HasPOPCNT = true; 3518 } else if (Feature == "+rtm") { 3519 HasRTM = true; 3520 } else if (Feature == "+prfchw") { 3521 HasPRFCHW = true; 3522 } else if (Feature == "+rdseed") { 3523 HasRDSEED = true; 3524 } else if (Feature == "+adx") { 3525 HasADX = true; 3526 } else if (Feature == "+tbm") { 3527 HasTBM = true; 3528 } else if (Feature == "+fma") { 3529 HasFMA = true; 3530 } else if (Feature == "+f16c") { 3531 HasF16C = true; 3532 } else if (Feature == "+avx512cd") { 3533 HasAVX512CD = true; 3534 } else if (Feature == "+avx512er") { 3535 HasAVX512ER = true; 3536 } else if (Feature == "+avx512pf") { 3537 HasAVX512PF = true; 3538 } else if (Feature == "+avx512dq") { 3539 HasAVX512DQ = true; 3540 } else if (Feature == "+avx512bw") { 3541 HasAVX512BW = true; 3542 } else if (Feature == "+avx512vl") { 3543 HasAVX512VL = true; 3544 } else if (Feature == "+avx512vbmi") { 3545 HasAVX512VBMI = true; 3546 } else if (Feature == "+avx512ifma") { 3547 HasAVX512IFMA = true; 3548 } else if (Feature == "+sha") { 3549 HasSHA = true; 3550 } else if (Feature == "+mpx") { 3551 HasMPX = true; 3552 } else if (Feature == "+movbe") { 3553 HasMOVBE = true; 3554 } else if (Feature == "+sgx") { 3555 HasSGX = true; 3556 } else if (Feature == "+cx16") { 3557 HasCX16 = true; 3558 } else if (Feature == "+fxsr") { 3559 HasFXSR = true; 3560 } else if (Feature == "+xsave") { 3561 HasXSAVE = true; 3562 } else if (Feature == "+xsaveopt") { 3563 HasXSAVEOPT = true; 3564 } else if (Feature == "+xsavec") { 3565 HasXSAVEC = true; 3566 } else if (Feature == "+xsaves") { 3567 HasXSAVES = true; 3568 } else if (Feature == "+mwaitx") { 3569 HasMWAITX = true; 3570 } else if (Feature == "+pku") { 3571 HasPKU = true; 3572 } else if (Feature == "+clflushopt") { 3573 HasCLFLUSHOPT = true; 3574 } else if (Feature == "+clwb") { 3575 HasCLWB = true; 3576 } else if (Feature == "+prefetchwt1") { 3577 HasPREFETCHWT1 = true; 3578 } else if (Feature == "+clzero") { 3579 HasCLZERO = true; 3580 } 3581 3582 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3583 .Case("+avx512f", AVX512F) 3584 .Case("+avx2", AVX2) 3585 .Case("+avx", AVX) 3586 .Case("+sse4.2", SSE42) 3587 .Case("+sse4.1", SSE41) 3588 .Case("+ssse3", SSSE3) 3589 .Case("+sse3", SSE3) 3590 .Case("+sse2", SSE2) 3591 .Case("+sse", SSE1) 3592 .Default(NoSSE); 3593 SSELevel = std::max(SSELevel, Level); 3594 3595 MMX3DNowEnum ThreeDNowLevel = 3596 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3597 .Case("+3dnowa", AMD3DNowAthlon) 3598 .Case("+3dnow", AMD3DNow) 3599 .Case("+mmx", MMX) 3600 .Default(NoMMX3DNow); 3601 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3602 3603 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3604 .Case("+xop", XOP) 3605 .Case("+fma4", FMA4) 3606 .Case("+sse4a", SSE4A) 3607 .Default(NoXOP); 3608 XOPLevel = std::max(XOPLevel, XLevel); 3609 } 3610 3611 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3612 // matches the selected sse level. 3613 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3614 (FPMath == FP_387 && SSELevel >= SSE1)) { 3615 Diags.Report(diag::err_target_unsupported_fpmath) << 3616 (FPMath == FP_SSE ? "sse" : "387"); 3617 return false; 3618 } 3619 3620 SimdDefaultAlign = 3621 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3622 return true; 3623 } 3624 3625 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3626 /// definitions for this particular subtarget. 3627 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3628 MacroBuilder &Builder) const { 3629 // Target identification. 3630 if (getTriple().getArch() == llvm::Triple::x86_64) { 3631 Builder.defineMacro("__amd64__"); 3632 Builder.defineMacro("__amd64"); 3633 Builder.defineMacro("__x86_64"); 3634 Builder.defineMacro("__x86_64__"); 3635 if (getTriple().getArchName() == "x86_64h") { 3636 Builder.defineMacro("__x86_64h"); 3637 Builder.defineMacro("__x86_64h__"); 3638 } 3639 } else { 3640 DefineStd(Builder, "i386", Opts); 3641 } 3642 3643 // Subtarget options. 3644 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3645 // truly should be based on -mtune options. 3646 switch (CPU) { 3647 case CK_Generic: 3648 break; 3649 case CK_i386: 3650 // The rest are coming from the i386 define above. 3651 Builder.defineMacro("__tune_i386__"); 3652 break; 3653 case CK_i486: 3654 case CK_WinChipC6: 3655 case CK_WinChip2: 3656 case CK_C3: 3657 defineCPUMacros(Builder, "i486"); 3658 break; 3659 case CK_PentiumMMX: 3660 Builder.defineMacro("__pentium_mmx__"); 3661 Builder.defineMacro("__tune_pentium_mmx__"); 3662 // Fallthrough 3663 case CK_i586: 3664 case CK_Pentium: 3665 defineCPUMacros(Builder, "i586"); 3666 defineCPUMacros(Builder, "pentium"); 3667 break; 3668 case CK_Pentium3: 3669 case CK_Pentium3M: 3670 case CK_PentiumM: 3671 Builder.defineMacro("__tune_pentium3__"); 3672 // Fallthrough 3673 case CK_Pentium2: 3674 case CK_C3_2: 3675 Builder.defineMacro("__tune_pentium2__"); 3676 // Fallthrough 3677 case CK_PentiumPro: 3678 Builder.defineMacro("__tune_i686__"); 3679 Builder.defineMacro("__tune_pentiumpro__"); 3680 // Fallthrough 3681 case CK_i686: 3682 Builder.defineMacro("__i686"); 3683 Builder.defineMacro("__i686__"); 3684 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3685 Builder.defineMacro("__pentiumpro"); 3686 Builder.defineMacro("__pentiumpro__"); 3687 break; 3688 case CK_Pentium4: 3689 case CK_Pentium4M: 3690 defineCPUMacros(Builder, "pentium4"); 3691 break; 3692 case CK_Yonah: 3693 case CK_Prescott: 3694 case CK_Nocona: 3695 defineCPUMacros(Builder, "nocona"); 3696 break; 3697 case CK_Core2: 3698 case CK_Penryn: 3699 defineCPUMacros(Builder, "core2"); 3700 break; 3701 case CK_Bonnell: 3702 defineCPUMacros(Builder, "atom"); 3703 break; 3704 case CK_Silvermont: 3705 defineCPUMacros(Builder, "slm"); 3706 break; 3707 case CK_Nehalem: 3708 case CK_Westmere: 3709 case CK_SandyBridge: 3710 case CK_IvyBridge: 3711 case CK_Haswell: 3712 case CK_Broadwell: 3713 case CK_SkylakeClient: 3714 // FIXME: Historically, we defined this legacy name, it would be nice to 3715 // remove it at some point. We've never exposed fine-grained names for 3716 // recent primary x86 CPUs, and we should keep it that way. 3717 defineCPUMacros(Builder, "corei7"); 3718 break; 3719 case CK_SkylakeServer: 3720 defineCPUMacros(Builder, "skx"); 3721 break; 3722 case CK_Cannonlake: 3723 break; 3724 case CK_KNL: 3725 defineCPUMacros(Builder, "knl"); 3726 break; 3727 case CK_Lakemont: 3728 Builder.defineMacro("__tune_lakemont__"); 3729 break; 3730 case CK_K6_2: 3731 Builder.defineMacro("__k6_2__"); 3732 Builder.defineMacro("__tune_k6_2__"); 3733 // Fallthrough 3734 case CK_K6_3: 3735 if (CPU != CK_K6_2) { // In case of fallthrough 3736 // FIXME: GCC may be enabling these in cases where some other k6 3737 // architecture is specified but -m3dnow is explicitly provided. The 3738 // exact semantics need to be determined and emulated here. 3739 Builder.defineMacro("__k6_3__"); 3740 Builder.defineMacro("__tune_k6_3__"); 3741 } 3742 // Fallthrough 3743 case CK_K6: 3744 defineCPUMacros(Builder, "k6"); 3745 break; 3746 case CK_Athlon: 3747 case CK_AthlonThunderbird: 3748 case CK_Athlon4: 3749 case CK_AthlonXP: 3750 case CK_AthlonMP: 3751 defineCPUMacros(Builder, "athlon"); 3752 if (SSELevel != NoSSE) { 3753 Builder.defineMacro("__athlon_sse__"); 3754 Builder.defineMacro("__tune_athlon_sse__"); 3755 } 3756 break; 3757 case CK_K8: 3758 case CK_K8SSE3: 3759 case CK_x86_64: 3760 case CK_Opteron: 3761 case CK_OpteronSSE3: 3762 case CK_Athlon64: 3763 case CK_Athlon64SSE3: 3764 case CK_AthlonFX: 3765 defineCPUMacros(Builder, "k8"); 3766 break; 3767 case CK_AMDFAM10: 3768 defineCPUMacros(Builder, "amdfam10"); 3769 break; 3770 case CK_BTVER1: 3771 defineCPUMacros(Builder, "btver1"); 3772 break; 3773 case CK_BTVER2: 3774 defineCPUMacros(Builder, "btver2"); 3775 break; 3776 case CK_BDVER1: 3777 defineCPUMacros(Builder, "bdver1"); 3778 break; 3779 case CK_BDVER2: 3780 defineCPUMacros(Builder, "bdver2"); 3781 break; 3782 case CK_BDVER3: 3783 defineCPUMacros(Builder, "bdver3"); 3784 break; 3785 case CK_BDVER4: 3786 defineCPUMacros(Builder, "bdver4"); 3787 break; 3788 case CK_ZNVER1: 3789 defineCPUMacros(Builder, "znver1"); 3790 break; 3791 case CK_Geode: 3792 defineCPUMacros(Builder, "geode"); 3793 break; 3794 } 3795 3796 // Target properties. 3797 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3798 3799 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3800 // functions in glibc header files that use FP Stack inline asm which the 3801 // backend can't deal with (PR879). 3802 Builder.defineMacro("__NO_MATH_INLINES"); 3803 3804 if (HasAES) 3805 Builder.defineMacro("__AES__"); 3806 3807 if (HasPCLMUL) 3808 Builder.defineMacro("__PCLMUL__"); 3809 3810 if (HasLZCNT) 3811 Builder.defineMacro("__LZCNT__"); 3812 3813 if (HasRDRND) 3814 Builder.defineMacro("__RDRND__"); 3815 3816 if (HasFSGSBASE) 3817 Builder.defineMacro("__FSGSBASE__"); 3818 3819 if (HasBMI) 3820 Builder.defineMacro("__BMI__"); 3821 3822 if (HasBMI2) 3823 Builder.defineMacro("__BMI2__"); 3824 3825 if (HasPOPCNT) 3826 Builder.defineMacro("__POPCNT__"); 3827 3828 if (HasRTM) 3829 Builder.defineMacro("__RTM__"); 3830 3831 if (HasPRFCHW) 3832 Builder.defineMacro("__PRFCHW__"); 3833 3834 if (HasRDSEED) 3835 Builder.defineMacro("__RDSEED__"); 3836 3837 if (HasADX) 3838 Builder.defineMacro("__ADX__"); 3839 3840 if (HasTBM) 3841 Builder.defineMacro("__TBM__"); 3842 3843 if (HasMWAITX) 3844 Builder.defineMacro("__MWAITX__"); 3845 3846 switch (XOPLevel) { 3847 case XOP: 3848 Builder.defineMacro("__XOP__"); 3849 case FMA4: 3850 Builder.defineMacro("__FMA4__"); 3851 case SSE4A: 3852 Builder.defineMacro("__SSE4A__"); 3853 case NoXOP: 3854 break; 3855 } 3856 3857 if (HasFMA) 3858 Builder.defineMacro("__FMA__"); 3859 3860 if (HasF16C) 3861 Builder.defineMacro("__F16C__"); 3862 3863 if (HasAVX512CD) 3864 Builder.defineMacro("__AVX512CD__"); 3865 if (HasAVX512ER) 3866 Builder.defineMacro("__AVX512ER__"); 3867 if (HasAVX512PF) 3868 Builder.defineMacro("__AVX512PF__"); 3869 if (HasAVX512DQ) 3870 Builder.defineMacro("__AVX512DQ__"); 3871 if (HasAVX512BW) 3872 Builder.defineMacro("__AVX512BW__"); 3873 if (HasAVX512VL) 3874 Builder.defineMacro("__AVX512VL__"); 3875 if (HasAVX512VBMI) 3876 Builder.defineMacro("__AVX512VBMI__"); 3877 if (HasAVX512IFMA) 3878 Builder.defineMacro("__AVX512IFMA__"); 3879 3880 if (HasSHA) 3881 Builder.defineMacro("__SHA__"); 3882 3883 if (HasFXSR) 3884 Builder.defineMacro("__FXSR__"); 3885 if (HasXSAVE) 3886 Builder.defineMacro("__XSAVE__"); 3887 if (HasXSAVEOPT) 3888 Builder.defineMacro("__XSAVEOPT__"); 3889 if (HasXSAVEC) 3890 Builder.defineMacro("__XSAVEC__"); 3891 if (HasXSAVES) 3892 Builder.defineMacro("__XSAVES__"); 3893 if (HasPKU) 3894 Builder.defineMacro("__PKU__"); 3895 if (HasCX16) 3896 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3897 if (HasCLFLUSHOPT) 3898 Builder.defineMacro("__CLFLUSHOPT__"); 3899 if (HasCLWB) 3900 Builder.defineMacro("__CLWB__"); 3901 if (HasMPX) 3902 Builder.defineMacro("__MPX__"); 3903 if (HasSGX) 3904 Builder.defineMacro("__SGX__"); 3905 if (HasPREFETCHWT1) 3906 Builder.defineMacro("__PREFETCHWT1__"); 3907 if (HasCLZERO) 3908 Builder.defineMacro("__CLZERO__"); 3909 3910 // Each case falls through to the previous one here. 3911 switch (SSELevel) { 3912 case AVX512F: 3913 Builder.defineMacro("__AVX512F__"); 3914 case AVX2: 3915 Builder.defineMacro("__AVX2__"); 3916 case AVX: 3917 Builder.defineMacro("__AVX__"); 3918 case SSE42: 3919 Builder.defineMacro("__SSE4_2__"); 3920 case SSE41: 3921 Builder.defineMacro("__SSE4_1__"); 3922 case SSSE3: 3923 Builder.defineMacro("__SSSE3__"); 3924 case SSE3: 3925 Builder.defineMacro("__SSE3__"); 3926 case SSE2: 3927 Builder.defineMacro("__SSE2__"); 3928 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3929 case SSE1: 3930 Builder.defineMacro("__SSE__"); 3931 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3932 case NoSSE: 3933 break; 3934 } 3935 3936 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3937 switch (SSELevel) { 3938 case AVX512F: 3939 case AVX2: 3940 case AVX: 3941 case SSE42: 3942 case SSE41: 3943 case SSSE3: 3944 case SSE3: 3945 case SSE2: 3946 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3947 break; 3948 case SSE1: 3949 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3950 break; 3951 default: 3952 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3953 } 3954 } 3955 3956 // Each case falls through to the previous one here. 3957 switch (MMX3DNowLevel) { 3958 case AMD3DNowAthlon: 3959 Builder.defineMacro("__3dNOW_A__"); 3960 case AMD3DNow: 3961 Builder.defineMacro("__3dNOW__"); 3962 case MMX: 3963 Builder.defineMacro("__MMX__"); 3964 case NoMMX3DNow: 3965 break; 3966 } 3967 3968 if (CPU >= CK_i486) { 3969 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3970 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3971 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3972 } 3973 if (CPU >= CK_i586) 3974 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3975 } 3976 3977 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3978 return llvm::StringSwitch<bool>(Feature) 3979 .Case("aes", HasAES) 3980 .Case("avx", SSELevel >= AVX) 3981 .Case("avx2", SSELevel >= AVX2) 3982 .Case("avx512f", SSELevel >= AVX512F) 3983 .Case("avx512cd", HasAVX512CD) 3984 .Case("avx512er", HasAVX512ER) 3985 .Case("avx512pf", HasAVX512PF) 3986 .Case("avx512dq", HasAVX512DQ) 3987 .Case("avx512bw", HasAVX512BW) 3988 .Case("avx512vl", HasAVX512VL) 3989 .Case("avx512vbmi", HasAVX512VBMI) 3990 .Case("avx512ifma", HasAVX512IFMA) 3991 .Case("bmi", HasBMI) 3992 .Case("bmi2", HasBMI2) 3993 .Case("clflushopt", HasCLFLUSHOPT) 3994 .Case("clwb", HasCLWB) 3995 .Case("clzero", HasCLZERO) 3996 .Case("cx16", HasCX16) 3997 .Case("f16c", HasF16C) 3998 .Case("fma", HasFMA) 3999 .Case("fma4", XOPLevel >= FMA4) 4000 .Case("fsgsbase", HasFSGSBASE) 4001 .Case("fxsr", HasFXSR) 4002 .Case("lzcnt", HasLZCNT) 4003 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4004 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4005 .Case("mmx", MMX3DNowLevel >= MMX) 4006 .Case("movbe", HasMOVBE) 4007 .Case("mpx", HasMPX) 4008 .Case("pclmul", HasPCLMUL) 4009 .Case("pku", HasPKU) 4010 .Case("popcnt", HasPOPCNT) 4011 .Case("prefetchwt1", HasPREFETCHWT1) 4012 .Case("prfchw", HasPRFCHW) 4013 .Case("rdrnd", HasRDRND) 4014 .Case("rdseed", HasRDSEED) 4015 .Case("rtm", HasRTM) 4016 .Case("sgx", HasSGX) 4017 .Case("sha", HasSHA) 4018 .Case("sse", SSELevel >= SSE1) 4019 .Case("sse2", SSELevel >= SSE2) 4020 .Case("sse3", SSELevel >= SSE3) 4021 .Case("ssse3", SSELevel >= SSSE3) 4022 .Case("sse4.1", SSELevel >= SSE41) 4023 .Case("sse4.2", SSELevel >= SSE42) 4024 .Case("sse4a", XOPLevel >= SSE4A) 4025 .Case("tbm", HasTBM) 4026 .Case("x86", true) 4027 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4028 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4029 .Case("xop", XOPLevel >= XOP) 4030 .Case("xsave", HasXSAVE) 4031 .Case("xsavec", HasXSAVEC) 4032 .Case("xsaves", HasXSAVES) 4033 .Case("xsaveopt", HasXSAVEOPT) 4034 .Default(false); 4035 } 4036 4037 // We can't use a generic validation scheme for the features accepted here 4038 // versus subtarget features accepted in the target attribute because the 4039 // bitfield structure that's initialized in the runtime only supports the 4040 // below currently rather than the full range of subtarget features. (See 4041 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4042 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4043 return llvm::StringSwitch<bool>(FeatureStr) 4044 .Case("cmov", true) 4045 .Case("mmx", true) 4046 .Case("popcnt", true) 4047 .Case("sse", true) 4048 .Case("sse2", true) 4049 .Case("sse3", true) 4050 .Case("ssse3", true) 4051 .Case("sse4.1", true) 4052 .Case("sse4.2", true) 4053 .Case("avx", true) 4054 .Case("avx2", true) 4055 .Case("sse4a", true) 4056 .Case("fma4", true) 4057 .Case("xop", true) 4058 .Case("fma", true) 4059 .Case("avx512f", true) 4060 .Case("bmi", true) 4061 .Case("bmi2", true) 4062 .Case("aes", true) 4063 .Case("pclmul", true) 4064 .Case("avx512vl", true) 4065 .Case("avx512bw", true) 4066 .Case("avx512dq", true) 4067 .Case("avx512cd", true) 4068 .Case("avx512er", true) 4069 .Case("avx512pf", true) 4070 .Case("avx512vbmi", true) 4071 .Case("avx512ifma", true) 4072 .Default(false); 4073 } 4074 4075 bool 4076 X86TargetInfo::validateAsmConstraint(const char *&Name, 4077 TargetInfo::ConstraintInfo &Info) const { 4078 switch (*Name) { 4079 default: return false; 4080 // Constant constraints. 4081 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4082 // instructions. 4083 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4084 // x86_64 instructions. 4085 case 's': 4086 Info.setRequiresImmediate(); 4087 return true; 4088 case 'I': 4089 Info.setRequiresImmediate(0, 31); 4090 return true; 4091 case 'J': 4092 Info.setRequiresImmediate(0, 63); 4093 return true; 4094 case 'K': 4095 Info.setRequiresImmediate(-128, 127); 4096 return true; 4097 case 'L': 4098 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4099 return true; 4100 case 'M': 4101 Info.setRequiresImmediate(0, 3); 4102 return true; 4103 case 'N': 4104 Info.setRequiresImmediate(0, 255); 4105 return true; 4106 case 'O': 4107 Info.setRequiresImmediate(0, 127); 4108 return true; 4109 // Register constraints. 4110 case 'Y': // 'Y' is the first character for several 2-character constraints. 4111 // Shift the pointer to the second character of the constraint. 4112 Name++; 4113 switch (*Name) { 4114 default: 4115 return false; 4116 case '0': // First SSE register. 4117 case 't': // Any SSE register, when SSE2 is enabled. 4118 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4119 case 'm': // Any MMX register, when inter-unit moves enabled. 4120 case 'k': // AVX512 arch mask registers: k1-k7. 4121 Info.setAllowsRegister(); 4122 return true; 4123 } 4124 case 'f': // Any x87 floating point stack register. 4125 // Constraint 'f' cannot be used for output operands. 4126 if (Info.ConstraintStr[0] == '=') 4127 return false; 4128 Info.setAllowsRegister(); 4129 return true; 4130 case 'a': // eax. 4131 case 'b': // ebx. 4132 case 'c': // ecx. 4133 case 'd': // edx. 4134 case 'S': // esi. 4135 case 'D': // edi. 4136 case 'A': // edx:eax. 4137 case 't': // Top of floating point stack. 4138 case 'u': // Second from top of floating point stack. 4139 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4140 case 'y': // Any MMX register. 4141 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4142 case 'x': // Any SSE register. 4143 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4144 // for intermideate k reg operations). 4145 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4146 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4147 case 'l': // "Index" registers: any general register that can be used as an 4148 // index in a base+index memory access. 4149 Info.setAllowsRegister(); 4150 return true; 4151 // Floating point constant constraints. 4152 case 'C': // SSE floating point constant. 4153 case 'G': // x87 floating point constant. 4154 return true; 4155 } 4156 } 4157 4158 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4159 unsigned Size) const { 4160 // Strip off constraint modifiers. 4161 while (Constraint[0] == '=' || 4162 Constraint[0] == '+' || 4163 Constraint[0] == '&') 4164 Constraint = Constraint.substr(1); 4165 4166 return validateOperandSize(Constraint, Size); 4167 } 4168 4169 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4170 unsigned Size) const { 4171 return validateOperandSize(Constraint, Size); 4172 } 4173 4174 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4175 unsigned Size) const { 4176 switch (Constraint[0]) { 4177 default: break; 4178 case 'k': 4179 // Registers k0-k7 (AVX512) size limit is 64 bit. 4180 case 'y': 4181 return Size <= 64; 4182 case 'f': 4183 case 't': 4184 case 'u': 4185 return Size <= 128; 4186 case 'v': 4187 case 'x': 4188 if (SSELevel >= AVX512F) 4189 // 512-bit zmm registers can be used if target supports AVX512F. 4190 return Size <= 512U; 4191 else if (SSELevel >= AVX) 4192 // 256-bit ymm registers can be used if target supports AVX. 4193 return Size <= 256U; 4194 return Size <= 128U; 4195 case 'Y': 4196 // 'Y' is the first character for several 2-character constraints. 4197 switch (Constraint[1]) { 4198 default: break; 4199 case 'm': 4200 // 'Ym' is synonymous with 'y'. 4201 case 'k': 4202 return Size <= 64; 4203 case 'i': 4204 case 't': 4205 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4206 if (SSELevel >= AVX512F) 4207 return Size <= 512U; 4208 else if (SSELevel >= AVX) 4209 return Size <= 256U; 4210 return SSELevel >= SSE2 && Size <= 128U; 4211 } 4212 4213 } 4214 4215 return true; 4216 } 4217 4218 std::string 4219 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4220 switch (*Constraint) { 4221 case 'a': return std::string("{ax}"); 4222 case 'b': return std::string("{bx}"); 4223 case 'c': return std::string("{cx}"); 4224 case 'd': return std::string("{dx}"); 4225 case 'S': return std::string("{si}"); 4226 case 'D': return std::string("{di}"); 4227 case 'p': // address 4228 return std::string("im"); 4229 case 't': // top of floating point stack. 4230 return std::string("{st}"); 4231 case 'u': // second from top of floating point stack. 4232 return std::string("{st(1)}"); // second from top of floating point stack. 4233 case 'Y': 4234 switch (Constraint[1]) { 4235 default: 4236 // Break from inner switch and fall through (copy single char), 4237 // continue parsing after copying the current constraint into 4238 // the return string. 4239 break; 4240 case 'k': 4241 // "^" hints llvm that this is a 2 letter constraint. 4242 // "Constraint++" is used to promote the string iterator 4243 // to the next constraint. 4244 return std::string("^") + std::string(Constraint++, 2); 4245 } 4246 LLVM_FALLTHROUGH; 4247 default: 4248 return std::string(1, *Constraint); 4249 } 4250 } 4251 4252 // X86-32 generic target 4253 class X86_32TargetInfo : public X86TargetInfo { 4254 public: 4255 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4256 : X86TargetInfo(Triple, Opts) { 4257 DoubleAlign = LongLongAlign = 32; 4258 LongDoubleWidth = 96; 4259 LongDoubleAlign = 32; 4260 SuitableAlign = 128; 4261 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4262 SizeType = UnsignedInt; 4263 PtrDiffType = SignedInt; 4264 IntPtrType = SignedInt; 4265 RegParmMax = 3; 4266 4267 // Use fpret for all types. 4268 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4269 (1 << TargetInfo::Double) | 4270 (1 << TargetInfo::LongDouble)); 4271 4272 // x86-32 has atomics up to 8 bytes 4273 // FIXME: Check that we actually have cmpxchg8b before setting 4274 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4275 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4276 } 4277 BuiltinVaListKind getBuiltinVaListKind() const override { 4278 return TargetInfo::CharPtrBuiltinVaList; 4279 } 4280 4281 int getEHDataRegisterNumber(unsigned RegNo) const override { 4282 if (RegNo == 0) return 0; 4283 if (RegNo == 1) return 2; 4284 return -1; 4285 } 4286 bool validateOperandSize(StringRef Constraint, 4287 unsigned Size) const override { 4288 switch (Constraint[0]) { 4289 default: break; 4290 case 'R': 4291 case 'q': 4292 case 'Q': 4293 case 'a': 4294 case 'b': 4295 case 'c': 4296 case 'd': 4297 case 'S': 4298 case 'D': 4299 return Size <= 32; 4300 case 'A': 4301 return Size <= 64; 4302 } 4303 4304 return X86TargetInfo::validateOperandSize(Constraint, Size); 4305 } 4306 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4307 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4308 Builtin::FirstTSBuiltin + 1); 4309 } 4310 }; 4311 4312 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4313 public: 4314 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4315 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4316 4317 unsigned getFloatEvalMethod() const override { 4318 unsigned Major, Minor, Micro; 4319 getTriple().getOSVersion(Major, Minor, Micro); 4320 // New NetBSD uses the default rounding mode. 4321 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4322 return X86_32TargetInfo::getFloatEvalMethod(); 4323 // NetBSD before 6.99.26 defaults to "double" rounding. 4324 return 1; 4325 } 4326 }; 4327 4328 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4329 public: 4330 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4331 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4332 SizeType = UnsignedLong; 4333 IntPtrType = SignedLong; 4334 PtrDiffType = SignedLong; 4335 } 4336 }; 4337 4338 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4339 public: 4340 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4341 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4342 SizeType = UnsignedLong; 4343 IntPtrType = SignedLong; 4344 PtrDiffType = SignedLong; 4345 } 4346 }; 4347 4348 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4349 public: 4350 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4351 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4352 LongDoubleWidth = 128; 4353 LongDoubleAlign = 128; 4354 SuitableAlign = 128; 4355 MaxVectorAlign = 256; 4356 // The watchOS simulator uses the builtin bool type for Objective-C. 4357 llvm::Triple T = llvm::Triple(Triple); 4358 if (T.isWatchOS()) 4359 UseSignedCharForObjCBool = false; 4360 SizeType = UnsignedLong; 4361 IntPtrType = SignedLong; 4362 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4363 HasAlignMac68kSupport = true; 4364 } 4365 4366 bool handleTargetFeatures(std::vector<std::string> &Features, 4367 DiagnosticsEngine &Diags) override { 4368 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4369 Diags)) 4370 return false; 4371 // We now know the features we have: we can decide how to align vectors. 4372 MaxVectorAlign = 4373 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4374 return true; 4375 } 4376 }; 4377 4378 // x86-32 Windows target 4379 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4380 public: 4381 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4382 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4383 WCharType = UnsignedShort; 4384 DoubleAlign = LongLongAlign = 64; 4385 bool IsWinCOFF = 4386 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4387 resetDataLayout(IsWinCOFF 4388 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4389 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4390 } 4391 void getTargetDefines(const LangOptions &Opts, 4392 MacroBuilder &Builder) const override { 4393 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4394 } 4395 }; 4396 4397 // x86-32 Windows Visual Studio target 4398 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4399 public: 4400 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4401 const TargetOptions &Opts) 4402 : WindowsX86_32TargetInfo(Triple, Opts) { 4403 LongDoubleWidth = LongDoubleAlign = 64; 4404 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4405 } 4406 void getTargetDefines(const LangOptions &Opts, 4407 MacroBuilder &Builder) const override { 4408 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4409 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4410 // The value of the following reflects processor type. 4411 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4412 // We lost the original triple, so we use the default. 4413 Builder.defineMacro("_M_IX86", "600"); 4414 } 4415 }; 4416 4417 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4418 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4419 // supports __declspec natively under -fms-extensions, but we define a no-op 4420 // __declspec macro anyway for pre-processor compatibility. 4421 if (Opts.MicrosoftExt) 4422 Builder.defineMacro("__declspec", "__declspec"); 4423 else 4424 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4425 4426 if (!Opts.MicrosoftExt) { 4427 // Provide macros for all the calling convention keywords. Provide both 4428 // single and double underscore prefixed variants. These are available on 4429 // x64 as well as x86, even though they have no effect. 4430 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4431 for (const char *CC : CCs) { 4432 std::string GCCSpelling = "__attribute__((__"; 4433 GCCSpelling += CC; 4434 GCCSpelling += "__))"; 4435 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4436 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4437 } 4438 } 4439 } 4440 4441 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4442 Builder.defineMacro("__MSVCRT__"); 4443 Builder.defineMacro("__MINGW32__"); 4444 addCygMingDefines(Opts, Builder); 4445 } 4446 4447 // x86-32 MinGW target 4448 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4449 public: 4450 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4451 : WindowsX86_32TargetInfo(Triple, Opts) {} 4452 void getTargetDefines(const LangOptions &Opts, 4453 MacroBuilder &Builder) const override { 4454 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4455 DefineStd(Builder, "WIN32", Opts); 4456 DefineStd(Builder, "WINNT", Opts); 4457 Builder.defineMacro("_X86_"); 4458 addMinGWDefines(Opts, Builder); 4459 } 4460 }; 4461 4462 // x86-32 Cygwin target 4463 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4464 public: 4465 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4466 : X86_32TargetInfo(Triple, Opts) { 4467 WCharType = UnsignedShort; 4468 DoubleAlign = LongLongAlign = 64; 4469 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4470 } 4471 void getTargetDefines(const LangOptions &Opts, 4472 MacroBuilder &Builder) const override { 4473 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4474 Builder.defineMacro("_X86_"); 4475 Builder.defineMacro("__CYGWIN__"); 4476 Builder.defineMacro("__CYGWIN32__"); 4477 addCygMingDefines(Opts, Builder); 4478 DefineStd(Builder, "unix", Opts); 4479 if (Opts.CPlusPlus) 4480 Builder.defineMacro("_GNU_SOURCE"); 4481 } 4482 }; 4483 4484 // x86-32 Haiku target 4485 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4486 public: 4487 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4488 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4489 } 4490 void getTargetDefines(const LangOptions &Opts, 4491 MacroBuilder &Builder) const override { 4492 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4493 Builder.defineMacro("__INTEL__"); 4494 } 4495 }; 4496 4497 // X86-32 MCU target 4498 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4499 public: 4500 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4501 : X86_32TargetInfo(Triple, Opts) { 4502 LongDoubleWidth = 64; 4503 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4504 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4505 WIntType = UnsignedInt; 4506 } 4507 4508 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4509 // On MCU we support only C calling convention. 4510 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4511 } 4512 4513 void getTargetDefines(const LangOptions &Opts, 4514 MacroBuilder &Builder) const override { 4515 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4516 Builder.defineMacro("__iamcu"); 4517 Builder.defineMacro("__iamcu__"); 4518 } 4519 4520 bool allowsLargerPreferedTypeAlignment() const override { 4521 return false; 4522 } 4523 }; 4524 4525 // RTEMS Target 4526 template<typename Target> 4527 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4528 protected: 4529 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4530 MacroBuilder &Builder) const override { 4531 // RTEMS defines; list based off of gcc output 4532 4533 Builder.defineMacro("__rtems__"); 4534 Builder.defineMacro("__ELF__"); 4535 } 4536 4537 public: 4538 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4539 : OSTargetInfo<Target>(Triple, Opts) { 4540 switch (Triple.getArch()) { 4541 default: 4542 case llvm::Triple::x86: 4543 // this->MCountName = ".mcount"; 4544 break; 4545 case llvm::Triple::mips: 4546 case llvm::Triple::mipsel: 4547 case llvm::Triple::ppc: 4548 case llvm::Triple::ppc64: 4549 case llvm::Triple::ppc64le: 4550 // this->MCountName = "_mcount"; 4551 break; 4552 case llvm::Triple::arm: 4553 // this->MCountName = "__mcount"; 4554 break; 4555 } 4556 } 4557 }; 4558 4559 // x86-32 RTEMS target 4560 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4561 public: 4562 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4563 : X86_32TargetInfo(Triple, Opts) { 4564 SizeType = UnsignedLong; 4565 IntPtrType = SignedLong; 4566 PtrDiffType = SignedLong; 4567 } 4568 void getTargetDefines(const LangOptions &Opts, 4569 MacroBuilder &Builder) const override { 4570 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4571 Builder.defineMacro("__INTEL__"); 4572 Builder.defineMacro("__rtems__"); 4573 } 4574 }; 4575 4576 // x86-64 generic target 4577 class X86_64TargetInfo : public X86TargetInfo { 4578 public: 4579 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4580 : X86TargetInfo(Triple, Opts) { 4581 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4582 bool IsWinCOFF = 4583 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4584 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4585 LongDoubleWidth = 128; 4586 LongDoubleAlign = 128; 4587 LargeArrayMinWidth = 128; 4588 LargeArrayAlign = 128; 4589 SuitableAlign = 128; 4590 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4591 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4592 IntPtrType = IsX32 ? SignedInt : SignedLong; 4593 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4594 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4595 RegParmMax = 6; 4596 4597 // Pointers are 32-bit in x32. 4598 resetDataLayout(IsX32 4599 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4600 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4601 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4602 4603 // Use fpret only for long double. 4604 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4605 4606 // Use fp2ret for _Complex long double. 4607 ComplexLongDoubleUsesFP2Ret = true; 4608 4609 // Make __builtin_ms_va_list available. 4610 HasBuiltinMSVaList = true; 4611 4612 // x86-64 has atomics up to 16 bytes. 4613 MaxAtomicPromoteWidth = 128; 4614 MaxAtomicInlineWidth = 128; 4615 } 4616 BuiltinVaListKind getBuiltinVaListKind() const override { 4617 return TargetInfo::X86_64ABIBuiltinVaList; 4618 } 4619 4620 int getEHDataRegisterNumber(unsigned RegNo) const override { 4621 if (RegNo == 0) return 0; 4622 if (RegNo == 1) return 1; 4623 return -1; 4624 } 4625 4626 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4627 switch (CC) { 4628 case CC_C: 4629 case CC_Swift: 4630 case CC_X86VectorCall: 4631 case CC_IntelOclBicc: 4632 case CC_X86_64Win64: 4633 case CC_PreserveMost: 4634 case CC_PreserveAll: 4635 case CC_X86RegCall: 4636 return CCCR_OK; 4637 default: 4638 return CCCR_Warning; 4639 } 4640 } 4641 4642 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4643 return CC_C; 4644 } 4645 4646 // for x32 we need it here explicitly 4647 bool hasInt128Type() const override { return true; } 4648 unsigned getUnwindWordWidth() const override { return 64; } 4649 unsigned getRegisterWidth() const override { return 64; } 4650 4651 bool validateGlobalRegisterVariable(StringRef RegName, 4652 unsigned RegSize, 4653 bool &HasSizeMismatch) const override { 4654 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4655 // handle. 4656 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4657 // Check that the register size is 64-bit. 4658 HasSizeMismatch = RegSize != 64; 4659 return true; 4660 } 4661 4662 // Check if the register is a 32-bit register the backend can handle. 4663 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4664 HasSizeMismatch); 4665 } 4666 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4667 return llvm::makeArrayRef(BuiltinInfoX86, 4668 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4669 } 4670 }; 4671 4672 // x86-64 Windows target 4673 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4674 public: 4675 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4676 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4677 WCharType = UnsignedShort; 4678 LongWidth = LongAlign = 32; 4679 DoubleAlign = LongLongAlign = 64; 4680 IntMaxType = SignedLongLong; 4681 Int64Type = SignedLongLong; 4682 SizeType = UnsignedLongLong; 4683 PtrDiffType = SignedLongLong; 4684 IntPtrType = SignedLongLong; 4685 } 4686 4687 void getTargetDefines(const LangOptions &Opts, 4688 MacroBuilder &Builder) const override { 4689 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4690 Builder.defineMacro("_WIN64"); 4691 } 4692 4693 BuiltinVaListKind getBuiltinVaListKind() const override { 4694 return TargetInfo::CharPtrBuiltinVaList; 4695 } 4696 4697 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4698 switch (CC) { 4699 case CC_X86StdCall: 4700 case CC_X86ThisCall: 4701 case CC_X86FastCall: 4702 return CCCR_Ignore; 4703 case CC_C: 4704 case CC_X86VectorCall: 4705 case CC_IntelOclBicc: 4706 case CC_X86_64SysV: 4707 case CC_Swift: 4708 case CC_X86RegCall: 4709 return CCCR_OK; 4710 default: 4711 return CCCR_Warning; 4712 } 4713 } 4714 }; 4715 4716 // x86-64 Windows Visual Studio target 4717 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4718 public: 4719 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4720 const TargetOptions &Opts) 4721 : WindowsX86_64TargetInfo(Triple, Opts) { 4722 LongDoubleWidth = LongDoubleAlign = 64; 4723 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4724 } 4725 void getTargetDefines(const LangOptions &Opts, 4726 MacroBuilder &Builder) const override { 4727 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4728 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4729 Builder.defineMacro("_M_X64", "100"); 4730 Builder.defineMacro("_M_AMD64", "100"); 4731 } 4732 }; 4733 4734 // x86-64 MinGW target 4735 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4736 public: 4737 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4738 : WindowsX86_64TargetInfo(Triple, Opts) { 4739 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4740 // with x86 FP ops. Weird. 4741 LongDoubleWidth = LongDoubleAlign = 128; 4742 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 4743 } 4744 4745 void getTargetDefines(const LangOptions &Opts, 4746 MacroBuilder &Builder) const override { 4747 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4748 DefineStd(Builder, "WIN64", Opts); 4749 Builder.defineMacro("__MINGW64__"); 4750 addMinGWDefines(Opts, Builder); 4751 4752 // GCC defines this macro when it is using __gxx_personality_seh0. 4753 if (!Opts.SjLjExceptions) 4754 Builder.defineMacro("__SEH__"); 4755 } 4756 }; 4757 4758 // x86-64 Cygwin target 4759 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4760 public: 4761 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4762 : X86_64TargetInfo(Triple, Opts) { 4763 TLSSupported = false; 4764 WCharType = UnsignedShort; 4765 } 4766 void getTargetDefines(const LangOptions &Opts, 4767 MacroBuilder &Builder) const override { 4768 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4769 Builder.defineMacro("__x86_64__"); 4770 Builder.defineMacro("__CYGWIN__"); 4771 Builder.defineMacro("__CYGWIN64__"); 4772 addCygMingDefines(Opts, Builder); 4773 DefineStd(Builder, "unix", Opts); 4774 if (Opts.CPlusPlus) 4775 Builder.defineMacro("_GNU_SOURCE"); 4776 4777 // GCC defines this macro when it is using __gxx_personality_seh0. 4778 if (!Opts.SjLjExceptions) 4779 Builder.defineMacro("__SEH__"); 4780 } 4781 }; 4782 4783 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4784 public: 4785 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4786 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4787 Int64Type = SignedLongLong; 4788 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4789 llvm::Triple T = llvm::Triple(Triple); 4790 if (T.isiOS()) 4791 UseSignedCharForObjCBool = false; 4792 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4793 } 4794 4795 bool handleTargetFeatures(std::vector<std::string> &Features, 4796 DiagnosticsEngine &Diags) override { 4797 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4798 Diags)) 4799 return false; 4800 // We now know the features we have: we can decide how to align vectors. 4801 MaxVectorAlign = 4802 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4803 return true; 4804 } 4805 }; 4806 4807 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4808 public: 4809 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4810 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4811 IntMaxType = SignedLongLong; 4812 Int64Type = SignedLongLong; 4813 } 4814 }; 4815 4816 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4817 public: 4818 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4819 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4820 IntMaxType = SignedLongLong; 4821 Int64Type = SignedLongLong; 4822 } 4823 }; 4824 4825 class ARMTargetInfo : public TargetInfo { 4826 // Possible FPU choices. 4827 enum FPUMode { 4828 VFP2FPU = (1 << 0), 4829 VFP3FPU = (1 << 1), 4830 VFP4FPU = (1 << 2), 4831 NeonFPU = (1 << 3), 4832 FPARMV8 = (1 << 4) 4833 }; 4834 4835 // Possible HWDiv features. 4836 enum HWDivMode { 4837 HWDivThumb = (1 << 0), 4838 HWDivARM = (1 << 1) 4839 }; 4840 4841 static bool FPUModeIsVFP(FPUMode Mode) { 4842 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4843 } 4844 4845 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4846 static const char * const GCCRegNames[]; 4847 4848 std::string ABI, CPU; 4849 4850 StringRef CPUProfile; 4851 StringRef CPUAttr; 4852 4853 enum { 4854 FP_Default, 4855 FP_VFP, 4856 FP_Neon 4857 } FPMath; 4858 4859 unsigned ArchISA; 4860 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4861 unsigned ArchProfile; 4862 unsigned ArchVersion; 4863 4864 unsigned FPU : 5; 4865 4866 unsigned IsAAPCS : 1; 4867 unsigned HWDiv : 2; 4868 4869 // Initialized via features. 4870 unsigned SoftFloat : 1; 4871 unsigned SoftFloatABI : 1; 4872 4873 unsigned CRC : 1; 4874 unsigned Crypto : 1; 4875 unsigned DSP : 1; 4876 unsigned Unaligned : 1; 4877 4878 enum { 4879 LDREX_B = (1 << 0), /// byte (8-bit) 4880 LDREX_H = (1 << 1), /// half (16-bit) 4881 LDREX_W = (1 << 2), /// word (32-bit) 4882 LDREX_D = (1 << 3), /// double (64-bit) 4883 }; 4884 4885 uint32_t LDREX; 4886 4887 // ACLE 6.5.1 Hardware floating point 4888 enum { 4889 HW_FP_HP = (1 << 1), /// half (16-bit) 4890 HW_FP_SP = (1 << 2), /// single (32-bit) 4891 HW_FP_DP = (1 << 3), /// double (64-bit) 4892 }; 4893 uint32_t HW_FP; 4894 4895 static const Builtin::Info BuiltinInfo[]; 4896 4897 void setABIAAPCS() { 4898 IsAAPCS = true; 4899 4900 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4901 const llvm::Triple &T = getTriple(); 4902 4903 // size_t is unsigned long on MachO-derived environments, NetBSD, 4904 // OpenBSD and Bitrig. 4905 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4906 T.getOS() == llvm::Triple::OpenBSD || 4907 T.getOS() == llvm::Triple::Bitrig) 4908 SizeType = UnsignedLong; 4909 else 4910 SizeType = UnsignedInt; 4911 4912 switch (T.getOS()) { 4913 case llvm::Triple::NetBSD: 4914 case llvm::Triple::OpenBSD: 4915 WCharType = SignedInt; 4916 break; 4917 case llvm::Triple::Win32: 4918 WCharType = UnsignedShort; 4919 break; 4920 case llvm::Triple::Linux: 4921 default: 4922 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4923 WCharType = UnsignedInt; 4924 break; 4925 } 4926 4927 UseBitFieldTypeAlignment = true; 4928 4929 ZeroLengthBitfieldBoundary = 0; 4930 4931 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4932 // so set preferred for small types to 32. 4933 if (T.isOSBinFormatMachO()) { 4934 resetDataLayout(BigEndian 4935 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4936 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4937 } else if (T.isOSWindows()) { 4938 assert(!BigEndian && "Windows on ARM does not support big endian"); 4939 resetDataLayout("e" 4940 "-m:w" 4941 "-p:32:32" 4942 "-i64:64" 4943 "-v128:64:128" 4944 "-a:0:32" 4945 "-n32" 4946 "-S64"); 4947 } else if (T.isOSNaCl()) { 4948 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4949 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4950 } else { 4951 resetDataLayout(BigEndian 4952 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4953 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4954 } 4955 4956 // FIXME: Enumerated types are variable width in straight AAPCS. 4957 } 4958 4959 void setABIAPCS(bool IsAAPCS16) { 4960 const llvm::Triple &T = getTriple(); 4961 4962 IsAAPCS = false; 4963 4964 if (IsAAPCS16) 4965 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4966 else 4967 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4968 4969 // size_t is unsigned int on FreeBSD. 4970 if (T.getOS() == llvm::Triple::FreeBSD) 4971 SizeType = UnsignedInt; 4972 else 4973 SizeType = UnsignedLong; 4974 4975 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4976 WCharType = SignedInt; 4977 4978 // Do not respect the alignment of bit-field types when laying out 4979 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4980 UseBitFieldTypeAlignment = false; 4981 4982 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4983 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4984 /// gcc. 4985 ZeroLengthBitfieldBoundary = 32; 4986 4987 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4988 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4989 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4990 } else if (T.isOSBinFormatMachO()) 4991 resetDataLayout( 4992 BigEndian 4993 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4994 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4995 else 4996 resetDataLayout( 4997 BigEndian 4998 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4999 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5000 5001 // FIXME: Override "preferred align" for double and long long. 5002 } 5003 5004 void setArchInfo() { 5005 StringRef ArchName = getTriple().getArchName(); 5006 5007 ArchISA = llvm::ARM::parseArchISA(ArchName); 5008 CPU = llvm::ARM::getDefaultCPU(ArchName); 5009 unsigned AK = llvm::ARM::parseArch(ArchName); 5010 if (AK != llvm::ARM::AK_INVALID) 5011 ArchKind = AK; 5012 setArchInfo(ArchKind); 5013 } 5014 5015 void setArchInfo(unsigned Kind) { 5016 StringRef SubArch; 5017 5018 // cache TargetParser info 5019 ArchKind = Kind; 5020 SubArch = llvm::ARM::getSubArch(ArchKind); 5021 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5022 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5023 5024 // cache CPU related strings 5025 CPUAttr = getCPUAttr(); 5026 CPUProfile = getCPUProfile(); 5027 } 5028 5029 void setAtomic() { 5030 // when triple does not specify a sub arch, 5031 // then we are not using inline atomics 5032 bool ShouldUseInlineAtomic = 5033 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5034 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5035 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5036 if (ArchProfile == llvm::ARM::PK_M) { 5037 MaxAtomicPromoteWidth = 32; 5038 if (ShouldUseInlineAtomic) 5039 MaxAtomicInlineWidth = 32; 5040 } 5041 else { 5042 MaxAtomicPromoteWidth = 64; 5043 if (ShouldUseInlineAtomic) 5044 MaxAtomicInlineWidth = 64; 5045 } 5046 } 5047 5048 bool isThumb() const { 5049 return (ArchISA == llvm::ARM::IK_THUMB); 5050 } 5051 5052 bool supportsThumb() const { 5053 return CPUAttr.count('T') || ArchVersion >= 6; 5054 } 5055 5056 bool supportsThumb2() const { 5057 return CPUAttr.equals("6T2") || 5058 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5059 } 5060 5061 StringRef getCPUAttr() const { 5062 // For most sub-arches, the build attribute CPU name is enough. 5063 // For Cortex variants, it's slightly different. 5064 switch(ArchKind) { 5065 default: 5066 return llvm::ARM::getCPUAttr(ArchKind); 5067 case llvm::ARM::AK_ARMV6M: 5068 return "6M"; 5069 case llvm::ARM::AK_ARMV7S: 5070 return "7S"; 5071 case llvm::ARM::AK_ARMV7A: 5072 return "7A"; 5073 case llvm::ARM::AK_ARMV7R: 5074 return "7R"; 5075 case llvm::ARM::AK_ARMV7M: 5076 return "7M"; 5077 case llvm::ARM::AK_ARMV7EM: 5078 return "7EM"; 5079 case llvm::ARM::AK_ARMV7VE: 5080 return "7VE"; 5081 case llvm::ARM::AK_ARMV8A: 5082 return "8A"; 5083 case llvm::ARM::AK_ARMV8_1A: 5084 return "8_1A"; 5085 case llvm::ARM::AK_ARMV8_2A: 5086 return "8_2A"; 5087 case llvm::ARM::AK_ARMV8MBaseline: 5088 return "8M_BASE"; 5089 case llvm::ARM::AK_ARMV8MMainline: 5090 return "8M_MAIN"; 5091 case llvm::ARM::AK_ARMV8R: 5092 return "8R"; 5093 } 5094 } 5095 5096 StringRef getCPUProfile() const { 5097 switch(ArchProfile) { 5098 case llvm::ARM::PK_A: 5099 return "A"; 5100 case llvm::ARM::PK_R: 5101 return "R"; 5102 case llvm::ARM::PK_M: 5103 return "M"; 5104 default: 5105 return ""; 5106 } 5107 } 5108 5109 public: 5110 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5111 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5112 HW_FP(0) { 5113 5114 switch (getTriple().getOS()) { 5115 case llvm::Triple::NetBSD: 5116 case llvm::Triple::OpenBSD: 5117 PtrDiffType = SignedLong; 5118 break; 5119 default: 5120 PtrDiffType = SignedInt; 5121 break; 5122 } 5123 5124 // Cache arch related info. 5125 setArchInfo(); 5126 5127 // {} in inline assembly are neon specifiers, not assembly variant 5128 // specifiers. 5129 NoAsmVariants = true; 5130 5131 // FIXME: This duplicates code from the driver that sets the -target-abi 5132 // option - this code is used if -target-abi isn't passed and should 5133 // be unified in some way. 5134 if (Triple.isOSBinFormatMachO()) { 5135 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5136 // the frontend matches that. 5137 if (Triple.getEnvironment() == llvm::Triple::EABI || 5138 Triple.getOS() == llvm::Triple::UnknownOS || 5139 ArchProfile == llvm::ARM::PK_M) { 5140 setABI("aapcs"); 5141 } else if (Triple.isWatchABI()) { 5142 setABI("aapcs16"); 5143 } else { 5144 setABI("apcs-gnu"); 5145 } 5146 } else if (Triple.isOSWindows()) { 5147 // FIXME: this is invalid for WindowsCE 5148 setABI("aapcs"); 5149 } else { 5150 // Select the default based on the platform. 5151 switch (Triple.getEnvironment()) { 5152 case llvm::Triple::Android: 5153 case llvm::Triple::GNUEABI: 5154 case llvm::Triple::GNUEABIHF: 5155 case llvm::Triple::MuslEABI: 5156 case llvm::Triple::MuslEABIHF: 5157 setABI("aapcs-linux"); 5158 break; 5159 case llvm::Triple::EABIHF: 5160 case llvm::Triple::EABI: 5161 setABI("aapcs"); 5162 break; 5163 case llvm::Triple::GNU: 5164 setABI("apcs-gnu"); 5165 break; 5166 default: 5167 if (Triple.getOS() == llvm::Triple::NetBSD) 5168 setABI("apcs-gnu"); 5169 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5170 setABI("aapcs-linux"); 5171 else 5172 setABI("aapcs"); 5173 break; 5174 } 5175 } 5176 5177 // ARM targets default to using the ARM C++ ABI. 5178 TheCXXABI.set(TargetCXXABI::GenericARM); 5179 5180 // ARM has atomics up to 8 bytes 5181 setAtomic(); 5182 5183 // Do force alignment of members that follow zero length bitfields. If 5184 // the alignment of the zero-length bitfield is greater than the member 5185 // that follows it, `bar', `bar' will be aligned as the type of the 5186 // zero length bitfield. 5187 UseZeroLengthBitfieldAlignment = true; 5188 5189 if (Triple.getOS() == llvm::Triple::Linux || 5190 Triple.getOS() == llvm::Triple::UnknownOS) 5191 this->MCountName = 5192 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5193 } 5194 5195 StringRef getABI() const override { return ABI; } 5196 5197 bool setABI(const std::string &Name) override { 5198 ABI = Name; 5199 5200 // The defaults (above) are for AAPCS, check if we need to change them. 5201 // 5202 // FIXME: We need support for -meabi... we could just mangle it into the 5203 // name. 5204 if (Name == "apcs-gnu" || Name == "aapcs16") { 5205 setABIAPCS(Name == "aapcs16"); 5206 return true; 5207 } 5208 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5209 setABIAAPCS(); 5210 return true; 5211 } 5212 return false; 5213 } 5214 5215 // FIXME: This should be based on Arch attributes, not CPU names. 5216 bool 5217 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5218 StringRef CPU, 5219 const std::vector<std::string> &FeaturesVec) const override { 5220 5221 std::vector<StringRef> TargetFeatures; 5222 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5223 5224 // get default FPU features 5225 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5226 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5227 5228 // get default Extension features 5229 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5230 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5231 5232 for (auto Feature : TargetFeatures) 5233 if (Feature[0] == '+') 5234 Features[Feature.drop_front(1)] = true; 5235 5236 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5237 } 5238 5239 bool handleTargetFeatures(std::vector<std::string> &Features, 5240 DiagnosticsEngine &Diags) override { 5241 FPU = 0; 5242 CRC = 0; 5243 Crypto = 0; 5244 DSP = 0; 5245 Unaligned = 1; 5246 SoftFloat = SoftFloatABI = false; 5247 HWDiv = 0; 5248 5249 // This does not diagnose illegal cases like having both 5250 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5251 uint32_t HW_FP_remove = 0; 5252 for (const auto &Feature : Features) { 5253 if (Feature == "+soft-float") { 5254 SoftFloat = true; 5255 } else if (Feature == "+soft-float-abi") { 5256 SoftFloatABI = true; 5257 } else if (Feature == "+vfp2") { 5258 FPU |= VFP2FPU; 5259 HW_FP |= HW_FP_SP | HW_FP_DP; 5260 } else if (Feature == "+vfp3") { 5261 FPU |= VFP3FPU; 5262 HW_FP |= HW_FP_SP | HW_FP_DP; 5263 } else if (Feature == "+vfp4") { 5264 FPU |= VFP4FPU; 5265 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5266 } else if (Feature == "+fp-armv8") { 5267 FPU |= FPARMV8; 5268 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5269 } else if (Feature == "+neon") { 5270 FPU |= NeonFPU; 5271 HW_FP |= HW_FP_SP | HW_FP_DP; 5272 } else if (Feature == "+hwdiv") { 5273 HWDiv |= HWDivThumb; 5274 } else if (Feature == "+hwdiv-arm") { 5275 HWDiv |= HWDivARM; 5276 } else if (Feature == "+crc") { 5277 CRC = 1; 5278 } else if (Feature == "+crypto") { 5279 Crypto = 1; 5280 } else if (Feature == "+dsp") { 5281 DSP = 1; 5282 } else if (Feature == "+fp-only-sp") { 5283 HW_FP_remove |= HW_FP_DP; 5284 } else if (Feature == "+strict-align") { 5285 Unaligned = 0; 5286 } else if (Feature == "+fp16") { 5287 HW_FP |= HW_FP_HP; 5288 } 5289 } 5290 HW_FP &= ~HW_FP_remove; 5291 5292 switch (ArchVersion) { 5293 case 6: 5294 if (ArchProfile == llvm::ARM::PK_M) 5295 LDREX = 0; 5296 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5297 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5298 else 5299 LDREX = LDREX_W; 5300 break; 5301 case 7: 5302 if (ArchProfile == llvm::ARM::PK_M) 5303 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5304 else 5305 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5306 break; 5307 case 8: 5308 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5309 } 5310 5311 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5312 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5313 return false; 5314 } 5315 5316 if (FPMath == FP_Neon) 5317 Features.push_back("+neonfp"); 5318 else if (FPMath == FP_VFP) 5319 Features.push_back("-neonfp"); 5320 5321 // Remove front-end specific options which the backend handles differently. 5322 auto Feature = 5323 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5324 if (Feature != Features.end()) 5325 Features.erase(Feature); 5326 5327 return true; 5328 } 5329 5330 bool hasFeature(StringRef Feature) const override { 5331 return llvm::StringSwitch<bool>(Feature) 5332 .Case("arm", true) 5333 .Case("aarch32", true) 5334 .Case("softfloat", SoftFloat) 5335 .Case("thumb", isThumb()) 5336 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5337 .Case("hwdiv", HWDiv & HWDivThumb) 5338 .Case("hwdiv-arm", HWDiv & HWDivARM) 5339 .Default(false); 5340 } 5341 5342 bool setCPU(const std::string &Name) override { 5343 if (Name != "generic") 5344 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5345 5346 if (ArchKind == llvm::ARM::AK_INVALID) 5347 return false; 5348 setAtomic(); 5349 CPU = Name; 5350 return true; 5351 } 5352 5353 bool setFPMath(StringRef Name) override; 5354 5355 void getTargetDefines(const LangOptions &Opts, 5356 MacroBuilder &Builder) const override { 5357 // Target identification. 5358 Builder.defineMacro("__arm"); 5359 Builder.defineMacro("__arm__"); 5360 // For bare-metal none-eabi. 5361 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5362 getTriple().getEnvironment() == llvm::Triple::EABI) 5363 Builder.defineMacro("__ELF__"); 5364 5365 // Target properties. 5366 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5367 5368 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5369 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5370 if (getTriple().isWatchABI()) 5371 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5372 5373 if (!CPUAttr.empty()) 5374 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5375 5376 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5377 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5378 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5379 5380 if (ArchVersion >= 8) { 5381 // ACLE 6.5.7 Crypto Extension 5382 if (Crypto) 5383 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5384 // ACLE 6.5.8 CRC32 Extension 5385 if (CRC) 5386 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5387 // ACLE 6.5.10 Numeric Maximum and Minimum 5388 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5389 // ACLE 6.5.9 Directed Rounding 5390 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5391 } 5392 5393 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5394 // is not defined for the M-profile. 5395 // NOTE that the default profile is assumed to be 'A' 5396 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5397 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5398 5399 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5400 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5401 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5402 // v7 and v8 architectures excluding v8-M Baseline. 5403 if (supportsThumb2()) 5404 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5405 else if (supportsThumb()) 5406 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5407 5408 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5409 // instruction set such as ARM or Thumb. 5410 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5411 5412 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5413 5414 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5415 if (!CPUProfile.empty()) 5416 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5417 5418 // ACLE 6.4.3 Unaligned access supported in hardware 5419 if (Unaligned) 5420 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5421 5422 // ACLE 6.4.4 LDREX/STREX 5423 if (LDREX) 5424 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5425 5426 // ACLE 6.4.5 CLZ 5427 if (ArchVersion == 5 || 5428 (ArchVersion == 6 && CPUProfile != "M") || 5429 ArchVersion > 6) 5430 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5431 5432 // ACLE 6.5.1 Hardware Floating Point 5433 if (HW_FP) 5434 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5435 5436 // ACLE predefines. 5437 Builder.defineMacro("__ARM_ACLE", "200"); 5438 5439 // FP16 support (we currently only support IEEE format). 5440 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5441 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5442 5443 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5444 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5445 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5446 5447 // Subtarget options. 5448 5449 // FIXME: It's more complicated than this and we don't really support 5450 // interworking. 5451 // Windows on ARM does not "support" interworking 5452 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5453 Builder.defineMacro("__THUMB_INTERWORK__"); 5454 5455 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5456 // Embedded targets on Darwin follow AAPCS, but not EABI. 5457 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5458 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5459 Builder.defineMacro("__ARM_EABI__"); 5460 Builder.defineMacro("__ARM_PCS", "1"); 5461 } 5462 5463 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5464 ABI == "aapcs16") 5465 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5466 5467 if (SoftFloat) 5468 Builder.defineMacro("__SOFTFP__"); 5469 5470 if (ArchKind == llvm::ARM::AK_XSCALE) 5471 Builder.defineMacro("__XSCALE__"); 5472 5473 if (isThumb()) { 5474 Builder.defineMacro("__THUMBEL__"); 5475 Builder.defineMacro("__thumb__"); 5476 if (supportsThumb2()) 5477 Builder.defineMacro("__thumb2__"); 5478 } 5479 5480 // ACLE 6.4.9 32-bit SIMD instructions 5481 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5482 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5483 5484 // ACLE 6.4.10 Hardware Integer Divide 5485 if (((HWDiv & HWDivThumb) && isThumb()) || 5486 ((HWDiv & HWDivARM) && !isThumb())) { 5487 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5488 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5489 } 5490 5491 // Note, this is always on in gcc, even though it doesn't make sense. 5492 Builder.defineMacro("__APCS_32__"); 5493 5494 if (FPUModeIsVFP((FPUMode) FPU)) { 5495 Builder.defineMacro("__VFP_FP__"); 5496 if (FPU & VFP2FPU) 5497 Builder.defineMacro("__ARM_VFPV2__"); 5498 if (FPU & VFP3FPU) 5499 Builder.defineMacro("__ARM_VFPV3__"); 5500 if (FPU & VFP4FPU) 5501 Builder.defineMacro("__ARM_VFPV4__"); 5502 if (FPU & FPARMV8) 5503 Builder.defineMacro("__ARM_FPV5__"); 5504 } 5505 5506 // This only gets set when Neon instructions are actually available, unlike 5507 // the VFP define, hence the soft float and arch check. This is subtly 5508 // different from gcc, we follow the intent which was that it should be set 5509 // when Neon instructions are actually available. 5510 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5511 Builder.defineMacro("__ARM_NEON", "1"); 5512 Builder.defineMacro("__ARM_NEON__"); 5513 // current AArch32 NEON implementations do not support double-precision 5514 // floating-point even when it is present in VFP. 5515 Builder.defineMacro("__ARM_NEON_FP", 5516 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5517 } 5518 5519 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5520 Opts.ShortWChar ? "2" : "4"); 5521 5522 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5523 Opts.ShortEnums ? "1" : "4"); 5524 5525 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5526 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5527 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5528 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5529 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5530 } 5531 5532 // ACLE 6.4.7 DSP instructions 5533 if (DSP) { 5534 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5535 } 5536 5537 // ACLE 6.4.8 Saturation instructions 5538 bool SAT = false; 5539 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5540 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5541 SAT = true; 5542 } 5543 5544 // ACLE 6.4.6 Q (saturation) flag 5545 if (DSP || SAT) 5546 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5547 5548 if (Opts.UnsafeFPMath) 5549 Builder.defineMacro("__ARM_FP_FAST", "1"); 5550 5551 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5552 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5553 } 5554 5555 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5556 return llvm::makeArrayRef(BuiltinInfo, 5557 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5558 } 5559 bool isCLZForZeroUndef() const override { return false; } 5560 BuiltinVaListKind getBuiltinVaListKind() const override { 5561 return IsAAPCS 5562 ? AAPCSABIBuiltinVaList 5563 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5564 : TargetInfo::VoidPtrBuiltinVaList); 5565 } 5566 ArrayRef<const char *> getGCCRegNames() const override; 5567 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5568 bool validateAsmConstraint(const char *&Name, 5569 TargetInfo::ConstraintInfo &Info) const override { 5570 switch (*Name) { 5571 default: break; 5572 case 'l': // r0-r7 5573 case 'h': // r8-r15 5574 case 't': // VFP Floating point register single precision 5575 case 'w': // VFP Floating point register double precision 5576 Info.setAllowsRegister(); 5577 return true; 5578 case 'I': 5579 case 'J': 5580 case 'K': 5581 case 'L': 5582 case 'M': 5583 // FIXME 5584 return true; 5585 case 'Q': // A memory address that is a single base register. 5586 Info.setAllowsMemory(); 5587 return true; 5588 case 'U': // a memory reference... 5589 switch (Name[1]) { 5590 case 'q': // ...ARMV4 ldrsb 5591 case 'v': // ...VFP load/store (reg+constant offset) 5592 case 'y': // ...iWMMXt load/store 5593 case 't': // address valid for load/store opaque types wider 5594 // than 128-bits 5595 case 'n': // valid address for Neon doubleword vector load/store 5596 case 'm': // valid address for Neon element and structure load/store 5597 case 's': // valid address for non-offset loads/stores of quad-word 5598 // values in four ARM registers 5599 Info.setAllowsMemory(); 5600 Name++; 5601 return true; 5602 } 5603 } 5604 return false; 5605 } 5606 std::string convertConstraint(const char *&Constraint) const override { 5607 std::string R; 5608 switch (*Constraint) { 5609 case 'U': // Two-character constraint; add "^" hint for later parsing. 5610 R = std::string("^") + std::string(Constraint, 2); 5611 Constraint++; 5612 break; 5613 case 'p': // 'p' should be translated to 'r' by default. 5614 R = std::string("r"); 5615 break; 5616 default: 5617 return std::string(1, *Constraint); 5618 } 5619 return R; 5620 } 5621 bool 5622 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5623 std::string &SuggestedModifier) const override { 5624 bool isOutput = (Constraint[0] == '='); 5625 bool isInOut = (Constraint[0] == '+'); 5626 5627 // Strip off constraint modifiers. 5628 while (Constraint[0] == '=' || 5629 Constraint[0] == '+' || 5630 Constraint[0] == '&') 5631 Constraint = Constraint.substr(1); 5632 5633 switch (Constraint[0]) { 5634 default: break; 5635 case 'r': { 5636 switch (Modifier) { 5637 default: 5638 return (isInOut || isOutput || Size <= 64); 5639 case 'q': 5640 // A register of size 32 cannot fit a vector type. 5641 return false; 5642 } 5643 } 5644 } 5645 5646 return true; 5647 } 5648 const char *getClobbers() const override { 5649 // FIXME: Is this really right? 5650 return ""; 5651 } 5652 5653 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5654 switch (CC) { 5655 case CC_AAPCS: 5656 case CC_AAPCS_VFP: 5657 case CC_Swift: 5658 return CCCR_OK; 5659 default: 5660 return CCCR_Warning; 5661 } 5662 } 5663 5664 int getEHDataRegisterNumber(unsigned RegNo) const override { 5665 if (RegNo == 0) return 0; 5666 if (RegNo == 1) return 1; 5667 return -1; 5668 } 5669 5670 bool hasSjLjLowering() const override { 5671 return true; 5672 } 5673 }; 5674 5675 bool ARMTargetInfo::setFPMath(StringRef Name) { 5676 if (Name == "neon") { 5677 FPMath = FP_Neon; 5678 return true; 5679 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5680 Name == "vfp4") { 5681 FPMath = FP_VFP; 5682 return true; 5683 } 5684 return false; 5685 } 5686 5687 const char * const ARMTargetInfo::GCCRegNames[] = { 5688 // Integer registers 5689 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5690 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5691 5692 // Float registers 5693 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5694 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5695 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5696 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5697 5698 // Double registers 5699 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5700 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5701 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5702 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5703 5704 // Quad registers 5705 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5706 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5707 }; 5708 5709 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5710 return llvm::makeArrayRef(GCCRegNames); 5711 } 5712 5713 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5714 { { "a1" }, "r0" }, 5715 { { "a2" }, "r1" }, 5716 { { "a3" }, "r2" }, 5717 { { "a4" }, "r3" }, 5718 { { "v1" }, "r4" }, 5719 { { "v2" }, "r5" }, 5720 { { "v3" }, "r6" }, 5721 { { "v4" }, "r7" }, 5722 { { "v5" }, "r8" }, 5723 { { "v6", "rfp" }, "r9" }, 5724 { { "sl" }, "r10" }, 5725 { { "fp" }, "r11" }, 5726 { { "ip" }, "r12" }, 5727 { { "r13" }, "sp" }, 5728 { { "r14" }, "lr" }, 5729 { { "r15" }, "pc" }, 5730 // The S, D and Q registers overlap, but aren't really aliases; we 5731 // don't want to substitute one of these for a different-sized one. 5732 }; 5733 5734 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5735 return llvm::makeArrayRef(GCCRegAliases); 5736 } 5737 5738 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5739 #define BUILTIN(ID, TYPE, ATTRS) \ 5740 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5741 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5742 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5743 #include "clang/Basic/BuiltinsNEON.def" 5744 5745 #define BUILTIN(ID, TYPE, ATTRS) \ 5746 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5747 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5748 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5749 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5750 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5751 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5752 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5753 #include "clang/Basic/BuiltinsARM.def" 5754 }; 5755 5756 class ARMleTargetInfo : public ARMTargetInfo { 5757 public: 5758 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5759 : ARMTargetInfo(Triple, Opts) {} 5760 void getTargetDefines(const LangOptions &Opts, 5761 MacroBuilder &Builder) const override { 5762 Builder.defineMacro("__ARMEL__"); 5763 ARMTargetInfo::getTargetDefines(Opts, Builder); 5764 } 5765 }; 5766 5767 class ARMbeTargetInfo : public ARMTargetInfo { 5768 public: 5769 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5770 : ARMTargetInfo(Triple, Opts) {} 5771 void getTargetDefines(const LangOptions &Opts, 5772 MacroBuilder &Builder) const override { 5773 Builder.defineMacro("__ARMEB__"); 5774 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5775 ARMTargetInfo::getTargetDefines(Opts, Builder); 5776 } 5777 }; 5778 5779 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5780 const llvm::Triple Triple; 5781 public: 5782 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5783 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5784 WCharType = UnsignedShort; 5785 SizeType = UnsignedInt; 5786 } 5787 void getVisualStudioDefines(const LangOptions &Opts, 5788 MacroBuilder &Builder) const { 5789 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5790 5791 // FIXME: this is invalid for WindowsCE 5792 Builder.defineMacro("_M_ARM_NT", "1"); 5793 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5794 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5795 5796 assert((Triple.getArch() == llvm::Triple::arm || 5797 Triple.getArch() == llvm::Triple::thumb) && 5798 "invalid architecture for Windows ARM target info"); 5799 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5800 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5801 5802 // TODO map the complete set of values 5803 // 31: VFPv3 40: VFPv4 5804 Builder.defineMacro("_M_ARM_FP", "31"); 5805 } 5806 BuiltinVaListKind getBuiltinVaListKind() const override { 5807 return TargetInfo::CharPtrBuiltinVaList; 5808 } 5809 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5810 switch (CC) { 5811 case CC_X86StdCall: 5812 case CC_X86ThisCall: 5813 case CC_X86FastCall: 5814 case CC_X86VectorCall: 5815 return CCCR_Ignore; 5816 case CC_C: 5817 return CCCR_OK; 5818 default: 5819 return CCCR_Warning; 5820 } 5821 } 5822 }; 5823 5824 // Windows ARM + Itanium C++ ABI Target 5825 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5826 public: 5827 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5828 const TargetOptions &Opts) 5829 : WindowsARMTargetInfo(Triple, Opts) { 5830 TheCXXABI.set(TargetCXXABI::GenericARM); 5831 } 5832 5833 void getTargetDefines(const LangOptions &Opts, 5834 MacroBuilder &Builder) const override { 5835 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5836 5837 if (Opts.MSVCCompat) 5838 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5839 } 5840 }; 5841 5842 // Windows ARM, MS (C++) ABI 5843 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5844 public: 5845 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5846 const TargetOptions &Opts) 5847 : WindowsARMTargetInfo(Triple, Opts) { 5848 TheCXXABI.set(TargetCXXABI::Microsoft); 5849 } 5850 5851 void getTargetDefines(const LangOptions &Opts, 5852 MacroBuilder &Builder) const override { 5853 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5854 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5855 } 5856 }; 5857 5858 // ARM MinGW target 5859 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5860 public: 5861 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5862 : WindowsARMTargetInfo(Triple, Opts) { 5863 TheCXXABI.set(TargetCXXABI::GenericARM); 5864 } 5865 5866 void getTargetDefines(const LangOptions &Opts, 5867 MacroBuilder &Builder) const override { 5868 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5869 DefineStd(Builder, "WIN32", Opts); 5870 DefineStd(Builder, "WINNT", Opts); 5871 Builder.defineMacro("_ARM_"); 5872 addMinGWDefines(Opts, Builder); 5873 } 5874 }; 5875 5876 // ARM Cygwin target 5877 class CygwinARMTargetInfo : public ARMleTargetInfo { 5878 public: 5879 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5880 : ARMleTargetInfo(Triple, Opts) { 5881 TLSSupported = false; 5882 WCharType = UnsignedShort; 5883 DoubleAlign = LongLongAlign = 64; 5884 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5885 } 5886 void getTargetDefines(const LangOptions &Opts, 5887 MacroBuilder &Builder) const override { 5888 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5889 Builder.defineMacro("_ARM_"); 5890 Builder.defineMacro("__CYGWIN__"); 5891 Builder.defineMacro("__CYGWIN32__"); 5892 DefineStd(Builder, "unix", Opts); 5893 if (Opts.CPlusPlus) 5894 Builder.defineMacro("_GNU_SOURCE"); 5895 } 5896 }; 5897 5898 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5899 protected: 5900 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5901 MacroBuilder &Builder) const override { 5902 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5903 } 5904 5905 public: 5906 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5907 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5908 HasAlignMac68kSupport = true; 5909 // iOS always has 64-bit atomic instructions. 5910 // FIXME: This should be based off of the target features in 5911 // ARMleTargetInfo. 5912 MaxAtomicInlineWidth = 64; 5913 5914 if (Triple.isWatchABI()) { 5915 // Darwin on iOS uses a variant of the ARM C++ ABI. 5916 TheCXXABI.set(TargetCXXABI::WatchOS); 5917 5918 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5919 // size_t is long, it's a bit weird for it to be int. 5920 PtrDiffType = SignedLong; 5921 5922 // BOOL should be a real boolean on the new ABI 5923 UseSignedCharForObjCBool = false; 5924 } else 5925 TheCXXABI.set(TargetCXXABI::iOS); 5926 } 5927 }; 5928 5929 class AArch64TargetInfo : public TargetInfo { 5930 virtual void setDataLayout() = 0; 5931 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5932 static const char *const GCCRegNames[]; 5933 5934 enum FPUModeEnum { 5935 FPUMode, 5936 NeonMode 5937 }; 5938 5939 unsigned FPU; 5940 unsigned CRC; 5941 unsigned Crypto; 5942 unsigned Unaligned; 5943 unsigned V8_1A; 5944 5945 static const Builtin::Info BuiltinInfo[]; 5946 5947 std::string ABI; 5948 5949 public: 5950 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5951 : TargetInfo(Triple), ABI("aapcs") { 5952 if (getTriple().getOS() == llvm::Triple::NetBSD || 5953 getTriple().getOS() == llvm::Triple::OpenBSD) { 5954 WCharType = SignedInt; 5955 5956 // NetBSD apparently prefers consistency across ARM targets to consistency 5957 // across 64-bit targets. 5958 Int64Type = SignedLongLong; 5959 IntMaxType = SignedLongLong; 5960 } else { 5961 WCharType = UnsignedInt; 5962 Int64Type = SignedLong; 5963 IntMaxType = SignedLong; 5964 } 5965 5966 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5967 MaxVectorAlign = 128; 5968 MaxAtomicInlineWidth = 128; 5969 MaxAtomicPromoteWidth = 128; 5970 5971 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5972 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 5973 5974 // {} in inline assembly are neon specifiers, not assembly variant 5975 // specifiers. 5976 NoAsmVariants = true; 5977 5978 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5979 // contributes to the alignment of the containing aggregate in the same way 5980 // a plain (non bit-field) member of that type would, without exception for 5981 // zero-sized or anonymous bit-fields." 5982 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5983 UseZeroLengthBitfieldAlignment = true; 5984 5985 // AArch64 targets default to using the ARM C++ ABI. 5986 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5987 5988 if (Triple.getOS() == llvm::Triple::Linux) 5989 this->MCountName = "\01_mcount"; 5990 else if (Triple.getOS() == llvm::Triple::UnknownOS) 5991 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5992 } 5993 5994 StringRef getABI() const override { return ABI; } 5995 bool setABI(const std::string &Name) override { 5996 if (Name != "aapcs" && Name != "darwinpcs") 5997 return false; 5998 5999 ABI = Name; 6000 return true; 6001 } 6002 6003 bool setCPU(const std::string &Name) override { 6004 return Name == "generic" || 6005 llvm::AArch64::parseCPUArch(Name) != 6006 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6007 } 6008 6009 void getTargetDefines(const LangOptions &Opts, 6010 MacroBuilder &Builder) const override { 6011 // Target identification. 6012 Builder.defineMacro("__aarch64__"); 6013 6014 // Target properties. 6015 Builder.defineMacro("_LP64"); 6016 Builder.defineMacro("__LP64__"); 6017 6018 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6019 Builder.defineMacro("__ARM_ACLE", "200"); 6020 Builder.defineMacro("__ARM_ARCH", "8"); 6021 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6022 6023 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6024 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6025 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6026 6027 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6028 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6029 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6030 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6031 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6032 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6033 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6034 6035 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6036 6037 // 0xe implies support for half, single and double precision operations. 6038 Builder.defineMacro("__ARM_FP", "0xE"); 6039 6040 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6041 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6042 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6043 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6044 6045 if (Opts.UnsafeFPMath) 6046 Builder.defineMacro("__ARM_FP_FAST", "1"); 6047 6048 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6049 6050 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6051 Opts.ShortEnums ? "1" : "4"); 6052 6053 if (FPU == NeonMode) { 6054 Builder.defineMacro("__ARM_NEON", "1"); 6055 // 64-bit NEON supports half, single and double precision operations. 6056 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6057 } 6058 6059 if (CRC) 6060 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6061 6062 if (Crypto) 6063 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6064 6065 if (Unaligned) 6066 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6067 6068 if (V8_1A) 6069 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6070 6071 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6072 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6073 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6074 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6075 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6076 } 6077 6078 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6079 return llvm::makeArrayRef(BuiltinInfo, 6080 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6081 } 6082 6083 bool hasFeature(StringRef Feature) const override { 6084 return Feature == "aarch64" || 6085 Feature == "arm64" || 6086 Feature == "arm" || 6087 (Feature == "neon" && FPU == NeonMode); 6088 } 6089 6090 bool handleTargetFeatures(std::vector<std::string> &Features, 6091 DiagnosticsEngine &Diags) override { 6092 FPU = FPUMode; 6093 CRC = 0; 6094 Crypto = 0; 6095 Unaligned = 1; 6096 V8_1A = 0; 6097 6098 for (const auto &Feature : Features) { 6099 if (Feature == "+neon") 6100 FPU = NeonMode; 6101 if (Feature == "+crc") 6102 CRC = 1; 6103 if (Feature == "+crypto") 6104 Crypto = 1; 6105 if (Feature == "+strict-align") 6106 Unaligned = 0; 6107 if (Feature == "+v8.1a") 6108 V8_1A = 1; 6109 } 6110 6111 setDataLayout(); 6112 6113 return true; 6114 } 6115 6116 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6117 switch (CC) { 6118 case CC_C: 6119 case CC_Swift: 6120 case CC_PreserveMost: 6121 case CC_PreserveAll: 6122 return CCCR_OK; 6123 default: 6124 return CCCR_Warning; 6125 } 6126 } 6127 6128 bool isCLZForZeroUndef() const override { return false; } 6129 6130 BuiltinVaListKind getBuiltinVaListKind() const override { 6131 return TargetInfo::AArch64ABIBuiltinVaList; 6132 } 6133 6134 ArrayRef<const char *> getGCCRegNames() const override; 6135 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6136 6137 bool validateAsmConstraint(const char *&Name, 6138 TargetInfo::ConstraintInfo &Info) const override { 6139 switch (*Name) { 6140 default: 6141 return false; 6142 case 'w': // Floating point and SIMD registers (V0-V31) 6143 Info.setAllowsRegister(); 6144 return true; 6145 case 'I': // Constant that can be used with an ADD instruction 6146 case 'J': // Constant that can be used with a SUB instruction 6147 case 'K': // Constant that can be used with a 32-bit logical instruction 6148 case 'L': // Constant that can be used with a 64-bit logical instruction 6149 case 'M': // Constant that can be used as a 32-bit MOV immediate 6150 case 'N': // Constant that can be used as a 64-bit MOV immediate 6151 case 'Y': // Floating point constant zero 6152 case 'Z': // Integer constant zero 6153 return true; 6154 case 'Q': // A memory reference with base register and no offset 6155 Info.setAllowsMemory(); 6156 return true; 6157 case 'S': // A symbolic address 6158 Info.setAllowsRegister(); 6159 return true; 6160 case 'U': 6161 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6162 // Utf: A memory address suitable for ldp/stp in TF mode. 6163 // Usa: An absolute symbolic address. 6164 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6165 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6166 case 'z': // Zero register, wzr or xzr 6167 Info.setAllowsRegister(); 6168 return true; 6169 case 'x': // Floating point and SIMD registers (V0-V15) 6170 Info.setAllowsRegister(); 6171 return true; 6172 } 6173 return false; 6174 } 6175 6176 bool 6177 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6178 std::string &SuggestedModifier) const override { 6179 // Strip off constraint modifiers. 6180 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6181 Constraint = Constraint.substr(1); 6182 6183 switch (Constraint[0]) { 6184 default: 6185 return true; 6186 case 'z': 6187 case 'r': { 6188 switch (Modifier) { 6189 case 'x': 6190 case 'w': 6191 // For now assume that the person knows what they're 6192 // doing with the modifier. 6193 return true; 6194 default: 6195 // By default an 'r' constraint will be in the 'x' 6196 // registers. 6197 if (Size == 64) 6198 return true; 6199 6200 SuggestedModifier = "w"; 6201 return false; 6202 } 6203 } 6204 } 6205 } 6206 6207 const char *getClobbers() const override { return ""; } 6208 6209 int getEHDataRegisterNumber(unsigned RegNo) const override { 6210 if (RegNo == 0) 6211 return 0; 6212 if (RegNo == 1) 6213 return 1; 6214 return -1; 6215 } 6216 }; 6217 6218 const char *const AArch64TargetInfo::GCCRegNames[] = { 6219 // 32-bit Integer registers 6220 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6221 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6222 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6223 6224 // 64-bit Integer registers 6225 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6226 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6227 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6228 6229 // 32-bit floating point regsisters 6230 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6231 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6232 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6233 6234 // 64-bit floating point regsisters 6235 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6236 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6237 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6238 6239 // Vector registers 6240 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6241 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6242 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6243 }; 6244 6245 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6246 return llvm::makeArrayRef(GCCRegNames); 6247 } 6248 6249 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6250 { { "w31" }, "wsp" }, 6251 { { "x29" }, "fp" }, 6252 { { "x30" }, "lr" }, 6253 { { "x31" }, "sp" }, 6254 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6255 // don't want to substitute one of these for a different-sized one. 6256 }; 6257 6258 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6259 return llvm::makeArrayRef(GCCRegAliases); 6260 } 6261 6262 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6263 #define BUILTIN(ID, TYPE, ATTRS) \ 6264 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6265 #include "clang/Basic/BuiltinsNEON.def" 6266 6267 #define BUILTIN(ID, TYPE, ATTRS) \ 6268 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6269 #include "clang/Basic/BuiltinsAArch64.def" 6270 }; 6271 6272 class AArch64leTargetInfo : public AArch64TargetInfo { 6273 void setDataLayout() override { 6274 if (getTriple().isOSBinFormatMachO()) 6275 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6276 else 6277 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6278 } 6279 6280 public: 6281 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6282 : AArch64TargetInfo(Triple, Opts) { 6283 } 6284 void getTargetDefines(const LangOptions &Opts, 6285 MacroBuilder &Builder) const override { 6286 Builder.defineMacro("__AARCH64EL__"); 6287 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6288 } 6289 }; 6290 6291 class AArch64beTargetInfo : public AArch64TargetInfo { 6292 void setDataLayout() override { 6293 assert(!getTriple().isOSBinFormatMachO()); 6294 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6295 } 6296 6297 public: 6298 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6299 : AArch64TargetInfo(Triple, Opts) {} 6300 void getTargetDefines(const LangOptions &Opts, 6301 MacroBuilder &Builder) const override { 6302 Builder.defineMacro("__AARCH64EB__"); 6303 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6304 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6305 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6306 } 6307 }; 6308 6309 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6310 protected: 6311 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6312 MacroBuilder &Builder) const override { 6313 Builder.defineMacro("__AARCH64_SIMD__"); 6314 Builder.defineMacro("__ARM64_ARCH_8__"); 6315 Builder.defineMacro("__ARM_NEON__"); 6316 Builder.defineMacro("__LITTLE_ENDIAN__"); 6317 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6318 Builder.defineMacro("__arm64", "1"); 6319 Builder.defineMacro("__arm64__", "1"); 6320 6321 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6322 } 6323 6324 public: 6325 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6326 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6327 Int64Type = SignedLongLong; 6328 WCharType = SignedInt; 6329 UseSignedCharForObjCBool = false; 6330 6331 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6332 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6333 6334 TheCXXABI.set(TargetCXXABI::iOS64); 6335 } 6336 6337 BuiltinVaListKind getBuiltinVaListKind() const override { 6338 return TargetInfo::CharPtrBuiltinVaList; 6339 } 6340 }; 6341 6342 // Hexagon abstract base class 6343 class HexagonTargetInfo : public TargetInfo { 6344 static const Builtin::Info BuiltinInfo[]; 6345 static const char * const GCCRegNames[]; 6346 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6347 std::string CPU; 6348 bool HasHVX, HasHVXDouble; 6349 bool UseLongCalls; 6350 6351 public: 6352 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6353 : TargetInfo(Triple) { 6354 // Specify the vector alignment explicitly. For v512x1, the calculated 6355 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6356 // the required minimum of 64 bytes. 6357 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6358 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6359 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6360 SizeType = UnsignedInt; 6361 PtrDiffType = SignedInt; 6362 IntPtrType = SignedInt; 6363 6364 // {} in inline assembly are packet specifiers, not assembly variant 6365 // specifiers. 6366 NoAsmVariants = true; 6367 6368 LargeArrayMinWidth = 64; 6369 LargeArrayAlign = 64; 6370 UseBitFieldTypeAlignment = true; 6371 ZeroLengthBitfieldBoundary = 32; 6372 HasHVX = HasHVXDouble = false; 6373 UseLongCalls = false; 6374 } 6375 6376 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6377 return llvm::makeArrayRef(BuiltinInfo, 6378 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6379 } 6380 6381 bool validateAsmConstraint(const char *&Name, 6382 TargetInfo::ConstraintInfo &Info) const override { 6383 switch (*Name) { 6384 case 'v': 6385 case 'q': 6386 if (HasHVX) { 6387 Info.setAllowsRegister(); 6388 return true; 6389 } 6390 break; 6391 case 's': 6392 // Relocatable constant. 6393 return true; 6394 } 6395 return false; 6396 } 6397 6398 void getTargetDefines(const LangOptions &Opts, 6399 MacroBuilder &Builder) const override; 6400 6401 bool isCLZForZeroUndef() const override { return false; } 6402 6403 bool hasFeature(StringRef Feature) const override { 6404 return llvm::StringSwitch<bool>(Feature) 6405 .Case("hexagon", true) 6406 .Case("hvx", HasHVX) 6407 .Case("hvx-double", HasHVXDouble) 6408 .Case("long-calls", UseLongCalls) 6409 .Default(false); 6410 } 6411 6412 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6413 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6414 const override; 6415 6416 bool handleTargetFeatures(std::vector<std::string> &Features, 6417 DiagnosticsEngine &Diags) override; 6418 6419 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6420 bool Enabled) const override; 6421 6422 BuiltinVaListKind getBuiltinVaListKind() const override { 6423 return TargetInfo::CharPtrBuiltinVaList; 6424 } 6425 ArrayRef<const char *> getGCCRegNames() const override; 6426 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6427 const char *getClobbers() const override { 6428 return ""; 6429 } 6430 6431 static const char *getHexagonCPUSuffix(StringRef Name) { 6432 return llvm::StringSwitch<const char*>(Name) 6433 .Case("hexagonv4", "4") 6434 .Case("hexagonv5", "5") 6435 .Case("hexagonv55", "55") 6436 .Case("hexagonv60", "60") 6437 .Default(nullptr); 6438 } 6439 6440 bool setCPU(const std::string &Name) override { 6441 if (!getHexagonCPUSuffix(Name)) 6442 return false; 6443 CPU = Name; 6444 return true; 6445 } 6446 6447 int getEHDataRegisterNumber(unsigned RegNo) const override { 6448 return RegNo < 2 ? RegNo : -1; 6449 } 6450 }; 6451 6452 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6453 MacroBuilder &Builder) const { 6454 Builder.defineMacro("__qdsp6__", "1"); 6455 Builder.defineMacro("__hexagon__", "1"); 6456 6457 if (CPU == "hexagonv4") { 6458 Builder.defineMacro("__HEXAGON_V4__"); 6459 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6460 if (Opts.HexagonQdsp6Compat) { 6461 Builder.defineMacro("__QDSP6_V4__"); 6462 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6463 } 6464 } else if (CPU == "hexagonv5") { 6465 Builder.defineMacro("__HEXAGON_V5__"); 6466 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6467 if(Opts.HexagonQdsp6Compat) { 6468 Builder.defineMacro("__QDSP6_V5__"); 6469 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6470 } 6471 } else if (CPU == "hexagonv55") { 6472 Builder.defineMacro("__HEXAGON_V55__"); 6473 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6474 Builder.defineMacro("__QDSP6_V55__"); 6475 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6476 } else if (CPU == "hexagonv60") { 6477 Builder.defineMacro("__HEXAGON_V60__"); 6478 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6479 Builder.defineMacro("__QDSP6_V60__"); 6480 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6481 } 6482 6483 if (hasFeature("hvx")) { 6484 Builder.defineMacro("__HVX__"); 6485 if (hasFeature("hvx-double")) 6486 Builder.defineMacro("__HVXDBL__"); 6487 } 6488 } 6489 6490 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6491 DiagnosticsEngine &Diags, StringRef CPU, 6492 const std::vector<std::string> &FeaturesVec) const { 6493 // Default for v60: -hvx, -hvx-double. 6494 Features["hvx"] = false; 6495 Features["hvx-double"] = false; 6496 Features["long-calls"] = false; 6497 6498 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6499 } 6500 6501 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6502 DiagnosticsEngine &Diags) { 6503 for (auto &F : Features) { 6504 if (F == "+hvx") 6505 HasHVX = true; 6506 else if (F == "-hvx") 6507 HasHVX = HasHVXDouble = false; 6508 else if (F == "+hvx-double") 6509 HasHVX = HasHVXDouble = true; 6510 else if (F == "-hvx-double") 6511 HasHVXDouble = false; 6512 6513 if (F == "+long-calls") 6514 UseLongCalls = true; 6515 else if (F == "-long-calls") 6516 UseLongCalls = false; 6517 } 6518 return true; 6519 } 6520 6521 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6522 StringRef Name, bool Enabled) const { 6523 if (Enabled) { 6524 if (Name == "hvx-double") 6525 Features["hvx"] = true; 6526 } else { 6527 if (Name == "hvx") 6528 Features["hvx-double"] = false; 6529 } 6530 Features[Name] = Enabled; 6531 } 6532 6533 const char *const HexagonTargetInfo::GCCRegNames[] = { 6534 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6535 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6536 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6537 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6538 "p0", "p1", "p2", "p3", 6539 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6540 }; 6541 6542 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6543 return llvm::makeArrayRef(GCCRegNames); 6544 } 6545 6546 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6547 { { "sp" }, "r29" }, 6548 { { "fp" }, "r30" }, 6549 { { "lr" }, "r31" }, 6550 }; 6551 6552 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6553 return llvm::makeArrayRef(GCCRegAliases); 6554 } 6555 6556 6557 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6558 #define BUILTIN(ID, TYPE, ATTRS) \ 6559 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6560 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6561 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6562 #include "clang/Basic/BuiltinsHexagon.def" 6563 }; 6564 6565 class LanaiTargetInfo : public TargetInfo { 6566 // Class for Lanai (32-bit). 6567 // The CPU profiles supported by the Lanai backend 6568 enum CPUKind { 6569 CK_NONE, 6570 CK_V11, 6571 } CPU; 6572 6573 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6574 static const char *const GCCRegNames[]; 6575 6576 public: 6577 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6578 : TargetInfo(Triple) { 6579 // Description string has to be kept in sync with backend. 6580 resetDataLayout("E" // Big endian 6581 "-m:e" // ELF name manging 6582 "-p:32:32" // 32 bit pointers, 32 bit aligned 6583 "-i64:64" // 64 bit integers, 64 bit aligned 6584 "-a:0:32" // 32 bit alignment of objects of aggregate type 6585 "-n32" // 32 bit native integer width 6586 "-S64" // 64 bit natural stack alignment 6587 ); 6588 6589 // Setting RegParmMax equal to what mregparm was set to in the old 6590 // toolchain 6591 RegParmMax = 4; 6592 6593 // Set the default CPU to V11 6594 CPU = CK_V11; 6595 6596 // Temporary approach to make everything at least word-aligned and allow for 6597 // safely casting between pointers with different alignment requirements. 6598 // TODO: Remove this when there are no more cast align warnings on the 6599 // firmware. 6600 MinGlobalAlign = 32; 6601 } 6602 6603 void getTargetDefines(const LangOptions &Opts, 6604 MacroBuilder &Builder) const override { 6605 // Define __lanai__ when building for target lanai. 6606 Builder.defineMacro("__lanai__"); 6607 6608 // Set define for the CPU specified. 6609 switch (CPU) { 6610 case CK_V11: 6611 Builder.defineMacro("__LANAI_V11__"); 6612 break; 6613 case CK_NONE: 6614 llvm_unreachable("Unhandled target CPU"); 6615 } 6616 } 6617 6618 bool setCPU(const std::string &Name) override { 6619 CPU = llvm::StringSwitch<CPUKind>(Name) 6620 .Case("v11", CK_V11) 6621 .Default(CK_NONE); 6622 6623 return CPU != CK_NONE; 6624 } 6625 6626 bool hasFeature(StringRef Feature) const override { 6627 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6628 } 6629 6630 ArrayRef<const char *> getGCCRegNames() const override; 6631 6632 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6633 6634 BuiltinVaListKind getBuiltinVaListKind() const override { 6635 return TargetInfo::VoidPtrBuiltinVaList; 6636 } 6637 6638 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6639 6640 bool validateAsmConstraint(const char *&Name, 6641 TargetInfo::ConstraintInfo &info) const override { 6642 return false; 6643 } 6644 6645 const char *getClobbers() const override { return ""; } 6646 }; 6647 6648 const char *const LanaiTargetInfo::GCCRegNames[] = { 6649 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6650 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6651 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6652 6653 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6654 return llvm::makeArrayRef(GCCRegNames); 6655 } 6656 6657 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6658 {{"pc"}, "r2"}, 6659 {{"sp"}, "r4"}, 6660 {{"fp"}, "r5"}, 6661 {{"rv"}, "r8"}, 6662 {{"rr1"}, "r10"}, 6663 {{"rr2"}, "r11"}, 6664 {{"rca"}, "r15"}, 6665 }; 6666 6667 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6668 return llvm::makeArrayRef(GCCRegAliases); 6669 } 6670 6671 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6672 class SparcTargetInfo : public TargetInfo { 6673 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6674 static const char * const GCCRegNames[]; 6675 bool SoftFloat; 6676 public: 6677 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6678 : TargetInfo(Triple), SoftFloat(false) {} 6679 6680 int getEHDataRegisterNumber(unsigned RegNo) const override { 6681 if (RegNo == 0) return 24; 6682 if (RegNo == 1) return 25; 6683 return -1; 6684 } 6685 6686 bool handleTargetFeatures(std::vector<std::string> &Features, 6687 DiagnosticsEngine &Diags) override { 6688 // Check if software floating point is enabled 6689 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6690 if (Feature != Features.end()) { 6691 SoftFloat = true; 6692 } 6693 return true; 6694 } 6695 void getTargetDefines(const LangOptions &Opts, 6696 MacroBuilder &Builder) const override { 6697 DefineStd(Builder, "sparc", Opts); 6698 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6699 6700 if (SoftFloat) 6701 Builder.defineMacro("SOFT_FLOAT", "1"); 6702 } 6703 6704 bool hasFeature(StringRef Feature) const override { 6705 return llvm::StringSwitch<bool>(Feature) 6706 .Case("softfloat", SoftFloat) 6707 .Case("sparc", true) 6708 .Default(false); 6709 } 6710 6711 bool hasSjLjLowering() const override { 6712 return true; 6713 } 6714 6715 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6716 // FIXME: Implement! 6717 return None; 6718 } 6719 BuiltinVaListKind getBuiltinVaListKind() const override { 6720 return TargetInfo::VoidPtrBuiltinVaList; 6721 } 6722 ArrayRef<const char *> getGCCRegNames() const override; 6723 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6724 bool validateAsmConstraint(const char *&Name, 6725 TargetInfo::ConstraintInfo &info) const override { 6726 // FIXME: Implement! 6727 switch (*Name) { 6728 case 'I': // Signed 13-bit constant 6729 case 'J': // Zero 6730 case 'K': // 32-bit constant with the low 12 bits clear 6731 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6732 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6733 case 'N': // Same as 'K' but zext (required for SIMode) 6734 case 'O': // The constant 4096 6735 return true; 6736 } 6737 return false; 6738 } 6739 const char *getClobbers() const override { 6740 // FIXME: Implement! 6741 return ""; 6742 } 6743 6744 // No Sparc V7 for now, the backend doesn't support it anyway. 6745 enum CPUKind { 6746 CK_GENERIC, 6747 CK_V8, 6748 CK_SUPERSPARC, 6749 CK_SPARCLITE, 6750 CK_F934, 6751 CK_HYPERSPARC, 6752 CK_SPARCLITE86X, 6753 CK_SPARCLET, 6754 CK_TSC701, 6755 CK_V9, 6756 CK_ULTRASPARC, 6757 CK_ULTRASPARC3, 6758 CK_NIAGARA, 6759 CK_NIAGARA2, 6760 CK_NIAGARA3, 6761 CK_NIAGARA4, 6762 CK_MYRIAD2100, 6763 CK_MYRIAD2150, 6764 CK_MYRIAD2450, 6765 CK_LEON2, 6766 CK_LEON2_AT697E, 6767 CK_LEON2_AT697F, 6768 CK_LEON3, 6769 CK_LEON3_UT699, 6770 CK_LEON3_GR712RC, 6771 CK_LEON4, 6772 CK_LEON4_GR740 6773 } CPU = CK_GENERIC; 6774 6775 enum CPUGeneration { 6776 CG_V8, 6777 CG_V9, 6778 }; 6779 6780 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6781 switch (Kind) { 6782 case CK_GENERIC: 6783 case CK_V8: 6784 case CK_SUPERSPARC: 6785 case CK_SPARCLITE: 6786 case CK_F934: 6787 case CK_HYPERSPARC: 6788 case CK_SPARCLITE86X: 6789 case CK_SPARCLET: 6790 case CK_TSC701: 6791 case CK_MYRIAD2100: 6792 case CK_MYRIAD2150: 6793 case CK_MYRIAD2450: 6794 case CK_LEON2: 6795 case CK_LEON2_AT697E: 6796 case CK_LEON2_AT697F: 6797 case CK_LEON3: 6798 case CK_LEON3_UT699: 6799 case CK_LEON3_GR712RC: 6800 case CK_LEON4: 6801 case CK_LEON4_GR740: 6802 return CG_V8; 6803 case CK_V9: 6804 case CK_ULTRASPARC: 6805 case CK_ULTRASPARC3: 6806 case CK_NIAGARA: 6807 case CK_NIAGARA2: 6808 case CK_NIAGARA3: 6809 case CK_NIAGARA4: 6810 return CG_V9; 6811 } 6812 llvm_unreachable("Unexpected CPU kind"); 6813 } 6814 6815 CPUKind getCPUKind(StringRef Name) const { 6816 return llvm::StringSwitch<CPUKind>(Name) 6817 .Case("v8", CK_V8) 6818 .Case("supersparc", CK_SUPERSPARC) 6819 .Case("sparclite", CK_SPARCLITE) 6820 .Case("f934", CK_F934) 6821 .Case("hypersparc", CK_HYPERSPARC) 6822 .Case("sparclite86x", CK_SPARCLITE86X) 6823 .Case("sparclet", CK_SPARCLET) 6824 .Case("tsc701", CK_TSC701) 6825 .Case("v9", CK_V9) 6826 .Case("ultrasparc", CK_ULTRASPARC) 6827 .Case("ultrasparc3", CK_ULTRASPARC3) 6828 .Case("niagara", CK_NIAGARA) 6829 .Case("niagara2", CK_NIAGARA2) 6830 .Case("niagara3", CK_NIAGARA3) 6831 .Case("niagara4", CK_NIAGARA4) 6832 .Case("ma2100", CK_MYRIAD2100) 6833 .Case("ma2150", CK_MYRIAD2150) 6834 .Case("ma2450", CK_MYRIAD2450) 6835 // FIXME: the myriad2[.n] spellings are obsolete, 6836 // but a grace period is needed to allow updating dependent builds. 6837 .Case("myriad2", CK_MYRIAD2100) 6838 .Case("myriad2.1", CK_MYRIAD2100) 6839 .Case("myriad2.2", CK_MYRIAD2150) 6840 .Case("leon2", CK_LEON2) 6841 .Case("at697e", CK_LEON2_AT697E) 6842 .Case("at697f", CK_LEON2_AT697F) 6843 .Case("leon3", CK_LEON3) 6844 .Case("ut699", CK_LEON3_UT699) 6845 .Case("gr712rc", CK_LEON3_GR712RC) 6846 .Case("leon4", CK_LEON4) 6847 .Case("gr740", CK_LEON4_GR740) 6848 .Default(CK_GENERIC); 6849 } 6850 6851 bool setCPU(const std::string &Name) override { 6852 CPU = getCPUKind(Name); 6853 return CPU != CK_GENERIC; 6854 } 6855 }; 6856 6857 const char * const SparcTargetInfo::GCCRegNames[] = { 6858 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6859 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6860 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6861 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6862 }; 6863 6864 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6865 return llvm::makeArrayRef(GCCRegNames); 6866 } 6867 6868 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6869 { { "g0" }, "r0" }, 6870 { { "g1" }, "r1" }, 6871 { { "g2" }, "r2" }, 6872 { { "g3" }, "r3" }, 6873 { { "g4" }, "r4" }, 6874 { { "g5" }, "r5" }, 6875 { { "g6" }, "r6" }, 6876 { { "g7" }, "r7" }, 6877 { { "o0" }, "r8" }, 6878 { { "o1" }, "r9" }, 6879 { { "o2" }, "r10" }, 6880 { { "o3" }, "r11" }, 6881 { { "o4" }, "r12" }, 6882 { { "o5" }, "r13" }, 6883 { { "o6", "sp" }, "r14" }, 6884 { { "o7" }, "r15" }, 6885 { { "l0" }, "r16" }, 6886 { { "l1" }, "r17" }, 6887 { { "l2" }, "r18" }, 6888 { { "l3" }, "r19" }, 6889 { { "l4" }, "r20" }, 6890 { { "l5" }, "r21" }, 6891 { { "l6" }, "r22" }, 6892 { { "l7" }, "r23" }, 6893 { { "i0" }, "r24" }, 6894 { { "i1" }, "r25" }, 6895 { { "i2" }, "r26" }, 6896 { { "i3" }, "r27" }, 6897 { { "i4" }, "r28" }, 6898 { { "i5" }, "r29" }, 6899 { { "i6", "fp" }, "r30" }, 6900 { { "i7" }, "r31" }, 6901 }; 6902 6903 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6904 return llvm::makeArrayRef(GCCRegAliases); 6905 } 6906 6907 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6908 class SparcV8TargetInfo : public SparcTargetInfo { 6909 public: 6910 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6911 : SparcTargetInfo(Triple, Opts) { 6912 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6913 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6914 switch (getTriple().getOS()) { 6915 default: 6916 SizeType = UnsignedInt; 6917 IntPtrType = SignedInt; 6918 PtrDiffType = SignedInt; 6919 break; 6920 case llvm::Triple::NetBSD: 6921 case llvm::Triple::OpenBSD: 6922 SizeType = UnsignedLong; 6923 IntPtrType = SignedLong; 6924 PtrDiffType = SignedLong; 6925 break; 6926 } 6927 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 6928 // on up to 64 bits. 6929 MaxAtomicPromoteWidth = 64; 6930 MaxAtomicInlineWidth = 32; 6931 } 6932 6933 void getTargetDefines(const LangOptions &Opts, 6934 MacroBuilder &Builder) const override { 6935 SparcTargetInfo::getTargetDefines(Opts, Builder); 6936 switch (getCPUGeneration(CPU)) { 6937 case CG_V8: 6938 Builder.defineMacro("__sparcv8"); 6939 if (getTriple().getOS() != llvm::Triple::Solaris) 6940 Builder.defineMacro("__sparcv8__"); 6941 break; 6942 case CG_V9: 6943 Builder.defineMacro("__sparcv9"); 6944 if (getTriple().getOS() != llvm::Triple::Solaris) { 6945 Builder.defineMacro("__sparcv9__"); 6946 Builder.defineMacro("__sparc_v9__"); 6947 } 6948 break; 6949 } 6950 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6951 std::string MyriadArchValue, Myriad2Value; 6952 Builder.defineMacro("__sparc_v8__"); 6953 Builder.defineMacro("__leon__"); 6954 switch (CPU) { 6955 case CK_MYRIAD2150: 6956 MyriadArchValue = "__ma2150"; 6957 Myriad2Value = "2"; 6958 break; 6959 case CK_MYRIAD2450: 6960 MyriadArchValue = "__ma2450"; 6961 Myriad2Value = "2"; 6962 break; 6963 default: 6964 MyriadArchValue = "__ma2100"; 6965 Myriad2Value = "1"; 6966 break; 6967 } 6968 Builder.defineMacro(MyriadArchValue, "1"); 6969 Builder.defineMacro(MyriadArchValue+"__", "1"); 6970 Builder.defineMacro("__myriad2__", Myriad2Value); 6971 Builder.defineMacro("__myriad2", Myriad2Value); 6972 } 6973 } 6974 6975 bool hasSjLjLowering() const override { 6976 return true; 6977 } 6978 }; 6979 6980 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6981 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6982 public: 6983 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6984 : SparcV8TargetInfo(Triple, Opts) { 6985 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6986 } 6987 }; 6988 6989 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6990 class SparcV9TargetInfo : public SparcTargetInfo { 6991 public: 6992 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6993 : SparcTargetInfo(Triple, Opts) { 6994 // FIXME: Support Sparc quad-precision long double? 6995 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6996 // This is an LP64 platform. 6997 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6998 6999 // OpenBSD uses long long for int64_t and intmax_t. 7000 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7001 IntMaxType = SignedLongLong; 7002 else 7003 IntMaxType = SignedLong; 7004 Int64Type = IntMaxType; 7005 7006 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7007 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7008 LongDoubleWidth = 128; 7009 LongDoubleAlign = 128; 7010 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7011 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7012 } 7013 7014 void getTargetDefines(const LangOptions &Opts, 7015 MacroBuilder &Builder) const override { 7016 SparcTargetInfo::getTargetDefines(Opts, Builder); 7017 Builder.defineMacro("__sparcv9"); 7018 Builder.defineMacro("__arch64__"); 7019 // Solaris doesn't need these variants, but the BSDs do. 7020 if (getTriple().getOS() != llvm::Triple::Solaris) { 7021 Builder.defineMacro("__sparc64__"); 7022 Builder.defineMacro("__sparc_v9__"); 7023 Builder.defineMacro("__sparcv9__"); 7024 } 7025 } 7026 7027 bool setCPU(const std::string &Name) override { 7028 if (!SparcTargetInfo::setCPU(Name)) 7029 return false; 7030 return getCPUGeneration(CPU) == CG_V9; 7031 } 7032 }; 7033 7034 class SystemZTargetInfo : public TargetInfo { 7035 static const Builtin::Info BuiltinInfo[]; 7036 static const char *const GCCRegNames[]; 7037 std::string CPU; 7038 bool HasTransactionalExecution; 7039 bool HasVector; 7040 7041 public: 7042 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7043 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 7044 HasVector(false) { 7045 IntMaxType = SignedLong; 7046 Int64Type = SignedLong; 7047 TLSSupported = true; 7048 IntWidth = IntAlign = 32; 7049 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7050 PointerWidth = PointerAlign = 64; 7051 LongDoubleWidth = 128; 7052 LongDoubleAlign = 64; 7053 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7054 DefaultAlignForAttributeAligned = 64; 7055 MinGlobalAlign = 16; 7056 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7057 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7058 } 7059 void getTargetDefines(const LangOptions &Opts, 7060 MacroBuilder &Builder) const override { 7061 Builder.defineMacro("__s390__"); 7062 Builder.defineMacro("__s390x__"); 7063 Builder.defineMacro("__zarch__"); 7064 Builder.defineMacro("__LONG_DOUBLE_128__"); 7065 7066 const std::string ISARev = llvm::StringSwitch<std::string>(CPU) 7067 .Cases("arch8", "z10", "8") 7068 .Cases("arch9", "z196", "9") 7069 .Cases("arch10", "zEC12", "10") 7070 .Cases("arch11", "z13", "11") 7071 .Default(""); 7072 if (!ISARev.empty()) 7073 Builder.defineMacro("__ARCH__", ISARev); 7074 7075 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7076 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7077 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7078 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7079 7080 if (HasTransactionalExecution) 7081 Builder.defineMacro("__HTM__"); 7082 if (HasVector) 7083 Builder.defineMacro("__VX__"); 7084 if (Opts.ZVector) 7085 Builder.defineMacro("__VEC__", "10301"); 7086 } 7087 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7088 return llvm::makeArrayRef(BuiltinInfo, 7089 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7090 } 7091 7092 ArrayRef<const char *> getGCCRegNames() const override; 7093 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7094 // No aliases. 7095 return None; 7096 } 7097 bool validateAsmConstraint(const char *&Name, 7098 TargetInfo::ConstraintInfo &info) const override; 7099 const char *getClobbers() const override { 7100 // FIXME: Is this really right? 7101 return ""; 7102 } 7103 BuiltinVaListKind getBuiltinVaListKind() const override { 7104 return TargetInfo::SystemZBuiltinVaList; 7105 } 7106 bool setCPU(const std::string &Name) override { 7107 CPU = Name; 7108 bool CPUKnown = llvm::StringSwitch<bool>(Name) 7109 .Case("z10", true) 7110 .Case("arch8", true) 7111 .Case("z196", true) 7112 .Case("arch9", true) 7113 .Case("zEC12", true) 7114 .Case("arch10", true) 7115 .Case("z13", true) 7116 .Case("arch11", true) 7117 .Default(false); 7118 7119 return CPUKnown; 7120 } 7121 bool 7122 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7123 StringRef CPU, 7124 const std::vector<std::string> &FeaturesVec) const override { 7125 if (CPU == "zEC12" || CPU == "arch10") 7126 Features["transactional-execution"] = true; 7127 if (CPU == "z13" || CPU == "arch11") { 7128 Features["transactional-execution"] = true; 7129 Features["vector"] = true; 7130 } 7131 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7132 } 7133 7134 bool handleTargetFeatures(std::vector<std::string> &Features, 7135 DiagnosticsEngine &Diags) override { 7136 HasTransactionalExecution = false; 7137 for (const auto &Feature : Features) { 7138 if (Feature == "+transactional-execution") 7139 HasTransactionalExecution = true; 7140 else if (Feature == "+vector") 7141 HasVector = true; 7142 } 7143 // If we use the vector ABI, vector types are 64-bit aligned. 7144 if (HasVector) { 7145 MaxVectorAlign = 64; 7146 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7147 "-v128:64-a:8:16-n32:64"); 7148 } 7149 return true; 7150 } 7151 7152 bool hasFeature(StringRef Feature) const override { 7153 return llvm::StringSwitch<bool>(Feature) 7154 .Case("systemz", true) 7155 .Case("htm", HasTransactionalExecution) 7156 .Case("vx", HasVector) 7157 .Default(false); 7158 } 7159 7160 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7161 switch (CC) { 7162 case CC_C: 7163 case CC_Swift: 7164 return CCCR_OK; 7165 default: 7166 return CCCR_Warning; 7167 } 7168 } 7169 7170 StringRef getABI() const override { 7171 if (HasVector) 7172 return "vector"; 7173 return ""; 7174 } 7175 7176 bool useFloat128ManglingForLongDouble() const override { 7177 return true; 7178 } 7179 }; 7180 7181 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7182 #define BUILTIN(ID, TYPE, ATTRS) \ 7183 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7184 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7185 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7186 #include "clang/Basic/BuiltinsSystemZ.def" 7187 }; 7188 7189 const char *const SystemZTargetInfo::GCCRegNames[] = { 7190 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7191 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7192 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7193 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7194 }; 7195 7196 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7197 return llvm::makeArrayRef(GCCRegNames); 7198 } 7199 7200 bool SystemZTargetInfo:: 7201 validateAsmConstraint(const char *&Name, 7202 TargetInfo::ConstraintInfo &Info) const { 7203 switch (*Name) { 7204 default: 7205 return false; 7206 7207 case 'a': // Address register 7208 case 'd': // Data register (equivalent to 'r') 7209 case 'f': // Floating-point register 7210 Info.setAllowsRegister(); 7211 return true; 7212 7213 case 'I': // Unsigned 8-bit constant 7214 case 'J': // Unsigned 12-bit constant 7215 case 'K': // Signed 16-bit constant 7216 case 'L': // Signed 20-bit displacement (on all targets we support) 7217 case 'M': // 0x7fffffff 7218 return true; 7219 7220 case 'Q': // Memory with base and unsigned 12-bit displacement 7221 case 'R': // Likewise, plus an index 7222 case 'S': // Memory with base and signed 20-bit displacement 7223 case 'T': // Likewise, plus an index 7224 Info.setAllowsMemory(); 7225 return true; 7226 } 7227 } 7228 7229 class MSP430TargetInfo : public TargetInfo { 7230 static const char *const GCCRegNames[]; 7231 7232 public: 7233 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7234 : TargetInfo(Triple) { 7235 TLSSupported = false; 7236 IntWidth = 16; 7237 IntAlign = 16; 7238 LongWidth = 32; 7239 LongLongWidth = 64; 7240 LongAlign = LongLongAlign = 16; 7241 PointerWidth = 16; 7242 PointerAlign = 16; 7243 SuitableAlign = 16; 7244 SizeType = UnsignedInt; 7245 IntMaxType = SignedLongLong; 7246 IntPtrType = SignedInt; 7247 PtrDiffType = SignedInt; 7248 SigAtomicType = SignedLong; 7249 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7250 } 7251 void getTargetDefines(const LangOptions &Opts, 7252 MacroBuilder &Builder) const override { 7253 Builder.defineMacro("MSP430"); 7254 Builder.defineMacro("__MSP430__"); 7255 // FIXME: defines for different 'flavours' of MCU 7256 } 7257 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7258 // FIXME: Implement. 7259 return None; 7260 } 7261 bool hasFeature(StringRef Feature) const override { 7262 return Feature == "msp430"; 7263 } 7264 ArrayRef<const char *> getGCCRegNames() const override; 7265 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7266 // No aliases. 7267 return None; 7268 } 7269 bool validateAsmConstraint(const char *&Name, 7270 TargetInfo::ConstraintInfo &info) const override { 7271 // FIXME: implement 7272 switch (*Name) { 7273 case 'K': // the constant 1 7274 case 'L': // constant -1^20 .. 1^19 7275 case 'M': // constant 1-4: 7276 return true; 7277 } 7278 // No target constraints for now. 7279 return false; 7280 } 7281 const char *getClobbers() const override { 7282 // FIXME: Is this really right? 7283 return ""; 7284 } 7285 BuiltinVaListKind getBuiltinVaListKind() const override { 7286 // FIXME: implement 7287 return TargetInfo::CharPtrBuiltinVaList; 7288 } 7289 }; 7290 7291 const char *const MSP430TargetInfo::GCCRegNames[] = { 7292 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7293 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7294 7295 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7296 return llvm::makeArrayRef(GCCRegNames); 7297 } 7298 7299 // LLVM and Clang cannot be used directly to output native binaries for 7300 // target, but is used to compile C code to llvm bitcode with correct 7301 // type and alignment information. 7302 // 7303 // TCE uses the llvm bitcode as input and uses it for generating customized 7304 // target processor and program binary. TCE co-design environment is 7305 // publicly available in http://tce.cs.tut.fi 7306 7307 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7308 3, // opencl_global 7309 4, // opencl_local 7310 5, // opencl_constant 7311 // FIXME: generic has to be added to the target 7312 0, // opencl_generic 7313 0, // cuda_device 7314 0, // cuda_constant 7315 0 // cuda_shared 7316 }; 7317 7318 class TCETargetInfo : public TargetInfo { 7319 public: 7320 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7321 : TargetInfo(Triple) { 7322 TLSSupported = false; 7323 IntWidth = 32; 7324 LongWidth = LongLongWidth = 32; 7325 PointerWidth = 32; 7326 IntAlign = 32; 7327 LongAlign = LongLongAlign = 32; 7328 PointerAlign = 32; 7329 SuitableAlign = 32; 7330 SizeType = UnsignedInt; 7331 IntMaxType = SignedLong; 7332 IntPtrType = SignedInt; 7333 PtrDiffType = SignedInt; 7334 FloatWidth = 32; 7335 FloatAlign = 32; 7336 DoubleWidth = 32; 7337 DoubleAlign = 32; 7338 LongDoubleWidth = 32; 7339 LongDoubleAlign = 32; 7340 FloatFormat = &llvm::APFloat::IEEEsingle(); 7341 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7342 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7343 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7344 "i16:16:32-i32:32:32-i64:32:32-" 7345 "f32:32:32-f64:32:32-v64:32:32-" 7346 "v128:32:32-v256:32:32-v512:32:32-" 7347 "v1024:32:32-a0:0:32-n32"); 7348 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7349 UseAddrSpaceMapMangling = true; 7350 } 7351 7352 void getTargetDefines(const LangOptions &Opts, 7353 MacroBuilder &Builder) const override { 7354 DefineStd(Builder, "tce", Opts); 7355 Builder.defineMacro("__TCE__"); 7356 Builder.defineMacro("__TCE_V1__"); 7357 } 7358 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7359 7360 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7361 const char *getClobbers() const override { return ""; } 7362 BuiltinVaListKind getBuiltinVaListKind() const override { 7363 return TargetInfo::VoidPtrBuiltinVaList; 7364 } 7365 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7366 bool validateAsmConstraint(const char *&Name, 7367 TargetInfo::ConstraintInfo &info) const override { 7368 return true; 7369 } 7370 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7371 return None; 7372 } 7373 }; 7374 7375 class TCELETargetInfo : public TCETargetInfo { 7376 public: 7377 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7378 : TCETargetInfo(Triple, Opts) { 7379 BigEndian = false; 7380 7381 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7382 "i16:16:32-i32:32:32-i64:32:32-" 7383 "f32:32:32-f64:32:32-v64:32:32-" 7384 "v128:32:32-v256:32:32-v512:32:32-" 7385 "v1024:32:32-a0:0:32-n32"); 7386 7387 } 7388 7389 virtual void getTargetDefines(const LangOptions &Opts, 7390 MacroBuilder &Builder) const { 7391 DefineStd(Builder, "tcele", Opts); 7392 Builder.defineMacro("__TCE__"); 7393 Builder.defineMacro("__TCE_V1__"); 7394 Builder.defineMacro("__TCELE__"); 7395 Builder.defineMacro("__TCELE_V1__"); 7396 } 7397 7398 }; 7399 7400 class BPFTargetInfo : public TargetInfo { 7401 public: 7402 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7403 : TargetInfo(Triple) { 7404 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7405 SizeType = UnsignedLong; 7406 PtrDiffType = SignedLong; 7407 IntPtrType = SignedLong; 7408 IntMaxType = SignedLong; 7409 Int64Type = SignedLong; 7410 RegParmMax = 5; 7411 if (Triple.getArch() == llvm::Triple::bpfeb) { 7412 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7413 } else { 7414 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7415 } 7416 MaxAtomicPromoteWidth = 64; 7417 MaxAtomicInlineWidth = 64; 7418 TLSSupported = false; 7419 } 7420 void getTargetDefines(const LangOptions &Opts, 7421 MacroBuilder &Builder) const override { 7422 DefineStd(Builder, "bpf", Opts); 7423 Builder.defineMacro("__BPF__"); 7424 } 7425 bool hasFeature(StringRef Feature) const override { 7426 return Feature == "bpf"; 7427 } 7428 7429 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7430 const char *getClobbers() const override { 7431 return ""; 7432 } 7433 BuiltinVaListKind getBuiltinVaListKind() const override { 7434 return TargetInfo::VoidPtrBuiltinVaList; 7435 } 7436 ArrayRef<const char *> getGCCRegNames() const override { 7437 return None; 7438 } 7439 bool validateAsmConstraint(const char *&Name, 7440 TargetInfo::ConstraintInfo &info) const override { 7441 return true; 7442 } 7443 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7444 return None; 7445 } 7446 }; 7447 7448 class MipsTargetInfo : public TargetInfo { 7449 void setDataLayout() { 7450 StringRef Layout; 7451 7452 if (ABI == "o32") 7453 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7454 else if (ABI == "n32") 7455 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7456 else if (ABI == "n64") 7457 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7458 else 7459 llvm_unreachable("Invalid ABI"); 7460 7461 if (BigEndian) 7462 resetDataLayout(("E-" + Layout).str()); 7463 else 7464 resetDataLayout(("e-" + Layout).str()); 7465 } 7466 7467 7468 static const Builtin::Info BuiltinInfo[]; 7469 std::string CPU; 7470 bool IsMips16; 7471 bool IsMicromips; 7472 bool IsNan2008; 7473 bool IsSingleFloat; 7474 bool IsNoABICalls; 7475 bool CanUseBSDABICalls; 7476 enum MipsFloatABI { 7477 HardFloat, SoftFloat 7478 } FloatABI; 7479 enum DspRevEnum { 7480 NoDSP, DSP1, DSP2 7481 } DspRev; 7482 bool HasMSA; 7483 7484 protected: 7485 bool HasFP64; 7486 std::string ABI; 7487 7488 public: 7489 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7490 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7491 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 7492 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 7493 HasMSA(false), HasFP64(false) { 7494 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7495 7496 setABI((getTriple().getArch() == llvm::Triple::mips || 7497 getTriple().getArch() == llvm::Triple::mipsel) 7498 ? "o32" 7499 : "n64"); 7500 7501 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7502 7503 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 7504 Triple.getOS() == llvm::Triple::OpenBSD; 7505 } 7506 7507 bool isNaN2008Default() const { 7508 return CPU == "mips32r6" || CPU == "mips64r6"; 7509 } 7510 7511 bool isFP64Default() const { 7512 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7513 } 7514 7515 bool isNan2008() const override { 7516 return IsNan2008; 7517 } 7518 7519 bool processorSupportsGPR64() const { 7520 return llvm::StringSwitch<bool>(CPU) 7521 .Case("mips3", true) 7522 .Case("mips4", true) 7523 .Case("mips5", true) 7524 .Case("mips64", true) 7525 .Case("mips64r2", true) 7526 .Case("mips64r3", true) 7527 .Case("mips64r5", true) 7528 .Case("mips64r6", true) 7529 .Case("octeon", true) 7530 .Default(false); 7531 return false; 7532 } 7533 7534 StringRef getABI() const override { return ABI; } 7535 bool setABI(const std::string &Name) override { 7536 if (Name == "o32") { 7537 setO32ABITypes(); 7538 ABI = Name; 7539 return true; 7540 } 7541 7542 if (Name == "n32") { 7543 setN32ABITypes(); 7544 ABI = Name; 7545 return true; 7546 } 7547 if (Name == "n64") { 7548 setN64ABITypes(); 7549 ABI = Name; 7550 return true; 7551 } 7552 return false; 7553 } 7554 7555 void setO32ABITypes() { 7556 Int64Type = SignedLongLong; 7557 IntMaxType = Int64Type; 7558 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7559 LongDoubleWidth = LongDoubleAlign = 64; 7560 LongWidth = LongAlign = 32; 7561 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7562 PointerWidth = PointerAlign = 32; 7563 PtrDiffType = SignedInt; 7564 SizeType = UnsignedInt; 7565 SuitableAlign = 64; 7566 } 7567 7568 void setN32N64ABITypes() { 7569 LongDoubleWidth = LongDoubleAlign = 128; 7570 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7571 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7572 LongDoubleWidth = LongDoubleAlign = 64; 7573 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7574 } 7575 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7576 SuitableAlign = 128; 7577 } 7578 7579 void setN64ABITypes() { 7580 setN32N64ABITypes(); 7581 Int64Type = SignedLong; 7582 IntMaxType = Int64Type; 7583 LongWidth = LongAlign = 64; 7584 PointerWidth = PointerAlign = 64; 7585 PtrDiffType = SignedLong; 7586 SizeType = UnsignedLong; 7587 } 7588 7589 void setN32ABITypes() { 7590 setN32N64ABITypes(); 7591 Int64Type = SignedLongLong; 7592 IntMaxType = Int64Type; 7593 LongWidth = LongAlign = 32; 7594 PointerWidth = PointerAlign = 32; 7595 PtrDiffType = SignedInt; 7596 SizeType = UnsignedInt; 7597 } 7598 7599 bool setCPU(const std::string &Name) override { 7600 CPU = Name; 7601 return llvm::StringSwitch<bool>(Name) 7602 .Case("mips1", true) 7603 .Case("mips2", true) 7604 .Case("mips3", true) 7605 .Case("mips4", true) 7606 .Case("mips5", true) 7607 .Case("mips32", true) 7608 .Case("mips32r2", true) 7609 .Case("mips32r3", true) 7610 .Case("mips32r5", true) 7611 .Case("mips32r6", true) 7612 .Case("mips64", true) 7613 .Case("mips64r2", true) 7614 .Case("mips64r3", true) 7615 .Case("mips64r5", true) 7616 .Case("mips64r6", true) 7617 .Case("octeon", true) 7618 .Case("p5600", true) 7619 .Default(false); 7620 } 7621 const std::string& getCPU() const { return CPU; } 7622 bool 7623 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7624 StringRef CPU, 7625 const std::vector<std::string> &FeaturesVec) const override { 7626 if (CPU.empty()) 7627 CPU = getCPU(); 7628 if (CPU == "octeon") 7629 Features["mips64r2"] = Features["cnmips"] = true; 7630 else 7631 Features[CPU] = true; 7632 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7633 } 7634 7635 void getTargetDefines(const LangOptions &Opts, 7636 MacroBuilder &Builder) const override { 7637 if (BigEndian) { 7638 DefineStd(Builder, "MIPSEB", Opts); 7639 Builder.defineMacro("_MIPSEB"); 7640 } else { 7641 DefineStd(Builder, "MIPSEL", Opts); 7642 Builder.defineMacro("_MIPSEL"); 7643 } 7644 7645 Builder.defineMacro("__mips__"); 7646 Builder.defineMacro("_mips"); 7647 if (Opts.GNUMode) 7648 Builder.defineMacro("mips"); 7649 7650 if (ABI == "o32") { 7651 Builder.defineMacro("__mips", "32"); 7652 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7653 } else { 7654 Builder.defineMacro("__mips", "64"); 7655 Builder.defineMacro("__mips64"); 7656 Builder.defineMacro("__mips64__"); 7657 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7658 } 7659 7660 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7661 .Cases("mips32", "mips64", "1") 7662 .Cases("mips32r2", "mips64r2", "2") 7663 .Cases("mips32r3", "mips64r3", "3") 7664 .Cases("mips32r5", "mips64r5", "5") 7665 .Cases("mips32r6", "mips64r6", "6") 7666 .Default(""); 7667 if (!ISARev.empty()) 7668 Builder.defineMacro("__mips_isa_rev", ISARev); 7669 7670 if (ABI == "o32") { 7671 Builder.defineMacro("__mips_o32"); 7672 Builder.defineMacro("_ABIO32", "1"); 7673 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7674 } else if (ABI == "n32") { 7675 Builder.defineMacro("__mips_n32"); 7676 Builder.defineMacro("_ABIN32", "2"); 7677 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7678 } else if (ABI == "n64") { 7679 Builder.defineMacro("__mips_n64"); 7680 Builder.defineMacro("_ABI64", "3"); 7681 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7682 } else 7683 llvm_unreachable("Invalid ABI."); 7684 7685 if (!IsNoABICalls) { 7686 Builder.defineMacro("__mips_abicalls"); 7687 if (CanUseBSDABICalls) 7688 Builder.defineMacro("__ABICALLS__"); 7689 } 7690 7691 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7692 7693 switch (FloatABI) { 7694 case HardFloat: 7695 Builder.defineMacro("__mips_hard_float", Twine(1)); 7696 break; 7697 case SoftFloat: 7698 Builder.defineMacro("__mips_soft_float", Twine(1)); 7699 break; 7700 } 7701 7702 if (IsSingleFloat) 7703 Builder.defineMacro("__mips_single_float", Twine(1)); 7704 7705 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7706 Builder.defineMacro("_MIPS_FPSET", 7707 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7708 7709 if (IsMips16) 7710 Builder.defineMacro("__mips16", Twine(1)); 7711 7712 if (IsMicromips) 7713 Builder.defineMacro("__mips_micromips", Twine(1)); 7714 7715 if (IsNan2008) 7716 Builder.defineMacro("__mips_nan2008", Twine(1)); 7717 7718 switch (DspRev) { 7719 default: 7720 break; 7721 case DSP1: 7722 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7723 Builder.defineMacro("__mips_dsp", Twine(1)); 7724 break; 7725 case DSP2: 7726 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7727 Builder.defineMacro("__mips_dspr2", Twine(1)); 7728 Builder.defineMacro("__mips_dsp", Twine(1)); 7729 break; 7730 } 7731 7732 if (HasMSA) 7733 Builder.defineMacro("__mips_msa", Twine(1)); 7734 7735 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7736 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7737 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7738 7739 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7740 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7741 7742 // These shouldn't be defined for MIPS-I but there's no need to check 7743 // for that since MIPS-I isn't supported. 7744 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7745 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7746 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7747 7748 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7749 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7750 // the instructions exist but using them violates the ABI since they 7751 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7752 if (ABI == "n32" || ABI == "n64") 7753 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7754 } 7755 7756 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7757 return llvm::makeArrayRef(BuiltinInfo, 7758 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7759 } 7760 bool hasFeature(StringRef Feature) const override { 7761 return llvm::StringSwitch<bool>(Feature) 7762 .Case("mips", true) 7763 .Case("fp64", HasFP64) 7764 .Default(false); 7765 } 7766 BuiltinVaListKind getBuiltinVaListKind() const override { 7767 return TargetInfo::VoidPtrBuiltinVaList; 7768 } 7769 ArrayRef<const char *> getGCCRegNames() const override { 7770 static const char *const GCCRegNames[] = { 7771 // CPU register names 7772 // Must match second column of GCCRegAliases 7773 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7774 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7775 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7776 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7777 // Floating point register names 7778 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7779 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7780 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7781 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7782 // Hi/lo and condition register names 7783 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7784 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7785 "$ac3hi","$ac3lo", 7786 // MSA register names 7787 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7788 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7789 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7790 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7791 // MSA control register names 7792 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7793 "$msarequest", "$msamap", "$msaunmap" 7794 }; 7795 return llvm::makeArrayRef(GCCRegNames); 7796 } 7797 bool validateAsmConstraint(const char *&Name, 7798 TargetInfo::ConstraintInfo &Info) const override { 7799 switch (*Name) { 7800 default: 7801 return false; 7802 case 'r': // CPU registers. 7803 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7804 case 'y': // Equivalent to "r", backward compatibility only. 7805 case 'f': // floating-point registers. 7806 case 'c': // $25 for indirect jumps 7807 case 'l': // lo register 7808 case 'x': // hilo register pair 7809 Info.setAllowsRegister(); 7810 return true; 7811 case 'I': // Signed 16-bit constant 7812 case 'J': // Integer 0 7813 case 'K': // Unsigned 16-bit constant 7814 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7815 case 'M': // Constants not loadable via lui, addiu, or ori 7816 case 'N': // Constant -1 to -65535 7817 case 'O': // A signed 15-bit constant 7818 case 'P': // A constant between 1 go 65535 7819 return true; 7820 case 'R': // An address that can be used in a non-macro load or store 7821 Info.setAllowsMemory(); 7822 return true; 7823 case 'Z': 7824 if (Name[1] == 'C') { // An address usable by ll, and sc. 7825 Info.setAllowsMemory(); 7826 Name++; // Skip over 'Z'. 7827 return true; 7828 } 7829 return false; 7830 } 7831 } 7832 7833 std::string convertConstraint(const char *&Constraint) const override { 7834 std::string R; 7835 switch (*Constraint) { 7836 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7837 if (Constraint[1] == 'C') { 7838 R = std::string("^") + std::string(Constraint, 2); 7839 Constraint++; 7840 return R; 7841 } 7842 break; 7843 } 7844 return TargetInfo::convertConstraint(Constraint); 7845 } 7846 7847 const char *getClobbers() const override { 7848 // In GCC, $1 is not widely used in generated code (it's used only in a few 7849 // specific situations), so there is no real need for users to add it to 7850 // the clobbers list if they want to use it in their inline assembly code. 7851 // 7852 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7853 // code generation, so using it in inline assembly without adding it to the 7854 // clobbers list can cause conflicts between the inline assembly code and 7855 // the surrounding generated code. 7856 // 7857 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7858 // operands, which will conflict with the ".set at" assembler option (which 7859 // we use only for inline assembly, in order to maintain compatibility with 7860 // GCC) and will also conflict with the user's usage of $1. 7861 // 7862 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7863 // register for generated code is to automatically clobber $1 for all inline 7864 // assembly code. 7865 // 7866 // FIXME: We should automatically clobber $1 only for inline assembly code 7867 // which actually uses it. This would allow LLVM to use $1 for inline 7868 // assembly operands if the user's assembly code doesn't use it. 7869 return "~{$1}"; 7870 } 7871 7872 bool handleTargetFeatures(std::vector<std::string> &Features, 7873 DiagnosticsEngine &Diags) override { 7874 IsMips16 = false; 7875 IsMicromips = false; 7876 IsNan2008 = isNaN2008Default(); 7877 IsSingleFloat = false; 7878 FloatABI = HardFloat; 7879 DspRev = NoDSP; 7880 HasFP64 = isFP64Default(); 7881 7882 for (const auto &Feature : Features) { 7883 if (Feature == "+single-float") 7884 IsSingleFloat = true; 7885 else if (Feature == "+soft-float") 7886 FloatABI = SoftFloat; 7887 else if (Feature == "+mips16") 7888 IsMips16 = true; 7889 else if (Feature == "+micromips") 7890 IsMicromips = true; 7891 else if (Feature == "+dsp") 7892 DspRev = std::max(DspRev, DSP1); 7893 else if (Feature == "+dspr2") 7894 DspRev = std::max(DspRev, DSP2); 7895 else if (Feature == "+msa") 7896 HasMSA = true; 7897 else if (Feature == "+fp64") 7898 HasFP64 = true; 7899 else if (Feature == "-fp64") 7900 HasFP64 = false; 7901 else if (Feature == "+nan2008") 7902 IsNan2008 = true; 7903 else if (Feature == "-nan2008") 7904 IsNan2008 = false; 7905 else if (Feature == "+noabicalls") 7906 IsNoABICalls = true; 7907 } 7908 7909 setDataLayout(); 7910 7911 return true; 7912 } 7913 7914 int getEHDataRegisterNumber(unsigned RegNo) const override { 7915 if (RegNo == 0) return 4; 7916 if (RegNo == 1) return 5; 7917 return -1; 7918 } 7919 7920 bool isCLZForZeroUndef() const override { return false; } 7921 7922 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7923 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7924 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7925 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7926 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7927 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7928 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7929 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7930 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7931 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7932 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7933 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7934 {{"ra"}, "$31"}}; 7935 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7936 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7937 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7938 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7939 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7940 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7941 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7942 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7943 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7944 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7945 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7946 {{"ra"}, "$31"}}; 7947 if (ABI == "o32") 7948 return llvm::makeArrayRef(O32RegAliases); 7949 return llvm::makeArrayRef(NewABIRegAliases); 7950 } 7951 7952 bool hasInt128Type() const override { 7953 return ABI == "n32" || ABI == "n64"; 7954 } 7955 7956 bool validateTarget(DiagnosticsEngine &Diags) const override { 7957 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7958 // this yet. It's better to fail here than on the backend assertion. 7959 if (processorSupportsGPR64() && ABI == "o32") { 7960 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7961 return false; 7962 } 7963 7964 // 64-bit ABI's require 64-bit CPU's. 7965 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 7966 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7967 return false; 7968 } 7969 7970 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 7971 // can't handle this yet. It's better to fail here than on the 7972 // backend assertion. 7973 if ((getTriple().getArch() == llvm::Triple::mips64 || 7974 getTriple().getArch() == llvm::Triple::mips64el) && 7975 ABI == "o32") { 7976 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7977 << ABI << getTriple().str(); 7978 return false; 7979 } 7980 7981 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 7982 // can't handle this yet. It's better to fail here than on the 7983 // backend assertion. 7984 if ((getTriple().getArch() == llvm::Triple::mips || 7985 getTriple().getArch() == llvm::Triple::mipsel) && 7986 (ABI == "n32" || ABI == "n64")) { 7987 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7988 << ABI << getTriple().str(); 7989 return false; 7990 } 7991 7992 return true; 7993 } 7994 }; 7995 7996 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7997 #define BUILTIN(ID, TYPE, ATTRS) \ 7998 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7999 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8000 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8001 #include "clang/Basic/BuiltinsMips.def" 8002 }; 8003 8004 class PNaClTargetInfo : public TargetInfo { 8005 public: 8006 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8007 : TargetInfo(Triple) { 8008 this->LongAlign = 32; 8009 this->LongWidth = 32; 8010 this->PointerAlign = 32; 8011 this->PointerWidth = 32; 8012 this->IntMaxType = TargetInfo::SignedLongLong; 8013 this->Int64Type = TargetInfo::SignedLongLong; 8014 this->DoubleAlign = 64; 8015 this->LongDoubleWidth = 64; 8016 this->LongDoubleAlign = 64; 8017 this->SizeType = TargetInfo::UnsignedInt; 8018 this->PtrDiffType = TargetInfo::SignedInt; 8019 this->IntPtrType = TargetInfo::SignedInt; 8020 this->RegParmMax = 0; // Disallow regparm 8021 } 8022 8023 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8024 Builder.defineMacro("__le32__"); 8025 Builder.defineMacro("__pnacl__"); 8026 } 8027 void getTargetDefines(const LangOptions &Opts, 8028 MacroBuilder &Builder) const override { 8029 getArchDefines(Opts, Builder); 8030 } 8031 bool hasFeature(StringRef Feature) const override { 8032 return Feature == "pnacl"; 8033 } 8034 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8035 BuiltinVaListKind getBuiltinVaListKind() const override { 8036 return TargetInfo::PNaClABIBuiltinVaList; 8037 } 8038 ArrayRef<const char *> getGCCRegNames() const override; 8039 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8040 bool validateAsmConstraint(const char *&Name, 8041 TargetInfo::ConstraintInfo &Info) const override { 8042 return false; 8043 } 8044 8045 const char *getClobbers() const override { 8046 return ""; 8047 } 8048 }; 8049 8050 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8051 return None; 8052 } 8053 8054 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8055 return None; 8056 } 8057 8058 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8059 class NaClMips32TargetInfo : public MipsTargetInfo { 8060 public: 8061 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8062 : MipsTargetInfo(Triple, Opts) {} 8063 8064 BuiltinVaListKind getBuiltinVaListKind() const override { 8065 return TargetInfo::PNaClABIBuiltinVaList; 8066 } 8067 }; 8068 8069 class Le64TargetInfo : public TargetInfo { 8070 static const Builtin::Info BuiltinInfo[]; 8071 8072 public: 8073 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8074 : TargetInfo(Triple) { 8075 NoAsmVariants = true; 8076 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8077 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8078 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8079 } 8080 8081 void getTargetDefines(const LangOptions &Opts, 8082 MacroBuilder &Builder) const override { 8083 DefineStd(Builder, "unix", Opts); 8084 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8085 Builder.defineMacro("__ELF__"); 8086 } 8087 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8088 return llvm::makeArrayRef(BuiltinInfo, 8089 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8090 } 8091 BuiltinVaListKind getBuiltinVaListKind() const override { 8092 return TargetInfo::PNaClABIBuiltinVaList; 8093 } 8094 const char *getClobbers() const override { return ""; } 8095 ArrayRef<const char *> getGCCRegNames() const override { 8096 return None; 8097 } 8098 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8099 return None; 8100 } 8101 bool validateAsmConstraint(const char *&Name, 8102 TargetInfo::ConstraintInfo &Info) const override { 8103 return false; 8104 } 8105 8106 bool hasProtectedVisibility() const override { return false; } 8107 }; 8108 8109 class WebAssemblyTargetInfo : public TargetInfo { 8110 static const Builtin::Info BuiltinInfo[]; 8111 8112 enum SIMDEnum { 8113 NoSIMD, 8114 SIMD128, 8115 } SIMDLevel; 8116 8117 public: 8118 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8119 : TargetInfo(T), SIMDLevel(NoSIMD) { 8120 NoAsmVariants = true; 8121 SuitableAlign = 128; 8122 LargeArrayMinWidth = 128; 8123 LargeArrayAlign = 128; 8124 SimdDefaultAlign = 128; 8125 SigAtomicType = SignedLong; 8126 LongDoubleWidth = LongDoubleAlign = 128; 8127 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8128 SizeType = UnsignedInt; 8129 PtrDiffType = SignedInt; 8130 IntPtrType = SignedInt; 8131 } 8132 8133 protected: 8134 void getTargetDefines(const LangOptions &Opts, 8135 MacroBuilder &Builder) const override { 8136 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8137 if (SIMDLevel >= SIMD128) 8138 Builder.defineMacro("__wasm_simd128__"); 8139 } 8140 8141 private: 8142 bool 8143 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8144 StringRef CPU, 8145 const std::vector<std::string> &FeaturesVec) const override { 8146 if (CPU == "bleeding-edge") 8147 Features["simd128"] = true; 8148 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8149 } 8150 bool hasFeature(StringRef Feature) const final { 8151 return llvm::StringSwitch<bool>(Feature) 8152 .Case("simd128", SIMDLevel >= SIMD128) 8153 .Default(false); 8154 } 8155 bool handleTargetFeatures(std::vector<std::string> &Features, 8156 DiagnosticsEngine &Diags) final { 8157 for (const auto &Feature : Features) { 8158 if (Feature == "+simd128") { 8159 SIMDLevel = std::max(SIMDLevel, SIMD128); 8160 continue; 8161 } 8162 if (Feature == "-simd128") { 8163 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8164 continue; 8165 } 8166 8167 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8168 << "-target-feature"; 8169 return false; 8170 } 8171 return true; 8172 } 8173 bool setCPU(const std::string &Name) final { 8174 return llvm::StringSwitch<bool>(Name) 8175 .Case("mvp", true) 8176 .Case("bleeding-edge", true) 8177 .Case("generic", true) 8178 .Default(false); 8179 } 8180 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8181 return llvm::makeArrayRef(BuiltinInfo, 8182 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8183 } 8184 BuiltinVaListKind getBuiltinVaListKind() const final { 8185 return VoidPtrBuiltinVaList; 8186 } 8187 ArrayRef<const char *> getGCCRegNames() const final { 8188 return None; 8189 } 8190 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8191 return None; 8192 } 8193 bool 8194 validateAsmConstraint(const char *&Name, 8195 TargetInfo::ConstraintInfo &Info) const final { 8196 return false; 8197 } 8198 const char *getClobbers() const final { return ""; } 8199 bool isCLZForZeroUndef() const final { return false; } 8200 bool hasInt128Type() const final { return true; } 8201 IntType getIntTypeByWidth(unsigned BitWidth, 8202 bool IsSigned) const final { 8203 // WebAssembly prefers long long for explicitly 64-bit integers. 8204 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8205 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8206 } 8207 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8208 bool IsSigned) const final { 8209 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8210 return BitWidth == 64 8211 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8212 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8213 } 8214 }; 8215 8216 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8217 #define BUILTIN(ID, TYPE, ATTRS) \ 8218 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8219 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8220 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8221 #include "clang/Basic/BuiltinsWebAssembly.def" 8222 }; 8223 8224 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8225 public: 8226 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8227 const TargetOptions &Opts) 8228 : WebAssemblyTargetInfo(T, Opts) { 8229 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8230 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8231 } 8232 8233 protected: 8234 void getTargetDefines(const LangOptions &Opts, 8235 MacroBuilder &Builder) const override { 8236 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8237 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8238 } 8239 }; 8240 8241 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8242 public: 8243 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8244 const TargetOptions &Opts) 8245 : WebAssemblyTargetInfo(T, Opts) { 8246 LongAlign = LongWidth = 64; 8247 PointerAlign = PointerWidth = 64; 8248 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8249 SizeType = UnsignedLong; 8250 PtrDiffType = SignedLong; 8251 IntPtrType = SignedLong; 8252 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8253 } 8254 8255 protected: 8256 void getTargetDefines(const LangOptions &Opts, 8257 MacroBuilder &Builder) const override { 8258 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8259 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8260 } 8261 }; 8262 8263 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8264 #define BUILTIN(ID, TYPE, ATTRS) \ 8265 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8266 #include "clang/Basic/BuiltinsLe64.def" 8267 }; 8268 8269 static const unsigned SPIRAddrSpaceMap[] = { 8270 1, // opencl_global 8271 3, // opencl_local 8272 2, // opencl_constant 8273 4, // opencl_generic 8274 0, // cuda_device 8275 0, // cuda_constant 8276 0 // cuda_shared 8277 }; 8278 class SPIRTargetInfo : public TargetInfo { 8279 public: 8280 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8281 : TargetInfo(Triple) { 8282 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8283 "SPIR target must use unknown OS"); 8284 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8285 "SPIR target must use unknown environment type"); 8286 TLSSupported = false; 8287 LongWidth = LongAlign = 64; 8288 AddrSpaceMap = &SPIRAddrSpaceMap; 8289 UseAddrSpaceMapMangling = true; 8290 // Define available target features 8291 // These must be defined in sorted order! 8292 NoAsmVariants = true; 8293 } 8294 void getTargetDefines(const LangOptions &Opts, 8295 MacroBuilder &Builder) const override { 8296 DefineStd(Builder, "SPIR", Opts); 8297 } 8298 bool hasFeature(StringRef Feature) const override { 8299 return Feature == "spir"; 8300 } 8301 8302 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8303 const char *getClobbers() const override { return ""; } 8304 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8305 bool validateAsmConstraint(const char *&Name, 8306 TargetInfo::ConstraintInfo &info) const override { 8307 return true; 8308 } 8309 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8310 return None; 8311 } 8312 BuiltinVaListKind getBuiltinVaListKind() const override { 8313 return TargetInfo::VoidPtrBuiltinVaList; 8314 } 8315 8316 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8317 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8318 : CCCR_Warning; 8319 } 8320 8321 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8322 return CC_SpirFunction; 8323 } 8324 8325 void setSupportedOpenCLOpts() override { 8326 // Assume all OpenCL extensions and optional core features are supported 8327 // for SPIR since it is a generic target. 8328 getSupportedOpenCLOpts().supportAll(); 8329 } 8330 }; 8331 8332 class SPIR32TargetInfo : public SPIRTargetInfo { 8333 public: 8334 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8335 : SPIRTargetInfo(Triple, Opts) { 8336 PointerWidth = PointerAlign = 32; 8337 SizeType = TargetInfo::UnsignedInt; 8338 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8339 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8340 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8341 } 8342 void getTargetDefines(const LangOptions &Opts, 8343 MacroBuilder &Builder) const override { 8344 DefineStd(Builder, "SPIR32", Opts); 8345 } 8346 }; 8347 8348 class SPIR64TargetInfo : public SPIRTargetInfo { 8349 public: 8350 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8351 : SPIRTargetInfo(Triple, Opts) { 8352 PointerWidth = PointerAlign = 64; 8353 SizeType = TargetInfo::UnsignedLong; 8354 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8355 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8356 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8357 } 8358 void getTargetDefines(const LangOptions &Opts, 8359 MacroBuilder &Builder) const override { 8360 DefineStd(Builder, "SPIR64", Opts); 8361 } 8362 }; 8363 8364 class XCoreTargetInfo : public TargetInfo { 8365 static const Builtin::Info BuiltinInfo[]; 8366 public: 8367 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8368 : TargetInfo(Triple) { 8369 NoAsmVariants = true; 8370 LongLongAlign = 32; 8371 SuitableAlign = 32; 8372 DoubleAlign = LongDoubleAlign = 32; 8373 SizeType = UnsignedInt; 8374 PtrDiffType = SignedInt; 8375 IntPtrType = SignedInt; 8376 WCharType = UnsignedChar; 8377 WIntType = UnsignedInt; 8378 UseZeroLengthBitfieldAlignment = true; 8379 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8380 "-f64:32-a:0:32-n32"); 8381 } 8382 void getTargetDefines(const LangOptions &Opts, 8383 MacroBuilder &Builder) const override { 8384 Builder.defineMacro("__XS1B__"); 8385 } 8386 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8387 return llvm::makeArrayRef(BuiltinInfo, 8388 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8389 } 8390 BuiltinVaListKind getBuiltinVaListKind() const override { 8391 return TargetInfo::VoidPtrBuiltinVaList; 8392 } 8393 const char *getClobbers() const override { 8394 return ""; 8395 } 8396 ArrayRef<const char *> getGCCRegNames() const override { 8397 static const char * const GCCRegNames[] = { 8398 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8399 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8400 }; 8401 return llvm::makeArrayRef(GCCRegNames); 8402 } 8403 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8404 return None; 8405 } 8406 bool validateAsmConstraint(const char *&Name, 8407 TargetInfo::ConstraintInfo &Info) const override { 8408 return false; 8409 } 8410 int getEHDataRegisterNumber(unsigned RegNo) const override { 8411 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8412 return (RegNo < 2)? RegNo : -1; 8413 } 8414 bool allowsLargerPreferedTypeAlignment() const override { 8415 return false; 8416 } 8417 }; 8418 8419 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8420 #define BUILTIN(ID, TYPE, ATTRS) \ 8421 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8422 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8423 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8424 #include "clang/Basic/BuiltinsXCore.def" 8425 }; 8426 8427 // x86_32 Android target 8428 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8429 public: 8430 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8431 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8432 SuitableAlign = 32; 8433 LongDoubleWidth = 64; 8434 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8435 } 8436 }; 8437 8438 // x86_64 Android target 8439 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8440 public: 8441 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8442 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8443 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8444 } 8445 8446 bool useFloat128ManglingForLongDouble() const override { 8447 return true; 8448 } 8449 }; 8450 8451 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8452 class RenderScript32TargetInfo : public ARMleTargetInfo { 8453 public: 8454 RenderScript32TargetInfo(const llvm::Triple &Triple, 8455 const TargetOptions &Opts) 8456 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8457 Triple.getOSName(), 8458 Triple.getEnvironmentName()), 8459 Opts) { 8460 IsRenderScriptTarget = true; 8461 LongWidth = LongAlign = 64; 8462 } 8463 void getTargetDefines(const LangOptions &Opts, 8464 MacroBuilder &Builder) const override { 8465 Builder.defineMacro("__RENDERSCRIPT__"); 8466 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8467 } 8468 }; 8469 8470 // 64-bit RenderScript is aarch64 8471 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8472 public: 8473 RenderScript64TargetInfo(const llvm::Triple &Triple, 8474 const TargetOptions &Opts) 8475 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8476 Triple.getOSName(), 8477 Triple.getEnvironmentName()), 8478 Opts) { 8479 IsRenderScriptTarget = true; 8480 } 8481 8482 void getTargetDefines(const LangOptions &Opts, 8483 MacroBuilder &Builder) const override { 8484 Builder.defineMacro("__RENDERSCRIPT__"); 8485 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8486 } 8487 }; 8488 8489 /// Information about a specific microcontroller. 8490 struct MCUInfo { 8491 const char *Name; 8492 const char *DefineName; 8493 }; 8494 8495 // This list should be kept up-to-date with AVRDevices.td in LLVM. 8496 static ArrayRef<MCUInfo> AVRMcus = { 8497 { "at90s1200", "__AVR_AT90S1200__" }, 8498 { "attiny11", "__AVR_ATtiny11__" }, 8499 { "attiny12", "__AVR_ATtiny12__" }, 8500 { "attiny15", "__AVR_ATtiny15__" }, 8501 { "attiny28", "__AVR_ATtiny28__" }, 8502 { "at90s2313", "__AVR_AT90S2313__" }, 8503 { "at90s2323", "__AVR_AT90S2323__" }, 8504 { "at90s2333", "__AVR_AT90S2333__" }, 8505 { "at90s2343", "__AVR_AT90S2343__" }, 8506 { "attiny22", "__AVR_ATtiny22__" }, 8507 { "attiny26", "__AVR_ATtiny26__" }, 8508 { "at86rf401", "__AVR_AT86RF401__" }, 8509 { "at90s4414", "__AVR_AT90S4414__" }, 8510 { "at90s4433", "__AVR_AT90S4433__" }, 8511 { "at90s4434", "__AVR_AT90S4434__" }, 8512 { "at90s8515", "__AVR_AT90S8515__" }, 8513 { "at90c8534", "__AVR_AT90c8534__" }, 8514 { "at90s8535", "__AVR_AT90S8535__" }, 8515 { "ata5272", "__AVR_ATA5272__" }, 8516 { "attiny13", "__AVR_ATtiny13__" }, 8517 { "attiny13a", "__AVR_ATtiny13A__" }, 8518 { "attiny2313", "__AVR_ATtiny2313__" }, 8519 { "attiny2313a", "__AVR_ATtiny2313A__" }, 8520 { "attiny24", "__AVR_ATtiny24__" }, 8521 { "attiny24a", "__AVR_ATtiny24A__" }, 8522 { "attiny4313", "__AVR_ATtiny4313__" }, 8523 { "attiny44", "__AVR_ATtiny44__" }, 8524 { "attiny44a", "__AVR_ATtiny44A__" }, 8525 { "attiny84", "__AVR_ATtiny84__" }, 8526 { "attiny84a", "__AVR_ATtiny84A__" }, 8527 { "attiny25", "__AVR_ATtiny25__" }, 8528 { "attiny45", "__AVR_ATtiny45__" }, 8529 { "attiny85", "__AVR_ATtiny85__" }, 8530 { "attiny261", "__AVR_ATtiny261__" }, 8531 { "attiny261a", "__AVR_ATtiny261A__" }, 8532 { "attiny461", "__AVR_ATtiny461__" }, 8533 { "attiny461a", "__AVR_ATtiny461A__" }, 8534 { "attiny861", "__AVR_ATtiny861__" }, 8535 { "attiny861a", "__AVR_ATtiny861A__" }, 8536 { "attiny87", "__AVR_ATtiny87__" }, 8537 { "attiny43u", "__AVR_ATtiny43U__" }, 8538 { "attiny48", "__AVR_ATtiny48__" }, 8539 { "attiny88", "__AVR_ATtiny88__" }, 8540 { "attiny828", "__AVR_ATtiny828__" }, 8541 { "at43usb355", "__AVR_AT43USB355__" }, 8542 { "at76c711", "__AVR_AT76C711__" }, 8543 { "atmega103", "__AVR_ATmega103__" }, 8544 { "at43usb320", "__AVR_AT43USB320__" }, 8545 { "attiny167", "__AVR_ATtiny167__" }, 8546 { "at90usb82", "__AVR_AT90USB82__" }, 8547 { "at90usb162", "__AVR_AT90USB162__" }, 8548 { "ata5505", "__AVR_ATA5505__" }, 8549 { "atmega8u2", "__AVR_ATmega8U2__" }, 8550 { "atmega16u2", "__AVR_ATmega16U2__" }, 8551 { "atmega32u2", "__AVR_ATmega32U2__" }, 8552 { "attiny1634", "__AVR_ATtiny1634__" }, 8553 { "atmega8", "__AVR_ATmega8__" }, 8554 { "ata6289", "__AVR_ATA6289__" }, 8555 { "atmega8a", "__AVR_ATmega8A__" }, 8556 { "ata6285", "__AVR_ATA6285__" }, 8557 { "ata6286", "__AVR_ATA6286__" }, 8558 { "atmega48", "__AVR_ATmega48__" }, 8559 { "atmega48a", "__AVR_ATmega48A__" }, 8560 { "atmega48pa", "__AVR_ATmega48PA__" }, 8561 { "atmega48p", "__AVR_ATmega48P__" }, 8562 { "atmega88", "__AVR_ATmega88__" }, 8563 { "atmega88a", "__AVR_ATmega88A__" }, 8564 { "atmega88p", "__AVR_ATmega88P__" }, 8565 { "atmega88pa", "__AVR_ATmega88PA__" }, 8566 { "atmega8515", "__AVR_ATmega8515__" }, 8567 { "atmega8535", "__AVR_ATmega8535__" }, 8568 { "atmega8hva", "__AVR_ATmega8HVA__" }, 8569 { "at90pwm1", "__AVR_AT90PWM1__" }, 8570 { "at90pwm2", "__AVR_AT90PWM2__" }, 8571 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 8572 { "at90pwm3", "__AVR_AT90PWM3__" }, 8573 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 8574 { "at90pwm81", "__AVR_AT90PWM81__" }, 8575 { "ata5790", "__AVR_ATA5790__" }, 8576 { "ata5795", "__AVR_ATA5795__" }, 8577 { "atmega16", "__AVR_ATmega16__" }, 8578 { "atmega16a", "__AVR_ATmega16A__" }, 8579 { "atmega161", "__AVR_ATmega161__" }, 8580 { "atmega162", "__AVR_ATmega162__" }, 8581 { "atmega163", "__AVR_ATmega163__" }, 8582 { "atmega164a", "__AVR_ATmega164A__" }, 8583 { "atmega164p", "__AVR_ATmega164P__" }, 8584 { "atmega164pa", "__AVR_ATmega164PA__" }, 8585 { "atmega165", "__AVR_ATmega165__" }, 8586 { "atmega165a", "__AVR_ATmega165A__" }, 8587 { "atmega165p", "__AVR_ATmega165P__" }, 8588 { "atmega165pa", "__AVR_ATmega165PA__" }, 8589 { "atmega168", "__AVR_ATmega168__" }, 8590 { "atmega168a", "__AVR_ATmega168A__" }, 8591 { "atmega168p", "__AVR_ATmega168P__" }, 8592 { "atmega168pa", "__AVR_ATmega168PA__" }, 8593 { "atmega169", "__AVR_ATmega169__" }, 8594 { "atmega169a", "__AVR_ATmega169A__" }, 8595 { "atmega169p", "__AVR_ATmega169P__" }, 8596 { "atmega169pa", "__AVR_ATmega169PA__" }, 8597 { "atmega32", "__AVR_ATmega32__" }, 8598 { "atmega32a", "__AVR_ATmega32A__" }, 8599 { "atmega323", "__AVR_ATmega323__" }, 8600 { "atmega324a", "__AVR_ATmega324A__" }, 8601 { "atmega324p", "__AVR_ATmega324P__" }, 8602 { "atmega324pa", "__AVR_ATmega324PA__" }, 8603 { "atmega325", "__AVR_ATmega325__" }, 8604 { "atmega325a", "__AVR_ATmega325A__" }, 8605 { "atmega325p", "__AVR_ATmega325P__" }, 8606 { "atmega325pa", "__AVR_ATmega325PA__" }, 8607 { "atmega3250", "__AVR_ATmega3250__" }, 8608 { "atmega3250a", "__AVR_ATmega3250A__" }, 8609 { "atmega3250p", "__AVR_ATmega3250P__" }, 8610 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 8611 { "atmega328", "__AVR_ATmega328__" }, 8612 { "atmega328p", "__AVR_ATmega328P__" }, 8613 { "atmega329", "__AVR_ATmega329__" }, 8614 { "atmega329a", "__AVR_ATmega329A__" }, 8615 { "atmega329p", "__AVR_ATmega329P__" }, 8616 { "atmega329pa", "__AVR_ATmega329PA__" }, 8617 { "atmega3290", "__AVR_ATmega3290__" }, 8618 { "atmega3290a", "__AVR_ATmega3290A__" }, 8619 { "atmega3290p", "__AVR_ATmega3290P__" }, 8620 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 8621 { "atmega406", "__AVR_ATmega406__" }, 8622 { "atmega64", "__AVR_ATmega64__" }, 8623 { "atmega64a", "__AVR_ATmega64A__" }, 8624 { "atmega640", "__AVR_ATmega640__" }, 8625 { "atmega644", "__AVR_ATmega644__" }, 8626 { "atmega644a", "__AVR_ATmega644A__" }, 8627 { "atmega644p", "__AVR_ATmega644P__" }, 8628 { "atmega644pa", "__AVR_ATmega644PA__" }, 8629 { "atmega645", "__AVR_ATmega645__" }, 8630 { "atmega645a", "__AVR_ATmega645A__" }, 8631 { "atmega645p", "__AVR_ATmega645P__" }, 8632 { "atmega649", "__AVR_ATmega649__" }, 8633 { "atmega649a", "__AVR_ATmega649A__" }, 8634 { "atmega649p", "__AVR_ATmega649P__" }, 8635 { "atmega6450", "__AVR_ATmega6450__" }, 8636 { "atmega6450a", "__AVR_ATmega6450A__" }, 8637 { "atmega6450p", "__AVR_ATmega6450P__" }, 8638 { "atmega6490", "__AVR_ATmega6490__" }, 8639 { "atmega6490a", "__AVR_ATmega6490A__" }, 8640 { "atmega6490p", "__AVR_ATmega6490P__" }, 8641 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 8642 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 8643 { "atmega16hva", "__AVR_ATmega16HVA__" }, 8644 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 8645 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 8646 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 8647 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 8648 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 8649 { "atmega64hve", "__AVR_ATmega64HVE__" }, 8650 { "at90can32", "__AVR_AT90CAN32__" }, 8651 { "at90can64", "__AVR_AT90CAN64__" }, 8652 { "at90pwm161", "__AVR_AT90PWM161__" }, 8653 { "at90pwm216", "__AVR_AT90PWM216__" }, 8654 { "at90pwm316", "__AVR_AT90PWM316__" }, 8655 { "atmega32c1", "__AVR_ATmega32C1__" }, 8656 { "atmega64c1", "__AVR_ATmega64C1__" }, 8657 { "atmega16m1", "__AVR_ATmega16M1__" }, 8658 { "atmega32m1", "__AVR_ATmega32M1__" }, 8659 { "atmega64m1", "__AVR_ATmega64M1__" }, 8660 { "atmega16u4", "__AVR_ATmega16U4__" }, 8661 { "atmega32u4", "__AVR_ATmega32U4__" }, 8662 { "atmega32u6", "__AVR_ATmega32U6__" }, 8663 { "at90usb646", "__AVR_AT90USB646__" }, 8664 { "at90usb647", "__AVR_AT90USB647__" }, 8665 { "at90scr100", "__AVR_AT90SCR100__" }, 8666 { "at94k", "__AVR_AT94K__" }, 8667 { "m3000", "__AVR_AT000__" }, 8668 { "atmega128", "__AVR_ATmega128__" }, 8669 { "atmega128a", "__AVR_ATmega128A__" }, 8670 { "atmega1280", "__AVR_ATmega1280__" }, 8671 { "atmega1281", "__AVR_ATmega1281__" }, 8672 { "atmega1284", "__AVR_ATmega1284__" }, 8673 { "atmega1284p", "__AVR_ATmega1284P__" }, 8674 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 8675 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 8676 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 8677 { "at90can128", "__AVR_AT90CAN128__" }, 8678 { "at90usb1286", "__AVR_AT90USB1286__" }, 8679 { "at90usb1287", "__AVR_AT90USB1287__" }, 8680 { "atmega2560", "__AVR_ATmega2560__" }, 8681 { "atmega2561", "__AVR_ATmega2561__" }, 8682 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 8683 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 8684 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 8685 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 8686 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 8687 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 8688 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 8689 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 8690 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 8691 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 8692 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 8693 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 8694 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 8695 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 8696 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 8697 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 8698 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 8699 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 8700 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 8701 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 8702 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 8703 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 8704 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 8705 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 8706 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 8707 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 8708 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 8709 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 8710 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 8711 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 8712 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 8713 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 8714 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 8715 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 8716 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 8717 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 8718 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 8719 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 8720 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 8721 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 8722 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 8723 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 8724 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 8725 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 8726 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 8727 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 8728 { "attiny4", "__AVR_ATtiny4__" }, 8729 { "attiny5", "__AVR_ATtiny5__" }, 8730 { "attiny9", "__AVR_ATtiny9__" }, 8731 { "attiny10", "__AVR_ATtiny10__" }, 8732 { "attiny20", "__AVR_ATtiny20__" }, 8733 { "attiny40", "__AVR_ATtiny40__" }, 8734 { "attiny102", "__AVR_ATtiny102__" }, 8735 { "attiny104", "__AVR_ATtiny104__" }, 8736 }; 8737 8738 // AVR Target 8739 class AVRTargetInfo : public TargetInfo { 8740 public: 8741 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8742 : TargetInfo(Triple) { 8743 TLSSupported = false; 8744 PointerWidth = 16; 8745 PointerAlign = 8; 8746 IntWidth = 16; 8747 IntAlign = 8; 8748 LongWidth = 32; 8749 LongAlign = 8; 8750 LongLongWidth = 64; 8751 LongLongAlign = 8; 8752 SuitableAlign = 8; 8753 DefaultAlignForAttributeAligned = 8; 8754 HalfWidth = 16; 8755 HalfAlign = 8; 8756 FloatWidth = 32; 8757 FloatAlign = 8; 8758 DoubleWidth = 32; 8759 DoubleAlign = 8; 8760 DoubleFormat = &llvm::APFloat::IEEEsingle(); 8761 LongDoubleWidth = 32; 8762 LongDoubleAlign = 8; 8763 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 8764 SizeType = UnsignedInt; 8765 PtrDiffType = SignedInt; 8766 IntPtrType = SignedInt; 8767 Char16Type = UnsignedInt; 8768 WCharType = SignedInt; 8769 WIntType = SignedInt; 8770 Char32Type = UnsignedLong; 8771 SigAtomicType = SignedChar; 8772 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 8773 "-f32:32:32-f64:64:64-n8"); 8774 } 8775 8776 void getTargetDefines(const LangOptions &Opts, 8777 MacroBuilder &Builder) const override { 8778 Builder.defineMacro("AVR"); 8779 Builder.defineMacro("__AVR"); 8780 Builder.defineMacro("__AVR__"); 8781 8782 if (!this->CPU.empty()) { 8783 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 8784 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 8785 8786 if (It != AVRMcus.end()) 8787 Builder.defineMacro(It->DefineName); 8788 } 8789 } 8790 8791 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8792 return None; 8793 } 8794 8795 BuiltinVaListKind getBuiltinVaListKind() const override { 8796 return TargetInfo::VoidPtrBuiltinVaList; 8797 } 8798 8799 const char *getClobbers() const override { 8800 return ""; 8801 } 8802 8803 ArrayRef<const char *> getGCCRegNames() const override { 8804 static const char * const GCCRegNames[] = { 8805 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8806 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 8807 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 8808 "r24", "r25", "X", "Y", "Z", "SP" 8809 }; 8810 return llvm::makeArrayRef(GCCRegNames); 8811 } 8812 8813 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8814 return None; 8815 } 8816 8817 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 8818 static const TargetInfo::AddlRegName AddlRegNames[] = { 8819 { { "r26", "r27"}, 26 }, 8820 { { "r28", "r29"}, 27 }, 8821 { { "r30", "r31"}, 28 }, 8822 { { "SPL", "SPH"}, 29 }, 8823 }; 8824 return llvm::makeArrayRef(AddlRegNames); 8825 } 8826 8827 bool validateAsmConstraint(const char *&Name, 8828 TargetInfo::ConstraintInfo &Info) const override { 8829 // There aren't any multi-character AVR specific constraints. 8830 if (StringRef(Name).size() > 1) return false; 8831 8832 switch (*Name) { 8833 default: return false; 8834 case 'a': // Simple upper registers 8835 case 'b': // Base pointer registers pairs 8836 case 'd': // Upper register 8837 case 'l': // Lower registers 8838 case 'e': // Pointer register pairs 8839 case 'q': // Stack pointer register 8840 case 'r': // Any register 8841 case 'w': // Special upper register pairs 8842 case 't': // Temporary register 8843 case 'x': case 'X': // Pointer register pair X 8844 case 'y': case 'Y': // Pointer register pair Y 8845 case 'z': case 'Z': // Pointer register pair Z 8846 Info.setAllowsRegister(); 8847 return true; 8848 case 'I': // 6-bit positive integer constant 8849 Info.setRequiresImmediate(0, 63); 8850 return true; 8851 case 'J': // 6-bit negative integer constant 8852 Info.setRequiresImmediate(-63, 0); 8853 return true; 8854 case 'K': // Integer constant (Range: 2) 8855 Info.setRequiresImmediate(2); 8856 return true; 8857 case 'L': // Integer constant (Range: 0) 8858 Info.setRequiresImmediate(0); 8859 return true; 8860 case 'M': // 8-bit integer constant 8861 Info.setRequiresImmediate(0, 0xff); 8862 return true; 8863 case 'N': // Integer constant (Range: -1) 8864 Info.setRequiresImmediate(-1); 8865 return true; 8866 case 'O': // Integer constant (Range: 8, 16, 24) 8867 Info.setRequiresImmediate({8, 16, 24}); 8868 return true; 8869 case 'P': // Integer constant (Range: 1) 8870 Info.setRequiresImmediate(1); 8871 return true; 8872 case 'R': // Integer constant (Range: -6 to 5) 8873 Info.setRequiresImmediate(-6, 5); 8874 return true; 8875 case 'G': // Floating point constant 8876 case 'Q': // A memory address based on Y or Z pointer with displacement. 8877 return true; 8878 } 8879 8880 return false; 8881 } 8882 8883 IntType getIntTypeByWidth(unsigned BitWidth, 8884 bool IsSigned) const final { 8885 // AVR prefers int for 16-bit integers. 8886 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 8887 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8888 } 8889 8890 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8891 bool IsSigned) const final { 8892 // AVR uses int for int_least16_t and int_fast16_t. 8893 return BitWidth == 16 8894 ? (IsSigned ? SignedInt : UnsignedInt) 8895 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8896 } 8897 8898 bool setCPU(const std::string &Name) override { 8899 bool IsFamily = llvm::StringSwitch<bool>(Name) 8900 .Case("avr1", true) 8901 .Case("avr2", true) 8902 .Case("avr25", true) 8903 .Case("avr3", true) 8904 .Case("avr31", true) 8905 .Case("avr35", true) 8906 .Case("avr4", true) 8907 .Case("avr5", true) 8908 .Case("avr51", true) 8909 .Case("avr6", true) 8910 .Case("avrxmega1", true) 8911 .Case("avrxmega2", true) 8912 .Case("avrxmega3", true) 8913 .Case("avrxmega4", true) 8914 .Case("avrxmega5", true) 8915 .Case("avrxmega6", true) 8916 .Case("avrxmega7", true) 8917 .Case("avrtiny", true) 8918 .Default(false); 8919 8920 if (IsFamily) this->CPU = Name; 8921 8922 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 8923 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 8924 8925 if (IsMCU) this->CPU = Name; 8926 8927 return IsFamily || IsMCU; 8928 } 8929 8930 protected: 8931 std::string CPU; 8932 }; 8933 8934 } // end anonymous namespace 8935 8936 //===----------------------------------------------------------------------===// 8937 // Driver code 8938 //===----------------------------------------------------------------------===// 8939 8940 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8941 const TargetOptions &Opts) { 8942 llvm::Triple::OSType os = Triple.getOS(); 8943 8944 switch (Triple.getArch()) { 8945 default: 8946 return nullptr; 8947 8948 case llvm::Triple::xcore: 8949 return new XCoreTargetInfo(Triple, Opts); 8950 8951 case llvm::Triple::hexagon: 8952 return new HexagonTargetInfo(Triple, Opts); 8953 8954 case llvm::Triple::lanai: 8955 return new LanaiTargetInfo(Triple, Opts); 8956 8957 case llvm::Triple::aarch64: 8958 if (Triple.isOSDarwin()) 8959 return new DarwinAArch64TargetInfo(Triple, Opts); 8960 8961 switch (os) { 8962 case llvm::Triple::CloudABI: 8963 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8964 case llvm::Triple::FreeBSD: 8965 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8966 case llvm::Triple::Fuchsia: 8967 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8968 case llvm::Triple::Linux: 8969 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8970 case llvm::Triple::NetBSD: 8971 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8972 case llvm::Triple::OpenBSD: 8973 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8974 default: 8975 return new AArch64leTargetInfo(Triple, Opts); 8976 } 8977 8978 case llvm::Triple::aarch64_be: 8979 switch (os) { 8980 case llvm::Triple::FreeBSD: 8981 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8982 case llvm::Triple::Fuchsia: 8983 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8984 case llvm::Triple::Linux: 8985 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8986 case llvm::Triple::NetBSD: 8987 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8988 default: 8989 return new AArch64beTargetInfo(Triple, Opts); 8990 } 8991 8992 case llvm::Triple::arm: 8993 case llvm::Triple::thumb: 8994 if (Triple.isOSBinFormatMachO()) 8995 return new DarwinARMTargetInfo(Triple, Opts); 8996 8997 switch (os) { 8998 case llvm::Triple::CloudABI: 8999 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9000 case llvm::Triple::Linux: 9001 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9002 case llvm::Triple::FreeBSD: 9003 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9004 case llvm::Triple::NetBSD: 9005 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9006 case llvm::Triple::OpenBSD: 9007 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9008 case llvm::Triple::Bitrig: 9009 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9010 case llvm::Triple::RTEMS: 9011 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9012 case llvm::Triple::NaCl: 9013 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9014 case llvm::Triple::Win32: 9015 switch (Triple.getEnvironment()) { 9016 case llvm::Triple::Cygnus: 9017 return new CygwinARMTargetInfo(Triple, Opts); 9018 case llvm::Triple::GNU: 9019 return new MinGWARMTargetInfo(Triple, Opts); 9020 case llvm::Triple::Itanium: 9021 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9022 case llvm::Triple::MSVC: 9023 default: // Assume MSVC for unknown environments 9024 return new MicrosoftARMleTargetInfo(Triple, Opts); 9025 } 9026 default: 9027 return new ARMleTargetInfo(Triple, Opts); 9028 } 9029 9030 case llvm::Triple::armeb: 9031 case llvm::Triple::thumbeb: 9032 if (Triple.isOSDarwin()) 9033 return new DarwinARMTargetInfo(Triple, Opts); 9034 9035 switch (os) { 9036 case llvm::Triple::Linux: 9037 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9038 case llvm::Triple::FreeBSD: 9039 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9040 case llvm::Triple::NetBSD: 9041 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9042 case llvm::Triple::OpenBSD: 9043 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9044 case llvm::Triple::Bitrig: 9045 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9046 case llvm::Triple::RTEMS: 9047 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9048 case llvm::Triple::NaCl: 9049 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9050 default: 9051 return new ARMbeTargetInfo(Triple, Opts); 9052 } 9053 9054 case llvm::Triple::avr: 9055 return new AVRTargetInfo(Triple, Opts); 9056 case llvm::Triple::bpfeb: 9057 case llvm::Triple::bpfel: 9058 return new BPFTargetInfo(Triple, Opts); 9059 9060 case llvm::Triple::msp430: 9061 return new MSP430TargetInfo(Triple, Opts); 9062 9063 case llvm::Triple::mips: 9064 switch (os) { 9065 case llvm::Triple::Linux: 9066 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9067 case llvm::Triple::RTEMS: 9068 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9069 case llvm::Triple::FreeBSD: 9070 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9071 case llvm::Triple::NetBSD: 9072 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9073 default: 9074 return new MipsTargetInfo(Triple, Opts); 9075 } 9076 9077 case llvm::Triple::mipsel: 9078 switch (os) { 9079 case llvm::Triple::Linux: 9080 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9081 case llvm::Triple::RTEMS: 9082 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9083 case llvm::Triple::FreeBSD: 9084 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9085 case llvm::Triple::NetBSD: 9086 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9087 case llvm::Triple::NaCl: 9088 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9089 default: 9090 return new MipsTargetInfo(Triple, Opts); 9091 } 9092 9093 case llvm::Triple::mips64: 9094 switch (os) { 9095 case llvm::Triple::Linux: 9096 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9097 case llvm::Triple::RTEMS: 9098 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9099 case llvm::Triple::FreeBSD: 9100 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9101 case llvm::Triple::NetBSD: 9102 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9103 case llvm::Triple::OpenBSD: 9104 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9105 default: 9106 return new MipsTargetInfo(Triple, Opts); 9107 } 9108 9109 case llvm::Triple::mips64el: 9110 switch (os) { 9111 case llvm::Triple::Linux: 9112 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9113 case llvm::Triple::RTEMS: 9114 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9115 case llvm::Triple::FreeBSD: 9116 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9117 case llvm::Triple::NetBSD: 9118 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9119 case llvm::Triple::OpenBSD: 9120 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9121 default: 9122 return new MipsTargetInfo(Triple, Opts); 9123 } 9124 9125 case llvm::Triple::le32: 9126 switch (os) { 9127 case llvm::Triple::NaCl: 9128 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9129 default: 9130 return nullptr; 9131 } 9132 9133 case llvm::Triple::le64: 9134 return new Le64TargetInfo(Triple, Opts); 9135 9136 case llvm::Triple::ppc: 9137 if (Triple.isOSDarwin()) 9138 return new DarwinPPC32TargetInfo(Triple, Opts); 9139 switch (os) { 9140 case llvm::Triple::Linux: 9141 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9142 case llvm::Triple::FreeBSD: 9143 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9144 case llvm::Triple::NetBSD: 9145 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9146 case llvm::Triple::OpenBSD: 9147 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9148 case llvm::Triple::RTEMS: 9149 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9150 default: 9151 return new PPC32TargetInfo(Triple, Opts); 9152 } 9153 9154 case llvm::Triple::ppc64: 9155 if (Triple.isOSDarwin()) 9156 return new DarwinPPC64TargetInfo(Triple, Opts); 9157 switch (os) { 9158 case llvm::Triple::Linux: 9159 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9160 case llvm::Triple::Lv2: 9161 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9162 case llvm::Triple::FreeBSD: 9163 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9164 case llvm::Triple::NetBSD: 9165 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9166 default: 9167 return new PPC64TargetInfo(Triple, Opts); 9168 } 9169 9170 case llvm::Triple::ppc64le: 9171 switch (os) { 9172 case llvm::Triple::Linux: 9173 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9174 case llvm::Triple::NetBSD: 9175 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9176 default: 9177 return new PPC64TargetInfo(Triple, Opts); 9178 } 9179 9180 case llvm::Triple::nvptx: 9181 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9182 case llvm::Triple::nvptx64: 9183 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9184 9185 case llvm::Triple::amdgcn: 9186 case llvm::Triple::r600: 9187 return new AMDGPUTargetInfo(Triple, Opts); 9188 9189 case llvm::Triple::sparc: 9190 switch (os) { 9191 case llvm::Triple::Linux: 9192 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9193 case llvm::Triple::Solaris: 9194 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9195 case llvm::Triple::NetBSD: 9196 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9197 case llvm::Triple::OpenBSD: 9198 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9199 case llvm::Triple::RTEMS: 9200 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9201 default: 9202 return new SparcV8TargetInfo(Triple, Opts); 9203 } 9204 9205 // The 'sparcel' architecture copies all the above cases except for Solaris. 9206 case llvm::Triple::sparcel: 9207 switch (os) { 9208 case llvm::Triple::Linux: 9209 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9210 case llvm::Triple::NetBSD: 9211 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9212 case llvm::Triple::OpenBSD: 9213 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9214 case llvm::Triple::RTEMS: 9215 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9216 default: 9217 return new SparcV8elTargetInfo(Triple, Opts); 9218 } 9219 9220 case llvm::Triple::sparcv9: 9221 switch (os) { 9222 case llvm::Triple::Linux: 9223 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9224 case llvm::Triple::Solaris: 9225 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9226 case llvm::Triple::NetBSD: 9227 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9228 case llvm::Triple::OpenBSD: 9229 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9230 case llvm::Triple::FreeBSD: 9231 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9232 default: 9233 return new SparcV9TargetInfo(Triple, Opts); 9234 } 9235 9236 case llvm::Triple::systemz: 9237 switch (os) { 9238 case llvm::Triple::Linux: 9239 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9240 default: 9241 return new SystemZTargetInfo(Triple, Opts); 9242 } 9243 9244 case llvm::Triple::tce: 9245 return new TCETargetInfo(Triple, Opts); 9246 9247 case llvm::Triple::tcele: 9248 return new TCELETargetInfo(Triple, Opts); 9249 9250 case llvm::Triple::x86: 9251 if (Triple.isOSDarwin()) 9252 return new DarwinI386TargetInfo(Triple, Opts); 9253 9254 switch (os) { 9255 case llvm::Triple::CloudABI: 9256 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9257 case llvm::Triple::Linux: { 9258 switch (Triple.getEnvironment()) { 9259 default: 9260 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9261 case llvm::Triple::Android: 9262 return new AndroidX86_32TargetInfo(Triple, Opts); 9263 } 9264 } 9265 case llvm::Triple::DragonFly: 9266 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9267 case llvm::Triple::NetBSD: 9268 return new NetBSDI386TargetInfo(Triple, Opts); 9269 case llvm::Triple::OpenBSD: 9270 return new OpenBSDI386TargetInfo(Triple, Opts); 9271 case llvm::Triple::Bitrig: 9272 return new BitrigI386TargetInfo(Triple, Opts); 9273 case llvm::Triple::FreeBSD: 9274 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9275 case llvm::Triple::KFreeBSD: 9276 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9277 case llvm::Triple::Minix: 9278 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9279 case llvm::Triple::Solaris: 9280 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9281 case llvm::Triple::Win32: { 9282 switch (Triple.getEnvironment()) { 9283 case llvm::Triple::Cygnus: 9284 return new CygwinX86_32TargetInfo(Triple, Opts); 9285 case llvm::Triple::GNU: 9286 return new MinGWX86_32TargetInfo(Triple, Opts); 9287 case llvm::Triple::Itanium: 9288 case llvm::Triple::MSVC: 9289 default: // Assume MSVC for unknown environments 9290 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9291 } 9292 } 9293 case llvm::Triple::Haiku: 9294 return new HaikuX86_32TargetInfo(Triple, Opts); 9295 case llvm::Triple::RTEMS: 9296 return new RTEMSX86_32TargetInfo(Triple, Opts); 9297 case llvm::Triple::NaCl: 9298 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9299 case llvm::Triple::ELFIAMCU: 9300 return new MCUX86_32TargetInfo(Triple, Opts); 9301 default: 9302 return new X86_32TargetInfo(Triple, Opts); 9303 } 9304 9305 case llvm::Triple::x86_64: 9306 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9307 return new DarwinX86_64TargetInfo(Triple, Opts); 9308 9309 switch (os) { 9310 case llvm::Triple::CloudABI: 9311 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9312 case llvm::Triple::Linux: { 9313 switch (Triple.getEnvironment()) { 9314 default: 9315 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9316 case llvm::Triple::Android: 9317 return new AndroidX86_64TargetInfo(Triple, Opts); 9318 } 9319 } 9320 case llvm::Triple::DragonFly: 9321 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9322 case llvm::Triple::NetBSD: 9323 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9324 case llvm::Triple::OpenBSD: 9325 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9326 case llvm::Triple::Bitrig: 9327 return new BitrigX86_64TargetInfo(Triple, Opts); 9328 case llvm::Triple::FreeBSD: 9329 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9330 case llvm::Triple::Fuchsia: 9331 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9332 case llvm::Triple::KFreeBSD: 9333 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9334 case llvm::Triple::Solaris: 9335 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9336 case llvm::Triple::Win32: { 9337 switch (Triple.getEnvironment()) { 9338 case llvm::Triple::Cygnus: 9339 return new CygwinX86_64TargetInfo(Triple, Opts); 9340 case llvm::Triple::GNU: 9341 return new MinGWX86_64TargetInfo(Triple, Opts); 9342 case llvm::Triple::MSVC: 9343 default: // Assume MSVC for unknown environments 9344 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9345 } 9346 } 9347 case llvm::Triple::Haiku: 9348 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9349 case llvm::Triple::NaCl: 9350 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9351 case llvm::Triple::PS4: 9352 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9353 default: 9354 return new X86_64TargetInfo(Triple, Opts); 9355 } 9356 9357 case llvm::Triple::spir: { 9358 if (Triple.getOS() != llvm::Triple::UnknownOS || 9359 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9360 return nullptr; 9361 return new SPIR32TargetInfo(Triple, Opts); 9362 } 9363 case llvm::Triple::spir64: { 9364 if (Triple.getOS() != llvm::Triple::UnknownOS || 9365 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9366 return nullptr; 9367 return new SPIR64TargetInfo(Triple, Opts); 9368 } 9369 case llvm::Triple::wasm32: 9370 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9371 Triple.getVendor() != llvm::Triple::UnknownVendor || 9372 Triple.getOS() != llvm::Triple::UnknownOS || 9373 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9374 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9375 return nullptr; 9376 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9377 case llvm::Triple::wasm64: 9378 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9379 Triple.getVendor() != llvm::Triple::UnknownVendor || 9380 Triple.getOS() != llvm::Triple::UnknownOS || 9381 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9382 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9383 return nullptr; 9384 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9385 9386 case llvm::Triple::renderscript32: 9387 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9388 case llvm::Triple::renderscript64: 9389 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9390 } 9391 } 9392 9393 /// CreateTargetInfo - Return the target info object for the specified target 9394 /// options. 9395 TargetInfo * 9396 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9397 const std::shared_ptr<TargetOptions> &Opts) { 9398 llvm::Triple Triple(Opts->Triple); 9399 9400 // Construct the target 9401 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9402 if (!Target) { 9403 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9404 return nullptr; 9405 } 9406 Target->TargetOpts = Opts; 9407 9408 // Set the target CPU if specified. 9409 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9410 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9411 return nullptr; 9412 } 9413 9414 // Set the target ABI if specified. 9415 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 9416 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 9417 return nullptr; 9418 } 9419 9420 // Set the fp math unit. 9421 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 9422 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 9423 return nullptr; 9424 } 9425 9426 // Compute the default target features, we need the target to handle this 9427 // because features may have dependencies on one another. 9428 llvm::StringMap<bool> Features; 9429 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 9430 Opts->FeaturesAsWritten)) 9431 return nullptr; 9432 9433 // Add the features to the compile options. 9434 Opts->Features.clear(); 9435 for (const auto &F : Features) 9436 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 9437 9438 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 9439 return nullptr; 9440 9441 Target->setSupportedOpenCLOpts(); 9442 Target->setOpenCLExtensionOpts(); 9443 9444 if (!Target->validateTarget(Diags)) 9445 return nullptr; 9446 9447 return Target.release(); 9448 } 9449