1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include <algorithm>
32 #include <memory>
33 using namespace clang;
34 
35 //===----------------------------------------------------------------------===//
36 //  Common code shared among targets.
37 //===----------------------------------------------------------------------===//
38 
39 /// DefineStd - Define a macro name and standard variants.  For example if
40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
41 /// when in GNU mode.
42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
43                       const LangOptions &Opts) {
44   assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
45 
46   // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
47   // in the user's namespace.
48   if (Opts.GNUMode)
49     Builder.defineMacro(MacroName);
50 
51   // Define __unix.
52   Builder.defineMacro("__" + MacroName);
53 
54   // Define __unix__.
55   Builder.defineMacro("__" + MacroName + "__");
56 }
57 
58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
59                             bool Tuning = true) {
60   Builder.defineMacro("__" + CPUName);
61   Builder.defineMacro("__" + CPUName + "__");
62   if (Tuning)
63     Builder.defineMacro("__tune_" + CPUName + "__");
64 }
65 
66 //===----------------------------------------------------------------------===//
67 // Defines specific to certain operating systems.
68 //===----------------------------------------------------------------------===//
69 
70 namespace {
71 template<typename TgtInfo>
72 class OSTargetInfo : public TgtInfo {
73 protected:
74   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
75                             MacroBuilder &Builder) const=0;
76 public:
77   OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
78   void getTargetDefines(const LangOptions &Opts,
79                         MacroBuilder &Builder) const override {
80     TgtInfo::getTargetDefines(Opts, Builder);
81     getOSDefines(Opts, TgtInfo::getTriple(), Builder);
82   }
83 
84 };
85 } // end anonymous namespace
86 
87 
88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
89                              const llvm::Triple &Triple,
90                              StringRef &PlatformName,
91                              VersionTuple &PlatformMinVersion) {
92   Builder.defineMacro("__APPLE_CC__", "6000");
93   Builder.defineMacro("__APPLE__");
94   Builder.defineMacro("OBJC_NEW_PROPERTIES");
95   // AddressSanitizer doesn't play well with source fortification, which is on
96   // by default on Darwin.
97   if (Opts.Sanitize.has(SanitizerKind::Address))
98     Builder.defineMacro("_FORTIFY_SOURCE", "0");
99 
100   if (!Opts.ObjCAutoRefCount) {
101     // __weak is always defined, for use in blocks and with objc pointers.
102     Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
103 
104     // Darwin defines __strong even in C mode (just to nothing).
105     if (Opts.getGC() != LangOptions::NonGC)
106       Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
107     else
108       Builder.defineMacro("__strong", "");
109 
110     // __unsafe_unretained is defined to nothing in non-ARC mode. We even
111     // allow this in C, since one might have block pointers in structs that
112     // are used in pure C code and in Objective-C ARC.
113     Builder.defineMacro("__unsafe_unretained", "");
114   }
115 
116   if (Opts.Static)
117     Builder.defineMacro("__STATIC__");
118   else
119     Builder.defineMacro("__DYNAMIC__");
120 
121   if (Opts.POSIXThreads)
122     Builder.defineMacro("_REENTRANT");
123 
124   // Get the platform type and version number from the triple.
125   unsigned Maj, Min, Rev;
126   if (Triple.isMacOSX()) {
127     Triple.getMacOSXVersion(Maj, Min, Rev);
128     PlatformName = "macosx";
129   } else {
130     Triple.getOSVersion(Maj, Min, Rev);
131     PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
132   }
133 
134   // If -target arch-pc-win32-macho option specified, we're
135   // generating code for Win32 ABI. No need to emit
136   // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
137   if (PlatformName == "win32") {
138     PlatformMinVersion = VersionTuple(Maj, Min, Rev);
139     return;
140   }
141 
142   // Set the appropriate OS version define.
143   if (Triple.isiOS()) {
144     assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
145     char Str[6];
146     Str[0] = '0' + Maj;
147     Str[1] = '0' + (Min / 10);
148     Str[2] = '0' + (Min % 10);
149     Str[3] = '0' + (Rev / 10);
150     Str[4] = '0' + (Rev % 10);
151     Str[5] = '\0';
152     Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
153                         Str);
154   } else if (Triple.isMacOSX()) {
155     // Note that the Driver allows versions which aren't representable in the
156     // define (because we only get a single digit for the minor and micro
157     // revision numbers). So, we limit them to the maximum representable
158     // version.
159     assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
160     char Str[7];
161     if (Maj < 10 || (Maj == 10 && Min < 10)) {
162       Str[0] = '0' + (Maj / 10);
163       Str[1] = '0' + (Maj % 10);
164       Str[2] = '0' + std::min(Min, 9U);
165       Str[3] = '0' + std::min(Rev, 9U);
166       Str[4] = '\0';
167     } else {
168       // Handle versions > 10.9.
169       Str[0] = '0' + (Maj / 10);
170       Str[1] = '0' + (Maj % 10);
171       Str[2] = '0' + (Min / 10);
172       Str[3] = '0' + (Min % 10);
173       Str[4] = '0' + (Rev / 10);
174       Str[5] = '0' + (Rev % 10);
175       Str[6] = '\0';
176     }
177     Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
178   }
179 
180   // Tell users about the kernel if there is one.
181   if (Triple.isOSDarwin())
182     Builder.defineMacro("__MACH__");
183 
184   PlatformMinVersion = VersionTuple(Maj, Min, Rev);
185 }
186 
187 namespace {
188 template<typename Target>
189 class DarwinTargetInfo : public OSTargetInfo<Target> {
190 protected:
191   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
192                     MacroBuilder &Builder) const override {
193     getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
194                      this->PlatformMinVersion);
195   }
196 
197 public:
198   DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
199     this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
200     this->MCountName = "\01mcount";
201   }
202 
203   std::string isValidSectionSpecifier(StringRef SR) const override {
204     // Let MCSectionMachO validate this.
205     StringRef Segment, Section;
206     unsigned TAA, StubSize;
207     bool HasTAA;
208     return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
209                                                        TAA, HasTAA, StubSize);
210   }
211 
212   const char *getStaticInitSectionSpecifier() const override {
213     // FIXME: We should return 0 when building kexts.
214     return "__TEXT,__StaticInit,regular,pure_instructions";
215   }
216 
217   /// Darwin does not support protected visibility.  Darwin's "default"
218   /// is very similar to ELF's "protected";  Darwin requires a "weak"
219   /// attribute on declarations that can be dynamically replaced.
220   bool hasProtectedVisibility() const override {
221     return false;
222   }
223 };
224 
225 
226 // DragonFlyBSD Target
227 template<typename Target>
228 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
229 protected:
230   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
231                     MacroBuilder &Builder) const override {
232     // DragonFly defines; list based off of gcc output
233     Builder.defineMacro("__DragonFly__");
234     Builder.defineMacro("__DragonFly_cc_version", "100001");
235     Builder.defineMacro("__ELF__");
236     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
237     Builder.defineMacro("__tune_i386__");
238     DefineStd(Builder, "unix", Opts);
239   }
240 public:
241   DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
242       : OSTargetInfo<Target>(Triple) {
243     this->UserLabelPrefix = "";
244 
245     switch (Triple.getArch()) {
246     default:
247     case llvm::Triple::x86:
248     case llvm::Triple::x86_64:
249       this->MCountName = ".mcount";
250       break;
251     }
252   }
253 };
254 
255 // FreeBSD Target
256 template<typename Target>
257 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
258 protected:
259   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
260                     MacroBuilder &Builder) const override {
261     // FreeBSD defines; list based off of gcc output
262 
263     unsigned Release = Triple.getOSMajorVersion();
264     if (Release == 0U)
265       Release = 8;
266 
267     Builder.defineMacro("__FreeBSD__", Twine(Release));
268     Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
269     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
270     DefineStd(Builder, "unix", Opts);
271     Builder.defineMacro("__ELF__");
272 
273     // On FreeBSD, wchar_t contains the number of the code point as
274     // used by the character set of the locale. These character sets are
275     // not necessarily a superset of ASCII.
276     Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
277   }
278 public:
279   FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
280     this->UserLabelPrefix = "";
281 
282     switch (Triple.getArch()) {
283     default:
284     case llvm::Triple::x86:
285     case llvm::Triple::x86_64:
286       this->MCountName = ".mcount";
287       break;
288     case llvm::Triple::mips:
289     case llvm::Triple::mipsel:
290     case llvm::Triple::ppc:
291     case llvm::Triple::ppc64:
292     case llvm::Triple::ppc64le:
293       this->MCountName = "_mcount";
294       break;
295     case llvm::Triple::arm:
296       this->MCountName = "__mcount";
297       break;
298     }
299   }
300 };
301 
302 // GNU/kFreeBSD Target
303 template<typename Target>
304 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
305 protected:
306   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
307                     MacroBuilder &Builder) const override {
308     // GNU/kFreeBSD defines; list based off of gcc output
309 
310     DefineStd(Builder, "unix", Opts);
311     Builder.defineMacro("__FreeBSD_kernel__");
312     Builder.defineMacro("__GLIBC__");
313     Builder.defineMacro("__ELF__");
314     if (Opts.POSIXThreads)
315       Builder.defineMacro("_REENTRANT");
316     if (Opts.CPlusPlus)
317       Builder.defineMacro("_GNU_SOURCE");
318   }
319 public:
320   KFreeBSDTargetInfo(const llvm::Triple &Triple)
321       : OSTargetInfo<Target>(Triple) {
322     this->UserLabelPrefix = "";
323   }
324 };
325 
326 // Minix Target
327 template<typename Target>
328 class MinixTargetInfo : public OSTargetInfo<Target> {
329 protected:
330   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
331                     MacroBuilder &Builder) const override {
332     // Minix defines
333 
334     Builder.defineMacro("__minix", "3");
335     Builder.defineMacro("_EM_WSIZE", "4");
336     Builder.defineMacro("_EM_PSIZE", "4");
337     Builder.defineMacro("_EM_SSIZE", "2");
338     Builder.defineMacro("_EM_LSIZE", "4");
339     Builder.defineMacro("_EM_FSIZE", "4");
340     Builder.defineMacro("_EM_DSIZE", "8");
341     Builder.defineMacro("__ELF__");
342     DefineStd(Builder, "unix", Opts);
343   }
344 public:
345   MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
346     this->UserLabelPrefix = "";
347   }
348 };
349 
350 // Linux target
351 template<typename Target>
352 class LinuxTargetInfo : public OSTargetInfo<Target> {
353 protected:
354   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
355                     MacroBuilder &Builder) const override {
356     // Linux defines; list based off of gcc output
357     DefineStd(Builder, "unix", Opts);
358     DefineStd(Builder, "linux", Opts);
359     Builder.defineMacro("__gnu_linux__");
360     Builder.defineMacro("__ELF__");
361     if (Triple.getEnvironment() == llvm::Triple::Android)
362       Builder.defineMacro("__ANDROID__", "1");
363     if (Opts.POSIXThreads)
364       Builder.defineMacro("_REENTRANT");
365     if (Opts.CPlusPlus)
366       Builder.defineMacro("_GNU_SOURCE");
367   }
368 public:
369   LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
370     this->UserLabelPrefix = "";
371     this->WIntType = TargetInfo::UnsignedInt;
372 
373     switch (Triple.getArch()) {
374     default:
375       break;
376     case llvm::Triple::ppc:
377     case llvm::Triple::ppc64:
378     case llvm::Triple::ppc64le:
379       this->MCountName = "_mcount";
380       break;
381     }
382   }
383 
384   const char *getStaticInitSectionSpecifier() const override {
385     return ".text.startup";
386   }
387 };
388 
389 // NetBSD Target
390 template<typename Target>
391 class NetBSDTargetInfo : public OSTargetInfo<Target> {
392 protected:
393   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
394                     MacroBuilder &Builder) const override {
395     // NetBSD defines; list based off of gcc output
396     Builder.defineMacro("__NetBSD__");
397     Builder.defineMacro("__unix__");
398     Builder.defineMacro("__ELF__");
399     if (Opts.POSIXThreads)
400       Builder.defineMacro("_POSIX_THREADS");
401 
402     switch (Triple.getArch()) {
403     default:
404       break;
405     case llvm::Triple::arm:
406     case llvm::Triple::armeb:
407     case llvm::Triple::thumb:
408     case llvm::Triple::thumbeb:
409       Builder.defineMacro("__ARM_DWARF_EH__");
410       break;
411     }
412   }
413 public:
414   NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
415     this->UserLabelPrefix = "";
416   }
417 };
418 
419 // OpenBSD Target
420 template<typename Target>
421 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
422 protected:
423   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
424                     MacroBuilder &Builder) const override {
425     // OpenBSD defines; list based off of gcc output
426 
427     Builder.defineMacro("__OpenBSD__");
428     DefineStd(Builder, "unix", Opts);
429     Builder.defineMacro("__ELF__");
430     if (Opts.POSIXThreads)
431       Builder.defineMacro("_REENTRANT");
432   }
433 public:
434   OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
435     this->UserLabelPrefix = "";
436     this->TLSSupported = false;
437 
438       switch (Triple.getArch()) {
439         default:
440         case llvm::Triple::x86:
441         case llvm::Triple::x86_64:
442         case llvm::Triple::arm:
443         case llvm::Triple::sparc:
444           this->MCountName = "__mcount";
445           break;
446         case llvm::Triple::mips64:
447         case llvm::Triple::mips64el:
448         case llvm::Triple::ppc:
449         case llvm::Triple::sparcv9:
450           this->MCountName = "_mcount";
451           break;
452       }
453   }
454 };
455 
456 // Bitrig Target
457 template<typename Target>
458 class BitrigTargetInfo : public OSTargetInfo<Target> {
459 protected:
460   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
461                     MacroBuilder &Builder) const override {
462     // Bitrig defines; list based off of gcc output
463 
464     Builder.defineMacro("__Bitrig__");
465     DefineStd(Builder, "unix", Opts);
466     Builder.defineMacro("__ELF__");
467     if (Opts.POSIXThreads)
468       Builder.defineMacro("_REENTRANT");
469   }
470 public:
471   BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
472     this->UserLabelPrefix = "";
473     this->MCountName = "__mcount";
474   }
475 };
476 
477 // PSP Target
478 template<typename Target>
479 class PSPTargetInfo : public OSTargetInfo<Target> {
480 protected:
481   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
482                     MacroBuilder &Builder) const override {
483     // PSP defines; list based on the output of the pspdev gcc toolchain.
484     Builder.defineMacro("PSP");
485     Builder.defineMacro("_PSP");
486     Builder.defineMacro("__psp__");
487     Builder.defineMacro("__ELF__");
488   }
489 public:
490   PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
491     this->UserLabelPrefix = "";
492   }
493 };
494 
495 // PS3 PPU Target
496 template<typename Target>
497 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
498 protected:
499   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
500                     MacroBuilder &Builder) const override {
501     // PS3 PPU defines.
502     Builder.defineMacro("__PPC__");
503     Builder.defineMacro("__PPU__");
504     Builder.defineMacro("__CELLOS_LV2__");
505     Builder.defineMacro("__ELF__");
506     Builder.defineMacro("__LP32__");
507     Builder.defineMacro("_ARCH_PPC64");
508     Builder.defineMacro("__powerpc64__");
509   }
510 public:
511   PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
512     this->UserLabelPrefix = "";
513     this->LongWidth = this->LongAlign = 32;
514     this->PointerWidth = this->PointerAlign = 32;
515     this->IntMaxType = TargetInfo::SignedLongLong;
516     this->Int64Type = TargetInfo::SignedLongLong;
517     this->SizeType = TargetInfo::UnsignedInt;
518     this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
519   }
520 };
521 
522 // Solaris target
523 template<typename Target>
524 class SolarisTargetInfo : public OSTargetInfo<Target> {
525 protected:
526   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
527                     MacroBuilder &Builder) const override {
528     DefineStd(Builder, "sun", Opts);
529     DefineStd(Builder, "unix", Opts);
530     Builder.defineMacro("__ELF__");
531     Builder.defineMacro("__svr4__");
532     Builder.defineMacro("__SVR4");
533     // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
534     // newer, but to 500 for everything else.  feature_test.h has a check to
535     // ensure that you are not using C99 with an old version of X/Open or C89
536     // with a new version.
537     if (Opts.C99)
538       Builder.defineMacro("_XOPEN_SOURCE", "600");
539     else
540       Builder.defineMacro("_XOPEN_SOURCE", "500");
541     if (Opts.CPlusPlus)
542       Builder.defineMacro("__C99FEATURES__");
543     Builder.defineMacro("_LARGEFILE_SOURCE");
544     Builder.defineMacro("_LARGEFILE64_SOURCE");
545     Builder.defineMacro("__EXTENSIONS__");
546     Builder.defineMacro("_REENTRANT");
547   }
548 public:
549   SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
550     this->UserLabelPrefix = "";
551     this->WCharType = this->SignedInt;
552     // FIXME: WIntType should be SignedLong
553   }
554 };
555 
556 // Windows target
557 template<typename Target>
558 class WindowsTargetInfo : public OSTargetInfo<Target> {
559 protected:
560   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
561                     MacroBuilder &Builder) const override {
562     Builder.defineMacro("_WIN32");
563   }
564   void getVisualStudioDefines(const LangOptions &Opts,
565                               MacroBuilder &Builder) const {
566     if (Opts.CPlusPlus) {
567       if (Opts.RTTIData)
568         Builder.defineMacro("_CPPRTTI");
569 
570       if (Opts.Exceptions)
571         Builder.defineMacro("_CPPUNWIND");
572     }
573 
574     if (!Opts.CharIsSigned)
575       Builder.defineMacro("_CHAR_UNSIGNED");
576 
577     // FIXME: POSIXThreads isn't exactly the option this should be defined for,
578     //        but it works for now.
579     if (Opts.POSIXThreads)
580       Builder.defineMacro("_MT");
581 
582     if (Opts.MSCompatibilityVersion) {
583       Builder.defineMacro("_MSC_VER",
584                           Twine(Opts.MSCompatibilityVersion / 100000));
585       Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
586       // FIXME We cannot encode the revision information into 32-bits
587       Builder.defineMacro("_MSC_BUILD", Twine(1));
588     }
589 
590     if (Opts.MicrosoftExt) {
591       Builder.defineMacro("_MSC_EXTENSIONS");
592 
593       if (Opts.CPlusPlus11) {
594         Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
595         Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
596         Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
597       }
598     }
599 
600     Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
601   }
602 
603 public:
604   WindowsTargetInfo(const llvm::Triple &Triple)
605       : OSTargetInfo<Target>(Triple) {}
606 };
607 
608 template <typename Target>
609 class NaClTargetInfo : public OSTargetInfo<Target> {
610 protected:
611   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
612                     MacroBuilder &Builder) const override {
613     if (Opts.POSIXThreads)
614       Builder.defineMacro("_REENTRANT");
615     if (Opts.CPlusPlus)
616       Builder.defineMacro("_GNU_SOURCE");
617 
618     DefineStd(Builder, "unix", Opts);
619     Builder.defineMacro("__ELF__");
620     Builder.defineMacro("__native_client__");
621   }
622 
623 public:
624   NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
625     this->UserLabelPrefix = "";
626     this->LongAlign = 32;
627     this->LongWidth = 32;
628     this->PointerAlign = 32;
629     this->PointerWidth = 32;
630     this->IntMaxType = TargetInfo::SignedLongLong;
631     this->Int64Type = TargetInfo::SignedLongLong;
632     this->DoubleAlign = 64;
633     this->LongDoubleWidth = 64;
634     this->LongDoubleAlign = 64;
635     this->LongLongWidth = 64;
636     this->LongLongAlign = 64;
637     this->SizeType = TargetInfo::UnsignedInt;
638     this->PtrDiffType = TargetInfo::SignedInt;
639     this->IntPtrType = TargetInfo::SignedInt;
640     // RegParmMax is inherited from the underlying architecture
641     this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
642     if (Triple.getArch() == llvm::Triple::arm) {
643       this->DescriptionString =
644           "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
645     } else if (Triple.getArch() == llvm::Triple::x86) {
646       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
647     } else if (Triple.getArch() == llvm::Triple::x86_64) {
648       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
649     } else if (Triple.getArch() == llvm::Triple::mipsel) {
650       // Handled on mips' setDescriptionString.
651     } else {
652       assert(Triple.getArch() == llvm::Triple::le32);
653       this->DescriptionString = "e-p:32:32-i64:64";
654     }
655   }
656   typename Target::CallingConvCheckResult checkCallingConvention(
657       CallingConv CC) const override {
658     return CC == CC_PnaclCall ? Target::CCCR_OK :
659         Target::checkCallingConvention(CC);
660   }
661 };
662 } // end anonymous namespace.
663 
664 //===----------------------------------------------------------------------===//
665 // Specific target implementations.
666 //===----------------------------------------------------------------------===//
667 
668 namespace {
669 // PPC abstract base class
670 class PPCTargetInfo : public TargetInfo {
671   static const Builtin::Info BuiltinInfo[];
672   static const char * const GCCRegNames[];
673   static const TargetInfo::GCCRegAlias GCCRegAliases[];
674   std::string CPU;
675 
676   // Target cpu features.
677   bool HasVSX;
678   bool HasP8Vector;
679 
680 protected:
681   std::string ABI;
682 
683 public:
684   PPCTargetInfo(const llvm::Triple &Triple)
685     : TargetInfo(Triple), HasVSX(false), HasP8Vector(false) {
686     BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
687     LongDoubleWidth = LongDoubleAlign = 128;
688     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
689   }
690 
691   /// \brief Flags for architecture specific defines.
692   typedef enum {
693     ArchDefineNone  = 0,
694     ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
695     ArchDefinePpcgr = 1 << 1,
696     ArchDefinePpcsq = 1 << 2,
697     ArchDefine440   = 1 << 3,
698     ArchDefine603   = 1 << 4,
699     ArchDefine604   = 1 << 5,
700     ArchDefinePwr4  = 1 << 6,
701     ArchDefinePwr5  = 1 << 7,
702     ArchDefinePwr5x = 1 << 8,
703     ArchDefinePwr6  = 1 << 9,
704     ArchDefinePwr6x = 1 << 10,
705     ArchDefinePwr7  = 1 << 11,
706     ArchDefinePwr8  = 1 << 12,
707     ArchDefineA2    = 1 << 13,
708     ArchDefineA2q   = 1 << 14
709   } ArchDefineTypes;
710 
711   // Note: GCC recognizes the following additional cpus:
712   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
713   //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
714   //  titan, rs64.
715   bool setCPU(const std::string &Name) override {
716     bool CPUKnown = llvm::StringSwitch<bool>(Name)
717       .Case("generic", true)
718       .Case("440", true)
719       .Case("450", true)
720       .Case("601", true)
721       .Case("602", true)
722       .Case("603", true)
723       .Case("603e", true)
724       .Case("603ev", true)
725       .Case("604", true)
726       .Case("604e", true)
727       .Case("620", true)
728       .Case("630", true)
729       .Case("g3", true)
730       .Case("7400", true)
731       .Case("g4", true)
732       .Case("7450", true)
733       .Case("g4+", true)
734       .Case("750", true)
735       .Case("970", true)
736       .Case("g5", true)
737       .Case("a2", true)
738       .Case("a2q", true)
739       .Case("e500mc", true)
740       .Case("e5500", true)
741       .Case("power3", true)
742       .Case("pwr3", true)
743       .Case("power4", true)
744       .Case("pwr4", true)
745       .Case("power5", true)
746       .Case("pwr5", true)
747       .Case("power5x", true)
748       .Case("pwr5x", true)
749       .Case("power6", true)
750       .Case("pwr6", true)
751       .Case("power6x", true)
752       .Case("pwr6x", true)
753       .Case("power7", true)
754       .Case("pwr7", true)
755       .Case("power8", true)
756       .Case("pwr8", true)
757       .Case("powerpc", true)
758       .Case("ppc", true)
759       .Case("powerpc64", true)
760       .Case("ppc64", true)
761       .Case("powerpc64le", true)
762       .Case("ppc64le", true)
763       .Default(false);
764 
765     if (CPUKnown)
766       CPU = Name;
767 
768     return CPUKnown;
769   }
770 
771 
772   StringRef getABI() const override { return ABI; }
773 
774   void getTargetBuiltins(const Builtin::Info *&Records,
775                          unsigned &NumRecords) const override {
776     Records = BuiltinInfo;
777     NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
778   }
779 
780   bool isCLZForZeroUndef() const override { return false; }
781 
782   void getTargetDefines(const LangOptions &Opts,
783                         MacroBuilder &Builder) const override;
784 
785   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
786 
787   bool handleTargetFeatures(std::vector<std::string> &Features,
788                             DiagnosticsEngine &Diags) override;
789   bool hasFeature(StringRef Feature) const override;
790 
791   void getGCCRegNames(const char * const *&Names,
792                       unsigned &NumNames) const override;
793   void getGCCRegAliases(const GCCRegAlias *&Aliases,
794                         unsigned &NumAliases) const override;
795   bool validateAsmConstraint(const char *&Name,
796                              TargetInfo::ConstraintInfo &Info) const override {
797     switch (*Name) {
798     default: return false;
799     case 'O': // Zero
800       break;
801     case 'b': // Base register
802     case 'f': // Floating point register
803       Info.setAllowsRegister();
804       break;
805     // FIXME: The following are added to allow parsing.
806     // I just took a guess at what the actions should be.
807     // Also, is more specific checking needed?  I.e. specific registers?
808     case 'd': // Floating point register (containing 64-bit value)
809     case 'v': // Altivec vector register
810       Info.setAllowsRegister();
811       break;
812     case 'w':
813       switch (Name[1]) {
814         case 'd':// VSX vector register to hold vector double data
815         case 'f':// VSX vector register to hold vector float data
816         case 's':// VSX vector register to hold scalar float data
817         case 'a':// Any VSX register
818         case 'c':// An individual CR bit
819           break;
820         default:
821           return false;
822       }
823       Info.setAllowsRegister();
824       Name++; // Skip over 'w'.
825       break;
826     case 'h': // `MQ', `CTR', or `LINK' register
827     case 'q': // `MQ' register
828     case 'c': // `CTR' register
829     case 'l': // `LINK' register
830     case 'x': // `CR' register (condition register) number 0
831     case 'y': // `CR' register (condition register)
832     case 'z': // `XER[CA]' carry bit (part of the XER register)
833       Info.setAllowsRegister();
834       break;
835     case 'I': // Signed 16-bit constant
836     case 'J': // Unsigned 16-bit constant shifted left 16 bits
837               //  (use `L' instead for SImode constants)
838     case 'K': // Unsigned 16-bit constant
839     case 'L': // Signed 16-bit constant shifted left 16 bits
840     case 'M': // Constant larger than 31
841     case 'N': // Exact power of 2
842     case 'P': // Constant whose negation is a signed 16-bit constant
843     case 'G': // Floating point constant that can be loaded into a
844               // register with one instruction per word
845     case 'H': // Integer/Floating point constant that can be loaded
846               // into a register using three instructions
847       break;
848     case 'm': // Memory operand. Note that on PowerPC targets, m can
849               // include addresses that update the base register. It
850               // is therefore only safe to use `m' in an asm statement
851               // if that asm statement accesses the operand exactly once.
852               // The asm statement must also use `%U<opno>' as a
853               // placeholder for the "update" flag in the corresponding
854               // load or store instruction. For example:
855               // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
856               // is correct but:
857               // asm ("st %1,%0" : "=m" (mem) : "r" (val));
858               // is not. Use es rather than m if you don't want the base
859               // register to be updated.
860     case 'e':
861       if (Name[1] != 's')
862           return false;
863               // es: A "stable" memory operand; that is, one which does not
864               // include any automodification of the base register. Unlike
865               // `m', this constraint can be used in asm statements that
866               // might access the operand several times, or that might not
867               // access it at all.
868       Info.setAllowsMemory();
869       Name++; // Skip over 'e'.
870       break;
871     case 'Q': // Memory operand that is an offset from a register (it is
872               // usually better to use `m' or `es' in asm statements)
873     case 'Z': // Memory operand that is an indexed or indirect from a
874               // register (it is usually better to use `m' or `es' in
875               // asm statements)
876       Info.setAllowsMemory();
877       Info.setAllowsRegister();
878       break;
879     case 'R': // AIX TOC entry
880     case 'a': // Address operand that is an indexed or indirect from a
881               // register (`p' is preferable for asm statements)
882     case 'S': // Constant suitable as a 64-bit mask operand
883     case 'T': // Constant suitable as a 32-bit mask operand
884     case 'U': // System V Release 4 small data area reference
885     case 't': // AND masks that can be performed by two rldic{l, r}
886               // instructions
887     case 'W': // Vector constant that does not require memory
888     case 'j': // Vector constant that is all zeros.
889       break;
890     // End FIXME.
891     }
892     return true;
893   }
894   std::string convertConstraint(const char *&Constraint) const override {
895     std::string R;
896     switch (*Constraint) {
897     case 'e':
898     case 'w':
899       // Two-character constraint; add "^" hint for later parsing.
900       R = std::string("^") + std::string(Constraint, 2);
901       Constraint++;
902       break;
903     default:
904       return TargetInfo::convertConstraint(Constraint);
905     }
906     return R;
907   }
908   const char *getClobbers() const override {
909     return "";
910   }
911   int getEHDataRegisterNumber(unsigned RegNo) const override {
912     if (RegNo == 0) return 3;
913     if (RegNo == 1) return 4;
914     return -1;
915   }
916 };
917 
918 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
919 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
920 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
921                                               ALL_LANGUAGES },
922 #include "clang/Basic/BuiltinsPPC.def"
923 };
924 
925 /// handleTargetFeatures - Perform initialization based on the user
926 /// configured set of features.
927 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
928                                          DiagnosticsEngine &Diags) {
929   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
930     // Ignore disabled features.
931     if (Features[i][0] == '-')
932       continue;
933 
934     StringRef Feature = StringRef(Features[i]).substr(1);
935 
936     if (Feature == "vsx") {
937       HasVSX = true;
938       continue;
939     }
940 
941     if (Feature == "power8-vector") {
942       HasP8Vector = true;
943       continue;
944     }
945 
946     // TODO: Finish this list and add an assert that we've handled them
947     // all.
948   }
949 
950   return true;
951 }
952 
953 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
954 /// #defines that are not tied to a specific subtarget.
955 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
956                                      MacroBuilder &Builder) const {
957   // Target identification.
958   Builder.defineMacro("__ppc__");
959   Builder.defineMacro("__PPC__");
960   Builder.defineMacro("_ARCH_PPC");
961   Builder.defineMacro("__powerpc__");
962   Builder.defineMacro("__POWERPC__");
963   if (PointerWidth == 64) {
964     Builder.defineMacro("_ARCH_PPC64");
965     Builder.defineMacro("__powerpc64__");
966     Builder.defineMacro("__ppc64__");
967     Builder.defineMacro("__PPC64__");
968   }
969 
970   // Target properties.
971   if (getTriple().getArch() == llvm::Triple::ppc64le) {
972     Builder.defineMacro("_LITTLE_ENDIAN");
973   } else {
974     if (getTriple().getOS() != llvm::Triple::NetBSD &&
975         getTriple().getOS() != llvm::Triple::OpenBSD)
976       Builder.defineMacro("_BIG_ENDIAN");
977   }
978 
979   // ABI options.
980   if (ABI == "elfv1")
981     Builder.defineMacro("_CALL_ELF", "1");
982   if (ABI == "elfv2")
983     Builder.defineMacro("_CALL_ELF", "2");
984 
985   // Subtarget options.
986   Builder.defineMacro("__NATURAL_ALIGNMENT__");
987   Builder.defineMacro("__REGISTER_PREFIX__", "");
988 
989   // FIXME: Should be controlled by command line option.
990   if (LongDoubleWidth == 128)
991     Builder.defineMacro("__LONG_DOUBLE_128__");
992 
993   if (Opts.AltiVec) {
994     Builder.defineMacro("__VEC__", "10206");
995     Builder.defineMacro("__ALTIVEC__");
996   }
997 
998   // CPU identification.
999   ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1000     .Case("440",   ArchDefineName)
1001     .Case("450",   ArchDefineName | ArchDefine440)
1002     .Case("601",   ArchDefineName)
1003     .Case("602",   ArchDefineName | ArchDefinePpcgr)
1004     .Case("603",   ArchDefineName | ArchDefinePpcgr)
1005     .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1006     .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1007     .Case("604",   ArchDefineName | ArchDefinePpcgr)
1008     .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1009     .Case("620",   ArchDefineName | ArchDefinePpcgr)
1010     .Case("630",   ArchDefineName | ArchDefinePpcgr)
1011     .Case("7400",  ArchDefineName | ArchDefinePpcgr)
1012     .Case("7450",  ArchDefineName | ArchDefinePpcgr)
1013     .Case("750",   ArchDefineName | ArchDefinePpcgr)
1014     .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1015                      | ArchDefinePpcsq)
1016     .Case("a2",    ArchDefineA2)
1017     .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1018     .Case("pwr3",  ArchDefinePpcgr)
1019     .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1020     .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1021                      | ArchDefinePpcsq)
1022     .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1023                      | ArchDefinePpcgr | ArchDefinePpcsq)
1024     .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1025                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1026     .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1027                      | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1028                      | ArchDefinePpcsq)
1029     .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1030                      | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1031                      | ArchDefinePpcgr | ArchDefinePpcsq)
1032     .Case("pwr8",  ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1033                      | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1034                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1035     .Case("power3",  ArchDefinePpcgr)
1036     .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1037     .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1038                        | ArchDefinePpcsq)
1039     .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1040                        | ArchDefinePpcgr | ArchDefinePpcsq)
1041     .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1042                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1043     .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1044                        | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1045                        | ArchDefinePpcsq)
1046     .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1047                        | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1048                        | ArchDefinePpcgr | ArchDefinePpcsq)
1049     .Case("power8",  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1050                        | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1051                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1052     .Default(ArchDefineNone);
1053 
1054   if (defs & ArchDefineName)
1055     Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1056   if (defs & ArchDefinePpcgr)
1057     Builder.defineMacro("_ARCH_PPCGR");
1058   if (defs & ArchDefinePpcsq)
1059     Builder.defineMacro("_ARCH_PPCSQ");
1060   if (defs & ArchDefine440)
1061     Builder.defineMacro("_ARCH_440");
1062   if (defs & ArchDefine603)
1063     Builder.defineMacro("_ARCH_603");
1064   if (defs & ArchDefine604)
1065     Builder.defineMacro("_ARCH_604");
1066   if (defs & ArchDefinePwr4)
1067     Builder.defineMacro("_ARCH_PWR4");
1068   if (defs & ArchDefinePwr5)
1069     Builder.defineMacro("_ARCH_PWR5");
1070   if (defs & ArchDefinePwr5x)
1071     Builder.defineMacro("_ARCH_PWR5X");
1072   if (defs & ArchDefinePwr6)
1073     Builder.defineMacro("_ARCH_PWR6");
1074   if (defs & ArchDefinePwr6x)
1075     Builder.defineMacro("_ARCH_PWR6X");
1076   if (defs & ArchDefinePwr7)
1077     Builder.defineMacro("_ARCH_PWR7");
1078   if (defs & ArchDefinePwr8)
1079     Builder.defineMacro("_ARCH_PWR8");
1080   if (defs & ArchDefineA2)
1081     Builder.defineMacro("_ARCH_A2");
1082   if (defs & ArchDefineA2q) {
1083     Builder.defineMacro("_ARCH_A2Q");
1084     Builder.defineMacro("_ARCH_QP");
1085   }
1086 
1087   if (getTriple().getVendor() == llvm::Triple::BGQ) {
1088     Builder.defineMacro("__bg__");
1089     Builder.defineMacro("__THW_BLUEGENE__");
1090     Builder.defineMacro("__bgq__");
1091     Builder.defineMacro("__TOS_BGQ__");
1092   }
1093 
1094   if (HasVSX)
1095     Builder.defineMacro("__VSX__");
1096   if (HasP8Vector)
1097     Builder.defineMacro("__POWER8_VECTOR__");
1098 
1099   // FIXME: The following are not yet generated here by Clang, but are
1100   //        generated by GCC:
1101   //
1102   //   _SOFT_FLOAT_
1103   //   __RECIP_PRECISION__
1104   //   __APPLE_ALTIVEC__
1105   //   __RECIP__
1106   //   __RECIPF__
1107   //   __RSQRTE__
1108   //   __RSQRTEF__
1109   //   _SOFT_DOUBLE_
1110   //   __NO_LWSYNC__
1111   //   __HAVE_BSWAP__
1112   //   __LONGDOUBLE128
1113   //   __CMODEL_MEDIUM__
1114   //   __CMODEL_LARGE__
1115   //   _CALL_SYSV
1116   //   _CALL_DARWIN
1117   //   __NO_FPRS__
1118 }
1119 
1120 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1121   Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1122     .Case("7400", true)
1123     .Case("g4", true)
1124     .Case("7450", true)
1125     .Case("g4+", true)
1126     .Case("970", true)
1127     .Case("g5", true)
1128     .Case("pwr6", true)
1129     .Case("pwr7", true)
1130     .Case("pwr8", true)
1131     .Case("ppc64", true)
1132     .Case("ppc64le", true)
1133     .Default(false);
1134 
1135   Features["qpx"] = (CPU == "a2q");
1136 
1137   if (!ABI.empty())
1138     Features[ABI] = true;
1139 }
1140 
1141 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1142   return llvm::StringSwitch<bool>(Feature)
1143     .Case("powerpc", true)
1144     .Case("vsx", HasVSX)
1145     .Case("power8-vector", HasP8Vector)
1146     .Default(false);
1147 }
1148 
1149 const char * const PPCTargetInfo::GCCRegNames[] = {
1150   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1151   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1152   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1153   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1154   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1155   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1156   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1157   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1158   "mq", "lr", "ctr", "ap",
1159   "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1160   "xer",
1161   "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1162   "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1163   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1164   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1165   "vrsave", "vscr",
1166   "spe_acc", "spefscr",
1167   "sfp"
1168 };
1169 
1170 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1171                                    unsigned &NumNames) const {
1172   Names = GCCRegNames;
1173   NumNames = llvm::array_lengthof(GCCRegNames);
1174 }
1175 
1176 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1177   // While some of these aliases do map to different registers
1178   // they still share the same register name.
1179   { { "0" }, "r0" },
1180   { { "1"}, "r1" },
1181   { { "2" }, "r2" },
1182   { { "3" }, "r3" },
1183   { { "4" }, "r4" },
1184   { { "5" }, "r5" },
1185   { { "6" }, "r6" },
1186   { { "7" }, "r7" },
1187   { { "8" }, "r8" },
1188   { { "9" }, "r9" },
1189   { { "10" }, "r10" },
1190   { { "11" }, "r11" },
1191   { { "12" }, "r12" },
1192   { { "13" }, "r13" },
1193   { { "14" }, "r14" },
1194   { { "15" }, "r15" },
1195   { { "16" }, "r16" },
1196   { { "17" }, "r17" },
1197   { { "18" }, "r18" },
1198   { { "19" }, "r19" },
1199   { { "20" }, "r20" },
1200   { { "21" }, "r21" },
1201   { { "22" }, "r22" },
1202   { { "23" }, "r23" },
1203   { { "24" }, "r24" },
1204   { { "25" }, "r25" },
1205   { { "26" }, "r26" },
1206   { { "27" }, "r27" },
1207   { { "28" }, "r28" },
1208   { { "29" }, "r29" },
1209   { { "30" }, "r30" },
1210   { { "31" }, "r31" },
1211   { { "fr0" }, "f0" },
1212   { { "fr1" }, "f1" },
1213   { { "fr2" }, "f2" },
1214   { { "fr3" }, "f3" },
1215   { { "fr4" }, "f4" },
1216   { { "fr5" }, "f5" },
1217   { { "fr6" }, "f6" },
1218   { { "fr7" }, "f7" },
1219   { { "fr8" }, "f8" },
1220   { { "fr9" }, "f9" },
1221   { { "fr10" }, "f10" },
1222   { { "fr11" }, "f11" },
1223   { { "fr12" }, "f12" },
1224   { { "fr13" }, "f13" },
1225   { { "fr14" }, "f14" },
1226   { { "fr15" }, "f15" },
1227   { { "fr16" }, "f16" },
1228   { { "fr17" }, "f17" },
1229   { { "fr18" }, "f18" },
1230   { { "fr19" }, "f19" },
1231   { { "fr20" }, "f20" },
1232   { { "fr21" }, "f21" },
1233   { { "fr22" }, "f22" },
1234   { { "fr23" }, "f23" },
1235   { { "fr24" }, "f24" },
1236   { { "fr25" }, "f25" },
1237   { { "fr26" }, "f26" },
1238   { { "fr27" }, "f27" },
1239   { { "fr28" }, "f28" },
1240   { { "fr29" }, "f29" },
1241   { { "fr30" }, "f30" },
1242   { { "fr31" }, "f31" },
1243   { { "cc" }, "cr0" },
1244 };
1245 
1246 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1247                                      unsigned &NumAliases) const {
1248   Aliases = GCCRegAliases;
1249   NumAliases = llvm::array_lengthof(GCCRegAliases);
1250 }
1251 } // end anonymous namespace.
1252 
1253 namespace {
1254 class PPC32TargetInfo : public PPCTargetInfo {
1255 public:
1256   PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1257     DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1258 
1259     switch (getTriple().getOS()) {
1260     case llvm::Triple::Linux:
1261     case llvm::Triple::FreeBSD:
1262     case llvm::Triple::NetBSD:
1263       SizeType = UnsignedInt;
1264       PtrDiffType = SignedInt;
1265       IntPtrType = SignedInt;
1266       break;
1267     default:
1268       break;
1269     }
1270 
1271     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1272       LongDoubleWidth = LongDoubleAlign = 64;
1273       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1274     }
1275 
1276     // PPC32 supports atomics up to 4 bytes.
1277     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1278   }
1279 
1280   BuiltinVaListKind getBuiltinVaListKind() const override {
1281     // This is the ELF definition, and is overridden by the Darwin sub-target
1282     return TargetInfo::PowerABIBuiltinVaList;
1283   }
1284 };
1285 } // end anonymous namespace.
1286 
1287 // Note: ABI differences may eventually require us to have a separate
1288 // TargetInfo for little endian.
1289 namespace {
1290 class PPC64TargetInfo : public PPCTargetInfo {
1291 public:
1292   PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1293     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1294     IntMaxType = SignedLong;
1295     Int64Type = SignedLong;
1296 
1297     if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1298       DescriptionString = "e-m:e-i64:64-n32:64";
1299       ABI = "elfv2";
1300     } else {
1301       DescriptionString = "E-m:e-i64:64-n32:64";
1302       ABI = "elfv1";
1303     }
1304 
1305     switch (getTriple().getOS()) {
1306     case llvm::Triple::FreeBSD:
1307       LongDoubleWidth = LongDoubleAlign = 64;
1308       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1309       break;
1310     case llvm::Triple::NetBSD:
1311       IntMaxType = SignedLongLong;
1312       Int64Type = SignedLongLong;
1313       break;
1314     default:
1315       break;
1316     }
1317 
1318     // PPC64 supports atomics up to 8 bytes.
1319     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1320   }
1321   BuiltinVaListKind getBuiltinVaListKind() const override {
1322     return TargetInfo::CharPtrBuiltinVaList;
1323   }
1324   // PPC64 Linux-specifc ABI options.
1325   bool setABI(const std::string &Name) override {
1326     if (Name == "elfv1" || Name == "elfv2") {
1327       ABI = Name;
1328       return true;
1329     }
1330     return false;
1331   }
1332 };
1333 } // end anonymous namespace.
1334 
1335 
1336 namespace {
1337 class DarwinPPC32TargetInfo :
1338   public DarwinTargetInfo<PPC32TargetInfo> {
1339 public:
1340   DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1341       : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1342     HasAlignMac68kSupport = true;
1343     BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1344     PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1345     LongLongAlign = 32;
1346     SuitableAlign = 128;
1347     DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1348   }
1349   BuiltinVaListKind getBuiltinVaListKind() const override {
1350     return TargetInfo::CharPtrBuiltinVaList;
1351   }
1352 };
1353 
1354 class DarwinPPC64TargetInfo :
1355   public DarwinTargetInfo<PPC64TargetInfo> {
1356 public:
1357   DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1358       : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1359     HasAlignMac68kSupport = true;
1360     SuitableAlign = 128;
1361     DescriptionString = "E-m:o-i64:64-n32:64";
1362   }
1363 };
1364 } // end anonymous namespace.
1365 
1366 namespace {
1367   static const unsigned NVPTXAddrSpaceMap[] = {
1368     1,    // opencl_global
1369     3,    // opencl_local
1370     4,    // opencl_constant
1371     // FIXME: generic has to be added to the target
1372     0,    // opencl_generic
1373     1,    // cuda_device
1374     4,    // cuda_constant
1375     3,    // cuda_shared
1376   };
1377   class NVPTXTargetInfo : public TargetInfo {
1378     static const char * const GCCRegNames[];
1379     static const Builtin::Info BuiltinInfo[];
1380 
1381   // The GPU profiles supported by the NVPTX backend
1382   enum GPUKind {
1383     GK_NONE,
1384     GK_SM20,
1385     GK_SM21,
1386     GK_SM30,
1387     GK_SM35,
1388   } GPU;
1389 
1390   public:
1391     NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1392       BigEndian = false;
1393       TLSSupported = false;
1394       LongWidth = LongAlign = 64;
1395       AddrSpaceMap = &NVPTXAddrSpaceMap;
1396       UseAddrSpaceMapMangling = true;
1397       // Define available target features
1398       // These must be defined in sorted order!
1399       NoAsmVariants = true;
1400       // Set the default GPU to sm20
1401       GPU = GK_SM20;
1402     }
1403     void getTargetDefines(const LangOptions &Opts,
1404                           MacroBuilder &Builder) const override {
1405       Builder.defineMacro("__PTX__");
1406       Builder.defineMacro("__NVPTX__");
1407       if (Opts.CUDAIsDevice) {
1408         // Set __CUDA_ARCH__ for the GPU specified.
1409         std::string CUDAArchCode;
1410         switch (GPU) {
1411         case GK_SM20:
1412           CUDAArchCode = "200";
1413           break;
1414         case GK_SM21:
1415           CUDAArchCode = "210";
1416           break;
1417         case GK_SM30:
1418           CUDAArchCode = "300";
1419           break;
1420         case GK_SM35:
1421           CUDAArchCode = "350";
1422           break;
1423         default:
1424           llvm_unreachable("Unhandled target CPU");
1425         }
1426         Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1427       }
1428     }
1429     void getTargetBuiltins(const Builtin::Info *&Records,
1430                            unsigned &NumRecords) const override {
1431       Records = BuiltinInfo;
1432       NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1433     }
1434     bool hasFeature(StringRef Feature) const override {
1435       return Feature == "ptx" || Feature == "nvptx";
1436     }
1437 
1438     void getGCCRegNames(const char * const *&Names,
1439                         unsigned &NumNames) const override;
1440     void getGCCRegAliases(const GCCRegAlias *&Aliases,
1441                                   unsigned &NumAliases) const override {
1442       // No aliases.
1443       Aliases = nullptr;
1444       NumAliases = 0;
1445     }
1446     bool
1447     validateAsmConstraint(const char *&Name,
1448                           TargetInfo::ConstraintInfo &Info) const override {
1449       switch (*Name) {
1450       default: return false;
1451       case 'c':
1452       case 'h':
1453       case 'r':
1454       case 'l':
1455       case 'f':
1456       case 'd':
1457         Info.setAllowsRegister();
1458         return true;
1459       }
1460     }
1461     const char *getClobbers() const override {
1462       // FIXME: Is this really right?
1463       return "";
1464     }
1465     BuiltinVaListKind getBuiltinVaListKind() const override {
1466       // FIXME: implement
1467       return TargetInfo::CharPtrBuiltinVaList;
1468     }
1469     bool setCPU(const std::string &Name) override {
1470       GPU = llvm::StringSwitch<GPUKind>(Name)
1471                 .Case("sm_20", GK_SM20)
1472                 .Case("sm_21", GK_SM21)
1473                 .Case("sm_30", GK_SM30)
1474                 .Case("sm_35", GK_SM35)
1475                 .Default(GK_NONE);
1476 
1477       return GPU != GK_NONE;
1478     }
1479   };
1480 
1481   const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1482 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1483 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1484                                               ALL_LANGUAGES },
1485 #include "clang/Basic/BuiltinsNVPTX.def"
1486   };
1487 
1488   const char * const NVPTXTargetInfo::GCCRegNames[] = {
1489     "r0"
1490   };
1491 
1492   void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1493                                      unsigned &NumNames) const {
1494     Names = GCCRegNames;
1495     NumNames = llvm::array_lengthof(GCCRegNames);
1496   }
1497 
1498   class NVPTX32TargetInfo : public NVPTXTargetInfo {
1499   public:
1500     NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1501       PointerWidth = PointerAlign = 32;
1502       SizeType     = PtrDiffType = TargetInfo::UnsignedInt;
1503       IntPtrType = TargetInfo::SignedInt;
1504       DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1505   }
1506   };
1507 
1508   class NVPTX64TargetInfo : public NVPTXTargetInfo {
1509   public:
1510     NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1511       PointerWidth = PointerAlign = 64;
1512       SizeType     = PtrDiffType = TargetInfo::UnsignedLongLong;
1513       IntPtrType = TargetInfo::SignedLongLong;
1514       DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1515   }
1516   };
1517 }
1518 
1519 namespace {
1520 
1521 static const unsigned R600AddrSpaceMap[] = {
1522   1,    // opencl_global
1523   3,    // opencl_local
1524   2,    // opencl_constant
1525   4,    // opencl_generic
1526   1,    // cuda_device
1527   2,    // cuda_constant
1528   3     // cuda_shared
1529 };
1530 
1531 // If you edit the description strings, make sure you update
1532 // getPointerWidthV().
1533 
1534 static const char *DescriptionStringR600 =
1535   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1536   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1537 
1538 static const char *DescriptionStringR600DoubleOps =
1539   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1540   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1541 
1542 static const char *DescriptionStringSI =
1543   "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1544   "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1545   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1546 
1547 class R600TargetInfo : public TargetInfo {
1548   static const Builtin::Info BuiltinInfo[];
1549 
1550   /// \brief The GPU profiles supported by the R600 target.
1551   enum GPUKind {
1552     GK_NONE,
1553     GK_R600,
1554     GK_R600_DOUBLE_OPS,
1555     GK_R700,
1556     GK_R700_DOUBLE_OPS,
1557     GK_EVERGREEN,
1558     GK_EVERGREEN_DOUBLE_OPS,
1559     GK_NORTHERN_ISLANDS,
1560     GK_CAYMAN,
1561     GK_SOUTHERN_ISLANDS,
1562     GK_SEA_ISLANDS
1563   } GPU;
1564 
1565 public:
1566   R600TargetInfo(const llvm::Triple &Triple)
1567       : TargetInfo(Triple), GPU(GK_R600) {
1568     DescriptionString = DescriptionStringR600;
1569     AddrSpaceMap = &R600AddrSpaceMap;
1570     UseAddrSpaceMapMangling = true;
1571   }
1572 
1573   uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1574     if (GPU <= GK_CAYMAN)
1575       return 32;
1576 
1577     switch(AddrSpace) {
1578       default:
1579         return 64;
1580       case 0:
1581       case 3:
1582       case 5:
1583         return 32;
1584     }
1585   }
1586 
1587   const char * getClobbers() const override {
1588     return "";
1589   }
1590 
1591   void getGCCRegNames(const char * const *&Names,
1592                       unsigned &numNames) const override {
1593     Names = nullptr;
1594     numNames = 0;
1595   }
1596 
1597   void getGCCRegAliases(const GCCRegAlias *&Aliases,
1598                         unsigned &NumAliases) const override {
1599     Aliases = nullptr;
1600     NumAliases = 0;
1601   }
1602 
1603   bool validateAsmConstraint(const char *&Name,
1604                              TargetInfo::ConstraintInfo &info) const override {
1605     return true;
1606   }
1607 
1608   void getTargetBuiltins(const Builtin::Info *&Records,
1609                          unsigned &NumRecords) const override {
1610     Records = BuiltinInfo;
1611     NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
1612   }
1613 
1614   void getTargetDefines(const LangOptions &Opts,
1615                         MacroBuilder &Builder) const override {
1616     Builder.defineMacro("__R600__");
1617   }
1618 
1619   BuiltinVaListKind getBuiltinVaListKind() const override {
1620     return TargetInfo::CharPtrBuiltinVaList;
1621   }
1622 
1623   bool setCPU(const std::string &Name) override {
1624     GPU = llvm::StringSwitch<GPUKind>(Name)
1625       .Case("r600" ,    GK_R600)
1626       .Case("rv610",    GK_R600)
1627       .Case("rv620",    GK_R600)
1628       .Case("rv630",    GK_R600)
1629       .Case("rv635",    GK_R600)
1630       .Case("rs780",    GK_R600)
1631       .Case("rs880",    GK_R600)
1632       .Case("rv670",    GK_R600_DOUBLE_OPS)
1633       .Case("rv710",    GK_R700)
1634       .Case("rv730",    GK_R700)
1635       .Case("rv740",    GK_R700_DOUBLE_OPS)
1636       .Case("rv770",    GK_R700_DOUBLE_OPS)
1637       .Case("palm",     GK_EVERGREEN)
1638       .Case("cedar",    GK_EVERGREEN)
1639       .Case("sumo",     GK_EVERGREEN)
1640       .Case("sumo2",    GK_EVERGREEN)
1641       .Case("redwood",  GK_EVERGREEN)
1642       .Case("juniper",  GK_EVERGREEN)
1643       .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1644       .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1645       .Case("barts",    GK_NORTHERN_ISLANDS)
1646       .Case("turks",    GK_NORTHERN_ISLANDS)
1647       .Case("caicos",   GK_NORTHERN_ISLANDS)
1648       .Case("cayman",   GK_CAYMAN)
1649       .Case("aruba",    GK_CAYMAN)
1650       .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1651       .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1652       .Case("verde",    GK_SOUTHERN_ISLANDS)
1653       .Case("oland",    GK_SOUTHERN_ISLANDS)
1654       .Case("hainan",   GK_SOUTHERN_ISLANDS)
1655       .Case("bonaire",  GK_SEA_ISLANDS)
1656       .Case("kabini",   GK_SEA_ISLANDS)
1657       .Case("kaveri",   GK_SEA_ISLANDS)
1658       .Case("hawaii",   GK_SEA_ISLANDS)
1659       .Case("mullins",  GK_SEA_ISLANDS)
1660       .Default(GK_NONE);
1661 
1662     if (GPU == GK_NONE) {
1663       return false;
1664     }
1665 
1666     // Set the correct data layout
1667     switch (GPU) {
1668     case GK_NONE:
1669     case GK_R600:
1670     case GK_R700:
1671     case GK_EVERGREEN:
1672     case GK_NORTHERN_ISLANDS:
1673       DescriptionString = DescriptionStringR600;
1674       break;
1675     case GK_R600_DOUBLE_OPS:
1676     case GK_R700_DOUBLE_OPS:
1677     case GK_EVERGREEN_DOUBLE_OPS:
1678     case GK_CAYMAN:
1679       DescriptionString = DescriptionStringR600DoubleOps;
1680       break;
1681     case GK_SOUTHERN_ISLANDS:
1682     case GK_SEA_ISLANDS:
1683       DescriptionString = DescriptionStringSI;
1684       break;
1685     }
1686 
1687     return true;
1688   }
1689 };
1690 
1691 const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
1692 #define BUILTIN(ID, TYPE, ATTRS)                \
1693   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1694 #include "clang/Basic/BuiltinsR600.def"
1695 };
1696 
1697 } // end anonymous namespace
1698 
1699 namespace {
1700 // Namespace for x86 abstract base class
1701 const Builtin::Info BuiltinInfo[] = {
1702 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1703 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1704                                               ALL_LANGUAGES },
1705 #include "clang/Basic/BuiltinsX86.def"
1706 };
1707 
1708 static const char* const GCCRegNames[] = {
1709   "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1710   "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1711   "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1712   "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1713   "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1714   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1715   "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1716   "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1717   "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1718 };
1719 
1720 const TargetInfo::AddlRegName AddlRegNames[] = {
1721   { { "al", "ah", "eax", "rax" }, 0 },
1722   { { "bl", "bh", "ebx", "rbx" }, 3 },
1723   { { "cl", "ch", "ecx", "rcx" }, 2 },
1724   { { "dl", "dh", "edx", "rdx" }, 1 },
1725   { { "esi", "rsi" }, 4 },
1726   { { "edi", "rdi" }, 5 },
1727   { { "esp", "rsp" }, 7 },
1728   { { "ebp", "rbp" }, 6 },
1729 };
1730 
1731 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1732 // most of the implementation can be shared.
1733 class X86TargetInfo : public TargetInfo {
1734   enum X86SSEEnum {
1735     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1736   } SSELevel;
1737   enum MMX3DNowEnum {
1738     NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1739   } MMX3DNowLevel;
1740   enum XOPEnum {
1741     NoXOP,
1742     SSE4A,
1743     FMA4,
1744     XOP
1745   } XOPLevel;
1746 
1747   bool HasAES;
1748   bool HasPCLMUL;
1749   bool HasLZCNT;
1750   bool HasRDRND;
1751   bool HasFSGSBASE;
1752   bool HasBMI;
1753   bool HasBMI2;
1754   bool HasPOPCNT;
1755   bool HasRTM;
1756   bool HasPRFCHW;
1757   bool HasRDSEED;
1758   bool HasADX;
1759   bool HasTBM;
1760   bool HasFMA;
1761   bool HasF16C;
1762   bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
1763       HasAVX512VL;
1764   bool HasSHA;
1765   bool HasCX16;
1766 
1767   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1768   ///
1769   /// Each enumeration represents a particular CPU supported by Clang. These
1770   /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1771   enum CPUKind {
1772     CK_Generic,
1773 
1774     /// \name i386
1775     /// i386-generation processors.
1776     //@{
1777     CK_i386,
1778     //@}
1779 
1780     /// \name i486
1781     /// i486-generation processors.
1782     //@{
1783     CK_i486,
1784     CK_WinChipC6,
1785     CK_WinChip2,
1786     CK_C3,
1787     //@}
1788 
1789     /// \name i586
1790     /// i586-generation processors, P5 microarchitecture based.
1791     //@{
1792     CK_i586,
1793     CK_Pentium,
1794     CK_PentiumMMX,
1795     //@}
1796 
1797     /// \name i686
1798     /// i686-generation processors, P6 / Pentium M microarchitecture based.
1799     //@{
1800     CK_i686,
1801     CK_PentiumPro,
1802     CK_Pentium2,
1803     CK_Pentium3,
1804     CK_Pentium3M,
1805     CK_PentiumM,
1806     CK_C3_2,
1807 
1808     /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1809     /// Clang however has some logic to suport this.
1810     // FIXME: Warn, deprecate, and potentially remove this.
1811     CK_Yonah,
1812     //@}
1813 
1814     /// \name Netburst
1815     /// Netburst microarchitecture based processors.
1816     //@{
1817     CK_Pentium4,
1818     CK_Pentium4M,
1819     CK_Prescott,
1820     CK_Nocona,
1821     //@}
1822 
1823     /// \name Core
1824     /// Core microarchitecture based processors.
1825     //@{
1826     CK_Core2,
1827 
1828     /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1829     /// codename which GCC no longer accepts as an option to -march, but Clang
1830     /// has some logic for recognizing it.
1831     // FIXME: Warn, deprecate, and potentially remove this.
1832     CK_Penryn,
1833     //@}
1834 
1835     /// \name Atom
1836     /// Atom processors
1837     //@{
1838     CK_Bonnell,
1839     CK_Silvermont,
1840     //@}
1841 
1842     /// \name Nehalem
1843     /// Nehalem microarchitecture based processors.
1844     CK_Nehalem,
1845 
1846     /// \name Westmere
1847     /// Westmere microarchitecture based processors.
1848     CK_Westmere,
1849 
1850     /// \name Sandy Bridge
1851     /// Sandy Bridge microarchitecture based processors.
1852     CK_SandyBridge,
1853 
1854     /// \name Ivy Bridge
1855     /// Ivy Bridge microarchitecture based processors.
1856     CK_IvyBridge,
1857 
1858     /// \name Haswell
1859     /// Haswell microarchitecture based processors.
1860     CK_Haswell,
1861 
1862     /// \name Broadwell
1863     /// Broadwell microarchitecture based processors.
1864     CK_Broadwell,
1865 
1866     /// \name Skylake
1867     /// Skylake microarchitecture based processors.
1868     CK_Skylake,
1869 
1870     /// \name Knights Landing
1871     /// Knights Landing processor.
1872     CK_KNL,
1873 
1874     /// \name K6
1875     /// K6 architecture processors.
1876     //@{
1877     CK_K6,
1878     CK_K6_2,
1879     CK_K6_3,
1880     //@}
1881 
1882     /// \name K7
1883     /// K7 architecture processors.
1884     //@{
1885     CK_Athlon,
1886     CK_AthlonThunderbird,
1887     CK_Athlon4,
1888     CK_AthlonXP,
1889     CK_AthlonMP,
1890     //@}
1891 
1892     /// \name K8
1893     /// K8 architecture processors.
1894     //@{
1895     CK_Athlon64,
1896     CK_Athlon64SSE3,
1897     CK_AthlonFX,
1898     CK_K8,
1899     CK_K8SSE3,
1900     CK_Opteron,
1901     CK_OpteronSSE3,
1902     CK_AMDFAM10,
1903     //@}
1904 
1905     /// \name Bobcat
1906     /// Bobcat architecture processors.
1907     //@{
1908     CK_BTVER1,
1909     CK_BTVER2,
1910     //@}
1911 
1912     /// \name Bulldozer
1913     /// Bulldozer architecture processors.
1914     //@{
1915     CK_BDVER1,
1916     CK_BDVER2,
1917     CK_BDVER3,
1918     CK_BDVER4,
1919     //@}
1920 
1921     /// This specification is deprecated and will be removed in the future.
1922     /// Users should prefer \see CK_K8.
1923     // FIXME: Warn on this when the CPU is set to it.
1924     //@{
1925     CK_x86_64,
1926     //@}
1927 
1928     /// \name Geode
1929     /// Geode processors.
1930     //@{
1931     CK_Geode
1932     //@}
1933   } CPU;
1934 
1935   enum FPMathKind {
1936     FP_Default,
1937     FP_SSE,
1938     FP_387
1939   } FPMath;
1940 
1941 public:
1942   X86TargetInfo(const llvm::Triple &Triple)
1943       : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1944         XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
1945         HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
1946         HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
1947         HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
1948         HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
1949         HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
1950         HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
1951     BigEndian = false;
1952     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1953   }
1954   unsigned getFloatEvalMethod() const override {
1955     // X87 evaluates with 80 bits "long double" precision.
1956     return SSELevel == NoSSE ? 2 : 0;
1957   }
1958   void getTargetBuiltins(const Builtin::Info *&Records,
1959                                  unsigned &NumRecords) const override {
1960     Records = BuiltinInfo;
1961     NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1962   }
1963   void getGCCRegNames(const char * const *&Names,
1964                       unsigned &NumNames) const override {
1965     Names = GCCRegNames;
1966     NumNames = llvm::array_lengthof(GCCRegNames);
1967   }
1968   void getGCCRegAliases(const GCCRegAlias *&Aliases,
1969                         unsigned &NumAliases) const override {
1970     Aliases = nullptr;
1971     NumAliases = 0;
1972   }
1973   void getGCCAddlRegNames(const AddlRegName *&Names,
1974                           unsigned &NumNames) const override {
1975     Names = AddlRegNames;
1976     NumNames = llvm::array_lengthof(AddlRegNames);
1977   }
1978   bool validateAsmConstraint(const char *&Name,
1979                              TargetInfo::ConstraintInfo &info) const override;
1980 
1981   bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
1982 
1983   bool validateInputSize(StringRef Constraint, unsigned Size) const override;
1984 
1985   virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
1986 
1987   std::string convertConstraint(const char *&Constraint) const override;
1988   const char *getClobbers() const override {
1989     return "~{dirflag},~{fpsr},~{flags}";
1990   }
1991   void getTargetDefines(const LangOptions &Opts,
1992                         MacroBuilder &Builder) const override;
1993   static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
1994                           bool Enabled);
1995   static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
1996                           bool Enabled);
1997   static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
1998                           bool Enabled);
1999   void setFeatureEnabled(llvm::StringMap<bool> &Features,
2000                          StringRef Name, bool Enabled) const override {
2001     setFeatureEnabledImpl(Features, Name, Enabled);
2002   }
2003   // This exists purely to cut down on the number of virtual calls in
2004   // getDefaultFeatures which calls this repeatedly.
2005   static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2006                                     StringRef Name, bool Enabled);
2007   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
2008   bool hasFeature(StringRef Feature) const override;
2009   bool handleTargetFeatures(std::vector<std::string> &Features,
2010                             DiagnosticsEngine &Diags) override;
2011   StringRef getABI() const override {
2012     if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2013       return "avx";
2014     else if (getTriple().getArch() == llvm::Triple::x86 &&
2015              MMX3DNowLevel == NoMMX3DNow)
2016       return "no-mmx";
2017     return "";
2018   }
2019   bool setCPU(const std::string &Name) override {
2020     CPU = llvm::StringSwitch<CPUKind>(Name)
2021       .Case("i386", CK_i386)
2022       .Case("i486", CK_i486)
2023       .Case("winchip-c6", CK_WinChipC6)
2024       .Case("winchip2", CK_WinChip2)
2025       .Case("c3", CK_C3)
2026       .Case("i586", CK_i586)
2027       .Case("pentium", CK_Pentium)
2028       .Case("pentium-mmx", CK_PentiumMMX)
2029       .Case("i686", CK_i686)
2030       .Case("pentiumpro", CK_PentiumPro)
2031       .Case("pentium2", CK_Pentium2)
2032       .Case("pentium3", CK_Pentium3)
2033       .Case("pentium3m", CK_Pentium3M)
2034       .Case("pentium-m", CK_PentiumM)
2035       .Case("c3-2", CK_C3_2)
2036       .Case("yonah", CK_Yonah)
2037       .Case("pentium4", CK_Pentium4)
2038       .Case("pentium4m", CK_Pentium4M)
2039       .Case("prescott", CK_Prescott)
2040       .Case("nocona", CK_Nocona)
2041       .Case("core2", CK_Core2)
2042       .Case("penryn", CK_Penryn)
2043       .Case("bonnell", CK_Bonnell)
2044       .Case("atom", CK_Bonnell) // Legacy name.
2045       .Case("silvermont", CK_Silvermont)
2046       .Case("slm", CK_Silvermont) // Legacy name.
2047       .Case("nehalem", CK_Nehalem)
2048       .Case("corei7", CK_Nehalem) // Legacy name.
2049       .Case("westmere", CK_Westmere)
2050       .Case("sandybridge", CK_SandyBridge)
2051       .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2052       .Case("ivybridge", CK_IvyBridge)
2053       .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2054       .Case("haswell", CK_Haswell)
2055       .Case("core-avx2", CK_Haswell) // Legacy name.
2056       .Case("broadwell", CK_Broadwell)
2057       .Case("skylake", CK_Skylake)
2058       .Case("skx", CK_Skylake) // Legacy name.
2059       .Case("knl", CK_KNL)
2060       .Case("k6", CK_K6)
2061       .Case("k6-2", CK_K6_2)
2062       .Case("k6-3", CK_K6_3)
2063       .Case("athlon", CK_Athlon)
2064       .Case("athlon-tbird", CK_AthlonThunderbird)
2065       .Case("athlon-4", CK_Athlon4)
2066       .Case("athlon-xp", CK_AthlonXP)
2067       .Case("athlon-mp", CK_AthlonMP)
2068       .Case("athlon64", CK_Athlon64)
2069       .Case("athlon64-sse3", CK_Athlon64SSE3)
2070       .Case("athlon-fx", CK_AthlonFX)
2071       .Case("k8", CK_K8)
2072       .Case("k8-sse3", CK_K8SSE3)
2073       .Case("opteron", CK_Opteron)
2074       .Case("opteron-sse3", CK_OpteronSSE3)
2075       .Case("barcelona", CK_AMDFAM10)
2076       .Case("amdfam10", CK_AMDFAM10)
2077       .Case("btver1", CK_BTVER1)
2078       .Case("btver2", CK_BTVER2)
2079       .Case("bdver1", CK_BDVER1)
2080       .Case("bdver2", CK_BDVER2)
2081       .Case("bdver3", CK_BDVER3)
2082       .Case("bdver4", CK_BDVER4)
2083       .Case("x86-64", CK_x86_64)
2084       .Case("geode", CK_Geode)
2085       .Default(CK_Generic);
2086 
2087     // Perform any per-CPU checks necessary to determine if this CPU is
2088     // acceptable.
2089     // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2090     // invalid without explaining *why*.
2091     switch (CPU) {
2092     case CK_Generic:
2093       // No processor selected!
2094       return false;
2095 
2096     case CK_i386:
2097     case CK_i486:
2098     case CK_WinChipC6:
2099     case CK_WinChip2:
2100     case CK_C3:
2101     case CK_i586:
2102     case CK_Pentium:
2103     case CK_PentiumMMX:
2104     case CK_i686:
2105     case CK_PentiumPro:
2106     case CK_Pentium2:
2107     case CK_Pentium3:
2108     case CK_Pentium3M:
2109     case CK_PentiumM:
2110     case CK_Yonah:
2111     case CK_C3_2:
2112     case CK_Pentium4:
2113     case CK_Pentium4M:
2114     case CK_Prescott:
2115     case CK_K6:
2116     case CK_K6_2:
2117     case CK_K6_3:
2118     case CK_Athlon:
2119     case CK_AthlonThunderbird:
2120     case CK_Athlon4:
2121     case CK_AthlonXP:
2122     case CK_AthlonMP:
2123     case CK_Geode:
2124       // Only accept certain architectures when compiling in 32-bit mode.
2125       if (getTriple().getArch() != llvm::Triple::x86)
2126         return false;
2127 
2128       // Fallthrough
2129     case CK_Nocona:
2130     case CK_Core2:
2131     case CK_Penryn:
2132     case CK_Bonnell:
2133     case CK_Silvermont:
2134     case CK_Nehalem:
2135     case CK_Westmere:
2136     case CK_SandyBridge:
2137     case CK_IvyBridge:
2138     case CK_Haswell:
2139     case CK_Broadwell:
2140     case CK_Skylake:
2141     case CK_KNL:
2142     case CK_Athlon64:
2143     case CK_Athlon64SSE3:
2144     case CK_AthlonFX:
2145     case CK_K8:
2146     case CK_K8SSE3:
2147     case CK_Opteron:
2148     case CK_OpteronSSE3:
2149     case CK_AMDFAM10:
2150     case CK_BTVER1:
2151     case CK_BTVER2:
2152     case CK_BDVER1:
2153     case CK_BDVER2:
2154     case CK_BDVER3:
2155     case CK_BDVER4:
2156     case CK_x86_64:
2157       return true;
2158     }
2159     llvm_unreachable("Unhandled CPU kind");
2160   }
2161 
2162   bool setFPMath(StringRef Name) override;
2163 
2164   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2165     // We accept all non-ARM calling conventions
2166     return (CC == CC_X86ThisCall ||
2167             CC == CC_X86FastCall ||
2168             CC == CC_X86StdCall ||
2169             CC == CC_X86VectorCall ||
2170             CC == CC_C ||
2171             CC == CC_X86Pascal ||
2172             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2173   }
2174 
2175   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2176     return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2177   }
2178 };
2179 
2180 bool X86TargetInfo::setFPMath(StringRef Name) {
2181   if (Name == "387") {
2182     FPMath = FP_387;
2183     return true;
2184   }
2185   if (Name == "sse") {
2186     FPMath = FP_SSE;
2187     return true;
2188   }
2189   return false;
2190 }
2191 
2192 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2193   // FIXME: This *really* should not be here.
2194 
2195   // X86_64 always has SSE2.
2196   if (getTriple().getArch() == llvm::Triple::x86_64)
2197     setFeatureEnabledImpl(Features, "sse2", true);
2198 
2199   switch (CPU) {
2200   case CK_Generic:
2201   case CK_i386:
2202   case CK_i486:
2203   case CK_i586:
2204   case CK_Pentium:
2205   case CK_i686:
2206   case CK_PentiumPro:
2207     break;
2208   case CK_PentiumMMX:
2209   case CK_Pentium2:
2210   case CK_K6:
2211   case CK_WinChipC6:
2212     setFeatureEnabledImpl(Features, "mmx", true);
2213     break;
2214   case CK_Pentium3:
2215   case CK_Pentium3M:
2216   case CK_C3_2:
2217     setFeatureEnabledImpl(Features, "sse", true);
2218     break;
2219   case CK_PentiumM:
2220   case CK_Pentium4:
2221   case CK_Pentium4M:
2222   case CK_x86_64:
2223     setFeatureEnabledImpl(Features, "sse2", true);
2224     break;
2225   case CK_Yonah:
2226   case CK_Prescott:
2227   case CK_Nocona:
2228     setFeatureEnabledImpl(Features, "sse3", true);
2229     setFeatureEnabledImpl(Features, "cx16", true);
2230     break;
2231   case CK_Core2:
2232   case CK_Bonnell:
2233     setFeatureEnabledImpl(Features, "ssse3", true);
2234     setFeatureEnabledImpl(Features, "cx16", true);
2235     break;
2236   case CK_Penryn:
2237     setFeatureEnabledImpl(Features, "sse4.1", true);
2238     setFeatureEnabledImpl(Features, "cx16", true);
2239     break;
2240   case CK_Skylake:
2241     setFeatureEnabledImpl(Features, "avx512f", true);
2242     setFeatureEnabledImpl(Features, "avx512cd", true);
2243     setFeatureEnabledImpl(Features, "avx512dq", true);
2244     setFeatureEnabledImpl(Features, "avx512bw", true);
2245     setFeatureEnabledImpl(Features, "avx512vl", true);
2246     // FALLTHROUGH
2247   case CK_Broadwell:
2248     setFeatureEnabledImpl(Features, "rdseed", true);
2249     setFeatureEnabledImpl(Features, "adx", true);
2250     // FALLTHROUGH
2251   case CK_Haswell:
2252     setFeatureEnabledImpl(Features, "avx2", true);
2253     setFeatureEnabledImpl(Features, "lzcnt", true);
2254     setFeatureEnabledImpl(Features, "bmi", true);
2255     setFeatureEnabledImpl(Features, "bmi2", true);
2256     setFeatureEnabledImpl(Features, "rtm", true);
2257     setFeatureEnabledImpl(Features, "fma", true);
2258     // FALLTHROUGH
2259   case CK_IvyBridge:
2260     setFeatureEnabledImpl(Features, "rdrnd", true);
2261     setFeatureEnabledImpl(Features, "f16c", true);
2262     setFeatureEnabledImpl(Features, "fsgsbase", true);
2263     // FALLTHROUGH
2264   case CK_SandyBridge:
2265     setFeatureEnabledImpl(Features, "avx", true);
2266     // FALLTHROUGH
2267   case CK_Westmere:
2268   case CK_Silvermont:
2269     setFeatureEnabledImpl(Features, "aes", true);
2270     setFeatureEnabledImpl(Features, "pclmul", true);
2271     // FALLTHROUGH
2272   case CK_Nehalem:
2273     setFeatureEnabledImpl(Features, "sse4.2", true);
2274     setFeatureEnabledImpl(Features, "cx16", true);
2275     break;
2276   case CK_KNL:
2277     setFeatureEnabledImpl(Features, "avx512f", true);
2278     setFeatureEnabledImpl(Features, "avx512cd", true);
2279     setFeatureEnabledImpl(Features, "avx512er", true);
2280     setFeatureEnabledImpl(Features, "avx512pf", true);
2281     setFeatureEnabledImpl(Features, "rdseed", true);
2282     setFeatureEnabledImpl(Features, "adx", true);
2283     setFeatureEnabledImpl(Features, "lzcnt", true);
2284     setFeatureEnabledImpl(Features, "bmi", true);
2285     setFeatureEnabledImpl(Features, "bmi2", true);
2286     setFeatureEnabledImpl(Features, "rtm", true);
2287     setFeatureEnabledImpl(Features, "fma", true);
2288     setFeatureEnabledImpl(Features, "rdrnd", true);
2289     setFeatureEnabledImpl(Features, "f16c", true);
2290     setFeatureEnabledImpl(Features, "fsgsbase", true);
2291     setFeatureEnabledImpl(Features, "aes", true);
2292     setFeatureEnabledImpl(Features, "pclmul", true);
2293     setFeatureEnabledImpl(Features, "cx16", true);
2294     break;
2295   case CK_K6_2:
2296   case CK_K6_3:
2297   case CK_WinChip2:
2298   case CK_C3:
2299     setFeatureEnabledImpl(Features, "3dnow", true);
2300     break;
2301   case CK_Athlon:
2302   case CK_AthlonThunderbird:
2303   case CK_Geode:
2304     setFeatureEnabledImpl(Features, "3dnowa", true);
2305     break;
2306   case CK_Athlon4:
2307   case CK_AthlonXP:
2308   case CK_AthlonMP:
2309     setFeatureEnabledImpl(Features, "sse", true);
2310     setFeatureEnabledImpl(Features, "3dnowa", true);
2311     break;
2312   case CK_K8:
2313   case CK_Opteron:
2314   case CK_Athlon64:
2315   case CK_AthlonFX:
2316     setFeatureEnabledImpl(Features, "sse2", true);
2317     setFeatureEnabledImpl(Features, "3dnowa", true);
2318     break;
2319   case CK_AMDFAM10:
2320     setFeatureEnabledImpl(Features, "sse4a", true);
2321     setFeatureEnabledImpl(Features, "lzcnt", true);
2322     setFeatureEnabledImpl(Features, "popcnt", true);
2323     // FALLTHROUGH
2324   case CK_K8SSE3:
2325   case CK_OpteronSSE3:
2326   case CK_Athlon64SSE3:
2327     setFeatureEnabledImpl(Features, "sse3", true);
2328     setFeatureEnabledImpl(Features, "3dnowa", true);
2329     break;
2330   case CK_BTVER2:
2331     setFeatureEnabledImpl(Features, "avx", true);
2332     setFeatureEnabledImpl(Features, "aes", true);
2333     setFeatureEnabledImpl(Features, "pclmul", true);
2334     setFeatureEnabledImpl(Features, "bmi", true);
2335     setFeatureEnabledImpl(Features, "f16c", true);
2336     // FALLTHROUGH
2337   case CK_BTVER1:
2338     setFeatureEnabledImpl(Features, "ssse3", true);
2339     setFeatureEnabledImpl(Features, "sse4a", true);
2340     setFeatureEnabledImpl(Features, "lzcnt", true);
2341     setFeatureEnabledImpl(Features, "popcnt", true);
2342     setFeatureEnabledImpl(Features, "prfchw", true);
2343     setFeatureEnabledImpl(Features, "cx16", true);
2344     break;
2345   case CK_BDVER4:
2346     setFeatureEnabledImpl(Features, "avx2", true);
2347     setFeatureEnabledImpl(Features, "bmi2", true);
2348     // FALLTHROUGH
2349   case CK_BDVER3:
2350     setFeatureEnabledImpl(Features, "fsgsbase", true);
2351     // FALLTHROUGH
2352   case CK_BDVER2:
2353     setFeatureEnabledImpl(Features, "bmi", true);
2354     setFeatureEnabledImpl(Features, "fma", true);
2355     setFeatureEnabledImpl(Features, "f16c", true);
2356     setFeatureEnabledImpl(Features, "tbm", true);
2357     // FALLTHROUGH
2358   case CK_BDVER1:
2359     // xop implies avx, sse4a and fma4.
2360     setFeatureEnabledImpl(Features, "xop", true);
2361     setFeatureEnabledImpl(Features, "lzcnt", true);
2362     setFeatureEnabledImpl(Features, "aes", true);
2363     setFeatureEnabledImpl(Features, "pclmul", true);
2364     setFeatureEnabledImpl(Features, "prfchw", true);
2365     setFeatureEnabledImpl(Features, "cx16", true);
2366     break;
2367   }
2368 }
2369 
2370 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2371                                 X86SSEEnum Level, bool Enabled) {
2372   if (Enabled) {
2373     switch (Level) {
2374     case AVX512F:
2375       Features["avx512f"] = true;
2376     case AVX2:
2377       Features["avx2"] = true;
2378     case AVX:
2379       Features["avx"] = true;
2380     case SSE42:
2381       Features["sse4.2"] = true;
2382     case SSE41:
2383       Features["sse4.1"] = true;
2384     case SSSE3:
2385       Features["ssse3"] = true;
2386     case SSE3:
2387       Features["sse3"] = true;
2388     case SSE2:
2389       Features["sse2"] = true;
2390     case SSE1:
2391       Features["sse"] = true;
2392     case NoSSE:
2393       break;
2394     }
2395     return;
2396   }
2397 
2398   switch (Level) {
2399   case NoSSE:
2400   case SSE1:
2401     Features["sse"] = false;
2402   case SSE2:
2403     Features["sse2"] = Features["pclmul"] = Features["aes"] =
2404       Features["sha"] = false;
2405   case SSE3:
2406     Features["sse3"] = false;
2407     setXOPLevel(Features, NoXOP, false);
2408   case SSSE3:
2409     Features["ssse3"] = false;
2410   case SSE41:
2411     Features["sse4.1"] = false;
2412   case SSE42:
2413     Features["sse4.2"] = false;
2414   case AVX:
2415     Features["fma"] = Features["avx"] = Features["f16c"] = false;
2416     setXOPLevel(Features, FMA4, false);
2417   case AVX2:
2418     Features["avx2"] = false;
2419   case AVX512F:
2420     Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2421         Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2422             Features["avx512vl"] = false;
2423   }
2424 }
2425 
2426 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2427                                 MMX3DNowEnum Level, bool Enabled) {
2428   if (Enabled) {
2429     switch (Level) {
2430     case AMD3DNowAthlon:
2431       Features["3dnowa"] = true;
2432     case AMD3DNow:
2433       Features["3dnow"] = true;
2434     case MMX:
2435       Features["mmx"] = true;
2436     case NoMMX3DNow:
2437       break;
2438     }
2439     return;
2440   }
2441 
2442   switch (Level) {
2443   case NoMMX3DNow:
2444   case MMX:
2445     Features["mmx"] = false;
2446   case AMD3DNow:
2447     Features["3dnow"] = false;
2448   case AMD3DNowAthlon:
2449     Features["3dnowa"] = false;
2450   }
2451 }
2452 
2453 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2454                                 bool Enabled) {
2455   if (Enabled) {
2456     switch (Level) {
2457     case XOP:
2458       Features["xop"] = true;
2459     case FMA4:
2460       Features["fma4"] = true;
2461       setSSELevel(Features, AVX, true);
2462     case SSE4A:
2463       Features["sse4a"] = true;
2464       setSSELevel(Features, SSE3, true);
2465     case NoXOP:
2466       break;
2467     }
2468     return;
2469   }
2470 
2471   switch (Level) {
2472   case NoXOP:
2473   case SSE4A:
2474     Features["sse4a"] = false;
2475   case FMA4:
2476     Features["fma4"] = false;
2477   case XOP:
2478     Features["xop"] = false;
2479   }
2480 }
2481 
2482 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2483                                           StringRef Name, bool Enabled) {
2484   // FIXME: This *really* should not be here.  We need some way of translating
2485   // options into llvm subtarget features.
2486   if (Name == "sse4")
2487     Name = "sse4.2";
2488 
2489   Features[Name] = Enabled;
2490 
2491   if (Name == "mmx") {
2492     setMMXLevel(Features, MMX, Enabled);
2493   } else if (Name == "sse") {
2494     setSSELevel(Features, SSE1, Enabled);
2495   } else if (Name == "sse2") {
2496     setSSELevel(Features, SSE2, Enabled);
2497   } else if (Name == "sse3") {
2498     setSSELevel(Features, SSE3, Enabled);
2499   } else if (Name == "ssse3") {
2500     setSSELevel(Features, SSSE3, Enabled);
2501   } else if (Name == "sse4.2") {
2502     setSSELevel(Features, SSE42, Enabled);
2503   } else if (Name == "sse4.1") {
2504     setSSELevel(Features, SSE41, Enabled);
2505   } else if (Name == "3dnow") {
2506     setMMXLevel(Features, AMD3DNow, Enabled);
2507   } else if (Name == "3dnowa") {
2508     setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2509   } else if (Name == "aes") {
2510     if (Enabled)
2511       setSSELevel(Features, SSE2, Enabled);
2512   } else if (Name == "pclmul") {
2513     if (Enabled)
2514       setSSELevel(Features, SSE2, Enabled);
2515   } else if (Name == "avx") {
2516     setSSELevel(Features, AVX, Enabled);
2517   } else if (Name == "avx2") {
2518     setSSELevel(Features, AVX2, Enabled);
2519   } else if (Name == "avx512f") {
2520     setSSELevel(Features, AVX512F, Enabled);
2521   } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2522           || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2523     if (Enabled)
2524       setSSELevel(Features, AVX512F, Enabled);
2525   } else if (Name == "fma") {
2526     if (Enabled)
2527       setSSELevel(Features, AVX, Enabled);
2528   } else if (Name == "fma4") {
2529     setXOPLevel(Features, FMA4, Enabled);
2530   } else if (Name == "xop") {
2531     setXOPLevel(Features, XOP, Enabled);
2532   } else if (Name == "sse4a") {
2533     setXOPLevel(Features, SSE4A, Enabled);
2534   } else if (Name == "f16c") {
2535     if (Enabled)
2536       setSSELevel(Features, AVX, Enabled);
2537   } else if (Name == "sha") {
2538     if (Enabled)
2539       setSSELevel(Features, SSE2, Enabled);
2540   }
2541 }
2542 
2543 /// handleTargetFeatures - Perform initialization based on the user
2544 /// configured set of features.
2545 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2546                                          DiagnosticsEngine &Diags) {
2547   // Remember the maximum enabled sselevel.
2548   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2549     // Ignore disabled features.
2550     if (Features[i][0] == '-')
2551       continue;
2552 
2553     StringRef Feature = StringRef(Features[i]).substr(1);
2554 
2555     if (Feature == "aes") {
2556       HasAES = true;
2557       continue;
2558     }
2559 
2560     if (Feature == "pclmul") {
2561       HasPCLMUL = true;
2562       continue;
2563     }
2564 
2565     if (Feature == "lzcnt") {
2566       HasLZCNT = true;
2567       continue;
2568     }
2569 
2570     if (Feature == "rdrnd") {
2571       HasRDRND = true;
2572       continue;
2573     }
2574 
2575     if (Feature == "fsgsbase") {
2576       HasFSGSBASE = true;
2577       continue;
2578     }
2579 
2580     if (Feature == "bmi") {
2581       HasBMI = true;
2582       continue;
2583     }
2584 
2585     if (Feature == "bmi2") {
2586       HasBMI2 = true;
2587       continue;
2588     }
2589 
2590     if (Feature == "popcnt") {
2591       HasPOPCNT = true;
2592       continue;
2593     }
2594 
2595     if (Feature == "rtm") {
2596       HasRTM = true;
2597       continue;
2598     }
2599 
2600     if (Feature == "prfchw") {
2601       HasPRFCHW = true;
2602       continue;
2603     }
2604 
2605     if (Feature == "rdseed") {
2606       HasRDSEED = true;
2607       continue;
2608     }
2609 
2610     if (Feature == "adx") {
2611       HasADX = true;
2612       continue;
2613     }
2614 
2615     if (Feature == "tbm") {
2616       HasTBM = true;
2617       continue;
2618     }
2619 
2620     if (Feature == "fma") {
2621       HasFMA = true;
2622       continue;
2623     }
2624 
2625     if (Feature == "f16c") {
2626       HasF16C = true;
2627       continue;
2628     }
2629 
2630     if (Feature == "avx512cd") {
2631       HasAVX512CD = true;
2632       continue;
2633     }
2634 
2635     if (Feature == "avx512er") {
2636       HasAVX512ER = true;
2637       continue;
2638     }
2639 
2640     if (Feature == "avx512pf") {
2641       HasAVX512PF = true;
2642       continue;
2643     }
2644 
2645     if (Feature == "avx512dq") {
2646       HasAVX512DQ = true;
2647       continue;
2648     }
2649 
2650     if (Feature == "avx512bw") {
2651       HasAVX512BW = true;
2652       continue;
2653     }
2654 
2655     if (Feature == "avx512vl") {
2656       HasAVX512VL = true;
2657       continue;
2658     }
2659 
2660     if (Feature == "sha") {
2661       HasSHA = true;
2662       continue;
2663     }
2664 
2665     if (Feature == "cx16") {
2666       HasCX16 = true;
2667       continue;
2668     }
2669 
2670     assert(Features[i][0] == '+' && "Invalid target feature!");
2671     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2672       .Case("avx512f", AVX512F)
2673       .Case("avx2", AVX2)
2674       .Case("avx", AVX)
2675       .Case("sse4.2", SSE42)
2676       .Case("sse4.1", SSE41)
2677       .Case("ssse3", SSSE3)
2678       .Case("sse3", SSE3)
2679       .Case("sse2", SSE2)
2680       .Case("sse", SSE1)
2681       .Default(NoSSE);
2682     SSELevel = std::max(SSELevel, Level);
2683 
2684     MMX3DNowEnum ThreeDNowLevel =
2685       llvm::StringSwitch<MMX3DNowEnum>(Feature)
2686         .Case("3dnowa", AMD3DNowAthlon)
2687         .Case("3dnow", AMD3DNow)
2688         .Case("mmx", MMX)
2689         .Default(NoMMX3DNow);
2690     MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2691 
2692     XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2693         .Case("xop", XOP)
2694         .Case("fma4", FMA4)
2695         .Case("sse4a", SSE4A)
2696         .Default(NoXOP);
2697     XOPLevel = std::max(XOPLevel, XLevel);
2698   }
2699 
2700   // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2701   // Can't do this earlier because we need to be able to explicitly enable
2702   // popcnt and still disable sse4.2.
2703   if (!HasPOPCNT && SSELevel >= SSE42 &&
2704       std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2705     HasPOPCNT = true;
2706     Features.push_back("+popcnt");
2707   }
2708 
2709   // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2710   if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2711       std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2712     HasPRFCHW = true;
2713     Features.push_back("+prfchw");
2714   }
2715 
2716   // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2717   // matches the selected sse level.
2718   if (FPMath == FP_SSE && SSELevel < SSE1) {
2719     Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2720     return false;
2721   } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2722     Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2723     return false;
2724   }
2725 
2726   // Don't tell the backend if we're turning off mmx; it will end up disabling
2727   // SSE, which we don't want.
2728   // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2729   // then enable MMX.
2730   std::vector<std::string>::iterator it;
2731   it = std::find(Features.begin(), Features.end(), "-mmx");
2732   if (it != Features.end())
2733     Features.erase(it);
2734   else if (SSELevel > NoSSE)
2735     MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2736   return true;
2737 }
2738 
2739 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2740 /// definitions for this particular subtarget.
2741 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2742                                      MacroBuilder &Builder) const {
2743   // Target identification.
2744   if (getTriple().getArch() == llvm::Triple::x86_64) {
2745     Builder.defineMacro("__amd64__");
2746     Builder.defineMacro("__amd64");
2747     Builder.defineMacro("__x86_64");
2748     Builder.defineMacro("__x86_64__");
2749     if (getTriple().getArchName() == "x86_64h") {
2750       Builder.defineMacro("__x86_64h");
2751       Builder.defineMacro("__x86_64h__");
2752     }
2753   } else {
2754     DefineStd(Builder, "i386", Opts);
2755   }
2756 
2757   // Subtarget options.
2758   // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2759   // truly should be based on -mtune options.
2760   switch (CPU) {
2761   case CK_Generic:
2762     break;
2763   case CK_i386:
2764     // The rest are coming from the i386 define above.
2765     Builder.defineMacro("__tune_i386__");
2766     break;
2767   case CK_i486:
2768   case CK_WinChipC6:
2769   case CK_WinChip2:
2770   case CK_C3:
2771     defineCPUMacros(Builder, "i486");
2772     break;
2773   case CK_PentiumMMX:
2774     Builder.defineMacro("__pentium_mmx__");
2775     Builder.defineMacro("__tune_pentium_mmx__");
2776     // Fallthrough
2777   case CK_i586:
2778   case CK_Pentium:
2779     defineCPUMacros(Builder, "i586");
2780     defineCPUMacros(Builder, "pentium");
2781     break;
2782   case CK_Pentium3:
2783   case CK_Pentium3M:
2784   case CK_PentiumM:
2785     Builder.defineMacro("__tune_pentium3__");
2786     // Fallthrough
2787   case CK_Pentium2:
2788   case CK_C3_2:
2789     Builder.defineMacro("__tune_pentium2__");
2790     // Fallthrough
2791   case CK_PentiumPro:
2792     Builder.defineMacro("__tune_i686__");
2793     Builder.defineMacro("__tune_pentiumpro__");
2794     // Fallthrough
2795   case CK_i686:
2796     Builder.defineMacro("__i686");
2797     Builder.defineMacro("__i686__");
2798     // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2799     Builder.defineMacro("__pentiumpro");
2800     Builder.defineMacro("__pentiumpro__");
2801     break;
2802   case CK_Pentium4:
2803   case CK_Pentium4M:
2804     defineCPUMacros(Builder, "pentium4");
2805     break;
2806   case CK_Yonah:
2807   case CK_Prescott:
2808   case CK_Nocona:
2809     defineCPUMacros(Builder, "nocona");
2810     break;
2811   case CK_Core2:
2812   case CK_Penryn:
2813     defineCPUMacros(Builder, "core2");
2814     break;
2815   case CK_Bonnell:
2816     defineCPUMacros(Builder, "atom");
2817     break;
2818   case CK_Silvermont:
2819     defineCPUMacros(Builder, "slm");
2820     break;
2821   case CK_Nehalem:
2822   case CK_Westmere:
2823   case CK_SandyBridge:
2824   case CK_IvyBridge:
2825   case CK_Haswell:
2826   case CK_Broadwell:
2827     // FIXME: Historically, we defined this legacy name, it would be nice to
2828     // remove it at some point. We've never exposed fine-grained names for
2829     // recent primary x86 CPUs, and we should keep it that way.
2830     defineCPUMacros(Builder, "corei7");
2831     break;
2832   case CK_Skylake:
2833     // FIXME: Historically, we defined this legacy name, it would be nice to
2834     // remove it at some point. This is the only fine-grained CPU macro in the
2835     // main intel CPU line, and it would be better to not have these and force
2836     // people to use ISA macros.
2837     defineCPUMacros(Builder, "skx");
2838     break;
2839   case CK_KNL:
2840     defineCPUMacros(Builder, "knl");
2841     break;
2842   case CK_K6_2:
2843     Builder.defineMacro("__k6_2__");
2844     Builder.defineMacro("__tune_k6_2__");
2845     // Fallthrough
2846   case CK_K6_3:
2847     if (CPU != CK_K6_2) {  // In case of fallthrough
2848       // FIXME: GCC may be enabling these in cases where some other k6
2849       // architecture is specified but -m3dnow is explicitly provided. The
2850       // exact semantics need to be determined and emulated here.
2851       Builder.defineMacro("__k6_3__");
2852       Builder.defineMacro("__tune_k6_3__");
2853     }
2854     // Fallthrough
2855   case CK_K6:
2856     defineCPUMacros(Builder, "k6");
2857     break;
2858   case CK_Athlon:
2859   case CK_AthlonThunderbird:
2860   case CK_Athlon4:
2861   case CK_AthlonXP:
2862   case CK_AthlonMP:
2863     defineCPUMacros(Builder, "athlon");
2864     if (SSELevel != NoSSE) {
2865       Builder.defineMacro("__athlon_sse__");
2866       Builder.defineMacro("__tune_athlon_sse__");
2867     }
2868     break;
2869   case CK_K8:
2870   case CK_K8SSE3:
2871   case CK_x86_64:
2872   case CK_Opteron:
2873   case CK_OpteronSSE3:
2874   case CK_Athlon64:
2875   case CK_Athlon64SSE3:
2876   case CK_AthlonFX:
2877     defineCPUMacros(Builder, "k8");
2878     break;
2879   case CK_AMDFAM10:
2880     defineCPUMacros(Builder, "amdfam10");
2881     break;
2882   case CK_BTVER1:
2883     defineCPUMacros(Builder, "btver1");
2884     break;
2885   case CK_BTVER2:
2886     defineCPUMacros(Builder, "btver2");
2887     break;
2888   case CK_BDVER1:
2889     defineCPUMacros(Builder, "bdver1");
2890     break;
2891   case CK_BDVER2:
2892     defineCPUMacros(Builder, "bdver2");
2893     break;
2894   case CK_BDVER3:
2895     defineCPUMacros(Builder, "bdver3");
2896     break;
2897   case CK_BDVER4:
2898     defineCPUMacros(Builder, "bdver4");
2899     break;
2900   case CK_Geode:
2901     defineCPUMacros(Builder, "geode");
2902     break;
2903   }
2904 
2905   // Target properties.
2906   Builder.defineMacro("__REGISTER_PREFIX__", "");
2907 
2908   // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2909   // functions in glibc header files that use FP Stack inline asm which the
2910   // backend can't deal with (PR879).
2911   Builder.defineMacro("__NO_MATH_INLINES");
2912 
2913   if (HasAES)
2914     Builder.defineMacro("__AES__");
2915 
2916   if (HasPCLMUL)
2917     Builder.defineMacro("__PCLMUL__");
2918 
2919   if (HasLZCNT)
2920     Builder.defineMacro("__LZCNT__");
2921 
2922   if (HasRDRND)
2923     Builder.defineMacro("__RDRND__");
2924 
2925   if (HasFSGSBASE)
2926     Builder.defineMacro("__FSGSBASE__");
2927 
2928   if (HasBMI)
2929     Builder.defineMacro("__BMI__");
2930 
2931   if (HasBMI2)
2932     Builder.defineMacro("__BMI2__");
2933 
2934   if (HasPOPCNT)
2935     Builder.defineMacro("__POPCNT__");
2936 
2937   if (HasRTM)
2938     Builder.defineMacro("__RTM__");
2939 
2940   if (HasPRFCHW)
2941     Builder.defineMacro("__PRFCHW__");
2942 
2943   if (HasRDSEED)
2944     Builder.defineMacro("__RDSEED__");
2945 
2946   if (HasADX)
2947     Builder.defineMacro("__ADX__");
2948 
2949   if (HasTBM)
2950     Builder.defineMacro("__TBM__");
2951 
2952   switch (XOPLevel) {
2953   case XOP:
2954     Builder.defineMacro("__XOP__");
2955   case FMA4:
2956     Builder.defineMacro("__FMA4__");
2957   case SSE4A:
2958     Builder.defineMacro("__SSE4A__");
2959   case NoXOP:
2960     break;
2961   }
2962 
2963   if (HasFMA)
2964     Builder.defineMacro("__FMA__");
2965 
2966   if (HasF16C)
2967     Builder.defineMacro("__F16C__");
2968 
2969   if (HasAVX512CD)
2970     Builder.defineMacro("__AVX512CD__");
2971   if (HasAVX512ER)
2972     Builder.defineMacro("__AVX512ER__");
2973   if (HasAVX512PF)
2974     Builder.defineMacro("__AVX512PF__");
2975   if (HasAVX512DQ)
2976     Builder.defineMacro("__AVX512DQ__");
2977   if (HasAVX512BW)
2978     Builder.defineMacro("__AVX512BW__");
2979   if (HasAVX512VL)
2980     Builder.defineMacro("__AVX512VL__");
2981 
2982   if (HasSHA)
2983     Builder.defineMacro("__SHA__");
2984 
2985   if (HasCX16)
2986     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
2987 
2988   // Each case falls through to the previous one here.
2989   switch (SSELevel) {
2990   case AVX512F:
2991     Builder.defineMacro("__AVX512F__");
2992   case AVX2:
2993     Builder.defineMacro("__AVX2__");
2994   case AVX:
2995     Builder.defineMacro("__AVX__");
2996   case SSE42:
2997     Builder.defineMacro("__SSE4_2__");
2998   case SSE41:
2999     Builder.defineMacro("__SSE4_1__");
3000   case SSSE3:
3001     Builder.defineMacro("__SSSE3__");
3002   case SSE3:
3003     Builder.defineMacro("__SSE3__");
3004   case SSE2:
3005     Builder.defineMacro("__SSE2__");
3006     Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
3007   case SSE1:
3008     Builder.defineMacro("__SSE__");
3009     Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
3010   case NoSSE:
3011     break;
3012   }
3013 
3014   if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3015     switch (SSELevel) {
3016     case AVX512F:
3017     case AVX2:
3018     case AVX:
3019     case SSE42:
3020     case SSE41:
3021     case SSSE3:
3022     case SSE3:
3023     case SSE2:
3024       Builder.defineMacro("_M_IX86_FP", Twine(2));
3025       break;
3026     case SSE1:
3027       Builder.defineMacro("_M_IX86_FP", Twine(1));
3028       break;
3029     default:
3030       Builder.defineMacro("_M_IX86_FP", Twine(0));
3031     }
3032   }
3033 
3034   // Each case falls through to the previous one here.
3035   switch (MMX3DNowLevel) {
3036   case AMD3DNowAthlon:
3037     Builder.defineMacro("__3dNOW_A__");
3038   case AMD3DNow:
3039     Builder.defineMacro("__3dNOW__");
3040   case MMX:
3041     Builder.defineMacro("__MMX__");
3042   case NoMMX3DNow:
3043     break;
3044   }
3045 
3046   if (CPU >= CK_i486) {
3047     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3048     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3049     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3050   }
3051   if (CPU >= CK_i586)
3052     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3053 }
3054 
3055 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3056   return llvm::StringSwitch<bool>(Feature)
3057       .Case("aes", HasAES)
3058       .Case("avx", SSELevel >= AVX)
3059       .Case("avx2", SSELevel >= AVX2)
3060       .Case("avx512f", SSELevel >= AVX512F)
3061       .Case("avx512cd", HasAVX512CD)
3062       .Case("avx512er", HasAVX512ER)
3063       .Case("avx512pf", HasAVX512PF)
3064       .Case("avx512dq", HasAVX512DQ)
3065       .Case("avx512bw", HasAVX512BW)
3066       .Case("avx512vl", HasAVX512VL)
3067       .Case("bmi", HasBMI)
3068       .Case("bmi2", HasBMI2)
3069       .Case("cx16", HasCX16)
3070       .Case("f16c", HasF16C)
3071       .Case("fma", HasFMA)
3072       .Case("fma4", XOPLevel >= FMA4)
3073       .Case("fsgsbase", HasFSGSBASE)
3074       .Case("lzcnt", HasLZCNT)
3075       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3076       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3077       .Case("mmx", MMX3DNowLevel >= MMX)
3078       .Case("pclmul", HasPCLMUL)
3079       .Case("popcnt", HasPOPCNT)
3080       .Case("prfchw", HasPRFCHW)
3081       .Case("rdrnd", HasRDRND)
3082       .Case("rdseed", HasRDSEED)
3083       .Case("rtm", HasRTM)
3084       .Case("sha", HasSHA)
3085       .Case("sse", SSELevel >= SSE1)
3086       .Case("sse2", SSELevel >= SSE2)
3087       .Case("sse3", SSELevel >= SSE3)
3088       .Case("ssse3", SSELevel >= SSSE3)
3089       .Case("sse4.1", SSELevel >= SSE41)
3090       .Case("sse4.2", SSELevel >= SSE42)
3091       .Case("sse4a", XOPLevel >= SSE4A)
3092       .Case("tbm", HasTBM)
3093       .Case("x86", true)
3094       .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3095       .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3096       .Case("xop", XOPLevel >= XOP)
3097       .Default(false);
3098 }
3099 
3100 bool
3101 X86TargetInfo::validateAsmConstraint(const char *&Name,
3102                                      TargetInfo::ConstraintInfo &Info) const {
3103   switch (*Name) {
3104   default: return false;
3105   case 'Y': // first letter of a pair:
3106     switch (*(Name+1)) {
3107     default: return false;
3108     case '0':  // First SSE register.
3109     case 't':  // Any SSE register, when SSE2 is enabled.
3110     case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
3111     case 'm':  // any MMX register, when inter-unit moves enabled.
3112       break;   // falls through to setAllowsRegister.
3113   }
3114   case 'f': // any x87 floating point stack register.
3115     // Constraint 'f' cannot be used for output operands.
3116     if (Info.ConstraintStr[0] == '=')
3117       return false;
3118 
3119     Info.setAllowsRegister();
3120     return true;
3121   case 'a': // eax.
3122   case 'b': // ebx.
3123   case 'c': // ecx.
3124   case 'd': // edx.
3125   case 'S': // esi.
3126   case 'D': // edi.
3127   case 'A': // edx:eax.
3128   case 't': // top of floating point stack.
3129   case 'u': // second from top of floating point stack.
3130   case 'q': // Any register accessible as [r]l: a, b, c, and d.
3131   case 'y': // Any MMX register.
3132   case 'x': // Any SSE register.
3133   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3134   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3135   case 'l': // "Index" registers: any general register that can be used as an
3136             // index in a base+index memory access.
3137     Info.setAllowsRegister();
3138     return true;
3139   case 'C': // SSE floating point constant.
3140   case 'G': // x87 floating point constant.
3141   case 'e': // 32-bit signed integer constant for use with zero-extending
3142             // x86_64 instructions.
3143   case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3144             // x86_64 instructions.
3145     return true;
3146   }
3147 }
3148 
3149 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3150                                        unsigned Size) const {
3151   // Strip off constraint modifiers.
3152   while (Constraint[0] == '=' ||
3153          Constraint[0] == '+' ||
3154          Constraint[0] == '&')
3155     Constraint = Constraint.substr(1);
3156 
3157   return validateOperandSize(Constraint, Size);
3158 }
3159 
3160 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3161                                       unsigned Size) const {
3162   return validateOperandSize(Constraint, Size);
3163 }
3164 
3165 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3166                                         unsigned Size) const {
3167   switch (Constraint[0]) {
3168   default: break;
3169   case 'y':
3170     return Size <= 64;
3171   case 'f':
3172   case 't':
3173   case 'u':
3174     return Size <= 128;
3175   case 'x':
3176     // 256-bit ymm registers can be used if target supports AVX.
3177     return Size <= (SSELevel >= AVX ? 256U : 128U);
3178   }
3179 
3180   return true;
3181 }
3182 
3183 std::string
3184 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3185   switch (*Constraint) {
3186   case 'a': return std::string("{ax}");
3187   case 'b': return std::string("{bx}");
3188   case 'c': return std::string("{cx}");
3189   case 'd': return std::string("{dx}");
3190   case 'S': return std::string("{si}");
3191   case 'D': return std::string("{di}");
3192   case 'p': // address
3193     return std::string("im");
3194   case 't': // top of floating point stack.
3195     return std::string("{st}");
3196   case 'u': // second from top of floating point stack.
3197     return std::string("{st(1)}"); // second from top of floating point stack.
3198   default:
3199     return std::string(1, *Constraint);
3200   }
3201 }
3202 } // end anonymous namespace
3203 
3204 namespace {
3205 // X86-32 generic target
3206 class X86_32TargetInfo : public X86TargetInfo {
3207 public:
3208   X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3209     DoubleAlign = LongLongAlign = 32;
3210     LongDoubleWidth = 96;
3211     LongDoubleAlign = 32;
3212     SuitableAlign = 128;
3213     DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3214     SizeType = UnsignedInt;
3215     PtrDiffType = SignedInt;
3216     IntPtrType = SignedInt;
3217     RegParmMax = 3;
3218 
3219     // Use fpret for all types.
3220     RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3221                              (1 << TargetInfo::Double) |
3222                              (1 << TargetInfo::LongDouble));
3223 
3224     // x86-32 has atomics up to 8 bytes
3225     // FIXME: Check that we actually have cmpxchg8b before setting
3226     // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3227     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3228   }
3229   BuiltinVaListKind getBuiltinVaListKind() const override {
3230     return TargetInfo::CharPtrBuiltinVaList;
3231   }
3232 
3233   int getEHDataRegisterNumber(unsigned RegNo) const override {
3234     if (RegNo == 0) return 0;
3235     if (RegNo == 1) return 2;
3236     return -1;
3237   }
3238   bool validateOperandSize(StringRef Constraint,
3239                            unsigned Size) const override {
3240     switch (Constraint[0]) {
3241     default: break;
3242     case 'R':
3243     case 'q':
3244     case 'Q':
3245     case 'a':
3246     case 'b':
3247     case 'c':
3248     case 'd':
3249     case 'S':
3250     case 'D':
3251       return Size <= 32;
3252     case 'A':
3253       return Size <= 64;
3254     }
3255 
3256     return X86TargetInfo::validateOperandSize(Constraint, Size);
3257   }
3258 };
3259 } // end anonymous namespace
3260 
3261 namespace {
3262 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3263 public:
3264   NetBSDI386TargetInfo(const llvm::Triple &Triple)
3265       : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3266 
3267   unsigned getFloatEvalMethod() const override {
3268     unsigned Major, Minor, Micro;
3269     getTriple().getOSVersion(Major, Minor, Micro);
3270     // New NetBSD uses the default rounding mode.
3271     if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3272       return X86_32TargetInfo::getFloatEvalMethod();
3273     // NetBSD before 6.99.26 defaults to "double" rounding.
3274     return 1;
3275   }
3276 };
3277 } // end anonymous namespace
3278 
3279 namespace {
3280 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3281 public:
3282   OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3283       : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3284     SizeType = UnsignedLong;
3285     IntPtrType = SignedLong;
3286     PtrDiffType = SignedLong;
3287   }
3288 };
3289 } // end anonymous namespace
3290 
3291 namespace {
3292 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3293 public:
3294   BitrigI386TargetInfo(const llvm::Triple &Triple)
3295       : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3296     SizeType = UnsignedLong;
3297     IntPtrType = SignedLong;
3298     PtrDiffType = SignedLong;
3299   }
3300 };
3301 } // end anonymous namespace
3302 
3303 namespace {
3304 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3305 public:
3306   DarwinI386TargetInfo(const llvm::Triple &Triple)
3307       : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3308     LongDoubleWidth = 128;
3309     LongDoubleAlign = 128;
3310     SuitableAlign = 128;
3311     MaxVectorAlign = 256;
3312     SizeType = UnsignedLong;
3313     IntPtrType = SignedLong;
3314     DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3315     HasAlignMac68kSupport = true;
3316   }
3317 
3318 };
3319 } // end anonymous namespace
3320 
3321 namespace {
3322 // x86-32 Windows target
3323 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3324 public:
3325   WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3326       : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3327     WCharType = UnsignedShort;
3328     DoubleAlign = LongLongAlign = 64;
3329     DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3330   }
3331   void getTargetDefines(const LangOptions &Opts,
3332                         MacroBuilder &Builder) const override {
3333     WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3334   }
3335 };
3336 
3337 // x86-32 Windows Visual Studio target
3338 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3339 public:
3340   MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3341       : WindowsX86_32TargetInfo(Triple) {
3342     LongDoubleWidth = LongDoubleAlign = 64;
3343     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3344   }
3345   void getTargetDefines(const LangOptions &Opts,
3346                         MacroBuilder &Builder) const override {
3347     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3348     WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3349     // The value of the following reflects processor type.
3350     // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3351     // We lost the original triple, so we use the default.
3352     Builder.defineMacro("_M_IX86", "600");
3353   }
3354 };
3355 } // end anonymous namespace
3356 
3357 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3358   Builder.defineMacro("__MSVCRT__");
3359   Builder.defineMacro("__MINGW32__");
3360 
3361   // Mingw defines __declspec(a) to __attribute__((a)).  Clang supports
3362   // __declspec natively under -fms-extensions, but we define a no-op __declspec
3363   // macro anyway for pre-processor compatibility.
3364   if (Opts.MicrosoftExt)
3365     Builder.defineMacro("__declspec", "__declspec");
3366   else
3367     Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3368 
3369   if (!Opts.MicrosoftExt) {
3370     // Provide macros for all the calling convention keywords.  Provide both
3371     // single and double underscore prefixed variants.  These are available on
3372     // x64 as well as x86, even though they have no effect.
3373     const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3374     for (const char *CC : CCs) {
3375       std::string GCCSpelling = "__attribute__((__";
3376       GCCSpelling += CC;
3377       GCCSpelling += "__))";
3378       Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3379       Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3380     }
3381   }
3382 }
3383 
3384 namespace {
3385 // x86-32 MinGW target
3386 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3387 public:
3388   MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3389       : WindowsX86_32TargetInfo(Triple) {}
3390   void getTargetDefines(const LangOptions &Opts,
3391                         MacroBuilder &Builder) const override {
3392     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3393     DefineStd(Builder, "WIN32", Opts);
3394     DefineStd(Builder, "WINNT", Opts);
3395     Builder.defineMacro("_X86_");
3396     addMinGWDefines(Opts, Builder);
3397   }
3398 };
3399 } // end anonymous namespace
3400 
3401 namespace {
3402 // x86-32 Cygwin target
3403 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3404 public:
3405   CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3406       : X86_32TargetInfo(Triple) {
3407     TLSSupported = false;
3408     WCharType = UnsignedShort;
3409     DoubleAlign = LongLongAlign = 64;
3410     DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3411   }
3412   void getTargetDefines(const LangOptions &Opts,
3413                         MacroBuilder &Builder) const override {
3414     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3415     Builder.defineMacro("_X86_");
3416     Builder.defineMacro("__CYGWIN__");
3417     Builder.defineMacro("__CYGWIN32__");
3418     DefineStd(Builder, "unix", Opts);
3419     if (Opts.CPlusPlus)
3420       Builder.defineMacro("_GNU_SOURCE");
3421   }
3422 };
3423 } // end anonymous namespace
3424 
3425 namespace {
3426 // x86-32 Haiku target
3427 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3428 public:
3429   HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3430     SizeType = UnsignedLong;
3431     IntPtrType = SignedLong;
3432     PtrDiffType = SignedLong;
3433     ProcessIDType = SignedLong;
3434     this->UserLabelPrefix = "";
3435     this->TLSSupported = false;
3436   }
3437   void getTargetDefines(const LangOptions &Opts,
3438                         MacroBuilder &Builder) const override {
3439     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3440     Builder.defineMacro("__INTEL__");
3441     Builder.defineMacro("__HAIKU__");
3442   }
3443 };
3444 } // end anonymous namespace
3445 
3446 // RTEMS Target
3447 template<typename Target>
3448 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3449 protected:
3450   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3451                     MacroBuilder &Builder) const override {
3452     // RTEMS defines; list based off of gcc output
3453 
3454     Builder.defineMacro("__rtems__");
3455     Builder.defineMacro("__ELF__");
3456   }
3457 
3458 public:
3459   RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3460     this->UserLabelPrefix = "";
3461 
3462     switch (Triple.getArch()) {
3463     default:
3464     case llvm::Triple::x86:
3465       // this->MCountName = ".mcount";
3466       break;
3467     case llvm::Triple::mips:
3468     case llvm::Triple::mipsel:
3469     case llvm::Triple::ppc:
3470     case llvm::Triple::ppc64:
3471     case llvm::Triple::ppc64le:
3472       // this->MCountName = "_mcount";
3473       break;
3474     case llvm::Triple::arm:
3475       // this->MCountName = "__mcount";
3476       break;
3477     }
3478   }
3479 };
3480 
3481 namespace {
3482 // x86-32 RTEMS target
3483 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3484 public:
3485   RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3486     SizeType = UnsignedLong;
3487     IntPtrType = SignedLong;
3488     PtrDiffType = SignedLong;
3489     this->UserLabelPrefix = "";
3490   }
3491   void getTargetDefines(const LangOptions &Opts,
3492                         MacroBuilder &Builder) const override {
3493     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3494     Builder.defineMacro("__INTEL__");
3495     Builder.defineMacro("__rtems__");
3496   }
3497 };
3498 } // end anonymous namespace
3499 
3500 namespace {
3501 // x86-64 generic target
3502 class X86_64TargetInfo : public X86TargetInfo {
3503 public:
3504   X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3505     const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3506     LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3507     LongDoubleWidth = 128;
3508     LongDoubleAlign = 128;
3509     LargeArrayMinWidth = 128;
3510     LargeArrayAlign = 128;
3511     SuitableAlign = 128;
3512     SizeType    = IsX32 ? UnsignedInt      : UnsignedLong;
3513     PtrDiffType = IsX32 ? SignedInt        : SignedLong;
3514     IntPtrType  = IsX32 ? SignedInt        : SignedLong;
3515     IntMaxType  = IsX32 ? SignedLongLong   : SignedLong;
3516     Int64Type   = IsX32 ? SignedLongLong   : SignedLong;
3517     RegParmMax = 6;
3518 
3519     // Pointers are 32-bit in x32.
3520     DescriptionString = (IsX32)
3521                             ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3522                             : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3523 
3524     // Use fpret only for long double.
3525     RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3526 
3527     // Use fp2ret for _Complex long double.
3528     ComplexLongDoubleUsesFP2Ret = true;
3529 
3530     // x86-64 has atomics up to 16 bytes.
3531     MaxAtomicPromoteWidth = 128;
3532     MaxAtomicInlineWidth = 128;
3533   }
3534   BuiltinVaListKind getBuiltinVaListKind() const override {
3535     return TargetInfo::X86_64ABIBuiltinVaList;
3536   }
3537 
3538   int getEHDataRegisterNumber(unsigned RegNo) const override {
3539     if (RegNo == 0) return 0;
3540     if (RegNo == 1) return 1;
3541     return -1;
3542   }
3543 
3544   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3545     return (CC == CC_C ||
3546             CC == CC_X86VectorCall ||
3547             CC == CC_IntelOclBicc ||
3548             CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3549   }
3550 
3551   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3552     return CC_C;
3553   }
3554 
3555   // for x32 we need it here explicitly
3556   bool hasInt128Type() const override { return true; }
3557 };
3558 } // end anonymous namespace
3559 
3560 namespace {
3561 // x86-64 Windows target
3562 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3563 public:
3564   WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3565       : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3566     WCharType = UnsignedShort;
3567     LongWidth = LongAlign = 32;
3568     DoubleAlign = LongLongAlign = 64;
3569     IntMaxType = SignedLongLong;
3570     Int64Type = SignedLongLong;
3571     SizeType = UnsignedLongLong;
3572     PtrDiffType = SignedLongLong;
3573     IntPtrType = SignedLongLong;
3574     this->UserLabelPrefix = "";
3575   }
3576   void getTargetDefines(const LangOptions &Opts,
3577                                 MacroBuilder &Builder) const override {
3578     WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3579     Builder.defineMacro("_WIN64");
3580   }
3581   BuiltinVaListKind getBuiltinVaListKind() const override {
3582     return TargetInfo::CharPtrBuiltinVaList;
3583   }
3584   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3585     return (CC == CC_C ||
3586             CC == CC_X86VectorCall ||
3587             CC == CC_IntelOclBicc ||
3588             CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
3589   }
3590 };
3591 } // end anonymous namespace
3592 
3593 namespace {
3594 // x86-64 Windows Visual Studio target
3595 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3596 public:
3597   MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3598       : WindowsX86_64TargetInfo(Triple) {
3599     LongDoubleWidth = LongDoubleAlign = 64;
3600     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3601   }
3602   void getTargetDefines(const LangOptions &Opts,
3603                         MacroBuilder &Builder) const override {
3604     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3605     WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3606     Builder.defineMacro("_M_X64");
3607     Builder.defineMacro("_M_AMD64");
3608   }
3609 };
3610 } // end anonymous namespace
3611 
3612 namespace {
3613 // x86-64 MinGW target
3614 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3615 public:
3616   MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3617       : WindowsX86_64TargetInfo(Triple) {}
3618   void getTargetDefines(const LangOptions &Opts,
3619                         MacroBuilder &Builder) const override {
3620     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3621     DefineStd(Builder, "WIN64", Opts);
3622     Builder.defineMacro("__MINGW64__");
3623     addMinGWDefines(Opts, Builder);
3624 
3625     // GCC defines this macro when it is using __gxx_personality_seh0.
3626     if (!Opts.SjLjExceptions)
3627       Builder.defineMacro("__SEH__");
3628   }
3629 };
3630 } // end anonymous namespace
3631 
3632 namespace {
3633 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3634 public:
3635   DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3636       : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3637     Int64Type = SignedLongLong;
3638     MaxVectorAlign = 256;
3639     // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3640     llvm::Triple T = llvm::Triple(Triple);
3641     if (T.isiOS())
3642       UseSignedCharForObjCBool = false;
3643     DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3644   }
3645 };
3646 } // end anonymous namespace
3647 
3648 namespace {
3649 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3650 public:
3651   OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3652       : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3653     IntMaxType = SignedLongLong;
3654     Int64Type = SignedLongLong;
3655   }
3656 };
3657 } // end anonymous namespace
3658 
3659 namespace {
3660 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3661 public:
3662   BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3663       : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3664     IntMaxType = SignedLongLong;
3665     Int64Type = SignedLongLong;
3666   }
3667 };
3668 }
3669 
3670 
3671 namespace {
3672 class ARMTargetInfo : public TargetInfo {
3673   // Possible FPU choices.
3674   enum FPUMode {
3675     VFP2FPU = (1 << 0),
3676     VFP3FPU = (1 << 1),
3677     VFP4FPU = (1 << 2),
3678     NeonFPU = (1 << 3),
3679     FPARMV8 = (1 << 4)
3680   };
3681 
3682   // Possible HWDiv features.
3683   enum HWDivMode {
3684     HWDivThumb = (1 << 0),
3685     HWDivARM = (1 << 1)
3686   };
3687 
3688   static bool FPUModeIsVFP(FPUMode Mode) {
3689     return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3690   }
3691 
3692   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3693   static const char * const GCCRegNames[];
3694 
3695   std::string ABI, CPU;
3696 
3697   enum {
3698     FP_Default,
3699     FP_VFP,
3700     FP_Neon
3701   } FPMath;
3702 
3703   unsigned FPU : 5;
3704 
3705   unsigned IsAAPCS : 1;
3706   unsigned IsThumb : 1;
3707   unsigned HWDiv : 2;
3708 
3709   // Initialized via features.
3710   unsigned SoftFloat : 1;
3711   unsigned SoftFloatABI : 1;
3712 
3713   unsigned CRC : 1;
3714   unsigned Crypto : 1;
3715 
3716   // ACLE 6.5.1 Hardware floating point
3717   enum {
3718     HW_FP_HP = (1 << 1), /// half (16-bit)
3719     HW_FP_SP = (1 << 2), /// single (32-bit)
3720     HW_FP_DP = (1 << 3), /// double (64-bit)
3721   };
3722   uint32_t HW_FP;
3723 
3724   static const Builtin::Info BuiltinInfo[];
3725 
3726   static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3727     StringRef ArchName = T.getArchName();
3728     if (T.getArch() == llvm::Triple::arm ||
3729         T.getArch() == llvm::Triple::armeb) {
3730       StringRef VersionStr;
3731       if (ArchName.startswith("armv"))
3732         VersionStr = ArchName.substr(4, 1);
3733       else if (ArchName.startswith("armebv"))
3734         VersionStr = ArchName.substr(6, 1);
3735       else
3736         return false;
3737       unsigned Version;
3738       if (VersionStr.getAsInteger(10, Version))
3739         return false;
3740       return Version >= 6;
3741     }
3742     assert(T.getArch() == llvm::Triple::thumb ||
3743            T.getArch() == llvm::Triple::thumbeb);
3744     StringRef VersionStr;
3745     if (ArchName.startswith("thumbv"))
3746       VersionStr = ArchName.substr(6, 1);
3747     else if (ArchName.startswith("thumbebv"))
3748       VersionStr = ArchName.substr(8, 1);
3749     else
3750       return false;
3751     unsigned Version;
3752     if (VersionStr.getAsInteger(10, Version))
3753       return false;
3754     return Version >= 7;
3755   }
3756 
3757   void setABIAAPCS() {
3758     IsAAPCS = true;
3759 
3760     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
3761     const llvm::Triple &T = getTriple();
3762 
3763     // size_t is unsigned long on MachO-derived environments and NetBSD.
3764     if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD)
3765       SizeType = UnsignedLong;
3766     else
3767       SizeType = UnsignedInt;
3768 
3769     switch (T.getOS()) {
3770     case llvm::Triple::NetBSD:
3771       WCharType = SignedInt;
3772       break;
3773     case llvm::Triple::Win32:
3774       WCharType = UnsignedShort;
3775       break;
3776     case llvm::Triple::Linux:
3777     default:
3778       // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3779       WCharType = UnsignedInt;
3780       break;
3781     }
3782 
3783     UseBitFieldTypeAlignment = true;
3784 
3785     ZeroLengthBitfieldBoundary = 0;
3786 
3787     // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3788     // so set preferred for small types to 32.
3789     if (T.isOSBinFormatMachO()) {
3790       DescriptionString =
3791           BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3792                     : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3793     } else if (T.isOSWindows()) {
3794       // FIXME: this is invalid for WindowsCE
3795       assert(!BigEndian && "Windows on ARM does not support big endian");
3796       DescriptionString = "e"
3797                           "-m:e"
3798                           "-p:32:32"
3799                           "-i64:64"
3800                           "-v128:64:128"
3801                           "-a:0:32"
3802                           "-n32"
3803                           "-S64";
3804     } else {
3805       DescriptionString =
3806           BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3807                     : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3808     }
3809 
3810     // FIXME: Enumerated types are variable width in straight AAPCS.
3811   }
3812 
3813   void setABIAPCS() {
3814     const llvm::Triple &T = getTriple();
3815 
3816     IsAAPCS = false;
3817 
3818     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3819 
3820     // size_t is unsigned int on FreeBSD.
3821     if (T.getOS() == llvm::Triple::FreeBSD)
3822       SizeType = UnsignedInt;
3823     else
3824       SizeType = UnsignedLong;
3825 
3826     // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3827     WCharType = SignedInt;
3828 
3829     // Do not respect the alignment of bit-field types when laying out
3830     // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3831     UseBitFieldTypeAlignment = false;
3832 
3833     /// gcc forces the alignment to 4 bytes, regardless of the type of the
3834     /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3835     /// gcc.
3836     ZeroLengthBitfieldBoundary = 32;
3837 
3838     if (T.isOSBinFormatMachO())
3839       DescriptionString =
3840           BigEndian
3841               ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3842               : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3843     else
3844       DescriptionString =
3845           BigEndian
3846               ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3847               : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3848 
3849     // FIXME: Override "preferred align" for double and long long.
3850   }
3851 
3852 public:
3853   ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
3854       : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
3855         IsAAPCS(true), HW_FP(0) {
3856     BigEndian = IsBigEndian;
3857 
3858     switch (getTriple().getOS()) {
3859     case llvm::Triple::NetBSD:
3860       PtrDiffType = SignedLong;
3861       break;
3862     default:
3863       PtrDiffType = SignedInt;
3864       break;
3865     }
3866 
3867     // {} in inline assembly are neon specifiers, not assembly variant
3868     // specifiers.
3869     NoAsmVariants = true;
3870 
3871     // FIXME: Should we just treat this as a feature?
3872     IsThumb = getTriple().getArchName().startswith("thumb");
3873 
3874     // FIXME: This duplicates code from the driver that sets the -target-abi
3875     // option - this code is used if -target-abi isn't passed and should
3876     // be unified in some way.
3877     if (Triple.isOSBinFormatMachO()) {
3878       // The backend is hardwired to assume AAPCS for M-class processors, ensure
3879       // the frontend matches that.
3880       if (Triple.getEnvironment() == llvm::Triple::EABI ||
3881           Triple.getOS() == llvm::Triple::UnknownOS ||
3882           StringRef(CPU).startswith("cortex-m")) {
3883         setABI("aapcs");
3884       } else {
3885         setABI("apcs-gnu");
3886       }
3887     } else if (Triple.isOSWindows()) {
3888       // FIXME: this is invalid for WindowsCE
3889       setABI("aapcs");
3890     } else {
3891       // Select the default based on the platform.
3892       switch (Triple.getEnvironment()) {
3893       case llvm::Triple::Android:
3894       case llvm::Triple::GNUEABI:
3895       case llvm::Triple::GNUEABIHF:
3896         setABI("aapcs-linux");
3897         break;
3898       case llvm::Triple::EABIHF:
3899       case llvm::Triple::EABI:
3900         setABI("aapcs");
3901         break;
3902       case llvm::Triple::GNU:
3903 	setABI("apcs-gnu");
3904 	break;
3905       default:
3906         if (Triple.getOS() == llvm::Triple::NetBSD)
3907           setABI("apcs-gnu");
3908         else
3909           setABI("aapcs");
3910         break;
3911       }
3912     }
3913 
3914     // ARM targets default to using the ARM C++ ABI.
3915     TheCXXABI.set(TargetCXXABI::GenericARM);
3916 
3917     // ARM has atomics up to 8 bytes
3918     MaxAtomicPromoteWidth = 64;
3919     if (shouldUseInlineAtomic(getTriple()))
3920       MaxAtomicInlineWidth = 64;
3921 
3922     // Do force alignment of members that follow zero length bitfields.  If
3923     // the alignment of the zero-length bitfield is greater than the member
3924     // that follows it, `bar', `bar' will be aligned as the  type of the
3925     // zero length bitfield.
3926     UseZeroLengthBitfieldAlignment = true;
3927   }
3928   StringRef getABI() const override { return ABI; }
3929   bool setABI(const std::string &Name) override {
3930     ABI = Name;
3931 
3932     // The defaults (above) are for AAPCS, check if we need to change them.
3933     //
3934     // FIXME: We need support for -meabi... we could just mangle it into the
3935     // name.
3936     if (Name == "apcs-gnu") {
3937       setABIAPCS();
3938       return true;
3939     }
3940     if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
3941       setABIAAPCS();
3942       return true;
3943     }
3944     return false;
3945   }
3946 
3947   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
3948     StringRef ArchName = getTriple().getArchName();
3949     if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3950       Features["vfp2"] = true;
3951     else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
3952       Features["vfp3"] = true;
3953       Features["neon"] = true;
3954     }
3955     else if (CPU == "cortex-a5") {
3956       Features["vfp4"] = true;
3957       Features["neon"] = true;
3958     } else if (CPU == "swift" || CPU == "cortex-a7" ||
3959                CPU == "cortex-a12" || CPU == "cortex-a15" ||
3960                CPU == "cortex-a17" || CPU == "krait") {
3961       Features["vfp4"] = true;
3962       Features["neon"] = true;
3963       Features["hwdiv"] = true;
3964       Features["hwdiv-arm"] = true;
3965     } else if (CPU == "cyclone") {
3966       Features["v8fp"] = true;
3967       Features["neon"] = true;
3968       Features["hwdiv"] = true;
3969       Features["hwdiv-arm"] = true;
3970     } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
3971       Features["fp-armv8"] = true;
3972       Features["neon"] = true;
3973       Features["hwdiv"] = true;
3974       Features["hwdiv-arm"] = true;
3975       Features["crc"] = true;
3976       Features["crypto"] = true;
3977     } else if (CPU == "cortex-r5" ||
3978                // Enable the hwdiv extension for all v8a AArch32 cores by
3979                // default.
3980                ArchName == "armv8a" || ArchName == "armv8" ||
3981                ArchName == "armebv8a" || ArchName == "armebv8" ||
3982                ArchName == "thumbv8a" || ArchName == "thumbv8" ||
3983                ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
3984       Features["hwdiv"] = true;
3985       Features["hwdiv-arm"] = true;
3986     } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7") {
3987       Features["hwdiv"] = true;
3988     }
3989   }
3990 
3991   bool handleTargetFeatures(std::vector<std::string> &Features,
3992                             DiagnosticsEngine &Diags) override {
3993     FPU = 0;
3994     CRC = 0;
3995     Crypto = 0;
3996     SoftFloat = SoftFloatABI = false;
3997     HWDiv = 0;
3998 
3999     for (const auto &Feature : Features) {
4000       if (Feature == "+soft-float") {
4001         SoftFloat = true;
4002       } else if (Feature == "+soft-float-abi") {
4003         SoftFloatABI = true;
4004       } else if (Feature == "+vfp2") {
4005         FPU |= VFP2FPU;
4006         HW_FP = HW_FP_SP | HW_FP_DP;
4007       } else if (Feature == "+vfp3") {
4008         FPU |= VFP3FPU;
4009         HW_FP = HW_FP_SP | HW_FP_DP;
4010       } else if (Feature == "+vfp4") {
4011         FPU |= VFP4FPU;
4012         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4013       } else if (Feature == "+fp-armv8") {
4014         FPU |= FPARMV8;
4015         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4016       } else if (Feature == "+neon") {
4017         FPU |= NeonFPU;
4018         HW_FP = HW_FP_SP | HW_FP_DP;
4019       } else if (Feature == "+hwdiv") {
4020         HWDiv |= HWDivThumb;
4021       } else if (Feature == "+hwdiv-arm") {
4022         HWDiv |= HWDivARM;
4023       } else if (Feature == "+crc") {
4024         CRC = 1;
4025       } else if (Feature == "+crypto") {
4026         Crypto = 1;
4027       } else if (Feature == "+fp-only-sp") {
4028         HW_FP &= ~HW_FP_DP;
4029       }
4030     }
4031 
4032     if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4033       Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4034       return false;
4035     }
4036 
4037     if (FPMath == FP_Neon)
4038       Features.push_back("+neonfp");
4039     else if (FPMath == FP_VFP)
4040       Features.push_back("-neonfp");
4041 
4042     // Remove front-end specific options which the backend handles differently.
4043     const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" };
4044     for (const auto &FEFeature : FrontEndFeatures) {
4045       auto Feature = std::find(Features.begin(), Features.end(), FEFeature);
4046       if (Feature != Features.end())
4047         Features.erase(Feature);
4048     }
4049 
4050     return true;
4051   }
4052 
4053   bool hasFeature(StringRef Feature) const override {
4054     return llvm::StringSwitch<bool>(Feature)
4055         .Case("arm", true)
4056         .Case("softfloat", SoftFloat)
4057         .Case("thumb", IsThumb)
4058         .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4059         .Case("hwdiv", HWDiv & HWDivThumb)
4060         .Case("hwdiv-arm", HWDiv & HWDivARM)
4061         .Default(false);
4062   }
4063   // FIXME: Should we actually have some table instead of these switches?
4064   static const char *getCPUDefineSuffix(StringRef Name) {
4065     return llvm::StringSwitch<const char *>(Name)
4066         .Cases("arm8", "arm810", "4")
4067         .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110",
4068                "4")
4069         .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
4070         .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
4071         .Case("ep9312", "4T")
4072         .Cases("arm10tdmi", "arm1020t", "5T")
4073         .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
4074         .Case("arm926ej-s", "5TEJ")
4075         .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
4076         .Cases("xscale", "iwmmxt", "5TE")
4077         .Case("arm1136j-s", "6J")
4078         .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
4079         .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
4080         .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
4081         .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
4082         .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4083                "7A")
4084         .Cases("cortex-r4", "cortex-r5", "7R")
4085         .Case("swift", "7S")
4086         .Case("cyclone", "8A")
4087         .Case("cortex-m3", "7M")
4088         .Cases("cortex-m4", "cortex-m7", "7EM")
4089         .Case("cortex-m0", "6M")
4090         .Cases("cortex-a53", "cortex-a57", "8A")
4091         .Default(nullptr);
4092   }
4093   static const char *getCPUProfile(StringRef Name) {
4094     return llvm::StringSwitch<const char *>(Name)
4095         .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
4096         .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4097                "A")
4098         .Cases("cortex-a53", "cortex-a57", "A")
4099         .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M")
4100         .Cases("cortex-r4", "cortex-r5", "R")
4101         .Default("");
4102   }
4103   bool setCPU(const std::string &Name) override {
4104     if (!getCPUDefineSuffix(Name))
4105       return false;
4106 
4107     // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4108     StringRef Profile = getCPUProfile(Name);
4109     if (Profile == "M" && MaxAtomicInlineWidth) {
4110       MaxAtomicPromoteWidth = 32;
4111       MaxAtomicInlineWidth = 32;
4112     }
4113 
4114     CPU = Name;
4115     return true;
4116   }
4117   bool setFPMath(StringRef Name) override;
4118   bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4119                      unsigned CPUArchVer) const {
4120     return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4121            (CPUArch.find('M') != StringRef::npos);
4122   }
4123   bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4124                       unsigned CPUArchVer) const {
4125     // We check both CPUArchVer and ArchName because when only triple is
4126     // specified, the default CPU is arm1136j-s.
4127     return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4128            ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4129   }
4130   void getTargetDefines(const LangOptions &Opts,
4131                         MacroBuilder &Builder) const override {
4132     // Target identification.
4133     Builder.defineMacro("__arm");
4134     Builder.defineMacro("__arm__");
4135 
4136     // Target properties.
4137     Builder.defineMacro("__REGISTER_PREFIX__", "");
4138 
4139     StringRef CPUArch = getCPUDefineSuffix(CPU);
4140     unsigned int CPUArchVer;
4141     if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4142       llvm_unreachable("Invalid char for architecture version number");
4143     Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4144 
4145     // ACLE 6.4.1 ARM/Thumb instruction set architecture
4146     StringRef CPUProfile = getCPUProfile(CPU);
4147     StringRef ArchName = getTriple().getArchName();
4148 
4149     // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4150     Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4151     if (CPUArch[0] >= '8') {
4152       Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4153       Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4154     }
4155 
4156     // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
4157     // is not defined for the M-profile.
4158     // NOTE that the deffault profile is assumed to be 'A'
4159     if (CPUProfile.empty() || CPUProfile != "M")
4160       Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4161 
4162     // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4163     // Thumb ISA (including v6-M).  It is set to 2 if the core supports the
4164     // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4165     if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4166       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4167     else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4168       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4169 
4170     // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4171     // instruction set such as ARM or Thumb.
4172     Builder.defineMacro("__ARM_32BIT_STATE", "1");
4173 
4174     // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4175 
4176     // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4177     if (!CPUProfile.empty())
4178       Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4179 
4180     // ACLE 6.5.1 Hardware Floating Point
4181     if (HW_FP)
4182       Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4183 
4184     // ACLE predefines.
4185     Builder.defineMacro("__ARM_ACLE", "200");
4186 
4187     // Subtarget options.
4188 
4189     // FIXME: It's more complicated than this and we don't really support
4190     // interworking.
4191     // Windows on ARM does not "support" interworking
4192     if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4193       Builder.defineMacro("__THUMB_INTERWORK__");
4194 
4195     if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4196       // Embedded targets on Darwin follow AAPCS, but not EABI.
4197       // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4198       if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4199         Builder.defineMacro("__ARM_EABI__");
4200       Builder.defineMacro("__ARM_PCS", "1");
4201 
4202       if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4203         Builder.defineMacro("__ARM_PCS_VFP", "1");
4204     }
4205 
4206     if (SoftFloat)
4207       Builder.defineMacro("__SOFTFP__");
4208 
4209     if (CPU == "xscale")
4210       Builder.defineMacro("__XSCALE__");
4211 
4212     if (IsThumb) {
4213       Builder.defineMacro("__THUMBEL__");
4214       Builder.defineMacro("__thumb__");
4215       if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4216         Builder.defineMacro("__thumb2__");
4217     }
4218     if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4219       Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4220 
4221     // Note, this is always on in gcc, even though it doesn't make sense.
4222     Builder.defineMacro("__APCS_32__");
4223 
4224     if (FPUModeIsVFP((FPUMode) FPU)) {
4225       Builder.defineMacro("__VFP_FP__");
4226       if (FPU & VFP2FPU)
4227         Builder.defineMacro("__ARM_VFPV2__");
4228       if (FPU & VFP3FPU)
4229         Builder.defineMacro("__ARM_VFPV3__");
4230       if (FPU & VFP4FPU)
4231         Builder.defineMacro("__ARM_VFPV4__");
4232     }
4233 
4234     // This only gets set when Neon instructions are actually available, unlike
4235     // the VFP define, hence the soft float and arch check. This is subtly
4236     // different from gcc, we follow the intent which was that it should be set
4237     // when Neon instructions are actually available.
4238     if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4239       Builder.defineMacro("__ARM_NEON");
4240       Builder.defineMacro("__ARM_NEON__");
4241     }
4242 
4243     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4244                         Opts.ShortWChar ? "2" : "4");
4245 
4246     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4247                         Opts.ShortEnums ? "1" : "4");
4248 
4249     if (CRC)
4250       Builder.defineMacro("__ARM_FEATURE_CRC32");
4251 
4252     if (Crypto)
4253       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4254 
4255     if (CPUArchVer >= 6 && CPUArch != "6M") {
4256       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4257       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4258       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4259       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4260     }
4261 
4262     bool is5EOrAbove = (CPUArchVer >= 6 ||
4263                         (CPUArchVer == 5 &&
4264                          CPUArch.find('E') != StringRef::npos));
4265     bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
4266     if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch  == "7EM"))
4267       Builder.defineMacro("__ARM_FEATURE_DSP");
4268   }
4269   void getTargetBuiltins(const Builtin::Info *&Records,
4270                          unsigned &NumRecords) const override {
4271     Records = BuiltinInfo;
4272     NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4273   }
4274   bool isCLZForZeroUndef() const override { return false; }
4275   BuiltinVaListKind getBuiltinVaListKind() const override {
4276     return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4277   }
4278   void getGCCRegNames(const char * const *&Names,
4279                       unsigned &NumNames) const override;
4280   void getGCCRegAliases(const GCCRegAlias *&Aliases,
4281                         unsigned &NumAliases) const override;
4282   bool validateAsmConstraint(const char *&Name,
4283                              TargetInfo::ConstraintInfo &Info) const override {
4284     switch (*Name) {
4285     default: break;
4286     case 'l': // r0-r7
4287     case 'h': // r8-r15
4288     case 'w': // VFP Floating point register single precision
4289     case 'P': // VFP Floating point register double precision
4290       Info.setAllowsRegister();
4291       return true;
4292     case 'Q': // A memory address that is a single base register.
4293       Info.setAllowsMemory();
4294       return true;
4295     case 'U': // a memory reference...
4296       switch (Name[1]) {
4297       case 'q': // ...ARMV4 ldrsb
4298       case 'v': // ...VFP load/store (reg+constant offset)
4299       case 'y': // ...iWMMXt load/store
4300       case 't': // address valid for load/store opaque types wider
4301                 // than 128-bits
4302       case 'n': // valid address for Neon doubleword vector load/store
4303       case 'm': // valid address for Neon element and structure load/store
4304       case 's': // valid address for non-offset loads/stores of quad-word
4305                 // values in four ARM registers
4306         Info.setAllowsMemory();
4307         Name++;
4308         return true;
4309       }
4310     }
4311     return false;
4312   }
4313   std::string convertConstraint(const char *&Constraint) const override {
4314     std::string R;
4315     switch (*Constraint) {
4316     case 'U':   // Two-character constraint; add "^" hint for later parsing.
4317       R = std::string("^") + std::string(Constraint, 2);
4318       Constraint++;
4319       break;
4320     case 'p': // 'p' should be translated to 'r' by default.
4321       R = std::string("r");
4322       break;
4323     default:
4324       return std::string(1, *Constraint);
4325     }
4326     return R;
4327   }
4328   bool
4329   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4330                              std::string &SuggestedModifier) const override {
4331     bool isOutput = (Constraint[0] == '=');
4332     bool isInOut = (Constraint[0] == '+');
4333 
4334     // Strip off constraint modifiers.
4335     while (Constraint[0] == '=' ||
4336            Constraint[0] == '+' ||
4337            Constraint[0] == '&')
4338       Constraint = Constraint.substr(1);
4339 
4340     switch (Constraint[0]) {
4341     default: break;
4342     case 'r': {
4343       switch (Modifier) {
4344       default:
4345         return (isInOut || isOutput || Size <= 64);
4346       case 'q':
4347         // A register of size 32 cannot fit a vector type.
4348         return false;
4349       }
4350     }
4351     }
4352 
4353     return true;
4354   }
4355   const char *getClobbers() const override {
4356     // FIXME: Is this really right?
4357     return "";
4358   }
4359 
4360   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4361     return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4362   }
4363 
4364   int getEHDataRegisterNumber(unsigned RegNo) const override {
4365     if (RegNo == 0) return 0;
4366     if (RegNo == 1) return 1;
4367     return -1;
4368   }
4369 };
4370 
4371 bool ARMTargetInfo::setFPMath(StringRef Name) {
4372   if (Name == "neon") {
4373     FPMath = FP_Neon;
4374     return true;
4375   } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4376              Name == "vfp4") {
4377     FPMath = FP_VFP;
4378     return true;
4379   }
4380   return false;
4381 }
4382 
4383 const char * const ARMTargetInfo::GCCRegNames[] = {
4384   // Integer registers
4385   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4386   "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4387 
4388   // Float registers
4389   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4390   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4391   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4392   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4393 
4394   // Double registers
4395   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4396   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4397   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4398   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4399 
4400   // Quad registers
4401   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4402   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4403 };
4404 
4405 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4406                                    unsigned &NumNames) const {
4407   Names = GCCRegNames;
4408   NumNames = llvm::array_lengthof(GCCRegNames);
4409 }
4410 
4411 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4412   { { "a1" }, "r0" },
4413   { { "a2" }, "r1" },
4414   { { "a3" }, "r2" },
4415   { { "a4" }, "r3" },
4416   { { "v1" }, "r4" },
4417   { { "v2" }, "r5" },
4418   { { "v3" }, "r6" },
4419   { { "v4" }, "r7" },
4420   { { "v5" }, "r8" },
4421   { { "v6", "rfp" }, "r9" },
4422   { { "sl" }, "r10" },
4423   { { "fp" }, "r11" },
4424   { { "ip" }, "r12" },
4425   { { "r13" }, "sp" },
4426   { { "r14" }, "lr" },
4427   { { "r15" }, "pc" },
4428   // The S, D and Q registers overlap, but aren't really aliases; we
4429   // don't want to substitute one of these for a different-sized one.
4430 };
4431 
4432 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4433                                        unsigned &NumAliases) const {
4434   Aliases = GCCRegAliases;
4435   NumAliases = llvm::array_lengthof(GCCRegAliases);
4436 }
4437 
4438 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4439 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4440 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4441                                               ALL_LANGUAGES },
4442 #include "clang/Basic/BuiltinsNEON.def"
4443 
4444 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4445 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4446 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4447                                               ALL_LANGUAGES },
4448 #include "clang/Basic/BuiltinsARM.def"
4449 };
4450 
4451 class ARMleTargetInfo : public ARMTargetInfo {
4452 public:
4453   ARMleTargetInfo(const llvm::Triple &Triple)
4454     : ARMTargetInfo(Triple, false) { }
4455   virtual void getTargetDefines(const LangOptions &Opts,
4456                                 MacroBuilder &Builder) const {
4457     Builder.defineMacro("__ARMEL__");
4458     ARMTargetInfo::getTargetDefines(Opts, Builder);
4459   }
4460 };
4461 
4462 class ARMbeTargetInfo : public ARMTargetInfo {
4463 public:
4464   ARMbeTargetInfo(const llvm::Triple &Triple)
4465     : ARMTargetInfo(Triple, true) { }
4466   virtual void getTargetDefines(const LangOptions &Opts,
4467                                 MacroBuilder &Builder) const {
4468     Builder.defineMacro("__ARMEB__");
4469     Builder.defineMacro("__ARM_BIG_ENDIAN");
4470     ARMTargetInfo::getTargetDefines(Opts, Builder);
4471   }
4472 };
4473 } // end anonymous namespace.
4474 
4475 namespace {
4476 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4477   const llvm::Triple Triple;
4478 public:
4479   WindowsARMTargetInfo(const llvm::Triple &Triple)
4480     : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4481     TLSSupported = false;
4482     WCharType = UnsignedShort;
4483     SizeType = UnsignedInt;
4484     UserLabelPrefix = "";
4485   }
4486   void getVisualStudioDefines(const LangOptions &Opts,
4487                               MacroBuilder &Builder) const {
4488     WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4489 
4490     // FIXME: this is invalid for WindowsCE
4491     Builder.defineMacro("_M_ARM_NT", "1");
4492     Builder.defineMacro("_M_ARMT", "_M_ARM");
4493     Builder.defineMacro("_M_THUMB", "_M_ARM");
4494 
4495     assert((Triple.getArch() == llvm::Triple::arm ||
4496             Triple.getArch() == llvm::Triple::thumb) &&
4497            "invalid architecture for Windows ARM target info");
4498     unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4499     Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4500 
4501     // TODO map the complete set of values
4502     // 31: VFPv3 40: VFPv4
4503     Builder.defineMacro("_M_ARM_FP", "31");
4504   }
4505   BuiltinVaListKind getBuiltinVaListKind() const override {
4506     return TargetInfo::CharPtrBuiltinVaList;
4507   }
4508 };
4509 
4510 // Windows ARM + Itanium C++ ABI Target
4511 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4512 public:
4513   ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4514     : WindowsARMTargetInfo(Triple) {
4515     TheCXXABI.set(TargetCXXABI::GenericARM);
4516   }
4517 
4518   void getTargetDefines(const LangOptions &Opts,
4519                         MacroBuilder &Builder) const override {
4520     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4521 
4522     if (Opts.MSVCCompat)
4523       WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4524   }
4525 };
4526 
4527 // Windows ARM, MS (C++) ABI
4528 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4529 public:
4530   MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4531     : WindowsARMTargetInfo(Triple) {
4532     TheCXXABI.set(TargetCXXABI::Microsoft);
4533   }
4534 
4535   void getTargetDefines(const LangOptions &Opts,
4536                         MacroBuilder &Builder) const override {
4537     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4538     WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4539   }
4540 };
4541 }
4542 
4543 
4544 namespace {
4545 class DarwinARMTargetInfo :
4546   public DarwinTargetInfo<ARMleTargetInfo> {
4547 protected:
4548   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4549                     MacroBuilder &Builder) const override {
4550     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4551   }
4552 
4553 public:
4554   DarwinARMTargetInfo(const llvm::Triple &Triple)
4555       : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4556     HasAlignMac68kSupport = true;
4557     // iOS always has 64-bit atomic instructions.
4558     // FIXME: This should be based off of the target features in
4559     // ARMleTargetInfo.
4560     MaxAtomicInlineWidth = 64;
4561 
4562     // Darwin on iOS uses a variant of the ARM C++ ABI.
4563     TheCXXABI.set(TargetCXXABI::iOS);
4564   }
4565 };
4566 } // end anonymous namespace.
4567 
4568 
4569 namespace {
4570 class AArch64TargetInfo : public TargetInfo {
4571   virtual void setDescriptionString() = 0;
4572   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4573   static const char *const GCCRegNames[];
4574 
4575   enum FPUModeEnum {
4576     FPUMode,
4577     NeonMode
4578   };
4579 
4580   unsigned FPU;
4581   unsigned CRC;
4582   unsigned Crypto;
4583 
4584   static const Builtin::Info BuiltinInfo[];
4585 
4586   std::string ABI;
4587 
4588 public:
4589   AArch64TargetInfo(const llvm::Triple &Triple)
4590       : TargetInfo(Triple), ABI("aapcs") {
4591 
4592     if (getTriple().getOS() == llvm::Triple::NetBSD) {
4593       WCharType = SignedInt;
4594 
4595       // NetBSD apparently prefers consistency across ARM targets to consistency
4596       // across 64-bit targets.
4597       Int64Type = SignedLongLong;
4598       IntMaxType = SignedLongLong;
4599     } else {
4600       WCharType = UnsignedInt;
4601       Int64Type = SignedLong;
4602       IntMaxType = SignedLong;
4603     }
4604 
4605     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4606     MaxVectorAlign = 128;
4607     RegParmMax = 8;
4608     MaxAtomicInlineWidth = 128;
4609     MaxAtomicPromoteWidth = 128;
4610 
4611     LongDoubleWidth = LongDoubleAlign = 128;
4612     LongDoubleFormat = &llvm::APFloat::IEEEquad;
4613 
4614     // {} in inline assembly are neon specifiers, not assembly variant
4615     // specifiers.
4616     NoAsmVariants = true;
4617 
4618     // AArch64 targets default to using the ARM C++ ABI.
4619     TheCXXABI.set(TargetCXXABI::GenericAArch64);
4620   }
4621 
4622   StringRef getABI() const override { return ABI; }
4623   bool setABI(const std::string &Name) override {
4624     if (Name != "aapcs" && Name != "darwinpcs")
4625       return false;
4626 
4627     ABI = Name;
4628     return true;
4629   }
4630 
4631   bool setCPU(const std::string &Name) override {
4632     bool CPUKnown = llvm::StringSwitch<bool>(Name)
4633                         .Case("generic", true)
4634                         .Cases("cortex-a53", "cortex-a57", true)
4635                         .Case("cyclone", true)
4636                         .Default(false);
4637     return CPUKnown;
4638   }
4639 
4640   virtual void getTargetDefines(const LangOptions &Opts,
4641                                 MacroBuilder &Builder) const  override {
4642     // Target identification.
4643     Builder.defineMacro("__aarch64__");
4644 
4645     // Target properties.
4646     Builder.defineMacro("_LP64");
4647     Builder.defineMacro("__LP64__");
4648 
4649     // ACLE predefines. Many can only have one possible value on v8 AArch64.
4650     Builder.defineMacro("__ARM_ACLE", "200");
4651     Builder.defineMacro("__ARM_ARCH", "8");
4652     Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4653 
4654     Builder.defineMacro("__ARM_64BIT_STATE");
4655     Builder.defineMacro("__ARM_PCS_AAPCS64");
4656     Builder.defineMacro("__ARM_ARCH_ISA_A64");
4657 
4658     Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4659     Builder.defineMacro("__ARM_FEATURE_CLZ");
4660     Builder.defineMacro("__ARM_FEATURE_FMA");
4661     Builder.defineMacro("__ARM_FEATURE_DIV");
4662     Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
4663     Builder.defineMacro("__ARM_FEATURE_DIV");  // For backwards compatibility
4664     Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4665     Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4666 
4667     Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4668 
4669     // 0xe implies support for half, single and double precision operations.
4670     Builder.defineMacro("__ARM_FP", "0xe");
4671 
4672     // PCS specifies this for SysV variants, which is all we support. Other ABIs
4673     // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4674     Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4675 
4676     if (Opts.FastMath || Opts.FiniteMathOnly)
4677       Builder.defineMacro("__ARM_FP_FAST");
4678 
4679     if (Opts.C99 && !Opts.Freestanding)
4680       Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4681 
4682     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4683 
4684     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4685                         Opts.ShortEnums ? "1" : "4");
4686 
4687     if (FPU == NeonMode) {
4688       Builder.defineMacro("__ARM_NEON");
4689       // 64-bit NEON supports half, single and double precision operations.
4690       Builder.defineMacro("__ARM_NEON_FP", "0xe");
4691     }
4692 
4693     if (CRC)
4694       Builder.defineMacro("__ARM_FEATURE_CRC32");
4695 
4696     if (Crypto)
4697       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4698   }
4699 
4700   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4701                                  unsigned &NumRecords) const override {
4702     Records = BuiltinInfo;
4703     NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4704   }
4705 
4706   bool hasFeature(StringRef Feature) const override {
4707     return Feature == "aarch64" ||
4708       Feature == "arm64" ||
4709       (Feature == "neon" && FPU == NeonMode);
4710   }
4711 
4712   bool handleTargetFeatures(std::vector<std::string> &Features,
4713                             DiagnosticsEngine &Diags) override {
4714     FPU = FPUMode;
4715     CRC = 0;
4716     Crypto = 0;
4717     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
4718       if (Features[i] == "+neon")
4719         FPU = NeonMode;
4720       if (Features[i] == "+crc")
4721         CRC = 1;
4722       if (Features[i] == "+crypto")
4723         Crypto = 1;
4724     }
4725 
4726     setDescriptionString();
4727 
4728     return true;
4729   }
4730 
4731   bool isCLZForZeroUndef() const override { return false; }
4732 
4733   BuiltinVaListKind getBuiltinVaListKind() const override {
4734     return TargetInfo::AArch64ABIBuiltinVaList;
4735   }
4736 
4737   virtual void getGCCRegNames(const char *const *&Names,
4738                               unsigned &NumNames) const override;
4739   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4740                                 unsigned &NumAliases) const override;
4741 
4742   virtual bool
4743   validateAsmConstraint(const char *&Name,
4744                         TargetInfo::ConstraintInfo &Info) const override {
4745     switch (*Name) {
4746     default:
4747       return false;
4748     case 'w': // Floating point and SIMD registers (V0-V31)
4749       Info.setAllowsRegister();
4750       return true;
4751     case 'I': // Constant that can be used with an ADD instruction
4752     case 'J': // Constant that can be used with a SUB instruction
4753     case 'K': // Constant that can be used with a 32-bit logical instruction
4754     case 'L': // Constant that can be used with a 64-bit logical instruction
4755     case 'M': // Constant that can be used as a 32-bit MOV immediate
4756     case 'N': // Constant that can be used as a 64-bit MOV immediate
4757     case 'Y': // Floating point constant zero
4758     case 'Z': // Integer constant zero
4759       return true;
4760     case 'Q': // A memory reference with base register and no offset
4761       Info.setAllowsMemory();
4762       return true;
4763     case 'S': // A symbolic address
4764       Info.setAllowsRegister();
4765       return true;
4766     case 'U':
4767       // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
4768       // Utf: A memory address suitable for ldp/stp in TF mode.
4769       // Usa: An absolute symbolic address.
4770       // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
4771       llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
4772     case 'z': // Zero register, wzr or xzr
4773       Info.setAllowsRegister();
4774       return true;
4775     case 'x': // Floating point and SIMD registers (V0-V15)
4776       Info.setAllowsRegister();
4777       return true;
4778     }
4779     return false;
4780   }
4781 
4782   bool
4783   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4784                              std::string &SuggestedModifier) const override {
4785     // Strip off constraint modifiers.
4786     while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
4787       Constraint = Constraint.substr(1);
4788 
4789     switch (Constraint[0]) {
4790     default:
4791       return true;
4792     case 'z':
4793     case 'r': {
4794       switch (Modifier) {
4795       case 'x':
4796       case 'w':
4797         // For now assume that the person knows what they're
4798         // doing with the modifier.
4799         return true;
4800       default:
4801         // By default an 'r' constraint will be in the 'x'
4802         // registers.
4803         if (Size == 64)
4804           return true;
4805 
4806         SuggestedModifier = "w";
4807         return false;
4808       }
4809     }
4810     }
4811   }
4812 
4813   const char *getClobbers() const override { return ""; }
4814 
4815   int getEHDataRegisterNumber(unsigned RegNo) const override {
4816     if (RegNo == 0)
4817       return 0;
4818     if (RegNo == 1)
4819       return 1;
4820     return -1;
4821   }
4822 };
4823 
4824 const char *const AArch64TargetInfo::GCCRegNames[] = {
4825   // 32-bit Integer registers
4826   "w0",  "w1",  "w2",  "w3",  "w4",  "w5",  "w6",  "w7",  "w8",  "w9",  "w10",
4827   "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
4828   "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
4829 
4830   // 64-bit Integer registers
4831   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",  "x8",  "x9",  "x10",
4832   "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
4833   "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp",  "lr",  "sp",
4834 
4835   // 32-bit floating point regsisters
4836   "s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",  "s8",  "s9",  "s10",
4837   "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
4838   "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4839 
4840   // 64-bit floating point regsisters
4841   "d0",  "d1",  "d2",  "d3",  "d4",  "d5",  "d6",  "d7",  "d8",  "d9",  "d10",
4842   "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
4843   "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4844 
4845   // Vector registers
4846   "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",  "v8",  "v9",  "v10",
4847   "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
4848   "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
4849 };
4850 
4851 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
4852                                      unsigned &NumNames) const {
4853   Names = GCCRegNames;
4854   NumNames = llvm::array_lengthof(GCCRegNames);
4855 }
4856 
4857 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
4858   { { "w31" }, "wsp" },
4859   { { "x29" }, "fp" },
4860   { { "x30" }, "lr" },
4861   { { "x31" }, "sp" },
4862   // The S/D/Q and W/X registers overlap, but aren't really aliases; we
4863   // don't want to substitute one of these for a different-sized one.
4864 };
4865 
4866 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4867                                        unsigned &NumAliases) const {
4868   Aliases = GCCRegAliases;
4869   NumAliases = llvm::array_lengthof(GCCRegAliases);
4870 }
4871 
4872 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
4873 #define BUILTIN(ID, TYPE, ATTRS)                                               \
4874   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4875 #include "clang/Basic/BuiltinsNEON.def"
4876 
4877 #define BUILTIN(ID, TYPE, ATTRS)                                               \
4878   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4879 #include "clang/Basic/BuiltinsAArch64.def"
4880 };
4881 
4882 class AArch64leTargetInfo : public AArch64TargetInfo {
4883   void setDescriptionString() override {
4884     if (getTriple().isOSBinFormatMachO())
4885       DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
4886     else
4887       DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
4888   }
4889 
4890 public:
4891   AArch64leTargetInfo(const llvm::Triple &Triple)
4892     : AArch64TargetInfo(Triple) {
4893     BigEndian = false;
4894     }
4895   void getTargetDefines(const LangOptions &Opts,
4896                         MacroBuilder &Builder) const override {
4897     Builder.defineMacro("__AARCH64EL__");
4898     AArch64TargetInfo::getTargetDefines(Opts, Builder);
4899   }
4900 };
4901 
4902 class AArch64beTargetInfo : public AArch64TargetInfo {
4903   void setDescriptionString() override {
4904     assert(!getTriple().isOSBinFormatMachO());
4905     DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
4906   }
4907 
4908 public:
4909   AArch64beTargetInfo(const llvm::Triple &Triple)
4910     : AArch64TargetInfo(Triple) { }
4911   void getTargetDefines(const LangOptions &Opts,
4912                         MacroBuilder &Builder) const override {
4913     Builder.defineMacro("__AARCH64EB__");
4914     Builder.defineMacro("__AARCH_BIG_ENDIAN");
4915     Builder.defineMacro("__ARM_BIG_ENDIAN");
4916     AArch64TargetInfo::getTargetDefines(Opts, Builder);
4917   }
4918 };
4919 } // end anonymous namespace.
4920 
4921 namespace {
4922 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
4923 protected:
4924   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4925                     MacroBuilder &Builder) const override {
4926     Builder.defineMacro("__AARCH64_SIMD__");
4927     Builder.defineMacro("__ARM64_ARCH_8__");
4928     Builder.defineMacro("__ARM_NEON__");
4929     Builder.defineMacro("__LITTLE_ENDIAN__");
4930     Builder.defineMacro("__REGISTER_PREFIX__", "");
4931     Builder.defineMacro("__arm64", "1");
4932     Builder.defineMacro("__arm64__", "1");
4933 
4934     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4935   }
4936 
4937 public:
4938   DarwinAArch64TargetInfo(const llvm::Triple &Triple)
4939       : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
4940     Int64Type = SignedLongLong;
4941     WCharType = SignedInt;
4942     UseSignedCharForObjCBool = false;
4943 
4944     LongDoubleWidth = LongDoubleAlign = 64;
4945     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4946 
4947     TheCXXABI.set(TargetCXXABI::iOS64);
4948   }
4949 
4950   BuiltinVaListKind getBuiltinVaListKind() const override {
4951     return TargetInfo::CharPtrBuiltinVaList;
4952   }
4953 };
4954 } // end anonymous namespace
4955 
4956 namespace {
4957 // Hexagon abstract base class
4958 class HexagonTargetInfo : public TargetInfo {
4959   static const Builtin::Info BuiltinInfo[];
4960   static const char * const GCCRegNames[];
4961   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4962   std::string CPU;
4963 public:
4964   HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4965     BigEndian = false;
4966     DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
4967 
4968     // {} in inline assembly are packet specifiers, not assembly variant
4969     // specifiers.
4970     NoAsmVariants = true;
4971   }
4972 
4973   void getTargetBuiltins(const Builtin::Info *&Records,
4974                          unsigned &NumRecords) const override {
4975     Records = BuiltinInfo;
4976     NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
4977   }
4978 
4979   bool validateAsmConstraint(const char *&Name,
4980                              TargetInfo::ConstraintInfo &Info) const override {
4981     return true;
4982   }
4983 
4984   void getTargetDefines(const LangOptions &Opts,
4985                         MacroBuilder &Builder) const override;
4986 
4987   bool hasFeature(StringRef Feature) const override {
4988     return Feature == "hexagon";
4989   }
4990 
4991   BuiltinVaListKind getBuiltinVaListKind() const override {
4992     return TargetInfo::CharPtrBuiltinVaList;
4993   }
4994   void getGCCRegNames(const char * const *&Names,
4995                       unsigned &NumNames) const override;
4996   void getGCCRegAliases(const GCCRegAlias *&Aliases,
4997                         unsigned &NumAliases) const override;
4998   const char *getClobbers() const override {
4999     return "";
5000   }
5001 
5002   static const char *getHexagonCPUSuffix(StringRef Name) {
5003     return llvm::StringSwitch<const char*>(Name)
5004       .Case("hexagonv4", "4")
5005       .Case("hexagonv5", "5")
5006       .Default(nullptr);
5007   }
5008 
5009   bool setCPU(const std::string &Name) override {
5010     if (!getHexagonCPUSuffix(Name))
5011       return false;
5012 
5013     CPU = Name;
5014     return true;
5015   }
5016 };
5017 
5018 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5019                                 MacroBuilder &Builder) const {
5020   Builder.defineMacro("qdsp6");
5021   Builder.defineMacro("__qdsp6", "1");
5022   Builder.defineMacro("__qdsp6__", "1");
5023 
5024   Builder.defineMacro("hexagon");
5025   Builder.defineMacro("__hexagon", "1");
5026   Builder.defineMacro("__hexagon__", "1");
5027 
5028   if(CPU == "hexagonv1") {
5029     Builder.defineMacro("__HEXAGON_V1__");
5030     Builder.defineMacro("__HEXAGON_ARCH__", "1");
5031     if(Opts.HexagonQdsp6Compat) {
5032       Builder.defineMacro("__QDSP6_V1__");
5033       Builder.defineMacro("__QDSP6_ARCH__", "1");
5034     }
5035   }
5036   else if(CPU == "hexagonv2") {
5037     Builder.defineMacro("__HEXAGON_V2__");
5038     Builder.defineMacro("__HEXAGON_ARCH__", "2");
5039     if(Opts.HexagonQdsp6Compat) {
5040       Builder.defineMacro("__QDSP6_V2__");
5041       Builder.defineMacro("__QDSP6_ARCH__", "2");
5042     }
5043   }
5044   else if(CPU == "hexagonv3") {
5045     Builder.defineMacro("__HEXAGON_V3__");
5046     Builder.defineMacro("__HEXAGON_ARCH__", "3");
5047     if(Opts.HexagonQdsp6Compat) {
5048       Builder.defineMacro("__QDSP6_V3__");
5049       Builder.defineMacro("__QDSP6_ARCH__", "3");
5050     }
5051   }
5052   else if(CPU == "hexagonv4") {
5053     Builder.defineMacro("__HEXAGON_V4__");
5054     Builder.defineMacro("__HEXAGON_ARCH__", "4");
5055     if(Opts.HexagonQdsp6Compat) {
5056       Builder.defineMacro("__QDSP6_V4__");
5057       Builder.defineMacro("__QDSP6_ARCH__", "4");
5058     }
5059   }
5060   else if(CPU == "hexagonv5") {
5061     Builder.defineMacro("__HEXAGON_V5__");
5062     Builder.defineMacro("__HEXAGON_ARCH__", "5");
5063     if(Opts.HexagonQdsp6Compat) {
5064       Builder.defineMacro("__QDSP6_V5__");
5065       Builder.defineMacro("__QDSP6_ARCH__", "5");
5066     }
5067   }
5068 }
5069 
5070 const char * const HexagonTargetInfo::GCCRegNames[] = {
5071   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5072   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5073   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5074   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5075   "p0", "p1", "p2", "p3",
5076   "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5077 };
5078 
5079 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5080                                    unsigned &NumNames) const {
5081   Names = GCCRegNames;
5082   NumNames = llvm::array_lengthof(GCCRegNames);
5083 }
5084 
5085 
5086 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5087   { { "sp" }, "r29" },
5088   { { "fp" }, "r30" },
5089   { { "lr" }, "r31" },
5090  };
5091 
5092 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5093                                      unsigned &NumAliases) const {
5094   Aliases = GCCRegAliases;
5095   NumAliases = llvm::array_lengthof(GCCRegAliases);
5096 }
5097 
5098 
5099 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5100 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5101 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5102                                               ALL_LANGUAGES },
5103 #include "clang/Basic/BuiltinsHexagon.def"
5104 };
5105 }
5106 
5107 
5108 namespace {
5109 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5110 class SparcTargetInfo : public TargetInfo {
5111   static const TargetInfo::GCCRegAlias GCCRegAliases[];
5112   static const char * const GCCRegNames[];
5113   bool SoftFloat;
5114 public:
5115   SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
5116 
5117   bool handleTargetFeatures(std::vector<std::string> &Features,
5118                             DiagnosticsEngine &Diags) override {
5119     SoftFloat = false;
5120     for (unsigned i = 0, e = Features.size(); i != e; ++i)
5121       if (Features[i] == "+soft-float")
5122         SoftFloat = true;
5123     return true;
5124   }
5125   void getTargetDefines(const LangOptions &Opts,
5126                         MacroBuilder &Builder) const override {
5127     DefineStd(Builder, "sparc", Opts);
5128     Builder.defineMacro("__REGISTER_PREFIX__", "");
5129 
5130     if (SoftFloat)
5131       Builder.defineMacro("SOFT_FLOAT", "1");
5132   }
5133 
5134   bool hasFeature(StringRef Feature) const override {
5135     return llvm::StringSwitch<bool>(Feature)
5136              .Case("softfloat", SoftFloat)
5137              .Case("sparc", true)
5138              .Default(false);
5139   }
5140 
5141   void getTargetBuiltins(const Builtin::Info *&Records,
5142                          unsigned &NumRecords) const override {
5143     // FIXME: Implement!
5144   }
5145   BuiltinVaListKind getBuiltinVaListKind() const override {
5146     return TargetInfo::VoidPtrBuiltinVaList;
5147   }
5148   void getGCCRegNames(const char * const *&Names,
5149                       unsigned &NumNames) const override;
5150   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5151                         unsigned &NumAliases) const override;
5152   bool validateAsmConstraint(const char *&Name,
5153                              TargetInfo::ConstraintInfo &info) const override {
5154     // FIXME: Implement!
5155     return false;
5156   }
5157   const char *getClobbers() const override {
5158     // FIXME: Implement!
5159     return "";
5160   }
5161 };
5162 
5163 const char * const SparcTargetInfo::GCCRegNames[] = {
5164   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5165   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5166   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5167   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5168 };
5169 
5170 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5171                                      unsigned &NumNames) const {
5172   Names = GCCRegNames;
5173   NumNames = llvm::array_lengthof(GCCRegNames);
5174 }
5175 
5176 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5177   { { "g0" }, "r0" },
5178   { { "g1" }, "r1" },
5179   { { "g2" }, "r2" },
5180   { { "g3" }, "r3" },
5181   { { "g4" }, "r4" },
5182   { { "g5" }, "r5" },
5183   { { "g6" }, "r6" },
5184   { { "g7" }, "r7" },
5185   { { "o0" }, "r8" },
5186   { { "o1" }, "r9" },
5187   { { "o2" }, "r10" },
5188   { { "o3" }, "r11" },
5189   { { "o4" }, "r12" },
5190   { { "o5" }, "r13" },
5191   { { "o6", "sp" }, "r14" },
5192   { { "o7" }, "r15" },
5193   { { "l0" }, "r16" },
5194   { { "l1" }, "r17" },
5195   { { "l2" }, "r18" },
5196   { { "l3" }, "r19" },
5197   { { "l4" }, "r20" },
5198   { { "l5" }, "r21" },
5199   { { "l6" }, "r22" },
5200   { { "l7" }, "r23" },
5201   { { "i0" }, "r24" },
5202   { { "i1" }, "r25" },
5203   { { "i2" }, "r26" },
5204   { { "i3" }, "r27" },
5205   { { "i4" }, "r28" },
5206   { { "i5" }, "r29" },
5207   { { "i6", "fp" }, "r30" },
5208   { { "i7" }, "r31" },
5209 };
5210 
5211 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5212                                        unsigned &NumAliases) const {
5213   Aliases = GCCRegAliases;
5214   NumAliases = llvm::array_lengthof(GCCRegAliases);
5215 }
5216 
5217 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5218 class SparcV8TargetInfo : public SparcTargetInfo {
5219 public:
5220   SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5221     DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5222   }
5223 
5224   void getTargetDefines(const LangOptions &Opts,
5225                         MacroBuilder &Builder) const override {
5226     SparcTargetInfo::getTargetDefines(Opts, Builder);
5227     Builder.defineMacro("__sparcv8");
5228   }
5229 };
5230 
5231 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5232 class SparcV9TargetInfo : public SparcTargetInfo {
5233 public:
5234   SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5235     // FIXME: Support Sparc quad-precision long double?
5236     DescriptionString = "E-m:e-i64:64-n32:64-S128";
5237     // This is an LP64 platform.
5238     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5239 
5240     // OpenBSD uses long long for int64_t and intmax_t.
5241     if (getTriple().getOS() == llvm::Triple::OpenBSD)
5242       IntMaxType = SignedLongLong;
5243     else
5244       IntMaxType = SignedLong;
5245     Int64Type = IntMaxType;
5246 
5247     // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5248     // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5249     LongDoubleWidth = 128;
5250     LongDoubleAlign = 128;
5251     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5252     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5253   }
5254 
5255   void getTargetDefines(const LangOptions &Opts,
5256                         MacroBuilder &Builder) const override {
5257     SparcTargetInfo::getTargetDefines(Opts, Builder);
5258     Builder.defineMacro("__sparcv9");
5259     Builder.defineMacro("__arch64__");
5260     // Solaris doesn't need these variants, but the BSDs do.
5261     if (getTriple().getOS() != llvm::Triple::Solaris) {
5262       Builder.defineMacro("__sparc64__");
5263       Builder.defineMacro("__sparc_v9__");
5264       Builder.defineMacro("__sparcv9__");
5265     }
5266   }
5267 
5268   bool setCPU(const std::string &Name) override {
5269     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5270       .Case("v9", true)
5271       .Case("ultrasparc", true)
5272       .Case("ultrasparc3", true)
5273       .Case("niagara", true)
5274       .Case("niagara2", true)
5275       .Case("niagara3", true)
5276       .Case("niagara4", true)
5277       .Default(false);
5278 
5279     // No need to store the CPU yet.  There aren't any CPU-specific
5280     // macros to define.
5281     return CPUKnown;
5282   }
5283 };
5284 
5285 } // end anonymous namespace.
5286 
5287 namespace {
5288 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
5289 public:
5290   SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
5291       : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
5292     SizeType = UnsignedInt;
5293     PtrDiffType = SignedInt;
5294   }
5295 };
5296 } // end anonymous namespace.
5297 
5298 namespace {
5299 class SystemZTargetInfo : public TargetInfo {
5300   static const char *const GCCRegNames[];
5301 
5302 public:
5303   SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5304     TLSSupported = true;
5305     IntWidth = IntAlign = 32;
5306     LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5307     PointerWidth = PointerAlign = 64;
5308     LongDoubleWidth = 128;
5309     LongDoubleAlign = 64;
5310     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5311     MinGlobalAlign = 16;
5312     DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5313     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5314   }
5315   void getTargetDefines(const LangOptions &Opts,
5316                         MacroBuilder &Builder) const override {
5317     Builder.defineMacro("__s390__");
5318     Builder.defineMacro("__s390x__");
5319     Builder.defineMacro("__zarch__");
5320     Builder.defineMacro("__LONG_DOUBLE_128__");
5321   }
5322   void getTargetBuiltins(const Builtin::Info *&Records,
5323                          unsigned &NumRecords) const override {
5324     // FIXME: Implement.
5325     Records = nullptr;
5326     NumRecords = 0;
5327   }
5328 
5329   void getGCCRegNames(const char *const *&Names,
5330                       unsigned &NumNames) const override;
5331   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5332                         unsigned &NumAliases) const override {
5333     // No aliases.
5334     Aliases = nullptr;
5335     NumAliases = 0;
5336   }
5337   bool validateAsmConstraint(const char *&Name,
5338                              TargetInfo::ConstraintInfo &info) const override;
5339   const char *getClobbers() const override {
5340     // FIXME: Is this really right?
5341     return "";
5342   }
5343   BuiltinVaListKind getBuiltinVaListKind() const override {
5344     return TargetInfo::SystemZBuiltinVaList;
5345   }
5346   bool setCPU(const std::string &Name) override {
5347     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5348       .Case("z10", true)
5349       .Case("z196", true)
5350       .Case("zEC12", true)
5351       .Default(false);
5352 
5353     // No need to store the CPU yet.  There aren't any CPU-specific
5354     // macros to define.
5355     return CPUKnown;
5356   }
5357 };
5358 
5359 const char *const SystemZTargetInfo::GCCRegNames[] = {
5360   "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
5361   "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
5362   "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
5363   "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
5364 };
5365 
5366 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5367                                        unsigned &NumNames) const {
5368   Names = GCCRegNames;
5369   NumNames = llvm::array_lengthof(GCCRegNames);
5370 }
5371 
5372 bool SystemZTargetInfo::
5373 validateAsmConstraint(const char *&Name,
5374                       TargetInfo::ConstraintInfo &Info) const {
5375   switch (*Name) {
5376   default:
5377     return false;
5378 
5379   case 'a': // Address register
5380   case 'd': // Data register (equivalent to 'r')
5381   case 'f': // Floating-point register
5382     Info.setAllowsRegister();
5383     return true;
5384 
5385   case 'I': // Unsigned 8-bit constant
5386   case 'J': // Unsigned 12-bit constant
5387   case 'K': // Signed 16-bit constant
5388   case 'L': // Signed 20-bit displacement (on all targets we support)
5389   case 'M': // 0x7fffffff
5390     return true;
5391 
5392   case 'Q': // Memory with base and unsigned 12-bit displacement
5393   case 'R': // Likewise, plus an index
5394   case 'S': // Memory with base and signed 20-bit displacement
5395   case 'T': // Likewise, plus an index
5396     Info.setAllowsMemory();
5397     return true;
5398   }
5399 }
5400 }
5401 
5402 namespace {
5403   class MSP430TargetInfo : public TargetInfo {
5404     static const char * const GCCRegNames[];
5405   public:
5406     MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5407       BigEndian = false;
5408       TLSSupported = false;
5409       IntWidth = 16; IntAlign = 16;
5410       LongWidth = 32; LongLongWidth = 64;
5411       LongAlign = LongLongAlign = 16;
5412       PointerWidth = 16; PointerAlign = 16;
5413       SuitableAlign = 16;
5414       SizeType = UnsignedInt;
5415       IntMaxType = SignedLongLong;
5416       IntPtrType = SignedInt;
5417       PtrDiffType = SignedInt;
5418       SigAtomicType = SignedLong;
5419       DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5420     }
5421     void getTargetDefines(const LangOptions &Opts,
5422                           MacroBuilder &Builder) const override {
5423       Builder.defineMacro("MSP430");
5424       Builder.defineMacro("__MSP430__");
5425       // FIXME: defines for different 'flavours' of MCU
5426     }
5427     void getTargetBuiltins(const Builtin::Info *&Records,
5428                            unsigned &NumRecords) const override {
5429       // FIXME: Implement.
5430       Records = nullptr;
5431       NumRecords = 0;
5432     }
5433     bool hasFeature(StringRef Feature) const override {
5434       return Feature == "msp430";
5435     }
5436     void getGCCRegNames(const char * const *&Names,
5437                         unsigned &NumNames) const override;
5438     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5439                           unsigned &NumAliases) const override {
5440       // No aliases.
5441       Aliases = nullptr;
5442       NumAliases = 0;
5443     }
5444     bool
5445     validateAsmConstraint(const char *&Name,
5446                           TargetInfo::ConstraintInfo &info) const override {
5447       // No target constraints for now.
5448       return false;
5449     }
5450     const char *getClobbers() const override {
5451       // FIXME: Is this really right?
5452       return "";
5453     }
5454     BuiltinVaListKind getBuiltinVaListKind() const override {
5455       // FIXME: implement
5456       return TargetInfo::CharPtrBuiltinVaList;
5457    }
5458   };
5459 
5460   const char * const MSP430TargetInfo::GCCRegNames[] = {
5461     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5462     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5463   };
5464 
5465   void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5466                                         unsigned &NumNames) const {
5467     Names = GCCRegNames;
5468     NumNames = llvm::array_lengthof(GCCRegNames);
5469   }
5470 }
5471 
5472 namespace {
5473 
5474   // LLVM and Clang cannot be used directly to output native binaries for
5475   // target, but is used to compile C code to llvm bitcode with correct
5476   // type and alignment information.
5477   //
5478   // TCE uses the llvm bitcode as input and uses it for generating customized
5479   // target processor and program binary. TCE co-design environment is
5480   // publicly available in http://tce.cs.tut.fi
5481 
5482   static const unsigned TCEOpenCLAddrSpaceMap[] = {
5483       3, // opencl_global
5484       4, // opencl_local
5485       5, // opencl_constant
5486       // FIXME: generic has to be added to the target
5487       0, // opencl_generic
5488       0, // cuda_device
5489       0, // cuda_constant
5490       0  // cuda_shared
5491   };
5492 
5493   class TCETargetInfo : public TargetInfo{
5494   public:
5495     TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5496       TLSSupported = false;
5497       IntWidth = 32;
5498       LongWidth = LongLongWidth = 32;
5499       PointerWidth = 32;
5500       IntAlign = 32;
5501       LongAlign = LongLongAlign = 32;
5502       PointerAlign = 32;
5503       SuitableAlign = 32;
5504       SizeType = UnsignedInt;
5505       IntMaxType = SignedLong;
5506       IntPtrType = SignedInt;
5507       PtrDiffType = SignedInt;
5508       FloatWidth = 32;
5509       FloatAlign = 32;
5510       DoubleWidth = 32;
5511       DoubleAlign = 32;
5512       LongDoubleWidth = 32;
5513       LongDoubleAlign = 32;
5514       FloatFormat = &llvm::APFloat::IEEEsingle;
5515       DoubleFormat = &llvm::APFloat::IEEEsingle;
5516       LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5517       DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5518                           "-f64:32-v64:32-v128:32-a:0:32-n32";
5519       AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5520       UseAddrSpaceMapMangling = true;
5521     }
5522 
5523     void getTargetDefines(const LangOptions &Opts,
5524                           MacroBuilder &Builder) const override {
5525       DefineStd(Builder, "tce", Opts);
5526       Builder.defineMacro("__TCE__");
5527       Builder.defineMacro("__TCE_V1__");
5528     }
5529     bool hasFeature(StringRef Feature) const override {
5530       return Feature == "tce";
5531     }
5532 
5533     void getTargetBuiltins(const Builtin::Info *&Records,
5534                            unsigned &NumRecords) const override {}
5535     const char *getClobbers() const override {
5536       return "";
5537     }
5538     BuiltinVaListKind getBuiltinVaListKind() const override {
5539       return TargetInfo::VoidPtrBuiltinVaList;
5540     }
5541     void getGCCRegNames(const char * const *&Names,
5542                         unsigned &NumNames) const override {}
5543     bool validateAsmConstraint(const char *&Name,
5544                                TargetInfo::ConstraintInfo &info) const override{
5545       return true;
5546     }
5547     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5548                           unsigned &NumAliases) const override {}
5549   };
5550 }
5551 
5552 namespace {
5553 class MipsTargetInfoBase : public TargetInfo {
5554   virtual void setDescriptionString() = 0;
5555 
5556   static const Builtin::Info BuiltinInfo[];
5557   std::string CPU;
5558   bool IsMips16;
5559   bool IsMicromips;
5560   bool IsNan2008;
5561   bool IsSingleFloat;
5562   enum MipsFloatABI {
5563     HardFloat, SoftFloat
5564   } FloatABI;
5565   enum DspRevEnum {
5566     NoDSP, DSP1, DSP2
5567   } DspRev;
5568   bool HasMSA;
5569 
5570 protected:
5571   bool HasFP64;
5572   std::string ABI;
5573 
5574 public:
5575   MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5576                      const std::string &CPUStr)
5577       : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5578         IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
5579         DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {}
5580 
5581   bool isNaN2008Default() const {
5582     return CPU == "mips32r6" || CPU == "mips64r6";
5583   }
5584 
5585   bool isFP64Default() const {
5586     return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
5587   }
5588 
5589   StringRef getABI() const override { return ABI; }
5590   bool setCPU(const std::string &Name) override {
5591     bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
5592                     getTriple().getArch() == llvm::Triple::mipsel;
5593     CPU = Name;
5594     return llvm::StringSwitch<bool>(Name)
5595         .Case("mips1", IsMips32)
5596         .Case("mips2", IsMips32)
5597         .Case("mips3", true)
5598         .Case("mips4", true)
5599         .Case("mips5", true)
5600         .Case("mips32", IsMips32)
5601         .Case("mips32r2", IsMips32)
5602         .Case("mips32r6", IsMips32)
5603         .Case("mips64", true)
5604         .Case("mips64r2", true)
5605         .Case("mips64r6", true)
5606         .Case("octeon", true)
5607         .Default(false);
5608   }
5609   const std::string& getCPU() const { return CPU; }
5610   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5611     // The backend enables certain ABI's by default according to the
5612     // architecture.
5613     // Disable both possible defaults so that we don't end up with multiple
5614     // ABI's selected and trigger an assertion.
5615     Features["o32"] = false;
5616     Features["n64"] = false;
5617 
5618     Features[ABI] = true;
5619     if (CPU == "octeon")
5620       Features["mips64r2"] = Features["cnmips"] = true;
5621     else
5622       Features[CPU] = true;
5623   }
5624 
5625   void getTargetDefines(const LangOptions &Opts,
5626                         MacroBuilder &Builder) const override {
5627     Builder.defineMacro("__mips__");
5628     Builder.defineMacro("_mips");
5629     if (Opts.GNUMode)
5630       Builder.defineMacro("mips");
5631 
5632     Builder.defineMacro("__REGISTER_PREFIX__", "");
5633 
5634     switch (FloatABI) {
5635     case HardFloat:
5636       Builder.defineMacro("__mips_hard_float", Twine(1));
5637       break;
5638     case SoftFloat:
5639       Builder.defineMacro("__mips_soft_float", Twine(1));
5640       break;
5641     }
5642 
5643     if (IsSingleFloat)
5644       Builder.defineMacro("__mips_single_float", Twine(1));
5645 
5646     Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
5647     Builder.defineMacro("_MIPS_FPSET",
5648                         Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
5649 
5650     if (IsMips16)
5651       Builder.defineMacro("__mips16", Twine(1));
5652 
5653     if (IsMicromips)
5654       Builder.defineMacro("__mips_micromips", Twine(1));
5655 
5656     if (IsNan2008)
5657       Builder.defineMacro("__mips_nan2008", Twine(1));
5658 
5659     switch (DspRev) {
5660     default:
5661       break;
5662     case DSP1:
5663       Builder.defineMacro("__mips_dsp_rev", Twine(1));
5664       Builder.defineMacro("__mips_dsp", Twine(1));
5665       break;
5666     case DSP2:
5667       Builder.defineMacro("__mips_dsp_rev", Twine(2));
5668       Builder.defineMacro("__mips_dspr2", Twine(1));
5669       Builder.defineMacro("__mips_dsp", Twine(1));
5670       break;
5671     }
5672 
5673     if (HasMSA)
5674       Builder.defineMacro("__mips_msa", Twine(1));
5675 
5676     Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
5677     Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
5678     Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
5679 
5680     Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
5681     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
5682   }
5683 
5684   void getTargetBuiltins(const Builtin::Info *&Records,
5685                          unsigned &NumRecords) const override {
5686     Records = BuiltinInfo;
5687     NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
5688   }
5689   bool hasFeature(StringRef Feature) const override {
5690     return llvm::StringSwitch<bool>(Feature)
5691       .Case("mips", true)
5692       .Case("fp64", HasFP64)
5693       .Default(false);
5694   }
5695   BuiltinVaListKind getBuiltinVaListKind() const override {
5696     return TargetInfo::VoidPtrBuiltinVaList;
5697   }
5698   void getGCCRegNames(const char * const *&Names,
5699                       unsigned &NumNames) const override {
5700     static const char *const GCCRegNames[] = {
5701       // CPU register names
5702       // Must match second column of GCCRegAliases
5703       "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
5704       "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
5705       "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
5706       "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
5707       // Floating point register names
5708       "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
5709       "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
5710       "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
5711       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
5712       // Hi/lo and condition register names
5713       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
5714       "$fcc5","$fcc6","$fcc7",
5715       // MSA register names
5716       "$w0",  "$w1",  "$w2",  "$w3",  "$w4",  "$w5",  "$w6",  "$w7",
5717       "$w8",  "$w9",  "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
5718       "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
5719       "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
5720       // MSA control register names
5721       "$msair",      "$msacsr", "$msaaccess", "$msasave", "$msamodify",
5722       "$msarequest", "$msamap", "$msaunmap"
5723     };
5724     Names = GCCRegNames;
5725     NumNames = llvm::array_lengthof(GCCRegNames);
5726   }
5727   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5728                         unsigned &NumAliases) const override = 0;
5729   bool validateAsmConstraint(const char *&Name,
5730                              TargetInfo::ConstraintInfo &Info) const override {
5731     switch (*Name) {
5732     default:
5733       return false;
5734     case 'r': // CPU registers.
5735     case 'd': // Equivalent to "r" unless generating MIPS16 code.
5736     case 'y': // Equivalent to "r", backward compatibility only.
5737     case 'f': // floating-point registers.
5738     case 'c': // $25 for indirect jumps
5739     case 'l': // lo register
5740     case 'x': // hilo register pair
5741       Info.setAllowsRegister();
5742       return true;
5743     case 'R': // An address that can be used in a non-macro load or store
5744       Info.setAllowsMemory();
5745       return true;
5746     }
5747   }
5748 
5749   const char *getClobbers() const override {
5750     return "~{$1}";
5751   }
5752 
5753   bool handleTargetFeatures(std::vector<std::string> &Features,
5754                             DiagnosticsEngine &Diags) override {
5755     IsMips16 = false;
5756     IsMicromips = false;
5757     IsNan2008 = isNaN2008Default();
5758     IsSingleFloat = false;
5759     FloatABI = HardFloat;
5760     DspRev = NoDSP;
5761     HasFP64 = isFP64Default();
5762 
5763     for (std::vector<std::string>::iterator it = Features.begin(),
5764          ie = Features.end(); it != ie; ++it) {
5765       if (*it == "+single-float")
5766         IsSingleFloat = true;
5767       else if (*it == "+soft-float")
5768         FloatABI = SoftFloat;
5769       else if (*it == "+mips16")
5770         IsMips16 = true;
5771       else if (*it == "+micromips")
5772         IsMicromips = true;
5773       else if (*it == "+dsp")
5774         DspRev = std::max(DspRev, DSP1);
5775       else if (*it == "+dspr2")
5776         DspRev = std::max(DspRev, DSP2);
5777       else if (*it == "+msa")
5778         HasMSA = true;
5779       else if (*it == "+fp64")
5780         HasFP64 = true;
5781       else if (*it == "-fp64")
5782         HasFP64 = false;
5783       else if (*it == "+nan2008")
5784         IsNan2008 = true;
5785       else if (*it == "-nan2008")
5786         IsNan2008 = false;
5787     }
5788 
5789     // Remove front-end specific options.
5790     std::vector<std::string>::iterator it =
5791       std::find(Features.begin(), Features.end(), "+soft-float");
5792     if (it != Features.end())
5793       Features.erase(it);
5794 
5795     setDescriptionString();
5796 
5797     return true;
5798   }
5799 
5800   int getEHDataRegisterNumber(unsigned RegNo) const override {
5801     if (RegNo == 0) return 4;
5802     if (RegNo == 1) return 5;
5803     return -1;
5804   }
5805 
5806   bool isCLZForZeroUndef() const override { return false; }
5807 };
5808 
5809 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
5810 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5811 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5812                                               ALL_LANGUAGES },
5813 #include "clang/Basic/BuiltinsMips.def"
5814 };
5815 
5816 class Mips32TargetInfoBase : public MipsTargetInfoBase {
5817 public:
5818   Mips32TargetInfoBase(const llvm::Triple &Triple)
5819       : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
5820     SizeType = UnsignedInt;
5821     PtrDiffType = SignedInt;
5822     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
5823   }
5824   bool setABI(const std::string &Name) override {
5825     if (Name == "o32" || Name == "eabi") {
5826       ABI = Name;
5827       return true;
5828     }
5829     return false;
5830   }
5831   void getTargetDefines(const LangOptions &Opts,
5832                         MacroBuilder &Builder) const override {
5833     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5834 
5835     Builder.defineMacro("__mips", "32");
5836     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
5837 
5838     const std::string& CPUStr = getCPU();
5839     if (CPUStr == "mips32")
5840       Builder.defineMacro("__mips_isa_rev", "1");
5841     else if (CPUStr == "mips32r2")
5842       Builder.defineMacro("__mips_isa_rev", "2");
5843 
5844     if (ABI == "o32") {
5845       Builder.defineMacro("__mips_o32");
5846       Builder.defineMacro("_ABIO32", "1");
5847       Builder.defineMacro("_MIPS_SIM", "_ABIO32");
5848     }
5849     else if (ABI == "eabi")
5850       Builder.defineMacro("__mips_eabi");
5851     else
5852       llvm_unreachable("Invalid ABI for Mips32.");
5853   }
5854   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5855                         unsigned &NumAliases) const override {
5856     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5857       { { "at" },  "$1" },
5858       { { "v0" },  "$2" },
5859       { { "v1" },  "$3" },
5860       { { "a0" },  "$4" },
5861       { { "a1" },  "$5" },
5862       { { "a2" },  "$6" },
5863       { { "a3" },  "$7" },
5864       { { "t0" },  "$8" },
5865       { { "t1" },  "$9" },
5866       { { "t2" }, "$10" },
5867       { { "t3" }, "$11" },
5868       { { "t4" }, "$12" },
5869       { { "t5" }, "$13" },
5870       { { "t6" }, "$14" },
5871       { { "t7" }, "$15" },
5872       { { "s0" }, "$16" },
5873       { { "s1" }, "$17" },
5874       { { "s2" }, "$18" },
5875       { { "s3" }, "$19" },
5876       { { "s4" }, "$20" },
5877       { { "s5" }, "$21" },
5878       { { "s6" }, "$22" },
5879       { { "s7" }, "$23" },
5880       { { "t8" }, "$24" },
5881       { { "t9" }, "$25" },
5882       { { "k0" }, "$26" },
5883       { { "k1" }, "$27" },
5884       { { "gp" }, "$28" },
5885       { { "sp","$sp" }, "$29" },
5886       { { "fp","$fp" }, "$30" },
5887       { { "ra" }, "$31" }
5888     };
5889     Aliases = GCCRegAliases;
5890     NumAliases = llvm::array_lengthof(GCCRegAliases);
5891   }
5892 };
5893 
5894 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
5895   void setDescriptionString() override {
5896     DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
5897   }
5898 
5899 public:
5900   Mips32EBTargetInfo(const llvm::Triple &Triple)
5901       : Mips32TargetInfoBase(Triple) {
5902   }
5903   void getTargetDefines(const LangOptions &Opts,
5904                         MacroBuilder &Builder) const override {
5905     DefineStd(Builder, "MIPSEB", Opts);
5906     Builder.defineMacro("_MIPSEB");
5907     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5908   }
5909 };
5910 
5911 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
5912   void setDescriptionString() override {
5913     DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
5914   }
5915 
5916 public:
5917   Mips32ELTargetInfo(const llvm::Triple &Triple)
5918       : Mips32TargetInfoBase(Triple) {
5919     BigEndian = false;
5920   }
5921   void getTargetDefines(const LangOptions &Opts,
5922                         MacroBuilder &Builder) const override {
5923     DefineStd(Builder, "MIPSEL", Opts);
5924     Builder.defineMacro("_MIPSEL");
5925     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5926   }
5927 };
5928 
5929 class Mips64TargetInfoBase : public MipsTargetInfoBase {
5930 public:
5931   Mips64TargetInfoBase(const llvm::Triple &Triple)
5932       : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
5933     LongDoubleWidth = LongDoubleAlign = 128;
5934     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5935     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
5936       LongDoubleWidth = LongDoubleAlign = 64;
5937       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5938     }
5939     setN64ABITypes();
5940     SuitableAlign = 128;
5941     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5942   }
5943 
5944   void setN64ABITypes() {
5945     LongWidth = LongAlign = 64;
5946     PointerWidth = PointerAlign = 64;
5947     SizeType = UnsignedLong;
5948     PtrDiffType = SignedLong;
5949   }
5950 
5951   void setN32ABITypes() {
5952     LongWidth = LongAlign = 32;
5953     PointerWidth = PointerAlign = 32;
5954     SizeType = UnsignedInt;
5955     PtrDiffType = SignedInt;
5956   }
5957 
5958   bool setABI(const std::string &Name) override {
5959     if (Name == "n32") {
5960       setN32ABITypes();
5961       ABI = Name;
5962       return true;
5963     }
5964     if (Name == "n64") {
5965       setN64ABITypes();
5966       ABI = Name;
5967       return true;
5968     }
5969     return false;
5970   }
5971 
5972   void getTargetDefines(const LangOptions &Opts,
5973                         MacroBuilder &Builder) const override {
5974     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5975 
5976     Builder.defineMacro("__mips", "64");
5977     Builder.defineMacro("__mips64");
5978     Builder.defineMacro("__mips64__");
5979     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
5980 
5981     const std::string& CPUStr = getCPU();
5982     if (CPUStr == "mips64")
5983       Builder.defineMacro("__mips_isa_rev", "1");
5984     else if (CPUStr == "mips64r2")
5985       Builder.defineMacro("__mips_isa_rev", "2");
5986 
5987     if (ABI == "n32") {
5988       Builder.defineMacro("__mips_n32");
5989       Builder.defineMacro("_ABIN32", "2");
5990       Builder.defineMacro("_MIPS_SIM", "_ABIN32");
5991     }
5992     else if (ABI == "n64") {
5993       Builder.defineMacro("__mips_n64");
5994       Builder.defineMacro("_ABI64", "3");
5995       Builder.defineMacro("_MIPS_SIM", "_ABI64");
5996     }
5997     else
5998       llvm_unreachable("Invalid ABI for Mips64.");
5999   }
6000   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6001                         unsigned &NumAliases) const override {
6002     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6003       { { "at" },  "$1" },
6004       { { "v0" },  "$2" },
6005       { { "v1" },  "$3" },
6006       { { "a0" },  "$4" },
6007       { { "a1" },  "$5" },
6008       { { "a2" },  "$6" },
6009       { { "a3" },  "$7" },
6010       { { "a4" },  "$8" },
6011       { { "a5" },  "$9" },
6012       { { "a6" }, "$10" },
6013       { { "a7" }, "$11" },
6014       { { "t0" }, "$12" },
6015       { { "t1" }, "$13" },
6016       { { "t2" }, "$14" },
6017       { { "t3" }, "$15" },
6018       { { "s0" }, "$16" },
6019       { { "s1" }, "$17" },
6020       { { "s2" }, "$18" },
6021       { { "s3" }, "$19" },
6022       { { "s4" }, "$20" },
6023       { { "s5" }, "$21" },
6024       { { "s6" }, "$22" },
6025       { { "s7" }, "$23" },
6026       { { "t8" }, "$24" },
6027       { { "t9" }, "$25" },
6028       { { "k0" }, "$26" },
6029       { { "k1" }, "$27" },
6030       { { "gp" }, "$28" },
6031       { { "sp","$sp" }, "$29" },
6032       { { "fp","$fp" }, "$30" },
6033       { { "ra" }, "$31" }
6034     };
6035     Aliases = GCCRegAliases;
6036     NumAliases = llvm::array_lengthof(GCCRegAliases);
6037   }
6038 
6039   bool hasInt128Type() const override { return true; }
6040 };
6041 
6042 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
6043   void setDescriptionString() override {
6044     if (ABI == "n32")
6045       DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6046     else
6047       DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6048 
6049   }
6050 
6051 public:
6052   Mips64EBTargetInfo(const llvm::Triple &Triple)
6053       : Mips64TargetInfoBase(Triple) {}
6054   void getTargetDefines(const LangOptions &Opts,
6055                         MacroBuilder &Builder) const override {
6056     DefineStd(Builder, "MIPSEB", Opts);
6057     Builder.defineMacro("_MIPSEB");
6058     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6059   }
6060 };
6061 
6062 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
6063   void setDescriptionString() override {
6064     if (ABI == "n32")
6065       DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6066     else
6067       DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6068   }
6069 public:
6070   Mips64ELTargetInfo(const llvm::Triple &Triple)
6071       : Mips64TargetInfoBase(Triple) {
6072     // Default ABI is n64.
6073     BigEndian = false;
6074   }
6075   void getTargetDefines(const LangOptions &Opts,
6076                         MacroBuilder &Builder) const override {
6077     DefineStd(Builder, "MIPSEL", Opts);
6078     Builder.defineMacro("_MIPSEL");
6079     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6080   }
6081 };
6082 } // end anonymous namespace.
6083 
6084 namespace {
6085 class PNaClTargetInfo : public TargetInfo {
6086 public:
6087   PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6088     BigEndian = false;
6089     this->UserLabelPrefix = "";
6090     this->LongAlign = 32;
6091     this->LongWidth = 32;
6092     this->PointerAlign = 32;
6093     this->PointerWidth = 32;
6094     this->IntMaxType = TargetInfo::SignedLongLong;
6095     this->Int64Type = TargetInfo::SignedLongLong;
6096     this->DoubleAlign = 64;
6097     this->LongDoubleWidth = 64;
6098     this->LongDoubleAlign = 64;
6099     this->SizeType = TargetInfo::UnsignedInt;
6100     this->PtrDiffType = TargetInfo::SignedInt;
6101     this->IntPtrType = TargetInfo::SignedInt;
6102     this->RegParmMax = 0; // Disallow regparm
6103   }
6104 
6105   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6106   }
6107   void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6108     Builder.defineMacro("__le32__");
6109     Builder.defineMacro("__pnacl__");
6110   }
6111   void getTargetDefines(const LangOptions &Opts,
6112                         MacroBuilder &Builder) const override {
6113     getArchDefines(Opts, Builder);
6114   }
6115   bool hasFeature(StringRef Feature) const override {
6116     return Feature == "pnacl";
6117   }
6118   void getTargetBuiltins(const Builtin::Info *&Records,
6119                          unsigned &NumRecords) const override {
6120   }
6121   BuiltinVaListKind getBuiltinVaListKind() const override {
6122     return TargetInfo::PNaClABIBuiltinVaList;
6123   }
6124   void getGCCRegNames(const char * const *&Names,
6125                       unsigned &NumNames) const override;
6126   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6127                         unsigned &NumAliases) const override;
6128   bool validateAsmConstraint(const char *&Name,
6129                              TargetInfo::ConstraintInfo &Info) const override {
6130     return false;
6131   }
6132 
6133   const char *getClobbers() const override {
6134     return "";
6135   }
6136 };
6137 
6138 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6139                                      unsigned &NumNames) const {
6140   Names = nullptr;
6141   NumNames = 0;
6142 }
6143 
6144 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6145                                        unsigned &NumAliases) const {
6146   Aliases = nullptr;
6147   NumAliases = 0;
6148 }
6149 } // end anonymous namespace.
6150 
6151 namespace {
6152 class Le64TargetInfo : public TargetInfo {
6153   static const Builtin::Info BuiltinInfo[];
6154 
6155 public:
6156   Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6157     BigEndian = false;
6158     NoAsmVariants = true;
6159     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6160     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6161     DescriptionString =
6162         "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
6163   }
6164 
6165   void getTargetDefines(const LangOptions &Opts,
6166                         MacroBuilder &Builder) const override {
6167     DefineStd(Builder, "unix", Opts);
6168     defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6169     Builder.defineMacro("__ELF__");
6170   }
6171   void getTargetBuiltins(const Builtin::Info *&Records,
6172                          unsigned &NumRecords) const override {
6173     Records = BuiltinInfo;
6174     NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6175   }
6176   BuiltinVaListKind getBuiltinVaListKind() const override {
6177     return TargetInfo::PNaClABIBuiltinVaList;
6178   }
6179   const char *getClobbers() const override { return ""; }
6180   void getGCCRegNames(const char *const *&Names,
6181                       unsigned &NumNames) const override {
6182     Names = nullptr;
6183     NumNames = 0;
6184   }
6185   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6186                         unsigned &NumAliases) const override {
6187     Aliases = nullptr;
6188     NumAliases = 0;
6189   }
6190   bool validateAsmConstraint(const char *&Name,
6191                              TargetInfo::ConstraintInfo &Info) const override {
6192     return false;
6193   }
6194 
6195   bool hasProtectedVisibility() const override { return false; }
6196 };
6197 } // end anonymous namespace.
6198 
6199 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6200 #define BUILTIN(ID, TYPE, ATTRS)                                               \
6201   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6202 #include "clang/Basic/BuiltinsLe64.def"
6203 };
6204 
6205 namespace {
6206   static const unsigned SPIRAddrSpaceMap[] = {
6207     1,    // opencl_global
6208     3,    // opencl_local
6209     2,    // opencl_constant
6210     4,    // opencl_generic
6211     0,    // cuda_device
6212     0,    // cuda_constant
6213     0     // cuda_shared
6214   };
6215   class SPIRTargetInfo : public TargetInfo {
6216   public:
6217     SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6218       assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6219         "SPIR target must use unknown OS");
6220       assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6221         "SPIR target must use unknown environment type");
6222       BigEndian = false;
6223       TLSSupported = false;
6224       LongWidth = LongAlign = 64;
6225       AddrSpaceMap = &SPIRAddrSpaceMap;
6226       UseAddrSpaceMapMangling = true;
6227       // Define available target features
6228       // These must be defined in sorted order!
6229       NoAsmVariants = true;
6230     }
6231     void getTargetDefines(const LangOptions &Opts,
6232                           MacroBuilder &Builder) const override {
6233       DefineStd(Builder, "SPIR", Opts);
6234     }
6235     bool hasFeature(StringRef Feature) const override {
6236       return Feature == "spir";
6237     }
6238 
6239     void getTargetBuiltins(const Builtin::Info *&Records,
6240                            unsigned &NumRecords) const override {}
6241     const char *getClobbers() const override {
6242       return "";
6243     }
6244     void getGCCRegNames(const char * const *&Names,
6245                         unsigned &NumNames) const override {}
6246     bool
6247     validateAsmConstraint(const char *&Name,
6248                           TargetInfo::ConstraintInfo &info) const override {
6249       return true;
6250     }
6251     void getGCCRegAliases(const GCCRegAlias *&Aliases,
6252                           unsigned &NumAliases) const override {}
6253     BuiltinVaListKind getBuiltinVaListKind() const override {
6254       return TargetInfo::VoidPtrBuiltinVaList;
6255     }
6256   };
6257 
6258 
6259   class SPIR32TargetInfo : public SPIRTargetInfo {
6260   public:
6261     SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6262       PointerWidth = PointerAlign = 32;
6263       SizeType     = TargetInfo::UnsignedInt;
6264       PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6265       DescriptionString
6266         = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6267           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6268     }
6269     void getTargetDefines(const LangOptions &Opts,
6270                           MacroBuilder &Builder) const override {
6271       DefineStd(Builder, "SPIR32", Opts);
6272     }
6273   };
6274 
6275   class SPIR64TargetInfo : public SPIRTargetInfo {
6276   public:
6277     SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6278       PointerWidth = PointerAlign = 64;
6279       SizeType     = TargetInfo::UnsignedLong;
6280       PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6281       DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6282                           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6283     }
6284     void getTargetDefines(const LangOptions &Opts,
6285                           MacroBuilder &Builder) const override {
6286       DefineStd(Builder, "SPIR64", Opts);
6287     }
6288   };
6289 }
6290 
6291 namespace {
6292 class XCoreTargetInfo : public TargetInfo {
6293   static const Builtin::Info BuiltinInfo[];
6294 public:
6295   XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6296     BigEndian = false;
6297     NoAsmVariants = true;
6298     LongLongAlign = 32;
6299     SuitableAlign = 32;
6300     DoubleAlign = LongDoubleAlign = 32;
6301     SizeType = UnsignedInt;
6302     PtrDiffType = SignedInt;
6303     IntPtrType = SignedInt;
6304     WCharType = UnsignedChar;
6305     WIntType = UnsignedInt;
6306     UseZeroLengthBitfieldAlignment = true;
6307     DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6308                         "-f64:32-a:0:32-n32";
6309   }
6310   void getTargetDefines(const LangOptions &Opts,
6311                         MacroBuilder &Builder) const override {
6312     Builder.defineMacro("__XS1B__");
6313   }
6314   void getTargetBuiltins(const Builtin::Info *&Records,
6315                          unsigned &NumRecords) const override {
6316     Records = BuiltinInfo;
6317     NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6318   }
6319   BuiltinVaListKind getBuiltinVaListKind() const override {
6320     return TargetInfo::VoidPtrBuiltinVaList;
6321   }
6322   const char *getClobbers() const override {
6323     return "";
6324   }
6325   void getGCCRegNames(const char * const *&Names,
6326                       unsigned &NumNames) const override {
6327     static const char * const GCCRegNames[] = {
6328       "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
6329       "r8",   "r9",   "r10",  "r11",  "cp",   "dp",   "sp",   "lr"
6330     };
6331     Names = GCCRegNames;
6332     NumNames = llvm::array_lengthof(GCCRegNames);
6333   }
6334   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6335                         unsigned &NumAliases) const override {
6336     Aliases = nullptr;
6337     NumAliases = 0;
6338   }
6339   bool validateAsmConstraint(const char *&Name,
6340                              TargetInfo::ConstraintInfo &Info) const override {
6341     return false;
6342   }
6343   int getEHDataRegisterNumber(unsigned RegNo) const override {
6344     // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6345     return (RegNo < 2)? RegNo : -1;
6346   }
6347 };
6348 
6349 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6350 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6351 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6352                                               ALL_LANGUAGES },
6353 #include "clang/Basic/BuiltinsXCore.def"
6354 };
6355 } // end anonymous namespace.
6356 
6357 
6358 //===----------------------------------------------------------------------===//
6359 // Driver code
6360 //===----------------------------------------------------------------------===//
6361 
6362 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6363   llvm::Triple::OSType os = Triple.getOS();
6364 
6365   switch (Triple.getArch()) {
6366   default:
6367     return nullptr;
6368 
6369   case llvm::Triple::xcore:
6370     return new XCoreTargetInfo(Triple);
6371 
6372   case llvm::Triple::hexagon:
6373     return new HexagonTargetInfo(Triple);
6374 
6375   case llvm::Triple::aarch64:
6376     if (Triple.isOSDarwin())
6377       return new DarwinAArch64TargetInfo(Triple);
6378 
6379     switch (os) {
6380     case llvm::Triple::FreeBSD:
6381       return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
6382     case llvm::Triple::Linux:
6383       return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6384     case llvm::Triple::NetBSD:
6385       return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6386     default:
6387       return new AArch64leTargetInfo(Triple);
6388     }
6389 
6390   case llvm::Triple::aarch64_be:
6391     switch (os) {
6392     case llvm::Triple::FreeBSD:
6393       return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
6394     case llvm::Triple::Linux:
6395       return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6396     case llvm::Triple::NetBSD:
6397       return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6398     default:
6399       return new AArch64beTargetInfo(Triple);
6400     }
6401 
6402   case llvm::Triple::arm:
6403   case llvm::Triple::thumb:
6404     if (Triple.isOSBinFormatMachO())
6405       return new DarwinARMTargetInfo(Triple);
6406 
6407     switch (os) {
6408     case llvm::Triple::Linux:
6409       return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6410     case llvm::Triple::FreeBSD:
6411       return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6412     case llvm::Triple::NetBSD:
6413       return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6414     case llvm::Triple::OpenBSD:
6415       return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6416     case llvm::Triple::Bitrig:
6417       return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6418     case llvm::Triple::RTEMS:
6419       return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6420     case llvm::Triple::NaCl:
6421       return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6422     case llvm::Triple::Win32:
6423       switch (Triple.getEnvironment()) {
6424       default:
6425         return new ARMleTargetInfo(Triple);
6426       case llvm::Triple::Itanium:
6427         return new ItaniumWindowsARMleTargetInfo(Triple);
6428       case llvm::Triple::MSVC:
6429         return new MicrosoftARMleTargetInfo(Triple);
6430       }
6431     default:
6432       return new ARMleTargetInfo(Triple);
6433     }
6434 
6435   case llvm::Triple::armeb:
6436   case llvm::Triple::thumbeb:
6437     if (Triple.isOSDarwin())
6438       return new DarwinARMTargetInfo(Triple);
6439 
6440     switch (os) {
6441     case llvm::Triple::Linux:
6442       return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6443     case llvm::Triple::FreeBSD:
6444       return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6445     case llvm::Triple::NetBSD:
6446       return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6447     case llvm::Triple::OpenBSD:
6448       return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6449     case llvm::Triple::Bitrig:
6450       return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6451     case llvm::Triple::RTEMS:
6452       return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6453     case llvm::Triple::NaCl:
6454       return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6455     default:
6456       return new ARMbeTargetInfo(Triple);
6457     }
6458 
6459   case llvm::Triple::msp430:
6460     return new MSP430TargetInfo(Triple);
6461 
6462   case llvm::Triple::mips:
6463     switch (os) {
6464     case llvm::Triple::Linux:
6465       return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6466     case llvm::Triple::RTEMS:
6467       return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6468     case llvm::Triple::FreeBSD:
6469       return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6470     case llvm::Triple::NetBSD:
6471       return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6472     default:
6473       return new Mips32EBTargetInfo(Triple);
6474     }
6475 
6476   case llvm::Triple::mipsel:
6477     switch (os) {
6478     case llvm::Triple::Linux:
6479       return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6480     case llvm::Triple::RTEMS:
6481       return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6482     case llvm::Triple::FreeBSD:
6483       return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6484     case llvm::Triple::NetBSD:
6485       return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6486     case llvm::Triple::NaCl:
6487       return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6488     default:
6489       return new Mips32ELTargetInfo(Triple);
6490     }
6491 
6492   case llvm::Triple::mips64:
6493     switch (os) {
6494     case llvm::Triple::Linux:
6495       return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
6496     case llvm::Triple::RTEMS:
6497       return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
6498     case llvm::Triple::FreeBSD:
6499       return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6500     case llvm::Triple::NetBSD:
6501       return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6502     case llvm::Triple::OpenBSD:
6503       return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6504     default:
6505       return new Mips64EBTargetInfo(Triple);
6506     }
6507 
6508   case llvm::Triple::mips64el:
6509     switch (os) {
6510     case llvm::Triple::Linux:
6511       return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
6512     case llvm::Triple::RTEMS:
6513       return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
6514     case llvm::Triple::FreeBSD:
6515       return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6516     case llvm::Triple::NetBSD:
6517       return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6518     case llvm::Triple::OpenBSD:
6519       return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6520     default:
6521       return new Mips64ELTargetInfo(Triple);
6522     }
6523 
6524   case llvm::Triple::le32:
6525     switch (os) {
6526       case llvm::Triple::NaCl:
6527         return new NaClTargetInfo<PNaClTargetInfo>(Triple);
6528       default:
6529         return nullptr;
6530     }
6531 
6532   case llvm::Triple::le64:
6533     return new Le64TargetInfo(Triple);
6534 
6535   case llvm::Triple::ppc:
6536     if (Triple.isOSDarwin())
6537       return new DarwinPPC32TargetInfo(Triple);
6538     switch (os) {
6539     case llvm::Triple::Linux:
6540       return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
6541     case llvm::Triple::FreeBSD:
6542       return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
6543     case llvm::Triple::NetBSD:
6544       return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
6545     case llvm::Triple::OpenBSD:
6546       return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
6547     case llvm::Triple::RTEMS:
6548       return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
6549     default:
6550       return new PPC32TargetInfo(Triple);
6551     }
6552 
6553   case llvm::Triple::ppc64:
6554     if (Triple.isOSDarwin())
6555       return new DarwinPPC64TargetInfo(Triple);
6556     switch (os) {
6557     case llvm::Triple::Linux:
6558       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6559     case llvm::Triple::Lv2:
6560       return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
6561     case llvm::Triple::FreeBSD:
6562       return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
6563     case llvm::Triple::NetBSD:
6564       return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6565     default:
6566       return new PPC64TargetInfo(Triple);
6567     }
6568 
6569   case llvm::Triple::ppc64le:
6570     switch (os) {
6571     case llvm::Triple::Linux:
6572       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6573     default:
6574       return new PPC64TargetInfo(Triple);
6575     }
6576 
6577   case llvm::Triple::nvptx:
6578     return new NVPTX32TargetInfo(Triple);
6579   case llvm::Triple::nvptx64:
6580     return new NVPTX64TargetInfo(Triple);
6581 
6582   case llvm::Triple::r600:
6583     return new R600TargetInfo(Triple);
6584 
6585   case llvm::Triple::sparc:
6586     switch (os) {
6587     case llvm::Triple::Linux:
6588       return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
6589     case llvm::Triple::Solaris:
6590       return new SolarisSparcV8TargetInfo(Triple);
6591     case llvm::Triple::NetBSD:
6592       return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
6593     case llvm::Triple::OpenBSD:
6594       return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
6595     case llvm::Triple::RTEMS:
6596       return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
6597     default:
6598       return new SparcV8TargetInfo(Triple);
6599     }
6600 
6601   case llvm::Triple::sparcv9:
6602     switch (os) {
6603     case llvm::Triple::Linux:
6604       return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
6605     case llvm::Triple::Solaris:
6606       return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
6607     case llvm::Triple::NetBSD:
6608       return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
6609     case llvm::Triple::OpenBSD:
6610       return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
6611     case llvm::Triple::FreeBSD:
6612       return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
6613     default:
6614       return new SparcV9TargetInfo(Triple);
6615     }
6616 
6617   case llvm::Triple::systemz:
6618     switch (os) {
6619     case llvm::Triple::Linux:
6620       return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
6621     default:
6622       return new SystemZTargetInfo(Triple);
6623     }
6624 
6625   case llvm::Triple::tce:
6626     return new TCETargetInfo(Triple);
6627 
6628   case llvm::Triple::x86:
6629     if (Triple.isOSDarwin())
6630       return new DarwinI386TargetInfo(Triple);
6631 
6632     switch (os) {
6633     case llvm::Triple::Linux:
6634       return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
6635     case llvm::Triple::DragonFly:
6636       return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
6637     case llvm::Triple::NetBSD:
6638       return new NetBSDI386TargetInfo(Triple);
6639     case llvm::Triple::OpenBSD:
6640       return new OpenBSDI386TargetInfo(Triple);
6641     case llvm::Triple::Bitrig:
6642       return new BitrigI386TargetInfo(Triple);
6643     case llvm::Triple::FreeBSD:
6644       return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6645     case llvm::Triple::KFreeBSD:
6646       return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6647     case llvm::Triple::Minix:
6648       return new MinixTargetInfo<X86_32TargetInfo>(Triple);
6649     case llvm::Triple::Solaris:
6650       return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
6651     case llvm::Triple::Win32: {
6652       switch (Triple.getEnvironment()) {
6653       default:
6654         return new X86_32TargetInfo(Triple);
6655       case llvm::Triple::Cygnus:
6656         return new CygwinX86_32TargetInfo(Triple);
6657       case llvm::Triple::GNU:
6658         return new MinGWX86_32TargetInfo(Triple);
6659       case llvm::Triple::Itanium:
6660       case llvm::Triple::MSVC:
6661         return new MicrosoftX86_32TargetInfo(Triple);
6662       }
6663     }
6664     case llvm::Triple::Haiku:
6665       return new HaikuX86_32TargetInfo(Triple);
6666     case llvm::Triple::RTEMS:
6667       return new RTEMSX86_32TargetInfo(Triple);
6668     case llvm::Triple::NaCl:
6669       return new NaClTargetInfo<X86_32TargetInfo>(Triple);
6670     default:
6671       return new X86_32TargetInfo(Triple);
6672     }
6673 
6674   case llvm::Triple::x86_64:
6675     if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
6676       return new DarwinX86_64TargetInfo(Triple);
6677 
6678     switch (os) {
6679     case llvm::Triple::Linux:
6680       return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
6681     case llvm::Triple::DragonFly:
6682       return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
6683     case llvm::Triple::NetBSD:
6684       return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
6685     case llvm::Triple::OpenBSD:
6686       return new OpenBSDX86_64TargetInfo(Triple);
6687     case llvm::Triple::Bitrig:
6688       return new BitrigX86_64TargetInfo(Triple);
6689     case llvm::Triple::FreeBSD:
6690       return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6691     case llvm::Triple::KFreeBSD:
6692       return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6693     case llvm::Triple::Solaris:
6694       return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
6695     case llvm::Triple::Win32: {
6696       switch (Triple.getEnvironment()) {
6697       default:
6698         return new X86_64TargetInfo(Triple);
6699       case llvm::Triple::GNU:
6700         return new MinGWX86_64TargetInfo(Triple);
6701       case llvm::Triple::MSVC:
6702         return new MicrosoftX86_64TargetInfo(Triple);
6703       }
6704     }
6705     case llvm::Triple::NaCl:
6706       return new NaClTargetInfo<X86_64TargetInfo>(Triple);
6707     default:
6708       return new X86_64TargetInfo(Triple);
6709     }
6710 
6711     case llvm::Triple::spir: {
6712       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6713           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6714         return nullptr;
6715       return new SPIR32TargetInfo(Triple);
6716     }
6717     case llvm::Triple::spir64: {
6718       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6719           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6720         return nullptr;
6721       return new SPIR64TargetInfo(Triple);
6722     }
6723   }
6724 }
6725 
6726 /// CreateTargetInfo - Return the target info object for the specified target
6727 /// triple.
6728 TargetInfo *
6729 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
6730                              const std::shared_ptr<TargetOptions> &Opts) {
6731   llvm::Triple Triple(Opts->Triple);
6732 
6733   // Construct the target
6734   std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
6735   if (!Target) {
6736     Diags.Report(diag::err_target_unknown_triple) << Triple.str();
6737     return nullptr;
6738   }
6739   Target->TargetOpts = Opts;
6740 
6741   // Set the target CPU if specified.
6742   if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
6743     Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
6744     return nullptr;
6745   }
6746 
6747   // Set the target ABI if specified.
6748   if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
6749     Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
6750     return nullptr;
6751   }
6752 
6753   // Set the fp math unit.
6754   if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
6755     Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
6756     return nullptr;
6757   }
6758 
6759   // Compute the default target features, we need the target to handle this
6760   // because features may have dependencies on one another.
6761   llvm::StringMap<bool> Features;
6762   Target->getDefaultFeatures(Features);
6763 
6764   // Apply the user specified deltas.
6765   for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
6766        I < N; ++I) {
6767     const char *Name = Opts->FeaturesAsWritten[I].c_str();
6768     // Apply the feature via the target.
6769     bool Enabled = Name[0] == '+';
6770     Target->setFeatureEnabled(Features, Name + 1, Enabled);
6771   }
6772 
6773   // Add the features to the compile options.
6774   //
6775   // FIXME: If we are completely confident that we have the right set, we only
6776   // need to pass the minuses.
6777   Opts->Features.clear();
6778   for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
6779          ie = Features.end(); it != ie; ++it)
6780     Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
6781   if (!Target->handleTargetFeatures(Opts->Features, Diags))
6782     return nullptr;
6783 
6784   return Target.release();
6785 }
6786