1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "llvm/ADT/APFloat.h" 25 #include "llvm/ADT/STLExtras.h" 26 #include "llvm/ADT/StringExtras.h" 27 #include "llvm/ADT/StringRef.h" 28 #include "llvm/ADT/StringSwitch.h" 29 #include "llvm/ADT/Triple.h" 30 #include "llvm/MC/MCSectionMachO.h" 31 #include "llvm/Support/ErrorHandling.h" 32 #include "llvm/Support/TargetParser.h" 33 #include <algorithm> 34 #include <memory> 35 36 using namespace clang; 37 38 //===----------------------------------------------------------------------===// 39 // Common code shared among targets. 40 //===----------------------------------------------------------------------===// 41 42 /// DefineStd - Define a macro name and standard variants. For example if 43 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 44 /// when in GNU mode. 45 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 46 const LangOptions &Opts) { 47 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 48 49 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 50 // in the user's namespace. 51 if (Opts.GNUMode) 52 Builder.defineMacro(MacroName); 53 54 // Define __unix. 55 Builder.defineMacro("__" + MacroName); 56 57 // Define __unix__. 58 Builder.defineMacro("__" + MacroName + "__"); 59 } 60 61 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 62 bool Tuning = true) { 63 Builder.defineMacro("__" + CPUName); 64 Builder.defineMacro("__" + CPUName + "__"); 65 if (Tuning) 66 Builder.defineMacro("__tune_" + CPUName + "__"); 67 } 68 69 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 70 const TargetOptions &Opts); 71 72 //===----------------------------------------------------------------------===// 73 // Defines specific to certain operating systems. 74 //===----------------------------------------------------------------------===// 75 76 namespace { 77 template<typename TgtInfo> 78 class OSTargetInfo : public TgtInfo { 79 protected: 80 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 81 MacroBuilder &Builder) const=0; 82 public: 83 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 84 : TgtInfo(Triple, Opts) {} 85 void getTargetDefines(const LangOptions &Opts, 86 MacroBuilder &Builder) const override { 87 TgtInfo::getTargetDefines(Opts, Builder); 88 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 89 } 90 91 }; 92 93 // CloudABI Target 94 template <typename Target> 95 class CloudABITargetInfo : public OSTargetInfo<Target> { 96 protected: 97 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 98 MacroBuilder &Builder) const override { 99 Builder.defineMacro("__CloudABI__"); 100 Builder.defineMacro("__ELF__"); 101 102 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 103 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 104 Builder.defineMacro("__STDC_UTF_16__"); 105 Builder.defineMacro("__STDC_UTF_32__"); 106 } 107 108 public: 109 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 110 : OSTargetInfo<Target>(Triple, Opts) {} 111 }; 112 113 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 114 const llvm::Triple &Triple, 115 StringRef &PlatformName, 116 VersionTuple &PlatformMinVersion) { 117 Builder.defineMacro("__APPLE_CC__", "6000"); 118 Builder.defineMacro("__APPLE__"); 119 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 120 // AddressSanitizer doesn't play well with source fortification, which is on 121 // by default on Darwin. 122 if (Opts.Sanitize.has(SanitizerKind::Address)) 123 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 124 125 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 126 if (!Opts.ObjC1) { 127 // __weak is always defined, for use in blocks and with objc pointers. 128 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 129 Builder.defineMacro("__strong", ""); 130 Builder.defineMacro("__unsafe_unretained", ""); 131 } 132 133 if (Opts.Static) 134 Builder.defineMacro("__STATIC__"); 135 else 136 Builder.defineMacro("__DYNAMIC__"); 137 138 if (Opts.POSIXThreads) 139 Builder.defineMacro("_REENTRANT"); 140 141 // Get the platform type and version number from the triple. 142 unsigned Maj, Min, Rev; 143 if (Triple.isMacOSX()) { 144 Triple.getMacOSXVersion(Maj, Min, Rev); 145 PlatformName = "macos"; 146 } else { 147 Triple.getOSVersion(Maj, Min, Rev); 148 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 149 } 150 151 // If -target arch-pc-win32-macho option specified, we're 152 // generating code for Win32 ABI. No need to emit 153 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 154 if (PlatformName == "win32") { 155 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 156 return; 157 } 158 159 // Set the appropriate OS version define. 160 if (Triple.isiOS()) { 161 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 162 char Str[7]; 163 if (Maj < 10) { 164 Str[0] = '0' + Maj; 165 Str[1] = '0' + (Min / 10); 166 Str[2] = '0' + (Min % 10); 167 Str[3] = '0' + (Rev / 10); 168 Str[4] = '0' + (Rev % 10); 169 Str[5] = '\0'; 170 } else { 171 // Handle versions >= 10. 172 Str[0] = '0' + (Maj / 10); 173 Str[1] = '0' + (Maj % 10); 174 Str[2] = '0' + (Min / 10); 175 Str[3] = '0' + (Min % 10); 176 Str[4] = '0' + (Rev / 10); 177 Str[5] = '0' + (Rev % 10); 178 Str[6] = '\0'; 179 } 180 if (Triple.isTvOS()) 181 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 182 else 183 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 184 Str); 185 186 } else if (Triple.isWatchOS()) { 187 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 188 char Str[6]; 189 Str[0] = '0' + Maj; 190 Str[1] = '0' + (Min / 10); 191 Str[2] = '0' + (Min % 10); 192 Str[3] = '0' + (Rev / 10); 193 Str[4] = '0' + (Rev % 10); 194 Str[5] = '\0'; 195 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 196 } else if (Triple.isMacOSX()) { 197 // Note that the Driver allows versions which aren't representable in the 198 // define (because we only get a single digit for the minor and micro 199 // revision numbers). So, we limit them to the maximum representable 200 // version. 201 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 202 char Str[7]; 203 if (Maj < 10 || (Maj == 10 && Min < 10)) { 204 Str[0] = '0' + (Maj / 10); 205 Str[1] = '0' + (Maj % 10); 206 Str[2] = '0' + std::min(Min, 9U); 207 Str[3] = '0' + std::min(Rev, 9U); 208 Str[4] = '\0'; 209 } else { 210 // Handle versions > 10.9. 211 Str[0] = '0' + (Maj / 10); 212 Str[1] = '0' + (Maj % 10); 213 Str[2] = '0' + (Min / 10); 214 Str[3] = '0' + (Min % 10); 215 Str[4] = '0' + (Rev / 10); 216 Str[5] = '0' + (Rev % 10); 217 Str[6] = '\0'; 218 } 219 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 220 } 221 222 // Tell users about the kernel if there is one. 223 if (Triple.isOSDarwin()) 224 Builder.defineMacro("__MACH__"); 225 226 // The Watch ABI uses Dwarf EH. 227 if(Triple.isWatchABI()) 228 Builder.defineMacro("__ARM_DWARF_EH__"); 229 230 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 231 } 232 233 template<typename Target> 234 class DarwinTargetInfo : public OSTargetInfo<Target> { 235 protected: 236 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 237 MacroBuilder &Builder) const override { 238 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 239 this->PlatformMinVersion); 240 } 241 242 public: 243 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 244 : OSTargetInfo<Target>(Triple, Opts) { 245 // By default, no TLS, and we whitelist permitted architecture/OS 246 // combinations. 247 this->TLSSupported = false; 248 249 if (Triple.isMacOSX()) 250 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 251 else if (Triple.isiOS()) { 252 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 253 if (Triple.getArch() == llvm::Triple::x86_64 || 254 Triple.getArch() == llvm::Triple::aarch64) 255 this->TLSSupported = !Triple.isOSVersionLT(8); 256 else if (Triple.getArch() == llvm::Triple::x86 || 257 Triple.getArch() == llvm::Triple::arm || 258 Triple.getArch() == llvm::Triple::thumb) 259 this->TLSSupported = !Triple.isOSVersionLT(9); 260 } else if (Triple.isWatchOS()) 261 this->TLSSupported = !Triple.isOSVersionLT(2); 262 263 this->MCountName = "\01mcount"; 264 } 265 266 std::string isValidSectionSpecifier(StringRef SR) const override { 267 // Let MCSectionMachO validate this. 268 StringRef Segment, Section; 269 unsigned TAA, StubSize; 270 bool HasTAA; 271 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 272 TAA, HasTAA, StubSize); 273 } 274 275 const char *getStaticInitSectionSpecifier() const override { 276 // FIXME: We should return 0 when building kexts. 277 return "__TEXT,__StaticInit,regular,pure_instructions"; 278 } 279 280 /// Darwin does not support protected visibility. Darwin's "default" 281 /// is very similar to ELF's "protected"; Darwin requires a "weak" 282 /// attribute on declarations that can be dynamically replaced. 283 bool hasProtectedVisibility() const override { 284 return false; 285 } 286 287 unsigned getExnObjectAlignment() const override { 288 // The alignment of an exception object is 8-bytes for darwin since 289 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 290 // and therefore doesn't guarantee 16-byte alignment. 291 return 64; 292 } 293 }; 294 295 296 // DragonFlyBSD Target 297 template<typename Target> 298 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 299 protected: 300 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 301 MacroBuilder &Builder) const override { 302 // DragonFly defines; list based off of gcc output 303 Builder.defineMacro("__DragonFly__"); 304 Builder.defineMacro("__DragonFly_cc_version", "100001"); 305 Builder.defineMacro("__ELF__"); 306 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 307 Builder.defineMacro("__tune_i386__"); 308 DefineStd(Builder, "unix", Opts); 309 } 310 public: 311 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 312 : OSTargetInfo<Target>(Triple, Opts) { 313 switch (Triple.getArch()) { 314 default: 315 case llvm::Triple::x86: 316 case llvm::Triple::x86_64: 317 this->MCountName = ".mcount"; 318 break; 319 } 320 } 321 }; 322 323 #ifndef FREEBSD_CC_VERSION 324 #define FREEBSD_CC_VERSION 0U 325 #endif 326 327 // FreeBSD Target 328 template<typename Target> 329 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 330 protected: 331 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 332 MacroBuilder &Builder) const override { 333 // FreeBSD defines; list based off of gcc output 334 335 unsigned Release = Triple.getOSMajorVersion(); 336 if (Release == 0U) 337 Release = 8U; 338 unsigned CCVersion = FREEBSD_CC_VERSION; 339 if (CCVersion == 0U) 340 CCVersion = Release * 100000U + 1U; 341 342 Builder.defineMacro("__FreeBSD__", Twine(Release)); 343 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 344 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 345 DefineStd(Builder, "unix", Opts); 346 Builder.defineMacro("__ELF__"); 347 348 // On FreeBSD, wchar_t contains the number of the code point as 349 // used by the character set of the locale. These character sets are 350 // not necessarily a superset of ASCII. 351 // 352 // FIXME: This is wrong; the macro refers to the numerical values 353 // of wchar_t *literals*, which are not locale-dependent. However, 354 // FreeBSD systems apparently depend on us getting this wrong, and 355 // setting this to 1 is conforming even if all the basic source 356 // character literals have the same encoding as char and wchar_t. 357 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 358 } 359 public: 360 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 361 : OSTargetInfo<Target>(Triple, Opts) { 362 switch (Triple.getArch()) { 363 default: 364 case llvm::Triple::x86: 365 case llvm::Triple::x86_64: 366 this->MCountName = ".mcount"; 367 break; 368 case llvm::Triple::mips: 369 case llvm::Triple::mipsel: 370 case llvm::Triple::ppc: 371 case llvm::Triple::ppc64: 372 case llvm::Triple::ppc64le: 373 this->MCountName = "_mcount"; 374 break; 375 case llvm::Triple::arm: 376 this->MCountName = "__mcount"; 377 break; 378 } 379 } 380 }; 381 382 // GNU/kFreeBSD Target 383 template<typename Target> 384 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 385 protected: 386 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 387 MacroBuilder &Builder) const override { 388 // GNU/kFreeBSD defines; list based off of gcc output 389 390 DefineStd(Builder, "unix", Opts); 391 Builder.defineMacro("__FreeBSD_kernel__"); 392 Builder.defineMacro("__GLIBC__"); 393 Builder.defineMacro("__ELF__"); 394 if (Opts.POSIXThreads) 395 Builder.defineMacro("_REENTRANT"); 396 if (Opts.CPlusPlus) 397 Builder.defineMacro("_GNU_SOURCE"); 398 } 399 public: 400 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 401 : OSTargetInfo<Target>(Triple, Opts) {} 402 }; 403 404 // Haiku Target 405 template<typename Target> 406 class HaikuTargetInfo : public OSTargetInfo<Target> { 407 protected: 408 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 409 MacroBuilder &Builder) const override { 410 // Haiku defines; list based off of gcc output 411 Builder.defineMacro("__HAIKU__"); 412 Builder.defineMacro("__ELF__"); 413 DefineStd(Builder, "unix", Opts); 414 } 415 public: 416 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 417 : OSTargetInfo<Target>(Triple, Opts) { 418 this->SizeType = TargetInfo::UnsignedLong; 419 this->IntPtrType = TargetInfo::SignedLong; 420 this->PtrDiffType = TargetInfo::SignedLong; 421 this->ProcessIDType = TargetInfo::SignedLong; 422 this->TLSSupported = false; 423 424 } 425 }; 426 427 // Minix Target 428 template<typename Target> 429 class MinixTargetInfo : public OSTargetInfo<Target> { 430 protected: 431 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 432 MacroBuilder &Builder) const override { 433 // Minix defines 434 435 Builder.defineMacro("__minix", "3"); 436 Builder.defineMacro("_EM_WSIZE", "4"); 437 Builder.defineMacro("_EM_PSIZE", "4"); 438 Builder.defineMacro("_EM_SSIZE", "2"); 439 Builder.defineMacro("_EM_LSIZE", "4"); 440 Builder.defineMacro("_EM_FSIZE", "4"); 441 Builder.defineMacro("_EM_DSIZE", "8"); 442 Builder.defineMacro("__ELF__"); 443 DefineStd(Builder, "unix", Opts); 444 } 445 public: 446 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 447 : OSTargetInfo<Target>(Triple, Opts) {} 448 }; 449 450 // Linux target 451 template<typename Target> 452 class LinuxTargetInfo : public OSTargetInfo<Target> { 453 protected: 454 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 455 MacroBuilder &Builder) const override { 456 // Linux defines; list based off of gcc output 457 DefineStd(Builder, "unix", Opts); 458 DefineStd(Builder, "linux", Opts); 459 Builder.defineMacro("__gnu_linux__"); 460 Builder.defineMacro("__ELF__"); 461 if (Triple.isAndroid()) { 462 Builder.defineMacro("__ANDROID__", "1"); 463 unsigned Maj, Min, Rev; 464 Triple.getEnvironmentVersion(Maj, Min, Rev); 465 this->PlatformName = "android"; 466 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 467 } 468 if (Opts.POSIXThreads) 469 Builder.defineMacro("_REENTRANT"); 470 if (Opts.CPlusPlus) 471 Builder.defineMacro("_GNU_SOURCE"); 472 if (this->HasFloat128) 473 Builder.defineMacro("__FLOAT128__"); 474 } 475 public: 476 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 477 : OSTargetInfo<Target>(Triple, Opts) { 478 this->WIntType = TargetInfo::UnsignedInt; 479 480 switch (Triple.getArch()) { 481 default: 482 break; 483 case llvm::Triple::ppc: 484 case llvm::Triple::ppc64: 485 case llvm::Triple::ppc64le: 486 this->MCountName = "_mcount"; 487 break; 488 case llvm::Triple::x86: 489 case llvm::Triple::x86_64: 490 case llvm::Triple::systemz: 491 this->HasFloat128 = true; 492 break; 493 } 494 } 495 496 const char *getStaticInitSectionSpecifier() const override { 497 return ".text.startup"; 498 } 499 }; 500 501 // NetBSD Target 502 template<typename Target> 503 class NetBSDTargetInfo : public OSTargetInfo<Target> { 504 protected: 505 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 506 MacroBuilder &Builder) const override { 507 // NetBSD defines; list based off of gcc output 508 Builder.defineMacro("__NetBSD__"); 509 Builder.defineMacro("__unix__"); 510 Builder.defineMacro("__ELF__"); 511 if (Opts.POSIXThreads) 512 Builder.defineMacro("_POSIX_THREADS"); 513 514 switch (Triple.getArch()) { 515 default: 516 break; 517 case llvm::Triple::arm: 518 case llvm::Triple::armeb: 519 case llvm::Triple::thumb: 520 case llvm::Triple::thumbeb: 521 Builder.defineMacro("__ARM_DWARF_EH__"); 522 break; 523 } 524 } 525 public: 526 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 527 : OSTargetInfo<Target>(Triple, Opts) { 528 this->MCountName = "_mcount"; 529 } 530 }; 531 532 // OpenBSD Target 533 template<typename Target> 534 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 535 protected: 536 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 537 MacroBuilder &Builder) const override { 538 // OpenBSD defines; list based off of gcc output 539 540 Builder.defineMacro("__OpenBSD__"); 541 DefineStd(Builder, "unix", Opts); 542 Builder.defineMacro("__ELF__"); 543 if (Opts.POSIXThreads) 544 Builder.defineMacro("_REENTRANT"); 545 } 546 public: 547 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 548 : OSTargetInfo<Target>(Triple, Opts) { 549 this->TLSSupported = false; 550 551 switch (Triple.getArch()) { 552 default: 553 case llvm::Triple::x86: 554 case llvm::Triple::x86_64: 555 case llvm::Triple::arm: 556 case llvm::Triple::sparc: 557 this->MCountName = "__mcount"; 558 break; 559 case llvm::Triple::mips64: 560 case llvm::Triple::mips64el: 561 case llvm::Triple::ppc: 562 case llvm::Triple::sparcv9: 563 this->MCountName = "_mcount"; 564 break; 565 } 566 } 567 }; 568 569 // Bitrig Target 570 template<typename Target> 571 class BitrigTargetInfo : public OSTargetInfo<Target> { 572 protected: 573 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 574 MacroBuilder &Builder) const override { 575 // Bitrig defines; list based off of gcc output 576 577 Builder.defineMacro("__Bitrig__"); 578 DefineStd(Builder, "unix", Opts); 579 Builder.defineMacro("__ELF__"); 580 if (Opts.POSIXThreads) 581 Builder.defineMacro("_REENTRANT"); 582 583 switch (Triple.getArch()) { 584 default: 585 break; 586 case llvm::Triple::arm: 587 case llvm::Triple::armeb: 588 case llvm::Triple::thumb: 589 case llvm::Triple::thumbeb: 590 Builder.defineMacro("__ARM_DWARF_EH__"); 591 break; 592 } 593 } 594 public: 595 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 596 : OSTargetInfo<Target>(Triple, Opts) { 597 this->MCountName = "__mcount"; 598 } 599 }; 600 601 // PSP Target 602 template<typename Target> 603 class PSPTargetInfo : public OSTargetInfo<Target> { 604 protected: 605 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 606 MacroBuilder &Builder) const override { 607 // PSP defines; list based on the output of the pspdev gcc toolchain. 608 Builder.defineMacro("PSP"); 609 Builder.defineMacro("_PSP"); 610 Builder.defineMacro("__psp__"); 611 Builder.defineMacro("__ELF__"); 612 } 613 public: 614 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 615 }; 616 617 // PS3 PPU Target 618 template<typename Target> 619 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 620 protected: 621 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 622 MacroBuilder &Builder) const override { 623 // PS3 PPU defines. 624 Builder.defineMacro("__PPC__"); 625 Builder.defineMacro("__PPU__"); 626 Builder.defineMacro("__CELLOS_LV2__"); 627 Builder.defineMacro("__ELF__"); 628 Builder.defineMacro("__LP32__"); 629 Builder.defineMacro("_ARCH_PPC64"); 630 Builder.defineMacro("__powerpc64__"); 631 } 632 public: 633 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 634 : OSTargetInfo<Target>(Triple, Opts) { 635 this->LongWidth = this->LongAlign = 32; 636 this->PointerWidth = this->PointerAlign = 32; 637 this->IntMaxType = TargetInfo::SignedLongLong; 638 this->Int64Type = TargetInfo::SignedLongLong; 639 this->SizeType = TargetInfo::UnsignedInt; 640 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 641 } 642 }; 643 644 template <typename Target> 645 class PS4OSTargetInfo : public OSTargetInfo<Target> { 646 protected: 647 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 648 MacroBuilder &Builder) const override { 649 Builder.defineMacro("__FreeBSD__", "9"); 650 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 651 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 652 DefineStd(Builder, "unix", Opts); 653 Builder.defineMacro("__ELF__"); 654 Builder.defineMacro("__ORBIS__"); 655 } 656 public: 657 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 658 : OSTargetInfo<Target>(Triple, Opts) { 659 this->WCharType = this->UnsignedShort; 660 661 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 662 this->MaxTLSAlign = 256; 663 664 // On PS4, do not honor explicit bit field alignment, 665 // as in "__attribute__((aligned(2))) int b : 1;". 666 this->UseExplicitBitFieldAlignment = false; 667 668 switch (Triple.getArch()) { 669 default: 670 case llvm::Triple::x86_64: 671 this->MCountName = ".mcount"; 672 break; 673 } 674 } 675 }; 676 677 // Solaris target 678 template<typename Target> 679 class SolarisTargetInfo : public OSTargetInfo<Target> { 680 protected: 681 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 682 MacroBuilder &Builder) const override { 683 DefineStd(Builder, "sun", Opts); 684 DefineStd(Builder, "unix", Opts); 685 Builder.defineMacro("__ELF__"); 686 Builder.defineMacro("__svr4__"); 687 Builder.defineMacro("__SVR4"); 688 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 689 // newer, but to 500 for everything else. feature_test.h has a check to 690 // ensure that you are not using C99 with an old version of X/Open or C89 691 // with a new version. 692 if (Opts.C99) 693 Builder.defineMacro("_XOPEN_SOURCE", "600"); 694 else 695 Builder.defineMacro("_XOPEN_SOURCE", "500"); 696 if (Opts.CPlusPlus) 697 Builder.defineMacro("__C99FEATURES__"); 698 Builder.defineMacro("_LARGEFILE_SOURCE"); 699 Builder.defineMacro("_LARGEFILE64_SOURCE"); 700 Builder.defineMacro("__EXTENSIONS__"); 701 Builder.defineMacro("_REENTRANT"); 702 } 703 public: 704 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 705 : OSTargetInfo<Target>(Triple, Opts) { 706 this->WCharType = this->SignedInt; 707 // FIXME: WIntType should be SignedLong 708 } 709 }; 710 711 // Windows target 712 template<typename Target> 713 class WindowsTargetInfo : public OSTargetInfo<Target> { 714 protected: 715 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 716 MacroBuilder &Builder) const override { 717 Builder.defineMacro("_WIN32"); 718 } 719 void getVisualStudioDefines(const LangOptions &Opts, 720 MacroBuilder &Builder) const { 721 if (Opts.CPlusPlus) { 722 if (Opts.RTTIData) 723 Builder.defineMacro("_CPPRTTI"); 724 725 if (Opts.CXXExceptions) 726 Builder.defineMacro("_CPPUNWIND"); 727 } 728 729 if (Opts.Bool) 730 Builder.defineMacro("__BOOL_DEFINED"); 731 732 if (!Opts.CharIsSigned) 733 Builder.defineMacro("_CHAR_UNSIGNED"); 734 735 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 736 // but it works for now. 737 if (Opts.POSIXThreads) 738 Builder.defineMacro("_MT"); 739 740 if (Opts.MSCompatibilityVersion) { 741 Builder.defineMacro("_MSC_VER", 742 Twine(Opts.MSCompatibilityVersion / 100000)); 743 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 744 // FIXME We cannot encode the revision information into 32-bits 745 Builder.defineMacro("_MSC_BUILD", Twine(1)); 746 747 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 748 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 749 750 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 751 if (Opts.CPlusPlus1z) 752 Builder.defineMacro("_MSVC_LANG", "201403L"); 753 else if (Opts.CPlusPlus14) 754 Builder.defineMacro("_MSVC_LANG", "201402L"); 755 } 756 } 757 758 if (Opts.MicrosoftExt) { 759 Builder.defineMacro("_MSC_EXTENSIONS"); 760 761 if (Opts.CPlusPlus11) { 762 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 763 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 764 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 765 } 766 } 767 768 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 769 } 770 771 public: 772 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 773 : OSTargetInfo<Target>(Triple, Opts) {} 774 }; 775 776 template <typename Target> 777 class NaClTargetInfo : public OSTargetInfo<Target> { 778 protected: 779 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 780 MacroBuilder &Builder) const override { 781 if (Opts.POSIXThreads) 782 Builder.defineMacro("_REENTRANT"); 783 if (Opts.CPlusPlus) 784 Builder.defineMacro("_GNU_SOURCE"); 785 786 DefineStd(Builder, "unix", Opts); 787 Builder.defineMacro("__ELF__"); 788 Builder.defineMacro("__native_client__"); 789 } 790 791 public: 792 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 793 : OSTargetInfo<Target>(Triple, Opts) { 794 this->LongAlign = 32; 795 this->LongWidth = 32; 796 this->PointerAlign = 32; 797 this->PointerWidth = 32; 798 this->IntMaxType = TargetInfo::SignedLongLong; 799 this->Int64Type = TargetInfo::SignedLongLong; 800 this->DoubleAlign = 64; 801 this->LongDoubleWidth = 64; 802 this->LongDoubleAlign = 64; 803 this->LongLongWidth = 64; 804 this->LongLongAlign = 64; 805 this->SizeType = TargetInfo::UnsignedInt; 806 this->PtrDiffType = TargetInfo::SignedInt; 807 this->IntPtrType = TargetInfo::SignedInt; 808 // RegParmMax is inherited from the underlying architecture 809 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 810 if (Triple.getArch() == llvm::Triple::arm) { 811 // Handled in ARM's setABI(). 812 } else if (Triple.getArch() == llvm::Triple::x86) { 813 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 814 } else if (Triple.getArch() == llvm::Triple::x86_64) { 815 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 816 } else if (Triple.getArch() == llvm::Triple::mipsel) { 817 // Handled on mips' setDataLayout. 818 } else { 819 assert(Triple.getArch() == llvm::Triple::le32); 820 this->resetDataLayout("e-p:32:32-i64:64"); 821 } 822 } 823 }; 824 825 // WebAssembly target 826 template <typename Target> 827 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 828 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 829 MacroBuilder &Builder) const final { 830 // A common platform macro. 831 if (Opts.POSIXThreads) 832 Builder.defineMacro("_REENTRANT"); 833 // Follow g++ convention and predefine _GNU_SOURCE for C++. 834 if (Opts.CPlusPlus) 835 Builder.defineMacro("_GNU_SOURCE"); 836 } 837 838 // As an optimization, group static init code together in a section. 839 const char *getStaticInitSectionSpecifier() const final { 840 return ".text.__startup"; 841 } 842 843 public: 844 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 845 const TargetOptions &Opts) 846 : OSTargetInfo<Target>(Triple, Opts) { 847 this->MCountName = "__mcount"; 848 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 849 } 850 }; 851 852 //===----------------------------------------------------------------------===// 853 // Specific target implementations. 854 //===----------------------------------------------------------------------===// 855 856 // PPC abstract base class 857 class PPCTargetInfo : public TargetInfo { 858 static const Builtin::Info BuiltinInfo[]; 859 static const char * const GCCRegNames[]; 860 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 861 std::string CPU; 862 863 // Target cpu features. 864 bool HasVSX; 865 bool HasP8Vector; 866 bool HasP8Crypto; 867 bool HasDirectMove; 868 bool HasQPX; 869 bool HasHTM; 870 bool HasBPERMD; 871 bool HasExtDiv; 872 873 protected: 874 std::string ABI; 875 876 public: 877 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 878 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 879 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 880 HasBPERMD(false), HasExtDiv(false) { 881 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 882 SimdDefaultAlign = 128; 883 LongDoubleWidth = LongDoubleAlign = 128; 884 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 885 } 886 887 /// \brief Flags for architecture specific defines. 888 typedef enum { 889 ArchDefineNone = 0, 890 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 891 ArchDefinePpcgr = 1 << 1, 892 ArchDefinePpcsq = 1 << 2, 893 ArchDefine440 = 1 << 3, 894 ArchDefine603 = 1 << 4, 895 ArchDefine604 = 1 << 5, 896 ArchDefinePwr4 = 1 << 6, 897 ArchDefinePwr5 = 1 << 7, 898 ArchDefinePwr5x = 1 << 8, 899 ArchDefinePwr6 = 1 << 9, 900 ArchDefinePwr6x = 1 << 10, 901 ArchDefinePwr7 = 1 << 11, 902 ArchDefinePwr8 = 1 << 12, 903 ArchDefinePwr9 = 1 << 13, 904 ArchDefineA2 = 1 << 14, 905 ArchDefineA2q = 1 << 15 906 } ArchDefineTypes; 907 908 // Note: GCC recognizes the following additional cpus: 909 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 910 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 911 // titan, rs64. 912 bool setCPU(const std::string &Name) override { 913 bool CPUKnown = llvm::StringSwitch<bool>(Name) 914 .Case("generic", true) 915 .Case("440", true) 916 .Case("450", true) 917 .Case("601", true) 918 .Case("602", true) 919 .Case("603", true) 920 .Case("603e", true) 921 .Case("603ev", true) 922 .Case("604", true) 923 .Case("604e", true) 924 .Case("620", true) 925 .Case("630", true) 926 .Case("g3", true) 927 .Case("7400", true) 928 .Case("g4", true) 929 .Case("7450", true) 930 .Case("g4+", true) 931 .Case("750", true) 932 .Case("970", true) 933 .Case("g5", true) 934 .Case("a2", true) 935 .Case("a2q", true) 936 .Case("e500mc", true) 937 .Case("e5500", true) 938 .Case("power3", true) 939 .Case("pwr3", true) 940 .Case("power4", true) 941 .Case("pwr4", true) 942 .Case("power5", true) 943 .Case("pwr5", true) 944 .Case("power5x", true) 945 .Case("pwr5x", true) 946 .Case("power6", true) 947 .Case("pwr6", true) 948 .Case("power6x", true) 949 .Case("pwr6x", true) 950 .Case("power7", true) 951 .Case("pwr7", true) 952 .Case("power8", true) 953 .Case("pwr8", true) 954 .Case("power9", true) 955 .Case("pwr9", true) 956 .Case("powerpc", true) 957 .Case("ppc", true) 958 .Case("powerpc64", true) 959 .Case("ppc64", true) 960 .Case("powerpc64le", true) 961 .Case("ppc64le", true) 962 .Default(false); 963 964 if (CPUKnown) 965 CPU = Name; 966 967 return CPUKnown; 968 } 969 970 971 StringRef getABI() const override { return ABI; } 972 973 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 974 return llvm::makeArrayRef(BuiltinInfo, 975 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 976 } 977 978 bool isCLZForZeroUndef() const override { return false; } 979 980 void getTargetDefines(const LangOptions &Opts, 981 MacroBuilder &Builder) const override; 982 983 bool 984 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 985 StringRef CPU, 986 const std::vector<std::string> &FeaturesVec) const override; 987 988 bool handleTargetFeatures(std::vector<std::string> &Features, 989 DiagnosticsEngine &Diags) override; 990 bool hasFeature(StringRef Feature) const override; 991 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 992 bool Enabled) const override; 993 994 ArrayRef<const char *> getGCCRegNames() const override; 995 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 996 bool validateAsmConstraint(const char *&Name, 997 TargetInfo::ConstraintInfo &Info) const override { 998 switch (*Name) { 999 default: return false; 1000 case 'O': // Zero 1001 break; 1002 case 'b': // Base register 1003 case 'f': // Floating point register 1004 Info.setAllowsRegister(); 1005 break; 1006 // FIXME: The following are added to allow parsing. 1007 // I just took a guess at what the actions should be. 1008 // Also, is more specific checking needed? I.e. specific registers? 1009 case 'd': // Floating point register (containing 64-bit value) 1010 case 'v': // Altivec vector register 1011 Info.setAllowsRegister(); 1012 break; 1013 case 'w': 1014 switch (Name[1]) { 1015 case 'd':// VSX vector register to hold vector double data 1016 case 'f':// VSX vector register to hold vector float data 1017 case 's':// VSX vector register to hold scalar float data 1018 case 'a':// Any VSX register 1019 case 'c':// An individual CR bit 1020 break; 1021 default: 1022 return false; 1023 } 1024 Info.setAllowsRegister(); 1025 Name++; // Skip over 'w'. 1026 break; 1027 case 'h': // `MQ', `CTR', or `LINK' register 1028 case 'q': // `MQ' register 1029 case 'c': // `CTR' register 1030 case 'l': // `LINK' register 1031 case 'x': // `CR' register (condition register) number 0 1032 case 'y': // `CR' register (condition register) 1033 case 'z': // `XER[CA]' carry bit (part of the XER register) 1034 Info.setAllowsRegister(); 1035 break; 1036 case 'I': // Signed 16-bit constant 1037 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1038 // (use `L' instead for SImode constants) 1039 case 'K': // Unsigned 16-bit constant 1040 case 'L': // Signed 16-bit constant shifted left 16 bits 1041 case 'M': // Constant larger than 31 1042 case 'N': // Exact power of 2 1043 case 'P': // Constant whose negation is a signed 16-bit constant 1044 case 'G': // Floating point constant that can be loaded into a 1045 // register with one instruction per word 1046 case 'H': // Integer/Floating point constant that can be loaded 1047 // into a register using three instructions 1048 break; 1049 case 'm': // Memory operand. Note that on PowerPC targets, m can 1050 // include addresses that update the base register. It 1051 // is therefore only safe to use `m' in an asm statement 1052 // if that asm statement accesses the operand exactly once. 1053 // The asm statement must also use `%U<opno>' as a 1054 // placeholder for the "update" flag in the corresponding 1055 // load or store instruction. For example: 1056 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1057 // is correct but: 1058 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1059 // is not. Use es rather than m if you don't want the base 1060 // register to be updated. 1061 case 'e': 1062 if (Name[1] != 's') 1063 return false; 1064 // es: A "stable" memory operand; that is, one which does not 1065 // include any automodification of the base register. Unlike 1066 // `m', this constraint can be used in asm statements that 1067 // might access the operand several times, or that might not 1068 // access it at all. 1069 Info.setAllowsMemory(); 1070 Name++; // Skip over 'e'. 1071 break; 1072 case 'Q': // Memory operand that is an offset from a register (it is 1073 // usually better to use `m' or `es' in asm statements) 1074 case 'Z': // Memory operand that is an indexed or indirect from a 1075 // register (it is usually better to use `m' or `es' in 1076 // asm statements) 1077 Info.setAllowsMemory(); 1078 Info.setAllowsRegister(); 1079 break; 1080 case 'R': // AIX TOC entry 1081 case 'a': // Address operand that is an indexed or indirect from a 1082 // register (`p' is preferable for asm statements) 1083 case 'S': // Constant suitable as a 64-bit mask operand 1084 case 'T': // Constant suitable as a 32-bit mask operand 1085 case 'U': // System V Release 4 small data area reference 1086 case 't': // AND masks that can be performed by two rldic{l, r} 1087 // instructions 1088 case 'W': // Vector constant that does not require memory 1089 case 'j': // Vector constant that is all zeros. 1090 break; 1091 // End FIXME. 1092 } 1093 return true; 1094 } 1095 std::string convertConstraint(const char *&Constraint) const override { 1096 std::string R; 1097 switch (*Constraint) { 1098 case 'e': 1099 case 'w': 1100 // Two-character constraint; add "^" hint for later parsing. 1101 R = std::string("^") + std::string(Constraint, 2); 1102 Constraint++; 1103 break; 1104 default: 1105 return TargetInfo::convertConstraint(Constraint); 1106 } 1107 return R; 1108 } 1109 const char *getClobbers() const override { 1110 return ""; 1111 } 1112 int getEHDataRegisterNumber(unsigned RegNo) const override { 1113 if (RegNo == 0) return 3; 1114 if (RegNo == 1) return 4; 1115 return -1; 1116 } 1117 1118 bool hasSjLjLowering() const override { 1119 return true; 1120 } 1121 1122 bool useFloat128ManglingForLongDouble() const override { 1123 return LongDoubleWidth == 128 && 1124 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1125 getTriple().isOSBinFormatELF(); 1126 } 1127 }; 1128 1129 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1130 #define BUILTIN(ID, TYPE, ATTRS) \ 1131 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1132 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1133 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1134 #include "clang/Basic/BuiltinsPPC.def" 1135 }; 1136 1137 /// handleTargetFeatures - Perform initialization based on the user 1138 /// configured set of features. 1139 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1140 DiagnosticsEngine &Diags) { 1141 for (const auto &Feature : Features) { 1142 if (Feature == "+vsx") { 1143 HasVSX = true; 1144 } else if (Feature == "+bpermd") { 1145 HasBPERMD = true; 1146 } else if (Feature == "+extdiv") { 1147 HasExtDiv = true; 1148 } else if (Feature == "+power8-vector") { 1149 HasP8Vector = true; 1150 } else if (Feature == "+crypto") { 1151 HasP8Crypto = true; 1152 } else if (Feature == "+direct-move") { 1153 HasDirectMove = true; 1154 } else if (Feature == "+qpx") { 1155 HasQPX = true; 1156 } else if (Feature == "+htm") { 1157 HasHTM = true; 1158 } else if (Feature == "+float128") { 1159 HasFloat128 = true; 1160 } 1161 // TODO: Finish this list and add an assert that we've handled them 1162 // all. 1163 } 1164 1165 return true; 1166 } 1167 1168 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1169 /// #defines that are not tied to a specific subtarget. 1170 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1171 MacroBuilder &Builder) const { 1172 // Target identification. 1173 Builder.defineMacro("__ppc__"); 1174 Builder.defineMacro("__PPC__"); 1175 Builder.defineMacro("_ARCH_PPC"); 1176 Builder.defineMacro("__powerpc__"); 1177 Builder.defineMacro("__POWERPC__"); 1178 if (PointerWidth == 64) { 1179 Builder.defineMacro("_ARCH_PPC64"); 1180 Builder.defineMacro("__powerpc64__"); 1181 Builder.defineMacro("__ppc64__"); 1182 Builder.defineMacro("__PPC64__"); 1183 } 1184 1185 // Target properties. 1186 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1187 Builder.defineMacro("_LITTLE_ENDIAN"); 1188 } else { 1189 if (getTriple().getOS() != llvm::Triple::NetBSD && 1190 getTriple().getOS() != llvm::Triple::OpenBSD) 1191 Builder.defineMacro("_BIG_ENDIAN"); 1192 } 1193 1194 // ABI options. 1195 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1196 Builder.defineMacro("_CALL_ELF", "1"); 1197 if (ABI == "elfv2") 1198 Builder.defineMacro("_CALL_ELF", "2"); 1199 1200 // Subtarget options. 1201 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1202 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1203 1204 // FIXME: Should be controlled by command line option. 1205 if (LongDoubleWidth == 128) 1206 Builder.defineMacro("__LONG_DOUBLE_128__"); 1207 1208 if (Opts.AltiVec) { 1209 Builder.defineMacro("__VEC__", "10206"); 1210 Builder.defineMacro("__ALTIVEC__"); 1211 } 1212 1213 // CPU identification. 1214 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1215 .Case("440", ArchDefineName) 1216 .Case("450", ArchDefineName | ArchDefine440) 1217 .Case("601", ArchDefineName) 1218 .Case("602", ArchDefineName | ArchDefinePpcgr) 1219 .Case("603", ArchDefineName | ArchDefinePpcgr) 1220 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1221 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1222 .Case("604", ArchDefineName | ArchDefinePpcgr) 1223 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1224 .Case("620", ArchDefineName | ArchDefinePpcgr) 1225 .Case("630", ArchDefineName | ArchDefinePpcgr) 1226 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1227 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1228 .Case("750", ArchDefineName | ArchDefinePpcgr) 1229 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1230 | ArchDefinePpcsq) 1231 .Case("a2", ArchDefineA2) 1232 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1233 .Case("pwr3", ArchDefinePpcgr) 1234 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1235 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1236 | ArchDefinePpcsq) 1237 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1238 | ArchDefinePpcgr | ArchDefinePpcsq) 1239 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1240 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1241 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1242 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1243 | ArchDefinePpcsq) 1244 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1245 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1246 | ArchDefinePpcgr | ArchDefinePpcsq) 1247 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1248 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1249 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1250 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1251 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1252 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1253 | ArchDefinePpcsq) 1254 .Case("power3", ArchDefinePpcgr) 1255 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1256 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1257 | ArchDefinePpcsq) 1258 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1259 | ArchDefinePpcgr | ArchDefinePpcsq) 1260 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1261 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1262 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1263 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1264 | ArchDefinePpcsq) 1265 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1266 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1267 | ArchDefinePpcgr | ArchDefinePpcsq) 1268 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1269 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1270 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1271 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1272 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1273 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1274 | ArchDefinePpcsq) 1275 .Default(ArchDefineNone); 1276 1277 if (defs & ArchDefineName) 1278 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1279 if (defs & ArchDefinePpcgr) 1280 Builder.defineMacro("_ARCH_PPCGR"); 1281 if (defs & ArchDefinePpcsq) 1282 Builder.defineMacro("_ARCH_PPCSQ"); 1283 if (defs & ArchDefine440) 1284 Builder.defineMacro("_ARCH_440"); 1285 if (defs & ArchDefine603) 1286 Builder.defineMacro("_ARCH_603"); 1287 if (defs & ArchDefine604) 1288 Builder.defineMacro("_ARCH_604"); 1289 if (defs & ArchDefinePwr4) 1290 Builder.defineMacro("_ARCH_PWR4"); 1291 if (defs & ArchDefinePwr5) 1292 Builder.defineMacro("_ARCH_PWR5"); 1293 if (defs & ArchDefinePwr5x) 1294 Builder.defineMacro("_ARCH_PWR5X"); 1295 if (defs & ArchDefinePwr6) 1296 Builder.defineMacro("_ARCH_PWR6"); 1297 if (defs & ArchDefinePwr6x) 1298 Builder.defineMacro("_ARCH_PWR6X"); 1299 if (defs & ArchDefinePwr7) 1300 Builder.defineMacro("_ARCH_PWR7"); 1301 if (defs & ArchDefinePwr8) 1302 Builder.defineMacro("_ARCH_PWR8"); 1303 if (defs & ArchDefinePwr9) 1304 Builder.defineMacro("_ARCH_PWR9"); 1305 if (defs & ArchDefineA2) 1306 Builder.defineMacro("_ARCH_A2"); 1307 if (defs & ArchDefineA2q) { 1308 Builder.defineMacro("_ARCH_A2Q"); 1309 Builder.defineMacro("_ARCH_QP"); 1310 } 1311 1312 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1313 Builder.defineMacro("__bg__"); 1314 Builder.defineMacro("__THW_BLUEGENE__"); 1315 Builder.defineMacro("__bgq__"); 1316 Builder.defineMacro("__TOS_BGQ__"); 1317 } 1318 1319 if (HasVSX) 1320 Builder.defineMacro("__VSX__"); 1321 if (HasP8Vector) 1322 Builder.defineMacro("__POWER8_VECTOR__"); 1323 if (HasP8Crypto) 1324 Builder.defineMacro("__CRYPTO__"); 1325 if (HasHTM) 1326 Builder.defineMacro("__HTM__"); 1327 if (HasFloat128) 1328 Builder.defineMacro("__FLOAT128__"); 1329 1330 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1331 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1332 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1333 if (PointerWidth == 64) 1334 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1335 1336 // FIXME: The following are not yet generated here by Clang, but are 1337 // generated by GCC: 1338 // 1339 // _SOFT_FLOAT_ 1340 // __RECIP_PRECISION__ 1341 // __APPLE_ALTIVEC__ 1342 // __RECIP__ 1343 // __RECIPF__ 1344 // __RSQRTE__ 1345 // __RSQRTEF__ 1346 // _SOFT_DOUBLE_ 1347 // __NO_LWSYNC__ 1348 // __HAVE_BSWAP__ 1349 // __LONGDOUBLE128 1350 // __CMODEL_MEDIUM__ 1351 // __CMODEL_LARGE__ 1352 // _CALL_SYSV 1353 // _CALL_DARWIN 1354 // __NO_FPRS__ 1355 } 1356 1357 // Handle explicit options being passed to the compiler here: if we've 1358 // explicitly turned off vsx and turned on power8-vector or direct-move then 1359 // go ahead and error since the customer has expressed a somewhat incompatible 1360 // set of options. 1361 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1362 const std::vector<std::string> &FeaturesVec) { 1363 1364 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1365 FeaturesVec.end()) { 1366 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1367 FeaturesVec.end()) { 1368 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1369 << "-mno-vsx"; 1370 return false; 1371 } 1372 1373 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1374 FeaturesVec.end()) { 1375 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1376 << "-mno-vsx"; 1377 return false; 1378 } 1379 1380 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1381 FeaturesVec.end()) { 1382 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1383 << "-mno-vsx"; 1384 return false; 1385 } 1386 } 1387 1388 return true; 1389 } 1390 1391 bool PPCTargetInfo::initFeatureMap( 1392 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1393 const std::vector<std::string> &FeaturesVec) const { 1394 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1395 .Case("7400", true) 1396 .Case("g4", true) 1397 .Case("7450", true) 1398 .Case("g4+", true) 1399 .Case("970", true) 1400 .Case("g5", true) 1401 .Case("pwr6", true) 1402 .Case("pwr7", true) 1403 .Case("pwr8", true) 1404 .Case("pwr9", true) 1405 .Case("ppc64", true) 1406 .Case("ppc64le", true) 1407 .Default(false); 1408 1409 Features["qpx"] = (CPU == "a2q"); 1410 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1411 .Case("ppc64le", true) 1412 .Case("pwr9", true) 1413 .Case("pwr8", true) 1414 .Default(false); 1415 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1416 .Case("ppc64le", true) 1417 .Case("pwr9", true) 1418 .Case("pwr8", true) 1419 .Default(false); 1420 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1421 .Case("ppc64le", true) 1422 .Case("pwr9", true) 1423 .Case("pwr8", true) 1424 .Case("pwr7", true) 1425 .Default(false); 1426 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1427 .Case("ppc64le", true) 1428 .Case("pwr9", true) 1429 .Case("pwr8", true) 1430 .Case("pwr7", true) 1431 .Default(false); 1432 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1433 .Case("ppc64le", true) 1434 .Case("pwr9", true) 1435 .Case("pwr8", true) 1436 .Default(false); 1437 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1438 .Case("ppc64le", true) 1439 .Case("pwr9", true) 1440 .Case("pwr8", true) 1441 .Case("pwr7", true) 1442 .Default(false); 1443 1444 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1445 return false; 1446 1447 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1448 } 1449 1450 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1451 return llvm::StringSwitch<bool>(Feature) 1452 .Case("powerpc", true) 1453 .Case("vsx", HasVSX) 1454 .Case("power8-vector", HasP8Vector) 1455 .Case("crypto", HasP8Crypto) 1456 .Case("direct-move", HasDirectMove) 1457 .Case("qpx", HasQPX) 1458 .Case("htm", HasHTM) 1459 .Case("bpermd", HasBPERMD) 1460 .Case("extdiv", HasExtDiv) 1461 .Case("float128", HasFloat128) 1462 .Default(false); 1463 } 1464 1465 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1466 StringRef Name, bool Enabled) const { 1467 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1468 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1469 // incompatible options. 1470 if (Enabled) { 1471 if (Name == "direct-move") { 1472 Features[Name] = Features["vsx"] = true; 1473 } else if (Name == "power8-vector") { 1474 Features[Name] = Features["vsx"] = true; 1475 } else if (Name == "float128") { 1476 Features[Name] = Features["vsx"] = true; 1477 } else { 1478 Features[Name] = true; 1479 } 1480 } else { 1481 if (Name == "vsx") { 1482 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1483 Features["float128"] = false; 1484 } else { 1485 Features[Name] = false; 1486 } 1487 } 1488 } 1489 1490 const char * const PPCTargetInfo::GCCRegNames[] = { 1491 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1492 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1493 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1494 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1495 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1496 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1497 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1498 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1499 "mq", "lr", "ctr", "ap", 1500 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1501 "xer", 1502 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1503 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1504 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1505 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1506 "vrsave", "vscr", 1507 "spe_acc", "spefscr", 1508 "sfp" 1509 }; 1510 1511 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1512 return llvm::makeArrayRef(GCCRegNames); 1513 } 1514 1515 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1516 // While some of these aliases do map to different registers 1517 // they still share the same register name. 1518 { { "0" }, "r0" }, 1519 { { "1"}, "r1" }, 1520 { { "2" }, "r2" }, 1521 { { "3" }, "r3" }, 1522 { { "4" }, "r4" }, 1523 { { "5" }, "r5" }, 1524 { { "6" }, "r6" }, 1525 { { "7" }, "r7" }, 1526 { { "8" }, "r8" }, 1527 { { "9" }, "r9" }, 1528 { { "10" }, "r10" }, 1529 { { "11" }, "r11" }, 1530 { { "12" }, "r12" }, 1531 { { "13" }, "r13" }, 1532 { { "14" }, "r14" }, 1533 { { "15" }, "r15" }, 1534 { { "16" }, "r16" }, 1535 { { "17" }, "r17" }, 1536 { { "18" }, "r18" }, 1537 { { "19" }, "r19" }, 1538 { { "20" }, "r20" }, 1539 { { "21" }, "r21" }, 1540 { { "22" }, "r22" }, 1541 { { "23" }, "r23" }, 1542 { { "24" }, "r24" }, 1543 { { "25" }, "r25" }, 1544 { { "26" }, "r26" }, 1545 { { "27" }, "r27" }, 1546 { { "28" }, "r28" }, 1547 { { "29" }, "r29" }, 1548 { { "30" }, "r30" }, 1549 { { "31" }, "r31" }, 1550 { { "fr0" }, "f0" }, 1551 { { "fr1" }, "f1" }, 1552 { { "fr2" }, "f2" }, 1553 { { "fr3" }, "f3" }, 1554 { { "fr4" }, "f4" }, 1555 { { "fr5" }, "f5" }, 1556 { { "fr6" }, "f6" }, 1557 { { "fr7" }, "f7" }, 1558 { { "fr8" }, "f8" }, 1559 { { "fr9" }, "f9" }, 1560 { { "fr10" }, "f10" }, 1561 { { "fr11" }, "f11" }, 1562 { { "fr12" }, "f12" }, 1563 { { "fr13" }, "f13" }, 1564 { { "fr14" }, "f14" }, 1565 { { "fr15" }, "f15" }, 1566 { { "fr16" }, "f16" }, 1567 { { "fr17" }, "f17" }, 1568 { { "fr18" }, "f18" }, 1569 { { "fr19" }, "f19" }, 1570 { { "fr20" }, "f20" }, 1571 { { "fr21" }, "f21" }, 1572 { { "fr22" }, "f22" }, 1573 { { "fr23" }, "f23" }, 1574 { { "fr24" }, "f24" }, 1575 { { "fr25" }, "f25" }, 1576 { { "fr26" }, "f26" }, 1577 { { "fr27" }, "f27" }, 1578 { { "fr28" }, "f28" }, 1579 { { "fr29" }, "f29" }, 1580 { { "fr30" }, "f30" }, 1581 { { "fr31" }, "f31" }, 1582 { { "cc" }, "cr0" }, 1583 }; 1584 1585 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1586 return llvm::makeArrayRef(GCCRegAliases); 1587 } 1588 1589 class PPC32TargetInfo : public PPCTargetInfo { 1590 public: 1591 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1592 : PPCTargetInfo(Triple, Opts) { 1593 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1594 1595 switch (getTriple().getOS()) { 1596 case llvm::Triple::Linux: 1597 case llvm::Triple::FreeBSD: 1598 case llvm::Triple::NetBSD: 1599 SizeType = UnsignedInt; 1600 PtrDiffType = SignedInt; 1601 IntPtrType = SignedInt; 1602 break; 1603 default: 1604 break; 1605 } 1606 1607 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1608 LongDoubleWidth = LongDoubleAlign = 64; 1609 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1610 } 1611 1612 // PPC32 supports atomics up to 4 bytes. 1613 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1614 } 1615 1616 BuiltinVaListKind getBuiltinVaListKind() const override { 1617 // This is the ELF definition, and is overridden by the Darwin sub-target 1618 return TargetInfo::PowerABIBuiltinVaList; 1619 } 1620 }; 1621 1622 // Note: ABI differences may eventually require us to have a separate 1623 // TargetInfo for little endian. 1624 class PPC64TargetInfo : public PPCTargetInfo { 1625 public: 1626 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1627 : PPCTargetInfo(Triple, Opts) { 1628 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1629 IntMaxType = SignedLong; 1630 Int64Type = SignedLong; 1631 1632 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1633 resetDataLayout("e-m:e-i64:64-n32:64"); 1634 ABI = "elfv2"; 1635 } else { 1636 resetDataLayout("E-m:e-i64:64-n32:64"); 1637 ABI = "elfv1"; 1638 } 1639 1640 switch (getTriple().getOS()) { 1641 case llvm::Triple::FreeBSD: 1642 LongDoubleWidth = LongDoubleAlign = 64; 1643 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1644 break; 1645 case llvm::Triple::NetBSD: 1646 IntMaxType = SignedLongLong; 1647 Int64Type = SignedLongLong; 1648 break; 1649 default: 1650 break; 1651 } 1652 1653 // PPC64 supports atomics up to 8 bytes. 1654 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1655 } 1656 BuiltinVaListKind getBuiltinVaListKind() const override { 1657 return TargetInfo::CharPtrBuiltinVaList; 1658 } 1659 // PPC64 Linux-specific ABI options. 1660 bool setABI(const std::string &Name) override { 1661 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1662 ABI = Name; 1663 return true; 1664 } 1665 return false; 1666 } 1667 }; 1668 1669 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1670 public: 1671 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1672 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1673 HasAlignMac68kSupport = true; 1674 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1675 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1676 LongLongAlign = 32; 1677 SuitableAlign = 128; 1678 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1679 } 1680 BuiltinVaListKind getBuiltinVaListKind() const override { 1681 return TargetInfo::CharPtrBuiltinVaList; 1682 } 1683 }; 1684 1685 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1686 public: 1687 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1688 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1689 HasAlignMac68kSupport = true; 1690 SuitableAlign = 128; 1691 resetDataLayout("E-m:o-i64:64-n32:64"); 1692 } 1693 }; 1694 1695 static const unsigned NVPTXAddrSpaceMap[] = { 1696 1, // opencl_global 1697 3, // opencl_local 1698 4, // opencl_constant 1699 // FIXME: generic has to be added to the target 1700 0, // opencl_generic 1701 1, // cuda_device 1702 4, // cuda_constant 1703 3, // cuda_shared 1704 }; 1705 1706 class NVPTXTargetInfo : public TargetInfo { 1707 static const char *const GCCRegNames[]; 1708 static const Builtin::Info BuiltinInfo[]; 1709 CudaArch GPU; 1710 1711 public: 1712 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1713 : TargetInfo(Triple) { 1714 BigEndian = false; 1715 TLSSupported = false; 1716 LongWidth = LongAlign = 64; 1717 AddrSpaceMap = &NVPTXAddrSpaceMap; 1718 UseAddrSpaceMapMangling = true; 1719 // Define available target features 1720 // These must be defined in sorted order! 1721 NoAsmVariants = true; 1722 GPU = CudaArch::SM_20; 1723 1724 // If possible, get a TargetInfo for our host triple, so we can match its 1725 // types. 1726 llvm::Triple HostTriple(Opts.HostTriple); 1727 if (HostTriple.isNVPTX()) 1728 return; 1729 std::unique_ptr<TargetInfo> HostTarget( 1730 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1731 if (!HostTarget) { 1732 return; 1733 } 1734 1735 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1736 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1737 BoolWidth = HostTarget->getBoolWidth(); 1738 BoolAlign = HostTarget->getBoolAlign(); 1739 IntWidth = HostTarget->getIntWidth(); 1740 IntAlign = HostTarget->getIntAlign(); 1741 HalfWidth = HostTarget->getHalfWidth(); 1742 HalfAlign = HostTarget->getHalfAlign(); 1743 FloatWidth = HostTarget->getFloatWidth(); 1744 FloatAlign = HostTarget->getFloatAlign(); 1745 DoubleWidth = HostTarget->getDoubleWidth(); 1746 DoubleAlign = HostTarget->getDoubleAlign(); 1747 LongWidth = HostTarget->getLongWidth(); 1748 LongAlign = HostTarget->getLongAlign(); 1749 LongLongWidth = HostTarget->getLongLongWidth(); 1750 LongLongAlign = HostTarget->getLongLongAlign(); 1751 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1752 DefaultAlignForAttributeAligned = 1753 HostTarget->getDefaultAlignForAttributeAligned(); 1754 SizeType = HostTarget->getSizeType(); 1755 IntMaxType = HostTarget->getIntMaxType(); 1756 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1757 IntPtrType = HostTarget->getIntPtrType(); 1758 WCharType = HostTarget->getWCharType(); 1759 WIntType = HostTarget->getWIntType(); 1760 Char16Type = HostTarget->getChar16Type(); 1761 Char32Type = HostTarget->getChar32Type(); 1762 Int64Type = HostTarget->getInt64Type(); 1763 SigAtomicType = HostTarget->getSigAtomicType(); 1764 ProcessIDType = HostTarget->getProcessIDType(); 1765 1766 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1767 UseZeroLengthBitfieldAlignment = 1768 HostTarget->useZeroLengthBitfieldAlignment(); 1769 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1770 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1771 1772 // Properties intentionally not copied from host: 1773 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1774 // host/device boundary. 1775 // - SuitableAlign: Not visible across the host/device boundary, and may 1776 // correctly be different on host/device, e.g. if host has wider vector 1777 // types than device. 1778 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1779 // as its double type, but that's not necessarily true on the host. 1780 // TODO: nvcc emits a warning when using long double on device; we should 1781 // do the same. 1782 } 1783 void getTargetDefines(const LangOptions &Opts, 1784 MacroBuilder &Builder) const override { 1785 Builder.defineMacro("__PTX__"); 1786 Builder.defineMacro("__NVPTX__"); 1787 if (Opts.CUDAIsDevice) { 1788 // Set __CUDA_ARCH__ for the GPU specified. 1789 std::string CUDAArchCode = [this] { 1790 switch (GPU) { 1791 case CudaArch::UNKNOWN: 1792 assert(false && "No GPU arch when compiling CUDA device code."); 1793 return ""; 1794 case CudaArch::SM_20: 1795 return "200"; 1796 case CudaArch::SM_21: 1797 return "210"; 1798 case CudaArch::SM_30: 1799 return "300"; 1800 case CudaArch::SM_32: 1801 return "320"; 1802 case CudaArch::SM_35: 1803 return "350"; 1804 case CudaArch::SM_37: 1805 return "370"; 1806 case CudaArch::SM_50: 1807 return "500"; 1808 case CudaArch::SM_52: 1809 return "520"; 1810 case CudaArch::SM_53: 1811 return "530"; 1812 case CudaArch::SM_60: 1813 return "600"; 1814 case CudaArch::SM_61: 1815 return "610"; 1816 case CudaArch::SM_62: 1817 return "620"; 1818 } 1819 llvm_unreachable("unhandled CudaArch"); 1820 }(); 1821 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1822 } 1823 } 1824 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1825 return llvm::makeArrayRef(BuiltinInfo, 1826 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1827 } 1828 bool hasFeature(StringRef Feature) const override { 1829 return Feature == "ptx" || Feature == "nvptx"; 1830 } 1831 1832 ArrayRef<const char *> getGCCRegNames() const override; 1833 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1834 // No aliases. 1835 return None; 1836 } 1837 bool validateAsmConstraint(const char *&Name, 1838 TargetInfo::ConstraintInfo &Info) const override { 1839 switch (*Name) { 1840 default: 1841 return false; 1842 case 'c': 1843 case 'h': 1844 case 'r': 1845 case 'l': 1846 case 'f': 1847 case 'd': 1848 Info.setAllowsRegister(); 1849 return true; 1850 } 1851 } 1852 const char *getClobbers() const override { 1853 // FIXME: Is this really right? 1854 return ""; 1855 } 1856 BuiltinVaListKind getBuiltinVaListKind() const override { 1857 // FIXME: implement 1858 return TargetInfo::CharPtrBuiltinVaList; 1859 } 1860 bool setCPU(const std::string &Name) override { 1861 GPU = StringToCudaArch(Name); 1862 return GPU != CudaArch::UNKNOWN; 1863 } 1864 void setSupportedOpenCLOpts() override { 1865 auto &Opts = getSupportedOpenCLOpts(); 1866 Opts.cl_clang_storage_class_specifiers = 1; 1867 Opts.cl_khr_gl_sharing = 1; 1868 Opts.cl_khr_icd = 1; 1869 1870 Opts.cl_khr_fp64 = 1; 1871 Opts.cl_khr_byte_addressable_store = 1; 1872 Opts.cl_khr_global_int32_base_atomics = 1; 1873 Opts.cl_khr_global_int32_extended_atomics = 1; 1874 Opts.cl_khr_local_int32_base_atomics = 1; 1875 Opts.cl_khr_local_int32_extended_atomics = 1; 1876 } 1877 }; 1878 1879 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1880 #define BUILTIN(ID, TYPE, ATTRS) \ 1881 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1882 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1883 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1884 #include "clang/Basic/BuiltinsNVPTX.def" 1885 }; 1886 1887 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1888 1889 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1890 return llvm::makeArrayRef(GCCRegNames); 1891 } 1892 1893 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1894 public: 1895 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1896 : NVPTXTargetInfo(Triple, Opts) { 1897 LongWidth = LongAlign = 32; 1898 PointerWidth = PointerAlign = 32; 1899 SizeType = TargetInfo::UnsignedInt; 1900 PtrDiffType = TargetInfo::SignedInt; 1901 IntPtrType = TargetInfo::SignedInt; 1902 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1903 } 1904 }; 1905 1906 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1907 public: 1908 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1909 : NVPTXTargetInfo(Triple, Opts) { 1910 PointerWidth = PointerAlign = 64; 1911 SizeType = TargetInfo::UnsignedLong; 1912 PtrDiffType = TargetInfo::SignedLong; 1913 IntPtrType = TargetInfo::SignedLong; 1914 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1915 } 1916 }; 1917 1918 static const unsigned AMDGPUAddrSpaceMap[] = { 1919 1, // opencl_global 1920 3, // opencl_local 1921 2, // opencl_constant 1922 4, // opencl_generic 1923 1, // cuda_device 1924 2, // cuda_constant 1925 3 // cuda_shared 1926 }; 1927 1928 // If you edit the description strings, make sure you update 1929 // getPointerWidthV(). 1930 1931 static const char *const DataLayoutStringR600 = 1932 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1933 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1934 1935 static const char *const DataLayoutStringSI = 1936 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 1937 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1938 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1939 1940 class AMDGPUTargetInfo final : public TargetInfo { 1941 static const Builtin::Info BuiltinInfo[]; 1942 static const char * const GCCRegNames[]; 1943 1944 /// \brief The GPU profiles supported by the AMDGPU target. 1945 enum GPUKind { 1946 GK_NONE, 1947 GK_R600, 1948 GK_R600_DOUBLE_OPS, 1949 GK_R700, 1950 GK_R700_DOUBLE_OPS, 1951 GK_EVERGREEN, 1952 GK_EVERGREEN_DOUBLE_OPS, 1953 GK_NORTHERN_ISLANDS, 1954 GK_CAYMAN, 1955 GK_SOUTHERN_ISLANDS, 1956 GK_SEA_ISLANDS, 1957 GK_VOLCANIC_ISLANDS 1958 } GPU; 1959 1960 bool hasFP64:1; 1961 bool hasFMAF:1; 1962 bool hasLDEXPF:1; 1963 1964 static bool isAMDGCN(const llvm::Triple &TT) { 1965 return TT.getArch() == llvm::Triple::amdgcn; 1966 } 1967 1968 public: 1969 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 1970 : TargetInfo(Triple) , 1971 GPU(isAMDGCN(Triple) ? GK_SOUTHERN_ISLANDS : GK_R600), 1972 hasFP64(false), 1973 hasFMAF(false), 1974 hasLDEXPF(false) { 1975 if (getTriple().getArch() == llvm::Triple::amdgcn) { 1976 hasFP64 = true; 1977 hasFMAF = true; 1978 hasLDEXPF = true; 1979 } 1980 1981 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 1982 DataLayoutStringSI : DataLayoutStringR600); 1983 1984 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1985 UseAddrSpaceMapMangling = true; 1986 } 1987 1988 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1989 if (GPU <= GK_CAYMAN) 1990 return 32; 1991 1992 switch(AddrSpace) { 1993 default: 1994 return 64; 1995 case 0: 1996 case 3: 1997 case 5: 1998 return 32; 1999 } 2000 } 2001 2002 const char * getClobbers() const override { 2003 return ""; 2004 } 2005 2006 ArrayRef<const char *> getGCCRegNames() const override; 2007 2008 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2009 return None; 2010 } 2011 2012 bool validateAsmConstraint(const char *&Name, 2013 TargetInfo::ConstraintInfo &Info) const override { 2014 switch (*Name) { 2015 default: break; 2016 case 'v': // vgpr 2017 case 's': // sgpr 2018 Info.setAllowsRegister(); 2019 return true; 2020 } 2021 return false; 2022 } 2023 2024 bool initFeatureMap(llvm::StringMap<bool> &Features, 2025 DiagnosticsEngine &Diags, StringRef CPU, 2026 const std::vector<std::string> &FeatureVec) const override; 2027 2028 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2029 return llvm::makeArrayRef(BuiltinInfo, 2030 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2031 } 2032 2033 void getTargetDefines(const LangOptions &Opts, 2034 MacroBuilder &Builder) const override { 2035 if (getTriple().getArch() == llvm::Triple::amdgcn) 2036 Builder.defineMacro("__AMDGCN__"); 2037 else 2038 Builder.defineMacro("__R600__"); 2039 2040 if (hasFMAF) 2041 Builder.defineMacro("__HAS_FMAF__"); 2042 if (hasLDEXPF) 2043 Builder.defineMacro("__HAS_LDEXPF__"); 2044 if (hasFP64) 2045 Builder.defineMacro("__HAS_FP64__"); 2046 } 2047 2048 BuiltinVaListKind getBuiltinVaListKind() const override { 2049 return TargetInfo::CharPtrBuiltinVaList; 2050 } 2051 2052 static GPUKind parseR600Name(StringRef Name) { 2053 return llvm::StringSwitch<GPUKind>(Name) 2054 .Case("r600" , GK_R600) 2055 .Case("rv610", GK_R600) 2056 .Case("rv620", GK_R600) 2057 .Case("rv630", GK_R600) 2058 .Case("rv635", GK_R600) 2059 .Case("rs780", GK_R600) 2060 .Case("rs880", GK_R600) 2061 .Case("rv670", GK_R600_DOUBLE_OPS) 2062 .Case("rv710", GK_R700) 2063 .Case("rv730", GK_R700) 2064 .Case("rv740", GK_R700_DOUBLE_OPS) 2065 .Case("rv770", GK_R700_DOUBLE_OPS) 2066 .Case("palm", GK_EVERGREEN) 2067 .Case("cedar", GK_EVERGREEN) 2068 .Case("sumo", GK_EVERGREEN) 2069 .Case("sumo2", GK_EVERGREEN) 2070 .Case("redwood", GK_EVERGREEN) 2071 .Case("juniper", GK_EVERGREEN) 2072 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2073 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2074 .Case("barts", GK_NORTHERN_ISLANDS) 2075 .Case("turks", GK_NORTHERN_ISLANDS) 2076 .Case("caicos", GK_NORTHERN_ISLANDS) 2077 .Case("cayman", GK_CAYMAN) 2078 .Case("aruba", GK_CAYMAN) 2079 .Default(GK_NONE); 2080 } 2081 2082 static GPUKind parseAMDGCNName(StringRef Name) { 2083 return llvm::StringSwitch<GPUKind>(Name) 2084 .Case("tahiti", GK_SOUTHERN_ISLANDS) 2085 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 2086 .Case("verde", GK_SOUTHERN_ISLANDS) 2087 .Case("oland", GK_SOUTHERN_ISLANDS) 2088 .Case("hainan", GK_SOUTHERN_ISLANDS) 2089 .Case("bonaire", GK_SEA_ISLANDS) 2090 .Case("kabini", GK_SEA_ISLANDS) 2091 .Case("kaveri", GK_SEA_ISLANDS) 2092 .Case("hawaii", GK_SEA_ISLANDS) 2093 .Case("mullins", GK_SEA_ISLANDS) 2094 .Case("tonga", GK_VOLCANIC_ISLANDS) 2095 .Case("iceland", GK_VOLCANIC_ISLANDS) 2096 .Case("carrizo", GK_VOLCANIC_ISLANDS) 2097 .Case("fiji", GK_VOLCANIC_ISLANDS) 2098 .Case("stoney", GK_VOLCANIC_ISLANDS) 2099 .Default(GK_NONE); 2100 } 2101 2102 bool setCPU(const std::string &Name) override { 2103 if (getTriple().getArch() == llvm::Triple::amdgcn) 2104 GPU = parseAMDGCNName(Name); 2105 else 2106 GPU = parseR600Name(Name); 2107 2108 return GPU != GK_NONE; 2109 } 2110 2111 void setSupportedOpenCLOpts() override { 2112 auto &Opts = getSupportedOpenCLOpts(); 2113 Opts.cl_clang_storage_class_specifiers = 1; 2114 Opts.cl_khr_icd = 1; 2115 2116 if (hasFP64) 2117 Opts.cl_khr_fp64 = 1; 2118 if (GPU >= GK_EVERGREEN) { 2119 Opts.cl_khr_byte_addressable_store = 1; 2120 Opts.cl_khr_global_int32_base_atomics = 1; 2121 Opts.cl_khr_global_int32_extended_atomics = 1; 2122 Opts.cl_khr_local_int32_base_atomics = 1; 2123 Opts.cl_khr_local_int32_extended_atomics = 1; 2124 } 2125 if (GPU >= GK_SOUTHERN_ISLANDS) { 2126 Opts.cl_khr_fp16 = 1; 2127 Opts.cl_khr_int64_base_atomics = 1; 2128 Opts.cl_khr_int64_extended_atomics = 1; 2129 Opts.cl_khr_3d_image_writes = 1; 2130 } 2131 } 2132 2133 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2134 switch (CC) { 2135 default: 2136 return CCCR_Warning; 2137 case CC_C: 2138 case CC_OpenCLKernel: 2139 return CCCR_OK; 2140 } 2141 } 2142 }; 2143 2144 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2145 #define BUILTIN(ID, TYPE, ATTRS) \ 2146 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2147 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2148 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2149 #include "clang/Basic/BuiltinsAMDGPU.def" 2150 }; 2151 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2152 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2153 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2154 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2155 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2156 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2157 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2158 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2159 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2160 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2161 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2162 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2163 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2164 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2165 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2166 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2167 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2168 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2169 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2170 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2171 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2172 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2173 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2174 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2175 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2176 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2177 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2178 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2179 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2180 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2181 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2182 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2183 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2184 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2185 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2186 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2187 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2188 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2189 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2190 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2191 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2192 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2193 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2194 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2195 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2196 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2197 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2198 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2199 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2200 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2201 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2202 }; 2203 2204 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2205 return llvm::makeArrayRef(GCCRegNames); 2206 } 2207 2208 bool AMDGPUTargetInfo::initFeatureMap( 2209 llvm::StringMap<bool> &Features, 2210 DiagnosticsEngine &Diags, StringRef CPU, 2211 const std::vector<std::string> &FeatureVec) const { 2212 2213 // XXX - What does the member GPU mean if device name string passed here? 2214 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2215 if (CPU.empty()) 2216 CPU = "tahiti"; 2217 2218 switch (parseAMDGCNName(CPU)) { 2219 case GK_SOUTHERN_ISLANDS: 2220 case GK_SEA_ISLANDS: 2221 break; 2222 2223 case GK_VOLCANIC_ISLANDS: 2224 Features["s-memrealtime"] = true; 2225 Features["16-bit-insts"] = true; 2226 break; 2227 2228 case GK_NONE: 2229 return false; 2230 default: 2231 llvm_unreachable("unhandled subtarget"); 2232 } 2233 } else { 2234 if (CPU.empty()) 2235 CPU = "r600"; 2236 2237 switch (parseR600Name(CPU)) { 2238 case GK_R600: 2239 case GK_R700: 2240 case GK_EVERGREEN: 2241 case GK_NORTHERN_ISLANDS: 2242 break; 2243 case GK_R600_DOUBLE_OPS: 2244 case GK_R700_DOUBLE_OPS: 2245 case GK_EVERGREEN_DOUBLE_OPS: 2246 case GK_CAYMAN: 2247 Features["fp64"] = true; 2248 break; 2249 case GK_NONE: 2250 return false; 2251 default: 2252 llvm_unreachable("unhandled subtarget"); 2253 } 2254 } 2255 2256 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2257 } 2258 2259 // Namespace for x86 abstract base class 2260 const Builtin::Info BuiltinInfo[] = { 2261 #define BUILTIN(ID, TYPE, ATTRS) \ 2262 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2263 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2264 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2265 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2266 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2267 #include "clang/Basic/BuiltinsX86.def" 2268 }; 2269 2270 static const char* const GCCRegNames[] = { 2271 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2272 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2273 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2274 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2275 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2276 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2277 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2278 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2279 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2280 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2281 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2282 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2283 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2284 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2285 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2286 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2287 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2288 }; 2289 2290 const TargetInfo::AddlRegName AddlRegNames[] = { 2291 { { "al", "ah", "eax", "rax" }, 0 }, 2292 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2293 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2294 { { "dl", "dh", "edx", "rdx" }, 1 }, 2295 { { "esi", "rsi" }, 4 }, 2296 { { "edi", "rdi" }, 5 }, 2297 { { "esp", "rsp" }, 7 }, 2298 { { "ebp", "rbp" }, 6 }, 2299 { { "r8d", "r8w", "r8b" }, 38 }, 2300 { { "r9d", "r9w", "r9b" }, 39 }, 2301 { { "r10d", "r10w", "r10b" }, 40 }, 2302 { { "r11d", "r11w", "r11b" }, 41 }, 2303 { { "r12d", "r12w", "r12b" }, 42 }, 2304 { { "r13d", "r13w", "r13b" }, 43 }, 2305 { { "r14d", "r14w", "r14b" }, 44 }, 2306 { { "r15d", "r15w", "r15b" }, 45 }, 2307 }; 2308 2309 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2310 // most of the implementation can be shared. 2311 class X86TargetInfo : public TargetInfo { 2312 enum X86SSEEnum { 2313 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2314 } SSELevel = NoSSE; 2315 enum MMX3DNowEnum { 2316 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2317 } MMX3DNowLevel = NoMMX3DNow; 2318 enum XOPEnum { 2319 NoXOP, 2320 SSE4A, 2321 FMA4, 2322 XOP 2323 } XOPLevel = NoXOP; 2324 2325 bool HasAES = false; 2326 bool HasPCLMUL = false; 2327 bool HasLZCNT = false; 2328 bool HasRDRND = false; 2329 bool HasFSGSBASE = false; 2330 bool HasBMI = false; 2331 bool HasBMI2 = false; 2332 bool HasPOPCNT = false; 2333 bool HasRTM = false; 2334 bool HasPRFCHW = false; 2335 bool HasRDSEED = false; 2336 bool HasADX = false; 2337 bool HasTBM = false; 2338 bool HasFMA = false; 2339 bool HasF16C = false; 2340 bool HasAVX512CD = false; 2341 bool HasAVX512ER = false; 2342 bool HasAVX512PF = false; 2343 bool HasAVX512DQ = false; 2344 bool HasAVX512BW = false; 2345 bool HasAVX512VL = false; 2346 bool HasAVX512VBMI = false; 2347 bool HasAVX512IFMA = false; 2348 bool HasSHA = false; 2349 bool HasMPX = false; 2350 bool HasSGX = false; 2351 bool HasCX16 = false; 2352 bool HasFXSR = false; 2353 bool HasXSAVE = false; 2354 bool HasXSAVEOPT = false; 2355 bool HasXSAVEC = false; 2356 bool HasXSAVES = false; 2357 bool HasMWAITX = false; 2358 bool HasPKU = false; 2359 bool HasCLFLUSHOPT = false; 2360 bool HasPCOMMIT = false; 2361 bool HasCLWB = false; 2362 bool HasUMIP = false; 2363 bool HasMOVBE = false; 2364 bool HasPREFETCHWT1 = false; 2365 2366 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2367 /// 2368 /// Each enumeration represents a particular CPU supported by Clang. These 2369 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2370 enum CPUKind { 2371 CK_Generic, 2372 2373 /// \name i386 2374 /// i386-generation processors. 2375 //@{ 2376 CK_i386, 2377 //@} 2378 2379 /// \name i486 2380 /// i486-generation processors. 2381 //@{ 2382 CK_i486, 2383 CK_WinChipC6, 2384 CK_WinChip2, 2385 CK_C3, 2386 //@} 2387 2388 /// \name i586 2389 /// i586-generation processors, P5 microarchitecture based. 2390 //@{ 2391 CK_i586, 2392 CK_Pentium, 2393 CK_PentiumMMX, 2394 //@} 2395 2396 /// \name i686 2397 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2398 //@{ 2399 CK_i686, 2400 CK_PentiumPro, 2401 CK_Pentium2, 2402 CK_Pentium3, 2403 CK_Pentium3M, 2404 CK_PentiumM, 2405 CK_C3_2, 2406 2407 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2408 /// Clang however has some logic to suport this. 2409 // FIXME: Warn, deprecate, and potentially remove this. 2410 CK_Yonah, 2411 //@} 2412 2413 /// \name Netburst 2414 /// Netburst microarchitecture based processors. 2415 //@{ 2416 CK_Pentium4, 2417 CK_Pentium4M, 2418 CK_Prescott, 2419 CK_Nocona, 2420 //@} 2421 2422 /// \name Core 2423 /// Core microarchitecture based processors. 2424 //@{ 2425 CK_Core2, 2426 2427 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2428 /// codename which GCC no longer accepts as an option to -march, but Clang 2429 /// has some logic for recognizing it. 2430 // FIXME: Warn, deprecate, and potentially remove this. 2431 CK_Penryn, 2432 //@} 2433 2434 /// \name Atom 2435 /// Atom processors 2436 //@{ 2437 CK_Bonnell, 2438 CK_Silvermont, 2439 //@} 2440 2441 /// \name Nehalem 2442 /// Nehalem microarchitecture based processors. 2443 CK_Nehalem, 2444 2445 /// \name Westmere 2446 /// Westmere microarchitecture based processors. 2447 CK_Westmere, 2448 2449 /// \name Sandy Bridge 2450 /// Sandy Bridge microarchitecture based processors. 2451 CK_SandyBridge, 2452 2453 /// \name Ivy Bridge 2454 /// Ivy Bridge microarchitecture based processors. 2455 CK_IvyBridge, 2456 2457 /// \name Haswell 2458 /// Haswell microarchitecture based processors. 2459 CK_Haswell, 2460 2461 /// \name Broadwell 2462 /// Broadwell microarchitecture based processors. 2463 CK_Broadwell, 2464 2465 /// \name Skylake Client 2466 /// Skylake client microarchitecture based processors. 2467 CK_SkylakeClient, 2468 2469 /// \name Skylake Server 2470 /// Skylake server microarchitecture based processors. 2471 CK_SkylakeServer, 2472 2473 /// \name Cannonlake Client 2474 /// Cannonlake client microarchitecture based processors. 2475 CK_Cannonlake, 2476 2477 /// \name Knights Landing 2478 /// Knights Landing processor. 2479 CK_KNL, 2480 2481 /// \name Lakemont 2482 /// Lakemont microarchitecture based processors. 2483 CK_Lakemont, 2484 2485 /// \name K6 2486 /// K6 architecture processors. 2487 //@{ 2488 CK_K6, 2489 CK_K6_2, 2490 CK_K6_3, 2491 //@} 2492 2493 /// \name K7 2494 /// K7 architecture processors. 2495 //@{ 2496 CK_Athlon, 2497 CK_AthlonThunderbird, 2498 CK_Athlon4, 2499 CK_AthlonXP, 2500 CK_AthlonMP, 2501 //@} 2502 2503 /// \name K8 2504 /// K8 architecture processors. 2505 //@{ 2506 CK_Athlon64, 2507 CK_Athlon64SSE3, 2508 CK_AthlonFX, 2509 CK_K8, 2510 CK_K8SSE3, 2511 CK_Opteron, 2512 CK_OpteronSSE3, 2513 CK_AMDFAM10, 2514 //@} 2515 2516 /// \name Bobcat 2517 /// Bobcat architecture processors. 2518 //@{ 2519 CK_BTVER1, 2520 CK_BTVER2, 2521 //@} 2522 2523 /// \name Bulldozer 2524 /// Bulldozer architecture processors. 2525 //@{ 2526 CK_BDVER1, 2527 CK_BDVER2, 2528 CK_BDVER3, 2529 CK_BDVER4, 2530 //@} 2531 2532 /// This specification is deprecated and will be removed in the future. 2533 /// Users should prefer \see CK_K8. 2534 // FIXME: Warn on this when the CPU is set to it. 2535 //@{ 2536 CK_x86_64, 2537 //@} 2538 2539 /// \name Geode 2540 /// Geode processors. 2541 //@{ 2542 CK_Geode 2543 //@} 2544 } CPU = CK_Generic; 2545 2546 CPUKind getCPUKind(StringRef CPU) const { 2547 return llvm::StringSwitch<CPUKind>(CPU) 2548 .Case("i386", CK_i386) 2549 .Case("i486", CK_i486) 2550 .Case("winchip-c6", CK_WinChipC6) 2551 .Case("winchip2", CK_WinChip2) 2552 .Case("c3", CK_C3) 2553 .Case("i586", CK_i586) 2554 .Case("pentium", CK_Pentium) 2555 .Case("pentium-mmx", CK_PentiumMMX) 2556 .Case("i686", CK_i686) 2557 .Case("pentiumpro", CK_PentiumPro) 2558 .Case("pentium2", CK_Pentium2) 2559 .Case("pentium3", CK_Pentium3) 2560 .Case("pentium3m", CK_Pentium3M) 2561 .Case("pentium-m", CK_PentiumM) 2562 .Case("c3-2", CK_C3_2) 2563 .Case("yonah", CK_Yonah) 2564 .Case("pentium4", CK_Pentium4) 2565 .Case("pentium4m", CK_Pentium4M) 2566 .Case("prescott", CK_Prescott) 2567 .Case("nocona", CK_Nocona) 2568 .Case("core2", CK_Core2) 2569 .Case("penryn", CK_Penryn) 2570 .Case("bonnell", CK_Bonnell) 2571 .Case("atom", CK_Bonnell) // Legacy name. 2572 .Case("silvermont", CK_Silvermont) 2573 .Case("slm", CK_Silvermont) // Legacy name. 2574 .Case("nehalem", CK_Nehalem) 2575 .Case("corei7", CK_Nehalem) // Legacy name. 2576 .Case("westmere", CK_Westmere) 2577 .Case("sandybridge", CK_SandyBridge) 2578 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2579 .Case("ivybridge", CK_IvyBridge) 2580 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2581 .Case("haswell", CK_Haswell) 2582 .Case("core-avx2", CK_Haswell) // Legacy name. 2583 .Case("broadwell", CK_Broadwell) 2584 .Case("skylake", CK_SkylakeClient) 2585 .Case("skylake-avx512", CK_SkylakeServer) 2586 .Case("skx", CK_SkylakeServer) // Legacy name. 2587 .Case("cannonlake", CK_Cannonlake) 2588 .Case("knl", CK_KNL) 2589 .Case("lakemont", CK_Lakemont) 2590 .Case("k6", CK_K6) 2591 .Case("k6-2", CK_K6_2) 2592 .Case("k6-3", CK_K6_3) 2593 .Case("athlon", CK_Athlon) 2594 .Case("athlon-tbird", CK_AthlonThunderbird) 2595 .Case("athlon-4", CK_Athlon4) 2596 .Case("athlon-xp", CK_AthlonXP) 2597 .Case("athlon-mp", CK_AthlonMP) 2598 .Case("athlon64", CK_Athlon64) 2599 .Case("athlon64-sse3", CK_Athlon64SSE3) 2600 .Case("athlon-fx", CK_AthlonFX) 2601 .Case("k8", CK_K8) 2602 .Case("k8-sse3", CK_K8SSE3) 2603 .Case("opteron", CK_Opteron) 2604 .Case("opteron-sse3", CK_OpteronSSE3) 2605 .Case("barcelona", CK_AMDFAM10) 2606 .Case("amdfam10", CK_AMDFAM10) 2607 .Case("btver1", CK_BTVER1) 2608 .Case("btver2", CK_BTVER2) 2609 .Case("bdver1", CK_BDVER1) 2610 .Case("bdver2", CK_BDVER2) 2611 .Case("bdver3", CK_BDVER3) 2612 .Case("bdver4", CK_BDVER4) 2613 .Case("x86-64", CK_x86_64) 2614 .Case("geode", CK_Geode) 2615 .Default(CK_Generic); 2616 } 2617 2618 enum FPMathKind { 2619 FP_Default, 2620 FP_SSE, 2621 FP_387 2622 } FPMath = FP_Default; 2623 2624 public: 2625 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2626 : TargetInfo(Triple) { 2627 BigEndian = false; 2628 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2629 } 2630 unsigned getFloatEvalMethod() const override { 2631 // X87 evaluates with 80 bits "long double" precision. 2632 return SSELevel == NoSSE ? 2 : 0; 2633 } 2634 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2635 return llvm::makeArrayRef(BuiltinInfo, 2636 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2637 } 2638 ArrayRef<const char *> getGCCRegNames() const override { 2639 return llvm::makeArrayRef(GCCRegNames); 2640 } 2641 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2642 return None; 2643 } 2644 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2645 return llvm::makeArrayRef(AddlRegNames); 2646 } 2647 bool validateCpuSupports(StringRef Name) const override; 2648 bool validateAsmConstraint(const char *&Name, 2649 TargetInfo::ConstraintInfo &info) const override; 2650 2651 bool validateGlobalRegisterVariable(StringRef RegName, 2652 unsigned RegSize, 2653 bool &HasSizeMismatch) const override { 2654 // esp and ebp are the only 32-bit registers the x86 backend can currently 2655 // handle. 2656 if (RegName.equals("esp") || RegName.equals("ebp")) { 2657 // Check that the register size is 32-bit. 2658 HasSizeMismatch = RegSize != 32; 2659 return true; 2660 } 2661 2662 return false; 2663 } 2664 2665 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2666 2667 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2668 2669 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2670 2671 std::string convertConstraint(const char *&Constraint) const override; 2672 const char *getClobbers() const override { 2673 return "~{dirflag},~{fpsr},~{flags}"; 2674 } 2675 void getTargetDefines(const LangOptions &Opts, 2676 MacroBuilder &Builder) const override; 2677 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2678 bool Enabled); 2679 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2680 bool Enabled); 2681 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2682 bool Enabled); 2683 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2684 StringRef Name, bool Enabled) const override { 2685 setFeatureEnabledImpl(Features, Name, Enabled); 2686 } 2687 // This exists purely to cut down on the number of virtual calls in 2688 // initFeatureMap which calls this repeatedly. 2689 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2690 StringRef Name, bool Enabled); 2691 bool 2692 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2693 StringRef CPU, 2694 const std::vector<std::string> &FeaturesVec) const override; 2695 bool hasFeature(StringRef Feature) const override; 2696 bool handleTargetFeatures(std::vector<std::string> &Features, 2697 DiagnosticsEngine &Diags) override; 2698 StringRef getABI() const override { 2699 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2700 return "avx512"; 2701 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2702 return "avx"; 2703 if (getTriple().getArch() == llvm::Triple::x86 && 2704 MMX3DNowLevel == NoMMX3DNow) 2705 return "no-mmx"; 2706 return ""; 2707 } 2708 bool setCPU(const std::string &Name) override { 2709 CPU = getCPUKind(Name); 2710 2711 // Perform any per-CPU checks necessary to determine if this CPU is 2712 // acceptable. 2713 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2714 // invalid without explaining *why*. 2715 switch (CPU) { 2716 case CK_Generic: 2717 // No processor selected! 2718 return false; 2719 2720 case CK_i386: 2721 case CK_i486: 2722 case CK_WinChipC6: 2723 case CK_WinChip2: 2724 case CK_C3: 2725 case CK_i586: 2726 case CK_Pentium: 2727 case CK_PentiumMMX: 2728 case CK_i686: 2729 case CK_PentiumPro: 2730 case CK_Pentium2: 2731 case CK_Pentium3: 2732 case CK_Pentium3M: 2733 case CK_PentiumM: 2734 case CK_Yonah: 2735 case CK_C3_2: 2736 case CK_Pentium4: 2737 case CK_Pentium4M: 2738 case CK_Lakemont: 2739 case CK_Prescott: 2740 case CK_K6: 2741 case CK_K6_2: 2742 case CK_K6_3: 2743 case CK_Athlon: 2744 case CK_AthlonThunderbird: 2745 case CK_Athlon4: 2746 case CK_AthlonXP: 2747 case CK_AthlonMP: 2748 case CK_Geode: 2749 // Only accept certain architectures when compiling in 32-bit mode. 2750 if (getTriple().getArch() != llvm::Triple::x86) 2751 return false; 2752 2753 // Fallthrough 2754 case CK_Nocona: 2755 case CK_Core2: 2756 case CK_Penryn: 2757 case CK_Bonnell: 2758 case CK_Silvermont: 2759 case CK_Nehalem: 2760 case CK_Westmere: 2761 case CK_SandyBridge: 2762 case CK_IvyBridge: 2763 case CK_Haswell: 2764 case CK_Broadwell: 2765 case CK_SkylakeClient: 2766 case CK_SkylakeServer: 2767 case CK_Cannonlake: 2768 case CK_KNL: 2769 case CK_Athlon64: 2770 case CK_Athlon64SSE3: 2771 case CK_AthlonFX: 2772 case CK_K8: 2773 case CK_K8SSE3: 2774 case CK_Opteron: 2775 case CK_OpteronSSE3: 2776 case CK_AMDFAM10: 2777 case CK_BTVER1: 2778 case CK_BTVER2: 2779 case CK_BDVER1: 2780 case CK_BDVER2: 2781 case CK_BDVER3: 2782 case CK_BDVER4: 2783 case CK_x86_64: 2784 return true; 2785 } 2786 llvm_unreachable("Unhandled CPU kind"); 2787 } 2788 2789 bool setFPMath(StringRef Name) override; 2790 2791 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2792 // Most of the non-ARM calling conventions are i386 conventions. 2793 switch (CC) { 2794 case CC_X86ThisCall: 2795 case CC_X86FastCall: 2796 case CC_X86StdCall: 2797 case CC_X86VectorCall: 2798 case CC_C: 2799 case CC_Swift: 2800 case CC_X86Pascal: 2801 case CC_IntelOclBicc: 2802 return CCCR_OK; 2803 default: 2804 return CCCR_Warning; 2805 } 2806 } 2807 2808 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2809 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2810 } 2811 2812 bool hasSjLjLowering() const override { 2813 return true; 2814 } 2815 2816 void setSupportedOpenCLOpts() override { 2817 getSupportedOpenCLOpts().setAll(); 2818 } 2819 }; 2820 2821 bool X86TargetInfo::setFPMath(StringRef Name) { 2822 if (Name == "387") { 2823 FPMath = FP_387; 2824 return true; 2825 } 2826 if (Name == "sse") { 2827 FPMath = FP_SSE; 2828 return true; 2829 } 2830 return false; 2831 } 2832 2833 bool X86TargetInfo::initFeatureMap( 2834 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2835 const std::vector<std::string> &FeaturesVec) const { 2836 // FIXME: This *really* should not be here. 2837 // X86_64 always has SSE2. 2838 if (getTriple().getArch() == llvm::Triple::x86_64) 2839 setFeatureEnabledImpl(Features, "sse2", true); 2840 2841 const CPUKind Kind = getCPUKind(CPU); 2842 2843 // Enable X87 for all X86 processors but Lakemont. 2844 if (Kind != CK_Lakemont) 2845 setFeatureEnabledImpl(Features, "x87", true); 2846 2847 switch (Kind) { 2848 case CK_Generic: 2849 case CK_i386: 2850 case CK_i486: 2851 case CK_i586: 2852 case CK_Pentium: 2853 case CK_i686: 2854 case CK_PentiumPro: 2855 case CK_Lakemont: 2856 break; 2857 case CK_PentiumMMX: 2858 case CK_Pentium2: 2859 case CK_K6: 2860 case CK_WinChipC6: 2861 setFeatureEnabledImpl(Features, "mmx", true); 2862 break; 2863 case CK_Pentium3: 2864 case CK_Pentium3M: 2865 case CK_C3_2: 2866 setFeatureEnabledImpl(Features, "sse", true); 2867 setFeatureEnabledImpl(Features, "fxsr", true); 2868 break; 2869 case CK_PentiumM: 2870 case CK_Pentium4: 2871 case CK_Pentium4M: 2872 case CK_x86_64: 2873 setFeatureEnabledImpl(Features, "sse2", true); 2874 setFeatureEnabledImpl(Features, "fxsr", true); 2875 break; 2876 case CK_Yonah: 2877 case CK_Prescott: 2878 case CK_Nocona: 2879 setFeatureEnabledImpl(Features, "sse3", true); 2880 setFeatureEnabledImpl(Features, "fxsr", true); 2881 setFeatureEnabledImpl(Features, "cx16", true); 2882 break; 2883 case CK_Core2: 2884 case CK_Bonnell: 2885 setFeatureEnabledImpl(Features, "ssse3", true); 2886 setFeatureEnabledImpl(Features, "fxsr", true); 2887 setFeatureEnabledImpl(Features, "cx16", true); 2888 break; 2889 case CK_Penryn: 2890 setFeatureEnabledImpl(Features, "sse4.1", true); 2891 setFeatureEnabledImpl(Features, "fxsr", true); 2892 setFeatureEnabledImpl(Features, "cx16", true); 2893 break; 2894 case CK_Cannonlake: 2895 setFeatureEnabledImpl(Features, "avx512ifma", true); 2896 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2897 setFeatureEnabledImpl(Features, "sha", true); 2898 setFeatureEnabledImpl(Features, "umip", true); 2899 // FALLTHROUGH 2900 case CK_SkylakeServer: 2901 setFeatureEnabledImpl(Features, "avx512f", true); 2902 setFeatureEnabledImpl(Features, "avx512cd", true); 2903 setFeatureEnabledImpl(Features, "avx512dq", true); 2904 setFeatureEnabledImpl(Features, "avx512bw", true); 2905 setFeatureEnabledImpl(Features, "avx512vl", true); 2906 setFeatureEnabledImpl(Features, "pku", true); 2907 setFeatureEnabledImpl(Features, "pcommit", true); 2908 setFeatureEnabledImpl(Features, "clwb", true); 2909 // FALLTHROUGH 2910 case CK_SkylakeClient: 2911 setFeatureEnabledImpl(Features, "xsavec", true); 2912 setFeatureEnabledImpl(Features, "xsaves", true); 2913 setFeatureEnabledImpl(Features, "mpx", true); 2914 setFeatureEnabledImpl(Features, "sgx", true); 2915 setFeatureEnabledImpl(Features, "clflushopt", true); 2916 // FALLTHROUGH 2917 case CK_Broadwell: 2918 setFeatureEnabledImpl(Features, "rdseed", true); 2919 setFeatureEnabledImpl(Features, "adx", true); 2920 // FALLTHROUGH 2921 case CK_Haswell: 2922 setFeatureEnabledImpl(Features, "avx2", true); 2923 setFeatureEnabledImpl(Features, "lzcnt", true); 2924 setFeatureEnabledImpl(Features, "bmi", true); 2925 setFeatureEnabledImpl(Features, "bmi2", true); 2926 setFeatureEnabledImpl(Features, "rtm", true); 2927 setFeatureEnabledImpl(Features, "fma", true); 2928 setFeatureEnabledImpl(Features, "movbe", true); 2929 // FALLTHROUGH 2930 case CK_IvyBridge: 2931 setFeatureEnabledImpl(Features, "rdrnd", true); 2932 setFeatureEnabledImpl(Features, "f16c", true); 2933 setFeatureEnabledImpl(Features, "fsgsbase", true); 2934 // FALLTHROUGH 2935 case CK_SandyBridge: 2936 setFeatureEnabledImpl(Features, "avx", true); 2937 setFeatureEnabledImpl(Features, "xsave", true); 2938 setFeatureEnabledImpl(Features, "xsaveopt", true); 2939 // FALLTHROUGH 2940 case CK_Westmere: 2941 case CK_Silvermont: 2942 setFeatureEnabledImpl(Features, "aes", true); 2943 setFeatureEnabledImpl(Features, "pclmul", true); 2944 // FALLTHROUGH 2945 case CK_Nehalem: 2946 setFeatureEnabledImpl(Features, "sse4.2", true); 2947 setFeatureEnabledImpl(Features, "fxsr", true); 2948 setFeatureEnabledImpl(Features, "cx16", true); 2949 break; 2950 case CK_KNL: 2951 setFeatureEnabledImpl(Features, "avx512f", true); 2952 setFeatureEnabledImpl(Features, "avx512cd", true); 2953 setFeatureEnabledImpl(Features, "avx512er", true); 2954 setFeatureEnabledImpl(Features, "avx512pf", true); 2955 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2956 setFeatureEnabledImpl(Features, "fxsr", true); 2957 setFeatureEnabledImpl(Features, "rdseed", true); 2958 setFeatureEnabledImpl(Features, "adx", true); 2959 setFeatureEnabledImpl(Features, "lzcnt", true); 2960 setFeatureEnabledImpl(Features, "bmi", true); 2961 setFeatureEnabledImpl(Features, "bmi2", true); 2962 setFeatureEnabledImpl(Features, "rtm", true); 2963 setFeatureEnabledImpl(Features, "fma", true); 2964 setFeatureEnabledImpl(Features, "rdrnd", true); 2965 setFeatureEnabledImpl(Features, "f16c", true); 2966 setFeatureEnabledImpl(Features, "fsgsbase", true); 2967 setFeatureEnabledImpl(Features, "aes", true); 2968 setFeatureEnabledImpl(Features, "pclmul", true); 2969 setFeatureEnabledImpl(Features, "cx16", true); 2970 setFeatureEnabledImpl(Features, "xsaveopt", true); 2971 setFeatureEnabledImpl(Features, "xsave", true); 2972 setFeatureEnabledImpl(Features, "movbe", true); 2973 break; 2974 case CK_K6_2: 2975 case CK_K6_3: 2976 case CK_WinChip2: 2977 case CK_C3: 2978 setFeatureEnabledImpl(Features, "3dnow", true); 2979 break; 2980 case CK_Athlon: 2981 case CK_AthlonThunderbird: 2982 case CK_Geode: 2983 setFeatureEnabledImpl(Features, "3dnowa", true); 2984 break; 2985 case CK_Athlon4: 2986 case CK_AthlonXP: 2987 case CK_AthlonMP: 2988 setFeatureEnabledImpl(Features, "sse", true); 2989 setFeatureEnabledImpl(Features, "3dnowa", true); 2990 setFeatureEnabledImpl(Features, "fxsr", true); 2991 break; 2992 case CK_K8: 2993 case CK_Opteron: 2994 case CK_Athlon64: 2995 case CK_AthlonFX: 2996 setFeatureEnabledImpl(Features, "sse2", true); 2997 setFeatureEnabledImpl(Features, "3dnowa", true); 2998 setFeatureEnabledImpl(Features, "fxsr", true); 2999 break; 3000 case CK_AMDFAM10: 3001 setFeatureEnabledImpl(Features, "sse4a", true); 3002 setFeatureEnabledImpl(Features, "lzcnt", true); 3003 setFeatureEnabledImpl(Features, "popcnt", true); 3004 // FALLTHROUGH 3005 case CK_K8SSE3: 3006 case CK_OpteronSSE3: 3007 case CK_Athlon64SSE3: 3008 setFeatureEnabledImpl(Features, "sse3", true); 3009 setFeatureEnabledImpl(Features, "3dnowa", true); 3010 setFeatureEnabledImpl(Features, "fxsr", true); 3011 break; 3012 case CK_BTVER2: 3013 setFeatureEnabledImpl(Features, "avx", true); 3014 setFeatureEnabledImpl(Features, "aes", true); 3015 setFeatureEnabledImpl(Features, "pclmul", true); 3016 setFeatureEnabledImpl(Features, "bmi", true); 3017 setFeatureEnabledImpl(Features, "f16c", true); 3018 setFeatureEnabledImpl(Features, "xsaveopt", true); 3019 // FALLTHROUGH 3020 case CK_BTVER1: 3021 setFeatureEnabledImpl(Features, "ssse3", true); 3022 setFeatureEnabledImpl(Features, "sse4a", true); 3023 setFeatureEnabledImpl(Features, "lzcnt", true); 3024 setFeatureEnabledImpl(Features, "popcnt", true); 3025 setFeatureEnabledImpl(Features, "prfchw", true); 3026 setFeatureEnabledImpl(Features, "cx16", true); 3027 setFeatureEnabledImpl(Features, "fxsr", true); 3028 break; 3029 case CK_BDVER4: 3030 setFeatureEnabledImpl(Features, "avx2", true); 3031 setFeatureEnabledImpl(Features, "bmi2", true); 3032 setFeatureEnabledImpl(Features, "mwaitx", true); 3033 // FALLTHROUGH 3034 case CK_BDVER3: 3035 setFeatureEnabledImpl(Features, "fsgsbase", true); 3036 setFeatureEnabledImpl(Features, "xsaveopt", true); 3037 // FALLTHROUGH 3038 case CK_BDVER2: 3039 setFeatureEnabledImpl(Features, "bmi", true); 3040 setFeatureEnabledImpl(Features, "fma", true); 3041 setFeatureEnabledImpl(Features, "f16c", true); 3042 setFeatureEnabledImpl(Features, "tbm", true); 3043 // FALLTHROUGH 3044 case CK_BDVER1: 3045 // xop implies avx, sse4a and fma4. 3046 setFeatureEnabledImpl(Features, "xop", true); 3047 setFeatureEnabledImpl(Features, "lzcnt", true); 3048 setFeatureEnabledImpl(Features, "aes", true); 3049 setFeatureEnabledImpl(Features, "pclmul", true); 3050 setFeatureEnabledImpl(Features, "prfchw", true); 3051 setFeatureEnabledImpl(Features, "cx16", true); 3052 setFeatureEnabledImpl(Features, "fxsr", true); 3053 setFeatureEnabledImpl(Features, "xsave", true); 3054 break; 3055 } 3056 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3057 return false; 3058 3059 // Can't do this earlier because we need to be able to explicitly enable 3060 // or disable these features and the things that they depend upon. 3061 3062 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3063 auto I = Features.find("sse4.2"); 3064 if (I != Features.end() && I->getValue() && 3065 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3066 FeaturesVec.end()) 3067 Features["popcnt"] = true; 3068 3069 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3070 I = Features.find("3dnow"); 3071 if (I != Features.end() && I->getValue() && 3072 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3073 FeaturesVec.end()) 3074 Features["prfchw"] = true; 3075 3076 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3077 // then enable MMX. 3078 I = Features.find("sse"); 3079 if (I != Features.end() && I->getValue() && 3080 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3081 FeaturesVec.end()) 3082 Features["mmx"] = true; 3083 3084 return true; 3085 } 3086 3087 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3088 X86SSEEnum Level, bool Enabled) { 3089 if (Enabled) { 3090 switch (Level) { 3091 case AVX512F: 3092 Features["avx512f"] = true; 3093 case AVX2: 3094 Features["avx2"] = true; 3095 case AVX: 3096 Features["avx"] = true; 3097 Features["xsave"] = true; 3098 case SSE42: 3099 Features["sse4.2"] = true; 3100 case SSE41: 3101 Features["sse4.1"] = true; 3102 case SSSE3: 3103 Features["ssse3"] = true; 3104 case SSE3: 3105 Features["sse3"] = true; 3106 case SSE2: 3107 Features["sse2"] = true; 3108 case SSE1: 3109 Features["sse"] = true; 3110 case NoSSE: 3111 break; 3112 } 3113 return; 3114 } 3115 3116 switch (Level) { 3117 case NoSSE: 3118 case SSE1: 3119 Features["sse"] = false; 3120 case SSE2: 3121 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3122 Features["sha"] = false; 3123 case SSE3: 3124 Features["sse3"] = false; 3125 setXOPLevel(Features, NoXOP, false); 3126 case SSSE3: 3127 Features["ssse3"] = false; 3128 case SSE41: 3129 Features["sse4.1"] = false; 3130 case SSE42: 3131 Features["sse4.2"] = false; 3132 case AVX: 3133 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3134 Features["xsaveopt"] = false; 3135 setXOPLevel(Features, FMA4, false); 3136 case AVX2: 3137 Features["avx2"] = false; 3138 case AVX512F: 3139 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3140 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3141 Features["avx512vl"] = Features["avx512vbmi"] = 3142 Features["avx512ifma"] = false; 3143 } 3144 } 3145 3146 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3147 MMX3DNowEnum Level, bool Enabled) { 3148 if (Enabled) { 3149 switch (Level) { 3150 case AMD3DNowAthlon: 3151 Features["3dnowa"] = true; 3152 case AMD3DNow: 3153 Features["3dnow"] = true; 3154 case MMX: 3155 Features["mmx"] = true; 3156 case NoMMX3DNow: 3157 break; 3158 } 3159 return; 3160 } 3161 3162 switch (Level) { 3163 case NoMMX3DNow: 3164 case MMX: 3165 Features["mmx"] = false; 3166 case AMD3DNow: 3167 Features["3dnow"] = false; 3168 case AMD3DNowAthlon: 3169 Features["3dnowa"] = false; 3170 } 3171 } 3172 3173 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3174 bool Enabled) { 3175 if (Enabled) { 3176 switch (Level) { 3177 case XOP: 3178 Features["xop"] = true; 3179 case FMA4: 3180 Features["fma4"] = true; 3181 setSSELevel(Features, AVX, true); 3182 case SSE4A: 3183 Features["sse4a"] = true; 3184 setSSELevel(Features, SSE3, true); 3185 case NoXOP: 3186 break; 3187 } 3188 return; 3189 } 3190 3191 switch (Level) { 3192 case NoXOP: 3193 case SSE4A: 3194 Features["sse4a"] = false; 3195 case FMA4: 3196 Features["fma4"] = false; 3197 case XOP: 3198 Features["xop"] = false; 3199 } 3200 } 3201 3202 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3203 StringRef Name, bool Enabled) { 3204 // This is a bit of a hack to deal with the sse4 target feature when used 3205 // as part of the target attribute. We handle sse4 correctly everywhere 3206 // else. See below for more information on how we handle the sse4 options. 3207 if (Name != "sse4") 3208 Features[Name] = Enabled; 3209 3210 if (Name == "mmx") { 3211 setMMXLevel(Features, MMX, Enabled); 3212 } else if (Name == "sse") { 3213 setSSELevel(Features, SSE1, Enabled); 3214 } else if (Name == "sse2") { 3215 setSSELevel(Features, SSE2, Enabled); 3216 } else if (Name == "sse3") { 3217 setSSELevel(Features, SSE3, Enabled); 3218 } else if (Name == "ssse3") { 3219 setSSELevel(Features, SSSE3, Enabled); 3220 } else if (Name == "sse4.2") { 3221 setSSELevel(Features, SSE42, Enabled); 3222 } else if (Name == "sse4.1") { 3223 setSSELevel(Features, SSE41, Enabled); 3224 } else if (Name == "3dnow") { 3225 setMMXLevel(Features, AMD3DNow, Enabled); 3226 } else if (Name == "3dnowa") { 3227 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3228 } else if (Name == "aes") { 3229 if (Enabled) 3230 setSSELevel(Features, SSE2, Enabled); 3231 } else if (Name == "pclmul") { 3232 if (Enabled) 3233 setSSELevel(Features, SSE2, Enabled); 3234 } else if (Name == "avx") { 3235 setSSELevel(Features, AVX, Enabled); 3236 } else if (Name == "avx2") { 3237 setSSELevel(Features, AVX2, Enabled); 3238 } else if (Name == "avx512f") { 3239 setSSELevel(Features, AVX512F, Enabled); 3240 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3241 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3242 Name == "avx512vbmi" || Name == "avx512ifma") { 3243 if (Enabled) 3244 setSSELevel(Features, AVX512F, Enabled); 3245 } else if (Name == "fma") { 3246 if (Enabled) 3247 setSSELevel(Features, AVX, Enabled); 3248 } else if (Name == "fma4") { 3249 setXOPLevel(Features, FMA4, Enabled); 3250 } else if (Name == "xop") { 3251 setXOPLevel(Features, XOP, Enabled); 3252 } else if (Name == "sse4a") { 3253 setXOPLevel(Features, SSE4A, Enabled); 3254 } else if (Name == "f16c") { 3255 if (Enabled) 3256 setSSELevel(Features, AVX, Enabled); 3257 } else if (Name == "sha") { 3258 if (Enabled) 3259 setSSELevel(Features, SSE2, Enabled); 3260 } else if (Name == "sse4") { 3261 // We can get here via the __target__ attribute since that's not controlled 3262 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3263 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3264 // disabled. 3265 if (Enabled) 3266 setSSELevel(Features, SSE42, Enabled); 3267 else 3268 setSSELevel(Features, SSE41, Enabled); 3269 } else if (Name == "xsave") { 3270 if (!Enabled) 3271 Features["xsaveopt"] = false; 3272 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3273 if (Enabled) 3274 Features["xsave"] = true; 3275 } 3276 } 3277 3278 /// handleTargetFeatures - Perform initialization based on the user 3279 /// configured set of features. 3280 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3281 DiagnosticsEngine &Diags) { 3282 for (const auto &Feature : Features) { 3283 if (Feature[0] != '+') 3284 continue; 3285 3286 if (Feature == "+aes") { 3287 HasAES = true; 3288 } else if (Feature == "+pclmul") { 3289 HasPCLMUL = true; 3290 } else if (Feature == "+lzcnt") { 3291 HasLZCNT = true; 3292 } else if (Feature == "+rdrnd") { 3293 HasRDRND = true; 3294 } else if (Feature == "+fsgsbase") { 3295 HasFSGSBASE = true; 3296 } else if (Feature == "+bmi") { 3297 HasBMI = true; 3298 } else if (Feature == "+bmi2") { 3299 HasBMI2 = true; 3300 } else if (Feature == "+popcnt") { 3301 HasPOPCNT = true; 3302 } else if (Feature == "+rtm") { 3303 HasRTM = true; 3304 } else if (Feature == "+prfchw") { 3305 HasPRFCHW = true; 3306 } else if (Feature == "+rdseed") { 3307 HasRDSEED = true; 3308 } else if (Feature == "+adx") { 3309 HasADX = true; 3310 } else if (Feature == "+tbm") { 3311 HasTBM = true; 3312 } else if (Feature == "+fma") { 3313 HasFMA = true; 3314 } else if (Feature == "+f16c") { 3315 HasF16C = true; 3316 } else if (Feature == "+avx512cd") { 3317 HasAVX512CD = true; 3318 } else if (Feature == "+avx512er") { 3319 HasAVX512ER = true; 3320 } else if (Feature == "+avx512pf") { 3321 HasAVX512PF = true; 3322 } else if (Feature == "+avx512dq") { 3323 HasAVX512DQ = true; 3324 } else if (Feature == "+avx512bw") { 3325 HasAVX512BW = true; 3326 } else if (Feature == "+avx512vl") { 3327 HasAVX512VL = true; 3328 } else if (Feature == "+avx512vbmi") { 3329 HasAVX512VBMI = true; 3330 } else if (Feature == "+avx512ifma") { 3331 HasAVX512IFMA = true; 3332 } else if (Feature == "+sha") { 3333 HasSHA = true; 3334 } else if (Feature == "+mpx") { 3335 HasMPX = true; 3336 } else if (Feature == "+movbe") { 3337 HasMOVBE = true; 3338 } else if (Feature == "+sgx") { 3339 HasSGX = true; 3340 } else if (Feature == "+cx16") { 3341 HasCX16 = true; 3342 } else if (Feature == "+fxsr") { 3343 HasFXSR = true; 3344 } else if (Feature == "+xsave") { 3345 HasXSAVE = true; 3346 } else if (Feature == "+xsaveopt") { 3347 HasXSAVEOPT = true; 3348 } else if (Feature == "+xsavec") { 3349 HasXSAVEC = true; 3350 } else if (Feature == "+xsaves") { 3351 HasXSAVES = true; 3352 } else if (Feature == "+mwaitx") { 3353 HasMWAITX = true; 3354 } else if (Feature == "+pku") { 3355 HasPKU = true; 3356 } else if (Feature == "+clflushopt") { 3357 HasCLFLUSHOPT = true; 3358 } else if (Feature == "+pcommit") { 3359 HasPCOMMIT = true; 3360 } else if (Feature == "+clwb") { 3361 HasCLWB = true; 3362 } else if (Feature == "+umip") { 3363 HasUMIP = true; 3364 } else if (Feature == "+prefetchwt1") { 3365 HasPREFETCHWT1 = true; 3366 } 3367 3368 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3369 .Case("+avx512f", AVX512F) 3370 .Case("+avx2", AVX2) 3371 .Case("+avx", AVX) 3372 .Case("+sse4.2", SSE42) 3373 .Case("+sse4.1", SSE41) 3374 .Case("+ssse3", SSSE3) 3375 .Case("+sse3", SSE3) 3376 .Case("+sse2", SSE2) 3377 .Case("+sse", SSE1) 3378 .Default(NoSSE); 3379 SSELevel = std::max(SSELevel, Level); 3380 3381 MMX3DNowEnum ThreeDNowLevel = 3382 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3383 .Case("+3dnowa", AMD3DNowAthlon) 3384 .Case("+3dnow", AMD3DNow) 3385 .Case("+mmx", MMX) 3386 .Default(NoMMX3DNow); 3387 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3388 3389 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3390 .Case("+xop", XOP) 3391 .Case("+fma4", FMA4) 3392 .Case("+sse4a", SSE4A) 3393 .Default(NoXOP); 3394 XOPLevel = std::max(XOPLevel, XLevel); 3395 } 3396 3397 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3398 // matches the selected sse level. 3399 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3400 (FPMath == FP_387 && SSELevel >= SSE1)) { 3401 Diags.Report(diag::err_target_unsupported_fpmath) << 3402 (FPMath == FP_SSE ? "sse" : "387"); 3403 return false; 3404 } 3405 3406 SimdDefaultAlign = 3407 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3408 return true; 3409 } 3410 3411 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3412 /// definitions for this particular subtarget. 3413 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3414 MacroBuilder &Builder) const { 3415 // Target identification. 3416 if (getTriple().getArch() == llvm::Triple::x86_64) { 3417 Builder.defineMacro("__amd64__"); 3418 Builder.defineMacro("__amd64"); 3419 Builder.defineMacro("__x86_64"); 3420 Builder.defineMacro("__x86_64__"); 3421 if (getTriple().getArchName() == "x86_64h") { 3422 Builder.defineMacro("__x86_64h"); 3423 Builder.defineMacro("__x86_64h__"); 3424 } 3425 } else { 3426 DefineStd(Builder, "i386", Opts); 3427 } 3428 3429 // Subtarget options. 3430 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3431 // truly should be based on -mtune options. 3432 switch (CPU) { 3433 case CK_Generic: 3434 break; 3435 case CK_i386: 3436 // The rest are coming from the i386 define above. 3437 Builder.defineMacro("__tune_i386__"); 3438 break; 3439 case CK_i486: 3440 case CK_WinChipC6: 3441 case CK_WinChip2: 3442 case CK_C3: 3443 defineCPUMacros(Builder, "i486"); 3444 break; 3445 case CK_PentiumMMX: 3446 Builder.defineMacro("__pentium_mmx__"); 3447 Builder.defineMacro("__tune_pentium_mmx__"); 3448 // Fallthrough 3449 case CK_i586: 3450 case CK_Pentium: 3451 defineCPUMacros(Builder, "i586"); 3452 defineCPUMacros(Builder, "pentium"); 3453 break; 3454 case CK_Pentium3: 3455 case CK_Pentium3M: 3456 case CK_PentiumM: 3457 Builder.defineMacro("__tune_pentium3__"); 3458 // Fallthrough 3459 case CK_Pentium2: 3460 case CK_C3_2: 3461 Builder.defineMacro("__tune_pentium2__"); 3462 // Fallthrough 3463 case CK_PentiumPro: 3464 Builder.defineMacro("__tune_i686__"); 3465 Builder.defineMacro("__tune_pentiumpro__"); 3466 // Fallthrough 3467 case CK_i686: 3468 Builder.defineMacro("__i686"); 3469 Builder.defineMacro("__i686__"); 3470 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3471 Builder.defineMacro("__pentiumpro"); 3472 Builder.defineMacro("__pentiumpro__"); 3473 break; 3474 case CK_Pentium4: 3475 case CK_Pentium4M: 3476 defineCPUMacros(Builder, "pentium4"); 3477 break; 3478 case CK_Yonah: 3479 case CK_Prescott: 3480 case CK_Nocona: 3481 defineCPUMacros(Builder, "nocona"); 3482 break; 3483 case CK_Core2: 3484 case CK_Penryn: 3485 defineCPUMacros(Builder, "core2"); 3486 break; 3487 case CK_Bonnell: 3488 defineCPUMacros(Builder, "atom"); 3489 break; 3490 case CK_Silvermont: 3491 defineCPUMacros(Builder, "slm"); 3492 break; 3493 case CK_Nehalem: 3494 case CK_Westmere: 3495 case CK_SandyBridge: 3496 case CK_IvyBridge: 3497 case CK_Haswell: 3498 case CK_Broadwell: 3499 case CK_SkylakeClient: 3500 // FIXME: Historically, we defined this legacy name, it would be nice to 3501 // remove it at some point. We've never exposed fine-grained names for 3502 // recent primary x86 CPUs, and we should keep it that way. 3503 defineCPUMacros(Builder, "corei7"); 3504 break; 3505 case CK_SkylakeServer: 3506 defineCPUMacros(Builder, "skx"); 3507 break; 3508 case CK_Cannonlake: 3509 break; 3510 case CK_KNL: 3511 defineCPUMacros(Builder, "knl"); 3512 break; 3513 case CK_Lakemont: 3514 Builder.defineMacro("__tune_lakemont__"); 3515 break; 3516 case CK_K6_2: 3517 Builder.defineMacro("__k6_2__"); 3518 Builder.defineMacro("__tune_k6_2__"); 3519 // Fallthrough 3520 case CK_K6_3: 3521 if (CPU != CK_K6_2) { // In case of fallthrough 3522 // FIXME: GCC may be enabling these in cases where some other k6 3523 // architecture is specified but -m3dnow is explicitly provided. The 3524 // exact semantics need to be determined and emulated here. 3525 Builder.defineMacro("__k6_3__"); 3526 Builder.defineMacro("__tune_k6_3__"); 3527 } 3528 // Fallthrough 3529 case CK_K6: 3530 defineCPUMacros(Builder, "k6"); 3531 break; 3532 case CK_Athlon: 3533 case CK_AthlonThunderbird: 3534 case CK_Athlon4: 3535 case CK_AthlonXP: 3536 case CK_AthlonMP: 3537 defineCPUMacros(Builder, "athlon"); 3538 if (SSELevel != NoSSE) { 3539 Builder.defineMacro("__athlon_sse__"); 3540 Builder.defineMacro("__tune_athlon_sse__"); 3541 } 3542 break; 3543 case CK_K8: 3544 case CK_K8SSE3: 3545 case CK_x86_64: 3546 case CK_Opteron: 3547 case CK_OpteronSSE3: 3548 case CK_Athlon64: 3549 case CK_Athlon64SSE3: 3550 case CK_AthlonFX: 3551 defineCPUMacros(Builder, "k8"); 3552 break; 3553 case CK_AMDFAM10: 3554 defineCPUMacros(Builder, "amdfam10"); 3555 break; 3556 case CK_BTVER1: 3557 defineCPUMacros(Builder, "btver1"); 3558 break; 3559 case CK_BTVER2: 3560 defineCPUMacros(Builder, "btver2"); 3561 break; 3562 case CK_BDVER1: 3563 defineCPUMacros(Builder, "bdver1"); 3564 break; 3565 case CK_BDVER2: 3566 defineCPUMacros(Builder, "bdver2"); 3567 break; 3568 case CK_BDVER3: 3569 defineCPUMacros(Builder, "bdver3"); 3570 break; 3571 case CK_BDVER4: 3572 defineCPUMacros(Builder, "bdver4"); 3573 break; 3574 case CK_Geode: 3575 defineCPUMacros(Builder, "geode"); 3576 break; 3577 } 3578 3579 // Target properties. 3580 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3581 3582 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3583 // functions in glibc header files that use FP Stack inline asm which the 3584 // backend can't deal with (PR879). 3585 Builder.defineMacro("__NO_MATH_INLINES"); 3586 3587 if (HasAES) 3588 Builder.defineMacro("__AES__"); 3589 3590 if (HasPCLMUL) 3591 Builder.defineMacro("__PCLMUL__"); 3592 3593 if (HasLZCNT) 3594 Builder.defineMacro("__LZCNT__"); 3595 3596 if (HasRDRND) 3597 Builder.defineMacro("__RDRND__"); 3598 3599 if (HasFSGSBASE) 3600 Builder.defineMacro("__FSGSBASE__"); 3601 3602 if (HasBMI) 3603 Builder.defineMacro("__BMI__"); 3604 3605 if (HasBMI2) 3606 Builder.defineMacro("__BMI2__"); 3607 3608 if (HasPOPCNT) 3609 Builder.defineMacro("__POPCNT__"); 3610 3611 if (HasRTM) 3612 Builder.defineMacro("__RTM__"); 3613 3614 if (HasPRFCHW) 3615 Builder.defineMacro("__PRFCHW__"); 3616 3617 if (HasRDSEED) 3618 Builder.defineMacro("__RDSEED__"); 3619 3620 if (HasADX) 3621 Builder.defineMacro("__ADX__"); 3622 3623 if (HasTBM) 3624 Builder.defineMacro("__TBM__"); 3625 3626 if (HasMWAITX) 3627 Builder.defineMacro("__MWAITX__"); 3628 3629 switch (XOPLevel) { 3630 case XOP: 3631 Builder.defineMacro("__XOP__"); 3632 case FMA4: 3633 Builder.defineMacro("__FMA4__"); 3634 case SSE4A: 3635 Builder.defineMacro("__SSE4A__"); 3636 case NoXOP: 3637 break; 3638 } 3639 3640 if (HasFMA) 3641 Builder.defineMacro("__FMA__"); 3642 3643 if (HasF16C) 3644 Builder.defineMacro("__F16C__"); 3645 3646 if (HasAVX512CD) 3647 Builder.defineMacro("__AVX512CD__"); 3648 if (HasAVX512ER) 3649 Builder.defineMacro("__AVX512ER__"); 3650 if (HasAVX512PF) 3651 Builder.defineMacro("__AVX512PF__"); 3652 if (HasAVX512DQ) 3653 Builder.defineMacro("__AVX512DQ__"); 3654 if (HasAVX512BW) 3655 Builder.defineMacro("__AVX512BW__"); 3656 if (HasAVX512VL) 3657 Builder.defineMacro("__AVX512VL__"); 3658 if (HasAVX512VBMI) 3659 Builder.defineMacro("__AVX512VBMI__"); 3660 if (HasAVX512IFMA) 3661 Builder.defineMacro("__AVX512IFMA__"); 3662 3663 if (HasSHA) 3664 Builder.defineMacro("__SHA__"); 3665 3666 if (HasFXSR) 3667 Builder.defineMacro("__FXSR__"); 3668 if (HasXSAVE) 3669 Builder.defineMacro("__XSAVE__"); 3670 if (HasXSAVEOPT) 3671 Builder.defineMacro("__XSAVEOPT__"); 3672 if (HasXSAVEC) 3673 Builder.defineMacro("__XSAVEC__"); 3674 if (HasXSAVES) 3675 Builder.defineMacro("__XSAVES__"); 3676 if (HasPKU) 3677 Builder.defineMacro("__PKU__"); 3678 if (HasCX16) 3679 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3680 3681 // Each case falls through to the previous one here. 3682 switch (SSELevel) { 3683 case AVX512F: 3684 Builder.defineMacro("__AVX512F__"); 3685 case AVX2: 3686 Builder.defineMacro("__AVX2__"); 3687 case AVX: 3688 Builder.defineMacro("__AVX__"); 3689 case SSE42: 3690 Builder.defineMacro("__SSE4_2__"); 3691 case SSE41: 3692 Builder.defineMacro("__SSE4_1__"); 3693 case SSSE3: 3694 Builder.defineMacro("__SSSE3__"); 3695 case SSE3: 3696 Builder.defineMacro("__SSE3__"); 3697 case SSE2: 3698 Builder.defineMacro("__SSE2__"); 3699 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3700 case SSE1: 3701 Builder.defineMacro("__SSE__"); 3702 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3703 case NoSSE: 3704 break; 3705 } 3706 3707 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3708 switch (SSELevel) { 3709 case AVX512F: 3710 case AVX2: 3711 case AVX: 3712 case SSE42: 3713 case SSE41: 3714 case SSSE3: 3715 case SSE3: 3716 case SSE2: 3717 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3718 break; 3719 case SSE1: 3720 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3721 break; 3722 default: 3723 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3724 } 3725 } 3726 3727 // Each case falls through to the previous one here. 3728 switch (MMX3DNowLevel) { 3729 case AMD3DNowAthlon: 3730 Builder.defineMacro("__3dNOW_A__"); 3731 case AMD3DNow: 3732 Builder.defineMacro("__3dNOW__"); 3733 case MMX: 3734 Builder.defineMacro("__MMX__"); 3735 case NoMMX3DNow: 3736 break; 3737 } 3738 3739 if (CPU >= CK_i486) { 3740 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3741 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3742 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3743 } 3744 if (CPU >= CK_i586) 3745 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3746 } 3747 3748 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3749 return llvm::StringSwitch<bool>(Feature) 3750 .Case("aes", HasAES) 3751 .Case("avx", SSELevel >= AVX) 3752 .Case("avx2", SSELevel >= AVX2) 3753 .Case("avx512f", SSELevel >= AVX512F) 3754 .Case("avx512cd", HasAVX512CD) 3755 .Case("avx512er", HasAVX512ER) 3756 .Case("avx512pf", HasAVX512PF) 3757 .Case("avx512dq", HasAVX512DQ) 3758 .Case("avx512bw", HasAVX512BW) 3759 .Case("avx512vl", HasAVX512VL) 3760 .Case("avx512vbmi", HasAVX512VBMI) 3761 .Case("avx512ifma", HasAVX512IFMA) 3762 .Case("bmi", HasBMI) 3763 .Case("bmi2", HasBMI2) 3764 .Case("clflushopt", HasCLFLUSHOPT) 3765 .Case("clwb", HasCLWB) 3766 .Case("cx16", HasCX16) 3767 .Case("f16c", HasF16C) 3768 .Case("fma", HasFMA) 3769 .Case("fma4", XOPLevel >= FMA4) 3770 .Case("fsgsbase", HasFSGSBASE) 3771 .Case("fxsr", HasFXSR) 3772 .Case("lzcnt", HasLZCNT) 3773 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3774 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3775 .Case("mmx", MMX3DNowLevel >= MMX) 3776 .Case("movbe", HasMOVBE) 3777 .Case("mpx", HasMPX) 3778 .Case("pclmul", HasPCLMUL) 3779 .Case("pcommit", HasPCOMMIT) 3780 .Case("pku", HasPKU) 3781 .Case("popcnt", HasPOPCNT) 3782 .Case("prefetchwt1", HasPREFETCHWT1) 3783 .Case("prfchw", HasPRFCHW) 3784 .Case("rdrnd", HasRDRND) 3785 .Case("rdseed", HasRDSEED) 3786 .Case("rtm", HasRTM) 3787 .Case("sgx", HasSGX) 3788 .Case("sha", HasSHA) 3789 .Case("sse", SSELevel >= SSE1) 3790 .Case("sse2", SSELevel >= SSE2) 3791 .Case("sse3", SSELevel >= SSE3) 3792 .Case("ssse3", SSELevel >= SSSE3) 3793 .Case("sse4.1", SSELevel >= SSE41) 3794 .Case("sse4.2", SSELevel >= SSE42) 3795 .Case("sse4a", XOPLevel >= SSE4A) 3796 .Case("tbm", HasTBM) 3797 .Case("umip", HasUMIP) 3798 .Case("x86", true) 3799 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3800 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3801 .Case("xop", XOPLevel >= XOP) 3802 .Case("xsave", HasXSAVE) 3803 .Case("xsavec", HasXSAVEC) 3804 .Case("xsaves", HasXSAVES) 3805 .Case("xsaveopt", HasXSAVEOPT) 3806 .Default(false); 3807 } 3808 3809 // We can't use a generic validation scheme for the features accepted here 3810 // versus subtarget features accepted in the target attribute because the 3811 // bitfield structure that's initialized in the runtime only supports the 3812 // below currently rather than the full range of subtarget features. (See 3813 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3814 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3815 return llvm::StringSwitch<bool>(FeatureStr) 3816 .Case("cmov", true) 3817 .Case("mmx", true) 3818 .Case("popcnt", true) 3819 .Case("sse", true) 3820 .Case("sse2", true) 3821 .Case("sse3", true) 3822 .Case("ssse3", true) 3823 .Case("sse4.1", true) 3824 .Case("sse4.2", true) 3825 .Case("avx", true) 3826 .Case("avx2", true) 3827 .Case("sse4a", true) 3828 .Case("fma4", true) 3829 .Case("xop", true) 3830 .Case("fma", true) 3831 .Case("avx512f", true) 3832 .Case("bmi", true) 3833 .Case("bmi2", true) 3834 .Case("aes", true) 3835 .Case("pclmul", true) 3836 .Case("avx512vl", true) 3837 .Case("avx512bw", true) 3838 .Case("avx512dq", true) 3839 .Case("avx512cd", true) 3840 .Case("avx512er", true) 3841 .Case("avx512pf", true) 3842 .Case("avx512vbmi", true) 3843 .Case("avx512ifma", true) 3844 .Default(false); 3845 } 3846 3847 bool 3848 X86TargetInfo::validateAsmConstraint(const char *&Name, 3849 TargetInfo::ConstraintInfo &Info) const { 3850 switch (*Name) { 3851 default: return false; 3852 // Constant constraints. 3853 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3854 // instructions. 3855 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3856 // x86_64 instructions. 3857 case 's': 3858 Info.setRequiresImmediate(); 3859 return true; 3860 case 'I': 3861 Info.setRequiresImmediate(0, 31); 3862 return true; 3863 case 'J': 3864 Info.setRequiresImmediate(0, 63); 3865 return true; 3866 case 'K': 3867 Info.setRequiresImmediate(-128, 127); 3868 return true; 3869 case 'L': 3870 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3871 return true; 3872 case 'M': 3873 Info.setRequiresImmediate(0, 3); 3874 return true; 3875 case 'N': 3876 Info.setRequiresImmediate(0, 255); 3877 return true; 3878 case 'O': 3879 Info.setRequiresImmediate(0, 127); 3880 return true; 3881 // Register constraints. 3882 case 'Y': // 'Y' is the first character for several 2-character constraints. 3883 // Shift the pointer to the second character of the constraint. 3884 Name++; 3885 switch (*Name) { 3886 default: 3887 return false; 3888 case '0': // First SSE register. 3889 case 't': // Any SSE register, when SSE2 is enabled. 3890 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3891 case 'm': // Any MMX register, when inter-unit moves enabled. 3892 Info.setAllowsRegister(); 3893 return true; 3894 } 3895 case 'f': // Any x87 floating point stack register. 3896 // Constraint 'f' cannot be used for output operands. 3897 if (Info.ConstraintStr[0] == '=') 3898 return false; 3899 Info.setAllowsRegister(); 3900 return true; 3901 case 'a': // eax. 3902 case 'b': // ebx. 3903 case 'c': // ecx. 3904 case 'd': // edx. 3905 case 'S': // esi. 3906 case 'D': // edi. 3907 case 'A': // edx:eax. 3908 case 't': // Top of floating point stack. 3909 case 'u': // Second from top of floating point stack. 3910 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3911 case 'y': // Any MMX register. 3912 case 'x': // Any SSE register. 3913 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3914 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3915 case 'l': // "Index" registers: any general register that can be used as an 3916 // index in a base+index memory access. 3917 Info.setAllowsRegister(); 3918 return true; 3919 // Floating point constant constraints. 3920 case 'C': // SSE floating point constant. 3921 case 'G': // x87 floating point constant. 3922 return true; 3923 } 3924 } 3925 3926 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3927 unsigned Size) const { 3928 // Strip off constraint modifiers. 3929 while (Constraint[0] == '=' || 3930 Constraint[0] == '+' || 3931 Constraint[0] == '&') 3932 Constraint = Constraint.substr(1); 3933 3934 return validateOperandSize(Constraint, Size); 3935 } 3936 3937 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3938 unsigned Size) const { 3939 return validateOperandSize(Constraint, Size); 3940 } 3941 3942 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3943 unsigned Size) const { 3944 switch (Constraint[0]) { 3945 default: break; 3946 case 'y': 3947 return Size <= 64; 3948 case 'f': 3949 case 't': 3950 case 'u': 3951 return Size <= 128; 3952 case 'x': 3953 if (SSELevel >= AVX512F) 3954 // 512-bit zmm registers can be used if target supports AVX512F. 3955 return Size <= 512U; 3956 else if (SSELevel >= AVX) 3957 // 256-bit ymm registers can be used if target supports AVX. 3958 return Size <= 256U; 3959 return Size <= 128U; 3960 case 'Y': 3961 // 'Y' is the first character for several 2-character constraints. 3962 switch (Constraint[1]) { 3963 default: break; 3964 case 'm': 3965 // 'Ym' is synonymous with 'y'. 3966 return Size <= 64; 3967 case 'i': 3968 case 't': 3969 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3970 if (SSELevel >= AVX512F) 3971 return Size <= 512U; 3972 else if (SSELevel >= AVX) 3973 return Size <= 256U; 3974 return SSELevel >= SSE2 && Size <= 128U; 3975 } 3976 3977 } 3978 3979 return true; 3980 } 3981 3982 std::string 3983 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3984 switch (*Constraint) { 3985 case 'a': return std::string("{ax}"); 3986 case 'b': return std::string("{bx}"); 3987 case 'c': return std::string("{cx}"); 3988 case 'd': return std::string("{dx}"); 3989 case 'S': return std::string("{si}"); 3990 case 'D': return std::string("{di}"); 3991 case 'p': // address 3992 return std::string("im"); 3993 case 't': // top of floating point stack. 3994 return std::string("{st}"); 3995 case 'u': // second from top of floating point stack. 3996 return std::string("{st(1)}"); // second from top of floating point stack. 3997 default: 3998 return std::string(1, *Constraint); 3999 } 4000 } 4001 4002 // X86-32 generic target 4003 class X86_32TargetInfo : public X86TargetInfo { 4004 public: 4005 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4006 : X86TargetInfo(Triple, Opts) { 4007 DoubleAlign = LongLongAlign = 32; 4008 LongDoubleWidth = 96; 4009 LongDoubleAlign = 32; 4010 SuitableAlign = 128; 4011 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4012 SizeType = UnsignedInt; 4013 PtrDiffType = SignedInt; 4014 IntPtrType = SignedInt; 4015 RegParmMax = 3; 4016 4017 // Use fpret for all types. 4018 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4019 (1 << TargetInfo::Double) | 4020 (1 << TargetInfo::LongDouble)); 4021 4022 // x86-32 has atomics up to 8 bytes 4023 // FIXME: Check that we actually have cmpxchg8b before setting 4024 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4025 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4026 } 4027 BuiltinVaListKind getBuiltinVaListKind() const override { 4028 return TargetInfo::CharPtrBuiltinVaList; 4029 } 4030 4031 int getEHDataRegisterNumber(unsigned RegNo) const override { 4032 if (RegNo == 0) return 0; 4033 if (RegNo == 1) return 2; 4034 return -1; 4035 } 4036 bool validateOperandSize(StringRef Constraint, 4037 unsigned Size) const override { 4038 switch (Constraint[0]) { 4039 default: break; 4040 case 'R': 4041 case 'q': 4042 case 'Q': 4043 case 'a': 4044 case 'b': 4045 case 'c': 4046 case 'd': 4047 case 'S': 4048 case 'D': 4049 return Size <= 32; 4050 case 'A': 4051 return Size <= 64; 4052 } 4053 4054 return X86TargetInfo::validateOperandSize(Constraint, Size); 4055 } 4056 }; 4057 4058 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4059 public: 4060 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4061 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4062 4063 unsigned getFloatEvalMethod() const override { 4064 unsigned Major, Minor, Micro; 4065 getTriple().getOSVersion(Major, Minor, Micro); 4066 // New NetBSD uses the default rounding mode. 4067 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4068 return X86_32TargetInfo::getFloatEvalMethod(); 4069 // NetBSD before 6.99.26 defaults to "double" rounding. 4070 return 1; 4071 } 4072 }; 4073 4074 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4075 public: 4076 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4077 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4078 SizeType = UnsignedLong; 4079 IntPtrType = SignedLong; 4080 PtrDiffType = SignedLong; 4081 } 4082 }; 4083 4084 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4085 public: 4086 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4087 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4088 SizeType = UnsignedLong; 4089 IntPtrType = SignedLong; 4090 PtrDiffType = SignedLong; 4091 } 4092 }; 4093 4094 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4095 public: 4096 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4097 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4098 LongDoubleWidth = 128; 4099 LongDoubleAlign = 128; 4100 SuitableAlign = 128; 4101 MaxVectorAlign = 256; 4102 // The watchOS simulator uses the builtin bool type for Objective-C. 4103 llvm::Triple T = llvm::Triple(Triple); 4104 if (T.isWatchOS()) 4105 UseSignedCharForObjCBool = false; 4106 SizeType = UnsignedLong; 4107 IntPtrType = SignedLong; 4108 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4109 HasAlignMac68kSupport = true; 4110 } 4111 4112 bool handleTargetFeatures(std::vector<std::string> &Features, 4113 DiagnosticsEngine &Diags) override { 4114 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4115 Diags)) 4116 return false; 4117 // We now know the features we have: we can decide how to align vectors. 4118 MaxVectorAlign = 4119 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4120 return true; 4121 } 4122 }; 4123 4124 // x86-32 Windows target 4125 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4126 public: 4127 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4128 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4129 WCharType = UnsignedShort; 4130 DoubleAlign = LongLongAlign = 64; 4131 bool IsWinCOFF = 4132 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4133 resetDataLayout(IsWinCOFF 4134 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4135 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4136 } 4137 void getTargetDefines(const LangOptions &Opts, 4138 MacroBuilder &Builder) const override { 4139 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4140 } 4141 }; 4142 4143 // x86-32 Windows Visual Studio target 4144 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4145 public: 4146 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4147 const TargetOptions &Opts) 4148 : WindowsX86_32TargetInfo(Triple, Opts) { 4149 LongDoubleWidth = LongDoubleAlign = 64; 4150 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4151 } 4152 void getTargetDefines(const LangOptions &Opts, 4153 MacroBuilder &Builder) const override { 4154 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4155 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4156 // The value of the following reflects processor type. 4157 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4158 // We lost the original triple, so we use the default. 4159 Builder.defineMacro("_M_IX86", "600"); 4160 } 4161 }; 4162 4163 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4164 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4165 // supports __declspec natively under -fms-extensions, but we define a no-op 4166 // __declspec macro anyway for pre-processor compatibility. 4167 if (Opts.MicrosoftExt) 4168 Builder.defineMacro("__declspec", "__declspec"); 4169 else 4170 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4171 4172 if (!Opts.MicrosoftExt) { 4173 // Provide macros for all the calling convention keywords. Provide both 4174 // single and double underscore prefixed variants. These are available on 4175 // x64 as well as x86, even though they have no effect. 4176 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4177 for (const char *CC : CCs) { 4178 std::string GCCSpelling = "__attribute__((__"; 4179 GCCSpelling += CC; 4180 GCCSpelling += "__))"; 4181 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4182 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4183 } 4184 } 4185 } 4186 4187 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4188 Builder.defineMacro("__MSVCRT__"); 4189 Builder.defineMacro("__MINGW32__"); 4190 addCygMingDefines(Opts, Builder); 4191 } 4192 4193 // x86-32 MinGW target 4194 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4195 public: 4196 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4197 : WindowsX86_32TargetInfo(Triple, Opts) {} 4198 void getTargetDefines(const LangOptions &Opts, 4199 MacroBuilder &Builder) const override { 4200 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4201 DefineStd(Builder, "WIN32", Opts); 4202 DefineStd(Builder, "WINNT", Opts); 4203 Builder.defineMacro("_X86_"); 4204 addMinGWDefines(Opts, Builder); 4205 } 4206 }; 4207 4208 // x86-32 Cygwin target 4209 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4210 public: 4211 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4212 : X86_32TargetInfo(Triple, Opts) { 4213 WCharType = UnsignedShort; 4214 DoubleAlign = LongLongAlign = 64; 4215 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4216 } 4217 void getTargetDefines(const LangOptions &Opts, 4218 MacroBuilder &Builder) const override { 4219 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4220 Builder.defineMacro("_X86_"); 4221 Builder.defineMacro("__CYGWIN__"); 4222 Builder.defineMacro("__CYGWIN32__"); 4223 addCygMingDefines(Opts, Builder); 4224 DefineStd(Builder, "unix", Opts); 4225 if (Opts.CPlusPlus) 4226 Builder.defineMacro("_GNU_SOURCE"); 4227 } 4228 }; 4229 4230 // x86-32 Haiku target 4231 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4232 public: 4233 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4234 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4235 } 4236 void getTargetDefines(const LangOptions &Opts, 4237 MacroBuilder &Builder) const override { 4238 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4239 Builder.defineMacro("__INTEL__"); 4240 } 4241 }; 4242 4243 // X86-32 MCU target 4244 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4245 public: 4246 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4247 : X86_32TargetInfo(Triple, Opts) { 4248 LongDoubleWidth = 64; 4249 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4250 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4251 WIntType = UnsignedInt; 4252 } 4253 4254 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4255 // On MCU we support only C calling convention. 4256 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4257 } 4258 4259 void getTargetDefines(const LangOptions &Opts, 4260 MacroBuilder &Builder) const override { 4261 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4262 Builder.defineMacro("__iamcu"); 4263 Builder.defineMacro("__iamcu__"); 4264 } 4265 4266 bool allowsLargerPreferedTypeAlignment() const override { 4267 return false; 4268 } 4269 }; 4270 4271 // RTEMS Target 4272 template<typename Target> 4273 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4274 protected: 4275 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4276 MacroBuilder &Builder) const override { 4277 // RTEMS defines; list based off of gcc output 4278 4279 Builder.defineMacro("__rtems__"); 4280 Builder.defineMacro("__ELF__"); 4281 } 4282 4283 public: 4284 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4285 : OSTargetInfo<Target>(Triple, Opts) { 4286 switch (Triple.getArch()) { 4287 default: 4288 case llvm::Triple::x86: 4289 // this->MCountName = ".mcount"; 4290 break; 4291 case llvm::Triple::mips: 4292 case llvm::Triple::mipsel: 4293 case llvm::Triple::ppc: 4294 case llvm::Triple::ppc64: 4295 case llvm::Triple::ppc64le: 4296 // this->MCountName = "_mcount"; 4297 break; 4298 case llvm::Triple::arm: 4299 // this->MCountName = "__mcount"; 4300 break; 4301 } 4302 } 4303 }; 4304 4305 // x86-32 RTEMS target 4306 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4307 public: 4308 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4309 : X86_32TargetInfo(Triple, Opts) { 4310 SizeType = UnsignedLong; 4311 IntPtrType = SignedLong; 4312 PtrDiffType = SignedLong; 4313 } 4314 void getTargetDefines(const LangOptions &Opts, 4315 MacroBuilder &Builder) const override { 4316 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4317 Builder.defineMacro("__INTEL__"); 4318 Builder.defineMacro("__rtems__"); 4319 } 4320 }; 4321 4322 // x86-64 generic target 4323 class X86_64TargetInfo : public X86TargetInfo { 4324 public: 4325 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4326 : X86TargetInfo(Triple, Opts) { 4327 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4328 bool IsWinCOFF = 4329 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4330 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4331 LongDoubleWidth = 128; 4332 LongDoubleAlign = 128; 4333 LargeArrayMinWidth = 128; 4334 LargeArrayAlign = 128; 4335 SuitableAlign = 128; 4336 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4337 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4338 IntPtrType = IsX32 ? SignedInt : SignedLong; 4339 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4340 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4341 RegParmMax = 6; 4342 4343 // Pointers are 32-bit in x32. 4344 resetDataLayout(IsX32 4345 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4346 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4347 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4348 4349 // Use fpret only for long double. 4350 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4351 4352 // Use fp2ret for _Complex long double. 4353 ComplexLongDoubleUsesFP2Ret = true; 4354 4355 // Make __builtin_ms_va_list available. 4356 HasBuiltinMSVaList = true; 4357 4358 // x86-64 has atomics up to 16 bytes. 4359 MaxAtomicPromoteWidth = 128; 4360 MaxAtomicInlineWidth = 128; 4361 } 4362 BuiltinVaListKind getBuiltinVaListKind() const override { 4363 return TargetInfo::X86_64ABIBuiltinVaList; 4364 } 4365 4366 int getEHDataRegisterNumber(unsigned RegNo) const override { 4367 if (RegNo == 0) return 0; 4368 if (RegNo == 1) return 1; 4369 return -1; 4370 } 4371 4372 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4373 switch (CC) { 4374 case CC_C: 4375 case CC_Swift: 4376 case CC_X86VectorCall: 4377 case CC_IntelOclBicc: 4378 case CC_X86_64Win64: 4379 case CC_PreserveMost: 4380 case CC_PreserveAll: 4381 return CCCR_OK; 4382 default: 4383 return CCCR_Warning; 4384 } 4385 } 4386 4387 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4388 return CC_C; 4389 } 4390 4391 // for x32 we need it here explicitly 4392 bool hasInt128Type() const override { return true; } 4393 unsigned getUnwindWordWidth() const override { return 64; } 4394 unsigned getRegisterWidth() const override { return 64; } 4395 4396 bool validateGlobalRegisterVariable(StringRef RegName, 4397 unsigned RegSize, 4398 bool &HasSizeMismatch) const override { 4399 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4400 // handle. 4401 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4402 // Check that the register size is 64-bit. 4403 HasSizeMismatch = RegSize != 64; 4404 return true; 4405 } 4406 4407 // Check if the register is a 32-bit register the backend can handle. 4408 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4409 HasSizeMismatch); 4410 } 4411 }; 4412 4413 // x86-64 Windows target 4414 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4415 public: 4416 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4417 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4418 WCharType = UnsignedShort; 4419 LongWidth = LongAlign = 32; 4420 DoubleAlign = LongLongAlign = 64; 4421 IntMaxType = SignedLongLong; 4422 Int64Type = SignedLongLong; 4423 SizeType = UnsignedLongLong; 4424 PtrDiffType = SignedLongLong; 4425 IntPtrType = SignedLongLong; 4426 } 4427 4428 void getTargetDefines(const LangOptions &Opts, 4429 MacroBuilder &Builder) const override { 4430 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4431 Builder.defineMacro("_WIN64"); 4432 } 4433 4434 BuiltinVaListKind getBuiltinVaListKind() const override { 4435 return TargetInfo::CharPtrBuiltinVaList; 4436 } 4437 4438 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4439 switch (CC) { 4440 case CC_X86StdCall: 4441 case CC_X86ThisCall: 4442 case CC_X86FastCall: 4443 return CCCR_Ignore; 4444 case CC_C: 4445 case CC_X86VectorCall: 4446 case CC_IntelOclBicc: 4447 case CC_X86_64SysV: 4448 return CCCR_OK; 4449 default: 4450 return CCCR_Warning; 4451 } 4452 } 4453 }; 4454 4455 // x86-64 Windows Visual Studio target 4456 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4457 public: 4458 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4459 const TargetOptions &Opts) 4460 : WindowsX86_64TargetInfo(Triple, Opts) { 4461 LongDoubleWidth = LongDoubleAlign = 64; 4462 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4463 } 4464 void getTargetDefines(const LangOptions &Opts, 4465 MacroBuilder &Builder) const override { 4466 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4467 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4468 Builder.defineMacro("_M_X64", "100"); 4469 Builder.defineMacro("_M_AMD64", "100"); 4470 } 4471 }; 4472 4473 // x86-64 MinGW target 4474 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4475 public: 4476 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4477 : WindowsX86_64TargetInfo(Triple, Opts) { 4478 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4479 // with x86 FP ops. Weird. 4480 LongDoubleWidth = LongDoubleAlign = 128; 4481 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4482 } 4483 4484 void getTargetDefines(const LangOptions &Opts, 4485 MacroBuilder &Builder) const override { 4486 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4487 DefineStd(Builder, "WIN64", Opts); 4488 Builder.defineMacro("__MINGW64__"); 4489 addMinGWDefines(Opts, Builder); 4490 4491 // GCC defines this macro when it is using __gxx_personality_seh0. 4492 if (!Opts.SjLjExceptions) 4493 Builder.defineMacro("__SEH__"); 4494 } 4495 }; 4496 4497 // x86-64 Cygwin target 4498 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4499 public: 4500 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4501 : X86_64TargetInfo(Triple, Opts) { 4502 TLSSupported = false; 4503 WCharType = UnsignedShort; 4504 } 4505 void getTargetDefines(const LangOptions &Opts, 4506 MacroBuilder &Builder) const override { 4507 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4508 Builder.defineMacro("__x86_64__"); 4509 Builder.defineMacro("__CYGWIN__"); 4510 Builder.defineMacro("__CYGWIN64__"); 4511 addCygMingDefines(Opts, Builder); 4512 DefineStd(Builder, "unix", Opts); 4513 if (Opts.CPlusPlus) 4514 Builder.defineMacro("_GNU_SOURCE"); 4515 4516 // GCC defines this macro when it is using __gxx_personality_seh0. 4517 if (!Opts.SjLjExceptions) 4518 Builder.defineMacro("__SEH__"); 4519 } 4520 }; 4521 4522 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4523 public: 4524 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4525 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4526 Int64Type = SignedLongLong; 4527 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4528 llvm::Triple T = llvm::Triple(Triple); 4529 if (T.isiOS()) 4530 UseSignedCharForObjCBool = false; 4531 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4532 } 4533 4534 bool handleTargetFeatures(std::vector<std::string> &Features, 4535 DiagnosticsEngine &Diags) override { 4536 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4537 Diags)) 4538 return false; 4539 // We now know the features we have: we can decide how to align vectors. 4540 MaxVectorAlign = 4541 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4542 return true; 4543 } 4544 }; 4545 4546 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4547 public: 4548 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4549 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4550 IntMaxType = SignedLongLong; 4551 Int64Type = SignedLongLong; 4552 } 4553 }; 4554 4555 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4556 public: 4557 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4558 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4559 IntMaxType = SignedLongLong; 4560 Int64Type = SignedLongLong; 4561 } 4562 }; 4563 4564 class ARMTargetInfo : public TargetInfo { 4565 // Possible FPU choices. 4566 enum FPUMode { 4567 VFP2FPU = (1 << 0), 4568 VFP3FPU = (1 << 1), 4569 VFP4FPU = (1 << 2), 4570 NeonFPU = (1 << 3), 4571 FPARMV8 = (1 << 4) 4572 }; 4573 4574 // Possible HWDiv features. 4575 enum HWDivMode { 4576 HWDivThumb = (1 << 0), 4577 HWDivARM = (1 << 1) 4578 }; 4579 4580 static bool FPUModeIsVFP(FPUMode Mode) { 4581 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4582 } 4583 4584 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4585 static const char * const GCCRegNames[]; 4586 4587 std::string ABI, CPU; 4588 4589 StringRef CPUProfile; 4590 StringRef CPUAttr; 4591 4592 enum { 4593 FP_Default, 4594 FP_VFP, 4595 FP_Neon 4596 } FPMath; 4597 4598 unsigned ArchISA; 4599 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4600 unsigned ArchProfile; 4601 unsigned ArchVersion; 4602 4603 unsigned FPU : 5; 4604 4605 unsigned IsAAPCS : 1; 4606 unsigned HWDiv : 2; 4607 4608 // Initialized via features. 4609 unsigned SoftFloat : 1; 4610 unsigned SoftFloatABI : 1; 4611 4612 unsigned CRC : 1; 4613 unsigned Crypto : 1; 4614 unsigned DSP : 1; 4615 unsigned Unaligned : 1; 4616 4617 enum { 4618 LDREX_B = (1 << 0), /// byte (8-bit) 4619 LDREX_H = (1 << 1), /// half (16-bit) 4620 LDREX_W = (1 << 2), /// word (32-bit) 4621 LDREX_D = (1 << 3), /// double (64-bit) 4622 }; 4623 4624 uint32_t LDREX; 4625 4626 // ACLE 6.5.1 Hardware floating point 4627 enum { 4628 HW_FP_HP = (1 << 1), /// half (16-bit) 4629 HW_FP_SP = (1 << 2), /// single (32-bit) 4630 HW_FP_DP = (1 << 3), /// double (64-bit) 4631 }; 4632 uint32_t HW_FP; 4633 4634 static const Builtin::Info BuiltinInfo[]; 4635 4636 void setABIAAPCS() { 4637 IsAAPCS = true; 4638 4639 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4640 const llvm::Triple &T = getTriple(); 4641 4642 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4643 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4644 T.getOS() == llvm::Triple::Bitrig) 4645 SizeType = UnsignedLong; 4646 else 4647 SizeType = UnsignedInt; 4648 4649 switch (T.getOS()) { 4650 case llvm::Triple::NetBSD: 4651 WCharType = SignedInt; 4652 break; 4653 case llvm::Triple::Win32: 4654 WCharType = UnsignedShort; 4655 break; 4656 case llvm::Triple::Linux: 4657 default: 4658 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4659 WCharType = UnsignedInt; 4660 break; 4661 } 4662 4663 UseBitFieldTypeAlignment = true; 4664 4665 ZeroLengthBitfieldBoundary = 0; 4666 4667 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4668 // so set preferred for small types to 32. 4669 if (T.isOSBinFormatMachO()) { 4670 resetDataLayout(BigEndian 4671 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4672 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4673 } else if (T.isOSWindows()) { 4674 assert(!BigEndian && "Windows on ARM does not support big endian"); 4675 resetDataLayout("e" 4676 "-m:w" 4677 "-p:32:32" 4678 "-i64:64" 4679 "-v128:64:128" 4680 "-a:0:32" 4681 "-n32" 4682 "-S64"); 4683 } else if (T.isOSNaCl()) { 4684 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4685 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4686 } else { 4687 resetDataLayout(BigEndian 4688 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4689 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4690 } 4691 4692 // FIXME: Enumerated types are variable width in straight AAPCS. 4693 } 4694 4695 void setABIAPCS(bool IsAAPCS16) { 4696 const llvm::Triple &T = getTriple(); 4697 4698 IsAAPCS = false; 4699 4700 if (IsAAPCS16) 4701 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4702 else 4703 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4704 4705 // size_t is unsigned int on FreeBSD. 4706 if (T.getOS() == llvm::Triple::FreeBSD) 4707 SizeType = UnsignedInt; 4708 else 4709 SizeType = UnsignedLong; 4710 4711 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4712 WCharType = SignedInt; 4713 4714 // Do not respect the alignment of bit-field types when laying out 4715 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4716 UseBitFieldTypeAlignment = false; 4717 4718 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4719 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4720 /// gcc. 4721 ZeroLengthBitfieldBoundary = 32; 4722 4723 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4724 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4725 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4726 } else if (T.isOSBinFormatMachO()) 4727 resetDataLayout( 4728 BigEndian 4729 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4730 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4731 else 4732 resetDataLayout( 4733 BigEndian 4734 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4735 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4736 4737 // FIXME: Override "preferred align" for double and long long. 4738 } 4739 4740 void setArchInfo() { 4741 StringRef ArchName = getTriple().getArchName(); 4742 4743 ArchISA = llvm::ARM::parseArchISA(ArchName); 4744 CPU = llvm::ARM::getDefaultCPU(ArchName); 4745 unsigned AK = llvm::ARM::parseArch(ArchName); 4746 if (AK != llvm::ARM::AK_INVALID) 4747 ArchKind = AK; 4748 setArchInfo(ArchKind); 4749 } 4750 4751 void setArchInfo(unsigned Kind) { 4752 StringRef SubArch; 4753 4754 // cache TargetParser info 4755 ArchKind = Kind; 4756 SubArch = llvm::ARM::getSubArch(ArchKind); 4757 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4758 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4759 4760 // cache CPU related strings 4761 CPUAttr = getCPUAttr(); 4762 CPUProfile = getCPUProfile(); 4763 } 4764 4765 void setAtomic() { 4766 // when triple does not specify a sub arch, 4767 // then we are not using inline atomics 4768 bool ShouldUseInlineAtomic = 4769 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4770 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4771 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4772 if (ArchProfile == llvm::ARM::PK_M) { 4773 MaxAtomicPromoteWidth = 32; 4774 if (ShouldUseInlineAtomic) 4775 MaxAtomicInlineWidth = 32; 4776 } 4777 else { 4778 MaxAtomicPromoteWidth = 64; 4779 if (ShouldUseInlineAtomic) 4780 MaxAtomicInlineWidth = 64; 4781 } 4782 } 4783 4784 bool isThumb() const { 4785 return (ArchISA == llvm::ARM::IK_THUMB); 4786 } 4787 4788 bool supportsThumb() const { 4789 return CPUAttr.count('T') || ArchVersion >= 6; 4790 } 4791 4792 bool supportsThumb2() const { 4793 return CPUAttr.equals("6T2") || 4794 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4795 } 4796 4797 StringRef getCPUAttr() const { 4798 // For most sub-arches, the build attribute CPU name is enough. 4799 // For Cortex variants, it's slightly different. 4800 switch(ArchKind) { 4801 default: 4802 return llvm::ARM::getCPUAttr(ArchKind); 4803 case llvm::ARM::AK_ARMV6M: 4804 return "6M"; 4805 case llvm::ARM::AK_ARMV7S: 4806 return "7S"; 4807 case llvm::ARM::AK_ARMV7A: 4808 return "7A"; 4809 case llvm::ARM::AK_ARMV7R: 4810 return "7R"; 4811 case llvm::ARM::AK_ARMV7M: 4812 return "7M"; 4813 case llvm::ARM::AK_ARMV7EM: 4814 return "7EM"; 4815 case llvm::ARM::AK_ARMV8A: 4816 return "8A"; 4817 case llvm::ARM::AK_ARMV8_1A: 4818 return "8_1A"; 4819 case llvm::ARM::AK_ARMV8_2A: 4820 return "8_2A"; 4821 case llvm::ARM::AK_ARMV8MBaseline: 4822 return "8M_BASE"; 4823 case llvm::ARM::AK_ARMV8MMainline: 4824 return "8M_MAIN"; 4825 } 4826 } 4827 4828 StringRef getCPUProfile() const { 4829 switch(ArchProfile) { 4830 case llvm::ARM::PK_A: 4831 return "A"; 4832 case llvm::ARM::PK_R: 4833 return "R"; 4834 case llvm::ARM::PK_M: 4835 return "M"; 4836 default: 4837 return ""; 4838 } 4839 } 4840 4841 public: 4842 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 4843 bool IsBigEndian) 4844 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4845 HW_FP(0) { 4846 BigEndian = IsBigEndian; 4847 4848 switch (getTriple().getOS()) { 4849 case llvm::Triple::NetBSD: 4850 PtrDiffType = SignedLong; 4851 break; 4852 default: 4853 PtrDiffType = SignedInt; 4854 break; 4855 } 4856 4857 // Cache arch related info. 4858 setArchInfo(); 4859 4860 // {} in inline assembly are neon specifiers, not assembly variant 4861 // specifiers. 4862 NoAsmVariants = true; 4863 4864 // FIXME: This duplicates code from the driver that sets the -target-abi 4865 // option - this code is used if -target-abi isn't passed and should 4866 // be unified in some way. 4867 if (Triple.isOSBinFormatMachO()) { 4868 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4869 // the frontend matches that. 4870 if (Triple.getEnvironment() == llvm::Triple::EABI || 4871 Triple.getOS() == llvm::Triple::UnknownOS || 4872 StringRef(CPU).startswith("cortex-m")) { 4873 setABI("aapcs"); 4874 } else if (Triple.isWatchABI()) { 4875 setABI("aapcs16"); 4876 } else { 4877 setABI("apcs-gnu"); 4878 } 4879 } else if (Triple.isOSWindows()) { 4880 // FIXME: this is invalid for WindowsCE 4881 setABI("aapcs"); 4882 } else { 4883 // Select the default based on the platform. 4884 switch (Triple.getEnvironment()) { 4885 case llvm::Triple::Android: 4886 case llvm::Triple::GNUEABI: 4887 case llvm::Triple::GNUEABIHF: 4888 case llvm::Triple::MuslEABI: 4889 case llvm::Triple::MuslEABIHF: 4890 setABI("aapcs-linux"); 4891 break; 4892 case llvm::Triple::EABIHF: 4893 case llvm::Triple::EABI: 4894 setABI("aapcs"); 4895 break; 4896 case llvm::Triple::GNU: 4897 setABI("apcs-gnu"); 4898 break; 4899 default: 4900 if (Triple.getOS() == llvm::Triple::NetBSD) 4901 setABI("apcs-gnu"); 4902 else 4903 setABI("aapcs"); 4904 break; 4905 } 4906 } 4907 4908 // ARM targets default to using the ARM C++ ABI. 4909 TheCXXABI.set(TargetCXXABI::GenericARM); 4910 4911 // ARM has atomics up to 8 bytes 4912 setAtomic(); 4913 4914 // Do force alignment of members that follow zero length bitfields. If 4915 // the alignment of the zero-length bitfield is greater than the member 4916 // that follows it, `bar', `bar' will be aligned as the type of the 4917 // zero length bitfield. 4918 UseZeroLengthBitfieldAlignment = true; 4919 4920 if (Triple.getOS() == llvm::Triple::Linux || 4921 Triple.getOS() == llvm::Triple::UnknownOS) 4922 this->MCountName = 4923 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 4924 } 4925 4926 StringRef getABI() const override { return ABI; } 4927 4928 bool setABI(const std::string &Name) override { 4929 ABI = Name; 4930 4931 // The defaults (above) are for AAPCS, check if we need to change them. 4932 // 4933 // FIXME: We need support for -meabi... we could just mangle it into the 4934 // name. 4935 if (Name == "apcs-gnu" || Name == "aapcs16") { 4936 setABIAPCS(Name == "aapcs16"); 4937 return true; 4938 } 4939 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4940 setABIAAPCS(); 4941 return true; 4942 } 4943 return false; 4944 } 4945 4946 // FIXME: This should be based on Arch attributes, not CPU names. 4947 bool 4948 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4949 StringRef CPU, 4950 const std::vector<std::string> &FeaturesVec) const override { 4951 4952 std::vector<const char*> TargetFeatures; 4953 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4954 4955 // get default FPU features 4956 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4957 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4958 4959 // get default Extension features 4960 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4961 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4962 4963 for (const char *Feature : TargetFeatures) 4964 if (Feature[0] == '+') 4965 Features[Feature+1] = true; 4966 4967 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4968 } 4969 4970 bool handleTargetFeatures(std::vector<std::string> &Features, 4971 DiagnosticsEngine &Diags) override { 4972 FPU = 0; 4973 CRC = 0; 4974 Crypto = 0; 4975 DSP = 0; 4976 Unaligned = 1; 4977 SoftFloat = SoftFloatABI = false; 4978 HWDiv = 0; 4979 4980 // This does not diagnose illegal cases like having both 4981 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4982 uint32_t HW_FP_remove = 0; 4983 for (const auto &Feature : Features) { 4984 if (Feature == "+soft-float") { 4985 SoftFloat = true; 4986 } else if (Feature == "+soft-float-abi") { 4987 SoftFloatABI = true; 4988 } else if (Feature == "+vfp2") { 4989 FPU |= VFP2FPU; 4990 HW_FP |= HW_FP_SP | HW_FP_DP; 4991 } else if (Feature == "+vfp3") { 4992 FPU |= VFP3FPU; 4993 HW_FP |= HW_FP_SP | HW_FP_DP; 4994 } else if (Feature == "+vfp4") { 4995 FPU |= VFP4FPU; 4996 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4997 } else if (Feature == "+fp-armv8") { 4998 FPU |= FPARMV8; 4999 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5000 } else if (Feature == "+neon") { 5001 FPU |= NeonFPU; 5002 HW_FP |= HW_FP_SP | HW_FP_DP; 5003 } else if (Feature == "+hwdiv") { 5004 HWDiv |= HWDivThumb; 5005 } else if (Feature == "+hwdiv-arm") { 5006 HWDiv |= HWDivARM; 5007 } else if (Feature == "+crc") { 5008 CRC = 1; 5009 } else if (Feature == "+crypto") { 5010 Crypto = 1; 5011 } else if (Feature == "+dsp") { 5012 DSP = 1; 5013 } else if (Feature == "+fp-only-sp") { 5014 HW_FP_remove |= HW_FP_DP; 5015 } else if (Feature == "+strict-align") { 5016 Unaligned = 0; 5017 } else if (Feature == "+fp16") { 5018 HW_FP |= HW_FP_HP; 5019 } 5020 } 5021 HW_FP &= ~HW_FP_remove; 5022 5023 switch (ArchVersion) { 5024 case 6: 5025 if (ArchProfile == llvm::ARM::PK_M) 5026 LDREX = 0; 5027 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5028 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5029 else 5030 LDREX = LDREX_W; 5031 break; 5032 case 7: 5033 if (ArchProfile == llvm::ARM::PK_M) 5034 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5035 else 5036 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5037 break; 5038 case 8: 5039 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5040 } 5041 5042 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5043 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5044 return false; 5045 } 5046 5047 if (FPMath == FP_Neon) 5048 Features.push_back("+neonfp"); 5049 else if (FPMath == FP_VFP) 5050 Features.push_back("-neonfp"); 5051 5052 // Remove front-end specific options which the backend handles differently. 5053 auto Feature = 5054 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5055 if (Feature != Features.end()) 5056 Features.erase(Feature); 5057 5058 return true; 5059 } 5060 5061 bool hasFeature(StringRef Feature) const override { 5062 return llvm::StringSwitch<bool>(Feature) 5063 .Case("arm", true) 5064 .Case("aarch32", true) 5065 .Case("softfloat", SoftFloat) 5066 .Case("thumb", isThumb()) 5067 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5068 .Case("hwdiv", HWDiv & HWDivThumb) 5069 .Case("hwdiv-arm", HWDiv & HWDivARM) 5070 .Default(false); 5071 } 5072 5073 bool setCPU(const std::string &Name) override { 5074 if (Name != "generic") 5075 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5076 5077 if (ArchKind == llvm::ARM::AK_INVALID) 5078 return false; 5079 setAtomic(); 5080 CPU = Name; 5081 return true; 5082 } 5083 5084 bool setFPMath(StringRef Name) override; 5085 5086 void getTargetDefines(const LangOptions &Opts, 5087 MacroBuilder &Builder) const override { 5088 // Target identification. 5089 Builder.defineMacro("__arm"); 5090 Builder.defineMacro("__arm__"); 5091 // For bare-metal none-eabi. 5092 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5093 getTriple().getEnvironment() == llvm::Triple::EABI) 5094 Builder.defineMacro("__ELF__"); 5095 5096 // Target properties. 5097 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5098 5099 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5100 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5101 if (getTriple().isWatchABI()) 5102 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5103 5104 if (!CPUAttr.empty()) 5105 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5106 5107 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5108 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5109 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5110 5111 if (ArchVersion >= 8) { 5112 // ACLE 6.5.7 Crypto Extension 5113 if (Crypto) 5114 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5115 // ACLE 6.5.8 CRC32 Extension 5116 if (CRC) 5117 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5118 // ACLE 6.5.10 Numeric Maximum and Minimum 5119 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5120 // ACLE 6.5.9 Directed Rounding 5121 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5122 } 5123 5124 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5125 // is not defined for the M-profile. 5126 // NOTE that the default profile is assumed to be 'A' 5127 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5128 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5129 5130 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5131 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5132 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5133 // v7 and v8 architectures excluding v8-M Baseline. 5134 if (supportsThumb2()) 5135 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5136 else if (supportsThumb()) 5137 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5138 5139 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5140 // instruction set such as ARM or Thumb. 5141 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5142 5143 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5144 5145 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5146 if (!CPUProfile.empty()) 5147 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5148 5149 // ACLE 6.4.3 Unaligned access supported in hardware 5150 if (Unaligned) 5151 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5152 5153 // ACLE 6.4.4 LDREX/STREX 5154 if (LDREX) 5155 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5156 5157 // ACLE 6.4.5 CLZ 5158 if (ArchVersion == 5 || 5159 (ArchVersion == 6 && CPUProfile != "M") || 5160 ArchVersion > 6) 5161 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5162 5163 // ACLE 6.5.1 Hardware Floating Point 5164 if (HW_FP) 5165 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5166 5167 // ACLE predefines. 5168 Builder.defineMacro("__ARM_ACLE", "200"); 5169 5170 // FP16 support (we currently only support IEEE format). 5171 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5172 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5173 5174 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5175 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5176 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5177 5178 // Subtarget options. 5179 5180 // FIXME: It's more complicated than this and we don't really support 5181 // interworking. 5182 // Windows on ARM does not "support" interworking 5183 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5184 Builder.defineMacro("__THUMB_INTERWORK__"); 5185 5186 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5187 // Embedded targets on Darwin follow AAPCS, but not EABI. 5188 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5189 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5190 Builder.defineMacro("__ARM_EABI__"); 5191 Builder.defineMacro("__ARM_PCS", "1"); 5192 } 5193 5194 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5195 ABI == "aapcs16") 5196 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5197 5198 if (SoftFloat) 5199 Builder.defineMacro("__SOFTFP__"); 5200 5201 if (CPU == "xscale") 5202 Builder.defineMacro("__XSCALE__"); 5203 5204 if (isThumb()) { 5205 Builder.defineMacro("__THUMBEL__"); 5206 Builder.defineMacro("__thumb__"); 5207 if (supportsThumb2()) 5208 Builder.defineMacro("__thumb2__"); 5209 } 5210 5211 // ACLE 6.4.9 32-bit SIMD instructions 5212 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5213 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5214 5215 // ACLE 6.4.10 Hardware Integer Divide 5216 if (((HWDiv & HWDivThumb) && isThumb()) || 5217 ((HWDiv & HWDivARM) && !isThumb())) { 5218 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5219 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5220 } 5221 5222 // Note, this is always on in gcc, even though it doesn't make sense. 5223 Builder.defineMacro("__APCS_32__"); 5224 5225 if (FPUModeIsVFP((FPUMode) FPU)) { 5226 Builder.defineMacro("__VFP_FP__"); 5227 if (FPU & VFP2FPU) 5228 Builder.defineMacro("__ARM_VFPV2__"); 5229 if (FPU & VFP3FPU) 5230 Builder.defineMacro("__ARM_VFPV3__"); 5231 if (FPU & VFP4FPU) 5232 Builder.defineMacro("__ARM_VFPV4__"); 5233 } 5234 5235 // This only gets set when Neon instructions are actually available, unlike 5236 // the VFP define, hence the soft float and arch check. This is subtly 5237 // different from gcc, we follow the intent which was that it should be set 5238 // when Neon instructions are actually available. 5239 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5240 Builder.defineMacro("__ARM_NEON", "1"); 5241 Builder.defineMacro("__ARM_NEON__"); 5242 // current AArch32 NEON implementations do not support double-precision 5243 // floating-point even when it is present in VFP. 5244 Builder.defineMacro("__ARM_NEON_FP", 5245 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5246 } 5247 5248 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5249 Opts.ShortWChar ? "2" : "4"); 5250 5251 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5252 Opts.ShortEnums ? "1" : "4"); 5253 5254 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5255 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5256 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5257 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5258 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5259 } 5260 5261 // ACLE 6.4.7 DSP instructions 5262 if (DSP) { 5263 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5264 } 5265 5266 // ACLE 6.4.8 Saturation instructions 5267 bool SAT = false; 5268 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5269 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5270 SAT = true; 5271 } 5272 5273 // ACLE 6.4.6 Q (saturation) flag 5274 if (DSP || SAT) 5275 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5276 5277 if (Opts.UnsafeFPMath) 5278 Builder.defineMacro("__ARM_FP_FAST", "1"); 5279 5280 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5281 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5282 } 5283 5284 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5285 return llvm::makeArrayRef(BuiltinInfo, 5286 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5287 } 5288 bool isCLZForZeroUndef() const override { return false; } 5289 BuiltinVaListKind getBuiltinVaListKind() const override { 5290 return IsAAPCS 5291 ? AAPCSABIBuiltinVaList 5292 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5293 : TargetInfo::VoidPtrBuiltinVaList); 5294 } 5295 ArrayRef<const char *> getGCCRegNames() const override; 5296 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5297 bool validateAsmConstraint(const char *&Name, 5298 TargetInfo::ConstraintInfo &Info) const override { 5299 switch (*Name) { 5300 default: break; 5301 case 'l': // r0-r7 5302 case 'h': // r8-r15 5303 case 't': // VFP Floating point register single precision 5304 case 'w': // VFP Floating point register double precision 5305 Info.setAllowsRegister(); 5306 return true; 5307 case 'I': 5308 case 'J': 5309 case 'K': 5310 case 'L': 5311 case 'M': 5312 // FIXME 5313 return true; 5314 case 'Q': // A memory address that is a single base register. 5315 Info.setAllowsMemory(); 5316 return true; 5317 case 'U': // a memory reference... 5318 switch (Name[1]) { 5319 case 'q': // ...ARMV4 ldrsb 5320 case 'v': // ...VFP load/store (reg+constant offset) 5321 case 'y': // ...iWMMXt load/store 5322 case 't': // address valid for load/store opaque types wider 5323 // than 128-bits 5324 case 'n': // valid address for Neon doubleword vector load/store 5325 case 'm': // valid address for Neon element and structure load/store 5326 case 's': // valid address for non-offset loads/stores of quad-word 5327 // values in four ARM registers 5328 Info.setAllowsMemory(); 5329 Name++; 5330 return true; 5331 } 5332 } 5333 return false; 5334 } 5335 std::string convertConstraint(const char *&Constraint) const override { 5336 std::string R; 5337 switch (*Constraint) { 5338 case 'U': // Two-character constraint; add "^" hint for later parsing. 5339 R = std::string("^") + std::string(Constraint, 2); 5340 Constraint++; 5341 break; 5342 case 'p': // 'p' should be translated to 'r' by default. 5343 R = std::string("r"); 5344 break; 5345 default: 5346 return std::string(1, *Constraint); 5347 } 5348 return R; 5349 } 5350 bool 5351 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5352 std::string &SuggestedModifier) const override { 5353 bool isOutput = (Constraint[0] == '='); 5354 bool isInOut = (Constraint[0] == '+'); 5355 5356 // Strip off constraint modifiers. 5357 while (Constraint[0] == '=' || 5358 Constraint[0] == '+' || 5359 Constraint[0] == '&') 5360 Constraint = Constraint.substr(1); 5361 5362 switch (Constraint[0]) { 5363 default: break; 5364 case 'r': { 5365 switch (Modifier) { 5366 default: 5367 return (isInOut || isOutput || Size <= 64); 5368 case 'q': 5369 // A register of size 32 cannot fit a vector type. 5370 return false; 5371 } 5372 } 5373 } 5374 5375 return true; 5376 } 5377 const char *getClobbers() const override { 5378 // FIXME: Is this really right? 5379 return ""; 5380 } 5381 5382 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5383 switch (CC) { 5384 case CC_AAPCS: 5385 case CC_AAPCS_VFP: 5386 case CC_Swift: 5387 return CCCR_OK; 5388 default: 5389 return CCCR_Warning; 5390 } 5391 } 5392 5393 int getEHDataRegisterNumber(unsigned RegNo) const override { 5394 if (RegNo == 0) return 0; 5395 if (RegNo == 1) return 1; 5396 return -1; 5397 } 5398 5399 bool hasSjLjLowering() const override { 5400 return true; 5401 } 5402 }; 5403 5404 bool ARMTargetInfo::setFPMath(StringRef Name) { 5405 if (Name == "neon") { 5406 FPMath = FP_Neon; 5407 return true; 5408 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5409 Name == "vfp4") { 5410 FPMath = FP_VFP; 5411 return true; 5412 } 5413 return false; 5414 } 5415 5416 const char * const ARMTargetInfo::GCCRegNames[] = { 5417 // Integer registers 5418 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5419 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5420 5421 // Float registers 5422 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5423 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5424 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5425 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5426 5427 // Double registers 5428 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5429 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5430 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5431 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5432 5433 // Quad registers 5434 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5435 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5436 }; 5437 5438 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5439 return llvm::makeArrayRef(GCCRegNames); 5440 } 5441 5442 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5443 { { "a1" }, "r0" }, 5444 { { "a2" }, "r1" }, 5445 { { "a3" }, "r2" }, 5446 { { "a4" }, "r3" }, 5447 { { "v1" }, "r4" }, 5448 { { "v2" }, "r5" }, 5449 { { "v3" }, "r6" }, 5450 { { "v4" }, "r7" }, 5451 { { "v5" }, "r8" }, 5452 { { "v6", "rfp" }, "r9" }, 5453 { { "sl" }, "r10" }, 5454 { { "fp" }, "r11" }, 5455 { { "ip" }, "r12" }, 5456 { { "r13" }, "sp" }, 5457 { { "r14" }, "lr" }, 5458 { { "r15" }, "pc" }, 5459 // The S, D and Q registers overlap, but aren't really aliases; we 5460 // don't want to substitute one of these for a different-sized one. 5461 }; 5462 5463 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5464 return llvm::makeArrayRef(GCCRegAliases); 5465 } 5466 5467 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5468 #define BUILTIN(ID, TYPE, ATTRS) \ 5469 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5470 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5471 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5472 #include "clang/Basic/BuiltinsNEON.def" 5473 5474 #define BUILTIN(ID, TYPE, ATTRS) \ 5475 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5476 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5477 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5478 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5479 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5480 #include "clang/Basic/BuiltinsARM.def" 5481 }; 5482 5483 class ARMleTargetInfo : public ARMTargetInfo { 5484 public: 5485 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5486 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/false) {} 5487 void getTargetDefines(const LangOptions &Opts, 5488 MacroBuilder &Builder) const override { 5489 Builder.defineMacro("__ARMEL__"); 5490 ARMTargetInfo::getTargetDefines(Opts, Builder); 5491 } 5492 }; 5493 5494 class ARMbeTargetInfo : public ARMTargetInfo { 5495 public: 5496 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5497 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/true) {} 5498 void getTargetDefines(const LangOptions &Opts, 5499 MacroBuilder &Builder) const override { 5500 Builder.defineMacro("__ARMEB__"); 5501 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5502 ARMTargetInfo::getTargetDefines(Opts, Builder); 5503 } 5504 }; 5505 5506 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5507 const llvm::Triple Triple; 5508 public: 5509 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5510 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5511 WCharType = UnsignedShort; 5512 SizeType = UnsignedInt; 5513 } 5514 void getVisualStudioDefines(const LangOptions &Opts, 5515 MacroBuilder &Builder) const { 5516 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5517 5518 // FIXME: this is invalid for WindowsCE 5519 Builder.defineMacro("_M_ARM_NT", "1"); 5520 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5521 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5522 5523 assert((Triple.getArch() == llvm::Triple::arm || 5524 Triple.getArch() == llvm::Triple::thumb) && 5525 "invalid architecture for Windows ARM target info"); 5526 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5527 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5528 5529 // TODO map the complete set of values 5530 // 31: VFPv3 40: VFPv4 5531 Builder.defineMacro("_M_ARM_FP", "31"); 5532 } 5533 BuiltinVaListKind getBuiltinVaListKind() const override { 5534 return TargetInfo::CharPtrBuiltinVaList; 5535 } 5536 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5537 switch (CC) { 5538 case CC_X86StdCall: 5539 case CC_X86ThisCall: 5540 case CC_X86FastCall: 5541 case CC_X86VectorCall: 5542 return CCCR_Ignore; 5543 case CC_C: 5544 return CCCR_OK; 5545 default: 5546 return CCCR_Warning; 5547 } 5548 } 5549 }; 5550 5551 // Windows ARM + Itanium C++ ABI Target 5552 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5553 public: 5554 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5555 const TargetOptions &Opts) 5556 : WindowsARMTargetInfo(Triple, Opts) { 5557 TheCXXABI.set(TargetCXXABI::GenericARM); 5558 } 5559 5560 void getTargetDefines(const LangOptions &Opts, 5561 MacroBuilder &Builder) const override { 5562 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5563 5564 if (Opts.MSVCCompat) 5565 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5566 } 5567 }; 5568 5569 // Windows ARM, MS (C++) ABI 5570 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5571 public: 5572 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5573 const TargetOptions &Opts) 5574 : WindowsARMTargetInfo(Triple, Opts) { 5575 TheCXXABI.set(TargetCXXABI::Microsoft); 5576 } 5577 5578 void getTargetDefines(const LangOptions &Opts, 5579 MacroBuilder &Builder) const override { 5580 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5581 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5582 } 5583 }; 5584 5585 // ARM MinGW target 5586 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5587 public: 5588 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5589 : WindowsARMTargetInfo(Triple, Opts) { 5590 TheCXXABI.set(TargetCXXABI::GenericARM); 5591 } 5592 5593 void getTargetDefines(const LangOptions &Opts, 5594 MacroBuilder &Builder) const override { 5595 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5596 DefineStd(Builder, "WIN32", Opts); 5597 DefineStd(Builder, "WINNT", Opts); 5598 Builder.defineMacro("_ARM_"); 5599 addMinGWDefines(Opts, Builder); 5600 } 5601 }; 5602 5603 // ARM Cygwin target 5604 class CygwinARMTargetInfo : public ARMleTargetInfo { 5605 public: 5606 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5607 : ARMleTargetInfo(Triple, Opts) { 5608 TLSSupported = false; 5609 WCharType = UnsignedShort; 5610 DoubleAlign = LongLongAlign = 64; 5611 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5612 } 5613 void getTargetDefines(const LangOptions &Opts, 5614 MacroBuilder &Builder) const override { 5615 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5616 Builder.defineMacro("_ARM_"); 5617 Builder.defineMacro("__CYGWIN__"); 5618 Builder.defineMacro("__CYGWIN32__"); 5619 DefineStd(Builder, "unix", Opts); 5620 if (Opts.CPlusPlus) 5621 Builder.defineMacro("_GNU_SOURCE"); 5622 } 5623 }; 5624 5625 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5626 protected: 5627 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5628 MacroBuilder &Builder) const override { 5629 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5630 } 5631 5632 public: 5633 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5634 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5635 HasAlignMac68kSupport = true; 5636 // iOS always has 64-bit atomic instructions. 5637 // FIXME: This should be based off of the target features in 5638 // ARMleTargetInfo. 5639 MaxAtomicInlineWidth = 64; 5640 5641 if (Triple.isWatchABI()) { 5642 // Darwin on iOS uses a variant of the ARM C++ ABI. 5643 TheCXXABI.set(TargetCXXABI::WatchOS); 5644 5645 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5646 // size_t is long, it's a bit weird for it to be int. 5647 PtrDiffType = SignedLong; 5648 5649 // BOOL should be a real boolean on the new ABI 5650 UseSignedCharForObjCBool = false; 5651 } else 5652 TheCXXABI.set(TargetCXXABI::iOS); 5653 } 5654 }; 5655 5656 class AArch64TargetInfo : public TargetInfo { 5657 virtual void setDataLayout() = 0; 5658 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5659 static const char *const GCCRegNames[]; 5660 5661 enum FPUModeEnum { 5662 FPUMode, 5663 NeonMode 5664 }; 5665 5666 unsigned FPU; 5667 unsigned CRC; 5668 unsigned Crypto; 5669 unsigned Unaligned; 5670 unsigned V8_1A; 5671 5672 static const Builtin::Info BuiltinInfo[]; 5673 5674 std::string ABI; 5675 5676 public: 5677 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5678 : TargetInfo(Triple), ABI("aapcs") { 5679 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5680 WCharType = SignedInt; 5681 5682 // NetBSD apparently prefers consistency across ARM targets to consistency 5683 // across 64-bit targets. 5684 Int64Type = SignedLongLong; 5685 IntMaxType = SignedLongLong; 5686 } else { 5687 WCharType = UnsignedInt; 5688 Int64Type = SignedLong; 5689 IntMaxType = SignedLong; 5690 } 5691 5692 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5693 MaxVectorAlign = 128; 5694 MaxAtomicInlineWidth = 128; 5695 MaxAtomicPromoteWidth = 128; 5696 5697 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5698 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5699 5700 // {} in inline assembly are neon specifiers, not assembly variant 5701 // specifiers. 5702 NoAsmVariants = true; 5703 5704 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5705 // contributes to the alignment of the containing aggregate in the same way 5706 // a plain (non bit-field) member of that type would, without exception for 5707 // zero-sized or anonymous bit-fields." 5708 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5709 UseZeroLengthBitfieldAlignment = true; 5710 5711 // AArch64 targets default to using the ARM C++ ABI. 5712 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5713 5714 if (Triple.getOS() == llvm::Triple::Linux || 5715 Triple.getOS() == llvm::Triple::UnknownOS) 5716 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5717 } 5718 5719 StringRef getABI() const override { return ABI; } 5720 bool setABI(const std::string &Name) override { 5721 if (Name != "aapcs" && Name != "darwinpcs") 5722 return false; 5723 5724 ABI = Name; 5725 return true; 5726 } 5727 5728 bool setCPU(const std::string &Name) override { 5729 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5730 .Case("generic", true) 5731 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5732 "cortex-a35", "exynos-m1", true) 5733 .Case("cortex-a73", true) 5734 .Case("cyclone", true) 5735 .Case("kryo", true) 5736 .Case("vulcan", true) 5737 .Default(false); 5738 return CPUKnown; 5739 } 5740 5741 void getTargetDefines(const LangOptions &Opts, 5742 MacroBuilder &Builder) const override { 5743 // Target identification. 5744 Builder.defineMacro("__aarch64__"); 5745 5746 // Target properties. 5747 Builder.defineMacro("_LP64"); 5748 Builder.defineMacro("__LP64__"); 5749 5750 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5751 Builder.defineMacro("__ARM_ACLE", "200"); 5752 Builder.defineMacro("__ARM_ARCH", "8"); 5753 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5754 5755 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5756 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5757 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5758 5759 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5760 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5761 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5762 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5763 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5764 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5765 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5766 5767 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5768 5769 // 0xe implies support for half, single and double precision operations. 5770 Builder.defineMacro("__ARM_FP", "0xE"); 5771 5772 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5773 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5774 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5775 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5776 5777 if (Opts.UnsafeFPMath) 5778 Builder.defineMacro("__ARM_FP_FAST", "1"); 5779 5780 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5781 5782 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5783 Opts.ShortEnums ? "1" : "4"); 5784 5785 if (FPU == NeonMode) { 5786 Builder.defineMacro("__ARM_NEON", "1"); 5787 // 64-bit NEON supports half, single and double precision operations. 5788 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5789 } 5790 5791 if (CRC) 5792 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5793 5794 if (Crypto) 5795 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5796 5797 if (Unaligned) 5798 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5799 5800 if (V8_1A) 5801 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5802 5803 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5804 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5805 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5806 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5807 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5808 } 5809 5810 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5811 return llvm::makeArrayRef(BuiltinInfo, 5812 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5813 } 5814 5815 bool hasFeature(StringRef Feature) const override { 5816 return Feature == "aarch64" || 5817 Feature == "arm64" || 5818 Feature == "arm" || 5819 (Feature == "neon" && FPU == NeonMode); 5820 } 5821 5822 bool handleTargetFeatures(std::vector<std::string> &Features, 5823 DiagnosticsEngine &Diags) override { 5824 FPU = FPUMode; 5825 CRC = 0; 5826 Crypto = 0; 5827 Unaligned = 1; 5828 V8_1A = 0; 5829 5830 for (const auto &Feature : Features) { 5831 if (Feature == "+neon") 5832 FPU = NeonMode; 5833 if (Feature == "+crc") 5834 CRC = 1; 5835 if (Feature == "+crypto") 5836 Crypto = 1; 5837 if (Feature == "+strict-align") 5838 Unaligned = 0; 5839 if (Feature == "+v8.1a") 5840 V8_1A = 1; 5841 } 5842 5843 setDataLayout(); 5844 5845 return true; 5846 } 5847 5848 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5849 switch (CC) { 5850 case CC_C: 5851 case CC_Swift: 5852 case CC_PreserveMost: 5853 case CC_PreserveAll: 5854 return CCCR_OK; 5855 default: 5856 return CCCR_Warning; 5857 } 5858 } 5859 5860 bool isCLZForZeroUndef() const override { return false; } 5861 5862 BuiltinVaListKind getBuiltinVaListKind() const override { 5863 return TargetInfo::AArch64ABIBuiltinVaList; 5864 } 5865 5866 ArrayRef<const char *> getGCCRegNames() const override; 5867 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5868 5869 bool validateAsmConstraint(const char *&Name, 5870 TargetInfo::ConstraintInfo &Info) const override { 5871 switch (*Name) { 5872 default: 5873 return false; 5874 case 'w': // Floating point and SIMD registers (V0-V31) 5875 Info.setAllowsRegister(); 5876 return true; 5877 case 'I': // Constant that can be used with an ADD instruction 5878 case 'J': // Constant that can be used with a SUB instruction 5879 case 'K': // Constant that can be used with a 32-bit logical instruction 5880 case 'L': // Constant that can be used with a 64-bit logical instruction 5881 case 'M': // Constant that can be used as a 32-bit MOV immediate 5882 case 'N': // Constant that can be used as a 64-bit MOV immediate 5883 case 'Y': // Floating point constant zero 5884 case 'Z': // Integer constant zero 5885 return true; 5886 case 'Q': // A memory reference with base register and no offset 5887 Info.setAllowsMemory(); 5888 return true; 5889 case 'S': // A symbolic address 5890 Info.setAllowsRegister(); 5891 return true; 5892 case 'U': 5893 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5894 // Utf: A memory address suitable for ldp/stp in TF mode. 5895 // Usa: An absolute symbolic address. 5896 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5897 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5898 case 'z': // Zero register, wzr or xzr 5899 Info.setAllowsRegister(); 5900 return true; 5901 case 'x': // Floating point and SIMD registers (V0-V15) 5902 Info.setAllowsRegister(); 5903 return true; 5904 } 5905 return false; 5906 } 5907 5908 bool 5909 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5910 std::string &SuggestedModifier) const override { 5911 // Strip off constraint modifiers. 5912 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5913 Constraint = Constraint.substr(1); 5914 5915 switch (Constraint[0]) { 5916 default: 5917 return true; 5918 case 'z': 5919 case 'r': { 5920 switch (Modifier) { 5921 case 'x': 5922 case 'w': 5923 // For now assume that the person knows what they're 5924 // doing with the modifier. 5925 return true; 5926 default: 5927 // By default an 'r' constraint will be in the 'x' 5928 // registers. 5929 if (Size == 64) 5930 return true; 5931 5932 SuggestedModifier = "w"; 5933 return false; 5934 } 5935 } 5936 } 5937 } 5938 5939 const char *getClobbers() const override { return ""; } 5940 5941 int getEHDataRegisterNumber(unsigned RegNo) const override { 5942 if (RegNo == 0) 5943 return 0; 5944 if (RegNo == 1) 5945 return 1; 5946 return -1; 5947 } 5948 }; 5949 5950 const char *const AArch64TargetInfo::GCCRegNames[] = { 5951 // 32-bit Integer registers 5952 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5953 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5954 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5955 5956 // 64-bit Integer registers 5957 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5958 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5959 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5960 5961 // 32-bit floating point regsisters 5962 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5963 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5964 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5965 5966 // 64-bit floating point regsisters 5967 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5968 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5969 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5970 5971 // Vector registers 5972 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5973 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5974 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5975 }; 5976 5977 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5978 return llvm::makeArrayRef(GCCRegNames); 5979 } 5980 5981 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5982 { { "w31" }, "wsp" }, 5983 { { "x29" }, "fp" }, 5984 { { "x30" }, "lr" }, 5985 { { "x31" }, "sp" }, 5986 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5987 // don't want to substitute one of these for a different-sized one. 5988 }; 5989 5990 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5991 return llvm::makeArrayRef(GCCRegAliases); 5992 } 5993 5994 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5995 #define BUILTIN(ID, TYPE, ATTRS) \ 5996 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5997 #include "clang/Basic/BuiltinsNEON.def" 5998 5999 #define BUILTIN(ID, TYPE, ATTRS) \ 6000 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6001 #include "clang/Basic/BuiltinsAArch64.def" 6002 }; 6003 6004 class AArch64leTargetInfo : public AArch64TargetInfo { 6005 void setDataLayout() override { 6006 if (getTriple().isOSBinFormatMachO()) 6007 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6008 else 6009 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6010 } 6011 6012 public: 6013 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6014 : AArch64TargetInfo(Triple, Opts) { 6015 BigEndian = false; 6016 } 6017 void getTargetDefines(const LangOptions &Opts, 6018 MacroBuilder &Builder) const override { 6019 Builder.defineMacro("__AARCH64EL__"); 6020 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6021 } 6022 }; 6023 6024 class AArch64beTargetInfo : public AArch64TargetInfo { 6025 void setDataLayout() override { 6026 assert(!getTriple().isOSBinFormatMachO()); 6027 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6028 } 6029 6030 public: 6031 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6032 : AArch64TargetInfo(Triple, Opts) {} 6033 void getTargetDefines(const LangOptions &Opts, 6034 MacroBuilder &Builder) const override { 6035 Builder.defineMacro("__AARCH64EB__"); 6036 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6037 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6038 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6039 } 6040 }; 6041 6042 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6043 protected: 6044 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6045 MacroBuilder &Builder) const override { 6046 Builder.defineMacro("__AARCH64_SIMD__"); 6047 Builder.defineMacro("__ARM64_ARCH_8__"); 6048 Builder.defineMacro("__ARM_NEON__"); 6049 Builder.defineMacro("__LITTLE_ENDIAN__"); 6050 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6051 Builder.defineMacro("__arm64", "1"); 6052 Builder.defineMacro("__arm64__", "1"); 6053 6054 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6055 } 6056 6057 public: 6058 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6059 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6060 Int64Type = SignedLongLong; 6061 WCharType = SignedInt; 6062 UseSignedCharForObjCBool = false; 6063 6064 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6065 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6066 6067 TheCXXABI.set(TargetCXXABI::iOS64); 6068 } 6069 6070 BuiltinVaListKind getBuiltinVaListKind() const override { 6071 return TargetInfo::CharPtrBuiltinVaList; 6072 } 6073 }; 6074 6075 // Hexagon abstract base class 6076 class HexagonTargetInfo : public TargetInfo { 6077 static const Builtin::Info BuiltinInfo[]; 6078 static const char * const GCCRegNames[]; 6079 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6080 std::string CPU; 6081 bool HasHVX, HasHVXDouble; 6082 6083 public: 6084 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6085 : TargetInfo(Triple) { 6086 BigEndian = false; 6087 // Specify the vector alignment explicitly. For v512x1, the calculated 6088 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6089 // the required minimum of 64 bytes. 6090 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6091 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6092 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6093 SizeType = UnsignedInt; 6094 PtrDiffType = SignedInt; 6095 IntPtrType = SignedInt; 6096 6097 // {} in inline assembly are packet specifiers, not assembly variant 6098 // specifiers. 6099 NoAsmVariants = true; 6100 6101 LargeArrayMinWidth = 64; 6102 LargeArrayAlign = 64; 6103 UseBitFieldTypeAlignment = true; 6104 ZeroLengthBitfieldBoundary = 32; 6105 HasHVX = HasHVXDouble = false; 6106 } 6107 6108 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6109 return llvm::makeArrayRef(BuiltinInfo, 6110 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6111 } 6112 6113 bool validateAsmConstraint(const char *&Name, 6114 TargetInfo::ConstraintInfo &Info) const override { 6115 switch (*Name) { 6116 case 'v': 6117 case 'q': 6118 if (HasHVX) { 6119 Info.setAllowsRegister(); 6120 return true; 6121 } 6122 break; 6123 case 's': 6124 // Relocatable constant. 6125 return true; 6126 } 6127 return false; 6128 } 6129 6130 void getTargetDefines(const LangOptions &Opts, 6131 MacroBuilder &Builder) const override; 6132 6133 bool isCLZForZeroUndef() const override { return false; } 6134 6135 bool hasFeature(StringRef Feature) const override { 6136 return llvm::StringSwitch<bool>(Feature) 6137 .Case("hexagon", true) 6138 .Case("hvx", HasHVX) 6139 .Case("hvx-double", HasHVXDouble) 6140 .Default(false); 6141 } 6142 6143 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6144 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6145 const override; 6146 6147 bool handleTargetFeatures(std::vector<std::string> &Features, 6148 DiagnosticsEngine &Diags) override; 6149 6150 BuiltinVaListKind getBuiltinVaListKind() const override { 6151 return TargetInfo::CharPtrBuiltinVaList; 6152 } 6153 ArrayRef<const char *> getGCCRegNames() const override; 6154 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6155 const char *getClobbers() const override { 6156 return ""; 6157 } 6158 6159 static const char *getHexagonCPUSuffix(StringRef Name) { 6160 return llvm::StringSwitch<const char*>(Name) 6161 .Case("hexagonv4", "4") 6162 .Case("hexagonv5", "5") 6163 .Case("hexagonv55", "55") 6164 .Case("hexagonv60", "60") 6165 .Default(nullptr); 6166 } 6167 6168 bool setCPU(const std::string &Name) override { 6169 if (!getHexagonCPUSuffix(Name)) 6170 return false; 6171 CPU = Name; 6172 return true; 6173 } 6174 6175 int getEHDataRegisterNumber(unsigned RegNo) const override { 6176 return RegNo < 2 ? RegNo : -1; 6177 } 6178 }; 6179 6180 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6181 MacroBuilder &Builder) const { 6182 Builder.defineMacro("__qdsp6__", "1"); 6183 Builder.defineMacro("__hexagon__", "1"); 6184 6185 if (CPU == "hexagonv4") { 6186 Builder.defineMacro("__HEXAGON_V4__"); 6187 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6188 if (Opts.HexagonQdsp6Compat) { 6189 Builder.defineMacro("__QDSP6_V4__"); 6190 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6191 } 6192 } else if (CPU == "hexagonv5") { 6193 Builder.defineMacro("__HEXAGON_V5__"); 6194 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6195 if(Opts.HexagonQdsp6Compat) { 6196 Builder.defineMacro("__QDSP6_V5__"); 6197 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6198 } 6199 } else if (CPU == "hexagonv55") { 6200 Builder.defineMacro("__HEXAGON_V55__"); 6201 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6202 Builder.defineMacro("__QDSP6_V55__"); 6203 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6204 } else if (CPU == "hexagonv60") { 6205 Builder.defineMacro("__HEXAGON_V60__"); 6206 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6207 Builder.defineMacro("__QDSP6_V60__"); 6208 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6209 } 6210 6211 if (hasFeature("hvx")) { 6212 Builder.defineMacro("__HVX__"); 6213 if (hasFeature("hvx-double")) 6214 Builder.defineMacro("__HVXDBL__"); 6215 } 6216 } 6217 6218 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6219 DiagnosticsEngine &Diags) { 6220 for (auto &F : Features) { 6221 if (F == "+hvx") 6222 HasHVX = true; 6223 else if (F == "-hvx") 6224 HasHVX = HasHVXDouble = false; 6225 else if (F == "+hvx-double") 6226 HasHVX = HasHVXDouble = true; 6227 else if (F == "-hvx-double") 6228 HasHVXDouble = false; 6229 } 6230 return true; 6231 } 6232 6233 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6234 DiagnosticsEngine &Diags, StringRef CPU, 6235 const std::vector<std::string> &FeaturesVec) const { 6236 // Default for v60: -hvx, -hvx-double. 6237 Features["hvx"] = false; 6238 Features["hvx-double"] = false; 6239 6240 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6241 } 6242 6243 6244 const char *const HexagonTargetInfo::GCCRegNames[] = { 6245 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6246 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6247 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6248 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6249 "p0", "p1", "p2", "p3", 6250 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6251 }; 6252 6253 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6254 return llvm::makeArrayRef(GCCRegNames); 6255 } 6256 6257 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6258 { { "sp" }, "r29" }, 6259 { { "fp" }, "r30" }, 6260 { { "lr" }, "r31" }, 6261 }; 6262 6263 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6264 return llvm::makeArrayRef(GCCRegAliases); 6265 } 6266 6267 6268 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6269 #define BUILTIN(ID, TYPE, ATTRS) \ 6270 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6271 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6272 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6273 #include "clang/Basic/BuiltinsHexagon.def" 6274 }; 6275 6276 class LanaiTargetInfo : public TargetInfo { 6277 // Class for Lanai (32-bit). 6278 // The CPU profiles supported by the Lanai backend 6279 enum CPUKind { 6280 CK_NONE, 6281 CK_V11, 6282 } CPU; 6283 6284 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6285 static const char *const GCCRegNames[]; 6286 6287 public: 6288 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6289 : TargetInfo(Triple) { 6290 // Description string has to be kept in sync with backend. 6291 resetDataLayout("E" // Big endian 6292 "-m:e" // ELF name manging 6293 "-p:32:32" // 32 bit pointers, 32 bit aligned 6294 "-i64:64" // 64 bit integers, 64 bit aligned 6295 "-a:0:32" // 32 bit alignment of objects of aggregate type 6296 "-n32" // 32 bit native integer width 6297 "-S64" // 64 bit natural stack alignment 6298 ); 6299 6300 // Setting RegParmMax equal to what mregparm was set to in the old 6301 // toolchain 6302 RegParmMax = 4; 6303 6304 // Set the default CPU to V11 6305 CPU = CK_V11; 6306 6307 // Temporary approach to make everything at least word-aligned and allow for 6308 // safely casting between pointers with different alignment requirements. 6309 // TODO: Remove this when there are no more cast align warnings on the 6310 // firmware. 6311 MinGlobalAlign = 32; 6312 } 6313 6314 void getTargetDefines(const LangOptions &Opts, 6315 MacroBuilder &Builder) const override { 6316 // Define __lanai__ when building for target lanai. 6317 Builder.defineMacro("__lanai__"); 6318 6319 // Set define for the CPU specified. 6320 switch (CPU) { 6321 case CK_V11: 6322 Builder.defineMacro("__LANAI_V11__"); 6323 break; 6324 case CK_NONE: 6325 llvm_unreachable("Unhandled target CPU"); 6326 } 6327 } 6328 6329 bool setCPU(const std::string &Name) override { 6330 CPU = llvm::StringSwitch<CPUKind>(Name) 6331 .Case("v11", CK_V11) 6332 .Default(CK_NONE); 6333 6334 return CPU != CK_NONE; 6335 } 6336 6337 bool hasFeature(StringRef Feature) const override { 6338 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6339 } 6340 6341 ArrayRef<const char *> getGCCRegNames() const override; 6342 6343 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6344 6345 BuiltinVaListKind getBuiltinVaListKind() const override { 6346 return TargetInfo::VoidPtrBuiltinVaList; 6347 } 6348 6349 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6350 6351 bool validateAsmConstraint(const char *&Name, 6352 TargetInfo::ConstraintInfo &info) const override { 6353 return false; 6354 } 6355 6356 const char *getClobbers() const override { return ""; } 6357 }; 6358 6359 const char *const LanaiTargetInfo::GCCRegNames[] = { 6360 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6361 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6362 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6363 6364 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6365 return llvm::makeArrayRef(GCCRegNames); 6366 } 6367 6368 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6369 {{"pc"}, "r2"}, 6370 {{"sp"}, "r4"}, 6371 {{"fp"}, "r5"}, 6372 {{"rv"}, "r8"}, 6373 {{"rr1"}, "r10"}, 6374 {{"rr2"}, "r11"}, 6375 {{"rca"}, "r15"}, 6376 }; 6377 6378 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6379 return llvm::makeArrayRef(GCCRegAliases); 6380 } 6381 6382 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6383 class SparcTargetInfo : public TargetInfo { 6384 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6385 static const char * const GCCRegNames[]; 6386 bool SoftFloat; 6387 public: 6388 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6389 : TargetInfo(Triple), SoftFloat(false) {} 6390 6391 int getEHDataRegisterNumber(unsigned RegNo) const override { 6392 if (RegNo == 0) return 24; 6393 if (RegNo == 1) return 25; 6394 return -1; 6395 } 6396 6397 bool handleTargetFeatures(std::vector<std::string> &Features, 6398 DiagnosticsEngine &Diags) override { 6399 // Check if software floating point is enabled 6400 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6401 if (Feature != Features.end()) { 6402 SoftFloat = true; 6403 } 6404 return true; 6405 } 6406 void getTargetDefines(const LangOptions &Opts, 6407 MacroBuilder &Builder) const override { 6408 DefineStd(Builder, "sparc", Opts); 6409 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6410 6411 if (SoftFloat) 6412 Builder.defineMacro("SOFT_FLOAT", "1"); 6413 } 6414 6415 bool hasFeature(StringRef Feature) const override { 6416 return llvm::StringSwitch<bool>(Feature) 6417 .Case("softfloat", SoftFloat) 6418 .Case("sparc", true) 6419 .Default(false); 6420 } 6421 6422 bool hasSjLjLowering() const override { 6423 return true; 6424 } 6425 6426 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6427 // FIXME: Implement! 6428 return None; 6429 } 6430 BuiltinVaListKind getBuiltinVaListKind() const override { 6431 return TargetInfo::VoidPtrBuiltinVaList; 6432 } 6433 ArrayRef<const char *> getGCCRegNames() const override; 6434 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6435 bool validateAsmConstraint(const char *&Name, 6436 TargetInfo::ConstraintInfo &info) const override { 6437 // FIXME: Implement! 6438 switch (*Name) { 6439 case 'I': // Signed 13-bit constant 6440 case 'J': // Zero 6441 case 'K': // 32-bit constant with the low 12 bits clear 6442 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6443 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6444 case 'N': // Same as 'K' but zext (required for SIMode) 6445 case 'O': // The constant 4096 6446 return true; 6447 } 6448 return false; 6449 } 6450 const char *getClobbers() const override { 6451 // FIXME: Implement! 6452 return ""; 6453 } 6454 6455 // No Sparc V7 for now, the backend doesn't support it anyway. 6456 enum CPUKind { 6457 CK_GENERIC, 6458 CK_V8, 6459 CK_SUPERSPARC, 6460 CK_SPARCLITE, 6461 CK_F934, 6462 CK_HYPERSPARC, 6463 CK_SPARCLITE86X, 6464 CK_SPARCLET, 6465 CK_TSC701, 6466 CK_V9, 6467 CK_ULTRASPARC, 6468 CK_ULTRASPARC3, 6469 CK_NIAGARA, 6470 CK_NIAGARA2, 6471 CK_NIAGARA3, 6472 CK_NIAGARA4, 6473 CK_MYRIAD2_1, 6474 CK_MYRIAD2_2, 6475 CK_LEON2, 6476 CK_LEON2_AT697E, 6477 CK_LEON2_AT697F, 6478 CK_LEON3, 6479 CK_LEON3_UT699, 6480 CK_LEON3_GR712RC, 6481 CK_LEON4, 6482 CK_LEON4_GR740 6483 } CPU = CK_GENERIC; 6484 6485 enum CPUGeneration { 6486 CG_V8, 6487 CG_V9, 6488 }; 6489 6490 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6491 switch (Kind) { 6492 case CK_GENERIC: 6493 case CK_V8: 6494 case CK_SUPERSPARC: 6495 case CK_SPARCLITE: 6496 case CK_F934: 6497 case CK_HYPERSPARC: 6498 case CK_SPARCLITE86X: 6499 case CK_SPARCLET: 6500 case CK_TSC701: 6501 case CK_MYRIAD2_1: 6502 case CK_MYRIAD2_2: 6503 case CK_LEON2: 6504 case CK_LEON2_AT697E: 6505 case CK_LEON2_AT697F: 6506 case CK_LEON3: 6507 case CK_LEON3_UT699: 6508 case CK_LEON3_GR712RC: 6509 case CK_LEON4: 6510 case CK_LEON4_GR740: 6511 return CG_V8; 6512 case CK_V9: 6513 case CK_ULTRASPARC: 6514 case CK_ULTRASPARC3: 6515 case CK_NIAGARA: 6516 case CK_NIAGARA2: 6517 case CK_NIAGARA3: 6518 case CK_NIAGARA4: 6519 return CG_V9; 6520 } 6521 llvm_unreachable("Unexpected CPU kind"); 6522 } 6523 6524 CPUKind getCPUKind(StringRef Name) const { 6525 return llvm::StringSwitch<CPUKind>(Name) 6526 .Case("v8", CK_V8) 6527 .Case("supersparc", CK_SUPERSPARC) 6528 .Case("sparclite", CK_SPARCLITE) 6529 .Case("f934", CK_F934) 6530 .Case("hypersparc", CK_HYPERSPARC) 6531 .Case("sparclite86x", CK_SPARCLITE86X) 6532 .Case("sparclet", CK_SPARCLET) 6533 .Case("tsc701", CK_TSC701) 6534 .Case("v9", CK_V9) 6535 .Case("ultrasparc", CK_ULTRASPARC) 6536 .Case("ultrasparc3", CK_ULTRASPARC3) 6537 .Case("niagara", CK_NIAGARA) 6538 .Case("niagara2", CK_NIAGARA2) 6539 .Case("niagara3", CK_NIAGARA3) 6540 .Case("niagara4", CK_NIAGARA4) 6541 .Case("myriad2", CK_MYRIAD2_1) 6542 .Case("myriad2.1", CK_MYRIAD2_1) 6543 .Case("myriad2.2", CK_MYRIAD2_2) 6544 .Case("leon2", CK_LEON2) 6545 .Case("at697e", CK_LEON2_AT697E) 6546 .Case("at697f", CK_LEON2_AT697F) 6547 .Case("leon3", CK_LEON3) 6548 .Case("ut699", CK_LEON3_UT699) 6549 .Case("gr712rc", CK_LEON3_GR712RC) 6550 .Case("leon4", CK_LEON4) 6551 .Case("gr740", CK_LEON4_GR740) 6552 .Default(CK_GENERIC); 6553 } 6554 6555 bool setCPU(const std::string &Name) override { 6556 CPU = getCPUKind(Name); 6557 return CPU != CK_GENERIC; 6558 } 6559 }; 6560 6561 const char * const SparcTargetInfo::GCCRegNames[] = { 6562 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6563 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6564 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6565 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6566 }; 6567 6568 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6569 return llvm::makeArrayRef(GCCRegNames); 6570 } 6571 6572 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6573 { { "g0" }, "r0" }, 6574 { { "g1" }, "r1" }, 6575 { { "g2" }, "r2" }, 6576 { { "g3" }, "r3" }, 6577 { { "g4" }, "r4" }, 6578 { { "g5" }, "r5" }, 6579 { { "g6" }, "r6" }, 6580 { { "g7" }, "r7" }, 6581 { { "o0" }, "r8" }, 6582 { { "o1" }, "r9" }, 6583 { { "o2" }, "r10" }, 6584 { { "o3" }, "r11" }, 6585 { { "o4" }, "r12" }, 6586 { { "o5" }, "r13" }, 6587 { { "o6", "sp" }, "r14" }, 6588 { { "o7" }, "r15" }, 6589 { { "l0" }, "r16" }, 6590 { { "l1" }, "r17" }, 6591 { { "l2" }, "r18" }, 6592 { { "l3" }, "r19" }, 6593 { { "l4" }, "r20" }, 6594 { { "l5" }, "r21" }, 6595 { { "l6" }, "r22" }, 6596 { { "l7" }, "r23" }, 6597 { { "i0" }, "r24" }, 6598 { { "i1" }, "r25" }, 6599 { { "i2" }, "r26" }, 6600 { { "i3" }, "r27" }, 6601 { { "i4" }, "r28" }, 6602 { { "i5" }, "r29" }, 6603 { { "i6", "fp" }, "r30" }, 6604 { { "i7" }, "r31" }, 6605 }; 6606 6607 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6608 return llvm::makeArrayRef(GCCRegAliases); 6609 } 6610 6611 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6612 class SparcV8TargetInfo : public SparcTargetInfo { 6613 public: 6614 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6615 : SparcTargetInfo(Triple, Opts) { 6616 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6617 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6618 switch (getTriple().getOS()) { 6619 default: 6620 SizeType = UnsignedInt; 6621 IntPtrType = SignedInt; 6622 PtrDiffType = SignedInt; 6623 break; 6624 case llvm::Triple::NetBSD: 6625 case llvm::Triple::OpenBSD: 6626 SizeType = UnsignedLong; 6627 IntPtrType = SignedLong; 6628 PtrDiffType = SignedLong; 6629 break; 6630 } 6631 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6632 } 6633 6634 void getTargetDefines(const LangOptions &Opts, 6635 MacroBuilder &Builder) const override { 6636 SparcTargetInfo::getTargetDefines(Opts, Builder); 6637 switch (getCPUGeneration(CPU)) { 6638 case CG_V8: 6639 Builder.defineMacro("__sparcv8"); 6640 if (getTriple().getOS() != llvm::Triple::Solaris) 6641 Builder.defineMacro("__sparcv8__"); 6642 break; 6643 case CG_V9: 6644 Builder.defineMacro("__sparcv9"); 6645 if (getTriple().getOS() != llvm::Triple::Solaris) { 6646 Builder.defineMacro("__sparcv9__"); 6647 Builder.defineMacro("__sparc_v9__"); 6648 } 6649 break; 6650 } 6651 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6652 switch (CPU) { 6653 case CK_MYRIAD2_1: 6654 Builder.defineMacro("__myriad2", "1"); 6655 Builder.defineMacro("__myriad2__", "1"); 6656 break; 6657 case CK_MYRIAD2_2: 6658 Builder.defineMacro("__myriad2", "2"); 6659 Builder.defineMacro("__myriad2__", "2"); 6660 break; 6661 default: 6662 break; 6663 } 6664 } 6665 } 6666 6667 bool hasSjLjLowering() const override { 6668 return true; 6669 } 6670 }; 6671 6672 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6673 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6674 public: 6675 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6676 : SparcV8TargetInfo(Triple, Opts) { 6677 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6678 BigEndian = false; 6679 } 6680 }; 6681 6682 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6683 class SparcV9TargetInfo : public SparcTargetInfo { 6684 public: 6685 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6686 : SparcTargetInfo(Triple, Opts) { 6687 // FIXME: Support Sparc quad-precision long double? 6688 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6689 // This is an LP64 platform. 6690 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6691 6692 // OpenBSD uses long long for int64_t and intmax_t. 6693 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6694 IntMaxType = SignedLongLong; 6695 else 6696 IntMaxType = SignedLong; 6697 Int64Type = IntMaxType; 6698 6699 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6700 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6701 LongDoubleWidth = 128; 6702 LongDoubleAlign = 128; 6703 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6704 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6705 } 6706 6707 void getTargetDefines(const LangOptions &Opts, 6708 MacroBuilder &Builder) const override { 6709 SparcTargetInfo::getTargetDefines(Opts, Builder); 6710 Builder.defineMacro("__sparcv9"); 6711 Builder.defineMacro("__arch64__"); 6712 // Solaris doesn't need these variants, but the BSDs do. 6713 if (getTriple().getOS() != llvm::Triple::Solaris) { 6714 Builder.defineMacro("__sparc64__"); 6715 Builder.defineMacro("__sparc_v9__"); 6716 Builder.defineMacro("__sparcv9__"); 6717 } 6718 } 6719 6720 bool setCPU(const std::string &Name) override { 6721 if (!SparcTargetInfo::setCPU(Name)) 6722 return false; 6723 return getCPUGeneration(CPU) == CG_V9; 6724 } 6725 }; 6726 6727 class SystemZTargetInfo : public TargetInfo { 6728 static const Builtin::Info BuiltinInfo[]; 6729 static const char *const GCCRegNames[]; 6730 std::string CPU; 6731 bool HasTransactionalExecution; 6732 bool HasVector; 6733 6734 public: 6735 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6736 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6737 HasVector(false) { 6738 IntMaxType = SignedLong; 6739 Int64Type = SignedLong; 6740 TLSSupported = true; 6741 IntWidth = IntAlign = 32; 6742 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6743 PointerWidth = PointerAlign = 64; 6744 LongDoubleWidth = 128; 6745 LongDoubleAlign = 64; 6746 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6747 DefaultAlignForAttributeAligned = 64; 6748 MinGlobalAlign = 16; 6749 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6750 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6751 } 6752 void getTargetDefines(const LangOptions &Opts, 6753 MacroBuilder &Builder) const override { 6754 Builder.defineMacro("__s390__"); 6755 Builder.defineMacro("__s390x__"); 6756 Builder.defineMacro("__zarch__"); 6757 Builder.defineMacro("__LONG_DOUBLE_128__"); 6758 6759 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6760 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6761 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6762 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6763 6764 if (HasTransactionalExecution) 6765 Builder.defineMacro("__HTM__"); 6766 if (Opts.ZVector) 6767 Builder.defineMacro("__VEC__", "10301"); 6768 } 6769 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6770 return llvm::makeArrayRef(BuiltinInfo, 6771 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6772 } 6773 6774 ArrayRef<const char *> getGCCRegNames() const override; 6775 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6776 // No aliases. 6777 return None; 6778 } 6779 bool validateAsmConstraint(const char *&Name, 6780 TargetInfo::ConstraintInfo &info) const override; 6781 const char *getClobbers() const override { 6782 // FIXME: Is this really right? 6783 return ""; 6784 } 6785 BuiltinVaListKind getBuiltinVaListKind() const override { 6786 return TargetInfo::SystemZBuiltinVaList; 6787 } 6788 bool setCPU(const std::string &Name) override { 6789 CPU = Name; 6790 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6791 .Case("z10", true) 6792 .Case("z196", true) 6793 .Case("zEC12", true) 6794 .Case("z13", true) 6795 .Default(false); 6796 6797 return CPUKnown; 6798 } 6799 bool 6800 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6801 StringRef CPU, 6802 const std::vector<std::string> &FeaturesVec) const override { 6803 if (CPU == "zEC12") 6804 Features["transactional-execution"] = true; 6805 if (CPU == "z13") { 6806 Features["transactional-execution"] = true; 6807 Features["vector"] = true; 6808 } 6809 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6810 } 6811 6812 bool handleTargetFeatures(std::vector<std::string> &Features, 6813 DiagnosticsEngine &Diags) override { 6814 HasTransactionalExecution = false; 6815 for (const auto &Feature : Features) { 6816 if (Feature == "+transactional-execution") 6817 HasTransactionalExecution = true; 6818 else if (Feature == "+vector") 6819 HasVector = true; 6820 } 6821 // If we use the vector ABI, vector types are 64-bit aligned. 6822 if (HasVector) { 6823 MaxVectorAlign = 64; 6824 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6825 "-v128:64-a:8:16-n32:64"); 6826 } 6827 return true; 6828 } 6829 6830 bool hasFeature(StringRef Feature) const override { 6831 return llvm::StringSwitch<bool>(Feature) 6832 .Case("systemz", true) 6833 .Case("htm", HasTransactionalExecution) 6834 .Case("vx", HasVector) 6835 .Default(false); 6836 } 6837 6838 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6839 switch (CC) { 6840 case CC_C: 6841 case CC_Swift: 6842 return CCCR_OK; 6843 default: 6844 return CCCR_Warning; 6845 } 6846 } 6847 6848 StringRef getABI() const override { 6849 if (HasVector) 6850 return "vector"; 6851 return ""; 6852 } 6853 6854 bool useFloat128ManglingForLongDouble() const override { 6855 return true; 6856 } 6857 }; 6858 6859 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6860 #define BUILTIN(ID, TYPE, ATTRS) \ 6861 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6862 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6863 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6864 #include "clang/Basic/BuiltinsSystemZ.def" 6865 }; 6866 6867 const char *const SystemZTargetInfo::GCCRegNames[] = { 6868 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6869 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6870 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6871 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6872 }; 6873 6874 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6875 return llvm::makeArrayRef(GCCRegNames); 6876 } 6877 6878 bool SystemZTargetInfo:: 6879 validateAsmConstraint(const char *&Name, 6880 TargetInfo::ConstraintInfo &Info) const { 6881 switch (*Name) { 6882 default: 6883 return false; 6884 6885 case 'a': // Address register 6886 case 'd': // Data register (equivalent to 'r') 6887 case 'f': // Floating-point register 6888 Info.setAllowsRegister(); 6889 return true; 6890 6891 case 'I': // Unsigned 8-bit constant 6892 case 'J': // Unsigned 12-bit constant 6893 case 'K': // Signed 16-bit constant 6894 case 'L': // Signed 20-bit displacement (on all targets we support) 6895 case 'M': // 0x7fffffff 6896 return true; 6897 6898 case 'Q': // Memory with base and unsigned 12-bit displacement 6899 case 'R': // Likewise, plus an index 6900 case 'S': // Memory with base and signed 20-bit displacement 6901 case 'T': // Likewise, plus an index 6902 Info.setAllowsMemory(); 6903 return true; 6904 } 6905 } 6906 6907 class MSP430TargetInfo : public TargetInfo { 6908 static const char *const GCCRegNames[]; 6909 6910 public: 6911 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6912 : TargetInfo(Triple) { 6913 BigEndian = false; 6914 TLSSupported = false; 6915 IntWidth = 16; 6916 IntAlign = 16; 6917 LongWidth = 32; 6918 LongLongWidth = 64; 6919 LongAlign = LongLongAlign = 16; 6920 PointerWidth = 16; 6921 PointerAlign = 16; 6922 SuitableAlign = 16; 6923 SizeType = UnsignedInt; 6924 IntMaxType = SignedLongLong; 6925 IntPtrType = SignedInt; 6926 PtrDiffType = SignedInt; 6927 SigAtomicType = SignedLong; 6928 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6929 } 6930 void getTargetDefines(const LangOptions &Opts, 6931 MacroBuilder &Builder) const override { 6932 Builder.defineMacro("MSP430"); 6933 Builder.defineMacro("__MSP430__"); 6934 // FIXME: defines for different 'flavours' of MCU 6935 } 6936 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6937 // FIXME: Implement. 6938 return None; 6939 } 6940 bool hasFeature(StringRef Feature) const override { 6941 return Feature == "msp430"; 6942 } 6943 ArrayRef<const char *> getGCCRegNames() const override; 6944 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6945 // No aliases. 6946 return None; 6947 } 6948 bool validateAsmConstraint(const char *&Name, 6949 TargetInfo::ConstraintInfo &info) const override { 6950 // FIXME: implement 6951 switch (*Name) { 6952 case 'K': // the constant 1 6953 case 'L': // constant -1^20 .. 1^19 6954 case 'M': // constant 1-4: 6955 return true; 6956 } 6957 // No target constraints for now. 6958 return false; 6959 } 6960 const char *getClobbers() const override { 6961 // FIXME: Is this really right? 6962 return ""; 6963 } 6964 BuiltinVaListKind getBuiltinVaListKind() const override { 6965 // FIXME: implement 6966 return TargetInfo::CharPtrBuiltinVaList; 6967 } 6968 }; 6969 6970 const char *const MSP430TargetInfo::GCCRegNames[] = { 6971 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6972 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6973 6974 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6975 return llvm::makeArrayRef(GCCRegNames); 6976 } 6977 6978 // LLVM and Clang cannot be used directly to output native binaries for 6979 // target, but is used to compile C code to llvm bitcode with correct 6980 // type and alignment information. 6981 // 6982 // TCE uses the llvm bitcode as input and uses it for generating customized 6983 // target processor and program binary. TCE co-design environment is 6984 // publicly available in http://tce.cs.tut.fi 6985 6986 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6987 3, // opencl_global 6988 4, // opencl_local 6989 5, // opencl_constant 6990 // FIXME: generic has to be added to the target 6991 0, // opencl_generic 6992 0, // cuda_device 6993 0, // cuda_constant 6994 0 // cuda_shared 6995 }; 6996 6997 class TCETargetInfo : public TargetInfo { 6998 public: 6999 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7000 : TargetInfo(Triple) { 7001 TLSSupported = false; 7002 IntWidth = 32; 7003 LongWidth = LongLongWidth = 32; 7004 PointerWidth = 32; 7005 IntAlign = 32; 7006 LongAlign = LongLongAlign = 32; 7007 PointerAlign = 32; 7008 SuitableAlign = 32; 7009 SizeType = UnsignedInt; 7010 IntMaxType = SignedLong; 7011 IntPtrType = SignedInt; 7012 PtrDiffType = SignedInt; 7013 FloatWidth = 32; 7014 FloatAlign = 32; 7015 DoubleWidth = 32; 7016 DoubleAlign = 32; 7017 LongDoubleWidth = 32; 7018 LongDoubleAlign = 32; 7019 FloatFormat = &llvm::APFloat::IEEEsingle; 7020 DoubleFormat = &llvm::APFloat::IEEEsingle; 7021 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 7022 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 7023 "-f64:32-v64:32-v128:32-a:0:32-n32"); 7024 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7025 UseAddrSpaceMapMangling = true; 7026 } 7027 7028 void getTargetDefines(const LangOptions &Opts, 7029 MacroBuilder &Builder) const override { 7030 DefineStd(Builder, "tce", Opts); 7031 Builder.defineMacro("__TCE__"); 7032 Builder.defineMacro("__TCE_V1__"); 7033 } 7034 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7035 7036 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7037 const char *getClobbers() const override { return ""; } 7038 BuiltinVaListKind getBuiltinVaListKind() const override { 7039 return TargetInfo::VoidPtrBuiltinVaList; 7040 } 7041 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7042 bool validateAsmConstraint(const char *&Name, 7043 TargetInfo::ConstraintInfo &info) const override { 7044 return true; 7045 } 7046 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7047 return None; 7048 } 7049 }; 7050 7051 class BPFTargetInfo : public TargetInfo { 7052 public: 7053 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7054 : TargetInfo(Triple) { 7055 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7056 SizeType = UnsignedLong; 7057 PtrDiffType = SignedLong; 7058 IntPtrType = SignedLong; 7059 IntMaxType = SignedLong; 7060 Int64Type = SignedLong; 7061 RegParmMax = 5; 7062 if (Triple.getArch() == llvm::Triple::bpfeb) { 7063 BigEndian = true; 7064 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7065 } else { 7066 BigEndian = false; 7067 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7068 } 7069 MaxAtomicPromoteWidth = 64; 7070 MaxAtomicInlineWidth = 64; 7071 TLSSupported = false; 7072 } 7073 void getTargetDefines(const LangOptions &Opts, 7074 MacroBuilder &Builder) const override { 7075 DefineStd(Builder, "bpf", Opts); 7076 Builder.defineMacro("__BPF__"); 7077 } 7078 bool hasFeature(StringRef Feature) const override { 7079 return Feature == "bpf"; 7080 } 7081 7082 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7083 const char *getClobbers() const override { 7084 return ""; 7085 } 7086 BuiltinVaListKind getBuiltinVaListKind() const override { 7087 return TargetInfo::VoidPtrBuiltinVaList; 7088 } 7089 ArrayRef<const char *> getGCCRegNames() const override { 7090 return None; 7091 } 7092 bool validateAsmConstraint(const char *&Name, 7093 TargetInfo::ConstraintInfo &info) const override { 7094 return true; 7095 } 7096 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7097 return None; 7098 } 7099 }; 7100 7101 class MipsTargetInfo : public TargetInfo { 7102 void setDataLayout() { 7103 StringRef Layout; 7104 7105 if (ABI == "o32") 7106 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7107 else if (ABI == "n32") 7108 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7109 else if (ABI == "n64") 7110 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7111 else 7112 llvm_unreachable("Invalid ABI"); 7113 7114 if (BigEndian) 7115 resetDataLayout(("E-" + Layout).str()); 7116 else 7117 resetDataLayout(("e-" + Layout).str()); 7118 } 7119 7120 7121 static const Builtin::Info BuiltinInfo[]; 7122 std::string CPU; 7123 bool IsMips16; 7124 bool IsMicromips; 7125 bool IsNan2008; 7126 bool IsSingleFloat; 7127 enum MipsFloatABI { 7128 HardFloat, SoftFloat 7129 } FloatABI; 7130 enum DspRevEnum { 7131 NoDSP, DSP1, DSP2 7132 } DspRev; 7133 bool HasMSA; 7134 7135 protected: 7136 bool HasFP64; 7137 std::string ABI; 7138 7139 public: 7140 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7141 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7142 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7143 DspRev(NoDSP), HasMSA(false), HasFP64(false) { 7144 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7145 BigEndian = getTriple().getArch() == llvm::Triple::mips || 7146 getTriple().getArch() == llvm::Triple::mips64; 7147 7148 setABI((getTriple().getArch() == llvm::Triple::mips || 7149 getTriple().getArch() == llvm::Triple::mipsel) 7150 ? "o32" 7151 : "n64"); 7152 7153 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7154 } 7155 7156 bool isNaN2008Default() const { 7157 return CPU == "mips32r6" || CPU == "mips64r6"; 7158 } 7159 7160 bool isFP64Default() const { 7161 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7162 } 7163 7164 bool isNan2008() const override { 7165 return IsNan2008; 7166 } 7167 7168 bool processorSupportsGPR64() const { 7169 return llvm::StringSwitch<bool>(CPU) 7170 .Case("mips3", true) 7171 .Case("mips4", true) 7172 .Case("mips5", true) 7173 .Case("mips64", true) 7174 .Case("mips64r2", true) 7175 .Case("mips64r3", true) 7176 .Case("mips64r5", true) 7177 .Case("mips64r6", true) 7178 .Case("octeon", true) 7179 .Default(false); 7180 return false; 7181 } 7182 7183 StringRef getABI() const override { return ABI; } 7184 bool setABI(const std::string &Name) override { 7185 if (Name == "o32") { 7186 setO32ABITypes(); 7187 ABI = Name; 7188 return true; 7189 } 7190 7191 if (Name == "n32") { 7192 setN32ABITypes(); 7193 ABI = Name; 7194 return true; 7195 } 7196 if (Name == "n64") { 7197 setN64ABITypes(); 7198 ABI = Name; 7199 return true; 7200 } 7201 return false; 7202 } 7203 7204 void setO32ABITypes() { 7205 Int64Type = SignedLongLong; 7206 IntMaxType = Int64Type; 7207 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7208 LongDoubleWidth = LongDoubleAlign = 64; 7209 LongWidth = LongAlign = 32; 7210 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7211 PointerWidth = PointerAlign = 32; 7212 PtrDiffType = SignedInt; 7213 SizeType = UnsignedInt; 7214 SuitableAlign = 64; 7215 } 7216 7217 void setN32N64ABITypes() { 7218 LongDoubleWidth = LongDoubleAlign = 128; 7219 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7220 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7221 LongDoubleWidth = LongDoubleAlign = 64; 7222 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7223 } 7224 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7225 SuitableAlign = 128; 7226 } 7227 7228 void setN64ABITypes() { 7229 setN32N64ABITypes(); 7230 Int64Type = SignedLong; 7231 IntMaxType = Int64Type; 7232 LongWidth = LongAlign = 64; 7233 PointerWidth = PointerAlign = 64; 7234 PtrDiffType = SignedLong; 7235 SizeType = UnsignedLong; 7236 } 7237 7238 void setN32ABITypes() { 7239 setN32N64ABITypes(); 7240 Int64Type = SignedLongLong; 7241 IntMaxType = Int64Type; 7242 LongWidth = LongAlign = 32; 7243 PointerWidth = PointerAlign = 32; 7244 PtrDiffType = SignedInt; 7245 SizeType = UnsignedInt; 7246 } 7247 7248 bool setCPU(const std::string &Name) override { 7249 CPU = Name; 7250 return llvm::StringSwitch<bool>(Name) 7251 .Case("mips1", true) 7252 .Case("mips2", true) 7253 .Case("mips3", true) 7254 .Case("mips4", true) 7255 .Case("mips5", true) 7256 .Case("mips32", true) 7257 .Case("mips32r2", true) 7258 .Case("mips32r3", true) 7259 .Case("mips32r5", true) 7260 .Case("mips32r6", true) 7261 .Case("mips64", true) 7262 .Case("mips64r2", true) 7263 .Case("mips64r3", true) 7264 .Case("mips64r5", true) 7265 .Case("mips64r6", true) 7266 .Case("octeon", true) 7267 .Case("p5600", true) 7268 .Default(false); 7269 } 7270 const std::string& getCPU() const { return CPU; } 7271 bool 7272 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7273 StringRef CPU, 7274 const std::vector<std::string> &FeaturesVec) const override { 7275 if (CPU.empty()) 7276 CPU = getCPU(); 7277 if (CPU == "octeon") 7278 Features["mips64r2"] = Features["cnmips"] = true; 7279 else 7280 Features[CPU] = true; 7281 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7282 } 7283 7284 void getTargetDefines(const LangOptions &Opts, 7285 MacroBuilder &Builder) const override { 7286 if (BigEndian) { 7287 DefineStd(Builder, "MIPSEB", Opts); 7288 Builder.defineMacro("_MIPSEB"); 7289 } else { 7290 DefineStd(Builder, "MIPSEL", Opts); 7291 Builder.defineMacro("_MIPSEL"); 7292 } 7293 7294 Builder.defineMacro("__mips__"); 7295 Builder.defineMacro("_mips"); 7296 if (Opts.GNUMode) 7297 Builder.defineMacro("mips"); 7298 7299 if (ABI == "o32") { 7300 Builder.defineMacro("__mips", "32"); 7301 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7302 } else { 7303 Builder.defineMacro("__mips", "64"); 7304 Builder.defineMacro("__mips64"); 7305 Builder.defineMacro("__mips64__"); 7306 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7307 } 7308 7309 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7310 .Cases("mips32", "mips64", "1") 7311 .Cases("mips32r2", "mips64r2", "2") 7312 .Cases("mips32r3", "mips64r3", "3") 7313 .Cases("mips32r5", "mips64r5", "5") 7314 .Cases("mips32r6", "mips64r6", "6") 7315 .Default(""); 7316 if (!ISARev.empty()) 7317 Builder.defineMacro("__mips_isa_rev", ISARev); 7318 7319 if (ABI == "o32") { 7320 Builder.defineMacro("__mips_o32"); 7321 Builder.defineMacro("_ABIO32", "1"); 7322 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7323 } else if (ABI == "n32") { 7324 Builder.defineMacro("__mips_n32"); 7325 Builder.defineMacro("_ABIN32", "2"); 7326 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7327 } else if (ABI == "n64") { 7328 Builder.defineMacro("__mips_n64"); 7329 Builder.defineMacro("_ABI64", "3"); 7330 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7331 } else 7332 llvm_unreachable("Invalid ABI."); 7333 7334 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7335 7336 switch (FloatABI) { 7337 case HardFloat: 7338 Builder.defineMacro("__mips_hard_float", Twine(1)); 7339 break; 7340 case SoftFloat: 7341 Builder.defineMacro("__mips_soft_float", Twine(1)); 7342 break; 7343 } 7344 7345 if (IsSingleFloat) 7346 Builder.defineMacro("__mips_single_float", Twine(1)); 7347 7348 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7349 Builder.defineMacro("_MIPS_FPSET", 7350 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7351 7352 if (IsMips16) 7353 Builder.defineMacro("__mips16", Twine(1)); 7354 7355 if (IsMicromips) 7356 Builder.defineMacro("__mips_micromips", Twine(1)); 7357 7358 if (IsNan2008) 7359 Builder.defineMacro("__mips_nan2008", Twine(1)); 7360 7361 switch (DspRev) { 7362 default: 7363 break; 7364 case DSP1: 7365 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7366 Builder.defineMacro("__mips_dsp", Twine(1)); 7367 break; 7368 case DSP2: 7369 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7370 Builder.defineMacro("__mips_dspr2", Twine(1)); 7371 Builder.defineMacro("__mips_dsp", Twine(1)); 7372 break; 7373 } 7374 7375 if (HasMSA) 7376 Builder.defineMacro("__mips_msa", Twine(1)); 7377 7378 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7379 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7380 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7381 7382 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7383 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7384 7385 // These shouldn't be defined for MIPS-I but there's no need to check 7386 // for that since MIPS-I isn't supported. 7387 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7388 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7389 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7390 7391 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7392 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7393 // the instructions exist but using them violates the ABI since they 7394 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7395 if (ABI == "n32" || ABI == "n64") 7396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7397 } 7398 7399 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7400 return llvm::makeArrayRef(BuiltinInfo, 7401 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7402 } 7403 bool hasFeature(StringRef Feature) const override { 7404 return llvm::StringSwitch<bool>(Feature) 7405 .Case("mips", true) 7406 .Case("fp64", HasFP64) 7407 .Default(false); 7408 } 7409 BuiltinVaListKind getBuiltinVaListKind() const override { 7410 return TargetInfo::VoidPtrBuiltinVaList; 7411 } 7412 ArrayRef<const char *> getGCCRegNames() const override { 7413 static const char *const GCCRegNames[] = { 7414 // CPU register names 7415 // Must match second column of GCCRegAliases 7416 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7417 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7418 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7419 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7420 // Floating point register names 7421 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7422 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7423 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7424 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7425 // Hi/lo and condition register names 7426 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7427 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7428 "$ac3hi","$ac3lo", 7429 // MSA register names 7430 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7431 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7432 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7433 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7434 // MSA control register names 7435 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7436 "$msarequest", "$msamap", "$msaunmap" 7437 }; 7438 return llvm::makeArrayRef(GCCRegNames); 7439 } 7440 bool validateAsmConstraint(const char *&Name, 7441 TargetInfo::ConstraintInfo &Info) const override { 7442 switch (*Name) { 7443 default: 7444 return false; 7445 case 'r': // CPU registers. 7446 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7447 case 'y': // Equivalent to "r", backward compatibility only. 7448 case 'f': // floating-point registers. 7449 case 'c': // $25 for indirect jumps 7450 case 'l': // lo register 7451 case 'x': // hilo register pair 7452 Info.setAllowsRegister(); 7453 return true; 7454 case 'I': // Signed 16-bit constant 7455 case 'J': // Integer 0 7456 case 'K': // Unsigned 16-bit constant 7457 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7458 case 'M': // Constants not loadable via lui, addiu, or ori 7459 case 'N': // Constant -1 to -65535 7460 case 'O': // A signed 15-bit constant 7461 case 'P': // A constant between 1 go 65535 7462 return true; 7463 case 'R': // An address that can be used in a non-macro load or store 7464 Info.setAllowsMemory(); 7465 return true; 7466 case 'Z': 7467 if (Name[1] == 'C') { // An address usable by ll, and sc. 7468 Info.setAllowsMemory(); 7469 Name++; // Skip over 'Z'. 7470 return true; 7471 } 7472 return false; 7473 } 7474 } 7475 7476 std::string convertConstraint(const char *&Constraint) const override { 7477 std::string R; 7478 switch (*Constraint) { 7479 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7480 if (Constraint[1] == 'C') { 7481 R = std::string("^") + std::string(Constraint, 2); 7482 Constraint++; 7483 return R; 7484 } 7485 break; 7486 } 7487 return TargetInfo::convertConstraint(Constraint); 7488 } 7489 7490 const char *getClobbers() const override { 7491 // In GCC, $1 is not widely used in generated code (it's used only in a few 7492 // specific situations), so there is no real need for users to add it to 7493 // the clobbers list if they want to use it in their inline assembly code. 7494 // 7495 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7496 // code generation, so using it in inline assembly without adding it to the 7497 // clobbers list can cause conflicts between the inline assembly code and 7498 // the surrounding generated code. 7499 // 7500 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7501 // operands, which will conflict with the ".set at" assembler option (which 7502 // we use only for inline assembly, in order to maintain compatibility with 7503 // GCC) and will also conflict with the user's usage of $1. 7504 // 7505 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7506 // register for generated code is to automatically clobber $1 for all inline 7507 // assembly code. 7508 // 7509 // FIXME: We should automatically clobber $1 only for inline assembly code 7510 // which actually uses it. This would allow LLVM to use $1 for inline 7511 // assembly operands if the user's assembly code doesn't use it. 7512 return "~{$1}"; 7513 } 7514 7515 bool handleTargetFeatures(std::vector<std::string> &Features, 7516 DiagnosticsEngine &Diags) override { 7517 IsMips16 = false; 7518 IsMicromips = false; 7519 IsNan2008 = isNaN2008Default(); 7520 IsSingleFloat = false; 7521 FloatABI = HardFloat; 7522 DspRev = NoDSP; 7523 HasFP64 = isFP64Default(); 7524 7525 for (const auto &Feature : Features) { 7526 if (Feature == "+single-float") 7527 IsSingleFloat = true; 7528 else if (Feature == "+soft-float") 7529 FloatABI = SoftFloat; 7530 else if (Feature == "+mips16") 7531 IsMips16 = true; 7532 else if (Feature == "+micromips") 7533 IsMicromips = true; 7534 else if (Feature == "+dsp") 7535 DspRev = std::max(DspRev, DSP1); 7536 else if (Feature == "+dspr2") 7537 DspRev = std::max(DspRev, DSP2); 7538 else if (Feature == "+msa") 7539 HasMSA = true; 7540 else if (Feature == "+fp64") 7541 HasFP64 = true; 7542 else if (Feature == "-fp64") 7543 HasFP64 = false; 7544 else if (Feature == "+nan2008") 7545 IsNan2008 = true; 7546 else if (Feature == "-nan2008") 7547 IsNan2008 = false; 7548 } 7549 7550 setDataLayout(); 7551 7552 return true; 7553 } 7554 7555 int getEHDataRegisterNumber(unsigned RegNo) const override { 7556 if (RegNo == 0) return 4; 7557 if (RegNo == 1) return 5; 7558 return -1; 7559 } 7560 7561 bool isCLZForZeroUndef() const override { return false; } 7562 7563 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7564 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7565 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7566 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7567 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7568 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7569 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7570 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7571 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7572 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7573 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7574 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7575 {{"ra"}, "$31"}}; 7576 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7577 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7578 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7579 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7580 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7581 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7582 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7583 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7584 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7585 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7586 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7587 {{"ra"}, "$31"}}; 7588 if (ABI == "o32") 7589 return llvm::makeArrayRef(O32RegAliases); 7590 return llvm::makeArrayRef(NewABIRegAliases); 7591 } 7592 7593 bool hasInt128Type() const override { 7594 return ABI == "n32" || ABI == "n64"; 7595 } 7596 7597 bool validateTarget(DiagnosticsEngine &Diags) const override { 7598 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7599 // this yet. It's better to fail here than on the backend assertion. 7600 if (processorSupportsGPR64() && ABI == "o32") { 7601 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7602 return false; 7603 } 7604 7605 // 64-bit ABI's require 64-bit CPU's. 7606 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 7607 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7608 return false; 7609 } 7610 7611 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 7612 // can't handle this yet. It's better to fail here than on the 7613 // backend assertion. 7614 if ((getTriple().getArch() == llvm::Triple::mips64 || 7615 getTriple().getArch() == llvm::Triple::mips64el) && 7616 ABI == "o32") { 7617 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7618 << ABI << getTriple().str(); 7619 return false; 7620 } 7621 7622 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 7623 // can't handle this yet. It's better to fail here than on the 7624 // backend assertion. 7625 if ((getTriple().getArch() == llvm::Triple::mips || 7626 getTriple().getArch() == llvm::Triple::mipsel) && 7627 (ABI == "n32" || ABI == "n64")) { 7628 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7629 << ABI << getTriple().str(); 7630 return false; 7631 } 7632 7633 return true; 7634 } 7635 }; 7636 7637 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7638 #define BUILTIN(ID, TYPE, ATTRS) \ 7639 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7640 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7641 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7642 #include "clang/Basic/BuiltinsMips.def" 7643 }; 7644 7645 class PNaClTargetInfo : public TargetInfo { 7646 public: 7647 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7648 : TargetInfo(Triple) { 7649 BigEndian = false; 7650 this->LongAlign = 32; 7651 this->LongWidth = 32; 7652 this->PointerAlign = 32; 7653 this->PointerWidth = 32; 7654 this->IntMaxType = TargetInfo::SignedLongLong; 7655 this->Int64Type = TargetInfo::SignedLongLong; 7656 this->DoubleAlign = 64; 7657 this->LongDoubleWidth = 64; 7658 this->LongDoubleAlign = 64; 7659 this->SizeType = TargetInfo::UnsignedInt; 7660 this->PtrDiffType = TargetInfo::SignedInt; 7661 this->IntPtrType = TargetInfo::SignedInt; 7662 this->RegParmMax = 0; // Disallow regparm 7663 } 7664 7665 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7666 Builder.defineMacro("__le32__"); 7667 Builder.defineMacro("__pnacl__"); 7668 } 7669 void getTargetDefines(const LangOptions &Opts, 7670 MacroBuilder &Builder) const override { 7671 getArchDefines(Opts, Builder); 7672 } 7673 bool hasFeature(StringRef Feature) const override { 7674 return Feature == "pnacl"; 7675 } 7676 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7677 BuiltinVaListKind getBuiltinVaListKind() const override { 7678 return TargetInfo::PNaClABIBuiltinVaList; 7679 } 7680 ArrayRef<const char *> getGCCRegNames() const override; 7681 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7682 bool validateAsmConstraint(const char *&Name, 7683 TargetInfo::ConstraintInfo &Info) const override { 7684 return false; 7685 } 7686 7687 const char *getClobbers() const override { 7688 return ""; 7689 } 7690 }; 7691 7692 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7693 return None; 7694 } 7695 7696 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7697 return None; 7698 } 7699 7700 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7701 class NaClMips32TargetInfo : public MipsTargetInfo { 7702 public: 7703 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7704 : MipsTargetInfo(Triple, Opts) {} 7705 7706 BuiltinVaListKind getBuiltinVaListKind() const override { 7707 return TargetInfo::PNaClABIBuiltinVaList; 7708 } 7709 }; 7710 7711 class Le64TargetInfo : public TargetInfo { 7712 static const Builtin::Info BuiltinInfo[]; 7713 7714 public: 7715 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7716 : TargetInfo(Triple) { 7717 BigEndian = false; 7718 NoAsmVariants = true; 7719 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7720 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7721 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7722 } 7723 7724 void getTargetDefines(const LangOptions &Opts, 7725 MacroBuilder &Builder) const override { 7726 DefineStd(Builder, "unix", Opts); 7727 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7728 Builder.defineMacro("__ELF__"); 7729 } 7730 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7731 return llvm::makeArrayRef(BuiltinInfo, 7732 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7733 } 7734 BuiltinVaListKind getBuiltinVaListKind() const override { 7735 return TargetInfo::PNaClABIBuiltinVaList; 7736 } 7737 const char *getClobbers() const override { return ""; } 7738 ArrayRef<const char *> getGCCRegNames() const override { 7739 return None; 7740 } 7741 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7742 return None; 7743 } 7744 bool validateAsmConstraint(const char *&Name, 7745 TargetInfo::ConstraintInfo &Info) const override { 7746 return false; 7747 } 7748 7749 bool hasProtectedVisibility() const override { return false; } 7750 }; 7751 7752 class WebAssemblyTargetInfo : public TargetInfo { 7753 static const Builtin::Info BuiltinInfo[]; 7754 7755 enum SIMDEnum { 7756 NoSIMD, 7757 SIMD128, 7758 } SIMDLevel; 7759 7760 public: 7761 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7762 : TargetInfo(T), SIMDLevel(NoSIMD) { 7763 BigEndian = false; 7764 NoAsmVariants = true; 7765 SuitableAlign = 128; 7766 LargeArrayMinWidth = 128; 7767 LargeArrayAlign = 128; 7768 SimdDefaultAlign = 128; 7769 SigAtomicType = SignedLong; 7770 LongDoubleWidth = LongDoubleAlign = 128; 7771 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7772 } 7773 7774 protected: 7775 void getTargetDefines(const LangOptions &Opts, 7776 MacroBuilder &Builder) const override { 7777 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7778 if (SIMDLevel >= SIMD128) 7779 Builder.defineMacro("__wasm_simd128__"); 7780 } 7781 7782 private: 7783 bool 7784 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7785 StringRef CPU, 7786 const std::vector<std::string> &FeaturesVec) const override { 7787 if (CPU == "bleeding-edge") 7788 Features["simd128"] = true; 7789 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7790 } 7791 bool hasFeature(StringRef Feature) const final { 7792 return llvm::StringSwitch<bool>(Feature) 7793 .Case("simd128", SIMDLevel >= SIMD128) 7794 .Default(false); 7795 } 7796 bool handleTargetFeatures(std::vector<std::string> &Features, 7797 DiagnosticsEngine &Diags) final { 7798 for (const auto &Feature : Features) { 7799 if (Feature == "+simd128") { 7800 SIMDLevel = std::max(SIMDLevel, SIMD128); 7801 continue; 7802 } 7803 if (Feature == "-simd128") { 7804 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7805 continue; 7806 } 7807 7808 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7809 << "-target-feature"; 7810 return false; 7811 } 7812 return true; 7813 } 7814 bool setCPU(const std::string &Name) final { 7815 return llvm::StringSwitch<bool>(Name) 7816 .Case("mvp", true) 7817 .Case("bleeding-edge", true) 7818 .Case("generic", true) 7819 .Default(false); 7820 } 7821 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7822 return llvm::makeArrayRef(BuiltinInfo, 7823 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7824 } 7825 BuiltinVaListKind getBuiltinVaListKind() const final { 7826 return VoidPtrBuiltinVaList; 7827 } 7828 ArrayRef<const char *> getGCCRegNames() const final { 7829 return None; 7830 } 7831 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7832 return None; 7833 } 7834 bool 7835 validateAsmConstraint(const char *&Name, 7836 TargetInfo::ConstraintInfo &Info) const final { 7837 return false; 7838 } 7839 const char *getClobbers() const final { return ""; } 7840 bool isCLZForZeroUndef() const final { return false; } 7841 bool hasInt128Type() const final { return true; } 7842 IntType getIntTypeByWidth(unsigned BitWidth, 7843 bool IsSigned) const final { 7844 // WebAssembly prefers long long for explicitly 64-bit integers. 7845 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7846 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7847 } 7848 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7849 bool IsSigned) const final { 7850 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7851 return BitWidth == 64 7852 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7853 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7854 } 7855 }; 7856 7857 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7858 #define BUILTIN(ID, TYPE, ATTRS) \ 7859 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7860 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7861 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7862 #include "clang/Basic/BuiltinsWebAssembly.def" 7863 }; 7864 7865 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7866 public: 7867 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 7868 const TargetOptions &Opts) 7869 : WebAssemblyTargetInfo(T, Opts) { 7870 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7871 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7872 } 7873 7874 protected: 7875 void getTargetDefines(const LangOptions &Opts, 7876 MacroBuilder &Builder) const override { 7877 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7878 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7879 } 7880 }; 7881 7882 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7883 public: 7884 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 7885 const TargetOptions &Opts) 7886 : WebAssemblyTargetInfo(T, Opts) { 7887 LongAlign = LongWidth = 64; 7888 PointerAlign = PointerWidth = 64; 7889 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7890 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7891 } 7892 7893 protected: 7894 void getTargetDefines(const LangOptions &Opts, 7895 MacroBuilder &Builder) const override { 7896 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7897 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7898 } 7899 }; 7900 7901 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7902 #define BUILTIN(ID, TYPE, ATTRS) \ 7903 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7904 #include "clang/Basic/BuiltinsLe64.def" 7905 }; 7906 7907 static const unsigned SPIRAddrSpaceMap[] = { 7908 1, // opencl_global 7909 3, // opencl_local 7910 2, // opencl_constant 7911 4, // opencl_generic 7912 0, // cuda_device 7913 0, // cuda_constant 7914 0 // cuda_shared 7915 }; 7916 class SPIRTargetInfo : public TargetInfo { 7917 public: 7918 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7919 : TargetInfo(Triple) { 7920 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7921 "SPIR target must use unknown OS"); 7922 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7923 "SPIR target must use unknown environment type"); 7924 BigEndian = false; 7925 TLSSupported = false; 7926 LongWidth = LongAlign = 64; 7927 AddrSpaceMap = &SPIRAddrSpaceMap; 7928 UseAddrSpaceMapMangling = true; 7929 // Define available target features 7930 // These must be defined in sorted order! 7931 NoAsmVariants = true; 7932 } 7933 void getTargetDefines(const LangOptions &Opts, 7934 MacroBuilder &Builder) const override { 7935 DefineStd(Builder, "SPIR", Opts); 7936 } 7937 bool hasFeature(StringRef Feature) const override { 7938 return Feature == "spir"; 7939 } 7940 7941 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7942 const char *getClobbers() const override { return ""; } 7943 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7944 bool validateAsmConstraint(const char *&Name, 7945 TargetInfo::ConstraintInfo &info) const override { 7946 return true; 7947 } 7948 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7949 return None; 7950 } 7951 BuiltinVaListKind getBuiltinVaListKind() const override { 7952 return TargetInfo::VoidPtrBuiltinVaList; 7953 } 7954 7955 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7956 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 7957 : CCCR_Warning; 7958 } 7959 7960 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7961 return CC_SpirFunction; 7962 } 7963 7964 void setSupportedOpenCLOpts() override { 7965 // Assume all OpenCL extensions and optional core features are supported 7966 // for SPIR since it is a generic target. 7967 getSupportedOpenCLOpts().setAll(); 7968 } 7969 }; 7970 7971 class SPIR32TargetInfo : public SPIRTargetInfo { 7972 public: 7973 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7974 : SPIRTargetInfo(Triple, Opts) { 7975 PointerWidth = PointerAlign = 32; 7976 SizeType = TargetInfo::UnsignedInt; 7977 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7978 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7979 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7980 } 7981 void getTargetDefines(const LangOptions &Opts, 7982 MacroBuilder &Builder) const override { 7983 DefineStd(Builder, "SPIR32", Opts); 7984 } 7985 }; 7986 7987 class SPIR64TargetInfo : public SPIRTargetInfo { 7988 public: 7989 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7990 : SPIRTargetInfo(Triple, Opts) { 7991 PointerWidth = PointerAlign = 64; 7992 SizeType = TargetInfo::UnsignedLong; 7993 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7994 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7995 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7996 } 7997 void getTargetDefines(const LangOptions &Opts, 7998 MacroBuilder &Builder) const override { 7999 DefineStd(Builder, "SPIR64", Opts); 8000 } 8001 }; 8002 8003 class XCoreTargetInfo : public TargetInfo { 8004 static const Builtin::Info BuiltinInfo[]; 8005 public: 8006 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8007 : TargetInfo(Triple) { 8008 BigEndian = false; 8009 NoAsmVariants = true; 8010 LongLongAlign = 32; 8011 SuitableAlign = 32; 8012 DoubleAlign = LongDoubleAlign = 32; 8013 SizeType = UnsignedInt; 8014 PtrDiffType = SignedInt; 8015 IntPtrType = SignedInt; 8016 WCharType = UnsignedChar; 8017 WIntType = UnsignedInt; 8018 UseZeroLengthBitfieldAlignment = true; 8019 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8020 "-f64:32-a:0:32-n32"); 8021 } 8022 void getTargetDefines(const LangOptions &Opts, 8023 MacroBuilder &Builder) const override { 8024 Builder.defineMacro("__XS1B__"); 8025 } 8026 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8027 return llvm::makeArrayRef(BuiltinInfo, 8028 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8029 } 8030 BuiltinVaListKind getBuiltinVaListKind() const override { 8031 return TargetInfo::VoidPtrBuiltinVaList; 8032 } 8033 const char *getClobbers() const override { 8034 return ""; 8035 } 8036 ArrayRef<const char *> getGCCRegNames() const override { 8037 static const char * const GCCRegNames[] = { 8038 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8039 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8040 }; 8041 return llvm::makeArrayRef(GCCRegNames); 8042 } 8043 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8044 return None; 8045 } 8046 bool validateAsmConstraint(const char *&Name, 8047 TargetInfo::ConstraintInfo &Info) const override { 8048 return false; 8049 } 8050 int getEHDataRegisterNumber(unsigned RegNo) const override { 8051 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8052 return (RegNo < 2)? RegNo : -1; 8053 } 8054 bool allowsLargerPreferedTypeAlignment() const override { 8055 return false; 8056 } 8057 }; 8058 8059 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8060 #define BUILTIN(ID, TYPE, ATTRS) \ 8061 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8062 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8063 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8064 #include "clang/Basic/BuiltinsXCore.def" 8065 }; 8066 8067 // x86_32 Android target 8068 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8069 public: 8070 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8071 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8072 SuitableAlign = 32; 8073 LongDoubleWidth = 64; 8074 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 8075 } 8076 }; 8077 8078 // x86_64 Android target 8079 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8080 public: 8081 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8082 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8083 LongDoubleFormat = &llvm::APFloat::IEEEquad; 8084 } 8085 8086 bool useFloat128ManglingForLongDouble() const override { 8087 return true; 8088 } 8089 }; 8090 8091 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8092 class RenderScript32TargetInfo : public ARMleTargetInfo { 8093 public: 8094 RenderScript32TargetInfo(const llvm::Triple &Triple, 8095 const TargetOptions &Opts) 8096 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8097 Triple.getOSName(), 8098 Triple.getEnvironmentName()), 8099 Opts) { 8100 LongWidth = LongAlign = 64; 8101 } 8102 void getTargetDefines(const LangOptions &Opts, 8103 MacroBuilder &Builder) const override { 8104 Builder.defineMacro("__RENDERSCRIPT__"); 8105 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8106 } 8107 }; 8108 8109 // 64-bit RenderScript is aarch64 8110 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8111 public: 8112 RenderScript64TargetInfo(const llvm::Triple &Triple, 8113 const TargetOptions &Opts) 8114 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8115 Triple.getOSName(), 8116 Triple.getEnvironmentName()), 8117 Opts) {} 8118 8119 void getTargetDefines(const LangOptions &Opts, 8120 MacroBuilder &Builder) const override { 8121 Builder.defineMacro("__RENDERSCRIPT__"); 8122 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8123 } 8124 }; 8125 8126 } // end anonymous namespace 8127 8128 //===----------------------------------------------------------------------===// 8129 // Driver code 8130 //===----------------------------------------------------------------------===// 8131 8132 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8133 const TargetOptions &Opts) { 8134 llvm::Triple::OSType os = Triple.getOS(); 8135 8136 switch (Triple.getArch()) { 8137 default: 8138 return nullptr; 8139 8140 case llvm::Triple::xcore: 8141 return new XCoreTargetInfo(Triple, Opts); 8142 8143 case llvm::Triple::hexagon: 8144 return new HexagonTargetInfo(Triple, Opts); 8145 8146 case llvm::Triple::lanai: 8147 return new LanaiTargetInfo(Triple, Opts); 8148 8149 case llvm::Triple::aarch64: 8150 if (Triple.isOSDarwin()) 8151 return new DarwinAArch64TargetInfo(Triple, Opts); 8152 8153 switch (os) { 8154 case llvm::Triple::CloudABI: 8155 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8156 case llvm::Triple::FreeBSD: 8157 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8158 case llvm::Triple::Linux: 8159 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8160 case llvm::Triple::NetBSD: 8161 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8162 default: 8163 return new AArch64leTargetInfo(Triple, Opts); 8164 } 8165 8166 case llvm::Triple::aarch64_be: 8167 switch (os) { 8168 case llvm::Triple::FreeBSD: 8169 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8170 case llvm::Triple::Linux: 8171 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8172 case llvm::Triple::NetBSD: 8173 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8174 default: 8175 return new AArch64beTargetInfo(Triple, Opts); 8176 } 8177 8178 case llvm::Triple::arm: 8179 case llvm::Triple::thumb: 8180 if (Triple.isOSBinFormatMachO()) 8181 return new DarwinARMTargetInfo(Triple, Opts); 8182 8183 switch (os) { 8184 case llvm::Triple::Linux: 8185 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8186 case llvm::Triple::FreeBSD: 8187 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8188 case llvm::Triple::NetBSD: 8189 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8190 case llvm::Triple::OpenBSD: 8191 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8192 case llvm::Triple::Bitrig: 8193 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8194 case llvm::Triple::RTEMS: 8195 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8196 case llvm::Triple::NaCl: 8197 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8198 case llvm::Triple::Win32: 8199 switch (Triple.getEnvironment()) { 8200 case llvm::Triple::Cygnus: 8201 return new CygwinARMTargetInfo(Triple, Opts); 8202 case llvm::Triple::GNU: 8203 return new MinGWARMTargetInfo(Triple, Opts); 8204 case llvm::Triple::Itanium: 8205 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8206 case llvm::Triple::MSVC: 8207 default: // Assume MSVC for unknown environments 8208 return new MicrosoftARMleTargetInfo(Triple, Opts); 8209 } 8210 default: 8211 return new ARMleTargetInfo(Triple, Opts); 8212 } 8213 8214 case llvm::Triple::armeb: 8215 case llvm::Triple::thumbeb: 8216 if (Triple.isOSDarwin()) 8217 return new DarwinARMTargetInfo(Triple, Opts); 8218 8219 switch (os) { 8220 case llvm::Triple::Linux: 8221 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8222 case llvm::Triple::FreeBSD: 8223 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8224 case llvm::Triple::NetBSD: 8225 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8226 case llvm::Triple::OpenBSD: 8227 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8228 case llvm::Triple::Bitrig: 8229 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8230 case llvm::Triple::RTEMS: 8231 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8232 case llvm::Triple::NaCl: 8233 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8234 default: 8235 return new ARMbeTargetInfo(Triple, Opts); 8236 } 8237 8238 case llvm::Triple::bpfeb: 8239 case llvm::Triple::bpfel: 8240 return new BPFTargetInfo(Triple, Opts); 8241 8242 case llvm::Triple::msp430: 8243 return new MSP430TargetInfo(Triple, Opts); 8244 8245 case llvm::Triple::mips: 8246 switch (os) { 8247 case llvm::Triple::Linux: 8248 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8249 case llvm::Triple::RTEMS: 8250 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8251 case llvm::Triple::FreeBSD: 8252 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8253 case llvm::Triple::NetBSD: 8254 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8255 default: 8256 return new MipsTargetInfo(Triple, Opts); 8257 } 8258 8259 case llvm::Triple::mipsel: 8260 switch (os) { 8261 case llvm::Triple::Linux: 8262 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8263 case llvm::Triple::RTEMS: 8264 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8265 case llvm::Triple::FreeBSD: 8266 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8267 case llvm::Triple::NetBSD: 8268 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8269 case llvm::Triple::NaCl: 8270 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 8271 default: 8272 return new MipsTargetInfo(Triple, Opts); 8273 } 8274 8275 case llvm::Triple::mips64: 8276 switch (os) { 8277 case llvm::Triple::Linux: 8278 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8279 case llvm::Triple::RTEMS: 8280 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8281 case llvm::Triple::FreeBSD: 8282 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8283 case llvm::Triple::NetBSD: 8284 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8285 case llvm::Triple::OpenBSD: 8286 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8287 default: 8288 return new MipsTargetInfo(Triple, Opts); 8289 } 8290 8291 case llvm::Triple::mips64el: 8292 switch (os) { 8293 case llvm::Triple::Linux: 8294 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8295 case llvm::Triple::RTEMS: 8296 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8297 case llvm::Triple::FreeBSD: 8298 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8299 case llvm::Triple::NetBSD: 8300 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8301 case llvm::Triple::OpenBSD: 8302 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8303 default: 8304 return new MipsTargetInfo(Triple, Opts); 8305 } 8306 8307 case llvm::Triple::le32: 8308 switch (os) { 8309 case llvm::Triple::NaCl: 8310 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8311 default: 8312 return nullptr; 8313 } 8314 8315 case llvm::Triple::le64: 8316 return new Le64TargetInfo(Triple, Opts); 8317 8318 case llvm::Triple::ppc: 8319 if (Triple.isOSDarwin()) 8320 return new DarwinPPC32TargetInfo(Triple, Opts); 8321 switch (os) { 8322 case llvm::Triple::Linux: 8323 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8324 case llvm::Triple::FreeBSD: 8325 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8326 case llvm::Triple::NetBSD: 8327 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8328 case llvm::Triple::OpenBSD: 8329 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8330 case llvm::Triple::RTEMS: 8331 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8332 default: 8333 return new PPC32TargetInfo(Triple, Opts); 8334 } 8335 8336 case llvm::Triple::ppc64: 8337 if (Triple.isOSDarwin()) 8338 return new DarwinPPC64TargetInfo(Triple, Opts); 8339 switch (os) { 8340 case llvm::Triple::Linux: 8341 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8342 case llvm::Triple::Lv2: 8343 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8344 case llvm::Triple::FreeBSD: 8345 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8346 case llvm::Triple::NetBSD: 8347 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8348 default: 8349 return new PPC64TargetInfo(Triple, Opts); 8350 } 8351 8352 case llvm::Triple::ppc64le: 8353 switch (os) { 8354 case llvm::Triple::Linux: 8355 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8356 case llvm::Triple::NetBSD: 8357 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8358 default: 8359 return new PPC64TargetInfo(Triple, Opts); 8360 } 8361 8362 case llvm::Triple::nvptx: 8363 return new NVPTX32TargetInfo(Triple, Opts); 8364 case llvm::Triple::nvptx64: 8365 return new NVPTX64TargetInfo(Triple, Opts); 8366 8367 case llvm::Triple::amdgcn: 8368 case llvm::Triple::r600: 8369 return new AMDGPUTargetInfo(Triple, Opts); 8370 8371 case llvm::Triple::sparc: 8372 switch (os) { 8373 case llvm::Triple::Linux: 8374 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8375 case llvm::Triple::Solaris: 8376 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8377 case llvm::Triple::NetBSD: 8378 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8379 case llvm::Triple::OpenBSD: 8380 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8381 case llvm::Triple::RTEMS: 8382 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8383 default: 8384 return new SparcV8TargetInfo(Triple, Opts); 8385 } 8386 8387 // The 'sparcel' architecture copies all the above cases except for Solaris. 8388 case llvm::Triple::sparcel: 8389 switch (os) { 8390 case llvm::Triple::Linux: 8391 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8392 case llvm::Triple::NetBSD: 8393 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8394 case llvm::Triple::OpenBSD: 8395 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8396 case llvm::Triple::RTEMS: 8397 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8398 default: 8399 return new SparcV8elTargetInfo(Triple, Opts); 8400 } 8401 8402 case llvm::Triple::sparcv9: 8403 switch (os) { 8404 case llvm::Triple::Linux: 8405 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8406 case llvm::Triple::Solaris: 8407 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8408 case llvm::Triple::NetBSD: 8409 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8410 case llvm::Triple::OpenBSD: 8411 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8412 case llvm::Triple::FreeBSD: 8413 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8414 default: 8415 return new SparcV9TargetInfo(Triple, Opts); 8416 } 8417 8418 case llvm::Triple::systemz: 8419 switch (os) { 8420 case llvm::Triple::Linux: 8421 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8422 default: 8423 return new SystemZTargetInfo(Triple, Opts); 8424 } 8425 8426 case llvm::Triple::tce: 8427 return new TCETargetInfo(Triple, Opts); 8428 8429 case llvm::Triple::x86: 8430 if (Triple.isOSDarwin()) 8431 return new DarwinI386TargetInfo(Triple, Opts); 8432 8433 switch (os) { 8434 case llvm::Triple::CloudABI: 8435 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8436 case llvm::Triple::Linux: { 8437 switch (Triple.getEnvironment()) { 8438 default: 8439 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8440 case llvm::Triple::Android: 8441 return new AndroidX86_32TargetInfo(Triple, Opts); 8442 } 8443 } 8444 case llvm::Triple::DragonFly: 8445 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8446 case llvm::Triple::NetBSD: 8447 return new NetBSDI386TargetInfo(Triple, Opts); 8448 case llvm::Triple::OpenBSD: 8449 return new OpenBSDI386TargetInfo(Triple, Opts); 8450 case llvm::Triple::Bitrig: 8451 return new BitrigI386TargetInfo(Triple, Opts); 8452 case llvm::Triple::FreeBSD: 8453 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8454 case llvm::Triple::KFreeBSD: 8455 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8456 case llvm::Triple::Minix: 8457 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8458 case llvm::Triple::Solaris: 8459 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8460 case llvm::Triple::Win32: { 8461 switch (Triple.getEnvironment()) { 8462 case llvm::Triple::Cygnus: 8463 return new CygwinX86_32TargetInfo(Triple, Opts); 8464 case llvm::Triple::GNU: 8465 return new MinGWX86_32TargetInfo(Triple, Opts); 8466 case llvm::Triple::Itanium: 8467 case llvm::Triple::MSVC: 8468 default: // Assume MSVC for unknown environments 8469 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8470 } 8471 } 8472 case llvm::Triple::Haiku: 8473 return new HaikuX86_32TargetInfo(Triple, Opts); 8474 case llvm::Triple::RTEMS: 8475 return new RTEMSX86_32TargetInfo(Triple, Opts); 8476 case llvm::Triple::NaCl: 8477 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8478 case llvm::Triple::ELFIAMCU: 8479 return new MCUX86_32TargetInfo(Triple, Opts); 8480 default: 8481 return new X86_32TargetInfo(Triple, Opts); 8482 } 8483 8484 case llvm::Triple::x86_64: 8485 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8486 return new DarwinX86_64TargetInfo(Triple, Opts); 8487 8488 switch (os) { 8489 case llvm::Triple::CloudABI: 8490 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8491 case llvm::Triple::Linux: { 8492 switch (Triple.getEnvironment()) { 8493 default: 8494 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8495 case llvm::Triple::Android: 8496 return new AndroidX86_64TargetInfo(Triple, Opts); 8497 } 8498 } 8499 case llvm::Triple::DragonFly: 8500 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8501 case llvm::Triple::NetBSD: 8502 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8503 case llvm::Triple::OpenBSD: 8504 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8505 case llvm::Triple::Bitrig: 8506 return new BitrigX86_64TargetInfo(Triple, Opts); 8507 case llvm::Triple::FreeBSD: 8508 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8509 case llvm::Triple::KFreeBSD: 8510 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8511 case llvm::Triple::Solaris: 8512 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8513 case llvm::Triple::Win32: { 8514 switch (Triple.getEnvironment()) { 8515 case llvm::Triple::Cygnus: 8516 return new CygwinX86_64TargetInfo(Triple, Opts); 8517 case llvm::Triple::GNU: 8518 return new MinGWX86_64TargetInfo(Triple, Opts); 8519 case llvm::Triple::MSVC: 8520 default: // Assume MSVC for unknown environments 8521 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8522 } 8523 } 8524 case llvm::Triple::Haiku: 8525 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8526 case llvm::Triple::NaCl: 8527 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8528 case llvm::Triple::PS4: 8529 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8530 default: 8531 return new X86_64TargetInfo(Triple, Opts); 8532 } 8533 8534 case llvm::Triple::spir: { 8535 if (Triple.getOS() != llvm::Triple::UnknownOS || 8536 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8537 return nullptr; 8538 return new SPIR32TargetInfo(Triple, Opts); 8539 } 8540 case llvm::Triple::spir64: { 8541 if (Triple.getOS() != llvm::Triple::UnknownOS || 8542 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8543 return nullptr; 8544 return new SPIR64TargetInfo(Triple, Opts); 8545 } 8546 case llvm::Triple::wasm32: 8547 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8548 return nullptr; 8549 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8550 case llvm::Triple::wasm64: 8551 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8552 return nullptr; 8553 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8554 8555 case llvm::Triple::renderscript32: 8556 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 8557 case llvm::Triple::renderscript64: 8558 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 8559 } 8560 } 8561 8562 /// CreateTargetInfo - Return the target info object for the specified target 8563 /// options. 8564 TargetInfo * 8565 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8566 const std::shared_ptr<TargetOptions> &Opts) { 8567 llvm::Triple Triple(Opts->Triple); 8568 8569 // Construct the target 8570 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8571 if (!Target) { 8572 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8573 return nullptr; 8574 } 8575 Target->TargetOpts = Opts; 8576 8577 // Set the target CPU if specified. 8578 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8579 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8580 return nullptr; 8581 } 8582 8583 // Set the target ABI if specified. 8584 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8585 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8586 return nullptr; 8587 } 8588 8589 // Set the fp math unit. 8590 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8591 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8592 return nullptr; 8593 } 8594 8595 // Compute the default target features, we need the target to handle this 8596 // because features may have dependencies on one another. 8597 llvm::StringMap<bool> Features; 8598 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8599 Opts->FeaturesAsWritten)) 8600 return nullptr; 8601 8602 // Add the features to the compile options. 8603 Opts->Features.clear(); 8604 for (const auto &F : Features) 8605 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8606 8607 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8608 return nullptr; 8609 8610 Target->setSupportedOpenCLOpts(); 8611 8612 if (!Target->validateTarget(Diags)) 8613 return nullptr; 8614 8615 return Target.release(); 8616 } 8617