1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/MC/MCSectionMachO.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include <algorithm>
31 #include <memory>
32 using namespace clang;
33 
34 //===----------------------------------------------------------------------===//
35 //  Common code shared among targets.
36 //===----------------------------------------------------------------------===//
37 
38 /// DefineStd - Define a macro name and standard variants.  For example if
39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40 /// when in GNU mode.
41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                       const LangOptions &Opts) {
43   assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44 
45   // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46   // in the user's namespace.
47   if (Opts.GNUMode)
48     Builder.defineMacro(MacroName);
49 
50   // Define __unix.
51   Builder.defineMacro("__" + MacroName);
52 
53   // Define __unix__.
54   Builder.defineMacro("__" + MacroName + "__");
55 }
56 
57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                             bool Tuning = true) {
59   Builder.defineMacro("__" + CPUName);
60   Builder.defineMacro("__" + CPUName + "__");
61   if (Tuning)
62     Builder.defineMacro("__tune_" + CPUName + "__");
63 }
64 
65 //===----------------------------------------------------------------------===//
66 // Defines specific to certain operating systems.
67 //===----------------------------------------------------------------------===//
68 
69 namespace {
70 template<typename TgtInfo>
71 class OSTargetInfo : public TgtInfo {
72 protected:
73   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                             MacroBuilder &Builder) const=0;
75 public:
76   OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
77   void getTargetDefines(const LangOptions &Opts,
78                         MacroBuilder &Builder) const override {
79     TgtInfo::getTargetDefines(Opts, Builder);
80     getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81   }
82 
83 };
84 } // end anonymous namespace
85 
86 
87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                              const llvm::Triple &Triple,
89                              StringRef &PlatformName,
90                              VersionTuple &PlatformMinVersion) {
91   Builder.defineMacro("__APPLE_CC__", "6000");
92   Builder.defineMacro("__APPLE__");
93   Builder.defineMacro("OBJC_NEW_PROPERTIES");
94   // AddressSanitizer doesn't play well with source fortification, which is on
95   // by default on Darwin.
96   if (Opts.Sanitize.has(SanitizerKind::Address))
97     Builder.defineMacro("_FORTIFY_SOURCE", "0");
98 
99   if (!Opts.ObjCAutoRefCount) {
100     // __weak is always defined, for use in blocks and with objc pointers.
101     Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102 
103     // Darwin defines __strong even in C mode (just to nothing).
104     if (Opts.getGC() != LangOptions::NonGC)
105       Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106     else
107       Builder.defineMacro("__strong", "");
108 
109     // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110     // allow this in C, since one might have block pointers in structs that
111     // are used in pure C code and in Objective-C ARC.
112     Builder.defineMacro("__unsafe_unretained", "");
113   }
114 
115   if (Opts.Static)
116     Builder.defineMacro("__STATIC__");
117   else
118     Builder.defineMacro("__DYNAMIC__");
119 
120   if (Opts.POSIXThreads)
121     Builder.defineMacro("_REENTRANT");
122 
123   // Get the platform type and version number from the triple.
124   unsigned Maj, Min, Rev;
125   if (Triple.isMacOSX()) {
126     Triple.getMacOSXVersion(Maj, Min, Rev);
127     PlatformName = "macosx";
128   } else {
129     Triple.getOSVersion(Maj, Min, Rev);
130     PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131   }
132 
133   // If -target arch-pc-win32-macho option specified, we're
134   // generating code for Win32 ABI. No need to emit
135   // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136   if (PlatformName == "win32") {
137     PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138     return;
139   }
140 
141   // Set the appropriate OS version define.
142   if (Triple.isiOS()) {
143     assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144     char Str[6];
145     Str[0] = '0' + Maj;
146     Str[1] = '0' + (Min / 10);
147     Str[2] = '0' + (Min % 10);
148     Str[3] = '0' + (Rev / 10);
149     Str[4] = '0' + (Rev % 10);
150     Str[5] = '\0';
151     Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
152                         Str);
153   } else if (Triple.isMacOSX()) {
154     // Note that the Driver allows versions which aren't representable in the
155     // define (because we only get a single digit for the minor and micro
156     // revision numbers). So, we limit them to the maximum representable
157     // version.
158     assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159     char Str[7];
160     if (Maj < 10 || (Maj == 10 && Min < 10)) {
161       Str[0] = '0' + (Maj / 10);
162       Str[1] = '0' + (Maj % 10);
163       Str[2] = '0' + std::min(Min, 9U);
164       Str[3] = '0' + std::min(Rev, 9U);
165       Str[4] = '\0';
166     } else {
167       // Handle versions > 10.9.
168       Str[0] = '0' + (Maj / 10);
169       Str[1] = '0' + (Maj % 10);
170       Str[2] = '0' + (Min / 10);
171       Str[3] = '0' + (Min % 10);
172       Str[4] = '0' + (Rev / 10);
173       Str[5] = '0' + (Rev % 10);
174       Str[6] = '\0';
175     }
176     Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
177   }
178 
179   // Tell users about the kernel if there is one.
180   if (Triple.isOSDarwin())
181     Builder.defineMacro("__MACH__");
182 
183   PlatformMinVersion = VersionTuple(Maj, Min, Rev);
184 }
185 
186 namespace {
187 template<typename Target>
188 class DarwinTargetInfo : public OSTargetInfo<Target> {
189 protected:
190   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
191                     MacroBuilder &Builder) const override {
192     getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
193                      this->PlatformMinVersion);
194   }
195 
196 public:
197   DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
198     this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
199     this->MCountName = "\01mcount";
200   }
201 
202   std::string isValidSectionSpecifier(StringRef SR) const override {
203     // Let MCSectionMachO validate this.
204     StringRef Segment, Section;
205     unsigned TAA, StubSize;
206     bool HasTAA;
207     return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
208                                                        TAA, HasTAA, StubSize);
209   }
210 
211   const char *getStaticInitSectionSpecifier() const override {
212     // FIXME: We should return 0 when building kexts.
213     return "__TEXT,__StaticInit,regular,pure_instructions";
214   }
215 
216   /// Darwin does not support protected visibility.  Darwin's "default"
217   /// is very similar to ELF's "protected";  Darwin requires a "weak"
218   /// attribute on declarations that can be dynamically replaced.
219   bool hasProtectedVisibility() const override {
220     return false;
221   }
222 };
223 
224 
225 // DragonFlyBSD Target
226 template<typename Target>
227 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
228 protected:
229   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
230                     MacroBuilder &Builder) const override {
231     // DragonFly defines; list based off of gcc output
232     Builder.defineMacro("__DragonFly__");
233     Builder.defineMacro("__DragonFly_cc_version", "100001");
234     Builder.defineMacro("__ELF__");
235     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
236     Builder.defineMacro("__tune_i386__");
237     DefineStd(Builder, "unix", Opts);
238   }
239 public:
240   DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
241       : OSTargetInfo<Target>(Triple) {
242     this->UserLabelPrefix = "";
243 
244     switch (Triple.getArch()) {
245     default:
246     case llvm::Triple::x86:
247     case llvm::Triple::x86_64:
248       this->MCountName = ".mcount";
249       break;
250     }
251   }
252 };
253 
254 // FreeBSD Target
255 template<typename Target>
256 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
257 protected:
258   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
259                     MacroBuilder &Builder) const override {
260     // FreeBSD defines; list based off of gcc output
261 
262     unsigned Release = Triple.getOSMajorVersion();
263     if (Release == 0U)
264       Release = 8;
265 
266     Builder.defineMacro("__FreeBSD__", Twine(Release));
267     Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
268     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
269     DefineStd(Builder, "unix", Opts);
270     Builder.defineMacro("__ELF__");
271 
272     // On FreeBSD, wchar_t contains the number of the code point as
273     // used by the character set of the locale. These character sets are
274     // not necessarily a superset of ASCII.
275     //
276     // FIXME: This is wrong; the macro refers to the numerical values
277     // of wchar_t *literals*, which are not locale-dependent. However,
278     // FreeBSD systems apparently depend on us getting this wrong, and
279     // setting this to 1 is conforming even if all the basic source
280     // character literals have the same encoding as char and wchar_t.
281     Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
282   }
283 public:
284   FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
285     this->UserLabelPrefix = "";
286 
287     switch (Triple.getArch()) {
288     default:
289     case llvm::Triple::x86:
290     case llvm::Triple::x86_64:
291       this->MCountName = ".mcount";
292       break;
293     case llvm::Triple::mips:
294     case llvm::Triple::mipsel:
295     case llvm::Triple::ppc:
296     case llvm::Triple::ppc64:
297     case llvm::Triple::ppc64le:
298       this->MCountName = "_mcount";
299       break;
300     case llvm::Triple::arm:
301       this->MCountName = "__mcount";
302       break;
303     }
304   }
305 };
306 
307 // GNU/kFreeBSD Target
308 template<typename Target>
309 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
310 protected:
311   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
312                     MacroBuilder &Builder) const override {
313     // GNU/kFreeBSD defines; list based off of gcc output
314 
315     DefineStd(Builder, "unix", Opts);
316     Builder.defineMacro("__FreeBSD_kernel__");
317     Builder.defineMacro("__GLIBC__");
318     Builder.defineMacro("__ELF__");
319     if (Opts.POSIXThreads)
320       Builder.defineMacro("_REENTRANT");
321     if (Opts.CPlusPlus)
322       Builder.defineMacro("_GNU_SOURCE");
323   }
324 public:
325   KFreeBSDTargetInfo(const llvm::Triple &Triple)
326       : OSTargetInfo<Target>(Triple) {
327     this->UserLabelPrefix = "";
328   }
329 };
330 
331 // Minix Target
332 template<typename Target>
333 class MinixTargetInfo : public OSTargetInfo<Target> {
334 protected:
335   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
336                     MacroBuilder &Builder) const override {
337     // Minix defines
338 
339     Builder.defineMacro("__minix", "3");
340     Builder.defineMacro("_EM_WSIZE", "4");
341     Builder.defineMacro("_EM_PSIZE", "4");
342     Builder.defineMacro("_EM_SSIZE", "2");
343     Builder.defineMacro("_EM_LSIZE", "4");
344     Builder.defineMacro("_EM_FSIZE", "4");
345     Builder.defineMacro("_EM_DSIZE", "8");
346     Builder.defineMacro("__ELF__");
347     DefineStd(Builder, "unix", Opts);
348   }
349 public:
350   MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
351     this->UserLabelPrefix = "";
352   }
353 };
354 
355 // Linux target
356 template<typename Target>
357 class LinuxTargetInfo : public OSTargetInfo<Target> {
358 protected:
359   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
360                     MacroBuilder &Builder) const override {
361     // Linux defines; list based off of gcc output
362     DefineStd(Builder, "unix", Opts);
363     DefineStd(Builder, "linux", Opts);
364     Builder.defineMacro("__gnu_linux__");
365     Builder.defineMacro("__ELF__");
366     if (Triple.getEnvironment() == llvm::Triple::Android) {
367       Builder.defineMacro("__ANDROID__", "1");
368       unsigned Maj, Min, Rev;
369       Triple.getOSVersion(Maj, Min, Rev);
370       this->PlatformName = "android";
371       this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
372     }
373     if (Opts.POSIXThreads)
374       Builder.defineMacro("_REENTRANT");
375     if (Opts.CPlusPlus)
376       Builder.defineMacro("_GNU_SOURCE");
377   }
378 public:
379   LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
380     this->UserLabelPrefix = "";
381     this->WIntType = TargetInfo::UnsignedInt;
382 
383     switch (Triple.getArch()) {
384     default:
385       break;
386     case llvm::Triple::ppc:
387     case llvm::Triple::ppc64:
388     case llvm::Triple::ppc64le:
389       this->MCountName = "_mcount";
390       break;
391     }
392   }
393 
394   const char *getStaticInitSectionSpecifier() const override {
395     return ".text.startup";
396   }
397 };
398 
399 // NetBSD Target
400 template<typename Target>
401 class NetBSDTargetInfo : public OSTargetInfo<Target> {
402 protected:
403   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
404                     MacroBuilder &Builder) const override {
405     // NetBSD defines; list based off of gcc output
406     Builder.defineMacro("__NetBSD__");
407     Builder.defineMacro("__unix__");
408     Builder.defineMacro("__ELF__");
409     if (Opts.POSIXThreads)
410       Builder.defineMacro("_POSIX_THREADS");
411 
412     switch (Triple.getArch()) {
413     default:
414       break;
415     case llvm::Triple::arm:
416     case llvm::Triple::armeb:
417     case llvm::Triple::thumb:
418     case llvm::Triple::thumbeb:
419       Builder.defineMacro("__ARM_DWARF_EH__");
420       break;
421     }
422   }
423 public:
424   NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
425     this->UserLabelPrefix = "";
426   }
427 };
428 
429 // OpenBSD Target
430 template<typename Target>
431 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
432 protected:
433   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
434                     MacroBuilder &Builder) const override {
435     // OpenBSD defines; list based off of gcc output
436 
437     Builder.defineMacro("__OpenBSD__");
438     DefineStd(Builder, "unix", Opts);
439     Builder.defineMacro("__ELF__");
440     if (Opts.POSIXThreads)
441       Builder.defineMacro("_REENTRANT");
442   }
443 public:
444   OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
445     this->UserLabelPrefix = "";
446     this->TLSSupported = false;
447 
448       switch (Triple.getArch()) {
449         default:
450         case llvm::Triple::x86:
451         case llvm::Triple::x86_64:
452         case llvm::Triple::arm:
453         case llvm::Triple::sparc:
454           this->MCountName = "__mcount";
455           break;
456         case llvm::Triple::mips64:
457         case llvm::Triple::mips64el:
458         case llvm::Triple::ppc:
459         case llvm::Triple::sparcv9:
460           this->MCountName = "_mcount";
461           break;
462       }
463   }
464 };
465 
466 // Bitrig Target
467 template<typename Target>
468 class BitrigTargetInfo : public OSTargetInfo<Target> {
469 protected:
470   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
471                     MacroBuilder &Builder) const override {
472     // Bitrig defines; list based off of gcc output
473 
474     Builder.defineMacro("__Bitrig__");
475     DefineStd(Builder, "unix", Opts);
476     Builder.defineMacro("__ELF__");
477     if (Opts.POSIXThreads)
478       Builder.defineMacro("_REENTRANT");
479 
480     switch (Triple.getArch()) {
481     default:
482       break;
483     case llvm::Triple::arm:
484     case llvm::Triple::armeb:
485     case llvm::Triple::thumb:
486     case llvm::Triple::thumbeb:
487       Builder.defineMacro("__ARM_DWARF_EH__");
488       break;
489     }
490   }
491 public:
492   BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
493     this->UserLabelPrefix = "";
494     this->MCountName = "__mcount";
495   }
496 };
497 
498 // PSP Target
499 template<typename Target>
500 class PSPTargetInfo : public OSTargetInfo<Target> {
501 protected:
502   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
503                     MacroBuilder &Builder) const override {
504     // PSP defines; list based on the output of the pspdev gcc toolchain.
505     Builder.defineMacro("PSP");
506     Builder.defineMacro("_PSP");
507     Builder.defineMacro("__psp__");
508     Builder.defineMacro("__ELF__");
509   }
510 public:
511   PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
512     this->UserLabelPrefix = "";
513   }
514 };
515 
516 // PS3 PPU Target
517 template<typename Target>
518 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
519 protected:
520   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
521                     MacroBuilder &Builder) const override {
522     // PS3 PPU defines.
523     Builder.defineMacro("__PPC__");
524     Builder.defineMacro("__PPU__");
525     Builder.defineMacro("__CELLOS_LV2__");
526     Builder.defineMacro("__ELF__");
527     Builder.defineMacro("__LP32__");
528     Builder.defineMacro("_ARCH_PPC64");
529     Builder.defineMacro("__powerpc64__");
530   }
531 public:
532   PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
533     this->UserLabelPrefix = "";
534     this->LongWidth = this->LongAlign = 32;
535     this->PointerWidth = this->PointerAlign = 32;
536     this->IntMaxType = TargetInfo::SignedLongLong;
537     this->Int64Type = TargetInfo::SignedLongLong;
538     this->SizeType = TargetInfo::UnsignedInt;
539     this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
540   }
541 };
542 
543 template <typename Target>
544 class PS4OSTargetInfo : public OSTargetInfo<Target> {
545 protected:
546   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
547                     MacroBuilder &Builder) const override {
548     Builder.defineMacro("__FreeBSD__", "9");
549     Builder.defineMacro("__FreeBSD_cc_version", "900001");
550     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
551     DefineStd(Builder, "unix", Opts);
552     Builder.defineMacro("__ELF__");
553     Builder.defineMacro("__PS4__");
554   }
555 public:
556   PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
557     this->WCharType = this->UnsignedShort;
558 
559     this->UserLabelPrefix = "";
560 
561     switch (Triple.getArch()) {
562     default:
563     case llvm::Triple::x86_64:
564       this->MCountName = ".mcount";
565       break;
566     }
567   }
568 };
569 
570 // Solaris target
571 template<typename Target>
572 class SolarisTargetInfo : public OSTargetInfo<Target> {
573 protected:
574   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
575                     MacroBuilder &Builder) const override {
576     DefineStd(Builder, "sun", Opts);
577     DefineStd(Builder, "unix", Opts);
578     Builder.defineMacro("__ELF__");
579     Builder.defineMacro("__svr4__");
580     Builder.defineMacro("__SVR4");
581     // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
582     // newer, but to 500 for everything else.  feature_test.h has a check to
583     // ensure that you are not using C99 with an old version of X/Open or C89
584     // with a new version.
585     if (Opts.C99)
586       Builder.defineMacro("_XOPEN_SOURCE", "600");
587     else
588       Builder.defineMacro("_XOPEN_SOURCE", "500");
589     if (Opts.CPlusPlus)
590       Builder.defineMacro("__C99FEATURES__");
591     Builder.defineMacro("_LARGEFILE_SOURCE");
592     Builder.defineMacro("_LARGEFILE64_SOURCE");
593     Builder.defineMacro("__EXTENSIONS__");
594     Builder.defineMacro("_REENTRANT");
595   }
596 public:
597   SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
598     this->UserLabelPrefix = "";
599     this->WCharType = this->SignedInt;
600     // FIXME: WIntType should be SignedLong
601   }
602 };
603 
604 // Windows target
605 template<typename Target>
606 class WindowsTargetInfo : public OSTargetInfo<Target> {
607 protected:
608   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
609                     MacroBuilder &Builder) const override {
610     Builder.defineMacro("_WIN32");
611   }
612   void getVisualStudioDefines(const LangOptions &Opts,
613                               MacroBuilder &Builder) const {
614     if (Opts.CPlusPlus) {
615       if (Opts.RTTIData)
616         Builder.defineMacro("_CPPRTTI");
617 
618       if (Opts.CXXExceptions)
619         Builder.defineMacro("_CPPUNWIND");
620     }
621 
622     if (!Opts.CharIsSigned)
623       Builder.defineMacro("_CHAR_UNSIGNED");
624 
625     // FIXME: POSIXThreads isn't exactly the option this should be defined for,
626     //        but it works for now.
627     if (Opts.POSIXThreads)
628       Builder.defineMacro("_MT");
629 
630     if (Opts.MSCompatibilityVersion) {
631       Builder.defineMacro("_MSC_VER",
632                           Twine(Opts.MSCompatibilityVersion / 100000));
633       Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
634       // FIXME We cannot encode the revision information into 32-bits
635       Builder.defineMacro("_MSC_BUILD", Twine(1));
636     }
637 
638     if (Opts.MicrosoftExt) {
639       Builder.defineMacro("_MSC_EXTENSIONS");
640 
641       if (Opts.CPlusPlus11) {
642         Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
643         Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
644         Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
645       }
646     }
647 
648     Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
649   }
650 
651 public:
652   WindowsTargetInfo(const llvm::Triple &Triple)
653       : OSTargetInfo<Target>(Triple) {}
654 };
655 
656 template <typename Target>
657 class NaClTargetInfo : public OSTargetInfo<Target> {
658 protected:
659   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
660                     MacroBuilder &Builder) const override {
661     if (Opts.POSIXThreads)
662       Builder.defineMacro("_REENTRANT");
663     if (Opts.CPlusPlus)
664       Builder.defineMacro("_GNU_SOURCE");
665 
666     DefineStd(Builder, "unix", Opts);
667     Builder.defineMacro("__ELF__");
668     Builder.defineMacro("__native_client__");
669   }
670 
671 public:
672   NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
673     this->UserLabelPrefix = "";
674     this->LongAlign = 32;
675     this->LongWidth = 32;
676     this->PointerAlign = 32;
677     this->PointerWidth = 32;
678     this->IntMaxType = TargetInfo::SignedLongLong;
679     this->Int64Type = TargetInfo::SignedLongLong;
680     this->DoubleAlign = 64;
681     this->LongDoubleWidth = 64;
682     this->LongDoubleAlign = 64;
683     this->LongLongWidth = 64;
684     this->LongLongAlign = 64;
685     this->SizeType = TargetInfo::UnsignedInt;
686     this->PtrDiffType = TargetInfo::SignedInt;
687     this->IntPtrType = TargetInfo::SignedInt;
688     // RegParmMax is inherited from the underlying architecture
689     this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
690     if (Triple.getArch() == llvm::Triple::arm) {
691       this->DescriptionString =
692           "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
693     } else if (Triple.getArch() == llvm::Triple::x86) {
694       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
695     } else if (Triple.getArch() == llvm::Triple::x86_64) {
696       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
697     } else if (Triple.getArch() == llvm::Triple::mipsel) {
698       // Handled on mips' setDescriptionString.
699     } else {
700       assert(Triple.getArch() == llvm::Triple::le32);
701       this->DescriptionString = "e-p:32:32-i64:64";
702     }
703   }
704 };
705 } // end anonymous namespace.
706 
707 //===----------------------------------------------------------------------===//
708 // Specific target implementations.
709 //===----------------------------------------------------------------------===//
710 
711 namespace {
712 // PPC abstract base class
713 class PPCTargetInfo : public TargetInfo {
714   static const Builtin::Info BuiltinInfo[];
715   static const char * const GCCRegNames[];
716   static const TargetInfo::GCCRegAlias GCCRegAliases[];
717   std::string CPU;
718 
719   // Target cpu features.
720   bool HasVSX;
721   bool HasP8Vector;
722 
723 protected:
724   std::string ABI;
725 
726 public:
727   PPCTargetInfo(const llvm::Triple &Triple)
728     : TargetInfo(Triple), HasVSX(false), HasP8Vector(false) {
729     BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
730     LongDoubleWidth = LongDoubleAlign = 128;
731     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
732   }
733 
734   /// \brief Flags for architecture specific defines.
735   typedef enum {
736     ArchDefineNone  = 0,
737     ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
738     ArchDefinePpcgr = 1 << 1,
739     ArchDefinePpcsq = 1 << 2,
740     ArchDefine440   = 1 << 3,
741     ArchDefine603   = 1 << 4,
742     ArchDefine604   = 1 << 5,
743     ArchDefinePwr4  = 1 << 6,
744     ArchDefinePwr5  = 1 << 7,
745     ArchDefinePwr5x = 1 << 8,
746     ArchDefinePwr6  = 1 << 9,
747     ArchDefinePwr6x = 1 << 10,
748     ArchDefinePwr7  = 1 << 11,
749     ArchDefinePwr8  = 1 << 12,
750     ArchDefineA2    = 1 << 13,
751     ArchDefineA2q   = 1 << 14
752   } ArchDefineTypes;
753 
754   // Note: GCC recognizes the following additional cpus:
755   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
756   //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
757   //  titan, rs64.
758   bool setCPU(const std::string &Name) override {
759     bool CPUKnown = llvm::StringSwitch<bool>(Name)
760       .Case("generic", true)
761       .Case("440", true)
762       .Case("450", true)
763       .Case("601", true)
764       .Case("602", true)
765       .Case("603", true)
766       .Case("603e", true)
767       .Case("603ev", true)
768       .Case("604", true)
769       .Case("604e", true)
770       .Case("620", true)
771       .Case("630", true)
772       .Case("g3", true)
773       .Case("7400", true)
774       .Case("g4", true)
775       .Case("7450", true)
776       .Case("g4+", true)
777       .Case("750", true)
778       .Case("970", true)
779       .Case("g5", true)
780       .Case("a2", true)
781       .Case("a2q", true)
782       .Case("e500mc", true)
783       .Case("e5500", true)
784       .Case("power3", true)
785       .Case("pwr3", true)
786       .Case("power4", true)
787       .Case("pwr4", true)
788       .Case("power5", true)
789       .Case("pwr5", true)
790       .Case("power5x", true)
791       .Case("pwr5x", true)
792       .Case("power6", true)
793       .Case("pwr6", true)
794       .Case("power6x", true)
795       .Case("pwr6x", true)
796       .Case("power7", true)
797       .Case("pwr7", true)
798       .Case("power8", true)
799       .Case("pwr8", true)
800       .Case("powerpc", true)
801       .Case("ppc", true)
802       .Case("powerpc64", true)
803       .Case("ppc64", true)
804       .Case("powerpc64le", true)
805       .Case("ppc64le", true)
806       .Default(false);
807 
808     if (CPUKnown)
809       CPU = Name;
810 
811     return CPUKnown;
812   }
813 
814 
815   StringRef getABI() const override { return ABI; }
816 
817   void getTargetBuiltins(const Builtin::Info *&Records,
818                          unsigned &NumRecords) const override {
819     Records = BuiltinInfo;
820     NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
821   }
822 
823   bool isCLZForZeroUndef() const override { return false; }
824 
825   void getTargetDefines(const LangOptions &Opts,
826                         MacroBuilder &Builder) const override;
827 
828   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
829 
830   bool handleTargetFeatures(std::vector<std::string> &Features,
831                             DiagnosticsEngine &Diags) override;
832   bool hasFeature(StringRef Feature) const override;
833 
834   void getGCCRegNames(const char * const *&Names,
835                       unsigned &NumNames) const override;
836   void getGCCRegAliases(const GCCRegAlias *&Aliases,
837                         unsigned &NumAliases) const override;
838   bool validateAsmConstraint(const char *&Name,
839                              TargetInfo::ConstraintInfo &Info) const override {
840     switch (*Name) {
841     default: return false;
842     case 'O': // Zero
843       break;
844     case 'b': // Base register
845     case 'f': // Floating point register
846       Info.setAllowsRegister();
847       break;
848     // FIXME: The following are added to allow parsing.
849     // I just took a guess at what the actions should be.
850     // Also, is more specific checking needed?  I.e. specific registers?
851     case 'd': // Floating point register (containing 64-bit value)
852     case 'v': // Altivec vector register
853       Info.setAllowsRegister();
854       break;
855     case 'w':
856       switch (Name[1]) {
857         case 'd':// VSX vector register to hold vector double data
858         case 'f':// VSX vector register to hold vector float data
859         case 's':// VSX vector register to hold scalar float data
860         case 'a':// Any VSX register
861         case 'c':// An individual CR bit
862           break;
863         default:
864           return false;
865       }
866       Info.setAllowsRegister();
867       Name++; // Skip over 'w'.
868       break;
869     case 'h': // `MQ', `CTR', or `LINK' register
870     case 'q': // `MQ' register
871     case 'c': // `CTR' register
872     case 'l': // `LINK' register
873     case 'x': // `CR' register (condition register) number 0
874     case 'y': // `CR' register (condition register)
875     case 'z': // `XER[CA]' carry bit (part of the XER register)
876       Info.setAllowsRegister();
877       break;
878     case 'I': // Signed 16-bit constant
879     case 'J': // Unsigned 16-bit constant shifted left 16 bits
880               //  (use `L' instead for SImode constants)
881     case 'K': // Unsigned 16-bit constant
882     case 'L': // Signed 16-bit constant shifted left 16 bits
883     case 'M': // Constant larger than 31
884     case 'N': // Exact power of 2
885     case 'P': // Constant whose negation is a signed 16-bit constant
886     case 'G': // Floating point constant that can be loaded into a
887               // register with one instruction per word
888     case 'H': // Integer/Floating point constant that can be loaded
889               // into a register using three instructions
890       break;
891     case 'm': // Memory operand. Note that on PowerPC targets, m can
892               // include addresses that update the base register. It
893               // is therefore only safe to use `m' in an asm statement
894               // if that asm statement accesses the operand exactly once.
895               // The asm statement must also use `%U<opno>' as a
896               // placeholder for the "update" flag in the corresponding
897               // load or store instruction. For example:
898               // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
899               // is correct but:
900               // asm ("st %1,%0" : "=m" (mem) : "r" (val));
901               // is not. Use es rather than m if you don't want the base
902               // register to be updated.
903     case 'e':
904       if (Name[1] != 's')
905           return false;
906               // es: A "stable" memory operand; that is, one which does not
907               // include any automodification of the base register. Unlike
908               // `m', this constraint can be used in asm statements that
909               // might access the operand several times, or that might not
910               // access it at all.
911       Info.setAllowsMemory();
912       Name++; // Skip over 'e'.
913       break;
914     case 'Q': // Memory operand that is an offset from a register (it is
915               // usually better to use `m' or `es' in asm statements)
916     case 'Z': // Memory operand that is an indexed or indirect from a
917               // register (it is usually better to use `m' or `es' in
918               // asm statements)
919       Info.setAllowsMemory();
920       Info.setAllowsRegister();
921       break;
922     case 'R': // AIX TOC entry
923     case 'a': // Address operand that is an indexed or indirect from a
924               // register (`p' is preferable for asm statements)
925     case 'S': // Constant suitable as a 64-bit mask operand
926     case 'T': // Constant suitable as a 32-bit mask operand
927     case 'U': // System V Release 4 small data area reference
928     case 't': // AND masks that can be performed by two rldic{l, r}
929               // instructions
930     case 'W': // Vector constant that does not require memory
931     case 'j': // Vector constant that is all zeros.
932       break;
933     // End FIXME.
934     }
935     return true;
936   }
937   std::string convertConstraint(const char *&Constraint) const override {
938     std::string R;
939     switch (*Constraint) {
940     case 'e':
941     case 'w':
942       // Two-character constraint; add "^" hint for later parsing.
943       R = std::string("^") + std::string(Constraint, 2);
944       Constraint++;
945       break;
946     default:
947       return TargetInfo::convertConstraint(Constraint);
948     }
949     return R;
950   }
951   const char *getClobbers() const override {
952     return "";
953   }
954   int getEHDataRegisterNumber(unsigned RegNo) const override {
955     if (RegNo == 0) return 3;
956     if (RegNo == 1) return 4;
957     return -1;
958   }
959 };
960 
961 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
962 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
963 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
964                                               ALL_LANGUAGES },
965 #include "clang/Basic/BuiltinsPPC.def"
966 };
967 
968 /// handleTargetFeatures - Perform initialization based on the user
969 /// configured set of features.
970 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
971                                          DiagnosticsEngine &Diags) {
972   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
973     // Ignore disabled features.
974     if (Features[i][0] == '-')
975       continue;
976 
977     StringRef Feature = StringRef(Features[i]).substr(1);
978 
979     if (Feature == "vsx") {
980       HasVSX = true;
981       continue;
982     }
983 
984     if (Feature == "power8-vector") {
985       HasP8Vector = true;
986       continue;
987     }
988 
989     // TODO: Finish this list and add an assert that we've handled them
990     // all.
991   }
992 
993   return true;
994 }
995 
996 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
997 /// #defines that are not tied to a specific subtarget.
998 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
999                                      MacroBuilder &Builder) const {
1000   // Target identification.
1001   Builder.defineMacro("__ppc__");
1002   Builder.defineMacro("__PPC__");
1003   Builder.defineMacro("_ARCH_PPC");
1004   Builder.defineMacro("__powerpc__");
1005   Builder.defineMacro("__POWERPC__");
1006   if (PointerWidth == 64) {
1007     Builder.defineMacro("_ARCH_PPC64");
1008     Builder.defineMacro("__powerpc64__");
1009     Builder.defineMacro("__ppc64__");
1010     Builder.defineMacro("__PPC64__");
1011   }
1012 
1013   // Target properties.
1014   if (getTriple().getArch() == llvm::Triple::ppc64le) {
1015     Builder.defineMacro("_LITTLE_ENDIAN");
1016   } else {
1017     if (getTriple().getOS() != llvm::Triple::NetBSD &&
1018         getTriple().getOS() != llvm::Triple::OpenBSD)
1019       Builder.defineMacro("_BIG_ENDIAN");
1020   }
1021 
1022   // ABI options.
1023   if (ABI == "elfv1")
1024     Builder.defineMacro("_CALL_ELF", "1");
1025   if (ABI == "elfv2")
1026     Builder.defineMacro("_CALL_ELF", "2");
1027 
1028   // Subtarget options.
1029   Builder.defineMacro("__NATURAL_ALIGNMENT__");
1030   Builder.defineMacro("__REGISTER_PREFIX__", "");
1031 
1032   // FIXME: Should be controlled by command line option.
1033   if (LongDoubleWidth == 128)
1034     Builder.defineMacro("__LONG_DOUBLE_128__");
1035 
1036   if (Opts.AltiVec) {
1037     Builder.defineMacro("__VEC__", "10206");
1038     Builder.defineMacro("__ALTIVEC__");
1039   }
1040 
1041   // CPU identification.
1042   ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1043     .Case("440",   ArchDefineName)
1044     .Case("450",   ArchDefineName | ArchDefine440)
1045     .Case("601",   ArchDefineName)
1046     .Case("602",   ArchDefineName | ArchDefinePpcgr)
1047     .Case("603",   ArchDefineName | ArchDefinePpcgr)
1048     .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1049     .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1050     .Case("604",   ArchDefineName | ArchDefinePpcgr)
1051     .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1052     .Case("620",   ArchDefineName | ArchDefinePpcgr)
1053     .Case("630",   ArchDefineName | ArchDefinePpcgr)
1054     .Case("7400",  ArchDefineName | ArchDefinePpcgr)
1055     .Case("7450",  ArchDefineName | ArchDefinePpcgr)
1056     .Case("750",   ArchDefineName | ArchDefinePpcgr)
1057     .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1058                      | ArchDefinePpcsq)
1059     .Case("a2",    ArchDefineA2)
1060     .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1061     .Case("pwr3",  ArchDefinePpcgr)
1062     .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1063     .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1064                      | ArchDefinePpcsq)
1065     .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1066                      | ArchDefinePpcgr | ArchDefinePpcsq)
1067     .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1068                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1069     .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1070                      | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1071                      | ArchDefinePpcsq)
1072     .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1073                      | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1074                      | ArchDefinePpcgr | ArchDefinePpcsq)
1075     .Case("pwr8",  ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1076                      | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1077                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1078     .Case("power3",  ArchDefinePpcgr)
1079     .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1080     .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1081                        | ArchDefinePpcsq)
1082     .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1083                        | ArchDefinePpcgr | ArchDefinePpcsq)
1084     .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1085                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1086     .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1087                        | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1088                        | ArchDefinePpcsq)
1089     .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1090                        | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1091                        | ArchDefinePpcgr | ArchDefinePpcsq)
1092     .Case("power8",  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1093                        | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1094                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1095     .Default(ArchDefineNone);
1096 
1097   if (defs & ArchDefineName)
1098     Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1099   if (defs & ArchDefinePpcgr)
1100     Builder.defineMacro("_ARCH_PPCGR");
1101   if (defs & ArchDefinePpcsq)
1102     Builder.defineMacro("_ARCH_PPCSQ");
1103   if (defs & ArchDefine440)
1104     Builder.defineMacro("_ARCH_440");
1105   if (defs & ArchDefine603)
1106     Builder.defineMacro("_ARCH_603");
1107   if (defs & ArchDefine604)
1108     Builder.defineMacro("_ARCH_604");
1109   if (defs & ArchDefinePwr4)
1110     Builder.defineMacro("_ARCH_PWR4");
1111   if (defs & ArchDefinePwr5)
1112     Builder.defineMacro("_ARCH_PWR5");
1113   if (defs & ArchDefinePwr5x)
1114     Builder.defineMacro("_ARCH_PWR5X");
1115   if (defs & ArchDefinePwr6)
1116     Builder.defineMacro("_ARCH_PWR6");
1117   if (defs & ArchDefinePwr6x)
1118     Builder.defineMacro("_ARCH_PWR6X");
1119   if (defs & ArchDefinePwr7)
1120     Builder.defineMacro("_ARCH_PWR7");
1121   if (defs & ArchDefinePwr8)
1122     Builder.defineMacro("_ARCH_PWR8");
1123   if (defs & ArchDefineA2)
1124     Builder.defineMacro("_ARCH_A2");
1125   if (defs & ArchDefineA2q) {
1126     Builder.defineMacro("_ARCH_A2Q");
1127     Builder.defineMacro("_ARCH_QP");
1128   }
1129 
1130   if (getTriple().getVendor() == llvm::Triple::BGQ) {
1131     Builder.defineMacro("__bg__");
1132     Builder.defineMacro("__THW_BLUEGENE__");
1133     Builder.defineMacro("__bgq__");
1134     Builder.defineMacro("__TOS_BGQ__");
1135   }
1136 
1137   if (HasVSX)
1138     Builder.defineMacro("__VSX__");
1139   if (HasP8Vector)
1140     Builder.defineMacro("__POWER8_VECTOR__");
1141 
1142   // FIXME: The following are not yet generated here by Clang, but are
1143   //        generated by GCC:
1144   //
1145   //   _SOFT_FLOAT_
1146   //   __RECIP_PRECISION__
1147   //   __APPLE_ALTIVEC__
1148   //   __RECIP__
1149   //   __RECIPF__
1150   //   __RSQRTE__
1151   //   __RSQRTEF__
1152   //   _SOFT_DOUBLE_
1153   //   __NO_LWSYNC__
1154   //   __HAVE_BSWAP__
1155   //   __LONGDOUBLE128
1156   //   __CMODEL_MEDIUM__
1157   //   __CMODEL_LARGE__
1158   //   _CALL_SYSV
1159   //   _CALL_DARWIN
1160   //   __NO_FPRS__
1161 }
1162 
1163 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1164   Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1165     .Case("7400", true)
1166     .Case("g4", true)
1167     .Case("7450", true)
1168     .Case("g4+", true)
1169     .Case("970", true)
1170     .Case("g5", true)
1171     .Case("pwr6", true)
1172     .Case("pwr7", true)
1173     .Case("pwr8", true)
1174     .Case("ppc64", true)
1175     .Case("ppc64le", true)
1176     .Default(false);
1177 
1178   Features["qpx"] = (CPU == "a2q");
1179 }
1180 
1181 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1182   return llvm::StringSwitch<bool>(Feature)
1183     .Case("powerpc", true)
1184     .Case("vsx", HasVSX)
1185     .Case("power8-vector", HasP8Vector)
1186     .Default(false);
1187 }
1188 
1189 const char * const PPCTargetInfo::GCCRegNames[] = {
1190   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1191   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1192   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1193   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1194   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1195   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1196   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1197   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1198   "mq", "lr", "ctr", "ap",
1199   "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1200   "xer",
1201   "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1202   "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1203   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1204   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1205   "vrsave", "vscr",
1206   "spe_acc", "spefscr",
1207   "sfp"
1208 };
1209 
1210 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1211                                    unsigned &NumNames) const {
1212   Names = GCCRegNames;
1213   NumNames = llvm::array_lengthof(GCCRegNames);
1214 }
1215 
1216 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1217   // While some of these aliases do map to different registers
1218   // they still share the same register name.
1219   { { "0" }, "r0" },
1220   { { "1"}, "r1" },
1221   { { "2" }, "r2" },
1222   { { "3" }, "r3" },
1223   { { "4" }, "r4" },
1224   { { "5" }, "r5" },
1225   { { "6" }, "r6" },
1226   { { "7" }, "r7" },
1227   { { "8" }, "r8" },
1228   { { "9" }, "r9" },
1229   { { "10" }, "r10" },
1230   { { "11" }, "r11" },
1231   { { "12" }, "r12" },
1232   { { "13" }, "r13" },
1233   { { "14" }, "r14" },
1234   { { "15" }, "r15" },
1235   { { "16" }, "r16" },
1236   { { "17" }, "r17" },
1237   { { "18" }, "r18" },
1238   { { "19" }, "r19" },
1239   { { "20" }, "r20" },
1240   { { "21" }, "r21" },
1241   { { "22" }, "r22" },
1242   { { "23" }, "r23" },
1243   { { "24" }, "r24" },
1244   { { "25" }, "r25" },
1245   { { "26" }, "r26" },
1246   { { "27" }, "r27" },
1247   { { "28" }, "r28" },
1248   { { "29" }, "r29" },
1249   { { "30" }, "r30" },
1250   { { "31" }, "r31" },
1251   { { "fr0" }, "f0" },
1252   { { "fr1" }, "f1" },
1253   { { "fr2" }, "f2" },
1254   { { "fr3" }, "f3" },
1255   { { "fr4" }, "f4" },
1256   { { "fr5" }, "f5" },
1257   { { "fr6" }, "f6" },
1258   { { "fr7" }, "f7" },
1259   { { "fr8" }, "f8" },
1260   { { "fr9" }, "f9" },
1261   { { "fr10" }, "f10" },
1262   { { "fr11" }, "f11" },
1263   { { "fr12" }, "f12" },
1264   { { "fr13" }, "f13" },
1265   { { "fr14" }, "f14" },
1266   { { "fr15" }, "f15" },
1267   { { "fr16" }, "f16" },
1268   { { "fr17" }, "f17" },
1269   { { "fr18" }, "f18" },
1270   { { "fr19" }, "f19" },
1271   { { "fr20" }, "f20" },
1272   { { "fr21" }, "f21" },
1273   { { "fr22" }, "f22" },
1274   { { "fr23" }, "f23" },
1275   { { "fr24" }, "f24" },
1276   { { "fr25" }, "f25" },
1277   { { "fr26" }, "f26" },
1278   { { "fr27" }, "f27" },
1279   { { "fr28" }, "f28" },
1280   { { "fr29" }, "f29" },
1281   { { "fr30" }, "f30" },
1282   { { "fr31" }, "f31" },
1283   { { "cc" }, "cr0" },
1284 };
1285 
1286 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1287                                      unsigned &NumAliases) const {
1288   Aliases = GCCRegAliases;
1289   NumAliases = llvm::array_lengthof(GCCRegAliases);
1290 }
1291 } // end anonymous namespace.
1292 
1293 namespace {
1294 class PPC32TargetInfo : public PPCTargetInfo {
1295 public:
1296   PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1297     DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1298 
1299     switch (getTriple().getOS()) {
1300     case llvm::Triple::Linux:
1301     case llvm::Triple::FreeBSD:
1302     case llvm::Triple::NetBSD:
1303       SizeType = UnsignedInt;
1304       PtrDiffType = SignedInt;
1305       IntPtrType = SignedInt;
1306       break;
1307     default:
1308       break;
1309     }
1310 
1311     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1312       LongDoubleWidth = LongDoubleAlign = 64;
1313       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1314     }
1315 
1316     // PPC32 supports atomics up to 4 bytes.
1317     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1318   }
1319 
1320   BuiltinVaListKind getBuiltinVaListKind() const override {
1321     // This is the ELF definition, and is overridden by the Darwin sub-target
1322     return TargetInfo::PowerABIBuiltinVaList;
1323   }
1324 };
1325 } // end anonymous namespace.
1326 
1327 // Note: ABI differences may eventually require us to have a separate
1328 // TargetInfo for little endian.
1329 namespace {
1330 class PPC64TargetInfo : public PPCTargetInfo {
1331 public:
1332   PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1333     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1334     IntMaxType = SignedLong;
1335     Int64Type = SignedLong;
1336 
1337     if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1338       DescriptionString = "e-m:e-i64:64-n32:64";
1339       ABI = "elfv2";
1340     } else {
1341       DescriptionString = "E-m:e-i64:64-n32:64";
1342       ABI = "elfv1";
1343     }
1344 
1345     switch (getTriple().getOS()) {
1346     case llvm::Triple::FreeBSD:
1347       LongDoubleWidth = LongDoubleAlign = 64;
1348       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1349       break;
1350     case llvm::Triple::NetBSD:
1351       IntMaxType = SignedLongLong;
1352       Int64Type = SignedLongLong;
1353       break;
1354     default:
1355       break;
1356     }
1357 
1358     // PPC64 supports atomics up to 8 bytes.
1359     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1360   }
1361   BuiltinVaListKind getBuiltinVaListKind() const override {
1362     return TargetInfo::CharPtrBuiltinVaList;
1363   }
1364   // PPC64 Linux-specifc ABI options.
1365   bool setABI(const std::string &Name) override {
1366     if (Name == "elfv1" || Name == "elfv2") {
1367       ABI = Name;
1368       return true;
1369     }
1370     return false;
1371   }
1372 };
1373 } // end anonymous namespace.
1374 
1375 
1376 namespace {
1377 class DarwinPPC32TargetInfo :
1378   public DarwinTargetInfo<PPC32TargetInfo> {
1379 public:
1380   DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1381       : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1382     HasAlignMac68kSupport = true;
1383     BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1384     PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1385     LongLongAlign = 32;
1386     SuitableAlign = 128;
1387     DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1388   }
1389   BuiltinVaListKind getBuiltinVaListKind() const override {
1390     return TargetInfo::CharPtrBuiltinVaList;
1391   }
1392 };
1393 
1394 class DarwinPPC64TargetInfo :
1395   public DarwinTargetInfo<PPC64TargetInfo> {
1396 public:
1397   DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1398       : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1399     HasAlignMac68kSupport = true;
1400     SuitableAlign = 128;
1401     DescriptionString = "E-m:o-i64:64-n32:64";
1402   }
1403 };
1404 } // end anonymous namespace.
1405 
1406 namespace {
1407   static const unsigned NVPTXAddrSpaceMap[] = {
1408     1,    // opencl_global
1409     3,    // opencl_local
1410     4,    // opencl_constant
1411     // FIXME: generic has to be added to the target
1412     0,    // opencl_generic
1413     1,    // cuda_device
1414     4,    // cuda_constant
1415     3,    // cuda_shared
1416   };
1417   class NVPTXTargetInfo : public TargetInfo {
1418     static const char * const GCCRegNames[];
1419     static const Builtin::Info BuiltinInfo[];
1420 
1421   // The GPU profiles supported by the NVPTX backend
1422   enum GPUKind {
1423     GK_NONE,
1424     GK_SM20,
1425     GK_SM21,
1426     GK_SM30,
1427     GK_SM35,
1428   } GPU;
1429 
1430   public:
1431     NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1432       BigEndian = false;
1433       TLSSupported = false;
1434       LongWidth = LongAlign = 64;
1435       AddrSpaceMap = &NVPTXAddrSpaceMap;
1436       UseAddrSpaceMapMangling = true;
1437       // Define available target features
1438       // These must be defined in sorted order!
1439       NoAsmVariants = true;
1440       // Set the default GPU to sm20
1441       GPU = GK_SM20;
1442     }
1443     void getTargetDefines(const LangOptions &Opts,
1444                           MacroBuilder &Builder) const override {
1445       Builder.defineMacro("__PTX__");
1446       Builder.defineMacro("__NVPTX__");
1447       if (Opts.CUDAIsDevice) {
1448         // Set __CUDA_ARCH__ for the GPU specified.
1449         std::string CUDAArchCode;
1450         switch (GPU) {
1451         case GK_SM20:
1452           CUDAArchCode = "200";
1453           break;
1454         case GK_SM21:
1455           CUDAArchCode = "210";
1456           break;
1457         case GK_SM30:
1458           CUDAArchCode = "300";
1459           break;
1460         case GK_SM35:
1461           CUDAArchCode = "350";
1462           break;
1463         default:
1464           llvm_unreachable("Unhandled target CPU");
1465         }
1466         Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1467       }
1468     }
1469     void getTargetBuiltins(const Builtin::Info *&Records,
1470                            unsigned &NumRecords) const override {
1471       Records = BuiltinInfo;
1472       NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1473     }
1474     bool hasFeature(StringRef Feature) const override {
1475       return Feature == "ptx" || Feature == "nvptx";
1476     }
1477 
1478     void getGCCRegNames(const char * const *&Names,
1479                         unsigned &NumNames) const override;
1480     void getGCCRegAliases(const GCCRegAlias *&Aliases,
1481                                   unsigned &NumAliases) const override {
1482       // No aliases.
1483       Aliases = nullptr;
1484       NumAliases = 0;
1485     }
1486     bool
1487     validateAsmConstraint(const char *&Name,
1488                           TargetInfo::ConstraintInfo &Info) const override {
1489       switch (*Name) {
1490       default: return false;
1491       case 'c':
1492       case 'h':
1493       case 'r':
1494       case 'l':
1495       case 'f':
1496       case 'd':
1497         Info.setAllowsRegister();
1498         return true;
1499       }
1500     }
1501     const char *getClobbers() const override {
1502       // FIXME: Is this really right?
1503       return "";
1504     }
1505     BuiltinVaListKind getBuiltinVaListKind() const override {
1506       // FIXME: implement
1507       return TargetInfo::CharPtrBuiltinVaList;
1508     }
1509     bool setCPU(const std::string &Name) override {
1510       GPU = llvm::StringSwitch<GPUKind>(Name)
1511                 .Case("sm_20", GK_SM20)
1512                 .Case("sm_21", GK_SM21)
1513                 .Case("sm_30", GK_SM30)
1514                 .Case("sm_35", GK_SM35)
1515                 .Default(GK_NONE);
1516 
1517       return GPU != GK_NONE;
1518     }
1519   };
1520 
1521   const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1522 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1523 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1524                                               ALL_LANGUAGES },
1525 #include "clang/Basic/BuiltinsNVPTX.def"
1526   };
1527 
1528   const char * const NVPTXTargetInfo::GCCRegNames[] = {
1529     "r0"
1530   };
1531 
1532   void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1533                                      unsigned &NumNames) const {
1534     Names = GCCRegNames;
1535     NumNames = llvm::array_lengthof(GCCRegNames);
1536   }
1537 
1538   class NVPTX32TargetInfo : public NVPTXTargetInfo {
1539   public:
1540     NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1541       PointerWidth = PointerAlign = 32;
1542       SizeType     = PtrDiffType = TargetInfo::UnsignedInt;
1543       IntPtrType = TargetInfo::SignedInt;
1544       DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1545   }
1546   };
1547 
1548   class NVPTX64TargetInfo : public NVPTXTargetInfo {
1549   public:
1550     NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1551       PointerWidth = PointerAlign = 64;
1552       SizeType     = PtrDiffType = TargetInfo::UnsignedLongLong;
1553       IntPtrType = TargetInfo::SignedLongLong;
1554       DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1555   }
1556   };
1557 }
1558 
1559 namespace {
1560 
1561 static const unsigned R600AddrSpaceMap[] = {
1562   1,    // opencl_global
1563   3,    // opencl_local
1564   2,    // opencl_constant
1565   4,    // opencl_generic
1566   1,    // cuda_device
1567   2,    // cuda_constant
1568   3     // cuda_shared
1569 };
1570 
1571 // If you edit the description strings, make sure you update
1572 // getPointerWidthV().
1573 
1574 static const char *DescriptionStringR600 =
1575   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1576   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1577 
1578 static const char *DescriptionStringR600DoubleOps =
1579   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1580   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1581 
1582 static const char *DescriptionStringSI =
1583   "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1584   "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1585   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1586 
1587 class R600TargetInfo : public TargetInfo {
1588   static const Builtin::Info BuiltinInfo[];
1589 
1590   /// \brief The GPU profiles supported by the R600 target.
1591   enum GPUKind {
1592     GK_NONE,
1593     GK_R600,
1594     GK_R600_DOUBLE_OPS,
1595     GK_R700,
1596     GK_R700_DOUBLE_OPS,
1597     GK_EVERGREEN,
1598     GK_EVERGREEN_DOUBLE_OPS,
1599     GK_NORTHERN_ISLANDS,
1600     GK_CAYMAN,
1601     GK_SOUTHERN_ISLANDS,
1602     GK_SEA_ISLANDS
1603   } GPU;
1604 
1605 public:
1606   R600TargetInfo(const llvm::Triple &Triple)
1607       : TargetInfo(Triple) {
1608 
1609     if (Triple.getArch() == llvm::Triple::amdgcn) {
1610       DescriptionString = DescriptionStringSI;
1611       GPU = GK_SOUTHERN_ISLANDS;
1612     } else {
1613       DescriptionString = DescriptionStringR600;
1614       GPU = GK_R600;
1615     }
1616     AddrSpaceMap = &R600AddrSpaceMap;
1617     UseAddrSpaceMapMangling = true;
1618   }
1619 
1620   uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1621     if (GPU <= GK_CAYMAN)
1622       return 32;
1623 
1624     switch(AddrSpace) {
1625       default:
1626         return 64;
1627       case 0:
1628       case 3:
1629       case 5:
1630         return 32;
1631     }
1632   }
1633 
1634   const char * getClobbers() const override {
1635     return "";
1636   }
1637 
1638   void getGCCRegNames(const char * const *&Names,
1639                       unsigned &numNames) const override {
1640     Names = nullptr;
1641     numNames = 0;
1642   }
1643 
1644   void getGCCRegAliases(const GCCRegAlias *&Aliases,
1645                         unsigned &NumAliases) const override {
1646     Aliases = nullptr;
1647     NumAliases = 0;
1648   }
1649 
1650   bool validateAsmConstraint(const char *&Name,
1651                              TargetInfo::ConstraintInfo &info) const override {
1652     return true;
1653   }
1654 
1655   void getTargetBuiltins(const Builtin::Info *&Records,
1656                          unsigned &NumRecords) const override {
1657     Records = BuiltinInfo;
1658     NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
1659   }
1660 
1661   void getTargetDefines(const LangOptions &Opts,
1662                         MacroBuilder &Builder) const override {
1663     Builder.defineMacro("__R600__");
1664     if (GPU >= GK_SOUTHERN_ISLANDS && Opts.OpenCL)
1665       Builder.defineMacro("cl_khr_fp64");
1666   }
1667 
1668   BuiltinVaListKind getBuiltinVaListKind() const override {
1669     return TargetInfo::CharPtrBuiltinVaList;
1670   }
1671 
1672   bool setCPU(const std::string &Name) override {
1673     GPU = llvm::StringSwitch<GPUKind>(Name)
1674       .Case("r600" ,    GK_R600)
1675       .Case("rv610",    GK_R600)
1676       .Case("rv620",    GK_R600)
1677       .Case("rv630",    GK_R600)
1678       .Case("rv635",    GK_R600)
1679       .Case("rs780",    GK_R600)
1680       .Case("rs880",    GK_R600)
1681       .Case("rv670",    GK_R600_DOUBLE_OPS)
1682       .Case("rv710",    GK_R700)
1683       .Case("rv730",    GK_R700)
1684       .Case("rv740",    GK_R700_DOUBLE_OPS)
1685       .Case("rv770",    GK_R700_DOUBLE_OPS)
1686       .Case("palm",     GK_EVERGREEN)
1687       .Case("cedar",    GK_EVERGREEN)
1688       .Case("sumo",     GK_EVERGREEN)
1689       .Case("sumo2",    GK_EVERGREEN)
1690       .Case("redwood",  GK_EVERGREEN)
1691       .Case("juniper",  GK_EVERGREEN)
1692       .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1693       .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1694       .Case("barts",    GK_NORTHERN_ISLANDS)
1695       .Case("turks",    GK_NORTHERN_ISLANDS)
1696       .Case("caicos",   GK_NORTHERN_ISLANDS)
1697       .Case("cayman",   GK_CAYMAN)
1698       .Case("aruba",    GK_CAYMAN)
1699       .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1700       .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1701       .Case("verde",    GK_SOUTHERN_ISLANDS)
1702       .Case("oland",    GK_SOUTHERN_ISLANDS)
1703       .Case("hainan",   GK_SOUTHERN_ISLANDS)
1704       .Case("bonaire",  GK_SEA_ISLANDS)
1705       .Case("kabini",   GK_SEA_ISLANDS)
1706       .Case("kaveri",   GK_SEA_ISLANDS)
1707       .Case("hawaii",   GK_SEA_ISLANDS)
1708       .Case("mullins",  GK_SEA_ISLANDS)
1709       .Default(GK_NONE);
1710 
1711     if (GPU == GK_NONE) {
1712       return false;
1713     }
1714 
1715     // Set the correct data layout
1716     switch (GPU) {
1717     case GK_NONE:
1718     case GK_R600:
1719     case GK_R700:
1720     case GK_EVERGREEN:
1721     case GK_NORTHERN_ISLANDS:
1722       DescriptionString = DescriptionStringR600;
1723       break;
1724     case GK_R600_DOUBLE_OPS:
1725     case GK_R700_DOUBLE_OPS:
1726     case GK_EVERGREEN_DOUBLE_OPS:
1727     case GK_CAYMAN:
1728       DescriptionString = DescriptionStringR600DoubleOps;
1729       break;
1730     case GK_SOUTHERN_ISLANDS:
1731     case GK_SEA_ISLANDS:
1732       DescriptionString = DescriptionStringSI;
1733       break;
1734     }
1735 
1736     return true;
1737   }
1738 };
1739 
1740 const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
1741 #define BUILTIN(ID, TYPE, ATTRS)                \
1742   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1743 #include "clang/Basic/BuiltinsR600.def"
1744 };
1745 
1746 } // end anonymous namespace
1747 
1748 namespace {
1749 // Namespace for x86 abstract base class
1750 const Builtin::Info BuiltinInfo[] = {
1751 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1752 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1753                                               ALL_LANGUAGES },
1754 #include "clang/Basic/BuiltinsX86.def"
1755 };
1756 
1757 static const char* const GCCRegNames[] = {
1758   "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1759   "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1760   "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1761   "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1762   "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1763   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1764   "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1765   "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1766   "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1767 };
1768 
1769 const TargetInfo::AddlRegName AddlRegNames[] = {
1770   { { "al", "ah", "eax", "rax" }, 0 },
1771   { { "bl", "bh", "ebx", "rbx" }, 3 },
1772   { { "cl", "ch", "ecx", "rcx" }, 2 },
1773   { { "dl", "dh", "edx", "rdx" }, 1 },
1774   { { "esi", "rsi" }, 4 },
1775   { { "edi", "rdi" }, 5 },
1776   { { "esp", "rsp" }, 7 },
1777   { { "ebp", "rbp" }, 6 },
1778 };
1779 
1780 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1781 // most of the implementation can be shared.
1782 class X86TargetInfo : public TargetInfo {
1783   enum X86SSEEnum {
1784     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1785   } SSELevel;
1786   enum MMX3DNowEnum {
1787     NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1788   } MMX3DNowLevel;
1789   enum XOPEnum {
1790     NoXOP,
1791     SSE4A,
1792     FMA4,
1793     XOP
1794   } XOPLevel;
1795 
1796   bool HasAES;
1797   bool HasPCLMUL;
1798   bool HasLZCNT;
1799   bool HasRDRND;
1800   bool HasFSGSBASE;
1801   bool HasBMI;
1802   bool HasBMI2;
1803   bool HasPOPCNT;
1804   bool HasRTM;
1805   bool HasPRFCHW;
1806   bool HasRDSEED;
1807   bool HasADX;
1808   bool HasTBM;
1809   bool HasFMA;
1810   bool HasF16C;
1811   bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
1812       HasAVX512VL;
1813   bool HasSHA;
1814   bool HasCX16;
1815 
1816   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1817   ///
1818   /// Each enumeration represents a particular CPU supported by Clang. These
1819   /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1820   enum CPUKind {
1821     CK_Generic,
1822 
1823     /// \name i386
1824     /// i386-generation processors.
1825     //@{
1826     CK_i386,
1827     //@}
1828 
1829     /// \name i486
1830     /// i486-generation processors.
1831     //@{
1832     CK_i486,
1833     CK_WinChipC6,
1834     CK_WinChip2,
1835     CK_C3,
1836     //@}
1837 
1838     /// \name i586
1839     /// i586-generation processors, P5 microarchitecture based.
1840     //@{
1841     CK_i586,
1842     CK_Pentium,
1843     CK_PentiumMMX,
1844     //@}
1845 
1846     /// \name i686
1847     /// i686-generation processors, P6 / Pentium M microarchitecture based.
1848     //@{
1849     CK_i686,
1850     CK_PentiumPro,
1851     CK_Pentium2,
1852     CK_Pentium3,
1853     CK_Pentium3M,
1854     CK_PentiumM,
1855     CK_C3_2,
1856 
1857     /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1858     /// Clang however has some logic to suport this.
1859     // FIXME: Warn, deprecate, and potentially remove this.
1860     CK_Yonah,
1861     //@}
1862 
1863     /// \name Netburst
1864     /// Netburst microarchitecture based processors.
1865     //@{
1866     CK_Pentium4,
1867     CK_Pentium4M,
1868     CK_Prescott,
1869     CK_Nocona,
1870     //@}
1871 
1872     /// \name Core
1873     /// Core microarchitecture based processors.
1874     //@{
1875     CK_Core2,
1876 
1877     /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1878     /// codename which GCC no longer accepts as an option to -march, but Clang
1879     /// has some logic for recognizing it.
1880     // FIXME: Warn, deprecate, and potentially remove this.
1881     CK_Penryn,
1882     //@}
1883 
1884     /// \name Atom
1885     /// Atom processors
1886     //@{
1887     CK_Bonnell,
1888     CK_Silvermont,
1889     //@}
1890 
1891     /// \name Nehalem
1892     /// Nehalem microarchitecture based processors.
1893     CK_Nehalem,
1894 
1895     /// \name Westmere
1896     /// Westmere microarchitecture based processors.
1897     CK_Westmere,
1898 
1899     /// \name Sandy Bridge
1900     /// Sandy Bridge microarchitecture based processors.
1901     CK_SandyBridge,
1902 
1903     /// \name Ivy Bridge
1904     /// Ivy Bridge microarchitecture based processors.
1905     CK_IvyBridge,
1906 
1907     /// \name Haswell
1908     /// Haswell microarchitecture based processors.
1909     CK_Haswell,
1910 
1911     /// \name Broadwell
1912     /// Broadwell microarchitecture based processors.
1913     CK_Broadwell,
1914 
1915     /// \name Skylake
1916     /// Skylake microarchitecture based processors.
1917     CK_Skylake,
1918 
1919     /// \name Knights Landing
1920     /// Knights Landing processor.
1921     CK_KNL,
1922 
1923     /// \name K6
1924     /// K6 architecture processors.
1925     //@{
1926     CK_K6,
1927     CK_K6_2,
1928     CK_K6_3,
1929     //@}
1930 
1931     /// \name K7
1932     /// K7 architecture processors.
1933     //@{
1934     CK_Athlon,
1935     CK_AthlonThunderbird,
1936     CK_Athlon4,
1937     CK_AthlonXP,
1938     CK_AthlonMP,
1939     //@}
1940 
1941     /// \name K8
1942     /// K8 architecture processors.
1943     //@{
1944     CK_Athlon64,
1945     CK_Athlon64SSE3,
1946     CK_AthlonFX,
1947     CK_K8,
1948     CK_K8SSE3,
1949     CK_Opteron,
1950     CK_OpteronSSE3,
1951     CK_AMDFAM10,
1952     //@}
1953 
1954     /// \name Bobcat
1955     /// Bobcat architecture processors.
1956     //@{
1957     CK_BTVER1,
1958     CK_BTVER2,
1959     //@}
1960 
1961     /// \name Bulldozer
1962     /// Bulldozer architecture processors.
1963     //@{
1964     CK_BDVER1,
1965     CK_BDVER2,
1966     CK_BDVER3,
1967     CK_BDVER4,
1968     //@}
1969 
1970     /// This specification is deprecated and will be removed in the future.
1971     /// Users should prefer \see CK_K8.
1972     // FIXME: Warn on this when the CPU is set to it.
1973     //@{
1974     CK_x86_64,
1975     //@}
1976 
1977     /// \name Geode
1978     /// Geode processors.
1979     //@{
1980     CK_Geode
1981     //@}
1982   } CPU;
1983 
1984   enum FPMathKind {
1985     FP_Default,
1986     FP_SSE,
1987     FP_387
1988   } FPMath;
1989 
1990 public:
1991   X86TargetInfo(const llvm::Triple &Triple)
1992       : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1993         XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
1994         HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
1995         HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
1996         HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
1997         HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
1998         HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
1999         HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
2000     BigEndian = false;
2001     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
2002   }
2003   unsigned getFloatEvalMethod() const override {
2004     // X87 evaluates with 80 bits "long double" precision.
2005     return SSELevel == NoSSE ? 2 : 0;
2006   }
2007   void getTargetBuiltins(const Builtin::Info *&Records,
2008                                  unsigned &NumRecords) const override {
2009     Records = BuiltinInfo;
2010     NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
2011   }
2012   void getGCCRegNames(const char * const *&Names,
2013                       unsigned &NumNames) const override {
2014     Names = GCCRegNames;
2015     NumNames = llvm::array_lengthof(GCCRegNames);
2016   }
2017   void getGCCRegAliases(const GCCRegAlias *&Aliases,
2018                         unsigned &NumAliases) const override {
2019     Aliases = nullptr;
2020     NumAliases = 0;
2021   }
2022   void getGCCAddlRegNames(const AddlRegName *&Names,
2023                           unsigned &NumNames) const override {
2024     Names = AddlRegNames;
2025     NumNames = llvm::array_lengthof(AddlRegNames);
2026   }
2027   bool validateAsmConstraint(const char *&Name,
2028                              TargetInfo::ConstraintInfo &info) const override;
2029 
2030   bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2031 
2032   bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2033 
2034   virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2035 
2036   std::string convertConstraint(const char *&Constraint) const override;
2037   const char *getClobbers() const override {
2038     return "~{dirflag},~{fpsr},~{flags}";
2039   }
2040   void getTargetDefines(const LangOptions &Opts,
2041                         MacroBuilder &Builder) const override;
2042   static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2043                           bool Enabled);
2044   static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2045                           bool Enabled);
2046   static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2047                           bool Enabled);
2048   void setFeatureEnabled(llvm::StringMap<bool> &Features,
2049                          StringRef Name, bool Enabled) const override {
2050     setFeatureEnabledImpl(Features, Name, Enabled);
2051   }
2052   // This exists purely to cut down on the number of virtual calls in
2053   // getDefaultFeatures which calls this repeatedly.
2054   static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2055                                     StringRef Name, bool Enabled);
2056   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
2057   bool hasFeature(StringRef Feature) const override;
2058   bool handleTargetFeatures(std::vector<std::string> &Features,
2059                             DiagnosticsEngine &Diags) override;
2060   StringRef getABI() const override {
2061     if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2062       return "avx";
2063     else if (getTriple().getArch() == llvm::Triple::x86 &&
2064              MMX3DNowLevel == NoMMX3DNow)
2065       return "no-mmx";
2066     return "";
2067   }
2068   bool setCPU(const std::string &Name) override {
2069     CPU = llvm::StringSwitch<CPUKind>(Name)
2070       .Case("i386", CK_i386)
2071       .Case("i486", CK_i486)
2072       .Case("winchip-c6", CK_WinChipC6)
2073       .Case("winchip2", CK_WinChip2)
2074       .Case("c3", CK_C3)
2075       .Case("i586", CK_i586)
2076       .Case("pentium", CK_Pentium)
2077       .Case("pentium-mmx", CK_PentiumMMX)
2078       .Case("i686", CK_i686)
2079       .Case("pentiumpro", CK_PentiumPro)
2080       .Case("pentium2", CK_Pentium2)
2081       .Case("pentium3", CK_Pentium3)
2082       .Case("pentium3m", CK_Pentium3M)
2083       .Case("pentium-m", CK_PentiumM)
2084       .Case("c3-2", CK_C3_2)
2085       .Case("yonah", CK_Yonah)
2086       .Case("pentium4", CK_Pentium4)
2087       .Case("pentium4m", CK_Pentium4M)
2088       .Case("prescott", CK_Prescott)
2089       .Case("nocona", CK_Nocona)
2090       .Case("core2", CK_Core2)
2091       .Case("penryn", CK_Penryn)
2092       .Case("bonnell", CK_Bonnell)
2093       .Case("atom", CK_Bonnell) // Legacy name.
2094       .Case("silvermont", CK_Silvermont)
2095       .Case("slm", CK_Silvermont) // Legacy name.
2096       .Case("nehalem", CK_Nehalem)
2097       .Case("corei7", CK_Nehalem) // Legacy name.
2098       .Case("westmere", CK_Westmere)
2099       .Case("sandybridge", CK_SandyBridge)
2100       .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2101       .Case("ivybridge", CK_IvyBridge)
2102       .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2103       .Case("haswell", CK_Haswell)
2104       .Case("core-avx2", CK_Haswell) // Legacy name.
2105       .Case("broadwell", CK_Broadwell)
2106       .Case("skylake", CK_Skylake)
2107       .Case("skx", CK_Skylake) // Legacy name.
2108       .Case("knl", CK_KNL)
2109       .Case("k6", CK_K6)
2110       .Case("k6-2", CK_K6_2)
2111       .Case("k6-3", CK_K6_3)
2112       .Case("athlon", CK_Athlon)
2113       .Case("athlon-tbird", CK_AthlonThunderbird)
2114       .Case("athlon-4", CK_Athlon4)
2115       .Case("athlon-xp", CK_AthlonXP)
2116       .Case("athlon-mp", CK_AthlonMP)
2117       .Case("athlon64", CK_Athlon64)
2118       .Case("athlon64-sse3", CK_Athlon64SSE3)
2119       .Case("athlon-fx", CK_AthlonFX)
2120       .Case("k8", CK_K8)
2121       .Case("k8-sse3", CK_K8SSE3)
2122       .Case("opteron", CK_Opteron)
2123       .Case("opteron-sse3", CK_OpteronSSE3)
2124       .Case("barcelona", CK_AMDFAM10)
2125       .Case("amdfam10", CK_AMDFAM10)
2126       .Case("btver1", CK_BTVER1)
2127       .Case("btver2", CK_BTVER2)
2128       .Case("bdver1", CK_BDVER1)
2129       .Case("bdver2", CK_BDVER2)
2130       .Case("bdver3", CK_BDVER3)
2131       .Case("bdver4", CK_BDVER4)
2132       .Case("x86-64", CK_x86_64)
2133       .Case("geode", CK_Geode)
2134       .Default(CK_Generic);
2135 
2136     // Perform any per-CPU checks necessary to determine if this CPU is
2137     // acceptable.
2138     // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2139     // invalid without explaining *why*.
2140     switch (CPU) {
2141     case CK_Generic:
2142       // No processor selected!
2143       return false;
2144 
2145     case CK_i386:
2146     case CK_i486:
2147     case CK_WinChipC6:
2148     case CK_WinChip2:
2149     case CK_C3:
2150     case CK_i586:
2151     case CK_Pentium:
2152     case CK_PentiumMMX:
2153     case CK_i686:
2154     case CK_PentiumPro:
2155     case CK_Pentium2:
2156     case CK_Pentium3:
2157     case CK_Pentium3M:
2158     case CK_PentiumM:
2159     case CK_Yonah:
2160     case CK_C3_2:
2161     case CK_Pentium4:
2162     case CK_Pentium4M:
2163     case CK_Prescott:
2164     case CK_K6:
2165     case CK_K6_2:
2166     case CK_K6_3:
2167     case CK_Athlon:
2168     case CK_AthlonThunderbird:
2169     case CK_Athlon4:
2170     case CK_AthlonXP:
2171     case CK_AthlonMP:
2172     case CK_Geode:
2173       // Only accept certain architectures when compiling in 32-bit mode.
2174       if (getTriple().getArch() != llvm::Triple::x86)
2175         return false;
2176 
2177       // Fallthrough
2178     case CK_Nocona:
2179     case CK_Core2:
2180     case CK_Penryn:
2181     case CK_Bonnell:
2182     case CK_Silvermont:
2183     case CK_Nehalem:
2184     case CK_Westmere:
2185     case CK_SandyBridge:
2186     case CK_IvyBridge:
2187     case CK_Haswell:
2188     case CK_Broadwell:
2189     case CK_Skylake:
2190     case CK_KNL:
2191     case CK_Athlon64:
2192     case CK_Athlon64SSE3:
2193     case CK_AthlonFX:
2194     case CK_K8:
2195     case CK_K8SSE3:
2196     case CK_Opteron:
2197     case CK_OpteronSSE3:
2198     case CK_AMDFAM10:
2199     case CK_BTVER1:
2200     case CK_BTVER2:
2201     case CK_BDVER1:
2202     case CK_BDVER2:
2203     case CK_BDVER3:
2204     case CK_BDVER4:
2205     case CK_x86_64:
2206       return true;
2207     }
2208     llvm_unreachable("Unhandled CPU kind");
2209   }
2210 
2211   bool setFPMath(StringRef Name) override;
2212 
2213   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2214     // We accept all non-ARM calling conventions
2215     return (CC == CC_X86ThisCall ||
2216             CC == CC_X86FastCall ||
2217             CC == CC_X86StdCall ||
2218             CC == CC_X86VectorCall ||
2219             CC == CC_C ||
2220             CC == CC_X86Pascal ||
2221             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2222   }
2223 
2224   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2225     return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2226   }
2227 };
2228 
2229 bool X86TargetInfo::setFPMath(StringRef Name) {
2230   if (Name == "387") {
2231     FPMath = FP_387;
2232     return true;
2233   }
2234   if (Name == "sse") {
2235     FPMath = FP_SSE;
2236     return true;
2237   }
2238   return false;
2239 }
2240 
2241 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2242   // FIXME: This *really* should not be here.
2243 
2244   // X86_64 always has SSE2.
2245   if (getTriple().getArch() == llvm::Triple::x86_64)
2246     setFeatureEnabledImpl(Features, "sse2", true);
2247 
2248   switch (CPU) {
2249   case CK_Generic:
2250   case CK_i386:
2251   case CK_i486:
2252   case CK_i586:
2253   case CK_Pentium:
2254   case CK_i686:
2255   case CK_PentiumPro:
2256     break;
2257   case CK_PentiumMMX:
2258   case CK_Pentium2:
2259   case CK_K6:
2260   case CK_WinChipC6:
2261     setFeatureEnabledImpl(Features, "mmx", true);
2262     break;
2263   case CK_Pentium3:
2264   case CK_Pentium3M:
2265   case CK_C3_2:
2266     setFeatureEnabledImpl(Features, "sse", true);
2267     break;
2268   case CK_PentiumM:
2269   case CK_Pentium4:
2270   case CK_Pentium4M:
2271   case CK_x86_64:
2272     setFeatureEnabledImpl(Features, "sse2", true);
2273     break;
2274   case CK_Yonah:
2275   case CK_Prescott:
2276   case CK_Nocona:
2277     setFeatureEnabledImpl(Features, "sse3", true);
2278     setFeatureEnabledImpl(Features, "cx16", true);
2279     break;
2280   case CK_Core2:
2281   case CK_Bonnell:
2282     setFeatureEnabledImpl(Features, "ssse3", true);
2283     setFeatureEnabledImpl(Features, "cx16", true);
2284     break;
2285   case CK_Penryn:
2286     setFeatureEnabledImpl(Features, "sse4.1", true);
2287     setFeatureEnabledImpl(Features, "cx16", true);
2288     break;
2289   case CK_Skylake:
2290     setFeatureEnabledImpl(Features, "avx512f", true);
2291     setFeatureEnabledImpl(Features, "avx512cd", true);
2292     setFeatureEnabledImpl(Features, "avx512dq", true);
2293     setFeatureEnabledImpl(Features, "avx512bw", true);
2294     setFeatureEnabledImpl(Features, "avx512vl", true);
2295     // FALLTHROUGH
2296   case CK_Broadwell:
2297     setFeatureEnabledImpl(Features, "rdseed", true);
2298     setFeatureEnabledImpl(Features, "adx", true);
2299     // FALLTHROUGH
2300   case CK_Haswell:
2301     setFeatureEnabledImpl(Features, "avx2", true);
2302     setFeatureEnabledImpl(Features, "lzcnt", true);
2303     setFeatureEnabledImpl(Features, "bmi", true);
2304     setFeatureEnabledImpl(Features, "bmi2", true);
2305     setFeatureEnabledImpl(Features, "rtm", true);
2306     setFeatureEnabledImpl(Features, "fma", true);
2307     // FALLTHROUGH
2308   case CK_IvyBridge:
2309     setFeatureEnabledImpl(Features, "rdrnd", true);
2310     setFeatureEnabledImpl(Features, "f16c", true);
2311     setFeatureEnabledImpl(Features, "fsgsbase", true);
2312     // FALLTHROUGH
2313   case CK_SandyBridge:
2314     setFeatureEnabledImpl(Features, "avx", true);
2315     // FALLTHROUGH
2316   case CK_Westmere:
2317   case CK_Silvermont:
2318     setFeatureEnabledImpl(Features, "aes", true);
2319     setFeatureEnabledImpl(Features, "pclmul", true);
2320     // FALLTHROUGH
2321   case CK_Nehalem:
2322     setFeatureEnabledImpl(Features, "sse4.2", true);
2323     setFeatureEnabledImpl(Features, "cx16", true);
2324     break;
2325   case CK_KNL:
2326     setFeatureEnabledImpl(Features, "avx512f", true);
2327     setFeatureEnabledImpl(Features, "avx512cd", true);
2328     setFeatureEnabledImpl(Features, "avx512er", true);
2329     setFeatureEnabledImpl(Features, "avx512pf", true);
2330     setFeatureEnabledImpl(Features, "rdseed", true);
2331     setFeatureEnabledImpl(Features, "adx", true);
2332     setFeatureEnabledImpl(Features, "lzcnt", true);
2333     setFeatureEnabledImpl(Features, "bmi", true);
2334     setFeatureEnabledImpl(Features, "bmi2", true);
2335     setFeatureEnabledImpl(Features, "rtm", true);
2336     setFeatureEnabledImpl(Features, "fma", true);
2337     setFeatureEnabledImpl(Features, "rdrnd", true);
2338     setFeatureEnabledImpl(Features, "f16c", true);
2339     setFeatureEnabledImpl(Features, "fsgsbase", true);
2340     setFeatureEnabledImpl(Features, "aes", true);
2341     setFeatureEnabledImpl(Features, "pclmul", true);
2342     setFeatureEnabledImpl(Features, "cx16", true);
2343     break;
2344   case CK_K6_2:
2345   case CK_K6_3:
2346   case CK_WinChip2:
2347   case CK_C3:
2348     setFeatureEnabledImpl(Features, "3dnow", true);
2349     break;
2350   case CK_Athlon:
2351   case CK_AthlonThunderbird:
2352   case CK_Geode:
2353     setFeatureEnabledImpl(Features, "3dnowa", true);
2354     break;
2355   case CK_Athlon4:
2356   case CK_AthlonXP:
2357   case CK_AthlonMP:
2358     setFeatureEnabledImpl(Features, "sse", true);
2359     setFeatureEnabledImpl(Features, "3dnowa", true);
2360     break;
2361   case CK_K8:
2362   case CK_Opteron:
2363   case CK_Athlon64:
2364   case CK_AthlonFX:
2365     setFeatureEnabledImpl(Features, "sse2", true);
2366     setFeatureEnabledImpl(Features, "3dnowa", true);
2367     break;
2368   case CK_AMDFAM10:
2369     setFeatureEnabledImpl(Features, "sse4a", true);
2370     setFeatureEnabledImpl(Features, "lzcnt", true);
2371     setFeatureEnabledImpl(Features, "popcnt", true);
2372     // FALLTHROUGH
2373   case CK_K8SSE3:
2374   case CK_OpteronSSE3:
2375   case CK_Athlon64SSE3:
2376     setFeatureEnabledImpl(Features, "sse3", true);
2377     setFeatureEnabledImpl(Features, "3dnowa", true);
2378     break;
2379   case CK_BTVER2:
2380     setFeatureEnabledImpl(Features, "avx", true);
2381     setFeatureEnabledImpl(Features, "aes", true);
2382     setFeatureEnabledImpl(Features, "pclmul", true);
2383     setFeatureEnabledImpl(Features, "bmi", true);
2384     setFeatureEnabledImpl(Features, "f16c", true);
2385     // FALLTHROUGH
2386   case CK_BTVER1:
2387     setFeatureEnabledImpl(Features, "ssse3", true);
2388     setFeatureEnabledImpl(Features, "sse4a", true);
2389     setFeatureEnabledImpl(Features, "lzcnt", true);
2390     setFeatureEnabledImpl(Features, "popcnt", true);
2391     setFeatureEnabledImpl(Features, "prfchw", true);
2392     setFeatureEnabledImpl(Features, "cx16", true);
2393     break;
2394   case CK_BDVER4:
2395     setFeatureEnabledImpl(Features, "avx2", true);
2396     setFeatureEnabledImpl(Features, "bmi2", true);
2397     // FALLTHROUGH
2398   case CK_BDVER3:
2399     setFeatureEnabledImpl(Features, "fsgsbase", true);
2400     // FALLTHROUGH
2401   case CK_BDVER2:
2402     setFeatureEnabledImpl(Features, "bmi", true);
2403     setFeatureEnabledImpl(Features, "fma", true);
2404     setFeatureEnabledImpl(Features, "f16c", true);
2405     setFeatureEnabledImpl(Features, "tbm", true);
2406     // FALLTHROUGH
2407   case CK_BDVER1:
2408     // xop implies avx, sse4a and fma4.
2409     setFeatureEnabledImpl(Features, "xop", true);
2410     setFeatureEnabledImpl(Features, "lzcnt", true);
2411     setFeatureEnabledImpl(Features, "aes", true);
2412     setFeatureEnabledImpl(Features, "pclmul", true);
2413     setFeatureEnabledImpl(Features, "prfchw", true);
2414     setFeatureEnabledImpl(Features, "cx16", true);
2415     break;
2416   }
2417 }
2418 
2419 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2420                                 X86SSEEnum Level, bool Enabled) {
2421   if (Enabled) {
2422     switch (Level) {
2423     case AVX512F:
2424       Features["avx512f"] = true;
2425     case AVX2:
2426       Features["avx2"] = true;
2427     case AVX:
2428       Features["avx"] = true;
2429     case SSE42:
2430       Features["sse4.2"] = true;
2431     case SSE41:
2432       Features["sse4.1"] = true;
2433     case SSSE3:
2434       Features["ssse3"] = true;
2435     case SSE3:
2436       Features["sse3"] = true;
2437     case SSE2:
2438       Features["sse2"] = true;
2439     case SSE1:
2440       Features["sse"] = true;
2441     case NoSSE:
2442       break;
2443     }
2444     return;
2445   }
2446 
2447   switch (Level) {
2448   case NoSSE:
2449   case SSE1:
2450     Features["sse"] = false;
2451   case SSE2:
2452     Features["sse2"] = Features["pclmul"] = Features["aes"] =
2453       Features["sha"] = false;
2454   case SSE3:
2455     Features["sse3"] = false;
2456     setXOPLevel(Features, NoXOP, false);
2457   case SSSE3:
2458     Features["ssse3"] = false;
2459   case SSE41:
2460     Features["sse4.1"] = false;
2461   case SSE42:
2462     Features["sse4.2"] = false;
2463   case AVX:
2464     Features["fma"] = Features["avx"] = Features["f16c"] = false;
2465     setXOPLevel(Features, FMA4, false);
2466   case AVX2:
2467     Features["avx2"] = false;
2468   case AVX512F:
2469     Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2470       Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2471       Features["avx512vl"] = false;
2472   }
2473 }
2474 
2475 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2476                                 MMX3DNowEnum Level, bool Enabled) {
2477   if (Enabled) {
2478     switch (Level) {
2479     case AMD3DNowAthlon:
2480       Features["3dnowa"] = true;
2481     case AMD3DNow:
2482       Features["3dnow"] = true;
2483     case MMX:
2484       Features["mmx"] = true;
2485     case NoMMX3DNow:
2486       break;
2487     }
2488     return;
2489   }
2490 
2491   switch (Level) {
2492   case NoMMX3DNow:
2493   case MMX:
2494     Features["mmx"] = false;
2495   case AMD3DNow:
2496     Features["3dnow"] = false;
2497   case AMD3DNowAthlon:
2498     Features["3dnowa"] = false;
2499   }
2500 }
2501 
2502 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2503                                 bool Enabled) {
2504   if (Enabled) {
2505     switch (Level) {
2506     case XOP:
2507       Features["xop"] = true;
2508     case FMA4:
2509       Features["fma4"] = true;
2510       setSSELevel(Features, AVX, true);
2511     case SSE4A:
2512       Features["sse4a"] = true;
2513       setSSELevel(Features, SSE3, true);
2514     case NoXOP:
2515       break;
2516     }
2517     return;
2518   }
2519 
2520   switch (Level) {
2521   case NoXOP:
2522   case SSE4A:
2523     Features["sse4a"] = false;
2524   case FMA4:
2525     Features["fma4"] = false;
2526   case XOP:
2527     Features["xop"] = false;
2528   }
2529 }
2530 
2531 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2532                                           StringRef Name, bool Enabled) {
2533   // FIXME: This *really* should not be here.  We need some way of translating
2534   // options into llvm subtarget features.
2535   if (Name == "sse4")
2536     Name = "sse4.2";
2537 
2538   Features[Name] = Enabled;
2539 
2540   if (Name == "mmx") {
2541     setMMXLevel(Features, MMX, Enabled);
2542   } else if (Name == "sse") {
2543     setSSELevel(Features, SSE1, Enabled);
2544   } else if (Name == "sse2") {
2545     setSSELevel(Features, SSE2, Enabled);
2546   } else if (Name == "sse3") {
2547     setSSELevel(Features, SSE3, Enabled);
2548   } else if (Name == "ssse3") {
2549     setSSELevel(Features, SSSE3, Enabled);
2550   } else if (Name == "sse4.2") {
2551     setSSELevel(Features, SSE42, Enabled);
2552   } else if (Name == "sse4.1") {
2553     setSSELevel(Features, SSE41, Enabled);
2554   } else if (Name == "3dnow") {
2555     setMMXLevel(Features, AMD3DNow, Enabled);
2556   } else if (Name == "3dnowa") {
2557     setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2558   } else if (Name == "aes") {
2559     if (Enabled)
2560       setSSELevel(Features, SSE2, Enabled);
2561   } else if (Name == "pclmul") {
2562     if (Enabled)
2563       setSSELevel(Features, SSE2, Enabled);
2564   } else if (Name == "avx") {
2565     setSSELevel(Features, AVX, Enabled);
2566   } else if (Name == "avx2") {
2567     setSSELevel(Features, AVX2, Enabled);
2568   } else if (Name == "avx512f") {
2569     setSSELevel(Features, AVX512F, Enabled);
2570   } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2571           || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2572     if (Enabled)
2573       setSSELevel(Features, AVX512F, Enabled);
2574   } else if (Name == "fma") {
2575     if (Enabled)
2576       setSSELevel(Features, AVX, Enabled);
2577   } else if (Name == "fma4") {
2578     setXOPLevel(Features, FMA4, Enabled);
2579   } else if (Name == "xop") {
2580     setXOPLevel(Features, XOP, Enabled);
2581   } else if (Name == "sse4a") {
2582     setXOPLevel(Features, SSE4A, Enabled);
2583   } else if (Name == "f16c") {
2584     if (Enabled)
2585       setSSELevel(Features, AVX, Enabled);
2586   } else if (Name == "sha") {
2587     if (Enabled)
2588       setSSELevel(Features, SSE2, Enabled);
2589   }
2590 }
2591 
2592 /// handleTargetFeatures - Perform initialization based on the user
2593 /// configured set of features.
2594 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2595                                          DiagnosticsEngine &Diags) {
2596   // Remember the maximum enabled sselevel.
2597   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2598     // Ignore disabled features.
2599     if (Features[i][0] == '-')
2600       continue;
2601 
2602     StringRef Feature = StringRef(Features[i]).substr(1);
2603 
2604     if (Feature == "aes") {
2605       HasAES = true;
2606       continue;
2607     }
2608 
2609     if (Feature == "pclmul") {
2610       HasPCLMUL = true;
2611       continue;
2612     }
2613 
2614     if (Feature == "lzcnt") {
2615       HasLZCNT = true;
2616       continue;
2617     }
2618 
2619     if (Feature == "rdrnd") {
2620       HasRDRND = true;
2621       continue;
2622     }
2623 
2624     if (Feature == "fsgsbase") {
2625       HasFSGSBASE = true;
2626       continue;
2627     }
2628 
2629     if (Feature == "bmi") {
2630       HasBMI = true;
2631       continue;
2632     }
2633 
2634     if (Feature == "bmi2") {
2635       HasBMI2 = true;
2636       continue;
2637     }
2638 
2639     if (Feature == "popcnt") {
2640       HasPOPCNT = true;
2641       continue;
2642     }
2643 
2644     if (Feature == "rtm") {
2645       HasRTM = true;
2646       continue;
2647     }
2648 
2649     if (Feature == "prfchw") {
2650       HasPRFCHW = true;
2651       continue;
2652     }
2653 
2654     if (Feature == "rdseed") {
2655       HasRDSEED = true;
2656       continue;
2657     }
2658 
2659     if (Feature == "adx") {
2660       HasADX = true;
2661       continue;
2662     }
2663 
2664     if (Feature == "tbm") {
2665       HasTBM = true;
2666       continue;
2667     }
2668 
2669     if (Feature == "fma") {
2670       HasFMA = true;
2671       continue;
2672     }
2673 
2674     if (Feature == "f16c") {
2675       HasF16C = true;
2676       continue;
2677     }
2678 
2679     if (Feature == "avx512cd") {
2680       HasAVX512CD = true;
2681       continue;
2682     }
2683 
2684     if (Feature == "avx512er") {
2685       HasAVX512ER = true;
2686       continue;
2687     }
2688 
2689     if (Feature == "avx512pf") {
2690       HasAVX512PF = true;
2691       continue;
2692     }
2693 
2694     if (Feature == "avx512dq") {
2695       HasAVX512DQ = true;
2696       continue;
2697     }
2698 
2699     if (Feature == "avx512bw") {
2700       HasAVX512BW = true;
2701       continue;
2702     }
2703 
2704     if (Feature == "avx512vl") {
2705       HasAVX512VL = true;
2706       continue;
2707     }
2708 
2709     if (Feature == "sha") {
2710       HasSHA = true;
2711       continue;
2712     }
2713 
2714     if (Feature == "cx16") {
2715       HasCX16 = true;
2716       continue;
2717     }
2718 
2719     assert(Features[i][0] == '+' && "Invalid target feature!");
2720     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2721       .Case("avx512f", AVX512F)
2722       .Case("avx2", AVX2)
2723       .Case("avx", AVX)
2724       .Case("sse4.2", SSE42)
2725       .Case("sse4.1", SSE41)
2726       .Case("ssse3", SSSE3)
2727       .Case("sse3", SSE3)
2728       .Case("sse2", SSE2)
2729       .Case("sse", SSE1)
2730       .Default(NoSSE);
2731     SSELevel = std::max(SSELevel, Level);
2732 
2733     MMX3DNowEnum ThreeDNowLevel =
2734       llvm::StringSwitch<MMX3DNowEnum>(Feature)
2735         .Case("3dnowa", AMD3DNowAthlon)
2736         .Case("3dnow", AMD3DNow)
2737         .Case("mmx", MMX)
2738         .Default(NoMMX3DNow);
2739     MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2740 
2741     XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2742         .Case("xop", XOP)
2743         .Case("fma4", FMA4)
2744         .Case("sse4a", SSE4A)
2745         .Default(NoXOP);
2746     XOPLevel = std::max(XOPLevel, XLevel);
2747   }
2748 
2749   // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2750   // Can't do this earlier because we need to be able to explicitly enable
2751   // popcnt and still disable sse4.2.
2752   if (!HasPOPCNT && SSELevel >= SSE42 &&
2753       std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2754     HasPOPCNT = true;
2755     Features.push_back("+popcnt");
2756   }
2757 
2758   // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2759   if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2760       std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2761     HasPRFCHW = true;
2762     Features.push_back("+prfchw");
2763   }
2764 
2765   // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2766   // matches the selected sse level.
2767   if (FPMath == FP_SSE && SSELevel < SSE1) {
2768     Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2769     return false;
2770   } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2771     Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2772     return false;
2773   }
2774 
2775   // Don't tell the backend if we're turning off mmx; it will end up disabling
2776   // SSE, which we don't want.
2777   // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2778   // then enable MMX.
2779   std::vector<std::string>::iterator it;
2780   it = std::find(Features.begin(), Features.end(), "-mmx");
2781   if (it != Features.end())
2782     Features.erase(it);
2783   else if (SSELevel > NoSSE)
2784     MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2785   return true;
2786 }
2787 
2788 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2789 /// definitions for this particular subtarget.
2790 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2791                                      MacroBuilder &Builder) const {
2792   // Target identification.
2793   if (getTriple().getArch() == llvm::Triple::x86_64) {
2794     Builder.defineMacro("__amd64__");
2795     Builder.defineMacro("__amd64");
2796     Builder.defineMacro("__x86_64");
2797     Builder.defineMacro("__x86_64__");
2798     if (getTriple().getArchName() == "x86_64h") {
2799       Builder.defineMacro("__x86_64h");
2800       Builder.defineMacro("__x86_64h__");
2801     }
2802   } else {
2803     DefineStd(Builder, "i386", Opts);
2804   }
2805 
2806   // Subtarget options.
2807   // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2808   // truly should be based on -mtune options.
2809   switch (CPU) {
2810   case CK_Generic:
2811     break;
2812   case CK_i386:
2813     // The rest are coming from the i386 define above.
2814     Builder.defineMacro("__tune_i386__");
2815     break;
2816   case CK_i486:
2817   case CK_WinChipC6:
2818   case CK_WinChip2:
2819   case CK_C3:
2820     defineCPUMacros(Builder, "i486");
2821     break;
2822   case CK_PentiumMMX:
2823     Builder.defineMacro("__pentium_mmx__");
2824     Builder.defineMacro("__tune_pentium_mmx__");
2825     // Fallthrough
2826   case CK_i586:
2827   case CK_Pentium:
2828     defineCPUMacros(Builder, "i586");
2829     defineCPUMacros(Builder, "pentium");
2830     break;
2831   case CK_Pentium3:
2832   case CK_Pentium3M:
2833   case CK_PentiumM:
2834     Builder.defineMacro("__tune_pentium3__");
2835     // Fallthrough
2836   case CK_Pentium2:
2837   case CK_C3_2:
2838     Builder.defineMacro("__tune_pentium2__");
2839     // Fallthrough
2840   case CK_PentiumPro:
2841     Builder.defineMacro("__tune_i686__");
2842     Builder.defineMacro("__tune_pentiumpro__");
2843     // Fallthrough
2844   case CK_i686:
2845     Builder.defineMacro("__i686");
2846     Builder.defineMacro("__i686__");
2847     // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2848     Builder.defineMacro("__pentiumpro");
2849     Builder.defineMacro("__pentiumpro__");
2850     break;
2851   case CK_Pentium4:
2852   case CK_Pentium4M:
2853     defineCPUMacros(Builder, "pentium4");
2854     break;
2855   case CK_Yonah:
2856   case CK_Prescott:
2857   case CK_Nocona:
2858     defineCPUMacros(Builder, "nocona");
2859     break;
2860   case CK_Core2:
2861   case CK_Penryn:
2862     defineCPUMacros(Builder, "core2");
2863     break;
2864   case CK_Bonnell:
2865     defineCPUMacros(Builder, "atom");
2866     break;
2867   case CK_Silvermont:
2868     defineCPUMacros(Builder, "slm");
2869     break;
2870   case CK_Nehalem:
2871   case CK_Westmere:
2872   case CK_SandyBridge:
2873   case CK_IvyBridge:
2874   case CK_Haswell:
2875   case CK_Broadwell:
2876     // FIXME: Historically, we defined this legacy name, it would be nice to
2877     // remove it at some point. We've never exposed fine-grained names for
2878     // recent primary x86 CPUs, and we should keep it that way.
2879     defineCPUMacros(Builder, "corei7");
2880     break;
2881   case CK_Skylake:
2882     // FIXME: Historically, we defined this legacy name, it would be nice to
2883     // remove it at some point. This is the only fine-grained CPU macro in the
2884     // main intel CPU line, and it would be better to not have these and force
2885     // people to use ISA macros.
2886     defineCPUMacros(Builder, "skx");
2887     break;
2888   case CK_KNL:
2889     defineCPUMacros(Builder, "knl");
2890     break;
2891   case CK_K6_2:
2892     Builder.defineMacro("__k6_2__");
2893     Builder.defineMacro("__tune_k6_2__");
2894     // Fallthrough
2895   case CK_K6_3:
2896     if (CPU != CK_K6_2) {  // In case of fallthrough
2897       // FIXME: GCC may be enabling these in cases where some other k6
2898       // architecture is specified but -m3dnow is explicitly provided. The
2899       // exact semantics need to be determined and emulated here.
2900       Builder.defineMacro("__k6_3__");
2901       Builder.defineMacro("__tune_k6_3__");
2902     }
2903     // Fallthrough
2904   case CK_K6:
2905     defineCPUMacros(Builder, "k6");
2906     break;
2907   case CK_Athlon:
2908   case CK_AthlonThunderbird:
2909   case CK_Athlon4:
2910   case CK_AthlonXP:
2911   case CK_AthlonMP:
2912     defineCPUMacros(Builder, "athlon");
2913     if (SSELevel != NoSSE) {
2914       Builder.defineMacro("__athlon_sse__");
2915       Builder.defineMacro("__tune_athlon_sse__");
2916     }
2917     break;
2918   case CK_K8:
2919   case CK_K8SSE3:
2920   case CK_x86_64:
2921   case CK_Opteron:
2922   case CK_OpteronSSE3:
2923   case CK_Athlon64:
2924   case CK_Athlon64SSE3:
2925   case CK_AthlonFX:
2926     defineCPUMacros(Builder, "k8");
2927     break;
2928   case CK_AMDFAM10:
2929     defineCPUMacros(Builder, "amdfam10");
2930     break;
2931   case CK_BTVER1:
2932     defineCPUMacros(Builder, "btver1");
2933     break;
2934   case CK_BTVER2:
2935     defineCPUMacros(Builder, "btver2");
2936     break;
2937   case CK_BDVER1:
2938     defineCPUMacros(Builder, "bdver1");
2939     break;
2940   case CK_BDVER2:
2941     defineCPUMacros(Builder, "bdver2");
2942     break;
2943   case CK_BDVER3:
2944     defineCPUMacros(Builder, "bdver3");
2945     break;
2946   case CK_BDVER4:
2947     defineCPUMacros(Builder, "bdver4");
2948     break;
2949   case CK_Geode:
2950     defineCPUMacros(Builder, "geode");
2951     break;
2952   }
2953 
2954   // Target properties.
2955   Builder.defineMacro("__REGISTER_PREFIX__", "");
2956 
2957   // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2958   // functions in glibc header files that use FP Stack inline asm which the
2959   // backend can't deal with (PR879).
2960   Builder.defineMacro("__NO_MATH_INLINES");
2961 
2962   if (HasAES)
2963     Builder.defineMacro("__AES__");
2964 
2965   if (HasPCLMUL)
2966     Builder.defineMacro("__PCLMUL__");
2967 
2968   if (HasLZCNT)
2969     Builder.defineMacro("__LZCNT__");
2970 
2971   if (HasRDRND)
2972     Builder.defineMacro("__RDRND__");
2973 
2974   if (HasFSGSBASE)
2975     Builder.defineMacro("__FSGSBASE__");
2976 
2977   if (HasBMI)
2978     Builder.defineMacro("__BMI__");
2979 
2980   if (HasBMI2)
2981     Builder.defineMacro("__BMI2__");
2982 
2983   if (HasPOPCNT)
2984     Builder.defineMacro("__POPCNT__");
2985 
2986   if (HasRTM)
2987     Builder.defineMacro("__RTM__");
2988 
2989   if (HasPRFCHW)
2990     Builder.defineMacro("__PRFCHW__");
2991 
2992   if (HasRDSEED)
2993     Builder.defineMacro("__RDSEED__");
2994 
2995   if (HasADX)
2996     Builder.defineMacro("__ADX__");
2997 
2998   if (HasTBM)
2999     Builder.defineMacro("__TBM__");
3000 
3001   switch (XOPLevel) {
3002   case XOP:
3003     Builder.defineMacro("__XOP__");
3004   case FMA4:
3005     Builder.defineMacro("__FMA4__");
3006   case SSE4A:
3007     Builder.defineMacro("__SSE4A__");
3008   case NoXOP:
3009     break;
3010   }
3011 
3012   if (HasFMA)
3013     Builder.defineMacro("__FMA__");
3014 
3015   if (HasF16C)
3016     Builder.defineMacro("__F16C__");
3017 
3018   if (HasAVX512CD)
3019     Builder.defineMacro("__AVX512CD__");
3020   if (HasAVX512ER)
3021     Builder.defineMacro("__AVX512ER__");
3022   if (HasAVX512PF)
3023     Builder.defineMacro("__AVX512PF__");
3024   if (HasAVX512DQ)
3025     Builder.defineMacro("__AVX512DQ__");
3026   if (HasAVX512BW)
3027     Builder.defineMacro("__AVX512BW__");
3028   if (HasAVX512VL)
3029     Builder.defineMacro("__AVX512VL__");
3030 
3031   if (HasSHA)
3032     Builder.defineMacro("__SHA__");
3033 
3034   if (HasCX16)
3035     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3036 
3037   // Each case falls through to the previous one here.
3038   switch (SSELevel) {
3039   case AVX512F:
3040     Builder.defineMacro("__AVX512F__");
3041   case AVX2:
3042     Builder.defineMacro("__AVX2__");
3043   case AVX:
3044     Builder.defineMacro("__AVX__");
3045   case SSE42:
3046     Builder.defineMacro("__SSE4_2__");
3047   case SSE41:
3048     Builder.defineMacro("__SSE4_1__");
3049   case SSSE3:
3050     Builder.defineMacro("__SSSE3__");
3051   case SSE3:
3052     Builder.defineMacro("__SSE3__");
3053   case SSE2:
3054     Builder.defineMacro("__SSE2__");
3055     Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
3056   case SSE1:
3057     Builder.defineMacro("__SSE__");
3058     Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
3059   case NoSSE:
3060     break;
3061   }
3062 
3063   if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3064     switch (SSELevel) {
3065     case AVX512F:
3066     case AVX2:
3067     case AVX:
3068     case SSE42:
3069     case SSE41:
3070     case SSSE3:
3071     case SSE3:
3072     case SSE2:
3073       Builder.defineMacro("_M_IX86_FP", Twine(2));
3074       break;
3075     case SSE1:
3076       Builder.defineMacro("_M_IX86_FP", Twine(1));
3077       break;
3078     default:
3079       Builder.defineMacro("_M_IX86_FP", Twine(0));
3080     }
3081   }
3082 
3083   // Each case falls through to the previous one here.
3084   switch (MMX3DNowLevel) {
3085   case AMD3DNowAthlon:
3086     Builder.defineMacro("__3dNOW_A__");
3087   case AMD3DNow:
3088     Builder.defineMacro("__3dNOW__");
3089   case MMX:
3090     Builder.defineMacro("__MMX__");
3091   case NoMMX3DNow:
3092     break;
3093   }
3094 
3095   if (CPU >= CK_i486) {
3096     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3097     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3098     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3099   }
3100   if (CPU >= CK_i586)
3101     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3102 }
3103 
3104 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3105   return llvm::StringSwitch<bool>(Feature)
3106       .Case("aes", HasAES)
3107       .Case("avx", SSELevel >= AVX)
3108       .Case("avx2", SSELevel >= AVX2)
3109       .Case("avx512f", SSELevel >= AVX512F)
3110       .Case("avx512cd", HasAVX512CD)
3111       .Case("avx512er", HasAVX512ER)
3112       .Case("avx512pf", HasAVX512PF)
3113       .Case("avx512dq", HasAVX512DQ)
3114       .Case("avx512bw", HasAVX512BW)
3115       .Case("avx512vl", HasAVX512VL)
3116       .Case("bmi", HasBMI)
3117       .Case("bmi2", HasBMI2)
3118       .Case("cx16", HasCX16)
3119       .Case("f16c", HasF16C)
3120       .Case("fma", HasFMA)
3121       .Case("fma4", XOPLevel >= FMA4)
3122       .Case("fsgsbase", HasFSGSBASE)
3123       .Case("lzcnt", HasLZCNT)
3124       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3125       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3126       .Case("mmx", MMX3DNowLevel >= MMX)
3127       .Case("pclmul", HasPCLMUL)
3128       .Case("popcnt", HasPOPCNT)
3129       .Case("prfchw", HasPRFCHW)
3130       .Case("rdrnd", HasRDRND)
3131       .Case("rdseed", HasRDSEED)
3132       .Case("rtm", HasRTM)
3133       .Case("sha", HasSHA)
3134       .Case("sse", SSELevel >= SSE1)
3135       .Case("sse2", SSELevel >= SSE2)
3136       .Case("sse3", SSELevel >= SSE3)
3137       .Case("ssse3", SSELevel >= SSSE3)
3138       .Case("sse4.1", SSELevel >= SSE41)
3139       .Case("sse4.2", SSELevel >= SSE42)
3140       .Case("sse4a", XOPLevel >= SSE4A)
3141       .Case("tbm", HasTBM)
3142       .Case("x86", true)
3143       .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3144       .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3145       .Case("xop", XOPLevel >= XOP)
3146       .Default(false);
3147 }
3148 
3149 bool
3150 X86TargetInfo::validateAsmConstraint(const char *&Name,
3151                                      TargetInfo::ConstraintInfo &Info) const {
3152   switch (*Name) {
3153   default: return false;
3154   case 'I':
3155     Info.setRequiresImmediate(0, 31);
3156     return true;
3157   case 'J':
3158     Info.setRequiresImmediate(0, 63);
3159     return true;
3160   case 'K':
3161     Info.setRequiresImmediate(-128, 127);
3162     return true;
3163   case 'L':
3164     // FIXME: properly analyze this constraint:
3165     //  must be one of 0xff, 0xffff, or 0xffffffff
3166     return true;
3167   case 'M':
3168     Info.setRequiresImmediate(0, 3);
3169     return true;
3170   case 'N':
3171     Info.setRequiresImmediate(0, 255);
3172     return true;
3173   case 'O':
3174     Info.setRequiresImmediate(0, 127);
3175     return true;
3176   case 'Y': // first letter of a pair:
3177     switch (*(Name+1)) {
3178     default: return false;
3179     case '0':  // First SSE register.
3180     case 't':  // Any SSE register, when SSE2 is enabled.
3181     case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
3182     case 'm':  // any MMX register, when inter-unit moves enabled.
3183       break;   // falls through to setAllowsRegister.
3184   }
3185   case 'f': // any x87 floating point stack register.
3186     // Constraint 'f' cannot be used for output operands.
3187     if (Info.ConstraintStr[0] == '=')
3188       return false;
3189 
3190     Info.setAllowsRegister();
3191     return true;
3192   case 'a': // eax.
3193   case 'b': // ebx.
3194   case 'c': // ecx.
3195   case 'd': // edx.
3196   case 'S': // esi.
3197   case 'D': // edi.
3198   case 'A': // edx:eax.
3199   case 't': // top of floating point stack.
3200   case 'u': // second from top of floating point stack.
3201   case 'q': // Any register accessible as [r]l: a, b, c, and d.
3202   case 'y': // Any MMX register.
3203   case 'x': // Any SSE register.
3204   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3205   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3206   case 'l': // "Index" registers: any general register that can be used as an
3207             // index in a base+index memory access.
3208     Info.setAllowsRegister();
3209     return true;
3210   case 'C': // SSE floating point constant.
3211   case 'G': // x87 floating point constant.
3212   case 'e': // 32-bit signed integer constant for use with zero-extending
3213             // x86_64 instructions.
3214   case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3215             // x86_64 instructions.
3216     return true;
3217   }
3218 }
3219 
3220 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3221                                        unsigned Size) const {
3222   // Strip off constraint modifiers.
3223   while (Constraint[0] == '=' ||
3224          Constraint[0] == '+' ||
3225          Constraint[0] == '&')
3226     Constraint = Constraint.substr(1);
3227 
3228   return validateOperandSize(Constraint, Size);
3229 }
3230 
3231 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3232                                       unsigned Size) const {
3233   return validateOperandSize(Constraint, Size);
3234 }
3235 
3236 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3237                                         unsigned Size) const {
3238   switch (Constraint[0]) {
3239   default: break;
3240   case 'y':
3241     return Size <= 64;
3242   case 'f':
3243   case 't':
3244   case 'u':
3245     return Size <= 128;
3246   case 'x':
3247     // 256-bit ymm registers can be used if target supports AVX.
3248     return Size <= (SSELevel >= AVX ? 256U : 128U);
3249   }
3250 
3251   return true;
3252 }
3253 
3254 std::string
3255 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3256   switch (*Constraint) {
3257   case 'a': return std::string("{ax}");
3258   case 'b': return std::string("{bx}");
3259   case 'c': return std::string("{cx}");
3260   case 'd': return std::string("{dx}");
3261   case 'S': return std::string("{si}");
3262   case 'D': return std::string("{di}");
3263   case 'p': // address
3264     return std::string("im");
3265   case 't': // top of floating point stack.
3266     return std::string("{st}");
3267   case 'u': // second from top of floating point stack.
3268     return std::string("{st(1)}"); // second from top of floating point stack.
3269   default:
3270     return std::string(1, *Constraint);
3271   }
3272 }
3273 } // end anonymous namespace
3274 
3275 namespace {
3276 // X86-32 generic target
3277 class X86_32TargetInfo : public X86TargetInfo {
3278 public:
3279   X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3280     DoubleAlign = LongLongAlign = 32;
3281     LongDoubleWidth = 96;
3282     LongDoubleAlign = 32;
3283     SuitableAlign = 128;
3284     DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3285     SizeType = UnsignedInt;
3286     PtrDiffType = SignedInt;
3287     IntPtrType = SignedInt;
3288     RegParmMax = 3;
3289 
3290     // Use fpret for all types.
3291     RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3292                              (1 << TargetInfo::Double) |
3293                              (1 << TargetInfo::LongDouble));
3294 
3295     // x86-32 has atomics up to 8 bytes
3296     // FIXME: Check that we actually have cmpxchg8b before setting
3297     // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3298     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3299   }
3300   BuiltinVaListKind getBuiltinVaListKind() const override {
3301     return TargetInfo::CharPtrBuiltinVaList;
3302   }
3303 
3304   int getEHDataRegisterNumber(unsigned RegNo) const override {
3305     if (RegNo == 0) return 0;
3306     if (RegNo == 1) return 2;
3307     return -1;
3308   }
3309   bool validateOperandSize(StringRef Constraint,
3310                            unsigned Size) const override {
3311     switch (Constraint[0]) {
3312     default: break;
3313     case 'R':
3314     case 'q':
3315     case 'Q':
3316     case 'a':
3317     case 'b':
3318     case 'c':
3319     case 'd':
3320     case 'S':
3321     case 'D':
3322       return Size <= 32;
3323     case 'A':
3324       return Size <= 64;
3325     }
3326 
3327     return X86TargetInfo::validateOperandSize(Constraint, Size);
3328   }
3329 };
3330 } // end anonymous namespace
3331 
3332 namespace {
3333 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3334 public:
3335   NetBSDI386TargetInfo(const llvm::Triple &Triple)
3336       : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3337 
3338   unsigned getFloatEvalMethod() const override {
3339     unsigned Major, Minor, Micro;
3340     getTriple().getOSVersion(Major, Minor, Micro);
3341     // New NetBSD uses the default rounding mode.
3342     if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3343       return X86_32TargetInfo::getFloatEvalMethod();
3344     // NetBSD before 6.99.26 defaults to "double" rounding.
3345     return 1;
3346   }
3347 };
3348 } // end anonymous namespace
3349 
3350 namespace {
3351 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3352 public:
3353   OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3354       : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3355     SizeType = UnsignedLong;
3356     IntPtrType = SignedLong;
3357     PtrDiffType = SignedLong;
3358   }
3359 };
3360 } // end anonymous namespace
3361 
3362 namespace {
3363 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3364 public:
3365   BitrigI386TargetInfo(const llvm::Triple &Triple)
3366       : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3367     SizeType = UnsignedLong;
3368     IntPtrType = SignedLong;
3369     PtrDiffType = SignedLong;
3370   }
3371 };
3372 } // end anonymous namespace
3373 
3374 namespace {
3375 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3376 public:
3377   DarwinI386TargetInfo(const llvm::Triple &Triple)
3378       : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3379     LongDoubleWidth = 128;
3380     LongDoubleAlign = 128;
3381     SuitableAlign = 128;
3382     MaxVectorAlign = 256;
3383     SizeType = UnsignedLong;
3384     IntPtrType = SignedLong;
3385     DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3386     HasAlignMac68kSupport = true;
3387   }
3388 
3389 };
3390 } // end anonymous namespace
3391 
3392 namespace {
3393 // x86-32 Windows target
3394 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3395 public:
3396   WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3397       : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3398     WCharType = UnsignedShort;
3399     DoubleAlign = LongLongAlign = 64;
3400     DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3401   }
3402   void getTargetDefines(const LangOptions &Opts,
3403                         MacroBuilder &Builder) const override {
3404     WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3405   }
3406 };
3407 
3408 // x86-32 Windows Visual Studio target
3409 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3410 public:
3411   MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3412       : WindowsX86_32TargetInfo(Triple) {
3413     LongDoubleWidth = LongDoubleAlign = 64;
3414     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3415   }
3416   void getTargetDefines(const LangOptions &Opts,
3417                         MacroBuilder &Builder) const override {
3418     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3419     WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3420     // The value of the following reflects processor type.
3421     // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3422     // We lost the original triple, so we use the default.
3423     Builder.defineMacro("_M_IX86", "600");
3424   }
3425 };
3426 } // end anonymous namespace
3427 
3428 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3429   Builder.defineMacro("__MSVCRT__");
3430   Builder.defineMacro("__MINGW32__");
3431 
3432   // Mingw defines __declspec(a) to __attribute__((a)).  Clang supports
3433   // __declspec natively under -fms-extensions, but we define a no-op __declspec
3434   // macro anyway for pre-processor compatibility.
3435   if (Opts.MicrosoftExt)
3436     Builder.defineMacro("__declspec", "__declspec");
3437   else
3438     Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3439 
3440   if (!Opts.MicrosoftExt) {
3441     // Provide macros for all the calling convention keywords.  Provide both
3442     // single and double underscore prefixed variants.  These are available on
3443     // x64 as well as x86, even though they have no effect.
3444     const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3445     for (const char *CC : CCs) {
3446       std::string GCCSpelling = "__attribute__((__";
3447       GCCSpelling += CC;
3448       GCCSpelling += "__))";
3449       Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3450       Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3451     }
3452   }
3453 }
3454 
3455 namespace {
3456 // x86-32 MinGW target
3457 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3458 public:
3459   MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3460       : WindowsX86_32TargetInfo(Triple) {}
3461   void getTargetDefines(const LangOptions &Opts,
3462                         MacroBuilder &Builder) const override {
3463     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3464     DefineStd(Builder, "WIN32", Opts);
3465     DefineStd(Builder, "WINNT", Opts);
3466     Builder.defineMacro("_X86_");
3467     addMinGWDefines(Opts, Builder);
3468   }
3469 };
3470 } // end anonymous namespace
3471 
3472 namespace {
3473 // x86-32 Cygwin target
3474 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3475 public:
3476   CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3477       : X86_32TargetInfo(Triple) {
3478     TLSSupported = false;
3479     WCharType = UnsignedShort;
3480     DoubleAlign = LongLongAlign = 64;
3481     DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3482   }
3483   void getTargetDefines(const LangOptions &Opts,
3484                         MacroBuilder &Builder) const override {
3485     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3486     Builder.defineMacro("_X86_");
3487     Builder.defineMacro("__CYGWIN__");
3488     Builder.defineMacro("__CYGWIN32__");
3489     DefineStd(Builder, "unix", Opts);
3490     if (Opts.CPlusPlus)
3491       Builder.defineMacro("_GNU_SOURCE");
3492   }
3493 };
3494 } // end anonymous namespace
3495 
3496 namespace {
3497 // x86-32 Haiku target
3498 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3499 public:
3500   HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3501     SizeType = UnsignedLong;
3502     IntPtrType = SignedLong;
3503     PtrDiffType = SignedLong;
3504     ProcessIDType = SignedLong;
3505     this->UserLabelPrefix = "";
3506     this->TLSSupported = false;
3507   }
3508   void getTargetDefines(const LangOptions &Opts,
3509                         MacroBuilder &Builder) const override {
3510     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3511     Builder.defineMacro("__INTEL__");
3512     Builder.defineMacro("__HAIKU__");
3513   }
3514 };
3515 } // end anonymous namespace
3516 
3517 // RTEMS Target
3518 template<typename Target>
3519 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3520 protected:
3521   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3522                     MacroBuilder &Builder) const override {
3523     // RTEMS defines; list based off of gcc output
3524 
3525     Builder.defineMacro("__rtems__");
3526     Builder.defineMacro("__ELF__");
3527   }
3528 
3529 public:
3530   RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3531     this->UserLabelPrefix = "";
3532 
3533     switch (Triple.getArch()) {
3534     default:
3535     case llvm::Triple::x86:
3536       // this->MCountName = ".mcount";
3537       break;
3538     case llvm::Triple::mips:
3539     case llvm::Triple::mipsel:
3540     case llvm::Triple::ppc:
3541     case llvm::Triple::ppc64:
3542     case llvm::Triple::ppc64le:
3543       // this->MCountName = "_mcount";
3544       break;
3545     case llvm::Triple::arm:
3546       // this->MCountName = "__mcount";
3547       break;
3548     }
3549   }
3550 };
3551 
3552 namespace {
3553 // x86-32 RTEMS target
3554 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3555 public:
3556   RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3557     SizeType = UnsignedLong;
3558     IntPtrType = SignedLong;
3559     PtrDiffType = SignedLong;
3560     this->UserLabelPrefix = "";
3561   }
3562   void getTargetDefines(const LangOptions &Opts,
3563                         MacroBuilder &Builder) const override {
3564     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3565     Builder.defineMacro("__INTEL__");
3566     Builder.defineMacro("__rtems__");
3567   }
3568 };
3569 } // end anonymous namespace
3570 
3571 namespace {
3572 // x86-64 generic target
3573 class X86_64TargetInfo : public X86TargetInfo {
3574 public:
3575   X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3576     const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3577     LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3578     LongDoubleWidth = 128;
3579     LongDoubleAlign = 128;
3580     LargeArrayMinWidth = 128;
3581     LargeArrayAlign = 128;
3582     SuitableAlign = 128;
3583     SizeType    = IsX32 ? UnsignedInt      : UnsignedLong;
3584     PtrDiffType = IsX32 ? SignedInt        : SignedLong;
3585     IntPtrType  = IsX32 ? SignedInt        : SignedLong;
3586     IntMaxType  = IsX32 ? SignedLongLong   : SignedLong;
3587     Int64Type   = IsX32 ? SignedLongLong   : SignedLong;
3588     RegParmMax = 6;
3589 
3590     // Pointers are 32-bit in x32.
3591     DescriptionString = (IsX32)
3592                             ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3593                             : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3594 
3595     // Use fpret only for long double.
3596     RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3597 
3598     // Use fp2ret for _Complex long double.
3599     ComplexLongDoubleUsesFP2Ret = true;
3600 
3601     // x86-64 has atomics up to 16 bytes.
3602     MaxAtomicPromoteWidth = 128;
3603     MaxAtomicInlineWidth = 128;
3604   }
3605   BuiltinVaListKind getBuiltinVaListKind() const override {
3606     return TargetInfo::X86_64ABIBuiltinVaList;
3607   }
3608 
3609   int getEHDataRegisterNumber(unsigned RegNo) const override {
3610     if (RegNo == 0) return 0;
3611     if (RegNo == 1) return 1;
3612     return -1;
3613   }
3614 
3615   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3616     return (CC == CC_C ||
3617             CC == CC_X86VectorCall ||
3618             CC == CC_IntelOclBicc ||
3619             CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3620   }
3621 
3622   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3623     return CC_C;
3624   }
3625 
3626   // for x32 we need it here explicitly
3627   bool hasInt128Type() const override { return true; }
3628 };
3629 } // end anonymous namespace
3630 
3631 namespace {
3632 // x86-64 Windows target
3633 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3634 public:
3635   WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3636       : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3637     WCharType = UnsignedShort;
3638     LongWidth = LongAlign = 32;
3639     DoubleAlign = LongLongAlign = 64;
3640     IntMaxType = SignedLongLong;
3641     Int64Type = SignedLongLong;
3642     SizeType = UnsignedLongLong;
3643     PtrDiffType = SignedLongLong;
3644     IntPtrType = SignedLongLong;
3645     this->UserLabelPrefix = "";
3646   }
3647 
3648   void getTargetDefines(const LangOptions &Opts,
3649                                 MacroBuilder &Builder) const override {
3650     WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3651     Builder.defineMacro("_WIN64");
3652   }
3653 
3654   BuiltinVaListKind getBuiltinVaListKind() const override {
3655     return TargetInfo::CharPtrBuiltinVaList;
3656   }
3657 
3658   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3659     switch (CC) {
3660     case CC_X86StdCall:
3661     case CC_X86ThisCall:
3662     case CC_X86FastCall:
3663       return CCCR_Ignore;
3664     case CC_C:
3665     case CC_X86VectorCall:
3666     case CC_IntelOclBicc:
3667     case CC_X86_64SysV:
3668       return CCCR_OK;
3669     default:
3670       return CCCR_Warning;
3671     }
3672   }
3673 };
3674 } // end anonymous namespace
3675 
3676 namespace {
3677 // x86-64 Windows Visual Studio target
3678 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3679 public:
3680   MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3681       : WindowsX86_64TargetInfo(Triple) {
3682     LongDoubleWidth = LongDoubleAlign = 64;
3683     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3684   }
3685   void getTargetDefines(const LangOptions &Opts,
3686                         MacroBuilder &Builder) const override {
3687     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3688     WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3689     Builder.defineMacro("_M_X64");
3690     Builder.defineMacro("_M_AMD64");
3691   }
3692 };
3693 } // end anonymous namespace
3694 
3695 namespace {
3696 // x86-64 MinGW target
3697 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3698 public:
3699   MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3700       : WindowsX86_64TargetInfo(Triple) {}
3701   void getTargetDefines(const LangOptions &Opts,
3702                         MacroBuilder &Builder) const override {
3703     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3704     DefineStd(Builder, "WIN64", Opts);
3705     Builder.defineMacro("__MINGW64__");
3706     addMinGWDefines(Opts, Builder);
3707 
3708     // GCC defines this macro when it is using __gxx_personality_seh0.
3709     if (!Opts.SjLjExceptions)
3710       Builder.defineMacro("__SEH__");
3711   }
3712 };
3713 } // end anonymous namespace
3714 
3715 namespace {
3716 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3717 public:
3718   DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3719       : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3720     Int64Type = SignedLongLong;
3721     MaxVectorAlign = 256;
3722     // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3723     llvm::Triple T = llvm::Triple(Triple);
3724     if (T.isiOS())
3725       UseSignedCharForObjCBool = false;
3726     DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3727   }
3728 };
3729 } // end anonymous namespace
3730 
3731 namespace {
3732 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3733 public:
3734   OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3735       : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3736     IntMaxType = SignedLongLong;
3737     Int64Type = SignedLongLong;
3738   }
3739 };
3740 } // end anonymous namespace
3741 
3742 namespace {
3743 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3744 public:
3745   BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3746       : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3747     IntMaxType = SignedLongLong;
3748     Int64Type = SignedLongLong;
3749   }
3750 };
3751 }
3752 
3753 
3754 namespace {
3755 class ARMTargetInfo : public TargetInfo {
3756   // Possible FPU choices.
3757   enum FPUMode {
3758     VFP2FPU = (1 << 0),
3759     VFP3FPU = (1 << 1),
3760     VFP4FPU = (1 << 2),
3761     NeonFPU = (1 << 3),
3762     FPARMV8 = (1 << 4)
3763   };
3764 
3765   // Possible HWDiv features.
3766   enum HWDivMode {
3767     HWDivThumb = (1 << 0),
3768     HWDivARM = (1 << 1)
3769   };
3770 
3771   static bool FPUModeIsVFP(FPUMode Mode) {
3772     return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3773   }
3774 
3775   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3776   static const char * const GCCRegNames[];
3777 
3778   std::string ABI, CPU;
3779 
3780   enum {
3781     FP_Default,
3782     FP_VFP,
3783     FP_Neon
3784   } FPMath;
3785 
3786   unsigned FPU : 5;
3787 
3788   unsigned IsAAPCS : 1;
3789   unsigned IsThumb : 1;
3790   unsigned HWDiv : 2;
3791 
3792   // Initialized via features.
3793   unsigned SoftFloat : 1;
3794   unsigned SoftFloatABI : 1;
3795 
3796   unsigned CRC : 1;
3797   unsigned Crypto : 1;
3798 
3799   // ACLE 6.5.1 Hardware floating point
3800   enum {
3801     HW_FP_HP = (1 << 1), /// half (16-bit)
3802     HW_FP_SP = (1 << 2), /// single (32-bit)
3803     HW_FP_DP = (1 << 3), /// double (64-bit)
3804   };
3805   uint32_t HW_FP;
3806 
3807   static const Builtin::Info BuiltinInfo[];
3808 
3809   static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3810     StringRef ArchName = T.getArchName();
3811     if (T.getArch() == llvm::Triple::arm ||
3812         T.getArch() == llvm::Triple::armeb) {
3813       StringRef VersionStr;
3814       if (ArchName.startswith("armv"))
3815         VersionStr = ArchName.substr(4, 1);
3816       else if (ArchName.startswith("armebv"))
3817         VersionStr = ArchName.substr(6, 1);
3818       else
3819         return false;
3820       unsigned Version;
3821       if (VersionStr.getAsInteger(10, Version))
3822         return false;
3823       return Version >= 6;
3824     }
3825     assert(T.getArch() == llvm::Triple::thumb ||
3826            T.getArch() == llvm::Triple::thumbeb);
3827     StringRef VersionStr;
3828     if (ArchName.startswith("thumbv"))
3829       VersionStr = ArchName.substr(6, 1);
3830     else if (ArchName.startswith("thumbebv"))
3831       VersionStr = ArchName.substr(8, 1);
3832     else
3833       return false;
3834     unsigned Version;
3835     if (VersionStr.getAsInteger(10, Version))
3836       return false;
3837     return Version >= 7;
3838   }
3839 
3840   void setABIAAPCS() {
3841     IsAAPCS = true;
3842 
3843     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
3844     const llvm::Triple &T = getTriple();
3845 
3846     // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig.
3847     if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
3848         T.getOS() == llvm::Triple::Bitrig)
3849       SizeType = UnsignedLong;
3850     else
3851       SizeType = UnsignedInt;
3852 
3853     switch (T.getOS()) {
3854     case llvm::Triple::NetBSD:
3855       WCharType = SignedInt;
3856       break;
3857     case llvm::Triple::Win32:
3858       WCharType = UnsignedShort;
3859       break;
3860     case llvm::Triple::Linux:
3861     default:
3862       // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3863       WCharType = UnsignedInt;
3864       break;
3865     }
3866 
3867     UseBitFieldTypeAlignment = true;
3868 
3869     ZeroLengthBitfieldBoundary = 0;
3870 
3871     // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3872     // so set preferred for small types to 32.
3873     if (T.isOSBinFormatMachO()) {
3874       DescriptionString =
3875           BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3876                     : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3877     } else if (T.isOSWindows()) {
3878       // FIXME: this is invalid for WindowsCE
3879       assert(!BigEndian && "Windows on ARM does not support big endian");
3880       DescriptionString = "e"
3881                           "-m:e"
3882                           "-p:32:32"
3883                           "-i64:64"
3884                           "-v128:64:128"
3885                           "-a:0:32"
3886                           "-n32"
3887                           "-S64";
3888     } else {
3889       DescriptionString =
3890           BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3891                     : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3892     }
3893 
3894     // FIXME: Enumerated types are variable width in straight AAPCS.
3895   }
3896 
3897   void setABIAPCS() {
3898     const llvm::Triple &T = getTriple();
3899 
3900     IsAAPCS = false;
3901 
3902     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3903 
3904     // size_t is unsigned int on FreeBSD.
3905     if (T.getOS() == llvm::Triple::FreeBSD)
3906       SizeType = UnsignedInt;
3907     else
3908       SizeType = UnsignedLong;
3909 
3910     // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3911     WCharType = SignedInt;
3912 
3913     // Do not respect the alignment of bit-field types when laying out
3914     // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3915     UseBitFieldTypeAlignment = false;
3916 
3917     /// gcc forces the alignment to 4 bytes, regardless of the type of the
3918     /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3919     /// gcc.
3920     ZeroLengthBitfieldBoundary = 32;
3921 
3922     if (T.isOSBinFormatMachO())
3923       DescriptionString =
3924           BigEndian
3925               ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3926               : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3927     else
3928       DescriptionString =
3929           BigEndian
3930               ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3931               : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3932 
3933     // FIXME: Override "preferred align" for double and long long.
3934   }
3935 
3936 public:
3937   ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
3938       : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
3939         IsAAPCS(true), HW_FP(0) {
3940     BigEndian = IsBigEndian;
3941 
3942     switch (getTriple().getOS()) {
3943     case llvm::Triple::NetBSD:
3944       PtrDiffType = SignedLong;
3945       break;
3946     default:
3947       PtrDiffType = SignedInt;
3948       break;
3949     }
3950 
3951     // {} in inline assembly are neon specifiers, not assembly variant
3952     // specifiers.
3953     NoAsmVariants = true;
3954 
3955     // FIXME: Should we just treat this as a feature?
3956     IsThumb = getTriple().getArchName().startswith("thumb");
3957 
3958     // FIXME: This duplicates code from the driver that sets the -target-abi
3959     // option - this code is used if -target-abi isn't passed and should
3960     // be unified in some way.
3961     if (Triple.isOSBinFormatMachO()) {
3962       // The backend is hardwired to assume AAPCS for M-class processors, ensure
3963       // the frontend matches that.
3964       if (Triple.getEnvironment() == llvm::Triple::EABI ||
3965           Triple.getOS() == llvm::Triple::UnknownOS ||
3966           StringRef(CPU).startswith("cortex-m")) {
3967         setABI("aapcs");
3968       } else {
3969         setABI("apcs-gnu");
3970       }
3971     } else if (Triple.isOSWindows()) {
3972       // FIXME: this is invalid for WindowsCE
3973       setABI("aapcs");
3974     } else {
3975       // Select the default based on the platform.
3976       switch (Triple.getEnvironment()) {
3977       case llvm::Triple::Android:
3978       case llvm::Triple::GNUEABI:
3979       case llvm::Triple::GNUEABIHF:
3980         setABI("aapcs-linux");
3981         break;
3982       case llvm::Triple::EABIHF:
3983       case llvm::Triple::EABI:
3984         setABI("aapcs");
3985         break;
3986       case llvm::Triple::GNU:
3987 	setABI("apcs-gnu");
3988 	break;
3989       default:
3990         if (Triple.getOS() == llvm::Triple::NetBSD)
3991           setABI("apcs-gnu");
3992         else
3993           setABI("aapcs");
3994         break;
3995       }
3996     }
3997 
3998     // ARM targets default to using the ARM C++ ABI.
3999     TheCXXABI.set(TargetCXXABI::GenericARM);
4000 
4001     // ARM has atomics up to 8 bytes
4002     MaxAtomicPromoteWidth = 64;
4003     if (shouldUseInlineAtomic(getTriple()))
4004       MaxAtomicInlineWidth = 64;
4005 
4006     // Do force alignment of members that follow zero length bitfields.  If
4007     // the alignment of the zero-length bitfield is greater than the member
4008     // that follows it, `bar', `bar' will be aligned as the  type of the
4009     // zero length bitfield.
4010     UseZeroLengthBitfieldAlignment = true;
4011   }
4012   StringRef getABI() const override { return ABI; }
4013   bool setABI(const std::string &Name) override {
4014     ABI = Name;
4015 
4016     // The defaults (above) are for AAPCS, check if we need to change them.
4017     //
4018     // FIXME: We need support for -meabi... we could just mangle it into the
4019     // name.
4020     if (Name == "apcs-gnu") {
4021       setABIAPCS();
4022       return true;
4023     }
4024     if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
4025       setABIAAPCS();
4026       return true;
4027     }
4028     return false;
4029   }
4030 
4031   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
4032     StringRef ArchName = getTriple().getArchName();
4033     if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
4034       Features["vfp2"] = true;
4035     else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
4036       Features["vfp3"] = true;
4037       Features["neon"] = true;
4038     }
4039     else if (CPU == "cortex-a5") {
4040       Features["vfp4"] = true;
4041       Features["neon"] = true;
4042     } else if (CPU == "swift" || CPU == "cortex-a7" ||
4043                CPU == "cortex-a12" || CPU == "cortex-a15" ||
4044                CPU == "cortex-a17" || CPU == "krait") {
4045       Features["vfp4"] = true;
4046       Features["neon"] = true;
4047       Features["hwdiv"] = true;
4048       Features["hwdiv-arm"] = true;
4049     } else if (CPU == "cyclone") {
4050       Features["v8fp"] = true;
4051       Features["neon"] = true;
4052       Features["hwdiv"] = true;
4053       Features["hwdiv-arm"] = true;
4054     } else if (CPU == "cortex-a53" || CPU == "cortex-a57" || CPU == "cortex-a72") {
4055       Features["fp-armv8"] = true;
4056       Features["neon"] = true;
4057       Features["hwdiv"] = true;
4058       Features["hwdiv-arm"] = true;
4059       Features["crc"] = true;
4060       Features["crypto"] = true;
4061     } else if (CPU == "cortex-r5" || CPU == "cortex-r7" ||
4062                // Enable the hwdiv extension for all v8a AArch32 cores by
4063                // default.
4064                ArchName == "armv8a" || ArchName == "armv8" ||
4065                ArchName == "armebv8a" || ArchName == "armebv8" ||
4066                ArchName == "thumbv8a" || ArchName == "thumbv8" ||
4067                ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
4068       Features["hwdiv"] = true;
4069       Features["hwdiv-arm"] = true;
4070     } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" ||
4071                CPU == "sc300") {
4072       Features["hwdiv"] = true;
4073     }
4074   }
4075 
4076   bool handleTargetFeatures(std::vector<std::string> &Features,
4077                             DiagnosticsEngine &Diags) override {
4078     FPU = 0;
4079     CRC = 0;
4080     Crypto = 0;
4081     SoftFloat = SoftFloatABI = false;
4082     HWDiv = 0;
4083 
4084     for (const auto &Feature : Features) {
4085       if (Feature == "+soft-float") {
4086         SoftFloat = true;
4087       } else if (Feature == "+soft-float-abi") {
4088         SoftFloatABI = true;
4089       } else if (Feature == "+vfp2") {
4090         FPU |= VFP2FPU;
4091         HW_FP = HW_FP_SP | HW_FP_DP;
4092       } else if (Feature == "+vfp3") {
4093         FPU |= VFP3FPU;
4094         HW_FP = HW_FP_SP | HW_FP_DP;
4095       } else if (Feature == "+vfp4") {
4096         FPU |= VFP4FPU;
4097         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4098       } else if (Feature == "+fp-armv8") {
4099         FPU |= FPARMV8;
4100         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4101       } else if (Feature == "+neon") {
4102         FPU |= NeonFPU;
4103         HW_FP = HW_FP_SP | HW_FP_DP;
4104       } else if (Feature == "+hwdiv") {
4105         HWDiv |= HWDivThumb;
4106       } else if (Feature == "+hwdiv-arm") {
4107         HWDiv |= HWDivARM;
4108       } else if (Feature == "+crc") {
4109         CRC = 1;
4110       } else if (Feature == "+crypto") {
4111         Crypto = 1;
4112       } else if (Feature == "+fp-only-sp") {
4113         HW_FP &= ~HW_FP_DP;
4114       }
4115     }
4116 
4117     if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4118       Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4119       return false;
4120     }
4121 
4122     if (FPMath == FP_Neon)
4123       Features.push_back("+neonfp");
4124     else if (FPMath == FP_VFP)
4125       Features.push_back("-neonfp");
4126 
4127     // Remove front-end specific options which the backend handles differently.
4128     const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" };
4129     for (const auto &FEFeature : FrontEndFeatures) {
4130       auto Feature = std::find(Features.begin(), Features.end(), FEFeature);
4131       if (Feature != Features.end())
4132         Features.erase(Feature);
4133     }
4134 
4135     return true;
4136   }
4137 
4138   bool hasFeature(StringRef Feature) const override {
4139     return llvm::StringSwitch<bool>(Feature)
4140         .Case("arm", true)
4141         .Case("softfloat", SoftFloat)
4142         .Case("thumb", IsThumb)
4143         .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4144         .Case("hwdiv", HWDiv & HWDivThumb)
4145         .Case("hwdiv-arm", HWDiv & HWDivARM)
4146         .Default(false);
4147   }
4148   // FIXME: Should we actually have some table instead of these switches?
4149   static const char *getCPUDefineSuffix(StringRef Name) {
4150     return llvm::StringSwitch<const char *>(Name)
4151         .Cases("arm8", "arm810", "4")
4152         .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110",
4153                "4")
4154         .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
4155         .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
4156         .Case("ep9312", "4T")
4157         .Cases("arm10tdmi", "arm1020t", "5T")
4158         .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
4159         .Case("arm926ej-s", "5TEJ")
4160         .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
4161         .Cases("xscale", "iwmmxt", "5TE")
4162         .Case("arm1136j-s", "6J")
4163         .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
4164         .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
4165         .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
4166         .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
4167         .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4168                "7A")
4169         .Cases("cortex-r4", "cortex-r5", "cortex-r7", "7R")
4170         .Case("swift", "7S")
4171         .Case("cyclone", "8A")
4172         .Cases("sc300", "cortex-m3", "7M")
4173         .Cases("cortex-m4", "cortex-m7", "7EM")
4174         .Cases("sc000", "cortex-m0", "cortex-m0plus", "cortex-m1", "6M")
4175         .Cases("cortex-a53", "cortex-a57", "cortex-a72", "8A")
4176         .Default(nullptr);
4177   }
4178   static const char *getCPUProfile(StringRef Name) {
4179     return llvm::StringSwitch<const char *>(Name)
4180         .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
4181         .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4182                "A")
4183         .Cases("cortex-a53", "cortex-a57", "cortex-a72", "A")
4184         .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m0plus", "M")
4185         .Cases("cortex-m1", "cortex-m7", "sc000", "sc300", "M")
4186         .Cases("cortex-r4", "cortex-r5", "cortex-r7", "R")
4187         .Default("");
4188   }
4189   bool setCPU(const std::string &Name) override {
4190     if (!getCPUDefineSuffix(Name))
4191       return false;
4192 
4193     // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4194     StringRef Profile = getCPUProfile(Name);
4195     if (Profile == "M" && MaxAtomicInlineWidth) {
4196       MaxAtomicPromoteWidth = 32;
4197       MaxAtomicInlineWidth = 32;
4198     }
4199 
4200     CPU = Name;
4201     return true;
4202   }
4203   bool setFPMath(StringRef Name) override;
4204   bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4205                      unsigned CPUArchVer) const {
4206     return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4207            (CPUArch.find('M') != StringRef::npos);
4208   }
4209   bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4210                       unsigned CPUArchVer) const {
4211     // We check both CPUArchVer and ArchName because when only triple is
4212     // specified, the default CPU is arm1136j-s.
4213     return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4214            ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4215   }
4216   void getTargetDefines(const LangOptions &Opts,
4217                         MacroBuilder &Builder) const override {
4218     // Target identification.
4219     Builder.defineMacro("__arm");
4220     Builder.defineMacro("__arm__");
4221 
4222     // Target properties.
4223     Builder.defineMacro("__REGISTER_PREFIX__", "");
4224 
4225     StringRef CPUArch = getCPUDefineSuffix(CPU);
4226     unsigned int CPUArchVer;
4227     if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4228       llvm_unreachable("Invalid char for architecture version number");
4229     Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4230 
4231     // ACLE 6.4.1 ARM/Thumb instruction set architecture
4232     StringRef CPUProfile = getCPUProfile(CPU);
4233     StringRef ArchName = getTriple().getArchName();
4234 
4235     // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4236     Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4237     if (CPUArch[0] >= '8') {
4238       Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4239       Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4240     }
4241 
4242     // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
4243     // is not defined for the M-profile.
4244     // NOTE that the deffault profile is assumed to be 'A'
4245     if (CPUProfile.empty() || CPUProfile != "M")
4246       Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4247 
4248     // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4249     // Thumb ISA (including v6-M).  It is set to 2 if the core supports the
4250     // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4251     if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4252       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4253     else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4254       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4255 
4256     // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4257     // instruction set such as ARM or Thumb.
4258     Builder.defineMacro("__ARM_32BIT_STATE", "1");
4259 
4260     // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4261 
4262     // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4263     if (!CPUProfile.empty())
4264       Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4265 
4266     // ACLE 6.5.1 Hardware Floating Point
4267     if (HW_FP)
4268       Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4269 
4270     // ACLE predefines.
4271     Builder.defineMacro("__ARM_ACLE", "200");
4272 
4273     // Subtarget options.
4274 
4275     // FIXME: It's more complicated than this and we don't really support
4276     // interworking.
4277     // Windows on ARM does not "support" interworking
4278     if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4279       Builder.defineMacro("__THUMB_INTERWORK__");
4280 
4281     if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4282       // Embedded targets on Darwin follow AAPCS, but not EABI.
4283       // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4284       if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4285         Builder.defineMacro("__ARM_EABI__");
4286       Builder.defineMacro("__ARM_PCS", "1");
4287 
4288       if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4289         Builder.defineMacro("__ARM_PCS_VFP", "1");
4290     }
4291 
4292     if (SoftFloat)
4293       Builder.defineMacro("__SOFTFP__");
4294 
4295     if (CPU == "xscale")
4296       Builder.defineMacro("__XSCALE__");
4297 
4298     if (IsThumb) {
4299       Builder.defineMacro("__THUMBEL__");
4300       Builder.defineMacro("__thumb__");
4301       if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4302         Builder.defineMacro("__thumb2__");
4303     }
4304     if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4305       Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4306 
4307     // Note, this is always on in gcc, even though it doesn't make sense.
4308     Builder.defineMacro("__APCS_32__");
4309 
4310     if (FPUModeIsVFP((FPUMode) FPU)) {
4311       Builder.defineMacro("__VFP_FP__");
4312       if (FPU & VFP2FPU)
4313         Builder.defineMacro("__ARM_VFPV2__");
4314       if (FPU & VFP3FPU)
4315         Builder.defineMacro("__ARM_VFPV3__");
4316       if (FPU & VFP4FPU)
4317         Builder.defineMacro("__ARM_VFPV4__");
4318     }
4319 
4320     // This only gets set when Neon instructions are actually available, unlike
4321     // the VFP define, hence the soft float and arch check. This is subtly
4322     // different from gcc, we follow the intent which was that it should be set
4323     // when Neon instructions are actually available.
4324     if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4325       Builder.defineMacro("__ARM_NEON");
4326       Builder.defineMacro("__ARM_NEON__");
4327     }
4328 
4329     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4330                         Opts.ShortWChar ? "2" : "4");
4331 
4332     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4333                         Opts.ShortEnums ? "1" : "4");
4334 
4335     if (CRC)
4336       Builder.defineMacro("__ARM_FEATURE_CRC32");
4337 
4338     if (Crypto)
4339       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4340 
4341     if (CPUArchVer >= 6 && CPUArch != "6M") {
4342       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4343       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4344       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4345       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4346     }
4347 
4348     bool is5EOrAbove = (CPUArchVer >= 6 ||
4349                         (CPUArchVer == 5 &&
4350                          CPUArch.find('E') != StringRef::npos));
4351     bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
4352     if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch  == "7EM"))
4353       Builder.defineMacro("__ARM_FEATURE_DSP");
4354   }
4355   void getTargetBuiltins(const Builtin::Info *&Records,
4356                          unsigned &NumRecords) const override {
4357     Records = BuiltinInfo;
4358     NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4359   }
4360   bool isCLZForZeroUndef() const override { return false; }
4361   BuiltinVaListKind getBuiltinVaListKind() const override {
4362     return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4363   }
4364   void getGCCRegNames(const char * const *&Names,
4365                       unsigned &NumNames) const override;
4366   void getGCCRegAliases(const GCCRegAlias *&Aliases,
4367                         unsigned &NumAliases) const override;
4368   bool validateAsmConstraint(const char *&Name,
4369                              TargetInfo::ConstraintInfo &Info) const override {
4370     switch (*Name) {
4371     default: break;
4372     case 'l': // r0-r7
4373     case 'h': // r8-r15
4374     case 'w': // VFP Floating point register single precision
4375     case 'P': // VFP Floating point register double precision
4376       Info.setAllowsRegister();
4377       return true;
4378     case 'I':
4379     case 'J':
4380     case 'K':
4381     case 'L':
4382     case 'M':
4383       // FIXME
4384       return true;
4385     case 'Q': // A memory address that is a single base register.
4386       Info.setAllowsMemory();
4387       return true;
4388     case 'U': // a memory reference...
4389       switch (Name[1]) {
4390       case 'q': // ...ARMV4 ldrsb
4391       case 'v': // ...VFP load/store (reg+constant offset)
4392       case 'y': // ...iWMMXt load/store
4393       case 't': // address valid for load/store opaque types wider
4394                 // than 128-bits
4395       case 'n': // valid address for Neon doubleword vector load/store
4396       case 'm': // valid address for Neon element and structure load/store
4397       case 's': // valid address for non-offset loads/stores of quad-word
4398                 // values in four ARM registers
4399         Info.setAllowsMemory();
4400         Name++;
4401         return true;
4402       }
4403     }
4404     return false;
4405   }
4406   std::string convertConstraint(const char *&Constraint) const override {
4407     std::string R;
4408     switch (*Constraint) {
4409     case 'U':   // Two-character constraint; add "^" hint for later parsing.
4410       R = std::string("^") + std::string(Constraint, 2);
4411       Constraint++;
4412       break;
4413     case 'p': // 'p' should be translated to 'r' by default.
4414       R = std::string("r");
4415       break;
4416     default:
4417       return std::string(1, *Constraint);
4418     }
4419     return R;
4420   }
4421   bool
4422   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4423                              std::string &SuggestedModifier) const override {
4424     bool isOutput = (Constraint[0] == '=');
4425     bool isInOut = (Constraint[0] == '+');
4426 
4427     // Strip off constraint modifiers.
4428     while (Constraint[0] == '=' ||
4429            Constraint[0] == '+' ||
4430            Constraint[0] == '&')
4431       Constraint = Constraint.substr(1);
4432 
4433     switch (Constraint[0]) {
4434     default: break;
4435     case 'r': {
4436       switch (Modifier) {
4437       default:
4438         return (isInOut || isOutput || Size <= 64);
4439       case 'q':
4440         // A register of size 32 cannot fit a vector type.
4441         return false;
4442       }
4443     }
4444     }
4445 
4446     return true;
4447   }
4448   const char *getClobbers() const override {
4449     // FIXME: Is this really right?
4450     return "";
4451   }
4452 
4453   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4454     return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4455   }
4456 
4457   int getEHDataRegisterNumber(unsigned RegNo) const override {
4458     if (RegNo == 0) return 0;
4459     if (RegNo == 1) return 1;
4460     return -1;
4461   }
4462 };
4463 
4464 bool ARMTargetInfo::setFPMath(StringRef Name) {
4465   if (Name == "neon") {
4466     FPMath = FP_Neon;
4467     return true;
4468   } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4469              Name == "vfp4") {
4470     FPMath = FP_VFP;
4471     return true;
4472   }
4473   return false;
4474 }
4475 
4476 const char * const ARMTargetInfo::GCCRegNames[] = {
4477   // Integer registers
4478   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4479   "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4480 
4481   // Float registers
4482   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4483   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4484   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4485   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4486 
4487   // Double registers
4488   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4489   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4490   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4491   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4492 
4493   // Quad registers
4494   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4495   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4496 };
4497 
4498 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4499                                    unsigned &NumNames) const {
4500   Names = GCCRegNames;
4501   NumNames = llvm::array_lengthof(GCCRegNames);
4502 }
4503 
4504 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4505   { { "a1" }, "r0" },
4506   { { "a2" }, "r1" },
4507   { { "a3" }, "r2" },
4508   { { "a4" }, "r3" },
4509   { { "v1" }, "r4" },
4510   { { "v2" }, "r5" },
4511   { { "v3" }, "r6" },
4512   { { "v4" }, "r7" },
4513   { { "v5" }, "r8" },
4514   { { "v6", "rfp" }, "r9" },
4515   { { "sl" }, "r10" },
4516   { { "fp" }, "r11" },
4517   { { "ip" }, "r12" },
4518   { { "r13" }, "sp" },
4519   { { "r14" }, "lr" },
4520   { { "r15" }, "pc" },
4521   // The S, D and Q registers overlap, but aren't really aliases; we
4522   // don't want to substitute one of these for a different-sized one.
4523 };
4524 
4525 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4526                                        unsigned &NumAliases) const {
4527   Aliases = GCCRegAliases;
4528   NumAliases = llvm::array_lengthof(GCCRegAliases);
4529 }
4530 
4531 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4532 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4533 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4534                                               ALL_LANGUAGES },
4535 #include "clang/Basic/BuiltinsNEON.def"
4536 
4537 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4538 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4539 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4540                                               ALL_LANGUAGES },
4541 #include "clang/Basic/BuiltinsARM.def"
4542 };
4543 
4544 class ARMleTargetInfo : public ARMTargetInfo {
4545 public:
4546   ARMleTargetInfo(const llvm::Triple &Triple)
4547     : ARMTargetInfo(Triple, false) { }
4548   virtual void getTargetDefines(const LangOptions &Opts,
4549                                 MacroBuilder &Builder) const {
4550     Builder.defineMacro("__ARMEL__");
4551     ARMTargetInfo::getTargetDefines(Opts, Builder);
4552   }
4553 };
4554 
4555 class ARMbeTargetInfo : public ARMTargetInfo {
4556 public:
4557   ARMbeTargetInfo(const llvm::Triple &Triple)
4558     : ARMTargetInfo(Triple, true) { }
4559   virtual void getTargetDefines(const LangOptions &Opts,
4560                                 MacroBuilder &Builder) const {
4561     Builder.defineMacro("__ARMEB__");
4562     Builder.defineMacro("__ARM_BIG_ENDIAN");
4563     ARMTargetInfo::getTargetDefines(Opts, Builder);
4564   }
4565 };
4566 } // end anonymous namespace.
4567 
4568 namespace {
4569 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4570   const llvm::Triple Triple;
4571 public:
4572   WindowsARMTargetInfo(const llvm::Triple &Triple)
4573     : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4574     TLSSupported = false;
4575     WCharType = UnsignedShort;
4576     SizeType = UnsignedInt;
4577     UserLabelPrefix = "";
4578   }
4579   void getVisualStudioDefines(const LangOptions &Opts,
4580                               MacroBuilder &Builder) const {
4581     WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4582 
4583     // FIXME: this is invalid for WindowsCE
4584     Builder.defineMacro("_M_ARM_NT", "1");
4585     Builder.defineMacro("_M_ARMT", "_M_ARM");
4586     Builder.defineMacro("_M_THUMB", "_M_ARM");
4587 
4588     assert((Triple.getArch() == llvm::Triple::arm ||
4589             Triple.getArch() == llvm::Triple::thumb) &&
4590            "invalid architecture for Windows ARM target info");
4591     unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4592     Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4593 
4594     // TODO map the complete set of values
4595     // 31: VFPv3 40: VFPv4
4596     Builder.defineMacro("_M_ARM_FP", "31");
4597   }
4598   BuiltinVaListKind getBuiltinVaListKind() const override {
4599     return TargetInfo::CharPtrBuiltinVaList;
4600   }
4601 };
4602 
4603 // Windows ARM + Itanium C++ ABI Target
4604 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4605 public:
4606   ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4607     : WindowsARMTargetInfo(Triple) {
4608     TheCXXABI.set(TargetCXXABI::GenericARM);
4609   }
4610 
4611   void getTargetDefines(const LangOptions &Opts,
4612                         MacroBuilder &Builder) const override {
4613     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4614 
4615     if (Opts.MSVCCompat)
4616       WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4617   }
4618 };
4619 
4620 // Windows ARM, MS (C++) ABI
4621 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4622 public:
4623   MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4624     : WindowsARMTargetInfo(Triple) {
4625     TheCXXABI.set(TargetCXXABI::Microsoft);
4626   }
4627 
4628   void getTargetDefines(const LangOptions &Opts,
4629                         MacroBuilder &Builder) const override {
4630     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4631     WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4632   }
4633 };
4634 }
4635 
4636 
4637 namespace {
4638 class DarwinARMTargetInfo :
4639   public DarwinTargetInfo<ARMleTargetInfo> {
4640 protected:
4641   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4642                     MacroBuilder &Builder) const override {
4643     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4644   }
4645 
4646 public:
4647   DarwinARMTargetInfo(const llvm::Triple &Triple)
4648       : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4649     HasAlignMac68kSupport = true;
4650     // iOS always has 64-bit atomic instructions.
4651     // FIXME: This should be based off of the target features in
4652     // ARMleTargetInfo.
4653     MaxAtomicInlineWidth = 64;
4654 
4655     // Darwin on iOS uses a variant of the ARM C++ ABI.
4656     TheCXXABI.set(TargetCXXABI::iOS);
4657   }
4658 };
4659 } // end anonymous namespace.
4660 
4661 
4662 namespace {
4663 class AArch64TargetInfo : public TargetInfo {
4664   virtual void setDescriptionString() = 0;
4665   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4666   static const char *const GCCRegNames[];
4667 
4668   enum FPUModeEnum {
4669     FPUMode,
4670     NeonMode
4671   };
4672 
4673   unsigned FPU;
4674   unsigned CRC;
4675   unsigned Crypto;
4676 
4677   static const Builtin::Info BuiltinInfo[];
4678 
4679   std::string ABI;
4680 
4681 public:
4682   AArch64TargetInfo(const llvm::Triple &Triple)
4683       : TargetInfo(Triple), ABI("aapcs") {
4684 
4685     if (getTriple().getOS() == llvm::Triple::NetBSD) {
4686       WCharType = SignedInt;
4687 
4688       // NetBSD apparently prefers consistency across ARM targets to consistency
4689       // across 64-bit targets.
4690       Int64Type = SignedLongLong;
4691       IntMaxType = SignedLongLong;
4692     } else {
4693       WCharType = UnsignedInt;
4694       Int64Type = SignedLong;
4695       IntMaxType = SignedLong;
4696     }
4697 
4698     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4699     MaxVectorAlign = 128;
4700     RegParmMax = 8;
4701     MaxAtomicInlineWidth = 128;
4702     MaxAtomicPromoteWidth = 128;
4703 
4704     LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
4705     LongDoubleFormat = &llvm::APFloat::IEEEquad;
4706 
4707     // {} in inline assembly are neon specifiers, not assembly variant
4708     // specifiers.
4709     NoAsmVariants = true;
4710 
4711     // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
4712     // contributes to the alignment of the containing aggregate in the same way
4713     // a plain (non bit-field) member of that type would, without exception for
4714     // zero-sized or anonymous bit-fields."
4715     UseBitFieldTypeAlignment = true;
4716     UseZeroLengthBitfieldAlignment = true;
4717 
4718     // AArch64 targets default to using the ARM C++ ABI.
4719     TheCXXABI.set(TargetCXXABI::GenericAArch64);
4720   }
4721 
4722   StringRef getABI() const override { return ABI; }
4723   bool setABI(const std::string &Name) override {
4724     if (Name != "aapcs" && Name != "darwinpcs")
4725       return false;
4726 
4727     ABI = Name;
4728     return true;
4729   }
4730 
4731   bool setCPU(const std::string &Name) override {
4732     bool CPUKnown = llvm::StringSwitch<bool>(Name)
4733                         .Case("generic", true)
4734                         .Cases("cortex-a53", "cortex-a57", "cortex-a72", true)
4735                         .Case("cyclone", true)
4736                         .Default(false);
4737     return CPUKnown;
4738   }
4739 
4740   virtual void getTargetDefines(const LangOptions &Opts,
4741                                 MacroBuilder &Builder) const  override {
4742     // Target identification.
4743     Builder.defineMacro("__aarch64__");
4744 
4745     // Target properties.
4746     Builder.defineMacro("_LP64");
4747     Builder.defineMacro("__LP64__");
4748 
4749     // ACLE predefines. Many can only have one possible value on v8 AArch64.
4750     Builder.defineMacro("__ARM_ACLE", "200");
4751     Builder.defineMacro("__ARM_ARCH", "8");
4752     Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4753 
4754     Builder.defineMacro("__ARM_64BIT_STATE");
4755     Builder.defineMacro("__ARM_PCS_AAPCS64");
4756     Builder.defineMacro("__ARM_ARCH_ISA_A64");
4757 
4758     Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4759     Builder.defineMacro("__ARM_FEATURE_CLZ");
4760     Builder.defineMacro("__ARM_FEATURE_FMA");
4761     Builder.defineMacro("__ARM_FEATURE_DIV");
4762     Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
4763     Builder.defineMacro("__ARM_FEATURE_DIV");  // For backwards compatibility
4764     Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4765     Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4766 
4767     Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4768 
4769     // 0xe implies support for half, single and double precision operations.
4770     Builder.defineMacro("__ARM_FP", "0xe");
4771 
4772     // PCS specifies this for SysV variants, which is all we support. Other ABIs
4773     // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4774     Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4775 
4776     if (Opts.FastMath || Opts.FiniteMathOnly)
4777       Builder.defineMacro("__ARM_FP_FAST");
4778 
4779     if (Opts.C99 && !Opts.Freestanding)
4780       Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4781 
4782     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4783 
4784     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4785                         Opts.ShortEnums ? "1" : "4");
4786 
4787     if (FPU == NeonMode) {
4788       Builder.defineMacro("__ARM_NEON");
4789       // 64-bit NEON supports half, single and double precision operations.
4790       Builder.defineMacro("__ARM_NEON_FP", "0xe");
4791     }
4792 
4793     if (CRC)
4794       Builder.defineMacro("__ARM_FEATURE_CRC32");
4795 
4796     if (Crypto)
4797       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4798   }
4799 
4800   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4801                                  unsigned &NumRecords) const override {
4802     Records = BuiltinInfo;
4803     NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4804   }
4805 
4806   bool hasFeature(StringRef Feature) const override {
4807     return Feature == "aarch64" ||
4808       Feature == "arm64" ||
4809       (Feature == "neon" && FPU == NeonMode);
4810   }
4811 
4812   bool handleTargetFeatures(std::vector<std::string> &Features,
4813                             DiagnosticsEngine &Diags) override {
4814     FPU = FPUMode;
4815     CRC = 0;
4816     Crypto = 0;
4817     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
4818       if (Features[i] == "+neon")
4819         FPU = NeonMode;
4820       if (Features[i] == "+crc")
4821         CRC = 1;
4822       if (Features[i] == "+crypto")
4823         Crypto = 1;
4824     }
4825 
4826     setDescriptionString();
4827 
4828     return true;
4829   }
4830 
4831   bool isCLZForZeroUndef() const override { return false; }
4832 
4833   BuiltinVaListKind getBuiltinVaListKind() const override {
4834     return TargetInfo::AArch64ABIBuiltinVaList;
4835   }
4836 
4837   virtual void getGCCRegNames(const char *const *&Names,
4838                               unsigned &NumNames) const override;
4839   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4840                                 unsigned &NumAliases) const override;
4841 
4842   virtual bool
4843   validateAsmConstraint(const char *&Name,
4844                         TargetInfo::ConstraintInfo &Info) const override {
4845     switch (*Name) {
4846     default:
4847       return false;
4848     case 'w': // Floating point and SIMD registers (V0-V31)
4849       Info.setAllowsRegister();
4850       return true;
4851     case 'I': // Constant that can be used with an ADD instruction
4852     case 'J': // Constant that can be used with a SUB instruction
4853     case 'K': // Constant that can be used with a 32-bit logical instruction
4854     case 'L': // Constant that can be used with a 64-bit logical instruction
4855     case 'M': // Constant that can be used as a 32-bit MOV immediate
4856     case 'N': // Constant that can be used as a 64-bit MOV immediate
4857     case 'Y': // Floating point constant zero
4858     case 'Z': // Integer constant zero
4859       return true;
4860     case 'Q': // A memory reference with base register and no offset
4861       Info.setAllowsMemory();
4862       return true;
4863     case 'S': // A symbolic address
4864       Info.setAllowsRegister();
4865       return true;
4866     case 'U':
4867       // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
4868       // Utf: A memory address suitable for ldp/stp in TF mode.
4869       // Usa: An absolute symbolic address.
4870       // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
4871       llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
4872     case 'z': // Zero register, wzr or xzr
4873       Info.setAllowsRegister();
4874       return true;
4875     case 'x': // Floating point and SIMD registers (V0-V15)
4876       Info.setAllowsRegister();
4877       return true;
4878     }
4879     return false;
4880   }
4881 
4882   bool
4883   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4884                              std::string &SuggestedModifier) const override {
4885     // Strip off constraint modifiers.
4886     while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
4887       Constraint = Constraint.substr(1);
4888 
4889     switch (Constraint[0]) {
4890     default:
4891       return true;
4892     case 'z':
4893     case 'r': {
4894       switch (Modifier) {
4895       case 'x':
4896       case 'w':
4897         // For now assume that the person knows what they're
4898         // doing with the modifier.
4899         return true;
4900       default:
4901         // By default an 'r' constraint will be in the 'x'
4902         // registers.
4903         if (Size == 64)
4904           return true;
4905 
4906         SuggestedModifier = "w";
4907         return false;
4908       }
4909     }
4910     }
4911   }
4912 
4913   const char *getClobbers() const override { return ""; }
4914 
4915   int getEHDataRegisterNumber(unsigned RegNo) const override {
4916     if (RegNo == 0)
4917       return 0;
4918     if (RegNo == 1)
4919       return 1;
4920     return -1;
4921   }
4922 };
4923 
4924 const char *const AArch64TargetInfo::GCCRegNames[] = {
4925   // 32-bit Integer registers
4926   "w0",  "w1",  "w2",  "w3",  "w4",  "w5",  "w6",  "w7",  "w8",  "w9",  "w10",
4927   "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
4928   "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
4929 
4930   // 64-bit Integer registers
4931   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",  "x8",  "x9",  "x10",
4932   "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
4933   "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp",  "lr",  "sp",
4934 
4935   // 32-bit floating point regsisters
4936   "s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",  "s8",  "s9",  "s10",
4937   "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
4938   "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4939 
4940   // 64-bit floating point regsisters
4941   "d0",  "d1",  "d2",  "d3",  "d4",  "d5",  "d6",  "d7",  "d8",  "d9",  "d10",
4942   "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
4943   "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4944 
4945   // Vector registers
4946   "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",  "v8",  "v9",  "v10",
4947   "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
4948   "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
4949 };
4950 
4951 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
4952                                      unsigned &NumNames) const {
4953   Names = GCCRegNames;
4954   NumNames = llvm::array_lengthof(GCCRegNames);
4955 }
4956 
4957 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
4958   { { "w31" }, "wsp" },
4959   { { "x29" }, "fp" },
4960   { { "x30" }, "lr" },
4961   { { "x31" }, "sp" },
4962   // The S/D/Q and W/X registers overlap, but aren't really aliases; we
4963   // don't want to substitute one of these for a different-sized one.
4964 };
4965 
4966 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4967                                        unsigned &NumAliases) const {
4968   Aliases = GCCRegAliases;
4969   NumAliases = llvm::array_lengthof(GCCRegAliases);
4970 }
4971 
4972 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
4973 #define BUILTIN(ID, TYPE, ATTRS)                                               \
4974   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4975 #include "clang/Basic/BuiltinsNEON.def"
4976 
4977 #define BUILTIN(ID, TYPE, ATTRS)                                               \
4978   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4979 #include "clang/Basic/BuiltinsAArch64.def"
4980 };
4981 
4982 class AArch64leTargetInfo : public AArch64TargetInfo {
4983   void setDescriptionString() override {
4984     if (getTriple().isOSBinFormatMachO())
4985       DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
4986     else
4987       DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
4988   }
4989 
4990 public:
4991   AArch64leTargetInfo(const llvm::Triple &Triple)
4992     : AArch64TargetInfo(Triple) {
4993     BigEndian = false;
4994     }
4995   void getTargetDefines(const LangOptions &Opts,
4996                         MacroBuilder &Builder) const override {
4997     Builder.defineMacro("__AARCH64EL__");
4998     AArch64TargetInfo::getTargetDefines(Opts, Builder);
4999   }
5000 };
5001 
5002 class AArch64beTargetInfo : public AArch64TargetInfo {
5003   void setDescriptionString() override {
5004     assert(!getTriple().isOSBinFormatMachO());
5005     DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
5006   }
5007 
5008 public:
5009   AArch64beTargetInfo(const llvm::Triple &Triple)
5010     : AArch64TargetInfo(Triple) { }
5011   void getTargetDefines(const LangOptions &Opts,
5012                         MacroBuilder &Builder) const override {
5013     Builder.defineMacro("__AARCH64EB__");
5014     Builder.defineMacro("__AARCH_BIG_ENDIAN");
5015     Builder.defineMacro("__ARM_BIG_ENDIAN");
5016     AArch64TargetInfo::getTargetDefines(Opts, Builder);
5017   }
5018 };
5019 } // end anonymous namespace.
5020 
5021 namespace {
5022 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
5023 protected:
5024   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5025                     MacroBuilder &Builder) const override {
5026     Builder.defineMacro("__AARCH64_SIMD__");
5027     Builder.defineMacro("__ARM64_ARCH_8__");
5028     Builder.defineMacro("__ARM_NEON__");
5029     Builder.defineMacro("__LITTLE_ENDIAN__");
5030     Builder.defineMacro("__REGISTER_PREFIX__", "");
5031     Builder.defineMacro("__arm64", "1");
5032     Builder.defineMacro("__arm64__", "1");
5033 
5034     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5035   }
5036 
5037 public:
5038   DarwinAArch64TargetInfo(const llvm::Triple &Triple)
5039       : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
5040     Int64Type = SignedLongLong;
5041     WCharType = SignedInt;
5042     UseSignedCharForObjCBool = false;
5043 
5044     LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
5045     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5046 
5047     TheCXXABI.set(TargetCXXABI::iOS64);
5048   }
5049 
5050   BuiltinVaListKind getBuiltinVaListKind() const override {
5051     return TargetInfo::CharPtrBuiltinVaList;
5052   }
5053 };
5054 } // end anonymous namespace
5055 
5056 namespace {
5057 // Hexagon abstract base class
5058 class HexagonTargetInfo : public TargetInfo {
5059   static const Builtin::Info BuiltinInfo[];
5060   static const char * const GCCRegNames[];
5061   static const TargetInfo::GCCRegAlias GCCRegAliases[];
5062   std::string CPU;
5063 public:
5064   HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5065     BigEndian = false;
5066     DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
5067 
5068     // {} in inline assembly are packet specifiers, not assembly variant
5069     // specifiers.
5070     NoAsmVariants = true;
5071   }
5072 
5073   void getTargetBuiltins(const Builtin::Info *&Records,
5074                          unsigned &NumRecords) const override {
5075     Records = BuiltinInfo;
5076     NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
5077   }
5078 
5079   bool validateAsmConstraint(const char *&Name,
5080                              TargetInfo::ConstraintInfo &Info) const override {
5081     return true;
5082   }
5083 
5084   void getTargetDefines(const LangOptions &Opts,
5085                         MacroBuilder &Builder) const override;
5086 
5087   bool hasFeature(StringRef Feature) const override {
5088     return Feature == "hexagon";
5089   }
5090 
5091   BuiltinVaListKind getBuiltinVaListKind() const override {
5092     return TargetInfo::CharPtrBuiltinVaList;
5093   }
5094   void getGCCRegNames(const char * const *&Names,
5095                       unsigned &NumNames) const override;
5096   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5097                         unsigned &NumAliases) const override;
5098   const char *getClobbers() const override {
5099     return "";
5100   }
5101 
5102   static const char *getHexagonCPUSuffix(StringRef Name) {
5103     return llvm::StringSwitch<const char*>(Name)
5104       .Case("hexagonv4", "4")
5105       .Case("hexagonv5", "5")
5106       .Default(nullptr);
5107   }
5108 
5109   bool setCPU(const std::string &Name) override {
5110     if (!getHexagonCPUSuffix(Name))
5111       return false;
5112 
5113     CPU = Name;
5114     return true;
5115   }
5116 };
5117 
5118 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5119                                 MacroBuilder &Builder) const {
5120   Builder.defineMacro("qdsp6");
5121   Builder.defineMacro("__qdsp6", "1");
5122   Builder.defineMacro("__qdsp6__", "1");
5123 
5124   Builder.defineMacro("hexagon");
5125   Builder.defineMacro("__hexagon", "1");
5126   Builder.defineMacro("__hexagon__", "1");
5127 
5128   if(CPU == "hexagonv1") {
5129     Builder.defineMacro("__HEXAGON_V1__");
5130     Builder.defineMacro("__HEXAGON_ARCH__", "1");
5131     if(Opts.HexagonQdsp6Compat) {
5132       Builder.defineMacro("__QDSP6_V1__");
5133       Builder.defineMacro("__QDSP6_ARCH__", "1");
5134     }
5135   }
5136   else if(CPU == "hexagonv2") {
5137     Builder.defineMacro("__HEXAGON_V2__");
5138     Builder.defineMacro("__HEXAGON_ARCH__", "2");
5139     if(Opts.HexagonQdsp6Compat) {
5140       Builder.defineMacro("__QDSP6_V2__");
5141       Builder.defineMacro("__QDSP6_ARCH__", "2");
5142     }
5143   }
5144   else if(CPU == "hexagonv3") {
5145     Builder.defineMacro("__HEXAGON_V3__");
5146     Builder.defineMacro("__HEXAGON_ARCH__", "3");
5147     if(Opts.HexagonQdsp6Compat) {
5148       Builder.defineMacro("__QDSP6_V3__");
5149       Builder.defineMacro("__QDSP6_ARCH__", "3");
5150     }
5151   }
5152   else if(CPU == "hexagonv4") {
5153     Builder.defineMacro("__HEXAGON_V4__");
5154     Builder.defineMacro("__HEXAGON_ARCH__", "4");
5155     if(Opts.HexagonQdsp6Compat) {
5156       Builder.defineMacro("__QDSP6_V4__");
5157       Builder.defineMacro("__QDSP6_ARCH__", "4");
5158     }
5159   }
5160   else if(CPU == "hexagonv5") {
5161     Builder.defineMacro("__HEXAGON_V5__");
5162     Builder.defineMacro("__HEXAGON_ARCH__", "5");
5163     if(Opts.HexagonQdsp6Compat) {
5164       Builder.defineMacro("__QDSP6_V5__");
5165       Builder.defineMacro("__QDSP6_ARCH__", "5");
5166     }
5167   }
5168 }
5169 
5170 const char * const HexagonTargetInfo::GCCRegNames[] = {
5171   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5172   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5173   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5174   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5175   "p0", "p1", "p2", "p3",
5176   "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5177 };
5178 
5179 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5180                                    unsigned &NumNames) const {
5181   Names = GCCRegNames;
5182   NumNames = llvm::array_lengthof(GCCRegNames);
5183 }
5184 
5185 
5186 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5187   { { "sp" }, "r29" },
5188   { { "fp" }, "r30" },
5189   { { "lr" }, "r31" },
5190  };
5191 
5192 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5193                                      unsigned &NumAliases) const {
5194   Aliases = GCCRegAliases;
5195   NumAliases = llvm::array_lengthof(GCCRegAliases);
5196 }
5197 
5198 
5199 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5200 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5201 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5202                                               ALL_LANGUAGES },
5203 #include "clang/Basic/BuiltinsHexagon.def"
5204 };
5205 }
5206 
5207 
5208 namespace {
5209 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5210 class SparcTargetInfo : public TargetInfo {
5211   static const TargetInfo::GCCRegAlias GCCRegAliases[];
5212   static const char * const GCCRegNames[];
5213   bool SoftFloat;
5214 public:
5215   SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
5216 
5217   bool handleTargetFeatures(std::vector<std::string> &Features,
5218                             DiagnosticsEngine &Diags) override {
5219     SoftFloat = false;
5220     for (unsigned i = 0, e = Features.size(); i != e; ++i)
5221       if (Features[i] == "+soft-float")
5222         SoftFloat = true;
5223     return true;
5224   }
5225   void getTargetDefines(const LangOptions &Opts,
5226                         MacroBuilder &Builder) const override {
5227     DefineStd(Builder, "sparc", Opts);
5228     Builder.defineMacro("__REGISTER_PREFIX__", "");
5229 
5230     if (SoftFloat)
5231       Builder.defineMacro("SOFT_FLOAT", "1");
5232   }
5233 
5234   bool hasFeature(StringRef Feature) const override {
5235     return llvm::StringSwitch<bool>(Feature)
5236              .Case("softfloat", SoftFloat)
5237              .Case("sparc", true)
5238              .Default(false);
5239   }
5240 
5241   void getTargetBuiltins(const Builtin::Info *&Records,
5242                          unsigned &NumRecords) const override {
5243     // FIXME: Implement!
5244   }
5245   BuiltinVaListKind getBuiltinVaListKind() const override {
5246     return TargetInfo::VoidPtrBuiltinVaList;
5247   }
5248   void getGCCRegNames(const char * const *&Names,
5249                       unsigned &NumNames) const override;
5250   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5251                         unsigned &NumAliases) const override;
5252   bool validateAsmConstraint(const char *&Name,
5253                              TargetInfo::ConstraintInfo &info) const override {
5254     // FIXME: Implement!
5255     switch (*Name) {
5256     case 'I': // Signed 13-bit constant
5257     case 'J': // Zero
5258     case 'K': // 32-bit constant with the low 12 bits clear
5259     case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5260     case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5261     case 'N': // Same as 'K' but zext (required for SIMode)
5262     case 'O': // The constant 4096
5263       return true;
5264     }
5265     return false;
5266   }
5267   const char *getClobbers() const override {
5268     // FIXME: Implement!
5269     return "";
5270   }
5271 };
5272 
5273 const char * const SparcTargetInfo::GCCRegNames[] = {
5274   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5275   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5276   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5277   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5278 };
5279 
5280 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5281                                      unsigned &NumNames) const {
5282   Names = GCCRegNames;
5283   NumNames = llvm::array_lengthof(GCCRegNames);
5284 }
5285 
5286 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5287   { { "g0" }, "r0" },
5288   { { "g1" }, "r1" },
5289   { { "g2" }, "r2" },
5290   { { "g3" }, "r3" },
5291   { { "g4" }, "r4" },
5292   { { "g5" }, "r5" },
5293   { { "g6" }, "r6" },
5294   { { "g7" }, "r7" },
5295   { { "o0" }, "r8" },
5296   { { "o1" }, "r9" },
5297   { { "o2" }, "r10" },
5298   { { "o3" }, "r11" },
5299   { { "o4" }, "r12" },
5300   { { "o5" }, "r13" },
5301   { { "o6", "sp" }, "r14" },
5302   { { "o7" }, "r15" },
5303   { { "l0" }, "r16" },
5304   { { "l1" }, "r17" },
5305   { { "l2" }, "r18" },
5306   { { "l3" }, "r19" },
5307   { { "l4" }, "r20" },
5308   { { "l5" }, "r21" },
5309   { { "l6" }, "r22" },
5310   { { "l7" }, "r23" },
5311   { { "i0" }, "r24" },
5312   { { "i1" }, "r25" },
5313   { { "i2" }, "r26" },
5314   { { "i3" }, "r27" },
5315   { { "i4" }, "r28" },
5316   { { "i5" }, "r29" },
5317   { { "i6", "fp" }, "r30" },
5318   { { "i7" }, "r31" },
5319 };
5320 
5321 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5322                                        unsigned &NumAliases) const {
5323   Aliases = GCCRegAliases;
5324   NumAliases = llvm::array_lengthof(GCCRegAliases);
5325 }
5326 
5327 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5328 class SparcV8TargetInfo : public SparcTargetInfo {
5329 public:
5330   SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5331     DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5332   }
5333 
5334   void getTargetDefines(const LangOptions &Opts,
5335                         MacroBuilder &Builder) const override {
5336     SparcTargetInfo::getTargetDefines(Opts, Builder);
5337     Builder.defineMacro("__sparcv8");
5338   }
5339 };
5340 
5341 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5342 class SparcV9TargetInfo : public SparcTargetInfo {
5343 public:
5344   SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5345     // FIXME: Support Sparc quad-precision long double?
5346     DescriptionString = "E-m:e-i64:64-n32:64-S128";
5347     // This is an LP64 platform.
5348     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5349 
5350     // OpenBSD uses long long for int64_t and intmax_t.
5351     if (getTriple().getOS() == llvm::Triple::OpenBSD)
5352       IntMaxType = SignedLongLong;
5353     else
5354       IntMaxType = SignedLong;
5355     Int64Type = IntMaxType;
5356 
5357     // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5358     // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5359     LongDoubleWidth = 128;
5360     LongDoubleAlign = 128;
5361     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5362     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5363   }
5364 
5365   void getTargetDefines(const LangOptions &Opts,
5366                         MacroBuilder &Builder) const override {
5367     SparcTargetInfo::getTargetDefines(Opts, Builder);
5368     Builder.defineMacro("__sparcv9");
5369     Builder.defineMacro("__arch64__");
5370     // Solaris doesn't need these variants, but the BSDs do.
5371     if (getTriple().getOS() != llvm::Triple::Solaris) {
5372       Builder.defineMacro("__sparc64__");
5373       Builder.defineMacro("__sparc_v9__");
5374       Builder.defineMacro("__sparcv9__");
5375     }
5376   }
5377 
5378   bool setCPU(const std::string &Name) override {
5379     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5380       .Case("v9", true)
5381       .Case("ultrasparc", true)
5382       .Case("ultrasparc3", true)
5383       .Case("niagara", true)
5384       .Case("niagara2", true)
5385       .Case("niagara3", true)
5386       .Case("niagara4", true)
5387       .Default(false);
5388 
5389     // No need to store the CPU yet.  There aren't any CPU-specific
5390     // macros to define.
5391     return CPUKnown;
5392   }
5393 };
5394 
5395 } // end anonymous namespace.
5396 
5397 namespace {
5398 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
5399 public:
5400   SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
5401       : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
5402     SizeType = UnsignedInt;
5403     PtrDiffType = SignedInt;
5404   }
5405 };
5406 } // end anonymous namespace.
5407 
5408 namespace {
5409 class SystemZTargetInfo : public TargetInfo {
5410   static const char *const GCCRegNames[];
5411 
5412 public:
5413   SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5414     TLSSupported = true;
5415     IntWidth = IntAlign = 32;
5416     LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5417     PointerWidth = PointerAlign = 64;
5418     LongDoubleWidth = 128;
5419     LongDoubleAlign = 64;
5420     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5421     MinGlobalAlign = 16;
5422     DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5423     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5424   }
5425   void getTargetDefines(const LangOptions &Opts,
5426                         MacroBuilder &Builder) const override {
5427     Builder.defineMacro("__s390__");
5428     Builder.defineMacro("__s390x__");
5429     Builder.defineMacro("__zarch__");
5430     Builder.defineMacro("__LONG_DOUBLE_128__");
5431   }
5432   void getTargetBuiltins(const Builtin::Info *&Records,
5433                          unsigned &NumRecords) const override {
5434     // FIXME: Implement.
5435     Records = nullptr;
5436     NumRecords = 0;
5437   }
5438 
5439   void getGCCRegNames(const char *const *&Names,
5440                       unsigned &NumNames) const override;
5441   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5442                         unsigned &NumAliases) const override {
5443     // No aliases.
5444     Aliases = nullptr;
5445     NumAliases = 0;
5446   }
5447   bool validateAsmConstraint(const char *&Name,
5448                              TargetInfo::ConstraintInfo &info) const override;
5449   const char *getClobbers() const override {
5450     // FIXME: Is this really right?
5451     return "";
5452   }
5453   BuiltinVaListKind getBuiltinVaListKind() const override {
5454     return TargetInfo::SystemZBuiltinVaList;
5455   }
5456   bool setCPU(const std::string &Name) override {
5457     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5458       .Case("z10", true)
5459       .Case("z196", true)
5460       .Case("zEC12", true)
5461       .Default(false);
5462 
5463     // No need to store the CPU yet.  There aren't any CPU-specific
5464     // macros to define.
5465     return CPUKnown;
5466   }
5467 };
5468 
5469 const char *const SystemZTargetInfo::GCCRegNames[] = {
5470   "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
5471   "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
5472   "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
5473   "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
5474 };
5475 
5476 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5477                                        unsigned &NumNames) const {
5478   Names = GCCRegNames;
5479   NumNames = llvm::array_lengthof(GCCRegNames);
5480 }
5481 
5482 bool SystemZTargetInfo::
5483 validateAsmConstraint(const char *&Name,
5484                       TargetInfo::ConstraintInfo &Info) const {
5485   switch (*Name) {
5486   default:
5487     return false;
5488 
5489   case 'a': // Address register
5490   case 'd': // Data register (equivalent to 'r')
5491   case 'f': // Floating-point register
5492     Info.setAllowsRegister();
5493     return true;
5494 
5495   case 'I': // Unsigned 8-bit constant
5496   case 'J': // Unsigned 12-bit constant
5497   case 'K': // Signed 16-bit constant
5498   case 'L': // Signed 20-bit displacement (on all targets we support)
5499   case 'M': // 0x7fffffff
5500     return true;
5501 
5502   case 'Q': // Memory with base and unsigned 12-bit displacement
5503   case 'R': // Likewise, plus an index
5504   case 'S': // Memory with base and signed 20-bit displacement
5505   case 'T': // Likewise, plus an index
5506     Info.setAllowsMemory();
5507     return true;
5508   }
5509 }
5510 }
5511 
5512 namespace {
5513   class MSP430TargetInfo : public TargetInfo {
5514     static const char * const GCCRegNames[];
5515   public:
5516     MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5517       BigEndian = false;
5518       TLSSupported = false;
5519       IntWidth = 16; IntAlign = 16;
5520       LongWidth = 32; LongLongWidth = 64;
5521       LongAlign = LongLongAlign = 16;
5522       PointerWidth = 16; PointerAlign = 16;
5523       SuitableAlign = 16;
5524       SizeType = UnsignedInt;
5525       IntMaxType = SignedLongLong;
5526       IntPtrType = SignedInt;
5527       PtrDiffType = SignedInt;
5528       SigAtomicType = SignedLong;
5529       DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5530     }
5531     void getTargetDefines(const LangOptions &Opts,
5532                           MacroBuilder &Builder) const override {
5533       Builder.defineMacro("MSP430");
5534       Builder.defineMacro("__MSP430__");
5535       // FIXME: defines for different 'flavours' of MCU
5536     }
5537     void getTargetBuiltins(const Builtin::Info *&Records,
5538                            unsigned &NumRecords) const override {
5539       // FIXME: Implement.
5540       Records = nullptr;
5541       NumRecords = 0;
5542     }
5543     bool hasFeature(StringRef Feature) const override {
5544       return Feature == "msp430";
5545     }
5546     void getGCCRegNames(const char * const *&Names,
5547                         unsigned &NumNames) const override;
5548     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5549                           unsigned &NumAliases) const override {
5550       // No aliases.
5551       Aliases = nullptr;
5552       NumAliases = 0;
5553     }
5554     bool
5555     validateAsmConstraint(const char *&Name,
5556                           TargetInfo::ConstraintInfo &info) const override {
5557       // FIXME: implement
5558       switch (*Name) {
5559       case 'K': // the constant 1
5560       case 'L': // constant -1^20 .. 1^19
5561       case 'M': // constant 1-4:
5562         return true;
5563       }
5564       // No target constraints for now.
5565       return false;
5566     }
5567     const char *getClobbers() const override {
5568       // FIXME: Is this really right?
5569       return "";
5570     }
5571     BuiltinVaListKind getBuiltinVaListKind() const override {
5572       // FIXME: implement
5573       return TargetInfo::CharPtrBuiltinVaList;
5574    }
5575   };
5576 
5577   const char * const MSP430TargetInfo::GCCRegNames[] = {
5578     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5579     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5580   };
5581 
5582   void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5583                                         unsigned &NumNames) const {
5584     Names = GCCRegNames;
5585     NumNames = llvm::array_lengthof(GCCRegNames);
5586   }
5587 }
5588 
5589 namespace {
5590 
5591   // LLVM and Clang cannot be used directly to output native binaries for
5592   // target, but is used to compile C code to llvm bitcode with correct
5593   // type and alignment information.
5594   //
5595   // TCE uses the llvm bitcode as input and uses it for generating customized
5596   // target processor and program binary. TCE co-design environment is
5597   // publicly available in http://tce.cs.tut.fi
5598 
5599   static const unsigned TCEOpenCLAddrSpaceMap[] = {
5600       3, // opencl_global
5601       4, // opencl_local
5602       5, // opencl_constant
5603       // FIXME: generic has to be added to the target
5604       0, // opencl_generic
5605       0, // cuda_device
5606       0, // cuda_constant
5607       0  // cuda_shared
5608   };
5609 
5610   class TCETargetInfo : public TargetInfo{
5611   public:
5612     TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5613       TLSSupported = false;
5614       IntWidth = 32;
5615       LongWidth = LongLongWidth = 32;
5616       PointerWidth = 32;
5617       IntAlign = 32;
5618       LongAlign = LongLongAlign = 32;
5619       PointerAlign = 32;
5620       SuitableAlign = 32;
5621       SizeType = UnsignedInt;
5622       IntMaxType = SignedLong;
5623       IntPtrType = SignedInt;
5624       PtrDiffType = SignedInt;
5625       FloatWidth = 32;
5626       FloatAlign = 32;
5627       DoubleWidth = 32;
5628       DoubleAlign = 32;
5629       LongDoubleWidth = 32;
5630       LongDoubleAlign = 32;
5631       FloatFormat = &llvm::APFloat::IEEEsingle;
5632       DoubleFormat = &llvm::APFloat::IEEEsingle;
5633       LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5634       DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5635                           "-f64:32-v64:32-v128:32-a:0:32-n32";
5636       AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5637       UseAddrSpaceMapMangling = true;
5638     }
5639 
5640     void getTargetDefines(const LangOptions &Opts,
5641                           MacroBuilder &Builder) const override {
5642       DefineStd(Builder, "tce", Opts);
5643       Builder.defineMacro("__TCE__");
5644       Builder.defineMacro("__TCE_V1__");
5645     }
5646     bool hasFeature(StringRef Feature) const override {
5647       return Feature == "tce";
5648     }
5649 
5650     void getTargetBuiltins(const Builtin::Info *&Records,
5651                            unsigned &NumRecords) const override {}
5652     const char *getClobbers() const override {
5653       return "";
5654     }
5655     BuiltinVaListKind getBuiltinVaListKind() const override {
5656       return TargetInfo::VoidPtrBuiltinVaList;
5657     }
5658     void getGCCRegNames(const char * const *&Names,
5659                         unsigned &NumNames) const override {}
5660     bool validateAsmConstraint(const char *&Name,
5661                                TargetInfo::ConstraintInfo &info) const override{
5662       return true;
5663     }
5664     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5665                           unsigned &NumAliases) const override {}
5666   };
5667 }
5668 
5669 namespace {
5670 class MipsTargetInfoBase : public TargetInfo {
5671   virtual void setDescriptionString() = 0;
5672 
5673   static const Builtin::Info BuiltinInfo[];
5674   std::string CPU;
5675   bool IsMips16;
5676   bool IsMicromips;
5677   bool IsNan2008;
5678   bool IsSingleFloat;
5679   enum MipsFloatABI {
5680     HardFloat, SoftFloat
5681   } FloatABI;
5682   enum DspRevEnum {
5683     NoDSP, DSP1, DSP2
5684   } DspRev;
5685   bool HasMSA;
5686 
5687 protected:
5688   bool HasFP64;
5689   std::string ABI;
5690 
5691 public:
5692   MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5693                      const std::string &CPUStr)
5694       : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5695         IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
5696         DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
5697     TheCXXABI.set(TargetCXXABI::GenericMIPS);
5698   }
5699 
5700   bool isNaN2008Default() const {
5701     return CPU == "mips32r6" || CPU == "mips64r6";
5702   }
5703 
5704   bool isFP64Default() const {
5705     return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
5706   }
5707 
5708   bool isNan2008() const override {
5709     return IsNan2008;
5710   }
5711 
5712   StringRef getABI() const override { return ABI; }
5713   bool setCPU(const std::string &Name) override {
5714     bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
5715                     getTriple().getArch() == llvm::Triple::mipsel;
5716     CPU = Name;
5717     return llvm::StringSwitch<bool>(Name)
5718         .Case("mips1", IsMips32)
5719         .Case("mips2", IsMips32)
5720         .Case("mips3", true)
5721         .Case("mips4", true)
5722         .Case("mips5", true)
5723         .Case("mips32", IsMips32)
5724         .Case("mips32r2", IsMips32)
5725         .Case("mips32r3", IsMips32)
5726         .Case("mips32r5", IsMips32)
5727         .Case("mips32r6", IsMips32)
5728         .Case("mips64", true)
5729         .Case("mips64r2", true)
5730         .Case("mips64r3", true)
5731         .Case("mips64r5", true)
5732         .Case("mips64r6", true)
5733         .Case("octeon", true)
5734         .Default(false);
5735   }
5736   const std::string& getCPU() const { return CPU; }
5737   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5738     if (CPU == "octeon")
5739       Features["mips64r2"] = Features["cnmips"] = true;
5740     else
5741       Features[CPU] = true;
5742   }
5743 
5744   void getTargetDefines(const LangOptions &Opts,
5745                         MacroBuilder &Builder) const override {
5746     Builder.defineMacro("__mips__");
5747     Builder.defineMacro("_mips");
5748     if (Opts.GNUMode)
5749       Builder.defineMacro("mips");
5750 
5751     Builder.defineMacro("__REGISTER_PREFIX__", "");
5752 
5753     switch (FloatABI) {
5754     case HardFloat:
5755       Builder.defineMacro("__mips_hard_float", Twine(1));
5756       break;
5757     case SoftFloat:
5758       Builder.defineMacro("__mips_soft_float", Twine(1));
5759       break;
5760     }
5761 
5762     if (IsSingleFloat)
5763       Builder.defineMacro("__mips_single_float", Twine(1));
5764 
5765     Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
5766     Builder.defineMacro("_MIPS_FPSET",
5767                         Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
5768 
5769     if (IsMips16)
5770       Builder.defineMacro("__mips16", Twine(1));
5771 
5772     if (IsMicromips)
5773       Builder.defineMacro("__mips_micromips", Twine(1));
5774 
5775     if (IsNan2008)
5776       Builder.defineMacro("__mips_nan2008", Twine(1));
5777 
5778     switch (DspRev) {
5779     default:
5780       break;
5781     case DSP1:
5782       Builder.defineMacro("__mips_dsp_rev", Twine(1));
5783       Builder.defineMacro("__mips_dsp", Twine(1));
5784       break;
5785     case DSP2:
5786       Builder.defineMacro("__mips_dsp_rev", Twine(2));
5787       Builder.defineMacro("__mips_dspr2", Twine(1));
5788       Builder.defineMacro("__mips_dsp", Twine(1));
5789       break;
5790     }
5791 
5792     if (HasMSA)
5793       Builder.defineMacro("__mips_msa", Twine(1));
5794 
5795     Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
5796     Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
5797     Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
5798 
5799     Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
5800     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
5801   }
5802 
5803   void getTargetBuiltins(const Builtin::Info *&Records,
5804                          unsigned &NumRecords) const override {
5805     Records = BuiltinInfo;
5806     NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
5807   }
5808   bool hasFeature(StringRef Feature) const override {
5809     return llvm::StringSwitch<bool>(Feature)
5810       .Case("mips", true)
5811       .Case("fp64", HasFP64)
5812       .Default(false);
5813   }
5814   BuiltinVaListKind getBuiltinVaListKind() const override {
5815     return TargetInfo::VoidPtrBuiltinVaList;
5816   }
5817   void getGCCRegNames(const char * const *&Names,
5818                       unsigned &NumNames) const override {
5819     static const char *const GCCRegNames[] = {
5820       // CPU register names
5821       // Must match second column of GCCRegAliases
5822       "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
5823       "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
5824       "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
5825       "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
5826       // Floating point register names
5827       "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
5828       "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
5829       "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
5830       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
5831       // Hi/lo and condition register names
5832       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
5833       "$fcc5","$fcc6","$fcc7",
5834       // MSA register names
5835       "$w0",  "$w1",  "$w2",  "$w3",  "$w4",  "$w5",  "$w6",  "$w7",
5836       "$w8",  "$w9",  "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
5837       "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
5838       "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
5839       // MSA control register names
5840       "$msair",      "$msacsr", "$msaaccess", "$msasave", "$msamodify",
5841       "$msarequest", "$msamap", "$msaunmap"
5842     };
5843     Names = GCCRegNames;
5844     NumNames = llvm::array_lengthof(GCCRegNames);
5845   }
5846   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5847                         unsigned &NumAliases) const override = 0;
5848   bool validateAsmConstraint(const char *&Name,
5849                              TargetInfo::ConstraintInfo &Info) const override {
5850     switch (*Name) {
5851     default:
5852       return false;
5853     case 'r': // CPU registers.
5854     case 'd': // Equivalent to "r" unless generating MIPS16 code.
5855     case 'y': // Equivalent to "r", backward compatibility only.
5856     case 'f': // floating-point registers.
5857     case 'c': // $25 for indirect jumps
5858     case 'l': // lo register
5859     case 'x': // hilo register pair
5860       Info.setAllowsRegister();
5861       return true;
5862     case 'I': // Signed 16-bit constant
5863     case 'J': // Integer 0
5864     case 'K': // Unsigned 16-bit constant
5865     case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
5866     case 'M': // Constants not loadable via lui, addiu, or ori
5867     case 'N': // Constant -1 to -65535
5868     case 'O': // A signed 15-bit constant
5869     case 'P': // A constant between 1 go 65535
5870       return true;
5871     case 'R': // An address that can be used in a non-macro load or store
5872       Info.setAllowsMemory();
5873       return true;
5874     }
5875   }
5876 
5877   const char *getClobbers() const override {
5878     // In GCC, $1 is not widely used in generated code (it's used only in a few
5879     // specific situations), so there is no real need for users to add it to
5880     // the clobbers list if they want to use it in their inline assembly code.
5881     //
5882     // In LLVM, $1 is treated as a normal GPR and is always allocatable during
5883     // code generation, so using it in inline assembly without adding it to the
5884     // clobbers list can cause conflicts between the inline assembly code and
5885     // the surrounding generated code.
5886     //
5887     // Another problem is that LLVM is allowed to choose $1 for inline assembly
5888     // operands, which will conflict with the ".set at" assembler option (which
5889     // we use only for inline assembly, in order to maintain compatibility with
5890     // GCC) and will also conflict with the user's usage of $1.
5891     //
5892     // The easiest way to avoid these conflicts and keep $1 as an allocatable
5893     // register for generated code is to automatically clobber $1 for all inline
5894     // assembly code.
5895     //
5896     // FIXME: We should automatically clobber $1 only for inline assembly code
5897     // which actually uses it. This would allow LLVM to use $1 for inline
5898     // assembly operands if the user's assembly code doesn't use it.
5899     return "~{$1}";
5900   }
5901 
5902   bool handleTargetFeatures(std::vector<std::string> &Features,
5903                             DiagnosticsEngine &Diags) override {
5904     IsMips16 = false;
5905     IsMicromips = false;
5906     IsNan2008 = isNaN2008Default();
5907     IsSingleFloat = false;
5908     FloatABI = HardFloat;
5909     DspRev = NoDSP;
5910     HasFP64 = isFP64Default();
5911 
5912     for (std::vector<std::string>::iterator it = Features.begin(),
5913          ie = Features.end(); it != ie; ++it) {
5914       if (*it == "+single-float")
5915         IsSingleFloat = true;
5916       else if (*it == "+soft-float")
5917         FloatABI = SoftFloat;
5918       else if (*it == "+mips16")
5919         IsMips16 = true;
5920       else if (*it == "+micromips")
5921         IsMicromips = true;
5922       else if (*it == "+dsp")
5923         DspRev = std::max(DspRev, DSP1);
5924       else if (*it == "+dspr2")
5925         DspRev = std::max(DspRev, DSP2);
5926       else if (*it == "+msa")
5927         HasMSA = true;
5928       else if (*it == "+fp64")
5929         HasFP64 = true;
5930       else if (*it == "-fp64")
5931         HasFP64 = false;
5932       else if (*it == "+nan2008")
5933         IsNan2008 = true;
5934       else if (*it == "-nan2008")
5935         IsNan2008 = false;
5936     }
5937 
5938     // Remove front-end specific options.
5939     std::vector<std::string>::iterator it =
5940       std::find(Features.begin(), Features.end(), "+soft-float");
5941     if (it != Features.end())
5942       Features.erase(it);
5943 
5944     setDescriptionString();
5945 
5946     return true;
5947   }
5948 
5949   int getEHDataRegisterNumber(unsigned RegNo) const override {
5950     if (RegNo == 0) return 4;
5951     if (RegNo == 1) return 5;
5952     return -1;
5953   }
5954 
5955   bool isCLZForZeroUndef() const override { return false; }
5956 };
5957 
5958 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
5959 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5960 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5961                                               ALL_LANGUAGES },
5962 #include "clang/Basic/BuiltinsMips.def"
5963 };
5964 
5965 class Mips32TargetInfoBase : public MipsTargetInfoBase {
5966 public:
5967   Mips32TargetInfoBase(const llvm::Triple &Triple)
5968       : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
5969     SizeType = UnsignedInt;
5970     PtrDiffType = SignedInt;
5971     Int64Type = SignedLongLong;
5972     IntMaxType = Int64Type;
5973     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
5974   }
5975   bool setABI(const std::string &Name) override {
5976     if (Name == "o32" || Name == "eabi") {
5977       ABI = Name;
5978       return true;
5979     }
5980     return false;
5981   }
5982   void getTargetDefines(const LangOptions &Opts,
5983                         MacroBuilder &Builder) const override {
5984     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5985 
5986     Builder.defineMacro("__mips", "32");
5987     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
5988 
5989     const std::string& CPUStr = getCPU();
5990     if (CPUStr == "mips32")
5991       Builder.defineMacro("__mips_isa_rev", "1");
5992     else if (CPUStr == "mips32r2")
5993       Builder.defineMacro("__mips_isa_rev", "2");
5994     else if (CPUStr == "mips32r3")
5995       Builder.defineMacro("__mips_isa_rev", "3");
5996     else if (CPUStr == "mips32r5")
5997       Builder.defineMacro("__mips_isa_rev", "5");
5998     else if (CPUStr == "mips32r6")
5999       Builder.defineMacro("__mips_isa_rev", "6");
6000 
6001     if (ABI == "o32") {
6002       Builder.defineMacro("__mips_o32");
6003       Builder.defineMacro("_ABIO32", "1");
6004       Builder.defineMacro("_MIPS_SIM", "_ABIO32");
6005     }
6006     else if (ABI == "eabi")
6007       Builder.defineMacro("__mips_eabi");
6008     else
6009       llvm_unreachable("Invalid ABI for Mips32.");
6010   }
6011   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6012                         unsigned &NumAliases) const override {
6013     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6014       { { "at" },  "$1" },
6015       { { "v0" },  "$2" },
6016       { { "v1" },  "$3" },
6017       { { "a0" },  "$4" },
6018       { { "a1" },  "$5" },
6019       { { "a2" },  "$6" },
6020       { { "a3" },  "$7" },
6021       { { "t0" },  "$8" },
6022       { { "t1" },  "$9" },
6023       { { "t2" }, "$10" },
6024       { { "t3" }, "$11" },
6025       { { "t4" }, "$12" },
6026       { { "t5" }, "$13" },
6027       { { "t6" }, "$14" },
6028       { { "t7" }, "$15" },
6029       { { "s0" }, "$16" },
6030       { { "s1" }, "$17" },
6031       { { "s2" }, "$18" },
6032       { { "s3" }, "$19" },
6033       { { "s4" }, "$20" },
6034       { { "s5" }, "$21" },
6035       { { "s6" }, "$22" },
6036       { { "s7" }, "$23" },
6037       { { "t8" }, "$24" },
6038       { { "t9" }, "$25" },
6039       { { "k0" }, "$26" },
6040       { { "k1" }, "$27" },
6041       { { "gp" }, "$28" },
6042       { { "sp","$sp" }, "$29" },
6043       { { "fp","$fp" }, "$30" },
6044       { { "ra" }, "$31" }
6045     };
6046     Aliases = GCCRegAliases;
6047     NumAliases = llvm::array_lengthof(GCCRegAliases);
6048   }
6049 };
6050 
6051 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
6052   void setDescriptionString() override {
6053     DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6054   }
6055 
6056 public:
6057   Mips32EBTargetInfo(const llvm::Triple &Triple)
6058       : Mips32TargetInfoBase(Triple) {
6059   }
6060   void getTargetDefines(const LangOptions &Opts,
6061                         MacroBuilder &Builder) const override {
6062     DefineStd(Builder, "MIPSEB", Opts);
6063     Builder.defineMacro("_MIPSEB");
6064     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6065   }
6066 };
6067 
6068 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
6069   void setDescriptionString() override {
6070     DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6071   }
6072 
6073 public:
6074   Mips32ELTargetInfo(const llvm::Triple &Triple)
6075       : Mips32TargetInfoBase(Triple) {
6076     BigEndian = false;
6077   }
6078   void getTargetDefines(const LangOptions &Opts,
6079                         MacroBuilder &Builder) const override {
6080     DefineStd(Builder, "MIPSEL", Opts);
6081     Builder.defineMacro("_MIPSEL");
6082     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6083   }
6084 };
6085 
6086 class Mips64TargetInfoBase : public MipsTargetInfoBase {
6087 public:
6088   Mips64TargetInfoBase(const llvm::Triple &Triple)
6089       : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6090     LongDoubleWidth = LongDoubleAlign = 128;
6091     LongDoubleFormat = &llvm::APFloat::IEEEquad;
6092     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6093       LongDoubleWidth = LongDoubleAlign = 64;
6094       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6095     }
6096     setN64ABITypes();
6097     SuitableAlign = 128;
6098     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6099   }
6100 
6101   void setN64ABITypes() {
6102     LongWidth = LongAlign = 64;
6103     PointerWidth = PointerAlign = 64;
6104     SizeType = UnsignedLong;
6105     PtrDiffType = SignedLong;
6106     Int64Type = SignedLong;
6107     IntMaxType = Int64Type;
6108   }
6109 
6110   void setN32ABITypes() {
6111     LongWidth = LongAlign = 32;
6112     PointerWidth = PointerAlign = 32;
6113     SizeType = UnsignedInt;
6114     PtrDiffType = SignedInt;
6115     Int64Type = SignedLongLong;
6116     IntMaxType = Int64Type;
6117   }
6118 
6119   bool setABI(const std::string &Name) override {
6120     if (Name == "n32") {
6121       setN32ABITypes();
6122       ABI = Name;
6123       return true;
6124     }
6125     if (Name == "n64") {
6126       setN64ABITypes();
6127       ABI = Name;
6128       return true;
6129     }
6130     return false;
6131   }
6132 
6133   void getTargetDefines(const LangOptions &Opts,
6134                         MacroBuilder &Builder) const override {
6135     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6136 
6137     Builder.defineMacro("__mips", "64");
6138     Builder.defineMacro("__mips64");
6139     Builder.defineMacro("__mips64__");
6140     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6141 
6142     const std::string& CPUStr = getCPU();
6143     if (CPUStr == "mips64")
6144       Builder.defineMacro("__mips_isa_rev", "1");
6145     else if (CPUStr == "mips64r2")
6146       Builder.defineMacro("__mips_isa_rev", "2");
6147     else if (CPUStr == "mips64r3")
6148       Builder.defineMacro("__mips_isa_rev", "3");
6149     else if (CPUStr == "mips64r5")
6150       Builder.defineMacro("__mips_isa_rev", "5");
6151     else if (CPUStr == "mips64r6")
6152       Builder.defineMacro("__mips_isa_rev", "6");
6153 
6154     if (ABI == "n32") {
6155       Builder.defineMacro("__mips_n32");
6156       Builder.defineMacro("_ABIN32", "2");
6157       Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6158     }
6159     else if (ABI == "n64") {
6160       Builder.defineMacro("__mips_n64");
6161       Builder.defineMacro("_ABI64", "3");
6162       Builder.defineMacro("_MIPS_SIM", "_ABI64");
6163     }
6164     else
6165       llvm_unreachable("Invalid ABI for Mips64.");
6166   }
6167   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6168                         unsigned &NumAliases) const override {
6169     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6170       { { "at" },  "$1" },
6171       { { "v0" },  "$2" },
6172       { { "v1" },  "$3" },
6173       { { "a0" },  "$4" },
6174       { { "a1" },  "$5" },
6175       { { "a2" },  "$6" },
6176       { { "a3" },  "$7" },
6177       { { "a4" },  "$8" },
6178       { { "a5" },  "$9" },
6179       { { "a6" }, "$10" },
6180       { { "a7" }, "$11" },
6181       { { "t0" }, "$12" },
6182       { { "t1" }, "$13" },
6183       { { "t2" }, "$14" },
6184       { { "t3" }, "$15" },
6185       { { "s0" }, "$16" },
6186       { { "s1" }, "$17" },
6187       { { "s2" }, "$18" },
6188       { { "s3" }, "$19" },
6189       { { "s4" }, "$20" },
6190       { { "s5" }, "$21" },
6191       { { "s6" }, "$22" },
6192       { { "s7" }, "$23" },
6193       { { "t8" }, "$24" },
6194       { { "t9" }, "$25" },
6195       { { "k0" }, "$26" },
6196       { { "k1" }, "$27" },
6197       { { "gp" }, "$28" },
6198       { { "sp","$sp" }, "$29" },
6199       { { "fp","$fp" }, "$30" },
6200       { { "ra" }, "$31" }
6201     };
6202     Aliases = GCCRegAliases;
6203     NumAliases = llvm::array_lengthof(GCCRegAliases);
6204   }
6205 
6206   bool hasInt128Type() const override { return true; }
6207 };
6208 
6209 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
6210   void setDescriptionString() override {
6211     if (ABI == "n32")
6212       DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6213     else
6214       DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6215 
6216   }
6217 
6218 public:
6219   Mips64EBTargetInfo(const llvm::Triple &Triple)
6220       : Mips64TargetInfoBase(Triple) {}
6221   void getTargetDefines(const LangOptions &Opts,
6222                         MacroBuilder &Builder) const override {
6223     DefineStd(Builder, "MIPSEB", Opts);
6224     Builder.defineMacro("_MIPSEB");
6225     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6226   }
6227 };
6228 
6229 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
6230   void setDescriptionString() override {
6231     if (ABI == "n32")
6232       DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6233     else
6234       DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6235   }
6236 public:
6237   Mips64ELTargetInfo(const llvm::Triple &Triple)
6238       : Mips64TargetInfoBase(Triple) {
6239     // Default ABI is n64.
6240     BigEndian = false;
6241   }
6242   void getTargetDefines(const LangOptions &Opts,
6243                         MacroBuilder &Builder) const override {
6244     DefineStd(Builder, "MIPSEL", Opts);
6245     Builder.defineMacro("_MIPSEL");
6246     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6247   }
6248 };
6249 } // end anonymous namespace.
6250 
6251 namespace {
6252 class PNaClTargetInfo : public TargetInfo {
6253 public:
6254   PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6255     BigEndian = false;
6256     this->UserLabelPrefix = "";
6257     this->LongAlign = 32;
6258     this->LongWidth = 32;
6259     this->PointerAlign = 32;
6260     this->PointerWidth = 32;
6261     this->IntMaxType = TargetInfo::SignedLongLong;
6262     this->Int64Type = TargetInfo::SignedLongLong;
6263     this->DoubleAlign = 64;
6264     this->LongDoubleWidth = 64;
6265     this->LongDoubleAlign = 64;
6266     this->SizeType = TargetInfo::UnsignedInt;
6267     this->PtrDiffType = TargetInfo::SignedInt;
6268     this->IntPtrType = TargetInfo::SignedInt;
6269     this->RegParmMax = 0; // Disallow regparm
6270   }
6271 
6272   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6273   }
6274   void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6275     Builder.defineMacro("__le32__");
6276     Builder.defineMacro("__pnacl__");
6277   }
6278   void getTargetDefines(const LangOptions &Opts,
6279                         MacroBuilder &Builder) const override {
6280     getArchDefines(Opts, Builder);
6281   }
6282   bool hasFeature(StringRef Feature) const override {
6283     return Feature == "pnacl";
6284   }
6285   void getTargetBuiltins(const Builtin::Info *&Records,
6286                          unsigned &NumRecords) const override {
6287   }
6288   BuiltinVaListKind getBuiltinVaListKind() const override {
6289     return TargetInfo::PNaClABIBuiltinVaList;
6290   }
6291   void getGCCRegNames(const char * const *&Names,
6292                       unsigned &NumNames) const override;
6293   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6294                         unsigned &NumAliases) const override;
6295   bool validateAsmConstraint(const char *&Name,
6296                              TargetInfo::ConstraintInfo &Info) const override {
6297     return false;
6298   }
6299 
6300   const char *getClobbers() const override {
6301     return "";
6302   }
6303 };
6304 
6305 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6306                                      unsigned &NumNames) const {
6307   Names = nullptr;
6308   NumNames = 0;
6309 }
6310 
6311 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6312                                        unsigned &NumAliases) const {
6313   Aliases = nullptr;
6314   NumAliases = 0;
6315 }
6316 } // end anonymous namespace.
6317 
6318 namespace {
6319 class Le64TargetInfo : public TargetInfo {
6320   static const Builtin::Info BuiltinInfo[];
6321 
6322 public:
6323   Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6324     BigEndian = false;
6325     NoAsmVariants = true;
6326     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6327     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6328     DescriptionString =
6329         "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
6330   }
6331 
6332   void getTargetDefines(const LangOptions &Opts,
6333                         MacroBuilder &Builder) const override {
6334     DefineStd(Builder, "unix", Opts);
6335     defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6336     Builder.defineMacro("__ELF__");
6337   }
6338   void getTargetBuiltins(const Builtin::Info *&Records,
6339                          unsigned &NumRecords) const override {
6340     Records = BuiltinInfo;
6341     NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6342   }
6343   BuiltinVaListKind getBuiltinVaListKind() const override {
6344     return TargetInfo::PNaClABIBuiltinVaList;
6345   }
6346   const char *getClobbers() const override { return ""; }
6347   void getGCCRegNames(const char *const *&Names,
6348                       unsigned &NumNames) const override {
6349     Names = nullptr;
6350     NumNames = 0;
6351   }
6352   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6353                         unsigned &NumAliases) const override {
6354     Aliases = nullptr;
6355     NumAliases = 0;
6356   }
6357   bool validateAsmConstraint(const char *&Name,
6358                              TargetInfo::ConstraintInfo &Info) const override {
6359     return false;
6360   }
6361 
6362   bool hasProtectedVisibility() const override { return false; }
6363 };
6364 } // end anonymous namespace.
6365 
6366 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6367 #define BUILTIN(ID, TYPE, ATTRS)                                               \
6368   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6369 #include "clang/Basic/BuiltinsLe64.def"
6370 };
6371 
6372 namespace {
6373   static const unsigned SPIRAddrSpaceMap[] = {
6374     1,    // opencl_global
6375     3,    // opencl_local
6376     2,    // opencl_constant
6377     4,    // opencl_generic
6378     0,    // cuda_device
6379     0,    // cuda_constant
6380     0     // cuda_shared
6381   };
6382   class SPIRTargetInfo : public TargetInfo {
6383   public:
6384     SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6385       assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6386         "SPIR target must use unknown OS");
6387       assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6388         "SPIR target must use unknown environment type");
6389       BigEndian = false;
6390       TLSSupported = false;
6391       LongWidth = LongAlign = 64;
6392       AddrSpaceMap = &SPIRAddrSpaceMap;
6393       UseAddrSpaceMapMangling = true;
6394       // Define available target features
6395       // These must be defined in sorted order!
6396       NoAsmVariants = true;
6397     }
6398     void getTargetDefines(const LangOptions &Opts,
6399                           MacroBuilder &Builder) const override {
6400       DefineStd(Builder, "SPIR", Opts);
6401     }
6402     bool hasFeature(StringRef Feature) const override {
6403       return Feature == "spir";
6404     }
6405 
6406     void getTargetBuiltins(const Builtin::Info *&Records,
6407                            unsigned &NumRecords) const override {}
6408     const char *getClobbers() const override {
6409       return "";
6410     }
6411     void getGCCRegNames(const char * const *&Names,
6412                         unsigned &NumNames) const override {}
6413     bool
6414     validateAsmConstraint(const char *&Name,
6415                           TargetInfo::ConstraintInfo &info) const override {
6416       return true;
6417     }
6418     void getGCCRegAliases(const GCCRegAlias *&Aliases,
6419                           unsigned &NumAliases) const override {}
6420     BuiltinVaListKind getBuiltinVaListKind() const override {
6421       return TargetInfo::VoidPtrBuiltinVaList;
6422     }
6423 
6424     CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6425       return (CC == CC_SpirFunction ||
6426               CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning;
6427     }
6428 
6429     CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
6430       return CC_SpirFunction;
6431     }
6432   };
6433 
6434 
6435   class SPIR32TargetInfo : public SPIRTargetInfo {
6436   public:
6437     SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6438       PointerWidth = PointerAlign = 32;
6439       SizeType     = TargetInfo::UnsignedInt;
6440       PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6441       DescriptionString
6442         = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6443           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6444     }
6445     void getTargetDefines(const LangOptions &Opts,
6446                           MacroBuilder &Builder) const override {
6447       DefineStd(Builder, "SPIR32", Opts);
6448     }
6449   };
6450 
6451   class SPIR64TargetInfo : public SPIRTargetInfo {
6452   public:
6453     SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6454       PointerWidth = PointerAlign = 64;
6455       SizeType     = TargetInfo::UnsignedLong;
6456       PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6457       DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6458                           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6459     }
6460     void getTargetDefines(const LangOptions &Opts,
6461                           MacroBuilder &Builder) const override {
6462       DefineStd(Builder, "SPIR64", Opts);
6463     }
6464   };
6465 }
6466 
6467 namespace {
6468 class XCoreTargetInfo : public TargetInfo {
6469   static const Builtin::Info BuiltinInfo[];
6470 public:
6471   XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6472     BigEndian = false;
6473     NoAsmVariants = true;
6474     LongLongAlign = 32;
6475     SuitableAlign = 32;
6476     DoubleAlign = LongDoubleAlign = 32;
6477     SizeType = UnsignedInt;
6478     PtrDiffType = SignedInt;
6479     IntPtrType = SignedInt;
6480     WCharType = UnsignedChar;
6481     WIntType = UnsignedInt;
6482     UseZeroLengthBitfieldAlignment = true;
6483     DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6484                         "-f64:32-a:0:32-n32";
6485   }
6486   void getTargetDefines(const LangOptions &Opts,
6487                         MacroBuilder &Builder) const override {
6488     Builder.defineMacro("__XS1B__");
6489   }
6490   void getTargetBuiltins(const Builtin::Info *&Records,
6491                          unsigned &NumRecords) const override {
6492     Records = BuiltinInfo;
6493     NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6494   }
6495   BuiltinVaListKind getBuiltinVaListKind() const override {
6496     return TargetInfo::VoidPtrBuiltinVaList;
6497   }
6498   const char *getClobbers() const override {
6499     return "";
6500   }
6501   void getGCCRegNames(const char * const *&Names,
6502                       unsigned &NumNames) const override {
6503     static const char * const GCCRegNames[] = {
6504       "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
6505       "r8",   "r9",   "r10",  "r11",  "cp",   "dp",   "sp",   "lr"
6506     };
6507     Names = GCCRegNames;
6508     NumNames = llvm::array_lengthof(GCCRegNames);
6509   }
6510   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6511                         unsigned &NumAliases) const override {
6512     Aliases = nullptr;
6513     NumAliases = 0;
6514   }
6515   bool validateAsmConstraint(const char *&Name,
6516                              TargetInfo::ConstraintInfo &Info) const override {
6517     return false;
6518   }
6519   int getEHDataRegisterNumber(unsigned RegNo) const override {
6520     // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6521     return (RegNo < 2)? RegNo : -1;
6522   }
6523 };
6524 
6525 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6526 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6527 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6528                                               ALL_LANGUAGES },
6529 #include "clang/Basic/BuiltinsXCore.def"
6530 };
6531 } // end anonymous namespace.
6532 
6533 
6534 //===----------------------------------------------------------------------===//
6535 // Driver code
6536 //===----------------------------------------------------------------------===//
6537 
6538 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6539   llvm::Triple::OSType os = Triple.getOS();
6540 
6541   switch (Triple.getArch()) {
6542   default:
6543     return nullptr;
6544 
6545   case llvm::Triple::xcore:
6546     return new XCoreTargetInfo(Triple);
6547 
6548   case llvm::Triple::hexagon:
6549     return new HexagonTargetInfo(Triple);
6550 
6551   case llvm::Triple::aarch64:
6552     if (Triple.isOSDarwin())
6553       return new DarwinAArch64TargetInfo(Triple);
6554 
6555     switch (os) {
6556     case llvm::Triple::FreeBSD:
6557       return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
6558     case llvm::Triple::Linux:
6559       return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6560     case llvm::Triple::NetBSD:
6561       return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6562     default:
6563       return new AArch64leTargetInfo(Triple);
6564     }
6565 
6566   case llvm::Triple::aarch64_be:
6567     switch (os) {
6568     case llvm::Triple::FreeBSD:
6569       return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
6570     case llvm::Triple::Linux:
6571       return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6572     case llvm::Triple::NetBSD:
6573       return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6574     default:
6575       return new AArch64beTargetInfo(Triple);
6576     }
6577 
6578   case llvm::Triple::arm:
6579   case llvm::Triple::thumb:
6580     if (Triple.isOSBinFormatMachO())
6581       return new DarwinARMTargetInfo(Triple);
6582 
6583     switch (os) {
6584     case llvm::Triple::Linux:
6585       return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6586     case llvm::Triple::FreeBSD:
6587       return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6588     case llvm::Triple::NetBSD:
6589       return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6590     case llvm::Triple::OpenBSD:
6591       return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6592     case llvm::Triple::Bitrig:
6593       return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6594     case llvm::Triple::RTEMS:
6595       return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6596     case llvm::Triple::NaCl:
6597       return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6598     case llvm::Triple::Win32:
6599       switch (Triple.getEnvironment()) {
6600       default:
6601         return new ARMleTargetInfo(Triple);
6602       case llvm::Triple::Itanium:
6603         return new ItaniumWindowsARMleTargetInfo(Triple);
6604       case llvm::Triple::MSVC:
6605         return new MicrosoftARMleTargetInfo(Triple);
6606       }
6607     default:
6608       return new ARMleTargetInfo(Triple);
6609     }
6610 
6611   case llvm::Triple::armeb:
6612   case llvm::Triple::thumbeb:
6613     if (Triple.isOSDarwin())
6614       return new DarwinARMTargetInfo(Triple);
6615 
6616     switch (os) {
6617     case llvm::Triple::Linux:
6618       return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6619     case llvm::Triple::FreeBSD:
6620       return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6621     case llvm::Triple::NetBSD:
6622       return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6623     case llvm::Triple::OpenBSD:
6624       return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6625     case llvm::Triple::Bitrig:
6626       return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6627     case llvm::Triple::RTEMS:
6628       return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6629     case llvm::Triple::NaCl:
6630       return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6631     default:
6632       return new ARMbeTargetInfo(Triple);
6633     }
6634 
6635   case llvm::Triple::msp430:
6636     return new MSP430TargetInfo(Triple);
6637 
6638   case llvm::Triple::mips:
6639     switch (os) {
6640     case llvm::Triple::Linux:
6641       return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6642     case llvm::Triple::RTEMS:
6643       return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6644     case llvm::Triple::FreeBSD:
6645       return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6646     case llvm::Triple::NetBSD:
6647       return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6648     default:
6649       return new Mips32EBTargetInfo(Triple);
6650     }
6651 
6652   case llvm::Triple::mipsel:
6653     switch (os) {
6654     case llvm::Triple::Linux:
6655       return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6656     case llvm::Triple::RTEMS:
6657       return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6658     case llvm::Triple::FreeBSD:
6659       return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6660     case llvm::Triple::NetBSD:
6661       return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6662     case llvm::Triple::NaCl:
6663       return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6664     default:
6665       return new Mips32ELTargetInfo(Triple);
6666     }
6667 
6668   case llvm::Triple::mips64:
6669     switch (os) {
6670     case llvm::Triple::Linux:
6671       return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
6672     case llvm::Triple::RTEMS:
6673       return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
6674     case llvm::Triple::FreeBSD:
6675       return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6676     case llvm::Triple::NetBSD:
6677       return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6678     case llvm::Triple::OpenBSD:
6679       return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6680     default:
6681       return new Mips64EBTargetInfo(Triple);
6682     }
6683 
6684   case llvm::Triple::mips64el:
6685     switch (os) {
6686     case llvm::Triple::Linux:
6687       return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
6688     case llvm::Triple::RTEMS:
6689       return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
6690     case llvm::Triple::FreeBSD:
6691       return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6692     case llvm::Triple::NetBSD:
6693       return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6694     case llvm::Triple::OpenBSD:
6695       return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6696     default:
6697       return new Mips64ELTargetInfo(Triple);
6698     }
6699 
6700   case llvm::Triple::le32:
6701     switch (os) {
6702       case llvm::Triple::NaCl:
6703         return new NaClTargetInfo<PNaClTargetInfo>(Triple);
6704       default:
6705         return nullptr;
6706     }
6707 
6708   case llvm::Triple::le64:
6709     return new Le64TargetInfo(Triple);
6710 
6711   case llvm::Triple::ppc:
6712     if (Triple.isOSDarwin())
6713       return new DarwinPPC32TargetInfo(Triple);
6714     switch (os) {
6715     case llvm::Triple::Linux:
6716       return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
6717     case llvm::Triple::FreeBSD:
6718       return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
6719     case llvm::Triple::NetBSD:
6720       return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
6721     case llvm::Triple::OpenBSD:
6722       return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
6723     case llvm::Triple::RTEMS:
6724       return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
6725     default:
6726       return new PPC32TargetInfo(Triple);
6727     }
6728 
6729   case llvm::Triple::ppc64:
6730     if (Triple.isOSDarwin())
6731       return new DarwinPPC64TargetInfo(Triple);
6732     switch (os) {
6733     case llvm::Triple::Linux:
6734       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6735     case llvm::Triple::Lv2:
6736       return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
6737     case llvm::Triple::FreeBSD:
6738       return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
6739     case llvm::Triple::NetBSD:
6740       return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6741     default:
6742       return new PPC64TargetInfo(Triple);
6743     }
6744 
6745   case llvm::Triple::ppc64le:
6746     switch (os) {
6747     case llvm::Triple::Linux:
6748       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6749     default:
6750       return new PPC64TargetInfo(Triple);
6751     }
6752 
6753   case llvm::Triple::nvptx:
6754     return new NVPTX32TargetInfo(Triple);
6755   case llvm::Triple::nvptx64:
6756     return new NVPTX64TargetInfo(Triple);
6757 
6758   case llvm::Triple::amdgcn:
6759   case llvm::Triple::r600:
6760     return new R600TargetInfo(Triple);
6761 
6762   case llvm::Triple::sparc:
6763     switch (os) {
6764     case llvm::Triple::Linux:
6765       return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
6766     case llvm::Triple::Solaris:
6767       return new SolarisSparcV8TargetInfo(Triple);
6768     case llvm::Triple::NetBSD:
6769       return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
6770     case llvm::Triple::OpenBSD:
6771       return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
6772     case llvm::Triple::RTEMS:
6773       return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
6774     default:
6775       return new SparcV8TargetInfo(Triple);
6776     }
6777 
6778   case llvm::Triple::sparcv9:
6779     switch (os) {
6780     case llvm::Triple::Linux:
6781       return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
6782     case llvm::Triple::Solaris:
6783       return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
6784     case llvm::Triple::NetBSD:
6785       return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
6786     case llvm::Triple::OpenBSD:
6787       return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
6788     case llvm::Triple::FreeBSD:
6789       return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
6790     default:
6791       return new SparcV9TargetInfo(Triple);
6792     }
6793 
6794   case llvm::Triple::systemz:
6795     switch (os) {
6796     case llvm::Triple::Linux:
6797       return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
6798     default:
6799       return new SystemZTargetInfo(Triple);
6800     }
6801 
6802   case llvm::Triple::tce:
6803     return new TCETargetInfo(Triple);
6804 
6805   case llvm::Triple::x86:
6806     if (Triple.isOSDarwin())
6807       return new DarwinI386TargetInfo(Triple);
6808 
6809     switch (os) {
6810     case llvm::Triple::Linux:
6811       return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
6812     case llvm::Triple::DragonFly:
6813       return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
6814     case llvm::Triple::NetBSD:
6815       return new NetBSDI386TargetInfo(Triple);
6816     case llvm::Triple::OpenBSD:
6817       return new OpenBSDI386TargetInfo(Triple);
6818     case llvm::Triple::Bitrig:
6819       return new BitrigI386TargetInfo(Triple);
6820     case llvm::Triple::FreeBSD:
6821       return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6822     case llvm::Triple::KFreeBSD:
6823       return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6824     case llvm::Triple::Minix:
6825       return new MinixTargetInfo<X86_32TargetInfo>(Triple);
6826     case llvm::Triple::Solaris:
6827       return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
6828     case llvm::Triple::Win32: {
6829       switch (Triple.getEnvironment()) {
6830       default:
6831         return new X86_32TargetInfo(Triple);
6832       case llvm::Triple::Cygnus:
6833         return new CygwinX86_32TargetInfo(Triple);
6834       case llvm::Triple::GNU:
6835         return new MinGWX86_32TargetInfo(Triple);
6836       case llvm::Triple::Itanium:
6837       case llvm::Triple::MSVC:
6838         return new MicrosoftX86_32TargetInfo(Triple);
6839       }
6840     }
6841     case llvm::Triple::Haiku:
6842       return new HaikuX86_32TargetInfo(Triple);
6843     case llvm::Triple::RTEMS:
6844       return new RTEMSX86_32TargetInfo(Triple);
6845     case llvm::Triple::NaCl:
6846       return new NaClTargetInfo<X86_32TargetInfo>(Triple);
6847     default:
6848       return new X86_32TargetInfo(Triple);
6849     }
6850 
6851   case llvm::Triple::x86_64:
6852     if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
6853       return new DarwinX86_64TargetInfo(Triple);
6854 
6855     switch (os) {
6856     case llvm::Triple::Linux:
6857       return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
6858     case llvm::Triple::DragonFly:
6859       return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
6860     case llvm::Triple::NetBSD:
6861       return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
6862     case llvm::Triple::OpenBSD:
6863       return new OpenBSDX86_64TargetInfo(Triple);
6864     case llvm::Triple::Bitrig:
6865       return new BitrigX86_64TargetInfo(Triple);
6866     case llvm::Triple::FreeBSD:
6867       return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6868     case llvm::Triple::KFreeBSD:
6869       return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6870     case llvm::Triple::Solaris:
6871       return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
6872     case llvm::Triple::Win32: {
6873       switch (Triple.getEnvironment()) {
6874       default:
6875         return new X86_64TargetInfo(Triple);
6876       case llvm::Triple::GNU:
6877         return new MinGWX86_64TargetInfo(Triple);
6878       case llvm::Triple::MSVC:
6879         return new MicrosoftX86_64TargetInfo(Triple);
6880       }
6881     }
6882     case llvm::Triple::NaCl:
6883       return new NaClTargetInfo<X86_64TargetInfo>(Triple);
6884     case llvm::Triple::PS4:
6885       return new PS4OSTargetInfo<X86_64TargetInfo>(Triple);
6886     default:
6887       return new X86_64TargetInfo(Triple);
6888     }
6889 
6890     case llvm::Triple::spir: {
6891       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6892           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6893         return nullptr;
6894       return new SPIR32TargetInfo(Triple);
6895     }
6896     case llvm::Triple::spir64: {
6897       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6898           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6899         return nullptr;
6900       return new SPIR64TargetInfo(Triple);
6901     }
6902   }
6903 }
6904 
6905 /// CreateTargetInfo - Return the target info object for the specified target
6906 /// triple.
6907 TargetInfo *
6908 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
6909                              const std::shared_ptr<TargetOptions> &Opts) {
6910   llvm::Triple Triple(Opts->Triple);
6911 
6912   // Construct the target
6913   std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
6914   if (!Target) {
6915     Diags.Report(diag::err_target_unknown_triple) << Triple.str();
6916     return nullptr;
6917   }
6918   Target->TargetOpts = Opts;
6919 
6920   // Set the target CPU if specified.
6921   if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
6922     Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
6923     return nullptr;
6924   }
6925 
6926   // Set the target ABI if specified.
6927   if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
6928     Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
6929     return nullptr;
6930   }
6931 
6932   // Set the fp math unit.
6933   if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
6934     Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
6935     return nullptr;
6936   }
6937 
6938   // Compute the default target features, we need the target to handle this
6939   // because features may have dependencies on one another.
6940   llvm::StringMap<bool> Features;
6941   Target->getDefaultFeatures(Features);
6942 
6943   // Apply the user specified deltas.
6944   for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
6945        I < N; ++I) {
6946     const char *Name = Opts->FeaturesAsWritten[I].c_str();
6947     // Apply the feature via the target.
6948     bool Enabled = Name[0] == '+';
6949     Target->setFeatureEnabled(Features, Name + 1, Enabled);
6950   }
6951 
6952   // Add the features to the compile options.
6953   //
6954   // FIXME: If we are completely confident that we have the right set, we only
6955   // need to pass the minuses.
6956   Opts->Features.clear();
6957   for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
6958          ie = Features.end(); it != ie; ++it)
6959     Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
6960   if (!Target->handleTargetFeatures(Opts->Features, Diags))
6961     return nullptr;
6962 
6963   return Target.release();
6964 }
6965