1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/OwningPtr.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/IR/Type.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include <algorithm> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 virtual void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "5621"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("__MACH__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 98 99 if (!Opts.ObjCAutoRefCount) { 100 // __weak is always defined, for use in blocks and with objc pointers. 101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 102 103 // Darwin defines __strong even in C mode (just to nothing). 104 if (Opts.getGC() != LangOptions::NonGC) 105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 106 else 107 Builder.defineMacro("__strong", ""); 108 109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 110 // allow this in C, since one might have block pointers in structs that 111 // are used in pure C code and in Objective-C ARC. 112 Builder.defineMacro("__unsafe_unretained", ""); 113 } 114 115 if (Opts.Static) 116 Builder.defineMacro("__STATIC__"); 117 else 118 Builder.defineMacro("__DYNAMIC__"); 119 120 if (Opts.POSIXThreads) 121 Builder.defineMacro("_REENTRANT"); 122 123 // Get the platform type and version number from the triple. 124 unsigned Maj, Min, Rev; 125 if (Triple.isMacOSX()) { 126 Triple.getMacOSXVersion(Maj, Min, Rev); 127 PlatformName = "macosx"; 128 } else { 129 Triple.getOSVersion(Maj, Min, Rev); 130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 131 } 132 133 // If -target arch-pc-win32-macho option specified, we're 134 // generating code for Win32 ABI. No need to emit 135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 136 if (PlatformName == "win32") { 137 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 138 return; 139 } 140 141 // Set the appropriate OS version define. 142 if (Triple.getOS() == llvm::Triple::IOS) { 143 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 144 char Str[6]; 145 Str[0] = '0' + Maj; 146 Str[1] = '0' + (Min / 10); 147 Str[2] = '0' + (Min % 10); 148 Str[3] = '0' + (Rev / 10); 149 Str[4] = '0' + (Rev % 10); 150 Str[5] = '\0'; 151 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str); 152 } else { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Triple.getEnvironmentName().empty() && "Invalid environment!"); 158 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[5]; 160 Str[0] = '0' + (Maj / 10); 161 Str[1] = '0' + (Maj % 10); 162 Str[2] = '0' + std::min(Min, 9U); 163 Str[3] = '0' + std::min(Rev, 9U); 164 Str[4] = '\0'; 165 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 166 } 167 168 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 169 } 170 171 namespace { 172 template<typename Target> 173 class DarwinTargetInfo : public OSTargetInfo<Target> { 174 protected: 175 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 176 MacroBuilder &Builder) const { 177 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 178 this->PlatformMinVersion); 179 } 180 181 public: 182 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 183 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 184 this->MCountName = "\01mcount"; 185 } 186 187 virtual std::string isValidSectionSpecifier(StringRef SR) const { 188 // Let MCSectionMachO validate this. 189 StringRef Segment, Section; 190 unsigned TAA, StubSize; 191 bool HasTAA; 192 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 193 TAA, HasTAA, StubSize); 194 } 195 196 virtual const char *getStaticInitSectionSpecifier() const { 197 // FIXME: We should return 0 when building kexts. 198 return "__TEXT,__StaticInit,regular,pure_instructions"; 199 } 200 201 /// Darwin does not support protected visibility. Darwin's "default" 202 /// is very similar to ELF's "protected"; Darwin requires a "weak" 203 /// attribute on declarations that can be dynamically replaced. 204 virtual bool hasProtectedVisibility() const { 205 return false; 206 } 207 }; 208 209 210 // DragonFlyBSD Target 211 template<typename Target> 212 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 213 protected: 214 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 215 MacroBuilder &Builder) const { 216 // DragonFly defines; list based off of gcc output 217 Builder.defineMacro("__DragonFly__"); 218 Builder.defineMacro("__DragonFly_cc_version", "100001"); 219 Builder.defineMacro("__ELF__"); 220 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 221 Builder.defineMacro("__tune_i386__"); 222 DefineStd(Builder, "unix", Opts); 223 } 224 public: 225 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 226 : OSTargetInfo<Target>(Triple) { 227 this->UserLabelPrefix = ""; 228 229 switch (Triple.getArch()) { 230 default: 231 case llvm::Triple::x86: 232 case llvm::Triple::x86_64: 233 this->MCountName = ".mcount"; 234 break; 235 } 236 } 237 }; 238 239 // FreeBSD Target 240 template<typename Target> 241 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 242 protected: 243 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 244 MacroBuilder &Builder) const { 245 // FreeBSD defines; list based off of gcc output 246 247 unsigned Release = Triple.getOSMajorVersion(); 248 if (Release == 0U) 249 Release = 8; 250 251 Builder.defineMacro("__FreeBSD__", Twine(Release)); 252 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 253 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 254 DefineStd(Builder, "unix", Opts); 255 Builder.defineMacro("__ELF__"); 256 } 257 public: 258 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 259 this->UserLabelPrefix = ""; 260 261 switch (Triple.getArch()) { 262 default: 263 case llvm::Triple::x86: 264 case llvm::Triple::x86_64: 265 this->MCountName = ".mcount"; 266 break; 267 case llvm::Triple::mips: 268 case llvm::Triple::mipsel: 269 case llvm::Triple::ppc: 270 case llvm::Triple::ppc64: 271 case llvm::Triple::ppc64le: 272 this->MCountName = "_mcount"; 273 break; 274 case llvm::Triple::arm: 275 this->MCountName = "__mcount"; 276 break; 277 } 278 } 279 }; 280 281 // Minix Target 282 template<typename Target> 283 class MinixTargetInfo : public OSTargetInfo<Target> { 284 protected: 285 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 286 MacroBuilder &Builder) const { 287 // Minix defines 288 289 Builder.defineMacro("__minix", "3"); 290 Builder.defineMacro("_EM_WSIZE", "4"); 291 Builder.defineMacro("_EM_PSIZE", "4"); 292 Builder.defineMacro("_EM_SSIZE", "2"); 293 Builder.defineMacro("_EM_LSIZE", "4"); 294 Builder.defineMacro("_EM_FSIZE", "4"); 295 Builder.defineMacro("_EM_DSIZE", "8"); 296 Builder.defineMacro("__ELF__"); 297 DefineStd(Builder, "unix", Opts); 298 } 299 public: 300 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 301 this->UserLabelPrefix = ""; 302 } 303 }; 304 305 // Linux target 306 template<typename Target> 307 class LinuxTargetInfo : public OSTargetInfo<Target> { 308 protected: 309 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 310 MacroBuilder &Builder) const { 311 // Linux defines; list based off of gcc output 312 DefineStd(Builder, "unix", Opts); 313 DefineStd(Builder, "linux", Opts); 314 Builder.defineMacro("__gnu_linux__"); 315 Builder.defineMacro("__ELF__"); 316 if (Triple.getEnvironment() == llvm::Triple::Android) 317 Builder.defineMacro("__ANDROID__", "1"); 318 if (Opts.POSIXThreads) 319 Builder.defineMacro("_REENTRANT"); 320 if (Opts.CPlusPlus) 321 Builder.defineMacro("_GNU_SOURCE"); 322 } 323 public: 324 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 325 this->UserLabelPrefix = ""; 326 this->WIntType = TargetInfo::UnsignedInt; 327 } 328 329 virtual const char *getStaticInitSectionSpecifier() const { 330 return ".text.startup"; 331 } 332 }; 333 334 // NetBSD Target 335 template<typename Target> 336 class NetBSDTargetInfo : public OSTargetInfo<Target> { 337 protected: 338 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 339 MacroBuilder &Builder) const { 340 // NetBSD defines; list based off of gcc output 341 Builder.defineMacro("__NetBSD__"); 342 Builder.defineMacro("__unix__"); 343 Builder.defineMacro("__ELF__"); 344 if (Opts.POSIXThreads) 345 Builder.defineMacro("_POSIX_THREADS"); 346 } 347 public: 348 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 349 this->UserLabelPrefix = ""; 350 } 351 }; 352 353 // OpenBSD Target 354 template<typename Target> 355 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 356 protected: 357 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 358 MacroBuilder &Builder) const { 359 // OpenBSD defines; list based off of gcc output 360 361 Builder.defineMacro("__OpenBSD__"); 362 DefineStd(Builder, "unix", Opts); 363 Builder.defineMacro("__ELF__"); 364 if (Opts.POSIXThreads) 365 Builder.defineMacro("_REENTRANT"); 366 } 367 public: 368 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 369 this->UserLabelPrefix = ""; 370 this->TLSSupported = false; 371 372 switch (Triple.getArch()) { 373 default: 374 case llvm::Triple::x86: 375 case llvm::Triple::x86_64: 376 case llvm::Triple::arm: 377 case llvm::Triple::sparc: 378 this->MCountName = "__mcount"; 379 break; 380 case llvm::Triple::mips64: 381 case llvm::Triple::mips64el: 382 case llvm::Triple::ppc: 383 case llvm::Triple::sparcv9: 384 this->MCountName = "_mcount"; 385 break; 386 } 387 } 388 }; 389 390 // Bitrig Target 391 template<typename Target> 392 class BitrigTargetInfo : public OSTargetInfo<Target> { 393 protected: 394 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 395 MacroBuilder &Builder) const { 396 // Bitrig defines; list based off of gcc output 397 398 Builder.defineMacro("__Bitrig__"); 399 DefineStd(Builder, "unix", Opts); 400 Builder.defineMacro("__ELF__"); 401 if (Opts.POSIXThreads) 402 Builder.defineMacro("_REENTRANT"); 403 } 404 public: 405 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 406 this->UserLabelPrefix = ""; 407 this->TLSSupported = false; 408 this->MCountName = "__mcount"; 409 } 410 }; 411 412 // PSP Target 413 template<typename Target> 414 class PSPTargetInfo : public OSTargetInfo<Target> { 415 protected: 416 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 417 MacroBuilder &Builder) const { 418 // PSP defines; list based on the output of the pspdev gcc toolchain. 419 Builder.defineMacro("PSP"); 420 Builder.defineMacro("_PSP"); 421 Builder.defineMacro("__psp__"); 422 Builder.defineMacro("__ELF__"); 423 } 424 public: 425 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 426 this->UserLabelPrefix = ""; 427 } 428 }; 429 430 // PS3 PPU Target 431 template<typename Target> 432 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 433 protected: 434 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 435 MacroBuilder &Builder) const { 436 // PS3 PPU defines. 437 Builder.defineMacro("__PPC__"); 438 Builder.defineMacro("__PPU__"); 439 Builder.defineMacro("__CELLOS_LV2__"); 440 Builder.defineMacro("__ELF__"); 441 Builder.defineMacro("__LP32__"); 442 Builder.defineMacro("_ARCH_PPC64"); 443 Builder.defineMacro("__powerpc64__"); 444 } 445 public: 446 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 447 this->UserLabelPrefix = ""; 448 this->LongWidth = this->LongAlign = 32; 449 this->PointerWidth = this->PointerAlign = 32; 450 this->IntMaxType = TargetInfo::SignedLongLong; 451 this->UIntMaxType = TargetInfo::UnsignedLongLong; 452 this->Int64Type = TargetInfo::SignedLongLong; 453 this->SizeType = TargetInfo::UnsignedInt; 454 this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 455 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 456 } 457 }; 458 459 // FIXME: Need a real SPU target. 460 // PS3 SPU Target 461 template<typename Target> 462 class PS3SPUTargetInfo : public OSTargetInfo<Target> { 463 protected: 464 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 465 MacroBuilder &Builder) const { 466 // PS3 PPU defines. 467 Builder.defineMacro("__SPU__"); 468 Builder.defineMacro("__ELF__"); 469 } 470 public: 471 PS3SPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 472 this->UserLabelPrefix = ""; 473 } 474 }; 475 476 // AuroraUX target 477 template<typename Target> 478 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 479 protected: 480 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 481 MacroBuilder &Builder) const { 482 DefineStd(Builder, "sun", Opts); 483 DefineStd(Builder, "unix", Opts); 484 Builder.defineMacro("__ELF__"); 485 Builder.defineMacro("__svr4__"); 486 Builder.defineMacro("__SVR4"); 487 } 488 public: 489 AuroraUXTargetInfo(const llvm::Triple &Triple) 490 : OSTargetInfo<Target>(Triple) { 491 this->UserLabelPrefix = ""; 492 this->WCharType = this->SignedLong; 493 // FIXME: WIntType should be SignedLong 494 } 495 }; 496 497 // Solaris target 498 template<typename Target> 499 class SolarisTargetInfo : public OSTargetInfo<Target> { 500 protected: 501 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 502 MacroBuilder &Builder) const { 503 DefineStd(Builder, "sun", Opts); 504 DefineStd(Builder, "unix", Opts); 505 Builder.defineMacro("__ELF__"); 506 Builder.defineMacro("__svr4__"); 507 Builder.defineMacro("__SVR4"); 508 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 509 // newer, but to 500 for everything else. feature_test.h has a check to 510 // ensure that you are not using C99 with an old version of X/Open or C89 511 // with a new version. 512 if (Opts.C99 || Opts.C11) 513 Builder.defineMacro("_XOPEN_SOURCE", "600"); 514 else 515 Builder.defineMacro("_XOPEN_SOURCE", "500"); 516 if (Opts.CPlusPlus) 517 Builder.defineMacro("__C99FEATURES__"); 518 Builder.defineMacro("_LARGEFILE_SOURCE"); 519 Builder.defineMacro("_LARGEFILE64_SOURCE"); 520 Builder.defineMacro("__EXTENSIONS__"); 521 Builder.defineMacro("_REENTRANT"); 522 } 523 public: 524 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 525 this->UserLabelPrefix = ""; 526 this->WCharType = this->SignedInt; 527 // FIXME: WIntType should be SignedLong 528 } 529 }; 530 531 // Windows target 532 template<typename Target> 533 class WindowsTargetInfo : public OSTargetInfo<Target> { 534 protected: 535 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 536 MacroBuilder &Builder) const { 537 Builder.defineMacro("_WIN32"); 538 } 539 void getVisualStudioDefines(const LangOptions &Opts, 540 MacroBuilder &Builder) const { 541 if (Opts.CPlusPlus) { 542 if (Opts.RTTI) 543 Builder.defineMacro("_CPPRTTI"); 544 545 if (Opts.Exceptions) 546 Builder.defineMacro("_CPPUNWIND"); 547 } 548 549 if (!Opts.CharIsSigned) 550 Builder.defineMacro("_CHAR_UNSIGNED"); 551 552 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 553 // but it works for now. 554 if (Opts.POSIXThreads) 555 Builder.defineMacro("_MT"); 556 557 if (Opts.MSCVersion != 0) 558 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 559 560 if (Opts.MicrosoftExt) { 561 Builder.defineMacro("_MSC_EXTENSIONS"); 562 563 if (Opts.CPlusPlus11) { 564 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 565 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 566 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 567 } 568 } 569 570 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 571 } 572 573 public: 574 WindowsTargetInfo(const llvm::Triple &Triple) 575 : OSTargetInfo<Target>(Triple) {} 576 }; 577 578 template <typename Target> 579 class NaClTargetInfo : public OSTargetInfo<Target> { 580 protected: 581 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 582 MacroBuilder &Builder) const { 583 if (Opts.POSIXThreads) 584 Builder.defineMacro("_REENTRANT"); 585 if (Opts.CPlusPlus) 586 Builder.defineMacro("_GNU_SOURCE"); 587 588 DefineStd(Builder, "unix", Opts); 589 Builder.defineMacro("__ELF__"); 590 Builder.defineMacro("__native_client__"); 591 } 592 593 public: 594 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 595 this->UserLabelPrefix = ""; 596 this->LongAlign = 32; 597 this->LongWidth = 32; 598 this->PointerAlign = 32; 599 this->PointerWidth = 32; 600 this->IntMaxType = TargetInfo::SignedLongLong; 601 this->UIntMaxType = TargetInfo::UnsignedLongLong; 602 this->Int64Type = TargetInfo::SignedLongLong; 603 this->DoubleAlign = 64; 604 this->LongDoubleWidth = 64; 605 this->LongDoubleAlign = 64; 606 this->SizeType = TargetInfo::UnsignedInt; 607 this->PtrDiffType = TargetInfo::SignedInt; 608 this->IntPtrType = TargetInfo::SignedInt; 609 // RegParmMax is inherited from the underlying architecture 610 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 611 this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 612 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 613 } 614 virtual typename Target::CallingConvCheckResult checkCallingConvention( 615 CallingConv CC) const { 616 return CC == CC_PnaclCall ? Target::CCCR_OK : 617 Target::checkCallingConvention(CC); 618 } 619 }; 620 } // end anonymous namespace. 621 622 //===----------------------------------------------------------------------===// 623 // Specific target implementations. 624 //===----------------------------------------------------------------------===// 625 626 namespace { 627 // PPC abstract base class 628 class PPCTargetInfo : public TargetInfo { 629 static const Builtin::Info BuiltinInfo[]; 630 static const char * const GCCRegNames[]; 631 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 632 std::string CPU; 633 public: 634 PPCTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 635 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 636 LongDoubleWidth = LongDoubleAlign = 128; 637 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 638 } 639 640 /// \brief Flags for architecture specific defines. 641 typedef enum { 642 ArchDefineNone = 0, 643 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 644 ArchDefinePpcgr = 1 << 1, 645 ArchDefinePpcsq = 1 << 2, 646 ArchDefine440 = 1 << 3, 647 ArchDefine603 = 1 << 4, 648 ArchDefine604 = 1 << 5, 649 ArchDefinePwr4 = 1 << 6, 650 ArchDefinePwr5 = 1 << 7, 651 ArchDefinePwr5x = 1 << 8, 652 ArchDefinePwr6 = 1 << 9, 653 ArchDefinePwr6x = 1 << 10, 654 ArchDefinePwr7 = 1 << 11, 655 ArchDefineA2 = 1 << 12, 656 ArchDefineA2q = 1 << 13 657 } ArchDefineTypes; 658 659 // Note: GCC recognizes the following additional cpus: 660 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 661 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 662 // titan, rs64. 663 virtual bool setCPU(const std::string &Name) { 664 bool CPUKnown = llvm::StringSwitch<bool>(Name) 665 .Case("generic", true) 666 .Case("440", true) 667 .Case("450", true) 668 .Case("601", true) 669 .Case("602", true) 670 .Case("603", true) 671 .Case("603e", true) 672 .Case("603ev", true) 673 .Case("604", true) 674 .Case("604e", true) 675 .Case("620", true) 676 .Case("630", true) 677 .Case("g3", true) 678 .Case("7400", true) 679 .Case("g4", true) 680 .Case("7450", true) 681 .Case("g4+", true) 682 .Case("750", true) 683 .Case("970", true) 684 .Case("g5", true) 685 .Case("a2", true) 686 .Case("a2q", true) 687 .Case("e500mc", true) 688 .Case("e5500", true) 689 .Case("power3", true) 690 .Case("pwr3", true) 691 .Case("power4", true) 692 .Case("pwr4", true) 693 .Case("power5", true) 694 .Case("pwr5", true) 695 .Case("power5x", true) 696 .Case("pwr5x", true) 697 .Case("power6", true) 698 .Case("pwr6", true) 699 .Case("power6x", true) 700 .Case("pwr6x", true) 701 .Case("power7", true) 702 .Case("pwr7", true) 703 .Case("powerpc", true) 704 .Case("ppc", true) 705 .Case("powerpc64", true) 706 .Case("ppc64", true) 707 .Case("powerpc64le", true) 708 .Case("ppc64le", true) 709 .Default(false); 710 711 if (CPUKnown) 712 CPU = Name; 713 714 return CPUKnown; 715 } 716 717 virtual void getTargetBuiltins(const Builtin::Info *&Records, 718 unsigned &NumRecords) const { 719 Records = BuiltinInfo; 720 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 721 } 722 723 virtual bool isCLZForZeroUndef() const { return false; } 724 725 virtual void getTargetDefines(const LangOptions &Opts, 726 MacroBuilder &Builder) const; 727 728 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 729 730 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 731 StringRef Name, 732 bool Enabled) const; 733 734 virtual bool hasFeature(StringRef Feature) const; 735 736 virtual void getGCCRegNames(const char * const *&Names, 737 unsigned &NumNames) const; 738 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 739 unsigned &NumAliases) const; 740 virtual bool validateAsmConstraint(const char *&Name, 741 TargetInfo::ConstraintInfo &Info) const { 742 switch (*Name) { 743 default: return false; 744 case 'O': // Zero 745 break; 746 case 'b': // Base register 747 case 'f': // Floating point register 748 Info.setAllowsRegister(); 749 break; 750 // FIXME: The following are added to allow parsing. 751 // I just took a guess at what the actions should be. 752 // Also, is more specific checking needed? I.e. specific registers? 753 case 'd': // Floating point register (containing 64-bit value) 754 case 'v': // Altivec vector register 755 Info.setAllowsRegister(); 756 break; 757 case 'w': 758 switch (Name[1]) { 759 case 'd':// VSX vector register to hold vector double data 760 case 'f':// VSX vector register to hold vector float data 761 case 's':// VSX vector register to hold scalar float data 762 case 'a':// Any VSX register 763 break; 764 default: 765 return false; 766 } 767 Info.setAllowsRegister(); 768 Name++; // Skip over 'w'. 769 break; 770 case 'h': // `MQ', `CTR', or `LINK' register 771 case 'q': // `MQ' register 772 case 'c': // `CTR' register 773 case 'l': // `LINK' register 774 case 'x': // `CR' register (condition register) number 0 775 case 'y': // `CR' register (condition register) 776 case 'z': // `XER[CA]' carry bit (part of the XER register) 777 Info.setAllowsRegister(); 778 break; 779 case 'I': // Signed 16-bit constant 780 case 'J': // Unsigned 16-bit constant shifted left 16 bits 781 // (use `L' instead for SImode constants) 782 case 'K': // Unsigned 16-bit constant 783 case 'L': // Signed 16-bit constant shifted left 16 bits 784 case 'M': // Constant larger than 31 785 case 'N': // Exact power of 2 786 case 'P': // Constant whose negation is a signed 16-bit constant 787 case 'G': // Floating point constant that can be loaded into a 788 // register with one instruction per word 789 case 'H': // Integer/Floating point constant that can be loaded 790 // into a register using three instructions 791 break; 792 case 'm': // Memory operand. Note that on PowerPC targets, m can 793 // include addresses that update the base register. It 794 // is therefore only safe to use `m' in an asm statement 795 // if that asm statement accesses the operand exactly once. 796 // The asm statement must also use `%U<opno>' as a 797 // placeholder for the "update" flag in the corresponding 798 // load or store instruction. For example: 799 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 800 // is correct but: 801 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 802 // is not. Use es rather than m if you don't want the base 803 // register to be updated. 804 case 'e': 805 if (Name[1] != 's') 806 return false; 807 // es: A "stable" memory operand; that is, one which does not 808 // include any automodification of the base register. Unlike 809 // `m', this constraint can be used in asm statements that 810 // might access the operand several times, or that might not 811 // access it at all. 812 Info.setAllowsMemory(); 813 Name++; // Skip over 'e'. 814 break; 815 case 'Q': // Memory operand that is an offset from a register (it is 816 // usually better to use `m' or `es' in asm statements) 817 case 'Z': // Memory operand that is an indexed or indirect from a 818 // register (it is usually better to use `m' or `es' in 819 // asm statements) 820 Info.setAllowsMemory(); 821 Info.setAllowsRegister(); 822 break; 823 case 'R': // AIX TOC entry 824 case 'a': // Address operand that is an indexed or indirect from a 825 // register (`p' is preferable for asm statements) 826 case 'S': // Constant suitable as a 64-bit mask operand 827 case 'T': // Constant suitable as a 32-bit mask operand 828 case 'U': // System V Release 4 small data area reference 829 case 't': // AND masks that can be performed by two rldic{l, r} 830 // instructions 831 case 'W': // Vector constant that does not require memory 832 case 'j': // Vector constant that is all zeros. 833 break; 834 // End FIXME. 835 } 836 return true; 837 } 838 virtual const char *getClobbers() const { 839 return ""; 840 } 841 int getEHDataRegisterNumber(unsigned RegNo) const { 842 if (RegNo == 0) return 3; 843 if (RegNo == 1) return 4; 844 return -1; 845 } 846 }; 847 848 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 849 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 850 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 851 ALL_LANGUAGES }, 852 #include "clang/Basic/BuiltinsPPC.def" 853 }; 854 855 856 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 857 /// #defines that are not tied to a specific subtarget. 858 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 859 MacroBuilder &Builder) const { 860 // Target identification. 861 Builder.defineMacro("__ppc__"); 862 Builder.defineMacro("__PPC__"); 863 Builder.defineMacro("_ARCH_PPC"); 864 Builder.defineMacro("__powerpc__"); 865 Builder.defineMacro("__POWERPC__"); 866 if (PointerWidth == 64) { 867 Builder.defineMacro("_ARCH_PPC64"); 868 Builder.defineMacro("__powerpc64__"); 869 Builder.defineMacro("__ppc64__"); 870 Builder.defineMacro("__PPC64__"); 871 } 872 873 // Target properties. 874 if (getTriple().getArch() == llvm::Triple::ppc64le) { 875 Builder.defineMacro("_LITTLE_ENDIAN"); 876 Builder.defineMacro("__LITTLE_ENDIAN__"); 877 } else { 878 if (getTriple().getOS() != llvm::Triple::NetBSD && 879 getTriple().getOS() != llvm::Triple::OpenBSD) 880 Builder.defineMacro("_BIG_ENDIAN"); 881 Builder.defineMacro("__BIG_ENDIAN__"); 882 } 883 884 // Subtarget options. 885 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 886 Builder.defineMacro("__REGISTER_PREFIX__", ""); 887 888 // FIXME: Should be controlled by command line option. 889 if (LongDoubleWidth == 128) 890 Builder.defineMacro("__LONG_DOUBLE_128__"); 891 892 if (Opts.AltiVec) { 893 Builder.defineMacro("__VEC__", "10206"); 894 Builder.defineMacro("__ALTIVEC__"); 895 } 896 897 // CPU identification. 898 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 899 .Case("440", ArchDefineName) 900 .Case("450", ArchDefineName | ArchDefine440) 901 .Case("601", ArchDefineName) 902 .Case("602", ArchDefineName | ArchDefinePpcgr) 903 .Case("603", ArchDefineName | ArchDefinePpcgr) 904 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 905 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 906 .Case("604", ArchDefineName | ArchDefinePpcgr) 907 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 908 .Case("620", ArchDefineName | ArchDefinePpcgr) 909 .Case("630", ArchDefineName | ArchDefinePpcgr) 910 .Case("7400", ArchDefineName | ArchDefinePpcgr) 911 .Case("7450", ArchDefineName | ArchDefinePpcgr) 912 .Case("750", ArchDefineName | ArchDefinePpcgr) 913 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 914 | ArchDefinePpcsq) 915 .Case("a2", ArchDefineA2) 916 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 917 .Case("pwr3", ArchDefinePpcgr) 918 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 919 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 920 | ArchDefinePpcsq) 921 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 922 | ArchDefinePpcgr | ArchDefinePpcsq) 923 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 924 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 925 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 926 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 927 | ArchDefinePpcsq) 928 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 929 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 930 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 931 .Case("power3", ArchDefinePpcgr) 932 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 933 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 934 | ArchDefinePpcsq) 935 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 936 | ArchDefinePpcgr | ArchDefinePpcsq) 937 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 938 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 939 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 940 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 941 | ArchDefinePpcsq) 942 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 943 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 944 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 945 .Default(ArchDefineNone); 946 947 if (defs & ArchDefineName) 948 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 949 if (defs & ArchDefinePpcgr) 950 Builder.defineMacro("_ARCH_PPCGR"); 951 if (defs & ArchDefinePpcsq) 952 Builder.defineMacro("_ARCH_PPCSQ"); 953 if (defs & ArchDefine440) 954 Builder.defineMacro("_ARCH_440"); 955 if (defs & ArchDefine603) 956 Builder.defineMacro("_ARCH_603"); 957 if (defs & ArchDefine604) 958 Builder.defineMacro("_ARCH_604"); 959 if (defs & ArchDefinePwr4) 960 Builder.defineMacro("_ARCH_PWR4"); 961 if (defs & ArchDefinePwr5) 962 Builder.defineMacro("_ARCH_PWR5"); 963 if (defs & ArchDefinePwr5x) 964 Builder.defineMacro("_ARCH_PWR5X"); 965 if (defs & ArchDefinePwr6) 966 Builder.defineMacro("_ARCH_PWR6"); 967 if (defs & ArchDefinePwr6x) 968 Builder.defineMacro("_ARCH_PWR6X"); 969 if (defs & ArchDefinePwr7) 970 Builder.defineMacro("_ARCH_PWR7"); 971 if (defs & ArchDefineA2) 972 Builder.defineMacro("_ARCH_A2"); 973 if (defs & ArchDefineA2q) { 974 Builder.defineMacro("_ARCH_A2Q"); 975 Builder.defineMacro("_ARCH_QP"); 976 } 977 978 if (getTriple().getVendor() == llvm::Triple::BGQ) { 979 Builder.defineMacro("__bg__"); 980 Builder.defineMacro("__THW_BLUEGENE__"); 981 Builder.defineMacro("__bgq__"); 982 Builder.defineMacro("__TOS_BGQ__"); 983 } 984 985 // FIXME: The following are not yet generated here by Clang, but are 986 // generated by GCC: 987 // 988 // _SOFT_FLOAT_ 989 // __RECIP_PRECISION__ 990 // __APPLE_ALTIVEC__ 991 // __VSX__ 992 // __RECIP__ 993 // __RECIPF__ 994 // __RSQRTE__ 995 // __RSQRTEF__ 996 // _SOFT_DOUBLE_ 997 // __NO_LWSYNC__ 998 // __HAVE_BSWAP__ 999 // __LONGDOUBLE128 1000 // __CMODEL_MEDIUM__ 1001 // __CMODEL_LARGE__ 1002 // _CALL_SYSV 1003 // _CALL_DARWIN 1004 // __NO_FPRS__ 1005 } 1006 1007 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1008 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1009 .Case("7400", true) 1010 .Case("g4", true) 1011 .Case("7450", true) 1012 .Case("g4+", true) 1013 .Case("970", true) 1014 .Case("g5", true) 1015 .Case("pwr6", true) 1016 .Case("pwr7", true) 1017 .Case("ppc64", true) 1018 .Case("ppc64le", true) 1019 .Default(false); 1020 1021 Features["qpx"] = (CPU == "a2q"); 1022 } 1023 1024 bool PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1025 StringRef Name, 1026 bool Enabled) const { 1027 if (Name == "altivec" || Name == "fprnd" || Name == "mfocrf" || 1028 Name == "popcntd" || Name == "qpx") { 1029 Features[Name] = Enabled; 1030 return true; 1031 } 1032 1033 return false; 1034 } 1035 1036 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1037 return Feature == "powerpc"; 1038 } 1039 1040 1041 const char * const PPCTargetInfo::GCCRegNames[] = { 1042 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1043 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1044 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1045 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1046 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1047 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1048 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1049 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1050 "mq", "lr", "ctr", "ap", 1051 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1052 "xer", 1053 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1054 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1055 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1056 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1057 "vrsave", "vscr", 1058 "spe_acc", "spefscr", 1059 "sfp" 1060 }; 1061 1062 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1063 unsigned &NumNames) const { 1064 Names = GCCRegNames; 1065 NumNames = llvm::array_lengthof(GCCRegNames); 1066 } 1067 1068 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1069 // While some of these aliases do map to different registers 1070 // they still share the same register name. 1071 { { "0" }, "r0" }, 1072 { { "1"}, "r1" }, 1073 { { "2" }, "r2" }, 1074 { { "3" }, "r3" }, 1075 { { "4" }, "r4" }, 1076 { { "5" }, "r5" }, 1077 { { "6" }, "r6" }, 1078 { { "7" }, "r7" }, 1079 { { "8" }, "r8" }, 1080 { { "9" }, "r9" }, 1081 { { "10" }, "r10" }, 1082 { { "11" }, "r11" }, 1083 { { "12" }, "r12" }, 1084 { { "13" }, "r13" }, 1085 { { "14" }, "r14" }, 1086 { { "15" }, "r15" }, 1087 { { "16" }, "r16" }, 1088 { { "17" }, "r17" }, 1089 { { "18" }, "r18" }, 1090 { { "19" }, "r19" }, 1091 { { "20" }, "r20" }, 1092 { { "21" }, "r21" }, 1093 { { "22" }, "r22" }, 1094 { { "23" }, "r23" }, 1095 { { "24" }, "r24" }, 1096 { { "25" }, "r25" }, 1097 { { "26" }, "r26" }, 1098 { { "27" }, "r27" }, 1099 { { "28" }, "r28" }, 1100 { { "29" }, "r29" }, 1101 { { "30" }, "r30" }, 1102 { { "31" }, "r31" }, 1103 { { "fr0" }, "f0" }, 1104 { { "fr1" }, "f1" }, 1105 { { "fr2" }, "f2" }, 1106 { { "fr3" }, "f3" }, 1107 { { "fr4" }, "f4" }, 1108 { { "fr5" }, "f5" }, 1109 { { "fr6" }, "f6" }, 1110 { { "fr7" }, "f7" }, 1111 { { "fr8" }, "f8" }, 1112 { { "fr9" }, "f9" }, 1113 { { "fr10" }, "f10" }, 1114 { { "fr11" }, "f11" }, 1115 { { "fr12" }, "f12" }, 1116 { { "fr13" }, "f13" }, 1117 { { "fr14" }, "f14" }, 1118 { { "fr15" }, "f15" }, 1119 { { "fr16" }, "f16" }, 1120 { { "fr17" }, "f17" }, 1121 { { "fr18" }, "f18" }, 1122 { { "fr19" }, "f19" }, 1123 { { "fr20" }, "f20" }, 1124 { { "fr21" }, "f21" }, 1125 { { "fr22" }, "f22" }, 1126 { { "fr23" }, "f23" }, 1127 { { "fr24" }, "f24" }, 1128 { { "fr25" }, "f25" }, 1129 { { "fr26" }, "f26" }, 1130 { { "fr27" }, "f27" }, 1131 { { "fr28" }, "f28" }, 1132 { { "fr29" }, "f29" }, 1133 { { "fr30" }, "f30" }, 1134 { { "fr31" }, "f31" }, 1135 { { "cc" }, "cr0" }, 1136 }; 1137 1138 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1139 unsigned &NumAliases) const { 1140 Aliases = GCCRegAliases; 1141 NumAliases = llvm::array_lengthof(GCCRegAliases); 1142 } 1143 } // end anonymous namespace. 1144 1145 namespace { 1146 class PPC32TargetInfo : public PPCTargetInfo { 1147 public: 1148 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1149 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1150 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1151 1152 switch (getTriple().getOS()) { 1153 case llvm::Triple::Linux: 1154 case llvm::Triple::FreeBSD: 1155 case llvm::Triple::NetBSD: 1156 SizeType = UnsignedInt; 1157 PtrDiffType = SignedInt; 1158 IntPtrType = SignedInt; 1159 break; 1160 default: 1161 break; 1162 } 1163 1164 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1165 LongDoubleWidth = LongDoubleAlign = 64; 1166 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1167 } 1168 1169 // PPC32 supports atomics up to 4 bytes. 1170 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1171 } 1172 1173 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1174 // This is the ELF definition, and is overridden by the Darwin sub-target 1175 return TargetInfo::PowerABIBuiltinVaList; 1176 } 1177 }; 1178 } // end anonymous namespace. 1179 1180 // Note: ABI differences may eventually require us to have a separate 1181 // TargetInfo for little endian. 1182 namespace { 1183 class PPC64TargetInfo : public PPCTargetInfo { 1184 public: 1185 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1186 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1187 IntMaxType = SignedLong; 1188 UIntMaxType = UnsignedLong; 1189 Int64Type = SignedLong; 1190 1191 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1192 LongDoubleWidth = LongDoubleAlign = 64; 1193 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1194 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1195 "i64:64:64-f32:32:32-f64:64:64-" 1196 "v128:128:128-n32:64"; 1197 } else 1198 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1199 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 1200 "v128:128:128-n32:64"; 1201 1202 // PPC64 supports atomics up to 8 bytes. 1203 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1204 } 1205 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1206 return TargetInfo::CharPtrBuiltinVaList; 1207 } 1208 }; 1209 } // end anonymous namespace. 1210 1211 1212 namespace { 1213 class DarwinPPC32TargetInfo : 1214 public DarwinTargetInfo<PPC32TargetInfo> { 1215 public: 1216 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1217 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1218 HasAlignMac68kSupport = true; 1219 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1220 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1221 LongLongAlign = 32; 1222 SuitableAlign = 128; 1223 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1224 "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1225 } 1226 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1227 return TargetInfo::CharPtrBuiltinVaList; 1228 } 1229 }; 1230 1231 class DarwinPPC64TargetInfo : 1232 public DarwinTargetInfo<PPC64TargetInfo> { 1233 public: 1234 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1235 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1236 HasAlignMac68kSupport = true; 1237 SuitableAlign = 128; 1238 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1239 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"; 1240 } 1241 }; 1242 } // end anonymous namespace. 1243 1244 namespace { 1245 static const unsigned NVPTXAddrSpaceMap[] = { 1246 1, // opencl_global 1247 3, // opencl_local 1248 4, // opencl_constant 1249 1, // cuda_device 1250 4, // cuda_constant 1251 3, // cuda_shared 1252 }; 1253 class NVPTXTargetInfo : public TargetInfo { 1254 static const char * const GCCRegNames[]; 1255 static const Builtin::Info BuiltinInfo[]; 1256 std::vector<StringRef> AvailableFeatures; 1257 public: 1258 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1259 BigEndian = false; 1260 TLSSupported = false; 1261 LongWidth = LongAlign = 64; 1262 AddrSpaceMap = &NVPTXAddrSpaceMap; 1263 // Define available target features 1264 // These must be defined in sorted order! 1265 NoAsmVariants = true; 1266 } 1267 virtual void getTargetDefines(const LangOptions &Opts, 1268 MacroBuilder &Builder) const { 1269 Builder.defineMacro("__PTX__"); 1270 Builder.defineMacro("__NVPTX__"); 1271 } 1272 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1273 unsigned &NumRecords) const { 1274 Records = BuiltinInfo; 1275 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1276 } 1277 virtual bool hasFeature(StringRef Feature) const { 1278 return Feature == "ptx" || Feature == "nvptx"; 1279 } 1280 1281 virtual void getGCCRegNames(const char * const *&Names, 1282 unsigned &NumNames) const; 1283 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1284 unsigned &NumAliases) const { 1285 // No aliases. 1286 Aliases = 0; 1287 NumAliases = 0; 1288 } 1289 virtual bool validateAsmConstraint(const char *&Name, 1290 TargetInfo::ConstraintInfo &Info) const { 1291 switch (*Name) { 1292 default: return false; 1293 case 'c': 1294 case 'h': 1295 case 'r': 1296 case 'l': 1297 case 'f': 1298 case 'd': 1299 Info.setAllowsRegister(); 1300 return true; 1301 } 1302 } 1303 virtual const char *getClobbers() const { 1304 // FIXME: Is this really right? 1305 return ""; 1306 } 1307 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1308 // FIXME: implement 1309 return TargetInfo::CharPtrBuiltinVaList; 1310 } 1311 virtual bool setCPU(const std::string &Name) { 1312 bool Valid = llvm::StringSwitch<bool>(Name) 1313 .Case("sm_20", true) 1314 .Case("sm_21", true) 1315 .Case("sm_30", true) 1316 .Case("sm_35", true) 1317 .Default(false); 1318 1319 return Valid; 1320 } 1321 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 1322 StringRef Name, 1323 bool Enabled) const; 1324 }; 1325 1326 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1327 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1328 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1329 ALL_LANGUAGES }, 1330 #include "clang/Basic/BuiltinsNVPTX.def" 1331 }; 1332 1333 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1334 "r0" 1335 }; 1336 1337 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1338 unsigned &NumNames) const { 1339 Names = GCCRegNames; 1340 NumNames = llvm::array_lengthof(GCCRegNames); 1341 } 1342 1343 bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1344 StringRef Name, 1345 bool Enabled) const { 1346 if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(), 1347 Name)) { 1348 Features[Name] = Enabled; 1349 return true; 1350 } else { 1351 return false; 1352 } 1353 } 1354 1355 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1356 public: 1357 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1358 PointerWidth = PointerAlign = 32; 1359 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1360 DescriptionString 1361 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1362 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1363 "n16:32:64"; 1364 } 1365 }; 1366 1367 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1368 public: 1369 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1370 PointerWidth = PointerAlign = 64; 1371 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1372 DescriptionString 1373 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1374 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1375 "n16:32:64"; 1376 } 1377 }; 1378 } 1379 1380 namespace { 1381 1382 static const unsigned R600AddrSpaceMap[] = { 1383 1, // opencl_global 1384 3, // opencl_local 1385 2, // opencl_constant 1386 1, // cuda_device 1387 2, // cuda_constant 1388 3 // cuda_shared 1389 }; 1390 1391 static const char *DescriptionStringR600 = 1392 "e" 1393 "-p:32:32:32" 1394 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32" 1395 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1396 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1397 "-n32:64"; 1398 1399 static const char *DescriptionStringR600DoubleOps = 1400 "e" 1401 "-p:32:32:32" 1402 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64" 1403 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1404 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1405 "-n32:64"; 1406 1407 static const char *DescriptionStringSI = 1408 "e" 1409 "-p:64:64:64" 1410 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64" 1411 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1412 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1413 "-n32:64"; 1414 1415 class R600TargetInfo : public TargetInfo { 1416 /// \brief The GPU profiles supported by the R600 target. 1417 enum GPUKind { 1418 GK_NONE, 1419 GK_R600, 1420 GK_R600_DOUBLE_OPS, 1421 GK_R700, 1422 GK_R700_DOUBLE_OPS, 1423 GK_EVERGREEN, 1424 GK_EVERGREEN_DOUBLE_OPS, 1425 GK_NORTHERN_ISLANDS, 1426 GK_CAYMAN, 1427 GK_SOUTHERN_ISLANDS 1428 } GPU; 1429 1430 public: 1431 R600TargetInfo(const llvm::Triple &Triple) 1432 : TargetInfo(Triple), GPU(GK_R600) { 1433 DescriptionString = DescriptionStringR600; 1434 AddrSpaceMap = &R600AddrSpaceMap; 1435 } 1436 1437 virtual const char * getClobbers() const { 1438 return ""; 1439 } 1440 1441 virtual void getGCCRegNames(const char * const *&Names, 1442 unsigned &numNames) const { 1443 Names = NULL; 1444 numNames = 0; 1445 } 1446 1447 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1448 unsigned &NumAliases) const { 1449 Aliases = NULL; 1450 NumAliases = 0; 1451 } 1452 1453 virtual bool validateAsmConstraint(const char *&Name, 1454 TargetInfo::ConstraintInfo &info) const { 1455 return true; 1456 } 1457 1458 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1459 unsigned &NumRecords) const { 1460 Records = NULL; 1461 NumRecords = 0; 1462 } 1463 1464 1465 virtual void getTargetDefines(const LangOptions &Opts, 1466 MacroBuilder &Builder) const { 1467 Builder.defineMacro("__R600__"); 1468 } 1469 1470 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1471 return TargetInfo::CharPtrBuiltinVaList; 1472 } 1473 1474 virtual bool setCPU(const std::string &Name) { 1475 GPU = llvm::StringSwitch<GPUKind>(Name) 1476 .Case("r600" , GK_R600) 1477 .Case("rv610", GK_R600) 1478 .Case("rv620", GK_R600) 1479 .Case("rv630", GK_R600) 1480 .Case("rv635", GK_R600) 1481 .Case("rs780", GK_R600) 1482 .Case("rs880", GK_R600) 1483 .Case("rv670", GK_R600_DOUBLE_OPS) 1484 .Case("rv710", GK_R700) 1485 .Case("rv730", GK_R700) 1486 .Case("rv740", GK_R700_DOUBLE_OPS) 1487 .Case("rv770", GK_R700_DOUBLE_OPS) 1488 .Case("palm", GK_EVERGREEN) 1489 .Case("cedar", GK_EVERGREEN) 1490 .Case("sumo", GK_EVERGREEN) 1491 .Case("sumo2", GK_EVERGREEN) 1492 .Case("redwood", GK_EVERGREEN) 1493 .Case("juniper", GK_EVERGREEN) 1494 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1495 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1496 .Case("barts", GK_NORTHERN_ISLANDS) 1497 .Case("turks", GK_NORTHERN_ISLANDS) 1498 .Case("caicos", GK_NORTHERN_ISLANDS) 1499 .Case("cayman", GK_CAYMAN) 1500 .Case("aruba", GK_CAYMAN) 1501 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1502 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1503 .Case("verde", GK_SOUTHERN_ISLANDS) 1504 .Case("oland", GK_SOUTHERN_ISLANDS) 1505 .Default(GK_NONE); 1506 1507 if (GPU == GK_NONE) { 1508 return false; 1509 } 1510 1511 // Set the correct data layout 1512 switch (GPU) { 1513 case GK_NONE: 1514 case GK_R600: 1515 case GK_R700: 1516 case GK_EVERGREEN: 1517 case GK_NORTHERN_ISLANDS: 1518 DescriptionString = DescriptionStringR600; 1519 break; 1520 case GK_R600_DOUBLE_OPS: 1521 case GK_R700_DOUBLE_OPS: 1522 case GK_EVERGREEN_DOUBLE_OPS: 1523 case GK_CAYMAN: 1524 DescriptionString = DescriptionStringR600DoubleOps; 1525 break; 1526 case GK_SOUTHERN_ISLANDS: 1527 DescriptionString = DescriptionStringSI; 1528 break; 1529 } 1530 1531 return true; 1532 } 1533 }; 1534 1535 } // end anonymous namespace 1536 1537 namespace { 1538 // Namespace for x86 abstract base class 1539 const Builtin::Info BuiltinInfo[] = { 1540 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1541 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1542 ALL_LANGUAGES }, 1543 #include "clang/Basic/BuiltinsX86.def" 1544 }; 1545 1546 static const char* const GCCRegNames[] = { 1547 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1548 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1549 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1550 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1551 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1552 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1553 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1554 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1555 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1556 }; 1557 1558 const TargetInfo::AddlRegName AddlRegNames[] = { 1559 { { "al", "ah", "eax", "rax" }, 0 }, 1560 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1561 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1562 { { "dl", "dh", "edx", "rdx" }, 1 }, 1563 { { "esi", "rsi" }, 4 }, 1564 { { "edi", "rdi" }, 5 }, 1565 { { "esp", "rsp" }, 7 }, 1566 { { "ebp", "rbp" }, 6 }, 1567 }; 1568 1569 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1570 // most of the implementation can be shared. 1571 class X86TargetInfo : public TargetInfo { 1572 enum X86SSEEnum { 1573 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2 1574 } SSELevel; 1575 enum MMX3DNowEnum { 1576 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1577 } MMX3DNowLevel; 1578 1579 bool HasAES; 1580 bool HasPCLMUL; 1581 bool HasLZCNT; 1582 bool HasRDRND; 1583 bool HasBMI; 1584 bool HasBMI2; 1585 bool HasPOPCNT; 1586 bool HasRTM; 1587 bool HasPRFCHW; 1588 bool HasRDSEED; 1589 bool HasSSE4a; 1590 bool HasFMA4; 1591 bool HasFMA; 1592 bool HasXOP; 1593 bool HasF16C; 1594 1595 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1596 /// 1597 /// Each enumeration represents a particular CPU supported by Clang. These 1598 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1599 enum CPUKind { 1600 CK_Generic, 1601 1602 /// \name i386 1603 /// i386-generation processors. 1604 //@{ 1605 CK_i386, 1606 //@} 1607 1608 /// \name i486 1609 /// i486-generation processors. 1610 //@{ 1611 CK_i486, 1612 CK_WinChipC6, 1613 CK_WinChip2, 1614 CK_C3, 1615 //@} 1616 1617 /// \name i586 1618 /// i586-generation processors, P5 microarchitecture based. 1619 //@{ 1620 CK_i586, 1621 CK_Pentium, 1622 CK_PentiumMMX, 1623 //@} 1624 1625 /// \name i686 1626 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1627 //@{ 1628 CK_i686, 1629 CK_PentiumPro, 1630 CK_Pentium2, 1631 CK_Pentium3, 1632 CK_Pentium3M, 1633 CK_PentiumM, 1634 CK_C3_2, 1635 1636 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1637 /// Clang however has some logic to suport this. 1638 // FIXME: Warn, deprecate, and potentially remove this. 1639 CK_Yonah, 1640 //@} 1641 1642 /// \name Netburst 1643 /// Netburst microarchitecture based processors. 1644 //@{ 1645 CK_Pentium4, 1646 CK_Pentium4M, 1647 CK_Prescott, 1648 CK_Nocona, 1649 //@} 1650 1651 /// \name Core 1652 /// Core microarchitecture based processors. 1653 //@{ 1654 CK_Core2, 1655 1656 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1657 /// codename which GCC no longer accepts as an option to -march, but Clang 1658 /// has some logic for recognizing it. 1659 // FIXME: Warn, deprecate, and potentially remove this. 1660 CK_Penryn, 1661 //@} 1662 1663 /// \name Atom 1664 /// Atom processors 1665 //@{ 1666 CK_Atom, 1667 //@} 1668 1669 /// \name Nehalem 1670 /// Nehalem microarchitecture based processors. 1671 //@{ 1672 CK_Corei7, 1673 CK_Corei7AVX, 1674 CK_CoreAVXi, 1675 CK_CoreAVX2, 1676 //@} 1677 1678 /// \name K6 1679 /// K6 architecture processors. 1680 //@{ 1681 CK_K6, 1682 CK_K6_2, 1683 CK_K6_3, 1684 //@} 1685 1686 /// \name K7 1687 /// K7 architecture processors. 1688 //@{ 1689 CK_Athlon, 1690 CK_AthlonThunderbird, 1691 CK_Athlon4, 1692 CK_AthlonXP, 1693 CK_AthlonMP, 1694 //@} 1695 1696 /// \name K8 1697 /// K8 architecture processors. 1698 //@{ 1699 CK_Athlon64, 1700 CK_Athlon64SSE3, 1701 CK_AthlonFX, 1702 CK_K8, 1703 CK_K8SSE3, 1704 CK_Opteron, 1705 CK_OpteronSSE3, 1706 CK_AMDFAM10, 1707 //@} 1708 1709 /// \name Bobcat 1710 /// Bobcat architecture processors. 1711 //@{ 1712 CK_BTVER1, 1713 CK_BTVER2, 1714 //@} 1715 1716 /// \name Bulldozer 1717 /// Bulldozer architecture processors. 1718 //@{ 1719 CK_BDVER1, 1720 CK_BDVER2, 1721 //@} 1722 1723 /// This specification is deprecated and will be removed in the future. 1724 /// Users should prefer \see CK_K8. 1725 // FIXME: Warn on this when the CPU is set to it. 1726 CK_x86_64, 1727 //@} 1728 1729 /// \name Geode 1730 /// Geode processors. 1731 //@{ 1732 CK_Geode 1733 //@} 1734 } CPU; 1735 1736 public: 1737 X86TargetInfo(const llvm::Triple &Triple) 1738 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1739 HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false), 1740 HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false), 1741 HasPRFCHW(false), HasRDSEED(false), HasSSE4a(false), HasFMA4(false), 1742 HasFMA(false), HasXOP(false), HasF16C(false), CPU(CK_Generic) { 1743 BigEndian = false; 1744 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1745 } 1746 virtual unsigned getFloatEvalMethod() const { 1747 // X87 evaluates with 80 bits "long double" precision. 1748 return SSELevel == NoSSE ? 2 : 0; 1749 } 1750 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1751 unsigned &NumRecords) const { 1752 Records = BuiltinInfo; 1753 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1754 } 1755 virtual void getGCCRegNames(const char * const *&Names, 1756 unsigned &NumNames) const { 1757 Names = GCCRegNames; 1758 NumNames = llvm::array_lengthof(GCCRegNames); 1759 } 1760 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1761 unsigned &NumAliases) const { 1762 Aliases = 0; 1763 NumAliases = 0; 1764 } 1765 virtual void getGCCAddlRegNames(const AddlRegName *&Names, 1766 unsigned &NumNames) const { 1767 Names = AddlRegNames; 1768 NumNames = llvm::array_lengthof(AddlRegNames); 1769 } 1770 virtual bool validateAsmConstraint(const char *&Name, 1771 TargetInfo::ConstraintInfo &info) const; 1772 virtual std::string convertConstraint(const char *&Constraint) const; 1773 virtual const char *getClobbers() const { 1774 return "~{dirflag},~{fpsr},~{flags}"; 1775 } 1776 virtual void getTargetDefines(const LangOptions &Opts, 1777 MacroBuilder &Builder) const; 1778 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 1779 StringRef Name, 1780 bool Enabled) const; 1781 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 1782 virtual bool hasFeature(StringRef Feature) const; 1783 virtual void HandleTargetFeatures(std::vector<std::string> &Features); 1784 virtual const char* getABI() const { 1785 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1786 return "avx"; 1787 else if (getTriple().getArch() == llvm::Triple::x86 && 1788 MMX3DNowLevel == NoMMX3DNow) 1789 return "no-mmx"; 1790 return ""; 1791 } 1792 virtual bool setCPU(const std::string &Name) { 1793 CPU = llvm::StringSwitch<CPUKind>(Name) 1794 .Case("i386", CK_i386) 1795 .Case("i486", CK_i486) 1796 .Case("winchip-c6", CK_WinChipC6) 1797 .Case("winchip2", CK_WinChip2) 1798 .Case("c3", CK_C3) 1799 .Case("i586", CK_i586) 1800 .Case("pentium", CK_Pentium) 1801 .Case("pentium-mmx", CK_PentiumMMX) 1802 .Case("i686", CK_i686) 1803 .Case("pentiumpro", CK_PentiumPro) 1804 .Case("pentium2", CK_Pentium2) 1805 .Case("pentium3", CK_Pentium3) 1806 .Case("pentium3m", CK_Pentium3M) 1807 .Case("pentium-m", CK_PentiumM) 1808 .Case("c3-2", CK_C3_2) 1809 .Case("yonah", CK_Yonah) 1810 .Case("pentium4", CK_Pentium4) 1811 .Case("pentium4m", CK_Pentium4M) 1812 .Case("prescott", CK_Prescott) 1813 .Case("nocona", CK_Nocona) 1814 .Case("core2", CK_Core2) 1815 .Case("penryn", CK_Penryn) 1816 .Case("atom", CK_Atom) 1817 .Case("corei7", CK_Corei7) 1818 .Case("corei7-avx", CK_Corei7AVX) 1819 .Case("core-avx-i", CK_CoreAVXi) 1820 .Case("core-avx2", CK_CoreAVX2) 1821 .Case("k6", CK_K6) 1822 .Case("k6-2", CK_K6_2) 1823 .Case("k6-3", CK_K6_3) 1824 .Case("athlon", CK_Athlon) 1825 .Case("athlon-tbird", CK_AthlonThunderbird) 1826 .Case("athlon-4", CK_Athlon4) 1827 .Case("athlon-xp", CK_AthlonXP) 1828 .Case("athlon-mp", CK_AthlonMP) 1829 .Case("athlon64", CK_Athlon64) 1830 .Case("athlon64-sse3", CK_Athlon64SSE3) 1831 .Case("athlon-fx", CK_AthlonFX) 1832 .Case("k8", CK_K8) 1833 .Case("k8-sse3", CK_K8SSE3) 1834 .Case("opteron", CK_Opteron) 1835 .Case("opteron-sse3", CK_OpteronSSE3) 1836 .Case("amdfam10", CK_AMDFAM10) 1837 .Case("btver1", CK_BTVER1) 1838 .Case("btver2", CK_BTVER2) 1839 .Case("bdver1", CK_BDVER1) 1840 .Case("bdver2", CK_BDVER2) 1841 .Case("x86-64", CK_x86_64) 1842 .Case("geode", CK_Geode) 1843 .Default(CK_Generic); 1844 1845 // Perform any per-CPU checks necessary to determine if this CPU is 1846 // acceptable. 1847 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1848 // invalid without explaining *why*. 1849 switch (CPU) { 1850 case CK_Generic: 1851 // No processor selected! 1852 return false; 1853 1854 case CK_i386: 1855 case CK_i486: 1856 case CK_WinChipC6: 1857 case CK_WinChip2: 1858 case CK_C3: 1859 case CK_i586: 1860 case CK_Pentium: 1861 case CK_PentiumMMX: 1862 case CK_i686: 1863 case CK_PentiumPro: 1864 case CK_Pentium2: 1865 case CK_Pentium3: 1866 case CK_Pentium3M: 1867 case CK_PentiumM: 1868 case CK_Yonah: 1869 case CK_C3_2: 1870 case CK_Pentium4: 1871 case CK_Pentium4M: 1872 case CK_Prescott: 1873 case CK_K6: 1874 case CK_K6_2: 1875 case CK_K6_3: 1876 case CK_Athlon: 1877 case CK_AthlonThunderbird: 1878 case CK_Athlon4: 1879 case CK_AthlonXP: 1880 case CK_AthlonMP: 1881 case CK_Geode: 1882 // Only accept certain architectures when compiling in 32-bit mode. 1883 if (getTriple().getArch() != llvm::Triple::x86) 1884 return false; 1885 1886 // Fallthrough 1887 case CK_Nocona: 1888 case CK_Core2: 1889 case CK_Penryn: 1890 case CK_Atom: 1891 case CK_Corei7: 1892 case CK_Corei7AVX: 1893 case CK_CoreAVXi: 1894 case CK_CoreAVX2: 1895 case CK_Athlon64: 1896 case CK_Athlon64SSE3: 1897 case CK_AthlonFX: 1898 case CK_K8: 1899 case CK_K8SSE3: 1900 case CK_Opteron: 1901 case CK_OpteronSSE3: 1902 case CK_AMDFAM10: 1903 case CK_BTVER1: 1904 case CK_BTVER2: 1905 case CK_BDVER1: 1906 case CK_BDVER2: 1907 case CK_x86_64: 1908 return true; 1909 } 1910 llvm_unreachable("Unhandled CPU kind"); 1911 } 1912 1913 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 1914 // We accept all non-ARM calling conventions 1915 return (CC == CC_X86ThisCall || 1916 CC == CC_X86FastCall || 1917 CC == CC_X86StdCall || 1918 CC == CC_C || 1919 CC == CC_X86Pascal || 1920 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 1921 } 1922 1923 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 1924 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 1925 } 1926 }; 1927 1928 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1929 // FIXME: This should not be here. 1930 Features["3dnow"] = false; 1931 Features["3dnowa"] = false; 1932 Features["mmx"] = false; 1933 Features["sse"] = false; 1934 Features["sse2"] = false; 1935 Features["sse3"] = false; 1936 Features["ssse3"] = false; 1937 Features["sse41"] = false; 1938 Features["sse42"] = false; 1939 Features["sse4a"] = false; 1940 Features["aes"] = false; 1941 Features["pclmul"] = false; 1942 Features["avx"] = false; 1943 Features["avx2"] = false; 1944 Features["lzcnt"] = false; 1945 Features["rdrand"] = false; 1946 Features["bmi"] = false; 1947 Features["bmi2"] = false; 1948 Features["popcnt"] = false; 1949 Features["rtm"] = false; 1950 Features["prfchw"] = false; 1951 Features["rdseed"] = false; 1952 Features["fma4"] = false; 1953 Features["fma"] = false; 1954 Features["xop"] = false; 1955 Features["f16c"] = false; 1956 1957 // FIXME: This *really* should not be here. 1958 1959 // X86_64 always has SSE2. 1960 if (getTriple().getArch() == llvm::Triple::x86_64) 1961 setFeatureEnabled(Features, "sse2", true); 1962 1963 switch (CPU) { 1964 case CK_Generic: 1965 case CK_i386: 1966 case CK_i486: 1967 case CK_i586: 1968 case CK_Pentium: 1969 case CK_i686: 1970 case CK_PentiumPro: 1971 break; 1972 case CK_PentiumMMX: 1973 case CK_Pentium2: 1974 setFeatureEnabled(Features, "mmx", true); 1975 break; 1976 case CK_Pentium3: 1977 case CK_Pentium3M: 1978 setFeatureEnabled(Features, "sse", true); 1979 break; 1980 case CK_PentiumM: 1981 case CK_Pentium4: 1982 case CK_Pentium4M: 1983 case CK_x86_64: 1984 setFeatureEnabled(Features, "sse2", true); 1985 break; 1986 case CK_Yonah: 1987 case CK_Prescott: 1988 case CK_Nocona: 1989 setFeatureEnabled(Features, "sse3", true); 1990 break; 1991 case CK_Core2: 1992 setFeatureEnabled(Features, "ssse3", true); 1993 break; 1994 case CK_Penryn: 1995 setFeatureEnabled(Features, "sse4.1", true); 1996 break; 1997 case CK_Atom: 1998 setFeatureEnabled(Features, "ssse3", true); 1999 break; 2000 case CK_Corei7: 2001 setFeatureEnabled(Features, "sse4", true); 2002 break; 2003 case CK_Corei7AVX: 2004 setFeatureEnabled(Features, "avx", true); 2005 setFeatureEnabled(Features, "aes", true); 2006 setFeatureEnabled(Features, "pclmul", true); 2007 break; 2008 case CK_CoreAVXi: 2009 setFeatureEnabled(Features, "avx", true); 2010 setFeatureEnabled(Features, "aes", true); 2011 setFeatureEnabled(Features, "pclmul", true); 2012 setFeatureEnabled(Features, "rdrnd", true); 2013 setFeatureEnabled(Features, "f16c", true); 2014 break; 2015 case CK_CoreAVX2: 2016 setFeatureEnabled(Features, "avx2", true); 2017 setFeatureEnabled(Features, "aes", true); 2018 setFeatureEnabled(Features, "pclmul", true); 2019 setFeatureEnabled(Features, "lzcnt", true); 2020 setFeatureEnabled(Features, "rdrnd", true); 2021 setFeatureEnabled(Features, "f16c", true); 2022 setFeatureEnabled(Features, "bmi", true); 2023 setFeatureEnabled(Features, "bmi2", true); 2024 setFeatureEnabled(Features, "rtm", true); 2025 setFeatureEnabled(Features, "fma", true); 2026 break; 2027 case CK_K6: 2028 case CK_WinChipC6: 2029 setFeatureEnabled(Features, "mmx", true); 2030 break; 2031 case CK_K6_2: 2032 case CK_K6_3: 2033 case CK_WinChip2: 2034 case CK_C3: 2035 setFeatureEnabled(Features, "3dnow", true); 2036 break; 2037 case CK_Athlon: 2038 case CK_AthlonThunderbird: 2039 case CK_Geode: 2040 setFeatureEnabled(Features, "3dnowa", true); 2041 break; 2042 case CK_Athlon4: 2043 case CK_AthlonXP: 2044 case CK_AthlonMP: 2045 setFeatureEnabled(Features, "sse", true); 2046 setFeatureEnabled(Features, "3dnowa", true); 2047 break; 2048 case CK_K8: 2049 case CK_Opteron: 2050 case CK_Athlon64: 2051 case CK_AthlonFX: 2052 setFeatureEnabled(Features, "sse2", true); 2053 setFeatureEnabled(Features, "3dnowa", true); 2054 break; 2055 case CK_K8SSE3: 2056 case CK_OpteronSSE3: 2057 case CK_Athlon64SSE3: 2058 setFeatureEnabled(Features, "sse3", true); 2059 setFeatureEnabled(Features, "3dnowa", true); 2060 break; 2061 case CK_AMDFAM10: 2062 setFeatureEnabled(Features, "sse3", true); 2063 setFeatureEnabled(Features, "sse4a", true); 2064 setFeatureEnabled(Features, "3dnowa", true); 2065 setFeatureEnabled(Features, "lzcnt", true); 2066 setFeatureEnabled(Features, "popcnt", true); 2067 break; 2068 case CK_BTVER1: 2069 setFeatureEnabled(Features, "ssse3", true); 2070 setFeatureEnabled(Features, "sse4a", true); 2071 setFeatureEnabled(Features, "lzcnt", true); 2072 setFeatureEnabled(Features, "popcnt", true); 2073 break; 2074 case CK_BTVER2: 2075 setFeatureEnabled(Features, "avx", true); 2076 setFeatureEnabled(Features, "sse4a", true); 2077 setFeatureEnabled(Features, "lzcnt", true); 2078 setFeatureEnabled(Features, "aes", true); 2079 setFeatureEnabled(Features, "pclmul", true); 2080 setFeatureEnabled(Features, "bmi", true); 2081 setFeatureEnabled(Features, "f16c", true); 2082 break; 2083 case CK_BDVER1: 2084 setFeatureEnabled(Features, "xop", true); 2085 setFeatureEnabled(Features, "lzcnt", true); 2086 setFeatureEnabled(Features, "aes", true); 2087 setFeatureEnabled(Features, "pclmul", true); 2088 break; 2089 case CK_BDVER2: 2090 setFeatureEnabled(Features, "xop", true); 2091 setFeatureEnabled(Features, "lzcnt", true); 2092 setFeatureEnabled(Features, "aes", true); 2093 setFeatureEnabled(Features, "pclmul", true); 2094 setFeatureEnabled(Features, "bmi", true); 2095 setFeatureEnabled(Features, "fma", true); 2096 setFeatureEnabled(Features, "f16c", true); 2097 break; 2098 case CK_C3_2: 2099 setFeatureEnabled(Features, "sse", true); 2100 break; 2101 } 2102 } 2103 2104 bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 2105 StringRef Name, 2106 bool Enabled) const { 2107 // FIXME: This *really* should not be here. We need some way of translating 2108 // options into llvm subtarget features. 2109 if (!Features.count(Name) && 2110 (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" && 2111 Name != "rdrnd")) 2112 return false; 2113 2114 // FIXME: this should probably use a switch with fall through. 2115 2116 if (Enabled) { 2117 if (Name == "mmx") 2118 Features["mmx"] = true; 2119 else if (Name == "sse") 2120 Features["mmx"] = Features["sse"] = true; 2121 else if (Name == "sse2") 2122 Features["mmx"] = Features["sse"] = Features["sse2"] = true; 2123 else if (Name == "sse3") 2124 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2125 true; 2126 else if (Name == "ssse3") 2127 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2128 Features["ssse3"] = true; 2129 else if (Name == "sse4" || Name == "sse4.2") 2130 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2131 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2132 Features["popcnt"] = true; 2133 else if (Name == "sse4.1") 2134 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2135 Features["ssse3"] = Features["sse41"] = true; 2136 else if (Name == "3dnow") 2137 Features["mmx"] = Features["3dnow"] = true; 2138 else if (Name == "3dnowa") 2139 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true; 2140 else if (Name == "aes") 2141 Features["sse"] = Features["sse2"] = Features["aes"] = true; 2142 else if (Name == "pclmul") 2143 Features["sse"] = Features["sse2"] = Features["pclmul"] = true; 2144 else if (Name == "avx") 2145 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2146 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2147 Features["popcnt"] = Features["avx"] = true; 2148 else if (Name == "avx2") 2149 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2150 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2151 Features["popcnt"] = Features["avx"] = Features["avx2"] = true; 2152 else if (Name == "fma") 2153 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2154 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2155 Features["popcnt"] = Features["avx"] = Features["fma"] = true; 2156 else if (Name == "fma4") 2157 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2158 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2159 Features["popcnt"] = Features["avx"] = Features["sse4a"] = 2160 Features["fma4"] = true; 2161 else if (Name == "xop") 2162 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2163 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2164 Features["popcnt"] = Features["avx"] = Features["sse4a"] = 2165 Features["fma4"] = Features["xop"] = true; 2166 else if (Name == "sse4a") 2167 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2168 Features["sse4a"] = true; 2169 else if (Name == "lzcnt") 2170 Features["lzcnt"] = true; 2171 else if (Name == "rdrnd") 2172 Features["rdrand"] = true; 2173 else if (Name == "bmi") 2174 Features["bmi"] = true; 2175 else if (Name == "bmi2") 2176 Features["bmi2"] = true; 2177 else if (Name == "popcnt") 2178 Features["popcnt"] = true; 2179 else if (Name == "f16c") 2180 Features["f16c"] = true; 2181 else if (Name == "rtm") 2182 Features["rtm"] = true; 2183 else if (Name == "prfchw") 2184 Features["prfchw"] = true; 2185 else if (Name == "rdseed") 2186 Features["rdseed"] = true; 2187 } else { 2188 if (Name == "mmx") 2189 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false; 2190 else if (Name == "sse") 2191 Features["sse"] = Features["sse2"] = Features["sse3"] = 2192 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2193 Features["sse4a"] = Features["avx"] = Features["avx2"] = 2194 Features["fma"] = Features["fma4"] = Features["aes"] = 2195 Features["pclmul"] = Features["xop"] = false; 2196 else if (Name == "sse2") 2197 Features["sse2"] = Features["sse3"] = Features["ssse3"] = 2198 Features["sse41"] = Features["sse42"] = Features["sse4a"] = 2199 Features["avx"] = Features["avx2"] = Features["fma"] = 2200 Features["fma4"] = Features["aes"] = Features["pclmul"] = 2201 Features["xop"] = false; 2202 else if (Name == "sse3") 2203 Features["sse3"] = Features["ssse3"] = Features["sse41"] = 2204 Features["sse42"] = Features["sse4a"] = Features["avx"] = 2205 Features["avx2"] = Features["fma"] = Features["fma4"] = 2206 Features["xop"] = false; 2207 else if (Name == "ssse3") 2208 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2209 Features["avx"] = Features["avx2"] = Features["fma"] = false; 2210 else if (Name == "sse4" || Name == "sse4.1") 2211 Features["sse41"] = Features["sse42"] = Features["avx"] = 2212 Features["avx2"] = Features["fma"] = false; 2213 else if (Name == "sse4.2") 2214 Features["sse42"] = Features["avx"] = Features["avx2"] = 2215 Features["fma"] = false; 2216 else if (Name == "3dnow") 2217 Features["3dnow"] = Features["3dnowa"] = false; 2218 else if (Name == "3dnowa") 2219 Features["3dnowa"] = false; 2220 else if (Name == "aes") 2221 Features["aes"] = false; 2222 else if (Name == "pclmul") 2223 Features["pclmul"] = false; 2224 else if (Name == "avx") 2225 Features["avx"] = Features["avx2"] = Features["fma"] = 2226 Features["fma4"] = Features["xop"] = false; 2227 else if (Name == "avx2") 2228 Features["avx2"] = false; 2229 else if (Name == "fma") 2230 Features["fma"] = false; 2231 else if (Name == "sse4a") 2232 Features["sse4a"] = Features["fma4"] = Features["xop"] = false; 2233 else if (Name == "lzcnt") 2234 Features["lzcnt"] = false; 2235 else if (Name == "rdrnd") 2236 Features["rdrand"] = false; 2237 else if (Name == "bmi") 2238 Features["bmi"] = false; 2239 else if (Name == "bmi2") 2240 Features["bmi2"] = false; 2241 else if (Name == "popcnt") 2242 Features["popcnt"] = false; 2243 else if (Name == "fma4") 2244 Features["fma4"] = Features["xop"] = false; 2245 else if (Name == "xop") 2246 Features["xop"] = false; 2247 else if (Name == "f16c") 2248 Features["f16c"] = false; 2249 else if (Name == "rtm") 2250 Features["rtm"] = false; 2251 else if (Name == "prfchw") 2252 Features["prfchw"] = false; 2253 else if (Name == "rdseed") 2254 Features["rdseed"] = false; 2255 } 2256 2257 return true; 2258 } 2259 2260 /// HandleTargetOptions - Perform initialization based on the user 2261 /// configured set of features. 2262 void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) { 2263 // Remember the maximum enabled sselevel. 2264 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2265 // Ignore disabled features. 2266 if (Features[i][0] == '-') 2267 continue; 2268 2269 StringRef Feature = StringRef(Features[i]).substr(1); 2270 2271 if (Feature == "aes") { 2272 HasAES = true; 2273 continue; 2274 } 2275 2276 if (Feature == "pclmul") { 2277 HasPCLMUL = true; 2278 continue; 2279 } 2280 2281 if (Feature == "lzcnt") { 2282 HasLZCNT = true; 2283 continue; 2284 } 2285 2286 if (Feature == "rdrand") { 2287 HasRDRND = true; 2288 continue; 2289 } 2290 2291 if (Feature == "bmi") { 2292 HasBMI = true; 2293 continue; 2294 } 2295 2296 if (Feature == "bmi2") { 2297 HasBMI2 = true; 2298 continue; 2299 } 2300 2301 if (Feature == "popcnt") { 2302 HasPOPCNT = true; 2303 continue; 2304 } 2305 2306 if (Feature == "rtm") { 2307 HasRTM = true; 2308 continue; 2309 } 2310 2311 if (Feature == "prfchw") { 2312 HasPRFCHW = true; 2313 continue; 2314 } 2315 2316 if (Feature == "rdseed") { 2317 HasRDSEED = true; 2318 continue; 2319 } 2320 2321 if (Feature == "sse4a") { 2322 HasSSE4a = true; 2323 continue; 2324 } 2325 2326 if (Feature == "fma4") { 2327 HasFMA4 = true; 2328 continue; 2329 } 2330 2331 if (Feature == "fma") { 2332 HasFMA = true; 2333 continue; 2334 } 2335 2336 if (Feature == "xop") { 2337 HasXOP = true; 2338 continue; 2339 } 2340 2341 if (Feature == "f16c") { 2342 HasF16C = true; 2343 continue; 2344 } 2345 2346 assert(Features[i][0] == '+' && "Invalid target feature!"); 2347 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2348 .Case("avx2", AVX2) 2349 .Case("avx", AVX) 2350 .Case("sse42", SSE42) 2351 .Case("sse41", SSE41) 2352 .Case("ssse3", SSSE3) 2353 .Case("sse3", SSE3) 2354 .Case("sse2", SSE2) 2355 .Case("sse", SSE1) 2356 .Default(NoSSE); 2357 SSELevel = std::max(SSELevel, Level); 2358 2359 MMX3DNowEnum ThreeDNowLevel = 2360 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2361 .Case("3dnowa", AMD3DNowAthlon) 2362 .Case("3dnow", AMD3DNow) 2363 .Case("mmx", MMX) 2364 .Default(NoMMX3DNow); 2365 2366 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2367 } 2368 2369 // Don't tell the backend if we're turning off mmx; it will end up disabling 2370 // SSE, which we don't want. 2371 std::vector<std::string>::iterator it; 2372 it = std::find(Features.begin(), Features.end(), "-mmx"); 2373 if (it != Features.end()) 2374 Features.erase(it); 2375 } 2376 2377 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2378 /// definitions for this particular subtarget. 2379 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2380 MacroBuilder &Builder) const { 2381 // Target identification. 2382 if (getTriple().getArch() == llvm::Triple::x86_64) { 2383 Builder.defineMacro("__amd64__"); 2384 Builder.defineMacro("__amd64"); 2385 Builder.defineMacro("__x86_64"); 2386 Builder.defineMacro("__x86_64__"); 2387 } else { 2388 DefineStd(Builder, "i386", Opts); 2389 } 2390 2391 // Subtarget options. 2392 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2393 // truly should be based on -mtune options. 2394 switch (CPU) { 2395 case CK_Generic: 2396 break; 2397 case CK_i386: 2398 // The rest are coming from the i386 define above. 2399 Builder.defineMacro("__tune_i386__"); 2400 break; 2401 case CK_i486: 2402 case CK_WinChipC6: 2403 case CK_WinChip2: 2404 case CK_C3: 2405 defineCPUMacros(Builder, "i486"); 2406 break; 2407 case CK_PentiumMMX: 2408 Builder.defineMacro("__pentium_mmx__"); 2409 Builder.defineMacro("__tune_pentium_mmx__"); 2410 // Fallthrough 2411 case CK_i586: 2412 case CK_Pentium: 2413 defineCPUMacros(Builder, "i586"); 2414 defineCPUMacros(Builder, "pentium"); 2415 break; 2416 case CK_Pentium3: 2417 case CK_Pentium3M: 2418 case CK_PentiumM: 2419 Builder.defineMacro("__tune_pentium3__"); 2420 // Fallthrough 2421 case CK_Pentium2: 2422 case CK_C3_2: 2423 Builder.defineMacro("__tune_pentium2__"); 2424 // Fallthrough 2425 case CK_PentiumPro: 2426 Builder.defineMacro("__tune_i686__"); 2427 Builder.defineMacro("__tune_pentiumpro__"); 2428 // Fallthrough 2429 case CK_i686: 2430 Builder.defineMacro("__i686"); 2431 Builder.defineMacro("__i686__"); 2432 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2433 Builder.defineMacro("__pentiumpro"); 2434 Builder.defineMacro("__pentiumpro__"); 2435 break; 2436 case CK_Pentium4: 2437 case CK_Pentium4M: 2438 defineCPUMacros(Builder, "pentium4"); 2439 break; 2440 case CK_Yonah: 2441 case CK_Prescott: 2442 case CK_Nocona: 2443 defineCPUMacros(Builder, "nocona"); 2444 break; 2445 case CK_Core2: 2446 case CK_Penryn: 2447 defineCPUMacros(Builder, "core2"); 2448 break; 2449 case CK_Atom: 2450 defineCPUMacros(Builder, "atom"); 2451 break; 2452 case CK_Corei7: 2453 case CK_Corei7AVX: 2454 case CK_CoreAVXi: 2455 case CK_CoreAVX2: 2456 defineCPUMacros(Builder, "corei7"); 2457 break; 2458 case CK_K6_2: 2459 Builder.defineMacro("__k6_2__"); 2460 Builder.defineMacro("__tune_k6_2__"); 2461 // Fallthrough 2462 case CK_K6_3: 2463 if (CPU != CK_K6_2) { // In case of fallthrough 2464 // FIXME: GCC may be enabling these in cases where some other k6 2465 // architecture is specified but -m3dnow is explicitly provided. The 2466 // exact semantics need to be determined and emulated here. 2467 Builder.defineMacro("__k6_3__"); 2468 Builder.defineMacro("__tune_k6_3__"); 2469 } 2470 // Fallthrough 2471 case CK_K6: 2472 defineCPUMacros(Builder, "k6"); 2473 break; 2474 case CK_Athlon: 2475 case CK_AthlonThunderbird: 2476 case CK_Athlon4: 2477 case CK_AthlonXP: 2478 case CK_AthlonMP: 2479 defineCPUMacros(Builder, "athlon"); 2480 if (SSELevel != NoSSE) { 2481 Builder.defineMacro("__athlon_sse__"); 2482 Builder.defineMacro("__tune_athlon_sse__"); 2483 } 2484 break; 2485 case CK_K8: 2486 case CK_K8SSE3: 2487 case CK_x86_64: 2488 case CK_Opteron: 2489 case CK_OpteronSSE3: 2490 case CK_Athlon64: 2491 case CK_Athlon64SSE3: 2492 case CK_AthlonFX: 2493 defineCPUMacros(Builder, "k8"); 2494 break; 2495 case CK_AMDFAM10: 2496 defineCPUMacros(Builder, "amdfam10"); 2497 break; 2498 case CK_BTVER1: 2499 defineCPUMacros(Builder, "btver1"); 2500 break; 2501 case CK_BTVER2: 2502 defineCPUMacros(Builder, "btver2"); 2503 break; 2504 case CK_BDVER1: 2505 defineCPUMacros(Builder, "bdver1"); 2506 break; 2507 case CK_BDVER2: 2508 defineCPUMacros(Builder, "bdver2"); 2509 break; 2510 case CK_Geode: 2511 defineCPUMacros(Builder, "geode"); 2512 break; 2513 } 2514 2515 // Target properties. 2516 Builder.defineMacro("__LITTLE_ENDIAN__"); 2517 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2518 2519 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2520 // functions in glibc header files that use FP Stack inline asm which the 2521 // backend can't deal with (PR879). 2522 Builder.defineMacro("__NO_MATH_INLINES"); 2523 2524 if (HasAES) 2525 Builder.defineMacro("__AES__"); 2526 2527 if (HasPCLMUL) 2528 Builder.defineMacro("__PCLMUL__"); 2529 2530 if (HasLZCNT) 2531 Builder.defineMacro("__LZCNT__"); 2532 2533 if (HasRDRND) 2534 Builder.defineMacro("__RDRND__"); 2535 2536 if (HasBMI) 2537 Builder.defineMacro("__BMI__"); 2538 2539 if (HasBMI2) 2540 Builder.defineMacro("__BMI2__"); 2541 2542 if (HasPOPCNT) 2543 Builder.defineMacro("__POPCNT__"); 2544 2545 if (HasRTM) 2546 Builder.defineMacro("__RTM__"); 2547 2548 if (HasPRFCHW) 2549 Builder.defineMacro("__PRFCHW__"); 2550 2551 if (HasRDSEED) 2552 Builder.defineMacro("__RDSEED__"); 2553 2554 if (HasSSE4a) 2555 Builder.defineMacro("__SSE4A__"); 2556 2557 if (HasFMA4) 2558 Builder.defineMacro("__FMA4__"); 2559 2560 if (HasFMA) 2561 Builder.defineMacro("__FMA__"); 2562 2563 if (HasXOP) 2564 Builder.defineMacro("__XOP__"); 2565 2566 if (HasF16C) 2567 Builder.defineMacro("__F16C__"); 2568 2569 // Each case falls through to the previous one here. 2570 switch (SSELevel) { 2571 case AVX2: 2572 Builder.defineMacro("__AVX2__"); 2573 case AVX: 2574 Builder.defineMacro("__AVX__"); 2575 case SSE42: 2576 Builder.defineMacro("__SSE4_2__"); 2577 case SSE41: 2578 Builder.defineMacro("__SSE4_1__"); 2579 case SSSE3: 2580 Builder.defineMacro("__SSSE3__"); 2581 case SSE3: 2582 Builder.defineMacro("__SSE3__"); 2583 case SSE2: 2584 Builder.defineMacro("__SSE2__"); 2585 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2586 case SSE1: 2587 Builder.defineMacro("__SSE__"); 2588 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2589 case NoSSE: 2590 break; 2591 } 2592 2593 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2594 switch (SSELevel) { 2595 case AVX2: 2596 case AVX: 2597 case SSE42: 2598 case SSE41: 2599 case SSSE3: 2600 case SSE3: 2601 case SSE2: 2602 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2603 break; 2604 case SSE1: 2605 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2606 break; 2607 default: 2608 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2609 } 2610 } 2611 2612 // Each case falls through to the previous one here. 2613 switch (MMX3DNowLevel) { 2614 case AMD3DNowAthlon: 2615 Builder.defineMacro("__3dNOW_A__"); 2616 case AMD3DNow: 2617 Builder.defineMacro("__3dNOW__"); 2618 case MMX: 2619 Builder.defineMacro("__MMX__"); 2620 case NoMMX3DNow: 2621 break; 2622 } 2623 2624 if (CPU >= CK_i486) { 2625 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2626 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2627 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2628 } 2629 if (CPU >= CK_i586) 2630 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2631 } 2632 2633 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2634 return llvm::StringSwitch<bool>(Feature) 2635 .Case("aes", HasAES) 2636 .Case("avx", SSELevel >= AVX) 2637 .Case("avx2", SSELevel >= AVX2) 2638 .Case("bmi", HasBMI) 2639 .Case("bmi2", HasBMI2) 2640 .Case("fma", HasFMA) 2641 .Case("fma4", HasFMA4) 2642 .Case("lzcnt", HasLZCNT) 2643 .Case("rdrnd", HasRDRND) 2644 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2645 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2646 .Case("mmx", MMX3DNowLevel >= MMX) 2647 .Case("pclmul", HasPCLMUL) 2648 .Case("popcnt", HasPOPCNT) 2649 .Case("rtm", HasRTM) 2650 .Case("prfchw", HasPRFCHW) 2651 .Case("rdseed", HasRDSEED) 2652 .Case("sse", SSELevel >= SSE1) 2653 .Case("sse2", SSELevel >= SSE2) 2654 .Case("sse3", SSELevel >= SSE3) 2655 .Case("ssse3", SSELevel >= SSSE3) 2656 .Case("sse41", SSELevel >= SSE41) 2657 .Case("sse42", SSELevel >= SSE42) 2658 .Case("sse4a", HasSSE4a) 2659 .Case("x86", true) 2660 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2661 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2662 .Case("xop", HasXOP) 2663 .Case("f16c", HasF16C) 2664 .Default(false); 2665 } 2666 2667 bool 2668 X86TargetInfo::validateAsmConstraint(const char *&Name, 2669 TargetInfo::ConstraintInfo &Info) const { 2670 switch (*Name) { 2671 default: return false; 2672 case 'Y': // first letter of a pair: 2673 switch (*(Name+1)) { 2674 default: return false; 2675 case '0': // First SSE register. 2676 case 't': // Any SSE register, when SSE2 is enabled. 2677 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2678 case 'm': // any MMX register, when inter-unit moves enabled. 2679 break; // falls through to setAllowsRegister. 2680 } 2681 case 'a': // eax. 2682 case 'b': // ebx. 2683 case 'c': // ecx. 2684 case 'd': // edx. 2685 case 'S': // esi. 2686 case 'D': // edi. 2687 case 'A': // edx:eax. 2688 case 'f': // any x87 floating point stack register. 2689 case 't': // top of floating point stack. 2690 case 'u': // second from top of floating point stack. 2691 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2692 case 'y': // Any MMX register. 2693 case 'x': // Any SSE register. 2694 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2695 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2696 case 'l': // "Index" registers: any general register that can be used as an 2697 // index in a base+index memory access. 2698 Info.setAllowsRegister(); 2699 return true; 2700 case 'C': // SSE floating point constant. 2701 case 'G': // x87 floating point constant. 2702 case 'e': // 32-bit signed integer constant for use with zero-extending 2703 // x86_64 instructions. 2704 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2705 // x86_64 instructions. 2706 return true; 2707 } 2708 } 2709 2710 2711 std::string 2712 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2713 switch (*Constraint) { 2714 case 'a': return std::string("{ax}"); 2715 case 'b': return std::string("{bx}"); 2716 case 'c': return std::string("{cx}"); 2717 case 'd': return std::string("{dx}"); 2718 case 'S': return std::string("{si}"); 2719 case 'D': return std::string("{di}"); 2720 case 'p': // address 2721 return std::string("im"); 2722 case 't': // top of floating point stack. 2723 return std::string("{st}"); 2724 case 'u': // second from top of floating point stack. 2725 return std::string("{st(1)}"); // second from top of floating point stack. 2726 default: 2727 return std::string(1, *Constraint); 2728 } 2729 } 2730 } // end anonymous namespace 2731 2732 namespace { 2733 // X86-32 generic target 2734 class X86_32TargetInfo : public X86TargetInfo { 2735 public: 2736 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 2737 DoubleAlign = LongLongAlign = 32; 2738 LongDoubleWidth = 96; 2739 LongDoubleAlign = 32; 2740 SuitableAlign = 128; 2741 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2742 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2743 "a0:0:64-f80:32:32-n8:16:32-S128"; 2744 SizeType = UnsignedInt; 2745 PtrDiffType = SignedInt; 2746 IntPtrType = SignedInt; 2747 RegParmMax = 3; 2748 2749 // Use fpret for all types. 2750 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2751 (1 << TargetInfo::Double) | 2752 (1 << TargetInfo::LongDouble)); 2753 2754 // x86-32 has atomics up to 8 bytes 2755 // FIXME: Check that we actually have cmpxchg8b before setting 2756 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2757 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2758 } 2759 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2760 return TargetInfo::CharPtrBuiltinVaList; 2761 } 2762 2763 int getEHDataRegisterNumber(unsigned RegNo) const { 2764 if (RegNo == 0) return 0; 2765 if (RegNo == 1) return 2; 2766 return -1; 2767 } 2768 virtual bool validateInputSize(StringRef Constraint, 2769 unsigned Size) const { 2770 switch (Constraint[0]) { 2771 default: break; 2772 case 'a': 2773 case 'b': 2774 case 'c': 2775 case 'd': 2776 return Size <= 32; 2777 } 2778 2779 return true; 2780 } 2781 }; 2782 } // end anonymous namespace 2783 2784 namespace { 2785 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2786 public: 2787 NetBSDI386TargetInfo(const llvm::Triple &Triple) 2788 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 2789 2790 virtual unsigned getFloatEvalMethod() const { 2791 // NetBSD defaults to "double" rounding 2792 return 1; 2793 } 2794 }; 2795 } // end anonymous namespace 2796 2797 namespace { 2798 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 2799 public: 2800 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 2801 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 2802 SizeType = UnsignedLong; 2803 IntPtrType = SignedLong; 2804 PtrDiffType = SignedLong; 2805 } 2806 }; 2807 } // end anonymous namespace 2808 2809 namespace { 2810 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 2811 public: 2812 BitrigI386TargetInfo(const llvm::Triple &Triple) 2813 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 2814 SizeType = UnsignedLong; 2815 IntPtrType = SignedLong; 2816 PtrDiffType = SignedLong; 2817 } 2818 }; 2819 } // end anonymous namespace 2820 2821 namespace { 2822 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 2823 public: 2824 DarwinI386TargetInfo(const llvm::Triple &Triple) 2825 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 2826 LongDoubleWidth = 128; 2827 LongDoubleAlign = 128; 2828 SuitableAlign = 128; 2829 MaxVectorAlign = 256; 2830 SizeType = UnsignedLong; 2831 IntPtrType = SignedLong; 2832 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2833 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2834 "a0:0:64-f80:128:128-n8:16:32-S128"; 2835 HasAlignMac68kSupport = true; 2836 } 2837 2838 }; 2839 } // end anonymous namespace 2840 2841 namespace { 2842 // x86-32 Windows target 2843 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 2844 public: 2845 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 2846 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 2847 TLSSupported = false; 2848 WCharType = UnsignedShort; 2849 DoubleAlign = LongLongAlign = 64; 2850 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2851 "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-" 2852 "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"; 2853 } 2854 virtual void getTargetDefines(const LangOptions &Opts, 2855 MacroBuilder &Builder) const { 2856 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 2857 } 2858 }; 2859 } // end anonymous namespace 2860 2861 namespace { 2862 2863 // x86-32 Windows Visual Studio target 2864 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 2865 public: 2866 VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple) 2867 : WindowsX86_32TargetInfo(Triple) { 2868 LongDoubleWidth = LongDoubleAlign = 64; 2869 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 2870 } 2871 virtual void getTargetDefines(const LangOptions &Opts, 2872 MacroBuilder &Builder) const { 2873 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 2874 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 2875 // The value of the following reflects processor type. 2876 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 2877 // We lost the original triple, so we use the default. 2878 Builder.defineMacro("_M_IX86", "600"); 2879 } 2880 }; 2881 } // end anonymous namespace 2882 2883 namespace { 2884 // x86-32 MinGW target 2885 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 2886 public: 2887 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 2888 : WindowsX86_32TargetInfo(Triple) {} 2889 virtual void getTargetDefines(const LangOptions &Opts, 2890 MacroBuilder &Builder) const { 2891 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 2892 DefineStd(Builder, "WIN32", Opts); 2893 DefineStd(Builder, "WINNT", Opts); 2894 Builder.defineMacro("_X86_"); 2895 Builder.defineMacro("__MSVCRT__"); 2896 Builder.defineMacro("__MINGW32__"); 2897 2898 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 2899 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 2900 if (Opts.MicrosoftExt) 2901 // Provide "as-is" __declspec. 2902 Builder.defineMacro("__declspec", "__declspec"); 2903 else 2904 // Provide alias of __attribute__ like mingw32-gcc. 2905 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 2906 } 2907 }; 2908 } // end anonymous namespace 2909 2910 namespace { 2911 // x86-32 Cygwin target 2912 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 2913 public: 2914 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 2915 : X86_32TargetInfo(Triple) { 2916 TLSSupported = false; 2917 WCharType = UnsignedShort; 2918 DoubleAlign = LongLongAlign = 64; 2919 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2920 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 2921 "a0:0:64-f80:32:32-n8:16:32-S32"; 2922 } 2923 virtual void getTargetDefines(const LangOptions &Opts, 2924 MacroBuilder &Builder) const { 2925 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2926 Builder.defineMacro("_X86_"); 2927 Builder.defineMacro("__CYGWIN__"); 2928 Builder.defineMacro("__CYGWIN32__"); 2929 DefineStd(Builder, "unix", Opts); 2930 if (Opts.CPlusPlus) 2931 Builder.defineMacro("_GNU_SOURCE"); 2932 } 2933 }; 2934 } // end anonymous namespace 2935 2936 namespace { 2937 // x86-32 Haiku target 2938 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 2939 public: 2940 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 2941 SizeType = UnsignedLong; 2942 IntPtrType = SignedLong; 2943 PtrDiffType = SignedLong; 2944 ProcessIDType = SignedLong; 2945 this->UserLabelPrefix = ""; 2946 this->TLSSupported = false; 2947 } 2948 virtual void getTargetDefines(const LangOptions &Opts, 2949 MacroBuilder &Builder) const { 2950 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2951 Builder.defineMacro("__INTEL__"); 2952 Builder.defineMacro("__HAIKU__"); 2953 } 2954 }; 2955 } // end anonymous namespace 2956 2957 // RTEMS Target 2958 template<typename Target> 2959 class RTEMSTargetInfo : public OSTargetInfo<Target> { 2960 protected: 2961 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 2962 MacroBuilder &Builder) const { 2963 // RTEMS defines; list based off of gcc output 2964 2965 Builder.defineMacro("__rtems__"); 2966 Builder.defineMacro("__ELF__"); 2967 } 2968 2969 public: 2970 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 2971 this->UserLabelPrefix = ""; 2972 2973 switch (Triple.getArch()) { 2974 default: 2975 case llvm::Triple::x86: 2976 // this->MCountName = ".mcount"; 2977 break; 2978 case llvm::Triple::mips: 2979 case llvm::Triple::mipsel: 2980 case llvm::Triple::ppc: 2981 case llvm::Triple::ppc64: 2982 case llvm::Triple::ppc64le: 2983 // this->MCountName = "_mcount"; 2984 break; 2985 case llvm::Triple::arm: 2986 // this->MCountName = "__mcount"; 2987 break; 2988 } 2989 } 2990 }; 2991 2992 namespace { 2993 // x86-32 RTEMS target 2994 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 2995 public: 2996 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 2997 SizeType = UnsignedLong; 2998 IntPtrType = SignedLong; 2999 PtrDiffType = SignedLong; 3000 this->UserLabelPrefix = ""; 3001 } 3002 virtual void getTargetDefines(const LangOptions &Opts, 3003 MacroBuilder &Builder) const { 3004 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3005 Builder.defineMacro("__INTEL__"); 3006 Builder.defineMacro("__rtems__"); 3007 } 3008 }; 3009 } // end anonymous namespace 3010 3011 namespace { 3012 // x86-64 generic target 3013 class X86_64TargetInfo : public X86TargetInfo { 3014 public: 3015 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3016 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 3017 LongDoubleWidth = 128; 3018 LongDoubleAlign = 128; 3019 LargeArrayMinWidth = 128; 3020 LargeArrayAlign = 128; 3021 SuitableAlign = 128; 3022 IntMaxType = SignedLong; 3023 UIntMaxType = UnsignedLong; 3024 Int64Type = SignedLong; 3025 RegParmMax = 6; 3026 3027 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3028 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 3029 "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"; 3030 3031 // Use fpret only for long double. 3032 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3033 3034 // Use fp2ret for _Complex long double. 3035 ComplexLongDoubleUsesFP2Ret = true; 3036 3037 // x86-64 has atomics up to 16 bytes. 3038 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 3039 // on CPUs with cmpxchg16b 3040 MaxAtomicPromoteWidth = 128; 3041 MaxAtomicInlineWidth = 64; 3042 } 3043 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3044 return TargetInfo::X86_64ABIBuiltinVaList; 3045 } 3046 3047 int getEHDataRegisterNumber(unsigned RegNo) const { 3048 if (RegNo == 0) return 0; 3049 if (RegNo == 1) return 1; 3050 return -1; 3051 } 3052 3053 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3054 return (CC == CC_Default || 3055 CC == CC_C || 3056 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 3057 } 3058 3059 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 3060 return CC_C; 3061 } 3062 3063 }; 3064 } // end anonymous namespace 3065 3066 namespace { 3067 // x86-64 Windows target 3068 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3069 public: 3070 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3071 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3072 TLSSupported = false; 3073 WCharType = UnsignedShort; 3074 LongWidth = LongAlign = 32; 3075 DoubleAlign = LongLongAlign = 64; 3076 IntMaxType = SignedLongLong; 3077 UIntMaxType = UnsignedLongLong; 3078 Int64Type = SignedLongLong; 3079 SizeType = UnsignedLongLong; 3080 PtrDiffType = SignedLongLong; 3081 IntPtrType = SignedLongLong; 3082 this->UserLabelPrefix = ""; 3083 } 3084 virtual void getTargetDefines(const LangOptions &Opts, 3085 MacroBuilder &Builder) const { 3086 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3087 Builder.defineMacro("_WIN64"); 3088 } 3089 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3090 return TargetInfo::CharPtrBuiltinVaList; 3091 } 3092 }; 3093 } // end anonymous namespace 3094 3095 namespace { 3096 // x86-64 Windows Visual Studio target 3097 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 3098 public: 3099 VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple) 3100 : WindowsX86_64TargetInfo(Triple) { 3101 LongDoubleWidth = LongDoubleAlign = 64; 3102 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3103 } 3104 virtual void getTargetDefines(const LangOptions &Opts, 3105 MacroBuilder &Builder) const { 3106 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3107 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3108 Builder.defineMacro("_M_X64"); 3109 Builder.defineMacro("_M_AMD64"); 3110 } 3111 }; 3112 } // end anonymous namespace 3113 3114 namespace { 3115 // x86-64 MinGW target 3116 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3117 public: 3118 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3119 : WindowsX86_64TargetInfo(Triple) {} 3120 virtual void getTargetDefines(const LangOptions &Opts, 3121 MacroBuilder &Builder) const { 3122 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3123 DefineStd(Builder, "WIN64", Opts); 3124 Builder.defineMacro("__MSVCRT__"); 3125 Builder.defineMacro("__MINGW32__"); 3126 Builder.defineMacro("__MINGW64__"); 3127 3128 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3129 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3130 if (Opts.MicrosoftExt) 3131 // Provide "as-is" __declspec. 3132 Builder.defineMacro("__declspec", "__declspec"); 3133 else 3134 // Provide alias of __attribute__ like mingw32-gcc. 3135 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3136 } 3137 }; 3138 } // end anonymous namespace 3139 3140 namespace { 3141 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3142 public: 3143 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3144 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3145 Int64Type = SignedLongLong; 3146 MaxVectorAlign = 256; 3147 } 3148 }; 3149 } // end anonymous namespace 3150 3151 namespace { 3152 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3153 public: 3154 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3155 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3156 IntMaxType = SignedLongLong; 3157 UIntMaxType = UnsignedLongLong; 3158 Int64Type = SignedLongLong; 3159 } 3160 }; 3161 } // end anonymous namespace 3162 3163 namespace { 3164 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3165 public: 3166 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3167 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3168 IntMaxType = SignedLongLong; 3169 UIntMaxType = UnsignedLongLong; 3170 Int64Type = SignedLongLong; 3171 } 3172 }; 3173 } 3174 3175 namespace { 3176 class AArch64TargetInfo : public TargetInfo { 3177 static const char * const GCCRegNames[]; 3178 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3179 3180 enum FPUModeEnum { 3181 FPUMode, 3182 NeonMode 3183 }; 3184 3185 unsigned FPU; 3186 static const Builtin::Info BuiltinInfo[]; 3187 3188 public: 3189 AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 3190 BigEndian = false; 3191 LongWidth = LongAlign = 64; 3192 LongDoubleWidth = LongDoubleAlign = 128; 3193 PointerWidth = PointerAlign = 64; 3194 SuitableAlign = 128; 3195 DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3196 "i64:64:64-i128:128:128-f32:32:32-f64:64:64-" 3197 "f128:128:128-n32:64-S128"; 3198 3199 WCharType = UnsignedInt; 3200 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3201 3202 // AArch64 backend supports 64-bit operations at the moment. In principle 3203 // 128-bit is possible if register-pairs are used. 3204 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3205 3206 TheCXXABI.set(TargetCXXABI::GenericAArch64); 3207 } 3208 virtual void getTargetDefines(const LangOptions &Opts, 3209 MacroBuilder &Builder) const { 3210 // GCC defines theses currently 3211 Builder.defineMacro("__aarch64__"); 3212 Builder.defineMacro("__AARCH64EL__"); 3213 3214 // ACLE predefines. Many can only have one possible value on v8 AArch64. 3215 3216 // FIXME: these were written based on an unreleased version of a 32-bit ACLE 3217 // which was intended to be compatible with a 64-bit implementation. They 3218 // will need updating when a real 64-bit ACLE exists. Particularly pressing 3219 // instances are: __ARM_ARCH_ISA_ARM, __ARM_ARCH_ISA_THUMB, __ARM_PCS. 3220 Builder.defineMacro("__ARM_ACLE", "101"); 3221 Builder.defineMacro("__ARM_ARCH", "8"); 3222 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 3223 3224 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 3225 Builder.defineMacro("__ARM_FEATURE_CLZ"); 3226 Builder.defineMacro("__ARM_FEATURE_FMA"); 3227 3228 // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean 3229 // 128-bit LDXP present, at which point this becomes 0x1f. 3230 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xf"); 3231 3232 // 0xe implies support for half, single and double precision operations. 3233 Builder.defineMacro("__ARM_FP", "0xe"); 3234 3235 // PCS specifies this for SysV variants, which is all we support. Other ABIs 3236 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 3237 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 3238 3239 if (Opts.FastMath || Opts.FiniteMathOnly) 3240 Builder.defineMacro("__ARM_FP_FAST"); 3241 3242 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 3243 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 3244 3245 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3246 Opts.ShortWChar ? "2" : "4"); 3247 3248 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3249 Opts.ShortEnums ? "1" : "4"); 3250 3251 if (BigEndian) 3252 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 3253 3254 if (FPU == NeonMode) { 3255 Builder.defineMacro("__AARCH_FEATURE_ADVSIMD"); 3256 3257 // 64-bit NEON supports half, single and double precision operations. 3258 Builder.defineMacro("__AARCH_ADVSIMD_FP", "0xe"); 3259 } 3260 } 3261 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3262 unsigned &NumRecords) const { 3263 Records = BuiltinInfo; 3264 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin; 3265 } 3266 virtual bool hasFeature(StringRef Feature) const { 3267 return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode); 3268 } 3269 3270 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 3271 StringRef Name, bool Enabled) const { 3272 if (Name == "neon") { 3273 Features[Name] = Enabled; 3274 return true; 3275 } 3276 3277 return false; 3278 } 3279 3280 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 3281 FPU = FPUMode; 3282 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3283 if (Features[i] == "+neon") 3284 FPU = NeonMode; 3285 } 3286 } 3287 3288 virtual void getGCCRegNames(const char *const *&Names, 3289 unsigned &NumNames) const; 3290 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3291 unsigned &NumAliases) const; 3292 3293 virtual bool isCLZForZeroUndef() const { return false; } 3294 3295 virtual bool validateAsmConstraint(const char *&Name, 3296 TargetInfo::ConstraintInfo &Info) const { 3297 switch (*Name) { 3298 default: return false; 3299 case 'w': // An FP/SIMD vector register 3300 Info.setAllowsRegister(); 3301 return true; 3302 case 'I': // Constant that can be used with an ADD instruction 3303 case 'J': // Constant that can be used with a SUB instruction 3304 case 'K': // Constant that can be used with a 32-bit logical instruction 3305 case 'L': // Constant that can be used with a 64-bit logical instruction 3306 case 'M': // Constant that can be used as a 32-bit MOV immediate 3307 case 'N': // Constant that can be used as a 64-bit MOV immediate 3308 case 'Y': // Floating point constant zero 3309 case 'Z': // Integer constant zero 3310 return true; 3311 case 'Q': // A memory reference with base register and no offset 3312 Info.setAllowsMemory(); 3313 return true; 3314 case 'S': // A symbolic address 3315 Info.setAllowsRegister(); 3316 return true; 3317 case 'U': 3318 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 3319 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 3320 // Usa: An absolute symbolic address 3321 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 3322 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 3323 } 3324 } 3325 3326 virtual const char *getClobbers() const { 3327 // There are no AArch64 clobbers shared by all asm statements. 3328 return ""; 3329 } 3330 3331 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3332 return TargetInfo::AArch64ABIBuiltinVaList; 3333 } 3334 }; 3335 3336 const char * const AArch64TargetInfo::GCCRegNames[] = { 3337 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", 3338 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", 3339 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", 3340 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr", 3341 3342 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 3343 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 3344 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 3345 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr", 3346 3347 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", 3348 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", 3349 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", 3350 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31", 3351 3352 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", 3353 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", 3354 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", 3355 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", 3356 3357 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3358 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3359 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3360 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3361 3362 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3363 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3364 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3365 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3366 3367 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3368 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", 3369 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", 3370 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" 3371 }; 3372 3373 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names, 3374 unsigned &NumNames) const { 3375 Names = GCCRegNames; 3376 NumNames = llvm::array_lengthof(GCCRegNames); 3377 } 3378 3379 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 3380 { { "x16" }, "ip0"}, 3381 { { "x17" }, "ip1"}, 3382 { { "x29" }, "fp" }, 3383 { { "x30" }, "lr" } 3384 }; 3385 3386 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3387 unsigned &NumAliases) const { 3388 Aliases = GCCRegAliases; 3389 NumAliases = llvm::array_lengthof(GCCRegAliases); 3390 3391 } 3392 3393 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 3394 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3395 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3396 ALL_LANGUAGES }, 3397 #include "clang/Basic/BuiltinsAArch64.def" 3398 }; 3399 3400 } // end anonymous namespace 3401 3402 namespace { 3403 class ARMTargetInfo : public TargetInfo { 3404 // Possible FPU choices. 3405 enum FPUMode { 3406 VFP2FPU = (1 << 0), 3407 VFP3FPU = (1 << 1), 3408 VFP4FPU = (1 << 2), 3409 NeonFPU = (1 << 3) 3410 }; 3411 3412 static bool FPUModeIsVFP(FPUMode Mode) { 3413 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU); 3414 } 3415 3416 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3417 static const char * const GCCRegNames[]; 3418 3419 std::string ABI, CPU; 3420 3421 unsigned FPU : 4; 3422 3423 unsigned IsAAPCS : 1; 3424 unsigned IsThumb : 1; 3425 3426 // Initialized via features. 3427 unsigned SoftFloat : 1; 3428 unsigned SoftFloatABI : 1; 3429 3430 static const Builtin::Info BuiltinInfo[]; 3431 3432 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3433 // On linux, binaries targeting old cpus call functions in libgcc to 3434 // perform atomic operations. The implementation in libgcc then calls into 3435 // the kernel which on armv6 and newer uses ldrex and strex. The net result 3436 // is that if we assume the kernel is at least as recent as the hardware, 3437 // it is safe to use atomic instructions on armv6 and newer. 3438 if (T.getOS() != llvm::Triple::Linux && 3439 T.getOS() != llvm::Triple::FreeBSD && 3440 T.getOS() != llvm::Triple::Bitrig) 3441 return false; 3442 StringRef ArchName = T.getArchName(); 3443 if (T.getArch() == llvm::Triple::arm) { 3444 if (!ArchName.startswith("armv")) 3445 return false; 3446 StringRef VersionStr = ArchName.substr(4); 3447 unsigned Version; 3448 if (VersionStr.getAsInteger(10, Version)) 3449 return false; 3450 return Version >= 6; 3451 } 3452 assert(T.getArch() == llvm::Triple::thumb); 3453 if (!ArchName.startswith("thumbv")) 3454 return false; 3455 StringRef VersionStr = ArchName.substr(6); 3456 unsigned Version; 3457 if (VersionStr.getAsInteger(10, Version)) 3458 return false; 3459 return Version >= 7; 3460 } 3461 3462 public: 3463 ARMTargetInfo(const llvm::Triple &Triple) 3464 : TargetInfo(Triple), ABI("aapcs-linux"), CPU("arm1136j-s"), 3465 IsAAPCS(true) { 3466 BigEndian = false; 3467 SizeType = UnsignedInt; 3468 PtrDiffType = SignedInt; 3469 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3470 WCharType = UnsignedInt; 3471 3472 // {} in inline assembly are neon specifiers, not assembly variant 3473 // specifiers. 3474 NoAsmVariants = true; 3475 3476 // FIXME: Should we just treat this as a feature? 3477 IsThumb = getTriple().getArchName().startswith("thumb"); 3478 if (IsThumb) { 3479 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3480 // so set preferred for small types to 32. 3481 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3482 "i64:64:64-f32:32:32-f64:64:64-" 3483 "v64:64:64-v128:64:128-a0:0:32-n32-S64"); 3484 } else { 3485 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3486 "i64:64:64-f32:32:32-f64:64:64-" 3487 "v64:64:64-v128:64:128-a0:0:64-n32-S64"); 3488 } 3489 3490 // ARM targets default to using the ARM C++ ABI. 3491 TheCXXABI.set(TargetCXXABI::GenericARM); 3492 3493 // ARM has atomics up to 8 bytes 3494 MaxAtomicPromoteWidth = 64; 3495 if (shouldUseInlineAtomic(getTriple())) 3496 MaxAtomicInlineWidth = 64; 3497 3498 // Do force alignment of members that follow zero length bitfields. If 3499 // the alignment of the zero-length bitfield is greater than the member 3500 // that follows it, `bar', `bar' will be aligned as the type of the 3501 // zero length bitfield. 3502 UseZeroLengthBitfieldAlignment = true; 3503 } 3504 virtual const char *getABI() const { return ABI.c_str(); } 3505 virtual bool setABI(const std::string &Name) { 3506 ABI = Name; 3507 3508 // The defaults (above) are for AAPCS, check if we need to change them. 3509 // 3510 // FIXME: We need support for -meabi... we could just mangle it into the 3511 // name. 3512 if (Name == "apcs-gnu") { 3513 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3514 // size_t is unsigned int on FreeBSD. 3515 if (getTriple().getOS() != llvm::Triple::FreeBSD) 3516 SizeType = UnsignedLong; 3517 3518 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3519 WCharType = SignedInt; 3520 3521 // Do not respect the alignment of bit-field types when laying out 3522 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3523 UseBitFieldTypeAlignment = false; 3524 3525 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3526 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3527 /// gcc. 3528 ZeroLengthBitfieldBoundary = 32; 3529 3530 IsAAPCS = false; 3531 3532 if (IsThumb) { 3533 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3534 // so set preferred for small types to 32. 3535 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3536 "i64:32:64-f32:32:32-f64:32:64-" 3537 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3538 } else { 3539 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3540 "i64:32:64-f32:32:32-f64:32:64-" 3541 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3542 } 3543 3544 // FIXME: Override "preferred align" for double and long long. 3545 } else if (Name == "aapcs" || Name == "aapcs-vfp") { 3546 // size_t is unsigned long on Darwin. 3547 if (getTriple().isOSDarwin()) 3548 SizeType = UnsignedLong; 3549 IsAAPCS = true; 3550 // FIXME: Enumerated types are variable width in straight AAPCS. 3551 } else if (Name == "aapcs-linux") { 3552 IsAAPCS = true; 3553 } else 3554 return false; 3555 3556 return true; 3557 } 3558 3559 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3560 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3561 Features["vfp2"] = true; 3562 else if (CPU == "cortex-a8" || CPU == "cortex-a15" || 3563 CPU == "cortex-a9" || CPU == "cortex-a9-mp") 3564 Features["neon"] = true; 3565 else if (CPU == "swift" || CPU == "cortex-a7") { 3566 Features["vfp4"] = true; 3567 Features["neon"] = true; 3568 } 3569 } 3570 3571 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 3572 StringRef Name, 3573 bool Enabled) const { 3574 if (Name == "soft-float" || Name == "soft-float-abi" || 3575 Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" || 3576 Name == "d16" || Name == "neonfp" || Name == "v8fp") { 3577 Features[Name] = Enabled; 3578 } else 3579 return false; 3580 3581 return true; 3582 } 3583 3584 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 3585 FPU = 0; 3586 SoftFloat = SoftFloatABI = false; 3587 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3588 if (Features[i] == "+soft-float") 3589 SoftFloat = true; 3590 else if (Features[i] == "+soft-float-abi") 3591 SoftFloatABI = true; 3592 else if (Features[i] == "+vfp2") 3593 FPU |= VFP2FPU; 3594 else if (Features[i] == "+vfp3") 3595 FPU |= VFP3FPU; 3596 else if (Features[i] == "+vfp4") 3597 FPU |= VFP4FPU; 3598 else if (Features[i] == "+neon") 3599 FPU |= NeonFPU; 3600 } 3601 3602 // Remove front-end specific options which the backend handles differently. 3603 std::vector<std::string>::iterator it; 3604 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3605 if (it != Features.end()) 3606 Features.erase(it); 3607 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3608 if (it != Features.end()) 3609 Features.erase(it); 3610 } 3611 3612 virtual bool hasFeature(StringRef Feature) const { 3613 return llvm::StringSwitch<bool>(Feature) 3614 .Case("arm", true) 3615 .Case("softfloat", SoftFloat) 3616 .Case("thumb", IsThumb) 3617 .Case("neon", FPU == NeonFPU && !SoftFloat && 3618 StringRef(getCPUDefineSuffix(CPU)).startswith("7")) 3619 .Default(false); 3620 } 3621 // FIXME: Should we actually have some table instead of these switches? 3622 static const char *getCPUDefineSuffix(StringRef Name) { 3623 return llvm::StringSwitch<const char*>(Name) 3624 .Cases("arm8", "arm810", "4") 3625 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3626 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3627 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3628 .Case("ep9312", "4T") 3629 .Cases("arm10tdmi", "arm1020t", "5T") 3630 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3631 .Case("arm926ej-s", "5TEJ") 3632 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3633 .Cases("xscale", "iwmmxt", "5TE") 3634 .Case("arm1136j-s", "6J") 3635 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3636 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3637 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3638 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A") 3639 .Cases("cortex-a9", "cortex-a15", "7A") 3640 .Case("cortex-r5", "7R") 3641 .Case("cortex-a9-mp", "7F") 3642 .Case("swift", "7S") 3643 .Cases("cortex-m3", "cortex-m4", "7M") 3644 .Case("cortex-m0", "6M") 3645 .Case("cortex-a53", "8A") 3646 .Default(0); 3647 } 3648 static const char *getCPUProfile(StringRef Name) { 3649 return llvm::StringSwitch<const char*>(Name) 3650 .Cases("cortex-a8", "cortex-a9", "A") 3651 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 3652 .Case("cortex-r5", "R") 3653 .Default(""); 3654 } 3655 virtual bool setCPU(const std::string &Name) { 3656 if (!getCPUDefineSuffix(Name)) 3657 return false; 3658 3659 CPU = Name; 3660 return true; 3661 } 3662 virtual void getTargetDefines(const LangOptions &Opts, 3663 MacroBuilder &Builder) const { 3664 // Target identification. 3665 Builder.defineMacro("__arm"); 3666 Builder.defineMacro("__arm__"); 3667 3668 // Target properties. 3669 Builder.defineMacro("__ARMEL__"); 3670 Builder.defineMacro("__LITTLE_ENDIAN__"); 3671 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3672 3673 StringRef CPUArch = getCPUDefineSuffix(CPU); 3674 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 3675 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 3676 StringRef CPUProfile = getCPUProfile(CPU); 3677 if (!CPUProfile.empty()) 3678 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 3679 3680 // Subtarget options. 3681 3682 // FIXME: It's more complicated than this and we don't really support 3683 // interworking. 3684 if ('5' <= CPUArch[0] && CPUArch[0] <= '7') 3685 Builder.defineMacro("__THUMB_INTERWORK__"); 3686 3687 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 3688 // M-class CPUs on Darwin follow AAPCS, but not EABI. 3689 if (!(getTriple().isOSDarwin() && CPUProfile == "M")) 3690 Builder.defineMacro("__ARM_EABI__"); 3691 Builder.defineMacro("__ARM_PCS", "1"); 3692 3693 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 3694 Builder.defineMacro("__ARM_PCS_VFP", "1"); 3695 } 3696 3697 if (SoftFloat) 3698 Builder.defineMacro("__SOFTFP__"); 3699 3700 if (CPU == "xscale") 3701 Builder.defineMacro("__XSCALE__"); 3702 3703 bool IsARMv7 = CPUArch.startswith("7"); 3704 if (IsThumb) { 3705 Builder.defineMacro("__THUMBEL__"); 3706 Builder.defineMacro("__thumb__"); 3707 if (CPUArch == "6T2" || IsARMv7) 3708 Builder.defineMacro("__thumb2__"); 3709 } 3710 3711 // Note, this is always on in gcc, even though it doesn't make sense. 3712 Builder.defineMacro("__APCS_32__"); 3713 3714 if (FPUModeIsVFP((FPUMode) FPU)) { 3715 Builder.defineMacro("__VFP_FP__"); 3716 if (FPU & VFP2FPU) 3717 Builder.defineMacro("__ARM_VFPV2__"); 3718 if (FPU & VFP3FPU) 3719 Builder.defineMacro("__ARM_VFPV3__"); 3720 if (FPU & VFP4FPU) 3721 Builder.defineMacro("__ARM_VFPV4__"); 3722 } 3723 3724 // This only gets set when Neon instructions are actually available, unlike 3725 // the VFP define, hence the soft float and arch check. This is subtly 3726 // different from gcc, we follow the intent which was that it should be set 3727 // when Neon instructions are actually available. 3728 if ((FPU & NeonFPU) && !SoftFloat && IsARMv7) 3729 Builder.defineMacro("__ARM_NEON__"); 3730 } 3731 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3732 unsigned &NumRecords) const { 3733 Records = BuiltinInfo; 3734 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 3735 } 3736 virtual bool isCLZForZeroUndef() const { return false; } 3737 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3738 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 3739 } 3740 virtual void getGCCRegNames(const char * const *&Names, 3741 unsigned &NumNames) const; 3742 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3743 unsigned &NumAliases) const; 3744 virtual bool validateAsmConstraint(const char *&Name, 3745 TargetInfo::ConstraintInfo &Info) const { 3746 switch (*Name) { 3747 default: break; 3748 case 'l': // r0-r7 3749 case 'h': // r8-r15 3750 case 'w': // VFP Floating point register single precision 3751 case 'P': // VFP Floating point register double precision 3752 Info.setAllowsRegister(); 3753 return true; 3754 case 'Q': // A memory address that is a single base register. 3755 Info.setAllowsMemory(); 3756 return true; 3757 case 'U': // a memory reference... 3758 switch (Name[1]) { 3759 case 'q': // ...ARMV4 ldrsb 3760 case 'v': // ...VFP load/store (reg+constant offset) 3761 case 'y': // ...iWMMXt load/store 3762 case 't': // address valid for load/store opaque types wider 3763 // than 128-bits 3764 case 'n': // valid address for Neon doubleword vector load/store 3765 case 'm': // valid address for Neon element and structure load/store 3766 case 's': // valid address for non-offset loads/stores of quad-word 3767 // values in four ARM registers 3768 Info.setAllowsMemory(); 3769 Name++; 3770 return true; 3771 } 3772 } 3773 return false; 3774 } 3775 virtual std::string convertConstraint(const char *&Constraint) const { 3776 std::string R; 3777 switch (*Constraint) { 3778 case 'U': // Two-character constraint; add "^" hint for later parsing. 3779 R = std::string("^") + std::string(Constraint, 2); 3780 Constraint++; 3781 break; 3782 case 'p': // 'p' should be translated to 'r' by default. 3783 R = std::string("r"); 3784 break; 3785 default: 3786 return std::string(1, *Constraint); 3787 } 3788 return R; 3789 } 3790 virtual bool validateConstraintModifier(StringRef Constraint, 3791 const char Modifier, 3792 unsigned Size) const { 3793 bool isOutput = (Constraint[0] == '='); 3794 bool isInOut = (Constraint[0] == '+'); 3795 3796 // Strip off constraint modifiers. 3797 while (Constraint[0] == '=' || 3798 Constraint[0] == '+' || 3799 Constraint[0] == '&') 3800 Constraint = Constraint.substr(1); 3801 3802 switch (Constraint[0]) { 3803 default: break; 3804 case 'r': { 3805 switch (Modifier) { 3806 default: 3807 return (isInOut || isOutput || Size <= 32); 3808 case 'q': 3809 // A register of size 32 cannot fit a vector type. 3810 return false; 3811 } 3812 } 3813 } 3814 3815 return true; 3816 } 3817 virtual const char *getClobbers() const { 3818 // FIXME: Is this really right? 3819 return ""; 3820 } 3821 3822 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3823 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 3824 } 3825 3826 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 3827 if (RegNo == 0) return 0; 3828 if (RegNo == 1) return 1; 3829 return -1; 3830 } 3831 }; 3832 3833 const char * const ARMTargetInfo::GCCRegNames[] = { 3834 // Integer registers 3835 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3836 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 3837 3838 // Float registers 3839 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3840 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3841 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3842 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3843 3844 // Double registers 3845 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3846 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3847 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3848 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3849 3850 // Quad registers 3851 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3852 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 3853 }; 3854 3855 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 3856 unsigned &NumNames) const { 3857 Names = GCCRegNames; 3858 NumNames = llvm::array_lengthof(GCCRegNames); 3859 } 3860 3861 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 3862 { { "a1" }, "r0" }, 3863 { { "a2" }, "r1" }, 3864 { { "a3" }, "r2" }, 3865 { { "a4" }, "r3" }, 3866 { { "v1" }, "r4" }, 3867 { { "v2" }, "r5" }, 3868 { { "v3" }, "r6" }, 3869 { { "v4" }, "r7" }, 3870 { { "v5" }, "r8" }, 3871 { { "v6", "rfp" }, "r9" }, 3872 { { "sl" }, "r10" }, 3873 { { "fp" }, "r11" }, 3874 { { "ip" }, "r12" }, 3875 { { "r13" }, "sp" }, 3876 { { "r14" }, "lr" }, 3877 { { "r15" }, "pc" }, 3878 // The S, D and Q registers overlap, but aren't really aliases; we 3879 // don't want to substitute one of these for a different-sized one. 3880 }; 3881 3882 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3883 unsigned &NumAliases) const { 3884 Aliases = GCCRegAliases; 3885 NumAliases = llvm::array_lengthof(GCCRegAliases); 3886 } 3887 3888 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 3889 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3890 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3891 ALL_LANGUAGES }, 3892 #include "clang/Basic/BuiltinsARM.def" 3893 }; 3894 } // end anonymous namespace. 3895 3896 namespace { 3897 class DarwinARMTargetInfo : 3898 public DarwinTargetInfo<ARMTargetInfo> { 3899 protected: 3900 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3901 MacroBuilder &Builder) const { 3902 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 3903 } 3904 3905 public: 3906 DarwinARMTargetInfo(const llvm::Triple &Triple) 3907 : DarwinTargetInfo<ARMTargetInfo>(Triple) { 3908 HasAlignMac68kSupport = true; 3909 // iOS always has 64-bit atomic instructions. 3910 // FIXME: This should be based off of the target features in ARMTargetInfo. 3911 MaxAtomicInlineWidth = 64; 3912 3913 // Darwin on iOS uses a variant of the ARM C++ ABI. 3914 TheCXXABI.set(TargetCXXABI::iOS); 3915 } 3916 }; 3917 } // end anonymous namespace. 3918 3919 3920 namespace { 3921 // Hexagon abstract base class 3922 class HexagonTargetInfo : public TargetInfo { 3923 static const Builtin::Info BuiltinInfo[]; 3924 static const char * const GCCRegNames[]; 3925 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3926 std::string CPU; 3927 public: 3928 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 3929 BigEndian = false; 3930 DescriptionString = ("e-p:32:32:32-" 3931 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-" 3932 "f64:64:64-f32:32:32-a0:0-n32"); 3933 3934 // {} in inline assembly are packet specifiers, not assembly variant 3935 // specifiers. 3936 NoAsmVariants = true; 3937 } 3938 3939 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3940 unsigned &NumRecords) const { 3941 Records = BuiltinInfo; 3942 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 3943 } 3944 3945 virtual bool validateAsmConstraint(const char *&Name, 3946 TargetInfo::ConstraintInfo &Info) const { 3947 return true; 3948 } 3949 3950 virtual void getTargetDefines(const LangOptions &Opts, 3951 MacroBuilder &Builder) const; 3952 3953 virtual bool hasFeature(StringRef Feature) const { 3954 return Feature == "hexagon"; 3955 } 3956 3957 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3958 return TargetInfo::CharPtrBuiltinVaList; 3959 } 3960 virtual void getGCCRegNames(const char * const *&Names, 3961 unsigned &NumNames) const; 3962 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3963 unsigned &NumAliases) const; 3964 virtual const char *getClobbers() const { 3965 return ""; 3966 } 3967 3968 static const char *getHexagonCPUSuffix(StringRef Name) { 3969 return llvm::StringSwitch<const char*>(Name) 3970 .Case("hexagonv4", "4") 3971 .Case("hexagonv5", "5") 3972 .Default(0); 3973 } 3974 3975 virtual bool setCPU(const std::string &Name) { 3976 if (!getHexagonCPUSuffix(Name)) 3977 return false; 3978 3979 CPU = Name; 3980 return true; 3981 } 3982 }; 3983 3984 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 3985 MacroBuilder &Builder) const { 3986 Builder.defineMacro("qdsp6"); 3987 Builder.defineMacro("__qdsp6", "1"); 3988 Builder.defineMacro("__qdsp6__", "1"); 3989 3990 Builder.defineMacro("hexagon"); 3991 Builder.defineMacro("__hexagon", "1"); 3992 Builder.defineMacro("__hexagon__", "1"); 3993 3994 if(CPU == "hexagonv1") { 3995 Builder.defineMacro("__HEXAGON_V1__"); 3996 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 3997 if(Opts.HexagonQdsp6Compat) { 3998 Builder.defineMacro("__QDSP6_V1__"); 3999 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4000 } 4001 } 4002 else if(CPU == "hexagonv2") { 4003 Builder.defineMacro("__HEXAGON_V2__"); 4004 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4005 if(Opts.HexagonQdsp6Compat) { 4006 Builder.defineMacro("__QDSP6_V2__"); 4007 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4008 } 4009 } 4010 else if(CPU == "hexagonv3") { 4011 Builder.defineMacro("__HEXAGON_V3__"); 4012 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4013 if(Opts.HexagonQdsp6Compat) { 4014 Builder.defineMacro("__QDSP6_V3__"); 4015 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4016 } 4017 } 4018 else if(CPU == "hexagonv4") { 4019 Builder.defineMacro("__HEXAGON_V4__"); 4020 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4021 if(Opts.HexagonQdsp6Compat) { 4022 Builder.defineMacro("__QDSP6_V4__"); 4023 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4024 } 4025 } 4026 else if(CPU == "hexagonv5") { 4027 Builder.defineMacro("__HEXAGON_V5__"); 4028 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4029 if(Opts.HexagonQdsp6Compat) { 4030 Builder.defineMacro("__QDSP6_V5__"); 4031 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4032 } 4033 } 4034 } 4035 4036 const char * const HexagonTargetInfo::GCCRegNames[] = { 4037 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4038 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4039 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4040 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4041 "p0", "p1", "p2", "p3", 4042 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4043 }; 4044 4045 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4046 unsigned &NumNames) const { 4047 Names = GCCRegNames; 4048 NumNames = llvm::array_lengthof(GCCRegNames); 4049 } 4050 4051 4052 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4053 { { "sp" }, "r29" }, 4054 { { "fp" }, "r30" }, 4055 { { "lr" }, "r31" }, 4056 }; 4057 4058 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4059 unsigned &NumAliases) const { 4060 Aliases = GCCRegAliases; 4061 NumAliases = llvm::array_lengthof(GCCRegAliases); 4062 } 4063 4064 4065 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4066 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4067 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4068 ALL_LANGUAGES }, 4069 #include "clang/Basic/BuiltinsHexagon.def" 4070 }; 4071 } 4072 4073 4074 namespace { 4075 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4076 class SparcTargetInfo : public TargetInfo { 4077 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4078 static const char * const GCCRegNames[]; 4079 bool SoftFloat; 4080 public: 4081 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4082 4083 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 4084 StringRef Name, 4085 bool Enabled) const { 4086 if (Name == "soft-float") 4087 Features[Name] = Enabled; 4088 else 4089 return false; 4090 4091 return true; 4092 } 4093 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 4094 SoftFloat = false; 4095 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4096 if (Features[i] == "+soft-float") 4097 SoftFloat = true; 4098 } 4099 virtual void getTargetDefines(const LangOptions &Opts, 4100 MacroBuilder &Builder) const { 4101 DefineStd(Builder, "sparc", Opts); 4102 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4103 4104 if (SoftFloat) 4105 Builder.defineMacro("SOFT_FLOAT", "1"); 4106 } 4107 4108 virtual bool hasFeature(StringRef Feature) const { 4109 return llvm::StringSwitch<bool>(Feature) 4110 .Case("softfloat", SoftFloat) 4111 .Case("sparc", true) 4112 .Default(false); 4113 } 4114 4115 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4116 unsigned &NumRecords) const { 4117 // FIXME: Implement! 4118 } 4119 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4120 return TargetInfo::VoidPtrBuiltinVaList; 4121 } 4122 virtual void getGCCRegNames(const char * const *&Names, 4123 unsigned &NumNames) const; 4124 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4125 unsigned &NumAliases) const; 4126 virtual bool validateAsmConstraint(const char *&Name, 4127 TargetInfo::ConstraintInfo &info) const { 4128 // FIXME: Implement! 4129 return false; 4130 } 4131 virtual const char *getClobbers() const { 4132 // FIXME: Implement! 4133 return ""; 4134 } 4135 }; 4136 4137 const char * const SparcTargetInfo::GCCRegNames[] = { 4138 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4139 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4140 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4141 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4142 }; 4143 4144 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4145 unsigned &NumNames) const { 4146 Names = GCCRegNames; 4147 NumNames = llvm::array_lengthof(GCCRegNames); 4148 } 4149 4150 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4151 { { "g0" }, "r0" }, 4152 { { "g1" }, "r1" }, 4153 { { "g2" }, "r2" }, 4154 { { "g3" }, "r3" }, 4155 { { "g4" }, "r4" }, 4156 { { "g5" }, "r5" }, 4157 { { "g6" }, "r6" }, 4158 { { "g7" }, "r7" }, 4159 { { "o0" }, "r8" }, 4160 { { "o1" }, "r9" }, 4161 { { "o2" }, "r10" }, 4162 { { "o3" }, "r11" }, 4163 { { "o4" }, "r12" }, 4164 { { "o5" }, "r13" }, 4165 { { "o6", "sp" }, "r14" }, 4166 { { "o7" }, "r15" }, 4167 { { "l0" }, "r16" }, 4168 { { "l1" }, "r17" }, 4169 { { "l2" }, "r18" }, 4170 { { "l3" }, "r19" }, 4171 { { "l4" }, "r20" }, 4172 { { "l5" }, "r21" }, 4173 { { "l6" }, "r22" }, 4174 { { "l7" }, "r23" }, 4175 { { "i0" }, "r24" }, 4176 { { "i1" }, "r25" }, 4177 { { "i2" }, "r26" }, 4178 { { "i3" }, "r27" }, 4179 { { "i4" }, "r28" }, 4180 { { "i5" }, "r29" }, 4181 { { "i6", "fp" }, "r30" }, 4182 { { "i7" }, "r31" }, 4183 }; 4184 4185 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4186 unsigned &NumAliases) const { 4187 Aliases = GCCRegAliases; 4188 NumAliases = llvm::array_lengthof(GCCRegAliases); 4189 } 4190 4191 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 4192 class SparcV8TargetInfo : public SparcTargetInfo { 4193 public: 4194 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4195 // FIXME: Support Sparc quad-precision long double? 4196 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 4197 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 4198 } 4199 4200 virtual void getTargetDefines(const LangOptions &Opts, 4201 MacroBuilder &Builder) const { 4202 SparcTargetInfo::getTargetDefines(Opts, Builder); 4203 Builder.defineMacro("__sparcv8"); 4204 } 4205 }; 4206 4207 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 4208 class SparcV9TargetInfo : public SparcTargetInfo { 4209 public: 4210 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4211 // FIXME: Support Sparc quad-precision long double? 4212 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 4213 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128"; 4214 // This is an LP64 platform. 4215 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4216 4217 // OpenBSD uses long long for int64_t and intmax_t. 4218 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 4219 IntMaxType = SignedLongLong; 4220 UIntMaxType = UnsignedLongLong; 4221 } else { 4222 IntMaxType = SignedLong; 4223 UIntMaxType = UnsignedLong; 4224 } 4225 Int64Type = IntMaxType; 4226 } 4227 4228 virtual void getTargetDefines(const LangOptions &Opts, 4229 MacroBuilder &Builder) const { 4230 SparcTargetInfo::getTargetDefines(Opts, Builder); 4231 Builder.defineMacro("__sparcv9"); 4232 Builder.defineMacro("__arch64__"); 4233 // Solaris and its derivative AuroraUX don't need these variants, but the 4234 // BSDs do. 4235 if (getTriple().getOS() != llvm::Triple::Solaris && 4236 getTriple().getOS() != llvm::Triple::AuroraUX) { 4237 Builder.defineMacro("__sparc64__"); 4238 Builder.defineMacro("__sparc_v9__"); 4239 Builder.defineMacro("__sparcv9__"); 4240 } 4241 } 4242 }; 4243 4244 } // end anonymous namespace. 4245 4246 namespace { 4247 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 4248 public: 4249 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 4250 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 4251 SizeType = UnsignedInt; 4252 PtrDiffType = SignedInt; 4253 } 4254 }; 4255 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 4256 public: 4257 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 4258 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 4259 SizeType = UnsignedInt; 4260 PtrDiffType = SignedInt; 4261 } 4262 }; 4263 } // end anonymous namespace. 4264 4265 namespace { 4266 class SystemZTargetInfo : public TargetInfo { 4267 static const char *const GCCRegNames[]; 4268 4269 public: 4270 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4271 TLSSupported = true; 4272 IntWidth = IntAlign = 32; 4273 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 4274 PointerWidth = PointerAlign = 64; 4275 LongDoubleWidth = 128; 4276 LongDoubleAlign = 64; 4277 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4278 MinGlobalAlign = 16; 4279 DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64" 4280 "-f32:32-f64:64-f128:64-a0:8:16-n32:64"; 4281 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4282 } 4283 virtual void getTargetDefines(const LangOptions &Opts, 4284 MacroBuilder &Builder) const { 4285 Builder.defineMacro("__s390__"); 4286 Builder.defineMacro("__s390x__"); 4287 Builder.defineMacro("__zarch__"); 4288 Builder.defineMacro("__LONG_DOUBLE_128__"); 4289 } 4290 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4291 unsigned &NumRecords) const { 4292 // FIXME: Implement. 4293 Records = 0; 4294 NumRecords = 0; 4295 } 4296 4297 virtual void getGCCRegNames(const char *const *&Names, 4298 unsigned &NumNames) const; 4299 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4300 unsigned &NumAliases) const { 4301 // No aliases. 4302 Aliases = 0; 4303 NumAliases = 0; 4304 } 4305 virtual bool validateAsmConstraint(const char *&Name, 4306 TargetInfo::ConstraintInfo &info) const; 4307 virtual const char *getClobbers() const { 4308 // FIXME: Is this really right? 4309 return ""; 4310 } 4311 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4312 return TargetInfo::SystemZBuiltinVaList; 4313 } 4314 virtual bool setCPU(const std::string &Name) { 4315 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4316 .Case("z10", true) 4317 .Case("z196", true) 4318 .Case("zEC12", true) 4319 .Default(false); 4320 4321 // No need to store the CPU yet. There aren't any CPU-specific 4322 // macros to define. 4323 return CPUKnown; 4324 } 4325 }; 4326 4327 const char *const SystemZTargetInfo::GCCRegNames[] = { 4328 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4329 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4330 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 4331 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 4332 }; 4333 4334 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 4335 unsigned &NumNames) const { 4336 Names = GCCRegNames; 4337 NumNames = llvm::array_lengthof(GCCRegNames); 4338 } 4339 4340 bool SystemZTargetInfo:: 4341 validateAsmConstraint(const char *&Name, 4342 TargetInfo::ConstraintInfo &Info) const { 4343 switch (*Name) { 4344 default: 4345 return false; 4346 4347 case 'a': // Address register 4348 case 'd': // Data register (equivalent to 'r') 4349 case 'f': // Floating-point register 4350 Info.setAllowsRegister(); 4351 return true; 4352 4353 case 'I': // Unsigned 8-bit constant 4354 case 'J': // Unsigned 12-bit constant 4355 case 'K': // Signed 16-bit constant 4356 case 'L': // Signed 20-bit displacement (on all targets we support) 4357 case 'M': // 0x7fffffff 4358 return true; 4359 4360 case 'Q': // Memory with base and unsigned 12-bit displacement 4361 case 'R': // Likewise, plus an index 4362 case 'S': // Memory with base and signed 20-bit displacement 4363 case 'T': // Likewise, plus an index 4364 Info.setAllowsMemory(); 4365 return true; 4366 } 4367 } 4368 } 4369 4370 namespace { 4371 class MSP430TargetInfo : public TargetInfo { 4372 static const char * const GCCRegNames[]; 4373 public: 4374 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4375 BigEndian = false; 4376 TLSSupported = false; 4377 IntWidth = 16; IntAlign = 16; 4378 LongWidth = 32; LongLongWidth = 64; 4379 LongAlign = LongLongAlign = 16; 4380 PointerWidth = 16; PointerAlign = 16; 4381 SuitableAlign = 16; 4382 SizeType = UnsignedInt; 4383 IntMaxType = SignedLongLong; 4384 UIntMaxType = UnsignedLongLong; 4385 IntPtrType = SignedInt; 4386 PtrDiffType = SignedInt; 4387 SigAtomicType = SignedLong; 4388 DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"; 4389 } 4390 virtual void getTargetDefines(const LangOptions &Opts, 4391 MacroBuilder &Builder) const { 4392 Builder.defineMacro("MSP430"); 4393 Builder.defineMacro("__MSP430__"); 4394 // FIXME: defines for different 'flavours' of MCU 4395 } 4396 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4397 unsigned &NumRecords) const { 4398 // FIXME: Implement. 4399 Records = 0; 4400 NumRecords = 0; 4401 } 4402 virtual bool hasFeature(StringRef Feature) const { 4403 return Feature == "msp430"; 4404 } 4405 virtual void getGCCRegNames(const char * const *&Names, 4406 unsigned &NumNames) const; 4407 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4408 unsigned &NumAliases) const { 4409 // No aliases. 4410 Aliases = 0; 4411 NumAliases = 0; 4412 } 4413 virtual bool validateAsmConstraint(const char *&Name, 4414 TargetInfo::ConstraintInfo &info) const { 4415 // No target constraints for now. 4416 return false; 4417 } 4418 virtual const char *getClobbers() const { 4419 // FIXME: Is this really right? 4420 return ""; 4421 } 4422 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4423 // FIXME: implement 4424 return TargetInfo::CharPtrBuiltinVaList; 4425 } 4426 }; 4427 4428 const char * const MSP430TargetInfo::GCCRegNames[] = { 4429 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4430 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 4431 }; 4432 4433 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 4434 unsigned &NumNames) const { 4435 Names = GCCRegNames; 4436 NumNames = llvm::array_lengthof(GCCRegNames); 4437 } 4438 } 4439 4440 namespace { 4441 4442 // LLVM and Clang cannot be used directly to output native binaries for 4443 // target, but is used to compile C code to llvm bitcode with correct 4444 // type and alignment information. 4445 // 4446 // TCE uses the llvm bitcode as input and uses it for generating customized 4447 // target processor and program binary. TCE co-design environment is 4448 // publicly available in http://tce.cs.tut.fi 4449 4450 static const unsigned TCEOpenCLAddrSpaceMap[] = { 4451 3, // opencl_global 4452 4, // opencl_local 4453 5, // opencl_constant 4454 0, // cuda_device 4455 0, // cuda_constant 4456 0 // cuda_shared 4457 }; 4458 4459 class TCETargetInfo : public TargetInfo{ 4460 public: 4461 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4462 TLSSupported = false; 4463 IntWidth = 32; 4464 LongWidth = LongLongWidth = 32; 4465 PointerWidth = 32; 4466 IntAlign = 32; 4467 LongAlign = LongLongAlign = 32; 4468 PointerAlign = 32; 4469 SuitableAlign = 32; 4470 SizeType = UnsignedInt; 4471 IntMaxType = SignedLong; 4472 UIntMaxType = UnsignedLong; 4473 IntPtrType = SignedInt; 4474 PtrDiffType = SignedInt; 4475 FloatWidth = 32; 4476 FloatAlign = 32; 4477 DoubleWidth = 32; 4478 DoubleAlign = 32; 4479 LongDoubleWidth = 32; 4480 LongDoubleAlign = 32; 4481 FloatFormat = &llvm::APFloat::IEEEsingle; 4482 DoubleFormat = &llvm::APFloat::IEEEsingle; 4483 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 4484 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-" 4485 "i16:16:32-i32:32:32-i64:32:32-" 4486 "f32:32:32-f64:32:32-v64:32:32-" 4487 "v128:32:32-a0:0:32-n32"; 4488 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 4489 } 4490 4491 virtual void getTargetDefines(const LangOptions &Opts, 4492 MacroBuilder &Builder) const { 4493 DefineStd(Builder, "tce", Opts); 4494 Builder.defineMacro("__TCE__"); 4495 Builder.defineMacro("__TCE_V1__"); 4496 } 4497 virtual bool hasFeature(StringRef Feature) const { 4498 return Feature == "tce"; 4499 } 4500 4501 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4502 unsigned &NumRecords) const {} 4503 virtual const char *getClobbers() const { 4504 return ""; 4505 } 4506 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4507 return TargetInfo::VoidPtrBuiltinVaList; 4508 } 4509 virtual void getGCCRegNames(const char * const *&Names, 4510 unsigned &NumNames) const {} 4511 virtual bool validateAsmConstraint(const char *&Name, 4512 TargetInfo::ConstraintInfo &info) const { 4513 return true; 4514 } 4515 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4516 unsigned &NumAliases) const {} 4517 }; 4518 } 4519 4520 namespace { 4521 class MipsTargetInfoBase : public TargetInfo { 4522 static const Builtin::Info BuiltinInfo[]; 4523 std::string CPU; 4524 bool IsMips16; 4525 bool IsMicromips; 4526 bool IsSingleFloat; 4527 enum MipsFloatABI { 4528 HardFloat, SoftFloat 4529 } FloatABI; 4530 enum DspRevEnum { 4531 NoDSP, DSP1, DSP2 4532 } DspRev; 4533 bool HasMSA; 4534 4535 protected: 4536 std::string ABI; 4537 4538 public: 4539 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 4540 const std::string &CPUStr) 4541 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 4542 IsSingleFloat(false), FloatABI(HardFloat), DspRev(NoDSP), 4543 HasMSA(false), ABI(ABIStr) {} 4544 4545 virtual const char *getABI() const { return ABI.c_str(); } 4546 virtual bool setABI(const std::string &Name) = 0; 4547 virtual bool setCPU(const std::string &Name) { 4548 CPU = Name; 4549 return true; 4550 } 4551 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 4552 Features[ABI] = true; 4553 Features[CPU] = true; 4554 } 4555 4556 virtual void getTargetDefines(const LangOptions &Opts, 4557 MacroBuilder &Builder) const { 4558 DefineStd(Builder, "mips", Opts); 4559 Builder.defineMacro("_mips"); 4560 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4561 4562 switch (FloatABI) { 4563 case HardFloat: 4564 Builder.defineMacro("__mips_hard_float", Twine(1)); 4565 break; 4566 case SoftFloat: 4567 Builder.defineMacro("__mips_soft_float", Twine(1)); 4568 break; 4569 } 4570 4571 if (IsSingleFloat) 4572 Builder.defineMacro("__mips_single_float", Twine(1)); 4573 4574 if (IsMips16) 4575 Builder.defineMacro("__mips16", Twine(1)); 4576 4577 if (IsMicromips) 4578 Builder.defineMacro("__mips_micromips", Twine(1)); 4579 4580 switch (DspRev) { 4581 default: 4582 break; 4583 case DSP1: 4584 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 4585 Builder.defineMacro("__mips_dsp", Twine(1)); 4586 break; 4587 case DSP2: 4588 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 4589 Builder.defineMacro("__mips_dspr2", Twine(1)); 4590 Builder.defineMacro("__mips_dsp", Twine(1)); 4591 break; 4592 } 4593 4594 if (HasMSA) 4595 Builder.defineMacro("__mips_msa", Twine(1)); 4596 4597 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 4598 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 4599 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 4600 4601 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 4602 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 4603 } 4604 4605 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4606 unsigned &NumRecords) const { 4607 Records = BuiltinInfo; 4608 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 4609 } 4610 virtual bool hasFeature(StringRef Feature) const { 4611 return Feature == "mips"; 4612 } 4613 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4614 return TargetInfo::VoidPtrBuiltinVaList; 4615 } 4616 virtual void getGCCRegNames(const char * const *&Names, 4617 unsigned &NumNames) const { 4618 static const char * const GCCRegNames[] = { 4619 // CPU register names 4620 // Must match second column of GCCRegAliases 4621 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 4622 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 4623 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 4624 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 4625 // Floating point register names 4626 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 4627 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 4628 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 4629 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 4630 // Hi/lo and condition register names 4631 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 4632 "$fcc5","$fcc6","$fcc7" 4633 }; 4634 Names = GCCRegNames; 4635 NumNames = llvm::array_lengthof(GCCRegNames); 4636 } 4637 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4638 unsigned &NumAliases) const = 0; 4639 virtual bool validateAsmConstraint(const char *&Name, 4640 TargetInfo::ConstraintInfo &Info) const { 4641 switch (*Name) { 4642 default: 4643 return false; 4644 4645 case 'r': // CPU registers. 4646 case 'd': // Equivalent to "r" unless generating MIPS16 code. 4647 case 'y': // Equivalent to "r", backwards compatibility only. 4648 case 'f': // floating-point registers. 4649 case 'c': // $25 for indirect jumps 4650 case 'l': // lo register 4651 case 'x': // hilo register pair 4652 Info.setAllowsRegister(); 4653 return true; 4654 case 'R': // An address that can be used in a non-macro load or store 4655 Info.setAllowsMemory(); 4656 return true; 4657 } 4658 } 4659 4660 virtual const char *getClobbers() const { 4661 // FIXME: Implement! 4662 return ""; 4663 } 4664 4665 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 4666 StringRef Name, 4667 bool Enabled) const { 4668 if (Name == "soft-float" || Name == "single-float" || 4669 Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" || 4670 Name == "mips32" || Name == "mips32r2" || 4671 Name == "mips64" || Name == "mips64r2" || 4672 Name == "mips16" || Name == "micromips" || 4673 Name == "dsp" || Name == "dspr2" || 4674 Name == "msa") { 4675 Features[Name] = Enabled; 4676 return true; 4677 } else if (Name == "32") { 4678 Features["o32"] = Enabled; 4679 return true; 4680 } else if (Name == "64") { 4681 Features["n64"] = Enabled; 4682 return true; 4683 } 4684 return false; 4685 } 4686 4687 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 4688 IsMips16 = false; 4689 IsMicromips = false; 4690 IsSingleFloat = false; 4691 FloatABI = HardFloat; 4692 DspRev = NoDSP; 4693 4694 for (std::vector<std::string>::iterator it = Features.begin(), 4695 ie = Features.end(); it != ie; ++it) { 4696 if (*it == "+single-float") 4697 IsSingleFloat = true; 4698 else if (*it == "+soft-float") 4699 FloatABI = SoftFloat; 4700 else if (*it == "+mips16") 4701 IsMips16 = true; 4702 else if (*it == "+micromips") 4703 IsMicromips = true; 4704 else if (*it == "+dsp") 4705 DspRev = std::max(DspRev, DSP1); 4706 else if (*it == "+dspr2") 4707 DspRev = std::max(DspRev, DSP2); 4708 else if (*it == "+msa") 4709 HasMSA = true; 4710 } 4711 4712 // Remove front-end specific option. 4713 std::vector<std::string>::iterator it = 4714 std::find(Features.begin(), Features.end(), "+soft-float"); 4715 if (it != Features.end()) 4716 Features.erase(it); 4717 } 4718 4719 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 4720 if (RegNo == 0) return 4; 4721 if (RegNo == 1) return 5; 4722 return -1; 4723 } 4724 }; 4725 4726 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 4727 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4728 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4729 ALL_LANGUAGES }, 4730 #include "clang/Basic/BuiltinsMips.def" 4731 }; 4732 4733 class Mips32TargetInfoBase : public MipsTargetInfoBase { 4734 public: 4735 Mips32TargetInfoBase(const llvm::Triple &Triple) 4736 : MipsTargetInfoBase(Triple, "o32", "mips32") { 4737 SizeType = UnsignedInt; 4738 PtrDiffType = SignedInt; 4739 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 4740 } 4741 virtual bool setABI(const std::string &Name) { 4742 if ((Name == "o32") || (Name == "eabi")) { 4743 ABI = Name; 4744 return true; 4745 } else if (Name == "32") { 4746 ABI = "o32"; 4747 return true; 4748 } else 4749 return false; 4750 } 4751 virtual void getTargetDefines(const LangOptions &Opts, 4752 MacroBuilder &Builder) const { 4753 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 4754 4755 if (ABI == "o32") { 4756 Builder.defineMacro("__mips_o32"); 4757 Builder.defineMacro("_ABIO32", "1"); 4758 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 4759 } 4760 else if (ABI == "eabi") 4761 Builder.defineMacro("__mips_eabi"); 4762 else 4763 llvm_unreachable("Invalid ABI for Mips32."); 4764 } 4765 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4766 unsigned &NumAliases) const { 4767 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 4768 { { "at" }, "$1" }, 4769 { { "v0" }, "$2" }, 4770 { { "v1" }, "$3" }, 4771 { { "a0" }, "$4" }, 4772 { { "a1" }, "$5" }, 4773 { { "a2" }, "$6" }, 4774 { { "a3" }, "$7" }, 4775 { { "t0" }, "$8" }, 4776 { { "t1" }, "$9" }, 4777 { { "t2" }, "$10" }, 4778 { { "t3" }, "$11" }, 4779 { { "t4" }, "$12" }, 4780 { { "t5" }, "$13" }, 4781 { { "t6" }, "$14" }, 4782 { { "t7" }, "$15" }, 4783 { { "s0" }, "$16" }, 4784 { { "s1" }, "$17" }, 4785 { { "s2" }, "$18" }, 4786 { { "s3" }, "$19" }, 4787 { { "s4" }, "$20" }, 4788 { { "s5" }, "$21" }, 4789 { { "s6" }, "$22" }, 4790 { { "s7" }, "$23" }, 4791 { { "t8" }, "$24" }, 4792 { { "t9" }, "$25" }, 4793 { { "k0" }, "$26" }, 4794 { { "k1" }, "$27" }, 4795 { { "gp" }, "$28" }, 4796 { { "sp","$sp" }, "$29" }, 4797 { { "fp","$fp" }, "$30" }, 4798 { { "ra" }, "$31" } 4799 }; 4800 Aliases = GCCRegAliases; 4801 NumAliases = llvm::array_lengthof(GCCRegAliases); 4802 } 4803 }; 4804 4805 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 4806 public: 4807 Mips32EBTargetInfo(const llvm::Triple &Triple) 4808 : Mips32TargetInfoBase(Triple) { 4809 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4810 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 4811 } 4812 virtual void getTargetDefines(const LangOptions &Opts, 4813 MacroBuilder &Builder) const { 4814 DefineStd(Builder, "MIPSEB", Opts); 4815 Builder.defineMacro("_MIPSEB"); 4816 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 4817 } 4818 }; 4819 4820 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 4821 public: 4822 Mips32ELTargetInfo(const llvm::Triple &Triple) 4823 : Mips32TargetInfoBase(Triple) { 4824 BigEndian = false; 4825 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4826 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 4827 } 4828 virtual void getTargetDefines(const LangOptions &Opts, 4829 MacroBuilder &Builder) const { 4830 DefineStd(Builder, "MIPSEL", Opts); 4831 Builder.defineMacro("_MIPSEL"); 4832 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 4833 } 4834 }; 4835 4836 class Mips64TargetInfoBase : public MipsTargetInfoBase { 4837 virtual void SetDescriptionString(const std::string &Name) = 0; 4838 public: 4839 Mips64TargetInfoBase(const llvm::Triple &Triple) 4840 : MipsTargetInfoBase(Triple, "n64", "mips64") { 4841 LongWidth = LongAlign = 64; 4842 PointerWidth = PointerAlign = 64; 4843 LongDoubleWidth = LongDoubleAlign = 128; 4844 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4845 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 4846 LongDoubleWidth = LongDoubleAlign = 64; 4847 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4848 } 4849 SuitableAlign = 128; 4850 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4851 } 4852 virtual bool setABI(const std::string &Name) { 4853 SetDescriptionString(Name); 4854 if (Name == "n32") { 4855 LongWidth = LongAlign = 32; 4856 PointerWidth = PointerAlign = 32; 4857 ABI = Name; 4858 return true; 4859 } else if (Name == "n64") { 4860 ABI = Name; 4861 return true; 4862 } else if (Name == "64") { 4863 ABI = "n64"; 4864 return true; 4865 } else 4866 return false; 4867 } 4868 virtual void getTargetDefines(const LangOptions &Opts, 4869 MacroBuilder &Builder) const { 4870 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 4871 4872 Builder.defineMacro("__mips64"); 4873 Builder.defineMacro("__mips64__"); 4874 4875 if (ABI == "n32") { 4876 Builder.defineMacro("__mips_n32"); 4877 Builder.defineMacro("_ABIN32", "2"); 4878 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 4879 } 4880 else if (ABI == "n64") { 4881 Builder.defineMacro("__mips_n64"); 4882 Builder.defineMacro("_ABI64", "3"); 4883 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 4884 } 4885 else 4886 llvm_unreachable("Invalid ABI for Mips64."); 4887 } 4888 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4889 unsigned &NumAliases) const { 4890 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 4891 { { "at" }, "$1" }, 4892 { { "v0" }, "$2" }, 4893 { { "v1" }, "$3" }, 4894 { { "a0" }, "$4" }, 4895 { { "a1" }, "$5" }, 4896 { { "a2" }, "$6" }, 4897 { { "a3" }, "$7" }, 4898 { { "a4" }, "$8" }, 4899 { { "a5" }, "$9" }, 4900 { { "a6" }, "$10" }, 4901 { { "a7" }, "$11" }, 4902 { { "t0" }, "$12" }, 4903 { { "t1" }, "$13" }, 4904 { { "t2" }, "$14" }, 4905 { { "t3" }, "$15" }, 4906 { { "s0" }, "$16" }, 4907 { { "s1" }, "$17" }, 4908 { { "s2" }, "$18" }, 4909 { { "s3" }, "$19" }, 4910 { { "s4" }, "$20" }, 4911 { { "s5" }, "$21" }, 4912 { { "s6" }, "$22" }, 4913 { { "s7" }, "$23" }, 4914 { { "t8" }, "$24" }, 4915 { { "t9" }, "$25" }, 4916 { { "k0" }, "$26" }, 4917 { { "k1" }, "$27" }, 4918 { { "gp" }, "$28" }, 4919 { { "sp","$sp" }, "$29" }, 4920 { { "fp","$fp" }, "$30" }, 4921 { { "ra" }, "$31" } 4922 }; 4923 Aliases = GCCRegAliases; 4924 NumAliases = llvm::array_lengthof(GCCRegAliases); 4925 } 4926 }; 4927 4928 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 4929 virtual void SetDescriptionString(const std::string &Name) { 4930 // Change DescriptionString only if ABI is n32. 4931 if (Name == "n32") 4932 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4933 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 4934 "v64:64:64-n32:64-S128"; 4935 } 4936 public: 4937 Mips64EBTargetInfo(const llvm::Triple &Triple) 4938 : Mips64TargetInfoBase(Triple) { 4939 // Default ABI is n64. 4940 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4941 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 4942 "v64:64:64-n32:64-S128"; 4943 } 4944 virtual void getTargetDefines(const LangOptions &Opts, 4945 MacroBuilder &Builder) const { 4946 DefineStd(Builder, "MIPSEB", Opts); 4947 Builder.defineMacro("_MIPSEB"); 4948 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 4949 } 4950 }; 4951 4952 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 4953 virtual void SetDescriptionString(const std::string &Name) { 4954 // Change DescriptionString only if ABI is n32. 4955 if (Name == "n32") 4956 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4957 "i64:64:64-f32:32:32-f64:64:64-f128:128:128" 4958 "-v64:64:64-n32:64-S128"; 4959 } 4960 public: 4961 Mips64ELTargetInfo(const llvm::Triple &Triple) 4962 : Mips64TargetInfoBase(Triple) { 4963 // Default ABI is n64. 4964 BigEndian = false; 4965 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4966 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 4967 "v64:64:64-n32:64-S128"; 4968 } 4969 virtual void getTargetDefines(const LangOptions &Opts, 4970 MacroBuilder &Builder) const { 4971 DefineStd(Builder, "MIPSEL", Opts); 4972 Builder.defineMacro("_MIPSEL"); 4973 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 4974 } 4975 }; 4976 } // end anonymous namespace. 4977 4978 namespace { 4979 class PNaClTargetInfo : public TargetInfo { 4980 public: 4981 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4982 BigEndian = false; 4983 this->UserLabelPrefix = ""; 4984 this->LongAlign = 32; 4985 this->LongWidth = 32; 4986 this->PointerAlign = 32; 4987 this->PointerWidth = 32; 4988 this->IntMaxType = TargetInfo::SignedLongLong; 4989 this->UIntMaxType = TargetInfo::UnsignedLongLong; 4990 this->Int64Type = TargetInfo::SignedLongLong; 4991 this->DoubleAlign = 64; 4992 this->LongDoubleWidth = 64; 4993 this->LongDoubleAlign = 64; 4994 this->SizeType = TargetInfo::UnsignedInt; 4995 this->PtrDiffType = TargetInfo::SignedInt; 4996 this->IntPtrType = TargetInfo::SignedInt; 4997 this->RegParmMax = 0; // Disallow regparm 4998 DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 4999 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 5000 } 5001 5002 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 5003 } 5004 virtual void getArchDefines(const LangOptions &Opts, 5005 MacroBuilder &Builder) const { 5006 Builder.defineMacro("__le32__"); 5007 Builder.defineMacro("__pnacl__"); 5008 } 5009 virtual void getTargetDefines(const LangOptions &Opts, 5010 MacroBuilder &Builder) const { 5011 Builder.defineMacro("__LITTLE_ENDIAN__"); 5012 getArchDefines(Opts, Builder); 5013 } 5014 virtual bool hasFeature(StringRef Feature) const { 5015 return Feature == "pnacl"; 5016 } 5017 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5018 unsigned &NumRecords) const { 5019 } 5020 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5021 return TargetInfo::PNaClABIBuiltinVaList; 5022 } 5023 virtual void getGCCRegNames(const char * const *&Names, 5024 unsigned &NumNames) const; 5025 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5026 unsigned &NumAliases) const; 5027 virtual bool validateAsmConstraint(const char *&Name, 5028 TargetInfo::ConstraintInfo &Info) const { 5029 return false; 5030 } 5031 5032 virtual const char *getClobbers() const { 5033 return ""; 5034 } 5035 }; 5036 5037 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5038 unsigned &NumNames) const { 5039 Names = NULL; 5040 NumNames = 0; 5041 } 5042 5043 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5044 unsigned &NumAliases) const { 5045 Aliases = NULL; 5046 NumAliases = 0; 5047 } 5048 } // end anonymous namespace. 5049 5050 namespace { 5051 static const unsigned SPIRAddrSpaceMap[] = { 5052 1, // opencl_global 5053 3, // opencl_local 5054 2, // opencl_constant 5055 0, // cuda_device 5056 0, // cuda_constant 5057 0 // cuda_shared 5058 }; 5059 class SPIRTargetInfo : public TargetInfo { 5060 static const char * const GCCRegNames[]; 5061 static const Builtin::Info BuiltinInfo[]; 5062 std::vector<StringRef> AvailableFeatures; 5063 public: 5064 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5065 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5066 "SPIR target must use unknown OS"); 5067 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5068 "SPIR target must use unknown environment type"); 5069 BigEndian = false; 5070 TLSSupported = false; 5071 LongWidth = LongAlign = 64; 5072 AddrSpaceMap = &SPIRAddrSpaceMap; 5073 // Define available target features 5074 // These must be defined in sorted order! 5075 NoAsmVariants = true; 5076 } 5077 virtual void getTargetDefines(const LangOptions &Opts, 5078 MacroBuilder &Builder) const { 5079 DefineStd(Builder, "SPIR", Opts); 5080 } 5081 virtual bool hasFeature(StringRef Feature) const { 5082 return Feature == "spir"; 5083 } 5084 5085 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5086 unsigned &NumRecords) const {} 5087 virtual const char *getClobbers() const { 5088 return ""; 5089 } 5090 virtual void getGCCRegNames(const char * const *&Names, 5091 unsigned &NumNames) const {} 5092 virtual bool validateAsmConstraint(const char *&Name, 5093 TargetInfo::ConstraintInfo &info) const { 5094 return true; 5095 } 5096 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5097 unsigned &NumAliases) const {} 5098 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5099 return TargetInfo::VoidPtrBuiltinVaList; 5100 } 5101 }; 5102 5103 5104 class SPIR32TargetInfo : public SPIRTargetInfo { 5105 public: 5106 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5107 PointerWidth = PointerAlign = 32; 5108 SizeType = TargetInfo::UnsignedInt; 5109 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 5110 DescriptionString 5111 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5112 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-" 5113 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-" 5114 "v512:512:512-v1024:1024:1024"; 5115 } 5116 virtual void getTargetDefines(const LangOptions &Opts, 5117 MacroBuilder &Builder) const { 5118 DefineStd(Builder, "SPIR32", Opts); 5119 } 5120 }; 5121 5122 class SPIR64TargetInfo : public SPIRTargetInfo { 5123 public: 5124 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5125 PointerWidth = PointerAlign = 64; 5126 SizeType = TargetInfo::UnsignedLong; 5127 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 5128 DescriptionString 5129 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5130 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-" 5131 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-" 5132 "v512:512:512-v1024:1024:1024"; 5133 } 5134 virtual void getTargetDefines(const LangOptions &Opts, 5135 MacroBuilder &Builder) const { 5136 DefineStd(Builder, "SPIR64", Opts); 5137 } 5138 }; 5139 } 5140 5141 namespace { 5142 class XCoreTargetInfo : public TargetInfo { 5143 static const Builtin::Info BuiltinInfo[]; 5144 public: 5145 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5146 BigEndian = false; 5147 NoAsmVariants = true; 5148 LongLongAlign = 32; 5149 SuitableAlign = 32; 5150 DoubleAlign = LongDoubleAlign = 32; 5151 UseZeroLengthBitfieldAlignment = true; 5152 DescriptionString = "e-p:32:32:32-a0:0:32-n32" 5153 "-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32" 5154 "-f16:16:32-f32:32:32-f64:32:32"; 5155 } 5156 virtual void getTargetDefines(const LangOptions &Opts, 5157 MacroBuilder &Builder) const { 5158 Builder.defineMacro("__XS1B__"); 5159 } 5160 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5161 unsigned &NumRecords) const { 5162 Records = BuiltinInfo; 5163 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 5164 } 5165 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5166 return TargetInfo::VoidPtrBuiltinVaList; 5167 } 5168 virtual const char *getClobbers() const { 5169 return ""; 5170 } 5171 virtual void getGCCRegNames(const char * const *&Names, 5172 unsigned &NumNames) const { 5173 static const char * const GCCRegNames[] = { 5174 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5175 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 5176 }; 5177 Names = GCCRegNames; 5178 NumNames = llvm::array_lengthof(GCCRegNames); 5179 } 5180 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5181 unsigned &NumAliases) const { 5182 Aliases = NULL; 5183 NumAliases = 0; 5184 } 5185 virtual bool validateAsmConstraint(const char *&Name, 5186 TargetInfo::ConstraintInfo &Info) const { 5187 return false; 5188 } 5189 }; 5190 5191 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 5192 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5193 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5194 ALL_LANGUAGES }, 5195 #include "clang/Basic/BuiltinsXCore.def" 5196 }; 5197 } // end anonymous namespace. 5198 5199 5200 //===----------------------------------------------------------------------===// 5201 // Driver code 5202 //===----------------------------------------------------------------------===// 5203 5204 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 5205 llvm::Triple::OSType os = Triple.getOS(); 5206 5207 switch (Triple.getArch()) { 5208 default: 5209 return NULL; 5210 5211 case llvm::Triple::xcore: 5212 return new XCoreTargetInfo(Triple); 5213 5214 case llvm::Triple::hexagon: 5215 return new HexagonTargetInfo(Triple); 5216 5217 case llvm::Triple::aarch64: 5218 switch (os) { 5219 case llvm::Triple::Linux: 5220 return new LinuxTargetInfo<AArch64TargetInfo>(Triple); 5221 default: 5222 return new AArch64TargetInfo(Triple); 5223 } 5224 5225 case llvm::Triple::arm: 5226 case llvm::Triple::thumb: 5227 if (Triple.isOSDarwin()) 5228 return new DarwinARMTargetInfo(Triple); 5229 5230 switch (os) { 5231 case llvm::Triple::Linux: 5232 return new LinuxTargetInfo<ARMTargetInfo>(Triple); 5233 case llvm::Triple::FreeBSD: 5234 return new FreeBSDTargetInfo<ARMTargetInfo>(Triple); 5235 case llvm::Triple::NetBSD: 5236 return new NetBSDTargetInfo<ARMTargetInfo>(Triple); 5237 case llvm::Triple::OpenBSD: 5238 return new OpenBSDTargetInfo<ARMTargetInfo>(Triple); 5239 case llvm::Triple::Bitrig: 5240 return new BitrigTargetInfo<ARMTargetInfo>(Triple); 5241 case llvm::Triple::RTEMS: 5242 return new RTEMSTargetInfo<ARMTargetInfo>(Triple); 5243 case llvm::Triple::NaCl: 5244 return new NaClTargetInfo<ARMTargetInfo>(Triple); 5245 default: 5246 return new ARMTargetInfo(Triple); 5247 } 5248 5249 case llvm::Triple::msp430: 5250 return new MSP430TargetInfo(Triple); 5251 5252 case llvm::Triple::mips: 5253 switch (os) { 5254 case llvm::Triple::Linux: 5255 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 5256 case llvm::Triple::RTEMS: 5257 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 5258 case llvm::Triple::FreeBSD: 5259 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5260 case llvm::Triple::NetBSD: 5261 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5262 default: 5263 return new Mips32EBTargetInfo(Triple); 5264 } 5265 5266 case llvm::Triple::mipsel: 5267 switch (os) { 5268 case llvm::Triple::Linux: 5269 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 5270 case llvm::Triple::RTEMS: 5271 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 5272 case llvm::Triple::FreeBSD: 5273 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5274 case llvm::Triple::NetBSD: 5275 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5276 default: 5277 return new Mips32ELTargetInfo(Triple); 5278 } 5279 5280 case llvm::Triple::mips64: 5281 switch (os) { 5282 case llvm::Triple::Linux: 5283 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 5284 case llvm::Triple::RTEMS: 5285 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 5286 case llvm::Triple::FreeBSD: 5287 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5288 case llvm::Triple::NetBSD: 5289 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5290 case llvm::Triple::OpenBSD: 5291 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5292 default: 5293 return new Mips64EBTargetInfo(Triple); 5294 } 5295 5296 case llvm::Triple::mips64el: 5297 switch (os) { 5298 case llvm::Triple::Linux: 5299 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 5300 case llvm::Triple::RTEMS: 5301 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 5302 case llvm::Triple::FreeBSD: 5303 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5304 case llvm::Triple::NetBSD: 5305 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5306 case llvm::Triple::OpenBSD: 5307 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5308 default: 5309 return new Mips64ELTargetInfo(Triple); 5310 } 5311 5312 case llvm::Triple::le32: 5313 switch (os) { 5314 case llvm::Triple::NaCl: 5315 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 5316 default: 5317 return NULL; 5318 } 5319 5320 case llvm::Triple::ppc: 5321 if (Triple.isOSDarwin()) 5322 return new DarwinPPC32TargetInfo(Triple); 5323 switch (os) { 5324 case llvm::Triple::Linux: 5325 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 5326 case llvm::Triple::FreeBSD: 5327 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 5328 case llvm::Triple::NetBSD: 5329 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 5330 case llvm::Triple::OpenBSD: 5331 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 5332 case llvm::Triple::RTEMS: 5333 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 5334 default: 5335 return new PPC32TargetInfo(Triple); 5336 } 5337 5338 case llvm::Triple::ppc64: 5339 if (Triple.isOSDarwin()) 5340 return new DarwinPPC64TargetInfo(Triple); 5341 switch (os) { 5342 case llvm::Triple::Linux: 5343 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5344 case llvm::Triple::Lv2: 5345 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 5346 case llvm::Triple::FreeBSD: 5347 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 5348 case llvm::Triple::NetBSD: 5349 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 5350 default: 5351 return new PPC64TargetInfo(Triple); 5352 } 5353 5354 case llvm::Triple::ppc64le: 5355 switch (os) { 5356 case llvm::Triple::Linux: 5357 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5358 default: 5359 return new PPC64TargetInfo(Triple); 5360 } 5361 5362 case llvm::Triple::nvptx: 5363 return new NVPTX32TargetInfo(Triple); 5364 case llvm::Triple::nvptx64: 5365 return new NVPTX64TargetInfo(Triple); 5366 5367 case llvm::Triple::r600: 5368 return new R600TargetInfo(Triple); 5369 5370 case llvm::Triple::sparc: 5371 switch (os) { 5372 case llvm::Triple::Linux: 5373 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 5374 case llvm::Triple::AuroraUX: 5375 return new AuroraUXSparcV8TargetInfo(Triple); 5376 case llvm::Triple::Solaris: 5377 return new SolarisSparcV8TargetInfo(Triple); 5378 case llvm::Triple::NetBSD: 5379 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 5380 case llvm::Triple::OpenBSD: 5381 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 5382 case llvm::Triple::RTEMS: 5383 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 5384 default: 5385 return new SparcV8TargetInfo(Triple); 5386 } 5387 5388 case llvm::Triple::sparcv9: 5389 switch (os) { 5390 case llvm::Triple::Linux: 5391 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 5392 case llvm::Triple::AuroraUX: 5393 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 5394 case llvm::Triple::Solaris: 5395 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 5396 case llvm::Triple::NetBSD: 5397 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 5398 case llvm::Triple::OpenBSD: 5399 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 5400 case llvm::Triple::FreeBSD: 5401 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 5402 default: 5403 return new SparcV9TargetInfo(Triple); 5404 } 5405 5406 case llvm::Triple::systemz: 5407 switch (os) { 5408 case llvm::Triple::Linux: 5409 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 5410 default: 5411 return new SystemZTargetInfo(Triple); 5412 } 5413 5414 case llvm::Triple::tce: 5415 return new TCETargetInfo(Triple); 5416 5417 case llvm::Triple::x86: 5418 if (Triple.isOSDarwin()) 5419 return new DarwinI386TargetInfo(Triple); 5420 5421 switch (os) { 5422 case llvm::Triple::AuroraUX: 5423 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 5424 case llvm::Triple::Linux: 5425 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 5426 case llvm::Triple::DragonFly: 5427 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 5428 case llvm::Triple::NetBSD: 5429 return new NetBSDI386TargetInfo(Triple); 5430 case llvm::Triple::OpenBSD: 5431 return new OpenBSDI386TargetInfo(Triple); 5432 case llvm::Triple::Bitrig: 5433 return new BitrigI386TargetInfo(Triple); 5434 case llvm::Triple::FreeBSD: 5435 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5436 case llvm::Triple::Minix: 5437 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 5438 case llvm::Triple::Solaris: 5439 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 5440 case llvm::Triple::Cygwin: 5441 return new CygwinX86_32TargetInfo(Triple); 5442 case llvm::Triple::MinGW32: 5443 return new MinGWX86_32TargetInfo(Triple); 5444 case llvm::Triple::Win32: 5445 return new VisualStudioWindowsX86_32TargetInfo(Triple); 5446 case llvm::Triple::Haiku: 5447 return new HaikuX86_32TargetInfo(Triple); 5448 case llvm::Triple::RTEMS: 5449 return new RTEMSX86_32TargetInfo(Triple); 5450 case llvm::Triple::NaCl: 5451 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 5452 default: 5453 return new X86_32TargetInfo(Triple); 5454 } 5455 5456 case llvm::Triple::x86_64: 5457 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO) 5458 return new DarwinX86_64TargetInfo(Triple); 5459 5460 switch (os) { 5461 case llvm::Triple::AuroraUX: 5462 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 5463 case llvm::Triple::Linux: 5464 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 5465 case llvm::Triple::DragonFly: 5466 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 5467 case llvm::Triple::NetBSD: 5468 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 5469 case llvm::Triple::OpenBSD: 5470 return new OpenBSDX86_64TargetInfo(Triple); 5471 case llvm::Triple::Bitrig: 5472 return new BitrigX86_64TargetInfo(Triple); 5473 case llvm::Triple::FreeBSD: 5474 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5475 case llvm::Triple::Solaris: 5476 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 5477 case llvm::Triple::MinGW32: 5478 return new MinGWX86_64TargetInfo(Triple); 5479 case llvm::Triple::Win32: // This is what Triple.h supports now. 5480 return new VisualStudioWindowsX86_64TargetInfo(Triple); 5481 case llvm::Triple::NaCl: 5482 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 5483 default: 5484 return new X86_64TargetInfo(Triple); 5485 } 5486 5487 case llvm::Triple::spir: { 5488 if (Triple.getOS() != llvm::Triple::UnknownOS || 5489 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5490 return NULL; 5491 return new SPIR32TargetInfo(Triple); 5492 } 5493 case llvm::Triple::spir64: { 5494 if (Triple.getOS() != llvm::Triple::UnknownOS || 5495 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5496 return NULL; 5497 return new SPIR64TargetInfo(Triple); 5498 } 5499 } 5500 } 5501 5502 /// CreateTargetInfo - Return the target info object for the specified target 5503 /// triple. 5504 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 5505 TargetOptions *Opts) { 5506 llvm::Triple Triple(Opts->Triple); 5507 5508 // Construct the target 5509 OwningPtr<TargetInfo> Target(AllocateTarget(Triple)); 5510 if (!Target) { 5511 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 5512 return 0; 5513 } 5514 Target->setTargetOpts(Opts); 5515 5516 // Set the target CPU if specified. 5517 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 5518 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 5519 return 0; 5520 } 5521 5522 // Set the target ABI if specified. 5523 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 5524 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 5525 return 0; 5526 } 5527 5528 // Set the target C++ ABI. 5529 if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) { 5530 Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI; 5531 return 0; 5532 } 5533 5534 // Compute the default target features, we need the target to handle this 5535 // because features may have dependencies on one another. 5536 llvm::StringMap<bool> Features; 5537 Target->getDefaultFeatures(Features); 5538 5539 // Apply the user specified deltas. 5540 // First the enables. 5541 for (std::vector<std::string>::const_iterator 5542 it = Opts->FeaturesAsWritten.begin(), 5543 ie = Opts->FeaturesAsWritten.end(); 5544 it != ie; ++it) { 5545 const char *Name = it->c_str(); 5546 5547 if (Name[0] != '+') 5548 continue; 5549 5550 // Apply the feature via the target. 5551 if (!Target->setFeatureEnabled(Features, Name + 1, true)) { 5552 Diags.Report(diag::err_target_invalid_feature) << Name; 5553 return 0; 5554 } 5555 } 5556 5557 // Then the disables. 5558 for (std::vector<std::string>::const_iterator 5559 it = Opts->FeaturesAsWritten.begin(), 5560 ie = Opts->FeaturesAsWritten.end(); 5561 it != ie; ++it) { 5562 const char *Name = it->c_str(); 5563 5564 if (Name[0] == '+') 5565 continue; 5566 5567 // Apply the feature via the target. 5568 if (Name[0] != '-' || 5569 !Target->setFeatureEnabled(Features, Name + 1, false)) { 5570 Diags.Report(diag::err_target_invalid_feature) << Name; 5571 return 0; 5572 } 5573 } 5574 5575 // Add the features to the compile options. 5576 // 5577 // FIXME: If we are completely confident that we have the right set, we only 5578 // need to pass the minuses. 5579 Opts->Features.clear(); 5580 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 5581 ie = Features.end(); it != ie; ++it) 5582 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 5583 Target->HandleTargetFeatures(Opts->Features); 5584 5585 return Target.take(); 5586 } 5587