1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 } 469 if (Opts.POSIXThreads) 470 Builder.defineMacro("_REENTRANT"); 471 if (Opts.CPlusPlus) 472 Builder.defineMacro("_GNU_SOURCE"); 473 if (this->HasFloat128) 474 Builder.defineMacro("__FLOAT128__"); 475 } 476 public: 477 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 478 : OSTargetInfo<Target>(Triple, Opts) { 479 this->WIntType = TargetInfo::UnsignedInt; 480 481 switch (Triple.getArch()) { 482 default: 483 break; 484 case llvm::Triple::ppc: 485 case llvm::Triple::ppc64: 486 case llvm::Triple::ppc64le: 487 this->MCountName = "_mcount"; 488 break; 489 case llvm::Triple::x86: 490 case llvm::Triple::x86_64: 491 case llvm::Triple::systemz: 492 this->HasFloat128 = true; 493 break; 494 } 495 } 496 497 const char *getStaticInitSectionSpecifier() const override { 498 return ".text.startup"; 499 } 500 }; 501 502 // NetBSD Target 503 template<typename Target> 504 class NetBSDTargetInfo : public OSTargetInfo<Target> { 505 protected: 506 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 507 MacroBuilder &Builder) const override { 508 // NetBSD defines; list based off of gcc output 509 Builder.defineMacro("__NetBSD__"); 510 Builder.defineMacro("__unix__"); 511 Builder.defineMacro("__ELF__"); 512 if (Opts.POSIXThreads) 513 Builder.defineMacro("_POSIX_THREADS"); 514 515 switch (Triple.getArch()) { 516 default: 517 break; 518 case llvm::Triple::arm: 519 case llvm::Triple::armeb: 520 case llvm::Triple::thumb: 521 case llvm::Triple::thumbeb: 522 Builder.defineMacro("__ARM_DWARF_EH__"); 523 break; 524 } 525 } 526 public: 527 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 528 : OSTargetInfo<Target>(Triple, Opts) { 529 this->MCountName = "_mcount"; 530 } 531 }; 532 533 // OpenBSD Target 534 template<typename Target> 535 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 536 protected: 537 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 538 MacroBuilder &Builder) const override { 539 // OpenBSD defines; list based off of gcc output 540 541 Builder.defineMacro("__OpenBSD__"); 542 DefineStd(Builder, "unix", Opts); 543 Builder.defineMacro("__ELF__"); 544 if (Opts.POSIXThreads) 545 Builder.defineMacro("_REENTRANT"); 546 } 547 public: 548 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 549 : OSTargetInfo<Target>(Triple, Opts) { 550 this->TLSSupported = false; 551 552 switch (Triple.getArch()) { 553 default: 554 case llvm::Triple::x86: 555 case llvm::Triple::x86_64: 556 case llvm::Triple::arm: 557 case llvm::Triple::sparc: 558 this->MCountName = "__mcount"; 559 break; 560 case llvm::Triple::mips64: 561 case llvm::Triple::mips64el: 562 case llvm::Triple::ppc: 563 case llvm::Triple::sparcv9: 564 this->MCountName = "_mcount"; 565 break; 566 } 567 } 568 }; 569 570 // Bitrig Target 571 template<typename Target> 572 class BitrigTargetInfo : public OSTargetInfo<Target> { 573 protected: 574 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 575 MacroBuilder &Builder) const override { 576 // Bitrig defines; list based off of gcc output 577 578 Builder.defineMacro("__Bitrig__"); 579 DefineStd(Builder, "unix", Opts); 580 Builder.defineMacro("__ELF__"); 581 if (Opts.POSIXThreads) 582 Builder.defineMacro("_REENTRANT"); 583 584 switch (Triple.getArch()) { 585 default: 586 break; 587 case llvm::Triple::arm: 588 case llvm::Triple::armeb: 589 case llvm::Triple::thumb: 590 case llvm::Triple::thumbeb: 591 Builder.defineMacro("__ARM_DWARF_EH__"); 592 break; 593 } 594 } 595 public: 596 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 597 : OSTargetInfo<Target>(Triple, Opts) { 598 this->MCountName = "__mcount"; 599 } 600 }; 601 602 // PSP Target 603 template<typename Target> 604 class PSPTargetInfo : public OSTargetInfo<Target> { 605 protected: 606 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 607 MacroBuilder &Builder) const override { 608 // PSP defines; list based on the output of the pspdev gcc toolchain. 609 Builder.defineMacro("PSP"); 610 Builder.defineMacro("_PSP"); 611 Builder.defineMacro("__psp__"); 612 Builder.defineMacro("__ELF__"); 613 } 614 public: 615 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 616 }; 617 618 // PS3 PPU Target 619 template<typename Target> 620 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 621 protected: 622 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 623 MacroBuilder &Builder) const override { 624 // PS3 PPU defines. 625 Builder.defineMacro("__PPC__"); 626 Builder.defineMacro("__PPU__"); 627 Builder.defineMacro("__CELLOS_LV2__"); 628 Builder.defineMacro("__ELF__"); 629 Builder.defineMacro("__LP32__"); 630 Builder.defineMacro("_ARCH_PPC64"); 631 Builder.defineMacro("__powerpc64__"); 632 } 633 public: 634 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 635 : OSTargetInfo<Target>(Triple, Opts) { 636 this->LongWidth = this->LongAlign = 32; 637 this->PointerWidth = this->PointerAlign = 32; 638 this->IntMaxType = TargetInfo::SignedLongLong; 639 this->Int64Type = TargetInfo::SignedLongLong; 640 this->SizeType = TargetInfo::UnsignedInt; 641 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 642 } 643 }; 644 645 template <typename Target> 646 class PS4OSTargetInfo : public OSTargetInfo<Target> { 647 protected: 648 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 649 MacroBuilder &Builder) const override { 650 Builder.defineMacro("__FreeBSD__", "9"); 651 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 652 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 653 DefineStd(Builder, "unix", Opts); 654 Builder.defineMacro("__ELF__"); 655 Builder.defineMacro("__ORBIS__"); 656 } 657 public: 658 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 659 : OSTargetInfo<Target>(Triple, Opts) { 660 this->WCharType = this->UnsignedShort; 661 662 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 663 this->MaxTLSAlign = 256; 664 665 // On PS4, do not honor explicit bit field alignment, 666 // as in "__attribute__((aligned(2))) int b : 1;". 667 this->UseExplicitBitFieldAlignment = false; 668 669 switch (Triple.getArch()) { 670 default: 671 case llvm::Triple::x86_64: 672 this->MCountName = ".mcount"; 673 break; 674 } 675 } 676 }; 677 678 // Solaris target 679 template<typename Target> 680 class SolarisTargetInfo : public OSTargetInfo<Target> { 681 protected: 682 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 683 MacroBuilder &Builder) const override { 684 DefineStd(Builder, "sun", Opts); 685 DefineStd(Builder, "unix", Opts); 686 Builder.defineMacro("__ELF__"); 687 Builder.defineMacro("__svr4__"); 688 Builder.defineMacro("__SVR4"); 689 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 690 // newer, but to 500 for everything else. feature_test.h has a check to 691 // ensure that you are not using C99 with an old version of X/Open or C89 692 // with a new version. 693 if (Opts.C99) 694 Builder.defineMacro("_XOPEN_SOURCE", "600"); 695 else 696 Builder.defineMacro("_XOPEN_SOURCE", "500"); 697 if (Opts.CPlusPlus) 698 Builder.defineMacro("__C99FEATURES__"); 699 Builder.defineMacro("_LARGEFILE_SOURCE"); 700 Builder.defineMacro("_LARGEFILE64_SOURCE"); 701 Builder.defineMacro("__EXTENSIONS__"); 702 Builder.defineMacro("_REENTRANT"); 703 } 704 public: 705 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 706 : OSTargetInfo<Target>(Triple, Opts) { 707 this->WCharType = this->SignedInt; 708 // FIXME: WIntType should be SignedLong 709 } 710 }; 711 712 // Windows target 713 template<typename Target> 714 class WindowsTargetInfo : public OSTargetInfo<Target> { 715 protected: 716 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 717 MacroBuilder &Builder) const override { 718 Builder.defineMacro("_WIN32"); 719 } 720 void getVisualStudioDefines(const LangOptions &Opts, 721 MacroBuilder &Builder) const { 722 if (Opts.CPlusPlus) { 723 if (Opts.RTTIData) 724 Builder.defineMacro("_CPPRTTI"); 725 726 if (Opts.CXXExceptions) 727 Builder.defineMacro("_CPPUNWIND"); 728 } 729 730 if (Opts.Bool) 731 Builder.defineMacro("__BOOL_DEFINED"); 732 733 if (!Opts.CharIsSigned) 734 Builder.defineMacro("_CHAR_UNSIGNED"); 735 736 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 737 // but it works for now. 738 if (Opts.POSIXThreads) 739 Builder.defineMacro("_MT"); 740 741 if (Opts.MSCompatibilityVersion) { 742 Builder.defineMacro("_MSC_VER", 743 Twine(Opts.MSCompatibilityVersion / 100000)); 744 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 745 // FIXME We cannot encode the revision information into 32-bits 746 Builder.defineMacro("_MSC_BUILD", Twine(1)); 747 748 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 749 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 750 751 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 752 if (Opts.CPlusPlus1z) 753 Builder.defineMacro("_MSVC_LANG", "201403L"); 754 else if (Opts.CPlusPlus14) 755 Builder.defineMacro("_MSVC_LANG", "201402L"); 756 } 757 } 758 759 if (Opts.MicrosoftExt) { 760 Builder.defineMacro("_MSC_EXTENSIONS"); 761 762 if (Opts.CPlusPlus11) { 763 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 764 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 765 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 766 } 767 } 768 769 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 770 } 771 772 public: 773 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 774 : OSTargetInfo<Target>(Triple, Opts) {} 775 }; 776 777 template <typename Target> 778 class NaClTargetInfo : public OSTargetInfo<Target> { 779 protected: 780 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 781 MacroBuilder &Builder) const override { 782 if (Opts.POSIXThreads) 783 Builder.defineMacro("_REENTRANT"); 784 if (Opts.CPlusPlus) 785 Builder.defineMacro("_GNU_SOURCE"); 786 787 DefineStd(Builder, "unix", Opts); 788 Builder.defineMacro("__ELF__"); 789 Builder.defineMacro("__native_client__"); 790 } 791 792 public: 793 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 794 : OSTargetInfo<Target>(Triple, Opts) { 795 this->LongAlign = 32; 796 this->LongWidth = 32; 797 this->PointerAlign = 32; 798 this->PointerWidth = 32; 799 this->IntMaxType = TargetInfo::SignedLongLong; 800 this->Int64Type = TargetInfo::SignedLongLong; 801 this->DoubleAlign = 64; 802 this->LongDoubleWidth = 64; 803 this->LongDoubleAlign = 64; 804 this->LongLongWidth = 64; 805 this->LongLongAlign = 64; 806 this->SizeType = TargetInfo::UnsignedInt; 807 this->PtrDiffType = TargetInfo::SignedInt; 808 this->IntPtrType = TargetInfo::SignedInt; 809 // RegParmMax is inherited from the underlying architecture. 810 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 811 if (Triple.getArch() == llvm::Triple::arm) { 812 // Handled in ARM's setABI(). 813 } else if (Triple.getArch() == llvm::Triple::x86) { 814 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 815 } else if (Triple.getArch() == llvm::Triple::x86_64) { 816 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 817 } else if (Triple.getArch() == llvm::Triple::mipsel) { 818 // Handled on mips' setDataLayout. 819 } else { 820 assert(Triple.getArch() == llvm::Triple::le32); 821 this->resetDataLayout("e-p:32:32-i64:64"); 822 } 823 } 824 }; 825 826 // WebAssembly target 827 template <typename Target> 828 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 829 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 830 MacroBuilder &Builder) const final { 831 // A common platform macro. 832 if (Opts.POSIXThreads) 833 Builder.defineMacro("_REENTRANT"); 834 // Follow g++ convention and predefine _GNU_SOURCE for C++. 835 if (Opts.CPlusPlus) 836 Builder.defineMacro("_GNU_SOURCE"); 837 } 838 839 // As an optimization, group static init code together in a section. 840 const char *getStaticInitSectionSpecifier() const final { 841 return ".text.__startup"; 842 } 843 844 public: 845 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 846 const TargetOptions &Opts) 847 : OSTargetInfo<Target>(Triple, Opts) { 848 this->MCountName = "__mcount"; 849 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 850 } 851 }; 852 853 //===----------------------------------------------------------------------===// 854 // Specific target implementations. 855 //===----------------------------------------------------------------------===// 856 857 // PPC abstract base class 858 class PPCTargetInfo : public TargetInfo { 859 static const Builtin::Info BuiltinInfo[]; 860 static const char * const GCCRegNames[]; 861 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 862 std::string CPU; 863 864 // Target cpu features. 865 bool HasVSX; 866 bool HasP8Vector; 867 bool HasP8Crypto; 868 bool HasDirectMove; 869 bool HasQPX; 870 bool HasHTM; 871 bool HasBPERMD; 872 bool HasExtDiv; 873 874 protected: 875 std::string ABI; 876 877 public: 878 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 879 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 880 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 881 HasBPERMD(false), HasExtDiv(false) { 882 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 883 SimdDefaultAlign = 128; 884 LongDoubleWidth = LongDoubleAlign = 128; 885 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 886 } 887 888 /// \brief Flags for architecture specific defines. 889 typedef enum { 890 ArchDefineNone = 0, 891 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 892 ArchDefinePpcgr = 1 << 1, 893 ArchDefinePpcsq = 1 << 2, 894 ArchDefine440 = 1 << 3, 895 ArchDefine603 = 1 << 4, 896 ArchDefine604 = 1 << 5, 897 ArchDefinePwr4 = 1 << 6, 898 ArchDefinePwr5 = 1 << 7, 899 ArchDefinePwr5x = 1 << 8, 900 ArchDefinePwr6 = 1 << 9, 901 ArchDefinePwr6x = 1 << 10, 902 ArchDefinePwr7 = 1 << 11, 903 ArchDefinePwr8 = 1 << 12, 904 ArchDefinePwr9 = 1 << 13, 905 ArchDefineA2 = 1 << 14, 906 ArchDefineA2q = 1 << 15 907 } ArchDefineTypes; 908 909 // Note: GCC recognizes the following additional cpus: 910 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 911 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 912 // titan, rs64. 913 bool setCPU(const std::string &Name) override { 914 bool CPUKnown = llvm::StringSwitch<bool>(Name) 915 .Case("generic", true) 916 .Case("440", true) 917 .Case("450", true) 918 .Case("601", true) 919 .Case("602", true) 920 .Case("603", true) 921 .Case("603e", true) 922 .Case("603ev", true) 923 .Case("604", true) 924 .Case("604e", true) 925 .Case("620", true) 926 .Case("630", true) 927 .Case("g3", true) 928 .Case("7400", true) 929 .Case("g4", true) 930 .Case("7450", true) 931 .Case("g4+", true) 932 .Case("750", true) 933 .Case("970", true) 934 .Case("g5", true) 935 .Case("a2", true) 936 .Case("a2q", true) 937 .Case("e500mc", true) 938 .Case("e5500", true) 939 .Case("power3", true) 940 .Case("pwr3", true) 941 .Case("power4", true) 942 .Case("pwr4", true) 943 .Case("power5", true) 944 .Case("pwr5", true) 945 .Case("power5x", true) 946 .Case("pwr5x", true) 947 .Case("power6", true) 948 .Case("pwr6", true) 949 .Case("power6x", true) 950 .Case("pwr6x", true) 951 .Case("power7", true) 952 .Case("pwr7", true) 953 .Case("power8", true) 954 .Case("pwr8", true) 955 .Case("power9", true) 956 .Case("pwr9", true) 957 .Case("powerpc", true) 958 .Case("ppc", true) 959 .Case("powerpc64", true) 960 .Case("ppc64", true) 961 .Case("powerpc64le", true) 962 .Case("ppc64le", true) 963 .Default(false); 964 965 if (CPUKnown) 966 CPU = Name; 967 968 return CPUKnown; 969 } 970 971 972 StringRef getABI() const override { return ABI; } 973 974 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 975 return llvm::makeArrayRef(BuiltinInfo, 976 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 977 } 978 979 bool isCLZForZeroUndef() const override { return false; } 980 981 void getTargetDefines(const LangOptions &Opts, 982 MacroBuilder &Builder) const override; 983 984 bool 985 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 986 StringRef CPU, 987 const std::vector<std::string> &FeaturesVec) const override; 988 989 bool handleTargetFeatures(std::vector<std::string> &Features, 990 DiagnosticsEngine &Diags) override; 991 bool hasFeature(StringRef Feature) const override; 992 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 993 bool Enabled) const override; 994 995 ArrayRef<const char *> getGCCRegNames() const override; 996 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 997 bool validateAsmConstraint(const char *&Name, 998 TargetInfo::ConstraintInfo &Info) const override { 999 switch (*Name) { 1000 default: return false; 1001 case 'O': // Zero 1002 break; 1003 case 'b': // Base register 1004 case 'f': // Floating point register 1005 Info.setAllowsRegister(); 1006 break; 1007 // FIXME: The following are added to allow parsing. 1008 // I just took a guess at what the actions should be. 1009 // Also, is more specific checking needed? I.e. specific registers? 1010 case 'd': // Floating point register (containing 64-bit value) 1011 case 'v': // Altivec vector register 1012 Info.setAllowsRegister(); 1013 break; 1014 case 'w': 1015 switch (Name[1]) { 1016 case 'd':// VSX vector register to hold vector double data 1017 case 'f':// VSX vector register to hold vector float data 1018 case 's':// VSX vector register to hold scalar float data 1019 case 'a':// Any VSX register 1020 case 'c':// An individual CR bit 1021 break; 1022 default: 1023 return false; 1024 } 1025 Info.setAllowsRegister(); 1026 Name++; // Skip over 'w'. 1027 break; 1028 case 'h': // `MQ', `CTR', or `LINK' register 1029 case 'q': // `MQ' register 1030 case 'c': // `CTR' register 1031 case 'l': // `LINK' register 1032 case 'x': // `CR' register (condition register) number 0 1033 case 'y': // `CR' register (condition register) 1034 case 'z': // `XER[CA]' carry bit (part of the XER register) 1035 Info.setAllowsRegister(); 1036 break; 1037 case 'I': // Signed 16-bit constant 1038 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1039 // (use `L' instead for SImode constants) 1040 case 'K': // Unsigned 16-bit constant 1041 case 'L': // Signed 16-bit constant shifted left 16 bits 1042 case 'M': // Constant larger than 31 1043 case 'N': // Exact power of 2 1044 case 'P': // Constant whose negation is a signed 16-bit constant 1045 case 'G': // Floating point constant that can be loaded into a 1046 // register with one instruction per word 1047 case 'H': // Integer/Floating point constant that can be loaded 1048 // into a register using three instructions 1049 break; 1050 case 'm': // Memory operand. Note that on PowerPC targets, m can 1051 // include addresses that update the base register. It 1052 // is therefore only safe to use `m' in an asm statement 1053 // if that asm statement accesses the operand exactly once. 1054 // The asm statement must also use `%U<opno>' as a 1055 // placeholder for the "update" flag in the corresponding 1056 // load or store instruction. For example: 1057 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1058 // is correct but: 1059 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1060 // is not. Use es rather than m if you don't want the base 1061 // register to be updated. 1062 case 'e': 1063 if (Name[1] != 's') 1064 return false; 1065 // es: A "stable" memory operand; that is, one which does not 1066 // include any automodification of the base register. Unlike 1067 // `m', this constraint can be used in asm statements that 1068 // might access the operand several times, or that might not 1069 // access it at all. 1070 Info.setAllowsMemory(); 1071 Name++; // Skip over 'e'. 1072 break; 1073 case 'Q': // Memory operand that is an offset from a register (it is 1074 // usually better to use `m' or `es' in asm statements) 1075 case 'Z': // Memory operand that is an indexed or indirect from a 1076 // register (it is usually better to use `m' or `es' in 1077 // asm statements) 1078 Info.setAllowsMemory(); 1079 Info.setAllowsRegister(); 1080 break; 1081 case 'R': // AIX TOC entry 1082 case 'a': // Address operand that is an indexed or indirect from a 1083 // register (`p' is preferable for asm statements) 1084 case 'S': // Constant suitable as a 64-bit mask operand 1085 case 'T': // Constant suitable as a 32-bit mask operand 1086 case 'U': // System V Release 4 small data area reference 1087 case 't': // AND masks that can be performed by two rldic{l, r} 1088 // instructions 1089 case 'W': // Vector constant that does not require memory 1090 case 'j': // Vector constant that is all zeros. 1091 break; 1092 // End FIXME. 1093 } 1094 return true; 1095 } 1096 std::string convertConstraint(const char *&Constraint) const override { 1097 std::string R; 1098 switch (*Constraint) { 1099 case 'e': 1100 case 'w': 1101 // Two-character constraint; add "^" hint for later parsing. 1102 R = std::string("^") + std::string(Constraint, 2); 1103 Constraint++; 1104 break; 1105 default: 1106 return TargetInfo::convertConstraint(Constraint); 1107 } 1108 return R; 1109 } 1110 const char *getClobbers() const override { 1111 return ""; 1112 } 1113 int getEHDataRegisterNumber(unsigned RegNo) const override { 1114 if (RegNo == 0) return 3; 1115 if (RegNo == 1) return 4; 1116 return -1; 1117 } 1118 1119 bool hasSjLjLowering() const override { 1120 return true; 1121 } 1122 1123 bool useFloat128ManglingForLongDouble() const override { 1124 return LongDoubleWidth == 128 && 1125 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1126 getTriple().isOSBinFormatELF(); 1127 } 1128 }; 1129 1130 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1131 #define BUILTIN(ID, TYPE, ATTRS) \ 1132 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1133 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1134 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1135 #include "clang/Basic/BuiltinsPPC.def" 1136 }; 1137 1138 /// handleTargetFeatures - Perform initialization based on the user 1139 /// configured set of features. 1140 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1141 DiagnosticsEngine &Diags) { 1142 for (const auto &Feature : Features) { 1143 if (Feature == "+vsx") { 1144 HasVSX = true; 1145 } else if (Feature == "+bpermd") { 1146 HasBPERMD = true; 1147 } else if (Feature == "+extdiv") { 1148 HasExtDiv = true; 1149 } else if (Feature == "+power8-vector") { 1150 HasP8Vector = true; 1151 } else if (Feature == "+crypto") { 1152 HasP8Crypto = true; 1153 } else if (Feature == "+direct-move") { 1154 HasDirectMove = true; 1155 } else if (Feature == "+qpx") { 1156 HasQPX = true; 1157 } else if (Feature == "+htm") { 1158 HasHTM = true; 1159 } else if (Feature == "+float128") { 1160 HasFloat128 = true; 1161 } 1162 // TODO: Finish this list and add an assert that we've handled them 1163 // all. 1164 } 1165 1166 return true; 1167 } 1168 1169 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1170 /// #defines that are not tied to a specific subtarget. 1171 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1172 MacroBuilder &Builder) const { 1173 // Target identification. 1174 Builder.defineMacro("__ppc__"); 1175 Builder.defineMacro("__PPC__"); 1176 Builder.defineMacro("_ARCH_PPC"); 1177 Builder.defineMacro("__powerpc__"); 1178 Builder.defineMacro("__POWERPC__"); 1179 if (PointerWidth == 64) { 1180 Builder.defineMacro("_ARCH_PPC64"); 1181 Builder.defineMacro("__powerpc64__"); 1182 Builder.defineMacro("__ppc64__"); 1183 Builder.defineMacro("__PPC64__"); 1184 } 1185 1186 // Target properties. 1187 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1188 Builder.defineMacro("_LITTLE_ENDIAN"); 1189 } else { 1190 if (getTriple().getOS() != llvm::Triple::NetBSD && 1191 getTriple().getOS() != llvm::Triple::OpenBSD) 1192 Builder.defineMacro("_BIG_ENDIAN"); 1193 } 1194 1195 // ABI options. 1196 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1197 Builder.defineMacro("_CALL_ELF", "1"); 1198 if (ABI == "elfv2") 1199 Builder.defineMacro("_CALL_ELF", "2"); 1200 1201 // Subtarget options. 1202 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1203 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1204 1205 // FIXME: Should be controlled by command line option. 1206 if (LongDoubleWidth == 128) 1207 Builder.defineMacro("__LONG_DOUBLE_128__"); 1208 1209 if (Opts.AltiVec) { 1210 Builder.defineMacro("__VEC__", "10206"); 1211 Builder.defineMacro("__ALTIVEC__"); 1212 } 1213 1214 // CPU identification. 1215 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1216 .Case("440", ArchDefineName) 1217 .Case("450", ArchDefineName | ArchDefine440) 1218 .Case("601", ArchDefineName) 1219 .Case("602", ArchDefineName | ArchDefinePpcgr) 1220 .Case("603", ArchDefineName | ArchDefinePpcgr) 1221 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1222 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1223 .Case("604", ArchDefineName | ArchDefinePpcgr) 1224 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1225 .Case("620", ArchDefineName | ArchDefinePpcgr) 1226 .Case("630", ArchDefineName | ArchDefinePpcgr) 1227 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1228 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1229 .Case("750", ArchDefineName | ArchDefinePpcgr) 1230 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1231 | ArchDefinePpcsq) 1232 .Case("a2", ArchDefineA2) 1233 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1234 .Case("pwr3", ArchDefinePpcgr) 1235 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1236 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1237 | ArchDefinePpcsq) 1238 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1239 | ArchDefinePpcgr | ArchDefinePpcsq) 1240 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1241 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1242 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1243 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1244 | ArchDefinePpcsq) 1245 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1246 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1247 | ArchDefinePpcgr | ArchDefinePpcsq) 1248 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1249 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1250 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1251 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1252 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1253 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1254 | ArchDefinePpcsq) 1255 .Case("power3", ArchDefinePpcgr) 1256 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1257 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1258 | ArchDefinePpcsq) 1259 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1260 | ArchDefinePpcgr | ArchDefinePpcsq) 1261 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1262 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1263 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1264 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1265 | ArchDefinePpcsq) 1266 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1267 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1268 | ArchDefinePpcgr | ArchDefinePpcsq) 1269 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1270 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1271 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1272 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1273 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1274 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1275 | ArchDefinePpcsq) 1276 .Default(ArchDefineNone); 1277 1278 if (defs & ArchDefineName) 1279 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1280 if (defs & ArchDefinePpcgr) 1281 Builder.defineMacro("_ARCH_PPCGR"); 1282 if (defs & ArchDefinePpcsq) 1283 Builder.defineMacro("_ARCH_PPCSQ"); 1284 if (defs & ArchDefine440) 1285 Builder.defineMacro("_ARCH_440"); 1286 if (defs & ArchDefine603) 1287 Builder.defineMacro("_ARCH_603"); 1288 if (defs & ArchDefine604) 1289 Builder.defineMacro("_ARCH_604"); 1290 if (defs & ArchDefinePwr4) 1291 Builder.defineMacro("_ARCH_PWR4"); 1292 if (defs & ArchDefinePwr5) 1293 Builder.defineMacro("_ARCH_PWR5"); 1294 if (defs & ArchDefinePwr5x) 1295 Builder.defineMacro("_ARCH_PWR5X"); 1296 if (defs & ArchDefinePwr6) 1297 Builder.defineMacro("_ARCH_PWR6"); 1298 if (defs & ArchDefinePwr6x) 1299 Builder.defineMacro("_ARCH_PWR6X"); 1300 if (defs & ArchDefinePwr7) 1301 Builder.defineMacro("_ARCH_PWR7"); 1302 if (defs & ArchDefinePwr8) 1303 Builder.defineMacro("_ARCH_PWR8"); 1304 if (defs & ArchDefinePwr9) 1305 Builder.defineMacro("_ARCH_PWR9"); 1306 if (defs & ArchDefineA2) 1307 Builder.defineMacro("_ARCH_A2"); 1308 if (defs & ArchDefineA2q) { 1309 Builder.defineMacro("_ARCH_A2Q"); 1310 Builder.defineMacro("_ARCH_QP"); 1311 } 1312 1313 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1314 Builder.defineMacro("__bg__"); 1315 Builder.defineMacro("__THW_BLUEGENE__"); 1316 Builder.defineMacro("__bgq__"); 1317 Builder.defineMacro("__TOS_BGQ__"); 1318 } 1319 1320 if (HasVSX) 1321 Builder.defineMacro("__VSX__"); 1322 if (HasP8Vector) 1323 Builder.defineMacro("__POWER8_VECTOR__"); 1324 if (HasP8Crypto) 1325 Builder.defineMacro("__CRYPTO__"); 1326 if (HasHTM) 1327 Builder.defineMacro("__HTM__"); 1328 if (HasFloat128) 1329 Builder.defineMacro("__FLOAT128__"); 1330 1331 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1332 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1333 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1334 if (PointerWidth == 64) 1335 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1336 1337 // FIXME: The following are not yet generated here by Clang, but are 1338 // generated by GCC: 1339 // 1340 // _SOFT_FLOAT_ 1341 // __RECIP_PRECISION__ 1342 // __APPLE_ALTIVEC__ 1343 // __RECIP__ 1344 // __RECIPF__ 1345 // __RSQRTE__ 1346 // __RSQRTEF__ 1347 // _SOFT_DOUBLE_ 1348 // __NO_LWSYNC__ 1349 // __HAVE_BSWAP__ 1350 // __LONGDOUBLE128 1351 // __CMODEL_MEDIUM__ 1352 // __CMODEL_LARGE__ 1353 // _CALL_SYSV 1354 // _CALL_DARWIN 1355 // __NO_FPRS__ 1356 } 1357 1358 // Handle explicit options being passed to the compiler here: if we've 1359 // explicitly turned off vsx and turned on power8-vector or direct-move then 1360 // go ahead and error since the customer has expressed a somewhat incompatible 1361 // set of options. 1362 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1363 const std::vector<std::string> &FeaturesVec) { 1364 1365 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1366 FeaturesVec.end()) { 1367 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1368 FeaturesVec.end()) { 1369 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1370 << "-mno-vsx"; 1371 return false; 1372 } 1373 1374 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1375 FeaturesVec.end()) { 1376 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1377 << "-mno-vsx"; 1378 return false; 1379 } 1380 1381 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1382 FeaturesVec.end()) { 1383 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1384 << "-mno-vsx"; 1385 return false; 1386 } 1387 } 1388 1389 return true; 1390 } 1391 1392 bool PPCTargetInfo::initFeatureMap( 1393 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1394 const std::vector<std::string> &FeaturesVec) const { 1395 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1396 .Case("7400", true) 1397 .Case("g4", true) 1398 .Case("7450", true) 1399 .Case("g4+", true) 1400 .Case("970", true) 1401 .Case("g5", true) 1402 .Case("pwr6", true) 1403 .Case("pwr7", true) 1404 .Case("pwr8", true) 1405 .Case("pwr9", true) 1406 .Case("ppc64", true) 1407 .Case("ppc64le", true) 1408 .Default(false); 1409 1410 Features["qpx"] = (CPU == "a2q"); 1411 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1412 .Case("ppc64le", true) 1413 .Case("pwr9", true) 1414 .Case("pwr8", true) 1415 .Default(false); 1416 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1417 .Case("ppc64le", true) 1418 .Case("pwr9", true) 1419 .Case("pwr8", true) 1420 .Default(false); 1421 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1422 .Case("ppc64le", true) 1423 .Case("pwr9", true) 1424 .Case("pwr8", true) 1425 .Case("pwr7", true) 1426 .Default(false); 1427 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1428 .Case("ppc64le", true) 1429 .Case("pwr9", true) 1430 .Case("pwr8", true) 1431 .Case("pwr7", true) 1432 .Default(false); 1433 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1434 .Case("ppc64le", true) 1435 .Case("pwr9", true) 1436 .Case("pwr8", true) 1437 .Default(false); 1438 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1439 .Case("ppc64le", true) 1440 .Case("pwr9", true) 1441 .Case("pwr8", true) 1442 .Case("pwr7", true) 1443 .Default(false); 1444 1445 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1446 return false; 1447 1448 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1449 } 1450 1451 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1452 return llvm::StringSwitch<bool>(Feature) 1453 .Case("powerpc", true) 1454 .Case("vsx", HasVSX) 1455 .Case("power8-vector", HasP8Vector) 1456 .Case("crypto", HasP8Crypto) 1457 .Case("direct-move", HasDirectMove) 1458 .Case("qpx", HasQPX) 1459 .Case("htm", HasHTM) 1460 .Case("bpermd", HasBPERMD) 1461 .Case("extdiv", HasExtDiv) 1462 .Case("float128", HasFloat128) 1463 .Default(false); 1464 } 1465 1466 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1467 StringRef Name, bool Enabled) const { 1468 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1469 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1470 // incompatible options. 1471 if (Enabled) { 1472 if (Name == "direct-move") { 1473 Features[Name] = Features["vsx"] = true; 1474 } else if (Name == "power8-vector") { 1475 Features[Name] = Features["vsx"] = true; 1476 } else if (Name == "float128") { 1477 Features[Name] = Features["vsx"] = true; 1478 } else { 1479 Features[Name] = true; 1480 } 1481 } else { 1482 if (Name == "vsx") { 1483 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1484 Features["float128"] = false; 1485 } else { 1486 Features[Name] = false; 1487 } 1488 } 1489 } 1490 1491 const char * const PPCTargetInfo::GCCRegNames[] = { 1492 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1493 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1494 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1495 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1496 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1497 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1498 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1499 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1500 "mq", "lr", "ctr", "ap", 1501 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1502 "xer", 1503 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1504 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1505 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1506 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1507 "vrsave", "vscr", 1508 "spe_acc", "spefscr", 1509 "sfp" 1510 }; 1511 1512 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1513 return llvm::makeArrayRef(GCCRegNames); 1514 } 1515 1516 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1517 // While some of these aliases do map to different registers 1518 // they still share the same register name. 1519 { { "0" }, "r0" }, 1520 { { "1"}, "r1" }, 1521 { { "2" }, "r2" }, 1522 { { "3" }, "r3" }, 1523 { { "4" }, "r4" }, 1524 { { "5" }, "r5" }, 1525 { { "6" }, "r6" }, 1526 { { "7" }, "r7" }, 1527 { { "8" }, "r8" }, 1528 { { "9" }, "r9" }, 1529 { { "10" }, "r10" }, 1530 { { "11" }, "r11" }, 1531 { { "12" }, "r12" }, 1532 { { "13" }, "r13" }, 1533 { { "14" }, "r14" }, 1534 { { "15" }, "r15" }, 1535 { { "16" }, "r16" }, 1536 { { "17" }, "r17" }, 1537 { { "18" }, "r18" }, 1538 { { "19" }, "r19" }, 1539 { { "20" }, "r20" }, 1540 { { "21" }, "r21" }, 1541 { { "22" }, "r22" }, 1542 { { "23" }, "r23" }, 1543 { { "24" }, "r24" }, 1544 { { "25" }, "r25" }, 1545 { { "26" }, "r26" }, 1546 { { "27" }, "r27" }, 1547 { { "28" }, "r28" }, 1548 { { "29" }, "r29" }, 1549 { { "30" }, "r30" }, 1550 { { "31" }, "r31" }, 1551 { { "fr0" }, "f0" }, 1552 { { "fr1" }, "f1" }, 1553 { { "fr2" }, "f2" }, 1554 { { "fr3" }, "f3" }, 1555 { { "fr4" }, "f4" }, 1556 { { "fr5" }, "f5" }, 1557 { { "fr6" }, "f6" }, 1558 { { "fr7" }, "f7" }, 1559 { { "fr8" }, "f8" }, 1560 { { "fr9" }, "f9" }, 1561 { { "fr10" }, "f10" }, 1562 { { "fr11" }, "f11" }, 1563 { { "fr12" }, "f12" }, 1564 { { "fr13" }, "f13" }, 1565 { { "fr14" }, "f14" }, 1566 { { "fr15" }, "f15" }, 1567 { { "fr16" }, "f16" }, 1568 { { "fr17" }, "f17" }, 1569 { { "fr18" }, "f18" }, 1570 { { "fr19" }, "f19" }, 1571 { { "fr20" }, "f20" }, 1572 { { "fr21" }, "f21" }, 1573 { { "fr22" }, "f22" }, 1574 { { "fr23" }, "f23" }, 1575 { { "fr24" }, "f24" }, 1576 { { "fr25" }, "f25" }, 1577 { { "fr26" }, "f26" }, 1578 { { "fr27" }, "f27" }, 1579 { { "fr28" }, "f28" }, 1580 { { "fr29" }, "f29" }, 1581 { { "fr30" }, "f30" }, 1582 { { "fr31" }, "f31" }, 1583 { { "cc" }, "cr0" }, 1584 }; 1585 1586 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1587 return llvm::makeArrayRef(GCCRegAliases); 1588 } 1589 1590 class PPC32TargetInfo : public PPCTargetInfo { 1591 public: 1592 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1593 : PPCTargetInfo(Triple, Opts) { 1594 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1595 1596 switch (getTriple().getOS()) { 1597 case llvm::Triple::Linux: 1598 case llvm::Triple::FreeBSD: 1599 case llvm::Triple::NetBSD: 1600 SizeType = UnsignedInt; 1601 PtrDiffType = SignedInt; 1602 IntPtrType = SignedInt; 1603 break; 1604 default: 1605 break; 1606 } 1607 1608 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1609 LongDoubleWidth = LongDoubleAlign = 64; 1610 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1611 } 1612 1613 // PPC32 supports atomics up to 4 bytes. 1614 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1615 } 1616 1617 BuiltinVaListKind getBuiltinVaListKind() const override { 1618 // This is the ELF definition, and is overridden by the Darwin sub-target 1619 return TargetInfo::PowerABIBuiltinVaList; 1620 } 1621 }; 1622 1623 // Note: ABI differences may eventually require us to have a separate 1624 // TargetInfo for little endian. 1625 class PPC64TargetInfo : public PPCTargetInfo { 1626 public: 1627 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1628 : PPCTargetInfo(Triple, Opts) { 1629 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1630 IntMaxType = SignedLong; 1631 Int64Type = SignedLong; 1632 1633 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1634 resetDataLayout("e-m:e-i64:64-n32:64"); 1635 ABI = "elfv2"; 1636 } else { 1637 resetDataLayout("E-m:e-i64:64-n32:64"); 1638 ABI = "elfv1"; 1639 } 1640 1641 switch (getTriple().getOS()) { 1642 case llvm::Triple::FreeBSD: 1643 LongDoubleWidth = LongDoubleAlign = 64; 1644 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1645 break; 1646 case llvm::Triple::NetBSD: 1647 IntMaxType = SignedLongLong; 1648 Int64Type = SignedLongLong; 1649 break; 1650 default: 1651 break; 1652 } 1653 1654 // PPC64 supports atomics up to 8 bytes. 1655 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1656 } 1657 BuiltinVaListKind getBuiltinVaListKind() const override { 1658 return TargetInfo::CharPtrBuiltinVaList; 1659 } 1660 // PPC64 Linux-specific ABI options. 1661 bool setABI(const std::string &Name) override { 1662 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1663 ABI = Name; 1664 return true; 1665 } 1666 return false; 1667 } 1668 }; 1669 1670 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1671 public: 1672 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1673 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1674 HasAlignMac68kSupport = true; 1675 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1676 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1677 LongLongAlign = 32; 1678 SuitableAlign = 128; 1679 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1680 } 1681 BuiltinVaListKind getBuiltinVaListKind() const override { 1682 return TargetInfo::CharPtrBuiltinVaList; 1683 } 1684 }; 1685 1686 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1687 public: 1688 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1689 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1690 HasAlignMac68kSupport = true; 1691 SuitableAlign = 128; 1692 resetDataLayout("E-m:o-i64:64-n32:64"); 1693 } 1694 }; 1695 1696 static const unsigned NVPTXAddrSpaceMap[] = { 1697 1, // opencl_global 1698 3, // opencl_local 1699 4, // opencl_constant 1700 // FIXME: generic has to be added to the target 1701 0, // opencl_generic 1702 1, // cuda_device 1703 4, // cuda_constant 1704 3, // cuda_shared 1705 }; 1706 1707 class NVPTXTargetInfo : public TargetInfo { 1708 static const char *const GCCRegNames[]; 1709 static const Builtin::Info BuiltinInfo[]; 1710 CudaArch GPU; 1711 1712 public: 1713 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1714 : TargetInfo(Triple) { 1715 BigEndian = false; 1716 TLSSupported = false; 1717 LongWidth = LongAlign = 64; 1718 AddrSpaceMap = &NVPTXAddrSpaceMap; 1719 UseAddrSpaceMapMangling = true; 1720 // Define available target features 1721 // These must be defined in sorted order! 1722 NoAsmVariants = true; 1723 GPU = CudaArch::SM_20; 1724 1725 // If possible, get a TargetInfo for our host triple, so we can match its 1726 // types. 1727 llvm::Triple HostTriple(Opts.HostTriple); 1728 if (HostTriple.isNVPTX()) 1729 return; 1730 std::unique_ptr<TargetInfo> HostTarget( 1731 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1732 if (!HostTarget) { 1733 return; 1734 } 1735 1736 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1737 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1738 BoolWidth = HostTarget->getBoolWidth(); 1739 BoolAlign = HostTarget->getBoolAlign(); 1740 IntWidth = HostTarget->getIntWidth(); 1741 IntAlign = HostTarget->getIntAlign(); 1742 HalfWidth = HostTarget->getHalfWidth(); 1743 HalfAlign = HostTarget->getHalfAlign(); 1744 FloatWidth = HostTarget->getFloatWidth(); 1745 FloatAlign = HostTarget->getFloatAlign(); 1746 DoubleWidth = HostTarget->getDoubleWidth(); 1747 DoubleAlign = HostTarget->getDoubleAlign(); 1748 LongWidth = HostTarget->getLongWidth(); 1749 LongAlign = HostTarget->getLongAlign(); 1750 LongLongWidth = HostTarget->getLongLongWidth(); 1751 LongLongAlign = HostTarget->getLongLongAlign(); 1752 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1753 DefaultAlignForAttributeAligned = 1754 HostTarget->getDefaultAlignForAttributeAligned(); 1755 SizeType = HostTarget->getSizeType(); 1756 IntMaxType = HostTarget->getIntMaxType(); 1757 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1758 IntPtrType = HostTarget->getIntPtrType(); 1759 WCharType = HostTarget->getWCharType(); 1760 WIntType = HostTarget->getWIntType(); 1761 Char16Type = HostTarget->getChar16Type(); 1762 Char32Type = HostTarget->getChar32Type(); 1763 Int64Type = HostTarget->getInt64Type(); 1764 SigAtomicType = HostTarget->getSigAtomicType(); 1765 ProcessIDType = HostTarget->getProcessIDType(); 1766 1767 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1768 UseZeroLengthBitfieldAlignment = 1769 HostTarget->useZeroLengthBitfieldAlignment(); 1770 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1771 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1772 1773 // Properties intentionally not copied from host: 1774 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1775 // host/device boundary. 1776 // - SuitableAlign: Not visible across the host/device boundary, and may 1777 // correctly be different on host/device, e.g. if host has wider vector 1778 // types than device. 1779 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1780 // as its double type, but that's not necessarily true on the host. 1781 // TODO: nvcc emits a warning when using long double on device; we should 1782 // do the same. 1783 } 1784 void getTargetDefines(const LangOptions &Opts, 1785 MacroBuilder &Builder) const override { 1786 Builder.defineMacro("__PTX__"); 1787 Builder.defineMacro("__NVPTX__"); 1788 if (Opts.CUDAIsDevice) { 1789 // Set __CUDA_ARCH__ for the GPU specified. 1790 std::string CUDAArchCode = [this] { 1791 switch (GPU) { 1792 case CudaArch::UNKNOWN: 1793 assert(false && "No GPU arch when compiling CUDA device code."); 1794 return ""; 1795 case CudaArch::SM_20: 1796 return "200"; 1797 case CudaArch::SM_21: 1798 return "210"; 1799 case CudaArch::SM_30: 1800 return "300"; 1801 case CudaArch::SM_32: 1802 return "320"; 1803 case CudaArch::SM_35: 1804 return "350"; 1805 case CudaArch::SM_37: 1806 return "370"; 1807 case CudaArch::SM_50: 1808 return "500"; 1809 case CudaArch::SM_52: 1810 return "520"; 1811 case CudaArch::SM_53: 1812 return "530"; 1813 case CudaArch::SM_60: 1814 return "600"; 1815 case CudaArch::SM_61: 1816 return "610"; 1817 case CudaArch::SM_62: 1818 return "620"; 1819 } 1820 llvm_unreachable("unhandled CudaArch"); 1821 }(); 1822 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1823 } 1824 } 1825 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1826 return llvm::makeArrayRef(BuiltinInfo, 1827 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1828 } 1829 bool hasFeature(StringRef Feature) const override { 1830 return Feature == "ptx" || Feature == "nvptx"; 1831 } 1832 1833 ArrayRef<const char *> getGCCRegNames() const override; 1834 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1835 // No aliases. 1836 return None; 1837 } 1838 bool validateAsmConstraint(const char *&Name, 1839 TargetInfo::ConstraintInfo &Info) const override { 1840 switch (*Name) { 1841 default: 1842 return false; 1843 case 'c': 1844 case 'h': 1845 case 'r': 1846 case 'l': 1847 case 'f': 1848 case 'd': 1849 Info.setAllowsRegister(); 1850 return true; 1851 } 1852 } 1853 const char *getClobbers() const override { 1854 // FIXME: Is this really right? 1855 return ""; 1856 } 1857 BuiltinVaListKind getBuiltinVaListKind() const override { 1858 // FIXME: implement 1859 return TargetInfo::CharPtrBuiltinVaList; 1860 } 1861 bool setCPU(const std::string &Name) override { 1862 GPU = StringToCudaArch(Name); 1863 return GPU != CudaArch::UNKNOWN; 1864 } 1865 void setSupportedOpenCLOpts() override { 1866 auto &Opts = getSupportedOpenCLOpts(); 1867 Opts.cl_clang_storage_class_specifiers = 1; 1868 Opts.cl_khr_gl_sharing = 1; 1869 Opts.cl_khr_icd = 1; 1870 1871 Opts.cl_khr_fp64 = 1; 1872 Opts.cl_khr_byte_addressable_store = 1; 1873 Opts.cl_khr_global_int32_base_atomics = 1; 1874 Opts.cl_khr_global_int32_extended_atomics = 1; 1875 Opts.cl_khr_local_int32_base_atomics = 1; 1876 Opts.cl_khr_local_int32_extended_atomics = 1; 1877 } 1878 }; 1879 1880 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1881 #define BUILTIN(ID, TYPE, ATTRS) \ 1882 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1883 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1884 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1885 #include "clang/Basic/BuiltinsNVPTX.def" 1886 }; 1887 1888 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1889 1890 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1891 return llvm::makeArrayRef(GCCRegNames); 1892 } 1893 1894 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1895 public: 1896 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1897 : NVPTXTargetInfo(Triple, Opts) { 1898 LongWidth = LongAlign = 32; 1899 PointerWidth = PointerAlign = 32; 1900 SizeType = TargetInfo::UnsignedInt; 1901 PtrDiffType = TargetInfo::SignedInt; 1902 IntPtrType = TargetInfo::SignedInt; 1903 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1904 } 1905 }; 1906 1907 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1908 public: 1909 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1910 : NVPTXTargetInfo(Triple, Opts) { 1911 PointerWidth = PointerAlign = 64; 1912 SizeType = TargetInfo::UnsignedLong; 1913 PtrDiffType = TargetInfo::SignedLong; 1914 IntPtrType = TargetInfo::SignedLong; 1915 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1916 } 1917 }; 1918 1919 static const unsigned AMDGPUAddrSpaceMap[] = { 1920 1, // opencl_global 1921 3, // opencl_local 1922 2, // opencl_constant 1923 4, // opencl_generic 1924 1, // cuda_device 1925 2, // cuda_constant 1926 3 // cuda_shared 1927 }; 1928 1929 // If you edit the description strings, make sure you update 1930 // getPointerWidthV(). 1931 1932 static const char *const DataLayoutStringR600 = 1933 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1934 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1935 1936 static const char *const DataLayoutStringSI = 1937 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 1938 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1939 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1940 1941 class AMDGPUTargetInfo final : public TargetInfo { 1942 static const Builtin::Info BuiltinInfo[]; 1943 static const char * const GCCRegNames[]; 1944 1945 /// \brief The GPU profiles supported by the AMDGPU target. 1946 enum GPUKind { 1947 GK_NONE, 1948 GK_R600, 1949 GK_R600_DOUBLE_OPS, 1950 GK_R700, 1951 GK_R700_DOUBLE_OPS, 1952 GK_EVERGREEN, 1953 GK_EVERGREEN_DOUBLE_OPS, 1954 GK_NORTHERN_ISLANDS, 1955 GK_CAYMAN, 1956 GK_SOUTHERN_ISLANDS, 1957 GK_SEA_ISLANDS, 1958 GK_VOLCANIC_ISLANDS 1959 } GPU; 1960 1961 bool hasFP64:1; 1962 bool hasFMAF:1; 1963 bool hasLDEXPF:1; 1964 bool hasDenormSupport:1; 1965 1966 static bool isAMDGCN(const llvm::Triple &TT) { 1967 return TT.getArch() == llvm::Triple::amdgcn; 1968 } 1969 1970 public: 1971 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1972 : TargetInfo(Triple) , 1973 GPU(isAMDGCN(Triple) ? GK_SOUTHERN_ISLANDS : GK_R600), 1974 hasFP64(false), 1975 hasFMAF(false), 1976 hasLDEXPF(false), 1977 hasDenormSupport(false){ 1978 if (getTriple().getArch() == llvm::Triple::amdgcn) { 1979 hasFP64 = true; 1980 hasFMAF = true; 1981 hasLDEXPF = true; 1982 } 1983 if (Opts.CPU == "fiji") 1984 hasDenormSupport = true; 1985 1986 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 1987 DataLayoutStringSI : DataLayoutStringR600); 1988 1989 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1990 UseAddrSpaceMapMangling = true; 1991 } 1992 1993 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1994 if (GPU <= GK_CAYMAN) 1995 return 32; 1996 1997 switch(AddrSpace) { 1998 default: 1999 return 64; 2000 case 0: 2001 case 3: 2002 case 5: 2003 return 32; 2004 } 2005 } 2006 2007 const char * getClobbers() const override { 2008 return ""; 2009 } 2010 2011 ArrayRef<const char *> getGCCRegNames() const override; 2012 2013 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2014 return None; 2015 } 2016 2017 bool validateAsmConstraint(const char *&Name, 2018 TargetInfo::ConstraintInfo &Info) const override { 2019 switch (*Name) { 2020 default: break; 2021 case 'v': // vgpr 2022 case 's': // sgpr 2023 Info.setAllowsRegister(); 2024 return true; 2025 } 2026 return false; 2027 } 2028 2029 bool initFeatureMap(llvm::StringMap<bool> &Features, 2030 DiagnosticsEngine &Diags, StringRef CPU, 2031 const std::vector<std::string> &FeatureVec) const override; 2032 2033 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2034 TargetOptions &TargetOpts) const override { 2035 if (!hasDenormSupport) 2036 return; 2037 bool hasFP32Denormals = false; 2038 bool hasFP64Denormals = false; 2039 for (auto &I : TargetOpts.FeaturesAsWritten) { 2040 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2041 hasFP32Denormals = true; 2042 if (I == "+fp64-denormals" || I == "-fp64-denormals") 2043 hasFP64Denormals = true; 2044 } 2045 if (!hasFP32Denormals) 2046 TargetOpts.Features.push_back((Twine(CGOpts.FlushDenorm ? '-' : '+') + 2047 Twine("fp32-denormals")).str()); 2048 if (!hasFP64Denormals && hasFP64) 2049 TargetOpts.Features.push_back((Twine(CGOpts.FlushDenorm ? '-' : '+') + 2050 Twine("fp64-denormals")).str()); 2051 } 2052 2053 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2054 return llvm::makeArrayRef(BuiltinInfo, 2055 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2056 } 2057 2058 void getTargetDefines(const LangOptions &Opts, 2059 MacroBuilder &Builder) const override { 2060 if (getTriple().getArch() == llvm::Triple::amdgcn) 2061 Builder.defineMacro("__AMDGCN__"); 2062 else 2063 Builder.defineMacro("__R600__"); 2064 2065 if (hasFMAF) 2066 Builder.defineMacro("__HAS_FMAF__"); 2067 if (hasLDEXPF) 2068 Builder.defineMacro("__HAS_LDEXPF__"); 2069 if (hasFP64) 2070 Builder.defineMacro("__HAS_FP64__"); 2071 } 2072 2073 BuiltinVaListKind getBuiltinVaListKind() const override { 2074 return TargetInfo::CharPtrBuiltinVaList; 2075 } 2076 2077 static GPUKind parseR600Name(StringRef Name) { 2078 return llvm::StringSwitch<GPUKind>(Name) 2079 .Case("r600" , GK_R600) 2080 .Case("rv610", GK_R600) 2081 .Case("rv620", GK_R600) 2082 .Case("rv630", GK_R600) 2083 .Case("rv635", GK_R600) 2084 .Case("rs780", GK_R600) 2085 .Case("rs880", GK_R600) 2086 .Case("rv670", GK_R600_DOUBLE_OPS) 2087 .Case("rv710", GK_R700) 2088 .Case("rv730", GK_R700) 2089 .Case("rv740", GK_R700_DOUBLE_OPS) 2090 .Case("rv770", GK_R700_DOUBLE_OPS) 2091 .Case("palm", GK_EVERGREEN) 2092 .Case("cedar", GK_EVERGREEN) 2093 .Case("sumo", GK_EVERGREEN) 2094 .Case("sumo2", GK_EVERGREEN) 2095 .Case("redwood", GK_EVERGREEN) 2096 .Case("juniper", GK_EVERGREEN) 2097 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2098 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2099 .Case("barts", GK_NORTHERN_ISLANDS) 2100 .Case("turks", GK_NORTHERN_ISLANDS) 2101 .Case("caicos", GK_NORTHERN_ISLANDS) 2102 .Case("cayman", GK_CAYMAN) 2103 .Case("aruba", GK_CAYMAN) 2104 .Default(GK_NONE); 2105 } 2106 2107 static GPUKind parseAMDGCNName(StringRef Name) { 2108 return llvm::StringSwitch<GPUKind>(Name) 2109 .Case("tahiti", GK_SOUTHERN_ISLANDS) 2110 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 2111 .Case("verde", GK_SOUTHERN_ISLANDS) 2112 .Case("oland", GK_SOUTHERN_ISLANDS) 2113 .Case("hainan", GK_SOUTHERN_ISLANDS) 2114 .Case("bonaire", GK_SEA_ISLANDS) 2115 .Case("kabini", GK_SEA_ISLANDS) 2116 .Case("kaveri", GK_SEA_ISLANDS) 2117 .Case("hawaii", GK_SEA_ISLANDS) 2118 .Case("mullins", GK_SEA_ISLANDS) 2119 .Case("tonga", GK_VOLCANIC_ISLANDS) 2120 .Case("iceland", GK_VOLCANIC_ISLANDS) 2121 .Case("carrizo", GK_VOLCANIC_ISLANDS) 2122 .Case("fiji", GK_VOLCANIC_ISLANDS) 2123 .Case("stoney", GK_VOLCANIC_ISLANDS) 2124 .Default(GK_NONE); 2125 } 2126 2127 bool setCPU(const std::string &Name) override { 2128 if (getTriple().getArch() == llvm::Triple::amdgcn) 2129 GPU = parseAMDGCNName(Name); 2130 else 2131 GPU = parseR600Name(Name); 2132 2133 return GPU != GK_NONE; 2134 } 2135 2136 void setSupportedOpenCLOpts() override { 2137 auto &Opts = getSupportedOpenCLOpts(); 2138 Opts.cl_clang_storage_class_specifiers = 1; 2139 Opts.cl_khr_icd = 1; 2140 2141 if (hasFP64) 2142 Opts.cl_khr_fp64 = 1; 2143 if (GPU >= GK_EVERGREEN) { 2144 Opts.cl_khr_byte_addressable_store = 1; 2145 Opts.cl_khr_global_int32_base_atomics = 1; 2146 Opts.cl_khr_global_int32_extended_atomics = 1; 2147 Opts.cl_khr_local_int32_base_atomics = 1; 2148 Opts.cl_khr_local_int32_extended_atomics = 1; 2149 } 2150 if (GPU >= GK_SOUTHERN_ISLANDS) { 2151 Opts.cl_khr_fp16 = 1; 2152 Opts.cl_khr_int64_base_atomics = 1; 2153 Opts.cl_khr_int64_extended_atomics = 1; 2154 Opts.cl_khr_mipmap_image = 1; 2155 Opts.cl_khr_subgroups = 1; 2156 Opts.cl_khr_3d_image_writes = 1; 2157 Opts.cl_amd_media_ops = 1; 2158 Opts.cl_amd_media_ops2 = 1; 2159 } 2160 } 2161 2162 LangAS::ID getOpenCLImageAddrSpace() const override { 2163 return LangAS::opencl_constant; 2164 } 2165 2166 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2167 switch (CC) { 2168 default: 2169 return CCCR_Warning; 2170 case CC_C: 2171 case CC_OpenCLKernel: 2172 return CCCR_OK; 2173 } 2174 } 2175 }; 2176 2177 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2178 #define BUILTIN(ID, TYPE, ATTRS) \ 2179 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2180 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2181 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2182 #include "clang/Basic/BuiltinsAMDGPU.def" 2183 }; 2184 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2185 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2186 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2187 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2188 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2189 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2190 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2191 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2192 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2193 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2194 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2195 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2196 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2197 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2198 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2199 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2200 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2201 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2202 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2203 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2204 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2205 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2206 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2207 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2208 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2209 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2210 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2211 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2212 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2213 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2214 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2215 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2216 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2217 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2218 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2219 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2220 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2221 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2222 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2223 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2224 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2225 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2226 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2227 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2228 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2229 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2230 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2231 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2232 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2233 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2234 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2235 }; 2236 2237 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2238 return llvm::makeArrayRef(GCCRegNames); 2239 } 2240 2241 bool AMDGPUTargetInfo::initFeatureMap( 2242 llvm::StringMap<bool> &Features, 2243 DiagnosticsEngine &Diags, StringRef CPU, 2244 const std::vector<std::string> &FeatureVec) const { 2245 2246 // XXX - What does the member GPU mean if device name string passed here? 2247 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2248 if (CPU.empty()) 2249 CPU = "tahiti"; 2250 2251 switch (parseAMDGCNName(CPU)) { 2252 case GK_SOUTHERN_ISLANDS: 2253 case GK_SEA_ISLANDS: 2254 break; 2255 2256 case GK_VOLCANIC_ISLANDS: 2257 Features["s-memrealtime"] = true; 2258 Features["16-bit-insts"] = true; 2259 break; 2260 2261 case GK_NONE: 2262 return false; 2263 default: 2264 llvm_unreachable("unhandled subtarget"); 2265 } 2266 } else { 2267 if (CPU.empty()) 2268 CPU = "r600"; 2269 2270 switch (parseR600Name(CPU)) { 2271 case GK_R600: 2272 case GK_R700: 2273 case GK_EVERGREEN: 2274 case GK_NORTHERN_ISLANDS: 2275 break; 2276 case GK_R600_DOUBLE_OPS: 2277 case GK_R700_DOUBLE_OPS: 2278 case GK_EVERGREEN_DOUBLE_OPS: 2279 case GK_CAYMAN: 2280 Features["fp64"] = true; 2281 break; 2282 case GK_NONE: 2283 return false; 2284 default: 2285 llvm_unreachable("unhandled subtarget"); 2286 } 2287 } 2288 2289 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2290 } 2291 2292 // Namespace for x86 abstract base class 2293 const Builtin::Info BuiltinInfo[] = { 2294 #define BUILTIN(ID, TYPE, ATTRS) \ 2295 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2296 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2297 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2298 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2299 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2300 #include "clang/Basic/BuiltinsX86.def" 2301 }; 2302 2303 static const char* const GCCRegNames[] = { 2304 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2305 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2306 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2307 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2308 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2309 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2310 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2311 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2312 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2313 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2314 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2315 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2316 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2317 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2318 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2319 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2320 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2321 }; 2322 2323 const TargetInfo::AddlRegName AddlRegNames[] = { 2324 { { "al", "ah", "eax", "rax" }, 0 }, 2325 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2326 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2327 { { "dl", "dh", "edx", "rdx" }, 1 }, 2328 { { "esi", "rsi" }, 4 }, 2329 { { "edi", "rdi" }, 5 }, 2330 { { "esp", "rsp" }, 7 }, 2331 { { "ebp", "rbp" }, 6 }, 2332 { { "r8d", "r8w", "r8b" }, 38 }, 2333 { { "r9d", "r9w", "r9b" }, 39 }, 2334 { { "r10d", "r10w", "r10b" }, 40 }, 2335 { { "r11d", "r11w", "r11b" }, 41 }, 2336 { { "r12d", "r12w", "r12b" }, 42 }, 2337 { { "r13d", "r13w", "r13b" }, 43 }, 2338 { { "r14d", "r14w", "r14b" }, 44 }, 2339 { { "r15d", "r15w", "r15b" }, 45 }, 2340 }; 2341 2342 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2343 // most of the implementation can be shared. 2344 class X86TargetInfo : public TargetInfo { 2345 enum X86SSEEnum { 2346 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2347 } SSELevel = NoSSE; 2348 enum MMX3DNowEnum { 2349 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2350 } MMX3DNowLevel = NoMMX3DNow; 2351 enum XOPEnum { 2352 NoXOP, 2353 SSE4A, 2354 FMA4, 2355 XOP 2356 } XOPLevel = NoXOP; 2357 2358 bool HasAES = false; 2359 bool HasPCLMUL = false; 2360 bool HasLZCNT = false; 2361 bool HasRDRND = false; 2362 bool HasFSGSBASE = false; 2363 bool HasBMI = false; 2364 bool HasBMI2 = false; 2365 bool HasPOPCNT = false; 2366 bool HasRTM = false; 2367 bool HasPRFCHW = false; 2368 bool HasRDSEED = false; 2369 bool HasADX = false; 2370 bool HasTBM = false; 2371 bool HasFMA = false; 2372 bool HasF16C = false; 2373 bool HasAVX512CD = false; 2374 bool HasAVX512ER = false; 2375 bool HasAVX512PF = false; 2376 bool HasAVX512DQ = false; 2377 bool HasAVX512BW = false; 2378 bool HasAVX512VL = false; 2379 bool HasAVX512VBMI = false; 2380 bool HasAVX512IFMA = false; 2381 bool HasSHA = false; 2382 bool HasMPX = false; 2383 bool HasSGX = false; 2384 bool HasCX16 = false; 2385 bool HasFXSR = false; 2386 bool HasXSAVE = false; 2387 bool HasXSAVEOPT = false; 2388 bool HasXSAVEC = false; 2389 bool HasXSAVES = false; 2390 bool HasMWAITX = false; 2391 bool HasPKU = false; 2392 bool HasCLFLUSHOPT = false; 2393 bool HasPCOMMIT = false; 2394 bool HasCLWB = false; 2395 bool HasUMIP = false; 2396 bool HasMOVBE = false; 2397 bool HasPREFETCHWT1 = false; 2398 2399 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2400 /// 2401 /// Each enumeration represents a particular CPU supported by Clang. These 2402 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2403 enum CPUKind { 2404 CK_Generic, 2405 2406 /// \name i386 2407 /// i386-generation processors. 2408 //@{ 2409 CK_i386, 2410 //@} 2411 2412 /// \name i486 2413 /// i486-generation processors. 2414 //@{ 2415 CK_i486, 2416 CK_WinChipC6, 2417 CK_WinChip2, 2418 CK_C3, 2419 //@} 2420 2421 /// \name i586 2422 /// i586-generation processors, P5 microarchitecture based. 2423 //@{ 2424 CK_i586, 2425 CK_Pentium, 2426 CK_PentiumMMX, 2427 //@} 2428 2429 /// \name i686 2430 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2431 //@{ 2432 CK_i686, 2433 CK_PentiumPro, 2434 CK_Pentium2, 2435 CK_Pentium3, 2436 CK_Pentium3M, 2437 CK_PentiumM, 2438 CK_C3_2, 2439 2440 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2441 /// Clang however has some logic to suport this. 2442 // FIXME: Warn, deprecate, and potentially remove this. 2443 CK_Yonah, 2444 //@} 2445 2446 /// \name Netburst 2447 /// Netburst microarchitecture based processors. 2448 //@{ 2449 CK_Pentium4, 2450 CK_Pentium4M, 2451 CK_Prescott, 2452 CK_Nocona, 2453 //@} 2454 2455 /// \name Core 2456 /// Core microarchitecture based processors. 2457 //@{ 2458 CK_Core2, 2459 2460 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2461 /// codename which GCC no longer accepts as an option to -march, but Clang 2462 /// has some logic for recognizing it. 2463 // FIXME: Warn, deprecate, and potentially remove this. 2464 CK_Penryn, 2465 //@} 2466 2467 /// \name Atom 2468 /// Atom processors 2469 //@{ 2470 CK_Bonnell, 2471 CK_Silvermont, 2472 //@} 2473 2474 /// \name Nehalem 2475 /// Nehalem microarchitecture based processors. 2476 CK_Nehalem, 2477 2478 /// \name Westmere 2479 /// Westmere microarchitecture based processors. 2480 CK_Westmere, 2481 2482 /// \name Sandy Bridge 2483 /// Sandy Bridge microarchitecture based processors. 2484 CK_SandyBridge, 2485 2486 /// \name Ivy Bridge 2487 /// Ivy Bridge microarchitecture based processors. 2488 CK_IvyBridge, 2489 2490 /// \name Haswell 2491 /// Haswell microarchitecture based processors. 2492 CK_Haswell, 2493 2494 /// \name Broadwell 2495 /// Broadwell microarchitecture based processors. 2496 CK_Broadwell, 2497 2498 /// \name Skylake Client 2499 /// Skylake client microarchitecture based processors. 2500 CK_SkylakeClient, 2501 2502 /// \name Skylake Server 2503 /// Skylake server microarchitecture based processors. 2504 CK_SkylakeServer, 2505 2506 /// \name Cannonlake Client 2507 /// Cannonlake client microarchitecture based processors. 2508 CK_Cannonlake, 2509 2510 /// \name Knights Landing 2511 /// Knights Landing processor. 2512 CK_KNL, 2513 2514 /// \name Lakemont 2515 /// Lakemont microarchitecture based processors. 2516 CK_Lakemont, 2517 2518 /// \name K6 2519 /// K6 architecture processors. 2520 //@{ 2521 CK_K6, 2522 CK_K6_2, 2523 CK_K6_3, 2524 //@} 2525 2526 /// \name K7 2527 /// K7 architecture processors. 2528 //@{ 2529 CK_Athlon, 2530 CK_AthlonThunderbird, 2531 CK_Athlon4, 2532 CK_AthlonXP, 2533 CK_AthlonMP, 2534 //@} 2535 2536 /// \name K8 2537 /// K8 architecture processors. 2538 //@{ 2539 CK_Athlon64, 2540 CK_Athlon64SSE3, 2541 CK_AthlonFX, 2542 CK_K8, 2543 CK_K8SSE3, 2544 CK_Opteron, 2545 CK_OpteronSSE3, 2546 CK_AMDFAM10, 2547 //@} 2548 2549 /// \name Bobcat 2550 /// Bobcat architecture processors. 2551 //@{ 2552 CK_BTVER1, 2553 CK_BTVER2, 2554 //@} 2555 2556 /// \name Bulldozer 2557 /// Bulldozer architecture processors. 2558 //@{ 2559 CK_BDVER1, 2560 CK_BDVER2, 2561 CK_BDVER3, 2562 CK_BDVER4, 2563 //@} 2564 2565 /// This specification is deprecated and will be removed in the future. 2566 /// Users should prefer \see CK_K8. 2567 // FIXME: Warn on this when the CPU is set to it. 2568 //@{ 2569 CK_x86_64, 2570 //@} 2571 2572 /// \name Geode 2573 /// Geode processors. 2574 //@{ 2575 CK_Geode 2576 //@} 2577 } CPU = CK_Generic; 2578 2579 CPUKind getCPUKind(StringRef CPU) const { 2580 return llvm::StringSwitch<CPUKind>(CPU) 2581 .Case("i386", CK_i386) 2582 .Case("i486", CK_i486) 2583 .Case("winchip-c6", CK_WinChipC6) 2584 .Case("winchip2", CK_WinChip2) 2585 .Case("c3", CK_C3) 2586 .Case("i586", CK_i586) 2587 .Case("pentium", CK_Pentium) 2588 .Case("pentium-mmx", CK_PentiumMMX) 2589 .Case("i686", CK_i686) 2590 .Case("pentiumpro", CK_PentiumPro) 2591 .Case("pentium2", CK_Pentium2) 2592 .Case("pentium3", CK_Pentium3) 2593 .Case("pentium3m", CK_Pentium3M) 2594 .Case("pentium-m", CK_PentiumM) 2595 .Case("c3-2", CK_C3_2) 2596 .Case("yonah", CK_Yonah) 2597 .Case("pentium4", CK_Pentium4) 2598 .Case("pentium4m", CK_Pentium4M) 2599 .Case("prescott", CK_Prescott) 2600 .Case("nocona", CK_Nocona) 2601 .Case("core2", CK_Core2) 2602 .Case("penryn", CK_Penryn) 2603 .Case("bonnell", CK_Bonnell) 2604 .Case("atom", CK_Bonnell) // Legacy name. 2605 .Case("silvermont", CK_Silvermont) 2606 .Case("slm", CK_Silvermont) // Legacy name. 2607 .Case("nehalem", CK_Nehalem) 2608 .Case("corei7", CK_Nehalem) // Legacy name. 2609 .Case("westmere", CK_Westmere) 2610 .Case("sandybridge", CK_SandyBridge) 2611 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2612 .Case("ivybridge", CK_IvyBridge) 2613 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2614 .Case("haswell", CK_Haswell) 2615 .Case("core-avx2", CK_Haswell) // Legacy name. 2616 .Case("broadwell", CK_Broadwell) 2617 .Case("skylake", CK_SkylakeClient) 2618 .Case("skylake-avx512", CK_SkylakeServer) 2619 .Case("skx", CK_SkylakeServer) // Legacy name. 2620 .Case("cannonlake", CK_Cannonlake) 2621 .Case("knl", CK_KNL) 2622 .Case("lakemont", CK_Lakemont) 2623 .Case("k6", CK_K6) 2624 .Case("k6-2", CK_K6_2) 2625 .Case("k6-3", CK_K6_3) 2626 .Case("athlon", CK_Athlon) 2627 .Case("athlon-tbird", CK_AthlonThunderbird) 2628 .Case("athlon-4", CK_Athlon4) 2629 .Case("athlon-xp", CK_AthlonXP) 2630 .Case("athlon-mp", CK_AthlonMP) 2631 .Case("athlon64", CK_Athlon64) 2632 .Case("athlon64-sse3", CK_Athlon64SSE3) 2633 .Case("athlon-fx", CK_AthlonFX) 2634 .Case("k8", CK_K8) 2635 .Case("k8-sse3", CK_K8SSE3) 2636 .Case("opteron", CK_Opteron) 2637 .Case("opteron-sse3", CK_OpteronSSE3) 2638 .Case("barcelona", CK_AMDFAM10) 2639 .Case("amdfam10", CK_AMDFAM10) 2640 .Case("btver1", CK_BTVER1) 2641 .Case("btver2", CK_BTVER2) 2642 .Case("bdver1", CK_BDVER1) 2643 .Case("bdver2", CK_BDVER2) 2644 .Case("bdver3", CK_BDVER3) 2645 .Case("bdver4", CK_BDVER4) 2646 .Case("x86-64", CK_x86_64) 2647 .Case("geode", CK_Geode) 2648 .Default(CK_Generic); 2649 } 2650 2651 enum FPMathKind { 2652 FP_Default, 2653 FP_SSE, 2654 FP_387 2655 } FPMath = FP_Default; 2656 2657 public: 2658 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2659 : TargetInfo(Triple) { 2660 BigEndian = false; 2661 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2662 } 2663 unsigned getFloatEvalMethod() const override { 2664 // X87 evaluates with 80 bits "long double" precision. 2665 return SSELevel == NoSSE ? 2 : 0; 2666 } 2667 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2668 return llvm::makeArrayRef(BuiltinInfo, 2669 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2670 } 2671 ArrayRef<const char *> getGCCRegNames() const override { 2672 return llvm::makeArrayRef(GCCRegNames); 2673 } 2674 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2675 return None; 2676 } 2677 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2678 return llvm::makeArrayRef(AddlRegNames); 2679 } 2680 bool validateCpuSupports(StringRef Name) const override; 2681 bool validateAsmConstraint(const char *&Name, 2682 TargetInfo::ConstraintInfo &info) const override; 2683 2684 bool validateGlobalRegisterVariable(StringRef RegName, 2685 unsigned RegSize, 2686 bool &HasSizeMismatch) const override { 2687 // esp and ebp are the only 32-bit registers the x86 backend can currently 2688 // handle. 2689 if (RegName.equals("esp") || RegName.equals("ebp")) { 2690 // Check that the register size is 32-bit. 2691 HasSizeMismatch = RegSize != 32; 2692 return true; 2693 } 2694 2695 return false; 2696 } 2697 2698 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2699 2700 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2701 2702 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2703 2704 std::string convertConstraint(const char *&Constraint) const override; 2705 const char *getClobbers() const override { 2706 return "~{dirflag},~{fpsr},~{flags}"; 2707 } 2708 void getTargetDefines(const LangOptions &Opts, 2709 MacroBuilder &Builder) const override; 2710 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2711 bool Enabled); 2712 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2713 bool Enabled); 2714 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2715 bool Enabled); 2716 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2717 StringRef Name, bool Enabled) const override { 2718 setFeatureEnabledImpl(Features, Name, Enabled); 2719 } 2720 // This exists purely to cut down on the number of virtual calls in 2721 // initFeatureMap which calls this repeatedly. 2722 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2723 StringRef Name, bool Enabled); 2724 bool 2725 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2726 StringRef CPU, 2727 const std::vector<std::string> &FeaturesVec) const override; 2728 bool hasFeature(StringRef Feature) const override; 2729 bool handleTargetFeatures(std::vector<std::string> &Features, 2730 DiagnosticsEngine &Diags) override; 2731 StringRef getABI() const override { 2732 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2733 return "avx512"; 2734 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2735 return "avx"; 2736 if (getTriple().getArch() == llvm::Triple::x86 && 2737 MMX3DNowLevel == NoMMX3DNow) 2738 return "no-mmx"; 2739 return ""; 2740 } 2741 bool setCPU(const std::string &Name) override { 2742 CPU = getCPUKind(Name); 2743 2744 // Perform any per-CPU checks necessary to determine if this CPU is 2745 // acceptable. 2746 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2747 // invalid without explaining *why*. 2748 switch (CPU) { 2749 case CK_Generic: 2750 // No processor selected! 2751 return false; 2752 2753 case CK_i386: 2754 case CK_i486: 2755 case CK_WinChipC6: 2756 case CK_WinChip2: 2757 case CK_C3: 2758 case CK_i586: 2759 case CK_Pentium: 2760 case CK_PentiumMMX: 2761 case CK_i686: 2762 case CK_PentiumPro: 2763 case CK_Pentium2: 2764 case CK_Pentium3: 2765 case CK_Pentium3M: 2766 case CK_PentiumM: 2767 case CK_Yonah: 2768 case CK_C3_2: 2769 case CK_Pentium4: 2770 case CK_Pentium4M: 2771 case CK_Lakemont: 2772 case CK_Prescott: 2773 case CK_K6: 2774 case CK_K6_2: 2775 case CK_K6_3: 2776 case CK_Athlon: 2777 case CK_AthlonThunderbird: 2778 case CK_Athlon4: 2779 case CK_AthlonXP: 2780 case CK_AthlonMP: 2781 case CK_Geode: 2782 // Only accept certain architectures when compiling in 32-bit mode. 2783 if (getTriple().getArch() != llvm::Triple::x86) 2784 return false; 2785 2786 // Fallthrough 2787 case CK_Nocona: 2788 case CK_Core2: 2789 case CK_Penryn: 2790 case CK_Bonnell: 2791 case CK_Silvermont: 2792 case CK_Nehalem: 2793 case CK_Westmere: 2794 case CK_SandyBridge: 2795 case CK_IvyBridge: 2796 case CK_Haswell: 2797 case CK_Broadwell: 2798 case CK_SkylakeClient: 2799 case CK_SkylakeServer: 2800 case CK_Cannonlake: 2801 case CK_KNL: 2802 case CK_Athlon64: 2803 case CK_Athlon64SSE3: 2804 case CK_AthlonFX: 2805 case CK_K8: 2806 case CK_K8SSE3: 2807 case CK_Opteron: 2808 case CK_OpteronSSE3: 2809 case CK_AMDFAM10: 2810 case CK_BTVER1: 2811 case CK_BTVER2: 2812 case CK_BDVER1: 2813 case CK_BDVER2: 2814 case CK_BDVER3: 2815 case CK_BDVER4: 2816 case CK_x86_64: 2817 return true; 2818 } 2819 llvm_unreachable("Unhandled CPU kind"); 2820 } 2821 2822 bool setFPMath(StringRef Name) override; 2823 2824 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2825 // Most of the non-ARM calling conventions are i386 conventions. 2826 switch (CC) { 2827 case CC_X86ThisCall: 2828 case CC_X86FastCall: 2829 case CC_X86StdCall: 2830 case CC_X86VectorCall: 2831 case CC_C: 2832 case CC_Swift: 2833 case CC_X86Pascal: 2834 case CC_IntelOclBicc: 2835 return CCCR_OK; 2836 default: 2837 return CCCR_Warning; 2838 } 2839 } 2840 2841 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2842 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2843 } 2844 2845 bool hasSjLjLowering() const override { 2846 return true; 2847 } 2848 2849 void setSupportedOpenCLOpts() override { 2850 getSupportedOpenCLOpts().setAll(); 2851 } 2852 }; 2853 2854 bool X86TargetInfo::setFPMath(StringRef Name) { 2855 if (Name == "387") { 2856 FPMath = FP_387; 2857 return true; 2858 } 2859 if (Name == "sse") { 2860 FPMath = FP_SSE; 2861 return true; 2862 } 2863 return false; 2864 } 2865 2866 bool X86TargetInfo::initFeatureMap( 2867 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2868 const std::vector<std::string> &FeaturesVec) const { 2869 // FIXME: This *really* should not be here. 2870 // X86_64 always has SSE2. 2871 if (getTriple().getArch() == llvm::Triple::x86_64) 2872 setFeatureEnabledImpl(Features, "sse2", true); 2873 2874 const CPUKind Kind = getCPUKind(CPU); 2875 2876 // Enable X87 for all X86 processors but Lakemont. 2877 if (Kind != CK_Lakemont) 2878 setFeatureEnabledImpl(Features, "x87", true); 2879 2880 switch (Kind) { 2881 case CK_Generic: 2882 case CK_i386: 2883 case CK_i486: 2884 case CK_i586: 2885 case CK_Pentium: 2886 case CK_i686: 2887 case CK_PentiumPro: 2888 case CK_Lakemont: 2889 break; 2890 case CK_PentiumMMX: 2891 case CK_Pentium2: 2892 case CK_K6: 2893 case CK_WinChipC6: 2894 setFeatureEnabledImpl(Features, "mmx", true); 2895 break; 2896 case CK_Pentium3: 2897 case CK_Pentium3M: 2898 case CK_C3_2: 2899 setFeatureEnabledImpl(Features, "sse", true); 2900 setFeatureEnabledImpl(Features, "fxsr", true); 2901 break; 2902 case CK_PentiumM: 2903 case CK_Pentium4: 2904 case CK_Pentium4M: 2905 case CK_x86_64: 2906 setFeatureEnabledImpl(Features, "sse2", true); 2907 setFeatureEnabledImpl(Features, "fxsr", true); 2908 break; 2909 case CK_Yonah: 2910 case CK_Prescott: 2911 case CK_Nocona: 2912 setFeatureEnabledImpl(Features, "sse3", true); 2913 setFeatureEnabledImpl(Features, "fxsr", true); 2914 setFeatureEnabledImpl(Features, "cx16", true); 2915 break; 2916 case CK_Core2: 2917 case CK_Bonnell: 2918 setFeatureEnabledImpl(Features, "ssse3", true); 2919 setFeatureEnabledImpl(Features, "fxsr", true); 2920 setFeatureEnabledImpl(Features, "cx16", true); 2921 break; 2922 case CK_Penryn: 2923 setFeatureEnabledImpl(Features, "sse4.1", true); 2924 setFeatureEnabledImpl(Features, "fxsr", true); 2925 setFeatureEnabledImpl(Features, "cx16", true); 2926 break; 2927 case CK_Cannonlake: 2928 setFeatureEnabledImpl(Features, "avx512ifma", true); 2929 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2930 setFeatureEnabledImpl(Features, "sha", true); 2931 setFeatureEnabledImpl(Features, "umip", true); 2932 // FALLTHROUGH 2933 case CK_SkylakeServer: 2934 setFeatureEnabledImpl(Features, "avx512f", true); 2935 setFeatureEnabledImpl(Features, "avx512cd", true); 2936 setFeatureEnabledImpl(Features, "avx512dq", true); 2937 setFeatureEnabledImpl(Features, "avx512bw", true); 2938 setFeatureEnabledImpl(Features, "avx512vl", true); 2939 setFeatureEnabledImpl(Features, "pku", true); 2940 setFeatureEnabledImpl(Features, "pcommit", true); 2941 setFeatureEnabledImpl(Features, "clwb", true); 2942 // FALLTHROUGH 2943 case CK_SkylakeClient: 2944 setFeatureEnabledImpl(Features, "xsavec", true); 2945 setFeatureEnabledImpl(Features, "xsaves", true); 2946 setFeatureEnabledImpl(Features, "mpx", true); 2947 setFeatureEnabledImpl(Features, "sgx", true); 2948 setFeatureEnabledImpl(Features, "clflushopt", true); 2949 // FALLTHROUGH 2950 case CK_Broadwell: 2951 setFeatureEnabledImpl(Features, "rdseed", true); 2952 setFeatureEnabledImpl(Features, "adx", true); 2953 // FALLTHROUGH 2954 case CK_Haswell: 2955 setFeatureEnabledImpl(Features, "avx2", true); 2956 setFeatureEnabledImpl(Features, "lzcnt", true); 2957 setFeatureEnabledImpl(Features, "bmi", true); 2958 setFeatureEnabledImpl(Features, "bmi2", true); 2959 setFeatureEnabledImpl(Features, "rtm", true); 2960 setFeatureEnabledImpl(Features, "fma", true); 2961 setFeatureEnabledImpl(Features, "movbe", true); 2962 // FALLTHROUGH 2963 case CK_IvyBridge: 2964 setFeatureEnabledImpl(Features, "rdrnd", true); 2965 setFeatureEnabledImpl(Features, "f16c", true); 2966 setFeatureEnabledImpl(Features, "fsgsbase", true); 2967 // FALLTHROUGH 2968 case CK_SandyBridge: 2969 setFeatureEnabledImpl(Features, "avx", true); 2970 setFeatureEnabledImpl(Features, "xsave", true); 2971 setFeatureEnabledImpl(Features, "xsaveopt", true); 2972 // FALLTHROUGH 2973 case CK_Westmere: 2974 case CK_Silvermont: 2975 setFeatureEnabledImpl(Features, "aes", true); 2976 setFeatureEnabledImpl(Features, "pclmul", true); 2977 // FALLTHROUGH 2978 case CK_Nehalem: 2979 setFeatureEnabledImpl(Features, "sse4.2", true); 2980 setFeatureEnabledImpl(Features, "fxsr", true); 2981 setFeatureEnabledImpl(Features, "cx16", true); 2982 break; 2983 case CK_KNL: 2984 setFeatureEnabledImpl(Features, "avx512f", true); 2985 setFeatureEnabledImpl(Features, "avx512cd", true); 2986 setFeatureEnabledImpl(Features, "avx512er", true); 2987 setFeatureEnabledImpl(Features, "avx512pf", true); 2988 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2989 setFeatureEnabledImpl(Features, "fxsr", true); 2990 setFeatureEnabledImpl(Features, "rdseed", true); 2991 setFeatureEnabledImpl(Features, "adx", true); 2992 setFeatureEnabledImpl(Features, "lzcnt", true); 2993 setFeatureEnabledImpl(Features, "bmi", true); 2994 setFeatureEnabledImpl(Features, "bmi2", true); 2995 setFeatureEnabledImpl(Features, "rtm", true); 2996 setFeatureEnabledImpl(Features, "fma", true); 2997 setFeatureEnabledImpl(Features, "rdrnd", true); 2998 setFeatureEnabledImpl(Features, "f16c", true); 2999 setFeatureEnabledImpl(Features, "fsgsbase", true); 3000 setFeatureEnabledImpl(Features, "aes", true); 3001 setFeatureEnabledImpl(Features, "pclmul", true); 3002 setFeatureEnabledImpl(Features, "cx16", true); 3003 setFeatureEnabledImpl(Features, "xsaveopt", true); 3004 setFeatureEnabledImpl(Features, "xsave", true); 3005 setFeatureEnabledImpl(Features, "movbe", true); 3006 break; 3007 case CK_K6_2: 3008 case CK_K6_3: 3009 case CK_WinChip2: 3010 case CK_C3: 3011 setFeatureEnabledImpl(Features, "3dnow", true); 3012 break; 3013 case CK_Athlon: 3014 case CK_AthlonThunderbird: 3015 case CK_Geode: 3016 setFeatureEnabledImpl(Features, "3dnowa", true); 3017 break; 3018 case CK_Athlon4: 3019 case CK_AthlonXP: 3020 case CK_AthlonMP: 3021 setFeatureEnabledImpl(Features, "sse", true); 3022 setFeatureEnabledImpl(Features, "3dnowa", true); 3023 setFeatureEnabledImpl(Features, "fxsr", true); 3024 break; 3025 case CK_K8: 3026 case CK_Opteron: 3027 case CK_Athlon64: 3028 case CK_AthlonFX: 3029 setFeatureEnabledImpl(Features, "sse2", true); 3030 setFeatureEnabledImpl(Features, "3dnowa", true); 3031 setFeatureEnabledImpl(Features, "fxsr", true); 3032 break; 3033 case CK_AMDFAM10: 3034 setFeatureEnabledImpl(Features, "sse4a", true); 3035 setFeatureEnabledImpl(Features, "lzcnt", true); 3036 setFeatureEnabledImpl(Features, "popcnt", true); 3037 // FALLTHROUGH 3038 case CK_K8SSE3: 3039 case CK_OpteronSSE3: 3040 case CK_Athlon64SSE3: 3041 setFeatureEnabledImpl(Features, "sse3", true); 3042 setFeatureEnabledImpl(Features, "3dnowa", true); 3043 setFeatureEnabledImpl(Features, "fxsr", true); 3044 break; 3045 case CK_BTVER2: 3046 setFeatureEnabledImpl(Features, "avx", true); 3047 setFeatureEnabledImpl(Features, "aes", true); 3048 setFeatureEnabledImpl(Features, "pclmul", true); 3049 setFeatureEnabledImpl(Features, "bmi", true); 3050 setFeatureEnabledImpl(Features, "f16c", true); 3051 setFeatureEnabledImpl(Features, "xsaveopt", true); 3052 // FALLTHROUGH 3053 case CK_BTVER1: 3054 setFeatureEnabledImpl(Features, "ssse3", true); 3055 setFeatureEnabledImpl(Features, "sse4a", true); 3056 setFeatureEnabledImpl(Features, "lzcnt", true); 3057 setFeatureEnabledImpl(Features, "popcnt", true); 3058 setFeatureEnabledImpl(Features, "prfchw", true); 3059 setFeatureEnabledImpl(Features, "cx16", true); 3060 setFeatureEnabledImpl(Features, "fxsr", true); 3061 break; 3062 case CK_BDVER4: 3063 setFeatureEnabledImpl(Features, "avx2", true); 3064 setFeatureEnabledImpl(Features, "bmi2", true); 3065 setFeatureEnabledImpl(Features, "mwaitx", true); 3066 // FALLTHROUGH 3067 case CK_BDVER3: 3068 setFeatureEnabledImpl(Features, "fsgsbase", true); 3069 setFeatureEnabledImpl(Features, "xsaveopt", true); 3070 // FALLTHROUGH 3071 case CK_BDVER2: 3072 setFeatureEnabledImpl(Features, "bmi", true); 3073 setFeatureEnabledImpl(Features, "fma", true); 3074 setFeatureEnabledImpl(Features, "f16c", true); 3075 setFeatureEnabledImpl(Features, "tbm", true); 3076 // FALLTHROUGH 3077 case CK_BDVER1: 3078 // xop implies avx, sse4a and fma4. 3079 setFeatureEnabledImpl(Features, "xop", true); 3080 setFeatureEnabledImpl(Features, "lzcnt", true); 3081 setFeatureEnabledImpl(Features, "aes", true); 3082 setFeatureEnabledImpl(Features, "pclmul", true); 3083 setFeatureEnabledImpl(Features, "prfchw", true); 3084 setFeatureEnabledImpl(Features, "cx16", true); 3085 setFeatureEnabledImpl(Features, "fxsr", true); 3086 setFeatureEnabledImpl(Features, "xsave", true); 3087 break; 3088 } 3089 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3090 return false; 3091 3092 // Can't do this earlier because we need to be able to explicitly enable 3093 // or disable these features and the things that they depend upon. 3094 3095 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3096 auto I = Features.find("sse4.2"); 3097 if (I != Features.end() && I->getValue() && 3098 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3099 FeaturesVec.end()) 3100 Features["popcnt"] = true; 3101 3102 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3103 I = Features.find("3dnow"); 3104 if (I != Features.end() && I->getValue() && 3105 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3106 FeaturesVec.end()) 3107 Features["prfchw"] = true; 3108 3109 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3110 // then enable MMX. 3111 I = Features.find("sse"); 3112 if (I != Features.end() && I->getValue() && 3113 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3114 FeaturesVec.end()) 3115 Features["mmx"] = true; 3116 3117 return true; 3118 } 3119 3120 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3121 X86SSEEnum Level, bool Enabled) { 3122 if (Enabled) { 3123 switch (Level) { 3124 case AVX512F: 3125 Features["avx512f"] = true; 3126 case AVX2: 3127 Features["avx2"] = true; 3128 case AVX: 3129 Features["avx"] = true; 3130 Features["xsave"] = true; 3131 case SSE42: 3132 Features["sse4.2"] = true; 3133 case SSE41: 3134 Features["sse4.1"] = true; 3135 case SSSE3: 3136 Features["ssse3"] = true; 3137 case SSE3: 3138 Features["sse3"] = true; 3139 case SSE2: 3140 Features["sse2"] = true; 3141 case SSE1: 3142 Features["sse"] = true; 3143 case NoSSE: 3144 break; 3145 } 3146 return; 3147 } 3148 3149 switch (Level) { 3150 case NoSSE: 3151 case SSE1: 3152 Features["sse"] = false; 3153 case SSE2: 3154 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3155 Features["sha"] = false; 3156 case SSE3: 3157 Features["sse3"] = false; 3158 setXOPLevel(Features, NoXOP, false); 3159 case SSSE3: 3160 Features["ssse3"] = false; 3161 case SSE41: 3162 Features["sse4.1"] = false; 3163 case SSE42: 3164 Features["sse4.2"] = false; 3165 case AVX: 3166 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3167 Features["xsaveopt"] = false; 3168 setXOPLevel(Features, FMA4, false); 3169 case AVX2: 3170 Features["avx2"] = false; 3171 case AVX512F: 3172 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3173 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3174 Features["avx512vl"] = Features["avx512vbmi"] = 3175 Features["avx512ifma"] = false; 3176 } 3177 } 3178 3179 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3180 MMX3DNowEnum Level, bool Enabled) { 3181 if (Enabled) { 3182 switch (Level) { 3183 case AMD3DNowAthlon: 3184 Features["3dnowa"] = true; 3185 case AMD3DNow: 3186 Features["3dnow"] = true; 3187 case MMX: 3188 Features["mmx"] = true; 3189 case NoMMX3DNow: 3190 break; 3191 } 3192 return; 3193 } 3194 3195 switch (Level) { 3196 case NoMMX3DNow: 3197 case MMX: 3198 Features["mmx"] = false; 3199 case AMD3DNow: 3200 Features["3dnow"] = false; 3201 case AMD3DNowAthlon: 3202 Features["3dnowa"] = false; 3203 } 3204 } 3205 3206 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3207 bool Enabled) { 3208 if (Enabled) { 3209 switch (Level) { 3210 case XOP: 3211 Features["xop"] = true; 3212 case FMA4: 3213 Features["fma4"] = true; 3214 setSSELevel(Features, AVX, true); 3215 case SSE4A: 3216 Features["sse4a"] = true; 3217 setSSELevel(Features, SSE3, true); 3218 case NoXOP: 3219 break; 3220 } 3221 return; 3222 } 3223 3224 switch (Level) { 3225 case NoXOP: 3226 case SSE4A: 3227 Features["sse4a"] = false; 3228 case FMA4: 3229 Features["fma4"] = false; 3230 case XOP: 3231 Features["xop"] = false; 3232 } 3233 } 3234 3235 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3236 StringRef Name, bool Enabled) { 3237 // This is a bit of a hack to deal with the sse4 target feature when used 3238 // as part of the target attribute. We handle sse4 correctly everywhere 3239 // else. See below for more information on how we handle the sse4 options. 3240 if (Name != "sse4") 3241 Features[Name] = Enabled; 3242 3243 if (Name == "mmx") { 3244 setMMXLevel(Features, MMX, Enabled); 3245 } else if (Name == "sse") { 3246 setSSELevel(Features, SSE1, Enabled); 3247 } else if (Name == "sse2") { 3248 setSSELevel(Features, SSE2, Enabled); 3249 } else if (Name == "sse3") { 3250 setSSELevel(Features, SSE3, Enabled); 3251 } else if (Name == "ssse3") { 3252 setSSELevel(Features, SSSE3, Enabled); 3253 } else if (Name == "sse4.2") { 3254 setSSELevel(Features, SSE42, Enabled); 3255 } else if (Name == "sse4.1") { 3256 setSSELevel(Features, SSE41, Enabled); 3257 } else if (Name == "3dnow") { 3258 setMMXLevel(Features, AMD3DNow, Enabled); 3259 } else if (Name == "3dnowa") { 3260 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3261 } else if (Name == "aes") { 3262 if (Enabled) 3263 setSSELevel(Features, SSE2, Enabled); 3264 } else if (Name == "pclmul") { 3265 if (Enabled) 3266 setSSELevel(Features, SSE2, Enabled); 3267 } else if (Name == "avx") { 3268 setSSELevel(Features, AVX, Enabled); 3269 } else if (Name == "avx2") { 3270 setSSELevel(Features, AVX2, Enabled); 3271 } else if (Name == "avx512f") { 3272 setSSELevel(Features, AVX512F, Enabled); 3273 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3274 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3275 Name == "avx512vbmi" || Name == "avx512ifma") { 3276 if (Enabled) 3277 setSSELevel(Features, AVX512F, Enabled); 3278 } else if (Name == "fma") { 3279 if (Enabled) 3280 setSSELevel(Features, AVX, Enabled); 3281 } else if (Name == "fma4") { 3282 setXOPLevel(Features, FMA4, Enabled); 3283 } else if (Name == "xop") { 3284 setXOPLevel(Features, XOP, Enabled); 3285 } else if (Name == "sse4a") { 3286 setXOPLevel(Features, SSE4A, Enabled); 3287 } else if (Name == "f16c") { 3288 if (Enabled) 3289 setSSELevel(Features, AVX, Enabled); 3290 } else if (Name == "sha") { 3291 if (Enabled) 3292 setSSELevel(Features, SSE2, Enabled); 3293 } else if (Name == "sse4") { 3294 // We can get here via the __target__ attribute since that's not controlled 3295 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3296 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3297 // disabled. 3298 if (Enabled) 3299 setSSELevel(Features, SSE42, Enabled); 3300 else 3301 setSSELevel(Features, SSE41, Enabled); 3302 } else if (Name == "xsave") { 3303 if (!Enabled) 3304 Features["xsaveopt"] = false; 3305 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3306 if (Enabled) 3307 Features["xsave"] = true; 3308 } 3309 } 3310 3311 /// handleTargetFeatures - Perform initialization based on the user 3312 /// configured set of features. 3313 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3314 DiagnosticsEngine &Diags) { 3315 for (const auto &Feature : Features) { 3316 if (Feature[0] != '+') 3317 continue; 3318 3319 if (Feature == "+aes") { 3320 HasAES = true; 3321 } else if (Feature == "+pclmul") { 3322 HasPCLMUL = true; 3323 } else if (Feature == "+lzcnt") { 3324 HasLZCNT = true; 3325 } else if (Feature == "+rdrnd") { 3326 HasRDRND = true; 3327 } else if (Feature == "+fsgsbase") { 3328 HasFSGSBASE = true; 3329 } else if (Feature == "+bmi") { 3330 HasBMI = true; 3331 } else if (Feature == "+bmi2") { 3332 HasBMI2 = true; 3333 } else if (Feature == "+popcnt") { 3334 HasPOPCNT = true; 3335 } else if (Feature == "+rtm") { 3336 HasRTM = true; 3337 } else if (Feature == "+prfchw") { 3338 HasPRFCHW = true; 3339 } else if (Feature == "+rdseed") { 3340 HasRDSEED = true; 3341 } else if (Feature == "+adx") { 3342 HasADX = true; 3343 } else if (Feature == "+tbm") { 3344 HasTBM = true; 3345 } else if (Feature == "+fma") { 3346 HasFMA = true; 3347 } else if (Feature == "+f16c") { 3348 HasF16C = true; 3349 } else if (Feature == "+avx512cd") { 3350 HasAVX512CD = true; 3351 } else if (Feature == "+avx512er") { 3352 HasAVX512ER = true; 3353 } else if (Feature == "+avx512pf") { 3354 HasAVX512PF = true; 3355 } else if (Feature == "+avx512dq") { 3356 HasAVX512DQ = true; 3357 } else if (Feature == "+avx512bw") { 3358 HasAVX512BW = true; 3359 } else if (Feature == "+avx512vl") { 3360 HasAVX512VL = true; 3361 } else if (Feature == "+avx512vbmi") { 3362 HasAVX512VBMI = true; 3363 } else if (Feature == "+avx512ifma") { 3364 HasAVX512IFMA = true; 3365 } else if (Feature == "+sha") { 3366 HasSHA = true; 3367 } else if (Feature == "+mpx") { 3368 HasMPX = true; 3369 } else if (Feature == "+movbe") { 3370 HasMOVBE = true; 3371 } else if (Feature == "+sgx") { 3372 HasSGX = true; 3373 } else if (Feature == "+cx16") { 3374 HasCX16 = true; 3375 } else if (Feature == "+fxsr") { 3376 HasFXSR = true; 3377 } else if (Feature == "+xsave") { 3378 HasXSAVE = true; 3379 } else if (Feature == "+xsaveopt") { 3380 HasXSAVEOPT = true; 3381 } else if (Feature == "+xsavec") { 3382 HasXSAVEC = true; 3383 } else if (Feature == "+xsaves") { 3384 HasXSAVES = true; 3385 } else if (Feature == "+mwaitx") { 3386 HasMWAITX = true; 3387 } else if (Feature == "+pku") { 3388 HasPKU = true; 3389 } else if (Feature == "+clflushopt") { 3390 HasCLFLUSHOPT = true; 3391 } else if (Feature == "+pcommit") { 3392 HasPCOMMIT = true; 3393 } else if (Feature == "+clwb") { 3394 HasCLWB = true; 3395 } else if (Feature == "+umip") { 3396 HasUMIP = true; 3397 } else if (Feature == "+prefetchwt1") { 3398 HasPREFETCHWT1 = true; 3399 } 3400 3401 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3402 .Case("+avx512f", AVX512F) 3403 .Case("+avx2", AVX2) 3404 .Case("+avx", AVX) 3405 .Case("+sse4.2", SSE42) 3406 .Case("+sse4.1", SSE41) 3407 .Case("+ssse3", SSSE3) 3408 .Case("+sse3", SSE3) 3409 .Case("+sse2", SSE2) 3410 .Case("+sse", SSE1) 3411 .Default(NoSSE); 3412 SSELevel = std::max(SSELevel, Level); 3413 3414 MMX3DNowEnum ThreeDNowLevel = 3415 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3416 .Case("+3dnowa", AMD3DNowAthlon) 3417 .Case("+3dnow", AMD3DNow) 3418 .Case("+mmx", MMX) 3419 .Default(NoMMX3DNow); 3420 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3421 3422 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3423 .Case("+xop", XOP) 3424 .Case("+fma4", FMA4) 3425 .Case("+sse4a", SSE4A) 3426 .Default(NoXOP); 3427 XOPLevel = std::max(XOPLevel, XLevel); 3428 } 3429 3430 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3431 // matches the selected sse level. 3432 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3433 (FPMath == FP_387 && SSELevel >= SSE1)) { 3434 Diags.Report(diag::err_target_unsupported_fpmath) << 3435 (FPMath == FP_SSE ? "sse" : "387"); 3436 return false; 3437 } 3438 3439 SimdDefaultAlign = 3440 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3441 return true; 3442 } 3443 3444 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3445 /// definitions for this particular subtarget. 3446 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3447 MacroBuilder &Builder) const { 3448 // Target identification. 3449 if (getTriple().getArch() == llvm::Triple::x86_64) { 3450 Builder.defineMacro("__amd64__"); 3451 Builder.defineMacro("__amd64"); 3452 Builder.defineMacro("__x86_64"); 3453 Builder.defineMacro("__x86_64__"); 3454 if (getTriple().getArchName() == "x86_64h") { 3455 Builder.defineMacro("__x86_64h"); 3456 Builder.defineMacro("__x86_64h__"); 3457 } 3458 } else { 3459 DefineStd(Builder, "i386", Opts); 3460 } 3461 3462 // Subtarget options. 3463 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3464 // truly should be based on -mtune options. 3465 switch (CPU) { 3466 case CK_Generic: 3467 break; 3468 case CK_i386: 3469 // The rest are coming from the i386 define above. 3470 Builder.defineMacro("__tune_i386__"); 3471 break; 3472 case CK_i486: 3473 case CK_WinChipC6: 3474 case CK_WinChip2: 3475 case CK_C3: 3476 defineCPUMacros(Builder, "i486"); 3477 break; 3478 case CK_PentiumMMX: 3479 Builder.defineMacro("__pentium_mmx__"); 3480 Builder.defineMacro("__tune_pentium_mmx__"); 3481 // Fallthrough 3482 case CK_i586: 3483 case CK_Pentium: 3484 defineCPUMacros(Builder, "i586"); 3485 defineCPUMacros(Builder, "pentium"); 3486 break; 3487 case CK_Pentium3: 3488 case CK_Pentium3M: 3489 case CK_PentiumM: 3490 Builder.defineMacro("__tune_pentium3__"); 3491 // Fallthrough 3492 case CK_Pentium2: 3493 case CK_C3_2: 3494 Builder.defineMacro("__tune_pentium2__"); 3495 // Fallthrough 3496 case CK_PentiumPro: 3497 Builder.defineMacro("__tune_i686__"); 3498 Builder.defineMacro("__tune_pentiumpro__"); 3499 // Fallthrough 3500 case CK_i686: 3501 Builder.defineMacro("__i686"); 3502 Builder.defineMacro("__i686__"); 3503 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3504 Builder.defineMacro("__pentiumpro"); 3505 Builder.defineMacro("__pentiumpro__"); 3506 break; 3507 case CK_Pentium4: 3508 case CK_Pentium4M: 3509 defineCPUMacros(Builder, "pentium4"); 3510 break; 3511 case CK_Yonah: 3512 case CK_Prescott: 3513 case CK_Nocona: 3514 defineCPUMacros(Builder, "nocona"); 3515 break; 3516 case CK_Core2: 3517 case CK_Penryn: 3518 defineCPUMacros(Builder, "core2"); 3519 break; 3520 case CK_Bonnell: 3521 defineCPUMacros(Builder, "atom"); 3522 break; 3523 case CK_Silvermont: 3524 defineCPUMacros(Builder, "slm"); 3525 break; 3526 case CK_Nehalem: 3527 case CK_Westmere: 3528 case CK_SandyBridge: 3529 case CK_IvyBridge: 3530 case CK_Haswell: 3531 case CK_Broadwell: 3532 case CK_SkylakeClient: 3533 // FIXME: Historically, we defined this legacy name, it would be nice to 3534 // remove it at some point. We've never exposed fine-grained names for 3535 // recent primary x86 CPUs, and we should keep it that way. 3536 defineCPUMacros(Builder, "corei7"); 3537 break; 3538 case CK_SkylakeServer: 3539 defineCPUMacros(Builder, "skx"); 3540 break; 3541 case CK_Cannonlake: 3542 break; 3543 case CK_KNL: 3544 defineCPUMacros(Builder, "knl"); 3545 break; 3546 case CK_Lakemont: 3547 Builder.defineMacro("__tune_lakemont__"); 3548 break; 3549 case CK_K6_2: 3550 Builder.defineMacro("__k6_2__"); 3551 Builder.defineMacro("__tune_k6_2__"); 3552 // Fallthrough 3553 case CK_K6_3: 3554 if (CPU != CK_K6_2) { // In case of fallthrough 3555 // FIXME: GCC may be enabling these in cases where some other k6 3556 // architecture is specified but -m3dnow is explicitly provided. The 3557 // exact semantics need to be determined and emulated here. 3558 Builder.defineMacro("__k6_3__"); 3559 Builder.defineMacro("__tune_k6_3__"); 3560 } 3561 // Fallthrough 3562 case CK_K6: 3563 defineCPUMacros(Builder, "k6"); 3564 break; 3565 case CK_Athlon: 3566 case CK_AthlonThunderbird: 3567 case CK_Athlon4: 3568 case CK_AthlonXP: 3569 case CK_AthlonMP: 3570 defineCPUMacros(Builder, "athlon"); 3571 if (SSELevel != NoSSE) { 3572 Builder.defineMacro("__athlon_sse__"); 3573 Builder.defineMacro("__tune_athlon_sse__"); 3574 } 3575 break; 3576 case CK_K8: 3577 case CK_K8SSE3: 3578 case CK_x86_64: 3579 case CK_Opteron: 3580 case CK_OpteronSSE3: 3581 case CK_Athlon64: 3582 case CK_Athlon64SSE3: 3583 case CK_AthlonFX: 3584 defineCPUMacros(Builder, "k8"); 3585 break; 3586 case CK_AMDFAM10: 3587 defineCPUMacros(Builder, "amdfam10"); 3588 break; 3589 case CK_BTVER1: 3590 defineCPUMacros(Builder, "btver1"); 3591 break; 3592 case CK_BTVER2: 3593 defineCPUMacros(Builder, "btver2"); 3594 break; 3595 case CK_BDVER1: 3596 defineCPUMacros(Builder, "bdver1"); 3597 break; 3598 case CK_BDVER2: 3599 defineCPUMacros(Builder, "bdver2"); 3600 break; 3601 case CK_BDVER3: 3602 defineCPUMacros(Builder, "bdver3"); 3603 break; 3604 case CK_BDVER4: 3605 defineCPUMacros(Builder, "bdver4"); 3606 break; 3607 case CK_Geode: 3608 defineCPUMacros(Builder, "geode"); 3609 break; 3610 } 3611 3612 // Target properties. 3613 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3614 3615 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3616 // functions in glibc header files that use FP Stack inline asm which the 3617 // backend can't deal with (PR879). 3618 Builder.defineMacro("__NO_MATH_INLINES"); 3619 3620 if (HasAES) 3621 Builder.defineMacro("__AES__"); 3622 3623 if (HasPCLMUL) 3624 Builder.defineMacro("__PCLMUL__"); 3625 3626 if (HasLZCNT) 3627 Builder.defineMacro("__LZCNT__"); 3628 3629 if (HasRDRND) 3630 Builder.defineMacro("__RDRND__"); 3631 3632 if (HasFSGSBASE) 3633 Builder.defineMacro("__FSGSBASE__"); 3634 3635 if (HasBMI) 3636 Builder.defineMacro("__BMI__"); 3637 3638 if (HasBMI2) 3639 Builder.defineMacro("__BMI2__"); 3640 3641 if (HasPOPCNT) 3642 Builder.defineMacro("__POPCNT__"); 3643 3644 if (HasRTM) 3645 Builder.defineMacro("__RTM__"); 3646 3647 if (HasPRFCHW) 3648 Builder.defineMacro("__PRFCHW__"); 3649 3650 if (HasRDSEED) 3651 Builder.defineMacro("__RDSEED__"); 3652 3653 if (HasADX) 3654 Builder.defineMacro("__ADX__"); 3655 3656 if (HasTBM) 3657 Builder.defineMacro("__TBM__"); 3658 3659 if (HasMWAITX) 3660 Builder.defineMacro("__MWAITX__"); 3661 3662 switch (XOPLevel) { 3663 case XOP: 3664 Builder.defineMacro("__XOP__"); 3665 case FMA4: 3666 Builder.defineMacro("__FMA4__"); 3667 case SSE4A: 3668 Builder.defineMacro("__SSE4A__"); 3669 case NoXOP: 3670 break; 3671 } 3672 3673 if (HasFMA) 3674 Builder.defineMacro("__FMA__"); 3675 3676 if (HasF16C) 3677 Builder.defineMacro("__F16C__"); 3678 3679 if (HasAVX512CD) 3680 Builder.defineMacro("__AVX512CD__"); 3681 if (HasAVX512ER) 3682 Builder.defineMacro("__AVX512ER__"); 3683 if (HasAVX512PF) 3684 Builder.defineMacro("__AVX512PF__"); 3685 if (HasAVX512DQ) 3686 Builder.defineMacro("__AVX512DQ__"); 3687 if (HasAVX512BW) 3688 Builder.defineMacro("__AVX512BW__"); 3689 if (HasAVX512VL) 3690 Builder.defineMacro("__AVX512VL__"); 3691 if (HasAVX512VBMI) 3692 Builder.defineMacro("__AVX512VBMI__"); 3693 if (HasAVX512IFMA) 3694 Builder.defineMacro("__AVX512IFMA__"); 3695 3696 if (HasSHA) 3697 Builder.defineMacro("__SHA__"); 3698 3699 if (HasFXSR) 3700 Builder.defineMacro("__FXSR__"); 3701 if (HasXSAVE) 3702 Builder.defineMacro("__XSAVE__"); 3703 if (HasXSAVEOPT) 3704 Builder.defineMacro("__XSAVEOPT__"); 3705 if (HasXSAVEC) 3706 Builder.defineMacro("__XSAVEC__"); 3707 if (HasXSAVES) 3708 Builder.defineMacro("__XSAVES__"); 3709 if (HasPKU) 3710 Builder.defineMacro("__PKU__"); 3711 if (HasCX16) 3712 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3713 3714 // Each case falls through to the previous one here. 3715 switch (SSELevel) { 3716 case AVX512F: 3717 Builder.defineMacro("__AVX512F__"); 3718 case AVX2: 3719 Builder.defineMacro("__AVX2__"); 3720 case AVX: 3721 Builder.defineMacro("__AVX__"); 3722 case SSE42: 3723 Builder.defineMacro("__SSE4_2__"); 3724 case SSE41: 3725 Builder.defineMacro("__SSE4_1__"); 3726 case SSSE3: 3727 Builder.defineMacro("__SSSE3__"); 3728 case SSE3: 3729 Builder.defineMacro("__SSE3__"); 3730 case SSE2: 3731 Builder.defineMacro("__SSE2__"); 3732 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3733 case SSE1: 3734 Builder.defineMacro("__SSE__"); 3735 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3736 case NoSSE: 3737 break; 3738 } 3739 3740 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3741 switch (SSELevel) { 3742 case AVX512F: 3743 case AVX2: 3744 case AVX: 3745 case SSE42: 3746 case SSE41: 3747 case SSSE3: 3748 case SSE3: 3749 case SSE2: 3750 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3751 break; 3752 case SSE1: 3753 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3754 break; 3755 default: 3756 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3757 } 3758 } 3759 3760 // Each case falls through to the previous one here. 3761 switch (MMX3DNowLevel) { 3762 case AMD3DNowAthlon: 3763 Builder.defineMacro("__3dNOW_A__"); 3764 case AMD3DNow: 3765 Builder.defineMacro("__3dNOW__"); 3766 case MMX: 3767 Builder.defineMacro("__MMX__"); 3768 case NoMMX3DNow: 3769 break; 3770 } 3771 3772 if (CPU >= CK_i486) { 3773 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3774 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3775 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3776 } 3777 if (CPU >= CK_i586) 3778 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3779 } 3780 3781 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3782 return llvm::StringSwitch<bool>(Feature) 3783 .Case("aes", HasAES) 3784 .Case("avx", SSELevel >= AVX) 3785 .Case("avx2", SSELevel >= AVX2) 3786 .Case("avx512f", SSELevel >= AVX512F) 3787 .Case("avx512cd", HasAVX512CD) 3788 .Case("avx512er", HasAVX512ER) 3789 .Case("avx512pf", HasAVX512PF) 3790 .Case("avx512dq", HasAVX512DQ) 3791 .Case("avx512bw", HasAVX512BW) 3792 .Case("avx512vl", HasAVX512VL) 3793 .Case("avx512vbmi", HasAVX512VBMI) 3794 .Case("avx512ifma", HasAVX512IFMA) 3795 .Case("bmi", HasBMI) 3796 .Case("bmi2", HasBMI2) 3797 .Case("clflushopt", HasCLFLUSHOPT) 3798 .Case("clwb", HasCLWB) 3799 .Case("cx16", HasCX16) 3800 .Case("f16c", HasF16C) 3801 .Case("fma", HasFMA) 3802 .Case("fma4", XOPLevel >= FMA4) 3803 .Case("fsgsbase", HasFSGSBASE) 3804 .Case("fxsr", HasFXSR) 3805 .Case("lzcnt", HasLZCNT) 3806 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3807 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3808 .Case("mmx", MMX3DNowLevel >= MMX) 3809 .Case("movbe", HasMOVBE) 3810 .Case("mpx", HasMPX) 3811 .Case("pclmul", HasPCLMUL) 3812 .Case("pcommit", HasPCOMMIT) 3813 .Case("pku", HasPKU) 3814 .Case("popcnt", HasPOPCNT) 3815 .Case("prefetchwt1", HasPREFETCHWT1) 3816 .Case("prfchw", HasPRFCHW) 3817 .Case("rdrnd", HasRDRND) 3818 .Case("rdseed", HasRDSEED) 3819 .Case("rtm", HasRTM) 3820 .Case("sgx", HasSGX) 3821 .Case("sha", HasSHA) 3822 .Case("sse", SSELevel >= SSE1) 3823 .Case("sse2", SSELevel >= SSE2) 3824 .Case("sse3", SSELevel >= SSE3) 3825 .Case("ssse3", SSELevel >= SSSE3) 3826 .Case("sse4.1", SSELevel >= SSE41) 3827 .Case("sse4.2", SSELevel >= SSE42) 3828 .Case("sse4a", XOPLevel >= SSE4A) 3829 .Case("tbm", HasTBM) 3830 .Case("umip", HasUMIP) 3831 .Case("x86", true) 3832 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3833 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3834 .Case("xop", XOPLevel >= XOP) 3835 .Case("xsave", HasXSAVE) 3836 .Case("xsavec", HasXSAVEC) 3837 .Case("xsaves", HasXSAVES) 3838 .Case("xsaveopt", HasXSAVEOPT) 3839 .Default(false); 3840 } 3841 3842 // We can't use a generic validation scheme for the features accepted here 3843 // versus subtarget features accepted in the target attribute because the 3844 // bitfield structure that's initialized in the runtime only supports the 3845 // below currently rather than the full range of subtarget features. (See 3846 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3847 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3848 return llvm::StringSwitch<bool>(FeatureStr) 3849 .Case("cmov", true) 3850 .Case("mmx", true) 3851 .Case("popcnt", true) 3852 .Case("sse", true) 3853 .Case("sse2", true) 3854 .Case("sse3", true) 3855 .Case("ssse3", true) 3856 .Case("sse4.1", true) 3857 .Case("sse4.2", true) 3858 .Case("avx", true) 3859 .Case("avx2", true) 3860 .Case("sse4a", true) 3861 .Case("fma4", true) 3862 .Case("xop", true) 3863 .Case("fma", true) 3864 .Case("avx512f", true) 3865 .Case("bmi", true) 3866 .Case("bmi2", true) 3867 .Case("aes", true) 3868 .Case("pclmul", true) 3869 .Case("avx512vl", true) 3870 .Case("avx512bw", true) 3871 .Case("avx512dq", true) 3872 .Case("avx512cd", true) 3873 .Case("avx512er", true) 3874 .Case("avx512pf", true) 3875 .Case("avx512vbmi", true) 3876 .Case("avx512ifma", true) 3877 .Default(false); 3878 } 3879 3880 bool 3881 X86TargetInfo::validateAsmConstraint(const char *&Name, 3882 TargetInfo::ConstraintInfo &Info) const { 3883 switch (*Name) { 3884 default: return false; 3885 // Constant constraints. 3886 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3887 // instructions. 3888 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3889 // x86_64 instructions. 3890 case 's': 3891 Info.setRequiresImmediate(); 3892 return true; 3893 case 'I': 3894 Info.setRequiresImmediate(0, 31); 3895 return true; 3896 case 'J': 3897 Info.setRequiresImmediate(0, 63); 3898 return true; 3899 case 'K': 3900 Info.setRequiresImmediate(-128, 127); 3901 return true; 3902 case 'L': 3903 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3904 return true; 3905 case 'M': 3906 Info.setRequiresImmediate(0, 3); 3907 return true; 3908 case 'N': 3909 Info.setRequiresImmediate(0, 255); 3910 return true; 3911 case 'O': 3912 Info.setRequiresImmediate(0, 127); 3913 return true; 3914 // Register constraints. 3915 case 'Y': // 'Y' is the first character for several 2-character constraints. 3916 // Shift the pointer to the second character of the constraint. 3917 Name++; 3918 switch (*Name) { 3919 default: 3920 return false; 3921 case '0': // First SSE register. 3922 case 't': // Any SSE register, when SSE2 is enabled. 3923 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3924 case 'm': // Any MMX register, when inter-unit moves enabled. 3925 Info.setAllowsRegister(); 3926 return true; 3927 } 3928 case 'f': // Any x87 floating point stack register. 3929 // Constraint 'f' cannot be used for output operands. 3930 if (Info.ConstraintStr[0] == '=') 3931 return false; 3932 Info.setAllowsRegister(); 3933 return true; 3934 case 'a': // eax. 3935 case 'b': // ebx. 3936 case 'c': // ecx. 3937 case 'd': // edx. 3938 case 'S': // esi. 3939 case 'D': // edi. 3940 case 'A': // edx:eax. 3941 case 't': // Top of floating point stack. 3942 case 'u': // Second from top of floating point stack. 3943 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3944 case 'y': // Any MMX register. 3945 case 'x': // Any SSE register. 3946 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3947 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3948 case 'l': // "Index" registers: any general register that can be used as an 3949 // index in a base+index memory access. 3950 Info.setAllowsRegister(); 3951 return true; 3952 // Floating point constant constraints. 3953 case 'C': // SSE floating point constant. 3954 case 'G': // x87 floating point constant. 3955 return true; 3956 } 3957 } 3958 3959 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3960 unsigned Size) const { 3961 // Strip off constraint modifiers. 3962 while (Constraint[0] == '=' || 3963 Constraint[0] == '+' || 3964 Constraint[0] == '&') 3965 Constraint = Constraint.substr(1); 3966 3967 return validateOperandSize(Constraint, Size); 3968 } 3969 3970 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3971 unsigned Size) const { 3972 return validateOperandSize(Constraint, Size); 3973 } 3974 3975 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3976 unsigned Size) const { 3977 switch (Constraint[0]) { 3978 default: break; 3979 case 'y': 3980 return Size <= 64; 3981 case 'f': 3982 case 't': 3983 case 'u': 3984 return Size <= 128; 3985 case 'x': 3986 if (SSELevel >= AVX512F) 3987 // 512-bit zmm registers can be used if target supports AVX512F. 3988 return Size <= 512U; 3989 else if (SSELevel >= AVX) 3990 // 256-bit ymm registers can be used if target supports AVX. 3991 return Size <= 256U; 3992 return Size <= 128U; 3993 case 'Y': 3994 // 'Y' is the first character for several 2-character constraints. 3995 switch (Constraint[1]) { 3996 default: break; 3997 case 'm': 3998 // 'Ym' is synonymous with 'y'. 3999 return Size <= 64; 4000 case 'i': 4001 case 't': 4002 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4003 if (SSELevel >= AVX512F) 4004 return Size <= 512U; 4005 else if (SSELevel >= AVX) 4006 return Size <= 256U; 4007 return SSELevel >= SSE2 && Size <= 128U; 4008 } 4009 4010 } 4011 4012 return true; 4013 } 4014 4015 std::string 4016 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4017 switch (*Constraint) { 4018 case 'a': return std::string("{ax}"); 4019 case 'b': return std::string("{bx}"); 4020 case 'c': return std::string("{cx}"); 4021 case 'd': return std::string("{dx}"); 4022 case 'S': return std::string("{si}"); 4023 case 'D': return std::string("{di}"); 4024 case 'p': // address 4025 return std::string("im"); 4026 case 't': // top of floating point stack. 4027 return std::string("{st}"); 4028 case 'u': // second from top of floating point stack. 4029 return std::string("{st(1)}"); // second from top of floating point stack. 4030 default: 4031 return std::string(1, *Constraint); 4032 } 4033 } 4034 4035 // X86-32 generic target 4036 class X86_32TargetInfo : public X86TargetInfo { 4037 public: 4038 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4039 : X86TargetInfo(Triple, Opts) { 4040 DoubleAlign = LongLongAlign = 32; 4041 LongDoubleWidth = 96; 4042 LongDoubleAlign = 32; 4043 SuitableAlign = 128; 4044 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4045 SizeType = UnsignedInt; 4046 PtrDiffType = SignedInt; 4047 IntPtrType = SignedInt; 4048 RegParmMax = 3; 4049 4050 // Use fpret for all types. 4051 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4052 (1 << TargetInfo::Double) | 4053 (1 << TargetInfo::LongDouble)); 4054 4055 // x86-32 has atomics up to 8 bytes 4056 // FIXME: Check that we actually have cmpxchg8b before setting 4057 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4058 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4059 } 4060 BuiltinVaListKind getBuiltinVaListKind() const override { 4061 return TargetInfo::CharPtrBuiltinVaList; 4062 } 4063 4064 int getEHDataRegisterNumber(unsigned RegNo) const override { 4065 if (RegNo == 0) return 0; 4066 if (RegNo == 1) return 2; 4067 return -1; 4068 } 4069 bool validateOperandSize(StringRef Constraint, 4070 unsigned Size) const override { 4071 switch (Constraint[0]) { 4072 default: break; 4073 case 'R': 4074 case 'q': 4075 case 'Q': 4076 case 'a': 4077 case 'b': 4078 case 'c': 4079 case 'd': 4080 case 'S': 4081 case 'D': 4082 return Size <= 32; 4083 case 'A': 4084 return Size <= 64; 4085 } 4086 4087 return X86TargetInfo::validateOperandSize(Constraint, Size); 4088 } 4089 }; 4090 4091 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4092 public: 4093 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4094 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4095 4096 unsigned getFloatEvalMethod() const override { 4097 unsigned Major, Minor, Micro; 4098 getTriple().getOSVersion(Major, Minor, Micro); 4099 // New NetBSD uses the default rounding mode. 4100 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4101 return X86_32TargetInfo::getFloatEvalMethod(); 4102 // NetBSD before 6.99.26 defaults to "double" rounding. 4103 return 1; 4104 } 4105 }; 4106 4107 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4108 public: 4109 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4110 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4111 SizeType = UnsignedLong; 4112 IntPtrType = SignedLong; 4113 PtrDiffType = SignedLong; 4114 } 4115 }; 4116 4117 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4118 public: 4119 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4120 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4121 SizeType = UnsignedLong; 4122 IntPtrType = SignedLong; 4123 PtrDiffType = SignedLong; 4124 } 4125 }; 4126 4127 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4128 public: 4129 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4130 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4131 LongDoubleWidth = 128; 4132 LongDoubleAlign = 128; 4133 SuitableAlign = 128; 4134 MaxVectorAlign = 256; 4135 // The watchOS simulator uses the builtin bool type for Objective-C. 4136 llvm::Triple T = llvm::Triple(Triple); 4137 if (T.isWatchOS()) 4138 UseSignedCharForObjCBool = false; 4139 SizeType = UnsignedLong; 4140 IntPtrType = SignedLong; 4141 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4142 HasAlignMac68kSupport = true; 4143 } 4144 4145 bool handleTargetFeatures(std::vector<std::string> &Features, 4146 DiagnosticsEngine &Diags) override { 4147 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4148 Diags)) 4149 return false; 4150 // We now know the features we have: we can decide how to align vectors. 4151 MaxVectorAlign = 4152 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4153 return true; 4154 } 4155 }; 4156 4157 // x86-32 Windows target 4158 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4159 public: 4160 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4161 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4162 WCharType = UnsignedShort; 4163 DoubleAlign = LongLongAlign = 64; 4164 bool IsWinCOFF = 4165 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4166 resetDataLayout(IsWinCOFF 4167 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4168 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4169 } 4170 void getTargetDefines(const LangOptions &Opts, 4171 MacroBuilder &Builder) const override { 4172 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4173 } 4174 }; 4175 4176 // x86-32 Windows Visual Studio target 4177 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4178 public: 4179 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4180 const TargetOptions &Opts) 4181 : WindowsX86_32TargetInfo(Triple, Opts) { 4182 LongDoubleWidth = LongDoubleAlign = 64; 4183 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4184 } 4185 void getTargetDefines(const LangOptions &Opts, 4186 MacroBuilder &Builder) const override { 4187 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4188 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4189 // The value of the following reflects processor type. 4190 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4191 // We lost the original triple, so we use the default. 4192 Builder.defineMacro("_M_IX86", "600"); 4193 } 4194 }; 4195 4196 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4197 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4198 // supports __declspec natively under -fms-extensions, but we define a no-op 4199 // __declspec macro anyway for pre-processor compatibility. 4200 if (Opts.MicrosoftExt) 4201 Builder.defineMacro("__declspec", "__declspec"); 4202 else 4203 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4204 4205 if (!Opts.MicrosoftExt) { 4206 // Provide macros for all the calling convention keywords. Provide both 4207 // single and double underscore prefixed variants. These are available on 4208 // x64 as well as x86, even though they have no effect. 4209 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4210 for (const char *CC : CCs) { 4211 std::string GCCSpelling = "__attribute__((__"; 4212 GCCSpelling += CC; 4213 GCCSpelling += "__))"; 4214 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4215 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4216 } 4217 } 4218 } 4219 4220 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4221 Builder.defineMacro("__MSVCRT__"); 4222 Builder.defineMacro("__MINGW32__"); 4223 addCygMingDefines(Opts, Builder); 4224 } 4225 4226 // x86-32 MinGW target 4227 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4228 public: 4229 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4230 : WindowsX86_32TargetInfo(Triple, Opts) {} 4231 void getTargetDefines(const LangOptions &Opts, 4232 MacroBuilder &Builder) const override { 4233 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4234 DefineStd(Builder, "WIN32", Opts); 4235 DefineStd(Builder, "WINNT", Opts); 4236 Builder.defineMacro("_X86_"); 4237 addMinGWDefines(Opts, Builder); 4238 } 4239 }; 4240 4241 // x86-32 Cygwin target 4242 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4243 public: 4244 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4245 : X86_32TargetInfo(Triple, Opts) { 4246 WCharType = UnsignedShort; 4247 DoubleAlign = LongLongAlign = 64; 4248 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4249 } 4250 void getTargetDefines(const LangOptions &Opts, 4251 MacroBuilder &Builder) const override { 4252 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4253 Builder.defineMacro("_X86_"); 4254 Builder.defineMacro("__CYGWIN__"); 4255 Builder.defineMacro("__CYGWIN32__"); 4256 addCygMingDefines(Opts, Builder); 4257 DefineStd(Builder, "unix", Opts); 4258 if (Opts.CPlusPlus) 4259 Builder.defineMacro("_GNU_SOURCE"); 4260 } 4261 }; 4262 4263 // x86-32 Haiku target 4264 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4265 public: 4266 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4267 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4268 } 4269 void getTargetDefines(const LangOptions &Opts, 4270 MacroBuilder &Builder) const override { 4271 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4272 Builder.defineMacro("__INTEL__"); 4273 } 4274 }; 4275 4276 // X86-32 MCU target 4277 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4278 public: 4279 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4280 : X86_32TargetInfo(Triple, Opts) { 4281 LongDoubleWidth = 64; 4282 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4283 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4284 WIntType = UnsignedInt; 4285 } 4286 4287 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4288 // On MCU we support only C calling convention. 4289 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4290 } 4291 4292 void getTargetDefines(const LangOptions &Opts, 4293 MacroBuilder &Builder) const override { 4294 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4295 Builder.defineMacro("__iamcu"); 4296 Builder.defineMacro("__iamcu__"); 4297 } 4298 4299 bool allowsLargerPreferedTypeAlignment() const override { 4300 return false; 4301 } 4302 }; 4303 4304 // RTEMS Target 4305 template<typename Target> 4306 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4307 protected: 4308 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4309 MacroBuilder &Builder) const override { 4310 // RTEMS defines; list based off of gcc output 4311 4312 Builder.defineMacro("__rtems__"); 4313 Builder.defineMacro("__ELF__"); 4314 } 4315 4316 public: 4317 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4318 : OSTargetInfo<Target>(Triple, Opts) { 4319 switch (Triple.getArch()) { 4320 default: 4321 case llvm::Triple::x86: 4322 // this->MCountName = ".mcount"; 4323 break; 4324 case llvm::Triple::mips: 4325 case llvm::Triple::mipsel: 4326 case llvm::Triple::ppc: 4327 case llvm::Triple::ppc64: 4328 case llvm::Triple::ppc64le: 4329 // this->MCountName = "_mcount"; 4330 break; 4331 case llvm::Triple::arm: 4332 // this->MCountName = "__mcount"; 4333 break; 4334 } 4335 } 4336 }; 4337 4338 // x86-32 RTEMS target 4339 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4340 public: 4341 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4342 : X86_32TargetInfo(Triple, Opts) { 4343 SizeType = UnsignedLong; 4344 IntPtrType = SignedLong; 4345 PtrDiffType = SignedLong; 4346 } 4347 void getTargetDefines(const LangOptions &Opts, 4348 MacroBuilder &Builder) const override { 4349 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4350 Builder.defineMacro("__INTEL__"); 4351 Builder.defineMacro("__rtems__"); 4352 } 4353 }; 4354 4355 // x86-64 generic target 4356 class X86_64TargetInfo : public X86TargetInfo { 4357 public: 4358 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4359 : X86TargetInfo(Triple, Opts) { 4360 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4361 bool IsWinCOFF = 4362 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4363 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4364 LongDoubleWidth = 128; 4365 LongDoubleAlign = 128; 4366 LargeArrayMinWidth = 128; 4367 LargeArrayAlign = 128; 4368 SuitableAlign = 128; 4369 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4370 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4371 IntPtrType = IsX32 ? SignedInt : SignedLong; 4372 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4373 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4374 RegParmMax = 6; 4375 4376 // Pointers are 32-bit in x32. 4377 resetDataLayout(IsX32 4378 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4379 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4380 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4381 4382 // Use fpret only for long double. 4383 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4384 4385 // Use fp2ret for _Complex long double. 4386 ComplexLongDoubleUsesFP2Ret = true; 4387 4388 // Make __builtin_ms_va_list available. 4389 HasBuiltinMSVaList = true; 4390 4391 // x86-64 has atomics up to 16 bytes. 4392 MaxAtomicPromoteWidth = 128; 4393 MaxAtomicInlineWidth = 128; 4394 } 4395 BuiltinVaListKind getBuiltinVaListKind() const override { 4396 return TargetInfo::X86_64ABIBuiltinVaList; 4397 } 4398 4399 int getEHDataRegisterNumber(unsigned RegNo) const override { 4400 if (RegNo == 0) return 0; 4401 if (RegNo == 1) return 1; 4402 return -1; 4403 } 4404 4405 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4406 switch (CC) { 4407 case CC_C: 4408 case CC_Swift: 4409 case CC_X86VectorCall: 4410 case CC_IntelOclBicc: 4411 case CC_X86_64Win64: 4412 case CC_PreserveMost: 4413 case CC_PreserveAll: 4414 return CCCR_OK; 4415 default: 4416 return CCCR_Warning; 4417 } 4418 } 4419 4420 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4421 return CC_C; 4422 } 4423 4424 // for x32 we need it here explicitly 4425 bool hasInt128Type() const override { return true; } 4426 unsigned getUnwindWordWidth() const override { return 64; } 4427 unsigned getRegisterWidth() const override { return 64; } 4428 4429 bool validateGlobalRegisterVariable(StringRef RegName, 4430 unsigned RegSize, 4431 bool &HasSizeMismatch) const override { 4432 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4433 // handle. 4434 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4435 // Check that the register size is 64-bit. 4436 HasSizeMismatch = RegSize != 64; 4437 return true; 4438 } 4439 4440 // Check if the register is a 32-bit register the backend can handle. 4441 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4442 HasSizeMismatch); 4443 } 4444 }; 4445 4446 // x86-64 Windows target 4447 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4448 public: 4449 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4450 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4451 WCharType = UnsignedShort; 4452 LongWidth = LongAlign = 32; 4453 DoubleAlign = LongLongAlign = 64; 4454 IntMaxType = SignedLongLong; 4455 Int64Type = SignedLongLong; 4456 SizeType = UnsignedLongLong; 4457 PtrDiffType = SignedLongLong; 4458 IntPtrType = SignedLongLong; 4459 } 4460 4461 void getTargetDefines(const LangOptions &Opts, 4462 MacroBuilder &Builder) const override { 4463 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4464 Builder.defineMacro("_WIN64"); 4465 } 4466 4467 BuiltinVaListKind getBuiltinVaListKind() const override { 4468 return TargetInfo::CharPtrBuiltinVaList; 4469 } 4470 4471 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4472 switch (CC) { 4473 case CC_X86StdCall: 4474 case CC_X86ThisCall: 4475 case CC_X86FastCall: 4476 return CCCR_Ignore; 4477 case CC_C: 4478 case CC_X86VectorCall: 4479 case CC_IntelOclBicc: 4480 case CC_X86_64SysV: 4481 return CCCR_OK; 4482 default: 4483 return CCCR_Warning; 4484 } 4485 } 4486 }; 4487 4488 // x86-64 Windows Visual Studio target 4489 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4490 public: 4491 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4492 const TargetOptions &Opts) 4493 : WindowsX86_64TargetInfo(Triple, Opts) { 4494 LongDoubleWidth = LongDoubleAlign = 64; 4495 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4496 } 4497 void getTargetDefines(const LangOptions &Opts, 4498 MacroBuilder &Builder) const override { 4499 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4500 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4501 Builder.defineMacro("_M_X64", "100"); 4502 Builder.defineMacro("_M_AMD64", "100"); 4503 } 4504 }; 4505 4506 // x86-64 MinGW target 4507 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4508 public: 4509 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4510 : WindowsX86_64TargetInfo(Triple, Opts) { 4511 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4512 // with x86 FP ops. Weird. 4513 LongDoubleWidth = LongDoubleAlign = 128; 4514 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4515 } 4516 4517 void getTargetDefines(const LangOptions &Opts, 4518 MacroBuilder &Builder) const override { 4519 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4520 DefineStd(Builder, "WIN64", Opts); 4521 Builder.defineMacro("__MINGW64__"); 4522 addMinGWDefines(Opts, Builder); 4523 4524 // GCC defines this macro when it is using __gxx_personality_seh0. 4525 if (!Opts.SjLjExceptions) 4526 Builder.defineMacro("__SEH__"); 4527 } 4528 }; 4529 4530 // x86-64 Cygwin target 4531 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4532 public: 4533 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4534 : X86_64TargetInfo(Triple, Opts) { 4535 TLSSupported = false; 4536 WCharType = UnsignedShort; 4537 } 4538 void getTargetDefines(const LangOptions &Opts, 4539 MacroBuilder &Builder) const override { 4540 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4541 Builder.defineMacro("__x86_64__"); 4542 Builder.defineMacro("__CYGWIN__"); 4543 Builder.defineMacro("__CYGWIN64__"); 4544 addCygMingDefines(Opts, Builder); 4545 DefineStd(Builder, "unix", Opts); 4546 if (Opts.CPlusPlus) 4547 Builder.defineMacro("_GNU_SOURCE"); 4548 4549 // GCC defines this macro when it is using __gxx_personality_seh0. 4550 if (!Opts.SjLjExceptions) 4551 Builder.defineMacro("__SEH__"); 4552 } 4553 }; 4554 4555 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4556 public: 4557 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4558 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4559 Int64Type = SignedLongLong; 4560 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4561 llvm::Triple T = llvm::Triple(Triple); 4562 if (T.isiOS()) 4563 UseSignedCharForObjCBool = false; 4564 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4565 } 4566 4567 bool handleTargetFeatures(std::vector<std::string> &Features, 4568 DiagnosticsEngine &Diags) override { 4569 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4570 Diags)) 4571 return false; 4572 // We now know the features we have: we can decide how to align vectors. 4573 MaxVectorAlign = 4574 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4575 return true; 4576 } 4577 }; 4578 4579 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4580 public: 4581 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4582 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4583 IntMaxType = SignedLongLong; 4584 Int64Type = SignedLongLong; 4585 } 4586 }; 4587 4588 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4589 public: 4590 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4591 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4592 IntMaxType = SignedLongLong; 4593 Int64Type = SignedLongLong; 4594 } 4595 }; 4596 4597 class ARMTargetInfo : public TargetInfo { 4598 // Possible FPU choices. 4599 enum FPUMode { 4600 VFP2FPU = (1 << 0), 4601 VFP3FPU = (1 << 1), 4602 VFP4FPU = (1 << 2), 4603 NeonFPU = (1 << 3), 4604 FPARMV8 = (1 << 4) 4605 }; 4606 4607 // Possible HWDiv features. 4608 enum HWDivMode { 4609 HWDivThumb = (1 << 0), 4610 HWDivARM = (1 << 1) 4611 }; 4612 4613 static bool FPUModeIsVFP(FPUMode Mode) { 4614 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4615 } 4616 4617 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4618 static const char * const GCCRegNames[]; 4619 4620 std::string ABI, CPU; 4621 4622 StringRef CPUProfile; 4623 StringRef CPUAttr; 4624 4625 enum { 4626 FP_Default, 4627 FP_VFP, 4628 FP_Neon 4629 } FPMath; 4630 4631 unsigned ArchISA; 4632 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4633 unsigned ArchProfile; 4634 unsigned ArchVersion; 4635 4636 unsigned FPU : 5; 4637 4638 unsigned IsAAPCS : 1; 4639 unsigned HWDiv : 2; 4640 4641 // Initialized via features. 4642 unsigned SoftFloat : 1; 4643 unsigned SoftFloatABI : 1; 4644 4645 unsigned CRC : 1; 4646 unsigned Crypto : 1; 4647 unsigned DSP : 1; 4648 unsigned Unaligned : 1; 4649 4650 enum { 4651 LDREX_B = (1 << 0), /// byte (8-bit) 4652 LDREX_H = (1 << 1), /// half (16-bit) 4653 LDREX_W = (1 << 2), /// word (32-bit) 4654 LDREX_D = (1 << 3), /// double (64-bit) 4655 }; 4656 4657 uint32_t LDREX; 4658 4659 // ACLE 6.5.1 Hardware floating point 4660 enum { 4661 HW_FP_HP = (1 << 1), /// half (16-bit) 4662 HW_FP_SP = (1 << 2), /// single (32-bit) 4663 HW_FP_DP = (1 << 3), /// double (64-bit) 4664 }; 4665 uint32_t HW_FP; 4666 4667 static const Builtin::Info BuiltinInfo[]; 4668 4669 void setABIAAPCS() { 4670 IsAAPCS = true; 4671 4672 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4673 const llvm::Triple &T = getTriple(); 4674 4675 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4676 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4677 T.getOS() == llvm::Triple::Bitrig) 4678 SizeType = UnsignedLong; 4679 else 4680 SizeType = UnsignedInt; 4681 4682 switch (T.getOS()) { 4683 case llvm::Triple::NetBSD: 4684 WCharType = SignedInt; 4685 break; 4686 case llvm::Triple::Win32: 4687 WCharType = UnsignedShort; 4688 break; 4689 case llvm::Triple::Linux: 4690 default: 4691 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4692 WCharType = UnsignedInt; 4693 break; 4694 } 4695 4696 UseBitFieldTypeAlignment = true; 4697 4698 ZeroLengthBitfieldBoundary = 0; 4699 4700 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4701 // so set preferred for small types to 32. 4702 if (T.isOSBinFormatMachO()) { 4703 resetDataLayout(BigEndian 4704 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4705 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4706 } else if (T.isOSWindows()) { 4707 assert(!BigEndian && "Windows on ARM does not support big endian"); 4708 resetDataLayout("e" 4709 "-m:w" 4710 "-p:32:32" 4711 "-i64:64" 4712 "-v128:64:128" 4713 "-a:0:32" 4714 "-n32" 4715 "-S64"); 4716 } else if (T.isOSNaCl()) { 4717 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4718 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4719 } else { 4720 resetDataLayout(BigEndian 4721 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4722 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4723 } 4724 4725 // FIXME: Enumerated types are variable width in straight AAPCS. 4726 } 4727 4728 void setABIAPCS(bool IsAAPCS16) { 4729 const llvm::Triple &T = getTriple(); 4730 4731 IsAAPCS = false; 4732 4733 if (IsAAPCS16) 4734 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4735 else 4736 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4737 4738 // size_t is unsigned int on FreeBSD. 4739 if (T.getOS() == llvm::Triple::FreeBSD) 4740 SizeType = UnsignedInt; 4741 else 4742 SizeType = UnsignedLong; 4743 4744 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4745 WCharType = SignedInt; 4746 4747 // Do not respect the alignment of bit-field types when laying out 4748 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4749 UseBitFieldTypeAlignment = false; 4750 4751 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4752 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4753 /// gcc. 4754 ZeroLengthBitfieldBoundary = 32; 4755 4756 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4757 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4758 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4759 } else if (T.isOSBinFormatMachO()) 4760 resetDataLayout( 4761 BigEndian 4762 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4763 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4764 else 4765 resetDataLayout( 4766 BigEndian 4767 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4768 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4769 4770 // FIXME: Override "preferred align" for double and long long. 4771 } 4772 4773 void setArchInfo() { 4774 StringRef ArchName = getTriple().getArchName(); 4775 4776 ArchISA = llvm::ARM::parseArchISA(ArchName); 4777 CPU = llvm::ARM::getDefaultCPU(ArchName); 4778 unsigned AK = llvm::ARM::parseArch(ArchName); 4779 if (AK != llvm::ARM::AK_INVALID) 4780 ArchKind = AK; 4781 setArchInfo(ArchKind); 4782 } 4783 4784 void setArchInfo(unsigned Kind) { 4785 StringRef SubArch; 4786 4787 // cache TargetParser info 4788 ArchKind = Kind; 4789 SubArch = llvm::ARM::getSubArch(ArchKind); 4790 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4791 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4792 4793 // cache CPU related strings 4794 CPUAttr = getCPUAttr(); 4795 CPUProfile = getCPUProfile(); 4796 } 4797 4798 void setAtomic() { 4799 // when triple does not specify a sub arch, 4800 // then we are not using inline atomics 4801 bool ShouldUseInlineAtomic = 4802 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4803 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4804 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4805 if (ArchProfile == llvm::ARM::PK_M) { 4806 MaxAtomicPromoteWidth = 32; 4807 if (ShouldUseInlineAtomic) 4808 MaxAtomicInlineWidth = 32; 4809 } 4810 else { 4811 MaxAtomicPromoteWidth = 64; 4812 if (ShouldUseInlineAtomic) 4813 MaxAtomicInlineWidth = 64; 4814 } 4815 } 4816 4817 bool isThumb() const { 4818 return (ArchISA == llvm::ARM::IK_THUMB); 4819 } 4820 4821 bool supportsThumb() const { 4822 return CPUAttr.count('T') || ArchVersion >= 6; 4823 } 4824 4825 bool supportsThumb2() const { 4826 return CPUAttr.equals("6T2") || 4827 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4828 } 4829 4830 StringRef getCPUAttr() const { 4831 // For most sub-arches, the build attribute CPU name is enough. 4832 // For Cortex variants, it's slightly different. 4833 switch(ArchKind) { 4834 default: 4835 return llvm::ARM::getCPUAttr(ArchKind); 4836 case llvm::ARM::AK_ARMV6M: 4837 return "6M"; 4838 case llvm::ARM::AK_ARMV7S: 4839 return "7S"; 4840 case llvm::ARM::AK_ARMV7A: 4841 return "7A"; 4842 case llvm::ARM::AK_ARMV7R: 4843 return "7R"; 4844 case llvm::ARM::AK_ARMV7M: 4845 return "7M"; 4846 case llvm::ARM::AK_ARMV7EM: 4847 return "7EM"; 4848 case llvm::ARM::AK_ARMV8A: 4849 return "8A"; 4850 case llvm::ARM::AK_ARMV8_1A: 4851 return "8_1A"; 4852 case llvm::ARM::AK_ARMV8_2A: 4853 return "8_2A"; 4854 case llvm::ARM::AK_ARMV8MBaseline: 4855 return "8M_BASE"; 4856 case llvm::ARM::AK_ARMV8MMainline: 4857 return "8M_MAIN"; 4858 } 4859 } 4860 4861 StringRef getCPUProfile() const { 4862 switch(ArchProfile) { 4863 case llvm::ARM::PK_A: 4864 return "A"; 4865 case llvm::ARM::PK_R: 4866 return "R"; 4867 case llvm::ARM::PK_M: 4868 return "M"; 4869 default: 4870 return ""; 4871 } 4872 } 4873 4874 public: 4875 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 4876 bool IsBigEndian) 4877 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4878 HW_FP(0) { 4879 BigEndian = IsBigEndian; 4880 4881 switch (getTriple().getOS()) { 4882 case llvm::Triple::NetBSD: 4883 PtrDiffType = SignedLong; 4884 break; 4885 default: 4886 PtrDiffType = SignedInt; 4887 break; 4888 } 4889 4890 // Cache arch related info. 4891 setArchInfo(); 4892 4893 // {} in inline assembly are neon specifiers, not assembly variant 4894 // specifiers. 4895 NoAsmVariants = true; 4896 4897 // FIXME: This duplicates code from the driver that sets the -target-abi 4898 // option - this code is used if -target-abi isn't passed and should 4899 // be unified in some way. 4900 if (Triple.isOSBinFormatMachO()) { 4901 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4902 // the frontend matches that. 4903 if (Triple.getEnvironment() == llvm::Triple::EABI || 4904 Triple.getOS() == llvm::Triple::UnknownOS || 4905 ArchProfile == llvm::ARM::PK_M) { 4906 setABI("aapcs"); 4907 } else if (Triple.isWatchABI()) { 4908 setABI("aapcs16"); 4909 } else { 4910 setABI("apcs-gnu"); 4911 } 4912 } else if (Triple.isOSWindows()) { 4913 // FIXME: this is invalid for WindowsCE 4914 setABI("aapcs"); 4915 } else { 4916 // Select the default based on the platform. 4917 switch (Triple.getEnvironment()) { 4918 case llvm::Triple::Android: 4919 case llvm::Triple::GNUEABI: 4920 case llvm::Triple::GNUEABIHF: 4921 case llvm::Triple::MuslEABI: 4922 case llvm::Triple::MuslEABIHF: 4923 setABI("aapcs-linux"); 4924 break; 4925 case llvm::Triple::EABIHF: 4926 case llvm::Triple::EABI: 4927 setABI("aapcs"); 4928 break; 4929 case llvm::Triple::GNU: 4930 setABI("apcs-gnu"); 4931 break; 4932 default: 4933 if (Triple.getOS() == llvm::Triple::NetBSD) 4934 setABI("apcs-gnu"); 4935 else 4936 setABI("aapcs"); 4937 break; 4938 } 4939 } 4940 4941 // ARM targets default to using the ARM C++ ABI. 4942 TheCXXABI.set(TargetCXXABI::GenericARM); 4943 4944 // ARM has atomics up to 8 bytes 4945 setAtomic(); 4946 4947 // Do force alignment of members that follow zero length bitfields. If 4948 // the alignment of the zero-length bitfield is greater than the member 4949 // that follows it, `bar', `bar' will be aligned as the type of the 4950 // zero length bitfield. 4951 UseZeroLengthBitfieldAlignment = true; 4952 4953 if (Triple.getOS() == llvm::Triple::Linux || 4954 Triple.getOS() == llvm::Triple::UnknownOS) 4955 this->MCountName = 4956 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 4957 } 4958 4959 StringRef getABI() const override { return ABI; } 4960 4961 bool setABI(const std::string &Name) override { 4962 ABI = Name; 4963 4964 // The defaults (above) are for AAPCS, check if we need to change them. 4965 // 4966 // FIXME: We need support for -meabi... we could just mangle it into the 4967 // name. 4968 if (Name == "apcs-gnu" || Name == "aapcs16") { 4969 setABIAPCS(Name == "aapcs16"); 4970 return true; 4971 } 4972 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4973 setABIAAPCS(); 4974 return true; 4975 } 4976 return false; 4977 } 4978 4979 // FIXME: This should be based on Arch attributes, not CPU names. 4980 bool 4981 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4982 StringRef CPU, 4983 const std::vector<std::string> &FeaturesVec) const override { 4984 4985 std::vector<const char*> TargetFeatures; 4986 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4987 4988 // get default FPU features 4989 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4990 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4991 4992 // get default Extension features 4993 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4994 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4995 4996 for (const char *Feature : TargetFeatures) 4997 if (Feature[0] == '+') 4998 Features[Feature+1] = true; 4999 5000 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5001 } 5002 5003 bool handleTargetFeatures(std::vector<std::string> &Features, 5004 DiagnosticsEngine &Diags) override { 5005 FPU = 0; 5006 CRC = 0; 5007 Crypto = 0; 5008 DSP = 0; 5009 Unaligned = 1; 5010 SoftFloat = SoftFloatABI = false; 5011 HWDiv = 0; 5012 5013 // This does not diagnose illegal cases like having both 5014 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5015 uint32_t HW_FP_remove = 0; 5016 for (const auto &Feature : Features) { 5017 if (Feature == "+soft-float") { 5018 SoftFloat = true; 5019 } else if (Feature == "+soft-float-abi") { 5020 SoftFloatABI = true; 5021 } else if (Feature == "+vfp2") { 5022 FPU |= VFP2FPU; 5023 HW_FP |= HW_FP_SP | HW_FP_DP; 5024 } else if (Feature == "+vfp3") { 5025 FPU |= VFP3FPU; 5026 HW_FP |= HW_FP_SP | HW_FP_DP; 5027 } else if (Feature == "+vfp4") { 5028 FPU |= VFP4FPU; 5029 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5030 } else if (Feature == "+fp-armv8") { 5031 FPU |= FPARMV8; 5032 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5033 } else if (Feature == "+neon") { 5034 FPU |= NeonFPU; 5035 HW_FP |= HW_FP_SP | HW_FP_DP; 5036 } else if (Feature == "+hwdiv") { 5037 HWDiv |= HWDivThumb; 5038 } else if (Feature == "+hwdiv-arm") { 5039 HWDiv |= HWDivARM; 5040 } else if (Feature == "+crc") { 5041 CRC = 1; 5042 } else if (Feature == "+crypto") { 5043 Crypto = 1; 5044 } else if (Feature == "+dsp") { 5045 DSP = 1; 5046 } else if (Feature == "+fp-only-sp") { 5047 HW_FP_remove |= HW_FP_DP; 5048 } else if (Feature == "+strict-align") { 5049 Unaligned = 0; 5050 } else if (Feature == "+fp16") { 5051 HW_FP |= HW_FP_HP; 5052 } 5053 } 5054 HW_FP &= ~HW_FP_remove; 5055 5056 switch (ArchVersion) { 5057 case 6: 5058 if (ArchProfile == llvm::ARM::PK_M) 5059 LDREX = 0; 5060 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5061 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5062 else 5063 LDREX = LDREX_W; 5064 break; 5065 case 7: 5066 if (ArchProfile == llvm::ARM::PK_M) 5067 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5068 else 5069 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5070 break; 5071 case 8: 5072 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5073 } 5074 5075 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5076 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5077 return false; 5078 } 5079 5080 if (FPMath == FP_Neon) 5081 Features.push_back("+neonfp"); 5082 else if (FPMath == FP_VFP) 5083 Features.push_back("-neonfp"); 5084 5085 // Remove front-end specific options which the backend handles differently. 5086 auto Feature = 5087 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5088 if (Feature != Features.end()) 5089 Features.erase(Feature); 5090 5091 return true; 5092 } 5093 5094 bool hasFeature(StringRef Feature) const override { 5095 return llvm::StringSwitch<bool>(Feature) 5096 .Case("arm", true) 5097 .Case("aarch32", true) 5098 .Case("softfloat", SoftFloat) 5099 .Case("thumb", isThumb()) 5100 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5101 .Case("hwdiv", HWDiv & HWDivThumb) 5102 .Case("hwdiv-arm", HWDiv & HWDivARM) 5103 .Default(false); 5104 } 5105 5106 bool setCPU(const std::string &Name) override { 5107 if (Name != "generic") 5108 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5109 5110 if (ArchKind == llvm::ARM::AK_INVALID) 5111 return false; 5112 setAtomic(); 5113 CPU = Name; 5114 return true; 5115 } 5116 5117 bool setFPMath(StringRef Name) override; 5118 5119 void getTargetDefines(const LangOptions &Opts, 5120 MacroBuilder &Builder) const override { 5121 // Target identification. 5122 Builder.defineMacro("__arm"); 5123 Builder.defineMacro("__arm__"); 5124 // For bare-metal none-eabi. 5125 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5126 getTriple().getEnvironment() == llvm::Triple::EABI) 5127 Builder.defineMacro("__ELF__"); 5128 5129 // Target properties. 5130 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5131 5132 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5133 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5134 if (getTriple().isWatchABI()) 5135 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5136 5137 if (!CPUAttr.empty()) 5138 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5139 5140 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5141 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5142 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5143 5144 if (ArchVersion >= 8) { 5145 // ACLE 6.5.7 Crypto Extension 5146 if (Crypto) 5147 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5148 // ACLE 6.5.8 CRC32 Extension 5149 if (CRC) 5150 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5151 // ACLE 6.5.10 Numeric Maximum and Minimum 5152 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5153 // ACLE 6.5.9 Directed Rounding 5154 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5155 } 5156 5157 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5158 // is not defined for the M-profile. 5159 // NOTE that the default profile is assumed to be 'A' 5160 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5161 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5162 5163 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5164 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5165 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5166 // v7 and v8 architectures excluding v8-M Baseline. 5167 if (supportsThumb2()) 5168 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5169 else if (supportsThumb()) 5170 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5171 5172 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5173 // instruction set such as ARM or Thumb. 5174 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5175 5176 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5177 5178 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5179 if (!CPUProfile.empty()) 5180 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5181 5182 // ACLE 6.4.3 Unaligned access supported in hardware 5183 if (Unaligned) 5184 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5185 5186 // ACLE 6.4.4 LDREX/STREX 5187 if (LDREX) 5188 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5189 5190 // ACLE 6.4.5 CLZ 5191 if (ArchVersion == 5 || 5192 (ArchVersion == 6 && CPUProfile != "M") || 5193 ArchVersion > 6) 5194 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5195 5196 // ACLE 6.5.1 Hardware Floating Point 5197 if (HW_FP) 5198 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5199 5200 // ACLE predefines. 5201 Builder.defineMacro("__ARM_ACLE", "200"); 5202 5203 // FP16 support (we currently only support IEEE format). 5204 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5205 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5206 5207 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5208 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5209 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5210 5211 // Subtarget options. 5212 5213 // FIXME: It's more complicated than this and we don't really support 5214 // interworking. 5215 // Windows on ARM does not "support" interworking 5216 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5217 Builder.defineMacro("__THUMB_INTERWORK__"); 5218 5219 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5220 // Embedded targets on Darwin follow AAPCS, but not EABI. 5221 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5222 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5223 Builder.defineMacro("__ARM_EABI__"); 5224 Builder.defineMacro("__ARM_PCS", "1"); 5225 } 5226 5227 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5228 ABI == "aapcs16") 5229 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5230 5231 if (SoftFloat) 5232 Builder.defineMacro("__SOFTFP__"); 5233 5234 if (ArchKind == llvm::ARM::AK_XSCALE) 5235 Builder.defineMacro("__XSCALE__"); 5236 5237 if (isThumb()) { 5238 Builder.defineMacro("__THUMBEL__"); 5239 Builder.defineMacro("__thumb__"); 5240 if (supportsThumb2()) 5241 Builder.defineMacro("__thumb2__"); 5242 } 5243 5244 // ACLE 6.4.9 32-bit SIMD instructions 5245 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5246 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5247 5248 // ACLE 6.4.10 Hardware Integer Divide 5249 if (((HWDiv & HWDivThumb) && isThumb()) || 5250 ((HWDiv & HWDivARM) && !isThumb())) { 5251 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5252 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5253 } 5254 5255 // Note, this is always on in gcc, even though it doesn't make sense. 5256 Builder.defineMacro("__APCS_32__"); 5257 5258 if (FPUModeIsVFP((FPUMode) FPU)) { 5259 Builder.defineMacro("__VFP_FP__"); 5260 if (FPU & VFP2FPU) 5261 Builder.defineMacro("__ARM_VFPV2__"); 5262 if (FPU & VFP3FPU) 5263 Builder.defineMacro("__ARM_VFPV3__"); 5264 if (FPU & VFP4FPU) 5265 Builder.defineMacro("__ARM_VFPV4__"); 5266 } 5267 5268 // This only gets set when Neon instructions are actually available, unlike 5269 // the VFP define, hence the soft float and arch check. This is subtly 5270 // different from gcc, we follow the intent which was that it should be set 5271 // when Neon instructions are actually available. 5272 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5273 Builder.defineMacro("__ARM_NEON", "1"); 5274 Builder.defineMacro("__ARM_NEON__"); 5275 // current AArch32 NEON implementations do not support double-precision 5276 // floating-point even when it is present in VFP. 5277 Builder.defineMacro("__ARM_NEON_FP", 5278 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5279 } 5280 5281 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5282 Opts.ShortWChar ? "2" : "4"); 5283 5284 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5285 Opts.ShortEnums ? "1" : "4"); 5286 5287 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5288 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5289 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5290 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5291 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5292 } 5293 5294 // ACLE 6.4.7 DSP instructions 5295 if (DSP) { 5296 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5297 } 5298 5299 // ACLE 6.4.8 Saturation instructions 5300 bool SAT = false; 5301 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5302 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5303 SAT = true; 5304 } 5305 5306 // ACLE 6.4.6 Q (saturation) flag 5307 if (DSP || SAT) 5308 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5309 5310 if (Opts.UnsafeFPMath) 5311 Builder.defineMacro("__ARM_FP_FAST", "1"); 5312 5313 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5314 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5315 } 5316 5317 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5318 return llvm::makeArrayRef(BuiltinInfo, 5319 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5320 } 5321 bool isCLZForZeroUndef() const override { return false; } 5322 BuiltinVaListKind getBuiltinVaListKind() const override { 5323 return IsAAPCS 5324 ? AAPCSABIBuiltinVaList 5325 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5326 : TargetInfo::VoidPtrBuiltinVaList); 5327 } 5328 ArrayRef<const char *> getGCCRegNames() const override; 5329 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5330 bool validateAsmConstraint(const char *&Name, 5331 TargetInfo::ConstraintInfo &Info) const override { 5332 switch (*Name) { 5333 default: break; 5334 case 'l': // r0-r7 5335 case 'h': // r8-r15 5336 case 't': // VFP Floating point register single precision 5337 case 'w': // VFP Floating point register double precision 5338 Info.setAllowsRegister(); 5339 return true; 5340 case 'I': 5341 case 'J': 5342 case 'K': 5343 case 'L': 5344 case 'M': 5345 // FIXME 5346 return true; 5347 case 'Q': // A memory address that is a single base register. 5348 Info.setAllowsMemory(); 5349 return true; 5350 case 'U': // a memory reference... 5351 switch (Name[1]) { 5352 case 'q': // ...ARMV4 ldrsb 5353 case 'v': // ...VFP load/store (reg+constant offset) 5354 case 'y': // ...iWMMXt load/store 5355 case 't': // address valid for load/store opaque types wider 5356 // than 128-bits 5357 case 'n': // valid address for Neon doubleword vector load/store 5358 case 'm': // valid address for Neon element and structure load/store 5359 case 's': // valid address for non-offset loads/stores of quad-word 5360 // values in four ARM registers 5361 Info.setAllowsMemory(); 5362 Name++; 5363 return true; 5364 } 5365 } 5366 return false; 5367 } 5368 std::string convertConstraint(const char *&Constraint) const override { 5369 std::string R; 5370 switch (*Constraint) { 5371 case 'U': // Two-character constraint; add "^" hint for later parsing. 5372 R = std::string("^") + std::string(Constraint, 2); 5373 Constraint++; 5374 break; 5375 case 'p': // 'p' should be translated to 'r' by default. 5376 R = std::string("r"); 5377 break; 5378 default: 5379 return std::string(1, *Constraint); 5380 } 5381 return R; 5382 } 5383 bool 5384 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5385 std::string &SuggestedModifier) const override { 5386 bool isOutput = (Constraint[0] == '='); 5387 bool isInOut = (Constraint[0] == '+'); 5388 5389 // Strip off constraint modifiers. 5390 while (Constraint[0] == '=' || 5391 Constraint[0] == '+' || 5392 Constraint[0] == '&') 5393 Constraint = Constraint.substr(1); 5394 5395 switch (Constraint[0]) { 5396 default: break; 5397 case 'r': { 5398 switch (Modifier) { 5399 default: 5400 return (isInOut || isOutput || Size <= 64); 5401 case 'q': 5402 // A register of size 32 cannot fit a vector type. 5403 return false; 5404 } 5405 } 5406 } 5407 5408 return true; 5409 } 5410 const char *getClobbers() const override { 5411 // FIXME: Is this really right? 5412 return ""; 5413 } 5414 5415 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5416 switch (CC) { 5417 case CC_AAPCS: 5418 case CC_AAPCS_VFP: 5419 case CC_Swift: 5420 return CCCR_OK; 5421 default: 5422 return CCCR_Warning; 5423 } 5424 } 5425 5426 int getEHDataRegisterNumber(unsigned RegNo) const override { 5427 if (RegNo == 0) return 0; 5428 if (RegNo == 1) return 1; 5429 return -1; 5430 } 5431 5432 bool hasSjLjLowering() const override { 5433 return true; 5434 } 5435 }; 5436 5437 bool ARMTargetInfo::setFPMath(StringRef Name) { 5438 if (Name == "neon") { 5439 FPMath = FP_Neon; 5440 return true; 5441 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5442 Name == "vfp4") { 5443 FPMath = FP_VFP; 5444 return true; 5445 } 5446 return false; 5447 } 5448 5449 const char * const ARMTargetInfo::GCCRegNames[] = { 5450 // Integer registers 5451 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5452 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5453 5454 // Float registers 5455 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5456 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5457 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5458 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5459 5460 // Double registers 5461 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5462 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5463 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5464 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5465 5466 // Quad registers 5467 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5468 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5469 }; 5470 5471 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5472 return llvm::makeArrayRef(GCCRegNames); 5473 } 5474 5475 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5476 { { "a1" }, "r0" }, 5477 { { "a2" }, "r1" }, 5478 { { "a3" }, "r2" }, 5479 { { "a4" }, "r3" }, 5480 { { "v1" }, "r4" }, 5481 { { "v2" }, "r5" }, 5482 { { "v3" }, "r6" }, 5483 { { "v4" }, "r7" }, 5484 { { "v5" }, "r8" }, 5485 { { "v6", "rfp" }, "r9" }, 5486 { { "sl" }, "r10" }, 5487 { { "fp" }, "r11" }, 5488 { { "ip" }, "r12" }, 5489 { { "r13" }, "sp" }, 5490 { { "r14" }, "lr" }, 5491 { { "r15" }, "pc" }, 5492 // The S, D and Q registers overlap, but aren't really aliases; we 5493 // don't want to substitute one of these for a different-sized one. 5494 }; 5495 5496 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5497 return llvm::makeArrayRef(GCCRegAliases); 5498 } 5499 5500 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5501 #define BUILTIN(ID, TYPE, ATTRS) \ 5502 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5503 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5504 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5505 #include "clang/Basic/BuiltinsNEON.def" 5506 5507 #define BUILTIN(ID, TYPE, ATTRS) \ 5508 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5509 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5510 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5511 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5512 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5513 #include "clang/Basic/BuiltinsARM.def" 5514 }; 5515 5516 class ARMleTargetInfo : public ARMTargetInfo { 5517 public: 5518 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5519 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/false) {} 5520 void getTargetDefines(const LangOptions &Opts, 5521 MacroBuilder &Builder) const override { 5522 Builder.defineMacro("__ARMEL__"); 5523 ARMTargetInfo::getTargetDefines(Opts, Builder); 5524 } 5525 }; 5526 5527 class ARMbeTargetInfo : public ARMTargetInfo { 5528 public: 5529 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5530 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/true) {} 5531 void getTargetDefines(const LangOptions &Opts, 5532 MacroBuilder &Builder) const override { 5533 Builder.defineMacro("__ARMEB__"); 5534 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5535 ARMTargetInfo::getTargetDefines(Opts, Builder); 5536 } 5537 }; 5538 5539 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5540 const llvm::Triple Triple; 5541 public: 5542 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5543 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5544 WCharType = UnsignedShort; 5545 SizeType = UnsignedInt; 5546 } 5547 void getVisualStudioDefines(const LangOptions &Opts, 5548 MacroBuilder &Builder) const { 5549 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5550 5551 // FIXME: this is invalid for WindowsCE 5552 Builder.defineMacro("_M_ARM_NT", "1"); 5553 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5554 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5555 5556 assert((Triple.getArch() == llvm::Triple::arm || 5557 Triple.getArch() == llvm::Triple::thumb) && 5558 "invalid architecture for Windows ARM target info"); 5559 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5560 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5561 5562 // TODO map the complete set of values 5563 // 31: VFPv3 40: VFPv4 5564 Builder.defineMacro("_M_ARM_FP", "31"); 5565 } 5566 BuiltinVaListKind getBuiltinVaListKind() const override { 5567 return TargetInfo::CharPtrBuiltinVaList; 5568 } 5569 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5570 switch (CC) { 5571 case CC_X86StdCall: 5572 case CC_X86ThisCall: 5573 case CC_X86FastCall: 5574 case CC_X86VectorCall: 5575 return CCCR_Ignore; 5576 case CC_C: 5577 return CCCR_OK; 5578 default: 5579 return CCCR_Warning; 5580 } 5581 } 5582 }; 5583 5584 // Windows ARM + Itanium C++ ABI Target 5585 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5586 public: 5587 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5588 const TargetOptions &Opts) 5589 : WindowsARMTargetInfo(Triple, Opts) { 5590 TheCXXABI.set(TargetCXXABI::GenericARM); 5591 } 5592 5593 void getTargetDefines(const LangOptions &Opts, 5594 MacroBuilder &Builder) const override { 5595 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5596 5597 if (Opts.MSVCCompat) 5598 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5599 } 5600 }; 5601 5602 // Windows ARM, MS (C++) ABI 5603 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5604 public: 5605 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5606 const TargetOptions &Opts) 5607 : WindowsARMTargetInfo(Triple, Opts) { 5608 TheCXXABI.set(TargetCXXABI::Microsoft); 5609 } 5610 5611 void getTargetDefines(const LangOptions &Opts, 5612 MacroBuilder &Builder) const override { 5613 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5614 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5615 } 5616 }; 5617 5618 // ARM MinGW target 5619 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5620 public: 5621 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5622 : WindowsARMTargetInfo(Triple, Opts) { 5623 TheCXXABI.set(TargetCXXABI::GenericARM); 5624 } 5625 5626 void getTargetDefines(const LangOptions &Opts, 5627 MacroBuilder &Builder) const override { 5628 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5629 DefineStd(Builder, "WIN32", Opts); 5630 DefineStd(Builder, "WINNT", Opts); 5631 Builder.defineMacro("_ARM_"); 5632 addMinGWDefines(Opts, Builder); 5633 } 5634 }; 5635 5636 // ARM Cygwin target 5637 class CygwinARMTargetInfo : public ARMleTargetInfo { 5638 public: 5639 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5640 : ARMleTargetInfo(Triple, Opts) { 5641 TLSSupported = false; 5642 WCharType = UnsignedShort; 5643 DoubleAlign = LongLongAlign = 64; 5644 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5645 } 5646 void getTargetDefines(const LangOptions &Opts, 5647 MacroBuilder &Builder) const override { 5648 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5649 Builder.defineMacro("_ARM_"); 5650 Builder.defineMacro("__CYGWIN__"); 5651 Builder.defineMacro("__CYGWIN32__"); 5652 DefineStd(Builder, "unix", Opts); 5653 if (Opts.CPlusPlus) 5654 Builder.defineMacro("_GNU_SOURCE"); 5655 } 5656 }; 5657 5658 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5659 protected: 5660 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5661 MacroBuilder &Builder) const override { 5662 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5663 } 5664 5665 public: 5666 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5667 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5668 HasAlignMac68kSupport = true; 5669 // iOS always has 64-bit atomic instructions. 5670 // FIXME: This should be based off of the target features in 5671 // ARMleTargetInfo. 5672 MaxAtomicInlineWidth = 64; 5673 5674 if (Triple.isWatchABI()) { 5675 // Darwin on iOS uses a variant of the ARM C++ ABI. 5676 TheCXXABI.set(TargetCXXABI::WatchOS); 5677 5678 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5679 // size_t is long, it's a bit weird for it to be int. 5680 PtrDiffType = SignedLong; 5681 5682 // BOOL should be a real boolean on the new ABI 5683 UseSignedCharForObjCBool = false; 5684 } else 5685 TheCXXABI.set(TargetCXXABI::iOS); 5686 } 5687 }; 5688 5689 class AArch64TargetInfo : public TargetInfo { 5690 virtual void setDataLayout() = 0; 5691 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5692 static const char *const GCCRegNames[]; 5693 5694 enum FPUModeEnum { 5695 FPUMode, 5696 NeonMode 5697 }; 5698 5699 unsigned FPU; 5700 unsigned CRC; 5701 unsigned Crypto; 5702 unsigned Unaligned; 5703 unsigned V8_1A; 5704 5705 static const Builtin::Info BuiltinInfo[]; 5706 5707 std::string ABI; 5708 5709 public: 5710 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5711 : TargetInfo(Triple), ABI("aapcs") { 5712 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5713 WCharType = SignedInt; 5714 5715 // NetBSD apparently prefers consistency across ARM targets to consistency 5716 // across 64-bit targets. 5717 Int64Type = SignedLongLong; 5718 IntMaxType = SignedLongLong; 5719 } else { 5720 WCharType = UnsignedInt; 5721 Int64Type = SignedLong; 5722 IntMaxType = SignedLong; 5723 } 5724 5725 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5726 MaxVectorAlign = 128; 5727 MaxAtomicInlineWidth = 128; 5728 MaxAtomicPromoteWidth = 128; 5729 5730 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5731 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5732 5733 // {} in inline assembly are neon specifiers, not assembly variant 5734 // specifiers. 5735 NoAsmVariants = true; 5736 5737 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5738 // contributes to the alignment of the containing aggregate in the same way 5739 // a plain (non bit-field) member of that type would, without exception for 5740 // zero-sized or anonymous bit-fields." 5741 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5742 UseZeroLengthBitfieldAlignment = true; 5743 5744 // AArch64 targets default to using the ARM C++ ABI. 5745 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5746 5747 if (Triple.getOS() == llvm::Triple::Linux || 5748 Triple.getOS() == llvm::Triple::UnknownOS) 5749 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5750 } 5751 5752 StringRef getABI() const override { return ABI; } 5753 bool setABI(const std::string &Name) override { 5754 if (Name != "aapcs" && Name != "darwinpcs") 5755 return false; 5756 5757 ABI = Name; 5758 return true; 5759 } 5760 5761 bool setCPU(const std::string &Name) override { 5762 return Name == "generic" || 5763 llvm::AArch64::parseCPUArch(Name) != 5764 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 5765 } 5766 5767 void getTargetDefines(const LangOptions &Opts, 5768 MacroBuilder &Builder) const override { 5769 // Target identification. 5770 Builder.defineMacro("__aarch64__"); 5771 5772 // Target properties. 5773 Builder.defineMacro("_LP64"); 5774 Builder.defineMacro("__LP64__"); 5775 5776 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5777 Builder.defineMacro("__ARM_ACLE", "200"); 5778 Builder.defineMacro("__ARM_ARCH", "8"); 5779 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5780 5781 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5782 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5783 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5784 5785 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5786 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5787 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5788 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5789 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5790 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5791 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5792 5793 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5794 5795 // 0xe implies support for half, single and double precision operations. 5796 Builder.defineMacro("__ARM_FP", "0xE"); 5797 5798 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5799 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5800 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5801 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5802 5803 if (Opts.UnsafeFPMath) 5804 Builder.defineMacro("__ARM_FP_FAST", "1"); 5805 5806 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5807 5808 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5809 Opts.ShortEnums ? "1" : "4"); 5810 5811 if (FPU == NeonMode) { 5812 Builder.defineMacro("__ARM_NEON", "1"); 5813 // 64-bit NEON supports half, single and double precision operations. 5814 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5815 } 5816 5817 if (CRC) 5818 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5819 5820 if (Crypto) 5821 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5822 5823 if (Unaligned) 5824 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5825 5826 if (V8_1A) 5827 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5828 5829 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5830 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5831 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5832 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5833 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5834 } 5835 5836 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5837 return llvm::makeArrayRef(BuiltinInfo, 5838 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5839 } 5840 5841 bool hasFeature(StringRef Feature) const override { 5842 return Feature == "aarch64" || 5843 Feature == "arm64" || 5844 Feature == "arm" || 5845 (Feature == "neon" && FPU == NeonMode); 5846 } 5847 5848 bool handleTargetFeatures(std::vector<std::string> &Features, 5849 DiagnosticsEngine &Diags) override { 5850 FPU = FPUMode; 5851 CRC = 0; 5852 Crypto = 0; 5853 Unaligned = 1; 5854 V8_1A = 0; 5855 5856 for (const auto &Feature : Features) { 5857 if (Feature == "+neon") 5858 FPU = NeonMode; 5859 if (Feature == "+crc") 5860 CRC = 1; 5861 if (Feature == "+crypto") 5862 Crypto = 1; 5863 if (Feature == "+strict-align") 5864 Unaligned = 0; 5865 if (Feature == "+v8.1a") 5866 V8_1A = 1; 5867 } 5868 5869 setDataLayout(); 5870 5871 return true; 5872 } 5873 5874 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5875 switch (CC) { 5876 case CC_C: 5877 case CC_Swift: 5878 case CC_PreserveMost: 5879 case CC_PreserveAll: 5880 return CCCR_OK; 5881 default: 5882 return CCCR_Warning; 5883 } 5884 } 5885 5886 bool isCLZForZeroUndef() const override { return false; } 5887 5888 BuiltinVaListKind getBuiltinVaListKind() const override { 5889 return TargetInfo::AArch64ABIBuiltinVaList; 5890 } 5891 5892 ArrayRef<const char *> getGCCRegNames() const override; 5893 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5894 5895 bool validateAsmConstraint(const char *&Name, 5896 TargetInfo::ConstraintInfo &Info) const override { 5897 switch (*Name) { 5898 default: 5899 return false; 5900 case 'w': // Floating point and SIMD registers (V0-V31) 5901 Info.setAllowsRegister(); 5902 return true; 5903 case 'I': // Constant that can be used with an ADD instruction 5904 case 'J': // Constant that can be used with a SUB instruction 5905 case 'K': // Constant that can be used with a 32-bit logical instruction 5906 case 'L': // Constant that can be used with a 64-bit logical instruction 5907 case 'M': // Constant that can be used as a 32-bit MOV immediate 5908 case 'N': // Constant that can be used as a 64-bit MOV immediate 5909 case 'Y': // Floating point constant zero 5910 case 'Z': // Integer constant zero 5911 return true; 5912 case 'Q': // A memory reference with base register and no offset 5913 Info.setAllowsMemory(); 5914 return true; 5915 case 'S': // A symbolic address 5916 Info.setAllowsRegister(); 5917 return true; 5918 case 'U': 5919 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5920 // Utf: A memory address suitable for ldp/stp in TF mode. 5921 // Usa: An absolute symbolic address. 5922 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5923 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5924 case 'z': // Zero register, wzr or xzr 5925 Info.setAllowsRegister(); 5926 return true; 5927 case 'x': // Floating point and SIMD registers (V0-V15) 5928 Info.setAllowsRegister(); 5929 return true; 5930 } 5931 return false; 5932 } 5933 5934 bool 5935 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5936 std::string &SuggestedModifier) const override { 5937 // Strip off constraint modifiers. 5938 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5939 Constraint = Constraint.substr(1); 5940 5941 switch (Constraint[0]) { 5942 default: 5943 return true; 5944 case 'z': 5945 case 'r': { 5946 switch (Modifier) { 5947 case 'x': 5948 case 'w': 5949 // For now assume that the person knows what they're 5950 // doing with the modifier. 5951 return true; 5952 default: 5953 // By default an 'r' constraint will be in the 'x' 5954 // registers. 5955 if (Size == 64) 5956 return true; 5957 5958 SuggestedModifier = "w"; 5959 return false; 5960 } 5961 } 5962 } 5963 } 5964 5965 const char *getClobbers() const override { return ""; } 5966 5967 int getEHDataRegisterNumber(unsigned RegNo) const override { 5968 if (RegNo == 0) 5969 return 0; 5970 if (RegNo == 1) 5971 return 1; 5972 return -1; 5973 } 5974 }; 5975 5976 const char *const AArch64TargetInfo::GCCRegNames[] = { 5977 // 32-bit Integer registers 5978 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5979 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5980 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5981 5982 // 64-bit Integer registers 5983 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5984 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5985 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5986 5987 // 32-bit floating point regsisters 5988 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5989 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5990 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5991 5992 // 64-bit floating point regsisters 5993 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5994 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5995 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5996 5997 // Vector registers 5998 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5999 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6000 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6001 }; 6002 6003 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6004 return llvm::makeArrayRef(GCCRegNames); 6005 } 6006 6007 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6008 { { "w31" }, "wsp" }, 6009 { { "x29" }, "fp" }, 6010 { { "x30" }, "lr" }, 6011 { { "x31" }, "sp" }, 6012 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6013 // don't want to substitute one of these for a different-sized one. 6014 }; 6015 6016 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6017 return llvm::makeArrayRef(GCCRegAliases); 6018 } 6019 6020 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6021 #define BUILTIN(ID, TYPE, ATTRS) \ 6022 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6023 #include "clang/Basic/BuiltinsNEON.def" 6024 6025 #define BUILTIN(ID, TYPE, ATTRS) \ 6026 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6027 #include "clang/Basic/BuiltinsAArch64.def" 6028 }; 6029 6030 class AArch64leTargetInfo : public AArch64TargetInfo { 6031 void setDataLayout() override { 6032 if (getTriple().isOSBinFormatMachO()) 6033 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6034 else 6035 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6036 } 6037 6038 public: 6039 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6040 : AArch64TargetInfo(Triple, Opts) { 6041 BigEndian = false; 6042 } 6043 void getTargetDefines(const LangOptions &Opts, 6044 MacroBuilder &Builder) const override { 6045 Builder.defineMacro("__AARCH64EL__"); 6046 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6047 } 6048 }; 6049 6050 class AArch64beTargetInfo : public AArch64TargetInfo { 6051 void setDataLayout() override { 6052 assert(!getTriple().isOSBinFormatMachO()); 6053 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6054 } 6055 6056 public: 6057 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6058 : AArch64TargetInfo(Triple, Opts) {} 6059 void getTargetDefines(const LangOptions &Opts, 6060 MacroBuilder &Builder) const override { 6061 Builder.defineMacro("__AARCH64EB__"); 6062 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6063 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6064 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6065 } 6066 }; 6067 6068 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6069 protected: 6070 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6071 MacroBuilder &Builder) const override { 6072 Builder.defineMacro("__AARCH64_SIMD__"); 6073 Builder.defineMacro("__ARM64_ARCH_8__"); 6074 Builder.defineMacro("__ARM_NEON__"); 6075 Builder.defineMacro("__LITTLE_ENDIAN__"); 6076 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6077 Builder.defineMacro("__arm64", "1"); 6078 Builder.defineMacro("__arm64__", "1"); 6079 6080 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6081 } 6082 6083 public: 6084 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6085 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6086 Int64Type = SignedLongLong; 6087 WCharType = SignedInt; 6088 UseSignedCharForObjCBool = false; 6089 6090 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6091 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6092 6093 TheCXXABI.set(TargetCXXABI::iOS64); 6094 } 6095 6096 BuiltinVaListKind getBuiltinVaListKind() const override { 6097 return TargetInfo::CharPtrBuiltinVaList; 6098 } 6099 }; 6100 6101 // Hexagon abstract base class 6102 class HexagonTargetInfo : public TargetInfo { 6103 static const Builtin::Info BuiltinInfo[]; 6104 static const char * const GCCRegNames[]; 6105 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6106 std::string CPU; 6107 bool HasHVX, HasHVXDouble; 6108 6109 public: 6110 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6111 : TargetInfo(Triple) { 6112 BigEndian = false; 6113 // Specify the vector alignment explicitly. For v512x1, the calculated 6114 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6115 // the required minimum of 64 bytes. 6116 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6117 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6118 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6119 SizeType = UnsignedInt; 6120 PtrDiffType = SignedInt; 6121 IntPtrType = SignedInt; 6122 6123 // {} in inline assembly are packet specifiers, not assembly variant 6124 // specifiers. 6125 NoAsmVariants = true; 6126 6127 LargeArrayMinWidth = 64; 6128 LargeArrayAlign = 64; 6129 UseBitFieldTypeAlignment = true; 6130 ZeroLengthBitfieldBoundary = 32; 6131 HasHVX = HasHVXDouble = false; 6132 } 6133 6134 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6135 return llvm::makeArrayRef(BuiltinInfo, 6136 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6137 } 6138 6139 bool validateAsmConstraint(const char *&Name, 6140 TargetInfo::ConstraintInfo &Info) const override { 6141 switch (*Name) { 6142 case 'v': 6143 case 'q': 6144 if (HasHVX) { 6145 Info.setAllowsRegister(); 6146 return true; 6147 } 6148 break; 6149 case 's': 6150 // Relocatable constant. 6151 return true; 6152 } 6153 return false; 6154 } 6155 6156 void getTargetDefines(const LangOptions &Opts, 6157 MacroBuilder &Builder) const override; 6158 6159 bool isCLZForZeroUndef() const override { return false; } 6160 6161 bool hasFeature(StringRef Feature) const override { 6162 return llvm::StringSwitch<bool>(Feature) 6163 .Case("hexagon", true) 6164 .Case("hvx", HasHVX) 6165 .Case("hvx-double", HasHVXDouble) 6166 .Default(false); 6167 } 6168 6169 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6170 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6171 const override; 6172 6173 bool handleTargetFeatures(std::vector<std::string> &Features, 6174 DiagnosticsEngine &Diags) override; 6175 6176 BuiltinVaListKind getBuiltinVaListKind() const override { 6177 return TargetInfo::CharPtrBuiltinVaList; 6178 } 6179 ArrayRef<const char *> getGCCRegNames() const override; 6180 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6181 const char *getClobbers() const override { 6182 return ""; 6183 } 6184 6185 static const char *getHexagonCPUSuffix(StringRef Name) { 6186 return llvm::StringSwitch<const char*>(Name) 6187 .Case("hexagonv4", "4") 6188 .Case("hexagonv5", "5") 6189 .Case("hexagonv55", "55") 6190 .Case("hexagonv60", "60") 6191 .Default(nullptr); 6192 } 6193 6194 bool setCPU(const std::string &Name) override { 6195 if (!getHexagonCPUSuffix(Name)) 6196 return false; 6197 CPU = Name; 6198 return true; 6199 } 6200 6201 int getEHDataRegisterNumber(unsigned RegNo) const override { 6202 return RegNo < 2 ? RegNo : -1; 6203 } 6204 }; 6205 6206 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6207 MacroBuilder &Builder) const { 6208 Builder.defineMacro("__qdsp6__", "1"); 6209 Builder.defineMacro("__hexagon__", "1"); 6210 6211 if (CPU == "hexagonv4") { 6212 Builder.defineMacro("__HEXAGON_V4__"); 6213 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6214 if (Opts.HexagonQdsp6Compat) { 6215 Builder.defineMacro("__QDSP6_V4__"); 6216 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6217 } 6218 } else if (CPU == "hexagonv5") { 6219 Builder.defineMacro("__HEXAGON_V5__"); 6220 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6221 if(Opts.HexagonQdsp6Compat) { 6222 Builder.defineMacro("__QDSP6_V5__"); 6223 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6224 } 6225 } else if (CPU == "hexagonv55") { 6226 Builder.defineMacro("__HEXAGON_V55__"); 6227 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6228 Builder.defineMacro("__QDSP6_V55__"); 6229 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6230 } else if (CPU == "hexagonv60") { 6231 Builder.defineMacro("__HEXAGON_V60__"); 6232 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6233 Builder.defineMacro("__QDSP6_V60__"); 6234 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6235 } 6236 6237 if (hasFeature("hvx")) { 6238 Builder.defineMacro("__HVX__"); 6239 if (hasFeature("hvx-double")) 6240 Builder.defineMacro("__HVXDBL__"); 6241 } 6242 } 6243 6244 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6245 DiagnosticsEngine &Diags) { 6246 for (auto &F : Features) { 6247 if (F == "+hvx") 6248 HasHVX = true; 6249 else if (F == "-hvx") 6250 HasHVX = HasHVXDouble = false; 6251 else if (F == "+hvx-double") 6252 HasHVX = HasHVXDouble = true; 6253 else if (F == "-hvx-double") 6254 HasHVXDouble = false; 6255 } 6256 return true; 6257 } 6258 6259 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6260 DiagnosticsEngine &Diags, StringRef CPU, 6261 const std::vector<std::string> &FeaturesVec) const { 6262 // Default for v60: -hvx, -hvx-double. 6263 Features["hvx"] = false; 6264 Features["hvx-double"] = false; 6265 6266 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6267 } 6268 6269 6270 const char *const HexagonTargetInfo::GCCRegNames[] = { 6271 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6272 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6273 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6274 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6275 "p0", "p1", "p2", "p3", 6276 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6277 }; 6278 6279 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6280 return llvm::makeArrayRef(GCCRegNames); 6281 } 6282 6283 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6284 { { "sp" }, "r29" }, 6285 { { "fp" }, "r30" }, 6286 { { "lr" }, "r31" }, 6287 }; 6288 6289 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6290 return llvm::makeArrayRef(GCCRegAliases); 6291 } 6292 6293 6294 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6295 #define BUILTIN(ID, TYPE, ATTRS) \ 6296 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6297 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6298 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6299 #include "clang/Basic/BuiltinsHexagon.def" 6300 }; 6301 6302 class LanaiTargetInfo : public TargetInfo { 6303 // Class for Lanai (32-bit). 6304 // The CPU profiles supported by the Lanai backend 6305 enum CPUKind { 6306 CK_NONE, 6307 CK_V11, 6308 } CPU; 6309 6310 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6311 static const char *const GCCRegNames[]; 6312 6313 public: 6314 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6315 : TargetInfo(Triple) { 6316 // Description string has to be kept in sync with backend. 6317 resetDataLayout("E" // Big endian 6318 "-m:e" // ELF name manging 6319 "-p:32:32" // 32 bit pointers, 32 bit aligned 6320 "-i64:64" // 64 bit integers, 64 bit aligned 6321 "-a:0:32" // 32 bit alignment of objects of aggregate type 6322 "-n32" // 32 bit native integer width 6323 "-S64" // 64 bit natural stack alignment 6324 ); 6325 6326 // Setting RegParmMax equal to what mregparm was set to in the old 6327 // toolchain 6328 RegParmMax = 4; 6329 6330 // Set the default CPU to V11 6331 CPU = CK_V11; 6332 6333 // Temporary approach to make everything at least word-aligned and allow for 6334 // safely casting between pointers with different alignment requirements. 6335 // TODO: Remove this when there are no more cast align warnings on the 6336 // firmware. 6337 MinGlobalAlign = 32; 6338 } 6339 6340 void getTargetDefines(const LangOptions &Opts, 6341 MacroBuilder &Builder) const override { 6342 // Define __lanai__ when building for target lanai. 6343 Builder.defineMacro("__lanai__"); 6344 6345 // Set define for the CPU specified. 6346 switch (CPU) { 6347 case CK_V11: 6348 Builder.defineMacro("__LANAI_V11__"); 6349 break; 6350 case CK_NONE: 6351 llvm_unreachable("Unhandled target CPU"); 6352 } 6353 } 6354 6355 bool setCPU(const std::string &Name) override { 6356 CPU = llvm::StringSwitch<CPUKind>(Name) 6357 .Case("v11", CK_V11) 6358 .Default(CK_NONE); 6359 6360 return CPU != CK_NONE; 6361 } 6362 6363 bool hasFeature(StringRef Feature) const override { 6364 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6365 } 6366 6367 ArrayRef<const char *> getGCCRegNames() const override; 6368 6369 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6370 6371 BuiltinVaListKind getBuiltinVaListKind() const override { 6372 return TargetInfo::VoidPtrBuiltinVaList; 6373 } 6374 6375 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6376 6377 bool validateAsmConstraint(const char *&Name, 6378 TargetInfo::ConstraintInfo &info) const override { 6379 return false; 6380 } 6381 6382 const char *getClobbers() const override { return ""; } 6383 }; 6384 6385 const char *const LanaiTargetInfo::GCCRegNames[] = { 6386 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6387 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6388 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6389 6390 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6391 return llvm::makeArrayRef(GCCRegNames); 6392 } 6393 6394 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6395 {{"pc"}, "r2"}, 6396 {{"sp"}, "r4"}, 6397 {{"fp"}, "r5"}, 6398 {{"rv"}, "r8"}, 6399 {{"rr1"}, "r10"}, 6400 {{"rr2"}, "r11"}, 6401 {{"rca"}, "r15"}, 6402 }; 6403 6404 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6405 return llvm::makeArrayRef(GCCRegAliases); 6406 } 6407 6408 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6409 class SparcTargetInfo : public TargetInfo { 6410 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6411 static const char * const GCCRegNames[]; 6412 bool SoftFloat; 6413 public: 6414 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6415 : TargetInfo(Triple), SoftFloat(false) {} 6416 6417 int getEHDataRegisterNumber(unsigned RegNo) const override { 6418 if (RegNo == 0) return 24; 6419 if (RegNo == 1) return 25; 6420 return -1; 6421 } 6422 6423 bool handleTargetFeatures(std::vector<std::string> &Features, 6424 DiagnosticsEngine &Diags) override { 6425 // Check if software floating point is enabled 6426 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6427 if (Feature != Features.end()) { 6428 SoftFloat = true; 6429 } 6430 return true; 6431 } 6432 void getTargetDefines(const LangOptions &Opts, 6433 MacroBuilder &Builder) const override { 6434 DefineStd(Builder, "sparc", Opts); 6435 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6436 6437 if (SoftFloat) 6438 Builder.defineMacro("SOFT_FLOAT", "1"); 6439 } 6440 6441 bool hasFeature(StringRef Feature) const override { 6442 return llvm::StringSwitch<bool>(Feature) 6443 .Case("softfloat", SoftFloat) 6444 .Case("sparc", true) 6445 .Default(false); 6446 } 6447 6448 bool hasSjLjLowering() const override { 6449 return true; 6450 } 6451 6452 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6453 // FIXME: Implement! 6454 return None; 6455 } 6456 BuiltinVaListKind getBuiltinVaListKind() const override { 6457 return TargetInfo::VoidPtrBuiltinVaList; 6458 } 6459 ArrayRef<const char *> getGCCRegNames() const override; 6460 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6461 bool validateAsmConstraint(const char *&Name, 6462 TargetInfo::ConstraintInfo &info) const override { 6463 // FIXME: Implement! 6464 switch (*Name) { 6465 case 'I': // Signed 13-bit constant 6466 case 'J': // Zero 6467 case 'K': // 32-bit constant with the low 12 bits clear 6468 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6469 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6470 case 'N': // Same as 'K' but zext (required for SIMode) 6471 case 'O': // The constant 4096 6472 return true; 6473 } 6474 return false; 6475 } 6476 const char *getClobbers() const override { 6477 // FIXME: Implement! 6478 return ""; 6479 } 6480 6481 // No Sparc V7 for now, the backend doesn't support it anyway. 6482 enum CPUKind { 6483 CK_GENERIC, 6484 CK_V8, 6485 CK_SUPERSPARC, 6486 CK_SPARCLITE, 6487 CK_F934, 6488 CK_HYPERSPARC, 6489 CK_SPARCLITE86X, 6490 CK_SPARCLET, 6491 CK_TSC701, 6492 CK_V9, 6493 CK_ULTRASPARC, 6494 CK_ULTRASPARC3, 6495 CK_NIAGARA, 6496 CK_NIAGARA2, 6497 CK_NIAGARA3, 6498 CK_NIAGARA4, 6499 CK_MYRIAD2100, 6500 CK_MYRIAD2150, 6501 CK_MYRIAD2450, 6502 CK_LEON2, 6503 CK_LEON2_AT697E, 6504 CK_LEON2_AT697F, 6505 CK_LEON3, 6506 CK_LEON3_UT699, 6507 CK_LEON3_GR712RC, 6508 CK_LEON4, 6509 CK_LEON4_GR740 6510 } CPU = CK_GENERIC; 6511 6512 enum CPUGeneration { 6513 CG_V8, 6514 CG_V9, 6515 }; 6516 6517 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6518 switch (Kind) { 6519 case CK_GENERIC: 6520 case CK_V8: 6521 case CK_SUPERSPARC: 6522 case CK_SPARCLITE: 6523 case CK_F934: 6524 case CK_HYPERSPARC: 6525 case CK_SPARCLITE86X: 6526 case CK_SPARCLET: 6527 case CK_TSC701: 6528 case CK_MYRIAD2100: 6529 case CK_MYRIAD2150: 6530 case CK_MYRIAD2450: 6531 case CK_LEON2: 6532 case CK_LEON2_AT697E: 6533 case CK_LEON2_AT697F: 6534 case CK_LEON3: 6535 case CK_LEON3_UT699: 6536 case CK_LEON3_GR712RC: 6537 case CK_LEON4: 6538 case CK_LEON4_GR740: 6539 return CG_V8; 6540 case CK_V9: 6541 case CK_ULTRASPARC: 6542 case CK_ULTRASPARC3: 6543 case CK_NIAGARA: 6544 case CK_NIAGARA2: 6545 case CK_NIAGARA3: 6546 case CK_NIAGARA4: 6547 return CG_V9; 6548 } 6549 llvm_unreachable("Unexpected CPU kind"); 6550 } 6551 6552 CPUKind getCPUKind(StringRef Name) const { 6553 return llvm::StringSwitch<CPUKind>(Name) 6554 .Case("v8", CK_V8) 6555 .Case("supersparc", CK_SUPERSPARC) 6556 .Case("sparclite", CK_SPARCLITE) 6557 .Case("f934", CK_F934) 6558 .Case("hypersparc", CK_HYPERSPARC) 6559 .Case("sparclite86x", CK_SPARCLITE86X) 6560 .Case("sparclet", CK_SPARCLET) 6561 .Case("tsc701", CK_TSC701) 6562 .Case("v9", CK_V9) 6563 .Case("ultrasparc", CK_ULTRASPARC) 6564 .Case("ultrasparc3", CK_ULTRASPARC3) 6565 .Case("niagara", CK_NIAGARA) 6566 .Case("niagara2", CK_NIAGARA2) 6567 .Case("niagara3", CK_NIAGARA3) 6568 .Case("niagara4", CK_NIAGARA4) 6569 .Case("ma2100", CK_MYRIAD2100) 6570 .Case("ma2150", CK_MYRIAD2150) 6571 .Case("ma2450", CK_MYRIAD2450) 6572 // FIXME: the myriad2[.n] spellings are obsolete, 6573 // but a grace period is needed to allow updating dependent builds. 6574 .Case("myriad2", CK_MYRIAD2100) 6575 .Case("myriad2.1", CK_MYRIAD2100) 6576 .Case("myriad2.2", CK_MYRIAD2150) 6577 .Case("leon2", CK_LEON2) 6578 .Case("at697e", CK_LEON2_AT697E) 6579 .Case("at697f", CK_LEON2_AT697F) 6580 .Case("leon3", CK_LEON3) 6581 .Case("ut699", CK_LEON3_UT699) 6582 .Case("gr712rc", CK_LEON3_GR712RC) 6583 .Case("leon4", CK_LEON4) 6584 .Case("gr740", CK_LEON4_GR740) 6585 .Default(CK_GENERIC); 6586 } 6587 6588 bool setCPU(const std::string &Name) override { 6589 CPU = getCPUKind(Name); 6590 return CPU != CK_GENERIC; 6591 } 6592 }; 6593 6594 const char * const SparcTargetInfo::GCCRegNames[] = { 6595 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6596 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6597 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6598 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6599 }; 6600 6601 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6602 return llvm::makeArrayRef(GCCRegNames); 6603 } 6604 6605 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6606 { { "g0" }, "r0" }, 6607 { { "g1" }, "r1" }, 6608 { { "g2" }, "r2" }, 6609 { { "g3" }, "r3" }, 6610 { { "g4" }, "r4" }, 6611 { { "g5" }, "r5" }, 6612 { { "g6" }, "r6" }, 6613 { { "g7" }, "r7" }, 6614 { { "o0" }, "r8" }, 6615 { { "o1" }, "r9" }, 6616 { { "o2" }, "r10" }, 6617 { { "o3" }, "r11" }, 6618 { { "o4" }, "r12" }, 6619 { { "o5" }, "r13" }, 6620 { { "o6", "sp" }, "r14" }, 6621 { { "o7" }, "r15" }, 6622 { { "l0" }, "r16" }, 6623 { { "l1" }, "r17" }, 6624 { { "l2" }, "r18" }, 6625 { { "l3" }, "r19" }, 6626 { { "l4" }, "r20" }, 6627 { { "l5" }, "r21" }, 6628 { { "l6" }, "r22" }, 6629 { { "l7" }, "r23" }, 6630 { { "i0" }, "r24" }, 6631 { { "i1" }, "r25" }, 6632 { { "i2" }, "r26" }, 6633 { { "i3" }, "r27" }, 6634 { { "i4" }, "r28" }, 6635 { { "i5" }, "r29" }, 6636 { { "i6", "fp" }, "r30" }, 6637 { { "i7" }, "r31" }, 6638 }; 6639 6640 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6641 return llvm::makeArrayRef(GCCRegAliases); 6642 } 6643 6644 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6645 class SparcV8TargetInfo : public SparcTargetInfo { 6646 public: 6647 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6648 : SparcTargetInfo(Triple, Opts) { 6649 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6650 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6651 switch (getTriple().getOS()) { 6652 default: 6653 SizeType = UnsignedInt; 6654 IntPtrType = SignedInt; 6655 PtrDiffType = SignedInt; 6656 break; 6657 case llvm::Triple::NetBSD: 6658 case llvm::Triple::OpenBSD: 6659 SizeType = UnsignedLong; 6660 IntPtrType = SignedLong; 6661 PtrDiffType = SignedLong; 6662 break; 6663 } 6664 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6665 } 6666 6667 void getTargetDefines(const LangOptions &Opts, 6668 MacroBuilder &Builder) const override { 6669 SparcTargetInfo::getTargetDefines(Opts, Builder); 6670 switch (getCPUGeneration(CPU)) { 6671 case CG_V8: 6672 Builder.defineMacro("__sparcv8"); 6673 if (getTriple().getOS() != llvm::Triple::Solaris) 6674 Builder.defineMacro("__sparcv8__"); 6675 break; 6676 case CG_V9: 6677 Builder.defineMacro("__sparcv9"); 6678 if (getTriple().getOS() != llvm::Triple::Solaris) { 6679 Builder.defineMacro("__sparcv9__"); 6680 Builder.defineMacro("__sparc_v9__"); 6681 } 6682 break; 6683 } 6684 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6685 std::string MyriadArchValue, Myriad2Value; 6686 Builder.defineMacro("__sparc_v8__"); 6687 Builder.defineMacro("__leon__"); 6688 switch (CPU) { 6689 case CK_MYRIAD2150: 6690 MyriadArchValue = "__ma2150"; 6691 Myriad2Value = "2"; 6692 break; 6693 case CK_MYRIAD2450: 6694 MyriadArchValue = "__ma2450"; 6695 Myriad2Value = "2"; 6696 break; 6697 default: 6698 MyriadArchValue = "__ma2100"; 6699 Myriad2Value = "1"; 6700 break; 6701 } 6702 Builder.defineMacro(MyriadArchValue, "1"); 6703 Builder.defineMacro(MyriadArchValue+"__", "1"); 6704 Builder.defineMacro("__myriad2__", Myriad2Value); 6705 Builder.defineMacro("__myriad2", Myriad2Value); 6706 } 6707 } 6708 6709 bool hasSjLjLowering() const override { 6710 return true; 6711 } 6712 }; 6713 6714 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6715 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6716 public: 6717 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6718 : SparcV8TargetInfo(Triple, Opts) { 6719 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6720 BigEndian = false; 6721 } 6722 }; 6723 6724 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6725 class SparcV9TargetInfo : public SparcTargetInfo { 6726 public: 6727 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6728 : SparcTargetInfo(Triple, Opts) { 6729 // FIXME: Support Sparc quad-precision long double? 6730 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6731 // This is an LP64 platform. 6732 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6733 6734 // OpenBSD uses long long for int64_t and intmax_t. 6735 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6736 IntMaxType = SignedLongLong; 6737 else 6738 IntMaxType = SignedLong; 6739 Int64Type = IntMaxType; 6740 6741 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6742 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6743 LongDoubleWidth = 128; 6744 LongDoubleAlign = 128; 6745 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6746 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6747 } 6748 6749 void getTargetDefines(const LangOptions &Opts, 6750 MacroBuilder &Builder) const override { 6751 SparcTargetInfo::getTargetDefines(Opts, Builder); 6752 Builder.defineMacro("__sparcv9"); 6753 Builder.defineMacro("__arch64__"); 6754 // Solaris doesn't need these variants, but the BSDs do. 6755 if (getTriple().getOS() != llvm::Triple::Solaris) { 6756 Builder.defineMacro("__sparc64__"); 6757 Builder.defineMacro("__sparc_v9__"); 6758 Builder.defineMacro("__sparcv9__"); 6759 } 6760 } 6761 6762 bool setCPU(const std::string &Name) override { 6763 if (!SparcTargetInfo::setCPU(Name)) 6764 return false; 6765 return getCPUGeneration(CPU) == CG_V9; 6766 } 6767 }; 6768 6769 class SystemZTargetInfo : public TargetInfo { 6770 static const Builtin::Info BuiltinInfo[]; 6771 static const char *const GCCRegNames[]; 6772 std::string CPU; 6773 bool HasTransactionalExecution; 6774 bool HasVector; 6775 6776 public: 6777 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6778 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6779 HasVector(false) { 6780 IntMaxType = SignedLong; 6781 Int64Type = SignedLong; 6782 TLSSupported = true; 6783 IntWidth = IntAlign = 32; 6784 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6785 PointerWidth = PointerAlign = 64; 6786 LongDoubleWidth = 128; 6787 LongDoubleAlign = 64; 6788 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6789 DefaultAlignForAttributeAligned = 64; 6790 MinGlobalAlign = 16; 6791 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6792 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6793 } 6794 void getTargetDefines(const LangOptions &Opts, 6795 MacroBuilder &Builder) const override { 6796 Builder.defineMacro("__s390__"); 6797 Builder.defineMacro("__s390x__"); 6798 Builder.defineMacro("__zarch__"); 6799 Builder.defineMacro("__LONG_DOUBLE_128__"); 6800 6801 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6802 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6803 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6804 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6805 6806 if (HasTransactionalExecution) 6807 Builder.defineMacro("__HTM__"); 6808 if (Opts.ZVector) 6809 Builder.defineMacro("__VEC__", "10301"); 6810 } 6811 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6812 return llvm::makeArrayRef(BuiltinInfo, 6813 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6814 } 6815 6816 ArrayRef<const char *> getGCCRegNames() const override; 6817 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6818 // No aliases. 6819 return None; 6820 } 6821 bool validateAsmConstraint(const char *&Name, 6822 TargetInfo::ConstraintInfo &info) const override; 6823 const char *getClobbers() const override { 6824 // FIXME: Is this really right? 6825 return ""; 6826 } 6827 BuiltinVaListKind getBuiltinVaListKind() const override { 6828 return TargetInfo::SystemZBuiltinVaList; 6829 } 6830 bool setCPU(const std::string &Name) override { 6831 CPU = Name; 6832 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6833 .Case("z10", true) 6834 .Case("z196", true) 6835 .Case("zEC12", true) 6836 .Case("z13", true) 6837 .Default(false); 6838 6839 return CPUKnown; 6840 } 6841 bool 6842 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6843 StringRef CPU, 6844 const std::vector<std::string> &FeaturesVec) const override { 6845 if (CPU == "zEC12") 6846 Features["transactional-execution"] = true; 6847 if (CPU == "z13") { 6848 Features["transactional-execution"] = true; 6849 Features["vector"] = true; 6850 } 6851 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6852 } 6853 6854 bool handleTargetFeatures(std::vector<std::string> &Features, 6855 DiagnosticsEngine &Diags) override { 6856 HasTransactionalExecution = false; 6857 for (const auto &Feature : Features) { 6858 if (Feature == "+transactional-execution") 6859 HasTransactionalExecution = true; 6860 else if (Feature == "+vector") 6861 HasVector = true; 6862 } 6863 // If we use the vector ABI, vector types are 64-bit aligned. 6864 if (HasVector) { 6865 MaxVectorAlign = 64; 6866 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6867 "-v128:64-a:8:16-n32:64"); 6868 } 6869 return true; 6870 } 6871 6872 bool hasFeature(StringRef Feature) const override { 6873 return llvm::StringSwitch<bool>(Feature) 6874 .Case("systemz", true) 6875 .Case("htm", HasTransactionalExecution) 6876 .Case("vx", HasVector) 6877 .Default(false); 6878 } 6879 6880 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6881 switch (CC) { 6882 case CC_C: 6883 case CC_Swift: 6884 return CCCR_OK; 6885 default: 6886 return CCCR_Warning; 6887 } 6888 } 6889 6890 StringRef getABI() const override { 6891 if (HasVector) 6892 return "vector"; 6893 return ""; 6894 } 6895 6896 bool useFloat128ManglingForLongDouble() const override { 6897 return true; 6898 } 6899 }; 6900 6901 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6902 #define BUILTIN(ID, TYPE, ATTRS) \ 6903 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6904 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6905 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6906 #include "clang/Basic/BuiltinsSystemZ.def" 6907 }; 6908 6909 const char *const SystemZTargetInfo::GCCRegNames[] = { 6910 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6911 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6912 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6913 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6914 }; 6915 6916 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6917 return llvm::makeArrayRef(GCCRegNames); 6918 } 6919 6920 bool SystemZTargetInfo:: 6921 validateAsmConstraint(const char *&Name, 6922 TargetInfo::ConstraintInfo &Info) const { 6923 switch (*Name) { 6924 default: 6925 return false; 6926 6927 case 'a': // Address register 6928 case 'd': // Data register (equivalent to 'r') 6929 case 'f': // Floating-point register 6930 Info.setAllowsRegister(); 6931 return true; 6932 6933 case 'I': // Unsigned 8-bit constant 6934 case 'J': // Unsigned 12-bit constant 6935 case 'K': // Signed 16-bit constant 6936 case 'L': // Signed 20-bit displacement (on all targets we support) 6937 case 'M': // 0x7fffffff 6938 return true; 6939 6940 case 'Q': // Memory with base and unsigned 12-bit displacement 6941 case 'R': // Likewise, plus an index 6942 case 'S': // Memory with base and signed 20-bit displacement 6943 case 'T': // Likewise, plus an index 6944 Info.setAllowsMemory(); 6945 return true; 6946 } 6947 } 6948 6949 class MSP430TargetInfo : public TargetInfo { 6950 static const char *const GCCRegNames[]; 6951 6952 public: 6953 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6954 : TargetInfo(Triple) { 6955 BigEndian = false; 6956 TLSSupported = false; 6957 IntWidth = 16; 6958 IntAlign = 16; 6959 LongWidth = 32; 6960 LongLongWidth = 64; 6961 LongAlign = LongLongAlign = 16; 6962 PointerWidth = 16; 6963 PointerAlign = 16; 6964 SuitableAlign = 16; 6965 SizeType = UnsignedInt; 6966 IntMaxType = SignedLongLong; 6967 IntPtrType = SignedInt; 6968 PtrDiffType = SignedInt; 6969 SigAtomicType = SignedLong; 6970 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6971 } 6972 void getTargetDefines(const LangOptions &Opts, 6973 MacroBuilder &Builder) const override { 6974 Builder.defineMacro("MSP430"); 6975 Builder.defineMacro("__MSP430__"); 6976 // FIXME: defines for different 'flavours' of MCU 6977 } 6978 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6979 // FIXME: Implement. 6980 return None; 6981 } 6982 bool hasFeature(StringRef Feature) const override { 6983 return Feature == "msp430"; 6984 } 6985 ArrayRef<const char *> getGCCRegNames() const override; 6986 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6987 // No aliases. 6988 return None; 6989 } 6990 bool validateAsmConstraint(const char *&Name, 6991 TargetInfo::ConstraintInfo &info) const override { 6992 // FIXME: implement 6993 switch (*Name) { 6994 case 'K': // the constant 1 6995 case 'L': // constant -1^20 .. 1^19 6996 case 'M': // constant 1-4: 6997 return true; 6998 } 6999 // No target constraints for now. 7000 return false; 7001 } 7002 const char *getClobbers() const override { 7003 // FIXME: Is this really right? 7004 return ""; 7005 } 7006 BuiltinVaListKind getBuiltinVaListKind() const override { 7007 // FIXME: implement 7008 return TargetInfo::CharPtrBuiltinVaList; 7009 } 7010 }; 7011 7012 const char *const MSP430TargetInfo::GCCRegNames[] = { 7013 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7014 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7015 7016 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7017 return llvm::makeArrayRef(GCCRegNames); 7018 } 7019 7020 // LLVM and Clang cannot be used directly to output native binaries for 7021 // target, but is used to compile C code to llvm bitcode with correct 7022 // type and alignment information. 7023 // 7024 // TCE uses the llvm bitcode as input and uses it for generating customized 7025 // target processor and program binary. TCE co-design environment is 7026 // publicly available in http://tce.cs.tut.fi 7027 7028 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7029 3, // opencl_global 7030 4, // opencl_local 7031 5, // opencl_constant 7032 // FIXME: generic has to be added to the target 7033 0, // opencl_generic 7034 0, // cuda_device 7035 0, // cuda_constant 7036 0 // cuda_shared 7037 }; 7038 7039 class TCETargetInfo : public TargetInfo { 7040 public: 7041 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7042 : TargetInfo(Triple) { 7043 TLSSupported = false; 7044 IntWidth = 32; 7045 LongWidth = LongLongWidth = 32; 7046 PointerWidth = 32; 7047 IntAlign = 32; 7048 LongAlign = LongLongAlign = 32; 7049 PointerAlign = 32; 7050 SuitableAlign = 32; 7051 SizeType = UnsignedInt; 7052 IntMaxType = SignedLong; 7053 IntPtrType = SignedInt; 7054 PtrDiffType = SignedInt; 7055 FloatWidth = 32; 7056 FloatAlign = 32; 7057 DoubleWidth = 32; 7058 DoubleAlign = 32; 7059 LongDoubleWidth = 32; 7060 LongDoubleAlign = 32; 7061 FloatFormat = &llvm::APFloat::IEEEsingle; 7062 DoubleFormat = &llvm::APFloat::IEEEsingle; 7063 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 7064 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 7065 "-f64:32-v64:32-v128:32-a:0:32-n32"); 7066 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7067 UseAddrSpaceMapMangling = true; 7068 } 7069 7070 void getTargetDefines(const LangOptions &Opts, 7071 MacroBuilder &Builder) const override { 7072 DefineStd(Builder, "tce", Opts); 7073 Builder.defineMacro("__TCE__"); 7074 Builder.defineMacro("__TCE_V1__"); 7075 } 7076 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7077 7078 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7079 const char *getClobbers() const override { return ""; } 7080 BuiltinVaListKind getBuiltinVaListKind() const override { 7081 return TargetInfo::VoidPtrBuiltinVaList; 7082 } 7083 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7084 bool validateAsmConstraint(const char *&Name, 7085 TargetInfo::ConstraintInfo &info) const override { 7086 return true; 7087 } 7088 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7089 return None; 7090 } 7091 }; 7092 7093 class BPFTargetInfo : public TargetInfo { 7094 public: 7095 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7096 : TargetInfo(Triple) { 7097 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7098 SizeType = UnsignedLong; 7099 PtrDiffType = SignedLong; 7100 IntPtrType = SignedLong; 7101 IntMaxType = SignedLong; 7102 Int64Type = SignedLong; 7103 RegParmMax = 5; 7104 if (Triple.getArch() == llvm::Triple::bpfeb) { 7105 BigEndian = true; 7106 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7107 } else { 7108 BigEndian = false; 7109 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7110 } 7111 MaxAtomicPromoteWidth = 64; 7112 MaxAtomicInlineWidth = 64; 7113 TLSSupported = false; 7114 } 7115 void getTargetDefines(const LangOptions &Opts, 7116 MacroBuilder &Builder) const override { 7117 DefineStd(Builder, "bpf", Opts); 7118 Builder.defineMacro("__BPF__"); 7119 } 7120 bool hasFeature(StringRef Feature) const override { 7121 return Feature == "bpf"; 7122 } 7123 7124 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7125 const char *getClobbers() const override { 7126 return ""; 7127 } 7128 BuiltinVaListKind getBuiltinVaListKind() const override { 7129 return TargetInfo::VoidPtrBuiltinVaList; 7130 } 7131 ArrayRef<const char *> getGCCRegNames() const override { 7132 return None; 7133 } 7134 bool validateAsmConstraint(const char *&Name, 7135 TargetInfo::ConstraintInfo &info) const override { 7136 return true; 7137 } 7138 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7139 return None; 7140 } 7141 }; 7142 7143 class MipsTargetInfo : public TargetInfo { 7144 void setDataLayout() { 7145 StringRef Layout; 7146 7147 if (ABI == "o32") 7148 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7149 else if (ABI == "n32") 7150 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7151 else if (ABI == "n64") 7152 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7153 else 7154 llvm_unreachable("Invalid ABI"); 7155 7156 if (BigEndian) 7157 resetDataLayout(("E-" + Layout).str()); 7158 else 7159 resetDataLayout(("e-" + Layout).str()); 7160 } 7161 7162 7163 static const Builtin::Info BuiltinInfo[]; 7164 std::string CPU; 7165 bool IsMips16; 7166 bool IsMicromips; 7167 bool IsNan2008; 7168 bool IsSingleFloat; 7169 enum MipsFloatABI { 7170 HardFloat, SoftFloat 7171 } FloatABI; 7172 enum DspRevEnum { 7173 NoDSP, DSP1, DSP2 7174 } DspRev; 7175 bool HasMSA; 7176 7177 protected: 7178 bool HasFP64; 7179 std::string ABI; 7180 7181 public: 7182 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7183 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7184 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7185 DspRev(NoDSP), HasMSA(false), HasFP64(false) { 7186 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7187 BigEndian = getTriple().getArch() == llvm::Triple::mips || 7188 getTriple().getArch() == llvm::Triple::mips64; 7189 7190 setABI((getTriple().getArch() == llvm::Triple::mips || 7191 getTriple().getArch() == llvm::Triple::mipsel) 7192 ? "o32" 7193 : "n64"); 7194 7195 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7196 } 7197 7198 bool isNaN2008Default() const { 7199 return CPU == "mips32r6" || CPU == "mips64r6"; 7200 } 7201 7202 bool isFP64Default() const { 7203 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7204 } 7205 7206 bool isNan2008() const override { 7207 return IsNan2008; 7208 } 7209 7210 bool processorSupportsGPR64() const { 7211 return llvm::StringSwitch<bool>(CPU) 7212 .Case("mips3", true) 7213 .Case("mips4", true) 7214 .Case("mips5", true) 7215 .Case("mips64", true) 7216 .Case("mips64r2", true) 7217 .Case("mips64r3", true) 7218 .Case("mips64r5", true) 7219 .Case("mips64r6", true) 7220 .Case("octeon", true) 7221 .Default(false); 7222 return false; 7223 } 7224 7225 StringRef getABI() const override { return ABI; } 7226 bool setABI(const std::string &Name) override { 7227 if (Name == "o32") { 7228 setO32ABITypes(); 7229 ABI = Name; 7230 return true; 7231 } 7232 7233 if (Name == "n32") { 7234 setN32ABITypes(); 7235 ABI = Name; 7236 return true; 7237 } 7238 if (Name == "n64") { 7239 setN64ABITypes(); 7240 ABI = Name; 7241 return true; 7242 } 7243 return false; 7244 } 7245 7246 void setO32ABITypes() { 7247 Int64Type = SignedLongLong; 7248 IntMaxType = Int64Type; 7249 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7250 LongDoubleWidth = LongDoubleAlign = 64; 7251 LongWidth = LongAlign = 32; 7252 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7253 PointerWidth = PointerAlign = 32; 7254 PtrDiffType = SignedInt; 7255 SizeType = UnsignedInt; 7256 SuitableAlign = 64; 7257 } 7258 7259 void setN32N64ABITypes() { 7260 LongDoubleWidth = LongDoubleAlign = 128; 7261 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7262 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7263 LongDoubleWidth = LongDoubleAlign = 64; 7264 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7265 } 7266 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7267 SuitableAlign = 128; 7268 } 7269 7270 void setN64ABITypes() { 7271 setN32N64ABITypes(); 7272 Int64Type = SignedLong; 7273 IntMaxType = Int64Type; 7274 LongWidth = LongAlign = 64; 7275 PointerWidth = PointerAlign = 64; 7276 PtrDiffType = SignedLong; 7277 SizeType = UnsignedLong; 7278 } 7279 7280 void setN32ABITypes() { 7281 setN32N64ABITypes(); 7282 Int64Type = SignedLongLong; 7283 IntMaxType = Int64Type; 7284 LongWidth = LongAlign = 32; 7285 PointerWidth = PointerAlign = 32; 7286 PtrDiffType = SignedInt; 7287 SizeType = UnsignedInt; 7288 } 7289 7290 bool setCPU(const std::string &Name) override { 7291 CPU = Name; 7292 return llvm::StringSwitch<bool>(Name) 7293 .Case("mips1", true) 7294 .Case("mips2", true) 7295 .Case("mips3", true) 7296 .Case("mips4", true) 7297 .Case("mips5", true) 7298 .Case("mips32", true) 7299 .Case("mips32r2", true) 7300 .Case("mips32r3", true) 7301 .Case("mips32r5", true) 7302 .Case("mips32r6", true) 7303 .Case("mips64", true) 7304 .Case("mips64r2", true) 7305 .Case("mips64r3", true) 7306 .Case("mips64r5", true) 7307 .Case("mips64r6", true) 7308 .Case("octeon", true) 7309 .Case("p5600", true) 7310 .Default(false); 7311 } 7312 const std::string& getCPU() const { return CPU; } 7313 bool 7314 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7315 StringRef CPU, 7316 const std::vector<std::string> &FeaturesVec) const override { 7317 if (CPU.empty()) 7318 CPU = getCPU(); 7319 if (CPU == "octeon") 7320 Features["mips64r2"] = Features["cnmips"] = true; 7321 else 7322 Features[CPU] = true; 7323 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7324 } 7325 7326 void getTargetDefines(const LangOptions &Opts, 7327 MacroBuilder &Builder) const override { 7328 if (BigEndian) { 7329 DefineStd(Builder, "MIPSEB", Opts); 7330 Builder.defineMacro("_MIPSEB"); 7331 } else { 7332 DefineStd(Builder, "MIPSEL", Opts); 7333 Builder.defineMacro("_MIPSEL"); 7334 } 7335 7336 Builder.defineMacro("__mips__"); 7337 Builder.defineMacro("_mips"); 7338 if (Opts.GNUMode) 7339 Builder.defineMacro("mips"); 7340 7341 if (ABI == "o32") { 7342 Builder.defineMacro("__mips", "32"); 7343 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7344 } else { 7345 Builder.defineMacro("__mips", "64"); 7346 Builder.defineMacro("__mips64"); 7347 Builder.defineMacro("__mips64__"); 7348 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7349 } 7350 7351 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7352 .Cases("mips32", "mips64", "1") 7353 .Cases("mips32r2", "mips64r2", "2") 7354 .Cases("mips32r3", "mips64r3", "3") 7355 .Cases("mips32r5", "mips64r5", "5") 7356 .Cases("mips32r6", "mips64r6", "6") 7357 .Default(""); 7358 if (!ISARev.empty()) 7359 Builder.defineMacro("__mips_isa_rev", ISARev); 7360 7361 if (ABI == "o32") { 7362 Builder.defineMacro("__mips_o32"); 7363 Builder.defineMacro("_ABIO32", "1"); 7364 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7365 } else if (ABI == "n32") { 7366 Builder.defineMacro("__mips_n32"); 7367 Builder.defineMacro("_ABIN32", "2"); 7368 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7369 } else if (ABI == "n64") { 7370 Builder.defineMacro("__mips_n64"); 7371 Builder.defineMacro("_ABI64", "3"); 7372 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7373 } else 7374 llvm_unreachable("Invalid ABI."); 7375 7376 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7377 7378 switch (FloatABI) { 7379 case HardFloat: 7380 Builder.defineMacro("__mips_hard_float", Twine(1)); 7381 break; 7382 case SoftFloat: 7383 Builder.defineMacro("__mips_soft_float", Twine(1)); 7384 break; 7385 } 7386 7387 if (IsSingleFloat) 7388 Builder.defineMacro("__mips_single_float", Twine(1)); 7389 7390 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7391 Builder.defineMacro("_MIPS_FPSET", 7392 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7393 7394 if (IsMips16) 7395 Builder.defineMacro("__mips16", Twine(1)); 7396 7397 if (IsMicromips) 7398 Builder.defineMacro("__mips_micromips", Twine(1)); 7399 7400 if (IsNan2008) 7401 Builder.defineMacro("__mips_nan2008", Twine(1)); 7402 7403 switch (DspRev) { 7404 default: 7405 break; 7406 case DSP1: 7407 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7408 Builder.defineMacro("__mips_dsp", Twine(1)); 7409 break; 7410 case DSP2: 7411 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7412 Builder.defineMacro("__mips_dspr2", Twine(1)); 7413 Builder.defineMacro("__mips_dsp", Twine(1)); 7414 break; 7415 } 7416 7417 if (HasMSA) 7418 Builder.defineMacro("__mips_msa", Twine(1)); 7419 7420 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7421 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7422 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7423 7424 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7425 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7426 7427 // These shouldn't be defined for MIPS-I but there's no need to check 7428 // for that since MIPS-I isn't supported. 7429 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7430 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7431 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7432 7433 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7434 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7435 // the instructions exist but using them violates the ABI since they 7436 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7437 if (ABI == "n32" || ABI == "n64") 7438 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7439 } 7440 7441 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7442 return llvm::makeArrayRef(BuiltinInfo, 7443 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7444 } 7445 bool hasFeature(StringRef Feature) const override { 7446 return llvm::StringSwitch<bool>(Feature) 7447 .Case("mips", true) 7448 .Case("fp64", HasFP64) 7449 .Default(false); 7450 } 7451 BuiltinVaListKind getBuiltinVaListKind() const override { 7452 return TargetInfo::VoidPtrBuiltinVaList; 7453 } 7454 ArrayRef<const char *> getGCCRegNames() const override { 7455 static const char *const GCCRegNames[] = { 7456 // CPU register names 7457 // Must match second column of GCCRegAliases 7458 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7459 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7460 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7461 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7462 // Floating point register names 7463 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7464 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7465 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7466 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7467 // Hi/lo and condition register names 7468 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7469 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7470 "$ac3hi","$ac3lo", 7471 // MSA register names 7472 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7473 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7474 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7475 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7476 // MSA control register names 7477 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7478 "$msarequest", "$msamap", "$msaunmap" 7479 }; 7480 return llvm::makeArrayRef(GCCRegNames); 7481 } 7482 bool validateAsmConstraint(const char *&Name, 7483 TargetInfo::ConstraintInfo &Info) const override { 7484 switch (*Name) { 7485 default: 7486 return false; 7487 case 'r': // CPU registers. 7488 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7489 case 'y': // Equivalent to "r", backward compatibility only. 7490 case 'f': // floating-point registers. 7491 case 'c': // $25 for indirect jumps 7492 case 'l': // lo register 7493 case 'x': // hilo register pair 7494 Info.setAllowsRegister(); 7495 return true; 7496 case 'I': // Signed 16-bit constant 7497 case 'J': // Integer 0 7498 case 'K': // Unsigned 16-bit constant 7499 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7500 case 'M': // Constants not loadable via lui, addiu, or ori 7501 case 'N': // Constant -1 to -65535 7502 case 'O': // A signed 15-bit constant 7503 case 'P': // A constant between 1 go 65535 7504 return true; 7505 case 'R': // An address that can be used in a non-macro load or store 7506 Info.setAllowsMemory(); 7507 return true; 7508 case 'Z': 7509 if (Name[1] == 'C') { // An address usable by ll, and sc. 7510 Info.setAllowsMemory(); 7511 Name++; // Skip over 'Z'. 7512 return true; 7513 } 7514 return false; 7515 } 7516 } 7517 7518 std::string convertConstraint(const char *&Constraint) const override { 7519 std::string R; 7520 switch (*Constraint) { 7521 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7522 if (Constraint[1] == 'C') { 7523 R = std::string("^") + std::string(Constraint, 2); 7524 Constraint++; 7525 return R; 7526 } 7527 break; 7528 } 7529 return TargetInfo::convertConstraint(Constraint); 7530 } 7531 7532 const char *getClobbers() const override { 7533 // In GCC, $1 is not widely used in generated code (it's used only in a few 7534 // specific situations), so there is no real need for users to add it to 7535 // the clobbers list if they want to use it in their inline assembly code. 7536 // 7537 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7538 // code generation, so using it in inline assembly without adding it to the 7539 // clobbers list can cause conflicts between the inline assembly code and 7540 // the surrounding generated code. 7541 // 7542 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7543 // operands, which will conflict with the ".set at" assembler option (which 7544 // we use only for inline assembly, in order to maintain compatibility with 7545 // GCC) and will also conflict with the user's usage of $1. 7546 // 7547 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7548 // register for generated code is to automatically clobber $1 for all inline 7549 // assembly code. 7550 // 7551 // FIXME: We should automatically clobber $1 only for inline assembly code 7552 // which actually uses it. This would allow LLVM to use $1 for inline 7553 // assembly operands if the user's assembly code doesn't use it. 7554 return "~{$1}"; 7555 } 7556 7557 bool handleTargetFeatures(std::vector<std::string> &Features, 7558 DiagnosticsEngine &Diags) override { 7559 IsMips16 = false; 7560 IsMicromips = false; 7561 IsNan2008 = isNaN2008Default(); 7562 IsSingleFloat = false; 7563 FloatABI = HardFloat; 7564 DspRev = NoDSP; 7565 HasFP64 = isFP64Default(); 7566 7567 for (const auto &Feature : Features) { 7568 if (Feature == "+single-float") 7569 IsSingleFloat = true; 7570 else if (Feature == "+soft-float") 7571 FloatABI = SoftFloat; 7572 else if (Feature == "+mips16") 7573 IsMips16 = true; 7574 else if (Feature == "+micromips") 7575 IsMicromips = true; 7576 else if (Feature == "+dsp") 7577 DspRev = std::max(DspRev, DSP1); 7578 else if (Feature == "+dspr2") 7579 DspRev = std::max(DspRev, DSP2); 7580 else if (Feature == "+msa") 7581 HasMSA = true; 7582 else if (Feature == "+fp64") 7583 HasFP64 = true; 7584 else if (Feature == "-fp64") 7585 HasFP64 = false; 7586 else if (Feature == "+nan2008") 7587 IsNan2008 = true; 7588 else if (Feature == "-nan2008") 7589 IsNan2008 = false; 7590 } 7591 7592 setDataLayout(); 7593 7594 return true; 7595 } 7596 7597 int getEHDataRegisterNumber(unsigned RegNo) const override { 7598 if (RegNo == 0) return 4; 7599 if (RegNo == 1) return 5; 7600 return -1; 7601 } 7602 7603 bool isCLZForZeroUndef() const override { return false; } 7604 7605 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7606 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7607 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7608 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7609 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7610 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7611 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7612 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7613 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7614 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7615 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7616 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7617 {{"ra"}, "$31"}}; 7618 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7619 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7620 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7621 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7622 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7623 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7624 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7625 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7626 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7627 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7628 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7629 {{"ra"}, "$31"}}; 7630 if (ABI == "o32") 7631 return llvm::makeArrayRef(O32RegAliases); 7632 return llvm::makeArrayRef(NewABIRegAliases); 7633 } 7634 7635 bool hasInt128Type() const override { 7636 return ABI == "n32" || ABI == "n64"; 7637 } 7638 7639 bool validateTarget(DiagnosticsEngine &Diags) const override { 7640 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7641 // this yet. It's better to fail here than on the backend assertion. 7642 if (processorSupportsGPR64() && ABI == "o32") { 7643 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7644 return false; 7645 } 7646 7647 // 64-bit ABI's require 64-bit CPU's. 7648 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 7649 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7650 return false; 7651 } 7652 7653 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 7654 // can't handle this yet. It's better to fail here than on the 7655 // backend assertion. 7656 if ((getTriple().getArch() == llvm::Triple::mips64 || 7657 getTriple().getArch() == llvm::Triple::mips64el) && 7658 ABI == "o32") { 7659 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7660 << ABI << getTriple().str(); 7661 return false; 7662 } 7663 7664 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 7665 // can't handle this yet. It's better to fail here than on the 7666 // backend assertion. 7667 if ((getTriple().getArch() == llvm::Triple::mips || 7668 getTriple().getArch() == llvm::Triple::mipsel) && 7669 (ABI == "n32" || ABI == "n64")) { 7670 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7671 << ABI << getTriple().str(); 7672 return false; 7673 } 7674 7675 return true; 7676 } 7677 }; 7678 7679 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7680 #define BUILTIN(ID, TYPE, ATTRS) \ 7681 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7682 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7683 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7684 #include "clang/Basic/BuiltinsMips.def" 7685 }; 7686 7687 class PNaClTargetInfo : public TargetInfo { 7688 public: 7689 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7690 : TargetInfo(Triple) { 7691 BigEndian = false; 7692 this->LongAlign = 32; 7693 this->LongWidth = 32; 7694 this->PointerAlign = 32; 7695 this->PointerWidth = 32; 7696 this->IntMaxType = TargetInfo::SignedLongLong; 7697 this->Int64Type = TargetInfo::SignedLongLong; 7698 this->DoubleAlign = 64; 7699 this->LongDoubleWidth = 64; 7700 this->LongDoubleAlign = 64; 7701 this->SizeType = TargetInfo::UnsignedInt; 7702 this->PtrDiffType = TargetInfo::SignedInt; 7703 this->IntPtrType = TargetInfo::SignedInt; 7704 this->RegParmMax = 0; // Disallow regparm 7705 } 7706 7707 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7708 Builder.defineMacro("__le32__"); 7709 Builder.defineMacro("__pnacl__"); 7710 } 7711 void getTargetDefines(const LangOptions &Opts, 7712 MacroBuilder &Builder) const override { 7713 getArchDefines(Opts, Builder); 7714 } 7715 bool hasFeature(StringRef Feature) const override { 7716 return Feature == "pnacl"; 7717 } 7718 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7719 BuiltinVaListKind getBuiltinVaListKind() const override { 7720 return TargetInfo::PNaClABIBuiltinVaList; 7721 } 7722 ArrayRef<const char *> getGCCRegNames() const override; 7723 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7724 bool validateAsmConstraint(const char *&Name, 7725 TargetInfo::ConstraintInfo &Info) const override { 7726 return false; 7727 } 7728 7729 const char *getClobbers() const override { 7730 return ""; 7731 } 7732 }; 7733 7734 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7735 return None; 7736 } 7737 7738 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7739 return None; 7740 } 7741 7742 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7743 class NaClMips32TargetInfo : public MipsTargetInfo { 7744 public: 7745 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7746 : MipsTargetInfo(Triple, Opts) {} 7747 7748 BuiltinVaListKind getBuiltinVaListKind() const override { 7749 return TargetInfo::PNaClABIBuiltinVaList; 7750 } 7751 }; 7752 7753 class Le64TargetInfo : public TargetInfo { 7754 static const Builtin::Info BuiltinInfo[]; 7755 7756 public: 7757 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7758 : TargetInfo(Triple) { 7759 BigEndian = false; 7760 NoAsmVariants = true; 7761 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7762 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7763 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7764 } 7765 7766 void getTargetDefines(const LangOptions &Opts, 7767 MacroBuilder &Builder) const override { 7768 DefineStd(Builder, "unix", Opts); 7769 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7770 Builder.defineMacro("__ELF__"); 7771 } 7772 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7773 return llvm::makeArrayRef(BuiltinInfo, 7774 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7775 } 7776 BuiltinVaListKind getBuiltinVaListKind() const override { 7777 return TargetInfo::PNaClABIBuiltinVaList; 7778 } 7779 const char *getClobbers() const override { return ""; } 7780 ArrayRef<const char *> getGCCRegNames() const override { 7781 return None; 7782 } 7783 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7784 return None; 7785 } 7786 bool validateAsmConstraint(const char *&Name, 7787 TargetInfo::ConstraintInfo &Info) const override { 7788 return false; 7789 } 7790 7791 bool hasProtectedVisibility() const override { return false; } 7792 }; 7793 7794 class WebAssemblyTargetInfo : public TargetInfo { 7795 static const Builtin::Info BuiltinInfo[]; 7796 7797 enum SIMDEnum { 7798 NoSIMD, 7799 SIMD128, 7800 } SIMDLevel; 7801 7802 public: 7803 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7804 : TargetInfo(T), SIMDLevel(NoSIMD) { 7805 BigEndian = false; 7806 NoAsmVariants = true; 7807 SuitableAlign = 128; 7808 LargeArrayMinWidth = 128; 7809 LargeArrayAlign = 128; 7810 SimdDefaultAlign = 128; 7811 SigAtomicType = SignedLong; 7812 LongDoubleWidth = LongDoubleAlign = 128; 7813 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7814 } 7815 7816 protected: 7817 void getTargetDefines(const LangOptions &Opts, 7818 MacroBuilder &Builder) const override { 7819 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7820 if (SIMDLevel >= SIMD128) 7821 Builder.defineMacro("__wasm_simd128__"); 7822 } 7823 7824 private: 7825 bool 7826 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7827 StringRef CPU, 7828 const std::vector<std::string> &FeaturesVec) const override { 7829 if (CPU == "bleeding-edge") 7830 Features["simd128"] = true; 7831 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7832 } 7833 bool hasFeature(StringRef Feature) const final { 7834 return llvm::StringSwitch<bool>(Feature) 7835 .Case("simd128", SIMDLevel >= SIMD128) 7836 .Default(false); 7837 } 7838 bool handleTargetFeatures(std::vector<std::string> &Features, 7839 DiagnosticsEngine &Diags) final { 7840 for (const auto &Feature : Features) { 7841 if (Feature == "+simd128") { 7842 SIMDLevel = std::max(SIMDLevel, SIMD128); 7843 continue; 7844 } 7845 if (Feature == "-simd128") { 7846 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7847 continue; 7848 } 7849 7850 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7851 << "-target-feature"; 7852 return false; 7853 } 7854 return true; 7855 } 7856 bool setCPU(const std::string &Name) final { 7857 return llvm::StringSwitch<bool>(Name) 7858 .Case("mvp", true) 7859 .Case("bleeding-edge", true) 7860 .Case("generic", true) 7861 .Default(false); 7862 } 7863 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7864 return llvm::makeArrayRef(BuiltinInfo, 7865 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7866 } 7867 BuiltinVaListKind getBuiltinVaListKind() const final { 7868 return VoidPtrBuiltinVaList; 7869 } 7870 ArrayRef<const char *> getGCCRegNames() const final { 7871 return None; 7872 } 7873 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7874 return None; 7875 } 7876 bool 7877 validateAsmConstraint(const char *&Name, 7878 TargetInfo::ConstraintInfo &Info) const final { 7879 return false; 7880 } 7881 const char *getClobbers() const final { return ""; } 7882 bool isCLZForZeroUndef() const final { return false; } 7883 bool hasInt128Type() const final { return true; } 7884 IntType getIntTypeByWidth(unsigned BitWidth, 7885 bool IsSigned) const final { 7886 // WebAssembly prefers long long for explicitly 64-bit integers. 7887 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7888 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7889 } 7890 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7891 bool IsSigned) const final { 7892 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7893 return BitWidth == 64 7894 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7895 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7896 } 7897 }; 7898 7899 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7900 #define BUILTIN(ID, TYPE, ATTRS) \ 7901 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7902 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7903 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7904 #include "clang/Basic/BuiltinsWebAssembly.def" 7905 }; 7906 7907 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7908 public: 7909 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 7910 const TargetOptions &Opts) 7911 : WebAssemblyTargetInfo(T, Opts) { 7912 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7913 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7914 } 7915 7916 protected: 7917 void getTargetDefines(const LangOptions &Opts, 7918 MacroBuilder &Builder) const override { 7919 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7920 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7921 } 7922 }; 7923 7924 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7925 public: 7926 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 7927 const TargetOptions &Opts) 7928 : WebAssemblyTargetInfo(T, Opts) { 7929 LongAlign = LongWidth = 64; 7930 PointerAlign = PointerWidth = 64; 7931 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7932 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7933 } 7934 7935 protected: 7936 void getTargetDefines(const LangOptions &Opts, 7937 MacroBuilder &Builder) const override { 7938 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7939 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7940 } 7941 }; 7942 7943 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7944 #define BUILTIN(ID, TYPE, ATTRS) \ 7945 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7946 #include "clang/Basic/BuiltinsLe64.def" 7947 }; 7948 7949 static const unsigned SPIRAddrSpaceMap[] = { 7950 1, // opencl_global 7951 3, // opencl_local 7952 2, // opencl_constant 7953 4, // opencl_generic 7954 0, // cuda_device 7955 0, // cuda_constant 7956 0 // cuda_shared 7957 }; 7958 class SPIRTargetInfo : public TargetInfo { 7959 public: 7960 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7961 : TargetInfo(Triple) { 7962 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7963 "SPIR target must use unknown OS"); 7964 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7965 "SPIR target must use unknown environment type"); 7966 BigEndian = false; 7967 TLSSupported = false; 7968 LongWidth = LongAlign = 64; 7969 AddrSpaceMap = &SPIRAddrSpaceMap; 7970 UseAddrSpaceMapMangling = true; 7971 // Define available target features 7972 // These must be defined in sorted order! 7973 NoAsmVariants = true; 7974 } 7975 void getTargetDefines(const LangOptions &Opts, 7976 MacroBuilder &Builder) const override { 7977 DefineStd(Builder, "SPIR", Opts); 7978 } 7979 bool hasFeature(StringRef Feature) const override { 7980 return Feature == "spir"; 7981 } 7982 7983 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7984 const char *getClobbers() const override { return ""; } 7985 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7986 bool validateAsmConstraint(const char *&Name, 7987 TargetInfo::ConstraintInfo &info) const override { 7988 return true; 7989 } 7990 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7991 return None; 7992 } 7993 BuiltinVaListKind getBuiltinVaListKind() const override { 7994 return TargetInfo::VoidPtrBuiltinVaList; 7995 } 7996 7997 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7998 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 7999 : CCCR_Warning; 8000 } 8001 8002 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8003 return CC_SpirFunction; 8004 } 8005 8006 void setSupportedOpenCLOpts() override { 8007 // Assume all OpenCL extensions and optional core features are supported 8008 // for SPIR since it is a generic target. 8009 getSupportedOpenCLOpts().setAll(); 8010 } 8011 }; 8012 8013 class SPIR32TargetInfo : public SPIRTargetInfo { 8014 public: 8015 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8016 : SPIRTargetInfo(Triple, Opts) { 8017 PointerWidth = PointerAlign = 32; 8018 SizeType = TargetInfo::UnsignedInt; 8019 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8020 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8021 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8022 } 8023 void getTargetDefines(const LangOptions &Opts, 8024 MacroBuilder &Builder) const override { 8025 DefineStd(Builder, "SPIR32", Opts); 8026 } 8027 }; 8028 8029 class SPIR64TargetInfo : public SPIRTargetInfo { 8030 public: 8031 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8032 : SPIRTargetInfo(Triple, Opts) { 8033 PointerWidth = PointerAlign = 64; 8034 SizeType = TargetInfo::UnsignedLong; 8035 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8036 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8037 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8038 } 8039 void getTargetDefines(const LangOptions &Opts, 8040 MacroBuilder &Builder) const override { 8041 DefineStd(Builder, "SPIR64", Opts); 8042 } 8043 }; 8044 8045 class XCoreTargetInfo : public TargetInfo { 8046 static const Builtin::Info BuiltinInfo[]; 8047 public: 8048 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8049 : TargetInfo(Triple) { 8050 BigEndian = false; 8051 NoAsmVariants = true; 8052 LongLongAlign = 32; 8053 SuitableAlign = 32; 8054 DoubleAlign = LongDoubleAlign = 32; 8055 SizeType = UnsignedInt; 8056 PtrDiffType = SignedInt; 8057 IntPtrType = SignedInt; 8058 WCharType = UnsignedChar; 8059 WIntType = UnsignedInt; 8060 UseZeroLengthBitfieldAlignment = true; 8061 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8062 "-f64:32-a:0:32-n32"); 8063 } 8064 void getTargetDefines(const LangOptions &Opts, 8065 MacroBuilder &Builder) const override { 8066 Builder.defineMacro("__XS1B__"); 8067 } 8068 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8069 return llvm::makeArrayRef(BuiltinInfo, 8070 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8071 } 8072 BuiltinVaListKind getBuiltinVaListKind() const override { 8073 return TargetInfo::VoidPtrBuiltinVaList; 8074 } 8075 const char *getClobbers() const override { 8076 return ""; 8077 } 8078 ArrayRef<const char *> getGCCRegNames() const override { 8079 static const char * const GCCRegNames[] = { 8080 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8081 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8082 }; 8083 return llvm::makeArrayRef(GCCRegNames); 8084 } 8085 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8086 return None; 8087 } 8088 bool validateAsmConstraint(const char *&Name, 8089 TargetInfo::ConstraintInfo &Info) const override { 8090 return false; 8091 } 8092 int getEHDataRegisterNumber(unsigned RegNo) const override { 8093 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8094 return (RegNo < 2)? RegNo : -1; 8095 } 8096 bool allowsLargerPreferedTypeAlignment() const override { 8097 return false; 8098 } 8099 }; 8100 8101 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8102 #define BUILTIN(ID, TYPE, ATTRS) \ 8103 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8104 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8105 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8106 #include "clang/Basic/BuiltinsXCore.def" 8107 }; 8108 8109 // x86_32 Android target 8110 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8111 public: 8112 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8113 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8114 SuitableAlign = 32; 8115 LongDoubleWidth = 64; 8116 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 8117 } 8118 }; 8119 8120 // x86_64 Android target 8121 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8122 public: 8123 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8124 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8125 LongDoubleFormat = &llvm::APFloat::IEEEquad; 8126 } 8127 8128 bool useFloat128ManglingForLongDouble() const override { 8129 return true; 8130 } 8131 }; 8132 8133 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8134 class RenderScript32TargetInfo : public ARMleTargetInfo { 8135 public: 8136 RenderScript32TargetInfo(const llvm::Triple &Triple, 8137 const TargetOptions &Opts) 8138 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8139 Triple.getOSName(), 8140 Triple.getEnvironmentName()), 8141 Opts) { 8142 IsRenderScriptTarget = true; 8143 LongWidth = LongAlign = 64; 8144 } 8145 void getTargetDefines(const LangOptions &Opts, 8146 MacroBuilder &Builder) const override { 8147 Builder.defineMacro("__RENDERSCRIPT__"); 8148 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8149 } 8150 }; 8151 8152 // 64-bit RenderScript is aarch64 8153 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8154 public: 8155 RenderScript64TargetInfo(const llvm::Triple &Triple, 8156 const TargetOptions &Opts) 8157 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8158 Triple.getOSName(), 8159 Triple.getEnvironmentName()), 8160 Opts) { 8161 IsRenderScriptTarget = true; 8162 } 8163 8164 void getTargetDefines(const LangOptions &Opts, 8165 MacroBuilder &Builder) const override { 8166 Builder.defineMacro("__RENDERSCRIPT__"); 8167 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8168 } 8169 }; 8170 8171 } // end anonymous namespace 8172 8173 //===----------------------------------------------------------------------===// 8174 // Driver code 8175 //===----------------------------------------------------------------------===// 8176 8177 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8178 const TargetOptions &Opts) { 8179 llvm::Triple::OSType os = Triple.getOS(); 8180 8181 switch (Triple.getArch()) { 8182 default: 8183 return nullptr; 8184 8185 case llvm::Triple::xcore: 8186 return new XCoreTargetInfo(Triple, Opts); 8187 8188 case llvm::Triple::hexagon: 8189 return new HexagonTargetInfo(Triple, Opts); 8190 8191 case llvm::Triple::lanai: 8192 return new LanaiTargetInfo(Triple, Opts); 8193 8194 case llvm::Triple::aarch64: 8195 if (Triple.isOSDarwin()) 8196 return new DarwinAArch64TargetInfo(Triple, Opts); 8197 8198 switch (os) { 8199 case llvm::Triple::CloudABI: 8200 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8201 case llvm::Triple::FreeBSD: 8202 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8203 case llvm::Triple::Linux: 8204 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8205 case llvm::Triple::NetBSD: 8206 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8207 default: 8208 return new AArch64leTargetInfo(Triple, Opts); 8209 } 8210 8211 case llvm::Triple::aarch64_be: 8212 switch (os) { 8213 case llvm::Triple::FreeBSD: 8214 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8215 case llvm::Triple::Linux: 8216 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8217 case llvm::Triple::NetBSD: 8218 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8219 default: 8220 return new AArch64beTargetInfo(Triple, Opts); 8221 } 8222 8223 case llvm::Triple::arm: 8224 case llvm::Triple::thumb: 8225 if (Triple.isOSBinFormatMachO()) 8226 return new DarwinARMTargetInfo(Triple, Opts); 8227 8228 switch (os) { 8229 case llvm::Triple::Linux: 8230 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8231 case llvm::Triple::FreeBSD: 8232 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8233 case llvm::Triple::NetBSD: 8234 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8235 case llvm::Triple::OpenBSD: 8236 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8237 case llvm::Triple::Bitrig: 8238 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8239 case llvm::Triple::RTEMS: 8240 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8241 case llvm::Triple::NaCl: 8242 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8243 case llvm::Triple::Win32: 8244 switch (Triple.getEnvironment()) { 8245 case llvm::Triple::Cygnus: 8246 return new CygwinARMTargetInfo(Triple, Opts); 8247 case llvm::Triple::GNU: 8248 return new MinGWARMTargetInfo(Triple, Opts); 8249 case llvm::Triple::Itanium: 8250 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8251 case llvm::Triple::MSVC: 8252 default: // Assume MSVC for unknown environments 8253 return new MicrosoftARMleTargetInfo(Triple, Opts); 8254 } 8255 default: 8256 return new ARMleTargetInfo(Triple, Opts); 8257 } 8258 8259 case llvm::Triple::armeb: 8260 case llvm::Triple::thumbeb: 8261 if (Triple.isOSDarwin()) 8262 return new DarwinARMTargetInfo(Triple, Opts); 8263 8264 switch (os) { 8265 case llvm::Triple::Linux: 8266 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8267 case llvm::Triple::FreeBSD: 8268 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8269 case llvm::Triple::NetBSD: 8270 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8271 case llvm::Triple::OpenBSD: 8272 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8273 case llvm::Triple::Bitrig: 8274 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8275 case llvm::Triple::RTEMS: 8276 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8277 case llvm::Triple::NaCl: 8278 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8279 default: 8280 return new ARMbeTargetInfo(Triple, Opts); 8281 } 8282 8283 case llvm::Triple::bpfeb: 8284 case llvm::Triple::bpfel: 8285 return new BPFTargetInfo(Triple, Opts); 8286 8287 case llvm::Triple::msp430: 8288 return new MSP430TargetInfo(Triple, Opts); 8289 8290 case llvm::Triple::mips: 8291 switch (os) { 8292 case llvm::Triple::Linux: 8293 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8294 case llvm::Triple::RTEMS: 8295 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8296 case llvm::Triple::FreeBSD: 8297 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8298 case llvm::Triple::NetBSD: 8299 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8300 default: 8301 return new MipsTargetInfo(Triple, Opts); 8302 } 8303 8304 case llvm::Triple::mipsel: 8305 switch (os) { 8306 case llvm::Triple::Linux: 8307 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8308 case llvm::Triple::RTEMS: 8309 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8310 case llvm::Triple::FreeBSD: 8311 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8312 case llvm::Triple::NetBSD: 8313 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8314 case llvm::Triple::NaCl: 8315 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 8316 default: 8317 return new MipsTargetInfo(Triple, Opts); 8318 } 8319 8320 case llvm::Triple::mips64: 8321 switch (os) { 8322 case llvm::Triple::Linux: 8323 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8324 case llvm::Triple::RTEMS: 8325 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8326 case llvm::Triple::FreeBSD: 8327 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8328 case llvm::Triple::NetBSD: 8329 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8330 case llvm::Triple::OpenBSD: 8331 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8332 default: 8333 return new MipsTargetInfo(Triple, Opts); 8334 } 8335 8336 case llvm::Triple::mips64el: 8337 switch (os) { 8338 case llvm::Triple::Linux: 8339 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8340 case llvm::Triple::RTEMS: 8341 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8342 case llvm::Triple::FreeBSD: 8343 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8344 case llvm::Triple::NetBSD: 8345 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8346 case llvm::Triple::OpenBSD: 8347 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8348 default: 8349 return new MipsTargetInfo(Triple, Opts); 8350 } 8351 8352 case llvm::Triple::le32: 8353 switch (os) { 8354 case llvm::Triple::NaCl: 8355 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8356 default: 8357 return nullptr; 8358 } 8359 8360 case llvm::Triple::le64: 8361 return new Le64TargetInfo(Triple, Opts); 8362 8363 case llvm::Triple::ppc: 8364 if (Triple.isOSDarwin()) 8365 return new DarwinPPC32TargetInfo(Triple, Opts); 8366 switch (os) { 8367 case llvm::Triple::Linux: 8368 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8369 case llvm::Triple::FreeBSD: 8370 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8371 case llvm::Triple::NetBSD: 8372 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8373 case llvm::Triple::OpenBSD: 8374 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8375 case llvm::Triple::RTEMS: 8376 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8377 default: 8378 return new PPC32TargetInfo(Triple, Opts); 8379 } 8380 8381 case llvm::Triple::ppc64: 8382 if (Triple.isOSDarwin()) 8383 return new DarwinPPC64TargetInfo(Triple, Opts); 8384 switch (os) { 8385 case llvm::Triple::Linux: 8386 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8387 case llvm::Triple::Lv2: 8388 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8389 case llvm::Triple::FreeBSD: 8390 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8391 case llvm::Triple::NetBSD: 8392 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8393 default: 8394 return new PPC64TargetInfo(Triple, Opts); 8395 } 8396 8397 case llvm::Triple::ppc64le: 8398 switch (os) { 8399 case llvm::Triple::Linux: 8400 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8401 case llvm::Triple::NetBSD: 8402 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8403 default: 8404 return new PPC64TargetInfo(Triple, Opts); 8405 } 8406 8407 case llvm::Triple::nvptx: 8408 return new NVPTX32TargetInfo(Triple, Opts); 8409 case llvm::Triple::nvptx64: 8410 return new NVPTX64TargetInfo(Triple, Opts); 8411 8412 case llvm::Triple::amdgcn: 8413 case llvm::Triple::r600: 8414 return new AMDGPUTargetInfo(Triple, Opts); 8415 8416 case llvm::Triple::sparc: 8417 switch (os) { 8418 case llvm::Triple::Linux: 8419 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8420 case llvm::Triple::Solaris: 8421 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8422 case llvm::Triple::NetBSD: 8423 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8424 case llvm::Triple::OpenBSD: 8425 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8426 case llvm::Triple::RTEMS: 8427 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8428 default: 8429 return new SparcV8TargetInfo(Triple, Opts); 8430 } 8431 8432 // The 'sparcel' architecture copies all the above cases except for Solaris. 8433 case llvm::Triple::sparcel: 8434 switch (os) { 8435 case llvm::Triple::Linux: 8436 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8437 case llvm::Triple::NetBSD: 8438 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8439 case llvm::Triple::OpenBSD: 8440 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8441 case llvm::Triple::RTEMS: 8442 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8443 default: 8444 return new SparcV8elTargetInfo(Triple, Opts); 8445 } 8446 8447 case llvm::Triple::sparcv9: 8448 switch (os) { 8449 case llvm::Triple::Linux: 8450 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8451 case llvm::Triple::Solaris: 8452 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8453 case llvm::Triple::NetBSD: 8454 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8455 case llvm::Triple::OpenBSD: 8456 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8457 case llvm::Triple::FreeBSD: 8458 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8459 default: 8460 return new SparcV9TargetInfo(Triple, Opts); 8461 } 8462 8463 case llvm::Triple::systemz: 8464 switch (os) { 8465 case llvm::Triple::Linux: 8466 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8467 default: 8468 return new SystemZTargetInfo(Triple, Opts); 8469 } 8470 8471 case llvm::Triple::tce: 8472 return new TCETargetInfo(Triple, Opts); 8473 8474 case llvm::Triple::x86: 8475 if (Triple.isOSDarwin()) 8476 return new DarwinI386TargetInfo(Triple, Opts); 8477 8478 switch (os) { 8479 case llvm::Triple::CloudABI: 8480 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8481 case llvm::Triple::Linux: { 8482 switch (Triple.getEnvironment()) { 8483 default: 8484 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8485 case llvm::Triple::Android: 8486 return new AndroidX86_32TargetInfo(Triple, Opts); 8487 } 8488 } 8489 case llvm::Triple::DragonFly: 8490 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8491 case llvm::Triple::NetBSD: 8492 return new NetBSDI386TargetInfo(Triple, Opts); 8493 case llvm::Triple::OpenBSD: 8494 return new OpenBSDI386TargetInfo(Triple, Opts); 8495 case llvm::Triple::Bitrig: 8496 return new BitrigI386TargetInfo(Triple, Opts); 8497 case llvm::Triple::FreeBSD: 8498 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8499 case llvm::Triple::KFreeBSD: 8500 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8501 case llvm::Triple::Minix: 8502 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8503 case llvm::Triple::Solaris: 8504 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8505 case llvm::Triple::Win32: { 8506 switch (Triple.getEnvironment()) { 8507 case llvm::Triple::Cygnus: 8508 return new CygwinX86_32TargetInfo(Triple, Opts); 8509 case llvm::Triple::GNU: 8510 return new MinGWX86_32TargetInfo(Triple, Opts); 8511 case llvm::Triple::Itanium: 8512 case llvm::Triple::MSVC: 8513 default: // Assume MSVC for unknown environments 8514 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8515 } 8516 } 8517 case llvm::Triple::Haiku: 8518 return new HaikuX86_32TargetInfo(Triple, Opts); 8519 case llvm::Triple::RTEMS: 8520 return new RTEMSX86_32TargetInfo(Triple, Opts); 8521 case llvm::Triple::NaCl: 8522 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8523 case llvm::Triple::ELFIAMCU: 8524 return new MCUX86_32TargetInfo(Triple, Opts); 8525 default: 8526 return new X86_32TargetInfo(Triple, Opts); 8527 } 8528 8529 case llvm::Triple::x86_64: 8530 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8531 return new DarwinX86_64TargetInfo(Triple, Opts); 8532 8533 switch (os) { 8534 case llvm::Triple::CloudABI: 8535 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8536 case llvm::Triple::Linux: { 8537 switch (Triple.getEnvironment()) { 8538 default: 8539 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8540 case llvm::Triple::Android: 8541 return new AndroidX86_64TargetInfo(Triple, Opts); 8542 } 8543 } 8544 case llvm::Triple::DragonFly: 8545 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8546 case llvm::Triple::NetBSD: 8547 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8548 case llvm::Triple::OpenBSD: 8549 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8550 case llvm::Triple::Bitrig: 8551 return new BitrigX86_64TargetInfo(Triple, Opts); 8552 case llvm::Triple::FreeBSD: 8553 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8554 case llvm::Triple::KFreeBSD: 8555 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8556 case llvm::Triple::Solaris: 8557 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8558 case llvm::Triple::Win32: { 8559 switch (Triple.getEnvironment()) { 8560 case llvm::Triple::Cygnus: 8561 return new CygwinX86_64TargetInfo(Triple, Opts); 8562 case llvm::Triple::GNU: 8563 return new MinGWX86_64TargetInfo(Triple, Opts); 8564 case llvm::Triple::MSVC: 8565 default: // Assume MSVC for unknown environments 8566 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8567 } 8568 } 8569 case llvm::Triple::Haiku: 8570 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8571 case llvm::Triple::NaCl: 8572 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8573 case llvm::Triple::PS4: 8574 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8575 default: 8576 return new X86_64TargetInfo(Triple, Opts); 8577 } 8578 8579 case llvm::Triple::spir: { 8580 if (Triple.getOS() != llvm::Triple::UnknownOS || 8581 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8582 return nullptr; 8583 return new SPIR32TargetInfo(Triple, Opts); 8584 } 8585 case llvm::Triple::spir64: { 8586 if (Triple.getOS() != llvm::Triple::UnknownOS || 8587 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8588 return nullptr; 8589 return new SPIR64TargetInfo(Triple, Opts); 8590 } 8591 case llvm::Triple::wasm32: 8592 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8593 return nullptr; 8594 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8595 case llvm::Triple::wasm64: 8596 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8597 return nullptr; 8598 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8599 8600 case llvm::Triple::renderscript32: 8601 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 8602 case llvm::Triple::renderscript64: 8603 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 8604 } 8605 } 8606 8607 /// CreateTargetInfo - Return the target info object for the specified target 8608 /// options. 8609 TargetInfo * 8610 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8611 const std::shared_ptr<TargetOptions> &Opts) { 8612 llvm::Triple Triple(Opts->Triple); 8613 8614 // Construct the target 8615 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8616 if (!Target) { 8617 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8618 return nullptr; 8619 } 8620 Target->TargetOpts = Opts; 8621 8622 // Set the target CPU if specified. 8623 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8624 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8625 return nullptr; 8626 } 8627 8628 // Set the target ABI if specified. 8629 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8630 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8631 return nullptr; 8632 } 8633 8634 // Set the fp math unit. 8635 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8636 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8637 return nullptr; 8638 } 8639 8640 // Compute the default target features, we need the target to handle this 8641 // because features may have dependencies on one another. 8642 llvm::StringMap<bool> Features; 8643 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8644 Opts->FeaturesAsWritten)) 8645 return nullptr; 8646 8647 // Add the features to the compile options. 8648 Opts->Features.clear(); 8649 for (const auto &F : Features) 8650 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8651 8652 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8653 return nullptr; 8654 8655 Target->setSupportedOpenCLOpts(); 8656 8657 if (!Target->validateTarget(Diags)) 8658 return nullptr; 8659 8660 return Target.release(); 8661 } 8662