1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/TargetParser.h" 31 #include <algorithm> 32 #include <memory> 33 34 using namespace clang; 35 36 //===----------------------------------------------------------------------===// 37 // Common code shared among targets. 38 //===----------------------------------------------------------------------===// 39 40 /// DefineStd - Define a macro name and standard variants. For example if 41 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 42 /// when in GNU mode. 43 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 44 const LangOptions &Opts) { 45 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 46 47 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 48 // in the user's namespace. 49 if (Opts.GNUMode) 50 Builder.defineMacro(MacroName); 51 52 // Define __unix. 53 Builder.defineMacro("__" + MacroName); 54 55 // Define __unix__. 56 Builder.defineMacro("__" + MacroName + "__"); 57 } 58 59 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 60 bool Tuning = true) { 61 Builder.defineMacro("__" + CPUName); 62 Builder.defineMacro("__" + CPUName + "__"); 63 if (Tuning) 64 Builder.defineMacro("__tune_" + CPUName + "__"); 65 } 66 67 //===----------------------------------------------------------------------===// 68 // Defines specific to certain operating systems. 69 //===----------------------------------------------------------------------===// 70 71 namespace { 72 template<typename TgtInfo> 73 class OSTargetInfo : public TgtInfo { 74 protected: 75 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 76 MacroBuilder &Builder) const=0; 77 public: 78 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 79 void getTargetDefines(const LangOptions &Opts, 80 MacroBuilder &Builder) const override { 81 TgtInfo::getTargetDefines(Opts, Builder); 82 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 83 } 84 85 }; 86 87 // CloudABI Target 88 template <typename Target> 89 class CloudABITargetInfo : public OSTargetInfo<Target> { 90 protected: 91 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 92 MacroBuilder &Builder) const override { 93 Builder.defineMacro("__CloudABI__"); 94 Builder.defineMacro("__ELF__"); 95 96 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 97 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 98 Builder.defineMacro("__STDC_UTF_16__"); 99 Builder.defineMacro("__STDC_UTF_32__"); 100 } 101 102 public: 103 CloudABITargetInfo(const llvm::Triple &Triple) 104 : OSTargetInfo<Target>(Triple) { 105 this->UserLabelPrefix = ""; 106 } 107 }; 108 109 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 110 const llvm::Triple &Triple, 111 StringRef &PlatformName, 112 VersionTuple &PlatformMinVersion) { 113 Builder.defineMacro("__APPLE_CC__", "6000"); 114 Builder.defineMacro("__APPLE__"); 115 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 116 // AddressSanitizer doesn't play well with source fortification, which is on 117 // by default on Darwin. 118 if (Opts.Sanitize.has(SanitizerKind::Address)) 119 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 120 121 if (!Opts.ObjCAutoRefCount) { 122 // __weak is always defined, for use in blocks and with objc pointers. 123 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 124 125 // Darwin defines __strong even in C mode (just to nothing). 126 if (Opts.getGC() != LangOptions::NonGC) 127 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 128 else 129 Builder.defineMacro("__strong", ""); 130 131 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 132 // allow this in C, since one might have block pointers in structs that 133 // are used in pure C code and in Objective-C ARC. 134 Builder.defineMacro("__unsafe_unretained", ""); 135 } 136 137 if (Opts.Static) 138 Builder.defineMacro("__STATIC__"); 139 else 140 Builder.defineMacro("__DYNAMIC__"); 141 142 if (Opts.POSIXThreads) 143 Builder.defineMacro("_REENTRANT"); 144 145 // Get the platform type and version number from the triple. 146 unsigned Maj, Min, Rev; 147 if (Triple.isMacOSX()) { 148 Triple.getMacOSXVersion(Maj, Min, Rev); 149 PlatformName = "macosx"; 150 } else { 151 Triple.getOSVersion(Maj, Min, Rev); 152 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 153 } 154 155 // If -target arch-pc-win32-macho option specified, we're 156 // generating code for Win32 ABI. No need to emit 157 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 158 if (PlatformName == "win32") { 159 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 160 return; 161 } 162 163 // Set the appropriate OS version define. 164 if (Triple.isiOS()) { 165 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 166 char Str[6]; 167 Str[0] = '0' + Maj; 168 Str[1] = '0' + (Min / 10); 169 Str[2] = '0' + (Min % 10); 170 Str[3] = '0' + (Rev / 10); 171 Str[4] = '0' + (Rev % 10); 172 Str[5] = '\0'; 173 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str); 174 } else if (Triple.isMacOSX()) { 175 // Note that the Driver allows versions which aren't representable in the 176 // define (because we only get a single digit for the minor and micro 177 // revision numbers). So, we limit them to the maximum representable 178 // version. 179 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 180 char Str[7]; 181 if (Maj < 10 || (Maj == 10 && Min < 10)) { 182 Str[0] = '0' + (Maj / 10); 183 Str[1] = '0' + (Maj % 10); 184 Str[2] = '0' + std::min(Min, 9U); 185 Str[3] = '0' + std::min(Rev, 9U); 186 Str[4] = '\0'; 187 } else { 188 // Handle versions > 10.9. 189 Str[0] = '0' + (Maj / 10); 190 Str[1] = '0' + (Maj % 10); 191 Str[2] = '0' + (Min / 10); 192 Str[3] = '0' + (Min % 10); 193 Str[4] = '0' + (Rev / 10); 194 Str[5] = '0' + (Rev % 10); 195 Str[6] = '\0'; 196 } 197 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 198 } 199 200 // Tell users about the kernel if there is one. 201 if (Triple.isOSDarwin()) 202 Builder.defineMacro("__MACH__"); 203 204 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 205 } 206 207 template<typename Target> 208 class DarwinTargetInfo : public OSTargetInfo<Target> { 209 protected: 210 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 211 MacroBuilder &Builder) const override { 212 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 213 this->PlatformMinVersion); 214 } 215 216 public: 217 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 218 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 219 this->MCountName = "\01mcount"; 220 } 221 222 std::string isValidSectionSpecifier(StringRef SR) const override { 223 // Let MCSectionMachO validate this. 224 StringRef Segment, Section; 225 unsigned TAA, StubSize; 226 bool HasTAA; 227 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 228 TAA, HasTAA, StubSize); 229 } 230 231 const char *getStaticInitSectionSpecifier() const override { 232 // FIXME: We should return 0 when building kexts. 233 return "__TEXT,__StaticInit,regular,pure_instructions"; 234 } 235 236 /// Darwin does not support protected visibility. Darwin's "default" 237 /// is very similar to ELF's "protected"; Darwin requires a "weak" 238 /// attribute on declarations that can be dynamically replaced. 239 bool hasProtectedVisibility() const override { 240 return false; 241 } 242 }; 243 244 245 // DragonFlyBSD Target 246 template<typename Target> 247 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 248 protected: 249 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 250 MacroBuilder &Builder) const override { 251 // DragonFly defines; list based off of gcc output 252 Builder.defineMacro("__DragonFly__"); 253 Builder.defineMacro("__DragonFly_cc_version", "100001"); 254 Builder.defineMacro("__ELF__"); 255 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 256 Builder.defineMacro("__tune_i386__"); 257 DefineStd(Builder, "unix", Opts); 258 } 259 public: 260 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 261 : OSTargetInfo<Target>(Triple) { 262 this->UserLabelPrefix = ""; 263 264 switch (Triple.getArch()) { 265 default: 266 case llvm::Triple::x86: 267 case llvm::Triple::x86_64: 268 this->MCountName = ".mcount"; 269 break; 270 } 271 } 272 }; 273 274 // FreeBSD Target 275 template<typename Target> 276 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 277 protected: 278 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 279 MacroBuilder &Builder) const override { 280 // FreeBSD defines; list based off of gcc output 281 282 unsigned Release = Triple.getOSMajorVersion(); 283 if (Release == 0U) 284 Release = 8; 285 286 Builder.defineMacro("__FreeBSD__", Twine(Release)); 287 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 288 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 289 DefineStd(Builder, "unix", Opts); 290 Builder.defineMacro("__ELF__"); 291 292 // On FreeBSD, wchar_t contains the number of the code point as 293 // used by the character set of the locale. These character sets are 294 // not necessarily a superset of ASCII. 295 // 296 // FIXME: This is wrong; the macro refers to the numerical values 297 // of wchar_t *literals*, which are not locale-dependent. However, 298 // FreeBSD systems apparently depend on us getting this wrong, and 299 // setting this to 1 is conforming even if all the basic source 300 // character literals have the same encoding as char and wchar_t. 301 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 302 } 303 public: 304 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 305 this->UserLabelPrefix = ""; 306 307 switch (Triple.getArch()) { 308 default: 309 case llvm::Triple::x86: 310 case llvm::Triple::x86_64: 311 this->MCountName = ".mcount"; 312 break; 313 case llvm::Triple::mips: 314 case llvm::Triple::mipsel: 315 case llvm::Triple::ppc: 316 case llvm::Triple::ppc64: 317 case llvm::Triple::ppc64le: 318 this->MCountName = "_mcount"; 319 break; 320 case llvm::Triple::arm: 321 this->MCountName = "__mcount"; 322 break; 323 } 324 } 325 }; 326 327 // GNU/kFreeBSD Target 328 template<typename Target> 329 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 330 protected: 331 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 332 MacroBuilder &Builder) const override { 333 // GNU/kFreeBSD defines; list based off of gcc output 334 335 DefineStd(Builder, "unix", Opts); 336 Builder.defineMacro("__FreeBSD_kernel__"); 337 Builder.defineMacro("__GLIBC__"); 338 Builder.defineMacro("__ELF__"); 339 if (Opts.POSIXThreads) 340 Builder.defineMacro("_REENTRANT"); 341 if (Opts.CPlusPlus) 342 Builder.defineMacro("_GNU_SOURCE"); 343 } 344 public: 345 KFreeBSDTargetInfo(const llvm::Triple &Triple) 346 : OSTargetInfo<Target>(Triple) { 347 this->UserLabelPrefix = ""; 348 } 349 }; 350 351 // Minix Target 352 template<typename Target> 353 class MinixTargetInfo : public OSTargetInfo<Target> { 354 protected: 355 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 356 MacroBuilder &Builder) const override { 357 // Minix defines 358 359 Builder.defineMacro("__minix", "3"); 360 Builder.defineMacro("_EM_WSIZE", "4"); 361 Builder.defineMacro("_EM_PSIZE", "4"); 362 Builder.defineMacro("_EM_SSIZE", "2"); 363 Builder.defineMacro("_EM_LSIZE", "4"); 364 Builder.defineMacro("_EM_FSIZE", "4"); 365 Builder.defineMacro("_EM_DSIZE", "8"); 366 Builder.defineMacro("__ELF__"); 367 DefineStd(Builder, "unix", Opts); 368 } 369 public: 370 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 371 this->UserLabelPrefix = ""; 372 } 373 }; 374 375 // Linux target 376 template<typename Target> 377 class LinuxTargetInfo : public OSTargetInfo<Target> { 378 protected: 379 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 380 MacroBuilder &Builder) const override { 381 // Linux defines; list based off of gcc output 382 DefineStd(Builder, "unix", Opts); 383 DefineStd(Builder, "linux", Opts); 384 Builder.defineMacro("__gnu_linux__"); 385 Builder.defineMacro("__ELF__"); 386 if (Triple.isAndroid()) { 387 Builder.defineMacro("__ANDROID__", "1"); 388 unsigned Maj, Min, Rev; 389 Triple.getEnvironmentVersion(Maj, Min, Rev); 390 this->PlatformName = "android"; 391 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 392 } 393 if (Opts.POSIXThreads) 394 Builder.defineMacro("_REENTRANT"); 395 if (Opts.CPlusPlus) 396 Builder.defineMacro("_GNU_SOURCE"); 397 } 398 public: 399 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 400 this->UserLabelPrefix = ""; 401 this->WIntType = TargetInfo::UnsignedInt; 402 403 switch (Triple.getArch()) { 404 default: 405 break; 406 case llvm::Triple::ppc: 407 case llvm::Triple::ppc64: 408 case llvm::Triple::ppc64le: 409 this->MCountName = "_mcount"; 410 break; 411 } 412 } 413 414 const char *getStaticInitSectionSpecifier() const override { 415 return ".text.startup"; 416 } 417 }; 418 419 // NetBSD Target 420 template<typename Target> 421 class NetBSDTargetInfo : public OSTargetInfo<Target> { 422 protected: 423 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 424 MacroBuilder &Builder) const override { 425 // NetBSD defines; list based off of gcc output 426 Builder.defineMacro("__NetBSD__"); 427 Builder.defineMacro("__unix__"); 428 Builder.defineMacro("__ELF__"); 429 if (Opts.POSIXThreads) 430 Builder.defineMacro("_POSIX_THREADS"); 431 432 switch (Triple.getArch()) { 433 default: 434 break; 435 case llvm::Triple::arm: 436 case llvm::Triple::armeb: 437 case llvm::Triple::thumb: 438 case llvm::Triple::thumbeb: 439 Builder.defineMacro("__ARM_DWARF_EH__"); 440 break; 441 } 442 } 443 public: 444 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 445 this->UserLabelPrefix = ""; 446 this->MCountName = "_mcount"; 447 } 448 }; 449 450 // OpenBSD Target 451 template<typename Target> 452 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 453 protected: 454 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 455 MacroBuilder &Builder) const override { 456 // OpenBSD defines; list based off of gcc output 457 458 Builder.defineMacro("__OpenBSD__"); 459 DefineStd(Builder, "unix", Opts); 460 Builder.defineMacro("__ELF__"); 461 if (Opts.POSIXThreads) 462 Builder.defineMacro("_REENTRANT"); 463 } 464 public: 465 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 466 this->UserLabelPrefix = ""; 467 this->TLSSupported = false; 468 469 switch (Triple.getArch()) { 470 default: 471 case llvm::Triple::x86: 472 case llvm::Triple::x86_64: 473 case llvm::Triple::arm: 474 case llvm::Triple::sparc: 475 this->MCountName = "__mcount"; 476 break; 477 case llvm::Triple::mips64: 478 case llvm::Triple::mips64el: 479 case llvm::Triple::ppc: 480 case llvm::Triple::sparcv9: 481 this->MCountName = "_mcount"; 482 break; 483 } 484 } 485 }; 486 487 // Bitrig Target 488 template<typename Target> 489 class BitrigTargetInfo : public OSTargetInfo<Target> { 490 protected: 491 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 492 MacroBuilder &Builder) const override { 493 // Bitrig defines; list based off of gcc output 494 495 Builder.defineMacro("__Bitrig__"); 496 DefineStd(Builder, "unix", Opts); 497 Builder.defineMacro("__ELF__"); 498 if (Opts.POSIXThreads) 499 Builder.defineMacro("_REENTRANT"); 500 501 switch (Triple.getArch()) { 502 default: 503 break; 504 case llvm::Triple::arm: 505 case llvm::Triple::armeb: 506 case llvm::Triple::thumb: 507 case llvm::Triple::thumbeb: 508 Builder.defineMacro("__ARM_DWARF_EH__"); 509 break; 510 } 511 } 512 public: 513 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 514 this->UserLabelPrefix = ""; 515 this->MCountName = "__mcount"; 516 } 517 }; 518 519 // PSP Target 520 template<typename Target> 521 class PSPTargetInfo : public OSTargetInfo<Target> { 522 protected: 523 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 524 MacroBuilder &Builder) const override { 525 // PSP defines; list based on the output of the pspdev gcc toolchain. 526 Builder.defineMacro("PSP"); 527 Builder.defineMacro("_PSP"); 528 Builder.defineMacro("__psp__"); 529 Builder.defineMacro("__ELF__"); 530 } 531 public: 532 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 533 this->UserLabelPrefix = ""; 534 } 535 }; 536 537 // PS3 PPU Target 538 template<typename Target> 539 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 540 protected: 541 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 542 MacroBuilder &Builder) const override { 543 // PS3 PPU defines. 544 Builder.defineMacro("__PPC__"); 545 Builder.defineMacro("__PPU__"); 546 Builder.defineMacro("__CELLOS_LV2__"); 547 Builder.defineMacro("__ELF__"); 548 Builder.defineMacro("__LP32__"); 549 Builder.defineMacro("_ARCH_PPC64"); 550 Builder.defineMacro("__powerpc64__"); 551 } 552 public: 553 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 554 this->UserLabelPrefix = ""; 555 this->LongWidth = this->LongAlign = 32; 556 this->PointerWidth = this->PointerAlign = 32; 557 this->IntMaxType = TargetInfo::SignedLongLong; 558 this->Int64Type = TargetInfo::SignedLongLong; 559 this->SizeType = TargetInfo::UnsignedInt; 560 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64"; 561 } 562 }; 563 564 template <typename Target> 565 class PS4OSTargetInfo : public OSTargetInfo<Target> { 566 protected: 567 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 568 MacroBuilder &Builder) const override { 569 Builder.defineMacro("__FreeBSD__", "9"); 570 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 571 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 572 DefineStd(Builder, "unix", Opts); 573 Builder.defineMacro("__ELF__"); 574 Builder.defineMacro("__PS4__"); 575 } 576 public: 577 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 578 this->WCharType = this->UnsignedShort; 579 580 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 581 this->MaxTLSAlign = 256; 582 this->UserLabelPrefix = ""; 583 584 switch (Triple.getArch()) { 585 default: 586 case llvm::Triple::x86_64: 587 this->MCountName = ".mcount"; 588 break; 589 } 590 } 591 }; 592 593 // Solaris target 594 template<typename Target> 595 class SolarisTargetInfo : public OSTargetInfo<Target> { 596 protected: 597 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 598 MacroBuilder &Builder) const override { 599 DefineStd(Builder, "sun", Opts); 600 DefineStd(Builder, "unix", Opts); 601 Builder.defineMacro("__ELF__"); 602 Builder.defineMacro("__svr4__"); 603 Builder.defineMacro("__SVR4"); 604 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 605 // newer, but to 500 for everything else. feature_test.h has a check to 606 // ensure that you are not using C99 with an old version of X/Open or C89 607 // with a new version. 608 if (Opts.C99) 609 Builder.defineMacro("_XOPEN_SOURCE", "600"); 610 else 611 Builder.defineMacro("_XOPEN_SOURCE", "500"); 612 if (Opts.CPlusPlus) 613 Builder.defineMacro("__C99FEATURES__"); 614 Builder.defineMacro("_LARGEFILE_SOURCE"); 615 Builder.defineMacro("_LARGEFILE64_SOURCE"); 616 Builder.defineMacro("__EXTENSIONS__"); 617 Builder.defineMacro("_REENTRANT"); 618 } 619 public: 620 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 621 this->UserLabelPrefix = ""; 622 this->WCharType = this->SignedInt; 623 // FIXME: WIntType should be SignedLong 624 } 625 }; 626 627 // Windows target 628 template<typename Target> 629 class WindowsTargetInfo : public OSTargetInfo<Target> { 630 protected: 631 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 632 MacroBuilder &Builder) const override { 633 Builder.defineMacro("_WIN32"); 634 } 635 void getVisualStudioDefines(const LangOptions &Opts, 636 MacroBuilder &Builder) const { 637 if (Opts.CPlusPlus) { 638 if (Opts.RTTIData) 639 Builder.defineMacro("_CPPRTTI"); 640 641 if (Opts.CXXExceptions) 642 Builder.defineMacro("_CPPUNWIND"); 643 } 644 645 if (Opts.Bool) 646 Builder.defineMacro("__BOOL_DEFINED"); 647 648 if (!Opts.CharIsSigned) 649 Builder.defineMacro("_CHAR_UNSIGNED"); 650 651 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 652 // but it works for now. 653 if (Opts.POSIXThreads) 654 Builder.defineMacro("_MT"); 655 656 if (Opts.MSCompatibilityVersion) { 657 Builder.defineMacro("_MSC_VER", 658 Twine(Opts.MSCompatibilityVersion / 100000)); 659 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 660 // FIXME We cannot encode the revision information into 32-bits 661 Builder.defineMacro("_MSC_BUILD", Twine(1)); 662 663 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 664 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 665 } 666 667 if (Opts.MicrosoftExt) { 668 Builder.defineMacro("_MSC_EXTENSIONS"); 669 670 if (Opts.CPlusPlus11) { 671 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 672 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 673 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 674 } 675 } 676 677 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 678 } 679 680 public: 681 WindowsTargetInfo(const llvm::Triple &Triple) 682 : OSTargetInfo<Target>(Triple) {} 683 }; 684 685 template <typename Target> 686 class NaClTargetInfo : public OSTargetInfo<Target> { 687 protected: 688 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 689 MacroBuilder &Builder) const override { 690 if (Opts.POSIXThreads) 691 Builder.defineMacro("_REENTRANT"); 692 if (Opts.CPlusPlus) 693 Builder.defineMacro("_GNU_SOURCE"); 694 695 DefineStd(Builder, "unix", Opts); 696 Builder.defineMacro("__ELF__"); 697 Builder.defineMacro("__native_client__"); 698 } 699 700 public: 701 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 702 this->UserLabelPrefix = ""; 703 this->LongAlign = 32; 704 this->LongWidth = 32; 705 this->PointerAlign = 32; 706 this->PointerWidth = 32; 707 this->IntMaxType = TargetInfo::SignedLongLong; 708 this->Int64Type = TargetInfo::SignedLongLong; 709 this->DoubleAlign = 64; 710 this->LongDoubleWidth = 64; 711 this->LongDoubleAlign = 64; 712 this->LongLongWidth = 64; 713 this->LongLongAlign = 64; 714 this->SizeType = TargetInfo::UnsignedInt; 715 this->PtrDiffType = TargetInfo::SignedInt; 716 this->IntPtrType = TargetInfo::SignedInt; 717 // RegParmMax is inherited from the underlying architecture 718 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 719 if (Triple.getArch() == llvm::Triple::arm) { 720 // Handled in ARM's setABI(). 721 } else if (Triple.getArch() == llvm::Triple::x86) { 722 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 723 } else if (Triple.getArch() == llvm::Triple::x86_64) { 724 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 725 } else if (Triple.getArch() == llvm::Triple::mipsel) { 726 // Handled on mips' setDataLayoutString. 727 } else { 728 assert(Triple.getArch() == llvm::Triple::le32); 729 this->DataLayoutString = "e-p:32:32-i64:64"; 730 } 731 } 732 }; 733 734 // WebAssembly target 735 template <typename Target> 736 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 737 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 738 MacroBuilder &Builder) const final { 739 // A common platform macro. 740 if (Opts.POSIXThreads) 741 Builder.defineMacro("_REENTRANT"); 742 // Follow g++ convention and predefine _GNU_SOURCE for C++. 743 if (Opts.CPlusPlus) 744 Builder.defineMacro("_GNU_SOURCE"); 745 } 746 747 // As an optimization, group static init code together in a section. 748 const char *getStaticInitSectionSpecifier() const final { 749 return ".text.__startup"; 750 } 751 752 public: 753 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 754 : OSTargetInfo<Target>(Triple) { 755 this->MCountName = "__mcount"; 756 this->UserLabelPrefix = ""; 757 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 758 } 759 }; 760 761 //===----------------------------------------------------------------------===// 762 // Specific target implementations. 763 //===----------------------------------------------------------------------===// 764 765 // PPC abstract base class 766 class PPCTargetInfo : public TargetInfo { 767 static const Builtin::Info BuiltinInfo[]; 768 static const char * const GCCRegNames[]; 769 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 770 std::string CPU; 771 772 // Target cpu features. 773 bool HasVSX; 774 bool HasP8Vector; 775 bool HasP8Crypto; 776 bool HasDirectMove; 777 bool HasQPX; 778 bool HasHTM; 779 bool HasBPERMD; 780 bool HasExtDiv; 781 782 protected: 783 std::string ABI; 784 785 public: 786 PPCTargetInfo(const llvm::Triple &Triple) 787 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 788 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 789 HasBPERMD(false), HasExtDiv(false) { 790 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 791 SimdDefaultAlign = 128; 792 LongDoubleWidth = LongDoubleAlign = 128; 793 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 794 } 795 796 /// \brief Flags for architecture specific defines. 797 typedef enum { 798 ArchDefineNone = 0, 799 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 800 ArchDefinePpcgr = 1 << 1, 801 ArchDefinePpcsq = 1 << 2, 802 ArchDefine440 = 1 << 3, 803 ArchDefine603 = 1 << 4, 804 ArchDefine604 = 1 << 5, 805 ArchDefinePwr4 = 1 << 6, 806 ArchDefinePwr5 = 1 << 7, 807 ArchDefinePwr5x = 1 << 8, 808 ArchDefinePwr6 = 1 << 9, 809 ArchDefinePwr6x = 1 << 10, 810 ArchDefinePwr7 = 1 << 11, 811 ArchDefinePwr8 = 1 << 12, 812 ArchDefineA2 = 1 << 13, 813 ArchDefineA2q = 1 << 14 814 } ArchDefineTypes; 815 816 // Note: GCC recognizes the following additional cpus: 817 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 818 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 819 // titan, rs64. 820 bool setCPU(const std::string &Name) override { 821 bool CPUKnown = llvm::StringSwitch<bool>(Name) 822 .Case("generic", true) 823 .Case("440", true) 824 .Case("450", true) 825 .Case("601", true) 826 .Case("602", true) 827 .Case("603", true) 828 .Case("603e", true) 829 .Case("603ev", true) 830 .Case("604", true) 831 .Case("604e", true) 832 .Case("620", true) 833 .Case("630", true) 834 .Case("g3", true) 835 .Case("7400", true) 836 .Case("g4", true) 837 .Case("7450", true) 838 .Case("g4+", true) 839 .Case("750", true) 840 .Case("970", true) 841 .Case("g5", true) 842 .Case("a2", true) 843 .Case("a2q", true) 844 .Case("e500mc", true) 845 .Case("e5500", true) 846 .Case("power3", true) 847 .Case("pwr3", true) 848 .Case("power4", true) 849 .Case("pwr4", true) 850 .Case("power5", true) 851 .Case("pwr5", true) 852 .Case("power5x", true) 853 .Case("pwr5x", true) 854 .Case("power6", true) 855 .Case("pwr6", true) 856 .Case("power6x", true) 857 .Case("pwr6x", true) 858 .Case("power7", true) 859 .Case("pwr7", true) 860 .Case("power8", true) 861 .Case("pwr8", true) 862 .Case("powerpc", true) 863 .Case("ppc", true) 864 .Case("powerpc64", true) 865 .Case("ppc64", true) 866 .Case("powerpc64le", true) 867 .Case("ppc64le", true) 868 .Default(false); 869 870 if (CPUKnown) 871 CPU = Name; 872 873 return CPUKnown; 874 } 875 876 877 StringRef getABI() const override { return ABI; } 878 879 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 880 return llvm::makeArrayRef(BuiltinInfo, 881 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 882 } 883 884 bool isCLZForZeroUndef() const override { return false; } 885 886 void getTargetDefines(const LangOptions &Opts, 887 MacroBuilder &Builder) const override; 888 889 bool 890 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 891 StringRef CPU, 892 const std::vector<std::string> &FeaturesVec) const override; 893 894 bool handleTargetFeatures(std::vector<std::string> &Features, 895 DiagnosticsEngine &Diags) override; 896 bool hasFeature(StringRef Feature) const override; 897 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 898 bool Enabled) const override; 899 900 ArrayRef<const char *> getGCCRegNames() const override; 901 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 902 bool validateAsmConstraint(const char *&Name, 903 TargetInfo::ConstraintInfo &Info) const override { 904 switch (*Name) { 905 default: return false; 906 case 'O': // Zero 907 break; 908 case 'b': // Base register 909 case 'f': // Floating point register 910 Info.setAllowsRegister(); 911 break; 912 // FIXME: The following are added to allow parsing. 913 // I just took a guess at what the actions should be. 914 // Also, is more specific checking needed? I.e. specific registers? 915 case 'd': // Floating point register (containing 64-bit value) 916 case 'v': // Altivec vector register 917 Info.setAllowsRegister(); 918 break; 919 case 'w': 920 switch (Name[1]) { 921 case 'd':// VSX vector register to hold vector double data 922 case 'f':// VSX vector register to hold vector float data 923 case 's':// VSX vector register to hold scalar float data 924 case 'a':// Any VSX register 925 case 'c':// An individual CR bit 926 break; 927 default: 928 return false; 929 } 930 Info.setAllowsRegister(); 931 Name++; // Skip over 'w'. 932 break; 933 case 'h': // `MQ', `CTR', or `LINK' register 934 case 'q': // `MQ' register 935 case 'c': // `CTR' register 936 case 'l': // `LINK' register 937 case 'x': // `CR' register (condition register) number 0 938 case 'y': // `CR' register (condition register) 939 case 'z': // `XER[CA]' carry bit (part of the XER register) 940 Info.setAllowsRegister(); 941 break; 942 case 'I': // Signed 16-bit constant 943 case 'J': // Unsigned 16-bit constant shifted left 16 bits 944 // (use `L' instead for SImode constants) 945 case 'K': // Unsigned 16-bit constant 946 case 'L': // Signed 16-bit constant shifted left 16 bits 947 case 'M': // Constant larger than 31 948 case 'N': // Exact power of 2 949 case 'P': // Constant whose negation is a signed 16-bit constant 950 case 'G': // Floating point constant that can be loaded into a 951 // register with one instruction per word 952 case 'H': // Integer/Floating point constant that can be loaded 953 // into a register using three instructions 954 break; 955 case 'm': // Memory operand. Note that on PowerPC targets, m can 956 // include addresses that update the base register. It 957 // is therefore only safe to use `m' in an asm statement 958 // if that asm statement accesses the operand exactly once. 959 // The asm statement must also use `%U<opno>' as a 960 // placeholder for the "update" flag in the corresponding 961 // load or store instruction. For example: 962 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 963 // is correct but: 964 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 965 // is not. Use es rather than m if you don't want the base 966 // register to be updated. 967 case 'e': 968 if (Name[1] != 's') 969 return false; 970 // es: A "stable" memory operand; that is, one which does not 971 // include any automodification of the base register. Unlike 972 // `m', this constraint can be used in asm statements that 973 // might access the operand several times, or that might not 974 // access it at all. 975 Info.setAllowsMemory(); 976 Name++; // Skip over 'e'. 977 break; 978 case 'Q': // Memory operand that is an offset from a register (it is 979 // usually better to use `m' or `es' in asm statements) 980 case 'Z': // Memory operand that is an indexed or indirect from a 981 // register (it is usually better to use `m' or `es' in 982 // asm statements) 983 Info.setAllowsMemory(); 984 Info.setAllowsRegister(); 985 break; 986 case 'R': // AIX TOC entry 987 case 'a': // Address operand that is an indexed or indirect from a 988 // register (`p' is preferable for asm statements) 989 case 'S': // Constant suitable as a 64-bit mask operand 990 case 'T': // Constant suitable as a 32-bit mask operand 991 case 'U': // System V Release 4 small data area reference 992 case 't': // AND masks that can be performed by two rldic{l, r} 993 // instructions 994 case 'W': // Vector constant that does not require memory 995 case 'j': // Vector constant that is all zeros. 996 break; 997 // End FIXME. 998 } 999 return true; 1000 } 1001 std::string convertConstraint(const char *&Constraint) const override { 1002 std::string R; 1003 switch (*Constraint) { 1004 case 'e': 1005 case 'w': 1006 // Two-character constraint; add "^" hint for later parsing. 1007 R = std::string("^") + std::string(Constraint, 2); 1008 Constraint++; 1009 break; 1010 default: 1011 return TargetInfo::convertConstraint(Constraint); 1012 } 1013 return R; 1014 } 1015 const char *getClobbers() const override { 1016 return ""; 1017 } 1018 int getEHDataRegisterNumber(unsigned RegNo) const override { 1019 if (RegNo == 0) return 3; 1020 if (RegNo == 1) return 4; 1021 return -1; 1022 } 1023 1024 bool hasSjLjLowering() const override { 1025 return true; 1026 } 1027 1028 bool useFloat128ManglingForLongDouble() const override { 1029 return LongDoubleWidth == 128 && 1030 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1031 getTriple().isOSBinFormatELF(); 1032 } 1033 }; 1034 1035 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1036 #define BUILTIN(ID, TYPE, ATTRS) \ 1037 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1038 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1039 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1040 #include "clang/Basic/BuiltinsPPC.def" 1041 }; 1042 1043 /// handleTargetFeatures - Perform initialization based on the user 1044 /// configured set of features. 1045 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1046 DiagnosticsEngine &Diags) { 1047 for (const auto &Feature : Features) { 1048 if (Feature == "+vsx") { 1049 HasVSX = true; 1050 } else if (Feature == "+bpermd") { 1051 HasBPERMD = true; 1052 } else if (Feature == "+extdiv") { 1053 HasExtDiv = true; 1054 } else if (Feature == "+power8-vector") { 1055 HasP8Vector = true; 1056 } else if (Feature == "+crypto") { 1057 HasP8Crypto = true; 1058 } else if (Feature == "+direct-move") { 1059 HasDirectMove = true; 1060 } else if (Feature == "+qpx") { 1061 HasQPX = true; 1062 } else if (Feature == "+htm") { 1063 HasHTM = true; 1064 } 1065 // TODO: Finish this list and add an assert that we've handled them 1066 // all. 1067 } 1068 1069 return true; 1070 } 1071 1072 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1073 /// #defines that are not tied to a specific subtarget. 1074 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1075 MacroBuilder &Builder) const { 1076 // Target identification. 1077 Builder.defineMacro("__ppc__"); 1078 Builder.defineMacro("__PPC__"); 1079 Builder.defineMacro("_ARCH_PPC"); 1080 Builder.defineMacro("__powerpc__"); 1081 Builder.defineMacro("__POWERPC__"); 1082 if (PointerWidth == 64) { 1083 Builder.defineMacro("_ARCH_PPC64"); 1084 Builder.defineMacro("__powerpc64__"); 1085 Builder.defineMacro("__ppc64__"); 1086 Builder.defineMacro("__PPC64__"); 1087 } 1088 1089 // Target properties. 1090 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1091 Builder.defineMacro("_LITTLE_ENDIAN"); 1092 } else { 1093 if (getTriple().getOS() != llvm::Triple::NetBSD && 1094 getTriple().getOS() != llvm::Triple::OpenBSD) 1095 Builder.defineMacro("_BIG_ENDIAN"); 1096 } 1097 1098 // ABI options. 1099 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1100 Builder.defineMacro("_CALL_ELF", "1"); 1101 if (ABI == "elfv2") 1102 Builder.defineMacro("_CALL_ELF", "2"); 1103 1104 // Subtarget options. 1105 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1106 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1107 1108 // FIXME: Should be controlled by command line option. 1109 if (LongDoubleWidth == 128) 1110 Builder.defineMacro("__LONG_DOUBLE_128__"); 1111 1112 if (Opts.AltiVec) { 1113 Builder.defineMacro("__VEC__", "10206"); 1114 Builder.defineMacro("__ALTIVEC__"); 1115 } 1116 1117 // CPU identification. 1118 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1119 .Case("440", ArchDefineName) 1120 .Case("450", ArchDefineName | ArchDefine440) 1121 .Case("601", ArchDefineName) 1122 .Case("602", ArchDefineName | ArchDefinePpcgr) 1123 .Case("603", ArchDefineName | ArchDefinePpcgr) 1124 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1125 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1126 .Case("604", ArchDefineName | ArchDefinePpcgr) 1127 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1128 .Case("620", ArchDefineName | ArchDefinePpcgr) 1129 .Case("630", ArchDefineName | ArchDefinePpcgr) 1130 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1131 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1132 .Case("750", ArchDefineName | ArchDefinePpcgr) 1133 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1134 | ArchDefinePpcsq) 1135 .Case("a2", ArchDefineA2) 1136 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1137 .Case("pwr3", ArchDefinePpcgr) 1138 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1139 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1140 | ArchDefinePpcsq) 1141 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1142 | ArchDefinePpcgr | ArchDefinePpcsq) 1143 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1144 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1145 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1146 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1147 | ArchDefinePpcsq) 1148 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1149 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1150 | ArchDefinePpcgr | ArchDefinePpcsq) 1151 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1152 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1153 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1154 .Case("power3", ArchDefinePpcgr) 1155 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1156 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1157 | ArchDefinePpcsq) 1158 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1159 | ArchDefinePpcgr | ArchDefinePpcsq) 1160 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1161 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1162 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1163 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1164 | ArchDefinePpcsq) 1165 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1166 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1167 | ArchDefinePpcgr | ArchDefinePpcsq) 1168 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1169 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1170 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1171 .Default(ArchDefineNone); 1172 1173 if (defs & ArchDefineName) 1174 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1175 if (defs & ArchDefinePpcgr) 1176 Builder.defineMacro("_ARCH_PPCGR"); 1177 if (defs & ArchDefinePpcsq) 1178 Builder.defineMacro("_ARCH_PPCSQ"); 1179 if (defs & ArchDefine440) 1180 Builder.defineMacro("_ARCH_440"); 1181 if (defs & ArchDefine603) 1182 Builder.defineMacro("_ARCH_603"); 1183 if (defs & ArchDefine604) 1184 Builder.defineMacro("_ARCH_604"); 1185 if (defs & ArchDefinePwr4) 1186 Builder.defineMacro("_ARCH_PWR4"); 1187 if (defs & ArchDefinePwr5) 1188 Builder.defineMacro("_ARCH_PWR5"); 1189 if (defs & ArchDefinePwr5x) 1190 Builder.defineMacro("_ARCH_PWR5X"); 1191 if (defs & ArchDefinePwr6) 1192 Builder.defineMacro("_ARCH_PWR6"); 1193 if (defs & ArchDefinePwr6x) 1194 Builder.defineMacro("_ARCH_PWR6X"); 1195 if (defs & ArchDefinePwr7) 1196 Builder.defineMacro("_ARCH_PWR7"); 1197 if (defs & ArchDefinePwr8) 1198 Builder.defineMacro("_ARCH_PWR8"); 1199 if (defs & ArchDefineA2) 1200 Builder.defineMacro("_ARCH_A2"); 1201 if (defs & ArchDefineA2q) { 1202 Builder.defineMacro("_ARCH_A2Q"); 1203 Builder.defineMacro("_ARCH_QP"); 1204 } 1205 1206 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1207 Builder.defineMacro("__bg__"); 1208 Builder.defineMacro("__THW_BLUEGENE__"); 1209 Builder.defineMacro("__bgq__"); 1210 Builder.defineMacro("__TOS_BGQ__"); 1211 } 1212 1213 if (HasVSX) 1214 Builder.defineMacro("__VSX__"); 1215 if (HasP8Vector) 1216 Builder.defineMacro("__POWER8_VECTOR__"); 1217 if (HasP8Crypto) 1218 Builder.defineMacro("__CRYPTO__"); 1219 if (HasHTM) 1220 Builder.defineMacro("__HTM__"); 1221 1222 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1223 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1224 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1225 if (PointerWidth == 64) 1226 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1227 1228 // FIXME: The following are not yet generated here by Clang, but are 1229 // generated by GCC: 1230 // 1231 // _SOFT_FLOAT_ 1232 // __RECIP_PRECISION__ 1233 // __APPLE_ALTIVEC__ 1234 // __RECIP__ 1235 // __RECIPF__ 1236 // __RSQRTE__ 1237 // __RSQRTEF__ 1238 // _SOFT_DOUBLE_ 1239 // __NO_LWSYNC__ 1240 // __HAVE_BSWAP__ 1241 // __LONGDOUBLE128 1242 // __CMODEL_MEDIUM__ 1243 // __CMODEL_LARGE__ 1244 // _CALL_SYSV 1245 // _CALL_DARWIN 1246 // __NO_FPRS__ 1247 } 1248 1249 // Handle explicit options being passed to the compiler here: if we've 1250 // explicitly turned off vsx and turned on power8-vector or direct-move then 1251 // go ahead and error since the customer has expressed a somewhat incompatible 1252 // set of options. 1253 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1254 const std::vector<std::string> &FeaturesVec) { 1255 1256 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1257 FeaturesVec.end()) { 1258 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1259 FeaturesVec.end()) { 1260 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1261 << "-mno-vsx"; 1262 return false; 1263 } 1264 1265 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1266 FeaturesVec.end()) { 1267 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1268 << "-mno-vsx"; 1269 return false; 1270 } 1271 } 1272 1273 return true; 1274 } 1275 1276 bool PPCTargetInfo::initFeatureMap( 1277 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1278 const std::vector<std::string> &FeaturesVec) const { 1279 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1280 .Case("7400", true) 1281 .Case("g4", true) 1282 .Case("7450", true) 1283 .Case("g4+", true) 1284 .Case("970", true) 1285 .Case("g5", true) 1286 .Case("pwr6", true) 1287 .Case("pwr7", true) 1288 .Case("pwr8", true) 1289 .Case("ppc64", true) 1290 .Case("ppc64le", true) 1291 .Default(false); 1292 1293 Features["qpx"] = (CPU == "a2q"); 1294 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1295 .Case("ppc64le", true) 1296 .Case("pwr8", true) 1297 .Default(false); 1298 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1299 .Case("ppc64le", true) 1300 .Case("pwr8", true) 1301 .Default(false); 1302 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1303 .Case("ppc64le", true) 1304 .Case("pwr8", true) 1305 .Case("pwr7", true) 1306 .Default(false); 1307 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1308 .Case("ppc64le", true) 1309 .Case("pwr8", true) 1310 .Case("pwr7", true) 1311 .Default(false); 1312 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1313 .Case("ppc64le", true) 1314 .Case("pwr8", true) 1315 .Default(false); 1316 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1317 .Case("ppc64le", true) 1318 .Case("pwr8", true) 1319 .Case("pwr7", true) 1320 .Default(false); 1321 1322 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1323 return false; 1324 1325 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1326 } 1327 1328 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1329 return llvm::StringSwitch<bool>(Feature) 1330 .Case("powerpc", true) 1331 .Case("vsx", HasVSX) 1332 .Case("power8-vector", HasP8Vector) 1333 .Case("crypto", HasP8Crypto) 1334 .Case("direct-move", HasDirectMove) 1335 .Case("qpx", HasQPX) 1336 .Case("htm", HasHTM) 1337 .Case("bpermd", HasBPERMD) 1338 .Case("extdiv", HasExtDiv) 1339 .Default(false); 1340 } 1341 1342 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1343 StringRef Name, bool Enabled) const { 1344 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1345 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1346 // incompatible options. 1347 if (Enabled) { 1348 if (Name == "vsx") { 1349 Features[Name] = true; 1350 } else if (Name == "direct-move") { 1351 Features[Name] = Features["vsx"] = true; 1352 } else if (Name == "power8-vector") { 1353 Features[Name] = Features["vsx"] = true; 1354 } else { 1355 Features[Name] = true; 1356 } 1357 } else { 1358 if (Name == "vsx") { 1359 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1360 false; 1361 } else { 1362 Features[Name] = false; 1363 } 1364 } 1365 } 1366 1367 const char * const PPCTargetInfo::GCCRegNames[] = { 1368 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1369 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1370 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1371 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1372 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1373 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1374 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1375 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1376 "mq", "lr", "ctr", "ap", 1377 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1378 "xer", 1379 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1380 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1381 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1382 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1383 "vrsave", "vscr", 1384 "spe_acc", "spefscr", 1385 "sfp" 1386 }; 1387 1388 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1389 return llvm::makeArrayRef(GCCRegNames); 1390 } 1391 1392 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1393 // While some of these aliases do map to different registers 1394 // they still share the same register name. 1395 { { "0" }, "r0" }, 1396 { { "1"}, "r1" }, 1397 { { "2" }, "r2" }, 1398 { { "3" }, "r3" }, 1399 { { "4" }, "r4" }, 1400 { { "5" }, "r5" }, 1401 { { "6" }, "r6" }, 1402 { { "7" }, "r7" }, 1403 { { "8" }, "r8" }, 1404 { { "9" }, "r9" }, 1405 { { "10" }, "r10" }, 1406 { { "11" }, "r11" }, 1407 { { "12" }, "r12" }, 1408 { { "13" }, "r13" }, 1409 { { "14" }, "r14" }, 1410 { { "15" }, "r15" }, 1411 { { "16" }, "r16" }, 1412 { { "17" }, "r17" }, 1413 { { "18" }, "r18" }, 1414 { { "19" }, "r19" }, 1415 { { "20" }, "r20" }, 1416 { { "21" }, "r21" }, 1417 { { "22" }, "r22" }, 1418 { { "23" }, "r23" }, 1419 { { "24" }, "r24" }, 1420 { { "25" }, "r25" }, 1421 { { "26" }, "r26" }, 1422 { { "27" }, "r27" }, 1423 { { "28" }, "r28" }, 1424 { { "29" }, "r29" }, 1425 { { "30" }, "r30" }, 1426 { { "31" }, "r31" }, 1427 { { "fr0" }, "f0" }, 1428 { { "fr1" }, "f1" }, 1429 { { "fr2" }, "f2" }, 1430 { { "fr3" }, "f3" }, 1431 { { "fr4" }, "f4" }, 1432 { { "fr5" }, "f5" }, 1433 { { "fr6" }, "f6" }, 1434 { { "fr7" }, "f7" }, 1435 { { "fr8" }, "f8" }, 1436 { { "fr9" }, "f9" }, 1437 { { "fr10" }, "f10" }, 1438 { { "fr11" }, "f11" }, 1439 { { "fr12" }, "f12" }, 1440 { { "fr13" }, "f13" }, 1441 { { "fr14" }, "f14" }, 1442 { { "fr15" }, "f15" }, 1443 { { "fr16" }, "f16" }, 1444 { { "fr17" }, "f17" }, 1445 { { "fr18" }, "f18" }, 1446 { { "fr19" }, "f19" }, 1447 { { "fr20" }, "f20" }, 1448 { { "fr21" }, "f21" }, 1449 { { "fr22" }, "f22" }, 1450 { { "fr23" }, "f23" }, 1451 { { "fr24" }, "f24" }, 1452 { { "fr25" }, "f25" }, 1453 { { "fr26" }, "f26" }, 1454 { { "fr27" }, "f27" }, 1455 { { "fr28" }, "f28" }, 1456 { { "fr29" }, "f29" }, 1457 { { "fr30" }, "f30" }, 1458 { { "fr31" }, "f31" }, 1459 { { "cc" }, "cr0" }, 1460 }; 1461 1462 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1463 return llvm::makeArrayRef(GCCRegAliases); 1464 } 1465 1466 class PPC32TargetInfo : public PPCTargetInfo { 1467 public: 1468 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1469 DataLayoutString = "E-m:e-p:32:32-i64:64-n32"; 1470 1471 switch (getTriple().getOS()) { 1472 case llvm::Triple::Linux: 1473 case llvm::Triple::FreeBSD: 1474 case llvm::Triple::NetBSD: 1475 SizeType = UnsignedInt; 1476 PtrDiffType = SignedInt; 1477 IntPtrType = SignedInt; 1478 break; 1479 default: 1480 break; 1481 } 1482 1483 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1484 LongDoubleWidth = LongDoubleAlign = 64; 1485 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1486 } 1487 1488 // PPC32 supports atomics up to 4 bytes. 1489 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1490 } 1491 1492 BuiltinVaListKind getBuiltinVaListKind() const override { 1493 // This is the ELF definition, and is overridden by the Darwin sub-target 1494 return TargetInfo::PowerABIBuiltinVaList; 1495 } 1496 }; 1497 1498 // Note: ABI differences may eventually require us to have a separate 1499 // TargetInfo for little endian. 1500 class PPC64TargetInfo : public PPCTargetInfo { 1501 public: 1502 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1503 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1504 IntMaxType = SignedLong; 1505 Int64Type = SignedLong; 1506 1507 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1508 DataLayoutString = "e-m:e-i64:64-n32:64"; 1509 ABI = "elfv2"; 1510 } else { 1511 DataLayoutString = "E-m:e-i64:64-n32:64"; 1512 ABI = "elfv1"; 1513 } 1514 1515 switch (getTriple().getOS()) { 1516 case llvm::Triple::FreeBSD: 1517 LongDoubleWidth = LongDoubleAlign = 64; 1518 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1519 break; 1520 case llvm::Triple::NetBSD: 1521 IntMaxType = SignedLongLong; 1522 Int64Type = SignedLongLong; 1523 break; 1524 default: 1525 break; 1526 } 1527 1528 // PPC64 supports atomics up to 8 bytes. 1529 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1530 } 1531 BuiltinVaListKind getBuiltinVaListKind() const override { 1532 return TargetInfo::CharPtrBuiltinVaList; 1533 } 1534 // PPC64 Linux-specific ABI options. 1535 bool setABI(const std::string &Name) override { 1536 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1537 ABI = Name; 1538 return true; 1539 } 1540 return false; 1541 } 1542 }; 1543 1544 class DarwinPPC32TargetInfo : 1545 public DarwinTargetInfo<PPC32TargetInfo> { 1546 public: 1547 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1548 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1549 HasAlignMac68kSupport = true; 1550 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1551 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1552 LongLongAlign = 32; 1553 SuitableAlign = 128; 1554 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32"; 1555 } 1556 BuiltinVaListKind getBuiltinVaListKind() const override { 1557 return TargetInfo::CharPtrBuiltinVaList; 1558 } 1559 }; 1560 1561 class DarwinPPC64TargetInfo : 1562 public DarwinTargetInfo<PPC64TargetInfo> { 1563 public: 1564 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1565 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1566 HasAlignMac68kSupport = true; 1567 SuitableAlign = 128; 1568 DataLayoutString = "E-m:o-i64:64-n32:64"; 1569 } 1570 }; 1571 1572 static const unsigned NVPTXAddrSpaceMap[] = { 1573 1, // opencl_global 1574 3, // opencl_local 1575 4, // opencl_constant 1576 // FIXME: generic has to be added to the target 1577 0, // opencl_generic 1578 1, // cuda_device 1579 4, // cuda_constant 1580 3, // cuda_shared 1581 }; 1582 1583 class NVPTXTargetInfo : public TargetInfo { 1584 static const char *const GCCRegNames[]; 1585 static const Builtin::Info BuiltinInfo[]; 1586 1587 // The GPU profiles supported by the NVPTX backend 1588 enum GPUKind { 1589 GK_NONE, 1590 GK_SM20, 1591 GK_SM21, 1592 GK_SM30, 1593 GK_SM35, 1594 GK_SM37, 1595 } GPU; 1596 1597 public: 1598 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1599 BigEndian = false; 1600 TLSSupported = false; 1601 LongWidth = LongAlign = 64; 1602 AddrSpaceMap = &NVPTXAddrSpaceMap; 1603 UseAddrSpaceMapMangling = true; 1604 // Define available target features 1605 // These must be defined in sorted order! 1606 NoAsmVariants = true; 1607 // Set the default GPU to sm20 1608 GPU = GK_SM20; 1609 } 1610 void getTargetDefines(const LangOptions &Opts, 1611 MacroBuilder &Builder) const override { 1612 Builder.defineMacro("__PTX__"); 1613 Builder.defineMacro("__NVPTX__"); 1614 if (Opts.CUDAIsDevice) { 1615 // Set __CUDA_ARCH__ for the GPU specified. 1616 std::string CUDAArchCode; 1617 switch (GPU) { 1618 case GK_SM20: 1619 CUDAArchCode = "200"; 1620 break; 1621 case GK_SM21: 1622 CUDAArchCode = "210"; 1623 break; 1624 case GK_SM30: 1625 CUDAArchCode = "300"; 1626 break; 1627 case GK_SM35: 1628 CUDAArchCode = "350"; 1629 break; 1630 case GK_SM37: 1631 CUDAArchCode = "370"; 1632 break; 1633 default: 1634 llvm_unreachable("Unhandled target CPU"); 1635 } 1636 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1637 } 1638 } 1639 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1640 return llvm::makeArrayRef(BuiltinInfo, 1641 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1642 } 1643 bool hasFeature(StringRef Feature) const override { 1644 return Feature == "ptx" || Feature == "nvptx"; 1645 } 1646 1647 ArrayRef<const char *> getGCCRegNames() const override; 1648 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1649 // No aliases. 1650 return None; 1651 } 1652 bool validateAsmConstraint(const char *&Name, 1653 TargetInfo::ConstraintInfo &Info) const override { 1654 switch (*Name) { 1655 default: 1656 return false; 1657 case 'c': 1658 case 'h': 1659 case 'r': 1660 case 'l': 1661 case 'f': 1662 case 'd': 1663 Info.setAllowsRegister(); 1664 return true; 1665 } 1666 } 1667 const char *getClobbers() const override { 1668 // FIXME: Is this really right? 1669 return ""; 1670 } 1671 BuiltinVaListKind getBuiltinVaListKind() const override { 1672 // FIXME: implement 1673 return TargetInfo::CharPtrBuiltinVaList; 1674 } 1675 bool setCPU(const std::string &Name) override { 1676 GPU = llvm::StringSwitch<GPUKind>(Name) 1677 .Case("sm_20", GK_SM20) 1678 .Case("sm_21", GK_SM21) 1679 .Case("sm_30", GK_SM30) 1680 .Case("sm_35", GK_SM35) 1681 .Case("sm_37", GK_SM37) 1682 .Default(GK_NONE); 1683 1684 return GPU != GK_NONE; 1685 } 1686 }; 1687 1688 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1689 #define BUILTIN(ID, TYPE, ATTRS) \ 1690 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1691 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1692 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1693 #include "clang/Basic/BuiltinsNVPTX.def" 1694 }; 1695 1696 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1697 1698 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1699 return llvm::makeArrayRef(GCCRegNames); 1700 } 1701 1702 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1703 public: 1704 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1705 LongWidth = LongAlign = 32; 1706 PointerWidth = PointerAlign = 32; 1707 SizeType = TargetInfo::UnsignedInt; 1708 PtrDiffType = TargetInfo::SignedInt; 1709 IntPtrType = TargetInfo::SignedInt; 1710 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1711 } 1712 }; 1713 1714 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1715 public: 1716 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1717 PointerWidth = PointerAlign = 64; 1718 SizeType = TargetInfo::UnsignedLong; 1719 PtrDiffType = TargetInfo::SignedLong; 1720 IntPtrType = TargetInfo::SignedLong; 1721 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1722 } 1723 }; 1724 1725 static const unsigned AMDGPUAddrSpaceMap[] = { 1726 1, // opencl_global 1727 3, // opencl_local 1728 2, // opencl_constant 1729 4, // opencl_generic 1730 1, // cuda_device 1731 2, // cuda_constant 1732 3 // cuda_shared 1733 }; 1734 1735 // If you edit the description strings, make sure you update 1736 // getPointerWidthV(). 1737 1738 static const char *const DataLayoutStringR600 = 1739 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1740 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1741 1742 static const char *const DataLayoutStringR600DoubleOps = 1743 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1744 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1745 1746 static const char *const DataLayoutStringSI = 1747 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1748 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1749 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1750 1751 class AMDGPUTargetInfo : public TargetInfo { 1752 static const Builtin::Info BuiltinInfo[]; 1753 static const char * const GCCRegNames[]; 1754 1755 /// \brief The GPU profiles supported by the AMDGPU target. 1756 enum GPUKind { 1757 GK_NONE, 1758 GK_R600, 1759 GK_R600_DOUBLE_OPS, 1760 GK_R700, 1761 GK_R700_DOUBLE_OPS, 1762 GK_EVERGREEN, 1763 GK_EVERGREEN_DOUBLE_OPS, 1764 GK_NORTHERN_ISLANDS, 1765 GK_CAYMAN, 1766 GK_SOUTHERN_ISLANDS, 1767 GK_SEA_ISLANDS, 1768 GK_VOLCANIC_ISLANDS 1769 } GPU; 1770 1771 bool hasFP64:1; 1772 bool hasFMAF:1; 1773 bool hasLDEXPF:1; 1774 1775 public: 1776 AMDGPUTargetInfo(const llvm::Triple &Triple) 1777 : TargetInfo(Triple) { 1778 1779 if (Triple.getArch() == llvm::Triple::amdgcn) { 1780 DataLayoutString = DataLayoutStringSI; 1781 GPU = GK_SOUTHERN_ISLANDS; 1782 hasFP64 = true; 1783 hasFMAF = true; 1784 hasLDEXPF = true; 1785 } else { 1786 DataLayoutString = DataLayoutStringR600; 1787 GPU = GK_R600; 1788 hasFP64 = false; 1789 hasFMAF = false; 1790 hasLDEXPF = false; 1791 } 1792 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1793 UseAddrSpaceMapMangling = true; 1794 } 1795 1796 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1797 if (GPU <= GK_CAYMAN) 1798 return 32; 1799 1800 switch(AddrSpace) { 1801 default: 1802 return 64; 1803 case 0: 1804 case 3: 1805 case 5: 1806 return 32; 1807 } 1808 } 1809 1810 const char * getClobbers() const override { 1811 return ""; 1812 } 1813 1814 ArrayRef<const char *> getGCCRegNames() const override; 1815 1816 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1817 return None; 1818 } 1819 1820 bool validateAsmConstraint(const char *&Name, 1821 TargetInfo::ConstraintInfo &info) const override { 1822 return true; 1823 } 1824 1825 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1826 return llvm::makeArrayRef(BuiltinInfo, 1827 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1828 } 1829 1830 void getTargetDefines(const LangOptions &Opts, 1831 MacroBuilder &Builder) const override { 1832 Builder.defineMacro("__R600__"); 1833 if (hasFMAF) 1834 Builder.defineMacro("__HAS_FMAF__"); 1835 if (hasLDEXPF) 1836 Builder.defineMacro("__HAS_LDEXPF__"); 1837 if (hasFP64 && Opts.OpenCL) 1838 Builder.defineMacro("cl_khr_fp64"); 1839 if (Opts.OpenCL) { 1840 if (GPU >= GK_NORTHERN_ISLANDS) { 1841 Builder.defineMacro("cl_khr_byte_addressable_store"); 1842 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1843 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1844 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1845 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1846 } 1847 } 1848 } 1849 1850 BuiltinVaListKind getBuiltinVaListKind() const override { 1851 return TargetInfo::CharPtrBuiltinVaList; 1852 } 1853 1854 bool setCPU(const std::string &Name) override { 1855 GPU = llvm::StringSwitch<GPUKind>(Name) 1856 .Case("r600" , GK_R600) 1857 .Case("rv610", GK_R600) 1858 .Case("rv620", GK_R600) 1859 .Case("rv630", GK_R600) 1860 .Case("rv635", GK_R600) 1861 .Case("rs780", GK_R600) 1862 .Case("rs880", GK_R600) 1863 .Case("rv670", GK_R600_DOUBLE_OPS) 1864 .Case("rv710", GK_R700) 1865 .Case("rv730", GK_R700) 1866 .Case("rv740", GK_R700_DOUBLE_OPS) 1867 .Case("rv770", GK_R700_DOUBLE_OPS) 1868 .Case("palm", GK_EVERGREEN) 1869 .Case("cedar", GK_EVERGREEN) 1870 .Case("sumo", GK_EVERGREEN) 1871 .Case("sumo2", GK_EVERGREEN) 1872 .Case("redwood", GK_EVERGREEN) 1873 .Case("juniper", GK_EVERGREEN) 1874 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1875 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1876 .Case("barts", GK_NORTHERN_ISLANDS) 1877 .Case("turks", GK_NORTHERN_ISLANDS) 1878 .Case("caicos", GK_NORTHERN_ISLANDS) 1879 .Case("cayman", GK_CAYMAN) 1880 .Case("aruba", GK_CAYMAN) 1881 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1882 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1883 .Case("verde", GK_SOUTHERN_ISLANDS) 1884 .Case("oland", GK_SOUTHERN_ISLANDS) 1885 .Case("hainan", GK_SOUTHERN_ISLANDS) 1886 .Case("bonaire", GK_SEA_ISLANDS) 1887 .Case("kabini", GK_SEA_ISLANDS) 1888 .Case("kaveri", GK_SEA_ISLANDS) 1889 .Case("hawaii", GK_SEA_ISLANDS) 1890 .Case("mullins", GK_SEA_ISLANDS) 1891 .Case("tonga", GK_VOLCANIC_ISLANDS) 1892 .Case("iceland", GK_VOLCANIC_ISLANDS) 1893 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1894 .Default(GK_NONE); 1895 1896 if (GPU == GK_NONE) { 1897 return false; 1898 } 1899 1900 // Set the correct data layout 1901 switch (GPU) { 1902 case GK_NONE: 1903 case GK_R600: 1904 case GK_R700: 1905 case GK_EVERGREEN: 1906 case GK_NORTHERN_ISLANDS: 1907 DataLayoutString = DataLayoutStringR600; 1908 hasFP64 = false; 1909 hasFMAF = false; 1910 hasLDEXPF = false; 1911 break; 1912 case GK_R600_DOUBLE_OPS: 1913 case GK_R700_DOUBLE_OPS: 1914 case GK_EVERGREEN_DOUBLE_OPS: 1915 case GK_CAYMAN: 1916 DataLayoutString = DataLayoutStringR600DoubleOps; 1917 hasFP64 = true; 1918 hasFMAF = true; 1919 hasLDEXPF = false; 1920 break; 1921 case GK_SOUTHERN_ISLANDS: 1922 case GK_SEA_ISLANDS: 1923 case GK_VOLCANIC_ISLANDS: 1924 DataLayoutString = DataLayoutStringSI; 1925 hasFP64 = true; 1926 hasFMAF = true; 1927 hasLDEXPF = true; 1928 break; 1929 } 1930 1931 return true; 1932 } 1933 }; 1934 1935 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1936 #define BUILTIN(ID, TYPE, ATTRS) \ 1937 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1938 #include "clang/Basic/BuiltinsAMDGPU.def" 1939 }; 1940 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1941 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1942 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1943 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1944 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1945 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1946 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1947 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1948 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1949 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1950 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1951 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1952 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1953 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1954 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1955 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1956 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1957 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1958 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1959 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1960 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1961 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1962 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1963 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1964 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1965 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1966 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1967 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1968 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1969 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1970 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1971 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1972 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1973 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1974 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1975 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1976 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1977 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1978 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1979 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1980 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1981 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1982 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 1983 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 1984 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 1985 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 1986 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 1987 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 1988 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 1989 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 1990 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 1991 }; 1992 1993 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 1994 return llvm::makeArrayRef(GCCRegNames); 1995 } 1996 1997 // Namespace for x86 abstract base class 1998 const Builtin::Info BuiltinInfo[] = { 1999 #define BUILTIN(ID, TYPE, ATTRS) \ 2000 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2001 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2002 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2003 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2004 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2005 #include "clang/Basic/BuiltinsX86.def" 2006 }; 2007 2008 static const char* const GCCRegNames[] = { 2009 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2010 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2011 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2012 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2013 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2014 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2015 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2016 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2017 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2018 }; 2019 2020 const TargetInfo::AddlRegName AddlRegNames[] = { 2021 { { "al", "ah", "eax", "rax" }, 0 }, 2022 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2023 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2024 { { "dl", "dh", "edx", "rdx" }, 1 }, 2025 { { "esi", "rsi" }, 4 }, 2026 { { "edi", "rdi" }, 5 }, 2027 { { "esp", "rsp" }, 7 }, 2028 { { "ebp", "rbp" }, 6 }, 2029 { { "r8d", "r8w", "r8b" }, 38 }, 2030 { { "r9d", "r9w", "r9b" }, 39 }, 2031 { { "r10d", "r10w", "r10b" }, 40 }, 2032 { { "r11d", "r11w", "r11b" }, 41 }, 2033 { { "r12d", "r12w", "r12b" }, 42 }, 2034 { { "r13d", "r13w", "r13b" }, 43 }, 2035 { { "r14d", "r14w", "r14b" }, 44 }, 2036 { { "r15d", "r15w", "r15b" }, 45 }, 2037 }; 2038 2039 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2040 // most of the implementation can be shared. 2041 class X86TargetInfo : public TargetInfo { 2042 enum X86SSEEnum { 2043 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2044 } SSELevel = NoSSE; 2045 enum MMX3DNowEnum { 2046 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2047 } MMX3DNowLevel = NoMMX3DNow; 2048 enum XOPEnum { 2049 NoXOP, 2050 SSE4A, 2051 FMA4, 2052 XOP 2053 } XOPLevel = NoXOP; 2054 2055 bool HasAES = false; 2056 bool HasPCLMUL = false; 2057 bool HasLZCNT = false; 2058 bool HasRDRND = false; 2059 bool HasFSGSBASE = false; 2060 bool HasBMI = false; 2061 bool HasBMI2 = false; 2062 bool HasPOPCNT = false; 2063 bool HasRTM = false; 2064 bool HasPRFCHW = false; 2065 bool HasRDSEED = false; 2066 bool HasADX = false; 2067 bool HasTBM = false; 2068 bool HasFMA = false; 2069 bool HasF16C = false; 2070 bool HasAVX512CD = false; 2071 bool HasAVX512ER = false; 2072 bool HasAVX512PF = false; 2073 bool HasAVX512DQ = false; 2074 bool HasAVX512BW = false; 2075 bool HasAVX512VL = false; 2076 bool HasSHA = false; 2077 bool HasCX16 = false; 2078 bool HasFXSR = false; 2079 bool HasXSAVE = false; 2080 bool HasXSAVEOPT = false; 2081 bool HasXSAVEC = false; 2082 bool HasXSAVES = false; 2083 2084 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2085 /// 2086 /// Each enumeration represents a particular CPU supported by Clang. These 2087 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2088 enum CPUKind { 2089 CK_Generic, 2090 2091 /// \name i386 2092 /// i386-generation processors. 2093 //@{ 2094 CK_i386, 2095 //@} 2096 2097 /// \name i486 2098 /// i486-generation processors. 2099 //@{ 2100 CK_i486, 2101 CK_WinChipC6, 2102 CK_WinChip2, 2103 CK_C3, 2104 //@} 2105 2106 /// \name i586 2107 /// i586-generation processors, P5 microarchitecture based. 2108 //@{ 2109 CK_i586, 2110 CK_Pentium, 2111 CK_PentiumMMX, 2112 //@} 2113 2114 /// \name i686 2115 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2116 //@{ 2117 CK_i686, 2118 CK_PentiumPro, 2119 CK_Pentium2, 2120 CK_Pentium3, 2121 CK_Pentium3M, 2122 CK_PentiumM, 2123 CK_C3_2, 2124 2125 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2126 /// Clang however has some logic to suport this. 2127 // FIXME: Warn, deprecate, and potentially remove this. 2128 CK_Yonah, 2129 //@} 2130 2131 /// \name Netburst 2132 /// Netburst microarchitecture based processors. 2133 //@{ 2134 CK_Pentium4, 2135 CK_Pentium4M, 2136 CK_Prescott, 2137 CK_Nocona, 2138 //@} 2139 2140 /// \name Core 2141 /// Core microarchitecture based processors. 2142 //@{ 2143 CK_Core2, 2144 2145 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2146 /// codename which GCC no longer accepts as an option to -march, but Clang 2147 /// has some logic for recognizing it. 2148 // FIXME: Warn, deprecate, and potentially remove this. 2149 CK_Penryn, 2150 //@} 2151 2152 /// \name Atom 2153 /// Atom processors 2154 //@{ 2155 CK_Bonnell, 2156 CK_Silvermont, 2157 //@} 2158 2159 /// \name Nehalem 2160 /// Nehalem microarchitecture based processors. 2161 CK_Nehalem, 2162 2163 /// \name Westmere 2164 /// Westmere microarchitecture based processors. 2165 CK_Westmere, 2166 2167 /// \name Sandy Bridge 2168 /// Sandy Bridge microarchitecture based processors. 2169 CK_SandyBridge, 2170 2171 /// \name Ivy Bridge 2172 /// Ivy Bridge microarchitecture based processors. 2173 CK_IvyBridge, 2174 2175 /// \name Haswell 2176 /// Haswell microarchitecture based processors. 2177 CK_Haswell, 2178 2179 /// \name Broadwell 2180 /// Broadwell microarchitecture based processors. 2181 CK_Broadwell, 2182 2183 /// \name Skylake 2184 /// Skylake microarchitecture based processors. 2185 CK_Skylake, 2186 2187 /// \name Knights Landing 2188 /// Knights Landing processor. 2189 CK_KNL, 2190 2191 /// \name K6 2192 /// K6 architecture processors. 2193 //@{ 2194 CK_K6, 2195 CK_K6_2, 2196 CK_K6_3, 2197 //@} 2198 2199 /// \name K7 2200 /// K7 architecture processors. 2201 //@{ 2202 CK_Athlon, 2203 CK_AthlonThunderbird, 2204 CK_Athlon4, 2205 CK_AthlonXP, 2206 CK_AthlonMP, 2207 //@} 2208 2209 /// \name K8 2210 /// K8 architecture processors. 2211 //@{ 2212 CK_Athlon64, 2213 CK_Athlon64SSE3, 2214 CK_AthlonFX, 2215 CK_K8, 2216 CK_K8SSE3, 2217 CK_Opteron, 2218 CK_OpteronSSE3, 2219 CK_AMDFAM10, 2220 //@} 2221 2222 /// \name Bobcat 2223 /// Bobcat architecture processors. 2224 //@{ 2225 CK_BTVER1, 2226 CK_BTVER2, 2227 //@} 2228 2229 /// \name Bulldozer 2230 /// Bulldozer architecture processors. 2231 //@{ 2232 CK_BDVER1, 2233 CK_BDVER2, 2234 CK_BDVER3, 2235 CK_BDVER4, 2236 //@} 2237 2238 /// This specification is deprecated and will be removed in the future. 2239 /// Users should prefer \see CK_K8. 2240 // FIXME: Warn on this when the CPU is set to it. 2241 //@{ 2242 CK_x86_64, 2243 //@} 2244 2245 /// \name Geode 2246 /// Geode processors. 2247 //@{ 2248 CK_Geode 2249 //@} 2250 } CPU = CK_Generic; 2251 2252 CPUKind getCPUKind(StringRef CPU) const { 2253 return llvm::StringSwitch<CPUKind>(CPU) 2254 .Case("i386", CK_i386) 2255 .Case("i486", CK_i486) 2256 .Case("winchip-c6", CK_WinChipC6) 2257 .Case("winchip2", CK_WinChip2) 2258 .Case("c3", CK_C3) 2259 .Case("i586", CK_i586) 2260 .Case("pentium", CK_Pentium) 2261 .Case("pentium-mmx", CK_PentiumMMX) 2262 .Case("i686", CK_i686) 2263 .Case("pentiumpro", CK_PentiumPro) 2264 .Case("pentium2", CK_Pentium2) 2265 .Case("pentium3", CK_Pentium3) 2266 .Case("pentium3m", CK_Pentium3M) 2267 .Case("pentium-m", CK_PentiumM) 2268 .Case("c3-2", CK_C3_2) 2269 .Case("yonah", CK_Yonah) 2270 .Case("pentium4", CK_Pentium4) 2271 .Case("pentium4m", CK_Pentium4M) 2272 .Case("prescott", CK_Prescott) 2273 .Case("nocona", CK_Nocona) 2274 .Case("core2", CK_Core2) 2275 .Case("penryn", CK_Penryn) 2276 .Case("bonnell", CK_Bonnell) 2277 .Case("atom", CK_Bonnell) // Legacy name. 2278 .Case("silvermont", CK_Silvermont) 2279 .Case("slm", CK_Silvermont) // Legacy name. 2280 .Case("nehalem", CK_Nehalem) 2281 .Case("corei7", CK_Nehalem) // Legacy name. 2282 .Case("westmere", CK_Westmere) 2283 .Case("sandybridge", CK_SandyBridge) 2284 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2285 .Case("ivybridge", CK_IvyBridge) 2286 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2287 .Case("haswell", CK_Haswell) 2288 .Case("core-avx2", CK_Haswell) // Legacy name. 2289 .Case("broadwell", CK_Broadwell) 2290 .Case("skylake", CK_Skylake) 2291 .Case("skx", CK_Skylake) // Legacy name. 2292 .Case("knl", CK_KNL) 2293 .Case("k6", CK_K6) 2294 .Case("k6-2", CK_K6_2) 2295 .Case("k6-3", CK_K6_3) 2296 .Case("athlon", CK_Athlon) 2297 .Case("athlon-tbird", CK_AthlonThunderbird) 2298 .Case("athlon-4", CK_Athlon4) 2299 .Case("athlon-xp", CK_AthlonXP) 2300 .Case("athlon-mp", CK_AthlonMP) 2301 .Case("athlon64", CK_Athlon64) 2302 .Case("athlon64-sse3", CK_Athlon64SSE3) 2303 .Case("athlon-fx", CK_AthlonFX) 2304 .Case("k8", CK_K8) 2305 .Case("k8-sse3", CK_K8SSE3) 2306 .Case("opteron", CK_Opteron) 2307 .Case("opteron-sse3", CK_OpteronSSE3) 2308 .Case("barcelona", CK_AMDFAM10) 2309 .Case("amdfam10", CK_AMDFAM10) 2310 .Case("btver1", CK_BTVER1) 2311 .Case("btver2", CK_BTVER2) 2312 .Case("bdver1", CK_BDVER1) 2313 .Case("bdver2", CK_BDVER2) 2314 .Case("bdver3", CK_BDVER3) 2315 .Case("bdver4", CK_BDVER4) 2316 .Case("x86-64", CK_x86_64) 2317 .Case("geode", CK_Geode) 2318 .Default(CK_Generic); 2319 } 2320 2321 enum FPMathKind { 2322 FP_Default, 2323 FP_SSE, 2324 FP_387 2325 } FPMath = FP_Default; 2326 2327 public: 2328 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 2329 BigEndian = false; 2330 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2331 } 2332 unsigned getFloatEvalMethod() const override { 2333 // X87 evaluates with 80 bits "long double" precision. 2334 return SSELevel == NoSSE ? 2 : 0; 2335 } 2336 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2337 return llvm::makeArrayRef(BuiltinInfo, 2338 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2339 } 2340 ArrayRef<const char *> getGCCRegNames() const override { 2341 return llvm::makeArrayRef(GCCRegNames); 2342 } 2343 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2344 return None; 2345 } 2346 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2347 return llvm::makeArrayRef(AddlRegNames); 2348 } 2349 bool validateCpuSupports(StringRef Name) const override; 2350 bool validateAsmConstraint(const char *&Name, 2351 TargetInfo::ConstraintInfo &info) const override; 2352 2353 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2354 2355 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2356 2357 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2358 2359 std::string convertConstraint(const char *&Constraint) const override; 2360 const char *getClobbers() const override { 2361 return "~{dirflag},~{fpsr},~{flags}"; 2362 } 2363 void getTargetDefines(const LangOptions &Opts, 2364 MacroBuilder &Builder) const override; 2365 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2366 bool Enabled); 2367 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2368 bool Enabled); 2369 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2370 bool Enabled); 2371 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2372 StringRef Name, bool Enabled) const override { 2373 setFeatureEnabledImpl(Features, Name, Enabled); 2374 } 2375 // This exists purely to cut down on the number of virtual calls in 2376 // initFeatureMap which calls this repeatedly. 2377 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2378 StringRef Name, bool Enabled); 2379 bool 2380 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2381 StringRef CPU, 2382 const std::vector<std::string> &FeaturesVec) const override; 2383 bool hasFeature(StringRef Feature) const override; 2384 bool handleTargetFeatures(std::vector<std::string> &Features, 2385 DiagnosticsEngine &Diags) override; 2386 StringRef getABI() const override { 2387 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2388 return "avx512"; 2389 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2390 return "avx"; 2391 if (getTriple().getArch() == llvm::Triple::x86 && 2392 MMX3DNowLevel == NoMMX3DNow) 2393 return "no-mmx"; 2394 return ""; 2395 } 2396 bool setCPU(const std::string &Name) override { 2397 CPU = getCPUKind(Name); 2398 2399 // Perform any per-CPU checks necessary to determine if this CPU is 2400 // acceptable. 2401 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2402 // invalid without explaining *why*. 2403 switch (CPU) { 2404 case CK_Generic: 2405 // No processor selected! 2406 return false; 2407 2408 case CK_i386: 2409 case CK_i486: 2410 case CK_WinChipC6: 2411 case CK_WinChip2: 2412 case CK_C3: 2413 case CK_i586: 2414 case CK_Pentium: 2415 case CK_PentiumMMX: 2416 case CK_i686: 2417 case CK_PentiumPro: 2418 case CK_Pentium2: 2419 case CK_Pentium3: 2420 case CK_Pentium3M: 2421 case CK_PentiumM: 2422 case CK_Yonah: 2423 case CK_C3_2: 2424 case CK_Pentium4: 2425 case CK_Pentium4M: 2426 case CK_Prescott: 2427 case CK_K6: 2428 case CK_K6_2: 2429 case CK_K6_3: 2430 case CK_Athlon: 2431 case CK_AthlonThunderbird: 2432 case CK_Athlon4: 2433 case CK_AthlonXP: 2434 case CK_AthlonMP: 2435 case CK_Geode: 2436 // Only accept certain architectures when compiling in 32-bit mode. 2437 if (getTriple().getArch() != llvm::Triple::x86) 2438 return false; 2439 2440 // Fallthrough 2441 case CK_Nocona: 2442 case CK_Core2: 2443 case CK_Penryn: 2444 case CK_Bonnell: 2445 case CK_Silvermont: 2446 case CK_Nehalem: 2447 case CK_Westmere: 2448 case CK_SandyBridge: 2449 case CK_IvyBridge: 2450 case CK_Haswell: 2451 case CK_Broadwell: 2452 case CK_Skylake: 2453 case CK_KNL: 2454 case CK_Athlon64: 2455 case CK_Athlon64SSE3: 2456 case CK_AthlonFX: 2457 case CK_K8: 2458 case CK_K8SSE3: 2459 case CK_Opteron: 2460 case CK_OpteronSSE3: 2461 case CK_AMDFAM10: 2462 case CK_BTVER1: 2463 case CK_BTVER2: 2464 case CK_BDVER1: 2465 case CK_BDVER2: 2466 case CK_BDVER3: 2467 case CK_BDVER4: 2468 case CK_x86_64: 2469 return true; 2470 } 2471 llvm_unreachable("Unhandled CPU kind"); 2472 } 2473 2474 bool setFPMath(StringRef Name) override; 2475 2476 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2477 // We accept all non-ARM calling conventions 2478 return (CC == CC_X86ThisCall || 2479 CC == CC_X86FastCall || 2480 CC == CC_X86StdCall || 2481 CC == CC_X86VectorCall || 2482 CC == CC_C || 2483 CC == CC_X86Pascal || 2484 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2485 } 2486 2487 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2488 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2489 } 2490 2491 bool hasSjLjLowering() const override { 2492 return true; 2493 } 2494 }; 2495 2496 bool X86TargetInfo::setFPMath(StringRef Name) { 2497 if (Name == "387") { 2498 FPMath = FP_387; 2499 return true; 2500 } 2501 if (Name == "sse") { 2502 FPMath = FP_SSE; 2503 return true; 2504 } 2505 return false; 2506 } 2507 2508 bool X86TargetInfo::initFeatureMap( 2509 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2510 const std::vector<std::string> &FeaturesVec) const { 2511 // FIXME: This *really* should not be here. 2512 // X86_64 always has SSE2. 2513 if (getTriple().getArch() == llvm::Triple::x86_64) 2514 setFeatureEnabledImpl(Features, "sse2", true); 2515 2516 switch (getCPUKind(CPU)) { 2517 case CK_Generic: 2518 case CK_i386: 2519 case CK_i486: 2520 case CK_i586: 2521 case CK_Pentium: 2522 case CK_i686: 2523 case CK_PentiumPro: 2524 break; 2525 case CK_PentiumMMX: 2526 case CK_Pentium2: 2527 case CK_K6: 2528 case CK_WinChipC6: 2529 setFeatureEnabledImpl(Features, "mmx", true); 2530 break; 2531 case CK_Pentium3: 2532 case CK_Pentium3M: 2533 case CK_C3_2: 2534 setFeatureEnabledImpl(Features, "sse", true); 2535 setFeatureEnabledImpl(Features, "fxsr", true); 2536 break; 2537 case CK_PentiumM: 2538 case CK_Pentium4: 2539 case CK_Pentium4M: 2540 case CK_x86_64: 2541 setFeatureEnabledImpl(Features, "sse2", true); 2542 setFeatureEnabledImpl(Features, "fxsr", true); 2543 break; 2544 case CK_Yonah: 2545 case CK_Prescott: 2546 case CK_Nocona: 2547 setFeatureEnabledImpl(Features, "sse3", true); 2548 setFeatureEnabledImpl(Features, "fxsr", true); 2549 setFeatureEnabledImpl(Features, "cx16", true); 2550 break; 2551 case CK_Core2: 2552 case CK_Bonnell: 2553 setFeatureEnabledImpl(Features, "ssse3", true); 2554 setFeatureEnabledImpl(Features, "fxsr", true); 2555 setFeatureEnabledImpl(Features, "cx16", true); 2556 break; 2557 case CK_Penryn: 2558 setFeatureEnabledImpl(Features, "sse4.1", true); 2559 setFeatureEnabledImpl(Features, "fxsr", true); 2560 setFeatureEnabledImpl(Features, "cx16", true); 2561 break; 2562 case CK_Skylake: 2563 setFeatureEnabledImpl(Features, "avx512f", true); 2564 setFeatureEnabledImpl(Features, "avx512cd", true); 2565 setFeatureEnabledImpl(Features, "avx512dq", true); 2566 setFeatureEnabledImpl(Features, "avx512bw", true); 2567 setFeatureEnabledImpl(Features, "avx512vl", true); 2568 setFeatureEnabledImpl(Features, "xsavec", true); 2569 setFeatureEnabledImpl(Features, "xsaves", true); 2570 // FALLTHROUGH 2571 case CK_Broadwell: 2572 setFeatureEnabledImpl(Features, "rdseed", true); 2573 setFeatureEnabledImpl(Features, "adx", true); 2574 // FALLTHROUGH 2575 case CK_Haswell: 2576 setFeatureEnabledImpl(Features, "avx2", true); 2577 setFeatureEnabledImpl(Features, "lzcnt", true); 2578 setFeatureEnabledImpl(Features, "bmi", true); 2579 setFeatureEnabledImpl(Features, "bmi2", true); 2580 setFeatureEnabledImpl(Features, "rtm", true); 2581 setFeatureEnabledImpl(Features, "fma", true); 2582 // FALLTHROUGH 2583 case CK_IvyBridge: 2584 setFeatureEnabledImpl(Features, "rdrnd", true); 2585 setFeatureEnabledImpl(Features, "f16c", true); 2586 setFeatureEnabledImpl(Features, "fsgsbase", true); 2587 // FALLTHROUGH 2588 case CK_SandyBridge: 2589 setFeatureEnabledImpl(Features, "avx", true); 2590 setFeatureEnabledImpl(Features, "xsave", true); 2591 setFeatureEnabledImpl(Features, "xsaveopt", true); 2592 // FALLTHROUGH 2593 case CK_Westmere: 2594 case CK_Silvermont: 2595 setFeatureEnabledImpl(Features, "aes", true); 2596 setFeatureEnabledImpl(Features, "pclmul", true); 2597 // FALLTHROUGH 2598 case CK_Nehalem: 2599 setFeatureEnabledImpl(Features, "sse4.2", true); 2600 setFeatureEnabledImpl(Features, "fxsr", true); 2601 setFeatureEnabledImpl(Features, "cx16", true); 2602 break; 2603 case CK_KNL: 2604 setFeatureEnabledImpl(Features, "avx512f", true); 2605 setFeatureEnabledImpl(Features, "avx512cd", true); 2606 setFeatureEnabledImpl(Features, "avx512er", true); 2607 setFeatureEnabledImpl(Features, "avx512pf", true); 2608 setFeatureEnabledImpl(Features, "fxsr", true); 2609 setFeatureEnabledImpl(Features, "rdseed", true); 2610 setFeatureEnabledImpl(Features, "adx", true); 2611 setFeatureEnabledImpl(Features, "lzcnt", true); 2612 setFeatureEnabledImpl(Features, "bmi", true); 2613 setFeatureEnabledImpl(Features, "bmi2", true); 2614 setFeatureEnabledImpl(Features, "rtm", true); 2615 setFeatureEnabledImpl(Features, "fma", true); 2616 setFeatureEnabledImpl(Features, "rdrnd", true); 2617 setFeatureEnabledImpl(Features, "f16c", true); 2618 setFeatureEnabledImpl(Features, "fsgsbase", true); 2619 setFeatureEnabledImpl(Features, "aes", true); 2620 setFeatureEnabledImpl(Features, "pclmul", true); 2621 setFeatureEnabledImpl(Features, "cx16", true); 2622 setFeatureEnabledImpl(Features, "xsaveopt", true); 2623 setFeatureEnabledImpl(Features, "xsave", true); 2624 break; 2625 case CK_K6_2: 2626 case CK_K6_3: 2627 case CK_WinChip2: 2628 case CK_C3: 2629 setFeatureEnabledImpl(Features, "3dnow", true); 2630 break; 2631 case CK_Athlon: 2632 case CK_AthlonThunderbird: 2633 case CK_Geode: 2634 setFeatureEnabledImpl(Features, "3dnowa", true); 2635 break; 2636 case CK_Athlon4: 2637 case CK_AthlonXP: 2638 case CK_AthlonMP: 2639 setFeatureEnabledImpl(Features, "sse", true); 2640 setFeatureEnabledImpl(Features, "3dnowa", true); 2641 setFeatureEnabledImpl(Features, "fxsr", true); 2642 break; 2643 case CK_K8: 2644 case CK_Opteron: 2645 case CK_Athlon64: 2646 case CK_AthlonFX: 2647 setFeatureEnabledImpl(Features, "sse2", true); 2648 setFeatureEnabledImpl(Features, "3dnowa", true); 2649 setFeatureEnabledImpl(Features, "fxsr", true); 2650 break; 2651 case CK_AMDFAM10: 2652 setFeatureEnabledImpl(Features, "sse4a", true); 2653 setFeatureEnabledImpl(Features, "lzcnt", true); 2654 setFeatureEnabledImpl(Features, "popcnt", true); 2655 // FALLTHROUGH 2656 case CK_K8SSE3: 2657 case CK_OpteronSSE3: 2658 case CK_Athlon64SSE3: 2659 setFeatureEnabledImpl(Features, "sse3", true); 2660 setFeatureEnabledImpl(Features, "3dnowa", true); 2661 setFeatureEnabledImpl(Features, "fxsr", true); 2662 break; 2663 case CK_BTVER2: 2664 setFeatureEnabledImpl(Features, "avx", true); 2665 setFeatureEnabledImpl(Features, "aes", true); 2666 setFeatureEnabledImpl(Features, "pclmul", true); 2667 setFeatureEnabledImpl(Features, "bmi", true); 2668 setFeatureEnabledImpl(Features, "f16c", true); 2669 setFeatureEnabledImpl(Features, "xsaveopt", true); 2670 // FALLTHROUGH 2671 case CK_BTVER1: 2672 setFeatureEnabledImpl(Features, "ssse3", true); 2673 setFeatureEnabledImpl(Features, "sse4a", true); 2674 setFeatureEnabledImpl(Features, "lzcnt", true); 2675 setFeatureEnabledImpl(Features, "popcnt", true); 2676 setFeatureEnabledImpl(Features, "prfchw", true); 2677 setFeatureEnabledImpl(Features, "cx16", true); 2678 setFeatureEnabledImpl(Features, "fxsr", true); 2679 setFeatureEnabledImpl(Features, "xsave", true); 2680 break; 2681 case CK_BDVER4: 2682 setFeatureEnabledImpl(Features, "avx2", true); 2683 setFeatureEnabledImpl(Features, "bmi2", true); 2684 // FALLTHROUGH 2685 case CK_BDVER3: 2686 setFeatureEnabledImpl(Features, "fsgsbase", true); 2687 setFeatureEnabledImpl(Features, "xsaveopt", true); 2688 // FALLTHROUGH 2689 case CK_BDVER2: 2690 setFeatureEnabledImpl(Features, "bmi", true); 2691 setFeatureEnabledImpl(Features, "fma", true); 2692 setFeatureEnabledImpl(Features, "f16c", true); 2693 setFeatureEnabledImpl(Features, "tbm", true); 2694 // FALLTHROUGH 2695 case CK_BDVER1: 2696 // xop implies avx, sse4a and fma4. 2697 setFeatureEnabledImpl(Features, "xop", true); 2698 setFeatureEnabledImpl(Features, "lzcnt", true); 2699 setFeatureEnabledImpl(Features, "aes", true); 2700 setFeatureEnabledImpl(Features, "pclmul", true); 2701 setFeatureEnabledImpl(Features, "prfchw", true); 2702 setFeatureEnabledImpl(Features, "cx16", true); 2703 setFeatureEnabledImpl(Features, "fxsr", true); 2704 setFeatureEnabledImpl(Features, "xsave", true); 2705 break; 2706 } 2707 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2708 return false; 2709 2710 // Can't do this earlier because we need to be able to explicitly enable 2711 // or disable these features and the things that they depend upon. 2712 2713 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2714 auto I = Features.find("sse4.2"); 2715 if (I != Features.end() && I->getValue() == true && 2716 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2717 FeaturesVec.end()) 2718 Features["popcnt"] = true; 2719 2720 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2721 I = Features.find("3dnow"); 2722 if (I != Features.end() && I->getValue() == true && 2723 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2724 FeaturesVec.end()) 2725 Features["prfchw"] = true; 2726 2727 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2728 // then enable MMX. 2729 I = Features.find("sse"); 2730 if (I != Features.end() && I->getValue() == true && 2731 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2732 FeaturesVec.end()) 2733 Features["mmx"] = true; 2734 2735 return true; 2736 } 2737 2738 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2739 X86SSEEnum Level, bool Enabled) { 2740 if (Enabled) { 2741 switch (Level) { 2742 case AVX512F: 2743 Features["avx512f"] = true; 2744 case AVX2: 2745 Features["avx2"] = true; 2746 case AVX: 2747 Features["avx"] = true; 2748 Features["xsave"] = true; 2749 case SSE42: 2750 Features["sse4.2"] = true; 2751 case SSE41: 2752 Features["sse4.1"] = true; 2753 case SSSE3: 2754 Features["ssse3"] = true; 2755 case SSE3: 2756 Features["sse3"] = true; 2757 case SSE2: 2758 Features["sse2"] = true; 2759 case SSE1: 2760 Features["sse"] = true; 2761 case NoSSE: 2762 break; 2763 } 2764 return; 2765 } 2766 2767 switch (Level) { 2768 case NoSSE: 2769 case SSE1: 2770 Features["sse"] = false; 2771 case SSE2: 2772 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2773 Features["sha"] = false; 2774 case SSE3: 2775 Features["sse3"] = false; 2776 setXOPLevel(Features, NoXOP, false); 2777 case SSSE3: 2778 Features["ssse3"] = false; 2779 case SSE41: 2780 Features["sse4.1"] = false; 2781 case SSE42: 2782 Features["sse4.2"] = false; 2783 case AVX: 2784 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2785 Features["xsaveopt"] = false; 2786 setXOPLevel(Features, FMA4, false); 2787 case AVX2: 2788 Features["avx2"] = false; 2789 case AVX512F: 2790 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2791 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2792 Features["avx512vl"] = false; 2793 } 2794 } 2795 2796 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2797 MMX3DNowEnum Level, bool Enabled) { 2798 if (Enabled) { 2799 switch (Level) { 2800 case AMD3DNowAthlon: 2801 Features["3dnowa"] = true; 2802 case AMD3DNow: 2803 Features["3dnow"] = true; 2804 case MMX: 2805 Features["mmx"] = true; 2806 case NoMMX3DNow: 2807 break; 2808 } 2809 return; 2810 } 2811 2812 switch (Level) { 2813 case NoMMX3DNow: 2814 case MMX: 2815 Features["mmx"] = false; 2816 case AMD3DNow: 2817 Features["3dnow"] = false; 2818 case AMD3DNowAthlon: 2819 Features["3dnowa"] = false; 2820 } 2821 } 2822 2823 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2824 bool Enabled) { 2825 if (Enabled) { 2826 switch (Level) { 2827 case XOP: 2828 Features["xop"] = true; 2829 case FMA4: 2830 Features["fma4"] = true; 2831 setSSELevel(Features, AVX, true); 2832 case SSE4A: 2833 Features["sse4a"] = true; 2834 setSSELevel(Features, SSE3, true); 2835 case NoXOP: 2836 break; 2837 } 2838 return; 2839 } 2840 2841 switch (Level) { 2842 case NoXOP: 2843 case SSE4A: 2844 Features["sse4a"] = false; 2845 case FMA4: 2846 Features["fma4"] = false; 2847 case XOP: 2848 Features["xop"] = false; 2849 } 2850 } 2851 2852 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2853 StringRef Name, bool Enabled) { 2854 // This is a bit of a hack to deal with the sse4 target feature when used 2855 // as part of the target attribute. We handle sse4 correctly everywhere 2856 // else. See below for more information on how we handle the sse4 options. 2857 if (Name != "sse4") 2858 Features[Name] = Enabled; 2859 2860 if (Name == "mmx") { 2861 setMMXLevel(Features, MMX, Enabled); 2862 } else if (Name == "sse") { 2863 setSSELevel(Features, SSE1, Enabled); 2864 } else if (Name == "sse2") { 2865 setSSELevel(Features, SSE2, Enabled); 2866 } else if (Name == "sse3") { 2867 setSSELevel(Features, SSE3, Enabled); 2868 } else if (Name == "ssse3") { 2869 setSSELevel(Features, SSSE3, Enabled); 2870 } else if (Name == "sse4.2") { 2871 setSSELevel(Features, SSE42, Enabled); 2872 } else if (Name == "sse4.1") { 2873 setSSELevel(Features, SSE41, Enabled); 2874 } else if (Name == "3dnow") { 2875 setMMXLevel(Features, AMD3DNow, Enabled); 2876 } else if (Name == "3dnowa") { 2877 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2878 } else if (Name == "aes") { 2879 if (Enabled) 2880 setSSELevel(Features, SSE2, Enabled); 2881 } else if (Name == "pclmul") { 2882 if (Enabled) 2883 setSSELevel(Features, SSE2, Enabled); 2884 } else if (Name == "avx") { 2885 setSSELevel(Features, AVX, Enabled); 2886 } else if (Name == "avx2") { 2887 setSSELevel(Features, AVX2, Enabled); 2888 } else if (Name == "avx512f") { 2889 setSSELevel(Features, AVX512F, Enabled); 2890 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2891 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2892 if (Enabled) 2893 setSSELevel(Features, AVX512F, Enabled); 2894 } else if (Name == "fma") { 2895 if (Enabled) 2896 setSSELevel(Features, AVX, Enabled); 2897 } else if (Name == "fma4") { 2898 setXOPLevel(Features, FMA4, Enabled); 2899 } else if (Name == "xop") { 2900 setXOPLevel(Features, XOP, Enabled); 2901 } else if (Name == "sse4a") { 2902 setXOPLevel(Features, SSE4A, Enabled); 2903 } else if (Name == "f16c") { 2904 if (Enabled) 2905 setSSELevel(Features, AVX, Enabled); 2906 } else if (Name == "sha") { 2907 if (Enabled) 2908 setSSELevel(Features, SSE2, Enabled); 2909 } else if (Name == "sse4") { 2910 // We can get here via the __target__ attribute since that's not controlled 2911 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2912 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2913 // disabled. 2914 if (Enabled) 2915 setSSELevel(Features, SSE42, Enabled); 2916 else 2917 setSSELevel(Features, SSE41, Enabled); 2918 } else if (Name == "xsave") { 2919 if (Enabled) 2920 setSSELevel(Features, AVX, Enabled); 2921 else 2922 Features["xsaveopt"] = false; 2923 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 2924 if (Enabled) { 2925 Features["xsave"] = true; 2926 setSSELevel(Features, AVX, Enabled); 2927 } 2928 } 2929 } 2930 2931 /// handleTargetFeatures - Perform initialization based on the user 2932 /// configured set of features. 2933 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2934 DiagnosticsEngine &Diags) { 2935 for (const auto &Feature : Features) { 2936 if (Feature[0] != '+') 2937 continue; 2938 2939 if (Feature == "+aes") { 2940 HasAES = true; 2941 } else if (Feature == "+pclmul") { 2942 HasPCLMUL = true; 2943 } else if (Feature == "+lzcnt") { 2944 HasLZCNT = true; 2945 } else if (Feature == "+rdrnd") { 2946 HasRDRND = true; 2947 } else if (Feature == "+fsgsbase") { 2948 HasFSGSBASE = true; 2949 } else if (Feature == "+bmi") { 2950 HasBMI = true; 2951 } else if (Feature == "+bmi2") { 2952 HasBMI2 = true; 2953 } else if (Feature == "+popcnt") { 2954 HasPOPCNT = true; 2955 } else if (Feature == "+rtm") { 2956 HasRTM = true; 2957 } else if (Feature == "+prfchw") { 2958 HasPRFCHW = true; 2959 } else if (Feature == "+rdseed") { 2960 HasRDSEED = true; 2961 } else if (Feature == "+adx") { 2962 HasADX = true; 2963 } else if (Feature == "+tbm") { 2964 HasTBM = true; 2965 } else if (Feature == "+fma") { 2966 HasFMA = true; 2967 } else if (Feature == "+f16c") { 2968 HasF16C = true; 2969 } else if (Feature == "+avx512cd") { 2970 HasAVX512CD = true; 2971 } else if (Feature == "+avx512er") { 2972 HasAVX512ER = true; 2973 } else if (Feature == "+avx512pf") { 2974 HasAVX512PF = true; 2975 } else if (Feature == "+avx512dq") { 2976 HasAVX512DQ = true; 2977 } else if (Feature == "+avx512bw") { 2978 HasAVX512BW = true; 2979 } else if (Feature == "+avx512vl") { 2980 HasAVX512VL = true; 2981 } else if (Feature == "+sha") { 2982 HasSHA = true; 2983 } else if (Feature == "+cx16") { 2984 HasCX16 = true; 2985 } else if (Feature == "+fxsr") { 2986 HasFXSR = true; 2987 } else if (Feature == "+xsave") { 2988 HasXSAVE = true; 2989 } else if (Feature == "+xsaveopt") { 2990 HasXSAVEOPT = true; 2991 } else if (Feature == "+xsavec") { 2992 HasXSAVEC = true; 2993 } else if (Feature == "+xsaves") { 2994 HasXSAVES = true; 2995 } 2996 2997 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2998 .Case("+avx512f", AVX512F) 2999 .Case("+avx2", AVX2) 3000 .Case("+avx", AVX) 3001 .Case("+sse4.2", SSE42) 3002 .Case("+sse4.1", SSE41) 3003 .Case("+ssse3", SSSE3) 3004 .Case("+sse3", SSE3) 3005 .Case("+sse2", SSE2) 3006 .Case("+sse", SSE1) 3007 .Default(NoSSE); 3008 SSELevel = std::max(SSELevel, Level); 3009 3010 MMX3DNowEnum ThreeDNowLevel = 3011 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3012 .Case("+3dnowa", AMD3DNowAthlon) 3013 .Case("+3dnow", AMD3DNow) 3014 .Case("+mmx", MMX) 3015 .Default(NoMMX3DNow); 3016 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3017 3018 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3019 .Case("+xop", XOP) 3020 .Case("+fma4", FMA4) 3021 .Case("+sse4a", SSE4A) 3022 .Default(NoXOP); 3023 XOPLevel = std::max(XOPLevel, XLevel); 3024 } 3025 3026 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3027 // matches the selected sse level. 3028 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3029 (FPMath == FP_387 && SSELevel >= SSE1)) { 3030 Diags.Report(diag::err_target_unsupported_fpmath) << 3031 (FPMath == FP_SSE ? "sse" : "387"); 3032 return false; 3033 } 3034 3035 SimdDefaultAlign = 3036 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3037 return true; 3038 } 3039 3040 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3041 /// definitions for this particular subtarget. 3042 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3043 MacroBuilder &Builder) const { 3044 // Target identification. 3045 if (getTriple().getArch() == llvm::Triple::x86_64) { 3046 Builder.defineMacro("__amd64__"); 3047 Builder.defineMacro("__amd64"); 3048 Builder.defineMacro("__x86_64"); 3049 Builder.defineMacro("__x86_64__"); 3050 if (getTriple().getArchName() == "x86_64h") { 3051 Builder.defineMacro("__x86_64h"); 3052 Builder.defineMacro("__x86_64h__"); 3053 } 3054 } else { 3055 DefineStd(Builder, "i386", Opts); 3056 } 3057 3058 // Subtarget options. 3059 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3060 // truly should be based on -mtune options. 3061 switch (CPU) { 3062 case CK_Generic: 3063 break; 3064 case CK_i386: 3065 // The rest are coming from the i386 define above. 3066 Builder.defineMacro("__tune_i386__"); 3067 break; 3068 case CK_i486: 3069 case CK_WinChipC6: 3070 case CK_WinChip2: 3071 case CK_C3: 3072 defineCPUMacros(Builder, "i486"); 3073 break; 3074 case CK_PentiumMMX: 3075 Builder.defineMacro("__pentium_mmx__"); 3076 Builder.defineMacro("__tune_pentium_mmx__"); 3077 // Fallthrough 3078 case CK_i586: 3079 case CK_Pentium: 3080 defineCPUMacros(Builder, "i586"); 3081 defineCPUMacros(Builder, "pentium"); 3082 break; 3083 case CK_Pentium3: 3084 case CK_Pentium3M: 3085 case CK_PentiumM: 3086 Builder.defineMacro("__tune_pentium3__"); 3087 // Fallthrough 3088 case CK_Pentium2: 3089 case CK_C3_2: 3090 Builder.defineMacro("__tune_pentium2__"); 3091 // Fallthrough 3092 case CK_PentiumPro: 3093 Builder.defineMacro("__tune_i686__"); 3094 Builder.defineMacro("__tune_pentiumpro__"); 3095 // Fallthrough 3096 case CK_i686: 3097 Builder.defineMacro("__i686"); 3098 Builder.defineMacro("__i686__"); 3099 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3100 Builder.defineMacro("__pentiumpro"); 3101 Builder.defineMacro("__pentiumpro__"); 3102 break; 3103 case CK_Pentium4: 3104 case CK_Pentium4M: 3105 defineCPUMacros(Builder, "pentium4"); 3106 break; 3107 case CK_Yonah: 3108 case CK_Prescott: 3109 case CK_Nocona: 3110 defineCPUMacros(Builder, "nocona"); 3111 break; 3112 case CK_Core2: 3113 case CK_Penryn: 3114 defineCPUMacros(Builder, "core2"); 3115 break; 3116 case CK_Bonnell: 3117 defineCPUMacros(Builder, "atom"); 3118 break; 3119 case CK_Silvermont: 3120 defineCPUMacros(Builder, "slm"); 3121 break; 3122 case CK_Nehalem: 3123 case CK_Westmere: 3124 case CK_SandyBridge: 3125 case CK_IvyBridge: 3126 case CK_Haswell: 3127 case CK_Broadwell: 3128 // FIXME: Historically, we defined this legacy name, it would be nice to 3129 // remove it at some point. We've never exposed fine-grained names for 3130 // recent primary x86 CPUs, and we should keep it that way. 3131 defineCPUMacros(Builder, "corei7"); 3132 break; 3133 case CK_Skylake: 3134 // FIXME: Historically, we defined this legacy name, it would be nice to 3135 // remove it at some point. This is the only fine-grained CPU macro in the 3136 // main intel CPU line, and it would be better to not have these and force 3137 // people to use ISA macros. 3138 defineCPUMacros(Builder, "skx"); 3139 break; 3140 case CK_KNL: 3141 defineCPUMacros(Builder, "knl"); 3142 break; 3143 case CK_K6_2: 3144 Builder.defineMacro("__k6_2__"); 3145 Builder.defineMacro("__tune_k6_2__"); 3146 // Fallthrough 3147 case CK_K6_3: 3148 if (CPU != CK_K6_2) { // In case of fallthrough 3149 // FIXME: GCC may be enabling these in cases where some other k6 3150 // architecture is specified but -m3dnow is explicitly provided. The 3151 // exact semantics need to be determined and emulated here. 3152 Builder.defineMacro("__k6_3__"); 3153 Builder.defineMacro("__tune_k6_3__"); 3154 } 3155 // Fallthrough 3156 case CK_K6: 3157 defineCPUMacros(Builder, "k6"); 3158 break; 3159 case CK_Athlon: 3160 case CK_AthlonThunderbird: 3161 case CK_Athlon4: 3162 case CK_AthlonXP: 3163 case CK_AthlonMP: 3164 defineCPUMacros(Builder, "athlon"); 3165 if (SSELevel != NoSSE) { 3166 Builder.defineMacro("__athlon_sse__"); 3167 Builder.defineMacro("__tune_athlon_sse__"); 3168 } 3169 break; 3170 case CK_K8: 3171 case CK_K8SSE3: 3172 case CK_x86_64: 3173 case CK_Opteron: 3174 case CK_OpteronSSE3: 3175 case CK_Athlon64: 3176 case CK_Athlon64SSE3: 3177 case CK_AthlonFX: 3178 defineCPUMacros(Builder, "k8"); 3179 break; 3180 case CK_AMDFAM10: 3181 defineCPUMacros(Builder, "amdfam10"); 3182 break; 3183 case CK_BTVER1: 3184 defineCPUMacros(Builder, "btver1"); 3185 break; 3186 case CK_BTVER2: 3187 defineCPUMacros(Builder, "btver2"); 3188 break; 3189 case CK_BDVER1: 3190 defineCPUMacros(Builder, "bdver1"); 3191 break; 3192 case CK_BDVER2: 3193 defineCPUMacros(Builder, "bdver2"); 3194 break; 3195 case CK_BDVER3: 3196 defineCPUMacros(Builder, "bdver3"); 3197 break; 3198 case CK_BDVER4: 3199 defineCPUMacros(Builder, "bdver4"); 3200 break; 3201 case CK_Geode: 3202 defineCPUMacros(Builder, "geode"); 3203 break; 3204 } 3205 3206 // Target properties. 3207 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3208 3209 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3210 // functions in glibc header files that use FP Stack inline asm which the 3211 // backend can't deal with (PR879). 3212 Builder.defineMacro("__NO_MATH_INLINES"); 3213 3214 if (HasAES) 3215 Builder.defineMacro("__AES__"); 3216 3217 if (HasPCLMUL) 3218 Builder.defineMacro("__PCLMUL__"); 3219 3220 if (HasLZCNT) 3221 Builder.defineMacro("__LZCNT__"); 3222 3223 if (HasRDRND) 3224 Builder.defineMacro("__RDRND__"); 3225 3226 if (HasFSGSBASE) 3227 Builder.defineMacro("__FSGSBASE__"); 3228 3229 if (HasBMI) 3230 Builder.defineMacro("__BMI__"); 3231 3232 if (HasBMI2) 3233 Builder.defineMacro("__BMI2__"); 3234 3235 if (HasPOPCNT) 3236 Builder.defineMacro("__POPCNT__"); 3237 3238 if (HasRTM) 3239 Builder.defineMacro("__RTM__"); 3240 3241 if (HasPRFCHW) 3242 Builder.defineMacro("__PRFCHW__"); 3243 3244 if (HasRDSEED) 3245 Builder.defineMacro("__RDSEED__"); 3246 3247 if (HasADX) 3248 Builder.defineMacro("__ADX__"); 3249 3250 if (HasTBM) 3251 Builder.defineMacro("__TBM__"); 3252 3253 switch (XOPLevel) { 3254 case XOP: 3255 Builder.defineMacro("__XOP__"); 3256 case FMA4: 3257 Builder.defineMacro("__FMA4__"); 3258 case SSE4A: 3259 Builder.defineMacro("__SSE4A__"); 3260 case NoXOP: 3261 break; 3262 } 3263 3264 if (HasFMA) 3265 Builder.defineMacro("__FMA__"); 3266 3267 if (HasF16C) 3268 Builder.defineMacro("__F16C__"); 3269 3270 if (HasAVX512CD) 3271 Builder.defineMacro("__AVX512CD__"); 3272 if (HasAVX512ER) 3273 Builder.defineMacro("__AVX512ER__"); 3274 if (HasAVX512PF) 3275 Builder.defineMacro("__AVX512PF__"); 3276 if (HasAVX512DQ) 3277 Builder.defineMacro("__AVX512DQ__"); 3278 if (HasAVX512BW) 3279 Builder.defineMacro("__AVX512BW__"); 3280 if (HasAVX512VL) 3281 Builder.defineMacro("__AVX512VL__"); 3282 3283 if (HasSHA) 3284 Builder.defineMacro("__SHA__"); 3285 3286 if (HasFXSR) 3287 Builder.defineMacro("__FXSR__"); 3288 if (HasXSAVE) 3289 Builder.defineMacro("__XSAVE__"); 3290 if (HasXSAVEOPT) 3291 Builder.defineMacro("__XSAVEOPT__"); 3292 if (HasXSAVEC) 3293 Builder.defineMacro("__XSAVEC__"); 3294 if (HasXSAVES) 3295 Builder.defineMacro("__XSAVES__"); 3296 3297 if (HasCX16) 3298 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3299 3300 // Each case falls through to the previous one here. 3301 switch (SSELevel) { 3302 case AVX512F: 3303 Builder.defineMacro("__AVX512F__"); 3304 case AVX2: 3305 Builder.defineMacro("__AVX2__"); 3306 case AVX: 3307 Builder.defineMacro("__AVX__"); 3308 case SSE42: 3309 Builder.defineMacro("__SSE4_2__"); 3310 case SSE41: 3311 Builder.defineMacro("__SSE4_1__"); 3312 case SSSE3: 3313 Builder.defineMacro("__SSSE3__"); 3314 case SSE3: 3315 Builder.defineMacro("__SSE3__"); 3316 case SSE2: 3317 Builder.defineMacro("__SSE2__"); 3318 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3319 case SSE1: 3320 Builder.defineMacro("__SSE__"); 3321 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3322 case NoSSE: 3323 break; 3324 } 3325 3326 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3327 switch (SSELevel) { 3328 case AVX512F: 3329 case AVX2: 3330 case AVX: 3331 case SSE42: 3332 case SSE41: 3333 case SSSE3: 3334 case SSE3: 3335 case SSE2: 3336 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3337 break; 3338 case SSE1: 3339 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3340 break; 3341 default: 3342 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3343 } 3344 } 3345 3346 // Each case falls through to the previous one here. 3347 switch (MMX3DNowLevel) { 3348 case AMD3DNowAthlon: 3349 Builder.defineMacro("__3dNOW_A__"); 3350 case AMD3DNow: 3351 Builder.defineMacro("__3dNOW__"); 3352 case MMX: 3353 Builder.defineMacro("__MMX__"); 3354 case NoMMX3DNow: 3355 break; 3356 } 3357 3358 if (CPU >= CK_i486) { 3359 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3360 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3361 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3362 } 3363 if (CPU >= CK_i586) 3364 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3365 } 3366 3367 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3368 return llvm::StringSwitch<bool>(Feature) 3369 .Case("aes", HasAES) 3370 .Case("avx", SSELevel >= AVX) 3371 .Case("avx2", SSELevel >= AVX2) 3372 .Case("avx512f", SSELevel >= AVX512F) 3373 .Case("avx512cd", HasAVX512CD) 3374 .Case("avx512er", HasAVX512ER) 3375 .Case("avx512pf", HasAVX512PF) 3376 .Case("avx512dq", HasAVX512DQ) 3377 .Case("avx512bw", HasAVX512BW) 3378 .Case("avx512vl", HasAVX512VL) 3379 .Case("bmi", HasBMI) 3380 .Case("bmi2", HasBMI2) 3381 .Case("cx16", HasCX16) 3382 .Case("f16c", HasF16C) 3383 .Case("fma", HasFMA) 3384 .Case("fma4", XOPLevel >= FMA4) 3385 .Case("fsgsbase", HasFSGSBASE) 3386 .Case("fxsr", HasFXSR) 3387 .Case("lzcnt", HasLZCNT) 3388 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3389 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3390 .Case("mmx", MMX3DNowLevel >= MMX) 3391 .Case("pclmul", HasPCLMUL) 3392 .Case("popcnt", HasPOPCNT) 3393 .Case("prfchw", HasPRFCHW) 3394 .Case("rdrnd", HasRDRND) 3395 .Case("rdseed", HasRDSEED) 3396 .Case("rtm", HasRTM) 3397 .Case("sha", HasSHA) 3398 .Case("sse", SSELevel >= SSE1) 3399 .Case("sse2", SSELevel >= SSE2) 3400 .Case("sse3", SSELevel >= SSE3) 3401 .Case("ssse3", SSELevel >= SSSE3) 3402 .Case("sse4.1", SSELevel >= SSE41) 3403 .Case("sse4.2", SSELevel >= SSE42) 3404 .Case("sse4a", XOPLevel >= SSE4A) 3405 .Case("tbm", HasTBM) 3406 .Case("x86", true) 3407 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3408 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3409 .Case("xop", XOPLevel >= XOP) 3410 .Case("xsave", HasXSAVE) 3411 .Case("xsavec", HasXSAVEC) 3412 .Case("xsaves", HasXSAVES) 3413 .Case("xsaveopt", HasXSAVEOPT) 3414 .Default(false); 3415 } 3416 3417 // We can't use a generic validation scheme for the features accepted here 3418 // versus subtarget features accepted in the target attribute because the 3419 // bitfield structure that's initialized in the runtime only supports the 3420 // below currently rather than the full range of subtarget features. (See 3421 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3422 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3423 return llvm::StringSwitch<bool>(FeatureStr) 3424 .Case("cmov", true) 3425 .Case("mmx", true) 3426 .Case("popcnt", true) 3427 .Case("sse", true) 3428 .Case("sse2", true) 3429 .Case("sse3", true) 3430 .Case("sse4.1", true) 3431 .Case("sse4.2", true) 3432 .Case("avx", true) 3433 .Case("avx2", true) 3434 .Case("sse4a", true) 3435 .Case("fma4", true) 3436 .Case("xop", true) 3437 .Case("fma", true) 3438 .Case("avx512f", true) 3439 .Case("bmi", true) 3440 .Case("bmi2", true) 3441 .Default(false); 3442 } 3443 3444 bool 3445 X86TargetInfo::validateAsmConstraint(const char *&Name, 3446 TargetInfo::ConstraintInfo &Info) const { 3447 switch (*Name) { 3448 default: return false; 3449 // Constant constraints. 3450 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3451 // instructions. 3452 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3453 // x86_64 instructions. 3454 case 's': 3455 Info.setRequiresImmediate(); 3456 return true; 3457 case 'I': 3458 Info.setRequiresImmediate(0, 31); 3459 return true; 3460 case 'J': 3461 Info.setRequiresImmediate(0, 63); 3462 return true; 3463 case 'K': 3464 Info.setRequiresImmediate(-128, 127); 3465 return true; 3466 case 'L': 3467 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3468 return true; 3469 case 'M': 3470 Info.setRequiresImmediate(0, 3); 3471 return true; 3472 case 'N': 3473 Info.setRequiresImmediate(0, 255); 3474 return true; 3475 case 'O': 3476 Info.setRequiresImmediate(0, 127); 3477 return true; 3478 // Register constraints. 3479 case 'Y': // 'Y' is the first character for several 2-character constraints. 3480 // Shift the pointer to the second character of the constraint. 3481 Name++; 3482 switch (*Name) { 3483 default: 3484 return false; 3485 case '0': // First SSE register. 3486 case 't': // Any SSE register, when SSE2 is enabled. 3487 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3488 case 'm': // Any MMX register, when inter-unit moves enabled. 3489 Info.setAllowsRegister(); 3490 return true; 3491 } 3492 case 'f': // Any x87 floating point stack register. 3493 // Constraint 'f' cannot be used for output operands. 3494 if (Info.ConstraintStr[0] == '=') 3495 return false; 3496 Info.setAllowsRegister(); 3497 return true; 3498 case 'a': // eax. 3499 case 'b': // ebx. 3500 case 'c': // ecx. 3501 case 'd': // edx. 3502 case 'S': // esi. 3503 case 'D': // edi. 3504 case 'A': // edx:eax. 3505 case 't': // Top of floating point stack. 3506 case 'u': // Second from top of floating point stack. 3507 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3508 case 'y': // Any MMX register. 3509 case 'x': // Any SSE register. 3510 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3511 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3512 case 'l': // "Index" registers: any general register that can be used as an 3513 // index in a base+index memory access. 3514 Info.setAllowsRegister(); 3515 return true; 3516 // Floating point constant constraints. 3517 case 'C': // SSE floating point constant. 3518 case 'G': // x87 floating point constant. 3519 return true; 3520 } 3521 } 3522 3523 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3524 unsigned Size) const { 3525 // Strip off constraint modifiers. 3526 while (Constraint[0] == '=' || 3527 Constraint[0] == '+' || 3528 Constraint[0] == '&') 3529 Constraint = Constraint.substr(1); 3530 3531 return validateOperandSize(Constraint, Size); 3532 } 3533 3534 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3535 unsigned Size) const { 3536 return validateOperandSize(Constraint, Size); 3537 } 3538 3539 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3540 unsigned Size) const { 3541 switch (Constraint[0]) { 3542 default: break; 3543 case 'y': 3544 return Size <= 64; 3545 case 'f': 3546 case 't': 3547 case 'u': 3548 return Size <= 128; 3549 case 'x': 3550 if (SSELevel >= AVX512F) 3551 // 512-bit zmm registers can be used if target supports AVX512F. 3552 return Size <= 512U; 3553 else if (SSELevel >= AVX) 3554 // 256-bit ymm registers can be used if target supports AVX. 3555 return Size <= 256U; 3556 return Size <= 128U; 3557 case 'Y': 3558 // 'Y' is the first character for several 2-character constraints. 3559 switch (Constraint[1]) { 3560 default: break; 3561 case 'm': 3562 // 'Ym' is synonymous with 'y'. 3563 return Size <= 64; 3564 case 'i': 3565 case 't': 3566 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3567 if (SSELevel >= AVX512F) 3568 return Size <= 512U; 3569 else if (SSELevel >= AVX) 3570 return Size <= 256U; 3571 return SSELevel >= SSE2 && Size <= 128U; 3572 } 3573 3574 } 3575 3576 return true; 3577 } 3578 3579 std::string 3580 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3581 switch (*Constraint) { 3582 case 'a': return std::string("{ax}"); 3583 case 'b': return std::string("{bx}"); 3584 case 'c': return std::string("{cx}"); 3585 case 'd': return std::string("{dx}"); 3586 case 'S': return std::string("{si}"); 3587 case 'D': return std::string("{di}"); 3588 case 'p': // address 3589 return std::string("im"); 3590 case 't': // top of floating point stack. 3591 return std::string("{st}"); 3592 case 'u': // second from top of floating point stack. 3593 return std::string("{st(1)}"); // second from top of floating point stack. 3594 default: 3595 return std::string(1, *Constraint); 3596 } 3597 } 3598 3599 // X86-32 generic target 3600 class X86_32TargetInfo : public X86TargetInfo { 3601 public: 3602 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3603 DoubleAlign = LongLongAlign = 32; 3604 LongDoubleWidth = 96; 3605 LongDoubleAlign = 32; 3606 SuitableAlign = 128; 3607 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3608 SizeType = UnsignedInt; 3609 PtrDiffType = SignedInt; 3610 IntPtrType = SignedInt; 3611 RegParmMax = 3; 3612 3613 // Use fpret for all types. 3614 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3615 (1 << TargetInfo::Double) | 3616 (1 << TargetInfo::LongDouble)); 3617 3618 // x86-32 has atomics up to 8 bytes 3619 // FIXME: Check that we actually have cmpxchg8b before setting 3620 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3621 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3622 } 3623 BuiltinVaListKind getBuiltinVaListKind() const override { 3624 return TargetInfo::CharPtrBuiltinVaList; 3625 } 3626 3627 int getEHDataRegisterNumber(unsigned RegNo) const override { 3628 if (RegNo == 0) return 0; 3629 if (RegNo == 1) return 2; 3630 return -1; 3631 } 3632 bool validateOperandSize(StringRef Constraint, 3633 unsigned Size) const override { 3634 switch (Constraint[0]) { 3635 default: break; 3636 case 'R': 3637 case 'q': 3638 case 'Q': 3639 case 'a': 3640 case 'b': 3641 case 'c': 3642 case 'd': 3643 case 'S': 3644 case 'D': 3645 return Size <= 32; 3646 case 'A': 3647 return Size <= 64; 3648 } 3649 3650 return X86TargetInfo::validateOperandSize(Constraint, Size); 3651 } 3652 }; 3653 3654 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3655 public: 3656 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3657 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3658 3659 unsigned getFloatEvalMethod() const override { 3660 unsigned Major, Minor, Micro; 3661 getTriple().getOSVersion(Major, Minor, Micro); 3662 // New NetBSD uses the default rounding mode. 3663 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3664 return X86_32TargetInfo::getFloatEvalMethod(); 3665 // NetBSD before 6.99.26 defaults to "double" rounding. 3666 return 1; 3667 } 3668 }; 3669 3670 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3671 public: 3672 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3673 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3674 SizeType = UnsignedLong; 3675 IntPtrType = SignedLong; 3676 PtrDiffType = SignedLong; 3677 } 3678 }; 3679 3680 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3681 public: 3682 BitrigI386TargetInfo(const llvm::Triple &Triple) 3683 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3684 SizeType = UnsignedLong; 3685 IntPtrType = SignedLong; 3686 PtrDiffType = SignedLong; 3687 } 3688 }; 3689 3690 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3691 public: 3692 DarwinI386TargetInfo(const llvm::Triple &Triple) 3693 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3694 LongDoubleWidth = 128; 3695 LongDoubleAlign = 128; 3696 SuitableAlign = 128; 3697 SizeType = UnsignedLong; 3698 IntPtrType = SignedLong; 3699 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3700 HasAlignMac68kSupport = true; 3701 } 3702 3703 bool handleTargetFeatures(std::vector<std::string> &Features, 3704 DiagnosticsEngine &Diags) override { 3705 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3706 Diags)) 3707 return false; 3708 // We now know the features we have: we can decide how to align vectors. 3709 MaxVectorAlign = 3710 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3711 return true; 3712 } 3713 }; 3714 3715 // x86-32 Windows target 3716 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3717 public: 3718 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3719 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3720 WCharType = UnsignedShort; 3721 DoubleAlign = LongLongAlign = 64; 3722 bool IsWinCOFF = 3723 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3724 DataLayoutString = IsWinCOFF 3725 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3726 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3727 } 3728 void getTargetDefines(const LangOptions &Opts, 3729 MacroBuilder &Builder) const override { 3730 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3731 } 3732 }; 3733 3734 // x86-32 Windows Visual Studio target 3735 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3736 public: 3737 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3738 : WindowsX86_32TargetInfo(Triple) { 3739 LongDoubleWidth = LongDoubleAlign = 64; 3740 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3741 } 3742 void getTargetDefines(const LangOptions &Opts, 3743 MacroBuilder &Builder) const override { 3744 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3745 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3746 // The value of the following reflects processor type. 3747 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3748 // We lost the original triple, so we use the default. 3749 Builder.defineMacro("_M_IX86", "600"); 3750 } 3751 }; 3752 3753 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3754 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3755 // supports __declspec natively under -fms-extensions, but we define a no-op 3756 // __declspec macro anyway for pre-processor compatibility. 3757 if (Opts.MicrosoftExt) 3758 Builder.defineMacro("__declspec", "__declspec"); 3759 else 3760 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3761 3762 if (!Opts.MicrosoftExt) { 3763 // Provide macros for all the calling convention keywords. Provide both 3764 // single and double underscore prefixed variants. These are available on 3765 // x64 as well as x86, even though they have no effect. 3766 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3767 for (const char *CC : CCs) { 3768 std::string GCCSpelling = "__attribute__((__"; 3769 GCCSpelling += CC; 3770 GCCSpelling += "__))"; 3771 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3772 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3773 } 3774 } 3775 } 3776 3777 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3778 Builder.defineMacro("__MSVCRT__"); 3779 Builder.defineMacro("__MINGW32__"); 3780 addCygMingDefines(Opts, Builder); 3781 } 3782 3783 // x86-32 MinGW target 3784 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3785 public: 3786 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3787 : WindowsX86_32TargetInfo(Triple) {} 3788 void getTargetDefines(const LangOptions &Opts, 3789 MacroBuilder &Builder) const override { 3790 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3791 DefineStd(Builder, "WIN32", Opts); 3792 DefineStd(Builder, "WINNT", Opts); 3793 Builder.defineMacro("_X86_"); 3794 addMinGWDefines(Opts, Builder); 3795 } 3796 }; 3797 3798 // x86-32 Cygwin target 3799 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3800 public: 3801 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3802 : X86_32TargetInfo(Triple) { 3803 TLSSupported = false; 3804 WCharType = UnsignedShort; 3805 DoubleAlign = LongLongAlign = 64; 3806 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3807 } 3808 void getTargetDefines(const LangOptions &Opts, 3809 MacroBuilder &Builder) const override { 3810 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3811 Builder.defineMacro("_X86_"); 3812 Builder.defineMacro("__CYGWIN__"); 3813 Builder.defineMacro("__CYGWIN32__"); 3814 addCygMingDefines(Opts, Builder); 3815 DefineStd(Builder, "unix", Opts); 3816 if (Opts.CPlusPlus) 3817 Builder.defineMacro("_GNU_SOURCE"); 3818 } 3819 }; 3820 3821 // x86-32 Haiku target 3822 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3823 public: 3824 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3825 SizeType = UnsignedLong; 3826 IntPtrType = SignedLong; 3827 PtrDiffType = SignedLong; 3828 ProcessIDType = SignedLong; 3829 this->UserLabelPrefix = ""; 3830 this->TLSSupported = false; 3831 } 3832 void getTargetDefines(const LangOptions &Opts, 3833 MacroBuilder &Builder) const override { 3834 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3835 Builder.defineMacro("__INTEL__"); 3836 Builder.defineMacro("__HAIKU__"); 3837 } 3838 }; 3839 3840 // RTEMS Target 3841 template<typename Target> 3842 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3843 protected: 3844 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3845 MacroBuilder &Builder) const override { 3846 // RTEMS defines; list based off of gcc output 3847 3848 Builder.defineMacro("__rtems__"); 3849 Builder.defineMacro("__ELF__"); 3850 } 3851 3852 public: 3853 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3854 this->UserLabelPrefix = ""; 3855 3856 switch (Triple.getArch()) { 3857 default: 3858 case llvm::Triple::x86: 3859 // this->MCountName = ".mcount"; 3860 break; 3861 case llvm::Triple::mips: 3862 case llvm::Triple::mipsel: 3863 case llvm::Triple::ppc: 3864 case llvm::Triple::ppc64: 3865 case llvm::Triple::ppc64le: 3866 // this->MCountName = "_mcount"; 3867 break; 3868 case llvm::Triple::arm: 3869 // this->MCountName = "__mcount"; 3870 break; 3871 } 3872 } 3873 }; 3874 3875 // x86-32 RTEMS target 3876 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3877 public: 3878 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3879 SizeType = UnsignedLong; 3880 IntPtrType = SignedLong; 3881 PtrDiffType = SignedLong; 3882 this->UserLabelPrefix = ""; 3883 } 3884 void getTargetDefines(const LangOptions &Opts, 3885 MacroBuilder &Builder) const override { 3886 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3887 Builder.defineMacro("__INTEL__"); 3888 Builder.defineMacro("__rtems__"); 3889 } 3890 }; 3891 3892 // x86-64 generic target 3893 class X86_64TargetInfo : public X86TargetInfo { 3894 public: 3895 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3896 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3897 bool IsWinCOFF = 3898 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3899 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3900 LongDoubleWidth = 128; 3901 LongDoubleAlign = 128; 3902 LargeArrayMinWidth = 128; 3903 LargeArrayAlign = 128; 3904 SuitableAlign = 128; 3905 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3906 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3907 IntPtrType = IsX32 ? SignedInt : SignedLong; 3908 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3909 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3910 RegParmMax = 6; 3911 3912 // Pointers are 32-bit in x32. 3913 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3914 : IsWinCOFF 3915 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3916 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3917 3918 // Use fpret only for long double. 3919 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3920 3921 // Use fp2ret for _Complex long double. 3922 ComplexLongDoubleUsesFP2Ret = true; 3923 3924 // Make __builtin_ms_va_list available. 3925 HasBuiltinMSVaList = true; 3926 3927 // x86-64 has atomics up to 16 bytes. 3928 MaxAtomicPromoteWidth = 128; 3929 MaxAtomicInlineWidth = 128; 3930 } 3931 BuiltinVaListKind getBuiltinVaListKind() const override { 3932 return TargetInfo::X86_64ABIBuiltinVaList; 3933 } 3934 3935 int getEHDataRegisterNumber(unsigned RegNo) const override { 3936 if (RegNo == 0) return 0; 3937 if (RegNo == 1) return 1; 3938 return -1; 3939 } 3940 3941 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3942 return (CC == CC_C || 3943 CC == CC_X86VectorCall || 3944 CC == CC_IntelOclBicc || 3945 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3946 } 3947 3948 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3949 return CC_C; 3950 } 3951 3952 // for x32 we need it here explicitly 3953 bool hasInt128Type() const override { return true; } 3954 }; 3955 3956 // x86-64 Windows target 3957 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3958 public: 3959 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3960 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3961 WCharType = UnsignedShort; 3962 LongWidth = LongAlign = 32; 3963 DoubleAlign = LongLongAlign = 64; 3964 IntMaxType = SignedLongLong; 3965 Int64Type = SignedLongLong; 3966 SizeType = UnsignedLongLong; 3967 PtrDiffType = SignedLongLong; 3968 IntPtrType = SignedLongLong; 3969 this->UserLabelPrefix = ""; 3970 } 3971 3972 void getTargetDefines(const LangOptions &Opts, 3973 MacroBuilder &Builder) const override { 3974 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3975 Builder.defineMacro("_WIN64"); 3976 } 3977 3978 BuiltinVaListKind getBuiltinVaListKind() const override { 3979 return TargetInfo::CharPtrBuiltinVaList; 3980 } 3981 3982 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3983 switch (CC) { 3984 case CC_X86StdCall: 3985 case CC_X86ThisCall: 3986 case CC_X86FastCall: 3987 return CCCR_Ignore; 3988 case CC_C: 3989 case CC_X86VectorCall: 3990 case CC_IntelOclBicc: 3991 case CC_X86_64SysV: 3992 return CCCR_OK; 3993 default: 3994 return CCCR_Warning; 3995 } 3996 } 3997 }; 3998 3999 // x86-64 Windows Visual Studio target 4000 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4001 public: 4002 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 4003 : WindowsX86_64TargetInfo(Triple) { 4004 LongDoubleWidth = LongDoubleAlign = 64; 4005 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4006 } 4007 void getTargetDefines(const LangOptions &Opts, 4008 MacroBuilder &Builder) const override { 4009 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4010 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4011 Builder.defineMacro("_M_X64", "100"); 4012 Builder.defineMacro("_M_AMD64", "100"); 4013 } 4014 }; 4015 4016 // x86-64 MinGW target 4017 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4018 public: 4019 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4020 : WindowsX86_64TargetInfo(Triple) {} 4021 void getTargetDefines(const LangOptions &Opts, 4022 MacroBuilder &Builder) const override { 4023 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4024 DefineStd(Builder, "WIN64", Opts); 4025 Builder.defineMacro("__MINGW64__"); 4026 addMinGWDefines(Opts, Builder); 4027 4028 // GCC defines this macro when it is using __gxx_personality_seh0. 4029 if (!Opts.SjLjExceptions) 4030 Builder.defineMacro("__SEH__"); 4031 } 4032 }; 4033 4034 // x86-64 Cygwin target 4035 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4036 public: 4037 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4038 : X86_64TargetInfo(Triple) { 4039 TLSSupported = false; 4040 WCharType = UnsignedShort; 4041 } 4042 void getTargetDefines(const LangOptions &Opts, 4043 MacroBuilder &Builder) const override { 4044 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4045 Builder.defineMacro("__x86_64__"); 4046 Builder.defineMacro("__CYGWIN__"); 4047 Builder.defineMacro("__CYGWIN64__"); 4048 addCygMingDefines(Opts, Builder); 4049 DefineStd(Builder, "unix", Opts); 4050 if (Opts.CPlusPlus) 4051 Builder.defineMacro("_GNU_SOURCE"); 4052 4053 // GCC defines this macro when it is using __gxx_personality_seh0. 4054 if (!Opts.SjLjExceptions) 4055 Builder.defineMacro("__SEH__"); 4056 } 4057 }; 4058 4059 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4060 public: 4061 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4062 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4063 Int64Type = SignedLongLong; 4064 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4065 llvm::Triple T = llvm::Triple(Triple); 4066 if (T.isiOS()) 4067 UseSignedCharForObjCBool = false; 4068 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 4069 } 4070 4071 bool handleTargetFeatures(std::vector<std::string> &Features, 4072 DiagnosticsEngine &Diags) override { 4073 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4074 Diags)) 4075 return false; 4076 // We now know the features we have: we can decide how to align vectors. 4077 MaxVectorAlign = 4078 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4079 return true; 4080 } 4081 }; 4082 4083 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4084 public: 4085 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4086 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4087 IntMaxType = SignedLongLong; 4088 Int64Type = SignedLongLong; 4089 } 4090 }; 4091 4092 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4093 public: 4094 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4095 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4096 IntMaxType = SignedLongLong; 4097 Int64Type = SignedLongLong; 4098 } 4099 }; 4100 4101 class ARMTargetInfo : public TargetInfo { 4102 // Possible FPU choices. 4103 enum FPUMode { 4104 VFP2FPU = (1 << 0), 4105 VFP3FPU = (1 << 1), 4106 VFP4FPU = (1 << 2), 4107 NeonFPU = (1 << 3), 4108 FPARMV8 = (1 << 4) 4109 }; 4110 4111 // Possible HWDiv features. 4112 enum HWDivMode { 4113 HWDivThumb = (1 << 0), 4114 HWDivARM = (1 << 1) 4115 }; 4116 4117 static bool FPUModeIsVFP(FPUMode Mode) { 4118 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4119 } 4120 4121 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4122 static const char * const GCCRegNames[]; 4123 4124 std::string ABI, CPU; 4125 4126 StringRef CPUProfile; 4127 StringRef CPUAttr; 4128 4129 enum { 4130 FP_Default, 4131 FP_VFP, 4132 FP_Neon 4133 } FPMath; 4134 4135 unsigned ArchISA; 4136 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4137 unsigned ArchProfile; 4138 unsigned ArchVersion; 4139 4140 unsigned FPU : 5; 4141 4142 unsigned IsAAPCS : 1; 4143 unsigned HWDiv : 2; 4144 4145 // Initialized via features. 4146 unsigned SoftFloat : 1; 4147 unsigned SoftFloatABI : 1; 4148 4149 unsigned CRC : 1; 4150 unsigned Crypto : 1; 4151 unsigned DSP : 1; 4152 unsigned Unaligned : 1; 4153 4154 enum { 4155 LDREX_B = (1 << 0), /// byte (8-bit) 4156 LDREX_H = (1 << 1), /// half (16-bit) 4157 LDREX_W = (1 << 2), /// word (32-bit) 4158 LDREX_D = (1 << 3), /// double (64-bit) 4159 }; 4160 4161 uint32_t LDREX; 4162 4163 // ACLE 6.5.1 Hardware floating point 4164 enum { 4165 HW_FP_HP = (1 << 1), /// half (16-bit) 4166 HW_FP_SP = (1 << 2), /// single (32-bit) 4167 HW_FP_DP = (1 << 3), /// double (64-bit) 4168 }; 4169 uint32_t HW_FP; 4170 4171 static const Builtin::Info BuiltinInfo[]; 4172 4173 void setABIAAPCS() { 4174 IsAAPCS = true; 4175 4176 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4177 const llvm::Triple &T = getTriple(); 4178 4179 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4180 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4181 T.getOS() == llvm::Triple::Bitrig) 4182 SizeType = UnsignedLong; 4183 else 4184 SizeType = UnsignedInt; 4185 4186 switch (T.getOS()) { 4187 case llvm::Triple::NetBSD: 4188 WCharType = SignedInt; 4189 break; 4190 case llvm::Triple::Win32: 4191 WCharType = UnsignedShort; 4192 break; 4193 case llvm::Triple::Linux: 4194 default: 4195 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4196 WCharType = UnsignedInt; 4197 break; 4198 } 4199 4200 UseBitFieldTypeAlignment = true; 4201 4202 ZeroLengthBitfieldBoundary = 0; 4203 4204 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4205 // so set preferred for small types to 32. 4206 if (T.isOSBinFormatMachO()) { 4207 DataLayoutString = 4208 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4209 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4210 } else if (T.isOSWindows()) { 4211 assert(!BigEndian && "Windows on ARM does not support big endian"); 4212 DataLayoutString = "e" 4213 "-m:w" 4214 "-p:32:32" 4215 "-i64:64" 4216 "-v128:64:128" 4217 "-a:0:32" 4218 "-n32" 4219 "-S64"; 4220 } else if (T.isOSNaCl()) { 4221 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4222 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4223 } else { 4224 DataLayoutString = 4225 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4226 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4227 } 4228 4229 // FIXME: Enumerated types are variable width in straight AAPCS. 4230 } 4231 4232 void setABIAPCS() { 4233 const llvm::Triple &T = getTriple(); 4234 4235 IsAAPCS = false; 4236 4237 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4238 4239 // size_t is unsigned int on FreeBSD. 4240 if (T.getOS() == llvm::Triple::FreeBSD) 4241 SizeType = UnsignedInt; 4242 else 4243 SizeType = UnsignedLong; 4244 4245 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4246 WCharType = SignedInt; 4247 4248 // Do not respect the alignment of bit-field types when laying out 4249 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4250 UseBitFieldTypeAlignment = false; 4251 4252 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4253 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4254 /// gcc. 4255 ZeroLengthBitfieldBoundary = 32; 4256 4257 if (T.isOSBinFormatMachO()) 4258 DataLayoutString = 4259 BigEndian 4260 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4261 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4262 else 4263 DataLayoutString = 4264 BigEndian 4265 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4266 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4267 4268 // FIXME: Override "preferred align" for double and long long. 4269 } 4270 4271 void setArchInfo() { 4272 StringRef ArchName = getTriple().getArchName(); 4273 4274 ArchISA = llvm::ARM::parseArchISA(ArchName); 4275 CPU = llvm::ARM::getDefaultCPU(ArchName); 4276 unsigned AK = llvm::ARM::parseArch(ArchName); 4277 if (AK != llvm::ARM::AK_INVALID) 4278 ArchKind = AK; 4279 setArchInfo(ArchKind); 4280 } 4281 4282 void setArchInfo(unsigned Kind) { 4283 StringRef SubArch; 4284 4285 // cache TargetParser info 4286 ArchKind = Kind; 4287 SubArch = llvm::ARM::getSubArch(ArchKind); 4288 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4289 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4290 4291 // cache CPU related strings 4292 CPUAttr = getCPUAttr(); 4293 CPUProfile = getCPUProfile(); 4294 } 4295 4296 void setAtomic() { 4297 // when triple does not specify a sub arch, 4298 // then we are not using inline atomics 4299 bool ShouldUseInlineAtomic = 4300 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4301 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4302 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4303 if (ArchProfile == llvm::ARM::PK_M) { 4304 MaxAtomicPromoteWidth = 32; 4305 if (ShouldUseInlineAtomic) 4306 MaxAtomicInlineWidth = 32; 4307 } 4308 else { 4309 MaxAtomicPromoteWidth = 64; 4310 if (ShouldUseInlineAtomic) 4311 MaxAtomicInlineWidth = 64; 4312 } 4313 } 4314 4315 bool isThumb() const { 4316 return (ArchISA == llvm::ARM::IK_THUMB); 4317 } 4318 4319 bool supportsThumb() const { 4320 return CPUAttr.count('T') || ArchVersion >= 6; 4321 } 4322 4323 bool supportsThumb2() const { 4324 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4325 } 4326 4327 StringRef getCPUAttr() const { 4328 // For most sub-arches, the build attribute CPU name is enough. 4329 // For Cortex variants, it's slightly different. 4330 switch(ArchKind) { 4331 default: 4332 return llvm::ARM::getCPUAttr(ArchKind); 4333 case llvm::ARM::AK_ARMV6M: 4334 case llvm::ARM::AK_ARMV6SM: 4335 case llvm::ARM::AK_ARMV6HL: 4336 return "6M"; 4337 case llvm::ARM::AK_ARMV7S: 4338 return "7S"; 4339 case llvm::ARM::AK_ARMV7: 4340 case llvm::ARM::AK_ARMV7A: 4341 case llvm::ARM::AK_ARMV7L: 4342 case llvm::ARM::AK_ARMV7HL: 4343 return "7A"; 4344 case llvm::ARM::AK_ARMV7R: 4345 return "7R"; 4346 case llvm::ARM::AK_ARMV7M: 4347 return "7M"; 4348 case llvm::ARM::AK_ARMV7EM: 4349 return "7EM"; 4350 case llvm::ARM::AK_ARMV8A: 4351 return "8A"; 4352 case llvm::ARM::AK_ARMV8_1A: 4353 return "8_1A"; 4354 } 4355 } 4356 4357 StringRef getCPUProfile() const { 4358 switch(ArchProfile) { 4359 case llvm::ARM::PK_A: 4360 return "A"; 4361 case llvm::ARM::PK_R: 4362 return "R"; 4363 case llvm::ARM::PK_M: 4364 return "M"; 4365 default: 4366 return ""; 4367 } 4368 } 4369 4370 public: 4371 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4372 : TargetInfo(Triple), FPMath(FP_Default), 4373 IsAAPCS(true), LDREX(0), HW_FP(0) { 4374 BigEndian = IsBigEndian; 4375 4376 switch (getTriple().getOS()) { 4377 case llvm::Triple::NetBSD: 4378 PtrDiffType = SignedLong; 4379 break; 4380 default: 4381 PtrDiffType = SignedInt; 4382 break; 4383 } 4384 4385 // Cache arch related info. 4386 setArchInfo(); 4387 4388 // {} in inline assembly are neon specifiers, not assembly variant 4389 // specifiers. 4390 NoAsmVariants = true; 4391 4392 // FIXME: This duplicates code from the driver that sets the -target-abi 4393 // option - this code is used if -target-abi isn't passed and should 4394 // be unified in some way. 4395 if (Triple.isOSBinFormatMachO()) { 4396 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4397 // the frontend matches that. 4398 if (Triple.getEnvironment() == llvm::Triple::EABI || 4399 Triple.getOS() == llvm::Triple::UnknownOS || 4400 StringRef(CPU).startswith("cortex-m")) { 4401 setABI("aapcs"); 4402 } else { 4403 setABI("apcs-gnu"); 4404 } 4405 } else if (Triple.isOSWindows()) { 4406 // FIXME: this is invalid for WindowsCE 4407 setABI("aapcs"); 4408 } else { 4409 // Select the default based on the platform. 4410 switch (Triple.getEnvironment()) { 4411 case llvm::Triple::Android: 4412 case llvm::Triple::GNUEABI: 4413 case llvm::Triple::GNUEABIHF: 4414 setABI("aapcs-linux"); 4415 break; 4416 case llvm::Triple::EABIHF: 4417 case llvm::Triple::EABI: 4418 setABI("aapcs"); 4419 break; 4420 case llvm::Triple::GNU: 4421 setABI("apcs-gnu"); 4422 break; 4423 default: 4424 if (Triple.getOS() == llvm::Triple::NetBSD) 4425 setABI("apcs-gnu"); 4426 else 4427 setABI("aapcs"); 4428 break; 4429 } 4430 } 4431 4432 // ARM targets default to using the ARM C++ ABI. 4433 TheCXXABI.set(TargetCXXABI::GenericARM); 4434 4435 // ARM has atomics up to 8 bytes 4436 setAtomic(); 4437 4438 // Do force alignment of members that follow zero length bitfields. If 4439 // the alignment of the zero-length bitfield is greater than the member 4440 // that follows it, `bar', `bar' will be aligned as the type of the 4441 // zero length bitfield. 4442 UseZeroLengthBitfieldAlignment = true; 4443 } 4444 4445 StringRef getABI() const override { return ABI; } 4446 4447 bool setABI(const std::string &Name) override { 4448 ABI = Name; 4449 4450 // The defaults (above) are for AAPCS, check if we need to change them. 4451 // 4452 // FIXME: We need support for -meabi... we could just mangle it into the 4453 // name. 4454 if (Name == "apcs-gnu") { 4455 setABIAPCS(); 4456 return true; 4457 } 4458 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4459 setABIAAPCS(); 4460 return true; 4461 } 4462 return false; 4463 } 4464 4465 // FIXME: This should be based on Arch attributes, not CPU names. 4466 bool 4467 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4468 StringRef CPU, 4469 const std::vector<std::string> &FeaturesVec) const override { 4470 4471 std::vector<const char*> TargetFeatures; 4472 4473 // get default FPU features 4474 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU); 4475 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4476 4477 // get default Extension features 4478 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU); 4479 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4480 4481 for (const char *Feature : TargetFeatures) 4482 if (Feature[0] == '+') 4483 Features[Feature+1] = true; 4484 4485 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4486 } 4487 4488 bool handleTargetFeatures(std::vector<std::string> &Features, 4489 DiagnosticsEngine &Diags) override { 4490 FPU = 0; 4491 CRC = 0; 4492 Crypto = 0; 4493 DSP = 0; 4494 Unaligned = 1; 4495 SoftFloat = SoftFloatABI = false; 4496 HWDiv = 0; 4497 4498 // This does not diagnose illegal cases like having both 4499 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4500 uint32_t HW_FP_remove = 0; 4501 for (const auto &Feature : Features) { 4502 if (Feature == "+soft-float") { 4503 SoftFloat = true; 4504 } else if (Feature == "+soft-float-abi") { 4505 SoftFloatABI = true; 4506 } else if (Feature == "+vfp2") { 4507 FPU |= VFP2FPU; 4508 HW_FP |= HW_FP_SP | HW_FP_DP; 4509 } else if (Feature == "+vfp3") { 4510 FPU |= VFP3FPU; 4511 HW_FP |= HW_FP_SP | HW_FP_DP; 4512 } else if (Feature == "+vfp4") { 4513 FPU |= VFP4FPU; 4514 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4515 } else if (Feature == "+fp-armv8") { 4516 FPU |= FPARMV8; 4517 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4518 } else if (Feature == "+neon") { 4519 FPU |= NeonFPU; 4520 HW_FP |= HW_FP_SP | HW_FP_DP; 4521 } else if (Feature == "+hwdiv") { 4522 HWDiv |= HWDivThumb; 4523 } else if (Feature == "+hwdiv-arm") { 4524 HWDiv |= HWDivARM; 4525 } else if (Feature == "+crc") { 4526 CRC = 1; 4527 } else if (Feature == "+crypto") { 4528 Crypto = 1; 4529 } else if (Feature == "+t2dsp") { 4530 DSP = 1; 4531 } else if (Feature == "+fp-only-sp") { 4532 HW_FP_remove |= HW_FP_DP | HW_FP_HP; 4533 } else if (Feature == "+strict-align") { 4534 Unaligned = 0; 4535 } else if (Feature == "+fp16") { 4536 HW_FP |= HW_FP_HP; 4537 } 4538 } 4539 HW_FP &= ~HW_FP_remove; 4540 4541 switch (ArchVersion) { 4542 case 6: 4543 if (ArchProfile == llvm::ARM::PK_M) 4544 LDREX = 0; 4545 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4546 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4547 else 4548 LDREX = LDREX_W; 4549 break; 4550 case 7: 4551 if (ArchProfile == llvm::ARM::PK_M) 4552 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4553 else 4554 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4555 break; 4556 case 8: 4557 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4558 } 4559 4560 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4561 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4562 return false; 4563 } 4564 4565 if (FPMath == FP_Neon) 4566 Features.push_back("+neonfp"); 4567 else if (FPMath == FP_VFP) 4568 Features.push_back("-neonfp"); 4569 4570 // Remove front-end specific options which the backend handles differently. 4571 auto Feature = 4572 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4573 if (Feature != Features.end()) 4574 Features.erase(Feature); 4575 4576 return true; 4577 } 4578 4579 bool hasFeature(StringRef Feature) const override { 4580 return llvm::StringSwitch<bool>(Feature) 4581 .Case("arm", true) 4582 .Case("aarch32", true) 4583 .Case("softfloat", SoftFloat) 4584 .Case("thumb", isThumb()) 4585 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4586 .Case("hwdiv", HWDiv & HWDivThumb) 4587 .Case("hwdiv-arm", HWDiv & HWDivARM) 4588 .Default(false); 4589 } 4590 4591 bool setCPU(const std::string &Name) override { 4592 if (Name != "generic") 4593 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4594 4595 if (ArchKind == llvm::ARM::AK_INVALID) 4596 return false; 4597 setAtomic(); 4598 CPU = Name; 4599 return true; 4600 } 4601 4602 bool setFPMath(StringRef Name) override; 4603 4604 void getTargetDefines(const LangOptions &Opts, 4605 MacroBuilder &Builder) const override { 4606 // Target identification. 4607 Builder.defineMacro("__arm"); 4608 Builder.defineMacro("__arm__"); 4609 4610 // Target properties. 4611 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4612 if (!CPUAttr.empty()) 4613 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4614 4615 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4616 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4617 Builder.defineMacro("__ARM_ARCH", llvm::utostr(ArchVersion)); 4618 4619 if (ArchVersion >= 8) { 4620 // ACLE 6.5.7 Crypto Extension 4621 if (Crypto) 4622 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4623 // ACLE 6.5.8 CRC32 Extension 4624 if (CRC) 4625 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4626 // ACLE 6.5.10 Numeric Maximum and Minimum 4627 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4628 // ACLE 6.5.9 Directed Rounding 4629 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4630 } 4631 4632 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4633 // is not defined for the M-profile. 4634 // NOTE that the deffault profile is assumed to be 'A' 4635 if (CPUProfile.empty() || CPUProfile != "M") 4636 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4637 4638 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4639 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4640 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4641 if (supportsThumb2()) 4642 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4643 else if (supportsThumb()) 4644 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4645 4646 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4647 // instruction set such as ARM or Thumb. 4648 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4649 4650 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4651 4652 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4653 if (!CPUProfile.empty()) 4654 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4655 4656 // ACLE 6.4.3 Unaligned access supported in hardware 4657 if (Unaligned) 4658 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4659 4660 // ACLE 6.4.4 LDREX/STREX 4661 if (LDREX) 4662 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4663 4664 // ACLE 6.4.5 CLZ 4665 if (ArchVersion == 5 || 4666 (ArchVersion == 6 && CPUProfile != "M") || 4667 ArchVersion > 6) 4668 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4669 4670 // ACLE 6.5.1 Hardware Floating Point 4671 if (HW_FP) 4672 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4673 4674 // ACLE predefines. 4675 Builder.defineMacro("__ARM_ACLE", "200"); 4676 4677 // FP16 support (we currently only support IEEE format). 4678 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4679 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4680 4681 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4682 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4683 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4684 4685 // Subtarget options. 4686 4687 // FIXME: It's more complicated than this and we don't really support 4688 // interworking. 4689 // Windows on ARM does not "support" interworking 4690 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4691 Builder.defineMacro("__THUMB_INTERWORK__"); 4692 4693 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4694 // Embedded targets on Darwin follow AAPCS, but not EABI. 4695 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4696 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4697 Builder.defineMacro("__ARM_EABI__"); 4698 Builder.defineMacro("__ARM_PCS", "1"); 4699 4700 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4701 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4702 } 4703 4704 if (SoftFloat) 4705 Builder.defineMacro("__SOFTFP__"); 4706 4707 if (CPU == "xscale") 4708 Builder.defineMacro("__XSCALE__"); 4709 4710 if (isThumb()) { 4711 Builder.defineMacro("__THUMBEL__"); 4712 Builder.defineMacro("__thumb__"); 4713 if (supportsThumb2()) 4714 Builder.defineMacro("__thumb2__"); 4715 } 4716 4717 // ACLE 6.4.9 32-bit SIMD instructions 4718 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4719 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4720 4721 // ACLE 6.4.10 Hardware Integer Divide 4722 if (((HWDiv & HWDivThumb) && isThumb()) || 4723 ((HWDiv & HWDivARM) && !isThumb())) { 4724 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4725 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4726 } 4727 4728 // Note, this is always on in gcc, even though it doesn't make sense. 4729 Builder.defineMacro("__APCS_32__"); 4730 4731 if (FPUModeIsVFP((FPUMode) FPU)) { 4732 Builder.defineMacro("__VFP_FP__"); 4733 if (FPU & VFP2FPU) 4734 Builder.defineMacro("__ARM_VFPV2__"); 4735 if (FPU & VFP3FPU) 4736 Builder.defineMacro("__ARM_VFPV3__"); 4737 if (FPU & VFP4FPU) 4738 Builder.defineMacro("__ARM_VFPV4__"); 4739 } 4740 4741 // This only gets set when Neon instructions are actually available, unlike 4742 // the VFP define, hence the soft float and arch check. This is subtly 4743 // different from gcc, we follow the intent which was that it should be set 4744 // when Neon instructions are actually available. 4745 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4746 Builder.defineMacro("__ARM_NEON", "1"); 4747 Builder.defineMacro("__ARM_NEON__"); 4748 // current AArch32 NEON implementations do not support double-precision 4749 // floating-point even when it is present in VFP. 4750 Builder.defineMacro("__ARM_NEON_FP", 4751 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4752 } 4753 4754 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4755 Opts.ShortWChar ? "2" : "4"); 4756 4757 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4758 Opts.ShortEnums ? "1" : "4"); 4759 4760 if (ArchVersion >= 6 && CPUAttr != "6M") { 4761 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4762 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4763 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4764 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4765 } 4766 4767 // ACLE 6.4.7 DSP instructions 4768 if (DSP) { 4769 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4770 } 4771 4772 // ACLE 6.4.8 Saturation instructions 4773 bool SAT = false; 4774 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4775 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4776 SAT = true; 4777 } 4778 4779 // ACLE 6.4.6 Q (saturation) flag 4780 if (DSP || SAT) 4781 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 4782 4783 if (Opts.UnsafeFPMath) 4784 Builder.defineMacro("__ARM_FP_FAST", "1"); 4785 } 4786 4787 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4788 return llvm::makeArrayRef(BuiltinInfo, 4789 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 4790 } 4791 bool isCLZForZeroUndef() const override { return false; } 4792 BuiltinVaListKind getBuiltinVaListKind() const override { 4793 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4794 } 4795 ArrayRef<const char *> getGCCRegNames() const override; 4796 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 4797 bool validateAsmConstraint(const char *&Name, 4798 TargetInfo::ConstraintInfo &Info) const override { 4799 switch (*Name) { 4800 default: break; 4801 case 'l': // r0-r7 4802 case 'h': // r8-r15 4803 case 'w': // VFP Floating point register single precision 4804 case 'P': // VFP Floating point register double precision 4805 Info.setAllowsRegister(); 4806 return true; 4807 case 'I': 4808 case 'J': 4809 case 'K': 4810 case 'L': 4811 case 'M': 4812 // FIXME 4813 return true; 4814 case 'Q': // A memory address that is a single base register. 4815 Info.setAllowsMemory(); 4816 return true; 4817 case 'U': // a memory reference... 4818 switch (Name[1]) { 4819 case 'q': // ...ARMV4 ldrsb 4820 case 'v': // ...VFP load/store (reg+constant offset) 4821 case 'y': // ...iWMMXt load/store 4822 case 't': // address valid for load/store opaque types wider 4823 // than 128-bits 4824 case 'n': // valid address for Neon doubleword vector load/store 4825 case 'm': // valid address for Neon element and structure load/store 4826 case 's': // valid address for non-offset loads/stores of quad-word 4827 // values in four ARM registers 4828 Info.setAllowsMemory(); 4829 Name++; 4830 return true; 4831 } 4832 } 4833 return false; 4834 } 4835 std::string convertConstraint(const char *&Constraint) const override { 4836 std::string R; 4837 switch (*Constraint) { 4838 case 'U': // Two-character constraint; add "^" hint for later parsing. 4839 R = std::string("^") + std::string(Constraint, 2); 4840 Constraint++; 4841 break; 4842 case 'p': // 'p' should be translated to 'r' by default. 4843 R = std::string("r"); 4844 break; 4845 default: 4846 return std::string(1, *Constraint); 4847 } 4848 return R; 4849 } 4850 bool 4851 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4852 std::string &SuggestedModifier) const override { 4853 bool isOutput = (Constraint[0] == '='); 4854 bool isInOut = (Constraint[0] == '+'); 4855 4856 // Strip off constraint modifiers. 4857 while (Constraint[0] == '=' || 4858 Constraint[0] == '+' || 4859 Constraint[0] == '&') 4860 Constraint = Constraint.substr(1); 4861 4862 switch (Constraint[0]) { 4863 default: break; 4864 case 'r': { 4865 switch (Modifier) { 4866 default: 4867 return (isInOut || isOutput || Size <= 64); 4868 case 'q': 4869 // A register of size 32 cannot fit a vector type. 4870 return false; 4871 } 4872 } 4873 } 4874 4875 return true; 4876 } 4877 const char *getClobbers() const override { 4878 // FIXME: Is this really right? 4879 return ""; 4880 } 4881 4882 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4883 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4884 } 4885 4886 int getEHDataRegisterNumber(unsigned RegNo) const override { 4887 if (RegNo == 0) return 0; 4888 if (RegNo == 1) return 1; 4889 return -1; 4890 } 4891 4892 bool hasSjLjLowering() const override { 4893 return true; 4894 } 4895 }; 4896 4897 bool ARMTargetInfo::setFPMath(StringRef Name) { 4898 if (Name == "neon") { 4899 FPMath = FP_Neon; 4900 return true; 4901 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4902 Name == "vfp4") { 4903 FPMath = FP_VFP; 4904 return true; 4905 } 4906 return false; 4907 } 4908 4909 const char * const ARMTargetInfo::GCCRegNames[] = { 4910 // Integer registers 4911 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4912 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4913 4914 // Float registers 4915 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4916 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4917 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4918 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4919 4920 // Double registers 4921 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4922 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4923 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4924 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4925 4926 // Quad registers 4927 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4928 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4929 }; 4930 4931 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 4932 return llvm::makeArrayRef(GCCRegNames); 4933 } 4934 4935 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4936 { { "a1" }, "r0" }, 4937 { { "a2" }, "r1" }, 4938 { { "a3" }, "r2" }, 4939 { { "a4" }, "r3" }, 4940 { { "v1" }, "r4" }, 4941 { { "v2" }, "r5" }, 4942 { { "v3" }, "r6" }, 4943 { { "v4" }, "r7" }, 4944 { { "v5" }, "r8" }, 4945 { { "v6", "rfp" }, "r9" }, 4946 { { "sl" }, "r10" }, 4947 { { "fp" }, "r11" }, 4948 { { "ip" }, "r12" }, 4949 { { "r13" }, "sp" }, 4950 { { "r14" }, "lr" }, 4951 { { "r15" }, "pc" }, 4952 // The S, D and Q registers overlap, but aren't really aliases; we 4953 // don't want to substitute one of these for a different-sized one. 4954 }; 4955 4956 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 4957 return llvm::makeArrayRef(GCCRegAliases); 4958 } 4959 4960 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4961 #define BUILTIN(ID, TYPE, ATTRS) \ 4962 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 4963 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 4964 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 4965 #include "clang/Basic/BuiltinsNEON.def" 4966 4967 #define BUILTIN(ID, TYPE, ATTRS) \ 4968 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 4969 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 4970 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 4971 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 4972 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 4973 #include "clang/Basic/BuiltinsARM.def" 4974 }; 4975 4976 class ARMleTargetInfo : public ARMTargetInfo { 4977 public: 4978 ARMleTargetInfo(const llvm::Triple &Triple) 4979 : ARMTargetInfo(Triple, false) { } 4980 void getTargetDefines(const LangOptions &Opts, 4981 MacroBuilder &Builder) const override { 4982 Builder.defineMacro("__ARMEL__"); 4983 ARMTargetInfo::getTargetDefines(Opts, Builder); 4984 } 4985 }; 4986 4987 class ARMbeTargetInfo : public ARMTargetInfo { 4988 public: 4989 ARMbeTargetInfo(const llvm::Triple &Triple) 4990 : ARMTargetInfo(Triple, true) { } 4991 void getTargetDefines(const LangOptions &Opts, 4992 MacroBuilder &Builder) const override { 4993 Builder.defineMacro("__ARMEB__"); 4994 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4995 ARMTargetInfo::getTargetDefines(Opts, Builder); 4996 } 4997 }; 4998 4999 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5000 const llvm::Triple Triple; 5001 public: 5002 WindowsARMTargetInfo(const llvm::Triple &Triple) 5003 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 5004 TLSSupported = false; 5005 WCharType = UnsignedShort; 5006 SizeType = UnsignedInt; 5007 UserLabelPrefix = ""; 5008 } 5009 void getVisualStudioDefines(const LangOptions &Opts, 5010 MacroBuilder &Builder) const { 5011 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5012 5013 // FIXME: this is invalid for WindowsCE 5014 Builder.defineMacro("_M_ARM_NT", "1"); 5015 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5016 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5017 5018 assert((Triple.getArch() == llvm::Triple::arm || 5019 Triple.getArch() == llvm::Triple::thumb) && 5020 "invalid architecture for Windows ARM target info"); 5021 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5022 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5023 5024 // TODO map the complete set of values 5025 // 31: VFPv3 40: VFPv4 5026 Builder.defineMacro("_M_ARM_FP", "31"); 5027 } 5028 BuiltinVaListKind getBuiltinVaListKind() const override { 5029 return TargetInfo::CharPtrBuiltinVaList; 5030 } 5031 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5032 switch (CC) { 5033 case CC_X86StdCall: 5034 case CC_X86ThisCall: 5035 case CC_X86FastCall: 5036 case CC_X86VectorCall: 5037 return CCCR_Ignore; 5038 case CC_C: 5039 return CCCR_OK; 5040 default: 5041 return CCCR_Warning; 5042 } 5043 } 5044 }; 5045 5046 // Windows ARM + Itanium C++ ABI Target 5047 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5048 public: 5049 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5050 : WindowsARMTargetInfo(Triple) { 5051 TheCXXABI.set(TargetCXXABI::GenericARM); 5052 } 5053 5054 void getTargetDefines(const LangOptions &Opts, 5055 MacroBuilder &Builder) const override { 5056 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5057 5058 if (Opts.MSVCCompat) 5059 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5060 } 5061 }; 5062 5063 // Windows ARM, MS (C++) ABI 5064 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5065 public: 5066 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5067 : WindowsARMTargetInfo(Triple) { 5068 TheCXXABI.set(TargetCXXABI::Microsoft); 5069 } 5070 5071 void getTargetDefines(const LangOptions &Opts, 5072 MacroBuilder &Builder) const override { 5073 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5074 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5075 } 5076 }; 5077 5078 // ARM MinGW target 5079 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5080 public: 5081 MinGWARMTargetInfo(const llvm::Triple &Triple) 5082 : WindowsARMTargetInfo(Triple) { 5083 TheCXXABI.set(TargetCXXABI::GenericARM); 5084 } 5085 5086 void getTargetDefines(const LangOptions &Opts, 5087 MacroBuilder &Builder) const override { 5088 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5089 DefineStd(Builder, "WIN32", Opts); 5090 DefineStd(Builder, "WINNT", Opts); 5091 Builder.defineMacro("_ARM_"); 5092 addMinGWDefines(Opts, Builder); 5093 } 5094 }; 5095 5096 // ARM Cygwin target 5097 class CygwinARMTargetInfo : public ARMleTargetInfo { 5098 public: 5099 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5100 TLSSupported = false; 5101 WCharType = UnsignedShort; 5102 DoubleAlign = LongLongAlign = 64; 5103 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 5104 } 5105 void getTargetDefines(const LangOptions &Opts, 5106 MacroBuilder &Builder) const override { 5107 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5108 Builder.defineMacro("_ARM_"); 5109 Builder.defineMacro("__CYGWIN__"); 5110 Builder.defineMacro("__CYGWIN32__"); 5111 DefineStd(Builder, "unix", Opts); 5112 if (Opts.CPlusPlus) 5113 Builder.defineMacro("_GNU_SOURCE"); 5114 } 5115 }; 5116 5117 class DarwinARMTargetInfo : 5118 public DarwinTargetInfo<ARMleTargetInfo> { 5119 protected: 5120 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5121 MacroBuilder &Builder) const override { 5122 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5123 } 5124 5125 public: 5126 DarwinARMTargetInfo(const llvm::Triple &Triple) 5127 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5128 HasAlignMac68kSupport = true; 5129 // iOS always has 64-bit atomic instructions. 5130 // FIXME: This should be based off of the target features in 5131 // ARMleTargetInfo. 5132 MaxAtomicInlineWidth = 64; 5133 5134 // Darwin on iOS uses a variant of the ARM C++ ABI. 5135 TheCXXABI.set(TargetCXXABI::iOS); 5136 } 5137 }; 5138 5139 class AArch64TargetInfo : public TargetInfo { 5140 virtual void setDataLayoutString() = 0; 5141 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5142 static const char *const GCCRegNames[]; 5143 5144 enum FPUModeEnum { 5145 FPUMode, 5146 NeonMode 5147 }; 5148 5149 unsigned FPU; 5150 unsigned CRC; 5151 unsigned Crypto; 5152 unsigned Unaligned; 5153 5154 static const Builtin::Info BuiltinInfo[]; 5155 5156 std::string ABI; 5157 5158 public: 5159 AArch64TargetInfo(const llvm::Triple &Triple) 5160 : TargetInfo(Triple), ABI("aapcs") { 5161 5162 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5163 WCharType = SignedInt; 5164 5165 // NetBSD apparently prefers consistency across ARM targets to consistency 5166 // across 64-bit targets. 5167 Int64Type = SignedLongLong; 5168 IntMaxType = SignedLongLong; 5169 } else { 5170 WCharType = UnsignedInt; 5171 Int64Type = SignedLong; 5172 IntMaxType = SignedLong; 5173 } 5174 5175 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5176 MaxVectorAlign = 128; 5177 MaxAtomicInlineWidth = 128; 5178 MaxAtomicPromoteWidth = 128; 5179 5180 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5181 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5182 5183 // {} in inline assembly are neon specifiers, not assembly variant 5184 // specifiers. 5185 NoAsmVariants = true; 5186 5187 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5188 // contributes to the alignment of the containing aggregate in the same way 5189 // a plain (non bit-field) member of that type would, without exception for 5190 // zero-sized or anonymous bit-fields." 5191 UseBitFieldTypeAlignment = true; 5192 UseZeroLengthBitfieldAlignment = true; 5193 5194 // AArch64 targets default to using the ARM C++ ABI. 5195 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5196 } 5197 5198 StringRef getABI() const override { return ABI; } 5199 bool setABI(const std::string &Name) override { 5200 if (Name != "aapcs" && Name != "darwinpcs") 5201 return false; 5202 5203 ABI = Name; 5204 return true; 5205 } 5206 5207 bool setCPU(const std::string &Name) override { 5208 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5209 .Case("generic", true) 5210 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 5211 .Case("cyclone", true) 5212 .Default(false); 5213 return CPUKnown; 5214 } 5215 5216 void getTargetDefines(const LangOptions &Opts, 5217 MacroBuilder &Builder) const override { 5218 // Target identification. 5219 Builder.defineMacro("__aarch64__"); 5220 5221 // Target properties. 5222 Builder.defineMacro("_LP64"); 5223 Builder.defineMacro("__LP64__"); 5224 5225 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5226 Builder.defineMacro("__ARM_ACLE", "200"); 5227 Builder.defineMacro("__ARM_ARCH", "8"); 5228 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5229 5230 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5231 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5232 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5233 5234 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5235 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5236 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5237 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5238 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5239 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5240 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5241 5242 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5243 5244 // 0xe implies support for half, single and double precision operations. 5245 Builder.defineMacro("__ARM_FP", "0xE"); 5246 5247 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5248 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5249 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5250 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5251 5252 if (Opts.UnsafeFPMath) 5253 Builder.defineMacro("__ARM_FP_FAST", "1"); 5254 5255 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5256 5257 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5258 Opts.ShortEnums ? "1" : "4"); 5259 5260 if (FPU == NeonMode) { 5261 Builder.defineMacro("__ARM_NEON", "1"); 5262 // 64-bit NEON supports half, single and double precision operations. 5263 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5264 } 5265 5266 if (CRC) 5267 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5268 5269 if (Crypto) 5270 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5271 5272 if (Unaligned) 5273 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5274 5275 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5276 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5277 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5278 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5279 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5280 } 5281 5282 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5283 return llvm::makeArrayRef(BuiltinInfo, 5284 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5285 } 5286 5287 bool hasFeature(StringRef Feature) const override { 5288 return Feature == "aarch64" || 5289 Feature == "arm64" || 5290 Feature == "arm" || 5291 (Feature == "neon" && FPU == NeonMode); 5292 } 5293 5294 bool handleTargetFeatures(std::vector<std::string> &Features, 5295 DiagnosticsEngine &Diags) override { 5296 FPU = FPUMode; 5297 CRC = 0; 5298 Crypto = 0; 5299 Unaligned = 1; 5300 5301 for (const auto &Feature : Features) { 5302 if (Feature == "+neon") 5303 FPU = NeonMode; 5304 if (Feature == "+crc") 5305 CRC = 1; 5306 if (Feature == "+crypto") 5307 Crypto = 1; 5308 if (Feature == "+strict-align") 5309 Unaligned = 0; 5310 } 5311 5312 setDataLayoutString(); 5313 5314 return true; 5315 } 5316 5317 bool isCLZForZeroUndef() const override { return false; } 5318 5319 BuiltinVaListKind getBuiltinVaListKind() const override { 5320 return TargetInfo::AArch64ABIBuiltinVaList; 5321 } 5322 5323 ArrayRef<const char *> getGCCRegNames() const override; 5324 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5325 5326 bool validateAsmConstraint(const char *&Name, 5327 TargetInfo::ConstraintInfo &Info) const override { 5328 switch (*Name) { 5329 default: 5330 return false; 5331 case 'w': // Floating point and SIMD registers (V0-V31) 5332 Info.setAllowsRegister(); 5333 return true; 5334 case 'I': // Constant that can be used with an ADD instruction 5335 case 'J': // Constant that can be used with a SUB instruction 5336 case 'K': // Constant that can be used with a 32-bit logical instruction 5337 case 'L': // Constant that can be used with a 64-bit logical instruction 5338 case 'M': // Constant that can be used as a 32-bit MOV immediate 5339 case 'N': // Constant that can be used as a 64-bit MOV immediate 5340 case 'Y': // Floating point constant zero 5341 case 'Z': // Integer constant zero 5342 return true; 5343 case 'Q': // A memory reference with base register and no offset 5344 Info.setAllowsMemory(); 5345 return true; 5346 case 'S': // A symbolic address 5347 Info.setAllowsRegister(); 5348 return true; 5349 case 'U': 5350 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5351 // Utf: A memory address suitable for ldp/stp in TF mode. 5352 // Usa: An absolute symbolic address. 5353 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5354 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5355 case 'z': // Zero register, wzr or xzr 5356 Info.setAllowsRegister(); 5357 return true; 5358 case 'x': // Floating point and SIMD registers (V0-V15) 5359 Info.setAllowsRegister(); 5360 return true; 5361 } 5362 return false; 5363 } 5364 5365 bool 5366 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5367 std::string &SuggestedModifier) const override { 5368 // Strip off constraint modifiers. 5369 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5370 Constraint = Constraint.substr(1); 5371 5372 switch (Constraint[0]) { 5373 default: 5374 return true; 5375 case 'z': 5376 case 'r': { 5377 switch (Modifier) { 5378 case 'x': 5379 case 'w': 5380 // For now assume that the person knows what they're 5381 // doing with the modifier. 5382 return true; 5383 default: 5384 // By default an 'r' constraint will be in the 'x' 5385 // registers. 5386 if (Size == 64) 5387 return true; 5388 5389 SuggestedModifier = "w"; 5390 return false; 5391 } 5392 } 5393 } 5394 } 5395 5396 const char *getClobbers() const override { return ""; } 5397 5398 int getEHDataRegisterNumber(unsigned RegNo) const override { 5399 if (RegNo == 0) 5400 return 0; 5401 if (RegNo == 1) 5402 return 1; 5403 return -1; 5404 } 5405 }; 5406 5407 const char *const AArch64TargetInfo::GCCRegNames[] = { 5408 // 32-bit Integer registers 5409 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5410 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5411 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5412 5413 // 64-bit Integer registers 5414 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5415 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5416 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5417 5418 // 32-bit floating point regsisters 5419 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5420 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5421 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5422 5423 // 64-bit floating point regsisters 5424 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5425 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5426 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5427 5428 // Vector registers 5429 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5430 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5431 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5432 }; 5433 5434 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5435 return llvm::makeArrayRef(GCCRegNames); 5436 } 5437 5438 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5439 { { "w31" }, "wsp" }, 5440 { { "x29" }, "fp" }, 5441 { { "x30" }, "lr" }, 5442 { { "x31" }, "sp" }, 5443 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5444 // don't want to substitute one of these for a different-sized one. 5445 }; 5446 5447 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5448 return llvm::makeArrayRef(GCCRegAliases); 5449 } 5450 5451 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5452 #define BUILTIN(ID, TYPE, ATTRS) \ 5453 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5454 #include "clang/Basic/BuiltinsNEON.def" 5455 5456 #define BUILTIN(ID, TYPE, ATTRS) \ 5457 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5458 #include "clang/Basic/BuiltinsAArch64.def" 5459 }; 5460 5461 class AArch64leTargetInfo : public AArch64TargetInfo { 5462 void setDataLayoutString() override { 5463 if (getTriple().isOSBinFormatMachO()) 5464 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5465 else 5466 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5467 } 5468 5469 public: 5470 AArch64leTargetInfo(const llvm::Triple &Triple) 5471 : AArch64TargetInfo(Triple) { 5472 BigEndian = false; 5473 } 5474 void getTargetDefines(const LangOptions &Opts, 5475 MacroBuilder &Builder) const override { 5476 Builder.defineMacro("__AARCH64EL__"); 5477 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5478 } 5479 }; 5480 5481 class AArch64beTargetInfo : public AArch64TargetInfo { 5482 void setDataLayoutString() override { 5483 assert(!getTriple().isOSBinFormatMachO()); 5484 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5485 } 5486 5487 public: 5488 AArch64beTargetInfo(const llvm::Triple &Triple) 5489 : AArch64TargetInfo(Triple) { } 5490 void getTargetDefines(const LangOptions &Opts, 5491 MacroBuilder &Builder) const override { 5492 Builder.defineMacro("__AARCH64EB__"); 5493 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5494 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5495 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5496 } 5497 }; 5498 5499 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5500 protected: 5501 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5502 MacroBuilder &Builder) const override { 5503 Builder.defineMacro("__AARCH64_SIMD__"); 5504 Builder.defineMacro("__ARM64_ARCH_8__"); 5505 Builder.defineMacro("__ARM_NEON__"); 5506 Builder.defineMacro("__LITTLE_ENDIAN__"); 5507 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5508 Builder.defineMacro("__arm64", "1"); 5509 Builder.defineMacro("__arm64__", "1"); 5510 5511 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5512 } 5513 5514 public: 5515 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5516 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5517 Int64Type = SignedLongLong; 5518 WCharType = SignedInt; 5519 UseSignedCharForObjCBool = false; 5520 5521 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5522 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5523 5524 TheCXXABI.set(TargetCXXABI::iOS64); 5525 } 5526 5527 BuiltinVaListKind getBuiltinVaListKind() const override { 5528 return TargetInfo::CharPtrBuiltinVaList; 5529 } 5530 }; 5531 5532 // Hexagon abstract base class 5533 class HexagonTargetInfo : public TargetInfo { 5534 static const Builtin::Info BuiltinInfo[]; 5535 static const char * const GCCRegNames[]; 5536 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5537 std::string CPU; 5538 public: 5539 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5540 BigEndian = false; 5541 DataLayoutString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5542 5543 // {} in inline assembly are packet specifiers, not assembly variant 5544 // specifiers. 5545 NoAsmVariants = true; 5546 } 5547 5548 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5549 return llvm::makeArrayRef(BuiltinInfo, 5550 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5551 } 5552 5553 bool validateAsmConstraint(const char *&Name, 5554 TargetInfo::ConstraintInfo &Info) const override { 5555 return true; 5556 } 5557 5558 void getTargetDefines(const LangOptions &Opts, 5559 MacroBuilder &Builder) const override; 5560 5561 bool hasFeature(StringRef Feature) const override { 5562 return Feature == "hexagon"; 5563 } 5564 5565 BuiltinVaListKind getBuiltinVaListKind() const override { 5566 return TargetInfo::CharPtrBuiltinVaList; 5567 } 5568 ArrayRef<const char *> getGCCRegNames() const override; 5569 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5570 const char *getClobbers() const override { 5571 return ""; 5572 } 5573 5574 static const char *getHexagonCPUSuffix(StringRef Name) { 5575 return llvm::StringSwitch<const char*>(Name) 5576 .Case("hexagonv4", "4") 5577 .Case("hexagonv5", "5") 5578 .Default(nullptr); 5579 } 5580 5581 bool setCPU(const std::string &Name) override { 5582 if (!getHexagonCPUSuffix(Name)) 5583 return false; 5584 5585 CPU = Name; 5586 return true; 5587 } 5588 }; 5589 5590 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5591 MacroBuilder &Builder) const { 5592 Builder.defineMacro("qdsp6"); 5593 Builder.defineMacro("__qdsp6", "1"); 5594 Builder.defineMacro("__qdsp6__", "1"); 5595 5596 Builder.defineMacro("hexagon"); 5597 Builder.defineMacro("__hexagon", "1"); 5598 Builder.defineMacro("__hexagon__", "1"); 5599 5600 if(CPU == "hexagonv1") { 5601 Builder.defineMacro("__HEXAGON_V1__"); 5602 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5603 if(Opts.HexagonQdsp6Compat) { 5604 Builder.defineMacro("__QDSP6_V1__"); 5605 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5606 } 5607 } 5608 else if(CPU == "hexagonv2") { 5609 Builder.defineMacro("__HEXAGON_V2__"); 5610 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5611 if(Opts.HexagonQdsp6Compat) { 5612 Builder.defineMacro("__QDSP6_V2__"); 5613 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5614 } 5615 } 5616 else if(CPU == "hexagonv3") { 5617 Builder.defineMacro("__HEXAGON_V3__"); 5618 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5619 if(Opts.HexagonQdsp6Compat) { 5620 Builder.defineMacro("__QDSP6_V3__"); 5621 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5622 } 5623 } 5624 else if(CPU == "hexagonv4") { 5625 Builder.defineMacro("__HEXAGON_V4__"); 5626 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5627 if(Opts.HexagonQdsp6Compat) { 5628 Builder.defineMacro("__QDSP6_V4__"); 5629 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5630 } 5631 } 5632 else if(CPU == "hexagonv5") { 5633 Builder.defineMacro("__HEXAGON_V5__"); 5634 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5635 if(Opts.HexagonQdsp6Compat) { 5636 Builder.defineMacro("__QDSP6_V5__"); 5637 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5638 } 5639 } 5640 } 5641 5642 const char * const HexagonTargetInfo::GCCRegNames[] = { 5643 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5644 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5645 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5646 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5647 "p0", "p1", "p2", "p3", 5648 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5649 }; 5650 5651 ArrayRef<const char *> HexagonTargetInfo::getGCCRegNames() const { 5652 return llvm::makeArrayRef(GCCRegNames); 5653 } 5654 5655 5656 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5657 { { "sp" }, "r29" }, 5658 { { "fp" }, "r30" }, 5659 { { "lr" }, "r31" }, 5660 }; 5661 5662 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 5663 return llvm::makeArrayRef(GCCRegAliases); 5664 } 5665 5666 5667 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5668 #define BUILTIN(ID, TYPE, ATTRS) \ 5669 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5670 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5671 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5672 #include "clang/Basic/BuiltinsHexagon.def" 5673 }; 5674 5675 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5676 class SparcTargetInfo : public TargetInfo { 5677 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5678 static const char * const GCCRegNames[]; 5679 bool SoftFloat; 5680 public: 5681 SparcTargetInfo(const llvm::Triple &Triple) 5682 : TargetInfo(Triple), SoftFloat(false) {} 5683 5684 bool handleTargetFeatures(std::vector<std::string> &Features, 5685 DiagnosticsEngine &Diags) override { 5686 // The backend doesn't actually handle soft float yet, but in case someone 5687 // is using the support for the front end continue to support it. 5688 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5689 if (Feature != Features.end()) { 5690 SoftFloat = true; 5691 Features.erase(Feature); 5692 } 5693 return true; 5694 } 5695 void getTargetDefines(const LangOptions &Opts, 5696 MacroBuilder &Builder) const override { 5697 DefineStd(Builder, "sparc", Opts); 5698 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5699 5700 if (SoftFloat) 5701 Builder.defineMacro("SOFT_FLOAT", "1"); 5702 } 5703 5704 bool hasFeature(StringRef Feature) const override { 5705 return llvm::StringSwitch<bool>(Feature) 5706 .Case("softfloat", SoftFloat) 5707 .Case("sparc", true) 5708 .Default(false); 5709 } 5710 5711 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5712 // FIXME: Implement! 5713 return None; 5714 } 5715 BuiltinVaListKind getBuiltinVaListKind() const override { 5716 return TargetInfo::VoidPtrBuiltinVaList; 5717 } 5718 ArrayRef<const char *> getGCCRegNames() const override; 5719 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5720 bool validateAsmConstraint(const char *&Name, 5721 TargetInfo::ConstraintInfo &info) const override { 5722 // FIXME: Implement! 5723 switch (*Name) { 5724 case 'I': // Signed 13-bit constant 5725 case 'J': // Zero 5726 case 'K': // 32-bit constant with the low 12 bits clear 5727 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5728 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5729 case 'N': // Same as 'K' but zext (required for SIMode) 5730 case 'O': // The constant 4096 5731 return true; 5732 } 5733 return false; 5734 } 5735 const char *getClobbers() const override { 5736 // FIXME: Implement! 5737 return ""; 5738 } 5739 }; 5740 5741 const char * const SparcTargetInfo::GCCRegNames[] = { 5742 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5743 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5744 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5745 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5746 }; 5747 5748 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 5749 return llvm::makeArrayRef(GCCRegNames); 5750 } 5751 5752 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5753 { { "g0" }, "r0" }, 5754 { { "g1" }, "r1" }, 5755 { { "g2" }, "r2" }, 5756 { { "g3" }, "r3" }, 5757 { { "g4" }, "r4" }, 5758 { { "g5" }, "r5" }, 5759 { { "g6" }, "r6" }, 5760 { { "g7" }, "r7" }, 5761 { { "o0" }, "r8" }, 5762 { { "o1" }, "r9" }, 5763 { { "o2" }, "r10" }, 5764 { { "o3" }, "r11" }, 5765 { { "o4" }, "r12" }, 5766 { { "o5" }, "r13" }, 5767 { { "o6", "sp" }, "r14" }, 5768 { { "o7" }, "r15" }, 5769 { { "l0" }, "r16" }, 5770 { { "l1" }, "r17" }, 5771 { { "l2" }, "r18" }, 5772 { { "l3" }, "r19" }, 5773 { { "l4" }, "r20" }, 5774 { { "l5" }, "r21" }, 5775 { { "l6" }, "r22" }, 5776 { { "l7" }, "r23" }, 5777 { { "i0" }, "r24" }, 5778 { { "i1" }, "r25" }, 5779 { { "i2" }, "r26" }, 5780 { { "i3" }, "r27" }, 5781 { { "i4" }, "r28" }, 5782 { { "i5" }, "r29" }, 5783 { { "i6", "fp" }, "r30" }, 5784 { { "i7" }, "r31" }, 5785 }; 5786 5787 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 5788 return llvm::makeArrayRef(GCCRegAliases); 5789 } 5790 5791 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5792 class SparcV8TargetInfo : public SparcTargetInfo { 5793 public: 5794 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5795 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5796 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 5797 switch (getTriple().getOS()) { 5798 default: 5799 SizeType = UnsignedInt; 5800 IntPtrType = SignedInt; 5801 PtrDiffType = SignedInt; 5802 break; 5803 case llvm::Triple::NetBSD: 5804 case llvm::Triple::OpenBSD: 5805 SizeType = UnsignedLong; 5806 IntPtrType = SignedLong; 5807 PtrDiffType = SignedLong; 5808 break; 5809 } 5810 } 5811 5812 void getTargetDefines(const LangOptions &Opts, 5813 MacroBuilder &Builder) const override { 5814 SparcTargetInfo::getTargetDefines(Opts, Builder); 5815 Builder.defineMacro("__sparcv8"); 5816 } 5817 }; 5818 5819 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 5820 class SparcV8elTargetInfo : public SparcV8TargetInfo { 5821 public: 5822 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 5823 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5824 BigEndian = false; 5825 } 5826 }; 5827 5828 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5829 class SparcV9TargetInfo : public SparcTargetInfo { 5830 public: 5831 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5832 // FIXME: Support Sparc quad-precision long double? 5833 DataLayoutString = "E-m:e-i64:64-n32:64-S128"; 5834 // This is an LP64 platform. 5835 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5836 5837 // OpenBSD uses long long for int64_t and intmax_t. 5838 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5839 IntMaxType = SignedLongLong; 5840 else 5841 IntMaxType = SignedLong; 5842 Int64Type = IntMaxType; 5843 5844 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5845 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5846 LongDoubleWidth = 128; 5847 LongDoubleAlign = 128; 5848 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5849 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5850 } 5851 5852 void getTargetDefines(const LangOptions &Opts, 5853 MacroBuilder &Builder) const override { 5854 SparcTargetInfo::getTargetDefines(Opts, Builder); 5855 Builder.defineMacro("__sparcv9"); 5856 Builder.defineMacro("__arch64__"); 5857 // Solaris doesn't need these variants, but the BSDs do. 5858 if (getTriple().getOS() != llvm::Triple::Solaris) { 5859 Builder.defineMacro("__sparc64__"); 5860 Builder.defineMacro("__sparc_v9__"); 5861 Builder.defineMacro("__sparcv9__"); 5862 } 5863 } 5864 5865 bool setCPU(const std::string &Name) override { 5866 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5867 .Case("v9", true) 5868 .Case("ultrasparc", true) 5869 .Case("ultrasparc3", true) 5870 .Case("niagara", true) 5871 .Case("niagara2", true) 5872 .Case("niagara3", true) 5873 .Case("niagara4", true) 5874 .Default(false); 5875 5876 // No need to store the CPU yet. There aren't any CPU-specific 5877 // macros to define. 5878 return CPUKnown; 5879 } 5880 }; 5881 5882 class SystemZTargetInfo : public TargetInfo { 5883 static const Builtin::Info BuiltinInfo[]; 5884 static const char *const GCCRegNames[]; 5885 std::string CPU; 5886 bool HasTransactionalExecution; 5887 bool HasVector; 5888 5889 public: 5890 SystemZTargetInfo(const llvm::Triple &Triple) 5891 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 5892 HasVector(false) { 5893 IntMaxType = SignedLong; 5894 Int64Type = SignedLong; 5895 TLSSupported = true; 5896 IntWidth = IntAlign = 32; 5897 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5898 PointerWidth = PointerAlign = 64; 5899 LongDoubleWidth = 128; 5900 LongDoubleAlign = 64; 5901 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5902 DefaultAlignForAttributeAligned = 64; 5903 MinGlobalAlign = 16; 5904 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5905 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5906 } 5907 void getTargetDefines(const LangOptions &Opts, 5908 MacroBuilder &Builder) const override { 5909 Builder.defineMacro("__s390__"); 5910 Builder.defineMacro("__s390x__"); 5911 Builder.defineMacro("__zarch__"); 5912 Builder.defineMacro("__LONG_DOUBLE_128__"); 5913 if (HasTransactionalExecution) 5914 Builder.defineMacro("__HTM__"); 5915 if (Opts.ZVector) 5916 Builder.defineMacro("__VEC__", "10301"); 5917 } 5918 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5919 return llvm::makeArrayRef(BuiltinInfo, 5920 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 5921 } 5922 5923 ArrayRef<const char *> getGCCRegNames() const override; 5924 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 5925 // No aliases. 5926 return None; 5927 } 5928 bool validateAsmConstraint(const char *&Name, 5929 TargetInfo::ConstraintInfo &info) const override; 5930 const char *getClobbers() const override { 5931 // FIXME: Is this really right? 5932 return ""; 5933 } 5934 BuiltinVaListKind getBuiltinVaListKind() const override { 5935 return TargetInfo::SystemZBuiltinVaList; 5936 } 5937 bool setCPU(const std::string &Name) override { 5938 CPU = Name; 5939 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5940 .Case("z10", true) 5941 .Case("z196", true) 5942 .Case("zEC12", true) 5943 .Case("z13", true) 5944 .Default(false); 5945 5946 return CPUKnown; 5947 } 5948 bool 5949 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5950 StringRef CPU, 5951 const std::vector<std::string> &FeaturesVec) const override { 5952 if (CPU == "zEC12") 5953 Features["transactional-execution"] = true; 5954 if (CPU == "z13") { 5955 Features["transactional-execution"] = true; 5956 Features["vector"] = true; 5957 } 5958 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5959 } 5960 5961 bool handleTargetFeatures(std::vector<std::string> &Features, 5962 DiagnosticsEngine &Diags) override { 5963 HasTransactionalExecution = false; 5964 for (const auto &Feature : Features) { 5965 if (Feature == "+transactional-execution") 5966 HasTransactionalExecution = true; 5967 else if (Feature == "+vector") 5968 HasVector = true; 5969 } 5970 // If we use the vector ABI, vector types are 64-bit aligned. 5971 if (HasVector) { 5972 MaxVectorAlign = 64; 5973 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 5974 "-v128:64-a:8:16-n32:64"; 5975 } 5976 return true; 5977 } 5978 5979 bool hasFeature(StringRef Feature) const override { 5980 return llvm::StringSwitch<bool>(Feature) 5981 .Case("systemz", true) 5982 .Case("htm", HasTransactionalExecution) 5983 .Case("vx", HasVector) 5984 .Default(false); 5985 } 5986 5987 StringRef getABI() const override { 5988 if (HasVector) 5989 return "vector"; 5990 return ""; 5991 } 5992 5993 bool useFloat128ManglingForLongDouble() const override { 5994 return true; 5995 } 5996 }; 5997 5998 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 5999 #define BUILTIN(ID, TYPE, ATTRS) \ 6000 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6001 #include "clang/Basic/BuiltinsSystemZ.def" 6002 }; 6003 6004 const char *const SystemZTargetInfo::GCCRegNames[] = { 6005 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6006 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6007 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6008 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6009 }; 6010 6011 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6012 return llvm::makeArrayRef(GCCRegNames); 6013 } 6014 6015 bool SystemZTargetInfo:: 6016 validateAsmConstraint(const char *&Name, 6017 TargetInfo::ConstraintInfo &Info) const { 6018 switch (*Name) { 6019 default: 6020 return false; 6021 6022 case 'a': // Address register 6023 case 'd': // Data register (equivalent to 'r') 6024 case 'f': // Floating-point register 6025 Info.setAllowsRegister(); 6026 return true; 6027 6028 case 'I': // Unsigned 8-bit constant 6029 case 'J': // Unsigned 12-bit constant 6030 case 'K': // Signed 16-bit constant 6031 case 'L': // Signed 20-bit displacement (on all targets we support) 6032 case 'M': // 0x7fffffff 6033 return true; 6034 6035 case 'Q': // Memory with base and unsigned 12-bit displacement 6036 case 'R': // Likewise, plus an index 6037 case 'S': // Memory with base and signed 20-bit displacement 6038 case 'T': // Likewise, plus an index 6039 Info.setAllowsMemory(); 6040 return true; 6041 } 6042 } 6043 6044 class MSP430TargetInfo : public TargetInfo { 6045 static const char *const GCCRegNames[]; 6046 6047 public: 6048 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6049 BigEndian = false; 6050 TLSSupported = false; 6051 IntWidth = 16; 6052 IntAlign = 16; 6053 LongWidth = 32; 6054 LongLongWidth = 64; 6055 LongAlign = LongLongAlign = 16; 6056 PointerWidth = 16; 6057 PointerAlign = 16; 6058 SuitableAlign = 16; 6059 SizeType = UnsignedInt; 6060 IntMaxType = SignedLongLong; 6061 IntPtrType = SignedInt; 6062 PtrDiffType = SignedInt; 6063 SigAtomicType = SignedLong; 6064 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 6065 } 6066 void getTargetDefines(const LangOptions &Opts, 6067 MacroBuilder &Builder) const override { 6068 Builder.defineMacro("MSP430"); 6069 Builder.defineMacro("__MSP430__"); 6070 // FIXME: defines for different 'flavours' of MCU 6071 } 6072 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6073 // FIXME: Implement. 6074 return None; 6075 } 6076 bool hasFeature(StringRef Feature) const override { 6077 return Feature == "msp430"; 6078 } 6079 ArrayRef<const char *> getGCCRegNames() const override; 6080 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6081 // No aliases. 6082 return None; 6083 } 6084 bool validateAsmConstraint(const char *&Name, 6085 TargetInfo::ConstraintInfo &info) const override { 6086 // FIXME: implement 6087 switch (*Name) { 6088 case 'K': // the constant 1 6089 case 'L': // constant -1^20 .. 1^19 6090 case 'M': // constant 1-4: 6091 return true; 6092 } 6093 // No target constraints for now. 6094 return false; 6095 } 6096 const char *getClobbers() const override { 6097 // FIXME: Is this really right? 6098 return ""; 6099 } 6100 BuiltinVaListKind getBuiltinVaListKind() const override { 6101 // FIXME: implement 6102 return TargetInfo::CharPtrBuiltinVaList; 6103 } 6104 }; 6105 6106 const char *const MSP430TargetInfo::GCCRegNames[] = { 6107 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6108 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6109 6110 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6111 return llvm::makeArrayRef(GCCRegNames); 6112 } 6113 6114 // LLVM and Clang cannot be used directly to output native binaries for 6115 // target, but is used to compile C code to llvm bitcode with correct 6116 // type and alignment information. 6117 // 6118 // TCE uses the llvm bitcode as input and uses it for generating customized 6119 // target processor and program binary. TCE co-design environment is 6120 // publicly available in http://tce.cs.tut.fi 6121 6122 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6123 3, // opencl_global 6124 4, // opencl_local 6125 5, // opencl_constant 6126 // FIXME: generic has to be added to the target 6127 0, // opencl_generic 6128 0, // cuda_device 6129 0, // cuda_constant 6130 0 // cuda_shared 6131 }; 6132 6133 class TCETargetInfo : public TargetInfo { 6134 public: 6135 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6136 TLSSupported = false; 6137 IntWidth = 32; 6138 LongWidth = LongLongWidth = 32; 6139 PointerWidth = 32; 6140 IntAlign = 32; 6141 LongAlign = LongLongAlign = 32; 6142 PointerAlign = 32; 6143 SuitableAlign = 32; 6144 SizeType = UnsignedInt; 6145 IntMaxType = SignedLong; 6146 IntPtrType = SignedInt; 6147 PtrDiffType = SignedInt; 6148 FloatWidth = 32; 6149 FloatAlign = 32; 6150 DoubleWidth = 32; 6151 DoubleAlign = 32; 6152 LongDoubleWidth = 32; 6153 LongDoubleAlign = 32; 6154 FloatFormat = &llvm::APFloat::IEEEsingle; 6155 DoubleFormat = &llvm::APFloat::IEEEsingle; 6156 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6157 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6158 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6159 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6160 UseAddrSpaceMapMangling = true; 6161 } 6162 6163 void getTargetDefines(const LangOptions &Opts, 6164 MacroBuilder &Builder) const override { 6165 DefineStd(Builder, "tce", Opts); 6166 Builder.defineMacro("__TCE__"); 6167 Builder.defineMacro("__TCE_V1__"); 6168 } 6169 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6170 6171 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6172 const char *getClobbers() const override { return ""; } 6173 BuiltinVaListKind getBuiltinVaListKind() const override { 6174 return TargetInfo::VoidPtrBuiltinVaList; 6175 } 6176 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6177 bool validateAsmConstraint(const char *&Name, 6178 TargetInfo::ConstraintInfo &info) const override { 6179 return true; 6180 } 6181 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6182 return None; 6183 } 6184 }; 6185 6186 class BPFTargetInfo : public TargetInfo { 6187 public: 6188 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6189 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6190 SizeType = UnsignedLong; 6191 PtrDiffType = SignedLong; 6192 IntPtrType = SignedLong; 6193 IntMaxType = SignedLong; 6194 Int64Type = SignedLong; 6195 RegParmMax = 5; 6196 if (Triple.getArch() == llvm::Triple::bpfeb) { 6197 BigEndian = true; 6198 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6199 } else { 6200 BigEndian = false; 6201 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6202 } 6203 MaxAtomicPromoteWidth = 64; 6204 MaxAtomicInlineWidth = 64; 6205 TLSSupported = false; 6206 } 6207 void getTargetDefines(const LangOptions &Opts, 6208 MacroBuilder &Builder) const override { 6209 DefineStd(Builder, "bpf", Opts); 6210 Builder.defineMacro("__BPF__"); 6211 } 6212 bool hasFeature(StringRef Feature) const override { 6213 return Feature == "bpf"; 6214 } 6215 6216 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6217 const char *getClobbers() const override { 6218 return ""; 6219 } 6220 BuiltinVaListKind getBuiltinVaListKind() const override { 6221 return TargetInfo::VoidPtrBuiltinVaList; 6222 } 6223 ArrayRef<const char *> getGCCRegNames() const override { 6224 return None; 6225 } 6226 bool validateAsmConstraint(const char *&Name, 6227 TargetInfo::ConstraintInfo &info) const override { 6228 return true; 6229 } 6230 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6231 return None; 6232 } 6233 }; 6234 6235 class MipsTargetInfoBase : public TargetInfo { 6236 virtual void setDataLayoutString() = 0; 6237 6238 static const Builtin::Info BuiltinInfo[]; 6239 std::string CPU; 6240 bool IsMips16; 6241 bool IsMicromips; 6242 bool IsNan2008; 6243 bool IsSingleFloat; 6244 enum MipsFloatABI { 6245 HardFloat, SoftFloat 6246 } FloatABI; 6247 enum DspRevEnum { 6248 NoDSP, DSP1, DSP2 6249 } DspRev; 6250 bool HasMSA; 6251 6252 protected: 6253 bool HasFP64; 6254 std::string ABI; 6255 6256 public: 6257 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6258 const std::string &CPUStr) 6259 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6260 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6261 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6262 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6263 } 6264 6265 bool isNaN2008Default() const { 6266 return CPU == "mips32r6" || CPU == "mips64r6"; 6267 } 6268 6269 bool isFP64Default() const { 6270 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6271 } 6272 6273 bool isNan2008() const override { 6274 return IsNan2008; 6275 } 6276 6277 StringRef getABI() const override { return ABI; } 6278 bool setCPU(const std::string &Name) override { 6279 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6280 getTriple().getArch() == llvm::Triple::mipsel; 6281 CPU = Name; 6282 return llvm::StringSwitch<bool>(Name) 6283 .Case("mips1", IsMips32) 6284 .Case("mips2", IsMips32) 6285 .Case("mips3", true) 6286 .Case("mips4", true) 6287 .Case("mips5", true) 6288 .Case("mips32", IsMips32) 6289 .Case("mips32r2", IsMips32) 6290 .Case("mips32r3", IsMips32) 6291 .Case("mips32r5", IsMips32) 6292 .Case("mips32r6", IsMips32) 6293 .Case("mips64", true) 6294 .Case("mips64r2", true) 6295 .Case("mips64r3", true) 6296 .Case("mips64r5", true) 6297 .Case("mips64r6", true) 6298 .Case("octeon", true) 6299 .Case("p5600", true) 6300 .Default(false); 6301 } 6302 const std::string& getCPU() const { return CPU; } 6303 bool 6304 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6305 StringRef CPU, 6306 const std::vector<std::string> &FeaturesVec) const override { 6307 if (CPU == "octeon") 6308 Features["mips64r2"] = Features["cnmips"] = true; 6309 else 6310 Features[CPU] = true; 6311 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6312 } 6313 6314 void getTargetDefines(const LangOptions &Opts, 6315 MacroBuilder &Builder) const override { 6316 Builder.defineMacro("__mips__"); 6317 Builder.defineMacro("_mips"); 6318 if (Opts.GNUMode) 6319 Builder.defineMacro("mips"); 6320 6321 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6322 6323 switch (FloatABI) { 6324 case HardFloat: 6325 Builder.defineMacro("__mips_hard_float", Twine(1)); 6326 break; 6327 case SoftFloat: 6328 Builder.defineMacro("__mips_soft_float", Twine(1)); 6329 break; 6330 } 6331 6332 if (IsSingleFloat) 6333 Builder.defineMacro("__mips_single_float", Twine(1)); 6334 6335 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6336 Builder.defineMacro("_MIPS_FPSET", 6337 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6338 6339 if (IsMips16) 6340 Builder.defineMacro("__mips16", Twine(1)); 6341 6342 if (IsMicromips) 6343 Builder.defineMacro("__mips_micromips", Twine(1)); 6344 6345 if (IsNan2008) 6346 Builder.defineMacro("__mips_nan2008", Twine(1)); 6347 6348 switch (DspRev) { 6349 default: 6350 break; 6351 case DSP1: 6352 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6353 Builder.defineMacro("__mips_dsp", Twine(1)); 6354 break; 6355 case DSP2: 6356 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6357 Builder.defineMacro("__mips_dspr2", Twine(1)); 6358 Builder.defineMacro("__mips_dsp", Twine(1)); 6359 break; 6360 } 6361 6362 if (HasMSA) 6363 Builder.defineMacro("__mips_msa", Twine(1)); 6364 6365 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6366 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6367 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6368 6369 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6370 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6371 } 6372 6373 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6374 return llvm::makeArrayRef(BuiltinInfo, 6375 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 6376 } 6377 bool hasFeature(StringRef Feature) const override { 6378 return llvm::StringSwitch<bool>(Feature) 6379 .Case("mips", true) 6380 .Case("fp64", HasFP64) 6381 .Default(false); 6382 } 6383 BuiltinVaListKind getBuiltinVaListKind() const override { 6384 return TargetInfo::VoidPtrBuiltinVaList; 6385 } 6386 ArrayRef<const char *> getGCCRegNames() const override { 6387 static const char *const GCCRegNames[] = { 6388 // CPU register names 6389 // Must match second column of GCCRegAliases 6390 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6391 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6392 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6393 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6394 // Floating point register names 6395 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6396 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6397 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6398 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6399 // Hi/lo and condition register names 6400 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6401 "$fcc5","$fcc6","$fcc7", 6402 // MSA register names 6403 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6404 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6405 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6406 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6407 // MSA control register names 6408 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6409 "$msarequest", "$msamap", "$msaunmap" 6410 }; 6411 return llvm::makeArrayRef(GCCRegNames); 6412 } 6413 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 6414 bool validateAsmConstraint(const char *&Name, 6415 TargetInfo::ConstraintInfo &Info) const override { 6416 switch (*Name) { 6417 default: 6418 return false; 6419 case 'r': // CPU registers. 6420 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6421 case 'y': // Equivalent to "r", backward compatibility only. 6422 case 'f': // floating-point registers. 6423 case 'c': // $25 for indirect jumps 6424 case 'l': // lo register 6425 case 'x': // hilo register pair 6426 Info.setAllowsRegister(); 6427 return true; 6428 case 'I': // Signed 16-bit constant 6429 case 'J': // Integer 0 6430 case 'K': // Unsigned 16-bit constant 6431 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6432 case 'M': // Constants not loadable via lui, addiu, or ori 6433 case 'N': // Constant -1 to -65535 6434 case 'O': // A signed 15-bit constant 6435 case 'P': // A constant between 1 go 65535 6436 return true; 6437 case 'R': // An address that can be used in a non-macro load or store 6438 Info.setAllowsMemory(); 6439 return true; 6440 case 'Z': 6441 if (Name[1] == 'C') { // An address usable by ll, and sc. 6442 Info.setAllowsMemory(); 6443 Name++; // Skip over 'Z'. 6444 return true; 6445 } 6446 return false; 6447 } 6448 } 6449 6450 std::string convertConstraint(const char *&Constraint) const override { 6451 std::string R; 6452 switch (*Constraint) { 6453 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6454 if (Constraint[1] == 'C') { 6455 R = std::string("^") + std::string(Constraint, 2); 6456 Constraint++; 6457 return R; 6458 } 6459 break; 6460 } 6461 return TargetInfo::convertConstraint(Constraint); 6462 } 6463 6464 const char *getClobbers() const override { 6465 // In GCC, $1 is not widely used in generated code (it's used only in a few 6466 // specific situations), so there is no real need for users to add it to 6467 // the clobbers list if they want to use it in their inline assembly code. 6468 // 6469 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6470 // code generation, so using it in inline assembly without adding it to the 6471 // clobbers list can cause conflicts between the inline assembly code and 6472 // the surrounding generated code. 6473 // 6474 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6475 // operands, which will conflict with the ".set at" assembler option (which 6476 // we use only for inline assembly, in order to maintain compatibility with 6477 // GCC) and will also conflict with the user's usage of $1. 6478 // 6479 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6480 // register for generated code is to automatically clobber $1 for all inline 6481 // assembly code. 6482 // 6483 // FIXME: We should automatically clobber $1 only for inline assembly code 6484 // which actually uses it. This would allow LLVM to use $1 for inline 6485 // assembly operands if the user's assembly code doesn't use it. 6486 return "~{$1}"; 6487 } 6488 6489 bool handleTargetFeatures(std::vector<std::string> &Features, 6490 DiagnosticsEngine &Diags) override { 6491 IsMips16 = false; 6492 IsMicromips = false; 6493 IsNan2008 = isNaN2008Default(); 6494 IsSingleFloat = false; 6495 FloatABI = HardFloat; 6496 DspRev = NoDSP; 6497 HasFP64 = isFP64Default(); 6498 6499 for (const auto &Feature : Features) { 6500 if (Feature == "+single-float") 6501 IsSingleFloat = true; 6502 else if (Feature == "+soft-float") 6503 FloatABI = SoftFloat; 6504 else if (Feature == "+mips16") 6505 IsMips16 = true; 6506 else if (Feature == "+micromips") 6507 IsMicromips = true; 6508 else if (Feature == "+dsp") 6509 DspRev = std::max(DspRev, DSP1); 6510 else if (Feature == "+dspr2") 6511 DspRev = std::max(DspRev, DSP2); 6512 else if (Feature == "+msa") 6513 HasMSA = true; 6514 else if (Feature == "+fp64") 6515 HasFP64 = true; 6516 else if (Feature == "-fp64") 6517 HasFP64 = false; 6518 else if (Feature == "+nan2008") 6519 IsNan2008 = true; 6520 else if (Feature == "-nan2008") 6521 IsNan2008 = false; 6522 } 6523 6524 setDataLayoutString(); 6525 6526 return true; 6527 } 6528 6529 int getEHDataRegisterNumber(unsigned RegNo) const override { 6530 if (RegNo == 0) return 4; 6531 if (RegNo == 1) return 5; 6532 return -1; 6533 } 6534 6535 bool isCLZForZeroUndef() const override { return false; } 6536 }; 6537 6538 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6539 #define BUILTIN(ID, TYPE, ATTRS) \ 6540 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6541 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6542 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6543 #include "clang/Basic/BuiltinsMips.def" 6544 }; 6545 6546 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6547 public: 6548 Mips32TargetInfoBase(const llvm::Triple &Triple) 6549 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6550 SizeType = UnsignedInt; 6551 PtrDiffType = SignedInt; 6552 Int64Type = SignedLongLong; 6553 IntMaxType = Int64Type; 6554 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6555 } 6556 bool setABI(const std::string &Name) override { 6557 if (Name == "o32" || Name == "eabi") { 6558 ABI = Name; 6559 return true; 6560 } 6561 return false; 6562 } 6563 void getTargetDefines(const LangOptions &Opts, 6564 MacroBuilder &Builder) const override { 6565 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6566 6567 Builder.defineMacro("__mips", "32"); 6568 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6569 6570 const std::string& CPUStr = getCPU(); 6571 if (CPUStr == "mips32") 6572 Builder.defineMacro("__mips_isa_rev", "1"); 6573 else if (CPUStr == "mips32r2") 6574 Builder.defineMacro("__mips_isa_rev", "2"); 6575 else if (CPUStr == "mips32r3") 6576 Builder.defineMacro("__mips_isa_rev", "3"); 6577 else if (CPUStr == "mips32r5") 6578 Builder.defineMacro("__mips_isa_rev", "5"); 6579 else if (CPUStr == "mips32r6") 6580 Builder.defineMacro("__mips_isa_rev", "6"); 6581 6582 if (ABI == "o32") { 6583 Builder.defineMacro("__mips_o32"); 6584 Builder.defineMacro("_ABIO32", "1"); 6585 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6586 } 6587 else if (ABI == "eabi") 6588 Builder.defineMacro("__mips_eabi"); 6589 else 6590 llvm_unreachable("Invalid ABI for Mips32."); 6591 } 6592 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6593 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6594 { { "at" }, "$1" }, 6595 { { "v0" }, "$2" }, 6596 { { "v1" }, "$3" }, 6597 { { "a0" }, "$4" }, 6598 { { "a1" }, "$5" }, 6599 { { "a2" }, "$6" }, 6600 { { "a3" }, "$7" }, 6601 { { "t0" }, "$8" }, 6602 { { "t1" }, "$9" }, 6603 { { "t2" }, "$10" }, 6604 { { "t3" }, "$11" }, 6605 { { "t4" }, "$12" }, 6606 { { "t5" }, "$13" }, 6607 { { "t6" }, "$14" }, 6608 { { "t7" }, "$15" }, 6609 { { "s0" }, "$16" }, 6610 { { "s1" }, "$17" }, 6611 { { "s2" }, "$18" }, 6612 { { "s3" }, "$19" }, 6613 { { "s4" }, "$20" }, 6614 { { "s5" }, "$21" }, 6615 { { "s6" }, "$22" }, 6616 { { "s7" }, "$23" }, 6617 { { "t8" }, "$24" }, 6618 { { "t9" }, "$25" }, 6619 { { "k0" }, "$26" }, 6620 { { "k1" }, "$27" }, 6621 { { "gp" }, "$28" }, 6622 { { "sp","$sp" }, "$29" }, 6623 { { "fp","$fp" }, "$30" }, 6624 { { "ra" }, "$31" } 6625 }; 6626 return llvm::makeArrayRef(GCCRegAliases); 6627 } 6628 }; 6629 6630 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6631 void setDataLayoutString() override { 6632 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6633 } 6634 6635 public: 6636 Mips32EBTargetInfo(const llvm::Triple &Triple) 6637 : Mips32TargetInfoBase(Triple) { 6638 } 6639 void getTargetDefines(const LangOptions &Opts, 6640 MacroBuilder &Builder) const override { 6641 DefineStd(Builder, "MIPSEB", Opts); 6642 Builder.defineMacro("_MIPSEB"); 6643 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6644 } 6645 }; 6646 6647 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6648 void setDataLayoutString() override { 6649 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6650 } 6651 6652 public: 6653 Mips32ELTargetInfo(const llvm::Triple &Triple) 6654 : Mips32TargetInfoBase(Triple) { 6655 BigEndian = false; 6656 } 6657 void getTargetDefines(const LangOptions &Opts, 6658 MacroBuilder &Builder) const override { 6659 DefineStd(Builder, "MIPSEL", Opts); 6660 Builder.defineMacro("_MIPSEL"); 6661 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6662 } 6663 }; 6664 6665 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6666 public: 6667 Mips64TargetInfoBase(const llvm::Triple &Triple) 6668 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6669 LongDoubleWidth = LongDoubleAlign = 128; 6670 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6671 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6672 LongDoubleWidth = LongDoubleAlign = 64; 6673 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6674 } 6675 setN64ABITypes(); 6676 SuitableAlign = 128; 6677 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6678 } 6679 6680 void setN64ABITypes() { 6681 LongWidth = LongAlign = 64; 6682 PointerWidth = PointerAlign = 64; 6683 SizeType = UnsignedLong; 6684 PtrDiffType = SignedLong; 6685 Int64Type = SignedLong; 6686 IntMaxType = Int64Type; 6687 } 6688 6689 void setN32ABITypes() { 6690 LongWidth = LongAlign = 32; 6691 PointerWidth = PointerAlign = 32; 6692 SizeType = UnsignedInt; 6693 PtrDiffType = SignedInt; 6694 Int64Type = SignedLongLong; 6695 IntMaxType = Int64Type; 6696 } 6697 6698 bool setABI(const std::string &Name) override { 6699 if (Name == "n32") { 6700 setN32ABITypes(); 6701 ABI = Name; 6702 return true; 6703 } 6704 if (Name == "n64") { 6705 setN64ABITypes(); 6706 ABI = Name; 6707 return true; 6708 } 6709 return false; 6710 } 6711 6712 void getTargetDefines(const LangOptions &Opts, 6713 MacroBuilder &Builder) const override { 6714 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6715 6716 Builder.defineMacro("__mips", "64"); 6717 Builder.defineMacro("__mips64"); 6718 Builder.defineMacro("__mips64__"); 6719 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6720 6721 const std::string& CPUStr = getCPU(); 6722 if (CPUStr == "mips64") 6723 Builder.defineMacro("__mips_isa_rev", "1"); 6724 else if (CPUStr == "mips64r2") 6725 Builder.defineMacro("__mips_isa_rev", "2"); 6726 else if (CPUStr == "mips64r3") 6727 Builder.defineMacro("__mips_isa_rev", "3"); 6728 else if (CPUStr == "mips64r5") 6729 Builder.defineMacro("__mips_isa_rev", "5"); 6730 else if (CPUStr == "mips64r6") 6731 Builder.defineMacro("__mips_isa_rev", "6"); 6732 6733 if (ABI == "n32") { 6734 Builder.defineMacro("__mips_n32"); 6735 Builder.defineMacro("_ABIN32", "2"); 6736 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6737 } 6738 else if (ABI == "n64") { 6739 Builder.defineMacro("__mips_n64"); 6740 Builder.defineMacro("_ABI64", "3"); 6741 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6742 } 6743 else 6744 llvm_unreachable("Invalid ABI for Mips64."); 6745 } 6746 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6747 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6748 { { "at" }, "$1" }, 6749 { { "v0" }, "$2" }, 6750 { { "v1" }, "$3" }, 6751 { { "a0" }, "$4" }, 6752 { { "a1" }, "$5" }, 6753 { { "a2" }, "$6" }, 6754 { { "a3" }, "$7" }, 6755 { { "a4" }, "$8" }, 6756 { { "a5" }, "$9" }, 6757 { { "a6" }, "$10" }, 6758 { { "a7" }, "$11" }, 6759 { { "t0" }, "$12" }, 6760 { { "t1" }, "$13" }, 6761 { { "t2" }, "$14" }, 6762 { { "t3" }, "$15" }, 6763 { { "s0" }, "$16" }, 6764 { { "s1" }, "$17" }, 6765 { { "s2" }, "$18" }, 6766 { { "s3" }, "$19" }, 6767 { { "s4" }, "$20" }, 6768 { { "s5" }, "$21" }, 6769 { { "s6" }, "$22" }, 6770 { { "s7" }, "$23" }, 6771 { { "t8" }, "$24" }, 6772 { { "t9" }, "$25" }, 6773 { { "k0" }, "$26" }, 6774 { { "k1" }, "$27" }, 6775 { { "gp" }, "$28" }, 6776 { { "sp","$sp" }, "$29" }, 6777 { { "fp","$fp" }, "$30" }, 6778 { { "ra" }, "$31" } 6779 }; 6780 return llvm::makeArrayRef(GCCRegAliases); 6781 } 6782 6783 bool hasInt128Type() const override { return true; } 6784 }; 6785 6786 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6787 void setDataLayoutString() override { 6788 if (ABI == "n32") 6789 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6790 else 6791 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6792 6793 } 6794 6795 public: 6796 Mips64EBTargetInfo(const llvm::Triple &Triple) 6797 : Mips64TargetInfoBase(Triple) {} 6798 void getTargetDefines(const LangOptions &Opts, 6799 MacroBuilder &Builder) const override { 6800 DefineStd(Builder, "MIPSEB", Opts); 6801 Builder.defineMacro("_MIPSEB"); 6802 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6803 } 6804 }; 6805 6806 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6807 void setDataLayoutString() override { 6808 if (ABI == "n32") 6809 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6810 else 6811 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6812 } 6813 public: 6814 Mips64ELTargetInfo(const llvm::Triple &Triple) 6815 : Mips64TargetInfoBase(Triple) { 6816 // Default ABI is n64. 6817 BigEndian = false; 6818 } 6819 void getTargetDefines(const LangOptions &Opts, 6820 MacroBuilder &Builder) const override { 6821 DefineStd(Builder, "MIPSEL", Opts); 6822 Builder.defineMacro("_MIPSEL"); 6823 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6824 } 6825 }; 6826 6827 class PNaClTargetInfo : public TargetInfo { 6828 public: 6829 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6830 BigEndian = false; 6831 this->UserLabelPrefix = ""; 6832 this->LongAlign = 32; 6833 this->LongWidth = 32; 6834 this->PointerAlign = 32; 6835 this->PointerWidth = 32; 6836 this->IntMaxType = TargetInfo::SignedLongLong; 6837 this->Int64Type = TargetInfo::SignedLongLong; 6838 this->DoubleAlign = 64; 6839 this->LongDoubleWidth = 64; 6840 this->LongDoubleAlign = 64; 6841 this->SizeType = TargetInfo::UnsignedInt; 6842 this->PtrDiffType = TargetInfo::SignedInt; 6843 this->IntPtrType = TargetInfo::SignedInt; 6844 this->RegParmMax = 0; // Disallow regparm 6845 } 6846 6847 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6848 Builder.defineMacro("__le32__"); 6849 Builder.defineMacro("__pnacl__"); 6850 } 6851 void getTargetDefines(const LangOptions &Opts, 6852 MacroBuilder &Builder) const override { 6853 getArchDefines(Opts, Builder); 6854 } 6855 bool hasFeature(StringRef Feature) const override { 6856 return Feature == "pnacl"; 6857 } 6858 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6859 BuiltinVaListKind getBuiltinVaListKind() const override { 6860 return TargetInfo::PNaClABIBuiltinVaList; 6861 } 6862 ArrayRef<const char *> getGCCRegNames() const override; 6863 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6864 bool validateAsmConstraint(const char *&Name, 6865 TargetInfo::ConstraintInfo &Info) const override { 6866 return false; 6867 } 6868 6869 const char *getClobbers() const override { 6870 return ""; 6871 } 6872 }; 6873 6874 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 6875 return None; 6876 } 6877 6878 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 6879 return None; 6880 } 6881 6882 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 6883 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 6884 public: 6885 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 6886 Mips32ELTargetInfo(Triple) { 6887 } 6888 6889 BuiltinVaListKind getBuiltinVaListKind() const override { 6890 return TargetInfo::PNaClABIBuiltinVaList; 6891 } 6892 }; 6893 6894 class Le64TargetInfo : public TargetInfo { 6895 static const Builtin::Info BuiltinInfo[]; 6896 6897 public: 6898 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6899 BigEndian = false; 6900 NoAsmVariants = true; 6901 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6902 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6903 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6904 } 6905 6906 void getTargetDefines(const LangOptions &Opts, 6907 MacroBuilder &Builder) const override { 6908 DefineStd(Builder, "unix", Opts); 6909 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6910 Builder.defineMacro("__ELF__"); 6911 } 6912 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6913 return llvm::makeArrayRef(BuiltinInfo, 6914 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6915 } 6916 BuiltinVaListKind getBuiltinVaListKind() const override { 6917 return TargetInfo::PNaClABIBuiltinVaList; 6918 } 6919 const char *getClobbers() const override { return ""; } 6920 ArrayRef<const char *> getGCCRegNames() const override { 6921 return None; 6922 } 6923 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6924 return None; 6925 } 6926 bool validateAsmConstraint(const char *&Name, 6927 TargetInfo::ConstraintInfo &Info) const override { 6928 return false; 6929 } 6930 6931 bool hasProtectedVisibility() const override { return false; } 6932 }; 6933 6934 class WebAssemblyTargetInfo : public TargetInfo { 6935 static const Builtin::Info BuiltinInfo[]; 6936 6937 enum SIMDEnum { 6938 NoSIMD, 6939 SIMD128, 6940 } SIMDLevel; 6941 6942 public: 6943 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 6944 : TargetInfo(T), SIMDLevel(NoSIMD) { 6945 BigEndian = false; 6946 NoAsmVariants = true; 6947 SuitableAlign = 128; 6948 LargeArrayMinWidth = 128; 6949 LargeArrayAlign = 128; 6950 SimdDefaultAlign = 128; 6951 SigAtomicType = SignedLong; 6952 } 6953 6954 protected: 6955 void getTargetDefines(const LangOptions &Opts, 6956 MacroBuilder &Builder) const override { 6957 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 6958 if (SIMDLevel >= SIMD128) 6959 Builder.defineMacro("__wasm_simd128__"); 6960 } 6961 6962 private: 6963 bool 6964 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6965 StringRef CPU, 6966 const std::vector<std::string> &FeaturesVec) const override { 6967 if (CPU == "bleeding-edge") 6968 Features["simd128"] = true; 6969 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6970 } 6971 bool hasFeature(StringRef Feature) const final { 6972 return llvm::StringSwitch<bool>(Feature) 6973 .Case("simd128", SIMDLevel >= SIMD128) 6974 .Default(false); 6975 } 6976 bool handleTargetFeatures(std::vector<std::string> &Features, 6977 DiagnosticsEngine &Diags) final { 6978 for (const auto &Feature : Features) { 6979 if (Feature == "+simd128") { 6980 SIMDLevel = std::max(SIMDLevel, SIMD128); 6981 continue; 6982 } 6983 if (Feature == "-simd128") { 6984 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 6985 continue; 6986 } 6987 6988 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 6989 << "-target-feature"; 6990 return false; 6991 } 6992 return true; 6993 } 6994 bool setCPU(const std::string &Name) final { 6995 return llvm::StringSwitch<bool>(Name) 6996 .Case("mvp", true) 6997 .Case("bleeding-edge", true) 6998 .Case("generic", true) 6999 .Default(false); 7000 } 7001 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7002 return llvm::makeArrayRef(BuiltinInfo, 7003 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7004 } 7005 BuiltinVaListKind getBuiltinVaListKind() const final { 7006 // TODO: Implement va_list properly. 7007 return VoidPtrBuiltinVaList; 7008 } 7009 ArrayRef<const char *> getGCCRegNames() const final { 7010 return None; 7011 } 7012 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7013 return None; 7014 } 7015 bool 7016 validateAsmConstraint(const char *&Name, 7017 TargetInfo::ConstraintInfo &Info) const final { 7018 return false; 7019 } 7020 const char *getClobbers() const final { return ""; } 7021 bool isCLZForZeroUndef() const final { return false; } 7022 bool hasInt128Type() const final { return true; } 7023 IntType getIntTypeByWidth(unsigned BitWidth, 7024 bool IsSigned) const final { 7025 // WebAssembly prefers long long for explicitly 64-bit integers. 7026 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7027 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7028 } 7029 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7030 bool IsSigned) const final { 7031 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7032 return BitWidth == 64 7033 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7034 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7035 } 7036 }; 7037 7038 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7039 #define BUILTIN(ID, TYPE, ATTRS) \ 7040 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7041 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7042 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7043 #include "clang/Basic/BuiltinsWebAssembly.def" 7044 }; 7045 7046 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7047 public: 7048 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7049 : WebAssemblyTargetInfo(T) { 7050 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7051 DataLayoutString = "e-p:32:32-i64:64-n32:64-S128"; 7052 } 7053 7054 protected: 7055 void getTargetDefines(const LangOptions &Opts, 7056 MacroBuilder &Builder) const override { 7057 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7058 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7059 } 7060 }; 7061 7062 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7063 public: 7064 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7065 : WebAssemblyTargetInfo(T) { 7066 LongAlign = LongWidth = 64; 7067 PointerAlign = PointerWidth = 64; 7068 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7069 DataLayoutString = "e-p:64:64-i64:64-n32:64-S128"; 7070 } 7071 7072 protected: 7073 void getTargetDefines(const LangOptions &Opts, 7074 MacroBuilder &Builder) const override { 7075 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7076 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7077 } 7078 }; 7079 7080 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7081 #define BUILTIN(ID, TYPE, ATTRS) \ 7082 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7083 #include "clang/Basic/BuiltinsLe64.def" 7084 }; 7085 7086 static const unsigned SPIRAddrSpaceMap[] = { 7087 1, // opencl_global 7088 3, // opencl_local 7089 2, // opencl_constant 7090 4, // opencl_generic 7091 0, // cuda_device 7092 0, // cuda_constant 7093 0 // cuda_shared 7094 }; 7095 class SPIRTargetInfo : public TargetInfo { 7096 public: 7097 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7098 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7099 "SPIR target must use unknown OS"); 7100 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7101 "SPIR target must use unknown environment type"); 7102 BigEndian = false; 7103 TLSSupported = false; 7104 LongWidth = LongAlign = 64; 7105 AddrSpaceMap = &SPIRAddrSpaceMap; 7106 UseAddrSpaceMapMangling = true; 7107 // Define available target features 7108 // These must be defined in sorted order! 7109 NoAsmVariants = true; 7110 } 7111 void getTargetDefines(const LangOptions &Opts, 7112 MacroBuilder &Builder) const override { 7113 DefineStd(Builder, "SPIR", Opts); 7114 } 7115 bool hasFeature(StringRef Feature) const override { 7116 return Feature == "spir"; 7117 } 7118 7119 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7120 const char *getClobbers() const override { return ""; } 7121 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7122 bool validateAsmConstraint(const char *&Name, 7123 TargetInfo::ConstraintInfo &info) const override { 7124 return true; 7125 } 7126 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7127 return None; 7128 } 7129 BuiltinVaListKind getBuiltinVaListKind() const override { 7130 return TargetInfo::VoidPtrBuiltinVaList; 7131 } 7132 7133 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7134 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7135 : CCCR_Warning; 7136 } 7137 7138 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7139 return CC_SpirFunction; 7140 } 7141 }; 7142 7143 class SPIR32TargetInfo : public SPIRTargetInfo { 7144 public: 7145 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7146 PointerWidth = PointerAlign = 32; 7147 SizeType = TargetInfo::UnsignedInt; 7148 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7149 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7150 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7151 } 7152 void getTargetDefines(const LangOptions &Opts, 7153 MacroBuilder &Builder) const override { 7154 DefineStd(Builder, "SPIR32", Opts); 7155 } 7156 }; 7157 7158 class SPIR64TargetInfo : public SPIRTargetInfo { 7159 public: 7160 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7161 PointerWidth = PointerAlign = 64; 7162 SizeType = TargetInfo::UnsignedLong; 7163 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7164 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7165 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7166 } 7167 void getTargetDefines(const LangOptions &Opts, 7168 MacroBuilder &Builder) const override { 7169 DefineStd(Builder, "SPIR64", Opts); 7170 } 7171 }; 7172 7173 class XCoreTargetInfo : public TargetInfo { 7174 static const Builtin::Info BuiltinInfo[]; 7175 public: 7176 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7177 BigEndian = false; 7178 NoAsmVariants = true; 7179 LongLongAlign = 32; 7180 SuitableAlign = 32; 7181 DoubleAlign = LongDoubleAlign = 32; 7182 SizeType = UnsignedInt; 7183 PtrDiffType = SignedInt; 7184 IntPtrType = SignedInt; 7185 WCharType = UnsignedChar; 7186 WIntType = UnsignedInt; 7187 UseZeroLengthBitfieldAlignment = true; 7188 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7189 "-f64:32-a:0:32-n32"; 7190 } 7191 void getTargetDefines(const LangOptions &Opts, 7192 MacroBuilder &Builder) const override { 7193 Builder.defineMacro("__XS1B__"); 7194 } 7195 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7196 return llvm::makeArrayRef(BuiltinInfo, 7197 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7198 } 7199 BuiltinVaListKind getBuiltinVaListKind() const override { 7200 return TargetInfo::VoidPtrBuiltinVaList; 7201 } 7202 const char *getClobbers() const override { 7203 return ""; 7204 } 7205 ArrayRef<const char *> getGCCRegNames() const override { 7206 static const char * const GCCRegNames[] = { 7207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7208 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7209 }; 7210 return llvm::makeArrayRef(GCCRegNames); 7211 } 7212 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7213 return None; 7214 } 7215 bool validateAsmConstraint(const char *&Name, 7216 TargetInfo::ConstraintInfo &Info) const override { 7217 return false; 7218 } 7219 int getEHDataRegisterNumber(unsigned RegNo) const override { 7220 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7221 return (RegNo < 2)? RegNo : -1; 7222 } 7223 }; 7224 7225 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7226 #define BUILTIN(ID, TYPE, ATTRS) \ 7227 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7228 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7229 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7230 #include "clang/Basic/BuiltinsXCore.def" 7231 }; 7232 7233 // x86_32 Android target 7234 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7235 public: 7236 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7237 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7238 SuitableAlign = 32; 7239 LongDoubleWidth = 64; 7240 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7241 } 7242 }; 7243 7244 // x86_64 Android target 7245 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7246 public: 7247 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7248 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7249 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7250 } 7251 7252 bool useFloat128ManglingForLongDouble() const override { 7253 return true; 7254 } 7255 }; 7256 } // end anonymous namespace 7257 7258 //===----------------------------------------------------------------------===// 7259 // Driver code 7260 //===----------------------------------------------------------------------===// 7261 7262 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7263 llvm::Triple::OSType os = Triple.getOS(); 7264 7265 switch (Triple.getArch()) { 7266 default: 7267 return nullptr; 7268 7269 case llvm::Triple::xcore: 7270 return new XCoreTargetInfo(Triple); 7271 7272 case llvm::Triple::hexagon: 7273 return new HexagonTargetInfo(Triple); 7274 7275 case llvm::Triple::aarch64: 7276 if (Triple.isOSDarwin()) 7277 return new DarwinAArch64TargetInfo(Triple); 7278 7279 switch (os) { 7280 case llvm::Triple::CloudABI: 7281 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple); 7282 case llvm::Triple::FreeBSD: 7283 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7284 case llvm::Triple::Linux: 7285 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7286 case llvm::Triple::NetBSD: 7287 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7288 default: 7289 return new AArch64leTargetInfo(Triple); 7290 } 7291 7292 case llvm::Triple::aarch64_be: 7293 switch (os) { 7294 case llvm::Triple::FreeBSD: 7295 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7296 case llvm::Triple::Linux: 7297 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7298 case llvm::Triple::NetBSD: 7299 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7300 default: 7301 return new AArch64beTargetInfo(Triple); 7302 } 7303 7304 case llvm::Triple::arm: 7305 case llvm::Triple::thumb: 7306 if (Triple.isOSBinFormatMachO()) 7307 return new DarwinARMTargetInfo(Triple); 7308 7309 switch (os) { 7310 case llvm::Triple::Linux: 7311 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7312 case llvm::Triple::FreeBSD: 7313 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7314 case llvm::Triple::NetBSD: 7315 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7316 case llvm::Triple::OpenBSD: 7317 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7318 case llvm::Triple::Bitrig: 7319 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7320 case llvm::Triple::RTEMS: 7321 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7322 case llvm::Triple::NaCl: 7323 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7324 case llvm::Triple::Win32: 7325 switch (Triple.getEnvironment()) { 7326 case llvm::Triple::Cygnus: 7327 return new CygwinARMTargetInfo(Triple); 7328 case llvm::Triple::GNU: 7329 return new MinGWARMTargetInfo(Triple); 7330 case llvm::Triple::Itanium: 7331 return new ItaniumWindowsARMleTargetInfo(Triple); 7332 case llvm::Triple::MSVC: 7333 default: // Assume MSVC for unknown environments 7334 return new MicrosoftARMleTargetInfo(Triple); 7335 } 7336 default: 7337 return new ARMleTargetInfo(Triple); 7338 } 7339 7340 case llvm::Triple::armeb: 7341 case llvm::Triple::thumbeb: 7342 if (Triple.isOSDarwin()) 7343 return new DarwinARMTargetInfo(Triple); 7344 7345 switch (os) { 7346 case llvm::Triple::Linux: 7347 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7348 case llvm::Triple::FreeBSD: 7349 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7350 case llvm::Triple::NetBSD: 7351 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7352 case llvm::Triple::OpenBSD: 7353 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7354 case llvm::Triple::Bitrig: 7355 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7356 case llvm::Triple::RTEMS: 7357 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7358 case llvm::Triple::NaCl: 7359 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7360 default: 7361 return new ARMbeTargetInfo(Triple); 7362 } 7363 7364 case llvm::Triple::bpfeb: 7365 case llvm::Triple::bpfel: 7366 return new BPFTargetInfo(Triple); 7367 7368 case llvm::Triple::msp430: 7369 return new MSP430TargetInfo(Triple); 7370 7371 case llvm::Triple::mips: 7372 switch (os) { 7373 case llvm::Triple::Linux: 7374 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7375 case llvm::Triple::RTEMS: 7376 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7377 case llvm::Triple::FreeBSD: 7378 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7379 case llvm::Triple::NetBSD: 7380 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7381 default: 7382 return new Mips32EBTargetInfo(Triple); 7383 } 7384 7385 case llvm::Triple::mipsel: 7386 switch (os) { 7387 case llvm::Triple::Linux: 7388 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7389 case llvm::Triple::RTEMS: 7390 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7391 case llvm::Triple::FreeBSD: 7392 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7393 case llvm::Triple::NetBSD: 7394 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7395 case llvm::Triple::NaCl: 7396 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7397 default: 7398 return new Mips32ELTargetInfo(Triple); 7399 } 7400 7401 case llvm::Triple::mips64: 7402 switch (os) { 7403 case llvm::Triple::Linux: 7404 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7405 case llvm::Triple::RTEMS: 7406 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7407 case llvm::Triple::FreeBSD: 7408 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7409 case llvm::Triple::NetBSD: 7410 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7411 case llvm::Triple::OpenBSD: 7412 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7413 default: 7414 return new Mips64EBTargetInfo(Triple); 7415 } 7416 7417 case llvm::Triple::mips64el: 7418 switch (os) { 7419 case llvm::Triple::Linux: 7420 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7421 case llvm::Triple::RTEMS: 7422 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7423 case llvm::Triple::FreeBSD: 7424 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7425 case llvm::Triple::NetBSD: 7426 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7427 case llvm::Triple::OpenBSD: 7428 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7429 default: 7430 return new Mips64ELTargetInfo(Triple); 7431 } 7432 7433 case llvm::Triple::le32: 7434 switch (os) { 7435 case llvm::Triple::NaCl: 7436 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7437 default: 7438 return nullptr; 7439 } 7440 7441 case llvm::Triple::le64: 7442 return new Le64TargetInfo(Triple); 7443 7444 case llvm::Triple::ppc: 7445 if (Triple.isOSDarwin()) 7446 return new DarwinPPC32TargetInfo(Triple); 7447 switch (os) { 7448 case llvm::Triple::Linux: 7449 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7450 case llvm::Triple::FreeBSD: 7451 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7452 case llvm::Triple::NetBSD: 7453 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7454 case llvm::Triple::OpenBSD: 7455 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7456 case llvm::Triple::RTEMS: 7457 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7458 default: 7459 return new PPC32TargetInfo(Triple); 7460 } 7461 7462 case llvm::Triple::ppc64: 7463 if (Triple.isOSDarwin()) 7464 return new DarwinPPC64TargetInfo(Triple); 7465 switch (os) { 7466 case llvm::Triple::Linux: 7467 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7468 case llvm::Triple::Lv2: 7469 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7470 case llvm::Triple::FreeBSD: 7471 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7472 case llvm::Triple::NetBSD: 7473 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7474 default: 7475 return new PPC64TargetInfo(Triple); 7476 } 7477 7478 case llvm::Triple::ppc64le: 7479 switch (os) { 7480 case llvm::Triple::Linux: 7481 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7482 case llvm::Triple::NetBSD: 7483 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7484 default: 7485 return new PPC64TargetInfo(Triple); 7486 } 7487 7488 case llvm::Triple::nvptx: 7489 return new NVPTX32TargetInfo(Triple); 7490 case llvm::Triple::nvptx64: 7491 return new NVPTX64TargetInfo(Triple); 7492 7493 case llvm::Triple::amdgcn: 7494 case llvm::Triple::r600: 7495 return new AMDGPUTargetInfo(Triple); 7496 7497 case llvm::Triple::sparc: 7498 switch (os) { 7499 case llvm::Triple::Linux: 7500 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7501 case llvm::Triple::Solaris: 7502 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7503 case llvm::Triple::NetBSD: 7504 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7505 case llvm::Triple::OpenBSD: 7506 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7507 case llvm::Triple::RTEMS: 7508 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7509 default: 7510 return new SparcV8TargetInfo(Triple); 7511 } 7512 7513 // The 'sparcel' architecture copies all the above cases except for Solaris. 7514 case llvm::Triple::sparcel: 7515 switch (os) { 7516 case llvm::Triple::Linux: 7517 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7518 case llvm::Triple::NetBSD: 7519 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7520 case llvm::Triple::OpenBSD: 7521 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7522 case llvm::Triple::RTEMS: 7523 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7524 default: 7525 return new SparcV8elTargetInfo(Triple); 7526 } 7527 7528 case llvm::Triple::sparcv9: 7529 switch (os) { 7530 case llvm::Triple::Linux: 7531 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7532 case llvm::Triple::Solaris: 7533 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7534 case llvm::Triple::NetBSD: 7535 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7536 case llvm::Triple::OpenBSD: 7537 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7538 case llvm::Triple::FreeBSD: 7539 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7540 default: 7541 return new SparcV9TargetInfo(Triple); 7542 } 7543 7544 case llvm::Triple::systemz: 7545 switch (os) { 7546 case llvm::Triple::Linux: 7547 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7548 default: 7549 return new SystemZTargetInfo(Triple); 7550 } 7551 7552 case llvm::Triple::tce: 7553 return new TCETargetInfo(Triple); 7554 7555 case llvm::Triple::x86: 7556 if (Triple.isOSDarwin()) 7557 return new DarwinI386TargetInfo(Triple); 7558 7559 switch (os) { 7560 case llvm::Triple::CloudABI: 7561 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7562 case llvm::Triple::Linux: { 7563 switch (Triple.getEnvironment()) { 7564 default: 7565 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7566 case llvm::Triple::Android: 7567 return new AndroidX86_32TargetInfo(Triple); 7568 } 7569 } 7570 case llvm::Triple::DragonFly: 7571 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7572 case llvm::Triple::NetBSD: 7573 return new NetBSDI386TargetInfo(Triple); 7574 case llvm::Triple::OpenBSD: 7575 return new OpenBSDI386TargetInfo(Triple); 7576 case llvm::Triple::Bitrig: 7577 return new BitrigI386TargetInfo(Triple); 7578 case llvm::Triple::FreeBSD: 7579 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7580 case llvm::Triple::KFreeBSD: 7581 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7582 case llvm::Triple::Minix: 7583 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7584 case llvm::Triple::Solaris: 7585 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7586 case llvm::Triple::Win32: { 7587 switch (Triple.getEnvironment()) { 7588 case llvm::Triple::Cygnus: 7589 return new CygwinX86_32TargetInfo(Triple); 7590 case llvm::Triple::GNU: 7591 return new MinGWX86_32TargetInfo(Triple); 7592 case llvm::Triple::Itanium: 7593 case llvm::Triple::MSVC: 7594 default: // Assume MSVC for unknown environments 7595 return new MicrosoftX86_32TargetInfo(Triple); 7596 } 7597 } 7598 case llvm::Triple::Haiku: 7599 return new HaikuX86_32TargetInfo(Triple); 7600 case llvm::Triple::RTEMS: 7601 return new RTEMSX86_32TargetInfo(Triple); 7602 case llvm::Triple::NaCl: 7603 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7604 default: 7605 return new X86_32TargetInfo(Triple); 7606 } 7607 7608 case llvm::Triple::x86_64: 7609 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7610 return new DarwinX86_64TargetInfo(Triple); 7611 7612 switch (os) { 7613 case llvm::Triple::CloudABI: 7614 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7615 case llvm::Triple::Linux: { 7616 switch (Triple.getEnvironment()) { 7617 default: 7618 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7619 case llvm::Triple::Android: 7620 return new AndroidX86_64TargetInfo(Triple); 7621 } 7622 } 7623 case llvm::Triple::DragonFly: 7624 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7625 case llvm::Triple::NetBSD: 7626 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7627 case llvm::Triple::OpenBSD: 7628 return new OpenBSDX86_64TargetInfo(Triple); 7629 case llvm::Triple::Bitrig: 7630 return new BitrigX86_64TargetInfo(Triple); 7631 case llvm::Triple::FreeBSD: 7632 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7633 case llvm::Triple::KFreeBSD: 7634 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7635 case llvm::Triple::Solaris: 7636 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7637 case llvm::Triple::Win32: { 7638 switch (Triple.getEnvironment()) { 7639 case llvm::Triple::Cygnus: 7640 return new CygwinX86_64TargetInfo(Triple); 7641 case llvm::Triple::GNU: 7642 return new MinGWX86_64TargetInfo(Triple); 7643 case llvm::Triple::MSVC: 7644 default: // Assume MSVC for unknown environments 7645 return new MicrosoftX86_64TargetInfo(Triple); 7646 } 7647 } 7648 case llvm::Triple::NaCl: 7649 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7650 case llvm::Triple::PS4: 7651 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7652 default: 7653 return new X86_64TargetInfo(Triple); 7654 } 7655 7656 case llvm::Triple::spir: { 7657 if (Triple.getOS() != llvm::Triple::UnknownOS || 7658 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7659 return nullptr; 7660 return new SPIR32TargetInfo(Triple); 7661 } 7662 case llvm::Triple::spir64: { 7663 if (Triple.getOS() != llvm::Triple::UnknownOS || 7664 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7665 return nullptr; 7666 return new SPIR64TargetInfo(Triple); 7667 } 7668 case llvm::Triple::wasm32: 7669 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 7670 return nullptr; 7671 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 7672 case llvm::Triple::wasm64: 7673 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 7674 return nullptr; 7675 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 7676 } 7677 } 7678 7679 /// CreateTargetInfo - Return the target info object for the specified target 7680 /// options. 7681 TargetInfo * 7682 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7683 const std::shared_ptr<TargetOptions> &Opts) { 7684 llvm::Triple Triple(Opts->Triple); 7685 7686 // Construct the target 7687 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7688 if (!Target) { 7689 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7690 return nullptr; 7691 } 7692 Target->TargetOpts = Opts; 7693 7694 // Set the target CPU if specified. 7695 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7696 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7697 return nullptr; 7698 } 7699 7700 // Set the target ABI if specified. 7701 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7702 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7703 return nullptr; 7704 } 7705 7706 // Set the fp math unit. 7707 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7708 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7709 return nullptr; 7710 } 7711 7712 // Compute the default target features, we need the target to handle this 7713 // because features may have dependencies on one another. 7714 llvm::StringMap<bool> Features; 7715 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 7716 Opts->FeaturesAsWritten)) 7717 return nullptr; 7718 7719 // Add the features to the compile options. 7720 Opts->Features.clear(); 7721 for (const auto &F : Features) 7722 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 7723 7724 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7725 return nullptr; 7726 7727 return Target.release(); 7728 } 7729