1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/OwningPtr.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/IR/Type.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include <algorithm> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 virtual void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 94 // AddressSanitizer doesn't play well with source fortification, which is on 95 // by default on Darwin. 96 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 97 98 if (!Opts.ObjCAutoRefCount) { 99 // __weak is always defined, for use in blocks and with objc pointers. 100 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 101 102 // Darwin defines __strong even in C mode (just to nothing). 103 if (Opts.getGC() != LangOptions::NonGC) 104 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 105 else 106 Builder.defineMacro("__strong", ""); 107 108 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 109 // allow this in C, since one might have block pointers in structs that 110 // are used in pure C code and in Objective-C ARC. 111 Builder.defineMacro("__unsafe_unretained", ""); 112 } 113 114 if (Opts.Static) 115 Builder.defineMacro("__STATIC__"); 116 else 117 Builder.defineMacro("__DYNAMIC__"); 118 119 if (Opts.POSIXThreads) 120 Builder.defineMacro("_REENTRANT"); 121 122 // Get the platform type and version number from the triple. 123 unsigned Maj, Min, Rev; 124 if (Triple.isMacOSX()) { 125 Triple.getMacOSXVersion(Maj, Min, Rev); 126 PlatformName = "macosx"; 127 } else { 128 Triple.getOSVersion(Maj, Min, Rev); 129 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 130 } 131 132 // If -target arch-pc-win32-macho option specified, we're 133 // generating code for Win32 ABI. No need to emit 134 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 135 if (PlatformName == "win32") { 136 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 137 return; 138 } 139 140 // If there's an environment specified in the triple, that means we're dealing 141 // with an embedded variant of some sort and don't want the platform 142 // version-min defines, so only add them if there's not one. 143 if (Triple.getEnvironmentName().empty()) { 144 // Set the appropriate OS version define. 145 if (Triple.isiOS()) { 146 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 147 char Str[6]; 148 Str[0] = '0' + Maj; 149 Str[1] = '0' + (Min / 10); 150 Str[2] = '0' + (Min % 10); 151 Str[3] = '0' + (Rev / 10); 152 Str[4] = '0' + (Rev % 10); 153 Str[5] = '\0'; 154 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 155 Str); 156 } else if (Triple.isMacOSX()) { 157 // Note that the Driver allows versions which aren't representable in the 158 // define (because we only get a single digit for the minor and micro 159 // revision numbers). So, we limit them to the maximum representable 160 // version. 161 assert(Triple.getEnvironmentName().empty() && "Invalid environment!"); 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[5]; 164 Str[0] = '0' + (Maj / 10); 165 Str[1] = '0' + (Maj % 10); 166 Str[2] = '0' + std::min(Min, 9U); 167 Str[3] = '0' + std::min(Rev, 9U); 168 Str[4] = '\0'; 169 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 170 } 171 } 172 173 // Tell users about the kernel if there is one. 174 if (Triple.isOSDarwin()) 175 Builder.defineMacro("__MACH__"); 176 177 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 178 } 179 180 namespace { 181 template<typename Target> 182 class DarwinTargetInfo : public OSTargetInfo<Target> { 183 protected: 184 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 185 MacroBuilder &Builder) const { 186 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 187 this->PlatformMinVersion); 188 } 189 190 public: 191 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 192 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 193 this->MCountName = "\01mcount"; 194 } 195 196 virtual std::string isValidSectionSpecifier(StringRef SR) const { 197 // Let MCSectionMachO validate this. 198 StringRef Segment, Section; 199 unsigned TAA, StubSize; 200 bool HasTAA; 201 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 202 TAA, HasTAA, StubSize); 203 } 204 205 virtual const char *getStaticInitSectionSpecifier() const { 206 // FIXME: We should return 0 when building kexts. 207 return "__TEXT,__StaticInit,regular,pure_instructions"; 208 } 209 210 /// Darwin does not support protected visibility. Darwin's "default" 211 /// is very similar to ELF's "protected"; Darwin requires a "weak" 212 /// attribute on declarations that can be dynamically replaced. 213 virtual bool hasProtectedVisibility() const { 214 return false; 215 } 216 }; 217 218 219 // DragonFlyBSD Target 220 template<typename Target> 221 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 222 protected: 223 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 224 MacroBuilder &Builder) const { 225 // DragonFly defines; list based off of gcc output 226 Builder.defineMacro("__DragonFly__"); 227 Builder.defineMacro("__DragonFly_cc_version", "100001"); 228 Builder.defineMacro("__ELF__"); 229 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 230 Builder.defineMacro("__tune_i386__"); 231 DefineStd(Builder, "unix", Opts); 232 } 233 public: 234 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 235 : OSTargetInfo<Target>(Triple) { 236 this->UserLabelPrefix = ""; 237 238 switch (Triple.getArch()) { 239 default: 240 case llvm::Triple::x86: 241 case llvm::Triple::x86_64: 242 this->MCountName = ".mcount"; 243 break; 244 } 245 } 246 }; 247 248 // FreeBSD Target 249 template<typename Target> 250 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 251 protected: 252 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 253 MacroBuilder &Builder) const { 254 // FreeBSD defines; list based off of gcc output 255 256 unsigned Release = Triple.getOSMajorVersion(); 257 if (Release == 0U) 258 Release = 8; 259 260 Builder.defineMacro("__FreeBSD__", Twine(Release)); 261 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 262 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 263 DefineStd(Builder, "unix", Opts); 264 Builder.defineMacro("__ELF__"); 265 266 // On FreeBSD, wchar_t contains the number of the code point as 267 // used by the character set of the locale. These character sets are 268 // not necessarily a superset of ASCII. 269 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 270 } 271 public: 272 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 273 this->UserLabelPrefix = ""; 274 275 switch (Triple.getArch()) { 276 default: 277 case llvm::Triple::x86: 278 case llvm::Triple::x86_64: 279 this->MCountName = ".mcount"; 280 break; 281 case llvm::Triple::mips: 282 case llvm::Triple::mipsel: 283 case llvm::Triple::ppc: 284 case llvm::Triple::ppc64: 285 case llvm::Triple::ppc64le: 286 this->MCountName = "_mcount"; 287 break; 288 case llvm::Triple::arm: 289 this->MCountName = "__mcount"; 290 break; 291 } 292 } 293 }; 294 295 // GNU/kFreeBSD Target 296 template<typename Target> 297 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 298 protected: 299 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 300 MacroBuilder &Builder) const { 301 // GNU/kFreeBSD defines; list based off of gcc output 302 303 DefineStd(Builder, "unix", Opts); 304 Builder.defineMacro("__FreeBSD_kernel__"); 305 Builder.defineMacro("__GLIBC__"); 306 Builder.defineMacro("__ELF__"); 307 if (Opts.POSIXThreads) 308 Builder.defineMacro("_REENTRANT"); 309 if (Opts.CPlusPlus) 310 Builder.defineMacro("_GNU_SOURCE"); 311 } 312 public: 313 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 314 this->UserLabelPrefix = ""; 315 } 316 }; 317 318 // Minix Target 319 template<typename Target> 320 class MinixTargetInfo : public OSTargetInfo<Target> { 321 protected: 322 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 323 MacroBuilder &Builder) const { 324 // Minix defines 325 326 Builder.defineMacro("__minix", "3"); 327 Builder.defineMacro("_EM_WSIZE", "4"); 328 Builder.defineMacro("_EM_PSIZE", "4"); 329 Builder.defineMacro("_EM_SSIZE", "2"); 330 Builder.defineMacro("_EM_LSIZE", "4"); 331 Builder.defineMacro("_EM_FSIZE", "4"); 332 Builder.defineMacro("_EM_DSIZE", "8"); 333 Builder.defineMacro("__ELF__"); 334 DefineStd(Builder, "unix", Opts); 335 } 336 public: 337 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 338 this->UserLabelPrefix = ""; 339 } 340 }; 341 342 // Linux target 343 template<typename Target> 344 class LinuxTargetInfo : public OSTargetInfo<Target> { 345 protected: 346 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 347 MacroBuilder &Builder) const { 348 // Linux defines; list based off of gcc output 349 DefineStd(Builder, "unix", Opts); 350 DefineStd(Builder, "linux", Opts); 351 Builder.defineMacro("__gnu_linux__"); 352 Builder.defineMacro("__ELF__"); 353 if (Triple.getEnvironment() == llvm::Triple::Android) 354 Builder.defineMacro("__ANDROID__", "1"); 355 if (Opts.POSIXThreads) 356 Builder.defineMacro("_REENTRANT"); 357 if (Opts.CPlusPlus) 358 Builder.defineMacro("_GNU_SOURCE"); 359 } 360 public: 361 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 362 this->UserLabelPrefix = ""; 363 this->WIntType = TargetInfo::UnsignedInt; 364 } 365 366 virtual const char *getStaticInitSectionSpecifier() const { 367 return ".text.startup"; 368 } 369 }; 370 371 // NetBSD Target 372 template<typename Target> 373 class NetBSDTargetInfo : public OSTargetInfo<Target> { 374 protected: 375 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 376 MacroBuilder &Builder) const { 377 // NetBSD defines; list based off of gcc output 378 Builder.defineMacro("__NetBSD__"); 379 Builder.defineMacro("__unix__"); 380 Builder.defineMacro("__ELF__"); 381 if (Opts.POSIXThreads) 382 Builder.defineMacro("_POSIX_THREADS"); 383 } 384 public: 385 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 386 this->UserLabelPrefix = ""; 387 } 388 }; 389 390 // OpenBSD Target 391 template<typename Target> 392 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 393 protected: 394 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 395 MacroBuilder &Builder) const { 396 // OpenBSD defines; list based off of gcc output 397 398 Builder.defineMacro("__OpenBSD__"); 399 DefineStd(Builder, "unix", Opts); 400 Builder.defineMacro("__ELF__"); 401 if (Opts.POSIXThreads) 402 Builder.defineMacro("_REENTRANT"); 403 } 404 public: 405 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 406 this->UserLabelPrefix = ""; 407 this->TLSSupported = false; 408 409 switch (Triple.getArch()) { 410 default: 411 case llvm::Triple::x86: 412 case llvm::Triple::x86_64: 413 case llvm::Triple::arm: 414 case llvm::Triple::sparc: 415 this->MCountName = "__mcount"; 416 break; 417 case llvm::Triple::mips64: 418 case llvm::Triple::mips64el: 419 case llvm::Triple::ppc: 420 case llvm::Triple::sparcv9: 421 this->MCountName = "_mcount"; 422 break; 423 } 424 } 425 }; 426 427 // Bitrig Target 428 template<typename Target> 429 class BitrigTargetInfo : public OSTargetInfo<Target> { 430 protected: 431 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 432 MacroBuilder &Builder) const { 433 // Bitrig defines; list based off of gcc output 434 435 Builder.defineMacro("__Bitrig__"); 436 DefineStd(Builder, "unix", Opts); 437 Builder.defineMacro("__ELF__"); 438 if (Opts.POSIXThreads) 439 Builder.defineMacro("_REENTRANT"); 440 } 441 public: 442 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 443 this->UserLabelPrefix = ""; 444 this->TLSSupported = false; 445 this->MCountName = "__mcount"; 446 } 447 }; 448 449 // PSP Target 450 template<typename Target> 451 class PSPTargetInfo : public OSTargetInfo<Target> { 452 protected: 453 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 454 MacroBuilder &Builder) const { 455 // PSP defines; list based on the output of the pspdev gcc toolchain. 456 Builder.defineMacro("PSP"); 457 Builder.defineMacro("_PSP"); 458 Builder.defineMacro("__psp__"); 459 Builder.defineMacro("__ELF__"); 460 } 461 public: 462 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 463 this->UserLabelPrefix = ""; 464 } 465 }; 466 467 // PS3 PPU Target 468 template<typename Target> 469 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 470 protected: 471 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 472 MacroBuilder &Builder) const { 473 // PS3 PPU defines. 474 Builder.defineMacro("__PPC__"); 475 Builder.defineMacro("__PPU__"); 476 Builder.defineMacro("__CELLOS_LV2__"); 477 Builder.defineMacro("__ELF__"); 478 Builder.defineMacro("__LP32__"); 479 Builder.defineMacro("_ARCH_PPC64"); 480 Builder.defineMacro("__powerpc64__"); 481 } 482 public: 483 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 484 this->UserLabelPrefix = ""; 485 this->LongWidth = this->LongAlign = 32; 486 this->PointerWidth = this->PointerAlign = 32; 487 this->IntMaxType = TargetInfo::SignedLongLong; 488 this->UIntMaxType = TargetInfo::UnsignedLongLong; 489 this->Int64Type = TargetInfo::SignedLongLong; 490 this->SizeType = TargetInfo::UnsignedInt; 491 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 492 } 493 }; 494 495 // AuroraUX target 496 template<typename Target> 497 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 498 protected: 499 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 500 MacroBuilder &Builder) const { 501 DefineStd(Builder, "sun", Opts); 502 DefineStd(Builder, "unix", Opts); 503 Builder.defineMacro("__ELF__"); 504 Builder.defineMacro("__svr4__"); 505 Builder.defineMacro("__SVR4"); 506 } 507 public: 508 AuroraUXTargetInfo(const llvm::Triple &Triple) 509 : OSTargetInfo<Target>(Triple) { 510 this->UserLabelPrefix = ""; 511 this->WCharType = this->SignedLong; 512 // FIXME: WIntType should be SignedLong 513 } 514 }; 515 516 // Solaris target 517 template<typename Target> 518 class SolarisTargetInfo : public OSTargetInfo<Target> { 519 protected: 520 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 521 MacroBuilder &Builder) const { 522 DefineStd(Builder, "sun", Opts); 523 DefineStd(Builder, "unix", Opts); 524 Builder.defineMacro("__ELF__"); 525 Builder.defineMacro("__svr4__"); 526 Builder.defineMacro("__SVR4"); 527 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 528 // newer, but to 500 for everything else. feature_test.h has a check to 529 // ensure that you are not using C99 with an old version of X/Open or C89 530 // with a new version. 531 if (Opts.C99 || Opts.C11) 532 Builder.defineMacro("_XOPEN_SOURCE", "600"); 533 else 534 Builder.defineMacro("_XOPEN_SOURCE", "500"); 535 if (Opts.CPlusPlus) 536 Builder.defineMacro("__C99FEATURES__"); 537 Builder.defineMacro("_LARGEFILE_SOURCE"); 538 Builder.defineMacro("_LARGEFILE64_SOURCE"); 539 Builder.defineMacro("__EXTENSIONS__"); 540 Builder.defineMacro("_REENTRANT"); 541 } 542 public: 543 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 544 this->UserLabelPrefix = ""; 545 this->WCharType = this->SignedInt; 546 // FIXME: WIntType should be SignedLong 547 } 548 }; 549 550 // Windows target 551 template<typename Target> 552 class WindowsTargetInfo : public OSTargetInfo<Target> { 553 protected: 554 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 555 MacroBuilder &Builder) const { 556 Builder.defineMacro("_WIN32"); 557 } 558 void getVisualStudioDefines(const LangOptions &Opts, 559 MacroBuilder &Builder) const { 560 if (Opts.CPlusPlus) { 561 if (Opts.RTTI) 562 Builder.defineMacro("_CPPRTTI"); 563 564 if (Opts.Exceptions) 565 Builder.defineMacro("_CPPUNWIND"); 566 } 567 568 if (!Opts.CharIsSigned) 569 Builder.defineMacro("_CHAR_UNSIGNED"); 570 571 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 572 // but it works for now. 573 if (Opts.POSIXThreads) 574 Builder.defineMacro("_MT"); 575 576 if (Opts.MSCVersion != 0) 577 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 578 579 if (Opts.MicrosoftExt) { 580 Builder.defineMacro("_MSC_EXTENSIONS"); 581 582 if (Opts.CPlusPlus11) { 583 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 584 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 585 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 586 } 587 } 588 589 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 590 } 591 592 public: 593 WindowsTargetInfo(const llvm::Triple &Triple) 594 : OSTargetInfo<Target>(Triple) {} 595 }; 596 597 template <typename Target> 598 class NaClTargetInfo : public OSTargetInfo<Target> { 599 protected: 600 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 601 MacroBuilder &Builder) const { 602 if (Opts.POSIXThreads) 603 Builder.defineMacro("_REENTRANT"); 604 if (Opts.CPlusPlus) 605 Builder.defineMacro("_GNU_SOURCE"); 606 607 DefineStd(Builder, "unix", Opts); 608 Builder.defineMacro("__ELF__"); 609 Builder.defineMacro("__native_client__"); 610 } 611 612 public: 613 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 614 this->UserLabelPrefix = ""; 615 this->LongAlign = 32; 616 this->LongWidth = 32; 617 this->PointerAlign = 32; 618 this->PointerWidth = 32; 619 this->IntMaxType = TargetInfo::SignedLongLong; 620 this->UIntMaxType = TargetInfo::UnsignedLongLong; 621 this->Int64Type = TargetInfo::SignedLongLong; 622 this->DoubleAlign = 64; 623 this->LongDoubleWidth = 64; 624 this->LongDoubleAlign = 64; 625 this->LongLongWidth = 64; 626 this->LongLongAlign = 64; 627 this->SizeType = TargetInfo::UnsignedInt; 628 this->PtrDiffType = TargetInfo::SignedInt; 629 this->IntPtrType = TargetInfo::SignedInt; 630 // RegParmMax is inherited from the underlying architecture 631 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 632 if (Triple.getArch() == llvm::Triple::arm) { 633 this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S128"; 634 } else if (Triple.getArch() == llvm::Triple::x86) { 635 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 636 } else if (Triple.getArch() == llvm::Triple::x86_64) { 637 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 638 } else if (Triple.getArch() == llvm::Triple::mipsel) { 639 // Handled on mips' setDescriptionString. 640 } else { 641 assert(Triple.getArch() == llvm::Triple::le32); 642 this->DescriptionString = "e-p:32:32-i64:64"; 643 } 644 } 645 virtual typename Target::CallingConvCheckResult checkCallingConvention( 646 CallingConv CC) const { 647 return CC == CC_PnaclCall ? Target::CCCR_OK : 648 Target::checkCallingConvention(CC); 649 } 650 }; 651 } // end anonymous namespace. 652 653 //===----------------------------------------------------------------------===// 654 // Specific target implementations. 655 //===----------------------------------------------------------------------===// 656 657 namespace { 658 // PPC abstract base class 659 class PPCTargetInfo : public TargetInfo { 660 static const Builtin::Info BuiltinInfo[]; 661 static const char * const GCCRegNames[]; 662 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 663 std::string CPU; 664 665 // Target cpu features. 666 bool HasVSX; 667 668 public: 669 PPCTargetInfo(const llvm::Triple &Triple) 670 : TargetInfo(Triple), HasVSX(false) { 671 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 672 LongDoubleWidth = LongDoubleAlign = 128; 673 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 674 } 675 676 /// \brief Flags for architecture specific defines. 677 typedef enum { 678 ArchDefineNone = 0, 679 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 680 ArchDefinePpcgr = 1 << 1, 681 ArchDefinePpcsq = 1 << 2, 682 ArchDefine440 = 1 << 3, 683 ArchDefine603 = 1 << 4, 684 ArchDefine604 = 1 << 5, 685 ArchDefinePwr4 = 1 << 6, 686 ArchDefinePwr5 = 1 << 7, 687 ArchDefinePwr5x = 1 << 8, 688 ArchDefinePwr6 = 1 << 9, 689 ArchDefinePwr6x = 1 << 10, 690 ArchDefinePwr7 = 1 << 11, 691 ArchDefineA2 = 1 << 12, 692 ArchDefineA2q = 1 << 13 693 } ArchDefineTypes; 694 695 // Note: GCC recognizes the following additional cpus: 696 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 697 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 698 // titan, rs64. 699 virtual bool setCPU(const std::string &Name) { 700 bool CPUKnown = llvm::StringSwitch<bool>(Name) 701 .Case("generic", true) 702 .Case("440", true) 703 .Case("450", true) 704 .Case("601", true) 705 .Case("602", true) 706 .Case("603", true) 707 .Case("603e", true) 708 .Case("603ev", true) 709 .Case("604", true) 710 .Case("604e", true) 711 .Case("620", true) 712 .Case("630", true) 713 .Case("g3", true) 714 .Case("7400", true) 715 .Case("g4", true) 716 .Case("7450", true) 717 .Case("g4+", true) 718 .Case("750", true) 719 .Case("970", true) 720 .Case("g5", true) 721 .Case("a2", true) 722 .Case("a2q", true) 723 .Case("e500mc", true) 724 .Case("e5500", true) 725 .Case("power3", true) 726 .Case("pwr3", true) 727 .Case("power4", true) 728 .Case("pwr4", true) 729 .Case("power5", true) 730 .Case("pwr5", true) 731 .Case("power5x", true) 732 .Case("pwr5x", true) 733 .Case("power6", true) 734 .Case("pwr6", true) 735 .Case("power6x", true) 736 .Case("pwr6x", true) 737 .Case("power7", true) 738 .Case("pwr7", true) 739 .Case("powerpc", true) 740 .Case("ppc", true) 741 .Case("powerpc64", true) 742 .Case("ppc64", true) 743 .Case("powerpc64le", true) 744 .Case("ppc64le", true) 745 .Default(false); 746 747 if (CPUKnown) 748 CPU = Name; 749 750 return CPUKnown; 751 } 752 753 virtual void getTargetBuiltins(const Builtin::Info *&Records, 754 unsigned &NumRecords) const { 755 Records = BuiltinInfo; 756 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 757 } 758 759 virtual bool isCLZForZeroUndef() const { return false; } 760 761 virtual void getTargetDefines(const LangOptions &Opts, 762 MacroBuilder &Builder) const; 763 764 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 765 766 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 767 DiagnosticsEngine &Diags); 768 virtual bool hasFeature(StringRef Feature) const; 769 770 virtual void getGCCRegNames(const char * const *&Names, 771 unsigned &NumNames) const; 772 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 773 unsigned &NumAliases) const; 774 virtual bool validateAsmConstraint(const char *&Name, 775 TargetInfo::ConstraintInfo &Info) const { 776 switch (*Name) { 777 default: return false; 778 case 'O': // Zero 779 break; 780 case 'b': // Base register 781 case 'f': // Floating point register 782 Info.setAllowsRegister(); 783 break; 784 // FIXME: The following are added to allow parsing. 785 // I just took a guess at what the actions should be. 786 // Also, is more specific checking needed? I.e. specific registers? 787 case 'd': // Floating point register (containing 64-bit value) 788 case 'v': // Altivec vector register 789 Info.setAllowsRegister(); 790 break; 791 case 'w': 792 switch (Name[1]) { 793 case 'd':// VSX vector register to hold vector double data 794 case 'f':// VSX vector register to hold vector float data 795 case 's':// VSX vector register to hold scalar float data 796 case 'a':// Any VSX register 797 break; 798 default: 799 return false; 800 } 801 Info.setAllowsRegister(); 802 Name++; // Skip over 'w'. 803 break; 804 case 'h': // `MQ', `CTR', or `LINK' register 805 case 'q': // `MQ' register 806 case 'c': // `CTR' register 807 case 'l': // `LINK' register 808 case 'x': // `CR' register (condition register) number 0 809 case 'y': // `CR' register (condition register) 810 case 'z': // `XER[CA]' carry bit (part of the XER register) 811 Info.setAllowsRegister(); 812 break; 813 case 'I': // Signed 16-bit constant 814 case 'J': // Unsigned 16-bit constant shifted left 16 bits 815 // (use `L' instead for SImode constants) 816 case 'K': // Unsigned 16-bit constant 817 case 'L': // Signed 16-bit constant shifted left 16 bits 818 case 'M': // Constant larger than 31 819 case 'N': // Exact power of 2 820 case 'P': // Constant whose negation is a signed 16-bit constant 821 case 'G': // Floating point constant that can be loaded into a 822 // register with one instruction per word 823 case 'H': // Integer/Floating point constant that can be loaded 824 // into a register using three instructions 825 break; 826 case 'm': // Memory operand. Note that on PowerPC targets, m can 827 // include addresses that update the base register. It 828 // is therefore only safe to use `m' in an asm statement 829 // if that asm statement accesses the operand exactly once. 830 // The asm statement must also use `%U<opno>' as a 831 // placeholder for the "update" flag in the corresponding 832 // load or store instruction. For example: 833 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 834 // is correct but: 835 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 836 // is not. Use es rather than m if you don't want the base 837 // register to be updated. 838 case 'e': 839 if (Name[1] != 's') 840 return false; 841 // es: A "stable" memory operand; that is, one which does not 842 // include any automodification of the base register. Unlike 843 // `m', this constraint can be used in asm statements that 844 // might access the operand several times, or that might not 845 // access it at all. 846 Info.setAllowsMemory(); 847 Name++; // Skip over 'e'. 848 break; 849 case 'Q': // Memory operand that is an offset from a register (it is 850 // usually better to use `m' or `es' in asm statements) 851 case 'Z': // Memory operand that is an indexed or indirect from a 852 // register (it is usually better to use `m' or `es' in 853 // asm statements) 854 Info.setAllowsMemory(); 855 Info.setAllowsRegister(); 856 break; 857 case 'R': // AIX TOC entry 858 case 'a': // Address operand that is an indexed or indirect from a 859 // register (`p' is preferable for asm statements) 860 case 'S': // Constant suitable as a 64-bit mask operand 861 case 'T': // Constant suitable as a 32-bit mask operand 862 case 'U': // System V Release 4 small data area reference 863 case 't': // AND masks that can be performed by two rldic{l, r} 864 // instructions 865 case 'W': // Vector constant that does not require memory 866 case 'j': // Vector constant that is all zeros. 867 break; 868 // End FIXME. 869 } 870 return true; 871 } 872 virtual const char *getClobbers() const { 873 return ""; 874 } 875 int getEHDataRegisterNumber(unsigned RegNo) const { 876 if (RegNo == 0) return 3; 877 if (RegNo == 1) return 4; 878 return -1; 879 } 880 }; 881 882 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 883 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 884 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 885 ALL_LANGUAGES }, 886 #include "clang/Basic/BuiltinsPPC.def" 887 }; 888 889 /// handleTargetFeatures - Perform initialization based on the user 890 /// configured set of features. 891 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 892 DiagnosticsEngine &Diags) { 893 // Remember the maximum enabled sselevel. 894 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 895 // Ignore disabled features. 896 if (Features[i][0] == '-') 897 continue; 898 899 StringRef Feature = StringRef(Features[i]).substr(1); 900 901 if (Feature == "vsx") { 902 HasVSX = true; 903 continue; 904 } 905 906 // TODO: Finish this list and add an assert that we've handled them 907 // all. 908 } 909 910 return true; 911 } 912 913 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 914 /// #defines that are not tied to a specific subtarget. 915 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 916 MacroBuilder &Builder) const { 917 // Target identification. 918 Builder.defineMacro("__ppc__"); 919 Builder.defineMacro("__PPC__"); 920 Builder.defineMacro("_ARCH_PPC"); 921 Builder.defineMacro("__powerpc__"); 922 Builder.defineMacro("__POWERPC__"); 923 if (PointerWidth == 64) { 924 Builder.defineMacro("_ARCH_PPC64"); 925 Builder.defineMacro("__powerpc64__"); 926 Builder.defineMacro("__ppc64__"); 927 Builder.defineMacro("__PPC64__"); 928 } 929 930 // Target properties. 931 if (getTriple().getArch() == llvm::Triple::ppc64le) { 932 Builder.defineMacro("_LITTLE_ENDIAN"); 933 Builder.defineMacro("__LITTLE_ENDIAN__"); 934 } else { 935 if (getTriple().getOS() != llvm::Triple::NetBSD && 936 getTriple().getOS() != llvm::Triple::OpenBSD) 937 Builder.defineMacro("_BIG_ENDIAN"); 938 Builder.defineMacro("__BIG_ENDIAN__"); 939 } 940 941 // Subtarget options. 942 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 943 Builder.defineMacro("__REGISTER_PREFIX__", ""); 944 945 // FIXME: Should be controlled by command line option. 946 if (LongDoubleWidth == 128) 947 Builder.defineMacro("__LONG_DOUBLE_128__"); 948 949 if (Opts.AltiVec) { 950 Builder.defineMacro("__VEC__", "10206"); 951 Builder.defineMacro("__ALTIVEC__"); 952 } 953 954 // CPU identification. 955 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 956 .Case("440", ArchDefineName) 957 .Case("450", ArchDefineName | ArchDefine440) 958 .Case("601", ArchDefineName) 959 .Case("602", ArchDefineName | ArchDefinePpcgr) 960 .Case("603", ArchDefineName | ArchDefinePpcgr) 961 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 962 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 963 .Case("604", ArchDefineName | ArchDefinePpcgr) 964 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 965 .Case("620", ArchDefineName | ArchDefinePpcgr) 966 .Case("630", ArchDefineName | ArchDefinePpcgr) 967 .Case("7400", ArchDefineName | ArchDefinePpcgr) 968 .Case("7450", ArchDefineName | ArchDefinePpcgr) 969 .Case("750", ArchDefineName | ArchDefinePpcgr) 970 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 971 | ArchDefinePpcsq) 972 .Case("a2", ArchDefineA2) 973 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 974 .Case("pwr3", ArchDefinePpcgr) 975 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 976 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 977 | ArchDefinePpcsq) 978 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 979 | ArchDefinePpcgr | ArchDefinePpcsq) 980 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 981 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 982 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 983 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 984 | ArchDefinePpcsq) 985 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 986 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 987 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 988 .Case("power3", ArchDefinePpcgr) 989 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 990 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 991 | ArchDefinePpcsq) 992 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 993 | ArchDefinePpcgr | ArchDefinePpcsq) 994 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 995 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 996 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 997 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 998 | ArchDefinePpcsq) 999 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1000 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1001 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 1002 .Default(ArchDefineNone); 1003 1004 if (defs & ArchDefineName) 1005 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1006 if (defs & ArchDefinePpcgr) 1007 Builder.defineMacro("_ARCH_PPCGR"); 1008 if (defs & ArchDefinePpcsq) 1009 Builder.defineMacro("_ARCH_PPCSQ"); 1010 if (defs & ArchDefine440) 1011 Builder.defineMacro("_ARCH_440"); 1012 if (defs & ArchDefine603) 1013 Builder.defineMacro("_ARCH_603"); 1014 if (defs & ArchDefine604) 1015 Builder.defineMacro("_ARCH_604"); 1016 if (defs & ArchDefinePwr4) 1017 Builder.defineMacro("_ARCH_PWR4"); 1018 if (defs & ArchDefinePwr5) 1019 Builder.defineMacro("_ARCH_PWR5"); 1020 if (defs & ArchDefinePwr5x) 1021 Builder.defineMacro("_ARCH_PWR5X"); 1022 if (defs & ArchDefinePwr6) 1023 Builder.defineMacro("_ARCH_PWR6"); 1024 if (defs & ArchDefinePwr6x) 1025 Builder.defineMacro("_ARCH_PWR6X"); 1026 if (defs & ArchDefinePwr7) 1027 Builder.defineMacro("_ARCH_PWR7"); 1028 if (defs & ArchDefineA2) 1029 Builder.defineMacro("_ARCH_A2"); 1030 if (defs & ArchDefineA2q) { 1031 Builder.defineMacro("_ARCH_A2Q"); 1032 Builder.defineMacro("_ARCH_QP"); 1033 } 1034 1035 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1036 Builder.defineMacro("__bg__"); 1037 Builder.defineMacro("__THW_BLUEGENE__"); 1038 Builder.defineMacro("__bgq__"); 1039 Builder.defineMacro("__TOS_BGQ__"); 1040 } 1041 1042 if (HasVSX) 1043 Builder.defineMacro("__VSX__"); 1044 1045 // FIXME: The following are not yet generated here by Clang, but are 1046 // generated by GCC: 1047 // 1048 // _SOFT_FLOAT_ 1049 // __RECIP_PRECISION__ 1050 // __APPLE_ALTIVEC__ 1051 // __RECIP__ 1052 // __RECIPF__ 1053 // __RSQRTE__ 1054 // __RSQRTEF__ 1055 // _SOFT_DOUBLE_ 1056 // __NO_LWSYNC__ 1057 // __HAVE_BSWAP__ 1058 // __LONGDOUBLE128 1059 // __CMODEL_MEDIUM__ 1060 // __CMODEL_LARGE__ 1061 // _CALL_SYSV 1062 // _CALL_DARWIN 1063 // __NO_FPRS__ 1064 } 1065 1066 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1067 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1068 .Case("7400", true) 1069 .Case("g4", true) 1070 .Case("7450", true) 1071 .Case("g4+", true) 1072 .Case("970", true) 1073 .Case("g5", true) 1074 .Case("pwr6", true) 1075 .Case("pwr7", true) 1076 .Case("ppc64", true) 1077 .Case("ppc64le", true) 1078 .Default(false); 1079 1080 Features["qpx"] = (CPU == "a2q"); 1081 } 1082 1083 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1084 return Feature == "powerpc"; 1085 } 1086 1087 1088 const char * const PPCTargetInfo::GCCRegNames[] = { 1089 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1090 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1091 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1092 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1093 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1094 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1095 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1096 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1097 "mq", "lr", "ctr", "ap", 1098 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1099 "xer", 1100 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1101 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1102 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1103 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1104 "vrsave", "vscr", 1105 "spe_acc", "spefscr", 1106 "sfp" 1107 }; 1108 1109 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1110 unsigned &NumNames) const { 1111 Names = GCCRegNames; 1112 NumNames = llvm::array_lengthof(GCCRegNames); 1113 } 1114 1115 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1116 // While some of these aliases do map to different registers 1117 // they still share the same register name. 1118 { { "0" }, "r0" }, 1119 { { "1"}, "r1" }, 1120 { { "2" }, "r2" }, 1121 { { "3" }, "r3" }, 1122 { { "4" }, "r4" }, 1123 { { "5" }, "r5" }, 1124 { { "6" }, "r6" }, 1125 { { "7" }, "r7" }, 1126 { { "8" }, "r8" }, 1127 { { "9" }, "r9" }, 1128 { { "10" }, "r10" }, 1129 { { "11" }, "r11" }, 1130 { { "12" }, "r12" }, 1131 { { "13" }, "r13" }, 1132 { { "14" }, "r14" }, 1133 { { "15" }, "r15" }, 1134 { { "16" }, "r16" }, 1135 { { "17" }, "r17" }, 1136 { { "18" }, "r18" }, 1137 { { "19" }, "r19" }, 1138 { { "20" }, "r20" }, 1139 { { "21" }, "r21" }, 1140 { { "22" }, "r22" }, 1141 { { "23" }, "r23" }, 1142 { { "24" }, "r24" }, 1143 { { "25" }, "r25" }, 1144 { { "26" }, "r26" }, 1145 { { "27" }, "r27" }, 1146 { { "28" }, "r28" }, 1147 { { "29" }, "r29" }, 1148 { { "30" }, "r30" }, 1149 { { "31" }, "r31" }, 1150 { { "fr0" }, "f0" }, 1151 { { "fr1" }, "f1" }, 1152 { { "fr2" }, "f2" }, 1153 { { "fr3" }, "f3" }, 1154 { { "fr4" }, "f4" }, 1155 { { "fr5" }, "f5" }, 1156 { { "fr6" }, "f6" }, 1157 { { "fr7" }, "f7" }, 1158 { { "fr8" }, "f8" }, 1159 { { "fr9" }, "f9" }, 1160 { { "fr10" }, "f10" }, 1161 { { "fr11" }, "f11" }, 1162 { { "fr12" }, "f12" }, 1163 { { "fr13" }, "f13" }, 1164 { { "fr14" }, "f14" }, 1165 { { "fr15" }, "f15" }, 1166 { { "fr16" }, "f16" }, 1167 { { "fr17" }, "f17" }, 1168 { { "fr18" }, "f18" }, 1169 { { "fr19" }, "f19" }, 1170 { { "fr20" }, "f20" }, 1171 { { "fr21" }, "f21" }, 1172 { { "fr22" }, "f22" }, 1173 { { "fr23" }, "f23" }, 1174 { { "fr24" }, "f24" }, 1175 { { "fr25" }, "f25" }, 1176 { { "fr26" }, "f26" }, 1177 { { "fr27" }, "f27" }, 1178 { { "fr28" }, "f28" }, 1179 { { "fr29" }, "f29" }, 1180 { { "fr30" }, "f30" }, 1181 { { "fr31" }, "f31" }, 1182 { { "cc" }, "cr0" }, 1183 }; 1184 1185 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1186 unsigned &NumAliases) const { 1187 Aliases = GCCRegAliases; 1188 NumAliases = llvm::array_lengthof(GCCRegAliases); 1189 } 1190 } // end anonymous namespace. 1191 1192 namespace { 1193 class PPC32TargetInfo : public PPCTargetInfo { 1194 public: 1195 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1196 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1197 1198 switch (getTriple().getOS()) { 1199 case llvm::Triple::Linux: 1200 case llvm::Triple::FreeBSD: 1201 case llvm::Triple::NetBSD: 1202 SizeType = UnsignedInt; 1203 PtrDiffType = SignedInt; 1204 IntPtrType = SignedInt; 1205 break; 1206 default: 1207 break; 1208 } 1209 1210 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1211 LongDoubleWidth = LongDoubleAlign = 64; 1212 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1213 } 1214 1215 // PPC32 supports atomics up to 4 bytes. 1216 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1217 } 1218 1219 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1220 // This is the ELF definition, and is overridden by the Darwin sub-target 1221 return TargetInfo::PowerABIBuiltinVaList; 1222 } 1223 }; 1224 } // end anonymous namespace. 1225 1226 // Note: ABI differences may eventually require us to have a separate 1227 // TargetInfo for little endian. 1228 namespace { 1229 class PPC64TargetInfo : public PPCTargetInfo { 1230 public: 1231 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1232 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1233 IntMaxType = SignedLong; 1234 UIntMaxType = UnsignedLong; 1235 Int64Type = SignedLong; 1236 1237 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1238 LongDoubleWidth = LongDoubleAlign = 64; 1239 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1240 DescriptionString = "E-m:e-i64:64-n32:64"; 1241 } else 1242 DescriptionString = "E-m:e-i64:64-n32:64"; 1243 1244 // PPC64 supports atomics up to 8 bytes. 1245 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1246 } 1247 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1248 return TargetInfo::CharPtrBuiltinVaList; 1249 } 1250 }; 1251 } // end anonymous namespace. 1252 1253 1254 namespace { 1255 class DarwinPPC32TargetInfo : 1256 public DarwinTargetInfo<PPC32TargetInfo> { 1257 public: 1258 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1259 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1260 HasAlignMac68kSupport = true; 1261 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1262 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1263 LongLongAlign = 32; 1264 SuitableAlign = 128; 1265 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1266 } 1267 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1268 return TargetInfo::CharPtrBuiltinVaList; 1269 } 1270 }; 1271 1272 class DarwinPPC64TargetInfo : 1273 public DarwinTargetInfo<PPC64TargetInfo> { 1274 public: 1275 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1276 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1277 HasAlignMac68kSupport = true; 1278 SuitableAlign = 128; 1279 DescriptionString = "E-m:o-i64:64-n32:64"; 1280 } 1281 }; 1282 } // end anonymous namespace. 1283 1284 namespace { 1285 static const unsigned NVPTXAddrSpaceMap[] = { 1286 1, // opencl_global 1287 3, // opencl_local 1288 4, // opencl_constant 1289 1, // cuda_device 1290 4, // cuda_constant 1291 3, // cuda_shared 1292 }; 1293 class NVPTXTargetInfo : public TargetInfo { 1294 static const char * const GCCRegNames[]; 1295 static const Builtin::Info BuiltinInfo[]; 1296 public: 1297 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1298 BigEndian = false; 1299 TLSSupported = false; 1300 LongWidth = LongAlign = 64; 1301 AddrSpaceMap = &NVPTXAddrSpaceMap; 1302 UseAddrSpaceMapMangling = true; 1303 // Define available target features 1304 // These must be defined in sorted order! 1305 NoAsmVariants = true; 1306 } 1307 virtual void getTargetDefines(const LangOptions &Opts, 1308 MacroBuilder &Builder) const { 1309 Builder.defineMacro("__PTX__"); 1310 Builder.defineMacro("__NVPTX__"); 1311 } 1312 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1313 unsigned &NumRecords) const { 1314 Records = BuiltinInfo; 1315 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1316 } 1317 virtual bool hasFeature(StringRef Feature) const { 1318 return Feature == "ptx" || Feature == "nvptx"; 1319 } 1320 1321 virtual void getGCCRegNames(const char * const *&Names, 1322 unsigned &NumNames) const; 1323 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1324 unsigned &NumAliases) const { 1325 // No aliases. 1326 Aliases = 0; 1327 NumAliases = 0; 1328 } 1329 virtual bool validateAsmConstraint(const char *&Name, 1330 TargetInfo::ConstraintInfo &Info) const { 1331 switch (*Name) { 1332 default: return false; 1333 case 'c': 1334 case 'h': 1335 case 'r': 1336 case 'l': 1337 case 'f': 1338 case 'd': 1339 Info.setAllowsRegister(); 1340 return true; 1341 } 1342 } 1343 virtual const char *getClobbers() const { 1344 // FIXME: Is this really right? 1345 return ""; 1346 } 1347 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1348 // FIXME: implement 1349 return TargetInfo::CharPtrBuiltinVaList; 1350 } 1351 virtual bool setCPU(const std::string &Name) { 1352 bool Valid = llvm::StringSwitch<bool>(Name) 1353 .Case("sm_20", true) 1354 .Case("sm_21", true) 1355 .Case("sm_30", true) 1356 .Case("sm_35", true) 1357 .Default(false); 1358 1359 return Valid; 1360 } 1361 }; 1362 1363 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1364 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1365 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1366 ALL_LANGUAGES }, 1367 #include "clang/Basic/BuiltinsNVPTX.def" 1368 }; 1369 1370 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1371 "r0" 1372 }; 1373 1374 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1375 unsigned &NumNames) const { 1376 Names = GCCRegNames; 1377 NumNames = llvm::array_lengthof(GCCRegNames); 1378 } 1379 1380 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1381 public: 1382 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1383 PointerWidth = PointerAlign = 32; 1384 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1385 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1386 } 1387 }; 1388 1389 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1390 public: 1391 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1392 PointerWidth = PointerAlign = 64; 1393 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1394 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1395 } 1396 }; 1397 } 1398 1399 namespace { 1400 1401 static const unsigned R600AddrSpaceMap[] = { 1402 1, // opencl_global 1403 3, // opencl_local 1404 2, // opencl_constant 1405 1, // cuda_device 1406 2, // cuda_constant 1407 3 // cuda_shared 1408 }; 1409 1410 static const char *DescriptionStringR600 = 1411 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1412 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1413 1414 static const char *DescriptionStringR600DoubleOps = 1415 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1416 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1417 1418 static const char *DescriptionStringSI = 1419 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64" 1420 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1421 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1422 1423 class R600TargetInfo : public TargetInfo { 1424 /// \brief The GPU profiles supported by the R600 target. 1425 enum GPUKind { 1426 GK_NONE, 1427 GK_R600, 1428 GK_R600_DOUBLE_OPS, 1429 GK_R700, 1430 GK_R700_DOUBLE_OPS, 1431 GK_EVERGREEN, 1432 GK_EVERGREEN_DOUBLE_OPS, 1433 GK_NORTHERN_ISLANDS, 1434 GK_CAYMAN, 1435 GK_SOUTHERN_ISLANDS, 1436 GK_SEA_ISLANDS 1437 } GPU; 1438 1439 public: 1440 R600TargetInfo(const llvm::Triple &Triple) 1441 : TargetInfo(Triple), GPU(GK_R600) { 1442 DescriptionString = DescriptionStringR600; 1443 AddrSpaceMap = &R600AddrSpaceMap; 1444 UseAddrSpaceMapMangling = true; 1445 } 1446 1447 virtual const char * getClobbers() const { 1448 return ""; 1449 } 1450 1451 virtual void getGCCRegNames(const char * const *&Names, 1452 unsigned &numNames) const { 1453 Names = NULL; 1454 numNames = 0; 1455 } 1456 1457 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1458 unsigned &NumAliases) const { 1459 Aliases = NULL; 1460 NumAliases = 0; 1461 } 1462 1463 virtual bool validateAsmConstraint(const char *&Name, 1464 TargetInfo::ConstraintInfo &info) const { 1465 return true; 1466 } 1467 1468 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1469 unsigned &NumRecords) const { 1470 Records = NULL; 1471 NumRecords = 0; 1472 } 1473 1474 1475 virtual void getTargetDefines(const LangOptions &Opts, 1476 MacroBuilder &Builder) const { 1477 Builder.defineMacro("__R600__"); 1478 } 1479 1480 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1481 return TargetInfo::CharPtrBuiltinVaList; 1482 } 1483 1484 virtual bool setCPU(const std::string &Name) { 1485 GPU = llvm::StringSwitch<GPUKind>(Name) 1486 .Case("r600" , GK_R600) 1487 .Case("rv610", GK_R600) 1488 .Case("rv620", GK_R600) 1489 .Case("rv630", GK_R600) 1490 .Case("rv635", GK_R600) 1491 .Case("rs780", GK_R600) 1492 .Case("rs880", GK_R600) 1493 .Case("rv670", GK_R600_DOUBLE_OPS) 1494 .Case("rv710", GK_R700) 1495 .Case("rv730", GK_R700) 1496 .Case("rv740", GK_R700_DOUBLE_OPS) 1497 .Case("rv770", GK_R700_DOUBLE_OPS) 1498 .Case("palm", GK_EVERGREEN) 1499 .Case("cedar", GK_EVERGREEN) 1500 .Case("sumo", GK_EVERGREEN) 1501 .Case("sumo2", GK_EVERGREEN) 1502 .Case("redwood", GK_EVERGREEN) 1503 .Case("juniper", GK_EVERGREEN) 1504 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1505 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1506 .Case("barts", GK_NORTHERN_ISLANDS) 1507 .Case("turks", GK_NORTHERN_ISLANDS) 1508 .Case("caicos", GK_NORTHERN_ISLANDS) 1509 .Case("cayman", GK_CAYMAN) 1510 .Case("aruba", GK_CAYMAN) 1511 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1512 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1513 .Case("verde", GK_SOUTHERN_ISLANDS) 1514 .Case("oland", GK_SOUTHERN_ISLANDS) 1515 .Case("bonaire", GK_SEA_ISLANDS) 1516 .Case("kabini", GK_SEA_ISLANDS) 1517 .Case("kaveri", GK_SEA_ISLANDS) 1518 .Case("hawaii", GK_SEA_ISLANDS) 1519 .Default(GK_NONE); 1520 1521 if (GPU == GK_NONE) { 1522 return false; 1523 } 1524 1525 // Set the correct data layout 1526 switch (GPU) { 1527 case GK_NONE: 1528 case GK_R600: 1529 case GK_R700: 1530 case GK_EVERGREEN: 1531 case GK_NORTHERN_ISLANDS: 1532 DescriptionString = DescriptionStringR600; 1533 break; 1534 case GK_R600_DOUBLE_OPS: 1535 case GK_R700_DOUBLE_OPS: 1536 case GK_EVERGREEN_DOUBLE_OPS: 1537 case GK_CAYMAN: 1538 DescriptionString = DescriptionStringR600DoubleOps; 1539 break; 1540 case GK_SOUTHERN_ISLANDS: 1541 case GK_SEA_ISLANDS: 1542 DescriptionString = DescriptionStringSI; 1543 break; 1544 } 1545 1546 return true; 1547 } 1548 }; 1549 1550 } // end anonymous namespace 1551 1552 namespace { 1553 // Namespace for x86 abstract base class 1554 const Builtin::Info BuiltinInfo[] = { 1555 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1556 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1557 ALL_LANGUAGES }, 1558 #include "clang/Basic/BuiltinsX86.def" 1559 }; 1560 1561 static const char* const GCCRegNames[] = { 1562 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1563 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1564 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1565 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1566 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1567 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1568 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1569 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1570 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1571 }; 1572 1573 const TargetInfo::AddlRegName AddlRegNames[] = { 1574 { { "al", "ah", "eax", "rax" }, 0 }, 1575 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1576 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1577 { { "dl", "dh", "edx", "rdx" }, 1 }, 1578 { { "esi", "rsi" }, 4 }, 1579 { { "edi", "rdi" }, 5 }, 1580 { { "esp", "rsp" }, 7 }, 1581 { { "ebp", "rbp" }, 6 }, 1582 }; 1583 1584 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1585 // most of the implementation can be shared. 1586 class X86TargetInfo : public TargetInfo { 1587 enum X86SSEEnum { 1588 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1589 } SSELevel; 1590 enum MMX3DNowEnum { 1591 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1592 } MMX3DNowLevel; 1593 enum XOPEnum { 1594 NoXOP, 1595 SSE4A, 1596 FMA4, 1597 XOP 1598 } XOPLevel; 1599 1600 bool HasAES; 1601 bool HasPCLMUL; 1602 bool HasLZCNT; 1603 bool HasRDRND; 1604 bool HasBMI; 1605 bool HasBMI2; 1606 bool HasPOPCNT; 1607 bool HasRTM; 1608 bool HasPRFCHW; 1609 bool HasRDSEED; 1610 bool HasTBM; 1611 bool HasFMA; 1612 bool HasF16C; 1613 bool HasAVX512CD, HasAVX512ER, HasAVX512PF; 1614 bool HasSHA; 1615 bool HasCX16; 1616 1617 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1618 /// 1619 /// Each enumeration represents a particular CPU supported by Clang. These 1620 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1621 enum CPUKind { 1622 CK_Generic, 1623 1624 /// \name i386 1625 /// i386-generation processors. 1626 //@{ 1627 CK_i386, 1628 //@} 1629 1630 /// \name i486 1631 /// i486-generation processors. 1632 //@{ 1633 CK_i486, 1634 CK_WinChipC6, 1635 CK_WinChip2, 1636 CK_C3, 1637 //@} 1638 1639 /// \name i586 1640 /// i586-generation processors, P5 microarchitecture based. 1641 //@{ 1642 CK_i586, 1643 CK_Pentium, 1644 CK_PentiumMMX, 1645 //@} 1646 1647 /// \name i686 1648 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1649 //@{ 1650 CK_i686, 1651 CK_PentiumPro, 1652 CK_Pentium2, 1653 CK_Pentium3, 1654 CK_Pentium3M, 1655 CK_PentiumM, 1656 CK_C3_2, 1657 1658 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1659 /// Clang however has some logic to suport this. 1660 // FIXME: Warn, deprecate, and potentially remove this. 1661 CK_Yonah, 1662 //@} 1663 1664 /// \name Netburst 1665 /// Netburst microarchitecture based processors. 1666 //@{ 1667 CK_Pentium4, 1668 CK_Pentium4M, 1669 CK_Prescott, 1670 CK_Nocona, 1671 //@} 1672 1673 /// \name Core 1674 /// Core microarchitecture based processors. 1675 //@{ 1676 CK_Core2, 1677 1678 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1679 /// codename which GCC no longer accepts as an option to -march, but Clang 1680 /// has some logic for recognizing it. 1681 // FIXME: Warn, deprecate, and potentially remove this. 1682 CK_Penryn, 1683 //@} 1684 1685 /// \name Atom 1686 /// Atom processors 1687 //@{ 1688 CK_Atom, 1689 CK_Silvermont, 1690 //@} 1691 1692 /// \name Nehalem 1693 /// Nehalem microarchitecture based processors. 1694 //@{ 1695 CK_Corei7, 1696 CK_Corei7AVX, 1697 CK_CoreAVXi, 1698 CK_CoreAVX2, 1699 //@} 1700 1701 /// \name Knights Landing 1702 /// Knights Landing processor. 1703 CK_KNL, 1704 1705 /// \name K6 1706 /// K6 architecture processors. 1707 //@{ 1708 CK_K6, 1709 CK_K6_2, 1710 CK_K6_3, 1711 //@} 1712 1713 /// \name K7 1714 /// K7 architecture processors. 1715 //@{ 1716 CK_Athlon, 1717 CK_AthlonThunderbird, 1718 CK_Athlon4, 1719 CK_AthlonXP, 1720 CK_AthlonMP, 1721 //@} 1722 1723 /// \name K8 1724 /// K8 architecture processors. 1725 //@{ 1726 CK_Athlon64, 1727 CK_Athlon64SSE3, 1728 CK_AthlonFX, 1729 CK_K8, 1730 CK_K8SSE3, 1731 CK_Opteron, 1732 CK_OpteronSSE3, 1733 CK_AMDFAM10, 1734 //@} 1735 1736 /// \name Bobcat 1737 /// Bobcat architecture processors. 1738 //@{ 1739 CK_BTVER1, 1740 CK_BTVER2, 1741 //@} 1742 1743 /// \name Bulldozer 1744 /// Bulldozer architecture processors. 1745 //@{ 1746 CK_BDVER1, 1747 CK_BDVER2, 1748 CK_BDVER3, 1749 //@} 1750 1751 /// This specification is deprecated and will be removed in the future. 1752 /// Users should prefer \see CK_K8. 1753 // FIXME: Warn on this when the CPU is set to it. 1754 CK_x86_64, 1755 //@} 1756 1757 /// \name Geode 1758 /// Geode processors. 1759 //@{ 1760 CK_Geode 1761 //@} 1762 } CPU; 1763 1764 enum FPMathKind { 1765 FP_Default, 1766 FP_SSE, 1767 FP_387 1768 } FPMath; 1769 1770 public: 1771 X86TargetInfo(const llvm::Triple &Triple) 1772 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1773 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1774 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1775 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), 1776 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1777 HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic), 1778 FPMath(FP_Default) { 1779 BigEndian = false; 1780 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1781 } 1782 virtual unsigned getFloatEvalMethod() const { 1783 // X87 evaluates with 80 bits "long double" precision. 1784 return SSELevel == NoSSE ? 2 : 0; 1785 } 1786 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1787 unsigned &NumRecords) const { 1788 Records = BuiltinInfo; 1789 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1790 } 1791 virtual void getGCCRegNames(const char * const *&Names, 1792 unsigned &NumNames) const { 1793 Names = GCCRegNames; 1794 NumNames = llvm::array_lengthof(GCCRegNames); 1795 } 1796 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1797 unsigned &NumAliases) const { 1798 Aliases = 0; 1799 NumAliases = 0; 1800 } 1801 virtual void getGCCAddlRegNames(const AddlRegName *&Names, 1802 unsigned &NumNames) const { 1803 Names = AddlRegNames; 1804 NumNames = llvm::array_lengthof(AddlRegNames); 1805 } 1806 virtual bool validateAsmConstraint(const char *&Name, 1807 TargetInfo::ConstraintInfo &info) const; 1808 virtual std::string convertConstraint(const char *&Constraint) const; 1809 virtual const char *getClobbers() const { 1810 return "~{dirflag},~{fpsr},~{flags}"; 1811 } 1812 virtual void getTargetDefines(const LangOptions &Opts, 1813 MacroBuilder &Builder) const; 1814 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1815 bool Enabled); 1816 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1817 bool Enabled); 1818 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1819 bool Enabled); 1820 virtual void setFeatureEnabled(llvm::StringMap<bool> &Features, 1821 StringRef Name, bool Enabled) const { 1822 setFeatureEnabledImpl(Features, Name, Enabled); 1823 } 1824 // This exists purely to cut down on the number of virtual calls in 1825 // getDefaultFeatures which calls this repeatedly. 1826 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1827 StringRef Name, bool Enabled); 1828 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 1829 virtual bool hasFeature(StringRef Feature) const; 1830 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 1831 DiagnosticsEngine &Diags); 1832 virtual const char* getABI() const { 1833 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1834 return "avx"; 1835 else if (getTriple().getArch() == llvm::Triple::x86 && 1836 MMX3DNowLevel == NoMMX3DNow) 1837 return "no-mmx"; 1838 return ""; 1839 } 1840 virtual bool setCPU(const std::string &Name) { 1841 CPU = llvm::StringSwitch<CPUKind>(Name) 1842 .Case("i386", CK_i386) 1843 .Case("i486", CK_i486) 1844 .Case("winchip-c6", CK_WinChipC6) 1845 .Case("winchip2", CK_WinChip2) 1846 .Case("c3", CK_C3) 1847 .Case("i586", CK_i586) 1848 .Case("pentium", CK_Pentium) 1849 .Case("pentium-mmx", CK_PentiumMMX) 1850 .Case("i686", CK_i686) 1851 .Case("pentiumpro", CK_PentiumPro) 1852 .Case("pentium2", CK_Pentium2) 1853 .Case("pentium3", CK_Pentium3) 1854 .Case("pentium3m", CK_Pentium3M) 1855 .Case("pentium-m", CK_PentiumM) 1856 .Case("c3-2", CK_C3_2) 1857 .Case("yonah", CK_Yonah) 1858 .Case("pentium4", CK_Pentium4) 1859 .Case("pentium4m", CK_Pentium4M) 1860 .Case("prescott", CK_Prescott) 1861 .Case("nocona", CK_Nocona) 1862 .Case("core2", CK_Core2) 1863 .Case("penryn", CK_Penryn) 1864 .Case("atom", CK_Atom) 1865 .Case("slm", CK_Silvermont) 1866 .Case("corei7", CK_Corei7) 1867 .Case("corei7-avx", CK_Corei7AVX) 1868 .Case("core-avx-i", CK_CoreAVXi) 1869 .Case("core-avx2", CK_CoreAVX2) 1870 .Case("knl", CK_KNL) 1871 .Case("k6", CK_K6) 1872 .Case("k6-2", CK_K6_2) 1873 .Case("k6-3", CK_K6_3) 1874 .Case("athlon", CK_Athlon) 1875 .Case("athlon-tbird", CK_AthlonThunderbird) 1876 .Case("athlon-4", CK_Athlon4) 1877 .Case("athlon-xp", CK_AthlonXP) 1878 .Case("athlon-mp", CK_AthlonMP) 1879 .Case("athlon64", CK_Athlon64) 1880 .Case("athlon64-sse3", CK_Athlon64SSE3) 1881 .Case("athlon-fx", CK_AthlonFX) 1882 .Case("k8", CK_K8) 1883 .Case("k8-sse3", CK_K8SSE3) 1884 .Case("opteron", CK_Opteron) 1885 .Case("opteron-sse3", CK_OpteronSSE3) 1886 .Case("amdfam10", CK_AMDFAM10) 1887 .Case("btver1", CK_BTVER1) 1888 .Case("btver2", CK_BTVER2) 1889 .Case("bdver1", CK_BDVER1) 1890 .Case("bdver2", CK_BDVER2) 1891 .Case("bdver3", CK_BDVER3) 1892 .Case("x86-64", CK_x86_64) 1893 .Case("geode", CK_Geode) 1894 .Default(CK_Generic); 1895 1896 // Perform any per-CPU checks necessary to determine if this CPU is 1897 // acceptable. 1898 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1899 // invalid without explaining *why*. 1900 switch (CPU) { 1901 case CK_Generic: 1902 // No processor selected! 1903 return false; 1904 1905 case CK_i386: 1906 case CK_i486: 1907 case CK_WinChipC6: 1908 case CK_WinChip2: 1909 case CK_C3: 1910 case CK_i586: 1911 case CK_Pentium: 1912 case CK_PentiumMMX: 1913 case CK_i686: 1914 case CK_PentiumPro: 1915 case CK_Pentium2: 1916 case CK_Pentium3: 1917 case CK_Pentium3M: 1918 case CK_PentiumM: 1919 case CK_Yonah: 1920 case CK_C3_2: 1921 case CK_Pentium4: 1922 case CK_Pentium4M: 1923 case CK_Prescott: 1924 case CK_K6: 1925 case CK_K6_2: 1926 case CK_K6_3: 1927 case CK_Athlon: 1928 case CK_AthlonThunderbird: 1929 case CK_Athlon4: 1930 case CK_AthlonXP: 1931 case CK_AthlonMP: 1932 case CK_Geode: 1933 // Only accept certain architectures when compiling in 32-bit mode. 1934 if (getTriple().getArch() != llvm::Triple::x86) 1935 return false; 1936 1937 // Fallthrough 1938 case CK_Nocona: 1939 case CK_Core2: 1940 case CK_Penryn: 1941 case CK_Atom: 1942 case CK_Silvermont: 1943 case CK_Corei7: 1944 case CK_Corei7AVX: 1945 case CK_CoreAVXi: 1946 case CK_CoreAVX2: 1947 case CK_KNL: 1948 case CK_Athlon64: 1949 case CK_Athlon64SSE3: 1950 case CK_AthlonFX: 1951 case CK_K8: 1952 case CK_K8SSE3: 1953 case CK_Opteron: 1954 case CK_OpteronSSE3: 1955 case CK_AMDFAM10: 1956 case CK_BTVER1: 1957 case CK_BTVER2: 1958 case CK_BDVER1: 1959 case CK_BDVER2: 1960 case CK_BDVER3: 1961 case CK_x86_64: 1962 return true; 1963 } 1964 llvm_unreachable("Unhandled CPU kind"); 1965 } 1966 1967 virtual bool setFPMath(StringRef Name); 1968 1969 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 1970 // We accept all non-ARM calling conventions 1971 return (CC == CC_X86ThisCall || 1972 CC == CC_X86FastCall || 1973 CC == CC_X86StdCall || 1974 CC == CC_C || 1975 CC == CC_X86Pascal || 1976 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 1977 } 1978 1979 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 1980 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 1981 } 1982 }; 1983 1984 bool X86TargetInfo::setFPMath(StringRef Name) { 1985 if (Name == "387") { 1986 FPMath = FP_387; 1987 return true; 1988 } 1989 if (Name == "sse") { 1990 FPMath = FP_SSE; 1991 return true; 1992 } 1993 return false; 1994 } 1995 1996 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1997 // FIXME: This *really* should not be here. 1998 1999 // X86_64 always has SSE2. 2000 if (getTriple().getArch() == llvm::Triple::x86_64) 2001 setFeatureEnabledImpl(Features, "sse2", true); 2002 2003 switch (CPU) { 2004 case CK_Generic: 2005 case CK_i386: 2006 case CK_i486: 2007 case CK_i586: 2008 case CK_Pentium: 2009 case CK_i686: 2010 case CK_PentiumPro: 2011 break; 2012 case CK_PentiumMMX: 2013 case CK_Pentium2: 2014 setFeatureEnabledImpl(Features, "mmx", true); 2015 break; 2016 case CK_Pentium3: 2017 case CK_Pentium3M: 2018 setFeatureEnabledImpl(Features, "sse", true); 2019 break; 2020 case CK_PentiumM: 2021 case CK_Pentium4: 2022 case CK_Pentium4M: 2023 case CK_x86_64: 2024 setFeatureEnabledImpl(Features, "sse2", true); 2025 break; 2026 case CK_Yonah: 2027 case CK_Prescott: 2028 case CK_Nocona: 2029 setFeatureEnabledImpl(Features, "sse3", true); 2030 setFeatureEnabledImpl(Features, "cx16", true); 2031 break; 2032 case CK_Core2: 2033 setFeatureEnabledImpl(Features, "ssse3", true); 2034 setFeatureEnabledImpl(Features, "cx16", true); 2035 break; 2036 case CK_Penryn: 2037 setFeatureEnabledImpl(Features, "sse4.1", true); 2038 setFeatureEnabledImpl(Features, "cx16", true); 2039 break; 2040 case CK_Atom: 2041 setFeatureEnabledImpl(Features, "ssse3", true); 2042 setFeatureEnabledImpl(Features, "cx16", true); 2043 break; 2044 case CK_Silvermont: 2045 setFeatureEnabledImpl(Features, "sse4.2", true); 2046 setFeatureEnabledImpl(Features, "aes", true); 2047 setFeatureEnabledImpl(Features, "cx16", true); 2048 setFeatureEnabledImpl(Features, "pclmul", true); 2049 break; 2050 case CK_Corei7: 2051 setFeatureEnabledImpl(Features, "sse4.2", true); 2052 setFeatureEnabledImpl(Features, "cx16", true); 2053 break; 2054 case CK_Corei7AVX: 2055 setFeatureEnabledImpl(Features, "avx", true); 2056 setFeatureEnabledImpl(Features, "aes", true); 2057 setFeatureEnabledImpl(Features, "cx16", true); 2058 setFeatureEnabledImpl(Features, "pclmul", true); 2059 break; 2060 case CK_CoreAVXi: 2061 setFeatureEnabledImpl(Features, "avx", true); 2062 setFeatureEnabledImpl(Features, "aes", true); 2063 setFeatureEnabledImpl(Features, "pclmul", true); 2064 setFeatureEnabledImpl(Features, "rdrnd", true); 2065 setFeatureEnabledImpl(Features, "f16c", true); 2066 break; 2067 case CK_CoreAVX2: 2068 setFeatureEnabledImpl(Features, "avx2", true); 2069 setFeatureEnabledImpl(Features, "aes", true); 2070 setFeatureEnabledImpl(Features, "pclmul", true); 2071 setFeatureEnabledImpl(Features, "lzcnt", true); 2072 setFeatureEnabledImpl(Features, "rdrnd", true); 2073 setFeatureEnabledImpl(Features, "f16c", true); 2074 setFeatureEnabledImpl(Features, "bmi", true); 2075 setFeatureEnabledImpl(Features, "bmi2", true); 2076 setFeatureEnabledImpl(Features, "rtm", true); 2077 setFeatureEnabledImpl(Features, "fma", true); 2078 setFeatureEnabledImpl(Features, "cx16", true); 2079 break; 2080 case CK_KNL: 2081 setFeatureEnabledImpl(Features, "avx512f", true); 2082 setFeatureEnabledImpl(Features, "avx512cd", true); 2083 setFeatureEnabledImpl(Features, "avx512er", true); 2084 setFeatureEnabledImpl(Features, "avx512pf", true); 2085 setFeatureEnabledImpl(Features, "aes", true); 2086 setFeatureEnabledImpl(Features, "pclmul", true); 2087 setFeatureEnabledImpl(Features, "lzcnt", true); 2088 setFeatureEnabledImpl(Features, "rdrnd", true); 2089 setFeatureEnabledImpl(Features, "f16c", true); 2090 setFeatureEnabledImpl(Features, "bmi", true); 2091 setFeatureEnabledImpl(Features, "bmi2", true); 2092 setFeatureEnabledImpl(Features, "rtm", true); 2093 setFeatureEnabledImpl(Features, "fma", true); 2094 break; 2095 case CK_K6: 2096 case CK_WinChipC6: 2097 setFeatureEnabledImpl(Features, "mmx", true); 2098 break; 2099 case CK_K6_2: 2100 case CK_K6_3: 2101 case CK_WinChip2: 2102 case CK_C3: 2103 setFeatureEnabledImpl(Features, "3dnow", true); 2104 break; 2105 case CK_Athlon: 2106 case CK_AthlonThunderbird: 2107 case CK_Geode: 2108 setFeatureEnabledImpl(Features, "3dnowa", true); 2109 break; 2110 case CK_Athlon4: 2111 case CK_AthlonXP: 2112 case CK_AthlonMP: 2113 setFeatureEnabledImpl(Features, "sse", true); 2114 setFeatureEnabledImpl(Features, "3dnowa", true); 2115 break; 2116 case CK_K8: 2117 case CK_Opteron: 2118 case CK_Athlon64: 2119 case CK_AthlonFX: 2120 setFeatureEnabledImpl(Features, "sse2", true); 2121 setFeatureEnabledImpl(Features, "3dnowa", true); 2122 break; 2123 case CK_K8SSE3: 2124 case CK_OpteronSSE3: 2125 case CK_Athlon64SSE3: 2126 setFeatureEnabledImpl(Features, "sse3", true); 2127 setFeatureEnabledImpl(Features, "3dnowa", true); 2128 break; 2129 case CK_AMDFAM10: 2130 setFeatureEnabledImpl(Features, "sse3", true); 2131 setFeatureEnabledImpl(Features, "sse4a", true); 2132 setFeatureEnabledImpl(Features, "3dnowa", true); 2133 setFeatureEnabledImpl(Features, "lzcnt", true); 2134 setFeatureEnabledImpl(Features, "popcnt", true); 2135 break; 2136 case CK_BTVER1: 2137 setFeatureEnabledImpl(Features, "ssse3", true); 2138 setFeatureEnabledImpl(Features, "sse4a", true); 2139 setFeatureEnabledImpl(Features, "cx16", true); 2140 setFeatureEnabledImpl(Features, "lzcnt", true); 2141 setFeatureEnabledImpl(Features, "popcnt", true); 2142 setFeatureEnabledImpl(Features, "prfchw", true); 2143 break; 2144 case CK_BTVER2: 2145 setFeatureEnabledImpl(Features, "avx", true); 2146 setFeatureEnabledImpl(Features, "sse4a", true); 2147 setFeatureEnabledImpl(Features, "lzcnt", true); 2148 setFeatureEnabledImpl(Features, "aes", true); 2149 setFeatureEnabledImpl(Features, "pclmul", true); 2150 setFeatureEnabledImpl(Features, "prfchw", true); 2151 setFeatureEnabledImpl(Features, "bmi", true); 2152 setFeatureEnabledImpl(Features, "f16c", true); 2153 setFeatureEnabledImpl(Features, "cx16", true); 2154 break; 2155 case CK_BDVER1: 2156 setFeatureEnabledImpl(Features, "xop", true); 2157 setFeatureEnabledImpl(Features, "lzcnt", true); 2158 setFeatureEnabledImpl(Features, "aes", true); 2159 setFeatureEnabledImpl(Features, "pclmul", true); 2160 setFeatureEnabledImpl(Features, "prfchw", true); 2161 setFeatureEnabledImpl(Features, "cx16", true); 2162 break; 2163 case CK_BDVER2: 2164 case CK_BDVER3: 2165 setFeatureEnabledImpl(Features, "xop", true); 2166 setFeatureEnabledImpl(Features, "lzcnt", true); 2167 setFeatureEnabledImpl(Features, "aes", true); 2168 setFeatureEnabledImpl(Features, "pclmul", true); 2169 setFeatureEnabledImpl(Features, "prfchw", true); 2170 setFeatureEnabledImpl(Features, "bmi", true); 2171 setFeatureEnabledImpl(Features, "fma", true); 2172 setFeatureEnabledImpl(Features, "f16c", true); 2173 setFeatureEnabledImpl(Features, "tbm", true); 2174 setFeatureEnabledImpl(Features, "cx16", true); 2175 break; 2176 case CK_C3_2: 2177 setFeatureEnabledImpl(Features, "sse", true); 2178 break; 2179 } 2180 } 2181 2182 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2183 X86SSEEnum Level, bool Enabled) { 2184 if (Enabled) { 2185 switch (Level) { 2186 case AVX512F: 2187 Features["avx512f"] = true; 2188 case AVX2: 2189 Features["avx2"] = true; 2190 case AVX: 2191 Features["avx"] = true; 2192 case SSE42: 2193 Features["sse4.2"] = true; 2194 case SSE41: 2195 Features["sse4.1"] = true; 2196 case SSSE3: 2197 Features["ssse3"] = true; 2198 case SSE3: 2199 Features["sse3"] = true; 2200 case SSE2: 2201 Features["sse2"] = true; 2202 case SSE1: 2203 Features["sse"] = true; 2204 case NoSSE: 2205 break; 2206 } 2207 return; 2208 } 2209 2210 switch (Level) { 2211 case NoSSE: 2212 case SSE1: 2213 Features["sse"] = false; 2214 case SSE2: 2215 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2216 Features["sha"] = false; 2217 case SSE3: 2218 Features["sse3"] = false; 2219 setXOPLevel(Features, NoXOP, false); 2220 case SSSE3: 2221 Features["ssse3"] = false; 2222 case SSE41: 2223 Features["sse4.1"] = false; 2224 case SSE42: 2225 Features["sse4.2"] = false; 2226 case AVX: 2227 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2228 setXOPLevel(Features, FMA4, false); 2229 case AVX2: 2230 Features["avx2"] = false; 2231 case AVX512F: 2232 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2233 Features["avx512pf"] = false; 2234 } 2235 } 2236 2237 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2238 MMX3DNowEnum Level, bool Enabled) { 2239 if (Enabled) { 2240 switch (Level) { 2241 case AMD3DNowAthlon: 2242 Features["3dnowa"] = true; 2243 case AMD3DNow: 2244 Features["3dnow"] = true; 2245 case MMX: 2246 Features["mmx"] = true; 2247 case NoMMX3DNow: 2248 break; 2249 } 2250 return; 2251 } 2252 2253 switch (Level) { 2254 case NoMMX3DNow: 2255 case MMX: 2256 Features["mmx"] = false; 2257 case AMD3DNow: 2258 Features["3dnow"] = false; 2259 case AMD3DNowAthlon: 2260 Features["3dnowa"] = false; 2261 } 2262 } 2263 2264 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2265 bool Enabled) { 2266 if (Enabled) { 2267 switch (Level) { 2268 case XOP: 2269 Features["xop"] = true; 2270 case FMA4: 2271 Features["fma4"] = true; 2272 setSSELevel(Features, AVX, true); 2273 case SSE4A: 2274 Features["sse4a"] = true; 2275 setSSELevel(Features, SSE3, true); 2276 case NoXOP: 2277 break; 2278 } 2279 return; 2280 } 2281 2282 switch (Level) { 2283 case NoXOP: 2284 case SSE4A: 2285 Features["sse4a"] = false; 2286 case FMA4: 2287 Features["fma4"] = false; 2288 case XOP: 2289 Features["xop"] = false; 2290 } 2291 } 2292 2293 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2294 StringRef Name, bool Enabled) { 2295 // FIXME: This *really* should not be here. We need some way of translating 2296 // options into llvm subtarget features. 2297 if (Name == "sse4") 2298 Name = "sse4.2"; 2299 2300 Features[Name] = Enabled; 2301 2302 if (Name == "mmx") { 2303 setMMXLevel(Features, MMX, Enabled); 2304 } else if (Name == "sse") { 2305 setSSELevel(Features, SSE1, Enabled); 2306 } else if (Name == "sse2") { 2307 setSSELevel(Features, SSE2, Enabled); 2308 } else if (Name == "sse3") { 2309 setSSELevel(Features, SSE3, Enabled); 2310 } else if (Name == "ssse3") { 2311 setSSELevel(Features, SSSE3, Enabled); 2312 } else if (Name == "sse4.2") { 2313 setSSELevel(Features, SSE42, Enabled); 2314 } else if (Name == "sse4.1") { 2315 setSSELevel(Features, SSE41, Enabled); 2316 } else if (Name == "3dnow") { 2317 setMMXLevel(Features, AMD3DNow, Enabled); 2318 } else if (Name == "3dnowa") { 2319 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2320 } else if (Name == "aes") { 2321 if (Enabled) 2322 setSSELevel(Features, SSE2, Enabled); 2323 } else if (Name == "pclmul") { 2324 if (Enabled) 2325 setSSELevel(Features, SSE2, Enabled); 2326 } else if (Name == "avx") { 2327 setSSELevel(Features, AVX, Enabled); 2328 } else if (Name == "avx2") { 2329 setSSELevel(Features, AVX2, Enabled); 2330 } else if (Name == "avx512f") { 2331 setSSELevel(Features, AVX512F, Enabled); 2332 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") { 2333 if (Enabled) 2334 setSSELevel(Features, AVX512F, Enabled); 2335 } else if (Name == "fma") { 2336 if (Enabled) 2337 setSSELevel(Features, AVX, Enabled); 2338 } else if (Name == "fma4") { 2339 setXOPLevel(Features, FMA4, Enabled); 2340 } else if (Name == "xop") { 2341 setXOPLevel(Features, XOP, Enabled); 2342 } else if (Name == "sse4a") { 2343 setXOPLevel(Features, SSE4A, Enabled); 2344 } else if (Name == "f16c") { 2345 if (Enabled) 2346 setSSELevel(Features, AVX, Enabled); 2347 } else if (Name == "sha") { 2348 if (Enabled) 2349 setSSELevel(Features, SSE2, Enabled); 2350 } 2351 } 2352 2353 /// handleTargetFeatures - Perform initialization based on the user 2354 /// configured set of features. 2355 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2356 DiagnosticsEngine &Diags) { 2357 // Remember the maximum enabled sselevel. 2358 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2359 // Ignore disabled features. 2360 if (Features[i][0] == '-') 2361 continue; 2362 2363 StringRef Feature = StringRef(Features[i]).substr(1); 2364 2365 if (Feature == "aes") { 2366 HasAES = true; 2367 continue; 2368 } 2369 2370 if (Feature == "pclmul") { 2371 HasPCLMUL = true; 2372 continue; 2373 } 2374 2375 if (Feature == "lzcnt") { 2376 HasLZCNT = true; 2377 continue; 2378 } 2379 2380 if (Feature == "rdrnd") { 2381 HasRDRND = true; 2382 continue; 2383 } 2384 2385 if (Feature == "bmi") { 2386 HasBMI = true; 2387 continue; 2388 } 2389 2390 if (Feature == "bmi2") { 2391 HasBMI2 = true; 2392 continue; 2393 } 2394 2395 if (Feature == "popcnt") { 2396 HasPOPCNT = true; 2397 continue; 2398 } 2399 2400 if (Feature == "rtm") { 2401 HasRTM = true; 2402 continue; 2403 } 2404 2405 if (Feature == "prfchw") { 2406 HasPRFCHW = true; 2407 continue; 2408 } 2409 2410 if (Feature == "rdseed") { 2411 HasRDSEED = true; 2412 continue; 2413 } 2414 2415 if (Feature == "tbm") { 2416 HasTBM = true; 2417 continue; 2418 } 2419 2420 if (Feature == "fma") { 2421 HasFMA = true; 2422 continue; 2423 } 2424 2425 if (Feature == "f16c") { 2426 HasF16C = true; 2427 continue; 2428 } 2429 2430 if (Feature == "avx512cd") { 2431 HasAVX512CD = true; 2432 continue; 2433 } 2434 2435 if (Feature == "avx512er") { 2436 HasAVX512ER = true; 2437 continue; 2438 } 2439 2440 if (Feature == "avx512pf") { 2441 HasAVX512PF = true; 2442 continue; 2443 } 2444 2445 if (Feature == "sha") { 2446 HasSHA = true; 2447 continue; 2448 } 2449 2450 if (Feature == "cx16") { 2451 HasCX16 = true; 2452 continue; 2453 } 2454 2455 assert(Features[i][0] == '+' && "Invalid target feature!"); 2456 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2457 .Case("avx512f", AVX512F) 2458 .Case("avx2", AVX2) 2459 .Case("avx", AVX) 2460 .Case("sse4.2", SSE42) 2461 .Case("sse4.1", SSE41) 2462 .Case("ssse3", SSSE3) 2463 .Case("sse3", SSE3) 2464 .Case("sse2", SSE2) 2465 .Case("sse", SSE1) 2466 .Default(NoSSE); 2467 SSELevel = std::max(SSELevel, Level); 2468 2469 MMX3DNowEnum ThreeDNowLevel = 2470 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2471 .Case("3dnowa", AMD3DNowAthlon) 2472 .Case("3dnow", AMD3DNow) 2473 .Case("mmx", MMX) 2474 .Default(NoMMX3DNow); 2475 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2476 2477 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2478 .Case("xop", XOP) 2479 .Case("fma4", FMA4) 2480 .Case("sse4a", SSE4A) 2481 .Default(NoXOP); 2482 XOPLevel = std::max(XOPLevel, XLevel); 2483 } 2484 2485 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2486 // Can't do this earlier because we need to be able to explicitly enable 2487 // popcnt and still disable sse4.2. 2488 if (!HasPOPCNT && SSELevel >= SSE42 && 2489 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2490 HasPOPCNT = true; 2491 Features.push_back("+popcnt"); 2492 } 2493 2494 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2495 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2496 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2497 HasPRFCHW = true; 2498 Features.push_back("+prfchw"); 2499 } 2500 2501 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2502 // matches the selected sse level. 2503 if (FPMath == FP_SSE && SSELevel < SSE1) { 2504 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2505 return false; 2506 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2507 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2508 return false; 2509 } 2510 2511 // Don't tell the backend if we're turning off mmx; it will end up disabling 2512 // SSE, which we don't want. 2513 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2514 // then enable MMX. 2515 std::vector<std::string>::iterator it; 2516 it = std::find(Features.begin(), Features.end(), "-mmx"); 2517 if (it != Features.end()) 2518 Features.erase(it); 2519 else if (SSELevel > NoSSE) 2520 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2521 return true; 2522 } 2523 2524 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2525 /// definitions for this particular subtarget. 2526 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2527 MacroBuilder &Builder) const { 2528 // Target identification. 2529 if (getTriple().getArch() == llvm::Triple::x86_64) { 2530 Builder.defineMacro("__amd64__"); 2531 Builder.defineMacro("__amd64"); 2532 Builder.defineMacro("__x86_64"); 2533 Builder.defineMacro("__x86_64__"); 2534 } else { 2535 DefineStd(Builder, "i386", Opts); 2536 } 2537 2538 // Subtarget options. 2539 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2540 // truly should be based on -mtune options. 2541 switch (CPU) { 2542 case CK_Generic: 2543 break; 2544 case CK_i386: 2545 // The rest are coming from the i386 define above. 2546 Builder.defineMacro("__tune_i386__"); 2547 break; 2548 case CK_i486: 2549 case CK_WinChipC6: 2550 case CK_WinChip2: 2551 case CK_C3: 2552 defineCPUMacros(Builder, "i486"); 2553 break; 2554 case CK_PentiumMMX: 2555 Builder.defineMacro("__pentium_mmx__"); 2556 Builder.defineMacro("__tune_pentium_mmx__"); 2557 // Fallthrough 2558 case CK_i586: 2559 case CK_Pentium: 2560 defineCPUMacros(Builder, "i586"); 2561 defineCPUMacros(Builder, "pentium"); 2562 break; 2563 case CK_Pentium3: 2564 case CK_Pentium3M: 2565 case CK_PentiumM: 2566 Builder.defineMacro("__tune_pentium3__"); 2567 // Fallthrough 2568 case CK_Pentium2: 2569 case CK_C3_2: 2570 Builder.defineMacro("__tune_pentium2__"); 2571 // Fallthrough 2572 case CK_PentiumPro: 2573 Builder.defineMacro("__tune_i686__"); 2574 Builder.defineMacro("__tune_pentiumpro__"); 2575 // Fallthrough 2576 case CK_i686: 2577 Builder.defineMacro("__i686"); 2578 Builder.defineMacro("__i686__"); 2579 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2580 Builder.defineMacro("__pentiumpro"); 2581 Builder.defineMacro("__pentiumpro__"); 2582 break; 2583 case CK_Pentium4: 2584 case CK_Pentium4M: 2585 defineCPUMacros(Builder, "pentium4"); 2586 break; 2587 case CK_Yonah: 2588 case CK_Prescott: 2589 case CK_Nocona: 2590 defineCPUMacros(Builder, "nocona"); 2591 break; 2592 case CK_Core2: 2593 case CK_Penryn: 2594 defineCPUMacros(Builder, "core2"); 2595 break; 2596 case CK_Atom: 2597 defineCPUMacros(Builder, "atom"); 2598 break; 2599 case CK_Silvermont: 2600 defineCPUMacros(Builder, "slm"); 2601 break; 2602 case CK_Corei7: 2603 case CK_Corei7AVX: 2604 case CK_CoreAVXi: 2605 case CK_CoreAVX2: 2606 defineCPUMacros(Builder, "corei7"); 2607 break; 2608 case CK_KNL: 2609 defineCPUMacros(Builder, "knl"); 2610 break; 2611 case CK_K6_2: 2612 Builder.defineMacro("__k6_2__"); 2613 Builder.defineMacro("__tune_k6_2__"); 2614 // Fallthrough 2615 case CK_K6_3: 2616 if (CPU != CK_K6_2) { // In case of fallthrough 2617 // FIXME: GCC may be enabling these in cases where some other k6 2618 // architecture is specified but -m3dnow is explicitly provided. The 2619 // exact semantics need to be determined and emulated here. 2620 Builder.defineMacro("__k6_3__"); 2621 Builder.defineMacro("__tune_k6_3__"); 2622 } 2623 // Fallthrough 2624 case CK_K6: 2625 defineCPUMacros(Builder, "k6"); 2626 break; 2627 case CK_Athlon: 2628 case CK_AthlonThunderbird: 2629 case CK_Athlon4: 2630 case CK_AthlonXP: 2631 case CK_AthlonMP: 2632 defineCPUMacros(Builder, "athlon"); 2633 if (SSELevel != NoSSE) { 2634 Builder.defineMacro("__athlon_sse__"); 2635 Builder.defineMacro("__tune_athlon_sse__"); 2636 } 2637 break; 2638 case CK_K8: 2639 case CK_K8SSE3: 2640 case CK_x86_64: 2641 case CK_Opteron: 2642 case CK_OpteronSSE3: 2643 case CK_Athlon64: 2644 case CK_Athlon64SSE3: 2645 case CK_AthlonFX: 2646 defineCPUMacros(Builder, "k8"); 2647 break; 2648 case CK_AMDFAM10: 2649 defineCPUMacros(Builder, "amdfam10"); 2650 break; 2651 case CK_BTVER1: 2652 defineCPUMacros(Builder, "btver1"); 2653 break; 2654 case CK_BTVER2: 2655 defineCPUMacros(Builder, "btver2"); 2656 break; 2657 case CK_BDVER1: 2658 defineCPUMacros(Builder, "bdver1"); 2659 break; 2660 case CK_BDVER2: 2661 defineCPUMacros(Builder, "bdver2"); 2662 break; 2663 case CK_BDVER3: 2664 defineCPUMacros(Builder, "bdver3"); 2665 break; 2666 case CK_Geode: 2667 defineCPUMacros(Builder, "geode"); 2668 break; 2669 } 2670 2671 // Target properties. 2672 Builder.defineMacro("__LITTLE_ENDIAN__"); 2673 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2674 2675 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2676 // functions in glibc header files that use FP Stack inline asm which the 2677 // backend can't deal with (PR879). 2678 Builder.defineMacro("__NO_MATH_INLINES"); 2679 2680 if (HasAES) 2681 Builder.defineMacro("__AES__"); 2682 2683 if (HasPCLMUL) 2684 Builder.defineMacro("__PCLMUL__"); 2685 2686 if (HasLZCNT) 2687 Builder.defineMacro("__LZCNT__"); 2688 2689 if (HasRDRND) 2690 Builder.defineMacro("__RDRND__"); 2691 2692 if (HasBMI) 2693 Builder.defineMacro("__BMI__"); 2694 2695 if (HasBMI2) 2696 Builder.defineMacro("__BMI2__"); 2697 2698 if (HasPOPCNT) 2699 Builder.defineMacro("__POPCNT__"); 2700 2701 if (HasRTM) 2702 Builder.defineMacro("__RTM__"); 2703 2704 if (HasPRFCHW) 2705 Builder.defineMacro("__PRFCHW__"); 2706 2707 if (HasRDSEED) 2708 Builder.defineMacro("__RDSEED__"); 2709 2710 if (HasTBM) 2711 Builder.defineMacro("__TBM__"); 2712 2713 switch (XOPLevel) { 2714 case XOP: 2715 Builder.defineMacro("__XOP__"); 2716 case FMA4: 2717 Builder.defineMacro("__FMA4__"); 2718 case SSE4A: 2719 Builder.defineMacro("__SSE4A__"); 2720 case NoXOP: 2721 break; 2722 } 2723 2724 if (HasFMA) 2725 Builder.defineMacro("__FMA__"); 2726 2727 if (HasF16C) 2728 Builder.defineMacro("__F16C__"); 2729 2730 if (HasAVX512CD) 2731 Builder.defineMacro("__AVX512CD__"); 2732 if (HasAVX512ER) 2733 Builder.defineMacro("__AVX512ER__"); 2734 if (HasAVX512PF) 2735 Builder.defineMacro("__AVX512PF__"); 2736 2737 if (HasSHA) 2738 Builder.defineMacro("__SHA__"); 2739 2740 if (HasCX16) 2741 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2742 2743 // Each case falls through to the previous one here. 2744 switch (SSELevel) { 2745 case AVX512F: 2746 Builder.defineMacro("__AVX512F__"); 2747 case AVX2: 2748 Builder.defineMacro("__AVX2__"); 2749 case AVX: 2750 Builder.defineMacro("__AVX__"); 2751 case SSE42: 2752 Builder.defineMacro("__SSE4_2__"); 2753 case SSE41: 2754 Builder.defineMacro("__SSE4_1__"); 2755 case SSSE3: 2756 Builder.defineMacro("__SSSE3__"); 2757 case SSE3: 2758 Builder.defineMacro("__SSE3__"); 2759 case SSE2: 2760 Builder.defineMacro("__SSE2__"); 2761 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2762 case SSE1: 2763 Builder.defineMacro("__SSE__"); 2764 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2765 case NoSSE: 2766 break; 2767 } 2768 2769 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2770 switch (SSELevel) { 2771 case AVX512F: 2772 case AVX2: 2773 case AVX: 2774 case SSE42: 2775 case SSE41: 2776 case SSSE3: 2777 case SSE3: 2778 case SSE2: 2779 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2780 break; 2781 case SSE1: 2782 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2783 break; 2784 default: 2785 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2786 } 2787 } 2788 2789 // Each case falls through to the previous one here. 2790 switch (MMX3DNowLevel) { 2791 case AMD3DNowAthlon: 2792 Builder.defineMacro("__3dNOW_A__"); 2793 case AMD3DNow: 2794 Builder.defineMacro("__3dNOW__"); 2795 case MMX: 2796 Builder.defineMacro("__MMX__"); 2797 case NoMMX3DNow: 2798 break; 2799 } 2800 2801 if (CPU >= CK_i486) { 2802 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2803 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2804 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2805 } 2806 if (CPU >= CK_i586) 2807 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2808 } 2809 2810 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2811 return llvm::StringSwitch<bool>(Feature) 2812 .Case("aes", HasAES) 2813 .Case("avx", SSELevel >= AVX) 2814 .Case("avx2", SSELevel >= AVX2) 2815 .Case("avx512f", SSELevel >= AVX512F) 2816 .Case("avx512cd", HasAVX512CD) 2817 .Case("avx512er", HasAVX512ER) 2818 .Case("avx512pf", HasAVX512PF) 2819 .Case("bmi", HasBMI) 2820 .Case("bmi2", HasBMI2) 2821 .Case("cx16", HasCX16) 2822 .Case("f16c", HasF16C) 2823 .Case("fma", HasFMA) 2824 .Case("fma4", XOPLevel >= FMA4) 2825 .Case("tbm", HasTBM) 2826 .Case("lzcnt", HasLZCNT) 2827 .Case("rdrnd", HasRDRND) 2828 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2829 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2830 .Case("mmx", MMX3DNowLevel >= MMX) 2831 .Case("pclmul", HasPCLMUL) 2832 .Case("popcnt", HasPOPCNT) 2833 .Case("rtm", HasRTM) 2834 .Case("prfchw", HasPRFCHW) 2835 .Case("rdseed", HasRDSEED) 2836 .Case("sha", HasSHA) 2837 .Case("sse", SSELevel >= SSE1) 2838 .Case("sse2", SSELevel >= SSE2) 2839 .Case("sse3", SSELevel >= SSE3) 2840 .Case("ssse3", SSELevel >= SSSE3) 2841 .Case("sse4.1", SSELevel >= SSE41) 2842 .Case("sse4.2", SSELevel >= SSE42) 2843 .Case("sse4a", XOPLevel >= SSE4A) 2844 .Case("x86", true) 2845 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2846 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2847 .Case("xop", XOPLevel >= XOP) 2848 .Default(false); 2849 } 2850 2851 bool 2852 X86TargetInfo::validateAsmConstraint(const char *&Name, 2853 TargetInfo::ConstraintInfo &Info) const { 2854 switch (*Name) { 2855 default: return false; 2856 case 'Y': // first letter of a pair: 2857 switch (*(Name+1)) { 2858 default: return false; 2859 case '0': // First SSE register. 2860 case 't': // Any SSE register, when SSE2 is enabled. 2861 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2862 case 'm': // any MMX register, when inter-unit moves enabled. 2863 break; // falls through to setAllowsRegister. 2864 } 2865 case 'a': // eax. 2866 case 'b': // ebx. 2867 case 'c': // ecx. 2868 case 'd': // edx. 2869 case 'S': // esi. 2870 case 'D': // edi. 2871 case 'A': // edx:eax. 2872 case 'f': // any x87 floating point stack register. 2873 case 't': // top of floating point stack. 2874 case 'u': // second from top of floating point stack. 2875 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2876 case 'y': // Any MMX register. 2877 case 'x': // Any SSE register. 2878 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2879 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2880 case 'l': // "Index" registers: any general register that can be used as an 2881 // index in a base+index memory access. 2882 Info.setAllowsRegister(); 2883 return true; 2884 case 'C': // SSE floating point constant. 2885 case 'G': // x87 floating point constant. 2886 case 'e': // 32-bit signed integer constant for use with zero-extending 2887 // x86_64 instructions. 2888 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2889 // x86_64 instructions. 2890 return true; 2891 } 2892 } 2893 2894 2895 std::string 2896 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2897 switch (*Constraint) { 2898 case 'a': return std::string("{ax}"); 2899 case 'b': return std::string("{bx}"); 2900 case 'c': return std::string("{cx}"); 2901 case 'd': return std::string("{dx}"); 2902 case 'S': return std::string("{si}"); 2903 case 'D': return std::string("{di}"); 2904 case 'p': // address 2905 return std::string("im"); 2906 case 't': // top of floating point stack. 2907 return std::string("{st}"); 2908 case 'u': // second from top of floating point stack. 2909 return std::string("{st(1)}"); // second from top of floating point stack. 2910 default: 2911 return std::string(1, *Constraint); 2912 } 2913 } 2914 } // end anonymous namespace 2915 2916 namespace { 2917 // X86-32 generic target 2918 class X86_32TargetInfo : public X86TargetInfo { 2919 public: 2920 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 2921 DoubleAlign = LongLongAlign = 32; 2922 LongDoubleWidth = 96; 2923 LongDoubleAlign = 32; 2924 SuitableAlign = 128; 2925 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 2926 SizeType = UnsignedInt; 2927 PtrDiffType = SignedInt; 2928 IntPtrType = SignedInt; 2929 RegParmMax = 3; 2930 2931 // Use fpret for all types. 2932 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2933 (1 << TargetInfo::Double) | 2934 (1 << TargetInfo::LongDouble)); 2935 2936 // x86-32 has atomics up to 8 bytes 2937 // FIXME: Check that we actually have cmpxchg8b before setting 2938 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2939 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2940 } 2941 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2942 return TargetInfo::CharPtrBuiltinVaList; 2943 } 2944 2945 int getEHDataRegisterNumber(unsigned RegNo) const { 2946 if (RegNo == 0) return 0; 2947 if (RegNo == 1) return 2; 2948 return -1; 2949 } 2950 virtual bool validateInputSize(StringRef Constraint, 2951 unsigned Size) const { 2952 switch (Constraint[0]) { 2953 default: break; 2954 case 'a': 2955 case 'b': 2956 case 'c': 2957 case 'd': 2958 return Size <= 32; 2959 } 2960 2961 return true; 2962 } 2963 }; 2964 } // end anonymous namespace 2965 2966 namespace { 2967 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2968 public: 2969 NetBSDI386TargetInfo(const llvm::Triple &Triple) 2970 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 2971 2972 virtual unsigned getFloatEvalMethod() const { 2973 unsigned Major, Minor, Micro; 2974 getTriple().getOSVersion(Major, Minor, Micro); 2975 // New NetBSD uses the default rounding mode. 2976 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 2977 return X86_32TargetInfo::getFloatEvalMethod(); 2978 // NetBSD before 6.99.26 defaults to "double" rounding. 2979 return 1; 2980 } 2981 }; 2982 } // end anonymous namespace 2983 2984 namespace { 2985 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 2986 public: 2987 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 2988 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 2989 SizeType = UnsignedLong; 2990 IntPtrType = SignedLong; 2991 PtrDiffType = SignedLong; 2992 } 2993 }; 2994 } // end anonymous namespace 2995 2996 namespace { 2997 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 2998 public: 2999 BitrigI386TargetInfo(const llvm::Triple &Triple) 3000 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3001 SizeType = UnsignedLong; 3002 IntPtrType = SignedLong; 3003 PtrDiffType = SignedLong; 3004 } 3005 }; 3006 } // end anonymous namespace 3007 3008 namespace { 3009 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3010 public: 3011 DarwinI386TargetInfo(const llvm::Triple &Triple) 3012 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3013 LongDoubleWidth = 128; 3014 LongDoubleAlign = 128; 3015 SuitableAlign = 128; 3016 MaxVectorAlign = 256; 3017 SizeType = UnsignedLong; 3018 IntPtrType = SignedLong; 3019 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3020 HasAlignMac68kSupport = true; 3021 } 3022 3023 }; 3024 } // end anonymous namespace 3025 3026 namespace { 3027 // x86-32 Windows target 3028 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3029 public: 3030 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3031 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3032 TLSSupported = false; 3033 WCharType = UnsignedShort; 3034 DoubleAlign = LongLongAlign = 64; 3035 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3036 } 3037 virtual void getTargetDefines(const LangOptions &Opts, 3038 MacroBuilder &Builder) const { 3039 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3040 } 3041 }; 3042 } // end anonymous namespace 3043 3044 namespace { 3045 3046 // x86-32 Windows Visual Studio target 3047 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 3048 public: 3049 VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple) 3050 : WindowsX86_32TargetInfo(Triple) { 3051 LongDoubleWidth = LongDoubleAlign = 64; 3052 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3053 } 3054 virtual void getTargetDefines(const LangOptions &Opts, 3055 MacroBuilder &Builder) const { 3056 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3057 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3058 // The value of the following reflects processor type. 3059 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3060 // We lost the original triple, so we use the default. 3061 Builder.defineMacro("_M_IX86", "600"); 3062 } 3063 }; 3064 } // end anonymous namespace 3065 3066 namespace { 3067 // x86-32 MinGW target 3068 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3069 public: 3070 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3071 : WindowsX86_32TargetInfo(Triple) {} 3072 virtual void getTargetDefines(const LangOptions &Opts, 3073 MacroBuilder &Builder) const { 3074 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3075 DefineStd(Builder, "WIN32", Opts); 3076 DefineStd(Builder, "WINNT", Opts); 3077 Builder.defineMacro("_X86_"); 3078 Builder.defineMacro("__MSVCRT__"); 3079 Builder.defineMacro("__MINGW32__"); 3080 3081 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3082 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3083 if (Opts.MicrosoftExt) 3084 // Provide "as-is" __declspec. 3085 Builder.defineMacro("__declspec", "__declspec"); 3086 else 3087 // Provide alias of __attribute__ like mingw32-gcc. 3088 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3089 } 3090 }; 3091 } // end anonymous namespace 3092 3093 namespace { 3094 // x86-32 Cygwin target 3095 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3096 public: 3097 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3098 : X86_32TargetInfo(Triple) { 3099 TLSSupported = false; 3100 WCharType = UnsignedShort; 3101 DoubleAlign = LongLongAlign = 64; 3102 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3103 } 3104 virtual void getTargetDefines(const LangOptions &Opts, 3105 MacroBuilder &Builder) const { 3106 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3107 Builder.defineMacro("_X86_"); 3108 Builder.defineMacro("__CYGWIN__"); 3109 Builder.defineMacro("__CYGWIN32__"); 3110 DefineStd(Builder, "unix", Opts); 3111 if (Opts.CPlusPlus) 3112 Builder.defineMacro("_GNU_SOURCE"); 3113 } 3114 }; 3115 } // end anonymous namespace 3116 3117 namespace { 3118 // x86-32 Haiku target 3119 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3120 public: 3121 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3122 SizeType = UnsignedLong; 3123 IntPtrType = SignedLong; 3124 PtrDiffType = SignedLong; 3125 ProcessIDType = SignedLong; 3126 this->UserLabelPrefix = ""; 3127 this->TLSSupported = false; 3128 } 3129 virtual void getTargetDefines(const LangOptions &Opts, 3130 MacroBuilder &Builder) const { 3131 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3132 Builder.defineMacro("__INTEL__"); 3133 Builder.defineMacro("__HAIKU__"); 3134 } 3135 }; 3136 } // end anonymous namespace 3137 3138 // RTEMS Target 3139 template<typename Target> 3140 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3141 protected: 3142 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3143 MacroBuilder &Builder) const { 3144 // RTEMS defines; list based off of gcc output 3145 3146 Builder.defineMacro("__rtems__"); 3147 Builder.defineMacro("__ELF__"); 3148 } 3149 3150 public: 3151 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3152 this->UserLabelPrefix = ""; 3153 3154 switch (Triple.getArch()) { 3155 default: 3156 case llvm::Triple::x86: 3157 // this->MCountName = ".mcount"; 3158 break; 3159 case llvm::Triple::mips: 3160 case llvm::Triple::mipsel: 3161 case llvm::Triple::ppc: 3162 case llvm::Triple::ppc64: 3163 case llvm::Triple::ppc64le: 3164 // this->MCountName = "_mcount"; 3165 break; 3166 case llvm::Triple::arm: 3167 // this->MCountName = "__mcount"; 3168 break; 3169 } 3170 } 3171 }; 3172 3173 namespace { 3174 // x86-32 RTEMS target 3175 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3176 public: 3177 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3178 SizeType = UnsignedLong; 3179 IntPtrType = SignedLong; 3180 PtrDiffType = SignedLong; 3181 this->UserLabelPrefix = ""; 3182 } 3183 virtual void getTargetDefines(const LangOptions &Opts, 3184 MacroBuilder &Builder) const { 3185 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3186 Builder.defineMacro("__INTEL__"); 3187 Builder.defineMacro("__rtems__"); 3188 } 3189 }; 3190 } // end anonymous namespace 3191 3192 namespace { 3193 // x86-64 generic target 3194 class X86_64TargetInfo : public X86TargetInfo { 3195 public: 3196 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3197 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 3198 LongDoubleWidth = 128; 3199 LongDoubleAlign = 128; 3200 LargeArrayMinWidth = 128; 3201 LargeArrayAlign = 128; 3202 SuitableAlign = 128; 3203 IntMaxType = SignedLong; 3204 UIntMaxType = UnsignedLong; 3205 Int64Type = SignedLong; 3206 RegParmMax = 6; 3207 3208 DescriptionString = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3209 3210 // Use fpret only for long double. 3211 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3212 3213 // Use fp2ret for _Complex long double. 3214 ComplexLongDoubleUsesFP2Ret = true; 3215 3216 // x86-64 has atomics up to 16 bytes. 3217 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 3218 // on CPUs with cmpxchg16b 3219 MaxAtomicPromoteWidth = 128; 3220 MaxAtomicInlineWidth = 64; 3221 } 3222 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3223 return TargetInfo::X86_64ABIBuiltinVaList; 3224 } 3225 3226 int getEHDataRegisterNumber(unsigned RegNo) const { 3227 if (RegNo == 0) return 0; 3228 if (RegNo == 1) return 1; 3229 return -1; 3230 } 3231 3232 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3233 return (CC == CC_C || 3234 CC == CC_IntelOclBicc || 3235 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3236 } 3237 3238 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 3239 return CC_C; 3240 } 3241 3242 }; 3243 } // end anonymous namespace 3244 3245 namespace { 3246 // x86-64 Windows target 3247 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3248 public: 3249 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3250 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3251 TLSSupported = false; 3252 WCharType = UnsignedShort; 3253 LongWidth = LongAlign = 32; 3254 DoubleAlign = LongLongAlign = 64; 3255 IntMaxType = SignedLongLong; 3256 UIntMaxType = UnsignedLongLong; 3257 Int64Type = SignedLongLong; 3258 SizeType = UnsignedLongLong; 3259 PtrDiffType = SignedLongLong; 3260 IntPtrType = SignedLongLong; 3261 this->UserLabelPrefix = ""; 3262 } 3263 virtual void getTargetDefines(const LangOptions &Opts, 3264 MacroBuilder &Builder) const { 3265 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3266 Builder.defineMacro("_WIN64"); 3267 } 3268 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3269 return TargetInfo::CharPtrBuiltinVaList; 3270 } 3271 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3272 return (CC == CC_C || 3273 CC == CC_IntelOclBicc || 3274 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3275 } 3276 }; 3277 } // end anonymous namespace 3278 3279 namespace { 3280 // x86-64 Windows Visual Studio target 3281 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 3282 public: 3283 VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple) 3284 : WindowsX86_64TargetInfo(Triple) { 3285 LongDoubleWidth = LongDoubleAlign = 64; 3286 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3287 } 3288 virtual void getTargetDefines(const LangOptions &Opts, 3289 MacroBuilder &Builder) const { 3290 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3291 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3292 Builder.defineMacro("_M_X64"); 3293 Builder.defineMacro("_M_AMD64"); 3294 } 3295 }; 3296 } // end anonymous namespace 3297 3298 namespace { 3299 // x86-64 MinGW target 3300 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3301 public: 3302 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3303 : WindowsX86_64TargetInfo(Triple) {} 3304 virtual void getTargetDefines(const LangOptions &Opts, 3305 MacroBuilder &Builder) const { 3306 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3307 DefineStd(Builder, "WIN64", Opts); 3308 Builder.defineMacro("__MSVCRT__"); 3309 Builder.defineMacro("__MINGW32__"); 3310 Builder.defineMacro("__MINGW64__"); 3311 3312 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3313 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3314 if (Opts.MicrosoftExt) 3315 // Provide "as-is" __declspec. 3316 Builder.defineMacro("__declspec", "__declspec"); 3317 else 3318 // Provide alias of __attribute__ like mingw32-gcc. 3319 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3320 } 3321 }; 3322 } // end anonymous namespace 3323 3324 namespace { 3325 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3326 public: 3327 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3328 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3329 Int64Type = SignedLongLong; 3330 MaxVectorAlign = 256; 3331 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3332 } 3333 }; 3334 } // end anonymous namespace 3335 3336 namespace { 3337 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3338 public: 3339 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3340 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3341 IntMaxType = SignedLongLong; 3342 UIntMaxType = UnsignedLongLong; 3343 Int64Type = SignedLongLong; 3344 } 3345 }; 3346 } // end anonymous namespace 3347 3348 namespace { 3349 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3350 public: 3351 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3352 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3353 IntMaxType = SignedLongLong; 3354 UIntMaxType = UnsignedLongLong; 3355 Int64Type = SignedLongLong; 3356 } 3357 }; 3358 } 3359 3360 namespace { 3361 class AArch64TargetInfo : public TargetInfo { 3362 static const char * const GCCRegNames[]; 3363 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3364 3365 enum FPUModeEnum { 3366 FPUMode, 3367 NeonMode 3368 }; 3369 3370 unsigned FPU; 3371 unsigned Crypto; 3372 static const Builtin::Info BuiltinInfo[]; 3373 3374 public: 3375 AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 3376 BigEndian = false; 3377 LongWidth = LongAlign = 64; 3378 LongDoubleWidth = LongDoubleAlign = 128; 3379 PointerWidth = PointerAlign = 64; 3380 SuitableAlign = 128; 3381 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 3382 3383 WCharType = UnsignedInt; 3384 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3385 3386 // AArch64 backend supports 64-bit operations at the moment. In principle 3387 // 128-bit is possible if register-pairs are used. 3388 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3389 3390 TheCXXABI.set(TargetCXXABI::GenericAArch64); 3391 } 3392 virtual void getTargetDefines(const LangOptions &Opts, 3393 MacroBuilder &Builder) const { 3394 // GCC defines theses currently 3395 Builder.defineMacro("__aarch64__"); 3396 Builder.defineMacro("__AARCH64EL__"); 3397 3398 // ACLE predefines. Many can only have one possible value on v8 AArch64. 3399 Builder.defineMacro("__ARM_ACLE", "200"); 3400 Builder.defineMacro("__ARM_ARCH", "8"); 3401 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 3402 3403 Builder.defineMacro("__ARM_64BIT_STATE"); 3404 Builder.defineMacro("__ARM_PCS_AAPCS64"); 3405 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 3406 3407 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 3408 Builder.defineMacro("__ARM_FEATURE_CLZ"); 3409 Builder.defineMacro("__ARM_FEATURE_FMA"); 3410 Builder.defineMacro("__ARM_FEATURE_DIV"); 3411 3412 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 3413 3414 // 0xe implies support for half, single and double precision operations. 3415 Builder.defineMacro("__ARM_FP", "0xe"); 3416 3417 // PCS specifies this for SysV variants, which is all we support. Other ABIs 3418 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 3419 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 3420 3421 if (Opts.FastMath || Opts.FiniteMathOnly) 3422 Builder.defineMacro("__ARM_FP_FAST"); 3423 3424 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 3425 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 3426 3427 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3428 Opts.ShortWChar ? "2" : "4"); 3429 3430 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3431 Opts.ShortEnums ? "1" : "4"); 3432 3433 if (BigEndian) 3434 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 3435 3436 if (FPU == NeonMode) { 3437 Builder.defineMacro("__ARM_NEON"); 3438 // 64-bit NEON supports half, single and double precision operations. 3439 Builder.defineMacro("__ARM_NEON_FP", "7"); 3440 } 3441 3442 if (Crypto) { 3443 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 3444 } 3445 } 3446 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3447 unsigned &NumRecords) const { 3448 Records = BuiltinInfo; 3449 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin; 3450 } 3451 virtual bool hasFeature(StringRef Feature) const { 3452 return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode); 3453 } 3454 3455 virtual bool setCPU(const std::string &Name) { 3456 return llvm::StringSwitch<bool>(Name) 3457 .Case("generic", true) 3458 .Cases("cortex-a53", "cortex-a57", true) 3459 .Default(false); 3460 } 3461 3462 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 3463 DiagnosticsEngine &Diags) { 3464 FPU = FPUMode; 3465 Crypto = 0; 3466 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3467 if (Features[i] == "+neon") 3468 FPU = NeonMode; 3469 if (Features[i] == "+crypto") 3470 Crypto = 1; 3471 } 3472 return true; 3473 } 3474 3475 virtual void getGCCRegNames(const char *const *&Names, 3476 unsigned &NumNames) const; 3477 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3478 unsigned &NumAliases) const; 3479 3480 virtual bool isCLZForZeroUndef() const { return false; } 3481 3482 virtual bool validateAsmConstraint(const char *&Name, 3483 TargetInfo::ConstraintInfo &Info) const { 3484 switch (*Name) { 3485 default: return false; 3486 case 'w': // An FP/SIMD vector register 3487 Info.setAllowsRegister(); 3488 return true; 3489 case 'I': // Constant that can be used with an ADD instruction 3490 case 'J': // Constant that can be used with a SUB instruction 3491 case 'K': // Constant that can be used with a 32-bit logical instruction 3492 case 'L': // Constant that can be used with a 64-bit logical instruction 3493 case 'M': // Constant that can be used as a 32-bit MOV immediate 3494 case 'N': // Constant that can be used as a 64-bit MOV immediate 3495 case 'Y': // Floating point constant zero 3496 case 'Z': // Integer constant zero 3497 return true; 3498 case 'Q': // A memory reference with base register and no offset 3499 Info.setAllowsMemory(); 3500 return true; 3501 case 'S': // A symbolic address 3502 Info.setAllowsRegister(); 3503 return true; 3504 case 'U': 3505 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 3506 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 3507 // Usa: An absolute symbolic address 3508 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 3509 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 3510 } 3511 } 3512 3513 virtual const char *getClobbers() const { 3514 // There are no AArch64 clobbers shared by all asm statements. 3515 return ""; 3516 } 3517 3518 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3519 return TargetInfo::AArch64ABIBuiltinVaList; 3520 } 3521 }; 3522 3523 const char * const AArch64TargetInfo::GCCRegNames[] = { 3524 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", 3525 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", 3526 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", 3527 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr", 3528 3529 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 3530 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 3531 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 3532 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr", 3533 3534 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", 3535 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", 3536 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", 3537 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31", 3538 3539 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", 3540 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", 3541 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", 3542 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", 3543 3544 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3545 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3546 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3547 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3548 3549 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3550 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3551 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3552 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3553 3554 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3555 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", 3556 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", 3557 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" 3558 }; 3559 3560 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names, 3561 unsigned &NumNames) const { 3562 Names = GCCRegNames; 3563 NumNames = llvm::array_lengthof(GCCRegNames); 3564 } 3565 3566 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 3567 { { "x16" }, "ip0"}, 3568 { { "x17" }, "ip1"}, 3569 { { "x29" }, "fp" }, 3570 { { "x30" }, "lr" } 3571 }; 3572 3573 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3574 unsigned &NumAliases) const { 3575 Aliases = GCCRegAliases; 3576 NumAliases = llvm::array_lengthof(GCCRegAliases); 3577 3578 } 3579 3580 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 3581 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3582 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3583 ALL_LANGUAGES }, 3584 #include "clang/Basic/BuiltinsAArch64.def" 3585 }; 3586 3587 } // end anonymous namespace 3588 3589 namespace { 3590 class ARMTargetInfo : public TargetInfo { 3591 // Possible FPU choices. 3592 enum FPUMode { 3593 VFP2FPU = (1 << 0), 3594 VFP3FPU = (1 << 1), 3595 VFP4FPU = (1 << 2), 3596 NeonFPU = (1 << 3), 3597 FPARMV8 = (1 << 4) 3598 }; 3599 3600 // Possible HWDiv features. 3601 enum HWDivMode { 3602 HWDivThumb = (1 << 0), 3603 HWDivARM = (1 << 1) 3604 }; 3605 3606 static bool FPUModeIsVFP(FPUMode Mode) { 3607 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3608 } 3609 3610 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3611 static const char * const GCCRegNames[]; 3612 3613 std::string ABI, CPU; 3614 3615 enum { 3616 FP_Default, 3617 FP_VFP, 3618 FP_Neon 3619 } FPMath; 3620 3621 unsigned FPU : 5; 3622 3623 unsigned IsAAPCS : 1; 3624 unsigned IsThumb : 1; 3625 unsigned HWDiv : 2; 3626 3627 // Initialized via features. 3628 unsigned SoftFloat : 1; 3629 unsigned SoftFloatABI : 1; 3630 3631 unsigned CRC : 1; 3632 3633 static const Builtin::Info BuiltinInfo[]; 3634 3635 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3636 // On linux, binaries targeting old cpus call functions in libgcc to 3637 // perform atomic operations. The implementation in libgcc then calls into 3638 // the kernel which on armv6 and newer uses ldrex and strex. The net result 3639 // is that if we assume the kernel is at least as recent as the hardware, 3640 // it is safe to use atomic instructions on armv6 and newer. 3641 if (!T.isOSLinux() && 3642 T.getOS() != llvm::Triple::FreeBSD && 3643 T.getOS() != llvm::Triple::NetBSD && 3644 T.getOS() != llvm::Triple::Bitrig) 3645 return false; 3646 StringRef ArchName = T.getArchName(); 3647 if (T.getArch() == llvm::Triple::arm) { 3648 if (!ArchName.startswith("armv")) 3649 return false; 3650 StringRef VersionStr = ArchName.substr(4); 3651 unsigned Version; 3652 if (VersionStr.getAsInteger(10, Version)) 3653 return false; 3654 return Version >= 6; 3655 } 3656 assert(T.getArch() == llvm::Triple::thumb); 3657 if (!ArchName.startswith("thumbv")) 3658 return false; 3659 StringRef VersionStr = ArchName.substr(6); 3660 unsigned Version; 3661 if (VersionStr.getAsInteger(10, Version)) 3662 return false; 3663 return Version >= 7; 3664 } 3665 3666 void setABIAAPCS() { 3667 IsAAPCS = true; 3668 3669 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3670 const llvm::Triple &T = getTriple(); 3671 3672 // size_t is unsigned long on Darwin and netbsd. 3673 if (T.isOSDarwin() || T.getOS() == llvm::Triple::NetBSD) 3674 SizeType = UnsignedLong; 3675 else 3676 SizeType = UnsignedInt; 3677 3678 if (T.getOS() == llvm::Triple::NetBSD) { 3679 WCharType = SignedInt; 3680 } else { 3681 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3682 WCharType = UnsignedInt; 3683 } 3684 3685 UseBitFieldTypeAlignment = true; 3686 3687 ZeroLengthBitfieldBoundary = 0; 3688 3689 if (IsThumb) { 3690 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3691 // so set preferred for small types to 32. 3692 if (T.isOSBinFormatMachO()) 3693 DescriptionString = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3694 "v128:64:128-a:0:32-n32-S64"; 3695 else 3696 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3697 "v128:64:128-a:0:32-n32-S64"; 3698 3699 } else { 3700 if (T.isOSBinFormatMachO()) 3701 DescriptionString = "e-m:o-p:32:32-i64:64-v128:64:128-n32-S64"; 3702 else 3703 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"; 3704 } 3705 3706 // FIXME: Enumerated types are variable width in straight AAPCS. 3707 } 3708 3709 void setABIAPCS() { 3710 const llvm::Triple &T = getTriple(); 3711 3712 IsAAPCS = false; 3713 3714 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3715 3716 // size_t is unsigned int on FreeBSD. 3717 if (T.getOS() == llvm::Triple::FreeBSD) 3718 SizeType = UnsignedInt; 3719 else 3720 SizeType = UnsignedLong; 3721 3722 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3723 WCharType = SignedInt; 3724 3725 // Do not respect the alignment of bit-field types when laying out 3726 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3727 UseBitFieldTypeAlignment = false; 3728 3729 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3730 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3731 /// gcc. 3732 ZeroLengthBitfieldBoundary = 32; 3733 3734 if (IsThumb) { 3735 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3736 // so set preferred for small types to 32. 3737 if (T.isOSBinFormatMachO()) 3738 DescriptionString = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3739 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3740 else 3741 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3742 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3743 } else { 3744 if (T.isOSBinFormatMachO()) 3745 DescriptionString = 3746 "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3747 else 3748 DescriptionString = 3749 "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3750 } 3751 3752 // FIXME: Override "preferred align" for double and long long. 3753 } 3754 3755 public: 3756 ARMTargetInfo(const llvm::Triple &Triple) 3757 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3758 IsAAPCS(true) { 3759 BigEndian = false; 3760 switch (getTriple().getOS()) { 3761 case llvm::Triple::NetBSD: 3762 PtrDiffType = SignedLong; 3763 break; 3764 default: 3765 PtrDiffType = SignedInt; 3766 break; 3767 } 3768 3769 // {} in inline assembly are neon specifiers, not assembly variant 3770 // specifiers. 3771 NoAsmVariants = true; 3772 3773 // FIXME: Should we just treat this as a feature? 3774 IsThumb = getTriple().getArchName().startswith("thumb"); 3775 3776 setABI("aapcs-linux"); 3777 3778 // ARM targets default to using the ARM C++ ABI. 3779 TheCXXABI.set(TargetCXXABI::GenericARM); 3780 3781 // ARM has atomics up to 8 bytes 3782 MaxAtomicPromoteWidth = 64; 3783 if (shouldUseInlineAtomic(getTriple())) 3784 MaxAtomicInlineWidth = 64; 3785 3786 // Do force alignment of members that follow zero length bitfields. If 3787 // the alignment of the zero-length bitfield is greater than the member 3788 // that follows it, `bar', `bar' will be aligned as the type of the 3789 // zero length bitfield. 3790 UseZeroLengthBitfieldAlignment = true; 3791 } 3792 virtual const char *getABI() const { return ABI.c_str(); } 3793 virtual bool setABI(const std::string &Name) { 3794 ABI = Name; 3795 3796 // The defaults (above) are for AAPCS, check if we need to change them. 3797 // 3798 // FIXME: We need support for -meabi... we could just mangle it into the 3799 // name. 3800 if (Name == "apcs-gnu") { 3801 setABIAPCS(); 3802 return true; 3803 } 3804 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 3805 setABIAAPCS(); 3806 return true; 3807 } 3808 return false; 3809 } 3810 3811 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3812 if (IsAAPCS) 3813 Features["aapcs"] = true; 3814 else 3815 Features["apcs"] = true; 3816 3817 StringRef ArchName = getTriple().getArchName(); 3818 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3819 Features["vfp2"] = true; 3820 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3821 CPU == "cortex-a9-mp") { 3822 Features["vfp3"] = true; 3823 Features["neon"] = true; 3824 } 3825 else if (CPU == "cortex-a5") { 3826 Features["vfp4"] = true; 3827 Features["neon"] = true; 3828 } else if (CPU == "swift" || CPU == "cortex-a7" || 3829 CPU == "cortex-a12" || CPU == "cortex-a15" || 3830 CPU == "krait") { 3831 Features["vfp4"] = true; 3832 Features["neon"] = true; 3833 Features["hwdiv"] = true; 3834 Features["hwdiv-arm"] = true; 3835 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 3836 Features["fp-armv8"] = true; 3837 Features["neon"] = true; 3838 Features["hwdiv"] = true; 3839 Features["hwdiv-arm"] = true; 3840 Features["crc"] = true; 3841 } else if (CPU == "cortex-r5" || CPU == "cortex-m3" || 3842 CPU == "cortex-m4" || 3843 // Enable the hwdiv extension for all v8a AArch32 cores by 3844 // default. 3845 ArchName == "armv8a" || ArchName == "armv8" || 3846 ArchName == "thumbv8a" || ArchName == "thumbv8") { 3847 Features["hwdiv"] = true; 3848 Features["hwdiv-arm"] = true; 3849 } 3850 } 3851 3852 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 3853 DiagnosticsEngine &Diags) { 3854 FPU = 0; 3855 CRC = 0; 3856 SoftFloat = SoftFloatABI = false; 3857 HWDiv = 0; 3858 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3859 if (Features[i] == "+soft-float") 3860 SoftFloat = true; 3861 else if (Features[i] == "+soft-float-abi") 3862 SoftFloatABI = true; 3863 else if (Features[i] == "+vfp2") 3864 FPU |= VFP2FPU; 3865 else if (Features[i] == "+vfp3") 3866 FPU |= VFP3FPU; 3867 else if (Features[i] == "+vfp4") 3868 FPU |= VFP4FPU; 3869 else if (Features[i] == "+fp-armv8") 3870 FPU |= FPARMV8; 3871 else if (Features[i] == "+neon") 3872 FPU |= NeonFPU; 3873 else if (Features[i] == "+hwdiv") 3874 HWDiv |= HWDivThumb; 3875 else if (Features[i] == "+hwdiv-arm") 3876 HWDiv |= HWDivARM; 3877 else if (Features[i] == "+crc") 3878 CRC = 1; 3879 } 3880 3881 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 3882 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 3883 return false; 3884 } 3885 3886 if (FPMath == FP_Neon) 3887 Features.push_back("+neonfp"); 3888 else if (FPMath == FP_VFP) 3889 Features.push_back("-neonfp"); 3890 3891 // Remove front-end specific options which the backend handles differently. 3892 std::vector<std::string>::iterator it; 3893 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3894 if (it != Features.end()) 3895 Features.erase(it); 3896 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3897 if (it != Features.end()) 3898 Features.erase(it); 3899 return true; 3900 } 3901 3902 virtual bool hasFeature(StringRef Feature) const { 3903 return llvm::StringSwitch<bool>(Feature) 3904 .Case("arm", true) 3905 .Case("softfloat", SoftFloat) 3906 .Case("thumb", IsThumb) 3907 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 3908 .Case("hwdiv", HWDiv & HWDivThumb) 3909 .Case("hwdiv-arm", HWDiv & HWDivARM) 3910 .Default(false); 3911 } 3912 // FIXME: Should we actually have some table instead of these switches? 3913 static const char *getCPUDefineSuffix(StringRef Name) { 3914 return llvm::StringSwitch<const char*>(Name) 3915 .Cases("arm8", "arm810", "4") 3916 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3917 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3918 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3919 .Case("ep9312", "4T") 3920 .Cases("arm10tdmi", "arm1020t", "5T") 3921 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3922 .Case("arm926ej-s", "5TEJ") 3923 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3924 .Cases("xscale", "iwmmxt", "5TE") 3925 .Case("arm1136j-s", "6J") 3926 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3927 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3928 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3929 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A") 3930 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "7A") 3931 .Cases("cortex-r4", "cortex-r5", "7R") 3932 .Case("swift", "7S") 3933 .Cases("cortex-m3", "cortex-m4", "7M") 3934 .Case("cortex-m0", "6M") 3935 .Cases("cortex-a53", "cortex-a57", "8A") 3936 .Default(0); 3937 } 3938 static const char *getCPUProfile(StringRef Name) { 3939 return llvm::StringSwitch<const char*>(Name) 3940 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 3941 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "A") 3942 .Cases("cortex-a53", "cortex-a57", "A") 3943 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 3944 .Cases("cortex-r4", "cortex-r5", "R") 3945 .Default(""); 3946 } 3947 virtual bool setCPU(const std::string &Name) { 3948 if (!getCPUDefineSuffix(Name)) 3949 return false; 3950 3951 CPU = Name; 3952 return true; 3953 } 3954 virtual bool setFPMath(StringRef Name); 3955 virtual void getTargetDefines(const LangOptions &Opts, 3956 MacroBuilder &Builder) const { 3957 // Target identification. 3958 Builder.defineMacro("__arm"); 3959 Builder.defineMacro("__arm__"); 3960 3961 // Target properties. 3962 Builder.defineMacro("__ARMEL__"); 3963 Builder.defineMacro("__LITTLE_ENDIAN__"); 3964 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3965 3966 StringRef CPUArch = getCPUDefineSuffix(CPU); 3967 unsigned int CPUArchVer; 3968 if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) { 3969 llvm_unreachable("Invalid char for architecture version number"); 3970 } 3971 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 3972 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 3973 StringRef CPUProfile = getCPUProfile(CPU); 3974 if (!CPUProfile.empty()) 3975 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 3976 3977 // Subtarget options. 3978 3979 // FIXME: It's more complicated than this and we don't really support 3980 // interworking. 3981 if (5 <= CPUArchVer && CPUArchVer <= 7) 3982 Builder.defineMacro("__THUMB_INTERWORK__"); 3983 3984 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 3985 // Embedded targets on Darwin follow AAPCS, but not EABI. 3986 if (!getTriple().isOSDarwin()) 3987 Builder.defineMacro("__ARM_EABI__"); 3988 Builder.defineMacro("__ARM_PCS", "1"); 3989 3990 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 3991 Builder.defineMacro("__ARM_PCS_VFP", "1"); 3992 } 3993 3994 if (SoftFloat) 3995 Builder.defineMacro("__SOFTFP__"); 3996 3997 if (CPU == "xscale") 3998 Builder.defineMacro("__XSCALE__"); 3999 4000 if (IsThumb) { 4001 Builder.defineMacro("__THUMBEL__"); 4002 Builder.defineMacro("__thumb__"); 4003 if (CPUArch == "6T2" || CPUArchVer == 7) 4004 Builder.defineMacro("__thumb2__"); 4005 } 4006 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4007 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4008 4009 // Note, this is always on in gcc, even though it doesn't make sense. 4010 Builder.defineMacro("__APCS_32__"); 4011 4012 if (FPUModeIsVFP((FPUMode) FPU)) { 4013 Builder.defineMacro("__VFP_FP__"); 4014 if (FPU & VFP2FPU) 4015 Builder.defineMacro("__ARM_VFPV2__"); 4016 if (FPU & VFP3FPU) 4017 Builder.defineMacro("__ARM_VFPV3__"); 4018 if (FPU & VFP4FPU) 4019 Builder.defineMacro("__ARM_VFPV4__"); 4020 } 4021 4022 // This only gets set when Neon instructions are actually available, unlike 4023 // the VFP define, hence the soft float and arch check. This is subtly 4024 // different from gcc, we follow the intent which was that it should be set 4025 // when Neon instructions are actually available. 4026 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4027 Builder.defineMacro("__ARM_NEON"); 4028 Builder.defineMacro("__ARM_NEON__"); 4029 } 4030 4031 if (CRC) 4032 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4033 4034 if (CPUArchVer >= 6 && CPUArch != "6M") { 4035 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4036 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4037 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4038 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4039 } 4040 } 4041 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4042 unsigned &NumRecords) const { 4043 Records = BuiltinInfo; 4044 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4045 } 4046 virtual bool isCLZForZeroUndef() const { return false; } 4047 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4048 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4049 } 4050 virtual void getGCCRegNames(const char * const *&Names, 4051 unsigned &NumNames) const; 4052 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4053 unsigned &NumAliases) const; 4054 virtual bool validateAsmConstraint(const char *&Name, 4055 TargetInfo::ConstraintInfo &Info) const { 4056 switch (*Name) { 4057 default: break; 4058 case 'l': // r0-r7 4059 case 'h': // r8-r15 4060 case 'w': // VFP Floating point register single precision 4061 case 'P': // VFP Floating point register double precision 4062 Info.setAllowsRegister(); 4063 return true; 4064 case 'Q': // A memory address that is a single base register. 4065 Info.setAllowsMemory(); 4066 return true; 4067 case 'U': // a memory reference... 4068 switch (Name[1]) { 4069 case 'q': // ...ARMV4 ldrsb 4070 case 'v': // ...VFP load/store (reg+constant offset) 4071 case 'y': // ...iWMMXt load/store 4072 case 't': // address valid for load/store opaque types wider 4073 // than 128-bits 4074 case 'n': // valid address for Neon doubleword vector load/store 4075 case 'm': // valid address for Neon element and structure load/store 4076 case 's': // valid address for non-offset loads/stores of quad-word 4077 // values in four ARM registers 4078 Info.setAllowsMemory(); 4079 Name++; 4080 return true; 4081 } 4082 } 4083 return false; 4084 } 4085 virtual std::string convertConstraint(const char *&Constraint) const { 4086 std::string R; 4087 switch (*Constraint) { 4088 case 'U': // Two-character constraint; add "^" hint for later parsing. 4089 R = std::string("^") + std::string(Constraint, 2); 4090 Constraint++; 4091 break; 4092 case 'p': // 'p' should be translated to 'r' by default. 4093 R = std::string("r"); 4094 break; 4095 default: 4096 return std::string(1, *Constraint); 4097 } 4098 return R; 4099 } 4100 virtual bool validateConstraintModifier(StringRef Constraint, 4101 const char Modifier, 4102 unsigned Size) const { 4103 bool isOutput = (Constraint[0] == '='); 4104 bool isInOut = (Constraint[0] == '+'); 4105 4106 // Strip off constraint modifiers. 4107 while (Constraint[0] == '=' || 4108 Constraint[0] == '+' || 4109 Constraint[0] == '&') 4110 Constraint = Constraint.substr(1); 4111 4112 switch (Constraint[0]) { 4113 default: break; 4114 case 'r': { 4115 switch (Modifier) { 4116 default: 4117 return (isInOut || isOutput || Size <= 64); 4118 case 'q': 4119 // A register of size 32 cannot fit a vector type. 4120 return false; 4121 } 4122 } 4123 } 4124 4125 return true; 4126 } 4127 virtual const char *getClobbers() const { 4128 // FIXME: Is this really right? 4129 return ""; 4130 } 4131 4132 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 4133 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4134 } 4135 4136 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 4137 if (RegNo == 0) return 0; 4138 if (RegNo == 1) return 1; 4139 return -1; 4140 } 4141 }; 4142 4143 bool ARMTargetInfo::setFPMath(StringRef Name) { 4144 if (Name == "neon") { 4145 FPMath = FP_Neon; 4146 return true; 4147 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4148 Name == "vfp4") { 4149 FPMath = FP_VFP; 4150 return true; 4151 } 4152 return false; 4153 } 4154 4155 const char * const ARMTargetInfo::GCCRegNames[] = { 4156 // Integer registers 4157 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4158 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4159 4160 // Float registers 4161 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4162 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4163 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4164 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4165 4166 // Double registers 4167 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4168 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4169 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4170 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4171 4172 // Quad registers 4173 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4174 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4175 }; 4176 4177 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4178 unsigned &NumNames) const { 4179 Names = GCCRegNames; 4180 NumNames = llvm::array_lengthof(GCCRegNames); 4181 } 4182 4183 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4184 { { "a1" }, "r0" }, 4185 { { "a2" }, "r1" }, 4186 { { "a3" }, "r2" }, 4187 { { "a4" }, "r3" }, 4188 { { "v1" }, "r4" }, 4189 { { "v2" }, "r5" }, 4190 { { "v3" }, "r6" }, 4191 { { "v4" }, "r7" }, 4192 { { "v5" }, "r8" }, 4193 { { "v6", "rfp" }, "r9" }, 4194 { { "sl" }, "r10" }, 4195 { { "fp" }, "r11" }, 4196 { { "ip" }, "r12" }, 4197 { { "r13" }, "sp" }, 4198 { { "r14" }, "lr" }, 4199 { { "r15" }, "pc" }, 4200 // The S, D and Q registers overlap, but aren't really aliases; we 4201 // don't want to substitute one of these for a different-sized one. 4202 }; 4203 4204 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4205 unsigned &NumAliases) const { 4206 Aliases = GCCRegAliases; 4207 NumAliases = llvm::array_lengthof(GCCRegAliases); 4208 } 4209 4210 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4211 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4212 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4213 ALL_LANGUAGES }, 4214 #include "clang/Basic/BuiltinsARM.def" 4215 }; 4216 } // end anonymous namespace. 4217 4218 namespace { 4219 class DarwinARMTargetInfo : 4220 public DarwinTargetInfo<ARMTargetInfo> { 4221 protected: 4222 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4223 MacroBuilder &Builder) const { 4224 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4225 } 4226 4227 public: 4228 DarwinARMTargetInfo(const llvm::Triple &Triple) 4229 : DarwinTargetInfo<ARMTargetInfo>(Triple) { 4230 HasAlignMac68kSupport = true; 4231 // iOS always has 64-bit atomic instructions. 4232 // FIXME: This should be based off of the target features in ARMTargetInfo. 4233 MaxAtomicInlineWidth = 64; 4234 4235 // Darwin on iOS uses a variant of the ARM C++ ABI. 4236 TheCXXABI.set(TargetCXXABI::iOS); 4237 } 4238 }; 4239 } // end anonymous namespace. 4240 4241 4242 namespace { 4243 // Hexagon abstract base class 4244 class HexagonTargetInfo : public TargetInfo { 4245 static const Builtin::Info BuiltinInfo[]; 4246 static const char * const GCCRegNames[]; 4247 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4248 std::string CPU; 4249 public: 4250 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4251 BigEndian = false; 4252 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 4253 4254 // {} in inline assembly are packet specifiers, not assembly variant 4255 // specifiers. 4256 NoAsmVariants = true; 4257 } 4258 4259 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4260 unsigned &NumRecords) const { 4261 Records = BuiltinInfo; 4262 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4263 } 4264 4265 virtual bool validateAsmConstraint(const char *&Name, 4266 TargetInfo::ConstraintInfo &Info) const { 4267 return true; 4268 } 4269 4270 virtual void getTargetDefines(const LangOptions &Opts, 4271 MacroBuilder &Builder) const; 4272 4273 virtual bool hasFeature(StringRef Feature) const { 4274 return Feature == "hexagon"; 4275 } 4276 4277 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4278 return TargetInfo::CharPtrBuiltinVaList; 4279 } 4280 virtual void getGCCRegNames(const char * const *&Names, 4281 unsigned &NumNames) const; 4282 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4283 unsigned &NumAliases) const; 4284 virtual const char *getClobbers() const { 4285 return ""; 4286 } 4287 4288 static const char *getHexagonCPUSuffix(StringRef Name) { 4289 return llvm::StringSwitch<const char*>(Name) 4290 .Case("hexagonv4", "4") 4291 .Case("hexagonv5", "5") 4292 .Default(0); 4293 } 4294 4295 virtual bool setCPU(const std::string &Name) { 4296 if (!getHexagonCPUSuffix(Name)) 4297 return false; 4298 4299 CPU = Name; 4300 return true; 4301 } 4302 }; 4303 4304 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4305 MacroBuilder &Builder) const { 4306 Builder.defineMacro("qdsp6"); 4307 Builder.defineMacro("__qdsp6", "1"); 4308 Builder.defineMacro("__qdsp6__", "1"); 4309 4310 Builder.defineMacro("hexagon"); 4311 Builder.defineMacro("__hexagon", "1"); 4312 Builder.defineMacro("__hexagon__", "1"); 4313 4314 if(CPU == "hexagonv1") { 4315 Builder.defineMacro("__HEXAGON_V1__"); 4316 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4317 if(Opts.HexagonQdsp6Compat) { 4318 Builder.defineMacro("__QDSP6_V1__"); 4319 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4320 } 4321 } 4322 else if(CPU == "hexagonv2") { 4323 Builder.defineMacro("__HEXAGON_V2__"); 4324 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4325 if(Opts.HexagonQdsp6Compat) { 4326 Builder.defineMacro("__QDSP6_V2__"); 4327 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4328 } 4329 } 4330 else if(CPU == "hexagonv3") { 4331 Builder.defineMacro("__HEXAGON_V3__"); 4332 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4333 if(Opts.HexagonQdsp6Compat) { 4334 Builder.defineMacro("__QDSP6_V3__"); 4335 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4336 } 4337 } 4338 else if(CPU == "hexagonv4") { 4339 Builder.defineMacro("__HEXAGON_V4__"); 4340 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4341 if(Opts.HexagonQdsp6Compat) { 4342 Builder.defineMacro("__QDSP6_V4__"); 4343 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4344 } 4345 } 4346 else if(CPU == "hexagonv5") { 4347 Builder.defineMacro("__HEXAGON_V5__"); 4348 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4349 if(Opts.HexagonQdsp6Compat) { 4350 Builder.defineMacro("__QDSP6_V5__"); 4351 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4352 } 4353 } 4354 } 4355 4356 const char * const HexagonTargetInfo::GCCRegNames[] = { 4357 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4358 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4359 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4360 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4361 "p0", "p1", "p2", "p3", 4362 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4363 }; 4364 4365 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4366 unsigned &NumNames) const { 4367 Names = GCCRegNames; 4368 NumNames = llvm::array_lengthof(GCCRegNames); 4369 } 4370 4371 4372 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4373 { { "sp" }, "r29" }, 4374 { { "fp" }, "r30" }, 4375 { { "lr" }, "r31" }, 4376 }; 4377 4378 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4379 unsigned &NumAliases) const { 4380 Aliases = GCCRegAliases; 4381 NumAliases = llvm::array_lengthof(GCCRegAliases); 4382 } 4383 4384 4385 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4386 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4387 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4388 ALL_LANGUAGES }, 4389 #include "clang/Basic/BuiltinsHexagon.def" 4390 }; 4391 } 4392 4393 4394 namespace { 4395 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4396 class SparcTargetInfo : public TargetInfo { 4397 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4398 static const char * const GCCRegNames[]; 4399 bool SoftFloat; 4400 public: 4401 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4402 4403 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 4404 DiagnosticsEngine &Diags) { 4405 SoftFloat = false; 4406 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4407 if (Features[i] == "+soft-float") 4408 SoftFloat = true; 4409 return true; 4410 } 4411 virtual void getTargetDefines(const LangOptions &Opts, 4412 MacroBuilder &Builder) const { 4413 DefineStd(Builder, "sparc", Opts); 4414 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4415 4416 if (SoftFloat) 4417 Builder.defineMacro("SOFT_FLOAT", "1"); 4418 } 4419 4420 virtual bool hasFeature(StringRef Feature) const { 4421 return llvm::StringSwitch<bool>(Feature) 4422 .Case("softfloat", SoftFloat) 4423 .Case("sparc", true) 4424 .Default(false); 4425 } 4426 4427 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4428 unsigned &NumRecords) const { 4429 // FIXME: Implement! 4430 } 4431 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4432 return TargetInfo::VoidPtrBuiltinVaList; 4433 } 4434 virtual void getGCCRegNames(const char * const *&Names, 4435 unsigned &NumNames) const; 4436 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4437 unsigned &NumAliases) const; 4438 virtual bool validateAsmConstraint(const char *&Name, 4439 TargetInfo::ConstraintInfo &info) const { 4440 // FIXME: Implement! 4441 return false; 4442 } 4443 virtual const char *getClobbers() const { 4444 // FIXME: Implement! 4445 return ""; 4446 } 4447 }; 4448 4449 const char * const SparcTargetInfo::GCCRegNames[] = { 4450 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4451 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4452 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4453 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4454 }; 4455 4456 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4457 unsigned &NumNames) const { 4458 Names = GCCRegNames; 4459 NumNames = llvm::array_lengthof(GCCRegNames); 4460 } 4461 4462 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4463 { { "g0" }, "r0" }, 4464 { { "g1" }, "r1" }, 4465 { { "g2" }, "r2" }, 4466 { { "g3" }, "r3" }, 4467 { { "g4" }, "r4" }, 4468 { { "g5" }, "r5" }, 4469 { { "g6" }, "r6" }, 4470 { { "g7" }, "r7" }, 4471 { { "o0" }, "r8" }, 4472 { { "o1" }, "r9" }, 4473 { { "o2" }, "r10" }, 4474 { { "o3" }, "r11" }, 4475 { { "o4" }, "r12" }, 4476 { { "o5" }, "r13" }, 4477 { { "o6", "sp" }, "r14" }, 4478 { { "o7" }, "r15" }, 4479 { { "l0" }, "r16" }, 4480 { { "l1" }, "r17" }, 4481 { { "l2" }, "r18" }, 4482 { { "l3" }, "r19" }, 4483 { { "l4" }, "r20" }, 4484 { { "l5" }, "r21" }, 4485 { { "l6" }, "r22" }, 4486 { { "l7" }, "r23" }, 4487 { { "i0" }, "r24" }, 4488 { { "i1" }, "r25" }, 4489 { { "i2" }, "r26" }, 4490 { { "i3" }, "r27" }, 4491 { { "i4" }, "r28" }, 4492 { { "i5" }, "r29" }, 4493 { { "i6", "fp" }, "r30" }, 4494 { { "i7" }, "r31" }, 4495 }; 4496 4497 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4498 unsigned &NumAliases) const { 4499 Aliases = GCCRegAliases; 4500 NumAliases = llvm::array_lengthof(GCCRegAliases); 4501 } 4502 4503 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 4504 class SparcV8TargetInfo : public SparcTargetInfo { 4505 public: 4506 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4507 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 4508 } 4509 4510 virtual void getTargetDefines(const LangOptions &Opts, 4511 MacroBuilder &Builder) const { 4512 SparcTargetInfo::getTargetDefines(Opts, Builder); 4513 Builder.defineMacro("__sparcv8"); 4514 } 4515 }; 4516 4517 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 4518 class SparcV9TargetInfo : public SparcTargetInfo { 4519 public: 4520 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4521 // FIXME: Support Sparc quad-precision long double? 4522 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 4523 // This is an LP64 platform. 4524 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4525 4526 // OpenBSD uses long long for int64_t and intmax_t. 4527 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 4528 IntMaxType = SignedLongLong; 4529 UIntMaxType = UnsignedLongLong; 4530 } else { 4531 IntMaxType = SignedLong; 4532 UIntMaxType = UnsignedLong; 4533 } 4534 Int64Type = IntMaxType; 4535 4536 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 4537 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 4538 LongDoubleWidth = 128; 4539 LongDoubleAlign = 128; 4540 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4541 } 4542 4543 virtual void getTargetDefines(const LangOptions &Opts, 4544 MacroBuilder &Builder) const { 4545 SparcTargetInfo::getTargetDefines(Opts, Builder); 4546 Builder.defineMacro("__sparcv9"); 4547 Builder.defineMacro("__arch64__"); 4548 // Solaris and its derivative AuroraUX don't need these variants, but the 4549 // BSDs do. 4550 if (getTriple().getOS() != llvm::Triple::Solaris && 4551 getTriple().getOS() != llvm::Triple::AuroraUX) { 4552 Builder.defineMacro("__sparc64__"); 4553 Builder.defineMacro("__sparc_v9__"); 4554 Builder.defineMacro("__sparcv9__"); 4555 } 4556 } 4557 }; 4558 4559 } // end anonymous namespace. 4560 4561 namespace { 4562 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 4563 public: 4564 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 4565 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 4566 SizeType = UnsignedInt; 4567 PtrDiffType = SignedInt; 4568 } 4569 }; 4570 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 4571 public: 4572 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 4573 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 4574 SizeType = UnsignedInt; 4575 PtrDiffType = SignedInt; 4576 } 4577 }; 4578 } // end anonymous namespace. 4579 4580 namespace { 4581 class SystemZTargetInfo : public TargetInfo { 4582 static const char *const GCCRegNames[]; 4583 4584 public: 4585 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4586 TLSSupported = true; 4587 IntWidth = IntAlign = 32; 4588 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 4589 PointerWidth = PointerAlign = 64; 4590 LongDoubleWidth = 128; 4591 LongDoubleAlign = 64; 4592 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4593 MinGlobalAlign = 16; 4594 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 4595 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4596 } 4597 virtual void getTargetDefines(const LangOptions &Opts, 4598 MacroBuilder &Builder) const { 4599 Builder.defineMacro("__s390__"); 4600 Builder.defineMacro("__s390x__"); 4601 Builder.defineMacro("__zarch__"); 4602 Builder.defineMacro("__LONG_DOUBLE_128__"); 4603 } 4604 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4605 unsigned &NumRecords) const { 4606 // FIXME: Implement. 4607 Records = 0; 4608 NumRecords = 0; 4609 } 4610 4611 virtual void getGCCRegNames(const char *const *&Names, 4612 unsigned &NumNames) const; 4613 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4614 unsigned &NumAliases) const { 4615 // No aliases. 4616 Aliases = 0; 4617 NumAliases = 0; 4618 } 4619 virtual bool validateAsmConstraint(const char *&Name, 4620 TargetInfo::ConstraintInfo &info) const; 4621 virtual const char *getClobbers() const { 4622 // FIXME: Is this really right? 4623 return ""; 4624 } 4625 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4626 return TargetInfo::SystemZBuiltinVaList; 4627 } 4628 virtual bool setCPU(const std::string &Name) { 4629 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4630 .Case("z10", true) 4631 .Case("z196", true) 4632 .Case("zEC12", true) 4633 .Default(false); 4634 4635 // No need to store the CPU yet. There aren't any CPU-specific 4636 // macros to define. 4637 return CPUKnown; 4638 } 4639 }; 4640 4641 const char *const SystemZTargetInfo::GCCRegNames[] = { 4642 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4643 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4644 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 4645 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 4646 }; 4647 4648 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 4649 unsigned &NumNames) const { 4650 Names = GCCRegNames; 4651 NumNames = llvm::array_lengthof(GCCRegNames); 4652 } 4653 4654 bool SystemZTargetInfo:: 4655 validateAsmConstraint(const char *&Name, 4656 TargetInfo::ConstraintInfo &Info) const { 4657 switch (*Name) { 4658 default: 4659 return false; 4660 4661 case 'a': // Address register 4662 case 'd': // Data register (equivalent to 'r') 4663 case 'f': // Floating-point register 4664 Info.setAllowsRegister(); 4665 return true; 4666 4667 case 'I': // Unsigned 8-bit constant 4668 case 'J': // Unsigned 12-bit constant 4669 case 'K': // Signed 16-bit constant 4670 case 'L': // Signed 20-bit displacement (on all targets we support) 4671 case 'M': // 0x7fffffff 4672 return true; 4673 4674 case 'Q': // Memory with base and unsigned 12-bit displacement 4675 case 'R': // Likewise, plus an index 4676 case 'S': // Memory with base and signed 20-bit displacement 4677 case 'T': // Likewise, plus an index 4678 Info.setAllowsMemory(); 4679 return true; 4680 } 4681 } 4682 } 4683 4684 namespace { 4685 class MSP430TargetInfo : public TargetInfo { 4686 static const char * const GCCRegNames[]; 4687 public: 4688 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4689 BigEndian = false; 4690 TLSSupported = false; 4691 IntWidth = 16; IntAlign = 16; 4692 LongWidth = 32; LongLongWidth = 64; 4693 LongAlign = LongLongAlign = 16; 4694 PointerWidth = 16; PointerAlign = 16; 4695 SuitableAlign = 16; 4696 SizeType = UnsignedInt; 4697 IntMaxType = SignedLongLong; 4698 UIntMaxType = UnsignedLongLong; 4699 IntPtrType = SignedInt; 4700 PtrDiffType = SignedInt; 4701 SigAtomicType = SignedLong; 4702 DescriptionString = "e-m:e-p:16:16-i32:16:32-n8:16"; 4703 } 4704 virtual void getTargetDefines(const LangOptions &Opts, 4705 MacroBuilder &Builder) const { 4706 Builder.defineMacro("MSP430"); 4707 Builder.defineMacro("__MSP430__"); 4708 // FIXME: defines for different 'flavours' of MCU 4709 } 4710 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4711 unsigned &NumRecords) const { 4712 // FIXME: Implement. 4713 Records = 0; 4714 NumRecords = 0; 4715 } 4716 virtual bool hasFeature(StringRef Feature) const { 4717 return Feature == "msp430"; 4718 } 4719 virtual void getGCCRegNames(const char * const *&Names, 4720 unsigned &NumNames) const; 4721 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4722 unsigned &NumAliases) const { 4723 // No aliases. 4724 Aliases = 0; 4725 NumAliases = 0; 4726 } 4727 virtual bool validateAsmConstraint(const char *&Name, 4728 TargetInfo::ConstraintInfo &info) const { 4729 // No target constraints for now. 4730 return false; 4731 } 4732 virtual const char *getClobbers() const { 4733 // FIXME: Is this really right? 4734 return ""; 4735 } 4736 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4737 // FIXME: implement 4738 return TargetInfo::CharPtrBuiltinVaList; 4739 } 4740 }; 4741 4742 const char * const MSP430TargetInfo::GCCRegNames[] = { 4743 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4744 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 4745 }; 4746 4747 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 4748 unsigned &NumNames) const { 4749 Names = GCCRegNames; 4750 NumNames = llvm::array_lengthof(GCCRegNames); 4751 } 4752 } 4753 4754 namespace { 4755 4756 // LLVM and Clang cannot be used directly to output native binaries for 4757 // target, but is used to compile C code to llvm bitcode with correct 4758 // type and alignment information. 4759 // 4760 // TCE uses the llvm bitcode as input and uses it for generating customized 4761 // target processor and program binary. TCE co-design environment is 4762 // publicly available in http://tce.cs.tut.fi 4763 4764 static const unsigned TCEOpenCLAddrSpaceMap[] = { 4765 3, // opencl_global 4766 4, // opencl_local 4767 5, // opencl_constant 4768 0, // cuda_device 4769 0, // cuda_constant 4770 0 // cuda_shared 4771 }; 4772 4773 class TCETargetInfo : public TargetInfo{ 4774 public: 4775 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4776 TLSSupported = false; 4777 IntWidth = 32; 4778 LongWidth = LongLongWidth = 32; 4779 PointerWidth = 32; 4780 IntAlign = 32; 4781 LongAlign = LongLongAlign = 32; 4782 PointerAlign = 32; 4783 SuitableAlign = 32; 4784 SizeType = UnsignedInt; 4785 IntMaxType = SignedLong; 4786 UIntMaxType = UnsignedLong; 4787 IntPtrType = SignedInt; 4788 PtrDiffType = SignedInt; 4789 FloatWidth = 32; 4790 FloatAlign = 32; 4791 DoubleWidth = 32; 4792 DoubleAlign = 32; 4793 LongDoubleWidth = 32; 4794 LongDoubleAlign = 32; 4795 FloatFormat = &llvm::APFloat::IEEEsingle; 4796 DoubleFormat = &llvm::APFloat::IEEEsingle; 4797 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 4798 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 4799 "-f64:32-v64:32-v128:32-a:0:32-n32"; 4800 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 4801 UseAddrSpaceMapMangling = true; 4802 } 4803 4804 virtual void getTargetDefines(const LangOptions &Opts, 4805 MacroBuilder &Builder) const { 4806 DefineStd(Builder, "tce", Opts); 4807 Builder.defineMacro("__TCE__"); 4808 Builder.defineMacro("__TCE_V1__"); 4809 } 4810 virtual bool hasFeature(StringRef Feature) const { 4811 return Feature == "tce"; 4812 } 4813 4814 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4815 unsigned &NumRecords) const {} 4816 virtual const char *getClobbers() const { 4817 return ""; 4818 } 4819 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4820 return TargetInfo::VoidPtrBuiltinVaList; 4821 } 4822 virtual void getGCCRegNames(const char * const *&Names, 4823 unsigned &NumNames) const {} 4824 virtual bool validateAsmConstraint(const char *&Name, 4825 TargetInfo::ConstraintInfo &info) const { 4826 return true; 4827 } 4828 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4829 unsigned &NumAliases) const {} 4830 }; 4831 } 4832 4833 namespace { 4834 class MipsTargetInfoBase : public TargetInfo { 4835 virtual void setDescriptionString() = 0; 4836 4837 static const Builtin::Info BuiltinInfo[]; 4838 std::string CPU; 4839 bool IsMips16; 4840 bool IsMicromips; 4841 bool IsNan2008; 4842 bool IsSingleFloat; 4843 enum MipsFloatABI { 4844 HardFloat, SoftFloat 4845 } FloatABI; 4846 enum DspRevEnum { 4847 NoDSP, DSP1, DSP2 4848 } DspRev; 4849 bool HasMSA; 4850 4851 protected: 4852 bool HasFP64; 4853 std::string ABI; 4854 4855 public: 4856 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 4857 const std::string &CPUStr) 4858 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 4859 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 4860 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 4861 4862 virtual const char *getABI() const { return ABI.c_str(); } 4863 virtual bool setABI(const std::string &Name) = 0; 4864 virtual bool setCPU(const std::string &Name) { 4865 CPU = Name; 4866 return true; 4867 } 4868 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 4869 Features[ABI] = true; 4870 Features[CPU] = true; 4871 } 4872 4873 virtual void getTargetDefines(const LangOptions &Opts, 4874 MacroBuilder &Builder) const { 4875 DefineStd(Builder, "mips", Opts); 4876 Builder.defineMacro("_mips"); 4877 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4878 4879 switch (FloatABI) { 4880 case HardFloat: 4881 Builder.defineMacro("__mips_hard_float", Twine(1)); 4882 break; 4883 case SoftFloat: 4884 Builder.defineMacro("__mips_soft_float", Twine(1)); 4885 break; 4886 } 4887 4888 if (IsSingleFloat) 4889 Builder.defineMacro("__mips_single_float", Twine(1)); 4890 4891 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 4892 Builder.defineMacro("_MIPS_FPSET", 4893 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 4894 4895 if (IsMips16) 4896 Builder.defineMacro("__mips16", Twine(1)); 4897 4898 if (IsMicromips) 4899 Builder.defineMacro("__mips_micromips", Twine(1)); 4900 4901 if (IsNan2008) 4902 Builder.defineMacro("__mips_nan2008", Twine(1)); 4903 4904 switch (DspRev) { 4905 default: 4906 break; 4907 case DSP1: 4908 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 4909 Builder.defineMacro("__mips_dsp", Twine(1)); 4910 break; 4911 case DSP2: 4912 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 4913 Builder.defineMacro("__mips_dspr2", Twine(1)); 4914 Builder.defineMacro("__mips_dsp", Twine(1)); 4915 break; 4916 } 4917 4918 if (HasMSA) 4919 Builder.defineMacro("__mips_msa", Twine(1)); 4920 4921 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 4922 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 4923 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 4924 4925 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 4926 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 4927 } 4928 4929 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4930 unsigned &NumRecords) const { 4931 Records = BuiltinInfo; 4932 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 4933 } 4934 virtual bool hasFeature(StringRef Feature) const { 4935 return llvm::StringSwitch<bool>(Feature) 4936 .Case("mips", true) 4937 .Case("fp64", HasFP64) 4938 .Default(false); 4939 } 4940 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4941 return TargetInfo::VoidPtrBuiltinVaList; 4942 } 4943 virtual void getGCCRegNames(const char * const *&Names, 4944 unsigned &NumNames) const { 4945 static const char *const GCCRegNames[] = { 4946 // CPU register names 4947 // Must match second column of GCCRegAliases 4948 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 4949 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 4950 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 4951 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 4952 // Floating point register names 4953 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 4954 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 4955 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 4956 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 4957 // Hi/lo and condition register names 4958 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 4959 "$fcc5","$fcc6","$fcc7", 4960 // MSA register names 4961 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 4962 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 4963 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 4964 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 4965 // MSA control register names 4966 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 4967 "$msarequest", "$msamap", "$msaunmap" 4968 }; 4969 Names = GCCRegNames; 4970 NumNames = llvm::array_lengthof(GCCRegNames); 4971 } 4972 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4973 unsigned &NumAliases) const = 0; 4974 virtual bool validateAsmConstraint(const char *&Name, 4975 TargetInfo::ConstraintInfo &Info) const { 4976 switch (*Name) { 4977 default: 4978 return false; 4979 4980 case 'r': // CPU registers. 4981 case 'd': // Equivalent to "r" unless generating MIPS16 code. 4982 case 'y': // Equivalent to "r", backwards compatibility only. 4983 case 'f': // floating-point registers. 4984 case 'c': // $25 for indirect jumps 4985 case 'l': // lo register 4986 case 'x': // hilo register pair 4987 Info.setAllowsRegister(); 4988 return true; 4989 case 'R': // An address that can be used in a non-macro load or store 4990 Info.setAllowsMemory(); 4991 return true; 4992 } 4993 } 4994 4995 virtual const char *getClobbers() const { 4996 // FIXME: Implement! 4997 return ""; 4998 } 4999 5000 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 5001 DiagnosticsEngine &Diags) { 5002 IsMips16 = false; 5003 IsMicromips = false; 5004 IsNan2008 = false; 5005 IsSingleFloat = false; 5006 FloatABI = HardFloat; 5007 DspRev = NoDSP; 5008 HasFP64 = ABI == "n32" || ABI == "n64" || ABI == "64"; 5009 5010 for (std::vector<std::string>::iterator it = Features.begin(), 5011 ie = Features.end(); it != ie; ++it) { 5012 if (*it == "+single-float") 5013 IsSingleFloat = true; 5014 else if (*it == "+soft-float") 5015 FloatABI = SoftFloat; 5016 else if (*it == "+mips16") 5017 IsMips16 = true; 5018 else if (*it == "+micromips") 5019 IsMicromips = true; 5020 else if (*it == "+dsp") 5021 DspRev = std::max(DspRev, DSP1); 5022 else if (*it == "+dspr2") 5023 DspRev = std::max(DspRev, DSP2); 5024 else if (*it == "+msa") 5025 HasMSA = true; 5026 else if (*it == "+fp64") 5027 HasFP64 = true; 5028 else if (*it == "-fp64") 5029 HasFP64 = false; 5030 else if (*it == "+nan2008") 5031 IsNan2008 = true; 5032 } 5033 5034 // Remove front-end specific options. 5035 std::vector<std::string>::iterator it = 5036 std::find(Features.begin(), Features.end(), "+soft-float"); 5037 if (it != Features.end()) 5038 Features.erase(it); 5039 it = std::find(Features.begin(), Features.end(), "+nan2008"); 5040 if (it != Features.end()) 5041 Features.erase(it); 5042 5043 setDescriptionString(); 5044 5045 return true; 5046 } 5047 5048 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 5049 if (RegNo == 0) return 4; 5050 if (RegNo == 1) return 5; 5051 return -1; 5052 } 5053 }; 5054 5055 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5056 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5057 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5058 ALL_LANGUAGES }, 5059 #include "clang/Basic/BuiltinsMips.def" 5060 }; 5061 5062 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5063 public: 5064 Mips32TargetInfoBase(const llvm::Triple &Triple) 5065 : MipsTargetInfoBase(Triple, "o32", "mips32") { 5066 SizeType = UnsignedInt; 5067 PtrDiffType = SignedInt; 5068 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5069 } 5070 virtual bool setABI(const std::string &Name) { 5071 if ((Name == "o32") || (Name == "eabi")) { 5072 ABI = Name; 5073 return true; 5074 } else if (Name == "32") { 5075 ABI = "o32"; 5076 return true; 5077 } else 5078 return false; 5079 } 5080 virtual void getTargetDefines(const LangOptions &Opts, 5081 MacroBuilder &Builder) const { 5082 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5083 5084 if (ABI == "o32") { 5085 Builder.defineMacro("__mips_o32"); 5086 Builder.defineMacro("_ABIO32", "1"); 5087 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5088 } 5089 else if (ABI == "eabi") 5090 Builder.defineMacro("__mips_eabi"); 5091 else 5092 llvm_unreachable("Invalid ABI for Mips32."); 5093 } 5094 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5095 unsigned &NumAliases) const { 5096 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5097 { { "at" }, "$1" }, 5098 { { "v0" }, "$2" }, 5099 { { "v1" }, "$3" }, 5100 { { "a0" }, "$4" }, 5101 { { "a1" }, "$5" }, 5102 { { "a2" }, "$6" }, 5103 { { "a3" }, "$7" }, 5104 { { "t0" }, "$8" }, 5105 { { "t1" }, "$9" }, 5106 { { "t2" }, "$10" }, 5107 { { "t3" }, "$11" }, 5108 { { "t4" }, "$12" }, 5109 { { "t5" }, "$13" }, 5110 { { "t6" }, "$14" }, 5111 { { "t7" }, "$15" }, 5112 { { "s0" }, "$16" }, 5113 { { "s1" }, "$17" }, 5114 { { "s2" }, "$18" }, 5115 { { "s3" }, "$19" }, 5116 { { "s4" }, "$20" }, 5117 { { "s5" }, "$21" }, 5118 { { "s6" }, "$22" }, 5119 { { "s7" }, "$23" }, 5120 { { "t8" }, "$24" }, 5121 { { "t9" }, "$25" }, 5122 { { "k0" }, "$26" }, 5123 { { "k1" }, "$27" }, 5124 { { "gp" }, "$28" }, 5125 { { "sp","$sp" }, "$29" }, 5126 { { "fp","$fp" }, "$30" }, 5127 { { "ra" }, "$31" } 5128 }; 5129 Aliases = GCCRegAliases; 5130 NumAliases = llvm::array_lengthof(GCCRegAliases); 5131 } 5132 }; 5133 5134 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5135 virtual void setDescriptionString() { 5136 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5137 } 5138 5139 public: 5140 Mips32EBTargetInfo(const llvm::Triple &Triple) 5141 : Mips32TargetInfoBase(Triple) { 5142 } 5143 virtual void getTargetDefines(const LangOptions &Opts, 5144 MacroBuilder &Builder) const { 5145 DefineStd(Builder, "MIPSEB", Opts); 5146 Builder.defineMacro("_MIPSEB"); 5147 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5148 } 5149 }; 5150 5151 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5152 virtual void setDescriptionString() { 5153 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5154 } 5155 5156 public: 5157 Mips32ELTargetInfo(const llvm::Triple &Triple) 5158 : Mips32TargetInfoBase(Triple) { 5159 BigEndian = false; 5160 } 5161 virtual void getTargetDefines(const LangOptions &Opts, 5162 MacroBuilder &Builder) const { 5163 DefineStd(Builder, "MIPSEL", Opts); 5164 Builder.defineMacro("_MIPSEL"); 5165 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5166 } 5167 }; 5168 5169 class Mips64TargetInfoBase : public MipsTargetInfoBase { 5170 public: 5171 Mips64TargetInfoBase(const llvm::Triple &Triple) 5172 : MipsTargetInfoBase(Triple, "n64", "mips64") { 5173 LongWidth = LongAlign = 64; 5174 PointerWidth = PointerAlign = 64; 5175 LongDoubleWidth = LongDoubleAlign = 128; 5176 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5177 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5178 LongDoubleWidth = LongDoubleAlign = 64; 5179 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5180 } 5181 SuitableAlign = 128; 5182 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5183 } 5184 virtual bool setABI(const std::string &Name) { 5185 if (Name == "n32") { 5186 LongWidth = LongAlign = 32; 5187 PointerWidth = PointerAlign = 32; 5188 ABI = Name; 5189 return true; 5190 } else if (Name == "n64") { 5191 ABI = Name; 5192 return true; 5193 } else if (Name == "64") { 5194 ABI = "n64"; 5195 return true; 5196 } else 5197 return false; 5198 } 5199 virtual void getTargetDefines(const LangOptions &Opts, 5200 MacroBuilder &Builder) const { 5201 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5202 5203 Builder.defineMacro("__mips64"); 5204 Builder.defineMacro("__mips64__"); 5205 5206 if (ABI == "n32") { 5207 Builder.defineMacro("__mips_n32"); 5208 Builder.defineMacro("_ABIN32", "2"); 5209 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5210 } 5211 else if (ABI == "n64") { 5212 Builder.defineMacro("__mips_n64"); 5213 Builder.defineMacro("_ABI64", "3"); 5214 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5215 } 5216 else 5217 llvm_unreachable("Invalid ABI for Mips64."); 5218 } 5219 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5220 unsigned &NumAliases) const { 5221 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5222 { { "at" }, "$1" }, 5223 { { "v0" }, "$2" }, 5224 { { "v1" }, "$3" }, 5225 { { "a0" }, "$4" }, 5226 { { "a1" }, "$5" }, 5227 { { "a2" }, "$6" }, 5228 { { "a3" }, "$7" }, 5229 { { "a4" }, "$8" }, 5230 { { "a5" }, "$9" }, 5231 { { "a6" }, "$10" }, 5232 { { "a7" }, "$11" }, 5233 { { "t0" }, "$12" }, 5234 { { "t1" }, "$13" }, 5235 { { "t2" }, "$14" }, 5236 { { "t3" }, "$15" }, 5237 { { "s0" }, "$16" }, 5238 { { "s1" }, "$17" }, 5239 { { "s2" }, "$18" }, 5240 { { "s3" }, "$19" }, 5241 { { "s4" }, "$20" }, 5242 { { "s5" }, "$21" }, 5243 { { "s6" }, "$22" }, 5244 { { "s7" }, "$23" }, 5245 { { "t8" }, "$24" }, 5246 { { "t9" }, "$25" }, 5247 { { "k0" }, "$26" }, 5248 { { "k1" }, "$27" }, 5249 { { "gp" }, "$28" }, 5250 { { "sp","$sp" }, "$29" }, 5251 { { "fp","$fp" }, "$30" }, 5252 { { "ra" }, "$31" } 5253 }; 5254 Aliases = GCCRegAliases; 5255 NumAliases = llvm::array_lengthof(GCCRegAliases); 5256 } 5257 }; 5258 5259 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5260 virtual void setDescriptionString() { 5261 if (ABI == "n32") 5262 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5263 else 5264 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5265 5266 } 5267 5268 public: 5269 Mips64EBTargetInfo(const llvm::Triple &Triple) 5270 : Mips64TargetInfoBase(Triple) {} 5271 virtual void getTargetDefines(const LangOptions &Opts, 5272 MacroBuilder &Builder) const { 5273 DefineStd(Builder, "MIPSEB", Opts); 5274 Builder.defineMacro("_MIPSEB"); 5275 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5276 } 5277 }; 5278 5279 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5280 virtual void setDescriptionString() { 5281 if (ABI == "n32") 5282 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5283 else 5284 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5285 } 5286 public: 5287 Mips64ELTargetInfo(const llvm::Triple &Triple) 5288 : Mips64TargetInfoBase(Triple) { 5289 // Default ABI is n64. 5290 BigEndian = false; 5291 } 5292 virtual void getTargetDefines(const LangOptions &Opts, 5293 MacroBuilder &Builder) const { 5294 DefineStd(Builder, "MIPSEL", Opts); 5295 Builder.defineMacro("_MIPSEL"); 5296 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5297 } 5298 }; 5299 } // end anonymous namespace. 5300 5301 namespace { 5302 class PNaClTargetInfo : public TargetInfo { 5303 public: 5304 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5305 BigEndian = false; 5306 this->UserLabelPrefix = ""; 5307 this->LongAlign = 32; 5308 this->LongWidth = 32; 5309 this->PointerAlign = 32; 5310 this->PointerWidth = 32; 5311 this->IntMaxType = TargetInfo::SignedLongLong; 5312 this->UIntMaxType = TargetInfo::UnsignedLongLong; 5313 this->Int64Type = TargetInfo::SignedLongLong; 5314 this->DoubleAlign = 64; 5315 this->LongDoubleWidth = 64; 5316 this->LongDoubleAlign = 64; 5317 this->SizeType = TargetInfo::UnsignedInt; 5318 this->PtrDiffType = TargetInfo::SignedInt; 5319 this->IntPtrType = TargetInfo::SignedInt; 5320 this->RegParmMax = 0; // Disallow regparm 5321 } 5322 5323 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 5324 } 5325 virtual void getArchDefines(const LangOptions &Opts, 5326 MacroBuilder &Builder) const { 5327 Builder.defineMacro("__le32__"); 5328 Builder.defineMacro("__pnacl__"); 5329 } 5330 virtual void getTargetDefines(const LangOptions &Opts, 5331 MacroBuilder &Builder) const { 5332 Builder.defineMacro("__LITTLE_ENDIAN__"); 5333 getArchDefines(Opts, Builder); 5334 } 5335 virtual bool hasFeature(StringRef Feature) const { 5336 return Feature == "pnacl"; 5337 } 5338 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5339 unsigned &NumRecords) const { 5340 } 5341 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5342 return TargetInfo::PNaClABIBuiltinVaList; 5343 } 5344 virtual void getGCCRegNames(const char * const *&Names, 5345 unsigned &NumNames) const; 5346 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5347 unsigned &NumAliases) const; 5348 virtual bool validateAsmConstraint(const char *&Name, 5349 TargetInfo::ConstraintInfo &Info) const { 5350 return false; 5351 } 5352 5353 virtual const char *getClobbers() const { 5354 return ""; 5355 } 5356 }; 5357 5358 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5359 unsigned &NumNames) const { 5360 Names = NULL; 5361 NumNames = 0; 5362 } 5363 5364 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5365 unsigned &NumAliases) const { 5366 Aliases = NULL; 5367 NumAliases = 0; 5368 } 5369 } // end anonymous namespace. 5370 5371 namespace { 5372 static const unsigned SPIRAddrSpaceMap[] = { 5373 1, // opencl_global 5374 3, // opencl_local 5375 2, // opencl_constant 5376 0, // cuda_device 5377 0, // cuda_constant 5378 0 // cuda_shared 5379 }; 5380 class SPIRTargetInfo : public TargetInfo { 5381 public: 5382 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5383 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5384 "SPIR target must use unknown OS"); 5385 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5386 "SPIR target must use unknown environment type"); 5387 BigEndian = false; 5388 TLSSupported = false; 5389 LongWidth = LongAlign = 64; 5390 AddrSpaceMap = &SPIRAddrSpaceMap; 5391 UseAddrSpaceMapMangling = true; 5392 // Define available target features 5393 // These must be defined in sorted order! 5394 NoAsmVariants = true; 5395 } 5396 virtual void getTargetDefines(const LangOptions &Opts, 5397 MacroBuilder &Builder) const { 5398 DefineStd(Builder, "SPIR", Opts); 5399 } 5400 virtual bool hasFeature(StringRef Feature) const { 5401 return Feature == "spir"; 5402 } 5403 5404 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5405 unsigned &NumRecords) const {} 5406 virtual const char *getClobbers() const { 5407 return ""; 5408 } 5409 virtual void getGCCRegNames(const char * const *&Names, 5410 unsigned &NumNames) const {} 5411 virtual bool validateAsmConstraint(const char *&Name, 5412 TargetInfo::ConstraintInfo &info) const { 5413 return true; 5414 } 5415 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5416 unsigned &NumAliases) const {} 5417 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5418 return TargetInfo::VoidPtrBuiltinVaList; 5419 } 5420 }; 5421 5422 5423 class SPIR32TargetInfo : public SPIRTargetInfo { 5424 public: 5425 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5426 PointerWidth = PointerAlign = 32; 5427 SizeType = TargetInfo::UnsignedInt; 5428 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 5429 DescriptionString 5430 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 5431 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5432 } 5433 virtual void getTargetDefines(const LangOptions &Opts, 5434 MacroBuilder &Builder) const { 5435 DefineStd(Builder, "SPIR32", Opts); 5436 } 5437 }; 5438 5439 class SPIR64TargetInfo : public SPIRTargetInfo { 5440 public: 5441 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5442 PointerWidth = PointerAlign = 64; 5443 SizeType = TargetInfo::UnsignedLong; 5444 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 5445 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 5446 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5447 } 5448 virtual void getTargetDefines(const LangOptions &Opts, 5449 MacroBuilder &Builder) const { 5450 DefineStd(Builder, "SPIR64", Opts); 5451 } 5452 }; 5453 } 5454 5455 namespace { 5456 class XCoreTargetInfo : public TargetInfo { 5457 static const Builtin::Info BuiltinInfo[]; 5458 public: 5459 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5460 BigEndian = false; 5461 NoAsmVariants = true; 5462 LongLongAlign = 32; 5463 SuitableAlign = 32; 5464 DoubleAlign = LongDoubleAlign = 32; 5465 SizeType = UnsignedInt; 5466 PtrDiffType = SignedInt; 5467 IntPtrType = SignedInt; 5468 WCharType = UnsignedChar; 5469 WIntType = UnsignedInt; 5470 UseZeroLengthBitfieldAlignment = true; 5471 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 5472 "-f64:32-a:0:32-n32"; 5473 } 5474 virtual void getTargetDefines(const LangOptions &Opts, 5475 MacroBuilder &Builder) const { 5476 Builder.defineMacro("__XS1B__"); 5477 } 5478 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5479 unsigned &NumRecords) const { 5480 Records = BuiltinInfo; 5481 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 5482 } 5483 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5484 return TargetInfo::VoidPtrBuiltinVaList; 5485 } 5486 virtual const char *getClobbers() const { 5487 return ""; 5488 } 5489 virtual void getGCCRegNames(const char * const *&Names, 5490 unsigned &NumNames) const { 5491 static const char * const GCCRegNames[] = { 5492 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5493 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 5494 }; 5495 Names = GCCRegNames; 5496 NumNames = llvm::array_lengthof(GCCRegNames); 5497 } 5498 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5499 unsigned &NumAliases) const { 5500 Aliases = NULL; 5501 NumAliases = 0; 5502 } 5503 virtual bool validateAsmConstraint(const char *&Name, 5504 TargetInfo::ConstraintInfo &Info) const { 5505 return false; 5506 } 5507 }; 5508 5509 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 5510 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5511 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5512 ALL_LANGUAGES }, 5513 #include "clang/Basic/BuiltinsXCore.def" 5514 }; 5515 } // end anonymous namespace. 5516 5517 5518 //===----------------------------------------------------------------------===// 5519 // Driver code 5520 //===----------------------------------------------------------------------===// 5521 5522 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 5523 llvm::Triple::OSType os = Triple.getOS(); 5524 5525 switch (Triple.getArch()) { 5526 default: 5527 return NULL; 5528 5529 case llvm::Triple::xcore: 5530 return new XCoreTargetInfo(Triple); 5531 5532 case llvm::Triple::hexagon: 5533 return new HexagonTargetInfo(Triple); 5534 5535 case llvm::Triple::aarch64: 5536 switch (os) { 5537 case llvm::Triple::Linux: 5538 return new LinuxTargetInfo<AArch64TargetInfo>(Triple); 5539 case llvm::Triple::NetBSD: 5540 return new NetBSDTargetInfo<AArch64TargetInfo>(Triple); 5541 default: 5542 return new AArch64TargetInfo(Triple); 5543 } 5544 5545 case llvm::Triple::arm: 5546 case llvm::Triple::thumb: 5547 if (Triple.isOSBinFormatMachO()) 5548 return new DarwinARMTargetInfo(Triple); 5549 5550 switch (os) { 5551 case llvm::Triple::Linux: 5552 return new LinuxTargetInfo<ARMTargetInfo>(Triple); 5553 case llvm::Triple::FreeBSD: 5554 return new FreeBSDTargetInfo<ARMTargetInfo>(Triple); 5555 case llvm::Triple::NetBSD: 5556 return new NetBSDTargetInfo<ARMTargetInfo>(Triple); 5557 case llvm::Triple::OpenBSD: 5558 return new OpenBSDTargetInfo<ARMTargetInfo>(Triple); 5559 case llvm::Triple::Bitrig: 5560 return new BitrigTargetInfo<ARMTargetInfo>(Triple); 5561 case llvm::Triple::RTEMS: 5562 return new RTEMSTargetInfo<ARMTargetInfo>(Triple); 5563 case llvm::Triple::NaCl: 5564 return new NaClTargetInfo<ARMTargetInfo>(Triple); 5565 default: 5566 return new ARMTargetInfo(Triple); 5567 } 5568 5569 case llvm::Triple::msp430: 5570 return new MSP430TargetInfo(Triple); 5571 5572 case llvm::Triple::mips: 5573 switch (os) { 5574 case llvm::Triple::Linux: 5575 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 5576 case llvm::Triple::RTEMS: 5577 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 5578 case llvm::Triple::FreeBSD: 5579 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5580 case llvm::Triple::NetBSD: 5581 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5582 default: 5583 return new Mips32EBTargetInfo(Triple); 5584 } 5585 5586 case llvm::Triple::mipsel: 5587 switch (os) { 5588 case llvm::Triple::Linux: 5589 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 5590 case llvm::Triple::RTEMS: 5591 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 5592 case llvm::Triple::FreeBSD: 5593 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5594 case llvm::Triple::NetBSD: 5595 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5596 case llvm::Triple::NaCl: 5597 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 5598 default: 5599 return new Mips32ELTargetInfo(Triple); 5600 } 5601 5602 case llvm::Triple::mips64: 5603 switch (os) { 5604 case llvm::Triple::Linux: 5605 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 5606 case llvm::Triple::RTEMS: 5607 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 5608 case llvm::Triple::FreeBSD: 5609 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5610 case llvm::Triple::NetBSD: 5611 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5612 case llvm::Triple::OpenBSD: 5613 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5614 default: 5615 return new Mips64EBTargetInfo(Triple); 5616 } 5617 5618 case llvm::Triple::mips64el: 5619 switch (os) { 5620 case llvm::Triple::Linux: 5621 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 5622 case llvm::Triple::RTEMS: 5623 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 5624 case llvm::Triple::FreeBSD: 5625 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5626 case llvm::Triple::NetBSD: 5627 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5628 case llvm::Triple::OpenBSD: 5629 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5630 default: 5631 return new Mips64ELTargetInfo(Triple); 5632 } 5633 5634 case llvm::Triple::le32: 5635 switch (os) { 5636 case llvm::Triple::NaCl: 5637 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 5638 default: 5639 return NULL; 5640 } 5641 5642 case llvm::Triple::ppc: 5643 if (Triple.isOSDarwin()) 5644 return new DarwinPPC32TargetInfo(Triple); 5645 switch (os) { 5646 case llvm::Triple::Linux: 5647 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 5648 case llvm::Triple::FreeBSD: 5649 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 5650 case llvm::Triple::NetBSD: 5651 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 5652 case llvm::Triple::OpenBSD: 5653 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 5654 case llvm::Triple::RTEMS: 5655 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 5656 default: 5657 return new PPC32TargetInfo(Triple); 5658 } 5659 5660 case llvm::Triple::ppc64: 5661 if (Triple.isOSDarwin()) 5662 return new DarwinPPC64TargetInfo(Triple); 5663 switch (os) { 5664 case llvm::Triple::Linux: 5665 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5666 case llvm::Triple::Lv2: 5667 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 5668 case llvm::Triple::FreeBSD: 5669 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 5670 case llvm::Triple::NetBSD: 5671 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 5672 default: 5673 return new PPC64TargetInfo(Triple); 5674 } 5675 5676 case llvm::Triple::ppc64le: 5677 switch (os) { 5678 case llvm::Triple::Linux: 5679 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5680 default: 5681 return new PPC64TargetInfo(Triple); 5682 } 5683 5684 case llvm::Triple::nvptx: 5685 return new NVPTX32TargetInfo(Triple); 5686 case llvm::Triple::nvptx64: 5687 return new NVPTX64TargetInfo(Triple); 5688 5689 case llvm::Triple::r600: 5690 return new R600TargetInfo(Triple); 5691 5692 case llvm::Triple::sparc: 5693 switch (os) { 5694 case llvm::Triple::Linux: 5695 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 5696 case llvm::Triple::AuroraUX: 5697 return new AuroraUXSparcV8TargetInfo(Triple); 5698 case llvm::Triple::Solaris: 5699 return new SolarisSparcV8TargetInfo(Triple); 5700 case llvm::Triple::NetBSD: 5701 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 5702 case llvm::Triple::OpenBSD: 5703 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 5704 case llvm::Triple::RTEMS: 5705 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 5706 default: 5707 return new SparcV8TargetInfo(Triple); 5708 } 5709 5710 case llvm::Triple::sparcv9: 5711 switch (os) { 5712 case llvm::Triple::Linux: 5713 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 5714 case llvm::Triple::AuroraUX: 5715 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 5716 case llvm::Triple::Solaris: 5717 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 5718 case llvm::Triple::NetBSD: 5719 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 5720 case llvm::Triple::OpenBSD: 5721 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 5722 case llvm::Triple::FreeBSD: 5723 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 5724 default: 5725 return new SparcV9TargetInfo(Triple); 5726 } 5727 5728 case llvm::Triple::systemz: 5729 switch (os) { 5730 case llvm::Triple::Linux: 5731 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 5732 default: 5733 return new SystemZTargetInfo(Triple); 5734 } 5735 5736 case llvm::Triple::tce: 5737 return new TCETargetInfo(Triple); 5738 5739 case llvm::Triple::x86: 5740 if (Triple.isOSDarwin()) 5741 return new DarwinI386TargetInfo(Triple); 5742 5743 switch (os) { 5744 case llvm::Triple::AuroraUX: 5745 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 5746 case llvm::Triple::Linux: 5747 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 5748 case llvm::Triple::DragonFly: 5749 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 5750 case llvm::Triple::NetBSD: 5751 return new NetBSDI386TargetInfo(Triple); 5752 case llvm::Triple::OpenBSD: 5753 return new OpenBSDI386TargetInfo(Triple); 5754 case llvm::Triple::Bitrig: 5755 return new BitrigI386TargetInfo(Triple); 5756 case llvm::Triple::FreeBSD: 5757 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5758 case llvm::Triple::KFreeBSD: 5759 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5760 case llvm::Triple::Minix: 5761 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 5762 case llvm::Triple::Solaris: 5763 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 5764 case llvm::Triple::Cygwin: 5765 return new CygwinX86_32TargetInfo(Triple); 5766 case llvm::Triple::MinGW32: 5767 return new MinGWX86_32TargetInfo(Triple); 5768 case llvm::Triple::Win32: 5769 return new VisualStudioWindowsX86_32TargetInfo(Triple); 5770 case llvm::Triple::Haiku: 5771 return new HaikuX86_32TargetInfo(Triple); 5772 case llvm::Triple::RTEMS: 5773 return new RTEMSX86_32TargetInfo(Triple); 5774 case llvm::Triple::NaCl: 5775 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 5776 default: 5777 return new X86_32TargetInfo(Triple); 5778 } 5779 5780 case llvm::Triple::x86_64: 5781 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO) 5782 return new DarwinX86_64TargetInfo(Triple); 5783 5784 switch (os) { 5785 case llvm::Triple::AuroraUX: 5786 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 5787 case llvm::Triple::Linux: 5788 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 5789 case llvm::Triple::DragonFly: 5790 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 5791 case llvm::Triple::NetBSD: 5792 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 5793 case llvm::Triple::OpenBSD: 5794 return new OpenBSDX86_64TargetInfo(Triple); 5795 case llvm::Triple::Bitrig: 5796 return new BitrigX86_64TargetInfo(Triple); 5797 case llvm::Triple::FreeBSD: 5798 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5799 case llvm::Triple::KFreeBSD: 5800 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5801 case llvm::Triple::Solaris: 5802 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 5803 case llvm::Triple::MinGW32: 5804 return new MinGWX86_64TargetInfo(Triple); 5805 case llvm::Triple::Win32: // This is what Triple.h supports now. 5806 return new VisualStudioWindowsX86_64TargetInfo(Triple); 5807 case llvm::Triple::NaCl: 5808 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 5809 default: 5810 return new X86_64TargetInfo(Triple); 5811 } 5812 5813 case llvm::Triple::spir: { 5814 if (Triple.getOS() != llvm::Triple::UnknownOS || 5815 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5816 return NULL; 5817 return new SPIR32TargetInfo(Triple); 5818 } 5819 case llvm::Triple::spir64: { 5820 if (Triple.getOS() != llvm::Triple::UnknownOS || 5821 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5822 return NULL; 5823 return new SPIR64TargetInfo(Triple); 5824 } 5825 } 5826 } 5827 5828 /// CreateTargetInfo - Return the target info object for the specified target 5829 /// triple. 5830 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 5831 TargetOptions *Opts) { 5832 llvm::Triple Triple(Opts->Triple); 5833 5834 // Construct the target 5835 OwningPtr<TargetInfo> Target(AllocateTarget(Triple)); 5836 if (!Target) { 5837 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 5838 return 0; 5839 } 5840 Target->setTargetOpts(Opts); 5841 5842 // Set the target CPU if specified. 5843 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 5844 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 5845 return 0; 5846 } 5847 5848 // Set the target ABI if specified. 5849 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 5850 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 5851 return 0; 5852 } 5853 5854 // Set the fp math unit. 5855 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 5856 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 5857 return 0; 5858 } 5859 5860 // Compute the default target features, we need the target to handle this 5861 // because features may have dependencies on one another. 5862 llvm::StringMap<bool> Features; 5863 Target->getDefaultFeatures(Features); 5864 5865 // Apply the user specified deltas. 5866 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 5867 I < N; ++I) { 5868 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 5869 // Apply the feature via the target. 5870 bool Enabled = Name[0] == '+'; 5871 Target->setFeatureEnabled(Features, Name + 1, Enabled); 5872 } 5873 5874 // Add the features to the compile options. 5875 // 5876 // FIXME: If we are completely confident that we have the right set, we only 5877 // need to pass the minuses. 5878 Opts->Features.clear(); 5879 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 5880 ie = Features.end(); it != ie; ++it) 5881 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 5882 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 5883 return 0; 5884 5885 return Target.take(); 5886 } 5887