1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("__STDC_NO_THREADS__"); 121 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 122 // AddressSanitizer doesn't play well with source fortification, which is on 123 // by default on Darwin. 124 if (Opts.Sanitize.has(SanitizerKind::Address)) 125 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 126 127 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 128 if (!Opts.ObjC1) { 129 // __weak is always defined, for use in blocks and with objc pointers. 130 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 131 Builder.defineMacro("__strong", ""); 132 Builder.defineMacro("__unsafe_unretained", ""); 133 } 134 135 if (Opts.Static) 136 Builder.defineMacro("__STATIC__"); 137 else 138 Builder.defineMacro("__DYNAMIC__"); 139 140 if (Opts.POSIXThreads) 141 Builder.defineMacro("_REENTRANT"); 142 143 // Get the platform type and version number from the triple. 144 unsigned Maj, Min, Rev; 145 if (Triple.isMacOSX()) { 146 Triple.getMacOSXVersion(Maj, Min, Rev); 147 PlatformName = "macos"; 148 } else { 149 Triple.getOSVersion(Maj, Min, Rev); 150 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 151 } 152 153 // If -target arch-pc-win32-macho option specified, we're 154 // generating code for Win32 ABI. No need to emit 155 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 156 if (PlatformName == "win32") { 157 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 158 return; 159 } 160 161 // Set the appropriate OS version define. 162 if (Triple.isiOS()) { 163 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 164 char Str[7]; 165 if (Maj < 10) { 166 Str[0] = '0' + Maj; 167 Str[1] = '0' + (Min / 10); 168 Str[2] = '0' + (Min % 10); 169 Str[3] = '0' + (Rev / 10); 170 Str[4] = '0' + (Rev % 10); 171 Str[5] = '\0'; 172 } else { 173 // Handle versions >= 10. 174 Str[0] = '0' + (Maj / 10); 175 Str[1] = '0' + (Maj % 10); 176 Str[2] = '0' + (Min / 10); 177 Str[3] = '0' + (Min % 10); 178 Str[4] = '0' + (Rev / 10); 179 Str[5] = '0' + (Rev % 10); 180 Str[6] = '\0'; 181 } 182 if (Triple.isTvOS()) 183 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 184 else 185 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 186 Str); 187 188 } else if (Triple.isWatchOS()) { 189 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 190 char Str[6]; 191 Str[0] = '0' + Maj; 192 Str[1] = '0' + (Min / 10); 193 Str[2] = '0' + (Min % 10); 194 Str[3] = '0' + (Rev / 10); 195 Str[4] = '0' + (Rev % 10); 196 Str[5] = '\0'; 197 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 198 } else if (Triple.isMacOSX()) { 199 // Note that the Driver allows versions which aren't representable in the 200 // define (because we only get a single digit for the minor and micro 201 // revision numbers). So, we limit them to the maximum representable 202 // version. 203 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 204 char Str[7]; 205 if (Maj < 10 || (Maj == 10 && Min < 10)) { 206 Str[0] = '0' + (Maj / 10); 207 Str[1] = '0' + (Maj % 10); 208 Str[2] = '0' + std::min(Min, 9U); 209 Str[3] = '0' + std::min(Rev, 9U); 210 Str[4] = '\0'; 211 } else { 212 // Handle versions > 10.9. 213 Str[0] = '0' + (Maj / 10); 214 Str[1] = '0' + (Maj % 10); 215 Str[2] = '0' + (Min / 10); 216 Str[3] = '0' + (Min % 10); 217 Str[4] = '0' + (Rev / 10); 218 Str[5] = '0' + (Rev % 10); 219 Str[6] = '\0'; 220 } 221 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 222 } 223 224 // Tell users about the kernel if there is one. 225 if (Triple.isOSDarwin()) 226 Builder.defineMacro("__MACH__"); 227 228 // The Watch ABI uses Dwarf EH. 229 if(Triple.isWatchABI()) 230 Builder.defineMacro("__ARM_DWARF_EH__"); 231 232 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 233 } 234 235 template<typename Target> 236 class DarwinTargetInfo : public OSTargetInfo<Target> { 237 protected: 238 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 239 MacroBuilder &Builder) const override { 240 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 241 this->PlatformMinVersion); 242 } 243 244 public: 245 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 246 : OSTargetInfo<Target>(Triple, Opts) { 247 // By default, no TLS, and we whitelist permitted architecture/OS 248 // combinations. 249 this->TLSSupported = false; 250 251 if (Triple.isMacOSX()) 252 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 253 else if (Triple.isiOS()) { 254 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 255 if (Triple.getArch() == llvm::Triple::x86_64 || 256 Triple.getArch() == llvm::Triple::aarch64) 257 this->TLSSupported = !Triple.isOSVersionLT(8); 258 else if (Triple.getArch() == llvm::Triple::x86 || 259 Triple.getArch() == llvm::Triple::arm || 260 Triple.getArch() == llvm::Triple::thumb) 261 this->TLSSupported = !Triple.isOSVersionLT(9); 262 } else if (Triple.isWatchOS()) 263 this->TLSSupported = !Triple.isOSVersionLT(2); 264 265 this->MCountName = "\01mcount"; 266 } 267 268 std::string isValidSectionSpecifier(StringRef SR) const override { 269 // Let MCSectionMachO validate this. 270 StringRef Segment, Section; 271 unsigned TAA, StubSize; 272 bool HasTAA; 273 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 274 TAA, HasTAA, StubSize); 275 } 276 277 const char *getStaticInitSectionSpecifier() const override { 278 // FIXME: We should return 0 when building kexts. 279 return "__TEXT,__StaticInit,regular,pure_instructions"; 280 } 281 282 /// Darwin does not support protected visibility. Darwin's "default" 283 /// is very similar to ELF's "protected"; Darwin requires a "weak" 284 /// attribute on declarations that can be dynamically replaced. 285 bool hasProtectedVisibility() const override { 286 return false; 287 } 288 289 unsigned getExnObjectAlignment() const override { 290 // The alignment of an exception object is 8-bytes for darwin since 291 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 292 // and therefore doesn't guarantee 16-byte alignment. 293 return 64; 294 } 295 }; 296 297 298 // DragonFlyBSD Target 299 template<typename Target> 300 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 301 protected: 302 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 303 MacroBuilder &Builder) const override { 304 // DragonFly defines; list based off of gcc output 305 Builder.defineMacro("__DragonFly__"); 306 Builder.defineMacro("__DragonFly_cc_version", "100001"); 307 Builder.defineMacro("__ELF__"); 308 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 309 Builder.defineMacro("__tune_i386__"); 310 DefineStd(Builder, "unix", Opts); 311 } 312 public: 313 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 314 : OSTargetInfo<Target>(Triple, Opts) { 315 switch (Triple.getArch()) { 316 default: 317 case llvm::Triple::x86: 318 case llvm::Triple::x86_64: 319 this->MCountName = ".mcount"; 320 break; 321 } 322 } 323 }; 324 325 #ifndef FREEBSD_CC_VERSION 326 #define FREEBSD_CC_VERSION 0U 327 #endif 328 329 // FreeBSD Target 330 template<typename Target> 331 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 332 protected: 333 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 334 MacroBuilder &Builder) const override { 335 // FreeBSD defines; list based off of gcc output 336 337 unsigned Release = Triple.getOSMajorVersion(); 338 if (Release == 0U) 339 Release = 8U; 340 unsigned CCVersion = FREEBSD_CC_VERSION; 341 if (CCVersion == 0U) 342 CCVersion = Release * 100000U + 1U; 343 344 Builder.defineMacro("__FreeBSD__", Twine(Release)); 345 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 346 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 347 DefineStd(Builder, "unix", Opts); 348 Builder.defineMacro("__ELF__"); 349 350 // On FreeBSD, wchar_t contains the number of the code point as 351 // used by the character set of the locale. These character sets are 352 // not necessarily a superset of ASCII. 353 // 354 // FIXME: This is wrong; the macro refers to the numerical values 355 // of wchar_t *literals*, which are not locale-dependent. However, 356 // FreeBSD systems apparently depend on us getting this wrong, and 357 // setting this to 1 is conforming even if all the basic source 358 // character literals have the same encoding as char and wchar_t. 359 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 360 } 361 public: 362 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 363 : OSTargetInfo<Target>(Triple, Opts) { 364 switch (Triple.getArch()) { 365 default: 366 case llvm::Triple::x86: 367 case llvm::Triple::x86_64: 368 this->MCountName = ".mcount"; 369 break; 370 case llvm::Triple::mips: 371 case llvm::Triple::mipsel: 372 case llvm::Triple::ppc: 373 case llvm::Triple::ppc64: 374 case llvm::Triple::ppc64le: 375 this->MCountName = "_mcount"; 376 break; 377 case llvm::Triple::arm: 378 this->MCountName = "__mcount"; 379 break; 380 } 381 } 382 }; 383 384 // GNU/kFreeBSD Target 385 template<typename Target> 386 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 387 protected: 388 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 389 MacroBuilder &Builder) const override { 390 // GNU/kFreeBSD defines; list based off of gcc output 391 392 DefineStd(Builder, "unix", Opts); 393 Builder.defineMacro("__FreeBSD_kernel__"); 394 Builder.defineMacro("__GLIBC__"); 395 Builder.defineMacro("__ELF__"); 396 if (Opts.POSIXThreads) 397 Builder.defineMacro("_REENTRANT"); 398 if (Opts.CPlusPlus) 399 Builder.defineMacro("_GNU_SOURCE"); 400 } 401 public: 402 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 403 : OSTargetInfo<Target>(Triple, Opts) {} 404 }; 405 406 // Haiku Target 407 template<typename Target> 408 class HaikuTargetInfo : public OSTargetInfo<Target> { 409 protected: 410 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 411 MacroBuilder &Builder) const override { 412 // Haiku defines; list based off of gcc output 413 Builder.defineMacro("__HAIKU__"); 414 Builder.defineMacro("__ELF__"); 415 DefineStd(Builder, "unix", Opts); 416 } 417 public: 418 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 419 : OSTargetInfo<Target>(Triple, Opts) { 420 this->SizeType = TargetInfo::UnsignedLong; 421 this->IntPtrType = TargetInfo::SignedLong; 422 this->PtrDiffType = TargetInfo::SignedLong; 423 this->ProcessIDType = TargetInfo::SignedLong; 424 this->TLSSupported = false; 425 426 } 427 }; 428 429 // Minix Target 430 template<typename Target> 431 class MinixTargetInfo : public OSTargetInfo<Target> { 432 protected: 433 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 434 MacroBuilder &Builder) const override { 435 // Minix defines 436 437 Builder.defineMacro("__minix", "3"); 438 Builder.defineMacro("_EM_WSIZE", "4"); 439 Builder.defineMacro("_EM_PSIZE", "4"); 440 Builder.defineMacro("_EM_SSIZE", "2"); 441 Builder.defineMacro("_EM_LSIZE", "4"); 442 Builder.defineMacro("_EM_FSIZE", "4"); 443 Builder.defineMacro("_EM_DSIZE", "8"); 444 Builder.defineMacro("__ELF__"); 445 DefineStd(Builder, "unix", Opts); 446 } 447 public: 448 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 449 : OSTargetInfo<Target>(Triple, Opts) {} 450 }; 451 452 // Linux target 453 template<typename Target> 454 class LinuxTargetInfo : public OSTargetInfo<Target> { 455 protected: 456 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 457 MacroBuilder &Builder) const override { 458 // Linux defines; list based off of gcc output 459 DefineStd(Builder, "unix", Opts); 460 DefineStd(Builder, "linux", Opts); 461 Builder.defineMacro("__gnu_linux__"); 462 Builder.defineMacro("__ELF__"); 463 if (Triple.isAndroid()) { 464 Builder.defineMacro("__ANDROID__", "1"); 465 unsigned Maj, Min, Rev; 466 Triple.getEnvironmentVersion(Maj, Min, Rev); 467 this->PlatformName = "android"; 468 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 469 if (Maj) 470 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 471 } 472 if (Opts.POSIXThreads) 473 Builder.defineMacro("_REENTRANT"); 474 if (Opts.CPlusPlus) 475 Builder.defineMacro("_GNU_SOURCE"); 476 if (this->HasFloat128) 477 Builder.defineMacro("__FLOAT128__"); 478 } 479 public: 480 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 481 : OSTargetInfo<Target>(Triple, Opts) { 482 this->WIntType = TargetInfo::UnsignedInt; 483 484 switch (Triple.getArch()) { 485 default: 486 break; 487 case llvm::Triple::ppc: 488 case llvm::Triple::ppc64: 489 case llvm::Triple::ppc64le: 490 this->MCountName = "_mcount"; 491 break; 492 case llvm::Triple::x86: 493 case llvm::Triple::x86_64: 494 case llvm::Triple::systemz: 495 this->HasFloat128 = true; 496 break; 497 } 498 } 499 500 const char *getStaticInitSectionSpecifier() const override { 501 return ".text.startup"; 502 } 503 }; 504 505 // NetBSD Target 506 template<typename Target> 507 class NetBSDTargetInfo : public OSTargetInfo<Target> { 508 protected: 509 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 510 MacroBuilder &Builder) const override { 511 // NetBSD defines; list based off of gcc output 512 Builder.defineMacro("__NetBSD__"); 513 Builder.defineMacro("__unix__"); 514 Builder.defineMacro("__ELF__"); 515 if (Opts.POSIXThreads) 516 Builder.defineMacro("_REENTRANT"); 517 518 switch (Triple.getArch()) { 519 default: 520 break; 521 case llvm::Triple::arm: 522 case llvm::Triple::armeb: 523 case llvm::Triple::thumb: 524 case llvm::Triple::thumbeb: 525 Builder.defineMacro("__ARM_DWARF_EH__"); 526 break; 527 } 528 } 529 public: 530 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 531 : OSTargetInfo<Target>(Triple, Opts) { 532 this->MCountName = "_mcount"; 533 } 534 }; 535 536 // OpenBSD Target 537 template<typename Target> 538 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 539 protected: 540 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 541 MacroBuilder &Builder) const override { 542 // OpenBSD defines; list based off of gcc output 543 544 Builder.defineMacro("__OpenBSD__"); 545 DefineStd(Builder, "unix", Opts); 546 Builder.defineMacro("__ELF__"); 547 if (Opts.POSIXThreads) 548 Builder.defineMacro("_REENTRANT"); 549 if (this->HasFloat128) 550 Builder.defineMacro("__FLOAT128__"); 551 } 552 public: 553 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 554 : OSTargetInfo<Target>(Triple, Opts) { 555 this->TLSSupported = false; 556 557 switch (Triple.getArch()) { 558 case llvm::Triple::x86: 559 case llvm::Triple::x86_64: 560 this->HasFloat128 = true; 561 // FALLTHROUGH 562 default: 563 this->MCountName = "__mcount"; 564 break; 565 case llvm::Triple::mips64: 566 case llvm::Triple::mips64el: 567 case llvm::Triple::ppc: 568 case llvm::Triple::sparcv9: 569 this->MCountName = "_mcount"; 570 break; 571 } 572 } 573 }; 574 575 // Bitrig Target 576 template<typename Target> 577 class BitrigTargetInfo : public OSTargetInfo<Target> { 578 protected: 579 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 580 MacroBuilder &Builder) const override { 581 // Bitrig defines; list based off of gcc output 582 583 Builder.defineMacro("__Bitrig__"); 584 DefineStd(Builder, "unix", Opts); 585 Builder.defineMacro("__ELF__"); 586 if (Opts.POSIXThreads) 587 Builder.defineMacro("_REENTRANT"); 588 589 switch (Triple.getArch()) { 590 default: 591 break; 592 case llvm::Triple::arm: 593 case llvm::Triple::armeb: 594 case llvm::Triple::thumb: 595 case llvm::Triple::thumbeb: 596 Builder.defineMacro("__ARM_DWARF_EH__"); 597 break; 598 } 599 } 600 public: 601 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 602 : OSTargetInfo<Target>(Triple, Opts) { 603 this->MCountName = "__mcount"; 604 } 605 }; 606 607 // PSP Target 608 template<typename Target> 609 class PSPTargetInfo : public OSTargetInfo<Target> { 610 protected: 611 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 612 MacroBuilder &Builder) const override { 613 // PSP defines; list based on the output of the pspdev gcc toolchain. 614 Builder.defineMacro("PSP"); 615 Builder.defineMacro("_PSP"); 616 Builder.defineMacro("__psp__"); 617 Builder.defineMacro("__ELF__"); 618 } 619 public: 620 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 621 }; 622 623 // PS3 PPU Target 624 template<typename Target> 625 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 626 protected: 627 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 628 MacroBuilder &Builder) const override { 629 // PS3 PPU defines. 630 Builder.defineMacro("__PPC__"); 631 Builder.defineMacro("__PPU__"); 632 Builder.defineMacro("__CELLOS_LV2__"); 633 Builder.defineMacro("__ELF__"); 634 Builder.defineMacro("__LP32__"); 635 Builder.defineMacro("_ARCH_PPC64"); 636 Builder.defineMacro("__powerpc64__"); 637 } 638 public: 639 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 640 : OSTargetInfo<Target>(Triple, Opts) { 641 this->LongWidth = this->LongAlign = 32; 642 this->PointerWidth = this->PointerAlign = 32; 643 this->IntMaxType = TargetInfo::SignedLongLong; 644 this->Int64Type = TargetInfo::SignedLongLong; 645 this->SizeType = TargetInfo::UnsignedInt; 646 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 647 } 648 }; 649 650 template <typename Target> 651 class PS4OSTargetInfo : public OSTargetInfo<Target> { 652 protected: 653 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 654 MacroBuilder &Builder) const override { 655 Builder.defineMacro("__FreeBSD__", "9"); 656 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 657 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 658 DefineStd(Builder, "unix", Opts); 659 Builder.defineMacro("__ELF__"); 660 Builder.defineMacro("__ORBIS__"); 661 } 662 public: 663 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 664 : OSTargetInfo<Target>(Triple, Opts) { 665 this->WCharType = this->UnsignedShort; 666 667 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 668 this->MaxTLSAlign = 256; 669 670 // On PS4, do not honor explicit bit field alignment, 671 // as in "__attribute__((aligned(2))) int b : 1;". 672 this->UseExplicitBitFieldAlignment = false; 673 674 switch (Triple.getArch()) { 675 default: 676 case llvm::Triple::x86_64: 677 this->MCountName = ".mcount"; 678 break; 679 } 680 } 681 }; 682 683 // Solaris target 684 template<typename Target> 685 class SolarisTargetInfo : public OSTargetInfo<Target> { 686 protected: 687 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 688 MacroBuilder &Builder) const override { 689 DefineStd(Builder, "sun", Opts); 690 DefineStd(Builder, "unix", Opts); 691 Builder.defineMacro("__ELF__"); 692 Builder.defineMacro("__svr4__"); 693 Builder.defineMacro("__SVR4"); 694 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 695 // newer, but to 500 for everything else. feature_test.h has a check to 696 // ensure that you are not using C99 with an old version of X/Open or C89 697 // with a new version. 698 if (Opts.C99) 699 Builder.defineMacro("_XOPEN_SOURCE", "600"); 700 else 701 Builder.defineMacro("_XOPEN_SOURCE", "500"); 702 if (Opts.CPlusPlus) 703 Builder.defineMacro("__C99FEATURES__"); 704 Builder.defineMacro("_LARGEFILE_SOURCE"); 705 Builder.defineMacro("_LARGEFILE64_SOURCE"); 706 Builder.defineMacro("__EXTENSIONS__"); 707 Builder.defineMacro("_REENTRANT"); 708 } 709 public: 710 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 711 : OSTargetInfo<Target>(Triple, Opts) { 712 this->WCharType = this->SignedInt; 713 // FIXME: WIntType should be SignedLong 714 } 715 }; 716 717 // Windows target 718 template<typename Target> 719 class WindowsTargetInfo : public OSTargetInfo<Target> { 720 protected: 721 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 722 MacroBuilder &Builder) const override { 723 Builder.defineMacro("_WIN32"); 724 } 725 void getVisualStudioDefines(const LangOptions &Opts, 726 MacroBuilder &Builder) const { 727 if (Opts.CPlusPlus) { 728 if (Opts.RTTIData) 729 Builder.defineMacro("_CPPRTTI"); 730 731 if (Opts.CXXExceptions) 732 Builder.defineMacro("_CPPUNWIND"); 733 } 734 735 if (Opts.Bool) 736 Builder.defineMacro("__BOOL_DEFINED"); 737 738 if (!Opts.CharIsSigned) 739 Builder.defineMacro("_CHAR_UNSIGNED"); 740 741 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 742 // but it works for now. 743 if (Opts.POSIXThreads) 744 Builder.defineMacro("_MT"); 745 746 if (Opts.MSCompatibilityVersion) { 747 Builder.defineMacro("_MSC_VER", 748 Twine(Opts.MSCompatibilityVersion / 100000)); 749 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 750 // FIXME We cannot encode the revision information into 32-bits 751 Builder.defineMacro("_MSC_BUILD", Twine(1)); 752 753 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 754 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 755 756 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 757 if (Opts.CPlusPlus1z) 758 Builder.defineMacro("_MSVC_LANG", "201403L"); 759 else if (Opts.CPlusPlus14) 760 Builder.defineMacro("_MSVC_LANG", "201402L"); 761 } 762 } 763 764 if (Opts.MicrosoftExt) { 765 Builder.defineMacro("_MSC_EXTENSIONS"); 766 767 if (Opts.CPlusPlus11) { 768 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 769 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 770 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 771 } 772 } 773 774 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 775 } 776 777 public: 778 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 779 : OSTargetInfo<Target>(Triple, Opts) {} 780 }; 781 782 template <typename Target> 783 class NaClTargetInfo : public OSTargetInfo<Target> { 784 protected: 785 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 786 MacroBuilder &Builder) const override { 787 if (Opts.POSIXThreads) 788 Builder.defineMacro("_REENTRANT"); 789 if (Opts.CPlusPlus) 790 Builder.defineMacro("_GNU_SOURCE"); 791 792 DefineStd(Builder, "unix", Opts); 793 Builder.defineMacro("__ELF__"); 794 Builder.defineMacro("__native_client__"); 795 } 796 797 public: 798 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 799 : OSTargetInfo<Target>(Triple, Opts) { 800 this->LongAlign = 32; 801 this->LongWidth = 32; 802 this->PointerAlign = 32; 803 this->PointerWidth = 32; 804 this->IntMaxType = TargetInfo::SignedLongLong; 805 this->Int64Type = TargetInfo::SignedLongLong; 806 this->DoubleAlign = 64; 807 this->LongDoubleWidth = 64; 808 this->LongDoubleAlign = 64; 809 this->LongLongWidth = 64; 810 this->LongLongAlign = 64; 811 this->SizeType = TargetInfo::UnsignedInt; 812 this->PtrDiffType = TargetInfo::SignedInt; 813 this->IntPtrType = TargetInfo::SignedInt; 814 // RegParmMax is inherited from the underlying architecture. 815 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 816 if (Triple.getArch() == llvm::Triple::arm) { 817 // Handled in ARM's setABI(). 818 } else if (Triple.getArch() == llvm::Triple::x86) { 819 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 820 } else if (Triple.getArch() == llvm::Triple::x86_64) { 821 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 822 } else if (Triple.getArch() == llvm::Triple::mipsel) { 823 // Handled on mips' setDataLayout. 824 } else { 825 assert(Triple.getArch() == llvm::Triple::le32); 826 this->resetDataLayout("e-p:32:32-i64:64"); 827 } 828 } 829 }; 830 831 // Fuchsia Target 832 template<typename Target> 833 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 834 protected: 835 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 836 MacroBuilder &Builder) const override { 837 Builder.defineMacro("__Fuchsia__"); 838 Builder.defineMacro("__ELF__"); 839 if (Opts.POSIXThreads) 840 Builder.defineMacro("_REENTRANT"); 841 // Required by the libc++ locale support. 842 if (Opts.CPlusPlus) 843 Builder.defineMacro("_GNU_SOURCE"); 844 } 845 public: 846 FuchsiaTargetInfo(const llvm::Triple &Triple, 847 const TargetOptions &Opts) 848 : OSTargetInfo<Target>(Triple, Opts) { 849 this->MCountName = "__mcount"; 850 } 851 }; 852 853 // WebAssembly target 854 template <typename Target> 855 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 856 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 857 MacroBuilder &Builder) const final { 858 // A common platform macro. 859 if (Opts.POSIXThreads) 860 Builder.defineMacro("_REENTRANT"); 861 // Follow g++ convention and predefine _GNU_SOURCE for C++. 862 if (Opts.CPlusPlus) 863 Builder.defineMacro("_GNU_SOURCE"); 864 } 865 866 // As an optimization, group static init code together in a section. 867 const char *getStaticInitSectionSpecifier() const final { 868 return ".text.__startup"; 869 } 870 871 public: 872 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 873 const TargetOptions &Opts) 874 : OSTargetInfo<Target>(Triple, Opts) { 875 this->MCountName = "__mcount"; 876 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 877 } 878 }; 879 880 //===----------------------------------------------------------------------===// 881 // Specific target implementations. 882 //===----------------------------------------------------------------------===// 883 884 // PPC abstract base class 885 class PPCTargetInfo : public TargetInfo { 886 static const Builtin::Info BuiltinInfo[]; 887 static const char * const GCCRegNames[]; 888 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 889 std::string CPU; 890 891 // Target cpu features. 892 bool HasAltivec; 893 bool HasVSX; 894 bool HasP8Vector; 895 bool HasP8Crypto; 896 bool HasDirectMove; 897 bool HasQPX; 898 bool HasHTM; 899 bool HasBPERMD; 900 bool HasExtDiv; 901 bool HasP9Vector; 902 903 protected: 904 std::string ABI; 905 906 public: 907 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 908 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false), 909 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 910 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 911 SuitableAlign = 128; 912 SimdDefaultAlign = 128; 913 LongDoubleWidth = LongDoubleAlign = 128; 914 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 915 } 916 917 /// \brief Flags for architecture specific defines. 918 typedef enum { 919 ArchDefineNone = 0, 920 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 921 ArchDefinePpcgr = 1 << 1, 922 ArchDefinePpcsq = 1 << 2, 923 ArchDefine440 = 1 << 3, 924 ArchDefine603 = 1 << 4, 925 ArchDefine604 = 1 << 5, 926 ArchDefinePwr4 = 1 << 6, 927 ArchDefinePwr5 = 1 << 7, 928 ArchDefinePwr5x = 1 << 8, 929 ArchDefinePwr6 = 1 << 9, 930 ArchDefinePwr6x = 1 << 10, 931 ArchDefinePwr7 = 1 << 11, 932 ArchDefinePwr8 = 1 << 12, 933 ArchDefinePwr9 = 1 << 13, 934 ArchDefineA2 = 1 << 14, 935 ArchDefineA2q = 1 << 15 936 } ArchDefineTypes; 937 938 // Set the language option for altivec based on our value. 939 void adjust(LangOptions &Opts) override { 940 if (HasAltivec) 941 Opts.AltiVec = 1; 942 TargetInfo::adjust(Opts); 943 } 944 945 // Note: GCC recognizes the following additional cpus: 946 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 947 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 948 // titan, rs64. 949 bool setCPU(const std::string &Name) override { 950 bool CPUKnown = llvm::StringSwitch<bool>(Name) 951 .Case("generic", true) 952 .Case("440", true) 953 .Case("450", true) 954 .Case("601", true) 955 .Case("602", true) 956 .Case("603", true) 957 .Case("603e", true) 958 .Case("603ev", true) 959 .Case("604", true) 960 .Case("604e", true) 961 .Case("620", true) 962 .Case("630", true) 963 .Case("g3", true) 964 .Case("7400", true) 965 .Case("g4", true) 966 .Case("7450", true) 967 .Case("g4+", true) 968 .Case("750", true) 969 .Case("970", true) 970 .Case("g5", true) 971 .Case("a2", true) 972 .Case("a2q", true) 973 .Case("e500mc", true) 974 .Case("e5500", true) 975 .Case("power3", true) 976 .Case("pwr3", true) 977 .Case("power4", true) 978 .Case("pwr4", true) 979 .Case("power5", true) 980 .Case("pwr5", true) 981 .Case("power5x", true) 982 .Case("pwr5x", true) 983 .Case("power6", true) 984 .Case("pwr6", true) 985 .Case("power6x", true) 986 .Case("pwr6x", true) 987 .Case("power7", true) 988 .Case("pwr7", true) 989 .Case("power8", true) 990 .Case("pwr8", true) 991 .Case("power9", true) 992 .Case("pwr9", true) 993 .Case("powerpc", true) 994 .Case("ppc", true) 995 .Case("powerpc64", true) 996 .Case("ppc64", true) 997 .Case("powerpc64le", true) 998 .Case("ppc64le", true) 999 .Default(false); 1000 1001 if (CPUKnown) 1002 CPU = Name; 1003 1004 return CPUKnown; 1005 } 1006 1007 1008 StringRef getABI() const override { return ABI; } 1009 1010 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1011 return llvm::makeArrayRef(BuiltinInfo, 1012 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1013 } 1014 1015 bool isCLZForZeroUndef() const override { return false; } 1016 1017 void getTargetDefines(const LangOptions &Opts, 1018 MacroBuilder &Builder) const override; 1019 1020 bool 1021 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1022 StringRef CPU, 1023 const std::vector<std::string> &FeaturesVec) const override; 1024 1025 bool handleTargetFeatures(std::vector<std::string> &Features, 1026 DiagnosticsEngine &Diags) override; 1027 bool hasFeature(StringRef Feature) const override; 1028 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1029 bool Enabled) const override; 1030 1031 ArrayRef<const char *> getGCCRegNames() const override; 1032 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1033 bool validateAsmConstraint(const char *&Name, 1034 TargetInfo::ConstraintInfo &Info) const override { 1035 switch (*Name) { 1036 default: return false; 1037 case 'O': // Zero 1038 break; 1039 case 'b': // Base register 1040 case 'f': // Floating point register 1041 Info.setAllowsRegister(); 1042 break; 1043 // FIXME: The following are added to allow parsing. 1044 // I just took a guess at what the actions should be. 1045 // Also, is more specific checking needed? I.e. specific registers? 1046 case 'd': // Floating point register (containing 64-bit value) 1047 case 'v': // Altivec vector register 1048 Info.setAllowsRegister(); 1049 break; 1050 case 'w': 1051 switch (Name[1]) { 1052 case 'd':// VSX vector register to hold vector double data 1053 case 'f':// VSX vector register to hold vector float data 1054 case 's':// VSX vector register to hold scalar float data 1055 case 'a':// Any VSX register 1056 case 'c':// An individual CR bit 1057 break; 1058 default: 1059 return false; 1060 } 1061 Info.setAllowsRegister(); 1062 Name++; // Skip over 'w'. 1063 break; 1064 case 'h': // `MQ', `CTR', or `LINK' register 1065 case 'q': // `MQ' register 1066 case 'c': // `CTR' register 1067 case 'l': // `LINK' register 1068 case 'x': // `CR' register (condition register) number 0 1069 case 'y': // `CR' register (condition register) 1070 case 'z': // `XER[CA]' carry bit (part of the XER register) 1071 Info.setAllowsRegister(); 1072 break; 1073 case 'I': // Signed 16-bit constant 1074 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1075 // (use `L' instead for SImode constants) 1076 case 'K': // Unsigned 16-bit constant 1077 case 'L': // Signed 16-bit constant shifted left 16 bits 1078 case 'M': // Constant larger than 31 1079 case 'N': // Exact power of 2 1080 case 'P': // Constant whose negation is a signed 16-bit constant 1081 case 'G': // Floating point constant that can be loaded into a 1082 // register with one instruction per word 1083 case 'H': // Integer/Floating point constant that can be loaded 1084 // into a register using three instructions 1085 break; 1086 case 'm': // Memory operand. Note that on PowerPC targets, m can 1087 // include addresses that update the base register. It 1088 // is therefore only safe to use `m' in an asm statement 1089 // if that asm statement accesses the operand exactly once. 1090 // The asm statement must also use `%U<opno>' as a 1091 // placeholder for the "update" flag in the corresponding 1092 // load or store instruction. For example: 1093 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1094 // is correct but: 1095 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1096 // is not. Use es rather than m if you don't want the base 1097 // register to be updated. 1098 case 'e': 1099 if (Name[1] != 's') 1100 return false; 1101 // es: A "stable" memory operand; that is, one which does not 1102 // include any automodification of the base register. Unlike 1103 // `m', this constraint can be used in asm statements that 1104 // might access the operand several times, or that might not 1105 // access it at all. 1106 Info.setAllowsMemory(); 1107 Name++; // Skip over 'e'. 1108 break; 1109 case 'Q': // Memory operand that is an offset from a register (it is 1110 // usually better to use `m' or `es' in asm statements) 1111 case 'Z': // Memory operand that is an indexed or indirect from a 1112 // register (it is usually better to use `m' or `es' in 1113 // asm statements) 1114 Info.setAllowsMemory(); 1115 Info.setAllowsRegister(); 1116 break; 1117 case 'R': // AIX TOC entry 1118 case 'a': // Address operand that is an indexed or indirect from a 1119 // register (`p' is preferable for asm statements) 1120 case 'S': // Constant suitable as a 64-bit mask operand 1121 case 'T': // Constant suitable as a 32-bit mask operand 1122 case 'U': // System V Release 4 small data area reference 1123 case 't': // AND masks that can be performed by two rldic{l, r} 1124 // instructions 1125 case 'W': // Vector constant that does not require memory 1126 case 'j': // Vector constant that is all zeros. 1127 break; 1128 // End FIXME. 1129 } 1130 return true; 1131 } 1132 std::string convertConstraint(const char *&Constraint) const override { 1133 std::string R; 1134 switch (*Constraint) { 1135 case 'e': 1136 case 'w': 1137 // Two-character constraint; add "^" hint for later parsing. 1138 R = std::string("^") + std::string(Constraint, 2); 1139 Constraint++; 1140 break; 1141 default: 1142 return TargetInfo::convertConstraint(Constraint); 1143 } 1144 return R; 1145 } 1146 const char *getClobbers() const override { 1147 return ""; 1148 } 1149 int getEHDataRegisterNumber(unsigned RegNo) const override { 1150 if (RegNo == 0) return 3; 1151 if (RegNo == 1) return 4; 1152 return -1; 1153 } 1154 1155 bool hasSjLjLowering() const override { 1156 return true; 1157 } 1158 1159 bool useFloat128ManglingForLongDouble() const override { 1160 return LongDoubleWidth == 128 && 1161 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1162 getTriple().isOSBinFormatELF(); 1163 } 1164 }; 1165 1166 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1167 #define BUILTIN(ID, TYPE, ATTRS) \ 1168 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1169 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1170 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1171 #include "clang/Basic/BuiltinsPPC.def" 1172 }; 1173 1174 /// handleTargetFeatures - Perform initialization based on the user 1175 /// configured set of features. 1176 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1177 DiagnosticsEngine &Diags) { 1178 for (const auto &Feature : Features) { 1179 if (Feature == "+altivec") { 1180 HasAltivec = true; 1181 } else if (Feature == "+vsx") { 1182 HasVSX = true; 1183 } else if (Feature == "+bpermd") { 1184 HasBPERMD = true; 1185 } else if (Feature == "+extdiv") { 1186 HasExtDiv = true; 1187 } else if (Feature == "+power8-vector") { 1188 HasP8Vector = true; 1189 } else if (Feature == "+crypto") { 1190 HasP8Crypto = true; 1191 } else if (Feature == "+direct-move") { 1192 HasDirectMove = true; 1193 } else if (Feature == "+qpx") { 1194 HasQPX = true; 1195 } else if (Feature == "+htm") { 1196 HasHTM = true; 1197 } else if (Feature == "+float128") { 1198 HasFloat128 = true; 1199 } else if (Feature == "+power9-vector") { 1200 HasP9Vector = true; 1201 } 1202 // TODO: Finish this list and add an assert that we've handled them 1203 // all. 1204 } 1205 1206 return true; 1207 } 1208 1209 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1210 /// #defines that are not tied to a specific subtarget. 1211 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1212 MacroBuilder &Builder) const { 1213 // Target identification. 1214 Builder.defineMacro("__ppc__"); 1215 Builder.defineMacro("__PPC__"); 1216 Builder.defineMacro("_ARCH_PPC"); 1217 Builder.defineMacro("__powerpc__"); 1218 Builder.defineMacro("__POWERPC__"); 1219 if (PointerWidth == 64) { 1220 Builder.defineMacro("_ARCH_PPC64"); 1221 Builder.defineMacro("__powerpc64__"); 1222 Builder.defineMacro("__ppc64__"); 1223 Builder.defineMacro("__PPC64__"); 1224 } 1225 1226 // Target properties. 1227 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1228 Builder.defineMacro("_LITTLE_ENDIAN"); 1229 } else { 1230 if (getTriple().getOS() != llvm::Triple::NetBSD && 1231 getTriple().getOS() != llvm::Triple::OpenBSD) 1232 Builder.defineMacro("_BIG_ENDIAN"); 1233 } 1234 1235 // ABI options. 1236 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1237 Builder.defineMacro("_CALL_ELF", "1"); 1238 if (ABI == "elfv2") 1239 Builder.defineMacro("_CALL_ELF", "2"); 1240 1241 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 1242 // our suppport post-dates this and it should work on all 64-bit ppc linux 1243 // platforms. It is guaranteed to work on all elfv2 platforms. 1244 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 1245 Builder.defineMacro("_CALL_LINUX", "1"); 1246 1247 // Subtarget options. 1248 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1249 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1250 1251 // FIXME: Should be controlled by command line option. 1252 if (LongDoubleWidth == 128) { 1253 Builder.defineMacro("__LONG_DOUBLE_128__"); 1254 Builder.defineMacro("__LONGDOUBLE128"); 1255 } 1256 1257 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1258 if (ABI == "elfv2" || 1259 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1260 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1261 1262 // CPU identification. 1263 ArchDefineTypes defs = 1264 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1265 .Case("440", ArchDefineName) 1266 .Case("450", ArchDefineName | ArchDefine440) 1267 .Case("601", ArchDefineName) 1268 .Case("602", ArchDefineName | ArchDefinePpcgr) 1269 .Case("603", ArchDefineName | ArchDefinePpcgr) 1270 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1271 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1272 .Case("604", ArchDefineName | ArchDefinePpcgr) 1273 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1274 .Case("620", ArchDefineName | ArchDefinePpcgr) 1275 .Case("630", ArchDefineName | ArchDefinePpcgr) 1276 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1277 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1278 .Case("750", ArchDefineName | ArchDefinePpcgr) 1279 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1280 ArchDefinePpcsq) 1281 .Case("a2", ArchDefineA2) 1282 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1283 .Case("pwr3", ArchDefinePpcgr) 1284 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1285 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1286 ArchDefinePpcsq) 1287 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 | 1288 ArchDefinePpcgr | ArchDefinePpcsq) 1289 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 | 1290 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1291 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x | 1292 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1293 ArchDefinePpcsq) 1294 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 | 1295 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1296 ArchDefinePpcgr | ArchDefinePpcsq) 1297 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x | 1298 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1299 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1300 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 | 1301 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1302 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1303 ArchDefinePpcsq) 1304 .Case("power3", ArchDefinePpcgr) 1305 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1306 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1307 ArchDefinePpcsq) 1308 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1309 ArchDefinePpcgr | ArchDefinePpcsq) 1310 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1311 ArchDefinePwr4 | ArchDefinePpcgr | 1312 ArchDefinePpcsq) 1313 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1314 ArchDefinePwr5 | ArchDefinePwr4 | 1315 ArchDefinePpcgr | ArchDefinePpcsq) 1316 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | 1317 ArchDefinePwr5x | ArchDefinePwr5 | 1318 ArchDefinePwr4 | ArchDefinePpcgr | 1319 ArchDefinePpcsq) 1320 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1321 ArchDefinePwr6 | ArchDefinePwr5x | 1322 ArchDefinePwr5 | ArchDefinePwr4 | 1323 ArchDefinePpcgr | ArchDefinePpcsq) 1324 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 1325 ArchDefinePwr6x | ArchDefinePwr6 | 1326 ArchDefinePwr5x | ArchDefinePwr5 | 1327 ArchDefinePwr4 | ArchDefinePpcgr | 1328 ArchDefinePpcsq) 1329 // powerpc64le automatically defaults to at least power8. 1330 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1331 ArchDefinePwr6 | ArchDefinePwr5x | 1332 ArchDefinePwr5 | ArchDefinePwr4 | 1333 ArchDefinePpcgr | ArchDefinePpcsq) 1334 .Default(ArchDefineNone); 1335 1336 if (defs & ArchDefineName) 1337 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1338 if (defs & ArchDefinePpcgr) 1339 Builder.defineMacro("_ARCH_PPCGR"); 1340 if (defs & ArchDefinePpcsq) 1341 Builder.defineMacro("_ARCH_PPCSQ"); 1342 if (defs & ArchDefine440) 1343 Builder.defineMacro("_ARCH_440"); 1344 if (defs & ArchDefine603) 1345 Builder.defineMacro("_ARCH_603"); 1346 if (defs & ArchDefine604) 1347 Builder.defineMacro("_ARCH_604"); 1348 if (defs & ArchDefinePwr4) 1349 Builder.defineMacro("_ARCH_PWR4"); 1350 if (defs & ArchDefinePwr5) 1351 Builder.defineMacro("_ARCH_PWR5"); 1352 if (defs & ArchDefinePwr5x) 1353 Builder.defineMacro("_ARCH_PWR5X"); 1354 if (defs & ArchDefinePwr6) 1355 Builder.defineMacro("_ARCH_PWR6"); 1356 if (defs & ArchDefinePwr6x) 1357 Builder.defineMacro("_ARCH_PWR6X"); 1358 if (defs & ArchDefinePwr7) 1359 Builder.defineMacro("_ARCH_PWR7"); 1360 if (defs & ArchDefinePwr8) 1361 Builder.defineMacro("_ARCH_PWR8"); 1362 if (defs & ArchDefinePwr9) 1363 Builder.defineMacro("_ARCH_PWR9"); 1364 if (defs & ArchDefineA2) 1365 Builder.defineMacro("_ARCH_A2"); 1366 if (defs & ArchDefineA2q) { 1367 Builder.defineMacro("_ARCH_A2Q"); 1368 Builder.defineMacro("_ARCH_QP"); 1369 } 1370 1371 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1372 Builder.defineMacro("__bg__"); 1373 Builder.defineMacro("__THW_BLUEGENE__"); 1374 Builder.defineMacro("__bgq__"); 1375 Builder.defineMacro("__TOS_BGQ__"); 1376 } 1377 1378 if (HasAltivec) { 1379 Builder.defineMacro("__VEC__", "10206"); 1380 Builder.defineMacro("__ALTIVEC__"); 1381 } 1382 if (HasVSX) 1383 Builder.defineMacro("__VSX__"); 1384 if (HasP8Vector) 1385 Builder.defineMacro("__POWER8_VECTOR__"); 1386 if (HasP8Crypto) 1387 Builder.defineMacro("__CRYPTO__"); 1388 if (HasHTM) 1389 Builder.defineMacro("__HTM__"); 1390 if (HasFloat128) 1391 Builder.defineMacro("__FLOAT128__"); 1392 if (HasP9Vector) 1393 Builder.defineMacro("__POWER9_VECTOR__"); 1394 1395 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1397 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1398 if (PointerWidth == 64) 1399 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1400 1401 // We have support for the bswap intrinsics so we can define this. 1402 Builder.defineMacro("__HAVE_BSWAP__", "1"); 1403 1404 // FIXME: The following are not yet generated here by Clang, but are 1405 // generated by GCC: 1406 // 1407 // _SOFT_FLOAT_ 1408 // __RECIP_PRECISION__ 1409 // __APPLE_ALTIVEC__ 1410 // __RECIP__ 1411 // __RECIPF__ 1412 // __RSQRTE__ 1413 // __RSQRTEF__ 1414 // _SOFT_DOUBLE_ 1415 // __NO_LWSYNC__ 1416 // __CMODEL_MEDIUM__ 1417 // __CMODEL_LARGE__ 1418 // _CALL_SYSV 1419 // _CALL_DARWIN 1420 // __NO_FPRS__ 1421 } 1422 1423 // Handle explicit options being passed to the compiler here: if we've 1424 // explicitly turned off vsx and turned on any of: 1425 // - power8-vector 1426 // - direct-move 1427 // - float128 1428 // - power9-vector 1429 // then go ahead and error since the customer has expressed an incompatible 1430 // set of options. 1431 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1432 const std::vector<std::string> &FeaturesVec) { 1433 1434 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1435 FeaturesVec.end()) { 1436 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1437 FeaturesVec.end()) { 1438 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1439 << "-mno-vsx"; 1440 return false; 1441 } 1442 1443 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1444 FeaturesVec.end()) { 1445 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1446 << "-mno-vsx"; 1447 return false; 1448 } 1449 1450 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1451 FeaturesVec.end()) { 1452 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1453 << "-mno-vsx"; 1454 return false; 1455 } 1456 1457 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1458 FeaturesVec.end()) { 1459 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1460 << "-mno-vsx"; 1461 return false; 1462 } 1463 } 1464 1465 return true; 1466 } 1467 1468 bool PPCTargetInfo::initFeatureMap( 1469 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1470 const std::vector<std::string> &FeaturesVec) const { 1471 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1472 .Case("7400", true) 1473 .Case("g4", true) 1474 .Case("7450", true) 1475 .Case("g4+", true) 1476 .Case("970", true) 1477 .Case("g5", true) 1478 .Case("pwr6", true) 1479 .Case("pwr7", true) 1480 .Case("pwr8", true) 1481 .Case("pwr9", true) 1482 .Case("ppc64", true) 1483 .Case("ppc64le", true) 1484 .Default(false); 1485 1486 Features["qpx"] = (CPU == "a2q"); 1487 Features["power9-vector"] = (CPU == "pwr9"); 1488 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1489 .Case("ppc64le", true) 1490 .Case("pwr9", true) 1491 .Case("pwr8", true) 1492 .Default(false); 1493 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1494 .Case("ppc64le", true) 1495 .Case("pwr9", true) 1496 .Case("pwr8", true) 1497 .Default(false); 1498 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1499 .Case("ppc64le", true) 1500 .Case("pwr9", true) 1501 .Case("pwr8", true) 1502 .Case("pwr7", true) 1503 .Default(false); 1504 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1505 .Case("ppc64le", true) 1506 .Case("pwr9", true) 1507 .Case("pwr8", true) 1508 .Case("pwr7", true) 1509 .Default(false); 1510 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1511 .Case("ppc64le", true) 1512 .Case("pwr9", true) 1513 .Case("pwr8", true) 1514 .Default(false); 1515 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1516 .Case("ppc64le", true) 1517 .Case("pwr9", true) 1518 .Case("pwr8", true) 1519 .Case("pwr7", true) 1520 .Default(false); 1521 Features["htm"] = llvm::StringSwitch<bool>(CPU) 1522 .Case("ppc64le", true) 1523 .Case("pwr9", true) 1524 .Case("pwr8", true) 1525 .Default(false); 1526 1527 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1528 return false; 1529 1530 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1531 } 1532 1533 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1534 return llvm::StringSwitch<bool>(Feature) 1535 .Case("powerpc", true) 1536 .Case("altivec", HasAltivec) 1537 .Case("vsx", HasVSX) 1538 .Case("power8-vector", HasP8Vector) 1539 .Case("crypto", HasP8Crypto) 1540 .Case("direct-move", HasDirectMove) 1541 .Case("qpx", HasQPX) 1542 .Case("htm", HasHTM) 1543 .Case("bpermd", HasBPERMD) 1544 .Case("extdiv", HasExtDiv) 1545 .Case("float128", HasFloat128) 1546 .Case("power9-vector", HasP9Vector) 1547 .Default(false); 1548 } 1549 1550 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1551 StringRef Name, bool Enabled) const { 1552 if (Enabled) { 1553 // If we're enabling any of the vsx based features then enable vsx and 1554 // altivec. We'll diagnose any problems later. 1555 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name) 1556 .Case("vsx", true) 1557 .Case("direct-move", true) 1558 .Case("power8-vector", true) 1559 .Case("power9-vector", true) 1560 .Case("float128", true) 1561 .Default(false); 1562 if (FeatureHasVSX) 1563 Features["vsx"] = Features["altivec"] = true; 1564 if (Name == "power9-vector") 1565 Features["power8-vector"] = true; 1566 Features[Name] = true; 1567 } else { 1568 // If we're disabling altivec or vsx go ahead and disable all of the vsx 1569 // features. 1570 if ((Name == "altivec") || (Name == "vsx")) 1571 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] = 1572 Features["float128"] = Features["power9-vector"] = false; 1573 if (Name == "power8-vector") 1574 Features["power9-vector"] = false; 1575 Features[Name] = false; 1576 } 1577 } 1578 1579 const char * const PPCTargetInfo::GCCRegNames[] = { 1580 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1581 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1582 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1583 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1584 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1585 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1586 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1587 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1588 "mq", "lr", "ctr", "ap", 1589 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1590 "xer", 1591 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1592 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1593 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1594 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1595 "vrsave", "vscr", 1596 "spe_acc", "spefscr", 1597 "sfp" 1598 }; 1599 1600 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1601 return llvm::makeArrayRef(GCCRegNames); 1602 } 1603 1604 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1605 // While some of these aliases do map to different registers 1606 // they still share the same register name. 1607 { { "0" }, "r0" }, 1608 { { "1"}, "r1" }, 1609 { { "2" }, "r2" }, 1610 { { "3" }, "r3" }, 1611 { { "4" }, "r4" }, 1612 { { "5" }, "r5" }, 1613 { { "6" }, "r6" }, 1614 { { "7" }, "r7" }, 1615 { { "8" }, "r8" }, 1616 { { "9" }, "r9" }, 1617 { { "10" }, "r10" }, 1618 { { "11" }, "r11" }, 1619 { { "12" }, "r12" }, 1620 { { "13" }, "r13" }, 1621 { { "14" }, "r14" }, 1622 { { "15" }, "r15" }, 1623 { { "16" }, "r16" }, 1624 { { "17" }, "r17" }, 1625 { { "18" }, "r18" }, 1626 { { "19" }, "r19" }, 1627 { { "20" }, "r20" }, 1628 { { "21" }, "r21" }, 1629 { { "22" }, "r22" }, 1630 { { "23" }, "r23" }, 1631 { { "24" }, "r24" }, 1632 { { "25" }, "r25" }, 1633 { { "26" }, "r26" }, 1634 { { "27" }, "r27" }, 1635 { { "28" }, "r28" }, 1636 { { "29" }, "r29" }, 1637 { { "30" }, "r30" }, 1638 { { "31" }, "r31" }, 1639 { { "fr0" }, "f0" }, 1640 { { "fr1" }, "f1" }, 1641 { { "fr2" }, "f2" }, 1642 { { "fr3" }, "f3" }, 1643 { { "fr4" }, "f4" }, 1644 { { "fr5" }, "f5" }, 1645 { { "fr6" }, "f6" }, 1646 { { "fr7" }, "f7" }, 1647 { { "fr8" }, "f8" }, 1648 { { "fr9" }, "f9" }, 1649 { { "fr10" }, "f10" }, 1650 { { "fr11" }, "f11" }, 1651 { { "fr12" }, "f12" }, 1652 { { "fr13" }, "f13" }, 1653 { { "fr14" }, "f14" }, 1654 { { "fr15" }, "f15" }, 1655 { { "fr16" }, "f16" }, 1656 { { "fr17" }, "f17" }, 1657 { { "fr18" }, "f18" }, 1658 { { "fr19" }, "f19" }, 1659 { { "fr20" }, "f20" }, 1660 { { "fr21" }, "f21" }, 1661 { { "fr22" }, "f22" }, 1662 { { "fr23" }, "f23" }, 1663 { { "fr24" }, "f24" }, 1664 { { "fr25" }, "f25" }, 1665 { { "fr26" }, "f26" }, 1666 { { "fr27" }, "f27" }, 1667 { { "fr28" }, "f28" }, 1668 { { "fr29" }, "f29" }, 1669 { { "fr30" }, "f30" }, 1670 { { "fr31" }, "f31" }, 1671 { { "cc" }, "cr0" }, 1672 }; 1673 1674 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1675 return llvm::makeArrayRef(GCCRegAliases); 1676 } 1677 1678 class PPC32TargetInfo : public PPCTargetInfo { 1679 public: 1680 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1681 : PPCTargetInfo(Triple, Opts) { 1682 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1683 1684 switch (getTriple().getOS()) { 1685 case llvm::Triple::Linux: 1686 case llvm::Triple::FreeBSD: 1687 case llvm::Triple::NetBSD: 1688 SizeType = UnsignedInt; 1689 PtrDiffType = SignedInt; 1690 IntPtrType = SignedInt; 1691 break; 1692 default: 1693 break; 1694 } 1695 1696 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1697 LongDoubleWidth = LongDoubleAlign = 64; 1698 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1699 } 1700 1701 // PPC32 supports atomics up to 4 bytes. 1702 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1703 } 1704 1705 BuiltinVaListKind getBuiltinVaListKind() const override { 1706 // This is the ELF definition, and is overridden by the Darwin sub-target 1707 return TargetInfo::PowerABIBuiltinVaList; 1708 } 1709 }; 1710 1711 // Note: ABI differences may eventually require us to have a separate 1712 // TargetInfo for little endian. 1713 class PPC64TargetInfo : public PPCTargetInfo { 1714 public: 1715 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1716 : PPCTargetInfo(Triple, Opts) { 1717 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1718 IntMaxType = SignedLong; 1719 Int64Type = SignedLong; 1720 1721 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1722 resetDataLayout("e-m:e-i64:64-n32:64"); 1723 ABI = "elfv2"; 1724 } else { 1725 resetDataLayout("E-m:e-i64:64-n32:64"); 1726 ABI = "elfv1"; 1727 } 1728 1729 switch (getTriple().getOS()) { 1730 case llvm::Triple::FreeBSD: 1731 LongDoubleWidth = LongDoubleAlign = 64; 1732 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1733 break; 1734 case llvm::Triple::NetBSD: 1735 IntMaxType = SignedLongLong; 1736 Int64Type = SignedLongLong; 1737 break; 1738 default: 1739 break; 1740 } 1741 1742 // PPC64 supports atomics up to 8 bytes. 1743 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1744 } 1745 BuiltinVaListKind getBuiltinVaListKind() const override { 1746 return TargetInfo::CharPtrBuiltinVaList; 1747 } 1748 // PPC64 Linux-specific ABI options. 1749 bool setABI(const std::string &Name) override { 1750 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1751 ABI = Name; 1752 return true; 1753 } 1754 return false; 1755 } 1756 }; 1757 1758 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1759 public: 1760 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1761 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1762 HasAlignMac68kSupport = true; 1763 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1764 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1765 LongLongAlign = 32; 1766 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1767 } 1768 BuiltinVaListKind getBuiltinVaListKind() const override { 1769 return TargetInfo::CharPtrBuiltinVaList; 1770 } 1771 }; 1772 1773 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1774 public: 1775 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1776 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1777 HasAlignMac68kSupport = true; 1778 resetDataLayout("E-m:o-i64:64-n32:64"); 1779 } 1780 }; 1781 1782 static const unsigned NVPTXAddrSpaceMap[] = { 1783 0, // Default 1784 1, // opencl_global 1785 3, // opencl_local 1786 4, // opencl_constant 1787 // FIXME: generic has to be added to the target 1788 0, // opencl_generic 1789 1, // cuda_device 1790 4, // cuda_constant 1791 3, // cuda_shared 1792 }; 1793 1794 class NVPTXTargetInfo : public TargetInfo { 1795 static const char *const GCCRegNames[]; 1796 static const Builtin::Info BuiltinInfo[]; 1797 CudaArch GPU; 1798 std::unique_ptr<TargetInfo> HostTarget; 1799 1800 public: 1801 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1802 unsigned TargetPointerWidth) 1803 : TargetInfo(Triple) { 1804 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1805 "NVPTX only supports 32- and 64-bit modes."); 1806 1807 TLSSupported = false; 1808 AddrSpaceMap = &NVPTXAddrSpaceMap; 1809 UseAddrSpaceMapMangling = true; 1810 1811 // Define available target features 1812 // These must be defined in sorted order! 1813 NoAsmVariants = true; 1814 GPU = CudaArch::SM_20; 1815 1816 if (TargetPointerWidth == 32) 1817 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1818 else 1819 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1820 1821 // If possible, get a TargetInfo for our host triple, so we can match its 1822 // types. 1823 llvm::Triple HostTriple(Opts.HostTriple); 1824 if (!HostTriple.isNVPTX()) 1825 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1826 1827 // If no host target, make some guesses about the data layout and return. 1828 if (!HostTarget) { 1829 LongWidth = LongAlign = TargetPointerWidth; 1830 PointerWidth = PointerAlign = TargetPointerWidth; 1831 switch (TargetPointerWidth) { 1832 case 32: 1833 SizeType = TargetInfo::UnsignedInt; 1834 PtrDiffType = TargetInfo::SignedInt; 1835 IntPtrType = TargetInfo::SignedInt; 1836 break; 1837 case 64: 1838 SizeType = TargetInfo::UnsignedLong; 1839 PtrDiffType = TargetInfo::SignedLong; 1840 IntPtrType = TargetInfo::SignedLong; 1841 break; 1842 default: 1843 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1844 } 1845 return; 1846 } 1847 1848 // Copy properties from host target. 1849 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1850 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1851 BoolWidth = HostTarget->getBoolWidth(); 1852 BoolAlign = HostTarget->getBoolAlign(); 1853 IntWidth = HostTarget->getIntWidth(); 1854 IntAlign = HostTarget->getIntAlign(); 1855 HalfWidth = HostTarget->getHalfWidth(); 1856 HalfAlign = HostTarget->getHalfAlign(); 1857 FloatWidth = HostTarget->getFloatWidth(); 1858 FloatAlign = HostTarget->getFloatAlign(); 1859 DoubleWidth = HostTarget->getDoubleWidth(); 1860 DoubleAlign = HostTarget->getDoubleAlign(); 1861 LongWidth = HostTarget->getLongWidth(); 1862 LongAlign = HostTarget->getLongAlign(); 1863 LongLongWidth = HostTarget->getLongLongWidth(); 1864 LongLongAlign = HostTarget->getLongLongAlign(); 1865 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1866 NewAlign = HostTarget->getNewAlign(); 1867 DefaultAlignForAttributeAligned = 1868 HostTarget->getDefaultAlignForAttributeAligned(); 1869 SizeType = HostTarget->getSizeType(); 1870 IntMaxType = HostTarget->getIntMaxType(); 1871 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1872 IntPtrType = HostTarget->getIntPtrType(); 1873 WCharType = HostTarget->getWCharType(); 1874 WIntType = HostTarget->getWIntType(); 1875 Char16Type = HostTarget->getChar16Type(); 1876 Char32Type = HostTarget->getChar32Type(); 1877 Int64Type = HostTarget->getInt64Type(); 1878 SigAtomicType = HostTarget->getSigAtomicType(); 1879 ProcessIDType = HostTarget->getProcessIDType(); 1880 1881 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1882 UseZeroLengthBitfieldAlignment = 1883 HostTarget->useZeroLengthBitfieldAlignment(); 1884 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1885 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1886 1887 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1888 // we need those macros to be identical on host and device, because (among 1889 // other things) they affect which standard library classes are defined, and 1890 // we need all classes to be defined on both the host and device. 1891 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1892 1893 // Properties intentionally not copied from host: 1894 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1895 // host/device boundary. 1896 // - SuitableAlign: Not visible across the host/device boundary, and may 1897 // correctly be different on host/device, e.g. if host has wider vector 1898 // types than device. 1899 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1900 // as its double type, but that's not necessarily true on the host. 1901 // TODO: nvcc emits a warning when using long double on device; we should 1902 // do the same. 1903 } 1904 void getTargetDefines(const LangOptions &Opts, 1905 MacroBuilder &Builder) const override { 1906 Builder.defineMacro("__PTX__"); 1907 Builder.defineMacro("__NVPTX__"); 1908 if (Opts.CUDAIsDevice) { 1909 // Set __CUDA_ARCH__ for the GPU specified. 1910 std::string CUDAArchCode = [this] { 1911 switch (GPU) { 1912 case CudaArch::UNKNOWN: 1913 assert(false && "No GPU arch when compiling CUDA device code."); 1914 return ""; 1915 case CudaArch::SM_20: 1916 return "200"; 1917 case CudaArch::SM_21: 1918 return "210"; 1919 case CudaArch::SM_30: 1920 return "300"; 1921 case CudaArch::SM_32: 1922 return "320"; 1923 case CudaArch::SM_35: 1924 return "350"; 1925 case CudaArch::SM_37: 1926 return "370"; 1927 case CudaArch::SM_50: 1928 return "500"; 1929 case CudaArch::SM_52: 1930 return "520"; 1931 case CudaArch::SM_53: 1932 return "530"; 1933 case CudaArch::SM_60: 1934 return "600"; 1935 case CudaArch::SM_61: 1936 return "610"; 1937 case CudaArch::SM_62: 1938 return "620"; 1939 } 1940 llvm_unreachable("unhandled CudaArch"); 1941 }(); 1942 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1943 } 1944 } 1945 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1946 return llvm::makeArrayRef(BuiltinInfo, 1947 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1948 } 1949 bool 1950 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1951 StringRef CPU, 1952 const std::vector<std::string> &FeaturesVec) const override { 1953 Features["satom"] = GPU >= CudaArch::SM_60; 1954 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1955 } 1956 1957 bool hasFeature(StringRef Feature) const override { 1958 return llvm::StringSwitch<bool>(Feature) 1959 .Cases("ptx", "nvptx", true) 1960 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1961 .Default(false); 1962 } 1963 1964 ArrayRef<const char *> getGCCRegNames() const override; 1965 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1966 // No aliases. 1967 return None; 1968 } 1969 bool validateAsmConstraint(const char *&Name, 1970 TargetInfo::ConstraintInfo &Info) const override { 1971 switch (*Name) { 1972 default: 1973 return false; 1974 case 'c': 1975 case 'h': 1976 case 'r': 1977 case 'l': 1978 case 'f': 1979 case 'd': 1980 Info.setAllowsRegister(); 1981 return true; 1982 } 1983 } 1984 const char *getClobbers() const override { 1985 // FIXME: Is this really right? 1986 return ""; 1987 } 1988 BuiltinVaListKind getBuiltinVaListKind() const override { 1989 // FIXME: implement 1990 return TargetInfo::CharPtrBuiltinVaList; 1991 } 1992 bool setCPU(const std::string &Name) override { 1993 GPU = StringToCudaArch(Name); 1994 return GPU != CudaArch::UNKNOWN; 1995 } 1996 void setSupportedOpenCLOpts() override { 1997 auto &Opts = getSupportedOpenCLOpts(); 1998 Opts.support("cl_clang_storage_class_specifiers"); 1999 Opts.support("cl_khr_gl_sharing"); 2000 Opts.support("cl_khr_icd"); 2001 2002 Opts.support("cl_khr_fp64"); 2003 Opts.support("cl_khr_byte_addressable_store"); 2004 Opts.support("cl_khr_global_int32_base_atomics"); 2005 Opts.support("cl_khr_global_int32_extended_atomics"); 2006 Opts.support("cl_khr_local_int32_base_atomics"); 2007 Opts.support("cl_khr_local_int32_extended_atomics"); 2008 } 2009 2010 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2011 // CUDA compilations support all of the host's calling conventions. 2012 // 2013 // TODO: We should warn if you apply a non-default CC to anything other than 2014 // a host function. 2015 if (HostTarget) 2016 return HostTarget->checkCallingConvention(CC); 2017 return CCCR_Warning; 2018 } 2019 }; 2020 2021 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 2022 #define BUILTIN(ID, TYPE, ATTRS) \ 2023 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2024 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2025 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2026 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2027 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2028 #include "clang/Basic/BuiltinsNVPTX.def" 2029 }; 2030 2031 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 2032 2033 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 2034 return llvm::makeArrayRef(GCCRegNames); 2035 } 2036 2037 static const LangAS::Map AMDGPUNonOpenCLPrivateIsZeroMap = { 2038 4, // Default 2039 1, // opencl_global 2040 3, // opencl_local 2041 2, // opencl_constant 2042 4, // opencl_generic 2043 1, // cuda_device 2044 2, // cuda_constant 2045 3 // cuda_shared 2046 }; 2047 static const LangAS::Map AMDGPUNonOpenCLGenericIsZeroMap = { 2048 0, // Default 2049 1, // opencl_global 2050 3, // opencl_local 2051 2, // opencl_constant 2052 0, // opencl_generic 2053 1, // cuda_device 2054 2, // cuda_constant 2055 3 // cuda_shared 2056 }; 2057 static const LangAS::Map AMDGPUOpenCLPrivateIsZeroMap = { 2058 0, // Default 2059 1, // opencl_global 2060 3, // opencl_local 2061 2, // opencl_constant 2062 4, // opencl_generic 2063 1, // cuda_device 2064 2, // cuda_constant 2065 3 // cuda_shared 2066 }; 2067 static const LangAS::Map AMDGPUOpenCLGenericIsZeroMap = { 2068 5, // Default 2069 1, // opencl_global 2070 3, // opencl_local 2071 2, // opencl_constant 2072 0, // opencl_generic 2073 1, // cuda_device 2074 2, // cuda_constant 2075 3 // cuda_shared 2076 }; 2077 2078 // If you edit the description strings, make sure you update 2079 // getPointerWidthV(). 2080 2081 static const char *const DataLayoutStringR600 = 2082 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2083 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2084 2085 static const char *const DataLayoutStringSIPrivateIsZero = 2086 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2087 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2088 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2089 2090 static const char *const DataLayoutStringSIGenericIsZero = 2091 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" 2092 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2093 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; 2094 2095 class AMDGPUTargetInfo final : public TargetInfo { 2096 static const Builtin::Info BuiltinInfo[]; 2097 static const char * const GCCRegNames[]; 2098 2099 struct AddrSpace { 2100 unsigned Generic, Global, Local, Constant, Private; 2101 AddrSpace(bool IsGenericZero_ = false){ 2102 if (IsGenericZero_) { 2103 Generic = 0; 2104 Global = 1; 2105 Local = 3; 2106 Constant = 2; 2107 Private = 5; 2108 } else { 2109 Generic = 4; 2110 Global = 1; 2111 Local = 3; 2112 Constant = 2; 2113 Private = 0; 2114 } 2115 } 2116 }; 2117 2118 /// \brief The GPU profiles supported by the AMDGPU target. 2119 enum GPUKind { 2120 GK_NONE, 2121 GK_R600, 2122 GK_R600_DOUBLE_OPS, 2123 GK_R700, 2124 GK_R700_DOUBLE_OPS, 2125 GK_EVERGREEN, 2126 GK_EVERGREEN_DOUBLE_OPS, 2127 GK_NORTHERN_ISLANDS, 2128 GK_CAYMAN, 2129 GK_GFX6, 2130 GK_GFX7, 2131 GK_GFX8, 2132 GK_GFX9 2133 } GPU; 2134 2135 bool hasFP64:1; 2136 bool hasFMAF:1; 2137 bool hasLDEXPF:1; 2138 const AddrSpace AS; 2139 2140 static bool hasFullSpeedFMAF32(StringRef GPUName) { 2141 return parseAMDGCNName(GPUName) >= GK_GFX9; 2142 } 2143 2144 static bool isAMDGCN(const llvm::Triple &TT) { 2145 return TT.getArch() == llvm::Triple::amdgcn; 2146 } 2147 2148 static bool isGenericZero(const llvm::Triple &TT) { 2149 return TT.getEnvironmentName() == "amdgiz" || 2150 TT.getEnvironmentName() == "amdgizcl"; 2151 } 2152 public: 2153 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2154 : TargetInfo(Triple) , 2155 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2156 hasFP64(false), 2157 hasFMAF(false), 2158 hasLDEXPF(false), 2159 AS(isGenericZero(Triple)){ 2160 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2161 hasFP64 = true; 2162 hasFMAF = true; 2163 hasLDEXPF = true; 2164 } 2165 auto IsGenericZero = isGenericZero(Triple); 2166 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2167 (IsGenericZero ? DataLayoutStringSIGenericIsZero : 2168 DataLayoutStringSIPrivateIsZero) 2169 : DataLayoutStringR600); 2170 assert(DataLayout->getAllocaAddrSpace() == AS.Private); 2171 2172 UseAddrSpaceMapMangling = true; 2173 } 2174 2175 void adjust(LangOptions &Opts) override { 2176 TargetInfo::adjust(Opts); 2177 if (isGenericZero(getTriple())) { 2178 AddrSpaceMap = Opts.OpenCL ? &AMDGPUOpenCLGenericIsZeroMap 2179 : &AMDGPUNonOpenCLGenericIsZeroMap; 2180 } else { 2181 AddrSpaceMap = Opts.OpenCL ? &AMDGPUOpenCLPrivateIsZeroMap 2182 : &AMDGPUNonOpenCLPrivateIsZeroMap; 2183 } 2184 } 2185 2186 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2187 if (GPU <= GK_CAYMAN) 2188 return 32; 2189 2190 if (AddrSpace == AS.Private || AddrSpace == AS.Local) { 2191 return 32; 2192 } 2193 return 64; 2194 } 2195 2196 uint64_t getMaxPointerWidth() const override { 2197 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2198 } 2199 2200 const char * getClobbers() const override { 2201 return ""; 2202 } 2203 2204 ArrayRef<const char *> getGCCRegNames() const override; 2205 2206 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2207 return None; 2208 } 2209 2210 bool validateAsmConstraint(const char *&Name, 2211 TargetInfo::ConstraintInfo &Info) const override { 2212 switch (*Name) { 2213 default: break; 2214 case 'v': // vgpr 2215 case 's': // sgpr 2216 Info.setAllowsRegister(); 2217 return true; 2218 } 2219 return false; 2220 } 2221 2222 bool initFeatureMap(llvm::StringMap<bool> &Features, 2223 DiagnosticsEngine &Diags, StringRef CPU, 2224 const std::vector<std::string> &FeatureVec) const override; 2225 2226 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2227 TargetOptions &TargetOpts) const override { 2228 bool hasFP32Denormals = false; 2229 bool hasFP64Denormals = false; 2230 for (auto &I : TargetOpts.FeaturesAsWritten) { 2231 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2232 hasFP32Denormals = true; 2233 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2234 hasFP64Denormals = true; 2235 } 2236 if (!hasFP32Denormals) 2237 TargetOpts.Features.push_back( 2238 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) && 2239 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2240 // Always do not flush fp64 or fp16 denorms. 2241 if (!hasFP64Denormals && hasFP64) 2242 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2243 } 2244 2245 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2246 return llvm::makeArrayRef(BuiltinInfo, 2247 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2248 } 2249 2250 void getTargetDefines(const LangOptions &Opts, 2251 MacroBuilder &Builder) const override { 2252 if (getTriple().getArch() == llvm::Triple::amdgcn) 2253 Builder.defineMacro("__AMDGCN__"); 2254 else 2255 Builder.defineMacro("__R600__"); 2256 2257 if (hasFMAF) 2258 Builder.defineMacro("__HAS_FMAF__"); 2259 if (hasLDEXPF) 2260 Builder.defineMacro("__HAS_LDEXPF__"); 2261 if (hasFP64) 2262 Builder.defineMacro("__HAS_FP64__"); 2263 } 2264 2265 BuiltinVaListKind getBuiltinVaListKind() const override { 2266 return TargetInfo::CharPtrBuiltinVaList; 2267 } 2268 2269 static GPUKind parseR600Name(StringRef Name) { 2270 return llvm::StringSwitch<GPUKind>(Name) 2271 .Case("r600" , GK_R600) 2272 .Case("rv610", GK_R600) 2273 .Case("rv620", GK_R600) 2274 .Case("rv630", GK_R600) 2275 .Case("rv635", GK_R600) 2276 .Case("rs780", GK_R600) 2277 .Case("rs880", GK_R600) 2278 .Case("rv670", GK_R600_DOUBLE_OPS) 2279 .Case("rv710", GK_R700) 2280 .Case("rv730", GK_R700) 2281 .Case("rv740", GK_R700_DOUBLE_OPS) 2282 .Case("rv770", GK_R700_DOUBLE_OPS) 2283 .Case("palm", GK_EVERGREEN) 2284 .Case("cedar", GK_EVERGREEN) 2285 .Case("sumo", GK_EVERGREEN) 2286 .Case("sumo2", GK_EVERGREEN) 2287 .Case("redwood", GK_EVERGREEN) 2288 .Case("juniper", GK_EVERGREEN) 2289 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2290 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2291 .Case("barts", GK_NORTHERN_ISLANDS) 2292 .Case("turks", GK_NORTHERN_ISLANDS) 2293 .Case("caicos", GK_NORTHERN_ISLANDS) 2294 .Case("cayman", GK_CAYMAN) 2295 .Case("aruba", GK_CAYMAN) 2296 .Default(GK_NONE); 2297 } 2298 2299 static GPUKind parseAMDGCNName(StringRef Name) { 2300 return llvm::StringSwitch<GPUKind>(Name) 2301 .Case("tahiti", GK_GFX6) 2302 .Case("pitcairn", GK_GFX6) 2303 .Case("verde", GK_GFX6) 2304 .Case("oland", GK_GFX6) 2305 .Case("hainan", GK_GFX6) 2306 .Case("bonaire", GK_GFX7) 2307 .Case("kabini", GK_GFX7) 2308 .Case("kaveri", GK_GFX7) 2309 .Case("hawaii", GK_GFX7) 2310 .Case("mullins", GK_GFX7) 2311 .Case("gfx700", GK_GFX7) 2312 .Case("gfx701", GK_GFX7) 2313 .Case("gfx702", GK_GFX7) 2314 .Case("tonga", GK_GFX8) 2315 .Case("iceland", GK_GFX8) 2316 .Case("carrizo", GK_GFX8) 2317 .Case("fiji", GK_GFX8) 2318 .Case("stoney", GK_GFX8) 2319 .Case("polaris10", GK_GFX8) 2320 .Case("polaris11", GK_GFX8) 2321 .Case("gfx800", GK_GFX8) 2322 .Case("gfx801", GK_GFX8) 2323 .Case("gfx802", GK_GFX8) 2324 .Case("gfx803", GK_GFX8) 2325 .Case("gfx804", GK_GFX8) 2326 .Case("gfx810", GK_GFX8) 2327 .Case("gfx900", GK_GFX9) 2328 .Case("gfx901", GK_GFX9) 2329 .Default(GK_NONE); 2330 } 2331 2332 bool setCPU(const std::string &Name) override { 2333 if (getTriple().getArch() == llvm::Triple::amdgcn) 2334 GPU = parseAMDGCNName(Name); 2335 else 2336 GPU = parseR600Name(Name); 2337 2338 return GPU != GK_NONE; 2339 } 2340 2341 void setSupportedOpenCLOpts() override { 2342 auto &Opts = getSupportedOpenCLOpts(); 2343 Opts.support("cl_clang_storage_class_specifiers"); 2344 Opts.support("cl_khr_icd"); 2345 2346 if (hasFP64) 2347 Opts.support("cl_khr_fp64"); 2348 if (GPU >= GK_EVERGREEN) { 2349 Opts.support("cl_khr_byte_addressable_store"); 2350 Opts.support("cl_khr_global_int32_base_atomics"); 2351 Opts.support("cl_khr_global_int32_extended_atomics"); 2352 Opts.support("cl_khr_local_int32_base_atomics"); 2353 Opts.support("cl_khr_local_int32_extended_atomics"); 2354 } 2355 if (GPU >= GK_GFX6) { 2356 Opts.support("cl_khr_fp16"); 2357 Opts.support("cl_khr_int64_base_atomics"); 2358 Opts.support("cl_khr_int64_extended_atomics"); 2359 Opts.support("cl_khr_mipmap_image"); 2360 Opts.support("cl_khr_subgroups"); 2361 Opts.support("cl_khr_3d_image_writes"); 2362 Opts.support("cl_amd_media_ops"); 2363 Opts.support("cl_amd_media_ops2"); 2364 } 2365 } 2366 2367 LangAS::ID getOpenCLImageAddrSpace() const override { 2368 return LangAS::opencl_constant; 2369 } 2370 2371 /// \returns Target specific vtbl ptr address space. 2372 unsigned getVtblPtrAddressSpace() const override { 2373 // \todo: We currently have address spaces defined in AMDGPU Backend. It 2374 // would be nice if we could use it here instead of using bare numbers (same 2375 // applies to getDWARFAddressSpace). 2376 return 2; // constant. 2377 } 2378 2379 /// \returns If a target requires an address within a target specific address 2380 /// space \p AddressSpace to be converted in order to be used, then return the 2381 /// corresponding target specific DWARF address space. 2382 /// 2383 /// \returns Otherwise return None and no conversion will be emitted in the 2384 /// DWARF. 2385 Optional<unsigned> getDWARFAddressSpace( 2386 unsigned AddressSpace) const override { 2387 const unsigned DWARF_Private = 1; 2388 const unsigned DWARF_Local = 2; 2389 if (AddressSpace == AS.Private) { 2390 return DWARF_Private; 2391 } else if (AddressSpace == AS.Local) { 2392 return DWARF_Local; 2393 } else { 2394 return None; 2395 } 2396 } 2397 2398 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2399 switch (CC) { 2400 default: 2401 return CCCR_Warning; 2402 case CC_C: 2403 case CC_OpenCLKernel: 2404 return CCCR_OK; 2405 } 2406 } 2407 2408 // In amdgcn target the null pointer in global, constant, and generic 2409 // address space has value 0 but in private and local address space has 2410 // value ~0. 2411 uint64_t getNullPointerValue(unsigned AS) const override { 2412 return AS == LangAS::opencl_local ? ~0 : 0; 2413 } 2414 }; 2415 2416 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2417 #define BUILTIN(ID, TYPE, ATTRS) \ 2418 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2419 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2420 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2421 #include "clang/Basic/BuiltinsAMDGPU.def" 2422 }; 2423 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2424 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2425 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2426 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2427 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2428 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2429 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2430 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2431 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2432 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2433 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2434 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2435 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2436 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2437 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2438 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2439 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2440 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2441 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2442 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2443 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2444 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2445 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2446 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2447 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2448 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2449 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2450 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2451 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2452 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2453 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2454 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2455 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2456 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2457 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2458 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2459 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2460 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2461 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2462 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2463 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2464 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2465 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2466 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2467 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2468 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2469 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2470 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2471 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2472 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2473 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2474 }; 2475 2476 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2477 return llvm::makeArrayRef(GCCRegNames); 2478 } 2479 2480 bool AMDGPUTargetInfo::initFeatureMap( 2481 llvm::StringMap<bool> &Features, 2482 DiagnosticsEngine &Diags, StringRef CPU, 2483 const std::vector<std::string> &FeatureVec) const { 2484 2485 // XXX - What does the member GPU mean if device name string passed here? 2486 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2487 if (CPU.empty()) 2488 CPU = "tahiti"; 2489 2490 switch (parseAMDGCNName(CPU)) { 2491 case GK_GFX6: 2492 case GK_GFX7: 2493 break; 2494 2495 case GK_GFX9: 2496 Features["gfx9-insts"] = true; 2497 LLVM_FALLTHROUGH; 2498 case GK_GFX8: 2499 Features["s-memrealtime"] = true; 2500 Features["16-bit-insts"] = true; 2501 Features["dpp"] = true; 2502 break; 2503 2504 case GK_NONE: 2505 return false; 2506 default: 2507 llvm_unreachable("unhandled subtarget"); 2508 } 2509 } else { 2510 if (CPU.empty()) 2511 CPU = "r600"; 2512 2513 switch (parseR600Name(CPU)) { 2514 case GK_R600: 2515 case GK_R700: 2516 case GK_EVERGREEN: 2517 case GK_NORTHERN_ISLANDS: 2518 break; 2519 case GK_R600_DOUBLE_OPS: 2520 case GK_R700_DOUBLE_OPS: 2521 case GK_EVERGREEN_DOUBLE_OPS: 2522 case GK_CAYMAN: 2523 Features["fp64"] = true; 2524 break; 2525 case GK_NONE: 2526 return false; 2527 default: 2528 llvm_unreachable("unhandled subtarget"); 2529 } 2530 } 2531 2532 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2533 } 2534 2535 const Builtin::Info BuiltinInfoX86[] = { 2536 #define BUILTIN(ID, TYPE, ATTRS) \ 2537 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2538 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2539 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2540 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2541 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2542 #include "clang/Basic/BuiltinsX86.def" 2543 2544 #define BUILTIN(ID, TYPE, ATTRS) \ 2545 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2546 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2547 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2548 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2549 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2550 #include "clang/Basic/BuiltinsX86_64.def" 2551 }; 2552 2553 2554 static const char* const GCCRegNames[] = { 2555 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2556 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2557 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2558 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2559 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2560 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2561 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2562 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2563 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2564 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2565 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2566 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2567 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2568 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2569 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2570 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2571 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2572 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2573 }; 2574 2575 const TargetInfo::AddlRegName AddlRegNames[] = { 2576 { { "al", "ah", "eax", "rax" }, 0 }, 2577 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2578 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2579 { { "dl", "dh", "edx", "rdx" }, 1 }, 2580 { { "esi", "rsi" }, 4 }, 2581 { { "edi", "rdi" }, 5 }, 2582 { { "esp", "rsp" }, 7 }, 2583 { { "ebp", "rbp" }, 6 }, 2584 { { "r8d", "r8w", "r8b" }, 38 }, 2585 { { "r9d", "r9w", "r9b" }, 39 }, 2586 { { "r10d", "r10w", "r10b" }, 40 }, 2587 { { "r11d", "r11w", "r11b" }, 41 }, 2588 { { "r12d", "r12w", "r12b" }, 42 }, 2589 { { "r13d", "r13w", "r13b" }, 43 }, 2590 { { "r14d", "r14w", "r14b" }, 44 }, 2591 { { "r15d", "r15w", "r15b" }, 45 }, 2592 }; 2593 2594 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2595 // most of the implementation can be shared. 2596 class X86TargetInfo : public TargetInfo { 2597 enum X86SSEEnum { 2598 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2599 } SSELevel = NoSSE; 2600 enum MMX3DNowEnum { 2601 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2602 } MMX3DNowLevel = NoMMX3DNow; 2603 enum XOPEnum { 2604 NoXOP, 2605 SSE4A, 2606 FMA4, 2607 XOP 2608 } XOPLevel = NoXOP; 2609 2610 bool HasAES = false; 2611 bool HasPCLMUL = false; 2612 bool HasLZCNT = false; 2613 bool HasRDRND = false; 2614 bool HasFSGSBASE = false; 2615 bool HasBMI = false; 2616 bool HasBMI2 = false; 2617 bool HasPOPCNT = false; 2618 bool HasRTM = false; 2619 bool HasPRFCHW = false; 2620 bool HasRDSEED = false; 2621 bool HasADX = false; 2622 bool HasTBM = false; 2623 bool HasLWP = false; 2624 bool HasFMA = false; 2625 bool HasF16C = false; 2626 bool HasAVX512CD = false; 2627 bool HasAVX512VPOPCNTDQ = false; 2628 bool HasAVX512ER = false; 2629 bool HasAVX512PF = false; 2630 bool HasAVX512DQ = false; 2631 bool HasAVX512BW = false; 2632 bool HasAVX512VL = false; 2633 bool HasAVX512VBMI = false; 2634 bool HasAVX512IFMA = false; 2635 bool HasSHA = false; 2636 bool HasMPX = false; 2637 bool HasSGX = false; 2638 bool HasCX16 = false; 2639 bool HasFXSR = false; 2640 bool HasXSAVE = false; 2641 bool HasXSAVEOPT = false; 2642 bool HasXSAVEC = false; 2643 bool HasXSAVES = false; 2644 bool HasMWAITX = false; 2645 bool HasCLZERO = false; 2646 bool HasPKU = false; 2647 bool HasCLFLUSHOPT = false; 2648 bool HasCLWB = false; 2649 bool HasMOVBE = false; 2650 bool HasPREFETCHWT1 = false; 2651 2652 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2653 /// 2654 /// Each enumeration represents a particular CPU supported by Clang. These 2655 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2656 enum CPUKind { 2657 CK_Generic, 2658 2659 /// \name i386 2660 /// i386-generation processors. 2661 //@{ 2662 CK_i386, 2663 //@} 2664 2665 /// \name i486 2666 /// i486-generation processors. 2667 //@{ 2668 CK_i486, 2669 CK_WinChipC6, 2670 CK_WinChip2, 2671 CK_C3, 2672 //@} 2673 2674 /// \name i586 2675 /// i586-generation processors, P5 microarchitecture based. 2676 //@{ 2677 CK_i586, 2678 CK_Pentium, 2679 CK_PentiumMMX, 2680 //@} 2681 2682 /// \name i686 2683 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2684 //@{ 2685 CK_i686, 2686 CK_PentiumPro, 2687 CK_Pentium2, 2688 CK_Pentium3, 2689 CK_Pentium3M, 2690 CK_PentiumM, 2691 CK_C3_2, 2692 2693 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2694 /// Clang however has some logic to suport this. 2695 // FIXME: Warn, deprecate, and potentially remove this. 2696 CK_Yonah, 2697 //@} 2698 2699 /// \name Netburst 2700 /// Netburst microarchitecture based processors. 2701 //@{ 2702 CK_Pentium4, 2703 CK_Pentium4M, 2704 CK_Prescott, 2705 CK_Nocona, 2706 //@} 2707 2708 /// \name Core 2709 /// Core microarchitecture based processors. 2710 //@{ 2711 CK_Core2, 2712 2713 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2714 /// codename which GCC no longer accepts as an option to -march, but Clang 2715 /// has some logic for recognizing it. 2716 // FIXME: Warn, deprecate, and potentially remove this. 2717 CK_Penryn, 2718 //@} 2719 2720 /// \name Atom 2721 /// Atom processors 2722 //@{ 2723 CK_Bonnell, 2724 CK_Silvermont, 2725 //@} 2726 2727 /// \name Nehalem 2728 /// Nehalem microarchitecture based processors. 2729 CK_Nehalem, 2730 2731 /// \name Westmere 2732 /// Westmere microarchitecture based processors. 2733 CK_Westmere, 2734 2735 /// \name Sandy Bridge 2736 /// Sandy Bridge microarchitecture based processors. 2737 CK_SandyBridge, 2738 2739 /// \name Ivy Bridge 2740 /// Ivy Bridge microarchitecture based processors. 2741 CK_IvyBridge, 2742 2743 /// \name Haswell 2744 /// Haswell microarchitecture based processors. 2745 CK_Haswell, 2746 2747 /// \name Broadwell 2748 /// Broadwell microarchitecture based processors. 2749 CK_Broadwell, 2750 2751 /// \name Skylake Client 2752 /// Skylake client microarchitecture based processors. 2753 CK_SkylakeClient, 2754 2755 /// \name Skylake Server 2756 /// Skylake server microarchitecture based processors. 2757 CK_SkylakeServer, 2758 2759 /// \name Cannonlake Client 2760 /// Cannonlake client microarchitecture based processors. 2761 CK_Cannonlake, 2762 2763 /// \name Knights Landing 2764 /// Knights Landing processor. 2765 CK_KNL, 2766 2767 /// \name Lakemont 2768 /// Lakemont microarchitecture based processors. 2769 CK_Lakemont, 2770 2771 /// \name K6 2772 /// K6 architecture processors. 2773 //@{ 2774 CK_K6, 2775 CK_K6_2, 2776 CK_K6_3, 2777 //@} 2778 2779 /// \name K7 2780 /// K7 architecture processors. 2781 //@{ 2782 CK_Athlon, 2783 CK_AthlonThunderbird, 2784 CK_Athlon4, 2785 CK_AthlonXP, 2786 CK_AthlonMP, 2787 //@} 2788 2789 /// \name K8 2790 /// K8 architecture processors. 2791 //@{ 2792 CK_Athlon64, 2793 CK_Athlon64SSE3, 2794 CK_AthlonFX, 2795 CK_K8, 2796 CK_K8SSE3, 2797 CK_Opteron, 2798 CK_OpteronSSE3, 2799 CK_AMDFAM10, 2800 //@} 2801 2802 /// \name Bobcat 2803 /// Bobcat architecture processors. 2804 //@{ 2805 CK_BTVER1, 2806 CK_BTVER2, 2807 //@} 2808 2809 /// \name Bulldozer 2810 /// Bulldozer architecture processors. 2811 //@{ 2812 CK_BDVER1, 2813 CK_BDVER2, 2814 CK_BDVER3, 2815 CK_BDVER4, 2816 //@} 2817 2818 /// \name zen 2819 /// Zen architecture processors. 2820 //@{ 2821 CK_ZNVER1, 2822 //@} 2823 2824 /// This specification is deprecated and will be removed in the future. 2825 /// Users should prefer \see CK_K8. 2826 // FIXME: Warn on this when the CPU is set to it. 2827 //@{ 2828 CK_x86_64, 2829 //@} 2830 2831 /// \name Geode 2832 /// Geode processors. 2833 //@{ 2834 CK_Geode 2835 //@} 2836 } CPU = CK_Generic; 2837 2838 CPUKind getCPUKind(StringRef CPU) const { 2839 return llvm::StringSwitch<CPUKind>(CPU) 2840 .Case("i386", CK_i386) 2841 .Case("i486", CK_i486) 2842 .Case("winchip-c6", CK_WinChipC6) 2843 .Case("winchip2", CK_WinChip2) 2844 .Case("c3", CK_C3) 2845 .Case("i586", CK_i586) 2846 .Case("pentium", CK_Pentium) 2847 .Case("pentium-mmx", CK_PentiumMMX) 2848 .Case("i686", CK_i686) 2849 .Case("pentiumpro", CK_PentiumPro) 2850 .Case("pentium2", CK_Pentium2) 2851 .Case("pentium3", CK_Pentium3) 2852 .Case("pentium3m", CK_Pentium3M) 2853 .Case("pentium-m", CK_PentiumM) 2854 .Case("c3-2", CK_C3_2) 2855 .Case("yonah", CK_Yonah) 2856 .Case("pentium4", CK_Pentium4) 2857 .Case("pentium4m", CK_Pentium4M) 2858 .Case("prescott", CK_Prescott) 2859 .Case("nocona", CK_Nocona) 2860 .Case("core2", CK_Core2) 2861 .Case("penryn", CK_Penryn) 2862 .Case("bonnell", CK_Bonnell) 2863 .Case("atom", CK_Bonnell) // Legacy name. 2864 .Case("silvermont", CK_Silvermont) 2865 .Case("slm", CK_Silvermont) // Legacy name. 2866 .Case("nehalem", CK_Nehalem) 2867 .Case("corei7", CK_Nehalem) // Legacy name. 2868 .Case("westmere", CK_Westmere) 2869 .Case("sandybridge", CK_SandyBridge) 2870 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2871 .Case("ivybridge", CK_IvyBridge) 2872 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2873 .Case("haswell", CK_Haswell) 2874 .Case("core-avx2", CK_Haswell) // Legacy name. 2875 .Case("broadwell", CK_Broadwell) 2876 .Case("skylake", CK_SkylakeClient) 2877 .Case("skylake-avx512", CK_SkylakeServer) 2878 .Case("skx", CK_SkylakeServer) // Legacy name. 2879 .Case("cannonlake", CK_Cannonlake) 2880 .Case("knl", CK_KNL) 2881 .Case("lakemont", CK_Lakemont) 2882 .Case("k6", CK_K6) 2883 .Case("k6-2", CK_K6_2) 2884 .Case("k6-3", CK_K6_3) 2885 .Case("athlon", CK_Athlon) 2886 .Case("athlon-tbird", CK_AthlonThunderbird) 2887 .Case("athlon-4", CK_Athlon4) 2888 .Case("athlon-xp", CK_AthlonXP) 2889 .Case("athlon-mp", CK_AthlonMP) 2890 .Case("athlon64", CK_Athlon64) 2891 .Case("athlon64-sse3", CK_Athlon64SSE3) 2892 .Case("athlon-fx", CK_AthlonFX) 2893 .Case("k8", CK_K8) 2894 .Case("k8-sse3", CK_K8SSE3) 2895 .Case("opteron", CK_Opteron) 2896 .Case("opteron-sse3", CK_OpteronSSE3) 2897 .Case("barcelona", CK_AMDFAM10) 2898 .Case("amdfam10", CK_AMDFAM10) 2899 .Case("btver1", CK_BTVER1) 2900 .Case("btver2", CK_BTVER2) 2901 .Case("bdver1", CK_BDVER1) 2902 .Case("bdver2", CK_BDVER2) 2903 .Case("bdver3", CK_BDVER3) 2904 .Case("bdver4", CK_BDVER4) 2905 .Case("znver1", CK_ZNVER1) 2906 .Case("x86-64", CK_x86_64) 2907 .Case("geode", CK_Geode) 2908 .Default(CK_Generic); 2909 } 2910 2911 enum FPMathKind { 2912 FP_Default, 2913 FP_SSE, 2914 FP_387 2915 } FPMath = FP_Default; 2916 2917 public: 2918 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2919 : TargetInfo(Triple) { 2920 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2921 } 2922 unsigned getFloatEvalMethod() const override { 2923 // X87 evaluates with 80 bits "long double" precision. 2924 return SSELevel == NoSSE ? 2 : 0; 2925 } 2926 ArrayRef<const char *> getGCCRegNames() const override { 2927 return llvm::makeArrayRef(GCCRegNames); 2928 } 2929 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2930 return None; 2931 } 2932 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2933 return llvm::makeArrayRef(AddlRegNames); 2934 } 2935 bool validateCpuSupports(StringRef Name) const override; 2936 bool validateAsmConstraint(const char *&Name, 2937 TargetInfo::ConstraintInfo &info) const override; 2938 2939 bool validateGlobalRegisterVariable(StringRef RegName, 2940 unsigned RegSize, 2941 bool &HasSizeMismatch) const override { 2942 // esp and ebp are the only 32-bit registers the x86 backend can currently 2943 // handle. 2944 if (RegName.equals("esp") || RegName.equals("ebp")) { 2945 // Check that the register size is 32-bit. 2946 HasSizeMismatch = RegSize != 32; 2947 return true; 2948 } 2949 2950 return false; 2951 } 2952 2953 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2954 2955 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2956 2957 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2958 2959 std::string convertConstraint(const char *&Constraint) const override; 2960 const char *getClobbers() const override { 2961 return "~{dirflag},~{fpsr},~{flags}"; 2962 } 2963 2964 StringRef getConstraintRegister(const StringRef &Constraint, 2965 const StringRef &Expression) const override { 2966 StringRef::iterator I, E; 2967 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 2968 if (isalpha(*I)) 2969 break; 2970 } 2971 if (I == E) 2972 return ""; 2973 switch (*I) { 2974 // For the register constraints, return the matching register name 2975 case 'a': 2976 return "ax"; 2977 case 'b': 2978 return "bx"; 2979 case 'c': 2980 return "cx"; 2981 case 'd': 2982 return "dx"; 2983 case 'S': 2984 return "si"; 2985 case 'D': 2986 return "di"; 2987 // In case the constraint is 'r' we need to return Expression 2988 case 'r': 2989 return Expression; 2990 default: 2991 // Default value if there is no constraint for the register 2992 return ""; 2993 } 2994 return ""; 2995 } 2996 2997 void getTargetDefines(const LangOptions &Opts, 2998 MacroBuilder &Builder) const override; 2999 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 3000 bool Enabled); 3001 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 3002 bool Enabled); 3003 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3004 bool Enabled); 3005 void setFeatureEnabled(llvm::StringMap<bool> &Features, 3006 StringRef Name, bool Enabled) const override { 3007 setFeatureEnabledImpl(Features, Name, Enabled); 3008 } 3009 // This exists purely to cut down on the number of virtual calls in 3010 // initFeatureMap which calls this repeatedly. 3011 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3012 StringRef Name, bool Enabled); 3013 bool 3014 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 3015 StringRef CPU, 3016 const std::vector<std::string> &FeaturesVec) const override; 3017 bool hasFeature(StringRef Feature) const override; 3018 bool handleTargetFeatures(std::vector<std::string> &Features, 3019 DiagnosticsEngine &Diags) override; 3020 StringRef getABI() const override { 3021 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 3022 return "avx512"; 3023 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 3024 return "avx"; 3025 if (getTriple().getArch() == llvm::Triple::x86 && 3026 MMX3DNowLevel == NoMMX3DNow) 3027 return "no-mmx"; 3028 return ""; 3029 } 3030 bool setCPU(const std::string &Name) override { 3031 CPU = getCPUKind(Name); 3032 3033 // Perform any per-CPU checks necessary to determine if this CPU is 3034 // acceptable. 3035 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 3036 // invalid without explaining *why*. 3037 switch (CPU) { 3038 case CK_Generic: 3039 // No processor selected! 3040 return false; 3041 3042 case CK_i386: 3043 case CK_i486: 3044 case CK_WinChipC6: 3045 case CK_WinChip2: 3046 case CK_C3: 3047 case CK_i586: 3048 case CK_Pentium: 3049 case CK_PentiumMMX: 3050 case CK_i686: 3051 case CK_PentiumPro: 3052 case CK_Pentium2: 3053 case CK_Pentium3: 3054 case CK_Pentium3M: 3055 case CK_PentiumM: 3056 case CK_Yonah: 3057 case CK_C3_2: 3058 case CK_Pentium4: 3059 case CK_Pentium4M: 3060 case CK_Lakemont: 3061 case CK_Prescott: 3062 case CK_K6: 3063 case CK_K6_2: 3064 case CK_K6_3: 3065 case CK_Athlon: 3066 case CK_AthlonThunderbird: 3067 case CK_Athlon4: 3068 case CK_AthlonXP: 3069 case CK_AthlonMP: 3070 case CK_Geode: 3071 // Only accept certain architectures when compiling in 32-bit mode. 3072 if (getTriple().getArch() != llvm::Triple::x86) 3073 return false; 3074 3075 // Fallthrough 3076 case CK_Nocona: 3077 case CK_Core2: 3078 case CK_Penryn: 3079 case CK_Bonnell: 3080 case CK_Silvermont: 3081 case CK_Nehalem: 3082 case CK_Westmere: 3083 case CK_SandyBridge: 3084 case CK_IvyBridge: 3085 case CK_Haswell: 3086 case CK_Broadwell: 3087 case CK_SkylakeClient: 3088 case CK_SkylakeServer: 3089 case CK_Cannonlake: 3090 case CK_KNL: 3091 case CK_Athlon64: 3092 case CK_Athlon64SSE3: 3093 case CK_AthlonFX: 3094 case CK_K8: 3095 case CK_K8SSE3: 3096 case CK_Opteron: 3097 case CK_OpteronSSE3: 3098 case CK_AMDFAM10: 3099 case CK_BTVER1: 3100 case CK_BTVER2: 3101 case CK_BDVER1: 3102 case CK_BDVER2: 3103 case CK_BDVER3: 3104 case CK_BDVER4: 3105 case CK_ZNVER1: 3106 case CK_x86_64: 3107 return true; 3108 } 3109 llvm_unreachable("Unhandled CPU kind"); 3110 } 3111 3112 bool setFPMath(StringRef Name) override; 3113 3114 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3115 // Most of the non-ARM calling conventions are i386 conventions. 3116 switch (CC) { 3117 case CC_X86ThisCall: 3118 case CC_X86FastCall: 3119 case CC_X86StdCall: 3120 case CC_X86VectorCall: 3121 case CC_X86RegCall: 3122 case CC_C: 3123 case CC_Swift: 3124 case CC_X86Pascal: 3125 case CC_IntelOclBicc: 3126 return CCCR_OK; 3127 default: 3128 return CCCR_Warning; 3129 } 3130 } 3131 3132 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3133 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 3134 } 3135 3136 bool hasSjLjLowering() const override { 3137 return true; 3138 } 3139 3140 void setSupportedOpenCLOpts() override { 3141 getSupportedOpenCLOpts().supportAll(); 3142 } 3143 }; 3144 3145 bool X86TargetInfo::setFPMath(StringRef Name) { 3146 if (Name == "387") { 3147 FPMath = FP_387; 3148 return true; 3149 } 3150 if (Name == "sse") { 3151 FPMath = FP_SSE; 3152 return true; 3153 } 3154 return false; 3155 } 3156 3157 bool X86TargetInfo::initFeatureMap( 3158 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3159 const std::vector<std::string> &FeaturesVec) const { 3160 // FIXME: This *really* should not be here. 3161 // X86_64 always has SSE2. 3162 if (getTriple().getArch() == llvm::Triple::x86_64) 3163 setFeatureEnabledImpl(Features, "sse2", true); 3164 3165 const CPUKind Kind = getCPUKind(CPU); 3166 3167 // Enable X87 for all X86 processors but Lakemont. 3168 if (Kind != CK_Lakemont) 3169 setFeatureEnabledImpl(Features, "x87", true); 3170 3171 switch (Kind) { 3172 case CK_Generic: 3173 case CK_i386: 3174 case CK_i486: 3175 case CK_i586: 3176 case CK_Pentium: 3177 case CK_i686: 3178 case CK_PentiumPro: 3179 case CK_Lakemont: 3180 break; 3181 case CK_PentiumMMX: 3182 case CK_Pentium2: 3183 case CK_K6: 3184 case CK_WinChipC6: 3185 setFeatureEnabledImpl(Features, "mmx", true); 3186 break; 3187 case CK_Pentium3: 3188 case CK_Pentium3M: 3189 case CK_C3_2: 3190 setFeatureEnabledImpl(Features, "sse", true); 3191 setFeatureEnabledImpl(Features, "fxsr", true); 3192 break; 3193 case CK_PentiumM: 3194 case CK_Pentium4: 3195 case CK_Pentium4M: 3196 case CK_x86_64: 3197 setFeatureEnabledImpl(Features, "sse2", true); 3198 setFeatureEnabledImpl(Features, "fxsr", true); 3199 break; 3200 case CK_Yonah: 3201 case CK_Prescott: 3202 case CK_Nocona: 3203 setFeatureEnabledImpl(Features, "sse3", true); 3204 setFeatureEnabledImpl(Features, "fxsr", true); 3205 setFeatureEnabledImpl(Features, "cx16", true); 3206 break; 3207 case CK_Core2: 3208 case CK_Bonnell: 3209 setFeatureEnabledImpl(Features, "ssse3", true); 3210 setFeatureEnabledImpl(Features, "fxsr", true); 3211 setFeatureEnabledImpl(Features, "cx16", true); 3212 break; 3213 case CK_Penryn: 3214 setFeatureEnabledImpl(Features, "sse4.1", true); 3215 setFeatureEnabledImpl(Features, "fxsr", true); 3216 setFeatureEnabledImpl(Features, "cx16", true); 3217 break; 3218 case CK_Cannonlake: 3219 setFeatureEnabledImpl(Features, "avx512ifma", true); 3220 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3221 setFeatureEnabledImpl(Features, "sha", true); 3222 LLVM_FALLTHROUGH; 3223 case CK_SkylakeServer: 3224 setFeatureEnabledImpl(Features, "avx512f", true); 3225 setFeatureEnabledImpl(Features, "avx512cd", true); 3226 setFeatureEnabledImpl(Features, "avx512dq", true); 3227 setFeatureEnabledImpl(Features, "avx512bw", true); 3228 setFeatureEnabledImpl(Features, "avx512vl", true); 3229 setFeatureEnabledImpl(Features, "pku", true); 3230 setFeatureEnabledImpl(Features, "clwb", true); 3231 LLVM_FALLTHROUGH; 3232 case CK_SkylakeClient: 3233 setFeatureEnabledImpl(Features, "xsavec", true); 3234 setFeatureEnabledImpl(Features, "xsaves", true); 3235 setFeatureEnabledImpl(Features, "mpx", true); 3236 setFeatureEnabledImpl(Features, "sgx", true); 3237 setFeatureEnabledImpl(Features, "clflushopt", true); 3238 setFeatureEnabledImpl(Features, "rtm", true); 3239 LLVM_FALLTHROUGH; 3240 case CK_Broadwell: 3241 setFeatureEnabledImpl(Features, "rdseed", true); 3242 setFeatureEnabledImpl(Features, "adx", true); 3243 LLVM_FALLTHROUGH; 3244 case CK_Haswell: 3245 setFeatureEnabledImpl(Features, "avx2", true); 3246 setFeatureEnabledImpl(Features, "lzcnt", true); 3247 setFeatureEnabledImpl(Features, "bmi", true); 3248 setFeatureEnabledImpl(Features, "bmi2", true); 3249 setFeatureEnabledImpl(Features, "fma", true); 3250 setFeatureEnabledImpl(Features, "movbe", true); 3251 LLVM_FALLTHROUGH; 3252 case CK_IvyBridge: 3253 setFeatureEnabledImpl(Features, "rdrnd", true); 3254 setFeatureEnabledImpl(Features, "f16c", true); 3255 setFeatureEnabledImpl(Features, "fsgsbase", true); 3256 LLVM_FALLTHROUGH; 3257 case CK_SandyBridge: 3258 setFeatureEnabledImpl(Features, "avx", true); 3259 setFeatureEnabledImpl(Features, "xsave", true); 3260 setFeatureEnabledImpl(Features, "xsaveopt", true); 3261 LLVM_FALLTHROUGH; 3262 case CK_Westmere: 3263 case CK_Silvermont: 3264 setFeatureEnabledImpl(Features, "aes", true); 3265 setFeatureEnabledImpl(Features, "pclmul", true); 3266 LLVM_FALLTHROUGH; 3267 case CK_Nehalem: 3268 setFeatureEnabledImpl(Features, "sse4.2", true); 3269 setFeatureEnabledImpl(Features, "fxsr", true); 3270 setFeatureEnabledImpl(Features, "cx16", true); 3271 break; 3272 case CK_KNL: 3273 setFeatureEnabledImpl(Features, "avx512f", true); 3274 setFeatureEnabledImpl(Features, "avx512cd", true); 3275 setFeatureEnabledImpl(Features, "avx512er", true); 3276 setFeatureEnabledImpl(Features, "avx512pf", true); 3277 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3278 setFeatureEnabledImpl(Features, "fxsr", true); 3279 setFeatureEnabledImpl(Features, "rdseed", true); 3280 setFeatureEnabledImpl(Features, "adx", true); 3281 setFeatureEnabledImpl(Features, "lzcnt", true); 3282 setFeatureEnabledImpl(Features, "bmi", true); 3283 setFeatureEnabledImpl(Features, "bmi2", true); 3284 setFeatureEnabledImpl(Features, "rtm", true); 3285 setFeatureEnabledImpl(Features, "fma", true); 3286 setFeatureEnabledImpl(Features, "rdrnd", true); 3287 setFeatureEnabledImpl(Features, "f16c", true); 3288 setFeatureEnabledImpl(Features, "fsgsbase", true); 3289 setFeatureEnabledImpl(Features, "aes", true); 3290 setFeatureEnabledImpl(Features, "pclmul", true); 3291 setFeatureEnabledImpl(Features, "cx16", true); 3292 setFeatureEnabledImpl(Features, "xsaveopt", true); 3293 setFeatureEnabledImpl(Features, "xsave", true); 3294 setFeatureEnabledImpl(Features, "movbe", true); 3295 break; 3296 case CK_K6_2: 3297 case CK_K6_3: 3298 case CK_WinChip2: 3299 case CK_C3: 3300 setFeatureEnabledImpl(Features, "3dnow", true); 3301 break; 3302 case CK_Athlon: 3303 case CK_AthlonThunderbird: 3304 case CK_Geode: 3305 setFeatureEnabledImpl(Features, "3dnowa", true); 3306 break; 3307 case CK_Athlon4: 3308 case CK_AthlonXP: 3309 case CK_AthlonMP: 3310 setFeatureEnabledImpl(Features, "sse", true); 3311 setFeatureEnabledImpl(Features, "3dnowa", true); 3312 setFeatureEnabledImpl(Features, "fxsr", true); 3313 break; 3314 case CK_K8: 3315 case CK_Opteron: 3316 case CK_Athlon64: 3317 case CK_AthlonFX: 3318 setFeatureEnabledImpl(Features, "sse2", true); 3319 setFeatureEnabledImpl(Features, "3dnowa", true); 3320 setFeatureEnabledImpl(Features, "fxsr", true); 3321 break; 3322 case CK_AMDFAM10: 3323 setFeatureEnabledImpl(Features, "sse4a", true); 3324 setFeatureEnabledImpl(Features, "lzcnt", true); 3325 setFeatureEnabledImpl(Features, "popcnt", true); 3326 LLVM_FALLTHROUGH; 3327 case CK_K8SSE3: 3328 case CK_OpteronSSE3: 3329 case CK_Athlon64SSE3: 3330 setFeatureEnabledImpl(Features, "sse3", true); 3331 setFeatureEnabledImpl(Features, "3dnowa", true); 3332 setFeatureEnabledImpl(Features, "fxsr", true); 3333 break; 3334 case CK_BTVER2: 3335 setFeatureEnabledImpl(Features, "avx", true); 3336 setFeatureEnabledImpl(Features, "aes", true); 3337 setFeatureEnabledImpl(Features, "pclmul", true); 3338 setFeatureEnabledImpl(Features, "bmi", true); 3339 setFeatureEnabledImpl(Features, "f16c", true); 3340 setFeatureEnabledImpl(Features, "xsaveopt", true); 3341 LLVM_FALLTHROUGH; 3342 case CK_BTVER1: 3343 setFeatureEnabledImpl(Features, "ssse3", true); 3344 setFeatureEnabledImpl(Features, "sse4a", true); 3345 setFeatureEnabledImpl(Features, "lzcnt", true); 3346 setFeatureEnabledImpl(Features, "popcnt", true); 3347 setFeatureEnabledImpl(Features, "prfchw", true); 3348 setFeatureEnabledImpl(Features, "cx16", true); 3349 setFeatureEnabledImpl(Features, "fxsr", true); 3350 break; 3351 case CK_ZNVER1: 3352 setFeatureEnabledImpl(Features, "adx", true); 3353 setFeatureEnabledImpl(Features, "aes", true); 3354 setFeatureEnabledImpl(Features, "avx2", true); 3355 setFeatureEnabledImpl(Features, "bmi", true); 3356 setFeatureEnabledImpl(Features, "bmi2", true); 3357 setFeatureEnabledImpl(Features, "clflushopt", true); 3358 setFeatureEnabledImpl(Features, "clzero", true); 3359 setFeatureEnabledImpl(Features, "cx16", true); 3360 setFeatureEnabledImpl(Features, "f16c", true); 3361 setFeatureEnabledImpl(Features, "fma", true); 3362 setFeatureEnabledImpl(Features, "fsgsbase", true); 3363 setFeatureEnabledImpl(Features, "fxsr", true); 3364 setFeatureEnabledImpl(Features, "lzcnt", true); 3365 setFeatureEnabledImpl(Features, "mwaitx", true); 3366 setFeatureEnabledImpl(Features, "movbe", true); 3367 setFeatureEnabledImpl(Features, "pclmul", true); 3368 setFeatureEnabledImpl(Features, "popcnt", true); 3369 setFeatureEnabledImpl(Features, "prfchw", true); 3370 setFeatureEnabledImpl(Features, "rdrnd", true); 3371 setFeatureEnabledImpl(Features, "rdseed", true); 3372 setFeatureEnabledImpl(Features, "sha", true); 3373 setFeatureEnabledImpl(Features, "sse4a", true); 3374 setFeatureEnabledImpl(Features, "xsave", true); 3375 setFeatureEnabledImpl(Features, "xsavec", true); 3376 setFeatureEnabledImpl(Features, "xsaveopt", true); 3377 setFeatureEnabledImpl(Features, "xsaves", true); 3378 break; 3379 case CK_BDVER4: 3380 setFeatureEnabledImpl(Features, "avx2", true); 3381 setFeatureEnabledImpl(Features, "bmi2", true); 3382 setFeatureEnabledImpl(Features, "mwaitx", true); 3383 LLVM_FALLTHROUGH; 3384 case CK_BDVER3: 3385 setFeatureEnabledImpl(Features, "fsgsbase", true); 3386 setFeatureEnabledImpl(Features, "xsaveopt", true); 3387 LLVM_FALLTHROUGH; 3388 case CK_BDVER2: 3389 setFeatureEnabledImpl(Features, "bmi", true); 3390 setFeatureEnabledImpl(Features, "fma", true); 3391 setFeatureEnabledImpl(Features, "f16c", true); 3392 setFeatureEnabledImpl(Features, "tbm", true); 3393 LLVM_FALLTHROUGH; 3394 case CK_BDVER1: 3395 // xop implies avx, sse4a and fma4. 3396 setFeatureEnabledImpl(Features, "xop", true); 3397 setFeatureEnabledImpl(Features, "lwp", true); 3398 setFeatureEnabledImpl(Features, "lzcnt", true); 3399 setFeatureEnabledImpl(Features, "aes", true); 3400 setFeatureEnabledImpl(Features, "pclmul", true); 3401 setFeatureEnabledImpl(Features, "prfchw", true); 3402 setFeatureEnabledImpl(Features, "cx16", true); 3403 setFeatureEnabledImpl(Features, "fxsr", true); 3404 setFeatureEnabledImpl(Features, "xsave", true); 3405 break; 3406 } 3407 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3408 return false; 3409 3410 // Can't do this earlier because we need to be able to explicitly enable 3411 // or disable these features and the things that they depend upon. 3412 3413 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3414 auto I = Features.find("sse4.2"); 3415 if (I != Features.end() && I->getValue() && 3416 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3417 FeaturesVec.end()) 3418 Features["popcnt"] = true; 3419 3420 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3421 I = Features.find("3dnow"); 3422 if (I != Features.end() && I->getValue() && 3423 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3424 FeaturesVec.end()) 3425 Features["prfchw"] = true; 3426 3427 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3428 // then enable MMX. 3429 I = Features.find("sse"); 3430 if (I != Features.end() && I->getValue() && 3431 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3432 FeaturesVec.end()) 3433 Features["mmx"] = true; 3434 3435 return true; 3436 } 3437 3438 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3439 X86SSEEnum Level, bool Enabled) { 3440 if (Enabled) { 3441 switch (Level) { 3442 case AVX512F: 3443 Features["avx512f"] = true; 3444 LLVM_FALLTHROUGH; 3445 case AVX2: 3446 Features["avx2"] = true; 3447 LLVM_FALLTHROUGH; 3448 case AVX: 3449 Features["avx"] = true; 3450 Features["xsave"] = true; 3451 LLVM_FALLTHROUGH; 3452 case SSE42: 3453 Features["sse4.2"] = true; 3454 LLVM_FALLTHROUGH; 3455 case SSE41: 3456 Features["sse4.1"] = true; 3457 LLVM_FALLTHROUGH; 3458 case SSSE3: 3459 Features["ssse3"] = true; 3460 LLVM_FALLTHROUGH; 3461 case SSE3: 3462 Features["sse3"] = true; 3463 LLVM_FALLTHROUGH; 3464 case SSE2: 3465 Features["sse2"] = true; 3466 LLVM_FALLTHROUGH; 3467 case SSE1: 3468 Features["sse"] = true; 3469 LLVM_FALLTHROUGH; 3470 case NoSSE: 3471 break; 3472 } 3473 return; 3474 } 3475 3476 switch (Level) { 3477 case NoSSE: 3478 case SSE1: 3479 Features["sse"] = false; 3480 LLVM_FALLTHROUGH; 3481 case SSE2: 3482 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3483 Features["sha"] = false; 3484 LLVM_FALLTHROUGH; 3485 case SSE3: 3486 Features["sse3"] = false; 3487 setXOPLevel(Features, NoXOP, false); 3488 LLVM_FALLTHROUGH; 3489 case SSSE3: 3490 Features["ssse3"] = false; 3491 LLVM_FALLTHROUGH; 3492 case SSE41: 3493 Features["sse4.1"] = false; 3494 LLVM_FALLTHROUGH; 3495 case SSE42: 3496 Features["sse4.2"] = false; 3497 LLVM_FALLTHROUGH; 3498 case AVX: 3499 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3500 Features["xsaveopt"] = false; 3501 setXOPLevel(Features, FMA4, false); 3502 LLVM_FALLTHROUGH; 3503 case AVX2: 3504 Features["avx2"] = false; 3505 LLVM_FALLTHROUGH; 3506 case AVX512F: 3507 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3508 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3509 Features["avx512vl"] = Features["avx512vbmi"] = 3510 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 3511 } 3512 } 3513 3514 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3515 MMX3DNowEnum Level, bool Enabled) { 3516 if (Enabled) { 3517 switch (Level) { 3518 case AMD3DNowAthlon: 3519 Features["3dnowa"] = true; 3520 LLVM_FALLTHROUGH; 3521 case AMD3DNow: 3522 Features["3dnow"] = true; 3523 LLVM_FALLTHROUGH; 3524 case MMX: 3525 Features["mmx"] = true; 3526 LLVM_FALLTHROUGH; 3527 case NoMMX3DNow: 3528 break; 3529 } 3530 return; 3531 } 3532 3533 switch (Level) { 3534 case NoMMX3DNow: 3535 case MMX: 3536 Features["mmx"] = false; 3537 LLVM_FALLTHROUGH; 3538 case AMD3DNow: 3539 Features["3dnow"] = false; 3540 LLVM_FALLTHROUGH; 3541 case AMD3DNowAthlon: 3542 Features["3dnowa"] = false; 3543 } 3544 } 3545 3546 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3547 bool Enabled) { 3548 if (Enabled) { 3549 switch (Level) { 3550 case XOP: 3551 Features["xop"] = true; 3552 LLVM_FALLTHROUGH; 3553 case FMA4: 3554 Features["fma4"] = true; 3555 setSSELevel(Features, AVX, true); 3556 LLVM_FALLTHROUGH; 3557 case SSE4A: 3558 Features["sse4a"] = true; 3559 setSSELevel(Features, SSE3, true); 3560 LLVM_FALLTHROUGH; 3561 case NoXOP: 3562 break; 3563 } 3564 return; 3565 } 3566 3567 switch (Level) { 3568 case NoXOP: 3569 case SSE4A: 3570 Features["sse4a"] = false; 3571 LLVM_FALLTHROUGH; 3572 case FMA4: 3573 Features["fma4"] = false; 3574 LLVM_FALLTHROUGH; 3575 case XOP: 3576 Features["xop"] = false; 3577 } 3578 } 3579 3580 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3581 StringRef Name, bool Enabled) { 3582 // This is a bit of a hack to deal with the sse4 target feature when used 3583 // as part of the target attribute. We handle sse4 correctly everywhere 3584 // else. See below for more information on how we handle the sse4 options. 3585 if (Name != "sse4") 3586 Features[Name] = Enabled; 3587 3588 if (Name == "mmx") { 3589 setMMXLevel(Features, MMX, Enabled); 3590 } else if (Name == "sse") { 3591 setSSELevel(Features, SSE1, Enabled); 3592 } else if (Name == "sse2") { 3593 setSSELevel(Features, SSE2, Enabled); 3594 } else if (Name == "sse3") { 3595 setSSELevel(Features, SSE3, Enabled); 3596 } else if (Name == "ssse3") { 3597 setSSELevel(Features, SSSE3, Enabled); 3598 } else if (Name == "sse4.2") { 3599 setSSELevel(Features, SSE42, Enabled); 3600 } else if (Name == "sse4.1") { 3601 setSSELevel(Features, SSE41, Enabled); 3602 } else if (Name == "3dnow") { 3603 setMMXLevel(Features, AMD3DNow, Enabled); 3604 } else if (Name == "3dnowa") { 3605 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3606 } else if (Name == "aes") { 3607 if (Enabled) 3608 setSSELevel(Features, SSE2, Enabled); 3609 } else if (Name == "pclmul") { 3610 if (Enabled) 3611 setSSELevel(Features, SSE2, Enabled); 3612 } else if (Name == "avx") { 3613 setSSELevel(Features, AVX, Enabled); 3614 } else if (Name == "avx2") { 3615 setSSELevel(Features, AVX2, Enabled); 3616 } else if (Name == "avx512f") { 3617 setSSELevel(Features, AVX512F, Enabled); 3618 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3619 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3620 Name == "avx512vbmi" || Name == "avx512ifma" || 3621 Name == "avx512vpopcntdq") { 3622 if (Enabled) 3623 setSSELevel(Features, AVX512F, Enabled); 3624 // Enable BWI instruction if VBMI is being enabled. 3625 if (Name == "avx512vbmi" && Enabled) 3626 Features["avx512bw"] = true; 3627 // Also disable VBMI if BWI is being disabled. 3628 if (Name == "avx512bw" && !Enabled) 3629 Features["avx512vbmi"] = false; 3630 } else if (Name == "fma") { 3631 if (Enabled) 3632 setSSELevel(Features, AVX, Enabled); 3633 } else if (Name == "fma4") { 3634 setXOPLevel(Features, FMA4, Enabled); 3635 } else if (Name == "xop") { 3636 setXOPLevel(Features, XOP, Enabled); 3637 } else if (Name == "sse4a") { 3638 setXOPLevel(Features, SSE4A, Enabled); 3639 } else if (Name == "f16c") { 3640 if (Enabled) 3641 setSSELevel(Features, AVX, Enabled); 3642 } else if (Name == "sha") { 3643 if (Enabled) 3644 setSSELevel(Features, SSE2, Enabled); 3645 } else if (Name == "sse4") { 3646 // We can get here via the __target__ attribute since that's not controlled 3647 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3648 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3649 // disabled. 3650 if (Enabled) 3651 setSSELevel(Features, SSE42, Enabled); 3652 else 3653 setSSELevel(Features, SSE41, Enabled); 3654 } else if (Name == "xsave") { 3655 if (!Enabled) 3656 Features["xsaveopt"] = false; 3657 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3658 if (Enabled) 3659 Features["xsave"] = true; 3660 } 3661 } 3662 3663 /// handleTargetFeatures - Perform initialization based on the user 3664 /// configured set of features. 3665 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3666 DiagnosticsEngine &Diags) { 3667 for (const auto &Feature : Features) { 3668 if (Feature[0] != '+') 3669 continue; 3670 3671 if (Feature == "+aes") { 3672 HasAES = true; 3673 } else if (Feature == "+pclmul") { 3674 HasPCLMUL = true; 3675 } else if (Feature == "+lzcnt") { 3676 HasLZCNT = true; 3677 } else if (Feature == "+rdrnd") { 3678 HasRDRND = true; 3679 } else if (Feature == "+fsgsbase") { 3680 HasFSGSBASE = true; 3681 } else if (Feature == "+bmi") { 3682 HasBMI = true; 3683 } else if (Feature == "+bmi2") { 3684 HasBMI2 = true; 3685 } else if (Feature == "+popcnt") { 3686 HasPOPCNT = true; 3687 } else if (Feature == "+rtm") { 3688 HasRTM = true; 3689 } else if (Feature == "+prfchw") { 3690 HasPRFCHW = true; 3691 } else if (Feature == "+rdseed") { 3692 HasRDSEED = true; 3693 } else if (Feature == "+adx") { 3694 HasADX = true; 3695 } else if (Feature == "+tbm") { 3696 HasTBM = true; 3697 } else if (Feature == "+lwp") { 3698 HasLWP = true; 3699 } else if (Feature == "+fma") { 3700 HasFMA = true; 3701 } else if (Feature == "+f16c") { 3702 HasF16C = true; 3703 } else if (Feature == "+avx512cd") { 3704 HasAVX512CD = true; 3705 } else if (Feature == "+avx512vpopcntdq") { 3706 HasAVX512VPOPCNTDQ = true; 3707 } else if (Feature == "+avx512er") { 3708 HasAVX512ER = true; 3709 } else if (Feature == "+avx512pf") { 3710 HasAVX512PF = true; 3711 } else if (Feature == "+avx512dq") { 3712 HasAVX512DQ = true; 3713 } else if (Feature == "+avx512bw") { 3714 HasAVX512BW = true; 3715 } else if (Feature == "+avx512vl") { 3716 HasAVX512VL = true; 3717 } else if (Feature == "+avx512vbmi") { 3718 HasAVX512VBMI = true; 3719 } else if (Feature == "+avx512ifma") { 3720 HasAVX512IFMA = true; 3721 } else if (Feature == "+sha") { 3722 HasSHA = true; 3723 } else if (Feature == "+mpx") { 3724 HasMPX = true; 3725 } else if (Feature == "+movbe") { 3726 HasMOVBE = true; 3727 } else if (Feature == "+sgx") { 3728 HasSGX = true; 3729 } else if (Feature == "+cx16") { 3730 HasCX16 = true; 3731 } else if (Feature == "+fxsr") { 3732 HasFXSR = true; 3733 } else if (Feature == "+xsave") { 3734 HasXSAVE = true; 3735 } else if (Feature == "+xsaveopt") { 3736 HasXSAVEOPT = true; 3737 } else if (Feature == "+xsavec") { 3738 HasXSAVEC = true; 3739 } else if (Feature == "+xsaves") { 3740 HasXSAVES = true; 3741 } else if (Feature == "+mwaitx") { 3742 HasMWAITX = true; 3743 } else if (Feature == "+pku") { 3744 HasPKU = true; 3745 } else if (Feature == "+clflushopt") { 3746 HasCLFLUSHOPT = true; 3747 } else if (Feature == "+clwb") { 3748 HasCLWB = true; 3749 } else if (Feature == "+prefetchwt1") { 3750 HasPREFETCHWT1 = true; 3751 } else if (Feature == "+clzero") { 3752 HasCLZERO = true; 3753 } 3754 3755 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3756 .Case("+avx512f", AVX512F) 3757 .Case("+avx2", AVX2) 3758 .Case("+avx", AVX) 3759 .Case("+sse4.2", SSE42) 3760 .Case("+sse4.1", SSE41) 3761 .Case("+ssse3", SSSE3) 3762 .Case("+sse3", SSE3) 3763 .Case("+sse2", SSE2) 3764 .Case("+sse", SSE1) 3765 .Default(NoSSE); 3766 SSELevel = std::max(SSELevel, Level); 3767 3768 MMX3DNowEnum ThreeDNowLevel = 3769 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3770 .Case("+3dnowa", AMD3DNowAthlon) 3771 .Case("+3dnow", AMD3DNow) 3772 .Case("+mmx", MMX) 3773 .Default(NoMMX3DNow); 3774 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3775 3776 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3777 .Case("+xop", XOP) 3778 .Case("+fma4", FMA4) 3779 .Case("+sse4a", SSE4A) 3780 .Default(NoXOP); 3781 XOPLevel = std::max(XOPLevel, XLevel); 3782 } 3783 3784 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3785 // matches the selected sse level. 3786 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3787 (FPMath == FP_387 && SSELevel >= SSE1)) { 3788 Diags.Report(diag::err_target_unsupported_fpmath) << 3789 (FPMath == FP_SSE ? "sse" : "387"); 3790 return false; 3791 } 3792 3793 SimdDefaultAlign = 3794 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3795 return true; 3796 } 3797 3798 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3799 /// definitions for this particular subtarget. 3800 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3801 MacroBuilder &Builder) const { 3802 // Target identification. 3803 if (getTriple().getArch() == llvm::Triple::x86_64) { 3804 Builder.defineMacro("__amd64__"); 3805 Builder.defineMacro("__amd64"); 3806 Builder.defineMacro("__x86_64"); 3807 Builder.defineMacro("__x86_64__"); 3808 if (getTriple().getArchName() == "x86_64h") { 3809 Builder.defineMacro("__x86_64h"); 3810 Builder.defineMacro("__x86_64h__"); 3811 } 3812 } else { 3813 DefineStd(Builder, "i386", Opts); 3814 } 3815 3816 // Subtarget options. 3817 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3818 // truly should be based on -mtune options. 3819 switch (CPU) { 3820 case CK_Generic: 3821 break; 3822 case CK_i386: 3823 // The rest are coming from the i386 define above. 3824 Builder.defineMacro("__tune_i386__"); 3825 break; 3826 case CK_i486: 3827 case CK_WinChipC6: 3828 case CK_WinChip2: 3829 case CK_C3: 3830 defineCPUMacros(Builder, "i486"); 3831 break; 3832 case CK_PentiumMMX: 3833 Builder.defineMacro("__pentium_mmx__"); 3834 Builder.defineMacro("__tune_pentium_mmx__"); 3835 // Fallthrough 3836 case CK_i586: 3837 case CK_Pentium: 3838 defineCPUMacros(Builder, "i586"); 3839 defineCPUMacros(Builder, "pentium"); 3840 break; 3841 case CK_Pentium3: 3842 case CK_Pentium3M: 3843 case CK_PentiumM: 3844 Builder.defineMacro("__tune_pentium3__"); 3845 // Fallthrough 3846 case CK_Pentium2: 3847 case CK_C3_2: 3848 Builder.defineMacro("__tune_pentium2__"); 3849 // Fallthrough 3850 case CK_PentiumPro: 3851 Builder.defineMacro("__tune_i686__"); 3852 Builder.defineMacro("__tune_pentiumpro__"); 3853 // Fallthrough 3854 case CK_i686: 3855 Builder.defineMacro("__i686"); 3856 Builder.defineMacro("__i686__"); 3857 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3858 Builder.defineMacro("__pentiumpro"); 3859 Builder.defineMacro("__pentiumpro__"); 3860 break; 3861 case CK_Pentium4: 3862 case CK_Pentium4M: 3863 defineCPUMacros(Builder, "pentium4"); 3864 break; 3865 case CK_Yonah: 3866 case CK_Prescott: 3867 case CK_Nocona: 3868 defineCPUMacros(Builder, "nocona"); 3869 break; 3870 case CK_Core2: 3871 case CK_Penryn: 3872 defineCPUMacros(Builder, "core2"); 3873 break; 3874 case CK_Bonnell: 3875 defineCPUMacros(Builder, "atom"); 3876 break; 3877 case CK_Silvermont: 3878 defineCPUMacros(Builder, "slm"); 3879 break; 3880 case CK_Nehalem: 3881 case CK_Westmere: 3882 case CK_SandyBridge: 3883 case CK_IvyBridge: 3884 case CK_Haswell: 3885 case CK_Broadwell: 3886 case CK_SkylakeClient: 3887 // FIXME: Historically, we defined this legacy name, it would be nice to 3888 // remove it at some point. We've never exposed fine-grained names for 3889 // recent primary x86 CPUs, and we should keep it that way. 3890 defineCPUMacros(Builder, "corei7"); 3891 break; 3892 case CK_SkylakeServer: 3893 defineCPUMacros(Builder, "skx"); 3894 break; 3895 case CK_Cannonlake: 3896 break; 3897 case CK_KNL: 3898 defineCPUMacros(Builder, "knl"); 3899 break; 3900 case CK_Lakemont: 3901 Builder.defineMacro("__tune_lakemont__"); 3902 break; 3903 case CK_K6_2: 3904 Builder.defineMacro("__k6_2__"); 3905 Builder.defineMacro("__tune_k6_2__"); 3906 // Fallthrough 3907 case CK_K6_3: 3908 if (CPU != CK_K6_2) { // In case of fallthrough 3909 // FIXME: GCC may be enabling these in cases where some other k6 3910 // architecture is specified but -m3dnow is explicitly provided. The 3911 // exact semantics need to be determined and emulated here. 3912 Builder.defineMacro("__k6_3__"); 3913 Builder.defineMacro("__tune_k6_3__"); 3914 } 3915 // Fallthrough 3916 case CK_K6: 3917 defineCPUMacros(Builder, "k6"); 3918 break; 3919 case CK_Athlon: 3920 case CK_AthlonThunderbird: 3921 case CK_Athlon4: 3922 case CK_AthlonXP: 3923 case CK_AthlonMP: 3924 defineCPUMacros(Builder, "athlon"); 3925 if (SSELevel != NoSSE) { 3926 Builder.defineMacro("__athlon_sse__"); 3927 Builder.defineMacro("__tune_athlon_sse__"); 3928 } 3929 break; 3930 case CK_K8: 3931 case CK_K8SSE3: 3932 case CK_x86_64: 3933 case CK_Opteron: 3934 case CK_OpteronSSE3: 3935 case CK_Athlon64: 3936 case CK_Athlon64SSE3: 3937 case CK_AthlonFX: 3938 defineCPUMacros(Builder, "k8"); 3939 break; 3940 case CK_AMDFAM10: 3941 defineCPUMacros(Builder, "amdfam10"); 3942 break; 3943 case CK_BTVER1: 3944 defineCPUMacros(Builder, "btver1"); 3945 break; 3946 case CK_BTVER2: 3947 defineCPUMacros(Builder, "btver2"); 3948 break; 3949 case CK_BDVER1: 3950 defineCPUMacros(Builder, "bdver1"); 3951 break; 3952 case CK_BDVER2: 3953 defineCPUMacros(Builder, "bdver2"); 3954 break; 3955 case CK_BDVER3: 3956 defineCPUMacros(Builder, "bdver3"); 3957 break; 3958 case CK_BDVER4: 3959 defineCPUMacros(Builder, "bdver4"); 3960 break; 3961 case CK_ZNVER1: 3962 defineCPUMacros(Builder, "znver1"); 3963 break; 3964 case CK_Geode: 3965 defineCPUMacros(Builder, "geode"); 3966 break; 3967 } 3968 3969 // Target properties. 3970 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3971 3972 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3973 // functions in glibc header files that use FP Stack inline asm which the 3974 // backend can't deal with (PR879). 3975 Builder.defineMacro("__NO_MATH_INLINES"); 3976 3977 if (HasAES) 3978 Builder.defineMacro("__AES__"); 3979 3980 if (HasPCLMUL) 3981 Builder.defineMacro("__PCLMUL__"); 3982 3983 if (HasLZCNT) 3984 Builder.defineMacro("__LZCNT__"); 3985 3986 if (HasRDRND) 3987 Builder.defineMacro("__RDRND__"); 3988 3989 if (HasFSGSBASE) 3990 Builder.defineMacro("__FSGSBASE__"); 3991 3992 if (HasBMI) 3993 Builder.defineMacro("__BMI__"); 3994 3995 if (HasBMI2) 3996 Builder.defineMacro("__BMI2__"); 3997 3998 if (HasPOPCNT) 3999 Builder.defineMacro("__POPCNT__"); 4000 4001 if (HasRTM) 4002 Builder.defineMacro("__RTM__"); 4003 4004 if (HasPRFCHW) 4005 Builder.defineMacro("__PRFCHW__"); 4006 4007 if (HasRDSEED) 4008 Builder.defineMacro("__RDSEED__"); 4009 4010 if (HasADX) 4011 Builder.defineMacro("__ADX__"); 4012 4013 if (HasTBM) 4014 Builder.defineMacro("__TBM__"); 4015 4016 if (HasLWP) 4017 Builder.defineMacro("__LWP__"); 4018 4019 if (HasMWAITX) 4020 Builder.defineMacro("__MWAITX__"); 4021 4022 switch (XOPLevel) { 4023 case XOP: 4024 Builder.defineMacro("__XOP__"); 4025 LLVM_FALLTHROUGH; 4026 case FMA4: 4027 Builder.defineMacro("__FMA4__"); 4028 LLVM_FALLTHROUGH; 4029 case SSE4A: 4030 Builder.defineMacro("__SSE4A__"); 4031 LLVM_FALLTHROUGH; 4032 case NoXOP: 4033 break; 4034 } 4035 4036 if (HasFMA) 4037 Builder.defineMacro("__FMA__"); 4038 4039 if (HasF16C) 4040 Builder.defineMacro("__F16C__"); 4041 4042 if (HasAVX512CD) 4043 Builder.defineMacro("__AVX512CD__"); 4044 if (HasAVX512VPOPCNTDQ) 4045 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 4046 if (HasAVX512ER) 4047 Builder.defineMacro("__AVX512ER__"); 4048 if (HasAVX512PF) 4049 Builder.defineMacro("__AVX512PF__"); 4050 if (HasAVX512DQ) 4051 Builder.defineMacro("__AVX512DQ__"); 4052 if (HasAVX512BW) 4053 Builder.defineMacro("__AVX512BW__"); 4054 if (HasAVX512VL) 4055 Builder.defineMacro("__AVX512VL__"); 4056 if (HasAVX512VBMI) 4057 Builder.defineMacro("__AVX512VBMI__"); 4058 if (HasAVX512IFMA) 4059 Builder.defineMacro("__AVX512IFMA__"); 4060 4061 if (HasSHA) 4062 Builder.defineMacro("__SHA__"); 4063 4064 if (HasFXSR) 4065 Builder.defineMacro("__FXSR__"); 4066 if (HasXSAVE) 4067 Builder.defineMacro("__XSAVE__"); 4068 if (HasXSAVEOPT) 4069 Builder.defineMacro("__XSAVEOPT__"); 4070 if (HasXSAVEC) 4071 Builder.defineMacro("__XSAVEC__"); 4072 if (HasXSAVES) 4073 Builder.defineMacro("__XSAVES__"); 4074 if (HasPKU) 4075 Builder.defineMacro("__PKU__"); 4076 if (HasCX16) 4077 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 4078 if (HasCLFLUSHOPT) 4079 Builder.defineMacro("__CLFLUSHOPT__"); 4080 if (HasCLWB) 4081 Builder.defineMacro("__CLWB__"); 4082 if (HasMPX) 4083 Builder.defineMacro("__MPX__"); 4084 if (HasSGX) 4085 Builder.defineMacro("__SGX__"); 4086 if (HasPREFETCHWT1) 4087 Builder.defineMacro("__PREFETCHWT1__"); 4088 if (HasCLZERO) 4089 Builder.defineMacro("__CLZERO__"); 4090 4091 // Each case falls through to the previous one here. 4092 switch (SSELevel) { 4093 case AVX512F: 4094 Builder.defineMacro("__AVX512F__"); 4095 LLVM_FALLTHROUGH; 4096 case AVX2: 4097 Builder.defineMacro("__AVX2__"); 4098 LLVM_FALLTHROUGH; 4099 case AVX: 4100 Builder.defineMacro("__AVX__"); 4101 LLVM_FALLTHROUGH; 4102 case SSE42: 4103 Builder.defineMacro("__SSE4_2__"); 4104 LLVM_FALLTHROUGH; 4105 case SSE41: 4106 Builder.defineMacro("__SSE4_1__"); 4107 LLVM_FALLTHROUGH; 4108 case SSSE3: 4109 Builder.defineMacro("__SSSE3__"); 4110 LLVM_FALLTHROUGH; 4111 case SSE3: 4112 Builder.defineMacro("__SSE3__"); 4113 LLVM_FALLTHROUGH; 4114 case SSE2: 4115 Builder.defineMacro("__SSE2__"); 4116 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 4117 LLVM_FALLTHROUGH; 4118 case SSE1: 4119 Builder.defineMacro("__SSE__"); 4120 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 4121 LLVM_FALLTHROUGH; 4122 case NoSSE: 4123 break; 4124 } 4125 4126 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 4127 switch (SSELevel) { 4128 case AVX512F: 4129 case AVX2: 4130 case AVX: 4131 case SSE42: 4132 case SSE41: 4133 case SSSE3: 4134 case SSE3: 4135 case SSE2: 4136 Builder.defineMacro("_M_IX86_FP", Twine(2)); 4137 break; 4138 case SSE1: 4139 Builder.defineMacro("_M_IX86_FP", Twine(1)); 4140 break; 4141 default: 4142 Builder.defineMacro("_M_IX86_FP", Twine(0)); 4143 } 4144 } 4145 4146 // Each case falls through to the previous one here. 4147 switch (MMX3DNowLevel) { 4148 case AMD3DNowAthlon: 4149 Builder.defineMacro("__3dNOW_A__"); 4150 LLVM_FALLTHROUGH; 4151 case AMD3DNow: 4152 Builder.defineMacro("__3dNOW__"); 4153 LLVM_FALLTHROUGH; 4154 case MMX: 4155 Builder.defineMacro("__MMX__"); 4156 LLVM_FALLTHROUGH; 4157 case NoMMX3DNow: 4158 break; 4159 } 4160 4161 if (CPU >= CK_i486) { 4162 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4163 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4164 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4165 } 4166 if (CPU >= CK_i586) 4167 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4168 4169 if (HasFloat128) 4170 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 4171 } 4172 4173 bool X86TargetInfo::hasFeature(StringRef Feature) const { 4174 return llvm::StringSwitch<bool>(Feature) 4175 .Case("aes", HasAES) 4176 .Case("avx", SSELevel >= AVX) 4177 .Case("avx2", SSELevel >= AVX2) 4178 .Case("avx512f", SSELevel >= AVX512F) 4179 .Case("avx512cd", HasAVX512CD) 4180 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 4181 .Case("avx512er", HasAVX512ER) 4182 .Case("avx512pf", HasAVX512PF) 4183 .Case("avx512dq", HasAVX512DQ) 4184 .Case("avx512bw", HasAVX512BW) 4185 .Case("avx512vl", HasAVX512VL) 4186 .Case("avx512vbmi", HasAVX512VBMI) 4187 .Case("avx512ifma", HasAVX512IFMA) 4188 .Case("bmi", HasBMI) 4189 .Case("bmi2", HasBMI2) 4190 .Case("clflushopt", HasCLFLUSHOPT) 4191 .Case("clwb", HasCLWB) 4192 .Case("clzero", HasCLZERO) 4193 .Case("cx16", HasCX16) 4194 .Case("f16c", HasF16C) 4195 .Case("fma", HasFMA) 4196 .Case("fma4", XOPLevel >= FMA4) 4197 .Case("fsgsbase", HasFSGSBASE) 4198 .Case("fxsr", HasFXSR) 4199 .Case("lzcnt", HasLZCNT) 4200 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4201 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4202 .Case("mmx", MMX3DNowLevel >= MMX) 4203 .Case("movbe", HasMOVBE) 4204 .Case("mpx", HasMPX) 4205 .Case("pclmul", HasPCLMUL) 4206 .Case("pku", HasPKU) 4207 .Case("popcnt", HasPOPCNT) 4208 .Case("prefetchwt1", HasPREFETCHWT1) 4209 .Case("prfchw", HasPRFCHW) 4210 .Case("rdrnd", HasRDRND) 4211 .Case("rdseed", HasRDSEED) 4212 .Case("rtm", HasRTM) 4213 .Case("sgx", HasSGX) 4214 .Case("sha", HasSHA) 4215 .Case("sse", SSELevel >= SSE1) 4216 .Case("sse2", SSELevel >= SSE2) 4217 .Case("sse3", SSELevel >= SSE3) 4218 .Case("ssse3", SSELevel >= SSSE3) 4219 .Case("sse4.1", SSELevel >= SSE41) 4220 .Case("sse4.2", SSELevel >= SSE42) 4221 .Case("sse4a", XOPLevel >= SSE4A) 4222 .Case("tbm", HasTBM) 4223 .Case("lwp", HasLWP) 4224 .Case("x86", true) 4225 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4226 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4227 .Case("xop", XOPLevel >= XOP) 4228 .Case("xsave", HasXSAVE) 4229 .Case("xsavec", HasXSAVEC) 4230 .Case("xsaves", HasXSAVES) 4231 .Case("xsaveopt", HasXSAVEOPT) 4232 .Default(false); 4233 } 4234 4235 // We can't use a generic validation scheme for the features accepted here 4236 // versus subtarget features accepted in the target attribute because the 4237 // bitfield structure that's initialized in the runtime only supports the 4238 // below currently rather than the full range of subtarget features. (See 4239 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4240 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4241 return llvm::StringSwitch<bool>(FeatureStr) 4242 .Case("cmov", true) 4243 .Case("mmx", true) 4244 .Case("popcnt", true) 4245 .Case("sse", true) 4246 .Case("sse2", true) 4247 .Case("sse3", true) 4248 .Case("ssse3", true) 4249 .Case("sse4.1", true) 4250 .Case("sse4.2", true) 4251 .Case("avx", true) 4252 .Case("avx2", true) 4253 .Case("sse4a", true) 4254 .Case("fma4", true) 4255 .Case("xop", true) 4256 .Case("fma", true) 4257 .Case("avx512f", true) 4258 .Case("bmi", true) 4259 .Case("bmi2", true) 4260 .Case("aes", true) 4261 .Case("pclmul", true) 4262 .Case("avx512vl", true) 4263 .Case("avx512bw", true) 4264 .Case("avx512dq", true) 4265 .Case("avx512cd", true) 4266 .Case("avx512vpopcntdq", true) 4267 .Case("avx512er", true) 4268 .Case("avx512pf", true) 4269 .Case("avx512vbmi", true) 4270 .Case("avx512ifma", true) 4271 .Default(false); 4272 } 4273 4274 bool 4275 X86TargetInfo::validateAsmConstraint(const char *&Name, 4276 TargetInfo::ConstraintInfo &Info) const { 4277 switch (*Name) { 4278 default: return false; 4279 // Constant constraints. 4280 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4281 // instructions. 4282 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4283 // x86_64 instructions. 4284 case 's': 4285 Info.setRequiresImmediate(); 4286 return true; 4287 case 'I': 4288 Info.setRequiresImmediate(0, 31); 4289 return true; 4290 case 'J': 4291 Info.setRequiresImmediate(0, 63); 4292 return true; 4293 case 'K': 4294 Info.setRequiresImmediate(-128, 127); 4295 return true; 4296 case 'L': 4297 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4298 return true; 4299 case 'M': 4300 Info.setRequiresImmediate(0, 3); 4301 return true; 4302 case 'N': 4303 Info.setRequiresImmediate(0, 255); 4304 return true; 4305 case 'O': 4306 Info.setRequiresImmediate(0, 127); 4307 return true; 4308 // Register constraints. 4309 case 'Y': // 'Y' is the first character for several 2-character constraints. 4310 // Shift the pointer to the second character of the constraint. 4311 Name++; 4312 switch (*Name) { 4313 default: 4314 return false; 4315 case '0': // First SSE register. 4316 case 't': // Any SSE register, when SSE2 is enabled. 4317 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4318 case 'm': // Any MMX register, when inter-unit moves enabled. 4319 case 'k': // AVX512 arch mask registers: k1-k7. 4320 Info.setAllowsRegister(); 4321 return true; 4322 } 4323 case 'f': // Any x87 floating point stack register. 4324 // Constraint 'f' cannot be used for output operands. 4325 if (Info.ConstraintStr[0] == '=') 4326 return false; 4327 Info.setAllowsRegister(); 4328 return true; 4329 case 'a': // eax. 4330 case 'b': // ebx. 4331 case 'c': // ecx. 4332 case 'd': // edx. 4333 case 'S': // esi. 4334 case 'D': // edi. 4335 case 'A': // edx:eax. 4336 case 't': // Top of floating point stack. 4337 case 'u': // Second from top of floating point stack. 4338 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4339 case 'y': // Any MMX register. 4340 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4341 case 'x': // Any SSE register. 4342 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4343 // for intermideate k reg operations). 4344 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4345 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4346 case 'l': // "Index" registers: any general register that can be used as an 4347 // index in a base+index memory access. 4348 Info.setAllowsRegister(); 4349 return true; 4350 // Floating point constant constraints. 4351 case 'C': // SSE floating point constant. 4352 case 'G': // x87 floating point constant. 4353 return true; 4354 } 4355 } 4356 4357 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4358 unsigned Size) const { 4359 // Strip off constraint modifiers. 4360 while (Constraint[0] == '=' || 4361 Constraint[0] == '+' || 4362 Constraint[0] == '&') 4363 Constraint = Constraint.substr(1); 4364 4365 return validateOperandSize(Constraint, Size); 4366 } 4367 4368 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4369 unsigned Size) const { 4370 return validateOperandSize(Constraint, Size); 4371 } 4372 4373 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4374 unsigned Size) const { 4375 switch (Constraint[0]) { 4376 default: break; 4377 case 'k': 4378 // Registers k0-k7 (AVX512) size limit is 64 bit. 4379 case 'y': 4380 return Size <= 64; 4381 case 'f': 4382 case 't': 4383 case 'u': 4384 return Size <= 128; 4385 case 'v': 4386 case 'x': 4387 if (SSELevel >= AVX512F) 4388 // 512-bit zmm registers can be used if target supports AVX512F. 4389 return Size <= 512U; 4390 else if (SSELevel >= AVX) 4391 // 256-bit ymm registers can be used if target supports AVX. 4392 return Size <= 256U; 4393 return Size <= 128U; 4394 case 'Y': 4395 // 'Y' is the first character for several 2-character constraints. 4396 switch (Constraint[1]) { 4397 default: break; 4398 case 'm': 4399 // 'Ym' is synonymous with 'y'. 4400 case 'k': 4401 return Size <= 64; 4402 case 'i': 4403 case 't': 4404 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4405 if (SSELevel >= AVX512F) 4406 return Size <= 512U; 4407 else if (SSELevel >= AVX) 4408 return Size <= 256U; 4409 return SSELevel >= SSE2 && Size <= 128U; 4410 } 4411 4412 } 4413 4414 return true; 4415 } 4416 4417 std::string 4418 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4419 switch (*Constraint) { 4420 case 'a': return std::string("{ax}"); 4421 case 'b': return std::string("{bx}"); 4422 case 'c': return std::string("{cx}"); 4423 case 'd': return std::string("{dx}"); 4424 case 'S': return std::string("{si}"); 4425 case 'D': return std::string("{di}"); 4426 case 'p': // address 4427 return std::string("im"); 4428 case 't': // top of floating point stack. 4429 return std::string("{st}"); 4430 case 'u': // second from top of floating point stack. 4431 return std::string("{st(1)}"); // second from top of floating point stack. 4432 case 'Y': 4433 switch (Constraint[1]) { 4434 default: 4435 // Break from inner switch and fall through (copy single char), 4436 // continue parsing after copying the current constraint into 4437 // the return string. 4438 break; 4439 case 'k': 4440 // "^" hints llvm that this is a 2 letter constraint. 4441 // "Constraint++" is used to promote the string iterator 4442 // to the next constraint. 4443 return std::string("^") + std::string(Constraint++, 2); 4444 } 4445 LLVM_FALLTHROUGH; 4446 default: 4447 return std::string(1, *Constraint); 4448 } 4449 } 4450 4451 // X86-32 generic target 4452 class X86_32TargetInfo : public X86TargetInfo { 4453 public: 4454 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4455 : X86TargetInfo(Triple, Opts) { 4456 DoubleAlign = LongLongAlign = 32; 4457 LongDoubleWidth = 96; 4458 LongDoubleAlign = 32; 4459 SuitableAlign = 128; 4460 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4461 SizeType = UnsignedInt; 4462 PtrDiffType = SignedInt; 4463 IntPtrType = SignedInt; 4464 RegParmMax = 3; 4465 4466 // Use fpret for all types. 4467 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4468 (1 << TargetInfo::Double) | 4469 (1 << TargetInfo::LongDouble)); 4470 4471 // x86-32 has atomics up to 8 bytes 4472 // FIXME: Check that we actually have cmpxchg8b before setting 4473 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4474 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4475 } 4476 BuiltinVaListKind getBuiltinVaListKind() const override { 4477 return TargetInfo::CharPtrBuiltinVaList; 4478 } 4479 4480 int getEHDataRegisterNumber(unsigned RegNo) const override { 4481 if (RegNo == 0) return 0; 4482 if (RegNo == 1) return 2; 4483 return -1; 4484 } 4485 bool validateOperandSize(StringRef Constraint, 4486 unsigned Size) const override { 4487 switch (Constraint[0]) { 4488 default: break; 4489 case 'R': 4490 case 'q': 4491 case 'Q': 4492 case 'a': 4493 case 'b': 4494 case 'c': 4495 case 'd': 4496 case 'S': 4497 case 'D': 4498 return Size <= 32; 4499 case 'A': 4500 return Size <= 64; 4501 } 4502 4503 return X86TargetInfo::validateOperandSize(Constraint, Size); 4504 } 4505 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4506 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4507 Builtin::FirstTSBuiltin + 1); 4508 } 4509 }; 4510 4511 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4512 public: 4513 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4514 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4515 4516 unsigned getFloatEvalMethod() const override { 4517 unsigned Major, Minor, Micro; 4518 getTriple().getOSVersion(Major, Minor, Micro); 4519 // New NetBSD uses the default rounding mode. 4520 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4521 return X86_32TargetInfo::getFloatEvalMethod(); 4522 // NetBSD before 6.99.26 defaults to "double" rounding. 4523 return 1; 4524 } 4525 }; 4526 4527 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4528 public: 4529 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4530 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4531 SizeType = UnsignedLong; 4532 IntPtrType = SignedLong; 4533 PtrDiffType = SignedLong; 4534 } 4535 }; 4536 4537 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4538 public: 4539 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4540 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4541 SizeType = UnsignedLong; 4542 IntPtrType = SignedLong; 4543 PtrDiffType = SignedLong; 4544 } 4545 }; 4546 4547 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4548 public: 4549 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4550 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4551 LongDoubleWidth = 128; 4552 LongDoubleAlign = 128; 4553 SuitableAlign = 128; 4554 MaxVectorAlign = 256; 4555 // The watchOS simulator uses the builtin bool type for Objective-C. 4556 llvm::Triple T = llvm::Triple(Triple); 4557 if (T.isWatchOS()) 4558 UseSignedCharForObjCBool = false; 4559 SizeType = UnsignedLong; 4560 IntPtrType = SignedLong; 4561 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4562 HasAlignMac68kSupport = true; 4563 } 4564 4565 bool handleTargetFeatures(std::vector<std::string> &Features, 4566 DiagnosticsEngine &Diags) override { 4567 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4568 Diags)) 4569 return false; 4570 // We now know the features we have: we can decide how to align vectors. 4571 MaxVectorAlign = 4572 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4573 return true; 4574 } 4575 }; 4576 4577 // x86-32 Windows target 4578 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4579 public: 4580 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4581 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4582 WCharType = UnsignedShort; 4583 DoubleAlign = LongLongAlign = 64; 4584 bool IsWinCOFF = 4585 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4586 resetDataLayout(IsWinCOFF 4587 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4588 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4589 } 4590 void getTargetDefines(const LangOptions &Opts, 4591 MacroBuilder &Builder) const override { 4592 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4593 } 4594 }; 4595 4596 // x86-32 Windows Visual Studio target 4597 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4598 public: 4599 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4600 const TargetOptions &Opts) 4601 : WindowsX86_32TargetInfo(Triple, Opts) { 4602 LongDoubleWidth = LongDoubleAlign = 64; 4603 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4604 } 4605 void getTargetDefines(const LangOptions &Opts, 4606 MacroBuilder &Builder) const override { 4607 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4608 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4609 // The value of the following reflects processor type. 4610 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4611 // We lost the original triple, so we use the default. 4612 Builder.defineMacro("_M_IX86", "600"); 4613 } 4614 }; 4615 4616 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4617 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4618 // supports __declspec natively under -fms-extensions, but we define a no-op 4619 // __declspec macro anyway for pre-processor compatibility. 4620 if (Opts.MicrosoftExt) 4621 Builder.defineMacro("__declspec", "__declspec"); 4622 else 4623 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4624 4625 if (!Opts.MicrosoftExt) { 4626 // Provide macros for all the calling convention keywords. Provide both 4627 // single and double underscore prefixed variants. These are available on 4628 // x64 as well as x86, even though they have no effect. 4629 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4630 for (const char *CC : CCs) { 4631 std::string GCCSpelling = "__attribute__((__"; 4632 GCCSpelling += CC; 4633 GCCSpelling += "__))"; 4634 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4635 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4636 } 4637 } 4638 } 4639 4640 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4641 Builder.defineMacro("__MSVCRT__"); 4642 Builder.defineMacro("__MINGW32__"); 4643 addCygMingDefines(Opts, Builder); 4644 } 4645 4646 // x86-32 MinGW target 4647 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4648 public: 4649 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4650 : WindowsX86_32TargetInfo(Triple, Opts) { 4651 HasFloat128 = true; 4652 } 4653 void getTargetDefines(const LangOptions &Opts, 4654 MacroBuilder &Builder) const override { 4655 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4656 DefineStd(Builder, "WIN32", Opts); 4657 DefineStd(Builder, "WINNT", Opts); 4658 Builder.defineMacro("_X86_"); 4659 addMinGWDefines(Opts, Builder); 4660 } 4661 }; 4662 4663 // x86-32 Cygwin target 4664 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4665 public: 4666 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4667 : X86_32TargetInfo(Triple, Opts) { 4668 WCharType = UnsignedShort; 4669 DoubleAlign = LongLongAlign = 64; 4670 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4671 } 4672 void getTargetDefines(const LangOptions &Opts, 4673 MacroBuilder &Builder) const override { 4674 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4675 Builder.defineMacro("_X86_"); 4676 Builder.defineMacro("__CYGWIN__"); 4677 Builder.defineMacro("__CYGWIN32__"); 4678 addCygMingDefines(Opts, Builder); 4679 DefineStd(Builder, "unix", Opts); 4680 if (Opts.CPlusPlus) 4681 Builder.defineMacro("_GNU_SOURCE"); 4682 } 4683 }; 4684 4685 // x86-32 Haiku target 4686 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4687 public: 4688 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4689 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4690 } 4691 void getTargetDefines(const LangOptions &Opts, 4692 MacroBuilder &Builder) const override { 4693 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4694 Builder.defineMacro("__INTEL__"); 4695 } 4696 }; 4697 4698 // X86-32 MCU target 4699 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4700 public: 4701 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4702 : X86_32TargetInfo(Triple, Opts) { 4703 LongDoubleWidth = 64; 4704 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4705 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4706 WIntType = UnsignedInt; 4707 } 4708 4709 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4710 // On MCU we support only C calling convention. 4711 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4712 } 4713 4714 void getTargetDefines(const LangOptions &Opts, 4715 MacroBuilder &Builder) const override { 4716 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4717 Builder.defineMacro("__iamcu"); 4718 Builder.defineMacro("__iamcu__"); 4719 } 4720 4721 bool allowsLargerPreferedTypeAlignment() const override { 4722 return false; 4723 } 4724 }; 4725 4726 // RTEMS Target 4727 template<typename Target> 4728 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4729 protected: 4730 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4731 MacroBuilder &Builder) const override { 4732 // RTEMS defines; list based off of gcc output 4733 4734 Builder.defineMacro("__rtems__"); 4735 Builder.defineMacro("__ELF__"); 4736 } 4737 4738 public: 4739 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4740 : OSTargetInfo<Target>(Triple, Opts) { 4741 switch (Triple.getArch()) { 4742 default: 4743 case llvm::Triple::x86: 4744 // this->MCountName = ".mcount"; 4745 break; 4746 case llvm::Triple::mips: 4747 case llvm::Triple::mipsel: 4748 case llvm::Triple::ppc: 4749 case llvm::Triple::ppc64: 4750 case llvm::Triple::ppc64le: 4751 // this->MCountName = "_mcount"; 4752 break; 4753 case llvm::Triple::arm: 4754 // this->MCountName = "__mcount"; 4755 break; 4756 } 4757 } 4758 }; 4759 4760 // x86-32 RTEMS target 4761 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4762 public: 4763 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4764 : X86_32TargetInfo(Triple, Opts) { 4765 SizeType = UnsignedLong; 4766 IntPtrType = SignedLong; 4767 PtrDiffType = SignedLong; 4768 } 4769 void getTargetDefines(const LangOptions &Opts, 4770 MacroBuilder &Builder) const override { 4771 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4772 Builder.defineMacro("__INTEL__"); 4773 Builder.defineMacro("__rtems__"); 4774 } 4775 }; 4776 4777 // x86-64 generic target 4778 class X86_64TargetInfo : public X86TargetInfo { 4779 public: 4780 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4781 : X86TargetInfo(Triple, Opts) { 4782 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4783 bool IsWinCOFF = 4784 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4785 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4786 LongDoubleWidth = 128; 4787 LongDoubleAlign = 128; 4788 LargeArrayMinWidth = 128; 4789 LargeArrayAlign = 128; 4790 SuitableAlign = 128; 4791 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4792 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4793 IntPtrType = IsX32 ? SignedInt : SignedLong; 4794 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4795 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4796 RegParmMax = 6; 4797 4798 // Pointers are 32-bit in x32. 4799 resetDataLayout(IsX32 4800 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4801 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4802 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4803 4804 // Use fpret only for long double. 4805 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4806 4807 // Use fp2ret for _Complex long double. 4808 ComplexLongDoubleUsesFP2Ret = true; 4809 4810 // Make __builtin_ms_va_list available. 4811 HasBuiltinMSVaList = true; 4812 4813 // x86-64 has atomics up to 16 bytes. 4814 MaxAtomicPromoteWidth = 128; 4815 MaxAtomicInlineWidth = 128; 4816 } 4817 BuiltinVaListKind getBuiltinVaListKind() const override { 4818 return TargetInfo::X86_64ABIBuiltinVaList; 4819 } 4820 4821 int getEHDataRegisterNumber(unsigned RegNo) const override { 4822 if (RegNo == 0) return 0; 4823 if (RegNo == 1) return 1; 4824 return -1; 4825 } 4826 4827 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4828 switch (CC) { 4829 case CC_C: 4830 case CC_Swift: 4831 case CC_X86VectorCall: 4832 case CC_IntelOclBicc: 4833 case CC_X86_64Win64: 4834 case CC_PreserveMost: 4835 case CC_PreserveAll: 4836 case CC_X86RegCall: 4837 return CCCR_OK; 4838 default: 4839 return CCCR_Warning; 4840 } 4841 } 4842 4843 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4844 return CC_C; 4845 } 4846 4847 // for x32 we need it here explicitly 4848 bool hasInt128Type() const override { return true; } 4849 unsigned getUnwindWordWidth() const override { return 64; } 4850 unsigned getRegisterWidth() const override { return 64; } 4851 4852 bool validateGlobalRegisterVariable(StringRef RegName, 4853 unsigned RegSize, 4854 bool &HasSizeMismatch) const override { 4855 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4856 // handle. 4857 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4858 // Check that the register size is 64-bit. 4859 HasSizeMismatch = RegSize != 64; 4860 return true; 4861 } 4862 4863 // Check if the register is a 32-bit register the backend can handle. 4864 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4865 HasSizeMismatch); 4866 } 4867 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4868 return llvm::makeArrayRef(BuiltinInfoX86, 4869 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4870 } 4871 }; 4872 4873 // x86-64 Windows target 4874 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4875 public: 4876 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4877 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4878 WCharType = UnsignedShort; 4879 LongWidth = LongAlign = 32; 4880 DoubleAlign = LongLongAlign = 64; 4881 IntMaxType = SignedLongLong; 4882 Int64Type = SignedLongLong; 4883 SizeType = UnsignedLongLong; 4884 PtrDiffType = SignedLongLong; 4885 IntPtrType = SignedLongLong; 4886 } 4887 4888 void getTargetDefines(const LangOptions &Opts, 4889 MacroBuilder &Builder) const override { 4890 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4891 Builder.defineMacro("_WIN64"); 4892 } 4893 4894 BuiltinVaListKind getBuiltinVaListKind() const override { 4895 return TargetInfo::CharPtrBuiltinVaList; 4896 } 4897 4898 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4899 switch (CC) { 4900 case CC_X86StdCall: 4901 case CC_X86ThisCall: 4902 case CC_X86FastCall: 4903 return CCCR_Ignore; 4904 case CC_C: 4905 case CC_X86VectorCall: 4906 case CC_IntelOclBicc: 4907 case CC_X86_64SysV: 4908 case CC_Swift: 4909 case CC_X86RegCall: 4910 return CCCR_OK; 4911 default: 4912 return CCCR_Warning; 4913 } 4914 } 4915 }; 4916 4917 // x86-64 Windows Visual Studio target 4918 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4919 public: 4920 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4921 const TargetOptions &Opts) 4922 : WindowsX86_64TargetInfo(Triple, Opts) { 4923 LongDoubleWidth = LongDoubleAlign = 64; 4924 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4925 } 4926 void getTargetDefines(const LangOptions &Opts, 4927 MacroBuilder &Builder) const override { 4928 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4929 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4930 Builder.defineMacro("_M_X64", "100"); 4931 Builder.defineMacro("_M_AMD64", "100"); 4932 } 4933 }; 4934 4935 // x86-64 MinGW target 4936 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4937 public: 4938 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4939 : WindowsX86_64TargetInfo(Triple, Opts) { 4940 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4941 // with x86 FP ops. Weird. 4942 LongDoubleWidth = LongDoubleAlign = 128; 4943 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 4944 HasFloat128 = true; 4945 } 4946 4947 void getTargetDefines(const LangOptions &Opts, 4948 MacroBuilder &Builder) const override { 4949 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4950 DefineStd(Builder, "WIN64", Opts); 4951 Builder.defineMacro("__MINGW64__"); 4952 addMinGWDefines(Opts, Builder); 4953 4954 // GCC defines this macro when it is using __gxx_personality_seh0. 4955 if (!Opts.SjLjExceptions) 4956 Builder.defineMacro("__SEH__"); 4957 } 4958 }; 4959 4960 // x86-64 Cygwin target 4961 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4962 public: 4963 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4964 : X86_64TargetInfo(Triple, Opts) { 4965 TLSSupported = false; 4966 WCharType = UnsignedShort; 4967 } 4968 void getTargetDefines(const LangOptions &Opts, 4969 MacroBuilder &Builder) const override { 4970 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4971 Builder.defineMacro("__x86_64__"); 4972 Builder.defineMacro("__CYGWIN__"); 4973 Builder.defineMacro("__CYGWIN64__"); 4974 addCygMingDefines(Opts, Builder); 4975 DefineStd(Builder, "unix", Opts); 4976 if (Opts.CPlusPlus) 4977 Builder.defineMacro("_GNU_SOURCE"); 4978 4979 // GCC defines this macro when it is using __gxx_personality_seh0. 4980 if (!Opts.SjLjExceptions) 4981 Builder.defineMacro("__SEH__"); 4982 } 4983 }; 4984 4985 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4986 public: 4987 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4988 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4989 Int64Type = SignedLongLong; 4990 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4991 llvm::Triple T = llvm::Triple(Triple); 4992 if (T.isiOS()) 4993 UseSignedCharForObjCBool = false; 4994 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4995 } 4996 4997 bool handleTargetFeatures(std::vector<std::string> &Features, 4998 DiagnosticsEngine &Diags) override { 4999 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 5000 Diags)) 5001 return false; 5002 // We now know the features we have: we can decide how to align vectors. 5003 MaxVectorAlign = 5004 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 5005 return true; 5006 } 5007 }; 5008 5009 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 5010 public: 5011 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5012 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5013 IntMaxType = SignedLongLong; 5014 Int64Type = SignedLongLong; 5015 } 5016 }; 5017 5018 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 5019 public: 5020 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5021 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5022 IntMaxType = SignedLongLong; 5023 Int64Type = SignedLongLong; 5024 } 5025 }; 5026 5027 class ARMTargetInfo : public TargetInfo { 5028 // Possible FPU choices. 5029 enum FPUMode { 5030 VFP2FPU = (1 << 0), 5031 VFP3FPU = (1 << 1), 5032 VFP4FPU = (1 << 2), 5033 NeonFPU = (1 << 3), 5034 FPARMV8 = (1 << 4) 5035 }; 5036 5037 // Possible HWDiv features. 5038 enum HWDivMode { 5039 HWDivThumb = (1 << 0), 5040 HWDivARM = (1 << 1) 5041 }; 5042 5043 static bool FPUModeIsVFP(FPUMode Mode) { 5044 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 5045 } 5046 5047 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5048 static const char * const GCCRegNames[]; 5049 5050 std::string ABI, CPU; 5051 5052 StringRef CPUProfile; 5053 StringRef CPUAttr; 5054 5055 enum { 5056 FP_Default, 5057 FP_VFP, 5058 FP_Neon 5059 } FPMath; 5060 5061 unsigned ArchISA; 5062 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 5063 unsigned ArchProfile; 5064 unsigned ArchVersion; 5065 5066 unsigned FPU : 5; 5067 5068 unsigned IsAAPCS : 1; 5069 unsigned HWDiv : 2; 5070 5071 // Initialized via features. 5072 unsigned SoftFloat : 1; 5073 unsigned SoftFloatABI : 1; 5074 5075 unsigned CRC : 1; 5076 unsigned Crypto : 1; 5077 unsigned DSP : 1; 5078 unsigned Unaligned : 1; 5079 5080 enum { 5081 LDREX_B = (1 << 0), /// byte (8-bit) 5082 LDREX_H = (1 << 1), /// half (16-bit) 5083 LDREX_W = (1 << 2), /// word (32-bit) 5084 LDREX_D = (1 << 3), /// double (64-bit) 5085 }; 5086 5087 uint32_t LDREX; 5088 5089 // ACLE 6.5.1 Hardware floating point 5090 enum { 5091 HW_FP_HP = (1 << 1), /// half (16-bit) 5092 HW_FP_SP = (1 << 2), /// single (32-bit) 5093 HW_FP_DP = (1 << 3), /// double (64-bit) 5094 }; 5095 uint32_t HW_FP; 5096 5097 static const Builtin::Info BuiltinInfo[]; 5098 5099 void setABIAAPCS() { 5100 IsAAPCS = true; 5101 5102 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5103 const llvm::Triple &T = getTriple(); 5104 5105 // size_t is unsigned long on MachO-derived environments, NetBSD, 5106 // OpenBSD and Bitrig. 5107 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 5108 T.getOS() == llvm::Triple::OpenBSD || 5109 T.getOS() == llvm::Triple::Bitrig) 5110 SizeType = UnsignedLong; 5111 else 5112 SizeType = UnsignedInt; 5113 5114 switch (T.getOS()) { 5115 case llvm::Triple::NetBSD: 5116 case llvm::Triple::OpenBSD: 5117 WCharType = SignedInt; 5118 break; 5119 case llvm::Triple::Win32: 5120 WCharType = UnsignedShort; 5121 break; 5122 case llvm::Triple::Linux: 5123 default: 5124 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 5125 WCharType = UnsignedInt; 5126 break; 5127 } 5128 5129 UseBitFieldTypeAlignment = true; 5130 5131 ZeroLengthBitfieldBoundary = 0; 5132 5133 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 5134 // so set preferred for small types to 32. 5135 if (T.isOSBinFormatMachO()) { 5136 resetDataLayout(BigEndian 5137 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5138 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5139 } else if (T.isOSWindows()) { 5140 assert(!BigEndian && "Windows on ARM does not support big endian"); 5141 resetDataLayout("e" 5142 "-m:w" 5143 "-p:32:32" 5144 "-i64:64" 5145 "-v128:64:128" 5146 "-a:0:32" 5147 "-n32" 5148 "-S64"); 5149 } else if (T.isOSNaCl()) { 5150 assert(!BigEndian && "NaCl on ARM does not support big endian"); 5151 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 5152 } else { 5153 resetDataLayout(BigEndian 5154 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5155 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5156 } 5157 5158 // FIXME: Enumerated types are variable width in straight AAPCS. 5159 } 5160 5161 void setABIAPCS(bool IsAAPCS16) { 5162 const llvm::Triple &T = getTriple(); 5163 5164 IsAAPCS = false; 5165 5166 if (IsAAPCS16) 5167 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5168 else 5169 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 5170 5171 // size_t is unsigned int on FreeBSD. 5172 if (T.getOS() == llvm::Triple::FreeBSD) 5173 SizeType = UnsignedInt; 5174 else 5175 SizeType = UnsignedLong; 5176 5177 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 5178 WCharType = SignedInt; 5179 5180 // Do not respect the alignment of bit-field types when laying out 5181 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 5182 UseBitFieldTypeAlignment = false; 5183 5184 /// gcc forces the alignment to 4 bytes, regardless of the type of the 5185 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 5186 /// gcc. 5187 ZeroLengthBitfieldBoundary = 32; 5188 5189 if (T.isOSBinFormatMachO() && IsAAPCS16) { 5190 assert(!BigEndian && "AAPCS16 does not support big-endian"); 5191 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 5192 } else if (T.isOSBinFormatMachO()) 5193 resetDataLayout( 5194 BigEndian 5195 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5196 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5197 else 5198 resetDataLayout( 5199 BigEndian 5200 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5201 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5202 5203 // FIXME: Override "preferred align" for double and long long. 5204 } 5205 5206 void setArchInfo() { 5207 StringRef ArchName = getTriple().getArchName(); 5208 5209 ArchISA = llvm::ARM::parseArchISA(ArchName); 5210 CPU = llvm::ARM::getDefaultCPU(ArchName); 5211 unsigned AK = llvm::ARM::parseArch(ArchName); 5212 if (AK != llvm::ARM::AK_INVALID) 5213 ArchKind = AK; 5214 setArchInfo(ArchKind); 5215 } 5216 5217 void setArchInfo(unsigned Kind) { 5218 StringRef SubArch; 5219 5220 // cache TargetParser info 5221 ArchKind = Kind; 5222 SubArch = llvm::ARM::getSubArch(ArchKind); 5223 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5224 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5225 5226 // cache CPU related strings 5227 CPUAttr = getCPUAttr(); 5228 CPUProfile = getCPUProfile(); 5229 } 5230 5231 void setAtomic() { 5232 // when triple does not specify a sub arch, 5233 // then we are not using inline atomics 5234 bool ShouldUseInlineAtomic = 5235 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5236 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5237 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5238 if (ArchProfile == llvm::ARM::PK_M) { 5239 MaxAtomicPromoteWidth = 32; 5240 if (ShouldUseInlineAtomic) 5241 MaxAtomicInlineWidth = 32; 5242 } 5243 else { 5244 MaxAtomicPromoteWidth = 64; 5245 if (ShouldUseInlineAtomic) 5246 MaxAtomicInlineWidth = 64; 5247 } 5248 } 5249 5250 bool isThumb() const { 5251 return (ArchISA == llvm::ARM::IK_THUMB); 5252 } 5253 5254 bool supportsThumb() const { 5255 return CPUAttr.count('T') || ArchVersion >= 6; 5256 } 5257 5258 bool supportsThumb2() const { 5259 return CPUAttr.equals("6T2") || 5260 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5261 } 5262 5263 StringRef getCPUAttr() const { 5264 // For most sub-arches, the build attribute CPU name is enough. 5265 // For Cortex variants, it's slightly different. 5266 switch(ArchKind) { 5267 default: 5268 return llvm::ARM::getCPUAttr(ArchKind); 5269 case llvm::ARM::AK_ARMV6M: 5270 return "6M"; 5271 case llvm::ARM::AK_ARMV7S: 5272 return "7S"; 5273 case llvm::ARM::AK_ARMV7A: 5274 return "7A"; 5275 case llvm::ARM::AK_ARMV7R: 5276 return "7R"; 5277 case llvm::ARM::AK_ARMV7M: 5278 return "7M"; 5279 case llvm::ARM::AK_ARMV7EM: 5280 return "7EM"; 5281 case llvm::ARM::AK_ARMV7VE: 5282 return "7VE"; 5283 case llvm::ARM::AK_ARMV8A: 5284 return "8A"; 5285 case llvm::ARM::AK_ARMV8_1A: 5286 return "8_1A"; 5287 case llvm::ARM::AK_ARMV8_2A: 5288 return "8_2A"; 5289 case llvm::ARM::AK_ARMV8MBaseline: 5290 return "8M_BASE"; 5291 case llvm::ARM::AK_ARMV8MMainline: 5292 return "8M_MAIN"; 5293 case llvm::ARM::AK_ARMV8R: 5294 return "8R"; 5295 } 5296 } 5297 5298 StringRef getCPUProfile() const { 5299 switch(ArchProfile) { 5300 case llvm::ARM::PK_A: 5301 return "A"; 5302 case llvm::ARM::PK_R: 5303 return "R"; 5304 case llvm::ARM::PK_M: 5305 return "M"; 5306 default: 5307 return ""; 5308 } 5309 } 5310 5311 public: 5312 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5313 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5314 HW_FP(0) { 5315 5316 switch (getTriple().getOS()) { 5317 case llvm::Triple::NetBSD: 5318 case llvm::Triple::OpenBSD: 5319 PtrDiffType = SignedLong; 5320 break; 5321 default: 5322 PtrDiffType = SignedInt; 5323 break; 5324 } 5325 5326 // Cache arch related info. 5327 setArchInfo(); 5328 5329 // {} in inline assembly are neon specifiers, not assembly variant 5330 // specifiers. 5331 NoAsmVariants = true; 5332 5333 // FIXME: This duplicates code from the driver that sets the -target-abi 5334 // option - this code is used if -target-abi isn't passed and should 5335 // be unified in some way. 5336 if (Triple.isOSBinFormatMachO()) { 5337 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5338 // the frontend matches that. 5339 if (Triple.getEnvironment() == llvm::Triple::EABI || 5340 Triple.getOS() == llvm::Triple::UnknownOS || 5341 ArchProfile == llvm::ARM::PK_M) { 5342 setABI("aapcs"); 5343 } else if (Triple.isWatchABI()) { 5344 setABI("aapcs16"); 5345 } else { 5346 setABI("apcs-gnu"); 5347 } 5348 } else if (Triple.isOSWindows()) { 5349 // FIXME: this is invalid for WindowsCE 5350 setABI("aapcs"); 5351 } else { 5352 // Select the default based on the platform. 5353 switch (Triple.getEnvironment()) { 5354 case llvm::Triple::Android: 5355 case llvm::Triple::GNUEABI: 5356 case llvm::Triple::GNUEABIHF: 5357 case llvm::Triple::MuslEABI: 5358 case llvm::Triple::MuslEABIHF: 5359 setABI("aapcs-linux"); 5360 break; 5361 case llvm::Triple::EABIHF: 5362 case llvm::Triple::EABI: 5363 setABI("aapcs"); 5364 break; 5365 case llvm::Triple::GNU: 5366 setABI("apcs-gnu"); 5367 break; 5368 default: 5369 if (Triple.getOS() == llvm::Triple::NetBSD) 5370 setABI("apcs-gnu"); 5371 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5372 setABI("aapcs-linux"); 5373 else 5374 setABI("aapcs"); 5375 break; 5376 } 5377 } 5378 5379 // ARM targets default to using the ARM C++ ABI. 5380 TheCXXABI.set(TargetCXXABI::GenericARM); 5381 5382 // ARM has atomics up to 8 bytes 5383 setAtomic(); 5384 5385 // Do force alignment of members that follow zero length bitfields. If 5386 // the alignment of the zero-length bitfield is greater than the member 5387 // that follows it, `bar', `bar' will be aligned as the type of the 5388 // zero length bitfield. 5389 UseZeroLengthBitfieldAlignment = true; 5390 5391 if (Triple.getOS() == llvm::Triple::Linux || 5392 Triple.getOS() == llvm::Triple::UnknownOS) 5393 this->MCountName = 5394 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5395 } 5396 5397 StringRef getABI() const override { return ABI; } 5398 5399 bool setABI(const std::string &Name) override { 5400 ABI = Name; 5401 5402 // The defaults (above) are for AAPCS, check if we need to change them. 5403 // 5404 // FIXME: We need support for -meabi... we could just mangle it into the 5405 // name. 5406 if (Name == "apcs-gnu" || Name == "aapcs16") { 5407 setABIAPCS(Name == "aapcs16"); 5408 return true; 5409 } 5410 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5411 setABIAAPCS(); 5412 return true; 5413 } 5414 return false; 5415 } 5416 5417 // FIXME: This should be based on Arch attributes, not CPU names. 5418 bool 5419 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5420 StringRef CPU, 5421 const std::vector<std::string> &FeaturesVec) const override { 5422 5423 std::vector<StringRef> TargetFeatures; 5424 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5425 5426 // get default FPU features 5427 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5428 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5429 5430 // get default Extension features 5431 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5432 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5433 5434 for (auto Feature : TargetFeatures) 5435 if (Feature[0] == '+') 5436 Features[Feature.drop_front(1)] = true; 5437 5438 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5439 } 5440 5441 bool handleTargetFeatures(std::vector<std::string> &Features, 5442 DiagnosticsEngine &Diags) override { 5443 FPU = 0; 5444 CRC = 0; 5445 Crypto = 0; 5446 DSP = 0; 5447 Unaligned = 1; 5448 SoftFloat = SoftFloatABI = false; 5449 HWDiv = 0; 5450 5451 // This does not diagnose illegal cases like having both 5452 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5453 uint32_t HW_FP_remove = 0; 5454 for (const auto &Feature : Features) { 5455 if (Feature == "+soft-float") { 5456 SoftFloat = true; 5457 } else if (Feature == "+soft-float-abi") { 5458 SoftFloatABI = true; 5459 } else if (Feature == "+vfp2") { 5460 FPU |= VFP2FPU; 5461 HW_FP |= HW_FP_SP | HW_FP_DP; 5462 } else if (Feature == "+vfp3") { 5463 FPU |= VFP3FPU; 5464 HW_FP |= HW_FP_SP | HW_FP_DP; 5465 } else if (Feature == "+vfp4") { 5466 FPU |= VFP4FPU; 5467 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5468 } else if (Feature == "+fp-armv8") { 5469 FPU |= FPARMV8; 5470 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5471 } else if (Feature == "+neon") { 5472 FPU |= NeonFPU; 5473 HW_FP |= HW_FP_SP | HW_FP_DP; 5474 } else if (Feature == "+hwdiv") { 5475 HWDiv |= HWDivThumb; 5476 } else if (Feature == "+hwdiv-arm") { 5477 HWDiv |= HWDivARM; 5478 } else if (Feature == "+crc") { 5479 CRC = 1; 5480 } else if (Feature == "+crypto") { 5481 Crypto = 1; 5482 } else if (Feature == "+dsp") { 5483 DSP = 1; 5484 } else if (Feature == "+fp-only-sp") { 5485 HW_FP_remove |= HW_FP_DP; 5486 } else if (Feature == "+strict-align") { 5487 Unaligned = 0; 5488 } else if (Feature == "+fp16") { 5489 HW_FP |= HW_FP_HP; 5490 } 5491 } 5492 HW_FP &= ~HW_FP_remove; 5493 5494 switch (ArchVersion) { 5495 case 6: 5496 if (ArchProfile == llvm::ARM::PK_M) 5497 LDREX = 0; 5498 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5499 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5500 else 5501 LDREX = LDREX_W; 5502 break; 5503 case 7: 5504 if (ArchProfile == llvm::ARM::PK_M) 5505 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5506 else 5507 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5508 break; 5509 case 8: 5510 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5511 } 5512 5513 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5514 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5515 return false; 5516 } 5517 5518 if (FPMath == FP_Neon) 5519 Features.push_back("+neonfp"); 5520 else if (FPMath == FP_VFP) 5521 Features.push_back("-neonfp"); 5522 5523 // Remove front-end specific options which the backend handles differently. 5524 auto Feature = 5525 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5526 if (Feature != Features.end()) 5527 Features.erase(Feature); 5528 5529 return true; 5530 } 5531 5532 bool hasFeature(StringRef Feature) const override { 5533 return llvm::StringSwitch<bool>(Feature) 5534 .Case("arm", true) 5535 .Case("aarch32", true) 5536 .Case("softfloat", SoftFloat) 5537 .Case("thumb", isThumb()) 5538 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5539 .Case("vfp", FPU && !SoftFloat) 5540 .Case("hwdiv", HWDiv & HWDivThumb) 5541 .Case("hwdiv-arm", HWDiv & HWDivARM) 5542 .Default(false); 5543 } 5544 5545 bool setCPU(const std::string &Name) override { 5546 if (Name != "generic") 5547 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5548 5549 if (ArchKind == llvm::ARM::AK_INVALID) 5550 return false; 5551 setAtomic(); 5552 CPU = Name; 5553 return true; 5554 } 5555 5556 bool setFPMath(StringRef Name) override; 5557 5558 void getTargetDefines(const LangOptions &Opts, 5559 MacroBuilder &Builder) const override { 5560 // Target identification. 5561 Builder.defineMacro("__arm"); 5562 Builder.defineMacro("__arm__"); 5563 // For bare-metal none-eabi. 5564 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5565 (getTriple().getEnvironment() == llvm::Triple::EABI || 5566 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 5567 Builder.defineMacro("__ELF__"); 5568 5569 5570 // Target properties. 5571 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5572 5573 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5574 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5575 if (getTriple().isWatchABI()) 5576 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5577 5578 if (!CPUAttr.empty()) 5579 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5580 5581 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5582 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5583 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5584 5585 if (ArchVersion >= 8) { 5586 // ACLE 6.5.7 Crypto Extension 5587 if (Crypto) 5588 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5589 // ACLE 6.5.8 CRC32 Extension 5590 if (CRC) 5591 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5592 // ACLE 6.5.10 Numeric Maximum and Minimum 5593 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5594 // ACLE 6.5.9 Directed Rounding 5595 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5596 } 5597 5598 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5599 // is not defined for the M-profile. 5600 // NOTE that the default profile is assumed to be 'A' 5601 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5602 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5603 5604 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5605 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5606 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5607 // v7 and v8 architectures excluding v8-M Baseline. 5608 if (supportsThumb2()) 5609 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5610 else if (supportsThumb()) 5611 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5612 5613 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5614 // instruction set such as ARM or Thumb. 5615 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5616 5617 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5618 5619 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5620 if (!CPUProfile.empty()) 5621 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5622 5623 // ACLE 6.4.3 Unaligned access supported in hardware 5624 if (Unaligned) 5625 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5626 5627 // ACLE 6.4.4 LDREX/STREX 5628 if (LDREX) 5629 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5630 5631 // ACLE 6.4.5 CLZ 5632 if (ArchVersion == 5 || 5633 (ArchVersion == 6 && CPUProfile != "M") || 5634 ArchVersion > 6) 5635 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5636 5637 // ACLE 6.5.1 Hardware Floating Point 5638 if (HW_FP) 5639 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5640 5641 // ACLE predefines. 5642 Builder.defineMacro("__ARM_ACLE", "200"); 5643 5644 // FP16 support (we currently only support IEEE format). 5645 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5646 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5647 5648 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5649 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5650 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5651 5652 // Subtarget options. 5653 5654 // FIXME: It's more complicated than this and we don't really support 5655 // interworking. 5656 // Windows on ARM does not "support" interworking 5657 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5658 Builder.defineMacro("__THUMB_INTERWORK__"); 5659 5660 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5661 // Embedded targets on Darwin follow AAPCS, but not EABI. 5662 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5663 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5664 Builder.defineMacro("__ARM_EABI__"); 5665 Builder.defineMacro("__ARM_PCS", "1"); 5666 } 5667 5668 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5669 ABI == "aapcs16") 5670 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5671 5672 if (SoftFloat) 5673 Builder.defineMacro("__SOFTFP__"); 5674 5675 if (ArchKind == llvm::ARM::AK_XSCALE) 5676 Builder.defineMacro("__XSCALE__"); 5677 5678 if (isThumb()) { 5679 Builder.defineMacro("__THUMBEL__"); 5680 Builder.defineMacro("__thumb__"); 5681 if (supportsThumb2()) 5682 Builder.defineMacro("__thumb2__"); 5683 } 5684 5685 // ACLE 6.4.9 32-bit SIMD instructions 5686 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5687 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5688 5689 // ACLE 6.4.10 Hardware Integer Divide 5690 if (((HWDiv & HWDivThumb) && isThumb()) || 5691 ((HWDiv & HWDivARM) && !isThumb())) { 5692 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5693 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5694 } 5695 5696 // Note, this is always on in gcc, even though it doesn't make sense. 5697 Builder.defineMacro("__APCS_32__"); 5698 5699 if (FPUModeIsVFP((FPUMode) FPU)) { 5700 Builder.defineMacro("__VFP_FP__"); 5701 if (FPU & VFP2FPU) 5702 Builder.defineMacro("__ARM_VFPV2__"); 5703 if (FPU & VFP3FPU) 5704 Builder.defineMacro("__ARM_VFPV3__"); 5705 if (FPU & VFP4FPU) 5706 Builder.defineMacro("__ARM_VFPV4__"); 5707 if (FPU & FPARMV8) 5708 Builder.defineMacro("__ARM_FPV5__"); 5709 } 5710 5711 // This only gets set when Neon instructions are actually available, unlike 5712 // the VFP define, hence the soft float and arch check. This is subtly 5713 // different from gcc, we follow the intent which was that it should be set 5714 // when Neon instructions are actually available. 5715 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5716 Builder.defineMacro("__ARM_NEON", "1"); 5717 Builder.defineMacro("__ARM_NEON__"); 5718 // current AArch32 NEON implementations do not support double-precision 5719 // floating-point even when it is present in VFP. 5720 Builder.defineMacro("__ARM_NEON_FP", 5721 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5722 } 5723 5724 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5725 Opts.ShortWChar ? "2" : "4"); 5726 5727 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5728 Opts.ShortEnums ? "1" : "4"); 5729 5730 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5731 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5732 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5733 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5734 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5735 } 5736 5737 // ACLE 6.4.7 DSP instructions 5738 if (DSP) { 5739 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5740 } 5741 5742 // ACLE 6.4.8 Saturation instructions 5743 bool SAT = false; 5744 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5745 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5746 SAT = true; 5747 } 5748 5749 // ACLE 6.4.6 Q (saturation) flag 5750 if (DSP || SAT) 5751 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5752 5753 if (Opts.UnsafeFPMath) 5754 Builder.defineMacro("__ARM_FP_FAST", "1"); 5755 5756 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5757 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5758 } 5759 5760 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5761 return llvm::makeArrayRef(BuiltinInfo, 5762 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5763 } 5764 bool isCLZForZeroUndef() const override { return false; } 5765 BuiltinVaListKind getBuiltinVaListKind() const override { 5766 return IsAAPCS 5767 ? AAPCSABIBuiltinVaList 5768 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5769 : TargetInfo::VoidPtrBuiltinVaList); 5770 } 5771 ArrayRef<const char *> getGCCRegNames() const override; 5772 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5773 bool validateAsmConstraint(const char *&Name, 5774 TargetInfo::ConstraintInfo &Info) const override { 5775 switch (*Name) { 5776 default: break; 5777 case 'l': // r0-r7 5778 case 'h': // r8-r15 5779 case 't': // VFP Floating point register single precision 5780 case 'w': // VFP Floating point register double precision 5781 Info.setAllowsRegister(); 5782 return true; 5783 case 'I': 5784 case 'J': 5785 case 'K': 5786 case 'L': 5787 case 'M': 5788 // FIXME 5789 return true; 5790 case 'Q': // A memory address that is a single base register. 5791 Info.setAllowsMemory(); 5792 return true; 5793 case 'U': // a memory reference... 5794 switch (Name[1]) { 5795 case 'q': // ...ARMV4 ldrsb 5796 case 'v': // ...VFP load/store (reg+constant offset) 5797 case 'y': // ...iWMMXt load/store 5798 case 't': // address valid for load/store opaque types wider 5799 // than 128-bits 5800 case 'n': // valid address for Neon doubleword vector load/store 5801 case 'm': // valid address for Neon element and structure load/store 5802 case 's': // valid address for non-offset loads/stores of quad-word 5803 // values in four ARM registers 5804 Info.setAllowsMemory(); 5805 Name++; 5806 return true; 5807 } 5808 } 5809 return false; 5810 } 5811 std::string convertConstraint(const char *&Constraint) const override { 5812 std::string R; 5813 switch (*Constraint) { 5814 case 'U': // Two-character constraint; add "^" hint for later parsing. 5815 R = std::string("^") + std::string(Constraint, 2); 5816 Constraint++; 5817 break; 5818 case 'p': // 'p' should be translated to 'r' by default. 5819 R = std::string("r"); 5820 break; 5821 default: 5822 return std::string(1, *Constraint); 5823 } 5824 return R; 5825 } 5826 bool 5827 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5828 std::string &SuggestedModifier) const override { 5829 bool isOutput = (Constraint[0] == '='); 5830 bool isInOut = (Constraint[0] == '+'); 5831 5832 // Strip off constraint modifiers. 5833 while (Constraint[0] == '=' || 5834 Constraint[0] == '+' || 5835 Constraint[0] == '&') 5836 Constraint = Constraint.substr(1); 5837 5838 switch (Constraint[0]) { 5839 default: break; 5840 case 'r': { 5841 switch (Modifier) { 5842 default: 5843 return (isInOut || isOutput || Size <= 64); 5844 case 'q': 5845 // A register of size 32 cannot fit a vector type. 5846 return false; 5847 } 5848 } 5849 } 5850 5851 return true; 5852 } 5853 const char *getClobbers() const override { 5854 // FIXME: Is this really right? 5855 return ""; 5856 } 5857 5858 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5859 switch (CC) { 5860 case CC_AAPCS: 5861 case CC_AAPCS_VFP: 5862 case CC_Swift: 5863 return CCCR_OK; 5864 default: 5865 return CCCR_Warning; 5866 } 5867 } 5868 5869 int getEHDataRegisterNumber(unsigned RegNo) const override { 5870 if (RegNo == 0) return 0; 5871 if (RegNo == 1) return 1; 5872 return -1; 5873 } 5874 5875 bool hasSjLjLowering() const override { 5876 return true; 5877 } 5878 }; 5879 5880 bool ARMTargetInfo::setFPMath(StringRef Name) { 5881 if (Name == "neon") { 5882 FPMath = FP_Neon; 5883 return true; 5884 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5885 Name == "vfp4") { 5886 FPMath = FP_VFP; 5887 return true; 5888 } 5889 return false; 5890 } 5891 5892 const char * const ARMTargetInfo::GCCRegNames[] = { 5893 // Integer registers 5894 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5895 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5896 5897 // Float registers 5898 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5899 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5900 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5901 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5902 5903 // Double registers 5904 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5905 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5906 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5907 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5908 5909 // Quad registers 5910 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5911 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5912 }; 5913 5914 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5915 return llvm::makeArrayRef(GCCRegNames); 5916 } 5917 5918 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5919 { { "a1" }, "r0" }, 5920 { { "a2" }, "r1" }, 5921 { { "a3" }, "r2" }, 5922 { { "a4" }, "r3" }, 5923 { { "v1" }, "r4" }, 5924 { { "v2" }, "r5" }, 5925 { { "v3" }, "r6" }, 5926 { { "v4" }, "r7" }, 5927 { { "v5" }, "r8" }, 5928 { { "v6", "rfp" }, "r9" }, 5929 { { "sl" }, "r10" }, 5930 { { "fp" }, "r11" }, 5931 { { "ip" }, "r12" }, 5932 { { "r13" }, "sp" }, 5933 { { "r14" }, "lr" }, 5934 { { "r15" }, "pc" }, 5935 // The S, D and Q registers overlap, but aren't really aliases; we 5936 // don't want to substitute one of these for a different-sized one. 5937 }; 5938 5939 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5940 return llvm::makeArrayRef(GCCRegAliases); 5941 } 5942 5943 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5944 #define BUILTIN(ID, TYPE, ATTRS) \ 5945 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5946 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5947 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5948 #include "clang/Basic/BuiltinsNEON.def" 5949 5950 #define BUILTIN(ID, TYPE, ATTRS) \ 5951 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5952 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5953 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5954 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5955 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5956 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5957 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5958 #include "clang/Basic/BuiltinsARM.def" 5959 }; 5960 5961 class ARMleTargetInfo : public ARMTargetInfo { 5962 public: 5963 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5964 : ARMTargetInfo(Triple, Opts) {} 5965 void getTargetDefines(const LangOptions &Opts, 5966 MacroBuilder &Builder) const override { 5967 Builder.defineMacro("__ARMEL__"); 5968 ARMTargetInfo::getTargetDefines(Opts, Builder); 5969 } 5970 }; 5971 5972 class ARMbeTargetInfo : public ARMTargetInfo { 5973 public: 5974 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5975 : ARMTargetInfo(Triple, Opts) {} 5976 void getTargetDefines(const LangOptions &Opts, 5977 MacroBuilder &Builder) const override { 5978 Builder.defineMacro("__ARMEB__"); 5979 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5980 ARMTargetInfo::getTargetDefines(Opts, Builder); 5981 } 5982 }; 5983 5984 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5985 const llvm::Triple Triple; 5986 public: 5987 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5988 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5989 WCharType = UnsignedShort; 5990 SizeType = UnsignedInt; 5991 } 5992 void getVisualStudioDefines(const LangOptions &Opts, 5993 MacroBuilder &Builder) const { 5994 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5995 5996 // FIXME: this is invalid for WindowsCE 5997 Builder.defineMacro("_M_ARM_NT", "1"); 5998 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5999 Builder.defineMacro("_M_THUMB", "_M_ARM"); 6000 6001 assert((Triple.getArch() == llvm::Triple::arm || 6002 Triple.getArch() == llvm::Triple::thumb) && 6003 "invalid architecture for Windows ARM target info"); 6004 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 6005 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 6006 6007 // TODO map the complete set of values 6008 // 31: VFPv3 40: VFPv4 6009 Builder.defineMacro("_M_ARM_FP", "31"); 6010 } 6011 BuiltinVaListKind getBuiltinVaListKind() const override { 6012 return TargetInfo::CharPtrBuiltinVaList; 6013 } 6014 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6015 switch (CC) { 6016 case CC_X86StdCall: 6017 case CC_X86ThisCall: 6018 case CC_X86FastCall: 6019 case CC_X86VectorCall: 6020 return CCCR_Ignore; 6021 case CC_C: 6022 return CCCR_OK; 6023 default: 6024 return CCCR_Warning; 6025 } 6026 } 6027 }; 6028 6029 // Windows ARM + Itanium C++ ABI Target 6030 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 6031 public: 6032 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 6033 const TargetOptions &Opts) 6034 : WindowsARMTargetInfo(Triple, Opts) { 6035 TheCXXABI.set(TargetCXXABI::GenericARM); 6036 } 6037 6038 void getTargetDefines(const LangOptions &Opts, 6039 MacroBuilder &Builder) const override { 6040 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6041 6042 if (Opts.MSVCCompat) 6043 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6044 } 6045 }; 6046 6047 // Windows ARM, MS (C++) ABI 6048 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 6049 public: 6050 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 6051 const TargetOptions &Opts) 6052 : WindowsARMTargetInfo(Triple, Opts) { 6053 TheCXXABI.set(TargetCXXABI::Microsoft); 6054 } 6055 6056 void getTargetDefines(const LangOptions &Opts, 6057 MacroBuilder &Builder) const override { 6058 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6059 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6060 } 6061 }; 6062 6063 // ARM MinGW target 6064 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 6065 public: 6066 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6067 : WindowsARMTargetInfo(Triple, Opts) { 6068 TheCXXABI.set(TargetCXXABI::GenericARM); 6069 } 6070 6071 void getTargetDefines(const LangOptions &Opts, 6072 MacroBuilder &Builder) const override { 6073 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6074 DefineStd(Builder, "WIN32", Opts); 6075 DefineStd(Builder, "WINNT", Opts); 6076 Builder.defineMacro("_ARM_"); 6077 addMinGWDefines(Opts, Builder); 6078 } 6079 }; 6080 6081 // ARM Cygwin target 6082 class CygwinARMTargetInfo : public ARMleTargetInfo { 6083 public: 6084 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6085 : ARMleTargetInfo(Triple, Opts) { 6086 TLSSupported = false; 6087 WCharType = UnsignedShort; 6088 DoubleAlign = LongLongAlign = 64; 6089 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 6090 } 6091 void getTargetDefines(const LangOptions &Opts, 6092 MacroBuilder &Builder) const override { 6093 ARMleTargetInfo::getTargetDefines(Opts, Builder); 6094 Builder.defineMacro("_ARM_"); 6095 Builder.defineMacro("__CYGWIN__"); 6096 Builder.defineMacro("__CYGWIN32__"); 6097 DefineStd(Builder, "unix", Opts); 6098 if (Opts.CPlusPlus) 6099 Builder.defineMacro("_GNU_SOURCE"); 6100 } 6101 }; 6102 6103 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 6104 protected: 6105 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6106 MacroBuilder &Builder) const override { 6107 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6108 } 6109 6110 public: 6111 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6112 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 6113 HasAlignMac68kSupport = true; 6114 // iOS always has 64-bit atomic instructions. 6115 // FIXME: This should be based off of the target features in 6116 // ARMleTargetInfo. 6117 MaxAtomicInlineWidth = 64; 6118 6119 if (Triple.isWatchABI()) { 6120 // Darwin on iOS uses a variant of the ARM C++ ABI. 6121 TheCXXABI.set(TargetCXXABI::WatchOS); 6122 6123 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 6124 // size_t is long, it's a bit weird for it to be int. 6125 PtrDiffType = SignedLong; 6126 6127 // BOOL should be a real boolean on the new ABI 6128 UseSignedCharForObjCBool = false; 6129 } else 6130 TheCXXABI.set(TargetCXXABI::iOS); 6131 } 6132 }; 6133 6134 class AArch64TargetInfo : public TargetInfo { 6135 virtual void setDataLayout() = 0; 6136 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6137 static const char *const GCCRegNames[]; 6138 6139 enum FPUModeEnum { 6140 FPUMode, 6141 NeonMode 6142 }; 6143 6144 unsigned FPU; 6145 unsigned CRC; 6146 unsigned Crypto; 6147 unsigned Unaligned; 6148 unsigned V8_1A; 6149 6150 static const Builtin::Info BuiltinInfo[]; 6151 6152 std::string ABI; 6153 6154 public: 6155 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6156 : TargetInfo(Triple), ABI("aapcs") { 6157 if (getTriple().getOS() == llvm::Triple::NetBSD || 6158 getTriple().getOS() == llvm::Triple::OpenBSD) { 6159 WCharType = SignedInt; 6160 6161 // NetBSD apparently prefers consistency across ARM targets to consistency 6162 // across 64-bit targets. 6163 Int64Type = SignedLongLong; 6164 IntMaxType = SignedLongLong; 6165 } else { 6166 WCharType = UnsignedInt; 6167 Int64Type = SignedLong; 6168 IntMaxType = SignedLong; 6169 } 6170 6171 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6172 MaxVectorAlign = 128; 6173 MaxAtomicInlineWidth = 128; 6174 MaxAtomicPromoteWidth = 128; 6175 6176 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 6177 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6178 6179 // {} in inline assembly are neon specifiers, not assembly variant 6180 // specifiers. 6181 NoAsmVariants = true; 6182 6183 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 6184 // contributes to the alignment of the containing aggregate in the same way 6185 // a plain (non bit-field) member of that type would, without exception for 6186 // zero-sized or anonymous bit-fields." 6187 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 6188 UseZeroLengthBitfieldAlignment = true; 6189 6190 // AArch64 targets default to using the ARM C++ ABI. 6191 TheCXXABI.set(TargetCXXABI::GenericAArch64); 6192 6193 if (Triple.getOS() == llvm::Triple::Linux) 6194 this->MCountName = "\01_mcount"; 6195 else if (Triple.getOS() == llvm::Triple::UnknownOS) 6196 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 6197 } 6198 6199 StringRef getABI() const override { return ABI; } 6200 bool setABI(const std::string &Name) override { 6201 if (Name != "aapcs" && Name != "darwinpcs") 6202 return false; 6203 6204 ABI = Name; 6205 return true; 6206 } 6207 6208 bool setCPU(const std::string &Name) override { 6209 return Name == "generic" || 6210 llvm::AArch64::parseCPUArch(Name) != 6211 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6212 } 6213 6214 void getTargetDefines(const LangOptions &Opts, 6215 MacroBuilder &Builder) const override { 6216 // Target identification. 6217 Builder.defineMacro("__aarch64__"); 6218 // For bare-metal none-eabi. 6219 if (getTriple().getOS() == llvm::Triple::UnknownOS && 6220 (getTriple().getEnvironment() == llvm::Triple::EABI || 6221 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 6222 Builder.defineMacro("__ELF__"); 6223 6224 // Target properties. 6225 Builder.defineMacro("_LP64"); 6226 Builder.defineMacro("__LP64__"); 6227 6228 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6229 Builder.defineMacro("__ARM_ACLE", "200"); 6230 Builder.defineMacro("__ARM_ARCH", "8"); 6231 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6232 6233 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6234 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6235 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6236 6237 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6238 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6239 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6240 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6241 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6242 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6243 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6244 6245 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6246 6247 // 0xe implies support for half, single and double precision operations. 6248 Builder.defineMacro("__ARM_FP", "0xE"); 6249 6250 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6251 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6252 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6253 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6254 6255 if (Opts.UnsafeFPMath) 6256 Builder.defineMacro("__ARM_FP_FAST", "1"); 6257 6258 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6259 6260 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6261 Opts.ShortEnums ? "1" : "4"); 6262 6263 if (FPU == NeonMode) { 6264 Builder.defineMacro("__ARM_NEON", "1"); 6265 // 64-bit NEON supports half, single and double precision operations. 6266 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6267 } 6268 6269 if (CRC) 6270 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6271 6272 if (Crypto) 6273 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6274 6275 if (Unaligned) 6276 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6277 6278 if (V8_1A) 6279 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6280 6281 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6282 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6283 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6284 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6285 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6286 } 6287 6288 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6289 return llvm::makeArrayRef(BuiltinInfo, 6290 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6291 } 6292 6293 bool hasFeature(StringRef Feature) const override { 6294 return Feature == "aarch64" || 6295 Feature == "arm64" || 6296 Feature == "arm" || 6297 (Feature == "neon" && FPU == NeonMode); 6298 } 6299 6300 bool handleTargetFeatures(std::vector<std::string> &Features, 6301 DiagnosticsEngine &Diags) override { 6302 FPU = FPUMode; 6303 CRC = 0; 6304 Crypto = 0; 6305 Unaligned = 1; 6306 V8_1A = 0; 6307 6308 for (const auto &Feature : Features) { 6309 if (Feature == "+neon") 6310 FPU = NeonMode; 6311 if (Feature == "+crc") 6312 CRC = 1; 6313 if (Feature == "+crypto") 6314 Crypto = 1; 6315 if (Feature == "+strict-align") 6316 Unaligned = 0; 6317 if (Feature == "+v8.1a") 6318 V8_1A = 1; 6319 } 6320 6321 setDataLayout(); 6322 6323 return true; 6324 } 6325 6326 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6327 switch (CC) { 6328 case CC_C: 6329 case CC_Swift: 6330 case CC_PreserveMost: 6331 case CC_PreserveAll: 6332 return CCCR_OK; 6333 default: 6334 return CCCR_Warning; 6335 } 6336 } 6337 6338 bool isCLZForZeroUndef() const override { return false; } 6339 6340 BuiltinVaListKind getBuiltinVaListKind() const override { 6341 return TargetInfo::AArch64ABIBuiltinVaList; 6342 } 6343 6344 ArrayRef<const char *> getGCCRegNames() const override; 6345 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6346 6347 bool validateAsmConstraint(const char *&Name, 6348 TargetInfo::ConstraintInfo &Info) const override { 6349 switch (*Name) { 6350 default: 6351 return false; 6352 case 'w': // Floating point and SIMD registers (V0-V31) 6353 Info.setAllowsRegister(); 6354 return true; 6355 case 'I': // Constant that can be used with an ADD instruction 6356 case 'J': // Constant that can be used with a SUB instruction 6357 case 'K': // Constant that can be used with a 32-bit logical instruction 6358 case 'L': // Constant that can be used with a 64-bit logical instruction 6359 case 'M': // Constant that can be used as a 32-bit MOV immediate 6360 case 'N': // Constant that can be used as a 64-bit MOV immediate 6361 case 'Y': // Floating point constant zero 6362 case 'Z': // Integer constant zero 6363 return true; 6364 case 'Q': // A memory reference with base register and no offset 6365 Info.setAllowsMemory(); 6366 return true; 6367 case 'S': // A symbolic address 6368 Info.setAllowsRegister(); 6369 return true; 6370 case 'U': 6371 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6372 // Utf: A memory address suitable for ldp/stp in TF mode. 6373 // Usa: An absolute symbolic address. 6374 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6375 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6376 case 'z': // Zero register, wzr or xzr 6377 Info.setAllowsRegister(); 6378 return true; 6379 case 'x': // Floating point and SIMD registers (V0-V15) 6380 Info.setAllowsRegister(); 6381 return true; 6382 } 6383 return false; 6384 } 6385 6386 bool 6387 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6388 std::string &SuggestedModifier) const override { 6389 // Strip off constraint modifiers. 6390 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6391 Constraint = Constraint.substr(1); 6392 6393 switch (Constraint[0]) { 6394 default: 6395 return true; 6396 case 'z': 6397 case 'r': { 6398 switch (Modifier) { 6399 case 'x': 6400 case 'w': 6401 // For now assume that the person knows what they're 6402 // doing with the modifier. 6403 return true; 6404 default: 6405 // By default an 'r' constraint will be in the 'x' 6406 // registers. 6407 if (Size == 64) 6408 return true; 6409 6410 SuggestedModifier = "w"; 6411 return false; 6412 } 6413 } 6414 } 6415 } 6416 6417 const char *getClobbers() const override { return ""; } 6418 6419 int getEHDataRegisterNumber(unsigned RegNo) const override { 6420 if (RegNo == 0) 6421 return 0; 6422 if (RegNo == 1) 6423 return 1; 6424 return -1; 6425 } 6426 }; 6427 6428 const char *const AArch64TargetInfo::GCCRegNames[] = { 6429 // 32-bit Integer registers 6430 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6431 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6432 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6433 6434 // 64-bit Integer registers 6435 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6436 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6437 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6438 6439 // 32-bit floating point regsisters 6440 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6441 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6442 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6443 6444 // 64-bit floating point regsisters 6445 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6446 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6447 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6448 6449 // Vector registers 6450 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6451 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6452 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6453 }; 6454 6455 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6456 return llvm::makeArrayRef(GCCRegNames); 6457 } 6458 6459 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6460 { { "w31" }, "wsp" }, 6461 { { "x29" }, "fp" }, 6462 { { "x30" }, "lr" }, 6463 { { "x31" }, "sp" }, 6464 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6465 // don't want to substitute one of these for a different-sized one. 6466 }; 6467 6468 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6469 return llvm::makeArrayRef(GCCRegAliases); 6470 } 6471 6472 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6473 #define BUILTIN(ID, TYPE, ATTRS) \ 6474 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6475 #include "clang/Basic/BuiltinsNEON.def" 6476 6477 #define BUILTIN(ID, TYPE, ATTRS) \ 6478 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6479 #include "clang/Basic/BuiltinsAArch64.def" 6480 }; 6481 6482 class AArch64leTargetInfo : public AArch64TargetInfo { 6483 void setDataLayout() override { 6484 if (getTriple().isOSBinFormatMachO()) 6485 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6486 else 6487 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6488 } 6489 6490 public: 6491 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6492 : AArch64TargetInfo(Triple, Opts) { 6493 } 6494 void getTargetDefines(const LangOptions &Opts, 6495 MacroBuilder &Builder) const override { 6496 Builder.defineMacro("__AARCH64EL__"); 6497 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6498 } 6499 }; 6500 6501 class AArch64beTargetInfo : public AArch64TargetInfo { 6502 void setDataLayout() override { 6503 assert(!getTriple().isOSBinFormatMachO()); 6504 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6505 } 6506 6507 public: 6508 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6509 : AArch64TargetInfo(Triple, Opts) {} 6510 void getTargetDefines(const LangOptions &Opts, 6511 MacroBuilder &Builder) const override { 6512 Builder.defineMacro("__AARCH64EB__"); 6513 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6514 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6515 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6516 } 6517 }; 6518 6519 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6520 protected: 6521 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6522 MacroBuilder &Builder) const override { 6523 Builder.defineMacro("__AARCH64_SIMD__"); 6524 Builder.defineMacro("__ARM64_ARCH_8__"); 6525 Builder.defineMacro("__ARM_NEON__"); 6526 Builder.defineMacro("__LITTLE_ENDIAN__"); 6527 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6528 Builder.defineMacro("__arm64", "1"); 6529 Builder.defineMacro("__arm64__", "1"); 6530 6531 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6532 } 6533 6534 public: 6535 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6536 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6537 Int64Type = SignedLongLong; 6538 WCharType = SignedInt; 6539 UseSignedCharForObjCBool = false; 6540 6541 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6542 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6543 6544 TheCXXABI.set(TargetCXXABI::iOS64); 6545 } 6546 6547 BuiltinVaListKind getBuiltinVaListKind() const override { 6548 return TargetInfo::CharPtrBuiltinVaList; 6549 } 6550 }; 6551 6552 // Hexagon abstract base class 6553 class HexagonTargetInfo : public TargetInfo { 6554 static const Builtin::Info BuiltinInfo[]; 6555 static const char * const GCCRegNames[]; 6556 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6557 std::string CPU; 6558 bool HasHVX, HasHVXDouble; 6559 bool UseLongCalls; 6560 6561 public: 6562 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6563 : TargetInfo(Triple) { 6564 // Specify the vector alignment explicitly. For v512x1, the calculated 6565 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6566 // the required minimum of 64 bytes. 6567 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6568 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6569 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6570 SizeType = UnsignedInt; 6571 PtrDiffType = SignedInt; 6572 IntPtrType = SignedInt; 6573 6574 // {} in inline assembly are packet specifiers, not assembly variant 6575 // specifiers. 6576 NoAsmVariants = true; 6577 6578 LargeArrayMinWidth = 64; 6579 LargeArrayAlign = 64; 6580 UseBitFieldTypeAlignment = true; 6581 ZeroLengthBitfieldBoundary = 32; 6582 HasHVX = HasHVXDouble = false; 6583 UseLongCalls = false; 6584 } 6585 6586 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6587 return llvm::makeArrayRef(BuiltinInfo, 6588 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6589 } 6590 6591 bool validateAsmConstraint(const char *&Name, 6592 TargetInfo::ConstraintInfo &Info) const override { 6593 switch (*Name) { 6594 case 'v': 6595 case 'q': 6596 if (HasHVX) { 6597 Info.setAllowsRegister(); 6598 return true; 6599 } 6600 break; 6601 case 's': 6602 // Relocatable constant. 6603 return true; 6604 } 6605 return false; 6606 } 6607 6608 void getTargetDefines(const LangOptions &Opts, 6609 MacroBuilder &Builder) const override; 6610 6611 bool isCLZForZeroUndef() const override { return false; } 6612 6613 bool hasFeature(StringRef Feature) const override { 6614 return llvm::StringSwitch<bool>(Feature) 6615 .Case("hexagon", true) 6616 .Case("hvx", HasHVX) 6617 .Case("hvx-double", HasHVXDouble) 6618 .Case("long-calls", UseLongCalls) 6619 .Default(false); 6620 } 6621 6622 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6623 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6624 const override; 6625 6626 bool handleTargetFeatures(std::vector<std::string> &Features, 6627 DiagnosticsEngine &Diags) override; 6628 6629 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6630 bool Enabled) const override; 6631 6632 BuiltinVaListKind getBuiltinVaListKind() const override { 6633 return TargetInfo::CharPtrBuiltinVaList; 6634 } 6635 ArrayRef<const char *> getGCCRegNames() const override; 6636 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6637 const char *getClobbers() const override { 6638 return ""; 6639 } 6640 6641 static const char *getHexagonCPUSuffix(StringRef Name) { 6642 return llvm::StringSwitch<const char*>(Name) 6643 .Case("hexagonv4", "4") 6644 .Case("hexagonv5", "5") 6645 .Case("hexagonv55", "55") 6646 .Case("hexagonv60", "60") 6647 .Case("hexagonv62", "62") 6648 .Default(nullptr); 6649 } 6650 6651 bool setCPU(const std::string &Name) override { 6652 if (!getHexagonCPUSuffix(Name)) 6653 return false; 6654 CPU = Name; 6655 return true; 6656 } 6657 6658 int getEHDataRegisterNumber(unsigned RegNo) const override { 6659 return RegNo < 2 ? RegNo : -1; 6660 } 6661 }; 6662 6663 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6664 MacroBuilder &Builder) const { 6665 Builder.defineMacro("__qdsp6__", "1"); 6666 Builder.defineMacro("__hexagon__", "1"); 6667 6668 if (CPU == "hexagonv4") { 6669 Builder.defineMacro("__HEXAGON_V4__"); 6670 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6671 if (Opts.HexagonQdsp6Compat) { 6672 Builder.defineMacro("__QDSP6_V4__"); 6673 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6674 } 6675 } else if (CPU == "hexagonv5") { 6676 Builder.defineMacro("__HEXAGON_V5__"); 6677 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6678 if(Opts.HexagonQdsp6Compat) { 6679 Builder.defineMacro("__QDSP6_V5__"); 6680 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6681 } 6682 } else if (CPU == "hexagonv55") { 6683 Builder.defineMacro("__HEXAGON_V55__"); 6684 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6685 Builder.defineMacro("__QDSP6_V55__"); 6686 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6687 } else if (CPU == "hexagonv60") { 6688 Builder.defineMacro("__HEXAGON_V60__"); 6689 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6690 Builder.defineMacro("__QDSP6_V60__"); 6691 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6692 } else if (CPU == "hexagonv62") { 6693 Builder.defineMacro("__HEXAGON_V62__"); 6694 Builder.defineMacro("__HEXAGON_ARCH__", "62"); 6695 } 6696 6697 if (hasFeature("hvx")) { 6698 Builder.defineMacro("__HVX__"); 6699 if (hasFeature("hvx-double")) 6700 Builder.defineMacro("__HVXDBL__"); 6701 } 6702 } 6703 6704 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6705 DiagnosticsEngine &Diags, StringRef CPU, 6706 const std::vector<std::string> &FeaturesVec) const { 6707 // Default for v60: -hvx, -hvx-double. 6708 Features["hvx"] = false; 6709 Features["hvx-double"] = false; 6710 Features["long-calls"] = false; 6711 6712 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6713 } 6714 6715 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6716 DiagnosticsEngine &Diags) { 6717 for (auto &F : Features) { 6718 if (F == "+hvx") 6719 HasHVX = true; 6720 else if (F == "-hvx") 6721 HasHVX = HasHVXDouble = false; 6722 else if (F == "+hvx-double") 6723 HasHVX = HasHVXDouble = true; 6724 else if (F == "-hvx-double") 6725 HasHVXDouble = false; 6726 6727 if (F == "+long-calls") 6728 UseLongCalls = true; 6729 else if (F == "-long-calls") 6730 UseLongCalls = false; 6731 } 6732 return true; 6733 } 6734 6735 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6736 StringRef Name, bool Enabled) const { 6737 if (Enabled) { 6738 if (Name == "hvx-double") 6739 Features["hvx"] = true; 6740 } else { 6741 if (Name == "hvx") 6742 Features["hvx-double"] = false; 6743 } 6744 Features[Name] = Enabled; 6745 } 6746 6747 const char *const HexagonTargetInfo::GCCRegNames[] = { 6748 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6749 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6750 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6751 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6752 "p0", "p1", "p2", "p3", 6753 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6754 }; 6755 6756 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6757 return llvm::makeArrayRef(GCCRegNames); 6758 } 6759 6760 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6761 { { "sp" }, "r29" }, 6762 { { "fp" }, "r30" }, 6763 { { "lr" }, "r31" }, 6764 }; 6765 6766 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6767 return llvm::makeArrayRef(GCCRegAliases); 6768 } 6769 6770 6771 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6772 #define BUILTIN(ID, TYPE, ATTRS) \ 6773 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6774 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6775 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6776 #include "clang/Basic/BuiltinsHexagon.def" 6777 }; 6778 6779 class LanaiTargetInfo : public TargetInfo { 6780 // Class for Lanai (32-bit). 6781 // The CPU profiles supported by the Lanai backend 6782 enum CPUKind { 6783 CK_NONE, 6784 CK_V11, 6785 } CPU; 6786 6787 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6788 static const char *const GCCRegNames[]; 6789 6790 public: 6791 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6792 : TargetInfo(Triple) { 6793 // Description string has to be kept in sync with backend. 6794 resetDataLayout("E" // Big endian 6795 "-m:e" // ELF name manging 6796 "-p:32:32" // 32 bit pointers, 32 bit aligned 6797 "-i64:64" // 64 bit integers, 64 bit aligned 6798 "-a:0:32" // 32 bit alignment of objects of aggregate type 6799 "-n32" // 32 bit native integer width 6800 "-S64" // 64 bit natural stack alignment 6801 ); 6802 6803 // Setting RegParmMax equal to what mregparm was set to in the old 6804 // toolchain 6805 RegParmMax = 4; 6806 6807 // Set the default CPU to V11 6808 CPU = CK_V11; 6809 6810 // Temporary approach to make everything at least word-aligned and allow for 6811 // safely casting between pointers with different alignment requirements. 6812 // TODO: Remove this when there are no more cast align warnings on the 6813 // firmware. 6814 MinGlobalAlign = 32; 6815 } 6816 6817 void getTargetDefines(const LangOptions &Opts, 6818 MacroBuilder &Builder) const override { 6819 // Define __lanai__ when building for target lanai. 6820 Builder.defineMacro("__lanai__"); 6821 6822 // Set define for the CPU specified. 6823 switch (CPU) { 6824 case CK_V11: 6825 Builder.defineMacro("__LANAI_V11__"); 6826 break; 6827 case CK_NONE: 6828 llvm_unreachable("Unhandled target CPU"); 6829 } 6830 } 6831 6832 bool setCPU(const std::string &Name) override { 6833 CPU = llvm::StringSwitch<CPUKind>(Name) 6834 .Case("v11", CK_V11) 6835 .Default(CK_NONE); 6836 6837 return CPU != CK_NONE; 6838 } 6839 6840 bool hasFeature(StringRef Feature) const override { 6841 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6842 } 6843 6844 ArrayRef<const char *> getGCCRegNames() const override; 6845 6846 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6847 6848 BuiltinVaListKind getBuiltinVaListKind() const override { 6849 return TargetInfo::VoidPtrBuiltinVaList; 6850 } 6851 6852 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6853 6854 bool validateAsmConstraint(const char *&Name, 6855 TargetInfo::ConstraintInfo &info) const override { 6856 return false; 6857 } 6858 6859 const char *getClobbers() const override { return ""; } 6860 }; 6861 6862 const char *const LanaiTargetInfo::GCCRegNames[] = { 6863 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6864 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6865 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6866 6867 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6868 return llvm::makeArrayRef(GCCRegNames); 6869 } 6870 6871 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6872 {{"pc"}, "r2"}, 6873 {{"sp"}, "r4"}, 6874 {{"fp"}, "r5"}, 6875 {{"rv"}, "r8"}, 6876 {{"rr1"}, "r10"}, 6877 {{"rr2"}, "r11"}, 6878 {{"rca"}, "r15"}, 6879 }; 6880 6881 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6882 return llvm::makeArrayRef(GCCRegAliases); 6883 } 6884 6885 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6886 class SparcTargetInfo : public TargetInfo { 6887 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6888 static const char * const GCCRegNames[]; 6889 bool SoftFloat; 6890 public: 6891 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6892 : TargetInfo(Triple), SoftFloat(false) {} 6893 6894 int getEHDataRegisterNumber(unsigned RegNo) const override { 6895 if (RegNo == 0) return 24; 6896 if (RegNo == 1) return 25; 6897 return -1; 6898 } 6899 6900 bool handleTargetFeatures(std::vector<std::string> &Features, 6901 DiagnosticsEngine &Diags) override { 6902 // Check if software floating point is enabled 6903 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6904 if (Feature != Features.end()) { 6905 SoftFloat = true; 6906 } 6907 return true; 6908 } 6909 void getTargetDefines(const LangOptions &Opts, 6910 MacroBuilder &Builder) const override { 6911 DefineStd(Builder, "sparc", Opts); 6912 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6913 6914 if (SoftFloat) 6915 Builder.defineMacro("SOFT_FLOAT", "1"); 6916 } 6917 6918 bool hasFeature(StringRef Feature) const override { 6919 return llvm::StringSwitch<bool>(Feature) 6920 .Case("softfloat", SoftFloat) 6921 .Case("sparc", true) 6922 .Default(false); 6923 } 6924 6925 bool hasSjLjLowering() const override { 6926 return true; 6927 } 6928 6929 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6930 // FIXME: Implement! 6931 return None; 6932 } 6933 BuiltinVaListKind getBuiltinVaListKind() const override { 6934 return TargetInfo::VoidPtrBuiltinVaList; 6935 } 6936 ArrayRef<const char *> getGCCRegNames() const override; 6937 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6938 bool validateAsmConstraint(const char *&Name, 6939 TargetInfo::ConstraintInfo &info) const override { 6940 // FIXME: Implement! 6941 switch (*Name) { 6942 case 'I': // Signed 13-bit constant 6943 case 'J': // Zero 6944 case 'K': // 32-bit constant with the low 12 bits clear 6945 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6946 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6947 case 'N': // Same as 'K' but zext (required for SIMode) 6948 case 'O': // The constant 4096 6949 return true; 6950 6951 case 'f': 6952 case 'e': 6953 info.setAllowsRegister(); 6954 return true; 6955 } 6956 return false; 6957 } 6958 const char *getClobbers() const override { 6959 // FIXME: Implement! 6960 return ""; 6961 } 6962 6963 // No Sparc V7 for now, the backend doesn't support it anyway. 6964 enum CPUKind { 6965 CK_GENERIC, 6966 CK_V8, 6967 CK_SUPERSPARC, 6968 CK_SPARCLITE, 6969 CK_F934, 6970 CK_HYPERSPARC, 6971 CK_SPARCLITE86X, 6972 CK_SPARCLET, 6973 CK_TSC701, 6974 CK_V9, 6975 CK_ULTRASPARC, 6976 CK_ULTRASPARC3, 6977 CK_NIAGARA, 6978 CK_NIAGARA2, 6979 CK_NIAGARA3, 6980 CK_NIAGARA4, 6981 CK_MYRIAD2100, 6982 CK_MYRIAD2150, 6983 CK_MYRIAD2450, 6984 CK_LEON2, 6985 CK_LEON2_AT697E, 6986 CK_LEON2_AT697F, 6987 CK_LEON3, 6988 CK_LEON3_UT699, 6989 CK_LEON3_GR712RC, 6990 CK_LEON4, 6991 CK_LEON4_GR740 6992 } CPU = CK_GENERIC; 6993 6994 enum CPUGeneration { 6995 CG_V8, 6996 CG_V9, 6997 }; 6998 6999 CPUGeneration getCPUGeneration(CPUKind Kind) const { 7000 switch (Kind) { 7001 case CK_GENERIC: 7002 case CK_V8: 7003 case CK_SUPERSPARC: 7004 case CK_SPARCLITE: 7005 case CK_F934: 7006 case CK_HYPERSPARC: 7007 case CK_SPARCLITE86X: 7008 case CK_SPARCLET: 7009 case CK_TSC701: 7010 case CK_MYRIAD2100: 7011 case CK_MYRIAD2150: 7012 case CK_MYRIAD2450: 7013 case CK_LEON2: 7014 case CK_LEON2_AT697E: 7015 case CK_LEON2_AT697F: 7016 case CK_LEON3: 7017 case CK_LEON3_UT699: 7018 case CK_LEON3_GR712RC: 7019 case CK_LEON4: 7020 case CK_LEON4_GR740: 7021 return CG_V8; 7022 case CK_V9: 7023 case CK_ULTRASPARC: 7024 case CK_ULTRASPARC3: 7025 case CK_NIAGARA: 7026 case CK_NIAGARA2: 7027 case CK_NIAGARA3: 7028 case CK_NIAGARA4: 7029 return CG_V9; 7030 } 7031 llvm_unreachable("Unexpected CPU kind"); 7032 } 7033 7034 CPUKind getCPUKind(StringRef Name) const { 7035 return llvm::StringSwitch<CPUKind>(Name) 7036 .Case("v8", CK_V8) 7037 .Case("supersparc", CK_SUPERSPARC) 7038 .Case("sparclite", CK_SPARCLITE) 7039 .Case("f934", CK_F934) 7040 .Case("hypersparc", CK_HYPERSPARC) 7041 .Case("sparclite86x", CK_SPARCLITE86X) 7042 .Case("sparclet", CK_SPARCLET) 7043 .Case("tsc701", CK_TSC701) 7044 .Case("v9", CK_V9) 7045 .Case("ultrasparc", CK_ULTRASPARC) 7046 .Case("ultrasparc3", CK_ULTRASPARC3) 7047 .Case("niagara", CK_NIAGARA) 7048 .Case("niagara2", CK_NIAGARA2) 7049 .Case("niagara3", CK_NIAGARA3) 7050 .Case("niagara4", CK_NIAGARA4) 7051 .Case("ma2100", CK_MYRIAD2100) 7052 .Case("ma2150", CK_MYRIAD2150) 7053 .Case("ma2450", CK_MYRIAD2450) 7054 // FIXME: the myriad2[.n] spellings are obsolete, 7055 // but a grace period is needed to allow updating dependent builds. 7056 .Case("myriad2", CK_MYRIAD2100) 7057 .Case("myriad2.1", CK_MYRIAD2100) 7058 .Case("myriad2.2", CK_MYRIAD2150) 7059 .Case("leon2", CK_LEON2) 7060 .Case("at697e", CK_LEON2_AT697E) 7061 .Case("at697f", CK_LEON2_AT697F) 7062 .Case("leon3", CK_LEON3) 7063 .Case("ut699", CK_LEON3_UT699) 7064 .Case("gr712rc", CK_LEON3_GR712RC) 7065 .Case("leon4", CK_LEON4) 7066 .Case("gr740", CK_LEON4_GR740) 7067 .Default(CK_GENERIC); 7068 } 7069 7070 bool setCPU(const std::string &Name) override { 7071 CPU = getCPUKind(Name); 7072 return CPU != CK_GENERIC; 7073 } 7074 }; 7075 7076 const char * const SparcTargetInfo::GCCRegNames[] = { 7077 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7078 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7079 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 7080 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 7081 }; 7082 7083 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 7084 return llvm::makeArrayRef(GCCRegNames); 7085 } 7086 7087 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 7088 { { "g0" }, "r0" }, 7089 { { "g1" }, "r1" }, 7090 { { "g2" }, "r2" }, 7091 { { "g3" }, "r3" }, 7092 { { "g4" }, "r4" }, 7093 { { "g5" }, "r5" }, 7094 { { "g6" }, "r6" }, 7095 { { "g7" }, "r7" }, 7096 { { "o0" }, "r8" }, 7097 { { "o1" }, "r9" }, 7098 { { "o2" }, "r10" }, 7099 { { "o3" }, "r11" }, 7100 { { "o4" }, "r12" }, 7101 { { "o5" }, "r13" }, 7102 { { "o6", "sp" }, "r14" }, 7103 { { "o7" }, "r15" }, 7104 { { "l0" }, "r16" }, 7105 { { "l1" }, "r17" }, 7106 { { "l2" }, "r18" }, 7107 { { "l3" }, "r19" }, 7108 { { "l4" }, "r20" }, 7109 { { "l5" }, "r21" }, 7110 { { "l6" }, "r22" }, 7111 { { "l7" }, "r23" }, 7112 { { "i0" }, "r24" }, 7113 { { "i1" }, "r25" }, 7114 { { "i2" }, "r26" }, 7115 { { "i3" }, "r27" }, 7116 { { "i4" }, "r28" }, 7117 { { "i5" }, "r29" }, 7118 { { "i6", "fp" }, "r30" }, 7119 { { "i7" }, "r31" }, 7120 }; 7121 7122 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 7123 return llvm::makeArrayRef(GCCRegAliases); 7124 } 7125 7126 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 7127 class SparcV8TargetInfo : public SparcTargetInfo { 7128 public: 7129 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7130 : SparcTargetInfo(Triple, Opts) { 7131 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7132 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 7133 switch (getTriple().getOS()) { 7134 default: 7135 SizeType = UnsignedInt; 7136 IntPtrType = SignedInt; 7137 PtrDiffType = SignedInt; 7138 break; 7139 case llvm::Triple::NetBSD: 7140 case llvm::Triple::OpenBSD: 7141 SizeType = UnsignedLong; 7142 IntPtrType = SignedLong; 7143 PtrDiffType = SignedLong; 7144 break; 7145 } 7146 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 7147 // on up to 64 bits. 7148 MaxAtomicPromoteWidth = 64; 7149 MaxAtomicInlineWidth = 32; 7150 } 7151 7152 void getTargetDefines(const LangOptions &Opts, 7153 MacroBuilder &Builder) const override { 7154 SparcTargetInfo::getTargetDefines(Opts, Builder); 7155 switch (getCPUGeneration(CPU)) { 7156 case CG_V8: 7157 Builder.defineMacro("__sparcv8"); 7158 if (getTriple().getOS() != llvm::Triple::Solaris) 7159 Builder.defineMacro("__sparcv8__"); 7160 break; 7161 case CG_V9: 7162 Builder.defineMacro("__sparcv9"); 7163 if (getTriple().getOS() != llvm::Triple::Solaris) { 7164 Builder.defineMacro("__sparcv9__"); 7165 Builder.defineMacro("__sparc_v9__"); 7166 } 7167 break; 7168 } 7169 if (getTriple().getVendor() == llvm::Triple::Myriad) { 7170 std::string MyriadArchValue, Myriad2Value; 7171 Builder.defineMacro("__sparc_v8__"); 7172 Builder.defineMacro("__leon__"); 7173 switch (CPU) { 7174 case CK_MYRIAD2150: 7175 MyriadArchValue = "__ma2150"; 7176 Myriad2Value = "2"; 7177 break; 7178 case CK_MYRIAD2450: 7179 MyriadArchValue = "__ma2450"; 7180 Myriad2Value = "2"; 7181 break; 7182 default: 7183 MyriadArchValue = "__ma2100"; 7184 Myriad2Value = "1"; 7185 break; 7186 } 7187 Builder.defineMacro(MyriadArchValue, "1"); 7188 Builder.defineMacro(MyriadArchValue+"__", "1"); 7189 Builder.defineMacro("__myriad2__", Myriad2Value); 7190 Builder.defineMacro("__myriad2", Myriad2Value); 7191 } 7192 } 7193 7194 bool hasSjLjLowering() const override { 7195 return true; 7196 } 7197 }; 7198 7199 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 7200 class SparcV8elTargetInfo : public SparcV8TargetInfo { 7201 public: 7202 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7203 : SparcV8TargetInfo(Triple, Opts) { 7204 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7205 } 7206 }; 7207 7208 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 7209 class SparcV9TargetInfo : public SparcTargetInfo { 7210 public: 7211 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7212 : SparcTargetInfo(Triple, Opts) { 7213 // FIXME: Support Sparc quad-precision long double? 7214 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 7215 // This is an LP64 platform. 7216 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7217 7218 // OpenBSD uses long long for int64_t and intmax_t. 7219 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7220 IntMaxType = SignedLongLong; 7221 else 7222 IntMaxType = SignedLong; 7223 Int64Type = IntMaxType; 7224 7225 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7226 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7227 LongDoubleWidth = 128; 7228 LongDoubleAlign = 128; 7229 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7230 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7231 } 7232 7233 void getTargetDefines(const LangOptions &Opts, 7234 MacroBuilder &Builder) const override { 7235 SparcTargetInfo::getTargetDefines(Opts, Builder); 7236 Builder.defineMacro("__sparcv9"); 7237 Builder.defineMacro("__arch64__"); 7238 // Solaris doesn't need these variants, but the BSDs do. 7239 if (getTriple().getOS() != llvm::Triple::Solaris) { 7240 Builder.defineMacro("__sparc64__"); 7241 Builder.defineMacro("__sparc_v9__"); 7242 Builder.defineMacro("__sparcv9__"); 7243 } 7244 } 7245 7246 bool setCPU(const std::string &Name) override { 7247 if (!SparcTargetInfo::setCPU(Name)) 7248 return false; 7249 return getCPUGeneration(CPU) == CG_V9; 7250 } 7251 }; 7252 7253 class SystemZTargetInfo : public TargetInfo { 7254 static const Builtin::Info BuiltinInfo[]; 7255 static const char *const GCCRegNames[]; 7256 std::string CPU; 7257 bool HasTransactionalExecution; 7258 bool HasVector; 7259 7260 public: 7261 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7262 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 7263 HasVector(false) { 7264 IntMaxType = SignedLong; 7265 Int64Type = SignedLong; 7266 TLSSupported = true; 7267 IntWidth = IntAlign = 32; 7268 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7269 PointerWidth = PointerAlign = 64; 7270 LongDoubleWidth = 128; 7271 LongDoubleAlign = 64; 7272 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7273 DefaultAlignForAttributeAligned = 64; 7274 MinGlobalAlign = 16; 7275 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7276 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7277 } 7278 void getTargetDefines(const LangOptions &Opts, 7279 MacroBuilder &Builder) const override { 7280 Builder.defineMacro("__s390__"); 7281 Builder.defineMacro("__s390x__"); 7282 Builder.defineMacro("__zarch__"); 7283 Builder.defineMacro("__LONG_DOUBLE_128__"); 7284 7285 const std::string ISARev = llvm::StringSwitch<std::string>(CPU) 7286 .Cases("arch8", "z10", "8") 7287 .Cases("arch9", "z196", "9") 7288 .Cases("arch10", "zEC12", "10") 7289 .Cases("arch11", "z13", "11") 7290 .Default(""); 7291 if (!ISARev.empty()) 7292 Builder.defineMacro("__ARCH__", ISARev); 7293 7294 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7295 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7296 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7297 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7298 7299 if (HasTransactionalExecution) 7300 Builder.defineMacro("__HTM__"); 7301 if (HasVector) 7302 Builder.defineMacro("__VX__"); 7303 if (Opts.ZVector) 7304 Builder.defineMacro("__VEC__", "10301"); 7305 } 7306 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7307 return llvm::makeArrayRef(BuiltinInfo, 7308 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7309 } 7310 7311 ArrayRef<const char *> getGCCRegNames() const override; 7312 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7313 // No aliases. 7314 return None; 7315 } 7316 bool validateAsmConstraint(const char *&Name, 7317 TargetInfo::ConstraintInfo &info) const override; 7318 const char *getClobbers() const override { 7319 // FIXME: Is this really right? 7320 return ""; 7321 } 7322 BuiltinVaListKind getBuiltinVaListKind() const override { 7323 return TargetInfo::SystemZBuiltinVaList; 7324 } 7325 bool setCPU(const std::string &Name) override { 7326 CPU = Name; 7327 bool CPUKnown = llvm::StringSwitch<bool>(Name) 7328 .Case("z10", true) 7329 .Case("arch8", true) 7330 .Case("z196", true) 7331 .Case("arch9", true) 7332 .Case("zEC12", true) 7333 .Case("arch10", true) 7334 .Case("z13", true) 7335 .Case("arch11", true) 7336 .Default(false); 7337 7338 return CPUKnown; 7339 } 7340 bool 7341 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7342 StringRef CPU, 7343 const std::vector<std::string> &FeaturesVec) const override { 7344 if (CPU == "zEC12" || CPU == "arch10") 7345 Features["transactional-execution"] = true; 7346 if (CPU == "z13" || CPU == "arch11") { 7347 Features["transactional-execution"] = true; 7348 Features["vector"] = true; 7349 } 7350 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7351 } 7352 7353 bool handleTargetFeatures(std::vector<std::string> &Features, 7354 DiagnosticsEngine &Diags) override { 7355 HasTransactionalExecution = false; 7356 for (const auto &Feature : Features) { 7357 if (Feature == "+transactional-execution") 7358 HasTransactionalExecution = true; 7359 else if (Feature == "+vector") 7360 HasVector = true; 7361 } 7362 // If we use the vector ABI, vector types are 64-bit aligned. 7363 if (HasVector) { 7364 MaxVectorAlign = 64; 7365 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7366 "-v128:64-a:8:16-n32:64"); 7367 } 7368 return true; 7369 } 7370 7371 bool hasFeature(StringRef Feature) const override { 7372 return llvm::StringSwitch<bool>(Feature) 7373 .Case("systemz", true) 7374 .Case("htm", HasTransactionalExecution) 7375 .Case("vx", HasVector) 7376 .Default(false); 7377 } 7378 7379 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7380 switch (CC) { 7381 case CC_C: 7382 case CC_Swift: 7383 return CCCR_OK; 7384 default: 7385 return CCCR_Warning; 7386 } 7387 } 7388 7389 StringRef getABI() const override { 7390 if (HasVector) 7391 return "vector"; 7392 return ""; 7393 } 7394 7395 bool useFloat128ManglingForLongDouble() const override { 7396 return true; 7397 } 7398 }; 7399 7400 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7401 #define BUILTIN(ID, TYPE, ATTRS) \ 7402 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7403 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7404 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7405 #include "clang/Basic/BuiltinsSystemZ.def" 7406 }; 7407 7408 const char *const SystemZTargetInfo::GCCRegNames[] = { 7409 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7410 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7411 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7412 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7413 }; 7414 7415 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7416 return llvm::makeArrayRef(GCCRegNames); 7417 } 7418 7419 bool SystemZTargetInfo:: 7420 validateAsmConstraint(const char *&Name, 7421 TargetInfo::ConstraintInfo &Info) const { 7422 switch (*Name) { 7423 default: 7424 return false; 7425 7426 case 'a': // Address register 7427 case 'd': // Data register (equivalent to 'r') 7428 case 'f': // Floating-point register 7429 Info.setAllowsRegister(); 7430 return true; 7431 7432 case 'I': // Unsigned 8-bit constant 7433 case 'J': // Unsigned 12-bit constant 7434 case 'K': // Signed 16-bit constant 7435 case 'L': // Signed 20-bit displacement (on all targets we support) 7436 case 'M': // 0x7fffffff 7437 return true; 7438 7439 case 'Q': // Memory with base and unsigned 12-bit displacement 7440 case 'R': // Likewise, plus an index 7441 case 'S': // Memory with base and signed 20-bit displacement 7442 case 'T': // Likewise, plus an index 7443 Info.setAllowsMemory(); 7444 return true; 7445 } 7446 } 7447 7448 class MSP430TargetInfo : public TargetInfo { 7449 static const char *const GCCRegNames[]; 7450 7451 public: 7452 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7453 : TargetInfo(Triple) { 7454 TLSSupported = false; 7455 IntWidth = 16; 7456 IntAlign = 16; 7457 LongWidth = 32; 7458 LongLongWidth = 64; 7459 LongAlign = LongLongAlign = 16; 7460 PointerWidth = 16; 7461 PointerAlign = 16; 7462 SuitableAlign = 16; 7463 SizeType = UnsignedInt; 7464 IntMaxType = SignedLongLong; 7465 IntPtrType = SignedInt; 7466 PtrDiffType = SignedInt; 7467 SigAtomicType = SignedLong; 7468 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7469 } 7470 void getTargetDefines(const LangOptions &Opts, 7471 MacroBuilder &Builder) const override { 7472 Builder.defineMacro("MSP430"); 7473 Builder.defineMacro("__MSP430__"); 7474 // FIXME: defines for different 'flavours' of MCU 7475 } 7476 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7477 // FIXME: Implement. 7478 return None; 7479 } 7480 bool hasFeature(StringRef Feature) const override { 7481 return Feature == "msp430"; 7482 } 7483 ArrayRef<const char *> getGCCRegNames() const override; 7484 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7485 // No aliases. 7486 return None; 7487 } 7488 bool validateAsmConstraint(const char *&Name, 7489 TargetInfo::ConstraintInfo &info) const override { 7490 // FIXME: implement 7491 switch (*Name) { 7492 case 'K': // the constant 1 7493 case 'L': // constant -1^20 .. 1^19 7494 case 'M': // constant 1-4: 7495 return true; 7496 } 7497 // No target constraints for now. 7498 return false; 7499 } 7500 const char *getClobbers() const override { 7501 // FIXME: Is this really right? 7502 return ""; 7503 } 7504 BuiltinVaListKind getBuiltinVaListKind() const override { 7505 // FIXME: implement 7506 return TargetInfo::CharPtrBuiltinVaList; 7507 } 7508 }; 7509 7510 const char *const MSP430TargetInfo::GCCRegNames[] = { 7511 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7512 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7513 7514 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7515 return llvm::makeArrayRef(GCCRegNames); 7516 } 7517 7518 // LLVM and Clang cannot be used directly to output native binaries for 7519 // target, but is used to compile C code to llvm bitcode with correct 7520 // type and alignment information. 7521 // 7522 // TCE uses the llvm bitcode as input and uses it for generating customized 7523 // target processor and program binary. TCE co-design environment is 7524 // publicly available in http://tce.cs.tut.fi 7525 7526 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7527 0, // Default 7528 3, // opencl_global 7529 4, // opencl_local 7530 5, // opencl_constant 7531 // FIXME: generic has to be added to the target 7532 0, // opencl_generic 7533 0, // cuda_device 7534 0, // cuda_constant 7535 0 // cuda_shared 7536 }; 7537 7538 class TCETargetInfo : public TargetInfo { 7539 public: 7540 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7541 : TargetInfo(Triple) { 7542 TLSSupported = false; 7543 IntWidth = 32; 7544 LongWidth = LongLongWidth = 32; 7545 PointerWidth = 32; 7546 IntAlign = 32; 7547 LongAlign = LongLongAlign = 32; 7548 PointerAlign = 32; 7549 SuitableAlign = 32; 7550 SizeType = UnsignedInt; 7551 IntMaxType = SignedLong; 7552 IntPtrType = SignedInt; 7553 PtrDiffType = SignedInt; 7554 FloatWidth = 32; 7555 FloatAlign = 32; 7556 DoubleWidth = 32; 7557 DoubleAlign = 32; 7558 LongDoubleWidth = 32; 7559 LongDoubleAlign = 32; 7560 FloatFormat = &llvm::APFloat::IEEEsingle(); 7561 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7562 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7563 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7564 "i16:16:32-i32:32:32-i64:32:32-" 7565 "f32:32:32-f64:32:32-v64:32:32-" 7566 "v128:32:32-v256:32:32-v512:32:32-" 7567 "v1024:32:32-a0:0:32-n32"); 7568 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7569 UseAddrSpaceMapMangling = true; 7570 } 7571 7572 void getTargetDefines(const LangOptions &Opts, 7573 MacroBuilder &Builder) const override { 7574 DefineStd(Builder, "tce", Opts); 7575 Builder.defineMacro("__TCE__"); 7576 Builder.defineMacro("__TCE_V1__"); 7577 } 7578 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7579 7580 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7581 const char *getClobbers() const override { return ""; } 7582 BuiltinVaListKind getBuiltinVaListKind() const override { 7583 return TargetInfo::VoidPtrBuiltinVaList; 7584 } 7585 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7586 bool validateAsmConstraint(const char *&Name, 7587 TargetInfo::ConstraintInfo &info) const override { 7588 return true; 7589 } 7590 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7591 return None; 7592 } 7593 }; 7594 7595 class TCELETargetInfo : public TCETargetInfo { 7596 public: 7597 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7598 : TCETargetInfo(Triple, Opts) { 7599 BigEndian = false; 7600 7601 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7602 "i16:16:32-i32:32:32-i64:32:32-" 7603 "f32:32:32-f64:32:32-v64:32:32-" 7604 "v128:32:32-v256:32:32-v512:32:32-" 7605 "v1024:32:32-a0:0:32-n32"); 7606 7607 } 7608 7609 virtual void getTargetDefines(const LangOptions &Opts, 7610 MacroBuilder &Builder) const { 7611 DefineStd(Builder, "tcele", Opts); 7612 Builder.defineMacro("__TCE__"); 7613 Builder.defineMacro("__TCE_V1__"); 7614 Builder.defineMacro("__TCELE__"); 7615 Builder.defineMacro("__TCELE_V1__"); 7616 } 7617 7618 }; 7619 7620 class BPFTargetInfo : public TargetInfo { 7621 public: 7622 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7623 : TargetInfo(Triple) { 7624 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7625 SizeType = UnsignedLong; 7626 PtrDiffType = SignedLong; 7627 IntPtrType = SignedLong; 7628 IntMaxType = SignedLong; 7629 Int64Type = SignedLong; 7630 RegParmMax = 5; 7631 if (Triple.getArch() == llvm::Triple::bpfeb) { 7632 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7633 } else { 7634 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7635 } 7636 MaxAtomicPromoteWidth = 64; 7637 MaxAtomicInlineWidth = 64; 7638 TLSSupported = false; 7639 } 7640 void getTargetDefines(const LangOptions &Opts, 7641 MacroBuilder &Builder) const override { 7642 DefineStd(Builder, "bpf", Opts); 7643 Builder.defineMacro("__BPF__"); 7644 } 7645 bool hasFeature(StringRef Feature) const override { 7646 return Feature == "bpf"; 7647 } 7648 7649 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7650 const char *getClobbers() const override { 7651 return ""; 7652 } 7653 BuiltinVaListKind getBuiltinVaListKind() const override { 7654 return TargetInfo::VoidPtrBuiltinVaList; 7655 } 7656 ArrayRef<const char *> getGCCRegNames() const override { 7657 return None; 7658 } 7659 bool validateAsmConstraint(const char *&Name, 7660 TargetInfo::ConstraintInfo &info) const override { 7661 return true; 7662 } 7663 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7664 return None; 7665 } 7666 }; 7667 7668 class MipsTargetInfo : public TargetInfo { 7669 void setDataLayout() { 7670 StringRef Layout; 7671 7672 if (ABI == "o32") 7673 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7674 else if (ABI == "n32") 7675 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7676 else if (ABI == "n64") 7677 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7678 else 7679 llvm_unreachable("Invalid ABI"); 7680 7681 if (BigEndian) 7682 resetDataLayout(("E-" + Layout).str()); 7683 else 7684 resetDataLayout(("e-" + Layout).str()); 7685 } 7686 7687 7688 static const Builtin::Info BuiltinInfo[]; 7689 std::string CPU; 7690 bool IsMips16; 7691 bool IsMicromips; 7692 bool IsNan2008; 7693 bool IsSingleFloat; 7694 bool IsNoABICalls; 7695 bool CanUseBSDABICalls; 7696 enum MipsFloatABI { 7697 HardFloat, SoftFloat 7698 } FloatABI; 7699 enum DspRevEnum { 7700 NoDSP, DSP1, DSP2 7701 } DspRev; 7702 bool HasMSA; 7703 7704 protected: 7705 bool HasFP64; 7706 std::string ABI; 7707 7708 public: 7709 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7710 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7711 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 7712 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 7713 HasMSA(false), HasFP64(false) { 7714 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7715 7716 setABI((getTriple().getArch() == llvm::Triple::mips || 7717 getTriple().getArch() == llvm::Triple::mipsel) 7718 ? "o32" 7719 : "n64"); 7720 7721 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7722 7723 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 7724 Triple.getOS() == llvm::Triple::OpenBSD; 7725 } 7726 7727 bool isNaN2008Default() const { 7728 return CPU == "mips32r6" || CPU == "mips64r6"; 7729 } 7730 7731 bool isFP64Default() const { 7732 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7733 } 7734 7735 bool isNan2008() const override { 7736 return IsNan2008; 7737 } 7738 7739 bool processorSupportsGPR64() const { 7740 return llvm::StringSwitch<bool>(CPU) 7741 .Case("mips3", true) 7742 .Case("mips4", true) 7743 .Case("mips5", true) 7744 .Case("mips64", true) 7745 .Case("mips64r2", true) 7746 .Case("mips64r3", true) 7747 .Case("mips64r5", true) 7748 .Case("mips64r6", true) 7749 .Case("octeon", true) 7750 .Default(false); 7751 return false; 7752 } 7753 7754 StringRef getABI() const override { return ABI; } 7755 bool setABI(const std::string &Name) override { 7756 if (Name == "o32") { 7757 setO32ABITypes(); 7758 ABI = Name; 7759 return true; 7760 } 7761 7762 if (Name == "n32") { 7763 setN32ABITypes(); 7764 ABI = Name; 7765 return true; 7766 } 7767 if (Name == "n64") { 7768 setN64ABITypes(); 7769 ABI = Name; 7770 return true; 7771 } 7772 return false; 7773 } 7774 7775 void setO32ABITypes() { 7776 Int64Type = SignedLongLong; 7777 IntMaxType = Int64Type; 7778 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7779 LongDoubleWidth = LongDoubleAlign = 64; 7780 LongWidth = LongAlign = 32; 7781 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7782 PointerWidth = PointerAlign = 32; 7783 PtrDiffType = SignedInt; 7784 SizeType = UnsignedInt; 7785 SuitableAlign = 64; 7786 } 7787 7788 void setN32N64ABITypes() { 7789 LongDoubleWidth = LongDoubleAlign = 128; 7790 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7791 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7792 LongDoubleWidth = LongDoubleAlign = 64; 7793 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7794 } 7795 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7796 SuitableAlign = 128; 7797 } 7798 7799 void setN64ABITypes() { 7800 setN32N64ABITypes(); 7801 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 7802 Int64Type = SignedLongLong; 7803 } else { 7804 Int64Type = SignedLong; 7805 } 7806 IntMaxType = Int64Type; 7807 LongWidth = LongAlign = 64; 7808 PointerWidth = PointerAlign = 64; 7809 PtrDiffType = SignedLong; 7810 SizeType = UnsignedLong; 7811 } 7812 7813 void setN32ABITypes() { 7814 setN32N64ABITypes(); 7815 Int64Type = SignedLongLong; 7816 IntMaxType = Int64Type; 7817 LongWidth = LongAlign = 32; 7818 PointerWidth = PointerAlign = 32; 7819 PtrDiffType = SignedInt; 7820 SizeType = UnsignedInt; 7821 } 7822 7823 bool setCPU(const std::string &Name) override { 7824 CPU = Name; 7825 return llvm::StringSwitch<bool>(Name) 7826 .Case("mips1", true) 7827 .Case("mips2", true) 7828 .Case("mips3", true) 7829 .Case("mips4", true) 7830 .Case("mips5", true) 7831 .Case("mips32", true) 7832 .Case("mips32r2", true) 7833 .Case("mips32r3", true) 7834 .Case("mips32r5", true) 7835 .Case("mips32r6", true) 7836 .Case("mips64", true) 7837 .Case("mips64r2", true) 7838 .Case("mips64r3", true) 7839 .Case("mips64r5", true) 7840 .Case("mips64r6", true) 7841 .Case("octeon", true) 7842 .Case("p5600", true) 7843 .Default(false); 7844 } 7845 const std::string& getCPU() const { return CPU; } 7846 bool 7847 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7848 StringRef CPU, 7849 const std::vector<std::string> &FeaturesVec) const override { 7850 if (CPU.empty()) 7851 CPU = getCPU(); 7852 if (CPU == "octeon") 7853 Features["mips64r2"] = Features["cnmips"] = true; 7854 else 7855 Features[CPU] = true; 7856 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7857 } 7858 7859 void getTargetDefines(const LangOptions &Opts, 7860 MacroBuilder &Builder) const override { 7861 if (BigEndian) { 7862 DefineStd(Builder, "MIPSEB", Opts); 7863 Builder.defineMacro("_MIPSEB"); 7864 } else { 7865 DefineStd(Builder, "MIPSEL", Opts); 7866 Builder.defineMacro("_MIPSEL"); 7867 } 7868 7869 Builder.defineMacro("__mips__"); 7870 Builder.defineMacro("_mips"); 7871 if (Opts.GNUMode) 7872 Builder.defineMacro("mips"); 7873 7874 if (ABI == "o32") { 7875 Builder.defineMacro("__mips", "32"); 7876 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7877 } else { 7878 Builder.defineMacro("__mips", "64"); 7879 Builder.defineMacro("__mips64"); 7880 Builder.defineMacro("__mips64__"); 7881 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7882 } 7883 7884 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7885 .Cases("mips32", "mips64", "1") 7886 .Cases("mips32r2", "mips64r2", "2") 7887 .Cases("mips32r3", "mips64r3", "3") 7888 .Cases("mips32r5", "mips64r5", "5") 7889 .Cases("mips32r6", "mips64r6", "6") 7890 .Default(""); 7891 if (!ISARev.empty()) 7892 Builder.defineMacro("__mips_isa_rev", ISARev); 7893 7894 if (ABI == "o32") { 7895 Builder.defineMacro("__mips_o32"); 7896 Builder.defineMacro("_ABIO32", "1"); 7897 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7898 } else if (ABI == "n32") { 7899 Builder.defineMacro("__mips_n32"); 7900 Builder.defineMacro("_ABIN32", "2"); 7901 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7902 } else if (ABI == "n64") { 7903 Builder.defineMacro("__mips_n64"); 7904 Builder.defineMacro("_ABI64", "3"); 7905 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7906 } else 7907 llvm_unreachable("Invalid ABI."); 7908 7909 if (!IsNoABICalls) { 7910 Builder.defineMacro("__mips_abicalls"); 7911 if (CanUseBSDABICalls) 7912 Builder.defineMacro("__ABICALLS__"); 7913 } 7914 7915 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7916 7917 switch (FloatABI) { 7918 case HardFloat: 7919 Builder.defineMacro("__mips_hard_float", Twine(1)); 7920 break; 7921 case SoftFloat: 7922 Builder.defineMacro("__mips_soft_float", Twine(1)); 7923 break; 7924 } 7925 7926 if (IsSingleFloat) 7927 Builder.defineMacro("__mips_single_float", Twine(1)); 7928 7929 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7930 Builder.defineMacro("_MIPS_FPSET", 7931 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7932 7933 if (IsMips16) 7934 Builder.defineMacro("__mips16", Twine(1)); 7935 7936 if (IsMicromips) 7937 Builder.defineMacro("__mips_micromips", Twine(1)); 7938 7939 if (IsNan2008) 7940 Builder.defineMacro("__mips_nan2008", Twine(1)); 7941 7942 switch (DspRev) { 7943 default: 7944 break; 7945 case DSP1: 7946 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7947 Builder.defineMacro("__mips_dsp", Twine(1)); 7948 break; 7949 case DSP2: 7950 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7951 Builder.defineMacro("__mips_dspr2", Twine(1)); 7952 Builder.defineMacro("__mips_dsp", Twine(1)); 7953 break; 7954 } 7955 7956 if (HasMSA) 7957 Builder.defineMacro("__mips_msa", Twine(1)); 7958 7959 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7960 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7961 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7962 7963 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7964 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7965 7966 // These shouldn't be defined for MIPS-I but there's no need to check 7967 // for that since MIPS-I isn't supported. 7968 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7969 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7970 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7971 7972 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7973 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7974 // the instructions exist but using them violates the ABI since they 7975 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7976 if (ABI == "n32" || ABI == "n64") 7977 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7978 } 7979 7980 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7981 return llvm::makeArrayRef(BuiltinInfo, 7982 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7983 } 7984 bool hasFeature(StringRef Feature) const override { 7985 return llvm::StringSwitch<bool>(Feature) 7986 .Case("mips", true) 7987 .Case("fp64", HasFP64) 7988 .Default(false); 7989 } 7990 BuiltinVaListKind getBuiltinVaListKind() const override { 7991 return TargetInfo::VoidPtrBuiltinVaList; 7992 } 7993 ArrayRef<const char *> getGCCRegNames() const override { 7994 static const char *const GCCRegNames[] = { 7995 // CPU register names 7996 // Must match second column of GCCRegAliases 7997 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7998 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7999 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 8000 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 8001 // Floating point register names 8002 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 8003 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 8004 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 8005 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 8006 // Hi/lo and condition register names 8007 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 8008 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 8009 "$ac3hi","$ac3lo", 8010 // MSA register names 8011 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 8012 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 8013 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 8014 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 8015 // MSA control register names 8016 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 8017 "$msarequest", "$msamap", "$msaunmap" 8018 }; 8019 return llvm::makeArrayRef(GCCRegNames); 8020 } 8021 bool validateAsmConstraint(const char *&Name, 8022 TargetInfo::ConstraintInfo &Info) const override { 8023 switch (*Name) { 8024 default: 8025 return false; 8026 case 'r': // CPU registers. 8027 case 'd': // Equivalent to "r" unless generating MIPS16 code. 8028 case 'y': // Equivalent to "r", backward compatibility only. 8029 case 'f': // floating-point registers. 8030 case 'c': // $25 for indirect jumps 8031 case 'l': // lo register 8032 case 'x': // hilo register pair 8033 Info.setAllowsRegister(); 8034 return true; 8035 case 'I': // Signed 16-bit constant 8036 case 'J': // Integer 0 8037 case 'K': // Unsigned 16-bit constant 8038 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 8039 case 'M': // Constants not loadable via lui, addiu, or ori 8040 case 'N': // Constant -1 to -65535 8041 case 'O': // A signed 15-bit constant 8042 case 'P': // A constant between 1 go 65535 8043 return true; 8044 case 'R': // An address that can be used in a non-macro load or store 8045 Info.setAllowsMemory(); 8046 return true; 8047 case 'Z': 8048 if (Name[1] == 'C') { // An address usable by ll, and sc. 8049 Info.setAllowsMemory(); 8050 Name++; // Skip over 'Z'. 8051 return true; 8052 } 8053 return false; 8054 } 8055 } 8056 8057 std::string convertConstraint(const char *&Constraint) const override { 8058 std::string R; 8059 switch (*Constraint) { 8060 case 'Z': // Two-character constraint; add "^" hint for later parsing. 8061 if (Constraint[1] == 'C') { 8062 R = std::string("^") + std::string(Constraint, 2); 8063 Constraint++; 8064 return R; 8065 } 8066 break; 8067 } 8068 return TargetInfo::convertConstraint(Constraint); 8069 } 8070 8071 const char *getClobbers() const override { 8072 // In GCC, $1 is not widely used in generated code (it's used only in a few 8073 // specific situations), so there is no real need for users to add it to 8074 // the clobbers list if they want to use it in their inline assembly code. 8075 // 8076 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 8077 // code generation, so using it in inline assembly without adding it to the 8078 // clobbers list can cause conflicts between the inline assembly code and 8079 // the surrounding generated code. 8080 // 8081 // Another problem is that LLVM is allowed to choose $1 for inline assembly 8082 // operands, which will conflict with the ".set at" assembler option (which 8083 // we use only for inline assembly, in order to maintain compatibility with 8084 // GCC) and will also conflict with the user's usage of $1. 8085 // 8086 // The easiest way to avoid these conflicts and keep $1 as an allocatable 8087 // register for generated code is to automatically clobber $1 for all inline 8088 // assembly code. 8089 // 8090 // FIXME: We should automatically clobber $1 only for inline assembly code 8091 // which actually uses it. This would allow LLVM to use $1 for inline 8092 // assembly operands if the user's assembly code doesn't use it. 8093 return "~{$1}"; 8094 } 8095 8096 bool handleTargetFeatures(std::vector<std::string> &Features, 8097 DiagnosticsEngine &Diags) override { 8098 IsMips16 = false; 8099 IsMicromips = false; 8100 IsNan2008 = isNaN2008Default(); 8101 IsSingleFloat = false; 8102 FloatABI = HardFloat; 8103 DspRev = NoDSP; 8104 HasFP64 = isFP64Default(); 8105 8106 for (const auto &Feature : Features) { 8107 if (Feature == "+single-float") 8108 IsSingleFloat = true; 8109 else if (Feature == "+soft-float") 8110 FloatABI = SoftFloat; 8111 else if (Feature == "+mips16") 8112 IsMips16 = true; 8113 else if (Feature == "+micromips") 8114 IsMicromips = true; 8115 else if (Feature == "+dsp") 8116 DspRev = std::max(DspRev, DSP1); 8117 else if (Feature == "+dspr2") 8118 DspRev = std::max(DspRev, DSP2); 8119 else if (Feature == "+msa") 8120 HasMSA = true; 8121 else if (Feature == "+fp64") 8122 HasFP64 = true; 8123 else if (Feature == "-fp64") 8124 HasFP64 = false; 8125 else if (Feature == "+nan2008") 8126 IsNan2008 = true; 8127 else if (Feature == "-nan2008") 8128 IsNan2008 = false; 8129 else if (Feature == "+noabicalls") 8130 IsNoABICalls = true; 8131 } 8132 8133 setDataLayout(); 8134 8135 return true; 8136 } 8137 8138 int getEHDataRegisterNumber(unsigned RegNo) const override { 8139 if (RegNo == 0) return 4; 8140 if (RegNo == 1) return 5; 8141 return -1; 8142 } 8143 8144 bool isCLZForZeroUndef() const override { return false; } 8145 8146 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8147 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 8148 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8149 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8150 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 8151 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 8152 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 8153 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8154 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8155 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8156 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8157 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8158 {{"ra"}, "$31"}}; 8159 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 8160 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8161 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8162 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 8163 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 8164 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 8165 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8166 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8167 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8168 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8169 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8170 {{"ra"}, "$31"}}; 8171 if (ABI == "o32") 8172 return llvm::makeArrayRef(O32RegAliases); 8173 return llvm::makeArrayRef(NewABIRegAliases); 8174 } 8175 8176 bool hasInt128Type() const override { 8177 return ABI == "n32" || ABI == "n64"; 8178 } 8179 8180 bool validateTarget(DiagnosticsEngine &Diags) const override { 8181 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 8182 // this yet. It's better to fail here than on the backend assertion. 8183 if (processorSupportsGPR64() && ABI == "o32") { 8184 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8185 return false; 8186 } 8187 8188 // 64-bit ABI's require 64-bit CPU's. 8189 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 8190 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8191 return false; 8192 } 8193 8194 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 8195 // can't handle this yet. It's better to fail here than on the 8196 // backend assertion. 8197 if ((getTriple().getArch() == llvm::Triple::mips64 || 8198 getTriple().getArch() == llvm::Triple::mips64el) && 8199 ABI == "o32") { 8200 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8201 << ABI << getTriple().str(); 8202 return false; 8203 } 8204 8205 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 8206 // can't handle this yet. It's better to fail here than on the 8207 // backend assertion. 8208 if ((getTriple().getArch() == llvm::Triple::mips || 8209 getTriple().getArch() == llvm::Triple::mipsel) && 8210 (ABI == "n32" || ABI == "n64")) { 8211 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8212 << ABI << getTriple().str(); 8213 return false; 8214 } 8215 8216 return true; 8217 } 8218 }; 8219 8220 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 8221 #define BUILTIN(ID, TYPE, ATTRS) \ 8222 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8223 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8224 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8225 #include "clang/Basic/BuiltinsMips.def" 8226 }; 8227 8228 class PNaClTargetInfo : public TargetInfo { 8229 public: 8230 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8231 : TargetInfo(Triple) { 8232 this->LongAlign = 32; 8233 this->LongWidth = 32; 8234 this->PointerAlign = 32; 8235 this->PointerWidth = 32; 8236 this->IntMaxType = TargetInfo::SignedLongLong; 8237 this->Int64Type = TargetInfo::SignedLongLong; 8238 this->DoubleAlign = 64; 8239 this->LongDoubleWidth = 64; 8240 this->LongDoubleAlign = 64; 8241 this->SizeType = TargetInfo::UnsignedInt; 8242 this->PtrDiffType = TargetInfo::SignedInt; 8243 this->IntPtrType = TargetInfo::SignedInt; 8244 this->RegParmMax = 0; // Disallow regparm 8245 } 8246 8247 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8248 Builder.defineMacro("__le32__"); 8249 Builder.defineMacro("__pnacl__"); 8250 } 8251 void getTargetDefines(const LangOptions &Opts, 8252 MacroBuilder &Builder) const override { 8253 getArchDefines(Opts, Builder); 8254 } 8255 bool hasFeature(StringRef Feature) const override { 8256 return Feature == "pnacl"; 8257 } 8258 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8259 BuiltinVaListKind getBuiltinVaListKind() const override { 8260 return TargetInfo::PNaClABIBuiltinVaList; 8261 } 8262 ArrayRef<const char *> getGCCRegNames() const override; 8263 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8264 bool validateAsmConstraint(const char *&Name, 8265 TargetInfo::ConstraintInfo &Info) const override { 8266 return false; 8267 } 8268 8269 const char *getClobbers() const override { 8270 return ""; 8271 } 8272 }; 8273 8274 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8275 return None; 8276 } 8277 8278 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8279 return None; 8280 } 8281 8282 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8283 class NaClMips32TargetInfo : public MipsTargetInfo { 8284 public: 8285 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8286 : MipsTargetInfo(Triple, Opts) {} 8287 8288 BuiltinVaListKind getBuiltinVaListKind() const override { 8289 return TargetInfo::PNaClABIBuiltinVaList; 8290 } 8291 }; 8292 8293 class Le64TargetInfo : public TargetInfo { 8294 static const Builtin::Info BuiltinInfo[]; 8295 8296 public: 8297 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8298 : TargetInfo(Triple) { 8299 NoAsmVariants = true; 8300 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8301 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8302 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8303 } 8304 8305 void getTargetDefines(const LangOptions &Opts, 8306 MacroBuilder &Builder) const override { 8307 DefineStd(Builder, "unix", Opts); 8308 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8309 Builder.defineMacro("__ELF__"); 8310 } 8311 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8312 return llvm::makeArrayRef(BuiltinInfo, 8313 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8314 } 8315 BuiltinVaListKind getBuiltinVaListKind() const override { 8316 return TargetInfo::PNaClABIBuiltinVaList; 8317 } 8318 const char *getClobbers() const override { return ""; } 8319 ArrayRef<const char *> getGCCRegNames() const override { 8320 return None; 8321 } 8322 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8323 return None; 8324 } 8325 bool validateAsmConstraint(const char *&Name, 8326 TargetInfo::ConstraintInfo &Info) const override { 8327 return false; 8328 } 8329 8330 bool hasProtectedVisibility() const override { return false; } 8331 }; 8332 8333 class WebAssemblyTargetInfo : public TargetInfo { 8334 static const Builtin::Info BuiltinInfo[]; 8335 8336 enum SIMDEnum { 8337 NoSIMD, 8338 SIMD128, 8339 } SIMDLevel; 8340 8341 public: 8342 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8343 : TargetInfo(T), SIMDLevel(NoSIMD) { 8344 NoAsmVariants = true; 8345 SuitableAlign = 128; 8346 LargeArrayMinWidth = 128; 8347 LargeArrayAlign = 128; 8348 SimdDefaultAlign = 128; 8349 SigAtomicType = SignedLong; 8350 LongDoubleWidth = LongDoubleAlign = 128; 8351 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8352 SizeType = UnsignedInt; 8353 PtrDiffType = SignedInt; 8354 IntPtrType = SignedInt; 8355 } 8356 8357 protected: 8358 void getTargetDefines(const LangOptions &Opts, 8359 MacroBuilder &Builder) const override { 8360 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8361 if (SIMDLevel >= SIMD128) 8362 Builder.defineMacro("__wasm_simd128__"); 8363 } 8364 8365 private: 8366 bool 8367 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8368 StringRef CPU, 8369 const std::vector<std::string> &FeaturesVec) const override { 8370 if (CPU == "bleeding-edge") 8371 Features["simd128"] = true; 8372 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8373 } 8374 bool hasFeature(StringRef Feature) const final { 8375 return llvm::StringSwitch<bool>(Feature) 8376 .Case("simd128", SIMDLevel >= SIMD128) 8377 .Default(false); 8378 } 8379 bool handleTargetFeatures(std::vector<std::string> &Features, 8380 DiagnosticsEngine &Diags) final { 8381 for (const auto &Feature : Features) { 8382 if (Feature == "+simd128") { 8383 SIMDLevel = std::max(SIMDLevel, SIMD128); 8384 continue; 8385 } 8386 if (Feature == "-simd128") { 8387 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8388 continue; 8389 } 8390 8391 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8392 << "-target-feature"; 8393 return false; 8394 } 8395 return true; 8396 } 8397 bool setCPU(const std::string &Name) final { 8398 return llvm::StringSwitch<bool>(Name) 8399 .Case("mvp", true) 8400 .Case("bleeding-edge", true) 8401 .Case("generic", true) 8402 .Default(false); 8403 } 8404 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8405 return llvm::makeArrayRef(BuiltinInfo, 8406 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8407 } 8408 BuiltinVaListKind getBuiltinVaListKind() const final { 8409 return VoidPtrBuiltinVaList; 8410 } 8411 ArrayRef<const char *> getGCCRegNames() const final { 8412 return None; 8413 } 8414 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8415 return None; 8416 } 8417 bool 8418 validateAsmConstraint(const char *&Name, 8419 TargetInfo::ConstraintInfo &Info) const final { 8420 return false; 8421 } 8422 const char *getClobbers() const final { return ""; } 8423 bool isCLZForZeroUndef() const final { return false; } 8424 bool hasInt128Type() const final { return true; } 8425 IntType getIntTypeByWidth(unsigned BitWidth, 8426 bool IsSigned) const final { 8427 // WebAssembly prefers long long for explicitly 64-bit integers. 8428 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8429 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8430 } 8431 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8432 bool IsSigned) const final { 8433 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8434 return BitWidth == 64 8435 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8436 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8437 } 8438 }; 8439 8440 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8441 #define BUILTIN(ID, TYPE, ATTRS) \ 8442 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8443 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8444 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8445 #include "clang/Basic/BuiltinsWebAssembly.def" 8446 }; 8447 8448 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8449 public: 8450 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8451 const TargetOptions &Opts) 8452 : WebAssemblyTargetInfo(T, Opts) { 8453 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8454 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8455 } 8456 8457 protected: 8458 void getTargetDefines(const LangOptions &Opts, 8459 MacroBuilder &Builder) const override { 8460 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8461 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8462 } 8463 }; 8464 8465 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8466 public: 8467 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8468 const TargetOptions &Opts) 8469 : WebAssemblyTargetInfo(T, Opts) { 8470 LongAlign = LongWidth = 64; 8471 PointerAlign = PointerWidth = 64; 8472 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8473 SizeType = UnsignedLong; 8474 PtrDiffType = SignedLong; 8475 IntPtrType = SignedLong; 8476 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8477 } 8478 8479 protected: 8480 void getTargetDefines(const LangOptions &Opts, 8481 MacroBuilder &Builder) const override { 8482 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8483 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8484 } 8485 }; 8486 8487 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8488 #define BUILTIN(ID, TYPE, ATTRS) \ 8489 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8490 #include "clang/Basic/BuiltinsLe64.def" 8491 }; 8492 8493 static const unsigned SPIRAddrSpaceMap[] = { 8494 0, // Default 8495 1, // opencl_global 8496 3, // opencl_local 8497 2, // opencl_constant 8498 4, // opencl_generic 8499 0, // cuda_device 8500 0, // cuda_constant 8501 0 // cuda_shared 8502 }; 8503 class SPIRTargetInfo : public TargetInfo { 8504 public: 8505 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8506 : TargetInfo(Triple) { 8507 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8508 "SPIR target must use unknown OS"); 8509 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8510 "SPIR target must use unknown environment type"); 8511 TLSSupported = false; 8512 LongWidth = LongAlign = 64; 8513 AddrSpaceMap = &SPIRAddrSpaceMap; 8514 UseAddrSpaceMapMangling = true; 8515 // Define available target features 8516 // These must be defined in sorted order! 8517 NoAsmVariants = true; 8518 } 8519 void getTargetDefines(const LangOptions &Opts, 8520 MacroBuilder &Builder) const override { 8521 DefineStd(Builder, "SPIR", Opts); 8522 } 8523 bool hasFeature(StringRef Feature) const override { 8524 return Feature == "spir"; 8525 } 8526 8527 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8528 const char *getClobbers() const override { return ""; } 8529 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8530 bool validateAsmConstraint(const char *&Name, 8531 TargetInfo::ConstraintInfo &info) const override { 8532 return true; 8533 } 8534 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8535 return None; 8536 } 8537 BuiltinVaListKind getBuiltinVaListKind() const override { 8538 return TargetInfo::VoidPtrBuiltinVaList; 8539 } 8540 8541 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8542 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8543 : CCCR_Warning; 8544 } 8545 8546 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8547 return CC_SpirFunction; 8548 } 8549 8550 void setSupportedOpenCLOpts() override { 8551 // Assume all OpenCL extensions and optional core features are supported 8552 // for SPIR since it is a generic target. 8553 getSupportedOpenCLOpts().supportAll(); 8554 } 8555 }; 8556 8557 class SPIR32TargetInfo : public SPIRTargetInfo { 8558 public: 8559 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8560 : SPIRTargetInfo(Triple, Opts) { 8561 PointerWidth = PointerAlign = 32; 8562 SizeType = TargetInfo::UnsignedInt; 8563 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8564 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8565 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8566 } 8567 void getTargetDefines(const LangOptions &Opts, 8568 MacroBuilder &Builder) const override { 8569 DefineStd(Builder, "SPIR32", Opts); 8570 } 8571 }; 8572 8573 class SPIR64TargetInfo : public SPIRTargetInfo { 8574 public: 8575 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8576 : SPIRTargetInfo(Triple, Opts) { 8577 PointerWidth = PointerAlign = 64; 8578 SizeType = TargetInfo::UnsignedLong; 8579 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8580 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8581 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8582 } 8583 void getTargetDefines(const LangOptions &Opts, 8584 MacroBuilder &Builder) const override { 8585 DefineStd(Builder, "SPIR64", Opts); 8586 } 8587 }; 8588 8589 class XCoreTargetInfo : public TargetInfo { 8590 static const Builtin::Info BuiltinInfo[]; 8591 public: 8592 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8593 : TargetInfo(Triple) { 8594 NoAsmVariants = true; 8595 LongLongAlign = 32; 8596 SuitableAlign = 32; 8597 DoubleAlign = LongDoubleAlign = 32; 8598 SizeType = UnsignedInt; 8599 PtrDiffType = SignedInt; 8600 IntPtrType = SignedInt; 8601 WCharType = UnsignedChar; 8602 WIntType = UnsignedInt; 8603 UseZeroLengthBitfieldAlignment = true; 8604 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8605 "-f64:32-a:0:32-n32"); 8606 } 8607 void getTargetDefines(const LangOptions &Opts, 8608 MacroBuilder &Builder) const override { 8609 Builder.defineMacro("__XS1B__"); 8610 } 8611 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8612 return llvm::makeArrayRef(BuiltinInfo, 8613 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8614 } 8615 BuiltinVaListKind getBuiltinVaListKind() const override { 8616 return TargetInfo::VoidPtrBuiltinVaList; 8617 } 8618 const char *getClobbers() const override { 8619 return ""; 8620 } 8621 ArrayRef<const char *> getGCCRegNames() const override { 8622 static const char * const GCCRegNames[] = { 8623 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8624 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8625 }; 8626 return llvm::makeArrayRef(GCCRegNames); 8627 } 8628 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8629 return None; 8630 } 8631 bool validateAsmConstraint(const char *&Name, 8632 TargetInfo::ConstraintInfo &Info) const override { 8633 return false; 8634 } 8635 int getEHDataRegisterNumber(unsigned RegNo) const override { 8636 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8637 return (RegNo < 2)? RegNo : -1; 8638 } 8639 bool allowsLargerPreferedTypeAlignment() const override { 8640 return false; 8641 } 8642 }; 8643 8644 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8645 #define BUILTIN(ID, TYPE, ATTRS) \ 8646 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8647 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8648 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8649 #include "clang/Basic/BuiltinsXCore.def" 8650 }; 8651 8652 // x86_32 Android target 8653 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8654 public: 8655 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8656 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8657 SuitableAlign = 32; 8658 LongDoubleWidth = 64; 8659 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8660 } 8661 }; 8662 8663 // x86_64 Android target 8664 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8665 public: 8666 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8667 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8668 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8669 } 8670 8671 bool useFloat128ManglingForLongDouble() const override { 8672 return true; 8673 } 8674 }; 8675 8676 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8677 class RenderScript32TargetInfo : public ARMleTargetInfo { 8678 public: 8679 RenderScript32TargetInfo(const llvm::Triple &Triple, 8680 const TargetOptions &Opts) 8681 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8682 Triple.getOSName(), 8683 Triple.getEnvironmentName()), 8684 Opts) { 8685 IsRenderScriptTarget = true; 8686 LongWidth = LongAlign = 64; 8687 } 8688 void getTargetDefines(const LangOptions &Opts, 8689 MacroBuilder &Builder) const override { 8690 Builder.defineMacro("__RENDERSCRIPT__"); 8691 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8692 } 8693 }; 8694 8695 // 64-bit RenderScript is aarch64 8696 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8697 public: 8698 RenderScript64TargetInfo(const llvm::Triple &Triple, 8699 const TargetOptions &Opts) 8700 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8701 Triple.getOSName(), 8702 Triple.getEnvironmentName()), 8703 Opts) { 8704 IsRenderScriptTarget = true; 8705 } 8706 8707 void getTargetDefines(const LangOptions &Opts, 8708 MacroBuilder &Builder) const override { 8709 Builder.defineMacro("__RENDERSCRIPT__"); 8710 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8711 } 8712 }; 8713 8714 /// Information about a specific microcontroller. 8715 struct MCUInfo { 8716 const char *Name; 8717 const char *DefineName; 8718 }; 8719 8720 // This list should be kept up-to-date with AVRDevices.td in LLVM. 8721 static ArrayRef<MCUInfo> AVRMcus = { 8722 { "at90s1200", "__AVR_AT90S1200__" }, 8723 { "attiny11", "__AVR_ATtiny11__" }, 8724 { "attiny12", "__AVR_ATtiny12__" }, 8725 { "attiny15", "__AVR_ATtiny15__" }, 8726 { "attiny28", "__AVR_ATtiny28__" }, 8727 { "at90s2313", "__AVR_AT90S2313__" }, 8728 { "at90s2323", "__AVR_AT90S2323__" }, 8729 { "at90s2333", "__AVR_AT90S2333__" }, 8730 { "at90s2343", "__AVR_AT90S2343__" }, 8731 { "attiny22", "__AVR_ATtiny22__" }, 8732 { "attiny26", "__AVR_ATtiny26__" }, 8733 { "at86rf401", "__AVR_AT86RF401__" }, 8734 { "at90s4414", "__AVR_AT90S4414__" }, 8735 { "at90s4433", "__AVR_AT90S4433__" }, 8736 { "at90s4434", "__AVR_AT90S4434__" }, 8737 { "at90s8515", "__AVR_AT90S8515__" }, 8738 { "at90c8534", "__AVR_AT90c8534__" }, 8739 { "at90s8535", "__AVR_AT90S8535__" }, 8740 { "ata5272", "__AVR_ATA5272__" }, 8741 { "attiny13", "__AVR_ATtiny13__" }, 8742 { "attiny13a", "__AVR_ATtiny13A__" }, 8743 { "attiny2313", "__AVR_ATtiny2313__" }, 8744 { "attiny2313a", "__AVR_ATtiny2313A__" }, 8745 { "attiny24", "__AVR_ATtiny24__" }, 8746 { "attiny24a", "__AVR_ATtiny24A__" }, 8747 { "attiny4313", "__AVR_ATtiny4313__" }, 8748 { "attiny44", "__AVR_ATtiny44__" }, 8749 { "attiny44a", "__AVR_ATtiny44A__" }, 8750 { "attiny84", "__AVR_ATtiny84__" }, 8751 { "attiny84a", "__AVR_ATtiny84A__" }, 8752 { "attiny25", "__AVR_ATtiny25__" }, 8753 { "attiny45", "__AVR_ATtiny45__" }, 8754 { "attiny85", "__AVR_ATtiny85__" }, 8755 { "attiny261", "__AVR_ATtiny261__" }, 8756 { "attiny261a", "__AVR_ATtiny261A__" }, 8757 { "attiny461", "__AVR_ATtiny461__" }, 8758 { "attiny461a", "__AVR_ATtiny461A__" }, 8759 { "attiny861", "__AVR_ATtiny861__" }, 8760 { "attiny861a", "__AVR_ATtiny861A__" }, 8761 { "attiny87", "__AVR_ATtiny87__" }, 8762 { "attiny43u", "__AVR_ATtiny43U__" }, 8763 { "attiny48", "__AVR_ATtiny48__" }, 8764 { "attiny88", "__AVR_ATtiny88__" }, 8765 { "attiny828", "__AVR_ATtiny828__" }, 8766 { "at43usb355", "__AVR_AT43USB355__" }, 8767 { "at76c711", "__AVR_AT76C711__" }, 8768 { "atmega103", "__AVR_ATmega103__" }, 8769 { "at43usb320", "__AVR_AT43USB320__" }, 8770 { "attiny167", "__AVR_ATtiny167__" }, 8771 { "at90usb82", "__AVR_AT90USB82__" }, 8772 { "at90usb162", "__AVR_AT90USB162__" }, 8773 { "ata5505", "__AVR_ATA5505__" }, 8774 { "atmega8u2", "__AVR_ATmega8U2__" }, 8775 { "atmega16u2", "__AVR_ATmega16U2__" }, 8776 { "atmega32u2", "__AVR_ATmega32U2__" }, 8777 { "attiny1634", "__AVR_ATtiny1634__" }, 8778 { "atmega8", "__AVR_ATmega8__" }, 8779 { "ata6289", "__AVR_ATA6289__" }, 8780 { "atmega8a", "__AVR_ATmega8A__" }, 8781 { "ata6285", "__AVR_ATA6285__" }, 8782 { "ata6286", "__AVR_ATA6286__" }, 8783 { "atmega48", "__AVR_ATmega48__" }, 8784 { "atmega48a", "__AVR_ATmega48A__" }, 8785 { "atmega48pa", "__AVR_ATmega48PA__" }, 8786 { "atmega48p", "__AVR_ATmega48P__" }, 8787 { "atmega88", "__AVR_ATmega88__" }, 8788 { "atmega88a", "__AVR_ATmega88A__" }, 8789 { "atmega88p", "__AVR_ATmega88P__" }, 8790 { "atmega88pa", "__AVR_ATmega88PA__" }, 8791 { "atmega8515", "__AVR_ATmega8515__" }, 8792 { "atmega8535", "__AVR_ATmega8535__" }, 8793 { "atmega8hva", "__AVR_ATmega8HVA__" }, 8794 { "at90pwm1", "__AVR_AT90PWM1__" }, 8795 { "at90pwm2", "__AVR_AT90PWM2__" }, 8796 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 8797 { "at90pwm3", "__AVR_AT90PWM3__" }, 8798 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 8799 { "at90pwm81", "__AVR_AT90PWM81__" }, 8800 { "ata5790", "__AVR_ATA5790__" }, 8801 { "ata5795", "__AVR_ATA5795__" }, 8802 { "atmega16", "__AVR_ATmega16__" }, 8803 { "atmega16a", "__AVR_ATmega16A__" }, 8804 { "atmega161", "__AVR_ATmega161__" }, 8805 { "atmega162", "__AVR_ATmega162__" }, 8806 { "atmega163", "__AVR_ATmega163__" }, 8807 { "atmega164a", "__AVR_ATmega164A__" }, 8808 { "atmega164p", "__AVR_ATmega164P__" }, 8809 { "atmega164pa", "__AVR_ATmega164PA__" }, 8810 { "atmega165", "__AVR_ATmega165__" }, 8811 { "atmega165a", "__AVR_ATmega165A__" }, 8812 { "atmega165p", "__AVR_ATmega165P__" }, 8813 { "atmega165pa", "__AVR_ATmega165PA__" }, 8814 { "atmega168", "__AVR_ATmega168__" }, 8815 { "atmega168a", "__AVR_ATmega168A__" }, 8816 { "atmega168p", "__AVR_ATmega168P__" }, 8817 { "atmega168pa", "__AVR_ATmega168PA__" }, 8818 { "atmega169", "__AVR_ATmega169__" }, 8819 { "atmega169a", "__AVR_ATmega169A__" }, 8820 { "atmega169p", "__AVR_ATmega169P__" }, 8821 { "atmega169pa", "__AVR_ATmega169PA__" }, 8822 { "atmega32", "__AVR_ATmega32__" }, 8823 { "atmega32a", "__AVR_ATmega32A__" }, 8824 { "atmega323", "__AVR_ATmega323__" }, 8825 { "atmega324a", "__AVR_ATmega324A__" }, 8826 { "atmega324p", "__AVR_ATmega324P__" }, 8827 { "atmega324pa", "__AVR_ATmega324PA__" }, 8828 { "atmega325", "__AVR_ATmega325__" }, 8829 { "atmega325a", "__AVR_ATmega325A__" }, 8830 { "atmega325p", "__AVR_ATmega325P__" }, 8831 { "atmega325pa", "__AVR_ATmega325PA__" }, 8832 { "atmega3250", "__AVR_ATmega3250__" }, 8833 { "atmega3250a", "__AVR_ATmega3250A__" }, 8834 { "atmega3250p", "__AVR_ATmega3250P__" }, 8835 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 8836 { "atmega328", "__AVR_ATmega328__" }, 8837 { "atmega328p", "__AVR_ATmega328P__" }, 8838 { "atmega329", "__AVR_ATmega329__" }, 8839 { "atmega329a", "__AVR_ATmega329A__" }, 8840 { "atmega329p", "__AVR_ATmega329P__" }, 8841 { "atmega329pa", "__AVR_ATmega329PA__" }, 8842 { "atmega3290", "__AVR_ATmega3290__" }, 8843 { "atmega3290a", "__AVR_ATmega3290A__" }, 8844 { "atmega3290p", "__AVR_ATmega3290P__" }, 8845 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 8846 { "atmega406", "__AVR_ATmega406__" }, 8847 { "atmega64", "__AVR_ATmega64__" }, 8848 { "atmega64a", "__AVR_ATmega64A__" }, 8849 { "atmega640", "__AVR_ATmega640__" }, 8850 { "atmega644", "__AVR_ATmega644__" }, 8851 { "atmega644a", "__AVR_ATmega644A__" }, 8852 { "atmega644p", "__AVR_ATmega644P__" }, 8853 { "atmega644pa", "__AVR_ATmega644PA__" }, 8854 { "atmega645", "__AVR_ATmega645__" }, 8855 { "atmega645a", "__AVR_ATmega645A__" }, 8856 { "atmega645p", "__AVR_ATmega645P__" }, 8857 { "atmega649", "__AVR_ATmega649__" }, 8858 { "atmega649a", "__AVR_ATmega649A__" }, 8859 { "atmega649p", "__AVR_ATmega649P__" }, 8860 { "atmega6450", "__AVR_ATmega6450__" }, 8861 { "atmega6450a", "__AVR_ATmega6450A__" }, 8862 { "atmega6450p", "__AVR_ATmega6450P__" }, 8863 { "atmega6490", "__AVR_ATmega6490__" }, 8864 { "atmega6490a", "__AVR_ATmega6490A__" }, 8865 { "atmega6490p", "__AVR_ATmega6490P__" }, 8866 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 8867 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 8868 { "atmega16hva", "__AVR_ATmega16HVA__" }, 8869 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 8870 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 8871 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 8872 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 8873 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 8874 { "atmega64hve", "__AVR_ATmega64HVE__" }, 8875 { "at90can32", "__AVR_AT90CAN32__" }, 8876 { "at90can64", "__AVR_AT90CAN64__" }, 8877 { "at90pwm161", "__AVR_AT90PWM161__" }, 8878 { "at90pwm216", "__AVR_AT90PWM216__" }, 8879 { "at90pwm316", "__AVR_AT90PWM316__" }, 8880 { "atmega32c1", "__AVR_ATmega32C1__" }, 8881 { "atmega64c1", "__AVR_ATmega64C1__" }, 8882 { "atmega16m1", "__AVR_ATmega16M1__" }, 8883 { "atmega32m1", "__AVR_ATmega32M1__" }, 8884 { "atmega64m1", "__AVR_ATmega64M1__" }, 8885 { "atmega16u4", "__AVR_ATmega16U4__" }, 8886 { "atmega32u4", "__AVR_ATmega32U4__" }, 8887 { "atmega32u6", "__AVR_ATmega32U6__" }, 8888 { "at90usb646", "__AVR_AT90USB646__" }, 8889 { "at90usb647", "__AVR_AT90USB647__" }, 8890 { "at90scr100", "__AVR_AT90SCR100__" }, 8891 { "at94k", "__AVR_AT94K__" }, 8892 { "m3000", "__AVR_AT000__" }, 8893 { "atmega128", "__AVR_ATmega128__" }, 8894 { "atmega128a", "__AVR_ATmega128A__" }, 8895 { "atmega1280", "__AVR_ATmega1280__" }, 8896 { "atmega1281", "__AVR_ATmega1281__" }, 8897 { "atmega1284", "__AVR_ATmega1284__" }, 8898 { "atmega1284p", "__AVR_ATmega1284P__" }, 8899 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 8900 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 8901 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 8902 { "at90can128", "__AVR_AT90CAN128__" }, 8903 { "at90usb1286", "__AVR_AT90USB1286__" }, 8904 { "at90usb1287", "__AVR_AT90USB1287__" }, 8905 { "atmega2560", "__AVR_ATmega2560__" }, 8906 { "atmega2561", "__AVR_ATmega2561__" }, 8907 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 8908 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 8909 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 8910 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 8911 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 8912 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 8913 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 8914 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 8915 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 8916 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 8917 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 8918 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 8919 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 8920 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 8921 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 8922 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 8923 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 8924 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 8925 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 8926 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 8927 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 8928 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 8929 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 8930 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 8931 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 8932 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 8933 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 8934 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 8935 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 8936 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 8937 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 8938 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 8939 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 8940 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 8941 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 8942 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 8943 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 8944 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 8945 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 8946 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 8947 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 8948 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 8949 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 8950 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 8951 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 8952 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 8953 { "attiny4", "__AVR_ATtiny4__" }, 8954 { "attiny5", "__AVR_ATtiny5__" }, 8955 { "attiny9", "__AVR_ATtiny9__" }, 8956 { "attiny10", "__AVR_ATtiny10__" }, 8957 { "attiny20", "__AVR_ATtiny20__" }, 8958 { "attiny40", "__AVR_ATtiny40__" }, 8959 { "attiny102", "__AVR_ATtiny102__" }, 8960 { "attiny104", "__AVR_ATtiny104__" }, 8961 }; 8962 8963 // AVR Target 8964 class AVRTargetInfo : public TargetInfo { 8965 public: 8966 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8967 : TargetInfo(Triple) { 8968 TLSSupported = false; 8969 PointerWidth = 16; 8970 PointerAlign = 8; 8971 IntWidth = 16; 8972 IntAlign = 8; 8973 LongWidth = 32; 8974 LongAlign = 8; 8975 LongLongWidth = 64; 8976 LongLongAlign = 8; 8977 SuitableAlign = 8; 8978 DefaultAlignForAttributeAligned = 8; 8979 HalfWidth = 16; 8980 HalfAlign = 8; 8981 FloatWidth = 32; 8982 FloatAlign = 8; 8983 DoubleWidth = 32; 8984 DoubleAlign = 8; 8985 DoubleFormat = &llvm::APFloat::IEEEsingle(); 8986 LongDoubleWidth = 32; 8987 LongDoubleAlign = 8; 8988 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 8989 SizeType = UnsignedInt; 8990 PtrDiffType = SignedInt; 8991 IntPtrType = SignedInt; 8992 Char16Type = UnsignedInt; 8993 WCharType = SignedInt; 8994 WIntType = SignedInt; 8995 Char32Type = UnsignedLong; 8996 SigAtomicType = SignedChar; 8997 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 8998 "-f32:32:32-f64:64:64-n8"); 8999 } 9000 9001 void getTargetDefines(const LangOptions &Opts, 9002 MacroBuilder &Builder) const override { 9003 Builder.defineMacro("AVR"); 9004 Builder.defineMacro("__AVR"); 9005 Builder.defineMacro("__AVR__"); 9006 9007 if (!this->CPU.empty()) { 9008 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9009 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 9010 9011 if (It != AVRMcus.end()) 9012 Builder.defineMacro(It->DefineName); 9013 } 9014 } 9015 9016 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 9017 return None; 9018 } 9019 9020 BuiltinVaListKind getBuiltinVaListKind() const override { 9021 return TargetInfo::VoidPtrBuiltinVaList; 9022 } 9023 9024 const char *getClobbers() const override { 9025 return ""; 9026 } 9027 9028 ArrayRef<const char *> getGCCRegNames() const override { 9029 static const char * const GCCRegNames[] = { 9030 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 9031 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 9032 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 9033 "r24", "r25", "X", "Y", "Z", "SP" 9034 }; 9035 return llvm::makeArrayRef(GCCRegNames); 9036 } 9037 9038 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 9039 return None; 9040 } 9041 9042 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 9043 static const TargetInfo::AddlRegName AddlRegNames[] = { 9044 { { "r26", "r27"}, 26 }, 9045 { { "r28", "r29"}, 27 }, 9046 { { "r30", "r31"}, 28 }, 9047 { { "SPL", "SPH"}, 29 }, 9048 }; 9049 return llvm::makeArrayRef(AddlRegNames); 9050 } 9051 9052 bool validateAsmConstraint(const char *&Name, 9053 TargetInfo::ConstraintInfo &Info) const override { 9054 // There aren't any multi-character AVR specific constraints. 9055 if (StringRef(Name).size() > 1) return false; 9056 9057 switch (*Name) { 9058 default: return false; 9059 case 'a': // Simple upper registers 9060 case 'b': // Base pointer registers pairs 9061 case 'd': // Upper register 9062 case 'l': // Lower registers 9063 case 'e': // Pointer register pairs 9064 case 'q': // Stack pointer register 9065 case 'r': // Any register 9066 case 'w': // Special upper register pairs 9067 case 't': // Temporary register 9068 case 'x': case 'X': // Pointer register pair X 9069 case 'y': case 'Y': // Pointer register pair Y 9070 case 'z': case 'Z': // Pointer register pair Z 9071 Info.setAllowsRegister(); 9072 return true; 9073 case 'I': // 6-bit positive integer constant 9074 Info.setRequiresImmediate(0, 63); 9075 return true; 9076 case 'J': // 6-bit negative integer constant 9077 Info.setRequiresImmediate(-63, 0); 9078 return true; 9079 case 'K': // Integer constant (Range: 2) 9080 Info.setRequiresImmediate(2); 9081 return true; 9082 case 'L': // Integer constant (Range: 0) 9083 Info.setRequiresImmediate(0); 9084 return true; 9085 case 'M': // 8-bit integer constant 9086 Info.setRequiresImmediate(0, 0xff); 9087 return true; 9088 case 'N': // Integer constant (Range: -1) 9089 Info.setRequiresImmediate(-1); 9090 return true; 9091 case 'O': // Integer constant (Range: 8, 16, 24) 9092 Info.setRequiresImmediate({8, 16, 24}); 9093 return true; 9094 case 'P': // Integer constant (Range: 1) 9095 Info.setRequiresImmediate(1); 9096 return true; 9097 case 'R': // Integer constant (Range: -6 to 5) 9098 Info.setRequiresImmediate(-6, 5); 9099 return true; 9100 case 'G': // Floating point constant 9101 case 'Q': // A memory address based on Y or Z pointer with displacement. 9102 return true; 9103 } 9104 9105 return false; 9106 } 9107 9108 IntType getIntTypeByWidth(unsigned BitWidth, 9109 bool IsSigned) const final { 9110 // AVR prefers int for 16-bit integers. 9111 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 9112 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 9113 } 9114 9115 IntType getLeastIntTypeByWidth(unsigned BitWidth, 9116 bool IsSigned) const final { 9117 // AVR uses int for int_least16_t and int_fast16_t. 9118 return BitWidth == 16 9119 ? (IsSigned ? SignedInt : UnsignedInt) 9120 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 9121 } 9122 9123 bool setCPU(const std::string &Name) override { 9124 bool IsFamily = llvm::StringSwitch<bool>(Name) 9125 .Case("avr1", true) 9126 .Case("avr2", true) 9127 .Case("avr25", true) 9128 .Case("avr3", true) 9129 .Case("avr31", true) 9130 .Case("avr35", true) 9131 .Case("avr4", true) 9132 .Case("avr5", true) 9133 .Case("avr51", true) 9134 .Case("avr6", true) 9135 .Case("avrxmega1", true) 9136 .Case("avrxmega2", true) 9137 .Case("avrxmega3", true) 9138 .Case("avrxmega4", true) 9139 .Case("avrxmega5", true) 9140 .Case("avrxmega6", true) 9141 .Case("avrxmega7", true) 9142 .Case("avrtiny", true) 9143 .Default(false); 9144 9145 if (IsFamily) this->CPU = Name; 9146 9147 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9148 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 9149 9150 if (IsMCU) this->CPU = Name; 9151 9152 return IsFamily || IsMCU; 9153 } 9154 9155 protected: 9156 std::string CPU; 9157 }; 9158 9159 } // end anonymous namespace 9160 9161 //===----------------------------------------------------------------------===// 9162 // Driver code 9163 //===----------------------------------------------------------------------===// 9164 9165 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 9166 const TargetOptions &Opts) { 9167 llvm::Triple::OSType os = Triple.getOS(); 9168 9169 switch (Triple.getArch()) { 9170 default: 9171 return nullptr; 9172 9173 case llvm::Triple::xcore: 9174 return new XCoreTargetInfo(Triple, Opts); 9175 9176 case llvm::Triple::hexagon: 9177 return new HexagonTargetInfo(Triple, Opts); 9178 9179 case llvm::Triple::lanai: 9180 return new LanaiTargetInfo(Triple, Opts); 9181 9182 case llvm::Triple::aarch64: 9183 if (Triple.isOSDarwin()) 9184 return new DarwinAArch64TargetInfo(Triple, Opts); 9185 9186 switch (os) { 9187 case llvm::Triple::CloudABI: 9188 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 9189 case llvm::Triple::FreeBSD: 9190 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9191 case llvm::Triple::Fuchsia: 9192 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9193 case llvm::Triple::Linux: 9194 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9195 case llvm::Triple::NetBSD: 9196 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9197 case llvm::Triple::OpenBSD: 9198 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9199 default: 9200 return new AArch64leTargetInfo(Triple, Opts); 9201 } 9202 9203 case llvm::Triple::aarch64_be: 9204 switch (os) { 9205 case llvm::Triple::FreeBSD: 9206 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9207 case llvm::Triple::Fuchsia: 9208 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9209 case llvm::Triple::Linux: 9210 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9211 case llvm::Triple::NetBSD: 9212 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9213 default: 9214 return new AArch64beTargetInfo(Triple, Opts); 9215 } 9216 9217 case llvm::Triple::arm: 9218 case llvm::Triple::thumb: 9219 if (Triple.isOSBinFormatMachO()) 9220 return new DarwinARMTargetInfo(Triple, Opts); 9221 9222 switch (os) { 9223 case llvm::Triple::CloudABI: 9224 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9225 case llvm::Triple::Linux: 9226 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9227 case llvm::Triple::FreeBSD: 9228 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9229 case llvm::Triple::NetBSD: 9230 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9231 case llvm::Triple::OpenBSD: 9232 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9233 case llvm::Triple::Bitrig: 9234 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9235 case llvm::Triple::RTEMS: 9236 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9237 case llvm::Triple::NaCl: 9238 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9239 case llvm::Triple::Win32: 9240 switch (Triple.getEnvironment()) { 9241 case llvm::Triple::Cygnus: 9242 return new CygwinARMTargetInfo(Triple, Opts); 9243 case llvm::Triple::GNU: 9244 return new MinGWARMTargetInfo(Triple, Opts); 9245 case llvm::Triple::Itanium: 9246 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9247 case llvm::Triple::MSVC: 9248 default: // Assume MSVC for unknown environments 9249 return new MicrosoftARMleTargetInfo(Triple, Opts); 9250 } 9251 default: 9252 return new ARMleTargetInfo(Triple, Opts); 9253 } 9254 9255 case llvm::Triple::armeb: 9256 case llvm::Triple::thumbeb: 9257 if (Triple.isOSDarwin()) 9258 return new DarwinARMTargetInfo(Triple, Opts); 9259 9260 switch (os) { 9261 case llvm::Triple::Linux: 9262 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9263 case llvm::Triple::FreeBSD: 9264 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9265 case llvm::Triple::NetBSD: 9266 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9267 case llvm::Triple::OpenBSD: 9268 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9269 case llvm::Triple::Bitrig: 9270 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9271 case llvm::Triple::RTEMS: 9272 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9273 case llvm::Triple::NaCl: 9274 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9275 default: 9276 return new ARMbeTargetInfo(Triple, Opts); 9277 } 9278 9279 case llvm::Triple::avr: 9280 return new AVRTargetInfo(Triple, Opts); 9281 case llvm::Triple::bpfeb: 9282 case llvm::Triple::bpfel: 9283 return new BPFTargetInfo(Triple, Opts); 9284 9285 case llvm::Triple::msp430: 9286 return new MSP430TargetInfo(Triple, Opts); 9287 9288 case llvm::Triple::mips: 9289 switch (os) { 9290 case llvm::Triple::Linux: 9291 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9292 case llvm::Triple::RTEMS: 9293 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9294 case llvm::Triple::FreeBSD: 9295 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9296 case llvm::Triple::NetBSD: 9297 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9298 default: 9299 return new MipsTargetInfo(Triple, Opts); 9300 } 9301 9302 case llvm::Triple::mipsel: 9303 switch (os) { 9304 case llvm::Triple::Linux: 9305 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9306 case llvm::Triple::RTEMS: 9307 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9308 case llvm::Triple::FreeBSD: 9309 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9310 case llvm::Triple::NetBSD: 9311 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9312 case llvm::Triple::NaCl: 9313 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9314 default: 9315 return new MipsTargetInfo(Triple, Opts); 9316 } 9317 9318 case llvm::Triple::mips64: 9319 switch (os) { 9320 case llvm::Triple::Linux: 9321 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9322 case llvm::Triple::RTEMS: 9323 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9324 case llvm::Triple::FreeBSD: 9325 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9326 case llvm::Triple::NetBSD: 9327 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9328 case llvm::Triple::OpenBSD: 9329 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9330 default: 9331 return new MipsTargetInfo(Triple, Opts); 9332 } 9333 9334 case llvm::Triple::mips64el: 9335 switch (os) { 9336 case llvm::Triple::Linux: 9337 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9338 case llvm::Triple::RTEMS: 9339 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9340 case llvm::Triple::FreeBSD: 9341 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9342 case llvm::Triple::NetBSD: 9343 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9344 case llvm::Triple::OpenBSD: 9345 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9346 default: 9347 return new MipsTargetInfo(Triple, Opts); 9348 } 9349 9350 case llvm::Triple::le32: 9351 switch (os) { 9352 case llvm::Triple::NaCl: 9353 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9354 default: 9355 return nullptr; 9356 } 9357 9358 case llvm::Triple::le64: 9359 return new Le64TargetInfo(Triple, Opts); 9360 9361 case llvm::Triple::ppc: 9362 if (Triple.isOSDarwin()) 9363 return new DarwinPPC32TargetInfo(Triple, Opts); 9364 switch (os) { 9365 case llvm::Triple::Linux: 9366 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9367 case llvm::Triple::FreeBSD: 9368 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9369 case llvm::Triple::NetBSD: 9370 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9371 case llvm::Triple::OpenBSD: 9372 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9373 case llvm::Triple::RTEMS: 9374 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9375 default: 9376 return new PPC32TargetInfo(Triple, Opts); 9377 } 9378 9379 case llvm::Triple::ppc64: 9380 if (Triple.isOSDarwin()) 9381 return new DarwinPPC64TargetInfo(Triple, Opts); 9382 switch (os) { 9383 case llvm::Triple::Linux: 9384 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9385 case llvm::Triple::Lv2: 9386 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9387 case llvm::Triple::FreeBSD: 9388 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9389 case llvm::Triple::NetBSD: 9390 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9391 default: 9392 return new PPC64TargetInfo(Triple, Opts); 9393 } 9394 9395 case llvm::Triple::ppc64le: 9396 switch (os) { 9397 case llvm::Triple::Linux: 9398 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9399 case llvm::Triple::NetBSD: 9400 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9401 default: 9402 return new PPC64TargetInfo(Triple, Opts); 9403 } 9404 9405 case llvm::Triple::nvptx: 9406 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9407 case llvm::Triple::nvptx64: 9408 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9409 9410 case llvm::Triple::amdgcn: 9411 case llvm::Triple::r600: 9412 return new AMDGPUTargetInfo(Triple, Opts); 9413 9414 case llvm::Triple::sparc: 9415 switch (os) { 9416 case llvm::Triple::Linux: 9417 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9418 case llvm::Triple::Solaris: 9419 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9420 case llvm::Triple::NetBSD: 9421 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9422 case llvm::Triple::OpenBSD: 9423 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9424 case llvm::Triple::RTEMS: 9425 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9426 default: 9427 return new SparcV8TargetInfo(Triple, Opts); 9428 } 9429 9430 // The 'sparcel' architecture copies all the above cases except for Solaris. 9431 case llvm::Triple::sparcel: 9432 switch (os) { 9433 case llvm::Triple::Linux: 9434 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9435 case llvm::Triple::NetBSD: 9436 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9437 case llvm::Triple::OpenBSD: 9438 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9439 case llvm::Triple::RTEMS: 9440 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9441 default: 9442 return new SparcV8elTargetInfo(Triple, Opts); 9443 } 9444 9445 case llvm::Triple::sparcv9: 9446 switch (os) { 9447 case llvm::Triple::Linux: 9448 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9449 case llvm::Triple::Solaris: 9450 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9451 case llvm::Triple::NetBSD: 9452 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9453 case llvm::Triple::OpenBSD: 9454 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9455 case llvm::Triple::FreeBSD: 9456 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9457 default: 9458 return new SparcV9TargetInfo(Triple, Opts); 9459 } 9460 9461 case llvm::Triple::systemz: 9462 switch (os) { 9463 case llvm::Triple::Linux: 9464 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9465 default: 9466 return new SystemZTargetInfo(Triple, Opts); 9467 } 9468 9469 case llvm::Triple::tce: 9470 return new TCETargetInfo(Triple, Opts); 9471 9472 case llvm::Triple::tcele: 9473 return new TCELETargetInfo(Triple, Opts); 9474 9475 case llvm::Triple::x86: 9476 if (Triple.isOSDarwin()) 9477 return new DarwinI386TargetInfo(Triple, Opts); 9478 9479 switch (os) { 9480 case llvm::Triple::CloudABI: 9481 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9482 case llvm::Triple::Linux: { 9483 switch (Triple.getEnvironment()) { 9484 default: 9485 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9486 case llvm::Triple::Android: 9487 return new AndroidX86_32TargetInfo(Triple, Opts); 9488 } 9489 } 9490 case llvm::Triple::DragonFly: 9491 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9492 case llvm::Triple::NetBSD: 9493 return new NetBSDI386TargetInfo(Triple, Opts); 9494 case llvm::Triple::OpenBSD: 9495 return new OpenBSDI386TargetInfo(Triple, Opts); 9496 case llvm::Triple::Bitrig: 9497 return new BitrigI386TargetInfo(Triple, Opts); 9498 case llvm::Triple::FreeBSD: 9499 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9500 case llvm::Triple::KFreeBSD: 9501 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9502 case llvm::Triple::Minix: 9503 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9504 case llvm::Triple::Solaris: 9505 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9506 case llvm::Triple::Win32: { 9507 switch (Triple.getEnvironment()) { 9508 case llvm::Triple::Cygnus: 9509 return new CygwinX86_32TargetInfo(Triple, Opts); 9510 case llvm::Triple::GNU: 9511 return new MinGWX86_32TargetInfo(Triple, Opts); 9512 case llvm::Triple::Itanium: 9513 case llvm::Triple::MSVC: 9514 default: // Assume MSVC for unknown environments 9515 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9516 } 9517 } 9518 case llvm::Triple::Haiku: 9519 return new HaikuX86_32TargetInfo(Triple, Opts); 9520 case llvm::Triple::RTEMS: 9521 return new RTEMSX86_32TargetInfo(Triple, Opts); 9522 case llvm::Triple::NaCl: 9523 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9524 case llvm::Triple::ELFIAMCU: 9525 return new MCUX86_32TargetInfo(Triple, Opts); 9526 default: 9527 return new X86_32TargetInfo(Triple, Opts); 9528 } 9529 9530 case llvm::Triple::x86_64: 9531 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9532 return new DarwinX86_64TargetInfo(Triple, Opts); 9533 9534 switch (os) { 9535 case llvm::Triple::CloudABI: 9536 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9537 case llvm::Triple::Linux: { 9538 switch (Triple.getEnvironment()) { 9539 default: 9540 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9541 case llvm::Triple::Android: 9542 return new AndroidX86_64TargetInfo(Triple, Opts); 9543 } 9544 } 9545 case llvm::Triple::DragonFly: 9546 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9547 case llvm::Triple::NetBSD: 9548 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9549 case llvm::Triple::OpenBSD: 9550 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9551 case llvm::Triple::Bitrig: 9552 return new BitrigX86_64TargetInfo(Triple, Opts); 9553 case llvm::Triple::FreeBSD: 9554 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9555 case llvm::Triple::Fuchsia: 9556 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9557 case llvm::Triple::KFreeBSD: 9558 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9559 case llvm::Triple::Solaris: 9560 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9561 case llvm::Triple::Win32: { 9562 switch (Triple.getEnvironment()) { 9563 case llvm::Triple::Cygnus: 9564 return new CygwinX86_64TargetInfo(Triple, Opts); 9565 case llvm::Triple::GNU: 9566 return new MinGWX86_64TargetInfo(Triple, Opts); 9567 case llvm::Triple::MSVC: 9568 default: // Assume MSVC for unknown environments 9569 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9570 } 9571 } 9572 case llvm::Triple::Haiku: 9573 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9574 case llvm::Triple::NaCl: 9575 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9576 case llvm::Triple::PS4: 9577 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9578 default: 9579 return new X86_64TargetInfo(Triple, Opts); 9580 } 9581 9582 case llvm::Triple::spir: { 9583 if (Triple.getOS() != llvm::Triple::UnknownOS || 9584 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9585 return nullptr; 9586 return new SPIR32TargetInfo(Triple, Opts); 9587 } 9588 case llvm::Triple::spir64: { 9589 if (Triple.getOS() != llvm::Triple::UnknownOS || 9590 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9591 return nullptr; 9592 return new SPIR64TargetInfo(Triple, Opts); 9593 } 9594 case llvm::Triple::wasm32: 9595 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9596 Triple.getVendor() != llvm::Triple::UnknownVendor || 9597 Triple.getOS() != llvm::Triple::UnknownOS || 9598 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9599 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9600 return nullptr; 9601 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9602 case llvm::Triple::wasm64: 9603 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9604 Triple.getVendor() != llvm::Triple::UnknownVendor || 9605 Triple.getOS() != llvm::Triple::UnknownOS || 9606 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9607 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9608 return nullptr; 9609 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9610 9611 case llvm::Triple::renderscript32: 9612 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9613 case llvm::Triple::renderscript64: 9614 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9615 } 9616 } 9617 9618 /// CreateTargetInfo - Return the target info object for the specified target 9619 /// options. 9620 TargetInfo * 9621 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9622 const std::shared_ptr<TargetOptions> &Opts) { 9623 llvm::Triple Triple(Opts->Triple); 9624 9625 // Construct the target 9626 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9627 if (!Target) { 9628 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9629 return nullptr; 9630 } 9631 Target->TargetOpts = Opts; 9632 9633 // Set the target CPU if specified. 9634 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9635 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9636 return nullptr; 9637 } 9638 9639 // Set the target ABI if specified. 9640 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 9641 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 9642 return nullptr; 9643 } 9644 9645 // Set the fp math unit. 9646 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 9647 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 9648 return nullptr; 9649 } 9650 9651 // Compute the default target features, we need the target to handle this 9652 // because features may have dependencies on one another. 9653 llvm::StringMap<bool> Features; 9654 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 9655 Opts->FeaturesAsWritten)) 9656 return nullptr; 9657 9658 // Add the features to the compile options. 9659 Opts->Features.clear(); 9660 for (const auto &F : Features) 9661 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 9662 9663 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 9664 return nullptr; 9665 9666 Target->setSupportedOpenCLOpts(); 9667 Target->setOpenCLExtensionOpts(); 9668 9669 if (!Target->validateTarget(Diags)) 9670 return nullptr; 9671 9672 return Target.release(); 9673 } 9674