1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/TargetParser.h" 31 #include <algorithm> 32 #include <memory> 33 34 using namespace clang; 35 36 //===----------------------------------------------------------------------===// 37 // Common code shared among targets. 38 //===----------------------------------------------------------------------===// 39 40 /// DefineStd - Define a macro name and standard variants. For example if 41 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 42 /// when in GNU mode. 43 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 44 const LangOptions &Opts) { 45 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 46 47 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 48 // in the user's namespace. 49 if (Opts.GNUMode) 50 Builder.defineMacro(MacroName); 51 52 // Define __unix. 53 Builder.defineMacro("__" + MacroName); 54 55 // Define __unix__. 56 Builder.defineMacro("__" + MacroName + "__"); 57 } 58 59 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 60 bool Tuning = true) { 61 Builder.defineMacro("__" + CPUName); 62 Builder.defineMacro("__" + CPUName + "__"); 63 if (Tuning) 64 Builder.defineMacro("__tune_" + CPUName + "__"); 65 } 66 67 //===----------------------------------------------------------------------===// 68 // Defines specific to certain operating systems. 69 //===----------------------------------------------------------------------===// 70 71 namespace { 72 template<typename TgtInfo> 73 class OSTargetInfo : public TgtInfo { 74 protected: 75 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 76 MacroBuilder &Builder) const=0; 77 public: 78 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 79 void getTargetDefines(const LangOptions &Opts, 80 MacroBuilder &Builder) const override { 81 TgtInfo::getTargetDefines(Opts, Builder); 82 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 83 } 84 85 }; 86 87 // CloudABI Target 88 template <typename Target> 89 class CloudABITargetInfo : public OSTargetInfo<Target> { 90 protected: 91 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 92 MacroBuilder &Builder) const override { 93 Builder.defineMacro("__CloudABI__"); 94 Builder.defineMacro("__ELF__"); 95 96 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 97 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 98 Builder.defineMacro("__STDC_UTF_16__"); 99 Builder.defineMacro("__STDC_UTF_32__"); 100 } 101 102 public: 103 CloudABITargetInfo(const llvm::Triple &Triple) 104 : OSTargetInfo<Target>(Triple) { 105 this->UserLabelPrefix = ""; 106 } 107 }; 108 109 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 110 const llvm::Triple &Triple, 111 StringRef &PlatformName, 112 VersionTuple &PlatformMinVersion) { 113 Builder.defineMacro("__APPLE_CC__", "6000"); 114 Builder.defineMacro("__APPLE__"); 115 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 116 // AddressSanitizer doesn't play well with source fortification, which is on 117 // by default on Darwin. 118 if (Opts.Sanitize.has(SanitizerKind::Address)) 119 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 120 121 if (!Opts.ObjCAutoRefCount) { 122 // __weak is always defined, for use in blocks and with objc pointers. 123 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 124 125 // Darwin defines __strong even in C mode (just to nothing). 126 if (Opts.getGC() != LangOptions::NonGC) 127 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 128 else 129 Builder.defineMacro("__strong", ""); 130 131 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 132 // allow this in C, since one might have block pointers in structs that 133 // are used in pure C code and in Objective-C ARC. 134 Builder.defineMacro("__unsafe_unretained", ""); 135 } 136 137 if (Opts.Static) 138 Builder.defineMacro("__STATIC__"); 139 else 140 Builder.defineMacro("__DYNAMIC__"); 141 142 if (Opts.POSIXThreads) 143 Builder.defineMacro("_REENTRANT"); 144 145 // Get the platform type and version number from the triple. 146 unsigned Maj, Min, Rev; 147 if (Triple.isMacOSX()) { 148 Triple.getMacOSXVersion(Maj, Min, Rev); 149 PlatformName = "macosx"; 150 } else { 151 Triple.getOSVersion(Maj, Min, Rev); 152 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 153 } 154 155 // If -target arch-pc-win32-macho option specified, we're 156 // generating code for Win32 ABI. No need to emit 157 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 158 if (PlatformName == "win32") { 159 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 160 return; 161 } 162 163 // Set the appropriate OS version define. 164 if (Triple.isiOS()) { 165 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 166 char Str[6]; 167 Str[0] = '0' + Maj; 168 Str[1] = '0' + (Min / 10); 169 Str[2] = '0' + (Min % 10); 170 Str[3] = '0' + (Rev / 10); 171 Str[4] = '0' + (Rev % 10); 172 Str[5] = '\0'; 173 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str); 174 } else if (Triple.isMacOSX()) { 175 // Note that the Driver allows versions which aren't representable in the 176 // define (because we only get a single digit for the minor and micro 177 // revision numbers). So, we limit them to the maximum representable 178 // version. 179 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 180 char Str[7]; 181 if (Maj < 10 || (Maj == 10 && Min < 10)) { 182 Str[0] = '0' + (Maj / 10); 183 Str[1] = '0' + (Maj % 10); 184 Str[2] = '0' + std::min(Min, 9U); 185 Str[3] = '0' + std::min(Rev, 9U); 186 Str[4] = '\0'; 187 } else { 188 // Handle versions > 10.9. 189 Str[0] = '0' + (Maj / 10); 190 Str[1] = '0' + (Maj % 10); 191 Str[2] = '0' + (Min / 10); 192 Str[3] = '0' + (Min % 10); 193 Str[4] = '0' + (Rev / 10); 194 Str[5] = '0' + (Rev % 10); 195 Str[6] = '\0'; 196 } 197 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 198 } 199 200 // Tell users about the kernel if there is one. 201 if (Triple.isOSDarwin()) 202 Builder.defineMacro("__MACH__"); 203 204 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 205 } 206 207 template<typename Target> 208 class DarwinTargetInfo : public OSTargetInfo<Target> { 209 protected: 210 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 211 MacroBuilder &Builder) const override { 212 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 213 this->PlatformMinVersion); 214 } 215 216 public: 217 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 218 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 219 this->MCountName = "\01mcount"; 220 } 221 222 std::string isValidSectionSpecifier(StringRef SR) const override { 223 // Let MCSectionMachO validate this. 224 StringRef Segment, Section; 225 unsigned TAA, StubSize; 226 bool HasTAA; 227 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 228 TAA, HasTAA, StubSize); 229 } 230 231 const char *getStaticInitSectionSpecifier() const override { 232 // FIXME: We should return 0 when building kexts. 233 return "__TEXT,__StaticInit,regular,pure_instructions"; 234 } 235 236 /// Darwin does not support protected visibility. Darwin's "default" 237 /// is very similar to ELF's "protected"; Darwin requires a "weak" 238 /// attribute on declarations that can be dynamically replaced. 239 bool hasProtectedVisibility() const override { 240 return false; 241 } 242 }; 243 244 245 // DragonFlyBSD Target 246 template<typename Target> 247 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 248 protected: 249 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 250 MacroBuilder &Builder) const override { 251 // DragonFly defines; list based off of gcc output 252 Builder.defineMacro("__DragonFly__"); 253 Builder.defineMacro("__DragonFly_cc_version", "100001"); 254 Builder.defineMacro("__ELF__"); 255 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 256 Builder.defineMacro("__tune_i386__"); 257 DefineStd(Builder, "unix", Opts); 258 } 259 public: 260 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 261 : OSTargetInfo<Target>(Triple) { 262 this->UserLabelPrefix = ""; 263 264 switch (Triple.getArch()) { 265 default: 266 case llvm::Triple::x86: 267 case llvm::Triple::x86_64: 268 this->MCountName = ".mcount"; 269 break; 270 } 271 } 272 }; 273 274 // FreeBSD Target 275 template<typename Target> 276 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 277 protected: 278 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 279 MacroBuilder &Builder) const override { 280 // FreeBSD defines; list based off of gcc output 281 282 unsigned Release = Triple.getOSMajorVersion(); 283 if (Release == 0U) 284 Release = 8; 285 286 Builder.defineMacro("__FreeBSD__", Twine(Release)); 287 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 288 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 289 DefineStd(Builder, "unix", Opts); 290 Builder.defineMacro("__ELF__"); 291 292 // On FreeBSD, wchar_t contains the number of the code point as 293 // used by the character set of the locale. These character sets are 294 // not necessarily a superset of ASCII. 295 // 296 // FIXME: This is wrong; the macro refers to the numerical values 297 // of wchar_t *literals*, which are not locale-dependent. However, 298 // FreeBSD systems apparently depend on us getting this wrong, and 299 // setting this to 1 is conforming even if all the basic source 300 // character literals have the same encoding as char and wchar_t. 301 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 302 } 303 public: 304 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 305 this->UserLabelPrefix = ""; 306 307 switch (Triple.getArch()) { 308 default: 309 case llvm::Triple::x86: 310 case llvm::Triple::x86_64: 311 this->MCountName = ".mcount"; 312 break; 313 case llvm::Triple::mips: 314 case llvm::Triple::mipsel: 315 case llvm::Triple::ppc: 316 case llvm::Triple::ppc64: 317 case llvm::Triple::ppc64le: 318 this->MCountName = "_mcount"; 319 break; 320 case llvm::Triple::arm: 321 this->MCountName = "__mcount"; 322 break; 323 } 324 } 325 }; 326 327 // GNU/kFreeBSD Target 328 template<typename Target> 329 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 330 protected: 331 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 332 MacroBuilder &Builder) const override { 333 // GNU/kFreeBSD defines; list based off of gcc output 334 335 DefineStd(Builder, "unix", Opts); 336 Builder.defineMacro("__FreeBSD_kernel__"); 337 Builder.defineMacro("__GLIBC__"); 338 Builder.defineMacro("__ELF__"); 339 if (Opts.POSIXThreads) 340 Builder.defineMacro("_REENTRANT"); 341 if (Opts.CPlusPlus) 342 Builder.defineMacro("_GNU_SOURCE"); 343 } 344 public: 345 KFreeBSDTargetInfo(const llvm::Triple &Triple) 346 : OSTargetInfo<Target>(Triple) { 347 this->UserLabelPrefix = ""; 348 } 349 }; 350 351 // Minix Target 352 template<typename Target> 353 class MinixTargetInfo : public OSTargetInfo<Target> { 354 protected: 355 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 356 MacroBuilder &Builder) const override { 357 // Minix defines 358 359 Builder.defineMacro("__minix", "3"); 360 Builder.defineMacro("_EM_WSIZE", "4"); 361 Builder.defineMacro("_EM_PSIZE", "4"); 362 Builder.defineMacro("_EM_SSIZE", "2"); 363 Builder.defineMacro("_EM_LSIZE", "4"); 364 Builder.defineMacro("_EM_FSIZE", "4"); 365 Builder.defineMacro("_EM_DSIZE", "8"); 366 Builder.defineMacro("__ELF__"); 367 DefineStd(Builder, "unix", Opts); 368 } 369 public: 370 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 371 this->UserLabelPrefix = ""; 372 } 373 }; 374 375 // Linux target 376 template<typename Target> 377 class LinuxTargetInfo : public OSTargetInfo<Target> { 378 protected: 379 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 380 MacroBuilder &Builder) const override { 381 // Linux defines; list based off of gcc output 382 DefineStd(Builder, "unix", Opts); 383 DefineStd(Builder, "linux", Opts); 384 Builder.defineMacro("__gnu_linux__"); 385 Builder.defineMacro("__ELF__"); 386 if (Triple.isAndroid()) { 387 Builder.defineMacro("__ANDROID__", "1"); 388 unsigned Maj, Min, Rev; 389 Triple.getEnvironmentVersion(Maj, Min, Rev); 390 this->PlatformName = "android"; 391 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 392 } 393 if (Opts.POSIXThreads) 394 Builder.defineMacro("_REENTRANT"); 395 if (Opts.CPlusPlus) 396 Builder.defineMacro("_GNU_SOURCE"); 397 } 398 public: 399 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 400 this->UserLabelPrefix = ""; 401 this->WIntType = TargetInfo::UnsignedInt; 402 403 switch (Triple.getArch()) { 404 default: 405 break; 406 case llvm::Triple::ppc: 407 case llvm::Triple::ppc64: 408 case llvm::Triple::ppc64le: 409 this->MCountName = "_mcount"; 410 break; 411 } 412 } 413 414 const char *getStaticInitSectionSpecifier() const override { 415 return ".text.startup"; 416 } 417 }; 418 419 // NetBSD Target 420 template<typename Target> 421 class NetBSDTargetInfo : public OSTargetInfo<Target> { 422 protected: 423 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 424 MacroBuilder &Builder) const override { 425 // NetBSD defines; list based off of gcc output 426 Builder.defineMacro("__NetBSD__"); 427 Builder.defineMacro("__unix__"); 428 Builder.defineMacro("__ELF__"); 429 if (Opts.POSIXThreads) 430 Builder.defineMacro("_POSIX_THREADS"); 431 432 switch (Triple.getArch()) { 433 default: 434 break; 435 case llvm::Triple::arm: 436 case llvm::Triple::armeb: 437 case llvm::Triple::thumb: 438 case llvm::Triple::thumbeb: 439 Builder.defineMacro("__ARM_DWARF_EH__"); 440 break; 441 } 442 } 443 public: 444 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 445 this->UserLabelPrefix = ""; 446 this->MCountName = "_mcount"; 447 } 448 }; 449 450 // OpenBSD Target 451 template<typename Target> 452 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 453 protected: 454 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 455 MacroBuilder &Builder) const override { 456 // OpenBSD defines; list based off of gcc output 457 458 Builder.defineMacro("__OpenBSD__"); 459 DefineStd(Builder, "unix", Opts); 460 Builder.defineMacro("__ELF__"); 461 if (Opts.POSIXThreads) 462 Builder.defineMacro("_REENTRANT"); 463 } 464 public: 465 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 466 this->UserLabelPrefix = ""; 467 this->TLSSupported = false; 468 469 switch (Triple.getArch()) { 470 default: 471 case llvm::Triple::x86: 472 case llvm::Triple::x86_64: 473 case llvm::Triple::arm: 474 case llvm::Triple::sparc: 475 this->MCountName = "__mcount"; 476 break; 477 case llvm::Triple::mips64: 478 case llvm::Triple::mips64el: 479 case llvm::Triple::ppc: 480 case llvm::Triple::sparcv9: 481 this->MCountName = "_mcount"; 482 break; 483 } 484 } 485 }; 486 487 // Bitrig Target 488 template<typename Target> 489 class BitrigTargetInfo : public OSTargetInfo<Target> { 490 protected: 491 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 492 MacroBuilder &Builder) const override { 493 // Bitrig defines; list based off of gcc output 494 495 Builder.defineMacro("__Bitrig__"); 496 DefineStd(Builder, "unix", Opts); 497 Builder.defineMacro("__ELF__"); 498 if (Opts.POSIXThreads) 499 Builder.defineMacro("_REENTRANT"); 500 501 switch (Triple.getArch()) { 502 default: 503 break; 504 case llvm::Triple::arm: 505 case llvm::Triple::armeb: 506 case llvm::Triple::thumb: 507 case llvm::Triple::thumbeb: 508 Builder.defineMacro("__ARM_DWARF_EH__"); 509 break; 510 } 511 } 512 public: 513 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 514 this->UserLabelPrefix = ""; 515 this->MCountName = "__mcount"; 516 } 517 }; 518 519 // PSP Target 520 template<typename Target> 521 class PSPTargetInfo : public OSTargetInfo<Target> { 522 protected: 523 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 524 MacroBuilder &Builder) const override { 525 // PSP defines; list based on the output of the pspdev gcc toolchain. 526 Builder.defineMacro("PSP"); 527 Builder.defineMacro("_PSP"); 528 Builder.defineMacro("__psp__"); 529 Builder.defineMacro("__ELF__"); 530 } 531 public: 532 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 533 this->UserLabelPrefix = ""; 534 } 535 }; 536 537 // PS3 PPU Target 538 template<typename Target> 539 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 540 protected: 541 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 542 MacroBuilder &Builder) const override { 543 // PS3 PPU defines. 544 Builder.defineMacro("__PPC__"); 545 Builder.defineMacro("__PPU__"); 546 Builder.defineMacro("__CELLOS_LV2__"); 547 Builder.defineMacro("__ELF__"); 548 Builder.defineMacro("__LP32__"); 549 Builder.defineMacro("_ARCH_PPC64"); 550 Builder.defineMacro("__powerpc64__"); 551 } 552 public: 553 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 554 this->UserLabelPrefix = ""; 555 this->LongWidth = this->LongAlign = 32; 556 this->PointerWidth = this->PointerAlign = 32; 557 this->IntMaxType = TargetInfo::SignedLongLong; 558 this->Int64Type = TargetInfo::SignedLongLong; 559 this->SizeType = TargetInfo::UnsignedInt; 560 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64"; 561 } 562 }; 563 564 template <typename Target> 565 class PS4OSTargetInfo : public OSTargetInfo<Target> { 566 protected: 567 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 568 MacroBuilder &Builder) const override { 569 Builder.defineMacro("__FreeBSD__", "9"); 570 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 571 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 572 DefineStd(Builder, "unix", Opts); 573 Builder.defineMacro("__ELF__"); 574 Builder.defineMacro("__PS4__"); 575 } 576 public: 577 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 578 this->WCharType = this->UnsignedShort; 579 580 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 581 this->MaxTLSAlign = 256; 582 this->UserLabelPrefix = ""; 583 584 switch (Triple.getArch()) { 585 default: 586 case llvm::Triple::x86_64: 587 this->MCountName = ".mcount"; 588 break; 589 } 590 } 591 }; 592 593 // Solaris target 594 template<typename Target> 595 class SolarisTargetInfo : public OSTargetInfo<Target> { 596 protected: 597 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 598 MacroBuilder &Builder) const override { 599 DefineStd(Builder, "sun", Opts); 600 DefineStd(Builder, "unix", Opts); 601 Builder.defineMacro("__ELF__"); 602 Builder.defineMacro("__svr4__"); 603 Builder.defineMacro("__SVR4"); 604 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 605 // newer, but to 500 for everything else. feature_test.h has a check to 606 // ensure that you are not using C99 with an old version of X/Open or C89 607 // with a new version. 608 if (Opts.C99) 609 Builder.defineMacro("_XOPEN_SOURCE", "600"); 610 else 611 Builder.defineMacro("_XOPEN_SOURCE", "500"); 612 if (Opts.CPlusPlus) 613 Builder.defineMacro("__C99FEATURES__"); 614 Builder.defineMacro("_LARGEFILE_SOURCE"); 615 Builder.defineMacro("_LARGEFILE64_SOURCE"); 616 Builder.defineMacro("__EXTENSIONS__"); 617 Builder.defineMacro("_REENTRANT"); 618 } 619 public: 620 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 621 this->UserLabelPrefix = ""; 622 this->WCharType = this->SignedInt; 623 // FIXME: WIntType should be SignedLong 624 } 625 }; 626 627 // Windows target 628 template<typename Target> 629 class WindowsTargetInfo : public OSTargetInfo<Target> { 630 protected: 631 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 632 MacroBuilder &Builder) const override { 633 Builder.defineMacro("_WIN32"); 634 } 635 void getVisualStudioDefines(const LangOptions &Opts, 636 MacroBuilder &Builder) const { 637 if (Opts.CPlusPlus) { 638 if (Opts.RTTIData) 639 Builder.defineMacro("_CPPRTTI"); 640 641 if (Opts.CXXExceptions) 642 Builder.defineMacro("_CPPUNWIND"); 643 } 644 645 if (Opts.Bool) 646 Builder.defineMacro("__BOOL_DEFINED"); 647 648 if (!Opts.CharIsSigned) 649 Builder.defineMacro("_CHAR_UNSIGNED"); 650 651 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 652 // but it works for now. 653 if (Opts.POSIXThreads) 654 Builder.defineMacro("_MT"); 655 656 if (Opts.MSCompatibilityVersion) { 657 Builder.defineMacro("_MSC_VER", 658 Twine(Opts.MSCompatibilityVersion / 100000)); 659 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 660 // FIXME We cannot encode the revision information into 32-bits 661 Builder.defineMacro("_MSC_BUILD", Twine(1)); 662 663 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 664 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 665 } 666 667 if (Opts.MicrosoftExt) { 668 Builder.defineMacro("_MSC_EXTENSIONS"); 669 670 if (Opts.CPlusPlus11) { 671 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 672 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 673 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 674 } 675 } 676 677 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 678 } 679 680 public: 681 WindowsTargetInfo(const llvm::Triple &Triple) 682 : OSTargetInfo<Target>(Triple) {} 683 }; 684 685 template <typename Target> 686 class NaClTargetInfo : public OSTargetInfo<Target> { 687 protected: 688 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 689 MacroBuilder &Builder) const override { 690 if (Opts.POSIXThreads) 691 Builder.defineMacro("_REENTRANT"); 692 if (Opts.CPlusPlus) 693 Builder.defineMacro("_GNU_SOURCE"); 694 695 DefineStd(Builder, "unix", Opts); 696 Builder.defineMacro("__ELF__"); 697 Builder.defineMacro("__native_client__"); 698 } 699 700 public: 701 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 702 this->UserLabelPrefix = ""; 703 this->LongAlign = 32; 704 this->LongWidth = 32; 705 this->PointerAlign = 32; 706 this->PointerWidth = 32; 707 this->IntMaxType = TargetInfo::SignedLongLong; 708 this->Int64Type = TargetInfo::SignedLongLong; 709 this->DoubleAlign = 64; 710 this->LongDoubleWidth = 64; 711 this->LongDoubleAlign = 64; 712 this->LongLongWidth = 64; 713 this->LongLongAlign = 64; 714 this->SizeType = TargetInfo::UnsignedInt; 715 this->PtrDiffType = TargetInfo::SignedInt; 716 this->IntPtrType = TargetInfo::SignedInt; 717 // RegParmMax is inherited from the underlying architecture 718 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 719 if (Triple.getArch() == llvm::Triple::arm) { 720 // Handled in ARM's setABI(). 721 } else if (Triple.getArch() == llvm::Triple::x86) { 722 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 723 } else if (Triple.getArch() == llvm::Triple::x86_64) { 724 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 725 } else if (Triple.getArch() == llvm::Triple::mipsel) { 726 // Handled on mips' setDataLayoutString. 727 } else { 728 assert(Triple.getArch() == llvm::Triple::le32); 729 this->DataLayoutString = "e-p:32:32-i64:64"; 730 } 731 } 732 }; 733 734 // WebAssembly target 735 template <typename Target> 736 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 737 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 738 MacroBuilder &Builder) const final { 739 // A common platform macro. 740 if (Opts.POSIXThreads) 741 Builder.defineMacro("_REENTRANT"); 742 // Follow g++ convention and predefine _GNU_SOURCE for C++. 743 if (Opts.CPlusPlus) 744 Builder.defineMacro("_GNU_SOURCE"); 745 } 746 747 // As an optimization, group static init code together in a section. 748 const char *getStaticInitSectionSpecifier() const final { 749 return ".text.__startup"; 750 } 751 752 public: 753 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 754 : OSTargetInfo<Target>(Triple) { 755 this->MCountName = "__mcount"; 756 this->UserLabelPrefix = ""; 757 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 758 } 759 }; 760 761 //===----------------------------------------------------------------------===// 762 // Specific target implementations. 763 //===----------------------------------------------------------------------===// 764 765 // PPC abstract base class 766 class PPCTargetInfo : public TargetInfo { 767 static const Builtin::Info BuiltinInfo[]; 768 static const char * const GCCRegNames[]; 769 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 770 std::string CPU; 771 772 // Target cpu features. 773 bool HasVSX; 774 bool HasP8Vector; 775 bool HasP8Crypto; 776 bool HasDirectMove; 777 bool HasQPX; 778 bool HasHTM; 779 bool HasBPERMD; 780 bool HasExtDiv; 781 782 protected: 783 std::string ABI; 784 785 public: 786 PPCTargetInfo(const llvm::Triple &Triple) 787 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 788 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 789 HasBPERMD(false), HasExtDiv(false) { 790 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 791 SimdDefaultAlign = 128; 792 LongDoubleWidth = LongDoubleAlign = 128; 793 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 794 } 795 796 /// \brief Flags for architecture specific defines. 797 typedef enum { 798 ArchDefineNone = 0, 799 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 800 ArchDefinePpcgr = 1 << 1, 801 ArchDefinePpcsq = 1 << 2, 802 ArchDefine440 = 1 << 3, 803 ArchDefine603 = 1 << 4, 804 ArchDefine604 = 1 << 5, 805 ArchDefinePwr4 = 1 << 6, 806 ArchDefinePwr5 = 1 << 7, 807 ArchDefinePwr5x = 1 << 8, 808 ArchDefinePwr6 = 1 << 9, 809 ArchDefinePwr6x = 1 << 10, 810 ArchDefinePwr7 = 1 << 11, 811 ArchDefinePwr8 = 1 << 12, 812 ArchDefineA2 = 1 << 13, 813 ArchDefineA2q = 1 << 14 814 } ArchDefineTypes; 815 816 // Note: GCC recognizes the following additional cpus: 817 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 818 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 819 // titan, rs64. 820 bool setCPU(const std::string &Name) override { 821 bool CPUKnown = llvm::StringSwitch<bool>(Name) 822 .Case("generic", true) 823 .Case("440", true) 824 .Case("450", true) 825 .Case("601", true) 826 .Case("602", true) 827 .Case("603", true) 828 .Case("603e", true) 829 .Case("603ev", true) 830 .Case("604", true) 831 .Case("604e", true) 832 .Case("620", true) 833 .Case("630", true) 834 .Case("g3", true) 835 .Case("7400", true) 836 .Case("g4", true) 837 .Case("7450", true) 838 .Case("g4+", true) 839 .Case("750", true) 840 .Case("970", true) 841 .Case("g5", true) 842 .Case("a2", true) 843 .Case("a2q", true) 844 .Case("e500mc", true) 845 .Case("e5500", true) 846 .Case("power3", true) 847 .Case("pwr3", true) 848 .Case("power4", true) 849 .Case("pwr4", true) 850 .Case("power5", true) 851 .Case("pwr5", true) 852 .Case("power5x", true) 853 .Case("pwr5x", true) 854 .Case("power6", true) 855 .Case("pwr6", true) 856 .Case("power6x", true) 857 .Case("pwr6x", true) 858 .Case("power7", true) 859 .Case("pwr7", true) 860 .Case("power8", true) 861 .Case("pwr8", true) 862 .Case("powerpc", true) 863 .Case("ppc", true) 864 .Case("powerpc64", true) 865 .Case("ppc64", true) 866 .Case("powerpc64le", true) 867 .Case("ppc64le", true) 868 .Default(false); 869 870 if (CPUKnown) 871 CPU = Name; 872 873 return CPUKnown; 874 } 875 876 877 StringRef getABI() const override { return ABI; } 878 879 void getTargetBuiltins(const Builtin::Info *&Records, 880 unsigned &NumRecords) const override { 881 Records = BuiltinInfo; 882 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 883 } 884 885 bool isCLZForZeroUndef() const override { return false; } 886 887 void getTargetDefines(const LangOptions &Opts, 888 MacroBuilder &Builder) const override; 889 890 bool 891 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 892 StringRef CPU, 893 const std::vector<std::string> &FeaturesVec) const override; 894 895 bool handleTargetFeatures(std::vector<std::string> &Features, 896 DiagnosticsEngine &Diags) override; 897 bool hasFeature(StringRef Feature) const override; 898 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 899 bool Enabled) const override; 900 901 void getGCCRegNames(const char * const *&Names, 902 unsigned &NumNames) const override; 903 void getGCCRegAliases(const GCCRegAlias *&Aliases, 904 unsigned &NumAliases) const override; 905 bool validateAsmConstraint(const char *&Name, 906 TargetInfo::ConstraintInfo &Info) const override { 907 switch (*Name) { 908 default: return false; 909 case 'O': // Zero 910 break; 911 case 'b': // Base register 912 case 'f': // Floating point register 913 Info.setAllowsRegister(); 914 break; 915 // FIXME: The following are added to allow parsing. 916 // I just took a guess at what the actions should be. 917 // Also, is more specific checking needed? I.e. specific registers? 918 case 'd': // Floating point register (containing 64-bit value) 919 case 'v': // Altivec vector register 920 Info.setAllowsRegister(); 921 break; 922 case 'w': 923 switch (Name[1]) { 924 case 'd':// VSX vector register to hold vector double data 925 case 'f':// VSX vector register to hold vector float data 926 case 's':// VSX vector register to hold scalar float data 927 case 'a':// Any VSX register 928 case 'c':// An individual CR bit 929 break; 930 default: 931 return false; 932 } 933 Info.setAllowsRegister(); 934 Name++; // Skip over 'w'. 935 break; 936 case 'h': // `MQ', `CTR', or `LINK' register 937 case 'q': // `MQ' register 938 case 'c': // `CTR' register 939 case 'l': // `LINK' register 940 case 'x': // `CR' register (condition register) number 0 941 case 'y': // `CR' register (condition register) 942 case 'z': // `XER[CA]' carry bit (part of the XER register) 943 Info.setAllowsRegister(); 944 break; 945 case 'I': // Signed 16-bit constant 946 case 'J': // Unsigned 16-bit constant shifted left 16 bits 947 // (use `L' instead for SImode constants) 948 case 'K': // Unsigned 16-bit constant 949 case 'L': // Signed 16-bit constant shifted left 16 bits 950 case 'M': // Constant larger than 31 951 case 'N': // Exact power of 2 952 case 'P': // Constant whose negation is a signed 16-bit constant 953 case 'G': // Floating point constant that can be loaded into a 954 // register with one instruction per word 955 case 'H': // Integer/Floating point constant that can be loaded 956 // into a register using three instructions 957 break; 958 case 'm': // Memory operand. Note that on PowerPC targets, m can 959 // include addresses that update the base register. It 960 // is therefore only safe to use `m' in an asm statement 961 // if that asm statement accesses the operand exactly once. 962 // The asm statement must also use `%U<opno>' as a 963 // placeholder for the "update" flag in the corresponding 964 // load or store instruction. For example: 965 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 966 // is correct but: 967 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 968 // is not. Use es rather than m if you don't want the base 969 // register to be updated. 970 case 'e': 971 if (Name[1] != 's') 972 return false; 973 // es: A "stable" memory operand; that is, one which does not 974 // include any automodification of the base register. Unlike 975 // `m', this constraint can be used in asm statements that 976 // might access the operand several times, or that might not 977 // access it at all. 978 Info.setAllowsMemory(); 979 Name++; // Skip over 'e'. 980 break; 981 case 'Q': // Memory operand that is an offset from a register (it is 982 // usually better to use `m' or `es' in asm statements) 983 case 'Z': // Memory operand that is an indexed or indirect from a 984 // register (it is usually better to use `m' or `es' in 985 // asm statements) 986 Info.setAllowsMemory(); 987 Info.setAllowsRegister(); 988 break; 989 case 'R': // AIX TOC entry 990 case 'a': // Address operand that is an indexed or indirect from a 991 // register (`p' is preferable for asm statements) 992 case 'S': // Constant suitable as a 64-bit mask operand 993 case 'T': // Constant suitable as a 32-bit mask operand 994 case 'U': // System V Release 4 small data area reference 995 case 't': // AND masks that can be performed by two rldic{l, r} 996 // instructions 997 case 'W': // Vector constant that does not require memory 998 case 'j': // Vector constant that is all zeros. 999 break; 1000 // End FIXME. 1001 } 1002 return true; 1003 } 1004 std::string convertConstraint(const char *&Constraint) const override { 1005 std::string R; 1006 switch (*Constraint) { 1007 case 'e': 1008 case 'w': 1009 // Two-character constraint; add "^" hint for later parsing. 1010 R = std::string("^") + std::string(Constraint, 2); 1011 Constraint++; 1012 break; 1013 default: 1014 return TargetInfo::convertConstraint(Constraint); 1015 } 1016 return R; 1017 } 1018 const char *getClobbers() const override { 1019 return ""; 1020 } 1021 int getEHDataRegisterNumber(unsigned RegNo) const override { 1022 if (RegNo == 0) return 3; 1023 if (RegNo == 1) return 4; 1024 return -1; 1025 } 1026 1027 bool hasSjLjLowering() const override { 1028 return true; 1029 } 1030 1031 bool useFloat128ManglingForLongDouble() const override { 1032 return LongDoubleWidth == 128 && 1033 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1034 getTriple().isOSBinFormatELF(); 1035 } 1036 }; 1037 1038 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1039 #define BUILTIN(ID, TYPE, ATTRS) \ 1040 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1041 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1042 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1043 #include "clang/Basic/BuiltinsPPC.def" 1044 }; 1045 1046 /// handleTargetFeatures - Perform initialization based on the user 1047 /// configured set of features. 1048 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1049 DiagnosticsEngine &Diags) { 1050 for (const auto &Feature : Features) { 1051 if (Feature == "+vsx") { 1052 HasVSX = true; 1053 } else if (Feature == "+bpermd") { 1054 HasBPERMD = true; 1055 } else if (Feature == "+extdiv") { 1056 HasExtDiv = true; 1057 } else if (Feature == "+power8-vector") { 1058 HasP8Vector = true; 1059 } else if (Feature == "+crypto") { 1060 HasP8Crypto = true; 1061 } else if (Feature == "+direct-move") { 1062 HasDirectMove = true; 1063 } else if (Feature == "+qpx") { 1064 HasQPX = true; 1065 } else if (Feature == "+htm") { 1066 HasHTM = true; 1067 } 1068 // TODO: Finish this list and add an assert that we've handled them 1069 // all. 1070 } 1071 1072 return true; 1073 } 1074 1075 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1076 /// #defines that are not tied to a specific subtarget. 1077 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1078 MacroBuilder &Builder) const { 1079 // Target identification. 1080 Builder.defineMacro("__ppc__"); 1081 Builder.defineMacro("__PPC__"); 1082 Builder.defineMacro("_ARCH_PPC"); 1083 Builder.defineMacro("__powerpc__"); 1084 Builder.defineMacro("__POWERPC__"); 1085 if (PointerWidth == 64) { 1086 Builder.defineMacro("_ARCH_PPC64"); 1087 Builder.defineMacro("__powerpc64__"); 1088 Builder.defineMacro("__ppc64__"); 1089 Builder.defineMacro("__PPC64__"); 1090 } 1091 1092 // Target properties. 1093 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1094 Builder.defineMacro("_LITTLE_ENDIAN"); 1095 } else { 1096 if (getTriple().getOS() != llvm::Triple::NetBSD && 1097 getTriple().getOS() != llvm::Triple::OpenBSD) 1098 Builder.defineMacro("_BIG_ENDIAN"); 1099 } 1100 1101 // ABI options. 1102 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1103 Builder.defineMacro("_CALL_ELF", "1"); 1104 if (ABI == "elfv2") 1105 Builder.defineMacro("_CALL_ELF", "2"); 1106 1107 // Subtarget options. 1108 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1109 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1110 1111 // FIXME: Should be controlled by command line option. 1112 if (LongDoubleWidth == 128) 1113 Builder.defineMacro("__LONG_DOUBLE_128__"); 1114 1115 if (Opts.AltiVec) { 1116 Builder.defineMacro("__VEC__", "10206"); 1117 Builder.defineMacro("__ALTIVEC__"); 1118 } 1119 1120 // CPU identification. 1121 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1122 .Case("440", ArchDefineName) 1123 .Case("450", ArchDefineName | ArchDefine440) 1124 .Case("601", ArchDefineName) 1125 .Case("602", ArchDefineName | ArchDefinePpcgr) 1126 .Case("603", ArchDefineName | ArchDefinePpcgr) 1127 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1128 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1129 .Case("604", ArchDefineName | ArchDefinePpcgr) 1130 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1131 .Case("620", ArchDefineName | ArchDefinePpcgr) 1132 .Case("630", ArchDefineName | ArchDefinePpcgr) 1133 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1134 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1135 .Case("750", ArchDefineName | ArchDefinePpcgr) 1136 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1137 | ArchDefinePpcsq) 1138 .Case("a2", ArchDefineA2) 1139 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1140 .Case("pwr3", ArchDefinePpcgr) 1141 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1142 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1143 | ArchDefinePpcsq) 1144 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1145 | ArchDefinePpcgr | ArchDefinePpcsq) 1146 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1147 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1148 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1149 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1150 | ArchDefinePpcsq) 1151 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1152 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1153 | ArchDefinePpcgr | ArchDefinePpcsq) 1154 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1155 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1156 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1157 .Case("power3", ArchDefinePpcgr) 1158 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1159 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1160 | ArchDefinePpcsq) 1161 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1162 | ArchDefinePpcgr | ArchDefinePpcsq) 1163 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1164 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1165 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1166 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1167 | ArchDefinePpcsq) 1168 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1169 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1170 | ArchDefinePpcgr | ArchDefinePpcsq) 1171 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1172 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1173 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1174 .Default(ArchDefineNone); 1175 1176 if (defs & ArchDefineName) 1177 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1178 if (defs & ArchDefinePpcgr) 1179 Builder.defineMacro("_ARCH_PPCGR"); 1180 if (defs & ArchDefinePpcsq) 1181 Builder.defineMacro("_ARCH_PPCSQ"); 1182 if (defs & ArchDefine440) 1183 Builder.defineMacro("_ARCH_440"); 1184 if (defs & ArchDefine603) 1185 Builder.defineMacro("_ARCH_603"); 1186 if (defs & ArchDefine604) 1187 Builder.defineMacro("_ARCH_604"); 1188 if (defs & ArchDefinePwr4) 1189 Builder.defineMacro("_ARCH_PWR4"); 1190 if (defs & ArchDefinePwr5) 1191 Builder.defineMacro("_ARCH_PWR5"); 1192 if (defs & ArchDefinePwr5x) 1193 Builder.defineMacro("_ARCH_PWR5X"); 1194 if (defs & ArchDefinePwr6) 1195 Builder.defineMacro("_ARCH_PWR6"); 1196 if (defs & ArchDefinePwr6x) 1197 Builder.defineMacro("_ARCH_PWR6X"); 1198 if (defs & ArchDefinePwr7) 1199 Builder.defineMacro("_ARCH_PWR7"); 1200 if (defs & ArchDefinePwr8) 1201 Builder.defineMacro("_ARCH_PWR8"); 1202 if (defs & ArchDefineA2) 1203 Builder.defineMacro("_ARCH_A2"); 1204 if (defs & ArchDefineA2q) { 1205 Builder.defineMacro("_ARCH_A2Q"); 1206 Builder.defineMacro("_ARCH_QP"); 1207 } 1208 1209 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1210 Builder.defineMacro("__bg__"); 1211 Builder.defineMacro("__THW_BLUEGENE__"); 1212 Builder.defineMacro("__bgq__"); 1213 Builder.defineMacro("__TOS_BGQ__"); 1214 } 1215 1216 if (HasVSX) 1217 Builder.defineMacro("__VSX__"); 1218 if (HasP8Vector) 1219 Builder.defineMacro("__POWER8_VECTOR__"); 1220 if (HasP8Crypto) 1221 Builder.defineMacro("__CRYPTO__"); 1222 if (HasHTM) 1223 Builder.defineMacro("__HTM__"); 1224 1225 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1226 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1227 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1228 if (PointerWidth == 64) 1229 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1230 1231 // FIXME: The following are not yet generated here by Clang, but are 1232 // generated by GCC: 1233 // 1234 // _SOFT_FLOAT_ 1235 // __RECIP_PRECISION__ 1236 // __APPLE_ALTIVEC__ 1237 // __RECIP__ 1238 // __RECIPF__ 1239 // __RSQRTE__ 1240 // __RSQRTEF__ 1241 // _SOFT_DOUBLE_ 1242 // __NO_LWSYNC__ 1243 // __HAVE_BSWAP__ 1244 // __LONGDOUBLE128 1245 // __CMODEL_MEDIUM__ 1246 // __CMODEL_LARGE__ 1247 // _CALL_SYSV 1248 // _CALL_DARWIN 1249 // __NO_FPRS__ 1250 } 1251 1252 // Handle explicit options being passed to the compiler here: if we've 1253 // explicitly turned off vsx and turned on power8-vector or direct-move then 1254 // go ahead and error since the customer has expressed a somewhat incompatible 1255 // set of options. 1256 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1257 const std::vector<std::string> &FeaturesVec) { 1258 1259 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1260 FeaturesVec.end()) { 1261 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1262 FeaturesVec.end()) { 1263 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1264 << "-mno-vsx"; 1265 return false; 1266 } 1267 1268 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1269 FeaturesVec.end()) { 1270 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1271 << "-mno-vsx"; 1272 return false; 1273 } 1274 } 1275 1276 return true; 1277 } 1278 1279 bool PPCTargetInfo::initFeatureMap( 1280 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1281 const std::vector<std::string> &FeaturesVec) const { 1282 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1283 .Case("7400", true) 1284 .Case("g4", true) 1285 .Case("7450", true) 1286 .Case("g4+", true) 1287 .Case("970", true) 1288 .Case("g5", true) 1289 .Case("pwr6", true) 1290 .Case("pwr7", true) 1291 .Case("pwr8", true) 1292 .Case("ppc64", true) 1293 .Case("ppc64le", true) 1294 .Default(false); 1295 1296 Features["qpx"] = (CPU == "a2q"); 1297 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1298 .Case("ppc64le", true) 1299 .Case("pwr8", true) 1300 .Default(false); 1301 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1302 .Case("ppc64le", true) 1303 .Case("pwr8", true) 1304 .Default(false); 1305 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1306 .Case("ppc64le", true) 1307 .Case("pwr8", true) 1308 .Case("pwr7", true) 1309 .Default(false); 1310 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1311 .Case("ppc64le", true) 1312 .Case("pwr8", true) 1313 .Case("pwr7", true) 1314 .Default(false); 1315 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1316 .Case("ppc64le", true) 1317 .Case("pwr8", true) 1318 .Default(false); 1319 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1320 .Case("ppc64le", true) 1321 .Case("pwr8", true) 1322 .Case("pwr7", true) 1323 .Default(false); 1324 1325 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1326 return false; 1327 1328 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1329 } 1330 1331 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1332 return llvm::StringSwitch<bool>(Feature) 1333 .Case("powerpc", true) 1334 .Case("vsx", HasVSX) 1335 .Case("power8-vector", HasP8Vector) 1336 .Case("crypto", HasP8Crypto) 1337 .Case("direct-move", HasDirectMove) 1338 .Case("qpx", HasQPX) 1339 .Case("htm", HasHTM) 1340 .Case("bpermd", HasBPERMD) 1341 .Case("extdiv", HasExtDiv) 1342 .Default(false); 1343 } 1344 1345 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1346 StringRef Name, bool Enabled) const { 1347 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1348 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1349 // incompatible options. 1350 if (Enabled) { 1351 if (Name == "vsx") { 1352 Features[Name] = true; 1353 } else if (Name == "direct-move") { 1354 Features[Name] = Features["vsx"] = true; 1355 } else if (Name == "power8-vector") { 1356 Features[Name] = Features["vsx"] = true; 1357 } else { 1358 Features[Name] = true; 1359 } 1360 } else { 1361 if (Name == "vsx") { 1362 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1363 false; 1364 } else { 1365 Features[Name] = false; 1366 } 1367 } 1368 } 1369 1370 const char * const PPCTargetInfo::GCCRegNames[] = { 1371 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1372 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1373 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1374 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1375 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1376 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1377 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1378 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1379 "mq", "lr", "ctr", "ap", 1380 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1381 "xer", 1382 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1383 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1384 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1385 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1386 "vrsave", "vscr", 1387 "spe_acc", "spefscr", 1388 "sfp" 1389 }; 1390 1391 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1392 unsigned &NumNames) const { 1393 Names = GCCRegNames; 1394 NumNames = llvm::array_lengthof(GCCRegNames); 1395 } 1396 1397 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1398 // While some of these aliases do map to different registers 1399 // they still share the same register name. 1400 { { "0" }, "r0" }, 1401 { { "1"}, "r1" }, 1402 { { "2" }, "r2" }, 1403 { { "3" }, "r3" }, 1404 { { "4" }, "r4" }, 1405 { { "5" }, "r5" }, 1406 { { "6" }, "r6" }, 1407 { { "7" }, "r7" }, 1408 { { "8" }, "r8" }, 1409 { { "9" }, "r9" }, 1410 { { "10" }, "r10" }, 1411 { { "11" }, "r11" }, 1412 { { "12" }, "r12" }, 1413 { { "13" }, "r13" }, 1414 { { "14" }, "r14" }, 1415 { { "15" }, "r15" }, 1416 { { "16" }, "r16" }, 1417 { { "17" }, "r17" }, 1418 { { "18" }, "r18" }, 1419 { { "19" }, "r19" }, 1420 { { "20" }, "r20" }, 1421 { { "21" }, "r21" }, 1422 { { "22" }, "r22" }, 1423 { { "23" }, "r23" }, 1424 { { "24" }, "r24" }, 1425 { { "25" }, "r25" }, 1426 { { "26" }, "r26" }, 1427 { { "27" }, "r27" }, 1428 { { "28" }, "r28" }, 1429 { { "29" }, "r29" }, 1430 { { "30" }, "r30" }, 1431 { { "31" }, "r31" }, 1432 { { "fr0" }, "f0" }, 1433 { { "fr1" }, "f1" }, 1434 { { "fr2" }, "f2" }, 1435 { { "fr3" }, "f3" }, 1436 { { "fr4" }, "f4" }, 1437 { { "fr5" }, "f5" }, 1438 { { "fr6" }, "f6" }, 1439 { { "fr7" }, "f7" }, 1440 { { "fr8" }, "f8" }, 1441 { { "fr9" }, "f9" }, 1442 { { "fr10" }, "f10" }, 1443 { { "fr11" }, "f11" }, 1444 { { "fr12" }, "f12" }, 1445 { { "fr13" }, "f13" }, 1446 { { "fr14" }, "f14" }, 1447 { { "fr15" }, "f15" }, 1448 { { "fr16" }, "f16" }, 1449 { { "fr17" }, "f17" }, 1450 { { "fr18" }, "f18" }, 1451 { { "fr19" }, "f19" }, 1452 { { "fr20" }, "f20" }, 1453 { { "fr21" }, "f21" }, 1454 { { "fr22" }, "f22" }, 1455 { { "fr23" }, "f23" }, 1456 { { "fr24" }, "f24" }, 1457 { { "fr25" }, "f25" }, 1458 { { "fr26" }, "f26" }, 1459 { { "fr27" }, "f27" }, 1460 { { "fr28" }, "f28" }, 1461 { { "fr29" }, "f29" }, 1462 { { "fr30" }, "f30" }, 1463 { { "fr31" }, "f31" }, 1464 { { "cc" }, "cr0" }, 1465 }; 1466 1467 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1468 unsigned &NumAliases) const { 1469 Aliases = GCCRegAliases; 1470 NumAliases = llvm::array_lengthof(GCCRegAliases); 1471 } 1472 1473 class PPC32TargetInfo : public PPCTargetInfo { 1474 public: 1475 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1476 DataLayoutString = "E-m:e-p:32:32-i64:64-n32"; 1477 1478 switch (getTriple().getOS()) { 1479 case llvm::Triple::Linux: 1480 case llvm::Triple::FreeBSD: 1481 case llvm::Triple::NetBSD: 1482 SizeType = UnsignedInt; 1483 PtrDiffType = SignedInt; 1484 IntPtrType = SignedInt; 1485 break; 1486 default: 1487 break; 1488 } 1489 1490 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1491 LongDoubleWidth = LongDoubleAlign = 64; 1492 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1493 } 1494 1495 // PPC32 supports atomics up to 4 bytes. 1496 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1497 } 1498 1499 BuiltinVaListKind getBuiltinVaListKind() const override { 1500 // This is the ELF definition, and is overridden by the Darwin sub-target 1501 return TargetInfo::PowerABIBuiltinVaList; 1502 } 1503 }; 1504 1505 // Note: ABI differences may eventually require us to have a separate 1506 // TargetInfo for little endian. 1507 class PPC64TargetInfo : public PPCTargetInfo { 1508 public: 1509 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1510 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1511 IntMaxType = SignedLong; 1512 Int64Type = SignedLong; 1513 1514 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1515 DataLayoutString = "e-m:e-i64:64-n32:64"; 1516 ABI = "elfv2"; 1517 } else { 1518 DataLayoutString = "E-m:e-i64:64-n32:64"; 1519 ABI = "elfv1"; 1520 } 1521 1522 switch (getTriple().getOS()) { 1523 case llvm::Triple::FreeBSD: 1524 LongDoubleWidth = LongDoubleAlign = 64; 1525 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1526 break; 1527 case llvm::Triple::NetBSD: 1528 IntMaxType = SignedLongLong; 1529 Int64Type = SignedLongLong; 1530 break; 1531 default: 1532 break; 1533 } 1534 1535 // PPC64 supports atomics up to 8 bytes. 1536 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1537 } 1538 BuiltinVaListKind getBuiltinVaListKind() const override { 1539 return TargetInfo::CharPtrBuiltinVaList; 1540 } 1541 // PPC64 Linux-specific ABI options. 1542 bool setABI(const std::string &Name) override { 1543 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1544 ABI = Name; 1545 return true; 1546 } 1547 return false; 1548 } 1549 }; 1550 1551 class DarwinPPC32TargetInfo : 1552 public DarwinTargetInfo<PPC32TargetInfo> { 1553 public: 1554 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1555 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1556 HasAlignMac68kSupport = true; 1557 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1558 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1559 LongLongAlign = 32; 1560 SuitableAlign = 128; 1561 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32"; 1562 } 1563 BuiltinVaListKind getBuiltinVaListKind() const override { 1564 return TargetInfo::CharPtrBuiltinVaList; 1565 } 1566 }; 1567 1568 class DarwinPPC64TargetInfo : 1569 public DarwinTargetInfo<PPC64TargetInfo> { 1570 public: 1571 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1572 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1573 HasAlignMac68kSupport = true; 1574 SuitableAlign = 128; 1575 DataLayoutString = "E-m:o-i64:64-n32:64"; 1576 } 1577 }; 1578 1579 static const unsigned NVPTXAddrSpaceMap[] = { 1580 1, // opencl_global 1581 3, // opencl_local 1582 4, // opencl_constant 1583 // FIXME: generic has to be added to the target 1584 0, // opencl_generic 1585 1, // cuda_device 1586 4, // cuda_constant 1587 3, // cuda_shared 1588 }; 1589 1590 class NVPTXTargetInfo : public TargetInfo { 1591 static const char *const GCCRegNames[]; 1592 static const Builtin::Info BuiltinInfo[]; 1593 1594 // The GPU profiles supported by the NVPTX backend 1595 enum GPUKind { 1596 GK_NONE, 1597 GK_SM20, 1598 GK_SM21, 1599 GK_SM30, 1600 GK_SM35, 1601 GK_SM37, 1602 } GPU; 1603 1604 public: 1605 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1606 BigEndian = false; 1607 TLSSupported = false; 1608 LongWidth = LongAlign = 64; 1609 AddrSpaceMap = &NVPTXAddrSpaceMap; 1610 UseAddrSpaceMapMangling = true; 1611 // Define available target features 1612 // These must be defined in sorted order! 1613 NoAsmVariants = true; 1614 // Set the default GPU to sm20 1615 GPU = GK_SM20; 1616 } 1617 void getTargetDefines(const LangOptions &Opts, 1618 MacroBuilder &Builder) const override { 1619 Builder.defineMacro("__PTX__"); 1620 Builder.defineMacro("__NVPTX__"); 1621 if (Opts.CUDAIsDevice) { 1622 // Set __CUDA_ARCH__ for the GPU specified. 1623 std::string CUDAArchCode; 1624 switch (GPU) { 1625 case GK_SM20: 1626 CUDAArchCode = "200"; 1627 break; 1628 case GK_SM21: 1629 CUDAArchCode = "210"; 1630 break; 1631 case GK_SM30: 1632 CUDAArchCode = "300"; 1633 break; 1634 case GK_SM35: 1635 CUDAArchCode = "350"; 1636 break; 1637 case GK_SM37: 1638 CUDAArchCode = "370"; 1639 break; 1640 default: 1641 llvm_unreachable("Unhandled target CPU"); 1642 } 1643 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1644 } 1645 } 1646 void getTargetBuiltins(const Builtin::Info *&Records, 1647 unsigned &NumRecords) const override { 1648 Records = BuiltinInfo; 1649 NumRecords = clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin; 1650 } 1651 bool hasFeature(StringRef Feature) const override { 1652 return Feature == "ptx" || Feature == "nvptx"; 1653 } 1654 1655 void getGCCRegNames(const char *const *&Names, 1656 unsigned &NumNames) const override; 1657 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1658 unsigned &NumAliases) const override { 1659 // No aliases. 1660 Aliases = nullptr; 1661 NumAliases = 0; 1662 } 1663 bool validateAsmConstraint(const char *&Name, 1664 TargetInfo::ConstraintInfo &Info) const override { 1665 switch (*Name) { 1666 default: 1667 return false; 1668 case 'c': 1669 case 'h': 1670 case 'r': 1671 case 'l': 1672 case 'f': 1673 case 'd': 1674 Info.setAllowsRegister(); 1675 return true; 1676 } 1677 } 1678 const char *getClobbers() const override { 1679 // FIXME: Is this really right? 1680 return ""; 1681 } 1682 BuiltinVaListKind getBuiltinVaListKind() const override { 1683 // FIXME: implement 1684 return TargetInfo::CharPtrBuiltinVaList; 1685 } 1686 bool setCPU(const std::string &Name) override { 1687 GPU = llvm::StringSwitch<GPUKind>(Name) 1688 .Case("sm_20", GK_SM20) 1689 .Case("sm_21", GK_SM21) 1690 .Case("sm_30", GK_SM30) 1691 .Case("sm_35", GK_SM35) 1692 .Case("sm_37", GK_SM37) 1693 .Default(GK_NONE); 1694 1695 return GPU != GK_NONE; 1696 } 1697 }; 1698 1699 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1700 #define BUILTIN(ID, TYPE, ATTRS) \ 1701 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1702 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1703 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1704 #include "clang/Basic/BuiltinsNVPTX.def" 1705 }; 1706 1707 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1708 1709 void NVPTXTargetInfo::getGCCRegNames(const char *const *&Names, 1710 unsigned &NumNames) const { 1711 Names = GCCRegNames; 1712 NumNames = llvm::array_lengthof(GCCRegNames); 1713 } 1714 1715 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1716 public: 1717 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1718 LongWidth = LongAlign = 32; 1719 PointerWidth = PointerAlign = 32; 1720 SizeType = TargetInfo::UnsignedInt; 1721 PtrDiffType = TargetInfo::SignedInt; 1722 IntPtrType = TargetInfo::SignedInt; 1723 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1724 } 1725 }; 1726 1727 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1728 public: 1729 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1730 PointerWidth = PointerAlign = 64; 1731 SizeType = TargetInfo::UnsignedLong; 1732 PtrDiffType = TargetInfo::SignedLong; 1733 IntPtrType = TargetInfo::SignedLong; 1734 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1735 } 1736 }; 1737 1738 static const unsigned AMDGPUAddrSpaceMap[] = { 1739 1, // opencl_global 1740 3, // opencl_local 1741 2, // opencl_constant 1742 4, // opencl_generic 1743 1, // cuda_device 1744 2, // cuda_constant 1745 3 // cuda_shared 1746 }; 1747 1748 // If you edit the description strings, make sure you update 1749 // getPointerWidthV(). 1750 1751 static const char *DataLayoutStringR600 = 1752 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1753 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1754 1755 static const char *DataLayoutStringR600DoubleOps = 1756 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1757 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1758 1759 static const char *DataLayoutStringSI = 1760 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1761 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1762 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1763 1764 class AMDGPUTargetInfo : public TargetInfo { 1765 static const Builtin::Info BuiltinInfo[]; 1766 static const char * const GCCRegNames[]; 1767 1768 /// \brief The GPU profiles supported by the AMDGPU target. 1769 enum GPUKind { 1770 GK_NONE, 1771 GK_R600, 1772 GK_R600_DOUBLE_OPS, 1773 GK_R700, 1774 GK_R700_DOUBLE_OPS, 1775 GK_EVERGREEN, 1776 GK_EVERGREEN_DOUBLE_OPS, 1777 GK_NORTHERN_ISLANDS, 1778 GK_CAYMAN, 1779 GK_SOUTHERN_ISLANDS, 1780 GK_SEA_ISLANDS, 1781 GK_VOLCANIC_ISLANDS 1782 } GPU; 1783 1784 bool hasFP64:1; 1785 bool hasFMAF:1; 1786 bool hasLDEXPF:1; 1787 1788 public: 1789 AMDGPUTargetInfo(const llvm::Triple &Triple) 1790 : TargetInfo(Triple) { 1791 1792 if (Triple.getArch() == llvm::Triple::amdgcn) { 1793 DataLayoutString = DataLayoutStringSI; 1794 GPU = GK_SOUTHERN_ISLANDS; 1795 hasFP64 = true; 1796 hasFMAF = true; 1797 hasLDEXPF = true; 1798 } else { 1799 DataLayoutString = DataLayoutStringR600; 1800 GPU = GK_R600; 1801 hasFP64 = false; 1802 hasFMAF = false; 1803 hasLDEXPF = false; 1804 } 1805 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1806 UseAddrSpaceMapMangling = true; 1807 } 1808 1809 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1810 if (GPU <= GK_CAYMAN) 1811 return 32; 1812 1813 switch(AddrSpace) { 1814 default: 1815 return 64; 1816 case 0: 1817 case 3: 1818 case 5: 1819 return 32; 1820 } 1821 } 1822 1823 const char * getClobbers() const override { 1824 return ""; 1825 } 1826 1827 void getGCCRegNames(const char * const *&Names, 1828 unsigned &NumNames) const override; 1829 1830 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1831 unsigned &NumAliases) const override { 1832 Aliases = nullptr; 1833 NumAliases = 0; 1834 } 1835 1836 bool validateAsmConstraint(const char *&Name, 1837 TargetInfo::ConstraintInfo &info) const override { 1838 return true; 1839 } 1840 1841 void getTargetBuiltins(const Builtin::Info *&Records, 1842 unsigned &NumRecords) const override { 1843 Records = BuiltinInfo; 1844 NumRecords = clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin; 1845 } 1846 1847 void getTargetDefines(const LangOptions &Opts, 1848 MacroBuilder &Builder) const override { 1849 Builder.defineMacro("__R600__"); 1850 if (hasFMAF) 1851 Builder.defineMacro("__HAS_FMAF__"); 1852 if (hasLDEXPF) 1853 Builder.defineMacro("__HAS_LDEXPF__"); 1854 if (hasFP64 && Opts.OpenCL) 1855 Builder.defineMacro("cl_khr_fp64"); 1856 if (Opts.OpenCL) { 1857 if (GPU >= GK_NORTHERN_ISLANDS) { 1858 Builder.defineMacro("cl_khr_byte_addressable_store"); 1859 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1860 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1861 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1862 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1863 } 1864 } 1865 } 1866 1867 BuiltinVaListKind getBuiltinVaListKind() const override { 1868 return TargetInfo::CharPtrBuiltinVaList; 1869 } 1870 1871 bool setCPU(const std::string &Name) override { 1872 GPU = llvm::StringSwitch<GPUKind>(Name) 1873 .Case("r600" , GK_R600) 1874 .Case("rv610", GK_R600) 1875 .Case("rv620", GK_R600) 1876 .Case("rv630", GK_R600) 1877 .Case("rv635", GK_R600) 1878 .Case("rs780", GK_R600) 1879 .Case("rs880", GK_R600) 1880 .Case("rv670", GK_R600_DOUBLE_OPS) 1881 .Case("rv710", GK_R700) 1882 .Case("rv730", GK_R700) 1883 .Case("rv740", GK_R700_DOUBLE_OPS) 1884 .Case("rv770", GK_R700_DOUBLE_OPS) 1885 .Case("palm", GK_EVERGREEN) 1886 .Case("cedar", GK_EVERGREEN) 1887 .Case("sumo", GK_EVERGREEN) 1888 .Case("sumo2", GK_EVERGREEN) 1889 .Case("redwood", GK_EVERGREEN) 1890 .Case("juniper", GK_EVERGREEN) 1891 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1892 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1893 .Case("barts", GK_NORTHERN_ISLANDS) 1894 .Case("turks", GK_NORTHERN_ISLANDS) 1895 .Case("caicos", GK_NORTHERN_ISLANDS) 1896 .Case("cayman", GK_CAYMAN) 1897 .Case("aruba", GK_CAYMAN) 1898 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1899 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1900 .Case("verde", GK_SOUTHERN_ISLANDS) 1901 .Case("oland", GK_SOUTHERN_ISLANDS) 1902 .Case("hainan", GK_SOUTHERN_ISLANDS) 1903 .Case("bonaire", GK_SEA_ISLANDS) 1904 .Case("kabini", GK_SEA_ISLANDS) 1905 .Case("kaveri", GK_SEA_ISLANDS) 1906 .Case("hawaii", GK_SEA_ISLANDS) 1907 .Case("mullins", GK_SEA_ISLANDS) 1908 .Case("tonga", GK_VOLCANIC_ISLANDS) 1909 .Case("iceland", GK_VOLCANIC_ISLANDS) 1910 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1911 .Default(GK_NONE); 1912 1913 if (GPU == GK_NONE) { 1914 return false; 1915 } 1916 1917 // Set the correct data layout 1918 switch (GPU) { 1919 case GK_NONE: 1920 case GK_R600: 1921 case GK_R700: 1922 case GK_EVERGREEN: 1923 case GK_NORTHERN_ISLANDS: 1924 DataLayoutString = DataLayoutStringR600; 1925 hasFP64 = false; 1926 hasFMAF = false; 1927 hasLDEXPF = false; 1928 break; 1929 case GK_R600_DOUBLE_OPS: 1930 case GK_R700_DOUBLE_OPS: 1931 case GK_EVERGREEN_DOUBLE_OPS: 1932 case GK_CAYMAN: 1933 DataLayoutString = DataLayoutStringR600DoubleOps; 1934 hasFP64 = true; 1935 hasFMAF = true; 1936 hasLDEXPF = false; 1937 break; 1938 case GK_SOUTHERN_ISLANDS: 1939 case GK_SEA_ISLANDS: 1940 case GK_VOLCANIC_ISLANDS: 1941 DataLayoutString = DataLayoutStringSI; 1942 hasFP64 = true; 1943 hasFMAF = true; 1944 hasLDEXPF = true; 1945 break; 1946 } 1947 1948 return true; 1949 } 1950 }; 1951 1952 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1953 #define BUILTIN(ID, TYPE, ATTRS) \ 1954 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1955 #include "clang/Basic/BuiltinsAMDGPU.def" 1956 }; 1957 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1958 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1959 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1960 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1961 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1962 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1963 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1964 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1965 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1966 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1967 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1968 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1969 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1970 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1971 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1972 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1973 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1974 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1975 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1976 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1977 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1978 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1979 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1980 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1981 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1982 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1983 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1984 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1985 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1986 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1987 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1988 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1989 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1990 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1991 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1992 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1993 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1994 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1995 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1996 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1997 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1998 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1999 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2000 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2001 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2002 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2003 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2004 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2005 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 2006 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 2007 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 2008 }; 2009 2010 void AMDGPUTargetInfo::getGCCRegNames(const char * const *&Names, 2011 unsigned &NumNames) const { 2012 Names = GCCRegNames; 2013 NumNames = llvm::array_lengthof(GCCRegNames); 2014 } 2015 2016 // Namespace for x86 abstract base class 2017 const Builtin::Info BuiltinInfo[] = { 2018 #define BUILTIN(ID, TYPE, ATTRS) \ 2019 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2020 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2021 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2022 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2023 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2024 #include "clang/Basic/BuiltinsX86.def" 2025 }; 2026 2027 static const char* const GCCRegNames[] = { 2028 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2029 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2030 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2031 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2032 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2033 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2034 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2035 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2036 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2037 }; 2038 2039 const TargetInfo::AddlRegName AddlRegNames[] = { 2040 { { "al", "ah", "eax", "rax" }, 0 }, 2041 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2042 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2043 { { "dl", "dh", "edx", "rdx" }, 1 }, 2044 { { "esi", "rsi" }, 4 }, 2045 { { "edi", "rdi" }, 5 }, 2046 { { "esp", "rsp" }, 7 }, 2047 { { "ebp", "rbp" }, 6 }, 2048 { { "r8d", "r8w", "r8b" }, 38 }, 2049 { { "r9d", "r9w", "r9b" }, 39 }, 2050 { { "r10d", "r10w", "r10b" }, 40 }, 2051 { { "r11d", "r11w", "r11b" }, 41 }, 2052 { { "r12d", "r12w", "r12b" }, 42 }, 2053 { { "r13d", "r13w", "r13b" }, 43 }, 2054 { { "r14d", "r14w", "r14b" }, 44 }, 2055 { { "r15d", "r15w", "r15b" }, 45 }, 2056 }; 2057 2058 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2059 // most of the implementation can be shared. 2060 class X86TargetInfo : public TargetInfo { 2061 enum X86SSEEnum { 2062 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2063 } SSELevel = NoSSE; 2064 enum MMX3DNowEnum { 2065 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2066 } MMX3DNowLevel = NoMMX3DNow; 2067 enum XOPEnum { 2068 NoXOP, 2069 SSE4A, 2070 FMA4, 2071 XOP 2072 } XOPLevel = NoXOP; 2073 2074 bool HasAES = false; 2075 bool HasPCLMUL = false; 2076 bool HasLZCNT = false; 2077 bool HasRDRND = false; 2078 bool HasFSGSBASE = false; 2079 bool HasBMI = false; 2080 bool HasBMI2 = false; 2081 bool HasPOPCNT = false; 2082 bool HasRTM = false; 2083 bool HasPRFCHW = false; 2084 bool HasRDSEED = false; 2085 bool HasADX = false; 2086 bool HasTBM = false; 2087 bool HasFMA = false; 2088 bool HasF16C = false; 2089 bool HasAVX512CD = false; 2090 bool HasAVX512ER = false; 2091 bool HasAVX512PF = false; 2092 bool HasAVX512DQ = false; 2093 bool HasAVX512BW = false; 2094 bool HasAVX512VL = false; 2095 bool HasSHA = false; 2096 bool HasCX16 = false; 2097 bool HasXSAVE = false; 2098 bool HasXSAVEOPT = false; 2099 bool HasXSAVEC = false; 2100 bool HasXSAVES = false; 2101 2102 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2103 /// 2104 /// Each enumeration represents a particular CPU supported by Clang. These 2105 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2106 enum CPUKind { 2107 CK_Generic, 2108 2109 /// \name i386 2110 /// i386-generation processors. 2111 //@{ 2112 CK_i386, 2113 //@} 2114 2115 /// \name i486 2116 /// i486-generation processors. 2117 //@{ 2118 CK_i486, 2119 CK_WinChipC6, 2120 CK_WinChip2, 2121 CK_C3, 2122 //@} 2123 2124 /// \name i586 2125 /// i586-generation processors, P5 microarchitecture based. 2126 //@{ 2127 CK_i586, 2128 CK_Pentium, 2129 CK_PentiumMMX, 2130 //@} 2131 2132 /// \name i686 2133 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2134 //@{ 2135 CK_i686, 2136 CK_PentiumPro, 2137 CK_Pentium2, 2138 CK_Pentium3, 2139 CK_Pentium3M, 2140 CK_PentiumM, 2141 CK_C3_2, 2142 2143 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2144 /// Clang however has some logic to suport this. 2145 // FIXME: Warn, deprecate, and potentially remove this. 2146 CK_Yonah, 2147 //@} 2148 2149 /// \name Netburst 2150 /// Netburst microarchitecture based processors. 2151 //@{ 2152 CK_Pentium4, 2153 CK_Pentium4M, 2154 CK_Prescott, 2155 CK_Nocona, 2156 //@} 2157 2158 /// \name Core 2159 /// Core microarchitecture based processors. 2160 //@{ 2161 CK_Core2, 2162 2163 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2164 /// codename which GCC no longer accepts as an option to -march, but Clang 2165 /// has some logic for recognizing it. 2166 // FIXME: Warn, deprecate, and potentially remove this. 2167 CK_Penryn, 2168 //@} 2169 2170 /// \name Atom 2171 /// Atom processors 2172 //@{ 2173 CK_Bonnell, 2174 CK_Silvermont, 2175 //@} 2176 2177 /// \name Nehalem 2178 /// Nehalem microarchitecture based processors. 2179 CK_Nehalem, 2180 2181 /// \name Westmere 2182 /// Westmere microarchitecture based processors. 2183 CK_Westmere, 2184 2185 /// \name Sandy Bridge 2186 /// Sandy Bridge microarchitecture based processors. 2187 CK_SandyBridge, 2188 2189 /// \name Ivy Bridge 2190 /// Ivy Bridge microarchitecture based processors. 2191 CK_IvyBridge, 2192 2193 /// \name Haswell 2194 /// Haswell microarchitecture based processors. 2195 CK_Haswell, 2196 2197 /// \name Broadwell 2198 /// Broadwell microarchitecture based processors. 2199 CK_Broadwell, 2200 2201 /// \name Skylake 2202 /// Skylake microarchitecture based processors. 2203 CK_Skylake, 2204 2205 /// \name Knights Landing 2206 /// Knights Landing processor. 2207 CK_KNL, 2208 2209 /// \name K6 2210 /// K6 architecture processors. 2211 //@{ 2212 CK_K6, 2213 CK_K6_2, 2214 CK_K6_3, 2215 //@} 2216 2217 /// \name K7 2218 /// K7 architecture processors. 2219 //@{ 2220 CK_Athlon, 2221 CK_AthlonThunderbird, 2222 CK_Athlon4, 2223 CK_AthlonXP, 2224 CK_AthlonMP, 2225 //@} 2226 2227 /// \name K8 2228 /// K8 architecture processors. 2229 //@{ 2230 CK_Athlon64, 2231 CK_Athlon64SSE3, 2232 CK_AthlonFX, 2233 CK_K8, 2234 CK_K8SSE3, 2235 CK_Opteron, 2236 CK_OpteronSSE3, 2237 CK_AMDFAM10, 2238 //@} 2239 2240 /// \name Bobcat 2241 /// Bobcat architecture processors. 2242 //@{ 2243 CK_BTVER1, 2244 CK_BTVER2, 2245 //@} 2246 2247 /// \name Bulldozer 2248 /// Bulldozer architecture processors. 2249 //@{ 2250 CK_BDVER1, 2251 CK_BDVER2, 2252 CK_BDVER3, 2253 CK_BDVER4, 2254 //@} 2255 2256 /// This specification is deprecated and will be removed in the future. 2257 /// Users should prefer \see CK_K8. 2258 // FIXME: Warn on this when the CPU is set to it. 2259 //@{ 2260 CK_x86_64, 2261 //@} 2262 2263 /// \name Geode 2264 /// Geode processors. 2265 //@{ 2266 CK_Geode 2267 //@} 2268 } CPU = CK_Generic; 2269 2270 CPUKind getCPUKind(StringRef CPU) const { 2271 return llvm::StringSwitch<CPUKind>(CPU) 2272 .Case("i386", CK_i386) 2273 .Case("i486", CK_i486) 2274 .Case("winchip-c6", CK_WinChipC6) 2275 .Case("winchip2", CK_WinChip2) 2276 .Case("c3", CK_C3) 2277 .Case("i586", CK_i586) 2278 .Case("pentium", CK_Pentium) 2279 .Case("pentium-mmx", CK_PentiumMMX) 2280 .Case("i686", CK_i686) 2281 .Case("pentiumpro", CK_PentiumPro) 2282 .Case("pentium2", CK_Pentium2) 2283 .Case("pentium3", CK_Pentium3) 2284 .Case("pentium3m", CK_Pentium3M) 2285 .Case("pentium-m", CK_PentiumM) 2286 .Case("c3-2", CK_C3_2) 2287 .Case("yonah", CK_Yonah) 2288 .Case("pentium4", CK_Pentium4) 2289 .Case("pentium4m", CK_Pentium4M) 2290 .Case("prescott", CK_Prescott) 2291 .Case("nocona", CK_Nocona) 2292 .Case("core2", CK_Core2) 2293 .Case("penryn", CK_Penryn) 2294 .Case("bonnell", CK_Bonnell) 2295 .Case("atom", CK_Bonnell) // Legacy name. 2296 .Case("silvermont", CK_Silvermont) 2297 .Case("slm", CK_Silvermont) // Legacy name. 2298 .Case("nehalem", CK_Nehalem) 2299 .Case("corei7", CK_Nehalem) // Legacy name. 2300 .Case("westmere", CK_Westmere) 2301 .Case("sandybridge", CK_SandyBridge) 2302 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2303 .Case("ivybridge", CK_IvyBridge) 2304 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2305 .Case("haswell", CK_Haswell) 2306 .Case("core-avx2", CK_Haswell) // Legacy name. 2307 .Case("broadwell", CK_Broadwell) 2308 .Case("skylake", CK_Skylake) 2309 .Case("skx", CK_Skylake) // Legacy name. 2310 .Case("knl", CK_KNL) 2311 .Case("k6", CK_K6) 2312 .Case("k6-2", CK_K6_2) 2313 .Case("k6-3", CK_K6_3) 2314 .Case("athlon", CK_Athlon) 2315 .Case("athlon-tbird", CK_AthlonThunderbird) 2316 .Case("athlon-4", CK_Athlon4) 2317 .Case("athlon-xp", CK_AthlonXP) 2318 .Case("athlon-mp", CK_AthlonMP) 2319 .Case("athlon64", CK_Athlon64) 2320 .Case("athlon64-sse3", CK_Athlon64SSE3) 2321 .Case("athlon-fx", CK_AthlonFX) 2322 .Case("k8", CK_K8) 2323 .Case("k8-sse3", CK_K8SSE3) 2324 .Case("opteron", CK_Opteron) 2325 .Case("opteron-sse3", CK_OpteronSSE3) 2326 .Case("barcelona", CK_AMDFAM10) 2327 .Case("amdfam10", CK_AMDFAM10) 2328 .Case("btver1", CK_BTVER1) 2329 .Case("btver2", CK_BTVER2) 2330 .Case("bdver1", CK_BDVER1) 2331 .Case("bdver2", CK_BDVER2) 2332 .Case("bdver3", CK_BDVER3) 2333 .Case("bdver4", CK_BDVER4) 2334 .Case("x86-64", CK_x86_64) 2335 .Case("geode", CK_Geode) 2336 .Default(CK_Generic); 2337 } 2338 2339 enum FPMathKind { 2340 FP_Default, 2341 FP_SSE, 2342 FP_387 2343 } FPMath = FP_Default; 2344 2345 public: 2346 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 2347 BigEndian = false; 2348 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2349 } 2350 unsigned getFloatEvalMethod() const override { 2351 // X87 evaluates with 80 bits "long double" precision. 2352 return SSELevel == NoSSE ? 2 : 0; 2353 } 2354 void getTargetBuiltins(const Builtin::Info *&Records, 2355 unsigned &NumRecords) const override { 2356 Records = BuiltinInfo; 2357 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 2358 } 2359 void getGCCRegNames(const char * const *&Names, 2360 unsigned &NumNames) const override { 2361 Names = GCCRegNames; 2362 NumNames = llvm::array_lengthof(GCCRegNames); 2363 } 2364 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2365 unsigned &NumAliases) const override { 2366 Aliases = nullptr; 2367 NumAliases = 0; 2368 } 2369 void getGCCAddlRegNames(const AddlRegName *&Names, 2370 unsigned &NumNames) const override { 2371 Names = AddlRegNames; 2372 NumNames = llvm::array_lengthof(AddlRegNames); 2373 } 2374 bool validateCpuSupports(StringRef Name) const override; 2375 bool validateAsmConstraint(const char *&Name, 2376 TargetInfo::ConstraintInfo &info) const override; 2377 2378 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2379 2380 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2381 2382 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2383 2384 std::string convertConstraint(const char *&Constraint) const override; 2385 const char *getClobbers() const override { 2386 return "~{dirflag},~{fpsr},~{flags}"; 2387 } 2388 void getTargetDefines(const LangOptions &Opts, 2389 MacroBuilder &Builder) const override; 2390 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2391 bool Enabled); 2392 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2393 bool Enabled); 2394 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2395 bool Enabled); 2396 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2397 StringRef Name, bool Enabled) const override { 2398 setFeatureEnabledImpl(Features, Name, Enabled); 2399 } 2400 // This exists purely to cut down on the number of virtual calls in 2401 // initFeatureMap which calls this repeatedly. 2402 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2403 StringRef Name, bool Enabled); 2404 bool 2405 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2406 StringRef CPU, 2407 const std::vector<std::string> &FeaturesVec) const override; 2408 bool hasFeature(StringRef Feature) const override; 2409 bool handleTargetFeatures(std::vector<std::string> &Features, 2410 DiagnosticsEngine &Diags) override; 2411 StringRef getABI() const override { 2412 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2413 return "avx512"; 2414 else if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2415 return "avx"; 2416 else if (getTriple().getArch() == llvm::Triple::x86 && 2417 MMX3DNowLevel == NoMMX3DNow) 2418 return "no-mmx"; 2419 return ""; 2420 } 2421 bool setCPU(const std::string &Name) override { 2422 CPU = getCPUKind(Name); 2423 2424 // Perform any per-CPU checks necessary to determine if this CPU is 2425 // acceptable. 2426 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2427 // invalid without explaining *why*. 2428 switch (CPU) { 2429 case CK_Generic: 2430 // No processor selected! 2431 return false; 2432 2433 case CK_i386: 2434 case CK_i486: 2435 case CK_WinChipC6: 2436 case CK_WinChip2: 2437 case CK_C3: 2438 case CK_i586: 2439 case CK_Pentium: 2440 case CK_PentiumMMX: 2441 case CK_i686: 2442 case CK_PentiumPro: 2443 case CK_Pentium2: 2444 case CK_Pentium3: 2445 case CK_Pentium3M: 2446 case CK_PentiumM: 2447 case CK_Yonah: 2448 case CK_C3_2: 2449 case CK_Pentium4: 2450 case CK_Pentium4M: 2451 case CK_Prescott: 2452 case CK_K6: 2453 case CK_K6_2: 2454 case CK_K6_3: 2455 case CK_Athlon: 2456 case CK_AthlonThunderbird: 2457 case CK_Athlon4: 2458 case CK_AthlonXP: 2459 case CK_AthlonMP: 2460 case CK_Geode: 2461 // Only accept certain architectures when compiling in 32-bit mode. 2462 if (getTriple().getArch() != llvm::Triple::x86) 2463 return false; 2464 2465 // Fallthrough 2466 case CK_Nocona: 2467 case CK_Core2: 2468 case CK_Penryn: 2469 case CK_Bonnell: 2470 case CK_Silvermont: 2471 case CK_Nehalem: 2472 case CK_Westmere: 2473 case CK_SandyBridge: 2474 case CK_IvyBridge: 2475 case CK_Haswell: 2476 case CK_Broadwell: 2477 case CK_Skylake: 2478 case CK_KNL: 2479 case CK_Athlon64: 2480 case CK_Athlon64SSE3: 2481 case CK_AthlonFX: 2482 case CK_K8: 2483 case CK_K8SSE3: 2484 case CK_Opteron: 2485 case CK_OpteronSSE3: 2486 case CK_AMDFAM10: 2487 case CK_BTVER1: 2488 case CK_BTVER2: 2489 case CK_BDVER1: 2490 case CK_BDVER2: 2491 case CK_BDVER3: 2492 case CK_BDVER4: 2493 case CK_x86_64: 2494 return true; 2495 } 2496 llvm_unreachable("Unhandled CPU kind"); 2497 } 2498 2499 bool setFPMath(StringRef Name) override; 2500 2501 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2502 // We accept all non-ARM calling conventions 2503 return (CC == CC_X86ThisCall || 2504 CC == CC_X86FastCall || 2505 CC == CC_X86StdCall || 2506 CC == CC_X86VectorCall || 2507 CC == CC_C || 2508 CC == CC_X86Pascal || 2509 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2510 } 2511 2512 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2513 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2514 } 2515 2516 bool hasSjLjLowering() const override { 2517 return true; 2518 } 2519 }; 2520 2521 bool X86TargetInfo::setFPMath(StringRef Name) { 2522 if (Name == "387") { 2523 FPMath = FP_387; 2524 return true; 2525 } 2526 if (Name == "sse") { 2527 FPMath = FP_SSE; 2528 return true; 2529 } 2530 return false; 2531 } 2532 2533 bool X86TargetInfo::initFeatureMap( 2534 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2535 const std::vector<std::string> &FeaturesVec) const { 2536 // FIXME: This *really* should not be here. 2537 // X86_64 always has SSE2. 2538 if (getTriple().getArch() == llvm::Triple::x86_64) 2539 setFeatureEnabledImpl(Features, "sse2", true); 2540 2541 switch (getCPUKind(CPU)) { 2542 case CK_Generic: 2543 case CK_i386: 2544 case CK_i486: 2545 case CK_i586: 2546 case CK_Pentium: 2547 case CK_i686: 2548 case CK_PentiumPro: 2549 break; 2550 case CK_PentiumMMX: 2551 case CK_Pentium2: 2552 case CK_K6: 2553 case CK_WinChipC6: 2554 setFeatureEnabledImpl(Features, "mmx", true); 2555 break; 2556 case CK_Pentium3: 2557 case CK_Pentium3M: 2558 case CK_C3_2: 2559 setFeatureEnabledImpl(Features, "sse", true); 2560 break; 2561 case CK_PentiumM: 2562 case CK_Pentium4: 2563 case CK_Pentium4M: 2564 case CK_x86_64: 2565 setFeatureEnabledImpl(Features, "sse2", true); 2566 break; 2567 case CK_Yonah: 2568 case CK_Prescott: 2569 case CK_Nocona: 2570 setFeatureEnabledImpl(Features, "sse3", true); 2571 setFeatureEnabledImpl(Features, "cx16", true); 2572 break; 2573 case CK_Core2: 2574 case CK_Bonnell: 2575 setFeatureEnabledImpl(Features, "ssse3", true); 2576 setFeatureEnabledImpl(Features, "cx16", true); 2577 break; 2578 case CK_Penryn: 2579 setFeatureEnabledImpl(Features, "sse4.1", true); 2580 setFeatureEnabledImpl(Features, "cx16", true); 2581 break; 2582 case CK_Skylake: 2583 setFeatureEnabledImpl(Features, "avx512f", true); 2584 setFeatureEnabledImpl(Features, "avx512cd", true); 2585 setFeatureEnabledImpl(Features, "avx512dq", true); 2586 setFeatureEnabledImpl(Features, "avx512bw", true); 2587 setFeatureEnabledImpl(Features, "avx512vl", true); 2588 setFeatureEnabledImpl(Features, "xsavec", true); 2589 setFeatureEnabledImpl(Features, "xsaves", true); 2590 // FALLTHROUGH 2591 case CK_Broadwell: 2592 setFeatureEnabledImpl(Features, "rdseed", true); 2593 setFeatureEnabledImpl(Features, "adx", true); 2594 // FALLTHROUGH 2595 case CK_Haswell: 2596 setFeatureEnabledImpl(Features, "avx2", true); 2597 setFeatureEnabledImpl(Features, "lzcnt", true); 2598 setFeatureEnabledImpl(Features, "bmi", true); 2599 setFeatureEnabledImpl(Features, "bmi2", true); 2600 setFeatureEnabledImpl(Features, "rtm", true); 2601 setFeatureEnabledImpl(Features, "fma", true); 2602 // FALLTHROUGH 2603 case CK_IvyBridge: 2604 setFeatureEnabledImpl(Features, "rdrnd", true); 2605 setFeatureEnabledImpl(Features, "f16c", true); 2606 setFeatureEnabledImpl(Features, "fsgsbase", true); 2607 // FALLTHROUGH 2608 case CK_SandyBridge: 2609 setFeatureEnabledImpl(Features, "avx", true); 2610 setFeatureEnabledImpl(Features, "xsave", true); 2611 setFeatureEnabledImpl(Features, "xsaveopt", true); 2612 // FALLTHROUGH 2613 case CK_Westmere: 2614 case CK_Silvermont: 2615 setFeatureEnabledImpl(Features, "aes", true); 2616 setFeatureEnabledImpl(Features, "pclmul", true); 2617 // FALLTHROUGH 2618 case CK_Nehalem: 2619 setFeatureEnabledImpl(Features, "sse4.2", true); 2620 setFeatureEnabledImpl(Features, "cx16", true); 2621 break; 2622 case CK_KNL: 2623 setFeatureEnabledImpl(Features, "avx512f", true); 2624 setFeatureEnabledImpl(Features, "avx512cd", true); 2625 setFeatureEnabledImpl(Features, "avx512er", true); 2626 setFeatureEnabledImpl(Features, "avx512pf", true); 2627 setFeatureEnabledImpl(Features, "rdseed", true); 2628 setFeatureEnabledImpl(Features, "adx", true); 2629 setFeatureEnabledImpl(Features, "lzcnt", true); 2630 setFeatureEnabledImpl(Features, "bmi", true); 2631 setFeatureEnabledImpl(Features, "bmi2", true); 2632 setFeatureEnabledImpl(Features, "rtm", true); 2633 setFeatureEnabledImpl(Features, "fma", true); 2634 setFeatureEnabledImpl(Features, "rdrnd", true); 2635 setFeatureEnabledImpl(Features, "f16c", true); 2636 setFeatureEnabledImpl(Features, "fsgsbase", true); 2637 setFeatureEnabledImpl(Features, "aes", true); 2638 setFeatureEnabledImpl(Features, "pclmul", true); 2639 setFeatureEnabledImpl(Features, "cx16", true); 2640 setFeatureEnabledImpl(Features, "xsaveopt", true); 2641 setFeatureEnabledImpl(Features, "xsave", true); 2642 break; 2643 case CK_K6_2: 2644 case CK_K6_3: 2645 case CK_WinChip2: 2646 case CK_C3: 2647 setFeatureEnabledImpl(Features, "3dnow", true); 2648 break; 2649 case CK_Athlon: 2650 case CK_AthlonThunderbird: 2651 case CK_Geode: 2652 setFeatureEnabledImpl(Features, "3dnowa", true); 2653 break; 2654 case CK_Athlon4: 2655 case CK_AthlonXP: 2656 case CK_AthlonMP: 2657 setFeatureEnabledImpl(Features, "sse", true); 2658 setFeatureEnabledImpl(Features, "3dnowa", true); 2659 break; 2660 case CK_K8: 2661 case CK_Opteron: 2662 case CK_Athlon64: 2663 case CK_AthlonFX: 2664 setFeatureEnabledImpl(Features, "sse2", true); 2665 setFeatureEnabledImpl(Features, "3dnowa", true); 2666 break; 2667 case CK_AMDFAM10: 2668 setFeatureEnabledImpl(Features, "sse4a", true); 2669 setFeatureEnabledImpl(Features, "lzcnt", true); 2670 setFeatureEnabledImpl(Features, "popcnt", true); 2671 // FALLTHROUGH 2672 case CK_K8SSE3: 2673 case CK_OpteronSSE3: 2674 case CK_Athlon64SSE3: 2675 setFeatureEnabledImpl(Features, "sse3", true); 2676 setFeatureEnabledImpl(Features, "3dnowa", true); 2677 break; 2678 case CK_BTVER2: 2679 setFeatureEnabledImpl(Features, "avx", true); 2680 setFeatureEnabledImpl(Features, "aes", true); 2681 setFeatureEnabledImpl(Features, "pclmul", true); 2682 setFeatureEnabledImpl(Features, "bmi", true); 2683 setFeatureEnabledImpl(Features, "f16c", true); 2684 setFeatureEnabledImpl(Features, "xsaveopt", true); 2685 // FALLTHROUGH 2686 case CK_BTVER1: 2687 setFeatureEnabledImpl(Features, "ssse3", true); 2688 setFeatureEnabledImpl(Features, "sse4a", true); 2689 setFeatureEnabledImpl(Features, "lzcnt", true); 2690 setFeatureEnabledImpl(Features, "popcnt", true); 2691 setFeatureEnabledImpl(Features, "prfchw", true); 2692 setFeatureEnabledImpl(Features, "cx16", true); 2693 setFeatureEnabledImpl(Features, "xsave", true); 2694 break; 2695 case CK_BDVER4: 2696 setFeatureEnabledImpl(Features, "avx2", true); 2697 setFeatureEnabledImpl(Features, "bmi2", true); 2698 // FALLTHROUGH 2699 case CK_BDVER3: 2700 setFeatureEnabledImpl(Features, "fsgsbase", true); 2701 setFeatureEnabledImpl(Features, "xsaveopt", true); 2702 // FALLTHROUGH 2703 case CK_BDVER2: 2704 setFeatureEnabledImpl(Features, "bmi", true); 2705 setFeatureEnabledImpl(Features, "fma", true); 2706 setFeatureEnabledImpl(Features, "f16c", true); 2707 setFeatureEnabledImpl(Features, "tbm", true); 2708 // FALLTHROUGH 2709 case CK_BDVER1: 2710 // xop implies avx, sse4a and fma4. 2711 setFeatureEnabledImpl(Features, "xop", true); 2712 setFeatureEnabledImpl(Features, "lzcnt", true); 2713 setFeatureEnabledImpl(Features, "aes", true); 2714 setFeatureEnabledImpl(Features, "pclmul", true); 2715 setFeatureEnabledImpl(Features, "prfchw", true); 2716 setFeatureEnabledImpl(Features, "cx16", true); 2717 setFeatureEnabledImpl(Features, "xsave", true); 2718 break; 2719 } 2720 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2721 return false; 2722 2723 // Can't do this earlier because we need to be able to explicitly enable 2724 // or disable these features and the things that they depend upon. 2725 2726 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2727 auto I = Features.find("sse4.2"); 2728 if (I != Features.end() && I->getValue() == true && 2729 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2730 FeaturesVec.end()) 2731 Features["popcnt"] = true; 2732 2733 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2734 I = Features.find("3dnow"); 2735 if (I != Features.end() && I->getValue() == true && 2736 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2737 FeaturesVec.end()) 2738 Features["prfchw"] = true; 2739 2740 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2741 // then enable MMX. 2742 I = Features.find("sse"); 2743 if (I != Features.end() && I->getValue() == true && 2744 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2745 FeaturesVec.end()) 2746 Features["mmx"] = true; 2747 2748 return true; 2749 } 2750 2751 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2752 X86SSEEnum Level, bool Enabled) { 2753 if (Enabled) { 2754 switch (Level) { 2755 case AVX512F: 2756 Features["avx512f"] = true; 2757 case AVX2: 2758 Features["avx2"] = true; 2759 case AVX: 2760 Features["avx"] = true; 2761 Features["xsave"] = true; 2762 case SSE42: 2763 Features["sse4.2"] = true; 2764 case SSE41: 2765 Features["sse4.1"] = true; 2766 case SSSE3: 2767 Features["ssse3"] = true; 2768 case SSE3: 2769 Features["sse3"] = true; 2770 case SSE2: 2771 Features["sse2"] = true; 2772 case SSE1: 2773 Features["sse"] = true; 2774 case NoSSE: 2775 break; 2776 } 2777 return; 2778 } 2779 2780 switch (Level) { 2781 case NoSSE: 2782 case SSE1: 2783 Features["sse"] = false; 2784 case SSE2: 2785 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2786 Features["sha"] = false; 2787 case SSE3: 2788 Features["sse3"] = false; 2789 setXOPLevel(Features, NoXOP, false); 2790 case SSSE3: 2791 Features["ssse3"] = false; 2792 case SSE41: 2793 Features["sse4.1"] = false; 2794 case SSE42: 2795 Features["sse4.2"] = false; 2796 case AVX: 2797 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2798 Features["xsaveopt"] = false; 2799 setXOPLevel(Features, FMA4, false); 2800 case AVX2: 2801 Features["avx2"] = false; 2802 case AVX512F: 2803 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2804 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2805 Features["avx512vl"] = false; 2806 } 2807 } 2808 2809 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2810 MMX3DNowEnum Level, bool Enabled) { 2811 if (Enabled) { 2812 switch (Level) { 2813 case AMD3DNowAthlon: 2814 Features["3dnowa"] = true; 2815 case AMD3DNow: 2816 Features["3dnow"] = true; 2817 case MMX: 2818 Features["mmx"] = true; 2819 case NoMMX3DNow: 2820 break; 2821 } 2822 return; 2823 } 2824 2825 switch (Level) { 2826 case NoMMX3DNow: 2827 case MMX: 2828 Features["mmx"] = false; 2829 case AMD3DNow: 2830 Features["3dnow"] = false; 2831 case AMD3DNowAthlon: 2832 Features["3dnowa"] = false; 2833 } 2834 } 2835 2836 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2837 bool Enabled) { 2838 if (Enabled) { 2839 switch (Level) { 2840 case XOP: 2841 Features["xop"] = true; 2842 case FMA4: 2843 Features["fma4"] = true; 2844 setSSELevel(Features, AVX, true); 2845 case SSE4A: 2846 Features["sse4a"] = true; 2847 setSSELevel(Features, SSE3, true); 2848 case NoXOP: 2849 break; 2850 } 2851 return; 2852 } 2853 2854 switch (Level) { 2855 case NoXOP: 2856 case SSE4A: 2857 Features["sse4a"] = false; 2858 case FMA4: 2859 Features["fma4"] = false; 2860 case XOP: 2861 Features["xop"] = false; 2862 } 2863 } 2864 2865 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2866 StringRef Name, bool Enabled) { 2867 // This is a bit of a hack to deal with the sse4 target feature when used 2868 // as part of the target attribute. We handle sse4 correctly everywhere 2869 // else. See below for more information on how we handle the sse4 options. 2870 if (Name != "sse4") 2871 Features[Name] = Enabled; 2872 2873 if (Name == "mmx") { 2874 setMMXLevel(Features, MMX, Enabled); 2875 } else if (Name == "sse") { 2876 setSSELevel(Features, SSE1, Enabled); 2877 } else if (Name == "sse2") { 2878 setSSELevel(Features, SSE2, Enabled); 2879 } else if (Name == "sse3") { 2880 setSSELevel(Features, SSE3, Enabled); 2881 } else if (Name == "ssse3") { 2882 setSSELevel(Features, SSSE3, Enabled); 2883 } else if (Name == "sse4.2") { 2884 setSSELevel(Features, SSE42, Enabled); 2885 } else if (Name == "sse4.1") { 2886 setSSELevel(Features, SSE41, Enabled); 2887 } else if (Name == "3dnow") { 2888 setMMXLevel(Features, AMD3DNow, Enabled); 2889 } else if (Name == "3dnowa") { 2890 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2891 } else if (Name == "aes") { 2892 if (Enabled) 2893 setSSELevel(Features, SSE2, Enabled); 2894 } else if (Name == "pclmul") { 2895 if (Enabled) 2896 setSSELevel(Features, SSE2, Enabled); 2897 } else if (Name == "avx") { 2898 setSSELevel(Features, AVX, Enabled); 2899 } else if (Name == "avx2") { 2900 setSSELevel(Features, AVX2, Enabled); 2901 } else if (Name == "avx512f") { 2902 setSSELevel(Features, AVX512F, Enabled); 2903 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2904 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2905 if (Enabled) 2906 setSSELevel(Features, AVX512F, Enabled); 2907 } else if (Name == "fma") { 2908 if (Enabled) 2909 setSSELevel(Features, AVX, Enabled); 2910 } else if (Name == "fma4") { 2911 setXOPLevel(Features, FMA4, Enabled); 2912 } else if (Name == "xop") { 2913 setXOPLevel(Features, XOP, Enabled); 2914 } else if (Name == "sse4a") { 2915 setXOPLevel(Features, SSE4A, Enabled); 2916 } else if (Name == "f16c") { 2917 if (Enabled) 2918 setSSELevel(Features, AVX, Enabled); 2919 } else if (Name == "sha") { 2920 if (Enabled) 2921 setSSELevel(Features, SSE2, Enabled); 2922 } else if (Name == "sse4") { 2923 // We can get here via the __target__ attribute since that's not controlled 2924 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2925 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2926 // disabled. 2927 if (Enabled) 2928 setSSELevel(Features, SSE42, Enabled); 2929 else 2930 setSSELevel(Features, SSE41, Enabled); 2931 } else if (Name == "xsave") { 2932 if (Enabled) 2933 setSSELevel(Features, AVX, Enabled); 2934 else 2935 Features["xsaveopt"] = false; 2936 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 2937 if (Enabled) { 2938 Features["xsave"] = true; 2939 setSSELevel(Features, AVX, Enabled); 2940 } 2941 } 2942 } 2943 2944 /// handleTargetFeatures - Perform initialization based on the user 2945 /// configured set of features. 2946 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2947 DiagnosticsEngine &Diags) { 2948 for (const auto &Feature : Features) { 2949 if (Feature[0] != '+') 2950 continue; 2951 2952 if (Feature == "+aes") { 2953 HasAES = true; 2954 } else if (Feature == "+pclmul") { 2955 HasPCLMUL = true; 2956 } else if (Feature == "+lzcnt") { 2957 HasLZCNT = true; 2958 } else if (Feature == "+rdrnd") { 2959 HasRDRND = true; 2960 } else if (Feature == "+fsgsbase") { 2961 HasFSGSBASE = true; 2962 } else if (Feature == "+bmi") { 2963 HasBMI = true; 2964 } else if (Feature == "+bmi2") { 2965 HasBMI2 = true; 2966 } else if (Feature == "+popcnt") { 2967 HasPOPCNT = true; 2968 } else if (Feature == "+rtm") { 2969 HasRTM = true; 2970 } else if (Feature == "+prfchw") { 2971 HasPRFCHW = true; 2972 } else if (Feature == "+rdseed") { 2973 HasRDSEED = true; 2974 } else if (Feature == "+adx") { 2975 HasADX = true; 2976 } else if (Feature == "+tbm") { 2977 HasTBM = true; 2978 } else if (Feature == "+fma") { 2979 HasFMA = true; 2980 } else if (Feature == "+f16c") { 2981 HasF16C = true; 2982 } else if (Feature == "+avx512cd") { 2983 HasAVX512CD = true; 2984 } else if (Feature == "+avx512er") { 2985 HasAVX512ER = true; 2986 } else if (Feature == "+avx512pf") { 2987 HasAVX512PF = true; 2988 } else if (Feature == "+avx512dq") { 2989 HasAVX512DQ = true; 2990 } else if (Feature == "+avx512bw") { 2991 HasAVX512BW = true; 2992 } else if (Feature == "+avx512vl") { 2993 HasAVX512VL = true; 2994 } else if (Feature == "+sha") { 2995 HasSHA = true; 2996 } else if (Feature == "+cx16") { 2997 HasCX16 = true; 2998 } else if (Feature == "+xsave") { 2999 HasXSAVE = true; 3000 } else if (Feature == "+xsaveopt") { 3001 HasXSAVEOPT = true; 3002 } else if (Feature == "+xsavec") { 3003 HasXSAVEC = true; 3004 } else if (Feature == "+xsaves") { 3005 HasXSAVES = true; 3006 } 3007 3008 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3009 .Case("+avx512f", AVX512F) 3010 .Case("+avx2", AVX2) 3011 .Case("+avx", AVX) 3012 .Case("+sse4.2", SSE42) 3013 .Case("+sse4.1", SSE41) 3014 .Case("+ssse3", SSSE3) 3015 .Case("+sse3", SSE3) 3016 .Case("+sse2", SSE2) 3017 .Case("+sse", SSE1) 3018 .Default(NoSSE); 3019 SSELevel = std::max(SSELevel, Level); 3020 3021 MMX3DNowEnum ThreeDNowLevel = 3022 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3023 .Case("+3dnowa", AMD3DNowAthlon) 3024 .Case("+3dnow", AMD3DNow) 3025 .Case("+mmx", MMX) 3026 .Default(NoMMX3DNow); 3027 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3028 3029 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3030 .Case("+xop", XOP) 3031 .Case("+fma4", FMA4) 3032 .Case("+sse4a", SSE4A) 3033 .Default(NoXOP); 3034 XOPLevel = std::max(XOPLevel, XLevel); 3035 } 3036 3037 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3038 // matches the selected sse level. 3039 if (FPMath == FP_SSE && SSELevel < SSE1) { 3040 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 3041 return false; 3042 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 3043 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 3044 return false; 3045 } 3046 3047 SimdDefaultAlign = 3048 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3049 return true; 3050 } 3051 3052 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3053 /// definitions for this particular subtarget. 3054 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3055 MacroBuilder &Builder) const { 3056 // Target identification. 3057 if (getTriple().getArch() == llvm::Triple::x86_64) { 3058 Builder.defineMacro("__amd64__"); 3059 Builder.defineMacro("__amd64"); 3060 Builder.defineMacro("__x86_64"); 3061 Builder.defineMacro("__x86_64__"); 3062 if (getTriple().getArchName() == "x86_64h") { 3063 Builder.defineMacro("__x86_64h"); 3064 Builder.defineMacro("__x86_64h__"); 3065 } 3066 } else { 3067 DefineStd(Builder, "i386", Opts); 3068 } 3069 3070 // Subtarget options. 3071 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3072 // truly should be based on -mtune options. 3073 switch (CPU) { 3074 case CK_Generic: 3075 break; 3076 case CK_i386: 3077 // The rest are coming from the i386 define above. 3078 Builder.defineMacro("__tune_i386__"); 3079 break; 3080 case CK_i486: 3081 case CK_WinChipC6: 3082 case CK_WinChip2: 3083 case CK_C3: 3084 defineCPUMacros(Builder, "i486"); 3085 break; 3086 case CK_PentiumMMX: 3087 Builder.defineMacro("__pentium_mmx__"); 3088 Builder.defineMacro("__tune_pentium_mmx__"); 3089 // Fallthrough 3090 case CK_i586: 3091 case CK_Pentium: 3092 defineCPUMacros(Builder, "i586"); 3093 defineCPUMacros(Builder, "pentium"); 3094 break; 3095 case CK_Pentium3: 3096 case CK_Pentium3M: 3097 case CK_PentiumM: 3098 Builder.defineMacro("__tune_pentium3__"); 3099 // Fallthrough 3100 case CK_Pentium2: 3101 case CK_C3_2: 3102 Builder.defineMacro("__tune_pentium2__"); 3103 // Fallthrough 3104 case CK_PentiumPro: 3105 Builder.defineMacro("__tune_i686__"); 3106 Builder.defineMacro("__tune_pentiumpro__"); 3107 // Fallthrough 3108 case CK_i686: 3109 Builder.defineMacro("__i686"); 3110 Builder.defineMacro("__i686__"); 3111 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3112 Builder.defineMacro("__pentiumpro"); 3113 Builder.defineMacro("__pentiumpro__"); 3114 break; 3115 case CK_Pentium4: 3116 case CK_Pentium4M: 3117 defineCPUMacros(Builder, "pentium4"); 3118 break; 3119 case CK_Yonah: 3120 case CK_Prescott: 3121 case CK_Nocona: 3122 defineCPUMacros(Builder, "nocona"); 3123 break; 3124 case CK_Core2: 3125 case CK_Penryn: 3126 defineCPUMacros(Builder, "core2"); 3127 break; 3128 case CK_Bonnell: 3129 defineCPUMacros(Builder, "atom"); 3130 break; 3131 case CK_Silvermont: 3132 defineCPUMacros(Builder, "slm"); 3133 break; 3134 case CK_Nehalem: 3135 case CK_Westmere: 3136 case CK_SandyBridge: 3137 case CK_IvyBridge: 3138 case CK_Haswell: 3139 case CK_Broadwell: 3140 // FIXME: Historically, we defined this legacy name, it would be nice to 3141 // remove it at some point. We've never exposed fine-grained names for 3142 // recent primary x86 CPUs, and we should keep it that way. 3143 defineCPUMacros(Builder, "corei7"); 3144 break; 3145 case CK_Skylake: 3146 // FIXME: Historically, we defined this legacy name, it would be nice to 3147 // remove it at some point. This is the only fine-grained CPU macro in the 3148 // main intel CPU line, and it would be better to not have these and force 3149 // people to use ISA macros. 3150 defineCPUMacros(Builder, "skx"); 3151 break; 3152 case CK_KNL: 3153 defineCPUMacros(Builder, "knl"); 3154 break; 3155 case CK_K6_2: 3156 Builder.defineMacro("__k6_2__"); 3157 Builder.defineMacro("__tune_k6_2__"); 3158 // Fallthrough 3159 case CK_K6_3: 3160 if (CPU != CK_K6_2) { // In case of fallthrough 3161 // FIXME: GCC may be enabling these in cases where some other k6 3162 // architecture is specified but -m3dnow is explicitly provided. The 3163 // exact semantics need to be determined and emulated here. 3164 Builder.defineMacro("__k6_3__"); 3165 Builder.defineMacro("__tune_k6_3__"); 3166 } 3167 // Fallthrough 3168 case CK_K6: 3169 defineCPUMacros(Builder, "k6"); 3170 break; 3171 case CK_Athlon: 3172 case CK_AthlonThunderbird: 3173 case CK_Athlon4: 3174 case CK_AthlonXP: 3175 case CK_AthlonMP: 3176 defineCPUMacros(Builder, "athlon"); 3177 if (SSELevel != NoSSE) { 3178 Builder.defineMacro("__athlon_sse__"); 3179 Builder.defineMacro("__tune_athlon_sse__"); 3180 } 3181 break; 3182 case CK_K8: 3183 case CK_K8SSE3: 3184 case CK_x86_64: 3185 case CK_Opteron: 3186 case CK_OpteronSSE3: 3187 case CK_Athlon64: 3188 case CK_Athlon64SSE3: 3189 case CK_AthlonFX: 3190 defineCPUMacros(Builder, "k8"); 3191 break; 3192 case CK_AMDFAM10: 3193 defineCPUMacros(Builder, "amdfam10"); 3194 break; 3195 case CK_BTVER1: 3196 defineCPUMacros(Builder, "btver1"); 3197 break; 3198 case CK_BTVER2: 3199 defineCPUMacros(Builder, "btver2"); 3200 break; 3201 case CK_BDVER1: 3202 defineCPUMacros(Builder, "bdver1"); 3203 break; 3204 case CK_BDVER2: 3205 defineCPUMacros(Builder, "bdver2"); 3206 break; 3207 case CK_BDVER3: 3208 defineCPUMacros(Builder, "bdver3"); 3209 break; 3210 case CK_BDVER4: 3211 defineCPUMacros(Builder, "bdver4"); 3212 break; 3213 case CK_Geode: 3214 defineCPUMacros(Builder, "geode"); 3215 break; 3216 } 3217 3218 // Target properties. 3219 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3220 3221 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3222 // functions in glibc header files that use FP Stack inline asm which the 3223 // backend can't deal with (PR879). 3224 Builder.defineMacro("__NO_MATH_INLINES"); 3225 3226 if (HasAES) 3227 Builder.defineMacro("__AES__"); 3228 3229 if (HasPCLMUL) 3230 Builder.defineMacro("__PCLMUL__"); 3231 3232 if (HasLZCNT) 3233 Builder.defineMacro("__LZCNT__"); 3234 3235 if (HasRDRND) 3236 Builder.defineMacro("__RDRND__"); 3237 3238 if (HasFSGSBASE) 3239 Builder.defineMacro("__FSGSBASE__"); 3240 3241 if (HasBMI) 3242 Builder.defineMacro("__BMI__"); 3243 3244 if (HasBMI2) 3245 Builder.defineMacro("__BMI2__"); 3246 3247 if (HasPOPCNT) 3248 Builder.defineMacro("__POPCNT__"); 3249 3250 if (HasRTM) 3251 Builder.defineMacro("__RTM__"); 3252 3253 if (HasPRFCHW) 3254 Builder.defineMacro("__PRFCHW__"); 3255 3256 if (HasRDSEED) 3257 Builder.defineMacro("__RDSEED__"); 3258 3259 if (HasADX) 3260 Builder.defineMacro("__ADX__"); 3261 3262 if (HasTBM) 3263 Builder.defineMacro("__TBM__"); 3264 3265 switch (XOPLevel) { 3266 case XOP: 3267 Builder.defineMacro("__XOP__"); 3268 case FMA4: 3269 Builder.defineMacro("__FMA4__"); 3270 case SSE4A: 3271 Builder.defineMacro("__SSE4A__"); 3272 case NoXOP: 3273 break; 3274 } 3275 3276 if (HasFMA) 3277 Builder.defineMacro("__FMA__"); 3278 3279 if (HasF16C) 3280 Builder.defineMacro("__F16C__"); 3281 3282 if (HasAVX512CD) 3283 Builder.defineMacro("__AVX512CD__"); 3284 if (HasAVX512ER) 3285 Builder.defineMacro("__AVX512ER__"); 3286 if (HasAVX512PF) 3287 Builder.defineMacro("__AVX512PF__"); 3288 if (HasAVX512DQ) 3289 Builder.defineMacro("__AVX512DQ__"); 3290 if (HasAVX512BW) 3291 Builder.defineMacro("__AVX512BW__"); 3292 if (HasAVX512VL) 3293 Builder.defineMacro("__AVX512VL__"); 3294 3295 if (HasSHA) 3296 Builder.defineMacro("__SHA__"); 3297 3298 if (HasXSAVE) 3299 Builder.defineMacro("__XSAVE__"); 3300 if (HasXSAVEOPT) 3301 Builder.defineMacro("__XSAVEOPT__"); 3302 if (HasXSAVEC) 3303 Builder.defineMacro("__XSAVEC__"); 3304 if (HasXSAVES) 3305 Builder.defineMacro("__XSAVES__"); 3306 3307 if (HasCX16) 3308 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3309 3310 // Each case falls through to the previous one here. 3311 switch (SSELevel) { 3312 case AVX512F: 3313 Builder.defineMacro("__AVX512F__"); 3314 case AVX2: 3315 Builder.defineMacro("__AVX2__"); 3316 case AVX: 3317 Builder.defineMacro("__AVX__"); 3318 case SSE42: 3319 Builder.defineMacro("__SSE4_2__"); 3320 case SSE41: 3321 Builder.defineMacro("__SSE4_1__"); 3322 case SSSE3: 3323 Builder.defineMacro("__SSSE3__"); 3324 case SSE3: 3325 Builder.defineMacro("__SSE3__"); 3326 case SSE2: 3327 Builder.defineMacro("__SSE2__"); 3328 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3329 case SSE1: 3330 Builder.defineMacro("__SSE__"); 3331 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3332 case NoSSE: 3333 break; 3334 } 3335 3336 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3337 switch (SSELevel) { 3338 case AVX512F: 3339 case AVX2: 3340 case AVX: 3341 case SSE42: 3342 case SSE41: 3343 case SSSE3: 3344 case SSE3: 3345 case SSE2: 3346 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3347 break; 3348 case SSE1: 3349 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3350 break; 3351 default: 3352 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3353 } 3354 } 3355 3356 // Each case falls through to the previous one here. 3357 switch (MMX3DNowLevel) { 3358 case AMD3DNowAthlon: 3359 Builder.defineMacro("__3dNOW_A__"); 3360 case AMD3DNow: 3361 Builder.defineMacro("__3dNOW__"); 3362 case MMX: 3363 Builder.defineMacro("__MMX__"); 3364 case NoMMX3DNow: 3365 break; 3366 } 3367 3368 if (CPU >= CK_i486) { 3369 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3370 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3371 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3372 } 3373 if (CPU >= CK_i586) 3374 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3375 } 3376 3377 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3378 return llvm::StringSwitch<bool>(Feature) 3379 .Case("aes", HasAES) 3380 .Case("avx", SSELevel >= AVX) 3381 .Case("avx2", SSELevel >= AVX2) 3382 .Case("avx512f", SSELevel >= AVX512F) 3383 .Case("avx512cd", HasAVX512CD) 3384 .Case("avx512er", HasAVX512ER) 3385 .Case("avx512pf", HasAVX512PF) 3386 .Case("avx512dq", HasAVX512DQ) 3387 .Case("avx512bw", HasAVX512BW) 3388 .Case("avx512vl", HasAVX512VL) 3389 .Case("bmi", HasBMI) 3390 .Case("bmi2", HasBMI2) 3391 .Case("cx16", HasCX16) 3392 .Case("f16c", HasF16C) 3393 .Case("fma", HasFMA) 3394 .Case("fma4", XOPLevel >= FMA4) 3395 .Case("fsgsbase", HasFSGSBASE) 3396 .Case("lzcnt", HasLZCNT) 3397 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3398 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3399 .Case("mmx", MMX3DNowLevel >= MMX) 3400 .Case("pclmul", HasPCLMUL) 3401 .Case("popcnt", HasPOPCNT) 3402 .Case("prfchw", HasPRFCHW) 3403 .Case("rdrnd", HasRDRND) 3404 .Case("rdseed", HasRDSEED) 3405 .Case("rtm", HasRTM) 3406 .Case("sha", HasSHA) 3407 .Case("sse", SSELevel >= SSE1) 3408 .Case("sse2", SSELevel >= SSE2) 3409 .Case("sse3", SSELevel >= SSE3) 3410 .Case("ssse3", SSELevel >= SSSE3) 3411 .Case("sse4.1", SSELevel >= SSE41) 3412 .Case("sse4.2", SSELevel >= SSE42) 3413 .Case("sse4a", XOPLevel >= SSE4A) 3414 .Case("tbm", HasTBM) 3415 .Case("x86", true) 3416 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3417 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3418 .Case("xop", XOPLevel >= XOP) 3419 .Case("xsave", HasXSAVE) 3420 .Case("xsavec", HasXSAVEC) 3421 .Case("xsaves", HasXSAVES) 3422 .Case("xsaveopt", HasXSAVEOPT) 3423 .Default(false); 3424 } 3425 3426 // We can't use a generic validation scheme for the features accepted here 3427 // versus subtarget features accepted in the target attribute because the 3428 // bitfield structure that's initialized in the runtime only supports the 3429 // below currently rather than the full range of subtarget features. (See 3430 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3431 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3432 return llvm::StringSwitch<bool>(FeatureStr) 3433 .Case("cmov", true) 3434 .Case("mmx", true) 3435 .Case("popcnt", true) 3436 .Case("sse", true) 3437 .Case("sse2", true) 3438 .Case("sse3", true) 3439 .Case("sse4.1", true) 3440 .Case("sse4.2", true) 3441 .Case("avx", true) 3442 .Case("avx2", true) 3443 .Case("sse4a", true) 3444 .Case("fma4", true) 3445 .Case("xop", true) 3446 .Case("fma", true) 3447 .Case("avx512f", true) 3448 .Case("bmi", true) 3449 .Case("bmi2", true) 3450 .Default(false); 3451 } 3452 3453 bool 3454 X86TargetInfo::validateAsmConstraint(const char *&Name, 3455 TargetInfo::ConstraintInfo &Info) const { 3456 switch (*Name) { 3457 default: return false; 3458 // Constant constraints. 3459 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3460 // instructions. 3461 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3462 // x86_64 instructions. 3463 case 's': 3464 Info.setRequiresImmediate(); 3465 return true; 3466 case 'I': 3467 Info.setRequiresImmediate(0, 31); 3468 return true; 3469 case 'J': 3470 Info.setRequiresImmediate(0, 63); 3471 return true; 3472 case 'K': 3473 Info.setRequiresImmediate(-128, 127); 3474 return true; 3475 case 'L': 3476 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3477 return true; 3478 case 'M': 3479 Info.setRequiresImmediate(0, 3); 3480 return true; 3481 case 'N': 3482 Info.setRequiresImmediate(0, 255); 3483 return true; 3484 case 'O': 3485 Info.setRequiresImmediate(0, 127); 3486 return true; 3487 // Register constraints. 3488 case 'Y': // 'Y' is the first character for several 2-character constraints. 3489 // Shift the pointer to the second character of the constraint. 3490 Name++; 3491 switch (*Name) { 3492 default: 3493 return false; 3494 case '0': // First SSE register. 3495 case 't': // Any SSE register, when SSE2 is enabled. 3496 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3497 case 'm': // Any MMX register, when inter-unit moves enabled. 3498 Info.setAllowsRegister(); 3499 return true; 3500 } 3501 case 'f': // Any x87 floating point stack register. 3502 // Constraint 'f' cannot be used for output operands. 3503 if (Info.ConstraintStr[0] == '=') 3504 return false; 3505 Info.setAllowsRegister(); 3506 return true; 3507 case 'a': // eax. 3508 case 'b': // ebx. 3509 case 'c': // ecx. 3510 case 'd': // edx. 3511 case 'S': // esi. 3512 case 'D': // edi. 3513 case 'A': // edx:eax. 3514 case 't': // Top of floating point stack. 3515 case 'u': // Second from top of floating point stack. 3516 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3517 case 'y': // Any MMX register. 3518 case 'x': // Any SSE register. 3519 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3520 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3521 case 'l': // "Index" registers: any general register that can be used as an 3522 // index in a base+index memory access. 3523 Info.setAllowsRegister(); 3524 return true; 3525 // Floating point constant constraints. 3526 case 'C': // SSE floating point constant. 3527 case 'G': // x87 floating point constant. 3528 return true; 3529 } 3530 } 3531 3532 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3533 unsigned Size) const { 3534 // Strip off constraint modifiers. 3535 while (Constraint[0] == '=' || 3536 Constraint[0] == '+' || 3537 Constraint[0] == '&') 3538 Constraint = Constraint.substr(1); 3539 3540 return validateOperandSize(Constraint, Size); 3541 } 3542 3543 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3544 unsigned Size) const { 3545 return validateOperandSize(Constraint, Size); 3546 } 3547 3548 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3549 unsigned Size) const { 3550 switch (Constraint[0]) { 3551 default: break; 3552 case 'y': 3553 return Size <= 64; 3554 case 'f': 3555 case 't': 3556 case 'u': 3557 return Size <= 128; 3558 case 'x': 3559 if (SSELevel >= AVX512F) 3560 // 512-bit zmm registers can be used if target supports AVX512F. 3561 return Size <= 512U; 3562 else if (SSELevel >= AVX) 3563 // 256-bit ymm registers can be used if target supports AVX. 3564 return Size <= 256U; 3565 return Size <= 128U; 3566 case 'Y': 3567 // 'Y' is the first character for several 2-character constraints. 3568 switch (Constraint[1]) { 3569 default: break; 3570 case 'm': 3571 // 'Ym' is synonymous with 'y'. 3572 return Size <= 64; 3573 case 'i': 3574 case 't': 3575 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3576 if (SSELevel >= AVX512F) 3577 return Size <= 512U; 3578 else if (SSELevel >= AVX) 3579 return Size <= 256U; 3580 return SSELevel >= SSE2 && Size <= 128U; 3581 } 3582 3583 } 3584 3585 return true; 3586 } 3587 3588 std::string 3589 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3590 switch (*Constraint) { 3591 case 'a': return std::string("{ax}"); 3592 case 'b': return std::string("{bx}"); 3593 case 'c': return std::string("{cx}"); 3594 case 'd': return std::string("{dx}"); 3595 case 'S': return std::string("{si}"); 3596 case 'D': return std::string("{di}"); 3597 case 'p': // address 3598 return std::string("im"); 3599 case 't': // top of floating point stack. 3600 return std::string("{st}"); 3601 case 'u': // second from top of floating point stack. 3602 return std::string("{st(1)}"); // second from top of floating point stack. 3603 default: 3604 return std::string(1, *Constraint); 3605 } 3606 } 3607 3608 // X86-32 generic target 3609 class X86_32TargetInfo : public X86TargetInfo { 3610 public: 3611 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3612 DoubleAlign = LongLongAlign = 32; 3613 LongDoubleWidth = 96; 3614 LongDoubleAlign = 32; 3615 SuitableAlign = 128; 3616 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3617 SizeType = UnsignedInt; 3618 PtrDiffType = SignedInt; 3619 IntPtrType = SignedInt; 3620 RegParmMax = 3; 3621 3622 // Use fpret for all types. 3623 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3624 (1 << TargetInfo::Double) | 3625 (1 << TargetInfo::LongDouble)); 3626 3627 // x86-32 has atomics up to 8 bytes 3628 // FIXME: Check that we actually have cmpxchg8b before setting 3629 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3630 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3631 } 3632 BuiltinVaListKind getBuiltinVaListKind() const override { 3633 return TargetInfo::CharPtrBuiltinVaList; 3634 } 3635 3636 int getEHDataRegisterNumber(unsigned RegNo) const override { 3637 if (RegNo == 0) return 0; 3638 if (RegNo == 1) return 2; 3639 return -1; 3640 } 3641 bool validateOperandSize(StringRef Constraint, 3642 unsigned Size) const override { 3643 switch (Constraint[0]) { 3644 default: break; 3645 case 'R': 3646 case 'q': 3647 case 'Q': 3648 case 'a': 3649 case 'b': 3650 case 'c': 3651 case 'd': 3652 case 'S': 3653 case 'D': 3654 return Size <= 32; 3655 case 'A': 3656 return Size <= 64; 3657 } 3658 3659 return X86TargetInfo::validateOperandSize(Constraint, Size); 3660 } 3661 }; 3662 3663 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3664 public: 3665 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3666 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3667 3668 unsigned getFloatEvalMethod() const override { 3669 unsigned Major, Minor, Micro; 3670 getTriple().getOSVersion(Major, Minor, Micro); 3671 // New NetBSD uses the default rounding mode. 3672 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3673 return X86_32TargetInfo::getFloatEvalMethod(); 3674 // NetBSD before 6.99.26 defaults to "double" rounding. 3675 return 1; 3676 } 3677 }; 3678 3679 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3680 public: 3681 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3682 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3683 SizeType = UnsignedLong; 3684 IntPtrType = SignedLong; 3685 PtrDiffType = SignedLong; 3686 } 3687 }; 3688 3689 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3690 public: 3691 BitrigI386TargetInfo(const llvm::Triple &Triple) 3692 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3693 SizeType = UnsignedLong; 3694 IntPtrType = SignedLong; 3695 PtrDiffType = SignedLong; 3696 } 3697 }; 3698 3699 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3700 public: 3701 DarwinI386TargetInfo(const llvm::Triple &Triple) 3702 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3703 LongDoubleWidth = 128; 3704 LongDoubleAlign = 128; 3705 SuitableAlign = 128; 3706 SizeType = UnsignedLong; 3707 IntPtrType = SignedLong; 3708 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3709 HasAlignMac68kSupport = true; 3710 } 3711 3712 bool handleTargetFeatures(std::vector<std::string> &Features, 3713 DiagnosticsEngine &Diags) override { 3714 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3715 Diags)) 3716 return false; 3717 // We now know the features we have: we can decide how to align vectors. 3718 MaxVectorAlign = 3719 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3720 return true; 3721 } 3722 }; 3723 3724 // x86-32 Windows target 3725 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3726 public: 3727 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3728 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3729 WCharType = UnsignedShort; 3730 DoubleAlign = LongLongAlign = 64; 3731 bool IsWinCOFF = 3732 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3733 DataLayoutString = IsWinCOFF 3734 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3735 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3736 } 3737 void getTargetDefines(const LangOptions &Opts, 3738 MacroBuilder &Builder) const override { 3739 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3740 } 3741 }; 3742 3743 // x86-32 Windows Visual Studio target 3744 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3745 public: 3746 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3747 : WindowsX86_32TargetInfo(Triple) { 3748 LongDoubleWidth = LongDoubleAlign = 64; 3749 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3750 } 3751 void getTargetDefines(const LangOptions &Opts, 3752 MacroBuilder &Builder) const override { 3753 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3754 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3755 // The value of the following reflects processor type. 3756 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3757 // We lost the original triple, so we use the default. 3758 Builder.defineMacro("_M_IX86", "600"); 3759 } 3760 }; 3761 3762 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3763 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3764 // supports __declspec natively under -fms-extensions, but we define a no-op 3765 // __declspec macro anyway for pre-processor compatibility. 3766 if (Opts.MicrosoftExt) 3767 Builder.defineMacro("__declspec", "__declspec"); 3768 else 3769 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3770 3771 if (!Opts.MicrosoftExt) { 3772 // Provide macros for all the calling convention keywords. Provide both 3773 // single and double underscore prefixed variants. These are available on 3774 // x64 as well as x86, even though they have no effect. 3775 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3776 for (const char *CC : CCs) { 3777 std::string GCCSpelling = "__attribute__((__"; 3778 GCCSpelling += CC; 3779 GCCSpelling += "__))"; 3780 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3781 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3782 } 3783 } 3784 } 3785 3786 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3787 Builder.defineMacro("__MSVCRT__"); 3788 Builder.defineMacro("__MINGW32__"); 3789 addCygMingDefines(Opts, Builder); 3790 } 3791 3792 // x86-32 MinGW target 3793 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3794 public: 3795 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3796 : WindowsX86_32TargetInfo(Triple) {} 3797 void getTargetDefines(const LangOptions &Opts, 3798 MacroBuilder &Builder) const override { 3799 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3800 DefineStd(Builder, "WIN32", Opts); 3801 DefineStd(Builder, "WINNT", Opts); 3802 Builder.defineMacro("_X86_"); 3803 addMinGWDefines(Opts, Builder); 3804 } 3805 }; 3806 3807 // x86-32 Cygwin target 3808 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3809 public: 3810 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3811 : X86_32TargetInfo(Triple) { 3812 TLSSupported = false; 3813 WCharType = UnsignedShort; 3814 DoubleAlign = LongLongAlign = 64; 3815 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3816 } 3817 void getTargetDefines(const LangOptions &Opts, 3818 MacroBuilder &Builder) const override { 3819 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3820 Builder.defineMacro("_X86_"); 3821 Builder.defineMacro("__CYGWIN__"); 3822 Builder.defineMacro("__CYGWIN32__"); 3823 addCygMingDefines(Opts, Builder); 3824 DefineStd(Builder, "unix", Opts); 3825 if (Opts.CPlusPlus) 3826 Builder.defineMacro("_GNU_SOURCE"); 3827 } 3828 }; 3829 3830 // x86-32 Haiku target 3831 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3832 public: 3833 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3834 SizeType = UnsignedLong; 3835 IntPtrType = SignedLong; 3836 PtrDiffType = SignedLong; 3837 ProcessIDType = SignedLong; 3838 this->UserLabelPrefix = ""; 3839 this->TLSSupported = false; 3840 } 3841 void getTargetDefines(const LangOptions &Opts, 3842 MacroBuilder &Builder) const override { 3843 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3844 Builder.defineMacro("__INTEL__"); 3845 Builder.defineMacro("__HAIKU__"); 3846 } 3847 }; 3848 3849 // RTEMS Target 3850 template<typename Target> 3851 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3852 protected: 3853 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3854 MacroBuilder &Builder) const override { 3855 // RTEMS defines; list based off of gcc output 3856 3857 Builder.defineMacro("__rtems__"); 3858 Builder.defineMacro("__ELF__"); 3859 } 3860 3861 public: 3862 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3863 this->UserLabelPrefix = ""; 3864 3865 switch (Triple.getArch()) { 3866 default: 3867 case llvm::Triple::x86: 3868 // this->MCountName = ".mcount"; 3869 break; 3870 case llvm::Triple::mips: 3871 case llvm::Triple::mipsel: 3872 case llvm::Triple::ppc: 3873 case llvm::Triple::ppc64: 3874 case llvm::Triple::ppc64le: 3875 // this->MCountName = "_mcount"; 3876 break; 3877 case llvm::Triple::arm: 3878 // this->MCountName = "__mcount"; 3879 break; 3880 } 3881 } 3882 }; 3883 3884 // x86-32 RTEMS target 3885 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3886 public: 3887 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3888 SizeType = UnsignedLong; 3889 IntPtrType = SignedLong; 3890 PtrDiffType = SignedLong; 3891 this->UserLabelPrefix = ""; 3892 } 3893 void getTargetDefines(const LangOptions &Opts, 3894 MacroBuilder &Builder) const override { 3895 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3896 Builder.defineMacro("__INTEL__"); 3897 Builder.defineMacro("__rtems__"); 3898 } 3899 }; 3900 3901 // x86-64 generic target 3902 class X86_64TargetInfo : public X86TargetInfo { 3903 public: 3904 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3905 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3906 bool IsWinCOFF = 3907 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3908 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3909 LongDoubleWidth = 128; 3910 LongDoubleAlign = 128; 3911 LargeArrayMinWidth = 128; 3912 LargeArrayAlign = 128; 3913 SuitableAlign = 128; 3914 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3915 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3916 IntPtrType = IsX32 ? SignedInt : SignedLong; 3917 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3918 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3919 RegParmMax = 6; 3920 3921 // Pointers are 32-bit in x32. 3922 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3923 : IsWinCOFF 3924 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3925 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3926 3927 // Use fpret only for long double. 3928 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3929 3930 // Use fp2ret for _Complex long double. 3931 ComplexLongDoubleUsesFP2Ret = true; 3932 3933 // Make __builtin_ms_va_list available. 3934 HasBuiltinMSVaList = true; 3935 3936 // x86-64 has atomics up to 16 bytes. 3937 MaxAtomicPromoteWidth = 128; 3938 MaxAtomicInlineWidth = 128; 3939 } 3940 BuiltinVaListKind getBuiltinVaListKind() const override { 3941 return TargetInfo::X86_64ABIBuiltinVaList; 3942 } 3943 3944 int getEHDataRegisterNumber(unsigned RegNo) const override { 3945 if (RegNo == 0) return 0; 3946 if (RegNo == 1) return 1; 3947 return -1; 3948 } 3949 3950 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3951 return (CC == CC_C || 3952 CC == CC_X86VectorCall || 3953 CC == CC_IntelOclBicc || 3954 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3955 } 3956 3957 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3958 return CC_C; 3959 } 3960 3961 // for x32 we need it here explicitly 3962 bool hasInt128Type() const override { return true; } 3963 }; 3964 3965 // x86-64 Windows target 3966 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3967 public: 3968 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3969 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3970 WCharType = UnsignedShort; 3971 LongWidth = LongAlign = 32; 3972 DoubleAlign = LongLongAlign = 64; 3973 IntMaxType = SignedLongLong; 3974 Int64Type = SignedLongLong; 3975 SizeType = UnsignedLongLong; 3976 PtrDiffType = SignedLongLong; 3977 IntPtrType = SignedLongLong; 3978 this->UserLabelPrefix = ""; 3979 } 3980 3981 void getTargetDefines(const LangOptions &Opts, 3982 MacroBuilder &Builder) const override { 3983 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3984 Builder.defineMacro("_WIN64"); 3985 } 3986 3987 BuiltinVaListKind getBuiltinVaListKind() const override { 3988 return TargetInfo::CharPtrBuiltinVaList; 3989 } 3990 3991 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3992 switch (CC) { 3993 case CC_X86StdCall: 3994 case CC_X86ThisCall: 3995 case CC_X86FastCall: 3996 return CCCR_Ignore; 3997 case CC_C: 3998 case CC_X86VectorCall: 3999 case CC_IntelOclBicc: 4000 case CC_X86_64SysV: 4001 return CCCR_OK; 4002 default: 4003 return CCCR_Warning; 4004 } 4005 } 4006 }; 4007 4008 // x86-64 Windows Visual Studio target 4009 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4010 public: 4011 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 4012 : WindowsX86_64TargetInfo(Triple) { 4013 LongDoubleWidth = LongDoubleAlign = 64; 4014 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4015 } 4016 void getTargetDefines(const LangOptions &Opts, 4017 MacroBuilder &Builder) const override { 4018 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4019 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4020 Builder.defineMacro("_M_X64", "100"); 4021 Builder.defineMacro("_M_AMD64", "100"); 4022 } 4023 }; 4024 4025 // x86-64 MinGW target 4026 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4027 public: 4028 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4029 : WindowsX86_64TargetInfo(Triple) {} 4030 void getTargetDefines(const LangOptions &Opts, 4031 MacroBuilder &Builder) const override { 4032 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4033 DefineStd(Builder, "WIN64", Opts); 4034 Builder.defineMacro("__MINGW64__"); 4035 addMinGWDefines(Opts, Builder); 4036 4037 // GCC defines this macro when it is using __gxx_personality_seh0. 4038 if (!Opts.SjLjExceptions) 4039 Builder.defineMacro("__SEH__"); 4040 } 4041 }; 4042 4043 // x86-64 Cygwin target 4044 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4045 public: 4046 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4047 : X86_64TargetInfo(Triple) { 4048 TLSSupported = false; 4049 WCharType = UnsignedShort; 4050 } 4051 void getTargetDefines(const LangOptions &Opts, 4052 MacroBuilder &Builder) const override { 4053 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4054 Builder.defineMacro("__x86_64__"); 4055 Builder.defineMacro("__CYGWIN__"); 4056 Builder.defineMacro("__CYGWIN64__"); 4057 addCygMingDefines(Opts, Builder); 4058 DefineStd(Builder, "unix", Opts); 4059 if (Opts.CPlusPlus) 4060 Builder.defineMacro("_GNU_SOURCE"); 4061 4062 // GCC defines this macro when it is using __gxx_personality_seh0. 4063 if (!Opts.SjLjExceptions) 4064 Builder.defineMacro("__SEH__"); 4065 } 4066 }; 4067 4068 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4069 public: 4070 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4071 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4072 Int64Type = SignedLongLong; 4073 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4074 llvm::Triple T = llvm::Triple(Triple); 4075 if (T.isiOS()) 4076 UseSignedCharForObjCBool = false; 4077 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 4078 } 4079 4080 bool handleTargetFeatures(std::vector<std::string> &Features, 4081 DiagnosticsEngine &Diags) override { 4082 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4083 Diags)) 4084 return false; 4085 // We now know the features we have: we can decide how to align vectors. 4086 MaxVectorAlign = 4087 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4088 return true; 4089 } 4090 }; 4091 4092 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4093 public: 4094 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4095 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4096 IntMaxType = SignedLongLong; 4097 Int64Type = SignedLongLong; 4098 } 4099 }; 4100 4101 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4102 public: 4103 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4104 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4105 IntMaxType = SignedLongLong; 4106 Int64Type = SignedLongLong; 4107 } 4108 }; 4109 4110 class ARMTargetInfo : public TargetInfo { 4111 // Possible FPU choices. 4112 enum FPUMode { 4113 VFP2FPU = (1 << 0), 4114 VFP3FPU = (1 << 1), 4115 VFP4FPU = (1 << 2), 4116 NeonFPU = (1 << 3), 4117 FPARMV8 = (1 << 4) 4118 }; 4119 4120 // Possible HWDiv features. 4121 enum HWDivMode { 4122 HWDivThumb = (1 << 0), 4123 HWDivARM = (1 << 1) 4124 }; 4125 4126 static bool FPUModeIsVFP(FPUMode Mode) { 4127 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4128 } 4129 4130 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4131 static const char * const GCCRegNames[]; 4132 4133 std::string ABI, CPU; 4134 4135 StringRef CPUProfile; 4136 StringRef CPUAttr; 4137 4138 enum { 4139 FP_Default, 4140 FP_VFP, 4141 FP_Neon 4142 } FPMath; 4143 4144 unsigned ArchISA; 4145 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4146 unsigned ArchProfile; 4147 unsigned ArchVersion; 4148 4149 unsigned FPU : 5; 4150 4151 unsigned IsAAPCS : 1; 4152 unsigned HWDiv : 2; 4153 4154 // Initialized via features. 4155 unsigned SoftFloat : 1; 4156 unsigned SoftFloatABI : 1; 4157 4158 unsigned CRC : 1; 4159 unsigned Crypto : 1; 4160 unsigned DSP : 1; 4161 unsigned Unaligned : 1; 4162 4163 enum { 4164 LDREX_B = (1 << 0), /// byte (8-bit) 4165 LDREX_H = (1 << 1), /// half (16-bit) 4166 LDREX_W = (1 << 2), /// word (32-bit) 4167 LDREX_D = (1 << 3), /// double (64-bit) 4168 }; 4169 4170 uint32_t LDREX; 4171 4172 // ACLE 6.5.1 Hardware floating point 4173 enum { 4174 HW_FP_HP = (1 << 1), /// half (16-bit) 4175 HW_FP_SP = (1 << 2), /// single (32-bit) 4176 HW_FP_DP = (1 << 3), /// double (64-bit) 4177 }; 4178 uint32_t HW_FP; 4179 4180 static const Builtin::Info BuiltinInfo[]; 4181 4182 void setABIAAPCS() { 4183 IsAAPCS = true; 4184 4185 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4186 const llvm::Triple &T = getTriple(); 4187 4188 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4189 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4190 T.getOS() == llvm::Triple::Bitrig) 4191 SizeType = UnsignedLong; 4192 else 4193 SizeType = UnsignedInt; 4194 4195 switch (T.getOS()) { 4196 case llvm::Triple::NetBSD: 4197 WCharType = SignedInt; 4198 break; 4199 case llvm::Triple::Win32: 4200 WCharType = UnsignedShort; 4201 break; 4202 case llvm::Triple::Linux: 4203 default: 4204 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4205 WCharType = UnsignedInt; 4206 break; 4207 } 4208 4209 UseBitFieldTypeAlignment = true; 4210 4211 ZeroLengthBitfieldBoundary = 0; 4212 4213 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4214 // so set preferred for small types to 32. 4215 if (T.isOSBinFormatMachO()) { 4216 DataLayoutString = 4217 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4218 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4219 } else if (T.isOSWindows()) { 4220 assert(!BigEndian && "Windows on ARM does not support big endian"); 4221 DataLayoutString = "e" 4222 "-m:w" 4223 "-p:32:32" 4224 "-i64:64" 4225 "-v128:64:128" 4226 "-a:0:32" 4227 "-n32" 4228 "-S64"; 4229 } else if (T.isOSNaCl()) { 4230 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4231 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4232 } else { 4233 DataLayoutString = 4234 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4235 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4236 } 4237 4238 // FIXME: Enumerated types are variable width in straight AAPCS. 4239 } 4240 4241 void setABIAPCS() { 4242 const llvm::Triple &T = getTriple(); 4243 4244 IsAAPCS = false; 4245 4246 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4247 4248 // size_t is unsigned int on FreeBSD. 4249 if (T.getOS() == llvm::Triple::FreeBSD) 4250 SizeType = UnsignedInt; 4251 else 4252 SizeType = UnsignedLong; 4253 4254 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4255 WCharType = SignedInt; 4256 4257 // Do not respect the alignment of bit-field types when laying out 4258 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4259 UseBitFieldTypeAlignment = false; 4260 4261 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4262 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4263 /// gcc. 4264 ZeroLengthBitfieldBoundary = 32; 4265 4266 if (T.isOSBinFormatMachO()) 4267 DataLayoutString = 4268 BigEndian 4269 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4270 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4271 else 4272 DataLayoutString = 4273 BigEndian 4274 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4275 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4276 4277 // FIXME: Override "preferred align" for double and long long. 4278 } 4279 4280 void setArchInfo() { 4281 StringRef ArchName = getTriple().getArchName(); 4282 4283 ArchISA = llvm::ARM::parseArchISA(ArchName); 4284 CPU = llvm::ARM::getDefaultCPU(ArchName); 4285 unsigned AK = llvm::ARM::parseArch(ArchName); 4286 if (AK != llvm::ARM::AK_INVALID) 4287 ArchKind = AK; 4288 setArchInfo(ArchKind); 4289 } 4290 4291 void setArchInfo(unsigned Kind) { 4292 StringRef SubArch; 4293 4294 // cache TargetParser info 4295 ArchKind = Kind; 4296 SubArch = llvm::ARM::getSubArch(ArchKind); 4297 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4298 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4299 4300 // cache CPU related strings 4301 CPUAttr = getCPUAttr(); 4302 CPUProfile = getCPUProfile(); 4303 } 4304 4305 void setAtomic() { 4306 // when triple does not specify a sub arch, 4307 // then we are not using inline atomics 4308 bool ShouldUseInlineAtomic = 4309 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4310 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4311 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4312 if (ArchProfile == llvm::ARM::PK_M) { 4313 MaxAtomicPromoteWidth = 32; 4314 if (ShouldUseInlineAtomic) 4315 MaxAtomicInlineWidth = 32; 4316 } 4317 else { 4318 MaxAtomicPromoteWidth = 64; 4319 if (ShouldUseInlineAtomic) 4320 MaxAtomicInlineWidth = 64; 4321 } 4322 } 4323 4324 bool isThumb() const { 4325 return (ArchISA == llvm::ARM::IK_THUMB); 4326 } 4327 4328 bool supportsThumb() const { 4329 return CPUAttr.count('T') || ArchVersion >= 6; 4330 } 4331 4332 bool supportsThumb2() const { 4333 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4334 } 4335 4336 StringRef getCPUAttr() const { 4337 // For most sub-arches, the build attribute CPU name is enough. 4338 // For Cortex variants, it's slightly different. 4339 switch(ArchKind) { 4340 default: 4341 return llvm::ARM::getCPUAttr(ArchKind); 4342 case llvm::ARM::AK_ARMV6M: 4343 case llvm::ARM::AK_ARMV6SM: 4344 case llvm::ARM::AK_ARMV6HL: 4345 return "6M"; 4346 case llvm::ARM::AK_ARMV7S: 4347 return "7S"; 4348 case llvm::ARM::AK_ARMV7: 4349 case llvm::ARM::AK_ARMV7A: 4350 case llvm::ARM::AK_ARMV7L: 4351 case llvm::ARM::AK_ARMV7HL: 4352 return "7A"; 4353 case llvm::ARM::AK_ARMV7R: 4354 return "7R"; 4355 case llvm::ARM::AK_ARMV7M: 4356 return "7M"; 4357 case llvm::ARM::AK_ARMV7EM: 4358 return "7EM"; 4359 case llvm::ARM::AK_ARMV8A: 4360 return "8A"; 4361 case llvm::ARM::AK_ARMV8_1A: 4362 return "8_1A"; 4363 } 4364 } 4365 4366 StringRef getCPUProfile() const { 4367 switch(ArchProfile) { 4368 case llvm::ARM::PK_A: 4369 return "A"; 4370 case llvm::ARM::PK_R: 4371 return "R"; 4372 case llvm::ARM::PK_M: 4373 return "M"; 4374 default: 4375 return ""; 4376 } 4377 } 4378 4379 public: 4380 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4381 : TargetInfo(Triple), FPMath(FP_Default), 4382 IsAAPCS(true), LDREX(0), HW_FP(0) { 4383 BigEndian = IsBigEndian; 4384 4385 switch (getTriple().getOS()) { 4386 case llvm::Triple::NetBSD: 4387 PtrDiffType = SignedLong; 4388 break; 4389 default: 4390 PtrDiffType = SignedInt; 4391 break; 4392 } 4393 4394 // Cache arch related info. 4395 setArchInfo(); 4396 4397 // {} in inline assembly are neon specifiers, not assembly variant 4398 // specifiers. 4399 NoAsmVariants = true; 4400 4401 // FIXME: This duplicates code from the driver that sets the -target-abi 4402 // option - this code is used if -target-abi isn't passed and should 4403 // be unified in some way. 4404 if (Triple.isOSBinFormatMachO()) { 4405 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4406 // the frontend matches that. 4407 if (Triple.getEnvironment() == llvm::Triple::EABI || 4408 Triple.getOS() == llvm::Triple::UnknownOS || 4409 StringRef(CPU).startswith("cortex-m")) { 4410 setABI("aapcs"); 4411 } else { 4412 setABI("apcs-gnu"); 4413 } 4414 } else if (Triple.isOSWindows()) { 4415 // FIXME: this is invalid for WindowsCE 4416 setABI("aapcs"); 4417 } else { 4418 // Select the default based on the platform. 4419 switch (Triple.getEnvironment()) { 4420 case llvm::Triple::Android: 4421 case llvm::Triple::GNUEABI: 4422 case llvm::Triple::GNUEABIHF: 4423 setABI("aapcs-linux"); 4424 break; 4425 case llvm::Triple::EABIHF: 4426 case llvm::Triple::EABI: 4427 setABI("aapcs"); 4428 break; 4429 case llvm::Triple::GNU: 4430 setABI("apcs-gnu"); 4431 break; 4432 default: 4433 if (Triple.getOS() == llvm::Triple::NetBSD) 4434 setABI("apcs-gnu"); 4435 else 4436 setABI("aapcs"); 4437 break; 4438 } 4439 } 4440 4441 // ARM targets default to using the ARM C++ ABI. 4442 TheCXXABI.set(TargetCXXABI::GenericARM); 4443 4444 // ARM has atomics up to 8 bytes 4445 setAtomic(); 4446 4447 // Do force alignment of members that follow zero length bitfields. If 4448 // the alignment of the zero-length bitfield is greater than the member 4449 // that follows it, `bar', `bar' will be aligned as the type of the 4450 // zero length bitfield. 4451 UseZeroLengthBitfieldAlignment = true; 4452 } 4453 4454 StringRef getABI() const override { return ABI; } 4455 4456 bool setABI(const std::string &Name) override { 4457 ABI = Name; 4458 4459 // The defaults (above) are for AAPCS, check if we need to change them. 4460 // 4461 // FIXME: We need support for -meabi... we could just mangle it into the 4462 // name. 4463 if (Name == "apcs-gnu") { 4464 setABIAPCS(); 4465 return true; 4466 } 4467 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4468 setABIAAPCS(); 4469 return true; 4470 } 4471 return false; 4472 } 4473 4474 // FIXME: This should be based on Arch attributes, not CPU names. 4475 bool 4476 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4477 StringRef CPU, 4478 const std::vector<std::string> &FeaturesVec) const override { 4479 4480 std::vector<const char*> TargetFeatures; 4481 4482 // get default FPU features 4483 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU); 4484 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4485 4486 // get default Extension features 4487 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU); 4488 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4489 4490 for (const char *Feature : TargetFeatures) 4491 if (Feature[0] == '+') 4492 Features[Feature+1] = true; 4493 4494 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4495 } 4496 4497 bool handleTargetFeatures(std::vector<std::string> &Features, 4498 DiagnosticsEngine &Diags) override { 4499 FPU = 0; 4500 CRC = 0; 4501 Crypto = 0; 4502 DSP = 0; 4503 Unaligned = 1; 4504 SoftFloat = SoftFloatABI = false; 4505 HWDiv = 0; 4506 4507 // This does not diagnose illegal cases like having both 4508 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4509 uint32_t HW_FP_remove = 0; 4510 for (const auto &Feature : Features) { 4511 if (Feature == "+soft-float") { 4512 SoftFloat = true; 4513 } else if (Feature == "+soft-float-abi") { 4514 SoftFloatABI = true; 4515 } else if (Feature == "+vfp2") { 4516 FPU |= VFP2FPU; 4517 HW_FP |= HW_FP_SP | HW_FP_DP; 4518 } else if (Feature == "+vfp3") { 4519 FPU |= VFP3FPU; 4520 HW_FP |= HW_FP_SP | HW_FP_DP; 4521 } else if (Feature == "+vfp4") { 4522 FPU |= VFP4FPU; 4523 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4524 } else if (Feature == "+fp-armv8") { 4525 FPU |= FPARMV8; 4526 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4527 } else if (Feature == "+neon") { 4528 FPU |= NeonFPU; 4529 HW_FP |= HW_FP_SP | HW_FP_DP; 4530 } else if (Feature == "+hwdiv") { 4531 HWDiv |= HWDivThumb; 4532 } else if (Feature == "+hwdiv-arm") { 4533 HWDiv |= HWDivARM; 4534 } else if (Feature == "+crc") { 4535 CRC = 1; 4536 } else if (Feature == "+crypto") { 4537 Crypto = 1; 4538 } else if (Feature == "+t2dsp") { 4539 DSP = 1; 4540 } else if (Feature == "+fp-only-sp") { 4541 HW_FP_remove |= HW_FP_DP | HW_FP_HP; 4542 } else if (Feature == "+strict-align") { 4543 Unaligned = 0; 4544 } else if (Feature == "+fp16") { 4545 HW_FP |= HW_FP_HP; 4546 } 4547 } 4548 HW_FP &= ~HW_FP_remove; 4549 4550 switch (ArchVersion) { 4551 case 6: 4552 if (ArchProfile == llvm::ARM::PK_M) 4553 LDREX = 0; 4554 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4555 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4556 else 4557 LDREX = LDREX_W; 4558 break; 4559 case 7: 4560 if (ArchProfile == llvm::ARM::PK_M) 4561 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4562 else 4563 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4564 break; 4565 case 8: 4566 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4567 } 4568 4569 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4570 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4571 return false; 4572 } 4573 4574 if (FPMath == FP_Neon) 4575 Features.push_back("+neonfp"); 4576 else if (FPMath == FP_VFP) 4577 Features.push_back("-neonfp"); 4578 4579 // Remove front-end specific options which the backend handles differently. 4580 auto Feature = 4581 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4582 if (Feature != Features.end()) 4583 Features.erase(Feature); 4584 4585 return true; 4586 } 4587 4588 bool hasFeature(StringRef Feature) const override { 4589 return llvm::StringSwitch<bool>(Feature) 4590 .Case("arm", true) 4591 .Case("aarch32", true) 4592 .Case("softfloat", SoftFloat) 4593 .Case("thumb", isThumb()) 4594 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4595 .Case("hwdiv", HWDiv & HWDivThumb) 4596 .Case("hwdiv-arm", HWDiv & HWDivARM) 4597 .Default(false); 4598 } 4599 4600 bool setCPU(const std::string &Name) override { 4601 if (Name != "generic") 4602 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4603 4604 if (ArchKind == llvm::ARM::AK_INVALID) 4605 return false; 4606 setAtomic(); 4607 CPU = Name; 4608 return true; 4609 } 4610 4611 bool setFPMath(StringRef Name) override; 4612 4613 void getTargetDefines(const LangOptions &Opts, 4614 MacroBuilder &Builder) const override { 4615 // Target identification. 4616 Builder.defineMacro("__arm"); 4617 Builder.defineMacro("__arm__"); 4618 4619 // Target properties. 4620 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4621 if (!CPUAttr.empty()) 4622 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4623 4624 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4625 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4626 Builder.defineMacro("__ARM_ARCH", llvm::utostr(ArchVersion)); 4627 4628 if (ArchVersion >= 8) { 4629 // ACLE 6.5.7 Crypto Extension 4630 if (Crypto) 4631 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4632 // ACLE 6.5.8 CRC32 Extension 4633 if (CRC) 4634 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4635 // ACLE 6.5.10 Numeric Maximum and Minimum 4636 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4637 // ACLE 6.5.9 Directed Rounding 4638 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4639 } 4640 4641 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4642 // is not defined for the M-profile. 4643 // NOTE that the deffault profile is assumed to be 'A' 4644 if (CPUProfile.empty() || CPUProfile != "M") 4645 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4646 4647 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4648 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4649 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4650 if (supportsThumb2()) 4651 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4652 else if (supportsThumb()) 4653 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4654 4655 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4656 // instruction set such as ARM or Thumb. 4657 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4658 4659 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4660 4661 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4662 if (!CPUProfile.empty()) 4663 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4664 4665 // ACLE 6.4.3 Unaligned access supported in hardware 4666 if (Unaligned) 4667 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4668 4669 // ACLE 6.4.4 LDREX/STREX 4670 if (LDREX) 4671 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4672 4673 // ACLE 6.4.5 CLZ 4674 if (ArchVersion == 5 || 4675 (ArchVersion == 6 && CPUProfile != "M") || 4676 ArchVersion > 6) 4677 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4678 4679 // ACLE 6.5.1 Hardware Floating Point 4680 if (HW_FP) 4681 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4682 4683 // ACLE predefines. 4684 Builder.defineMacro("__ARM_ACLE", "200"); 4685 4686 // FP16 support (we currently only support IEEE format). 4687 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4688 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4689 4690 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4691 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4692 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4693 4694 // Subtarget options. 4695 4696 // FIXME: It's more complicated than this and we don't really support 4697 // interworking. 4698 // Windows on ARM does not "support" interworking 4699 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4700 Builder.defineMacro("__THUMB_INTERWORK__"); 4701 4702 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4703 // Embedded targets on Darwin follow AAPCS, but not EABI. 4704 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4705 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4706 Builder.defineMacro("__ARM_EABI__"); 4707 Builder.defineMacro("__ARM_PCS", "1"); 4708 4709 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4710 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4711 } 4712 4713 if (SoftFloat) 4714 Builder.defineMacro("__SOFTFP__"); 4715 4716 if (CPU == "xscale") 4717 Builder.defineMacro("__XSCALE__"); 4718 4719 if (isThumb()) { 4720 Builder.defineMacro("__THUMBEL__"); 4721 Builder.defineMacro("__thumb__"); 4722 if (supportsThumb2()) 4723 Builder.defineMacro("__thumb2__"); 4724 } 4725 4726 // ACLE 6.4.9 32-bit SIMD instructions 4727 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4728 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4729 4730 // ACLE 6.4.10 Hardware Integer Divide 4731 if (((HWDiv & HWDivThumb) && isThumb()) || 4732 ((HWDiv & HWDivARM) && !isThumb())) { 4733 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4734 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4735 } 4736 4737 // Note, this is always on in gcc, even though it doesn't make sense. 4738 Builder.defineMacro("__APCS_32__"); 4739 4740 if (FPUModeIsVFP((FPUMode) FPU)) { 4741 Builder.defineMacro("__VFP_FP__"); 4742 if (FPU & VFP2FPU) 4743 Builder.defineMacro("__ARM_VFPV2__"); 4744 if (FPU & VFP3FPU) 4745 Builder.defineMacro("__ARM_VFPV3__"); 4746 if (FPU & VFP4FPU) 4747 Builder.defineMacro("__ARM_VFPV4__"); 4748 } 4749 4750 // This only gets set when Neon instructions are actually available, unlike 4751 // the VFP define, hence the soft float and arch check. This is subtly 4752 // different from gcc, we follow the intent which was that it should be set 4753 // when Neon instructions are actually available. 4754 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4755 Builder.defineMacro("__ARM_NEON", "1"); 4756 Builder.defineMacro("__ARM_NEON__"); 4757 // current AArch32 NEON implementations do not support double-precision 4758 // floating-point even when it is present in VFP. 4759 Builder.defineMacro("__ARM_NEON_FP", 4760 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4761 } 4762 4763 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4764 Opts.ShortWChar ? "2" : "4"); 4765 4766 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4767 Opts.ShortEnums ? "1" : "4"); 4768 4769 if (ArchVersion >= 6 && CPUAttr != "6M") { 4770 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4771 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4772 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4773 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4774 } 4775 4776 // ACLE 6.4.7 DSP instructions 4777 if (DSP) { 4778 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4779 } 4780 4781 // ACLE 6.4.8 Saturation instructions 4782 bool SAT = false; 4783 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4784 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4785 SAT = true; 4786 } 4787 4788 // ACLE 6.4.6 Q (saturation) flag 4789 if (DSP || SAT) 4790 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 4791 4792 if (Opts.UnsafeFPMath) 4793 Builder.defineMacro("__ARM_FP_FAST", "1"); 4794 } 4795 4796 void getTargetBuiltins(const Builtin::Info *&Records, 4797 unsigned &NumRecords) const override { 4798 Records = BuiltinInfo; 4799 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4800 } 4801 bool isCLZForZeroUndef() const override { return false; } 4802 BuiltinVaListKind getBuiltinVaListKind() const override { 4803 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4804 } 4805 void getGCCRegNames(const char * const *&Names, 4806 unsigned &NumNames) const override; 4807 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4808 unsigned &NumAliases) const override; 4809 bool validateAsmConstraint(const char *&Name, 4810 TargetInfo::ConstraintInfo &Info) const override { 4811 switch (*Name) { 4812 default: break; 4813 case 'l': // r0-r7 4814 case 'h': // r8-r15 4815 case 'w': // VFP Floating point register single precision 4816 case 'P': // VFP Floating point register double precision 4817 Info.setAllowsRegister(); 4818 return true; 4819 case 'I': 4820 case 'J': 4821 case 'K': 4822 case 'L': 4823 case 'M': 4824 // FIXME 4825 return true; 4826 case 'Q': // A memory address that is a single base register. 4827 Info.setAllowsMemory(); 4828 return true; 4829 case 'U': // a memory reference... 4830 switch (Name[1]) { 4831 case 'q': // ...ARMV4 ldrsb 4832 case 'v': // ...VFP load/store (reg+constant offset) 4833 case 'y': // ...iWMMXt load/store 4834 case 't': // address valid for load/store opaque types wider 4835 // than 128-bits 4836 case 'n': // valid address for Neon doubleword vector load/store 4837 case 'm': // valid address for Neon element and structure load/store 4838 case 's': // valid address for non-offset loads/stores of quad-word 4839 // values in four ARM registers 4840 Info.setAllowsMemory(); 4841 Name++; 4842 return true; 4843 } 4844 } 4845 return false; 4846 } 4847 std::string convertConstraint(const char *&Constraint) const override { 4848 std::string R; 4849 switch (*Constraint) { 4850 case 'U': // Two-character constraint; add "^" hint for later parsing. 4851 R = std::string("^") + std::string(Constraint, 2); 4852 Constraint++; 4853 break; 4854 case 'p': // 'p' should be translated to 'r' by default. 4855 R = std::string("r"); 4856 break; 4857 default: 4858 return std::string(1, *Constraint); 4859 } 4860 return R; 4861 } 4862 bool 4863 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4864 std::string &SuggestedModifier) const override { 4865 bool isOutput = (Constraint[0] == '='); 4866 bool isInOut = (Constraint[0] == '+'); 4867 4868 // Strip off constraint modifiers. 4869 while (Constraint[0] == '=' || 4870 Constraint[0] == '+' || 4871 Constraint[0] == '&') 4872 Constraint = Constraint.substr(1); 4873 4874 switch (Constraint[0]) { 4875 default: break; 4876 case 'r': { 4877 switch (Modifier) { 4878 default: 4879 return (isInOut || isOutput || Size <= 64); 4880 case 'q': 4881 // A register of size 32 cannot fit a vector type. 4882 return false; 4883 } 4884 } 4885 } 4886 4887 return true; 4888 } 4889 const char *getClobbers() const override { 4890 // FIXME: Is this really right? 4891 return ""; 4892 } 4893 4894 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4895 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4896 } 4897 4898 int getEHDataRegisterNumber(unsigned RegNo) const override { 4899 if (RegNo == 0) return 0; 4900 if (RegNo == 1) return 1; 4901 return -1; 4902 } 4903 4904 bool hasSjLjLowering() const override { 4905 return true; 4906 } 4907 }; 4908 4909 bool ARMTargetInfo::setFPMath(StringRef Name) { 4910 if (Name == "neon") { 4911 FPMath = FP_Neon; 4912 return true; 4913 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4914 Name == "vfp4") { 4915 FPMath = FP_VFP; 4916 return true; 4917 } 4918 return false; 4919 } 4920 4921 const char * const ARMTargetInfo::GCCRegNames[] = { 4922 // Integer registers 4923 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4924 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4925 4926 // Float registers 4927 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4928 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4929 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4930 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4931 4932 // Double registers 4933 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4934 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4935 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4936 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4937 4938 // Quad registers 4939 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4940 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4941 }; 4942 4943 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4944 unsigned &NumNames) const { 4945 Names = GCCRegNames; 4946 NumNames = llvm::array_lengthof(GCCRegNames); 4947 } 4948 4949 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4950 { { "a1" }, "r0" }, 4951 { { "a2" }, "r1" }, 4952 { { "a3" }, "r2" }, 4953 { { "a4" }, "r3" }, 4954 { { "v1" }, "r4" }, 4955 { { "v2" }, "r5" }, 4956 { { "v3" }, "r6" }, 4957 { { "v4" }, "r7" }, 4958 { { "v5" }, "r8" }, 4959 { { "v6", "rfp" }, "r9" }, 4960 { { "sl" }, "r10" }, 4961 { { "fp" }, "r11" }, 4962 { { "ip" }, "r12" }, 4963 { { "r13" }, "sp" }, 4964 { { "r14" }, "lr" }, 4965 { { "r15" }, "pc" }, 4966 // The S, D and Q registers overlap, but aren't really aliases; we 4967 // don't want to substitute one of these for a different-sized one. 4968 }; 4969 4970 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4971 unsigned &NumAliases) const { 4972 Aliases = GCCRegAliases; 4973 NumAliases = llvm::array_lengthof(GCCRegAliases); 4974 } 4975 4976 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4977 #define BUILTIN(ID, TYPE, ATTRS) \ 4978 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 4979 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 4980 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 4981 #include "clang/Basic/BuiltinsNEON.def" 4982 4983 #define BUILTIN(ID, TYPE, ATTRS) \ 4984 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 4985 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 4986 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 4987 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 4988 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 4989 #include "clang/Basic/BuiltinsARM.def" 4990 }; 4991 4992 class ARMleTargetInfo : public ARMTargetInfo { 4993 public: 4994 ARMleTargetInfo(const llvm::Triple &Triple) 4995 : ARMTargetInfo(Triple, false) { } 4996 void getTargetDefines(const LangOptions &Opts, 4997 MacroBuilder &Builder) const override { 4998 Builder.defineMacro("__ARMEL__"); 4999 ARMTargetInfo::getTargetDefines(Opts, Builder); 5000 } 5001 }; 5002 5003 class ARMbeTargetInfo : public ARMTargetInfo { 5004 public: 5005 ARMbeTargetInfo(const llvm::Triple &Triple) 5006 : ARMTargetInfo(Triple, true) { } 5007 void getTargetDefines(const LangOptions &Opts, 5008 MacroBuilder &Builder) const override { 5009 Builder.defineMacro("__ARMEB__"); 5010 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5011 ARMTargetInfo::getTargetDefines(Opts, Builder); 5012 } 5013 }; 5014 5015 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5016 const llvm::Triple Triple; 5017 public: 5018 WindowsARMTargetInfo(const llvm::Triple &Triple) 5019 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 5020 TLSSupported = false; 5021 WCharType = UnsignedShort; 5022 SizeType = UnsignedInt; 5023 UserLabelPrefix = ""; 5024 } 5025 void getVisualStudioDefines(const LangOptions &Opts, 5026 MacroBuilder &Builder) const { 5027 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5028 5029 // FIXME: this is invalid for WindowsCE 5030 Builder.defineMacro("_M_ARM_NT", "1"); 5031 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5032 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5033 5034 assert((Triple.getArch() == llvm::Triple::arm || 5035 Triple.getArch() == llvm::Triple::thumb) && 5036 "invalid architecture for Windows ARM target info"); 5037 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5038 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5039 5040 // TODO map the complete set of values 5041 // 31: VFPv3 40: VFPv4 5042 Builder.defineMacro("_M_ARM_FP", "31"); 5043 } 5044 BuiltinVaListKind getBuiltinVaListKind() const override { 5045 return TargetInfo::CharPtrBuiltinVaList; 5046 } 5047 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5048 switch (CC) { 5049 case CC_X86StdCall: 5050 case CC_X86ThisCall: 5051 case CC_X86FastCall: 5052 case CC_X86VectorCall: 5053 return CCCR_Ignore; 5054 case CC_C: 5055 return CCCR_OK; 5056 default: 5057 return CCCR_Warning; 5058 } 5059 } 5060 }; 5061 5062 // Windows ARM + Itanium C++ ABI Target 5063 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5064 public: 5065 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5066 : WindowsARMTargetInfo(Triple) { 5067 TheCXXABI.set(TargetCXXABI::GenericARM); 5068 } 5069 5070 void getTargetDefines(const LangOptions &Opts, 5071 MacroBuilder &Builder) const override { 5072 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5073 5074 if (Opts.MSVCCompat) 5075 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5076 } 5077 }; 5078 5079 // Windows ARM, MS (C++) ABI 5080 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5081 public: 5082 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5083 : WindowsARMTargetInfo(Triple) { 5084 TheCXXABI.set(TargetCXXABI::Microsoft); 5085 } 5086 5087 void getTargetDefines(const LangOptions &Opts, 5088 MacroBuilder &Builder) const override { 5089 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5090 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5091 } 5092 }; 5093 5094 // ARM MinGW target 5095 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5096 public: 5097 MinGWARMTargetInfo(const llvm::Triple &Triple) 5098 : WindowsARMTargetInfo(Triple) { 5099 TheCXXABI.set(TargetCXXABI::GenericARM); 5100 } 5101 5102 void getTargetDefines(const LangOptions &Opts, 5103 MacroBuilder &Builder) const override { 5104 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5105 DefineStd(Builder, "WIN32", Opts); 5106 DefineStd(Builder, "WINNT", Opts); 5107 Builder.defineMacro("_ARM_"); 5108 addMinGWDefines(Opts, Builder); 5109 } 5110 }; 5111 5112 // ARM Cygwin target 5113 class CygwinARMTargetInfo : public ARMleTargetInfo { 5114 public: 5115 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5116 TLSSupported = false; 5117 WCharType = UnsignedShort; 5118 DoubleAlign = LongLongAlign = 64; 5119 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 5120 } 5121 void getTargetDefines(const LangOptions &Opts, 5122 MacroBuilder &Builder) const override { 5123 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5124 Builder.defineMacro("_ARM_"); 5125 Builder.defineMacro("__CYGWIN__"); 5126 Builder.defineMacro("__CYGWIN32__"); 5127 DefineStd(Builder, "unix", Opts); 5128 if (Opts.CPlusPlus) 5129 Builder.defineMacro("_GNU_SOURCE"); 5130 } 5131 }; 5132 5133 class DarwinARMTargetInfo : 5134 public DarwinTargetInfo<ARMleTargetInfo> { 5135 protected: 5136 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5137 MacroBuilder &Builder) const override { 5138 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5139 } 5140 5141 public: 5142 DarwinARMTargetInfo(const llvm::Triple &Triple) 5143 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5144 HasAlignMac68kSupport = true; 5145 // iOS always has 64-bit atomic instructions. 5146 // FIXME: This should be based off of the target features in 5147 // ARMleTargetInfo. 5148 MaxAtomicInlineWidth = 64; 5149 5150 // Darwin on iOS uses a variant of the ARM C++ ABI. 5151 TheCXXABI.set(TargetCXXABI::iOS); 5152 } 5153 }; 5154 5155 class AArch64TargetInfo : public TargetInfo { 5156 virtual void setDataLayoutString() = 0; 5157 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5158 static const char *const GCCRegNames[]; 5159 5160 enum FPUModeEnum { 5161 FPUMode, 5162 NeonMode 5163 }; 5164 5165 unsigned FPU; 5166 unsigned CRC; 5167 unsigned Crypto; 5168 unsigned Unaligned; 5169 5170 static const Builtin::Info BuiltinInfo[]; 5171 5172 std::string ABI; 5173 5174 public: 5175 AArch64TargetInfo(const llvm::Triple &Triple) 5176 : TargetInfo(Triple), ABI("aapcs") { 5177 5178 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5179 WCharType = SignedInt; 5180 5181 // NetBSD apparently prefers consistency across ARM targets to consistency 5182 // across 64-bit targets. 5183 Int64Type = SignedLongLong; 5184 IntMaxType = SignedLongLong; 5185 } else { 5186 WCharType = UnsignedInt; 5187 Int64Type = SignedLong; 5188 IntMaxType = SignedLong; 5189 } 5190 5191 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5192 MaxVectorAlign = 128; 5193 MaxAtomicInlineWidth = 128; 5194 MaxAtomicPromoteWidth = 128; 5195 5196 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5197 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5198 5199 // {} in inline assembly are neon specifiers, not assembly variant 5200 // specifiers. 5201 NoAsmVariants = true; 5202 5203 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5204 // contributes to the alignment of the containing aggregate in the same way 5205 // a plain (non bit-field) member of that type would, without exception for 5206 // zero-sized or anonymous bit-fields." 5207 UseBitFieldTypeAlignment = true; 5208 UseZeroLengthBitfieldAlignment = true; 5209 5210 // AArch64 targets default to using the ARM C++ ABI. 5211 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5212 } 5213 5214 StringRef getABI() const override { return ABI; } 5215 bool setABI(const std::string &Name) override { 5216 if (Name != "aapcs" && Name != "darwinpcs") 5217 return false; 5218 5219 ABI = Name; 5220 return true; 5221 } 5222 5223 bool setCPU(const std::string &Name) override { 5224 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5225 .Case("generic", true) 5226 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 5227 .Case("cyclone", true) 5228 .Default(false); 5229 return CPUKnown; 5230 } 5231 5232 void getTargetDefines(const LangOptions &Opts, 5233 MacroBuilder &Builder) const override { 5234 // Target identification. 5235 Builder.defineMacro("__aarch64__"); 5236 5237 // Target properties. 5238 Builder.defineMacro("_LP64"); 5239 Builder.defineMacro("__LP64__"); 5240 5241 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5242 Builder.defineMacro("__ARM_ACLE", "200"); 5243 Builder.defineMacro("__ARM_ARCH", "8"); 5244 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5245 5246 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5247 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5248 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5249 5250 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5251 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5252 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5253 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5254 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5255 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5256 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5257 5258 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5259 5260 // 0xe implies support for half, single and double precision operations. 5261 Builder.defineMacro("__ARM_FP", "0xE"); 5262 5263 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5264 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5265 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5266 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5267 5268 if (Opts.UnsafeFPMath) 5269 Builder.defineMacro("__ARM_FP_FAST", "1"); 5270 5271 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5272 5273 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5274 Opts.ShortEnums ? "1" : "4"); 5275 5276 if (FPU == NeonMode) { 5277 Builder.defineMacro("__ARM_NEON", "1"); 5278 // 64-bit NEON supports half, single and double precision operations. 5279 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5280 } 5281 5282 if (CRC) 5283 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5284 5285 if (Crypto) 5286 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5287 5288 if (Unaligned) 5289 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5290 5291 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5292 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5293 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5294 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5295 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5296 } 5297 5298 void getTargetBuiltins(const Builtin::Info *&Records, 5299 unsigned &NumRecords) const override { 5300 Records = BuiltinInfo; 5301 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 5302 } 5303 5304 bool hasFeature(StringRef Feature) const override { 5305 return Feature == "aarch64" || 5306 Feature == "arm64" || 5307 Feature == "arm" || 5308 (Feature == "neon" && FPU == NeonMode); 5309 } 5310 5311 bool handleTargetFeatures(std::vector<std::string> &Features, 5312 DiagnosticsEngine &Diags) override { 5313 FPU = FPUMode; 5314 CRC = 0; 5315 Crypto = 0; 5316 Unaligned = 1; 5317 5318 for (const auto &Feature : Features) { 5319 if (Feature == "+neon") 5320 FPU = NeonMode; 5321 if (Feature == "+crc") 5322 CRC = 1; 5323 if (Feature == "+crypto") 5324 Crypto = 1; 5325 if (Feature == "+strict-align") 5326 Unaligned = 0; 5327 } 5328 5329 setDataLayoutString(); 5330 5331 return true; 5332 } 5333 5334 bool isCLZForZeroUndef() const override { return false; } 5335 5336 BuiltinVaListKind getBuiltinVaListKind() const override { 5337 return TargetInfo::AArch64ABIBuiltinVaList; 5338 } 5339 5340 void getGCCRegNames(const char *const *&Names, 5341 unsigned &NumNames) const override; 5342 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5343 unsigned &NumAliases) const override; 5344 5345 bool validateAsmConstraint(const char *&Name, 5346 TargetInfo::ConstraintInfo &Info) const override { 5347 switch (*Name) { 5348 default: 5349 return false; 5350 case 'w': // Floating point and SIMD registers (V0-V31) 5351 Info.setAllowsRegister(); 5352 return true; 5353 case 'I': // Constant that can be used with an ADD instruction 5354 case 'J': // Constant that can be used with a SUB instruction 5355 case 'K': // Constant that can be used with a 32-bit logical instruction 5356 case 'L': // Constant that can be used with a 64-bit logical instruction 5357 case 'M': // Constant that can be used as a 32-bit MOV immediate 5358 case 'N': // Constant that can be used as a 64-bit MOV immediate 5359 case 'Y': // Floating point constant zero 5360 case 'Z': // Integer constant zero 5361 return true; 5362 case 'Q': // A memory reference with base register and no offset 5363 Info.setAllowsMemory(); 5364 return true; 5365 case 'S': // A symbolic address 5366 Info.setAllowsRegister(); 5367 return true; 5368 case 'U': 5369 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5370 // Utf: A memory address suitable for ldp/stp in TF mode. 5371 // Usa: An absolute symbolic address. 5372 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5373 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5374 case 'z': // Zero register, wzr or xzr 5375 Info.setAllowsRegister(); 5376 return true; 5377 case 'x': // Floating point and SIMD registers (V0-V15) 5378 Info.setAllowsRegister(); 5379 return true; 5380 } 5381 return false; 5382 } 5383 5384 bool 5385 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5386 std::string &SuggestedModifier) const override { 5387 // Strip off constraint modifiers. 5388 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5389 Constraint = Constraint.substr(1); 5390 5391 switch (Constraint[0]) { 5392 default: 5393 return true; 5394 case 'z': 5395 case 'r': { 5396 switch (Modifier) { 5397 case 'x': 5398 case 'w': 5399 // For now assume that the person knows what they're 5400 // doing with the modifier. 5401 return true; 5402 default: 5403 // By default an 'r' constraint will be in the 'x' 5404 // registers. 5405 if (Size == 64) 5406 return true; 5407 5408 SuggestedModifier = "w"; 5409 return false; 5410 } 5411 } 5412 } 5413 } 5414 5415 const char *getClobbers() const override { return ""; } 5416 5417 int getEHDataRegisterNumber(unsigned RegNo) const override { 5418 if (RegNo == 0) 5419 return 0; 5420 if (RegNo == 1) 5421 return 1; 5422 return -1; 5423 } 5424 }; 5425 5426 const char *const AArch64TargetInfo::GCCRegNames[] = { 5427 // 32-bit Integer registers 5428 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5429 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5430 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5431 5432 // 64-bit Integer registers 5433 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5434 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5435 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5436 5437 // 32-bit floating point regsisters 5438 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5439 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5440 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5441 5442 // 64-bit floating point regsisters 5443 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5444 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5445 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5446 5447 // Vector registers 5448 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5449 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5450 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5451 }; 5452 5453 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 5454 unsigned &NumNames) const { 5455 Names = GCCRegNames; 5456 NumNames = llvm::array_lengthof(GCCRegNames); 5457 } 5458 5459 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5460 { { "w31" }, "wsp" }, 5461 { { "x29" }, "fp" }, 5462 { { "x30" }, "lr" }, 5463 { { "x31" }, "sp" }, 5464 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5465 // don't want to substitute one of these for a different-sized one. 5466 }; 5467 5468 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5469 unsigned &NumAliases) const { 5470 Aliases = GCCRegAliases; 5471 NumAliases = llvm::array_lengthof(GCCRegAliases); 5472 } 5473 5474 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5475 #define BUILTIN(ID, TYPE, ATTRS) \ 5476 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5477 #include "clang/Basic/BuiltinsNEON.def" 5478 5479 #define BUILTIN(ID, TYPE, ATTRS) \ 5480 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5481 #include "clang/Basic/BuiltinsAArch64.def" 5482 }; 5483 5484 class AArch64leTargetInfo : public AArch64TargetInfo { 5485 void setDataLayoutString() override { 5486 if (getTriple().isOSBinFormatMachO()) 5487 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5488 else 5489 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5490 } 5491 5492 public: 5493 AArch64leTargetInfo(const llvm::Triple &Triple) 5494 : AArch64TargetInfo(Triple) { 5495 BigEndian = false; 5496 } 5497 void getTargetDefines(const LangOptions &Opts, 5498 MacroBuilder &Builder) const override { 5499 Builder.defineMacro("__AARCH64EL__"); 5500 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5501 } 5502 }; 5503 5504 class AArch64beTargetInfo : public AArch64TargetInfo { 5505 void setDataLayoutString() override { 5506 assert(!getTriple().isOSBinFormatMachO()); 5507 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5508 } 5509 5510 public: 5511 AArch64beTargetInfo(const llvm::Triple &Triple) 5512 : AArch64TargetInfo(Triple) { } 5513 void getTargetDefines(const LangOptions &Opts, 5514 MacroBuilder &Builder) const override { 5515 Builder.defineMacro("__AARCH64EB__"); 5516 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5517 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5518 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5519 } 5520 }; 5521 5522 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5523 protected: 5524 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5525 MacroBuilder &Builder) const override { 5526 Builder.defineMacro("__AARCH64_SIMD__"); 5527 Builder.defineMacro("__ARM64_ARCH_8__"); 5528 Builder.defineMacro("__ARM_NEON__"); 5529 Builder.defineMacro("__LITTLE_ENDIAN__"); 5530 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5531 Builder.defineMacro("__arm64", "1"); 5532 Builder.defineMacro("__arm64__", "1"); 5533 5534 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5535 } 5536 5537 public: 5538 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5539 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5540 Int64Type = SignedLongLong; 5541 WCharType = SignedInt; 5542 UseSignedCharForObjCBool = false; 5543 5544 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5545 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5546 5547 TheCXXABI.set(TargetCXXABI::iOS64); 5548 } 5549 5550 BuiltinVaListKind getBuiltinVaListKind() const override { 5551 return TargetInfo::CharPtrBuiltinVaList; 5552 } 5553 }; 5554 5555 // Hexagon abstract base class 5556 class HexagonTargetInfo : public TargetInfo { 5557 static const Builtin::Info BuiltinInfo[]; 5558 static const char * const GCCRegNames[]; 5559 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5560 std::string CPU; 5561 public: 5562 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5563 BigEndian = false; 5564 DataLayoutString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5565 5566 // {} in inline assembly are packet specifiers, not assembly variant 5567 // specifiers. 5568 NoAsmVariants = true; 5569 } 5570 5571 void getTargetBuiltins(const Builtin::Info *&Records, 5572 unsigned &NumRecords) const override { 5573 Records = BuiltinInfo; 5574 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5575 } 5576 5577 bool validateAsmConstraint(const char *&Name, 5578 TargetInfo::ConstraintInfo &Info) const override { 5579 return true; 5580 } 5581 5582 void getTargetDefines(const LangOptions &Opts, 5583 MacroBuilder &Builder) const override; 5584 5585 bool hasFeature(StringRef Feature) const override { 5586 return Feature == "hexagon"; 5587 } 5588 5589 BuiltinVaListKind getBuiltinVaListKind() const override { 5590 return TargetInfo::CharPtrBuiltinVaList; 5591 } 5592 void getGCCRegNames(const char * const *&Names, 5593 unsigned &NumNames) const override; 5594 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5595 unsigned &NumAliases) const override; 5596 const char *getClobbers() const override { 5597 return ""; 5598 } 5599 5600 static const char *getHexagonCPUSuffix(StringRef Name) { 5601 return llvm::StringSwitch<const char*>(Name) 5602 .Case("hexagonv4", "4") 5603 .Case("hexagonv5", "5") 5604 .Default(nullptr); 5605 } 5606 5607 bool setCPU(const std::string &Name) override { 5608 if (!getHexagonCPUSuffix(Name)) 5609 return false; 5610 5611 CPU = Name; 5612 return true; 5613 } 5614 }; 5615 5616 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5617 MacroBuilder &Builder) const { 5618 Builder.defineMacro("qdsp6"); 5619 Builder.defineMacro("__qdsp6", "1"); 5620 Builder.defineMacro("__qdsp6__", "1"); 5621 5622 Builder.defineMacro("hexagon"); 5623 Builder.defineMacro("__hexagon", "1"); 5624 Builder.defineMacro("__hexagon__", "1"); 5625 5626 if(CPU == "hexagonv1") { 5627 Builder.defineMacro("__HEXAGON_V1__"); 5628 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5629 if(Opts.HexagonQdsp6Compat) { 5630 Builder.defineMacro("__QDSP6_V1__"); 5631 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5632 } 5633 } 5634 else if(CPU == "hexagonv2") { 5635 Builder.defineMacro("__HEXAGON_V2__"); 5636 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5637 if(Opts.HexagonQdsp6Compat) { 5638 Builder.defineMacro("__QDSP6_V2__"); 5639 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5640 } 5641 } 5642 else if(CPU == "hexagonv3") { 5643 Builder.defineMacro("__HEXAGON_V3__"); 5644 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5645 if(Opts.HexagonQdsp6Compat) { 5646 Builder.defineMacro("__QDSP6_V3__"); 5647 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5648 } 5649 } 5650 else if(CPU == "hexagonv4") { 5651 Builder.defineMacro("__HEXAGON_V4__"); 5652 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5653 if(Opts.HexagonQdsp6Compat) { 5654 Builder.defineMacro("__QDSP6_V4__"); 5655 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5656 } 5657 } 5658 else if(CPU == "hexagonv5") { 5659 Builder.defineMacro("__HEXAGON_V5__"); 5660 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5661 if(Opts.HexagonQdsp6Compat) { 5662 Builder.defineMacro("__QDSP6_V5__"); 5663 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5664 } 5665 } 5666 } 5667 5668 const char * const HexagonTargetInfo::GCCRegNames[] = { 5669 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5670 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5671 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5672 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5673 "p0", "p1", "p2", "p3", 5674 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5675 }; 5676 5677 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5678 unsigned &NumNames) const { 5679 Names = GCCRegNames; 5680 NumNames = llvm::array_lengthof(GCCRegNames); 5681 } 5682 5683 5684 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5685 { { "sp" }, "r29" }, 5686 { { "fp" }, "r30" }, 5687 { { "lr" }, "r31" }, 5688 }; 5689 5690 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5691 unsigned &NumAliases) const { 5692 Aliases = GCCRegAliases; 5693 NumAliases = llvm::array_lengthof(GCCRegAliases); 5694 } 5695 5696 5697 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5698 #define BUILTIN(ID, TYPE, ATTRS) \ 5699 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5700 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5701 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5702 #include "clang/Basic/BuiltinsHexagon.def" 5703 }; 5704 5705 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5706 class SparcTargetInfo : public TargetInfo { 5707 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5708 static const char * const GCCRegNames[]; 5709 bool SoftFloat; 5710 public: 5711 SparcTargetInfo(const llvm::Triple &Triple) 5712 : TargetInfo(Triple), SoftFloat(false) {} 5713 5714 bool handleTargetFeatures(std::vector<std::string> &Features, 5715 DiagnosticsEngine &Diags) override { 5716 // The backend doesn't actually handle soft float yet, but in case someone 5717 // is using the support for the front end continue to support it. 5718 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5719 if (Feature != Features.end()) { 5720 SoftFloat = true; 5721 Features.erase(Feature); 5722 } 5723 return true; 5724 } 5725 void getTargetDefines(const LangOptions &Opts, 5726 MacroBuilder &Builder) const override { 5727 DefineStd(Builder, "sparc", Opts); 5728 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5729 5730 if (SoftFloat) 5731 Builder.defineMacro("SOFT_FLOAT", "1"); 5732 } 5733 5734 bool hasFeature(StringRef Feature) const override { 5735 return llvm::StringSwitch<bool>(Feature) 5736 .Case("softfloat", SoftFloat) 5737 .Case("sparc", true) 5738 .Default(false); 5739 } 5740 5741 void getTargetBuiltins(const Builtin::Info *&Records, 5742 unsigned &NumRecords) const override { 5743 // FIXME: Implement! 5744 } 5745 BuiltinVaListKind getBuiltinVaListKind() const override { 5746 return TargetInfo::VoidPtrBuiltinVaList; 5747 } 5748 void getGCCRegNames(const char * const *&Names, 5749 unsigned &NumNames) const override; 5750 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5751 unsigned &NumAliases) const override; 5752 bool validateAsmConstraint(const char *&Name, 5753 TargetInfo::ConstraintInfo &info) const override { 5754 // FIXME: Implement! 5755 switch (*Name) { 5756 case 'I': // Signed 13-bit constant 5757 case 'J': // Zero 5758 case 'K': // 32-bit constant with the low 12 bits clear 5759 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5760 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5761 case 'N': // Same as 'K' but zext (required for SIMode) 5762 case 'O': // The constant 4096 5763 return true; 5764 } 5765 return false; 5766 } 5767 const char *getClobbers() const override { 5768 // FIXME: Implement! 5769 return ""; 5770 } 5771 }; 5772 5773 const char * const SparcTargetInfo::GCCRegNames[] = { 5774 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5775 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5776 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5777 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5778 }; 5779 5780 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5781 unsigned &NumNames) const { 5782 Names = GCCRegNames; 5783 NumNames = llvm::array_lengthof(GCCRegNames); 5784 } 5785 5786 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5787 { { "g0" }, "r0" }, 5788 { { "g1" }, "r1" }, 5789 { { "g2" }, "r2" }, 5790 { { "g3" }, "r3" }, 5791 { { "g4" }, "r4" }, 5792 { { "g5" }, "r5" }, 5793 { { "g6" }, "r6" }, 5794 { { "g7" }, "r7" }, 5795 { { "o0" }, "r8" }, 5796 { { "o1" }, "r9" }, 5797 { { "o2" }, "r10" }, 5798 { { "o3" }, "r11" }, 5799 { { "o4" }, "r12" }, 5800 { { "o5" }, "r13" }, 5801 { { "o6", "sp" }, "r14" }, 5802 { { "o7" }, "r15" }, 5803 { { "l0" }, "r16" }, 5804 { { "l1" }, "r17" }, 5805 { { "l2" }, "r18" }, 5806 { { "l3" }, "r19" }, 5807 { { "l4" }, "r20" }, 5808 { { "l5" }, "r21" }, 5809 { { "l6" }, "r22" }, 5810 { { "l7" }, "r23" }, 5811 { { "i0" }, "r24" }, 5812 { { "i1" }, "r25" }, 5813 { { "i2" }, "r26" }, 5814 { { "i3" }, "r27" }, 5815 { { "i4" }, "r28" }, 5816 { { "i5" }, "r29" }, 5817 { { "i6", "fp" }, "r30" }, 5818 { { "i7" }, "r31" }, 5819 }; 5820 5821 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5822 unsigned &NumAliases) const { 5823 Aliases = GCCRegAliases; 5824 NumAliases = llvm::array_lengthof(GCCRegAliases); 5825 } 5826 5827 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5828 class SparcV8TargetInfo : public SparcTargetInfo { 5829 public: 5830 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5831 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5832 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 5833 switch (getTriple().getOS()) { 5834 default: 5835 SizeType = UnsignedInt; 5836 IntPtrType = SignedInt; 5837 PtrDiffType = SignedInt; 5838 break; 5839 case llvm::Triple::NetBSD: 5840 case llvm::Triple::OpenBSD: 5841 SizeType = UnsignedLong; 5842 IntPtrType = SignedLong; 5843 PtrDiffType = SignedLong; 5844 break; 5845 } 5846 } 5847 5848 void getTargetDefines(const LangOptions &Opts, 5849 MacroBuilder &Builder) const override { 5850 SparcTargetInfo::getTargetDefines(Opts, Builder); 5851 Builder.defineMacro("__sparcv8"); 5852 } 5853 }; 5854 5855 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 5856 class SparcV8elTargetInfo : public SparcV8TargetInfo { 5857 public: 5858 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 5859 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5860 BigEndian = false; 5861 } 5862 }; 5863 5864 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5865 class SparcV9TargetInfo : public SparcTargetInfo { 5866 public: 5867 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5868 // FIXME: Support Sparc quad-precision long double? 5869 DataLayoutString = "E-m:e-i64:64-n32:64-S128"; 5870 // This is an LP64 platform. 5871 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5872 5873 // OpenBSD uses long long for int64_t and intmax_t. 5874 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5875 IntMaxType = SignedLongLong; 5876 else 5877 IntMaxType = SignedLong; 5878 Int64Type = IntMaxType; 5879 5880 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5881 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5882 LongDoubleWidth = 128; 5883 LongDoubleAlign = 128; 5884 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5885 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5886 } 5887 5888 void getTargetDefines(const LangOptions &Opts, 5889 MacroBuilder &Builder) const override { 5890 SparcTargetInfo::getTargetDefines(Opts, Builder); 5891 Builder.defineMacro("__sparcv9"); 5892 Builder.defineMacro("__arch64__"); 5893 // Solaris doesn't need these variants, but the BSDs do. 5894 if (getTriple().getOS() != llvm::Triple::Solaris) { 5895 Builder.defineMacro("__sparc64__"); 5896 Builder.defineMacro("__sparc_v9__"); 5897 Builder.defineMacro("__sparcv9__"); 5898 } 5899 } 5900 5901 bool setCPU(const std::string &Name) override { 5902 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5903 .Case("v9", true) 5904 .Case("ultrasparc", true) 5905 .Case("ultrasparc3", true) 5906 .Case("niagara", true) 5907 .Case("niagara2", true) 5908 .Case("niagara3", true) 5909 .Case("niagara4", true) 5910 .Default(false); 5911 5912 // No need to store the CPU yet. There aren't any CPU-specific 5913 // macros to define. 5914 return CPUKnown; 5915 } 5916 }; 5917 5918 class SystemZTargetInfo : public TargetInfo { 5919 static const Builtin::Info BuiltinInfo[]; 5920 static const char *const GCCRegNames[]; 5921 std::string CPU; 5922 bool HasTransactionalExecution; 5923 bool HasVector; 5924 5925 public: 5926 SystemZTargetInfo(const llvm::Triple &Triple) 5927 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 5928 HasVector(false) { 5929 IntMaxType = SignedLong; 5930 Int64Type = SignedLong; 5931 TLSSupported = true; 5932 IntWidth = IntAlign = 32; 5933 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5934 PointerWidth = PointerAlign = 64; 5935 LongDoubleWidth = 128; 5936 LongDoubleAlign = 64; 5937 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5938 DefaultAlignForAttributeAligned = 64; 5939 MinGlobalAlign = 16; 5940 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5941 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5942 } 5943 void getTargetDefines(const LangOptions &Opts, 5944 MacroBuilder &Builder) const override { 5945 Builder.defineMacro("__s390__"); 5946 Builder.defineMacro("__s390x__"); 5947 Builder.defineMacro("__zarch__"); 5948 Builder.defineMacro("__LONG_DOUBLE_128__"); 5949 if (HasTransactionalExecution) 5950 Builder.defineMacro("__HTM__"); 5951 if (Opts.ZVector) 5952 Builder.defineMacro("__VEC__", "10301"); 5953 } 5954 void getTargetBuiltins(const Builtin::Info *&Records, 5955 unsigned &NumRecords) const override { 5956 Records = BuiltinInfo; 5957 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin; 5958 } 5959 5960 void getGCCRegNames(const char *const *&Names, 5961 unsigned &NumNames) const override; 5962 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5963 unsigned &NumAliases) const override { 5964 // No aliases. 5965 Aliases = nullptr; 5966 NumAliases = 0; 5967 } 5968 bool validateAsmConstraint(const char *&Name, 5969 TargetInfo::ConstraintInfo &info) const override; 5970 const char *getClobbers() const override { 5971 // FIXME: Is this really right? 5972 return ""; 5973 } 5974 BuiltinVaListKind getBuiltinVaListKind() const override { 5975 return TargetInfo::SystemZBuiltinVaList; 5976 } 5977 bool setCPU(const std::string &Name) override { 5978 CPU = Name; 5979 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5980 .Case("z10", true) 5981 .Case("z196", true) 5982 .Case("zEC12", true) 5983 .Case("z13", true) 5984 .Default(false); 5985 5986 return CPUKnown; 5987 } 5988 bool 5989 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5990 StringRef CPU, 5991 const std::vector<std::string> &FeaturesVec) const override { 5992 if (CPU == "zEC12") 5993 Features["transactional-execution"] = true; 5994 if (CPU == "z13") { 5995 Features["transactional-execution"] = true; 5996 Features["vector"] = true; 5997 } 5998 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5999 } 6000 6001 bool handleTargetFeatures(std::vector<std::string> &Features, 6002 DiagnosticsEngine &Diags) override { 6003 HasTransactionalExecution = false; 6004 for (const auto &Feature : Features) { 6005 if (Feature == "+transactional-execution") 6006 HasTransactionalExecution = true; 6007 else if (Feature == "+vector") 6008 HasVector = true; 6009 } 6010 // If we use the vector ABI, vector types are 64-bit aligned. 6011 if (HasVector) { 6012 MaxVectorAlign = 64; 6013 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6014 "-v128:64-a:8:16-n32:64"; 6015 } 6016 return true; 6017 } 6018 6019 bool hasFeature(StringRef Feature) const override { 6020 return llvm::StringSwitch<bool>(Feature) 6021 .Case("systemz", true) 6022 .Case("htm", HasTransactionalExecution) 6023 .Case("vx", HasVector) 6024 .Default(false); 6025 } 6026 6027 StringRef getABI() const override { 6028 if (HasVector) 6029 return "vector"; 6030 return ""; 6031 } 6032 6033 bool useFloat128ManglingForLongDouble() const override { 6034 return true; 6035 } 6036 }; 6037 6038 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6039 #define BUILTIN(ID, TYPE, ATTRS) \ 6040 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6041 #include "clang/Basic/BuiltinsSystemZ.def" 6042 }; 6043 6044 const char *const SystemZTargetInfo::GCCRegNames[] = { 6045 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6046 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6047 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6048 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6049 }; 6050 6051 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 6052 unsigned &NumNames) const { 6053 Names = GCCRegNames; 6054 NumNames = llvm::array_lengthof(GCCRegNames); 6055 } 6056 6057 bool SystemZTargetInfo:: 6058 validateAsmConstraint(const char *&Name, 6059 TargetInfo::ConstraintInfo &Info) const { 6060 switch (*Name) { 6061 default: 6062 return false; 6063 6064 case 'a': // Address register 6065 case 'd': // Data register (equivalent to 'r') 6066 case 'f': // Floating-point register 6067 Info.setAllowsRegister(); 6068 return true; 6069 6070 case 'I': // Unsigned 8-bit constant 6071 case 'J': // Unsigned 12-bit constant 6072 case 'K': // Signed 16-bit constant 6073 case 'L': // Signed 20-bit displacement (on all targets we support) 6074 case 'M': // 0x7fffffff 6075 return true; 6076 6077 case 'Q': // Memory with base and unsigned 12-bit displacement 6078 case 'R': // Likewise, plus an index 6079 case 'S': // Memory with base and signed 20-bit displacement 6080 case 'T': // Likewise, plus an index 6081 Info.setAllowsMemory(); 6082 return true; 6083 } 6084 } 6085 6086 class MSP430TargetInfo : public TargetInfo { 6087 static const char *const GCCRegNames[]; 6088 6089 public: 6090 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6091 BigEndian = false; 6092 TLSSupported = false; 6093 IntWidth = 16; 6094 IntAlign = 16; 6095 LongWidth = 32; 6096 LongLongWidth = 64; 6097 LongAlign = LongLongAlign = 16; 6098 PointerWidth = 16; 6099 PointerAlign = 16; 6100 SuitableAlign = 16; 6101 SizeType = UnsignedInt; 6102 IntMaxType = SignedLongLong; 6103 IntPtrType = SignedInt; 6104 PtrDiffType = SignedInt; 6105 SigAtomicType = SignedLong; 6106 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 6107 } 6108 void getTargetDefines(const LangOptions &Opts, 6109 MacroBuilder &Builder) const override { 6110 Builder.defineMacro("MSP430"); 6111 Builder.defineMacro("__MSP430__"); 6112 // FIXME: defines for different 'flavours' of MCU 6113 } 6114 void getTargetBuiltins(const Builtin::Info *&Records, 6115 unsigned &NumRecords) const override { 6116 // FIXME: Implement. 6117 Records = nullptr; 6118 NumRecords = 0; 6119 } 6120 bool hasFeature(StringRef Feature) const override { 6121 return Feature == "msp430"; 6122 } 6123 void getGCCRegNames(const char *const *&Names, 6124 unsigned &NumNames) const override; 6125 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6126 unsigned &NumAliases) const override { 6127 // No aliases. 6128 Aliases = nullptr; 6129 NumAliases = 0; 6130 } 6131 bool validateAsmConstraint(const char *&Name, 6132 TargetInfo::ConstraintInfo &info) const override { 6133 // FIXME: implement 6134 switch (*Name) { 6135 case 'K': // the constant 1 6136 case 'L': // constant -1^20 .. 1^19 6137 case 'M': // constant 1-4: 6138 return true; 6139 } 6140 // No target constraints for now. 6141 return false; 6142 } 6143 const char *getClobbers() const override { 6144 // FIXME: Is this really right? 6145 return ""; 6146 } 6147 BuiltinVaListKind getBuiltinVaListKind() const override { 6148 // FIXME: implement 6149 return TargetInfo::CharPtrBuiltinVaList; 6150 } 6151 }; 6152 6153 const char *const MSP430TargetInfo::GCCRegNames[] = { 6154 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6155 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6156 6157 void MSP430TargetInfo::getGCCRegNames(const char *const *&Names, 6158 unsigned &NumNames) const { 6159 Names = GCCRegNames; 6160 NumNames = llvm::array_lengthof(GCCRegNames); 6161 } 6162 6163 // LLVM and Clang cannot be used directly to output native binaries for 6164 // target, but is used to compile C code to llvm bitcode with correct 6165 // type and alignment information. 6166 // 6167 // TCE uses the llvm bitcode as input and uses it for generating customized 6168 // target processor and program binary. TCE co-design environment is 6169 // publicly available in http://tce.cs.tut.fi 6170 6171 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6172 3, // opencl_global 6173 4, // opencl_local 6174 5, // opencl_constant 6175 // FIXME: generic has to be added to the target 6176 0, // opencl_generic 6177 0, // cuda_device 6178 0, // cuda_constant 6179 0 // cuda_shared 6180 }; 6181 6182 class TCETargetInfo : public TargetInfo { 6183 public: 6184 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6185 TLSSupported = false; 6186 IntWidth = 32; 6187 LongWidth = LongLongWidth = 32; 6188 PointerWidth = 32; 6189 IntAlign = 32; 6190 LongAlign = LongLongAlign = 32; 6191 PointerAlign = 32; 6192 SuitableAlign = 32; 6193 SizeType = UnsignedInt; 6194 IntMaxType = SignedLong; 6195 IntPtrType = SignedInt; 6196 PtrDiffType = SignedInt; 6197 FloatWidth = 32; 6198 FloatAlign = 32; 6199 DoubleWidth = 32; 6200 DoubleAlign = 32; 6201 LongDoubleWidth = 32; 6202 LongDoubleAlign = 32; 6203 FloatFormat = &llvm::APFloat::IEEEsingle; 6204 DoubleFormat = &llvm::APFloat::IEEEsingle; 6205 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6206 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6207 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6208 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6209 UseAddrSpaceMapMangling = true; 6210 } 6211 6212 void getTargetDefines(const LangOptions &Opts, 6213 MacroBuilder &Builder) const override { 6214 DefineStd(Builder, "tce", Opts); 6215 Builder.defineMacro("__TCE__"); 6216 Builder.defineMacro("__TCE_V1__"); 6217 } 6218 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6219 6220 void getTargetBuiltins(const Builtin::Info *&Records, 6221 unsigned &NumRecords) const override {} 6222 const char *getClobbers() const override { return ""; } 6223 BuiltinVaListKind getBuiltinVaListKind() const override { 6224 return TargetInfo::VoidPtrBuiltinVaList; 6225 } 6226 void getGCCRegNames(const char *const *&Names, 6227 unsigned &NumNames) const override {} 6228 bool validateAsmConstraint(const char *&Name, 6229 TargetInfo::ConstraintInfo &info) const override { 6230 return true; 6231 } 6232 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6233 unsigned &NumAliases) const override {} 6234 }; 6235 6236 class BPFTargetInfo : public TargetInfo { 6237 public: 6238 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6239 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6240 SizeType = UnsignedLong; 6241 PtrDiffType = SignedLong; 6242 IntPtrType = SignedLong; 6243 IntMaxType = SignedLong; 6244 Int64Type = SignedLong; 6245 RegParmMax = 5; 6246 if (Triple.getArch() == llvm::Triple::bpfeb) { 6247 BigEndian = true; 6248 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6249 } else { 6250 BigEndian = false; 6251 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6252 } 6253 MaxAtomicPromoteWidth = 64; 6254 MaxAtomicInlineWidth = 64; 6255 TLSSupported = false; 6256 } 6257 void getTargetDefines(const LangOptions &Opts, 6258 MacroBuilder &Builder) const override { 6259 DefineStd(Builder, "bpf", Opts); 6260 Builder.defineMacro("__BPF__"); 6261 } 6262 bool hasFeature(StringRef Feature) const override { 6263 return Feature == "bpf"; 6264 } 6265 6266 void getTargetBuiltins(const Builtin::Info *&Records, 6267 unsigned &NumRecords) const override {} 6268 const char *getClobbers() const override { 6269 return ""; 6270 } 6271 BuiltinVaListKind getBuiltinVaListKind() const override { 6272 return TargetInfo::VoidPtrBuiltinVaList; 6273 } 6274 void getGCCRegNames(const char * const *&Names, 6275 unsigned &NumNames) const override { 6276 Names = nullptr; 6277 NumNames = 0; 6278 } 6279 bool validateAsmConstraint(const char *&Name, 6280 TargetInfo::ConstraintInfo &info) const override { 6281 return true; 6282 } 6283 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6284 unsigned &NumAliases) const override { 6285 Aliases = nullptr; 6286 NumAliases = 0; 6287 } 6288 }; 6289 6290 class MipsTargetInfoBase : public TargetInfo { 6291 virtual void setDataLayoutString() = 0; 6292 6293 static const Builtin::Info BuiltinInfo[]; 6294 std::string CPU; 6295 bool IsMips16; 6296 bool IsMicromips; 6297 bool IsNan2008; 6298 bool IsSingleFloat; 6299 enum MipsFloatABI { 6300 HardFloat, SoftFloat 6301 } FloatABI; 6302 enum DspRevEnum { 6303 NoDSP, DSP1, DSP2 6304 } DspRev; 6305 bool HasMSA; 6306 6307 protected: 6308 bool HasFP64; 6309 std::string ABI; 6310 6311 public: 6312 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6313 const std::string &CPUStr) 6314 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6315 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6316 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6317 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6318 } 6319 6320 bool isNaN2008Default() const { 6321 return CPU == "mips32r6" || CPU == "mips64r6"; 6322 } 6323 6324 bool isFP64Default() const { 6325 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6326 } 6327 6328 bool isNan2008() const override { 6329 return IsNan2008; 6330 } 6331 6332 StringRef getABI() const override { return ABI; } 6333 bool setCPU(const std::string &Name) override { 6334 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6335 getTriple().getArch() == llvm::Triple::mipsel; 6336 CPU = Name; 6337 return llvm::StringSwitch<bool>(Name) 6338 .Case("mips1", IsMips32) 6339 .Case("mips2", IsMips32) 6340 .Case("mips3", true) 6341 .Case("mips4", true) 6342 .Case("mips5", true) 6343 .Case("mips32", IsMips32) 6344 .Case("mips32r2", IsMips32) 6345 .Case("mips32r3", IsMips32) 6346 .Case("mips32r5", IsMips32) 6347 .Case("mips32r6", IsMips32) 6348 .Case("mips64", true) 6349 .Case("mips64r2", true) 6350 .Case("mips64r3", true) 6351 .Case("mips64r5", true) 6352 .Case("mips64r6", true) 6353 .Case("octeon", true) 6354 .Case("p5600", true) 6355 .Default(false); 6356 } 6357 const std::string& getCPU() const { return CPU; } 6358 bool 6359 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6360 StringRef CPU, 6361 const std::vector<std::string> &FeaturesVec) const override { 6362 if (CPU == "octeon") 6363 Features["mips64r2"] = Features["cnmips"] = true; 6364 else 6365 Features[CPU] = true; 6366 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6367 } 6368 6369 void getTargetDefines(const LangOptions &Opts, 6370 MacroBuilder &Builder) const override { 6371 Builder.defineMacro("__mips__"); 6372 Builder.defineMacro("_mips"); 6373 if (Opts.GNUMode) 6374 Builder.defineMacro("mips"); 6375 6376 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6377 6378 switch (FloatABI) { 6379 case HardFloat: 6380 Builder.defineMacro("__mips_hard_float", Twine(1)); 6381 break; 6382 case SoftFloat: 6383 Builder.defineMacro("__mips_soft_float", Twine(1)); 6384 break; 6385 } 6386 6387 if (IsSingleFloat) 6388 Builder.defineMacro("__mips_single_float", Twine(1)); 6389 6390 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6391 Builder.defineMacro("_MIPS_FPSET", 6392 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6393 6394 if (IsMips16) 6395 Builder.defineMacro("__mips16", Twine(1)); 6396 6397 if (IsMicromips) 6398 Builder.defineMacro("__mips_micromips", Twine(1)); 6399 6400 if (IsNan2008) 6401 Builder.defineMacro("__mips_nan2008", Twine(1)); 6402 6403 switch (DspRev) { 6404 default: 6405 break; 6406 case DSP1: 6407 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6408 Builder.defineMacro("__mips_dsp", Twine(1)); 6409 break; 6410 case DSP2: 6411 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6412 Builder.defineMacro("__mips_dspr2", Twine(1)); 6413 Builder.defineMacro("__mips_dsp", Twine(1)); 6414 break; 6415 } 6416 6417 if (HasMSA) 6418 Builder.defineMacro("__mips_msa", Twine(1)); 6419 6420 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6421 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6422 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6423 6424 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6425 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6426 } 6427 6428 void getTargetBuiltins(const Builtin::Info *&Records, 6429 unsigned &NumRecords) const override { 6430 Records = BuiltinInfo; 6431 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 6432 } 6433 bool hasFeature(StringRef Feature) const override { 6434 return llvm::StringSwitch<bool>(Feature) 6435 .Case("mips", true) 6436 .Case("fp64", HasFP64) 6437 .Default(false); 6438 } 6439 BuiltinVaListKind getBuiltinVaListKind() const override { 6440 return TargetInfo::VoidPtrBuiltinVaList; 6441 } 6442 void getGCCRegNames(const char * const *&Names, 6443 unsigned &NumNames) const override { 6444 static const char *const GCCRegNames[] = { 6445 // CPU register names 6446 // Must match second column of GCCRegAliases 6447 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6448 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6449 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6450 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6451 // Floating point register names 6452 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6453 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6454 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6455 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6456 // Hi/lo and condition register names 6457 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6458 "$fcc5","$fcc6","$fcc7", 6459 // MSA register names 6460 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6461 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6462 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6463 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6464 // MSA control register names 6465 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6466 "$msarequest", "$msamap", "$msaunmap" 6467 }; 6468 Names = GCCRegNames; 6469 NumNames = llvm::array_lengthof(GCCRegNames); 6470 } 6471 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6472 unsigned &NumAliases) const override = 0; 6473 bool validateAsmConstraint(const char *&Name, 6474 TargetInfo::ConstraintInfo &Info) const override { 6475 switch (*Name) { 6476 default: 6477 return false; 6478 case 'r': // CPU registers. 6479 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6480 case 'y': // Equivalent to "r", backward compatibility only. 6481 case 'f': // floating-point registers. 6482 case 'c': // $25 for indirect jumps 6483 case 'l': // lo register 6484 case 'x': // hilo register pair 6485 Info.setAllowsRegister(); 6486 return true; 6487 case 'I': // Signed 16-bit constant 6488 case 'J': // Integer 0 6489 case 'K': // Unsigned 16-bit constant 6490 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6491 case 'M': // Constants not loadable via lui, addiu, or ori 6492 case 'N': // Constant -1 to -65535 6493 case 'O': // A signed 15-bit constant 6494 case 'P': // A constant between 1 go 65535 6495 return true; 6496 case 'R': // An address that can be used in a non-macro load or store 6497 Info.setAllowsMemory(); 6498 return true; 6499 case 'Z': 6500 if (Name[1] == 'C') { // An address usable by ll, and sc. 6501 Info.setAllowsMemory(); 6502 Name++; // Skip over 'Z'. 6503 return true; 6504 } 6505 return false; 6506 } 6507 } 6508 6509 std::string convertConstraint(const char *&Constraint) const override { 6510 std::string R; 6511 switch (*Constraint) { 6512 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6513 if (Constraint[1] == 'C') { 6514 R = std::string("^") + std::string(Constraint, 2); 6515 Constraint++; 6516 return R; 6517 } 6518 break; 6519 } 6520 return TargetInfo::convertConstraint(Constraint); 6521 } 6522 6523 const char *getClobbers() const override { 6524 // In GCC, $1 is not widely used in generated code (it's used only in a few 6525 // specific situations), so there is no real need for users to add it to 6526 // the clobbers list if they want to use it in their inline assembly code. 6527 // 6528 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6529 // code generation, so using it in inline assembly without adding it to the 6530 // clobbers list can cause conflicts between the inline assembly code and 6531 // the surrounding generated code. 6532 // 6533 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6534 // operands, which will conflict with the ".set at" assembler option (which 6535 // we use only for inline assembly, in order to maintain compatibility with 6536 // GCC) and will also conflict with the user's usage of $1. 6537 // 6538 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6539 // register for generated code is to automatically clobber $1 for all inline 6540 // assembly code. 6541 // 6542 // FIXME: We should automatically clobber $1 only for inline assembly code 6543 // which actually uses it. This would allow LLVM to use $1 for inline 6544 // assembly operands if the user's assembly code doesn't use it. 6545 return "~{$1}"; 6546 } 6547 6548 bool handleTargetFeatures(std::vector<std::string> &Features, 6549 DiagnosticsEngine &Diags) override { 6550 IsMips16 = false; 6551 IsMicromips = false; 6552 IsNan2008 = isNaN2008Default(); 6553 IsSingleFloat = false; 6554 FloatABI = HardFloat; 6555 DspRev = NoDSP; 6556 HasFP64 = isFP64Default(); 6557 6558 for (const auto &Feature : Features) { 6559 if (Feature == "+single-float") 6560 IsSingleFloat = true; 6561 else if (Feature == "+soft-float") 6562 FloatABI = SoftFloat; 6563 else if (Feature == "+mips16") 6564 IsMips16 = true; 6565 else if (Feature == "+micromips") 6566 IsMicromips = true; 6567 else if (Feature == "+dsp") 6568 DspRev = std::max(DspRev, DSP1); 6569 else if (Feature == "+dspr2") 6570 DspRev = std::max(DspRev, DSP2); 6571 else if (Feature == "+msa") 6572 HasMSA = true; 6573 else if (Feature == "+fp64") 6574 HasFP64 = true; 6575 else if (Feature == "-fp64") 6576 HasFP64 = false; 6577 else if (Feature == "+nan2008") 6578 IsNan2008 = true; 6579 else if (Feature == "-nan2008") 6580 IsNan2008 = false; 6581 } 6582 6583 setDataLayoutString(); 6584 6585 return true; 6586 } 6587 6588 int getEHDataRegisterNumber(unsigned RegNo) const override { 6589 if (RegNo == 0) return 4; 6590 if (RegNo == 1) return 5; 6591 return -1; 6592 } 6593 6594 bool isCLZForZeroUndef() const override { return false; } 6595 }; 6596 6597 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6598 #define BUILTIN(ID, TYPE, ATTRS) \ 6599 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6600 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6601 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6602 #include "clang/Basic/BuiltinsMips.def" 6603 }; 6604 6605 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6606 public: 6607 Mips32TargetInfoBase(const llvm::Triple &Triple) 6608 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6609 SizeType = UnsignedInt; 6610 PtrDiffType = SignedInt; 6611 Int64Type = SignedLongLong; 6612 IntMaxType = Int64Type; 6613 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6614 } 6615 bool setABI(const std::string &Name) override { 6616 if (Name == "o32" || Name == "eabi") { 6617 ABI = Name; 6618 return true; 6619 } 6620 return false; 6621 } 6622 void getTargetDefines(const LangOptions &Opts, 6623 MacroBuilder &Builder) const override { 6624 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6625 6626 Builder.defineMacro("__mips", "32"); 6627 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6628 6629 const std::string& CPUStr = getCPU(); 6630 if (CPUStr == "mips32") 6631 Builder.defineMacro("__mips_isa_rev", "1"); 6632 else if (CPUStr == "mips32r2") 6633 Builder.defineMacro("__mips_isa_rev", "2"); 6634 else if (CPUStr == "mips32r3") 6635 Builder.defineMacro("__mips_isa_rev", "3"); 6636 else if (CPUStr == "mips32r5") 6637 Builder.defineMacro("__mips_isa_rev", "5"); 6638 else if (CPUStr == "mips32r6") 6639 Builder.defineMacro("__mips_isa_rev", "6"); 6640 6641 if (ABI == "o32") { 6642 Builder.defineMacro("__mips_o32"); 6643 Builder.defineMacro("_ABIO32", "1"); 6644 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6645 } 6646 else if (ABI == "eabi") 6647 Builder.defineMacro("__mips_eabi"); 6648 else 6649 llvm_unreachable("Invalid ABI for Mips32."); 6650 } 6651 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6652 unsigned &NumAliases) const override { 6653 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6654 { { "at" }, "$1" }, 6655 { { "v0" }, "$2" }, 6656 { { "v1" }, "$3" }, 6657 { { "a0" }, "$4" }, 6658 { { "a1" }, "$5" }, 6659 { { "a2" }, "$6" }, 6660 { { "a3" }, "$7" }, 6661 { { "t0" }, "$8" }, 6662 { { "t1" }, "$9" }, 6663 { { "t2" }, "$10" }, 6664 { { "t3" }, "$11" }, 6665 { { "t4" }, "$12" }, 6666 { { "t5" }, "$13" }, 6667 { { "t6" }, "$14" }, 6668 { { "t7" }, "$15" }, 6669 { { "s0" }, "$16" }, 6670 { { "s1" }, "$17" }, 6671 { { "s2" }, "$18" }, 6672 { { "s3" }, "$19" }, 6673 { { "s4" }, "$20" }, 6674 { { "s5" }, "$21" }, 6675 { { "s6" }, "$22" }, 6676 { { "s7" }, "$23" }, 6677 { { "t8" }, "$24" }, 6678 { { "t9" }, "$25" }, 6679 { { "k0" }, "$26" }, 6680 { { "k1" }, "$27" }, 6681 { { "gp" }, "$28" }, 6682 { { "sp","$sp" }, "$29" }, 6683 { { "fp","$fp" }, "$30" }, 6684 { { "ra" }, "$31" } 6685 }; 6686 Aliases = GCCRegAliases; 6687 NumAliases = llvm::array_lengthof(GCCRegAliases); 6688 } 6689 }; 6690 6691 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6692 void setDataLayoutString() override { 6693 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6694 } 6695 6696 public: 6697 Mips32EBTargetInfo(const llvm::Triple &Triple) 6698 : Mips32TargetInfoBase(Triple) { 6699 } 6700 void getTargetDefines(const LangOptions &Opts, 6701 MacroBuilder &Builder) const override { 6702 DefineStd(Builder, "MIPSEB", Opts); 6703 Builder.defineMacro("_MIPSEB"); 6704 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6705 } 6706 }; 6707 6708 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6709 void setDataLayoutString() override { 6710 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6711 } 6712 6713 public: 6714 Mips32ELTargetInfo(const llvm::Triple &Triple) 6715 : Mips32TargetInfoBase(Triple) { 6716 BigEndian = false; 6717 } 6718 void getTargetDefines(const LangOptions &Opts, 6719 MacroBuilder &Builder) const override { 6720 DefineStd(Builder, "MIPSEL", Opts); 6721 Builder.defineMacro("_MIPSEL"); 6722 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6723 } 6724 }; 6725 6726 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6727 public: 6728 Mips64TargetInfoBase(const llvm::Triple &Triple) 6729 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6730 LongDoubleWidth = LongDoubleAlign = 128; 6731 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6732 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6733 LongDoubleWidth = LongDoubleAlign = 64; 6734 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6735 } 6736 setN64ABITypes(); 6737 SuitableAlign = 128; 6738 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6739 } 6740 6741 void setN64ABITypes() { 6742 LongWidth = LongAlign = 64; 6743 PointerWidth = PointerAlign = 64; 6744 SizeType = UnsignedLong; 6745 PtrDiffType = SignedLong; 6746 Int64Type = SignedLong; 6747 IntMaxType = Int64Type; 6748 } 6749 6750 void setN32ABITypes() { 6751 LongWidth = LongAlign = 32; 6752 PointerWidth = PointerAlign = 32; 6753 SizeType = UnsignedInt; 6754 PtrDiffType = SignedInt; 6755 Int64Type = SignedLongLong; 6756 IntMaxType = Int64Type; 6757 } 6758 6759 bool setABI(const std::string &Name) override { 6760 if (Name == "n32") { 6761 setN32ABITypes(); 6762 ABI = Name; 6763 return true; 6764 } 6765 if (Name == "n64") { 6766 setN64ABITypes(); 6767 ABI = Name; 6768 return true; 6769 } 6770 return false; 6771 } 6772 6773 void getTargetDefines(const LangOptions &Opts, 6774 MacroBuilder &Builder) const override { 6775 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6776 6777 Builder.defineMacro("__mips", "64"); 6778 Builder.defineMacro("__mips64"); 6779 Builder.defineMacro("__mips64__"); 6780 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6781 6782 const std::string& CPUStr = getCPU(); 6783 if (CPUStr == "mips64") 6784 Builder.defineMacro("__mips_isa_rev", "1"); 6785 else if (CPUStr == "mips64r2") 6786 Builder.defineMacro("__mips_isa_rev", "2"); 6787 else if (CPUStr == "mips64r3") 6788 Builder.defineMacro("__mips_isa_rev", "3"); 6789 else if (CPUStr == "mips64r5") 6790 Builder.defineMacro("__mips_isa_rev", "5"); 6791 else if (CPUStr == "mips64r6") 6792 Builder.defineMacro("__mips_isa_rev", "6"); 6793 6794 if (ABI == "n32") { 6795 Builder.defineMacro("__mips_n32"); 6796 Builder.defineMacro("_ABIN32", "2"); 6797 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6798 } 6799 else if (ABI == "n64") { 6800 Builder.defineMacro("__mips_n64"); 6801 Builder.defineMacro("_ABI64", "3"); 6802 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6803 } 6804 else 6805 llvm_unreachable("Invalid ABI for Mips64."); 6806 } 6807 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6808 unsigned &NumAliases) const override { 6809 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6810 { { "at" }, "$1" }, 6811 { { "v0" }, "$2" }, 6812 { { "v1" }, "$3" }, 6813 { { "a0" }, "$4" }, 6814 { { "a1" }, "$5" }, 6815 { { "a2" }, "$6" }, 6816 { { "a3" }, "$7" }, 6817 { { "a4" }, "$8" }, 6818 { { "a5" }, "$9" }, 6819 { { "a6" }, "$10" }, 6820 { { "a7" }, "$11" }, 6821 { { "t0" }, "$12" }, 6822 { { "t1" }, "$13" }, 6823 { { "t2" }, "$14" }, 6824 { { "t3" }, "$15" }, 6825 { { "s0" }, "$16" }, 6826 { { "s1" }, "$17" }, 6827 { { "s2" }, "$18" }, 6828 { { "s3" }, "$19" }, 6829 { { "s4" }, "$20" }, 6830 { { "s5" }, "$21" }, 6831 { { "s6" }, "$22" }, 6832 { { "s7" }, "$23" }, 6833 { { "t8" }, "$24" }, 6834 { { "t9" }, "$25" }, 6835 { { "k0" }, "$26" }, 6836 { { "k1" }, "$27" }, 6837 { { "gp" }, "$28" }, 6838 { { "sp","$sp" }, "$29" }, 6839 { { "fp","$fp" }, "$30" }, 6840 { { "ra" }, "$31" } 6841 }; 6842 Aliases = GCCRegAliases; 6843 NumAliases = llvm::array_lengthof(GCCRegAliases); 6844 } 6845 6846 bool hasInt128Type() const override { return true; } 6847 }; 6848 6849 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6850 void setDataLayoutString() override { 6851 if (ABI == "n32") 6852 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6853 else 6854 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6855 6856 } 6857 6858 public: 6859 Mips64EBTargetInfo(const llvm::Triple &Triple) 6860 : Mips64TargetInfoBase(Triple) {} 6861 void getTargetDefines(const LangOptions &Opts, 6862 MacroBuilder &Builder) const override { 6863 DefineStd(Builder, "MIPSEB", Opts); 6864 Builder.defineMacro("_MIPSEB"); 6865 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6866 } 6867 }; 6868 6869 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6870 void setDataLayoutString() override { 6871 if (ABI == "n32") 6872 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6873 else 6874 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6875 } 6876 public: 6877 Mips64ELTargetInfo(const llvm::Triple &Triple) 6878 : Mips64TargetInfoBase(Triple) { 6879 // Default ABI is n64. 6880 BigEndian = false; 6881 } 6882 void getTargetDefines(const LangOptions &Opts, 6883 MacroBuilder &Builder) const override { 6884 DefineStd(Builder, "MIPSEL", Opts); 6885 Builder.defineMacro("_MIPSEL"); 6886 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6887 } 6888 }; 6889 6890 class PNaClTargetInfo : public TargetInfo { 6891 public: 6892 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6893 BigEndian = false; 6894 this->UserLabelPrefix = ""; 6895 this->LongAlign = 32; 6896 this->LongWidth = 32; 6897 this->PointerAlign = 32; 6898 this->PointerWidth = 32; 6899 this->IntMaxType = TargetInfo::SignedLongLong; 6900 this->Int64Type = TargetInfo::SignedLongLong; 6901 this->DoubleAlign = 64; 6902 this->LongDoubleWidth = 64; 6903 this->LongDoubleAlign = 64; 6904 this->SizeType = TargetInfo::UnsignedInt; 6905 this->PtrDiffType = TargetInfo::SignedInt; 6906 this->IntPtrType = TargetInfo::SignedInt; 6907 this->RegParmMax = 0; // Disallow regparm 6908 } 6909 6910 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6911 Builder.defineMacro("__le32__"); 6912 Builder.defineMacro("__pnacl__"); 6913 } 6914 void getTargetDefines(const LangOptions &Opts, 6915 MacroBuilder &Builder) const override { 6916 getArchDefines(Opts, Builder); 6917 } 6918 bool hasFeature(StringRef Feature) const override { 6919 return Feature == "pnacl"; 6920 } 6921 void getTargetBuiltins(const Builtin::Info *&Records, 6922 unsigned &NumRecords) const override { 6923 } 6924 BuiltinVaListKind getBuiltinVaListKind() const override { 6925 return TargetInfo::PNaClABIBuiltinVaList; 6926 } 6927 void getGCCRegNames(const char * const *&Names, 6928 unsigned &NumNames) const override; 6929 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6930 unsigned &NumAliases) const override; 6931 bool validateAsmConstraint(const char *&Name, 6932 TargetInfo::ConstraintInfo &Info) const override { 6933 return false; 6934 } 6935 6936 const char *getClobbers() const override { 6937 return ""; 6938 } 6939 }; 6940 6941 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6942 unsigned &NumNames) const { 6943 Names = nullptr; 6944 NumNames = 0; 6945 } 6946 6947 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6948 unsigned &NumAliases) const { 6949 Aliases = nullptr; 6950 NumAliases = 0; 6951 } 6952 6953 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 6954 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 6955 public: 6956 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 6957 Mips32ELTargetInfo(Triple) { 6958 } 6959 6960 BuiltinVaListKind getBuiltinVaListKind() const override { 6961 return TargetInfo::PNaClABIBuiltinVaList; 6962 } 6963 }; 6964 6965 class Le64TargetInfo : public TargetInfo { 6966 static const Builtin::Info BuiltinInfo[]; 6967 6968 public: 6969 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6970 BigEndian = false; 6971 NoAsmVariants = true; 6972 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6973 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6974 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6975 } 6976 6977 void getTargetDefines(const LangOptions &Opts, 6978 MacroBuilder &Builder) const override { 6979 DefineStd(Builder, "unix", Opts); 6980 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6981 Builder.defineMacro("__ELF__"); 6982 } 6983 void getTargetBuiltins(const Builtin::Info *&Records, 6984 unsigned &NumRecords) const override { 6985 Records = BuiltinInfo; 6986 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6987 } 6988 BuiltinVaListKind getBuiltinVaListKind() const override { 6989 return TargetInfo::PNaClABIBuiltinVaList; 6990 } 6991 const char *getClobbers() const override { return ""; } 6992 void getGCCRegNames(const char *const *&Names, 6993 unsigned &NumNames) const override { 6994 Names = nullptr; 6995 NumNames = 0; 6996 } 6997 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6998 unsigned &NumAliases) const override { 6999 Aliases = nullptr; 7000 NumAliases = 0; 7001 } 7002 bool validateAsmConstraint(const char *&Name, 7003 TargetInfo::ConstraintInfo &Info) const override { 7004 return false; 7005 } 7006 7007 bool hasProtectedVisibility() const override { return false; } 7008 }; 7009 7010 class WebAssemblyTargetInfo : public TargetInfo { 7011 static const Builtin::Info BuiltinInfo[]; 7012 7013 enum SIMDEnum { 7014 NoSIMD, 7015 SIMD128, 7016 } SIMDLevel; 7017 7018 public: 7019 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 7020 : TargetInfo(T), SIMDLevel(NoSIMD) { 7021 BigEndian = false; 7022 NoAsmVariants = true; 7023 SuitableAlign = 128; 7024 LargeArrayMinWidth = 128; 7025 LargeArrayAlign = 128; 7026 SimdDefaultAlign = 128; 7027 SigAtomicType = SignedLong; 7028 } 7029 7030 protected: 7031 void getTargetDefines(const LangOptions &Opts, 7032 MacroBuilder &Builder) const override { 7033 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7034 if (SIMDLevel >= SIMD128) 7035 Builder.defineMacro("__wasm_simd128__"); 7036 } 7037 7038 private: 7039 bool 7040 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7041 StringRef CPU, 7042 const std::vector<std::string> &FeaturesVec) const override { 7043 if (CPU == "bleeding-edge") 7044 Features["simd128"] = true; 7045 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7046 } 7047 bool hasFeature(StringRef Feature) const final { 7048 return llvm::StringSwitch<bool>(Feature) 7049 .Case("simd128", SIMDLevel >= SIMD128) 7050 .Default(false); 7051 } 7052 bool handleTargetFeatures(std::vector<std::string> &Features, 7053 DiagnosticsEngine &Diags) final { 7054 for (const auto &Feature : Features) { 7055 if (Feature == "+simd128") { 7056 SIMDLevel = std::max(SIMDLevel, SIMD128); 7057 continue; 7058 } 7059 if (Feature == "-simd128") { 7060 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7061 continue; 7062 } 7063 7064 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7065 << "-target-feature"; 7066 return false; 7067 } 7068 return true; 7069 } 7070 bool setCPU(const std::string &Name) final { 7071 return llvm::StringSwitch<bool>(Name) 7072 .Case("mvp", true) 7073 .Case("bleeding-edge", true) 7074 .Case("generic", true) 7075 .Default(false); 7076 } 7077 void getTargetBuiltins(const Builtin::Info *&Records, 7078 unsigned &NumRecords) const final { 7079 Records = BuiltinInfo; 7080 NumRecords = clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin; 7081 } 7082 BuiltinVaListKind getBuiltinVaListKind() const final { 7083 // TODO: Implement va_list properly. 7084 return VoidPtrBuiltinVaList; 7085 } 7086 void getGCCRegNames(const char *const *&Names, 7087 unsigned &NumNames) const final { 7088 Names = nullptr; 7089 NumNames = 0; 7090 } 7091 void getGCCRegAliases(const GCCRegAlias *&Aliases, 7092 unsigned &NumAliases) const final { 7093 Aliases = nullptr; 7094 NumAliases = 0; 7095 } 7096 bool 7097 validateAsmConstraint(const char *&Name, 7098 TargetInfo::ConstraintInfo &Info) const final { 7099 return false; 7100 } 7101 const char *getClobbers() const final { return ""; } 7102 bool isCLZForZeroUndef() const final { return false; } 7103 bool hasInt128Type() const final { return true; } 7104 IntType getIntTypeByWidth(unsigned BitWidth, 7105 bool IsSigned) const final { 7106 // WebAssembly prefers long long for explicitly 64-bit integers. 7107 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7108 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7109 } 7110 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7111 bool IsSigned) const final { 7112 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7113 return BitWidth == 64 7114 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7115 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7116 } 7117 }; 7118 7119 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7120 #define BUILTIN(ID, TYPE, ATTRS) \ 7121 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7122 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7123 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7124 #include "clang/Basic/BuiltinsWebAssembly.def" 7125 }; 7126 7127 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7128 public: 7129 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7130 : WebAssemblyTargetInfo(T) { 7131 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7132 DataLayoutString = "e-p:32:32-i64:64-n32:64-S128"; 7133 } 7134 7135 protected: 7136 void getTargetDefines(const LangOptions &Opts, 7137 MacroBuilder &Builder) const override { 7138 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7139 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7140 } 7141 }; 7142 7143 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7144 public: 7145 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7146 : WebAssemblyTargetInfo(T) { 7147 LongAlign = LongWidth = 64; 7148 PointerAlign = PointerWidth = 64; 7149 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7150 DataLayoutString = "e-p:64:64-i64:64-n32:64-S128"; 7151 } 7152 7153 protected: 7154 void getTargetDefines(const LangOptions &Opts, 7155 MacroBuilder &Builder) const override { 7156 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7157 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7158 } 7159 }; 7160 7161 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7162 #define BUILTIN(ID, TYPE, ATTRS) \ 7163 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7164 #include "clang/Basic/BuiltinsLe64.def" 7165 }; 7166 7167 static const unsigned SPIRAddrSpaceMap[] = { 7168 1, // opencl_global 7169 3, // opencl_local 7170 2, // opencl_constant 7171 4, // opencl_generic 7172 0, // cuda_device 7173 0, // cuda_constant 7174 0 // cuda_shared 7175 }; 7176 class SPIRTargetInfo : public TargetInfo { 7177 public: 7178 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7179 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7180 "SPIR target must use unknown OS"); 7181 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7182 "SPIR target must use unknown environment type"); 7183 BigEndian = false; 7184 TLSSupported = false; 7185 LongWidth = LongAlign = 64; 7186 AddrSpaceMap = &SPIRAddrSpaceMap; 7187 UseAddrSpaceMapMangling = true; 7188 // Define available target features 7189 // These must be defined in sorted order! 7190 NoAsmVariants = true; 7191 } 7192 void getTargetDefines(const LangOptions &Opts, 7193 MacroBuilder &Builder) const override { 7194 DefineStd(Builder, "SPIR", Opts); 7195 } 7196 bool hasFeature(StringRef Feature) const override { 7197 return Feature == "spir"; 7198 } 7199 7200 void getTargetBuiltins(const Builtin::Info *&Records, 7201 unsigned &NumRecords) const override {} 7202 const char *getClobbers() const override { return ""; } 7203 void getGCCRegNames(const char *const *&Names, 7204 unsigned &NumNames) const override {} 7205 bool validateAsmConstraint(const char *&Name, 7206 TargetInfo::ConstraintInfo &info) const override { 7207 return true; 7208 } 7209 void getGCCRegAliases(const GCCRegAlias *&Aliases, 7210 unsigned &NumAliases) const override {} 7211 BuiltinVaListKind getBuiltinVaListKind() const override { 7212 return TargetInfo::VoidPtrBuiltinVaList; 7213 } 7214 7215 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7216 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7217 : CCCR_Warning; 7218 } 7219 7220 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7221 return CC_SpirFunction; 7222 } 7223 }; 7224 7225 class SPIR32TargetInfo : public SPIRTargetInfo { 7226 public: 7227 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7228 PointerWidth = PointerAlign = 32; 7229 SizeType = TargetInfo::UnsignedInt; 7230 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7231 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7232 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7233 } 7234 void getTargetDefines(const LangOptions &Opts, 7235 MacroBuilder &Builder) const override { 7236 DefineStd(Builder, "SPIR32", Opts); 7237 } 7238 }; 7239 7240 class SPIR64TargetInfo : public SPIRTargetInfo { 7241 public: 7242 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7243 PointerWidth = PointerAlign = 64; 7244 SizeType = TargetInfo::UnsignedLong; 7245 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7246 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7247 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7248 } 7249 void getTargetDefines(const LangOptions &Opts, 7250 MacroBuilder &Builder) const override { 7251 DefineStd(Builder, "SPIR64", Opts); 7252 } 7253 }; 7254 7255 class XCoreTargetInfo : public TargetInfo { 7256 static const Builtin::Info BuiltinInfo[]; 7257 public: 7258 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7259 BigEndian = false; 7260 NoAsmVariants = true; 7261 LongLongAlign = 32; 7262 SuitableAlign = 32; 7263 DoubleAlign = LongDoubleAlign = 32; 7264 SizeType = UnsignedInt; 7265 PtrDiffType = SignedInt; 7266 IntPtrType = SignedInt; 7267 WCharType = UnsignedChar; 7268 WIntType = UnsignedInt; 7269 UseZeroLengthBitfieldAlignment = true; 7270 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7271 "-f64:32-a:0:32-n32"; 7272 } 7273 void getTargetDefines(const LangOptions &Opts, 7274 MacroBuilder &Builder) const override { 7275 Builder.defineMacro("__XS1B__"); 7276 } 7277 void getTargetBuiltins(const Builtin::Info *&Records, 7278 unsigned &NumRecords) const override { 7279 Records = BuiltinInfo; 7280 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 7281 } 7282 BuiltinVaListKind getBuiltinVaListKind() const override { 7283 return TargetInfo::VoidPtrBuiltinVaList; 7284 } 7285 const char *getClobbers() const override { 7286 return ""; 7287 } 7288 void getGCCRegNames(const char * const *&Names, 7289 unsigned &NumNames) const override { 7290 static const char * const GCCRegNames[] = { 7291 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7292 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7293 }; 7294 Names = GCCRegNames; 7295 NumNames = llvm::array_lengthof(GCCRegNames); 7296 } 7297 void getGCCRegAliases(const GCCRegAlias *&Aliases, 7298 unsigned &NumAliases) const override { 7299 Aliases = nullptr; 7300 NumAliases = 0; 7301 } 7302 bool validateAsmConstraint(const char *&Name, 7303 TargetInfo::ConstraintInfo &Info) const override { 7304 return false; 7305 } 7306 int getEHDataRegisterNumber(unsigned RegNo) const override { 7307 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7308 return (RegNo < 2)? RegNo : -1; 7309 } 7310 }; 7311 7312 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7313 #define BUILTIN(ID, TYPE, ATTRS) \ 7314 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7315 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7316 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7317 #include "clang/Basic/BuiltinsXCore.def" 7318 }; 7319 7320 // x86_32 Android target 7321 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7322 public: 7323 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7324 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7325 SuitableAlign = 32; 7326 LongDoubleWidth = 64; 7327 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7328 } 7329 }; 7330 7331 // x86_64 Android target 7332 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7333 public: 7334 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7335 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7336 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7337 } 7338 7339 bool useFloat128ManglingForLongDouble() const override { 7340 return true; 7341 } 7342 }; 7343 } // end anonymous namespace 7344 7345 //===----------------------------------------------------------------------===// 7346 // Driver code 7347 //===----------------------------------------------------------------------===// 7348 7349 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7350 llvm::Triple::OSType os = Triple.getOS(); 7351 7352 switch (Triple.getArch()) { 7353 default: 7354 return nullptr; 7355 7356 case llvm::Triple::xcore: 7357 return new XCoreTargetInfo(Triple); 7358 7359 case llvm::Triple::hexagon: 7360 return new HexagonTargetInfo(Triple); 7361 7362 case llvm::Triple::aarch64: 7363 if (Triple.isOSDarwin()) 7364 return new DarwinAArch64TargetInfo(Triple); 7365 7366 switch (os) { 7367 case llvm::Triple::CloudABI: 7368 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple); 7369 case llvm::Triple::FreeBSD: 7370 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7371 case llvm::Triple::Linux: 7372 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7373 case llvm::Triple::NetBSD: 7374 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7375 default: 7376 return new AArch64leTargetInfo(Triple); 7377 } 7378 7379 case llvm::Triple::aarch64_be: 7380 switch (os) { 7381 case llvm::Triple::FreeBSD: 7382 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7383 case llvm::Triple::Linux: 7384 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7385 case llvm::Triple::NetBSD: 7386 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7387 default: 7388 return new AArch64beTargetInfo(Triple); 7389 } 7390 7391 case llvm::Triple::arm: 7392 case llvm::Triple::thumb: 7393 if (Triple.isOSBinFormatMachO()) 7394 return new DarwinARMTargetInfo(Triple); 7395 7396 switch (os) { 7397 case llvm::Triple::Linux: 7398 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7399 case llvm::Triple::FreeBSD: 7400 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7401 case llvm::Triple::NetBSD: 7402 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7403 case llvm::Triple::OpenBSD: 7404 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7405 case llvm::Triple::Bitrig: 7406 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7407 case llvm::Triple::RTEMS: 7408 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7409 case llvm::Triple::NaCl: 7410 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7411 case llvm::Triple::Win32: 7412 switch (Triple.getEnvironment()) { 7413 case llvm::Triple::Cygnus: 7414 return new CygwinARMTargetInfo(Triple); 7415 case llvm::Triple::GNU: 7416 return new MinGWARMTargetInfo(Triple); 7417 case llvm::Triple::Itanium: 7418 return new ItaniumWindowsARMleTargetInfo(Triple); 7419 case llvm::Triple::MSVC: 7420 default: // Assume MSVC for unknown environments 7421 return new MicrosoftARMleTargetInfo(Triple); 7422 } 7423 default: 7424 return new ARMleTargetInfo(Triple); 7425 } 7426 7427 case llvm::Triple::armeb: 7428 case llvm::Triple::thumbeb: 7429 if (Triple.isOSDarwin()) 7430 return new DarwinARMTargetInfo(Triple); 7431 7432 switch (os) { 7433 case llvm::Triple::Linux: 7434 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7435 case llvm::Triple::FreeBSD: 7436 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7437 case llvm::Triple::NetBSD: 7438 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7439 case llvm::Triple::OpenBSD: 7440 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7441 case llvm::Triple::Bitrig: 7442 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7443 case llvm::Triple::RTEMS: 7444 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7445 case llvm::Triple::NaCl: 7446 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7447 default: 7448 return new ARMbeTargetInfo(Triple); 7449 } 7450 7451 case llvm::Triple::bpfeb: 7452 case llvm::Triple::bpfel: 7453 return new BPFTargetInfo(Triple); 7454 7455 case llvm::Triple::msp430: 7456 return new MSP430TargetInfo(Triple); 7457 7458 case llvm::Triple::mips: 7459 switch (os) { 7460 case llvm::Triple::Linux: 7461 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7462 case llvm::Triple::RTEMS: 7463 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7464 case llvm::Triple::FreeBSD: 7465 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7466 case llvm::Triple::NetBSD: 7467 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7468 default: 7469 return new Mips32EBTargetInfo(Triple); 7470 } 7471 7472 case llvm::Triple::mipsel: 7473 switch (os) { 7474 case llvm::Triple::Linux: 7475 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7476 case llvm::Triple::RTEMS: 7477 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7478 case llvm::Triple::FreeBSD: 7479 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7480 case llvm::Triple::NetBSD: 7481 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7482 case llvm::Triple::NaCl: 7483 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7484 default: 7485 return new Mips32ELTargetInfo(Triple); 7486 } 7487 7488 case llvm::Triple::mips64: 7489 switch (os) { 7490 case llvm::Triple::Linux: 7491 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7492 case llvm::Triple::RTEMS: 7493 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7494 case llvm::Triple::FreeBSD: 7495 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7496 case llvm::Triple::NetBSD: 7497 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7498 case llvm::Triple::OpenBSD: 7499 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7500 default: 7501 return new Mips64EBTargetInfo(Triple); 7502 } 7503 7504 case llvm::Triple::mips64el: 7505 switch (os) { 7506 case llvm::Triple::Linux: 7507 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7508 case llvm::Triple::RTEMS: 7509 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7510 case llvm::Triple::FreeBSD: 7511 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7512 case llvm::Triple::NetBSD: 7513 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7514 case llvm::Triple::OpenBSD: 7515 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7516 default: 7517 return new Mips64ELTargetInfo(Triple); 7518 } 7519 7520 case llvm::Triple::le32: 7521 switch (os) { 7522 case llvm::Triple::NaCl: 7523 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7524 default: 7525 return nullptr; 7526 } 7527 7528 case llvm::Triple::le64: 7529 return new Le64TargetInfo(Triple); 7530 7531 case llvm::Triple::ppc: 7532 if (Triple.isOSDarwin()) 7533 return new DarwinPPC32TargetInfo(Triple); 7534 switch (os) { 7535 case llvm::Triple::Linux: 7536 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7537 case llvm::Triple::FreeBSD: 7538 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7539 case llvm::Triple::NetBSD: 7540 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7541 case llvm::Triple::OpenBSD: 7542 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7543 case llvm::Triple::RTEMS: 7544 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7545 default: 7546 return new PPC32TargetInfo(Triple); 7547 } 7548 7549 case llvm::Triple::ppc64: 7550 if (Triple.isOSDarwin()) 7551 return new DarwinPPC64TargetInfo(Triple); 7552 switch (os) { 7553 case llvm::Triple::Linux: 7554 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7555 case llvm::Triple::Lv2: 7556 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7557 case llvm::Triple::FreeBSD: 7558 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7559 case llvm::Triple::NetBSD: 7560 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7561 default: 7562 return new PPC64TargetInfo(Triple); 7563 } 7564 7565 case llvm::Triple::ppc64le: 7566 switch (os) { 7567 case llvm::Triple::Linux: 7568 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7569 case llvm::Triple::NetBSD: 7570 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7571 default: 7572 return new PPC64TargetInfo(Triple); 7573 } 7574 7575 case llvm::Triple::nvptx: 7576 return new NVPTX32TargetInfo(Triple); 7577 case llvm::Triple::nvptx64: 7578 return new NVPTX64TargetInfo(Triple); 7579 7580 case llvm::Triple::amdgcn: 7581 case llvm::Triple::r600: 7582 return new AMDGPUTargetInfo(Triple); 7583 7584 case llvm::Triple::sparc: 7585 switch (os) { 7586 case llvm::Triple::Linux: 7587 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7588 case llvm::Triple::Solaris: 7589 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7590 case llvm::Triple::NetBSD: 7591 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7592 case llvm::Triple::OpenBSD: 7593 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7594 case llvm::Triple::RTEMS: 7595 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7596 default: 7597 return new SparcV8TargetInfo(Triple); 7598 } 7599 7600 // The 'sparcel' architecture copies all the above cases except for Solaris. 7601 case llvm::Triple::sparcel: 7602 switch (os) { 7603 case llvm::Triple::Linux: 7604 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7605 case llvm::Triple::NetBSD: 7606 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7607 case llvm::Triple::OpenBSD: 7608 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7609 case llvm::Triple::RTEMS: 7610 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7611 default: 7612 return new SparcV8elTargetInfo(Triple); 7613 } 7614 7615 case llvm::Triple::sparcv9: 7616 switch (os) { 7617 case llvm::Triple::Linux: 7618 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7619 case llvm::Triple::Solaris: 7620 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7621 case llvm::Triple::NetBSD: 7622 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7623 case llvm::Triple::OpenBSD: 7624 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7625 case llvm::Triple::FreeBSD: 7626 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7627 default: 7628 return new SparcV9TargetInfo(Triple); 7629 } 7630 7631 case llvm::Triple::systemz: 7632 switch (os) { 7633 case llvm::Triple::Linux: 7634 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7635 default: 7636 return new SystemZTargetInfo(Triple); 7637 } 7638 7639 case llvm::Triple::tce: 7640 return new TCETargetInfo(Triple); 7641 7642 case llvm::Triple::x86: 7643 if (Triple.isOSDarwin()) 7644 return new DarwinI386TargetInfo(Triple); 7645 7646 switch (os) { 7647 case llvm::Triple::CloudABI: 7648 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7649 case llvm::Triple::Linux: { 7650 switch (Triple.getEnvironment()) { 7651 default: 7652 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7653 case llvm::Triple::Android: 7654 return new AndroidX86_32TargetInfo(Triple); 7655 } 7656 } 7657 case llvm::Triple::DragonFly: 7658 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7659 case llvm::Triple::NetBSD: 7660 return new NetBSDI386TargetInfo(Triple); 7661 case llvm::Triple::OpenBSD: 7662 return new OpenBSDI386TargetInfo(Triple); 7663 case llvm::Triple::Bitrig: 7664 return new BitrigI386TargetInfo(Triple); 7665 case llvm::Triple::FreeBSD: 7666 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7667 case llvm::Triple::KFreeBSD: 7668 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7669 case llvm::Triple::Minix: 7670 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7671 case llvm::Triple::Solaris: 7672 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7673 case llvm::Triple::Win32: { 7674 switch (Triple.getEnvironment()) { 7675 case llvm::Triple::Cygnus: 7676 return new CygwinX86_32TargetInfo(Triple); 7677 case llvm::Triple::GNU: 7678 return new MinGWX86_32TargetInfo(Triple); 7679 case llvm::Triple::Itanium: 7680 case llvm::Triple::MSVC: 7681 default: // Assume MSVC for unknown environments 7682 return new MicrosoftX86_32TargetInfo(Triple); 7683 } 7684 } 7685 case llvm::Triple::Haiku: 7686 return new HaikuX86_32TargetInfo(Triple); 7687 case llvm::Triple::RTEMS: 7688 return new RTEMSX86_32TargetInfo(Triple); 7689 case llvm::Triple::NaCl: 7690 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7691 default: 7692 return new X86_32TargetInfo(Triple); 7693 } 7694 7695 case llvm::Triple::x86_64: 7696 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7697 return new DarwinX86_64TargetInfo(Triple); 7698 7699 switch (os) { 7700 case llvm::Triple::CloudABI: 7701 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7702 case llvm::Triple::Linux: { 7703 switch (Triple.getEnvironment()) { 7704 default: 7705 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7706 case llvm::Triple::Android: 7707 return new AndroidX86_64TargetInfo(Triple); 7708 } 7709 } 7710 case llvm::Triple::DragonFly: 7711 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7712 case llvm::Triple::NetBSD: 7713 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7714 case llvm::Triple::OpenBSD: 7715 return new OpenBSDX86_64TargetInfo(Triple); 7716 case llvm::Triple::Bitrig: 7717 return new BitrigX86_64TargetInfo(Triple); 7718 case llvm::Triple::FreeBSD: 7719 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7720 case llvm::Triple::KFreeBSD: 7721 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7722 case llvm::Triple::Solaris: 7723 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7724 case llvm::Triple::Win32: { 7725 switch (Triple.getEnvironment()) { 7726 case llvm::Triple::Cygnus: 7727 return new CygwinX86_64TargetInfo(Triple); 7728 case llvm::Triple::GNU: 7729 return new MinGWX86_64TargetInfo(Triple); 7730 case llvm::Triple::MSVC: 7731 default: // Assume MSVC for unknown environments 7732 return new MicrosoftX86_64TargetInfo(Triple); 7733 } 7734 } 7735 case llvm::Triple::NaCl: 7736 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7737 case llvm::Triple::PS4: 7738 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7739 default: 7740 return new X86_64TargetInfo(Triple); 7741 } 7742 7743 case llvm::Triple::spir: { 7744 if (Triple.getOS() != llvm::Triple::UnknownOS || 7745 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7746 return nullptr; 7747 return new SPIR32TargetInfo(Triple); 7748 } 7749 case llvm::Triple::spir64: { 7750 if (Triple.getOS() != llvm::Triple::UnknownOS || 7751 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7752 return nullptr; 7753 return new SPIR64TargetInfo(Triple); 7754 } 7755 case llvm::Triple::wasm32: 7756 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 7757 return nullptr; 7758 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 7759 case llvm::Triple::wasm64: 7760 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 7761 return nullptr; 7762 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 7763 } 7764 } 7765 7766 /// CreateTargetInfo - Return the target info object for the specified target 7767 /// options. 7768 TargetInfo * 7769 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7770 const std::shared_ptr<TargetOptions> &Opts) { 7771 llvm::Triple Triple(Opts->Triple); 7772 7773 // Construct the target 7774 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7775 if (!Target) { 7776 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7777 return nullptr; 7778 } 7779 Target->TargetOpts = Opts; 7780 7781 // Set the target CPU if specified. 7782 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7783 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7784 return nullptr; 7785 } 7786 7787 // Set the target ABI if specified. 7788 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7789 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7790 return nullptr; 7791 } 7792 7793 // Set the fp math unit. 7794 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7795 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7796 return nullptr; 7797 } 7798 7799 // Compute the default target features, we need the target to handle this 7800 // because features may have dependencies on one another. 7801 llvm::StringMap<bool> Features; 7802 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 7803 Opts->FeaturesAsWritten)) 7804 return nullptr; 7805 7806 // Add the features to the compile options. 7807 Opts->Features.clear(); 7808 for (const auto &F : Features) 7809 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 7810 7811 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7812 return nullptr; 7813 7814 return Target.release(); 7815 } 7816