1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 if (Maj) 469 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 470 } 471 if (Opts.POSIXThreads) 472 Builder.defineMacro("_REENTRANT"); 473 if (Opts.CPlusPlus) 474 Builder.defineMacro("_GNU_SOURCE"); 475 if (this->HasFloat128) 476 Builder.defineMacro("__FLOAT128__"); 477 } 478 public: 479 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 480 : OSTargetInfo<Target>(Triple, Opts) { 481 this->WIntType = TargetInfo::UnsignedInt; 482 483 switch (Triple.getArch()) { 484 default: 485 break; 486 case llvm::Triple::ppc: 487 case llvm::Triple::ppc64: 488 case llvm::Triple::ppc64le: 489 this->MCountName = "_mcount"; 490 break; 491 case llvm::Triple::x86: 492 case llvm::Triple::x86_64: 493 case llvm::Triple::systemz: 494 this->HasFloat128 = true; 495 break; 496 } 497 } 498 499 const char *getStaticInitSectionSpecifier() const override { 500 return ".text.startup"; 501 } 502 }; 503 504 // NetBSD Target 505 template<typename Target> 506 class NetBSDTargetInfo : public OSTargetInfo<Target> { 507 protected: 508 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 509 MacroBuilder &Builder) const override { 510 // NetBSD defines; list based off of gcc output 511 Builder.defineMacro("__NetBSD__"); 512 Builder.defineMacro("__unix__"); 513 Builder.defineMacro("__ELF__"); 514 if (Opts.POSIXThreads) 515 Builder.defineMacro("_REENTRANT"); 516 517 switch (Triple.getArch()) { 518 default: 519 break; 520 case llvm::Triple::arm: 521 case llvm::Triple::armeb: 522 case llvm::Triple::thumb: 523 case llvm::Triple::thumbeb: 524 Builder.defineMacro("__ARM_DWARF_EH__"); 525 break; 526 } 527 } 528 public: 529 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 530 : OSTargetInfo<Target>(Triple, Opts) { 531 this->MCountName = "_mcount"; 532 } 533 }; 534 535 // OpenBSD Target 536 template<typename Target> 537 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 538 protected: 539 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 540 MacroBuilder &Builder) const override { 541 // OpenBSD defines; list based off of gcc output 542 543 Builder.defineMacro("__OpenBSD__"); 544 DefineStd(Builder, "unix", Opts); 545 Builder.defineMacro("__ELF__"); 546 if (Opts.POSIXThreads) 547 Builder.defineMacro("_REENTRANT"); 548 if (this->HasFloat128) 549 Builder.defineMacro("__FLOAT128__"); 550 } 551 public: 552 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 553 : OSTargetInfo<Target>(Triple, Opts) { 554 this->TLSSupported = false; 555 556 switch (Triple.getArch()) { 557 case llvm::Triple::x86: 558 case llvm::Triple::x86_64: 559 this->HasFloat128 = true; 560 // FALLTHROUGH 561 default: 562 this->MCountName = "__mcount"; 563 break; 564 case llvm::Triple::mips64: 565 case llvm::Triple::mips64el: 566 case llvm::Triple::ppc: 567 case llvm::Triple::sparcv9: 568 this->MCountName = "_mcount"; 569 break; 570 } 571 } 572 }; 573 574 // Bitrig Target 575 template<typename Target> 576 class BitrigTargetInfo : public OSTargetInfo<Target> { 577 protected: 578 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 579 MacroBuilder &Builder) const override { 580 // Bitrig defines; list based off of gcc output 581 582 Builder.defineMacro("__Bitrig__"); 583 DefineStd(Builder, "unix", Opts); 584 Builder.defineMacro("__ELF__"); 585 if (Opts.POSIXThreads) 586 Builder.defineMacro("_REENTRANT"); 587 588 switch (Triple.getArch()) { 589 default: 590 break; 591 case llvm::Triple::arm: 592 case llvm::Triple::armeb: 593 case llvm::Triple::thumb: 594 case llvm::Triple::thumbeb: 595 Builder.defineMacro("__ARM_DWARF_EH__"); 596 break; 597 } 598 } 599 public: 600 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 601 : OSTargetInfo<Target>(Triple, Opts) { 602 this->MCountName = "__mcount"; 603 } 604 }; 605 606 // PSP Target 607 template<typename Target> 608 class PSPTargetInfo : public OSTargetInfo<Target> { 609 protected: 610 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 611 MacroBuilder &Builder) const override { 612 // PSP defines; list based on the output of the pspdev gcc toolchain. 613 Builder.defineMacro("PSP"); 614 Builder.defineMacro("_PSP"); 615 Builder.defineMacro("__psp__"); 616 Builder.defineMacro("__ELF__"); 617 } 618 public: 619 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 620 }; 621 622 // PS3 PPU Target 623 template<typename Target> 624 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 625 protected: 626 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 627 MacroBuilder &Builder) const override { 628 // PS3 PPU defines. 629 Builder.defineMacro("__PPC__"); 630 Builder.defineMacro("__PPU__"); 631 Builder.defineMacro("__CELLOS_LV2__"); 632 Builder.defineMacro("__ELF__"); 633 Builder.defineMacro("__LP32__"); 634 Builder.defineMacro("_ARCH_PPC64"); 635 Builder.defineMacro("__powerpc64__"); 636 } 637 public: 638 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 639 : OSTargetInfo<Target>(Triple, Opts) { 640 this->LongWidth = this->LongAlign = 32; 641 this->PointerWidth = this->PointerAlign = 32; 642 this->IntMaxType = TargetInfo::SignedLongLong; 643 this->Int64Type = TargetInfo::SignedLongLong; 644 this->SizeType = TargetInfo::UnsignedInt; 645 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 646 } 647 }; 648 649 template <typename Target> 650 class PS4OSTargetInfo : public OSTargetInfo<Target> { 651 protected: 652 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 653 MacroBuilder &Builder) const override { 654 Builder.defineMacro("__FreeBSD__", "9"); 655 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 656 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 657 DefineStd(Builder, "unix", Opts); 658 Builder.defineMacro("__ELF__"); 659 Builder.defineMacro("__ORBIS__"); 660 } 661 public: 662 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 663 : OSTargetInfo<Target>(Triple, Opts) { 664 this->WCharType = this->UnsignedShort; 665 666 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 667 this->MaxTLSAlign = 256; 668 669 // On PS4, do not honor explicit bit field alignment, 670 // as in "__attribute__((aligned(2))) int b : 1;". 671 this->UseExplicitBitFieldAlignment = false; 672 673 switch (Triple.getArch()) { 674 default: 675 case llvm::Triple::x86_64: 676 this->MCountName = ".mcount"; 677 break; 678 } 679 } 680 }; 681 682 // Solaris target 683 template<typename Target> 684 class SolarisTargetInfo : public OSTargetInfo<Target> { 685 protected: 686 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 687 MacroBuilder &Builder) const override { 688 DefineStd(Builder, "sun", Opts); 689 DefineStd(Builder, "unix", Opts); 690 Builder.defineMacro("__ELF__"); 691 Builder.defineMacro("__svr4__"); 692 Builder.defineMacro("__SVR4"); 693 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 694 // newer, but to 500 for everything else. feature_test.h has a check to 695 // ensure that you are not using C99 with an old version of X/Open or C89 696 // with a new version. 697 if (Opts.C99) 698 Builder.defineMacro("_XOPEN_SOURCE", "600"); 699 else 700 Builder.defineMacro("_XOPEN_SOURCE", "500"); 701 if (Opts.CPlusPlus) 702 Builder.defineMacro("__C99FEATURES__"); 703 Builder.defineMacro("_LARGEFILE_SOURCE"); 704 Builder.defineMacro("_LARGEFILE64_SOURCE"); 705 Builder.defineMacro("__EXTENSIONS__"); 706 Builder.defineMacro("_REENTRANT"); 707 } 708 public: 709 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 710 : OSTargetInfo<Target>(Triple, Opts) { 711 this->WCharType = this->SignedInt; 712 // FIXME: WIntType should be SignedLong 713 } 714 }; 715 716 // Windows target 717 template<typename Target> 718 class WindowsTargetInfo : public OSTargetInfo<Target> { 719 protected: 720 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 721 MacroBuilder &Builder) const override { 722 Builder.defineMacro("_WIN32"); 723 } 724 void getVisualStudioDefines(const LangOptions &Opts, 725 MacroBuilder &Builder) const { 726 if (Opts.CPlusPlus) { 727 if (Opts.RTTIData) 728 Builder.defineMacro("_CPPRTTI"); 729 730 if (Opts.CXXExceptions) 731 Builder.defineMacro("_CPPUNWIND"); 732 } 733 734 if (Opts.Bool) 735 Builder.defineMacro("__BOOL_DEFINED"); 736 737 if (!Opts.CharIsSigned) 738 Builder.defineMacro("_CHAR_UNSIGNED"); 739 740 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 741 // but it works for now. 742 if (Opts.POSIXThreads) 743 Builder.defineMacro("_MT"); 744 745 if (Opts.MSCompatibilityVersion) { 746 Builder.defineMacro("_MSC_VER", 747 Twine(Opts.MSCompatibilityVersion / 100000)); 748 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 749 // FIXME We cannot encode the revision information into 32-bits 750 Builder.defineMacro("_MSC_BUILD", Twine(1)); 751 752 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 753 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 754 755 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 756 if (Opts.CPlusPlus1z) 757 Builder.defineMacro("_MSVC_LANG", "201403L"); 758 else if (Opts.CPlusPlus14) 759 Builder.defineMacro("_MSVC_LANG", "201402L"); 760 } 761 } 762 763 if (Opts.MicrosoftExt) { 764 Builder.defineMacro("_MSC_EXTENSIONS"); 765 766 if (Opts.CPlusPlus11) { 767 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 768 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 769 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 770 } 771 } 772 773 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 774 } 775 776 public: 777 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 778 : OSTargetInfo<Target>(Triple, Opts) {} 779 }; 780 781 template <typename Target> 782 class NaClTargetInfo : public OSTargetInfo<Target> { 783 protected: 784 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 785 MacroBuilder &Builder) const override { 786 if (Opts.POSIXThreads) 787 Builder.defineMacro("_REENTRANT"); 788 if (Opts.CPlusPlus) 789 Builder.defineMacro("_GNU_SOURCE"); 790 791 DefineStd(Builder, "unix", Opts); 792 Builder.defineMacro("__ELF__"); 793 Builder.defineMacro("__native_client__"); 794 } 795 796 public: 797 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 798 : OSTargetInfo<Target>(Triple, Opts) { 799 this->LongAlign = 32; 800 this->LongWidth = 32; 801 this->PointerAlign = 32; 802 this->PointerWidth = 32; 803 this->IntMaxType = TargetInfo::SignedLongLong; 804 this->Int64Type = TargetInfo::SignedLongLong; 805 this->DoubleAlign = 64; 806 this->LongDoubleWidth = 64; 807 this->LongDoubleAlign = 64; 808 this->LongLongWidth = 64; 809 this->LongLongAlign = 64; 810 this->SizeType = TargetInfo::UnsignedInt; 811 this->PtrDiffType = TargetInfo::SignedInt; 812 this->IntPtrType = TargetInfo::SignedInt; 813 // RegParmMax is inherited from the underlying architecture. 814 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 815 if (Triple.getArch() == llvm::Triple::arm) { 816 // Handled in ARM's setABI(). 817 } else if (Triple.getArch() == llvm::Triple::x86) { 818 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 819 } else if (Triple.getArch() == llvm::Triple::x86_64) { 820 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 821 } else if (Triple.getArch() == llvm::Triple::mipsel) { 822 // Handled on mips' setDataLayout. 823 } else { 824 assert(Triple.getArch() == llvm::Triple::le32); 825 this->resetDataLayout("e-p:32:32-i64:64"); 826 } 827 } 828 }; 829 830 // Fuchsia Target 831 template<typename Target> 832 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 833 protected: 834 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 835 MacroBuilder &Builder) const override { 836 Builder.defineMacro("__Fuchsia__"); 837 Builder.defineMacro("__ELF__"); 838 if (Opts.POSIXThreads) 839 Builder.defineMacro("_REENTRANT"); 840 // Required by the libc++ locale support. 841 if (Opts.CPlusPlus) 842 Builder.defineMacro("_GNU_SOURCE"); 843 } 844 public: 845 FuchsiaTargetInfo(const llvm::Triple &Triple, 846 const TargetOptions &Opts) 847 : OSTargetInfo<Target>(Triple, Opts) { 848 this->MCountName = "__mcount"; 849 } 850 }; 851 852 // WebAssembly target 853 template <typename Target> 854 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 855 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 856 MacroBuilder &Builder) const final { 857 // A common platform macro. 858 if (Opts.POSIXThreads) 859 Builder.defineMacro("_REENTRANT"); 860 // Follow g++ convention and predefine _GNU_SOURCE for C++. 861 if (Opts.CPlusPlus) 862 Builder.defineMacro("_GNU_SOURCE"); 863 } 864 865 // As an optimization, group static init code together in a section. 866 const char *getStaticInitSectionSpecifier() const final { 867 return ".text.__startup"; 868 } 869 870 public: 871 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 872 const TargetOptions &Opts) 873 : OSTargetInfo<Target>(Triple, Opts) { 874 this->MCountName = "__mcount"; 875 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 876 } 877 }; 878 879 //===----------------------------------------------------------------------===// 880 // Specific target implementations. 881 //===----------------------------------------------------------------------===// 882 883 // PPC abstract base class 884 class PPCTargetInfo : public TargetInfo { 885 static const Builtin::Info BuiltinInfo[]; 886 static const char * const GCCRegNames[]; 887 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 888 std::string CPU; 889 890 // Target cpu features. 891 bool HasVSX; 892 bool HasP8Vector; 893 bool HasP8Crypto; 894 bool HasDirectMove; 895 bool HasQPX; 896 bool HasHTM; 897 bool HasBPERMD; 898 bool HasExtDiv; 899 bool HasP9Vector; 900 901 protected: 902 std::string ABI; 903 904 public: 905 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 906 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 907 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 908 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 909 SimdDefaultAlign = 128; 910 LongDoubleWidth = LongDoubleAlign = 128; 911 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 912 } 913 914 /// \brief Flags for architecture specific defines. 915 typedef enum { 916 ArchDefineNone = 0, 917 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 918 ArchDefinePpcgr = 1 << 1, 919 ArchDefinePpcsq = 1 << 2, 920 ArchDefine440 = 1 << 3, 921 ArchDefine603 = 1 << 4, 922 ArchDefine604 = 1 << 5, 923 ArchDefinePwr4 = 1 << 6, 924 ArchDefinePwr5 = 1 << 7, 925 ArchDefinePwr5x = 1 << 8, 926 ArchDefinePwr6 = 1 << 9, 927 ArchDefinePwr6x = 1 << 10, 928 ArchDefinePwr7 = 1 << 11, 929 ArchDefinePwr8 = 1 << 12, 930 ArchDefinePwr9 = 1 << 13, 931 ArchDefineA2 = 1 << 14, 932 ArchDefineA2q = 1 << 15 933 } ArchDefineTypes; 934 935 // Note: GCC recognizes the following additional cpus: 936 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 937 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 938 // titan, rs64. 939 bool setCPU(const std::string &Name) override { 940 bool CPUKnown = llvm::StringSwitch<bool>(Name) 941 .Case("generic", true) 942 .Case("440", true) 943 .Case("450", true) 944 .Case("601", true) 945 .Case("602", true) 946 .Case("603", true) 947 .Case("603e", true) 948 .Case("603ev", true) 949 .Case("604", true) 950 .Case("604e", true) 951 .Case("620", true) 952 .Case("630", true) 953 .Case("g3", true) 954 .Case("7400", true) 955 .Case("g4", true) 956 .Case("7450", true) 957 .Case("g4+", true) 958 .Case("750", true) 959 .Case("970", true) 960 .Case("g5", true) 961 .Case("a2", true) 962 .Case("a2q", true) 963 .Case("e500mc", true) 964 .Case("e5500", true) 965 .Case("power3", true) 966 .Case("pwr3", true) 967 .Case("power4", true) 968 .Case("pwr4", true) 969 .Case("power5", true) 970 .Case("pwr5", true) 971 .Case("power5x", true) 972 .Case("pwr5x", true) 973 .Case("power6", true) 974 .Case("pwr6", true) 975 .Case("power6x", true) 976 .Case("pwr6x", true) 977 .Case("power7", true) 978 .Case("pwr7", true) 979 .Case("power8", true) 980 .Case("pwr8", true) 981 .Case("power9", true) 982 .Case("pwr9", true) 983 .Case("powerpc", true) 984 .Case("ppc", true) 985 .Case("powerpc64", true) 986 .Case("ppc64", true) 987 .Case("powerpc64le", true) 988 .Case("ppc64le", true) 989 .Default(false); 990 991 if (CPUKnown) 992 CPU = Name; 993 994 return CPUKnown; 995 } 996 997 998 StringRef getABI() const override { return ABI; } 999 1000 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1001 return llvm::makeArrayRef(BuiltinInfo, 1002 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1003 } 1004 1005 bool isCLZForZeroUndef() const override { return false; } 1006 1007 void getTargetDefines(const LangOptions &Opts, 1008 MacroBuilder &Builder) const override; 1009 1010 bool 1011 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1012 StringRef CPU, 1013 const std::vector<std::string> &FeaturesVec) const override; 1014 1015 bool handleTargetFeatures(std::vector<std::string> &Features, 1016 DiagnosticsEngine &Diags) override; 1017 bool hasFeature(StringRef Feature) const override; 1018 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1019 bool Enabled) const override; 1020 1021 ArrayRef<const char *> getGCCRegNames() const override; 1022 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1023 bool validateAsmConstraint(const char *&Name, 1024 TargetInfo::ConstraintInfo &Info) const override { 1025 switch (*Name) { 1026 default: return false; 1027 case 'O': // Zero 1028 break; 1029 case 'b': // Base register 1030 case 'f': // Floating point register 1031 Info.setAllowsRegister(); 1032 break; 1033 // FIXME: The following are added to allow parsing. 1034 // I just took a guess at what the actions should be. 1035 // Also, is more specific checking needed? I.e. specific registers? 1036 case 'd': // Floating point register (containing 64-bit value) 1037 case 'v': // Altivec vector register 1038 Info.setAllowsRegister(); 1039 break; 1040 case 'w': 1041 switch (Name[1]) { 1042 case 'd':// VSX vector register to hold vector double data 1043 case 'f':// VSX vector register to hold vector float data 1044 case 's':// VSX vector register to hold scalar float data 1045 case 'a':// Any VSX register 1046 case 'c':// An individual CR bit 1047 break; 1048 default: 1049 return false; 1050 } 1051 Info.setAllowsRegister(); 1052 Name++; // Skip over 'w'. 1053 break; 1054 case 'h': // `MQ', `CTR', or `LINK' register 1055 case 'q': // `MQ' register 1056 case 'c': // `CTR' register 1057 case 'l': // `LINK' register 1058 case 'x': // `CR' register (condition register) number 0 1059 case 'y': // `CR' register (condition register) 1060 case 'z': // `XER[CA]' carry bit (part of the XER register) 1061 Info.setAllowsRegister(); 1062 break; 1063 case 'I': // Signed 16-bit constant 1064 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1065 // (use `L' instead for SImode constants) 1066 case 'K': // Unsigned 16-bit constant 1067 case 'L': // Signed 16-bit constant shifted left 16 bits 1068 case 'M': // Constant larger than 31 1069 case 'N': // Exact power of 2 1070 case 'P': // Constant whose negation is a signed 16-bit constant 1071 case 'G': // Floating point constant that can be loaded into a 1072 // register with one instruction per word 1073 case 'H': // Integer/Floating point constant that can be loaded 1074 // into a register using three instructions 1075 break; 1076 case 'm': // Memory operand. Note that on PowerPC targets, m can 1077 // include addresses that update the base register. It 1078 // is therefore only safe to use `m' in an asm statement 1079 // if that asm statement accesses the operand exactly once. 1080 // The asm statement must also use `%U<opno>' as a 1081 // placeholder for the "update" flag in the corresponding 1082 // load or store instruction. For example: 1083 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1084 // is correct but: 1085 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1086 // is not. Use es rather than m if you don't want the base 1087 // register to be updated. 1088 case 'e': 1089 if (Name[1] != 's') 1090 return false; 1091 // es: A "stable" memory operand; that is, one which does not 1092 // include any automodification of the base register. Unlike 1093 // `m', this constraint can be used in asm statements that 1094 // might access the operand several times, or that might not 1095 // access it at all. 1096 Info.setAllowsMemory(); 1097 Name++; // Skip over 'e'. 1098 break; 1099 case 'Q': // Memory operand that is an offset from a register (it is 1100 // usually better to use `m' or `es' in asm statements) 1101 case 'Z': // Memory operand that is an indexed or indirect from a 1102 // register (it is usually better to use `m' or `es' in 1103 // asm statements) 1104 Info.setAllowsMemory(); 1105 Info.setAllowsRegister(); 1106 break; 1107 case 'R': // AIX TOC entry 1108 case 'a': // Address operand that is an indexed or indirect from a 1109 // register (`p' is preferable for asm statements) 1110 case 'S': // Constant suitable as a 64-bit mask operand 1111 case 'T': // Constant suitable as a 32-bit mask operand 1112 case 'U': // System V Release 4 small data area reference 1113 case 't': // AND masks that can be performed by two rldic{l, r} 1114 // instructions 1115 case 'W': // Vector constant that does not require memory 1116 case 'j': // Vector constant that is all zeros. 1117 break; 1118 // End FIXME. 1119 } 1120 return true; 1121 } 1122 std::string convertConstraint(const char *&Constraint) const override { 1123 std::string R; 1124 switch (*Constraint) { 1125 case 'e': 1126 case 'w': 1127 // Two-character constraint; add "^" hint for later parsing. 1128 R = std::string("^") + std::string(Constraint, 2); 1129 Constraint++; 1130 break; 1131 default: 1132 return TargetInfo::convertConstraint(Constraint); 1133 } 1134 return R; 1135 } 1136 const char *getClobbers() const override { 1137 return ""; 1138 } 1139 int getEHDataRegisterNumber(unsigned RegNo) const override { 1140 if (RegNo == 0) return 3; 1141 if (RegNo == 1) return 4; 1142 return -1; 1143 } 1144 1145 bool hasSjLjLowering() const override { 1146 return true; 1147 } 1148 1149 bool useFloat128ManglingForLongDouble() const override { 1150 return LongDoubleWidth == 128 && 1151 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1152 getTriple().isOSBinFormatELF(); 1153 } 1154 }; 1155 1156 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1157 #define BUILTIN(ID, TYPE, ATTRS) \ 1158 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1159 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1160 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1161 #include "clang/Basic/BuiltinsPPC.def" 1162 }; 1163 1164 /// handleTargetFeatures - Perform initialization based on the user 1165 /// configured set of features. 1166 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1167 DiagnosticsEngine &Diags) { 1168 for (const auto &Feature : Features) { 1169 if (Feature == "+vsx") { 1170 HasVSX = true; 1171 } else if (Feature == "+bpermd") { 1172 HasBPERMD = true; 1173 } else if (Feature == "+extdiv") { 1174 HasExtDiv = true; 1175 } else if (Feature == "+power8-vector") { 1176 HasP8Vector = true; 1177 } else if (Feature == "+crypto") { 1178 HasP8Crypto = true; 1179 } else if (Feature == "+direct-move") { 1180 HasDirectMove = true; 1181 } else if (Feature == "+qpx") { 1182 HasQPX = true; 1183 } else if (Feature == "+htm") { 1184 HasHTM = true; 1185 } else if (Feature == "+float128") { 1186 HasFloat128 = true; 1187 } else if (Feature == "+power9-vector") { 1188 HasP9Vector = true; 1189 } 1190 // TODO: Finish this list and add an assert that we've handled them 1191 // all. 1192 } 1193 1194 return true; 1195 } 1196 1197 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1198 /// #defines that are not tied to a specific subtarget. 1199 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1200 MacroBuilder &Builder) const { 1201 // Target identification. 1202 Builder.defineMacro("__ppc__"); 1203 Builder.defineMacro("__PPC__"); 1204 Builder.defineMacro("_ARCH_PPC"); 1205 Builder.defineMacro("__powerpc__"); 1206 Builder.defineMacro("__POWERPC__"); 1207 if (PointerWidth == 64) { 1208 Builder.defineMacro("_ARCH_PPC64"); 1209 Builder.defineMacro("__powerpc64__"); 1210 Builder.defineMacro("__ppc64__"); 1211 Builder.defineMacro("__PPC64__"); 1212 } 1213 1214 // Target properties. 1215 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1216 Builder.defineMacro("_LITTLE_ENDIAN"); 1217 } else { 1218 if (getTriple().getOS() != llvm::Triple::NetBSD && 1219 getTriple().getOS() != llvm::Triple::OpenBSD) 1220 Builder.defineMacro("_BIG_ENDIAN"); 1221 } 1222 1223 // ABI options. 1224 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1225 Builder.defineMacro("_CALL_ELF", "1"); 1226 if (ABI == "elfv2") 1227 Builder.defineMacro("_CALL_ELF", "2"); 1228 1229 // Subtarget options. 1230 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1231 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1232 1233 // FIXME: Should be controlled by command line option. 1234 if (LongDoubleWidth == 128) 1235 Builder.defineMacro("__LONG_DOUBLE_128__"); 1236 1237 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1238 if (ABI == "elfv2" || 1239 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1240 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1241 1242 if (Opts.AltiVec) { 1243 Builder.defineMacro("__VEC__", "10206"); 1244 Builder.defineMacro("__ALTIVEC__"); 1245 } 1246 1247 // CPU identification. 1248 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1249 .Case("440", ArchDefineName) 1250 .Case("450", ArchDefineName | ArchDefine440) 1251 .Case("601", ArchDefineName) 1252 .Case("602", ArchDefineName | ArchDefinePpcgr) 1253 .Case("603", ArchDefineName | ArchDefinePpcgr) 1254 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1255 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1256 .Case("604", ArchDefineName | ArchDefinePpcgr) 1257 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1258 .Case("620", ArchDefineName | ArchDefinePpcgr) 1259 .Case("630", ArchDefineName | ArchDefinePpcgr) 1260 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1261 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1262 .Case("750", ArchDefineName | ArchDefinePpcgr) 1263 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1264 | ArchDefinePpcsq) 1265 .Case("a2", ArchDefineA2) 1266 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1267 .Case("pwr3", ArchDefinePpcgr) 1268 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1269 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1270 | ArchDefinePpcsq) 1271 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1272 | ArchDefinePpcgr | ArchDefinePpcsq) 1273 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1274 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1275 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1276 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1277 | ArchDefinePpcsq) 1278 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1279 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1280 | ArchDefinePpcgr | ArchDefinePpcsq) 1281 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1282 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1283 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1284 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1285 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1286 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1287 | ArchDefinePpcsq) 1288 .Case("power3", ArchDefinePpcgr) 1289 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1290 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1291 | ArchDefinePpcsq) 1292 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1293 | ArchDefinePpcgr | ArchDefinePpcsq) 1294 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1295 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1296 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1297 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1298 | ArchDefinePpcsq) 1299 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1300 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1301 | ArchDefinePpcgr | ArchDefinePpcsq) 1302 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1303 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1304 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1305 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1306 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1307 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1308 | ArchDefinePpcsq) 1309 .Default(ArchDefineNone); 1310 1311 if (defs & ArchDefineName) 1312 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1313 if (defs & ArchDefinePpcgr) 1314 Builder.defineMacro("_ARCH_PPCGR"); 1315 if (defs & ArchDefinePpcsq) 1316 Builder.defineMacro("_ARCH_PPCSQ"); 1317 if (defs & ArchDefine440) 1318 Builder.defineMacro("_ARCH_440"); 1319 if (defs & ArchDefine603) 1320 Builder.defineMacro("_ARCH_603"); 1321 if (defs & ArchDefine604) 1322 Builder.defineMacro("_ARCH_604"); 1323 if (defs & ArchDefinePwr4) 1324 Builder.defineMacro("_ARCH_PWR4"); 1325 if (defs & ArchDefinePwr5) 1326 Builder.defineMacro("_ARCH_PWR5"); 1327 if (defs & ArchDefinePwr5x) 1328 Builder.defineMacro("_ARCH_PWR5X"); 1329 if (defs & ArchDefinePwr6) 1330 Builder.defineMacro("_ARCH_PWR6"); 1331 if (defs & ArchDefinePwr6x) 1332 Builder.defineMacro("_ARCH_PWR6X"); 1333 if (defs & ArchDefinePwr7) 1334 Builder.defineMacro("_ARCH_PWR7"); 1335 if (defs & ArchDefinePwr8) 1336 Builder.defineMacro("_ARCH_PWR8"); 1337 if (defs & ArchDefinePwr9) 1338 Builder.defineMacro("_ARCH_PWR9"); 1339 if (defs & ArchDefineA2) 1340 Builder.defineMacro("_ARCH_A2"); 1341 if (defs & ArchDefineA2q) { 1342 Builder.defineMacro("_ARCH_A2Q"); 1343 Builder.defineMacro("_ARCH_QP"); 1344 } 1345 1346 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1347 Builder.defineMacro("__bg__"); 1348 Builder.defineMacro("__THW_BLUEGENE__"); 1349 Builder.defineMacro("__bgq__"); 1350 Builder.defineMacro("__TOS_BGQ__"); 1351 } 1352 1353 if (HasVSX) 1354 Builder.defineMacro("__VSX__"); 1355 if (HasP8Vector) 1356 Builder.defineMacro("__POWER8_VECTOR__"); 1357 if (HasP8Crypto) 1358 Builder.defineMacro("__CRYPTO__"); 1359 if (HasHTM) 1360 Builder.defineMacro("__HTM__"); 1361 if (HasFloat128) 1362 Builder.defineMacro("__FLOAT128__"); 1363 if (HasP9Vector) 1364 Builder.defineMacro("__POWER9_VECTOR__"); 1365 1366 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1367 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1368 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1369 if (PointerWidth == 64) 1370 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1371 1372 // FIXME: The following are not yet generated here by Clang, but are 1373 // generated by GCC: 1374 // 1375 // _SOFT_FLOAT_ 1376 // __RECIP_PRECISION__ 1377 // __APPLE_ALTIVEC__ 1378 // __RECIP__ 1379 // __RECIPF__ 1380 // __RSQRTE__ 1381 // __RSQRTEF__ 1382 // _SOFT_DOUBLE_ 1383 // __NO_LWSYNC__ 1384 // __HAVE_BSWAP__ 1385 // __LONGDOUBLE128 1386 // __CMODEL_MEDIUM__ 1387 // __CMODEL_LARGE__ 1388 // _CALL_SYSV 1389 // _CALL_DARWIN 1390 // __NO_FPRS__ 1391 } 1392 1393 // Handle explicit options being passed to the compiler here: if we've 1394 // explicitly turned off vsx and turned on any of: 1395 // - power8-vector 1396 // - direct-move 1397 // - float128 1398 // - power9-vector 1399 // then go ahead and error since the customer has expressed an incompatible 1400 // set of options. 1401 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1402 const std::vector<std::string> &FeaturesVec) { 1403 1404 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1405 FeaturesVec.end()) { 1406 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1407 FeaturesVec.end()) { 1408 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1409 << "-mno-vsx"; 1410 return false; 1411 } 1412 1413 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1414 FeaturesVec.end()) { 1415 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1416 << "-mno-vsx"; 1417 return false; 1418 } 1419 1420 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1421 FeaturesVec.end()) { 1422 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1423 << "-mno-vsx"; 1424 return false; 1425 } 1426 1427 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1428 FeaturesVec.end()) { 1429 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1430 << "-mno-vsx"; 1431 return false; 1432 } 1433 } 1434 1435 return true; 1436 } 1437 1438 bool PPCTargetInfo::initFeatureMap( 1439 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1440 const std::vector<std::string> &FeaturesVec) const { 1441 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1442 .Case("7400", true) 1443 .Case("g4", true) 1444 .Case("7450", true) 1445 .Case("g4+", true) 1446 .Case("970", true) 1447 .Case("g5", true) 1448 .Case("pwr6", true) 1449 .Case("pwr7", true) 1450 .Case("pwr8", true) 1451 .Case("pwr9", true) 1452 .Case("ppc64", true) 1453 .Case("ppc64le", true) 1454 .Default(false); 1455 1456 Features["qpx"] = (CPU == "a2q"); 1457 Features["power9-vector"] = (CPU == "pwr9"); 1458 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1459 .Case("ppc64le", true) 1460 .Case("pwr9", true) 1461 .Case("pwr8", true) 1462 .Default(false); 1463 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1464 .Case("ppc64le", true) 1465 .Case("pwr9", true) 1466 .Case("pwr8", true) 1467 .Default(false); 1468 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1469 .Case("ppc64le", true) 1470 .Case("pwr9", true) 1471 .Case("pwr8", true) 1472 .Case("pwr7", true) 1473 .Default(false); 1474 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1475 .Case("ppc64le", true) 1476 .Case("pwr9", true) 1477 .Case("pwr8", true) 1478 .Case("pwr7", true) 1479 .Default(false); 1480 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1481 .Case("ppc64le", true) 1482 .Case("pwr9", true) 1483 .Case("pwr8", true) 1484 .Default(false); 1485 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1486 .Case("ppc64le", true) 1487 .Case("pwr9", true) 1488 .Case("pwr8", true) 1489 .Case("pwr7", true) 1490 .Default(false); 1491 Features["htm"] = llvm::StringSwitch<bool>(CPU) 1492 .Case("ppc64le", true) 1493 .Case("pwr9", true) 1494 .Case("pwr8", true) 1495 .Default(false); 1496 1497 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1498 return false; 1499 1500 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1501 } 1502 1503 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1504 return llvm::StringSwitch<bool>(Feature) 1505 .Case("powerpc", true) 1506 .Case("vsx", HasVSX) 1507 .Case("power8-vector", HasP8Vector) 1508 .Case("crypto", HasP8Crypto) 1509 .Case("direct-move", HasDirectMove) 1510 .Case("qpx", HasQPX) 1511 .Case("htm", HasHTM) 1512 .Case("bpermd", HasBPERMD) 1513 .Case("extdiv", HasExtDiv) 1514 .Case("float128", HasFloat128) 1515 .Case("power9-vector", HasP9Vector) 1516 .Default(false); 1517 } 1518 1519 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1520 StringRef Name, bool Enabled) const { 1521 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1522 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1523 // incompatible options. 1524 if (Enabled) { 1525 if (Name == "direct-move" || 1526 Name == "power8-vector" || 1527 Name == "float128" || 1528 Name == "power9-vector") { 1529 // power9-vector is really a superset of power8-vector so encode that. 1530 Features[Name] = Features["vsx"] = true; 1531 if (Name == "power9-vector") 1532 Features["power8-vector"] = true; 1533 } else { 1534 Features[Name] = true; 1535 } 1536 } else { 1537 if (Name == "vsx") { 1538 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1539 Features["float128"] = Features["power9-vector"] = false; 1540 } else { 1541 Features[Name] = false; 1542 } 1543 } 1544 } 1545 1546 const char * const PPCTargetInfo::GCCRegNames[] = { 1547 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1548 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1549 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1550 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1551 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1552 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1553 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1554 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1555 "mq", "lr", "ctr", "ap", 1556 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1557 "xer", 1558 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1559 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1560 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1561 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1562 "vrsave", "vscr", 1563 "spe_acc", "spefscr", 1564 "sfp" 1565 }; 1566 1567 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1568 return llvm::makeArrayRef(GCCRegNames); 1569 } 1570 1571 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1572 // While some of these aliases do map to different registers 1573 // they still share the same register name. 1574 { { "0" }, "r0" }, 1575 { { "1"}, "r1" }, 1576 { { "2" }, "r2" }, 1577 { { "3" }, "r3" }, 1578 { { "4" }, "r4" }, 1579 { { "5" }, "r5" }, 1580 { { "6" }, "r6" }, 1581 { { "7" }, "r7" }, 1582 { { "8" }, "r8" }, 1583 { { "9" }, "r9" }, 1584 { { "10" }, "r10" }, 1585 { { "11" }, "r11" }, 1586 { { "12" }, "r12" }, 1587 { { "13" }, "r13" }, 1588 { { "14" }, "r14" }, 1589 { { "15" }, "r15" }, 1590 { { "16" }, "r16" }, 1591 { { "17" }, "r17" }, 1592 { { "18" }, "r18" }, 1593 { { "19" }, "r19" }, 1594 { { "20" }, "r20" }, 1595 { { "21" }, "r21" }, 1596 { { "22" }, "r22" }, 1597 { { "23" }, "r23" }, 1598 { { "24" }, "r24" }, 1599 { { "25" }, "r25" }, 1600 { { "26" }, "r26" }, 1601 { { "27" }, "r27" }, 1602 { { "28" }, "r28" }, 1603 { { "29" }, "r29" }, 1604 { { "30" }, "r30" }, 1605 { { "31" }, "r31" }, 1606 { { "fr0" }, "f0" }, 1607 { { "fr1" }, "f1" }, 1608 { { "fr2" }, "f2" }, 1609 { { "fr3" }, "f3" }, 1610 { { "fr4" }, "f4" }, 1611 { { "fr5" }, "f5" }, 1612 { { "fr6" }, "f6" }, 1613 { { "fr7" }, "f7" }, 1614 { { "fr8" }, "f8" }, 1615 { { "fr9" }, "f9" }, 1616 { { "fr10" }, "f10" }, 1617 { { "fr11" }, "f11" }, 1618 { { "fr12" }, "f12" }, 1619 { { "fr13" }, "f13" }, 1620 { { "fr14" }, "f14" }, 1621 { { "fr15" }, "f15" }, 1622 { { "fr16" }, "f16" }, 1623 { { "fr17" }, "f17" }, 1624 { { "fr18" }, "f18" }, 1625 { { "fr19" }, "f19" }, 1626 { { "fr20" }, "f20" }, 1627 { { "fr21" }, "f21" }, 1628 { { "fr22" }, "f22" }, 1629 { { "fr23" }, "f23" }, 1630 { { "fr24" }, "f24" }, 1631 { { "fr25" }, "f25" }, 1632 { { "fr26" }, "f26" }, 1633 { { "fr27" }, "f27" }, 1634 { { "fr28" }, "f28" }, 1635 { { "fr29" }, "f29" }, 1636 { { "fr30" }, "f30" }, 1637 { { "fr31" }, "f31" }, 1638 { { "cc" }, "cr0" }, 1639 }; 1640 1641 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1642 return llvm::makeArrayRef(GCCRegAliases); 1643 } 1644 1645 class PPC32TargetInfo : public PPCTargetInfo { 1646 public: 1647 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1648 : PPCTargetInfo(Triple, Opts) { 1649 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1650 1651 switch (getTriple().getOS()) { 1652 case llvm::Triple::Linux: 1653 case llvm::Triple::FreeBSD: 1654 case llvm::Triple::NetBSD: 1655 SizeType = UnsignedInt; 1656 PtrDiffType = SignedInt; 1657 IntPtrType = SignedInt; 1658 break; 1659 default: 1660 break; 1661 } 1662 1663 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1664 LongDoubleWidth = LongDoubleAlign = 64; 1665 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1666 } 1667 1668 // PPC32 supports atomics up to 4 bytes. 1669 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1670 } 1671 1672 BuiltinVaListKind getBuiltinVaListKind() const override { 1673 // This is the ELF definition, and is overridden by the Darwin sub-target 1674 return TargetInfo::PowerABIBuiltinVaList; 1675 } 1676 }; 1677 1678 // Note: ABI differences may eventually require us to have a separate 1679 // TargetInfo for little endian. 1680 class PPC64TargetInfo : public PPCTargetInfo { 1681 public: 1682 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1683 : PPCTargetInfo(Triple, Opts) { 1684 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1685 IntMaxType = SignedLong; 1686 Int64Type = SignedLong; 1687 1688 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1689 resetDataLayout("e-m:e-i64:64-n32:64"); 1690 ABI = "elfv2"; 1691 } else { 1692 resetDataLayout("E-m:e-i64:64-n32:64"); 1693 ABI = "elfv1"; 1694 } 1695 1696 switch (getTriple().getOS()) { 1697 case llvm::Triple::FreeBSD: 1698 LongDoubleWidth = LongDoubleAlign = 64; 1699 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1700 break; 1701 case llvm::Triple::NetBSD: 1702 IntMaxType = SignedLongLong; 1703 Int64Type = SignedLongLong; 1704 break; 1705 default: 1706 break; 1707 } 1708 1709 // PPC64 supports atomics up to 8 bytes. 1710 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1711 } 1712 BuiltinVaListKind getBuiltinVaListKind() const override { 1713 return TargetInfo::CharPtrBuiltinVaList; 1714 } 1715 // PPC64 Linux-specific ABI options. 1716 bool setABI(const std::string &Name) override { 1717 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1718 ABI = Name; 1719 return true; 1720 } 1721 return false; 1722 } 1723 }; 1724 1725 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1726 public: 1727 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1728 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1729 HasAlignMac68kSupport = true; 1730 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1731 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1732 LongLongAlign = 32; 1733 SuitableAlign = 128; 1734 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1735 } 1736 BuiltinVaListKind getBuiltinVaListKind() const override { 1737 return TargetInfo::CharPtrBuiltinVaList; 1738 } 1739 }; 1740 1741 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1742 public: 1743 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1744 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1745 HasAlignMac68kSupport = true; 1746 SuitableAlign = 128; 1747 resetDataLayout("E-m:o-i64:64-n32:64"); 1748 } 1749 }; 1750 1751 static const unsigned NVPTXAddrSpaceMap[] = { 1752 1, // opencl_global 1753 3, // opencl_local 1754 4, // opencl_constant 1755 // FIXME: generic has to be added to the target 1756 0, // opencl_generic 1757 1, // cuda_device 1758 4, // cuda_constant 1759 3, // cuda_shared 1760 }; 1761 1762 class NVPTXTargetInfo : public TargetInfo { 1763 static const char *const GCCRegNames[]; 1764 static const Builtin::Info BuiltinInfo[]; 1765 CudaArch GPU; 1766 std::unique_ptr<TargetInfo> HostTarget; 1767 1768 public: 1769 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1770 unsigned TargetPointerWidth) 1771 : TargetInfo(Triple) { 1772 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1773 "NVPTX only supports 32- and 64-bit modes."); 1774 1775 TLSSupported = false; 1776 AddrSpaceMap = &NVPTXAddrSpaceMap; 1777 UseAddrSpaceMapMangling = true; 1778 1779 // Define available target features 1780 // These must be defined in sorted order! 1781 NoAsmVariants = true; 1782 GPU = CudaArch::SM_20; 1783 1784 if (TargetPointerWidth == 32) 1785 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1786 else 1787 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1788 1789 // If possible, get a TargetInfo for our host triple, so we can match its 1790 // types. 1791 llvm::Triple HostTriple(Opts.HostTriple); 1792 if (!HostTriple.isNVPTX()) 1793 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1794 1795 // If no host target, make some guesses about the data layout and return. 1796 if (!HostTarget) { 1797 LongWidth = LongAlign = TargetPointerWidth; 1798 PointerWidth = PointerAlign = TargetPointerWidth; 1799 switch (TargetPointerWidth) { 1800 case 32: 1801 SizeType = TargetInfo::UnsignedInt; 1802 PtrDiffType = TargetInfo::SignedInt; 1803 IntPtrType = TargetInfo::SignedInt; 1804 break; 1805 case 64: 1806 SizeType = TargetInfo::UnsignedLong; 1807 PtrDiffType = TargetInfo::SignedLong; 1808 IntPtrType = TargetInfo::SignedLong; 1809 break; 1810 default: 1811 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1812 } 1813 return; 1814 } 1815 1816 // Copy properties from host target. 1817 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1818 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1819 BoolWidth = HostTarget->getBoolWidth(); 1820 BoolAlign = HostTarget->getBoolAlign(); 1821 IntWidth = HostTarget->getIntWidth(); 1822 IntAlign = HostTarget->getIntAlign(); 1823 HalfWidth = HostTarget->getHalfWidth(); 1824 HalfAlign = HostTarget->getHalfAlign(); 1825 FloatWidth = HostTarget->getFloatWidth(); 1826 FloatAlign = HostTarget->getFloatAlign(); 1827 DoubleWidth = HostTarget->getDoubleWidth(); 1828 DoubleAlign = HostTarget->getDoubleAlign(); 1829 LongWidth = HostTarget->getLongWidth(); 1830 LongAlign = HostTarget->getLongAlign(); 1831 LongLongWidth = HostTarget->getLongLongWidth(); 1832 LongLongAlign = HostTarget->getLongLongAlign(); 1833 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1834 NewAlign = HostTarget->getNewAlign(); 1835 DefaultAlignForAttributeAligned = 1836 HostTarget->getDefaultAlignForAttributeAligned(); 1837 SizeType = HostTarget->getSizeType(); 1838 IntMaxType = HostTarget->getIntMaxType(); 1839 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1840 IntPtrType = HostTarget->getIntPtrType(); 1841 WCharType = HostTarget->getWCharType(); 1842 WIntType = HostTarget->getWIntType(); 1843 Char16Type = HostTarget->getChar16Type(); 1844 Char32Type = HostTarget->getChar32Type(); 1845 Int64Type = HostTarget->getInt64Type(); 1846 SigAtomicType = HostTarget->getSigAtomicType(); 1847 ProcessIDType = HostTarget->getProcessIDType(); 1848 1849 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1850 UseZeroLengthBitfieldAlignment = 1851 HostTarget->useZeroLengthBitfieldAlignment(); 1852 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1853 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1854 1855 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1856 // we need those macros to be identical on host and device, because (among 1857 // other things) they affect which standard library classes are defined, and 1858 // we need all classes to be defined on both the host and device. 1859 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1860 1861 // Properties intentionally not copied from host: 1862 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1863 // host/device boundary. 1864 // - SuitableAlign: Not visible across the host/device boundary, and may 1865 // correctly be different on host/device, e.g. if host has wider vector 1866 // types than device. 1867 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1868 // as its double type, but that's not necessarily true on the host. 1869 // TODO: nvcc emits a warning when using long double on device; we should 1870 // do the same. 1871 } 1872 void getTargetDefines(const LangOptions &Opts, 1873 MacroBuilder &Builder) const override { 1874 Builder.defineMacro("__PTX__"); 1875 Builder.defineMacro("__NVPTX__"); 1876 if (Opts.CUDAIsDevice) { 1877 // Set __CUDA_ARCH__ for the GPU specified. 1878 std::string CUDAArchCode = [this] { 1879 switch (GPU) { 1880 case CudaArch::UNKNOWN: 1881 assert(false && "No GPU arch when compiling CUDA device code."); 1882 return ""; 1883 case CudaArch::SM_20: 1884 return "200"; 1885 case CudaArch::SM_21: 1886 return "210"; 1887 case CudaArch::SM_30: 1888 return "300"; 1889 case CudaArch::SM_32: 1890 return "320"; 1891 case CudaArch::SM_35: 1892 return "350"; 1893 case CudaArch::SM_37: 1894 return "370"; 1895 case CudaArch::SM_50: 1896 return "500"; 1897 case CudaArch::SM_52: 1898 return "520"; 1899 case CudaArch::SM_53: 1900 return "530"; 1901 case CudaArch::SM_60: 1902 return "600"; 1903 case CudaArch::SM_61: 1904 return "610"; 1905 case CudaArch::SM_62: 1906 return "620"; 1907 } 1908 llvm_unreachable("unhandled CudaArch"); 1909 }(); 1910 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1911 } 1912 } 1913 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1914 return llvm::makeArrayRef(BuiltinInfo, 1915 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1916 } 1917 bool 1918 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1919 StringRef CPU, 1920 const std::vector<std::string> &FeaturesVec) const override { 1921 Features["satom"] = GPU >= CudaArch::SM_60; 1922 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1923 } 1924 1925 bool hasFeature(StringRef Feature) const override { 1926 return llvm::StringSwitch<bool>(Feature) 1927 .Cases("ptx", "nvptx", true) 1928 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1929 .Default(false); 1930 } 1931 1932 ArrayRef<const char *> getGCCRegNames() const override; 1933 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1934 // No aliases. 1935 return None; 1936 } 1937 bool validateAsmConstraint(const char *&Name, 1938 TargetInfo::ConstraintInfo &Info) const override { 1939 switch (*Name) { 1940 default: 1941 return false; 1942 case 'c': 1943 case 'h': 1944 case 'r': 1945 case 'l': 1946 case 'f': 1947 case 'd': 1948 Info.setAllowsRegister(); 1949 return true; 1950 } 1951 } 1952 const char *getClobbers() const override { 1953 // FIXME: Is this really right? 1954 return ""; 1955 } 1956 BuiltinVaListKind getBuiltinVaListKind() const override { 1957 // FIXME: implement 1958 return TargetInfo::CharPtrBuiltinVaList; 1959 } 1960 bool setCPU(const std::string &Name) override { 1961 GPU = StringToCudaArch(Name); 1962 return GPU != CudaArch::UNKNOWN; 1963 } 1964 void setSupportedOpenCLOpts() override { 1965 auto &Opts = getSupportedOpenCLOpts(); 1966 Opts.support("cl_clang_storage_class_specifiers"); 1967 Opts.support("cl_khr_gl_sharing"); 1968 Opts.support("cl_khr_icd"); 1969 1970 Opts.support("cl_khr_fp64"); 1971 Opts.support("cl_khr_byte_addressable_store"); 1972 Opts.support("cl_khr_global_int32_base_atomics"); 1973 Opts.support("cl_khr_global_int32_extended_atomics"); 1974 Opts.support("cl_khr_local_int32_base_atomics"); 1975 Opts.support("cl_khr_local_int32_extended_atomics"); 1976 } 1977 1978 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 1979 // CUDA compilations support all of the host's calling conventions. 1980 // 1981 // TODO: We should warn if you apply a non-default CC to anything other than 1982 // a host function. 1983 if (HostTarget) 1984 return HostTarget->checkCallingConvention(CC); 1985 return CCCR_Warning; 1986 } 1987 }; 1988 1989 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1990 #define BUILTIN(ID, TYPE, ATTRS) \ 1991 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1992 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1993 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1994 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 1995 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 1996 #include "clang/Basic/BuiltinsNVPTX.def" 1997 }; 1998 1999 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 2000 2001 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 2002 return llvm::makeArrayRef(GCCRegNames); 2003 } 2004 2005 static const unsigned AMDGPUAddrSpaceMap[] = { 2006 1, // opencl_global 2007 3, // opencl_local 2008 2, // opencl_constant 2009 4, // opencl_generic 2010 1, // cuda_device 2011 2, // cuda_constant 2012 3 // cuda_shared 2013 }; 2014 2015 // If you edit the description strings, make sure you update 2016 // getPointerWidthV(). 2017 2018 static const char *const DataLayoutStringR600 = 2019 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2020 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2021 2022 static const char *const DataLayoutStringSI = 2023 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2024 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2025 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2026 2027 class AMDGPUTargetInfo final : public TargetInfo { 2028 static const Builtin::Info BuiltinInfo[]; 2029 static const char * const GCCRegNames[]; 2030 2031 /// \brief The GPU profiles supported by the AMDGPU target. 2032 enum GPUKind { 2033 GK_NONE, 2034 GK_R600, 2035 GK_R600_DOUBLE_OPS, 2036 GK_R700, 2037 GK_R700_DOUBLE_OPS, 2038 GK_EVERGREEN, 2039 GK_EVERGREEN_DOUBLE_OPS, 2040 GK_NORTHERN_ISLANDS, 2041 GK_CAYMAN, 2042 GK_GFX6, 2043 GK_GFX7, 2044 GK_GFX8, 2045 GK_GFX9 2046 } GPU; 2047 2048 bool hasFP64:1; 2049 bool hasFMAF:1; 2050 bool hasLDEXPF:1; 2051 bool hasFullSpeedFP32Denorms:1; 2052 2053 static bool isAMDGCN(const llvm::Triple &TT) { 2054 return TT.getArch() == llvm::Triple::amdgcn; 2055 } 2056 2057 public: 2058 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2059 : TargetInfo(Triple) , 2060 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2061 hasFP64(false), 2062 hasFMAF(false), 2063 hasLDEXPF(false), 2064 hasFullSpeedFP32Denorms(false){ 2065 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2066 hasFP64 = true; 2067 hasFMAF = true; 2068 hasLDEXPF = true; 2069 } 2070 2071 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2072 DataLayoutStringSI : DataLayoutStringR600); 2073 2074 AddrSpaceMap = &AMDGPUAddrSpaceMap; 2075 UseAddrSpaceMapMangling = true; 2076 } 2077 2078 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2079 if (GPU <= GK_CAYMAN) 2080 return 32; 2081 2082 switch(AddrSpace) { 2083 default: 2084 return 64; 2085 case 0: 2086 case 3: 2087 case 5: 2088 return 32; 2089 } 2090 } 2091 2092 uint64_t getMaxPointerWidth() const override { 2093 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2094 } 2095 2096 const char * getClobbers() const override { 2097 return ""; 2098 } 2099 2100 ArrayRef<const char *> getGCCRegNames() const override; 2101 2102 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2103 return None; 2104 } 2105 2106 bool validateAsmConstraint(const char *&Name, 2107 TargetInfo::ConstraintInfo &Info) const override { 2108 switch (*Name) { 2109 default: break; 2110 case 'v': // vgpr 2111 case 's': // sgpr 2112 Info.setAllowsRegister(); 2113 return true; 2114 } 2115 return false; 2116 } 2117 2118 bool initFeatureMap(llvm::StringMap<bool> &Features, 2119 DiagnosticsEngine &Diags, StringRef CPU, 2120 const std::vector<std::string> &FeatureVec) const override; 2121 2122 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2123 TargetOptions &TargetOpts) const override { 2124 bool hasFP32Denormals = false; 2125 bool hasFP64Denormals = false; 2126 for (auto &I : TargetOpts.FeaturesAsWritten) { 2127 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2128 hasFP32Denormals = true; 2129 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2130 hasFP64Denormals = true; 2131 } 2132 if (!hasFP32Denormals) 2133 TargetOpts.Features.push_back((Twine(hasFullSpeedFP32Denorms && 2134 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2135 // Always do not flush fp64 or fp16 denorms. 2136 if (!hasFP64Denormals && hasFP64) 2137 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2138 } 2139 2140 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2141 return llvm::makeArrayRef(BuiltinInfo, 2142 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2143 } 2144 2145 void getTargetDefines(const LangOptions &Opts, 2146 MacroBuilder &Builder) const override { 2147 if (getTriple().getArch() == llvm::Triple::amdgcn) 2148 Builder.defineMacro("__AMDGCN__"); 2149 else 2150 Builder.defineMacro("__R600__"); 2151 2152 if (hasFMAF) 2153 Builder.defineMacro("__HAS_FMAF__"); 2154 if (hasLDEXPF) 2155 Builder.defineMacro("__HAS_LDEXPF__"); 2156 if (hasFP64) 2157 Builder.defineMacro("__HAS_FP64__"); 2158 } 2159 2160 BuiltinVaListKind getBuiltinVaListKind() const override { 2161 return TargetInfo::CharPtrBuiltinVaList; 2162 } 2163 2164 static GPUKind parseR600Name(StringRef Name) { 2165 return llvm::StringSwitch<GPUKind>(Name) 2166 .Case("r600" , GK_R600) 2167 .Case("rv610", GK_R600) 2168 .Case("rv620", GK_R600) 2169 .Case("rv630", GK_R600) 2170 .Case("rv635", GK_R600) 2171 .Case("rs780", GK_R600) 2172 .Case("rs880", GK_R600) 2173 .Case("rv670", GK_R600_DOUBLE_OPS) 2174 .Case("rv710", GK_R700) 2175 .Case("rv730", GK_R700) 2176 .Case("rv740", GK_R700_DOUBLE_OPS) 2177 .Case("rv770", GK_R700_DOUBLE_OPS) 2178 .Case("palm", GK_EVERGREEN) 2179 .Case("cedar", GK_EVERGREEN) 2180 .Case("sumo", GK_EVERGREEN) 2181 .Case("sumo2", GK_EVERGREEN) 2182 .Case("redwood", GK_EVERGREEN) 2183 .Case("juniper", GK_EVERGREEN) 2184 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2185 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2186 .Case("barts", GK_NORTHERN_ISLANDS) 2187 .Case("turks", GK_NORTHERN_ISLANDS) 2188 .Case("caicos", GK_NORTHERN_ISLANDS) 2189 .Case("cayman", GK_CAYMAN) 2190 .Case("aruba", GK_CAYMAN) 2191 .Default(GK_NONE); 2192 } 2193 2194 static GPUKind parseAMDGCNName(StringRef Name) { 2195 return llvm::StringSwitch<GPUKind>(Name) 2196 .Case("tahiti", GK_GFX6) 2197 .Case("pitcairn", GK_GFX6) 2198 .Case("verde", GK_GFX6) 2199 .Case("oland", GK_GFX6) 2200 .Case("hainan", GK_GFX6) 2201 .Case("bonaire", GK_GFX7) 2202 .Case("kabini", GK_GFX7) 2203 .Case("kaveri", GK_GFX7) 2204 .Case("hawaii", GK_GFX7) 2205 .Case("mullins", GK_GFX7) 2206 .Case("gfx700", GK_GFX7) 2207 .Case("gfx701", GK_GFX7) 2208 .Case("gfx702", GK_GFX7) 2209 .Case("tonga", GK_GFX8) 2210 .Case("iceland", GK_GFX8) 2211 .Case("carrizo", GK_GFX8) 2212 .Case("fiji", GK_GFX8) 2213 .Case("stoney", GK_GFX8) 2214 .Case("polaris10", GK_GFX8) 2215 .Case("polaris11", GK_GFX8) 2216 .Case("gfx800", GK_GFX8) 2217 .Case("gfx801", GK_GFX8) 2218 .Case("gfx802", GK_GFX8) 2219 .Case("gfx803", GK_GFX8) 2220 .Case("gfx804", GK_GFX8) 2221 .Case("gfx810", GK_GFX8) 2222 .Case("gfx900", GK_GFX9) 2223 .Case("gfx901", GK_GFX9) 2224 .Default(GK_NONE); 2225 } 2226 2227 bool setCPU(const std::string &Name) override { 2228 if (getTriple().getArch() == llvm::Triple::amdgcn) 2229 GPU = parseAMDGCNName(Name); 2230 else 2231 GPU = parseR600Name(Name); 2232 2233 return GPU != GK_NONE; 2234 } 2235 2236 void setSupportedOpenCLOpts() override { 2237 auto &Opts = getSupportedOpenCLOpts(); 2238 Opts.support("cl_clang_storage_class_specifiers"); 2239 Opts.support("cl_khr_icd"); 2240 2241 if (hasFP64) 2242 Opts.support("cl_khr_fp64"); 2243 if (GPU >= GK_EVERGREEN) { 2244 Opts.support("cl_khr_byte_addressable_store"); 2245 Opts.support("cl_khr_global_int32_base_atomics"); 2246 Opts.support("cl_khr_global_int32_extended_atomics"); 2247 Opts.support("cl_khr_local_int32_base_atomics"); 2248 Opts.support("cl_khr_local_int32_extended_atomics"); 2249 } 2250 if (GPU >= GK_GFX6) { 2251 Opts.support("cl_khr_fp16"); 2252 Opts.support("cl_khr_int64_base_atomics"); 2253 Opts.support("cl_khr_int64_extended_atomics"); 2254 Opts.support("cl_khr_mipmap_image"); 2255 Opts.support("cl_khr_subgroups"); 2256 Opts.support("cl_khr_3d_image_writes"); 2257 Opts.support("cl_amd_media_ops"); 2258 Opts.support("cl_amd_media_ops2"); 2259 } 2260 } 2261 2262 LangAS::ID getOpenCLImageAddrSpace() const override { 2263 return LangAS::opencl_constant; 2264 } 2265 2266 /// \returns Target specific vtbl ptr address space. 2267 unsigned getVtblPtrAddressSpace() const override { 2268 // \todo: We currently have address spaces defined in AMDGPU Backend. It 2269 // would be nice if we could use it here instead of using bare numbers (same 2270 // applies to getDWARFAddressSpace). 2271 return 2; // constant. 2272 } 2273 2274 /// \returns If a target requires an address within a target specific address 2275 /// space \p AddressSpace to be converted in order to be used, then return the 2276 /// corresponding target specific DWARF address space. 2277 /// 2278 /// \returns Otherwise return None and no conversion will be emitted in the 2279 /// DWARF. 2280 Optional<unsigned> getDWARFAddressSpace( 2281 unsigned AddressSpace) const override { 2282 switch (AddressSpace) { 2283 case 0: // LLVM Private. 2284 return 1; // DWARF Private. 2285 case 3: // LLVM Local. 2286 return 2; // DWARF Local. 2287 default: 2288 return None; 2289 } 2290 } 2291 2292 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2293 switch (CC) { 2294 default: 2295 return CCCR_Warning; 2296 case CC_C: 2297 case CC_OpenCLKernel: 2298 return CCCR_OK; 2299 } 2300 } 2301 2302 // In amdgcn target the null pointer in global, constant, and generic 2303 // address space has value 0 but in private and local address space has 2304 // value ~0. 2305 uint64_t getNullPointerValue(unsigned AS) const override { 2306 return AS == LangAS::opencl_local ? ~0 : 0; 2307 } 2308 }; 2309 2310 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2311 #define BUILTIN(ID, TYPE, ATTRS) \ 2312 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2313 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2314 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2315 #include "clang/Basic/BuiltinsAMDGPU.def" 2316 }; 2317 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2318 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2319 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2320 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2321 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2322 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2323 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2324 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2325 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2326 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2327 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2328 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2329 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2330 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2331 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2332 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2333 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2334 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2335 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2336 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2337 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2338 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2339 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2340 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2341 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2342 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2343 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2344 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2345 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2346 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2347 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2348 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2349 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2350 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2351 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2352 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2353 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2354 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2355 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2356 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2357 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2358 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2359 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2360 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2361 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2362 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2363 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2364 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2365 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2366 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2367 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2368 }; 2369 2370 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2371 return llvm::makeArrayRef(GCCRegNames); 2372 } 2373 2374 bool AMDGPUTargetInfo::initFeatureMap( 2375 llvm::StringMap<bool> &Features, 2376 DiagnosticsEngine &Diags, StringRef CPU, 2377 const std::vector<std::string> &FeatureVec) const { 2378 2379 // XXX - What does the member GPU mean if device name string passed here? 2380 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2381 if (CPU.empty()) 2382 CPU = "tahiti"; 2383 2384 switch (parseAMDGCNName(CPU)) { 2385 case GK_GFX6: 2386 case GK_GFX7: 2387 break; 2388 2389 case GK_GFX9: 2390 Features["gfx9-insts"] = true; 2391 LLVM_FALLTHROUGH; 2392 case GK_GFX8: 2393 Features["s-memrealtime"] = true; 2394 Features["16-bit-insts"] = true; 2395 Features["dpp"] = true; 2396 break; 2397 2398 case GK_NONE: 2399 return false; 2400 default: 2401 llvm_unreachable("unhandled subtarget"); 2402 } 2403 } else { 2404 if (CPU.empty()) 2405 CPU = "r600"; 2406 2407 switch (parseR600Name(CPU)) { 2408 case GK_R600: 2409 case GK_R700: 2410 case GK_EVERGREEN: 2411 case GK_NORTHERN_ISLANDS: 2412 break; 2413 case GK_R600_DOUBLE_OPS: 2414 case GK_R700_DOUBLE_OPS: 2415 case GK_EVERGREEN_DOUBLE_OPS: 2416 case GK_CAYMAN: 2417 Features["fp64"] = true; 2418 break; 2419 case GK_NONE: 2420 return false; 2421 default: 2422 llvm_unreachable("unhandled subtarget"); 2423 } 2424 } 2425 2426 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2427 } 2428 2429 const Builtin::Info BuiltinInfoX86[] = { 2430 #define BUILTIN(ID, TYPE, ATTRS) \ 2431 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2432 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2433 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2434 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2435 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2436 #include "clang/Basic/BuiltinsX86.def" 2437 2438 #define BUILTIN(ID, TYPE, ATTRS) \ 2439 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2440 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2441 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2442 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2443 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2444 #include "clang/Basic/BuiltinsX86_64.def" 2445 }; 2446 2447 2448 static const char* const GCCRegNames[] = { 2449 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2450 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2451 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2452 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2453 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2454 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2455 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2456 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2457 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2458 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2459 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2460 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2461 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2462 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2463 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2464 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2465 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2466 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2467 }; 2468 2469 const TargetInfo::AddlRegName AddlRegNames[] = { 2470 { { "al", "ah", "eax", "rax" }, 0 }, 2471 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2472 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2473 { { "dl", "dh", "edx", "rdx" }, 1 }, 2474 { { "esi", "rsi" }, 4 }, 2475 { { "edi", "rdi" }, 5 }, 2476 { { "esp", "rsp" }, 7 }, 2477 { { "ebp", "rbp" }, 6 }, 2478 { { "r8d", "r8w", "r8b" }, 38 }, 2479 { { "r9d", "r9w", "r9b" }, 39 }, 2480 { { "r10d", "r10w", "r10b" }, 40 }, 2481 { { "r11d", "r11w", "r11b" }, 41 }, 2482 { { "r12d", "r12w", "r12b" }, 42 }, 2483 { { "r13d", "r13w", "r13b" }, 43 }, 2484 { { "r14d", "r14w", "r14b" }, 44 }, 2485 { { "r15d", "r15w", "r15b" }, 45 }, 2486 }; 2487 2488 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2489 // most of the implementation can be shared. 2490 class X86TargetInfo : public TargetInfo { 2491 enum X86SSEEnum { 2492 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2493 } SSELevel = NoSSE; 2494 enum MMX3DNowEnum { 2495 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2496 } MMX3DNowLevel = NoMMX3DNow; 2497 enum XOPEnum { 2498 NoXOP, 2499 SSE4A, 2500 FMA4, 2501 XOP 2502 } XOPLevel = NoXOP; 2503 2504 bool HasAES = false; 2505 bool HasPCLMUL = false; 2506 bool HasLZCNT = false; 2507 bool HasRDRND = false; 2508 bool HasFSGSBASE = false; 2509 bool HasBMI = false; 2510 bool HasBMI2 = false; 2511 bool HasPOPCNT = false; 2512 bool HasRTM = false; 2513 bool HasPRFCHW = false; 2514 bool HasRDSEED = false; 2515 bool HasADX = false; 2516 bool HasTBM = false; 2517 bool HasFMA = false; 2518 bool HasF16C = false; 2519 bool HasAVX512CD = false; 2520 bool HasAVX512ER = false; 2521 bool HasAVX512PF = false; 2522 bool HasAVX512DQ = false; 2523 bool HasAVX512BW = false; 2524 bool HasAVX512VL = false; 2525 bool HasAVX512VBMI = false; 2526 bool HasAVX512IFMA = false; 2527 bool HasSHA = false; 2528 bool HasMPX = false; 2529 bool HasSGX = false; 2530 bool HasCX16 = false; 2531 bool HasFXSR = false; 2532 bool HasXSAVE = false; 2533 bool HasXSAVEOPT = false; 2534 bool HasXSAVEC = false; 2535 bool HasXSAVES = false; 2536 bool HasMWAITX = false; 2537 bool HasCLZERO = false; 2538 bool HasPKU = false; 2539 bool HasCLFLUSHOPT = false; 2540 bool HasCLWB = false; 2541 bool HasMOVBE = false; 2542 bool HasPREFETCHWT1 = false; 2543 2544 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2545 /// 2546 /// Each enumeration represents a particular CPU supported by Clang. These 2547 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2548 enum CPUKind { 2549 CK_Generic, 2550 2551 /// \name i386 2552 /// i386-generation processors. 2553 //@{ 2554 CK_i386, 2555 //@} 2556 2557 /// \name i486 2558 /// i486-generation processors. 2559 //@{ 2560 CK_i486, 2561 CK_WinChipC6, 2562 CK_WinChip2, 2563 CK_C3, 2564 //@} 2565 2566 /// \name i586 2567 /// i586-generation processors, P5 microarchitecture based. 2568 //@{ 2569 CK_i586, 2570 CK_Pentium, 2571 CK_PentiumMMX, 2572 //@} 2573 2574 /// \name i686 2575 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2576 //@{ 2577 CK_i686, 2578 CK_PentiumPro, 2579 CK_Pentium2, 2580 CK_Pentium3, 2581 CK_Pentium3M, 2582 CK_PentiumM, 2583 CK_C3_2, 2584 2585 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2586 /// Clang however has some logic to suport this. 2587 // FIXME: Warn, deprecate, and potentially remove this. 2588 CK_Yonah, 2589 //@} 2590 2591 /// \name Netburst 2592 /// Netburst microarchitecture based processors. 2593 //@{ 2594 CK_Pentium4, 2595 CK_Pentium4M, 2596 CK_Prescott, 2597 CK_Nocona, 2598 //@} 2599 2600 /// \name Core 2601 /// Core microarchitecture based processors. 2602 //@{ 2603 CK_Core2, 2604 2605 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2606 /// codename which GCC no longer accepts as an option to -march, but Clang 2607 /// has some logic for recognizing it. 2608 // FIXME: Warn, deprecate, and potentially remove this. 2609 CK_Penryn, 2610 //@} 2611 2612 /// \name Atom 2613 /// Atom processors 2614 //@{ 2615 CK_Bonnell, 2616 CK_Silvermont, 2617 //@} 2618 2619 /// \name Nehalem 2620 /// Nehalem microarchitecture based processors. 2621 CK_Nehalem, 2622 2623 /// \name Westmere 2624 /// Westmere microarchitecture based processors. 2625 CK_Westmere, 2626 2627 /// \name Sandy Bridge 2628 /// Sandy Bridge microarchitecture based processors. 2629 CK_SandyBridge, 2630 2631 /// \name Ivy Bridge 2632 /// Ivy Bridge microarchitecture based processors. 2633 CK_IvyBridge, 2634 2635 /// \name Haswell 2636 /// Haswell microarchitecture based processors. 2637 CK_Haswell, 2638 2639 /// \name Broadwell 2640 /// Broadwell microarchitecture based processors. 2641 CK_Broadwell, 2642 2643 /// \name Skylake Client 2644 /// Skylake client microarchitecture based processors. 2645 CK_SkylakeClient, 2646 2647 /// \name Skylake Server 2648 /// Skylake server microarchitecture based processors. 2649 CK_SkylakeServer, 2650 2651 /// \name Cannonlake Client 2652 /// Cannonlake client microarchitecture based processors. 2653 CK_Cannonlake, 2654 2655 /// \name Knights Landing 2656 /// Knights Landing processor. 2657 CK_KNL, 2658 2659 /// \name Lakemont 2660 /// Lakemont microarchitecture based processors. 2661 CK_Lakemont, 2662 2663 /// \name K6 2664 /// K6 architecture processors. 2665 //@{ 2666 CK_K6, 2667 CK_K6_2, 2668 CK_K6_3, 2669 //@} 2670 2671 /// \name K7 2672 /// K7 architecture processors. 2673 //@{ 2674 CK_Athlon, 2675 CK_AthlonThunderbird, 2676 CK_Athlon4, 2677 CK_AthlonXP, 2678 CK_AthlonMP, 2679 //@} 2680 2681 /// \name K8 2682 /// K8 architecture processors. 2683 //@{ 2684 CK_Athlon64, 2685 CK_Athlon64SSE3, 2686 CK_AthlonFX, 2687 CK_K8, 2688 CK_K8SSE3, 2689 CK_Opteron, 2690 CK_OpteronSSE3, 2691 CK_AMDFAM10, 2692 //@} 2693 2694 /// \name Bobcat 2695 /// Bobcat architecture processors. 2696 //@{ 2697 CK_BTVER1, 2698 CK_BTVER2, 2699 //@} 2700 2701 /// \name Bulldozer 2702 /// Bulldozer architecture processors. 2703 //@{ 2704 CK_BDVER1, 2705 CK_BDVER2, 2706 CK_BDVER3, 2707 CK_BDVER4, 2708 //@} 2709 2710 /// \name zen 2711 /// Zen architecture processors. 2712 //@{ 2713 CK_ZNVER1, 2714 //@} 2715 2716 /// This specification is deprecated and will be removed in the future. 2717 /// Users should prefer \see CK_K8. 2718 // FIXME: Warn on this when the CPU is set to it. 2719 //@{ 2720 CK_x86_64, 2721 //@} 2722 2723 /// \name Geode 2724 /// Geode processors. 2725 //@{ 2726 CK_Geode 2727 //@} 2728 } CPU = CK_Generic; 2729 2730 CPUKind getCPUKind(StringRef CPU) const { 2731 return llvm::StringSwitch<CPUKind>(CPU) 2732 .Case("i386", CK_i386) 2733 .Case("i486", CK_i486) 2734 .Case("winchip-c6", CK_WinChipC6) 2735 .Case("winchip2", CK_WinChip2) 2736 .Case("c3", CK_C3) 2737 .Case("i586", CK_i586) 2738 .Case("pentium", CK_Pentium) 2739 .Case("pentium-mmx", CK_PentiumMMX) 2740 .Case("i686", CK_i686) 2741 .Case("pentiumpro", CK_PentiumPro) 2742 .Case("pentium2", CK_Pentium2) 2743 .Case("pentium3", CK_Pentium3) 2744 .Case("pentium3m", CK_Pentium3M) 2745 .Case("pentium-m", CK_PentiumM) 2746 .Case("c3-2", CK_C3_2) 2747 .Case("yonah", CK_Yonah) 2748 .Case("pentium4", CK_Pentium4) 2749 .Case("pentium4m", CK_Pentium4M) 2750 .Case("prescott", CK_Prescott) 2751 .Case("nocona", CK_Nocona) 2752 .Case("core2", CK_Core2) 2753 .Case("penryn", CK_Penryn) 2754 .Case("bonnell", CK_Bonnell) 2755 .Case("atom", CK_Bonnell) // Legacy name. 2756 .Case("silvermont", CK_Silvermont) 2757 .Case("slm", CK_Silvermont) // Legacy name. 2758 .Case("nehalem", CK_Nehalem) 2759 .Case("corei7", CK_Nehalem) // Legacy name. 2760 .Case("westmere", CK_Westmere) 2761 .Case("sandybridge", CK_SandyBridge) 2762 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2763 .Case("ivybridge", CK_IvyBridge) 2764 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2765 .Case("haswell", CK_Haswell) 2766 .Case("core-avx2", CK_Haswell) // Legacy name. 2767 .Case("broadwell", CK_Broadwell) 2768 .Case("skylake", CK_SkylakeClient) 2769 .Case("skylake-avx512", CK_SkylakeServer) 2770 .Case("skx", CK_SkylakeServer) // Legacy name. 2771 .Case("cannonlake", CK_Cannonlake) 2772 .Case("knl", CK_KNL) 2773 .Case("lakemont", CK_Lakemont) 2774 .Case("k6", CK_K6) 2775 .Case("k6-2", CK_K6_2) 2776 .Case("k6-3", CK_K6_3) 2777 .Case("athlon", CK_Athlon) 2778 .Case("athlon-tbird", CK_AthlonThunderbird) 2779 .Case("athlon-4", CK_Athlon4) 2780 .Case("athlon-xp", CK_AthlonXP) 2781 .Case("athlon-mp", CK_AthlonMP) 2782 .Case("athlon64", CK_Athlon64) 2783 .Case("athlon64-sse3", CK_Athlon64SSE3) 2784 .Case("athlon-fx", CK_AthlonFX) 2785 .Case("k8", CK_K8) 2786 .Case("k8-sse3", CK_K8SSE3) 2787 .Case("opteron", CK_Opteron) 2788 .Case("opteron-sse3", CK_OpteronSSE3) 2789 .Case("barcelona", CK_AMDFAM10) 2790 .Case("amdfam10", CK_AMDFAM10) 2791 .Case("btver1", CK_BTVER1) 2792 .Case("btver2", CK_BTVER2) 2793 .Case("bdver1", CK_BDVER1) 2794 .Case("bdver2", CK_BDVER2) 2795 .Case("bdver3", CK_BDVER3) 2796 .Case("bdver4", CK_BDVER4) 2797 .Case("znver1", CK_ZNVER1) 2798 .Case("x86-64", CK_x86_64) 2799 .Case("geode", CK_Geode) 2800 .Default(CK_Generic); 2801 } 2802 2803 enum FPMathKind { 2804 FP_Default, 2805 FP_SSE, 2806 FP_387 2807 } FPMath = FP_Default; 2808 2809 public: 2810 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2811 : TargetInfo(Triple) { 2812 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2813 } 2814 unsigned getFloatEvalMethod() const override { 2815 // X87 evaluates with 80 bits "long double" precision. 2816 return SSELevel == NoSSE ? 2 : 0; 2817 } 2818 ArrayRef<const char *> getGCCRegNames() const override { 2819 return llvm::makeArrayRef(GCCRegNames); 2820 } 2821 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2822 return None; 2823 } 2824 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2825 return llvm::makeArrayRef(AddlRegNames); 2826 } 2827 bool validateCpuSupports(StringRef Name) const override; 2828 bool validateAsmConstraint(const char *&Name, 2829 TargetInfo::ConstraintInfo &info) const override; 2830 2831 bool validateGlobalRegisterVariable(StringRef RegName, 2832 unsigned RegSize, 2833 bool &HasSizeMismatch) const override { 2834 // esp and ebp are the only 32-bit registers the x86 backend can currently 2835 // handle. 2836 if (RegName.equals("esp") || RegName.equals("ebp")) { 2837 // Check that the register size is 32-bit. 2838 HasSizeMismatch = RegSize != 32; 2839 return true; 2840 } 2841 2842 return false; 2843 } 2844 2845 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2846 2847 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2848 2849 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2850 2851 std::string convertConstraint(const char *&Constraint) const override; 2852 const char *getClobbers() const override { 2853 return "~{dirflag},~{fpsr},~{flags}"; 2854 } 2855 2856 StringRef getConstraintRegister(const StringRef &Constraint, 2857 const StringRef &Expression) const override { 2858 StringRef::iterator I, E; 2859 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 2860 if (isalpha(*I)) 2861 break; 2862 } 2863 if (I == E) 2864 return ""; 2865 switch (*I) { 2866 // For the register constraints, return the matching register name 2867 case 'a': 2868 return "ax"; 2869 case 'b': 2870 return "bx"; 2871 case 'c': 2872 return "cx"; 2873 case 'd': 2874 return "dx"; 2875 case 'S': 2876 return "si"; 2877 case 'D': 2878 return "di"; 2879 // In case the constraint is 'r' we need to return Expression 2880 case 'r': 2881 return Expression; 2882 default: 2883 // Default value if there is no constraint for the register 2884 return ""; 2885 } 2886 return ""; 2887 } 2888 2889 void getTargetDefines(const LangOptions &Opts, 2890 MacroBuilder &Builder) const override; 2891 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2892 bool Enabled); 2893 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2894 bool Enabled); 2895 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2896 bool Enabled); 2897 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2898 StringRef Name, bool Enabled) const override { 2899 setFeatureEnabledImpl(Features, Name, Enabled); 2900 } 2901 // This exists purely to cut down on the number of virtual calls in 2902 // initFeatureMap which calls this repeatedly. 2903 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2904 StringRef Name, bool Enabled); 2905 bool 2906 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2907 StringRef CPU, 2908 const std::vector<std::string> &FeaturesVec) const override; 2909 bool hasFeature(StringRef Feature) const override; 2910 bool handleTargetFeatures(std::vector<std::string> &Features, 2911 DiagnosticsEngine &Diags) override; 2912 StringRef getABI() const override { 2913 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2914 return "avx512"; 2915 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2916 return "avx"; 2917 if (getTriple().getArch() == llvm::Triple::x86 && 2918 MMX3DNowLevel == NoMMX3DNow) 2919 return "no-mmx"; 2920 return ""; 2921 } 2922 bool setCPU(const std::string &Name) override { 2923 CPU = getCPUKind(Name); 2924 2925 // Perform any per-CPU checks necessary to determine if this CPU is 2926 // acceptable. 2927 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2928 // invalid without explaining *why*. 2929 switch (CPU) { 2930 case CK_Generic: 2931 // No processor selected! 2932 return false; 2933 2934 case CK_i386: 2935 case CK_i486: 2936 case CK_WinChipC6: 2937 case CK_WinChip2: 2938 case CK_C3: 2939 case CK_i586: 2940 case CK_Pentium: 2941 case CK_PentiumMMX: 2942 case CK_i686: 2943 case CK_PentiumPro: 2944 case CK_Pentium2: 2945 case CK_Pentium3: 2946 case CK_Pentium3M: 2947 case CK_PentiumM: 2948 case CK_Yonah: 2949 case CK_C3_2: 2950 case CK_Pentium4: 2951 case CK_Pentium4M: 2952 case CK_Lakemont: 2953 case CK_Prescott: 2954 case CK_K6: 2955 case CK_K6_2: 2956 case CK_K6_3: 2957 case CK_Athlon: 2958 case CK_AthlonThunderbird: 2959 case CK_Athlon4: 2960 case CK_AthlonXP: 2961 case CK_AthlonMP: 2962 case CK_Geode: 2963 // Only accept certain architectures when compiling in 32-bit mode. 2964 if (getTriple().getArch() != llvm::Triple::x86) 2965 return false; 2966 2967 // Fallthrough 2968 case CK_Nocona: 2969 case CK_Core2: 2970 case CK_Penryn: 2971 case CK_Bonnell: 2972 case CK_Silvermont: 2973 case CK_Nehalem: 2974 case CK_Westmere: 2975 case CK_SandyBridge: 2976 case CK_IvyBridge: 2977 case CK_Haswell: 2978 case CK_Broadwell: 2979 case CK_SkylakeClient: 2980 case CK_SkylakeServer: 2981 case CK_Cannonlake: 2982 case CK_KNL: 2983 case CK_Athlon64: 2984 case CK_Athlon64SSE3: 2985 case CK_AthlonFX: 2986 case CK_K8: 2987 case CK_K8SSE3: 2988 case CK_Opteron: 2989 case CK_OpteronSSE3: 2990 case CK_AMDFAM10: 2991 case CK_BTVER1: 2992 case CK_BTVER2: 2993 case CK_BDVER1: 2994 case CK_BDVER2: 2995 case CK_BDVER3: 2996 case CK_BDVER4: 2997 case CK_ZNVER1: 2998 case CK_x86_64: 2999 return true; 3000 } 3001 llvm_unreachable("Unhandled CPU kind"); 3002 } 3003 3004 bool setFPMath(StringRef Name) override; 3005 3006 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3007 // Most of the non-ARM calling conventions are i386 conventions. 3008 switch (CC) { 3009 case CC_X86ThisCall: 3010 case CC_X86FastCall: 3011 case CC_X86StdCall: 3012 case CC_X86VectorCall: 3013 case CC_X86RegCall: 3014 case CC_C: 3015 case CC_Swift: 3016 case CC_X86Pascal: 3017 case CC_IntelOclBicc: 3018 return CCCR_OK; 3019 default: 3020 return CCCR_Warning; 3021 } 3022 } 3023 3024 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3025 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 3026 } 3027 3028 bool hasSjLjLowering() const override { 3029 return true; 3030 } 3031 3032 void setSupportedOpenCLOpts() override { 3033 getSupportedOpenCLOpts().supportAll(); 3034 } 3035 }; 3036 3037 bool X86TargetInfo::setFPMath(StringRef Name) { 3038 if (Name == "387") { 3039 FPMath = FP_387; 3040 return true; 3041 } 3042 if (Name == "sse") { 3043 FPMath = FP_SSE; 3044 return true; 3045 } 3046 return false; 3047 } 3048 3049 bool X86TargetInfo::initFeatureMap( 3050 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3051 const std::vector<std::string> &FeaturesVec) const { 3052 // FIXME: This *really* should not be here. 3053 // X86_64 always has SSE2. 3054 if (getTriple().getArch() == llvm::Triple::x86_64) 3055 setFeatureEnabledImpl(Features, "sse2", true); 3056 3057 const CPUKind Kind = getCPUKind(CPU); 3058 3059 // Enable X87 for all X86 processors but Lakemont. 3060 if (Kind != CK_Lakemont) 3061 setFeatureEnabledImpl(Features, "x87", true); 3062 3063 switch (Kind) { 3064 case CK_Generic: 3065 case CK_i386: 3066 case CK_i486: 3067 case CK_i586: 3068 case CK_Pentium: 3069 case CK_i686: 3070 case CK_PentiumPro: 3071 case CK_Lakemont: 3072 break; 3073 case CK_PentiumMMX: 3074 case CK_Pentium2: 3075 case CK_K6: 3076 case CK_WinChipC6: 3077 setFeatureEnabledImpl(Features, "mmx", true); 3078 break; 3079 case CK_Pentium3: 3080 case CK_Pentium3M: 3081 case CK_C3_2: 3082 setFeatureEnabledImpl(Features, "sse", true); 3083 setFeatureEnabledImpl(Features, "fxsr", true); 3084 break; 3085 case CK_PentiumM: 3086 case CK_Pentium4: 3087 case CK_Pentium4M: 3088 case CK_x86_64: 3089 setFeatureEnabledImpl(Features, "sse2", true); 3090 setFeatureEnabledImpl(Features, "fxsr", true); 3091 break; 3092 case CK_Yonah: 3093 case CK_Prescott: 3094 case CK_Nocona: 3095 setFeatureEnabledImpl(Features, "sse3", true); 3096 setFeatureEnabledImpl(Features, "fxsr", true); 3097 setFeatureEnabledImpl(Features, "cx16", true); 3098 break; 3099 case CK_Core2: 3100 case CK_Bonnell: 3101 setFeatureEnabledImpl(Features, "ssse3", true); 3102 setFeatureEnabledImpl(Features, "fxsr", true); 3103 setFeatureEnabledImpl(Features, "cx16", true); 3104 break; 3105 case CK_Penryn: 3106 setFeatureEnabledImpl(Features, "sse4.1", true); 3107 setFeatureEnabledImpl(Features, "fxsr", true); 3108 setFeatureEnabledImpl(Features, "cx16", true); 3109 break; 3110 case CK_Cannonlake: 3111 setFeatureEnabledImpl(Features, "avx512ifma", true); 3112 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3113 setFeatureEnabledImpl(Features, "sha", true); 3114 LLVM_FALLTHROUGH; 3115 case CK_SkylakeServer: 3116 setFeatureEnabledImpl(Features, "avx512f", true); 3117 setFeatureEnabledImpl(Features, "avx512cd", true); 3118 setFeatureEnabledImpl(Features, "avx512dq", true); 3119 setFeatureEnabledImpl(Features, "avx512bw", true); 3120 setFeatureEnabledImpl(Features, "avx512vl", true); 3121 setFeatureEnabledImpl(Features, "pku", true); 3122 setFeatureEnabledImpl(Features, "clwb", true); 3123 LLVM_FALLTHROUGH; 3124 case CK_SkylakeClient: 3125 setFeatureEnabledImpl(Features, "xsavec", true); 3126 setFeatureEnabledImpl(Features, "xsaves", true); 3127 setFeatureEnabledImpl(Features, "mpx", true); 3128 setFeatureEnabledImpl(Features, "sgx", true); 3129 setFeatureEnabledImpl(Features, "clflushopt", true); 3130 LLVM_FALLTHROUGH; 3131 case CK_Broadwell: 3132 setFeatureEnabledImpl(Features, "rdseed", true); 3133 setFeatureEnabledImpl(Features, "adx", true); 3134 LLVM_FALLTHROUGH; 3135 case CK_Haswell: 3136 setFeatureEnabledImpl(Features, "avx2", true); 3137 setFeatureEnabledImpl(Features, "lzcnt", true); 3138 setFeatureEnabledImpl(Features, "bmi", true); 3139 setFeatureEnabledImpl(Features, "bmi2", true); 3140 setFeatureEnabledImpl(Features, "rtm", true); 3141 setFeatureEnabledImpl(Features, "fma", true); 3142 setFeatureEnabledImpl(Features, "movbe", true); 3143 LLVM_FALLTHROUGH; 3144 case CK_IvyBridge: 3145 setFeatureEnabledImpl(Features, "rdrnd", true); 3146 setFeatureEnabledImpl(Features, "f16c", true); 3147 setFeatureEnabledImpl(Features, "fsgsbase", true); 3148 LLVM_FALLTHROUGH; 3149 case CK_SandyBridge: 3150 setFeatureEnabledImpl(Features, "avx", true); 3151 setFeatureEnabledImpl(Features, "xsave", true); 3152 setFeatureEnabledImpl(Features, "xsaveopt", true); 3153 LLVM_FALLTHROUGH; 3154 case CK_Westmere: 3155 case CK_Silvermont: 3156 setFeatureEnabledImpl(Features, "aes", true); 3157 setFeatureEnabledImpl(Features, "pclmul", true); 3158 LLVM_FALLTHROUGH; 3159 case CK_Nehalem: 3160 setFeatureEnabledImpl(Features, "sse4.2", true); 3161 setFeatureEnabledImpl(Features, "fxsr", true); 3162 setFeatureEnabledImpl(Features, "cx16", true); 3163 break; 3164 case CK_KNL: 3165 setFeatureEnabledImpl(Features, "avx512f", true); 3166 setFeatureEnabledImpl(Features, "avx512cd", true); 3167 setFeatureEnabledImpl(Features, "avx512er", true); 3168 setFeatureEnabledImpl(Features, "avx512pf", true); 3169 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3170 setFeatureEnabledImpl(Features, "fxsr", true); 3171 setFeatureEnabledImpl(Features, "rdseed", true); 3172 setFeatureEnabledImpl(Features, "adx", true); 3173 setFeatureEnabledImpl(Features, "lzcnt", true); 3174 setFeatureEnabledImpl(Features, "bmi", true); 3175 setFeatureEnabledImpl(Features, "bmi2", true); 3176 setFeatureEnabledImpl(Features, "rtm", true); 3177 setFeatureEnabledImpl(Features, "fma", true); 3178 setFeatureEnabledImpl(Features, "rdrnd", true); 3179 setFeatureEnabledImpl(Features, "f16c", true); 3180 setFeatureEnabledImpl(Features, "fsgsbase", true); 3181 setFeatureEnabledImpl(Features, "aes", true); 3182 setFeatureEnabledImpl(Features, "pclmul", true); 3183 setFeatureEnabledImpl(Features, "cx16", true); 3184 setFeatureEnabledImpl(Features, "xsaveopt", true); 3185 setFeatureEnabledImpl(Features, "xsave", true); 3186 setFeatureEnabledImpl(Features, "movbe", true); 3187 break; 3188 case CK_K6_2: 3189 case CK_K6_3: 3190 case CK_WinChip2: 3191 case CK_C3: 3192 setFeatureEnabledImpl(Features, "3dnow", true); 3193 break; 3194 case CK_Athlon: 3195 case CK_AthlonThunderbird: 3196 case CK_Geode: 3197 setFeatureEnabledImpl(Features, "3dnowa", true); 3198 break; 3199 case CK_Athlon4: 3200 case CK_AthlonXP: 3201 case CK_AthlonMP: 3202 setFeatureEnabledImpl(Features, "sse", true); 3203 setFeatureEnabledImpl(Features, "3dnowa", true); 3204 setFeatureEnabledImpl(Features, "fxsr", true); 3205 break; 3206 case CK_K8: 3207 case CK_Opteron: 3208 case CK_Athlon64: 3209 case CK_AthlonFX: 3210 setFeatureEnabledImpl(Features, "sse2", true); 3211 setFeatureEnabledImpl(Features, "3dnowa", true); 3212 setFeatureEnabledImpl(Features, "fxsr", true); 3213 break; 3214 case CK_AMDFAM10: 3215 setFeatureEnabledImpl(Features, "sse4a", true); 3216 setFeatureEnabledImpl(Features, "lzcnt", true); 3217 setFeatureEnabledImpl(Features, "popcnt", true); 3218 LLVM_FALLTHROUGH; 3219 case CK_K8SSE3: 3220 case CK_OpteronSSE3: 3221 case CK_Athlon64SSE3: 3222 setFeatureEnabledImpl(Features, "sse3", true); 3223 setFeatureEnabledImpl(Features, "3dnowa", true); 3224 setFeatureEnabledImpl(Features, "fxsr", true); 3225 break; 3226 case CK_BTVER2: 3227 setFeatureEnabledImpl(Features, "avx", true); 3228 setFeatureEnabledImpl(Features, "aes", true); 3229 setFeatureEnabledImpl(Features, "pclmul", true); 3230 setFeatureEnabledImpl(Features, "bmi", true); 3231 setFeatureEnabledImpl(Features, "f16c", true); 3232 setFeatureEnabledImpl(Features, "xsaveopt", true); 3233 LLVM_FALLTHROUGH; 3234 case CK_BTVER1: 3235 setFeatureEnabledImpl(Features, "ssse3", true); 3236 setFeatureEnabledImpl(Features, "sse4a", true); 3237 setFeatureEnabledImpl(Features, "lzcnt", true); 3238 setFeatureEnabledImpl(Features, "popcnt", true); 3239 setFeatureEnabledImpl(Features, "prfchw", true); 3240 setFeatureEnabledImpl(Features, "cx16", true); 3241 setFeatureEnabledImpl(Features, "fxsr", true); 3242 break; 3243 case CK_ZNVER1: 3244 setFeatureEnabledImpl(Features, "adx", true); 3245 setFeatureEnabledImpl(Features, "aes", true); 3246 setFeatureEnabledImpl(Features, "avx2", true); 3247 setFeatureEnabledImpl(Features, "bmi", true); 3248 setFeatureEnabledImpl(Features, "bmi2", true); 3249 setFeatureEnabledImpl(Features, "clflushopt", true); 3250 setFeatureEnabledImpl(Features, "clzero", true); 3251 setFeatureEnabledImpl(Features, "cx16", true); 3252 setFeatureEnabledImpl(Features, "f16c", true); 3253 setFeatureEnabledImpl(Features, "fma", true); 3254 setFeatureEnabledImpl(Features, "fsgsbase", true); 3255 setFeatureEnabledImpl(Features, "fxsr", true); 3256 setFeatureEnabledImpl(Features, "lzcnt", true); 3257 setFeatureEnabledImpl(Features, "mwaitx", true); 3258 setFeatureEnabledImpl(Features, "movbe", true); 3259 setFeatureEnabledImpl(Features, "pclmul", true); 3260 setFeatureEnabledImpl(Features, "popcnt", true); 3261 setFeatureEnabledImpl(Features, "prfchw", true); 3262 setFeatureEnabledImpl(Features, "rdrnd", true); 3263 setFeatureEnabledImpl(Features, "rdseed", true); 3264 setFeatureEnabledImpl(Features, "sha", true); 3265 setFeatureEnabledImpl(Features, "sse4a", true); 3266 setFeatureEnabledImpl(Features, "xsave", true); 3267 setFeatureEnabledImpl(Features, "xsavec", true); 3268 setFeatureEnabledImpl(Features, "xsaveopt", true); 3269 setFeatureEnabledImpl(Features, "xsaves", true); 3270 break; 3271 case CK_BDVER4: 3272 setFeatureEnabledImpl(Features, "avx2", true); 3273 setFeatureEnabledImpl(Features, "bmi2", true); 3274 setFeatureEnabledImpl(Features, "mwaitx", true); 3275 LLVM_FALLTHROUGH; 3276 case CK_BDVER3: 3277 setFeatureEnabledImpl(Features, "fsgsbase", true); 3278 setFeatureEnabledImpl(Features, "xsaveopt", true); 3279 LLVM_FALLTHROUGH; 3280 case CK_BDVER2: 3281 setFeatureEnabledImpl(Features, "bmi", true); 3282 setFeatureEnabledImpl(Features, "fma", true); 3283 setFeatureEnabledImpl(Features, "f16c", true); 3284 setFeatureEnabledImpl(Features, "tbm", true); 3285 LLVM_FALLTHROUGH; 3286 case CK_BDVER1: 3287 // xop implies avx, sse4a and fma4. 3288 setFeatureEnabledImpl(Features, "xop", true); 3289 setFeatureEnabledImpl(Features, "lzcnt", true); 3290 setFeatureEnabledImpl(Features, "aes", true); 3291 setFeatureEnabledImpl(Features, "pclmul", true); 3292 setFeatureEnabledImpl(Features, "prfchw", true); 3293 setFeatureEnabledImpl(Features, "cx16", true); 3294 setFeatureEnabledImpl(Features, "fxsr", true); 3295 setFeatureEnabledImpl(Features, "xsave", true); 3296 break; 3297 } 3298 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3299 return false; 3300 3301 // Can't do this earlier because we need to be able to explicitly enable 3302 // or disable these features and the things that they depend upon. 3303 3304 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3305 auto I = Features.find("sse4.2"); 3306 if (I != Features.end() && I->getValue() && 3307 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3308 FeaturesVec.end()) 3309 Features["popcnt"] = true; 3310 3311 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3312 I = Features.find("3dnow"); 3313 if (I != Features.end() && I->getValue() && 3314 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3315 FeaturesVec.end()) 3316 Features["prfchw"] = true; 3317 3318 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3319 // then enable MMX. 3320 I = Features.find("sse"); 3321 if (I != Features.end() && I->getValue() && 3322 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3323 FeaturesVec.end()) 3324 Features["mmx"] = true; 3325 3326 return true; 3327 } 3328 3329 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3330 X86SSEEnum Level, bool Enabled) { 3331 if (Enabled) { 3332 switch (Level) { 3333 case AVX512F: 3334 Features["avx512f"] = true; 3335 case AVX2: 3336 Features["avx2"] = true; 3337 case AVX: 3338 Features["avx"] = true; 3339 Features["xsave"] = true; 3340 case SSE42: 3341 Features["sse4.2"] = true; 3342 case SSE41: 3343 Features["sse4.1"] = true; 3344 case SSSE3: 3345 Features["ssse3"] = true; 3346 case SSE3: 3347 Features["sse3"] = true; 3348 case SSE2: 3349 Features["sse2"] = true; 3350 case SSE1: 3351 Features["sse"] = true; 3352 case NoSSE: 3353 break; 3354 } 3355 return; 3356 } 3357 3358 switch (Level) { 3359 case NoSSE: 3360 case SSE1: 3361 Features["sse"] = false; 3362 case SSE2: 3363 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3364 Features["sha"] = false; 3365 case SSE3: 3366 Features["sse3"] = false; 3367 setXOPLevel(Features, NoXOP, false); 3368 case SSSE3: 3369 Features["ssse3"] = false; 3370 case SSE41: 3371 Features["sse4.1"] = false; 3372 case SSE42: 3373 Features["sse4.2"] = false; 3374 case AVX: 3375 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3376 Features["xsaveopt"] = false; 3377 setXOPLevel(Features, FMA4, false); 3378 case AVX2: 3379 Features["avx2"] = false; 3380 case AVX512F: 3381 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3382 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3383 Features["avx512vl"] = Features["avx512vbmi"] = 3384 Features["avx512ifma"] = false; 3385 } 3386 } 3387 3388 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3389 MMX3DNowEnum Level, bool Enabled) { 3390 if (Enabled) { 3391 switch (Level) { 3392 case AMD3DNowAthlon: 3393 Features["3dnowa"] = true; 3394 case AMD3DNow: 3395 Features["3dnow"] = true; 3396 case MMX: 3397 Features["mmx"] = true; 3398 case NoMMX3DNow: 3399 break; 3400 } 3401 return; 3402 } 3403 3404 switch (Level) { 3405 case NoMMX3DNow: 3406 case MMX: 3407 Features["mmx"] = false; 3408 case AMD3DNow: 3409 Features["3dnow"] = false; 3410 case AMD3DNowAthlon: 3411 Features["3dnowa"] = false; 3412 } 3413 } 3414 3415 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3416 bool Enabled) { 3417 if (Enabled) { 3418 switch (Level) { 3419 case XOP: 3420 Features["xop"] = true; 3421 case FMA4: 3422 Features["fma4"] = true; 3423 setSSELevel(Features, AVX, true); 3424 case SSE4A: 3425 Features["sse4a"] = true; 3426 setSSELevel(Features, SSE3, true); 3427 case NoXOP: 3428 break; 3429 } 3430 return; 3431 } 3432 3433 switch (Level) { 3434 case NoXOP: 3435 case SSE4A: 3436 Features["sse4a"] = false; 3437 case FMA4: 3438 Features["fma4"] = false; 3439 case XOP: 3440 Features["xop"] = false; 3441 } 3442 } 3443 3444 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3445 StringRef Name, bool Enabled) { 3446 // This is a bit of a hack to deal with the sse4 target feature when used 3447 // as part of the target attribute. We handle sse4 correctly everywhere 3448 // else. See below for more information on how we handle the sse4 options. 3449 if (Name != "sse4") 3450 Features[Name] = Enabled; 3451 3452 if (Name == "mmx") { 3453 setMMXLevel(Features, MMX, Enabled); 3454 } else if (Name == "sse") { 3455 setSSELevel(Features, SSE1, Enabled); 3456 } else if (Name == "sse2") { 3457 setSSELevel(Features, SSE2, Enabled); 3458 } else if (Name == "sse3") { 3459 setSSELevel(Features, SSE3, Enabled); 3460 } else if (Name == "ssse3") { 3461 setSSELevel(Features, SSSE3, Enabled); 3462 } else if (Name == "sse4.2") { 3463 setSSELevel(Features, SSE42, Enabled); 3464 } else if (Name == "sse4.1") { 3465 setSSELevel(Features, SSE41, Enabled); 3466 } else if (Name == "3dnow") { 3467 setMMXLevel(Features, AMD3DNow, Enabled); 3468 } else if (Name == "3dnowa") { 3469 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3470 } else if (Name == "aes") { 3471 if (Enabled) 3472 setSSELevel(Features, SSE2, Enabled); 3473 } else if (Name == "pclmul") { 3474 if (Enabled) 3475 setSSELevel(Features, SSE2, Enabled); 3476 } else if (Name == "avx") { 3477 setSSELevel(Features, AVX, Enabled); 3478 } else if (Name == "avx2") { 3479 setSSELevel(Features, AVX2, Enabled); 3480 } else if (Name == "avx512f") { 3481 setSSELevel(Features, AVX512F, Enabled); 3482 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3483 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3484 Name == "avx512vbmi" || Name == "avx512ifma") { 3485 if (Enabled) 3486 setSSELevel(Features, AVX512F, Enabled); 3487 // Enable BWI instruction if VBMI is being enabled. 3488 if (Name == "avx512vbmi" && Enabled) 3489 Features["avx512bw"] = true; 3490 // Also disable VBMI if BWI is being disabled. 3491 if (Name == "avx512bw" && !Enabled) 3492 Features["avx512vbmi"] = false; 3493 } else if (Name == "fma") { 3494 if (Enabled) 3495 setSSELevel(Features, AVX, Enabled); 3496 } else if (Name == "fma4") { 3497 setXOPLevel(Features, FMA4, Enabled); 3498 } else if (Name == "xop") { 3499 setXOPLevel(Features, XOP, Enabled); 3500 } else if (Name == "sse4a") { 3501 setXOPLevel(Features, SSE4A, Enabled); 3502 } else if (Name == "f16c") { 3503 if (Enabled) 3504 setSSELevel(Features, AVX, Enabled); 3505 } else if (Name == "sha") { 3506 if (Enabled) 3507 setSSELevel(Features, SSE2, Enabled); 3508 } else if (Name == "sse4") { 3509 // We can get here via the __target__ attribute since that's not controlled 3510 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3511 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3512 // disabled. 3513 if (Enabled) 3514 setSSELevel(Features, SSE42, Enabled); 3515 else 3516 setSSELevel(Features, SSE41, Enabled); 3517 } else if (Name == "xsave") { 3518 if (!Enabled) 3519 Features["xsaveopt"] = false; 3520 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3521 if (Enabled) 3522 Features["xsave"] = true; 3523 } 3524 } 3525 3526 /// handleTargetFeatures - Perform initialization based on the user 3527 /// configured set of features. 3528 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3529 DiagnosticsEngine &Diags) { 3530 for (const auto &Feature : Features) { 3531 if (Feature[0] != '+') 3532 continue; 3533 3534 if (Feature == "+aes") { 3535 HasAES = true; 3536 } else if (Feature == "+pclmul") { 3537 HasPCLMUL = true; 3538 } else if (Feature == "+lzcnt") { 3539 HasLZCNT = true; 3540 } else if (Feature == "+rdrnd") { 3541 HasRDRND = true; 3542 } else if (Feature == "+fsgsbase") { 3543 HasFSGSBASE = true; 3544 } else if (Feature == "+bmi") { 3545 HasBMI = true; 3546 } else if (Feature == "+bmi2") { 3547 HasBMI2 = true; 3548 } else if (Feature == "+popcnt") { 3549 HasPOPCNT = true; 3550 } else if (Feature == "+rtm") { 3551 HasRTM = true; 3552 } else if (Feature == "+prfchw") { 3553 HasPRFCHW = true; 3554 } else if (Feature == "+rdseed") { 3555 HasRDSEED = true; 3556 } else if (Feature == "+adx") { 3557 HasADX = true; 3558 } else if (Feature == "+tbm") { 3559 HasTBM = true; 3560 } else if (Feature == "+fma") { 3561 HasFMA = true; 3562 } else if (Feature == "+f16c") { 3563 HasF16C = true; 3564 } else if (Feature == "+avx512cd") { 3565 HasAVX512CD = true; 3566 } else if (Feature == "+avx512er") { 3567 HasAVX512ER = true; 3568 } else if (Feature == "+avx512pf") { 3569 HasAVX512PF = true; 3570 } else if (Feature == "+avx512dq") { 3571 HasAVX512DQ = true; 3572 } else if (Feature == "+avx512bw") { 3573 HasAVX512BW = true; 3574 } else if (Feature == "+avx512vl") { 3575 HasAVX512VL = true; 3576 } else if (Feature == "+avx512vbmi") { 3577 HasAVX512VBMI = true; 3578 } else if (Feature == "+avx512ifma") { 3579 HasAVX512IFMA = true; 3580 } else if (Feature == "+sha") { 3581 HasSHA = true; 3582 } else if (Feature == "+mpx") { 3583 HasMPX = true; 3584 } else if (Feature == "+movbe") { 3585 HasMOVBE = true; 3586 } else if (Feature == "+sgx") { 3587 HasSGX = true; 3588 } else if (Feature == "+cx16") { 3589 HasCX16 = true; 3590 } else if (Feature == "+fxsr") { 3591 HasFXSR = true; 3592 } else if (Feature == "+xsave") { 3593 HasXSAVE = true; 3594 } else if (Feature == "+xsaveopt") { 3595 HasXSAVEOPT = true; 3596 } else if (Feature == "+xsavec") { 3597 HasXSAVEC = true; 3598 } else if (Feature == "+xsaves") { 3599 HasXSAVES = true; 3600 } else if (Feature == "+mwaitx") { 3601 HasMWAITX = true; 3602 } else if (Feature == "+pku") { 3603 HasPKU = true; 3604 } else if (Feature == "+clflushopt") { 3605 HasCLFLUSHOPT = true; 3606 } else if (Feature == "+clwb") { 3607 HasCLWB = true; 3608 } else if (Feature == "+prefetchwt1") { 3609 HasPREFETCHWT1 = true; 3610 } else if (Feature == "+clzero") { 3611 HasCLZERO = true; 3612 } 3613 3614 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3615 .Case("+avx512f", AVX512F) 3616 .Case("+avx2", AVX2) 3617 .Case("+avx", AVX) 3618 .Case("+sse4.2", SSE42) 3619 .Case("+sse4.1", SSE41) 3620 .Case("+ssse3", SSSE3) 3621 .Case("+sse3", SSE3) 3622 .Case("+sse2", SSE2) 3623 .Case("+sse", SSE1) 3624 .Default(NoSSE); 3625 SSELevel = std::max(SSELevel, Level); 3626 3627 MMX3DNowEnum ThreeDNowLevel = 3628 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3629 .Case("+3dnowa", AMD3DNowAthlon) 3630 .Case("+3dnow", AMD3DNow) 3631 .Case("+mmx", MMX) 3632 .Default(NoMMX3DNow); 3633 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3634 3635 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3636 .Case("+xop", XOP) 3637 .Case("+fma4", FMA4) 3638 .Case("+sse4a", SSE4A) 3639 .Default(NoXOP); 3640 XOPLevel = std::max(XOPLevel, XLevel); 3641 } 3642 3643 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3644 // matches the selected sse level. 3645 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3646 (FPMath == FP_387 && SSELevel >= SSE1)) { 3647 Diags.Report(diag::err_target_unsupported_fpmath) << 3648 (FPMath == FP_SSE ? "sse" : "387"); 3649 return false; 3650 } 3651 3652 SimdDefaultAlign = 3653 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3654 return true; 3655 } 3656 3657 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3658 /// definitions for this particular subtarget. 3659 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3660 MacroBuilder &Builder) const { 3661 // Target identification. 3662 if (getTriple().getArch() == llvm::Triple::x86_64) { 3663 Builder.defineMacro("__amd64__"); 3664 Builder.defineMacro("__amd64"); 3665 Builder.defineMacro("__x86_64"); 3666 Builder.defineMacro("__x86_64__"); 3667 if (getTriple().getArchName() == "x86_64h") { 3668 Builder.defineMacro("__x86_64h"); 3669 Builder.defineMacro("__x86_64h__"); 3670 } 3671 } else { 3672 DefineStd(Builder, "i386", Opts); 3673 } 3674 3675 // Subtarget options. 3676 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3677 // truly should be based on -mtune options. 3678 switch (CPU) { 3679 case CK_Generic: 3680 break; 3681 case CK_i386: 3682 // The rest are coming from the i386 define above. 3683 Builder.defineMacro("__tune_i386__"); 3684 break; 3685 case CK_i486: 3686 case CK_WinChipC6: 3687 case CK_WinChip2: 3688 case CK_C3: 3689 defineCPUMacros(Builder, "i486"); 3690 break; 3691 case CK_PentiumMMX: 3692 Builder.defineMacro("__pentium_mmx__"); 3693 Builder.defineMacro("__tune_pentium_mmx__"); 3694 // Fallthrough 3695 case CK_i586: 3696 case CK_Pentium: 3697 defineCPUMacros(Builder, "i586"); 3698 defineCPUMacros(Builder, "pentium"); 3699 break; 3700 case CK_Pentium3: 3701 case CK_Pentium3M: 3702 case CK_PentiumM: 3703 Builder.defineMacro("__tune_pentium3__"); 3704 // Fallthrough 3705 case CK_Pentium2: 3706 case CK_C3_2: 3707 Builder.defineMacro("__tune_pentium2__"); 3708 // Fallthrough 3709 case CK_PentiumPro: 3710 Builder.defineMacro("__tune_i686__"); 3711 Builder.defineMacro("__tune_pentiumpro__"); 3712 // Fallthrough 3713 case CK_i686: 3714 Builder.defineMacro("__i686"); 3715 Builder.defineMacro("__i686__"); 3716 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3717 Builder.defineMacro("__pentiumpro"); 3718 Builder.defineMacro("__pentiumpro__"); 3719 break; 3720 case CK_Pentium4: 3721 case CK_Pentium4M: 3722 defineCPUMacros(Builder, "pentium4"); 3723 break; 3724 case CK_Yonah: 3725 case CK_Prescott: 3726 case CK_Nocona: 3727 defineCPUMacros(Builder, "nocona"); 3728 break; 3729 case CK_Core2: 3730 case CK_Penryn: 3731 defineCPUMacros(Builder, "core2"); 3732 break; 3733 case CK_Bonnell: 3734 defineCPUMacros(Builder, "atom"); 3735 break; 3736 case CK_Silvermont: 3737 defineCPUMacros(Builder, "slm"); 3738 break; 3739 case CK_Nehalem: 3740 case CK_Westmere: 3741 case CK_SandyBridge: 3742 case CK_IvyBridge: 3743 case CK_Haswell: 3744 case CK_Broadwell: 3745 case CK_SkylakeClient: 3746 // FIXME: Historically, we defined this legacy name, it would be nice to 3747 // remove it at some point. We've never exposed fine-grained names for 3748 // recent primary x86 CPUs, and we should keep it that way. 3749 defineCPUMacros(Builder, "corei7"); 3750 break; 3751 case CK_SkylakeServer: 3752 defineCPUMacros(Builder, "skx"); 3753 break; 3754 case CK_Cannonlake: 3755 break; 3756 case CK_KNL: 3757 defineCPUMacros(Builder, "knl"); 3758 break; 3759 case CK_Lakemont: 3760 Builder.defineMacro("__tune_lakemont__"); 3761 break; 3762 case CK_K6_2: 3763 Builder.defineMacro("__k6_2__"); 3764 Builder.defineMacro("__tune_k6_2__"); 3765 // Fallthrough 3766 case CK_K6_3: 3767 if (CPU != CK_K6_2) { // In case of fallthrough 3768 // FIXME: GCC may be enabling these in cases where some other k6 3769 // architecture is specified but -m3dnow is explicitly provided. The 3770 // exact semantics need to be determined and emulated here. 3771 Builder.defineMacro("__k6_3__"); 3772 Builder.defineMacro("__tune_k6_3__"); 3773 } 3774 // Fallthrough 3775 case CK_K6: 3776 defineCPUMacros(Builder, "k6"); 3777 break; 3778 case CK_Athlon: 3779 case CK_AthlonThunderbird: 3780 case CK_Athlon4: 3781 case CK_AthlonXP: 3782 case CK_AthlonMP: 3783 defineCPUMacros(Builder, "athlon"); 3784 if (SSELevel != NoSSE) { 3785 Builder.defineMacro("__athlon_sse__"); 3786 Builder.defineMacro("__tune_athlon_sse__"); 3787 } 3788 break; 3789 case CK_K8: 3790 case CK_K8SSE3: 3791 case CK_x86_64: 3792 case CK_Opteron: 3793 case CK_OpteronSSE3: 3794 case CK_Athlon64: 3795 case CK_Athlon64SSE3: 3796 case CK_AthlonFX: 3797 defineCPUMacros(Builder, "k8"); 3798 break; 3799 case CK_AMDFAM10: 3800 defineCPUMacros(Builder, "amdfam10"); 3801 break; 3802 case CK_BTVER1: 3803 defineCPUMacros(Builder, "btver1"); 3804 break; 3805 case CK_BTVER2: 3806 defineCPUMacros(Builder, "btver2"); 3807 break; 3808 case CK_BDVER1: 3809 defineCPUMacros(Builder, "bdver1"); 3810 break; 3811 case CK_BDVER2: 3812 defineCPUMacros(Builder, "bdver2"); 3813 break; 3814 case CK_BDVER3: 3815 defineCPUMacros(Builder, "bdver3"); 3816 break; 3817 case CK_BDVER4: 3818 defineCPUMacros(Builder, "bdver4"); 3819 break; 3820 case CK_ZNVER1: 3821 defineCPUMacros(Builder, "znver1"); 3822 break; 3823 case CK_Geode: 3824 defineCPUMacros(Builder, "geode"); 3825 break; 3826 } 3827 3828 // Target properties. 3829 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3830 3831 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3832 // functions in glibc header files that use FP Stack inline asm which the 3833 // backend can't deal with (PR879). 3834 Builder.defineMacro("__NO_MATH_INLINES"); 3835 3836 if (HasAES) 3837 Builder.defineMacro("__AES__"); 3838 3839 if (HasPCLMUL) 3840 Builder.defineMacro("__PCLMUL__"); 3841 3842 if (HasLZCNT) 3843 Builder.defineMacro("__LZCNT__"); 3844 3845 if (HasRDRND) 3846 Builder.defineMacro("__RDRND__"); 3847 3848 if (HasFSGSBASE) 3849 Builder.defineMacro("__FSGSBASE__"); 3850 3851 if (HasBMI) 3852 Builder.defineMacro("__BMI__"); 3853 3854 if (HasBMI2) 3855 Builder.defineMacro("__BMI2__"); 3856 3857 if (HasPOPCNT) 3858 Builder.defineMacro("__POPCNT__"); 3859 3860 if (HasRTM) 3861 Builder.defineMacro("__RTM__"); 3862 3863 if (HasPRFCHW) 3864 Builder.defineMacro("__PRFCHW__"); 3865 3866 if (HasRDSEED) 3867 Builder.defineMacro("__RDSEED__"); 3868 3869 if (HasADX) 3870 Builder.defineMacro("__ADX__"); 3871 3872 if (HasTBM) 3873 Builder.defineMacro("__TBM__"); 3874 3875 if (HasMWAITX) 3876 Builder.defineMacro("__MWAITX__"); 3877 3878 switch (XOPLevel) { 3879 case XOP: 3880 Builder.defineMacro("__XOP__"); 3881 case FMA4: 3882 Builder.defineMacro("__FMA4__"); 3883 case SSE4A: 3884 Builder.defineMacro("__SSE4A__"); 3885 case NoXOP: 3886 break; 3887 } 3888 3889 if (HasFMA) 3890 Builder.defineMacro("__FMA__"); 3891 3892 if (HasF16C) 3893 Builder.defineMacro("__F16C__"); 3894 3895 if (HasAVX512CD) 3896 Builder.defineMacro("__AVX512CD__"); 3897 if (HasAVX512ER) 3898 Builder.defineMacro("__AVX512ER__"); 3899 if (HasAVX512PF) 3900 Builder.defineMacro("__AVX512PF__"); 3901 if (HasAVX512DQ) 3902 Builder.defineMacro("__AVX512DQ__"); 3903 if (HasAVX512BW) 3904 Builder.defineMacro("__AVX512BW__"); 3905 if (HasAVX512VL) 3906 Builder.defineMacro("__AVX512VL__"); 3907 if (HasAVX512VBMI) 3908 Builder.defineMacro("__AVX512VBMI__"); 3909 if (HasAVX512IFMA) 3910 Builder.defineMacro("__AVX512IFMA__"); 3911 3912 if (HasSHA) 3913 Builder.defineMacro("__SHA__"); 3914 3915 if (HasFXSR) 3916 Builder.defineMacro("__FXSR__"); 3917 if (HasXSAVE) 3918 Builder.defineMacro("__XSAVE__"); 3919 if (HasXSAVEOPT) 3920 Builder.defineMacro("__XSAVEOPT__"); 3921 if (HasXSAVEC) 3922 Builder.defineMacro("__XSAVEC__"); 3923 if (HasXSAVES) 3924 Builder.defineMacro("__XSAVES__"); 3925 if (HasPKU) 3926 Builder.defineMacro("__PKU__"); 3927 if (HasCX16) 3928 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3929 if (HasCLFLUSHOPT) 3930 Builder.defineMacro("__CLFLUSHOPT__"); 3931 if (HasCLWB) 3932 Builder.defineMacro("__CLWB__"); 3933 if (HasMPX) 3934 Builder.defineMacro("__MPX__"); 3935 if (HasSGX) 3936 Builder.defineMacro("__SGX__"); 3937 if (HasPREFETCHWT1) 3938 Builder.defineMacro("__PREFETCHWT1__"); 3939 if (HasCLZERO) 3940 Builder.defineMacro("__CLZERO__"); 3941 3942 // Each case falls through to the previous one here. 3943 switch (SSELevel) { 3944 case AVX512F: 3945 Builder.defineMacro("__AVX512F__"); 3946 case AVX2: 3947 Builder.defineMacro("__AVX2__"); 3948 case AVX: 3949 Builder.defineMacro("__AVX__"); 3950 case SSE42: 3951 Builder.defineMacro("__SSE4_2__"); 3952 case SSE41: 3953 Builder.defineMacro("__SSE4_1__"); 3954 case SSSE3: 3955 Builder.defineMacro("__SSSE3__"); 3956 case SSE3: 3957 Builder.defineMacro("__SSE3__"); 3958 case SSE2: 3959 Builder.defineMacro("__SSE2__"); 3960 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3961 case SSE1: 3962 Builder.defineMacro("__SSE__"); 3963 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3964 case NoSSE: 3965 break; 3966 } 3967 3968 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3969 switch (SSELevel) { 3970 case AVX512F: 3971 case AVX2: 3972 case AVX: 3973 case SSE42: 3974 case SSE41: 3975 case SSSE3: 3976 case SSE3: 3977 case SSE2: 3978 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3979 break; 3980 case SSE1: 3981 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3982 break; 3983 default: 3984 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3985 } 3986 } 3987 3988 // Each case falls through to the previous one here. 3989 switch (MMX3DNowLevel) { 3990 case AMD3DNowAthlon: 3991 Builder.defineMacro("__3dNOW_A__"); 3992 case AMD3DNow: 3993 Builder.defineMacro("__3dNOW__"); 3994 case MMX: 3995 Builder.defineMacro("__MMX__"); 3996 case NoMMX3DNow: 3997 break; 3998 } 3999 4000 if (CPU >= CK_i486) { 4001 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4002 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4003 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4004 } 4005 if (CPU >= CK_i586) 4006 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4007 } 4008 4009 bool X86TargetInfo::hasFeature(StringRef Feature) const { 4010 return llvm::StringSwitch<bool>(Feature) 4011 .Case("aes", HasAES) 4012 .Case("avx", SSELevel >= AVX) 4013 .Case("avx2", SSELevel >= AVX2) 4014 .Case("avx512f", SSELevel >= AVX512F) 4015 .Case("avx512cd", HasAVX512CD) 4016 .Case("avx512er", HasAVX512ER) 4017 .Case("avx512pf", HasAVX512PF) 4018 .Case("avx512dq", HasAVX512DQ) 4019 .Case("avx512bw", HasAVX512BW) 4020 .Case("avx512vl", HasAVX512VL) 4021 .Case("avx512vbmi", HasAVX512VBMI) 4022 .Case("avx512ifma", HasAVX512IFMA) 4023 .Case("bmi", HasBMI) 4024 .Case("bmi2", HasBMI2) 4025 .Case("clflushopt", HasCLFLUSHOPT) 4026 .Case("clwb", HasCLWB) 4027 .Case("clzero", HasCLZERO) 4028 .Case("cx16", HasCX16) 4029 .Case("f16c", HasF16C) 4030 .Case("fma", HasFMA) 4031 .Case("fma4", XOPLevel >= FMA4) 4032 .Case("fsgsbase", HasFSGSBASE) 4033 .Case("fxsr", HasFXSR) 4034 .Case("lzcnt", HasLZCNT) 4035 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4036 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4037 .Case("mmx", MMX3DNowLevel >= MMX) 4038 .Case("movbe", HasMOVBE) 4039 .Case("mpx", HasMPX) 4040 .Case("pclmul", HasPCLMUL) 4041 .Case("pku", HasPKU) 4042 .Case("popcnt", HasPOPCNT) 4043 .Case("prefetchwt1", HasPREFETCHWT1) 4044 .Case("prfchw", HasPRFCHW) 4045 .Case("rdrnd", HasRDRND) 4046 .Case("rdseed", HasRDSEED) 4047 .Case("rtm", HasRTM) 4048 .Case("sgx", HasSGX) 4049 .Case("sha", HasSHA) 4050 .Case("sse", SSELevel >= SSE1) 4051 .Case("sse2", SSELevel >= SSE2) 4052 .Case("sse3", SSELevel >= SSE3) 4053 .Case("ssse3", SSELevel >= SSSE3) 4054 .Case("sse4.1", SSELevel >= SSE41) 4055 .Case("sse4.2", SSELevel >= SSE42) 4056 .Case("sse4a", XOPLevel >= SSE4A) 4057 .Case("tbm", HasTBM) 4058 .Case("x86", true) 4059 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4060 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4061 .Case("xop", XOPLevel >= XOP) 4062 .Case("xsave", HasXSAVE) 4063 .Case("xsavec", HasXSAVEC) 4064 .Case("xsaves", HasXSAVES) 4065 .Case("xsaveopt", HasXSAVEOPT) 4066 .Default(false); 4067 } 4068 4069 // We can't use a generic validation scheme for the features accepted here 4070 // versus subtarget features accepted in the target attribute because the 4071 // bitfield structure that's initialized in the runtime only supports the 4072 // below currently rather than the full range of subtarget features. (See 4073 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4074 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4075 return llvm::StringSwitch<bool>(FeatureStr) 4076 .Case("cmov", true) 4077 .Case("mmx", true) 4078 .Case("popcnt", true) 4079 .Case("sse", true) 4080 .Case("sse2", true) 4081 .Case("sse3", true) 4082 .Case("ssse3", true) 4083 .Case("sse4.1", true) 4084 .Case("sse4.2", true) 4085 .Case("avx", true) 4086 .Case("avx2", true) 4087 .Case("sse4a", true) 4088 .Case("fma4", true) 4089 .Case("xop", true) 4090 .Case("fma", true) 4091 .Case("avx512f", true) 4092 .Case("bmi", true) 4093 .Case("bmi2", true) 4094 .Case("aes", true) 4095 .Case("pclmul", true) 4096 .Case("avx512vl", true) 4097 .Case("avx512bw", true) 4098 .Case("avx512dq", true) 4099 .Case("avx512cd", true) 4100 .Case("avx512er", true) 4101 .Case("avx512pf", true) 4102 .Case("avx512vbmi", true) 4103 .Case("avx512ifma", true) 4104 .Default(false); 4105 } 4106 4107 bool 4108 X86TargetInfo::validateAsmConstraint(const char *&Name, 4109 TargetInfo::ConstraintInfo &Info) const { 4110 switch (*Name) { 4111 default: return false; 4112 // Constant constraints. 4113 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4114 // instructions. 4115 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4116 // x86_64 instructions. 4117 case 's': 4118 Info.setRequiresImmediate(); 4119 return true; 4120 case 'I': 4121 Info.setRequiresImmediate(0, 31); 4122 return true; 4123 case 'J': 4124 Info.setRequiresImmediate(0, 63); 4125 return true; 4126 case 'K': 4127 Info.setRequiresImmediate(-128, 127); 4128 return true; 4129 case 'L': 4130 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4131 return true; 4132 case 'M': 4133 Info.setRequiresImmediate(0, 3); 4134 return true; 4135 case 'N': 4136 Info.setRequiresImmediate(0, 255); 4137 return true; 4138 case 'O': 4139 Info.setRequiresImmediate(0, 127); 4140 return true; 4141 // Register constraints. 4142 case 'Y': // 'Y' is the first character for several 2-character constraints. 4143 // Shift the pointer to the second character of the constraint. 4144 Name++; 4145 switch (*Name) { 4146 default: 4147 return false; 4148 case '0': // First SSE register. 4149 case 't': // Any SSE register, when SSE2 is enabled. 4150 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4151 case 'm': // Any MMX register, when inter-unit moves enabled. 4152 case 'k': // AVX512 arch mask registers: k1-k7. 4153 Info.setAllowsRegister(); 4154 return true; 4155 } 4156 case 'f': // Any x87 floating point stack register. 4157 // Constraint 'f' cannot be used for output operands. 4158 if (Info.ConstraintStr[0] == '=') 4159 return false; 4160 Info.setAllowsRegister(); 4161 return true; 4162 case 'a': // eax. 4163 case 'b': // ebx. 4164 case 'c': // ecx. 4165 case 'd': // edx. 4166 case 'S': // esi. 4167 case 'D': // edi. 4168 case 'A': // edx:eax. 4169 case 't': // Top of floating point stack. 4170 case 'u': // Second from top of floating point stack. 4171 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4172 case 'y': // Any MMX register. 4173 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4174 case 'x': // Any SSE register. 4175 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4176 // for intermideate k reg operations). 4177 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4178 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4179 case 'l': // "Index" registers: any general register that can be used as an 4180 // index in a base+index memory access. 4181 Info.setAllowsRegister(); 4182 return true; 4183 // Floating point constant constraints. 4184 case 'C': // SSE floating point constant. 4185 case 'G': // x87 floating point constant. 4186 return true; 4187 } 4188 } 4189 4190 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4191 unsigned Size) const { 4192 // Strip off constraint modifiers. 4193 while (Constraint[0] == '=' || 4194 Constraint[0] == '+' || 4195 Constraint[0] == '&') 4196 Constraint = Constraint.substr(1); 4197 4198 return validateOperandSize(Constraint, Size); 4199 } 4200 4201 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4202 unsigned Size) const { 4203 return validateOperandSize(Constraint, Size); 4204 } 4205 4206 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4207 unsigned Size) const { 4208 switch (Constraint[0]) { 4209 default: break; 4210 case 'k': 4211 // Registers k0-k7 (AVX512) size limit is 64 bit. 4212 case 'y': 4213 return Size <= 64; 4214 case 'f': 4215 case 't': 4216 case 'u': 4217 return Size <= 128; 4218 case 'v': 4219 case 'x': 4220 if (SSELevel >= AVX512F) 4221 // 512-bit zmm registers can be used if target supports AVX512F. 4222 return Size <= 512U; 4223 else if (SSELevel >= AVX) 4224 // 256-bit ymm registers can be used if target supports AVX. 4225 return Size <= 256U; 4226 return Size <= 128U; 4227 case 'Y': 4228 // 'Y' is the first character for several 2-character constraints. 4229 switch (Constraint[1]) { 4230 default: break; 4231 case 'm': 4232 // 'Ym' is synonymous with 'y'. 4233 case 'k': 4234 return Size <= 64; 4235 case 'i': 4236 case 't': 4237 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4238 if (SSELevel >= AVX512F) 4239 return Size <= 512U; 4240 else if (SSELevel >= AVX) 4241 return Size <= 256U; 4242 return SSELevel >= SSE2 && Size <= 128U; 4243 } 4244 4245 } 4246 4247 return true; 4248 } 4249 4250 std::string 4251 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4252 switch (*Constraint) { 4253 case 'a': return std::string("{ax}"); 4254 case 'b': return std::string("{bx}"); 4255 case 'c': return std::string("{cx}"); 4256 case 'd': return std::string("{dx}"); 4257 case 'S': return std::string("{si}"); 4258 case 'D': return std::string("{di}"); 4259 case 'p': // address 4260 return std::string("im"); 4261 case 't': // top of floating point stack. 4262 return std::string("{st}"); 4263 case 'u': // second from top of floating point stack. 4264 return std::string("{st(1)}"); // second from top of floating point stack. 4265 case 'Y': 4266 switch (Constraint[1]) { 4267 default: 4268 // Break from inner switch and fall through (copy single char), 4269 // continue parsing after copying the current constraint into 4270 // the return string. 4271 break; 4272 case 'k': 4273 // "^" hints llvm that this is a 2 letter constraint. 4274 // "Constraint++" is used to promote the string iterator 4275 // to the next constraint. 4276 return std::string("^") + std::string(Constraint++, 2); 4277 } 4278 LLVM_FALLTHROUGH; 4279 default: 4280 return std::string(1, *Constraint); 4281 } 4282 } 4283 4284 // X86-32 generic target 4285 class X86_32TargetInfo : public X86TargetInfo { 4286 public: 4287 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4288 : X86TargetInfo(Triple, Opts) { 4289 DoubleAlign = LongLongAlign = 32; 4290 LongDoubleWidth = 96; 4291 LongDoubleAlign = 32; 4292 SuitableAlign = 128; 4293 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4294 SizeType = UnsignedInt; 4295 PtrDiffType = SignedInt; 4296 IntPtrType = SignedInt; 4297 RegParmMax = 3; 4298 4299 // Use fpret for all types. 4300 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4301 (1 << TargetInfo::Double) | 4302 (1 << TargetInfo::LongDouble)); 4303 4304 // x86-32 has atomics up to 8 bytes 4305 // FIXME: Check that we actually have cmpxchg8b before setting 4306 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4307 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4308 } 4309 BuiltinVaListKind getBuiltinVaListKind() const override { 4310 return TargetInfo::CharPtrBuiltinVaList; 4311 } 4312 4313 int getEHDataRegisterNumber(unsigned RegNo) const override { 4314 if (RegNo == 0) return 0; 4315 if (RegNo == 1) return 2; 4316 return -1; 4317 } 4318 bool validateOperandSize(StringRef Constraint, 4319 unsigned Size) const override { 4320 switch (Constraint[0]) { 4321 default: break; 4322 case 'R': 4323 case 'q': 4324 case 'Q': 4325 case 'a': 4326 case 'b': 4327 case 'c': 4328 case 'd': 4329 case 'S': 4330 case 'D': 4331 return Size <= 32; 4332 case 'A': 4333 return Size <= 64; 4334 } 4335 4336 return X86TargetInfo::validateOperandSize(Constraint, Size); 4337 } 4338 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4339 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4340 Builtin::FirstTSBuiltin + 1); 4341 } 4342 }; 4343 4344 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4345 public: 4346 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4347 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4348 4349 unsigned getFloatEvalMethod() const override { 4350 unsigned Major, Minor, Micro; 4351 getTriple().getOSVersion(Major, Minor, Micro); 4352 // New NetBSD uses the default rounding mode. 4353 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4354 return X86_32TargetInfo::getFloatEvalMethod(); 4355 // NetBSD before 6.99.26 defaults to "double" rounding. 4356 return 1; 4357 } 4358 }; 4359 4360 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4361 public: 4362 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4363 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4364 SizeType = UnsignedLong; 4365 IntPtrType = SignedLong; 4366 PtrDiffType = SignedLong; 4367 } 4368 }; 4369 4370 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4371 public: 4372 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4373 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4374 SizeType = UnsignedLong; 4375 IntPtrType = SignedLong; 4376 PtrDiffType = SignedLong; 4377 } 4378 }; 4379 4380 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4381 public: 4382 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4383 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4384 LongDoubleWidth = 128; 4385 LongDoubleAlign = 128; 4386 SuitableAlign = 128; 4387 MaxVectorAlign = 256; 4388 // The watchOS simulator uses the builtin bool type for Objective-C. 4389 llvm::Triple T = llvm::Triple(Triple); 4390 if (T.isWatchOS()) 4391 UseSignedCharForObjCBool = false; 4392 SizeType = UnsignedLong; 4393 IntPtrType = SignedLong; 4394 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4395 HasAlignMac68kSupport = true; 4396 } 4397 4398 bool handleTargetFeatures(std::vector<std::string> &Features, 4399 DiagnosticsEngine &Diags) override { 4400 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4401 Diags)) 4402 return false; 4403 // We now know the features we have: we can decide how to align vectors. 4404 MaxVectorAlign = 4405 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4406 return true; 4407 } 4408 }; 4409 4410 // x86-32 Windows target 4411 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4412 public: 4413 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4414 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4415 WCharType = UnsignedShort; 4416 DoubleAlign = LongLongAlign = 64; 4417 bool IsWinCOFF = 4418 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4419 resetDataLayout(IsWinCOFF 4420 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4421 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4422 } 4423 void getTargetDefines(const LangOptions &Opts, 4424 MacroBuilder &Builder) const override { 4425 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4426 } 4427 }; 4428 4429 // x86-32 Windows Visual Studio target 4430 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4431 public: 4432 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4433 const TargetOptions &Opts) 4434 : WindowsX86_32TargetInfo(Triple, Opts) { 4435 LongDoubleWidth = LongDoubleAlign = 64; 4436 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4437 } 4438 void getTargetDefines(const LangOptions &Opts, 4439 MacroBuilder &Builder) const override { 4440 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4441 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4442 // The value of the following reflects processor type. 4443 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4444 // We lost the original triple, so we use the default. 4445 Builder.defineMacro("_M_IX86", "600"); 4446 } 4447 }; 4448 4449 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4450 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4451 // supports __declspec natively under -fms-extensions, but we define a no-op 4452 // __declspec macro anyway for pre-processor compatibility. 4453 if (Opts.MicrosoftExt) 4454 Builder.defineMacro("__declspec", "__declspec"); 4455 else 4456 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4457 4458 if (!Opts.MicrosoftExt) { 4459 // Provide macros for all the calling convention keywords. Provide both 4460 // single and double underscore prefixed variants. These are available on 4461 // x64 as well as x86, even though they have no effect. 4462 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4463 for (const char *CC : CCs) { 4464 std::string GCCSpelling = "__attribute__((__"; 4465 GCCSpelling += CC; 4466 GCCSpelling += "__))"; 4467 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4468 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4469 } 4470 } 4471 } 4472 4473 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4474 Builder.defineMacro("__MSVCRT__"); 4475 Builder.defineMacro("__MINGW32__"); 4476 addCygMingDefines(Opts, Builder); 4477 } 4478 4479 // x86-32 MinGW target 4480 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4481 public: 4482 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4483 : WindowsX86_32TargetInfo(Triple, Opts) {} 4484 void getTargetDefines(const LangOptions &Opts, 4485 MacroBuilder &Builder) const override { 4486 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4487 DefineStd(Builder, "WIN32", Opts); 4488 DefineStd(Builder, "WINNT", Opts); 4489 Builder.defineMacro("_X86_"); 4490 addMinGWDefines(Opts, Builder); 4491 } 4492 }; 4493 4494 // x86-32 Cygwin target 4495 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4496 public: 4497 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4498 : X86_32TargetInfo(Triple, Opts) { 4499 WCharType = UnsignedShort; 4500 DoubleAlign = LongLongAlign = 64; 4501 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4502 } 4503 void getTargetDefines(const LangOptions &Opts, 4504 MacroBuilder &Builder) const override { 4505 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4506 Builder.defineMacro("_X86_"); 4507 Builder.defineMacro("__CYGWIN__"); 4508 Builder.defineMacro("__CYGWIN32__"); 4509 addCygMingDefines(Opts, Builder); 4510 DefineStd(Builder, "unix", Opts); 4511 if (Opts.CPlusPlus) 4512 Builder.defineMacro("_GNU_SOURCE"); 4513 } 4514 }; 4515 4516 // x86-32 Haiku target 4517 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4518 public: 4519 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4520 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4521 } 4522 void getTargetDefines(const LangOptions &Opts, 4523 MacroBuilder &Builder) const override { 4524 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4525 Builder.defineMacro("__INTEL__"); 4526 } 4527 }; 4528 4529 // X86-32 MCU target 4530 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4531 public: 4532 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4533 : X86_32TargetInfo(Triple, Opts) { 4534 LongDoubleWidth = 64; 4535 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4536 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4537 WIntType = UnsignedInt; 4538 } 4539 4540 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4541 // On MCU we support only C calling convention. 4542 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4543 } 4544 4545 void getTargetDefines(const LangOptions &Opts, 4546 MacroBuilder &Builder) const override { 4547 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4548 Builder.defineMacro("__iamcu"); 4549 Builder.defineMacro("__iamcu__"); 4550 } 4551 4552 bool allowsLargerPreferedTypeAlignment() const override { 4553 return false; 4554 } 4555 }; 4556 4557 // RTEMS Target 4558 template<typename Target> 4559 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4560 protected: 4561 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4562 MacroBuilder &Builder) const override { 4563 // RTEMS defines; list based off of gcc output 4564 4565 Builder.defineMacro("__rtems__"); 4566 Builder.defineMacro("__ELF__"); 4567 } 4568 4569 public: 4570 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4571 : OSTargetInfo<Target>(Triple, Opts) { 4572 switch (Triple.getArch()) { 4573 default: 4574 case llvm::Triple::x86: 4575 // this->MCountName = ".mcount"; 4576 break; 4577 case llvm::Triple::mips: 4578 case llvm::Triple::mipsel: 4579 case llvm::Triple::ppc: 4580 case llvm::Triple::ppc64: 4581 case llvm::Triple::ppc64le: 4582 // this->MCountName = "_mcount"; 4583 break; 4584 case llvm::Triple::arm: 4585 // this->MCountName = "__mcount"; 4586 break; 4587 } 4588 } 4589 }; 4590 4591 // x86-32 RTEMS target 4592 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4593 public: 4594 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4595 : X86_32TargetInfo(Triple, Opts) { 4596 SizeType = UnsignedLong; 4597 IntPtrType = SignedLong; 4598 PtrDiffType = SignedLong; 4599 } 4600 void getTargetDefines(const LangOptions &Opts, 4601 MacroBuilder &Builder) const override { 4602 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4603 Builder.defineMacro("__INTEL__"); 4604 Builder.defineMacro("__rtems__"); 4605 } 4606 }; 4607 4608 // x86-64 generic target 4609 class X86_64TargetInfo : public X86TargetInfo { 4610 public: 4611 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4612 : X86TargetInfo(Triple, Opts) { 4613 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4614 bool IsWinCOFF = 4615 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4616 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4617 LongDoubleWidth = 128; 4618 LongDoubleAlign = 128; 4619 LargeArrayMinWidth = 128; 4620 LargeArrayAlign = 128; 4621 SuitableAlign = 128; 4622 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4623 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4624 IntPtrType = IsX32 ? SignedInt : SignedLong; 4625 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4626 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4627 RegParmMax = 6; 4628 4629 // Pointers are 32-bit in x32. 4630 resetDataLayout(IsX32 4631 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4632 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4633 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4634 4635 // Use fpret only for long double. 4636 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4637 4638 // Use fp2ret for _Complex long double. 4639 ComplexLongDoubleUsesFP2Ret = true; 4640 4641 // Make __builtin_ms_va_list available. 4642 HasBuiltinMSVaList = true; 4643 4644 // x86-64 has atomics up to 16 bytes. 4645 MaxAtomicPromoteWidth = 128; 4646 MaxAtomicInlineWidth = 128; 4647 } 4648 BuiltinVaListKind getBuiltinVaListKind() const override { 4649 return TargetInfo::X86_64ABIBuiltinVaList; 4650 } 4651 4652 int getEHDataRegisterNumber(unsigned RegNo) const override { 4653 if (RegNo == 0) return 0; 4654 if (RegNo == 1) return 1; 4655 return -1; 4656 } 4657 4658 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4659 switch (CC) { 4660 case CC_C: 4661 case CC_Swift: 4662 case CC_X86VectorCall: 4663 case CC_IntelOclBicc: 4664 case CC_X86_64Win64: 4665 case CC_PreserveMost: 4666 case CC_PreserveAll: 4667 case CC_X86RegCall: 4668 return CCCR_OK; 4669 default: 4670 return CCCR_Warning; 4671 } 4672 } 4673 4674 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4675 return CC_C; 4676 } 4677 4678 // for x32 we need it here explicitly 4679 bool hasInt128Type() const override { return true; } 4680 unsigned getUnwindWordWidth() const override { return 64; } 4681 unsigned getRegisterWidth() const override { return 64; } 4682 4683 bool validateGlobalRegisterVariable(StringRef RegName, 4684 unsigned RegSize, 4685 bool &HasSizeMismatch) const override { 4686 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4687 // handle. 4688 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4689 // Check that the register size is 64-bit. 4690 HasSizeMismatch = RegSize != 64; 4691 return true; 4692 } 4693 4694 // Check if the register is a 32-bit register the backend can handle. 4695 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4696 HasSizeMismatch); 4697 } 4698 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4699 return llvm::makeArrayRef(BuiltinInfoX86, 4700 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4701 } 4702 }; 4703 4704 // x86-64 Windows target 4705 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4706 public: 4707 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4708 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4709 WCharType = UnsignedShort; 4710 LongWidth = LongAlign = 32; 4711 DoubleAlign = LongLongAlign = 64; 4712 IntMaxType = SignedLongLong; 4713 Int64Type = SignedLongLong; 4714 SizeType = UnsignedLongLong; 4715 PtrDiffType = SignedLongLong; 4716 IntPtrType = SignedLongLong; 4717 } 4718 4719 void getTargetDefines(const LangOptions &Opts, 4720 MacroBuilder &Builder) const override { 4721 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4722 Builder.defineMacro("_WIN64"); 4723 } 4724 4725 BuiltinVaListKind getBuiltinVaListKind() const override { 4726 return TargetInfo::CharPtrBuiltinVaList; 4727 } 4728 4729 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4730 switch (CC) { 4731 case CC_X86StdCall: 4732 case CC_X86ThisCall: 4733 case CC_X86FastCall: 4734 return CCCR_Ignore; 4735 case CC_C: 4736 case CC_X86VectorCall: 4737 case CC_IntelOclBicc: 4738 case CC_X86_64SysV: 4739 case CC_Swift: 4740 case CC_X86RegCall: 4741 return CCCR_OK; 4742 default: 4743 return CCCR_Warning; 4744 } 4745 } 4746 }; 4747 4748 // x86-64 Windows Visual Studio target 4749 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4750 public: 4751 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4752 const TargetOptions &Opts) 4753 : WindowsX86_64TargetInfo(Triple, Opts) { 4754 LongDoubleWidth = LongDoubleAlign = 64; 4755 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4756 } 4757 void getTargetDefines(const LangOptions &Opts, 4758 MacroBuilder &Builder) const override { 4759 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4760 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4761 Builder.defineMacro("_M_X64", "100"); 4762 Builder.defineMacro("_M_AMD64", "100"); 4763 } 4764 }; 4765 4766 // x86-64 MinGW target 4767 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4768 public: 4769 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4770 : WindowsX86_64TargetInfo(Triple, Opts) { 4771 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4772 // with x86 FP ops. Weird. 4773 LongDoubleWidth = LongDoubleAlign = 128; 4774 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 4775 } 4776 4777 void getTargetDefines(const LangOptions &Opts, 4778 MacroBuilder &Builder) const override { 4779 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4780 DefineStd(Builder, "WIN64", Opts); 4781 Builder.defineMacro("__MINGW64__"); 4782 addMinGWDefines(Opts, Builder); 4783 4784 // GCC defines this macro when it is using __gxx_personality_seh0. 4785 if (!Opts.SjLjExceptions) 4786 Builder.defineMacro("__SEH__"); 4787 } 4788 }; 4789 4790 // x86-64 Cygwin target 4791 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4792 public: 4793 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4794 : X86_64TargetInfo(Triple, Opts) { 4795 TLSSupported = false; 4796 WCharType = UnsignedShort; 4797 } 4798 void getTargetDefines(const LangOptions &Opts, 4799 MacroBuilder &Builder) const override { 4800 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4801 Builder.defineMacro("__x86_64__"); 4802 Builder.defineMacro("__CYGWIN__"); 4803 Builder.defineMacro("__CYGWIN64__"); 4804 addCygMingDefines(Opts, Builder); 4805 DefineStd(Builder, "unix", Opts); 4806 if (Opts.CPlusPlus) 4807 Builder.defineMacro("_GNU_SOURCE"); 4808 4809 // GCC defines this macro when it is using __gxx_personality_seh0. 4810 if (!Opts.SjLjExceptions) 4811 Builder.defineMacro("__SEH__"); 4812 } 4813 }; 4814 4815 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4816 public: 4817 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4818 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4819 Int64Type = SignedLongLong; 4820 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4821 llvm::Triple T = llvm::Triple(Triple); 4822 if (T.isiOS()) 4823 UseSignedCharForObjCBool = false; 4824 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4825 } 4826 4827 bool handleTargetFeatures(std::vector<std::string> &Features, 4828 DiagnosticsEngine &Diags) override { 4829 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4830 Diags)) 4831 return false; 4832 // We now know the features we have: we can decide how to align vectors. 4833 MaxVectorAlign = 4834 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4835 return true; 4836 } 4837 }; 4838 4839 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4840 public: 4841 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4842 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4843 IntMaxType = SignedLongLong; 4844 Int64Type = SignedLongLong; 4845 } 4846 }; 4847 4848 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4849 public: 4850 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4851 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4852 IntMaxType = SignedLongLong; 4853 Int64Type = SignedLongLong; 4854 } 4855 }; 4856 4857 class ARMTargetInfo : public TargetInfo { 4858 // Possible FPU choices. 4859 enum FPUMode { 4860 VFP2FPU = (1 << 0), 4861 VFP3FPU = (1 << 1), 4862 VFP4FPU = (1 << 2), 4863 NeonFPU = (1 << 3), 4864 FPARMV8 = (1 << 4) 4865 }; 4866 4867 // Possible HWDiv features. 4868 enum HWDivMode { 4869 HWDivThumb = (1 << 0), 4870 HWDivARM = (1 << 1) 4871 }; 4872 4873 static bool FPUModeIsVFP(FPUMode Mode) { 4874 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4875 } 4876 4877 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4878 static const char * const GCCRegNames[]; 4879 4880 std::string ABI, CPU; 4881 4882 StringRef CPUProfile; 4883 StringRef CPUAttr; 4884 4885 enum { 4886 FP_Default, 4887 FP_VFP, 4888 FP_Neon 4889 } FPMath; 4890 4891 unsigned ArchISA; 4892 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4893 unsigned ArchProfile; 4894 unsigned ArchVersion; 4895 4896 unsigned FPU : 5; 4897 4898 unsigned IsAAPCS : 1; 4899 unsigned HWDiv : 2; 4900 4901 // Initialized via features. 4902 unsigned SoftFloat : 1; 4903 unsigned SoftFloatABI : 1; 4904 4905 unsigned CRC : 1; 4906 unsigned Crypto : 1; 4907 unsigned DSP : 1; 4908 unsigned Unaligned : 1; 4909 4910 enum { 4911 LDREX_B = (1 << 0), /// byte (8-bit) 4912 LDREX_H = (1 << 1), /// half (16-bit) 4913 LDREX_W = (1 << 2), /// word (32-bit) 4914 LDREX_D = (1 << 3), /// double (64-bit) 4915 }; 4916 4917 uint32_t LDREX; 4918 4919 // ACLE 6.5.1 Hardware floating point 4920 enum { 4921 HW_FP_HP = (1 << 1), /// half (16-bit) 4922 HW_FP_SP = (1 << 2), /// single (32-bit) 4923 HW_FP_DP = (1 << 3), /// double (64-bit) 4924 }; 4925 uint32_t HW_FP; 4926 4927 static const Builtin::Info BuiltinInfo[]; 4928 4929 void setABIAAPCS() { 4930 IsAAPCS = true; 4931 4932 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4933 const llvm::Triple &T = getTriple(); 4934 4935 // size_t is unsigned long on MachO-derived environments, NetBSD, 4936 // OpenBSD and Bitrig. 4937 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4938 T.getOS() == llvm::Triple::OpenBSD || 4939 T.getOS() == llvm::Triple::Bitrig) 4940 SizeType = UnsignedLong; 4941 else 4942 SizeType = UnsignedInt; 4943 4944 switch (T.getOS()) { 4945 case llvm::Triple::NetBSD: 4946 case llvm::Triple::OpenBSD: 4947 WCharType = SignedInt; 4948 break; 4949 case llvm::Triple::Win32: 4950 WCharType = UnsignedShort; 4951 break; 4952 case llvm::Triple::Linux: 4953 default: 4954 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4955 WCharType = UnsignedInt; 4956 break; 4957 } 4958 4959 UseBitFieldTypeAlignment = true; 4960 4961 ZeroLengthBitfieldBoundary = 0; 4962 4963 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4964 // so set preferred for small types to 32. 4965 if (T.isOSBinFormatMachO()) { 4966 resetDataLayout(BigEndian 4967 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4968 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4969 } else if (T.isOSWindows()) { 4970 assert(!BigEndian && "Windows on ARM does not support big endian"); 4971 resetDataLayout("e" 4972 "-m:w" 4973 "-p:32:32" 4974 "-i64:64" 4975 "-v128:64:128" 4976 "-a:0:32" 4977 "-n32" 4978 "-S64"); 4979 } else if (T.isOSNaCl()) { 4980 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4981 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4982 } else { 4983 resetDataLayout(BigEndian 4984 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4985 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4986 } 4987 4988 // FIXME: Enumerated types are variable width in straight AAPCS. 4989 } 4990 4991 void setABIAPCS(bool IsAAPCS16) { 4992 const llvm::Triple &T = getTriple(); 4993 4994 IsAAPCS = false; 4995 4996 if (IsAAPCS16) 4997 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4998 else 4999 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 5000 5001 // size_t is unsigned int on FreeBSD. 5002 if (T.getOS() == llvm::Triple::FreeBSD) 5003 SizeType = UnsignedInt; 5004 else 5005 SizeType = UnsignedLong; 5006 5007 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 5008 WCharType = SignedInt; 5009 5010 // Do not respect the alignment of bit-field types when laying out 5011 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 5012 UseBitFieldTypeAlignment = false; 5013 5014 /// gcc forces the alignment to 4 bytes, regardless of the type of the 5015 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 5016 /// gcc. 5017 ZeroLengthBitfieldBoundary = 32; 5018 5019 if (T.isOSBinFormatMachO() && IsAAPCS16) { 5020 assert(!BigEndian && "AAPCS16 does not support big-endian"); 5021 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 5022 } else if (T.isOSBinFormatMachO()) 5023 resetDataLayout( 5024 BigEndian 5025 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5026 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5027 else 5028 resetDataLayout( 5029 BigEndian 5030 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5031 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5032 5033 // FIXME: Override "preferred align" for double and long long. 5034 } 5035 5036 void setArchInfo() { 5037 StringRef ArchName = getTriple().getArchName(); 5038 5039 ArchISA = llvm::ARM::parseArchISA(ArchName); 5040 CPU = llvm::ARM::getDefaultCPU(ArchName); 5041 unsigned AK = llvm::ARM::parseArch(ArchName); 5042 if (AK != llvm::ARM::AK_INVALID) 5043 ArchKind = AK; 5044 setArchInfo(ArchKind); 5045 } 5046 5047 void setArchInfo(unsigned Kind) { 5048 StringRef SubArch; 5049 5050 // cache TargetParser info 5051 ArchKind = Kind; 5052 SubArch = llvm::ARM::getSubArch(ArchKind); 5053 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5054 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5055 5056 // cache CPU related strings 5057 CPUAttr = getCPUAttr(); 5058 CPUProfile = getCPUProfile(); 5059 } 5060 5061 void setAtomic() { 5062 // when triple does not specify a sub arch, 5063 // then we are not using inline atomics 5064 bool ShouldUseInlineAtomic = 5065 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5066 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5067 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5068 if (ArchProfile == llvm::ARM::PK_M) { 5069 MaxAtomicPromoteWidth = 32; 5070 if (ShouldUseInlineAtomic) 5071 MaxAtomicInlineWidth = 32; 5072 } 5073 else { 5074 MaxAtomicPromoteWidth = 64; 5075 if (ShouldUseInlineAtomic) 5076 MaxAtomicInlineWidth = 64; 5077 } 5078 } 5079 5080 bool isThumb() const { 5081 return (ArchISA == llvm::ARM::IK_THUMB); 5082 } 5083 5084 bool supportsThumb() const { 5085 return CPUAttr.count('T') || ArchVersion >= 6; 5086 } 5087 5088 bool supportsThumb2() const { 5089 return CPUAttr.equals("6T2") || 5090 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5091 } 5092 5093 StringRef getCPUAttr() const { 5094 // For most sub-arches, the build attribute CPU name is enough. 5095 // For Cortex variants, it's slightly different. 5096 switch(ArchKind) { 5097 default: 5098 return llvm::ARM::getCPUAttr(ArchKind); 5099 case llvm::ARM::AK_ARMV6M: 5100 return "6M"; 5101 case llvm::ARM::AK_ARMV7S: 5102 return "7S"; 5103 case llvm::ARM::AK_ARMV7A: 5104 return "7A"; 5105 case llvm::ARM::AK_ARMV7R: 5106 return "7R"; 5107 case llvm::ARM::AK_ARMV7M: 5108 return "7M"; 5109 case llvm::ARM::AK_ARMV7EM: 5110 return "7EM"; 5111 case llvm::ARM::AK_ARMV7VE: 5112 return "7VE"; 5113 case llvm::ARM::AK_ARMV8A: 5114 return "8A"; 5115 case llvm::ARM::AK_ARMV8_1A: 5116 return "8_1A"; 5117 case llvm::ARM::AK_ARMV8_2A: 5118 return "8_2A"; 5119 case llvm::ARM::AK_ARMV8MBaseline: 5120 return "8M_BASE"; 5121 case llvm::ARM::AK_ARMV8MMainline: 5122 return "8M_MAIN"; 5123 case llvm::ARM::AK_ARMV8R: 5124 return "8R"; 5125 } 5126 } 5127 5128 StringRef getCPUProfile() const { 5129 switch(ArchProfile) { 5130 case llvm::ARM::PK_A: 5131 return "A"; 5132 case llvm::ARM::PK_R: 5133 return "R"; 5134 case llvm::ARM::PK_M: 5135 return "M"; 5136 default: 5137 return ""; 5138 } 5139 } 5140 5141 public: 5142 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5143 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5144 HW_FP(0) { 5145 5146 switch (getTriple().getOS()) { 5147 case llvm::Triple::NetBSD: 5148 case llvm::Triple::OpenBSD: 5149 PtrDiffType = SignedLong; 5150 break; 5151 default: 5152 PtrDiffType = SignedInt; 5153 break; 5154 } 5155 5156 // Cache arch related info. 5157 setArchInfo(); 5158 5159 // {} in inline assembly are neon specifiers, not assembly variant 5160 // specifiers. 5161 NoAsmVariants = true; 5162 5163 // FIXME: This duplicates code from the driver that sets the -target-abi 5164 // option - this code is used if -target-abi isn't passed and should 5165 // be unified in some way. 5166 if (Triple.isOSBinFormatMachO()) { 5167 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5168 // the frontend matches that. 5169 if (Triple.getEnvironment() == llvm::Triple::EABI || 5170 Triple.getOS() == llvm::Triple::UnknownOS || 5171 ArchProfile == llvm::ARM::PK_M) { 5172 setABI("aapcs"); 5173 } else if (Triple.isWatchABI()) { 5174 setABI("aapcs16"); 5175 } else { 5176 setABI("apcs-gnu"); 5177 } 5178 } else if (Triple.isOSWindows()) { 5179 // FIXME: this is invalid for WindowsCE 5180 setABI("aapcs"); 5181 } else { 5182 // Select the default based on the platform. 5183 switch (Triple.getEnvironment()) { 5184 case llvm::Triple::Android: 5185 case llvm::Triple::GNUEABI: 5186 case llvm::Triple::GNUEABIHF: 5187 case llvm::Triple::MuslEABI: 5188 case llvm::Triple::MuslEABIHF: 5189 setABI("aapcs-linux"); 5190 break; 5191 case llvm::Triple::EABIHF: 5192 case llvm::Triple::EABI: 5193 setABI("aapcs"); 5194 break; 5195 case llvm::Triple::GNU: 5196 setABI("apcs-gnu"); 5197 break; 5198 default: 5199 if (Triple.getOS() == llvm::Triple::NetBSD) 5200 setABI("apcs-gnu"); 5201 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5202 setABI("aapcs-linux"); 5203 else 5204 setABI("aapcs"); 5205 break; 5206 } 5207 } 5208 5209 // ARM targets default to using the ARM C++ ABI. 5210 TheCXXABI.set(TargetCXXABI::GenericARM); 5211 5212 // ARM has atomics up to 8 bytes 5213 setAtomic(); 5214 5215 // Do force alignment of members that follow zero length bitfields. If 5216 // the alignment of the zero-length bitfield is greater than the member 5217 // that follows it, `bar', `bar' will be aligned as the type of the 5218 // zero length bitfield. 5219 UseZeroLengthBitfieldAlignment = true; 5220 5221 if (Triple.getOS() == llvm::Triple::Linux || 5222 Triple.getOS() == llvm::Triple::UnknownOS) 5223 this->MCountName = 5224 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5225 } 5226 5227 StringRef getABI() const override { return ABI; } 5228 5229 bool setABI(const std::string &Name) override { 5230 ABI = Name; 5231 5232 // The defaults (above) are for AAPCS, check if we need to change them. 5233 // 5234 // FIXME: We need support for -meabi... we could just mangle it into the 5235 // name. 5236 if (Name == "apcs-gnu" || Name == "aapcs16") { 5237 setABIAPCS(Name == "aapcs16"); 5238 return true; 5239 } 5240 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5241 setABIAAPCS(); 5242 return true; 5243 } 5244 return false; 5245 } 5246 5247 // FIXME: This should be based on Arch attributes, not CPU names. 5248 bool 5249 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5250 StringRef CPU, 5251 const std::vector<std::string> &FeaturesVec) const override { 5252 5253 std::vector<StringRef> TargetFeatures; 5254 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5255 5256 // get default FPU features 5257 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5258 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5259 5260 // get default Extension features 5261 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5262 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5263 5264 for (auto Feature : TargetFeatures) 5265 if (Feature[0] == '+') 5266 Features[Feature.drop_front(1)] = true; 5267 5268 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5269 } 5270 5271 bool handleTargetFeatures(std::vector<std::string> &Features, 5272 DiagnosticsEngine &Diags) override { 5273 FPU = 0; 5274 CRC = 0; 5275 Crypto = 0; 5276 DSP = 0; 5277 Unaligned = 1; 5278 SoftFloat = SoftFloatABI = false; 5279 HWDiv = 0; 5280 5281 // This does not diagnose illegal cases like having both 5282 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5283 uint32_t HW_FP_remove = 0; 5284 for (const auto &Feature : Features) { 5285 if (Feature == "+soft-float") { 5286 SoftFloat = true; 5287 } else if (Feature == "+soft-float-abi") { 5288 SoftFloatABI = true; 5289 } else if (Feature == "+vfp2") { 5290 FPU |= VFP2FPU; 5291 HW_FP |= HW_FP_SP | HW_FP_DP; 5292 } else if (Feature == "+vfp3") { 5293 FPU |= VFP3FPU; 5294 HW_FP |= HW_FP_SP | HW_FP_DP; 5295 } else if (Feature == "+vfp4") { 5296 FPU |= VFP4FPU; 5297 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5298 } else if (Feature == "+fp-armv8") { 5299 FPU |= FPARMV8; 5300 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5301 } else if (Feature == "+neon") { 5302 FPU |= NeonFPU; 5303 HW_FP |= HW_FP_SP | HW_FP_DP; 5304 } else if (Feature == "+hwdiv") { 5305 HWDiv |= HWDivThumb; 5306 } else if (Feature == "+hwdiv-arm") { 5307 HWDiv |= HWDivARM; 5308 } else if (Feature == "+crc") { 5309 CRC = 1; 5310 } else if (Feature == "+crypto") { 5311 Crypto = 1; 5312 } else if (Feature == "+dsp") { 5313 DSP = 1; 5314 } else if (Feature == "+fp-only-sp") { 5315 HW_FP_remove |= HW_FP_DP; 5316 } else if (Feature == "+strict-align") { 5317 Unaligned = 0; 5318 } else if (Feature == "+fp16") { 5319 HW_FP |= HW_FP_HP; 5320 } 5321 } 5322 HW_FP &= ~HW_FP_remove; 5323 5324 switch (ArchVersion) { 5325 case 6: 5326 if (ArchProfile == llvm::ARM::PK_M) 5327 LDREX = 0; 5328 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5329 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5330 else 5331 LDREX = LDREX_W; 5332 break; 5333 case 7: 5334 if (ArchProfile == llvm::ARM::PK_M) 5335 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5336 else 5337 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5338 break; 5339 case 8: 5340 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5341 } 5342 5343 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5344 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5345 return false; 5346 } 5347 5348 if (FPMath == FP_Neon) 5349 Features.push_back("+neonfp"); 5350 else if (FPMath == FP_VFP) 5351 Features.push_back("-neonfp"); 5352 5353 // Remove front-end specific options which the backend handles differently. 5354 auto Feature = 5355 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5356 if (Feature != Features.end()) 5357 Features.erase(Feature); 5358 5359 return true; 5360 } 5361 5362 bool hasFeature(StringRef Feature) const override { 5363 return llvm::StringSwitch<bool>(Feature) 5364 .Case("arm", true) 5365 .Case("aarch32", true) 5366 .Case("softfloat", SoftFloat) 5367 .Case("thumb", isThumb()) 5368 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5369 .Case("hwdiv", HWDiv & HWDivThumb) 5370 .Case("hwdiv-arm", HWDiv & HWDivARM) 5371 .Default(false); 5372 } 5373 5374 bool setCPU(const std::string &Name) override { 5375 if (Name != "generic") 5376 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5377 5378 if (ArchKind == llvm::ARM::AK_INVALID) 5379 return false; 5380 setAtomic(); 5381 CPU = Name; 5382 return true; 5383 } 5384 5385 bool setFPMath(StringRef Name) override; 5386 5387 void getTargetDefines(const LangOptions &Opts, 5388 MacroBuilder &Builder) const override { 5389 // Target identification. 5390 Builder.defineMacro("__arm"); 5391 Builder.defineMacro("__arm__"); 5392 // For bare-metal none-eabi. 5393 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5394 getTriple().getEnvironment() == llvm::Triple::EABI) 5395 Builder.defineMacro("__ELF__"); 5396 5397 // Target properties. 5398 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5399 5400 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5401 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5402 if (getTriple().isWatchABI()) 5403 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5404 5405 if (!CPUAttr.empty()) 5406 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5407 5408 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5409 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5410 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5411 5412 if (ArchVersion >= 8) { 5413 // ACLE 6.5.7 Crypto Extension 5414 if (Crypto) 5415 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5416 // ACLE 6.5.8 CRC32 Extension 5417 if (CRC) 5418 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5419 // ACLE 6.5.10 Numeric Maximum and Minimum 5420 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5421 // ACLE 6.5.9 Directed Rounding 5422 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5423 } 5424 5425 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5426 // is not defined for the M-profile. 5427 // NOTE that the default profile is assumed to be 'A' 5428 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5429 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5430 5431 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5432 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5433 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5434 // v7 and v8 architectures excluding v8-M Baseline. 5435 if (supportsThumb2()) 5436 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5437 else if (supportsThumb()) 5438 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5439 5440 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5441 // instruction set such as ARM or Thumb. 5442 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5443 5444 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5445 5446 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5447 if (!CPUProfile.empty()) 5448 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5449 5450 // ACLE 6.4.3 Unaligned access supported in hardware 5451 if (Unaligned) 5452 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5453 5454 // ACLE 6.4.4 LDREX/STREX 5455 if (LDREX) 5456 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5457 5458 // ACLE 6.4.5 CLZ 5459 if (ArchVersion == 5 || 5460 (ArchVersion == 6 && CPUProfile != "M") || 5461 ArchVersion > 6) 5462 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5463 5464 // ACLE 6.5.1 Hardware Floating Point 5465 if (HW_FP) 5466 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5467 5468 // ACLE predefines. 5469 Builder.defineMacro("__ARM_ACLE", "200"); 5470 5471 // FP16 support (we currently only support IEEE format). 5472 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5473 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5474 5475 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5476 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5477 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5478 5479 // Subtarget options. 5480 5481 // FIXME: It's more complicated than this and we don't really support 5482 // interworking. 5483 // Windows on ARM does not "support" interworking 5484 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5485 Builder.defineMacro("__THUMB_INTERWORK__"); 5486 5487 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5488 // Embedded targets on Darwin follow AAPCS, but not EABI. 5489 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5490 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5491 Builder.defineMacro("__ARM_EABI__"); 5492 Builder.defineMacro("__ARM_PCS", "1"); 5493 } 5494 5495 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5496 ABI == "aapcs16") 5497 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5498 5499 if (SoftFloat) 5500 Builder.defineMacro("__SOFTFP__"); 5501 5502 if (ArchKind == llvm::ARM::AK_XSCALE) 5503 Builder.defineMacro("__XSCALE__"); 5504 5505 if (isThumb()) { 5506 Builder.defineMacro("__THUMBEL__"); 5507 Builder.defineMacro("__thumb__"); 5508 if (supportsThumb2()) 5509 Builder.defineMacro("__thumb2__"); 5510 } 5511 5512 // ACLE 6.4.9 32-bit SIMD instructions 5513 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5514 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5515 5516 // ACLE 6.4.10 Hardware Integer Divide 5517 if (((HWDiv & HWDivThumb) && isThumb()) || 5518 ((HWDiv & HWDivARM) && !isThumb())) { 5519 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5520 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5521 } 5522 5523 // Note, this is always on in gcc, even though it doesn't make sense. 5524 Builder.defineMacro("__APCS_32__"); 5525 5526 if (FPUModeIsVFP((FPUMode) FPU)) { 5527 Builder.defineMacro("__VFP_FP__"); 5528 if (FPU & VFP2FPU) 5529 Builder.defineMacro("__ARM_VFPV2__"); 5530 if (FPU & VFP3FPU) 5531 Builder.defineMacro("__ARM_VFPV3__"); 5532 if (FPU & VFP4FPU) 5533 Builder.defineMacro("__ARM_VFPV4__"); 5534 if (FPU & FPARMV8) 5535 Builder.defineMacro("__ARM_FPV5__"); 5536 } 5537 5538 // This only gets set when Neon instructions are actually available, unlike 5539 // the VFP define, hence the soft float and arch check. This is subtly 5540 // different from gcc, we follow the intent which was that it should be set 5541 // when Neon instructions are actually available. 5542 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5543 Builder.defineMacro("__ARM_NEON", "1"); 5544 Builder.defineMacro("__ARM_NEON__"); 5545 // current AArch32 NEON implementations do not support double-precision 5546 // floating-point even when it is present in VFP. 5547 Builder.defineMacro("__ARM_NEON_FP", 5548 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5549 } 5550 5551 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5552 Opts.ShortWChar ? "2" : "4"); 5553 5554 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5555 Opts.ShortEnums ? "1" : "4"); 5556 5557 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5558 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5559 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5560 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5561 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5562 } 5563 5564 // ACLE 6.4.7 DSP instructions 5565 if (DSP) { 5566 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5567 } 5568 5569 // ACLE 6.4.8 Saturation instructions 5570 bool SAT = false; 5571 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5572 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5573 SAT = true; 5574 } 5575 5576 // ACLE 6.4.6 Q (saturation) flag 5577 if (DSP || SAT) 5578 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5579 5580 if (Opts.UnsafeFPMath) 5581 Builder.defineMacro("__ARM_FP_FAST", "1"); 5582 5583 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5584 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5585 } 5586 5587 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5588 return llvm::makeArrayRef(BuiltinInfo, 5589 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5590 } 5591 bool isCLZForZeroUndef() const override { return false; } 5592 BuiltinVaListKind getBuiltinVaListKind() const override { 5593 return IsAAPCS 5594 ? AAPCSABIBuiltinVaList 5595 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5596 : TargetInfo::VoidPtrBuiltinVaList); 5597 } 5598 ArrayRef<const char *> getGCCRegNames() const override; 5599 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5600 bool validateAsmConstraint(const char *&Name, 5601 TargetInfo::ConstraintInfo &Info) const override { 5602 switch (*Name) { 5603 default: break; 5604 case 'l': // r0-r7 5605 case 'h': // r8-r15 5606 case 't': // VFP Floating point register single precision 5607 case 'w': // VFP Floating point register double precision 5608 Info.setAllowsRegister(); 5609 return true; 5610 case 'I': 5611 case 'J': 5612 case 'K': 5613 case 'L': 5614 case 'M': 5615 // FIXME 5616 return true; 5617 case 'Q': // A memory address that is a single base register. 5618 Info.setAllowsMemory(); 5619 return true; 5620 case 'U': // a memory reference... 5621 switch (Name[1]) { 5622 case 'q': // ...ARMV4 ldrsb 5623 case 'v': // ...VFP load/store (reg+constant offset) 5624 case 'y': // ...iWMMXt load/store 5625 case 't': // address valid for load/store opaque types wider 5626 // than 128-bits 5627 case 'n': // valid address for Neon doubleword vector load/store 5628 case 'm': // valid address for Neon element and structure load/store 5629 case 's': // valid address for non-offset loads/stores of quad-word 5630 // values in four ARM registers 5631 Info.setAllowsMemory(); 5632 Name++; 5633 return true; 5634 } 5635 } 5636 return false; 5637 } 5638 std::string convertConstraint(const char *&Constraint) const override { 5639 std::string R; 5640 switch (*Constraint) { 5641 case 'U': // Two-character constraint; add "^" hint for later parsing. 5642 R = std::string("^") + std::string(Constraint, 2); 5643 Constraint++; 5644 break; 5645 case 'p': // 'p' should be translated to 'r' by default. 5646 R = std::string("r"); 5647 break; 5648 default: 5649 return std::string(1, *Constraint); 5650 } 5651 return R; 5652 } 5653 bool 5654 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5655 std::string &SuggestedModifier) const override { 5656 bool isOutput = (Constraint[0] == '='); 5657 bool isInOut = (Constraint[0] == '+'); 5658 5659 // Strip off constraint modifiers. 5660 while (Constraint[0] == '=' || 5661 Constraint[0] == '+' || 5662 Constraint[0] == '&') 5663 Constraint = Constraint.substr(1); 5664 5665 switch (Constraint[0]) { 5666 default: break; 5667 case 'r': { 5668 switch (Modifier) { 5669 default: 5670 return (isInOut || isOutput || Size <= 64); 5671 case 'q': 5672 // A register of size 32 cannot fit a vector type. 5673 return false; 5674 } 5675 } 5676 } 5677 5678 return true; 5679 } 5680 const char *getClobbers() const override { 5681 // FIXME: Is this really right? 5682 return ""; 5683 } 5684 5685 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5686 switch (CC) { 5687 case CC_AAPCS: 5688 case CC_AAPCS_VFP: 5689 case CC_Swift: 5690 return CCCR_OK; 5691 default: 5692 return CCCR_Warning; 5693 } 5694 } 5695 5696 int getEHDataRegisterNumber(unsigned RegNo) const override { 5697 if (RegNo == 0) return 0; 5698 if (RegNo == 1) return 1; 5699 return -1; 5700 } 5701 5702 bool hasSjLjLowering() const override { 5703 return true; 5704 } 5705 }; 5706 5707 bool ARMTargetInfo::setFPMath(StringRef Name) { 5708 if (Name == "neon") { 5709 FPMath = FP_Neon; 5710 return true; 5711 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5712 Name == "vfp4") { 5713 FPMath = FP_VFP; 5714 return true; 5715 } 5716 return false; 5717 } 5718 5719 const char * const ARMTargetInfo::GCCRegNames[] = { 5720 // Integer registers 5721 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5722 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5723 5724 // Float registers 5725 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5726 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5727 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5728 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5729 5730 // Double registers 5731 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5732 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5733 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5734 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5735 5736 // Quad registers 5737 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5738 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5739 }; 5740 5741 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5742 return llvm::makeArrayRef(GCCRegNames); 5743 } 5744 5745 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5746 { { "a1" }, "r0" }, 5747 { { "a2" }, "r1" }, 5748 { { "a3" }, "r2" }, 5749 { { "a4" }, "r3" }, 5750 { { "v1" }, "r4" }, 5751 { { "v2" }, "r5" }, 5752 { { "v3" }, "r6" }, 5753 { { "v4" }, "r7" }, 5754 { { "v5" }, "r8" }, 5755 { { "v6", "rfp" }, "r9" }, 5756 { { "sl" }, "r10" }, 5757 { { "fp" }, "r11" }, 5758 { { "ip" }, "r12" }, 5759 { { "r13" }, "sp" }, 5760 { { "r14" }, "lr" }, 5761 { { "r15" }, "pc" }, 5762 // The S, D and Q registers overlap, but aren't really aliases; we 5763 // don't want to substitute one of these for a different-sized one. 5764 }; 5765 5766 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5767 return llvm::makeArrayRef(GCCRegAliases); 5768 } 5769 5770 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5771 #define BUILTIN(ID, TYPE, ATTRS) \ 5772 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5773 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5774 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5775 #include "clang/Basic/BuiltinsNEON.def" 5776 5777 #define BUILTIN(ID, TYPE, ATTRS) \ 5778 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5779 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5780 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5781 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5782 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5783 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5784 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5785 #include "clang/Basic/BuiltinsARM.def" 5786 }; 5787 5788 class ARMleTargetInfo : public ARMTargetInfo { 5789 public: 5790 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5791 : ARMTargetInfo(Triple, Opts) {} 5792 void getTargetDefines(const LangOptions &Opts, 5793 MacroBuilder &Builder) const override { 5794 Builder.defineMacro("__ARMEL__"); 5795 ARMTargetInfo::getTargetDefines(Opts, Builder); 5796 } 5797 }; 5798 5799 class ARMbeTargetInfo : public ARMTargetInfo { 5800 public: 5801 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5802 : ARMTargetInfo(Triple, Opts) {} 5803 void getTargetDefines(const LangOptions &Opts, 5804 MacroBuilder &Builder) const override { 5805 Builder.defineMacro("__ARMEB__"); 5806 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5807 ARMTargetInfo::getTargetDefines(Opts, Builder); 5808 } 5809 }; 5810 5811 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5812 const llvm::Triple Triple; 5813 public: 5814 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5815 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5816 WCharType = UnsignedShort; 5817 SizeType = UnsignedInt; 5818 } 5819 void getVisualStudioDefines(const LangOptions &Opts, 5820 MacroBuilder &Builder) const { 5821 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5822 5823 // FIXME: this is invalid for WindowsCE 5824 Builder.defineMacro("_M_ARM_NT", "1"); 5825 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5826 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5827 5828 assert((Triple.getArch() == llvm::Triple::arm || 5829 Triple.getArch() == llvm::Triple::thumb) && 5830 "invalid architecture for Windows ARM target info"); 5831 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5832 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5833 5834 // TODO map the complete set of values 5835 // 31: VFPv3 40: VFPv4 5836 Builder.defineMacro("_M_ARM_FP", "31"); 5837 } 5838 BuiltinVaListKind getBuiltinVaListKind() const override { 5839 return TargetInfo::CharPtrBuiltinVaList; 5840 } 5841 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5842 switch (CC) { 5843 case CC_X86StdCall: 5844 case CC_X86ThisCall: 5845 case CC_X86FastCall: 5846 case CC_X86VectorCall: 5847 return CCCR_Ignore; 5848 case CC_C: 5849 return CCCR_OK; 5850 default: 5851 return CCCR_Warning; 5852 } 5853 } 5854 }; 5855 5856 // Windows ARM + Itanium C++ ABI Target 5857 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5858 public: 5859 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5860 const TargetOptions &Opts) 5861 : WindowsARMTargetInfo(Triple, Opts) { 5862 TheCXXABI.set(TargetCXXABI::GenericARM); 5863 } 5864 5865 void getTargetDefines(const LangOptions &Opts, 5866 MacroBuilder &Builder) const override { 5867 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5868 5869 if (Opts.MSVCCompat) 5870 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5871 } 5872 }; 5873 5874 // Windows ARM, MS (C++) ABI 5875 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5876 public: 5877 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5878 const TargetOptions &Opts) 5879 : WindowsARMTargetInfo(Triple, Opts) { 5880 TheCXXABI.set(TargetCXXABI::Microsoft); 5881 } 5882 5883 void getTargetDefines(const LangOptions &Opts, 5884 MacroBuilder &Builder) const override { 5885 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5886 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5887 } 5888 }; 5889 5890 // ARM MinGW target 5891 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5892 public: 5893 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5894 : WindowsARMTargetInfo(Triple, Opts) { 5895 TheCXXABI.set(TargetCXXABI::GenericARM); 5896 } 5897 5898 void getTargetDefines(const LangOptions &Opts, 5899 MacroBuilder &Builder) const override { 5900 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5901 DefineStd(Builder, "WIN32", Opts); 5902 DefineStd(Builder, "WINNT", Opts); 5903 Builder.defineMacro("_ARM_"); 5904 addMinGWDefines(Opts, Builder); 5905 } 5906 }; 5907 5908 // ARM Cygwin target 5909 class CygwinARMTargetInfo : public ARMleTargetInfo { 5910 public: 5911 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5912 : ARMleTargetInfo(Triple, Opts) { 5913 TLSSupported = false; 5914 WCharType = UnsignedShort; 5915 DoubleAlign = LongLongAlign = 64; 5916 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5917 } 5918 void getTargetDefines(const LangOptions &Opts, 5919 MacroBuilder &Builder) const override { 5920 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5921 Builder.defineMacro("_ARM_"); 5922 Builder.defineMacro("__CYGWIN__"); 5923 Builder.defineMacro("__CYGWIN32__"); 5924 DefineStd(Builder, "unix", Opts); 5925 if (Opts.CPlusPlus) 5926 Builder.defineMacro("_GNU_SOURCE"); 5927 } 5928 }; 5929 5930 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5931 protected: 5932 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5933 MacroBuilder &Builder) const override { 5934 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5935 } 5936 5937 public: 5938 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5939 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5940 HasAlignMac68kSupport = true; 5941 // iOS always has 64-bit atomic instructions. 5942 // FIXME: This should be based off of the target features in 5943 // ARMleTargetInfo. 5944 MaxAtomicInlineWidth = 64; 5945 5946 if (Triple.isWatchABI()) { 5947 // Darwin on iOS uses a variant of the ARM C++ ABI. 5948 TheCXXABI.set(TargetCXXABI::WatchOS); 5949 5950 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5951 // size_t is long, it's a bit weird for it to be int. 5952 PtrDiffType = SignedLong; 5953 5954 // BOOL should be a real boolean on the new ABI 5955 UseSignedCharForObjCBool = false; 5956 } else 5957 TheCXXABI.set(TargetCXXABI::iOS); 5958 } 5959 }; 5960 5961 class AArch64TargetInfo : public TargetInfo { 5962 virtual void setDataLayout() = 0; 5963 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5964 static const char *const GCCRegNames[]; 5965 5966 enum FPUModeEnum { 5967 FPUMode, 5968 NeonMode 5969 }; 5970 5971 unsigned FPU; 5972 unsigned CRC; 5973 unsigned Crypto; 5974 unsigned Unaligned; 5975 unsigned V8_1A; 5976 5977 static const Builtin::Info BuiltinInfo[]; 5978 5979 std::string ABI; 5980 5981 public: 5982 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5983 : TargetInfo(Triple), ABI("aapcs") { 5984 if (getTriple().getOS() == llvm::Triple::NetBSD || 5985 getTriple().getOS() == llvm::Triple::OpenBSD) { 5986 WCharType = SignedInt; 5987 5988 // NetBSD apparently prefers consistency across ARM targets to consistency 5989 // across 64-bit targets. 5990 Int64Type = SignedLongLong; 5991 IntMaxType = SignedLongLong; 5992 } else { 5993 WCharType = UnsignedInt; 5994 Int64Type = SignedLong; 5995 IntMaxType = SignedLong; 5996 } 5997 5998 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5999 MaxVectorAlign = 128; 6000 MaxAtomicInlineWidth = 128; 6001 MaxAtomicPromoteWidth = 128; 6002 6003 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 6004 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6005 6006 // {} in inline assembly are neon specifiers, not assembly variant 6007 // specifiers. 6008 NoAsmVariants = true; 6009 6010 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 6011 // contributes to the alignment of the containing aggregate in the same way 6012 // a plain (non bit-field) member of that type would, without exception for 6013 // zero-sized or anonymous bit-fields." 6014 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 6015 UseZeroLengthBitfieldAlignment = true; 6016 6017 // AArch64 targets default to using the ARM C++ ABI. 6018 TheCXXABI.set(TargetCXXABI::GenericAArch64); 6019 6020 if (Triple.getOS() == llvm::Triple::Linux) 6021 this->MCountName = "\01_mcount"; 6022 else if (Triple.getOS() == llvm::Triple::UnknownOS) 6023 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 6024 } 6025 6026 StringRef getABI() const override { return ABI; } 6027 bool setABI(const std::string &Name) override { 6028 if (Name != "aapcs" && Name != "darwinpcs") 6029 return false; 6030 6031 ABI = Name; 6032 return true; 6033 } 6034 6035 bool setCPU(const std::string &Name) override { 6036 return Name == "generic" || 6037 llvm::AArch64::parseCPUArch(Name) != 6038 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6039 } 6040 6041 void getTargetDefines(const LangOptions &Opts, 6042 MacroBuilder &Builder) const override { 6043 // Target identification. 6044 Builder.defineMacro("__aarch64__"); 6045 6046 // Target properties. 6047 Builder.defineMacro("_LP64"); 6048 Builder.defineMacro("__LP64__"); 6049 6050 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6051 Builder.defineMacro("__ARM_ACLE", "200"); 6052 Builder.defineMacro("__ARM_ARCH", "8"); 6053 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6054 6055 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6056 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6057 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6058 6059 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6060 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6061 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6062 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6063 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6064 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6065 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6066 6067 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6068 6069 // 0xe implies support for half, single and double precision operations. 6070 Builder.defineMacro("__ARM_FP", "0xE"); 6071 6072 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6073 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6074 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6075 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6076 6077 if (Opts.UnsafeFPMath) 6078 Builder.defineMacro("__ARM_FP_FAST", "1"); 6079 6080 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6081 6082 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6083 Opts.ShortEnums ? "1" : "4"); 6084 6085 if (FPU == NeonMode) { 6086 Builder.defineMacro("__ARM_NEON", "1"); 6087 // 64-bit NEON supports half, single and double precision operations. 6088 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6089 } 6090 6091 if (CRC) 6092 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6093 6094 if (Crypto) 6095 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6096 6097 if (Unaligned) 6098 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6099 6100 if (V8_1A) 6101 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6102 6103 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6104 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6105 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6106 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6107 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6108 } 6109 6110 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6111 return llvm::makeArrayRef(BuiltinInfo, 6112 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6113 } 6114 6115 bool hasFeature(StringRef Feature) const override { 6116 return Feature == "aarch64" || 6117 Feature == "arm64" || 6118 Feature == "arm" || 6119 (Feature == "neon" && FPU == NeonMode); 6120 } 6121 6122 bool handleTargetFeatures(std::vector<std::string> &Features, 6123 DiagnosticsEngine &Diags) override { 6124 FPU = FPUMode; 6125 CRC = 0; 6126 Crypto = 0; 6127 Unaligned = 1; 6128 V8_1A = 0; 6129 6130 for (const auto &Feature : Features) { 6131 if (Feature == "+neon") 6132 FPU = NeonMode; 6133 if (Feature == "+crc") 6134 CRC = 1; 6135 if (Feature == "+crypto") 6136 Crypto = 1; 6137 if (Feature == "+strict-align") 6138 Unaligned = 0; 6139 if (Feature == "+v8.1a") 6140 V8_1A = 1; 6141 } 6142 6143 setDataLayout(); 6144 6145 return true; 6146 } 6147 6148 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6149 switch (CC) { 6150 case CC_C: 6151 case CC_Swift: 6152 case CC_PreserveMost: 6153 case CC_PreserveAll: 6154 return CCCR_OK; 6155 default: 6156 return CCCR_Warning; 6157 } 6158 } 6159 6160 bool isCLZForZeroUndef() const override { return false; } 6161 6162 BuiltinVaListKind getBuiltinVaListKind() const override { 6163 return TargetInfo::AArch64ABIBuiltinVaList; 6164 } 6165 6166 ArrayRef<const char *> getGCCRegNames() const override; 6167 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6168 6169 bool validateAsmConstraint(const char *&Name, 6170 TargetInfo::ConstraintInfo &Info) const override { 6171 switch (*Name) { 6172 default: 6173 return false; 6174 case 'w': // Floating point and SIMD registers (V0-V31) 6175 Info.setAllowsRegister(); 6176 return true; 6177 case 'I': // Constant that can be used with an ADD instruction 6178 case 'J': // Constant that can be used with a SUB instruction 6179 case 'K': // Constant that can be used with a 32-bit logical instruction 6180 case 'L': // Constant that can be used with a 64-bit logical instruction 6181 case 'M': // Constant that can be used as a 32-bit MOV immediate 6182 case 'N': // Constant that can be used as a 64-bit MOV immediate 6183 case 'Y': // Floating point constant zero 6184 case 'Z': // Integer constant zero 6185 return true; 6186 case 'Q': // A memory reference with base register and no offset 6187 Info.setAllowsMemory(); 6188 return true; 6189 case 'S': // A symbolic address 6190 Info.setAllowsRegister(); 6191 return true; 6192 case 'U': 6193 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6194 // Utf: A memory address suitable for ldp/stp in TF mode. 6195 // Usa: An absolute symbolic address. 6196 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6197 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6198 case 'z': // Zero register, wzr or xzr 6199 Info.setAllowsRegister(); 6200 return true; 6201 case 'x': // Floating point and SIMD registers (V0-V15) 6202 Info.setAllowsRegister(); 6203 return true; 6204 } 6205 return false; 6206 } 6207 6208 bool 6209 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6210 std::string &SuggestedModifier) const override { 6211 // Strip off constraint modifiers. 6212 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6213 Constraint = Constraint.substr(1); 6214 6215 switch (Constraint[0]) { 6216 default: 6217 return true; 6218 case 'z': 6219 case 'r': { 6220 switch (Modifier) { 6221 case 'x': 6222 case 'w': 6223 // For now assume that the person knows what they're 6224 // doing with the modifier. 6225 return true; 6226 default: 6227 // By default an 'r' constraint will be in the 'x' 6228 // registers. 6229 if (Size == 64) 6230 return true; 6231 6232 SuggestedModifier = "w"; 6233 return false; 6234 } 6235 } 6236 } 6237 } 6238 6239 const char *getClobbers() const override { return ""; } 6240 6241 int getEHDataRegisterNumber(unsigned RegNo) const override { 6242 if (RegNo == 0) 6243 return 0; 6244 if (RegNo == 1) 6245 return 1; 6246 return -1; 6247 } 6248 }; 6249 6250 const char *const AArch64TargetInfo::GCCRegNames[] = { 6251 // 32-bit Integer registers 6252 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6253 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6254 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6255 6256 // 64-bit Integer registers 6257 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6258 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6259 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6260 6261 // 32-bit floating point regsisters 6262 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6263 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6264 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6265 6266 // 64-bit floating point regsisters 6267 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6268 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6269 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6270 6271 // Vector registers 6272 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6273 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6274 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6275 }; 6276 6277 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6278 return llvm::makeArrayRef(GCCRegNames); 6279 } 6280 6281 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6282 { { "w31" }, "wsp" }, 6283 { { "x29" }, "fp" }, 6284 { { "x30" }, "lr" }, 6285 { { "x31" }, "sp" }, 6286 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6287 // don't want to substitute one of these for a different-sized one. 6288 }; 6289 6290 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6291 return llvm::makeArrayRef(GCCRegAliases); 6292 } 6293 6294 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6295 #define BUILTIN(ID, TYPE, ATTRS) \ 6296 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6297 #include "clang/Basic/BuiltinsNEON.def" 6298 6299 #define BUILTIN(ID, TYPE, ATTRS) \ 6300 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6301 #include "clang/Basic/BuiltinsAArch64.def" 6302 }; 6303 6304 class AArch64leTargetInfo : public AArch64TargetInfo { 6305 void setDataLayout() override { 6306 if (getTriple().isOSBinFormatMachO()) 6307 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6308 else 6309 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6310 } 6311 6312 public: 6313 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6314 : AArch64TargetInfo(Triple, Opts) { 6315 } 6316 void getTargetDefines(const LangOptions &Opts, 6317 MacroBuilder &Builder) const override { 6318 Builder.defineMacro("__AARCH64EL__"); 6319 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6320 } 6321 }; 6322 6323 class AArch64beTargetInfo : public AArch64TargetInfo { 6324 void setDataLayout() override { 6325 assert(!getTriple().isOSBinFormatMachO()); 6326 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6327 } 6328 6329 public: 6330 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6331 : AArch64TargetInfo(Triple, Opts) {} 6332 void getTargetDefines(const LangOptions &Opts, 6333 MacroBuilder &Builder) const override { 6334 Builder.defineMacro("__AARCH64EB__"); 6335 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6336 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6337 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6338 } 6339 }; 6340 6341 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6342 protected: 6343 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6344 MacroBuilder &Builder) const override { 6345 Builder.defineMacro("__AARCH64_SIMD__"); 6346 Builder.defineMacro("__ARM64_ARCH_8__"); 6347 Builder.defineMacro("__ARM_NEON__"); 6348 Builder.defineMacro("__LITTLE_ENDIAN__"); 6349 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6350 Builder.defineMacro("__arm64", "1"); 6351 Builder.defineMacro("__arm64__", "1"); 6352 6353 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6354 } 6355 6356 public: 6357 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6358 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6359 Int64Type = SignedLongLong; 6360 WCharType = SignedInt; 6361 UseSignedCharForObjCBool = false; 6362 6363 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6364 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6365 6366 TheCXXABI.set(TargetCXXABI::iOS64); 6367 } 6368 6369 BuiltinVaListKind getBuiltinVaListKind() const override { 6370 return TargetInfo::CharPtrBuiltinVaList; 6371 } 6372 }; 6373 6374 // Hexagon abstract base class 6375 class HexagonTargetInfo : public TargetInfo { 6376 static const Builtin::Info BuiltinInfo[]; 6377 static const char * const GCCRegNames[]; 6378 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6379 std::string CPU; 6380 bool HasHVX, HasHVXDouble; 6381 bool UseLongCalls; 6382 6383 public: 6384 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6385 : TargetInfo(Triple) { 6386 // Specify the vector alignment explicitly. For v512x1, the calculated 6387 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6388 // the required minimum of 64 bytes. 6389 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6390 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6391 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6392 SizeType = UnsignedInt; 6393 PtrDiffType = SignedInt; 6394 IntPtrType = SignedInt; 6395 6396 // {} in inline assembly are packet specifiers, not assembly variant 6397 // specifiers. 6398 NoAsmVariants = true; 6399 6400 LargeArrayMinWidth = 64; 6401 LargeArrayAlign = 64; 6402 UseBitFieldTypeAlignment = true; 6403 ZeroLengthBitfieldBoundary = 32; 6404 HasHVX = HasHVXDouble = false; 6405 UseLongCalls = false; 6406 } 6407 6408 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6409 return llvm::makeArrayRef(BuiltinInfo, 6410 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6411 } 6412 6413 bool validateAsmConstraint(const char *&Name, 6414 TargetInfo::ConstraintInfo &Info) const override { 6415 switch (*Name) { 6416 case 'v': 6417 case 'q': 6418 if (HasHVX) { 6419 Info.setAllowsRegister(); 6420 return true; 6421 } 6422 break; 6423 case 's': 6424 // Relocatable constant. 6425 return true; 6426 } 6427 return false; 6428 } 6429 6430 void getTargetDefines(const LangOptions &Opts, 6431 MacroBuilder &Builder) const override; 6432 6433 bool isCLZForZeroUndef() const override { return false; } 6434 6435 bool hasFeature(StringRef Feature) const override { 6436 return llvm::StringSwitch<bool>(Feature) 6437 .Case("hexagon", true) 6438 .Case("hvx", HasHVX) 6439 .Case("hvx-double", HasHVXDouble) 6440 .Case("long-calls", UseLongCalls) 6441 .Default(false); 6442 } 6443 6444 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6445 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6446 const override; 6447 6448 bool handleTargetFeatures(std::vector<std::string> &Features, 6449 DiagnosticsEngine &Diags) override; 6450 6451 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6452 bool Enabled) const override; 6453 6454 BuiltinVaListKind getBuiltinVaListKind() const override { 6455 return TargetInfo::CharPtrBuiltinVaList; 6456 } 6457 ArrayRef<const char *> getGCCRegNames() const override; 6458 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6459 const char *getClobbers() const override { 6460 return ""; 6461 } 6462 6463 static const char *getHexagonCPUSuffix(StringRef Name) { 6464 return llvm::StringSwitch<const char*>(Name) 6465 .Case("hexagonv4", "4") 6466 .Case("hexagonv5", "5") 6467 .Case("hexagonv55", "55") 6468 .Case("hexagonv60", "60") 6469 .Case("hexagonv62", "62") 6470 .Default(nullptr); 6471 } 6472 6473 bool setCPU(const std::string &Name) override { 6474 if (!getHexagonCPUSuffix(Name)) 6475 return false; 6476 CPU = Name; 6477 return true; 6478 } 6479 6480 int getEHDataRegisterNumber(unsigned RegNo) const override { 6481 return RegNo < 2 ? RegNo : -1; 6482 } 6483 }; 6484 6485 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6486 MacroBuilder &Builder) const { 6487 Builder.defineMacro("__qdsp6__", "1"); 6488 Builder.defineMacro("__hexagon__", "1"); 6489 6490 if (CPU == "hexagonv4") { 6491 Builder.defineMacro("__HEXAGON_V4__"); 6492 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6493 if (Opts.HexagonQdsp6Compat) { 6494 Builder.defineMacro("__QDSP6_V4__"); 6495 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6496 } 6497 } else if (CPU == "hexagonv5") { 6498 Builder.defineMacro("__HEXAGON_V5__"); 6499 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6500 if(Opts.HexagonQdsp6Compat) { 6501 Builder.defineMacro("__QDSP6_V5__"); 6502 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6503 } 6504 } else if (CPU == "hexagonv55") { 6505 Builder.defineMacro("__HEXAGON_V55__"); 6506 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6507 Builder.defineMacro("__QDSP6_V55__"); 6508 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6509 } else if (CPU == "hexagonv60") { 6510 Builder.defineMacro("__HEXAGON_V60__"); 6511 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6512 Builder.defineMacro("__QDSP6_V60__"); 6513 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6514 } else if (CPU == "hexagonv62") { 6515 Builder.defineMacro("__HEXAGON_V62__"); 6516 Builder.defineMacro("__HEXAGON_ARCH__", "62"); 6517 } 6518 6519 if (hasFeature("hvx")) { 6520 Builder.defineMacro("__HVX__"); 6521 if (hasFeature("hvx-double")) 6522 Builder.defineMacro("__HVXDBL__"); 6523 } 6524 } 6525 6526 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6527 DiagnosticsEngine &Diags, StringRef CPU, 6528 const std::vector<std::string> &FeaturesVec) const { 6529 // Default for v60: -hvx, -hvx-double. 6530 Features["hvx"] = false; 6531 Features["hvx-double"] = false; 6532 Features["long-calls"] = false; 6533 6534 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6535 } 6536 6537 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6538 DiagnosticsEngine &Diags) { 6539 for (auto &F : Features) { 6540 if (F == "+hvx") 6541 HasHVX = true; 6542 else if (F == "-hvx") 6543 HasHVX = HasHVXDouble = false; 6544 else if (F == "+hvx-double") 6545 HasHVX = HasHVXDouble = true; 6546 else if (F == "-hvx-double") 6547 HasHVXDouble = false; 6548 6549 if (F == "+long-calls") 6550 UseLongCalls = true; 6551 else if (F == "-long-calls") 6552 UseLongCalls = false; 6553 } 6554 return true; 6555 } 6556 6557 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6558 StringRef Name, bool Enabled) const { 6559 if (Enabled) { 6560 if (Name == "hvx-double") 6561 Features["hvx"] = true; 6562 } else { 6563 if (Name == "hvx") 6564 Features["hvx-double"] = false; 6565 } 6566 Features[Name] = Enabled; 6567 } 6568 6569 const char *const HexagonTargetInfo::GCCRegNames[] = { 6570 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6571 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6572 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6573 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6574 "p0", "p1", "p2", "p3", 6575 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6576 }; 6577 6578 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6579 return llvm::makeArrayRef(GCCRegNames); 6580 } 6581 6582 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6583 { { "sp" }, "r29" }, 6584 { { "fp" }, "r30" }, 6585 { { "lr" }, "r31" }, 6586 }; 6587 6588 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6589 return llvm::makeArrayRef(GCCRegAliases); 6590 } 6591 6592 6593 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6594 #define BUILTIN(ID, TYPE, ATTRS) \ 6595 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6596 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6597 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6598 #include "clang/Basic/BuiltinsHexagon.def" 6599 }; 6600 6601 class LanaiTargetInfo : public TargetInfo { 6602 // Class for Lanai (32-bit). 6603 // The CPU profiles supported by the Lanai backend 6604 enum CPUKind { 6605 CK_NONE, 6606 CK_V11, 6607 } CPU; 6608 6609 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6610 static const char *const GCCRegNames[]; 6611 6612 public: 6613 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6614 : TargetInfo(Triple) { 6615 // Description string has to be kept in sync with backend. 6616 resetDataLayout("E" // Big endian 6617 "-m:e" // ELF name manging 6618 "-p:32:32" // 32 bit pointers, 32 bit aligned 6619 "-i64:64" // 64 bit integers, 64 bit aligned 6620 "-a:0:32" // 32 bit alignment of objects of aggregate type 6621 "-n32" // 32 bit native integer width 6622 "-S64" // 64 bit natural stack alignment 6623 ); 6624 6625 // Setting RegParmMax equal to what mregparm was set to in the old 6626 // toolchain 6627 RegParmMax = 4; 6628 6629 // Set the default CPU to V11 6630 CPU = CK_V11; 6631 6632 // Temporary approach to make everything at least word-aligned and allow for 6633 // safely casting between pointers with different alignment requirements. 6634 // TODO: Remove this when there are no more cast align warnings on the 6635 // firmware. 6636 MinGlobalAlign = 32; 6637 } 6638 6639 void getTargetDefines(const LangOptions &Opts, 6640 MacroBuilder &Builder) const override { 6641 // Define __lanai__ when building for target lanai. 6642 Builder.defineMacro("__lanai__"); 6643 6644 // Set define for the CPU specified. 6645 switch (CPU) { 6646 case CK_V11: 6647 Builder.defineMacro("__LANAI_V11__"); 6648 break; 6649 case CK_NONE: 6650 llvm_unreachable("Unhandled target CPU"); 6651 } 6652 } 6653 6654 bool setCPU(const std::string &Name) override { 6655 CPU = llvm::StringSwitch<CPUKind>(Name) 6656 .Case("v11", CK_V11) 6657 .Default(CK_NONE); 6658 6659 return CPU != CK_NONE; 6660 } 6661 6662 bool hasFeature(StringRef Feature) const override { 6663 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6664 } 6665 6666 ArrayRef<const char *> getGCCRegNames() const override; 6667 6668 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6669 6670 BuiltinVaListKind getBuiltinVaListKind() const override { 6671 return TargetInfo::VoidPtrBuiltinVaList; 6672 } 6673 6674 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6675 6676 bool validateAsmConstraint(const char *&Name, 6677 TargetInfo::ConstraintInfo &info) const override { 6678 return false; 6679 } 6680 6681 const char *getClobbers() const override { return ""; } 6682 }; 6683 6684 const char *const LanaiTargetInfo::GCCRegNames[] = { 6685 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6686 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6687 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6688 6689 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6690 return llvm::makeArrayRef(GCCRegNames); 6691 } 6692 6693 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6694 {{"pc"}, "r2"}, 6695 {{"sp"}, "r4"}, 6696 {{"fp"}, "r5"}, 6697 {{"rv"}, "r8"}, 6698 {{"rr1"}, "r10"}, 6699 {{"rr2"}, "r11"}, 6700 {{"rca"}, "r15"}, 6701 }; 6702 6703 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6704 return llvm::makeArrayRef(GCCRegAliases); 6705 } 6706 6707 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6708 class SparcTargetInfo : public TargetInfo { 6709 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6710 static const char * const GCCRegNames[]; 6711 bool SoftFloat; 6712 public: 6713 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6714 : TargetInfo(Triple), SoftFloat(false) {} 6715 6716 int getEHDataRegisterNumber(unsigned RegNo) const override { 6717 if (RegNo == 0) return 24; 6718 if (RegNo == 1) return 25; 6719 return -1; 6720 } 6721 6722 bool handleTargetFeatures(std::vector<std::string> &Features, 6723 DiagnosticsEngine &Diags) override { 6724 // Check if software floating point is enabled 6725 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6726 if (Feature != Features.end()) { 6727 SoftFloat = true; 6728 } 6729 return true; 6730 } 6731 void getTargetDefines(const LangOptions &Opts, 6732 MacroBuilder &Builder) const override { 6733 DefineStd(Builder, "sparc", Opts); 6734 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6735 6736 if (SoftFloat) 6737 Builder.defineMacro("SOFT_FLOAT", "1"); 6738 } 6739 6740 bool hasFeature(StringRef Feature) const override { 6741 return llvm::StringSwitch<bool>(Feature) 6742 .Case("softfloat", SoftFloat) 6743 .Case("sparc", true) 6744 .Default(false); 6745 } 6746 6747 bool hasSjLjLowering() const override { 6748 return true; 6749 } 6750 6751 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6752 // FIXME: Implement! 6753 return None; 6754 } 6755 BuiltinVaListKind getBuiltinVaListKind() const override { 6756 return TargetInfo::VoidPtrBuiltinVaList; 6757 } 6758 ArrayRef<const char *> getGCCRegNames() const override; 6759 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6760 bool validateAsmConstraint(const char *&Name, 6761 TargetInfo::ConstraintInfo &info) const override { 6762 // FIXME: Implement! 6763 switch (*Name) { 6764 case 'I': // Signed 13-bit constant 6765 case 'J': // Zero 6766 case 'K': // 32-bit constant with the low 12 bits clear 6767 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6768 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6769 case 'N': // Same as 'K' but zext (required for SIMode) 6770 case 'O': // The constant 4096 6771 return true; 6772 } 6773 return false; 6774 } 6775 const char *getClobbers() const override { 6776 // FIXME: Implement! 6777 return ""; 6778 } 6779 6780 // No Sparc V7 for now, the backend doesn't support it anyway. 6781 enum CPUKind { 6782 CK_GENERIC, 6783 CK_V8, 6784 CK_SUPERSPARC, 6785 CK_SPARCLITE, 6786 CK_F934, 6787 CK_HYPERSPARC, 6788 CK_SPARCLITE86X, 6789 CK_SPARCLET, 6790 CK_TSC701, 6791 CK_V9, 6792 CK_ULTRASPARC, 6793 CK_ULTRASPARC3, 6794 CK_NIAGARA, 6795 CK_NIAGARA2, 6796 CK_NIAGARA3, 6797 CK_NIAGARA4, 6798 CK_MYRIAD2100, 6799 CK_MYRIAD2150, 6800 CK_MYRIAD2450, 6801 CK_LEON2, 6802 CK_LEON2_AT697E, 6803 CK_LEON2_AT697F, 6804 CK_LEON3, 6805 CK_LEON3_UT699, 6806 CK_LEON3_GR712RC, 6807 CK_LEON4, 6808 CK_LEON4_GR740 6809 } CPU = CK_GENERIC; 6810 6811 enum CPUGeneration { 6812 CG_V8, 6813 CG_V9, 6814 }; 6815 6816 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6817 switch (Kind) { 6818 case CK_GENERIC: 6819 case CK_V8: 6820 case CK_SUPERSPARC: 6821 case CK_SPARCLITE: 6822 case CK_F934: 6823 case CK_HYPERSPARC: 6824 case CK_SPARCLITE86X: 6825 case CK_SPARCLET: 6826 case CK_TSC701: 6827 case CK_MYRIAD2100: 6828 case CK_MYRIAD2150: 6829 case CK_MYRIAD2450: 6830 case CK_LEON2: 6831 case CK_LEON2_AT697E: 6832 case CK_LEON2_AT697F: 6833 case CK_LEON3: 6834 case CK_LEON3_UT699: 6835 case CK_LEON3_GR712RC: 6836 case CK_LEON4: 6837 case CK_LEON4_GR740: 6838 return CG_V8; 6839 case CK_V9: 6840 case CK_ULTRASPARC: 6841 case CK_ULTRASPARC3: 6842 case CK_NIAGARA: 6843 case CK_NIAGARA2: 6844 case CK_NIAGARA3: 6845 case CK_NIAGARA4: 6846 return CG_V9; 6847 } 6848 llvm_unreachable("Unexpected CPU kind"); 6849 } 6850 6851 CPUKind getCPUKind(StringRef Name) const { 6852 return llvm::StringSwitch<CPUKind>(Name) 6853 .Case("v8", CK_V8) 6854 .Case("supersparc", CK_SUPERSPARC) 6855 .Case("sparclite", CK_SPARCLITE) 6856 .Case("f934", CK_F934) 6857 .Case("hypersparc", CK_HYPERSPARC) 6858 .Case("sparclite86x", CK_SPARCLITE86X) 6859 .Case("sparclet", CK_SPARCLET) 6860 .Case("tsc701", CK_TSC701) 6861 .Case("v9", CK_V9) 6862 .Case("ultrasparc", CK_ULTRASPARC) 6863 .Case("ultrasparc3", CK_ULTRASPARC3) 6864 .Case("niagara", CK_NIAGARA) 6865 .Case("niagara2", CK_NIAGARA2) 6866 .Case("niagara3", CK_NIAGARA3) 6867 .Case("niagara4", CK_NIAGARA4) 6868 .Case("ma2100", CK_MYRIAD2100) 6869 .Case("ma2150", CK_MYRIAD2150) 6870 .Case("ma2450", CK_MYRIAD2450) 6871 // FIXME: the myriad2[.n] spellings are obsolete, 6872 // but a grace period is needed to allow updating dependent builds. 6873 .Case("myriad2", CK_MYRIAD2100) 6874 .Case("myriad2.1", CK_MYRIAD2100) 6875 .Case("myriad2.2", CK_MYRIAD2150) 6876 .Case("leon2", CK_LEON2) 6877 .Case("at697e", CK_LEON2_AT697E) 6878 .Case("at697f", CK_LEON2_AT697F) 6879 .Case("leon3", CK_LEON3) 6880 .Case("ut699", CK_LEON3_UT699) 6881 .Case("gr712rc", CK_LEON3_GR712RC) 6882 .Case("leon4", CK_LEON4) 6883 .Case("gr740", CK_LEON4_GR740) 6884 .Default(CK_GENERIC); 6885 } 6886 6887 bool setCPU(const std::string &Name) override { 6888 CPU = getCPUKind(Name); 6889 return CPU != CK_GENERIC; 6890 } 6891 }; 6892 6893 const char * const SparcTargetInfo::GCCRegNames[] = { 6894 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6895 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6896 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6897 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6898 }; 6899 6900 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6901 return llvm::makeArrayRef(GCCRegNames); 6902 } 6903 6904 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6905 { { "g0" }, "r0" }, 6906 { { "g1" }, "r1" }, 6907 { { "g2" }, "r2" }, 6908 { { "g3" }, "r3" }, 6909 { { "g4" }, "r4" }, 6910 { { "g5" }, "r5" }, 6911 { { "g6" }, "r6" }, 6912 { { "g7" }, "r7" }, 6913 { { "o0" }, "r8" }, 6914 { { "o1" }, "r9" }, 6915 { { "o2" }, "r10" }, 6916 { { "o3" }, "r11" }, 6917 { { "o4" }, "r12" }, 6918 { { "o5" }, "r13" }, 6919 { { "o6", "sp" }, "r14" }, 6920 { { "o7" }, "r15" }, 6921 { { "l0" }, "r16" }, 6922 { { "l1" }, "r17" }, 6923 { { "l2" }, "r18" }, 6924 { { "l3" }, "r19" }, 6925 { { "l4" }, "r20" }, 6926 { { "l5" }, "r21" }, 6927 { { "l6" }, "r22" }, 6928 { { "l7" }, "r23" }, 6929 { { "i0" }, "r24" }, 6930 { { "i1" }, "r25" }, 6931 { { "i2" }, "r26" }, 6932 { { "i3" }, "r27" }, 6933 { { "i4" }, "r28" }, 6934 { { "i5" }, "r29" }, 6935 { { "i6", "fp" }, "r30" }, 6936 { { "i7" }, "r31" }, 6937 }; 6938 6939 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6940 return llvm::makeArrayRef(GCCRegAliases); 6941 } 6942 6943 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6944 class SparcV8TargetInfo : public SparcTargetInfo { 6945 public: 6946 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6947 : SparcTargetInfo(Triple, Opts) { 6948 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6949 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6950 switch (getTriple().getOS()) { 6951 default: 6952 SizeType = UnsignedInt; 6953 IntPtrType = SignedInt; 6954 PtrDiffType = SignedInt; 6955 break; 6956 case llvm::Triple::NetBSD: 6957 case llvm::Triple::OpenBSD: 6958 SizeType = UnsignedLong; 6959 IntPtrType = SignedLong; 6960 PtrDiffType = SignedLong; 6961 break; 6962 } 6963 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 6964 // on up to 64 bits. 6965 MaxAtomicPromoteWidth = 64; 6966 MaxAtomicInlineWidth = 32; 6967 } 6968 6969 void getTargetDefines(const LangOptions &Opts, 6970 MacroBuilder &Builder) const override { 6971 SparcTargetInfo::getTargetDefines(Opts, Builder); 6972 switch (getCPUGeneration(CPU)) { 6973 case CG_V8: 6974 Builder.defineMacro("__sparcv8"); 6975 if (getTriple().getOS() != llvm::Triple::Solaris) 6976 Builder.defineMacro("__sparcv8__"); 6977 break; 6978 case CG_V9: 6979 Builder.defineMacro("__sparcv9"); 6980 if (getTriple().getOS() != llvm::Triple::Solaris) { 6981 Builder.defineMacro("__sparcv9__"); 6982 Builder.defineMacro("__sparc_v9__"); 6983 } 6984 break; 6985 } 6986 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6987 std::string MyriadArchValue, Myriad2Value; 6988 Builder.defineMacro("__sparc_v8__"); 6989 Builder.defineMacro("__leon__"); 6990 switch (CPU) { 6991 case CK_MYRIAD2150: 6992 MyriadArchValue = "__ma2150"; 6993 Myriad2Value = "2"; 6994 break; 6995 case CK_MYRIAD2450: 6996 MyriadArchValue = "__ma2450"; 6997 Myriad2Value = "2"; 6998 break; 6999 default: 7000 MyriadArchValue = "__ma2100"; 7001 Myriad2Value = "1"; 7002 break; 7003 } 7004 Builder.defineMacro(MyriadArchValue, "1"); 7005 Builder.defineMacro(MyriadArchValue+"__", "1"); 7006 Builder.defineMacro("__myriad2__", Myriad2Value); 7007 Builder.defineMacro("__myriad2", Myriad2Value); 7008 } 7009 } 7010 7011 bool hasSjLjLowering() const override { 7012 return true; 7013 } 7014 }; 7015 7016 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 7017 class SparcV8elTargetInfo : public SparcV8TargetInfo { 7018 public: 7019 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7020 : SparcV8TargetInfo(Triple, Opts) { 7021 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7022 } 7023 }; 7024 7025 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 7026 class SparcV9TargetInfo : public SparcTargetInfo { 7027 public: 7028 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7029 : SparcTargetInfo(Triple, Opts) { 7030 // FIXME: Support Sparc quad-precision long double? 7031 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 7032 // This is an LP64 platform. 7033 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7034 7035 // OpenBSD uses long long for int64_t and intmax_t. 7036 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7037 IntMaxType = SignedLongLong; 7038 else 7039 IntMaxType = SignedLong; 7040 Int64Type = IntMaxType; 7041 7042 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7043 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7044 LongDoubleWidth = 128; 7045 LongDoubleAlign = 128; 7046 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7047 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7048 } 7049 7050 void getTargetDefines(const LangOptions &Opts, 7051 MacroBuilder &Builder) const override { 7052 SparcTargetInfo::getTargetDefines(Opts, Builder); 7053 Builder.defineMacro("__sparcv9"); 7054 Builder.defineMacro("__arch64__"); 7055 // Solaris doesn't need these variants, but the BSDs do. 7056 if (getTriple().getOS() != llvm::Triple::Solaris) { 7057 Builder.defineMacro("__sparc64__"); 7058 Builder.defineMacro("__sparc_v9__"); 7059 Builder.defineMacro("__sparcv9__"); 7060 } 7061 } 7062 7063 bool setCPU(const std::string &Name) override { 7064 if (!SparcTargetInfo::setCPU(Name)) 7065 return false; 7066 return getCPUGeneration(CPU) == CG_V9; 7067 } 7068 }; 7069 7070 class SystemZTargetInfo : public TargetInfo { 7071 static const Builtin::Info BuiltinInfo[]; 7072 static const char *const GCCRegNames[]; 7073 std::string CPU; 7074 bool HasTransactionalExecution; 7075 bool HasVector; 7076 7077 public: 7078 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7079 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 7080 HasVector(false) { 7081 IntMaxType = SignedLong; 7082 Int64Type = SignedLong; 7083 TLSSupported = true; 7084 IntWidth = IntAlign = 32; 7085 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7086 PointerWidth = PointerAlign = 64; 7087 LongDoubleWidth = 128; 7088 LongDoubleAlign = 64; 7089 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7090 DefaultAlignForAttributeAligned = 64; 7091 MinGlobalAlign = 16; 7092 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7093 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7094 } 7095 void getTargetDefines(const LangOptions &Opts, 7096 MacroBuilder &Builder) const override { 7097 Builder.defineMacro("__s390__"); 7098 Builder.defineMacro("__s390x__"); 7099 Builder.defineMacro("__zarch__"); 7100 Builder.defineMacro("__LONG_DOUBLE_128__"); 7101 7102 const std::string ISARev = llvm::StringSwitch<std::string>(CPU) 7103 .Cases("arch8", "z10", "8") 7104 .Cases("arch9", "z196", "9") 7105 .Cases("arch10", "zEC12", "10") 7106 .Cases("arch11", "z13", "11") 7107 .Default(""); 7108 if (!ISARev.empty()) 7109 Builder.defineMacro("__ARCH__", ISARev); 7110 7111 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7112 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7113 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7114 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7115 7116 if (HasTransactionalExecution) 7117 Builder.defineMacro("__HTM__"); 7118 if (HasVector) 7119 Builder.defineMacro("__VX__"); 7120 if (Opts.ZVector) 7121 Builder.defineMacro("__VEC__", "10301"); 7122 } 7123 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7124 return llvm::makeArrayRef(BuiltinInfo, 7125 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7126 } 7127 7128 ArrayRef<const char *> getGCCRegNames() const override; 7129 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7130 // No aliases. 7131 return None; 7132 } 7133 bool validateAsmConstraint(const char *&Name, 7134 TargetInfo::ConstraintInfo &info) const override; 7135 const char *getClobbers() const override { 7136 // FIXME: Is this really right? 7137 return ""; 7138 } 7139 BuiltinVaListKind getBuiltinVaListKind() const override { 7140 return TargetInfo::SystemZBuiltinVaList; 7141 } 7142 bool setCPU(const std::string &Name) override { 7143 CPU = Name; 7144 bool CPUKnown = llvm::StringSwitch<bool>(Name) 7145 .Case("z10", true) 7146 .Case("arch8", true) 7147 .Case("z196", true) 7148 .Case("arch9", true) 7149 .Case("zEC12", true) 7150 .Case("arch10", true) 7151 .Case("z13", true) 7152 .Case("arch11", true) 7153 .Default(false); 7154 7155 return CPUKnown; 7156 } 7157 bool 7158 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7159 StringRef CPU, 7160 const std::vector<std::string> &FeaturesVec) const override { 7161 if (CPU == "zEC12" || CPU == "arch10") 7162 Features["transactional-execution"] = true; 7163 if (CPU == "z13" || CPU == "arch11") { 7164 Features["transactional-execution"] = true; 7165 Features["vector"] = true; 7166 } 7167 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7168 } 7169 7170 bool handleTargetFeatures(std::vector<std::string> &Features, 7171 DiagnosticsEngine &Diags) override { 7172 HasTransactionalExecution = false; 7173 for (const auto &Feature : Features) { 7174 if (Feature == "+transactional-execution") 7175 HasTransactionalExecution = true; 7176 else if (Feature == "+vector") 7177 HasVector = true; 7178 } 7179 // If we use the vector ABI, vector types are 64-bit aligned. 7180 if (HasVector) { 7181 MaxVectorAlign = 64; 7182 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7183 "-v128:64-a:8:16-n32:64"); 7184 } 7185 return true; 7186 } 7187 7188 bool hasFeature(StringRef Feature) const override { 7189 return llvm::StringSwitch<bool>(Feature) 7190 .Case("systemz", true) 7191 .Case("htm", HasTransactionalExecution) 7192 .Case("vx", HasVector) 7193 .Default(false); 7194 } 7195 7196 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7197 switch (CC) { 7198 case CC_C: 7199 case CC_Swift: 7200 return CCCR_OK; 7201 default: 7202 return CCCR_Warning; 7203 } 7204 } 7205 7206 StringRef getABI() const override { 7207 if (HasVector) 7208 return "vector"; 7209 return ""; 7210 } 7211 7212 bool useFloat128ManglingForLongDouble() const override { 7213 return true; 7214 } 7215 }; 7216 7217 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7218 #define BUILTIN(ID, TYPE, ATTRS) \ 7219 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7220 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7221 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7222 #include "clang/Basic/BuiltinsSystemZ.def" 7223 }; 7224 7225 const char *const SystemZTargetInfo::GCCRegNames[] = { 7226 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7227 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7228 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7229 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7230 }; 7231 7232 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7233 return llvm::makeArrayRef(GCCRegNames); 7234 } 7235 7236 bool SystemZTargetInfo:: 7237 validateAsmConstraint(const char *&Name, 7238 TargetInfo::ConstraintInfo &Info) const { 7239 switch (*Name) { 7240 default: 7241 return false; 7242 7243 case 'a': // Address register 7244 case 'd': // Data register (equivalent to 'r') 7245 case 'f': // Floating-point register 7246 Info.setAllowsRegister(); 7247 return true; 7248 7249 case 'I': // Unsigned 8-bit constant 7250 case 'J': // Unsigned 12-bit constant 7251 case 'K': // Signed 16-bit constant 7252 case 'L': // Signed 20-bit displacement (on all targets we support) 7253 case 'M': // 0x7fffffff 7254 return true; 7255 7256 case 'Q': // Memory with base and unsigned 12-bit displacement 7257 case 'R': // Likewise, plus an index 7258 case 'S': // Memory with base and signed 20-bit displacement 7259 case 'T': // Likewise, plus an index 7260 Info.setAllowsMemory(); 7261 return true; 7262 } 7263 } 7264 7265 class MSP430TargetInfo : public TargetInfo { 7266 static const char *const GCCRegNames[]; 7267 7268 public: 7269 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7270 : TargetInfo(Triple) { 7271 TLSSupported = false; 7272 IntWidth = 16; 7273 IntAlign = 16; 7274 LongWidth = 32; 7275 LongLongWidth = 64; 7276 LongAlign = LongLongAlign = 16; 7277 PointerWidth = 16; 7278 PointerAlign = 16; 7279 SuitableAlign = 16; 7280 SizeType = UnsignedInt; 7281 IntMaxType = SignedLongLong; 7282 IntPtrType = SignedInt; 7283 PtrDiffType = SignedInt; 7284 SigAtomicType = SignedLong; 7285 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7286 } 7287 void getTargetDefines(const LangOptions &Opts, 7288 MacroBuilder &Builder) const override { 7289 Builder.defineMacro("MSP430"); 7290 Builder.defineMacro("__MSP430__"); 7291 // FIXME: defines for different 'flavours' of MCU 7292 } 7293 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7294 // FIXME: Implement. 7295 return None; 7296 } 7297 bool hasFeature(StringRef Feature) const override { 7298 return Feature == "msp430"; 7299 } 7300 ArrayRef<const char *> getGCCRegNames() const override; 7301 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7302 // No aliases. 7303 return None; 7304 } 7305 bool validateAsmConstraint(const char *&Name, 7306 TargetInfo::ConstraintInfo &info) const override { 7307 // FIXME: implement 7308 switch (*Name) { 7309 case 'K': // the constant 1 7310 case 'L': // constant -1^20 .. 1^19 7311 case 'M': // constant 1-4: 7312 return true; 7313 } 7314 // No target constraints for now. 7315 return false; 7316 } 7317 const char *getClobbers() const override { 7318 // FIXME: Is this really right? 7319 return ""; 7320 } 7321 BuiltinVaListKind getBuiltinVaListKind() const override { 7322 // FIXME: implement 7323 return TargetInfo::CharPtrBuiltinVaList; 7324 } 7325 }; 7326 7327 const char *const MSP430TargetInfo::GCCRegNames[] = { 7328 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7329 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7330 7331 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7332 return llvm::makeArrayRef(GCCRegNames); 7333 } 7334 7335 // LLVM and Clang cannot be used directly to output native binaries for 7336 // target, but is used to compile C code to llvm bitcode with correct 7337 // type and alignment information. 7338 // 7339 // TCE uses the llvm bitcode as input and uses it for generating customized 7340 // target processor and program binary. TCE co-design environment is 7341 // publicly available in http://tce.cs.tut.fi 7342 7343 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7344 3, // opencl_global 7345 4, // opencl_local 7346 5, // opencl_constant 7347 // FIXME: generic has to be added to the target 7348 0, // opencl_generic 7349 0, // cuda_device 7350 0, // cuda_constant 7351 0 // cuda_shared 7352 }; 7353 7354 class TCETargetInfo : public TargetInfo { 7355 public: 7356 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7357 : TargetInfo(Triple) { 7358 TLSSupported = false; 7359 IntWidth = 32; 7360 LongWidth = LongLongWidth = 32; 7361 PointerWidth = 32; 7362 IntAlign = 32; 7363 LongAlign = LongLongAlign = 32; 7364 PointerAlign = 32; 7365 SuitableAlign = 32; 7366 SizeType = UnsignedInt; 7367 IntMaxType = SignedLong; 7368 IntPtrType = SignedInt; 7369 PtrDiffType = SignedInt; 7370 FloatWidth = 32; 7371 FloatAlign = 32; 7372 DoubleWidth = 32; 7373 DoubleAlign = 32; 7374 LongDoubleWidth = 32; 7375 LongDoubleAlign = 32; 7376 FloatFormat = &llvm::APFloat::IEEEsingle(); 7377 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7378 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7379 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7380 "i16:16:32-i32:32:32-i64:32:32-" 7381 "f32:32:32-f64:32:32-v64:32:32-" 7382 "v128:32:32-v256:32:32-v512:32:32-" 7383 "v1024:32:32-a0:0:32-n32"); 7384 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7385 UseAddrSpaceMapMangling = true; 7386 } 7387 7388 void getTargetDefines(const LangOptions &Opts, 7389 MacroBuilder &Builder) const override { 7390 DefineStd(Builder, "tce", Opts); 7391 Builder.defineMacro("__TCE__"); 7392 Builder.defineMacro("__TCE_V1__"); 7393 } 7394 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7395 7396 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7397 const char *getClobbers() const override { return ""; } 7398 BuiltinVaListKind getBuiltinVaListKind() const override { 7399 return TargetInfo::VoidPtrBuiltinVaList; 7400 } 7401 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7402 bool validateAsmConstraint(const char *&Name, 7403 TargetInfo::ConstraintInfo &info) const override { 7404 return true; 7405 } 7406 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7407 return None; 7408 } 7409 }; 7410 7411 class TCELETargetInfo : public TCETargetInfo { 7412 public: 7413 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7414 : TCETargetInfo(Triple, Opts) { 7415 BigEndian = false; 7416 7417 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7418 "i16:16:32-i32:32:32-i64:32:32-" 7419 "f32:32:32-f64:32:32-v64:32:32-" 7420 "v128:32:32-v256:32:32-v512:32:32-" 7421 "v1024:32:32-a0:0:32-n32"); 7422 7423 } 7424 7425 virtual void getTargetDefines(const LangOptions &Opts, 7426 MacroBuilder &Builder) const { 7427 DefineStd(Builder, "tcele", Opts); 7428 Builder.defineMacro("__TCE__"); 7429 Builder.defineMacro("__TCE_V1__"); 7430 Builder.defineMacro("__TCELE__"); 7431 Builder.defineMacro("__TCELE_V1__"); 7432 } 7433 7434 }; 7435 7436 class BPFTargetInfo : public TargetInfo { 7437 public: 7438 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7439 : TargetInfo(Triple) { 7440 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7441 SizeType = UnsignedLong; 7442 PtrDiffType = SignedLong; 7443 IntPtrType = SignedLong; 7444 IntMaxType = SignedLong; 7445 Int64Type = SignedLong; 7446 RegParmMax = 5; 7447 if (Triple.getArch() == llvm::Triple::bpfeb) { 7448 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7449 } else { 7450 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7451 } 7452 MaxAtomicPromoteWidth = 64; 7453 MaxAtomicInlineWidth = 64; 7454 TLSSupported = false; 7455 } 7456 void getTargetDefines(const LangOptions &Opts, 7457 MacroBuilder &Builder) const override { 7458 DefineStd(Builder, "bpf", Opts); 7459 Builder.defineMacro("__BPF__"); 7460 } 7461 bool hasFeature(StringRef Feature) const override { 7462 return Feature == "bpf"; 7463 } 7464 7465 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7466 const char *getClobbers() const override { 7467 return ""; 7468 } 7469 BuiltinVaListKind getBuiltinVaListKind() const override { 7470 return TargetInfo::VoidPtrBuiltinVaList; 7471 } 7472 ArrayRef<const char *> getGCCRegNames() const override { 7473 return None; 7474 } 7475 bool validateAsmConstraint(const char *&Name, 7476 TargetInfo::ConstraintInfo &info) const override { 7477 return true; 7478 } 7479 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7480 return None; 7481 } 7482 }; 7483 7484 class MipsTargetInfo : public TargetInfo { 7485 void setDataLayout() { 7486 StringRef Layout; 7487 7488 if (ABI == "o32") 7489 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7490 else if (ABI == "n32") 7491 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7492 else if (ABI == "n64") 7493 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7494 else 7495 llvm_unreachable("Invalid ABI"); 7496 7497 if (BigEndian) 7498 resetDataLayout(("E-" + Layout).str()); 7499 else 7500 resetDataLayout(("e-" + Layout).str()); 7501 } 7502 7503 7504 static const Builtin::Info BuiltinInfo[]; 7505 std::string CPU; 7506 bool IsMips16; 7507 bool IsMicromips; 7508 bool IsNan2008; 7509 bool IsSingleFloat; 7510 bool IsNoABICalls; 7511 bool CanUseBSDABICalls; 7512 enum MipsFloatABI { 7513 HardFloat, SoftFloat 7514 } FloatABI; 7515 enum DspRevEnum { 7516 NoDSP, DSP1, DSP2 7517 } DspRev; 7518 bool HasMSA; 7519 7520 protected: 7521 bool HasFP64; 7522 std::string ABI; 7523 7524 public: 7525 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7526 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7527 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 7528 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 7529 HasMSA(false), HasFP64(false) { 7530 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7531 7532 setABI((getTriple().getArch() == llvm::Triple::mips || 7533 getTriple().getArch() == llvm::Triple::mipsel) 7534 ? "o32" 7535 : "n64"); 7536 7537 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7538 7539 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 7540 Triple.getOS() == llvm::Triple::OpenBSD; 7541 } 7542 7543 bool isNaN2008Default() const { 7544 return CPU == "mips32r6" || CPU == "mips64r6"; 7545 } 7546 7547 bool isFP64Default() const { 7548 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7549 } 7550 7551 bool isNan2008() const override { 7552 return IsNan2008; 7553 } 7554 7555 bool processorSupportsGPR64() const { 7556 return llvm::StringSwitch<bool>(CPU) 7557 .Case("mips3", true) 7558 .Case("mips4", true) 7559 .Case("mips5", true) 7560 .Case("mips64", true) 7561 .Case("mips64r2", true) 7562 .Case("mips64r3", true) 7563 .Case("mips64r5", true) 7564 .Case("mips64r6", true) 7565 .Case("octeon", true) 7566 .Default(false); 7567 return false; 7568 } 7569 7570 StringRef getABI() const override { return ABI; } 7571 bool setABI(const std::string &Name) override { 7572 if (Name == "o32") { 7573 setO32ABITypes(); 7574 ABI = Name; 7575 return true; 7576 } 7577 7578 if (Name == "n32") { 7579 setN32ABITypes(); 7580 ABI = Name; 7581 return true; 7582 } 7583 if (Name == "n64") { 7584 setN64ABITypes(); 7585 ABI = Name; 7586 return true; 7587 } 7588 return false; 7589 } 7590 7591 void setO32ABITypes() { 7592 Int64Type = SignedLongLong; 7593 IntMaxType = Int64Type; 7594 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7595 LongDoubleWidth = LongDoubleAlign = 64; 7596 LongWidth = LongAlign = 32; 7597 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7598 PointerWidth = PointerAlign = 32; 7599 PtrDiffType = SignedInt; 7600 SizeType = UnsignedInt; 7601 SuitableAlign = 64; 7602 } 7603 7604 void setN32N64ABITypes() { 7605 LongDoubleWidth = LongDoubleAlign = 128; 7606 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7607 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7608 LongDoubleWidth = LongDoubleAlign = 64; 7609 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7610 } 7611 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7612 SuitableAlign = 128; 7613 } 7614 7615 void setN64ABITypes() { 7616 setN32N64ABITypes(); 7617 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 7618 Int64Type = SignedLongLong; 7619 } else { 7620 Int64Type = SignedLong; 7621 } 7622 IntMaxType = Int64Type; 7623 LongWidth = LongAlign = 64; 7624 PointerWidth = PointerAlign = 64; 7625 PtrDiffType = SignedLong; 7626 SizeType = UnsignedLong; 7627 } 7628 7629 void setN32ABITypes() { 7630 setN32N64ABITypes(); 7631 Int64Type = SignedLongLong; 7632 IntMaxType = Int64Type; 7633 LongWidth = LongAlign = 32; 7634 PointerWidth = PointerAlign = 32; 7635 PtrDiffType = SignedInt; 7636 SizeType = UnsignedInt; 7637 } 7638 7639 bool setCPU(const std::string &Name) override { 7640 CPU = Name; 7641 return llvm::StringSwitch<bool>(Name) 7642 .Case("mips1", true) 7643 .Case("mips2", true) 7644 .Case("mips3", true) 7645 .Case("mips4", true) 7646 .Case("mips5", true) 7647 .Case("mips32", true) 7648 .Case("mips32r2", true) 7649 .Case("mips32r3", true) 7650 .Case("mips32r5", true) 7651 .Case("mips32r6", true) 7652 .Case("mips64", true) 7653 .Case("mips64r2", true) 7654 .Case("mips64r3", true) 7655 .Case("mips64r5", true) 7656 .Case("mips64r6", true) 7657 .Case("octeon", true) 7658 .Case("p5600", true) 7659 .Default(false); 7660 } 7661 const std::string& getCPU() const { return CPU; } 7662 bool 7663 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7664 StringRef CPU, 7665 const std::vector<std::string> &FeaturesVec) const override { 7666 if (CPU.empty()) 7667 CPU = getCPU(); 7668 if (CPU == "octeon") 7669 Features["mips64r2"] = Features["cnmips"] = true; 7670 else 7671 Features[CPU] = true; 7672 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7673 } 7674 7675 void getTargetDefines(const LangOptions &Opts, 7676 MacroBuilder &Builder) const override { 7677 if (BigEndian) { 7678 DefineStd(Builder, "MIPSEB", Opts); 7679 Builder.defineMacro("_MIPSEB"); 7680 } else { 7681 DefineStd(Builder, "MIPSEL", Opts); 7682 Builder.defineMacro("_MIPSEL"); 7683 } 7684 7685 Builder.defineMacro("__mips__"); 7686 Builder.defineMacro("_mips"); 7687 if (Opts.GNUMode) 7688 Builder.defineMacro("mips"); 7689 7690 if (ABI == "o32") { 7691 Builder.defineMacro("__mips", "32"); 7692 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7693 } else { 7694 Builder.defineMacro("__mips", "64"); 7695 Builder.defineMacro("__mips64"); 7696 Builder.defineMacro("__mips64__"); 7697 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7698 } 7699 7700 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7701 .Cases("mips32", "mips64", "1") 7702 .Cases("mips32r2", "mips64r2", "2") 7703 .Cases("mips32r3", "mips64r3", "3") 7704 .Cases("mips32r5", "mips64r5", "5") 7705 .Cases("mips32r6", "mips64r6", "6") 7706 .Default(""); 7707 if (!ISARev.empty()) 7708 Builder.defineMacro("__mips_isa_rev", ISARev); 7709 7710 if (ABI == "o32") { 7711 Builder.defineMacro("__mips_o32"); 7712 Builder.defineMacro("_ABIO32", "1"); 7713 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7714 } else if (ABI == "n32") { 7715 Builder.defineMacro("__mips_n32"); 7716 Builder.defineMacro("_ABIN32", "2"); 7717 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7718 } else if (ABI == "n64") { 7719 Builder.defineMacro("__mips_n64"); 7720 Builder.defineMacro("_ABI64", "3"); 7721 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7722 } else 7723 llvm_unreachable("Invalid ABI."); 7724 7725 if (!IsNoABICalls) { 7726 Builder.defineMacro("__mips_abicalls"); 7727 if (CanUseBSDABICalls) 7728 Builder.defineMacro("__ABICALLS__"); 7729 } 7730 7731 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7732 7733 switch (FloatABI) { 7734 case HardFloat: 7735 Builder.defineMacro("__mips_hard_float", Twine(1)); 7736 break; 7737 case SoftFloat: 7738 Builder.defineMacro("__mips_soft_float", Twine(1)); 7739 break; 7740 } 7741 7742 if (IsSingleFloat) 7743 Builder.defineMacro("__mips_single_float", Twine(1)); 7744 7745 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7746 Builder.defineMacro("_MIPS_FPSET", 7747 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7748 7749 if (IsMips16) 7750 Builder.defineMacro("__mips16", Twine(1)); 7751 7752 if (IsMicromips) 7753 Builder.defineMacro("__mips_micromips", Twine(1)); 7754 7755 if (IsNan2008) 7756 Builder.defineMacro("__mips_nan2008", Twine(1)); 7757 7758 switch (DspRev) { 7759 default: 7760 break; 7761 case DSP1: 7762 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7763 Builder.defineMacro("__mips_dsp", Twine(1)); 7764 break; 7765 case DSP2: 7766 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7767 Builder.defineMacro("__mips_dspr2", Twine(1)); 7768 Builder.defineMacro("__mips_dsp", Twine(1)); 7769 break; 7770 } 7771 7772 if (HasMSA) 7773 Builder.defineMacro("__mips_msa", Twine(1)); 7774 7775 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7776 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7777 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7778 7779 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7780 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7781 7782 // These shouldn't be defined for MIPS-I but there's no need to check 7783 // for that since MIPS-I isn't supported. 7784 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7785 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7786 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7787 7788 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7789 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7790 // the instructions exist but using them violates the ABI since they 7791 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7792 if (ABI == "n32" || ABI == "n64") 7793 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7794 } 7795 7796 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7797 return llvm::makeArrayRef(BuiltinInfo, 7798 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7799 } 7800 bool hasFeature(StringRef Feature) const override { 7801 return llvm::StringSwitch<bool>(Feature) 7802 .Case("mips", true) 7803 .Case("fp64", HasFP64) 7804 .Default(false); 7805 } 7806 BuiltinVaListKind getBuiltinVaListKind() const override { 7807 return TargetInfo::VoidPtrBuiltinVaList; 7808 } 7809 ArrayRef<const char *> getGCCRegNames() const override { 7810 static const char *const GCCRegNames[] = { 7811 // CPU register names 7812 // Must match second column of GCCRegAliases 7813 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7814 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7815 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7816 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7817 // Floating point register names 7818 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7819 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7820 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7821 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7822 // Hi/lo and condition register names 7823 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7824 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7825 "$ac3hi","$ac3lo", 7826 // MSA register names 7827 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7828 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7829 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7830 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7831 // MSA control register names 7832 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7833 "$msarequest", "$msamap", "$msaunmap" 7834 }; 7835 return llvm::makeArrayRef(GCCRegNames); 7836 } 7837 bool validateAsmConstraint(const char *&Name, 7838 TargetInfo::ConstraintInfo &Info) const override { 7839 switch (*Name) { 7840 default: 7841 return false; 7842 case 'r': // CPU registers. 7843 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7844 case 'y': // Equivalent to "r", backward compatibility only. 7845 case 'f': // floating-point registers. 7846 case 'c': // $25 for indirect jumps 7847 case 'l': // lo register 7848 case 'x': // hilo register pair 7849 Info.setAllowsRegister(); 7850 return true; 7851 case 'I': // Signed 16-bit constant 7852 case 'J': // Integer 0 7853 case 'K': // Unsigned 16-bit constant 7854 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7855 case 'M': // Constants not loadable via lui, addiu, or ori 7856 case 'N': // Constant -1 to -65535 7857 case 'O': // A signed 15-bit constant 7858 case 'P': // A constant between 1 go 65535 7859 return true; 7860 case 'R': // An address that can be used in a non-macro load or store 7861 Info.setAllowsMemory(); 7862 return true; 7863 case 'Z': 7864 if (Name[1] == 'C') { // An address usable by ll, and sc. 7865 Info.setAllowsMemory(); 7866 Name++; // Skip over 'Z'. 7867 return true; 7868 } 7869 return false; 7870 } 7871 } 7872 7873 std::string convertConstraint(const char *&Constraint) const override { 7874 std::string R; 7875 switch (*Constraint) { 7876 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7877 if (Constraint[1] == 'C') { 7878 R = std::string("^") + std::string(Constraint, 2); 7879 Constraint++; 7880 return R; 7881 } 7882 break; 7883 } 7884 return TargetInfo::convertConstraint(Constraint); 7885 } 7886 7887 const char *getClobbers() const override { 7888 // In GCC, $1 is not widely used in generated code (it's used only in a few 7889 // specific situations), so there is no real need for users to add it to 7890 // the clobbers list if they want to use it in their inline assembly code. 7891 // 7892 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7893 // code generation, so using it in inline assembly without adding it to the 7894 // clobbers list can cause conflicts between the inline assembly code and 7895 // the surrounding generated code. 7896 // 7897 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7898 // operands, which will conflict with the ".set at" assembler option (which 7899 // we use only for inline assembly, in order to maintain compatibility with 7900 // GCC) and will also conflict with the user's usage of $1. 7901 // 7902 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7903 // register for generated code is to automatically clobber $1 for all inline 7904 // assembly code. 7905 // 7906 // FIXME: We should automatically clobber $1 only for inline assembly code 7907 // which actually uses it. This would allow LLVM to use $1 for inline 7908 // assembly operands if the user's assembly code doesn't use it. 7909 return "~{$1}"; 7910 } 7911 7912 bool handleTargetFeatures(std::vector<std::string> &Features, 7913 DiagnosticsEngine &Diags) override { 7914 IsMips16 = false; 7915 IsMicromips = false; 7916 IsNan2008 = isNaN2008Default(); 7917 IsSingleFloat = false; 7918 FloatABI = HardFloat; 7919 DspRev = NoDSP; 7920 HasFP64 = isFP64Default(); 7921 7922 for (const auto &Feature : Features) { 7923 if (Feature == "+single-float") 7924 IsSingleFloat = true; 7925 else if (Feature == "+soft-float") 7926 FloatABI = SoftFloat; 7927 else if (Feature == "+mips16") 7928 IsMips16 = true; 7929 else if (Feature == "+micromips") 7930 IsMicromips = true; 7931 else if (Feature == "+dsp") 7932 DspRev = std::max(DspRev, DSP1); 7933 else if (Feature == "+dspr2") 7934 DspRev = std::max(DspRev, DSP2); 7935 else if (Feature == "+msa") 7936 HasMSA = true; 7937 else if (Feature == "+fp64") 7938 HasFP64 = true; 7939 else if (Feature == "-fp64") 7940 HasFP64 = false; 7941 else if (Feature == "+nan2008") 7942 IsNan2008 = true; 7943 else if (Feature == "-nan2008") 7944 IsNan2008 = false; 7945 else if (Feature == "+noabicalls") 7946 IsNoABICalls = true; 7947 } 7948 7949 setDataLayout(); 7950 7951 return true; 7952 } 7953 7954 int getEHDataRegisterNumber(unsigned RegNo) const override { 7955 if (RegNo == 0) return 4; 7956 if (RegNo == 1) return 5; 7957 return -1; 7958 } 7959 7960 bool isCLZForZeroUndef() const override { return false; } 7961 7962 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7963 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7964 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7965 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7966 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7967 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7968 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7969 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7970 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7971 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7972 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7973 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7974 {{"ra"}, "$31"}}; 7975 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7976 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7977 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7978 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7979 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7980 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7981 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7982 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7983 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7984 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7985 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7986 {{"ra"}, "$31"}}; 7987 if (ABI == "o32") 7988 return llvm::makeArrayRef(O32RegAliases); 7989 return llvm::makeArrayRef(NewABIRegAliases); 7990 } 7991 7992 bool hasInt128Type() const override { 7993 return ABI == "n32" || ABI == "n64"; 7994 } 7995 7996 bool validateTarget(DiagnosticsEngine &Diags) const override { 7997 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7998 // this yet. It's better to fail here than on the backend assertion. 7999 if (processorSupportsGPR64() && ABI == "o32") { 8000 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8001 return false; 8002 } 8003 8004 // 64-bit ABI's require 64-bit CPU's. 8005 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 8006 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8007 return false; 8008 } 8009 8010 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 8011 // can't handle this yet. It's better to fail here than on the 8012 // backend assertion. 8013 if ((getTriple().getArch() == llvm::Triple::mips64 || 8014 getTriple().getArch() == llvm::Triple::mips64el) && 8015 ABI == "o32") { 8016 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8017 << ABI << getTriple().str(); 8018 return false; 8019 } 8020 8021 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 8022 // can't handle this yet. It's better to fail here than on the 8023 // backend assertion. 8024 if ((getTriple().getArch() == llvm::Triple::mips || 8025 getTriple().getArch() == llvm::Triple::mipsel) && 8026 (ABI == "n32" || ABI == "n64")) { 8027 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8028 << ABI << getTriple().str(); 8029 return false; 8030 } 8031 8032 return true; 8033 } 8034 }; 8035 8036 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 8037 #define BUILTIN(ID, TYPE, ATTRS) \ 8038 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8039 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8040 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8041 #include "clang/Basic/BuiltinsMips.def" 8042 }; 8043 8044 class PNaClTargetInfo : public TargetInfo { 8045 public: 8046 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8047 : TargetInfo(Triple) { 8048 this->LongAlign = 32; 8049 this->LongWidth = 32; 8050 this->PointerAlign = 32; 8051 this->PointerWidth = 32; 8052 this->IntMaxType = TargetInfo::SignedLongLong; 8053 this->Int64Type = TargetInfo::SignedLongLong; 8054 this->DoubleAlign = 64; 8055 this->LongDoubleWidth = 64; 8056 this->LongDoubleAlign = 64; 8057 this->SizeType = TargetInfo::UnsignedInt; 8058 this->PtrDiffType = TargetInfo::SignedInt; 8059 this->IntPtrType = TargetInfo::SignedInt; 8060 this->RegParmMax = 0; // Disallow regparm 8061 } 8062 8063 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8064 Builder.defineMacro("__le32__"); 8065 Builder.defineMacro("__pnacl__"); 8066 } 8067 void getTargetDefines(const LangOptions &Opts, 8068 MacroBuilder &Builder) const override { 8069 getArchDefines(Opts, Builder); 8070 } 8071 bool hasFeature(StringRef Feature) const override { 8072 return Feature == "pnacl"; 8073 } 8074 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8075 BuiltinVaListKind getBuiltinVaListKind() const override { 8076 return TargetInfo::PNaClABIBuiltinVaList; 8077 } 8078 ArrayRef<const char *> getGCCRegNames() const override; 8079 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8080 bool validateAsmConstraint(const char *&Name, 8081 TargetInfo::ConstraintInfo &Info) const override { 8082 return false; 8083 } 8084 8085 const char *getClobbers() const override { 8086 return ""; 8087 } 8088 }; 8089 8090 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8091 return None; 8092 } 8093 8094 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8095 return None; 8096 } 8097 8098 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8099 class NaClMips32TargetInfo : public MipsTargetInfo { 8100 public: 8101 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8102 : MipsTargetInfo(Triple, Opts) {} 8103 8104 BuiltinVaListKind getBuiltinVaListKind() const override { 8105 return TargetInfo::PNaClABIBuiltinVaList; 8106 } 8107 }; 8108 8109 class Le64TargetInfo : public TargetInfo { 8110 static const Builtin::Info BuiltinInfo[]; 8111 8112 public: 8113 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8114 : TargetInfo(Triple) { 8115 NoAsmVariants = true; 8116 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8117 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8118 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8119 } 8120 8121 void getTargetDefines(const LangOptions &Opts, 8122 MacroBuilder &Builder) const override { 8123 DefineStd(Builder, "unix", Opts); 8124 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8125 Builder.defineMacro("__ELF__"); 8126 } 8127 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8128 return llvm::makeArrayRef(BuiltinInfo, 8129 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8130 } 8131 BuiltinVaListKind getBuiltinVaListKind() const override { 8132 return TargetInfo::PNaClABIBuiltinVaList; 8133 } 8134 const char *getClobbers() const override { return ""; } 8135 ArrayRef<const char *> getGCCRegNames() const override { 8136 return None; 8137 } 8138 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8139 return None; 8140 } 8141 bool validateAsmConstraint(const char *&Name, 8142 TargetInfo::ConstraintInfo &Info) const override { 8143 return false; 8144 } 8145 8146 bool hasProtectedVisibility() const override { return false; } 8147 }; 8148 8149 class WebAssemblyTargetInfo : public TargetInfo { 8150 static const Builtin::Info BuiltinInfo[]; 8151 8152 enum SIMDEnum { 8153 NoSIMD, 8154 SIMD128, 8155 } SIMDLevel; 8156 8157 public: 8158 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8159 : TargetInfo(T), SIMDLevel(NoSIMD) { 8160 NoAsmVariants = true; 8161 SuitableAlign = 128; 8162 LargeArrayMinWidth = 128; 8163 LargeArrayAlign = 128; 8164 SimdDefaultAlign = 128; 8165 SigAtomicType = SignedLong; 8166 LongDoubleWidth = LongDoubleAlign = 128; 8167 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8168 SizeType = UnsignedInt; 8169 PtrDiffType = SignedInt; 8170 IntPtrType = SignedInt; 8171 } 8172 8173 protected: 8174 void getTargetDefines(const LangOptions &Opts, 8175 MacroBuilder &Builder) const override { 8176 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8177 if (SIMDLevel >= SIMD128) 8178 Builder.defineMacro("__wasm_simd128__"); 8179 } 8180 8181 private: 8182 bool 8183 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8184 StringRef CPU, 8185 const std::vector<std::string> &FeaturesVec) const override { 8186 if (CPU == "bleeding-edge") 8187 Features["simd128"] = true; 8188 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8189 } 8190 bool hasFeature(StringRef Feature) const final { 8191 return llvm::StringSwitch<bool>(Feature) 8192 .Case("simd128", SIMDLevel >= SIMD128) 8193 .Default(false); 8194 } 8195 bool handleTargetFeatures(std::vector<std::string> &Features, 8196 DiagnosticsEngine &Diags) final { 8197 for (const auto &Feature : Features) { 8198 if (Feature == "+simd128") { 8199 SIMDLevel = std::max(SIMDLevel, SIMD128); 8200 continue; 8201 } 8202 if (Feature == "-simd128") { 8203 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8204 continue; 8205 } 8206 8207 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8208 << "-target-feature"; 8209 return false; 8210 } 8211 return true; 8212 } 8213 bool setCPU(const std::string &Name) final { 8214 return llvm::StringSwitch<bool>(Name) 8215 .Case("mvp", true) 8216 .Case("bleeding-edge", true) 8217 .Case("generic", true) 8218 .Default(false); 8219 } 8220 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8221 return llvm::makeArrayRef(BuiltinInfo, 8222 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8223 } 8224 BuiltinVaListKind getBuiltinVaListKind() const final { 8225 return VoidPtrBuiltinVaList; 8226 } 8227 ArrayRef<const char *> getGCCRegNames() const final { 8228 return None; 8229 } 8230 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8231 return None; 8232 } 8233 bool 8234 validateAsmConstraint(const char *&Name, 8235 TargetInfo::ConstraintInfo &Info) const final { 8236 return false; 8237 } 8238 const char *getClobbers() const final { return ""; } 8239 bool isCLZForZeroUndef() const final { return false; } 8240 bool hasInt128Type() const final { return true; } 8241 IntType getIntTypeByWidth(unsigned BitWidth, 8242 bool IsSigned) const final { 8243 // WebAssembly prefers long long for explicitly 64-bit integers. 8244 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8245 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8246 } 8247 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8248 bool IsSigned) const final { 8249 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8250 return BitWidth == 64 8251 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8252 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8253 } 8254 }; 8255 8256 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8257 #define BUILTIN(ID, TYPE, ATTRS) \ 8258 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8259 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8260 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8261 #include "clang/Basic/BuiltinsWebAssembly.def" 8262 }; 8263 8264 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8265 public: 8266 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8267 const TargetOptions &Opts) 8268 : WebAssemblyTargetInfo(T, Opts) { 8269 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8270 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8271 } 8272 8273 protected: 8274 void getTargetDefines(const LangOptions &Opts, 8275 MacroBuilder &Builder) const override { 8276 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8277 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8278 } 8279 }; 8280 8281 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8282 public: 8283 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8284 const TargetOptions &Opts) 8285 : WebAssemblyTargetInfo(T, Opts) { 8286 LongAlign = LongWidth = 64; 8287 PointerAlign = PointerWidth = 64; 8288 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8289 SizeType = UnsignedLong; 8290 PtrDiffType = SignedLong; 8291 IntPtrType = SignedLong; 8292 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8293 } 8294 8295 protected: 8296 void getTargetDefines(const LangOptions &Opts, 8297 MacroBuilder &Builder) const override { 8298 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8299 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8300 } 8301 }; 8302 8303 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8304 #define BUILTIN(ID, TYPE, ATTRS) \ 8305 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8306 #include "clang/Basic/BuiltinsLe64.def" 8307 }; 8308 8309 static const unsigned SPIRAddrSpaceMap[] = { 8310 1, // opencl_global 8311 3, // opencl_local 8312 2, // opencl_constant 8313 4, // opencl_generic 8314 0, // cuda_device 8315 0, // cuda_constant 8316 0 // cuda_shared 8317 }; 8318 class SPIRTargetInfo : public TargetInfo { 8319 public: 8320 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8321 : TargetInfo(Triple) { 8322 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8323 "SPIR target must use unknown OS"); 8324 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8325 "SPIR target must use unknown environment type"); 8326 TLSSupported = false; 8327 LongWidth = LongAlign = 64; 8328 AddrSpaceMap = &SPIRAddrSpaceMap; 8329 UseAddrSpaceMapMangling = true; 8330 // Define available target features 8331 // These must be defined in sorted order! 8332 NoAsmVariants = true; 8333 } 8334 void getTargetDefines(const LangOptions &Opts, 8335 MacroBuilder &Builder) const override { 8336 DefineStd(Builder, "SPIR", Opts); 8337 } 8338 bool hasFeature(StringRef Feature) const override { 8339 return Feature == "spir"; 8340 } 8341 8342 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8343 const char *getClobbers() const override { return ""; } 8344 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8345 bool validateAsmConstraint(const char *&Name, 8346 TargetInfo::ConstraintInfo &info) const override { 8347 return true; 8348 } 8349 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8350 return None; 8351 } 8352 BuiltinVaListKind getBuiltinVaListKind() const override { 8353 return TargetInfo::VoidPtrBuiltinVaList; 8354 } 8355 8356 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8357 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8358 : CCCR_Warning; 8359 } 8360 8361 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8362 return CC_SpirFunction; 8363 } 8364 8365 void setSupportedOpenCLOpts() override { 8366 // Assume all OpenCL extensions and optional core features are supported 8367 // for SPIR since it is a generic target. 8368 getSupportedOpenCLOpts().supportAll(); 8369 } 8370 }; 8371 8372 class SPIR32TargetInfo : public SPIRTargetInfo { 8373 public: 8374 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8375 : SPIRTargetInfo(Triple, Opts) { 8376 PointerWidth = PointerAlign = 32; 8377 SizeType = TargetInfo::UnsignedInt; 8378 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8379 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8380 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8381 } 8382 void getTargetDefines(const LangOptions &Opts, 8383 MacroBuilder &Builder) const override { 8384 DefineStd(Builder, "SPIR32", Opts); 8385 } 8386 }; 8387 8388 class SPIR64TargetInfo : public SPIRTargetInfo { 8389 public: 8390 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8391 : SPIRTargetInfo(Triple, Opts) { 8392 PointerWidth = PointerAlign = 64; 8393 SizeType = TargetInfo::UnsignedLong; 8394 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8395 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8396 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8397 } 8398 void getTargetDefines(const LangOptions &Opts, 8399 MacroBuilder &Builder) const override { 8400 DefineStd(Builder, "SPIR64", Opts); 8401 } 8402 }; 8403 8404 class XCoreTargetInfo : public TargetInfo { 8405 static const Builtin::Info BuiltinInfo[]; 8406 public: 8407 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8408 : TargetInfo(Triple) { 8409 NoAsmVariants = true; 8410 LongLongAlign = 32; 8411 SuitableAlign = 32; 8412 DoubleAlign = LongDoubleAlign = 32; 8413 SizeType = UnsignedInt; 8414 PtrDiffType = SignedInt; 8415 IntPtrType = SignedInt; 8416 WCharType = UnsignedChar; 8417 WIntType = UnsignedInt; 8418 UseZeroLengthBitfieldAlignment = true; 8419 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8420 "-f64:32-a:0:32-n32"); 8421 } 8422 void getTargetDefines(const LangOptions &Opts, 8423 MacroBuilder &Builder) const override { 8424 Builder.defineMacro("__XS1B__"); 8425 } 8426 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8427 return llvm::makeArrayRef(BuiltinInfo, 8428 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8429 } 8430 BuiltinVaListKind getBuiltinVaListKind() const override { 8431 return TargetInfo::VoidPtrBuiltinVaList; 8432 } 8433 const char *getClobbers() const override { 8434 return ""; 8435 } 8436 ArrayRef<const char *> getGCCRegNames() const override { 8437 static const char * const GCCRegNames[] = { 8438 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8439 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8440 }; 8441 return llvm::makeArrayRef(GCCRegNames); 8442 } 8443 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8444 return None; 8445 } 8446 bool validateAsmConstraint(const char *&Name, 8447 TargetInfo::ConstraintInfo &Info) const override { 8448 return false; 8449 } 8450 int getEHDataRegisterNumber(unsigned RegNo) const override { 8451 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8452 return (RegNo < 2)? RegNo : -1; 8453 } 8454 bool allowsLargerPreferedTypeAlignment() const override { 8455 return false; 8456 } 8457 }; 8458 8459 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8460 #define BUILTIN(ID, TYPE, ATTRS) \ 8461 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8462 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8463 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8464 #include "clang/Basic/BuiltinsXCore.def" 8465 }; 8466 8467 // x86_32 Android target 8468 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8469 public: 8470 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8471 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8472 SuitableAlign = 32; 8473 LongDoubleWidth = 64; 8474 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8475 } 8476 }; 8477 8478 // x86_64 Android target 8479 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8480 public: 8481 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8482 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8483 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8484 } 8485 8486 bool useFloat128ManglingForLongDouble() const override { 8487 return true; 8488 } 8489 }; 8490 8491 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8492 class RenderScript32TargetInfo : public ARMleTargetInfo { 8493 public: 8494 RenderScript32TargetInfo(const llvm::Triple &Triple, 8495 const TargetOptions &Opts) 8496 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8497 Triple.getOSName(), 8498 Triple.getEnvironmentName()), 8499 Opts) { 8500 IsRenderScriptTarget = true; 8501 LongWidth = LongAlign = 64; 8502 } 8503 void getTargetDefines(const LangOptions &Opts, 8504 MacroBuilder &Builder) const override { 8505 Builder.defineMacro("__RENDERSCRIPT__"); 8506 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8507 } 8508 }; 8509 8510 // 64-bit RenderScript is aarch64 8511 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8512 public: 8513 RenderScript64TargetInfo(const llvm::Triple &Triple, 8514 const TargetOptions &Opts) 8515 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8516 Triple.getOSName(), 8517 Triple.getEnvironmentName()), 8518 Opts) { 8519 IsRenderScriptTarget = true; 8520 } 8521 8522 void getTargetDefines(const LangOptions &Opts, 8523 MacroBuilder &Builder) const override { 8524 Builder.defineMacro("__RENDERSCRIPT__"); 8525 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8526 } 8527 }; 8528 8529 /// Information about a specific microcontroller. 8530 struct MCUInfo { 8531 const char *Name; 8532 const char *DefineName; 8533 }; 8534 8535 // This list should be kept up-to-date with AVRDevices.td in LLVM. 8536 static ArrayRef<MCUInfo> AVRMcus = { 8537 { "at90s1200", "__AVR_AT90S1200__" }, 8538 { "attiny11", "__AVR_ATtiny11__" }, 8539 { "attiny12", "__AVR_ATtiny12__" }, 8540 { "attiny15", "__AVR_ATtiny15__" }, 8541 { "attiny28", "__AVR_ATtiny28__" }, 8542 { "at90s2313", "__AVR_AT90S2313__" }, 8543 { "at90s2323", "__AVR_AT90S2323__" }, 8544 { "at90s2333", "__AVR_AT90S2333__" }, 8545 { "at90s2343", "__AVR_AT90S2343__" }, 8546 { "attiny22", "__AVR_ATtiny22__" }, 8547 { "attiny26", "__AVR_ATtiny26__" }, 8548 { "at86rf401", "__AVR_AT86RF401__" }, 8549 { "at90s4414", "__AVR_AT90S4414__" }, 8550 { "at90s4433", "__AVR_AT90S4433__" }, 8551 { "at90s4434", "__AVR_AT90S4434__" }, 8552 { "at90s8515", "__AVR_AT90S8515__" }, 8553 { "at90c8534", "__AVR_AT90c8534__" }, 8554 { "at90s8535", "__AVR_AT90S8535__" }, 8555 { "ata5272", "__AVR_ATA5272__" }, 8556 { "attiny13", "__AVR_ATtiny13__" }, 8557 { "attiny13a", "__AVR_ATtiny13A__" }, 8558 { "attiny2313", "__AVR_ATtiny2313__" }, 8559 { "attiny2313a", "__AVR_ATtiny2313A__" }, 8560 { "attiny24", "__AVR_ATtiny24__" }, 8561 { "attiny24a", "__AVR_ATtiny24A__" }, 8562 { "attiny4313", "__AVR_ATtiny4313__" }, 8563 { "attiny44", "__AVR_ATtiny44__" }, 8564 { "attiny44a", "__AVR_ATtiny44A__" }, 8565 { "attiny84", "__AVR_ATtiny84__" }, 8566 { "attiny84a", "__AVR_ATtiny84A__" }, 8567 { "attiny25", "__AVR_ATtiny25__" }, 8568 { "attiny45", "__AVR_ATtiny45__" }, 8569 { "attiny85", "__AVR_ATtiny85__" }, 8570 { "attiny261", "__AVR_ATtiny261__" }, 8571 { "attiny261a", "__AVR_ATtiny261A__" }, 8572 { "attiny461", "__AVR_ATtiny461__" }, 8573 { "attiny461a", "__AVR_ATtiny461A__" }, 8574 { "attiny861", "__AVR_ATtiny861__" }, 8575 { "attiny861a", "__AVR_ATtiny861A__" }, 8576 { "attiny87", "__AVR_ATtiny87__" }, 8577 { "attiny43u", "__AVR_ATtiny43U__" }, 8578 { "attiny48", "__AVR_ATtiny48__" }, 8579 { "attiny88", "__AVR_ATtiny88__" }, 8580 { "attiny828", "__AVR_ATtiny828__" }, 8581 { "at43usb355", "__AVR_AT43USB355__" }, 8582 { "at76c711", "__AVR_AT76C711__" }, 8583 { "atmega103", "__AVR_ATmega103__" }, 8584 { "at43usb320", "__AVR_AT43USB320__" }, 8585 { "attiny167", "__AVR_ATtiny167__" }, 8586 { "at90usb82", "__AVR_AT90USB82__" }, 8587 { "at90usb162", "__AVR_AT90USB162__" }, 8588 { "ata5505", "__AVR_ATA5505__" }, 8589 { "atmega8u2", "__AVR_ATmega8U2__" }, 8590 { "atmega16u2", "__AVR_ATmega16U2__" }, 8591 { "atmega32u2", "__AVR_ATmega32U2__" }, 8592 { "attiny1634", "__AVR_ATtiny1634__" }, 8593 { "atmega8", "__AVR_ATmega8__" }, 8594 { "ata6289", "__AVR_ATA6289__" }, 8595 { "atmega8a", "__AVR_ATmega8A__" }, 8596 { "ata6285", "__AVR_ATA6285__" }, 8597 { "ata6286", "__AVR_ATA6286__" }, 8598 { "atmega48", "__AVR_ATmega48__" }, 8599 { "atmega48a", "__AVR_ATmega48A__" }, 8600 { "atmega48pa", "__AVR_ATmega48PA__" }, 8601 { "atmega48p", "__AVR_ATmega48P__" }, 8602 { "atmega88", "__AVR_ATmega88__" }, 8603 { "atmega88a", "__AVR_ATmega88A__" }, 8604 { "atmega88p", "__AVR_ATmega88P__" }, 8605 { "atmega88pa", "__AVR_ATmega88PA__" }, 8606 { "atmega8515", "__AVR_ATmega8515__" }, 8607 { "atmega8535", "__AVR_ATmega8535__" }, 8608 { "atmega8hva", "__AVR_ATmega8HVA__" }, 8609 { "at90pwm1", "__AVR_AT90PWM1__" }, 8610 { "at90pwm2", "__AVR_AT90PWM2__" }, 8611 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 8612 { "at90pwm3", "__AVR_AT90PWM3__" }, 8613 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 8614 { "at90pwm81", "__AVR_AT90PWM81__" }, 8615 { "ata5790", "__AVR_ATA5790__" }, 8616 { "ata5795", "__AVR_ATA5795__" }, 8617 { "atmega16", "__AVR_ATmega16__" }, 8618 { "atmega16a", "__AVR_ATmega16A__" }, 8619 { "atmega161", "__AVR_ATmega161__" }, 8620 { "atmega162", "__AVR_ATmega162__" }, 8621 { "atmega163", "__AVR_ATmega163__" }, 8622 { "atmega164a", "__AVR_ATmega164A__" }, 8623 { "atmega164p", "__AVR_ATmega164P__" }, 8624 { "atmega164pa", "__AVR_ATmega164PA__" }, 8625 { "atmega165", "__AVR_ATmega165__" }, 8626 { "atmega165a", "__AVR_ATmega165A__" }, 8627 { "atmega165p", "__AVR_ATmega165P__" }, 8628 { "atmega165pa", "__AVR_ATmega165PA__" }, 8629 { "atmega168", "__AVR_ATmega168__" }, 8630 { "atmega168a", "__AVR_ATmega168A__" }, 8631 { "atmega168p", "__AVR_ATmega168P__" }, 8632 { "atmega168pa", "__AVR_ATmega168PA__" }, 8633 { "atmega169", "__AVR_ATmega169__" }, 8634 { "atmega169a", "__AVR_ATmega169A__" }, 8635 { "atmega169p", "__AVR_ATmega169P__" }, 8636 { "atmega169pa", "__AVR_ATmega169PA__" }, 8637 { "atmega32", "__AVR_ATmega32__" }, 8638 { "atmega32a", "__AVR_ATmega32A__" }, 8639 { "atmega323", "__AVR_ATmega323__" }, 8640 { "atmega324a", "__AVR_ATmega324A__" }, 8641 { "atmega324p", "__AVR_ATmega324P__" }, 8642 { "atmega324pa", "__AVR_ATmega324PA__" }, 8643 { "atmega325", "__AVR_ATmega325__" }, 8644 { "atmega325a", "__AVR_ATmega325A__" }, 8645 { "atmega325p", "__AVR_ATmega325P__" }, 8646 { "atmega325pa", "__AVR_ATmega325PA__" }, 8647 { "atmega3250", "__AVR_ATmega3250__" }, 8648 { "atmega3250a", "__AVR_ATmega3250A__" }, 8649 { "atmega3250p", "__AVR_ATmega3250P__" }, 8650 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 8651 { "atmega328", "__AVR_ATmega328__" }, 8652 { "atmega328p", "__AVR_ATmega328P__" }, 8653 { "atmega329", "__AVR_ATmega329__" }, 8654 { "atmega329a", "__AVR_ATmega329A__" }, 8655 { "atmega329p", "__AVR_ATmega329P__" }, 8656 { "atmega329pa", "__AVR_ATmega329PA__" }, 8657 { "atmega3290", "__AVR_ATmega3290__" }, 8658 { "atmega3290a", "__AVR_ATmega3290A__" }, 8659 { "atmega3290p", "__AVR_ATmega3290P__" }, 8660 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 8661 { "atmega406", "__AVR_ATmega406__" }, 8662 { "atmega64", "__AVR_ATmega64__" }, 8663 { "atmega64a", "__AVR_ATmega64A__" }, 8664 { "atmega640", "__AVR_ATmega640__" }, 8665 { "atmega644", "__AVR_ATmega644__" }, 8666 { "atmega644a", "__AVR_ATmega644A__" }, 8667 { "atmega644p", "__AVR_ATmega644P__" }, 8668 { "atmega644pa", "__AVR_ATmega644PA__" }, 8669 { "atmega645", "__AVR_ATmega645__" }, 8670 { "atmega645a", "__AVR_ATmega645A__" }, 8671 { "atmega645p", "__AVR_ATmega645P__" }, 8672 { "atmega649", "__AVR_ATmega649__" }, 8673 { "atmega649a", "__AVR_ATmega649A__" }, 8674 { "atmega649p", "__AVR_ATmega649P__" }, 8675 { "atmega6450", "__AVR_ATmega6450__" }, 8676 { "atmega6450a", "__AVR_ATmega6450A__" }, 8677 { "atmega6450p", "__AVR_ATmega6450P__" }, 8678 { "atmega6490", "__AVR_ATmega6490__" }, 8679 { "atmega6490a", "__AVR_ATmega6490A__" }, 8680 { "atmega6490p", "__AVR_ATmega6490P__" }, 8681 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 8682 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 8683 { "atmega16hva", "__AVR_ATmega16HVA__" }, 8684 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 8685 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 8686 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 8687 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 8688 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 8689 { "atmega64hve", "__AVR_ATmega64HVE__" }, 8690 { "at90can32", "__AVR_AT90CAN32__" }, 8691 { "at90can64", "__AVR_AT90CAN64__" }, 8692 { "at90pwm161", "__AVR_AT90PWM161__" }, 8693 { "at90pwm216", "__AVR_AT90PWM216__" }, 8694 { "at90pwm316", "__AVR_AT90PWM316__" }, 8695 { "atmega32c1", "__AVR_ATmega32C1__" }, 8696 { "atmega64c1", "__AVR_ATmega64C1__" }, 8697 { "atmega16m1", "__AVR_ATmega16M1__" }, 8698 { "atmega32m1", "__AVR_ATmega32M1__" }, 8699 { "atmega64m1", "__AVR_ATmega64M1__" }, 8700 { "atmega16u4", "__AVR_ATmega16U4__" }, 8701 { "atmega32u4", "__AVR_ATmega32U4__" }, 8702 { "atmega32u6", "__AVR_ATmega32U6__" }, 8703 { "at90usb646", "__AVR_AT90USB646__" }, 8704 { "at90usb647", "__AVR_AT90USB647__" }, 8705 { "at90scr100", "__AVR_AT90SCR100__" }, 8706 { "at94k", "__AVR_AT94K__" }, 8707 { "m3000", "__AVR_AT000__" }, 8708 { "atmega128", "__AVR_ATmega128__" }, 8709 { "atmega128a", "__AVR_ATmega128A__" }, 8710 { "atmega1280", "__AVR_ATmega1280__" }, 8711 { "atmega1281", "__AVR_ATmega1281__" }, 8712 { "atmega1284", "__AVR_ATmega1284__" }, 8713 { "atmega1284p", "__AVR_ATmega1284P__" }, 8714 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 8715 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 8716 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 8717 { "at90can128", "__AVR_AT90CAN128__" }, 8718 { "at90usb1286", "__AVR_AT90USB1286__" }, 8719 { "at90usb1287", "__AVR_AT90USB1287__" }, 8720 { "atmega2560", "__AVR_ATmega2560__" }, 8721 { "atmega2561", "__AVR_ATmega2561__" }, 8722 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 8723 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 8724 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 8725 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 8726 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 8727 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 8728 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 8729 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 8730 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 8731 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 8732 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 8733 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 8734 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 8735 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 8736 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 8737 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 8738 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 8739 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 8740 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 8741 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 8742 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 8743 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 8744 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 8745 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 8746 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 8747 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 8748 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 8749 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 8750 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 8751 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 8752 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 8753 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 8754 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 8755 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 8756 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 8757 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 8758 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 8759 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 8760 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 8761 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 8762 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 8763 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 8764 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 8765 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 8766 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 8767 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 8768 { "attiny4", "__AVR_ATtiny4__" }, 8769 { "attiny5", "__AVR_ATtiny5__" }, 8770 { "attiny9", "__AVR_ATtiny9__" }, 8771 { "attiny10", "__AVR_ATtiny10__" }, 8772 { "attiny20", "__AVR_ATtiny20__" }, 8773 { "attiny40", "__AVR_ATtiny40__" }, 8774 { "attiny102", "__AVR_ATtiny102__" }, 8775 { "attiny104", "__AVR_ATtiny104__" }, 8776 }; 8777 8778 // AVR Target 8779 class AVRTargetInfo : public TargetInfo { 8780 public: 8781 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8782 : TargetInfo(Triple) { 8783 TLSSupported = false; 8784 PointerWidth = 16; 8785 PointerAlign = 8; 8786 IntWidth = 16; 8787 IntAlign = 8; 8788 LongWidth = 32; 8789 LongAlign = 8; 8790 LongLongWidth = 64; 8791 LongLongAlign = 8; 8792 SuitableAlign = 8; 8793 DefaultAlignForAttributeAligned = 8; 8794 HalfWidth = 16; 8795 HalfAlign = 8; 8796 FloatWidth = 32; 8797 FloatAlign = 8; 8798 DoubleWidth = 32; 8799 DoubleAlign = 8; 8800 DoubleFormat = &llvm::APFloat::IEEEsingle(); 8801 LongDoubleWidth = 32; 8802 LongDoubleAlign = 8; 8803 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 8804 SizeType = UnsignedInt; 8805 PtrDiffType = SignedInt; 8806 IntPtrType = SignedInt; 8807 Char16Type = UnsignedInt; 8808 WCharType = SignedInt; 8809 WIntType = SignedInt; 8810 Char32Type = UnsignedLong; 8811 SigAtomicType = SignedChar; 8812 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 8813 "-f32:32:32-f64:64:64-n8"); 8814 } 8815 8816 void getTargetDefines(const LangOptions &Opts, 8817 MacroBuilder &Builder) const override { 8818 Builder.defineMacro("AVR"); 8819 Builder.defineMacro("__AVR"); 8820 Builder.defineMacro("__AVR__"); 8821 8822 if (!this->CPU.empty()) { 8823 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 8824 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 8825 8826 if (It != AVRMcus.end()) 8827 Builder.defineMacro(It->DefineName); 8828 } 8829 } 8830 8831 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8832 return None; 8833 } 8834 8835 BuiltinVaListKind getBuiltinVaListKind() const override { 8836 return TargetInfo::VoidPtrBuiltinVaList; 8837 } 8838 8839 const char *getClobbers() const override { 8840 return ""; 8841 } 8842 8843 ArrayRef<const char *> getGCCRegNames() const override { 8844 static const char * const GCCRegNames[] = { 8845 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8846 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 8847 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 8848 "r24", "r25", "X", "Y", "Z", "SP" 8849 }; 8850 return llvm::makeArrayRef(GCCRegNames); 8851 } 8852 8853 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8854 return None; 8855 } 8856 8857 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 8858 static const TargetInfo::AddlRegName AddlRegNames[] = { 8859 { { "r26", "r27"}, 26 }, 8860 { { "r28", "r29"}, 27 }, 8861 { { "r30", "r31"}, 28 }, 8862 { { "SPL", "SPH"}, 29 }, 8863 }; 8864 return llvm::makeArrayRef(AddlRegNames); 8865 } 8866 8867 bool validateAsmConstraint(const char *&Name, 8868 TargetInfo::ConstraintInfo &Info) const override { 8869 // There aren't any multi-character AVR specific constraints. 8870 if (StringRef(Name).size() > 1) return false; 8871 8872 switch (*Name) { 8873 default: return false; 8874 case 'a': // Simple upper registers 8875 case 'b': // Base pointer registers pairs 8876 case 'd': // Upper register 8877 case 'l': // Lower registers 8878 case 'e': // Pointer register pairs 8879 case 'q': // Stack pointer register 8880 case 'r': // Any register 8881 case 'w': // Special upper register pairs 8882 case 't': // Temporary register 8883 case 'x': case 'X': // Pointer register pair X 8884 case 'y': case 'Y': // Pointer register pair Y 8885 case 'z': case 'Z': // Pointer register pair Z 8886 Info.setAllowsRegister(); 8887 return true; 8888 case 'I': // 6-bit positive integer constant 8889 Info.setRequiresImmediate(0, 63); 8890 return true; 8891 case 'J': // 6-bit negative integer constant 8892 Info.setRequiresImmediate(-63, 0); 8893 return true; 8894 case 'K': // Integer constant (Range: 2) 8895 Info.setRequiresImmediate(2); 8896 return true; 8897 case 'L': // Integer constant (Range: 0) 8898 Info.setRequiresImmediate(0); 8899 return true; 8900 case 'M': // 8-bit integer constant 8901 Info.setRequiresImmediate(0, 0xff); 8902 return true; 8903 case 'N': // Integer constant (Range: -1) 8904 Info.setRequiresImmediate(-1); 8905 return true; 8906 case 'O': // Integer constant (Range: 8, 16, 24) 8907 Info.setRequiresImmediate({8, 16, 24}); 8908 return true; 8909 case 'P': // Integer constant (Range: 1) 8910 Info.setRequiresImmediate(1); 8911 return true; 8912 case 'R': // Integer constant (Range: -6 to 5) 8913 Info.setRequiresImmediate(-6, 5); 8914 return true; 8915 case 'G': // Floating point constant 8916 case 'Q': // A memory address based on Y or Z pointer with displacement. 8917 return true; 8918 } 8919 8920 return false; 8921 } 8922 8923 IntType getIntTypeByWidth(unsigned BitWidth, 8924 bool IsSigned) const final { 8925 // AVR prefers int for 16-bit integers. 8926 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 8927 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8928 } 8929 8930 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8931 bool IsSigned) const final { 8932 // AVR uses int for int_least16_t and int_fast16_t. 8933 return BitWidth == 16 8934 ? (IsSigned ? SignedInt : UnsignedInt) 8935 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8936 } 8937 8938 bool setCPU(const std::string &Name) override { 8939 bool IsFamily = llvm::StringSwitch<bool>(Name) 8940 .Case("avr1", true) 8941 .Case("avr2", true) 8942 .Case("avr25", true) 8943 .Case("avr3", true) 8944 .Case("avr31", true) 8945 .Case("avr35", true) 8946 .Case("avr4", true) 8947 .Case("avr5", true) 8948 .Case("avr51", true) 8949 .Case("avr6", true) 8950 .Case("avrxmega1", true) 8951 .Case("avrxmega2", true) 8952 .Case("avrxmega3", true) 8953 .Case("avrxmega4", true) 8954 .Case("avrxmega5", true) 8955 .Case("avrxmega6", true) 8956 .Case("avrxmega7", true) 8957 .Case("avrtiny", true) 8958 .Default(false); 8959 8960 if (IsFamily) this->CPU = Name; 8961 8962 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 8963 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 8964 8965 if (IsMCU) this->CPU = Name; 8966 8967 return IsFamily || IsMCU; 8968 } 8969 8970 protected: 8971 std::string CPU; 8972 }; 8973 8974 } // end anonymous namespace 8975 8976 //===----------------------------------------------------------------------===// 8977 // Driver code 8978 //===----------------------------------------------------------------------===// 8979 8980 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8981 const TargetOptions &Opts) { 8982 llvm::Triple::OSType os = Triple.getOS(); 8983 8984 switch (Triple.getArch()) { 8985 default: 8986 return nullptr; 8987 8988 case llvm::Triple::xcore: 8989 return new XCoreTargetInfo(Triple, Opts); 8990 8991 case llvm::Triple::hexagon: 8992 return new HexagonTargetInfo(Triple, Opts); 8993 8994 case llvm::Triple::lanai: 8995 return new LanaiTargetInfo(Triple, Opts); 8996 8997 case llvm::Triple::aarch64: 8998 if (Triple.isOSDarwin()) 8999 return new DarwinAArch64TargetInfo(Triple, Opts); 9000 9001 switch (os) { 9002 case llvm::Triple::CloudABI: 9003 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 9004 case llvm::Triple::FreeBSD: 9005 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9006 case llvm::Triple::Fuchsia: 9007 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9008 case llvm::Triple::Linux: 9009 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9010 case llvm::Triple::NetBSD: 9011 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9012 case llvm::Triple::OpenBSD: 9013 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9014 default: 9015 return new AArch64leTargetInfo(Triple, Opts); 9016 } 9017 9018 case llvm::Triple::aarch64_be: 9019 switch (os) { 9020 case llvm::Triple::FreeBSD: 9021 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9022 case llvm::Triple::Fuchsia: 9023 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9024 case llvm::Triple::Linux: 9025 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9026 case llvm::Triple::NetBSD: 9027 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9028 default: 9029 return new AArch64beTargetInfo(Triple, Opts); 9030 } 9031 9032 case llvm::Triple::arm: 9033 case llvm::Triple::thumb: 9034 if (Triple.isOSBinFormatMachO()) 9035 return new DarwinARMTargetInfo(Triple, Opts); 9036 9037 switch (os) { 9038 case llvm::Triple::CloudABI: 9039 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9040 case llvm::Triple::Linux: 9041 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9042 case llvm::Triple::FreeBSD: 9043 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9044 case llvm::Triple::NetBSD: 9045 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9046 case llvm::Triple::OpenBSD: 9047 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9048 case llvm::Triple::Bitrig: 9049 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9050 case llvm::Triple::RTEMS: 9051 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9052 case llvm::Triple::NaCl: 9053 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9054 case llvm::Triple::Win32: 9055 switch (Triple.getEnvironment()) { 9056 case llvm::Triple::Cygnus: 9057 return new CygwinARMTargetInfo(Triple, Opts); 9058 case llvm::Triple::GNU: 9059 return new MinGWARMTargetInfo(Triple, Opts); 9060 case llvm::Triple::Itanium: 9061 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9062 case llvm::Triple::MSVC: 9063 default: // Assume MSVC for unknown environments 9064 return new MicrosoftARMleTargetInfo(Triple, Opts); 9065 } 9066 default: 9067 return new ARMleTargetInfo(Triple, Opts); 9068 } 9069 9070 case llvm::Triple::armeb: 9071 case llvm::Triple::thumbeb: 9072 if (Triple.isOSDarwin()) 9073 return new DarwinARMTargetInfo(Triple, Opts); 9074 9075 switch (os) { 9076 case llvm::Triple::Linux: 9077 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9078 case llvm::Triple::FreeBSD: 9079 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9080 case llvm::Triple::NetBSD: 9081 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9082 case llvm::Triple::OpenBSD: 9083 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9084 case llvm::Triple::Bitrig: 9085 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9086 case llvm::Triple::RTEMS: 9087 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9088 case llvm::Triple::NaCl: 9089 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9090 default: 9091 return new ARMbeTargetInfo(Triple, Opts); 9092 } 9093 9094 case llvm::Triple::avr: 9095 return new AVRTargetInfo(Triple, Opts); 9096 case llvm::Triple::bpfeb: 9097 case llvm::Triple::bpfel: 9098 return new BPFTargetInfo(Triple, Opts); 9099 9100 case llvm::Triple::msp430: 9101 return new MSP430TargetInfo(Triple, Opts); 9102 9103 case llvm::Triple::mips: 9104 switch (os) { 9105 case llvm::Triple::Linux: 9106 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9107 case llvm::Triple::RTEMS: 9108 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9109 case llvm::Triple::FreeBSD: 9110 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9111 case llvm::Triple::NetBSD: 9112 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9113 default: 9114 return new MipsTargetInfo(Triple, Opts); 9115 } 9116 9117 case llvm::Triple::mipsel: 9118 switch (os) { 9119 case llvm::Triple::Linux: 9120 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9121 case llvm::Triple::RTEMS: 9122 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9123 case llvm::Triple::FreeBSD: 9124 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9125 case llvm::Triple::NetBSD: 9126 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9127 case llvm::Triple::NaCl: 9128 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9129 default: 9130 return new MipsTargetInfo(Triple, Opts); 9131 } 9132 9133 case llvm::Triple::mips64: 9134 switch (os) { 9135 case llvm::Triple::Linux: 9136 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9137 case llvm::Triple::RTEMS: 9138 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9139 case llvm::Triple::FreeBSD: 9140 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9141 case llvm::Triple::NetBSD: 9142 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9143 case llvm::Triple::OpenBSD: 9144 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9145 default: 9146 return new MipsTargetInfo(Triple, Opts); 9147 } 9148 9149 case llvm::Triple::mips64el: 9150 switch (os) { 9151 case llvm::Triple::Linux: 9152 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9153 case llvm::Triple::RTEMS: 9154 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9155 case llvm::Triple::FreeBSD: 9156 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9157 case llvm::Triple::NetBSD: 9158 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9159 case llvm::Triple::OpenBSD: 9160 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9161 default: 9162 return new MipsTargetInfo(Triple, Opts); 9163 } 9164 9165 case llvm::Triple::le32: 9166 switch (os) { 9167 case llvm::Triple::NaCl: 9168 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9169 default: 9170 return nullptr; 9171 } 9172 9173 case llvm::Triple::le64: 9174 return new Le64TargetInfo(Triple, Opts); 9175 9176 case llvm::Triple::ppc: 9177 if (Triple.isOSDarwin()) 9178 return new DarwinPPC32TargetInfo(Triple, Opts); 9179 switch (os) { 9180 case llvm::Triple::Linux: 9181 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9182 case llvm::Triple::FreeBSD: 9183 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9184 case llvm::Triple::NetBSD: 9185 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9186 case llvm::Triple::OpenBSD: 9187 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9188 case llvm::Triple::RTEMS: 9189 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9190 default: 9191 return new PPC32TargetInfo(Triple, Opts); 9192 } 9193 9194 case llvm::Triple::ppc64: 9195 if (Triple.isOSDarwin()) 9196 return new DarwinPPC64TargetInfo(Triple, Opts); 9197 switch (os) { 9198 case llvm::Triple::Linux: 9199 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9200 case llvm::Triple::Lv2: 9201 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9202 case llvm::Triple::FreeBSD: 9203 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9204 case llvm::Triple::NetBSD: 9205 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9206 default: 9207 return new PPC64TargetInfo(Triple, Opts); 9208 } 9209 9210 case llvm::Triple::ppc64le: 9211 switch (os) { 9212 case llvm::Triple::Linux: 9213 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9214 case llvm::Triple::NetBSD: 9215 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9216 default: 9217 return new PPC64TargetInfo(Triple, Opts); 9218 } 9219 9220 case llvm::Triple::nvptx: 9221 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9222 case llvm::Triple::nvptx64: 9223 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9224 9225 case llvm::Triple::amdgcn: 9226 case llvm::Triple::r600: 9227 return new AMDGPUTargetInfo(Triple, Opts); 9228 9229 case llvm::Triple::sparc: 9230 switch (os) { 9231 case llvm::Triple::Linux: 9232 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9233 case llvm::Triple::Solaris: 9234 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9235 case llvm::Triple::NetBSD: 9236 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9237 case llvm::Triple::OpenBSD: 9238 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9239 case llvm::Triple::RTEMS: 9240 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9241 default: 9242 return new SparcV8TargetInfo(Triple, Opts); 9243 } 9244 9245 // The 'sparcel' architecture copies all the above cases except for Solaris. 9246 case llvm::Triple::sparcel: 9247 switch (os) { 9248 case llvm::Triple::Linux: 9249 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9250 case llvm::Triple::NetBSD: 9251 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9252 case llvm::Triple::OpenBSD: 9253 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9254 case llvm::Triple::RTEMS: 9255 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9256 default: 9257 return new SparcV8elTargetInfo(Triple, Opts); 9258 } 9259 9260 case llvm::Triple::sparcv9: 9261 switch (os) { 9262 case llvm::Triple::Linux: 9263 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9264 case llvm::Triple::Solaris: 9265 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9266 case llvm::Triple::NetBSD: 9267 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9268 case llvm::Triple::OpenBSD: 9269 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9270 case llvm::Triple::FreeBSD: 9271 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9272 default: 9273 return new SparcV9TargetInfo(Triple, Opts); 9274 } 9275 9276 case llvm::Triple::systemz: 9277 switch (os) { 9278 case llvm::Triple::Linux: 9279 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9280 default: 9281 return new SystemZTargetInfo(Triple, Opts); 9282 } 9283 9284 case llvm::Triple::tce: 9285 return new TCETargetInfo(Triple, Opts); 9286 9287 case llvm::Triple::tcele: 9288 return new TCELETargetInfo(Triple, Opts); 9289 9290 case llvm::Triple::x86: 9291 if (Triple.isOSDarwin()) 9292 return new DarwinI386TargetInfo(Triple, Opts); 9293 9294 switch (os) { 9295 case llvm::Triple::CloudABI: 9296 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9297 case llvm::Triple::Linux: { 9298 switch (Triple.getEnvironment()) { 9299 default: 9300 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9301 case llvm::Triple::Android: 9302 return new AndroidX86_32TargetInfo(Triple, Opts); 9303 } 9304 } 9305 case llvm::Triple::DragonFly: 9306 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9307 case llvm::Triple::NetBSD: 9308 return new NetBSDI386TargetInfo(Triple, Opts); 9309 case llvm::Triple::OpenBSD: 9310 return new OpenBSDI386TargetInfo(Triple, Opts); 9311 case llvm::Triple::Bitrig: 9312 return new BitrigI386TargetInfo(Triple, Opts); 9313 case llvm::Triple::FreeBSD: 9314 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9315 case llvm::Triple::KFreeBSD: 9316 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9317 case llvm::Triple::Minix: 9318 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9319 case llvm::Triple::Solaris: 9320 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9321 case llvm::Triple::Win32: { 9322 switch (Triple.getEnvironment()) { 9323 case llvm::Triple::Cygnus: 9324 return new CygwinX86_32TargetInfo(Triple, Opts); 9325 case llvm::Triple::GNU: 9326 return new MinGWX86_32TargetInfo(Triple, Opts); 9327 case llvm::Triple::Itanium: 9328 case llvm::Triple::MSVC: 9329 default: // Assume MSVC for unknown environments 9330 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9331 } 9332 } 9333 case llvm::Triple::Haiku: 9334 return new HaikuX86_32TargetInfo(Triple, Opts); 9335 case llvm::Triple::RTEMS: 9336 return new RTEMSX86_32TargetInfo(Triple, Opts); 9337 case llvm::Triple::NaCl: 9338 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9339 case llvm::Triple::ELFIAMCU: 9340 return new MCUX86_32TargetInfo(Triple, Opts); 9341 default: 9342 return new X86_32TargetInfo(Triple, Opts); 9343 } 9344 9345 case llvm::Triple::x86_64: 9346 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9347 return new DarwinX86_64TargetInfo(Triple, Opts); 9348 9349 switch (os) { 9350 case llvm::Triple::CloudABI: 9351 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9352 case llvm::Triple::Linux: { 9353 switch (Triple.getEnvironment()) { 9354 default: 9355 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9356 case llvm::Triple::Android: 9357 return new AndroidX86_64TargetInfo(Triple, Opts); 9358 } 9359 } 9360 case llvm::Triple::DragonFly: 9361 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9362 case llvm::Triple::NetBSD: 9363 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9364 case llvm::Triple::OpenBSD: 9365 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9366 case llvm::Triple::Bitrig: 9367 return new BitrigX86_64TargetInfo(Triple, Opts); 9368 case llvm::Triple::FreeBSD: 9369 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9370 case llvm::Triple::Fuchsia: 9371 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9372 case llvm::Triple::KFreeBSD: 9373 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9374 case llvm::Triple::Solaris: 9375 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9376 case llvm::Triple::Win32: { 9377 switch (Triple.getEnvironment()) { 9378 case llvm::Triple::Cygnus: 9379 return new CygwinX86_64TargetInfo(Triple, Opts); 9380 case llvm::Triple::GNU: 9381 return new MinGWX86_64TargetInfo(Triple, Opts); 9382 case llvm::Triple::MSVC: 9383 default: // Assume MSVC for unknown environments 9384 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9385 } 9386 } 9387 case llvm::Triple::Haiku: 9388 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9389 case llvm::Triple::NaCl: 9390 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9391 case llvm::Triple::PS4: 9392 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9393 default: 9394 return new X86_64TargetInfo(Triple, Opts); 9395 } 9396 9397 case llvm::Triple::spir: { 9398 if (Triple.getOS() != llvm::Triple::UnknownOS || 9399 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9400 return nullptr; 9401 return new SPIR32TargetInfo(Triple, Opts); 9402 } 9403 case llvm::Triple::spir64: { 9404 if (Triple.getOS() != llvm::Triple::UnknownOS || 9405 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9406 return nullptr; 9407 return new SPIR64TargetInfo(Triple, Opts); 9408 } 9409 case llvm::Triple::wasm32: 9410 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9411 Triple.getVendor() != llvm::Triple::UnknownVendor || 9412 Triple.getOS() != llvm::Triple::UnknownOS || 9413 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9414 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9415 return nullptr; 9416 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9417 case llvm::Triple::wasm64: 9418 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9419 Triple.getVendor() != llvm::Triple::UnknownVendor || 9420 Triple.getOS() != llvm::Triple::UnknownOS || 9421 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9422 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9423 return nullptr; 9424 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9425 9426 case llvm::Triple::renderscript32: 9427 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9428 case llvm::Triple::renderscript64: 9429 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9430 } 9431 } 9432 9433 /// CreateTargetInfo - Return the target info object for the specified target 9434 /// options. 9435 TargetInfo * 9436 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9437 const std::shared_ptr<TargetOptions> &Opts) { 9438 llvm::Triple Triple(Opts->Triple); 9439 9440 // Construct the target 9441 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9442 if (!Target) { 9443 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9444 return nullptr; 9445 } 9446 Target->TargetOpts = Opts; 9447 9448 // Set the target CPU if specified. 9449 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9450 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9451 return nullptr; 9452 } 9453 9454 // Set the target ABI if specified. 9455 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 9456 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 9457 return nullptr; 9458 } 9459 9460 // Set the fp math unit. 9461 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 9462 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 9463 return nullptr; 9464 } 9465 9466 // Compute the default target features, we need the target to handle this 9467 // because features may have dependencies on one another. 9468 llvm::StringMap<bool> Features; 9469 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 9470 Opts->FeaturesAsWritten)) 9471 return nullptr; 9472 9473 // Add the features to the compile options. 9474 Opts->Features.clear(); 9475 for (const auto &F : Features) 9476 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 9477 9478 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 9479 return nullptr; 9480 9481 Target->setSupportedOpenCLOpts(); 9482 Target->setOpenCLExtensionOpts(); 9483 9484 if (!Target->validateTarget(Diags)) 9485 return nullptr; 9486 9487 return Target.release(); 9488 } 9489