1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 // Ananas target 115 template<typename Target> 116 class AnanasTargetInfo : public OSTargetInfo<Target> { 117 protected: 118 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 119 MacroBuilder &Builder) const override { 120 // Ananas defines 121 Builder.defineMacro("__Ananas__"); 122 Builder.defineMacro("__ELF__"); 123 } 124 public: 125 AnanasTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 126 : OSTargetInfo<Target>(Triple, Opts) {} 127 }; 128 129 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 130 const llvm::Triple &Triple, 131 StringRef &PlatformName, 132 VersionTuple &PlatformMinVersion) { 133 Builder.defineMacro("__APPLE_CC__", "6000"); 134 Builder.defineMacro("__APPLE__"); 135 Builder.defineMacro("__STDC_NO_THREADS__"); 136 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 137 // AddressSanitizer doesn't play well with source fortification, which is on 138 // by default on Darwin. 139 if (Opts.Sanitize.has(SanitizerKind::Address)) 140 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 141 142 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 143 if (!Opts.ObjC1) { 144 // __weak is always defined, for use in blocks and with objc pointers. 145 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 146 Builder.defineMacro("__strong", ""); 147 Builder.defineMacro("__unsafe_unretained", ""); 148 } 149 150 if (Opts.Static) 151 Builder.defineMacro("__STATIC__"); 152 else 153 Builder.defineMacro("__DYNAMIC__"); 154 155 if (Opts.POSIXThreads) 156 Builder.defineMacro("_REENTRANT"); 157 158 // Get the platform type and version number from the triple. 159 unsigned Maj, Min, Rev; 160 if (Triple.isMacOSX()) { 161 Triple.getMacOSXVersion(Maj, Min, Rev); 162 PlatformName = "macos"; 163 } else { 164 Triple.getOSVersion(Maj, Min, Rev); 165 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 166 } 167 168 // If -target arch-pc-win32-macho option specified, we're 169 // generating code for Win32 ABI. No need to emit 170 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 171 if (PlatformName == "win32") { 172 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 173 return; 174 } 175 176 // Set the appropriate OS version define. 177 if (Triple.isiOS()) { 178 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 179 char Str[7]; 180 if (Maj < 10) { 181 Str[0] = '0' + Maj; 182 Str[1] = '0' + (Min / 10); 183 Str[2] = '0' + (Min % 10); 184 Str[3] = '0' + (Rev / 10); 185 Str[4] = '0' + (Rev % 10); 186 Str[5] = '\0'; 187 } else { 188 // Handle versions >= 10. 189 Str[0] = '0' + (Maj / 10); 190 Str[1] = '0' + (Maj % 10); 191 Str[2] = '0' + (Min / 10); 192 Str[3] = '0' + (Min % 10); 193 Str[4] = '0' + (Rev / 10); 194 Str[5] = '0' + (Rev % 10); 195 Str[6] = '\0'; 196 } 197 if (Triple.isTvOS()) 198 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 199 else 200 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 201 Str); 202 203 } else if (Triple.isWatchOS()) { 204 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 205 char Str[6]; 206 Str[0] = '0' + Maj; 207 Str[1] = '0' + (Min / 10); 208 Str[2] = '0' + (Min % 10); 209 Str[3] = '0' + (Rev / 10); 210 Str[4] = '0' + (Rev % 10); 211 Str[5] = '\0'; 212 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 213 } else if (Triple.isMacOSX()) { 214 // Note that the Driver allows versions which aren't representable in the 215 // define (because we only get a single digit for the minor and micro 216 // revision numbers). So, we limit them to the maximum representable 217 // version. 218 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 219 char Str[7]; 220 if (Maj < 10 || (Maj == 10 && Min < 10)) { 221 Str[0] = '0' + (Maj / 10); 222 Str[1] = '0' + (Maj % 10); 223 Str[2] = '0' + std::min(Min, 9U); 224 Str[3] = '0' + std::min(Rev, 9U); 225 Str[4] = '\0'; 226 } else { 227 // Handle versions > 10.9. 228 Str[0] = '0' + (Maj / 10); 229 Str[1] = '0' + (Maj % 10); 230 Str[2] = '0' + (Min / 10); 231 Str[3] = '0' + (Min % 10); 232 Str[4] = '0' + (Rev / 10); 233 Str[5] = '0' + (Rev % 10); 234 Str[6] = '\0'; 235 } 236 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 237 } 238 239 // Tell users about the kernel if there is one. 240 if (Triple.isOSDarwin()) 241 Builder.defineMacro("__MACH__"); 242 243 // The Watch ABI uses Dwarf EH. 244 if(Triple.isWatchABI()) 245 Builder.defineMacro("__ARM_DWARF_EH__"); 246 247 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 248 } 249 250 template<typename Target> 251 class DarwinTargetInfo : public OSTargetInfo<Target> { 252 protected: 253 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 254 MacroBuilder &Builder) const override { 255 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 256 this->PlatformMinVersion); 257 } 258 259 public: 260 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 261 : OSTargetInfo<Target>(Triple, Opts) { 262 // By default, no TLS, and we whitelist permitted architecture/OS 263 // combinations. 264 this->TLSSupported = false; 265 266 if (Triple.isMacOSX()) 267 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 268 else if (Triple.isiOS()) { 269 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 270 if (Triple.getArch() == llvm::Triple::x86_64 || 271 Triple.getArch() == llvm::Triple::aarch64) 272 this->TLSSupported = !Triple.isOSVersionLT(8); 273 else if (Triple.getArch() == llvm::Triple::x86 || 274 Triple.getArch() == llvm::Triple::arm || 275 Triple.getArch() == llvm::Triple::thumb) 276 this->TLSSupported = !Triple.isOSVersionLT(9); 277 } else if (Triple.isWatchOS()) 278 this->TLSSupported = !Triple.isOSVersionLT(2); 279 280 this->MCountName = "\01mcount"; 281 } 282 283 std::string isValidSectionSpecifier(StringRef SR) const override { 284 // Let MCSectionMachO validate this. 285 StringRef Segment, Section; 286 unsigned TAA, StubSize; 287 bool HasTAA; 288 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 289 TAA, HasTAA, StubSize); 290 } 291 292 const char *getStaticInitSectionSpecifier() const override { 293 // FIXME: We should return 0 when building kexts. 294 return "__TEXT,__StaticInit,regular,pure_instructions"; 295 } 296 297 /// Darwin does not support protected visibility. Darwin's "default" 298 /// is very similar to ELF's "protected"; Darwin requires a "weak" 299 /// attribute on declarations that can be dynamically replaced. 300 bool hasProtectedVisibility() const override { 301 return false; 302 } 303 304 unsigned getExnObjectAlignment() const override { 305 // The alignment of an exception object is 8-bytes for darwin since 306 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 307 // and therefore doesn't guarantee 16-byte alignment. 308 return 64; 309 } 310 }; 311 312 313 // DragonFlyBSD Target 314 template<typename Target> 315 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 316 protected: 317 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 318 MacroBuilder &Builder) const override { 319 // DragonFly defines; list based off of gcc output 320 Builder.defineMacro("__DragonFly__"); 321 Builder.defineMacro("__DragonFly_cc_version", "100001"); 322 Builder.defineMacro("__ELF__"); 323 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 324 Builder.defineMacro("__tune_i386__"); 325 DefineStd(Builder, "unix", Opts); 326 } 327 public: 328 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 329 : OSTargetInfo<Target>(Triple, Opts) { 330 switch (Triple.getArch()) { 331 default: 332 case llvm::Triple::x86: 333 case llvm::Triple::x86_64: 334 this->MCountName = ".mcount"; 335 break; 336 } 337 } 338 }; 339 340 #ifndef FREEBSD_CC_VERSION 341 #define FREEBSD_CC_VERSION 0U 342 #endif 343 344 // FreeBSD Target 345 template<typename Target> 346 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 347 protected: 348 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 349 MacroBuilder &Builder) const override { 350 // FreeBSD defines; list based off of gcc output 351 352 unsigned Release = Triple.getOSMajorVersion(); 353 if (Release == 0U) 354 Release = 8U; 355 unsigned CCVersion = FREEBSD_CC_VERSION; 356 if (CCVersion == 0U) 357 CCVersion = Release * 100000U + 1U; 358 359 Builder.defineMacro("__FreeBSD__", Twine(Release)); 360 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 361 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 362 DefineStd(Builder, "unix", Opts); 363 Builder.defineMacro("__ELF__"); 364 365 // On FreeBSD, wchar_t contains the number of the code point as 366 // used by the character set of the locale. These character sets are 367 // not necessarily a superset of ASCII. 368 // 369 // FIXME: This is wrong; the macro refers to the numerical values 370 // of wchar_t *literals*, which are not locale-dependent. However, 371 // FreeBSD systems apparently depend on us getting this wrong, and 372 // setting this to 1 is conforming even if all the basic source 373 // character literals have the same encoding as char and wchar_t. 374 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 375 } 376 public: 377 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 378 : OSTargetInfo<Target>(Triple, Opts) { 379 switch (Triple.getArch()) { 380 default: 381 case llvm::Triple::x86: 382 case llvm::Triple::x86_64: 383 this->MCountName = ".mcount"; 384 break; 385 case llvm::Triple::mips: 386 case llvm::Triple::mipsel: 387 case llvm::Triple::ppc: 388 case llvm::Triple::ppc64: 389 case llvm::Triple::ppc64le: 390 this->MCountName = "_mcount"; 391 break; 392 case llvm::Triple::arm: 393 this->MCountName = "__mcount"; 394 break; 395 } 396 } 397 }; 398 399 // GNU/kFreeBSD Target 400 template<typename Target> 401 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 402 protected: 403 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 404 MacroBuilder &Builder) const override { 405 // GNU/kFreeBSD defines; list based off of gcc output 406 407 DefineStd(Builder, "unix", Opts); 408 Builder.defineMacro("__FreeBSD_kernel__"); 409 Builder.defineMacro("__GLIBC__"); 410 Builder.defineMacro("__ELF__"); 411 if (Opts.POSIXThreads) 412 Builder.defineMacro("_REENTRANT"); 413 if (Opts.CPlusPlus) 414 Builder.defineMacro("_GNU_SOURCE"); 415 } 416 public: 417 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) {} 419 }; 420 421 // Haiku Target 422 template<typename Target> 423 class HaikuTargetInfo : public OSTargetInfo<Target> { 424 protected: 425 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 426 MacroBuilder &Builder) const override { 427 // Haiku defines; list based off of gcc output 428 Builder.defineMacro("__HAIKU__"); 429 Builder.defineMacro("__ELF__"); 430 DefineStd(Builder, "unix", Opts); 431 } 432 public: 433 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 434 : OSTargetInfo<Target>(Triple, Opts) { 435 this->SizeType = TargetInfo::UnsignedLong; 436 this->IntPtrType = TargetInfo::SignedLong; 437 this->PtrDiffType = TargetInfo::SignedLong; 438 this->ProcessIDType = TargetInfo::SignedLong; 439 this->TLSSupported = false; 440 441 } 442 }; 443 444 // Minix Target 445 template<typename Target> 446 class MinixTargetInfo : public OSTargetInfo<Target> { 447 protected: 448 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 449 MacroBuilder &Builder) const override { 450 // Minix defines 451 452 Builder.defineMacro("__minix", "3"); 453 Builder.defineMacro("_EM_WSIZE", "4"); 454 Builder.defineMacro("_EM_PSIZE", "4"); 455 Builder.defineMacro("_EM_SSIZE", "2"); 456 Builder.defineMacro("_EM_LSIZE", "4"); 457 Builder.defineMacro("_EM_FSIZE", "4"); 458 Builder.defineMacro("_EM_DSIZE", "8"); 459 Builder.defineMacro("__ELF__"); 460 DefineStd(Builder, "unix", Opts); 461 } 462 public: 463 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 464 : OSTargetInfo<Target>(Triple, Opts) {} 465 }; 466 467 // Linux target 468 template<typename Target> 469 class LinuxTargetInfo : public OSTargetInfo<Target> { 470 protected: 471 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 472 MacroBuilder &Builder) const override { 473 // Linux defines; list based off of gcc output 474 DefineStd(Builder, "unix", Opts); 475 DefineStd(Builder, "linux", Opts); 476 Builder.defineMacro("__gnu_linux__"); 477 Builder.defineMacro("__ELF__"); 478 if (Triple.isAndroid()) { 479 Builder.defineMacro("__ANDROID__", "1"); 480 unsigned Maj, Min, Rev; 481 Triple.getEnvironmentVersion(Maj, Min, Rev); 482 this->PlatformName = "android"; 483 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 484 if (Maj) 485 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 486 } 487 if (Opts.POSIXThreads) 488 Builder.defineMacro("_REENTRANT"); 489 if (Opts.CPlusPlus) 490 Builder.defineMacro("_GNU_SOURCE"); 491 if (this->HasFloat128) 492 Builder.defineMacro("__FLOAT128__"); 493 } 494 public: 495 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 496 : OSTargetInfo<Target>(Triple, Opts) { 497 this->WIntType = TargetInfo::UnsignedInt; 498 499 switch (Triple.getArch()) { 500 default: 501 break; 502 case llvm::Triple::ppc: 503 case llvm::Triple::ppc64: 504 case llvm::Triple::ppc64le: 505 this->MCountName = "_mcount"; 506 break; 507 case llvm::Triple::x86: 508 case llvm::Triple::x86_64: 509 case llvm::Triple::systemz: 510 this->HasFloat128 = true; 511 break; 512 } 513 } 514 515 const char *getStaticInitSectionSpecifier() const override { 516 return ".text.startup"; 517 } 518 }; 519 520 // NetBSD Target 521 template<typename Target> 522 class NetBSDTargetInfo : public OSTargetInfo<Target> { 523 protected: 524 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 525 MacroBuilder &Builder) const override { 526 // NetBSD defines; list based off of gcc output 527 Builder.defineMacro("__NetBSD__"); 528 Builder.defineMacro("__unix__"); 529 Builder.defineMacro("__ELF__"); 530 if (Opts.POSIXThreads) 531 Builder.defineMacro("_REENTRANT"); 532 533 switch (Triple.getArch()) { 534 default: 535 break; 536 case llvm::Triple::arm: 537 case llvm::Triple::armeb: 538 case llvm::Triple::thumb: 539 case llvm::Triple::thumbeb: 540 Builder.defineMacro("__ARM_DWARF_EH__"); 541 break; 542 } 543 } 544 public: 545 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 546 : OSTargetInfo<Target>(Triple, Opts) { 547 this->MCountName = "_mcount"; 548 } 549 }; 550 551 // OpenBSD Target 552 template<typename Target> 553 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 554 protected: 555 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 556 MacroBuilder &Builder) const override { 557 // OpenBSD defines; list based off of gcc output 558 559 Builder.defineMacro("__OpenBSD__"); 560 DefineStd(Builder, "unix", Opts); 561 Builder.defineMacro("__ELF__"); 562 if (Opts.POSIXThreads) 563 Builder.defineMacro("_REENTRANT"); 564 if (this->HasFloat128) 565 Builder.defineMacro("__FLOAT128__"); 566 } 567 public: 568 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 569 : OSTargetInfo<Target>(Triple, Opts) { 570 this->TLSSupported = false; 571 572 switch (Triple.getArch()) { 573 case llvm::Triple::x86: 574 case llvm::Triple::x86_64: 575 this->HasFloat128 = true; 576 // FALLTHROUGH 577 default: 578 this->MCountName = "__mcount"; 579 break; 580 case llvm::Triple::mips64: 581 case llvm::Triple::mips64el: 582 case llvm::Triple::ppc: 583 case llvm::Triple::sparcv9: 584 this->MCountName = "_mcount"; 585 break; 586 } 587 } 588 }; 589 590 // Bitrig Target 591 template<typename Target> 592 class BitrigTargetInfo : public OSTargetInfo<Target> { 593 protected: 594 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 595 MacroBuilder &Builder) const override { 596 // Bitrig defines; list based off of gcc output 597 598 Builder.defineMacro("__Bitrig__"); 599 DefineStd(Builder, "unix", Opts); 600 Builder.defineMacro("__ELF__"); 601 if (Opts.POSIXThreads) 602 Builder.defineMacro("_REENTRANT"); 603 604 switch (Triple.getArch()) { 605 default: 606 break; 607 case llvm::Triple::arm: 608 case llvm::Triple::armeb: 609 case llvm::Triple::thumb: 610 case llvm::Triple::thumbeb: 611 Builder.defineMacro("__ARM_DWARF_EH__"); 612 break; 613 } 614 } 615 public: 616 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 617 : OSTargetInfo<Target>(Triple, Opts) { 618 this->MCountName = "__mcount"; 619 } 620 }; 621 622 // PSP Target 623 template<typename Target> 624 class PSPTargetInfo : public OSTargetInfo<Target> { 625 protected: 626 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 627 MacroBuilder &Builder) const override { 628 // PSP defines; list based on the output of the pspdev gcc toolchain. 629 Builder.defineMacro("PSP"); 630 Builder.defineMacro("_PSP"); 631 Builder.defineMacro("__psp__"); 632 Builder.defineMacro("__ELF__"); 633 } 634 public: 635 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 636 }; 637 638 // PS3 PPU Target 639 template<typename Target> 640 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 641 protected: 642 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 643 MacroBuilder &Builder) const override { 644 // PS3 PPU defines. 645 Builder.defineMacro("__PPC__"); 646 Builder.defineMacro("__PPU__"); 647 Builder.defineMacro("__CELLOS_LV2__"); 648 Builder.defineMacro("__ELF__"); 649 Builder.defineMacro("__LP32__"); 650 Builder.defineMacro("_ARCH_PPC64"); 651 Builder.defineMacro("__powerpc64__"); 652 } 653 public: 654 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 655 : OSTargetInfo<Target>(Triple, Opts) { 656 this->LongWidth = this->LongAlign = 32; 657 this->PointerWidth = this->PointerAlign = 32; 658 this->IntMaxType = TargetInfo::SignedLongLong; 659 this->Int64Type = TargetInfo::SignedLongLong; 660 this->SizeType = TargetInfo::UnsignedInt; 661 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 662 } 663 }; 664 665 template <typename Target> 666 class PS4OSTargetInfo : public OSTargetInfo<Target> { 667 protected: 668 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 669 MacroBuilder &Builder) const override { 670 Builder.defineMacro("__FreeBSD__", "9"); 671 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 672 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 673 DefineStd(Builder, "unix", Opts); 674 Builder.defineMacro("__ELF__"); 675 Builder.defineMacro("__ORBIS__"); 676 } 677 public: 678 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 679 : OSTargetInfo<Target>(Triple, Opts) { 680 this->WCharType = this->UnsignedShort; 681 682 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 683 this->MaxTLSAlign = 256; 684 685 // On PS4, do not honor explicit bit field alignment, 686 // as in "__attribute__((aligned(2))) int b : 1;". 687 this->UseExplicitBitFieldAlignment = false; 688 689 switch (Triple.getArch()) { 690 default: 691 case llvm::Triple::x86_64: 692 this->MCountName = ".mcount"; 693 break; 694 } 695 } 696 }; 697 698 // Solaris target 699 template<typename Target> 700 class SolarisTargetInfo : public OSTargetInfo<Target> { 701 protected: 702 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 703 MacroBuilder &Builder) const override { 704 DefineStd(Builder, "sun", Opts); 705 DefineStd(Builder, "unix", Opts); 706 Builder.defineMacro("__ELF__"); 707 Builder.defineMacro("__svr4__"); 708 Builder.defineMacro("__SVR4"); 709 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 710 // newer, but to 500 for everything else. feature_test.h has a check to 711 // ensure that you are not using C99 with an old version of X/Open or C89 712 // with a new version. 713 if (Opts.C99) 714 Builder.defineMacro("_XOPEN_SOURCE", "600"); 715 else 716 Builder.defineMacro("_XOPEN_SOURCE", "500"); 717 if (Opts.CPlusPlus) 718 Builder.defineMacro("__C99FEATURES__"); 719 Builder.defineMacro("_LARGEFILE_SOURCE"); 720 Builder.defineMacro("_LARGEFILE64_SOURCE"); 721 Builder.defineMacro("__EXTENSIONS__"); 722 Builder.defineMacro("_REENTRANT"); 723 } 724 public: 725 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 726 : OSTargetInfo<Target>(Triple, Opts) { 727 this->WCharType = this->SignedInt; 728 // FIXME: WIntType should be SignedLong 729 } 730 }; 731 732 // Windows target 733 template<typename Target> 734 class WindowsTargetInfo : public OSTargetInfo<Target> { 735 protected: 736 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 737 MacroBuilder &Builder) const override { 738 Builder.defineMacro("_WIN32"); 739 } 740 void getVisualStudioDefines(const LangOptions &Opts, 741 MacroBuilder &Builder) const { 742 if (Opts.CPlusPlus) { 743 if (Opts.RTTIData) 744 Builder.defineMacro("_CPPRTTI"); 745 746 if (Opts.CXXExceptions) 747 Builder.defineMacro("_CPPUNWIND"); 748 } 749 750 if (Opts.Bool) 751 Builder.defineMacro("__BOOL_DEFINED"); 752 753 if (!Opts.CharIsSigned) 754 Builder.defineMacro("_CHAR_UNSIGNED"); 755 756 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 757 // but it works for now. 758 if (Opts.POSIXThreads) 759 Builder.defineMacro("_MT"); 760 761 if (Opts.MSCompatibilityVersion) { 762 Builder.defineMacro("_MSC_VER", 763 Twine(Opts.MSCompatibilityVersion / 100000)); 764 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 765 // FIXME We cannot encode the revision information into 32-bits 766 Builder.defineMacro("_MSC_BUILD", Twine(1)); 767 768 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 769 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 770 771 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 772 if (Opts.CPlusPlus1z) 773 Builder.defineMacro("_MSVC_LANG", "201403L"); 774 else if (Opts.CPlusPlus14) 775 Builder.defineMacro("_MSVC_LANG", "201402L"); 776 } 777 } 778 779 if (Opts.MicrosoftExt) { 780 Builder.defineMacro("_MSC_EXTENSIONS"); 781 782 if (Opts.CPlusPlus11) { 783 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 784 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 785 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 786 } 787 } 788 789 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 790 } 791 792 public: 793 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 794 : OSTargetInfo<Target>(Triple, Opts) {} 795 }; 796 797 template <typename Target> 798 class NaClTargetInfo : public OSTargetInfo<Target> { 799 protected: 800 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 801 MacroBuilder &Builder) const override { 802 if (Opts.POSIXThreads) 803 Builder.defineMacro("_REENTRANT"); 804 if (Opts.CPlusPlus) 805 Builder.defineMacro("_GNU_SOURCE"); 806 807 DefineStd(Builder, "unix", Opts); 808 Builder.defineMacro("__ELF__"); 809 Builder.defineMacro("__native_client__"); 810 } 811 812 public: 813 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 814 : OSTargetInfo<Target>(Triple, Opts) { 815 this->LongAlign = 32; 816 this->LongWidth = 32; 817 this->PointerAlign = 32; 818 this->PointerWidth = 32; 819 this->IntMaxType = TargetInfo::SignedLongLong; 820 this->Int64Type = TargetInfo::SignedLongLong; 821 this->DoubleAlign = 64; 822 this->LongDoubleWidth = 64; 823 this->LongDoubleAlign = 64; 824 this->LongLongWidth = 64; 825 this->LongLongAlign = 64; 826 this->SizeType = TargetInfo::UnsignedInt; 827 this->PtrDiffType = TargetInfo::SignedInt; 828 this->IntPtrType = TargetInfo::SignedInt; 829 // RegParmMax is inherited from the underlying architecture. 830 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 831 if (Triple.getArch() == llvm::Triple::arm) { 832 // Handled in ARM's setABI(). 833 } else if (Triple.getArch() == llvm::Triple::x86) { 834 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 835 } else if (Triple.getArch() == llvm::Triple::x86_64) { 836 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 837 } else if (Triple.getArch() == llvm::Triple::mipsel) { 838 // Handled on mips' setDataLayout. 839 } else { 840 assert(Triple.getArch() == llvm::Triple::le32); 841 this->resetDataLayout("e-p:32:32-i64:64"); 842 } 843 } 844 }; 845 846 // Fuchsia Target 847 template<typename Target> 848 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 849 protected: 850 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 851 MacroBuilder &Builder) const override { 852 Builder.defineMacro("__Fuchsia__"); 853 Builder.defineMacro("__ELF__"); 854 if (Opts.POSIXThreads) 855 Builder.defineMacro("_REENTRANT"); 856 // Required by the libc++ locale support. 857 if (Opts.CPlusPlus) 858 Builder.defineMacro("_GNU_SOURCE"); 859 } 860 public: 861 FuchsiaTargetInfo(const llvm::Triple &Triple, 862 const TargetOptions &Opts) 863 : OSTargetInfo<Target>(Triple, Opts) { 864 this->MCountName = "__mcount"; 865 } 866 }; 867 868 // WebAssembly target 869 template <typename Target> 870 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 871 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 872 MacroBuilder &Builder) const final { 873 // A common platform macro. 874 if (Opts.POSIXThreads) 875 Builder.defineMacro("_REENTRANT"); 876 // Follow g++ convention and predefine _GNU_SOURCE for C++. 877 if (Opts.CPlusPlus) 878 Builder.defineMacro("_GNU_SOURCE"); 879 } 880 881 // As an optimization, group static init code together in a section. 882 const char *getStaticInitSectionSpecifier() const final { 883 return ".text.__startup"; 884 } 885 886 public: 887 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 888 const TargetOptions &Opts) 889 : OSTargetInfo<Target>(Triple, Opts) { 890 this->MCountName = "__mcount"; 891 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 892 } 893 }; 894 895 //===----------------------------------------------------------------------===// 896 // Specific target implementations. 897 //===----------------------------------------------------------------------===// 898 899 // PPC abstract base class 900 class PPCTargetInfo : public TargetInfo { 901 static const Builtin::Info BuiltinInfo[]; 902 static const char * const GCCRegNames[]; 903 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 904 std::string CPU; 905 906 // Target cpu features. 907 bool HasAltivec; 908 bool HasVSX; 909 bool HasP8Vector; 910 bool HasP8Crypto; 911 bool HasDirectMove; 912 bool HasQPX; 913 bool HasHTM; 914 bool HasBPERMD; 915 bool HasExtDiv; 916 bool HasP9Vector; 917 918 protected: 919 std::string ABI; 920 921 public: 922 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 923 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false), 924 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 925 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 926 SuitableAlign = 128; 927 SimdDefaultAlign = 128; 928 LongDoubleWidth = LongDoubleAlign = 128; 929 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 930 } 931 932 /// \brief Flags for architecture specific defines. 933 typedef enum { 934 ArchDefineNone = 0, 935 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 936 ArchDefinePpcgr = 1 << 1, 937 ArchDefinePpcsq = 1 << 2, 938 ArchDefine440 = 1 << 3, 939 ArchDefine603 = 1 << 4, 940 ArchDefine604 = 1 << 5, 941 ArchDefinePwr4 = 1 << 6, 942 ArchDefinePwr5 = 1 << 7, 943 ArchDefinePwr5x = 1 << 8, 944 ArchDefinePwr6 = 1 << 9, 945 ArchDefinePwr6x = 1 << 10, 946 ArchDefinePwr7 = 1 << 11, 947 ArchDefinePwr8 = 1 << 12, 948 ArchDefinePwr9 = 1 << 13, 949 ArchDefineA2 = 1 << 14, 950 ArchDefineA2q = 1 << 15 951 } ArchDefineTypes; 952 953 // Set the language option for altivec based on our value. 954 void adjust(LangOptions &Opts) override { 955 if (HasAltivec) 956 Opts.AltiVec = 1; 957 TargetInfo::adjust(Opts); 958 } 959 960 // Note: GCC recognizes the following additional cpus: 961 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 962 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 963 // titan, rs64. 964 bool setCPU(const std::string &Name) override { 965 bool CPUKnown = llvm::StringSwitch<bool>(Name) 966 .Case("generic", true) 967 .Case("440", true) 968 .Case("450", true) 969 .Case("601", true) 970 .Case("602", true) 971 .Case("603", true) 972 .Case("603e", true) 973 .Case("603ev", true) 974 .Case("604", true) 975 .Case("604e", true) 976 .Case("620", true) 977 .Case("630", true) 978 .Case("g3", true) 979 .Case("7400", true) 980 .Case("g4", true) 981 .Case("7450", true) 982 .Case("g4+", true) 983 .Case("750", true) 984 .Case("970", true) 985 .Case("g5", true) 986 .Case("a2", true) 987 .Case("a2q", true) 988 .Case("e500mc", true) 989 .Case("e5500", true) 990 .Case("power3", true) 991 .Case("pwr3", true) 992 .Case("power4", true) 993 .Case("pwr4", true) 994 .Case("power5", true) 995 .Case("pwr5", true) 996 .Case("power5x", true) 997 .Case("pwr5x", true) 998 .Case("power6", true) 999 .Case("pwr6", true) 1000 .Case("power6x", true) 1001 .Case("pwr6x", true) 1002 .Case("power7", true) 1003 .Case("pwr7", true) 1004 .Case("power8", true) 1005 .Case("pwr8", true) 1006 .Case("power9", true) 1007 .Case("pwr9", true) 1008 .Case("powerpc", true) 1009 .Case("ppc", true) 1010 .Case("powerpc64", true) 1011 .Case("ppc64", true) 1012 .Case("powerpc64le", true) 1013 .Case("ppc64le", true) 1014 .Default(false); 1015 1016 if (CPUKnown) 1017 CPU = Name; 1018 1019 return CPUKnown; 1020 } 1021 1022 1023 StringRef getABI() const override { return ABI; } 1024 1025 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1026 return llvm::makeArrayRef(BuiltinInfo, 1027 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1028 } 1029 1030 bool isCLZForZeroUndef() const override { return false; } 1031 1032 void getTargetDefines(const LangOptions &Opts, 1033 MacroBuilder &Builder) const override; 1034 1035 bool 1036 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1037 StringRef CPU, 1038 const std::vector<std::string> &FeaturesVec) const override; 1039 1040 bool handleTargetFeatures(std::vector<std::string> &Features, 1041 DiagnosticsEngine &Diags) override; 1042 bool hasFeature(StringRef Feature) const override; 1043 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1044 bool Enabled) const override; 1045 1046 ArrayRef<const char *> getGCCRegNames() const override; 1047 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1048 bool validateAsmConstraint(const char *&Name, 1049 TargetInfo::ConstraintInfo &Info) const override { 1050 switch (*Name) { 1051 default: return false; 1052 case 'O': // Zero 1053 break; 1054 case 'b': // Base register 1055 case 'f': // Floating point register 1056 Info.setAllowsRegister(); 1057 break; 1058 // FIXME: The following are added to allow parsing. 1059 // I just took a guess at what the actions should be. 1060 // Also, is more specific checking needed? I.e. specific registers? 1061 case 'd': // Floating point register (containing 64-bit value) 1062 case 'v': // Altivec vector register 1063 Info.setAllowsRegister(); 1064 break; 1065 case 'w': 1066 switch (Name[1]) { 1067 case 'd':// VSX vector register to hold vector double data 1068 case 'f':// VSX vector register to hold vector float data 1069 case 's':// VSX vector register to hold scalar float data 1070 case 'a':// Any VSX register 1071 case 'c':// An individual CR bit 1072 break; 1073 default: 1074 return false; 1075 } 1076 Info.setAllowsRegister(); 1077 Name++; // Skip over 'w'. 1078 break; 1079 case 'h': // `MQ', `CTR', or `LINK' register 1080 case 'q': // `MQ' register 1081 case 'c': // `CTR' register 1082 case 'l': // `LINK' register 1083 case 'x': // `CR' register (condition register) number 0 1084 case 'y': // `CR' register (condition register) 1085 case 'z': // `XER[CA]' carry bit (part of the XER register) 1086 Info.setAllowsRegister(); 1087 break; 1088 case 'I': // Signed 16-bit constant 1089 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1090 // (use `L' instead for SImode constants) 1091 case 'K': // Unsigned 16-bit constant 1092 case 'L': // Signed 16-bit constant shifted left 16 bits 1093 case 'M': // Constant larger than 31 1094 case 'N': // Exact power of 2 1095 case 'P': // Constant whose negation is a signed 16-bit constant 1096 case 'G': // Floating point constant that can be loaded into a 1097 // register with one instruction per word 1098 case 'H': // Integer/Floating point constant that can be loaded 1099 // into a register using three instructions 1100 break; 1101 case 'm': // Memory operand. Note that on PowerPC targets, m can 1102 // include addresses that update the base register. It 1103 // is therefore only safe to use `m' in an asm statement 1104 // if that asm statement accesses the operand exactly once. 1105 // The asm statement must also use `%U<opno>' as a 1106 // placeholder for the "update" flag in the corresponding 1107 // load or store instruction. For example: 1108 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1109 // is correct but: 1110 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1111 // is not. Use es rather than m if you don't want the base 1112 // register to be updated. 1113 case 'e': 1114 if (Name[1] != 's') 1115 return false; 1116 // es: A "stable" memory operand; that is, one which does not 1117 // include any automodification of the base register. Unlike 1118 // `m', this constraint can be used in asm statements that 1119 // might access the operand several times, or that might not 1120 // access it at all. 1121 Info.setAllowsMemory(); 1122 Name++; // Skip over 'e'. 1123 break; 1124 case 'Q': // Memory operand that is an offset from a register (it is 1125 // usually better to use `m' or `es' in asm statements) 1126 case 'Z': // Memory operand that is an indexed or indirect from a 1127 // register (it is usually better to use `m' or `es' in 1128 // asm statements) 1129 Info.setAllowsMemory(); 1130 Info.setAllowsRegister(); 1131 break; 1132 case 'R': // AIX TOC entry 1133 case 'a': // Address operand that is an indexed or indirect from a 1134 // register (`p' is preferable for asm statements) 1135 case 'S': // Constant suitable as a 64-bit mask operand 1136 case 'T': // Constant suitable as a 32-bit mask operand 1137 case 'U': // System V Release 4 small data area reference 1138 case 't': // AND masks that can be performed by two rldic{l, r} 1139 // instructions 1140 case 'W': // Vector constant that does not require memory 1141 case 'j': // Vector constant that is all zeros. 1142 break; 1143 // End FIXME. 1144 } 1145 return true; 1146 } 1147 std::string convertConstraint(const char *&Constraint) const override { 1148 std::string R; 1149 switch (*Constraint) { 1150 case 'e': 1151 case 'w': 1152 // Two-character constraint; add "^" hint for later parsing. 1153 R = std::string("^") + std::string(Constraint, 2); 1154 Constraint++; 1155 break; 1156 default: 1157 return TargetInfo::convertConstraint(Constraint); 1158 } 1159 return R; 1160 } 1161 const char *getClobbers() const override { 1162 return ""; 1163 } 1164 int getEHDataRegisterNumber(unsigned RegNo) const override { 1165 if (RegNo == 0) return 3; 1166 if (RegNo == 1) return 4; 1167 return -1; 1168 } 1169 1170 bool hasSjLjLowering() const override { 1171 return true; 1172 } 1173 1174 bool useFloat128ManglingForLongDouble() const override { 1175 return LongDoubleWidth == 128 && 1176 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1177 getTriple().isOSBinFormatELF(); 1178 } 1179 }; 1180 1181 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1182 #define BUILTIN(ID, TYPE, ATTRS) \ 1183 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1184 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1185 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1186 #include "clang/Basic/BuiltinsPPC.def" 1187 }; 1188 1189 /// handleTargetFeatures - Perform initialization based on the user 1190 /// configured set of features. 1191 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1192 DiagnosticsEngine &Diags) { 1193 for (const auto &Feature : Features) { 1194 if (Feature == "+altivec") { 1195 HasAltivec = true; 1196 } else if (Feature == "+vsx") { 1197 HasVSX = true; 1198 } else if (Feature == "+bpermd") { 1199 HasBPERMD = true; 1200 } else if (Feature == "+extdiv") { 1201 HasExtDiv = true; 1202 } else if (Feature == "+power8-vector") { 1203 HasP8Vector = true; 1204 } else if (Feature == "+crypto") { 1205 HasP8Crypto = true; 1206 } else if (Feature == "+direct-move") { 1207 HasDirectMove = true; 1208 } else if (Feature == "+qpx") { 1209 HasQPX = true; 1210 } else if (Feature == "+htm") { 1211 HasHTM = true; 1212 } else if (Feature == "+float128") { 1213 HasFloat128 = true; 1214 } else if (Feature == "+power9-vector") { 1215 HasP9Vector = true; 1216 } 1217 // TODO: Finish this list and add an assert that we've handled them 1218 // all. 1219 } 1220 1221 return true; 1222 } 1223 1224 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1225 /// #defines that are not tied to a specific subtarget. 1226 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1227 MacroBuilder &Builder) const { 1228 // Target identification. 1229 Builder.defineMacro("__ppc__"); 1230 Builder.defineMacro("__PPC__"); 1231 Builder.defineMacro("_ARCH_PPC"); 1232 Builder.defineMacro("__powerpc__"); 1233 Builder.defineMacro("__POWERPC__"); 1234 if (PointerWidth == 64) { 1235 Builder.defineMacro("_ARCH_PPC64"); 1236 Builder.defineMacro("__powerpc64__"); 1237 Builder.defineMacro("__ppc64__"); 1238 Builder.defineMacro("__PPC64__"); 1239 } 1240 1241 // Target properties. 1242 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1243 Builder.defineMacro("_LITTLE_ENDIAN"); 1244 } else { 1245 if (getTriple().getOS() != llvm::Triple::NetBSD && 1246 getTriple().getOS() != llvm::Triple::OpenBSD) 1247 Builder.defineMacro("_BIG_ENDIAN"); 1248 } 1249 1250 // ABI options. 1251 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1252 Builder.defineMacro("_CALL_ELF", "1"); 1253 if (ABI == "elfv2") 1254 Builder.defineMacro("_CALL_ELF", "2"); 1255 1256 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 1257 // our suppport post-dates this and it should work on all 64-bit ppc linux 1258 // platforms. It is guaranteed to work on all elfv2 platforms. 1259 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 1260 Builder.defineMacro("_CALL_LINUX", "1"); 1261 1262 // Subtarget options. 1263 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1264 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1265 1266 // FIXME: Should be controlled by command line option. 1267 if (LongDoubleWidth == 128) { 1268 Builder.defineMacro("__LONG_DOUBLE_128__"); 1269 Builder.defineMacro("__LONGDOUBLE128"); 1270 } 1271 1272 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1273 if (ABI == "elfv2" || 1274 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1275 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1276 1277 // CPU identification. 1278 ArchDefineTypes defs = 1279 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1280 .Case("440", ArchDefineName) 1281 .Case("450", ArchDefineName | ArchDefine440) 1282 .Case("601", ArchDefineName) 1283 .Case("602", ArchDefineName | ArchDefinePpcgr) 1284 .Case("603", ArchDefineName | ArchDefinePpcgr) 1285 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1286 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1287 .Case("604", ArchDefineName | ArchDefinePpcgr) 1288 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1289 .Case("620", ArchDefineName | ArchDefinePpcgr) 1290 .Case("630", ArchDefineName | ArchDefinePpcgr) 1291 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1292 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1293 .Case("750", ArchDefineName | ArchDefinePpcgr) 1294 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1295 ArchDefinePpcsq) 1296 .Case("a2", ArchDefineA2) 1297 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1298 .Case("pwr3", ArchDefinePpcgr) 1299 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1300 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1301 ArchDefinePpcsq) 1302 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 | 1303 ArchDefinePpcgr | ArchDefinePpcsq) 1304 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 | 1305 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1306 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x | 1307 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1308 ArchDefinePpcsq) 1309 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 | 1310 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1311 ArchDefinePpcgr | ArchDefinePpcsq) 1312 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x | 1313 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1314 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1315 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 | 1316 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1317 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1318 ArchDefinePpcsq) 1319 .Case("power3", ArchDefinePpcgr) 1320 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1321 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1322 ArchDefinePpcsq) 1323 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1324 ArchDefinePpcgr | ArchDefinePpcsq) 1325 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1326 ArchDefinePwr4 | ArchDefinePpcgr | 1327 ArchDefinePpcsq) 1328 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1329 ArchDefinePwr5 | ArchDefinePwr4 | 1330 ArchDefinePpcgr | ArchDefinePpcsq) 1331 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | 1332 ArchDefinePwr5x | ArchDefinePwr5 | 1333 ArchDefinePwr4 | ArchDefinePpcgr | 1334 ArchDefinePpcsq) 1335 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1336 ArchDefinePwr6 | ArchDefinePwr5x | 1337 ArchDefinePwr5 | ArchDefinePwr4 | 1338 ArchDefinePpcgr | ArchDefinePpcsq) 1339 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 1340 ArchDefinePwr6x | ArchDefinePwr6 | 1341 ArchDefinePwr5x | ArchDefinePwr5 | 1342 ArchDefinePwr4 | ArchDefinePpcgr | 1343 ArchDefinePpcsq) 1344 // powerpc64le automatically defaults to at least power8. 1345 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1346 ArchDefinePwr6 | ArchDefinePwr5x | 1347 ArchDefinePwr5 | ArchDefinePwr4 | 1348 ArchDefinePpcgr | ArchDefinePpcsq) 1349 .Default(ArchDefineNone); 1350 1351 if (defs & ArchDefineName) 1352 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1353 if (defs & ArchDefinePpcgr) 1354 Builder.defineMacro("_ARCH_PPCGR"); 1355 if (defs & ArchDefinePpcsq) 1356 Builder.defineMacro("_ARCH_PPCSQ"); 1357 if (defs & ArchDefine440) 1358 Builder.defineMacro("_ARCH_440"); 1359 if (defs & ArchDefine603) 1360 Builder.defineMacro("_ARCH_603"); 1361 if (defs & ArchDefine604) 1362 Builder.defineMacro("_ARCH_604"); 1363 if (defs & ArchDefinePwr4) 1364 Builder.defineMacro("_ARCH_PWR4"); 1365 if (defs & ArchDefinePwr5) 1366 Builder.defineMacro("_ARCH_PWR5"); 1367 if (defs & ArchDefinePwr5x) 1368 Builder.defineMacro("_ARCH_PWR5X"); 1369 if (defs & ArchDefinePwr6) 1370 Builder.defineMacro("_ARCH_PWR6"); 1371 if (defs & ArchDefinePwr6x) 1372 Builder.defineMacro("_ARCH_PWR6X"); 1373 if (defs & ArchDefinePwr7) 1374 Builder.defineMacro("_ARCH_PWR7"); 1375 if (defs & ArchDefinePwr8) 1376 Builder.defineMacro("_ARCH_PWR8"); 1377 if (defs & ArchDefinePwr9) 1378 Builder.defineMacro("_ARCH_PWR9"); 1379 if (defs & ArchDefineA2) 1380 Builder.defineMacro("_ARCH_A2"); 1381 if (defs & ArchDefineA2q) { 1382 Builder.defineMacro("_ARCH_A2Q"); 1383 Builder.defineMacro("_ARCH_QP"); 1384 } 1385 1386 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1387 Builder.defineMacro("__bg__"); 1388 Builder.defineMacro("__THW_BLUEGENE__"); 1389 Builder.defineMacro("__bgq__"); 1390 Builder.defineMacro("__TOS_BGQ__"); 1391 } 1392 1393 if (HasAltivec) { 1394 Builder.defineMacro("__VEC__", "10206"); 1395 Builder.defineMacro("__ALTIVEC__"); 1396 } 1397 if (HasVSX) 1398 Builder.defineMacro("__VSX__"); 1399 if (HasP8Vector) 1400 Builder.defineMacro("__POWER8_VECTOR__"); 1401 if (HasP8Crypto) 1402 Builder.defineMacro("__CRYPTO__"); 1403 if (HasHTM) 1404 Builder.defineMacro("__HTM__"); 1405 if (HasFloat128) 1406 Builder.defineMacro("__FLOAT128__"); 1407 if (HasP9Vector) 1408 Builder.defineMacro("__POWER9_VECTOR__"); 1409 1410 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1411 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1412 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1413 if (PointerWidth == 64) 1414 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1415 1416 // We have support for the bswap intrinsics so we can define this. 1417 Builder.defineMacro("__HAVE_BSWAP__", "1"); 1418 1419 // FIXME: The following are not yet generated here by Clang, but are 1420 // generated by GCC: 1421 // 1422 // _SOFT_FLOAT_ 1423 // __RECIP_PRECISION__ 1424 // __APPLE_ALTIVEC__ 1425 // __RECIP__ 1426 // __RECIPF__ 1427 // __RSQRTE__ 1428 // __RSQRTEF__ 1429 // _SOFT_DOUBLE_ 1430 // __NO_LWSYNC__ 1431 // __CMODEL_MEDIUM__ 1432 // __CMODEL_LARGE__ 1433 // _CALL_SYSV 1434 // _CALL_DARWIN 1435 // __NO_FPRS__ 1436 } 1437 1438 // Handle explicit options being passed to the compiler here: if we've 1439 // explicitly turned off vsx and turned on any of: 1440 // - power8-vector 1441 // - direct-move 1442 // - float128 1443 // - power9-vector 1444 // then go ahead and error since the customer has expressed an incompatible 1445 // set of options. 1446 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1447 const std::vector<std::string> &FeaturesVec) { 1448 1449 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1450 FeaturesVec.end()) { 1451 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1452 FeaturesVec.end()) { 1453 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1454 << "-mno-vsx"; 1455 return false; 1456 } 1457 1458 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1459 FeaturesVec.end()) { 1460 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1461 << "-mno-vsx"; 1462 return false; 1463 } 1464 1465 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1466 FeaturesVec.end()) { 1467 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1468 << "-mno-vsx"; 1469 return false; 1470 } 1471 1472 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1473 FeaturesVec.end()) { 1474 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1475 << "-mno-vsx"; 1476 return false; 1477 } 1478 } 1479 1480 return true; 1481 } 1482 1483 bool PPCTargetInfo::initFeatureMap( 1484 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1485 const std::vector<std::string> &FeaturesVec) const { 1486 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1487 .Case("7400", true) 1488 .Case("g4", true) 1489 .Case("7450", true) 1490 .Case("g4+", true) 1491 .Case("970", true) 1492 .Case("g5", true) 1493 .Case("pwr6", true) 1494 .Case("pwr7", true) 1495 .Case("pwr8", true) 1496 .Case("pwr9", true) 1497 .Case("ppc64", true) 1498 .Case("ppc64le", true) 1499 .Default(false); 1500 1501 Features["qpx"] = (CPU == "a2q"); 1502 Features["power9-vector"] = (CPU == "pwr9"); 1503 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1504 .Case("ppc64le", true) 1505 .Case("pwr9", true) 1506 .Case("pwr8", true) 1507 .Default(false); 1508 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1509 .Case("ppc64le", true) 1510 .Case("pwr9", true) 1511 .Case("pwr8", true) 1512 .Default(false); 1513 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1514 .Case("ppc64le", true) 1515 .Case("pwr9", true) 1516 .Case("pwr8", true) 1517 .Case("pwr7", true) 1518 .Default(false); 1519 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1520 .Case("ppc64le", true) 1521 .Case("pwr9", true) 1522 .Case("pwr8", true) 1523 .Case("pwr7", true) 1524 .Default(false); 1525 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1526 .Case("ppc64le", true) 1527 .Case("pwr9", true) 1528 .Case("pwr8", true) 1529 .Default(false); 1530 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1531 .Case("ppc64le", true) 1532 .Case("pwr9", true) 1533 .Case("pwr8", true) 1534 .Case("pwr7", true) 1535 .Default(false); 1536 Features["htm"] = llvm::StringSwitch<bool>(CPU) 1537 .Case("ppc64le", true) 1538 .Case("pwr9", true) 1539 .Case("pwr8", true) 1540 .Default(false); 1541 1542 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1543 return false; 1544 1545 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1546 } 1547 1548 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1549 return llvm::StringSwitch<bool>(Feature) 1550 .Case("powerpc", true) 1551 .Case("altivec", HasAltivec) 1552 .Case("vsx", HasVSX) 1553 .Case("power8-vector", HasP8Vector) 1554 .Case("crypto", HasP8Crypto) 1555 .Case("direct-move", HasDirectMove) 1556 .Case("qpx", HasQPX) 1557 .Case("htm", HasHTM) 1558 .Case("bpermd", HasBPERMD) 1559 .Case("extdiv", HasExtDiv) 1560 .Case("float128", HasFloat128) 1561 .Case("power9-vector", HasP9Vector) 1562 .Default(false); 1563 } 1564 1565 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1566 StringRef Name, bool Enabled) const { 1567 if (Enabled) { 1568 // If we're enabling any of the vsx based features then enable vsx and 1569 // altivec. We'll diagnose any problems later. 1570 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name) 1571 .Case("vsx", true) 1572 .Case("direct-move", true) 1573 .Case("power8-vector", true) 1574 .Case("power9-vector", true) 1575 .Case("float128", true) 1576 .Default(false); 1577 if (FeatureHasVSX) 1578 Features["vsx"] = Features["altivec"] = true; 1579 if (Name == "power9-vector") 1580 Features["power8-vector"] = true; 1581 Features[Name] = true; 1582 } else { 1583 // If we're disabling altivec or vsx go ahead and disable all of the vsx 1584 // features. 1585 if ((Name == "altivec") || (Name == "vsx")) 1586 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] = 1587 Features["float128"] = Features["power9-vector"] = false; 1588 if (Name == "power8-vector") 1589 Features["power9-vector"] = false; 1590 Features[Name] = false; 1591 } 1592 } 1593 1594 const char * const PPCTargetInfo::GCCRegNames[] = { 1595 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1596 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1597 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1598 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1599 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1600 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1601 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1602 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1603 "mq", "lr", "ctr", "ap", 1604 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1605 "xer", 1606 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1607 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1608 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1609 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1610 "vrsave", "vscr", 1611 "spe_acc", "spefscr", 1612 "sfp" 1613 }; 1614 1615 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1616 return llvm::makeArrayRef(GCCRegNames); 1617 } 1618 1619 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1620 // While some of these aliases do map to different registers 1621 // they still share the same register name. 1622 { { "0" }, "r0" }, 1623 { { "1"}, "r1" }, 1624 { { "2" }, "r2" }, 1625 { { "3" }, "r3" }, 1626 { { "4" }, "r4" }, 1627 { { "5" }, "r5" }, 1628 { { "6" }, "r6" }, 1629 { { "7" }, "r7" }, 1630 { { "8" }, "r8" }, 1631 { { "9" }, "r9" }, 1632 { { "10" }, "r10" }, 1633 { { "11" }, "r11" }, 1634 { { "12" }, "r12" }, 1635 { { "13" }, "r13" }, 1636 { { "14" }, "r14" }, 1637 { { "15" }, "r15" }, 1638 { { "16" }, "r16" }, 1639 { { "17" }, "r17" }, 1640 { { "18" }, "r18" }, 1641 { { "19" }, "r19" }, 1642 { { "20" }, "r20" }, 1643 { { "21" }, "r21" }, 1644 { { "22" }, "r22" }, 1645 { { "23" }, "r23" }, 1646 { { "24" }, "r24" }, 1647 { { "25" }, "r25" }, 1648 { { "26" }, "r26" }, 1649 { { "27" }, "r27" }, 1650 { { "28" }, "r28" }, 1651 { { "29" }, "r29" }, 1652 { { "30" }, "r30" }, 1653 { { "31" }, "r31" }, 1654 { { "fr0" }, "f0" }, 1655 { { "fr1" }, "f1" }, 1656 { { "fr2" }, "f2" }, 1657 { { "fr3" }, "f3" }, 1658 { { "fr4" }, "f4" }, 1659 { { "fr5" }, "f5" }, 1660 { { "fr6" }, "f6" }, 1661 { { "fr7" }, "f7" }, 1662 { { "fr8" }, "f8" }, 1663 { { "fr9" }, "f9" }, 1664 { { "fr10" }, "f10" }, 1665 { { "fr11" }, "f11" }, 1666 { { "fr12" }, "f12" }, 1667 { { "fr13" }, "f13" }, 1668 { { "fr14" }, "f14" }, 1669 { { "fr15" }, "f15" }, 1670 { { "fr16" }, "f16" }, 1671 { { "fr17" }, "f17" }, 1672 { { "fr18" }, "f18" }, 1673 { { "fr19" }, "f19" }, 1674 { { "fr20" }, "f20" }, 1675 { { "fr21" }, "f21" }, 1676 { { "fr22" }, "f22" }, 1677 { { "fr23" }, "f23" }, 1678 { { "fr24" }, "f24" }, 1679 { { "fr25" }, "f25" }, 1680 { { "fr26" }, "f26" }, 1681 { { "fr27" }, "f27" }, 1682 { { "fr28" }, "f28" }, 1683 { { "fr29" }, "f29" }, 1684 { { "fr30" }, "f30" }, 1685 { { "fr31" }, "f31" }, 1686 { { "cc" }, "cr0" }, 1687 }; 1688 1689 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1690 return llvm::makeArrayRef(GCCRegAliases); 1691 } 1692 1693 class PPC32TargetInfo : public PPCTargetInfo { 1694 public: 1695 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1696 : PPCTargetInfo(Triple, Opts) { 1697 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1698 1699 switch (getTriple().getOS()) { 1700 case llvm::Triple::Linux: 1701 case llvm::Triple::FreeBSD: 1702 case llvm::Triple::NetBSD: 1703 SizeType = UnsignedInt; 1704 PtrDiffType = SignedInt; 1705 IntPtrType = SignedInt; 1706 break; 1707 default: 1708 break; 1709 } 1710 1711 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1712 LongDoubleWidth = LongDoubleAlign = 64; 1713 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1714 } 1715 1716 // PPC32 supports atomics up to 4 bytes. 1717 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1718 } 1719 1720 BuiltinVaListKind getBuiltinVaListKind() const override { 1721 // This is the ELF definition, and is overridden by the Darwin sub-target 1722 return TargetInfo::PowerABIBuiltinVaList; 1723 } 1724 }; 1725 1726 // Note: ABI differences may eventually require us to have a separate 1727 // TargetInfo for little endian. 1728 class PPC64TargetInfo : public PPCTargetInfo { 1729 public: 1730 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1731 : PPCTargetInfo(Triple, Opts) { 1732 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1733 IntMaxType = SignedLong; 1734 Int64Type = SignedLong; 1735 1736 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1737 resetDataLayout("e-m:e-i64:64-n32:64"); 1738 ABI = "elfv2"; 1739 } else { 1740 resetDataLayout("E-m:e-i64:64-n32:64"); 1741 ABI = "elfv1"; 1742 } 1743 1744 switch (getTriple().getOS()) { 1745 case llvm::Triple::FreeBSD: 1746 LongDoubleWidth = LongDoubleAlign = 64; 1747 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1748 break; 1749 case llvm::Triple::NetBSD: 1750 IntMaxType = SignedLongLong; 1751 Int64Type = SignedLongLong; 1752 break; 1753 default: 1754 break; 1755 } 1756 1757 // PPC64 supports atomics up to 8 bytes. 1758 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1759 } 1760 BuiltinVaListKind getBuiltinVaListKind() const override { 1761 return TargetInfo::CharPtrBuiltinVaList; 1762 } 1763 // PPC64 Linux-specific ABI options. 1764 bool setABI(const std::string &Name) override { 1765 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1766 ABI = Name; 1767 return true; 1768 } 1769 return false; 1770 } 1771 }; 1772 1773 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1774 public: 1775 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1776 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1777 HasAlignMac68kSupport = true; 1778 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1779 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1780 LongLongAlign = 32; 1781 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1782 } 1783 BuiltinVaListKind getBuiltinVaListKind() const override { 1784 return TargetInfo::CharPtrBuiltinVaList; 1785 } 1786 }; 1787 1788 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1789 public: 1790 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1791 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1792 HasAlignMac68kSupport = true; 1793 resetDataLayout("E-m:o-i64:64-n32:64"); 1794 } 1795 }; 1796 1797 static const unsigned NVPTXAddrSpaceMap[] = { 1798 0, // Default 1799 1, // opencl_global 1800 3, // opencl_local 1801 4, // opencl_constant 1802 // FIXME: generic has to be added to the target 1803 0, // opencl_generic 1804 1, // cuda_device 1805 4, // cuda_constant 1806 3, // cuda_shared 1807 }; 1808 1809 class NVPTXTargetInfo : public TargetInfo { 1810 static const char *const GCCRegNames[]; 1811 static const Builtin::Info BuiltinInfo[]; 1812 CudaArch GPU; 1813 std::unique_ptr<TargetInfo> HostTarget; 1814 1815 public: 1816 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1817 unsigned TargetPointerWidth) 1818 : TargetInfo(Triple) { 1819 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1820 "NVPTX only supports 32- and 64-bit modes."); 1821 1822 TLSSupported = false; 1823 AddrSpaceMap = &NVPTXAddrSpaceMap; 1824 UseAddrSpaceMapMangling = true; 1825 1826 // Define available target features 1827 // These must be defined in sorted order! 1828 NoAsmVariants = true; 1829 GPU = CudaArch::SM_20; 1830 1831 if (TargetPointerWidth == 32) 1832 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1833 else 1834 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1835 1836 // If possible, get a TargetInfo for our host triple, so we can match its 1837 // types. 1838 llvm::Triple HostTriple(Opts.HostTriple); 1839 if (!HostTriple.isNVPTX()) 1840 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1841 1842 // If no host target, make some guesses about the data layout and return. 1843 if (!HostTarget) { 1844 LongWidth = LongAlign = TargetPointerWidth; 1845 PointerWidth = PointerAlign = TargetPointerWidth; 1846 switch (TargetPointerWidth) { 1847 case 32: 1848 SizeType = TargetInfo::UnsignedInt; 1849 PtrDiffType = TargetInfo::SignedInt; 1850 IntPtrType = TargetInfo::SignedInt; 1851 break; 1852 case 64: 1853 SizeType = TargetInfo::UnsignedLong; 1854 PtrDiffType = TargetInfo::SignedLong; 1855 IntPtrType = TargetInfo::SignedLong; 1856 break; 1857 default: 1858 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1859 } 1860 return; 1861 } 1862 1863 // Copy properties from host target. 1864 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1865 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1866 BoolWidth = HostTarget->getBoolWidth(); 1867 BoolAlign = HostTarget->getBoolAlign(); 1868 IntWidth = HostTarget->getIntWidth(); 1869 IntAlign = HostTarget->getIntAlign(); 1870 HalfWidth = HostTarget->getHalfWidth(); 1871 HalfAlign = HostTarget->getHalfAlign(); 1872 FloatWidth = HostTarget->getFloatWidth(); 1873 FloatAlign = HostTarget->getFloatAlign(); 1874 DoubleWidth = HostTarget->getDoubleWidth(); 1875 DoubleAlign = HostTarget->getDoubleAlign(); 1876 LongWidth = HostTarget->getLongWidth(); 1877 LongAlign = HostTarget->getLongAlign(); 1878 LongLongWidth = HostTarget->getLongLongWidth(); 1879 LongLongAlign = HostTarget->getLongLongAlign(); 1880 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1881 NewAlign = HostTarget->getNewAlign(); 1882 DefaultAlignForAttributeAligned = 1883 HostTarget->getDefaultAlignForAttributeAligned(); 1884 SizeType = HostTarget->getSizeType(); 1885 IntMaxType = HostTarget->getIntMaxType(); 1886 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1887 IntPtrType = HostTarget->getIntPtrType(); 1888 WCharType = HostTarget->getWCharType(); 1889 WIntType = HostTarget->getWIntType(); 1890 Char16Type = HostTarget->getChar16Type(); 1891 Char32Type = HostTarget->getChar32Type(); 1892 Int64Type = HostTarget->getInt64Type(); 1893 SigAtomicType = HostTarget->getSigAtomicType(); 1894 ProcessIDType = HostTarget->getProcessIDType(); 1895 1896 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1897 UseZeroLengthBitfieldAlignment = 1898 HostTarget->useZeroLengthBitfieldAlignment(); 1899 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1900 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1901 1902 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1903 // we need those macros to be identical on host and device, because (among 1904 // other things) they affect which standard library classes are defined, and 1905 // we need all classes to be defined on both the host and device. 1906 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1907 1908 // Properties intentionally not copied from host: 1909 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1910 // host/device boundary. 1911 // - SuitableAlign: Not visible across the host/device boundary, and may 1912 // correctly be different on host/device, e.g. if host has wider vector 1913 // types than device. 1914 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1915 // as its double type, but that's not necessarily true on the host. 1916 // TODO: nvcc emits a warning when using long double on device; we should 1917 // do the same. 1918 } 1919 void getTargetDefines(const LangOptions &Opts, 1920 MacroBuilder &Builder) const override { 1921 Builder.defineMacro("__PTX__"); 1922 Builder.defineMacro("__NVPTX__"); 1923 if (Opts.CUDAIsDevice) { 1924 // Set __CUDA_ARCH__ for the GPU specified. 1925 std::string CUDAArchCode = [this] { 1926 switch (GPU) { 1927 case CudaArch::UNKNOWN: 1928 assert(false && "No GPU arch when compiling CUDA device code."); 1929 return ""; 1930 case CudaArch::SM_20: 1931 return "200"; 1932 case CudaArch::SM_21: 1933 return "210"; 1934 case CudaArch::SM_30: 1935 return "300"; 1936 case CudaArch::SM_32: 1937 return "320"; 1938 case CudaArch::SM_35: 1939 return "350"; 1940 case CudaArch::SM_37: 1941 return "370"; 1942 case CudaArch::SM_50: 1943 return "500"; 1944 case CudaArch::SM_52: 1945 return "520"; 1946 case CudaArch::SM_53: 1947 return "530"; 1948 case CudaArch::SM_60: 1949 return "600"; 1950 case CudaArch::SM_61: 1951 return "610"; 1952 case CudaArch::SM_62: 1953 return "620"; 1954 } 1955 llvm_unreachable("unhandled CudaArch"); 1956 }(); 1957 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1958 } 1959 } 1960 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1961 return llvm::makeArrayRef(BuiltinInfo, 1962 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1963 } 1964 bool 1965 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1966 StringRef CPU, 1967 const std::vector<std::string> &FeaturesVec) const override { 1968 Features["satom"] = GPU >= CudaArch::SM_60; 1969 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1970 } 1971 1972 bool hasFeature(StringRef Feature) const override { 1973 return llvm::StringSwitch<bool>(Feature) 1974 .Cases("ptx", "nvptx", true) 1975 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1976 .Default(false); 1977 } 1978 1979 ArrayRef<const char *> getGCCRegNames() const override; 1980 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1981 // No aliases. 1982 return None; 1983 } 1984 bool validateAsmConstraint(const char *&Name, 1985 TargetInfo::ConstraintInfo &Info) const override { 1986 switch (*Name) { 1987 default: 1988 return false; 1989 case 'c': 1990 case 'h': 1991 case 'r': 1992 case 'l': 1993 case 'f': 1994 case 'd': 1995 Info.setAllowsRegister(); 1996 return true; 1997 } 1998 } 1999 const char *getClobbers() const override { 2000 // FIXME: Is this really right? 2001 return ""; 2002 } 2003 BuiltinVaListKind getBuiltinVaListKind() const override { 2004 // FIXME: implement 2005 return TargetInfo::CharPtrBuiltinVaList; 2006 } 2007 bool setCPU(const std::string &Name) override { 2008 GPU = StringToCudaArch(Name); 2009 return GPU != CudaArch::UNKNOWN; 2010 } 2011 void setSupportedOpenCLOpts() override { 2012 auto &Opts = getSupportedOpenCLOpts(); 2013 Opts.support("cl_clang_storage_class_specifiers"); 2014 Opts.support("cl_khr_gl_sharing"); 2015 Opts.support("cl_khr_icd"); 2016 2017 Opts.support("cl_khr_fp64"); 2018 Opts.support("cl_khr_byte_addressable_store"); 2019 Opts.support("cl_khr_global_int32_base_atomics"); 2020 Opts.support("cl_khr_global_int32_extended_atomics"); 2021 Opts.support("cl_khr_local_int32_base_atomics"); 2022 Opts.support("cl_khr_local_int32_extended_atomics"); 2023 } 2024 2025 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2026 // CUDA compilations support all of the host's calling conventions. 2027 // 2028 // TODO: We should warn if you apply a non-default CC to anything other than 2029 // a host function. 2030 if (HostTarget) 2031 return HostTarget->checkCallingConvention(CC); 2032 return CCCR_Warning; 2033 } 2034 }; 2035 2036 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 2037 #define BUILTIN(ID, TYPE, ATTRS) \ 2038 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2039 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2040 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2041 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2042 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2043 #include "clang/Basic/BuiltinsNVPTX.def" 2044 }; 2045 2046 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 2047 2048 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 2049 return llvm::makeArrayRef(GCCRegNames); 2050 } 2051 2052 static const LangAS::Map AMDGPUPrivIsZeroDefIsGenMap = { 2053 4, // Default 2054 1, // opencl_global 2055 3, // opencl_local 2056 2, // opencl_constant 2057 4, // opencl_generic 2058 1, // cuda_device 2059 2, // cuda_constant 2060 3 // cuda_shared 2061 }; 2062 static const LangAS::Map AMDGPUGenIsZeroDefIsGenMap = { 2063 0, // Default 2064 1, // opencl_global 2065 3, // opencl_local 2066 2, // opencl_constant 2067 0, // opencl_generic 2068 1, // cuda_device 2069 2, // cuda_constant 2070 3 // cuda_shared 2071 }; 2072 static const LangAS::Map AMDGPUPrivIsZeroDefIsPrivMap = { 2073 0, // Default 2074 1, // opencl_global 2075 3, // opencl_local 2076 2, // opencl_constant 2077 4, // opencl_generic 2078 1, // cuda_device 2079 2, // cuda_constant 2080 3 // cuda_shared 2081 }; 2082 static const LangAS::Map AMDGPUGenIsZeroDefIsPrivMap = { 2083 5, // Default 2084 1, // opencl_global 2085 3, // opencl_local 2086 2, // opencl_constant 2087 0, // opencl_generic 2088 1, // cuda_device 2089 2, // cuda_constant 2090 3 // cuda_shared 2091 }; 2092 2093 // If you edit the description strings, make sure you update 2094 // getPointerWidthV(). 2095 2096 static const char *const DataLayoutStringR600 = 2097 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2098 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2099 2100 static const char *const DataLayoutStringSIPrivateIsZero = 2101 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2102 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2103 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2104 2105 static const char *const DataLayoutStringSIGenericIsZero = 2106 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" 2107 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2108 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; 2109 2110 class AMDGPUTargetInfo final : public TargetInfo { 2111 static const Builtin::Info BuiltinInfo[]; 2112 static const char * const GCCRegNames[]; 2113 2114 struct AddrSpace { 2115 unsigned Generic, Global, Local, Constant, Private; 2116 AddrSpace(bool IsGenericZero_ = false){ 2117 if (IsGenericZero_) { 2118 Generic = 0; 2119 Global = 1; 2120 Local = 3; 2121 Constant = 2; 2122 Private = 5; 2123 } else { 2124 Generic = 4; 2125 Global = 1; 2126 Local = 3; 2127 Constant = 2; 2128 Private = 0; 2129 } 2130 } 2131 }; 2132 2133 /// \brief The GPU profiles supported by the AMDGPU target. 2134 enum GPUKind { 2135 GK_NONE, 2136 GK_R600, 2137 GK_R600_DOUBLE_OPS, 2138 GK_R700, 2139 GK_R700_DOUBLE_OPS, 2140 GK_EVERGREEN, 2141 GK_EVERGREEN_DOUBLE_OPS, 2142 GK_NORTHERN_ISLANDS, 2143 GK_CAYMAN, 2144 GK_GFX6, 2145 GK_GFX7, 2146 GK_GFX8, 2147 GK_GFX9 2148 } GPU; 2149 2150 bool hasFP64:1; 2151 bool hasFMAF:1; 2152 bool hasLDEXPF:1; 2153 const AddrSpace AS; 2154 2155 static bool hasFullSpeedFMAF32(StringRef GPUName) { 2156 return parseAMDGCNName(GPUName) >= GK_GFX9; 2157 } 2158 2159 static bool isAMDGCN(const llvm::Triple &TT) { 2160 return TT.getArch() == llvm::Triple::amdgcn; 2161 } 2162 2163 static bool isGenericZero(const llvm::Triple &TT) { 2164 return TT.getEnvironmentName() == "amdgiz" || 2165 TT.getEnvironmentName() == "amdgizcl"; 2166 } 2167 public: 2168 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2169 : TargetInfo(Triple) , 2170 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2171 hasFP64(false), 2172 hasFMAF(false), 2173 hasLDEXPF(false), 2174 AS(isGenericZero(Triple)){ 2175 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2176 hasFP64 = true; 2177 hasFMAF = true; 2178 hasLDEXPF = true; 2179 } 2180 auto IsGenericZero = isGenericZero(Triple); 2181 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2182 (IsGenericZero ? DataLayoutStringSIGenericIsZero : 2183 DataLayoutStringSIPrivateIsZero) 2184 : DataLayoutStringR600); 2185 assert(DataLayout->getAllocaAddrSpace() == AS.Private); 2186 2187 setAddressSpaceMap(Triple.getOS() == llvm::Triple::Mesa3D || 2188 Triple.getEnvironment() == llvm::Triple::OpenCL || 2189 Triple.getEnvironmentName() == "amdgizcl" || 2190 !isAMDGCN(Triple)); 2191 UseAddrSpaceMapMangling = true; 2192 2193 // Set pointer width and alignment for target address space 0. 2194 PointerWidth = PointerAlign = DataLayout->getPointerSizeInBits(); 2195 if (getMaxPointerWidth() == 64) { 2196 LongWidth = LongAlign = 64; 2197 SizeType = UnsignedLong; 2198 PtrDiffType = SignedLong; 2199 IntPtrType = SignedLong; 2200 } 2201 } 2202 2203 void setAddressSpaceMap(bool DefaultIsPrivate) { 2204 if (isGenericZero(getTriple())) { 2205 AddrSpaceMap = DefaultIsPrivate ? &AMDGPUGenIsZeroDefIsPrivMap 2206 : &AMDGPUGenIsZeroDefIsGenMap; 2207 } else { 2208 AddrSpaceMap = DefaultIsPrivate ? &AMDGPUPrivIsZeroDefIsPrivMap 2209 : &AMDGPUPrivIsZeroDefIsGenMap; 2210 } 2211 } 2212 2213 void adjust(LangOptions &Opts) override { 2214 TargetInfo::adjust(Opts); 2215 setAddressSpaceMap(Opts.OpenCL || !isAMDGCN(getTriple())); 2216 } 2217 2218 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2219 if (GPU <= GK_CAYMAN) 2220 return 32; 2221 2222 if (AddrSpace == AS.Private || AddrSpace == AS.Local) { 2223 return 32; 2224 } 2225 return 64; 2226 } 2227 2228 uint64_t getPointerAlignV(unsigned AddrSpace) const override { 2229 return getPointerWidthV(AddrSpace); 2230 } 2231 2232 uint64_t getMaxPointerWidth() const override { 2233 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2234 } 2235 2236 const char * getClobbers() const override { 2237 return ""; 2238 } 2239 2240 ArrayRef<const char *> getGCCRegNames() const override; 2241 2242 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2243 return None; 2244 } 2245 2246 bool validateAsmConstraint(const char *&Name, 2247 TargetInfo::ConstraintInfo &Info) const override { 2248 switch (*Name) { 2249 default: break; 2250 case 'v': // vgpr 2251 case 's': // sgpr 2252 Info.setAllowsRegister(); 2253 return true; 2254 } 2255 return false; 2256 } 2257 2258 bool initFeatureMap(llvm::StringMap<bool> &Features, 2259 DiagnosticsEngine &Diags, StringRef CPU, 2260 const std::vector<std::string> &FeatureVec) const override; 2261 2262 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2263 TargetOptions &TargetOpts) const override { 2264 bool hasFP32Denormals = false; 2265 bool hasFP64Denormals = false; 2266 for (auto &I : TargetOpts.FeaturesAsWritten) { 2267 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2268 hasFP32Denormals = true; 2269 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2270 hasFP64Denormals = true; 2271 } 2272 if (!hasFP32Denormals) 2273 TargetOpts.Features.push_back( 2274 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) && 2275 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2276 // Always do not flush fp64 or fp16 denorms. 2277 if (!hasFP64Denormals && hasFP64) 2278 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2279 } 2280 2281 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2282 return llvm::makeArrayRef(BuiltinInfo, 2283 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2284 } 2285 2286 void getTargetDefines(const LangOptions &Opts, 2287 MacroBuilder &Builder) const override { 2288 if (getTriple().getArch() == llvm::Triple::amdgcn) 2289 Builder.defineMacro("__AMDGCN__"); 2290 else 2291 Builder.defineMacro("__R600__"); 2292 2293 if (hasFMAF) 2294 Builder.defineMacro("__HAS_FMAF__"); 2295 if (hasLDEXPF) 2296 Builder.defineMacro("__HAS_LDEXPF__"); 2297 if (hasFP64) 2298 Builder.defineMacro("__HAS_FP64__"); 2299 } 2300 2301 BuiltinVaListKind getBuiltinVaListKind() const override { 2302 return TargetInfo::CharPtrBuiltinVaList; 2303 } 2304 2305 static GPUKind parseR600Name(StringRef Name) { 2306 return llvm::StringSwitch<GPUKind>(Name) 2307 .Case("r600" , GK_R600) 2308 .Case("rv610", GK_R600) 2309 .Case("rv620", GK_R600) 2310 .Case("rv630", GK_R600) 2311 .Case("rv635", GK_R600) 2312 .Case("rs780", GK_R600) 2313 .Case("rs880", GK_R600) 2314 .Case("rv670", GK_R600_DOUBLE_OPS) 2315 .Case("rv710", GK_R700) 2316 .Case("rv730", GK_R700) 2317 .Case("rv740", GK_R700_DOUBLE_OPS) 2318 .Case("rv770", GK_R700_DOUBLE_OPS) 2319 .Case("palm", GK_EVERGREEN) 2320 .Case("cedar", GK_EVERGREEN) 2321 .Case("sumo", GK_EVERGREEN) 2322 .Case("sumo2", GK_EVERGREEN) 2323 .Case("redwood", GK_EVERGREEN) 2324 .Case("juniper", GK_EVERGREEN) 2325 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2326 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2327 .Case("barts", GK_NORTHERN_ISLANDS) 2328 .Case("turks", GK_NORTHERN_ISLANDS) 2329 .Case("caicos", GK_NORTHERN_ISLANDS) 2330 .Case("cayman", GK_CAYMAN) 2331 .Case("aruba", GK_CAYMAN) 2332 .Default(GK_NONE); 2333 } 2334 2335 static GPUKind parseAMDGCNName(StringRef Name) { 2336 return llvm::StringSwitch<GPUKind>(Name) 2337 .Case("tahiti", GK_GFX6) 2338 .Case("pitcairn", GK_GFX6) 2339 .Case("verde", GK_GFX6) 2340 .Case("oland", GK_GFX6) 2341 .Case("hainan", GK_GFX6) 2342 .Case("bonaire", GK_GFX7) 2343 .Case("kabini", GK_GFX7) 2344 .Case("kaveri", GK_GFX7) 2345 .Case("hawaii", GK_GFX7) 2346 .Case("mullins", GK_GFX7) 2347 .Case("gfx700", GK_GFX7) 2348 .Case("gfx701", GK_GFX7) 2349 .Case("gfx702", GK_GFX7) 2350 .Case("tonga", GK_GFX8) 2351 .Case("iceland", GK_GFX8) 2352 .Case("carrizo", GK_GFX8) 2353 .Case("fiji", GK_GFX8) 2354 .Case("stoney", GK_GFX8) 2355 .Case("polaris10", GK_GFX8) 2356 .Case("polaris11", GK_GFX8) 2357 .Case("gfx800", GK_GFX8) 2358 .Case("gfx801", GK_GFX8) 2359 .Case("gfx802", GK_GFX8) 2360 .Case("gfx803", GK_GFX8) 2361 .Case("gfx804", GK_GFX8) 2362 .Case("gfx810", GK_GFX8) 2363 .Case("gfx900", GK_GFX9) 2364 .Case("gfx901", GK_GFX9) 2365 .Default(GK_NONE); 2366 } 2367 2368 bool setCPU(const std::string &Name) override { 2369 if (getTriple().getArch() == llvm::Triple::amdgcn) 2370 GPU = parseAMDGCNName(Name); 2371 else 2372 GPU = parseR600Name(Name); 2373 2374 return GPU != GK_NONE; 2375 } 2376 2377 void setSupportedOpenCLOpts() override { 2378 auto &Opts = getSupportedOpenCLOpts(); 2379 Opts.support("cl_clang_storage_class_specifiers"); 2380 Opts.support("cl_khr_icd"); 2381 2382 if (hasFP64) 2383 Opts.support("cl_khr_fp64"); 2384 if (GPU >= GK_EVERGREEN) { 2385 Opts.support("cl_khr_byte_addressable_store"); 2386 Opts.support("cl_khr_global_int32_base_atomics"); 2387 Opts.support("cl_khr_global_int32_extended_atomics"); 2388 Opts.support("cl_khr_local_int32_base_atomics"); 2389 Opts.support("cl_khr_local_int32_extended_atomics"); 2390 } 2391 if (GPU >= GK_GFX6) { 2392 Opts.support("cl_khr_fp16"); 2393 Opts.support("cl_khr_int64_base_atomics"); 2394 Opts.support("cl_khr_int64_extended_atomics"); 2395 Opts.support("cl_khr_mipmap_image"); 2396 Opts.support("cl_khr_subgroups"); 2397 Opts.support("cl_khr_3d_image_writes"); 2398 Opts.support("cl_amd_media_ops"); 2399 Opts.support("cl_amd_media_ops2"); 2400 } 2401 } 2402 2403 LangAS::ID getOpenCLImageAddrSpace() const override { 2404 return LangAS::opencl_constant; 2405 } 2406 2407 llvm::Optional<unsigned> getConstantAddressSpace() const override { 2408 return LangAS::FirstTargetAddressSpace + AS.Constant; 2409 } 2410 2411 /// \returns Target specific vtbl ptr address space. 2412 unsigned getVtblPtrAddressSpace() const override { return AS.Constant; } 2413 2414 /// \returns If a target requires an address within a target specific address 2415 /// space \p AddressSpace to be converted in order to be used, then return the 2416 /// corresponding target specific DWARF address space. 2417 /// 2418 /// \returns Otherwise return None and no conversion will be emitted in the 2419 /// DWARF. 2420 Optional<unsigned> getDWARFAddressSpace( 2421 unsigned AddressSpace) const override { 2422 const unsigned DWARF_Private = 1; 2423 const unsigned DWARF_Local = 2; 2424 if (AddressSpace == AS.Private) { 2425 return DWARF_Private; 2426 } else if (AddressSpace == AS.Local) { 2427 return DWARF_Local; 2428 } else { 2429 return None; 2430 } 2431 } 2432 2433 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2434 switch (CC) { 2435 default: 2436 return CCCR_Warning; 2437 case CC_C: 2438 case CC_OpenCLKernel: 2439 return CCCR_OK; 2440 } 2441 } 2442 2443 // In amdgcn target the null pointer in global, constant, and generic 2444 // address space has value 0 but in private and local address space has 2445 // value ~0. 2446 uint64_t getNullPointerValue(unsigned AS) const override { 2447 return AS == LangAS::opencl_local ? ~0 : 0; 2448 } 2449 }; 2450 2451 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2452 #define BUILTIN(ID, TYPE, ATTRS) \ 2453 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2454 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2455 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2456 #include "clang/Basic/BuiltinsAMDGPU.def" 2457 }; 2458 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2459 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2460 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2461 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2462 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2463 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2464 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2465 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2466 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2467 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2468 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2469 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2470 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2471 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2472 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2473 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2474 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2475 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2476 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2477 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2478 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2479 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2480 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2481 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2482 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2483 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2484 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2485 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2486 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2487 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2488 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2489 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2490 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2491 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2492 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2493 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2494 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2495 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2496 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2497 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2498 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2499 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2500 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2501 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2502 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2503 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2504 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2505 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2506 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2507 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2508 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2509 }; 2510 2511 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2512 return llvm::makeArrayRef(GCCRegNames); 2513 } 2514 2515 bool AMDGPUTargetInfo::initFeatureMap( 2516 llvm::StringMap<bool> &Features, 2517 DiagnosticsEngine &Diags, StringRef CPU, 2518 const std::vector<std::string> &FeatureVec) const { 2519 2520 // XXX - What does the member GPU mean if device name string passed here? 2521 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2522 if (CPU.empty()) 2523 CPU = "tahiti"; 2524 2525 switch (parseAMDGCNName(CPU)) { 2526 case GK_GFX6: 2527 case GK_GFX7: 2528 break; 2529 2530 case GK_GFX9: 2531 Features["gfx9-insts"] = true; 2532 LLVM_FALLTHROUGH; 2533 case GK_GFX8: 2534 Features["s-memrealtime"] = true; 2535 Features["16-bit-insts"] = true; 2536 Features["dpp"] = true; 2537 break; 2538 2539 case GK_NONE: 2540 return false; 2541 default: 2542 llvm_unreachable("unhandled subtarget"); 2543 } 2544 } else { 2545 if (CPU.empty()) 2546 CPU = "r600"; 2547 2548 switch (parseR600Name(CPU)) { 2549 case GK_R600: 2550 case GK_R700: 2551 case GK_EVERGREEN: 2552 case GK_NORTHERN_ISLANDS: 2553 break; 2554 case GK_R600_DOUBLE_OPS: 2555 case GK_R700_DOUBLE_OPS: 2556 case GK_EVERGREEN_DOUBLE_OPS: 2557 case GK_CAYMAN: 2558 Features["fp64"] = true; 2559 break; 2560 case GK_NONE: 2561 return false; 2562 default: 2563 llvm_unreachable("unhandled subtarget"); 2564 } 2565 } 2566 2567 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2568 } 2569 2570 const Builtin::Info BuiltinInfoX86[] = { 2571 #define BUILTIN(ID, TYPE, ATTRS) \ 2572 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2573 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2574 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2575 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2576 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2577 #include "clang/Basic/BuiltinsX86.def" 2578 2579 #define BUILTIN(ID, TYPE, ATTRS) \ 2580 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2581 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2582 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2583 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2584 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2585 #include "clang/Basic/BuiltinsX86_64.def" 2586 }; 2587 2588 2589 static const char* const GCCRegNames[] = { 2590 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2591 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2592 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2593 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2594 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2595 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2596 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2597 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2598 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2599 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2600 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2601 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2602 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2603 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2604 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2605 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2606 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2607 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2608 }; 2609 2610 const TargetInfo::AddlRegName AddlRegNames[] = { 2611 { { "al", "ah", "eax", "rax" }, 0 }, 2612 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2613 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2614 { { "dl", "dh", "edx", "rdx" }, 1 }, 2615 { { "esi", "rsi" }, 4 }, 2616 { { "edi", "rdi" }, 5 }, 2617 { { "esp", "rsp" }, 7 }, 2618 { { "ebp", "rbp" }, 6 }, 2619 { { "r8d", "r8w", "r8b" }, 38 }, 2620 { { "r9d", "r9w", "r9b" }, 39 }, 2621 { { "r10d", "r10w", "r10b" }, 40 }, 2622 { { "r11d", "r11w", "r11b" }, 41 }, 2623 { { "r12d", "r12w", "r12b" }, 42 }, 2624 { { "r13d", "r13w", "r13b" }, 43 }, 2625 { { "r14d", "r14w", "r14b" }, 44 }, 2626 { { "r15d", "r15w", "r15b" }, 45 }, 2627 }; 2628 2629 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2630 // most of the implementation can be shared. 2631 class X86TargetInfo : public TargetInfo { 2632 enum X86SSEEnum { 2633 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2634 } SSELevel = NoSSE; 2635 enum MMX3DNowEnum { 2636 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2637 } MMX3DNowLevel = NoMMX3DNow; 2638 enum XOPEnum { 2639 NoXOP, 2640 SSE4A, 2641 FMA4, 2642 XOP 2643 } XOPLevel = NoXOP; 2644 2645 bool HasAES = false; 2646 bool HasPCLMUL = false; 2647 bool HasLZCNT = false; 2648 bool HasRDRND = false; 2649 bool HasFSGSBASE = false; 2650 bool HasBMI = false; 2651 bool HasBMI2 = false; 2652 bool HasPOPCNT = false; 2653 bool HasRTM = false; 2654 bool HasPRFCHW = false; 2655 bool HasRDSEED = false; 2656 bool HasADX = false; 2657 bool HasTBM = false; 2658 bool HasLWP = false; 2659 bool HasFMA = false; 2660 bool HasF16C = false; 2661 bool HasAVX512CD = false; 2662 bool HasAVX512VPOPCNTDQ = false; 2663 bool HasAVX512ER = false; 2664 bool HasAVX512PF = false; 2665 bool HasAVX512DQ = false; 2666 bool HasAVX512BW = false; 2667 bool HasAVX512VL = false; 2668 bool HasAVX512VBMI = false; 2669 bool HasAVX512IFMA = false; 2670 bool HasSHA = false; 2671 bool HasMPX = false; 2672 bool HasSGX = false; 2673 bool HasCX16 = false; 2674 bool HasFXSR = false; 2675 bool HasXSAVE = false; 2676 bool HasXSAVEOPT = false; 2677 bool HasXSAVEC = false; 2678 bool HasXSAVES = false; 2679 bool HasMWAITX = false; 2680 bool HasCLZERO = false; 2681 bool HasPKU = false; 2682 bool HasCLFLUSHOPT = false; 2683 bool HasCLWB = false; 2684 bool HasMOVBE = false; 2685 bool HasPREFETCHWT1 = false; 2686 2687 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2688 /// 2689 /// Each enumeration represents a particular CPU supported by Clang. These 2690 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2691 enum CPUKind { 2692 CK_Generic, 2693 2694 /// \name i386 2695 /// i386-generation processors. 2696 //@{ 2697 CK_i386, 2698 //@} 2699 2700 /// \name i486 2701 /// i486-generation processors. 2702 //@{ 2703 CK_i486, 2704 CK_WinChipC6, 2705 CK_WinChip2, 2706 CK_C3, 2707 //@} 2708 2709 /// \name i586 2710 /// i586-generation processors, P5 microarchitecture based. 2711 //@{ 2712 CK_i586, 2713 CK_Pentium, 2714 CK_PentiumMMX, 2715 //@} 2716 2717 /// \name i686 2718 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2719 //@{ 2720 CK_i686, 2721 CK_PentiumPro, 2722 CK_Pentium2, 2723 CK_Pentium3, 2724 CK_Pentium3M, 2725 CK_PentiumM, 2726 CK_C3_2, 2727 2728 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2729 /// Clang however has some logic to support this. 2730 // FIXME: Warn, deprecate, and potentially remove this. 2731 CK_Yonah, 2732 //@} 2733 2734 /// \name Netburst 2735 /// Netburst microarchitecture based processors. 2736 //@{ 2737 CK_Pentium4, 2738 CK_Pentium4M, 2739 CK_Prescott, 2740 CK_Nocona, 2741 //@} 2742 2743 /// \name Core 2744 /// Core microarchitecture based processors. 2745 //@{ 2746 CK_Core2, 2747 2748 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2749 /// codename which GCC no longer accepts as an option to -march, but Clang 2750 /// has some logic for recognizing it. 2751 // FIXME: Warn, deprecate, and potentially remove this. 2752 CK_Penryn, 2753 //@} 2754 2755 /// \name Atom 2756 /// Atom processors 2757 //@{ 2758 CK_Bonnell, 2759 CK_Silvermont, 2760 CK_Goldmont, 2761 //@} 2762 2763 /// \name Nehalem 2764 /// Nehalem microarchitecture based processors. 2765 CK_Nehalem, 2766 2767 /// \name Westmere 2768 /// Westmere microarchitecture based processors. 2769 CK_Westmere, 2770 2771 /// \name Sandy Bridge 2772 /// Sandy Bridge microarchitecture based processors. 2773 CK_SandyBridge, 2774 2775 /// \name Ivy Bridge 2776 /// Ivy Bridge microarchitecture based processors. 2777 CK_IvyBridge, 2778 2779 /// \name Haswell 2780 /// Haswell microarchitecture based processors. 2781 CK_Haswell, 2782 2783 /// \name Broadwell 2784 /// Broadwell microarchitecture based processors. 2785 CK_Broadwell, 2786 2787 /// \name Skylake Client 2788 /// Skylake client microarchitecture based processors. 2789 CK_SkylakeClient, 2790 2791 /// \name Skylake Server 2792 /// Skylake server microarchitecture based processors. 2793 CK_SkylakeServer, 2794 2795 /// \name Cannonlake Client 2796 /// Cannonlake client microarchitecture based processors. 2797 CK_Cannonlake, 2798 2799 /// \name Knights Landing 2800 /// Knights Landing processor. 2801 CK_KNL, 2802 2803 /// \name Lakemont 2804 /// Lakemont microarchitecture based processors. 2805 CK_Lakemont, 2806 2807 /// \name K6 2808 /// K6 architecture processors. 2809 //@{ 2810 CK_K6, 2811 CK_K6_2, 2812 CK_K6_3, 2813 //@} 2814 2815 /// \name K7 2816 /// K7 architecture processors. 2817 //@{ 2818 CK_Athlon, 2819 CK_AthlonThunderbird, 2820 CK_Athlon4, 2821 CK_AthlonXP, 2822 CK_AthlonMP, 2823 //@} 2824 2825 /// \name K8 2826 /// K8 architecture processors. 2827 //@{ 2828 CK_Athlon64, 2829 CK_Athlon64SSE3, 2830 CK_AthlonFX, 2831 CK_K8, 2832 CK_K8SSE3, 2833 CK_Opteron, 2834 CK_OpteronSSE3, 2835 CK_AMDFAM10, 2836 //@} 2837 2838 /// \name Bobcat 2839 /// Bobcat architecture processors. 2840 //@{ 2841 CK_BTVER1, 2842 CK_BTVER2, 2843 //@} 2844 2845 /// \name Bulldozer 2846 /// Bulldozer architecture processors. 2847 //@{ 2848 CK_BDVER1, 2849 CK_BDVER2, 2850 CK_BDVER3, 2851 CK_BDVER4, 2852 //@} 2853 2854 /// \name zen 2855 /// Zen architecture processors. 2856 //@{ 2857 CK_ZNVER1, 2858 //@} 2859 2860 /// This specification is deprecated and will be removed in the future. 2861 /// Users should prefer \see CK_K8. 2862 // FIXME: Warn on this when the CPU is set to it. 2863 //@{ 2864 CK_x86_64, 2865 //@} 2866 2867 /// \name Geode 2868 /// Geode processors. 2869 //@{ 2870 CK_Geode 2871 //@} 2872 } CPU = CK_Generic; 2873 2874 CPUKind getCPUKind(StringRef CPU) const { 2875 return llvm::StringSwitch<CPUKind>(CPU) 2876 .Case("i386", CK_i386) 2877 .Case("i486", CK_i486) 2878 .Case("winchip-c6", CK_WinChipC6) 2879 .Case("winchip2", CK_WinChip2) 2880 .Case("c3", CK_C3) 2881 .Case("i586", CK_i586) 2882 .Case("pentium", CK_Pentium) 2883 .Case("pentium-mmx", CK_PentiumMMX) 2884 .Case("i686", CK_i686) 2885 .Case("pentiumpro", CK_PentiumPro) 2886 .Case("pentium2", CK_Pentium2) 2887 .Case("pentium3", CK_Pentium3) 2888 .Case("pentium3m", CK_Pentium3M) 2889 .Case("pentium-m", CK_PentiumM) 2890 .Case("c3-2", CK_C3_2) 2891 .Case("yonah", CK_Yonah) 2892 .Case("pentium4", CK_Pentium4) 2893 .Case("pentium4m", CK_Pentium4M) 2894 .Case("prescott", CK_Prescott) 2895 .Case("nocona", CK_Nocona) 2896 .Case("core2", CK_Core2) 2897 .Case("penryn", CK_Penryn) 2898 .Case("bonnell", CK_Bonnell) 2899 .Case("atom", CK_Bonnell) // Legacy name. 2900 .Case("silvermont", CK_Silvermont) 2901 .Case("slm", CK_Silvermont) // Legacy name. 2902 .Case("goldmont", CK_Goldmont) 2903 .Case("nehalem", CK_Nehalem) 2904 .Case("corei7", CK_Nehalem) // Legacy name. 2905 .Case("westmere", CK_Westmere) 2906 .Case("sandybridge", CK_SandyBridge) 2907 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2908 .Case("ivybridge", CK_IvyBridge) 2909 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2910 .Case("haswell", CK_Haswell) 2911 .Case("core-avx2", CK_Haswell) // Legacy name. 2912 .Case("broadwell", CK_Broadwell) 2913 .Case("skylake", CK_SkylakeClient) 2914 .Case("skylake-avx512", CK_SkylakeServer) 2915 .Case("skx", CK_SkylakeServer) // Legacy name. 2916 .Case("cannonlake", CK_Cannonlake) 2917 .Case("knl", CK_KNL) 2918 .Case("lakemont", CK_Lakemont) 2919 .Case("k6", CK_K6) 2920 .Case("k6-2", CK_K6_2) 2921 .Case("k6-3", CK_K6_3) 2922 .Case("athlon", CK_Athlon) 2923 .Case("athlon-tbird", CK_AthlonThunderbird) 2924 .Case("athlon-4", CK_Athlon4) 2925 .Case("athlon-xp", CK_AthlonXP) 2926 .Case("athlon-mp", CK_AthlonMP) 2927 .Case("athlon64", CK_Athlon64) 2928 .Case("athlon64-sse3", CK_Athlon64SSE3) 2929 .Case("athlon-fx", CK_AthlonFX) 2930 .Case("k8", CK_K8) 2931 .Case("k8-sse3", CK_K8SSE3) 2932 .Case("opteron", CK_Opteron) 2933 .Case("opteron-sse3", CK_OpteronSSE3) 2934 .Case("barcelona", CK_AMDFAM10) 2935 .Case("amdfam10", CK_AMDFAM10) 2936 .Case("btver1", CK_BTVER1) 2937 .Case("btver2", CK_BTVER2) 2938 .Case("bdver1", CK_BDVER1) 2939 .Case("bdver2", CK_BDVER2) 2940 .Case("bdver3", CK_BDVER3) 2941 .Case("bdver4", CK_BDVER4) 2942 .Case("znver1", CK_ZNVER1) 2943 .Case("x86-64", CK_x86_64) 2944 .Case("geode", CK_Geode) 2945 .Default(CK_Generic); 2946 } 2947 2948 enum FPMathKind { 2949 FP_Default, 2950 FP_SSE, 2951 FP_387 2952 } FPMath = FP_Default; 2953 2954 public: 2955 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2956 : TargetInfo(Triple) { 2957 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2958 } 2959 unsigned getFloatEvalMethod() const override { 2960 // X87 evaluates with 80 bits "long double" precision. 2961 return SSELevel == NoSSE ? 2 : 0; 2962 } 2963 ArrayRef<const char *> getGCCRegNames() const override { 2964 return llvm::makeArrayRef(GCCRegNames); 2965 } 2966 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2967 return None; 2968 } 2969 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2970 return llvm::makeArrayRef(AddlRegNames); 2971 } 2972 bool validateCpuSupports(StringRef Name) const override; 2973 bool validateAsmConstraint(const char *&Name, 2974 TargetInfo::ConstraintInfo &info) const override; 2975 2976 bool validateGlobalRegisterVariable(StringRef RegName, 2977 unsigned RegSize, 2978 bool &HasSizeMismatch) const override { 2979 // esp and ebp are the only 32-bit registers the x86 backend can currently 2980 // handle. 2981 if (RegName.equals("esp") || RegName.equals("ebp")) { 2982 // Check that the register size is 32-bit. 2983 HasSizeMismatch = RegSize != 32; 2984 return true; 2985 } 2986 2987 return false; 2988 } 2989 2990 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2991 2992 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2993 2994 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2995 2996 std::string convertConstraint(const char *&Constraint) const override; 2997 const char *getClobbers() const override { 2998 return "~{dirflag},~{fpsr},~{flags}"; 2999 } 3000 3001 StringRef getConstraintRegister(const StringRef &Constraint, 3002 const StringRef &Expression) const override { 3003 StringRef::iterator I, E; 3004 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 3005 if (isalpha(*I)) 3006 break; 3007 } 3008 if (I == E) 3009 return ""; 3010 switch (*I) { 3011 // For the register constraints, return the matching register name 3012 case 'a': 3013 return "ax"; 3014 case 'b': 3015 return "bx"; 3016 case 'c': 3017 return "cx"; 3018 case 'd': 3019 return "dx"; 3020 case 'S': 3021 return "si"; 3022 case 'D': 3023 return "di"; 3024 // In case the constraint is 'r' we need to return Expression 3025 case 'r': 3026 return Expression; 3027 default: 3028 // Default value if there is no constraint for the register 3029 return ""; 3030 } 3031 return ""; 3032 } 3033 3034 void getTargetDefines(const LangOptions &Opts, 3035 MacroBuilder &Builder) const override; 3036 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 3037 bool Enabled); 3038 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 3039 bool Enabled); 3040 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3041 bool Enabled); 3042 void setFeatureEnabled(llvm::StringMap<bool> &Features, 3043 StringRef Name, bool Enabled) const override { 3044 setFeatureEnabledImpl(Features, Name, Enabled); 3045 } 3046 // This exists purely to cut down on the number of virtual calls in 3047 // initFeatureMap which calls this repeatedly. 3048 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3049 StringRef Name, bool Enabled); 3050 bool 3051 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 3052 StringRef CPU, 3053 const std::vector<std::string> &FeaturesVec) const override; 3054 bool hasFeature(StringRef Feature) const override; 3055 bool handleTargetFeatures(std::vector<std::string> &Features, 3056 DiagnosticsEngine &Diags) override; 3057 StringRef getABI() const override { 3058 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 3059 return "avx512"; 3060 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 3061 return "avx"; 3062 if (getTriple().getArch() == llvm::Triple::x86 && 3063 MMX3DNowLevel == NoMMX3DNow) 3064 return "no-mmx"; 3065 return ""; 3066 } 3067 bool setCPU(const std::string &Name) override { 3068 CPU = getCPUKind(Name); 3069 3070 // Perform any per-CPU checks necessary to determine if this CPU is 3071 // acceptable. 3072 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 3073 // invalid without explaining *why*. 3074 switch (CPU) { 3075 case CK_Generic: 3076 // No processor selected! 3077 return false; 3078 3079 case CK_i386: 3080 case CK_i486: 3081 case CK_WinChipC6: 3082 case CK_WinChip2: 3083 case CK_C3: 3084 case CK_i586: 3085 case CK_Pentium: 3086 case CK_PentiumMMX: 3087 case CK_i686: 3088 case CK_PentiumPro: 3089 case CK_Pentium2: 3090 case CK_Pentium3: 3091 case CK_Pentium3M: 3092 case CK_PentiumM: 3093 case CK_Yonah: 3094 case CK_C3_2: 3095 case CK_Pentium4: 3096 case CK_Pentium4M: 3097 case CK_Lakemont: 3098 case CK_Prescott: 3099 case CK_K6: 3100 case CK_K6_2: 3101 case CK_K6_3: 3102 case CK_Athlon: 3103 case CK_AthlonThunderbird: 3104 case CK_Athlon4: 3105 case CK_AthlonXP: 3106 case CK_AthlonMP: 3107 case CK_Geode: 3108 // Only accept certain architectures when compiling in 32-bit mode. 3109 if (getTriple().getArch() != llvm::Triple::x86) 3110 return false; 3111 3112 // Fallthrough 3113 case CK_Nocona: 3114 case CK_Core2: 3115 case CK_Penryn: 3116 case CK_Bonnell: 3117 case CK_Silvermont: 3118 case CK_Goldmont: 3119 case CK_Nehalem: 3120 case CK_Westmere: 3121 case CK_SandyBridge: 3122 case CK_IvyBridge: 3123 case CK_Haswell: 3124 case CK_Broadwell: 3125 case CK_SkylakeClient: 3126 case CK_SkylakeServer: 3127 case CK_Cannonlake: 3128 case CK_KNL: 3129 case CK_Athlon64: 3130 case CK_Athlon64SSE3: 3131 case CK_AthlonFX: 3132 case CK_K8: 3133 case CK_K8SSE3: 3134 case CK_Opteron: 3135 case CK_OpteronSSE3: 3136 case CK_AMDFAM10: 3137 case CK_BTVER1: 3138 case CK_BTVER2: 3139 case CK_BDVER1: 3140 case CK_BDVER2: 3141 case CK_BDVER3: 3142 case CK_BDVER4: 3143 case CK_ZNVER1: 3144 case CK_x86_64: 3145 return true; 3146 } 3147 llvm_unreachable("Unhandled CPU kind"); 3148 } 3149 3150 bool setFPMath(StringRef Name) override; 3151 3152 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3153 // Most of the non-ARM calling conventions are i386 conventions. 3154 switch (CC) { 3155 case CC_X86ThisCall: 3156 case CC_X86FastCall: 3157 case CC_X86StdCall: 3158 case CC_X86VectorCall: 3159 case CC_X86RegCall: 3160 case CC_C: 3161 case CC_Swift: 3162 case CC_X86Pascal: 3163 case CC_IntelOclBicc: 3164 case CC_OpenCLKernel: 3165 return CCCR_OK; 3166 default: 3167 return CCCR_Warning; 3168 } 3169 } 3170 3171 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3172 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 3173 } 3174 3175 bool hasSjLjLowering() const override { 3176 return true; 3177 } 3178 3179 void setSupportedOpenCLOpts() override { 3180 getSupportedOpenCLOpts().supportAll(); 3181 } 3182 }; 3183 3184 bool X86TargetInfo::setFPMath(StringRef Name) { 3185 if (Name == "387") { 3186 FPMath = FP_387; 3187 return true; 3188 } 3189 if (Name == "sse") { 3190 FPMath = FP_SSE; 3191 return true; 3192 } 3193 return false; 3194 } 3195 3196 bool X86TargetInfo::initFeatureMap( 3197 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3198 const std::vector<std::string> &FeaturesVec) const { 3199 // FIXME: This *really* should not be here. 3200 // X86_64 always has SSE2. 3201 if (getTriple().getArch() == llvm::Triple::x86_64) 3202 setFeatureEnabledImpl(Features, "sse2", true); 3203 3204 const CPUKind Kind = getCPUKind(CPU); 3205 3206 // Enable X87 for all X86 processors but Lakemont. 3207 if (Kind != CK_Lakemont) 3208 setFeatureEnabledImpl(Features, "x87", true); 3209 3210 switch (Kind) { 3211 case CK_Generic: 3212 case CK_i386: 3213 case CK_i486: 3214 case CK_i586: 3215 case CK_Pentium: 3216 case CK_i686: 3217 case CK_PentiumPro: 3218 case CK_Lakemont: 3219 break; 3220 case CK_PentiumMMX: 3221 case CK_Pentium2: 3222 case CK_K6: 3223 case CK_WinChipC6: 3224 setFeatureEnabledImpl(Features, "mmx", true); 3225 break; 3226 case CK_Pentium3: 3227 case CK_Pentium3M: 3228 case CK_C3_2: 3229 setFeatureEnabledImpl(Features, "sse", true); 3230 setFeatureEnabledImpl(Features, "fxsr", true); 3231 break; 3232 case CK_PentiumM: 3233 case CK_Pentium4: 3234 case CK_Pentium4M: 3235 case CK_x86_64: 3236 setFeatureEnabledImpl(Features, "sse2", true); 3237 setFeatureEnabledImpl(Features, "fxsr", true); 3238 break; 3239 case CK_Yonah: 3240 case CK_Prescott: 3241 case CK_Nocona: 3242 setFeatureEnabledImpl(Features, "sse3", true); 3243 setFeatureEnabledImpl(Features, "fxsr", true); 3244 setFeatureEnabledImpl(Features, "cx16", true); 3245 break; 3246 case CK_Core2: 3247 setFeatureEnabledImpl(Features, "ssse3", true); 3248 setFeatureEnabledImpl(Features, "fxsr", true); 3249 setFeatureEnabledImpl(Features, "cx16", true); 3250 break; 3251 case CK_Penryn: 3252 setFeatureEnabledImpl(Features, "sse4.1", true); 3253 setFeatureEnabledImpl(Features, "fxsr", true); 3254 setFeatureEnabledImpl(Features, "cx16", true); 3255 break; 3256 case CK_Cannonlake: 3257 setFeatureEnabledImpl(Features, "avx512ifma", true); 3258 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3259 setFeatureEnabledImpl(Features, "sha", true); 3260 LLVM_FALLTHROUGH; 3261 case CK_SkylakeServer: 3262 setFeatureEnabledImpl(Features, "avx512f", true); 3263 setFeatureEnabledImpl(Features, "avx512cd", true); 3264 setFeatureEnabledImpl(Features, "avx512dq", true); 3265 setFeatureEnabledImpl(Features, "avx512bw", true); 3266 setFeatureEnabledImpl(Features, "avx512vl", true); 3267 setFeatureEnabledImpl(Features, "pku", true); 3268 setFeatureEnabledImpl(Features, "clwb", true); 3269 LLVM_FALLTHROUGH; 3270 case CK_SkylakeClient: 3271 setFeatureEnabledImpl(Features, "xsavec", true); 3272 setFeatureEnabledImpl(Features, "xsaves", true); 3273 setFeatureEnabledImpl(Features, "mpx", true); 3274 setFeatureEnabledImpl(Features, "sgx", true); 3275 setFeatureEnabledImpl(Features, "clflushopt", true); 3276 setFeatureEnabledImpl(Features, "rtm", true); 3277 LLVM_FALLTHROUGH; 3278 case CK_Broadwell: 3279 setFeatureEnabledImpl(Features, "rdseed", true); 3280 setFeatureEnabledImpl(Features, "adx", true); 3281 LLVM_FALLTHROUGH; 3282 case CK_Haswell: 3283 setFeatureEnabledImpl(Features, "avx2", true); 3284 setFeatureEnabledImpl(Features, "lzcnt", true); 3285 setFeatureEnabledImpl(Features, "bmi", true); 3286 setFeatureEnabledImpl(Features, "bmi2", true); 3287 setFeatureEnabledImpl(Features, "fma", true); 3288 setFeatureEnabledImpl(Features, "movbe", true); 3289 LLVM_FALLTHROUGH; 3290 case CK_IvyBridge: 3291 setFeatureEnabledImpl(Features, "rdrnd", true); 3292 setFeatureEnabledImpl(Features, "f16c", true); 3293 setFeatureEnabledImpl(Features, "fsgsbase", true); 3294 LLVM_FALLTHROUGH; 3295 case CK_SandyBridge: 3296 setFeatureEnabledImpl(Features, "avx", true); 3297 setFeatureEnabledImpl(Features, "xsave", true); 3298 setFeatureEnabledImpl(Features, "xsaveopt", true); 3299 LLVM_FALLTHROUGH; 3300 case CK_Westmere: 3301 setFeatureEnabledImpl(Features, "aes", true); 3302 setFeatureEnabledImpl(Features, "pclmul", true); 3303 LLVM_FALLTHROUGH; 3304 case CK_Nehalem: 3305 setFeatureEnabledImpl(Features, "sse4.2", true); 3306 setFeatureEnabledImpl(Features, "fxsr", true); 3307 setFeatureEnabledImpl(Features, "cx16", true); 3308 break; 3309 case CK_Goldmont: 3310 setFeatureEnabledImpl(Features, "sha", true); 3311 setFeatureEnabledImpl(Features, "rdrnd", true); 3312 setFeatureEnabledImpl(Features, "rdseed", true); 3313 setFeatureEnabledImpl(Features, "xsave", true); 3314 setFeatureEnabledImpl(Features, "xsaveopt", true); 3315 setFeatureEnabledImpl(Features, "xsavec", true); 3316 setFeatureEnabledImpl(Features, "xsaves", true); 3317 setFeatureEnabledImpl(Features, "clflushopt", true); 3318 setFeatureEnabledImpl(Features, "mpx", true); 3319 LLVM_FALLTHROUGH; 3320 case CK_Silvermont: 3321 setFeatureEnabledImpl(Features, "aes", true); 3322 setFeatureEnabledImpl(Features, "pclmul", true); 3323 setFeatureEnabledImpl(Features, "sse4.2", true); 3324 LLVM_FALLTHROUGH; 3325 case CK_Bonnell: 3326 setFeatureEnabledImpl(Features, "movbe", true); 3327 setFeatureEnabledImpl(Features, "ssse3", true); 3328 setFeatureEnabledImpl(Features, "fxsr", true); 3329 setFeatureEnabledImpl(Features, "cx16", true); 3330 break; 3331 case CK_KNL: 3332 setFeatureEnabledImpl(Features, "avx512f", true); 3333 setFeatureEnabledImpl(Features, "avx512cd", true); 3334 setFeatureEnabledImpl(Features, "avx512er", true); 3335 setFeatureEnabledImpl(Features, "avx512pf", true); 3336 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3337 setFeatureEnabledImpl(Features, "fxsr", true); 3338 setFeatureEnabledImpl(Features, "rdseed", true); 3339 setFeatureEnabledImpl(Features, "adx", true); 3340 setFeatureEnabledImpl(Features, "lzcnt", true); 3341 setFeatureEnabledImpl(Features, "bmi", true); 3342 setFeatureEnabledImpl(Features, "bmi2", true); 3343 setFeatureEnabledImpl(Features, "rtm", true); 3344 setFeatureEnabledImpl(Features, "fma", true); 3345 setFeatureEnabledImpl(Features, "rdrnd", true); 3346 setFeatureEnabledImpl(Features, "f16c", true); 3347 setFeatureEnabledImpl(Features, "fsgsbase", true); 3348 setFeatureEnabledImpl(Features, "aes", true); 3349 setFeatureEnabledImpl(Features, "pclmul", true); 3350 setFeatureEnabledImpl(Features, "cx16", true); 3351 setFeatureEnabledImpl(Features, "xsaveopt", true); 3352 setFeatureEnabledImpl(Features, "xsave", true); 3353 setFeatureEnabledImpl(Features, "movbe", true); 3354 break; 3355 case CK_K6_2: 3356 case CK_K6_3: 3357 case CK_WinChip2: 3358 case CK_C3: 3359 setFeatureEnabledImpl(Features, "3dnow", true); 3360 break; 3361 case CK_Athlon: 3362 case CK_AthlonThunderbird: 3363 case CK_Geode: 3364 setFeatureEnabledImpl(Features, "3dnowa", true); 3365 break; 3366 case CK_Athlon4: 3367 case CK_AthlonXP: 3368 case CK_AthlonMP: 3369 setFeatureEnabledImpl(Features, "sse", true); 3370 setFeatureEnabledImpl(Features, "3dnowa", true); 3371 setFeatureEnabledImpl(Features, "fxsr", true); 3372 break; 3373 case CK_K8: 3374 case CK_Opteron: 3375 case CK_Athlon64: 3376 case CK_AthlonFX: 3377 setFeatureEnabledImpl(Features, "sse2", true); 3378 setFeatureEnabledImpl(Features, "3dnowa", true); 3379 setFeatureEnabledImpl(Features, "fxsr", true); 3380 break; 3381 case CK_AMDFAM10: 3382 setFeatureEnabledImpl(Features, "sse4a", true); 3383 setFeatureEnabledImpl(Features, "lzcnt", true); 3384 setFeatureEnabledImpl(Features, "popcnt", true); 3385 LLVM_FALLTHROUGH; 3386 case CK_K8SSE3: 3387 case CK_OpteronSSE3: 3388 case CK_Athlon64SSE3: 3389 setFeatureEnabledImpl(Features, "sse3", true); 3390 setFeatureEnabledImpl(Features, "3dnowa", true); 3391 setFeatureEnabledImpl(Features, "fxsr", true); 3392 break; 3393 case CK_BTVER2: 3394 setFeatureEnabledImpl(Features, "avx", true); 3395 setFeatureEnabledImpl(Features, "aes", true); 3396 setFeatureEnabledImpl(Features, "pclmul", true); 3397 setFeatureEnabledImpl(Features, "bmi", true); 3398 setFeatureEnabledImpl(Features, "f16c", true); 3399 setFeatureEnabledImpl(Features, "xsaveopt", true); 3400 LLVM_FALLTHROUGH; 3401 case CK_BTVER1: 3402 setFeatureEnabledImpl(Features, "ssse3", true); 3403 setFeatureEnabledImpl(Features, "sse4a", true); 3404 setFeatureEnabledImpl(Features, "lzcnt", true); 3405 setFeatureEnabledImpl(Features, "popcnt", true); 3406 setFeatureEnabledImpl(Features, "prfchw", true); 3407 setFeatureEnabledImpl(Features, "cx16", true); 3408 setFeatureEnabledImpl(Features, "fxsr", true); 3409 break; 3410 case CK_ZNVER1: 3411 setFeatureEnabledImpl(Features, "adx", true); 3412 setFeatureEnabledImpl(Features, "aes", true); 3413 setFeatureEnabledImpl(Features, "avx2", true); 3414 setFeatureEnabledImpl(Features, "bmi", true); 3415 setFeatureEnabledImpl(Features, "bmi2", true); 3416 setFeatureEnabledImpl(Features, "clflushopt", true); 3417 setFeatureEnabledImpl(Features, "clzero", true); 3418 setFeatureEnabledImpl(Features, "cx16", true); 3419 setFeatureEnabledImpl(Features, "f16c", true); 3420 setFeatureEnabledImpl(Features, "fma", true); 3421 setFeatureEnabledImpl(Features, "fsgsbase", true); 3422 setFeatureEnabledImpl(Features, "fxsr", true); 3423 setFeatureEnabledImpl(Features, "lzcnt", true); 3424 setFeatureEnabledImpl(Features, "mwaitx", true); 3425 setFeatureEnabledImpl(Features, "movbe", true); 3426 setFeatureEnabledImpl(Features, "pclmul", true); 3427 setFeatureEnabledImpl(Features, "popcnt", true); 3428 setFeatureEnabledImpl(Features, "prfchw", true); 3429 setFeatureEnabledImpl(Features, "rdrnd", true); 3430 setFeatureEnabledImpl(Features, "rdseed", true); 3431 setFeatureEnabledImpl(Features, "sha", true); 3432 setFeatureEnabledImpl(Features, "sse4a", true); 3433 setFeatureEnabledImpl(Features, "xsave", true); 3434 setFeatureEnabledImpl(Features, "xsavec", true); 3435 setFeatureEnabledImpl(Features, "xsaveopt", true); 3436 setFeatureEnabledImpl(Features, "xsaves", true); 3437 break; 3438 case CK_BDVER4: 3439 setFeatureEnabledImpl(Features, "avx2", true); 3440 setFeatureEnabledImpl(Features, "bmi2", true); 3441 setFeatureEnabledImpl(Features, "mwaitx", true); 3442 LLVM_FALLTHROUGH; 3443 case CK_BDVER3: 3444 setFeatureEnabledImpl(Features, "fsgsbase", true); 3445 setFeatureEnabledImpl(Features, "xsaveopt", true); 3446 LLVM_FALLTHROUGH; 3447 case CK_BDVER2: 3448 setFeatureEnabledImpl(Features, "bmi", true); 3449 setFeatureEnabledImpl(Features, "fma", true); 3450 setFeatureEnabledImpl(Features, "f16c", true); 3451 setFeatureEnabledImpl(Features, "tbm", true); 3452 LLVM_FALLTHROUGH; 3453 case CK_BDVER1: 3454 // xop implies avx, sse4a and fma4. 3455 setFeatureEnabledImpl(Features, "xop", true); 3456 setFeatureEnabledImpl(Features, "lwp", true); 3457 setFeatureEnabledImpl(Features, "lzcnt", true); 3458 setFeatureEnabledImpl(Features, "aes", true); 3459 setFeatureEnabledImpl(Features, "pclmul", true); 3460 setFeatureEnabledImpl(Features, "prfchw", true); 3461 setFeatureEnabledImpl(Features, "cx16", true); 3462 setFeatureEnabledImpl(Features, "fxsr", true); 3463 setFeatureEnabledImpl(Features, "xsave", true); 3464 break; 3465 } 3466 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3467 return false; 3468 3469 // Can't do this earlier because we need to be able to explicitly enable 3470 // or disable these features and the things that they depend upon. 3471 3472 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3473 auto I = Features.find("sse4.2"); 3474 if (I != Features.end() && I->getValue() && 3475 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3476 FeaturesVec.end()) 3477 Features["popcnt"] = true; 3478 3479 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3480 I = Features.find("3dnow"); 3481 if (I != Features.end() && I->getValue() && 3482 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3483 FeaturesVec.end()) 3484 Features["prfchw"] = true; 3485 3486 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3487 // then enable MMX. 3488 I = Features.find("sse"); 3489 if (I != Features.end() && I->getValue() && 3490 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3491 FeaturesVec.end()) 3492 Features["mmx"] = true; 3493 3494 return true; 3495 } 3496 3497 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3498 X86SSEEnum Level, bool Enabled) { 3499 if (Enabled) { 3500 switch (Level) { 3501 case AVX512F: 3502 Features["avx512f"] = true; 3503 LLVM_FALLTHROUGH; 3504 case AVX2: 3505 Features["avx2"] = true; 3506 LLVM_FALLTHROUGH; 3507 case AVX: 3508 Features["avx"] = true; 3509 Features["xsave"] = true; 3510 LLVM_FALLTHROUGH; 3511 case SSE42: 3512 Features["sse4.2"] = true; 3513 LLVM_FALLTHROUGH; 3514 case SSE41: 3515 Features["sse4.1"] = true; 3516 LLVM_FALLTHROUGH; 3517 case SSSE3: 3518 Features["ssse3"] = true; 3519 LLVM_FALLTHROUGH; 3520 case SSE3: 3521 Features["sse3"] = true; 3522 LLVM_FALLTHROUGH; 3523 case SSE2: 3524 Features["sse2"] = true; 3525 LLVM_FALLTHROUGH; 3526 case SSE1: 3527 Features["sse"] = true; 3528 LLVM_FALLTHROUGH; 3529 case NoSSE: 3530 break; 3531 } 3532 return; 3533 } 3534 3535 switch (Level) { 3536 case NoSSE: 3537 case SSE1: 3538 Features["sse"] = false; 3539 LLVM_FALLTHROUGH; 3540 case SSE2: 3541 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3542 Features["sha"] = false; 3543 LLVM_FALLTHROUGH; 3544 case SSE3: 3545 Features["sse3"] = false; 3546 setXOPLevel(Features, NoXOP, false); 3547 LLVM_FALLTHROUGH; 3548 case SSSE3: 3549 Features["ssse3"] = false; 3550 LLVM_FALLTHROUGH; 3551 case SSE41: 3552 Features["sse4.1"] = false; 3553 LLVM_FALLTHROUGH; 3554 case SSE42: 3555 Features["sse4.2"] = false; 3556 LLVM_FALLTHROUGH; 3557 case AVX: 3558 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3559 Features["xsaveopt"] = false; 3560 setXOPLevel(Features, FMA4, false); 3561 LLVM_FALLTHROUGH; 3562 case AVX2: 3563 Features["avx2"] = false; 3564 LLVM_FALLTHROUGH; 3565 case AVX512F: 3566 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3567 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3568 Features["avx512vl"] = Features["avx512vbmi"] = 3569 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 3570 break; 3571 } 3572 } 3573 3574 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3575 MMX3DNowEnum Level, bool Enabled) { 3576 if (Enabled) { 3577 switch (Level) { 3578 case AMD3DNowAthlon: 3579 Features["3dnowa"] = true; 3580 LLVM_FALLTHROUGH; 3581 case AMD3DNow: 3582 Features["3dnow"] = true; 3583 LLVM_FALLTHROUGH; 3584 case MMX: 3585 Features["mmx"] = true; 3586 LLVM_FALLTHROUGH; 3587 case NoMMX3DNow: 3588 break; 3589 } 3590 return; 3591 } 3592 3593 switch (Level) { 3594 case NoMMX3DNow: 3595 case MMX: 3596 Features["mmx"] = false; 3597 LLVM_FALLTHROUGH; 3598 case AMD3DNow: 3599 Features["3dnow"] = false; 3600 LLVM_FALLTHROUGH; 3601 case AMD3DNowAthlon: 3602 Features["3dnowa"] = false; 3603 break; 3604 } 3605 } 3606 3607 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3608 bool Enabled) { 3609 if (Enabled) { 3610 switch (Level) { 3611 case XOP: 3612 Features["xop"] = true; 3613 LLVM_FALLTHROUGH; 3614 case FMA4: 3615 Features["fma4"] = true; 3616 setSSELevel(Features, AVX, true); 3617 LLVM_FALLTHROUGH; 3618 case SSE4A: 3619 Features["sse4a"] = true; 3620 setSSELevel(Features, SSE3, true); 3621 LLVM_FALLTHROUGH; 3622 case NoXOP: 3623 break; 3624 } 3625 return; 3626 } 3627 3628 switch (Level) { 3629 case NoXOP: 3630 case SSE4A: 3631 Features["sse4a"] = false; 3632 LLVM_FALLTHROUGH; 3633 case FMA4: 3634 Features["fma4"] = false; 3635 LLVM_FALLTHROUGH; 3636 case XOP: 3637 Features["xop"] = false; 3638 break; 3639 } 3640 } 3641 3642 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3643 StringRef Name, bool Enabled) { 3644 // This is a bit of a hack to deal with the sse4 target feature when used 3645 // as part of the target attribute. We handle sse4 correctly everywhere 3646 // else. See below for more information on how we handle the sse4 options. 3647 if (Name != "sse4") 3648 Features[Name] = Enabled; 3649 3650 if (Name == "mmx") { 3651 setMMXLevel(Features, MMX, Enabled); 3652 } else if (Name == "sse") { 3653 setSSELevel(Features, SSE1, Enabled); 3654 } else if (Name == "sse2") { 3655 setSSELevel(Features, SSE2, Enabled); 3656 } else if (Name == "sse3") { 3657 setSSELevel(Features, SSE3, Enabled); 3658 } else if (Name == "ssse3") { 3659 setSSELevel(Features, SSSE3, Enabled); 3660 } else if (Name == "sse4.2") { 3661 setSSELevel(Features, SSE42, Enabled); 3662 } else if (Name == "sse4.1") { 3663 setSSELevel(Features, SSE41, Enabled); 3664 } else if (Name == "3dnow") { 3665 setMMXLevel(Features, AMD3DNow, Enabled); 3666 } else if (Name == "3dnowa") { 3667 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3668 } else if (Name == "aes") { 3669 if (Enabled) 3670 setSSELevel(Features, SSE2, Enabled); 3671 } else if (Name == "pclmul") { 3672 if (Enabled) 3673 setSSELevel(Features, SSE2, Enabled); 3674 } else if (Name == "avx") { 3675 setSSELevel(Features, AVX, Enabled); 3676 } else if (Name == "avx2") { 3677 setSSELevel(Features, AVX2, Enabled); 3678 } else if (Name == "avx512f") { 3679 setSSELevel(Features, AVX512F, Enabled); 3680 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3681 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3682 Name == "avx512vbmi" || Name == "avx512ifma" || 3683 Name == "avx512vpopcntdq") { 3684 if (Enabled) 3685 setSSELevel(Features, AVX512F, Enabled); 3686 // Enable BWI instruction if VBMI is being enabled. 3687 if (Name == "avx512vbmi" && Enabled) 3688 Features["avx512bw"] = true; 3689 // Also disable VBMI if BWI is being disabled. 3690 if (Name == "avx512bw" && !Enabled) 3691 Features["avx512vbmi"] = false; 3692 } else if (Name == "fma") { 3693 if (Enabled) 3694 setSSELevel(Features, AVX, Enabled); 3695 } else if (Name == "fma4") { 3696 setXOPLevel(Features, FMA4, Enabled); 3697 } else if (Name == "xop") { 3698 setXOPLevel(Features, XOP, Enabled); 3699 } else if (Name == "sse4a") { 3700 setXOPLevel(Features, SSE4A, Enabled); 3701 } else if (Name == "f16c") { 3702 if (Enabled) 3703 setSSELevel(Features, AVX, Enabled); 3704 } else if (Name == "sha") { 3705 if (Enabled) 3706 setSSELevel(Features, SSE2, Enabled); 3707 } else if (Name == "sse4") { 3708 // We can get here via the __target__ attribute since that's not controlled 3709 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3710 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3711 // disabled. 3712 if (Enabled) 3713 setSSELevel(Features, SSE42, Enabled); 3714 else 3715 setSSELevel(Features, SSE41, Enabled); 3716 } else if (Name == "xsave") { 3717 if (!Enabled) 3718 Features["xsaveopt"] = false; 3719 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3720 if (Enabled) 3721 Features["xsave"] = true; 3722 } 3723 } 3724 3725 /// handleTargetFeatures - Perform initialization based on the user 3726 /// configured set of features. 3727 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3728 DiagnosticsEngine &Diags) { 3729 for (const auto &Feature : Features) { 3730 if (Feature[0] != '+') 3731 continue; 3732 3733 if (Feature == "+aes") { 3734 HasAES = true; 3735 } else if (Feature == "+pclmul") { 3736 HasPCLMUL = true; 3737 } else if (Feature == "+lzcnt") { 3738 HasLZCNT = true; 3739 } else if (Feature == "+rdrnd") { 3740 HasRDRND = true; 3741 } else if (Feature == "+fsgsbase") { 3742 HasFSGSBASE = true; 3743 } else if (Feature == "+bmi") { 3744 HasBMI = true; 3745 } else if (Feature == "+bmi2") { 3746 HasBMI2 = true; 3747 } else if (Feature == "+popcnt") { 3748 HasPOPCNT = true; 3749 } else if (Feature == "+rtm") { 3750 HasRTM = true; 3751 } else if (Feature == "+prfchw") { 3752 HasPRFCHW = true; 3753 } else if (Feature == "+rdseed") { 3754 HasRDSEED = true; 3755 } else if (Feature == "+adx") { 3756 HasADX = true; 3757 } else if (Feature == "+tbm") { 3758 HasTBM = true; 3759 } else if (Feature == "+lwp") { 3760 HasLWP = true; 3761 } else if (Feature == "+fma") { 3762 HasFMA = true; 3763 } else if (Feature == "+f16c") { 3764 HasF16C = true; 3765 } else if (Feature == "+avx512cd") { 3766 HasAVX512CD = true; 3767 } else if (Feature == "+avx512vpopcntdq") { 3768 HasAVX512VPOPCNTDQ = true; 3769 } else if (Feature == "+avx512er") { 3770 HasAVX512ER = true; 3771 } else if (Feature == "+avx512pf") { 3772 HasAVX512PF = true; 3773 } else if (Feature == "+avx512dq") { 3774 HasAVX512DQ = true; 3775 } else if (Feature == "+avx512bw") { 3776 HasAVX512BW = true; 3777 } else if (Feature == "+avx512vl") { 3778 HasAVX512VL = true; 3779 } else if (Feature == "+avx512vbmi") { 3780 HasAVX512VBMI = true; 3781 } else if (Feature == "+avx512ifma") { 3782 HasAVX512IFMA = true; 3783 } else if (Feature == "+sha") { 3784 HasSHA = true; 3785 } else if (Feature == "+mpx") { 3786 HasMPX = true; 3787 } else if (Feature == "+movbe") { 3788 HasMOVBE = true; 3789 } else if (Feature == "+sgx") { 3790 HasSGX = true; 3791 } else if (Feature == "+cx16") { 3792 HasCX16 = true; 3793 } else if (Feature == "+fxsr") { 3794 HasFXSR = true; 3795 } else if (Feature == "+xsave") { 3796 HasXSAVE = true; 3797 } else if (Feature == "+xsaveopt") { 3798 HasXSAVEOPT = true; 3799 } else if (Feature == "+xsavec") { 3800 HasXSAVEC = true; 3801 } else if (Feature == "+xsaves") { 3802 HasXSAVES = true; 3803 } else if (Feature == "+mwaitx") { 3804 HasMWAITX = true; 3805 } else if (Feature == "+pku") { 3806 HasPKU = true; 3807 } else if (Feature == "+clflushopt") { 3808 HasCLFLUSHOPT = true; 3809 } else if (Feature == "+clwb") { 3810 HasCLWB = true; 3811 } else if (Feature == "+prefetchwt1") { 3812 HasPREFETCHWT1 = true; 3813 } else if (Feature == "+clzero") { 3814 HasCLZERO = true; 3815 } 3816 3817 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3818 .Case("+avx512f", AVX512F) 3819 .Case("+avx2", AVX2) 3820 .Case("+avx", AVX) 3821 .Case("+sse4.2", SSE42) 3822 .Case("+sse4.1", SSE41) 3823 .Case("+ssse3", SSSE3) 3824 .Case("+sse3", SSE3) 3825 .Case("+sse2", SSE2) 3826 .Case("+sse", SSE1) 3827 .Default(NoSSE); 3828 SSELevel = std::max(SSELevel, Level); 3829 3830 MMX3DNowEnum ThreeDNowLevel = 3831 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3832 .Case("+3dnowa", AMD3DNowAthlon) 3833 .Case("+3dnow", AMD3DNow) 3834 .Case("+mmx", MMX) 3835 .Default(NoMMX3DNow); 3836 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3837 3838 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3839 .Case("+xop", XOP) 3840 .Case("+fma4", FMA4) 3841 .Case("+sse4a", SSE4A) 3842 .Default(NoXOP); 3843 XOPLevel = std::max(XOPLevel, XLevel); 3844 } 3845 3846 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3847 // matches the selected sse level. 3848 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3849 (FPMath == FP_387 && SSELevel >= SSE1)) { 3850 Diags.Report(diag::err_target_unsupported_fpmath) << 3851 (FPMath == FP_SSE ? "sse" : "387"); 3852 return false; 3853 } 3854 3855 SimdDefaultAlign = 3856 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3857 return true; 3858 } 3859 3860 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3861 /// definitions for this particular subtarget. 3862 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3863 MacroBuilder &Builder) const { 3864 // Target identification. 3865 if (getTriple().getArch() == llvm::Triple::x86_64) { 3866 Builder.defineMacro("__amd64__"); 3867 Builder.defineMacro("__amd64"); 3868 Builder.defineMacro("__x86_64"); 3869 Builder.defineMacro("__x86_64__"); 3870 if (getTriple().getArchName() == "x86_64h") { 3871 Builder.defineMacro("__x86_64h"); 3872 Builder.defineMacro("__x86_64h__"); 3873 } 3874 } else { 3875 DefineStd(Builder, "i386", Opts); 3876 } 3877 3878 // Subtarget options. 3879 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3880 // truly should be based on -mtune options. 3881 switch (CPU) { 3882 case CK_Generic: 3883 break; 3884 case CK_i386: 3885 // The rest are coming from the i386 define above. 3886 Builder.defineMacro("__tune_i386__"); 3887 break; 3888 case CK_i486: 3889 case CK_WinChipC6: 3890 case CK_WinChip2: 3891 case CK_C3: 3892 defineCPUMacros(Builder, "i486"); 3893 break; 3894 case CK_PentiumMMX: 3895 Builder.defineMacro("__pentium_mmx__"); 3896 Builder.defineMacro("__tune_pentium_mmx__"); 3897 LLVM_FALLTHROUGH; 3898 case CK_i586: 3899 case CK_Pentium: 3900 defineCPUMacros(Builder, "i586"); 3901 defineCPUMacros(Builder, "pentium"); 3902 break; 3903 case CK_Pentium3: 3904 case CK_Pentium3M: 3905 case CK_PentiumM: 3906 Builder.defineMacro("__tune_pentium3__"); 3907 LLVM_FALLTHROUGH; 3908 case CK_Pentium2: 3909 case CK_C3_2: 3910 Builder.defineMacro("__tune_pentium2__"); 3911 LLVM_FALLTHROUGH; 3912 case CK_PentiumPro: 3913 Builder.defineMacro("__tune_i686__"); 3914 Builder.defineMacro("__tune_pentiumpro__"); 3915 LLVM_FALLTHROUGH; 3916 case CK_i686: 3917 Builder.defineMacro("__i686"); 3918 Builder.defineMacro("__i686__"); 3919 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3920 Builder.defineMacro("__pentiumpro"); 3921 Builder.defineMacro("__pentiumpro__"); 3922 break; 3923 case CK_Pentium4: 3924 case CK_Pentium4M: 3925 defineCPUMacros(Builder, "pentium4"); 3926 break; 3927 case CK_Yonah: 3928 case CK_Prescott: 3929 case CK_Nocona: 3930 defineCPUMacros(Builder, "nocona"); 3931 break; 3932 case CK_Core2: 3933 case CK_Penryn: 3934 defineCPUMacros(Builder, "core2"); 3935 break; 3936 case CK_Bonnell: 3937 defineCPUMacros(Builder, "atom"); 3938 break; 3939 case CK_Silvermont: 3940 defineCPUMacros(Builder, "slm"); 3941 break; 3942 case CK_Goldmont: 3943 defineCPUMacros(Builder, "goldmont"); 3944 break; 3945 case CK_Nehalem: 3946 case CK_Westmere: 3947 case CK_SandyBridge: 3948 case CK_IvyBridge: 3949 case CK_Haswell: 3950 case CK_Broadwell: 3951 case CK_SkylakeClient: 3952 // FIXME: Historically, we defined this legacy name, it would be nice to 3953 // remove it at some point. We've never exposed fine-grained names for 3954 // recent primary x86 CPUs, and we should keep it that way. 3955 defineCPUMacros(Builder, "corei7"); 3956 break; 3957 case CK_SkylakeServer: 3958 defineCPUMacros(Builder, "skx"); 3959 break; 3960 case CK_Cannonlake: 3961 break; 3962 case CK_KNL: 3963 defineCPUMacros(Builder, "knl"); 3964 break; 3965 case CK_Lakemont: 3966 Builder.defineMacro("__tune_lakemont__"); 3967 break; 3968 case CK_K6_2: 3969 Builder.defineMacro("__k6_2__"); 3970 Builder.defineMacro("__tune_k6_2__"); 3971 LLVM_FALLTHROUGH; 3972 case CK_K6_3: 3973 if (CPU != CK_K6_2) { // In case of fallthrough 3974 // FIXME: GCC may be enabling these in cases where some other k6 3975 // architecture is specified but -m3dnow is explicitly provided. The 3976 // exact semantics need to be determined and emulated here. 3977 Builder.defineMacro("__k6_3__"); 3978 Builder.defineMacro("__tune_k6_3__"); 3979 } 3980 LLVM_FALLTHROUGH; 3981 case CK_K6: 3982 defineCPUMacros(Builder, "k6"); 3983 break; 3984 case CK_Athlon: 3985 case CK_AthlonThunderbird: 3986 case CK_Athlon4: 3987 case CK_AthlonXP: 3988 case CK_AthlonMP: 3989 defineCPUMacros(Builder, "athlon"); 3990 if (SSELevel != NoSSE) { 3991 Builder.defineMacro("__athlon_sse__"); 3992 Builder.defineMacro("__tune_athlon_sse__"); 3993 } 3994 break; 3995 case CK_K8: 3996 case CK_K8SSE3: 3997 case CK_x86_64: 3998 case CK_Opteron: 3999 case CK_OpteronSSE3: 4000 case CK_Athlon64: 4001 case CK_Athlon64SSE3: 4002 case CK_AthlonFX: 4003 defineCPUMacros(Builder, "k8"); 4004 break; 4005 case CK_AMDFAM10: 4006 defineCPUMacros(Builder, "amdfam10"); 4007 break; 4008 case CK_BTVER1: 4009 defineCPUMacros(Builder, "btver1"); 4010 break; 4011 case CK_BTVER2: 4012 defineCPUMacros(Builder, "btver2"); 4013 break; 4014 case CK_BDVER1: 4015 defineCPUMacros(Builder, "bdver1"); 4016 break; 4017 case CK_BDVER2: 4018 defineCPUMacros(Builder, "bdver2"); 4019 break; 4020 case CK_BDVER3: 4021 defineCPUMacros(Builder, "bdver3"); 4022 break; 4023 case CK_BDVER4: 4024 defineCPUMacros(Builder, "bdver4"); 4025 break; 4026 case CK_ZNVER1: 4027 defineCPUMacros(Builder, "znver1"); 4028 break; 4029 case CK_Geode: 4030 defineCPUMacros(Builder, "geode"); 4031 break; 4032 } 4033 4034 // Target properties. 4035 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4036 4037 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 4038 // functions in glibc header files that use FP Stack inline asm which the 4039 // backend can't deal with (PR879). 4040 Builder.defineMacro("__NO_MATH_INLINES"); 4041 4042 if (HasAES) 4043 Builder.defineMacro("__AES__"); 4044 4045 if (HasPCLMUL) 4046 Builder.defineMacro("__PCLMUL__"); 4047 4048 if (HasLZCNT) 4049 Builder.defineMacro("__LZCNT__"); 4050 4051 if (HasRDRND) 4052 Builder.defineMacro("__RDRND__"); 4053 4054 if (HasFSGSBASE) 4055 Builder.defineMacro("__FSGSBASE__"); 4056 4057 if (HasBMI) 4058 Builder.defineMacro("__BMI__"); 4059 4060 if (HasBMI2) 4061 Builder.defineMacro("__BMI2__"); 4062 4063 if (HasPOPCNT) 4064 Builder.defineMacro("__POPCNT__"); 4065 4066 if (HasRTM) 4067 Builder.defineMacro("__RTM__"); 4068 4069 if (HasPRFCHW) 4070 Builder.defineMacro("__PRFCHW__"); 4071 4072 if (HasRDSEED) 4073 Builder.defineMacro("__RDSEED__"); 4074 4075 if (HasADX) 4076 Builder.defineMacro("__ADX__"); 4077 4078 if (HasTBM) 4079 Builder.defineMacro("__TBM__"); 4080 4081 if (HasLWP) 4082 Builder.defineMacro("__LWP__"); 4083 4084 if (HasMWAITX) 4085 Builder.defineMacro("__MWAITX__"); 4086 4087 switch (XOPLevel) { 4088 case XOP: 4089 Builder.defineMacro("__XOP__"); 4090 LLVM_FALLTHROUGH; 4091 case FMA4: 4092 Builder.defineMacro("__FMA4__"); 4093 LLVM_FALLTHROUGH; 4094 case SSE4A: 4095 Builder.defineMacro("__SSE4A__"); 4096 LLVM_FALLTHROUGH; 4097 case NoXOP: 4098 break; 4099 } 4100 4101 if (HasFMA) 4102 Builder.defineMacro("__FMA__"); 4103 4104 if (HasF16C) 4105 Builder.defineMacro("__F16C__"); 4106 4107 if (HasAVX512CD) 4108 Builder.defineMacro("__AVX512CD__"); 4109 if (HasAVX512VPOPCNTDQ) 4110 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 4111 if (HasAVX512ER) 4112 Builder.defineMacro("__AVX512ER__"); 4113 if (HasAVX512PF) 4114 Builder.defineMacro("__AVX512PF__"); 4115 if (HasAVX512DQ) 4116 Builder.defineMacro("__AVX512DQ__"); 4117 if (HasAVX512BW) 4118 Builder.defineMacro("__AVX512BW__"); 4119 if (HasAVX512VL) 4120 Builder.defineMacro("__AVX512VL__"); 4121 if (HasAVX512VBMI) 4122 Builder.defineMacro("__AVX512VBMI__"); 4123 if (HasAVX512IFMA) 4124 Builder.defineMacro("__AVX512IFMA__"); 4125 4126 if (HasSHA) 4127 Builder.defineMacro("__SHA__"); 4128 4129 if (HasFXSR) 4130 Builder.defineMacro("__FXSR__"); 4131 if (HasXSAVE) 4132 Builder.defineMacro("__XSAVE__"); 4133 if (HasXSAVEOPT) 4134 Builder.defineMacro("__XSAVEOPT__"); 4135 if (HasXSAVEC) 4136 Builder.defineMacro("__XSAVEC__"); 4137 if (HasXSAVES) 4138 Builder.defineMacro("__XSAVES__"); 4139 if (HasPKU) 4140 Builder.defineMacro("__PKU__"); 4141 if (HasCX16) 4142 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 4143 if (HasCLFLUSHOPT) 4144 Builder.defineMacro("__CLFLUSHOPT__"); 4145 if (HasCLWB) 4146 Builder.defineMacro("__CLWB__"); 4147 if (HasMPX) 4148 Builder.defineMacro("__MPX__"); 4149 if (HasSGX) 4150 Builder.defineMacro("__SGX__"); 4151 if (HasPREFETCHWT1) 4152 Builder.defineMacro("__PREFETCHWT1__"); 4153 if (HasCLZERO) 4154 Builder.defineMacro("__CLZERO__"); 4155 4156 // Each case falls through to the previous one here. 4157 switch (SSELevel) { 4158 case AVX512F: 4159 Builder.defineMacro("__AVX512F__"); 4160 LLVM_FALLTHROUGH; 4161 case AVX2: 4162 Builder.defineMacro("__AVX2__"); 4163 LLVM_FALLTHROUGH; 4164 case AVX: 4165 Builder.defineMacro("__AVX__"); 4166 LLVM_FALLTHROUGH; 4167 case SSE42: 4168 Builder.defineMacro("__SSE4_2__"); 4169 LLVM_FALLTHROUGH; 4170 case SSE41: 4171 Builder.defineMacro("__SSE4_1__"); 4172 LLVM_FALLTHROUGH; 4173 case SSSE3: 4174 Builder.defineMacro("__SSSE3__"); 4175 LLVM_FALLTHROUGH; 4176 case SSE3: 4177 Builder.defineMacro("__SSE3__"); 4178 LLVM_FALLTHROUGH; 4179 case SSE2: 4180 Builder.defineMacro("__SSE2__"); 4181 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 4182 LLVM_FALLTHROUGH; 4183 case SSE1: 4184 Builder.defineMacro("__SSE__"); 4185 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 4186 LLVM_FALLTHROUGH; 4187 case NoSSE: 4188 break; 4189 } 4190 4191 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 4192 switch (SSELevel) { 4193 case AVX512F: 4194 case AVX2: 4195 case AVX: 4196 case SSE42: 4197 case SSE41: 4198 case SSSE3: 4199 case SSE3: 4200 case SSE2: 4201 Builder.defineMacro("_M_IX86_FP", Twine(2)); 4202 break; 4203 case SSE1: 4204 Builder.defineMacro("_M_IX86_FP", Twine(1)); 4205 break; 4206 default: 4207 Builder.defineMacro("_M_IX86_FP", Twine(0)); 4208 break; 4209 } 4210 } 4211 4212 // Each case falls through to the previous one here. 4213 switch (MMX3DNowLevel) { 4214 case AMD3DNowAthlon: 4215 Builder.defineMacro("__3dNOW_A__"); 4216 LLVM_FALLTHROUGH; 4217 case AMD3DNow: 4218 Builder.defineMacro("__3dNOW__"); 4219 LLVM_FALLTHROUGH; 4220 case MMX: 4221 Builder.defineMacro("__MMX__"); 4222 LLVM_FALLTHROUGH; 4223 case NoMMX3DNow: 4224 break; 4225 } 4226 4227 if (CPU >= CK_i486) { 4228 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4229 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4230 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4231 } 4232 if (CPU >= CK_i586) 4233 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4234 4235 if (HasFloat128) 4236 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 4237 } 4238 4239 bool X86TargetInfo::hasFeature(StringRef Feature) const { 4240 return llvm::StringSwitch<bool>(Feature) 4241 .Case("aes", HasAES) 4242 .Case("avx", SSELevel >= AVX) 4243 .Case("avx2", SSELevel >= AVX2) 4244 .Case("avx512f", SSELevel >= AVX512F) 4245 .Case("avx512cd", HasAVX512CD) 4246 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 4247 .Case("avx512er", HasAVX512ER) 4248 .Case("avx512pf", HasAVX512PF) 4249 .Case("avx512dq", HasAVX512DQ) 4250 .Case("avx512bw", HasAVX512BW) 4251 .Case("avx512vl", HasAVX512VL) 4252 .Case("avx512vbmi", HasAVX512VBMI) 4253 .Case("avx512ifma", HasAVX512IFMA) 4254 .Case("bmi", HasBMI) 4255 .Case("bmi2", HasBMI2) 4256 .Case("clflushopt", HasCLFLUSHOPT) 4257 .Case("clwb", HasCLWB) 4258 .Case("clzero", HasCLZERO) 4259 .Case("cx16", HasCX16) 4260 .Case("f16c", HasF16C) 4261 .Case("fma", HasFMA) 4262 .Case("fma4", XOPLevel >= FMA4) 4263 .Case("fsgsbase", HasFSGSBASE) 4264 .Case("fxsr", HasFXSR) 4265 .Case("lzcnt", HasLZCNT) 4266 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4267 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4268 .Case("mmx", MMX3DNowLevel >= MMX) 4269 .Case("movbe", HasMOVBE) 4270 .Case("mpx", HasMPX) 4271 .Case("pclmul", HasPCLMUL) 4272 .Case("pku", HasPKU) 4273 .Case("popcnt", HasPOPCNT) 4274 .Case("prefetchwt1", HasPREFETCHWT1) 4275 .Case("prfchw", HasPRFCHW) 4276 .Case("rdrnd", HasRDRND) 4277 .Case("rdseed", HasRDSEED) 4278 .Case("rtm", HasRTM) 4279 .Case("sgx", HasSGX) 4280 .Case("sha", HasSHA) 4281 .Case("sse", SSELevel >= SSE1) 4282 .Case("sse2", SSELevel >= SSE2) 4283 .Case("sse3", SSELevel >= SSE3) 4284 .Case("ssse3", SSELevel >= SSSE3) 4285 .Case("sse4.1", SSELevel >= SSE41) 4286 .Case("sse4.2", SSELevel >= SSE42) 4287 .Case("sse4a", XOPLevel >= SSE4A) 4288 .Case("tbm", HasTBM) 4289 .Case("lwp", HasLWP) 4290 .Case("x86", true) 4291 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4292 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4293 .Case("xop", XOPLevel >= XOP) 4294 .Case("xsave", HasXSAVE) 4295 .Case("xsavec", HasXSAVEC) 4296 .Case("xsaves", HasXSAVES) 4297 .Case("xsaveopt", HasXSAVEOPT) 4298 .Default(false); 4299 } 4300 4301 // We can't use a generic validation scheme for the features accepted here 4302 // versus subtarget features accepted in the target attribute because the 4303 // bitfield structure that's initialized in the runtime only supports the 4304 // below currently rather than the full range of subtarget features. (See 4305 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4306 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4307 return llvm::StringSwitch<bool>(FeatureStr) 4308 .Case("cmov", true) 4309 .Case("mmx", true) 4310 .Case("popcnt", true) 4311 .Case("sse", true) 4312 .Case("sse2", true) 4313 .Case("sse3", true) 4314 .Case("ssse3", true) 4315 .Case("sse4.1", true) 4316 .Case("sse4.2", true) 4317 .Case("avx", true) 4318 .Case("avx2", true) 4319 .Case("sse4a", true) 4320 .Case("fma4", true) 4321 .Case("xop", true) 4322 .Case("fma", true) 4323 .Case("avx512f", true) 4324 .Case("bmi", true) 4325 .Case("bmi2", true) 4326 .Case("aes", true) 4327 .Case("pclmul", true) 4328 .Case("avx512vl", true) 4329 .Case("avx512bw", true) 4330 .Case("avx512dq", true) 4331 .Case("avx512cd", true) 4332 .Case("avx512vpopcntdq", true) 4333 .Case("avx512er", true) 4334 .Case("avx512pf", true) 4335 .Case("avx512vbmi", true) 4336 .Case("avx512ifma", true) 4337 .Default(false); 4338 } 4339 4340 bool 4341 X86TargetInfo::validateAsmConstraint(const char *&Name, 4342 TargetInfo::ConstraintInfo &Info) const { 4343 switch (*Name) { 4344 default: return false; 4345 // Constant constraints. 4346 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4347 // instructions. 4348 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4349 // x86_64 instructions. 4350 case 's': 4351 Info.setRequiresImmediate(); 4352 return true; 4353 case 'I': 4354 Info.setRequiresImmediate(0, 31); 4355 return true; 4356 case 'J': 4357 Info.setRequiresImmediate(0, 63); 4358 return true; 4359 case 'K': 4360 Info.setRequiresImmediate(-128, 127); 4361 return true; 4362 case 'L': 4363 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4364 return true; 4365 case 'M': 4366 Info.setRequiresImmediate(0, 3); 4367 return true; 4368 case 'N': 4369 Info.setRequiresImmediate(0, 255); 4370 return true; 4371 case 'O': 4372 Info.setRequiresImmediate(0, 127); 4373 return true; 4374 // Register constraints. 4375 case 'Y': // 'Y' is the first character for several 2-character constraints. 4376 // Shift the pointer to the second character of the constraint. 4377 Name++; 4378 switch (*Name) { 4379 default: 4380 return false; 4381 case '0': // First SSE register. 4382 case 't': // Any SSE register, when SSE2 is enabled. 4383 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4384 case 'm': // Any MMX register, when inter-unit moves enabled. 4385 case 'k': // AVX512 arch mask registers: k1-k7. 4386 Info.setAllowsRegister(); 4387 return true; 4388 } 4389 case 'f': // Any x87 floating point stack register. 4390 // Constraint 'f' cannot be used for output operands. 4391 if (Info.ConstraintStr[0] == '=') 4392 return false; 4393 Info.setAllowsRegister(); 4394 return true; 4395 case 'a': // eax. 4396 case 'b': // ebx. 4397 case 'c': // ecx. 4398 case 'd': // edx. 4399 case 'S': // esi. 4400 case 'D': // edi. 4401 case 'A': // edx:eax. 4402 case 't': // Top of floating point stack. 4403 case 'u': // Second from top of floating point stack. 4404 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4405 case 'y': // Any MMX register. 4406 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4407 case 'x': // Any SSE register. 4408 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4409 // for intermideate k reg operations). 4410 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4411 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4412 case 'l': // "Index" registers: any general register that can be used as an 4413 // index in a base+index memory access. 4414 Info.setAllowsRegister(); 4415 return true; 4416 // Floating point constant constraints. 4417 case 'C': // SSE floating point constant. 4418 case 'G': // x87 floating point constant. 4419 return true; 4420 } 4421 } 4422 4423 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4424 unsigned Size) const { 4425 // Strip off constraint modifiers. 4426 while (Constraint[0] == '=' || 4427 Constraint[0] == '+' || 4428 Constraint[0] == '&') 4429 Constraint = Constraint.substr(1); 4430 4431 return validateOperandSize(Constraint, Size); 4432 } 4433 4434 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4435 unsigned Size) const { 4436 return validateOperandSize(Constraint, Size); 4437 } 4438 4439 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4440 unsigned Size) const { 4441 switch (Constraint[0]) { 4442 default: break; 4443 case 'k': 4444 // Registers k0-k7 (AVX512) size limit is 64 bit. 4445 case 'y': 4446 return Size <= 64; 4447 case 'f': 4448 case 't': 4449 case 'u': 4450 return Size <= 128; 4451 case 'v': 4452 case 'x': 4453 if (SSELevel >= AVX512F) 4454 // 512-bit zmm registers can be used if target supports AVX512F. 4455 return Size <= 512U; 4456 else if (SSELevel >= AVX) 4457 // 256-bit ymm registers can be used if target supports AVX. 4458 return Size <= 256U; 4459 return Size <= 128U; 4460 case 'Y': 4461 // 'Y' is the first character for several 2-character constraints. 4462 switch (Constraint[1]) { 4463 default: break; 4464 case 'm': 4465 // 'Ym' is synonymous with 'y'. 4466 case 'k': 4467 return Size <= 64; 4468 case 'i': 4469 case 't': 4470 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4471 if (SSELevel >= AVX512F) 4472 return Size <= 512U; 4473 else if (SSELevel >= AVX) 4474 return Size <= 256U; 4475 return SSELevel >= SSE2 && Size <= 128U; 4476 } 4477 4478 } 4479 4480 return true; 4481 } 4482 4483 std::string 4484 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4485 switch (*Constraint) { 4486 case 'a': return std::string("{ax}"); 4487 case 'b': return std::string("{bx}"); 4488 case 'c': return std::string("{cx}"); 4489 case 'd': return std::string("{dx}"); 4490 case 'S': return std::string("{si}"); 4491 case 'D': return std::string("{di}"); 4492 case 'p': // address 4493 return std::string("im"); 4494 case 't': // top of floating point stack. 4495 return std::string("{st}"); 4496 case 'u': // second from top of floating point stack. 4497 return std::string("{st(1)}"); // second from top of floating point stack. 4498 case 'Y': 4499 switch (Constraint[1]) { 4500 default: 4501 // Break from inner switch and fall through (copy single char), 4502 // continue parsing after copying the current constraint into 4503 // the return string. 4504 break; 4505 case 'k': 4506 // "^" hints llvm that this is a 2 letter constraint. 4507 // "Constraint++" is used to promote the string iterator 4508 // to the next constraint. 4509 return std::string("^") + std::string(Constraint++, 2); 4510 } 4511 LLVM_FALLTHROUGH; 4512 default: 4513 return std::string(1, *Constraint); 4514 } 4515 } 4516 4517 // X86-32 generic target 4518 class X86_32TargetInfo : public X86TargetInfo { 4519 public: 4520 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4521 : X86TargetInfo(Triple, Opts) { 4522 DoubleAlign = LongLongAlign = 32; 4523 LongDoubleWidth = 96; 4524 LongDoubleAlign = 32; 4525 SuitableAlign = 128; 4526 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4527 SizeType = UnsignedInt; 4528 PtrDiffType = SignedInt; 4529 IntPtrType = SignedInt; 4530 RegParmMax = 3; 4531 4532 // Use fpret for all types. 4533 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4534 (1 << TargetInfo::Double) | 4535 (1 << TargetInfo::LongDouble)); 4536 4537 // x86-32 has atomics up to 8 bytes 4538 // FIXME: Check that we actually have cmpxchg8b before setting 4539 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4540 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4541 } 4542 BuiltinVaListKind getBuiltinVaListKind() const override { 4543 return TargetInfo::CharPtrBuiltinVaList; 4544 } 4545 4546 int getEHDataRegisterNumber(unsigned RegNo) const override { 4547 if (RegNo == 0) return 0; 4548 if (RegNo == 1) return 2; 4549 return -1; 4550 } 4551 bool validateOperandSize(StringRef Constraint, 4552 unsigned Size) const override { 4553 switch (Constraint[0]) { 4554 default: break; 4555 case 'R': 4556 case 'q': 4557 case 'Q': 4558 case 'a': 4559 case 'b': 4560 case 'c': 4561 case 'd': 4562 case 'S': 4563 case 'D': 4564 return Size <= 32; 4565 case 'A': 4566 return Size <= 64; 4567 } 4568 4569 return X86TargetInfo::validateOperandSize(Constraint, Size); 4570 } 4571 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4572 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4573 Builtin::FirstTSBuiltin + 1); 4574 } 4575 }; 4576 4577 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4578 public: 4579 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4580 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4581 4582 unsigned getFloatEvalMethod() const override { 4583 unsigned Major, Minor, Micro; 4584 getTriple().getOSVersion(Major, Minor, Micro); 4585 // New NetBSD uses the default rounding mode. 4586 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4587 return X86_32TargetInfo::getFloatEvalMethod(); 4588 // NetBSD before 6.99.26 defaults to "double" rounding. 4589 return 1; 4590 } 4591 }; 4592 4593 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4594 public: 4595 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4596 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4597 SizeType = UnsignedLong; 4598 IntPtrType = SignedLong; 4599 PtrDiffType = SignedLong; 4600 } 4601 }; 4602 4603 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4604 public: 4605 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4606 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4607 SizeType = UnsignedLong; 4608 IntPtrType = SignedLong; 4609 PtrDiffType = SignedLong; 4610 } 4611 }; 4612 4613 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4614 public: 4615 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4616 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4617 LongDoubleWidth = 128; 4618 LongDoubleAlign = 128; 4619 SuitableAlign = 128; 4620 MaxVectorAlign = 256; 4621 // The watchOS simulator uses the builtin bool type for Objective-C. 4622 llvm::Triple T = llvm::Triple(Triple); 4623 if (T.isWatchOS()) 4624 UseSignedCharForObjCBool = false; 4625 SizeType = UnsignedLong; 4626 IntPtrType = SignedLong; 4627 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4628 HasAlignMac68kSupport = true; 4629 } 4630 4631 bool handleTargetFeatures(std::vector<std::string> &Features, 4632 DiagnosticsEngine &Diags) override { 4633 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4634 Diags)) 4635 return false; 4636 // We now know the features we have: we can decide how to align vectors. 4637 MaxVectorAlign = 4638 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4639 return true; 4640 } 4641 }; 4642 4643 // x86-32 Windows target 4644 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4645 public: 4646 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4647 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4648 WCharType = UnsignedShort; 4649 DoubleAlign = LongLongAlign = 64; 4650 bool IsWinCOFF = 4651 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4652 resetDataLayout(IsWinCOFF 4653 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4654 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4655 } 4656 void getTargetDefines(const LangOptions &Opts, 4657 MacroBuilder &Builder) const override { 4658 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4659 } 4660 }; 4661 4662 // x86-32 Windows Visual Studio target 4663 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4664 public: 4665 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4666 const TargetOptions &Opts) 4667 : WindowsX86_32TargetInfo(Triple, Opts) { 4668 LongDoubleWidth = LongDoubleAlign = 64; 4669 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4670 } 4671 void getTargetDefines(const LangOptions &Opts, 4672 MacroBuilder &Builder) const override { 4673 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4674 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4675 // The value of the following reflects processor type. 4676 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4677 // We lost the original triple, so we use the default. 4678 Builder.defineMacro("_M_IX86", "600"); 4679 } 4680 }; 4681 4682 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4683 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4684 // supports __declspec natively under -fms-extensions, but we define a no-op 4685 // __declspec macro anyway for pre-processor compatibility. 4686 if (Opts.MicrosoftExt) 4687 Builder.defineMacro("__declspec", "__declspec"); 4688 else 4689 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4690 4691 if (!Opts.MicrosoftExt) { 4692 // Provide macros for all the calling convention keywords. Provide both 4693 // single and double underscore prefixed variants. These are available on 4694 // x64 as well as x86, even though they have no effect. 4695 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4696 for (const char *CC : CCs) { 4697 std::string GCCSpelling = "__attribute__((__"; 4698 GCCSpelling += CC; 4699 GCCSpelling += "__))"; 4700 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4701 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4702 } 4703 } 4704 } 4705 4706 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4707 Builder.defineMacro("__MSVCRT__"); 4708 Builder.defineMacro("__MINGW32__"); 4709 addCygMingDefines(Opts, Builder); 4710 } 4711 4712 // x86-32 MinGW target 4713 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4714 public: 4715 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4716 : WindowsX86_32TargetInfo(Triple, Opts) { 4717 HasFloat128 = true; 4718 } 4719 void getTargetDefines(const LangOptions &Opts, 4720 MacroBuilder &Builder) const override { 4721 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4722 DefineStd(Builder, "WIN32", Opts); 4723 DefineStd(Builder, "WINNT", Opts); 4724 Builder.defineMacro("_X86_"); 4725 addMinGWDefines(Opts, Builder); 4726 } 4727 }; 4728 4729 // x86-32 Cygwin target 4730 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4731 public: 4732 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4733 : X86_32TargetInfo(Triple, Opts) { 4734 WCharType = UnsignedShort; 4735 DoubleAlign = LongLongAlign = 64; 4736 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4737 } 4738 void getTargetDefines(const LangOptions &Opts, 4739 MacroBuilder &Builder) const override { 4740 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4741 Builder.defineMacro("_X86_"); 4742 Builder.defineMacro("__CYGWIN__"); 4743 Builder.defineMacro("__CYGWIN32__"); 4744 addCygMingDefines(Opts, Builder); 4745 DefineStd(Builder, "unix", Opts); 4746 if (Opts.CPlusPlus) 4747 Builder.defineMacro("_GNU_SOURCE"); 4748 } 4749 }; 4750 4751 // x86-32 Haiku target 4752 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4753 public: 4754 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4755 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4756 } 4757 void getTargetDefines(const LangOptions &Opts, 4758 MacroBuilder &Builder) const override { 4759 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4760 Builder.defineMacro("__INTEL__"); 4761 } 4762 }; 4763 4764 // X86-32 MCU target 4765 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4766 public: 4767 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4768 : X86_32TargetInfo(Triple, Opts) { 4769 LongDoubleWidth = 64; 4770 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4771 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4772 WIntType = UnsignedInt; 4773 } 4774 4775 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4776 // On MCU we support only C calling convention. 4777 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4778 } 4779 4780 void getTargetDefines(const LangOptions &Opts, 4781 MacroBuilder &Builder) const override { 4782 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4783 Builder.defineMacro("__iamcu"); 4784 Builder.defineMacro("__iamcu__"); 4785 } 4786 4787 bool allowsLargerPreferedTypeAlignment() const override { 4788 return false; 4789 } 4790 }; 4791 4792 // RTEMS Target 4793 template<typename Target> 4794 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4795 protected: 4796 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4797 MacroBuilder &Builder) const override { 4798 // RTEMS defines; list based off of gcc output 4799 4800 Builder.defineMacro("__rtems__"); 4801 Builder.defineMacro("__ELF__"); 4802 } 4803 4804 public: 4805 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4806 : OSTargetInfo<Target>(Triple, Opts) { 4807 switch (Triple.getArch()) { 4808 default: 4809 case llvm::Triple::x86: 4810 // this->MCountName = ".mcount"; 4811 break; 4812 case llvm::Triple::mips: 4813 case llvm::Triple::mipsel: 4814 case llvm::Triple::ppc: 4815 case llvm::Triple::ppc64: 4816 case llvm::Triple::ppc64le: 4817 // this->MCountName = "_mcount"; 4818 break; 4819 case llvm::Triple::arm: 4820 // this->MCountName = "__mcount"; 4821 break; 4822 } 4823 } 4824 }; 4825 4826 // x86-32 RTEMS target 4827 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4828 public: 4829 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4830 : X86_32TargetInfo(Triple, Opts) { 4831 SizeType = UnsignedLong; 4832 IntPtrType = SignedLong; 4833 PtrDiffType = SignedLong; 4834 } 4835 void getTargetDefines(const LangOptions &Opts, 4836 MacroBuilder &Builder) const override { 4837 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4838 Builder.defineMacro("__INTEL__"); 4839 Builder.defineMacro("__rtems__"); 4840 } 4841 }; 4842 4843 // x86-64 generic target 4844 class X86_64TargetInfo : public X86TargetInfo { 4845 public: 4846 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4847 : X86TargetInfo(Triple, Opts) { 4848 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4849 bool IsWinCOFF = 4850 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4851 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4852 LongDoubleWidth = 128; 4853 LongDoubleAlign = 128; 4854 LargeArrayMinWidth = 128; 4855 LargeArrayAlign = 128; 4856 SuitableAlign = 128; 4857 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4858 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4859 IntPtrType = IsX32 ? SignedInt : SignedLong; 4860 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4861 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4862 RegParmMax = 6; 4863 4864 // Pointers are 32-bit in x32. 4865 resetDataLayout(IsX32 4866 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4867 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4868 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4869 4870 // Use fpret only for long double. 4871 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4872 4873 // Use fp2ret for _Complex long double. 4874 ComplexLongDoubleUsesFP2Ret = true; 4875 4876 // Make __builtin_ms_va_list available. 4877 HasBuiltinMSVaList = true; 4878 4879 // x86-64 has atomics up to 16 bytes. 4880 MaxAtomicPromoteWidth = 128; 4881 MaxAtomicInlineWidth = 128; 4882 } 4883 BuiltinVaListKind getBuiltinVaListKind() const override { 4884 return TargetInfo::X86_64ABIBuiltinVaList; 4885 } 4886 4887 int getEHDataRegisterNumber(unsigned RegNo) const override { 4888 if (RegNo == 0) return 0; 4889 if (RegNo == 1) return 1; 4890 return -1; 4891 } 4892 4893 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4894 switch (CC) { 4895 case CC_C: 4896 case CC_Swift: 4897 case CC_X86VectorCall: 4898 case CC_IntelOclBicc: 4899 case CC_X86_64Win64: 4900 case CC_PreserveMost: 4901 case CC_PreserveAll: 4902 case CC_X86RegCall: 4903 case CC_OpenCLKernel: 4904 return CCCR_OK; 4905 default: 4906 return CCCR_Warning; 4907 } 4908 } 4909 4910 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4911 return CC_C; 4912 } 4913 4914 // for x32 we need it here explicitly 4915 bool hasInt128Type() const override { return true; } 4916 unsigned getUnwindWordWidth() const override { return 64; } 4917 unsigned getRegisterWidth() const override { return 64; } 4918 4919 bool validateGlobalRegisterVariable(StringRef RegName, 4920 unsigned RegSize, 4921 bool &HasSizeMismatch) const override { 4922 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4923 // handle. 4924 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4925 // Check that the register size is 64-bit. 4926 HasSizeMismatch = RegSize != 64; 4927 return true; 4928 } 4929 4930 // Check if the register is a 32-bit register the backend can handle. 4931 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4932 HasSizeMismatch); 4933 } 4934 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4935 return llvm::makeArrayRef(BuiltinInfoX86, 4936 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4937 } 4938 }; 4939 4940 // x86-64 Windows target 4941 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4942 public: 4943 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4944 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4945 WCharType = UnsignedShort; 4946 LongWidth = LongAlign = 32; 4947 DoubleAlign = LongLongAlign = 64; 4948 IntMaxType = SignedLongLong; 4949 Int64Type = SignedLongLong; 4950 SizeType = UnsignedLongLong; 4951 PtrDiffType = SignedLongLong; 4952 IntPtrType = SignedLongLong; 4953 } 4954 4955 void getTargetDefines(const LangOptions &Opts, 4956 MacroBuilder &Builder) const override { 4957 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4958 Builder.defineMacro("_WIN64"); 4959 } 4960 4961 BuiltinVaListKind getBuiltinVaListKind() const override { 4962 return TargetInfo::CharPtrBuiltinVaList; 4963 } 4964 4965 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4966 switch (CC) { 4967 case CC_X86StdCall: 4968 case CC_X86ThisCall: 4969 case CC_X86FastCall: 4970 return CCCR_Ignore; 4971 case CC_C: 4972 case CC_X86VectorCall: 4973 case CC_IntelOclBicc: 4974 case CC_X86_64SysV: 4975 case CC_Swift: 4976 case CC_X86RegCall: 4977 case CC_OpenCLKernel: 4978 return CCCR_OK; 4979 default: 4980 return CCCR_Warning; 4981 } 4982 } 4983 }; 4984 4985 // x86-64 Windows Visual Studio target 4986 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4987 public: 4988 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4989 const TargetOptions &Opts) 4990 : WindowsX86_64TargetInfo(Triple, Opts) { 4991 LongDoubleWidth = LongDoubleAlign = 64; 4992 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4993 } 4994 void getTargetDefines(const LangOptions &Opts, 4995 MacroBuilder &Builder) const override { 4996 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4997 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4998 Builder.defineMacro("_M_X64", "100"); 4999 Builder.defineMacro("_M_AMD64", "100"); 5000 } 5001 }; 5002 5003 // x86-64 MinGW target 5004 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 5005 public: 5006 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5007 : WindowsX86_64TargetInfo(Triple, Opts) { 5008 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 5009 // with x86 FP ops. Weird. 5010 LongDoubleWidth = LongDoubleAlign = 128; 5011 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 5012 HasFloat128 = true; 5013 } 5014 5015 void getTargetDefines(const LangOptions &Opts, 5016 MacroBuilder &Builder) const override { 5017 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 5018 DefineStd(Builder, "WIN64", Opts); 5019 Builder.defineMacro("__MINGW64__"); 5020 addMinGWDefines(Opts, Builder); 5021 5022 // GCC defines this macro when it is using __gxx_personality_seh0. 5023 if (!Opts.SjLjExceptions) 5024 Builder.defineMacro("__SEH__"); 5025 } 5026 }; 5027 5028 // x86-64 Cygwin target 5029 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 5030 public: 5031 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5032 : X86_64TargetInfo(Triple, Opts) { 5033 TLSSupported = false; 5034 WCharType = UnsignedShort; 5035 } 5036 void getTargetDefines(const LangOptions &Opts, 5037 MacroBuilder &Builder) const override { 5038 X86_64TargetInfo::getTargetDefines(Opts, Builder); 5039 Builder.defineMacro("__x86_64__"); 5040 Builder.defineMacro("__CYGWIN__"); 5041 Builder.defineMacro("__CYGWIN64__"); 5042 addCygMingDefines(Opts, Builder); 5043 DefineStd(Builder, "unix", Opts); 5044 if (Opts.CPlusPlus) 5045 Builder.defineMacro("_GNU_SOURCE"); 5046 5047 // GCC defines this macro when it is using __gxx_personality_seh0. 5048 if (!Opts.SjLjExceptions) 5049 Builder.defineMacro("__SEH__"); 5050 } 5051 }; 5052 5053 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 5054 public: 5055 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5056 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5057 Int64Type = SignedLongLong; 5058 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 5059 llvm::Triple T = llvm::Triple(Triple); 5060 if (T.isiOS()) 5061 UseSignedCharForObjCBool = false; 5062 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 5063 } 5064 5065 bool handleTargetFeatures(std::vector<std::string> &Features, 5066 DiagnosticsEngine &Diags) override { 5067 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 5068 Diags)) 5069 return false; 5070 // We now know the features we have: we can decide how to align vectors. 5071 MaxVectorAlign = 5072 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 5073 return true; 5074 } 5075 }; 5076 5077 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 5078 public: 5079 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5080 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5081 IntMaxType = SignedLongLong; 5082 Int64Type = SignedLongLong; 5083 } 5084 }; 5085 5086 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 5087 public: 5088 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5089 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5090 IntMaxType = SignedLongLong; 5091 Int64Type = SignedLongLong; 5092 } 5093 }; 5094 5095 class ARMTargetInfo : public TargetInfo { 5096 // Possible FPU choices. 5097 enum FPUMode { 5098 VFP2FPU = (1 << 0), 5099 VFP3FPU = (1 << 1), 5100 VFP4FPU = (1 << 2), 5101 NeonFPU = (1 << 3), 5102 FPARMV8 = (1 << 4) 5103 }; 5104 5105 // Possible HWDiv features. 5106 enum HWDivMode { 5107 HWDivThumb = (1 << 0), 5108 HWDivARM = (1 << 1) 5109 }; 5110 5111 static bool FPUModeIsVFP(FPUMode Mode) { 5112 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 5113 } 5114 5115 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5116 static const char * const GCCRegNames[]; 5117 5118 std::string ABI, CPU; 5119 5120 StringRef CPUProfile; 5121 StringRef CPUAttr; 5122 5123 enum { 5124 FP_Default, 5125 FP_VFP, 5126 FP_Neon 5127 } FPMath; 5128 5129 unsigned ArchISA; 5130 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 5131 unsigned ArchProfile; 5132 unsigned ArchVersion; 5133 5134 unsigned FPU : 5; 5135 5136 unsigned IsAAPCS : 1; 5137 unsigned HWDiv : 2; 5138 5139 // Initialized via features. 5140 unsigned SoftFloat : 1; 5141 unsigned SoftFloatABI : 1; 5142 5143 unsigned CRC : 1; 5144 unsigned Crypto : 1; 5145 unsigned DSP : 1; 5146 unsigned Unaligned : 1; 5147 5148 enum { 5149 LDREX_B = (1 << 0), /// byte (8-bit) 5150 LDREX_H = (1 << 1), /// half (16-bit) 5151 LDREX_W = (1 << 2), /// word (32-bit) 5152 LDREX_D = (1 << 3), /// double (64-bit) 5153 }; 5154 5155 uint32_t LDREX; 5156 5157 // ACLE 6.5.1 Hardware floating point 5158 enum { 5159 HW_FP_HP = (1 << 1), /// half (16-bit) 5160 HW_FP_SP = (1 << 2), /// single (32-bit) 5161 HW_FP_DP = (1 << 3), /// double (64-bit) 5162 }; 5163 uint32_t HW_FP; 5164 5165 static const Builtin::Info BuiltinInfo[]; 5166 5167 void setABIAAPCS() { 5168 IsAAPCS = true; 5169 5170 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5171 const llvm::Triple &T = getTriple(); 5172 5173 // size_t is unsigned long on MachO-derived environments, NetBSD, 5174 // OpenBSD and Bitrig. 5175 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 5176 T.getOS() == llvm::Triple::OpenBSD || 5177 T.getOS() == llvm::Triple::Bitrig) 5178 SizeType = UnsignedLong; 5179 else 5180 SizeType = UnsignedInt; 5181 5182 switch (T.getOS()) { 5183 case llvm::Triple::NetBSD: 5184 case llvm::Triple::OpenBSD: 5185 WCharType = SignedInt; 5186 break; 5187 case llvm::Triple::Win32: 5188 WCharType = UnsignedShort; 5189 break; 5190 case llvm::Triple::Linux: 5191 default: 5192 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 5193 WCharType = UnsignedInt; 5194 break; 5195 } 5196 5197 UseBitFieldTypeAlignment = true; 5198 5199 ZeroLengthBitfieldBoundary = 0; 5200 5201 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 5202 // so set preferred for small types to 32. 5203 if (T.isOSBinFormatMachO()) { 5204 resetDataLayout(BigEndian 5205 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5206 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5207 } else if (T.isOSWindows()) { 5208 assert(!BigEndian && "Windows on ARM does not support big endian"); 5209 resetDataLayout("e" 5210 "-m:w" 5211 "-p:32:32" 5212 "-i64:64" 5213 "-v128:64:128" 5214 "-a:0:32" 5215 "-n32" 5216 "-S64"); 5217 } else if (T.isOSNaCl()) { 5218 assert(!BigEndian && "NaCl on ARM does not support big endian"); 5219 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 5220 } else { 5221 resetDataLayout(BigEndian 5222 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5223 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5224 } 5225 5226 // FIXME: Enumerated types are variable width in straight AAPCS. 5227 } 5228 5229 void setABIAPCS(bool IsAAPCS16) { 5230 const llvm::Triple &T = getTriple(); 5231 5232 IsAAPCS = false; 5233 5234 if (IsAAPCS16) 5235 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5236 else 5237 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 5238 5239 // size_t is unsigned int on FreeBSD. 5240 if (T.getOS() == llvm::Triple::FreeBSD) 5241 SizeType = UnsignedInt; 5242 else 5243 SizeType = UnsignedLong; 5244 5245 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 5246 WCharType = SignedInt; 5247 5248 // Do not respect the alignment of bit-field types when laying out 5249 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 5250 UseBitFieldTypeAlignment = false; 5251 5252 /// gcc forces the alignment to 4 bytes, regardless of the type of the 5253 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 5254 /// gcc. 5255 ZeroLengthBitfieldBoundary = 32; 5256 5257 if (T.isOSBinFormatMachO() && IsAAPCS16) { 5258 assert(!BigEndian && "AAPCS16 does not support big-endian"); 5259 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 5260 } else if (T.isOSBinFormatMachO()) 5261 resetDataLayout( 5262 BigEndian 5263 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5264 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5265 else 5266 resetDataLayout( 5267 BigEndian 5268 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5269 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5270 5271 // FIXME: Override "preferred align" for double and long long. 5272 } 5273 5274 void setArchInfo() { 5275 StringRef ArchName = getTriple().getArchName(); 5276 5277 ArchISA = llvm::ARM::parseArchISA(ArchName); 5278 CPU = llvm::ARM::getDefaultCPU(ArchName); 5279 unsigned AK = llvm::ARM::parseArch(ArchName); 5280 if (AK != llvm::ARM::AK_INVALID) 5281 ArchKind = AK; 5282 setArchInfo(ArchKind); 5283 } 5284 5285 void setArchInfo(unsigned Kind) { 5286 StringRef SubArch; 5287 5288 // cache TargetParser info 5289 ArchKind = Kind; 5290 SubArch = llvm::ARM::getSubArch(ArchKind); 5291 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5292 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5293 5294 // cache CPU related strings 5295 CPUAttr = getCPUAttr(); 5296 CPUProfile = getCPUProfile(); 5297 } 5298 5299 void setAtomic() { 5300 // when triple does not specify a sub arch, 5301 // then we are not using inline atomics 5302 bool ShouldUseInlineAtomic = 5303 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5304 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5305 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5306 if (ArchProfile == llvm::ARM::PK_M) { 5307 MaxAtomicPromoteWidth = 32; 5308 if (ShouldUseInlineAtomic) 5309 MaxAtomicInlineWidth = 32; 5310 } 5311 else { 5312 MaxAtomicPromoteWidth = 64; 5313 if (ShouldUseInlineAtomic) 5314 MaxAtomicInlineWidth = 64; 5315 } 5316 } 5317 5318 bool isThumb() const { 5319 return (ArchISA == llvm::ARM::IK_THUMB); 5320 } 5321 5322 bool supportsThumb() const { 5323 return CPUAttr.count('T') || ArchVersion >= 6; 5324 } 5325 5326 bool supportsThumb2() const { 5327 return CPUAttr.equals("6T2") || 5328 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5329 } 5330 5331 StringRef getCPUAttr() const { 5332 // For most sub-arches, the build attribute CPU name is enough. 5333 // For Cortex variants, it's slightly different. 5334 switch(ArchKind) { 5335 default: 5336 return llvm::ARM::getCPUAttr(ArchKind); 5337 case llvm::ARM::AK_ARMV6M: 5338 return "6M"; 5339 case llvm::ARM::AK_ARMV7S: 5340 return "7S"; 5341 case llvm::ARM::AK_ARMV7A: 5342 return "7A"; 5343 case llvm::ARM::AK_ARMV7R: 5344 return "7R"; 5345 case llvm::ARM::AK_ARMV7M: 5346 return "7M"; 5347 case llvm::ARM::AK_ARMV7EM: 5348 return "7EM"; 5349 case llvm::ARM::AK_ARMV7VE: 5350 return "7VE"; 5351 case llvm::ARM::AK_ARMV8A: 5352 return "8A"; 5353 case llvm::ARM::AK_ARMV8_1A: 5354 return "8_1A"; 5355 case llvm::ARM::AK_ARMV8_2A: 5356 return "8_2A"; 5357 case llvm::ARM::AK_ARMV8MBaseline: 5358 return "8M_BASE"; 5359 case llvm::ARM::AK_ARMV8MMainline: 5360 return "8M_MAIN"; 5361 case llvm::ARM::AK_ARMV8R: 5362 return "8R"; 5363 } 5364 } 5365 5366 StringRef getCPUProfile() const { 5367 switch(ArchProfile) { 5368 case llvm::ARM::PK_A: 5369 return "A"; 5370 case llvm::ARM::PK_R: 5371 return "R"; 5372 case llvm::ARM::PK_M: 5373 return "M"; 5374 default: 5375 return ""; 5376 } 5377 } 5378 5379 public: 5380 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5381 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5382 HW_FP(0) { 5383 5384 switch (getTriple().getOS()) { 5385 case llvm::Triple::NetBSD: 5386 case llvm::Triple::OpenBSD: 5387 PtrDiffType = SignedLong; 5388 break; 5389 default: 5390 PtrDiffType = SignedInt; 5391 break; 5392 } 5393 5394 // Cache arch related info. 5395 setArchInfo(); 5396 5397 // {} in inline assembly are neon specifiers, not assembly variant 5398 // specifiers. 5399 NoAsmVariants = true; 5400 5401 // FIXME: This duplicates code from the driver that sets the -target-abi 5402 // option - this code is used if -target-abi isn't passed and should 5403 // be unified in some way. 5404 if (Triple.isOSBinFormatMachO()) { 5405 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5406 // the frontend matches that. 5407 if (Triple.getEnvironment() == llvm::Triple::EABI || 5408 Triple.getOS() == llvm::Triple::UnknownOS || 5409 ArchProfile == llvm::ARM::PK_M) { 5410 setABI("aapcs"); 5411 } else if (Triple.isWatchABI()) { 5412 setABI("aapcs16"); 5413 } else { 5414 setABI("apcs-gnu"); 5415 } 5416 } else if (Triple.isOSWindows()) { 5417 // FIXME: this is invalid for WindowsCE 5418 setABI("aapcs"); 5419 } else { 5420 // Select the default based on the platform. 5421 switch (Triple.getEnvironment()) { 5422 case llvm::Triple::Android: 5423 case llvm::Triple::GNUEABI: 5424 case llvm::Triple::GNUEABIHF: 5425 case llvm::Triple::MuslEABI: 5426 case llvm::Triple::MuslEABIHF: 5427 setABI("aapcs-linux"); 5428 break; 5429 case llvm::Triple::EABIHF: 5430 case llvm::Triple::EABI: 5431 setABI("aapcs"); 5432 break; 5433 case llvm::Triple::GNU: 5434 setABI("apcs-gnu"); 5435 break; 5436 default: 5437 if (Triple.getOS() == llvm::Triple::NetBSD) 5438 setABI("apcs-gnu"); 5439 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5440 setABI("aapcs-linux"); 5441 else 5442 setABI("aapcs"); 5443 break; 5444 } 5445 } 5446 5447 // ARM targets default to using the ARM C++ ABI. 5448 TheCXXABI.set(TargetCXXABI::GenericARM); 5449 5450 // ARM has atomics up to 8 bytes 5451 setAtomic(); 5452 5453 // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS) 5454 if (IsAAPCS && (Triple.getEnvironment() != llvm::Triple::Android)) 5455 MaxVectorAlign = 64; 5456 5457 // Do force alignment of members that follow zero length bitfields. If 5458 // the alignment of the zero-length bitfield is greater than the member 5459 // that follows it, `bar', `bar' will be aligned as the type of the 5460 // zero length bitfield. 5461 UseZeroLengthBitfieldAlignment = true; 5462 5463 if (Triple.getOS() == llvm::Triple::Linux || 5464 Triple.getOS() == llvm::Triple::UnknownOS) 5465 this->MCountName = 5466 Opts.EABIVersion == llvm::EABI::GNU ? "\01__gnu_mcount_nc" : "\01mcount"; 5467 } 5468 5469 StringRef getABI() const override { return ABI; } 5470 5471 bool setABI(const std::string &Name) override { 5472 ABI = Name; 5473 5474 // The defaults (above) are for AAPCS, check if we need to change them. 5475 // 5476 // FIXME: We need support for -meabi... we could just mangle it into the 5477 // name. 5478 if (Name == "apcs-gnu" || Name == "aapcs16") { 5479 setABIAPCS(Name == "aapcs16"); 5480 return true; 5481 } 5482 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5483 setABIAAPCS(); 5484 return true; 5485 } 5486 return false; 5487 } 5488 5489 // FIXME: This should be based on Arch attributes, not CPU names. 5490 bool 5491 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5492 StringRef CPU, 5493 const std::vector<std::string> &FeaturesVec) const override { 5494 5495 std::vector<StringRef> TargetFeatures; 5496 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5497 5498 // get default FPU features 5499 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5500 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5501 5502 // get default Extension features 5503 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5504 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5505 5506 for (auto Feature : TargetFeatures) 5507 if (Feature[0] == '+') 5508 Features[Feature.drop_front(1)] = true; 5509 5510 // Enable or disable thumb-mode explicitly per function to enable mixed 5511 // ARM and Thumb code generation. 5512 if (isThumb()) 5513 Features["thumb-mode"] = true; 5514 else 5515 Features["thumb-mode"] = false; 5516 5517 // Convert user-provided arm and thumb GNU target attributes to 5518 // [-|+]thumb-mode target features respectively. 5519 std::vector<std::string> UpdatedFeaturesVec(FeaturesVec); 5520 for (auto &Feature : UpdatedFeaturesVec) { 5521 if (Feature.compare("+arm") == 0) 5522 Feature = "-thumb-mode"; 5523 else if (Feature.compare("+thumb") == 0) 5524 Feature = "+thumb-mode"; 5525 } 5526 5527 return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec); 5528 } 5529 5530 bool handleTargetFeatures(std::vector<std::string> &Features, 5531 DiagnosticsEngine &Diags) override { 5532 FPU = 0; 5533 CRC = 0; 5534 Crypto = 0; 5535 DSP = 0; 5536 Unaligned = 1; 5537 SoftFloat = SoftFloatABI = false; 5538 HWDiv = 0; 5539 5540 // This does not diagnose illegal cases like having both 5541 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5542 uint32_t HW_FP_remove = 0; 5543 for (const auto &Feature : Features) { 5544 if (Feature == "+soft-float") { 5545 SoftFloat = true; 5546 } else if (Feature == "+soft-float-abi") { 5547 SoftFloatABI = true; 5548 } else if (Feature == "+vfp2") { 5549 FPU |= VFP2FPU; 5550 HW_FP |= HW_FP_SP | HW_FP_DP; 5551 } else if (Feature == "+vfp3") { 5552 FPU |= VFP3FPU; 5553 HW_FP |= HW_FP_SP | HW_FP_DP; 5554 } else if (Feature == "+vfp4") { 5555 FPU |= VFP4FPU; 5556 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5557 } else if (Feature == "+fp-armv8") { 5558 FPU |= FPARMV8; 5559 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5560 } else if (Feature == "+neon") { 5561 FPU |= NeonFPU; 5562 HW_FP |= HW_FP_SP | HW_FP_DP; 5563 } else if (Feature == "+hwdiv") { 5564 HWDiv |= HWDivThumb; 5565 } else if (Feature == "+hwdiv-arm") { 5566 HWDiv |= HWDivARM; 5567 } else if (Feature == "+crc") { 5568 CRC = 1; 5569 } else if (Feature == "+crypto") { 5570 Crypto = 1; 5571 } else if (Feature == "+dsp") { 5572 DSP = 1; 5573 } else if (Feature == "+fp-only-sp") { 5574 HW_FP_remove |= HW_FP_DP; 5575 } else if (Feature == "+strict-align") { 5576 Unaligned = 0; 5577 } else if (Feature == "+fp16") { 5578 HW_FP |= HW_FP_HP; 5579 } 5580 } 5581 HW_FP &= ~HW_FP_remove; 5582 5583 switch (ArchVersion) { 5584 case 6: 5585 if (ArchProfile == llvm::ARM::PK_M) 5586 LDREX = 0; 5587 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5588 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5589 else 5590 LDREX = LDREX_W; 5591 break; 5592 case 7: 5593 if (ArchProfile == llvm::ARM::PK_M) 5594 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5595 else 5596 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5597 break; 5598 case 8: 5599 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5600 } 5601 5602 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5603 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5604 return false; 5605 } 5606 5607 if (FPMath == FP_Neon) 5608 Features.push_back("+neonfp"); 5609 else if (FPMath == FP_VFP) 5610 Features.push_back("-neonfp"); 5611 5612 // Remove front-end specific options which the backend handles differently. 5613 auto Feature = 5614 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5615 if (Feature != Features.end()) 5616 Features.erase(Feature); 5617 5618 return true; 5619 } 5620 5621 bool hasFeature(StringRef Feature) const override { 5622 return llvm::StringSwitch<bool>(Feature) 5623 .Case("arm", true) 5624 .Case("aarch32", true) 5625 .Case("softfloat", SoftFloat) 5626 .Case("thumb", isThumb()) 5627 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5628 .Case("vfp", FPU && !SoftFloat) 5629 .Case("hwdiv", HWDiv & HWDivThumb) 5630 .Case("hwdiv-arm", HWDiv & HWDivARM) 5631 .Default(false); 5632 } 5633 5634 bool setCPU(const std::string &Name) override { 5635 if (Name != "generic") 5636 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5637 5638 if (ArchKind == llvm::ARM::AK_INVALID) 5639 return false; 5640 setAtomic(); 5641 CPU = Name; 5642 return true; 5643 } 5644 5645 bool setFPMath(StringRef Name) override; 5646 5647 void getTargetDefinesARMV81A(const LangOptions &Opts, 5648 MacroBuilder &Builder) const { 5649 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5650 } 5651 5652 void getTargetDefinesARMV82A(const LangOptions &Opts, 5653 MacroBuilder &Builder) const { 5654 // Also include the ARMv8.1-A defines 5655 getTargetDefinesARMV81A(Opts, Builder); 5656 } 5657 5658 void getTargetDefines(const LangOptions &Opts, 5659 MacroBuilder &Builder) const override { 5660 // Target identification. 5661 Builder.defineMacro("__arm"); 5662 Builder.defineMacro("__arm__"); 5663 // For bare-metal none-eabi. 5664 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5665 (getTriple().getEnvironment() == llvm::Triple::EABI || 5666 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 5667 Builder.defineMacro("__ELF__"); 5668 5669 5670 // Target properties. 5671 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5672 5673 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5674 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5675 if (getTriple().isWatchABI()) 5676 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5677 5678 if (!CPUAttr.empty()) 5679 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5680 5681 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5682 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5683 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5684 5685 if (ArchVersion >= 8) { 5686 // ACLE 6.5.7 Crypto Extension 5687 if (Crypto) 5688 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5689 // ACLE 6.5.8 CRC32 Extension 5690 if (CRC) 5691 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5692 // ACLE 6.5.10 Numeric Maximum and Minimum 5693 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5694 // ACLE 6.5.9 Directed Rounding 5695 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5696 } 5697 5698 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5699 // is not defined for the M-profile. 5700 // NOTE that the default profile is assumed to be 'A' 5701 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5702 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5703 5704 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5705 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5706 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5707 // v7 and v8 architectures excluding v8-M Baseline. 5708 if (supportsThumb2()) 5709 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5710 else if (supportsThumb()) 5711 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5712 5713 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5714 // instruction set such as ARM or Thumb. 5715 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5716 5717 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5718 5719 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5720 if (!CPUProfile.empty()) 5721 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5722 5723 // ACLE 6.4.3 Unaligned access supported in hardware 5724 if (Unaligned) 5725 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5726 5727 // ACLE 6.4.4 LDREX/STREX 5728 if (LDREX) 5729 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5730 5731 // ACLE 6.4.5 CLZ 5732 if (ArchVersion == 5 || 5733 (ArchVersion == 6 && CPUProfile != "M") || 5734 ArchVersion > 6) 5735 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5736 5737 // ACLE 6.5.1 Hardware Floating Point 5738 if (HW_FP) 5739 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5740 5741 // ACLE predefines. 5742 Builder.defineMacro("__ARM_ACLE", "200"); 5743 5744 // FP16 support (we currently only support IEEE format). 5745 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5746 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5747 5748 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5749 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5750 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5751 5752 // Subtarget options. 5753 5754 // FIXME: It's more complicated than this and we don't really support 5755 // interworking. 5756 // Windows on ARM does not "support" interworking 5757 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5758 Builder.defineMacro("__THUMB_INTERWORK__"); 5759 5760 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5761 // Embedded targets on Darwin follow AAPCS, but not EABI. 5762 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5763 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5764 Builder.defineMacro("__ARM_EABI__"); 5765 Builder.defineMacro("__ARM_PCS", "1"); 5766 } 5767 5768 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5769 ABI == "aapcs16") 5770 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5771 5772 if (SoftFloat) 5773 Builder.defineMacro("__SOFTFP__"); 5774 5775 if (ArchKind == llvm::ARM::AK_XSCALE) 5776 Builder.defineMacro("__XSCALE__"); 5777 5778 if (isThumb()) { 5779 Builder.defineMacro("__THUMBEL__"); 5780 Builder.defineMacro("__thumb__"); 5781 if (supportsThumb2()) 5782 Builder.defineMacro("__thumb2__"); 5783 } 5784 5785 // ACLE 6.4.9 32-bit SIMD instructions 5786 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5787 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5788 5789 // ACLE 6.4.10 Hardware Integer Divide 5790 if (((HWDiv & HWDivThumb) && isThumb()) || 5791 ((HWDiv & HWDivARM) && !isThumb())) { 5792 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5793 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5794 } 5795 5796 // Note, this is always on in gcc, even though it doesn't make sense. 5797 Builder.defineMacro("__APCS_32__"); 5798 5799 if (FPUModeIsVFP((FPUMode) FPU)) { 5800 Builder.defineMacro("__VFP_FP__"); 5801 if (FPU & VFP2FPU) 5802 Builder.defineMacro("__ARM_VFPV2__"); 5803 if (FPU & VFP3FPU) 5804 Builder.defineMacro("__ARM_VFPV3__"); 5805 if (FPU & VFP4FPU) 5806 Builder.defineMacro("__ARM_VFPV4__"); 5807 if (FPU & FPARMV8) 5808 Builder.defineMacro("__ARM_FPV5__"); 5809 } 5810 5811 // This only gets set when Neon instructions are actually available, unlike 5812 // the VFP define, hence the soft float and arch check. This is subtly 5813 // different from gcc, we follow the intent which was that it should be set 5814 // when Neon instructions are actually available. 5815 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5816 Builder.defineMacro("__ARM_NEON", "1"); 5817 Builder.defineMacro("__ARM_NEON__"); 5818 // current AArch32 NEON implementations do not support double-precision 5819 // floating-point even when it is present in VFP. 5820 Builder.defineMacro("__ARM_NEON_FP", 5821 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5822 } 5823 5824 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5825 Opts.ShortWChar ? "2" : "4"); 5826 5827 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5828 Opts.ShortEnums ? "1" : "4"); 5829 5830 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5831 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5832 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5833 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5834 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5835 } 5836 5837 // ACLE 6.4.7 DSP instructions 5838 if (DSP) { 5839 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5840 } 5841 5842 // ACLE 6.4.8 Saturation instructions 5843 bool SAT = false; 5844 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5845 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5846 SAT = true; 5847 } 5848 5849 // ACLE 6.4.6 Q (saturation) flag 5850 if (DSP || SAT) 5851 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5852 5853 if (Opts.UnsafeFPMath) 5854 Builder.defineMacro("__ARM_FP_FAST", "1"); 5855 5856 switch(ArchKind) { 5857 default: break; 5858 case llvm::ARM::AK_ARMV8_1A: 5859 getTargetDefinesARMV81A(Opts, Builder); 5860 break; 5861 case llvm::ARM::AK_ARMV8_2A: 5862 getTargetDefinesARMV82A(Opts, Builder); 5863 break; 5864 } 5865 } 5866 5867 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5868 return llvm::makeArrayRef(BuiltinInfo, 5869 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5870 } 5871 bool isCLZForZeroUndef() const override { return false; } 5872 BuiltinVaListKind getBuiltinVaListKind() const override { 5873 return IsAAPCS 5874 ? AAPCSABIBuiltinVaList 5875 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5876 : TargetInfo::VoidPtrBuiltinVaList); 5877 } 5878 ArrayRef<const char *> getGCCRegNames() const override; 5879 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5880 bool validateAsmConstraint(const char *&Name, 5881 TargetInfo::ConstraintInfo &Info) const override { 5882 switch (*Name) { 5883 default: break; 5884 case 'l': // r0-r7 5885 case 'h': // r8-r15 5886 case 't': // VFP Floating point register single precision 5887 case 'w': // VFP Floating point register double precision 5888 Info.setAllowsRegister(); 5889 return true; 5890 case 'I': 5891 case 'J': 5892 case 'K': 5893 case 'L': 5894 case 'M': 5895 // FIXME 5896 return true; 5897 case 'Q': // A memory address that is a single base register. 5898 Info.setAllowsMemory(); 5899 return true; 5900 case 'U': // a memory reference... 5901 switch (Name[1]) { 5902 case 'q': // ...ARMV4 ldrsb 5903 case 'v': // ...VFP load/store (reg+constant offset) 5904 case 'y': // ...iWMMXt load/store 5905 case 't': // address valid for load/store opaque types wider 5906 // than 128-bits 5907 case 'n': // valid address for Neon doubleword vector load/store 5908 case 'm': // valid address for Neon element and structure load/store 5909 case 's': // valid address for non-offset loads/stores of quad-word 5910 // values in four ARM registers 5911 Info.setAllowsMemory(); 5912 Name++; 5913 return true; 5914 } 5915 } 5916 return false; 5917 } 5918 std::string convertConstraint(const char *&Constraint) const override { 5919 std::string R; 5920 switch (*Constraint) { 5921 case 'U': // Two-character constraint; add "^" hint for later parsing. 5922 R = std::string("^") + std::string(Constraint, 2); 5923 Constraint++; 5924 break; 5925 case 'p': // 'p' should be translated to 'r' by default. 5926 R = std::string("r"); 5927 break; 5928 default: 5929 return std::string(1, *Constraint); 5930 } 5931 return R; 5932 } 5933 bool 5934 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5935 std::string &SuggestedModifier) const override { 5936 bool isOutput = (Constraint[0] == '='); 5937 bool isInOut = (Constraint[0] == '+'); 5938 5939 // Strip off constraint modifiers. 5940 while (Constraint[0] == '=' || 5941 Constraint[0] == '+' || 5942 Constraint[0] == '&') 5943 Constraint = Constraint.substr(1); 5944 5945 switch (Constraint[0]) { 5946 default: break; 5947 case 'r': { 5948 switch (Modifier) { 5949 default: 5950 return (isInOut || isOutput || Size <= 64); 5951 case 'q': 5952 // A register of size 32 cannot fit a vector type. 5953 return false; 5954 } 5955 } 5956 } 5957 5958 return true; 5959 } 5960 const char *getClobbers() const override { 5961 // FIXME: Is this really right? 5962 return ""; 5963 } 5964 5965 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5966 switch (CC) { 5967 case CC_AAPCS: 5968 case CC_AAPCS_VFP: 5969 case CC_Swift: 5970 case CC_OpenCLKernel: 5971 return CCCR_OK; 5972 default: 5973 return CCCR_Warning; 5974 } 5975 } 5976 5977 int getEHDataRegisterNumber(unsigned RegNo) const override { 5978 if (RegNo == 0) return 0; 5979 if (RegNo == 1) return 1; 5980 return -1; 5981 } 5982 5983 bool hasSjLjLowering() const override { 5984 return true; 5985 } 5986 }; 5987 5988 bool ARMTargetInfo::setFPMath(StringRef Name) { 5989 if (Name == "neon") { 5990 FPMath = FP_Neon; 5991 return true; 5992 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5993 Name == "vfp4") { 5994 FPMath = FP_VFP; 5995 return true; 5996 } 5997 return false; 5998 } 5999 6000 const char * const ARMTargetInfo::GCCRegNames[] = { 6001 // Integer registers 6002 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6003 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 6004 6005 // Float registers 6006 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 6007 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 6008 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 6009 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6010 6011 // Double registers 6012 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 6013 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 6014 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 6015 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6016 6017 // Quad registers 6018 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 6019 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 6020 }; 6021 6022 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 6023 return llvm::makeArrayRef(GCCRegNames); 6024 } 6025 6026 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 6027 { { "a1" }, "r0" }, 6028 { { "a2" }, "r1" }, 6029 { { "a3" }, "r2" }, 6030 { { "a4" }, "r3" }, 6031 { { "v1" }, "r4" }, 6032 { { "v2" }, "r5" }, 6033 { { "v3" }, "r6" }, 6034 { { "v4" }, "r7" }, 6035 { { "v5" }, "r8" }, 6036 { { "v6", "rfp" }, "r9" }, 6037 { { "sl" }, "r10" }, 6038 { { "fp" }, "r11" }, 6039 { { "ip" }, "r12" }, 6040 { { "r13" }, "sp" }, 6041 { { "r14" }, "lr" }, 6042 { { "r15" }, "pc" }, 6043 // The S, D and Q registers overlap, but aren't really aliases; we 6044 // don't want to substitute one of these for a different-sized one. 6045 }; 6046 6047 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 6048 return llvm::makeArrayRef(GCCRegAliases); 6049 } 6050 6051 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 6052 #define BUILTIN(ID, TYPE, ATTRS) \ 6053 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6054 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6055 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6056 #include "clang/Basic/BuiltinsNEON.def" 6057 6058 #define BUILTIN(ID, TYPE, ATTRS) \ 6059 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6060 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 6061 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 6062 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6063 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6064 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 6065 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 6066 #include "clang/Basic/BuiltinsARM.def" 6067 }; 6068 6069 class ARMleTargetInfo : public ARMTargetInfo { 6070 public: 6071 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6072 : ARMTargetInfo(Triple, Opts) {} 6073 void getTargetDefines(const LangOptions &Opts, 6074 MacroBuilder &Builder) const override { 6075 Builder.defineMacro("__ARMEL__"); 6076 ARMTargetInfo::getTargetDefines(Opts, Builder); 6077 } 6078 }; 6079 6080 class ARMbeTargetInfo : public ARMTargetInfo { 6081 public: 6082 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6083 : ARMTargetInfo(Triple, Opts) {} 6084 void getTargetDefines(const LangOptions &Opts, 6085 MacroBuilder &Builder) const override { 6086 Builder.defineMacro("__ARMEB__"); 6087 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6088 ARMTargetInfo::getTargetDefines(Opts, Builder); 6089 } 6090 }; 6091 6092 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 6093 const llvm::Triple Triple; 6094 public: 6095 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6096 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 6097 WCharType = UnsignedShort; 6098 SizeType = UnsignedInt; 6099 } 6100 void getVisualStudioDefines(const LangOptions &Opts, 6101 MacroBuilder &Builder) const { 6102 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 6103 6104 // FIXME: this is invalid for WindowsCE 6105 Builder.defineMacro("_M_ARM_NT", "1"); 6106 Builder.defineMacro("_M_ARMT", "_M_ARM"); 6107 Builder.defineMacro("_M_THUMB", "_M_ARM"); 6108 6109 assert((Triple.getArch() == llvm::Triple::arm || 6110 Triple.getArch() == llvm::Triple::thumb) && 6111 "invalid architecture for Windows ARM target info"); 6112 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 6113 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 6114 6115 // TODO map the complete set of values 6116 // 31: VFPv3 40: VFPv4 6117 Builder.defineMacro("_M_ARM_FP", "31"); 6118 } 6119 BuiltinVaListKind getBuiltinVaListKind() const override { 6120 return TargetInfo::CharPtrBuiltinVaList; 6121 } 6122 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6123 switch (CC) { 6124 case CC_X86StdCall: 6125 case CC_X86ThisCall: 6126 case CC_X86FastCall: 6127 case CC_X86VectorCall: 6128 return CCCR_Ignore; 6129 case CC_C: 6130 case CC_OpenCLKernel: 6131 return CCCR_OK; 6132 default: 6133 return CCCR_Warning; 6134 } 6135 } 6136 }; 6137 6138 // Windows ARM + Itanium C++ ABI Target 6139 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 6140 public: 6141 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 6142 const TargetOptions &Opts) 6143 : WindowsARMTargetInfo(Triple, Opts) { 6144 TheCXXABI.set(TargetCXXABI::GenericARM); 6145 } 6146 6147 void getTargetDefines(const LangOptions &Opts, 6148 MacroBuilder &Builder) const override { 6149 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6150 6151 if (Opts.MSVCCompat) 6152 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6153 } 6154 }; 6155 6156 // Windows ARM, MS (C++) ABI 6157 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 6158 public: 6159 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 6160 const TargetOptions &Opts) 6161 : WindowsARMTargetInfo(Triple, Opts) { 6162 TheCXXABI.set(TargetCXXABI::Microsoft); 6163 } 6164 6165 void getTargetDefines(const LangOptions &Opts, 6166 MacroBuilder &Builder) const override { 6167 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6168 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6169 } 6170 }; 6171 6172 // ARM MinGW target 6173 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 6174 public: 6175 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6176 : WindowsARMTargetInfo(Triple, Opts) { 6177 TheCXXABI.set(TargetCXXABI::GenericARM); 6178 } 6179 6180 void getTargetDefines(const LangOptions &Opts, 6181 MacroBuilder &Builder) const override { 6182 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6183 DefineStd(Builder, "WIN32", Opts); 6184 DefineStd(Builder, "WINNT", Opts); 6185 Builder.defineMacro("_ARM_"); 6186 addMinGWDefines(Opts, Builder); 6187 } 6188 }; 6189 6190 // ARM Cygwin target 6191 class CygwinARMTargetInfo : public ARMleTargetInfo { 6192 public: 6193 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6194 : ARMleTargetInfo(Triple, Opts) { 6195 TLSSupported = false; 6196 WCharType = UnsignedShort; 6197 DoubleAlign = LongLongAlign = 64; 6198 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 6199 } 6200 void getTargetDefines(const LangOptions &Opts, 6201 MacroBuilder &Builder) const override { 6202 ARMleTargetInfo::getTargetDefines(Opts, Builder); 6203 Builder.defineMacro("_ARM_"); 6204 Builder.defineMacro("__CYGWIN__"); 6205 Builder.defineMacro("__CYGWIN32__"); 6206 DefineStd(Builder, "unix", Opts); 6207 if (Opts.CPlusPlus) 6208 Builder.defineMacro("_GNU_SOURCE"); 6209 } 6210 }; 6211 6212 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 6213 protected: 6214 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6215 MacroBuilder &Builder) const override { 6216 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6217 } 6218 6219 public: 6220 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6221 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 6222 HasAlignMac68kSupport = true; 6223 // iOS always has 64-bit atomic instructions. 6224 // FIXME: This should be based off of the target features in 6225 // ARMleTargetInfo. 6226 MaxAtomicInlineWidth = 64; 6227 6228 if (Triple.isWatchABI()) { 6229 // Darwin on iOS uses a variant of the ARM C++ ABI. 6230 TheCXXABI.set(TargetCXXABI::WatchOS); 6231 6232 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 6233 // size_t is long, it's a bit weird for it to be int. 6234 PtrDiffType = SignedLong; 6235 6236 // BOOL should be a real boolean on the new ABI 6237 UseSignedCharForObjCBool = false; 6238 } else 6239 TheCXXABI.set(TargetCXXABI::iOS); 6240 } 6241 }; 6242 6243 class AArch64TargetInfo : public TargetInfo { 6244 virtual void setDataLayout() = 0; 6245 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6246 static const char *const GCCRegNames[]; 6247 6248 enum FPUModeEnum { 6249 FPUMode, 6250 NeonMode 6251 }; 6252 6253 unsigned FPU; 6254 unsigned CRC; 6255 unsigned Crypto; 6256 unsigned Unaligned; 6257 unsigned HasFullFP16; 6258 llvm::AArch64::ArchKind ArchKind; 6259 6260 static const Builtin::Info BuiltinInfo[]; 6261 6262 std::string ABI; 6263 6264 public: 6265 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6266 : TargetInfo(Triple), ABI("aapcs") { 6267 if (getTriple().getOS() == llvm::Triple::NetBSD || 6268 getTriple().getOS() == llvm::Triple::OpenBSD) { 6269 WCharType = SignedInt; 6270 6271 // NetBSD apparently prefers consistency across ARM targets to consistency 6272 // across 64-bit targets. 6273 Int64Type = SignedLongLong; 6274 IntMaxType = SignedLongLong; 6275 } else { 6276 WCharType = UnsignedInt; 6277 Int64Type = SignedLong; 6278 IntMaxType = SignedLong; 6279 } 6280 6281 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6282 MaxVectorAlign = 128; 6283 MaxAtomicInlineWidth = 128; 6284 MaxAtomicPromoteWidth = 128; 6285 6286 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 6287 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6288 6289 // {} in inline assembly are neon specifiers, not assembly variant 6290 // specifiers. 6291 NoAsmVariants = true; 6292 6293 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 6294 // contributes to the alignment of the containing aggregate in the same way 6295 // a plain (non bit-field) member of that type would, without exception for 6296 // zero-sized or anonymous bit-fields." 6297 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 6298 UseZeroLengthBitfieldAlignment = true; 6299 6300 // AArch64 targets default to using the ARM C++ ABI. 6301 TheCXXABI.set(TargetCXXABI::GenericAArch64); 6302 6303 if (Triple.getOS() == llvm::Triple::Linux) 6304 this->MCountName = "\01_mcount"; 6305 else if (Triple.getOS() == llvm::Triple::UnknownOS) 6306 this->MCountName = Opts.EABIVersion == llvm::EABI::GNU ? "\01_mcount" : "mcount"; 6307 } 6308 6309 StringRef getABI() const override { return ABI; } 6310 bool setABI(const std::string &Name) override { 6311 if (Name != "aapcs" && Name != "darwinpcs") 6312 return false; 6313 6314 ABI = Name; 6315 return true; 6316 } 6317 6318 bool setCPU(const std::string &Name) override { 6319 return Name == "generic" || 6320 llvm::AArch64::parseCPUArch(Name) != 6321 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6322 } 6323 6324 void getTargetDefinesARMV81A(const LangOptions &Opts, 6325 MacroBuilder &Builder) const { 6326 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6327 } 6328 6329 void getTargetDefinesARMV82A(const LangOptions &Opts, 6330 MacroBuilder &Builder) const { 6331 // Also include the ARMv8.1 defines 6332 getTargetDefinesARMV81A(Opts, Builder); 6333 } 6334 6335 void getTargetDefines(const LangOptions &Opts, 6336 MacroBuilder &Builder) const override { 6337 // Target identification. 6338 Builder.defineMacro("__aarch64__"); 6339 // For bare-metal none-eabi. 6340 if (getTriple().getOS() == llvm::Triple::UnknownOS && 6341 (getTriple().getEnvironment() == llvm::Triple::EABI || 6342 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 6343 Builder.defineMacro("__ELF__"); 6344 6345 // Target properties. 6346 Builder.defineMacro("_LP64"); 6347 Builder.defineMacro("__LP64__"); 6348 6349 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6350 Builder.defineMacro("__ARM_ACLE", "200"); 6351 Builder.defineMacro("__ARM_ARCH", "8"); 6352 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6353 6354 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6355 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6356 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6357 6358 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6359 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6360 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6361 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6362 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6363 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6364 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6365 6366 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6367 6368 // 0xe implies support for half, single and double precision operations. 6369 Builder.defineMacro("__ARM_FP", "0xE"); 6370 6371 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6372 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6373 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6374 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6375 6376 if (Opts.UnsafeFPMath) 6377 Builder.defineMacro("__ARM_FP_FAST", "1"); 6378 6379 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6380 6381 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6382 Opts.ShortEnums ? "1" : "4"); 6383 6384 if (FPU == NeonMode) { 6385 Builder.defineMacro("__ARM_NEON", "1"); 6386 // 64-bit NEON supports half, single and double precision operations. 6387 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6388 } 6389 6390 if (CRC) 6391 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6392 6393 if (Crypto) 6394 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6395 6396 if (Unaligned) 6397 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6398 6399 switch(ArchKind) { 6400 default: break; 6401 case llvm::AArch64::ArchKind::AK_ARMV8_1A: 6402 getTargetDefinesARMV81A(Opts, Builder); 6403 break; 6404 case llvm::AArch64::ArchKind::AK_ARMV8_2A: 6405 getTargetDefinesARMV82A(Opts, Builder); 6406 break; 6407 } 6408 6409 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6410 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6411 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6412 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6413 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6414 } 6415 6416 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6417 return llvm::makeArrayRef(BuiltinInfo, 6418 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6419 } 6420 6421 bool hasFeature(StringRef Feature) const override { 6422 return Feature == "aarch64" || 6423 Feature == "arm64" || 6424 Feature == "arm" || 6425 (Feature == "neon" && FPU == NeonMode); 6426 } 6427 6428 bool handleTargetFeatures(std::vector<std::string> &Features, 6429 DiagnosticsEngine &Diags) override { 6430 FPU = FPUMode; 6431 CRC = 0; 6432 Crypto = 0; 6433 Unaligned = 1; 6434 HasFullFP16 = 0; 6435 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8A; 6436 6437 for (const auto &Feature : Features) { 6438 if (Feature == "+neon") 6439 FPU = NeonMode; 6440 if (Feature == "+crc") 6441 CRC = 1; 6442 if (Feature == "+crypto") 6443 Crypto = 1; 6444 if (Feature == "+strict-align") 6445 Unaligned = 0; 6446 if (Feature == "+v8.1a") 6447 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_1A; 6448 if (Feature == "+v8.2a") 6449 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_2A; 6450 if (Feature == "+fullfp16") 6451 HasFullFP16 = 1; 6452 } 6453 6454 setDataLayout(); 6455 6456 return true; 6457 } 6458 6459 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6460 switch (CC) { 6461 case CC_C: 6462 case CC_Swift: 6463 case CC_PreserveMost: 6464 case CC_PreserveAll: 6465 case CC_OpenCLKernel: 6466 return CCCR_OK; 6467 default: 6468 return CCCR_Warning; 6469 } 6470 } 6471 6472 bool isCLZForZeroUndef() const override { return false; } 6473 6474 BuiltinVaListKind getBuiltinVaListKind() const override { 6475 return TargetInfo::AArch64ABIBuiltinVaList; 6476 } 6477 6478 ArrayRef<const char *> getGCCRegNames() const override; 6479 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6480 6481 bool validateAsmConstraint(const char *&Name, 6482 TargetInfo::ConstraintInfo &Info) const override { 6483 switch (*Name) { 6484 default: 6485 return false; 6486 case 'w': // Floating point and SIMD registers (V0-V31) 6487 Info.setAllowsRegister(); 6488 return true; 6489 case 'I': // Constant that can be used with an ADD instruction 6490 case 'J': // Constant that can be used with a SUB instruction 6491 case 'K': // Constant that can be used with a 32-bit logical instruction 6492 case 'L': // Constant that can be used with a 64-bit logical instruction 6493 case 'M': // Constant that can be used as a 32-bit MOV immediate 6494 case 'N': // Constant that can be used as a 64-bit MOV immediate 6495 case 'Y': // Floating point constant zero 6496 case 'Z': // Integer constant zero 6497 return true; 6498 case 'Q': // A memory reference with base register and no offset 6499 Info.setAllowsMemory(); 6500 return true; 6501 case 'S': // A symbolic address 6502 Info.setAllowsRegister(); 6503 return true; 6504 case 'U': 6505 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6506 // Utf: A memory address suitable for ldp/stp in TF mode. 6507 // Usa: An absolute symbolic address. 6508 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6509 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6510 case 'z': // Zero register, wzr or xzr 6511 Info.setAllowsRegister(); 6512 return true; 6513 case 'x': // Floating point and SIMD registers (V0-V15) 6514 Info.setAllowsRegister(); 6515 return true; 6516 } 6517 return false; 6518 } 6519 6520 bool 6521 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6522 std::string &SuggestedModifier) const override { 6523 // Strip off constraint modifiers. 6524 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6525 Constraint = Constraint.substr(1); 6526 6527 switch (Constraint[0]) { 6528 default: 6529 return true; 6530 case 'z': 6531 case 'r': { 6532 switch (Modifier) { 6533 case 'x': 6534 case 'w': 6535 // For now assume that the person knows what they're 6536 // doing with the modifier. 6537 return true; 6538 default: 6539 // By default an 'r' constraint will be in the 'x' 6540 // registers. 6541 if (Size == 64) 6542 return true; 6543 6544 SuggestedModifier = "w"; 6545 return false; 6546 } 6547 } 6548 } 6549 } 6550 6551 const char *getClobbers() const override { return ""; } 6552 6553 int getEHDataRegisterNumber(unsigned RegNo) const override { 6554 if (RegNo == 0) 6555 return 0; 6556 if (RegNo == 1) 6557 return 1; 6558 return -1; 6559 } 6560 }; 6561 6562 const char *const AArch64TargetInfo::GCCRegNames[] = { 6563 // 32-bit Integer registers 6564 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6565 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6566 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6567 6568 // 64-bit Integer registers 6569 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6570 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6571 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6572 6573 // 32-bit floating point regsisters 6574 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6575 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6576 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6577 6578 // 64-bit floating point regsisters 6579 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6580 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6581 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6582 6583 // Vector registers 6584 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6585 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6586 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6587 }; 6588 6589 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6590 return llvm::makeArrayRef(GCCRegNames); 6591 } 6592 6593 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6594 { { "w31" }, "wsp" }, 6595 { { "x29" }, "fp" }, 6596 { { "x30" }, "lr" }, 6597 { { "x31" }, "sp" }, 6598 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6599 // don't want to substitute one of these for a different-sized one. 6600 }; 6601 6602 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6603 return llvm::makeArrayRef(GCCRegAliases); 6604 } 6605 6606 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6607 #define BUILTIN(ID, TYPE, ATTRS) \ 6608 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6609 #include "clang/Basic/BuiltinsNEON.def" 6610 6611 #define BUILTIN(ID, TYPE, ATTRS) \ 6612 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6613 #include "clang/Basic/BuiltinsAArch64.def" 6614 }; 6615 6616 class AArch64leTargetInfo : public AArch64TargetInfo { 6617 void setDataLayout() override { 6618 if (getTriple().isOSBinFormatMachO()) 6619 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6620 else 6621 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6622 } 6623 6624 public: 6625 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6626 : AArch64TargetInfo(Triple, Opts) { 6627 } 6628 void getTargetDefines(const LangOptions &Opts, 6629 MacroBuilder &Builder) const override { 6630 Builder.defineMacro("__AARCH64EL__"); 6631 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6632 } 6633 }; 6634 6635 class MicrosoftARM64TargetInfo 6636 : public WindowsTargetInfo<AArch64leTargetInfo> { 6637 const llvm::Triple Triple; 6638 6639 public: 6640 MicrosoftARM64TargetInfo(const llvm::Triple &Triple, 6641 const TargetOptions &Opts) 6642 : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) { 6643 WCharType = UnsignedShort; 6644 SizeType = UnsignedLongLong; 6645 TheCXXABI.set(TargetCXXABI::Microsoft); 6646 } 6647 6648 void setDataLayout() override { 6649 resetDataLayout("e-m:w-i64:64-i128:128-n32:64-S128"); 6650 } 6651 6652 void getVisualStudioDefines(const LangOptions &Opts, 6653 MacroBuilder &Builder) const { 6654 WindowsTargetInfo<AArch64leTargetInfo>::getVisualStudioDefines(Opts, 6655 Builder); 6656 Builder.defineMacro("_WIN32", "1"); 6657 Builder.defineMacro("_WIN64", "1"); 6658 Builder.defineMacro("_M_ARM64", "1"); 6659 } 6660 6661 void getTargetDefines(const LangOptions &Opts, 6662 MacroBuilder &Builder) const override { 6663 WindowsTargetInfo::getTargetDefines(Opts, Builder); 6664 getVisualStudioDefines(Opts, Builder); 6665 } 6666 6667 BuiltinVaListKind getBuiltinVaListKind() const override { 6668 return TargetInfo::CharPtrBuiltinVaList; 6669 } 6670 }; 6671 6672 class AArch64beTargetInfo : public AArch64TargetInfo { 6673 void setDataLayout() override { 6674 assert(!getTriple().isOSBinFormatMachO()); 6675 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6676 } 6677 6678 public: 6679 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6680 : AArch64TargetInfo(Triple, Opts) {} 6681 void getTargetDefines(const LangOptions &Opts, 6682 MacroBuilder &Builder) const override { 6683 Builder.defineMacro("__AARCH64EB__"); 6684 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6685 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6686 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6687 } 6688 }; 6689 6690 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6691 protected: 6692 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6693 MacroBuilder &Builder) const override { 6694 Builder.defineMacro("__AARCH64_SIMD__"); 6695 Builder.defineMacro("__ARM64_ARCH_8__"); 6696 Builder.defineMacro("__ARM_NEON__"); 6697 Builder.defineMacro("__LITTLE_ENDIAN__"); 6698 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6699 Builder.defineMacro("__arm64", "1"); 6700 Builder.defineMacro("__arm64__", "1"); 6701 6702 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6703 } 6704 6705 public: 6706 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6707 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6708 Int64Type = SignedLongLong; 6709 WCharType = SignedInt; 6710 UseSignedCharForObjCBool = false; 6711 6712 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6713 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6714 6715 TheCXXABI.set(TargetCXXABI::iOS64); 6716 } 6717 6718 BuiltinVaListKind getBuiltinVaListKind() const override { 6719 return TargetInfo::CharPtrBuiltinVaList; 6720 } 6721 }; 6722 6723 // Hexagon abstract base class 6724 class HexagonTargetInfo : public TargetInfo { 6725 static const Builtin::Info BuiltinInfo[]; 6726 static const char * const GCCRegNames[]; 6727 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6728 std::string CPU; 6729 bool HasHVX, HasHVXDouble; 6730 bool UseLongCalls; 6731 6732 public: 6733 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6734 : TargetInfo(Triple) { 6735 // Specify the vector alignment explicitly. For v512x1, the calculated 6736 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6737 // the required minimum of 64 bytes. 6738 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6739 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6740 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6741 SizeType = UnsignedInt; 6742 PtrDiffType = SignedInt; 6743 IntPtrType = SignedInt; 6744 6745 // {} in inline assembly are packet specifiers, not assembly variant 6746 // specifiers. 6747 NoAsmVariants = true; 6748 6749 LargeArrayMinWidth = 64; 6750 LargeArrayAlign = 64; 6751 UseBitFieldTypeAlignment = true; 6752 ZeroLengthBitfieldBoundary = 32; 6753 HasHVX = HasHVXDouble = false; 6754 UseLongCalls = false; 6755 } 6756 6757 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6758 return llvm::makeArrayRef(BuiltinInfo, 6759 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6760 } 6761 6762 bool validateAsmConstraint(const char *&Name, 6763 TargetInfo::ConstraintInfo &Info) const override { 6764 switch (*Name) { 6765 case 'v': 6766 case 'q': 6767 if (HasHVX) { 6768 Info.setAllowsRegister(); 6769 return true; 6770 } 6771 break; 6772 case 's': 6773 // Relocatable constant. 6774 return true; 6775 } 6776 return false; 6777 } 6778 6779 void getTargetDefines(const LangOptions &Opts, 6780 MacroBuilder &Builder) const override; 6781 6782 bool isCLZForZeroUndef() const override { return false; } 6783 6784 bool hasFeature(StringRef Feature) const override { 6785 return llvm::StringSwitch<bool>(Feature) 6786 .Case("hexagon", true) 6787 .Case("hvx", HasHVX) 6788 .Case("hvx-double", HasHVXDouble) 6789 .Case("long-calls", UseLongCalls) 6790 .Default(false); 6791 } 6792 6793 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6794 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6795 const override; 6796 6797 bool handleTargetFeatures(std::vector<std::string> &Features, 6798 DiagnosticsEngine &Diags) override; 6799 6800 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6801 bool Enabled) const override; 6802 6803 BuiltinVaListKind getBuiltinVaListKind() const override { 6804 return TargetInfo::CharPtrBuiltinVaList; 6805 } 6806 ArrayRef<const char *> getGCCRegNames() const override; 6807 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6808 const char *getClobbers() const override { 6809 return ""; 6810 } 6811 6812 static const char *getHexagonCPUSuffix(StringRef Name) { 6813 return llvm::StringSwitch<const char*>(Name) 6814 .Case("hexagonv4", "4") 6815 .Case("hexagonv5", "5") 6816 .Case("hexagonv55", "55") 6817 .Case("hexagonv60", "60") 6818 .Case("hexagonv62", "62") 6819 .Default(nullptr); 6820 } 6821 6822 bool setCPU(const std::string &Name) override { 6823 if (!getHexagonCPUSuffix(Name)) 6824 return false; 6825 CPU = Name; 6826 return true; 6827 } 6828 6829 int getEHDataRegisterNumber(unsigned RegNo) const override { 6830 return RegNo < 2 ? RegNo : -1; 6831 } 6832 }; 6833 6834 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6835 MacroBuilder &Builder) const { 6836 Builder.defineMacro("__qdsp6__", "1"); 6837 Builder.defineMacro("__hexagon__", "1"); 6838 6839 if (CPU == "hexagonv4") { 6840 Builder.defineMacro("__HEXAGON_V4__"); 6841 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6842 if (Opts.HexagonQdsp6Compat) { 6843 Builder.defineMacro("__QDSP6_V4__"); 6844 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6845 } 6846 } else if (CPU == "hexagonv5") { 6847 Builder.defineMacro("__HEXAGON_V5__"); 6848 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6849 if(Opts.HexagonQdsp6Compat) { 6850 Builder.defineMacro("__QDSP6_V5__"); 6851 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6852 } 6853 } else if (CPU == "hexagonv55") { 6854 Builder.defineMacro("__HEXAGON_V55__"); 6855 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6856 Builder.defineMacro("__QDSP6_V55__"); 6857 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6858 } else if (CPU == "hexagonv60") { 6859 Builder.defineMacro("__HEXAGON_V60__"); 6860 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6861 Builder.defineMacro("__QDSP6_V60__"); 6862 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6863 } else if (CPU == "hexagonv62") { 6864 Builder.defineMacro("__HEXAGON_V62__"); 6865 Builder.defineMacro("__HEXAGON_ARCH__", "62"); 6866 } 6867 6868 if (hasFeature("hvx")) { 6869 Builder.defineMacro("__HVX__"); 6870 if (hasFeature("hvx-double")) 6871 Builder.defineMacro("__HVXDBL__"); 6872 } 6873 } 6874 6875 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6876 DiagnosticsEngine &Diags, StringRef CPU, 6877 const std::vector<std::string> &FeaturesVec) const { 6878 // Default for v60: -hvx, -hvx-double. 6879 Features["hvx"] = false; 6880 Features["hvx-double"] = false; 6881 Features["long-calls"] = false; 6882 6883 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6884 } 6885 6886 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6887 DiagnosticsEngine &Diags) { 6888 for (auto &F : Features) { 6889 if (F == "+hvx") 6890 HasHVX = true; 6891 else if (F == "-hvx") 6892 HasHVX = HasHVXDouble = false; 6893 else if (F == "+hvx-double") 6894 HasHVX = HasHVXDouble = true; 6895 else if (F == "-hvx-double") 6896 HasHVXDouble = false; 6897 6898 if (F == "+long-calls") 6899 UseLongCalls = true; 6900 else if (F == "-long-calls") 6901 UseLongCalls = false; 6902 } 6903 return true; 6904 } 6905 6906 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6907 StringRef Name, bool Enabled) const { 6908 if (Enabled) { 6909 if (Name == "hvx-double") 6910 Features["hvx"] = true; 6911 } else { 6912 if (Name == "hvx") 6913 Features["hvx-double"] = false; 6914 } 6915 Features[Name] = Enabled; 6916 } 6917 6918 const char *const HexagonTargetInfo::GCCRegNames[] = { 6919 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6920 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6921 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6922 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6923 "p0", "p1", "p2", "p3", 6924 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6925 }; 6926 6927 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6928 return llvm::makeArrayRef(GCCRegNames); 6929 } 6930 6931 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6932 { { "sp" }, "r29" }, 6933 { { "fp" }, "r30" }, 6934 { { "lr" }, "r31" }, 6935 }; 6936 6937 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6938 return llvm::makeArrayRef(GCCRegAliases); 6939 } 6940 6941 6942 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6943 #define BUILTIN(ID, TYPE, ATTRS) \ 6944 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6945 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6946 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6947 #include "clang/Basic/BuiltinsHexagon.def" 6948 }; 6949 6950 class LanaiTargetInfo : public TargetInfo { 6951 // Class for Lanai (32-bit). 6952 // The CPU profiles supported by the Lanai backend 6953 enum CPUKind { 6954 CK_NONE, 6955 CK_V11, 6956 } CPU; 6957 6958 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6959 static const char *const GCCRegNames[]; 6960 6961 public: 6962 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6963 : TargetInfo(Triple) { 6964 // Description string has to be kept in sync with backend. 6965 resetDataLayout("E" // Big endian 6966 "-m:e" // ELF name manging 6967 "-p:32:32" // 32 bit pointers, 32 bit aligned 6968 "-i64:64" // 64 bit integers, 64 bit aligned 6969 "-a:0:32" // 32 bit alignment of objects of aggregate type 6970 "-n32" // 32 bit native integer width 6971 "-S64" // 64 bit natural stack alignment 6972 ); 6973 6974 // Setting RegParmMax equal to what mregparm was set to in the old 6975 // toolchain 6976 RegParmMax = 4; 6977 6978 // Set the default CPU to V11 6979 CPU = CK_V11; 6980 6981 // Temporary approach to make everything at least word-aligned and allow for 6982 // safely casting between pointers with different alignment requirements. 6983 // TODO: Remove this when there are no more cast align warnings on the 6984 // firmware. 6985 MinGlobalAlign = 32; 6986 } 6987 6988 void getTargetDefines(const LangOptions &Opts, 6989 MacroBuilder &Builder) const override { 6990 // Define __lanai__ when building for target lanai. 6991 Builder.defineMacro("__lanai__"); 6992 6993 // Set define for the CPU specified. 6994 switch (CPU) { 6995 case CK_V11: 6996 Builder.defineMacro("__LANAI_V11__"); 6997 break; 6998 case CK_NONE: 6999 llvm_unreachable("Unhandled target CPU"); 7000 } 7001 } 7002 7003 bool setCPU(const std::string &Name) override { 7004 CPU = llvm::StringSwitch<CPUKind>(Name) 7005 .Case("v11", CK_V11) 7006 .Default(CK_NONE); 7007 7008 return CPU != CK_NONE; 7009 } 7010 7011 bool hasFeature(StringRef Feature) const override { 7012 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 7013 } 7014 7015 ArrayRef<const char *> getGCCRegNames() const override; 7016 7017 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7018 7019 BuiltinVaListKind getBuiltinVaListKind() const override { 7020 return TargetInfo::VoidPtrBuiltinVaList; 7021 } 7022 7023 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7024 7025 bool validateAsmConstraint(const char *&Name, 7026 TargetInfo::ConstraintInfo &info) const override { 7027 return false; 7028 } 7029 7030 const char *getClobbers() const override { return ""; } 7031 }; 7032 7033 const char *const LanaiTargetInfo::GCCRegNames[] = { 7034 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 7035 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 7036 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 7037 7038 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 7039 return llvm::makeArrayRef(GCCRegNames); 7040 } 7041 7042 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 7043 {{"pc"}, "r2"}, 7044 {{"sp"}, "r4"}, 7045 {{"fp"}, "r5"}, 7046 {{"rv"}, "r8"}, 7047 {{"rr1"}, "r10"}, 7048 {{"rr2"}, "r11"}, 7049 {{"rca"}, "r15"}, 7050 }; 7051 7052 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 7053 return llvm::makeArrayRef(GCCRegAliases); 7054 } 7055 7056 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 7057 class SparcTargetInfo : public TargetInfo { 7058 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 7059 static const char * const GCCRegNames[]; 7060 bool SoftFloat; 7061 public: 7062 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7063 : TargetInfo(Triple), SoftFloat(false) {} 7064 7065 int getEHDataRegisterNumber(unsigned RegNo) const override { 7066 if (RegNo == 0) return 24; 7067 if (RegNo == 1) return 25; 7068 return -1; 7069 } 7070 7071 bool handleTargetFeatures(std::vector<std::string> &Features, 7072 DiagnosticsEngine &Diags) override { 7073 // Check if software floating point is enabled 7074 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 7075 if (Feature != Features.end()) { 7076 SoftFloat = true; 7077 } 7078 return true; 7079 } 7080 void getTargetDefines(const LangOptions &Opts, 7081 MacroBuilder &Builder) const override { 7082 DefineStd(Builder, "sparc", Opts); 7083 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7084 7085 if (SoftFloat) 7086 Builder.defineMacro("SOFT_FLOAT", "1"); 7087 } 7088 7089 bool hasFeature(StringRef Feature) const override { 7090 return llvm::StringSwitch<bool>(Feature) 7091 .Case("softfloat", SoftFloat) 7092 .Case("sparc", true) 7093 .Default(false); 7094 } 7095 7096 bool hasSjLjLowering() const override { 7097 return true; 7098 } 7099 7100 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7101 // FIXME: Implement! 7102 return None; 7103 } 7104 BuiltinVaListKind getBuiltinVaListKind() const override { 7105 return TargetInfo::VoidPtrBuiltinVaList; 7106 } 7107 ArrayRef<const char *> getGCCRegNames() const override; 7108 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7109 bool validateAsmConstraint(const char *&Name, 7110 TargetInfo::ConstraintInfo &info) const override { 7111 // FIXME: Implement! 7112 switch (*Name) { 7113 case 'I': // Signed 13-bit constant 7114 case 'J': // Zero 7115 case 'K': // 32-bit constant with the low 12 bits clear 7116 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 7117 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 7118 case 'N': // Same as 'K' but zext (required for SIMode) 7119 case 'O': // The constant 4096 7120 return true; 7121 7122 case 'f': 7123 case 'e': 7124 info.setAllowsRegister(); 7125 return true; 7126 } 7127 return false; 7128 } 7129 const char *getClobbers() const override { 7130 // FIXME: Implement! 7131 return ""; 7132 } 7133 7134 // No Sparc V7 for now, the backend doesn't support it anyway. 7135 enum CPUKind { 7136 CK_GENERIC, 7137 CK_V8, 7138 CK_SUPERSPARC, 7139 CK_SPARCLITE, 7140 CK_F934, 7141 CK_HYPERSPARC, 7142 CK_SPARCLITE86X, 7143 CK_SPARCLET, 7144 CK_TSC701, 7145 CK_V9, 7146 CK_ULTRASPARC, 7147 CK_ULTRASPARC3, 7148 CK_NIAGARA, 7149 CK_NIAGARA2, 7150 CK_NIAGARA3, 7151 CK_NIAGARA4, 7152 CK_MYRIAD2100, 7153 CK_MYRIAD2150, 7154 CK_MYRIAD2450, 7155 CK_LEON2, 7156 CK_LEON2_AT697E, 7157 CK_LEON2_AT697F, 7158 CK_LEON3, 7159 CK_LEON3_UT699, 7160 CK_LEON3_GR712RC, 7161 CK_LEON4, 7162 CK_LEON4_GR740 7163 } CPU = CK_GENERIC; 7164 7165 enum CPUGeneration { 7166 CG_V8, 7167 CG_V9, 7168 }; 7169 7170 CPUGeneration getCPUGeneration(CPUKind Kind) const { 7171 switch (Kind) { 7172 case CK_GENERIC: 7173 case CK_V8: 7174 case CK_SUPERSPARC: 7175 case CK_SPARCLITE: 7176 case CK_F934: 7177 case CK_HYPERSPARC: 7178 case CK_SPARCLITE86X: 7179 case CK_SPARCLET: 7180 case CK_TSC701: 7181 case CK_MYRIAD2100: 7182 case CK_MYRIAD2150: 7183 case CK_MYRIAD2450: 7184 case CK_LEON2: 7185 case CK_LEON2_AT697E: 7186 case CK_LEON2_AT697F: 7187 case CK_LEON3: 7188 case CK_LEON3_UT699: 7189 case CK_LEON3_GR712RC: 7190 case CK_LEON4: 7191 case CK_LEON4_GR740: 7192 return CG_V8; 7193 case CK_V9: 7194 case CK_ULTRASPARC: 7195 case CK_ULTRASPARC3: 7196 case CK_NIAGARA: 7197 case CK_NIAGARA2: 7198 case CK_NIAGARA3: 7199 case CK_NIAGARA4: 7200 return CG_V9; 7201 } 7202 llvm_unreachable("Unexpected CPU kind"); 7203 } 7204 7205 CPUKind getCPUKind(StringRef Name) const { 7206 return llvm::StringSwitch<CPUKind>(Name) 7207 .Case("v8", CK_V8) 7208 .Case("supersparc", CK_SUPERSPARC) 7209 .Case("sparclite", CK_SPARCLITE) 7210 .Case("f934", CK_F934) 7211 .Case("hypersparc", CK_HYPERSPARC) 7212 .Case("sparclite86x", CK_SPARCLITE86X) 7213 .Case("sparclet", CK_SPARCLET) 7214 .Case("tsc701", CK_TSC701) 7215 .Case("v9", CK_V9) 7216 .Case("ultrasparc", CK_ULTRASPARC) 7217 .Case("ultrasparc3", CK_ULTRASPARC3) 7218 .Case("niagara", CK_NIAGARA) 7219 .Case("niagara2", CK_NIAGARA2) 7220 .Case("niagara3", CK_NIAGARA3) 7221 .Case("niagara4", CK_NIAGARA4) 7222 .Case("ma2100", CK_MYRIAD2100) 7223 .Case("ma2150", CK_MYRIAD2150) 7224 .Case("ma2450", CK_MYRIAD2450) 7225 // FIXME: the myriad2[.n] spellings are obsolete, 7226 // but a grace period is needed to allow updating dependent builds. 7227 .Case("myriad2", CK_MYRIAD2100) 7228 .Case("myriad2.1", CK_MYRIAD2100) 7229 .Case("myriad2.2", CK_MYRIAD2150) 7230 .Case("leon2", CK_LEON2) 7231 .Case("at697e", CK_LEON2_AT697E) 7232 .Case("at697f", CK_LEON2_AT697F) 7233 .Case("leon3", CK_LEON3) 7234 .Case("ut699", CK_LEON3_UT699) 7235 .Case("gr712rc", CK_LEON3_GR712RC) 7236 .Case("leon4", CK_LEON4) 7237 .Case("gr740", CK_LEON4_GR740) 7238 .Default(CK_GENERIC); 7239 } 7240 7241 bool setCPU(const std::string &Name) override { 7242 CPU = getCPUKind(Name); 7243 return CPU != CK_GENERIC; 7244 } 7245 }; 7246 7247 const char * const SparcTargetInfo::GCCRegNames[] = { 7248 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7249 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7250 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 7251 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 7252 }; 7253 7254 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 7255 return llvm::makeArrayRef(GCCRegNames); 7256 } 7257 7258 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 7259 { { "g0" }, "r0" }, 7260 { { "g1" }, "r1" }, 7261 { { "g2" }, "r2" }, 7262 { { "g3" }, "r3" }, 7263 { { "g4" }, "r4" }, 7264 { { "g5" }, "r5" }, 7265 { { "g6" }, "r6" }, 7266 { { "g7" }, "r7" }, 7267 { { "o0" }, "r8" }, 7268 { { "o1" }, "r9" }, 7269 { { "o2" }, "r10" }, 7270 { { "o3" }, "r11" }, 7271 { { "o4" }, "r12" }, 7272 { { "o5" }, "r13" }, 7273 { { "o6", "sp" }, "r14" }, 7274 { { "o7" }, "r15" }, 7275 { { "l0" }, "r16" }, 7276 { { "l1" }, "r17" }, 7277 { { "l2" }, "r18" }, 7278 { { "l3" }, "r19" }, 7279 { { "l4" }, "r20" }, 7280 { { "l5" }, "r21" }, 7281 { { "l6" }, "r22" }, 7282 { { "l7" }, "r23" }, 7283 { { "i0" }, "r24" }, 7284 { { "i1" }, "r25" }, 7285 { { "i2" }, "r26" }, 7286 { { "i3" }, "r27" }, 7287 { { "i4" }, "r28" }, 7288 { { "i5" }, "r29" }, 7289 { { "i6", "fp" }, "r30" }, 7290 { { "i7" }, "r31" }, 7291 }; 7292 7293 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 7294 return llvm::makeArrayRef(GCCRegAliases); 7295 } 7296 7297 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 7298 class SparcV8TargetInfo : public SparcTargetInfo { 7299 public: 7300 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7301 : SparcTargetInfo(Triple, Opts) { 7302 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7303 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 7304 switch (getTriple().getOS()) { 7305 default: 7306 SizeType = UnsignedInt; 7307 IntPtrType = SignedInt; 7308 PtrDiffType = SignedInt; 7309 break; 7310 case llvm::Triple::NetBSD: 7311 case llvm::Triple::OpenBSD: 7312 SizeType = UnsignedLong; 7313 IntPtrType = SignedLong; 7314 PtrDiffType = SignedLong; 7315 break; 7316 } 7317 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 7318 // on up to 64 bits. 7319 MaxAtomicPromoteWidth = 64; 7320 MaxAtomicInlineWidth = 32; 7321 } 7322 7323 void getTargetDefines(const LangOptions &Opts, 7324 MacroBuilder &Builder) const override { 7325 SparcTargetInfo::getTargetDefines(Opts, Builder); 7326 switch (getCPUGeneration(CPU)) { 7327 case CG_V8: 7328 Builder.defineMacro("__sparcv8"); 7329 if (getTriple().getOS() != llvm::Triple::Solaris) 7330 Builder.defineMacro("__sparcv8__"); 7331 break; 7332 case CG_V9: 7333 Builder.defineMacro("__sparcv9"); 7334 if (getTriple().getOS() != llvm::Triple::Solaris) { 7335 Builder.defineMacro("__sparcv9__"); 7336 Builder.defineMacro("__sparc_v9__"); 7337 } 7338 break; 7339 } 7340 if (getTriple().getVendor() == llvm::Triple::Myriad) { 7341 std::string MyriadArchValue, Myriad2Value; 7342 Builder.defineMacro("__sparc_v8__"); 7343 Builder.defineMacro("__leon__"); 7344 switch (CPU) { 7345 case CK_MYRIAD2150: 7346 MyriadArchValue = "__ma2150"; 7347 Myriad2Value = "2"; 7348 break; 7349 case CK_MYRIAD2450: 7350 MyriadArchValue = "__ma2450"; 7351 Myriad2Value = "2"; 7352 break; 7353 default: 7354 MyriadArchValue = "__ma2100"; 7355 Myriad2Value = "1"; 7356 break; 7357 } 7358 Builder.defineMacro(MyriadArchValue, "1"); 7359 Builder.defineMacro(MyriadArchValue+"__", "1"); 7360 Builder.defineMacro("__myriad2__", Myriad2Value); 7361 Builder.defineMacro("__myriad2", Myriad2Value); 7362 } 7363 } 7364 7365 bool hasSjLjLowering() const override { 7366 return true; 7367 } 7368 }; 7369 7370 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 7371 class SparcV8elTargetInfo : public SparcV8TargetInfo { 7372 public: 7373 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7374 : SparcV8TargetInfo(Triple, Opts) { 7375 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7376 } 7377 }; 7378 7379 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 7380 class SparcV9TargetInfo : public SparcTargetInfo { 7381 public: 7382 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7383 : SparcTargetInfo(Triple, Opts) { 7384 // FIXME: Support Sparc quad-precision long double? 7385 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 7386 // This is an LP64 platform. 7387 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7388 7389 // OpenBSD uses long long for int64_t and intmax_t. 7390 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7391 IntMaxType = SignedLongLong; 7392 else 7393 IntMaxType = SignedLong; 7394 Int64Type = IntMaxType; 7395 7396 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7397 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7398 LongDoubleWidth = 128; 7399 LongDoubleAlign = 128; 7400 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7401 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7402 } 7403 7404 void getTargetDefines(const LangOptions &Opts, 7405 MacroBuilder &Builder) const override { 7406 SparcTargetInfo::getTargetDefines(Opts, Builder); 7407 Builder.defineMacro("__sparcv9"); 7408 Builder.defineMacro("__arch64__"); 7409 // Solaris doesn't need these variants, but the BSDs do. 7410 if (getTriple().getOS() != llvm::Triple::Solaris) { 7411 Builder.defineMacro("__sparc64__"); 7412 Builder.defineMacro("__sparc_v9__"); 7413 Builder.defineMacro("__sparcv9__"); 7414 } 7415 } 7416 7417 bool setCPU(const std::string &Name) override { 7418 if (!SparcTargetInfo::setCPU(Name)) 7419 return false; 7420 return getCPUGeneration(CPU) == CG_V9; 7421 } 7422 }; 7423 7424 class SystemZTargetInfo : public TargetInfo { 7425 static const Builtin::Info BuiltinInfo[]; 7426 static const char *const GCCRegNames[]; 7427 std::string CPU; 7428 int ISARevision; 7429 bool HasTransactionalExecution; 7430 bool HasVector; 7431 7432 public: 7433 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7434 : TargetInfo(Triple), CPU("z10"), ISARevision(8), 7435 HasTransactionalExecution(false), HasVector(false) { 7436 IntMaxType = SignedLong; 7437 Int64Type = SignedLong; 7438 TLSSupported = true; 7439 IntWidth = IntAlign = 32; 7440 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7441 PointerWidth = PointerAlign = 64; 7442 LongDoubleWidth = 128; 7443 LongDoubleAlign = 64; 7444 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7445 DefaultAlignForAttributeAligned = 64; 7446 MinGlobalAlign = 16; 7447 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7448 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7449 } 7450 void getTargetDefines(const LangOptions &Opts, 7451 MacroBuilder &Builder) const override { 7452 Builder.defineMacro("__s390__"); 7453 Builder.defineMacro("__s390x__"); 7454 Builder.defineMacro("__zarch__"); 7455 Builder.defineMacro("__LONG_DOUBLE_128__"); 7456 7457 Builder.defineMacro("__ARCH__", Twine(ISARevision)); 7458 7459 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7460 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7461 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7462 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7463 7464 if (HasTransactionalExecution) 7465 Builder.defineMacro("__HTM__"); 7466 if (HasVector) 7467 Builder.defineMacro("__VX__"); 7468 if (Opts.ZVector) 7469 Builder.defineMacro("__VEC__", "10301"); 7470 } 7471 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7472 return llvm::makeArrayRef(BuiltinInfo, 7473 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7474 } 7475 7476 ArrayRef<const char *> getGCCRegNames() const override; 7477 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7478 // No aliases. 7479 return None; 7480 } 7481 bool validateAsmConstraint(const char *&Name, 7482 TargetInfo::ConstraintInfo &info) const override; 7483 const char *getClobbers() const override { 7484 // FIXME: Is this really right? 7485 return ""; 7486 } 7487 BuiltinVaListKind getBuiltinVaListKind() const override { 7488 return TargetInfo::SystemZBuiltinVaList; 7489 } 7490 int getISARevision(const StringRef &Name) const { 7491 return llvm::StringSwitch<int>(Name) 7492 .Cases("arch8", "z10", 8) 7493 .Cases("arch9", "z196", 9) 7494 .Cases("arch10", "zEC12", 10) 7495 .Cases("arch11", "z13", 11) 7496 .Default(-1); 7497 } 7498 bool setCPU(const std::string &Name) override { 7499 CPU = Name; 7500 ISARevision = getISARevision(CPU); 7501 return ISARevision != -1; 7502 } 7503 bool 7504 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7505 StringRef CPU, 7506 const std::vector<std::string> &FeaturesVec) const override { 7507 int ISARevision = getISARevision(CPU); 7508 if (ISARevision >= 10) 7509 Features["transactional-execution"] = true; 7510 if (ISARevision >= 11) 7511 Features["vector"] = true; 7512 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7513 } 7514 7515 bool handleTargetFeatures(std::vector<std::string> &Features, 7516 DiagnosticsEngine &Diags) override { 7517 HasTransactionalExecution = false; 7518 HasVector = false; 7519 for (const auto &Feature : Features) { 7520 if (Feature == "+transactional-execution") 7521 HasTransactionalExecution = true; 7522 else if (Feature == "+vector") 7523 HasVector = true; 7524 } 7525 // If we use the vector ABI, vector types are 64-bit aligned. 7526 if (HasVector) { 7527 MaxVectorAlign = 64; 7528 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7529 "-v128:64-a:8:16-n32:64"); 7530 } 7531 return true; 7532 } 7533 7534 bool hasFeature(StringRef Feature) const override { 7535 return llvm::StringSwitch<bool>(Feature) 7536 .Case("systemz", true) 7537 .Case("arch8", ISARevision >= 8) 7538 .Case("arch9", ISARevision >= 9) 7539 .Case("arch10", ISARevision >= 10) 7540 .Case("arch11", ISARevision >= 11) 7541 .Case("htm", HasTransactionalExecution) 7542 .Case("vx", HasVector) 7543 .Default(false); 7544 } 7545 7546 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7547 switch (CC) { 7548 case CC_C: 7549 case CC_Swift: 7550 case CC_OpenCLKernel: 7551 return CCCR_OK; 7552 default: 7553 return CCCR_Warning; 7554 } 7555 } 7556 7557 StringRef getABI() const override { 7558 if (HasVector) 7559 return "vector"; 7560 return ""; 7561 } 7562 7563 bool useFloat128ManglingForLongDouble() const override { 7564 return true; 7565 } 7566 }; 7567 7568 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7569 #define BUILTIN(ID, TYPE, ATTRS) \ 7570 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7571 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7572 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7573 #include "clang/Basic/BuiltinsSystemZ.def" 7574 }; 7575 7576 const char *const SystemZTargetInfo::GCCRegNames[] = { 7577 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7578 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7579 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7580 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7581 }; 7582 7583 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7584 return llvm::makeArrayRef(GCCRegNames); 7585 } 7586 7587 bool SystemZTargetInfo:: 7588 validateAsmConstraint(const char *&Name, 7589 TargetInfo::ConstraintInfo &Info) const { 7590 switch (*Name) { 7591 default: 7592 return false; 7593 7594 case 'a': // Address register 7595 case 'd': // Data register (equivalent to 'r') 7596 case 'f': // Floating-point register 7597 Info.setAllowsRegister(); 7598 return true; 7599 7600 case 'I': // Unsigned 8-bit constant 7601 case 'J': // Unsigned 12-bit constant 7602 case 'K': // Signed 16-bit constant 7603 case 'L': // Signed 20-bit displacement (on all targets we support) 7604 case 'M': // 0x7fffffff 7605 return true; 7606 7607 case 'Q': // Memory with base and unsigned 12-bit displacement 7608 case 'R': // Likewise, plus an index 7609 case 'S': // Memory with base and signed 20-bit displacement 7610 case 'T': // Likewise, plus an index 7611 Info.setAllowsMemory(); 7612 return true; 7613 } 7614 } 7615 7616 class MSP430TargetInfo : public TargetInfo { 7617 static const char *const GCCRegNames[]; 7618 7619 public: 7620 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7621 : TargetInfo(Triple) { 7622 TLSSupported = false; 7623 IntWidth = 16; 7624 IntAlign = 16; 7625 LongWidth = 32; 7626 LongLongWidth = 64; 7627 LongAlign = LongLongAlign = 16; 7628 PointerWidth = 16; 7629 PointerAlign = 16; 7630 SuitableAlign = 16; 7631 SizeType = UnsignedInt; 7632 IntMaxType = SignedLongLong; 7633 IntPtrType = SignedInt; 7634 PtrDiffType = SignedInt; 7635 SigAtomicType = SignedLong; 7636 resetDataLayout("e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16"); 7637 } 7638 void getTargetDefines(const LangOptions &Opts, 7639 MacroBuilder &Builder) const override { 7640 Builder.defineMacro("MSP430"); 7641 Builder.defineMacro("__MSP430__"); 7642 // FIXME: defines for different 'flavours' of MCU 7643 } 7644 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7645 // FIXME: Implement. 7646 return None; 7647 } 7648 bool hasFeature(StringRef Feature) const override { 7649 return Feature == "msp430"; 7650 } 7651 ArrayRef<const char *> getGCCRegNames() const override; 7652 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7653 // No aliases. 7654 return None; 7655 } 7656 bool validateAsmConstraint(const char *&Name, 7657 TargetInfo::ConstraintInfo &info) const override { 7658 // FIXME: implement 7659 switch (*Name) { 7660 case 'K': // the constant 1 7661 case 'L': // constant -1^20 .. 1^19 7662 case 'M': // constant 1-4: 7663 return true; 7664 } 7665 // No target constraints for now. 7666 return false; 7667 } 7668 const char *getClobbers() const override { 7669 // FIXME: Is this really right? 7670 return ""; 7671 } 7672 BuiltinVaListKind getBuiltinVaListKind() const override { 7673 // FIXME: implement 7674 return TargetInfo::CharPtrBuiltinVaList; 7675 } 7676 }; 7677 7678 const char *const MSP430TargetInfo::GCCRegNames[] = { 7679 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7680 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7681 7682 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7683 return llvm::makeArrayRef(GCCRegNames); 7684 } 7685 7686 // LLVM and Clang cannot be used directly to output native binaries for 7687 // target, but is used to compile C code to llvm bitcode with correct 7688 // type and alignment information. 7689 // 7690 // TCE uses the llvm bitcode as input and uses it for generating customized 7691 // target processor and program binary. TCE co-design environment is 7692 // publicly available in http://tce.cs.tut.fi 7693 7694 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7695 0, // Default 7696 3, // opencl_global 7697 4, // opencl_local 7698 5, // opencl_constant 7699 // FIXME: generic has to be added to the target 7700 0, // opencl_generic 7701 0, // cuda_device 7702 0, // cuda_constant 7703 0 // cuda_shared 7704 }; 7705 7706 class TCETargetInfo : public TargetInfo { 7707 public: 7708 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7709 : TargetInfo(Triple) { 7710 TLSSupported = false; 7711 IntWidth = 32; 7712 LongWidth = LongLongWidth = 32; 7713 PointerWidth = 32; 7714 IntAlign = 32; 7715 LongAlign = LongLongAlign = 32; 7716 PointerAlign = 32; 7717 SuitableAlign = 32; 7718 SizeType = UnsignedInt; 7719 IntMaxType = SignedLong; 7720 IntPtrType = SignedInt; 7721 PtrDiffType = SignedInt; 7722 FloatWidth = 32; 7723 FloatAlign = 32; 7724 DoubleWidth = 32; 7725 DoubleAlign = 32; 7726 LongDoubleWidth = 32; 7727 LongDoubleAlign = 32; 7728 FloatFormat = &llvm::APFloat::IEEEsingle(); 7729 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7730 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7731 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7732 "i16:16:32-i32:32:32-i64:32:32-" 7733 "f32:32:32-f64:32:32-v64:32:32-" 7734 "v128:32:32-v256:32:32-v512:32:32-" 7735 "v1024:32:32-a0:0:32-n32"); 7736 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7737 UseAddrSpaceMapMangling = true; 7738 } 7739 7740 void getTargetDefines(const LangOptions &Opts, 7741 MacroBuilder &Builder) const override { 7742 DefineStd(Builder, "tce", Opts); 7743 Builder.defineMacro("__TCE__"); 7744 Builder.defineMacro("__TCE_V1__"); 7745 } 7746 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7747 7748 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7749 const char *getClobbers() const override { return ""; } 7750 BuiltinVaListKind getBuiltinVaListKind() const override { 7751 return TargetInfo::VoidPtrBuiltinVaList; 7752 } 7753 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7754 bool validateAsmConstraint(const char *&Name, 7755 TargetInfo::ConstraintInfo &info) const override { 7756 return true; 7757 } 7758 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7759 return None; 7760 } 7761 }; 7762 7763 class TCELETargetInfo : public TCETargetInfo { 7764 public: 7765 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7766 : TCETargetInfo(Triple, Opts) { 7767 BigEndian = false; 7768 7769 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7770 "i16:16:32-i32:32:32-i64:32:32-" 7771 "f32:32:32-f64:32:32-v64:32:32-" 7772 "v128:32:32-v256:32:32-v512:32:32-" 7773 "v1024:32:32-a0:0:32-n32"); 7774 7775 } 7776 7777 virtual void getTargetDefines(const LangOptions &Opts, 7778 MacroBuilder &Builder) const { 7779 DefineStd(Builder, "tcele", Opts); 7780 Builder.defineMacro("__TCE__"); 7781 Builder.defineMacro("__TCE_V1__"); 7782 Builder.defineMacro("__TCELE__"); 7783 Builder.defineMacro("__TCELE_V1__"); 7784 } 7785 7786 }; 7787 7788 class BPFTargetInfo : public TargetInfo { 7789 public: 7790 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7791 : TargetInfo(Triple) { 7792 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7793 SizeType = UnsignedLong; 7794 PtrDiffType = SignedLong; 7795 IntPtrType = SignedLong; 7796 IntMaxType = SignedLong; 7797 Int64Type = SignedLong; 7798 RegParmMax = 5; 7799 if (Triple.getArch() == llvm::Triple::bpfeb) { 7800 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7801 } else { 7802 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7803 } 7804 MaxAtomicPromoteWidth = 64; 7805 MaxAtomicInlineWidth = 64; 7806 TLSSupported = false; 7807 } 7808 void getTargetDefines(const LangOptions &Opts, 7809 MacroBuilder &Builder) const override { 7810 DefineStd(Builder, "bpf", Opts); 7811 Builder.defineMacro("__BPF__"); 7812 } 7813 bool hasFeature(StringRef Feature) const override { 7814 return Feature == "bpf"; 7815 } 7816 7817 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7818 const char *getClobbers() const override { 7819 return ""; 7820 } 7821 BuiltinVaListKind getBuiltinVaListKind() const override { 7822 return TargetInfo::VoidPtrBuiltinVaList; 7823 } 7824 ArrayRef<const char *> getGCCRegNames() const override { 7825 return None; 7826 } 7827 bool validateAsmConstraint(const char *&Name, 7828 TargetInfo::ConstraintInfo &info) const override { 7829 return true; 7830 } 7831 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7832 return None; 7833 } 7834 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7835 switch (CC) { 7836 default: 7837 return CCCR_Warning; 7838 case CC_C: 7839 case CC_OpenCLKernel: 7840 return CCCR_OK; 7841 } 7842 } 7843 }; 7844 7845 class Nios2TargetInfo : public TargetInfo { 7846 void setDataLayout() { 7847 if (BigEndian) 7848 resetDataLayout("E-p:32:32:32-i8:8:32-i16:16:32-n32"); 7849 else 7850 resetDataLayout("e-p:32:32:32-i8:8:32-i16:16:32-n32"); 7851 } 7852 7853 static const Builtin::Info BuiltinInfo[]; 7854 std::string CPU; 7855 std::string ABI; 7856 7857 public: 7858 Nios2TargetInfo(const llvm::Triple &triple, const TargetOptions &opts) 7859 : TargetInfo(triple), CPU(opts.CPU), ABI(opts.ABI) { 7860 SizeType = UnsignedInt; 7861 PtrDiffType = SignedInt; 7862 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7863 setDataLayout(); 7864 } 7865 7866 StringRef getABI() const override { return ABI; } 7867 bool setABI(const std::string &Name) override { 7868 if (Name == "o32" || Name == "eabi") { 7869 ABI = Name; 7870 return true; 7871 } 7872 return false; 7873 } 7874 7875 bool setCPU(const std::string &Name) override { 7876 if (Name == "nios2r1" || Name == "nios2r2") { 7877 CPU = Name; 7878 return true; 7879 } 7880 return false; 7881 } 7882 7883 void getTargetDefines(const LangOptions &Opts, 7884 MacroBuilder &Builder) const override { 7885 DefineStd(Builder, "nios2", Opts); 7886 DefineStd(Builder, "NIOS2", Opts); 7887 7888 Builder.defineMacro("__nios2"); 7889 Builder.defineMacro("__NIOS2"); 7890 Builder.defineMacro("__nios2__"); 7891 Builder.defineMacro("__NIOS2__"); 7892 } 7893 7894 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7895 return llvm::makeArrayRef(BuiltinInfo, clang::Nios2::LastTSBuiltin - 7896 Builtin::FirstTSBuiltin); 7897 } 7898 7899 bool isFeatureSupportedByCPU(StringRef Feature, StringRef CPU) const { 7900 const bool isR2 = CPU == "nios2r2"; 7901 return llvm::StringSwitch<bool>(Feature) 7902 .Case("nios2r2mandatory", isR2) 7903 .Case("nios2r2bmx", isR2) 7904 .Case("nios2r2mpx", isR2) 7905 .Case("nios2r2cdx", isR2) 7906 .Default(false); 7907 } 7908 7909 bool initFeatureMap(llvm::StringMap<bool> &Features, 7910 DiagnosticsEngine &Diags, StringRef CPU, 7911 const std::vector<std::string> &FeatureVec) const override { 7912 static const char *allFeatures[] = { 7913 "nios2r2mandatory", "nios2r2bmx", "nios2r2mpx", "nios2r2cdx" 7914 }; 7915 for (const char *feature : allFeatures) { 7916 Features[feature] = isFeatureSupportedByCPU(feature, CPU); 7917 } 7918 return true; 7919 } 7920 7921 bool hasFeature(StringRef Feature) const override { 7922 return isFeatureSupportedByCPU(Feature, CPU); 7923 } 7924 7925 BuiltinVaListKind getBuiltinVaListKind() const override { 7926 return TargetInfo::VoidPtrBuiltinVaList; 7927 } 7928 7929 ArrayRef<const char *> getGCCRegNames() const override { 7930 static const char *const GCCRegNames[] = { 7931 // CPU register names 7932 // Must match second column of GCCRegAliases 7933 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 7934 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", 7935 "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", 7936 "r31", 7937 // Floating point register names 7938 "ctl0", "ctl1", "ctl2", "ctl3", "ctl4", "ctl5", "ctl6", "ctl7", "ctl8", 7939 "ctl9", "ctl10", "ctl11", "ctl12", "ctl13", "ctl14", "ctl15" 7940 }; 7941 return llvm::makeArrayRef(GCCRegNames); 7942 } 7943 7944 bool validateAsmConstraint(const char *&Name, 7945 TargetInfo::ConstraintInfo &Info) const override { 7946 switch (*Name) { 7947 default: 7948 return false; 7949 7950 case 'r': // CPU registers. 7951 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7952 case 'y': // Equivalent to "r", backwards compatibility only. 7953 case 'f': // floating-point registers. 7954 case 'c': // $25 for indirect jumps 7955 case 'l': // lo register 7956 case 'x': // hilo register pair 7957 Info.setAllowsRegister(); 7958 return true; 7959 } 7960 } 7961 7962 const char *getClobbers() const override { return ""; } 7963 7964 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7965 static const TargetInfo::GCCRegAlias aliases[] = { 7966 {{"zero"}, "r0"}, {{"at"}, "r1"}, {{"et"}, "r24"}, 7967 {{"bt"}, "r25"}, {{"gp"}, "r26"}, {{"sp"}, "r27"}, 7968 {{"fp"}, "r28"}, {{"ea"}, "r29"}, {{"ba"}, "r30"}, 7969 {{"ra"}, "r31"}, {{"status"}, "ctl0"}, {{"estatus"}, "ctl1"}, 7970 {{"bstatus"}, "ctl2"}, {{"ienable"}, "ctl3"}, {{"ipending"}, "ctl4"}, 7971 {{"cpuid"}, "ctl5"}, {{"exception"}, "ctl7"}, {{"pteaddr"}, "ctl8"}, 7972 {{"tlbacc"}, "ctl9"}, {{"tlbmisc"}, "ctl10"}, {{"badaddr"}, "ctl12"}, 7973 {{"config"}, "ctl13"}, {{"mpubase"}, "ctl14"}, {{"mpuacc"}, "ctl15"}, 7974 }; 7975 return llvm::makeArrayRef(aliases); 7976 } 7977 }; 7978 7979 const Builtin::Info Nios2TargetInfo::BuiltinInfo[] = { 7980 #define BUILTIN(ID, TYPE, ATTRS) \ 7981 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 7982 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7983 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 7984 #include "clang/Basic/BuiltinsNios2.def" 7985 }; 7986 7987 class MipsTargetInfo : public TargetInfo { 7988 void setDataLayout() { 7989 StringRef Layout; 7990 7991 if (ABI == "o32") 7992 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7993 else if (ABI == "n32") 7994 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7995 else if (ABI == "n64") 7996 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7997 else 7998 llvm_unreachable("Invalid ABI"); 7999 8000 if (BigEndian) 8001 resetDataLayout(("E-" + Layout).str()); 8002 else 8003 resetDataLayout(("e-" + Layout).str()); 8004 } 8005 8006 8007 static const Builtin::Info BuiltinInfo[]; 8008 std::string CPU; 8009 bool IsMips16; 8010 bool IsMicromips; 8011 bool IsNan2008; 8012 bool IsSingleFloat; 8013 bool IsNoABICalls; 8014 bool CanUseBSDABICalls; 8015 enum MipsFloatABI { 8016 HardFloat, SoftFloat 8017 } FloatABI; 8018 enum DspRevEnum { 8019 NoDSP, DSP1, DSP2 8020 } DspRev; 8021 bool HasMSA; 8022 bool DisableMadd4; 8023 8024 protected: 8025 bool HasFP64; 8026 std::string ABI; 8027 8028 public: 8029 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8030 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 8031 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 8032 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 8033 HasMSA(false), DisableMadd4(false), HasFP64(false) { 8034 TheCXXABI.set(TargetCXXABI::GenericMIPS); 8035 8036 setABI((getTriple().getArch() == llvm::Triple::mips || 8037 getTriple().getArch() == llvm::Triple::mipsel) 8038 ? "o32" 8039 : "n64"); 8040 8041 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 8042 8043 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 8044 Triple.getOS() == llvm::Triple::OpenBSD; 8045 } 8046 8047 bool isNaN2008Default() const { 8048 return CPU == "mips32r6" || CPU == "mips64r6"; 8049 } 8050 8051 bool isFP64Default() const { 8052 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 8053 } 8054 8055 bool isNan2008() const override { 8056 return IsNan2008; 8057 } 8058 8059 bool processorSupportsGPR64() const { 8060 return llvm::StringSwitch<bool>(CPU) 8061 .Case("mips3", true) 8062 .Case("mips4", true) 8063 .Case("mips5", true) 8064 .Case("mips64", true) 8065 .Case("mips64r2", true) 8066 .Case("mips64r3", true) 8067 .Case("mips64r5", true) 8068 .Case("mips64r6", true) 8069 .Case("octeon", true) 8070 .Default(false); 8071 return false; 8072 } 8073 8074 StringRef getABI() const override { return ABI; } 8075 bool setABI(const std::string &Name) override { 8076 if (Name == "o32") { 8077 setO32ABITypes(); 8078 ABI = Name; 8079 return true; 8080 } 8081 8082 if (Name == "n32") { 8083 setN32ABITypes(); 8084 ABI = Name; 8085 return true; 8086 } 8087 if (Name == "n64") { 8088 setN64ABITypes(); 8089 ABI = Name; 8090 return true; 8091 } 8092 return false; 8093 } 8094 8095 void setO32ABITypes() { 8096 Int64Type = SignedLongLong; 8097 IntMaxType = Int64Type; 8098 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8099 LongDoubleWidth = LongDoubleAlign = 64; 8100 LongWidth = LongAlign = 32; 8101 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8102 PointerWidth = PointerAlign = 32; 8103 PtrDiffType = SignedInt; 8104 SizeType = UnsignedInt; 8105 SuitableAlign = 64; 8106 } 8107 8108 void setN32N64ABITypes() { 8109 LongDoubleWidth = LongDoubleAlign = 128; 8110 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8111 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 8112 LongDoubleWidth = LongDoubleAlign = 64; 8113 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8114 } 8115 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8116 SuitableAlign = 128; 8117 } 8118 8119 void setN64ABITypes() { 8120 setN32N64ABITypes(); 8121 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 8122 Int64Type = SignedLongLong; 8123 } else { 8124 Int64Type = SignedLong; 8125 } 8126 IntMaxType = Int64Type; 8127 LongWidth = LongAlign = 64; 8128 PointerWidth = PointerAlign = 64; 8129 PtrDiffType = SignedLong; 8130 SizeType = UnsignedLong; 8131 } 8132 8133 void setN32ABITypes() { 8134 setN32N64ABITypes(); 8135 Int64Type = SignedLongLong; 8136 IntMaxType = Int64Type; 8137 LongWidth = LongAlign = 32; 8138 PointerWidth = PointerAlign = 32; 8139 PtrDiffType = SignedInt; 8140 SizeType = UnsignedInt; 8141 } 8142 8143 bool setCPU(const std::string &Name) override { 8144 CPU = Name; 8145 return llvm::StringSwitch<bool>(Name) 8146 .Case("mips1", true) 8147 .Case("mips2", true) 8148 .Case("mips3", true) 8149 .Case("mips4", true) 8150 .Case("mips5", true) 8151 .Case("mips32", true) 8152 .Case("mips32r2", true) 8153 .Case("mips32r3", true) 8154 .Case("mips32r5", true) 8155 .Case("mips32r6", true) 8156 .Case("mips64", true) 8157 .Case("mips64r2", true) 8158 .Case("mips64r3", true) 8159 .Case("mips64r5", true) 8160 .Case("mips64r6", true) 8161 .Case("octeon", true) 8162 .Case("p5600", true) 8163 .Default(false); 8164 } 8165 const std::string& getCPU() const { return CPU; } 8166 bool 8167 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8168 StringRef CPU, 8169 const std::vector<std::string> &FeaturesVec) const override { 8170 if (CPU.empty()) 8171 CPU = getCPU(); 8172 if (CPU == "octeon") 8173 Features["mips64r2"] = Features["cnmips"] = true; 8174 else 8175 Features[CPU] = true; 8176 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8177 } 8178 8179 void getTargetDefines(const LangOptions &Opts, 8180 MacroBuilder &Builder) const override { 8181 if (BigEndian) { 8182 DefineStd(Builder, "MIPSEB", Opts); 8183 Builder.defineMacro("_MIPSEB"); 8184 } else { 8185 DefineStd(Builder, "MIPSEL", Opts); 8186 Builder.defineMacro("_MIPSEL"); 8187 } 8188 8189 Builder.defineMacro("__mips__"); 8190 Builder.defineMacro("_mips"); 8191 if (Opts.GNUMode) 8192 Builder.defineMacro("mips"); 8193 8194 if (ABI == "o32") { 8195 Builder.defineMacro("__mips", "32"); 8196 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 8197 } else { 8198 Builder.defineMacro("__mips", "64"); 8199 Builder.defineMacro("__mips64"); 8200 Builder.defineMacro("__mips64__"); 8201 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 8202 } 8203 8204 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 8205 .Cases("mips32", "mips64", "1") 8206 .Cases("mips32r2", "mips64r2", "2") 8207 .Cases("mips32r3", "mips64r3", "3") 8208 .Cases("mips32r5", "mips64r5", "5") 8209 .Cases("mips32r6", "mips64r6", "6") 8210 .Default(""); 8211 if (!ISARev.empty()) 8212 Builder.defineMacro("__mips_isa_rev", ISARev); 8213 8214 if (ABI == "o32") { 8215 Builder.defineMacro("__mips_o32"); 8216 Builder.defineMacro("_ABIO32", "1"); 8217 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 8218 } else if (ABI == "n32") { 8219 Builder.defineMacro("__mips_n32"); 8220 Builder.defineMacro("_ABIN32", "2"); 8221 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 8222 } else if (ABI == "n64") { 8223 Builder.defineMacro("__mips_n64"); 8224 Builder.defineMacro("_ABI64", "3"); 8225 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 8226 } else 8227 llvm_unreachable("Invalid ABI."); 8228 8229 if (!IsNoABICalls) { 8230 Builder.defineMacro("__mips_abicalls"); 8231 if (CanUseBSDABICalls) 8232 Builder.defineMacro("__ABICALLS__"); 8233 } 8234 8235 Builder.defineMacro("__REGISTER_PREFIX__", ""); 8236 8237 switch (FloatABI) { 8238 case HardFloat: 8239 Builder.defineMacro("__mips_hard_float", Twine(1)); 8240 break; 8241 case SoftFloat: 8242 Builder.defineMacro("__mips_soft_float", Twine(1)); 8243 break; 8244 } 8245 8246 if (IsSingleFloat) 8247 Builder.defineMacro("__mips_single_float", Twine(1)); 8248 8249 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 8250 Builder.defineMacro("_MIPS_FPSET", 8251 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 8252 8253 if (IsMips16) 8254 Builder.defineMacro("__mips16", Twine(1)); 8255 8256 if (IsMicromips) 8257 Builder.defineMacro("__mips_micromips", Twine(1)); 8258 8259 if (IsNan2008) 8260 Builder.defineMacro("__mips_nan2008", Twine(1)); 8261 8262 switch (DspRev) { 8263 default: 8264 break; 8265 case DSP1: 8266 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 8267 Builder.defineMacro("__mips_dsp", Twine(1)); 8268 break; 8269 case DSP2: 8270 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 8271 Builder.defineMacro("__mips_dspr2", Twine(1)); 8272 Builder.defineMacro("__mips_dsp", Twine(1)); 8273 break; 8274 } 8275 8276 if (HasMSA) 8277 Builder.defineMacro("__mips_msa", Twine(1)); 8278 8279 if (DisableMadd4) 8280 Builder.defineMacro("__mips_no_madd4", Twine(1)); 8281 8282 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 8283 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 8284 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 8285 8286 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 8287 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 8288 8289 // These shouldn't be defined for MIPS-I but there's no need to check 8290 // for that since MIPS-I isn't supported. 8291 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 8292 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 8293 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 8294 8295 // 32-bit MIPS processors don't have the necessary lld/scd instructions 8296 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 8297 // the instructions exist but using them violates the ABI since they 8298 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 8299 if (ABI == "n32" || ABI == "n64") 8300 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 8301 } 8302 8303 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8304 return llvm::makeArrayRef(BuiltinInfo, 8305 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 8306 } 8307 bool hasFeature(StringRef Feature) const override { 8308 return llvm::StringSwitch<bool>(Feature) 8309 .Case("mips", true) 8310 .Case("fp64", HasFP64) 8311 .Default(false); 8312 } 8313 BuiltinVaListKind getBuiltinVaListKind() const override { 8314 return TargetInfo::VoidPtrBuiltinVaList; 8315 } 8316 ArrayRef<const char *> getGCCRegNames() const override { 8317 static const char *const GCCRegNames[] = { 8318 // CPU register names 8319 // Must match second column of GCCRegAliases 8320 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 8321 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 8322 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 8323 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 8324 // Floating point register names 8325 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 8326 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 8327 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 8328 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 8329 // Hi/lo and condition register names 8330 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 8331 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 8332 "$ac3hi","$ac3lo", 8333 // MSA register names 8334 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 8335 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 8336 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 8337 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 8338 // MSA control register names 8339 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 8340 "$msarequest", "$msamap", "$msaunmap" 8341 }; 8342 return llvm::makeArrayRef(GCCRegNames); 8343 } 8344 bool validateAsmConstraint(const char *&Name, 8345 TargetInfo::ConstraintInfo &Info) const override { 8346 switch (*Name) { 8347 default: 8348 return false; 8349 case 'r': // CPU registers. 8350 case 'd': // Equivalent to "r" unless generating MIPS16 code. 8351 case 'y': // Equivalent to "r", backward compatibility only. 8352 case 'f': // floating-point registers. 8353 case 'c': // $25 for indirect jumps 8354 case 'l': // lo register 8355 case 'x': // hilo register pair 8356 Info.setAllowsRegister(); 8357 return true; 8358 case 'I': // Signed 16-bit constant 8359 case 'J': // Integer 0 8360 case 'K': // Unsigned 16-bit constant 8361 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 8362 case 'M': // Constants not loadable via lui, addiu, or ori 8363 case 'N': // Constant -1 to -65535 8364 case 'O': // A signed 15-bit constant 8365 case 'P': // A constant between 1 go 65535 8366 return true; 8367 case 'R': // An address that can be used in a non-macro load or store 8368 Info.setAllowsMemory(); 8369 return true; 8370 case 'Z': 8371 if (Name[1] == 'C') { // An address usable by ll, and sc. 8372 Info.setAllowsMemory(); 8373 Name++; // Skip over 'Z'. 8374 return true; 8375 } 8376 return false; 8377 } 8378 } 8379 8380 std::string convertConstraint(const char *&Constraint) const override { 8381 std::string R; 8382 switch (*Constraint) { 8383 case 'Z': // Two-character constraint; add "^" hint for later parsing. 8384 if (Constraint[1] == 'C') { 8385 R = std::string("^") + std::string(Constraint, 2); 8386 Constraint++; 8387 return R; 8388 } 8389 break; 8390 } 8391 return TargetInfo::convertConstraint(Constraint); 8392 } 8393 8394 const char *getClobbers() const override { 8395 // In GCC, $1 is not widely used in generated code (it's used only in a few 8396 // specific situations), so there is no real need for users to add it to 8397 // the clobbers list if they want to use it in their inline assembly code. 8398 // 8399 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 8400 // code generation, so using it in inline assembly without adding it to the 8401 // clobbers list can cause conflicts between the inline assembly code and 8402 // the surrounding generated code. 8403 // 8404 // Another problem is that LLVM is allowed to choose $1 for inline assembly 8405 // operands, which will conflict with the ".set at" assembler option (which 8406 // we use only for inline assembly, in order to maintain compatibility with 8407 // GCC) and will also conflict with the user's usage of $1. 8408 // 8409 // The easiest way to avoid these conflicts and keep $1 as an allocatable 8410 // register for generated code is to automatically clobber $1 for all inline 8411 // assembly code. 8412 // 8413 // FIXME: We should automatically clobber $1 only for inline assembly code 8414 // which actually uses it. This would allow LLVM to use $1 for inline 8415 // assembly operands if the user's assembly code doesn't use it. 8416 return "~{$1}"; 8417 } 8418 8419 bool handleTargetFeatures(std::vector<std::string> &Features, 8420 DiagnosticsEngine &Diags) override { 8421 IsMips16 = false; 8422 IsMicromips = false; 8423 IsNan2008 = isNaN2008Default(); 8424 IsSingleFloat = false; 8425 FloatABI = HardFloat; 8426 DspRev = NoDSP; 8427 HasFP64 = isFP64Default(); 8428 8429 for (const auto &Feature : Features) { 8430 if (Feature == "+single-float") 8431 IsSingleFloat = true; 8432 else if (Feature == "+soft-float") 8433 FloatABI = SoftFloat; 8434 else if (Feature == "+mips16") 8435 IsMips16 = true; 8436 else if (Feature == "+micromips") 8437 IsMicromips = true; 8438 else if (Feature == "+dsp") 8439 DspRev = std::max(DspRev, DSP1); 8440 else if (Feature == "+dspr2") 8441 DspRev = std::max(DspRev, DSP2); 8442 else if (Feature == "+msa") 8443 HasMSA = true; 8444 else if (Feature == "+nomadd4") 8445 DisableMadd4 = true; 8446 else if (Feature == "+fp64") 8447 HasFP64 = true; 8448 else if (Feature == "-fp64") 8449 HasFP64 = false; 8450 else if (Feature == "+nan2008") 8451 IsNan2008 = true; 8452 else if (Feature == "-nan2008") 8453 IsNan2008 = false; 8454 else if (Feature == "+noabicalls") 8455 IsNoABICalls = true; 8456 } 8457 8458 setDataLayout(); 8459 8460 return true; 8461 } 8462 8463 int getEHDataRegisterNumber(unsigned RegNo) const override { 8464 if (RegNo == 0) return 4; 8465 if (RegNo == 1) return 5; 8466 return -1; 8467 } 8468 8469 bool isCLZForZeroUndef() const override { return false; } 8470 8471 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8472 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 8473 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8474 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8475 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 8476 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 8477 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 8478 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8479 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8480 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8481 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8482 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8483 {{"ra"}, "$31"}}; 8484 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 8485 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8486 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8487 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 8488 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 8489 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 8490 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8491 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8492 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8493 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8494 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8495 {{"ra"}, "$31"}}; 8496 if (ABI == "o32") 8497 return llvm::makeArrayRef(O32RegAliases); 8498 return llvm::makeArrayRef(NewABIRegAliases); 8499 } 8500 8501 bool hasInt128Type() const override { 8502 return ABI == "n32" || ABI == "n64"; 8503 } 8504 8505 bool validateTarget(DiagnosticsEngine &Diags) const override { 8506 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 8507 // this yet. It's better to fail here than on the backend assertion. 8508 if (processorSupportsGPR64() && ABI == "o32") { 8509 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8510 return false; 8511 } 8512 8513 // 64-bit ABI's require 64-bit CPU's. 8514 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 8515 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8516 return false; 8517 } 8518 8519 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 8520 // can't handle this yet. It's better to fail here than on the 8521 // backend assertion. 8522 if ((getTriple().getArch() == llvm::Triple::mips64 || 8523 getTriple().getArch() == llvm::Triple::mips64el) && 8524 ABI == "o32") { 8525 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8526 << ABI << getTriple().str(); 8527 return false; 8528 } 8529 8530 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 8531 // can't handle this yet. It's better to fail here than on the 8532 // backend assertion. 8533 if ((getTriple().getArch() == llvm::Triple::mips || 8534 getTriple().getArch() == llvm::Triple::mipsel) && 8535 (ABI == "n32" || ABI == "n64")) { 8536 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8537 << ABI << getTriple().str(); 8538 return false; 8539 } 8540 8541 return true; 8542 } 8543 }; 8544 8545 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 8546 #define BUILTIN(ID, TYPE, ATTRS) \ 8547 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8548 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8549 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8550 #include "clang/Basic/BuiltinsMips.def" 8551 }; 8552 8553 class PNaClTargetInfo : public TargetInfo { 8554 public: 8555 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8556 : TargetInfo(Triple) { 8557 this->LongAlign = 32; 8558 this->LongWidth = 32; 8559 this->PointerAlign = 32; 8560 this->PointerWidth = 32; 8561 this->IntMaxType = TargetInfo::SignedLongLong; 8562 this->Int64Type = TargetInfo::SignedLongLong; 8563 this->DoubleAlign = 64; 8564 this->LongDoubleWidth = 64; 8565 this->LongDoubleAlign = 64; 8566 this->SizeType = TargetInfo::UnsignedInt; 8567 this->PtrDiffType = TargetInfo::SignedInt; 8568 this->IntPtrType = TargetInfo::SignedInt; 8569 this->RegParmMax = 0; // Disallow regparm 8570 } 8571 8572 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8573 Builder.defineMacro("__le32__"); 8574 Builder.defineMacro("__pnacl__"); 8575 } 8576 void getTargetDefines(const LangOptions &Opts, 8577 MacroBuilder &Builder) const override { 8578 getArchDefines(Opts, Builder); 8579 } 8580 bool hasFeature(StringRef Feature) const override { 8581 return Feature == "pnacl"; 8582 } 8583 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8584 BuiltinVaListKind getBuiltinVaListKind() const override { 8585 return TargetInfo::PNaClABIBuiltinVaList; 8586 } 8587 ArrayRef<const char *> getGCCRegNames() const override; 8588 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8589 bool validateAsmConstraint(const char *&Name, 8590 TargetInfo::ConstraintInfo &Info) const override { 8591 return false; 8592 } 8593 8594 const char *getClobbers() const override { 8595 return ""; 8596 } 8597 }; 8598 8599 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8600 return None; 8601 } 8602 8603 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8604 return None; 8605 } 8606 8607 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8608 class NaClMips32TargetInfo : public MipsTargetInfo { 8609 public: 8610 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8611 : MipsTargetInfo(Triple, Opts) {} 8612 8613 BuiltinVaListKind getBuiltinVaListKind() const override { 8614 return TargetInfo::PNaClABIBuiltinVaList; 8615 } 8616 }; 8617 8618 class Le64TargetInfo : public TargetInfo { 8619 static const Builtin::Info BuiltinInfo[]; 8620 8621 public: 8622 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8623 : TargetInfo(Triple) { 8624 NoAsmVariants = true; 8625 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8626 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8627 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8628 } 8629 8630 void getTargetDefines(const LangOptions &Opts, 8631 MacroBuilder &Builder) const override { 8632 DefineStd(Builder, "unix", Opts); 8633 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8634 Builder.defineMacro("__ELF__"); 8635 } 8636 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8637 return llvm::makeArrayRef(BuiltinInfo, 8638 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8639 } 8640 BuiltinVaListKind getBuiltinVaListKind() const override { 8641 return TargetInfo::PNaClABIBuiltinVaList; 8642 } 8643 const char *getClobbers() const override { return ""; } 8644 ArrayRef<const char *> getGCCRegNames() const override { 8645 return None; 8646 } 8647 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8648 return None; 8649 } 8650 bool validateAsmConstraint(const char *&Name, 8651 TargetInfo::ConstraintInfo &Info) const override { 8652 return false; 8653 } 8654 8655 bool hasProtectedVisibility() const override { return false; } 8656 }; 8657 8658 class WebAssemblyTargetInfo : public TargetInfo { 8659 static const Builtin::Info BuiltinInfo[]; 8660 8661 enum SIMDEnum { 8662 NoSIMD, 8663 SIMD128, 8664 } SIMDLevel; 8665 8666 public: 8667 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8668 : TargetInfo(T), SIMDLevel(NoSIMD) { 8669 NoAsmVariants = true; 8670 SuitableAlign = 128; 8671 LargeArrayMinWidth = 128; 8672 LargeArrayAlign = 128; 8673 SimdDefaultAlign = 128; 8674 SigAtomicType = SignedLong; 8675 LongDoubleWidth = LongDoubleAlign = 128; 8676 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8677 SizeType = UnsignedInt; 8678 PtrDiffType = SignedInt; 8679 IntPtrType = SignedInt; 8680 } 8681 8682 protected: 8683 void getTargetDefines(const LangOptions &Opts, 8684 MacroBuilder &Builder) const override { 8685 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8686 if (SIMDLevel >= SIMD128) 8687 Builder.defineMacro("__wasm_simd128__"); 8688 } 8689 8690 private: 8691 bool 8692 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8693 StringRef CPU, 8694 const std::vector<std::string> &FeaturesVec) const override { 8695 if (CPU == "bleeding-edge") 8696 Features["simd128"] = true; 8697 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8698 } 8699 bool hasFeature(StringRef Feature) const final { 8700 return llvm::StringSwitch<bool>(Feature) 8701 .Case("simd128", SIMDLevel >= SIMD128) 8702 .Default(false); 8703 } 8704 bool handleTargetFeatures(std::vector<std::string> &Features, 8705 DiagnosticsEngine &Diags) final { 8706 for (const auto &Feature : Features) { 8707 if (Feature == "+simd128") { 8708 SIMDLevel = std::max(SIMDLevel, SIMD128); 8709 continue; 8710 } 8711 if (Feature == "-simd128") { 8712 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8713 continue; 8714 } 8715 8716 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8717 << "-target-feature"; 8718 return false; 8719 } 8720 return true; 8721 } 8722 bool setCPU(const std::string &Name) final { 8723 return llvm::StringSwitch<bool>(Name) 8724 .Case("mvp", true) 8725 .Case("bleeding-edge", true) 8726 .Case("generic", true) 8727 .Default(false); 8728 } 8729 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8730 return llvm::makeArrayRef(BuiltinInfo, 8731 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8732 } 8733 BuiltinVaListKind getBuiltinVaListKind() const final { 8734 return VoidPtrBuiltinVaList; 8735 } 8736 ArrayRef<const char *> getGCCRegNames() const final { 8737 return None; 8738 } 8739 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8740 return None; 8741 } 8742 bool 8743 validateAsmConstraint(const char *&Name, 8744 TargetInfo::ConstraintInfo &Info) const final { 8745 return false; 8746 } 8747 const char *getClobbers() const final { return ""; } 8748 bool isCLZForZeroUndef() const final { return false; } 8749 bool hasInt128Type() const final { return true; } 8750 IntType getIntTypeByWidth(unsigned BitWidth, 8751 bool IsSigned) const final { 8752 // WebAssembly prefers long long for explicitly 64-bit integers. 8753 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8754 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8755 } 8756 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8757 bool IsSigned) const final { 8758 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8759 return BitWidth == 64 8760 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8761 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8762 } 8763 }; 8764 8765 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8766 #define BUILTIN(ID, TYPE, ATTRS) \ 8767 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8768 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8769 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8770 #include "clang/Basic/BuiltinsWebAssembly.def" 8771 }; 8772 8773 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8774 public: 8775 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8776 const TargetOptions &Opts) 8777 : WebAssemblyTargetInfo(T, Opts) { 8778 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8779 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8780 } 8781 8782 protected: 8783 void getTargetDefines(const LangOptions &Opts, 8784 MacroBuilder &Builder) const override { 8785 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8786 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8787 } 8788 }; 8789 8790 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8791 public: 8792 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8793 const TargetOptions &Opts) 8794 : WebAssemblyTargetInfo(T, Opts) { 8795 LongAlign = LongWidth = 64; 8796 PointerAlign = PointerWidth = 64; 8797 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8798 SizeType = UnsignedLong; 8799 PtrDiffType = SignedLong; 8800 IntPtrType = SignedLong; 8801 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8802 } 8803 8804 protected: 8805 void getTargetDefines(const LangOptions &Opts, 8806 MacroBuilder &Builder) const override { 8807 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8808 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8809 } 8810 }; 8811 8812 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8813 #define BUILTIN(ID, TYPE, ATTRS) \ 8814 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8815 #include "clang/Basic/BuiltinsLe64.def" 8816 }; 8817 8818 static const unsigned SPIRAddrSpaceMap[] = { 8819 0, // Default 8820 1, // opencl_global 8821 3, // opencl_local 8822 2, // opencl_constant 8823 4, // opencl_generic 8824 0, // cuda_device 8825 0, // cuda_constant 8826 0 // cuda_shared 8827 }; 8828 class SPIRTargetInfo : public TargetInfo { 8829 public: 8830 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8831 : TargetInfo(Triple) { 8832 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8833 "SPIR target must use unknown OS"); 8834 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8835 "SPIR target must use unknown environment type"); 8836 TLSSupported = false; 8837 LongWidth = LongAlign = 64; 8838 AddrSpaceMap = &SPIRAddrSpaceMap; 8839 UseAddrSpaceMapMangling = true; 8840 // Define available target features 8841 // These must be defined in sorted order! 8842 NoAsmVariants = true; 8843 } 8844 void getTargetDefines(const LangOptions &Opts, 8845 MacroBuilder &Builder) const override { 8846 DefineStd(Builder, "SPIR", Opts); 8847 } 8848 bool hasFeature(StringRef Feature) const override { 8849 return Feature == "spir"; 8850 } 8851 8852 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8853 const char *getClobbers() const override { return ""; } 8854 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8855 bool validateAsmConstraint(const char *&Name, 8856 TargetInfo::ConstraintInfo &info) const override { 8857 return true; 8858 } 8859 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8860 return None; 8861 } 8862 BuiltinVaListKind getBuiltinVaListKind() const override { 8863 return TargetInfo::VoidPtrBuiltinVaList; 8864 } 8865 8866 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8867 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8868 : CCCR_Warning; 8869 } 8870 8871 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8872 return CC_SpirFunction; 8873 } 8874 8875 void setSupportedOpenCLOpts() override { 8876 // Assume all OpenCL extensions and optional core features are supported 8877 // for SPIR since it is a generic target. 8878 getSupportedOpenCLOpts().supportAll(); 8879 } 8880 }; 8881 8882 class SPIR32TargetInfo : public SPIRTargetInfo { 8883 public: 8884 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8885 : SPIRTargetInfo(Triple, Opts) { 8886 PointerWidth = PointerAlign = 32; 8887 SizeType = TargetInfo::UnsignedInt; 8888 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8889 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8890 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8891 } 8892 void getTargetDefines(const LangOptions &Opts, 8893 MacroBuilder &Builder) const override { 8894 DefineStd(Builder, "SPIR32", Opts); 8895 } 8896 }; 8897 8898 class SPIR64TargetInfo : public SPIRTargetInfo { 8899 public: 8900 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8901 : SPIRTargetInfo(Triple, Opts) { 8902 PointerWidth = PointerAlign = 64; 8903 SizeType = TargetInfo::UnsignedLong; 8904 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8905 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8906 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8907 } 8908 void getTargetDefines(const LangOptions &Opts, 8909 MacroBuilder &Builder) const override { 8910 DefineStd(Builder, "SPIR64", Opts); 8911 } 8912 }; 8913 8914 class XCoreTargetInfo : public TargetInfo { 8915 static const Builtin::Info BuiltinInfo[]; 8916 public: 8917 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8918 : TargetInfo(Triple) { 8919 NoAsmVariants = true; 8920 LongLongAlign = 32; 8921 SuitableAlign = 32; 8922 DoubleAlign = LongDoubleAlign = 32; 8923 SizeType = UnsignedInt; 8924 PtrDiffType = SignedInt; 8925 IntPtrType = SignedInt; 8926 WCharType = UnsignedChar; 8927 WIntType = UnsignedInt; 8928 UseZeroLengthBitfieldAlignment = true; 8929 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8930 "-f64:32-a:0:32-n32"); 8931 } 8932 void getTargetDefines(const LangOptions &Opts, 8933 MacroBuilder &Builder) const override { 8934 Builder.defineMacro("__XS1B__"); 8935 } 8936 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8937 return llvm::makeArrayRef(BuiltinInfo, 8938 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8939 } 8940 BuiltinVaListKind getBuiltinVaListKind() const override { 8941 return TargetInfo::VoidPtrBuiltinVaList; 8942 } 8943 const char *getClobbers() const override { 8944 return ""; 8945 } 8946 ArrayRef<const char *> getGCCRegNames() const override { 8947 static const char * const GCCRegNames[] = { 8948 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8949 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8950 }; 8951 return llvm::makeArrayRef(GCCRegNames); 8952 } 8953 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8954 return None; 8955 } 8956 bool validateAsmConstraint(const char *&Name, 8957 TargetInfo::ConstraintInfo &Info) const override { 8958 return false; 8959 } 8960 int getEHDataRegisterNumber(unsigned RegNo) const override { 8961 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8962 return (RegNo < 2)? RegNo : -1; 8963 } 8964 bool allowsLargerPreferedTypeAlignment() const override { 8965 return false; 8966 } 8967 }; 8968 8969 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8970 #define BUILTIN(ID, TYPE, ATTRS) \ 8971 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8972 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8973 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8974 #include "clang/Basic/BuiltinsXCore.def" 8975 }; 8976 8977 // x86_32 Android target 8978 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8979 public: 8980 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8981 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8982 SuitableAlign = 32; 8983 LongDoubleWidth = 64; 8984 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8985 } 8986 }; 8987 8988 // x86_64 Android target 8989 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8990 public: 8991 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8992 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8993 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8994 } 8995 8996 bool useFloat128ManglingForLongDouble() const override { 8997 return true; 8998 } 8999 }; 9000 9001 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 9002 class RenderScript32TargetInfo : public ARMleTargetInfo { 9003 public: 9004 RenderScript32TargetInfo(const llvm::Triple &Triple, 9005 const TargetOptions &Opts) 9006 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 9007 Triple.getOSName(), 9008 Triple.getEnvironmentName()), 9009 Opts) { 9010 IsRenderScriptTarget = true; 9011 LongWidth = LongAlign = 64; 9012 } 9013 void getTargetDefines(const LangOptions &Opts, 9014 MacroBuilder &Builder) const override { 9015 Builder.defineMacro("__RENDERSCRIPT__"); 9016 ARMleTargetInfo::getTargetDefines(Opts, Builder); 9017 } 9018 }; 9019 9020 // 64-bit RenderScript is aarch64 9021 class RenderScript64TargetInfo : public AArch64leTargetInfo { 9022 public: 9023 RenderScript64TargetInfo(const llvm::Triple &Triple, 9024 const TargetOptions &Opts) 9025 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 9026 Triple.getOSName(), 9027 Triple.getEnvironmentName()), 9028 Opts) { 9029 IsRenderScriptTarget = true; 9030 } 9031 9032 void getTargetDefines(const LangOptions &Opts, 9033 MacroBuilder &Builder) const override { 9034 Builder.defineMacro("__RENDERSCRIPT__"); 9035 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 9036 } 9037 }; 9038 9039 /// Information about a specific microcontroller. 9040 struct MCUInfo { 9041 const char *Name; 9042 const char *DefineName; 9043 }; 9044 9045 // This list should be kept up-to-date with AVRDevices.td in LLVM. 9046 static ArrayRef<MCUInfo> AVRMcus = { 9047 { "at90s1200", "__AVR_AT90S1200__" }, 9048 { "attiny11", "__AVR_ATtiny11__" }, 9049 { "attiny12", "__AVR_ATtiny12__" }, 9050 { "attiny15", "__AVR_ATtiny15__" }, 9051 { "attiny28", "__AVR_ATtiny28__" }, 9052 { "at90s2313", "__AVR_AT90S2313__" }, 9053 { "at90s2323", "__AVR_AT90S2323__" }, 9054 { "at90s2333", "__AVR_AT90S2333__" }, 9055 { "at90s2343", "__AVR_AT90S2343__" }, 9056 { "attiny22", "__AVR_ATtiny22__" }, 9057 { "attiny26", "__AVR_ATtiny26__" }, 9058 { "at86rf401", "__AVR_AT86RF401__" }, 9059 { "at90s4414", "__AVR_AT90S4414__" }, 9060 { "at90s4433", "__AVR_AT90S4433__" }, 9061 { "at90s4434", "__AVR_AT90S4434__" }, 9062 { "at90s8515", "__AVR_AT90S8515__" }, 9063 { "at90c8534", "__AVR_AT90c8534__" }, 9064 { "at90s8535", "__AVR_AT90S8535__" }, 9065 { "ata5272", "__AVR_ATA5272__" }, 9066 { "attiny13", "__AVR_ATtiny13__" }, 9067 { "attiny13a", "__AVR_ATtiny13A__" }, 9068 { "attiny2313", "__AVR_ATtiny2313__" }, 9069 { "attiny2313a", "__AVR_ATtiny2313A__" }, 9070 { "attiny24", "__AVR_ATtiny24__" }, 9071 { "attiny24a", "__AVR_ATtiny24A__" }, 9072 { "attiny4313", "__AVR_ATtiny4313__" }, 9073 { "attiny44", "__AVR_ATtiny44__" }, 9074 { "attiny44a", "__AVR_ATtiny44A__" }, 9075 { "attiny84", "__AVR_ATtiny84__" }, 9076 { "attiny84a", "__AVR_ATtiny84A__" }, 9077 { "attiny25", "__AVR_ATtiny25__" }, 9078 { "attiny45", "__AVR_ATtiny45__" }, 9079 { "attiny85", "__AVR_ATtiny85__" }, 9080 { "attiny261", "__AVR_ATtiny261__" }, 9081 { "attiny261a", "__AVR_ATtiny261A__" }, 9082 { "attiny461", "__AVR_ATtiny461__" }, 9083 { "attiny461a", "__AVR_ATtiny461A__" }, 9084 { "attiny861", "__AVR_ATtiny861__" }, 9085 { "attiny861a", "__AVR_ATtiny861A__" }, 9086 { "attiny87", "__AVR_ATtiny87__" }, 9087 { "attiny43u", "__AVR_ATtiny43U__" }, 9088 { "attiny48", "__AVR_ATtiny48__" }, 9089 { "attiny88", "__AVR_ATtiny88__" }, 9090 { "attiny828", "__AVR_ATtiny828__" }, 9091 { "at43usb355", "__AVR_AT43USB355__" }, 9092 { "at76c711", "__AVR_AT76C711__" }, 9093 { "atmega103", "__AVR_ATmega103__" }, 9094 { "at43usb320", "__AVR_AT43USB320__" }, 9095 { "attiny167", "__AVR_ATtiny167__" }, 9096 { "at90usb82", "__AVR_AT90USB82__" }, 9097 { "at90usb162", "__AVR_AT90USB162__" }, 9098 { "ata5505", "__AVR_ATA5505__" }, 9099 { "atmega8u2", "__AVR_ATmega8U2__" }, 9100 { "atmega16u2", "__AVR_ATmega16U2__" }, 9101 { "atmega32u2", "__AVR_ATmega32U2__" }, 9102 { "attiny1634", "__AVR_ATtiny1634__" }, 9103 { "atmega8", "__AVR_ATmega8__" }, 9104 { "ata6289", "__AVR_ATA6289__" }, 9105 { "atmega8a", "__AVR_ATmega8A__" }, 9106 { "ata6285", "__AVR_ATA6285__" }, 9107 { "ata6286", "__AVR_ATA6286__" }, 9108 { "atmega48", "__AVR_ATmega48__" }, 9109 { "atmega48a", "__AVR_ATmega48A__" }, 9110 { "atmega48pa", "__AVR_ATmega48PA__" }, 9111 { "atmega48p", "__AVR_ATmega48P__" }, 9112 { "atmega88", "__AVR_ATmega88__" }, 9113 { "atmega88a", "__AVR_ATmega88A__" }, 9114 { "atmega88p", "__AVR_ATmega88P__" }, 9115 { "atmega88pa", "__AVR_ATmega88PA__" }, 9116 { "atmega8515", "__AVR_ATmega8515__" }, 9117 { "atmega8535", "__AVR_ATmega8535__" }, 9118 { "atmega8hva", "__AVR_ATmega8HVA__" }, 9119 { "at90pwm1", "__AVR_AT90PWM1__" }, 9120 { "at90pwm2", "__AVR_AT90PWM2__" }, 9121 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 9122 { "at90pwm3", "__AVR_AT90PWM3__" }, 9123 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 9124 { "at90pwm81", "__AVR_AT90PWM81__" }, 9125 { "ata5790", "__AVR_ATA5790__" }, 9126 { "ata5795", "__AVR_ATA5795__" }, 9127 { "atmega16", "__AVR_ATmega16__" }, 9128 { "atmega16a", "__AVR_ATmega16A__" }, 9129 { "atmega161", "__AVR_ATmega161__" }, 9130 { "atmega162", "__AVR_ATmega162__" }, 9131 { "atmega163", "__AVR_ATmega163__" }, 9132 { "atmega164a", "__AVR_ATmega164A__" }, 9133 { "atmega164p", "__AVR_ATmega164P__" }, 9134 { "atmega164pa", "__AVR_ATmega164PA__" }, 9135 { "atmega165", "__AVR_ATmega165__" }, 9136 { "atmega165a", "__AVR_ATmega165A__" }, 9137 { "atmega165p", "__AVR_ATmega165P__" }, 9138 { "atmega165pa", "__AVR_ATmega165PA__" }, 9139 { "atmega168", "__AVR_ATmega168__" }, 9140 { "atmega168a", "__AVR_ATmega168A__" }, 9141 { "atmega168p", "__AVR_ATmega168P__" }, 9142 { "atmega168pa", "__AVR_ATmega168PA__" }, 9143 { "atmega169", "__AVR_ATmega169__" }, 9144 { "atmega169a", "__AVR_ATmega169A__" }, 9145 { "atmega169p", "__AVR_ATmega169P__" }, 9146 { "atmega169pa", "__AVR_ATmega169PA__" }, 9147 { "atmega32", "__AVR_ATmega32__" }, 9148 { "atmega32a", "__AVR_ATmega32A__" }, 9149 { "atmega323", "__AVR_ATmega323__" }, 9150 { "atmega324a", "__AVR_ATmega324A__" }, 9151 { "atmega324p", "__AVR_ATmega324P__" }, 9152 { "atmega324pa", "__AVR_ATmega324PA__" }, 9153 { "atmega325", "__AVR_ATmega325__" }, 9154 { "atmega325a", "__AVR_ATmega325A__" }, 9155 { "atmega325p", "__AVR_ATmega325P__" }, 9156 { "atmega325pa", "__AVR_ATmega325PA__" }, 9157 { "atmega3250", "__AVR_ATmega3250__" }, 9158 { "atmega3250a", "__AVR_ATmega3250A__" }, 9159 { "atmega3250p", "__AVR_ATmega3250P__" }, 9160 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 9161 { "atmega328", "__AVR_ATmega328__" }, 9162 { "atmega328p", "__AVR_ATmega328P__" }, 9163 { "atmega329", "__AVR_ATmega329__" }, 9164 { "atmega329a", "__AVR_ATmega329A__" }, 9165 { "atmega329p", "__AVR_ATmega329P__" }, 9166 { "atmega329pa", "__AVR_ATmega329PA__" }, 9167 { "atmega3290", "__AVR_ATmega3290__" }, 9168 { "atmega3290a", "__AVR_ATmega3290A__" }, 9169 { "atmega3290p", "__AVR_ATmega3290P__" }, 9170 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 9171 { "atmega406", "__AVR_ATmega406__" }, 9172 { "atmega64", "__AVR_ATmega64__" }, 9173 { "atmega64a", "__AVR_ATmega64A__" }, 9174 { "atmega640", "__AVR_ATmega640__" }, 9175 { "atmega644", "__AVR_ATmega644__" }, 9176 { "atmega644a", "__AVR_ATmega644A__" }, 9177 { "atmega644p", "__AVR_ATmega644P__" }, 9178 { "atmega644pa", "__AVR_ATmega644PA__" }, 9179 { "atmega645", "__AVR_ATmega645__" }, 9180 { "atmega645a", "__AVR_ATmega645A__" }, 9181 { "atmega645p", "__AVR_ATmega645P__" }, 9182 { "atmega649", "__AVR_ATmega649__" }, 9183 { "atmega649a", "__AVR_ATmega649A__" }, 9184 { "atmega649p", "__AVR_ATmega649P__" }, 9185 { "atmega6450", "__AVR_ATmega6450__" }, 9186 { "atmega6450a", "__AVR_ATmega6450A__" }, 9187 { "atmega6450p", "__AVR_ATmega6450P__" }, 9188 { "atmega6490", "__AVR_ATmega6490__" }, 9189 { "atmega6490a", "__AVR_ATmega6490A__" }, 9190 { "atmega6490p", "__AVR_ATmega6490P__" }, 9191 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 9192 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 9193 { "atmega16hva", "__AVR_ATmega16HVA__" }, 9194 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 9195 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 9196 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 9197 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 9198 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 9199 { "atmega64hve", "__AVR_ATmega64HVE__" }, 9200 { "at90can32", "__AVR_AT90CAN32__" }, 9201 { "at90can64", "__AVR_AT90CAN64__" }, 9202 { "at90pwm161", "__AVR_AT90PWM161__" }, 9203 { "at90pwm216", "__AVR_AT90PWM216__" }, 9204 { "at90pwm316", "__AVR_AT90PWM316__" }, 9205 { "atmega32c1", "__AVR_ATmega32C1__" }, 9206 { "atmega64c1", "__AVR_ATmega64C1__" }, 9207 { "atmega16m1", "__AVR_ATmega16M1__" }, 9208 { "atmega32m1", "__AVR_ATmega32M1__" }, 9209 { "atmega64m1", "__AVR_ATmega64M1__" }, 9210 { "atmega16u4", "__AVR_ATmega16U4__" }, 9211 { "atmega32u4", "__AVR_ATmega32U4__" }, 9212 { "atmega32u6", "__AVR_ATmega32U6__" }, 9213 { "at90usb646", "__AVR_AT90USB646__" }, 9214 { "at90usb647", "__AVR_AT90USB647__" }, 9215 { "at90scr100", "__AVR_AT90SCR100__" }, 9216 { "at94k", "__AVR_AT94K__" }, 9217 { "m3000", "__AVR_AT000__" }, 9218 { "atmega128", "__AVR_ATmega128__" }, 9219 { "atmega128a", "__AVR_ATmega128A__" }, 9220 { "atmega1280", "__AVR_ATmega1280__" }, 9221 { "atmega1281", "__AVR_ATmega1281__" }, 9222 { "atmega1284", "__AVR_ATmega1284__" }, 9223 { "atmega1284p", "__AVR_ATmega1284P__" }, 9224 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 9225 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 9226 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 9227 { "at90can128", "__AVR_AT90CAN128__" }, 9228 { "at90usb1286", "__AVR_AT90USB1286__" }, 9229 { "at90usb1287", "__AVR_AT90USB1287__" }, 9230 { "atmega2560", "__AVR_ATmega2560__" }, 9231 { "atmega2561", "__AVR_ATmega2561__" }, 9232 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 9233 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 9234 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 9235 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 9236 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 9237 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 9238 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 9239 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 9240 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 9241 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 9242 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 9243 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 9244 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 9245 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 9246 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 9247 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 9248 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 9249 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 9250 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 9251 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 9252 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 9253 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 9254 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 9255 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 9256 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 9257 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 9258 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 9259 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 9260 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 9261 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 9262 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 9263 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 9264 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 9265 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 9266 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 9267 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 9268 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 9269 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 9270 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 9271 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 9272 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 9273 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 9274 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 9275 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 9276 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 9277 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 9278 { "attiny4", "__AVR_ATtiny4__" }, 9279 { "attiny5", "__AVR_ATtiny5__" }, 9280 { "attiny9", "__AVR_ATtiny9__" }, 9281 { "attiny10", "__AVR_ATtiny10__" }, 9282 { "attiny20", "__AVR_ATtiny20__" }, 9283 { "attiny40", "__AVR_ATtiny40__" }, 9284 { "attiny102", "__AVR_ATtiny102__" }, 9285 { "attiny104", "__AVR_ATtiny104__" }, 9286 }; 9287 9288 // AVR Target 9289 class AVRTargetInfo : public TargetInfo { 9290 public: 9291 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 9292 : TargetInfo(Triple) { 9293 TLSSupported = false; 9294 PointerWidth = 16; 9295 PointerAlign = 8; 9296 IntWidth = 16; 9297 IntAlign = 8; 9298 LongWidth = 32; 9299 LongAlign = 8; 9300 LongLongWidth = 64; 9301 LongLongAlign = 8; 9302 SuitableAlign = 8; 9303 DefaultAlignForAttributeAligned = 8; 9304 HalfWidth = 16; 9305 HalfAlign = 8; 9306 FloatWidth = 32; 9307 FloatAlign = 8; 9308 DoubleWidth = 32; 9309 DoubleAlign = 8; 9310 DoubleFormat = &llvm::APFloat::IEEEsingle(); 9311 LongDoubleWidth = 32; 9312 LongDoubleAlign = 8; 9313 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 9314 SizeType = UnsignedInt; 9315 PtrDiffType = SignedInt; 9316 IntPtrType = SignedInt; 9317 Char16Type = UnsignedInt; 9318 WCharType = SignedInt; 9319 WIntType = SignedInt; 9320 Char32Type = UnsignedLong; 9321 SigAtomicType = SignedChar; 9322 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 9323 "-f32:32:32-f64:64:64-n8"); 9324 } 9325 9326 void getTargetDefines(const LangOptions &Opts, 9327 MacroBuilder &Builder) const override { 9328 Builder.defineMacro("AVR"); 9329 Builder.defineMacro("__AVR"); 9330 Builder.defineMacro("__AVR__"); 9331 9332 if (!this->CPU.empty()) { 9333 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9334 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 9335 9336 if (It != AVRMcus.end()) 9337 Builder.defineMacro(It->DefineName); 9338 } 9339 } 9340 9341 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 9342 return None; 9343 } 9344 9345 BuiltinVaListKind getBuiltinVaListKind() const override { 9346 return TargetInfo::VoidPtrBuiltinVaList; 9347 } 9348 9349 const char *getClobbers() const override { 9350 return ""; 9351 } 9352 9353 ArrayRef<const char *> getGCCRegNames() const override { 9354 static const char * const GCCRegNames[] = { 9355 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 9356 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 9357 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 9358 "r24", "r25", "X", "Y", "Z", "SP" 9359 }; 9360 return llvm::makeArrayRef(GCCRegNames); 9361 } 9362 9363 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 9364 return None; 9365 } 9366 9367 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 9368 static const TargetInfo::AddlRegName AddlRegNames[] = { 9369 { { "r26", "r27"}, 26 }, 9370 { { "r28", "r29"}, 27 }, 9371 { { "r30", "r31"}, 28 }, 9372 { { "SPL", "SPH"}, 29 }, 9373 }; 9374 return llvm::makeArrayRef(AddlRegNames); 9375 } 9376 9377 bool validateAsmConstraint(const char *&Name, 9378 TargetInfo::ConstraintInfo &Info) const override { 9379 // There aren't any multi-character AVR specific constraints. 9380 if (StringRef(Name).size() > 1) return false; 9381 9382 switch (*Name) { 9383 default: return false; 9384 case 'a': // Simple upper registers 9385 case 'b': // Base pointer registers pairs 9386 case 'd': // Upper register 9387 case 'l': // Lower registers 9388 case 'e': // Pointer register pairs 9389 case 'q': // Stack pointer register 9390 case 'r': // Any register 9391 case 'w': // Special upper register pairs 9392 case 't': // Temporary register 9393 case 'x': case 'X': // Pointer register pair X 9394 case 'y': case 'Y': // Pointer register pair Y 9395 case 'z': case 'Z': // Pointer register pair Z 9396 Info.setAllowsRegister(); 9397 return true; 9398 case 'I': // 6-bit positive integer constant 9399 Info.setRequiresImmediate(0, 63); 9400 return true; 9401 case 'J': // 6-bit negative integer constant 9402 Info.setRequiresImmediate(-63, 0); 9403 return true; 9404 case 'K': // Integer constant (Range: 2) 9405 Info.setRequiresImmediate(2); 9406 return true; 9407 case 'L': // Integer constant (Range: 0) 9408 Info.setRequiresImmediate(0); 9409 return true; 9410 case 'M': // 8-bit integer constant 9411 Info.setRequiresImmediate(0, 0xff); 9412 return true; 9413 case 'N': // Integer constant (Range: -1) 9414 Info.setRequiresImmediate(-1); 9415 return true; 9416 case 'O': // Integer constant (Range: 8, 16, 24) 9417 Info.setRequiresImmediate({8, 16, 24}); 9418 return true; 9419 case 'P': // Integer constant (Range: 1) 9420 Info.setRequiresImmediate(1); 9421 return true; 9422 case 'R': // Integer constant (Range: -6 to 5) 9423 Info.setRequiresImmediate(-6, 5); 9424 return true; 9425 case 'G': // Floating point constant 9426 case 'Q': // A memory address based on Y or Z pointer with displacement. 9427 return true; 9428 } 9429 9430 return false; 9431 } 9432 9433 IntType getIntTypeByWidth(unsigned BitWidth, 9434 bool IsSigned) const final { 9435 // AVR prefers int for 16-bit integers. 9436 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 9437 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 9438 } 9439 9440 IntType getLeastIntTypeByWidth(unsigned BitWidth, 9441 bool IsSigned) const final { 9442 // AVR uses int for int_least16_t and int_fast16_t. 9443 return BitWidth == 16 9444 ? (IsSigned ? SignedInt : UnsignedInt) 9445 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 9446 } 9447 9448 bool setCPU(const std::string &Name) override { 9449 bool IsFamily = llvm::StringSwitch<bool>(Name) 9450 .Case("avr1", true) 9451 .Case("avr2", true) 9452 .Case("avr25", true) 9453 .Case("avr3", true) 9454 .Case("avr31", true) 9455 .Case("avr35", true) 9456 .Case("avr4", true) 9457 .Case("avr5", true) 9458 .Case("avr51", true) 9459 .Case("avr6", true) 9460 .Case("avrxmega1", true) 9461 .Case("avrxmega2", true) 9462 .Case("avrxmega3", true) 9463 .Case("avrxmega4", true) 9464 .Case("avrxmega5", true) 9465 .Case("avrxmega6", true) 9466 .Case("avrxmega7", true) 9467 .Case("avrtiny", true) 9468 .Default(false); 9469 9470 if (IsFamily) this->CPU = Name; 9471 9472 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9473 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 9474 9475 if (IsMCU) this->CPU = Name; 9476 9477 return IsFamily || IsMCU; 9478 } 9479 9480 protected: 9481 std::string CPU; 9482 }; 9483 9484 } // end anonymous namespace 9485 9486 //===----------------------------------------------------------------------===// 9487 // Driver code 9488 //===----------------------------------------------------------------------===// 9489 9490 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 9491 const TargetOptions &Opts) { 9492 llvm::Triple::OSType os = Triple.getOS(); 9493 9494 switch (Triple.getArch()) { 9495 default: 9496 return nullptr; 9497 9498 case llvm::Triple::xcore: 9499 return new XCoreTargetInfo(Triple, Opts); 9500 9501 case llvm::Triple::hexagon: 9502 return new HexagonTargetInfo(Triple, Opts); 9503 9504 case llvm::Triple::lanai: 9505 return new LanaiTargetInfo(Triple, Opts); 9506 9507 case llvm::Triple::aarch64: 9508 if (Triple.isOSDarwin()) 9509 return new DarwinAArch64TargetInfo(Triple, Opts); 9510 9511 switch (os) { 9512 case llvm::Triple::CloudABI: 9513 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 9514 case llvm::Triple::FreeBSD: 9515 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9516 case llvm::Triple::Fuchsia: 9517 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9518 case llvm::Triple::Linux: 9519 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9520 case llvm::Triple::NetBSD: 9521 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9522 case llvm::Triple::OpenBSD: 9523 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9524 case llvm::Triple::Win32: 9525 return new MicrosoftARM64TargetInfo(Triple, Opts); 9526 default: 9527 return new AArch64leTargetInfo(Triple, Opts); 9528 } 9529 9530 case llvm::Triple::aarch64_be: 9531 switch (os) { 9532 case llvm::Triple::FreeBSD: 9533 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9534 case llvm::Triple::Fuchsia: 9535 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9536 case llvm::Triple::Linux: 9537 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9538 case llvm::Triple::NetBSD: 9539 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9540 default: 9541 return new AArch64beTargetInfo(Triple, Opts); 9542 } 9543 9544 case llvm::Triple::arm: 9545 case llvm::Triple::thumb: 9546 if (Triple.isOSBinFormatMachO()) 9547 return new DarwinARMTargetInfo(Triple, Opts); 9548 9549 switch (os) { 9550 case llvm::Triple::CloudABI: 9551 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9552 case llvm::Triple::Linux: 9553 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9554 case llvm::Triple::FreeBSD: 9555 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9556 case llvm::Triple::NetBSD: 9557 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9558 case llvm::Triple::OpenBSD: 9559 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9560 case llvm::Triple::Bitrig: 9561 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9562 case llvm::Triple::RTEMS: 9563 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9564 case llvm::Triple::NaCl: 9565 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9566 case llvm::Triple::Win32: 9567 switch (Triple.getEnvironment()) { 9568 case llvm::Triple::Cygnus: 9569 return new CygwinARMTargetInfo(Triple, Opts); 9570 case llvm::Triple::GNU: 9571 return new MinGWARMTargetInfo(Triple, Opts); 9572 case llvm::Triple::Itanium: 9573 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9574 case llvm::Triple::MSVC: 9575 default: // Assume MSVC for unknown environments 9576 return new MicrosoftARMleTargetInfo(Triple, Opts); 9577 } 9578 default: 9579 return new ARMleTargetInfo(Triple, Opts); 9580 } 9581 9582 case llvm::Triple::armeb: 9583 case llvm::Triple::thumbeb: 9584 if (Triple.isOSDarwin()) 9585 return new DarwinARMTargetInfo(Triple, Opts); 9586 9587 switch (os) { 9588 case llvm::Triple::Linux: 9589 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9590 case llvm::Triple::FreeBSD: 9591 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9592 case llvm::Triple::NetBSD: 9593 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9594 case llvm::Triple::OpenBSD: 9595 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9596 case llvm::Triple::Bitrig: 9597 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9598 case llvm::Triple::RTEMS: 9599 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9600 case llvm::Triple::NaCl: 9601 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9602 default: 9603 return new ARMbeTargetInfo(Triple, Opts); 9604 } 9605 9606 case llvm::Triple::avr: 9607 return new AVRTargetInfo(Triple, Opts); 9608 case llvm::Triple::bpfeb: 9609 case llvm::Triple::bpfel: 9610 return new BPFTargetInfo(Triple, Opts); 9611 9612 case llvm::Triple::msp430: 9613 return new MSP430TargetInfo(Triple, Opts); 9614 9615 case llvm::Triple::nios2: 9616 return new LinuxTargetInfo<Nios2TargetInfo>(Triple, Opts); 9617 9618 case llvm::Triple::mips: 9619 switch (os) { 9620 case llvm::Triple::Linux: 9621 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9622 case llvm::Triple::RTEMS: 9623 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9624 case llvm::Triple::FreeBSD: 9625 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9626 case llvm::Triple::NetBSD: 9627 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9628 default: 9629 return new MipsTargetInfo(Triple, Opts); 9630 } 9631 9632 case llvm::Triple::mipsel: 9633 switch (os) { 9634 case llvm::Triple::Linux: 9635 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9636 case llvm::Triple::RTEMS: 9637 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9638 case llvm::Triple::FreeBSD: 9639 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9640 case llvm::Triple::NetBSD: 9641 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9642 case llvm::Triple::NaCl: 9643 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9644 default: 9645 return new MipsTargetInfo(Triple, Opts); 9646 } 9647 9648 case llvm::Triple::mips64: 9649 switch (os) { 9650 case llvm::Triple::Linux: 9651 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9652 case llvm::Triple::RTEMS: 9653 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9654 case llvm::Triple::FreeBSD: 9655 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9656 case llvm::Triple::NetBSD: 9657 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9658 case llvm::Triple::OpenBSD: 9659 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9660 default: 9661 return new MipsTargetInfo(Triple, Opts); 9662 } 9663 9664 case llvm::Triple::mips64el: 9665 switch (os) { 9666 case llvm::Triple::Linux: 9667 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9668 case llvm::Triple::RTEMS: 9669 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9670 case llvm::Triple::FreeBSD: 9671 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9672 case llvm::Triple::NetBSD: 9673 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9674 case llvm::Triple::OpenBSD: 9675 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9676 default: 9677 return new MipsTargetInfo(Triple, Opts); 9678 } 9679 9680 case llvm::Triple::le32: 9681 switch (os) { 9682 case llvm::Triple::NaCl: 9683 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9684 default: 9685 return nullptr; 9686 } 9687 9688 case llvm::Triple::le64: 9689 return new Le64TargetInfo(Triple, Opts); 9690 9691 case llvm::Triple::ppc: 9692 if (Triple.isOSDarwin()) 9693 return new DarwinPPC32TargetInfo(Triple, Opts); 9694 switch (os) { 9695 case llvm::Triple::Linux: 9696 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9697 case llvm::Triple::FreeBSD: 9698 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9699 case llvm::Triple::NetBSD: 9700 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9701 case llvm::Triple::OpenBSD: 9702 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9703 case llvm::Triple::RTEMS: 9704 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9705 default: 9706 return new PPC32TargetInfo(Triple, Opts); 9707 } 9708 9709 case llvm::Triple::ppc64: 9710 if (Triple.isOSDarwin()) 9711 return new DarwinPPC64TargetInfo(Triple, Opts); 9712 switch (os) { 9713 case llvm::Triple::Linux: 9714 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9715 case llvm::Triple::Lv2: 9716 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9717 case llvm::Triple::FreeBSD: 9718 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9719 case llvm::Triple::NetBSD: 9720 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9721 default: 9722 return new PPC64TargetInfo(Triple, Opts); 9723 } 9724 9725 case llvm::Triple::ppc64le: 9726 switch (os) { 9727 case llvm::Triple::Linux: 9728 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9729 case llvm::Triple::NetBSD: 9730 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9731 default: 9732 return new PPC64TargetInfo(Triple, Opts); 9733 } 9734 9735 case llvm::Triple::nvptx: 9736 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9737 case llvm::Triple::nvptx64: 9738 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9739 9740 case llvm::Triple::amdgcn: 9741 case llvm::Triple::r600: 9742 return new AMDGPUTargetInfo(Triple, Opts); 9743 9744 case llvm::Triple::sparc: 9745 switch (os) { 9746 case llvm::Triple::Linux: 9747 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9748 case llvm::Triple::Solaris: 9749 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9750 case llvm::Triple::NetBSD: 9751 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9752 case llvm::Triple::OpenBSD: 9753 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9754 case llvm::Triple::RTEMS: 9755 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9756 default: 9757 return new SparcV8TargetInfo(Triple, Opts); 9758 } 9759 9760 // The 'sparcel' architecture copies all the above cases except for Solaris. 9761 case llvm::Triple::sparcel: 9762 switch (os) { 9763 case llvm::Triple::Linux: 9764 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9765 case llvm::Triple::NetBSD: 9766 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9767 case llvm::Triple::OpenBSD: 9768 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9769 case llvm::Triple::RTEMS: 9770 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9771 default: 9772 return new SparcV8elTargetInfo(Triple, Opts); 9773 } 9774 9775 case llvm::Triple::sparcv9: 9776 switch (os) { 9777 case llvm::Triple::Linux: 9778 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9779 case llvm::Triple::Solaris: 9780 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9781 case llvm::Triple::NetBSD: 9782 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9783 case llvm::Triple::OpenBSD: 9784 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9785 case llvm::Triple::FreeBSD: 9786 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9787 default: 9788 return new SparcV9TargetInfo(Triple, Opts); 9789 } 9790 9791 case llvm::Triple::systemz: 9792 switch (os) { 9793 case llvm::Triple::Linux: 9794 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9795 default: 9796 return new SystemZTargetInfo(Triple, Opts); 9797 } 9798 9799 case llvm::Triple::tce: 9800 return new TCETargetInfo(Triple, Opts); 9801 9802 case llvm::Triple::tcele: 9803 return new TCELETargetInfo(Triple, Opts); 9804 9805 case llvm::Triple::x86: 9806 if (Triple.isOSDarwin()) 9807 return new DarwinI386TargetInfo(Triple, Opts); 9808 9809 switch (os) { 9810 case llvm::Triple::Ananas: 9811 return new AnanasTargetInfo<X86_32TargetInfo>(Triple, Opts); 9812 case llvm::Triple::CloudABI: 9813 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9814 case llvm::Triple::Linux: { 9815 switch (Triple.getEnvironment()) { 9816 default: 9817 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9818 case llvm::Triple::Android: 9819 return new AndroidX86_32TargetInfo(Triple, Opts); 9820 } 9821 } 9822 case llvm::Triple::DragonFly: 9823 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9824 case llvm::Triple::NetBSD: 9825 return new NetBSDI386TargetInfo(Triple, Opts); 9826 case llvm::Triple::OpenBSD: 9827 return new OpenBSDI386TargetInfo(Triple, Opts); 9828 case llvm::Triple::Bitrig: 9829 return new BitrigI386TargetInfo(Triple, Opts); 9830 case llvm::Triple::FreeBSD: 9831 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9832 case llvm::Triple::KFreeBSD: 9833 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9834 case llvm::Triple::Minix: 9835 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9836 case llvm::Triple::Solaris: 9837 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9838 case llvm::Triple::Win32: { 9839 switch (Triple.getEnvironment()) { 9840 case llvm::Triple::Cygnus: 9841 return new CygwinX86_32TargetInfo(Triple, Opts); 9842 case llvm::Triple::GNU: 9843 return new MinGWX86_32TargetInfo(Triple, Opts); 9844 case llvm::Triple::Itanium: 9845 case llvm::Triple::MSVC: 9846 default: // Assume MSVC for unknown environments 9847 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9848 } 9849 } 9850 case llvm::Triple::Haiku: 9851 return new HaikuX86_32TargetInfo(Triple, Opts); 9852 case llvm::Triple::RTEMS: 9853 return new RTEMSX86_32TargetInfo(Triple, Opts); 9854 case llvm::Triple::NaCl: 9855 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9856 case llvm::Triple::ELFIAMCU: 9857 return new MCUX86_32TargetInfo(Triple, Opts); 9858 default: 9859 return new X86_32TargetInfo(Triple, Opts); 9860 } 9861 9862 case llvm::Triple::x86_64: 9863 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9864 return new DarwinX86_64TargetInfo(Triple, Opts); 9865 9866 switch (os) { 9867 case llvm::Triple::Ananas: 9868 return new AnanasTargetInfo<X86_64TargetInfo>(Triple, Opts); 9869 case llvm::Triple::CloudABI: 9870 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9871 case llvm::Triple::Linux: { 9872 switch (Triple.getEnvironment()) { 9873 default: 9874 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9875 case llvm::Triple::Android: 9876 return new AndroidX86_64TargetInfo(Triple, Opts); 9877 } 9878 } 9879 case llvm::Triple::DragonFly: 9880 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9881 case llvm::Triple::NetBSD: 9882 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9883 case llvm::Triple::OpenBSD: 9884 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9885 case llvm::Triple::Bitrig: 9886 return new BitrigX86_64TargetInfo(Triple, Opts); 9887 case llvm::Triple::FreeBSD: 9888 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9889 case llvm::Triple::Fuchsia: 9890 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9891 case llvm::Triple::KFreeBSD: 9892 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9893 case llvm::Triple::Solaris: 9894 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9895 case llvm::Triple::Win32: { 9896 switch (Triple.getEnvironment()) { 9897 case llvm::Triple::Cygnus: 9898 return new CygwinX86_64TargetInfo(Triple, Opts); 9899 case llvm::Triple::GNU: 9900 return new MinGWX86_64TargetInfo(Triple, Opts); 9901 case llvm::Triple::MSVC: 9902 default: // Assume MSVC for unknown environments 9903 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9904 } 9905 } 9906 case llvm::Triple::Haiku: 9907 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9908 case llvm::Triple::NaCl: 9909 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9910 case llvm::Triple::PS4: 9911 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9912 default: 9913 return new X86_64TargetInfo(Triple, Opts); 9914 } 9915 9916 case llvm::Triple::spir: { 9917 if (Triple.getOS() != llvm::Triple::UnknownOS || 9918 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9919 return nullptr; 9920 return new SPIR32TargetInfo(Triple, Opts); 9921 } 9922 case llvm::Triple::spir64: { 9923 if (Triple.getOS() != llvm::Triple::UnknownOS || 9924 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9925 return nullptr; 9926 return new SPIR64TargetInfo(Triple, Opts); 9927 } 9928 case llvm::Triple::wasm32: 9929 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9930 Triple.getVendor() != llvm::Triple::UnknownVendor || 9931 Triple.getOS() != llvm::Triple::UnknownOS || 9932 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9933 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9934 return nullptr; 9935 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9936 case llvm::Triple::wasm64: 9937 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9938 Triple.getVendor() != llvm::Triple::UnknownVendor || 9939 Triple.getOS() != llvm::Triple::UnknownOS || 9940 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9941 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9942 return nullptr; 9943 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9944 9945 case llvm::Triple::renderscript32: 9946 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9947 case llvm::Triple::renderscript64: 9948 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9949 } 9950 } 9951 9952 /// CreateTargetInfo - Return the target info object for the specified target 9953 /// options. 9954 TargetInfo * 9955 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9956 const std::shared_ptr<TargetOptions> &Opts) { 9957 llvm::Triple Triple(Opts->Triple); 9958 9959 // Construct the target 9960 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9961 if (!Target) { 9962 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9963 return nullptr; 9964 } 9965 Target->TargetOpts = Opts; 9966 9967 // Set the target CPU if specified. 9968 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9969 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9970 return nullptr; 9971 } 9972 9973 // Set the target ABI if specified. 9974 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 9975 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 9976 return nullptr; 9977 } 9978 9979 // Set the fp math unit. 9980 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 9981 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 9982 return nullptr; 9983 } 9984 9985 // Compute the default target features, we need the target to handle this 9986 // because features may have dependencies on one another. 9987 llvm::StringMap<bool> Features; 9988 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 9989 Opts->FeaturesAsWritten)) 9990 return nullptr; 9991 9992 // Add the features to the compile options. 9993 Opts->Features.clear(); 9994 for (const auto &F : Features) 9995 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 9996 9997 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 9998 return nullptr; 9999 10000 Target->setSupportedOpenCLOpts(); 10001 Target->setOpenCLExtensionOpts(); 10002 10003 if (!Target->validateTarget(Diags)) 10004 return nullptr; 10005 10006 return Target.release(); 10007 } 10008