1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/OwningPtr.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Type.h" 31 #include <algorithm> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const std::string& triple) : TgtInfo(triple) {} 77 virtual void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "5621"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("__MACH__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.AddressSanitizer) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 98 99 if (!Opts.ObjCAutoRefCount) { 100 // __weak is always defined, for use in blocks and with objc pointers. 101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 102 103 // Darwin defines __strong even in C mode (just to nothing). 104 if (Opts.getGC() != LangOptions::NonGC) 105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 106 else 107 Builder.defineMacro("__strong", ""); 108 109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 110 // allow this in C, since one might have block pointers in structs that 111 // are used in pure C code and in Objective-C ARC. 112 Builder.defineMacro("__unsafe_unretained", ""); 113 } 114 115 if (Opts.Static) 116 Builder.defineMacro("__STATIC__"); 117 else 118 Builder.defineMacro("__DYNAMIC__"); 119 120 if (Opts.POSIXThreads) 121 Builder.defineMacro("_REENTRANT"); 122 123 // Get the platform type and version number from the triple. 124 unsigned Maj, Min, Rev; 125 if (Triple.isMacOSX()) { 126 Triple.getMacOSXVersion(Maj, Min, Rev); 127 PlatformName = "macosx"; 128 } else { 129 Triple.getOSVersion(Maj, Min, Rev); 130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 131 } 132 133 // If -target arch-pc-win32-macho option specified, we're 134 // generating code for Win32 ABI. No need to emit 135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 136 if (PlatformName == "win32") { 137 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 138 return; 139 } 140 141 // Set the appropriate OS version define. 142 if (Triple.getOS() == llvm::Triple::IOS) { 143 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 144 char Str[6]; 145 Str[0] = '0' + Maj; 146 Str[1] = '0' + (Min / 10); 147 Str[2] = '0' + (Min % 10); 148 Str[3] = '0' + (Rev / 10); 149 Str[4] = '0' + (Rev % 10); 150 Str[5] = '\0'; 151 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str); 152 } else { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Triple.getEnvironmentName().empty() && "Invalid environment!"); 158 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[5]; 160 Str[0] = '0' + (Maj / 10); 161 Str[1] = '0' + (Maj % 10); 162 Str[2] = '0' + std::min(Min, 9U); 163 Str[3] = '0' + std::min(Rev, 9U); 164 Str[4] = '\0'; 165 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 166 } 167 168 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 169 } 170 171 namespace { 172 template<typename Target> 173 class DarwinTargetInfo : public OSTargetInfo<Target> { 174 protected: 175 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 176 MacroBuilder &Builder) const { 177 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 178 this->PlatformMinVersion); 179 } 180 181 public: 182 DarwinTargetInfo(const std::string& triple) : 183 OSTargetInfo<Target>(triple) { 184 llvm::Triple T = llvm::Triple(triple); 185 this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7); 186 this->MCountName = "\01mcount"; 187 } 188 189 virtual std::string isValidSectionSpecifier(StringRef SR) const { 190 // Let MCSectionMachO validate this. 191 StringRef Segment, Section; 192 unsigned TAA, StubSize; 193 bool HasTAA; 194 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 195 TAA, HasTAA, StubSize); 196 } 197 198 virtual const char *getStaticInitSectionSpecifier() const { 199 // FIXME: We should return 0 when building kexts. 200 return "__TEXT,__StaticInit,regular,pure_instructions"; 201 } 202 203 /// Darwin does not support protected visibility. Darwin's "default" 204 /// is very similar to ELF's "protected"; Darwin requires a "weak" 205 /// attribute on declarations that can be dynamically replaced. 206 virtual bool hasProtectedVisibility() const { 207 return false; 208 } 209 }; 210 211 212 // DragonFlyBSD Target 213 template<typename Target> 214 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 215 protected: 216 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 217 MacroBuilder &Builder) const { 218 // DragonFly defines; list based off of gcc output 219 Builder.defineMacro("__DragonFly__"); 220 Builder.defineMacro("__DragonFly_cc_version", "100001"); 221 Builder.defineMacro("__ELF__"); 222 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 223 Builder.defineMacro("__tune_i386__"); 224 DefineStd(Builder, "unix", Opts); 225 } 226 public: 227 DragonFlyBSDTargetInfo(const std::string &triple) 228 : OSTargetInfo<Target>(triple) { 229 this->UserLabelPrefix = ""; 230 231 llvm::Triple Triple(triple); 232 switch (Triple.getArch()) { 233 default: 234 case llvm::Triple::x86: 235 case llvm::Triple::x86_64: 236 this->MCountName = ".mcount"; 237 break; 238 } 239 } 240 }; 241 242 // FreeBSD Target 243 template<typename Target> 244 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 245 protected: 246 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 247 MacroBuilder &Builder) const { 248 // FreeBSD defines; list based off of gcc output 249 250 unsigned Release = Triple.getOSMajorVersion(); 251 if (Release == 0U) 252 Release = 8; 253 254 Builder.defineMacro("__FreeBSD__", Twine(Release)); 255 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 256 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 257 DefineStd(Builder, "unix", Opts); 258 Builder.defineMacro("__ELF__"); 259 } 260 public: 261 FreeBSDTargetInfo(const std::string &triple) 262 : OSTargetInfo<Target>(triple) { 263 this->UserLabelPrefix = ""; 264 265 llvm::Triple Triple(triple); 266 switch (Triple.getArch()) { 267 default: 268 case llvm::Triple::x86: 269 case llvm::Triple::x86_64: 270 this->MCountName = ".mcount"; 271 break; 272 case llvm::Triple::mips: 273 case llvm::Triple::mipsel: 274 case llvm::Triple::ppc: 275 case llvm::Triple::ppc64: 276 this->MCountName = "_mcount"; 277 break; 278 case llvm::Triple::arm: 279 this->MCountName = "__mcount"; 280 break; 281 } 282 283 } 284 }; 285 286 // Minix Target 287 template<typename Target> 288 class MinixTargetInfo : public OSTargetInfo<Target> { 289 protected: 290 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 291 MacroBuilder &Builder) const { 292 // Minix defines 293 294 Builder.defineMacro("__minix", "3"); 295 Builder.defineMacro("_EM_WSIZE", "4"); 296 Builder.defineMacro("_EM_PSIZE", "4"); 297 Builder.defineMacro("_EM_SSIZE", "2"); 298 Builder.defineMacro("_EM_LSIZE", "4"); 299 Builder.defineMacro("_EM_FSIZE", "4"); 300 Builder.defineMacro("_EM_DSIZE", "8"); 301 Builder.defineMacro("__ELF__"); 302 DefineStd(Builder, "unix", Opts); 303 } 304 public: 305 MinixTargetInfo(const std::string &triple) 306 : OSTargetInfo<Target>(triple) { 307 this->UserLabelPrefix = ""; 308 } 309 }; 310 311 // Linux target 312 template<typename Target> 313 class LinuxTargetInfo : public OSTargetInfo<Target> { 314 protected: 315 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 316 MacroBuilder &Builder) const { 317 // Linux defines; list based off of gcc output 318 DefineStd(Builder, "unix", Opts); 319 DefineStd(Builder, "linux", Opts); 320 Builder.defineMacro("__gnu_linux__"); 321 Builder.defineMacro("__ELF__"); 322 if (Triple.getEnvironment() == llvm::Triple::Android) 323 Builder.defineMacro("__ANDROID__", "1"); 324 if (Opts.POSIXThreads) 325 Builder.defineMacro("_REENTRANT"); 326 if (Opts.CPlusPlus) 327 Builder.defineMacro("_GNU_SOURCE"); 328 } 329 public: 330 LinuxTargetInfo(const std::string& triple) 331 : OSTargetInfo<Target>(triple) { 332 this->UserLabelPrefix = ""; 333 this->WIntType = TargetInfo::UnsignedInt; 334 } 335 336 virtual const char *getStaticInitSectionSpecifier() const { 337 return ".text.startup"; 338 } 339 }; 340 341 // NetBSD Target 342 template<typename Target> 343 class NetBSDTargetInfo : public OSTargetInfo<Target> { 344 protected: 345 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 346 MacroBuilder &Builder) const { 347 // NetBSD defines; list based off of gcc output 348 Builder.defineMacro("__NetBSD__"); 349 Builder.defineMacro("__unix__"); 350 Builder.defineMacro("__ELF__"); 351 if (Opts.POSIXThreads) 352 Builder.defineMacro("_POSIX_THREADS"); 353 } 354 public: 355 NetBSDTargetInfo(const std::string &triple) 356 : OSTargetInfo<Target>(triple) { 357 this->UserLabelPrefix = ""; 358 } 359 }; 360 361 // OpenBSD Target 362 template<typename Target> 363 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 364 protected: 365 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 366 MacroBuilder &Builder) const { 367 // OpenBSD defines; list based off of gcc output 368 369 Builder.defineMacro("__OpenBSD__"); 370 DefineStd(Builder, "unix", Opts); 371 Builder.defineMacro("__ELF__"); 372 if (Opts.POSIXThreads) 373 Builder.defineMacro("_REENTRANT"); 374 } 375 public: 376 OpenBSDTargetInfo(const std::string &triple) 377 : OSTargetInfo<Target>(triple) { 378 this->UserLabelPrefix = ""; 379 this->TLSSupported = false; 380 381 llvm::Triple Triple(triple); 382 switch (Triple.getArch()) { 383 default: 384 case llvm::Triple::x86: 385 case llvm::Triple::x86_64: 386 case llvm::Triple::arm: 387 case llvm::Triple::sparc: 388 this->MCountName = "__mcount"; 389 break; 390 case llvm::Triple::mips64: 391 case llvm::Triple::mips64el: 392 case llvm::Triple::ppc: 393 case llvm::Triple::sparcv9: 394 this->MCountName = "_mcount"; 395 break; 396 } 397 } 398 }; 399 400 // Bitrig Target 401 template<typename Target> 402 class BitrigTargetInfo : public OSTargetInfo<Target> { 403 protected: 404 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 405 MacroBuilder &Builder) const { 406 // Bitrig defines; list based off of gcc output 407 408 Builder.defineMacro("__Bitrig__"); 409 DefineStd(Builder, "unix", Opts); 410 Builder.defineMacro("__ELF__"); 411 if (Opts.POSIXThreads) 412 Builder.defineMacro("_REENTRANT"); 413 } 414 public: 415 BitrigTargetInfo(const std::string &triple) 416 : OSTargetInfo<Target>(triple) { 417 this->UserLabelPrefix = ""; 418 this->TLSSupported = false; 419 this->MCountName = "__mcount"; 420 } 421 }; 422 423 // PSP Target 424 template<typename Target> 425 class PSPTargetInfo : public OSTargetInfo<Target> { 426 protected: 427 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 428 MacroBuilder &Builder) const { 429 // PSP defines; list based on the output of the pspdev gcc toolchain. 430 Builder.defineMacro("PSP"); 431 Builder.defineMacro("_PSP"); 432 Builder.defineMacro("__psp__"); 433 Builder.defineMacro("__ELF__"); 434 } 435 public: 436 PSPTargetInfo(const std::string& triple) 437 : OSTargetInfo<Target>(triple) { 438 this->UserLabelPrefix = ""; 439 } 440 }; 441 442 // PS3 PPU Target 443 template<typename Target> 444 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 445 protected: 446 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 447 MacroBuilder &Builder) const { 448 // PS3 PPU defines. 449 Builder.defineMacro("__PPC__"); 450 Builder.defineMacro("__PPU__"); 451 Builder.defineMacro("__CELLOS_LV2__"); 452 Builder.defineMacro("__ELF__"); 453 Builder.defineMacro("__LP32__"); 454 Builder.defineMacro("_ARCH_PPC64"); 455 Builder.defineMacro("__powerpc64__"); 456 } 457 public: 458 PS3PPUTargetInfo(const std::string& triple) 459 : OSTargetInfo<Target>(triple) { 460 this->UserLabelPrefix = ""; 461 this->LongWidth = this->LongAlign = 32; 462 this->PointerWidth = this->PointerAlign = 32; 463 this->IntMaxType = TargetInfo::SignedLongLong; 464 this->UIntMaxType = TargetInfo::UnsignedLongLong; 465 this->Int64Type = TargetInfo::SignedLongLong; 466 this->SizeType = TargetInfo::UnsignedInt; 467 this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 468 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 469 } 470 }; 471 472 // FIXME: Need a real SPU target. 473 // PS3 SPU Target 474 template<typename Target> 475 class PS3SPUTargetInfo : public OSTargetInfo<Target> { 476 protected: 477 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 478 MacroBuilder &Builder) const { 479 // PS3 PPU defines. 480 Builder.defineMacro("__SPU__"); 481 Builder.defineMacro("__ELF__"); 482 } 483 public: 484 PS3SPUTargetInfo(const std::string& triple) 485 : OSTargetInfo<Target>(triple) { 486 this->UserLabelPrefix = ""; 487 } 488 }; 489 490 // AuroraUX target 491 template<typename Target> 492 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 493 protected: 494 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 495 MacroBuilder &Builder) const { 496 DefineStd(Builder, "sun", Opts); 497 DefineStd(Builder, "unix", Opts); 498 Builder.defineMacro("__ELF__"); 499 Builder.defineMacro("__svr4__"); 500 Builder.defineMacro("__SVR4"); 501 } 502 public: 503 AuroraUXTargetInfo(const std::string& triple) 504 : OSTargetInfo<Target>(triple) { 505 this->UserLabelPrefix = ""; 506 this->WCharType = this->SignedLong; 507 // FIXME: WIntType should be SignedLong 508 } 509 }; 510 511 // Solaris target 512 template<typename Target> 513 class SolarisTargetInfo : public OSTargetInfo<Target> { 514 protected: 515 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 516 MacroBuilder &Builder) const { 517 DefineStd(Builder, "sun", Opts); 518 DefineStd(Builder, "unix", Opts); 519 Builder.defineMacro("__ELF__"); 520 Builder.defineMacro("__svr4__"); 521 Builder.defineMacro("__SVR4"); 522 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 523 // newer, but to 500 for everything else. feature_test.h has a check to 524 // ensure that you are not using C99 with an old version of X/Open or C89 525 // with a new version. 526 if (Opts.C99 || Opts.C11) 527 Builder.defineMacro("_XOPEN_SOURCE", "600"); 528 else 529 Builder.defineMacro("_XOPEN_SOURCE", "500"); 530 if (Opts.CPlusPlus) 531 Builder.defineMacro("__C99FEATURES__"); 532 Builder.defineMacro("_LARGEFILE_SOURCE"); 533 Builder.defineMacro("_LARGEFILE64_SOURCE"); 534 Builder.defineMacro("__EXTENSIONS__"); 535 Builder.defineMacro("_REENTRANT"); 536 } 537 public: 538 SolarisTargetInfo(const std::string& triple) 539 : OSTargetInfo<Target>(triple) { 540 this->UserLabelPrefix = ""; 541 this->WCharType = this->SignedInt; 542 // FIXME: WIntType should be SignedLong 543 } 544 }; 545 546 // Windows target 547 template<typename Target> 548 class WindowsTargetInfo : public OSTargetInfo<Target> { 549 protected: 550 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 551 MacroBuilder &Builder) const { 552 Builder.defineMacro("_WIN32"); 553 } 554 void getVisualStudioDefines(const LangOptions &Opts, 555 MacroBuilder &Builder) const { 556 if (Opts.CPlusPlus) { 557 if (Opts.RTTI) 558 Builder.defineMacro("_CPPRTTI"); 559 560 if (Opts.Exceptions) 561 Builder.defineMacro("_CPPUNWIND"); 562 } 563 564 if (!Opts.CharIsSigned) 565 Builder.defineMacro("_CHAR_UNSIGNED"); 566 567 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 568 // but it works for now. 569 if (Opts.POSIXThreads) 570 Builder.defineMacro("_MT"); 571 572 if (Opts.MSCVersion != 0) 573 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 574 575 if (Opts.MicrosoftExt) { 576 Builder.defineMacro("_MSC_EXTENSIONS"); 577 578 if (Opts.CPlusPlus0x) { 579 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 580 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 581 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 582 } 583 } 584 585 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 586 } 587 588 public: 589 WindowsTargetInfo(const std::string &triple) 590 : OSTargetInfo<Target>(triple) {} 591 }; 592 593 template <typename Target> 594 class NaClTargetInfo : public OSTargetInfo<Target> { 595 protected: 596 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 597 MacroBuilder &Builder) const { 598 if (Opts.POSIXThreads) 599 Builder.defineMacro("_REENTRANT"); 600 if (Opts.CPlusPlus) 601 Builder.defineMacro("_GNU_SOURCE"); 602 603 DefineStd(Builder, "unix", Opts); 604 Builder.defineMacro("__ELF__"); 605 Builder.defineMacro("__native_client__"); 606 } 607 public: 608 NaClTargetInfo(const std::string &triple) 609 : OSTargetInfo<Target>(triple) { 610 this->UserLabelPrefix = ""; 611 this->LongAlign = 32; 612 this->LongWidth = 32; 613 this->PointerAlign = 32; 614 this->PointerWidth = 32; 615 this->IntMaxType = TargetInfo::SignedLongLong; 616 this->UIntMaxType = TargetInfo::UnsignedLongLong; 617 this->Int64Type = TargetInfo::SignedLongLong; 618 this->DoubleAlign = 64; 619 this->LongDoubleWidth = 64; 620 this->LongDoubleAlign = 64; 621 this->SizeType = TargetInfo::UnsignedInt; 622 this->PtrDiffType = TargetInfo::SignedInt; 623 this->IntPtrType = TargetInfo::SignedInt; 624 this->RegParmMax = 2; 625 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 626 this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 627 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 628 } 629 }; 630 } // end anonymous namespace. 631 632 //===----------------------------------------------------------------------===// 633 // Specific target implementations. 634 //===----------------------------------------------------------------------===// 635 636 namespace { 637 // PPC abstract base class 638 class PPCTargetInfo : public TargetInfo { 639 static const Builtin::Info BuiltinInfo[]; 640 static const char * const GCCRegNames[]; 641 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 642 std::string CPU; 643 public: 644 PPCTargetInfo(const std::string& triple) : TargetInfo(triple) { 645 LongDoubleWidth = LongDoubleAlign = 128; 646 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 647 } 648 649 /// \brief Flags for architecture specific defines. 650 typedef enum { 651 ArchDefineNone = 0, 652 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 653 ArchDefinePpcgr = 1 << 1, 654 ArchDefinePpcsq = 1 << 2, 655 ArchDefine440 = 1 << 3, 656 ArchDefine603 = 1 << 4, 657 ArchDefine604 = 1 << 5, 658 ArchDefinePwr4 = 1 << 6, 659 ArchDefinePwr6 = 1 << 7 660 } ArchDefineTypes; 661 662 virtual bool setCPU(const std::string &Name) { 663 bool CPUKnown = llvm::StringSwitch<bool>(Name) 664 .Case("generic", true) 665 .Case("440", true) 666 .Case("450", true) 667 .Case("601", true) 668 .Case("602", true) 669 .Case("603", true) 670 .Case("603e", true) 671 .Case("603ev", true) 672 .Case("604", true) 673 .Case("604e", true) 674 .Case("620", true) 675 .Case("g3", true) 676 .Case("7400", true) 677 .Case("g4", true) 678 .Case("7450", true) 679 .Case("g4+", true) 680 .Case("750", true) 681 .Case("970", true) 682 .Case("g5", true) 683 .Case("a2", true) 684 .Case("e500mc", true) 685 .Case("e5500", true) 686 .Case("pwr6", true) 687 .Case("pwr7", true) 688 .Case("ppc", true) 689 .Case("ppc64", true) 690 .Default(false); 691 692 if (CPUKnown) 693 CPU = Name; 694 695 return CPUKnown; 696 } 697 698 virtual void getTargetBuiltins(const Builtin::Info *&Records, 699 unsigned &NumRecords) const { 700 Records = BuiltinInfo; 701 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 702 } 703 704 virtual bool isCLZForZeroUndef() const { return false; } 705 706 virtual void getTargetDefines(const LangOptions &Opts, 707 MacroBuilder &Builder) const; 708 709 virtual bool hasFeature(StringRef Feature) const; 710 711 virtual void getGCCRegNames(const char * const *&Names, 712 unsigned &NumNames) const; 713 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 714 unsigned &NumAliases) const; 715 virtual bool validateAsmConstraint(const char *&Name, 716 TargetInfo::ConstraintInfo &Info) const { 717 switch (*Name) { 718 default: return false; 719 case 'O': // Zero 720 break; 721 case 'b': // Base register 722 case 'f': // Floating point register 723 Info.setAllowsRegister(); 724 break; 725 // FIXME: The following are added to allow parsing. 726 // I just took a guess at what the actions should be. 727 // Also, is more specific checking needed? I.e. specific registers? 728 case 'd': // Floating point register (containing 64-bit value) 729 case 'v': // Altivec vector register 730 Info.setAllowsRegister(); 731 break; 732 case 'w': 733 switch (Name[1]) { 734 case 'd':// VSX vector register to hold vector double data 735 case 'f':// VSX vector register to hold vector float data 736 case 's':// VSX vector register to hold scalar float data 737 case 'a':// Any VSX register 738 break; 739 default: 740 return false; 741 } 742 Info.setAllowsRegister(); 743 Name++; // Skip over 'w'. 744 break; 745 case 'h': // `MQ', `CTR', or `LINK' register 746 case 'q': // `MQ' register 747 case 'c': // `CTR' register 748 case 'l': // `LINK' register 749 case 'x': // `CR' register (condition register) number 0 750 case 'y': // `CR' register (condition register) 751 case 'z': // `XER[CA]' carry bit (part of the XER register) 752 Info.setAllowsRegister(); 753 break; 754 case 'I': // Signed 16-bit constant 755 case 'J': // Unsigned 16-bit constant shifted left 16 bits 756 // (use `L' instead for SImode constants) 757 case 'K': // Unsigned 16-bit constant 758 case 'L': // Signed 16-bit constant shifted left 16 bits 759 case 'M': // Constant larger than 31 760 case 'N': // Exact power of 2 761 case 'P': // Constant whose negation is a signed 16-bit constant 762 case 'G': // Floating point constant that can be loaded into a 763 // register with one instruction per word 764 case 'H': // Integer/Floating point constant that can be loaded 765 // into a register using three instructions 766 break; 767 case 'm': // Memory operand. Note that on PowerPC targets, m can 768 // include addresses that update the base register. It 769 // is therefore only safe to use `m' in an asm statement 770 // if that asm statement accesses the operand exactly once. 771 // The asm statement must also use `%U<opno>' as a 772 // placeholder for the "update" flag in the corresponding 773 // load or store instruction. For example: 774 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 775 // is correct but: 776 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 777 // is not. Use es rather than m if you don't want the base 778 // register to be updated. 779 case 'e': 780 if (Name[1] != 's') 781 return false; 782 // es: A "stable" memory operand; that is, one which does not 783 // include any automodification of the base register. Unlike 784 // `m', this constraint can be used in asm statements that 785 // might access the operand several times, or that might not 786 // access it at all. 787 Info.setAllowsMemory(); 788 Name++; // Skip over 'e'. 789 break; 790 case 'Q': // Memory operand that is an offset from a register (it is 791 // usually better to use `m' or `es' in asm statements) 792 case 'Z': // Memory operand that is an indexed or indirect from a 793 // register (it is usually better to use `m' or `es' in 794 // asm statements) 795 Info.setAllowsMemory(); 796 Info.setAllowsRegister(); 797 break; 798 case 'R': // AIX TOC entry 799 case 'a': // Address operand that is an indexed or indirect from a 800 // register (`p' is preferable for asm statements) 801 case 'S': // Constant suitable as a 64-bit mask operand 802 case 'T': // Constant suitable as a 32-bit mask operand 803 case 'U': // System V Release 4 small data area reference 804 case 't': // AND masks that can be performed by two rldic{l, r} 805 // instructions 806 case 'W': // Vector constant that does not require memory 807 case 'j': // Vector constant that is all zeros. 808 break; 809 // End FIXME. 810 } 811 return true; 812 } 813 virtual const char *getClobbers() const { 814 return ""; 815 } 816 }; 817 818 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 819 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 820 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 821 ALL_LANGUAGES }, 822 #include "clang/Basic/BuiltinsPPC.def" 823 }; 824 825 826 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 827 /// #defines that are not tied to a specific subtarget. 828 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 829 MacroBuilder &Builder) const { 830 // Target identification. 831 Builder.defineMacro("__ppc__"); 832 Builder.defineMacro("_ARCH_PPC"); 833 Builder.defineMacro("__powerpc__"); 834 Builder.defineMacro("__POWERPC__"); 835 if (PointerWidth == 64) { 836 Builder.defineMacro("_ARCH_PPC64"); 837 Builder.defineMacro("__powerpc64__"); 838 Builder.defineMacro("__ppc64__"); 839 } else { 840 Builder.defineMacro("__ppc__"); 841 } 842 843 // Target properties. 844 if (getTriple().getOS() != llvm::Triple::NetBSD && 845 getTriple().getOS() != llvm::Triple::OpenBSD) 846 Builder.defineMacro("_BIG_ENDIAN"); 847 Builder.defineMacro("__BIG_ENDIAN__"); 848 849 // Subtarget options. 850 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 851 Builder.defineMacro("__REGISTER_PREFIX__", ""); 852 853 // FIXME: Should be controlled by command line option. 854 Builder.defineMacro("__LONG_DOUBLE_128__"); 855 856 if (Opts.AltiVec) { 857 Builder.defineMacro("__VEC__", "10206"); 858 Builder.defineMacro("__ALTIVEC__"); 859 } 860 861 // CPU identification. 862 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 863 .Case("440", ArchDefineName) 864 .Case("450", ArchDefineName | ArchDefine440) 865 .Case("601", ArchDefineName) 866 .Case("602", ArchDefineName | ArchDefinePpcgr) 867 .Case("603", ArchDefineName | ArchDefinePpcgr) 868 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 869 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 870 .Case("604", ArchDefineName | ArchDefinePpcgr) 871 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 872 .Case("620", ArchDefineName | ArchDefinePpcgr) 873 .Case("7400", ArchDefineName | ArchDefinePpcgr) 874 .Case("7450", ArchDefineName | ArchDefinePpcgr) 875 .Case("750", ArchDefineName | ArchDefinePpcgr) 876 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 877 | ArchDefinePpcsq) 878 .Case("pwr6", ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 879 .Case("pwr7", ArchDefineName | ArchDefinePwr6 | ArchDefinePpcgr 880 | ArchDefinePpcsq) 881 .Default(ArchDefineNone); 882 883 if (defs & ArchDefineName) 884 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 885 if (defs & ArchDefinePpcgr) 886 Builder.defineMacro("_ARCH_PPCGR"); 887 if (defs & ArchDefinePpcsq) 888 Builder.defineMacro("_ARCH_PPCSQ"); 889 if (defs & ArchDefine440) 890 Builder.defineMacro("_ARCH_440"); 891 if (defs & ArchDefine603) 892 Builder.defineMacro("_ARCH_603"); 893 if (defs & ArchDefine604) 894 Builder.defineMacro("_ARCH_604"); 895 if (defs & (ArchDefinePwr4 | ArchDefinePwr6)) 896 Builder.defineMacro("_ARCH_PWR4"); 897 if (defs & ArchDefinePwr6) { 898 Builder.defineMacro("_ARCH_PWR5"); 899 Builder.defineMacro("_ARCH_PWR6"); 900 } 901 } 902 903 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 904 return Feature == "powerpc"; 905 } 906 907 908 const char * const PPCTargetInfo::GCCRegNames[] = { 909 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 910 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 911 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 912 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 913 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 914 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 915 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 916 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 917 "mq", "lr", "ctr", "ap", 918 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 919 "xer", 920 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 921 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 922 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 923 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 924 "vrsave", "vscr", 925 "spe_acc", "spefscr", 926 "sfp" 927 }; 928 929 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 930 unsigned &NumNames) const { 931 Names = GCCRegNames; 932 NumNames = llvm::array_lengthof(GCCRegNames); 933 } 934 935 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 936 // While some of these aliases do map to different registers 937 // they still share the same register name. 938 { { "0" }, "r0" }, 939 { { "1"}, "r1" }, 940 { { "2" }, "r2" }, 941 { { "3" }, "r3" }, 942 { { "4" }, "r4" }, 943 { { "5" }, "r5" }, 944 { { "6" }, "r6" }, 945 { { "7" }, "r7" }, 946 { { "8" }, "r8" }, 947 { { "9" }, "r9" }, 948 { { "10" }, "r10" }, 949 { { "11" }, "r11" }, 950 { { "12" }, "r12" }, 951 { { "13" }, "r13" }, 952 { { "14" }, "r14" }, 953 { { "15" }, "r15" }, 954 { { "16" }, "r16" }, 955 { { "17" }, "r17" }, 956 { { "18" }, "r18" }, 957 { { "19" }, "r19" }, 958 { { "20" }, "r20" }, 959 { { "21" }, "r21" }, 960 { { "22" }, "r22" }, 961 { { "23" }, "r23" }, 962 { { "24" }, "r24" }, 963 { { "25" }, "r25" }, 964 { { "26" }, "r26" }, 965 { { "27" }, "r27" }, 966 { { "28" }, "r28" }, 967 { { "29" }, "r29" }, 968 { { "30" }, "r30" }, 969 { { "31" }, "r31" }, 970 { { "fr0" }, "f0" }, 971 { { "fr1" }, "f1" }, 972 { { "fr2" }, "f2" }, 973 { { "fr3" }, "f3" }, 974 { { "fr4" }, "f4" }, 975 { { "fr5" }, "f5" }, 976 { { "fr6" }, "f6" }, 977 { { "fr7" }, "f7" }, 978 { { "fr8" }, "f8" }, 979 { { "fr9" }, "f9" }, 980 { { "fr10" }, "f10" }, 981 { { "fr11" }, "f11" }, 982 { { "fr12" }, "f12" }, 983 { { "fr13" }, "f13" }, 984 { { "fr14" }, "f14" }, 985 { { "fr15" }, "f15" }, 986 { { "fr16" }, "f16" }, 987 { { "fr17" }, "f17" }, 988 { { "fr18" }, "f18" }, 989 { { "fr19" }, "f19" }, 990 { { "fr20" }, "f20" }, 991 { { "fr21" }, "f21" }, 992 { { "fr22" }, "f22" }, 993 { { "fr23" }, "f23" }, 994 { { "fr24" }, "f24" }, 995 { { "fr25" }, "f25" }, 996 { { "fr26" }, "f26" }, 997 { { "fr27" }, "f27" }, 998 { { "fr28" }, "f28" }, 999 { { "fr29" }, "f29" }, 1000 { { "fr30" }, "f30" }, 1001 { { "fr31" }, "f31" }, 1002 { { "cc" }, "cr0" }, 1003 }; 1004 1005 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1006 unsigned &NumAliases) const { 1007 Aliases = GCCRegAliases; 1008 NumAliases = llvm::array_lengthof(GCCRegAliases); 1009 } 1010 } // end anonymous namespace. 1011 1012 namespace { 1013 class PPC32TargetInfo : public PPCTargetInfo { 1014 public: 1015 PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) { 1016 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1017 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1018 1019 switch (getTriple().getOS()) { 1020 case llvm::Triple::Linux: 1021 case llvm::Triple::FreeBSD: 1022 case llvm::Triple::NetBSD: 1023 SizeType = UnsignedInt; 1024 PtrDiffType = SignedInt; 1025 IntPtrType = SignedInt; 1026 break; 1027 default: 1028 break; 1029 } 1030 1031 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1032 LongDoubleWidth = LongDoubleAlign = 64; 1033 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1034 } 1035 } 1036 1037 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1038 // This is the ELF definition, and is overridden by the Darwin sub-target 1039 return TargetInfo::PowerABIBuiltinVaList; 1040 } 1041 }; 1042 } // end anonymous namespace. 1043 1044 namespace { 1045 class PPC64TargetInfo : public PPCTargetInfo { 1046 public: 1047 PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) { 1048 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1049 IntMaxType = SignedLong; 1050 UIntMaxType = UnsignedLong; 1051 Int64Type = SignedLong; 1052 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1053 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"; 1054 1055 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1056 LongDoubleWidth = LongDoubleAlign = 64; 1057 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1058 } 1059 } 1060 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1061 return TargetInfo::CharPtrBuiltinVaList; 1062 } 1063 }; 1064 } // end anonymous namespace. 1065 1066 1067 namespace { 1068 class DarwinPPC32TargetInfo : 1069 public DarwinTargetInfo<PPC32TargetInfo> { 1070 public: 1071 DarwinPPC32TargetInfo(const std::string& triple) 1072 : DarwinTargetInfo<PPC32TargetInfo>(triple) { 1073 HasAlignMac68kSupport = true; 1074 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1075 LongLongAlign = 32; 1076 SuitableAlign = 128; 1077 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1078 "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1079 } 1080 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1081 return TargetInfo::CharPtrBuiltinVaList; 1082 } 1083 }; 1084 1085 class DarwinPPC64TargetInfo : 1086 public DarwinTargetInfo<PPC64TargetInfo> { 1087 public: 1088 DarwinPPC64TargetInfo(const std::string& triple) 1089 : DarwinTargetInfo<PPC64TargetInfo>(triple) { 1090 HasAlignMac68kSupport = true; 1091 SuitableAlign = 128; 1092 } 1093 }; 1094 } // end anonymous namespace. 1095 1096 namespace { 1097 static const unsigned NVPTXAddrSpaceMap[] = { 1098 1, // opencl_global 1099 3, // opencl_local 1100 4, // opencl_constant 1101 1, // cuda_device 1102 4, // cuda_constant 1103 3, // cuda_shared 1104 }; 1105 class NVPTXTargetInfo : public TargetInfo { 1106 static const char * const GCCRegNames[]; 1107 static const Builtin::Info BuiltinInfo[]; 1108 std::vector<llvm::StringRef> AvailableFeatures; 1109 public: 1110 NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) { 1111 BigEndian = false; 1112 TLSSupported = false; 1113 LongWidth = LongAlign = 64; 1114 AddrSpaceMap = &NVPTXAddrSpaceMap; 1115 // Define available target features 1116 // These must be defined in sorted order! 1117 NoAsmVariants = true; 1118 } 1119 virtual void getTargetDefines(const LangOptions &Opts, 1120 MacroBuilder &Builder) const { 1121 Builder.defineMacro("__PTX__"); 1122 Builder.defineMacro("__NVPTX__"); 1123 } 1124 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1125 unsigned &NumRecords) const { 1126 Records = BuiltinInfo; 1127 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1128 } 1129 virtual bool hasFeature(StringRef Feature) const { 1130 return Feature == "ptx" || Feature == "nvptx"; 1131 } 1132 1133 virtual void getGCCRegNames(const char * const *&Names, 1134 unsigned &NumNames) const; 1135 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1136 unsigned &NumAliases) const { 1137 // No aliases. 1138 Aliases = 0; 1139 NumAliases = 0; 1140 } 1141 virtual bool validateAsmConstraint(const char *&Name, 1142 TargetInfo::ConstraintInfo &info) const { 1143 // FIXME: implement 1144 return true; 1145 } 1146 virtual const char *getClobbers() const { 1147 // FIXME: Is this really right? 1148 return ""; 1149 } 1150 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1151 // FIXME: implement 1152 return TargetInfo::CharPtrBuiltinVaList; 1153 } 1154 virtual bool setCPU(const std::string &Name) { 1155 return Name == "sm_10" || Name == "sm_13" || Name == "sm_20"; 1156 } 1157 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 1158 StringRef Name, 1159 bool Enabled) const; 1160 }; 1161 1162 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1163 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1164 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1165 ALL_LANGUAGES }, 1166 #include "clang/Basic/BuiltinsNVPTX.def" 1167 }; 1168 1169 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1170 "r0" 1171 }; 1172 1173 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1174 unsigned &NumNames) const { 1175 Names = GCCRegNames; 1176 NumNames = llvm::array_lengthof(GCCRegNames); 1177 } 1178 1179 bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1180 StringRef Name, 1181 bool Enabled) const { 1182 if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(), 1183 Name)) { 1184 Features[Name] = Enabled; 1185 return true; 1186 } else { 1187 return false; 1188 } 1189 } 1190 1191 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1192 public: 1193 NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) { 1194 PointerWidth = PointerAlign = 32; 1195 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1196 DescriptionString 1197 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1198 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1199 "n16:32:64"; 1200 } 1201 }; 1202 1203 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1204 public: 1205 NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) { 1206 PointerWidth = PointerAlign = 64; 1207 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1208 DescriptionString 1209 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1210 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1211 "n16:32:64"; 1212 } 1213 }; 1214 } 1215 1216 namespace { 1217 // MBlaze abstract base class 1218 class MBlazeTargetInfo : public TargetInfo { 1219 static const char * const GCCRegNames[]; 1220 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 1221 1222 public: 1223 MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) { 1224 DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16"; 1225 } 1226 1227 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1228 unsigned &NumRecords) const { 1229 // FIXME: Implement. 1230 Records = 0; 1231 NumRecords = 0; 1232 } 1233 1234 virtual void getTargetDefines(const LangOptions &Opts, 1235 MacroBuilder &Builder) const; 1236 1237 virtual bool hasFeature(StringRef Feature) const { 1238 return Feature == "mblaze"; 1239 } 1240 1241 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1242 return TargetInfo::CharPtrBuiltinVaList; 1243 } 1244 virtual const char *getTargetPrefix() const { 1245 return "mblaze"; 1246 } 1247 virtual void getGCCRegNames(const char * const *&Names, 1248 unsigned &NumNames) const; 1249 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1250 unsigned &NumAliases) const; 1251 virtual bool validateAsmConstraint(const char *&Name, 1252 TargetInfo::ConstraintInfo &Info) const { 1253 switch (*Name) { 1254 default: return false; 1255 case 'O': // Zero 1256 return true; 1257 case 'b': // Base register 1258 case 'f': // Floating point register 1259 Info.setAllowsRegister(); 1260 return true; 1261 } 1262 } 1263 virtual const char *getClobbers() const { 1264 return ""; 1265 } 1266 }; 1267 1268 /// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific 1269 /// #defines that are not tied to a specific subtarget. 1270 void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts, 1271 MacroBuilder &Builder) const { 1272 // Target identification. 1273 Builder.defineMacro("__microblaze__"); 1274 Builder.defineMacro("_ARCH_MICROBLAZE"); 1275 Builder.defineMacro("__MICROBLAZE__"); 1276 1277 // Target properties. 1278 Builder.defineMacro("_BIG_ENDIAN"); 1279 Builder.defineMacro("__BIG_ENDIAN__"); 1280 1281 // Subtarget options. 1282 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1283 } 1284 1285 1286 const char * const MBlazeTargetInfo::GCCRegNames[] = { 1287 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1288 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1289 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1290 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1291 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 1292 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 1293 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 1294 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 1295 "hi", "lo", "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4", 1296 "$fcc5","$fcc6","$fcc7","$ap", "$rap", "$frp" 1297 }; 1298 1299 void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names, 1300 unsigned &NumNames) const { 1301 Names = GCCRegNames; 1302 NumNames = llvm::array_lengthof(GCCRegNames); 1303 } 1304 1305 const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = { 1306 { {"f0"}, "r0" }, 1307 { {"f1"}, "r1" }, 1308 { {"f2"}, "r2" }, 1309 { {"f3"}, "r3" }, 1310 { {"f4"}, "r4" }, 1311 { {"f5"}, "r5" }, 1312 { {"f6"}, "r6" }, 1313 { {"f7"}, "r7" }, 1314 { {"f8"}, "r8" }, 1315 { {"f9"}, "r9" }, 1316 { {"f10"}, "r10" }, 1317 { {"f11"}, "r11" }, 1318 { {"f12"}, "r12" }, 1319 { {"f13"}, "r13" }, 1320 { {"f14"}, "r14" }, 1321 { {"f15"}, "r15" }, 1322 { {"f16"}, "r16" }, 1323 { {"f17"}, "r17" }, 1324 { {"f18"}, "r18" }, 1325 { {"f19"}, "r19" }, 1326 { {"f20"}, "r20" }, 1327 { {"f21"}, "r21" }, 1328 { {"f22"}, "r22" }, 1329 { {"f23"}, "r23" }, 1330 { {"f24"}, "r24" }, 1331 { {"f25"}, "r25" }, 1332 { {"f26"}, "r26" }, 1333 { {"f27"}, "r27" }, 1334 { {"f28"}, "r28" }, 1335 { {"f29"}, "r29" }, 1336 { {"f30"}, "r30" }, 1337 { {"f31"}, "r31" }, 1338 }; 1339 1340 void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1341 unsigned &NumAliases) const { 1342 Aliases = GCCRegAliases; 1343 NumAliases = llvm::array_lengthof(GCCRegAliases); 1344 } 1345 } // end anonymous namespace. 1346 1347 namespace { 1348 // Namespace for x86 abstract base class 1349 const Builtin::Info BuiltinInfo[] = { 1350 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1351 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1352 ALL_LANGUAGES }, 1353 #include "clang/Basic/BuiltinsX86.def" 1354 }; 1355 1356 static const char* const GCCRegNames[] = { 1357 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1358 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1359 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1360 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1361 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1362 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1363 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1364 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1365 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1366 }; 1367 1368 const TargetInfo::AddlRegName AddlRegNames[] = { 1369 { { "al", "ah", "eax", "rax" }, 0 }, 1370 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1371 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1372 { { "dl", "dh", "edx", "rdx" }, 1 }, 1373 { { "esi", "rsi" }, 4 }, 1374 { { "edi", "rdi" }, 5 }, 1375 { { "esp", "rsp" }, 7 }, 1376 { { "ebp", "rbp" }, 6 }, 1377 }; 1378 1379 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1380 // most of the implementation can be shared. 1381 class X86TargetInfo : public TargetInfo { 1382 enum X86SSEEnum { 1383 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2 1384 } SSELevel; 1385 enum MMX3DNowEnum { 1386 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1387 } MMX3DNowLevel; 1388 1389 bool HasAES; 1390 bool HasPCLMUL; 1391 bool HasLZCNT; 1392 bool HasRDRND; 1393 bool HasBMI; 1394 bool HasBMI2; 1395 bool HasPOPCNT; 1396 bool HasSSE4a; 1397 bool HasFMA4; 1398 bool HasFMA; 1399 bool HasXOP; 1400 bool HasF16C; 1401 1402 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1403 /// 1404 /// Each enumeration represents a particular CPU supported by Clang. These 1405 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1406 enum CPUKind { 1407 CK_Generic, 1408 1409 /// \name i386 1410 /// i386-generation processors. 1411 //@{ 1412 CK_i386, 1413 //@} 1414 1415 /// \name i486 1416 /// i486-generation processors. 1417 //@{ 1418 CK_i486, 1419 CK_WinChipC6, 1420 CK_WinChip2, 1421 CK_C3, 1422 //@} 1423 1424 /// \name i586 1425 /// i586-generation processors, P5 microarchitecture based. 1426 //@{ 1427 CK_i586, 1428 CK_Pentium, 1429 CK_PentiumMMX, 1430 //@} 1431 1432 /// \name i686 1433 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1434 //@{ 1435 CK_i686, 1436 CK_PentiumPro, 1437 CK_Pentium2, 1438 CK_Pentium3, 1439 CK_Pentium3M, 1440 CK_PentiumM, 1441 CK_C3_2, 1442 1443 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1444 /// Clang however has some logic to suport this. 1445 // FIXME: Warn, deprecate, and potentially remove this. 1446 CK_Yonah, 1447 //@} 1448 1449 /// \name Netburst 1450 /// Netburst microarchitecture based processors. 1451 //@{ 1452 CK_Pentium4, 1453 CK_Pentium4M, 1454 CK_Prescott, 1455 CK_Nocona, 1456 //@} 1457 1458 /// \name Core 1459 /// Core microarchitecture based processors. 1460 //@{ 1461 CK_Core2, 1462 1463 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1464 /// codename which GCC no longer accepts as an option to -march, but Clang 1465 /// has some logic for recognizing it. 1466 // FIXME: Warn, deprecate, and potentially remove this. 1467 CK_Penryn, 1468 //@} 1469 1470 /// \name Atom 1471 /// Atom processors 1472 //@{ 1473 CK_Atom, 1474 //@} 1475 1476 /// \name Nehalem 1477 /// Nehalem microarchitecture based processors. 1478 //@{ 1479 CK_Corei7, 1480 CK_Corei7AVX, 1481 CK_CoreAVXi, 1482 CK_CoreAVX2, 1483 //@} 1484 1485 /// \name K6 1486 /// K6 architecture processors. 1487 //@{ 1488 CK_K6, 1489 CK_K6_2, 1490 CK_K6_3, 1491 //@} 1492 1493 /// \name K7 1494 /// K7 architecture processors. 1495 //@{ 1496 CK_Athlon, 1497 CK_AthlonThunderbird, 1498 CK_Athlon4, 1499 CK_AthlonXP, 1500 CK_AthlonMP, 1501 //@} 1502 1503 /// \name K8 1504 /// K8 architecture processors. 1505 //@{ 1506 CK_Athlon64, 1507 CK_Athlon64SSE3, 1508 CK_AthlonFX, 1509 CK_K8, 1510 CK_K8SSE3, 1511 CK_Opteron, 1512 CK_OpteronSSE3, 1513 CK_AMDFAM10, 1514 //@} 1515 1516 /// \name Bobcat 1517 /// Bobcat architecture processors. 1518 //@{ 1519 CK_BTVER1, 1520 //@} 1521 1522 /// \name Bulldozer 1523 /// Bulldozer architecture processors. 1524 //@{ 1525 CK_BDVER1, 1526 CK_BDVER2, 1527 //@} 1528 1529 /// This specification is deprecated and will be removed in the future. 1530 /// Users should prefer \see CK_K8. 1531 // FIXME: Warn on this when the CPU is set to it. 1532 CK_x86_64, 1533 //@} 1534 1535 /// \name Geode 1536 /// Geode processors. 1537 //@{ 1538 CK_Geode 1539 //@} 1540 } CPU; 1541 1542 public: 1543 X86TargetInfo(const std::string& triple) 1544 : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1545 HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false), 1546 HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasSSE4a(false), 1547 HasFMA4(false), HasFMA(false), HasXOP(false), HasF16C(false), 1548 CPU(CK_Generic) { 1549 BigEndian = false; 1550 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1551 } 1552 virtual unsigned getFloatEvalMethod() const { 1553 // X87 evaluates with 80 bits "long double" precision. 1554 return SSELevel == NoSSE ? 2 : 0; 1555 } 1556 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1557 unsigned &NumRecords) const { 1558 Records = BuiltinInfo; 1559 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1560 } 1561 virtual void getGCCRegNames(const char * const *&Names, 1562 unsigned &NumNames) const { 1563 Names = GCCRegNames; 1564 NumNames = llvm::array_lengthof(GCCRegNames); 1565 } 1566 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1567 unsigned &NumAliases) const { 1568 Aliases = 0; 1569 NumAliases = 0; 1570 } 1571 virtual void getGCCAddlRegNames(const AddlRegName *&Names, 1572 unsigned &NumNames) const { 1573 Names = AddlRegNames; 1574 NumNames = llvm::array_lengthof(AddlRegNames); 1575 } 1576 virtual bool validateAsmConstraint(const char *&Name, 1577 TargetInfo::ConstraintInfo &info) const; 1578 virtual std::string convertConstraint(const char *&Constraint) const; 1579 virtual const char *getClobbers() const { 1580 return "~{dirflag},~{fpsr},~{flags}"; 1581 } 1582 virtual void getTargetDefines(const LangOptions &Opts, 1583 MacroBuilder &Builder) const; 1584 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 1585 StringRef Name, 1586 bool Enabled) const; 1587 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 1588 virtual bool hasFeature(StringRef Feature) const; 1589 virtual void HandleTargetFeatures(std::vector<std::string> &Features); 1590 virtual const char* getABI() const { 1591 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1592 return "avx"; 1593 else if (getTriple().getArch() == llvm::Triple::x86 && 1594 MMX3DNowLevel == NoMMX3DNow) 1595 return "no-mmx"; 1596 return ""; 1597 } 1598 virtual bool setCPU(const std::string &Name) { 1599 CPU = llvm::StringSwitch<CPUKind>(Name) 1600 .Case("i386", CK_i386) 1601 .Case("i486", CK_i486) 1602 .Case("winchip-c6", CK_WinChipC6) 1603 .Case("winchip2", CK_WinChip2) 1604 .Case("c3", CK_C3) 1605 .Case("i586", CK_i586) 1606 .Case("pentium", CK_Pentium) 1607 .Case("pentium-mmx", CK_PentiumMMX) 1608 .Case("i686", CK_i686) 1609 .Case("pentiumpro", CK_PentiumPro) 1610 .Case("pentium2", CK_Pentium2) 1611 .Case("pentium3", CK_Pentium3) 1612 .Case("pentium3m", CK_Pentium3M) 1613 .Case("pentium-m", CK_PentiumM) 1614 .Case("c3-2", CK_C3_2) 1615 .Case("yonah", CK_Yonah) 1616 .Case("pentium4", CK_Pentium4) 1617 .Case("pentium4m", CK_Pentium4M) 1618 .Case("prescott", CK_Prescott) 1619 .Case("nocona", CK_Nocona) 1620 .Case("core2", CK_Core2) 1621 .Case("penryn", CK_Penryn) 1622 .Case("atom", CK_Atom) 1623 .Case("corei7", CK_Corei7) 1624 .Case("corei7-avx", CK_Corei7AVX) 1625 .Case("core-avx-i", CK_CoreAVXi) 1626 .Case("core-avx2", CK_CoreAVX2) 1627 .Case("k6", CK_K6) 1628 .Case("k6-2", CK_K6_2) 1629 .Case("k6-3", CK_K6_3) 1630 .Case("athlon", CK_Athlon) 1631 .Case("athlon-tbird", CK_AthlonThunderbird) 1632 .Case("athlon-4", CK_Athlon4) 1633 .Case("athlon-xp", CK_AthlonXP) 1634 .Case("athlon-mp", CK_AthlonMP) 1635 .Case("athlon64", CK_Athlon64) 1636 .Case("athlon64-sse3", CK_Athlon64SSE3) 1637 .Case("athlon-fx", CK_AthlonFX) 1638 .Case("k8", CK_K8) 1639 .Case("k8-sse3", CK_K8SSE3) 1640 .Case("opteron", CK_Opteron) 1641 .Case("opteron-sse3", CK_OpteronSSE3) 1642 .Case("amdfam10", CK_AMDFAM10) 1643 .Case("btver1", CK_BTVER1) 1644 .Case("bdver1", CK_BDVER1) 1645 .Case("bdver2", CK_BDVER2) 1646 .Case("x86-64", CK_x86_64) 1647 .Case("geode", CK_Geode) 1648 .Default(CK_Generic); 1649 1650 // Perform any per-CPU checks necessary to determine if this CPU is 1651 // acceptable. 1652 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1653 // invalid without explaining *why*. 1654 switch (CPU) { 1655 case CK_Generic: 1656 // No processor selected! 1657 return false; 1658 1659 case CK_i386: 1660 case CK_i486: 1661 case CK_WinChipC6: 1662 case CK_WinChip2: 1663 case CK_C3: 1664 case CK_i586: 1665 case CK_Pentium: 1666 case CK_PentiumMMX: 1667 case CK_i686: 1668 case CK_PentiumPro: 1669 case CK_Pentium2: 1670 case CK_Pentium3: 1671 case CK_Pentium3M: 1672 case CK_PentiumM: 1673 case CK_Yonah: 1674 case CK_C3_2: 1675 case CK_Pentium4: 1676 case CK_Pentium4M: 1677 case CK_Prescott: 1678 case CK_K6: 1679 case CK_K6_2: 1680 case CK_K6_3: 1681 case CK_Athlon: 1682 case CK_AthlonThunderbird: 1683 case CK_Athlon4: 1684 case CK_AthlonXP: 1685 case CK_AthlonMP: 1686 case CK_Geode: 1687 // Only accept certain architectures when compiling in 32-bit mode. 1688 if (getTriple().getArch() != llvm::Triple::x86) 1689 return false; 1690 1691 // Fallthrough 1692 case CK_Nocona: 1693 case CK_Core2: 1694 case CK_Penryn: 1695 case CK_Atom: 1696 case CK_Corei7: 1697 case CK_Corei7AVX: 1698 case CK_CoreAVXi: 1699 case CK_CoreAVX2: 1700 case CK_Athlon64: 1701 case CK_Athlon64SSE3: 1702 case CK_AthlonFX: 1703 case CK_K8: 1704 case CK_K8SSE3: 1705 case CK_Opteron: 1706 case CK_OpteronSSE3: 1707 case CK_AMDFAM10: 1708 case CK_BTVER1: 1709 case CK_BDVER1: 1710 case CK_BDVER2: 1711 case CK_x86_64: 1712 return true; 1713 } 1714 llvm_unreachable("Unhandled CPU kind"); 1715 } 1716 1717 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 1718 // We accept all non-ARM calling conventions 1719 return (CC == CC_X86ThisCall || 1720 CC == CC_X86FastCall || 1721 CC == CC_X86StdCall || 1722 CC == CC_C || 1723 CC == CC_X86Pascal) ? CCCR_OK : CCCR_Warning; 1724 } 1725 1726 virtual CallingConv getDefaultCallingConv() const { 1727 return CC_C; 1728 } 1729 }; 1730 1731 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1732 // FIXME: This should not be here. 1733 Features["3dnow"] = false; 1734 Features["3dnowa"] = false; 1735 Features["mmx"] = false; 1736 Features["sse"] = false; 1737 Features["sse2"] = false; 1738 Features["sse3"] = false; 1739 Features["ssse3"] = false; 1740 Features["sse41"] = false; 1741 Features["sse42"] = false; 1742 Features["sse4a"] = false; 1743 Features["aes"] = false; 1744 Features["pclmul"] = false; 1745 Features["avx"] = false; 1746 Features["avx2"] = false; 1747 Features["lzcnt"] = false; 1748 Features["rdrand"] = false; 1749 Features["bmi"] = false; 1750 Features["bmi2"] = false; 1751 Features["popcnt"] = false; 1752 Features["fma4"] = false; 1753 Features["fma"] = false; 1754 Features["xop"] = false; 1755 Features["f16c"] = false; 1756 1757 // FIXME: This *really* should not be here. 1758 1759 // X86_64 always has SSE2. 1760 if (getTriple().getArch() == llvm::Triple::x86_64) 1761 Features["sse2"] = Features["sse"] = Features["mmx"] = true; 1762 1763 switch (CPU) { 1764 case CK_Generic: 1765 case CK_i386: 1766 case CK_i486: 1767 case CK_i586: 1768 case CK_Pentium: 1769 case CK_i686: 1770 case CK_PentiumPro: 1771 break; 1772 case CK_PentiumMMX: 1773 case CK_Pentium2: 1774 setFeatureEnabled(Features, "mmx", true); 1775 break; 1776 case CK_Pentium3: 1777 case CK_Pentium3M: 1778 setFeatureEnabled(Features, "mmx", true); 1779 setFeatureEnabled(Features, "sse", true); 1780 break; 1781 case CK_PentiumM: 1782 case CK_Pentium4: 1783 case CK_Pentium4M: 1784 case CK_x86_64: 1785 setFeatureEnabled(Features, "mmx", true); 1786 setFeatureEnabled(Features, "sse2", true); 1787 break; 1788 case CK_Yonah: 1789 case CK_Prescott: 1790 case CK_Nocona: 1791 setFeatureEnabled(Features, "mmx", true); 1792 setFeatureEnabled(Features, "sse3", true); 1793 break; 1794 case CK_Core2: 1795 setFeatureEnabled(Features, "mmx", true); 1796 setFeatureEnabled(Features, "ssse3", true); 1797 break; 1798 case CK_Penryn: 1799 setFeatureEnabled(Features, "mmx", true); 1800 setFeatureEnabled(Features, "sse4.1", true); 1801 break; 1802 case CK_Atom: 1803 setFeatureEnabled(Features, "mmx", true); 1804 setFeatureEnabled(Features, "ssse3", true); 1805 break; 1806 case CK_Corei7: 1807 setFeatureEnabled(Features, "mmx", true); 1808 setFeatureEnabled(Features, "sse4", true); 1809 break; 1810 case CK_Corei7AVX: 1811 setFeatureEnabled(Features, "mmx", true); 1812 setFeatureEnabled(Features, "avx", true); 1813 setFeatureEnabled(Features, "aes", true); 1814 setFeatureEnabled(Features, "pclmul", true); 1815 break; 1816 case CK_CoreAVXi: 1817 setFeatureEnabled(Features, "mmx", true); 1818 setFeatureEnabled(Features, "avx", true); 1819 setFeatureEnabled(Features, "aes", true); 1820 setFeatureEnabled(Features, "pclmul", true); 1821 setFeatureEnabled(Features, "rdrnd", true); 1822 break; 1823 case CK_CoreAVX2: 1824 setFeatureEnabled(Features, "mmx", true); 1825 setFeatureEnabled(Features, "avx2", true); 1826 setFeatureEnabled(Features, "aes", true); 1827 setFeatureEnabled(Features, "pclmul", true); 1828 setFeatureEnabled(Features, "lzcnt", true); 1829 setFeatureEnabled(Features, "rdrnd", true); 1830 setFeatureEnabled(Features, "bmi", true); 1831 setFeatureEnabled(Features, "bmi2", true); 1832 setFeatureEnabled(Features, "fma", true); 1833 break; 1834 case CK_K6: 1835 case CK_WinChipC6: 1836 setFeatureEnabled(Features, "mmx", true); 1837 break; 1838 case CK_K6_2: 1839 case CK_K6_3: 1840 case CK_WinChip2: 1841 case CK_C3: 1842 setFeatureEnabled(Features, "3dnow", true); 1843 break; 1844 case CK_Athlon: 1845 case CK_AthlonThunderbird: 1846 case CK_Geode: 1847 setFeatureEnabled(Features, "3dnowa", true); 1848 break; 1849 case CK_Athlon4: 1850 case CK_AthlonXP: 1851 case CK_AthlonMP: 1852 setFeatureEnabled(Features, "sse", true); 1853 setFeatureEnabled(Features, "3dnowa", true); 1854 break; 1855 case CK_K8: 1856 case CK_Opteron: 1857 case CK_Athlon64: 1858 case CK_AthlonFX: 1859 setFeatureEnabled(Features, "sse2", true); 1860 setFeatureEnabled(Features, "3dnowa", true); 1861 break; 1862 case CK_K8SSE3: 1863 case CK_OpteronSSE3: 1864 case CK_Athlon64SSE3: 1865 setFeatureEnabled(Features, "sse3", true); 1866 setFeatureEnabled(Features, "3dnowa", true); 1867 break; 1868 case CK_AMDFAM10: 1869 setFeatureEnabled(Features, "sse3", true); 1870 setFeatureEnabled(Features, "sse4a", true); 1871 setFeatureEnabled(Features, "3dnowa", true); 1872 break; 1873 case CK_BTVER1: 1874 setFeatureEnabled(Features, "ssse3", true); 1875 setFeatureEnabled(Features, "sse4a", true); 1876 break; 1877 case CK_BDVER1: 1878 case CK_BDVER2: 1879 setFeatureEnabled(Features, "avx", true); 1880 setFeatureEnabled(Features, "xop", true); 1881 setFeatureEnabled(Features, "aes", true); 1882 setFeatureEnabled(Features, "pclmul", true); 1883 break; 1884 case CK_C3_2: 1885 setFeatureEnabled(Features, "mmx", true); 1886 setFeatureEnabled(Features, "sse", true); 1887 break; 1888 } 1889 } 1890 1891 bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1892 StringRef Name, 1893 bool Enabled) const { 1894 // FIXME: This *really* should not be here. We need some way of translating 1895 // options into llvm subtarget features. 1896 if (!Features.count(Name) && 1897 (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" && 1898 Name != "rdrnd")) 1899 return false; 1900 1901 // FIXME: this should probably use a switch with fall through. 1902 1903 if (Enabled) { 1904 if (Name == "mmx") 1905 Features["mmx"] = true; 1906 else if (Name == "sse") 1907 Features["mmx"] = Features["sse"] = true; 1908 else if (Name == "sse2") 1909 Features["mmx"] = Features["sse"] = Features["sse2"] = true; 1910 else if (Name == "sse3") 1911 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1912 true; 1913 else if (Name == "ssse3") 1914 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1915 Features["ssse3"] = true; 1916 else if (Name == "sse4" || Name == "sse4.2") 1917 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1918 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1919 Features["popcnt"] = true; 1920 else if (Name == "sse4.1") 1921 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1922 Features["ssse3"] = Features["sse41"] = true; 1923 else if (Name == "3dnow") 1924 Features["mmx"] = Features["3dnow"] = true; 1925 else if (Name == "3dnowa") 1926 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true; 1927 else if (Name == "aes") 1928 Features["sse"] = Features["sse2"] = Features["aes"] = true; 1929 else if (Name == "pclmul") 1930 Features["sse"] = Features["sse2"] = Features["pclmul"] = true; 1931 else if (Name == "avx") 1932 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1933 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1934 Features["popcnt"] = Features["avx"] = true; 1935 else if (Name == "avx2") 1936 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1937 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1938 Features["popcnt"] = Features["avx"] = Features["avx2"] = true; 1939 else if (Name == "fma") 1940 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1941 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1942 Features["popcnt"] = Features["avx"] = Features["fma"] = true; 1943 else if (Name == "fma4") 1944 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1945 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1946 Features["popcnt"] = Features["avx"] = Features["sse4a"] = 1947 Features["fma4"] = true; 1948 else if (Name == "xop") 1949 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1950 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1951 Features["popcnt"] = Features["avx"] = Features["sse4a"] = 1952 Features["fma4"] = Features["xop"] = true; 1953 else if (Name == "sse4a") 1954 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1955 Features["sse4a"] = true; 1956 else if (Name == "lzcnt") 1957 Features["lzcnt"] = true; 1958 else if (Name == "rdrnd") 1959 Features["rdrand"] = true; 1960 else if (Name == "bmi") 1961 Features["bmi"] = true; 1962 else if (Name == "bmi2") 1963 Features["bmi2"] = true; 1964 else if (Name == "popcnt") 1965 Features["popcnt"] = true; 1966 else if (Name == "f16c") 1967 Features["f16c"] = true; 1968 } else { 1969 if (Name == "mmx") 1970 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false; 1971 else if (Name == "sse") 1972 Features["sse"] = Features["sse2"] = Features["sse3"] = 1973 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1974 Features["sse4a"] = Features["avx"] = Features["avx2"] = 1975 Features["fma"] = Features["fma4"] = Features["aes"] = 1976 Features["pclmul"] = Features["xop"] = false; 1977 else if (Name == "sse2") 1978 Features["sse2"] = Features["sse3"] = Features["ssse3"] = 1979 Features["sse41"] = Features["sse42"] = Features["sse4a"] = 1980 Features["avx"] = Features["avx2"] = Features["fma"] = 1981 Features["fma4"] = Features["aes"] = Features["pclmul"] = 1982 Features["xop"] = false; 1983 else if (Name == "sse3") 1984 Features["sse3"] = Features["ssse3"] = Features["sse41"] = 1985 Features["sse42"] = Features["sse4a"] = Features["avx"] = 1986 Features["avx2"] = Features["fma"] = Features["fma4"] = 1987 Features["xop"] = false; 1988 else if (Name == "ssse3") 1989 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1990 Features["avx"] = Features["avx2"] = Features["fma"] = false; 1991 else if (Name == "sse4" || Name == "sse4.1") 1992 Features["sse41"] = Features["sse42"] = Features["avx"] = 1993 Features["avx2"] = Features["fma"] = false; 1994 else if (Name == "sse4.2") 1995 Features["sse42"] = Features["avx"] = Features["avx2"] = 1996 Features["fma"] = false; 1997 else if (Name == "3dnow") 1998 Features["3dnow"] = Features["3dnowa"] = false; 1999 else if (Name == "3dnowa") 2000 Features["3dnowa"] = false; 2001 else if (Name == "aes") 2002 Features["aes"] = false; 2003 else if (Name == "pclmul") 2004 Features["pclmul"] = false; 2005 else if (Name == "avx") 2006 Features["avx"] = Features["avx2"] = Features["fma"] = 2007 Features["fma4"] = Features["xop"] = false; 2008 else if (Name == "avx2") 2009 Features["avx2"] = false; 2010 else if (Name == "fma") 2011 Features["fma"] = false; 2012 else if (Name == "sse4a") 2013 Features["sse4a"] = Features["fma4"] = Features["xop"] = false; 2014 else if (Name == "lzcnt") 2015 Features["lzcnt"] = false; 2016 else if (Name == "rdrnd") 2017 Features["rdrand"] = false; 2018 else if (Name == "bmi") 2019 Features["bmi"] = false; 2020 else if (Name == "bmi2") 2021 Features["bmi2"] = false; 2022 else if (Name == "popcnt") 2023 Features["popcnt"] = false; 2024 else if (Name == "fma4") 2025 Features["fma4"] = Features["xop"] = false; 2026 else if (Name == "xop") 2027 Features["xop"] = false; 2028 else if (Name == "f16c") 2029 Features["f16c"] = false; 2030 } 2031 2032 return true; 2033 } 2034 2035 /// HandleTargetOptions - Perform initialization based on the user 2036 /// configured set of features. 2037 void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) { 2038 // Remember the maximum enabled sselevel. 2039 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2040 // Ignore disabled features. 2041 if (Features[i][0] == '-') 2042 continue; 2043 2044 StringRef Feature = StringRef(Features[i]).substr(1); 2045 2046 if (Feature == "aes") { 2047 HasAES = true; 2048 continue; 2049 } 2050 2051 if (Feature == "pclmul") { 2052 HasPCLMUL = true; 2053 continue; 2054 } 2055 2056 if (Feature == "lzcnt") { 2057 HasLZCNT = true; 2058 continue; 2059 } 2060 2061 if (Feature == "rdrand") { 2062 HasRDRND = true; 2063 continue; 2064 } 2065 2066 if (Feature == "bmi") { 2067 HasBMI = true; 2068 continue; 2069 } 2070 2071 if (Feature == "bmi2") { 2072 HasBMI2 = true; 2073 continue; 2074 } 2075 2076 if (Feature == "popcnt") { 2077 HasPOPCNT = true; 2078 continue; 2079 } 2080 2081 if (Feature == "sse4a") { 2082 HasSSE4a = true; 2083 continue; 2084 } 2085 2086 if (Feature == "fma4") { 2087 HasFMA4 = true; 2088 continue; 2089 } 2090 2091 if (Feature == "fma") { 2092 HasFMA = true; 2093 continue; 2094 } 2095 2096 if (Feature == "xop") { 2097 HasXOP = true; 2098 continue; 2099 } 2100 2101 if (Feature == "f16c") { 2102 HasF16C = true; 2103 continue; 2104 } 2105 2106 assert(Features[i][0] == '+' && "Invalid target feature!"); 2107 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2108 .Case("avx2", AVX2) 2109 .Case("avx", AVX) 2110 .Case("sse42", SSE42) 2111 .Case("sse41", SSE41) 2112 .Case("ssse3", SSSE3) 2113 .Case("sse3", SSE3) 2114 .Case("sse2", SSE2) 2115 .Case("sse", SSE1) 2116 .Default(NoSSE); 2117 SSELevel = std::max(SSELevel, Level); 2118 2119 MMX3DNowEnum ThreeDNowLevel = 2120 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2121 .Case("3dnowa", AMD3DNowAthlon) 2122 .Case("3dnow", AMD3DNow) 2123 .Case("mmx", MMX) 2124 .Default(NoMMX3DNow); 2125 2126 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2127 } 2128 2129 // Don't tell the backend if we're turning off mmx; it will end up disabling 2130 // SSE, which we don't want. 2131 std::vector<std::string>::iterator it; 2132 it = std::find(Features.begin(), Features.end(), "-mmx"); 2133 if (it != Features.end()) 2134 Features.erase(it); 2135 } 2136 2137 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2138 /// definitions for this particular subtarget. 2139 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2140 MacroBuilder &Builder) const { 2141 // Target identification. 2142 if (getTriple().getArch() == llvm::Triple::x86_64) { 2143 Builder.defineMacro("__amd64__"); 2144 Builder.defineMacro("__amd64"); 2145 Builder.defineMacro("__x86_64"); 2146 Builder.defineMacro("__x86_64__"); 2147 } else { 2148 DefineStd(Builder, "i386", Opts); 2149 } 2150 2151 // Subtarget options. 2152 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2153 // truly should be based on -mtune options. 2154 switch (CPU) { 2155 case CK_Generic: 2156 break; 2157 case CK_i386: 2158 // The rest are coming from the i386 define above. 2159 Builder.defineMacro("__tune_i386__"); 2160 break; 2161 case CK_i486: 2162 case CK_WinChipC6: 2163 case CK_WinChip2: 2164 case CK_C3: 2165 defineCPUMacros(Builder, "i486"); 2166 break; 2167 case CK_PentiumMMX: 2168 Builder.defineMacro("__pentium_mmx__"); 2169 Builder.defineMacro("__tune_pentium_mmx__"); 2170 // Fallthrough 2171 case CK_i586: 2172 case CK_Pentium: 2173 defineCPUMacros(Builder, "i586"); 2174 defineCPUMacros(Builder, "pentium"); 2175 break; 2176 case CK_Pentium3: 2177 case CK_Pentium3M: 2178 case CK_PentiumM: 2179 Builder.defineMacro("__tune_pentium3__"); 2180 // Fallthrough 2181 case CK_Pentium2: 2182 case CK_C3_2: 2183 Builder.defineMacro("__tune_pentium2__"); 2184 // Fallthrough 2185 case CK_PentiumPro: 2186 Builder.defineMacro("__tune_i686__"); 2187 Builder.defineMacro("__tune_pentiumpro__"); 2188 // Fallthrough 2189 case CK_i686: 2190 Builder.defineMacro("__i686"); 2191 Builder.defineMacro("__i686__"); 2192 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2193 Builder.defineMacro("__pentiumpro"); 2194 Builder.defineMacro("__pentiumpro__"); 2195 break; 2196 case CK_Pentium4: 2197 case CK_Pentium4M: 2198 defineCPUMacros(Builder, "pentium4"); 2199 break; 2200 case CK_Yonah: 2201 case CK_Prescott: 2202 case CK_Nocona: 2203 defineCPUMacros(Builder, "nocona"); 2204 break; 2205 case CK_Core2: 2206 case CK_Penryn: 2207 defineCPUMacros(Builder, "core2"); 2208 break; 2209 case CK_Atom: 2210 defineCPUMacros(Builder, "atom"); 2211 break; 2212 case CK_Corei7: 2213 case CK_Corei7AVX: 2214 case CK_CoreAVXi: 2215 case CK_CoreAVX2: 2216 defineCPUMacros(Builder, "corei7"); 2217 break; 2218 case CK_K6_2: 2219 Builder.defineMacro("__k6_2__"); 2220 Builder.defineMacro("__tune_k6_2__"); 2221 // Fallthrough 2222 case CK_K6_3: 2223 if (CPU != CK_K6_2) { // In case of fallthrough 2224 // FIXME: GCC may be enabling these in cases where some other k6 2225 // architecture is specified but -m3dnow is explicitly provided. The 2226 // exact semantics need to be determined and emulated here. 2227 Builder.defineMacro("__k6_3__"); 2228 Builder.defineMacro("__tune_k6_3__"); 2229 } 2230 // Fallthrough 2231 case CK_K6: 2232 defineCPUMacros(Builder, "k6"); 2233 break; 2234 case CK_Athlon: 2235 case CK_AthlonThunderbird: 2236 case CK_Athlon4: 2237 case CK_AthlonXP: 2238 case CK_AthlonMP: 2239 defineCPUMacros(Builder, "athlon"); 2240 if (SSELevel != NoSSE) { 2241 Builder.defineMacro("__athlon_sse__"); 2242 Builder.defineMacro("__tune_athlon_sse__"); 2243 } 2244 break; 2245 case CK_K8: 2246 case CK_K8SSE3: 2247 case CK_x86_64: 2248 case CK_Opteron: 2249 case CK_OpteronSSE3: 2250 case CK_Athlon64: 2251 case CK_Athlon64SSE3: 2252 case CK_AthlonFX: 2253 defineCPUMacros(Builder, "k8"); 2254 break; 2255 case CK_AMDFAM10: 2256 defineCPUMacros(Builder, "amdfam10"); 2257 break; 2258 case CK_BTVER1: 2259 defineCPUMacros(Builder, "btver1"); 2260 break; 2261 case CK_BDVER1: 2262 defineCPUMacros(Builder, "bdver1"); 2263 break; 2264 case CK_BDVER2: 2265 defineCPUMacros(Builder, "bdver2"); 2266 break; 2267 case CK_Geode: 2268 defineCPUMacros(Builder, "geode"); 2269 break; 2270 } 2271 2272 // Target properties. 2273 Builder.defineMacro("__LITTLE_ENDIAN__"); 2274 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2275 2276 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2277 // functions in glibc header files that use FP Stack inline asm which the 2278 // backend can't deal with (PR879). 2279 Builder.defineMacro("__NO_MATH_INLINES"); 2280 2281 if (HasAES) 2282 Builder.defineMacro("__AES__"); 2283 2284 if (HasPCLMUL) 2285 Builder.defineMacro("__PCLMUL__"); 2286 2287 if (HasLZCNT) 2288 Builder.defineMacro("__LZCNT__"); 2289 2290 if (HasRDRND) 2291 Builder.defineMacro("__RDRND__"); 2292 2293 if (HasBMI) 2294 Builder.defineMacro("__BMI__"); 2295 2296 if (HasBMI2) 2297 Builder.defineMacro("__BMI2__"); 2298 2299 if (HasPOPCNT) 2300 Builder.defineMacro("__POPCNT__"); 2301 2302 if (HasSSE4a) 2303 Builder.defineMacro("__SSE4A__"); 2304 2305 if (HasFMA4) 2306 Builder.defineMacro("__FMA4__"); 2307 2308 if (HasFMA) 2309 Builder.defineMacro("__FMA__"); 2310 2311 if (HasXOP) 2312 Builder.defineMacro("__XOP__"); 2313 2314 if (HasF16C) 2315 Builder.defineMacro("__F16C__"); 2316 2317 // Each case falls through to the previous one here. 2318 switch (SSELevel) { 2319 case AVX2: 2320 Builder.defineMacro("__AVX2__"); 2321 case AVX: 2322 Builder.defineMacro("__AVX__"); 2323 case SSE42: 2324 Builder.defineMacro("__SSE4_2__"); 2325 case SSE41: 2326 Builder.defineMacro("__SSE4_1__"); 2327 case SSSE3: 2328 Builder.defineMacro("__SSSE3__"); 2329 case SSE3: 2330 Builder.defineMacro("__SSE3__"); 2331 case SSE2: 2332 Builder.defineMacro("__SSE2__"); 2333 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2334 case SSE1: 2335 Builder.defineMacro("__SSE__"); 2336 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2337 case NoSSE: 2338 break; 2339 } 2340 2341 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2342 switch (SSELevel) { 2343 case AVX2: 2344 case AVX: 2345 case SSE42: 2346 case SSE41: 2347 case SSSE3: 2348 case SSE3: 2349 case SSE2: 2350 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2351 break; 2352 case SSE1: 2353 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2354 break; 2355 default: 2356 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2357 } 2358 } 2359 2360 // Each case falls through to the previous one here. 2361 switch (MMX3DNowLevel) { 2362 case AMD3DNowAthlon: 2363 Builder.defineMacro("__3dNOW_A__"); 2364 case AMD3DNow: 2365 Builder.defineMacro("__3dNOW__"); 2366 case MMX: 2367 Builder.defineMacro("__MMX__"); 2368 case NoMMX3DNow: 2369 break; 2370 } 2371 } 2372 2373 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2374 return llvm::StringSwitch<bool>(Feature) 2375 .Case("aes", HasAES) 2376 .Case("avx", SSELevel >= AVX) 2377 .Case("avx2", SSELevel >= AVX2) 2378 .Case("bmi", HasBMI) 2379 .Case("bmi2", HasBMI2) 2380 .Case("fma", HasFMA) 2381 .Case("fma4", HasFMA4) 2382 .Case("lzcnt", HasLZCNT) 2383 .Case("rdrnd", HasRDRND) 2384 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2385 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2386 .Case("mmx", MMX3DNowLevel >= MMX) 2387 .Case("pclmul", HasPCLMUL) 2388 .Case("popcnt", HasPOPCNT) 2389 .Case("sse", SSELevel >= SSE1) 2390 .Case("sse2", SSELevel >= SSE2) 2391 .Case("sse3", SSELevel >= SSE3) 2392 .Case("ssse3", SSELevel >= SSSE3) 2393 .Case("sse41", SSELevel >= SSE41) 2394 .Case("sse42", SSELevel >= SSE42) 2395 .Case("sse4a", HasSSE4a) 2396 .Case("x86", true) 2397 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2398 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2399 .Case("xop", HasXOP) 2400 .Case("f16c", HasF16C) 2401 .Default(false); 2402 } 2403 2404 bool 2405 X86TargetInfo::validateAsmConstraint(const char *&Name, 2406 TargetInfo::ConstraintInfo &Info) const { 2407 switch (*Name) { 2408 default: return false; 2409 case 'Y': // first letter of a pair: 2410 switch (*(Name+1)) { 2411 default: return false; 2412 case '0': // First SSE register. 2413 case 't': // Any SSE register, when SSE2 is enabled. 2414 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2415 case 'm': // any MMX register, when inter-unit moves enabled. 2416 break; // falls through to setAllowsRegister. 2417 } 2418 case 'a': // eax. 2419 case 'b': // ebx. 2420 case 'c': // ecx. 2421 case 'd': // edx. 2422 case 'S': // esi. 2423 case 'D': // edi. 2424 case 'A': // edx:eax. 2425 case 'f': // any x87 floating point stack register. 2426 case 't': // top of floating point stack. 2427 case 'u': // second from top of floating point stack. 2428 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2429 case 'y': // Any MMX register. 2430 case 'x': // Any SSE register. 2431 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2432 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2433 case 'l': // "Index" registers: any general register that can be used as an 2434 // index in a base+index memory access. 2435 Info.setAllowsRegister(); 2436 return true; 2437 case 'C': // SSE floating point constant. 2438 case 'G': // x87 floating point constant. 2439 case 'e': // 32-bit signed integer constant for use with zero-extending 2440 // x86_64 instructions. 2441 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2442 // x86_64 instructions. 2443 return true; 2444 } 2445 } 2446 2447 2448 std::string 2449 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2450 switch (*Constraint) { 2451 case 'a': return std::string("{ax}"); 2452 case 'b': return std::string("{bx}"); 2453 case 'c': return std::string("{cx}"); 2454 case 'd': return std::string("{dx}"); 2455 case 'S': return std::string("{si}"); 2456 case 'D': return std::string("{di}"); 2457 case 'p': // address 2458 return std::string("im"); 2459 case 't': // top of floating point stack. 2460 return std::string("{st}"); 2461 case 'u': // second from top of floating point stack. 2462 return std::string("{st(1)}"); // second from top of floating point stack. 2463 default: 2464 return std::string(1, *Constraint); 2465 } 2466 } 2467 } // end anonymous namespace 2468 2469 namespace { 2470 // X86-32 generic target 2471 class X86_32TargetInfo : public X86TargetInfo { 2472 public: 2473 X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) { 2474 DoubleAlign = LongLongAlign = 32; 2475 LongDoubleWidth = 96; 2476 LongDoubleAlign = 32; 2477 SuitableAlign = 128; 2478 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2479 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2480 "a0:0:64-f80:32:32-n8:16:32-S128"; 2481 SizeType = UnsignedInt; 2482 PtrDiffType = SignedInt; 2483 IntPtrType = SignedInt; 2484 RegParmMax = 3; 2485 2486 // Use fpret for all types. 2487 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2488 (1 << TargetInfo::Double) | 2489 (1 << TargetInfo::LongDouble)); 2490 2491 // x86-32 has atomics up to 8 bytes 2492 // FIXME: Check that we actually have cmpxchg8b before setting 2493 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2494 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2495 } 2496 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2497 return TargetInfo::CharPtrBuiltinVaList; 2498 } 2499 2500 int getEHDataRegisterNumber(unsigned RegNo) const { 2501 if (RegNo == 0) return 0; 2502 if (RegNo == 1) return 2; 2503 return -1; 2504 } 2505 }; 2506 } // end anonymous namespace 2507 2508 namespace { 2509 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2510 public: 2511 NetBSDI386TargetInfo(const std::string &triple) : 2512 NetBSDTargetInfo<X86_32TargetInfo>(triple) { 2513 } 2514 2515 virtual unsigned getFloatEvalMethod() const { 2516 // NetBSD defaults to "double" rounding 2517 return 1; 2518 } 2519 }; 2520 } // end anonymous namespace 2521 2522 namespace { 2523 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 2524 public: 2525 OpenBSDI386TargetInfo(const std::string& triple) : 2526 OpenBSDTargetInfo<X86_32TargetInfo>(triple) { 2527 SizeType = UnsignedLong; 2528 IntPtrType = SignedLong; 2529 PtrDiffType = SignedLong; 2530 } 2531 }; 2532 } // end anonymous namespace 2533 2534 namespace { 2535 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 2536 public: 2537 BitrigI386TargetInfo(const std::string& triple) : 2538 BitrigTargetInfo<X86_32TargetInfo>(triple) { 2539 SizeType = UnsignedLong; 2540 IntPtrType = SignedLong; 2541 PtrDiffType = SignedLong; 2542 } 2543 }; 2544 } // end anonymous namespace 2545 2546 namespace { 2547 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 2548 public: 2549 DarwinI386TargetInfo(const std::string& triple) : 2550 DarwinTargetInfo<X86_32TargetInfo>(triple) { 2551 LongDoubleWidth = 128; 2552 LongDoubleAlign = 128; 2553 SuitableAlign = 128; 2554 MaxVectorAlign = 256; 2555 SizeType = UnsignedLong; 2556 IntPtrType = SignedLong; 2557 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2558 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2559 "a0:0:64-f80:128:128-n8:16:32-S128"; 2560 HasAlignMac68kSupport = true; 2561 } 2562 2563 }; 2564 } // end anonymous namespace 2565 2566 namespace { 2567 // x86-32 Windows target 2568 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 2569 public: 2570 WindowsX86_32TargetInfo(const std::string& triple) 2571 : WindowsTargetInfo<X86_32TargetInfo>(triple) { 2572 TLSSupported = false; 2573 WCharType = UnsignedShort; 2574 DoubleAlign = LongLongAlign = 64; 2575 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2576 "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-" 2577 "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"; 2578 } 2579 virtual void getTargetDefines(const LangOptions &Opts, 2580 MacroBuilder &Builder) const { 2581 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 2582 } 2583 }; 2584 } // end anonymous namespace 2585 2586 namespace { 2587 2588 // x86-32 Windows Visual Studio target 2589 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 2590 public: 2591 VisualStudioWindowsX86_32TargetInfo(const std::string& triple) 2592 : WindowsX86_32TargetInfo(triple) { 2593 LongDoubleWidth = LongDoubleAlign = 64; 2594 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 2595 } 2596 virtual void getTargetDefines(const LangOptions &Opts, 2597 MacroBuilder &Builder) const { 2598 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 2599 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 2600 // The value of the following reflects processor type. 2601 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 2602 // We lost the original triple, so we use the default. 2603 Builder.defineMacro("_M_IX86", "600"); 2604 } 2605 }; 2606 } // end anonymous namespace 2607 2608 namespace { 2609 // x86-32 MinGW target 2610 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 2611 public: 2612 MinGWX86_32TargetInfo(const std::string& triple) 2613 : WindowsX86_32TargetInfo(triple) { 2614 } 2615 virtual void getTargetDefines(const LangOptions &Opts, 2616 MacroBuilder &Builder) const { 2617 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 2618 DefineStd(Builder, "WIN32", Opts); 2619 DefineStd(Builder, "WINNT", Opts); 2620 Builder.defineMacro("_X86_"); 2621 Builder.defineMacro("__MSVCRT__"); 2622 Builder.defineMacro("__MINGW32__"); 2623 2624 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 2625 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 2626 if (Opts.MicrosoftExt) 2627 // Provide "as-is" __declspec. 2628 Builder.defineMacro("__declspec", "__declspec"); 2629 else 2630 // Provide alias of __attribute__ like mingw32-gcc. 2631 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 2632 } 2633 }; 2634 } // end anonymous namespace 2635 2636 namespace { 2637 // x86-32 Cygwin target 2638 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 2639 public: 2640 CygwinX86_32TargetInfo(const std::string& triple) 2641 : X86_32TargetInfo(triple) { 2642 TLSSupported = false; 2643 WCharType = UnsignedShort; 2644 DoubleAlign = LongLongAlign = 64; 2645 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2646 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 2647 "a0:0:64-f80:32:32-n8:16:32-S32"; 2648 } 2649 virtual void getTargetDefines(const LangOptions &Opts, 2650 MacroBuilder &Builder) const { 2651 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2652 Builder.defineMacro("__CYGWIN__"); 2653 Builder.defineMacro("__CYGWIN32__"); 2654 DefineStd(Builder, "unix", Opts); 2655 if (Opts.CPlusPlus) 2656 Builder.defineMacro("_GNU_SOURCE"); 2657 } 2658 }; 2659 } // end anonymous namespace 2660 2661 namespace { 2662 // x86-32 Haiku target 2663 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 2664 public: 2665 HaikuX86_32TargetInfo(const std::string& triple) 2666 : X86_32TargetInfo(triple) { 2667 SizeType = UnsignedLong; 2668 IntPtrType = SignedLong; 2669 PtrDiffType = SignedLong; 2670 this->UserLabelPrefix = ""; 2671 } 2672 virtual void getTargetDefines(const LangOptions &Opts, 2673 MacroBuilder &Builder) const { 2674 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2675 Builder.defineMacro("__INTEL__"); 2676 Builder.defineMacro("__HAIKU__"); 2677 } 2678 }; 2679 } // end anonymous namespace 2680 2681 // RTEMS Target 2682 template<typename Target> 2683 class RTEMSTargetInfo : public OSTargetInfo<Target> { 2684 protected: 2685 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 2686 MacroBuilder &Builder) const { 2687 // RTEMS defines; list based off of gcc output 2688 2689 Builder.defineMacro("__rtems__"); 2690 Builder.defineMacro("__ELF__"); 2691 } 2692 public: 2693 RTEMSTargetInfo(const std::string &triple) 2694 : OSTargetInfo<Target>(triple) { 2695 this->UserLabelPrefix = ""; 2696 2697 llvm::Triple Triple(triple); 2698 switch (Triple.getArch()) { 2699 default: 2700 case llvm::Triple::x86: 2701 // this->MCountName = ".mcount"; 2702 break; 2703 case llvm::Triple::mips: 2704 case llvm::Triple::mipsel: 2705 case llvm::Triple::ppc: 2706 case llvm::Triple::ppc64: 2707 // this->MCountName = "_mcount"; 2708 break; 2709 case llvm::Triple::arm: 2710 // this->MCountName = "__mcount"; 2711 break; 2712 } 2713 2714 } 2715 }; 2716 2717 namespace { 2718 // x86-32 RTEMS target 2719 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 2720 public: 2721 RTEMSX86_32TargetInfo(const std::string& triple) 2722 : X86_32TargetInfo(triple) { 2723 SizeType = UnsignedLong; 2724 IntPtrType = SignedLong; 2725 PtrDiffType = SignedLong; 2726 this->UserLabelPrefix = ""; 2727 } 2728 virtual void getTargetDefines(const LangOptions &Opts, 2729 MacroBuilder &Builder) const { 2730 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2731 Builder.defineMacro("__INTEL__"); 2732 Builder.defineMacro("__rtems__"); 2733 } 2734 }; 2735 } // end anonymous namespace 2736 2737 namespace { 2738 // x86-64 generic target 2739 class X86_64TargetInfo : public X86TargetInfo { 2740 public: 2741 X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) { 2742 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 2743 LongDoubleWidth = 128; 2744 LongDoubleAlign = 128; 2745 LargeArrayMinWidth = 128; 2746 LargeArrayAlign = 128; 2747 SuitableAlign = 128; 2748 IntMaxType = SignedLong; 2749 UIntMaxType = UnsignedLong; 2750 Int64Type = SignedLong; 2751 RegParmMax = 6; 2752 2753 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2754 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 2755 "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"; 2756 2757 // Use fpret only for long double. 2758 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 2759 2760 // Use fp2ret for _Complex long double. 2761 ComplexLongDoubleUsesFP2Ret = true; 2762 2763 // x86-64 has atomics up to 16 bytes. 2764 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 2765 // on CPUs with cmpxchg16b 2766 MaxAtomicPromoteWidth = 128; 2767 MaxAtomicInlineWidth = 64; 2768 } 2769 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2770 return TargetInfo::X86_64ABIBuiltinVaList; 2771 } 2772 2773 int getEHDataRegisterNumber(unsigned RegNo) const { 2774 if (RegNo == 0) return 0; 2775 if (RegNo == 1) return 1; 2776 return -1; 2777 } 2778 2779 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 2780 return TargetInfo::checkCallingConvention(CC); 2781 } 2782 2783 virtual CallingConv getDefaultCallingConv() const { 2784 return CC_Default; 2785 } 2786 2787 }; 2788 } // end anonymous namespace 2789 2790 namespace { 2791 // x86-64 Windows target 2792 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 2793 public: 2794 WindowsX86_64TargetInfo(const std::string& triple) 2795 : WindowsTargetInfo<X86_64TargetInfo>(triple) { 2796 TLSSupported = false; 2797 WCharType = UnsignedShort; 2798 LongWidth = LongAlign = 32; 2799 DoubleAlign = LongLongAlign = 64; 2800 IntMaxType = SignedLongLong; 2801 UIntMaxType = UnsignedLongLong; 2802 Int64Type = SignedLongLong; 2803 SizeType = UnsignedLongLong; 2804 PtrDiffType = SignedLongLong; 2805 IntPtrType = SignedLongLong; 2806 this->UserLabelPrefix = ""; 2807 } 2808 virtual void getTargetDefines(const LangOptions &Opts, 2809 MacroBuilder &Builder) const { 2810 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 2811 Builder.defineMacro("_WIN64"); 2812 } 2813 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2814 return TargetInfo::CharPtrBuiltinVaList; 2815 } 2816 }; 2817 } // end anonymous namespace 2818 2819 namespace { 2820 // x86-64 Windows Visual Studio target 2821 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 2822 public: 2823 VisualStudioWindowsX86_64TargetInfo(const std::string& triple) 2824 : WindowsX86_64TargetInfo(triple) { 2825 LongDoubleWidth = LongDoubleAlign = 64; 2826 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 2827 } 2828 virtual void getTargetDefines(const LangOptions &Opts, 2829 MacroBuilder &Builder) const { 2830 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 2831 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 2832 Builder.defineMacro("_M_X64"); 2833 Builder.defineMacro("_M_AMD64"); 2834 } 2835 }; 2836 } // end anonymous namespace 2837 2838 namespace { 2839 // x86-64 MinGW target 2840 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 2841 public: 2842 MinGWX86_64TargetInfo(const std::string& triple) 2843 : WindowsX86_64TargetInfo(triple) { 2844 } 2845 virtual void getTargetDefines(const LangOptions &Opts, 2846 MacroBuilder &Builder) const { 2847 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 2848 DefineStd(Builder, "WIN64", Opts); 2849 Builder.defineMacro("__MSVCRT__"); 2850 Builder.defineMacro("__MINGW32__"); 2851 Builder.defineMacro("__MINGW64__"); 2852 2853 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 2854 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 2855 if (Opts.MicrosoftExt) 2856 // Provide "as-is" __declspec. 2857 Builder.defineMacro("__declspec", "__declspec"); 2858 else 2859 // Provide alias of __attribute__ like mingw32-gcc. 2860 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 2861 } 2862 }; 2863 } // end anonymous namespace 2864 2865 namespace { 2866 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 2867 public: 2868 DarwinX86_64TargetInfo(const std::string& triple) 2869 : DarwinTargetInfo<X86_64TargetInfo>(triple) { 2870 Int64Type = SignedLongLong; 2871 MaxVectorAlign = 256; 2872 } 2873 }; 2874 } // end anonymous namespace 2875 2876 namespace { 2877 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 2878 public: 2879 OpenBSDX86_64TargetInfo(const std::string& triple) 2880 : OpenBSDTargetInfo<X86_64TargetInfo>(triple) { 2881 IntMaxType = SignedLongLong; 2882 UIntMaxType = UnsignedLongLong; 2883 Int64Type = SignedLongLong; 2884 } 2885 }; 2886 } // end anonymous namespace 2887 2888 namespace { 2889 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 2890 public: 2891 BitrigX86_64TargetInfo(const std::string& triple) 2892 : BitrigTargetInfo<X86_64TargetInfo>(triple) { 2893 IntMaxType = SignedLongLong; 2894 UIntMaxType = UnsignedLongLong; 2895 Int64Type = SignedLongLong; 2896 } 2897 }; 2898 } // end anonymous namespace 2899 2900 namespace { 2901 class ARMTargetInfo : public TargetInfo { 2902 // Possible FPU choices. 2903 enum FPUMode { 2904 VFP2FPU = (1 << 0), 2905 VFP3FPU = (1 << 1), 2906 VFP4FPU = (1 << 2), 2907 NeonFPU = (1 << 3) 2908 }; 2909 2910 static bool FPUModeIsVFP(FPUMode Mode) { 2911 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU); 2912 } 2913 2914 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 2915 static const char * const GCCRegNames[]; 2916 2917 std::string ABI, CPU; 2918 2919 unsigned FPU : 4; 2920 2921 unsigned IsAAPCS : 1; 2922 unsigned IsThumb : 1; 2923 2924 // Initialized via features. 2925 unsigned SoftFloat : 1; 2926 unsigned SoftFloatABI : 1; 2927 2928 static const Builtin::Info BuiltinInfo[]; 2929 2930 public: 2931 ARMTargetInfo(const std::string &TripleStr) 2932 : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s"), IsAAPCS(true) 2933 { 2934 BigEndian = false; 2935 SizeType = UnsignedInt; 2936 PtrDiffType = SignedInt; 2937 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 2938 WCharType = UnsignedInt; 2939 2940 // {} in inline assembly are neon specifiers, not assembly variant 2941 // specifiers. 2942 NoAsmVariants = true; 2943 2944 // FIXME: Should we just treat this as a feature? 2945 IsThumb = getTriple().getArchName().startswith("thumb"); 2946 if (IsThumb) { 2947 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 2948 // so set preferred for small types to 32. 2949 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 2950 "i64:64:64-f32:32:32-f64:64:64-" 2951 "v64:64:64-v128:64:128-a0:0:32-n32-S64"); 2952 } else { 2953 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2954 "i64:64:64-f32:32:32-f64:64:64-" 2955 "v64:64:64-v128:64:128-a0:0:64-n32-S64"); 2956 } 2957 2958 // ARM targets default to using the ARM C++ ABI. 2959 CXXABI = CXXABI_ARM; 2960 2961 // ARM has atomics up to 8 bytes 2962 // FIXME: Set MaxAtomicInlineWidth if we have the feature v6e 2963 MaxAtomicPromoteWidth = 64; 2964 2965 // Do force alignment of members that follow zero length bitfields. If 2966 // the alignment of the zero-length bitfield is greater than the member 2967 // that follows it, `bar', `bar' will be aligned as the type of the 2968 // zero length bitfield. 2969 UseZeroLengthBitfieldAlignment = true; 2970 } 2971 virtual const char *getABI() const { return ABI.c_str(); } 2972 virtual bool setABI(const std::string &Name) { 2973 ABI = Name; 2974 2975 // The defaults (above) are for AAPCS, check if we need to change them. 2976 // 2977 // FIXME: We need support for -meabi... we could just mangle it into the 2978 // name. 2979 if (Name == "apcs-gnu") { 2980 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 2981 SizeType = UnsignedLong; 2982 2983 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 2984 WCharType = SignedInt; 2985 2986 // Do not respect the alignment of bit-field types when laying out 2987 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 2988 UseBitFieldTypeAlignment = false; 2989 2990 /// gcc forces the alignment to 4 bytes, regardless of the type of the 2991 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 2992 /// gcc. 2993 ZeroLengthBitfieldBoundary = 32; 2994 2995 IsAAPCS = false; 2996 2997 if (IsThumb) { 2998 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 2999 // so set preferred for small types to 32. 3000 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3001 "i64:32:64-f32:32:32-f64:32:64-" 3002 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3003 } else { 3004 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3005 "i64:32:64-f32:32:32-f64:32:64-" 3006 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3007 } 3008 3009 // FIXME: Override "preferred align" for double and long long. 3010 } else if (Name == "aapcs") { 3011 IsAAPCS = true; 3012 // FIXME: Enumerated types are variable width in straight AAPCS. 3013 } else if (Name == "aapcs-linux") { 3014 IsAAPCS = true; 3015 } else 3016 return false; 3017 3018 return true; 3019 } 3020 3021 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3022 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3023 Features["vfp2"] = true; 3024 else if (CPU == "cortex-a8" || CPU == "cortex-a15" || 3025 CPU == "cortex-a9" || CPU == "cortex-a9-mp") 3026 Features["neon"] = true; 3027 else if (CPU == "swift") { 3028 Features["vfp4"] = true; 3029 Features["neon"] = true; 3030 } 3031 } 3032 3033 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 3034 StringRef Name, 3035 bool Enabled) const { 3036 if (Name == "soft-float" || Name == "soft-float-abi" || 3037 Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" || 3038 Name == "d16" || Name == "neonfp") { 3039 Features[Name] = Enabled; 3040 } else 3041 return false; 3042 3043 return true; 3044 } 3045 3046 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 3047 FPU = 0; 3048 SoftFloat = SoftFloatABI = false; 3049 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3050 if (Features[i] == "+soft-float") 3051 SoftFloat = true; 3052 else if (Features[i] == "+soft-float-abi") 3053 SoftFloatABI = true; 3054 else if (Features[i] == "+vfp2") 3055 FPU |= VFP2FPU; 3056 else if (Features[i] == "+vfp3") 3057 FPU |= VFP3FPU; 3058 else if (Features[i] == "+vfp4") 3059 FPU |= VFP4FPU; 3060 else if (Features[i] == "+neon") 3061 FPU |= NeonFPU; 3062 } 3063 3064 // Remove front-end specific options which the backend handles differently. 3065 std::vector<std::string>::iterator it; 3066 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3067 if (it != Features.end()) 3068 Features.erase(it); 3069 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3070 if (it != Features.end()) 3071 Features.erase(it); 3072 } 3073 3074 virtual bool hasFeature(StringRef Feature) const { 3075 return llvm::StringSwitch<bool>(Feature) 3076 .Case("arm", true) 3077 .Case("softfloat", SoftFloat) 3078 .Case("thumb", IsThumb) 3079 .Case("neon", FPU == NeonFPU && !SoftFloat && 3080 StringRef(getCPUDefineSuffix(CPU)).startswith("7")) 3081 .Default(false); 3082 } 3083 // FIXME: Should we actually have some table instead of these switches? 3084 static const char *getCPUDefineSuffix(StringRef Name) { 3085 return llvm::StringSwitch<const char*>(Name) 3086 .Cases("arm8", "arm810", "4") 3087 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3088 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3089 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3090 .Case("ep9312", "4T") 3091 .Cases("arm10tdmi", "arm1020t", "5T") 3092 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3093 .Case("arm926ej-s", "5TEJ") 3094 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3095 .Cases("xscale", "iwmmxt", "5TE") 3096 .Case("arm1136j-s", "6J") 3097 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3098 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3099 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3100 .Cases("cortex-a8", "cortex-a9", "cortex-a15", "7A") 3101 .Case("cortex-a9-mp", "7F") 3102 .Case("swift", "7S") 3103 .Cases("cortex-m3", "cortex-m4", "7M") 3104 .Case("cortex-m0", "6M") 3105 .Default(0); 3106 } 3107 static const char *getCPUProfile(StringRef Name) { 3108 return llvm::StringSwitch<const char*>(Name) 3109 .Cases("cortex-a8", "cortex-a9", "A") 3110 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 3111 .Default(""); 3112 } 3113 virtual bool setCPU(const std::string &Name) { 3114 if (!getCPUDefineSuffix(Name)) 3115 return false; 3116 3117 CPU = Name; 3118 return true; 3119 } 3120 virtual void getTargetDefines(const LangOptions &Opts, 3121 MacroBuilder &Builder) const { 3122 // Target identification. 3123 Builder.defineMacro("__arm"); 3124 Builder.defineMacro("__arm__"); 3125 3126 // Target properties. 3127 Builder.defineMacro("__ARMEL__"); 3128 Builder.defineMacro("__LITTLE_ENDIAN__"); 3129 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3130 3131 StringRef CPUArch = getCPUDefineSuffix(CPU); 3132 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 3133 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 3134 StringRef CPUProfile = getCPUProfile(CPU); 3135 if (!CPUProfile.empty()) 3136 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 3137 3138 // Subtarget options. 3139 3140 // FIXME: It's more complicated than this and we don't really support 3141 // interworking. 3142 if ('5' <= CPUArch[0] && CPUArch[0] <= '7') 3143 Builder.defineMacro("__THUMB_INTERWORK__"); 3144 3145 if (ABI == "aapcs" || ABI == "aapcs-linux") { 3146 Builder.defineMacro("__ARM_EABI__"); 3147 Builder.defineMacro("__ARM_PCS", "1"); 3148 3149 if (!SoftFloat && !SoftFloatABI) 3150 Builder.defineMacro("__ARM_PCS_VFP", "1"); 3151 } 3152 3153 if (SoftFloat) 3154 Builder.defineMacro("__SOFTFP__"); 3155 3156 if (CPU == "xscale") 3157 Builder.defineMacro("__XSCALE__"); 3158 3159 bool IsARMv7 = CPUArch.startswith("7"); 3160 if (IsThumb) { 3161 Builder.defineMacro("__THUMBEL__"); 3162 Builder.defineMacro("__thumb__"); 3163 if (CPUArch == "6T2" || IsARMv7) 3164 Builder.defineMacro("__thumb2__"); 3165 } 3166 3167 // Note, this is always on in gcc, even though it doesn't make sense. 3168 Builder.defineMacro("__APCS_32__"); 3169 3170 if (FPUModeIsVFP((FPUMode) FPU)) { 3171 Builder.defineMacro("__VFP_FP__"); 3172 if (FPU & VFP2FPU) 3173 Builder.defineMacro("__ARM_VFPV2__"); 3174 if (FPU & VFP3FPU) 3175 Builder.defineMacro("__ARM_VFPV3__"); 3176 if (FPU & VFP4FPU) 3177 Builder.defineMacro("__ARM_VFPV4__"); 3178 } 3179 3180 // This only gets set when Neon instructions are actually available, unlike 3181 // the VFP define, hence the soft float and arch check. This is subtly 3182 // different from gcc, we follow the intent which was that it should be set 3183 // when Neon instructions are actually available. 3184 if ((FPU & NeonFPU) && !SoftFloat && IsARMv7) 3185 Builder.defineMacro("__ARM_NEON__"); 3186 } 3187 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3188 unsigned &NumRecords) const { 3189 Records = BuiltinInfo; 3190 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 3191 } 3192 virtual bool isCLZForZeroUndef() const { return false; } 3193 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3194 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 3195 } 3196 virtual void getGCCRegNames(const char * const *&Names, 3197 unsigned &NumNames) const; 3198 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3199 unsigned &NumAliases) const; 3200 virtual bool validateAsmConstraint(const char *&Name, 3201 TargetInfo::ConstraintInfo &Info) const { 3202 switch (*Name) { 3203 default: break; 3204 case 'l': // r0-r7 3205 case 'h': // r8-r15 3206 case 'w': // VFP Floating point register single precision 3207 case 'P': // VFP Floating point register double precision 3208 Info.setAllowsRegister(); 3209 return true; 3210 case 'Q': // A memory address that is a single base register. 3211 Info.setAllowsMemory(); 3212 return true; 3213 case 'U': // a memory reference... 3214 switch (Name[1]) { 3215 case 'q': // ...ARMV4 ldrsb 3216 case 'v': // ...VFP load/store (reg+constant offset) 3217 case 'y': // ...iWMMXt load/store 3218 case 't': // address valid for load/store opaque types wider 3219 // than 128-bits 3220 case 'n': // valid address for Neon doubleword vector load/store 3221 case 'm': // valid address for Neon element and structure load/store 3222 case 's': // valid address for non-offset loads/stores of quad-word 3223 // values in four ARM registers 3224 Info.setAllowsMemory(); 3225 Name++; 3226 return true; 3227 } 3228 } 3229 return false; 3230 } 3231 virtual std::string convertConstraint(const char *&Constraint) const { 3232 std::string R; 3233 switch (*Constraint) { 3234 case 'U': // Two-character constraint; add "^" hint for later parsing. 3235 R = std::string("^") + std::string(Constraint, 2); 3236 Constraint++; 3237 break; 3238 case 'p': // 'p' should be translated to 'r' by default. 3239 R = std::string("r"); 3240 break; 3241 default: 3242 return std::string(1, *Constraint); 3243 } 3244 return R; 3245 } 3246 virtual const char *getClobbers() const { 3247 // FIXME: Is this really right? 3248 return ""; 3249 } 3250 3251 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3252 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 3253 } 3254 }; 3255 3256 const char * const ARMTargetInfo::GCCRegNames[] = { 3257 // Integer registers 3258 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3259 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 3260 3261 // Float registers 3262 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3263 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3264 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3265 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3266 3267 // Double registers 3268 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3269 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3270 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3271 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3272 3273 // Quad registers 3274 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3275 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 3276 }; 3277 3278 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 3279 unsigned &NumNames) const { 3280 Names = GCCRegNames; 3281 NumNames = llvm::array_lengthof(GCCRegNames); 3282 } 3283 3284 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 3285 { { "a1" }, "r0" }, 3286 { { "a2" }, "r1" }, 3287 { { "a3" }, "r2" }, 3288 { { "a4" }, "r3" }, 3289 { { "v1" }, "r4" }, 3290 { { "v2" }, "r5" }, 3291 { { "v3" }, "r6" }, 3292 { { "v4" }, "r7" }, 3293 { { "v5" }, "r8" }, 3294 { { "v6", "rfp" }, "r9" }, 3295 { { "sl" }, "r10" }, 3296 { { "fp" }, "r11" }, 3297 { { "ip" }, "r12" }, 3298 { { "r13" }, "sp" }, 3299 { { "r14" }, "lr" }, 3300 { { "r15" }, "pc" }, 3301 // The S, D and Q registers overlap, but aren't really aliases; we 3302 // don't want to substitute one of these for a different-sized one. 3303 }; 3304 3305 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3306 unsigned &NumAliases) const { 3307 Aliases = GCCRegAliases; 3308 NumAliases = llvm::array_lengthof(GCCRegAliases); 3309 } 3310 3311 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 3312 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3313 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3314 ALL_LANGUAGES }, 3315 #include "clang/Basic/BuiltinsARM.def" 3316 }; 3317 } // end anonymous namespace. 3318 3319 namespace { 3320 class DarwinARMTargetInfo : 3321 public DarwinTargetInfo<ARMTargetInfo> { 3322 protected: 3323 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3324 MacroBuilder &Builder) const { 3325 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 3326 } 3327 3328 public: 3329 DarwinARMTargetInfo(const std::string& triple) 3330 : DarwinTargetInfo<ARMTargetInfo>(triple) { 3331 HasAlignMac68kSupport = true; 3332 // iOS always has 64-bit atomic instructions. 3333 // FIXME: This should be based off of the target features in ARMTargetInfo. 3334 MaxAtomicInlineWidth = 64; 3335 } 3336 }; 3337 } // end anonymous namespace. 3338 3339 3340 namespace { 3341 // Hexagon abstract base class 3342 class HexagonTargetInfo : public TargetInfo { 3343 static const Builtin::Info BuiltinInfo[]; 3344 static const char * const GCCRegNames[]; 3345 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3346 std::string CPU; 3347 public: 3348 HexagonTargetInfo(const std::string& triple) : TargetInfo(triple) { 3349 BigEndian = false; 3350 DescriptionString = ("e-p:32:32:32-" 3351 "i64:64:64-i32:32:32-i16:16:16-i1:32:32" 3352 "f64:64:64-f32:32:32-a0:0-n32"); 3353 3354 // {} in inline assembly are packet specifiers, not assembly variant 3355 // specifiers. 3356 NoAsmVariants = true; 3357 } 3358 3359 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3360 unsigned &NumRecords) const { 3361 Records = BuiltinInfo; 3362 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 3363 } 3364 3365 virtual bool validateAsmConstraint(const char *&Name, 3366 TargetInfo::ConstraintInfo &Info) const { 3367 return true; 3368 } 3369 3370 virtual void getTargetDefines(const LangOptions &Opts, 3371 MacroBuilder &Builder) const; 3372 3373 virtual bool hasFeature(StringRef Feature) const { 3374 return Feature == "hexagon"; 3375 } 3376 3377 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3378 return TargetInfo::CharPtrBuiltinVaList; 3379 } 3380 virtual void getGCCRegNames(const char * const *&Names, 3381 unsigned &NumNames) const; 3382 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3383 unsigned &NumAliases) const; 3384 virtual const char *getClobbers() const { 3385 return ""; 3386 } 3387 3388 static const char *getHexagonCPUSuffix(StringRef Name) { 3389 return llvm::StringSwitch<const char*>(Name) 3390 .Case("hexagonv2", "2") 3391 .Case("hexagonv3", "3") 3392 .Case("hexagonv4", "4") 3393 .Case("hexagonv5", "5") 3394 .Default(0); 3395 } 3396 3397 virtual bool setCPU(const std::string &Name) { 3398 if (!getHexagonCPUSuffix(Name)) 3399 return false; 3400 3401 CPU = Name; 3402 return true; 3403 } 3404 }; 3405 3406 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 3407 MacroBuilder &Builder) const { 3408 Builder.defineMacro("qdsp6"); 3409 Builder.defineMacro("__qdsp6", "1"); 3410 Builder.defineMacro("__qdsp6__", "1"); 3411 3412 Builder.defineMacro("hexagon"); 3413 Builder.defineMacro("__hexagon", "1"); 3414 Builder.defineMacro("__hexagon__", "1"); 3415 3416 if(CPU == "hexagonv1") { 3417 Builder.defineMacro("__HEXAGON_V1__"); 3418 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 3419 if(Opts.HexagonQdsp6Compat) { 3420 Builder.defineMacro("__QDSP6_V1__"); 3421 Builder.defineMacro("__QDSP6_ARCH__", "1"); 3422 } 3423 } 3424 else if(CPU == "hexagonv2") { 3425 Builder.defineMacro("__HEXAGON_V2__"); 3426 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 3427 if(Opts.HexagonQdsp6Compat) { 3428 Builder.defineMacro("__QDSP6_V2__"); 3429 Builder.defineMacro("__QDSP6_ARCH__", "2"); 3430 } 3431 } 3432 else if(CPU == "hexagonv3") { 3433 Builder.defineMacro("__HEXAGON_V3__"); 3434 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 3435 if(Opts.HexagonQdsp6Compat) { 3436 Builder.defineMacro("__QDSP6_V3__"); 3437 Builder.defineMacro("__QDSP6_ARCH__", "3"); 3438 } 3439 } 3440 else if(CPU == "hexagonv4") { 3441 Builder.defineMacro("__HEXAGON_V4__"); 3442 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 3443 if(Opts.HexagonQdsp6Compat) { 3444 Builder.defineMacro("__QDSP6_V4__"); 3445 Builder.defineMacro("__QDSP6_ARCH__", "4"); 3446 } 3447 } 3448 else if(CPU == "hexagonv5") { 3449 Builder.defineMacro("__HEXAGON_V5__"); 3450 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 3451 if(Opts.HexagonQdsp6Compat) { 3452 Builder.defineMacro("__QDSP6_V5__"); 3453 Builder.defineMacro("__QDSP6_ARCH__", "5"); 3454 } 3455 } 3456 } 3457 3458 const char * const HexagonTargetInfo::GCCRegNames[] = { 3459 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3460 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 3461 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 3462 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 3463 "p0", "p1", "p2", "p3", 3464 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 3465 }; 3466 3467 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 3468 unsigned &NumNames) const { 3469 Names = GCCRegNames; 3470 NumNames = llvm::array_lengthof(GCCRegNames); 3471 } 3472 3473 3474 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 3475 { { "sp" }, "r29" }, 3476 { { "fp" }, "r30" }, 3477 { { "lr" }, "r31" }, 3478 }; 3479 3480 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3481 unsigned &NumAliases) const { 3482 Aliases = GCCRegAliases; 3483 NumAliases = llvm::array_lengthof(GCCRegAliases); 3484 } 3485 3486 3487 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 3488 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3489 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3490 ALL_LANGUAGES }, 3491 #include "clang/Basic/BuiltinsHexagon.def" 3492 }; 3493 } 3494 3495 3496 namespace { 3497 class SparcV8TargetInfo : public TargetInfo { 3498 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3499 static const char * const GCCRegNames[]; 3500 bool SoftFloat; 3501 public: 3502 SparcV8TargetInfo(const std::string& triple) : TargetInfo(triple) { 3503 // FIXME: Support Sparc quad-precision long double? 3504 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3505 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"; 3506 } 3507 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 3508 StringRef Name, 3509 bool Enabled) const { 3510 if (Name == "soft-float") 3511 Features[Name] = Enabled; 3512 else 3513 return false; 3514 3515 return true; 3516 } 3517 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 3518 SoftFloat = false; 3519 for (unsigned i = 0, e = Features.size(); i != e; ++i) 3520 if (Features[i] == "+soft-float") 3521 SoftFloat = true; 3522 } 3523 virtual void getTargetDefines(const LangOptions &Opts, 3524 MacroBuilder &Builder) const { 3525 DefineStd(Builder, "sparc", Opts); 3526 Builder.defineMacro("__sparcv8"); 3527 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3528 3529 if (SoftFloat) 3530 Builder.defineMacro("SOFT_FLOAT", "1"); 3531 } 3532 3533 virtual bool hasFeature(StringRef Feature) const { 3534 return llvm::StringSwitch<bool>(Feature) 3535 .Case("softfloat", SoftFloat) 3536 .Case("sparc", true) 3537 .Default(false); 3538 } 3539 3540 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3541 unsigned &NumRecords) const { 3542 // FIXME: Implement! 3543 } 3544 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3545 return TargetInfo::VoidPtrBuiltinVaList; 3546 } 3547 virtual void getGCCRegNames(const char * const *&Names, 3548 unsigned &NumNames) const; 3549 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3550 unsigned &NumAliases) const; 3551 virtual bool validateAsmConstraint(const char *&Name, 3552 TargetInfo::ConstraintInfo &info) const { 3553 // FIXME: Implement! 3554 return false; 3555 } 3556 virtual const char *getClobbers() const { 3557 // FIXME: Implement! 3558 return ""; 3559 } 3560 }; 3561 3562 const char * const SparcV8TargetInfo::GCCRegNames[] = { 3563 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3564 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 3565 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 3566 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 3567 }; 3568 3569 void SparcV8TargetInfo::getGCCRegNames(const char * const *&Names, 3570 unsigned &NumNames) const { 3571 Names = GCCRegNames; 3572 NumNames = llvm::array_lengthof(GCCRegNames); 3573 } 3574 3575 const TargetInfo::GCCRegAlias SparcV8TargetInfo::GCCRegAliases[] = { 3576 { { "g0" }, "r0" }, 3577 { { "g1" }, "r1" }, 3578 { { "g2" }, "r2" }, 3579 { { "g3" }, "r3" }, 3580 { { "g4" }, "r4" }, 3581 { { "g5" }, "r5" }, 3582 { { "g6" }, "r6" }, 3583 { { "g7" }, "r7" }, 3584 { { "o0" }, "r8" }, 3585 { { "o1" }, "r9" }, 3586 { { "o2" }, "r10" }, 3587 { { "o3" }, "r11" }, 3588 { { "o4" }, "r12" }, 3589 { { "o5" }, "r13" }, 3590 { { "o6", "sp" }, "r14" }, 3591 { { "o7" }, "r15" }, 3592 { { "l0" }, "r16" }, 3593 { { "l1" }, "r17" }, 3594 { { "l2" }, "r18" }, 3595 { { "l3" }, "r19" }, 3596 { { "l4" }, "r20" }, 3597 { { "l5" }, "r21" }, 3598 { { "l6" }, "r22" }, 3599 { { "l7" }, "r23" }, 3600 { { "i0" }, "r24" }, 3601 { { "i1" }, "r25" }, 3602 { { "i2" }, "r26" }, 3603 { { "i3" }, "r27" }, 3604 { { "i4" }, "r28" }, 3605 { { "i5" }, "r29" }, 3606 { { "i6", "fp" }, "r30" }, 3607 { { "i7" }, "r31" }, 3608 }; 3609 3610 void SparcV8TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3611 unsigned &NumAliases) const { 3612 Aliases = GCCRegAliases; 3613 NumAliases = llvm::array_lengthof(GCCRegAliases); 3614 } 3615 } // end anonymous namespace. 3616 3617 namespace { 3618 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 3619 public: 3620 AuroraUXSparcV8TargetInfo(const std::string& triple) : 3621 AuroraUXTargetInfo<SparcV8TargetInfo>(triple) { 3622 SizeType = UnsignedInt; 3623 PtrDiffType = SignedInt; 3624 } 3625 }; 3626 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 3627 public: 3628 SolarisSparcV8TargetInfo(const std::string& triple) : 3629 SolarisTargetInfo<SparcV8TargetInfo>(triple) { 3630 SizeType = UnsignedInt; 3631 PtrDiffType = SignedInt; 3632 } 3633 }; 3634 } // end anonymous namespace. 3635 3636 namespace { 3637 class MSP430TargetInfo : public TargetInfo { 3638 static const char * const GCCRegNames[]; 3639 public: 3640 MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) { 3641 BigEndian = false; 3642 TLSSupported = false; 3643 IntWidth = 16; IntAlign = 16; 3644 LongWidth = 32; LongLongWidth = 64; 3645 LongAlign = LongLongAlign = 16; 3646 PointerWidth = 16; PointerAlign = 16; 3647 SuitableAlign = 16; 3648 SizeType = UnsignedInt; 3649 IntMaxType = SignedLong; 3650 UIntMaxType = UnsignedLong; 3651 IntPtrType = SignedShort; 3652 PtrDiffType = SignedInt; 3653 SigAtomicType = SignedLong; 3654 DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"; 3655 } 3656 virtual void getTargetDefines(const LangOptions &Opts, 3657 MacroBuilder &Builder) const { 3658 Builder.defineMacro("MSP430"); 3659 Builder.defineMacro("__MSP430__"); 3660 // FIXME: defines for different 'flavours' of MCU 3661 } 3662 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3663 unsigned &NumRecords) const { 3664 // FIXME: Implement. 3665 Records = 0; 3666 NumRecords = 0; 3667 } 3668 virtual bool hasFeature(StringRef Feature) const { 3669 return Feature == "msp430"; 3670 } 3671 virtual void getGCCRegNames(const char * const *&Names, 3672 unsigned &NumNames) const; 3673 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3674 unsigned &NumAliases) const { 3675 // No aliases. 3676 Aliases = 0; 3677 NumAliases = 0; 3678 } 3679 virtual bool validateAsmConstraint(const char *&Name, 3680 TargetInfo::ConstraintInfo &info) const { 3681 // No target constraints for now. 3682 return false; 3683 } 3684 virtual const char *getClobbers() const { 3685 // FIXME: Is this really right? 3686 return ""; 3687 } 3688 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3689 // FIXME: implement 3690 return TargetInfo::CharPtrBuiltinVaList; 3691 } 3692 }; 3693 3694 const char * const MSP430TargetInfo::GCCRegNames[] = { 3695 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3696 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 3697 }; 3698 3699 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 3700 unsigned &NumNames) const { 3701 Names = GCCRegNames; 3702 NumNames = llvm::array_lengthof(GCCRegNames); 3703 } 3704 } 3705 3706 namespace { 3707 3708 // LLVM and Clang cannot be used directly to output native binaries for 3709 // target, but is used to compile C code to llvm bitcode with correct 3710 // type and alignment information. 3711 // 3712 // TCE uses the llvm bitcode as input and uses it for generating customized 3713 // target processor and program binary. TCE co-design environment is 3714 // publicly available in http://tce.cs.tut.fi 3715 3716 static const unsigned TCEOpenCLAddrSpaceMap[] = { 3717 3, // opencl_global 3718 4, // opencl_local 3719 5, // opencl_constant 3720 0, // cuda_device 3721 0, // cuda_constant 3722 0 // cuda_shared 3723 }; 3724 3725 class TCETargetInfo : public TargetInfo{ 3726 public: 3727 TCETargetInfo(const std::string& triple) : TargetInfo(triple) { 3728 TLSSupported = false; 3729 IntWidth = 32; 3730 LongWidth = LongLongWidth = 32; 3731 PointerWidth = 32; 3732 IntAlign = 32; 3733 LongAlign = LongLongAlign = 32; 3734 PointerAlign = 32; 3735 SuitableAlign = 32; 3736 SizeType = UnsignedInt; 3737 IntMaxType = SignedLong; 3738 UIntMaxType = UnsignedLong; 3739 IntPtrType = SignedInt; 3740 PtrDiffType = SignedInt; 3741 FloatWidth = 32; 3742 FloatAlign = 32; 3743 DoubleWidth = 32; 3744 DoubleAlign = 32; 3745 LongDoubleWidth = 32; 3746 LongDoubleAlign = 32; 3747 FloatFormat = &llvm::APFloat::IEEEsingle; 3748 DoubleFormat = &llvm::APFloat::IEEEsingle; 3749 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 3750 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-" 3751 "i16:16:32-i32:32:32-i64:32:32-" 3752 "f32:32:32-f64:32:32-v64:32:32-" 3753 "v128:32:32-a0:0:32-n32"; 3754 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 3755 } 3756 3757 virtual void getTargetDefines(const LangOptions &Opts, 3758 MacroBuilder &Builder) const { 3759 DefineStd(Builder, "tce", Opts); 3760 Builder.defineMacro("__TCE__"); 3761 Builder.defineMacro("__TCE_V1__"); 3762 } 3763 virtual bool hasFeature(StringRef Feature) const { 3764 return Feature == "tce"; 3765 } 3766 3767 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3768 unsigned &NumRecords) const {} 3769 virtual const char *getClobbers() const { 3770 return ""; 3771 } 3772 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3773 return TargetInfo::VoidPtrBuiltinVaList; 3774 } 3775 virtual void getGCCRegNames(const char * const *&Names, 3776 unsigned &NumNames) const {} 3777 virtual bool validateAsmConstraint(const char *&Name, 3778 TargetInfo::ConstraintInfo &info) const { 3779 return true; 3780 } 3781 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3782 unsigned &NumAliases) const {} 3783 }; 3784 } 3785 3786 namespace { 3787 class MipsTargetInfoBase : public TargetInfo { 3788 static const Builtin::Info BuiltinInfo[]; 3789 std::string CPU; 3790 bool IsMips16; 3791 enum MipsFloatABI { 3792 HardFloat, SingleFloat, SoftFloat 3793 } FloatABI; 3794 enum DspRevEnum { 3795 NoDSP, DSP1, DSP2 3796 } DspRev; 3797 3798 protected: 3799 std::string ABI; 3800 3801 public: 3802 MipsTargetInfoBase(const std::string& triple, 3803 const std::string& ABIStr, 3804 const std::string& CPUStr) 3805 : TargetInfo(triple), 3806 CPU(CPUStr), 3807 IsMips16(false), 3808 FloatABI(HardFloat), 3809 DspRev(NoDSP), 3810 ABI(ABIStr) 3811 {} 3812 3813 virtual const char *getABI() const { return ABI.c_str(); } 3814 virtual bool setABI(const std::string &Name) = 0; 3815 virtual bool setCPU(const std::string &Name) { 3816 CPU = Name; 3817 return true; 3818 } 3819 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3820 Features[ABI] = true; 3821 Features[CPU] = true; 3822 } 3823 3824 virtual void getTargetDefines(const LangOptions &Opts, 3825 MacroBuilder &Builder) const { 3826 DefineStd(Builder, "mips", Opts); 3827 Builder.defineMacro("_mips"); 3828 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3829 3830 switch (FloatABI) { 3831 case HardFloat: 3832 Builder.defineMacro("__mips_hard_float", Twine(1)); 3833 break; 3834 case SingleFloat: 3835 Builder.defineMacro("__mips_hard_float", Twine(1)); 3836 Builder.defineMacro("__mips_single_float", Twine(1)); 3837 break; 3838 case SoftFloat: 3839 Builder.defineMacro("__mips_soft_float", Twine(1)); 3840 break; 3841 } 3842 3843 if (IsMips16) 3844 Builder.defineMacro("__mips16", Twine(1)); 3845 3846 switch (DspRev) { 3847 default: 3848 break; 3849 case DSP1: 3850 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 3851 Builder.defineMacro("__mips_dsp", Twine(1)); 3852 break; 3853 case DSP2: 3854 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 3855 Builder.defineMacro("__mips_dspr2", Twine(1)); 3856 Builder.defineMacro("__mips_dsp", Twine(1)); 3857 break; 3858 } 3859 3860 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 3861 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 3862 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 3863 3864 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 3865 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 3866 } 3867 3868 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3869 unsigned &NumRecords) const { 3870 Records = BuiltinInfo; 3871 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 3872 } 3873 virtual bool hasFeature(StringRef Feature) const { 3874 return Feature == "mips"; 3875 } 3876 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3877 return TargetInfo::VoidPtrBuiltinVaList; 3878 } 3879 virtual void getGCCRegNames(const char * const *&Names, 3880 unsigned &NumNames) const { 3881 static const char * const GCCRegNames[] = { 3882 // CPU register names 3883 // Must match second column of GCCRegAliases 3884 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 3885 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 3886 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 3887 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 3888 // Floating point register names 3889 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 3890 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 3891 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 3892 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 3893 // Hi/lo and condition register names 3894 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 3895 "$fcc5","$fcc6","$fcc7" 3896 }; 3897 Names = GCCRegNames; 3898 NumNames = llvm::array_lengthof(GCCRegNames); 3899 } 3900 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3901 unsigned &NumAliases) const = 0; 3902 virtual bool validateAsmConstraint(const char *&Name, 3903 TargetInfo::ConstraintInfo &Info) const { 3904 switch (*Name) { 3905 default: 3906 return false; 3907 3908 case 'r': // CPU registers. 3909 case 'd': // Equivalent to "r" unless generating MIPS16 code. 3910 case 'y': // Equivalent to "r", backwards compatibility only. 3911 case 'f': // floating-point registers. 3912 case 'c': // $25 for indirect jumps 3913 case 'l': // lo register 3914 case 'x': // hilo register pair 3915 Info.setAllowsRegister(); 3916 return true; 3917 } 3918 } 3919 3920 virtual const char *getClobbers() const { 3921 // FIXME: Implement! 3922 return ""; 3923 } 3924 3925 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 3926 StringRef Name, 3927 bool Enabled) const { 3928 if (Name == "soft-float" || Name == "single-float" || 3929 Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" || 3930 Name == "mips32" || Name == "mips32r2" || 3931 Name == "mips64" || Name == "mips64r2" || 3932 Name == "mips16" || Name == "dsp" || Name == "dspr2") { 3933 Features[Name] = Enabled; 3934 return true; 3935 } 3936 return false; 3937 } 3938 3939 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 3940 IsMips16 = false; 3941 FloatABI = HardFloat; 3942 DspRev = NoDSP; 3943 3944 for (std::vector<std::string>::iterator it = Features.begin(), 3945 ie = Features.end(); it != ie; ++it) { 3946 if (*it == "+single-float") 3947 FloatABI = SingleFloat; 3948 else if (*it == "+soft-float") 3949 FloatABI = SoftFloat; 3950 else if (*it == "+mips16") 3951 IsMips16 = true; 3952 else if (*it == "+dsp") 3953 DspRev = std::max(DspRev, DSP1); 3954 else if (*it == "+dspr2") 3955 DspRev = std::max(DspRev, DSP2); 3956 } 3957 3958 // Remove front-end specific option. 3959 std::vector<std::string>::iterator it = 3960 std::find(Features.begin(), Features.end(), "+soft-float"); 3961 if (it != Features.end()) 3962 Features.erase(it); 3963 } 3964 }; 3965 3966 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 3967 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3968 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3969 ALL_LANGUAGES }, 3970 #include "clang/Basic/BuiltinsMips.def" 3971 }; 3972 3973 class Mips32TargetInfoBase : public MipsTargetInfoBase { 3974 public: 3975 Mips32TargetInfoBase(const std::string& triple) : 3976 MipsTargetInfoBase(triple, "o32", "mips32") { 3977 SizeType = UnsignedInt; 3978 PtrDiffType = SignedInt; 3979 } 3980 virtual bool setABI(const std::string &Name) { 3981 if ((Name == "o32") || (Name == "eabi")) { 3982 ABI = Name; 3983 return true; 3984 } else 3985 return false; 3986 } 3987 virtual void getTargetDefines(const LangOptions &Opts, 3988 MacroBuilder &Builder) const { 3989 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 3990 3991 if (ABI == "o32") { 3992 Builder.defineMacro("__mips_o32"); 3993 Builder.defineMacro("_ABIO32", "1"); 3994 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 3995 } 3996 else if (ABI == "eabi") 3997 Builder.defineMacro("__mips_eabi"); 3998 else 3999 llvm_unreachable("Invalid ABI for Mips32."); 4000 } 4001 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4002 unsigned &NumAliases) const { 4003 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 4004 { { "at" }, "$1" }, 4005 { { "v0" }, "$2" }, 4006 { { "v1" }, "$3" }, 4007 { { "a0" }, "$4" }, 4008 { { "a1" }, "$5" }, 4009 { { "a2" }, "$6" }, 4010 { { "a3" }, "$7" }, 4011 { { "t0" }, "$8" }, 4012 { { "t1" }, "$9" }, 4013 { { "t2" }, "$10" }, 4014 { { "t3" }, "$11" }, 4015 { { "t4" }, "$12" }, 4016 { { "t5" }, "$13" }, 4017 { { "t6" }, "$14" }, 4018 { { "t7" }, "$15" }, 4019 { { "s0" }, "$16" }, 4020 { { "s1" }, "$17" }, 4021 { { "s2" }, "$18" }, 4022 { { "s3" }, "$19" }, 4023 { { "s4" }, "$20" }, 4024 { { "s5" }, "$21" }, 4025 { { "s6" }, "$22" }, 4026 { { "s7" }, "$23" }, 4027 { { "t8" }, "$24" }, 4028 { { "t9" }, "$25" }, 4029 { { "k0" }, "$26" }, 4030 { { "k1" }, "$27" }, 4031 { { "gp" }, "$28" }, 4032 { { "sp","$sp" }, "$29" }, 4033 { { "fp","$fp" }, "$30" }, 4034 { { "ra" }, "$31" } 4035 }; 4036 Aliases = GCCRegAliases; 4037 NumAliases = llvm::array_lengthof(GCCRegAliases); 4038 } 4039 }; 4040 4041 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 4042 public: 4043 Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) { 4044 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4045 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"; 4046 } 4047 virtual void getTargetDefines(const LangOptions &Opts, 4048 MacroBuilder &Builder) const { 4049 DefineStd(Builder, "MIPSEB", Opts); 4050 Builder.defineMacro("_MIPSEB"); 4051 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 4052 } 4053 }; 4054 4055 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 4056 public: 4057 Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) { 4058 BigEndian = false; 4059 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4060 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"; 4061 } 4062 virtual void getTargetDefines(const LangOptions &Opts, 4063 MacroBuilder &Builder) const { 4064 DefineStd(Builder, "MIPSEL", Opts); 4065 Builder.defineMacro("_MIPSEL"); 4066 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 4067 } 4068 }; 4069 4070 class Mips64TargetInfoBase : public MipsTargetInfoBase { 4071 virtual void SetDescriptionString(const std::string &Name) = 0; 4072 public: 4073 Mips64TargetInfoBase(const std::string& triple) : 4074 MipsTargetInfoBase(triple, "n64", "mips64") { 4075 LongWidth = LongAlign = 64; 4076 PointerWidth = PointerAlign = 64; 4077 LongDoubleWidth = LongDoubleAlign = 128; 4078 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4079 SuitableAlign = 128; 4080 } 4081 virtual bool setABI(const std::string &Name) { 4082 SetDescriptionString(Name); 4083 4084 if (Name != "n32" && Name != "n64") 4085 return false; 4086 4087 ABI = Name; 4088 4089 if (Name == "n32") { 4090 LongWidth = LongAlign = 32; 4091 PointerWidth = PointerAlign = 32; 4092 } 4093 4094 return true; 4095 } 4096 virtual void getTargetDefines(const LangOptions &Opts, 4097 MacroBuilder &Builder) const { 4098 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 4099 4100 Builder.defineMacro("__mips64"); 4101 Builder.defineMacro("__mips64__"); 4102 4103 if (ABI == "n32") { 4104 Builder.defineMacro("__mips_n32"); 4105 Builder.defineMacro("_ABIN32", "2"); 4106 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 4107 } 4108 else if (ABI == "n64") { 4109 Builder.defineMacro("__mips_n64"); 4110 Builder.defineMacro("_ABI64", "3"); 4111 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 4112 } 4113 else 4114 llvm_unreachable("Invalid ABI for Mips64."); 4115 } 4116 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4117 unsigned &NumAliases) const { 4118 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 4119 { { "at" }, "$1" }, 4120 { { "v0" }, "$2" }, 4121 { { "v1" }, "$3" }, 4122 { { "a0" }, "$4" }, 4123 { { "a1" }, "$5" }, 4124 { { "a2" }, "$6" }, 4125 { { "a3" }, "$7" }, 4126 { { "a4" }, "$8" }, 4127 { { "a5" }, "$9" }, 4128 { { "a6" }, "$10" }, 4129 { { "a7" }, "$11" }, 4130 { { "t0" }, "$12" }, 4131 { { "t1" }, "$13" }, 4132 { { "t2" }, "$14" }, 4133 { { "t3" }, "$15" }, 4134 { { "s0" }, "$16" }, 4135 { { "s1" }, "$17" }, 4136 { { "s2" }, "$18" }, 4137 { { "s3" }, "$19" }, 4138 { { "s4" }, "$20" }, 4139 { { "s5" }, "$21" }, 4140 { { "s6" }, "$22" }, 4141 { { "s7" }, "$23" }, 4142 { { "t8" }, "$24" }, 4143 { { "t9" }, "$25" }, 4144 { { "k0" }, "$26" }, 4145 { { "k1" }, "$27" }, 4146 { { "gp" }, "$28" }, 4147 { { "sp","$sp" }, "$29" }, 4148 { { "fp","$fp" }, "$30" }, 4149 { { "ra" }, "$31" } 4150 }; 4151 Aliases = GCCRegAliases; 4152 NumAliases = llvm::array_lengthof(GCCRegAliases); 4153 } 4154 }; 4155 4156 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 4157 virtual void SetDescriptionString(const std::string &Name) { 4158 // Change DescriptionString only if ABI is n32. 4159 if (Name == "n32") 4160 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4161 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 4162 "v64:64:64-n32"; 4163 } 4164 public: 4165 Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) { 4166 // Default ABI is n64. 4167 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4168 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 4169 "v64:64:64-n32"; 4170 } 4171 virtual void getTargetDefines(const LangOptions &Opts, 4172 MacroBuilder &Builder) const { 4173 DefineStd(Builder, "MIPSEB", Opts); 4174 Builder.defineMacro("_MIPSEB"); 4175 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 4176 } 4177 }; 4178 4179 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 4180 virtual void SetDescriptionString(const std::string &Name) { 4181 // Change DescriptionString only if ABI is n32. 4182 if (Name == "n32") 4183 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4184 "i64:64:64-f32:32:32-f64:64:64-f128:128:128" 4185 "-v64:64:64-n32"; 4186 } 4187 public: 4188 Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) { 4189 // Default ABI is n64. 4190 BigEndian = false; 4191 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4192 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 4193 "v64:64:64-n32"; 4194 } 4195 virtual void getTargetDefines(const LangOptions &Opts, 4196 MacroBuilder &Builder) const { 4197 DefineStd(Builder, "MIPSEL", Opts); 4198 Builder.defineMacro("_MIPSEL"); 4199 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 4200 } 4201 }; 4202 } // end anonymous namespace. 4203 4204 namespace { 4205 class PNaClTargetInfo : public TargetInfo { 4206 public: 4207 PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) { 4208 BigEndian = false; 4209 this->UserLabelPrefix = ""; 4210 this->LongAlign = 32; 4211 this->LongWidth = 32; 4212 this->PointerAlign = 32; 4213 this->PointerWidth = 32; 4214 this->IntMaxType = TargetInfo::SignedLongLong; 4215 this->UIntMaxType = TargetInfo::UnsignedLongLong; 4216 this->Int64Type = TargetInfo::SignedLongLong; 4217 this->DoubleAlign = 64; 4218 this->LongDoubleWidth = 64; 4219 this->LongDoubleAlign = 64; 4220 this->SizeType = TargetInfo::UnsignedInt; 4221 this->PtrDiffType = TargetInfo::SignedInt; 4222 this->IntPtrType = TargetInfo::SignedInt; 4223 this->RegParmMax = 2; 4224 DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 4225 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 4226 } 4227 4228 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 4229 } 4230 virtual void getArchDefines(const LangOptions &Opts, 4231 MacroBuilder &Builder) const { 4232 Builder.defineMacro("__le32__"); 4233 Builder.defineMacro("__pnacl__"); 4234 } 4235 virtual void getTargetDefines(const LangOptions &Opts, 4236 MacroBuilder &Builder) const { 4237 Builder.defineMacro("__LITTLE_ENDIAN__"); 4238 getArchDefines(Opts, Builder); 4239 } 4240 virtual bool hasFeature(StringRef Feature) const { 4241 return Feature == "pnacl"; 4242 } 4243 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4244 unsigned &NumRecords) const { 4245 } 4246 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4247 return TargetInfo::PNaClABIBuiltinVaList; 4248 } 4249 virtual void getGCCRegNames(const char * const *&Names, 4250 unsigned &NumNames) const; 4251 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4252 unsigned &NumAliases) const; 4253 virtual bool validateAsmConstraint(const char *&Name, 4254 TargetInfo::ConstraintInfo &Info) const { 4255 return false; 4256 } 4257 4258 virtual const char *getClobbers() const { 4259 return ""; 4260 } 4261 }; 4262 4263 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 4264 unsigned &NumNames) const { 4265 Names = NULL; 4266 NumNames = 0; 4267 } 4268 4269 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4270 unsigned &NumAliases) const { 4271 Aliases = NULL; 4272 NumAliases = 0; 4273 } 4274 } // end anonymous namespace. 4275 4276 4277 //===----------------------------------------------------------------------===// 4278 // Driver code 4279 //===----------------------------------------------------------------------===// 4280 4281 static TargetInfo *AllocateTarget(const std::string &T) { 4282 llvm::Triple Triple(T); 4283 llvm::Triple::OSType os = Triple.getOS(); 4284 4285 switch (Triple.getArch()) { 4286 default: 4287 return NULL; 4288 4289 case llvm::Triple::hexagon: 4290 return new HexagonTargetInfo(T); 4291 4292 case llvm::Triple::arm: 4293 case llvm::Triple::thumb: 4294 if (Triple.isOSDarwin()) 4295 return new DarwinARMTargetInfo(T); 4296 4297 switch (os) { 4298 case llvm::Triple::Linux: 4299 return new LinuxTargetInfo<ARMTargetInfo>(T); 4300 case llvm::Triple::FreeBSD: 4301 return new FreeBSDTargetInfo<ARMTargetInfo>(T); 4302 case llvm::Triple::NetBSD: 4303 return new NetBSDTargetInfo<ARMTargetInfo>(T); 4304 case llvm::Triple::OpenBSD: 4305 return new OpenBSDTargetInfo<ARMTargetInfo>(T); 4306 case llvm::Triple::Bitrig: 4307 return new BitrigTargetInfo<ARMTargetInfo>(T); 4308 case llvm::Triple::RTEMS: 4309 return new RTEMSTargetInfo<ARMTargetInfo>(T); 4310 case llvm::Triple::NativeClient: 4311 return new NaClTargetInfo<ARMTargetInfo>(T); 4312 default: 4313 return new ARMTargetInfo(T); 4314 } 4315 4316 case llvm::Triple::msp430: 4317 return new MSP430TargetInfo(T); 4318 4319 case llvm::Triple::mips: 4320 switch (os) { 4321 case llvm::Triple::Linux: 4322 return new LinuxTargetInfo<Mips32EBTargetInfo>(T); 4323 case llvm::Triple::RTEMS: 4324 return new RTEMSTargetInfo<Mips32EBTargetInfo>(T); 4325 case llvm::Triple::FreeBSD: 4326 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T); 4327 case llvm::Triple::NetBSD: 4328 return new NetBSDTargetInfo<Mips32EBTargetInfo>(T); 4329 default: 4330 return new Mips32EBTargetInfo(T); 4331 } 4332 4333 case llvm::Triple::mipsel: 4334 switch (os) { 4335 case llvm::Triple::Linux: 4336 return new LinuxTargetInfo<Mips32ELTargetInfo>(T); 4337 case llvm::Triple::RTEMS: 4338 return new RTEMSTargetInfo<Mips32ELTargetInfo>(T); 4339 case llvm::Triple::FreeBSD: 4340 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T); 4341 case llvm::Triple::NetBSD: 4342 return new NetBSDTargetInfo<Mips32ELTargetInfo>(T); 4343 default: 4344 return new Mips32ELTargetInfo(T); 4345 } 4346 4347 case llvm::Triple::mips64: 4348 switch (os) { 4349 case llvm::Triple::Linux: 4350 return new LinuxTargetInfo<Mips64EBTargetInfo>(T); 4351 case llvm::Triple::RTEMS: 4352 return new RTEMSTargetInfo<Mips64EBTargetInfo>(T); 4353 case llvm::Triple::FreeBSD: 4354 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T); 4355 case llvm::Triple::NetBSD: 4356 return new NetBSDTargetInfo<Mips64EBTargetInfo>(T); 4357 case llvm::Triple::OpenBSD: 4358 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(T); 4359 default: 4360 return new Mips64EBTargetInfo(T); 4361 } 4362 4363 case llvm::Triple::mips64el: 4364 switch (os) { 4365 case llvm::Triple::Linux: 4366 return new LinuxTargetInfo<Mips64ELTargetInfo>(T); 4367 case llvm::Triple::RTEMS: 4368 return new RTEMSTargetInfo<Mips64ELTargetInfo>(T); 4369 case llvm::Triple::FreeBSD: 4370 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T); 4371 case llvm::Triple::NetBSD: 4372 return new NetBSDTargetInfo<Mips64ELTargetInfo>(T); 4373 case llvm::Triple::OpenBSD: 4374 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(T); 4375 default: 4376 return new Mips64ELTargetInfo(T); 4377 } 4378 4379 case llvm::Triple::le32: 4380 switch (os) { 4381 case llvm::Triple::NativeClient: 4382 return new NaClTargetInfo<PNaClTargetInfo>(T); 4383 default: 4384 return NULL; 4385 } 4386 4387 case llvm::Triple::ppc: 4388 if (Triple.isOSDarwin()) 4389 return new DarwinPPC32TargetInfo(T); 4390 switch (os) { 4391 case llvm::Triple::Linux: 4392 return new LinuxTargetInfo<PPC32TargetInfo>(T); 4393 case llvm::Triple::FreeBSD: 4394 return new FreeBSDTargetInfo<PPC32TargetInfo>(T); 4395 case llvm::Triple::NetBSD: 4396 return new NetBSDTargetInfo<PPC32TargetInfo>(T); 4397 case llvm::Triple::OpenBSD: 4398 return new OpenBSDTargetInfo<PPC32TargetInfo>(T); 4399 case llvm::Triple::RTEMS: 4400 return new RTEMSTargetInfo<PPC32TargetInfo>(T); 4401 default: 4402 return new PPC32TargetInfo(T); 4403 } 4404 4405 case llvm::Triple::ppc64: 4406 if (Triple.isOSDarwin()) 4407 return new DarwinPPC64TargetInfo(T); 4408 switch (os) { 4409 case llvm::Triple::Linux: 4410 return new LinuxTargetInfo<PPC64TargetInfo>(T); 4411 case llvm::Triple::Lv2: 4412 return new PS3PPUTargetInfo<PPC64TargetInfo>(T); 4413 case llvm::Triple::FreeBSD: 4414 return new FreeBSDTargetInfo<PPC64TargetInfo>(T); 4415 case llvm::Triple::NetBSD: 4416 return new NetBSDTargetInfo<PPC64TargetInfo>(T); 4417 default: 4418 return new PPC64TargetInfo(T); 4419 } 4420 4421 case llvm::Triple::nvptx: 4422 return new NVPTX32TargetInfo(T); 4423 case llvm::Triple::nvptx64: 4424 return new NVPTX64TargetInfo(T); 4425 4426 case llvm::Triple::mblaze: 4427 return new MBlazeTargetInfo(T); 4428 4429 case llvm::Triple::sparc: 4430 switch (os) { 4431 case llvm::Triple::Linux: 4432 return new LinuxTargetInfo<SparcV8TargetInfo>(T); 4433 case llvm::Triple::AuroraUX: 4434 return new AuroraUXSparcV8TargetInfo(T); 4435 case llvm::Triple::Solaris: 4436 return new SolarisSparcV8TargetInfo(T); 4437 case llvm::Triple::NetBSD: 4438 return new NetBSDTargetInfo<SparcV8TargetInfo>(T); 4439 case llvm::Triple::OpenBSD: 4440 return new OpenBSDTargetInfo<SparcV8TargetInfo>(T); 4441 case llvm::Triple::RTEMS: 4442 return new RTEMSTargetInfo<SparcV8TargetInfo>(T); 4443 default: 4444 return new SparcV8TargetInfo(T); 4445 } 4446 4447 // FIXME: Need a real SPU target. 4448 case llvm::Triple::cellspu: 4449 return new PS3SPUTargetInfo<PPC64TargetInfo>(T); 4450 4451 case llvm::Triple::tce: 4452 return new TCETargetInfo(T); 4453 4454 case llvm::Triple::x86: 4455 if (Triple.isOSDarwin()) 4456 return new DarwinI386TargetInfo(T); 4457 4458 switch (os) { 4459 case llvm::Triple::AuroraUX: 4460 return new AuroraUXTargetInfo<X86_32TargetInfo>(T); 4461 case llvm::Triple::Linux: 4462 return new LinuxTargetInfo<X86_32TargetInfo>(T); 4463 case llvm::Triple::DragonFly: 4464 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T); 4465 case llvm::Triple::NetBSD: 4466 return new NetBSDI386TargetInfo(T); 4467 case llvm::Triple::OpenBSD: 4468 return new OpenBSDI386TargetInfo(T); 4469 case llvm::Triple::Bitrig: 4470 return new BitrigI386TargetInfo(T); 4471 case llvm::Triple::FreeBSD: 4472 return new FreeBSDTargetInfo<X86_32TargetInfo>(T); 4473 case llvm::Triple::Minix: 4474 return new MinixTargetInfo<X86_32TargetInfo>(T); 4475 case llvm::Triple::Solaris: 4476 return new SolarisTargetInfo<X86_32TargetInfo>(T); 4477 case llvm::Triple::Cygwin: 4478 return new CygwinX86_32TargetInfo(T); 4479 case llvm::Triple::MinGW32: 4480 return new MinGWX86_32TargetInfo(T); 4481 case llvm::Triple::Win32: 4482 return new VisualStudioWindowsX86_32TargetInfo(T); 4483 case llvm::Triple::Haiku: 4484 return new HaikuX86_32TargetInfo(T); 4485 case llvm::Triple::RTEMS: 4486 return new RTEMSX86_32TargetInfo(T); 4487 case llvm::Triple::NativeClient: 4488 return new NaClTargetInfo<X86_32TargetInfo>(T); 4489 default: 4490 return new X86_32TargetInfo(T); 4491 } 4492 4493 case llvm::Triple::x86_64: 4494 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO) 4495 return new DarwinX86_64TargetInfo(T); 4496 4497 switch (os) { 4498 case llvm::Triple::AuroraUX: 4499 return new AuroraUXTargetInfo<X86_64TargetInfo>(T); 4500 case llvm::Triple::Linux: 4501 return new LinuxTargetInfo<X86_64TargetInfo>(T); 4502 case llvm::Triple::DragonFly: 4503 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T); 4504 case llvm::Triple::NetBSD: 4505 return new NetBSDTargetInfo<X86_64TargetInfo>(T); 4506 case llvm::Triple::OpenBSD: 4507 return new OpenBSDX86_64TargetInfo(T); 4508 case llvm::Triple::Bitrig: 4509 return new BitrigX86_64TargetInfo(T); 4510 case llvm::Triple::FreeBSD: 4511 return new FreeBSDTargetInfo<X86_64TargetInfo>(T); 4512 case llvm::Triple::Solaris: 4513 return new SolarisTargetInfo<X86_64TargetInfo>(T); 4514 case llvm::Triple::MinGW32: 4515 return new MinGWX86_64TargetInfo(T); 4516 case llvm::Triple::Win32: // This is what Triple.h supports now. 4517 return new VisualStudioWindowsX86_64TargetInfo(T); 4518 case llvm::Triple::NativeClient: 4519 return new NaClTargetInfo<X86_64TargetInfo>(T); 4520 default: 4521 return new X86_64TargetInfo(T); 4522 } 4523 } 4524 } 4525 4526 /// CreateTargetInfo - Return the target info object for the specified target 4527 /// triple. 4528 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 4529 TargetOptions &Opts) { 4530 llvm::Triple Triple(Opts.Triple); 4531 4532 // Construct the target 4533 OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str())); 4534 if (!Target) { 4535 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 4536 return 0; 4537 } 4538 4539 // Set the target CPU if specified. 4540 if (!Opts.CPU.empty() && !Target->setCPU(Opts.CPU)) { 4541 Diags.Report(diag::err_target_unknown_cpu) << Opts.CPU; 4542 return 0; 4543 } 4544 4545 // Set the target ABI if specified. 4546 if (!Opts.ABI.empty() && !Target->setABI(Opts.ABI)) { 4547 Diags.Report(diag::err_target_unknown_abi) << Opts.ABI; 4548 return 0; 4549 } 4550 4551 // Set the target C++ ABI. 4552 if (!Opts.CXXABI.empty() && !Target->setCXXABI(Opts.CXXABI)) { 4553 Diags.Report(diag::err_target_unknown_cxxabi) << Opts.CXXABI; 4554 return 0; 4555 } 4556 4557 // Compute the default target features, we need the target to handle this 4558 // because features may have dependencies on one another. 4559 llvm::StringMap<bool> Features; 4560 Target->getDefaultFeatures(Features); 4561 4562 // Apply the user specified deltas. 4563 // First the enables. 4564 for (std::vector<std::string>::const_iterator it = Opts.Features.begin(), 4565 ie = Opts.Features.end(); it != ie; ++it) { 4566 const char *Name = it->c_str(); 4567 4568 if (Name[0] != '+') 4569 continue; 4570 4571 // Apply the feature via the target. 4572 if (!Target->setFeatureEnabled(Features, Name + 1, true)) { 4573 Diags.Report(diag::err_target_invalid_feature) << Name; 4574 return 0; 4575 } 4576 } 4577 4578 // Then the disables. 4579 for (std::vector<std::string>::const_iterator it = Opts.Features.begin(), 4580 ie = Opts.Features.end(); it != ie; ++it) { 4581 const char *Name = it->c_str(); 4582 4583 if (Name[0] == '+') 4584 continue; 4585 4586 // Apply the feature via the target. 4587 if (Name[0] != '-' || 4588 !Target->setFeatureEnabled(Features, Name + 1, false)) { 4589 Diags.Report(diag::err_target_invalid_feature) << Name; 4590 return 0; 4591 } 4592 } 4593 4594 // Add the features to the compile options. 4595 // 4596 // FIXME: If we are completely confident that we have the right set, we only 4597 // need to pass the minuses. 4598 Opts.Features.clear(); 4599 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 4600 ie = Features.end(); it != ie; ++it) 4601 Opts.Features.push_back((it->second ? "+" : "-") + it->first().str()); 4602 Target->HandleTargetFeatures(Opts.Features); 4603 4604 return Target.take(); 4605 } 4606