1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/IR/Type.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include <algorithm> 32 #include <memory> 33 using namespace clang; 34 35 //===----------------------------------------------------------------------===// 36 // Common code shared among targets. 37 //===----------------------------------------------------------------------===// 38 39 /// DefineStd - Define a macro name and standard variants. For example if 40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 41 /// when in GNU mode. 42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 43 const LangOptions &Opts) { 44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 45 46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 47 // in the user's namespace. 48 if (Opts.GNUMode) 49 Builder.defineMacro(MacroName); 50 51 // Define __unix. 52 Builder.defineMacro("__" + MacroName); 53 54 // Define __unix__. 55 Builder.defineMacro("__" + MacroName + "__"); 56 } 57 58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 59 bool Tuning = true) { 60 Builder.defineMacro("__" + CPUName); 61 Builder.defineMacro("__" + CPUName + "__"); 62 if (Tuning) 63 Builder.defineMacro("__tune_" + CPUName + "__"); 64 } 65 66 //===----------------------------------------------------------------------===// 67 // Defines specific to certain operating systems. 68 //===----------------------------------------------------------------------===// 69 70 namespace { 71 template<typename TgtInfo> 72 class OSTargetInfo : public TgtInfo { 73 protected: 74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 75 MacroBuilder &Builder) const=0; 76 public: 77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 78 void getTargetDefines(const LangOptions &Opts, 79 MacroBuilder &Builder) const override { 80 TgtInfo::getTargetDefines(Opts, Builder); 81 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 82 } 83 84 }; 85 } // end anonymous namespace 86 87 88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 89 const llvm::Triple &Triple, 90 StringRef &PlatformName, 91 VersionTuple &PlatformMinVersion) { 92 Builder.defineMacro("__APPLE_CC__", "6000"); 93 Builder.defineMacro("__APPLE__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.has(SanitizerKind::Address)) 98 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 99 100 if (!Opts.ObjCAutoRefCount) { 101 // __weak is always defined, for use in blocks and with objc pointers. 102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 103 104 // Darwin defines __strong even in C mode (just to nothing). 105 if (Opts.getGC() != LangOptions::NonGC) 106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 107 else 108 Builder.defineMacro("__strong", ""); 109 110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 111 // allow this in C, since one might have block pointers in structs that 112 // are used in pure C code and in Objective-C ARC. 113 Builder.defineMacro("__unsafe_unretained", ""); 114 } 115 116 if (Opts.Static) 117 Builder.defineMacro("__STATIC__"); 118 else 119 Builder.defineMacro("__DYNAMIC__"); 120 121 if (Opts.POSIXThreads) 122 Builder.defineMacro("_REENTRANT"); 123 124 // Get the platform type and version number from the triple. 125 unsigned Maj, Min, Rev; 126 if (Triple.isMacOSX()) { 127 Triple.getMacOSXVersion(Maj, Min, Rev); 128 PlatformName = "macosx"; 129 } else { 130 Triple.getOSVersion(Maj, Min, Rev); 131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 132 } 133 134 // If -target arch-pc-win32-macho option specified, we're 135 // generating code for Win32 ABI. No need to emit 136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 137 if (PlatformName == "win32") { 138 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 139 return; 140 } 141 142 // Set the appropriate OS version define. 143 if (Triple.isiOS()) { 144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 145 char Str[6]; 146 Str[0] = '0' + Maj; 147 Str[1] = '0' + (Min / 10); 148 Str[2] = '0' + (Min % 10); 149 Str[3] = '0' + (Rev / 10); 150 Str[4] = '0' + (Rev % 10); 151 Str[5] = '\0'; 152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 153 Str); 154 } else if (Triple.isMacOSX()) { 155 // Note that the Driver allows versions which aren't representable in the 156 // define (because we only get a single digit for the minor and micro 157 // revision numbers). So, we limit them to the maximum representable 158 // version. 159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 160 char Str[7]; 161 if (Maj < 10 || (Maj == 10 && Min < 10)) { 162 Str[0] = '0' + (Maj / 10); 163 Str[1] = '0' + (Maj % 10); 164 Str[2] = '0' + std::min(Min, 9U); 165 Str[3] = '0' + std::min(Rev, 9U); 166 Str[4] = '\0'; 167 } else { 168 // Handle versions > 10.9. 169 Str[0] = '0' + (Maj / 10); 170 Str[1] = '0' + (Maj % 10); 171 Str[2] = '0' + (Min / 10); 172 Str[3] = '0' + (Min % 10); 173 Str[4] = '0' + (Rev / 10); 174 Str[5] = '0' + (Rev % 10); 175 Str[6] = '\0'; 176 } 177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 178 } 179 180 // Tell users about the kernel if there is one. 181 if (Triple.isOSDarwin()) 182 Builder.defineMacro("__MACH__"); 183 184 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 185 } 186 187 namespace { 188 template<typename Target> 189 class DarwinTargetInfo : public OSTargetInfo<Target> { 190 protected: 191 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 192 MacroBuilder &Builder) const override { 193 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 194 this->PlatformMinVersion); 195 } 196 197 public: 198 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 199 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 200 this->MCountName = "\01mcount"; 201 } 202 203 std::string isValidSectionSpecifier(StringRef SR) const override { 204 // Let MCSectionMachO validate this. 205 StringRef Segment, Section; 206 unsigned TAA, StubSize; 207 bool HasTAA; 208 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 209 TAA, HasTAA, StubSize); 210 } 211 212 const char *getStaticInitSectionSpecifier() const override { 213 // FIXME: We should return 0 when building kexts. 214 return "__TEXT,__StaticInit,regular,pure_instructions"; 215 } 216 217 /// Darwin does not support protected visibility. Darwin's "default" 218 /// is very similar to ELF's "protected"; Darwin requires a "weak" 219 /// attribute on declarations that can be dynamically replaced. 220 bool hasProtectedVisibility() const override { 221 return false; 222 } 223 }; 224 225 226 // DragonFlyBSD Target 227 template<typename Target> 228 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 229 protected: 230 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 231 MacroBuilder &Builder) const override { 232 // DragonFly defines; list based off of gcc output 233 Builder.defineMacro("__DragonFly__"); 234 Builder.defineMacro("__DragonFly_cc_version", "100001"); 235 Builder.defineMacro("__ELF__"); 236 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 237 Builder.defineMacro("__tune_i386__"); 238 DefineStd(Builder, "unix", Opts); 239 } 240 public: 241 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 242 : OSTargetInfo<Target>(Triple) { 243 this->UserLabelPrefix = ""; 244 245 switch (Triple.getArch()) { 246 default: 247 case llvm::Triple::x86: 248 case llvm::Triple::x86_64: 249 this->MCountName = ".mcount"; 250 break; 251 } 252 } 253 }; 254 255 // FreeBSD Target 256 template<typename Target> 257 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 258 protected: 259 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 260 MacroBuilder &Builder) const override { 261 // FreeBSD defines; list based off of gcc output 262 263 unsigned Release = Triple.getOSMajorVersion(); 264 if (Release == 0U) 265 Release = 8; 266 267 Builder.defineMacro("__FreeBSD__", Twine(Release)); 268 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 269 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 270 DefineStd(Builder, "unix", Opts); 271 Builder.defineMacro("__ELF__"); 272 273 // On FreeBSD, wchar_t contains the number of the code point as 274 // used by the character set of the locale. These character sets are 275 // not necessarily a superset of ASCII. 276 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 277 } 278 public: 279 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 280 this->UserLabelPrefix = ""; 281 282 switch (Triple.getArch()) { 283 default: 284 case llvm::Triple::x86: 285 case llvm::Triple::x86_64: 286 this->MCountName = ".mcount"; 287 break; 288 case llvm::Triple::mips: 289 case llvm::Triple::mipsel: 290 case llvm::Triple::ppc: 291 case llvm::Triple::ppc64: 292 case llvm::Triple::ppc64le: 293 this->MCountName = "_mcount"; 294 break; 295 case llvm::Triple::arm: 296 this->MCountName = "__mcount"; 297 break; 298 } 299 } 300 }; 301 302 // GNU/kFreeBSD Target 303 template<typename Target> 304 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 305 protected: 306 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 307 MacroBuilder &Builder) const override { 308 // GNU/kFreeBSD defines; list based off of gcc output 309 310 DefineStd(Builder, "unix", Opts); 311 Builder.defineMacro("__FreeBSD_kernel__"); 312 Builder.defineMacro("__GLIBC__"); 313 Builder.defineMacro("__ELF__"); 314 if (Opts.POSIXThreads) 315 Builder.defineMacro("_REENTRANT"); 316 if (Opts.CPlusPlus) 317 Builder.defineMacro("_GNU_SOURCE"); 318 } 319 public: 320 KFreeBSDTargetInfo(const llvm::Triple &Triple) 321 : OSTargetInfo<Target>(Triple) { 322 this->UserLabelPrefix = ""; 323 } 324 }; 325 326 // Minix Target 327 template<typename Target> 328 class MinixTargetInfo : public OSTargetInfo<Target> { 329 protected: 330 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 331 MacroBuilder &Builder) const override { 332 // Minix defines 333 334 Builder.defineMacro("__minix", "3"); 335 Builder.defineMacro("_EM_WSIZE", "4"); 336 Builder.defineMacro("_EM_PSIZE", "4"); 337 Builder.defineMacro("_EM_SSIZE", "2"); 338 Builder.defineMacro("_EM_LSIZE", "4"); 339 Builder.defineMacro("_EM_FSIZE", "4"); 340 Builder.defineMacro("_EM_DSIZE", "8"); 341 Builder.defineMacro("__ELF__"); 342 DefineStd(Builder, "unix", Opts); 343 } 344 public: 345 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 346 this->UserLabelPrefix = ""; 347 } 348 }; 349 350 // Linux target 351 template<typename Target> 352 class LinuxTargetInfo : public OSTargetInfo<Target> { 353 protected: 354 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 355 MacroBuilder &Builder) const override { 356 // Linux defines; list based off of gcc output 357 DefineStd(Builder, "unix", Opts); 358 DefineStd(Builder, "linux", Opts); 359 Builder.defineMacro("__gnu_linux__"); 360 Builder.defineMacro("__ELF__"); 361 if (Triple.getEnvironment() == llvm::Triple::Android) 362 Builder.defineMacro("__ANDROID__", "1"); 363 if (Opts.POSIXThreads) 364 Builder.defineMacro("_REENTRANT"); 365 if (Opts.CPlusPlus) 366 Builder.defineMacro("_GNU_SOURCE"); 367 } 368 public: 369 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 370 this->UserLabelPrefix = ""; 371 this->WIntType = TargetInfo::UnsignedInt; 372 373 switch (Triple.getArch()) { 374 default: 375 break; 376 case llvm::Triple::ppc: 377 case llvm::Triple::ppc64: 378 case llvm::Triple::ppc64le: 379 this->MCountName = "_mcount"; 380 break; 381 } 382 } 383 384 const char *getStaticInitSectionSpecifier() const override { 385 return ".text.startup"; 386 } 387 }; 388 389 // NetBSD Target 390 template<typename Target> 391 class NetBSDTargetInfo : public OSTargetInfo<Target> { 392 protected: 393 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 394 MacroBuilder &Builder) const override { 395 // NetBSD defines; list based off of gcc output 396 Builder.defineMacro("__NetBSD__"); 397 Builder.defineMacro("__unix__"); 398 Builder.defineMacro("__ELF__"); 399 if (Opts.POSIXThreads) 400 Builder.defineMacro("_POSIX_THREADS"); 401 402 switch (Triple.getArch()) { 403 default: 404 break; 405 case llvm::Triple::arm: 406 case llvm::Triple::armeb: 407 case llvm::Triple::thumb: 408 case llvm::Triple::thumbeb: 409 Builder.defineMacro("__ARM_DWARF_EH__"); 410 break; 411 } 412 } 413 public: 414 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 415 this->UserLabelPrefix = ""; 416 } 417 }; 418 419 // OpenBSD Target 420 template<typename Target> 421 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 422 protected: 423 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 424 MacroBuilder &Builder) const override { 425 // OpenBSD defines; list based off of gcc output 426 427 Builder.defineMacro("__OpenBSD__"); 428 DefineStd(Builder, "unix", Opts); 429 Builder.defineMacro("__ELF__"); 430 if (Opts.POSIXThreads) 431 Builder.defineMacro("_REENTRANT"); 432 } 433 public: 434 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 435 this->UserLabelPrefix = ""; 436 this->TLSSupported = false; 437 438 switch (Triple.getArch()) { 439 default: 440 case llvm::Triple::x86: 441 case llvm::Triple::x86_64: 442 case llvm::Triple::arm: 443 case llvm::Triple::sparc: 444 this->MCountName = "__mcount"; 445 break; 446 case llvm::Triple::mips64: 447 case llvm::Triple::mips64el: 448 case llvm::Triple::ppc: 449 case llvm::Triple::sparcv9: 450 this->MCountName = "_mcount"; 451 break; 452 } 453 } 454 }; 455 456 // Bitrig Target 457 template<typename Target> 458 class BitrigTargetInfo : public OSTargetInfo<Target> { 459 protected: 460 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 461 MacroBuilder &Builder) const override { 462 // Bitrig defines; list based off of gcc output 463 464 Builder.defineMacro("__Bitrig__"); 465 DefineStd(Builder, "unix", Opts); 466 Builder.defineMacro("__ELF__"); 467 if (Opts.POSIXThreads) 468 Builder.defineMacro("_REENTRANT"); 469 } 470 public: 471 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 472 this->UserLabelPrefix = ""; 473 this->MCountName = "__mcount"; 474 } 475 }; 476 477 // PSP Target 478 template<typename Target> 479 class PSPTargetInfo : public OSTargetInfo<Target> { 480 protected: 481 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 482 MacroBuilder &Builder) const override { 483 // PSP defines; list based on the output of the pspdev gcc toolchain. 484 Builder.defineMacro("PSP"); 485 Builder.defineMacro("_PSP"); 486 Builder.defineMacro("__psp__"); 487 Builder.defineMacro("__ELF__"); 488 } 489 public: 490 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 491 this->UserLabelPrefix = ""; 492 } 493 }; 494 495 // PS3 PPU Target 496 template<typename Target> 497 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 498 protected: 499 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 500 MacroBuilder &Builder) const override { 501 // PS3 PPU defines. 502 Builder.defineMacro("__PPC__"); 503 Builder.defineMacro("__PPU__"); 504 Builder.defineMacro("__CELLOS_LV2__"); 505 Builder.defineMacro("__ELF__"); 506 Builder.defineMacro("__LP32__"); 507 Builder.defineMacro("_ARCH_PPC64"); 508 Builder.defineMacro("__powerpc64__"); 509 } 510 public: 511 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 512 this->UserLabelPrefix = ""; 513 this->LongWidth = this->LongAlign = 32; 514 this->PointerWidth = this->PointerAlign = 32; 515 this->IntMaxType = TargetInfo::SignedLongLong; 516 this->Int64Type = TargetInfo::SignedLongLong; 517 this->SizeType = TargetInfo::UnsignedInt; 518 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 519 } 520 }; 521 522 // Solaris target 523 template<typename Target> 524 class SolarisTargetInfo : public OSTargetInfo<Target> { 525 protected: 526 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 527 MacroBuilder &Builder) const override { 528 DefineStd(Builder, "sun", Opts); 529 DefineStd(Builder, "unix", Opts); 530 Builder.defineMacro("__ELF__"); 531 Builder.defineMacro("__svr4__"); 532 Builder.defineMacro("__SVR4"); 533 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 534 // newer, but to 500 for everything else. feature_test.h has a check to 535 // ensure that you are not using C99 with an old version of X/Open or C89 536 // with a new version. 537 if (Opts.C99) 538 Builder.defineMacro("_XOPEN_SOURCE", "600"); 539 else 540 Builder.defineMacro("_XOPEN_SOURCE", "500"); 541 if (Opts.CPlusPlus) 542 Builder.defineMacro("__C99FEATURES__"); 543 Builder.defineMacro("_LARGEFILE_SOURCE"); 544 Builder.defineMacro("_LARGEFILE64_SOURCE"); 545 Builder.defineMacro("__EXTENSIONS__"); 546 Builder.defineMacro("_REENTRANT"); 547 } 548 public: 549 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 550 this->UserLabelPrefix = ""; 551 this->WCharType = this->SignedInt; 552 // FIXME: WIntType should be SignedLong 553 } 554 }; 555 556 // Windows target 557 template<typename Target> 558 class WindowsTargetInfo : public OSTargetInfo<Target> { 559 protected: 560 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 561 MacroBuilder &Builder) const override { 562 Builder.defineMacro("_WIN32"); 563 } 564 void getVisualStudioDefines(const LangOptions &Opts, 565 MacroBuilder &Builder) const { 566 if (Opts.CPlusPlus) { 567 if (Opts.RTTIData) 568 Builder.defineMacro("_CPPRTTI"); 569 570 if (Opts.Exceptions) 571 Builder.defineMacro("_CPPUNWIND"); 572 } 573 574 if (!Opts.CharIsSigned) 575 Builder.defineMacro("_CHAR_UNSIGNED"); 576 577 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 578 // but it works for now. 579 if (Opts.POSIXThreads) 580 Builder.defineMacro("_MT"); 581 582 if (Opts.MSCompatibilityVersion) { 583 Builder.defineMacro("_MSC_VER", 584 Twine(Opts.MSCompatibilityVersion / 100000)); 585 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 586 // FIXME We cannot encode the revision information into 32-bits 587 Builder.defineMacro("_MSC_BUILD", Twine(1)); 588 } 589 590 if (Opts.MicrosoftExt) { 591 Builder.defineMacro("_MSC_EXTENSIONS"); 592 593 if (Opts.CPlusPlus11) { 594 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 595 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 596 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 597 } 598 } 599 600 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 601 } 602 603 public: 604 WindowsTargetInfo(const llvm::Triple &Triple) 605 : OSTargetInfo<Target>(Triple) {} 606 }; 607 608 template <typename Target> 609 class NaClTargetInfo : public OSTargetInfo<Target> { 610 protected: 611 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 612 MacroBuilder &Builder) const override { 613 if (Opts.POSIXThreads) 614 Builder.defineMacro("_REENTRANT"); 615 if (Opts.CPlusPlus) 616 Builder.defineMacro("_GNU_SOURCE"); 617 618 DefineStd(Builder, "unix", Opts); 619 Builder.defineMacro("__ELF__"); 620 Builder.defineMacro("__native_client__"); 621 } 622 623 public: 624 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 625 this->UserLabelPrefix = ""; 626 this->LongAlign = 32; 627 this->LongWidth = 32; 628 this->PointerAlign = 32; 629 this->PointerWidth = 32; 630 this->IntMaxType = TargetInfo::SignedLongLong; 631 this->Int64Type = TargetInfo::SignedLongLong; 632 this->DoubleAlign = 64; 633 this->LongDoubleWidth = 64; 634 this->LongDoubleAlign = 64; 635 this->LongLongWidth = 64; 636 this->LongLongAlign = 64; 637 this->SizeType = TargetInfo::UnsignedInt; 638 this->PtrDiffType = TargetInfo::SignedInt; 639 this->IntPtrType = TargetInfo::SignedInt; 640 // RegParmMax is inherited from the underlying architecture 641 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 642 if (Triple.getArch() == llvm::Triple::arm) { 643 this->DescriptionString = 644 "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 645 } else if (Triple.getArch() == llvm::Triple::x86) { 646 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 647 } else if (Triple.getArch() == llvm::Triple::x86_64) { 648 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 649 } else if (Triple.getArch() == llvm::Triple::mipsel) { 650 // Handled on mips' setDescriptionString. 651 } else { 652 assert(Triple.getArch() == llvm::Triple::le32); 653 this->DescriptionString = "e-p:32:32-i64:64"; 654 } 655 } 656 typename Target::CallingConvCheckResult checkCallingConvention( 657 CallingConv CC) const override { 658 return CC == CC_PnaclCall ? Target::CCCR_OK : 659 Target::checkCallingConvention(CC); 660 } 661 }; 662 } // end anonymous namespace. 663 664 //===----------------------------------------------------------------------===// 665 // Specific target implementations. 666 //===----------------------------------------------------------------------===// 667 668 namespace { 669 // PPC abstract base class 670 class PPCTargetInfo : public TargetInfo { 671 static const Builtin::Info BuiltinInfo[]; 672 static const char * const GCCRegNames[]; 673 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 674 std::string CPU; 675 676 // Target cpu features. 677 bool HasVSX; 678 bool HasP8Vector; 679 680 protected: 681 std::string ABI; 682 683 public: 684 PPCTargetInfo(const llvm::Triple &Triple) 685 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false) { 686 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 687 LongDoubleWidth = LongDoubleAlign = 128; 688 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 689 } 690 691 /// \brief Flags for architecture specific defines. 692 typedef enum { 693 ArchDefineNone = 0, 694 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 695 ArchDefinePpcgr = 1 << 1, 696 ArchDefinePpcsq = 1 << 2, 697 ArchDefine440 = 1 << 3, 698 ArchDefine603 = 1 << 4, 699 ArchDefine604 = 1 << 5, 700 ArchDefinePwr4 = 1 << 6, 701 ArchDefinePwr5 = 1 << 7, 702 ArchDefinePwr5x = 1 << 8, 703 ArchDefinePwr6 = 1 << 9, 704 ArchDefinePwr6x = 1 << 10, 705 ArchDefinePwr7 = 1 << 11, 706 ArchDefinePwr8 = 1 << 12, 707 ArchDefineA2 = 1 << 13, 708 ArchDefineA2q = 1 << 14 709 } ArchDefineTypes; 710 711 // Note: GCC recognizes the following additional cpus: 712 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 713 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 714 // titan, rs64. 715 bool setCPU(const std::string &Name) override { 716 bool CPUKnown = llvm::StringSwitch<bool>(Name) 717 .Case("generic", true) 718 .Case("440", true) 719 .Case("450", true) 720 .Case("601", true) 721 .Case("602", true) 722 .Case("603", true) 723 .Case("603e", true) 724 .Case("603ev", true) 725 .Case("604", true) 726 .Case("604e", true) 727 .Case("620", true) 728 .Case("630", true) 729 .Case("g3", true) 730 .Case("7400", true) 731 .Case("g4", true) 732 .Case("7450", true) 733 .Case("g4+", true) 734 .Case("750", true) 735 .Case("970", true) 736 .Case("g5", true) 737 .Case("a2", true) 738 .Case("a2q", true) 739 .Case("e500mc", true) 740 .Case("e5500", true) 741 .Case("power3", true) 742 .Case("pwr3", true) 743 .Case("power4", true) 744 .Case("pwr4", true) 745 .Case("power5", true) 746 .Case("pwr5", true) 747 .Case("power5x", true) 748 .Case("pwr5x", true) 749 .Case("power6", true) 750 .Case("pwr6", true) 751 .Case("power6x", true) 752 .Case("pwr6x", true) 753 .Case("power7", true) 754 .Case("pwr7", true) 755 .Case("power8", true) 756 .Case("pwr8", true) 757 .Case("powerpc", true) 758 .Case("ppc", true) 759 .Case("powerpc64", true) 760 .Case("ppc64", true) 761 .Case("powerpc64le", true) 762 .Case("ppc64le", true) 763 .Default(false); 764 765 if (CPUKnown) 766 CPU = Name; 767 768 return CPUKnown; 769 } 770 771 772 StringRef getABI() const override { return ABI; } 773 774 void getTargetBuiltins(const Builtin::Info *&Records, 775 unsigned &NumRecords) const override { 776 Records = BuiltinInfo; 777 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 778 } 779 780 bool isCLZForZeroUndef() const override { return false; } 781 782 void getTargetDefines(const LangOptions &Opts, 783 MacroBuilder &Builder) const override; 784 785 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 786 787 bool handleTargetFeatures(std::vector<std::string> &Features, 788 DiagnosticsEngine &Diags) override; 789 bool hasFeature(StringRef Feature) const override; 790 791 void getGCCRegNames(const char * const *&Names, 792 unsigned &NumNames) const override; 793 void getGCCRegAliases(const GCCRegAlias *&Aliases, 794 unsigned &NumAliases) const override; 795 bool validateAsmConstraint(const char *&Name, 796 TargetInfo::ConstraintInfo &Info) const override { 797 switch (*Name) { 798 default: return false; 799 case 'O': // Zero 800 break; 801 case 'b': // Base register 802 case 'f': // Floating point register 803 Info.setAllowsRegister(); 804 break; 805 // FIXME: The following are added to allow parsing. 806 // I just took a guess at what the actions should be. 807 // Also, is more specific checking needed? I.e. specific registers? 808 case 'd': // Floating point register (containing 64-bit value) 809 case 'v': // Altivec vector register 810 Info.setAllowsRegister(); 811 break; 812 case 'w': 813 switch (Name[1]) { 814 case 'd':// VSX vector register to hold vector double data 815 case 'f':// VSX vector register to hold vector float data 816 case 's':// VSX vector register to hold scalar float data 817 case 'a':// Any VSX register 818 case 'c':// An individual CR bit 819 break; 820 default: 821 return false; 822 } 823 Info.setAllowsRegister(); 824 Name++; // Skip over 'w'. 825 break; 826 case 'h': // `MQ', `CTR', or `LINK' register 827 case 'q': // `MQ' register 828 case 'c': // `CTR' register 829 case 'l': // `LINK' register 830 case 'x': // `CR' register (condition register) number 0 831 case 'y': // `CR' register (condition register) 832 case 'z': // `XER[CA]' carry bit (part of the XER register) 833 Info.setAllowsRegister(); 834 break; 835 case 'I': // Signed 16-bit constant 836 case 'J': // Unsigned 16-bit constant shifted left 16 bits 837 // (use `L' instead for SImode constants) 838 case 'K': // Unsigned 16-bit constant 839 case 'L': // Signed 16-bit constant shifted left 16 bits 840 case 'M': // Constant larger than 31 841 case 'N': // Exact power of 2 842 case 'P': // Constant whose negation is a signed 16-bit constant 843 case 'G': // Floating point constant that can be loaded into a 844 // register with one instruction per word 845 case 'H': // Integer/Floating point constant that can be loaded 846 // into a register using three instructions 847 break; 848 case 'm': // Memory operand. Note that on PowerPC targets, m can 849 // include addresses that update the base register. It 850 // is therefore only safe to use `m' in an asm statement 851 // if that asm statement accesses the operand exactly once. 852 // The asm statement must also use `%U<opno>' as a 853 // placeholder for the "update" flag in the corresponding 854 // load or store instruction. For example: 855 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 856 // is correct but: 857 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 858 // is not. Use es rather than m if you don't want the base 859 // register to be updated. 860 case 'e': 861 if (Name[1] != 's') 862 return false; 863 // es: A "stable" memory operand; that is, one which does not 864 // include any automodification of the base register. Unlike 865 // `m', this constraint can be used in asm statements that 866 // might access the operand several times, or that might not 867 // access it at all. 868 Info.setAllowsMemory(); 869 Name++; // Skip over 'e'. 870 break; 871 case 'Q': // Memory operand that is an offset from a register (it is 872 // usually better to use `m' or `es' in asm statements) 873 case 'Z': // Memory operand that is an indexed or indirect from a 874 // register (it is usually better to use `m' or `es' in 875 // asm statements) 876 Info.setAllowsMemory(); 877 Info.setAllowsRegister(); 878 break; 879 case 'R': // AIX TOC entry 880 case 'a': // Address operand that is an indexed or indirect from a 881 // register (`p' is preferable for asm statements) 882 case 'S': // Constant suitable as a 64-bit mask operand 883 case 'T': // Constant suitable as a 32-bit mask operand 884 case 'U': // System V Release 4 small data area reference 885 case 't': // AND masks that can be performed by two rldic{l, r} 886 // instructions 887 case 'W': // Vector constant that does not require memory 888 case 'j': // Vector constant that is all zeros. 889 break; 890 // End FIXME. 891 } 892 return true; 893 } 894 std::string convertConstraint(const char *&Constraint) const override { 895 std::string R; 896 switch (*Constraint) { 897 case 'e': 898 case 'w': 899 // Two-character constraint; add "^" hint for later parsing. 900 R = std::string("^") + std::string(Constraint, 2); 901 Constraint++; 902 break; 903 default: 904 return TargetInfo::convertConstraint(Constraint); 905 } 906 return R; 907 } 908 const char *getClobbers() const override { 909 return ""; 910 } 911 int getEHDataRegisterNumber(unsigned RegNo) const override { 912 if (RegNo == 0) return 3; 913 if (RegNo == 1) return 4; 914 return -1; 915 } 916 }; 917 918 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 919 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 920 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 921 ALL_LANGUAGES }, 922 #include "clang/Basic/BuiltinsPPC.def" 923 }; 924 925 /// handleTargetFeatures - Perform initialization based on the user 926 /// configured set of features. 927 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 928 DiagnosticsEngine &Diags) { 929 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 930 // Ignore disabled features. 931 if (Features[i][0] == '-') 932 continue; 933 934 StringRef Feature = StringRef(Features[i]).substr(1); 935 936 if (Feature == "vsx") { 937 HasVSX = true; 938 continue; 939 } 940 941 if (Feature == "power8-vector") { 942 HasP8Vector = true; 943 continue; 944 } 945 946 // TODO: Finish this list and add an assert that we've handled them 947 // all. 948 } 949 950 return true; 951 } 952 953 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 954 /// #defines that are not tied to a specific subtarget. 955 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 956 MacroBuilder &Builder) const { 957 // Target identification. 958 Builder.defineMacro("__ppc__"); 959 Builder.defineMacro("__PPC__"); 960 Builder.defineMacro("_ARCH_PPC"); 961 Builder.defineMacro("__powerpc__"); 962 Builder.defineMacro("__POWERPC__"); 963 if (PointerWidth == 64) { 964 Builder.defineMacro("_ARCH_PPC64"); 965 Builder.defineMacro("__powerpc64__"); 966 Builder.defineMacro("__ppc64__"); 967 Builder.defineMacro("__PPC64__"); 968 } 969 970 // Target properties. 971 if (getTriple().getArch() == llvm::Triple::ppc64le) { 972 Builder.defineMacro("_LITTLE_ENDIAN"); 973 } else { 974 if (getTriple().getOS() != llvm::Triple::NetBSD && 975 getTriple().getOS() != llvm::Triple::OpenBSD) 976 Builder.defineMacro("_BIG_ENDIAN"); 977 } 978 979 // ABI options. 980 if (ABI == "elfv1") 981 Builder.defineMacro("_CALL_ELF", "1"); 982 if (ABI == "elfv2") 983 Builder.defineMacro("_CALL_ELF", "2"); 984 985 // Subtarget options. 986 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 987 Builder.defineMacro("__REGISTER_PREFIX__", ""); 988 989 // FIXME: Should be controlled by command line option. 990 if (LongDoubleWidth == 128) 991 Builder.defineMacro("__LONG_DOUBLE_128__"); 992 993 if (Opts.AltiVec) { 994 Builder.defineMacro("__VEC__", "10206"); 995 Builder.defineMacro("__ALTIVEC__"); 996 } 997 998 // CPU identification. 999 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1000 .Case("440", ArchDefineName) 1001 .Case("450", ArchDefineName | ArchDefine440) 1002 .Case("601", ArchDefineName) 1003 .Case("602", ArchDefineName | ArchDefinePpcgr) 1004 .Case("603", ArchDefineName | ArchDefinePpcgr) 1005 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1006 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1007 .Case("604", ArchDefineName | ArchDefinePpcgr) 1008 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1009 .Case("620", ArchDefineName | ArchDefinePpcgr) 1010 .Case("630", ArchDefineName | ArchDefinePpcgr) 1011 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1012 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1013 .Case("750", ArchDefineName | ArchDefinePpcgr) 1014 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1015 | ArchDefinePpcsq) 1016 .Case("a2", ArchDefineA2) 1017 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1018 .Case("pwr3", ArchDefinePpcgr) 1019 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1020 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1021 | ArchDefinePpcsq) 1022 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1023 | ArchDefinePpcgr | ArchDefinePpcsq) 1024 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1025 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1026 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1027 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1028 | ArchDefinePpcsq) 1029 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1030 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1031 | ArchDefinePpcgr | ArchDefinePpcsq) 1032 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1033 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1034 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1035 .Case("power3", ArchDefinePpcgr) 1036 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1037 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1038 | ArchDefinePpcsq) 1039 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1040 | ArchDefinePpcgr | ArchDefinePpcsq) 1041 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1042 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1043 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1044 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1045 | ArchDefinePpcsq) 1046 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1047 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1048 | ArchDefinePpcgr | ArchDefinePpcsq) 1049 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1050 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1051 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1052 .Default(ArchDefineNone); 1053 1054 if (defs & ArchDefineName) 1055 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1056 if (defs & ArchDefinePpcgr) 1057 Builder.defineMacro("_ARCH_PPCGR"); 1058 if (defs & ArchDefinePpcsq) 1059 Builder.defineMacro("_ARCH_PPCSQ"); 1060 if (defs & ArchDefine440) 1061 Builder.defineMacro("_ARCH_440"); 1062 if (defs & ArchDefine603) 1063 Builder.defineMacro("_ARCH_603"); 1064 if (defs & ArchDefine604) 1065 Builder.defineMacro("_ARCH_604"); 1066 if (defs & ArchDefinePwr4) 1067 Builder.defineMacro("_ARCH_PWR4"); 1068 if (defs & ArchDefinePwr5) 1069 Builder.defineMacro("_ARCH_PWR5"); 1070 if (defs & ArchDefinePwr5x) 1071 Builder.defineMacro("_ARCH_PWR5X"); 1072 if (defs & ArchDefinePwr6) 1073 Builder.defineMacro("_ARCH_PWR6"); 1074 if (defs & ArchDefinePwr6x) 1075 Builder.defineMacro("_ARCH_PWR6X"); 1076 if (defs & ArchDefinePwr7) 1077 Builder.defineMacro("_ARCH_PWR7"); 1078 if (defs & ArchDefinePwr8) 1079 Builder.defineMacro("_ARCH_PWR8"); 1080 if (defs & ArchDefineA2) 1081 Builder.defineMacro("_ARCH_A2"); 1082 if (defs & ArchDefineA2q) { 1083 Builder.defineMacro("_ARCH_A2Q"); 1084 Builder.defineMacro("_ARCH_QP"); 1085 } 1086 1087 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1088 Builder.defineMacro("__bg__"); 1089 Builder.defineMacro("__THW_BLUEGENE__"); 1090 Builder.defineMacro("__bgq__"); 1091 Builder.defineMacro("__TOS_BGQ__"); 1092 } 1093 1094 if (HasVSX) 1095 Builder.defineMacro("__VSX__"); 1096 if (HasP8Vector) 1097 Builder.defineMacro("__POWER8_VECTOR__"); 1098 1099 // FIXME: The following are not yet generated here by Clang, but are 1100 // generated by GCC: 1101 // 1102 // _SOFT_FLOAT_ 1103 // __RECIP_PRECISION__ 1104 // __APPLE_ALTIVEC__ 1105 // __RECIP__ 1106 // __RECIPF__ 1107 // __RSQRTE__ 1108 // __RSQRTEF__ 1109 // _SOFT_DOUBLE_ 1110 // __NO_LWSYNC__ 1111 // __HAVE_BSWAP__ 1112 // __LONGDOUBLE128 1113 // __CMODEL_MEDIUM__ 1114 // __CMODEL_LARGE__ 1115 // _CALL_SYSV 1116 // _CALL_DARWIN 1117 // __NO_FPRS__ 1118 } 1119 1120 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1121 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1122 .Case("7400", true) 1123 .Case("g4", true) 1124 .Case("7450", true) 1125 .Case("g4+", true) 1126 .Case("970", true) 1127 .Case("g5", true) 1128 .Case("pwr6", true) 1129 .Case("pwr7", true) 1130 .Case("pwr8", true) 1131 .Case("ppc64", true) 1132 .Case("ppc64le", true) 1133 .Default(false); 1134 1135 Features["qpx"] = (CPU == "a2q"); 1136 1137 if (!ABI.empty()) 1138 Features[ABI] = true; 1139 } 1140 1141 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1142 return llvm::StringSwitch<bool>(Feature) 1143 .Case("powerpc", true) 1144 .Case("vsx", HasVSX) 1145 .Case("power8-vector", HasP8Vector) 1146 .Default(false); 1147 } 1148 1149 const char * const PPCTargetInfo::GCCRegNames[] = { 1150 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1151 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1152 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1153 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1154 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1155 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1156 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1157 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1158 "mq", "lr", "ctr", "ap", 1159 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1160 "xer", 1161 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1162 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1163 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1164 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1165 "vrsave", "vscr", 1166 "spe_acc", "spefscr", 1167 "sfp" 1168 }; 1169 1170 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1171 unsigned &NumNames) const { 1172 Names = GCCRegNames; 1173 NumNames = llvm::array_lengthof(GCCRegNames); 1174 } 1175 1176 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1177 // While some of these aliases do map to different registers 1178 // they still share the same register name. 1179 { { "0" }, "r0" }, 1180 { { "1"}, "r1" }, 1181 { { "2" }, "r2" }, 1182 { { "3" }, "r3" }, 1183 { { "4" }, "r4" }, 1184 { { "5" }, "r5" }, 1185 { { "6" }, "r6" }, 1186 { { "7" }, "r7" }, 1187 { { "8" }, "r8" }, 1188 { { "9" }, "r9" }, 1189 { { "10" }, "r10" }, 1190 { { "11" }, "r11" }, 1191 { { "12" }, "r12" }, 1192 { { "13" }, "r13" }, 1193 { { "14" }, "r14" }, 1194 { { "15" }, "r15" }, 1195 { { "16" }, "r16" }, 1196 { { "17" }, "r17" }, 1197 { { "18" }, "r18" }, 1198 { { "19" }, "r19" }, 1199 { { "20" }, "r20" }, 1200 { { "21" }, "r21" }, 1201 { { "22" }, "r22" }, 1202 { { "23" }, "r23" }, 1203 { { "24" }, "r24" }, 1204 { { "25" }, "r25" }, 1205 { { "26" }, "r26" }, 1206 { { "27" }, "r27" }, 1207 { { "28" }, "r28" }, 1208 { { "29" }, "r29" }, 1209 { { "30" }, "r30" }, 1210 { { "31" }, "r31" }, 1211 { { "fr0" }, "f0" }, 1212 { { "fr1" }, "f1" }, 1213 { { "fr2" }, "f2" }, 1214 { { "fr3" }, "f3" }, 1215 { { "fr4" }, "f4" }, 1216 { { "fr5" }, "f5" }, 1217 { { "fr6" }, "f6" }, 1218 { { "fr7" }, "f7" }, 1219 { { "fr8" }, "f8" }, 1220 { { "fr9" }, "f9" }, 1221 { { "fr10" }, "f10" }, 1222 { { "fr11" }, "f11" }, 1223 { { "fr12" }, "f12" }, 1224 { { "fr13" }, "f13" }, 1225 { { "fr14" }, "f14" }, 1226 { { "fr15" }, "f15" }, 1227 { { "fr16" }, "f16" }, 1228 { { "fr17" }, "f17" }, 1229 { { "fr18" }, "f18" }, 1230 { { "fr19" }, "f19" }, 1231 { { "fr20" }, "f20" }, 1232 { { "fr21" }, "f21" }, 1233 { { "fr22" }, "f22" }, 1234 { { "fr23" }, "f23" }, 1235 { { "fr24" }, "f24" }, 1236 { { "fr25" }, "f25" }, 1237 { { "fr26" }, "f26" }, 1238 { { "fr27" }, "f27" }, 1239 { { "fr28" }, "f28" }, 1240 { { "fr29" }, "f29" }, 1241 { { "fr30" }, "f30" }, 1242 { { "fr31" }, "f31" }, 1243 { { "cc" }, "cr0" }, 1244 }; 1245 1246 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1247 unsigned &NumAliases) const { 1248 Aliases = GCCRegAliases; 1249 NumAliases = llvm::array_lengthof(GCCRegAliases); 1250 } 1251 } // end anonymous namespace. 1252 1253 namespace { 1254 class PPC32TargetInfo : public PPCTargetInfo { 1255 public: 1256 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1257 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1258 1259 switch (getTriple().getOS()) { 1260 case llvm::Triple::Linux: 1261 case llvm::Triple::FreeBSD: 1262 case llvm::Triple::NetBSD: 1263 SizeType = UnsignedInt; 1264 PtrDiffType = SignedInt; 1265 IntPtrType = SignedInt; 1266 break; 1267 default: 1268 break; 1269 } 1270 1271 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1272 LongDoubleWidth = LongDoubleAlign = 64; 1273 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1274 } 1275 1276 // PPC32 supports atomics up to 4 bytes. 1277 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1278 } 1279 1280 BuiltinVaListKind getBuiltinVaListKind() const override { 1281 // This is the ELF definition, and is overridden by the Darwin sub-target 1282 return TargetInfo::PowerABIBuiltinVaList; 1283 } 1284 }; 1285 } // end anonymous namespace. 1286 1287 // Note: ABI differences may eventually require us to have a separate 1288 // TargetInfo for little endian. 1289 namespace { 1290 class PPC64TargetInfo : public PPCTargetInfo { 1291 public: 1292 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1293 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1294 IntMaxType = SignedLong; 1295 Int64Type = SignedLong; 1296 1297 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1298 DescriptionString = "e-m:e-i64:64-n32:64"; 1299 ABI = "elfv2"; 1300 } else { 1301 DescriptionString = "E-m:e-i64:64-n32:64"; 1302 ABI = "elfv1"; 1303 } 1304 1305 switch (getTriple().getOS()) { 1306 case llvm::Triple::FreeBSD: 1307 LongDoubleWidth = LongDoubleAlign = 64; 1308 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1309 break; 1310 case llvm::Triple::NetBSD: 1311 IntMaxType = SignedLongLong; 1312 Int64Type = SignedLongLong; 1313 break; 1314 default: 1315 break; 1316 } 1317 1318 // PPC64 supports atomics up to 8 bytes. 1319 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1320 } 1321 BuiltinVaListKind getBuiltinVaListKind() const override { 1322 return TargetInfo::CharPtrBuiltinVaList; 1323 } 1324 // PPC64 Linux-specifc ABI options. 1325 bool setABI(const std::string &Name) override { 1326 if (Name == "elfv1" || Name == "elfv2") { 1327 ABI = Name; 1328 return true; 1329 } 1330 return false; 1331 } 1332 }; 1333 } // end anonymous namespace. 1334 1335 1336 namespace { 1337 class DarwinPPC32TargetInfo : 1338 public DarwinTargetInfo<PPC32TargetInfo> { 1339 public: 1340 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1341 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1342 HasAlignMac68kSupport = true; 1343 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1344 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1345 LongLongAlign = 32; 1346 SuitableAlign = 128; 1347 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1348 } 1349 BuiltinVaListKind getBuiltinVaListKind() const override { 1350 return TargetInfo::CharPtrBuiltinVaList; 1351 } 1352 }; 1353 1354 class DarwinPPC64TargetInfo : 1355 public DarwinTargetInfo<PPC64TargetInfo> { 1356 public: 1357 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1358 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1359 HasAlignMac68kSupport = true; 1360 SuitableAlign = 128; 1361 DescriptionString = "E-m:o-i64:64-n32:64"; 1362 } 1363 }; 1364 } // end anonymous namespace. 1365 1366 namespace { 1367 static const unsigned NVPTXAddrSpaceMap[] = { 1368 1, // opencl_global 1369 3, // opencl_local 1370 4, // opencl_constant 1371 // FIXME: generic has to be added to the target 1372 0, // opencl_generic 1373 1, // cuda_device 1374 4, // cuda_constant 1375 3, // cuda_shared 1376 }; 1377 class NVPTXTargetInfo : public TargetInfo { 1378 static const char * const GCCRegNames[]; 1379 static const Builtin::Info BuiltinInfo[]; 1380 1381 // The GPU profiles supported by the NVPTX backend 1382 enum GPUKind { 1383 GK_NONE, 1384 GK_SM20, 1385 GK_SM21, 1386 GK_SM30, 1387 GK_SM35, 1388 } GPU; 1389 1390 public: 1391 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1392 BigEndian = false; 1393 TLSSupported = false; 1394 LongWidth = LongAlign = 64; 1395 AddrSpaceMap = &NVPTXAddrSpaceMap; 1396 UseAddrSpaceMapMangling = true; 1397 // Define available target features 1398 // These must be defined in sorted order! 1399 NoAsmVariants = true; 1400 // Set the default GPU to sm20 1401 GPU = GK_SM20; 1402 } 1403 void getTargetDefines(const LangOptions &Opts, 1404 MacroBuilder &Builder) const override { 1405 Builder.defineMacro("__PTX__"); 1406 Builder.defineMacro("__NVPTX__"); 1407 if (Opts.CUDAIsDevice) { 1408 // Set __CUDA_ARCH__ for the GPU specified. 1409 std::string CUDAArchCode; 1410 switch (GPU) { 1411 case GK_SM20: 1412 CUDAArchCode = "200"; 1413 break; 1414 case GK_SM21: 1415 CUDAArchCode = "210"; 1416 break; 1417 case GK_SM30: 1418 CUDAArchCode = "300"; 1419 break; 1420 case GK_SM35: 1421 CUDAArchCode = "350"; 1422 break; 1423 default: 1424 llvm_unreachable("Unhandled target CPU"); 1425 } 1426 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1427 } 1428 } 1429 void getTargetBuiltins(const Builtin::Info *&Records, 1430 unsigned &NumRecords) const override { 1431 Records = BuiltinInfo; 1432 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1433 } 1434 bool hasFeature(StringRef Feature) const override { 1435 return Feature == "ptx" || Feature == "nvptx"; 1436 } 1437 1438 void getGCCRegNames(const char * const *&Names, 1439 unsigned &NumNames) const override; 1440 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1441 unsigned &NumAliases) const override { 1442 // No aliases. 1443 Aliases = nullptr; 1444 NumAliases = 0; 1445 } 1446 bool 1447 validateAsmConstraint(const char *&Name, 1448 TargetInfo::ConstraintInfo &Info) const override { 1449 switch (*Name) { 1450 default: return false; 1451 case 'c': 1452 case 'h': 1453 case 'r': 1454 case 'l': 1455 case 'f': 1456 case 'd': 1457 Info.setAllowsRegister(); 1458 return true; 1459 } 1460 } 1461 const char *getClobbers() const override { 1462 // FIXME: Is this really right? 1463 return ""; 1464 } 1465 BuiltinVaListKind getBuiltinVaListKind() const override { 1466 // FIXME: implement 1467 return TargetInfo::CharPtrBuiltinVaList; 1468 } 1469 bool setCPU(const std::string &Name) override { 1470 GPU = llvm::StringSwitch<GPUKind>(Name) 1471 .Case("sm_20", GK_SM20) 1472 .Case("sm_21", GK_SM21) 1473 .Case("sm_30", GK_SM30) 1474 .Case("sm_35", GK_SM35) 1475 .Default(GK_NONE); 1476 1477 return GPU != GK_NONE; 1478 } 1479 }; 1480 1481 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1482 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1483 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1484 ALL_LANGUAGES }, 1485 #include "clang/Basic/BuiltinsNVPTX.def" 1486 }; 1487 1488 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1489 "r0" 1490 }; 1491 1492 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1493 unsigned &NumNames) const { 1494 Names = GCCRegNames; 1495 NumNames = llvm::array_lengthof(GCCRegNames); 1496 } 1497 1498 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1499 public: 1500 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1501 PointerWidth = PointerAlign = 32; 1502 SizeType = PtrDiffType = TargetInfo::UnsignedInt; 1503 IntPtrType = TargetInfo::SignedInt; 1504 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1505 } 1506 }; 1507 1508 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1509 public: 1510 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1511 PointerWidth = PointerAlign = 64; 1512 SizeType = PtrDiffType = TargetInfo::UnsignedLongLong; 1513 IntPtrType = TargetInfo::SignedLongLong; 1514 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1515 } 1516 }; 1517 } 1518 1519 namespace { 1520 1521 static const unsigned R600AddrSpaceMap[] = { 1522 1, // opencl_global 1523 3, // opencl_local 1524 2, // opencl_constant 1525 4, // opencl_generic 1526 1, // cuda_device 1527 2, // cuda_constant 1528 3 // cuda_shared 1529 }; 1530 1531 // If you edit the description strings, make sure you update 1532 // getPointerWidthV(). 1533 1534 static const char *DescriptionStringR600 = 1535 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1536 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1537 1538 static const char *DescriptionStringR600DoubleOps = 1539 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1540 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1541 1542 static const char *DescriptionStringSI = 1543 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1544 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1545 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1546 1547 class R600TargetInfo : public TargetInfo { 1548 static const Builtin::Info BuiltinInfo[]; 1549 1550 /// \brief The GPU profiles supported by the R600 target. 1551 enum GPUKind { 1552 GK_NONE, 1553 GK_R600, 1554 GK_R600_DOUBLE_OPS, 1555 GK_R700, 1556 GK_R700_DOUBLE_OPS, 1557 GK_EVERGREEN, 1558 GK_EVERGREEN_DOUBLE_OPS, 1559 GK_NORTHERN_ISLANDS, 1560 GK_CAYMAN, 1561 GK_SOUTHERN_ISLANDS, 1562 GK_SEA_ISLANDS 1563 } GPU; 1564 1565 public: 1566 R600TargetInfo(const llvm::Triple &Triple) 1567 : TargetInfo(Triple), GPU(GK_R600) { 1568 DescriptionString = DescriptionStringR600; 1569 AddrSpaceMap = &R600AddrSpaceMap; 1570 UseAddrSpaceMapMangling = true; 1571 } 1572 1573 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1574 if (GPU <= GK_CAYMAN) 1575 return 32; 1576 1577 switch(AddrSpace) { 1578 default: 1579 return 64; 1580 case 0: 1581 case 3: 1582 case 5: 1583 return 32; 1584 } 1585 } 1586 1587 const char * getClobbers() const override { 1588 return ""; 1589 } 1590 1591 void getGCCRegNames(const char * const *&Names, 1592 unsigned &numNames) const override { 1593 Names = nullptr; 1594 numNames = 0; 1595 } 1596 1597 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1598 unsigned &NumAliases) const override { 1599 Aliases = nullptr; 1600 NumAliases = 0; 1601 } 1602 1603 bool validateAsmConstraint(const char *&Name, 1604 TargetInfo::ConstraintInfo &info) const override { 1605 return true; 1606 } 1607 1608 void getTargetBuiltins(const Builtin::Info *&Records, 1609 unsigned &NumRecords) const override { 1610 Records = BuiltinInfo; 1611 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin; 1612 } 1613 1614 void getTargetDefines(const LangOptions &Opts, 1615 MacroBuilder &Builder) const override { 1616 Builder.defineMacro("__R600__"); 1617 } 1618 1619 BuiltinVaListKind getBuiltinVaListKind() const override { 1620 return TargetInfo::CharPtrBuiltinVaList; 1621 } 1622 1623 bool setCPU(const std::string &Name) override { 1624 GPU = llvm::StringSwitch<GPUKind>(Name) 1625 .Case("r600" , GK_R600) 1626 .Case("rv610", GK_R600) 1627 .Case("rv620", GK_R600) 1628 .Case("rv630", GK_R600) 1629 .Case("rv635", GK_R600) 1630 .Case("rs780", GK_R600) 1631 .Case("rs880", GK_R600) 1632 .Case("rv670", GK_R600_DOUBLE_OPS) 1633 .Case("rv710", GK_R700) 1634 .Case("rv730", GK_R700) 1635 .Case("rv740", GK_R700_DOUBLE_OPS) 1636 .Case("rv770", GK_R700_DOUBLE_OPS) 1637 .Case("palm", GK_EVERGREEN) 1638 .Case("cedar", GK_EVERGREEN) 1639 .Case("sumo", GK_EVERGREEN) 1640 .Case("sumo2", GK_EVERGREEN) 1641 .Case("redwood", GK_EVERGREEN) 1642 .Case("juniper", GK_EVERGREEN) 1643 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1644 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1645 .Case("barts", GK_NORTHERN_ISLANDS) 1646 .Case("turks", GK_NORTHERN_ISLANDS) 1647 .Case("caicos", GK_NORTHERN_ISLANDS) 1648 .Case("cayman", GK_CAYMAN) 1649 .Case("aruba", GK_CAYMAN) 1650 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1651 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1652 .Case("verde", GK_SOUTHERN_ISLANDS) 1653 .Case("oland", GK_SOUTHERN_ISLANDS) 1654 .Case("hainan", GK_SOUTHERN_ISLANDS) 1655 .Case("bonaire", GK_SEA_ISLANDS) 1656 .Case("kabini", GK_SEA_ISLANDS) 1657 .Case("kaveri", GK_SEA_ISLANDS) 1658 .Case("hawaii", GK_SEA_ISLANDS) 1659 .Case("mullins", GK_SEA_ISLANDS) 1660 .Default(GK_NONE); 1661 1662 if (GPU == GK_NONE) { 1663 return false; 1664 } 1665 1666 // Set the correct data layout 1667 switch (GPU) { 1668 case GK_NONE: 1669 case GK_R600: 1670 case GK_R700: 1671 case GK_EVERGREEN: 1672 case GK_NORTHERN_ISLANDS: 1673 DescriptionString = DescriptionStringR600; 1674 break; 1675 case GK_R600_DOUBLE_OPS: 1676 case GK_R700_DOUBLE_OPS: 1677 case GK_EVERGREEN_DOUBLE_OPS: 1678 case GK_CAYMAN: 1679 DescriptionString = DescriptionStringR600DoubleOps; 1680 break; 1681 case GK_SOUTHERN_ISLANDS: 1682 case GK_SEA_ISLANDS: 1683 DescriptionString = DescriptionStringSI; 1684 break; 1685 } 1686 1687 return true; 1688 } 1689 }; 1690 1691 const Builtin::Info R600TargetInfo::BuiltinInfo[] = { 1692 #define BUILTIN(ID, TYPE, ATTRS) \ 1693 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1694 #include "clang/Basic/BuiltinsR600.def" 1695 }; 1696 1697 } // end anonymous namespace 1698 1699 namespace { 1700 // Namespace for x86 abstract base class 1701 const Builtin::Info BuiltinInfo[] = { 1702 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1703 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1704 ALL_LANGUAGES }, 1705 #include "clang/Basic/BuiltinsX86.def" 1706 }; 1707 1708 static const char* const GCCRegNames[] = { 1709 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1710 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1711 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1712 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1713 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1714 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1715 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1716 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1717 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1718 }; 1719 1720 const TargetInfo::AddlRegName AddlRegNames[] = { 1721 { { "al", "ah", "eax", "rax" }, 0 }, 1722 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1723 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1724 { { "dl", "dh", "edx", "rdx" }, 1 }, 1725 { { "esi", "rsi" }, 4 }, 1726 { { "edi", "rdi" }, 5 }, 1727 { { "esp", "rsp" }, 7 }, 1728 { { "ebp", "rbp" }, 6 }, 1729 }; 1730 1731 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1732 // most of the implementation can be shared. 1733 class X86TargetInfo : public TargetInfo { 1734 enum X86SSEEnum { 1735 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1736 } SSELevel; 1737 enum MMX3DNowEnum { 1738 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1739 } MMX3DNowLevel; 1740 enum XOPEnum { 1741 NoXOP, 1742 SSE4A, 1743 FMA4, 1744 XOP 1745 } XOPLevel; 1746 1747 bool HasAES; 1748 bool HasPCLMUL; 1749 bool HasLZCNT; 1750 bool HasRDRND; 1751 bool HasFSGSBASE; 1752 bool HasBMI; 1753 bool HasBMI2; 1754 bool HasPOPCNT; 1755 bool HasRTM; 1756 bool HasPRFCHW; 1757 bool HasRDSEED; 1758 bool HasADX; 1759 bool HasTBM; 1760 bool HasFMA; 1761 bool HasF16C; 1762 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 1763 HasAVX512VL; 1764 bool HasSHA; 1765 bool HasCX16; 1766 1767 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1768 /// 1769 /// Each enumeration represents a particular CPU supported by Clang. These 1770 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1771 enum CPUKind { 1772 CK_Generic, 1773 1774 /// \name i386 1775 /// i386-generation processors. 1776 //@{ 1777 CK_i386, 1778 //@} 1779 1780 /// \name i486 1781 /// i486-generation processors. 1782 //@{ 1783 CK_i486, 1784 CK_WinChipC6, 1785 CK_WinChip2, 1786 CK_C3, 1787 //@} 1788 1789 /// \name i586 1790 /// i586-generation processors, P5 microarchitecture based. 1791 //@{ 1792 CK_i586, 1793 CK_Pentium, 1794 CK_PentiumMMX, 1795 //@} 1796 1797 /// \name i686 1798 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1799 //@{ 1800 CK_i686, 1801 CK_PentiumPro, 1802 CK_Pentium2, 1803 CK_Pentium3, 1804 CK_Pentium3M, 1805 CK_PentiumM, 1806 CK_C3_2, 1807 1808 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1809 /// Clang however has some logic to suport this. 1810 // FIXME: Warn, deprecate, and potentially remove this. 1811 CK_Yonah, 1812 //@} 1813 1814 /// \name Netburst 1815 /// Netburst microarchitecture based processors. 1816 //@{ 1817 CK_Pentium4, 1818 CK_Pentium4M, 1819 CK_Prescott, 1820 CK_Nocona, 1821 //@} 1822 1823 /// \name Core 1824 /// Core microarchitecture based processors. 1825 //@{ 1826 CK_Core2, 1827 1828 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1829 /// codename which GCC no longer accepts as an option to -march, but Clang 1830 /// has some logic for recognizing it. 1831 // FIXME: Warn, deprecate, and potentially remove this. 1832 CK_Penryn, 1833 //@} 1834 1835 /// \name Atom 1836 /// Atom processors 1837 //@{ 1838 CK_Atom, 1839 CK_Silvermont, 1840 //@} 1841 1842 /// \name Nehalem 1843 /// Nehalem microarchitecture based processors. 1844 //@{ 1845 CK_Corei7, 1846 CK_Corei7AVX, 1847 CK_CoreAVXi, 1848 CK_CoreAVX2, 1849 CK_Broadwell, 1850 //@} 1851 1852 /// \name Knights Landing 1853 /// Knights Landing processor. 1854 CK_KNL, 1855 1856 /// \name Skylake Server 1857 /// Skylake server processor. 1858 CK_SKX, 1859 1860 /// \name K6 1861 /// K6 architecture processors. 1862 //@{ 1863 CK_K6, 1864 CK_K6_2, 1865 CK_K6_3, 1866 //@} 1867 1868 /// \name K7 1869 /// K7 architecture processors. 1870 //@{ 1871 CK_Athlon, 1872 CK_AthlonThunderbird, 1873 CK_Athlon4, 1874 CK_AthlonXP, 1875 CK_AthlonMP, 1876 //@} 1877 1878 /// \name K8 1879 /// K8 architecture processors. 1880 //@{ 1881 CK_Athlon64, 1882 CK_Athlon64SSE3, 1883 CK_AthlonFX, 1884 CK_K8, 1885 CK_K8SSE3, 1886 CK_Opteron, 1887 CK_OpteronSSE3, 1888 CK_AMDFAM10, 1889 //@} 1890 1891 /// \name Bobcat 1892 /// Bobcat architecture processors. 1893 //@{ 1894 CK_BTVER1, 1895 CK_BTVER2, 1896 //@} 1897 1898 /// \name Bulldozer 1899 /// Bulldozer architecture processors. 1900 //@{ 1901 CK_BDVER1, 1902 CK_BDVER2, 1903 CK_BDVER3, 1904 CK_BDVER4, 1905 //@} 1906 1907 /// This specification is deprecated and will be removed in the future. 1908 /// Users should prefer \see CK_K8. 1909 // FIXME: Warn on this when the CPU is set to it. 1910 //@{ 1911 CK_x86_64, 1912 //@} 1913 1914 /// \name Geode 1915 /// Geode processors. 1916 //@{ 1917 CK_Geode 1918 //@} 1919 } CPU; 1920 1921 enum FPMathKind { 1922 FP_Default, 1923 FP_SSE, 1924 FP_387 1925 } FPMath; 1926 1927 public: 1928 X86TargetInfo(const llvm::Triple &Triple) 1929 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1930 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1931 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 1932 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 1933 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 1934 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 1935 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 1936 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 1937 BigEndian = false; 1938 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1939 } 1940 unsigned getFloatEvalMethod() const override { 1941 // X87 evaluates with 80 bits "long double" precision. 1942 return SSELevel == NoSSE ? 2 : 0; 1943 } 1944 void getTargetBuiltins(const Builtin::Info *&Records, 1945 unsigned &NumRecords) const override { 1946 Records = BuiltinInfo; 1947 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1948 } 1949 void getGCCRegNames(const char * const *&Names, 1950 unsigned &NumNames) const override { 1951 Names = GCCRegNames; 1952 NumNames = llvm::array_lengthof(GCCRegNames); 1953 } 1954 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1955 unsigned &NumAliases) const override { 1956 Aliases = nullptr; 1957 NumAliases = 0; 1958 } 1959 void getGCCAddlRegNames(const AddlRegName *&Names, 1960 unsigned &NumNames) const override { 1961 Names = AddlRegNames; 1962 NumNames = llvm::array_lengthof(AddlRegNames); 1963 } 1964 bool validateAsmConstraint(const char *&Name, 1965 TargetInfo::ConstraintInfo &info) const override; 1966 1967 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 1968 1969 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 1970 1971 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 1972 1973 std::string convertConstraint(const char *&Constraint) const override; 1974 const char *getClobbers() const override { 1975 return "~{dirflag},~{fpsr},~{flags}"; 1976 } 1977 void getTargetDefines(const LangOptions &Opts, 1978 MacroBuilder &Builder) const override; 1979 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1980 bool Enabled); 1981 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1982 bool Enabled); 1983 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1984 bool Enabled); 1985 void setFeatureEnabled(llvm::StringMap<bool> &Features, 1986 StringRef Name, bool Enabled) const override { 1987 setFeatureEnabledImpl(Features, Name, Enabled); 1988 } 1989 // This exists purely to cut down on the number of virtual calls in 1990 // getDefaultFeatures which calls this repeatedly. 1991 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1992 StringRef Name, bool Enabled); 1993 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 1994 bool hasFeature(StringRef Feature) const override; 1995 bool handleTargetFeatures(std::vector<std::string> &Features, 1996 DiagnosticsEngine &Diags) override; 1997 StringRef getABI() const override { 1998 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1999 return "avx"; 2000 else if (getTriple().getArch() == llvm::Triple::x86 && 2001 MMX3DNowLevel == NoMMX3DNow) 2002 return "no-mmx"; 2003 return ""; 2004 } 2005 bool setCPU(const std::string &Name) override { 2006 CPU = llvm::StringSwitch<CPUKind>(Name) 2007 .Case("i386", CK_i386) 2008 .Case("i486", CK_i486) 2009 .Case("winchip-c6", CK_WinChipC6) 2010 .Case("winchip2", CK_WinChip2) 2011 .Case("c3", CK_C3) 2012 .Case("i586", CK_i586) 2013 .Case("pentium", CK_Pentium) 2014 .Case("pentium-mmx", CK_PentiumMMX) 2015 .Case("i686", CK_i686) 2016 .Case("pentiumpro", CK_PentiumPro) 2017 .Case("pentium2", CK_Pentium2) 2018 .Case("pentium3", CK_Pentium3) 2019 .Case("pentium3m", CK_Pentium3M) 2020 .Case("pentium-m", CK_PentiumM) 2021 .Case("c3-2", CK_C3_2) 2022 .Case("yonah", CK_Yonah) 2023 .Case("pentium4", CK_Pentium4) 2024 .Case("pentium4m", CK_Pentium4M) 2025 .Case("prescott", CK_Prescott) 2026 .Case("nocona", CK_Nocona) 2027 .Case("core2", CK_Core2) 2028 .Case("penryn", CK_Penryn) 2029 .Case("atom", CK_Atom) 2030 .Case("slm", CK_Silvermont) 2031 .Case("corei7", CK_Corei7) 2032 .Case("corei7-avx", CK_Corei7AVX) 2033 .Case("core-avx-i", CK_CoreAVXi) 2034 .Case("core-avx2", CK_CoreAVX2) 2035 .Case("broadwell", CK_Broadwell) 2036 .Case("knl", CK_KNL) 2037 .Case("skx", CK_SKX) 2038 .Case("k6", CK_K6) 2039 .Case("k6-2", CK_K6_2) 2040 .Case("k6-3", CK_K6_3) 2041 .Case("athlon", CK_Athlon) 2042 .Case("athlon-tbird", CK_AthlonThunderbird) 2043 .Case("athlon-4", CK_Athlon4) 2044 .Case("athlon-xp", CK_AthlonXP) 2045 .Case("athlon-mp", CK_AthlonMP) 2046 .Case("athlon64", CK_Athlon64) 2047 .Case("athlon64-sse3", CK_Athlon64SSE3) 2048 .Case("athlon-fx", CK_AthlonFX) 2049 .Case("k8", CK_K8) 2050 .Case("k8-sse3", CK_K8SSE3) 2051 .Case("opteron", CK_Opteron) 2052 .Case("opteron-sse3", CK_OpteronSSE3) 2053 .Case("amdfam10", CK_AMDFAM10) 2054 .Case("btver1", CK_BTVER1) 2055 .Case("btver2", CK_BTVER2) 2056 .Case("bdver1", CK_BDVER1) 2057 .Case("bdver2", CK_BDVER2) 2058 .Case("bdver3", CK_BDVER3) 2059 .Case("bdver4", CK_BDVER4) 2060 .Case("x86-64", CK_x86_64) 2061 .Case("geode", CK_Geode) 2062 .Default(CK_Generic); 2063 2064 // Perform any per-CPU checks necessary to determine if this CPU is 2065 // acceptable. 2066 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2067 // invalid without explaining *why*. 2068 switch (CPU) { 2069 case CK_Generic: 2070 // No processor selected! 2071 return false; 2072 2073 case CK_i386: 2074 case CK_i486: 2075 case CK_WinChipC6: 2076 case CK_WinChip2: 2077 case CK_C3: 2078 case CK_i586: 2079 case CK_Pentium: 2080 case CK_PentiumMMX: 2081 case CK_i686: 2082 case CK_PentiumPro: 2083 case CK_Pentium2: 2084 case CK_Pentium3: 2085 case CK_Pentium3M: 2086 case CK_PentiumM: 2087 case CK_Yonah: 2088 case CK_C3_2: 2089 case CK_Pentium4: 2090 case CK_Pentium4M: 2091 case CK_Prescott: 2092 case CK_K6: 2093 case CK_K6_2: 2094 case CK_K6_3: 2095 case CK_Athlon: 2096 case CK_AthlonThunderbird: 2097 case CK_Athlon4: 2098 case CK_AthlonXP: 2099 case CK_AthlonMP: 2100 case CK_Geode: 2101 // Only accept certain architectures when compiling in 32-bit mode. 2102 if (getTriple().getArch() != llvm::Triple::x86) 2103 return false; 2104 2105 // Fallthrough 2106 case CK_Nocona: 2107 case CK_Core2: 2108 case CK_Penryn: 2109 case CK_Atom: 2110 case CK_Silvermont: 2111 case CK_Corei7: 2112 case CK_Corei7AVX: 2113 case CK_CoreAVXi: 2114 case CK_CoreAVX2: 2115 case CK_Broadwell: 2116 case CK_KNL: 2117 case CK_SKX: 2118 case CK_Athlon64: 2119 case CK_Athlon64SSE3: 2120 case CK_AthlonFX: 2121 case CK_K8: 2122 case CK_K8SSE3: 2123 case CK_Opteron: 2124 case CK_OpteronSSE3: 2125 case CK_AMDFAM10: 2126 case CK_BTVER1: 2127 case CK_BTVER2: 2128 case CK_BDVER1: 2129 case CK_BDVER2: 2130 case CK_BDVER3: 2131 case CK_BDVER4: 2132 case CK_x86_64: 2133 return true; 2134 } 2135 llvm_unreachable("Unhandled CPU kind"); 2136 } 2137 2138 bool setFPMath(StringRef Name) override; 2139 2140 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2141 // We accept all non-ARM calling conventions 2142 return (CC == CC_X86ThisCall || 2143 CC == CC_X86FastCall || 2144 CC == CC_X86StdCall || 2145 CC == CC_X86VectorCall || 2146 CC == CC_C || 2147 CC == CC_X86Pascal || 2148 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2149 } 2150 2151 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2152 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2153 } 2154 }; 2155 2156 bool X86TargetInfo::setFPMath(StringRef Name) { 2157 if (Name == "387") { 2158 FPMath = FP_387; 2159 return true; 2160 } 2161 if (Name == "sse") { 2162 FPMath = FP_SSE; 2163 return true; 2164 } 2165 return false; 2166 } 2167 2168 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2169 // FIXME: This *really* should not be here. 2170 2171 // X86_64 always has SSE2. 2172 if (getTriple().getArch() == llvm::Triple::x86_64) 2173 setFeatureEnabledImpl(Features, "sse2", true); 2174 2175 switch (CPU) { 2176 case CK_Generic: 2177 case CK_i386: 2178 case CK_i486: 2179 case CK_i586: 2180 case CK_Pentium: 2181 case CK_i686: 2182 case CK_PentiumPro: 2183 break; 2184 case CK_PentiumMMX: 2185 case CK_Pentium2: 2186 case CK_K6: 2187 case CK_WinChipC6: 2188 setFeatureEnabledImpl(Features, "mmx", true); 2189 break; 2190 case CK_Pentium3: 2191 case CK_Pentium3M: 2192 case CK_C3_2: 2193 setFeatureEnabledImpl(Features, "sse", true); 2194 break; 2195 case CK_PentiumM: 2196 case CK_Pentium4: 2197 case CK_Pentium4M: 2198 case CK_x86_64: 2199 setFeatureEnabledImpl(Features, "sse2", true); 2200 break; 2201 case CK_Yonah: 2202 case CK_Prescott: 2203 case CK_Nocona: 2204 setFeatureEnabledImpl(Features, "sse3", true); 2205 setFeatureEnabledImpl(Features, "cx16", true); 2206 break; 2207 case CK_Core2: 2208 case CK_Atom: 2209 setFeatureEnabledImpl(Features, "ssse3", true); 2210 setFeatureEnabledImpl(Features, "cx16", true); 2211 break; 2212 case CK_Penryn: 2213 setFeatureEnabledImpl(Features, "sse4.1", true); 2214 setFeatureEnabledImpl(Features, "cx16", true); 2215 break; 2216 case CK_SKX: 2217 setFeatureEnabledImpl(Features, "avx512f", true); 2218 setFeatureEnabledImpl(Features, "avx512cd", true); 2219 setFeatureEnabledImpl(Features, "avx512dq", true); 2220 setFeatureEnabledImpl(Features, "avx512bw", true); 2221 setFeatureEnabledImpl(Features, "avx512vl", true); 2222 // FALLTHROUGH 2223 case CK_Broadwell: 2224 setFeatureEnabledImpl(Features, "rdseed", true); 2225 setFeatureEnabledImpl(Features, "adx", true); 2226 // FALLTHROUGH 2227 case CK_CoreAVX2: 2228 setFeatureEnabledImpl(Features, "avx2", true); 2229 setFeatureEnabledImpl(Features, "lzcnt", true); 2230 setFeatureEnabledImpl(Features, "bmi", true); 2231 setFeatureEnabledImpl(Features, "bmi2", true); 2232 setFeatureEnabledImpl(Features, "rtm", true); 2233 setFeatureEnabledImpl(Features, "fma", true); 2234 // FALLTHROUGH 2235 case CK_CoreAVXi: 2236 setFeatureEnabledImpl(Features, "rdrnd", true); 2237 setFeatureEnabledImpl(Features, "f16c", true); 2238 setFeatureEnabledImpl(Features, "fsgsbase", true); 2239 // FALLTHROUGH 2240 case CK_Corei7AVX: 2241 setFeatureEnabledImpl(Features, "avx", true); 2242 // FALLTHROUGH 2243 case CK_Silvermont: 2244 setFeatureEnabledImpl(Features, "aes", true); 2245 setFeatureEnabledImpl(Features, "pclmul", true); 2246 // FALLTHROUGH 2247 case CK_Corei7: 2248 setFeatureEnabledImpl(Features, "sse4.2", true); 2249 setFeatureEnabledImpl(Features, "cx16", true); 2250 break; 2251 case CK_KNL: 2252 setFeatureEnabledImpl(Features, "avx512f", true); 2253 setFeatureEnabledImpl(Features, "avx512cd", true); 2254 setFeatureEnabledImpl(Features, "avx512er", true); 2255 setFeatureEnabledImpl(Features, "avx512pf", true); 2256 setFeatureEnabledImpl(Features, "rdseed", true); 2257 setFeatureEnabledImpl(Features, "adx", true); 2258 setFeatureEnabledImpl(Features, "lzcnt", true); 2259 setFeatureEnabledImpl(Features, "bmi", true); 2260 setFeatureEnabledImpl(Features, "bmi2", true); 2261 setFeatureEnabledImpl(Features, "rtm", true); 2262 setFeatureEnabledImpl(Features, "fma", true); 2263 setFeatureEnabledImpl(Features, "rdrnd", true); 2264 setFeatureEnabledImpl(Features, "f16c", true); 2265 setFeatureEnabledImpl(Features, "fsgsbase", true); 2266 setFeatureEnabledImpl(Features, "aes", true); 2267 setFeatureEnabledImpl(Features, "pclmul", true); 2268 setFeatureEnabledImpl(Features, "cx16", true); 2269 break; 2270 case CK_K6_2: 2271 case CK_K6_3: 2272 case CK_WinChip2: 2273 case CK_C3: 2274 setFeatureEnabledImpl(Features, "3dnow", true); 2275 break; 2276 case CK_Athlon: 2277 case CK_AthlonThunderbird: 2278 case CK_Geode: 2279 setFeatureEnabledImpl(Features, "3dnowa", true); 2280 break; 2281 case CK_Athlon4: 2282 case CK_AthlonXP: 2283 case CK_AthlonMP: 2284 setFeatureEnabledImpl(Features, "sse", true); 2285 setFeatureEnabledImpl(Features, "3dnowa", true); 2286 break; 2287 case CK_K8: 2288 case CK_Opteron: 2289 case CK_Athlon64: 2290 case CK_AthlonFX: 2291 setFeatureEnabledImpl(Features, "sse2", true); 2292 setFeatureEnabledImpl(Features, "3dnowa", true); 2293 break; 2294 case CK_AMDFAM10: 2295 setFeatureEnabledImpl(Features, "sse4a", true); 2296 setFeatureEnabledImpl(Features, "lzcnt", true); 2297 setFeatureEnabledImpl(Features, "popcnt", true); 2298 // FALLTHROUGH 2299 case CK_K8SSE3: 2300 case CK_OpteronSSE3: 2301 case CK_Athlon64SSE3: 2302 setFeatureEnabledImpl(Features, "sse3", true); 2303 setFeatureEnabledImpl(Features, "3dnowa", true); 2304 break; 2305 case CK_BTVER2: 2306 setFeatureEnabledImpl(Features, "avx", true); 2307 setFeatureEnabledImpl(Features, "aes", true); 2308 setFeatureEnabledImpl(Features, "pclmul", true); 2309 setFeatureEnabledImpl(Features, "bmi", true); 2310 setFeatureEnabledImpl(Features, "f16c", true); 2311 // FALLTHROUGH 2312 case CK_BTVER1: 2313 setFeatureEnabledImpl(Features, "ssse3", true); 2314 setFeatureEnabledImpl(Features, "sse4a", true); 2315 setFeatureEnabledImpl(Features, "lzcnt", true); 2316 setFeatureEnabledImpl(Features, "popcnt", true); 2317 setFeatureEnabledImpl(Features, "prfchw", true); 2318 setFeatureEnabledImpl(Features, "cx16", true); 2319 break; 2320 case CK_BDVER4: 2321 setFeatureEnabledImpl(Features, "avx2", true); 2322 setFeatureEnabledImpl(Features, "bmi2", true); 2323 // FALLTHROUGH 2324 case CK_BDVER3: 2325 setFeatureEnabledImpl(Features, "fsgsbase", true); 2326 // FALLTHROUGH 2327 case CK_BDVER2: 2328 setFeatureEnabledImpl(Features, "bmi", true); 2329 setFeatureEnabledImpl(Features, "fma", true); 2330 setFeatureEnabledImpl(Features, "f16c", true); 2331 setFeatureEnabledImpl(Features, "tbm", true); 2332 // FALLTHROUGH 2333 case CK_BDVER1: 2334 // xop implies avx, sse4a and fma4. 2335 setFeatureEnabledImpl(Features, "xop", true); 2336 setFeatureEnabledImpl(Features, "lzcnt", true); 2337 setFeatureEnabledImpl(Features, "aes", true); 2338 setFeatureEnabledImpl(Features, "pclmul", true); 2339 setFeatureEnabledImpl(Features, "prfchw", true); 2340 setFeatureEnabledImpl(Features, "cx16", true); 2341 break; 2342 } 2343 } 2344 2345 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2346 X86SSEEnum Level, bool Enabled) { 2347 if (Enabled) { 2348 switch (Level) { 2349 case AVX512F: 2350 Features["avx512f"] = true; 2351 case AVX2: 2352 Features["avx2"] = true; 2353 case AVX: 2354 Features["avx"] = true; 2355 case SSE42: 2356 Features["sse4.2"] = true; 2357 case SSE41: 2358 Features["sse4.1"] = true; 2359 case SSSE3: 2360 Features["ssse3"] = true; 2361 case SSE3: 2362 Features["sse3"] = true; 2363 case SSE2: 2364 Features["sse2"] = true; 2365 case SSE1: 2366 Features["sse"] = true; 2367 case NoSSE: 2368 break; 2369 } 2370 return; 2371 } 2372 2373 switch (Level) { 2374 case NoSSE: 2375 case SSE1: 2376 Features["sse"] = false; 2377 case SSE2: 2378 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2379 Features["sha"] = false; 2380 case SSE3: 2381 Features["sse3"] = false; 2382 setXOPLevel(Features, NoXOP, false); 2383 case SSSE3: 2384 Features["ssse3"] = false; 2385 case SSE41: 2386 Features["sse4.1"] = false; 2387 case SSE42: 2388 Features["sse4.2"] = false; 2389 case AVX: 2390 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2391 setXOPLevel(Features, FMA4, false); 2392 case AVX2: 2393 Features["avx2"] = false; 2394 case AVX512F: 2395 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2396 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2397 Features["avx512vl"] = false; 2398 } 2399 } 2400 2401 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2402 MMX3DNowEnum Level, bool Enabled) { 2403 if (Enabled) { 2404 switch (Level) { 2405 case AMD3DNowAthlon: 2406 Features["3dnowa"] = true; 2407 case AMD3DNow: 2408 Features["3dnow"] = true; 2409 case MMX: 2410 Features["mmx"] = true; 2411 case NoMMX3DNow: 2412 break; 2413 } 2414 return; 2415 } 2416 2417 switch (Level) { 2418 case NoMMX3DNow: 2419 case MMX: 2420 Features["mmx"] = false; 2421 case AMD3DNow: 2422 Features["3dnow"] = false; 2423 case AMD3DNowAthlon: 2424 Features["3dnowa"] = false; 2425 } 2426 } 2427 2428 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2429 bool Enabled) { 2430 if (Enabled) { 2431 switch (Level) { 2432 case XOP: 2433 Features["xop"] = true; 2434 case FMA4: 2435 Features["fma4"] = true; 2436 setSSELevel(Features, AVX, true); 2437 case SSE4A: 2438 Features["sse4a"] = true; 2439 setSSELevel(Features, SSE3, true); 2440 case NoXOP: 2441 break; 2442 } 2443 return; 2444 } 2445 2446 switch (Level) { 2447 case NoXOP: 2448 case SSE4A: 2449 Features["sse4a"] = false; 2450 case FMA4: 2451 Features["fma4"] = false; 2452 case XOP: 2453 Features["xop"] = false; 2454 } 2455 } 2456 2457 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2458 StringRef Name, bool Enabled) { 2459 // FIXME: This *really* should not be here. We need some way of translating 2460 // options into llvm subtarget features. 2461 if (Name == "sse4") 2462 Name = "sse4.2"; 2463 2464 Features[Name] = Enabled; 2465 2466 if (Name == "mmx") { 2467 setMMXLevel(Features, MMX, Enabled); 2468 } else if (Name == "sse") { 2469 setSSELevel(Features, SSE1, Enabled); 2470 } else if (Name == "sse2") { 2471 setSSELevel(Features, SSE2, Enabled); 2472 } else if (Name == "sse3") { 2473 setSSELevel(Features, SSE3, Enabled); 2474 } else if (Name == "ssse3") { 2475 setSSELevel(Features, SSSE3, Enabled); 2476 } else if (Name == "sse4.2") { 2477 setSSELevel(Features, SSE42, Enabled); 2478 } else if (Name == "sse4.1") { 2479 setSSELevel(Features, SSE41, Enabled); 2480 } else if (Name == "3dnow") { 2481 setMMXLevel(Features, AMD3DNow, Enabled); 2482 } else if (Name == "3dnowa") { 2483 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2484 } else if (Name == "aes") { 2485 if (Enabled) 2486 setSSELevel(Features, SSE2, Enabled); 2487 } else if (Name == "pclmul") { 2488 if (Enabled) 2489 setSSELevel(Features, SSE2, Enabled); 2490 } else if (Name == "avx") { 2491 setSSELevel(Features, AVX, Enabled); 2492 } else if (Name == "avx2") { 2493 setSSELevel(Features, AVX2, Enabled); 2494 } else if (Name == "avx512f") { 2495 setSSELevel(Features, AVX512F, Enabled); 2496 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2497 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2498 if (Enabled) 2499 setSSELevel(Features, AVX512F, Enabled); 2500 } else if (Name == "fma") { 2501 if (Enabled) 2502 setSSELevel(Features, AVX, Enabled); 2503 } else if (Name == "fma4") { 2504 setXOPLevel(Features, FMA4, Enabled); 2505 } else if (Name == "xop") { 2506 setXOPLevel(Features, XOP, Enabled); 2507 } else if (Name == "sse4a") { 2508 setXOPLevel(Features, SSE4A, Enabled); 2509 } else if (Name == "f16c") { 2510 if (Enabled) 2511 setSSELevel(Features, AVX, Enabled); 2512 } else if (Name == "sha") { 2513 if (Enabled) 2514 setSSELevel(Features, SSE2, Enabled); 2515 } 2516 } 2517 2518 /// handleTargetFeatures - Perform initialization based on the user 2519 /// configured set of features. 2520 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2521 DiagnosticsEngine &Diags) { 2522 // Remember the maximum enabled sselevel. 2523 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2524 // Ignore disabled features. 2525 if (Features[i][0] == '-') 2526 continue; 2527 2528 StringRef Feature = StringRef(Features[i]).substr(1); 2529 2530 if (Feature == "aes") { 2531 HasAES = true; 2532 continue; 2533 } 2534 2535 if (Feature == "pclmul") { 2536 HasPCLMUL = true; 2537 continue; 2538 } 2539 2540 if (Feature == "lzcnt") { 2541 HasLZCNT = true; 2542 continue; 2543 } 2544 2545 if (Feature == "rdrnd") { 2546 HasRDRND = true; 2547 continue; 2548 } 2549 2550 if (Feature == "fsgsbase") { 2551 HasFSGSBASE = true; 2552 continue; 2553 } 2554 2555 if (Feature == "bmi") { 2556 HasBMI = true; 2557 continue; 2558 } 2559 2560 if (Feature == "bmi2") { 2561 HasBMI2 = true; 2562 continue; 2563 } 2564 2565 if (Feature == "popcnt") { 2566 HasPOPCNT = true; 2567 continue; 2568 } 2569 2570 if (Feature == "rtm") { 2571 HasRTM = true; 2572 continue; 2573 } 2574 2575 if (Feature == "prfchw") { 2576 HasPRFCHW = true; 2577 continue; 2578 } 2579 2580 if (Feature == "rdseed") { 2581 HasRDSEED = true; 2582 continue; 2583 } 2584 2585 if (Feature == "adx") { 2586 HasADX = true; 2587 continue; 2588 } 2589 2590 if (Feature == "tbm") { 2591 HasTBM = true; 2592 continue; 2593 } 2594 2595 if (Feature == "fma") { 2596 HasFMA = true; 2597 continue; 2598 } 2599 2600 if (Feature == "f16c") { 2601 HasF16C = true; 2602 continue; 2603 } 2604 2605 if (Feature == "avx512cd") { 2606 HasAVX512CD = true; 2607 continue; 2608 } 2609 2610 if (Feature == "avx512er") { 2611 HasAVX512ER = true; 2612 continue; 2613 } 2614 2615 if (Feature == "avx512pf") { 2616 HasAVX512PF = true; 2617 continue; 2618 } 2619 2620 if (Feature == "avx512dq") { 2621 HasAVX512DQ = true; 2622 continue; 2623 } 2624 2625 if (Feature == "avx512bw") { 2626 HasAVX512BW = true; 2627 continue; 2628 } 2629 2630 if (Feature == "avx512vl") { 2631 HasAVX512VL = true; 2632 continue; 2633 } 2634 2635 if (Feature == "sha") { 2636 HasSHA = true; 2637 continue; 2638 } 2639 2640 if (Feature == "cx16") { 2641 HasCX16 = true; 2642 continue; 2643 } 2644 2645 assert(Features[i][0] == '+' && "Invalid target feature!"); 2646 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2647 .Case("avx512f", AVX512F) 2648 .Case("avx2", AVX2) 2649 .Case("avx", AVX) 2650 .Case("sse4.2", SSE42) 2651 .Case("sse4.1", SSE41) 2652 .Case("ssse3", SSSE3) 2653 .Case("sse3", SSE3) 2654 .Case("sse2", SSE2) 2655 .Case("sse", SSE1) 2656 .Default(NoSSE); 2657 SSELevel = std::max(SSELevel, Level); 2658 2659 MMX3DNowEnum ThreeDNowLevel = 2660 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2661 .Case("3dnowa", AMD3DNowAthlon) 2662 .Case("3dnow", AMD3DNow) 2663 .Case("mmx", MMX) 2664 .Default(NoMMX3DNow); 2665 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2666 2667 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2668 .Case("xop", XOP) 2669 .Case("fma4", FMA4) 2670 .Case("sse4a", SSE4A) 2671 .Default(NoXOP); 2672 XOPLevel = std::max(XOPLevel, XLevel); 2673 } 2674 2675 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2676 // Can't do this earlier because we need to be able to explicitly enable 2677 // popcnt and still disable sse4.2. 2678 if (!HasPOPCNT && SSELevel >= SSE42 && 2679 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2680 HasPOPCNT = true; 2681 Features.push_back("+popcnt"); 2682 } 2683 2684 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2685 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2686 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2687 HasPRFCHW = true; 2688 Features.push_back("+prfchw"); 2689 } 2690 2691 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2692 // matches the selected sse level. 2693 if (FPMath == FP_SSE && SSELevel < SSE1) { 2694 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2695 return false; 2696 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2697 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2698 return false; 2699 } 2700 2701 // Don't tell the backend if we're turning off mmx; it will end up disabling 2702 // SSE, which we don't want. 2703 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2704 // then enable MMX. 2705 std::vector<std::string>::iterator it; 2706 it = std::find(Features.begin(), Features.end(), "-mmx"); 2707 if (it != Features.end()) 2708 Features.erase(it); 2709 else if (SSELevel > NoSSE) 2710 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2711 return true; 2712 } 2713 2714 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2715 /// definitions for this particular subtarget. 2716 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2717 MacroBuilder &Builder) const { 2718 // Target identification. 2719 if (getTriple().getArch() == llvm::Triple::x86_64) { 2720 Builder.defineMacro("__amd64__"); 2721 Builder.defineMacro("__amd64"); 2722 Builder.defineMacro("__x86_64"); 2723 Builder.defineMacro("__x86_64__"); 2724 if (getTriple().getArchName() == "x86_64h") { 2725 Builder.defineMacro("__x86_64h"); 2726 Builder.defineMacro("__x86_64h__"); 2727 } 2728 } else { 2729 DefineStd(Builder, "i386", Opts); 2730 } 2731 2732 // Subtarget options. 2733 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2734 // truly should be based on -mtune options. 2735 switch (CPU) { 2736 case CK_Generic: 2737 break; 2738 case CK_i386: 2739 // The rest are coming from the i386 define above. 2740 Builder.defineMacro("__tune_i386__"); 2741 break; 2742 case CK_i486: 2743 case CK_WinChipC6: 2744 case CK_WinChip2: 2745 case CK_C3: 2746 defineCPUMacros(Builder, "i486"); 2747 break; 2748 case CK_PentiumMMX: 2749 Builder.defineMacro("__pentium_mmx__"); 2750 Builder.defineMacro("__tune_pentium_mmx__"); 2751 // Fallthrough 2752 case CK_i586: 2753 case CK_Pentium: 2754 defineCPUMacros(Builder, "i586"); 2755 defineCPUMacros(Builder, "pentium"); 2756 break; 2757 case CK_Pentium3: 2758 case CK_Pentium3M: 2759 case CK_PentiumM: 2760 Builder.defineMacro("__tune_pentium3__"); 2761 // Fallthrough 2762 case CK_Pentium2: 2763 case CK_C3_2: 2764 Builder.defineMacro("__tune_pentium2__"); 2765 // Fallthrough 2766 case CK_PentiumPro: 2767 Builder.defineMacro("__tune_i686__"); 2768 Builder.defineMacro("__tune_pentiumpro__"); 2769 // Fallthrough 2770 case CK_i686: 2771 Builder.defineMacro("__i686"); 2772 Builder.defineMacro("__i686__"); 2773 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2774 Builder.defineMacro("__pentiumpro"); 2775 Builder.defineMacro("__pentiumpro__"); 2776 break; 2777 case CK_Pentium4: 2778 case CK_Pentium4M: 2779 defineCPUMacros(Builder, "pentium4"); 2780 break; 2781 case CK_Yonah: 2782 case CK_Prescott: 2783 case CK_Nocona: 2784 defineCPUMacros(Builder, "nocona"); 2785 break; 2786 case CK_Core2: 2787 case CK_Penryn: 2788 defineCPUMacros(Builder, "core2"); 2789 break; 2790 case CK_Atom: 2791 defineCPUMacros(Builder, "atom"); 2792 break; 2793 case CK_Silvermont: 2794 defineCPUMacros(Builder, "slm"); 2795 break; 2796 case CK_Corei7: 2797 case CK_Corei7AVX: 2798 case CK_CoreAVXi: 2799 case CK_CoreAVX2: 2800 case CK_Broadwell: 2801 defineCPUMacros(Builder, "corei7"); 2802 break; 2803 case CK_KNL: 2804 defineCPUMacros(Builder, "knl"); 2805 break; 2806 case CK_SKX: 2807 defineCPUMacros(Builder, "skx"); 2808 break; 2809 case CK_K6_2: 2810 Builder.defineMacro("__k6_2__"); 2811 Builder.defineMacro("__tune_k6_2__"); 2812 // Fallthrough 2813 case CK_K6_3: 2814 if (CPU != CK_K6_2) { // In case of fallthrough 2815 // FIXME: GCC may be enabling these in cases where some other k6 2816 // architecture is specified but -m3dnow is explicitly provided. The 2817 // exact semantics need to be determined and emulated here. 2818 Builder.defineMacro("__k6_3__"); 2819 Builder.defineMacro("__tune_k6_3__"); 2820 } 2821 // Fallthrough 2822 case CK_K6: 2823 defineCPUMacros(Builder, "k6"); 2824 break; 2825 case CK_Athlon: 2826 case CK_AthlonThunderbird: 2827 case CK_Athlon4: 2828 case CK_AthlonXP: 2829 case CK_AthlonMP: 2830 defineCPUMacros(Builder, "athlon"); 2831 if (SSELevel != NoSSE) { 2832 Builder.defineMacro("__athlon_sse__"); 2833 Builder.defineMacro("__tune_athlon_sse__"); 2834 } 2835 break; 2836 case CK_K8: 2837 case CK_K8SSE3: 2838 case CK_x86_64: 2839 case CK_Opteron: 2840 case CK_OpteronSSE3: 2841 case CK_Athlon64: 2842 case CK_Athlon64SSE3: 2843 case CK_AthlonFX: 2844 defineCPUMacros(Builder, "k8"); 2845 break; 2846 case CK_AMDFAM10: 2847 defineCPUMacros(Builder, "amdfam10"); 2848 break; 2849 case CK_BTVER1: 2850 defineCPUMacros(Builder, "btver1"); 2851 break; 2852 case CK_BTVER2: 2853 defineCPUMacros(Builder, "btver2"); 2854 break; 2855 case CK_BDVER1: 2856 defineCPUMacros(Builder, "bdver1"); 2857 break; 2858 case CK_BDVER2: 2859 defineCPUMacros(Builder, "bdver2"); 2860 break; 2861 case CK_BDVER3: 2862 defineCPUMacros(Builder, "bdver3"); 2863 break; 2864 case CK_BDVER4: 2865 defineCPUMacros(Builder, "bdver4"); 2866 break; 2867 case CK_Geode: 2868 defineCPUMacros(Builder, "geode"); 2869 break; 2870 } 2871 2872 // Target properties. 2873 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2874 2875 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2876 // functions in glibc header files that use FP Stack inline asm which the 2877 // backend can't deal with (PR879). 2878 Builder.defineMacro("__NO_MATH_INLINES"); 2879 2880 if (HasAES) 2881 Builder.defineMacro("__AES__"); 2882 2883 if (HasPCLMUL) 2884 Builder.defineMacro("__PCLMUL__"); 2885 2886 if (HasLZCNT) 2887 Builder.defineMacro("__LZCNT__"); 2888 2889 if (HasRDRND) 2890 Builder.defineMacro("__RDRND__"); 2891 2892 if (HasFSGSBASE) 2893 Builder.defineMacro("__FSGSBASE__"); 2894 2895 if (HasBMI) 2896 Builder.defineMacro("__BMI__"); 2897 2898 if (HasBMI2) 2899 Builder.defineMacro("__BMI2__"); 2900 2901 if (HasPOPCNT) 2902 Builder.defineMacro("__POPCNT__"); 2903 2904 if (HasRTM) 2905 Builder.defineMacro("__RTM__"); 2906 2907 if (HasPRFCHW) 2908 Builder.defineMacro("__PRFCHW__"); 2909 2910 if (HasRDSEED) 2911 Builder.defineMacro("__RDSEED__"); 2912 2913 if (HasADX) 2914 Builder.defineMacro("__ADX__"); 2915 2916 if (HasTBM) 2917 Builder.defineMacro("__TBM__"); 2918 2919 switch (XOPLevel) { 2920 case XOP: 2921 Builder.defineMacro("__XOP__"); 2922 case FMA4: 2923 Builder.defineMacro("__FMA4__"); 2924 case SSE4A: 2925 Builder.defineMacro("__SSE4A__"); 2926 case NoXOP: 2927 break; 2928 } 2929 2930 if (HasFMA) 2931 Builder.defineMacro("__FMA__"); 2932 2933 if (HasF16C) 2934 Builder.defineMacro("__F16C__"); 2935 2936 if (HasAVX512CD) 2937 Builder.defineMacro("__AVX512CD__"); 2938 if (HasAVX512ER) 2939 Builder.defineMacro("__AVX512ER__"); 2940 if (HasAVX512PF) 2941 Builder.defineMacro("__AVX512PF__"); 2942 if (HasAVX512DQ) 2943 Builder.defineMacro("__AVX512DQ__"); 2944 if (HasAVX512BW) 2945 Builder.defineMacro("__AVX512BW__"); 2946 if (HasAVX512VL) 2947 Builder.defineMacro("__AVX512VL__"); 2948 2949 if (HasSHA) 2950 Builder.defineMacro("__SHA__"); 2951 2952 if (HasCX16) 2953 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2954 2955 // Each case falls through to the previous one here. 2956 switch (SSELevel) { 2957 case AVX512F: 2958 Builder.defineMacro("__AVX512F__"); 2959 case AVX2: 2960 Builder.defineMacro("__AVX2__"); 2961 case AVX: 2962 Builder.defineMacro("__AVX__"); 2963 case SSE42: 2964 Builder.defineMacro("__SSE4_2__"); 2965 case SSE41: 2966 Builder.defineMacro("__SSE4_1__"); 2967 case SSSE3: 2968 Builder.defineMacro("__SSSE3__"); 2969 case SSE3: 2970 Builder.defineMacro("__SSE3__"); 2971 case SSE2: 2972 Builder.defineMacro("__SSE2__"); 2973 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2974 case SSE1: 2975 Builder.defineMacro("__SSE__"); 2976 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2977 case NoSSE: 2978 break; 2979 } 2980 2981 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2982 switch (SSELevel) { 2983 case AVX512F: 2984 case AVX2: 2985 case AVX: 2986 case SSE42: 2987 case SSE41: 2988 case SSSE3: 2989 case SSE3: 2990 case SSE2: 2991 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2992 break; 2993 case SSE1: 2994 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2995 break; 2996 default: 2997 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2998 } 2999 } 3000 3001 // Each case falls through to the previous one here. 3002 switch (MMX3DNowLevel) { 3003 case AMD3DNowAthlon: 3004 Builder.defineMacro("__3dNOW_A__"); 3005 case AMD3DNow: 3006 Builder.defineMacro("__3dNOW__"); 3007 case MMX: 3008 Builder.defineMacro("__MMX__"); 3009 case NoMMX3DNow: 3010 break; 3011 } 3012 3013 if (CPU >= CK_i486) { 3014 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3015 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3016 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3017 } 3018 if (CPU >= CK_i586) 3019 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3020 } 3021 3022 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3023 return llvm::StringSwitch<bool>(Feature) 3024 .Case("aes", HasAES) 3025 .Case("avx", SSELevel >= AVX) 3026 .Case("avx2", SSELevel >= AVX2) 3027 .Case("avx512f", SSELevel >= AVX512F) 3028 .Case("avx512cd", HasAVX512CD) 3029 .Case("avx512er", HasAVX512ER) 3030 .Case("avx512pf", HasAVX512PF) 3031 .Case("avx512dq", HasAVX512DQ) 3032 .Case("avx512bw", HasAVX512BW) 3033 .Case("avx512vl", HasAVX512VL) 3034 .Case("bmi", HasBMI) 3035 .Case("bmi2", HasBMI2) 3036 .Case("cx16", HasCX16) 3037 .Case("f16c", HasF16C) 3038 .Case("fma", HasFMA) 3039 .Case("fma4", XOPLevel >= FMA4) 3040 .Case("fsgsbase", HasFSGSBASE) 3041 .Case("lzcnt", HasLZCNT) 3042 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3043 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3044 .Case("mmx", MMX3DNowLevel >= MMX) 3045 .Case("pclmul", HasPCLMUL) 3046 .Case("popcnt", HasPOPCNT) 3047 .Case("prfchw", HasPRFCHW) 3048 .Case("rdrnd", HasRDRND) 3049 .Case("rdseed", HasRDSEED) 3050 .Case("rtm", HasRTM) 3051 .Case("sha", HasSHA) 3052 .Case("sse", SSELevel >= SSE1) 3053 .Case("sse2", SSELevel >= SSE2) 3054 .Case("sse3", SSELevel >= SSE3) 3055 .Case("ssse3", SSELevel >= SSSE3) 3056 .Case("sse4.1", SSELevel >= SSE41) 3057 .Case("sse4.2", SSELevel >= SSE42) 3058 .Case("sse4a", XOPLevel >= SSE4A) 3059 .Case("tbm", HasTBM) 3060 .Case("x86", true) 3061 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3062 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3063 .Case("xop", XOPLevel >= XOP) 3064 .Default(false); 3065 } 3066 3067 bool 3068 X86TargetInfo::validateAsmConstraint(const char *&Name, 3069 TargetInfo::ConstraintInfo &Info) const { 3070 switch (*Name) { 3071 default: return false; 3072 case 'Y': // first letter of a pair: 3073 switch (*(Name+1)) { 3074 default: return false; 3075 case '0': // First SSE register. 3076 case 't': // Any SSE register, when SSE2 is enabled. 3077 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3078 case 'm': // any MMX register, when inter-unit moves enabled. 3079 break; // falls through to setAllowsRegister. 3080 } 3081 case 'f': // any x87 floating point stack register. 3082 // Constraint 'f' cannot be used for output operands. 3083 if (Info.ConstraintStr[0] == '=') 3084 return false; 3085 3086 Info.setAllowsRegister(); 3087 return true; 3088 case 'a': // eax. 3089 case 'b': // ebx. 3090 case 'c': // ecx. 3091 case 'd': // edx. 3092 case 'S': // esi. 3093 case 'D': // edi. 3094 case 'A': // edx:eax. 3095 case 't': // top of floating point stack. 3096 case 'u': // second from top of floating point stack. 3097 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3098 case 'y': // Any MMX register. 3099 case 'x': // Any SSE register. 3100 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3101 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3102 case 'l': // "Index" registers: any general register that can be used as an 3103 // index in a base+index memory access. 3104 Info.setAllowsRegister(); 3105 return true; 3106 case 'C': // SSE floating point constant. 3107 case 'G': // x87 floating point constant. 3108 case 'e': // 32-bit signed integer constant for use with zero-extending 3109 // x86_64 instructions. 3110 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3111 // x86_64 instructions. 3112 return true; 3113 } 3114 } 3115 3116 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3117 unsigned Size) const { 3118 // Strip off constraint modifiers. 3119 while (Constraint[0] == '=' || 3120 Constraint[0] == '+' || 3121 Constraint[0] == '&') 3122 Constraint = Constraint.substr(1); 3123 3124 return validateOperandSize(Constraint, Size); 3125 } 3126 3127 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3128 unsigned Size) const { 3129 return validateOperandSize(Constraint, Size); 3130 } 3131 3132 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3133 unsigned Size) const { 3134 switch (Constraint[0]) { 3135 default: break; 3136 case 'y': 3137 return Size <= 64; 3138 case 'f': 3139 case 't': 3140 case 'u': 3141 return Size <= 128; 3142 case 'x': 3143 // 256-bit ymm registers can be used if target supports AVX. 3144 return Size <= (SSELevel >= AVX ? 256U : 128U); 3145 } 3146 3147 return true; 3148 } 3149 3150 std::string 3151 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3152 switch (*Constraint) { 3153 case 'a': return std::string("{ax}"); 3154 case 'b': return std::string("{bx}"); 3155 case 'c': return std::string("{cx}"); 3156 case 'd': return std::string("{dx}"); 3157 case 'S': return std::string("{si}"); 3158 case 'D': return std::string("{di}"); 3159 case 'p': // address 3160 return std::string("im"); 3161 case 't': // top of floating point stack. 3162 return std::string("{st}"); 3163 case 'u': // second from top of floating point stack. 3164 return std::string("{st(1)}"); // second from top of floating point stack. 3165 default: 3166 return std::string(1, *Constraint); 3167 } 3168 } 3169 } // end anonymous namespace 3170 3171 namespace { 3172 // X86-32 generic target 3173 class X86_32TargetInfo : public X86TargetInfo { 3174 public: 3175 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3176 DoubleAlign = LongLongAlign = 32; 3177 LongDoubleWidth = 96; 3178 LongDoubleAlign = 32; 3179 SuitableAlign = 128; 3180 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3181 SizeType = UnsignedInt; 3182 PtrDiffType = SignedInt; 3183 IntPtrType = SignedInt; 3184 RegParmMax = 3; 3185 3186 // Use fpret for all types. 3187 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3188 (1 << TargetInfo::Double) | 3189 (1 << TargetInfo::LongDouble)); 3190 3191 // x86-32 has atomics up to 8 bytes 3192 // FIXME: Check that we actually have cmpxchg8b before setting 3193 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3194 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3195 } 3196 BuiltinVaListKind getBuiltinVaListKind() const override { 3197 return TargetInfo::CharPtrBuiltinVaList; 3198 } 3199 3200 int getEHDataRegisterNumber(unsigned RegNo) const override { 3201 if (RegNo == 0) return 0; 3202 if (RegNo == 1) return 2; 3203 return -1; 3204 } 3205 bool validateOperandSize(StringRef Constraint, 3206 unsigned Size) const override { 3207 switch (Constraint[0]) { 3208 default: break; 3209 case 'R': 3210 case 'q': 3211 case 'Q': 3212 case 'a': 3213 case 'b': 3214 case 'c': 3215 case 'd': 3216 case 'S': 3217 case 'D': 3218 return Size <= 32; 3219 case 'A': 3220 return Size <= 64; 3221 } 3222 3223 return X86TargetInfo::validateOperandSize(Constraint, Size); 3224 } 3225 }; 3226 } // end anonymous namespace 3227 3228 namespace { 3229 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3230 public: 3231 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3232 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3233 3234 unsigned getFloatEvalMethod() const override { 3235 unsigned Major, Minor, Micro; 3236 getTriple().getOSVersion(Major, Minor, Micro); 3237 // New NetBSD uses the default rounding mode. 3238 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3239 return X86_32TargetInfo::getFloatEvalMethod(); 3240 // NetBSD before 6.99.26 defaults to "double" rounding. 3241 return 1; 3242 } 3243 }; 3244 } // end anonymous namespace 3245 3246 namespace { 3247 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3248 public: 3249 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3250 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3251 SizeType = UnsignedLong; 3252 IntPtrType = SignedLong; 3253 PtrDiffType = SignedLong; 3254 } 3255 }; 3256 } // end anonymous namespace 3257 3258 namespace { 3259 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3260 public: 3261 BitrigI386TargetInfo(const llvm::Triple &Triple) 3262 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3263 SizeType = UnsignedLong; 3264 IntPtrType = SignedLong; 3265 PtrDiffType = SignedLong; 3266 } 3267 }; 3268 } // end anonymous namespace 3269 3270 namespace { 3271 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3272 public: 3273 DarwinI386TargetInfo(const llvm::Triple &Triple) 3274 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3275 LongDoubleWidth = 128; 3276 LongDoubleAlign = 128; 3277 SuitableAlign = 128; 3278 MaxVectorAlign = 256; 3279 SizeType = UnsignedLong; 3280 IntPtrType = SignedLong; 3281 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3282 HasAlignMac68kSupport = true; 3283 } 3284 3285 }; 3286 } // end anonymous namespace 3287 3288 namespace { 3289 // x86-32 Windows target 3290 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3291 public: 3292 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3293 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3294 WCharType = UnsignedShort; 3295 DoubleAlign = LongLongAlign = 64; 3296 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3297 } 3298 void getTargetDefines(const LangOptions &Opts, 3299 MacroBuilder &Builder) const override { 3300 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3301 } 3302 }; 3303 3304 // x86-32 Windows Visual Studio target 3305 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3306 public: 3307 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3308 : WindowsX86_32TargetInfo(Triple) { 3309 LongDoubleWidth = LongDoubleAlign = 64; 3310 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3311 } 3312 void getTargetDefines(const LangOptions &Opts, 3313 MacroBuilder &Builder) const override { 3314 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3315 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3316 // The value of the following reflects processor type. 3317 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3318 // We lost the original triple, so we use the default. 3319 Builder.defineMacro("_M_IX86", "600"); 3320 } 3321 }; 3322 } // end anonymous namespace 3323 3324 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3325 Builder.defineMacro("__MSVCRT__"); 3326 Builder.defineMacro("__MINGW32__"); 3327 3328 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports 3329 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3330 // macro anyway for pre-processor compatibility. 3331 if (Opts.MicrosoftExt) 3332 Builder.defineMacro("__declspec", "__declspec"); 3333 else 3334 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3335 3336 if (!Opts.MicrosoftExt) { 3337 // Provide macros for all the calling convention keywords. Provide both 3338 // single and double underscore prefixed variants. These are available on 3339 // x64 as well as x86, even though they have no effect. 3340 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3341 for (const char *CC : CCs) { 3342 std::string GCCSpelling = "__attribute__((__"; 3343 GCCSpelling += CC; 3344 GCCSpelling += "__))"; 3345 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3346 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3347 } 3348 } 3349 } 3350 3351 namespace { 3352 // x86-32 MinGW target 3353 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3354 public: 3355 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3356 : WindowsX86_32TargetInfo(Triple) {} 3357 void getTargetDefines(const LangOptions &Opts, 3358 MacroBuilder &Builder) const override { 3359 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3360 DefineStd(Builder, "WIN32", Opts); 3361 DefineStd(Builder, "WINNT", Opts); 3362 Builder.defineMacro("_X86_"); 3363 addMinGWDefines(Opts, Builder); 3364 } 3365 }; 3366 } // end anonymous namespace 3367 3368 namespace { 3369 // x86-32 Cygwin target 3370 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3371 public: 3372 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3373 : X86_32TargetInfo(Triple) { 3374 TLSSupported = false; 3375 WCharType = UnsignedShort; 3376 DoubleAlign = LongLongAlign = 64; 3377 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3378 } 3379 void getTargetDefines(const LangOptions &Opts, 3380 MacroBuilder &Builder) const override { 3381 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3382 Builder.defineMacro("_X86_"); 3383 Builder.defineMacro("__CYGWIN__"); 3384 Builder.defineMacro("__CYGWIN32__"); 3385 DefineStd(Builder, "unix", Opts); 3386 if (Opts.CPlusPlus) 3387 Builder.defineMacro("_GNU_SOURCE"); 3388 } 3389 }; 3390 } // end anonymous namespace 3391 3392 namespace { 3393 // x86-32 Haiku target 3394 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3395 public: 3396 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3397 SizeType = UnsignedLong; 3398 IntPtrType = SignedLong; 3399 PtrDiffType = SignedLong; 3400 ProcessIDType = SignedLong; 3401 this->UserLabelPrefix = ""; 3402 this->TLSSupported = false; 3403 } 3404 void getTargetDefines(const LangOptions &Opts, 3405 MacroBuilder &Builder) const override { 3406 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3407 Builder.defineMacro("__INTEL__"); 3408 Builder.defineMacro("__HAIKU__"); 3409 } 3410 }; 3411 } // end anonymous namespace 3412 3413 // RTEMS Target 3414 template<typename Target> 3415 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3416 protected: 3417 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3418 MacroBuilder &Builder) const override { 3419 // RTEMS defines; list based off of gcc output 3420 3421 Builder.defineMacro("__rtems__"); 3422 Builder.defineMacro("__ELF__"); 3423 } 3424 3425 public: 3426 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3427 this->UserLabelPrefix = ""; 3428 3429 switch (Triple.getArch()) { 3430 default: 3431 case llvm::Triple::x86: 3432 // this->MCountName = ".mcount"; 3433 break; 3434 case llvm::Triple::mips: 3435 case llvm::Triple::mipsel: 3436 case llvm::Triple::ppc: 3437 case llvm::Triple::ppc64: 3438 case llvm::Triple::ppc64le: 3439 // this->MCountName = "_mcount"; 3440 break; 3441 case llvm::Triple::arm: 3442 // this->MCountName = "__mcount"; 3443 break; 3444 } 3445 } 3446 }; 3447 3448 namespace { 3449 // x86-32 RTEMS target 3450 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3451 public: 3452 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3453 SizeType = UnsignedLong; 3454 IntPtrType = SignedLong; 3455 PtrDiffType = SignedLong; 3456 this->UserLabelPrefix = ""; 3457 } 3458 void getTargetDefines(const LangOptions &Opts, 3459 MacroBuilder &Builder) const override { 3460 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3461 Builder.defineMacro("__INTEL__"); 3462 Builder.defineMacro("__rtems__"); 3463 } 3464 }; 3465 } // end anonymous namespace 3466 3467 namespace { 3468 // x86-64 generic target 3469 class X86_64TargetInfo : public X86TargetInfo { 3470 public: 3471 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3472 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3473 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3474 LongDoubleWidth = 128; 3475 LongDoubleAlign = 128; 3476 LargeArrayMinWidth = 128; 3477 LargeArrayAlign = 128; 3478 SuitableAlign = 128; 3479 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3480 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3481 IntPtrType = IsX32 ? SignedInt : SignedLong; 3482 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3483 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3484 RegParmMax = 6; 3485 3486 // Pointers are 32-bit in x32. 3487 DescriptionString = (IsX32) 3488 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3489 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3490 3491 // Use fpret only for long double. 3492 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3493 3494 // Use fp2ret for _Complex long double. 3495 ComplexLongDoubleUsesFP2Ret = true; 3496 3497 // x86-64 has atomics up to 16 bytes. 3498 MaxAtomicPromoteWidth = 128; 3499 MaxAtomicInlineWidth = 128; 3500 } 3501 BuiltinVaListKind getBuiltinVaListKind() const override { 3502 return TargetInfo::X86_64ABIBuiltinVaList; 3503 } 3504 3505 int getEHDataRegisterNumber(unsigned RegNo) const override { 3506 if (RegNo == 0) return 0; 3507 if (RegNo == 1) return 1; 3508 return -1; 3509 } 3510 3511 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3512 return (CC == CC_C || 3513 CC == CC_X86VectorCall || 3514 CC == CC_IntelOclBicc || 3515 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3516 } 3517 3518 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3519 return CC_C; 3520 } 3521 3522 // for x32 we need it here explicitly 3523 bool hasInt128Type() const override { return true; } 3524 }; 3525 } // end anonymous namespace 3526 3527 namespace { 3528 // x86-64 Windows target 3529 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3530 public: 3531 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3532 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3533 WCharType = UnsignedShort; 3534 LongWidth = LongAlign = 32; 3535 DoubleAlign = LongLongAlign = 64; 3536 IntMaxType = SignedLongLong; 3537 Int64Type = SignedLongLong; 3538 SizeType = UnsignedLongLong; 3539 PtrDiffType = SignedLongLong; 3540 IntPtrType = SignedLongLong; 3541 this->UserLabelPrefix = ""; 3542 } 3543 void getTargetDefines(const LangOptions &Opts, 3544 MacroBuilder &Builder) const override { 3545 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3546 Builder.defineMacro("_WIN64"); 3547 } 3548 BuiltinVaListKind getBuiltinVaListKind() const override { 3549 return TargetInfo::CharPtrBuiltinVaList; 3550 } 3551 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3552 return (CC == CC_C || 3553 CC == CC_X86VectorCall || 3554 CC == CC_IntelOclBicc || 3555 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3556 } 3557 }; 3558 } // end anonymous namespace 3559 3560 namespace { 3561 // x86-64 Windows Visual Studio target 3562 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3563 public: 3564 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3565 : WindowsX86_64TargetInfo(Triple) { 3566 LongDoubleWidth = LongDoubleAlign = 64; 3567 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3568 } 3569 void getTargetDefines(const LangOptions &Opts, 3570 MacroBuilder &Builder) const override { 3571 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3572 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3573 Builder.defineMacro("_M_X64"); 3574 Builder.defineMacro("_M_AMD64"); 3575 } 3576 }; 3577 } // end anonymous namespace 3578 3579 namespace { 3580 // x86-64 MinGW target 3581 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3582 public: 3583 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3584 : WindowsX86_64TargetInfo(Triple) {} 3585 void getTargetDefines(const LangOptions &Opts, 3586 MacroBuilder &Builder) const override { 3587 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3588 DefineStd(Builder, "WIN64", Opts); 3589 Builder.defineMacro("__MINGW64__"); 3590 addMinGWDefines(Opts, Builder); 3591 3592 // GCC defines this macro when it is using __gxx_personality_seh0. 3593 if (!Opts.SjLjExceptions) 3594 Builder.defineMacro("__SEH__"); 3595 } 3596 }; 3597 } // end anonymous namespace 3598 3599 namespace { 3600 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3601 public: 3602 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3603 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3604 Int64Type = SignedLongLong; 3605 MaxVectorAlign = 256; 3606 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3607 llvm::Triple T = llvm::Triple(Triple); 3608 if (T.isiOS()) 3609 UseSignedCharForObjCBool = false; 3610 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3611 } 3612 }; 3613 } // end anonymous namespace 3614 3615 namespace { 3616 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3617 public: 3618 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3619 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3620 IntMaxType = SignedLongLong; 3621 Int64Type = SignedLongLong; 3622 } 3623 }; 3624 } // end anonymous namespace 3625 3626 namespace { 3627 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3628 public: 3629 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3630 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3631 IntMaxType = SignedLongLong; 3632 Int64Type = SignedLongLong; 3633 } 3634 }; 3635 } 3636 3637 3638 namespace { 3639 class ARMTargetInfo : public TargetInfo { 3640 // Possible FPU choices. 3641 enum FPUMode { 3642 VFP2FPU = (1 << 0), 3643 VFP3FPU = (1 << 1), 3644 VFP4FPU = (1 << 2), 3645 NeonFPU = (1 << 3), 3646 FPARMV8 = (1 << 4) 3647 }; 3648 3649 // Possible HWDiv features. 3650 enum HWDivMode { 3651 HWDivThumb = (1 << 0), 3652 HWDivARM = (1 << 1) 3653 }; 3654 3655 static bool FPUModeIsVFP(FPUMode Mode) { 3656 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3657 } 3658 3659 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3660 static const char * const GCCRegNames[]; 3661 3662 std::string ABI, CPU; 3663 3664 enum { 3665 FP_Default, 3666 FP_VFP, 3667 FP_Neon 3668 } FPMath; 3669 3670 unsigned FPU : 5; 3671 3672 unsigned IsAAPCS : 1; 3673 unsigned IsThumb : 1; 3674 unsigned HWDiv : 2; 3675 3676 // Initialized via features. 3677 unsigned SoftFloat : 1; 3678 unsigned SoftFloatABI : 1; 3679 3680 unsigned CRC : 1; 3681 unsigned Crypto : 1; 3682 3683 // ACLE 6.5.1 Hardware floating point 3684 enum { 3685 HW_FP_HP = (1 << 1), /// half (16-bit) 3686 HW_FP_SP = (1 << 2), /// single (32-bit) 3687 HW_FP_DP = (1 << 3), /// double (64-bit) 3688 }; 3689 uint32_t HW_FP; 3690 3691 static const Builtin::Info BuiltinInfo[]; 3692 3693 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3694 StringRef ArchName = T.getArchName(); 3695 if (T.getArch() == llvm::Triple::arm || 3696 T.getArch() == llvm::Triple::armeb) { 3697 StringRef VersionStr; 3698 if (ArchName.startswith("armv")) 3699 VersionStr = ArchName.substr(4, 1); 3700 else if (ArchName.startswith("armebv")) 3701 VersionStr = ArchName.substr(6, 1); 3702 else 3703 return false; 3704 unsigned Version; 3705 if (VersionStr.getAsInteger(10, Version)) 3706 return false; 3707 return Version >= 6; 3708 } 3709 assert(T.getArch() == llvm::Triple::thumb || 3710 T.getArch() == llvm::Triple::thumbeb); 3711 StringRef VersionStr; 3712 if (ArchName.startswith("thumbv")) 3713 VersionStr = ArchName.substr(6, 1); 3714 else if (ArchName.startswith("thumbebv")) 3715 VersionStr = ArchName.substr(8, 1); 3716 else 3717 return false; 3718 unsigned Version; 3719 if (VersionStr.getAsInteger(10, Version)) 3720 return false; 3721 return Version >= 7; 3722 } 3723 3724 void setABIAAPCS() { 3725 IsAAPCS = true; 3726 3727 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3728 const llvm::Triple &T = getTriple(); 3729 3730 // size_t is unsigned long on MachO-derived environments and NetBSD. 3731 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD) 3732 SizeType = UnsignedLong; 3733 else 3734 SizeType = UnsignedInt; 3735 3736 switch (T.getOS()) { 3737 case llvm::Triple::NetBSD: 3738 WCharType = SignedInt; 3739 break; 3740 case llvm::Triple::Win32: 3741 WCharType = UnsignedShort; 3742 break; 3743 case llvm::Triple::Linux: 3744 default: 3745 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3746 WCharType = UnsignedInt; 3747 break; 3748 } 3749 3750 UseBitFieldTypeAlignment = true; 3751 3752 ZeroLengthBitfieldBoundary = 0; 3753 3754 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3755 // so set preferred for small types to 32. 3756 if (T.isOSBinFormatMachO()) { 3757 DescriptionString = 3758 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 3759 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 3760 } else if (T.isOSWindows()) { 3761 // FIXME: this is invalid for WindowsCE 3762 assert(!BigEndian && "Windows on ARM does not support big endian"); 3763 DescriptionString = "e" 3764 "-m:e" 3765 "-p:32:32" 3766 "-i64:64" 3767 "-v128:64:128" 3768 "-a:0:32" 3769 "-n32" 3770 "-S64"; 3771 } else { 3772 DescriptionString = 3773 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 3774 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 3775 } 3776 3777 // FIXME: Enumerated types are variable width in straight AAPCS. 3778 } 3779 3780 void setABIAPCS() { 3781 const llvm::Triple &T = getTriple(); 3782 3783 IsAAPCS = false; 3784 3785 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3786 3787 // size_t is unsigned int on FreeBSD. 3788 if (T.getOS() == llvm::Triple::FreeBSD) 3789 SizeType = UnsignedInt; 3790 else 3791 SizeType = UnsignedLong; 3792 3793 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3794 WCharType = SignedInt; 3795 3796 // Do not respect the alignment of bit-field types when laying out 3797 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3798 UseBitFieldTypeAlignment = false; 3799 3800 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3801 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3802 /// gcc. 3803 ZeroLengthBitfieldBoundary = 32; 3804 3805 if (T.isOSBinFormatMachO()) 3806 DescriptionString = 3807 BigEndian 3808 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 3809 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3810 else 3811 DescriptionString = 3812 BigEndian 3813 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 3814 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3815 3816 // FIXME: Override "preferred align" for double and long long. 3817 } 3818 3819 public: 3820 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 3821 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3822 IsAAPCS(true), HW_FP(0) { 3823 BigEndian = IsBigEndian; 3824 3825 switch (getTriple().getOS()) { 3826 case llvm::Triple::NetBSD: 3827 PtrDiffType = SignedLong; 3828 break; 3829 default: 3830 PtrDiffType = SignedInt; 3831 break; 3832 } 3833 3834 // {} in inline assembly are neon specifiers, not assembly variant 3835 // specifiers. 3836 NoAsmVariants = true; 3837 3838 // FIXME: Should we just treat this as a feature? 3839 IsThumb = getTriple().getArchName().startswith("thumb"); 3840 3841 // FIXME: This duplicates code from the driver that sets the -target-abi 3842 // option - this code is used if -target-abi isn't passed and should 3843 // be unified in some way. 3844 if (Triple.isOSBinFormatMachO()) { 3845 // The backend is hardwired to assume AAPCS for M-class processors, ensure 3846 // the frontend matches that. 3847 if (Triple.getEnvironment() == llvm::Triple::EABI || 3848 Triple.getOS() == llvm::Triple::UnknownOS || 3849 StringRef(CPU).startswith("cortex-m")) { 3850 setABI("aapcs"); 3851 } else { 3852 setABI("apcs-gnu"); 3853 } 3854 } else if (Triple.isOSWindows()) { 3855 // FIXME: this is invalid for WindowsCE 3856 setABI("aapcs"); 3857 } else { 3858 // Select the default based on the platform. 3859 switch (Triple.getEnvironment()) { 3860 case llvm::Triple::Android: 3861 case llvm::Triple::GNUEABI: 3862 case llvm::Triple::GNUEABIHF: 3863 setABI("aapcs-linux"); 3864 break; 3865 case llvm::Triple::EABIHF: 3866 case llvm::Triple::EABI: 3867 setABI("aapcs"); 3868 break; 3869 default: 3870 if (Triple.getOS() == llvm::Triple::NetBSD) 3871 setABI("apcs-gnu"); 3872 else 3873 setABI("aapcs"); 3874 break; 3875 } 3876 } 3877 3878 // ARM targets default to using the ARM C++ ABI. 3879 TheCXXABI.set(TargetCXXABI::GenericARM); 3880 3881 // ARM has atomics up to 8 bytes 3882 MaxAtomicPromoteWidth = 64; 3883 if (shouldUseInlineAtomic(getTriple())) 3884 MaxAtomicInlineWidth = 64; 3885 3886 // Do force alignment of members that follow zero length bitfields. If 3887 // the alignment of the zero-length bitfield is greater than the member 3888 // that follows it, `bar', `bar' will be aligned as the type of the 3889 // zero length bitfield. 3890 UseZeroLengthBitfieldAlignment = true; 3891 } 3892 StringRef getABI() const override { return ABI; } 3893 bool setABI(const std::string &Name) override { 3894 ABI = Name; 3895 3896 // The defaults (above) are for AAPCS, check if we need to change them. 3897 // 3898 // FIXME: We need support for -meabi... we could just mangle it into the 3899 // name. 3900 if (Name == "apcs-gnu") { 3901 setABIAPCS(); 3902 return true; 3903 } 3904 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 3905 setABIAAPCS(); 3906 return true; 3907 } 3908 return false; 3909 } 3910 3911 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 3912 if (IsAAPCS) 3913 Features["aapcs"] = true; 3914 else 3915 Features["apcs"] = true; 3916 3917 StringRef ArchName = getTriple().getArchName(); 3918 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3919 Features["vfp2"] = true; 3920 else if (CPU == "cortex-a8" || CPU == "cortex-a9") { 3921 Features["vfp3"] = true; 3922 Features["neon"] = true; 3923 } 3924 else if (CPU == "cortex-a5") { 3925 Features["vfp4"] = true; 3926 Features["neon"] = true; 3927 } else if (CPU == "swift" || CPU == "cortex-a7" || 3928 CPU == "cortex-a12" || CPU == "cortex-a15" || 3929 CPU == "cortex-a17" || CPU == "krait") { 3930 Features["vfp4"] = true; 3931 Features["neon"] = true; 3932 Features["hwdiv"] = true; 3933 Features["hwdiv-arm"] = true; 3934 } else if (CPU == "cyclone") { 3935 Features["v8fp"] = true; 3936 Features["neon"] = true; 3937 Features["hwdiv"] = true; 3938 Features["hwdiv-arm"] = true; 3939 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 3940 Features["fp-armv8"] = true; 3941 Features["neon"] = true; 3942 Features["hwdiv"] = true; 3943 Features["hwdiv-arm"] = true; 3944 Features["crc"] = true; 3945 Features["crypto"] = true; 3946 } else if (CPU == "cortex-r5" || 3947 // Enable the hwdiv extension for all v8a AArch32 cores by 3948 // default. 3949 ArchName == "armv8a" || ArchName == "armv8" || 3950 ArchName == "armebv8a" || ArchName == "armebv8" || 3951 ArchName == "thumbv8a" || ArchName == "thumbv8" || 3952 ArchName == "thumbebv8a" || ArchName == "thumbebv8") { 3953 Features["hwdiv"] = true; 3954 Features["hwdiv-arm"] = true; 3955 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7") { 3956 Features["hwdiv"] = true; 3957 } 3958 } 3959 3960 bool handleTargetFeatures(std::vector<std::string> &Features, 3961 DiagnosticsEngine &Diags) override { 3962 FPU = 0; 3963 CRC = 0; 3964 Crypto = 0; 3965 SoftFloat = SoftFloatABI = false; 3966 HWDiv = 0; 3967 3968 for (const auto &Feature : Features) { 3969 if (Feature == "+soft-float") { 3970 SoftFloat = true; 3971 } else if (Feature == "+soft-float-abi") { 3972 SoftFloatABI = true; 3973 } else if (Feature == "+vfp2") { 3974 FPU |= VFP2FPU; 3975 HW_FP = HW_FP_SP | HW_FP_DP; 3976 } else if (Feature == "+vfp3") { 3977 FPU |= VFP3FPU; 3978 HW_FP = HW_FP_SP | HW_FP_DP; 3979 } else if (Feature == "+vfp4") { 3980 FPU |= VFP4FPU; 3981 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 3982 } else if (Feature == "+fp-armv8") { 3983 FPU |= FPARMV8; 3984 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 3985 } else if (Feature == "+neon") { 3986 FPU |= NeonFPU; 3987 HW_FP = HW_FP_SP | HW_FP_DP; 3988 } else if (Feature == "+hwdiv") { 3989 HWDiv |= HWDivThumb; 3990 } else if (Feature == "+hwdiv-arm") { 3991 HWDiv |= HWDivARM; 3992 } else if (Feature == "+crc") { 3993 CRC = 1; 3994 } else if (Feature == "+crypto") { 3995 Crypto = 1; 3996 } else if (Feature == "+fp-only-sp") { 3997 HW_FP &= ~HW_FP_DP; 3998 } 3999 } 4000 4001 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4002 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4003 return false; 4004 } 4005 4006 if (FPMath == FP_Neon) 4007 Features.push_back("+neonfp"); 4008 else if (FPMath == FP_VFP) 4009 Features.push_back("-neonfp"); 4010 4011 // Remove front-end specific options which the backend handles differently. 4012 const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" }; 4013 for (const auto &FEFeature : FrontEndFeatures) { 4014 auto Feature = std::find(Features.begin(), Features.end(), FEFeature); 4015 if (Feature != Features.end()) 4016 Features.erase(Feature); 4017 } 4018 4019 return true; 4020 } 4021 4022 bool hasFeature(StringRef Feature) const override { 4023 return llvm::StringSwitch<bool>(Feature) 4024 .Case("arm", true) 4025 .Case("softfloat", SoftFloat) 4026 .Case("thumb", IsThumb) 4027 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4028 .Case("hwdiv", HWDiv & HWDivThumb) 4029 .Case("hwdiv-arm", HWDiv & HWDivARM) 4030 .Default(false); 4031 } 4032 // FIXME: Should we actually have some table instead of these switches? 4033 static const char *getCPUDefineSuffix(StringRef Name) { 4034 return llvm::StringSwitch<const char *>(Name) 4035 .Cases("arm8", "arm810", "4") 4036 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", 4037 "4") 4038 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 4039 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 4040 .Case("ep9312", "4T") 4041 .Cases("arm10tdmi", "arm1020t", "5T") 4042 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 4043 .Case("arm926ej-s", "5TEJ") 4044 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 4045 .Cases("xscale", "iwmmxt", "5TE") 4046 .Case("arm1136j-s", "6J") 4047 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 4048 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 4049 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 4050 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A") 4051 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", 4052 "7A") 4053 .Cases("cortex-r4", "cortex-r5", "7R") 4054 .Case("swift", "7S") 4055 .Case("cyclone", "8A") 4056 .Case("cortex-m3", "7M") 4057 .Cases("cortex-m4", "cortex-m7", "7EM") 4058 .Case("cortex-m0", "6M") 4059 .Cases("cortex-a53", "cortex-a57", "8A") 4060 .Default(nullptr); 4061 } 4062 static const char *getCPUProfile(StringRef Name) { 4063 return llvm::StringSwitch<const char *>(Name) 4064 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 4065 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", 4066 "A") 4067 .Cases("cortex-a53", "cortex-a57", "A") 4068 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M") 4069 .Cases("cortex-r4", "cortex-r5", "R") 4070 .Default(""); 4071 } 4072 bool setCPU(const std::string &Name) override { 4073 if (!getCPUDefineSuffix(Name)) 4074 return false; 4075 4076 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4077 StringRef Profile = getCPUProfile(Name); 4078 if (Profile == "M" && MaxAtomicInlineWidth) { 4079 MaxAtomicPromoteWidth = 32; 4080 MaxAtomicInlineWidth = 32; 4081 } 4082 4083 CPU = Name; 4084 return true; 4085 } 4086 bool setFPMath(StringRef Name) override; 4087 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 4088 unsigned CPUArchVer) const { 4089 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 4090 (CPUArch.find('M') != StringRef::npos); 4091 } 4092 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 4093 unsigned CPUArchVer) const { 4094 // We check both CPUArchVer and ArchName because when only triple is 4095 // specified, the default CPU is arm1136j-s. 4096 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 4097 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 4098 } 4099 void getTargetDefines(const LangOptions &Opts, 4100 MacroBuilder &Builder) const override { 4101 // Target identification. 4102 Builder.defineMacro("__arm"); 4103 Builder.defineMacro("__arm__"); 4104 4105 // Target properties. 4106 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4107 4108 StringRef CPUArch = getCPUDefineSuffix(CPU); 4109 unsigned int CPUArchVer; 4110 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) 4111 llvm_unreachable("Invalid char for architecture version number"); 4112 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4113 4114 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4115 StringRef CPUProfile = getCPUProfile(CPU); 4116 StringRef ArchName = getTriple().getArchName(); 4117 4118 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4119 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4120 if (CPUArch[0] >= '8') { 4121 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4122 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4123 } 4124 4125 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4126 // is not defined for the M-profile. 4127 // NOTE that the deffault profile is assumed to be 'A' 4128 if (CPUProfile.empty() || CPUProfile != "M") 4129 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4130 4131 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4132 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4133 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4134 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4135 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4136 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 4137 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4138 4139 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4140 // instruction set such as ARM or Thumb. 4141 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4142 4143 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4144 4145 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4146 if (!CPUProfile.empty()) 4147 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4148 4149 // ACLE 6.5.1 Hardware Floating Point 4150 if (HW_FP) 4151 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4152 4153 // ACLE predefines. 4154 Builder.defineMacro("__ARM_ACLE", "200"); 4155 4156 // Subtarget options. 4157 4158 // FIXME: It's more complicated than this and we don't really support 4159 // interworking. 4160 // Windows on ARM does not "support" interworking 4161 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 4162 Builder.defineMacro("__THUMB_INTERWORK__"); 4163 4164 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4165 // Embedded targets on Darwin follow AAPCS, but not EABI. 4166 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4167 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4168 Builder.defineMacro("__ARM_EABI__"); 4169 Builder.defineMacro("__ARM_PCS", "1"); 4170 4171 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4172 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4173 } 4174 4175 if (SoftFloat) 4176 Builder.defineMacro("__SOFTFP__"); 4177 4178 if (CPU == "xscale") 4179 Builder.defineMacro("__XSCALE__"); 4180 4181 if (IsThumb) { 4182 Builder.defineMacro("__THUMBEL__"); 4183 Builder.defineMacro("__thumb__"); 4184 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4185 Builder.defineMacro("__thumb2__"); 4186 } 4187 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4188 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4189 4190 // Note, this is always on in gcc, even though it doesn't make sense. 4191 Builder.defineMacro("__APCS_32__"); 4192 4193 if (FPUModeIsVFP((FPUMode) FPU)) { 4194 Builder.defineMacro("__VFP_FP__"); 4195 if (FPU & VFP2FPU) 4196 Builder.defineMacro("__ARM_VFPV2__"); 4197 if (FPU & VFP3FPU) 4198 Builder.defineMacro("__ARM_VFPV3__"); 4199 if (FPU & VFP4FPU) 4200 Builder.defineMacro("__ARM_VFPV4__"); 4201 } 4202 4203 // This only gets set when Neon instructions are actually available, unlike 4204 // the VFP define, hence the soft float and arch check. This is subtly 4205 // different from gcc, we follow the intent which was that it should be set 4206 // when Neon instructions are actually available. 4207 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4208 Builder.defineMacro("__ARM_NEON"); 4209 Builder.defineMacro("__ARM_NEON__"); 4210 } 4211 4212 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4213 Opts.ShortWChar ? "2" : "4"); 4214 4215 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4216 Opts.ShortEnums ? "1" : "4"); 4217 4218 if (CRC) 4219 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4220 4221 if (Crypto) 4222 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4223 4224 if (CPUArchVer >= 6 && CPUArch != "6M") { 4225 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4226 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4227 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4228 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4229 } 4230 4231 bool is5EOrAbove = (CPUArchVer >= 6 || 4232 (CPUArchVer == 5 && 4233 CPUArch.find('E') != StringRef::npos)); 4234 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer)); 4235 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM")) 4236 Builder.defineMacro("__ARM_FEATURE_DSP"); 4237 } 4238 void getTargetBuiltins(const Builtin::Info *&Records, 4239 unsigned &NumRecords) const override { 4240 Records = BuiltinInfo; 4241 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4242 } 4243 bool isCLZForZeroUndef() const override { return false; } 4244 BuiltinVaListKind getBuiltinVaListKind() const override { 4245 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4246 } 4247 void getGCCRegNames(const char * const *&Names, 4248 unsigned &NumNames) const override; 4249 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4250 unsigned &NumAliases) const override; 4251 bool validateAsmConstraint(const char *&Name, 4252 TargetInfo::ConstraintInfo &Info) const override { 4253 switch (*Name) { 4254 default: break; 4255 case 'l': // r0-r7 4256 case 'h': // r8-r15 4257 case 'w': // VFP Floating point register single precision 4258 case 'P': // VFP Floating point register double precision 4259 Info.setAllowsRegister(); 4260 return true; 4261 case 'Q': // A memory address that is a single base register. 4262 Info.setAllowsMemory(); 4263 return true; 4264 case 'U': // a memory reference... 4265 switch (Name[1]) { 4266 case 'q': // ...ARMV4 ldrsb 4267 case 'v': // ...VFP load/store (reg+constant offset) 4268 case 'y': // ...iWMMXt load/store 4269 case 't': // address valid for load/store opaque types wider 4270 // than 128-bits 4271 case 'n': // valid address for Neon doubleword vector load/store 4272 case 'm': // valid address for Neon element and structure load/store 4273 case 's': // valid address for non-offset loads/stores of quad-word 4274 // values in four ARM registers 4275 Info.setAllowsMemory(); 4276 Name++; 4277 return true; 4278 } 4279 } 4280 return false; 4281 } 4282 std::string convertConstraint(const char *&Constraint) const override { 4283 std::string R; 4284 switch (*Constraint) { 4285 case 'U': // Two-character constraint; add "^" hint for later parsing. 4286 R = std::string("^") + std::string(Constraint, 2); 4287 Constraint++; 4288 break; 4289 case 'p': // 'p' should be translated to 'r' by default. 4290 R = std::string("r"); 4291 break; 4292 default: 4293 return std::string(1, *Constraint); 4294 } 4295 return R; 4296 } 4297 bool 4298 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4299 std::string &SuggestedModifier) const override { 4300 bool isOutput = (Constraint[0] == '='); 4301 bool isInOut = (Constraint[0] == '+'); 4302 4303 // Strip off constraint modifiers. 4304 while (Constraint[0] == '=' || 4305 Constraint[0] == '+' || 4306 Constraint[0] == '&') 4307 Constraint = Constraint.substr(1); 4308 4309 switch (Constraint[0]) { 4310 default: break; 4311 case 'r': { 4312 switch (Modifier) { 4313 default: 4314 return (isInOut || isOutput || Size <= 64); 4315 case 'q': 4316 // A register of size 32 cannot fit a vector type. 4317 return false; 4318 } 4319 } 4320 } 4321 4322 return true; 4323 } 4324 const char *getClobbers() const override { 4325 // FIXME: Is this really right? 4326 return ""; 4327 } 4328 4329 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4330 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4331 } 4332 4333 int getEHDataRegisterNumber(unsigned RegNo) const override { 4334 if (RegNo == 0) return 0; 4335 if (RegNo == 1) return 1; 4336 return -1; 4337 } 4338 }; 4339 4340 bool ARMTargetInfo::setFPMath(StringRef Name) { 4341 if (Name == "neon") { 4342 FPMath = FP_Neon; 4343 return true; 4344 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4345 Name == "vfp4") { 4346 FPMath = FP_VFP; 4347 return true; 4348 } 4349 return false; 4350 } 4351 4352 const char * const ARMTargetInfo::GCCRegNames[] = { 4353 // Integer registers 4354 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4355 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4356 4357 // Float registers 4358 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4359 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4360 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4361 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4362 4363 // Double registers 4364 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4365 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4366 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4367 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4368 4369 // Quad registers 4370 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4371 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4372 }; 4373 4374 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4375 unsigned &NumNames) const { 4376 Names = GCCRegNames; 4377 NumNames = llvm::array_lengthof(GCCRegNames); 4378 } 4379 4380 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4381 { { "a1" }, "r0" }, 4382 { { "a2" }, "r1" }, 4383 { { "a3" }, "r2" }, 4384 { { "a4" }, "r3" }, 4385 { { "v1" }, "r4" }, 4386 { { "v2" }, "r5" }, 4387 { { "v3" }, "r6" }, 4388 { { "v4" }, "r7" }, 4389 { { "v5" }, "r8" }, 4390 { { "v6", "rfp" }, "r9" }, 4391 { { "sl" }, "r10" }, 4392 { { "fp" }, "r11" }, 4393 { { "ip" }, "r12" }, 4394 { { "r13" }, "sp" }, 4395 { { "r14" }, "lr" }, 4396 { { "r15" }, "pc" }, 4397 // The S, D and Q registers overlap, but aren't really aliases; we 4398 // don't want to substitute one of these for a different-sized one. 4399 }; 4400 4401 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4402 unsigned &NumAliases) const { 4403 Aliases = GCCRegAliases; 4404 NumAliases = llvm::array_lengthof(GCCRegAliases); 4405 } 4406 4407 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4408 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4409 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4410 ALL_LANGUAGES }, 4411 #include "clang/Basic/BuiltinsNEON.def" 4412 4413 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4414 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG }, 4415 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4416 ALL_LANGUAGES }, 4417 #include "clang/Basic/BuiltinsARM.def" 4418 }; 4419 4420 class ARMleTargetInfo : public ARMTargetInfo { 4421 public: 4422 ARMleTargetInfo(const llvm::Triple &Triple) 4423 : ARMTargetInfo(Triple, false) { } 4424 virtual void getTargetDefines(const LangOptions &Opts, 4425 MacroBuilder &Builder) const { 4426 Builder.defineMacro("__ARMEL__"); 4427 ARMTargetInfo::getTargetDefines(Opts, Builder); 4428 } 4429 }; 4430 4431 class ARMbeTargetInfo : public ARMTargetInfo { 4432 public: 4433 ARMbeTargetInfo(const llvm::Triple &Triple) 4434 : ARMTargetInfo(Triple, true) { } 4435 virtual void getTargetDefines(const LangOptions &Opts, 4436 MacroBuilder &Builder) const { 4437 Builder.defineMacro("__ARMEB__"); 4438 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4439 ARMTargetInfo::getTargetDefines(Opts, Builder); 4440 } 4441 }; 4442 } // end anonymous namespace. 4443 4444 namespace { 4445 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4446 const llvm::Triple Triple; 4447 public: 4448 WindowsARMTargetInfo(const llvm::Triple &Triple) 4449 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4450 TLSSupported = false; 4451 WCharType = UnsignedShort; 4452 SizeType = UnsignedInt; 4453 UserLabelPrefix = ""; 4454 } 4455 void getVisualStudioDefines(const LangOptions &Opts, 4456 MacroBuilder &Builder) const { 4457 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4458 4459 // FIXME: this is invalid for WindowsCE 4460 Builder.defineMacro("_M_ARM_NT", "1"); 4461 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4462 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4463 4464 assert((Triple.getArch() == llvm::Triple::arm || 4465 Triple.getArch() == llvm::Triple::thumb) && 4466 "invalid architecture for Windows ARM target info"); 4467 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4468 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4469 4470 // TODO map the complete set of values 4471 // 31: VFPv3 40: VFPv4 4472 Builder.defineMacro("_M_ARM_FP", "31"); 4473 } 4474 BuiltinVaListKind getBuiltinVaListKind() const override { 4475 return TargetInfo::CharPtrBuiltinVaList; 4476 } 4477 }; 4478 4479 // Windows ARM + Itanium C++ ABI Target 4480 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4481 public: 4482 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4483 : WindowsARMTargetInfo(Triple) { 4484 TheCXXABI.set(TargetCXXABI::GenericARM); 4485 } 4486 4487 void getTargetDefines(const LangOptions &Opts, 4488 MacroBuilder &Builder) const override { 4489 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4490 4491 if (Opts.MSVCCompat) 4492 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4493 } 4494 }; 4495 4496 // Windows ARM, MS (C++) ABI 4497 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4498 public: 4499 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4500 : WindowsARMTargetInfo(Triple) { 4501 TheCXXABI.set(TargetCXXABI::Microsoft); 4502 } 4503 4504 void getTargetDefines(const LangOptions &Opts, 4505 MacroBuilder &Builder) const override { 4506 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4507 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4508 } 4509 }; 4510 } 4511 4512 4513 namespace { 4514 class DarwinARMTargetInfo : 4515 public DarwinTargetInfo<ARMleTargetInfo> { 4516 protected: 4517 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4518 MacroBuilder &Builder) const override { 4519 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4520 } 4521 4522 public: 4523 DarwinARMTargetInfo(const llvm::Triple &Triple) 4524 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4525 HasAlignMac68kSupport = true; 4526 // iOS always has 64-bit atomic instructions. 4527 // FIXME: This should be based off of the target features in 4528 // ARMleTargetInfo. 4529 MaxAtomicInlineWidth = 64; 4530 4531 // Darwin on iOS uses a variant of the ARM C++ ABI. 4532 TheCXXABI.set(TargetCXXABI::iOS); 4533 } 4534 }; 4535 } // end anonymous namespace. 4536 4537 4538 namespace { 4539 class AArch64TargetInfo : public TargetInfo { 4540 virtual void setDescriptionString() = 0; 4541 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4542 static const char *const GCCRegNames[]; 4543 4544 enum FPUModeEnum { 4545 FPUMode, 4546 NeonMode 4547 }; 4548 4549 unsigned FPU; 4550 unsigned CRC; 4551 unsigned Crypto; 4552 4553 static const Builtin::Info BuiltinInfo[]; 4554 4555 std::string ABI; 4556 4557 public: 4558 AArch64TargetInfo(const llvm::Triple &Triple) 4559 : TargetInfo(Triple), ABI("aapcs") { 4560 4561 if (getTriple().getOS() == llvm::Triple::NetBSD) { 4562 WCharType = SignedInt; 4563 4564 // NetBSD apparently prefers consistency across ARM targets to consistency 4565 // across 64-bit targets. 4566 Int64Type = SignedLongLong; 4567 IntMaxType = SignedLongLong; 4568 } else { 4569 WCharType = UnsignedInt; 4570 Int64Type = SignedLong; 4571 IntMaxType = SignedLong; 4572 } 4573 4574 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4575 MaxVectorAlign = 128; 4576 RegParmMax = 8; 4577 MaxAtomicInlineWidth = 128; 4578 MaxAtomicPromoteWidth = 128; 4579 4580 LongDoubleWidth = LongDoubleAlign = 128; 4581 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4582 4583 // {} in inline assembly are neon specifiers, not assembly variant 4584 // specifiers. 4585 NoAsmVariants = true; 4586 4587 // AArch64 targets default to using the ARM C++ ABI. 4588 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4589 } 4590 4591 StringRef getABI() const override { return ABI; } 4592 bool setABI(const std::string &Name) override { 4593 if (Name != "aapcs" && Name != "darwinpcs") 4594 return false; 4595 4596 ABI = Name; 4597 return true; 4598 } 4599 4600 bool setCPU(const std::string &Name) override { 4601 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4602 .Case("generic", true) 4603 .Cases("cortex-a53", "cortex-a57", true) 4604 .Case("cyclone", true) 4605 .Default(false); 4606 return CPUKnown; 4607 } 4608 4609 virtual void getTargetDefines(const LangOptions &Opts, 4610 MacroBuilder &Builder) const override { 4611 // Target identification. 4612 Builder.defineMacro("__aarch64__"); 4613 4614 // Target properties. 4615 Builder.defineMacro("_LP64"); 4616 Builder.defineMacro("__LP64__"); 4617 4618 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4619 Builder.defineMacro("__ARM_ACLE", "200"); 4620 Builder.defineMacro("__ARM_ARCH", "8"); 4621 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4622 4623 Builder.defineMacro("__ARM_64BIT_STATE"); 4624 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4625 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4626 4627 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4628 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4629 Builder.defineMacro("__ARM_FEATURE_FMA"); 4630 Builder.defineMacro("__ARM_FEATURE_DIV"); 4631 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE 4632 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 4633 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4634 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4635 4636 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 4637 4638 // 0xe implies support for half, single and double precision operations. 4639 Builder.defineMacro("__ARM_FP", "0xe"); 4640 4641 // PCS specifies this for SysV variants, which is all we support. Other ABIs 4642 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 4643 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 4644 4645 if (Opts.FastMath || Opts.FiniteMathOnly) 4646 Builder.defineMacro("__ARM_FP_FAST"); 4647 4648 if (Opts.C99 && !Opts.Freestanding) 4649 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 4650 4651 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 4652 4653 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4654 Opts.ShortEnums ? "1" : "4"); 4655 4656 if (FPU == NeonMode) { 4657 Builder.defineMacro("__ARM_NEON"); 4658 // 64-bit NEON supports half, single and double precision operations. 4659 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 4660 } 4661 4662 if (CRC) 4663 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4664 4665 if (Crypto) 4666 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4667 } 4668 4669 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4670 unsigned &NumRecords) const override { 4671 Records = BuiltinInfo; 4672 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 4673 } 4674 4675 bool hasFeature(StringRef Feature) const override { 4676 return Feature == "aarch64" || 4677 Feature == "arm64" || 4678 (Feature == "neon" && FPU == NeonMode); 4679 } 4680 4681 bool handleTargetFeatures(std::vector<std::string> &Features, 4682 DiagnosticsEngine &Diags) override { 4683 FPU = FPUMode; 4684 CRC = 0; 4685 Crypto = 0; 4686 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 4687 if (Features[i] == "+neon") 4688 FPU = NeonMode; 4689 if (Features[i] == "+crc") 4690 CRC = 1; 4691 if (Features[i] == "+crypto") 4692 Crypto = 1; 4693 } 4694 4695 setDescriptionString(); 4696 4697 return true; 4698 } 4699 4700 bool isCLZForZeroUndef() const override { return false; } 4701 4702 BuiltinVaListKind getBuiltinVaListKind() const override { 4703 return TargetInfo::AArch64ABIBuiltinVaList; 4704 } 4705 4706 virtual void getGCCRegNames(const char *const *&Names, 4707 unsigned &NumNames) const override; 4708 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4709 unsigned &NumAliases) const override; 4710 4711 virtual bool 4712 validateAsmConstraint(const char *&Name, 4713 TargetInfo::ConstraintInfo &Info) const override { 4714 switch (*Name) { 4715 default: 4716 return false; 4717 case 'w': // Floating point and SIMD registers (V0-V31) 4718 Info.setAllowsRegister(); 4719 return true; 4720 case 'I': // Constant that can be used with an ADD instruction 4721 case 'J': // Constant that can be used with a SUB instruction 4722 case 'K': // Constant that can be used with a 32-bit logical instruction 4723 case 'L': // Constant that can be used with a 64-bit logical instruction 4724 case 'M': // Constant that can be used as a 32-bit MOV immediate 4725 case 'N': // Constant that can be used as a 64-bit MOV immediate 4726 case 'Y': // Floating point constant zero 4727 case 'Z': // Integer constant zero 4728 return true; 4729 case 'Q': // A memory reference with base register and no offset 4730 Info.setAllowsMemory(); 4731 return true; 4732 case 'S': // A symbolic address 4733 Info.setAllowsRegister(); 4734 return true; 4735 case 'U': 4736 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 4737 // Utf: A memory address suitable for ldp/stp in TF mode. 4738 // Usa: An absolute symbolic address. 4739 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 4740 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 4741 case 'z': // Zero register, wzr or xzr 4742 Info.setAllowsRegister(); 4743 return true; 4744 case 'x': // Floating point and SIMD registers (V0-V15) 4745 Info.setAllowsRegister(); 4746 return true; 4747 } 4748 return false; 4749 } 4750 4751 bool 4752 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4753 std::string &SuggestedModifier) const override { 4754 // Strip off constraint modifiers. 4755 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 4756 Constraint = Constraint.substr(1); 4757 4758 switch (Constraint[0]) { 4759 default: 4760 return true; 4761 case 'z': 4762 case 'r': { 4763 switch (Modifier) { 4764 case 'x': 4765 case 'w': 4766 // For now assume that the person knows what they're 4767 // doing with the modifier. 4768 return true; 4769 default: 4770 // By default an 'r' constraint will be in the 'x' 4771 // registers. 4772 if (Size == 64) 4773 return true; 4774 4775 SuggestedModifier = "w"; 4776 return false; 4777 } 4778 } 4779 } 4780 } 4781 4782 const char *getClobbers() const override { return ""; } 4783 4784 int getEHDataRegisterNumber(unsigned RegNo) const override { 4785 if (RegNo == 0) 4786 return 0; 4787 if (RegNo == 1) 4788 return 1; 4789 return -1; 4790 } 4791 }; 4792 4793 const char *const AArch64TargetInfo::GCCRegNames[] = { 4794 // 32-bit Integer registers 4795 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 4796 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 4797 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 4798 4799 // 64-bit Integer registers 4800 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 4801 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 4802 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 4803 4804 // 32-bit floating point regsisters 4805 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 4806 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 4807 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4808 4809 // 64-bit floating point regsisters 4810 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 4811 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 4812 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4813 4814 // Vector registers 4815 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 4816 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 4817 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 4818 }; 4819 4820 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 4821 unsigned &NumNames) const { 4822 Names = GCCRegNames; 4823 NumNames = llvm::array_lengthof(GCCRegNames); 4824 } 4825 4826 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 4827 { { "w31" }, "wsp" }, 4828 { { "x29" }, "fp" }, 4829 { { "x30" }, "lr" }, 4830 { { "x31" }, "sp" }, 4831 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 4832 // don't want to substitute one of these for a different-sized one. 4833 }; 4834 4835 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4836 unsigned &NumAliases) const { 4837 Aliases = GCCRegAliases; 4838 NumAliases = llvm::array_lengthof(GCCRegAliases); 4839 } 4840 4841 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 4842 #define BUILTIN(ID, TYPE, ATTRS) \ 4843 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4844 #include "clang/Basic/BuiltinsNEON.def" 4845 4846 #define BUILTIN(ID, TYPE, ATTRS) \ 4847 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4848 #include "clang/Basic/BuiltinsAArch64.def" 4849 }; 4850 4851 class AArch64leTargetInfo : public AArch64TargetInfo { 4852 void setDescriptionString() override { 4853 if (getTriple().isOSBinFormatMachO()) 4854 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 4855 else 4856 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 4857 } 4858 4859 public: 4860 AArch64leTargetInfo(const llvm::Triple &Triple) 4861 : AArch64TargetInfo(Triple) { 4862 BigEndian = false; 4863 } 4864 void getTargetDefines(const LangOptions &Opts, 4865 MacroBuilder &Builder) const override { 4866 Builder.defineMacro("__AARCH64EL__"); 4867 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4868 } 4869 }; 4870 4871 class AArch64beTargetInfo : public AArch64TargetInfo { 4872 void setDescriptionString() override { 4873 assert(!getTriple().isOSBinFormatMachO()); 4874 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 4875 } 4876 4877 public: 4878 AArch64beTargetInfo(const llvm::Triple &Triple) 4879 : AArch64TargetInfo(Triple) { } 4880 void getTargetDefines(const LangOptions &Opts, 4881 MacroBuilder &Builder) const override { 4882 Builder.defineMacro("__AARCH64EB__"); 4883 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 4884 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4885 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4886 } 4887 }; 4888 } // end anonymous namespace. 4889 4890 namespace { 4891 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 4892 protected: 4893 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4894 MacroBuilder &Builder) const override { 4895 Builder.defineMacro("__AARCH64_SIMD__"); 4896 Builder.defineMacro("__ARM64_ARCH_8__"); 4897 Builder.defineMacro("__ARM_NEON__"); 4898 Builder.defineMacro("__LITTLE_ENDIAN__"); 4899 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4900 Builder.defineMacro("__arm64", "1"); 4901 Builder.defineMacro("__arm64__", "1"); 4902 4903 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4904 } 4905 4906 public: 4907 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 4908 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 4909 Int64Type = SignedLongLong; 4910 WCharType = SignedInt; 4911 UseSignedCharForObjCBool = false; 4912 4913 LongDoubleWidth = LongDoubleAlign = 64; 4914 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4915 4916 TheCXXABI.set(TargetCXXABI::iOS64); 4917 } 4918 4919 BuiltinVaListKind getBuiltinVaListKind() const override { 4920 return TargetInfo::CharPtrBuiltinVaList; 4921 } 4922 }; 4923 } // end anonymous namespace 4924 4925 namespace { 4926 // Hexagon abstract base class 4927 class HexagonTargetInfo : public TargetInfo { 4928 static const Builtin::Info BuiltinInfo[]; 4929 static const char * const GCCRegNames[]; 4930 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4931 std::string CPU; 4932 public: 4933 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4934 BigEndian = false; 4935 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 4936 4937 // {} in inline assembly are packet specifiers, not assembly variant 4938 // specifiers. 4939 NoAsmVariants = true; 4940 } 4941 4942 void getTargetBuiltins(const Builtin::Info *&Records, 4943 unsigned &NumRecords) const override { 4944 Records = BuiltinInfo; 4945 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4946 } 4947 4948 bool validateAsmConstraint(const char *&Name, 4949 TargetInfo::ConstraintInfo &Info) const override { 4950 return true; 4951 } 4952 4953 void getTargetDefines(const LangOptions &Opts, 4954 MacroBuilder &Builder) const override; 4955 4956 bool hasFeature(StringRef Feature) const override { 4957 return Feature == "hexagon"; 4958 } 4959 4960 BuiltinVaListKind getBuiltinVaListKind() const override { 4961 return TargetInfo::CharPtrBuiltinVaList; 4962 } 4963 void getGCCRegNames(const char * const *&Names, 4964 unsigned &NumNames) const override; 4965 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4966 unsigned &NumAliases) const override; 4967 const char *getClobbers() const override { 4968 return ""; 4969 } 4970 4971 static const char *getHexagonCPUSuffix(StringRef Name) { 4972 return llvm::StringSwitch<const char*>(Name) 4973 .Case("hexagonv4", "4") 4974 .Case("hexagonv5", "5") 4975 .Default(nullptr); 4976 } 4977 4978 bool setCPU(const std::string &Name) override { 4979 if (!getHexagonCPUSuffix(Name)) 4980 return false; 4981 4982 CPU = Name; 4983 return true; 4984 } 4985 }; 4986 4987 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4988 MacroBuilder &Builder) const { 4989 Builder.defineMacro("qdsp6"); 4990 Builder.defineMacro("__qdsp6", "1"); 4991 Builder.defineMacro("__qdsp6__", "1"); 4992 4993 Builder.defineMacro("hexagon"); 4994 Builder.defineMacro("__hexagon", "1"); 4995 Builder.defineMacro("__hexagon__", "1"); 4996 4997 if(CPU == "hexagonv1") { 4998 Builder.defineMacro("__HEXAGON_V1__"); 4999 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5000 if(Opts.HexagonQdsp6Compat) { 5001 Builder.defineMacro("__QDSP6_V1__"); 5002 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5003 } 5004 } 5005 else if(CPU == "hexagonv2") { 5006 Builder.defineMacro("__HEXAGON_V2__"); 5007 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5008 if(Opts.HexagonQdsp6Compat) { 5009 Builder.defineMacro("__QDSP6_V2__"); 5010 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5011 } 5012 } 5013 else if(CPU == "hexagonv3") { 5014 Builder.defineMacro("__HEXAGON_V3__"); 5015 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5016 if(Opts.HexagonQdsp6Compat) { 5017 Builder.defineMacro("__QDSP6_V3__"); 5018 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5019 } 5020 } 5021 else if(CPU == "hexagonv4") { 5022 Builder.defineMacro("__HEXAGON_V4__"); 5023 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5024 if(Opts.HexagonQdsp6Compat) { 5025 Builder.defineMacro("__QDSP6_V4__"); 5026 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5027 } 5028 } 5029 else if(CPU == "hexagonv5") { 5030 Builder.defineMacro("__HEXAGON_V5__"); 5031 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5032 if(Opts.HexagonQdsp6Compat) { 5033 Builder.defineMacro("__QDSP6_V5__"); 5034 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5035 } 5036 } 5037 } 5038 5039 const char * const HexagonTargetInfo::GCCRegNames[] = { 5040 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5041 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5042 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5043 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5044 "p0", "p1", "p2", "p3", 5045 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5046 }; 5047 5048 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5049 unsigned &NumNames) const { 5050 Names = GCCRegNames; 5051 NumNames = llvm::array_lengthof(GCCRegNames); 5052 } 5053 5054 5055 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5056 { { "sp" }, "r29" }, 5057 { { "fp" }, "r30" }, 5058 { { "lr" }, "r31" }, 5059 }; 5060 5061 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5062 unsigned &NumAliases) const { 5063 Aliases = GCCRegAliases; 5064 NumAliases = llvm::array_lengthof(GCCRegAliases); 5065 } 5066 5067 5068 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5069 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5070 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5071 ALL_LANGUAGES }, 5072 #include "clang/Basic/BuiltinsHexagon.def" 5073 }; 5074 } 5075 5076 5077 namespace { 5078 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5079 class SparcTargetInfo : public TargetInfo { 5080 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5081 static const char * const GCCRegNames[]; 5082 bool SoftFloat; 5083 public: 5084 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 5085 5086 bool handleTargetFeatures(std::vector<std::string> &Features, 5087 DiagnosticsEngine &Diags) override { 5088 SoftFloat = false; 5089 for (unsigned i = 0, e = Features.size(); i != e; ++i) 5090 if (Features[i] == "+soft-float") 5091 SoftFloat = true; 5092 return true; 5093 } 5094 void getTargetDefines(const LangOptions &Opts, 5095 MacroBuilder &Builder) const override { 5096 DefineStd(Builder, "sparc", Opts); 5097 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5098 5099 if (SoftFloat) 5100 Builder.defineMacro("SOFT_FLOAT", "1"); 5101 } 5102 5103 bool hasFeature(StringRef Feature) const override { 5104 return llvm::StringSwitch<bool>(Feature) 5105 .Case("softfloat", SoftFloat) 5106 .Case("sparc", true) 5107 .Default(false); 5108 } 5109 5110 void getTargetBuiltins(const Builtin::Info *&Records, 5111 unsigned &NumRecords) const override { 5112 // FIXME: Implement! 5113 } 5114 BuiltinVaListKind getBuiltinVaListKind() const override { 5115 return TargetInfo::VoidPtrBuiltinVaList; 5116 } 5117 void getGCCRegNames(const char * const *&Names, 5118 unsigned &NumNames) const override; 5119 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5120 unsigned &NumAliases) const override; 5121 bool validateAsmConstraint(const char *&Name, 5122 TargetInfo::ConstraintInfo &info) const override { 5123 // FIXME: Implement! 5124 return false; 5125 } 5126 const char *getClobbers() const override { 5127 // FIXME: Implement! 5128 return ""; 5129 } 5130 }; 5131 5132 const char * const SparcTargetInfo::GCCRegNames[] = { 5133 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5134 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5135 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5136 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5137 }; 5138 5139 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5140 unsigned &NumNames) const { 5141 Names = GCCRegNames; 5142 NumNames = llvm::array_lengthof(GCCRegNames); 5143 } 5144 5145 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5146 { { "g0" }, "r0" }, 5147 { { "g1" }, "r1" }, 5148 { { "g2" }, "r2" }, 5149 { { "g3" }, "r3" }, 5150 { { "g4" }, "r4" }, 5151 { { "g5" }, "r5" }, 5152 { { "g6" }, "r6" }, 5153 { { "g7" }, "r7" }, 5154 { { "o0" }, "r8" }, 5155 { { "o1" }, "r9" }, 5156 { { "o2" }, "r10" }, 5157 { { "o3" }, "r11" }, 5158 { { "o4" }, "r12" }, 5159 { { "o5" }, "r13" }, 5160 { { "o6", "sp" }, "r14" }, 5161 { { "o7" }, "r15" }, 5162 { { "l0" }, "r16" }, 5163 { { "l1" }, "r17" }, 5164 { { "l2" }, "r18" }, 5165 { { "l3" }, "r19" }, 5166 { { "l4" }, "r20" }, 5167 { { "l5" }, "r21" }, 5168 { { "l6" }, "r22" }, 5169 { { "l7" }, "r23" }, 5170 { { "i0" }, "r24" }, 5171 { { "i1" }, "r25" }, 5172 { { "i2" }, "r26" }, 5173 { { "i3" }, "r27" }, 5174 { { "i4" }, "r28" }, 5175 { { "i5" }, "r29" }, 5176 { { "i6", "fp" }, "r30" }, 5177 { { "i7" }, "r31" }, 5178 }; 5179 5180 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5181 unsigned &NumAliases) const { 5182 Aliases = GCCRegAliases; 5183 NumAliases = llvm::array_lengthof(GCCRegAliases); 5184 } 5185 5186 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5187 class SparcV8TargetInfo : public SparcTargetInfo { 5188 public: 5189 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5190 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5191 } 5192 5193 void getTargetDefines(const LangOptions &Opts, 5194 MacroBuilder &Builder) const override { 5195 SparcTargetInfo::getTargetDefines(Opts, Builder); 5196 Builder.defineMacro("__sparcv8"); 5197 } 5198 }; 5199 5200 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5201 class SparcV9TargetInfo : public SparcTargetInfo { 5202 public: 5203 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5204 // FIXME: Support Sparc quad-precision long double? 5205 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5206 // This is an LP64 platform. 5207 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5208 5209 // OpenBSD uses long long for int64_t and intmax_t. 5210 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5211 IntMaxType = SignedLongLong; 5212 else 5213 IntMaxType = SignedLong; 5214 Int64Type = IntMaxType; 5215 5216 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5217 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5218 LongDoubleWidth = 128; 5219 LongDoubleAlign = 128; 5220 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5221 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5222 } 5223 5224 void getTargetDefines(const LangOptions &Opts, 5225 MacroBuilder &Builder) const override { 5226 SparcTargetInfo::getTargetDefines(Opts, Builder); 5227 Builder.defineMacro("__sparcv9"); 5228 Builder.defineMacro("__arch64__"); 5229 // Solaris doesn't need these variants, but the BSDs do. 5230 if (getTriple().getOS() != llvm::Triple::Solaris) { 5231 Builder.defineMacro("__sparc64__"); 5232 Builder.defineMacro("__sparc_v9__"); 5233 Builder.defineMacro("__sparcv9__"); 5234 } 5235 } 5236 5237 bool setCPU(const std::string &Name) override { 5238 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5239 .Case("v9", true) 5240 .Case("ultrasparc", true) 5241 .Case("ultrasparc3", true) 5242 .Case("niagara", true) 5243 .Case("niagara2", true) 5244 .Case("niagara3", true) 5245 .Case("niagara4", true) 5246 .Default(false); 5247 5248 // No need to store the CPU yet. There aren't any CPU-specific 5249 // macros to define. 5250 return CPUKnown; 5251 } 5252 }; 5253 5254 } // end anonymous namespace. 5255 5256 namespace { 5257 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 5258 public: 5259 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 5260 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 5261 SizeType = UnsignedInt; 5262 PtrDiffType = SignedInt; 5263 } 5264 }; 5265 } // end anonymous namespace. 5266 5267 namespace { 5268 class SystemZTargetInfo : public TargetInfo { 5269 static const char *const GCCRegNames[]; 5270 5271 public: 5272 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5273 TLSSupported = true; 5274 IntWidth = IntAlign = 32; 5275 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5276 PointerWidth = PointerAlign = 64; 5277 LongDoubleWidth = 128; 5278 LongDoubleAlign = 64; 5279 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5280 MinGlobalAlign = 16; 5281 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5282 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5283 } 5284 void getTargetDefines(const LangOptions &Opts, 5285 MacroBuilder &Builder) const override { 5286 Builder.defineMacro("__s390__"); 5287 Builder.defineMacro("__s390x__"); 5288 Builder.defineMacro("__zarch__"); 5289 Builder.defineMacro("__LONG_DOUBLE_128__"); 5290 } 5291 void getTargetBuiltins(const Builtin::Info *&Records, 5292 unsigned &NumRecords) const override { 5293 // FIXME: Implement. 5294 Records = nullptr; 5295 NumRecords = 0; 5296 } 5297 5298 void getGCCRegNames(const char *const *&Names, 5299 unsigned &NumNames) const override; 5300 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5301 unsigned &NumAliases) const override { 5302 // No aliases. 5303 Aliases = nullptr; 5304 NumAliases = 0; 5305 } 5306 bool validateAsmConstraint(const char *&Name, 5307 TargetInfo::ConstraintInfo &info) const override; 5308 const char *getClobbers() const override { 5309 // FIXME: Is this really right? 5310 return ""; 5311 } 5312 BuiltinVaListKind getBuiltinVaListKind() const override { 5313 return TargetInfo::SystemZBuiltinVaList; 5314 } 5315 bool setCPU(const std::string &Name) override { 5316 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5317 .Case("z10", true) 5318 .Case("z196", true) 5319 .Case("zEC12", true) 5320 .Default(false); 5321 5322 // No need to store the CPU yet. There aren't any CPU-specific 5323 // macros to define. 5324 return CPUKnown; 5325 } 5326 }; 5327 5328 const char *const SystemZTargetInfo::GCCRegNames[] = { 5329 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5330 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5331 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5332 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5333 }; 5334 5335 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5336 unsigned &NumNames) const { 5337 Names = GCCRegNames; 5338 NumNames = llvm::array_lengthof(GCCRegNames); 5339 } 5340 5341 bool SystemZTargetInfo:: 5342 validateAsmConstraint(const char *&Name, 5343 TargetInfo::ConstraintInfo &Info) const { 5344 switch (*Name) { 5345 default: 5346 return false; 5347 5348 case 'a': // Address register 5349 case 'd': // Data register (equivalent to 'r') 5350 case 'f': // Floating-point register 5351 Info.setAllowsRegister(); 5352 return true; 5353 5354 case 'I': // Unsigned 8-bit constant 5355 case 'J': // Unsigned 12-bit constant 5356 case 'K': // Signed 16-bit constant 5357 case 'L': // Signed 20-bit displacement (on all targets we support) 5358 case 'M': // 0x7fffffff 5359 return true; 5360 5361 case 'Q': // Memory with base and unsigned 12-bit displacement 5362 case 'R': // Likewise, plus an index 5363 case 'S': // Memory with base and signed 20-bit displacement 5364 case 'T': // Likewise, plus an index 5365 Info.setAllowsMemory(); 5366 return true; 5367 } 5368 } 5369 } 5370 5371 namespace { 5372 class MSP430TargetInfo : public TargetInfo { 5373 static const char * const GCCRegNames[]; 5374 public: 5375 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5376 BigEndian = false; 5377 TLSSupported = false; 5378 IntWidth = 16; IntAlign = 16; 5379 LongWidth = 32; LongLongWidth = 64; 5380 LongAlign = LongLongAlign = 16; 5381 PointerWidth = 16; PointerAlign = 16; 5382 SuitableAlign = 16; 5383 SizeType = UnsignedInt; 5384 IntMaxType = SignedLongLong; 5385 IntPtrType = SignedInt; 5386 PtrDiffType = SignedInt; 5387 SigAtomicType = SignedLong; 5388 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 5389 } 5390 void getTargetDefines(const LangOptions &Opts, 5391 MacroBuilder &Builder) const override { 5392 Builder.defineMacro("MSP430"); 5393 Builder.defineMacro("__MSP430__"); 5394 // FIXME: defines for different 'flavours' of MCU 5395 } 5396 void getTargetBuiltins(const Builtin::Info *&Records, 5397 unsigned &NumRecords) const override { 5398 // FIXME: Implement. 5399 Records = nullptr; 5400 NumRecords = 0; 5401 } 5402 bool hasFeature(StringRef Feature) const override { 5403 return Feature == "msp430"; 5404 } 5405 void getGCCRegNames(const char * const *&Names, 5406 unsigned &NumNames) const override; 5407 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5408 unsigned &NumAliases) const override { 5409 // No aliases. 5410 Aliases = nullptr; 5411 NumAliases = 0; 5412 } 5413 bool 5414 validateAsmConstraint(const char *&Name, 5415 TargetInfo::ConstraintInfo &info) const override { 5416 // No target constraints for now. 5417 return false; 5418 } 5419 const char *getClobbers() const override { 5420 // FIXME: Is this really right? 5421 return ""; 5422 } 5423 BuiltinVaListKind getBuiltinVaListKind() const override { 5424 // FIXME: implement 5425 return TargetInfo::CharPtrBuiltinVaList; 5426 } 5427 }; 5428 5429 const char * const MSP430TargetInfo::GCCRegNames[] = { 5430 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5431 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5432 }; 5433 5434 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5435 unsigned &NumNames) const { 5436 Names = GCCRegNames; 5437 NumNames = llvm::array_lengthof(GCCRegNames); 5438 } 5439 } 5440 5441 namespace { 5442 5443 // LLVM and Clang cannot be used directly to output native binaries for 5444 // target, but is used to compile C code to llvm bitcode with correct 5445 // type and alignment information. 5446 // 5447 // TCE uses the llvm bitcode as input and uses it for generating customized 5448 // target processor and program binary. TCE co-design environment is 5449 // publicly available in http://tce.cs.tut.fi 5450 5451 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5452 3, // opencl_global 5453 4, // opencl_local 5454 5, // opencl_constant 5455 // FIXME: generic has to be added to the target 5456 0, // opencl_generic 5457 0, // cuda_device 5458 0, // cuda_constant 5459 0 // cuda_shared 5460 }; 5461 5462 class TCETargetInfo : public TargetInfo{ 5463 public: 5464 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5465 TLSSupported = false; 5466 IntWidth = 32; 5467 LongWidth = LongLongWidth = 32; 5468 PointerWidth = 32; 5469 IntAlign = 32; 5470 LongAlign = LongLongAlign = 32; 5471 PointerAlign = 32; 5472 SuitableAlign = 32; 5473 SizeType = UnsignedInt; 5474 IntMaxType = SignedLong; 5475 IntPtrType = SignedInt; 5476 PtrDiffType = SignedInt; 5477 FloatWidth = 32; 5478 FloatAlign = 32; 5479 DoubleWidth = 32; 5480 DoubleAlign = 32; 5481 LongDoubleWidth = 32; 5482 LongDoubleAlign = 32; 5483 FloatFormat = &llvm::APFloat::IEEEsingle; 5484 DoubleFormat = &llvm::APFloat::IEEEsingle; 5485 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5486 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5487 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5488 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5489 UseAddrSpaceMapMangling = true; 5490 } 5491 5492 void getTargetDefines(const LangOptions &Opts, 5493 MacroBuilder &Builder) const override { 5494 DefineStd(Builder, "tce", Opts); 5495 Builder.defineMacro("__TCE__"); 5496 Builder.defineMacro("__TCE_V1__"); 5497 } 5498 bool hasFeature(StringRef Feature) const override { 5499 return Feature == "tce"; 5500 } 5501 5502 void getTargetBuiltins(const Builtin::Info *&Records, 5503 unsigned &NumRecords) const override {} 5504 const char *getClobbers() const override { 5505 return ""; 5506 } 5507 BuiltinVaListKind getBuiltinVaListKind() const override { 5508 return TargetInfo::VoidPtrBuiltinVaList; 5509 } 5510 void getGCCRegNames(const char * const *&Names, 5511 unsigned &NumNames) const override {} 5512 bool validateAsmConstraint(const char *&Name, 5513 TargetInfo::ConstraintInfo &info) const override{ 5514 return true; 5515 } 5516 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5517 unsigned &NumAliases) const override {} 5518 }; 5519 } 5520 5521 namespace { 5522 class MipsTargetInfoBase : public TargetInfo { 5523 virtual void setDescriptionString() = 0; 5524 5525 static const Builtin::Info BuiltinInfo[]; 5526 std::string CPU; 5527 bool IsMips16; 5528 bool IsMicromips; 5529 bool IsNan2008; 5530 bool IsSingleFloat; 5531 enum MipsFloatABI { 5532 HardFloat, SoftFloat 5533 } FloatABI; 5534 enum DspRevEnum { 5535 NoDSP, DSP1, DSP2 5536 } DspRev; 5537 bool HasMSA; 5538 5539 protected: 5540 bool HasFP64; 5541 std::string ABI; 5542 5543 public: 5544 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5545 const std::string &CPUStr) 5546 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5547 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5548 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 5549 5550 bool isNaN2008Default() const { 5551 return CPU == "mips32r6" || CPU == "mips64r6"; 5552 } 5553 5554 bool isFP64Default() const { 5555 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 5556 } 5557 5558 StringRef getABI() const override { return ABI; } 5559 bool setCPU(const std::string &Name) override { 5560 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 5561 getTriple().getArch() == llvm::Triple::mipsel; 5562 CPU = Name; 5563 return llvm::StringSwitch<bool>(Name) 5564 .Case("mips1", IsMips32) 5565 .Case("mips2", IsMips32) 5566 .Case("mips3", true) 5567 .Case("mips4", true) 5568 .Case("mips5", true) 5569 .Case("mips32", IsMips32) 5570 .Case("mips32r2", IsMips32) 5571 .Case("mips32r6", IsMips32) 5572 .Case("mips64", true) 5573 .Case("mips64r2", true) 5574 .Case("mips64r6", true) 5575 .Case("octeon", true) 5576 .Default(false); 5577 } 5578 const std::string& getCPU() const { return CPU; } 5579 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5580 // The backend enables certain ABI's by default according to the 5581 // architecture. 5582 // Disable both possible defaults so that we don't end up with multiple 5583 // ABI's selected and trigger an assertion. 5584 Features["o32"] = false; 5585 Features["n64"] = false; 5586 5587 Features[ABI] = true; 5588 if (CPU == "octeon") 5589 Features["mips64r2"] = Features["cnmips"] = true; 5590 else 5591 Features[CPU] = true; 5592 } 5593 5594 void getTargetDefines(const LangOptions &Opts, 5595 MacroBuilder &Builder) const override { 5596 Builder.defineMacro("__mips__"); 5597 Builder.defineMacro("_mips"); 5598 if (Opts.GNUMode) 5599 Builder.defineMacro("mips"); 5600 5601 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5602 5603 switch (FloatABI) { 5604 case HardFloat: 5605 Builder.defineMacro("__mips_hard_float", Twine(1)); 5606 break; 5607 case SoftFloat: 5608 Builder.defineMacro("__mips_soft_float", Twine(1)); 5609 break; 5610 } 5611 5612 if (IsSingleFloat) 5613 Builder.defineMacro("__mips_single_float", Twine(1)); 5614 5615 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5616 Builder.defineMacro("_MIPS_FPSET", 5617 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5618 5619 if (IsMips16) 5620 Builder.defineMacro("__mips16", Twine(1)); 5621 5622 if (IsMicromips) 5623 Builder.defineMacro("__mips_micromips", Twine(1)); 5624 5625 if (IsNan2008) 5626 Builder.defineMacro("__mips_nan2008", Twine(1)); 5627 5628 switch (DspRev) { 5629 default: 5630 break; 5631 case DSP1: 5632 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5633 Builder.defineMacro("__mips_dsp", Twine(1)); 5634 break; 5635 case DSP2: 5636 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5637 Builder.defineMacro("__mips_dspr2", Twine(1)); 5638 Builder.defineMacro("__mips_dsp", Twine(1)); 5639 break; 5640 } 5641 5642 if (HasMSA) 5643 Builder.defineMacro("__mips_msa", Twine(1)); 5644 5645 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5646 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5647 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5648 5649 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5650 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5651 } 5652 5653 void getTargetBuiltins(const Builtin::Info *&Records, 5654 unsigned &NumRecords) const override { 5655 Records = BuiltinInfo; 5656 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5657 } 5658 bool hasFeature(StringRef Feature) const override { 5659 return llvm::StringSwitch<bool>(Feature) 5660 .Case("mips", true) 5661 .Case("fp64", HasFP64) 5662 .Default(false); 5663 } 5664 BuiltinVaListKind getBuiltinVaListKind() const override { 5665 return TargetInfo::VoidPtrBuiltinVaList; 5666 } 5667 void getGCCRegNames(const char * const *&Names, 5668 unsigned &NumNames) const override { 5669 static const char *const GCCRegNames[] = { 5670 // CPU register names 5671 // Must match second column of GCCRegAliases 5672 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5673 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5674 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5675 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5676 // Floating point register names 5677 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5678 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5679 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5680 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5681 // Hi/lo and condition register names 5682 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5683 "$fcc5","$fcc6","$fcc7", 5684 // MSA register names 5685 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5686 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5687 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5688 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5689 // MSA control register names 5690 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5691 "$msarequest", "$msamap", "$msaunmap" 5692 }; 5693 Names = GCCRegNames; 5694 NumNames = llvm::array_lengthof(GCCRegNames); 5695 } 5696 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5697 unsigned &NumAliases) const override = 0; 5698 bool validateAsmConstraint(const char *&Name, 5699 TargetInfo::ConstraintInfo &Info) const override { 5700 switch (*Name) { 5701 default: 5702 return false; 5703 case 'r': // CPU registers. 5704 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5705 case 'y': // Equivalent to "r", backward compatibility only. 5706 case 'f': // floating-point registers. 5707 case 'c': // $25 for indirect jumps 5708 case 'l': // lo register 5709 case 'x': // hilo register pair 5710 Info.setAllowsRegister(); 5711 return true; 5712 case 'R': // An address that can be used in a non-macro load or store 5713 Info.setAllowsMemory(); 5714 return true; 5715 } 5716 } 5717 5718 const char *getClobbers() const override { 5719 // FIXME: Implement! 5720 return ""; 5721 } 5722 5723 bool handleTargetFeatures(std::vector<std::string> &Features, 5724 DiagnosticsEngine &Diags) override { 5725 IsMips16 = false; 5726 IsMicromips = false; 5727 IsNan2008 = isNaN2008Default(); 5728 IsSingleFloat = false; 5729 FloatABI = HardFloat; 5730 DspRev = NoDSP; 5731 HasFP64 = isFP64Default(); 5732 5733 for (std::vector<std::string>::iterator it = Features.begin(), 5734 ie = Features.end(); it != ie; ++it) { 5735 if (*it == "+single-float") 5736 IsSingleFloat = true; 5737 else if (*it == "+soft-float") 5738 FloatABI = SoftFloat; 5739 else if (*it == "+mips16") 5740 IsMips16 = true; 5741 else if (*it == "+micromips") 5742 IsMicromips = true; 5743 else if (*it == "+dsp") 5744 DspRev = std::max(DspRev, DSP1); 5745 else if (*it == "+dspr2") 5746 DspRev = std::max(DspRev, DSP2); 5747 else if (*it == "+msa") 5748 HasMSA = true; 5749 else if (*it == "+fp64") 5750 HasFP64 = true; 5751 else if (*it == "-fp64") 5752 HasFP64 = false; 5753 else if (*it == "+nan2008") 5754 IsNan2008 = true; 5755 else if (*it == "-nan2008") 5756 IsNan2008 = false; 5757 } 5758 5759 // Remove front-end specific options. 5760 std::vector<std::string>::iterator it = 5761 std::find(Features.begin(), Features.end(), "+soft-float"); 5762 if (it != Features.end()) 5763 Features.erase(it); 5764 5765 setDescriptionString(); 5766 5767 return true; 5768 } 5769 5770 int getEHDataRegisterNumber(unsigned RegNo) const override { 5771 if (RegNo == 0) return 4; 5772 if (RegNo == 1) return 5; 5773 return -1; 5774 } 5775 5776 bool isCLZForZeroUndef() const override { return false; } 5777 }; 5778 5779 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5780 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5781 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5782 ALL_LANGUAGES }, 5783 #include "clang/Basic/BuiltinsMips.def" 5784 }; 5785 5786 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5787 public: 5788 Mips32TargetInfoBase(const llvm::Triple &Triple) 5789 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 5790 SizeType = UnsignedInt; 5791 PtrDiffType = SignedInt; 5792 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5793 } 5794 bool setABI(const std::string &Name) override { 5795 if (Name == "o32" || Name == "eabi") { 5796 ABI = Name; 5797 return true; 5798 } 5799 return false; 5800 } 5801 void getTargetDefines(const LangOptions &Opts, 5802 MacroBuilder &Builder) const override { 5803 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5804 5805 Builder.defineMacro("__mips", "32"); 5806 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 5807 5808 const std::string& CPUStr = getCPU(); 5809 if (CPUStr == "mips32") 5810 Builder.defineMacro("__mips_isa_rev", "1"); 5811 else if (CPUStr == "mips32r2") 5812 Builder.defineMacro("__mips_isa_rev", "2"); 5813 5814 if (ABI == "o32") { 5815 Builder.defineMacro("__mips_o32"); 5816 Builder.defineMacro("_ABIO32", "1"); 5817 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5818 } 5819 else if (ABI == "eabi") 5820 Builder.defineMacro("__mips_eabi"); 5821 else 5822 llvm_unreachable("Invalid ABI for Mips32."); 5823 } 5824 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5825 unsigned &NumAliases) const override { 5826 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5827 { { "at" }, "$1" }, 5828 { { "v0" }, "$2" }, 5829 { { "v1" }, "$3" }, 5830 { { "a0" }, "$4" }, 5831 { { "a1" }, "$5" }, 5832 { { "a2" }, "$6" }, 5833 { { "a3" }, "$7" }, 5834 { { "t0" }, "$8" }, 5835 { { "t1" }, "$9" }, 5836 { { "t2" }, "$10" }, 5837 { { "t3" }, "$11" }, 5838 { { "t4" }, "$12" }, 5839 { { "t5" }, "$13" }, 5840 { { "t6" }, "$14" }, 5841 { { "t7" }, "$15" }, 5842 { { "s0" }, "$16" }, 5843 { { "s1" }, "$17" }, 5844 { { "s2" }, "$18" }, 5845 { { "s3" }, "$19" }, 5846 { { "s4" }, "$20" }, 5847 { { "s5" }, "$21" }, 5848 { { "s6" }, "$22" }, 5849 { { "s7" }, "$23" }, 5850 { { "t8" }, "$24" }, 5851 { { "t9" }, "$25" }, 5852 { { "k0" }, "$26" }, 5853 { { "k1" }, "$27" }, 5854 { { "gp" }, "$28" }, 5855 { { "sp","$sp" }, "$29" }, 5856 { { "fp","$fp" }, "$30" }, 5857 { { "ra" }, "$31" } 5858 }; 5859 Aliases = GCCRegAliases; 5860 NumAliases = llvm::array_lengthof(GCCRegAliases); 5861 } 5862 }; 5863 5864 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5865 void setDescriptionString() override { 5866 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5867 } 5868 5869 public: 5870 Mips32EBTargetInfo(const llvm::Triple &Triple) 5871 : Mips32TargetInfoBase(Triple) { 5872 } 5873 void getTargetDefines(const LangOptions &Opts, 5874 MacroBuilder &Builder) const override { 5875 DefineStd(Builder, "MIPSEB", Opts); 5876 Builder.defineMacro("_MIPSEB"); 5877 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5878 } 5879 }; 5880 5881 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5882 void setDescriptionString() override { 5883 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5884 } 5885 5886 public: 5887 Mips32ELTargetInfo(const llvm::Triple &Triple) 5888 : Mips32TargetInfoBase(Triple) { 5889 BigEndian = false; 5890 } 5891 void getTargetDefines(const LangOptions &Opts, 5892 MacroBuilder &Builder) const override { 5893 DefineStd(Builder, "MIPSEL", Opts); 5894 Builder.defineMacro("_MIPSEL"); 5895 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5896 } 5897 }; 5898 5899 class Mips64TargetInfoBase : public MipsTargetInfoBase { 5900 public: 5901 Mips64TargetInfoBase(const llvm::Triple &Triple) 5902 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 5903 LongDoubleWidth = LongDoubleAlign = 128; 5904 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5905 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5906 LongDoubleWidth = LongDoubleAlign = 64; 5907 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5908 } 5909 setN64ABITypes(); 5910 SuitableAlign = 128; 5911 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5912 } 5913 5914 void setN64ABITypes() { 5915 LongWidth = LongAlign = 64; 5916 PointerWidth = PointerAlign = 64; 5917 SizeType = UnsignedLong; 5918 PtrDiffType = SignedLong; 5919 } 5920 5921 void setN32ABITypes() { 5922 LongWidth = LongAlign = 32; 5923 PointerWidth = PointerAlign = 32; 5924 SizeType = UnsignedInt; 5925 PtrDiffType = SignedInt; 5926 } 5927 5928 bool setABI(const std::string &Name) override { 5929 if (Name == "n32") { 5930 setN32ABITypes(); 5931 ABI = Name; 5932 return true; 5933 } 5934 if (Name == "n64") { 5935 setN64ABITypes(); 5936 ABI = Name; 5937 return true; 5938 } 5939 return false; 5940 } 5941 5942 void getTargetDefines(const LangOptions &Opts, 5943 MacroBuilder &Builder) const override { 5944 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5945 5946 Builder.defineMacro("__mips", "64"); 5947 Builder.defineMacro("__mips64"); 5948 Builder.defineMacro("__mips64__"); 5949 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 5950 5951 const std::string& CPUStr = getCPU(); 5952 if (CPUStr == "mips64") 5953 Builder.defineMacro("__mips_isa_rev", "1"); 5954 else if (CPUStr == "mips64r2") 5955 Builder.defineMacro("__mips_isa_rev", "2"); 5956 5957 if (ABI == "n32") { 5958 Builder.defineMacro("__mips_n32"); 5959 Builder.defineMacro("_ABIN32", "2"); 5960 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5961 } 5962 else if (ABI == "n64") { 5963 Builder.defineMacro("__mips_n64"); 5964 Builder.defineMacro("_ABI64", "3"); 5965 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5966 } 5967 else 5968 llvm_unreachable("Invalid ABI for Mips64."); 5969 } 5970 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5971 unsigned &NumAliases) const override { 5972 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5973 { { "at" }, "$1" }, 5974 { { "v0" }, "$2" }, 5975 { { "v1" }, "$3" }, 5976 { { "a0" }, "$4" }, 5977 { { "a1" }, "$5" }, 5978 { { "a2" }, "$6" }, 5979 { { "a3" }, "$7" }, 5980 { { "a4" }, "$8" }, 5981 { { "a5" }, "$9" }, 5982 { { "a6" }, "$10" }, 5983 { { "a7" }, "$11" }, 5984 { { "t0" }, "$12" }, 5985 { { "t1" }, "$13" }, 5986 { { "t2" }, "$14" }, 5987 { { "t3" }, "$15" }, 5988 { { "s0" }, "$16" }, 5989 { { "s1" }, "$17" }, 5990 { { "s2" }, "$18" }, 5991 { { "s3" }, "$19" }, 5992 { { "s4" }, "$20" }, 5993 { { "s5" }, "$21" }, 5994 { { "s6" }, "$22" }, 5995 { { "s7" }, "$23" }, 5996 { { "t8" }, "$24" }, 5997 { { "t9" }, "$25" }, 5998 { { "k0" }, "$26" }, 5999 { { "k1" }, "$27" }, 6000 { { "gp" }, "$28" }, 6001 { { "sp","$sp" }, "$29" }, 6002 { { "fp","$fp" }, "$30" }, 6003 { { "ra" }, "$31" } 6004 }; 6005 Aliases = GCCRegAliases; 6006 NumAliases = llvm::array_lengthof(GCCRegAliases); 6007 } 6008 6009 bool hasInt128Type() const override { return true; } 6010 }; 6011 6012 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6013 void setDescriptionString() override { 6014 if (ABI == "n32") 6015 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6016 else 6017 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6018 6019 } 6020 6021 public: 6022 Mips64EBTargetInfo(const llvm::Triple &Triple) 6023 : Mips64TargetInfoBase(Triple) {} 6024 void getTargetDefines(const LangOptions &Opts, 6025 MacroBuilder &Builder) const override { 6026 DefineStd(Builder, "MIPSEB", Opts); 6027 Builder.defineMacro("_MIPSEB"); 6028 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6029 } 6030 }; 6031 6032 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6033 void setDescriptionString() override { 6034 if (ABI == "n32") 6035 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6036 else 6037 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6038 } 6039 public: 6040 Mips64ELTargetInfo(const llvm::Triple &Triple) 6041 : Mips64TargetInfoBase(Triple) { 6042 // Default ABI is n64. 6043 BigEndian = false; 6044 } 6045 void getTargetDefines(const LangOptions &Opts, 6046 MacroBuilder &Builder) const override { 6047 DefineStd(Builder, "MIPSEL", Opts); 6048 Builder.defineMacro("_MIPSEL"); 6049 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6050 } 6051 }; 6052 } // end anonymous namespace. 6053 6054 namespace { 6055 class PNaClTargetInfo : public TargetInfo { 6056 public: 6057 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6058 BigEndian = false; 6059 this->UserLabelPrefix = ""; 6060 this->LongAlign = 32; 6061 this->LongWidth = 32; 6062 this->PointerAlign = 32; 6063 this->PointerWidth = 32; 6064 this->IntMaxType = TargetInfo::SignedLongLong; 6065 this->Int64Type = TargetInfo::SignedLongLong; 6066 this->DoubleAlign = 64; 6067 this->LongDoubleWidth = 64; 6068 this->LongDoubleAlign = 64; 6069 this->SizeType = TargetInfo::UnsignedInt; 6070 this->PtrDiffType = TargetInfo::SignedInt; 6071 this->IntPtrType = TargetInfo::SignedInt; 6072 this->RegParmMax = 0; // Disallow regparm 6073 } 6074 6075 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6076 } 6077 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6078 Builder.defineMacro("__le32__"); 6079 Builder.defineMacro("__pnacl__"); 6080 } 6081 void getTargetDefines(const LangOptions &Opts, 6082 MacroBuilder &Builder) const override { 6083 getArchDefines(Opts, Builder); 6084 } 6085 bool hasFeature(StringRef Feature) const override { 6086 return Feature == "pnacl"; 6087 } 6088 void getTargetBuiltins(const Builtin::Info *&Records, 6089 unsigned &NumRecords) const override { 6090 } 6091 BuiltinVaListKind getBuiltinVaListKind() const override { 6092 return TargetInfo::PNaClABIBuiltinVaList; 6093 } 6094 void getGCCRegNames(const char * const *&Names, 6095 unsigned &NumNames) const override; 6096 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6097 unsigned &NumAliases) const override; 6098 bool validateAsmConstraint(const char *&Name, 6099 TargetInfo::ConstraintInfo &Info) const override { 6100 return false; 6101 } 6102 6103 const char *getClobbers() const override { 6104 return ""; 6105 } 6106 }; 6107 6108 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6109 unsigned &NumNames) const { 6110 Names = nullptr; 6111 NumNames = 0; 6112 } 6113 6114 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6115 unsigned &NumAliases) const { 6116 Aliases = nullptr; 6117 NumAliases = 0; 6118 } 6119 } // end anonymous namespace. 6120 6121 namespace { 6122 class Le64TargetInfo : public TargetInfo { 6123 static const Builtin::Info BuiltinInfo[]; 6124 6125 public: 6126 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6127 BigEndian = false; 6128 NoAsmVariants = true; 6129 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6130 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6131 DescriptionString = 6132 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6133 } 6134 6135 void getTargetDefines(const LangOptions &Opts, 6136 MacroBuilder &Builder) const override { 6137 DefineStd(Builder, "unix", Opts); 6138 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6139 Builder.defineMacro("__ELF__"); 6140 } 6141 void getTargetBuiltins(const Builtin::Info *&Records, 6142 unsigned &NumRecords) const override { 6143 Records = BuiltinInfo; 6144 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6145 } 6146 BuiltinVaListKind getBuiltinVaListKind() const override { 6147 return TargetInfo::PNaClABIBuiltinVaList; 6148 } 6149 const char *getClobbers() const override { return ""; } 6150 void getGCCRegNames(const char *const *&Names, 6151 unsigned &NumNames) const override { 6152 Names = nullptr; 6153 NumNames = 0; 6154 } 6155 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6156 unsigned &NumAliases) const override { 6157 Aliases = nullptr; 6158 NumAliases = 0; 6159 } 6160 bool validateAsmConstraint(const char *&Name, 6161 TargetInfo::ConstraintInfo &Info) const override { 6162 return false; 6163 } 6164 6165 bool hasProtectedVisibility() const override { return false; } 6166 }; 6167 } // end anonymous namespace. 6168 6169 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 6170 #define BUILTIN(ID, TYPE, ATTRS) \ 6171 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6172 #include "clang/Basic/BuiltinsLe64.def" 6173 }; 6174 6175 namespace { 6176 static const unsigned SPIRAddrSpaceMap[] = { 6177 1, // opencl_global 6178 3, // opencl_local 6179 2, // opencl_constant 6180 4, // opencl_generic 6181 0, // cuda_device 6182 0, // cuda_constant 6183 0 // cuda_shared 6184 }; 6185 class SPIRTargetInfo : public TargetInfo { 6186 public: 6187 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6188 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 6189 "SPIR target must use unknown OS"); 6190 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 6191 "SPIR target must use unknown environment type"); 6192 BigEndian = false; 6193 TLSSupported = false; 6194 LongWidth = LongAlign = 64; 6195 AddrSpaceMap = &SPIRAddrSpaceMap; 6196 UseAddrSpaceMapMangling = true; 6197 // Define available target features 6198 // These must be defined in sorted order! 6199 NoAsmVariants = true; 6200 } 6201 void getTargetDefines(const LangOptions &Opts, 6202 MacroBuilder &Builder) const override { 6203 DefineStd(Builder, "SPIR", Opts); 6204 } 6205 bool hasFeature(StringRef Feature) const override { 6206 return Feature == "spir"; 6207 } 6208 6209 void getTargetBuiltins(const Builtin::Info *&Records, 6210 unsigned &NumRecords) const override {} 6211 const char *getClobbers() const override { 6212 return ""; 6213 } 6214 void getGCCRegNames(const char * const *&Names, 6215 unsigned &NumNames) const override {} 6216 bool 6217 validateAsmConstraint(const char *&Name, 6218 TargetInfo::ConstraintInfo &info) const override { 6219 return true; 6220 } 6221 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6222 unsigned &NumAliases) const override {} 6223 BuiltinVaListKind getBuiltinVaListKind() const override { 6224 return TargetInfo::VoidPtrBuiltinVaList; 6225 } 6226 }; 6227 6228 6229 class SPIR32TargetInfo : public SPIRTargetInfo { 6230 public: 6231 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6232 PointerWidth = PointerAlign = 32; 6233 SizeType = TargetInfo::UnsignedInt; 6234 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6235 DescriptionString 6236 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6237 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6238 } 6239 void getTargetDefines(const LangOptions &Opts, 6240 MacroBuilder &Builder) const override { 6241 DefineStd(Builder, "SPIR32", Opts); 6242 } 6243 }; 6244 6245 class SPIR64TargetInfo : public SPIRTargetInfo { 6246 public: 6247 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6248 PointerWidth = PointerAlign = 64; 6249 SizeType = TargetInfo::UnsignedLong; 6250 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6251 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6252 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6253 } 6254 void getTargetDefines(const LangOptions &Opts, 6255 MacroBuilder &Builder) const override { 6256 DefineStd(Builder, "SPIR64", Opts); 6257 } 6258 }; 6259 } 6260 6261 namespace { 6262 class XCoreTargetInfo : public TargetInfo { 6263 static const Builtin::Info BuiltinInfo[]; 6264 public: 6265 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6266 BigEndian = false; 6267 NoAsmVariants = true; 6268 LongLongAlign = 32; 6269 SuitableAlign = 32; 6270 DoubleAlign = LongDoubleAlign = 32; 6271 SizeType = UnsignedInt; 6272 PtrDiffType = SignedInt; 6273 IntPtrType = SignedInt; 6274 WCharType = UnsignedChar; 6275 WIntType = UnsignedInt; 6276 UseZeroLengthBitfieldAlignment = true; 6277 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6278 "-f64:32-a:0:32-n32"; 6279 } 6280 void getTargetDefines(const LangOptions &Opts, 6281 MacroBuilder &Builder) const override { 6282 Builder.defineMacro("__XS1B__"); 6283 } 6284 void getTargetBuiltins(const Builtin::Info *&Records, 6285 unsigned &NumRecords) const override { 6286 Records = BuiltinInfo; 6287 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6288 } 6289 BuiltinVaListKind getBuiltinVaListKind() const override { 6290 return TargetInfo::VoidPtrBuiltinVaList; 6291 } 6292 const char *getClobbers() const override { 6293 return ""; 6294 } 6295 void getGCCRegNames(const char * const *&Names, 6296 unsigned &NumNames) const override { 6297 static const char * const GCCRegNames[] = { 6298 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6299 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6300 }; 6301 Names = GCCRegNames; 6302 NumNames = llvm::array_lengthof(GCCRegNames); 6303 } 6304 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6305 unsigned &NumAliases) const override { 6306 Aliases = nullptr; 6307 NumAliases = 0; 6308 } 6309 bool validateAsmConstraint(const char *&Name, 6310 TargetInfo::ConstraintInfo &Info) const override { 6311 return false; 6312 } 6313 int getEHDataRegisterNumber(unsigned RegNo) const override { 6314 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6315 return (RegNo < 2)? RegNo : -1; 6316 } 6317 }; 6318 6319 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6320 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6321 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6322 ALL_LANGUAGES }, 6323 #include "clang/Basic/BuiltinsXCore.def" 6324 }; 6325 } // end anonymous namespace. 6326 6327 6328 //===----------------------------------------------------------------------===// 6329 // Driver code 6330 //===----------------------------------------------------------------------===// 6331 6332 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 6333 llvm::Triple::OSType os = Triple.getOS(); 6334 6335 switch (Triple.getArch()) { 6336 default: 6337 return nullptr; 6338 6339 case llvm::Triple::xcore: 6340 return new XCoreTargetInfo(Triple); 6341 6342 case llvm::Triple::hexagon: 6343 return new HexagonTargetInfo(Triple); 6344 6345 case llvm::Triple::aarch64: 6346 if (Triple.isOSDarwin()) 6347 return new DarwinAArch64TargetInfo(Triple); 6348 6349 switch (os) { 6350 case llvm::Triple::FreeBSD: 6351 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 6352 case llvm::Triple::Linux: 6353 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6354 case llvm::Triple::NetBSD: 6355 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6356 default: 6357 return new AArch64leTargetInfo(Triple); 6358 } 6359 6360 case llvm::Triple::aarch64_be: 6361 switch (os) { 6362 case llvm::Triple::FreeBSD: 6363 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 6364 case llvm::Triple::Linux: 6365 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6366 case llvm::Triple::NetBSD: 6367 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6368 default: 6369 return new AArch64beTargetInfo(Triple); 6370 } 6371 6372 case llvm::Triple::arm: 6373 case llvm::Triple::thumb: 6374 if (Triple.isOSBinFormatMachO()) 6375 return new DarwinARMTargetInfo(Triple); 6376 6377 switch (os) { 6378 case llvm::Triple::Linux: 6379 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6380 case llvm::Triple::FreeBSD: 6381 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6382 case llvm::Triple::NetBSD: 6383 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6384 case llvm::Triple::OpenBSD: 6385 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6386 case llvm::Triple::Bitrig: 6387 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6388 case llvm::Triple::RTEMS: 6389 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6390 case llvm::Triple::NaCl: 6391 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6392 case llvm::Triple::Win32: 6393 switch (Triple.getEnvironment()) { 6394 default: 6395 return new ARMleTargetInfo(Triple); 6396 case llvm::Triple::Itanium: 6397 return new ItaniumWindowsARMleTargetInfo(Triple); 6398 case llvm::Triple::MSVC: 6399 return new MicrosoftARMleTargetInfo(Triple); 6400 } 6401 default: 6402 return new ARMleTargetInfo(Triple); 6403 } 6404 6405 case llvm::Triple::armeb: 6406 case llvm::Triple::thumbeb: 6407 if (Triple.isOSDarwin()) 6408 return new DarwinARMTargetInfo(Triple); 6409 6410 switch (os) { 6411 case llvm::Triple::Linux: 6412 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 6413 case llvm::Triple::FreeBSD: 6414 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 6415 case llvm::Triple::NetBSD: 6416 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 6417 case llvm::Triple::OpenBSD: 6418 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 6419 case llvm::Triple::Bitrig: 6420 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 6421 case llvm::Triple::RTEMS: 6422 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 6423 case llvm::Triple::NaCl: 6424 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 6425 default: 6426 return new ARMbeTargetInfo(Triple); 6427 } 6428 6429 case llvm::Triple::msp430: 6430 return new MSP430TargetInfo(Triple); 6431 6432 case llvm::Triple::mips: 6433 switch (os) { 6434 case llvm::Triple::Linux: 6435 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 6436 case llvm::Triple::RTEMS: 6437 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 6438 case llvm::Triple::FreeBSD: 6439 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6440 case llvm::Triple::NetBSD: 6441 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6442 default: 6443 return new Mips32EBTargetInfo(Triple); 6444 } 6445 6446 case llvm::Triple::mipsel: 6447 switch (os) { 6448 case llvm::Triple::Linux: 6449 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 6450 case llvm::Triple::RTEMS: 6451 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 6452 case llvm::Triple::FreeBSD: 6453 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6454 case llvm::Triple::NetBSD: 6455 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6456 case llvm::Triple::NaCl: 6457 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 6458 default: 6459 return new Mips32ELTargetInfo(Triple); 6460 } 6461 6462 case llvm::Triple::mips64: 6463 switch (os) { 6464 case llvm::Triple::Linux: 6465 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 6466 case llvm::Triple::RTEMS: 6467 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 6468 case llvm::Triple::FreeBSD: 6469 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6470 case llvm::Triple::NetBSD: 6471 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6472 case llvm::Triple::OpenBSD: 6473 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6474 default: 6475 return new Mips64EBTargetInfo(Triple); 6476 } 6477 6478 case llvm::Triple::mips64el: 6479 switch (os) { 6480 case llvm::Triple::Linux: 6481 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 6482 case llvm::Triple::RTEMS: 6483 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 6484 case llvm::Triple::FreeBSD: 6485 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6486 case llvm::Triple::NetBSD: 6487 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6488 case llvm::Triple::OpenBSD: 6489 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6490 default: 6491 return new Mips64ELTargetInfo(Triple); 6492 } 6493 6494 case llvm::Triple::le32: 6495 switch (os) { 6496 case llvm::Triple::NaCl: 6497 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 6498 default: 6499 return nullptr; 6500 } 6501 6502 case llvm::Triple::le64: 6503 return new Le64TargetInfo(Triple); 6504 6505 case llvm::Triple::ppc: 6506 if (Triple.isOSDarwin()) 6507 return new DarwinPPC32TargetInfo(Triple); 6508 switch (os) { 6509 case llvm::Triple::Linux: 6510 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 6511 case llvm::Triple::FreeBSD: 6512 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 6513 case llvm::Triple::NetBSD: 6514 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 6515 case llvm::Triple::OpenBSD: 6516 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 6517 case llvm::Triple::RTEMS: 6518 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 6519 default: 6520 return new PPC32TargetInfo(Triple); 6521 } 6522 6523 case llvm::Triple::ppc64: 6524 if (Triple.isOSDarwin()) 6525 return new DarwinPPC64TargetInfo(Triple); 6526 switch (os) { 6527 case llvm::Triple::Linux: 6528 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6529 case llvm::Triple::Lv2: 6530 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 6531 case llvm::Triple::FreeBSD: 6532 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 6533 case llvm::Triple::NetBSD: 6534 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6535 default: 6536 return new PPC64TargetInfo(Triple); 6537 } 6538 6539 case llvm::Triple::ppc64le: 6540 switch (os) { 6541 case llvm::Triple::Linux: 6542 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6543 default: 6544 return new PPC64TargetInfo(Triple); 6545 } 6546 6547 case llvm::Triple::nvptx: 6548 return new NVPTX32TargetInfo(Triple); 6549 case llvm::Triple::nvptx64: 6550 return new NVPTX64TargetInfo(Triple); 6551 6552 case llvm::Triple::r600: 6553 return new R600TargetInfo(Triple); 6554 6555 case llvm::Triple::sparc: 6556 switch (os) { 6557 case llvm::Triple::Linux: 6558 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 6559 case llvm::Triple::Solaris: 6560 return new SolarisSparcV8TargetInfo(Triple); 6561 case llvm::Triple::NetBSD: 6562 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 6563 case llvm::Triple::OpenBSD: 6564 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 6565 case llvm::Triple::RTEMS: 6566 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 6567 default: 6568 return new SparcV8TargetInfo(Triple); 6569 } 6570 6571 case llvm::Triple::sparcv9: 6572 switch (os) { 6573 case llvm::Triple::Linux: 6574 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 6575 case llvm::Triple::Solaris: 6576 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 6577 case llvm::Triple::NetBSD: 6578 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 6579 case llvm::Triple::OpenBSD: 6580 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 6581 case llvm::Triple::FreeBSD: 6582 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 6583 default: 6584 return new SparcV9TargetInfo(Triple); 6585 } 6586 6587 case llvm::Triple::systemz: 6588 switch (os) { 6589 case llvm::Triple::Linux: 6590 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 6591 default: 6592 return new SystemZTargetInfo(Triple); 6593 } 6594 6595 case llvm::Triple::tce: 6596 return new TCETargetInfo(Triple); 6597 6598 case llvm::Triple::x86: 6599 if (Triple.isOSDarwin()) 6600 return new DarwinI386TargetInfo(Triple); 6601 6602 switch (os) { 6603 case llvm::Triple::Linux: 6604 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 6605 case llvm::Triple::DragonFly: 6606 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 6607 case llvm::Triple::NetBSD: 6608 return new NetBSDI386TargetInfo(Triple); 6609 case llvm::Triple::OpenBSD: 6610 return new OpenBSDI386TargetInfo(Triple); 6611 case llvm::Triple::Bitrig: 6612 return new BitrigI386TargetInfo(Triple); 6613 case llvm::Triple::FreeBSD: 6614 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6615 case llvm::Triple::KFreeBSD: 6616 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6617 case llvm::Triple::Minix: 6618 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 6619 case llvm::Triple::Solaris: 6620 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 6621 case llvm::Triple::Win32: { 6622 switch (Triple.getEnvironment()) { 6623 default: 6624 return new X86_32TargetInfo(Triple); 6625 case llvm::Triple::Cygnus: 6626 return new CygwinX86_32TargetInfo(Triple); 6627 case llvm::Triple::GNU: 6628 return new MinGWX86_32TargetInfo(Triple); 6629 case llvm::Triple::Itanium: 6630 case llvm::Triple::MSVC: 6631 return new MicrosoftX86_32TargetInfo(Triple); 6632 } 6633 } 6634 case llvm::Triple::Haiku: 6635 return new HaikuX86_32TargetInfo(Triple); 6636 case llvm::Triple::RTEMS: 6637 return new RTEMSX86_32TargetInfo(Triple); 6638 case llvm::Triple::NaCl: 6639 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 6640 default: 6641 return new X86_32TargetInfo(Triple); 6642 } 6643 6644 case llvm::Triple::x86_64: 6645 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 6646 return new DarwinX86_64TargetInfo(Triple); 6647 6648 switch (os) { 6649 case llvm::Triple::Linux: 6650 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 6651 case llvm::Triple::DragonFly: 6652 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 6653 case llvm::Triple::NetBSD: 6654 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 6655 case llvm::Triple::OpenBSD: 6656 return new OpenBSDX86_64TargetInfo(Triple); 6657 case llvm::Triple::Bitrig: 6658 return new BitrigX86_64TargetInfo(Triple); 6659 case llvm::Triple::FreeBSD: 6660 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6661 case llvm::Triple::KFreeBSD: 6662 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6663 case llvm::Triple::Solaris: 6664 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 6665 case llvm::Triple::Win32: { 6666 switch (Triple.getEnvironment()) { 6667 default: 6668 return new X86_64TargetInfo(Triple); 6669 case llvm::Triple::GNU: 6670 return new MinGWX86_64TargetInfo(Triple); 6671 case llvm::Triple::MSVC: 6672 return new MicrosoftX86_64TargetInfo(Triple); 6673 } 6674 } 6675 case llvm::Triple::NaCl: 6676 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 6677 default: 6678 return new X86_64TargetInfo(Triple); 6679 } 6680 6681 case llvm::Triple::spir: { 6682 if (Triple.getOS() != llvm::Triple::UnknownOS || 6683 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6684 return nullptr; 6685 return new SPIR32TargetInfo(Triple); 6686 } 6687 case llvm::Triple::spir64: { 6688 if (Triple.getOS() != llvm::Triple::UnknownOS || 6689 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6690 return nullptr; 6691 return new SPIR64TargetInfo(Triple); 6692 } 6693 } 6694 } 6695 6696 /// CreateTargetInfo - Return the target info object for the specified target 6697 /// triple. 6698 TargetInfo * 6699 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 6700 const std::shared_ptr<TargetOptions> &Opts) { 6701 llvm::Triple Triple(Opts->Triple); 6702 6703 // Construct the target 6704 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 6705 if (!Target) { 6706 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 6707 return nullptr; 6708 } 6709 Target->TargetOpts = Opts; 6710 6711 // Set the target CPU if specified. 6712 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 6713 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 6714 return nullptr; 6715 } 6716 6717 // Set the target ABI if specified. 6718 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 6719 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 6720 return nullptr; 6721 } 6722 6723 // Set the fp math unit. 6724 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 6725 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 6726 return nullptr; 6727 } 6728 6729 // Compute the default target features, we need the target to handle this 6730 // because features may have dependencies on one another. 6731 llvm::StringMap<bool> Features; 6732 Target->getDefaultFeatures(Features); 6733 6734 // Apply the user specified deltas. 6735 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 6736 I < N; ++I) { 6737 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 6738 // Apply the feature via the target. 6739 bool Enabled = Name[0] == '+'; 6740 Target->setFeatureEnabled(Features, Name + 1, Enabled); 6741 } 6742 6743 // Add the features to the compile options. 6744 // 6745 // FIXME: If we are completely confident that we have the right set, we only 6746 // need to pass the minuses. 6747 Opts->Features.clear(); 6748 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 6749 ie = Features.end(); it != ie; ++it) 6750 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 6751 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 6752 return nullptr; 6753 6754 return Target.release(); 6755 } 6756