1*2874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2c827ac45SSimon Guo /* 3c827ac45SSimon Guo * Copyright 2009 Freescale Semiconductor, Inc. 4c827ac45SSimon Guo * 5c827ac45SSimon Guo * provides masks and opcode images for use by code generation, emulation 6c827ac45SSimon Guo * and for instructions that older assemblers might not know about 7c827ac45SSimon Guo */ 8c827ac45SSimon Guo #ifndef _ASM_POWERPC_PPC_OPCODE_H 9c827ac45SSimon Guo #define _ASM_POWERPC_PPC_OPCODE_H 10c827ac45SSimon Guo 11c827ac45SSimon Guo 12c827ac45SSimon Guo # define stringify_in_c(...) __VA_ARGS__ 13c827ac45SSimon Guo # define ASM_CONST(x) x 14c827ac45SSimon Guo 15c827ac45SSimon Guo 16c827ac45SSimon Guo #define PPC_INST_VCMPEQUD_RC 0x100000c7 17c827ac45SSimon Guo #define PPC_INST_VCMPEQUB_RC 0x10000006 18c827ac45SSimon Guo 19c827ac45SSimon Guo #define __PPC_RC21 (0x1 << 10) 20c827ac45SSimon Guo 21c827ac45SSimon Guo /* macros to insert fields into opcodes */ 22c827ac45SSimon Guo #define ___PPC_RA(a) (((a) & 0x1f) << 16) 23c827ac45SSimon Guo #define ___PPC_RB(b) (((b) & 0x1f) << 11) 24c827ac45SSimon Guo #define ___PPC_RS(s) (((s) & 0x1f) << 21) 25c827ac45SSimon Guo #define ___PPC_RT(t) ___PPC_RS(t) 26c827ac45SSimon Guo 27c827ac45SSimon Guo #define VCMPEQUD_RC(vrt, vra, vrb) stringify_in_c(.long PPC_INST_VCMPEQUD_RC | \ 28c827ac45SSimon Guo ___PPC_RT(vrt) | ___PPC_RA(vra) | \ 29c827ac45SSimon Guo ___PPC_RB(vrb) | __PPC_RC21) 30c827ac45SSimon Guo 31c827ac45SSimon Guo #define VCMPEQUB_RC(vrt, vra, vrb) stringify_in_c(.long PPC_INST_VCMPEQUB_RC | \ 32c827ac45SSimon Guo ___PPC_RT(vrt) | ___PPC_RA(vra) | \ 33c827ac45SSimon Guo ___PPC_RB(vrb) | __PPC_RC21) 34c827ac45SSimon Guo 35c827ac45SSimon Guo #endif /* _ASM_POWERPC_PPC_OPCODE_H */ 36