1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Performance events: 4 * 5 * Copyright (C) 2008-2009, Thomas Gleixner <[email protected]> 6 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 7 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 8 * 9 * Data type definitions, declarations, prototypes. 10 * 11 * Started by: Thomas Gleixner and Ingo Molnar 12 * 13 * For licencing details see kernel-base/COPYING 14 */ 15 #ifndef _UAPI_LINUX_PERF_EVENT_H 16 #define _UAPI_LINUX_PERF_EVENT_H 17 18 #include <linux/types.h> 19 #include <linux/ioctl.h> 20 #include <asm/byteorder.h> 21 22 /* 23 * User-space ABI bits: 24 */ 25 26 /* 27 * attr.type 28 */ 29 enum perf_type_id { 30 PERF_TYPE_HARDWARE = 0, 31 PERF_TYPE_SOFTWARE = 1, 32 PERF_TYPE_TRACEPOINT = 2, 33 PERF_TYPE_HW_CACHE = 3, 34 PERF_TYPE_RAW = 4, 35 PERF_TYPE_BREAKPOINT = 5, 36 37 PERF_TYPE_MAX, /* non-ABI */ 38 }; 39 40 /* 41 * attr.config layout for type PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE 42 * PERF_TYPE_HARDWARE: 0xEEEEEEEE000000AA 43 * AA: hardware event ID 44 * EEEEEEEE: PMU type ID 45 * PERF_TYPE_HW_CACHE: 0xEEEEEEEE00DDCCBB 46 * BB: hardware cache ID 47 * CC: hardware cache op ID 48 * DD: hardware cache op result ID 49 * EEEEEEEE: PMU type ID 50 * If the PMU type ID is 0, the PERF_TYPE_RAW will be applied. 51 */ 52 #define PERF_PMU_TYPE_SHIFT 32 53 #define PERF_HW_EVENT_MASK 0xffffffff 54 55 /* 56 * Generalized performance event event_id types, used by the 57 * attr.event_id parameter of the sys_perf_event_open() 58 * syscall: 59 */ 60 enum perf_hw_id { 61 /* 62 * Common hardware events, generalized by the kernel: 63 */ 64 PERF_COUNT_HW_CPU_CYCLES = 0, 65 PERF_COUNT_HW_INSTRUCTIONS = 1, 66 PERF_COUNT_HW_CACHE_REFERENCES = 2, 67 PERF_COUNT_HW_CACHE_MISSES = 3, 68 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 69 PERF_COUNT_HW_BRANCH_MISSES = 5, 70 PERF_COUNT_HW_BUS_CYCLES = 6, 71 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 72 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 73 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 74 75 PERF_COUNT_HW_MAX, /* non-ABI */ 76 }; 77 78 /* 79 * Generalized hardware cache events: 80 * 81 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 82 * { read, write, prefetch } x 83 * { accesses, misses } 84 */ 85 enum perf_hw_cache_id { 86 PERF_COUNT_HW_CACHE_L1D = 0, 87 PERF_COUNT_HW_CACHE_L1I = 1, 88 PERF_COUNT_HW_CACHE_LL = 2, 89 PERF_COUNT_HW_CACHE_DTLB = 3, 90 PERF_COUNT_HW_CACHE_ITLB = 4, 91 PERF_COUNT_HW_CACHE_BPU = 5, 92 PERF_COUNT_HW_CACHE_NODE = 6, 93 94 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 95 }; 96 97 enum perf_hw_cache_op_id { 98 PERF_COUNT_HW_CACHE_OP_READ = 0, 99 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 100 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 101 102 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 103 }; 104 105 enum perf_hw_cache_op_result_id { 106 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 107 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 108 109 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 110 }; 111 112 /* 113 * Special "software" events provided by the kernel, even if the hardware 114 * does not support performance events. These events measure various 115 * physical and sw events of the kernel (and allow the profiling of them as 116 * well): 117 */ 118 enum perf_sw_ids { 119 PERF_COUNT_SW_CPU_CLOCK = 0, 120 PERF_COUNT_SW_TASK_CLOCK = 1, 121 PERF_COUNT_SW_PAGE_FAULTS = 2, 122 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 123 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 124 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 125 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 126 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 127 PERF_COUNT_SW_EMULATION_FAULTS = 8, 128 PERF_COUNT_SW_DUMMY = 9, 129 PERF_COUNT_SW_BPF_OUTPUT = 10, 130 PERF_COUNT_SW_CGROUP_SWITCHES = 11, 131 132 PERF_COUNT_SW_MAX, /* non-ABI */ 133 }; 134 135 /* 136 * Bits that can be set in attr.sample_type to request information 137 * in the overflow packets. 138 */ 139 enum perf_event_sample_format { 140 PERF_SAMPLE_IP = 1U << 0, 141 PERF_SAMPLE_TID = 1U << 1, 142 PERF_SAMPLE_TIME = 1U << 2, 143 PERF_SAMPLE_ADDR = 1U << 3, 144 PERF_SAMPLE_READ = 1U << 4, 145 PERF_SAMPLE_CALLCHAIN = 1U << 5, 146 PERF_SAMPLE_ID = 1U << 6, 147 PERF_SAMPLE_CPU = 1U << 7, 148 PERF_SAMPLE_PERIOD = 1U << 8, 149 PERF_SAMPLE_STREAM_ID = 1U << 9, 150 PERF_SAMPLE_RAW = 1U << 10, 151 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 152 PERF_SAMPLE_REGS_USER = 1U << 12, 153 PERF_SAMPLE_STACK_USER = 1U << 13, 154 PERF_SAMPLE_WEIGHT = 1U << 14, 155 PERF_SAMPLE_DATA_SRC = 1U << 15, 156 PERF_SAMPLE_IDENTIFIER = 1U << 16, 157 PERF_SAMPLE_TRANSACTION = 1U << 17, 158 PERF_SAMPLE_REGS_INTR = 1U << 18, 159 PERF_SAMPLE_PHYS_ADDR = 1U << 19, 160 PERF_SAMPLE_AUX = 1U << 20, 161 PERF_SAMPLE_CGROUP = 1U << 21, 162 PERF_SAMPLE_DATA_PAGE_SIZE = 1U << 22, 163 PERF_SAMPLE_CODE_PAGE_SIZE = 1U << 23, 164 PERF_SAMPLE_WEIGHT_STRUCT = 1U << 24, 165 166 PERF_SAMPLE_MAX = 1U << 25, /* non-ABI */ 167 168 __PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, /* non-ABI; internal use */ 169 }; 170 171 #define PERF_SAMPLE_WEIGHT_TYPE (PERF_SAMPLE_WEIGHT | PERF_SAMPLE_WEIGHT_STRUCT) 172 /* 173 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set 174 * 175 * If the user does not pass priv level information via branch_sample_type, 176 * the kernel uses the event's priv level. Branch and event priv levels do 177 * not have to match. Branch priv level is checked for permissions. 178 * 179 * The branch types can be combined, however BRANCH_ANY covers all types 180 * of branches and therefore it supersedes all the other types. 181 */ 182 enum perf_branch_sample_type_shift { 183 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ 184 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ 185 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ 186 187 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ 188 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ 189 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ 190 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ 191 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ 192 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ 193 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ 194 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ 195 196 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */ 197 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */ 198 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */ 199 200 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */ 201 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */ 202 203 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */ 204 205 PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17, /* save low level index of raw branch records */ 206 207 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ 208 }; 209 210 enum perf_branch_sample_type { 211 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 212 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 213 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 214 215 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 216 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 217 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 218 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 219 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 220 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 221 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 222 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 223 224 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 225 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, 226 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 227 228 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, 229 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 230 231 PERF_SAMPLE_BRANCH_TYPE_SAVE = 232 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, 233 234 PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT, 235 236 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 237 }; 238 239 /* 240 * Common flow change classification 241 */ 242 enum { 243 PERF_BR_UNKNOWN = 0, /* unknown */ 244 PERF_BR_COND = 1, /* conditional */ 245 PERF_BR_UNCOND = 2, /* unconditional */ 246 PERF_BR_IND = 3, /* indirect */ 247 PERF_BR_CALL = 4, /* function call */ 248 PERF_BR_IND_CALL = 5, /* indirect function call */ 249 PERF_BR_RET = 6, /* function return */ 250 PERF_BR_SYSCALL = 7, /* syscall */ 251 PERF_BR_SYSRET = 8, /* syscall return */ 252 PERF_BR_COND_CALL = 9, /* conditional function call */ 253 PERF_BR_COND_RET = 10, /* conditional function return */ 254 PERF_BR_ERET = 11, /* exception return */ 255 PERF_BR_IRQ = 12, /* irq */ 256 PERF_BR_SERROR = 13, /* system error */ 257 PERF_BR_NO_TX = 14, /* not in transaction */ 258 PERF_BR_EXTEND_ABI = 15, /* extend ABI */ 259 PERF_BR_MAX, 260 }; 261 262 enum { 263 PERF_BR_NEW_FAULT_ALGN = 0, /* Alignment fault */ 264 PERF_BR_NEW_FAULT_DATA = 1, /* Data fault */ 265 PERF_BR_NEW_FAULT_INST = 2, /* Inst fault */ 266 PERF_BR_NEW_ARCH_1 = 3, /* Architecture specific */ 267 PERF_BR_NEW_ARCH_2 = 4, /* Architecture specific */ 268 PERF_BR_NEW_ARCH_3 = 5, /* Architecture specific */ 269 PERF_BR_NEW_ARCH_4 = 6, /* Architecture specific */ 270 PERF_BR_NEW_ARCH_5 = 7, /* Architecture specific */ 271 PERF_BR_NEW_MAX, 272 }; 273 274 #define PERF_SAMPLE_BRANCH_PLM_ALL \ 275 (PERF_SAMPLE_BRANCH_USER|\ 276 PERF_SAMPLE_BRANCH_KERNEL|\ 277 PERF_SAMPLE_BRANCH_HV) 278 279 /* 280 * Values to determine ABI of the registers dump. 281 */ 282 enum perf_sample_regs_abi { 283 PERF_SAMPLE_REGS_ABI_NONE = 0, 284 PERF_SAMPLE_REGS_ABI_32 = 1, 285 PERF_SAMPLE_REGS_ABI_64 = 2, 286 }; 287 288 /* 289 * Values for the memory transaction event qualifier, mostly for 290 * abort events. Multiple bits can be set. 291 */ 292 enum { 293 PERF_TXN_ELISION = (1 << 0), /* From elision */ 294 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ 295 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ 296 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ 297 PERF_TXN_RETRY = (1 << 4), /* Retry possible */ 298 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ 299 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ 300 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ 301 302 PERF_TXN_MAX = (1 << 8), /* non-ABI */ 303 304 /* bits 32..63 are reserved for the abort code */ 305 306 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 307 PERF_TXN_ABORT_SHIFT = 32, 308 }; 309 310 /* 311 * The format of the data returned by read() on a perf event fd, 312 * as specified by attr.read_format: 313 * 314 * struct read_format { 315 * { u64 value; 316 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 317 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 318 * { u64 id; } && PERF_FORMAT_ID 319 * { u64 lost; } && PERF_FORMAT_LOST 320 * } && !PERF_FORMAT_GROUP 321 * 322 * { u64 nr; 323 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 324 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 325 * { u64 value; 326 * { u64 id; } && PERF_FORMAT_ID 327 * { u64 lost; } && PERF_FORMAT_LOST 328 * } cntr[nr]; 329 * } && PERF_FORMAT_GROUP 330 * }; 331 */ 332 enum perf_event_read_format { 333 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 334 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 335 PERF_FORMAT_ID = 1U << 2, 336 PERF_FORMAT_GROUP = 1U << 3, 337 PERF_FORMAT_LOST = 1U << 4, 338 339 PERF_FORMAT_MAX = 1U << 5, /* non-ABI */ 340 }; 341 342 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ 343 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ 344 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ 345 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ 346 /* add: sample_stack_user */ 347 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ 348 #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ 349 #define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ 350 #define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */ 351 352 /* 353 * Hardware event_id to monitor via a performance monitoring event: 354 * 355 * @sample_max_stack: Max number of frame pointers in a callchain, 356 * should be < /proc/sys/kernel/perf_event_max_stack 357 */ 358 struct perf_event_attr { 359 360 /* 361 * Major type: hardware/software/tracepoint/etc. 362 */ 363 __u32 type; 364 365 /* 366 * Size of the attr structure, for fwd/bwd compat. 367 */ 368 __u32 size; 369 370 /* 371 * Type specific configuration information. 372 */ 373 __u64 config; 374 375 union { 376 __u64 sample_period; 377 __u64 sample_freq; 378 }; 379 380 __u64 sample_type; 381 __u64 read_format; 382 383 __u64 disabled : 1, /* off by default */ 384 inherit : 1, /* children inherit it */ 385 pinned : 1, /* must always be on PMU */ 386 exclusive : 1, /* only group on PMU */ 387 exclude_user : 1, /* don't count user */ 388 exclude_kernel : 1, /* ditto kernel */ 389 exclude_hv : 1, /* ditto hypervisor */ 390 exclude_idle : 1, /* don't count when idle */ 391 mmap : 1, /* include mmap data */ 392 comm : 1, /* include comm data */ 393 freq : 1, /* use freq, not period */ 394 inherit_stat : 1, /* per task counts */ 395 enable_on_exec : 1, /* next exec enables */ 396 task : 1, /* trace fork/exit */ 397 watermark : 1, /* wakeup_watermark */ 398 /* 399 * precise_ip: 400 * 401 * 0 - SAMPLE_IP can have arbitrary skid 402 * 1 - SAMPLE_IP must have constant skid 403 * 2 - SAMPLE_IP requested to have 0 skid 404 * 3 - SAMPLE_IP must have 0 skid 405 * 406 * See also PERF_RECORD_MISC_EXACT_IP 407 */ 408 precise_ip : 2, /* skid constraint */ 409 mmap_data : 1, /* non-exec mmap data */ 410 sample_id_all : 1, /* sample_type all events */ 411 412 exclude_host : 1, /* don't count in host */ 413 exclude_guest : 1, /* don't count in guest */ 414 415 exclude_callchain_kernel : 1, /* exclude kernel callchains */ 416 exclude_callchain_user : 1, /* exclude user callchains */ 417 mmap2 : 1, /* include mmap with inode data */ 418 comm_exec : 1, /* flag comm events that are due to an exec */ 419 use_clockid : 1, /* use @clockid for time fields */ 420 context_switch : 1, /* context switch data */ 421 write_backward : 1, /* Write ring buffer from end to beginning */ 422 namespaces : 1, /* include namespaces data */ 423 ksymbol : 1, /* include ksymbol events */ 424 bpf_event : 1, /* include bpf events */ 425 aux_output : 1, /* generate AUX records instead of events */ 426 cgroup : 1, /* include cgroup events */ 427 text_poke : 1, /* include text poke events */ 428 build_id : 1, /* use build id in mmap2 events */ 429 inherit_thread : 1, /* children only inherit if cloned with CLONE_THREAD */ 430 remove_on_exec : 1, /* event is removed from task on exec */ 431 sigtrap : 1, /* send synchronous SIGTRAP on event */ 432 __reserved_1 : 26; 433 434 union { 435 __u32 wakeup_events; /* wakeup every n events */ 436 __u32 wakeup_watermark; /* bytes before wakeup */ 437 }; 438 439 __u32 bp_type; 440 union { 441 __u64 bp_addr; 442 __u64 kprobe_func; /* for perf_kprobe */ 443 __u64 uprobe_path; /* for perf_uprobe */ 444 __u64 config1; /* extension of config */ 445 }; 446 union { 447 __u64 bp_len; 448 __u64 kprobe_addr; /* when kprobe_func == NULL */ 449 __u64 probe_offset; /* for perf_[k,u]probe */ 450 __u64 config2; /* extension of config1 */ 451 }; 452 __u64 branch_sample_type; /* enum perf_branch_sample_type */ 453 454 /* 455 * Defines set of user regs to dump on samples. 456 * See asm/perf_regs.h for details. 457 */ 458 __u64 sample_regs_user; 459 460 /* 461 * Defines size of the user stack to dump on samples. 462 */ 463 __u32 sample_stack_user; 464 465 __s32 clockid; 466 /* 467 * Defines set of regs to dump for each sample 468 * state captured on: 469 * - precise = 0: PMU interrupt 470 * - precise > 0: sampled instruction 471 * 472 * See asm/perf_regs.h for details. 473 */ 474 __u64 sample_regs_intr; 475 476 /* 477 * Wakeup watermark for AUX area 478 */ 479 __u32 aux_watermark; 480 __u16 sample_max_stack; 481 __u16 __reserved_2; 482 __u32 aux_sample_size; 483 __u32 __reserved_3; 484 485 /* 486 * User provided data if sigtrap=1, passed back to user via 487 * siginfo_t::si_perf_data, e.g. to permit user to identify the event. 488 * Note, siginfo_t::si_perf_data is long-sized, and sig_data will be 489 * truncated accordingly on 32 bit architectures. 490 */ 491 __u64 sig_data; 492 }; 493 494 /* 495 * Structure used by below PERF_EVENT_IOC_QUERY_BPF command 496 * to query bpf programs attached to the same perf tracepoint 497 * as the given perf event. 498 */ 499 struct perf_event_query_bpf { 500 /* 501 * The below ids array length 502 */ 503 __u32 ids_len; 504 /* 505 * Set by the kernel to indicate the number of 506 * available programs 507 */ 508 __u32 prog_cnt; 509 /* 510 * User provided buffer to store program ids 511 */ 512 __u32 ids[]; 513 }; 514 515 /* 516 * Ioctls that can be done on a perf event fd: 517 */ 518 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 519 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 520 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 521 #define PERF_EVENT_IOC_RESET _IO ('$', 3) 522 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 523 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 524 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 525 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 526 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) 527 #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) 528 #define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) 529 #define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *) 530 531 enum perf_event_ioc_flags { 532 PERF_IOC_FLAG_GROUP = 1U << 0, 533 }; 534 535 /* 536 * Structure of the page that can be mapped via mmap 537 */ 538 struct perf_event_mmap_page { 539 __u32 version; /* version number of this structure */ 540 __u32 compat_version; /* lowest version this is compat with */ 541 542 /* 543 * Bits needed to read the hw events in user-space. 544 * 545 * u32 seq, time_mult, time_shift, index, width; 546 * u64 count, enabled, running; 547 * u64 cyc, time_offset; 548 * s64 pmc = 0; 549 * 550 * do { 551 * seq = pc->lock; 552 * barrier() 553 * 554 * enabled = pc->time_enabled; 555 * running = pc->time_running; 556 * 557 * if (pc->cap_usr_time && enabled != running) { 558 * cyc = rdtsc(); 559 * time_offset = pc->time_offset; 560 * time_mult = pc->time_mult; 561 * time_shift = pc->time_shift; 562 * } 563 * 564 * index = pc->index; 565 * count = pc->offset; 566 * if (pc->cap_user_rdpmc && index) { 567 * width = pc->pmc_width; 568 * pmc = rdpmc(index - 1); 569 * } 570 * 571 * barrier(); 572 * } while (pc->lock != seq); 573 * 574 * NOTE: for obvious reason this only works on self-monitoring 575 * processes. 576 */ 577 __u32 lock; /* seqlock for synchronization */ 578 __u32 index; /* hardware event identifier */ 579 __s64 offset; /* add to hardware event value */ 580 __u64 time_enabled; /* time event active */ 581 __u64 time_running; /* time event on cpu */ 582 union { 583 __u64 capabilities; 584 struct { 585 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ 586 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ 587 588 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ 589 cap_user_time : 1, /* The time_{shift,mult,offset} fields are used */ 590 cap_user_time_zero : 1, /* The time_zero field is used */ 591 cap_user_time_short : 1, /* the time_{cycle,mask} fields are used */ 592 cap_____res : 58; 593 }; 594 }; 595 596 /* 597 * If cap_user_rdpmc this field provides the bit-width of the value 598 * read using the rdpmc() or equivalent instruction. This can be used 599 * to sign extend the result like: 600 * 601 * pmc <<= 64 - width; 602 * pmc >>= 64 - width; // signed shift right 603 * count += pmc; 604 */ 605 __u16 pmc_width; 606 607 /* 608 * If cap_usr_time the below fields can be used to compute the time 609 * delta since time_enabled (in ns) using rdtsc or similar. 610 * 611 * u64 quot, rem; 612 * u64 delta; 613 * 614 * quot = (cyc >> time_shift); 615 * rem = cyc & (((u64)1 << time_shift) - 1); 616 * delta = time_offset + quot * time_mult + 617 * ((rem * time_mult) >> time_shift); 618 * 619 * Where time_offset,time_mult,time_shift and cyc are read in the 620 * seqcount loop described above. This delta can then be added to 621 * enabled and possible running (if index), improving the scaling: 622 * 623 * enabled += delta; 624 * if (index) 625 * running += delta; 626 * 627 * quot = count / running; 628 * rem = count % running; 629 * count = quot * enabled + (rem * enabled) / running; 630 */ 631 __u16 time_shift; 632 __u32 time_mult; 633 __u64 time_offset; 634 /* 635 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated 636 * from sample timestamps. 637 * 638 * time = timestamp - time_zero; 639 * quot = time / time_mult; 640 * rem = time % time_mult; 641 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; 642 * 643 * And vice versa: 644 * 645 * quot = cyc >> time_shift; 646 * rem = cyc & (((u64)1 << time_shift) - 1); 647 * timestamp = time_zero + quot * time_mult + 648 * ((rem * time_mult) >> time_shift); 649 */ 650 __u64 time_zero; 651 652 __u32 size; /* Header size up to __reserved[] fields. */ 653 __u32 __reserved_1; 654 655 /* 656 * If cap_usr_time_short, the hardware clock is less than 64bit wide 657 * and we must compute the 'cyc' value, as used by cap_usr_time, as: 658 * 659 * cyc = time_cycles + ((cyc - time_cycles) & time_mask) 660 * 661 * NOTE: this form is explicitly chosen such that cap_usr_time_short 662 * is a correction on top of cap_usr_time, and code that doesn't 663 * know about cap_usr_time_short still works under the assumption 664 * the counter doesn't wrap. 665 */ 666 __u64 time_cycles; 667 __u64 time_mask; 668 669 /* 670 * Hole for extension of the self monitor capabilities 671 */ 672 673 __u8 __reserved[116*8]; /* align to 1k. */ 674 675 /* 676 * Control data for the mmap() data buffer. 677 * 678 * User-space reading the @data_head value should issue an smp_rmb(), 679 * after reading this value. 680 * 681 * When the mapping is PROT_WRITE the @data_tail value should be 682 * written by userspace to reflect the last read data, after issueing 683 * an smp_mb() to separate the data read from the ->data_tail store. 684 * In this case the kernel will not over-write unread data. 685 * 686 * See perf_output_put_handle() for the data ordering. 687 * 688 * data_{offset,size} indicate the location and size of the perf record 689 * buffer within the mmapped area. 690 */ 691 __u64 data_head; /* head in the data section */ 692 __u64 data_tail; /* user-space written tail */ 693 __u64 data_offset; /* where the buffer starts */ 694 __u64 data_size; /* data buffer size */ 695 696 /* 697 * AUX area is defined by aux_{offset,size} fields that should be set 698 * by the userspace, so that 699 * 700 * aux_offset >= data_offset + data_size 701 * 702 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size. 703 * 704 * Ring buffer pointers aux_{head,tail} have the same semantics as 705 * data_{head,tail} and same ordering rules apply. 706 */ 707 __u64 aux_head; 708 __u64 aux_tail; 709 __u64 aux_offset; 710 __u64 aux_size; 711 }; 712 713 /* 714 * The current state of perf_event_header::misc bits usage: 715 * ('|' used bit, '-' unused bit) 716 * 717 * 012 CDEF 718 * |||---------|||| 719 * 720 * Where: 721 * 0-2 CPUMODE_MASK 722 * 723 * C PROC_MAP_PARSE_TIMEOUT 724 * D MMAP_DATA / COMM_EXEC / FORK_EXEC / SWITCH_OUT 725 * E MMAP_BUILD_ID / EXACT_IP / SCHED_OUT_PREEMPT 726 * F (reserved) 727 */ 728 729 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 730 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 731 #define PERF_RECORD_MISC_KERNEL (1 << 0) 732 #define PERF_RECORD_MISC_USER (2 << 0) 733 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 734 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 735 #define PERF_RECORD_MISC_GUEST_USER (5 << 0) 736 737 /* 738 * Indicates that /proc/PID/maps parsing are truncated by time out. 739 */ 740 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) 741 /* 742 * Following PERF_RECORD_MISC_* are used on different 743 * events, so can reuse the same bit position: 744 * 745 * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events 746 * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event 747 * PERF_RECORD_MISC_FORK_EXEC - PERF_RECORD_FORK event (perf internal) 748 * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events 749 */ 750 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 751 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 752 #define PERF_RECORD_MISC_FORK_EXEC (1 << 13) 753 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) 754 /* 755 * These PERF_RECORD_MISC_* flags below are safely reused 756 * for the following events: 757 * 758 * PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events 759 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events 760 * PERF_RECORD_MISC_MMAP_BUILD_ID - PERF_RECORD_MMAP2 event 761 * 762 * 763 * PERF_RECORD_MISC_EXACT_IP: 764 * Indicates that the content of PERF_SAMPLE_IP points to 765 * the actual instruction that triggered the event. See also 766 * perf_event_attr::precise_ip. 767 * 768 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT: 769 * Indicates that thread was preempted in TASK_RUNNING state. 770 * 771 * PERF_RECORD_MISC_MMAP_BUILD_ID: 772 * Indicates that mmap2 event carries build id data. 773 */ 774 #define PERF_RECORD_MISC_EXACT_IP (1 << 14) 775 #define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14) 776 #define PERF_RECORD_MISC_MMAP_BUILD_ID (1 << 14) 777 /* 778 * Reserve the last bit to indicate some extended misc field 779 */ 780 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 781 782 struct perf_event_header { 783 __u32 type; 784 __u16 misc; 785 __u16 size; 786 }; 787 788 struct perf_ns_link_info { 789 __u64 dev; 790 __u64 ino; 791 }; 792 793 enum { 794 NET_NS_INDEX = 0, 795 UTS_NS_INDEX = 1, 796 IPC_NS_INDEX = 2, 797 PID_NS_INDEX = 3, 798 USER_NS_INDEX = 4, 799 MNT_NS_INDEX = 5, 800 CGROUP_NS_INDEX = 6, 801 802 NR_NAMESPACES, /* number of available namespaces */ 803 }; 804 805 enum perf_event_type { 806 807 /* 808 * If perf_event_attr.sample_id_all is set then all event types will 809 * have the sample_type selected fields related to where/when 810 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, 811 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed 812 * just after the perf_event_header and the fields already present for 813 * the existing fields, i.e. at the end of the payload. That way a newer 814 * perf.data file will be supported by older perf tools, with these new 815 * optional fields being ignored. 816 * 817 * struct sample_id { 818 * { u32 pid, tid; } && PERF_SAMPLE_TID 819 * { u64 time; } && PERF_SAMPLE_TIME 820 * { u64 id; } && PERF_SAMPLE_ID 821 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 822 * { u32 cpu, res; } && PERF_SAMPLE_CPU 823 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 824 * } && perf_event_attr::sample_id_all 825 * 826 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The 827 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed 828 * relative to header.size. 829 */ 830 831 /* 832 * The MMAP events record the PROT_EXEC mappings so that we can 833 * correlate userspace IPs to code. They have the following structure: 834 * 835 * struct { 836 * struct perf_event_header header; 837 * 838 * u32 pid, tid; 839 * u64 addr; 840 * u64 len; 841 * u64 pgoff; 842 * char filename[]; 843 * struct sample_id sample_id; 844 * }; 845 */ 846 PERF_RECORD_MMAP = 1, 847 848 /* 849 * struct { 850 * struct perf_event_header header; 851 * u64 id; 852 * u64 lost; 853 * struct sample_id sample_id; 854 * }; 855 */ 856 PERF_RECORD_LOST = 2, 857 858 /* 859 * struct { 860 * struct perf_event_header header; 861 * 862 * u32 pid, tid; 863 * char comm[]; 864 * struct sample_id sample_id; 865 * }; 866 */ 867 PERF_RECORD_COMM = 3, 868 869 /* 870 * struct { 871 * struct perf_event_header header; 872 * u32 pid, ppid; 873 * u32 tid, ptid; 874 * u64 time; 875 * struct sample_id sample_id; 876 * }; 877 */ 878 PERF_RECORD_EXIT = 4, 879 880 /* 881 * struct { 882 * struct perf_event_header header; 883 * u64 time; 884 * u64 id; 885 * u64 stream_id; 886 * struct sample_id sample_id; 887 * }; 888 */ 889 PERF_RECORD_THROTTLE = 5, 890 PERF_RECORD_UNTHROTTLE = 6, 891 892 /* 893 * struct { 894 * struct perf_event_header header; 895 * u32 pid, ppid; 896 * u32 tid, ptid; 897 * u64 time; 898 * struct sample_id sample_id; 899 * }; 900 */ 901 PERF_RECORD_FORK = 7, 902 903 /* 904 * struct { 905 * struct perf_event_header header; 906 * u32 pid, tid; 907 * 908 * struct read_format values; 909 * struct sample_id sample_id; 910 * }; 911 */ 912 PERF_RECORD_READ = 8, 913 914 /* 915 * struct { 916 * struct perf_event_header header; 917 * 918 * # 919 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. 920 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position 921 * # is fixed relative to header. 922 * # 923 * 924 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 925 * { u64 ip; } && PERF_SAMPLE_IP 926 * { u32 pid, tid; } && PERF_SAMPLE_TID 927 * { u64 time; } && PERF_SAMPLE_TIME 928 * { u64 addr; } && PERF_SAMPLE_ADDR 929 * { u64 id; } && PERF_SAMPLE_ID 930 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 931 * { u32 cpu, res; } && PERF_SAMPLE_CPU 932 * { u64 period; } && PERF_SAMPLE_PERIOD 933 * 934 * { struct read_format values; } && PERF_SAMPLE_READ 935 * 936 * { u64 nr, 937 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 938 * 939 * # 940 * # The RAW record below is opaque data wrt the ABI 941 * # 942 * # That is, the ABI doesn't make any promises wrt to 943 * # the stability of its content, it may vary depending 944 * # on event, hardware, kernel version and phase of 945 * # the moon. 946 * # 947 * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 948 * # 949 * 950 * { u32 size; 951 * char data[size];}&& PERF_SAMPLE_RAW 952 * 953 * { u64 nr; 954 * { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX 955 * { u64 from, to, flags } lbr[nr]; 956 * } && PERF_SAMPLE_BRANCH_STACK 957 * 958 * { u64 abi; # enum perf_sample_regs_abi 959 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER 960 * 961 * { u64 size; 962 * char data[size]; 963 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 964 * 965 * { union perf_sample_weight 966 * { 967 * u64 full; && PERF_SAMPLE_WEIGHT 968 * #if defined(__LITTLE_ENDIAN_BITFIELD) 969 * struct { 970 * u32 var1_dw; 971 * u16 var2_w; 972 * u16 var3_w; 973 * } && PERF_SAMPLE_WEIGHT_STRUCT 974 * #elif defined(__BIG_ENDIAN_BITFIELD) 975 * struct { 976 * u16 var3_w; 977 * u16 var2_w; 978 * u32 var1_dw; 979 * } && PERF_SAMPLE_WEIGHT_STRUCT 980 * #endif 981 * } 982 * } 983 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 984 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION 985 * { u64 abi; # enum perf_sample_regs_abi 986 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR 987 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR 988 * { u64 size; 989 * char data[size]; } && PERF_SAMPLE_AUX 990 * { u64 data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE 991 * { u64 code_page_size;} && PERF_SAMPLE_CODE_PAGE_SIZE 992 * }; 993 */ 994 PERF_RECORD_SAMPLE = 9, 995 996 /* 997 * The MMAP2 records are an augmented version of MMAP, they add 998 * maj, min, ino numbers to be used to uniquely identify each mapping 999 * 1000 * struct { 1001 * struct perf_event_header header; 1002 * 1003 * u32 pid, tid; 1004 * u64 addr; 1005 * u64 len; 1006 * u64 pgoff; 1007 * union { 1008 * struct { 1009 * u32 maj; 1010 * u32 min; 1011 * u64 ino; 1012 * u64 ino_generation; 1013 * }; 1014 * struct { 1015 * u8 build_id_size; 1016 * u8 __reserved_1; 1017 * u16 __reserved_2; 1018 * u8 build_id[20]; 1019 * }; 1020 * }; 1021 * u32 prot, flags; 1022 * char filename[]; 1023 * struct sample_id sample_id; 1024 * }; 1025 */ 1026 PERF_RECORD_MMAP2 = 10, 1027 1028 /* 1029 * Records that new data landed in the AUX buffer part. 1030 * 1031 * struct { 1032 * struct perf_event_header header; 1033 * 1034 * u64 aux_offset; 1035 * u64 aux_size; 1036 * u64 flags; 1037 * struct sample_id sample_id; 1038 * }; 1039 */ 1040 PERF_RECORD_AUX = 11, 1041 1042 /* 1043 * Indicates that instruction trace has started 1044 * 1045 * struct { 1046 * struct perf_event_header header; 1047 * u32 pid; 1048 * u32 tid; 1049 * struct sample_id sample_id; 1050 * }; 1051 */ 1052 PERF_RECORD_ITRACE_START = 12, 1053 1054 /* 1055 * Records the dropped/lost sample number. 1056 * 1057 * struct { 1058 * struct perf_event_header header; 1059 * 1060 * u64 lost; 1061 * struct sample_id sample_id; 1062 * }; 1063 */ 1064 PERF_RECORD_LOST_SAMPLES = 13, 1065 1066 /* 1067 * Records a context switch in or out (flagged by 1068 * PERF_RECORD_MISC_SWITCH_OUT). See also 1069 * PERF_RECORD_SWITCH_CPU_WIDE. 1070 * 1071 * struct { 1072 * struct perf_event_header header; 1073 * struct sample_id sample_id; 1074 * }; 1075 */ 1076 PERF_RECORD_SWITCH = 14, 1077 1078 /* 1079 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and 1080 * next_prev_tid that are the next (switching out) or previous 1081 * (switching in) pid/tid. 1082 * 1083 * struct { 1084 * struct perf_event_header header; 1085 * u32 next_prev_pid; 1086 * u32 next_prev_tid; 1087 * struct sample_id sample_id; 1088 * }; 1089 */ 1090 PERF_RECORD_SWITCH_CPU_WIDE = 15, 1091 1092 /* 1093 * struct { 1094 * struct perf_event_header header; 1095 * u32 pid; 1096 * u32 tid; 1097 * u64 nr_namespaces; 1098 * { u64 dev, inode; } [nr_namespaces]; 1099 * struct sample_id sample_id; 1100 * }; 1101 */ 1102 PERF_RECORD_NAMESPACES = 16, 1103 1104 /* 1105 * Record ksymbol register/unregister events: 1106 * 1107 * struct { 1108 * struct perf_event_header header; 1109 * u64 addr; 1110 * u32 len; 1111 * u16 ksym_type; 1112 * u16 flags; 1113 * char name[]; 1114 * struct sample_id sample_id; 1115 * }; 1116 */ 1117 PERF_RECORD_KSYMBOL = 17, 1118 1119 /* 1120 * Record bpf events: 1121 * enum perf_bpf_event_type { 1122 * PERF_BPF_EVENT_UNKNOWN = 0, 1123 * PERF_BPF_EVENT_PROG_LOAD = 1, 1124 * PERF_BPF_EVENT_PROG_UNLOAD = 2, 1125 * }; 1126 * 1127 * struct { 1128 * struct perf_event_header header; 1129 * u16 type; 1130 * u16 flags; 1131 * u32 id; 1132 * u8 tag[BPF_TAG_SIZE]; 1133 * struct sample_id sample_id; 1134 * }; 1135 */ 1136 PERF_RECORD_BPF_EVENT = 18, 1137 1138 /* 1139 * struct { 1140 * struct perf_event_header header; 1141 * u64 id; 1142 * char path[]; 1143 * struct sample_id sample_id; 1144 * }; 1145 */ 1146 PERF_RECORD_CGROUP = 19, 1147 1148 /* 1149 * Records changes to kernel text i.e. self-modified code. 'old_len' is 1150 * the number of old bytes, 'new_len' is the number of new bytes. Either 1151 * 'old_len' or 'new_len' may be zero to indicate, for example, the 1152 * addition or removal of a trampoline. 'bytes' contains the old bytes 1153 * followed immediately by the new bytes. 1154 * 1155 * struct { 1156 * struct perf_event_header header; 1157 * u64 addr; 1158 * u16 old_len; 1159 * u16 new_len; 1160 * u8 bytes[]; 1161 * struct sample_id sample_id; 1162 * }; 1163 */ 1164 PERF_RECORD_TEXT_POKE = 20, 1165 1166 /* 1167 * Data written to the AUX area by hardware due to aux_output, may need 1168 * to be matched to the event by an architecture-specific hardware ID. 1169 * This records the hardware ID, but requires sample_id to provide the 1170 * event ID. e.g. Intel PT uses this record to disambiguate PEBS-via-PT 1171 * records from multiple events. 1172 * 1173 * struct { 1174 * struct perf_event_header header; 1175 * u64 hw_id; 1176 * struct sample_id sample_id; 1177 * }; 1178 */ 1179 PERF_RECORD_AUX_OUTPUT_HW_ID = 21, 1180 1181 PERF_RECORD_MAX, /* non-ABI */ 1182 }; 1183 1184 enum perf_record_ksymbol_type { 1185 PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0, 1186 PERF_RECORD_KSYMBOL_TYPE_BPF = 1, 1187 /* 1188 * Out of line code such as kprobe-replaced instructions or optimized 1189 * kprobes or ftrace trampolines. 1190 */ 1191 PERF_RECORD_KSYMBOL_TYPE_OOL = 2, 1192 PERF_RECORD_KSYMBOL_TYPE_MAX /* non-ABI */ 1193 }; 1194 1195 #define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0) 1196 1197 enum perf_bpf_event_type { 1198 PERF_BPF_EVENT_UNKNOWN = 0, 1199 PERF_BPF_EVENT_PROG_LOAD = 1, 1200 PERF_BPF_EVENT_PROG_UNLOAD = 2, 1201 PERF_BPF_EVENT_MAX, /* non-ABI */ 1202 }; 1203 1204 #define PERF_MAX_STACK_DEPTH 127 1205 #define PERF_MAX_CONTEXTS_PER_STACK 8 1206 1207 enum perf_callchain_context { 1208 PERF_CONTEXT_HV = (__u64)-32, 1209 PERF_CONTEXT_KERNEL = (__u64)-128, 1210 PERF_CONTEXT_USER = (__u64)-512, 1211 1212 PERF_CONTEXT_GUEST = (__u64)-2048, 1213 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 1214 PERF_CONTEXT_GUEST_USER = (__u64)-2560, 1215 1216 PERF_CONTEXT_MAX = (__u64)-4095, 1217 }; 1218 1219 /** 1220 * PERF_RECORD_AUX::flags bits 1221 */ 1222 #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ 1223 #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ 1224 #define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ 1225 #define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ 1226 #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */ 1227 1228 /* CoreSight PMU AUX buffer formats */ 1229 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */ 1230 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format of the source */ 1231 1232 #define PERF_FLAG_FD_NO_GROUP (1UL << 0) 1233 #define PERF_FLAG_FD_OUTPUT (1UL << 1) 1234 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ 1235 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ 1236 1237 #if defined(__LITTLE_ENDIAN_BITFIELD) 1238 union perf_mem_data_src { 1239 __u64 val; 1240 struct { 1241 __u64 mem_op:5, /* type of opcode */ 1242 mem_lvl:14, /* memory hierarchy level */ 1243 mem_snoop:5, /* snoop mode */ 1244 mem_lock:2, /* lock instr */ 1245 mem_dtlb:7, /* tlb access */ 1246 mem_lvl_num:4, /* memory hierarchy level number */ 1247 mem_remote:1, /* remote */ 1248 mem_snoopx:2, /* snoop mode, ext */ 1249 mem_blk:3, /* access blocked */ 1250 mem_hops:3, /* hop level */ 1251 mem_rsvd:18; 1252 }; 1253 }; 1254 #elif defined(__BIG_ENDIAN_BITFIELD) 1255 union perf_mem_data_src { 1256 __u64 val; 1257 struct { 1258 __u64 mem_rsvd:18, 1259 mem_hops:3, /* hop level */ 1260 mem_blk:3, /* access blocked */ 1261 mem_snoopx:2, /* snoop mode, ext */ 1262 mem_remote:1, /* remote */ 1263 mem_lvl_num:4, /* memory hierarchy level number */ 1264 mem_dtlb:7, /* tlb access */ 1265 mem_lock:2, /* lock instr */ 1266 mem_snoop:5, /* snoop mode */ 1267 mem_lvl:14, /* memory hierarchy level */ 1268 mem_op:5; /* type of opcode */ 1269 }; 1270 }; 1271 #else 1272 #error "Unknown endianness" 1273 #endif 1274 1275 /* type of opcode (load/store/prefetch,code) */ 1276 #define PERF_MEM_OP_NA 0x01 /* not available */ 1277 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */ 1278 #define PERF_MEM_OP_STORE 0x04 /* store instruction */ 1279 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ 1280 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ 1281 #define PERF_MEM_OP_SHIFT 0 1282 1283 /* 1284 * PERF_MEM_LVL_* namespace being depricated to some extent in the 1285 * favour of newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_} fields. 1286 * Supporting this namespace inorder to not break defined ABIs. 1287 * 1288 * memory hierarchy (memory level, hit or miss) 1289 */ 1290 #define PERF_MEM_LVL_NA 0x01 /* not available */ 1291 #define PERF_MEM_LVL_HIT 0x02 /* hit level */ 1292 #define PERF_MEM_LVL_MISS 0x04 /* miss level */ 1293 #define PERF_MEM_LVL_L1 0x08 /* L1 */ 1294 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ 1295 #define PERF_MEM_LVL_L2 0x20 /* L2 */ 1296 #define PERF_MEM_LVL_L3 0x40 /* L3 */ 1297 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ 1298 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ 1299 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ 1300 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ 1301 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ 1302 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 1303 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 1304 #define PERF_MEM_LVL_SHIFT 5 1305 1306 #define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */ 1307 #define PERF_MEM_REMOTE_SHIFT 37 1308 1309 #define PERF_MEM_LVLNUM_L1 0x01 /* L1 */ 1310 #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ 1311 #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ 1312 #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ 1313 /* 5-0xa available */ 1314 #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ 1315 #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ 1316 #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ 1317 #define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */ 1318 #define PERF_MEM_LVLNUM_NA 0x0f /* N/A */ 1319 1320 #define PERF_MEM_LVLNUM_SHIFT 33 1321 1322 /* snoop mode */ 1323 #define PERF_MEM_SNOOP_NA 0x01 /* not available */ 1324 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ 1325 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ 1326 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ 1327 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ 1328 #define PERF_MEM_SNOOP_SHIFT 19 1329 1330 #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ 1331 #define PERF_MEM_SNOOPX_PEER 0x02 /* xfer from peer */ 1332 #define PERF_MEM_SNOOPX_SHIFT 38 1333 1334 /* locked instruction */ 1335 #define PERF_MEM_LOCK_NA 0x01 /* not available */ 1336 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ 1337 #define PERF_MEM_LOCK_SHIFT 24 1338 1339 /* TLB access */ 1340 #define PERF_MEM_TLB_NA 0x01 /* not available */ 1341 #define PERF_MEM_TLB_HIT 0x02 /* hit level */ 1342 #define PERF_MEM_TLB_MISS 0x04 /* miss level */ 1343 #define PERF_MEM_TLB_L1 0x08 /* L1 */ 1344 #define PERF_MEM_TLB_L2 0x10 /* L2 */ 1345 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ 1346 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ 1347 #define PERF_MEM_TLB_SHIFT 26 1348 1349 /* Access blocked */ 1350 #define PERF_MEM_BLK_NA 0x01 /* not available */ 1351 #define PERF_MEM_BLK_DATA 0x02 /* data could not be forwarded */ 1352 #define PERF_MEM_BLK_ADDR 0x04 /* address conflict */ 1353 #define PERF_MEM_BLK_SHIFT 40 1354 1355 /* hop level */ 1356 #define PERF_MEM_HOPS_0 0x01 /* remote core, same node */ 1357 #define PERF_MEM_HOPS_1 0x02 /* remote node, same socket */ 1358 #define PERF_MEM_HOPS_2 0x03 /* remote socket, same board */ 1359 #define PERF_MEM_HOPS_3 0x04 /* remote board */ 1360 /* 5-7 available */ 1361 #define PERF_MEM_HOPS_SHIFT 43 1362 1363 #define PERF_MEM_S(a, s) \ 1364 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 1365 1366 /* 1367 * single taken branch record layout: 1368 * 1369 * from: source instruction (may not always be a branch insn) 1370 * to: branch target 1371 * mispred: branch target was mispredicted 1372 * predicted: branch target was predicted 1373 * 1374 * support for mispred, predicted is optional. In case it 1375 * is not supported mispred = predicted = 0. 1376 * 1377 * in_tx: running in a hardware transaction 1378 * abort: aborting a hardware transaction 1379 * cycles: cycles from last branch (or 0 if not supported) 1380 * type: branch type 1381 */ 1382 struct perf_branch_entry { 1383 __u64 from; 1384 __u64 to; 1385 __u64 mispred:1, /* target mispredicted */ 1386 predicted:1,/* target predicted */ 1387 in_tx:1, /* in transaction */ 1388 abort:1, /* transaction abort */ 1389 cycles:16, /* cycle count to last branch */ 1390 type:4, /* branch type */ 1391 new_type:4, /* additional branch type */ 1392 reserved:36; 1393 }; 1394 1395 union perf_sample_weight { 1396 __u64 full; 1397 #if defined(__LITTLE_ENDIAN_BITFIELD) 1398 struct { 1399 __u32 var1_dw; 1400 __u16 var2_w; 1401 __u16 var3_w; 1402 }; 1403 #elif defined(__BIG_ENDIAN_BITFIELD) 1404 struct { 1405 __u16 var3_w; 1406 __u16 var2_w; 1407 __u32 var1_dw; 1408 }; 1409 #else 1410 #error "Unknown endianness" 1411 #endif 1412 }; 1413 1414 #endif /* _UAPI_LINUX_PERF_EVENT_H */ 1415