1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 // 8 // Authors: Vijendar Mukunda <[email protected]> 9 // Ajit Kumar Pandey <[email protected]> 10 11 /* 12 * Hardware interface for generic AMD ACP processor 13 */ 14 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/pci.h> 18 19 #include <asm/amd_node.h> 20 21 #include "../ops.h" 22 #include "acp.h" 23 #include "acp-dsp-offset.h" 24 25 static bool enable_fw_debug; 26 module_param(enable_fw_debug, bool, 0444); 27 MODULE_PARM_DESC(enable_fw_debug, "Enable Firmware debug"); 28 29 static struct acp_quirk_entry quirk_valve_galileo = { 30 .signed_fw_image = true, 31 .skip_iram_dram_size_mod = true, 32 }; 33 34 const struct dmi_system_id acp_sof_quirk_table[] = { 35 { 36 /* Steam Deck OLED device */ 37 .matches = { 38 DMI_MATCH(DMI_SYS_VENDOR, "Valve"), 39 DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"), 40 }, 41 .driver_data = &quirk_valve_galileo, 42 }, 43 {} 44 }; 45 EXPORT_SYMBOL_GPL(acp_sof_quirk_table); 46 47 static void init_dma_descriptor(struct acp_dev_data *adata) 48 { 49 struct snd_sof_dev *sdev = adata->dev; 50 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 51 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata; 52 unsigned int addr; 53 unsigned int acp_dma_desc_base_addr, acp_dma_desc_max_num_dscr; 54 55 addr = desc->sram_pte_offset + sdev->debug_box.offset + 56 offsetof(struct scratch_reg_conf, dma_desc); 57 58 switch (acp_data->pci_rev) { 59 case ACP70_PCI_ID: 60 acp_dma_desc_base_addr = ACP70_DMA_DESC_BASE_ADDR; 61 acp_dma_desc_max_num_dscr = ACP70_DMA_DESC_MAX_NUM_DSCR; 62 break; 63 default: 64 acp_dma_desc_base_addr = ACP_DMA_DESC_BASE_ADDR; 65 acp_dma_desc_max_num_dscr = ACP_DMA_DESC_MAX_NUM_DSCR; 66 } 67 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_base_addr, addr); 68 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_max_num_dscr, ACP_MAX_DESC_CNT); 69 } 70 71 static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx, 72 struct dma_descriptor *dscr_info) 73 { 74 struct snd_sof_dev *sdev = adata->dev; 75 unsigned int offset; 76 77 offset = ACP_SCRATCH_REG_0 + sdev->debug_box.offset + 78 offsetof(struct scratch_reg_conf, dma_desc) + 79 idx * sizeof(struct dma_descriptor); 80 81 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr); 82 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr); 83 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all); 84 } 85 86 static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch, 87 unsigned int idx, unsigned int dscr_count) 88 { 89 struct snd_sof_dev *sdev = adata->dev; 90 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata; 91 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 92 unsigned int val, status; 93 unsigned int acp_dma_cntl_0, acp_dma_ch_rst_sts, acp_dma_dscr_err_sts_0; 94 unsigned int acp_dma_dscr_cnt_0, acp_dma_prio_0, acp_dma_dscr_strt_idx_0; 95 int ret; 96 97 switch (acp_data->pci_rev) { 98 case ACP70_PCI_ID: 99 acp_dma_cntl_0 = ACP70_DMA_CNTL_0; 100 acp_dma_ch_rst_sts = ACP70_DMA_CH_RST_STS; 101 acp_dma_dscr_err_sts_0 = ACP70_DMA_ERR_STS_0; 102 acp_dma_dscr_cnt_0 = ACP70_DMA_DSCR_CNT_0; 103 acp_dma_prio_0 = ACP70_DMA_PRIO_0; 104 acp_dma_dscr_strt_idx_0 = ACP70_DMA_DSCR_STRT_IDX_0; 105 break; 106 default: 107 acp_dma_cntl_0 = ACP_DMA_CNTL_0; 108 acp_dma_ch_rst_sts = ACP_DMA_CH_RST_STS; 109 acp_dma_dscr_err_sts_0 = ACP_DMA_ERR_STS_0; 110 acp_dma_dscr_cnt_0 = ACP_DMA_DSCR_CNT_0; 111 acp_dma_prio_0 = ACP_DMA_PRIO_0; 112 acp_dma_dscr_strt_idx_0 = ACP_DMA_DSCR_STRT_IDX_0; 113 } 114 115 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), 116 ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN); 117 118 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_rst_sts, val, 119 val & (1 << ch), ACP_REG_POLL_INTERVAL, 120 ACP_REG_POLL_TIMEOUT_US); 121 if (ret < 0) { 122 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->acp_error_stat); 123 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, acp_dma_dscr_err_sts_0 + 124 ch * sizeof(u32)); 125 126 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status); 127 return ret; 128 } 129 130 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (acp_dma_cntl_0 + ch * sizeof(u32)), 0); 131 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_cnt_0 + ch * sizeof(u32), dscr_count); 132 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_strt_idx_0 + ch * sizeof(u32), idx); 133 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_prio_0 + ch * sizeof(u32), 0); 134 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), ACP_DMA_CH_RUN); 135 136 return ret; 137 } 138 139 static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch, 140 unsigned int dscr_count, struct dma_descriptor *dscr_info) 141 { 142 struct snd_sof_dev *sdev = adata->dev; 143 int ret; 144 u16 dscr; 145 146 if (!dscr_info || !dscr_count) 147 return -EINVAL; 148 149 for (dscr = 0; dscr < dscr_count; dscr++) 150 configure_dma_descriptor(adata, dscr, dscr_info++); 151 152 ret = config_dma_channel(adata, ch, 0, dscr_count); 153 if (ret < 0) 154 dev_err(sdev->dev, "config dma ch failed:%d\n", ret); 155 156 return ret; 157 } 158 159 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 160 unsigned int dest_addr, int dsp_data_size) 161 { 162 struct snd_sof_dev *sdev = adata->dev; 163 unsigned int desc_count, index; 164 int ret; 165 166 for (desc_count = 0; desc_count < ACP_MAX_DESC && dsp_data_size >= 0; 167 desc_count++, dsp_data_size -= ACP_PAGE_SIZE) { 168 adata->dscr_info[desc_count].src_addr = src_addr + desc_count * ACP_PAGE_SIZE; 169 adata->dscr_info[desc_count].dest_addr = dest_addr + desc_count * ACP_PAGE_SIZE; 170 adata->dscr_info[desc_count].tx_cnt.bits.count = ACP_PAGE_SIZE; 171 if (dsp_data_size < ACP_PAGE_SIZE) 172 adata->dscr_info[desc_count].tx_cnt.bits.count = dsp_data_size; 173 } 174 175 ret = acpbus_dma_start(adata, 0, desc_count, adata->dscr_info); 176 if (ret) 177 dev_err(sdev->dev, "acpbus_dma_start failed\n"); 178 179 /* Clear descriptor array */ 180 for (index = 0; index < desc_count; index++) 181 memset(&adata->dscr_info[index], 0x00, sizeof(struct dma_descriptor)); 182 183 return ret; 184 } 185 186 /* 187 * psp_mbox_ready- function to poll ready bit of psp mbox 188 * @adata: acp device data 189 * @ack: bool variable to check ready bit status or psp ack 190 */ 191 192 static int psp_mbox_ready(struct acp_dev_data *adata, bool ack) 193 { 194 struct snd_sof_dev *sdev = adata->dev; 195 int ret, data; 196 197 ret = read_poll_timeout(smn_read_register, data, data > 0 && data & MBOX_READY_MASK, 198 MBOX_DELAY_US, ACP_PSP_TIMEOUT_US, false, MP0_C2PMSG_114_REG); 199 200 if (!ret) 201 return 0; 202 203 dev_err(sdev->dev, "PSP error status %x\n", data & MBOX_STATUS_MASK); 204 205 if (ack) 206 return -ETIMEDOUT; 207 208 return -EBUSY; 209 } 210 211 /* 212 * psp_send_cmd - function to send psp command over mbox 213 * @adata: acp device data 214 * @cmd: non zero integer value for command type 215 */ 216 217 static int psp_send_cmd(struct acp_dev_data *adata, int cmd) 218 { 219 struct snd_sof_dev *sdev = adata->dev; 220 int ret; 221 u32 data; 222 223 if (!cmd) 224 return -EINVAL; 225 226 /* Get a non-zero Doorbell value from PSP */ 227 ret = read_poll_timeout(smn_read_register, data, data > 0, MBOX_DELAY_US, 228 ACP_PSP_TIMEOUT_US, false, MP0_C2PMSG_73_REG); 229 230 if (ret) { 231 dev_err(sdev->dev, "Failed to get Doorbell from MBOX %x\n", MP0_C2PMSG_73_REG); 232 return ret; 233 } 234 235 /* Check if PSP is ready for new command */ 236 ret = psp_mbox_ready(adata, 0); 237 if (ret) 238 return ret; 239 240 ret = amd_smn_write(0, MP0_C2PMSG_114_REG, cmd); 241 if (ret) 242 return ret; 243 244 /* Ring the Doorbell for PSP */ 245 ret = amd_smn_write(0, MP0_C2PMSG_73_REG, data); 246 if (ret) 247 return ret; 248 249 /* Check MBOX ready as PSP ack */ 250 ret = psp_mbox_ready(adata, 1); 251 252 return ret; 253 } 254 255 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 256 unsigned int start_addr, unsigned int dest_addr, 257 unsigned int image_length) 258 { 259 struct snd_sof_dev *sdev = adata->dev; 260 unsigned int tx_count, fw_qualifier, val; 261 int ret; 262 263 if (!image_addr) { 264 dev_err(sdev->dev, "SHA DMA image address is NULL\n"); 265 return -EINVAL; 266 } 267 268 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD); 269 if (val & ACP_SHA_RUN) { 270 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET); 271 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS, 272 val, val & ACP_SHA_RESET, 273 ACP_REG_POLL_INTERVAL, 274 ACP_REG_POLL_TIMEOUT_US); 275 if (ret < 0) { 276 dev_err(sdev->dev, "SHA DMA Failed to Reset\n"); 277 return ret; 278 } 279 } 280 281 if (adata->quirks && adata->quirks->signed_fw_image) 282 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_INCLUDE_HDR, ACP_SHA_HEADER); 283 284 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr); 285 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr); 286 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length); 287 288 /* psp_send_cmd only required for vangogh platform */ 289 if (adata->pci_rev == ACP_VANGOGH_PCI_ID && 290 !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) { 291 /* Modify IRAM and DRAM size */ 292 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2); 293 if (ret) 294 return ret; 295 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG); 296 if (ret) 297 return ret; 298 } 299 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN); 300 301 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT, 302 tx_count, tx_count == image_length, 303 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 304 if (ret < 0) { 305 dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count); 306 return ret; 307 } 308 309 /* psp_send_cmd only required for renoir platform*/ 310 if (adata->pci_rev == ACP_RN_PCI_ID) { 311 ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND); 312 if (ret) 313 return ret; 314 } 315 316 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER, 317 fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE, 318 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 319 if (ret < 0) { 320 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_PSP_ACK); 321 dev_err(sdev->dev, "PSP validation failed: fw_qualifier = %#x, ACP_SHA_PSP_ACK = %#x\n", 322 fw_qualifier, val); 323 return ret; 324 } 325 326 return 0; 327 } 328 329 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch) 330 { 331 struct snd_sof_dev *sdev = adata->dev; 332 unsigned int val; 333 unsigned int acp_dma_ch_sts; 334 int ret = 0; 335 336 switch (adata->pci_rev) { 337 case ACP70_PCI_ID: 338 acp_dma_ch_sts = ACP70_DMA_CH_STS; 339 break; 340 default: 341 acp_dma_ch_sts = ACP_DMA_CH_STS; 342 } 343 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32)); 344 if (val & ACP_DMA_CH_RUN) { 345 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_sts, val, !val, 346 ACP_REG_POLL_INTERVAL, 347 ACP_DMA_COMPLETE_TIMEOUT_US); 348 if (ret < 0) 349 dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch); 350 } 351 352 return ret; 353 } 354 355 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes) 356 { 357 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 358 int i, j; 359 360 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 361 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i); 362 } 363 364 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes) 365 { 366 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 367 int i, j; 368 369 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 370 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]); 371 } 372 373 static int acp_memory_init(struct snd_sof_dev *sdev) 374 { 375 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 376 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 377 378 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_CNTL_OFFSET, 379 ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK); 380 init_dma_descriptor(adata); 381 382 return 0; 383 } 384 385 static irqreturn_t acp_irq_thread(int irq, void *context) 386 { 387 struct snd_sof_dev *sdev = context; 388 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 389 unsigned int count = ACP_HW_SEM_RETRY_COUNT; 390 391 spin_lock_irq(&sdev->ipc_lock); 392 /* Wait until acquired HW Semaphore lock or timeout */ 393 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset) && --count) 394 ; 395 spin_unlock_irq(&sdev->ipc_lock); 396 397 if (!count) { 398 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__); 399 return IRQ_NONE; 400 } 401 402 sof_ops(sdev)->irq_thread(irq, sdev); 403 /* Unlock or Release HW Semaphore */ 404 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0); 405 406 return IRQ_HANDLED; 407 }; 408 409 static irqreturn_t acp_irq_handler(int irq, void *dev_id) 410 { 411 struct amd_sdw_manager *amd_manager; 412 struct snd_sof_dev *sdev = dev_id; 413 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 414 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 415 unsigned int base = desc->dsp_intr_base; 416 unsigned int val; 417 int irq_flag = 0; 418 419 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET); 420 if (val & ACP_DSP_TO_HOST_IRQ) { 421 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET, 422 ACP_DSP_TO_HOST_IRQ); 423 return IRQ_WAKE_THREAD; 424 } 425 426 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat); 427 if (val & ACP_SDW0_IRQ_MASK) { 428 amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev); 429 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_SDW0_IRQ_MASK); 430 if (amd_manager) 431 schedule_work(&amd_manager->amd_sdw_irq_thread); 432 irq_flag = 1; 433 } 434 435 if (val & ACP_ERROR_IRQ_MASK) { 436 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK); 437 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_sw0_i2s_err_reason, 0); 438 /* ACP_SW1_I2S_ERROR_REASON is newly added register from rmb platform onwards */ 439 if (adata->pci_rev >= ACP_RMB_PCI_ID) 440 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW1_I2S_ERROR_REASON, 0); 441 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_error_stat, 0); 442 irq_flag = 1; 443 } 444 445 if (desc->ext_intr_stat1) { 446 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1); 447 if (val & ACP_SDW1_IRQ_MASK) { 448 amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev); 449 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, 450 ACP_SDW1_IRQ_MASK); 451 if (amd_manager) 452 schedule_work(&amd_manager->amd_sdw_irq_thread); 453 irq_flag = 1; 454 } 455 } 456 if (irq_flag) 457 return IRQ_HANDLED; 458 else 459 return IRQ_NONE; 460 } 461 462 static int acp_power_on(struct snd_sof_dev *sdev) 463 { 464 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 465 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 466 unsigned int base = desc->pgfsm_base; 467 unsigned int val; 468 unsigned int acp_pgfsm_status_mask, acp_pgfsm_cntl_mask; 469 int ret; 470 471 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET); 472 473 if (val == ACP_POWERED_ON) 474 return 0; 475 476 switch (adata->pci_rev) { 477 case ACP_RN_PCI_ID: 478 case ACP_VANGOGH_PCI_ID: 479 acp_pgfsm_status_mask = ACP3X_PGFSM_STATUS_MASK; 480 acp_pgfsm_cntl_mask = ACP3X_PGFSM_CNTL_POWER_ON_MASK; 481 break; 482 case ACP_RMB_PCI_ID: 483 case ACP63_PCI_ID: 484 acp_pgfsm_status_mask = ACP6X_PGFSM_STATUS_MASK; 485 acp_pgfsm_cntl_mask = ACP6X_PGFSM_CNTL_POWER_ON_MASK; 486 break; 487 case ACP70_PCI_ID: 488 acp_pgfsm_status_mask = ACP70_PGFSM_STATUS_MASK; 489 acp_pgfsm_cntl_mask = ACP70_PGFSM_CNTL_POWER_ON_MASK; 490 break; 491 default: 492 return -EINVAL; 493 } 494 495 if (val & acp_pgfsm_status_mask) 496 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET, 497 acp_pgfsm_cntl_mask); 498 499 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val, 500 !val, ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 501 if (ret < 0) 502 dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n"); 503 504 return ret; 505 } 506 507 static int acp_reset(struct snd_sof_dev *sdev) 508 { 509 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 510 unsigned int val; 511 int ret; 512 513 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET); 514 515 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 516 val & ACP_SOFT_RESET_DONE_MASK, 517 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 518 if (ret < 0) { 519 dev_err(sdev->dev, "timeout asserting reset\n"); 520 return ret; 521 } 522 523 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET); 524 525 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 526 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 527 if (ret < 0) 528 dev_err(sdev->dev, "timeout in releasing reset\n"); 529 530 if (desc->acp_clkmux_sel) 531 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK); 532 533 if (desc->ext_intr_enb) 534 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01); 535 536 if (desc->ext_intr_cntl) 537 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_MASK); 538 return ret; 539 } 540 541 static int acp_dsp_reset(struct snd_sof_dev *sdev) 542 { 543 unsigned int val; 544 int ret; 545 546 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_ASSERT_RESET); 547 548 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 549 val & ACP_DSP_SOFT_RESET_DONE_MASK, 550 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 551 if (ret < 0) { 552 dev_err(sdev->dev, "timeout asserting reset\n"); 553 return ret; 554 } 555 556 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_RELEASE_RESET); 557 558 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 559 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 560 if (ret < 0) 561 dev_err(sdev->dev, "timeout in releasing reset\n"); 562 563 return ret; 564 } 565 566 static int acp_init(struct snd_sof_dev *sdev) 567 { 568 int ret; 569 570 /* power on */ 571 ret = acp_power_on(sdev); 572 if (ret) { 573 dev_err(sdev->dev, "ACP power on failed\n"); 574 return ret; 575 } 576 577 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01); 578 /* Reset */ 579 return acp_reset(sdev); 580 } 581 582 static bool check_acp_sdw_enable_status(struct snd_sof_dev *sdev) 583 { 584 struct acp_dev_data *acp_data; 585 u32 sdw0_en, sdw1_en; 586 587 acp_data = sdev->pdata->hw_pdata; 588 if (!acp_data->sdw) 589 return false; 590 591 sdw0_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW0_EN); 592 sdw1_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW1_EN); 593 acp_data->sdw_en_stat = sdw0_en || sdw1_en; 594 return acp_data->sdw_en_stat; 595 } 596 597 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state) 598 { 599 struct acp_dev_data *acp_data; 600 int ret; 601 bool enable = false; 602 603 acp_data = sdev->pdata->hw_pdata; 604 /* When acp_reset() function is invoked, it will apply ACP SOFT reset and 605 * DSP reset. ACP Soft reset sequence will cause all ACP IP registers will 606 * be reset to default values which will break the ClockStop Mode functionality. 607 * Add a condition check to apply DSP reset when SoundWire ClockStop mode 608 * is selected. For the rest of the scenarios, apply acp reset sequence. 609 */ 610 if (check_acp_sdw_enable_status(sdev)) 611 return acp_dsp_reset(sdev); 612 613 ret = acp_reset(sdev); 614 if (ret) { 615 dev_err(sdev->dev, "ACP Reset failed\n"); 616 return ret; 617 } 618 if (acp_data->pci_rev == ACP70_PCI_ID) 619 enable = true; 620 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, enable); 621 622 return 0; 623 } 624 EXPORT_SYMBOL_NS(amd_sof_acp_suspend, "SND_SOC_SOF_AMD_COMMON"); 625 626 int amd_sof_acp_resume(struct snd_sof_dev *sdev) 627 { 628 int ret; 629 struct acp_dev_data *acp_data; 630 631 acp_data = sdev->pdata->hw_pdata; 632 if (!acp_data->sdw_en_stat) { 633 ret = acp_init(sdev); 634 if (ret) { 635 dev_err(sdev->dev, "ACP Init failed\n"); 636 return ret; 637 } 638 return acp_memory_init(sdev); 639 } else { 640 return acp_dsp_reset(sdev); 641 } 642 } 643 EXPORT_SYMBOL_NS(amd_sof_acp_resume, "SND_SOC_SOF_AMD_COMMON"); 644 645 #if IS_ENABLED(CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE) 646 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr) 647 { 648 struct acpi_device *sdw_dev; 649 struct acp_dev_data *acp_data; 650 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 651 652 if (!addr) 653 return -ENODEV; 654 655 acp_data = sdev->pdata->hw_pdata; 656 sdw_dev = acpi_find_child_device(ACPI_COMPANION(sdev->dev), addr, 0); 657 if (!sdw_dev) 658 return -ENODEV; 659 660 acp_data->info.handle = sdw_dev->handle; 661 acp_data->info.count = desc->sdw_max_link_count; 662 663 return amd_sdw_scan_controller(&acp_data->info); 664 } 665 666 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev) 667 { 668 struct acp_dev_data *acp_data; 669 struct sdw_amd_res sdw_res; 670 int ret; 671 672 acp_data = sdev->pdata->hw_pdata; 673 674 memset(&sdw_res, 0, sizeof(sdw_res)); 675 sdw_res.addr = acp_data->addr; 676 sdw_res.reg_range = acp_data->reg_range; 677 sdw_res.handle = acp_data->info.handle; 678 sdw_res.parent = sdev->dev; 679 sdw_res.dev = sdev->dev; 680 sdw_res.acp_lock = &acp_data->acp_lock; 681 sdw_res.count = acp_data->info.count; 682 sdw_res.link_mask = acp_data->info.link_mask; 683 sdw_res.mmio_base = sdev->bar[ACP_DSP_BAR]; 684 sdw_res.acp_rev = acp_data->pci_rev; 685 686 ret = sdw_amd_probe(&sdw_res, &acp_data->sdw); 687 if (ret) 688 dev_err(sdev->dev, "SoundWire probe failed\n"); 689 return ret; 690 } 691 692 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev) 693 { 694 struct acp_dev_data *acp_data; 695 696 acp_data = sdev->pdata->hw_pdata; 697 if (acp_data->sdw) 698 sdw_amd_exit(acp_data->sdw); 699 acp_data->sdw = NULL; 700 701 return 0; 702 } 703 704 #else 705 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr) 706 { 707 return 0; 708 } 709 710 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev) 711 { 712 return 0; 713 } 714 715 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev) 716 { 717 return 0; 718 } 719 #endif 720 721 int amd_sof_acp_probe(struct snd_sof_dev *sdev) 722 { 723 struct pci_dev *pci = to_pci_dev(sdev->dev); 724 struct acp_dev_data *adata; 725 const struct sof_amd_acp_desc *chip; 726 const struct dmi_system_id *dmi_id; 727 unsigned int addr; 728 int ret; 729 730 chip = get_chip_info(sdev->pdata); 731 if (!chip) { 732 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device); 733 return -EIO; 734 } 735 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data), 736 GFP_KERNEL); 737 if (!adata) 738 return -ENOMEM; 739 740 adata->dev = sdev; 741 adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 742 PLATFORM_DEVID_NONE, NULL, 0); 743 if (IS_ERR(adata->dmic_dev)) { 744 dev_err(sdev->dev, "failed to register platform for dmic codec\n"); 745 return PTR_ERR(adata->dmic_dev); 746 } 747 addr = pci_resource_start(pci, ACP_DSP_BAR); 748 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR)); 749 if (!sdev->bar[ACP_DSP_BAR]) { 750 dev_err(sdev->dev, "ioremap error\n"); 751 ret = -ENXIO; 752 goto unregister_dev; 753 } 754 755 pci_set_master(pci); 756 adata->addr = addr; 757 adata->reg_range = chip->reg_end_addr - chip->reg_start_addr; 758 adata->pci_rev = pci->revision; 759 mutex_init(&adata->acp_lock); 760 sdev->pdata->hw_pdata = adata; 761 762 ret = acp_init(sdev); 763 if (ret < 0) 764 goto unregister_dev; 765 766 sdev->ipc_irq = pci->irq; 767 ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread, 768 IRQF_SHARED, "AudioDSP", sdev); 769 if (ret < 0) { 770 dev_err(sdev->dev, "failed to register IRQ %d\n", 771 sdev->ipc_irq); 772 goto unregister_dev; 773 } 774 775 /* scan SoundWire capabilities exposed by DSDT */ 776 ret = acp_sof_scan_sdw_devices(sdev, chip->sdw_acpi_dev_addr); 777 if (ret < 0) { 778 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n"); 779 goto skip_soundwire; 780 } 781 ret = amd_sof_sdw_probe(sdev); 782 if (ret < 0) { 783 dev_err(sdev->dev, "error: SoundWire probe error\n"); 784 free_irq(sdev->ipc_irq, sdev); 785 return ret; 786 } 787 788 skip_soundwire: 789 sdev->dsp_box.offset = 0; 790 sdev->dsp_box.size = BOX_SIZE_512; 791 792 sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size; 793 sdev->host_box.size = BOX_SIZE_512; 794 795 sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size; 796 sdev->debug_box.size = BOX_SIZE_1024; 797 798 dmi_id = dmi_first_match(acp_sof_quirk_table); 799 if (dmi_id) { 800 adata->quirks = dmi_id->driver_data; 801 802 if (adata->quirks->signed_fw_image) { 803 adata->fw_code_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 804 "sof-%s-code.bin", 805 chip->name); 806 if (!adata->fw_code_bin) { 807 ret = -ENOMEM; 808 goto free_ipc_irq; 809 } 810 811 adata->fw_data_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 812 "sof-%s-data.bin", 813 chip->name); 814 if (!adata->fw_data_bin) { 815 ret = -ENOMEM; 816 goto free_ipc_irq; 817 } 818 } 819 } 820 821 adata->enable_fw_debug = enable_fw_debug; 822 acp_memory_init(sdev); 823 824 acp_dsp_stream_init(sdev); 825 826 return 0; 827 828 free_ipc_irq: 829 free_irq(sdev->ipc_irq, sdev); 830 unregister_dev: 831 platform_device_unregister(adata->dmic_dev); 832 return ret; 833 } 834 EXPORT_SYMBOL_NS(amd_sof_acp_probe, "SND_SOC_SOF_AMD_COMMON"); 835 836 void amd_sof_acp_remove(struct snd_sof_dev *sdev) 837 { 838 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 839 840 if (adata->sdw) 841 amd_sof_sdw_exit(sdev); 842 843 if (sdev->ipc_irq) 844 free_irq(sdev->ipc_irq, sdev); 845 846 if (adata->dmic_dev) 847 platform_device_unregister(adata->dmic_dev); 848 849 acp_reset(sdev); 850 } 851 EXPORT_SYMBOL_NS(amd_sof_acp_remove, "SND_SOC_SOF_AMD_COMMON"); 852 853 MODULE_LICENSE("Dual BSD/GPL"); 854 MODULE_DESCRIPTION("AMD ACP sof driver"); 855 MODULE_IMPORT_NS("SOUNDWIRE_AMD_INIT"); 856 MODULE_IMPORT_NS("SND_AMD_SOUNDWIRE_ACPI"); 857