1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ subsystem" 3# Options selectable by the architecture code 4 5# Make sparse irq Kconfig switch below available 6config MAY_HAVE_SPARSE_IRQ 7 bool 8 9# Legacy support, required for itanic 10config GENERIC_IRQ_LEGACY 11 bool 12 13# Enable the generic irq autoprobe mechanism 14config GENERIC_IRQ_PROBE 15 bool 16 17# Use the generic /proc/interrupts implementation 18config GENERIC_IRQ_SHOW 19 bool 20 21# Print level/edge extra information 22config GENERIC_IRQ_SHOW_LEVEL 23 bool 24 25# Supports effective affinity mask 26config GENERIC_IRQ_EFFECTIVE_AFF_MASK 27 depends on SMP 28 bool 29 30# Support for delayed migration from interrupt context 31config GENERIC_PENDING_IRQ 32 bool 33 34# Deduce delayed migration from top-level interrupt chip flags 35config GENERIC_PENDING_IRQ_CHIPFLAGS 36 bool 37 38# Support for generic irq migrating off cpu before the cpu is offline. 39config GENERIC_IRQ_MIGRATION 40 bool 41 42# Alpha specific irq affinity mechanism 43config AUTO_IRQ_AFFINITY 44 bool 45 46# Interrupt injection mechanism 47config GENERIC_IRQ_INJECTION 48 bool 49 50# Tasklet based software resend for pending interrupts on enable_irq() 51config HARDIRQS_SW_RESEND 52 bool 53 54# Edge style eoi based handler (cell) 55config IRQ_EDGE_EOI_HANDLER 56 bool 57 58# Generic configurable interrupt chip implementation 59config GENERIC_IRQ_CHIP 60 bool 61 select IRQ_DOMAIN 62 63# Generic irq_domain hw <--> linux irq number translation 64config IRQ_DOMAIN 65 bool 66 67# Support for simulated interrupts 68config IRQ_SIM 69 bool 70 select IRQ_WORK 71 select IRQ_DOMAIN 72 73# Support for hierarchical irq domains 74config IRQ_DOMAIN_HIERARCHY 75 bool 76 select IRQ_DOMAIN 77 78# Support for obsolete non-mapping irq domains 79config IRQ_DOMAIN_NOMAP 80 bool 81 select IRQ_DOMAIN 82 83# Support for hierarchical fasteoi+edge and fasteoi+level handlers 84config IRQ_FASTEOI_HIERARCHY_HANDLERS 85 bool 86 87# Generic IRQ IPI support 88config GENERIC_IRQ_IPI 89 bool 90 depends on SMP 91 select IRQ_DOMAIN_HIERARCHY 92 93# Generic IRQ IPI Mux support 94config GENERIC_IRQ_IPI_MUX 95 bool 96 depends on SMP 97 98# Generic MSI hierarchical interrupt domain support 99config GENERIC_MSI_IRQ 100 bool 101 select IRQ_DOMAIN_HIERARCHY 102 103# irqchip drivers should select this if they call iommu_dma_prepare_msi() 104config IRQ_MSI_IOMMU 105 bool 106 107config IRQ_TIMINGS 108 bool 109 110config GENERIC_IRQ_MATRIX_ALLOCATOR 111 bool 112 113config GENERIC_IRQ_RESERVATION_MODE 114 bool 115 116# Snapshot for interrupt statistics 117config GENERIC_IRQ_STAT_SNAPSHOT 118 bool 119 120# Support forced irq threading 121config IRQ_FORCED_THREADING 122 bool 123 124config SPARSE_IRQ 125 bool "Support sparse irq numbering" if MAY_HAVE_SPARSE_IRQ 126 help 127 128 Sparse irq numbering is useful for distro kernels that want 129 to define a high CONFIG_NR_CPUS value but still want to have 130 low kernel memory footprint on smaller machines. 131 132 ( Sparse irqs can also be beneficial on NUMA boxes, as they spread 133 out the interrupt descriptors in a more NUMA-friendly way. ) 134 135 If you don't know what to do here, say N. 136 137config GENERIC_IRQ_DEBUGFS 138 bool "Expose irq internals in debugfs" 139 depends on DEBUG_FS 140 select GENERIC_IRQ_INJECTION 141 default n 142 help 143 144 Exposes internal state information through debugfs. Mostly for 145 developers and debugging of hard to diagnose interrupt problems. 146 147 If you don't know what to do here, say N. 148 149# Clear forwarded VM interrupts during kexec. 150# This option ensures the kernel clears active states for interrupts 151# forwarded to virtual machines (VMs) during a machine kexec. 152config GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD 153 bool 154 155endmenu 156 157config GENERIC_IRQ_MULTI_HANDLER 158 bool 159 help 160 Allow to specify the low level IRQ handler at run time. 161 162# Cavium Octeon is the last system to use this deprecated option 163# Do not even think of enabling this on any new platform 164config DEPRECATED_IRQ_CPU_ONOFFLINE 165 bool 166 depends on CAVIUM_OCTEON_SOC 167 default CAVIUM_OCTEON_SOC 168