xref: /linux-6.15/include/uapi/linux/virtio_pci.h (revision 7c1ae151)
1607ca46eSDavid Howells /*
2607ca46eSDavid Howells  * Virtio PCI driver
3607ca46eSDavid Howells  *
4607ca46eSDavid Howells  * This module allows virtio devices to be used over a virtual PCI device.
5607ca46eSDavid Howells  * This can be used with QEMU based VMMs like KVM or Xen.
6607ca46eSDavid Howells  *
7607ca46eSDavid Howells  * Copyright IBM Corp. 2007
8607ca46eSDavid Howells  *
9607ca46eSDavid Howells  * Authors:
10607ca46eSDavid Howells  *  Anthony Liguori  <[email protected]>
11607ca46eSDavid Howells  *
12607ca46eSDavid Howells  * This header is BSD licensed so anyone can use the definitions to implement
13607ca46eSDavid Howells  * compatible drivers/servers.
14607ca46eSDavid Howells  *
15607ca46eSDavid Howells  * Redistribution and use in source and binary forms, with or without
16607ca46eSDavid Howells  * modification, are permitted provided that the following conditions
17607ca46eSDavid Howells  * are met:
18607ca46eSDavid Howells  * 1. Redistributions of source code must retain the above copyright
19607ca46eSDavid Howells  *    notice, this list of conditions and the following disclaimer.
20607ca46eSDavid Howells  * 2. Redistributions in binary form must reproduce the above copyright
21607ca46eSDavid Howells  *    notice, this list of conditions and the following disclaimer in the
22607ca46eSDavid Howells  *    documentation and/or other materials provided with the distribution.
23607ca46eSDavid Howells  * 3. Neither the name of IBM nor the names of its contributors
24607ca46eSDavid Howells  *    may be used to endorse or promote products derived from this software
25607ca46eSDavid Howells  *    without specific prior written permission.
26607ca46eSDavid Howells  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' AND
27607ca46eSDavid Howells  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28607ca46eSDavid Howells  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29607ca46eSDavid Howells  * ARE DISCLAIMED.  IN NO EVENT SHALL IBM OR CONTRIBUTORS BE LIABLE
30607ca46eSDavid Howells  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31607ca46eSDavid Howells  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32607ca46eSDavid Howells  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33607ca46eSDavid Howells  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34607ca46eSDavid Howells  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35607ca46eSDavid Howells  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36607ca46eSDavid Howells  * SUCH DAMAGE.
37607ca46eSDavid Howells  */
38607ca46eSDavid Howells 
39607ca46eSDavid Howells #ifndef _LINUX_VIRTIO_PCI_H
40607ca46eSDavid Howells #define _LINUX_VIRTIO_PCI_H
41607ca46eSDavid Howells 
427f870c81SMichael S. Tsirkin #include <linux/types.h>
43*7c1ae151SYishai Hadas #include <linux/kernel.h>
44607ca46eSDavid Howells 
450dce3771SMichael S. Tsirkin #ifndef VIRTIO_PCI_NO_LEGACY
460dce3771SMichael S. Tsirkin 
47607ca46eSDavid Howells /* A 32-bit r/o bitmask of the features supported by the host */
48607ca46eSDavid Howells #define VIRTIO_PCI_HOST_FEATURES	0
49607ca46eSDavid Howells 
50607ca46eSDavid Howells /* A 32-bit r/w bitmask of features activated by the guest */
51607ca46eSDavid Howells #define VIRTIO_PCI_GUEST_FEATURES	4
52607ca46eSDavid Howells 
53607ca46eSDavid Howells /* A 32-bit r/w PFN for the currently selected queue */
54607ca46eSDavid Howells #define VIRTIO_PCI_QUEUE_PFN		8
55607ca46eSDavid Howells 
56607ca46eSDavid Howells /* A 16-bit r/o queue size for the currently selected queue */
57607ca46eSDavid Howells #define VIRTIO_PCI_QUEUE_NUM		12
58607ca46eSDavid Howells 
59607ca46eSDavid Howells /* A 16-bit r/w queue selector */
60607ca46eSDavid Howells #define VIRTIO_PCI_QUEUE_SEL		14
61607ca46eSDavid Howells 
62607ca46eSDavid Howells /* A 16-bit r/w queue notifier */
63607ca46eSDavid Howells #define VIRTIO_PCI_QUEUE_NOTIFY		16
64607ca46eSDavid Howells 
65607ca46eSDavid Howells /* An 8-bit device status register.  */
66607ca46eSDavid Howells #define VIRTIO_PCI_STATUS		18
67607ca46eSDavid Howells 
68607ca46eSDavid Howells /* An 8-bit r/o interrupt status register.  Reading the value will return the
69607ca46eSDavid Howells  * current contents of the ISR and will also clear it.  This is effectively
70607ca46eSDavid Howells  * a read-and-acknowledge. */
71607ca46eSDavid Howells #define VIRTIO_PCI_ISR			19
72607ca46eSDavid Howells 
73607ca46eSDavid Howells /* MSI-X registers: only enabled if MSI-X is enabled. */
74607ca46eSDavid Howells /* A 16-bit vector for configuration changes. */
75607ca46eSDavid Howells #define VIRTIO_MSI_CONFIG_VECTOR        20
76607ca46eSDavid Howells /* A 16-bit vector for selected queue notifications. */
77607ca46eSDavid Howells #define VIRTIO_MSI_QUEUE_VECTOR         22
78607ca46eSDavid Howells 
79607ca46eSDavid Howells /* The remaining space is defined by each driver as the per-driver
80607ca46eSDavid Howells  * configuration space */
818b21ab14SMichael S. Tsirkin #define VIRTIO_PCI_CONFIG_OFF(msix_enabled)	((msix_enabled) ? 24 : 20)
828b21ab14SMichael S. Tsirkin /* Deprecated: please use VIRTIO_PCI_CONFIG_OFF instead */
832008c154SMichael S. Tsirkin #define VIRTIO_PCI_CONFIG(dev)	VIRTIO_PCI_CONFIG_OFF((dev)->msix_enabled)
84607ca46eSDavid Howells 
85607ca46eSDavid Howells /* Virtio ABI version, this must match exactly */
86607ca46eSDavid Howells #define VIRTIO_PCI_ABI_VERSION		0
87607ca46eSDavid Howells 
88607ca46eSDavid Howells /* How many bits to shift physical queue address written to QUEUE_PFN.
89607ca46eSDavid Howells  * 12 is historical, and due to x86 page size. */
90607ca46eSDavid Howells #define VIRTIO_PCI_QUEUE_ADDR_SHIFT	12
91607ca46eSDavid Howells 
92607ca46eSDavid Howells /* The alignment to use between consumer and producer parts of vring.
93607ca46eSDavid Howells  * x86 pagesize again. */
94607ca46eSDavid Howells #define VIRTIO_PCI_VRING_ALIGN		4096
950dce3771SMichael S. Tsirkin 
960dce3771SMichael S. Tsirkin #endif /* VIRTIO_PCI_NO_LEGACY */
970dce3771SMichael S. Tsirkin 
980dce3771SMichael S. Tsirkin /* The bit of the ISR which indicates a device configuration change. */
990dce3771SMichael S. Tsirkin #define VIRTIO_PCI_ISR_CONFIG		0x2
1000dce3771SMichael S. Tsirkin /* Vector value used to disable MSI for queue */
1010dce3771SMichael S. Tsirkin #define VIRTIO_MSI_NO_VECTOR            0xffff
1020dce3771SMichael S. Tsirkin 
10371d70c26SRusty Russell #ifndef VIRTIO_PCI_NO_MODERN
10471d70c26SRusty Russell 
10571d70c26SRusty Russell /* IDs for different capabilities.  Must all exist. */
10671d70c26SRusty Russell 
10771d70c26SRusty Russell /* Common configuration */
10871d70c26SRusty Russell #define VIRTIO_PCI_CAP_COMMON_CFG	1
10971d70c26SRusty Russell /* Notifications */
11071d70c26SRusty Russell #define VIRTIO_PCI_CAP_NOTIFY_CFG	2
11171d70c26SRusty Russell /* ISR access */
11271d70c26SRusty Russell #define VIRTIO_PCI_CAP_ISR_CFG		3
113e6a02746SRusty Russell /* Device specific configuration */
11471d70c26SRusty Russell #define VIRTIO_PCI_CAP_DEVICE_CFG	4
115e6a02746SRusty Russell /* PCI configuration access */
116e6a02746SRusty Russell #define VIRTIO_PCI_CAP_PCI_CFG		5
1170dd4ff93SSebastien Boeuf /* Additional shared memory capability */
1180dd4ff93SSebastien Boeuf #define VIRTIO_PCI_CAP_SHARED_MEMORY_CFG 8
11971d70c26SRusty Russell 
12071d70c26SRusty Russell /* This is the PCI capability header: */
12171d70c26SRusty Russell struct virtio_pci_cap {
12271d70c26SRusty Russell 	__u8 cap_vndr;		/* Generic PCI field: PCI_CAP_ID_VNDR */
12371d70c26SRusty Russell 	__u8 cap_next;		/* Generic PCI field: next ptr. */
12471d70c26SRusty Russell 	__u8 cap_len;		/* Generic PCI field: capability length */
1251fcf0512SMichael S. Tsirkin 	__u8 cfg_type;		/* Identifies the structure. */
1261fcf0512SMichael S. Tsirkin 	__u8 bar;		/* Where to find it. */
1270dd4ff93SSebastien Boeuf 	__u8 id;		/* Multiple capabilities of the same type */
1280dd4ff93SSebastien Boeuf 	__u8 padding[2];	/* Pad to full dword. */
12971d70c26SRusty Russell 	__le32 offset;		/* Offset within bar. */
1301fcf0512SMichael S. Tsirkin 	__le32 length;		/* Length of the structure, in bytes. */
13171d70c26SRusty Russell };
13271d70c26SRusty Russell 
1330dd4ff93SSebastien Boeuf struct virtio_pci_cap64 {
1340dd4ff93SSebastien Boeuf 	struct virtio_pci_cap cap;
1350dd4ff93SSebastien Boeuf 	__le32 offset_hi;             /* Most sig 32 bits of offset */
1360dd4ff93SSebastien Boeuf 	__le32 length_hi;             /* Most sig 32 bits of length */
1370dd4ff93SSebastien Boeuf };
1380dd4ff93SSebastien Boeuf 
13971d70c26SRusty Russell struct virtio_pci_notify_cap {
14071d70c26SRusty Russell 	struct virtio_pci_cap cap;
14171d70c26SRusty Russell 	__le32 notify_off_multiplier;	/* Multiplier for queue_notify_off. */
14271d70c26SRusty Russell };
14371d70c26SRusty Russell 
14471d70c26SRusty Russell /* Fields in VIRTIO_PCI_CAP_COMMON_CFG: */
14571d70c26SRusty Russell struct virtio_pci_common_cfg {
14671d70c26SRusty Russell 	/* About the whole device. */
14771d70c26SRusty Russell 	__le32 device_feature_select;	/* read-write */
14871d70c26SRusty Russell 	__le32 device_feature;		/* read-only */
14971d70c26SRusty Russell 	__le32 guest_feature_select;	/* read-write */
15071d70c26SRusty Russell 	__le32 guest_feature;		/* read-write */
15171d70c26SRusty Russell 	__le16 msix_config;		/* read-write */
15271d70c26SRusty Russell 	__le16 num_queues;		/* read-only */
15371d70c26SRusty Russell 	__u8 device_status;		/* read-write */
15471d70c26SRusty Russell 	__u8 config_generation;		/* read-only */
15571d70c26SRusty Russell 
15671d70c26SRusty Russell 	/* About a specific virtqueue. */
15771d70c26SRusty Russell 	__le16 queue_select;		/* read-write */
15871d70c26SRusty Russell 	__le16 queue_size;		/* read-write, power of 2. */
15971d70c26SRusty Russell 	__le16 queue_msix_vector;	/* read-write */
16071d70c26SRusty Russell 	__le16 queue_enable;		/* read-write */
16171d70c26SRusty Russell 	__le16 queue_notify_off;	/* read-only */
16271d70c26SRusty Russell 	__le32 queue_desc_lo;		/* read-write */
16371d70c26SRusty Russell 	__le32 queue_desc_hi;		/* read-write */
16471d70c26SRusty Russell 	__le32 queue_avail_lo;		/* read-write */
16571d70c26SRusty Russell 	__le32 queue_avail_hi;		/* read-write */
16671d70c26SRusty Russell 	__le32 queue_used_lo;		/* read-write */
16771d70c26SRusty Russell 	__le32 queue_used_hi;		/* read-write */
16871d70c26SRusty Russell };
16971d70c26SRusty Russell 
17035038957SMichael S. Tsirkin /*
17135038957SMichael S. Tsirkin  * Warning: do not use sizeof on this: use offsetofend for
17235038957SMichael S. Tsirkin  * specific fields you need.
17335038957SMichael S. Tsirkin  */
17435038957SMichael S. Tsirkin struct virtio_pci_modern_common_cfg {
17535038957SMichael S. Tsirkin 	struct virtio_pci_common_cfg cfg;
17635038957SMichael S. Tsirkin 
17735038957SMichael S. Tsirkin 	__le16 queue_notify_data;	/* read-write */
17835038957SMichael S. Tsirkin 	__le16 queue_reset;		/* read-write */
179fd27ef6bSFeng Liu 
180fd27ef6bSFeng Liu 	__le16 admin_queue_index;	/* read-only */
181fd27ef6bSFeng Liu 	__le16 admin_queue_num;		/* read-only */
18235038957SMichael S. Tsirkin };
18335038957SMichael S. Tsirkin 
1843121bb02SMichael S. Tsirkin /* Fields in VIRTIO_PCI_CAP_PCI_CFG: */
1853121bb02SMichael S. Tsirkin struct virtio_pci_cfg_cap {
1863121bb02SMichael S. Tsirkin 	struct virtio_pci_cap cap;
1873121bb02SMichael S. Tsirkin 	__u8 pci_cfg_data[4]; /* Data for BAR access. */
1883121bb02SMichael S. Tsirkin };
1893121bb02SMichael S. Tsirkin 
19089461c4aSRusty Russell /* Macro versions of offsets for the Old Timers! */
19189461c4aSRusty Russell #define VIRTIO_PCI_CAP_VNDR		0
19289461c4aSRusty Russell #define VIRTIO_PCI_CAP_NEXT		1
19389461c4aSRusty Russell #define VIRTIO_PCI_CAP_LEN		2
19489461c4aSRusty Russell #define VIRTIO_PCI_CAP_CFG_TYPE		3
19589461c4aSRusty Russell #define VIRTIO_PCI_CAP_BAR		4
19689461c4aSRusty Russell #define VIRTIO_PCI_CAP_OFFSET		8
19789461c4aSRusty Russell #define VIRTIO_PCI_CAP_LENGTH		12
19889461c4aSRusty Russell 
19989461c4aSRusty Russell #define VIRTIO_PCI_NOTIFY_CAP_MULT	16
20089461c4aSRusty Russell 
20189461c4aSRusty Russell #define VIRTIO_PCI_COMMON_DFSELECT	0
20289461c4aSRusty Russell #define VIRTIO_PCI_COMMON_DF		4
20389461c4aSRusty Russell #define VIRTIO_PCI_COMMON_GFSELECT	8
20489461c4aSRusty Russell #define VIRTIO_PCI_COMMON_GF		12
20589461c4aSRusty Russell #define VIRTIO_PCI_COMMON_MSIX		16
20689461c4aSRusty Russell #define VIRTIO_PCI_COMMON_NUMQ		18
20789461c4aSRusty Russell #define VIRTIO_PCI_COMMON_STATUS	20
20889461c4aSRusty Russell #define VIRTIO_PCI_COMMON_CFGGENERATION	21
20989461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_SELECT	22
21089461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_SIZE	24
21189461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_MSIX	26
21289461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_ENABLE	28
21389461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_NOFF	30
21489461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_DESCLO	32
21589461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_DESCHI	36
21689461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_AVAILLO	40
21789461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_AVAILHI	44
21889461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_USEDLO	48
21989461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_USEDHI	52
220ea024594SXuan Zhuo #define VIRTIO_PCI_COMMON_Q_NDATA	56
2210cdd450eSXuan Zhuo #define VIRTIO_PCI_COMMON_Q_RESET	58
222fd27ef6bSFeng Liu #define VIRTIO_PCI_COMMON_ADM_Q_IDX	60
223fd27ef6bSFeng Liu #define VIRTIO_PCI_COMMON_ADM_Q_NUM	62
22489461c4aSRusty Russell 
22571d70c26SRusty Russell #endif /* VIRTIO_PCI_NO_MODERN */
22671d70c26SRusty Russell 
22792792ac7SFeng Liu /* Admin command status. */
22892792ac7SFeng Liu #define VIRTIO_ADMIN_STATUS_OK		0
22992792ac7SFeng Liu 
230388431b9SFeng Liu /* Admin command opcode. */
231388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_LIST_QUERY	0x0
232388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_LIST_USE	0x1
233388431b9SFeng Liu 
234388431b9SFeng Liu /* Admin command group type. */
235388431b9SFeng Liu #define VIRTIO_ADMIN_GROUP_TYPE_SRIOV	0x1
236388431b9SFeng Liu 
237388431b9SFeng Liu /* Transitional device admin command. */
238388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_LEGACY_COMMON_CFG_WRITE	0x2
239388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_LEGACY_COMMON_CFG_READ		0x3
240388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_WRITE		0x4
241388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_READ		0x5
242388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_LEGACY_NOTIFY_INFO		0x6
243388431b9SFeng Liu 
244*7c1ae151SYishai Hadas /* Device parts access commands. */
245*7c1ae151SYishai Hadas #define VIRTIO_ADMIN_CMD_CAP_ID_LIST_QUERY		0x7
246*7c1ae151SYishai Hadas #define VIRTIO_ADMIN_CMD_DEVICE_CAP_GET			0x8
247*7c1ae151SYishai Hadas #define VIRTIO_ADMIN_CMD_DRIVER_CAP_SET			0x9
248*7c1ae151SYishai Hadas #define VIRTIO_ADMIN_CMD_RESOURCE_OBJ_CREATE		0xa
249*7c1ae151SYishai Hadas #define VIRTIO_ADMIN_CMD_RESOURCE_OBJ_DESTROY		0xd
250*7c1ae151SYishai Hadas #define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_GET		0xe
251*7c1ae151SYishai Hadas #define VIRTIO_ADMIN_CMD_DEV_PARTS_GET			0xf
252*7c1ae151SYishai Hadas #define VIRTIO_ADMIN_CMD_DEV_PARTS_SET			0x10
253*7c1ae151SYishai Hadas #define VIRTIO_ADMIN_CMD_DEV_MODE_SET			0x11
254*7c1ae151SYishai Hadas 
255ec6ecb84SSuzuki K Poulose struct virtio_admin_cmd_hdr {
25692792ac7SFeng Liu 	__le16 opcode;
25792792ac7SFeng Liu 	/*
25892792ac7SFeng Liu 	 * 1 - SR-IOV
25992792ac7SFeng Liu 	 * 2-65535 - reserved
26092792ac7SFeng Liu 	 */
26192792ac7SFeng Liu 	__le16 group_type;
26292792ac7SFeng Liu 	/* Unused, reserved for future extensions. */
26392792ac7SFeng Liu 	__u8 reserved1[12];
26492792ac7SFeng Liu 	__le64 group_member_id;
26592792ac7SFeng Liu };
26692792ac7SFeng Liu 
267ec6ecb84SSuzuki K Poulose struct virtio_admin_cmd_status {
26892792ac7SFeng Liu 	__le16 status;
26992792ac7SFeng Liu 	__le16 status_qualifier;
27092792ac7SFeng Liu 	/* Unused, reserved for future extensions. */
27192792ac7SFeng Liu 	__u8 reserved2[4];
27292792ac7SFeng Liu };
27392792ac7SFeng Liu 
274ec6ecb84SSuzuki K Poulose struct virtio_admin_cmd_legacy_wr_data {
275388431b9SFeng Liu 	__u8 offset; /* Starting offset of the register(s) to write. */
276388431b9SFeng Liu 	__u8 reserved[7];
277388431b9SFeng Liu 	__u8 registers[];
278388431b9SFeng Liu };
279388431b9SFeng Liu 
280ec6ecb84SSuzuki K Poulose struct virtio_admin_cmd_legacy_rd_data {
281388431b9SFeng Liu 	__u8 offset; /* Starting offset of the register(s) to read. */
282388431b9SFeng Liu };
283388431b9SFeng Liu 
284388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_END 0
285388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_OWNER_DEV 0x1
286388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_OWNER_MEM 0x2
287388431b9SFeng Liu 
288388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_MAX_NOTIFY_INFO 4
289388431b9SFeng Liu 
290ec6ecb84SSuzuki K Poulose struct virtio_admin_cmd_notify_info_data {
291388431b9SFeng Liu 	__u8 flags; /* 0 = end of list, 1 = owner device, 2 = member device */
292388431b9SFeng Liu 	__u8 bar; /* BAR of the member or the owner device */
293388431b9SFeng Liu 	__u8 padding[6];
294388431b9SFeng Liu 	__le64 offset; /* Offset within bar. */
295388431b9SFeng Liu };
296388431b9SFeng Liu 
297388431b9SFeng Liu struct virtio_admin_cmd_notify_info_result {
298388431b9SFeng Liu 	struct virtio_admin_cmd_notify_info_data entries[VIRTIO_ADMIN_CMD_MAX_NOTIFY_INFO];
299388431b9SFeng Liu };
300388431b9SFeng Liu 
301*7c1ae151SYishai Hadas #define VIRTIO_DEV_PARTS_CAP 0x0000
302*7c1ae151SYishai Hadas 
303*7c1ae151SYishai Hadas struct virtio_dev_parts_cap {
304*7c1ae151SYishai Hadas 	__u8 get_parts_resource_objects_limit;
305*7c1ae151SYishai Hadas 	__u8 set_parts_resource_objects_limit;
306*7c1ae151SYishai Hadas };
307*7c1ae151SYishai Hadas 
308*7c1ae151SYishai Hadas #define MAX_CAP_ID __KERNEL_DIV_ROUND_UP(VIRTIO_DEV_PARTS_CAP + 1, 64)
309*7c1ae151SYishai Hadas 
310*7c1ae151SYishai Hadas struct virtio_admin_cmd_query_cap_id_result {
311*7c1ae151SYishai Hadas 	__le64 supported_caps[MAX_CAP_ID];
312*7c1ae151SYishai Hadas };
313*7c1ae151SYishai Hadas 
314*7c1ae151SYishai Hadas struct virtio_admin_cmd_cap_get_data {
315*7c1ae151SYishai Hadas 	__le16 id;
316*7c1ae151SYishai Hadas 	__u8 reserved[6];
317*7c1ae151SYishai Hadas };
318*7c1ae151SYishai Hadas 
319*7c1ae151SYishai Hadas struct virtio_admin_cmd_cap_set_data {
320*7c1ae151SYishai Hadas 	__le16 id;
321*7c1ae151SYishai Hadas 	__u8 reserved[6];
322*7c1ae151SYishai Hadas 	__u8 cap_specific_data[];
323*7c1ae151SYishai Hadas };
324*7c1ae151SYishai Hadas 
325*7c1ae151SYishai Hadas struct virtio_admin_cmd_resource_obj_cmd_hdr {
326*7c1ae151SYishai Hadas 	__le16 type;
327*7c1ae151SYishai Hadas 	__u8 reserved[2];
328*7c1ae151SYishai Hadas 	__le32 id; /* Indicates unique resource object id per resource object type */
329*7c1ae151SYishai Hadas };
330*7c1ae151SYishai Hadas 
331*7c1ae151SYishai Hadas struct virtio_admin_cmd_resource_obj_create_data {
332*7c1ae151SYishai Hadas 	struct virtio_admin_cmd_resource_obj_cmd_hdr hdr;
333*7c1ae151SYishai Hadas 	__le64 flags;
334*7c1ae151SYishai Hadas 	__u8 resource_obj_specific_data[];
335*7c1ae151SYishai Hadas };
336*7c1ae151SYishai Hadas 
337*7c1ae151SYishai Hadas #define VIRTIO_RESOURCE_OBJ_DEV_PARTS 0
338*7c1ae151SYishai Hadas 
339*7c1ae151SYishai Hadas #define VIRTIO_RESOURCE_OBJ_DEV_PARTS_TYPE_GET 0
340*7c1ae151SYishai Hadas #define VIRTIO_RESOURCE_OBJ_DEV_PARTS_TYPE_SET 1
341*7c1ae151SYishai Hadas 
342*7c1ae151SYishai Hadas struct virtio_resource_obj_dev_parts {
343*7c1ae151SYishai Hadas 	__u8 type;
344*7c1ae151SYishai Hadas 	__u8 reserved[7];
345*7c1ae151SYishai Hadas };
346*7c1ae151SYishai Hadas 
347*7c1ae151SYishai Hadas #define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_TYPE_SIZE 0
348*7c1ae151SYishai Hadas #define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_TYPE_COUNT 1
349*7c1ae151SYishai Hadas #define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_TYPE_LIST 2
350*7c1ae151SYishai Hadas 
351*7c1ae151SYishai Hadas struct virtio_admin_cmd_dev_parts_metadata_data {
352*7c1ae151SYishai Hadas 	struct virtio_admin_cmd_resource_obj_cmd_hdr hdr;
353*7c1ae151SYishai Hadas 	__u8 type;
354*7c1ae151SYishai Hadas 	__u8 reserved[7];
355*7c1ae151SYishai Hadas };
356*7c1ae151SYishai Hadas 
357*7c1ae151SYishai Hadas #define VIRTIO_DEV_PART_F_OPTIONAL 0
358*7c1ae151SYishai Hadas 
359*7c1ae151SYishai Hadas struct virtio_dev_part_hdr {
360*7c1ae151SYishai Hadas 	__le16 part_type;
361*7c1ae151SYishai Hadas 	__u8 flags;
362*7c1ae151SYishai Hadas 	__u8 reserved;
363*7c1ae151SYishai Hadas 	union {
364*7c1ae151SYishai Hadas 		struct {
365*7c1ae151SYishai Hadas 			__le32 offset;
366*7c1ae151SYishai Hadas 			__le32 reserved;
367*7c1ae151SYishai Hadas 		} pci_common_cfg;
368*7c1ae151SYishai Hadas 		struct {
369*7c1ae151SYishai Hadas 			__le16 index;
370*7c1ae151SYishai Hadas 			__u8 reserved[6];
371*7c1ae151SYishai Hadas 		} vq_index;
372*7c1ae151SYishai Hadas 	} selector;
373*7c1ae151SYishai Hadas 	__le32 length;
374*7c1ae151SYishai Hadas };
375*7c1ae151SYishai Hadas 
376*7c1ae151SYishai Hadas struct virtio_dev_part {
377*7c1ae151SYishai Hadas 	struct virtio_dev_part_hdr hdr;
378*7c1ae151SYishai Hadas 	__u8 value[];
379*7c1ae151SYishai Hadas };
380*7c1ae151SYishai Hadas 
381*7c1ae151SYishai Hadas struct virtio_admin_cmd_dev_parts_metadata_result {
382*7c1ae151SYishai Hadas 	union {
383*7c1ae151SYishai Hadas 		struct {
384*7c1ae151SYishai Hadas 			__le32 size;
385*7c1ae151SYishai Hadas 			__le32 reserved;
386*7c1ae151SYishai Hadas 		} parts_size;
387*7c1ae151SYishai Hadas 		struct {
388*7c1ae151SYishai Hadas 			__le32 count;
389*7c1ae151SYishai Hadas 			__le32 reserved;
390*7c1ae151SYishai Hadas 		} hdr_list_count;
391*7c1ae151SYishai Hadas 		struct {
392*7c1ae151SYishai Hadas 			__le32 count;
393*7c1ae151SYishai Hadas 			__le32 reserved;
394*7c1ae151SYishai Hadas 			struct virtio_dev_part_hdr hdrs[];
395*7c1ae151SYishai Hadas 		} hdr_list;
396*7c1ae151SYishai Hadas 	};
397*7c1ae151SYishai Hadas };
398*7c1ae151SYishai Hadas 
399*7c1ae151SYishai Hadas #define VIRTIO_ADMIN_CMD_DEV_PARTS_GET_TYPE_SELECTED 0
400*7c1ae151SYishai Hadas #define VIRTIO_ADMIN_CMD_DEV_PARTS_GET_TYPE_ALL 1
401*7c1ae151SYishai Hadas 
402*7c1ae151SYishai Hadas struct virtio_admin_cmd_dev_parts_get_data {
403*7c1ae151SYishai Hadas 	struct virtio_admin_cmd_resource_obj_cmd_hdr hdr;
404*7c1ae151SYishai Hadas 	__u8 type;
405*7c1ae151SYishai Hadas 	__u8 reserved[7];
406*7c1ae151SYishai Hadas 	struct virtio_dev_part_hdr hdr_list[];
407*7c1ae151SYishai Hadas };
408*7c1ae151SYishai Hadas 
409*7c1ae151SYishai Hadas struct virtio_admin_cmd_dev_parts_set_data {
410*7c1ae151SYishai Hadas 	struct virtio_admin_cmd_resource_obj_cmd_hdr hdr;
411*7c1ae151SYishai Hadas 	struct virtio_dev_part parts[];
412*7c1ae151SYishai Hadas };
413*7c1ae151SYishai Hadas 
414*7c1ae151SYishai Hadas #define VIRTIO_ADMIN_CMD_DEV_MODE_F_STOPPED 0
415*7c1ae151SYishai Hadas 
416*7c1ae151SYishai Hadas struct virtio_admin_cmd_dev_mode_set_data {
417*7c1ae151SYishai Hadas 	__u8 flags;
418*7c1ae151SYishai Hadas };
419*7c1ae151SYishai Hadas 
420607ca46eSDavid Howells #endif
421