1 /* 2 * Virtio GPU Device 3 * 4 * Copyright Red Hat, Inc. 2013-2014 5 * 6 * Authors: 7 * Dave Airlie <[email protected]> 8 * Gerd Hoffmann <[email protected]> 9 * 10 * This header is BSD licensed so anyone can use the definitions 11 * to implement compatible drivers/servers: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. Neither the name of IBM nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL IBM OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 31 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 32 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 */ 37 38 #ifndef VIRTIO_GPU_HW_H 39 #define VIRTIO_GPU_HW_H 40 41 #include <linux/types.h> 42 43 /* 44 * VIRTIO_GPU_CMD_CTX_* 45 * VIRTIO_GPU_CMD_*_3D 46 */ 47 #define VIRTIO_GPU_F_VIRGL 0 48 49 /* 50 * VIRTIO_GPU_CMD_GET_EDID 51 */ 52 #define VIRTIO_GPU_F_EDID 1 53 /* 54 * VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID 55 */ 56 #define VIRTIO_GPU_F_RESOURCE_UUID 2 57 58 /* 59 * VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB 60 */ 61 #define VIRTIO_GPU_F_RESOURCE_BLOB 3 62 63 enum virtio_gpu_ctrl_type { 64 VIRTIO_GPU_UNDEFINED = 0, 65 66 /* 2d commands */ 67 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100, 68 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D, 69 VIRTIO_GPU_CMD_RESOURCE_UNREF, 70 VIRTIO_GPU_CMD_SET_SCANOUT, 71 VIRTIO_GPU_CMD_RESOURCE_FLUSH, 72 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D, 73 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING, 74 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING, 75 VIRTIO_GPU_CMD_GET_CAPSET_INFO, 76 VIRTIO_GPU_CMD_GET_CAPSET, 77 VIRTIO_GPU_CMD_GET_EDID, 78 VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID, 79 VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB, 80 VIRTIO_GPU_CMD_SET_SCANOUT_BLOB, 81 82 /* 3d commands */ 83 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200, 84 VIRTIO_GPU_CMD_CTX_DESTROY, 85 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, 86 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE, 87 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D, 88 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, 89 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D, 90 VIRTIO_GPU_CMD_SUBMIT_3D, 91 92 /* cursor commands */ 93 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300, 94 VIRTIO_GPU_CMD_MOVE_CURSOR, 95 96 /* success responses */ 97 VIRTIO_GPU_RESP_OK_NODATA = 0x1100, 98 VIRTIO_GPU_RESP_OK_DISPLAY_INFO, 99 VIRTIO_GPU_RESP_OK_CAPSET_INFO, 100 VIRTIO_GPU_RESP_OK_CAPSET, 101 VIRTIO_GPU_RESP_OK_EDID, 102 VIRTIO_GPU_RESP_OK_RESOURCE_UUID, 103 104 /* error responses */ 105 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200, 106 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY, 107 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID, 108 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID, 109 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID, 110 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER, 111 }; 112 113 #define VIRTIO_GPU_FLAG_FENCE (1 << 0) 114 115 struct virtio_gpu_ctrl_hdr { 116 __le32 type; 117 __le32 flags; 118 __le64 fence_id; 119 __le32 ctx_id; 120 __le32 padding; 121 }; 122 123 /* data passed in the cursor vq */ 124 125 struct virtio_gpu_cursor_pos { 126 __le32 scanout_id; 127 __le32 x; 128 __le32 y; 129 __le32 padding; 130 }; 131 132 /* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */ 133 struct virtio_gpu_update_cursor { 134 struct virtio_gpu_ctrl_hdr hdr; 135 struct virtio_gpu_cursor_pos pos; /* update & move */ 136 __le32 resource_id; /* update only */ 137 __le32 hot_x; /* update only */ 138 __le32 hot_y; /* update only */ 139 __le32 padding; 140 }; 141 142 /* data passed in the control vq, 2d related */ 143 144 struct virtio_gpu_rect { 145 __le32 x; 146 __le32 y; 147 __le32 width; 148 __le32 height; 149 }; 150 151 /* VIRTIO_GPU_CMD_RESOURCE_UNREF */ 152 struct virtio_gpu_resource_unref { 153 struct virtio_gpu_ctrl_hdr hdr; 154 __le32 resource_id; 155 __le32 padding; 156 }; 157 158 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */ 159 struct virtio_gpu_resource_create_2d { 160 struct virtio_gpu_ctrl_hdr hdr; 161 __le32 resource_id; 162 __le32 format; 163 __le32 width; 164 __le32 height; 165 }; 166 167 /* VIRTIO_GPU_CMD_SET_SCANOUT */ 168 struct virtio_gpu_set_scanout { 169 struct virtio_gpu_ctrl_hdr hdr; 170 struct virtio_gpu_rect r; 171 __le32 scanout_id; 172 __le32 resource_id; 173 }; 174 175 /* VIRTIO_GPU_CMD_RESOURCE_FLUSH */ 176 struct virtio_gpu_resource_flush { 177 struct virtio_gpu_ctrl_hdr hdr; 178 struct virtio_gpu_rect r; 179 __le32 resource_id; 180 __le32 padding; 181 }; 182 183 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */ 184 struct virtio_gpu_transfer_to_host_2d { 185 struct virtio_gpu_ctrl_hdr hdr; 186 struct virtio_gpu_rect r; 187 __le64 offset; 188 __le32 resource_id; 189 __le32 padding; 190 }; 191 192 struct virtio_gpu_mem_entry { 193 __le64 addr; 194 __le32 length; 195 __le32 padding; 196 }; 197 198 /* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */ 199 struct virtio_gpu_resource_attach_backing { 200 struct virtio_gpu_ctrl_hdr hdr; 201 __le32 resource_id; 202 __le32 nr_entries; 203 }; 204 205 /* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */ 206 struct virtio_gpu_resource_detach_backing { 207 struct virtio_gpu_ctrl_hdr hdr; 208 __le32 resource_id; 209 __le32 padding; 210 }; 211 212 /* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */ 213 #define VIRTIO_GPU_MAX_SCANOUTS 16 214 struct virtio_gpu_resp_display_info { 215 struct virtio_gpu_ctrl_hdr hdr; 216 struct virtio_gpu_display_one { 217 struct virtio_gpu_rect r; 218 __le32 enabled; 219 __le32 flags; 220 } pmodes[VIRTIO_GPU_MAX_SCANOUTS]; 221 }; 222 223 /* data passed in the control vq, 3d related */ 224 225 struct virtio_gpu_box { 226 __le32 x, y, z; 227 __le32 w, h, d; 228 }; 229 230 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */ 231 struct virtio_gpu_transfer_host_3d { 232 struct virtio_gpu_ctrl_hdr hdr; 233 struct virtio_gpu_box box; 234 __le64 offset; 235 __le32 resource_id; 236 __le32 level; 237 __le32 stride; 238 __le32 layer_stride; 239 }; 240 241 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */ 242 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0) 243 struct virtio_gpu_resource_create_3d { 244 struct virtio_gpu_ctrl_hdr hdr; 245 __le32 resource_id; 246 __le32 target; 247 __le32 format; 248 __le32 bind; 249 __le32 width; 250 __le32 height; 251 __le32 depth; 252 __le32 array_size; 253 __le32 last_level; 254 __le32 nr_samples; 255 __le32 flags; 256 __le32 padding; 257 }; 258 259 /* VIRTIO_GPU_CMD_CTX_CREATE */ 260 struct virtio_gpu_ctx_create { 261 struct virtio_gpu_ctrl_hdr hdr; 262 __le32 nlen; 263 __le32 padding; 264 char debug_name[64]; 265 }; 266 267 /* VIRTIO_GPU_CMD_CTX_DESTROY */ 268 struct virtio_gpu_ctx_destroy { 269 struct virtio_gpu_ctrl_hdr hdr; 270 }; 271 272 /* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */ 273 struct virtio_gpu_ctx_resource { 274 struct virtio_gpu_ctrl_hdr hdr; 275 __le32 resource_id; 276 __le32 padding; 277 }; 278 279 /* VIRTIO_GPU_CMD_SUBMIT_3D */ 280 struct virtio_gpu_cmd_submit { 281 struct virtio_gpu_ctrl_hdr hdr; 282 __le32 size; 283 __le32 padding; 284 }; 285 286 #define VIRTIO_GPU_CAPSET_VIRGL 1 287 #define VIRTIO_GPU_CAPSET_VIRGL2 2 288 289 /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */ 290 struct virtio_gpu_get_capset_info { 291 struct virtio_gpu_ctrl_hdr hdr; 292 __le32 capset_index; 293 __le32 padding; 294 }; 295 296 /* VIRTIO_GPU_RESP_OK_CAPSET_INFO */ 297 struct virtio_gpu_resp_capset_info { 298 struct virtio_gpu_ctrl_hdr hdr; 299 __le32 capset_id; 300 __le32 capset_max_version; 301 __le32 capset_max_size; 302 __le32 padding; 303 }; 304 305 /* VIRTIO_GPU_CMD_GET_CAPSET */ 306 struct virtio_gpu_get_capset { 307 struct virtio_gpu_ctrl_hdr hdr; 308 __le32 capset_id; 309 __le32 capset_version; 310 }; 311 312 /* VIRTIO_GPU_RESP_OK_CAPSET */ 313 struct virtio_gpu_resp_capset { 314 struct virtio_gpu_ctrl_hdr hdr; 315 __u8 capset_data[]; 316 }; 317 318 /* VIRTIO_GPU_CMD_GET_EDID */ 319 struct virtio_gpu_cmd_get_edid { 320 struct virtio_gpu_ctrl_hdr hdr; 321 __le32 scanout; 322 __le32 padding; 323 }; 324 325 /* VIRTIO_GPU_RESP_OK_EDID */ 326 struct virtio_gpu_resp_edid { 327 struct virtio_gpu_ctrl_hdr hdr; 328 __le32 size; 329 __le32 padding; 330 __u8 edid[1024]; 331 }; 332 333 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0) 334 335 struct virtio_gpu_config { 336 __le32 events_read; 337 __le32 events_clear; 338 __le32 num_scanouts; 339 __le32 num_capsets; 340 }; 341 342 /* simple formats for fbcon/X use */ 343 enum virtio_gpu_formats { 344 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1, 345 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2, 346 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3, 347 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4, 348 349 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67, 350 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68, 351 352 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121, 353 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134, 354 }; 355 356 /* VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID */ 357 struct virtio_gpu_resource_assign_uuid { 358 struct virtio_gpu_ctrl_hdr hdr; 359 __le32 resource_id; 360 __le32 padding; 361 }; 362 363 /* VIRTIO_GPU_RESP_OK_RESOURCE_UUID */ 364 struct virtio_gpu_resp_resource_uuid { 365 struct virtio_gpu_ctrl_hdr hdr; 366 __u8 uuid[16]; 367 }; 368 369 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB */ 370 struct virtio_gpu_resource_create_blob { 371 struct virtio_gpu_ctrl_hdr hdr; 372 __le32 resource_id; 373 #define VIRTIO_GPU_BLOB_MEM_GUEST 0x0001 374 #define VIRTIO_GPU_BLOB_MEM_HOST3D 0x0002 375 #define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST 0x0003 376 377 #define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE 0x0001 378 #define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE 0x0002 379 #define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004 380 /* zero is invalid blob mem */ 381 __le32 blob_mem; 382 __le32 blob_flags; 383 __le64 blob_id; 384 __le64 size; 385 __le32 nr_entries; 386 /* 387 * sizeof(nr_entries * virtio_gpu_mem_entry) bytes follow 388 */ 389 }; 390 391 /* VIRTIO_GPU_CMD_SET_SCANOUT_BLOB */ 392 struct virtio_gpu_set_scanout_blob { 393 struct virtio_gpu_ctrl_hdr hdr; 394 struct virtio_gpu_rect r; 395 __le32 scanout_id; 396 __le32 resource_id; 397 __le32 width; 398 __le32 height; 399 __le32 format; 400 __le32 padding; 401 __le32 strides[4]; 402 __le32 offsets[4]; 403 }; 404 405 #endif 406