1 /* 2 * Virtio GPU Device 3 * 4 * Copyright Red Hat, Inc. 2013-2014 5 * 6 * Authors: 7 * Dave Airlie <[email protected]> 8 * Gerd Hoffmann <[email protected]> 9 * 10 * This header is BSD licensed so anyone can use the definitions 11 * to implement compatible drivers/servers: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. Neither the name of IBM nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL IBM OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 31 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 32 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 */ 37 38 #ifndef VIRTIO_GPU_HW_H 39 #define VIRTIO_GPU_HW_H 40 41 #include <linux/types.h> 42 43 /* 44 * VIRTIO_GPU_CMD_CTX_* 45 * VIRTIO_GPU_CMD_*_3D 46 */ 47 #define VIRTIO_GPU_F_VIRGL 0 48 49 /* 50 * VIRTIO_GPU_CMD_GET_EDID 51 */ 52 #define VIRTIO_GPU_F_EDID 1 53 /* 54 * VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID 55 */ 56 #define VIRTIO_GPU_F_RESOURCE_UUID 2 57 58 /* 59 * VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB 60 */ 61 #define VIRTIO_GPU_F_RESOURCE_BLOB 3 62 63 enum virtio_gpu_ctrl_type { 64 VIRTIO_GPU_UNDEFINED = 0, 65 66 /* 2d commands */ 67 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100, 68 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D, 69 VIRTIO_GPU_CMD_RESOURCE_UNREF, 70 VIRTIO_GPU_CMD_SET_SCANOUT, 71 VIRTIO_GPU_CMD_RESOURCE_FLUSH, 72 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D, 73 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING, 74 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING, 75 VIRTIO_GPU_CMD_GET_CAPSET_INFO, 76 VIRTIO_GPU_CMD_GET_CAPSET, 77 VIRTIO_GPU_CMD_GET_EDID, 78 VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID, 79 VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB, 80 VIRTIO_GPU_CMD_SET_SCANOUT_BLOB, 81 82 /* 3d commands */ 83 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200, 84 VIRTIO_GPU_CMD_CTX_DESTROY, 85 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, 86 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE, 87 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D, 88 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, 89 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D, 90 VIRTIO_GPU_CMD_SUBMIT_3D, 91 VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB, 92 VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB, 93 94 /* cursor commands */ 95 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300, 96 VIRTIO_GPU_CMD_MOVE_CURSOR, 97 98 /* success responses */ 99 VIRTIO_GPU_RESP_OK_NODATA = 0x1100, 100 VIRTIO_GPU_RESP_OK_DISPLAY_INFO, 101 VIRTIO_GPU_RESP_OK_CAPSET_INFO, 102 VIRTIO_GPU_RESP_OK_CAPSET, 103 VIRTIO_GPU_RESP_OK_EDID, 104 VIRTIO_GPU_RESP_OK_RESOURCE_UUID, 105 VIRTIO_GPU_RESP_OK_MAP_INFO, 106 107 /* error responses */ 108 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200, 109 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY, 110 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID, 111 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID, 112 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID, 113 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER, 114 }; 115 116 enum virtio_gpu_shm_id { 117 VIRTIO_GPU_SHM_ID_UNDEFINED = 0, 118 VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1 119 }; 120 121 #define VIRTIO_GPU_FLAG_FENCE (1 << 0) 122 123 struct virtio_gpu_ctrl_hdr { 124 __le32 type; 125 __le32 flags; 126 __le64 fence_id; 127 __le32 ctx_id; 128 __le32 padding; 129 }; 130 131 /* data passed in the cursor vq */ 132 133 struct virtio_gpu_cursor_pos { 134 __le32 scanout_id; 135 __le32 x; 136 __le32 y; 137 __le32 padding; 138 }; 139 140 /* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */ 141 struct virtio_gpu_update_cursor { 142 struct virtio_gpu_ctrl_hdr hdr; 143 struct virtio_gpu_cursor_pos pos; /* update & move */ 144 __le32 resource_id; /* update only */ 145 __le32 hot_x; /* update only */ 146 __le32 hot_y; /* update only */ 147 __le32 padding; 148 }; 149 150 /* data passed in the control vq, 2d related */ 151 152 struct virtio_gpu_rect { 153 __le32 x; 154 __le32 y; 155 __le32 width; 156 __le32 height; 157 }; 158 159 /* VIRTIO_GPU_CMD_RESOURCE_UNREF */ 160 struct virtio_gpu_resource_unref { 161 struct virtio_gpu_ctrl_hdr hdr; 162 __le32 resource_id; 163 __le32 padding; 164 }; 165 166 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */ 167 struct virtio_gpu_resource_create_2d { 168 struct virtio_gpu_ctrl_hdr hdr; 169 __le32 resource_id; 170 __le32 format; 171 __le32 width; 172 __le32 height; 173 }; 174 175 /* VIRTIO_GPU_CMD_SET_SCANOUT */ 176 struct virtio_gpu_set_scanout { 177 struct virtio_gpu_ctrl_hdr hdr; 178 struct virtio_gpu_rect r; 179 __le32 scanout_id; 180 __le32 resource_id; 181 }; 182 183 /* VIRTIO_GPU_CMD_RESOURCE_FLUSH */ 184 struct virtio_gpu_resource_flush { 185 struct virtio_gpu_ctrl_hdr hdr; 186 struct virtio_gpu_rect r; 187 __le32 resource_id; 188 __le32 padding; 189 }; 190 191 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */ 192 struct virtio_gpu_transfer_to_host_2d { 193 struct virtio_gpu_ctrl_hdr hdr; 194 struct virtio_gpu_rect r; 195 __le64 offset; 196 __le32 resource_id; 197 __le32 padding; 198 }; 199 200 struct virtio_gpu_mem_entry { 201 __le64 addr; 202 __le32 length; 203 __le32 padding; 204 }; 205 206 /* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */ 207 struct virtio_gpu_resource_attach_backing { 208 struct virtio_gpu_ctrl_hdr hdr; 209 __le32 resource_id; 210 __le32 nr_entries; 211 }; 212 213 /* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */ 214 struct virtio_gpu_resource_detach_backing { 215 struct virtio_gpu_ctrl_hdr hdr; 216 __le32 resource_id; 217 __le32 padding; 218 }; 219 220 /* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */ 221 #define VIRTIO_GPU_MAX_SCANOUTS 16 222 struct virtio_gpu_resp_display_info { 223 struct virtio_gpu_ctrl_hdr hdr; 224 struct virtio_gpu_display_one { 225 struct virtio_gpu_rect r; 226 __le32 enabled; 227 __le32 flags; 228 } pmodes[VIRTIO_GPU_MAX_SCANOUTS]; 229 }; 230 231 /* data passed in the control vq, 3d related */ 232 233 struct virtio_gpu_box { 234 __le32 x, y, z; 235 __le32 w, h, d; 236 }; 237 238 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */ 239 struct virtio_gpu_transfer_host_3d { 240 struct virtio_gpu_ctrl_hdr hdr; 241 struct virtio_gpu_box box; 242 __le64 offset; 243 __le32 resource_id; 244 __le32 level; 245 __le32 stride; 246 __le32 layer_stride; 247 }; 248 249 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */ 250 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0) 251 struct virtio_gpu_resource_create_3d { 252 struct virtio_gpu_ctrl_hdr hdr; 253 __le32 resource_id; 254 __le32 target; 255 __le32 format; 256 __le32 bind; 257 __le32 width; 258 __le32 height; 259 __le32 depth; 260 __le32 array_size; 261 __le32 last_level; 262 __le32 nr_samples; 263 __le32 flags; 264 __le32 padding; 265 }; 266 267 /* VIRTIO_GPU_CMD_CTX_CREATE */ 268 struct virtio_gpu_ctx_create { 269 struct virtio_gpu_ctrl_hdr hdr; 270 __le32 nlen; 271 __le32 padding; 272 char debug_name[64]; 273 }; 274 275 /* VIRTIO_GPU_CMD_CTX_DESTROY */ 276 struct virtio_gpu_ctx_destroy { 277 struct virtio_gpu_ctrl_hdr hdr; 278 }; 279 280 /* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */ 281 struct virtio_gpu_ctx_resource { 282 struct virtio_gpu_ctrl_hdr hdr; 283 __le32 resource_id; 284 __le32 padding; 285 }; 286 287 /* VIRTIO_GPU_CMD_SUBMIT_3D */ 288 struct virtio_gpu_cmd_submit { 289 struct virtio_gpu_ctrl_hdr hdr; 290 __le32 size; 291 __le32 padding; 292 }; 293 294 #define VIRTIO_GPU_CAPSET_VIRGL 1 295 #define VIRTIO_GPU_CAPSET_VIRGL2 2 296 297 /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */ 298 struct virtio_gpu_get_capset_info { 299 struct virtio_gpu_ctrl_hdr hdr; 300 __le32 capset_index; 301 __le32 padding; 302 }; 303 304 /* VIRTIO_GPU_RESP_OK_CAPSET_INFO */ 305 struct virtio_gpu_resp_capset_info { 306 struct virtio_gpu_ctrl_hdr hdr; 307 __le32 capset_id; 308 __le32 capset_max_version; 309 __le32 capset_max_size; 310 __le32 padding; 311 }; 312 313 /* VIRTIO_GPU_CMD_GET_CAPSET */ 314 struct virtio_gpu_get_capset { 315 struct virtio_gpu_ctrl_hdr hdr; 316 __le32 capset_id; 317 __le32 capset_version; 318 }; 319 320 /* VIRTIO_GPU_RESP_OK_CAPSET */ 321 struct virtio_gpu_resp_capset { 322 struct virtio_gpu_ctrl_hdr hdr; 323 __u8 capset_data[]; 324 }; 325 326 /* VIRTIO_GPU_CMD_GET_EDID */ 327 struct virtio_gpu_cmd_get_edid { 328 struct virtio_gpu_ctrl_hdr hdr; 329 __le32 scanout; 330 __le32 padding; 331 }; 332 333 /* VIRTIO_GPU_RESP_OK_EDID */ 334 struct virtio_gpu_resp_edid { 335 struct virtio_gpu_ctrl_hdr hdr; 336 __le32 size; 337 __le32 padding; 338 __u8 edid[1024]; 339 }; 340 341 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0) 342 343 struct virtio_gpu_config { 344 __le32 events_read; 345 __le32 events_clear; 346 __le32 num_scanouts; 347 __le32 num_capsets; 348 }; 349 350 /* simple formats for fbcon/X use */ 351 enum virtio_gpu_formats { 352 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1, 353 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2, 354 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3, 355 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4, 356 357 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67, 358 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68, 359 360 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121, 361 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134, 362 }; 363 364 /* VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID */ 365 struct virtio_gpu_resource_assign_uuid { 366 struct virtio_gpu_ctrl_hdr hdr; 367 __le32 resource_id; 368 __le32 padding; 369 }; 370 371 /* VIRTIO_GPU_RESP_OK_RESOURCE_UUID */ 372 struct virtio_gpu_resp_resource_uuid { 373 struct virtio_gpu_ctrl_hdr hdr; 374 __u8 uuid[16]; 375 }; 376 377 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB */ 378 struct virtio_gpu_resource_create_blob { 379 struct virtio_gpu_ctrl_hdr hdr; 380 __le32 resource_id; 381 #define VIRTIO_GPU_BLOB_MEM_GUEST 0x0001 382 #define VIRTIO_GPU_BLOB_MEM_HOST3D 0x0002 383 #define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST 0x0003 384 385 #define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE 0x0001 386 #define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE 0x0002 387 #define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004 388 /* zero is invalid blob mem */ 389 __le32 blob_mem; 390 __le32 blob_flags; 391 __le64 blob_id; 392 __le64 size; 393 __le32 nr_entries; 394 /* 395 * sizeof(nr_entries * virtio_gpu_mem_entry) bytes follow 396 */ 397 }; 398 399 /* VIRTIO_GPU_CMD_SET_SCANOUT_BLOB */ 400 struct virtio_gpu_set_scanout_blob { 401 struct virtio_gpu_ctrl_hdr hdr; 402 struct virtio_gpu_rect r; 403 __le32 scanout_id; 404 __le32 resource_id; 405 __le32 width; 406 __le32 height; 407 __le32 format; 408 __le32 padding; 409 __le32 strides[4]; 410 __le32 offsets[4]; 411 }; 412 413 /* VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB */ 414 struct virtio_gpu_resource_map_blob { 415 struct virtio_gpu_ctrl_hdr hdr; 416 __le32 resource_id; 417 __le32 padding; 418 __le64 offset; 419 }; 420 421 /* VIRTIO_GPU_RESP_OK_MAP_INFO */ 422 #define VIRTIO_GPU_MAP_CACHE_MASK 0x0f 423 #define VIRTIO_GPU_MAP_CACHE_NONE 0x00 424 #define VIRTIO_GPU_MAP_CACHE_CACHED 0x01 425 #define VIRTIO_GPU_MAP_CACHE_UNCACHED 0x02 426 #define VIRTIO_GPU_MAP_CACHE_WC 0x03 427 struct virtio_gpu_resp_map_info { 428 struct virtio_gpu_ctrl_hdr hdr; 429 __u32 map_info; 430 __u32 padding; 431 }; 432 433 /* VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB */ 434 struct virtio_gpu_resource_unmap_blob { 435 struct virtio_gpu_ctrl_hdr hdr; 436 __le32 resource_id; 437 __le32 padding; 438 }; 439 440 #endif 441