1 /* 2 * Performance events: 3 * 4 * Copyright (C) 2008-2009, Thomas Gleixner <[email protected]> 5 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 6 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 7 * 8 * Data type definitions, declarations, prototypes. 9 * 10 * Started by: Thomas Gleixner and Ingo Molnar 11 * 12 * For licencing details see kernel-base/COPYING 13 */ 14 #ifndef _UAPI_LINUX_PERF_EVENT_H 15 #define _UAPI_LINUX_PERF_EVENT_H 16 17 #include <linux/types.h> 18 #include <linux/ioctl.h> 19 #include <asm/byteorder.h> 20 21 /* 22 * User-space ABI bits: 23 */ 24 25 /* 26 * attr.type 27 */ 28 enum perf_type_id { 29 PERF_TYPE_HARDWARE = 0, 30 PERF_TYPE_SOFTWARE = 1, 31 PERF_TYPE_TRACEPOINT = 2, 32 PERF_TYPE_HW_CACHE = 3, 33 PERF_TYPE_RAW = 4, 34 PERF_TYPE_BREAKPOINT = 5, 35 36 PERF_TYPE_MAX, /* non-ABI */ 37 }; 38 39 /* 40 * Generalized performance event event_id types, used by the 41 * attr.event_id parameter of the sys_perf_event_open() 42 * syscall: 43 */ 44 enum perf_hw_id { 45 /* 46 * Common hardware events, generalized by the kernel: 47 */ 48 PERF_COUNT_HW_CPU_CYCLES = 0, 49 PERF_COUNT_HW_INSTRUCTIONS = 1, 50 PERF_COUNT_HW_CACHE_REFERENCES = 2, 51 PERF_COUNT_HW_CACHE_MISSES = 3, 52 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 53 PERF_COUNT_HW_BRANCH_MISSES = 5, 54 PERF_COUNT_HW_BUS_CYCLES = 6, 55 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 56 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 57 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 58 59 PERF_COUNT_HW_MAX, /* non-ABI */ 60 }; 61 62 /* 63 * Generalized hardware cache events: 64 * 65 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 66 * { read, write, prefetch } x 67 * { accesses, misses } 68 */ 69 enum perf_hw_cache_id { 70 PERF_COUNT_HW_CACHE_L1D = 0, 71 PERF_COUNT_HW_CACHE_L1I = 1, 72 PERF_COUNT_HW_CACHE_LL = 2, 73 PERF_COUNT_HW_CACHE_DTLB = 3, 74 PERF_COUNT_HW_CACHE_ITLB = 4, 75 PERF_COUNT_HW_CACHE_BPU = 5, 76 PERF_COUNT_HW_CACHE_NODE = 6, 77 78 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 79 }; 80 81 enum perf_hw_cache_op_id { 82 PERF_COUNT_HW_CACHE_OP_READ = 0, 83 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 84 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 85 86 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 87 }; 88 89 enum perf_hw_cache_op_result_id { 90 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 91 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 92 93 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 94 }; 95 96 /* 97 * Special "software" events provided by the kernel, even if the hardware 98 * does not support performance events. These events measure various 99 * physical and sw events of the kernel (and allow the profiling of them as 100 * well): 101 */ 102 enum perf_sw_ids { 103 PERF_COUNT_SW_CPU_CLOCK = 0, 104 PERF_COUNT_SW_TASK_CLOCK = 1, 105 PERF_COUNT_SW_PAGE_FAULTS = 2, 106 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 107 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 108 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 109 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 110 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 111 PERF_COUNT_SW_EMULATION_FAULTS = 8, 112 PERF_COUNT_SW_DUMMY = 9, 113 PERF_COUNT_SW_BPF_OUTPUT = 10, 114 115 PERF_COUNT_SW_MAX, /* non-ABI */ 116 }; 117 118 /* 119 * Bits that can be set in attr.sample_type to request information 120 * in the overflow packets. 121 */ 122 enum perf_event_sample_format { 123 PERF_SAMPLE_IP = 1U << 0, 124 PERF_SAMPLE_TID = 1U << 1, 125 PERF_SAMPLE_TIME = 1U << 2, 126 PERF_SAMPLE_ADDR = 1U << 3, 127 PERF_SAMPLE_READ = 1U << 4, 128 PERF_SAMPLE_CALLCHAIN = 1U << 5, 129 PERF_SAMPLE_ID = 1U << 6, 130 PERF_SAMPLE_CPU = 1U << 7, 131 PERF_SAMPLE_PERIOD = 1U << 8, 132 PERF_SAMPLE_STREAM_ID = 1U << 9, 133 PERF_SAMPLE_RAW = 1U << 10, 134 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 135 PERF_SAMPLE_REGS_USER = 1U << 12, 136 PERF_SAMPLE_STACK_USER = 1U << 13, 137 PERF_SAMPLE_WEIGHT = 1U << 14, 138 PERF_SAMPLE_DATA_SRC = 1U << 15, 139 PERF_SAMPLE_IDENTIFIER = 1U << 16, 140 PERF_SAMPLE_TRANSACTION = 1U << 17, 141 PERF_SAMPLE_REGS_INTR = 1U << 18, 142 PERF_SAMPLE_PHYS_ADDR = 1U << 19, 143 144 PERF_SAMPLE_MAX = 1U << 20, /* non-ABI */ 145 }; 146 147 /* 148 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set 149 * 150 * If the user does not pass priv level information via branch_sample_type, 151 * the kernel uses the event's priv level. Branch and event priv levels do 152 * not have to match. Branch priv level is checked for permissions. 153 * 154 * The branch types can be combined, however BRANCH_ANY covers all types 155 * of branches and therefore it supersedes all the other types. 156 */ 157 enum perf_branch_sample_type_shift { 158 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ 159 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ 160 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ 161 162 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ 163 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ 164 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ 165 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ 166 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ 167 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ 168 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ 169 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ 170 171 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */ 172 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */ 173 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */ 174 175 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */ 176 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */ 177 178 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */ 179 180 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ 181 }; 182 183 enum perf_branch_sample_type { 184 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 185 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 186 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 187 188 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 189 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 190 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 191 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 192 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 193 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 194 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 195 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 196 197 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 198 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, 199 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 200 201 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, 202 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 203 204 PERF_SAMPLE_BRANCH_TYPE_SAVE = 205 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, 206 207 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 208 }; 209 210 /* 211 * Common flow change classification 212 */ 213 enum { 214 PERF_BR_UNKNOWN = 0, /* unknown */ 215 PERF_BR_COND = 1, /* conditional */ 216 PERF_BR_UNCOND = 2, /* unconditional */ 217 PERF_BR_IND = 3, /* indirect */ 218 PERF_BR_CALL = 4, /* function call */ 219 PERF_BR_IND_CALL = 5, /* indirect function call */ 220 PERF_BR_RET = 6, /* function return */ 221 PERF_BR_SYSCALL = 7, /* syscall */ 222 PERF_BR_SYSRET = 8, /* syscall return */ 223 PERF_BR_COND_CALL = 9, /* conditional function call */ 224 PERF_BR_COND_RET = 10, /* conditional function return */ 225 PERF_BR_MAX, 226 }; 227 228 #define PERF_SAMPLE_BRANCH_PLM_ALL \ 229 (PERF_SAMPLE_BRANCH_USER|\ 230 PERF_SAMPLE_BRANCH_KERNEL|\ 231 PERF_SAMPLE_BRANCH_HV) 232 233 /* 234 * Values to determine ABI of the registers dump. 235 */ 236 enum perf_sample_regs_abi { 237 PERF_SAMPLE_REGS_ABI_NONE = 0, 238 PERF_SAMPLE_REGS_ABI_32 = 1, 239 PERF_SAMPLE_REGS_ABI_64 = 2, 240 }; 241 242 /* 243 * Values for the memory transaction event qualifier, mostly for 244 * abort events. Multiple bits can be set. 245 */ 246 enum { 247 PERF_TXN_ELISION = (1 << 0), /* From elision */ 248 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ 249 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ 250 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ 251 PERF_TXN_RETRY = (1 << 4), /* Retry possible */ 252 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ 253 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ 254 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ 255 256 PERF_TXN_MAX = (1 << 8), /* non-ABI */ 257 258 /* bits 32..63 are reserved for the abort code */ 259 260 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 261 PERF_TXN_ABORT_SHIFT = 32, 262 }; 263 264 /* 265 * The format of the data returned by read() on a perf event fd, 266 * as specified by attr.read_format: 267 * 268 * struct read_format { 269 * { u64 value; 270 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 271 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 272 * { u64 id; } && PERF_FORMAT_ID 273 * } && !PERF_FORMAT_GROUP 274 * 275 * { u64 nr; 276 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 277 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 278 * { u64 value; 279 * { u64 id; } && PERF_FORMAT_ID 280 * } cntr[nr]; 281 * } && PERF_FORMAT_GROUP 282 * }; 283 */ 284 enum perf_event_read_format { 285 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 286 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 287 PERF_FORMAT_ID = 1U << 2, 288 PERF_FORMAT_GROUP = 1U << 3, 289 290 PERF_FORMAT_MAX = 1U << 4, /* non-ABI */ 291 }; 292 293 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ 294 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ 295 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ 296 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ 297 /* add: sample_stack_user */ 298 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ 299 #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ 300 301 /* 302 * Hardware event_id to monitor via a performance monitoring event: 303 * 304 * @sample_max_stack: Max number of frame pointers in a callchain, 305 * should be < /proc/sys/kernel/perf_event_max_stack 306 */ 307 struct perf_event_attr { 308 309 /* 310 * Major type: hardware/software/tracepoint/etc. 311 */ 312 __u32 type; 313 314 /* 315 * Size of the attr structure, for fwd/bwd compat. 316 */ 317 __u32 size; 318 319 /* 320 * Type specific configuration information. 321 */ 322 __u64 config; 323 324 union { 325 __u64 sample_period; 326 __u64 sample_freq; 327 }; 328 329 __u64 sample_type; 330 __u64 read_format; 331 332 __u64 disabled : 1, /* off by default */ 333 inherit : 1, /* children inherit it */ 334 pinned : 1, /* must always be on PMU */ 335 exclusive : 1, /* only group on PMU */ 336 exclude_user : 1, /* don't count user */ 337 exclude_kernel : 1, /* ditto kernel */ 338 exclude_hv : 1, /* ditto hypervisor */ 339 exclude_idle : 1, /* don't count when idle */ 340 mmap : 1, /* include mmap data */ 341 comm : 1, /* include comm data */ 342 freq : 1, /* use freq, not period */ 343 inherit_stat : 1, /* per task counts */ 344 enable_on_exec : 1, /* next exec enables */ 345 task : 1, /* trace fork/exit */ 346 watermark : 1, /* wakeup_watermark */ 347 /* 348 * precise_ip: 349 * 350 * 0 - SAMPLE_IP can have arbitrary skid 351 * 1 - SAMPLE_IP must have constant skid 352 * 2 - SAMPLE_IP requested to have 0 skid 353 * 3 - SAMPLE_IP must have 0 skid 354 * 355 * See also PERF_RECORD_MISC_EXACT_IP 356 */ 357 precise_ip : 2, /* skid constraint */ 358 mmap_data : 1, /* non-exec mmap data */ 359 sample_id_all : 1, /* sample_type all events */ 360 361 exclude_host : 1, /* don't count in host */ 362 exclude_guest : 1, /* don't count in guest */ 363 364 exclude_callchain_kernel : 1, /* exclude kernel callchains */ 365 exclude_callchain_user : 1, /* exclude user callchains */ 366 mmap2 : 1, /* include mmap with inode data */ 367 comm_exec : 1, /* flag comm events that are due to an exec */ 368 use_clockid : 1, /* use @clockid for time fields */ 369 context_switch : 1, /* context switch data */ 370 write_backward : 1, /* Write ring buffer from end to beginning */ 371 namespaces : 1, /* include namespaces data */ 372 __reserved_1 : 35; 373 374 union { 375 __u32 wakeup_events; /* wakeup every n events */ 376 __u32 wakeup_watermark; /* bytes before wakeup */ 377 }; 378 379 __u32 bp_type; 380 union { 381 __u64 bp_addr; 382 __u64 config1; /* extension of config */ 383 }; 384 union { 385 __u64 bp_len; 386 __u64 config2; /* extension of config1 */ 387 }; 388 __u64 branch_sample_type; /* enum perf_branch_sample_type */ 389 390 /* 391 * Defines set of user regs to dump on samples. 392 * See asm/perf_regs.h for details. 393 */ 394 __u64 sample_regs_user; 395 396 /* 397 * Defines size of the user stack to dump on samples. 398 */ 399 __u32 sample_stack_user; 400 401 __s32 clockid; 402 /* 403 * Defines set of regs to dump for each sample 404 * state captured on: 405 * - precise = 0: PMU interrupt 406 * - precise > 0: sampled instruction 407 * 408 * See asm/perf_regs.h for details. 409 */ 410 __u64 sample_regs_intr; 411 412 /* 413 * Wakeup watermark for AUX area 414 */ 415 __u32 aux_watermark; 416 __u16 sample_max_stack; 417 __u16 __reserved_2; /* align to __u64 */ 418 }; 419 420 #define perf_flags(attr) (*(&(attr)->read_format + 1)) 421 422 /* 423 * Ioctls that can be done on a perf event fd: 424 */ 425 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 426 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 427 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 428 #define PERF_EVENT_IOC_RESET _IO ('$', 3) 429 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 430 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 431 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 432 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 433 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) 434 #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) 435 436 enum perf_event_ioc_flags { 437 PERF_IOC_FLAG_GROUP = 1U << 0, 438 }; 439 440 /* 441 * Structure of the page that can be mapped via mmap 442 */ 443 struct perf_event_mmap_page { 444 __u32 version; /* version number of this structure */ 445 __u32 compat_version; /* lowest version this is compat with */ 446 447 /* 448 * Bits needed to read the hw events in user-space. 449 * 450 * u32 seq, time_mult, time_shift, index, width; 451 * u64 count, enabled, running; 452 * u64 cyc, time_offset; 453 * s64 pmc = 0; 454 * 455 * do { 456 * seq = pc->lock; 457 * barrier() 458 * 459 * enabled = pc->time_enabled; 460 * running = pc->time_running; 461 * 462 * if (pc->cap_usr_time && enabled != running) { 463 * cyc = rdtsc(); 464 * time_offset = pc->time_offset; 465 * time_mult = pc->time_mult; 466 * time_shift = pc->time_shift; 467 * } 468 * 469 * index = pc->index; 470 * count = pc->offset; 471 * if (pc->cap_user_rdpmc && index) { 472 * width = pc->pmc_width; 473 * pmc = rdpmc(index - 1); 474 * } 475 * 476 * barrier(); 477 * } while (pc->lock != seq); 478 * 479 * NOTE: for obvious reason this only works on self-monitoring 480 * processes. 481 */ 482 __u32 lock; /* seqlock for synchronization */ 483 __u32 index; /* hardware event identifier */ 484 __s64 offset; /* add to hardware event value */ 485 __u64 time_enabled; /* time event active */ 486 __u64 time_running; /* time event on cpu */ 487 union { 488 __u64 capabilities; 489 struct { 490 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ 491 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ 492 493 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ 494 cap_user_time : 1, /* The time_* fields are used */ 495 cap_user_time_zero : 1, /* The time_zero field is used */ 496 cap_____res : 59; 497 }; 498 }; 499 500 /* 501 * If cap_user_rdpmc this field provides the bit-width of the value 502 * read using the rdpmc() or equivalent instruction. This can be used 503 * to sign extend the result like: 504 * 505 * pmc <<= 64 - width; 506 * pmc >>= 64 - width; // signed shift right 507 * count += pmc; 508 */ 509 __u16 pmc_width; 510 511 /* 512 * If cap_usr_time the below fields can be used to compute the time 513 * delta since time_enabled (in ns) using rdtsc or similar. 514 * 515 * u64 quot, rem; 516 * u64 delta; 517 * 518 * quot = (cyc >> time_shift); 519 * rem = cyc & (((u64)1 << time_shift) - 1); 520 * delta = time_offset + quot * time_mult + 521 * ((rem * time_mult) >> time_shift); 522 * 523 * Where time_offset,time_mult,time_shift and cyc are read in the 524 * seqcount loop described above. This delta can then be added to 525 * enabled and possible running (if index), improving the scaling: 526 * 527 * enabled += delta; 528 * if (index) 529 * running += delta; 530 * 531 * quot = count / running; 532 * rem = count % running; 533 * count = quot * enabled + (rem * enabled) / running; 534 */ 535 __u16 time_shift; 536 __u32 time_mult; 537 __u64 time_offset; 538 /* 539 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated 540 * from sample timestamps. 541 * 542 * time = timestamp - time_zero; 543 * quot = time / time_mult; 544 * rem = time % time_mult; 545 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; 546 * 547 * And vice versa: 548 * 549 * quot = cyc >> time_shift; 550 * rem = cyc & (((u64)1 << time_shift) - 1); 551 * timestamp = time_zero + quot * time_mult + 552 * ((rem * time_mult) >> time_shift); 553 */ 554 __u64 time_zero; 555 __u32 size; /* Header size up to __reserved[] fields. */ 556 557 /* 558 * Hole for extension of the self monitor capabilities 559 */ 560 561 __u8 __reserved[118*8+4]; /* align to 1k. */ 562 563 /* 564 * Control data for the mmap() data buffer. 565 * 566 * User-space reading the @data_head value should issue an smp_rmb(), 567 * after reading this value. 568 * 569 * When the mapping is PROT_WRITE the @data_tail value should be 570 * written by userspace to reflect the last read data, after issueing 571 * an smp_mb() to separate the data read from the ->data_tail store. 572 * In this case the kernel will not over-write unread data. 573 * 574 * See perf_output_put_handle() for the data ordering. 575 * 576 * data_{offset,size} indicate the location and size of the perf record 577 * buffer within the mmapped area. 578 */ 579 __u64 data_head; /* head in the data section */ 580 __u64 data_tail; /* user-space written tail */ 581 __u64 data_offset; /* where the buffer starts */ 582 __u64 data_size; /* data buffer size */ 583 584 /* 585 * AUX area is defined by aux_{offset,size} fields that should be set 586 * by the userspace, so that 587 * 588 * aux_offset >= data_offset + data_size 589 * 590 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size. 591 * 592 * Ring buffer pointers aux_{head,tail} have the same semantics as 593 * data_{head,tail} and same ordering rules apply. 594 */ 595 __u64 aux_head; 596 __u64 aux_tail; 597 __u64 aux_offset; 598 __u64 aux_size; 599 }; 600 601 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 602 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 603 #define PERF_RECORD_MISC_KERNEL (1 << 0) 604 #define PERF_RECORD_MISC_USER (2 << 0) 605 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 606 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 607 #define PERF_RECORD_MISC_GUEST_USER (5 << 0) 608 609 /* 610 * Indicates that /proc/PID/maps parsing are truncated by time out. 611 */ 612 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) 613 /* 614 * PERF_RECORD_MISC_MMAP_DATA and PERF_RECORD_MISC_COMM_EXEC are used on 615 * different events so can reuse the same bit position. 616 * Ditto PERF_RECORD_MISC_SWITCH_OUT. 617 */ 618 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 619 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 620 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) 621 /* 622 * Indicates that the content of PERF_SAMPLE_IP points to 623 * the actual instruction that triggered the event. See also 624 * perf_event_attr::precise_ip. 625 */ 626 #define PERF_RECORD_MISC_EXACT_IP (1 << 14) 627 /* 628 * Reserve the last bit to indicate some extended misc field 629 */ 630 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 631 632 struct perf_event_header { 633 __u32 type; 634 __u16 misc; 635 __u16 size; 636 }; 637 638 struct perf_ns_link_info { 639 __u64 dev; 640 __u64 ino; 641 }; 642 643 enum { 644 NET_NS_INDEX = 0, 645 UTS_NS_INDEX = 1, 646 IPC_NS_INDEX = 2, 647 PID_NS_INDEX = 3, 648 USER_NS_INDEX = 4, 649 MNT_NS_INDEX = 5, 650 CGROUP_NS_INDEX = 6, 651 652 NR_NAMESPACES, /* number of available namespaces */ 653 }; 654 655 enum perf_event_type { 656 657 /* 658 * If perf_event_attr.sample_id_all is set then all event types will 659 * have the sample_type selected fields related to where/when 660 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, 661 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed 662 * just after the perf_event_header and the fields already present for 663 * the existing fields, i.e. at the end of the payload. That way a newer 664 * perf.data file will be supported by older perf tools, with these new 665 * optional fields being ignored. 666 * 667 * struct sample_id { 668 * { u32 pid, tid; } && PERF_SAMPLE_TID 669 * { u64 time; } && PERF_SAMPLE_TIME 670 * { u64 id; } && PERF_SAMPLE_ID 671 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 672 * { u32 cpu, res; } && PERF_SAMPLE_CPU 673 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 674 * } && perf_event_attr::sample_id_all 675 * 676 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The 677 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed 678 * relative to header.size. 679 */ 680 681 /* 682 * The MMAP events record the PROT_EXEC mappings so that we can 683 * correlate userspace IPs to code. They have the following structure: 684 * 685 * struct { 686 * struct perf_event_header header; 687 * 688 * u32 pid, tid; 689 * u64 addr; 690 * u64 len; 691 * u64 pgoff; 692 * char filename[]; 693 * struct sample_id sample_id; 694 * }; 695 */ 696 PERF_RECORD_MMAP = 1, 697 698 /* 699 * struct { 700 * struct perf_event_header header; 701 * u64 id; 702 * u64 lost; 703 * struct sample_id sample_id; 704 * }; 705 */ 706 PERF_RECORD_LOST = 2, 707 708 /* 709 * struct { 710 * struct perf_event_header header; 711 * 712 * u32 pid, tid; 713 * char comm[]; 714 * struct sample_id sample_id; 715 * }; 716 */ 717 PERF_RECORD_COMM = 3, 718 719 /* 720 * struct { 721 * struct perf_event_header header; 722 * u32 pid, ppid; 723 * u32 tid, ptid; 724 * u64 time; 725 * struct sample_id sample_id; 726 * }; 727 */ 728 PERF_RECORD_EXIT = 4, 729 730 /* 731 * struct { 732 * struct perf_event_header header; 733 * u64 time; 734 * u64 id; 735 * u64 stream_id; 736 * struct sample_id sample_id; 737 * }; 738 */ 739 PERF_RECORD_THROTTLE = 5, 740 PERF_RECORD_UNTHROTTLE = 6, 741 742 /* 743 * struct { 744 * struct perf_event_header header; 745 * u32 pid, ppid; 746 * u32 tid, ptid; 747 * u64 time; 748 * struct sample_id sample_id; 749 * }; 750 */ 751 PERF_RECORD_FORK = 7, 752 753 /* 754 * struct { 755 * struct perf_event_header header; 756 * u32 pid, tid; 757 * 758 * struct read_format values; 759 * struct sample_id sample_id; 760 * }; 761 */ 762 PERF_RECORD_READ = 8, 763 764 /* 765 * struct { 766 * struct perf_event_header header; 767 * 768 * # 769 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. 770 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position 771 * # is fixed relative to header. 772 * # 773 * 774 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 775 * { u64 ip; } && PERF_SAMPLE_IP 776 * { u32 pid, tid; } && PERF_SAMPLE_TID 777 * { u64 time; } && PERF_SAMPLE_TIME 778 * { u64 addr; } && PERF_SAMPLE_ADDR 779 * { u64 id; } && PERF_SAMPLE_ID 780 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 781 * { u32 cpu, res; } && PERF_SAMPLE_CPU 782 * { u64 period; } && PERF_SAMPLE_PERIOD 783 * 784 * { struct read_format values; } && PERF_SAMPLE_READ 785 * 786 * { u64 nr, 787 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 788 * 789 * # 790 * # The RAW record below is opaque data wrt the ABI 791 * # 792 * # That is, the ABI doesn't make any promises wrt to 793 * # the stability of its content, it may vary depending 794 * # on event, hardware, kernel version and phase of 795 * # the moon. 796 * # 797 * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 798 * # 799 * 800 * { u32 size; 801 * char data[size];}&& PERF_SAMPLE_RAW 802 * 803 * { u64 nr; 804 * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK 805 * 806 * { u64 abi; # enum perf_sample_regs_abi 807 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER 808 * 809 * { u64 size; 810 * char data[size]; 811 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 812 * 813 * { u64 weight; } && PERF_SAMPLE_WEIGHT 814 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 815 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION 816 * { u64 abi; # enum perf_sample_regs_abi 817 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR 818 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR 819 * }; 820 */ 821 PERF_RECORD_SAMPLE = 9, 822 823 /* 824 * The MMAP2 records are an augmented version of MMAP, they add 825 * maj, min, ino numbers to be used to uniquely identify each mapping 826 * 827 * struct { 828 * struct perf_event_header header; 829 * 830 * u32 pid, tid; 831 * u64 addr; 832 * u64 len; 833 * u64 pgoff; 834 * u32 maj; 835 * u32 min; 836 * u64 ino; 837 * u64 ino_generation; 838 * u32 prot, flags; 839 * char filename[]; 840 * struct sample_id sample_id; 841 * }; 842 */ 843 PERF_RECORD_MMAP2 = 10, 844 845 /* 846 * Records that new data landed in the AUX buffer part. 847 * 848 * struct { 849 * struct perf_event_header header; 850 * 851 * u64 aux_offset; 852 * u64 aux_size; 853 * u64 flags; 854 * struct sample_id sample_id; 855 * }; 856 */ 857 PERF_RECORD_AUX = 11, 858 859 /* 860 * Indicates that instruction trace has started 861 * 862 * struct { 863 * struct perf_event_header header; 864 * u32 pid; 865 * u32 tid; 866 * }; 867 */ 868 PERF_RECORD_ITRACE_START = 12, 869 870 /* 871 * Records the dropped/lost sample number. 872 * 873 * struct { 874 * struct perf_event_header header; 875 * 876 * u64 lost; 877 * struct sample_id sample_id; 878 * }; 879 */ 880 PERF_RECORD_LOST_SAMPLES = 13, 881 882 /* 883 * Records a context switch in or out (flagged by 884 * PERF_RECORD_MISC_SWITCH_OUT). See also 885 * PERF_RECORD_SWITCH_CPU_WIDE. 886 * 887 * struct { 888 * struct perf_event_header header; 889 * struct sample_id sample_id; 890 * }; 891 */ 892 PERF_RECORD_SWITCH = 14, 893 894 /* 895 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and 896 * next_prev_tid that are the next (switching out) or previous 897 * (switching in) pid/tid. 898 * 899 * struct { 900 * struct perf_event_header header; 901 * u32 next_prev_pid; 902 * u32 next_prev_tid; 903 * struct sample_id sample_id; 904 * }; 905 */ 906 PERF_RECORD_SWITCH_CPU_WIDE = 15, 907 908 /* 909 * struct { 910 * struct perf_event_header header; 911 * u32 pid; 912 * u32 tid; 913 * u64 nr_namespaces; 914 * { u64 dev, inode; } [nr_namespaces]; 915 * struct sample_id sample_id; 916 * }; 917 */ 918 PERF_RECORD_NAMESPACES = 16, 919 920 PERF_RECORD_MAX, /* non-ABI */ 921 }; 922 923 #define PERF_MAX_STACK_DEPTH 127 924 #define PERF_MAX_CONTEXTS_PER_STACK 8 925 926 enum perf_callchain_context { 927 PERF_CONTEXT_HV = (__u64)-32, 928 PERF_CONTEXT_KERNEL = (__u64)-128, 929 PERF_CONTEXT_USER = (__u64)-512, 930 931 PERF_CONTEXT_GUEST = (__u64)-2048, 932 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 933 PERF_CONTEXT_GUEST_USER = (__u64)-2560, 934 935 PERF_CONTEXT_MAX = (__u64)-4095, 936 }; 937 938 /** 939 * PERF_RECORD_AUX::flags bits 940 */ 941 #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ 942 #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ 943 #define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ 944 945 #define PERF_FLAG_FD_NO_GROUP (1UL << 0) 946 #define PERF_FLAG_FD_OUTPUT (1UL << 1) 947 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ 948 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ 949 950 #if defined(__LITTLE_ENDIAN_BITFIELD) 951 union perf_mem_data_src { 952 __u64 val; 953 struct { 954 __u64 mem_op:5, /* type of opcode */ 955 mem_lvl:14, /* memory hierarchy level */ 956 mem_snoop:5, /* snoop mode */ 957 mem_lock:2, /* lock instr */ 958 mem_dtlb:7, /* tlb access */ 959 mem_lvl_num:4, /* memory hierarchy level number */ 960 mem_remote:1, /* remote */ 961 mem_snoopx:2, /* snoop mode, ext */ 962 mem_rsvd:24; 963 }; 964 }; 965 #elif defined(__BIG_ENDIAN_BITFIELD) 966 union perf_mem_data_src { 967 __u64 val; 968 struct { 969 __u64 mem_rsvd:24, 970 mem_snoopx:2, /* snoop mode, ext */ 971 mem_remote:1, /* remote */ 972 mem_lvl_num:4, /* memory hierarchy level number */ 973 mem_dtlb:7, /* tlb access */ 974 mem_lock:2, /* lock instr */ 975 mem_snoop:5, /* snoop mode */ 976 mem_lvl:14, /* memory hierarchy level */ 977 mem_op:5; /* type of opcode */ 978 }; 979 }; 980 #else 981 #error "Unknown endianness" 982 #endif 983 984 /* type of opcode (load/store/prefetch,code) */ 985 #define PERF_MEM_OP_NA 0x01 /* not available */ 986 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */ 987 #define PERF_MEM_OP_STORE 0x04 /* store instruction */ 988 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ 989 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ 990 #define PERF_MEM_OP_SHIFT 0 991 992 /* memory hierarchy (memory level, hit or miss) */ 993 #define PERF_MEM_LVL_NA 0x01 /* not available */ 994 #define PERF_MEM_LVL_HIT 0x02 /* hit level */ 995 #define PERF_MEM_LVL_MISS 0x04 /* miss level */ 996 #define PERF_MEM_LVL_L1 0x08 /* L1 */ 997 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ 998 #define PERF_MEM_LVL_L2 0x20 /* L2 */ 999 #define PERF_MEM_LVL_L3 0x40 /* L3 */ 1000 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ 1001 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ 1002 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ 1003 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ 1004 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ 1005 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 1006 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 1007 #define PERF_MEM_LVL_SHIFT 5 1008 1009 #define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */ 1010 #define PERF_MEM_REMOTE_SHIFT 37 1011 1012 #define PERF_MEM_LVLNUM_L1 0x01 /* L1 */ 1013 #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ 1014 #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ 1015 #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ 1016 /* 5-0xa available */ 1017 #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ 1018 #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ 1019 #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ 1020 #define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */ 1021 #define PERF_MEM_LVLNUM_NA 0x0f /* N/A */ 1022 1023 #define PERF_MEM_LVLNUM_SHIFT 33 1024 1025 /* snoop mode */ 1026 #define PERF_MEM_SNOOP_NA 0x01 /* not available */ 1027 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ 1028 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ 1029 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ 1030 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ 1031 #define PERF_MEM_SNOOP_SHIFT 19 1032 1033 #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ 1034 /* 1 free */ 1035 #define PERF_MEM_SNOOPX_SHIFT 37 1036 1037 /* locked instruction */ 1038 #define PERF_MEM_LOCK_NA 0x01 /* not available */ 1039 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ 1040 #define PERF_MEM_LOCK_SHIFT 24 1041 1042 /* TLB access */ 1043 #define PERF_MEM_TLB_NA 0x01 /* not available */ 1044 #define PERF_MEM_TLB_HIT 0x02 /* hit level */ 1045 #define PERF_MEM_TLB_MISS 0x04 /* miss level */ 1046 #define PERF_MEM_TLB_L1 0x08 /* L1 */ 1047 #define PERF_MEM_TLB_L2 0x10 /* L2 */ 1048 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ 1049 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ 1050 #define PERF_MEM_TLB_SHIFT 26 1051 1052 #define PERF_MEM_S(a, s) \ 1053 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 1054 1055 /* 1056 * single taken branch record layout: 1057 * 1058 * from: source instruction (may not always be a branch insn) 1059 * to: branch target 1060 * mispred: branch target was mispredicted 1061 * predicted: branch target was predicted 1062 * 1063 * support for mispred, predicted is optional. In case it 1064 * is not supported mispred = predicted = 0. 1065 * 1066 * in_tx: running in a hardware transaction 1067 * abort: aborting a hardware transaction 1068 * cycles: cycles from last branch (or 0 if not supported) 1069 * type: branch type 1070 */ 1071 struct perf_branch_entry { 1072 __u64 from; 1073 __u64 to; 1074 __u64 mispred:1, /* target mispredicted */ 1075 predicted:1,/* target predicted */ 1076 in_tx:1, /* in transaction */ 1077 abort:1, /* transaction abort */ 1078 cycles:16, /* cycle count to last branch */ 1079 type:4, /* branch type */ 1080 reserved:40; 1081 }; 1082 1083 #endif /* _UAPI_LINUX_PERF_EVENT_H */ 1084