1 /* 2 * Performance events: 3 * 4 * Copyright (C) 2008-2009, Thomas Gleixner <[email protected]> 5 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 6 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 7 * 8 * Data type definitions, declarations, prototypes. 9 * 10 * Started by: Thomas Gleixner and Ingo Molnar 11 * 12 * For licencing details see kernel-base/COPYING 13 */ 14 #ifndef _UAPI_LINUX_PERF_EVENT_H 15 #define _UAPI_LINUX_PERF_EVENT_H 16 17 #include <linux/types.h> 18 #include <linux/ioctl.h> 19 #include <asm/byteorder.h> 20 21 /* 22 * User-space ABI bits: 23 */ 24 25 /* 26 * attr.type 27 */ 28 enum perf_type_id { 29 PERF_TYPE_HARDWARE = 0, 30 PERF_TYPE_SOFTWARE = 1, 31 PERF_TYPE_TRACEPOINT = 2, 32 PERF_TYPE_HW_CACHE = 3, 33 PERF_TYPE_RAW = 4, 34 PERF_TYPE_BREAKPOINT = 5, 35 36 PERF_TYPE_MAX, /* non-ABI */ 37 }; 38 39 /* 40 * Generalized performance event event_id types, used by the 41 * attr.event_id parameter of the sys_perf_event_open() 42 * syscall: 43 */ 44 enum perf_hw_id { 45 /* 46 * Common hardware events, generalized by the kernel: 47 */ 48 PERF_COUNT_HW_CPU_CYCLES = 0, 49 PERF_COUNT_HW_INSTRUCTIONS = 1, 50 PERF_COUNT_HW_CACHE_REFERENCES = 2, 51 PERF_COUNT_HW_CACHE_MISSES = 3, 52 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 53 PERF_COUNT_HW_BRANCH_MISSES = 5, 54 PERF_COUNT_HW_BUS_CYCLES = 6, 55 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 56 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 57 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 58 59 PERF_COUNT_HW_MAX, /* non-ABI */ 60 }; 61 62 /* 63 * Generalized hardware cache events: 64 * 65 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 66 * { read, write, prefetch } x 67 * { accesses, misses } 68 */ 69 enum perf_hw_cache_id { 70 PERF_COUNT_HW_CACHE_L1D = 0, 71 PERF_COUNT_HW_CACHE_L1I = 1, 72 PERF_COUNT_HW_CACHE_LL = 2, 73 PERF_COUNT_HW_CACHE_DTLB = 3, 74 PERF_COUNT_HW_CACHE_ITLB = 4, 75 PERF_COUNT_HW_CACHE_BPU = 5, 76 PERF_COUNT_HW_CACHE_NODE = 6, 77 78 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 79 }; 80 81 enum perf_hw_cache_op_id { 82 PERF_COUNT_HW_CACHE_OP_READ = 0, 83 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 84 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 85 86 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 87 }; 88 89 enum perf_hw_cache_op_result_id { 90 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 91 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 92 93 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 94 }; 95 96 /* 97 * Special "software" events provided by the kernel, even if the hardware 98 * does not support performance events. These events measure various 99 * physical and sw events of the kernel (and allow the profiling of them as 100 * well): 101 */ 102 enum perf_sw_ids { 103 PERF_COUNT_SW_CPU_CLOCK = 0, 104 PERF_COUNT_SW_TASK_CLOCK = 1, 105 PERF_COUNT_SW_PAGE_FAULTS = 2, 106 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 107 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 108 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 109 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 110 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 111 PERF_COUNT_SW_EMULATION_FAULTS = 8, 112 PERF_COUNT_SW_DUMMY = 9, 113 114 PERF_COUNT_SW_MAX, /* non-ABI */ 115 }; 116 117 /* 118 * Bits that can be set in attr.sample_type to request information 119 * in the overflow packets. 120 */ 121 enum perf_event_sample_format { 122 PERF_SAMPLE_IP = 1U << 0, 123 PERF_SAMPLE_TID = 1U << 1, 124 PERF_SAMPLE_TIME = 1U << 2, 125 PERF_SAMPLE_ADDR = 1U << 3, 126 PERF_SAMPLE_READ = 1U << 4, 127 PERF_SAMPLE_CALLCHAIN = 1U << 5, 128 PERF_SAMPLE_ID = 1U << 6, 129 PERF_SAMPLE_CPU = 1U << 7, 130 PERF_SAMPLE_PERIOD = 1U << 8, 131 PERF_SAMPLE_STREAM_ID = 1U << 9, 132 PERF_SAMPLE_RAW = 1U << 10, 133 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 134 PERF_SAMPLE_REGS_USER = 1U << 12, 135 PERF_SAMPLE_STACK_USER = 1U << 13, 136 PERF_SAMPLE_WEIGHT = 1U << 14, 137 PERF_SAMPLE_DATA_SRC = 1U << 15, 138 PERF_SAMPLE_IDENTIFIER = 1U << 16, 139 PERF_SAMPLE_TRANSACTION = 1U << 17, 140 PERF_SAMPLE_REGS_INTR = 1U << 18, 141 142 PERF_SAMPLE_MAX = 1U << 19, /* non-ABI */ 143 }; 144 145 /* 146 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set 147 * 148 * If the user does not pass priv level information via branch_sample_type, 149 * the kernel uses the event's priv level. Branch and event priv levels do 150 * not have to match. Branch priv level is checked for permissions. 151 * 152 * The branch types can be combined, however BRANCH_ANY covers all types 153 * of branches and therefore it supersedes all the other types. 154 */ 155 enum perf_branch_sample_type { 156 PERF_SAMPLE_BRANCH_USER = 1U << 0, /* user branches */ 157 PERF_SAMPLE_BRANCH_KERNEL = 1U << 1, /* kernel branches */ 158 PERF_SAMPLE_BRANCH_HV = 1U << 2, /* hypervisor branches */ 159 160 PERF_SAMPLE_BRANCH_ANY = 1U << 3, /* any branch types */ 161 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << 4, /* any call branch */ 162 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << 5, /* any return branch */ 163 PERF_SAMPLE_BRANCH_IND_CALL = 1U << 6, /* indirect calls */ 164 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << 7, /* transaction aborts */ 165 PERF_SAMPLE_BRANCH_IN_TX = 1U << 8, /* in transaction */ 166 PERF_SAMPLE_BRANCH_NO_TX = 1U << 9, /* not in transaction */ 167 PERF_SAMPLE_BRANCH_COND = 1U << 10, /* conditional branches */ 168 169 PERF_SAMPLE_BRANCH_MAX = 1U << 11, /* non-ABI */ 170 }; 171 172 #define PERF_SAMPLE_BRANCH_PLM_ALL \ 173 (PERF_SAMPLE_BRANCH_USER|\ 174 PERF_SAMPLE_BRANCH_KERNEL|\ 175 PERF_SAMPLE_BRANCH_HV) 176 177 /* 178 * Values to determine ABI of the registers dump. 179 */ 180 enum perf_sample_regs_abi { 181 PERF_SAMPLE_REGS_ABI_NONE = 0, 182 PERF_SAMPLE_REGS_ABI_32 = 1, 183 PERF_SAMPLE_REGS_ABI_64 = 2, 184 }; 185 186 /* 187 * Values for the memory transaction event qualifier, mostly for 188 * abort events. Multiple bits can be set. 189 */ 190 enum { 191 PERF_TXN_ELISION = (1 << 0), /* From elision */ 192 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ 193 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ 194 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ 195 PERF_TXN_RETRY = (1 << 4), /* Retry possible */ 196 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ 197 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ 198 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ 199 200 PERF_TXN_MAX = (1 << 8), /* non-ABI */ 201 202 /* bits 32..63 are reserved for the abort code */ 203 204 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 205 PERF_TXN_ABORT_SHIFT = 32, 206 }; 207 208 /* 209 * The format of the data returned by read() on a perf event fd, 210 * as specified by attr.read_format: 211 * 212 * struct read_format { 213 * { u64 value; 214 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 215 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 216 * { u64 id; } && PERF_FORMAT_ID 217 * } && !PERF_FORMAT_GROUP 218 * 219 * { u64 nr; 220 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 221 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 222 * { u64 value; 223 * { u64 id; } && PERF_FORMAT_ID 224 * } cntr[nr]; 225 * } && PERF_FORMAT_GROUP 226 * }; 227 */ 228 enum perf_event_read_format { 229 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 230 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 231 PERF_FORMAT_ID = 1U << 2, 232 PERF_FORMAT_GROUP = 1U << 3, 233 234 PERF_FORMAT_MAX = 1U << 4, /* non-ABI */ 235 }; 236 237 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ 238 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ 239 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ 240 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ 241 /* add: sample_stack_user */ 242 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ 243 244 /* 245 * Hardware event_id to monitor via a performance monitoring event: 246 */ 247 struct perf_event_attr { 248 249 /* 250 * Major type: hardware/software/tracepoint/etc. 251 */ 252 __u32 type; 253 254 /* 255 * Size of the attr structure, for fwd/bwd compat. 256 */ 257 __u32 size; 258 259 /* 260 * Type specific configuration information. 261 */ 262 __u64 config; 263 264 union { 265 __u64 sample_period; 266 __u64 sample_freq; 267 }; 268 269 __u64 sample_type; 270 __u64 read_format; 271 272 __u64 disabled : 1, /* off by default */ 273 inherit : 1, /* children inherit it */ 274 pinned : 1, /* must always be on PMU */ 275 exclusive : 1, /* only group on PMU */ 276 exclude_user : 1, /* don't count user */ 277 exclude_kernel : 1, /* ditto kernel */ 278 exclude_hv : 1, /* ditto hypervisor */ 279 exclude_idle : 1, /* don't count when idle */ 280 mmap : 1, /* include mmap data */ 281 comm : 1, /* include comm data */ 282 freq : 1, /* use freq, not period */ 283 inherit_stat : 1, /* per task counts */ 284 enable_on_exec : 1, /* next exec enables */ 285 task : 1, /* trace fork/exit */ 286 watermark : 1, /* wakeup_watermark */ 287 /* 288 * precise_ip: 289 * 290 * 0 - SAMPLE_IP can have arbitrary skid 291 * 1 - SAMPLE_IP must have constant skid 292 * 2 - SAMPLE_IP requested to have 0 skid 293 * 3 - SAMPLE_IP must have 0 skid 294 * 295 * See also PERF_RECORD_MISC_EXACT_IP 296 */ 297 precise_ip : 2, /* skid constraint */ 298 mmap_data : 1, /* non-exec mmap data */ 299 sample_id_all : 1, /* sample_type all events */ 300 301 exclude_host : 1, /* don't count in host */ 302 exclude_guest : 1, /* don't count in guest */ 303 304 exclude_callchain_kernel : 1, /* exclude kernel callchains */ 305 exclude_callchain_user : 1, /* exclude user callchains */ 306 mmap2 : 1, /* include mmap with inode data */ 307 comm_exec : 1, /* flag comm events that are due to an exec */ 308 __reserved_1 : 39; 309 310 union { 311 __u32 wakeup_events; /* wakeup every n events */ 312 __u32 wakeup_watermark; /* bytes before wakeup */ 313 }; 314 315 __u32 bp_type; 316 union { 317 __u64 bp_addr; 318 __u64 config1; /* extension of config */ 319 }; 320 union { 321 __u64 bp_len; 322 __u64 config2; /* extension of config1 */ 323 }; 324 __u64 branch_sample_type; /* enum perf_branch_sample_type */ 325 326 /* 327 * Defines set of user regs to dump on samples. 328 * See asm/perf_regs.h for details. 329 */ 330 __u64 sample_regs_user; 331 332 /* 333 * Defines size of the user stack to dump on samples. 334 */ 335 __u32 sample_stack_user; 336 337 /* Align to u64. */ 338 __u32 __reserved_2; 339 /* 340 * Defines set of regs to dump for each sample 341 * state captured on: 342 * - precise = 0: PMU interrupt 343 * - precise > 0: sampled instruction 344 * 345 * See asm/perf_regs.h for details. 346 */ 347 __u64 sample_regs_intr; 348 }; 349 350 #define perf_flags(attr) (*(&(attr)->read_format + 1)) 351 352 /* 353 * Ioctls that can be done on a perf event fd: 354 */ 355 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 356 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 357 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 358 #define PERF_EVENT_IOC_RESET _IO ('$', 3) 359 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 360 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 361 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 362 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 363 364 enum perf_event_ioc_flags { 365 PERF_IOC_FLAG_GROUP = 1U << 0, 366 }; 367 368 /* 369 * Structure of the page that can be mapped via mmap 370 */ 371 struct perf_event_mmap_page { 372 __u32 version; /* version number of this structure */ 373 __u32 compat_version; /* lowest version this is compat with */ 374 375 /* 376 * Bits needed to read the hw events in user-space. 377 * 378 * u32 seq, time_mult, time_shift, index, width; 379 * u64 count, enabled, running; 380 * u64 cyc, time_offset; 381 * s64 pmc = 0; 382 * 383 * do { 384 * seq = pc->lock; 385 * barrier() 386 * 387 * enabled = pc->time_enabled; 388 * running = pc->time_running; 389 * 390 * if (pc->cap_usr_time && enabled != running) { 391 * cyc = rdtsc(); 392 * time_offset = pc->time_offset; 393 * time_mult = pc->time_mult; 394 * time_shift = pc->time_shift; 395 * } 396 * 397 * index = pc->index; 398 * count = pc->offset; 399 * if (pc->cap_user_rdpmc && index) { 400 * width = pc->pmc_width; 401 * pmc = rdpmc(index - 1); 402 * } 403 * 404 * barrier(); 405 * } while (pc->lock != seq); 406 * 407 * NOTE: for obvious reason this only works on self-monitoring 408 * processes. 409 */ 410 __u32 lock; /* seqlock for synchronization */ 411 __u32 index; /* hardware event identifier */ 412 __s64 offset; /* add to hardware event value */ 413 __u64 time_enabled; /* time event active */ 414 __u64 time_running; /* time event on cpu */ 415 union { 416 __u64 capabilities; 417 struct { 418 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ 419 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ 420 421 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ 422 cap_user_time : 1, /* The time_* fields are used */ 423 cap_user_time_zero : 1, /* The time_zero field is used */ 424 cap_____res : 59; 425 }; 426 }; 427 428 /* 429 * If cap_user_rdpmc this field provides the bit-width of the value 430 * read using the rdpmc() or equivalent instruction. This can be used 431 * to sign extend the result like: 432 * 433 * pmc <<= 64 - width; 434 * pmc >>= 64 - width; // signed shift right 435 * count += pmc; 436 */ 437 __u16 pmc_width; 438 439 /* 440 * If cap_usr_time the below fields can be used to compute the time 441 * delta since time_enabled (in ns) using rdtsc or similar. 442 * 443 * u64 quot, rem; 444 * u64 delta; 445 * 446 * quot = (cyc >> time_shift); 447 * rem = cyc & ((1 << time_shift) - 1); 448 * delta = time_offset + quot * time_mult + 449 * ((rem * time_mult) >> time_shift); 450 * 451 * Where time_offset,time_mult,time_shift and cyc are read in the 452 * seqcount loop described above. This delta can then be added to 453 * enabled and possible running (if index), improving the scaling: 454 * 455 * enabled += delta; 456 * if (index) 457 * running += delta; 458 * 459 * quot = count / running; 460 * rem = count % running; 461 * count = quot * enabled + (rem * enabled) / running; 462 */ 463 __u16 time_shift; 464 __u32 time_mult; 465 __u64 time_offset; 466 /* 467 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated 468 * from sample timestamps. 469 * 470 * time = timestamp - time_zero; 471 * quot = time / time_mult; 472 * rem = time % time_mult; 473 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; 474 * 475 * And vice versa: 476 * 477 * quot = cyc >> time_shift; 478 * rem = cyc & ((1 << time_shift) - 1); 479 * timestamp = time_zero + quot * time_mult + 480 * ((rem * time_mult) >> time_shift); 481 */ 482 __u64 time_zero; 483 __u32 size; /* Header size up to __reserved[] fields. */ 484 485 /* 486 * Hole for extension of the self monitor capabilities 487 */ 488 489 __u8 __reserved[118*8+4]; /* align to 1k. */ 490 491 /* 492 * Control data for the mmap() data buffer. 493 * 494 * User-space reading the @data_head value should issue an smp_rmb(), 495 * after reading this value. 496 * 497 * When the mapping is PROT_WRITE the @data_tail value should be 498 * written by userspace to reflect the last read data, after issueing 499 * an smp_mb() to separate the data read from the ->data_tail store. 500 * In this case the kernel will not over-write unread data. 501 * 502 * See perf_output_put_handle() for the data ordering. 503 */ 504 __u64 data_head; /* head in the data section */ 505 __u64 data_tail; /* user-space written tail */ 506 }; 507 508 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 509 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 510 #define PERF_RECORD_MISC_KERNEL (1 << 0) 511 #define PERF_RECORD_MISC_USER (2 << 0) 512 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 513 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 514 #define PERF_RECORD_MISC_GUEST_USER (5 << 0) 515 516 /* 517 * PERF_RECORD_MISC_MMAP_DATA and PERF_RECORD_MISC_COMM_EXEC are used on 518 * different events so can reuse the same bit position. 519 */ 520 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 521 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 522 /* 523 * Indicates that the content of PERF_SAMPLE_IP points to 524 * the actual instruction that triggered the event. See also 525 * perf_event_attr::precise_ip. 526 */ 527 #define PERF_RECORD_MISC_EXACT_IP (1 << 14) 528 /* 529 * Reserve the last bit to indicate some extended misc field 530 */ 531 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 532 533 struct perf_event_header { 534 __u32 type; 535 __u16 misc; 536 __u16 size; 537 }; 538 539 enum perf_event_type { 540 541 /* 542 * If perf_event_attr.sample_id_all is set then all event types will 543 * have the sample_type selected fields related to where/when 544 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, 545 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed 546 * just after the perf_event_header and the fields already present for 547 * the existing fields, i.e. at the end of the payload. That way a newer 548 * perf.data file will be supported by older perf tools, with these new 549 * optional fields being ignored. 550 * 551 * struct sample_id { 552 * { u32 pid, tid; } && PERF_SAMPLE_TID 553 * { u64 time; } && PERF_SAMPLE_TIME 554 * { u64 id; } && PERF_SAMPLE_ID 555 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 556 * { u32 cpu, res; } && PERF_SAMPLE_CPU 557 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 558 * } && perf_event_attr::sample_id_all 559 * 560 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The 561 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed 562 * relative to header.size. 563 */ 564 565 /* 566 * The MMAP events record the PROT_EXEC mappings so that we can 567 * correlate userspace IPs to code. They have the following structure: 568 * 569 * struct { 570 * struct perf_event_header header; 571 * 572 * u32 pid, tid; 573 * u64 addr; 574 * u64 len; 575 * u64 pgoff; 576 * char filename[]; 577 * struct sample_id sample_id; 578 * }; 579 */ 580 PERF_RECORD_MMAP = 1, 581 582 /* 583 * struct { 584 * struct perf_event_header header; 585 * u64 id; 586 * u64 lost; 587 * struct sample_id sample_id; 588 * }; 589 */ 590 PERF_RECORD_LOST = 2, 591 592 /* 593 * struct { 594 * struct perf_event_header header; 595 * 596 * u32 pid, tid; 597 * char comm[]; 598 * struct sample_id sample_id; 599 * }; 600 */ 601 PERF_RECORD_COMM = 3, 602 603 /* 604 * struct { 605 * struct perf_event_header header; 606 * u32 pid, ppid; 607 * u32 tid, ptid; 608 * u64 time; 609 * struct sample_id sample_id; 610 * }; 611 */ 612 PERF_RECORD_EXIT = 4, 613 614 /* 615 * struct { 616 * struct perf_event_header header; 617 * u64 time; 618 * u64 id; 619 * u64 stream_id; 620 * struct sample_id sample_id; 621 * }; 622 */ 623 PERF_RECORD_THROTTLE = 5, 624 PERF_RECORD_UNTHROTTLE = 6, 625 626 /* 627 * struct { 628 * struct perf_event_header header; 629 * u32 pid, ppid; 630 * u32 tid, ptid; 631 * u64 time; 632 * struct sample_id sample_id; 633 * }; 634 */ 635 PERF_RECORD_FORK = 7, 636 637 /* 638 * struct { 639 * struct perf_event_header header; 640 * u32 pid, tid; 641 * 642 * struct read_format values; 643 * struct sample_id sample_id; 644 * }; 645 */ 646 PERF_RECORD_READ = 8, 647 648 /* 649 * struct { 650 * struct perf_event_header header; 651 * 652 * # 653 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. 654 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position 655 * # is fixed relative to header. 656 * # 657 * 658 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 659 * { u64 ip; } && PERF_SAMPLE_IP 660 * { u32 pid, tid; } && PERF_SAMPLE_TID 661 * { u64 time; } && PERF_SAMPLE_TIME 662 * { u64 addr; } && PERF_SAMPLE_ADDR 663 * { u64 id; } && PERF_SAMPLE_ID 664 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 665 * { u32 cpu, res; } && PERF_SAMPLE_CPU 666 * { u64 period; } && PERF_SAMPLE_PERIOD 667 * 668 * { struct read_format values; } && PERF_SAMPLE_READ 669 * 670 * { u64 nr, 671 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 672 * 673 * # 674 * # The RAW record below is opaque data wrt the ABI 675 * # 676 * # That is, the ABI doesn't make any promises wrt to 677 * # the stability of its content, it may vary depending 678 * # on event, hardware, kernel version and phase of 679 * # the moon. 680 * # 681 * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 682 * # 683 * 684 * { u32 size; 685 * char data[size];}&& PERF_SAMPLE_RAW 686 * 687 * { u64 nr; 688 * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK 689 * 690 * { u64 abi; # enum perf_sample_regs_abi 691 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER 692 * 693 * { u64 size; 694 * char data[size]; 695 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 696 * 697 * { u64 weight; } && PERF_SAMPLE_WEIGHT 698 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 699 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION 700 * { u64 abi; # enum perf_sample_regs_abi 701 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR 702 * }; 703 */ 704 PERF_RECORD_SAMPLE = 9, 705 706 /* 707 * The MMAP2 records are an augmented version of MMAP, they add 708 * maj, min, ino numbers to be used to uniquely identify each mapping 709 * 710 * struct { 711 * struct perf_event_header header; 712 * 713 * u32 pid, tid; 714 * u64 addr; 715 * u64 len; 716 * u64 pgoff; 717 * u32 maj; 718 * u32 min; 719 * u64 ino; 720 * u64 ino_generation; 721 * u32 prot, flags; 722 * char filename[]; 723 * struct sample_id sample_id; 724 * }; 725 */ 726 PERF_RECORD_MMAP2 = 10, 727 728 PERF_RECORD_MAX, /* non-ABI */ 729 }; 730 731 #define PERF_MAX_STACK_DEPTH 127 732 733 enum perf_callchain_context { 734 PERF_CONTEXT_HV = (__u64)-32, 735 PERF_CONTEXT_KERNEL = (__u64)-128, 736 PERF_CONTEXT_USER = (__u64)-512, 737 738 PERF_CONTEXT_GUEST = (__u64)-2048, 739 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 740 PERF_CONTEXT_GUEST_USER = (__u64)-2560, 741 742 PERF_CONTEXT_MAX = (__u64)-4095, 743 }; 744 745 #define PERF_FLAG_FD_NO_GROUP (1UL << 0) 746 #define PERF_FLAG_FD_OUTPUT (1UL << 1) 747 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ 748 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ 749 750 union perf_mem_data_src { 751 __u64 val; 752 struct { 753 __u64 mem_op:5, /* type of opcode */ 754 mem_lvl:14, /* memory hierarchy level */ 755 mem_snoop:5, /* snoop mode */ 756 mem_lock:2, /* lock instr */ 757 mem_dtlb:7, /* tlb access */ 758 mem_rsvd:31; 759 }; 760 }; 761 762 /* type of opcode (load/store/prefetch,code) */ 763 #define PERF_MEM_OP_NA 0x01 /* not available */ 764 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */ 765 #define PERF_MEM_OP_STORE 0x04 /* store instruction */ 766 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ 767 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ 768 #define PERF_MEM_OP_SHIFT 0 769 770 /* memory hierarchy (memory level, hit or miss) */ 771 #define PERF_MEM_LVL_NA 0x01 /* not available */ 772 #define PERF_MEM_LVL_HIT 0x02 /* hit level */ 773 #define PERF_MEM_LVL_MISS 0x04 /* miss level */ 774 #define PERF_MEM_LVL_L1 0x08 /* L1 */ 775 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ 776 #define PERF_MEM_LVL_L2 0x20 /* L2 */ 777 #define PERF_MEM_LVL_L3 0x40 /* L3 */ 778 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ 779 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ 780 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ 781 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ 782 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ 783 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 784 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 785 #define PERF_MEM_LVL_SHIFT 5 786 787 /* snoop mode */ 788 #define PERF_MEM_SNOOP_NA 0x01 /* not available */ 789 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ 790 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ 791 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ 792 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ 793 #define PERF_MEM_SNOOP_SHIFT 19 794 795 /* locked instruction */ 796 #define PERF_MEM_LOCK_NA 0x01 /* not available */ 797 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ 798 #define PERF_MEM_LOCK_SHIFT 24 799 800 /* TLB access */ 801 #define PERF_MEM_TLB_NA 0x01 /* not available */ 802 #define PERF_MEM_TLB_HIT 0x02 /* hit level */ 803 #define PERF_MEM_TLB_MISS 0x04 /* miss level */ 804 #define PERF_MEM_TLB_L1 0x08 /* L1 */ 805 #define PERF_MEM_TLB_L2 0x10 /* L2 */ 806 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ 807 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ 808 #define PERF_MEM_TLB_SHIFT 26 809 810 #define PERF_MEM_S(a, s) \ 811 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 812 813 /* 814 * single taken branch record layout: 815 * 816 * from: source instruction (may not always be a branch insn) 817 * to: branch target 818 * mispred: branch target was mispredicted 819 * predicted: branch target was predicted 820 * 821 * support for mispred, predicted is optional. In case it 822 * is not supported mispred = predicted = 0. 823 * 824 * in_tx: running in a hardware transaction 825 * abort: aborting a hardware transaction 826 */ 827 struct perf_branch_entry { 828 __u64 from; 829 __u64 to; 830 __u64 mispred:1, /* target mispredicted */ 831 predicted:1,/* target predicted */ 832 in_tx:1, /* in transaction */ 833 abort:1, /* transaction abort */ 834 reserved:60; 835 }; 836 837 #endif /* _UAPI_LINUX_PERF_EVENT_H */ 838