1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Performance events: 4 * 5 * Copyright (C) 2008-2009, Thomas Gleixner <[email protected]> 6 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 7 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 8 * 9 * Data type definitions, declarations, prototypes. 10 * 11 * Started by: Thomas Gleixner and Ingo Molnar 12 * 13 * For licencing details see kernel-base/COPYING 14 */ 15 #ifndef _UAPI_LINUX_PERF_EVENT_H 16 #define _UAPI_LINUX_PERF_EVENT_H 17 18 #include <linux/types.h> 19 #include <linux/ioctl.h> 20 #include <asm/byteorder.h> 21 22 /* 23 * User-space ABI bits: 24 */ 25 26 /* 27 * attr.type 28 */ 29 enum perf_type_id { 30 PERF_TYPE_HARDWARE = 0, 31 PERF_TYPE_SOFTWARE = 1, 32 PERF_TYPE_TRACEPOINT = 2, 33 PERF_TYPE_HW_CACHE = 3, 34 PERF_TYPE_RAW = 4, 35 PERF_TYPE_BREAKPOINT = 5, 36 37 PERF_TYPE_MAX, /* non-ABI */ 38 }; 39 40 /* 41 * attr.config layout for type PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE 42 * PERF_TYPE_HARDWARE: 0xEEEEEEEE000000AA 43 * AA: hardware event ID 44 * EEEEEEEE: PMU type ID 45 * PERF_TYPE_HW_CACHE: 0xEEEEEEEE00DDCCBB 46 * BB: hardware cache ID 47 * CC: hardware cache op ID 48 * DD: hardware cache op result ID 49 * EEEEEEEE: PMU type ID 50 * If the PMU type ID is 0, the PERF_TYPE_RAW will be applied. 51 */ 52 #define PERF_PMU_TYPE_SHIFT 32 53 #define PERF_HW_EVENT_MASK 0xffffffff 54 55 /* 56 * Generalized performance event event_id types, used by the 57 * attr.event_id parameter of the sys_perf_event_open() 58 * syscall: 59 */ 60 enum perf_hw_id { 61 /* 62 * Common hardware events, generalized by the kernel: 63 */ 64 PERF_COUNT_HW_CPU_CYCLES = 0, 65 PERF_COUNT_HW_INSTRUCTIONS = 1, 66 PERF_COUNT_HW_CACHE_REFERENCES = 2, 67 PERF_COUNT_HW_CACHE_MISSES = 3, 68 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 69 PERF_COUNT_HW_BRANCH_MISSES = 5, 70 PERF_COUNT_HW_BUS_CYCLES = 6, 71 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 72 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 73 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 74 75 PERF_COUNT_HW_MAX, /* non-ABI */ 76 }; 77 78 /* 79 * Generalized hardware cache events: 80 * 81 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 82 * { read, write, prefetch } x 83 * { accesses, misses } 84 */ 85 enum perf_hw_cache_id { 86 PERF_COUNT_HW_CACHE_L1D = 0, 87 PERF_COUNT_HW_CACHE_L1I = 1, 88 PERF_COUNT_HW_CACHE_LL = 2, 89 PERF_COUNT_HW_CACHE_DTLB = 3, 90 PERF_COUNT_HW_CACHE_ITLB = 4, 91 PERF_COUNT_HW_CACHE_BPU = 5, 92 PERF_COUNT_HW_CACHE_NODE = 6, 93 94 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 95 }; 96 97 enum perf_hw_cache_op_id { 98 PERF_COUNT_HW_CACHE_OP_READ = 0, 99 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 100 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 101 102 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 103 }; 104 105 enum perf_hw_cache_op_result_id { 106 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 107 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 108 109 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 110 }; 111 112 /* 113 * Special "software" events provided by the kernel, even if the hardware 114 * does not support performance events. These events measure various 115 * physical and sw events of the kernel (and allow the profiling of them as 116 * well): 117 */ 118 enum perf_sw_ids { 119 PERF_COUNT_SW_CPU_CLOCK = 0, 120 PERF_COUNT_SW_TASK_CLOCK = 1, 121 PERF_COUNT_SW_PAGE_FAULTS = 2, 122 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 123 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 124 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 125 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 126 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 127 PERF_COUNT_SW_EMULATION_FAULTS = 8, 128 PERF_COUNT_SW_DUMMY = 9, 129 PERF_COUNT_SW_BPF_OUTPUT = 10, 130 PERF_COUNT_SW_CGROUP_SWITCHES = 11, 131 132 PERF_COUNT_SW_MAX, /* non-ABI */ 133 }; 134 135 /* 136 * Bits that can be set in attr.sample_type to request information 137 * in the overflow packets. 138 */ 139 enum perf_event_sample_format { 140 PERF_SAMPLE_IP = 1U << 0, 141 PERF_SAMPLE_TID = 1U << 1, 142 PERF_SAMPLE_TIME = 1U << 2, 143 PERF_SAMPLE_ADDR = 1U << 3, 144 PERF_SAMPLE_READ = 1U << 4, 145 PERF_SAMPLE_CALLCHAIN = 1U << 5, 146 PERF_SAMPLE_ID = 1U << 6, 147 PERF_SAMPLE_CPU = 1U << 7, 148 PERF_SAMPLE_PERIOD = 1U << 8, 149 PERF_SAMPLE_STREAM_ID = 1U << 9, 150 PERF_SAMPLE_RAW = 1U << 10, 151 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 152 PERF_SAMPLE_REGS_USER = 1U << 12, 153 PERF_SAMPLE_STACK_USER = 1U << 13, 154 PERF_SAMPLE_WEIGHT = 1U << 14, 155 PERF_SAMPLE_DATA_SRC = 1U << 15, 156 PERF_SAMPLE_IDENTIFIER = 1U << 16, 157 PERF_SAMPLE_TRANSACTION = 1U << 17, 158 PERF_SAMPLE_REGS_INTR = 1U << 18, 159 PERF_SAMPLE_PHYS_ADDR = 1U << 19, 160 PERF_SAMPLE_AUX = 1U << 20, 161 PERF_SAMPLE_CGROUP = 1U << 21, 162 PERF_SAMPLE_DATA_PAGE_SIZE = 1U << 22, 163 PERF_SAMPLE_CODE_PAGE_SIZE = 1U << 23, 164 PERF_SAMPLE_WEIGHT_STRUCT = 1U << 24, 165 166 PERF_SAMPLE_MAX = 1U << 25, /* non-ABI */ 167 168 __PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, /* non-ABI; internal use */ 169 }; 170 171 #define PERF_SAMPLE_WEIGHT_TYPE (PERF_SAMPLE_WEIGHT | PERF_SAMPLE_WEIGHT_STRUCT) 172 /* 173 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set 174 * 175 * If the user does not pass priv level information via branch_sample_type, 176 * the kernel uses the event's priv level. Branch and event priv levels do 177 * not have to match. Branch priv level is checked for permissions. 178 * 179 * The branch types can be combined, however BRANCH_ANY covers all types 180 * of branches and therefore it supersedes all the other types. 181 */ 182 enum perf_branch_sample_type_shift { 183 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ 184 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ 185 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ 186 187 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ 188 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ 189 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ 190 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ 191 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ 192 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ 193 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ 194 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ 195 196 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */ 197 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */ 198 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */ 199 200 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */ 201 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */ 202 203 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */ 204 205 PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17, /* save low level index of raw branch records */ 206 207 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ 208 }; 209 210 enum perf_branch_sample_type { 211 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 212 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 213 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 214 215 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 216 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 217 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 218 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 219 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 220 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 221 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 222 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 223 224 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 225 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, 226 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 227 228 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, 229 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 230 231 PERF_SAMPLE_BRANCH_TYPE_SAVE = 232 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, 233 234 PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT, 235 236 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 237 }; 238 239 /* 240 * Common flow change classification 241 */ 242 enum { 243 PERF_BR_UNKNOWN = 0, /* unknown */ 244 PERF_BR_COND = 1, /* conditional */ 245 PERF_BR_UNCOND = 2, /* unconditional */ 246 PERF_BR_IND = 3, /* indirect */ 247 PERF_BR_CALL = 4, /* function call */ 248 PERF_BR_IND_CALL = 5, /* indirect function call */ 249 PERF_BR_RET = 6, /* function return */ 250 PERF_BR_SYSCALL = 7, /* syscall */ 251 PERF_BR_SYSRET = 8, /* syscall return */ 252 PERF_BR_COND_CALL = 9, /* conditional function call */ 253 PERF_BR_COND_RET = 10, /* conditional function return */ 254 PERF_BR_ERET = 11, /* exception return */ 255 PERF_BR_IRQ = 12, /* irq */ 256 PERF_BR_SERROR = 13, /* system error */ 257 PERF_BR_NO_TX = 14, /* not in transaction */ 258 PERF_BR_EXTEND_ABI = 15, /* extend ABI */ 259 PERF_BR_MAX, 260 }; 261 262 /* 263 * Common branch speculation outcome classification 264 */ 265 enum { 266 PERF_BR_SPEC_NA = 0, /* Not available */ 267 PERF_BR_SPEC_WRONG_PATH = 1, /* Speculative but on wrong path */ 268 PERF_BR_NON_SPEC_CORRECT_PATH = 2, /* Non-speculative but on correct path */ 269 PERF_BR_SPEC_CORRECT_PATH = 3, /* Speculative and on correct path */ 270 PERF_BR_SPEC_MAX, 271 }; 272 273 enum { 274 PERF_BR_NEW_FAULT_ALGN = 0, /* Alignment fault */ 275 PERF_BR_NEW_FAULT_DATA = 1, /* Data fault */ 276 PERF_BR_NEW_FAULT_INST = 2, /* Inst fault */ 277 PERF_BR_NEW_ARCH_1 = 3, /* Architecture specific */ 278 PERF_BR_NEW_ARCH_2 = 4, /* Architecture specific */ 279 PERF_BR_NEW_ARCH_3 = 5, /* Architecture specific */ 280 PERF_BR_NEW_ARCH_4 = 6, /* Architecture specific */ 281 PERF_BR_NEW_ARCH_5 = 7, /* Architecture specific */ 282 PERF_BR_NEW_MAX, 283 }; 284 285 #define PERF_SAMPLE_BRANCH_PLM_ALL \ 286 (PERF_SAMPLE_BRANCH_USER|\ 287 PERF_SAMPLE_BRANCH_KERNEL|\ 288 PERF_SAMPLE_BRANCH_HV) 289 290 /* 291 * Values to determine ABI of the registers dump. 292 */ 293 enum perf_sample_regs_abi { 294 PERF_SAMPLE_REGS_ABI_NONE = 0, 295 PERF_SAMPLE_REGS_ABI_32 = 1, 296 PERF_SAMPLE_REGS_ABI_64 = 2, 297 }; 298 299 /* 300 * Values for the memory transaction event qualifier, mostly for 301 * abort events. Multiple bits can be set. 302 */ 303 enum { 304 PERF_TXN_ELISION = (1 << 0), /* From elision */ 305 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ 306 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ 307 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ 308 PERF_TXN_RETRY = (1 << 4), /* Retry possible */ 309 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ 310 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ 311 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ 312 313 PERF_TXN_MAX = (1 << 8), /* non-ABI */ 314 315 /* bits 32..63 are reserved for the abort code */ 316 317 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 318 PERF_TXN_ABORT_SHIFT = 32, 319 }; 320 321 /* 322 * The format of the data returned by read() on a perf event fd, 323 * as specified by attr.read_format: 324 * 325 * struct read_format { 326 * { u64 value; 327 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 328 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 329 * { u64 id; } && PERF_FORMAT_ID 330 * { u64 lost; } && PERF_FORMAT_LOST 331 * } && !PERF_FORMAT_GROUP 332 * 333 * { u64 nr; 334 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 335 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 336 * { u64 value; 337 * { u64 id; } && PERF_FORMAT_ID 338 * { u64 lost; } && PERF_FORMAT_LOST 339 * } cntr[nr]; 340 * } && PERF_FORMAT_GROUP 341 * }; 342 */ 343 enum perf_event_read_format { 344 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 345 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 346 PERF_FORMAT_ID = 1U << 2, 347 PERF_FORMAT_GROUP = 1U << 3, 348 PERF_FORMAT_LOST = 1U << 4, 349 350 PERF_FORMAT_MAX = 1U << 5, /* non-ABI */ 351 }; 352 353 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ 354 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ 355 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ 356 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ 357 /* add: sample_stack_user */ 358 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ 359 #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ 360 #define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ 361 #define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */ 362 363 /* 364 * Hardware event_id to monitor via a performance monitoring event: 365 * 366 * @sample_max_stack: Max number of frame pointers in a callchain, 367 * should be < /proc/sys/kernel/perf_event_max_stack 368 */ 369 struct perf_event_attr { 370 371 /* 372 * Major type: hardware/software/tracepoint/etc. 373 */ 374 __u32 type; 375 376 /* 377 * Size of the attr structure, for fwd/bwd compat. 378 */ 379 __u32 size; 380 381 /* 382 * Type specific configuration information. 383 */ 384 __u64 config; 385 386 union { 387 __u64 sample_period; 388 __u64 sample_freq; 389 }; 390 391 __u64 sample_type; 392 __u64 read_format; 393 394 __u64 disabled : 1, /* off by default */ 395 inherit : 1, /* children inherit it */ 396 pinned : 1, /* must always be on PMU */ 397 exclusive : 1, /* only group on PMU */ 398 exclude_user : 1, /* don't count user */ 399 exclude_kernel : 1, /* ditto kernel */ 400 exclude_hv : 1, /* ditto hypervisor */ 401 exclude_idle : 1, /* don't count when idle */ 402 mmap : 1, /* include mmap data */ 403 comm : 1, /* include comm data */ 404 freq : 1, /* use freq, not period */ 405 inherit_stat : 1, /* per task counts */ 406 enable_on_exec : 1, /* next exec enables */ 407 task : 1, /* trace fork/exit */ 408 watermark : 1, /* wakeup_watermark */ 409 /* 410 * precise_ip: 411 * 412 * 0 - SAMPLE_IP can have arbitrary skid 413 * 1 - SAMPLE_IP must have constant skid 414 * 2 - SAMPLE_IP requested to have 0 skid 415 * 3 - SAMPLE_IP must have 0 skid 416 * 417 * See also PERF_RECORD_MISC_EXACT_IP 418 */ 419 precise_ip : 2, /* skid constraint */ 420 mmap_data : 1, /* non-exec mmap data */ 421 sample_id_all : 1, /* sample_type all events */ 422 423 exclude_host : 1, /* don't count in host */ 424 exclude_guest : 1, /* don't count in guest */ 425 426 exclude_callchain_kernel : 1, /* exclude kernel callchains */ 427 exclude_callchain_user : 1, /* exclude user callchains */ 428 mmap2 : 1, /* include mmap with inode data */ 429 comm_exec : 1, /* flag comm events that are due to an exec */ 430 use_clockid : 1, /* use @clockid for time fields */ 431 context_switch : 1, /* context switch data */ 432 write_backward : 1, /* Write ring buffer from end to beginning */ 433 namespaces : 1, /* include namespaces data */ 434 ksymbol : 1, /* include ksymbol events */ 435 bpf_event : 1, /* include bpf events */ 436 aux_output : 1, /* generate AUX records instead of events */ 437 cgroup : 1, /* include cgroup events */ 438 text_poke : 1, /* include text poke events */ 439 build_id : 1, /* use build id in mmap2 events */ 440 inherit_thread : 1, /* children only inherit if cloned with CLONE_THREAD */ 441 remove_on_exec : 1, /* event is removed from task on exec */ 442 sigtrap : 1, /* send synchronous SIGTRAP on event */ 443 __reserved_1 : 26; 444 445 union { 446 __u32 wakeup_events; /* wakeup every n events */ 447 __u32 wakeup_watermark; /* bytes before wakeup */ 448 }; 449 450 __u32 bp_type; 451 union { 452 __u64 bp_addr; 453 __u64 kprobe_func; /* for perf_kprobe */ 454 __u64 uprobe_path; /* for perf_uprobe */ 455 __u64 config1; /* extension of config */ 456 }; 457 union { 458 __u64 bp_len; 459 __u64 kprobe_addr; /* when kprobe_func == NULL */ 460 __u64 probe_offset; /* for perf_[k,u]probe */ 461 __u64 config2; /* extension of config1 */ 462 }; 463 __u64 branch_sample_type; /* enum perf_branch_sample_type */ 464 465 /* 466 * Defines set of user regs to dump on samples. 467 * See asm/perf_regs.h for details. 468 */ 469 __u64 sample_regs_user; 470 471 /* 472 * Defines size of the user stack to dump on samples. 473 */ 474 __u32 sample_stack_user; 475 476 __s32 clockid; 477 /* 478 * Defines set of regs to dump for each sample 479 * state captured on: 480 * - precise = 0: PMU interrupt 481 * - precise > 0: sampled instruction 482 * 483 * See asm/perf_regs.h for details. 484 */ 485 __u64 sample_regs_intr; 486 487 /* 488 * Wakeup watermark for AUX area 489 */ 490 __u32 aux_watermark; 491 __u16 sample_max_stack; 492 __u16 __reserved_2; 493 __u32 aux_sample_size; 494 __u32 __reserved_3; 495 496 /* 497 * User provided data if sigtrap=1, passed back to user via 498 * siginfo_t::si_perf_data, e.g. to permit user to identify the event. 499 * Note, siginfo_t::si_perf_data is long-sized, and sig_data will be 500 * truncated accordingly on 32 bit architectures. 501 */ 502 __u64 sig_data; 503 }; 504 505 /* 506 * Structure used by below PERF_EVENT_IOC_QUERY_BPF command 507 * to query bpf programs attached to the same perf tracepoint 508 * as the given perf event. 509 */ 510 struct perf_event_query_bpf { 511 /* 512 * The below ids array length 513 */ 514 __u32 ids_len; 515 /* 516 * Set by the kernel to indicate the number of 517 * available programs 518 */ 519 __u32 prog_cnt; 520 /* 521 * User provided buffer to store program ids 522 */ 523 __u32 ids[]; 524 }; 525 526 /* 527 * Ioctls that can be done on a perf event fd: 528 */ 529 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 530 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 531 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 532 #define PERF_EVENT_IOC_RESET _IO ('$', 3) 533 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 534 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 535 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 536 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 537 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) 538 #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) 539 #define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) 540 #define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *) 541 542 enum perf_event_ioc_flags { 543 PERF_IOC_FLAG_GROUP = 1U << 0, 544 }; 545 546 /* 547 * Structure of the page that can be mapped via mmap 548 */ 549 struct perf_event_mmap_page { 550 __u32 version; /* version number of this structure */ 551 __u32 compat_version; /* lowest version this is compat with */ 552 553 /* 554 * Bits needed to read the hw events in user-space. 555 * 556 * u32 seq, time_mult, time_shift, index, width; 557 * u64 count, enabled, running; 558 * u64 cyc, time_offset; 559 * s64 pmc = 0; 560 * 561 * do { 562 * seq = pc->lock; 563 * barrier() 564 * 565 * enabled = pc->time_enabled; 566 * running = pc->time_running; 567 * 568 * if (pc->cap_usr_time && enabled != running) { 569 * cyc = rdtsc(); 570 * time_offset = pc->time_offset; 571 * time_mult = pc->time_mult; 572 * time_shift = pc->time_shift; 573 * } 574 * 575 * index = pc->index; 576 * count = pc->offset; 577 * if (pc->cap_user_rdpmc && index) { 578 * width = pc->pmc_width; 579 * pmc = rdpmc(index - 1); 580 * } 581 * 582 * barrier(); 583 * } while (pc->lock != seq); 584 * 585 * NOTE: for obvious reason this only works on self-monitoring 586 * processes. 587 */ 588 __u32 lock; /* seqlock for synchronization */ 589 __u32 index; /* hardware event identifier */ 590 __s64 offset; /* add to hardware event value */ 591 __u64 time_enabled; /* time event active */ 592 __u64 time_running; /* time event on cpu */ 593 union { 594 __u64 capabilities; 595 struct { 596 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ 597 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ 598 599 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ 600 cap_user_time : 1, /* The time_{shift,mult,offset} fields are used */ 601 cap_user_time_zero : 1, /* The time_zero field is used */ 602 cap_user_time_short : 1, /* the time_{cycle,mask} fields are used */ 603 cap_____res : 58; 604 }; 605 }; 606 607 /* 608 * If cap_user_rdpmc this field provides the bit-width of the value 609 * read using the rdpmc() or equivalent instruction. This can be used 610 * to sign extend the result like: 611 * 612 * pmc <<= 64 - width; 613 * pmc >>= 64 - width; // signed shift right 614 * count += pmc; 615 */ 616 __u16 pmc_width; 617 618 /* 619 * If cap_usr_time the below fields can be used to compute the time 620 * delta since time_enabled (in ns) using rdtsc or similar. 621 * 622 * u64 quot, rem; 623 * u64 delta; 624 * 625 * quot = (cyc >> time_shift); 626 * rem = cyc & (((u64)1 << time_shift) - 1); 627 * delta = time_offset + quot * time_mult + 628 * ((rem * time_mult) >> time_shift); 629 * 630 * Where time_offset,time_mult,time_shift and cyc are read in the 631 * seqcount loop described above. This delta can then be added to 632 * enabled and possible running (if index), improving the scaling: 633 * 634 * enabled += delta; 635 * if (index) 636 * running += delta; 637 * 638 * quot = count / running; 639 * rem = count % running; 640 * count = quot * enabled + (rem * enabled) / running; 641 */ 642 __u16 time_shift; 643 __u32 time_mult; 644 __u64 time_offset; 645 /* 646 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated 647 * from sample timestamps. 648 * 649 * time = timestamp - time_zero; 650 * quot = time / time_mult; 651 * rem = time % time_mult; 652 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; 653 * 654 * And vice versa: 655 * 656 * quot = cyc >> time_shift; 657 * rem = cyc & (((u64)1 << time_shift) - 1); 658 * timestamp = time_zero + quot * time_mult + 659 * ((rem * time_mult) >> time_shift); 660 */ 661 __u64 time_zero; 662 663 __u32 size; /* Header size up to __reserved[] fields. */ 664 __u32 __reserved_1; 665 666 /* 667 * If cap_usr_time_short, the hardware clock is less than 64bit wide 668 * and we must compute the 'cyc' value, as used by cap_usr_time, as: 669 * 670 * cyc = time_cycles + ((cyc - time_cycles) & time_mask) 671 * 672 * NOTE: this form is explicitly chosen such that cap_usr_time_short 673 * is a correction on top of cap_usr_time, and code that doesn't 674 * know about cap_usr_time_short still works under the assumption 675 * the counter doesn't wrap. 676 */ 677 __u64 time_cycles; 678 __u64 time_mask; 679 680 /* 681 * Hole for extension of the self monitor capabilities 682 */ 683 684 __u8 __reserved[116*8]; /* align to 1k. */ 685 686 /* 687 * Control data for the mmap() data buffer. 688 * 689 * User-space reading the @data_head value should issue an smp_rmb(), 690 * after reading this value. 691 * 692 * When the mapping is PROT_WRITE the @data_tail value should be 693 * written by userspace to reflect the last read data, after issueing 694 * an smp_mb() to separate the data read from the ->data_tail store. 695 * In this case the kernel will not over-write unread data. 696 * 697 * See perf_output_put_handle() for the data ordering. 698 * 699 * data_{offset,size} indicate the location and size of the perf record 700 * buffer within the mmapped area. 701 */ 702 __u64 data_head; /* head in the data section */ 703 __u64 data_tail; /* user-space written tail */ 704 __u64 data_offset; /* where the buffer starts */ 705 __u64 data_size; /* data buffer size */ 706 707 /* 708 * AUX area is defined by aux_{offset,size} fields that should be set 709 * by the userspace, so that 710 * 711 * aux_offset >= data_offset + data_size 712 * 713 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size. 714 * 715 * Ring buffer pointers aux_{head,tail} have the same semantics as 716 * data_{head,tail} and same ordering rules apply. 717 */ 718 __u64 aux_head; 719 __u64 aux_tail; 720 __u64 aux_offset; 721 __u64 aux_size; 722 }; 723 724 /* 725 * The current state of perf_event_header::misc bits usage: 726 * ('|' used bit, '-' unused bit) 727 * 728 * 012 CDEF 729 * |||---------|||| 730 * 731 * Where: 732 * 0-2 CPUMODE_MASK 733 * 734 * C PROC_MAP_PARSE_TIMEOUT 735 * D MMAP_DATA / COMM_EXEC / FORK_EXEC / SWITCH_OUT 736 * E MMAP_BUILD_ID / EXACT_IP / SCHED_OUT_PREEMPT 737 * F (reserved) 738 */ 739 740 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 741 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 742 #define PERF_RECORD_MISC_KERNEL (1 << 0) 743 #define PERF_RECORD_MISC_USER (2 << 0) 744 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 745 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 746 #define PERF_RECORD_MISC_GUEST_USER (5 << 0) 747 748 /* 749 * Indicates that /proc/PID/maps parsing are truncated by time out. 750 */ 751 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) 752 /* 753 * Following PERF_RECORD_MISC_* are used on different 754 * events, so can reuse the same bit position: 755 * 756 * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events 757 * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event 758 * PERF_RECORD_MISC_FORK_EXEC - PERF_RECORD_FORK event (perf internal) 759 * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events 760 */ 761 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 762 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 763 #define PERF_RECORD_MISC_FORK_EXEC (1 << 13) 764 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) 765 /* 766 * These PERF_RECORD_MISC_* flags below are safely reused 767 * for the following events: 768 * 769 * PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events 770 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events 771 * PERF_RECORD_MISC_MMAP_BUILD_ID - PERF_RECORD_MMAP2 event 772 * 773 * 774 * PERF_RECORD_MISC_EXACT_IP: 775 * Indicates that the content of PERF_SAMPLE_IP points to 776 * the actual instruction that triggered the event. See also 777 * perf_event_attr::precise_ip. 778 * 779 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT: 780 * Indicates that thread was preempted in TASK_RUNNING state. 781 * 782 * PERF_RECORD_MISC_MMAP_BUILD_ID: 783 * Indicates that mmap2 event carries build id data. 784 */ 785 #define PERF_RECORD_MISC_EXACT_IP (1 << 14) 786 #define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14) 787 #define PERF_RECORD_MISC_MMAP_BUILD_ID (1 << 14) 788 /* 789 * Reserve the last bit to indicate some extended misc field 790 */ 791 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 792 793 struct perf_event_header { 794 __u32 type; 795 __u16 misc; 796 __u16 size; 797 }; 798 799 struct perf_ns_link_info { 800 __u64 dev; 801 __u64 ino; 802 }; 803 804 enum { 805 NET_NS_INDEX = 0, 806 UTS_NS_INDEX = 1, 807 IPC_NS_INDEX = 2, 808 PID_NS_INDEX = 3, 809 USER_NS_INDEX = 4, 810 MNT_NS_INDEX = 5, 811 CGROUP_NS_INDEX = 6, 812 813 NR_NAMESPACES, /* number of available namespaces */ 814 }; 815 816 enum perf_event_type { 817 818 /* 819 * If perf_event_attr.sample_id_all is set then all event types will 820 * have the sample_type selected fields related to where/when 821 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, 822 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed 823 * just after the perf_event_header and the fields already present for 824 * the existing fields, i.e. at the end of the payload. That way a newer 825 * perf.data file will be supported by older perf tools, with these new 826 * optional fields being ignored. 827 * 828 * struct sample_id { 829 * { u32 pid, tid; } && PERF_SAMPLE_TID 830 * { u64 time; } && PERF_SAMPLE_TIME 831 * { u64 id; } && PERF_SAMPLE_ID 832 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 833 * { u32 cpu, res; } && PERF_SAMPLE_CPU 834 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 835 * } && perf_event_attr::sample_id_all 836 * 837 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The 838 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed 839 * relative to header.size. 840 */ 841 842 /* 843 * The MMAP events record the PROT_EXEC mappings so that we can 844 * correlate userspace IPs to code. They have the following structure: 845 * 846 * struct { 847 * struct perf_event_header header; 848 * 849 * u32 pid, tid; 850 * u64 addr; 851 * u64 len; 852 * u64 pgoff; 853 * char filename[]; 854 * struct sample_id sample_id; 855 * }; 856 */ 857 PERF_RECORD_MMAP = 1, 858 859 /* 860 * struct { 861 * struct perf_event_header header; 862 * u64 id; 863 * u64 lost; 864 * struct sample_id sample_id; 865 * }; 866 */ 867 PERF_RECORD_LOST = 2, 868 869 /* 870 * struct { 871 * struct perf_event_header header; 872 * 873 * u32 pid, tid; 874 * char comm[]; 875 * struct sample_id sample_id; 876 * }; 877 */ 878 PERF_RECORD_COMM = 3, 879 880 /* 881 * struct { 882 * struct perf_event_header header; 883 * u32 pid, ppid; 884 * u32 tid, ptid; 885 * u64 time; 886 * struct sample_id sample_id; 887 * }; 888 */ 889 PERF_RECORD_EXIT = 4, 890 891 /* 892 * struct { 893 * struct perf_event_header header; 894 * u64 time; 895 * u64 id; 896 * u64 stream_id; 897 * struct sample_id sample_id; 898 * }; 899 */ 900 PERF_RECORD_THROTTLE = 5, 901 PERF_RECORD_UNTHROTTLE = 6, 902 903 /* 904 * struct { 905 * struct perf_event_header header; 906 * u32 pid, ppid; 907 * u32 tid, ptid; 908 * u64 time; 909 * struct sample_id sample_id; 910 * }; 911 */ 912 PERF_RECORD_FORK = 7, 913 914 /* 915 * struct { 916 * struct perf_event_header header; 917 * u32 pid, tid; 918 * 919 * struct read_format values; 920 * struct sample_id sample_id; 921 * }; 922 */ 923 PERF_RECORD_READ = 8, 924 925 /* 926 * struct { 927 * struct perf_event_header header; 928 * 929 * # 930 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. 931 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position 932 * # is fixed relative to header. 933 * # 934 * 935 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 936 * { u64 ip; } && PERF_SAMPLE_IP 937 * { u32 pid, tid; } && PERF_SAMPLE_TID 938 * { u64 time; } && PERF_SAMPLE_TIME 939 * { u64 addr; } && PERF_SAMPLE_ADDR 940 * { u64 id; } && PERF_SAMPLE_ID 941 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 942 * { u32 cpu, res; } && PERF_SAMPLE_CPU 943 * { u64 period; } && PERF_SAMPLE_PERIOD 944 * 945 * { struct read_format values; } && PERF_SAMPLE_READ 946 * 947 * { u64 nr, 948 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 949 * 950 * # 951 * # The RAW record below is opaque data wrt the ABI 952 * # 953 * # That is, the ABI doesn't make any promises wrt to 954 * # the stability of its content, it may vary depending 955 * # on event, hardware, kernel version and phase of 956 * # the moon. 957 * # 958 * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 959 * # 960 * 961 * { u32 size; 962 * char data[size];}&& PERF_SAMPLE_RAW 963 * 964 * { u64 nr; 965 * { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX 966 * { u64 from, to, flags } lbr[nr]; 967 * } && PERF_SAMPLE_BRANCH_STACK 968 * 969 * { u64 abi; # enum perf_sample_regs_abi 970 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER 971 * 972 * { u64 size; 973 * char data[size]; 974 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 975 * 976 * { union perf_sample_weight 977 * { 978 * u64 full; && PERF_SAMPLE_WEIGHT 979 * #if defined(__LITTLE_ENDIAN_BITFIELD) 980 * struct { 981 * u32 var1_dw; 982 * u16 var2_w; 983 * u16 var3_w; 984 * } && PERF_SAMPLE_WEIGHT_STRUCT 985 * #elif defined(__BIG_ENDIAN_BITFIELD) 986 * struct { 987 * u16 var3_w; 988 * u16 var2_w; 989 * u32 var1_dw; 990 * } && PERF_SAMPLE_WEIGHT_STRUCT 991 * #endif 992 * } 993 * } 994 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 995 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION 996 * { u64 abi; # enum perf_sample_regs_abi 997 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR 998 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR 999 * { u64 size; 1000 * char data[size]; } && PERF_SAMPLE_AUX 1001 * { u64 data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE 1002 * { u64 code_page_size;} && PERF_SAMPLE_CODE_PAGE_SIZE 1003 * }; 1004 */ 1005 PERF_RECORD_SAMPLE = 9, 1006 1007 /* 1008 * The MMAP2 records are an augmented version of MMAP, they add 1009 * maj, min, ino numbers to be used to uniquely identify each mapping 1010 * 1011 * struct { 1012 * struct perf_event_header header; 1013 * 1014 * u32 pid, tid; 1015 * u64 addr; 1016 * u64 len; 1017 * u64 pgoff; 1018 * union { 1019 * struct { 1020 * u32 maj; 1021 * u32 min; 1022 * u64 ino; 1023 * u64 ino_generation; 1024 * }; 1025 * struct { 1026 * u8 build_id_size; 1027 * u8 __reserved_1; 1028 * u16 __reserved_2; 1029 * u8 build_id[20]; 1030 * }; 1031 * }; 1032 * u32 prot, flags; 1033 * char filename[]; 1034 * struct sample_id sample_id; 1035 * }; 1036 */ 1037 PERF_RECORD_MMAP2 = 10, 1038 1039 /* 1040 * Records that new data landed in the AUX buffer part. 1041 * 1042 * struct { 1043 * struct perf_event_header header; 1044 * 1045 * u64 aux_offset; 1046 * u64 aux_size; 1047 * u64 flags; 1048 * struct sample_id sample_id; 1049 * }; 1050 */ 1051 PERF_RECORD_AUX = 11, 1052 1053 /* 1054 * Indicates that instruction trace has started 1055 * 1056 * struct { 1057 * struct perf_event_header header; 1058 * u32 pid; 1059 * u32 tid; 1060 * struct sample_id sample_id; 1061 * }; 1062 */ 1063 PERF_RECORD_ITRACE_START = 12, 1064 1065 /* 1066 * Records the dropped/lost sample number. 1067 * 1068 * struct { 1069 * struct perf_event_header header; 1070 * 1071 * u64 lost; 1072 * struct sample_id sample_id; 1073 * }; 1074 */ 1075 PERF_RECORD_LOST_SAMPLES = 13, 1076 1077 /* 1078 * Records a context switch in or out (flagged by 1079 * PERF_RECORD_MISC_SWITCH_OUT). See also 1080 * PERF_RECORD_SWITCH_CPU_WIDE. 1081 * 1082 * struct { 1083 * struct perf_event_header header; 1084 * struct sample_id sample_id; 1085 * }; 1086 */ 1087 PERF_RECORD_SWITCH = 14, 1088 1089 /* 1090 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and 1091 * next_prev_tid that are the next (switching out) or previous 1092 * (switching in) pid/tid. 1093 * 1094 * struct { 1095 * struct perf_event_header header; 1096 * u32 next_prev_pid; 1097 * u32 next_prev_tid; 1098 * struct sample_id sample_id; 1099 * }; 1100 */ 1101 PERF_RECORD_SWITCH_CPU_WIDE = 15, 1102 1103 /* 1104 * struct { 1105 * struct perf_event_header header; 1106 * u32 pid; 1107 * u32 tid; 1108 * u64 nr_namespaces; 1109 * { u64 dev, inode; } [nr_namespaces]; 1110 * struct sample_id sample_id; 1111 * }; 1112 */ 1113 PERF_RECORD_NAMESPACES = 16, 1114 1115 /* 1116 * Record ksymbol register/unregister events: 1117 * 1118 * struct { 1119 * struct perf_event_header header; 1120 * u64 addr; 1121 * u32 len; 1122 * u16 ksym_type; 1123 * u16 flags; 1124 * char name[]; 1125 * struct sample_id sample_id; 1126 * }; 1127 */ 1128 PERF_RECORD_KSYMBOL = 17, 1129 1130 /* 1131 * Record bpf events: 1132 * enum perf_bpf_event_type { 1133 * PERF_BPF_EVENT_UNKNOWN = 0, 1134 * PERF_BPF_EVENT_PROG_LOAD = 1, 1135 * PERF_BPF_EVENT_PROG_UNLOAD = 2, 1136 * }; 1137 * 1138 * struct { 1139 * struct perf_event_header header; 1140 * u16 type; 1141 * u16 flags; 1142 * u32 id; 1143 * u8 tag[BPF_TAG_SIZE]; 1144 * struct sample_id sample_id; 1145 * }; 1146 */ 1147 PERF_RECORD_BPF_EVENT = 18, 1148 1149 /* 1150 * struct { 1151 * struct perf_event_header header; 1152 * u64 id; 1153 * char path[]; 1154 * struct sample_id sample_id; 1155 * }; 1156 */ 1157 PERF_RECORD_CGROUP = 19, 1158 1159 /* 1160 * Records changes to kernel text i.e. self-modified code. 'old_len' is 1161 * the number of old bytes, 'new_len' is the number of new bytes. Either 1162 * 'old_len' or 'new_len' may be zero to indicate, for example, the 1163 * addition or removal of a trampoline. 'bytes' contains the old bytes 1164 * followed immediately by the new bytes. 1165 * 1166 * struct { 1167 * struct perf_event_header header; 1168 * u64 addr; 1169 * u16 old_len; 1170 * u16 new_len; 1171 * u8 bytes[]; 1172 * struct sample_id sample_id; 1173 * }; 1174 */ 1175 PERF_RECORD_TEXT_POKE = 20, 1176 1177 /* 1178 * Data written to the AUX area by hardware due to aux_output, may need 1179 * to be matched to the event by an architecture-specific hardware ID. 1180 * This records the hardware ID, but requires sample_id to provide the 1181 * event ID. e.g. Intel PT uses this record to disambiguate PEBS-via-PT 1182 * records from multiple events. 1183 * 1184 * struct { 1185 * struct perf_event_header header; 1186 * u64 hw_id; 1187 * struct sample_id sample_id; 1188 * }; 1189 */ 1190 PERF_RECORD_AUX_OUTPUT_HW_ID = 21, 1191 1192 PERF_RECORD_MAX, /* non-ABI */ 1193 }; 1194 1195 enum perf_record_ksymbol_type { 1196 PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0, 1197 PERF_RECORD_KSYMBOL_TYPE_BPF = 1, 1198 /* 1199 * Out of line code such as kprobe-replaced instructions or optimized 1200 * kprobes or ftrace trampolines. 1201 */ 1202 PERF_RECORD_KSYMBOL_TYPE_OOL = 2, 1203 PERF_RECORD_KSYMBOL_TYPE_MAX /* non-ABI */ 1204 }; 1205 1206 #define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0) 1207 1208 enum perf_bpf_event_type { 1209 PERF_BPF_EVENT_UNKNOWN = 0, 1210 PERF_BPF_EVENT_PROG_LOAD = 1, 1211 PERF_BPF_EVENT_PROG_UNLOAD = 2, 1212 PERF_BPF_EVENT_MAX, /* non-ABI */ 1213 }; 1214 1215 #define PERF_MAX_STACK_DEPTH 127 1216 #define PERF_MAX_CONTEXTS_PER_STACK 8 1217 1218 enum perf_callchain_context { 1219 PERF_CONTEXT_HV = (__u64)-32, 1220 PERF_CONTEXT_KERNEL = (__u64)-128, 1221 PERF_CONTEXT_USER = (__u64)-512, 1222 1223 PERF_CONTEXT_GUEST = (__u64)-2048, 1224 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 1225 PERF_CONTEXT_GUEST_USER = (__u64)-2560, 1226 1227 PERF_CONTEXT_MAX = (__u64)-4095, 1228 }; 1229 1230 /** 1231 * PERF_RECORD_AUX::flags bits 1232 */ 1233 #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ 1234 #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ 1235 #define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ 1236 #define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ 1237 #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */ 1238 1239 /* CoreSight PMU AUX buffer formats */ 1240 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */ 1241 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format of the source */ 1242 1243 #define PERF_FLAG_FD_NO_GROUP (1UL << 0) 1244 #define PERF_FLAG_FD_OUTPUT (1UL << 1) 1245 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ 1246 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ 1247 1248 #if defined(__LITTLE_ENDIAN_BITFIELD) 1249 union perf_mem_data_src { 1250 __u64 val; 1251 struct { 1252 __u64 mem_op:5, /* type of opcode */ 1253 mem_lvl:14, /* memory hierarchy level */ 1254 mem_snoop:5, /* snoop mode */ 1255 mem_lock:2, /* lock instr */ 1256 mem_dtlb:7, /* tlb access */ 1257 mem_lvl_num:4, /* memory hierarchy level number */ 1258 mem_remote:1, /* remote */ 1259 mem_snoopx:2, /* snoop mode, ext */ 1260 mem_blk:3, /* access blocked */ 1261 mem_hops:3, /* hop level */ 1262 mem_rsvd:18; 1263 }; 1264 }; 1265 #elif defined(__BIG_ENDIAN_BITFIELD) 1266 union perf_mem_data_src { 1267 __u64 val; 1268 struct { 1269 __u64 mem_rsvd:18, 1270 mem_hops:3, /* hop level */ 1271 mem_blk:3, /* access blocked */ 1272 mem_snoopx:2, /* snoop mode, ext */ 1273 mem_remote:1, /* remote */ 1274 mem_lvl_num:4, /* memory hierarchy level number */ 1275 mem_dtlb:7, /* tlb access */ 1276 mem_lock:2, /* lock instr */ 1277 mem_snoop:5, /* snoop mode */ 1278 mem_lvl:14, /* memory hierarchy level */ 1279 mem_op:5; /* type of opcode */ 1280 }; 1281 }; 1282 #else 1283 #error "Unknown endianness" 1284 #endif 1285 1286 /* type of opcode (load/store/prefetch,code) */ 1287 #define PERF_MEM_OP_NA 0x01 /* not available */ 1288 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */ 1289 #define PERF_MEM_OP_STORE 0x04 /* store instruction */ 1290 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ 1291 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ 1292 #define PERF_MEM_OP_SHIFT 0 1293 1294 /* 1295 * PERF_MEM_LVL_* namespace being depricated to some extent in the 1296 * favour of newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_} fields. 1297 * Supporting this namespace inorder to not break defined ABIs. 1298 * 1299 * memory hierarchy (memory level, hit or miss) 1300 */ 1301 #define PERF_MEM_LVL_NA 0x01 /* not available */ 1302 #define PERF_MEM_LVL_HIT 0x02 /* hit level */ 1303 #define PERF_MEM_LVL_MISS 0x04 /* miss level */ 1304 #define PERF_MEM_LVL_L1 0x08 /* L1 */ 1305 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ 1306 #define PERF_MEM_LVL_L2 0x20 /* L2 */ 1307 #define PERF_MEM_LVL_L3 0x40 /* L3 */ 1308 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ 1309 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ 1310 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ 1311 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ 1312 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ 1313 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 1314 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 1315 #define PERF_MEM_LVL_SHIFT 5 1316 1317 #define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */ 1318 #define PERF_MEM_REMOTE_SHIFT 37 1319 1320 #define PERF_MEM_LVLNUM_L1 0x01 /* L1 */ 1321 #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ 1322 #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ 1323 #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ 1324 /* 5-0xa available */ 1325 #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ 1326 #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ 1327 #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ 1328 #define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */ 1329 #define PERF_MEM_LVLNUM_NA 0x0f /* N/A */ 1330 1331 #define PERF_MEM_LVLNUM_SHIFT 33 1332 1333 /* snoop mode */ 1334 #define PERF_MEM_SNOOP_NA 0x01 /* not available */ 1335 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ 1336 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ 1337 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ 1338 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ 1339 #define PERF_MEM_SNOOP_SHIFT 19 1340 1341 #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ 1342 /* 1 free */ 1343 #define PERF_MEM_SNOOPX_SHIFT 38 1344 1345 /* locked instruction */ 1346 #define PERF_MEM_LOCK_NA 0x01 /* not available */ 1347 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ 1348 #define PERF_MEM_LOCK_SHIFT 24 1349 1350 /* TLB access */ 1351 #define PERF_MEM_TLB_NA 0x01 /* not available */ 1352 #define PERF_MEM_TLB_HIT 0x02 /* hit level */ 1353 #define PERF_MEM_TLB_MISS 0x04 /* miss level */ 1354 #define PERF_MEM_TLB_L1 0x08 /* L1 */ 1355 #define PERF_MEM_TLB_L2 0x10 /* L2 */ 1356 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ 1357 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ 1358 #define PERF_MEM_TLB_SHIFT 26 1359 1360 /* Access blocked */ 1361 #define PERF_MEM_BLK_NA 0x01 /* not available */ 1362 #define PERF_MEM_BLK_DATA 0x02 /* data could not be forwarded */ 1363 #define PERF_MEM_BLK_ADDR 0x04 /* address conflict */ 1364 #define PERF_MEM_BLK_SHIFT 40 1365 1366 /* hop level */ 1367 #define PERF_MEM_HOPS_0 0x01 /* remote core, same node */ 1368 #define PERF_MEM_HOPS_1 0x02 /* remote node, same socket */ 1369 #define PERF_MEM_HOPS_2 0x03 /* remote socket, same board */ 1370 #define PERF_MEM_HOPS_3 0x04 /* remote board */ 1371 /* 5-7 available */ 1372 #define PERF_MEM_HOPS_SHIFT 43 1373 1374 #define PERF_MEM_S(a, s) \ 1375 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 1376 1377 /* 1378 * single taken branch record layout: 1379 * 1380 * from: source instruction (may not always be a branch insn) 1381 * to: branch target 1382 * mispred: branch target was mispredicted 1383 * predicted: branch target was predicted 1384 * 1385 * support for mispred, predicted is optional. In case it 1386 * is not supported mispred = predicted = 0. 1387 * 1388 * in_tx: running in a hardware transaction 1389 * abort: aborting a hardware transaction 1390 * cycles: cycles from last branch (or 0 if not supported) 1391 * type: branch type 1392 * spec: branch speculation info (or 0 if not supported) 1393 */ 1394 struct perf_branch_entry { 1395 __u64 from; 1396 __u64 to; 1397 __u64 mispred:1, /* target mispredicted */ 1398 predicted:1,/* target predicted */ 1399 in_tx:1, /* in transaction */ 1400 abort:1, /* transaction abort */ 1401 cycles:16, /* cycle count to last branch */ 1402 type:4, /* branch type */ 1403 spec:2, /* branch speculation info */ 1404 new_type:4, /* additional branch type */ 1405 reserved:34; 1406 }; 1407 1408 union perf_sample_weight { 1409 __u64 full; 1410 #if defined(__LITTLE_ENDIAN_BITFIELD) 1411 struct { 1412 __u32 var1_dw; 1413 __u16 var2_w; 1414 __u16 var3_w; 1415 }; 1416 #elif defined(__BIG_ENDIAN_BITFIELD) 1417 struct { 1418 __u16 var3_w; 1419 __u16 var2_w; 1420 __u32 var1_dw; 1421 }; 1422 #else 1423 #error "Unknown endianness" 1424 #endif 1425 }; 1426 1427 #endif /* _UAPI_LINUX_PERF_EVENT_H */ 1428