1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Performance events: 4 * 5 * Copyright (C) 2008-2009, Thomas Gleixner <[email protected]> 6 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 7 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 8 * 9 * Data type definitions, declarations, prototypes. 10 * 11 * Started by: Thomas Gleixner and Ingo Molnar 12 * 13 * For licencing details see kernel-base/COPYING 14 */ 15 #ifndef _UAPI_LINUX_PERF_EVENT_H 16 #define _UAPI_LINUX_PERF_EVENT_H 17 18 #include <linux/types.h> 19 #include <linux/ioctl.h> 20 #include <asm/byteorder.h> 21 22 /* 23 * User-space ABI bits: 24 */ 25 26 /* 27 * attr.type 28 */ 29 enum perf_type_id { 30 PERF_TYPE_HARDWARE = 0, 31 PERF_TYPE_SOFTWARE = 1, 32 PERF_TYPE_TRACEPOINT = 2, 33 PERF_TYPE_HW_CACHE = 3, 34 PERF_TYPE_RAW = 4, 35 PERF_TYPE_BREAKPOINT = 5, 36 37 PERF_TYPE_MAX, /* non-ABI */ 38 }; 39 40 /* 41 * attr.config layout for type PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE 42 * PERF_TYPE_HARDWARE: 0xEEEEEEEE000000AA 43 * AA: hardware event ID 44 * EEEEEEEE: PMU type ID 45 * PERF_TYPE_HW_CACHE: 0xEEEEEEEE00DDCCBB 46 * BB: hardware cache ID 47 * CC: hardware cache op ID 48 * DD: hardware cache op result ID 49 * EEEEEEEE: PMU type ID 50 * If the PMU type ID is 0, the PERF_TYPE_RAW will be applied. 51 */ 52 #define PERF_PMU_TYPE_SHIFT 32 53 #define PERF_HW_EVENT_MASK 0xffffffff 54 55 /* 56 * Generalized performance event event_id types, used by the 57 * attr.event_id parameter of the sys_perf_event_open() 58 * syscall: 59 */ 60 enum perf_hw_id { 61 /* 62 * Common hardware events, generalized by the kernel: 63 */ 64 PERF_COUNT_HW_CPU_CYCLES = 0, 65 PERF_COUNT_HW_INSTRUCTIONS = 1, 66 PERF_COUNT_HW_CACHE_REFERENCES = 2, 67 PERF_COUNT_HW_CACHE_MISSES = 3, 68 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 69 PERF_COUNT_HW_BRANCH_MISSES = 5, 70 PERF_COUNT_HW_BUS_CYCLES = 6, 71 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 72 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 73 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 74 75 PERF_COUNT_HW_MAX, /* non-ABI */ 76 }; 77 78 /* 79 * Generalized hardware cache events: 80 * 81 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 82 * { read, write, prefetch } x 83 * { accesses, misses } 84 */ 85 enum perf_hw_cache_id { 86 PERF_COUNT_HW_CACHE_L1D = 0, 87 PERF_COUNT_HW_CACHE_L1I = 1, 88 PERF_COUNT_HW_CACHE_LL = 2, 89 PERF_COUNT_HW_CACHE_DTLB = 3, 90 PERF_COUNT_HW_CACHE_ITLB = 4, 91 PERF_COUNT_HW_CACHE_BPU = 5, 92 PERF_COUNT_HW_CACHE_NODE = 6, 93 94 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 95 }; 96 97 enum perf_hw_cache_op_id { 98 PERF_COUNT_HW_CACHE_OP_READ = 0, 99 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 100 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 101 102 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 103 }; 104 105 enum perf_hw_cache_op_result_id { 106 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 107 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 108 109 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 110 }; 111 112 /* 113 * Special "software" events provided by the kernel, even if the hardware 114 * does not support performance events. These events measure various 115 * physical and sw events of the kernel (and allow the profiling of them as 116 * well): 117 */ 118 enum perf_sw_ids { 119 PERF_COUNT_SW_CPU_CLOCK = 0, 120 PERF_COUNT_SW_TASK_CLOCK = 1, 121 PERF_COUNT_SW_PAGE_FAULTS = 2, 122 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 123 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 124 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 125 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 126 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 127 PERF_COUNT_SW_EMULATION_FAULTS = 8, 128 PERF_COUNT_SW_DUMMY = 9, 129 PERF_COUNT_SW_BPF_OUTPUT = 10, 130 PERF_COUNT_SW_CGROUP_SWITCHES = 11, 131 132 PERF_COUNT_SW_MAX, /* non-ABI */ 133 }; 134 135 /* 136 * Bits that can be set in attr.sample_type to request information 137 * in the overflow packets. 138 */ 139 enum perf_event_sample_format { 140 PERF_SAMPLE_IP = 1U << 0, 141 PERF_SAMPLE_TID = 1U << 1, 142 PERF_SAMPLE_TIME = 1U << 2, 143 PERF_SAMPLE_ADDR = 1U << 3, 144 PERF_SAMPLE_READ = 1U << 4, 145 PERF_SAMPLE_CALLCHAIN = 1U << 5, 146 PERF_SAMPLE_ID = 1U << 6, 147 PERF_SAMPLE_CPU = 1U << 7, 148 PERF_SAMPLE_PERIOD = 1U << 8, 149 PERF_SAMPLE_STREAM_ID = 1U << 9, 150 PERF_SAMPLE_RAW = 1U << 10, 151 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 152 PERF_SAMPLE_REGS_USER = 1U << 12, 153 PERF_SAMPLE_STACK_USER = 1U << 13, 154 PERF_SAMPLE_WEIGHT = 1U << 14, 155 PERF_SAMPLE_DATA_SRC = 1U << 15, 156 PERF_SAMPLE_IDENTIFIER = 1U << 16, 157 PERF_SAMPLE_TRANSACTION = 1U << 17, 158 PERF_SAMPLE_REGS_INTR = 1U << 18, 159 PERF_SAMPLE_PHYS_ADDR = 1U << 19, 160 PERF_SAMPLE_AUX = 1U << 20, 161 PERF_SAMPLE_CGROUP = 1U << 21, 162 PERF_SAMPLE_DATA_PAGE_SIZE = 1U << 22, 163 PERF_SAMPLE_CODE_PAGE_SIZE = 1U << 23, 164 PERF_SAMPLE_WEIGHT_STRUCT = 1U << 24, 165 166 PERF_SAMPLE_MAX = 1U << 25, /* non-ABI */ 167 168 __PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, /* non-ABI; internal use */ 169 }; 170 171 #define PERF_SAMPLE_WEIGHT_TYPE (PERF_SAMPLE_WEIGHT | PERF_SAMPLE_WEIGHT_STRUCT) 172 /* 173 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set 174 * 175 * If the user does not pass priv level information via branch_sample_type, 176 * the kernel uses the event's priv level. Branch and event priv levels do 177 * not have to match. Branch priv level is checked for permissions. 178 * 179 * The branch types can be combined, however BRANCH_ANY covers all types 180 * of branches and therefore it supersedes all the other types. 181 */ 182 enum perf_branch_sample_type_shift { 183 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ 184 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ 185 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ 186 187 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ 188 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ 189 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ 190 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ 191 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ 192 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ 193 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ 194 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ 195 196 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */ 197 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */ 198 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */ 199 200 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */ 201 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */ 202 203 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */ 204 205 PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17, /* save low level index of raw branch records */ 206 207 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ 208 }; 209 210 enum perf_branch_sample_type { 211 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 212 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 213 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 214 215 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 216 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 217 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 218 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 219 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 220 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 221 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 222 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 223 224 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 225 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, 226 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 227 228 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, 229 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 230 231 PERF_SAMPLE_BRANCH_TYPE_SAVE = 232 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, 233 234 PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT, 235 236 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 237 }; 238 239 /* 240 * Common flow change classification 241 */ 242 enum { 243 PERF_BR_UNKNOWN = 0, /* unknown */ 244 PERF_BR_COND = 1, /* conditional */ 245 PERF_BR_UNCOND = 2, /* unconditional */ 246 PERF_BR_IND = 3, /* indirect */ 247 PERF_BR_CALL = 4, /* function call */ 248 PERF_BR_IND_CALL = 5, /* indirect function call */ 249 PERF_BR_RET = 6, /* function return */ 250 PERF_BR_SYSCALL = 7, /* syscall */ 251 PERF_BR_SYSRET = 8, /* syscall return */ 252 PERF_BR_COND_CALL = 9, /* conditional function call */ 253 PERF_BR_COND_RET = 10, /* conditional function return */ 254 PERF_BR_ERET = 11, /* exception return */ 255 PERF_BR_IRQ = 12, /* irq */ 256 PERF_BR_SERROR = 13, /* system error */ 257 PERF_BR_NO_TX = 14, /* not in transaction */ 258 PERF_BR_MAX, 259 }; 260 261 /* 262 * Common branch speculation outcome classification 263 */ 264 enum { 265 PERF_BR_SPEC_NA = 0, /* Not available */ 266 PERF_BR_SPEC_WRONG_PATH = 1, /* Speculative but on wrong path */ 267 PERF_BR_NON_SPEC_CORRECT_PATH = 2, /* Non-speculative but on correct path */ 268 PERF_BR_SPEC_CORRECT_PATH = 3, /* Speculative and on correct path */ 269 PERF_BR_SPEC_MAX, 270 }; 271 272 #define PERF_SAMPLE_BRANCH_PLM_ALL \ 273 (PERF_SAMPLE_BRANCH_USER|\ 274 PERF_SAMPLE_BRANCH_KERNEL|\ 275 PERF_SAMPLE_BRANCH_HV) 276 277 /* 278 * Values to determine ABI of the registers dump. 279 */ 280 enum perf_sample_regs_abi { 281 PERF_SAMPLE_REGS_ABI_NONE = 0, 282 PERF_SAMPLE_REGS_ABI_32 = 1, 283 PERF_SAMPLE_REGS_ABI_64 = 2, 284 }; 285 286 /* 287 * Values for the memory transaction event qualifier, mostly for 288 * abort events. Multiple bits can be set. 289 */ 290 enum { 291 PERF_TXN_ELISION = (1 << 0), /* From elision */ 292 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ 293 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ 294 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ 295 PERF_TXN_RETRY = (1 << 4), /* Retry possible */ 296 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ 297 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ 298 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ 299 300 PERF_TXN_MAX = (1 << 8), /* non-ABI */ 301 302 /* bits 32..63 are reserved for the abort code */ 303 304 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 305 PERF_TXN_ABORT_SHIFT = 32, 306 }; 307 308 /* 309 * The format of the data returned by read() on a perf event fd, 310 * as specified by attr.read_format: 311 * 312 * struct read_format { 313 * { u64 value; 314 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 315 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 316 * { u64 id; } && PERF_FORMAT_ID 317 * { u64 lost; } && PERF_FORMAT_LOST 318 * } && !PERF_FORMAT_GROUP 319 * 320 * { u64 nr; 321 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 322 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 323 * { u64 value; 324 * { u64 id; } && PERF_FORMAT_ID 325 * { u64 lost; } && PERF_FORMAT_LOST 326 * } cntr[nr]; 327 * } && PERF_FORMAT_GROUP 328 * }; 329 */ 330 enum perf_event_read_format { 331 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 332 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 333 PERF_FORMAT_ID = 1U << 2, 334 PERF_FORMAT_GROUP = 1U << 3, 335 PERF_FORMAT_LOST = 1U << 4, 336 337 PERF_FORMAT_MAX = 1U << 5, /* non-ABI */ 338 }; 339 340 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ 341 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ 342 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ 343 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ 344 /* add: sample_stack_user */ 345 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ 346 #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ 347 #define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ 348 #define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */ 349 350 /* 351 * Hardware event_id to monitor via a performance monitoring event: 352 * 353 * @sample_max_stack: Max number of frame pointers in a callchain, 354 * should be < /proc/sys/kernel/perf_event_max_stack 355 */ 356 struct perf_event_attr { 357 358 /* 359 * Major type: hardware/software/tracepoint/etc. 360 */ 361 __u32 type; 362 363 /* 364 * Size of the attr structure, for fwd/bwd compat. 365 */ 366 __u32 size; 367 368 /* 369 * Type specific configuration information. 370 */ 371 __u64 config; 372 373 union { 374 __u64 sample_period; 375 __u64 sample_freq; 376 }; 377 378 __u64 sample_type; 379 __u64 read_format; 380 381 __u64 disabled : 1, /* off by default */ 382 inherit : 1, /* children inherit it */ 383 pinned : 1, /* must always be on PMU */ 384 exclusive : 1, /* only group on PMU */ 385 exclude_user : 1, /* don't count user */ 386 exclude_kernel : 1, /* ditto kernel */ 387 exclude_hv : 1, /* ditto hypervisor */ 388 exclude_idle : 1, /* don't count when idle */ 389 mmap : 1, /* include mmap data */ 390 comm : 1, /* include comm data */ 391 freq : 1, /* use freq, not period */ 392 inherit_stat : 1, /* per task counts */ 393 enable_on_exec : 1, /* next exec enables */ 394 task : 1, /* trace fork/exit */ 395 watermark : 1, /* wakeup_watermark */ 396 /* 397 * precise_ip: 398 * 399 * 0 - SAMPLE_IP can have arbitrary skid 400 * 1 - SAMPLE_IP must have constant skid 401 * 2 - SAMPLE_IP requested to have 0 skid 402 * 3 - SAMPLE_IP must have 0 skid 403 * 404 * See also PERF_RECORD_MISC_EXACT_IP 405 */ 406 precise_ip : 2, /* skid constraint */ 407 mmap_data : 1, /* non-exec mmap data */ 408 sample_id_all : 1, /* sample_type all events */ 409 410 exclude_host : 1, /* don't count in host */ 411 exclude_guest : 1, /* don't count in guest */ 412 413 exclude_callchain_kernel : 1, /* exclude kernel callchains */ 414 exclude_callchain_user : 1, /* exclude user callchains */ 415 mmap2 : 1, /* include mmap with inode data */ 416 comm_exec : 1, /* flag comm events that are due to an exec */ 417 use_clockid : 1, /* use @clockid for time fields */ 418 context_switch : 1, /* context switch data */ 419 write_backward : 1, /* Write ring buffer from end to beginning */ 420 namespaces : 1, /* include namespaces data */ 421 ksymbol : 1, /* include ksymbol events */ 422 bpf_event : 1, /* include bpf events */ 423 aux_output : 1, /* generate AUX records instead of events */ 424 cgroup : 1, /* include cgroup events */ 425 text_poke : 1, /* include text poke events */ 426 build_id : 1, /* use build id in mmap2 events */ 427 inherit_thread : 1, /* children only inherit if cloned with CLONE_THREAD */ 428 remove_on_exec : 1, /* event is removed from task on exec */ 429 sigtrap : 1, /* send synchronous SIGTRAP on event */ 430 __reserved_1 : 26; 431 432 union { 433 __u32 wakeup_events; /* wakeup every n events */ 434 __u32 wakeup_watermark; /* bytes before wakeup */ 435 }; 436 437 __u32 bp_type; 438 union { 439 __u64 bp_addr; 440 __u64 kprobe_func; /* for perf_kprobe */ 441 __u64 uprobe_path; /* for perf_uprobe */ 442 __u64 config1; /* extension of config */ 443 }; 444 union { 445 __u64 bp_len; 446 __u64 kprobe_addr; /* when kprobe_func == NULL */ 447 __u64 probe_offset; /* for perf_[k,u]probe */ 448 __u64 config2; /* extension of config1 */ 449 }; 450 __u64 branch_sample_type; /* enum perf_branch_sample_type */ 451 452 /* 453 * Defines set of user regs to dump on samples. 454 * See asm/perf_regs.h for details. 455 */ 456 __u64 sample_regs_user; 457 458 /* 459 * Defines size of the user stack to dump on samples. 460 */ 461 __u32 sample_stack_user; 462 463 __s32 clockid; 464 /* 465 * Defines set of regs to dump for each sample 466 * state captured on: 467 * - precise = 0: PMU interrupt 468 * - precise > 0: sampled instruction 469 * 470 * See asm/perf_regs.h for details. 471 */ 472 __u64 sample_regs_intr; 473 474 /* 475 * Wakeup watermark for AUX area 476 */ 477 __u32 aux_watermark; 478 __u16 sample_max_stack; 479 __u16 __reserved_2; 480 __u32 aux_sample_size; 481 __u32 __reserved_3; 482 483 /* 484 * User provided data if sigtrap=1, passed back to user via 485 * siginfo_t::si_perf_data, e.g. to permit user to identify the event. 486 * Note, siginfo_t::si_perf_data is long-sized, and sig_data will be 487 * truncated accordingly on 32 bit architectures. 488 */ 489 __u64 sig_data; 490 }; 491 492 /* 493 * Structure used by below PERF_EVENT_IOC_QUERY_BPF command 494 * to query bpf programs attached to the same perf tracepoint 495 * as the given perf event. 496 */ 497 struct perf_event_query_bpf { 498 /* 499 * The below ids array length 500 */ 501 __u32 ids_len; 502 /* 503 * Set by the kernel to indicate the number of 504 * available programs 505 */ 506 __u32 prog_cnt; 507 /* 508 * User provided buffer to store program ids 509 */ 510 __u32 ids[]; 511 }; 512 513 /* 514 * Ioctls that can be done on a perf event fd: 515 */ 516 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 517 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 518 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 519 #define PERF_EVENT_IOC_RESET _IO ('$', 3) 520 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 521 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 522 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 523 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 524 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) 525 #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) 526 #define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) 527 #define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *) 528 529 enum perf_event_ioc_flags { 530 PERF_IOC_FLAG_GROUP = 1U << 0, 531 }; 532 533 /* 534 * Structure of the page that can be mapped via mmap 535 */ 536 struct perf_event_mmap_page { 537 __u32 version; /* version number of this structure */ 538 __u32 compat_version; /* lowest version this is compat with */ 539 540 /* 541 * Bits needed to read the hw events in user-space. 542 * 543 * u32 seq, time_mult, time_shift, index, width; 544 * u64 count, enabled, running; 545 * u64 cyc, time_offset; 546 * s64 pmc = 0; 547 * 548 * do { 549 * seq = pc->lock; 550 * barrier() 551 * 552 * enabled = pc->time_enabled; 553 * running = pc->time_running; 554 * 555 * if (pc->cap_usr_time && enabled != running) { 556 * cyc = rdtsc(); 557 * time_offset = pc->time_offset; 558 * time_mult = pc->time_mult; 559 * time_shift = pc->time_shift; 560 * } 561 * 562 * index = pc->index; 563 * count = pc->offset; 564 * if (pc->cap_user_rdpmc && index) { 565 * width = pc->pmc_width; 566 * pmc = rdpmc(index - 1); 567 * } 568 * 569 * barrier(); 570 * } while (pc->lock != seq); 571 * 572 * NOTE: for obvious reason this only works on self-monitoring 573 * processes. 574 */ 575 __u32 lock; /* seqlock for synchronization */ 576 __u32 index; /* hardware event identifier */ 577 __s64 offset; /* add to hardware event value */ 578 __u64 time_enabled; /* time event active */ 579 __u64 time_running; /* time event on cpu */ 580 union { 581 __u64 capabilities; 582 struct { 583 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ 584 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ 585 586 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ 587 cap_user_time : 1, /* The time_{shift,mult,offset} fields are used */ 588 cap_user_time_zero : 1, /* The time_zero field is used */ 589 cap_user_time_short : 1, /* the time_{cycle,mask} fields are used */ 590 cap_____res : 58; 591 }; 592 }; 593 594 /* 595 * If cap_user_rdpmc this field provides the bit-width of the value 596 * read using the rdpmc() or equivalent instruction. This can be used 597 * to sign extend the result like: 598 * 599 * pmc <<= 64 - width; 600 * pmc >>= 64 - width; // signed shift right 601 * count += pmc; 602 */ 603 __u16 pmc_width; 604 605 /* 606 * If cap_usr_time the below fields can be used to compute the time 607 * delta since time_enabled (in ns) using rdtsc or similar. 608 * 609 * u64 quot, rem; 610 * u64 delta; 611 * 612 * quot = (cyc >> time_shift); 613 * rem = cyc & (((u64)1 << time_shift) - 1); 614 * delta = time_offset + quot * time_mult + 615 * ((rem * time_mult) >> time_shift); 616 * 617 * Where time_offset,time_mult,time_shift and cyc are read in the 618 * seqcount loop described above. This delta can then be added to 619 * enabled and possible running (if index), improving the scaling: 620 * 621 * enabled += delta; 622 * if (index) 623 * running += delta; 624 * 625 * quot = count / running; 626 * rem = count % running; 627 * count = quot * enabled + (rem * enabled) / running; 628 */ 629 __u16 time_shift; 630 __u32 time_mult; 631 __u64 time_offset; 632 /* 633 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated 634 * from sample timestamps. 635 * 636 * time = timestamp - time_zero; 637 * quot = time / time_mult; 638 * rem = time % time_mult; 639 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; 640 * 641 * And vice versa: 642 * 643 * quot = cyc >> time_shift; 644 * rem = cyc & (((u64)1 << time_shift) - 1); 645 * timestamp = time_zero + quot * time_mult + 646 * ((rem * time_mult) >> time_shift); 647 */ 648 __u64 time_zero; 649 650 __u32 size; /* Header size up to __reserved[] fields. */ 651 __u32 __reserved_1; 652 653 /* 654 * If cap_usr_time_short, the hardware clock is less than 64bit wide 655 * and we must compute the 'cyc' value, as used by cap_usr_time, as: 656 * 657 * cyc = time_cycles + ((cyc - time_cycles) & time_mask) 658 * 659 * NOTE: this form is explicitly chosen such that cap_usr_time_short 660 * is a correction on top of cap_usr_time, and code that doesn't 661 * know about cap_usr_time_short still works under the assumption 662 * the counter doesn't wrap. 663 */ 664 __u64 time_cycles; 665 __u64 time_mask; 666 667 /* 668 * Hole for extension of the self monitor capabilities 669 */ 670 671 __u8 __reserved[116*8]; /* align to 1k. */ 672 673 /* 674 * Control data for the mmap() data buffer. 675 * 676 * User-space reading the @data_head value should issue an smp_rmb(), 677 * after reading this value. 678 * 679 * When the mapping is PROT_WRITE the @data_tail value should be 680 * written by userspace to reflect the last read data, after issueing 681 * an smp_mb() to separate the data read from the ->data_tail store. 682 * In this case the kernel will not over-write unread data. 683 * 684 * See perf_output_put_handle() for the data ordering. 685 * 686 * data_{offset,size} indicate the location and size of the perf record 687 * buffer within the mmapped area. 688 */ 689 __u64 data_head; /* head in the data section */ 690 __u64 data_tail; /* user-space written tail */ 691 __u64 data_offset; /* where the buffer starts */ 692 __u64 data_size; /* data buffer size */ 693 694 /* 695 * AUX area is defined by aux_{offset,size} fields that should be set 696 * by the userspace, so that 697 * 698 * aux_offset >= data_offset + data_size 699 * 700 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size. 701 * 702 * Ring buffer pointers aux_{head,tail} have the same semantics as 703 * data_{head,tail} and same ordering rules apply. 704 */ 705 __u64 aux_head; 706 __u64 aux_tail; 707 __u64 aux_offset; 708 __u64 aux_size; 709 }; 710 711 /* 712 * The current state of perf_event_header::misc bits usage: 713 * ('|' used bit, '-' unused bit) 714 * 715 * 012 CDEF 716 * |||---------|||| 717 * 718 * Where: 719 * 0-2 CPUMODE_MASK 720 * 721 * C PROC_MAP_PARSE_TIMEOUT 722 * D MMAP_DATA / COMM_EXEC / FORK_EXEC / SWITCH_OUT 723 * E MMAP_BUILD_ID / EXACT_IP / SCHED_OUT_PREEMPT 724 * F (reserved) 725 */ 726 727 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 728 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 729 #define PERF_RECORD_MISC_KERNEL (1 << 0) 730 #define PERF_RECORD_MISC_USER (2 << 0) 731 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 732 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 733 #define PERF_RECORD_MISC_GUEST_USER (5 << 0) 734 735 /* 736 * Indicates that /proc/PID/maps parsing are truncated by time out. 737 */ 738 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) 739 /* 740 * Following PERF_RECORD_MISC_* are used on different 741 * events, so can reuse the same bit position: 742 * 743 * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events 744 * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event 745 * PERF_RECORD_MISC_FORK_EXEC - PERF_RECORD_FORK event (perf internal) 746 * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events 747 */ 748 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 749 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 750 #define PERF_RECORD_MISC_FORK_EXEC (1 << 13) 751 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) 752 /* 753 * These PERF_RECORD_MISC_* flags below are safely reused 754 * for the following events: 755 * 756 * PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events 757 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events 758 * PERF_RECORD_MISC_MMAP_BUILD_ID - PERF_RECORD_MMAP2 event 759 * 760 * 761 * PERF_RECORD_MISC_EXACT_IP: 762 * Indicates that the content of PERF_SAMPLE_IP points to 763 * the actual instruction that triggered the event. See also 764 * perf_event_attr::precise_ip. 765 * 766 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT: 767 * Indicates that thread was preempted in TASK_RUNNING state. 768 * 769 * PERF_RECORD_MISC_MMAP_BUILD_ID: 770 * Indicates that mmap2 event carries build id data. 771 */ 772 #define PERF_RECORD_MISC_EXACT_IP (1 << 14) 773 #define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14) 774 #define PERF_RECORD_MISC_MMAP_BUILD_ID (1 << 14) 775 /* 776 * Reserve the last bit to indicate some extended misc field 777 */ 778 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 779 780 struct perf_event_header { 781 __u32 type; 782 __u16 misc; 783 __u16 size; 784 }; 785 786 struct perf_ns_link_info { 787 __u64 dev; 788 __u64 ino; 789 }; 790 791 enum { 792 NET_NS_INDEX = 0, 793 UTS_NS_INDEX = 1, 794 IPC_NS_INDEX = 2, 795 PID_NS_INDEX = 3, 796 USER_NS_INDEX = 4, 797 MNT_NS_INDEX = 5, 798 CGROUP_NS_INDEX = 6, 799 800 NR_NAMESPACES, /* number of available namespaces */ 801 }; 802 803 enum perf_event_type { 804 805 /* 806 * If perf_event_attr.sample_id_all is set then all event types will 807 * have the sample_type selected fields related to where/when 808 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, 809 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed 810 * just after the perf_event_header and the fields already present for 811 * the existing fields, i.e. at the end of the payload. That way a newer 812 * perf.data file will be supported by older perf tools, with these new 813 * optional fields being ignored. 814 * 815 * struct sample_id { 816 * { u32 pid, tid; } && PERF_SAMPLE_TID 817 * { u64 time; } && PERF_SAMPLE_TIME 818 * { u64 id; } && PERF_SAMPLE_ID 819 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 820 * { u32 cpu, res; } && PERF_SAMPLE_CPU 821 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 822 * } && perf_event_attr::sample_id_all 823 * 824 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The 825 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed 826 * relative to header.size. 827 */ 828 829 /* 830 * The MMAP events record the PROT_EXEC mappings so that we can 831 * correlate userspace IPs to code. They have the following structure: 832 * 833 * struct { 834 * struct perf_event_header header; 835 * 836 * u32 pid, tid; 837 * u64 addr; 838 * u64 len; 839 * u64 pgoff; 840 * char filename[]; 841 * struct sample_id sample_id; 842 * }; 843 */ 844 PERF_RECORD_MMAP = 1, 845 846 /* 847 * struct { 848 * struct perf_event_header header; 849 * u64 id; 850 * u64 lost; 851 * struct sample_id sample_id; 852 * }; 853 */ 854 PERF_RECORD_LOST = 2, 855 856 /* 857 * struct { 858 * struct perf_event_header header; 859 * 860 * u32 pid, tid; 861 * char comm[]; 862 * struct sample_id sample_id; 863 * }; 864 */ 865 PERF_RECORD_COMM = 3, 866 867 /* 868 * struct { 869 * struct perf_event_header header; 870 * u32 pid, ppid; 871 * u32 tid, ptid; 872 * u64 time; 873 * struct sample_id sample_id; 874 * }; 875 */ 876 PERF_RECORD_EXIT = 4, 877 878 /* 879 * struct { 880 * struct perf_event_header header; 881 * u64 time; 882 * u64 id; 883 * u64 stream_id; 884 * struct sample_id sample_id; 885 * }; 886 */ 887 PERF_RECORD_THROTTLE = 5, 888 PERF_RECORD_UNTHROTTLE = 6, 889 890 /* 891 * struct { 892 * struct perf_event_header header; 893 * u32 pid, ppid; 894 * u32 tid, ptid; 895 * u64 time; 896 * struct sample_id sample_id; 897 * }; 898 */ 899 PERF_RECORD_FORK = 7, 900 901 /* 902 * struct { 903 * struct perf_event_header header; 904 * u32 pid, tid; 905 * 906 * struct read_format values; 907 * struct sample_id sample_id; 908 * }; 909 */ 910 PERF_RECORD_READ = 8, 911 912 /* 913 * struct { 914 * struct perf_event_header header; 915 * 916 * # 917 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. 918 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position 919 * # is fixed relative to header. 920 * # 921 * 922 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 923 * { u64 ip; } && PERF_SAMPLE_IP 924 * { u32 pid, tid; } && PERF_SAMPLE_TID 925 * { u64 time; } && PERF_SAMPLE_TIME 926 * { u64 addr; } && PERF_SAMPLE_ADDR 927 * { u64 id; } && PERF_SAMPLE_ID 928 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 929 * { u32 cpu, res; } && PERF_SAMPLE_CPU 930 * { u64 period; } && PERF_SAMPLE_PERIOD 931 * 932 * { struct read_format values; } && PERF_SAMPLE_READ 933 * 934 * { u64 nr, 935 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 936 * 937 * # 938 * # The RAW record below is opaque data wrt the ABI 939 * # 940 * # That is, the ABI doesn't make any promises wrt to 941 * # the stability of its content, it may vary depending 942 * # on event, hardware, kernel version and phase of 943 * # the moon. 944 * # 945 * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 946 * # 947 * 948 * { u32 size; 949 * char data[size];}&& PERF_SAMPLE_RAW 950 * 951 * { u64 nr; 952 * { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX 953 * { u64 from, to, flags } lbr[nr]; 954 * } && PERF_SAMPLE_BRANCH_STACK 955 * 956 * { u64 abi; # enum perf_sample_regs_abi 957 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER 958 * 959 * { u64 size; 960 * char data[size]; 961 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 962 * 963 * { union perf_sample_weight 964 * { 965 * u64 full; && PERF_SAMPLE_WEIGHT 966 * #if defined(__LITTLE_ENDIAN_BITFIELD) 967 * struct { 968 * u32 var1_dw; 969 * u16 var2_w; 970 * u16 var3_w; 971 * } && PERF_SAMPLE_WEIGHT_STRUCT 972 * #elif defined(__BIG_ENDIAN_BITFIELD) 973 * struct { 974 * u16 var3_w; 975 * u16 var2_w; 976 * u32 var1_dw; 977 * } && PERF_SAMPLE_WEIGHT_STRUCT 978 * #endif 979 * } 980 * } 981 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 982 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION 983 * { u64 abi; # enum perf_sample_regs_abi 984 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR 985 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR 986 * { u64 size; 987 * char data[size]; } && PERF_SAMPLE_AUX 988 * { u64 data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE 989 * { u64 code_page_size;} && PERF_SAMPLE_CODE_PAGE_SIZE 990 * }; 991 */ 992 PERF_RECORD_SAMPLE = 9, 993 994 /* 995 * The MMAP2 records are an augmented version of MMAP, they add 996 * maj, min, ino numbers to be used to uniquely identify each mapping 997 * 998 * struct { 999 * struct perf_event_header header; 1000 * 1001 * u32 pid, tid; 1002 * u64 addr; 1003 * u64 len; 1004 * u64 pgoff; 1005 * union { 1006 * struct { 1007 * u32 maj; 1008 * u32 min; 1009 * u64 ino; 1010 * u64 ino_generation; 1011 * }; 1012 * struct { 1013 * u8 build_id_size; 1014 * u8 __reserved_1; 1015 * u16 __reserved_2; 1016 * u8 build_id[20]; 1017 * }; 1018 * }; 1019 * u32 prot, flags; 1020 * char filename[]; 1021 * struct sample_id sample_id; 1022 * }; 1023 */ 1024 PERF_RECORD_MMAP2 = 10, 1025 1026 /* 1027 * Records that new data landed in the AUX buffer part. 1028 * 1029 * struct { 1030 * struct perf_event_header header; 1031 * 1032 * u64 aux_offset; 1033 * u64 aux_size; 1034 * u64 flags; 1035 * struct sample_id sample_id; 1036 * }; 1037 */ 1038 PERF_RECORD_AUX = 11, 1039 1040 /* 1041 * Indicates that instruction trace has started 1042 * 1043 * struct { 1044 * struct perf_event_header header; 1045 * u32 pid; 1046 * u32 tid; 1047 * struct sample_id sample_id; 1048 * }; 1049 */ 1050 PERF_RECORD_ITRACE_START = 12, 1051 1052 /* 1053 * Records the dropped/lost sample number. 1054 * 1055 * struct { 1056 * struct perf_event_header header; 1057 * 1058 * u64 lost; 1059 * struct sample_id sample_id; 1060 * }; 1061 */ 1062 PERF_RECORD_LOST_SAMPLES = 13, 1063 1064 /* 1065 * Records a context switch in or out (flagged by 1066 * PERF_RECORD_MISC_SWITCH_OUT). See also 1067 * PERF_RECORD_SWITCH_CPU_WIDE. 1068 * 1069 * struct { 1070 * struct perf_event_header header; 1071 * struct sample_id sample_id; 1072 * }; 1073 */ 1074 PERF_RECORD_SWITCH = 14, 1075 1076 /* 1077 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and 1078 * next_prev_tid that are the next (switching out) or previous 1079 * (switching in) pid/tid. 1080 * 1081 * struct { 1082 * struct perf_event_header header; 1083 * u32 next_prev_pid; 1084 * u32 next_prev_tid; 1085 * struct sample_id sample_id; 1086 * }; 1087 */ 1088 PERF_RECORD_SWITCH_CPU_WIDE = 15, 1089 1090 /* 1091 * struct { 1092 * struct perf_event_header header; 1093 * u32 pid; 1094 * u32 tid; 1095 * u64 nr_namespaces; 1096 * { u64 dev, inode; } [nr_namespaces]; 1097 * struct sample_id sample_id; 1098 * }; 1099 */ 1100 PERF_RECORD_NAMESPACES = 16, 1101 1102 /* 1103 * Record ksymbol register/unregister events: 1104 * 1105 * struct { 1106 * struct perf_event_header header; 1107 * u64 addr; 1108 * u32 len; 1109 * u16 ksym_type; 1110 * u16 flags; 1111 * char name[]; 1112 * struct sample_id sample_id; 1113 * }; 1114 */ 1115 PERF_RECORD_KSYMBOL = 17, 1116 1117 /* 1118 * Record bpf events: 1119 * enum perf_bpf_event_type { 1120 * PERF_BPF_EVENT_UNKNOWN = 0, 1121 * PERF_BPF_EVENT_PROG_LOAD = 1, 1122 * PERF_BPF_EVENT_PROG_UNLOAD = 2, 1123 * }; 1124 * 1125 * struct { 1126 * struct perf_event_header header; 1127 * u16 type; 1128 * u16 flags; 1129 * u32 id; 1130 * u8 tag[BPF_TAG_SIZE]; 1131 * struct sample_id sample_id; 1132 * }; 1133 */ 1134 PERF_RECORD_BPF_EVENT = 18, 1135 1136 /* 1137 * struct { 1138 * struct perf_event_header header; 1139 * u64 id; 1140 * char path[]; 1141 * struct sample_id sample_id; 1142 * }; 1143 */ 1144 PERF_RECORD_CGROUP = 19, 1145 1146 /* 1147 * Records changes to kernel text i.e. self-modified code. 'old_len' is 1148 * the number of old bytes, 'new_len' is the number of new bytes. Either 1149 * 'old_len' or 'new_len' may be zero to indicate, for example, the 1150 * addition or removal of a trampoline. 'bytes' contains the old bytes 1151 * followed immediately by the new bytes. 1152 * 1153 * struct { 1154 * struct perf_event_header header; 1155 * u64 addr; 1156 * u16 old_len; 1157 * u16 new_len; 1158 * u8 bytes[]; 1159 * struct sample_id sample_id; 1160 * }; 1161 */ 1162 PERF_RECORD_TEXT_POKE = 20, 1163 1164 /* 1165 * Data written to the AUX area by hardware due to aux_output, may need 1166 * to be matched to the event by an architecture-specific hardware ID. 1167 * This records the hardware ID, but requires sample_id to provide the 1168 * event ID. e.g. Intel PT uses this record to disambiguate PEBS-via-PT 1169 * records from multiple events. 1170 * 1171 * struct { 1172 * struct perf_event_header header; 1173 * u64 hw_id; 1174 * struct sample_id sample_id; 1175 * }; 1176 */ 1177 PERF_RECORD_AUX_OUTPUT_HW_ID = 21, 1178 1179 PERF_RECORD_MAX, /* non-ABI */ 1180 }; 1181 1182 enum perf_record_ksymbol_type { 1183 PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0, 1184 PERF_RECORD_KSYMBOL_TYPE_BPF = 1, 1185 /* 1186 * Out of line code such as kprobe-replaced instructions or optimized 1187 * kprobes or ftrace trampolines. 1188 */ 1189 PERF_RECORD_KSYMBOL_TYPE_OOL = 2, 1190 PERF_RECORD_KSYMBOL_TYPE_MAX /* non-ABI */ 1191 }; 1192 1193 #define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0) 1194 1195 enum perf_bpf_event_type { 1196 PERF_BPF_EVENT_UNKNOWN = 0, 1197 PERF_BPF_EVENT_PROG_LOAD = 1, 1198 PERF_BPF_EVENT_PROG_UNLOAD = 2, 1199 PERF_BPF_EVENT_MAX, /* non-ABI */ 1200 }; 1201 1202 #define PERF_MAX_STACK_DEPTH 127 1203 #define PERF_MAX_CONTEXTS_PER_STACK 8 1204 1205 enum perf_callchain_context { 1206 PERF_CONTEXT_HV = (__u64)-32, 1207 PERF_CONTEXT_KERNEL = (__u64)-128, 1208 PERF_CONTEXT_USER = (__u64)-512, 1209 1210 PERF_CONTEXT_GUEST = (__u64)-2048, 1211 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 1212 PERF_CONTEXT_GUEST_USER = (__u64)-2560, 1213 1214 PERF_CONTEXT_MAX = (__u64)-4095, 1215 }; 1216 1217 /** 1218 * PERF_RECORD_AUX::flags bits 1219 */ 1220 #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ 1221 #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ 1222 #define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ 1223 #define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ 1224 #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */ 1225 1226 /* CoreSight PMU AUX buffer formats */ 1227 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */ 1228 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format of the source */ 1229 1230 #define PERF_FLAG_FD_NO_GROUP (1UL << 0) 1231 #define PERF_FLAG_FD_OUTPUT (1UL << 1) 1232 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ 1233 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ 1234 1235 #if defined(__LITTLE_ENDIAN_BITFIELD) 1236 union perf_mem_data_src { 1237 __u64 val; 1238 struct { 1239 __u64 mem_op:5, /* type of opcode */ 1240 mem_lvl:14, /* memory hierarchy level */ 1241 mem_snoop:5, /* snoop mode */ 1242 mem_lock:2, /* lock instr */ 1243 mem_dtlb:7, /* tlb access */ 1244 mem_lvl_num:4, /* memory hierarchy level number */ 1245 mem_remote:1, /* remote */ 1246 mem_snoopx:2, /* snoop mode, ext */ 1247 mem_blk:3, /* access blocked */ 1248 mem_hops:3, /* hop level */ 1249 mem_rsvd:18; 1250 }; 1251 }; 1252 #elif defined(__BIG_ENDIAN_BITFIELD) 1253 union perf_mem_data_src { 1254 __u64 val; 1255 struct { 1256 __u64 mem_rsvd:18, 1257 mem_hops:3, /* hop level */ 1258 mem_blk:3, /* access blocked */ 1259 mem_snoopx:2, /* snoop mode, ext */ 1260 mem_remote:1, /* remote */ 1261 mem_lvl_num:4, /* memory hierarchy level number */ 1262 mem_dtlb:7, /* tlb access */ 1263 mem_lock:2, /* lock instr */ 1264 mem_snoop:5, /* snoop mode */ 1265 mem_lvl:14, /* memory hierarchy level */ 1266 mem_op:5; /* type of opcode */ 1267 }; 1268 }; 1269 #else 1270 #error "Unknown endianness" 1271 #endif 1272 1273 /* type of opcode (load/store/prefetch,code) */ 1274 #define PERF_MEM_OP_NA 0x01 /* not available */ 1275 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */ 1276 #define PERF_MEM_OP_STORE 0x04 /* store instruction */ 1277 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ 1278 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ 1279 #define PERF_MEM_OP_SHIFT 0 1280 1281 /* 1282 * PERF_MEM_LVL_* namespace being depricated to some extent in the 1283 * favour of newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_} fields. 1284 * Supporting this namespace inorder to not break defined ABIs. 1285 * 1286 * memory hierarchy (memory level, hit or miss) 1287 */ 1288 #define PERF_MEM_LVL_NA 0x01 /* not available */ 1289 #define PERF_MEM_LVL_HIT 0x02 /* hit level */ 1290 #define PERF_MEM_LVL_MISS 0x04 /* miss level */ 1291 #define PERF_MEM_LVL_L1 0x08 /* L1 */ 1292 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ 1293 #define PERF_MEM_LVL_L2 0x20 /* L2 */ 1294 #define PERF_MEM_LVL_L3 0x40 /* L3 */ 1295 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ 1296 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ 1297 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ 1298 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ 1299 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ 1300 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 1301 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 1302 #define PERF_MEM_LVL_SHIFT 5 1303 1304 #define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */ 1305 #define PERF_MEM_REMOTE_SHIFT 37 1306 1307 #define PERF_MEM_LVLNUM_L1 0x01 /* L1 */ 1308 #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ 1309 #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ 1310 #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ 1311 /* 5-0xa available */ 1312 #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ 1313 #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ 1314 #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ 1315 #define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */ 1316 #define PERF_MEM_LVLNUM_NA 0x0f /* N/A */ 1317 1318 #define PERF_MEM_LVLNUM_SHIFT 33 1319 1320 /* snoop mode */ 1321 #define PERF_MEM_SNOOP_NA 0x01 /* not available */ 1322 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ 1323 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ 1324 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ 1325 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ 1326 #define PERF_MEM_SNOOP_SHIFT 19 1327 1328 #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ 1329 /* 1 free */ 1330 #define PERF_MEM_SNOOPX_SHIFT 38 1331 1332 /* locked instruction */ 1333 #define PERF_MEM_LOCK_NA 0x01 /* not available */ 1334 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ 1335 #define PERF_MEM_LOCK_SHIFT 24 1336 1337 /* TLB access */ 1338 #define PERF_MEM_TLB_NA 0x01 /* not available */ 1339 #define PERF_MEM_TLB_HIT 0x02 /* hit level */ 1340 #define PERF_MEM_TLB_MISS 0x04 /* miss level */ 1341 #define PERF_MEM_TLB_L1 0x08 /* L1 */ 1342 #define PERF_MEM_TLB_L2 0x10 /* L2 */ 1343 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ 1344 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ 1345 #define PERF_MEM_TLB_SHIFT 26 1346 1347 /* Access blocked */ 1348 #define PERF_MEM_BLK_NA 0x01 /* not available */ 1349 #define PERF_MEM_BLK_DATA 0x02 /* data could not be forwarded */ 1350 #define PERF_MEM_BLK_ADDR 0x04 /* address conflict */ 1351 #define PERF_MEM_BLK_SHIFT 40 1352 1353 /* hop level */ 1354 #define PERF_MEM_HOPS_0 0x01 /* remote core, same node */ 1355 #define PERF_MEM_HOPS_1 0x02 /* remote node, same socket */ 1356 #define PERF_MEM_HOPS_2 0x03 /* remote socket, same board */ 1357 #define PERF_MEM_HOPS_3 0x04 /* remote board */ 1358 /* 5-7 available */ 1359 #define PERF_MEM_HOPS_SHIFT 43 1360 1361 #define PERF_MEM_S(a, s) \ 1362 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 1363 1364 /* 1365 * single taken branch record layout: 1366 * 1367 * from: source instruction (may not always be a branch insn) 1368 * to: branch target 1369 * mispred: branch target was mispredicted 1370 * predicted: branch target was predicted 1371 * 1372 * support for mispred, predicted is optional. In case it 1373 * is not supported mispred = predicted = 0. 1374 * 1375 * in_tx: running in a hardware transaction 1376 * abort: aborting a hardware transaction 1377 * cycles: cycles from last branch (or 0 if not supported) 1378 * type: branch type 1379 * spec: branch speculation info (or 0 if not supported) 1380 */ 1381 struct perf_branch_entry { 1382 __u64 from; 1383 __u64 to; 1384 __u64 mispred:1, /* target mispredicted */ 1385 predicted:1,/* target predicted */ 1386 in_tx:1, /* in transaction */ 1387 abort:1, /* transaction abort */ 1388 cycles:16, /* cycle count to last branch */ 1389 type:4, /* branch type */ 1390 spec:2, /* branch speculation info */ 1391 reserved:38; 1392 }; 1393 1394 union perf_sample_weight { 1395 __u64 full; 1396 #if defined(__LITTLE_ENDIAN_BITFIELD) 1397 struct { 1398 __u32 var1_dw; 1399 __u16 var2_w; 1400 __u16 var3_w; 1401 }; 1402 #elif defined(__BIG_ENDIAN_BITFIELD) 1403 struct { 1404 __u16 var3_w; 1405 __u16 var2_w; 1406 __u32 var1_dw; 1407 }; 1408 #else 1409 #error "Unknown endianness" 1410 #endif 1411 }; 1412 1413 #endif /* _UAPI_LINUX_PERF_EVENT_H */ 1414