1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Performance events: 4 * 5 * Copyright (C) 2008-2009, Thomas Gleixner <[email protected]> 6 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 7 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 8 * 9 * Data type definitions, declarations, prototypes. 10 * 11 * Started by: Thomas Gleixner and Ingo Molnar 12 * 13 * For licencing details see kernel-base/COPYING 14 */ 15 #ifndef _UAPI_LINUX_PERF_EVENT_H 16 #define _UAPI_LINUX_PERF_EVENT_H 17 18 #include <linux/types.h> 19 #include <linux/ioctl.h> 20 #include <asm/byteorder.h> 21 22 /* 23 * User-space ABI bits: 24 */ 25 26 /* 27 * attr.type 28 */ 29 enum perf_type_id { 30 PERF_TYPE_HARDWARE = 0, 31 PERF_TYPE_SOFTWARE = 1, 32 PERF_TYPE_TRACEPOINT = 2, 33 PERF_TYPE_HW_CACHE = 3, 34 PERF_TYPE_RAW = 4, 35 PERF_TYPE_BREAKPOINT = 5, 36 37 PERF_TYPE_MAX, /* non-ABI */ 38 }; 39 40 /* 41 * Generalized performance event event_id types, used by the 42 * attr.event_id parameter of the sys_perf_event_open() 43 * syscall: 44 */ 45 enum perf_hw_id { 46 /* 47 * Common hardware events, generalized by the kernel: 48 */ 49 PERF_COUNT_HW_CPU_CYCLES = 0, 50 PERF_COUNT_HW_INSTRUCTIONS = 1, 51 PERF_COUNT_HW_CACHE_REFERENCES = 2, 52 PERF_COUNT_HW_CACHE_MISSES = 3, 53 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 54 PERF_COUNT_HW_BRANCH_MISSES = 5, 55 PERF_COUNT_HW_BUS_CYCLES = 6, 56 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 57 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 58 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 59 60 PERF_COUNT_HW_MAX, /* non-ABI */ 61 }; 62 63 /* 64 * Generalized hardware cache events: 65 * 66 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 67 * { read, write, prefetch } x 68 * { accesses, misses } 69 */ 70 enum perf_hw_cache_id { 71 PERF_COUNT_HW_CACHE_L1D = 0, 72 PERF_COUNT_HW_CACHE_L1I = 1, 73 PERF_COUNT_HW_CACHE_LL = 2, 74 PERF_COUNT_HW_CACHE_DTLB = 3, 75 PERF_COUNT_HW_CACHE_ITLB = 4, 76 PERF_COUNT_HW_CACHE_BPU = 5, 77 PERF_COUNT_HW_CACHE_NODE = 6, 78 79 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 80 }; 81 82 enum perf_hw_cache_op_id { 83 PERF_COUNT_HW_CACHE_OP_READ = 0, 84 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 85 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 86 87 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 88 }; 89 90 enum perf_hw_cache_op_result_id { 91 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 92 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 93 94 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 95 }; 96 97 /* 98 * Special "software" events provided by the kernel, even if the hardware 99 * does not support performance events. These events measure various 100 * physical and sw events of the kernel (and allow the profiling of them as 101 * well): 102 */ 103 enum perf_sw_ids { 104 PERF_COUNT_SW_CPU_CLOCK = 0, 105 PERF_COUNT_SW_TASK_CLOCK = 1, 106 PERF_COUNT_SW_PAGE_FAULTS = 2, 107 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 108 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 109 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 110 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 111 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 112 PERF_COUNT_SW_EMULATION_FAULTS = 8, 113 PERF_COUNT_SW_DUMMY = 9, 114 PERF_COUNT_SW_BPF_OUTPUT = 10, 115 116 PERF_COUNT_SW_MAX, /* non-ABI */ 117 }; 118 119 /* 120 * Bits that can be set in attr.sample_type to request information 121 * in the overflow packets. 122 */ 123 enum perf_event_sample_format { 124 PERF_SAMPLE_IP = 1U << 0, 125 PERF_SAMPLE_TID = 1U << 1, 126 PERF_SAMPLE_TIME = 1U << 2, 127 PERF_SAMPLE_ADDR = 1U << 3, 128 PERF_SAMPLE_READ = 1U << 4, 129 PERF_SAMPLE_CALLCHAIN = 1U << 5, 130 PERF_SAMPLE_ID = 1U << 6, 131 PERF_SAMPLE_CPU = 1U << 7, 132 PERF_SAMPLE_PERIOD = 1U << 8, 133 PERF_SAMPLE_STREAM_ID = 1U << 9, 134 PERF_SAMPLE_RAW = 1U << 10, 135 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 136 PERF_SAMPLE_REGS_USER = 1U << 12, 137 PERF_SAMPLE_STACK_USER = 1U << 13, 138 PERF_SAMPLE_WEIGHT = 1U << 14, 139 PERF_SAMPLE_DATA_SRC = 1U << 15, 140 PERF_SAMPLE_IDENTIFIER = 1U << 16, 141 PERF_SAMPLE_TRANSACTION = 1U << 17, 142 PERF_SAMPLE_REGS_INTR = 1U << 18, 143 PERF_SAMPLE_PHYS_ADDR = 1U << 19, 144 PERF_SAMPLE_AUX = 1U << 20, 145 146 PERF_SAMPLE_MAX = 1U << 21, /* non-ABI */ 147 148 __PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, /* non-ABI; internal use */ 149 }; 150 151 /* 152 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set 153 * 154 * If the user does not pass priv level information via branch_sample_type, 155 * the kernel uses the event's priv level. Branch and event priv levels do 156 * not have to match. Branch priv level is checked for permissions. 157 * 158 * The branch types can be combined, however BRANCH_ANY covers all types 159 * of branches and therefore it supersedes all the other types. 160 */ 161 enum perf_branch_sample_type_shift { 162 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ 163 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ 164 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ 165 166 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ 167 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ 168 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ 169 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ 170 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ 171 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ 172 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ 173 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ 174 175 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */ 176 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */ 177 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */ 178 179 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */ 180 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */ 181 182 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */ 183 184 PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17, /* save low level index of raw branch records */ 185 186 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ 187 }; 188 189 enum perf_branch_sample_type { 190 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 191 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 192 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 193 194 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 195 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 196 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 197 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 198 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 199 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 200 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 201 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 202 203 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 204 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, 205 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 206 207 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, 208 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 209 210 PERF_SAMPLE_BRANCH_TYPE_SAVE = 211 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, 212 213 PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT, 214 215 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 216 }; 217 218 /* 219 * Common flow change classification 220 */ 221 enum { 222 PERF_BR_UNKNOWN = 0, /* unknown */ 223 PERF_BR_COND = 1, /* conditional */ 224 PERF_BR_UNCOND = 2, /* unconditional */ 225 PERF_BR_IND = 3, /* indirect */ 226 PERF_BR_CALL = 4, /* function call */ 227 PERF_BR_IND_CALL = 5, /* indirect function call */ 228 PERF_BR_RET = 6, /* function return */ 229 PERF_BR_SYSCALL = 7, /* syscall */ 230 PERF_BR_SYSRET = 8, /* syscall return */ 231 PERF_BR_COND_CALL = 9, /* conditional function call */ 232 PERF_BR_COND_RET = 10, /* conditional function return */ 233 PERF_BR_MAX, 234 }; 235 236 #define PERF_SAMPLE_BRANCH_PLM_ALL \ 237 (PERF_SAMPLE_BRANCH_USER|\ 238 PERF_SAMPLE_BRANCH_KERNEL|\ 239 PERF_SAMPLE_BRANCH_HV) 240 241 /* 242 * Values to determine ABI of the registers dump. 243 */ 244 enum perf_sample_regs_abi { 245 PERF_SAMPLE_REGS_ABI_NONE = 0, 246 PERF_SAMPLE_REGS_ABI_32 = 1, 247 PERF_SAMPLE_REGS_ABI_64 = 2, 248 }; 249 250 /* 251 * Values for the memory transaction event qualifier, mostly for 252 * abort events. Multiple bits can be set. 253 */ 254 enum { 255 PERF_TXN_ELISION = (1 << 0), /* From elision */ 256 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ 257 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ 258 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ 259 PERF_TXN_RETRY = (1 << 4), /* Retry possible */ 260 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ 261 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ 262 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ 263 264 PERF_TXN_MAX = (1 << 8), /* non-ABI */ 265 266 /* bits 32..63 are reserved for the abort code */ 267 268 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 269 PERF_TXN_ABORT_SHIFT = 32, 270 }; 271 272 /* 273 * The format of the data returned by read() on a perf event fd, 274 * as specified by attr.read_format: 275 * 276 * struct read_format { 277 * { u64 value; 278 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 279 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 280 * { u64 id; } && PERF_FORMAT_ID 281 * } && !PERF_FORMAT_GROUP 282 * 283 * { u64 nr; 284 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 285 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 286 * { u64 value; 287 * { u64 id; } && PERF_FORMAT_ID 288 * } cntr[nr]; 289 * } && PERF_FORMAT_GROUP 290 * }; 291 */ 292 enum perf_event_read_format { 293 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 294 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 295 PERF_FORMAT_ID = 1U << 2, 296 PERF_FORMAT_GROUP = 1U << 3, 297 298 PERF_FORMAT_MAX = 1U << 4, /* non-ABI */ 299 }; 300 301 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ 302 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ 303 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ 304 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ 305 /* add: sample_stack_user */ 306 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ 307 #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ 308 #define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ 309 310 /* 311 * Hardware event_id to monitor via a performance monitoring event: 312 * 313 * @sample_max_stack: Max number of frame pointers in a callchain, 314 * should be < /proc/sys/kernel/perf_event_max_stack 315 */ 316 struct perf_event_attr { 317 318 /* 319 * Major type: hardware/software/tracepoint/etc. 320 */ 321 __u32 type; 322 323 /* 324 * Size of the attr structure, for fwd/bwd compat. 325 */ 326 __u32 size; 327 328 /* 329 * Type specific configuration information. 330 */ 331 __u64 config; 332 333 union { 334 __u64 sample_period; 335 __u64 sample_freq; 336 }; 337 338 __u64 sample_type; 339 __u64 read_format; 340 341 __u64 disabled : 1, /* off by default */ 342 inherit : 1, /* children inherit it */ 343 pinned : 1, /* must always be on PMU */ 344 exclusive : 1, /* only group on PMU */ 345 exclude_user : 1, /* don't count user */ 346 exclude_kernel : 1, /* ditto kernel */ 347 exclude_hv : 1, /* ditto hypervisor */ 348 exclude_idle : 1, /* don't count when idle */ 349 mmap : 1, /* include mmap data */ 350 comm : 1, /* include comm data */ 351 freq : 1, /* use freq, not period */ 352 inherit_stat : 1, /* per task counts */ 353 enable_on_exec : 1, /* next exec enables */ 354 task : 1, /* trace fork/exit */ 355 watermark : 1, /* wakeup_watermark */ 356 /* 357 * precise_ip: 358 * 359 * 0 - SAMPLE_IP can have arbitrary skid 360 * 1 - SAMPLE_IP must have constant skid 361 * 2 - SAMPLE_IP requested to have 0 skid 362 * 3 - SAMPLE_IP must have 0 skid 363 * 364 * See also PERF_RECORD_MISC_EXACT_IP 365 */ 366 precise_ip : 2, /* skid constraint */ 367 mmap_data : 1, /* non-exec mmap data */ 368 sample_id_all : 1, /* sample_type all events */ 369 370 exclude_host : 1, /* don't count in host */ 371 exclude_guest : 1, /* don't count in guest */ 372 373 exclude_callchain_kernel : 1, /* exclude kernel callchains */ 374 exclude_callchain_user : 1, /* exclude user callchains */ 375 mmap2 : 1, /* include mmap with inode data */ 376 comm_exec : 1, /* flag comm events that are due to an exec */ 377 use_clockid : 1, /* use @clockid for time fields */ 378 context_switch : 1, /* context switch data */ 379 write_backward : 1, /* Write ring buffer from end to beginning */ 380 namespaces : 1, /* include namespaces data */ 381 ksymbol : 1, /* include ksymbol events */ 382 bpf_event : 1, /* include bpf events */ 383 aux_output : 1, /* generate AUX records instead of events */ 384 __reserved_1 : 32; 385 386 union { 387 __u32 wakeup_events; /* wakeup every n events */ 388 __u32 wakeup_watermark; /* bytes before wakeup */ 389 }; 390 391 __u32 bp_type; 392 union { 393 __u64 bp_addr; 394 __u64 kprobe_func; /* for perf_kprobe */ 395 __u64 uprobe_path; /* for perf_uprobe */ 396 __u64 config1; /* extension of config */ 397 }; 398 union { 399 __u64 bp_len; 400 __u64 kprobe_addr; /* when kprobe_func == NULL */ 401 __u64 probe_offset; /* for perf_[k,u]probe */ 402 __u64 config2; /* extension of config1 */ 403 }; 404 __u64 branch_sample_type; /* enum perf_branch_sample_type */ 405 406 /* 407 * Defines set of user regs to dump on samples. 408 * See asm/perf_regs.h for details. 409 */ 410 __u64 sample_regs_user; 411 412 /* 413 * Defines size of the user stack to dump on samples. 414 */ 415 __u32 sample_stack_user; 416 417 __s32 clockid; 418 /* 419 * Defines set of regs to dump for each sample 420 * state captured on: 421 * - precise = 0: PMU interrupt 422 * - precise > 0: sampled instruction 423 * 424 * See asm/perf_regs.h for details. 425 */ 426 __u64 sample_regs_intr; 427 428 /* 429 * Wakeup watermark for AUX area 430 */ 431 __u32 aux_watermark; 432 __u16 sample_max_stack; 433 __u16 __reserved_2; 434 __u32 aux_sample_size; 435 __u32 __reserved_3; 436 }; 437 438 /* 439 * Structure used by below PERF_EVENT_IOC_QUERY_BPF command 440 * to query bpf programs attached to the same perf tracepoint 441 * as the given perf event. 442 */ 443 struct perf_event_query_bpf { 444 /* 445 * The below ids array length 446 */ 447 __u32 ids_len; 448 /* 449 * Set by the kernel to indicate the number of 450 * available programs 451 */ 452 __u32 prog_cnt; 453 /* 454 * User provided buffer to store program ids 455 */ 456 __u32 ids[0]; 457 }; 458 459 /* 460 * Ioctls that can be done on a perf event fd: 461 */ 462 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 463 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 464 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 465 #define PERF_EVENT_IOC_RESET _IO ('$', 3) 466 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 467 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 468 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 469 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 470 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) 471 #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) 472 #define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) 473 #define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *) 474 475 enum perf_event_ioc_flags { 476 PERF_IOC_FLAG_GROUP = 1U << 0, 477 }; 478 479 /* 480 * Structure of the page that can be mapped via mmap 481 */ 482 struct perf_event_mmap_page { 483 __u32 version; /* version number of this structure */ 484 __u32 compat_version; /* lowest version this is compat with */ 485 486 /* 487 * Bits needed to read the hw events in user-space. 488 * 489 * u32 seq, time_mult, time_shift, index, width; 490 * u64 count, enabled, running; 491 * u64 cyc, time_offset; 492 * s64 pmc = 0; 493 * 494 * do { 495 * seq = pc->lock; 496 * barrier() 497 * 498 * enabled = pc->time_enabled; 499 * running = pc->time_running; 500 * 501 * if (pc->cap_usr_time && enabled != running) { 502 * cyc = rdtsc(); 503 * time_offset = pc->time_offset; 504 * time_mult = pc->time_mult; 505 * time_shift = pc->time_shift; 506 * } 507 * 508 * index = pc->index; 509 * count = pc->offset; 510 * if (pc->cap_user_rdpmc && index) { 511 * width = pc->pmc_width; 512 * pmc = rdpmc(index - 1); 513 * } 514 * 515 * barrier(); 516 * } while (pc->lock != seq); 517 * 518 * NOTE: for obvious reason this only works on self-monitoring 519 * processes. 520 */ 521 __u32 lock; /* seqlock for synchronization */ 522 __u32 index; /* hardware event identifier */ 523 __s64 offset; /* add to hardware event value */ 524 __u64 time_enabled; /* time event active */ 525 __u64 time_running; /* time event on cpu */ 526 union { 527 __u64 capabilities; 528 struct { 529 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ 530 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ 531 532 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ 533 cap_user_time : 1, /* The time_* fields are used */ 534 cap_user_time_zero : 1, /* The time_zero field is used */ 535 cap_____res : 59; 536 }; 537 }; 538 539 /* 540 * If cap_user_rdpmc this field provides the bit-width of the value 541 * read using the rdpmc() or equivalent instruction. This can be used 542 * to sign extend the result like: 543 * 544 * pmc <<= 64 - width; 545 * pmc >>= 64 - width; // signed shift right 546 * count += pmc; 547 */ 548 __u16 pmc_width; 549 550 /* 551 * If cap_usr_time the below fields can be used to compute the time 552 * delta since time_enabled (in ns) using rdtsc or similar. 553 * 554 * u64 quot, rem; 555 * u64 delta; 556 * 557 * quot = (cyc >> time_shift); 558 * rem = cyc & (((u64)1 << time_shift) - 1); 559 * delta = time_offset + quot * time_mult + 560 * ((rem * time_mult) >> time_shift); 561 * 562 * Where time_offset,time_mult,time_shift and cyc are read in the 563 * seqcount loop described above. This delta can then be added to 564 * enabled and possible running (if index), improving the scaling: 565 * 566 * enabled += delta; 567 * if (index) 568 * running += delta; 569 * 570 * quot = count / running; 571 * rem = count % running; 572 * count = quot * enabled + (rem * enabled) / running; 573 */ 574 __u16 time_shift; 575 __u32 time_mult; 576 __u64 time_offset; 577 /* 578 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated 579 * from sample timestamps. 580 * 581 * time = timestamp - time_zero; 582 * quot = time / time_mult; 583 * rem = time % time_mult; 584 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; 585 * 586 * And vice versa: 587 * 588 * quot = cyc >> time_shift; 589 * rem = cyc & (((u64)1 << time_shift) - 1); 590 * timestamp = time_zero + quot * time_mult + 591 * ((rem * time_mult) >> time_shift); 592 */ 593 __u64 time_zero; 594 __u32 size; /* Header size up to __reserved[] fields. */ 595 596 /* 597 * Hole for extension of the self monitor capabilities 598 */ 599 600 __u8 __reserved[118*8+4]; /* align to 1k. */ 601 602 /* 603 * Control data for the mmap() data buffer. 604 * 605 * User-space reading the @data_head value should issue an smp_rmb(), 606 * after reading this value. 607 * 608 * When the mapping is PROT_WRITE the @data_tail value should be 609 * written by userspace to reflect the last read data, after issueing 610 * an smp_mb() to separate the data read from the ->data_tail store. 611 * In this case the kernel will not over-write unread data. 612 * 613 * See perf_output_put_handle() for the data ordering. 614 * 615 * data_{offset,size} indicate the location and size of the perf record 616 * buffer within the mmapped area. 617 */ 618 __u64 data_head; /* head in the data section */ 619 __u64 data_tail; /* user-space written tail */ 620 __u64 data_offset; /* where the buffer starts */ 621 __u64 data_size; /* data buffer size */ 622 623 /* 624 * AUX area is defined by aux_{offset,size} fields that should be set 625 * by the userspace, so that 626 * 627 * aux_offset >= data_offset + data_size 628 * 629 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size. 630 * 631 * Ring buffer pointers aux_{head,tail} have the same semantics as 632 * data_{head,tail} and same ordering rules apply. 633 */ 634 __u64 aux_head; 635 __u64 aux_tail; 636 __u64 aux_offset; 637 __u64 aux_size; 638 }; 639 640 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 641 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 642 #define PERF_RECORD_MISC_KERNEL (1 << 0) 643 #define PERF_RECORD_MISC_USER (2 << 0) 644 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 645 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 646 #define PERF_RECORD_MISC_GUEST_USER (5 << 0) 647 648 /* 649 * Indicates that /proc/PID/maps parsing are truncated by time out. 650 */ 651 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) 652 /* 653 * Following PERF_RECORD_MISC_* are used on different 654 * events, so can reuse the same bit position: 655 * 656 * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events 657 * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event 658 * PERF_RECORD_MISC_FORK_EXEC - PERF_RECORD_FORK event (perf internal) 659 * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events 660 */ 661 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 662 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 663 #define PERF_RECORD_MISC_FORK_EXEC (1 << 13) 664 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) 665 /* 666 * These PERF_RECORD_MISC_* flags below are safely reused 667 * for the following events: 668 * 669 * PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events 670 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events 671 * 672 * 673 * PERF_RECORD_MISC_EXACT_IP: 674 * Indicates that the content of PERF_SAMPLE_IP points to 675 * the actual instruction that triggered the event. See also 676 * perf_event_attr::precise_ip. 677 * 678 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT: 679 * Indicates that thread was preempted in TASK_RUNNING state. 680 */ 681 #define PERF_RECORD_MISC_EXACT_IP (1 << 14) 682 #define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14) 683 /* 684 * Reserve the last bit to indicate some extended misc field 685 */ 686 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 687 688 struct perf_event_header { 689 __u32 type; 690 __u16 misc; 691 __u16 size; 692 }; 693 694 struct perf_ns_link_info { 695 __u64 dev; 696 __u64 ino; 697 }; 698 699 enum { 700 NET_NS_INDEX = 0, 701 UTS_NS_INDEX = 1, 702 IPC_NS_INDEX = 2, 703 PID_NS_INDEX = 3, 704 USER_NS_INDEX = 4, 705 MNT_NS_INDEX = 5, 706 CGROUP_NS_INDEX = 6, 707 708 NR_NAMESPACES, /* number of available namespaces */ 709 }; 710 711 enum perf_event_type { 712 713 /* 714 * If perf_event_attr.sample_id_all is set then all event types will 715 * have the sample_type selected fields related to where/when 716 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, 717 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed 718 * just after the perf_event_header and the fields already present for 719 * the existing fields, i.e. at the end of the payload. That way a newer 720 * perf.data file will be supported by older perf tools, with these new 721 * optional fields being ignored. 722 * 723 * struct sample_id { 724 * { u32 pid, tid; } && PERF_SAMPLE_TID 725 * { u64 time; } && PERF_SAMPLE_TIME 726 * { u64 id; } && PERF_SAMPLE_ID 727 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 728 * { u32 cpu, res; } && PERF_SAMPLE_CPU 729 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 730 * } && perf_event_attr::sample_id_all 731 * 732 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The 733 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed 734 * relative to header.size. 735 */ 736 737 /* 738 * The MMAP events record the PROT_EXEC mappings so that we can 739 * correlate userspace IPs to code. They have the following structure: 740 * 741 * struct { 742 * struct perf_event_header header; 743 * 744 * u32 pid, tid; 745 * u64 addr; 746 * u64 len; 747 * u64 pgoff; 748 * char filename[]; 749 * struct sample_id sample_id; 750 * }; 751 */ 752 PERF_RECORD_MMAP = 1, 753 754 /* 755 * struct { 756 * struct perf_event_header header; 757 * u64 id; 758 * u64 lost; 759 * struct sample_id sample_id; 760 * }; 761 */ 762 PERF_RECORD_LOST = 2, 763 764 /* 765 * struct { 766 * struct perf_event_header header; 767 * 768 * u32 pid, tid; 769 * char comm[]; 770 * struct sample_id sample_id; 771 * }; 772 */ 773 PERF_RECORD_COMM = 3, 774 775 /* 776 * struct { 777 * struct perf_event_header header; 778 * u32 pid, ppid; 779 * u32 tid, ptid; 780 * u64 time; 781 * struct sample_id sample_id; 782 * }; 783 */ 784 PERF_RECORD_EXIT = 4, 785 786 /* 787 * struct { 788 * struct perf_event_header header; 789 * u64 time; 790 * u64 id; 791 * u64 stream_id; 792 * struct sample_id sample_id; 793 * }; 794 */ 795 PERF_RECORD_THROTTLE = 5, 796 PERF_RECORD_UNTHROTTLE = 6, 797 798 /* 799 * struct { 800 * struct perf_event_header header; 801 * u32 pid, ppid; 802 * u32 tid, ptid; 803 * u64 time; 804 * struct sample_id sample_id; 805 * }; 806 */ 807 PERF_RECORD_FORK = 7, 808 809 /* 810 * struct { 811 * struct perf_event_header header; 812 * u32 pid, tid; 813 * 814 * struct read_format values; 815 * struct sample_id sample_id; 816 * }; 817 */ 818 PERF_RECORD_READ = 8, 819 820 /* 821 * struct { 822 * struct perf_event_header header; 823 * 824 * # 825 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. 826 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position 827 * # is fixed relative to header. 828 * # 829 * 830 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 831 * { u64 ip; } && PERF_SAMPLE_IP 832 * { u32 pid, tid; } && PERF_SAMPLE_TID 833 * { u64 time; } && PERF_SAMPLE_TIME 834 * { u64 addr; } && PERF_SAMPLE_ADDR 835 * { u64 id; } && PERF_SAMPLE_ID 836 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 837 * { u32 cpu, res; } && PERF_SAMPLE_CPU 838 * { u64 period; } && PERF_SAMPLE_PERIOD 839 * 840 * { struct read_format values; } && PERF_SAMPLE_READ 841 * 842 * { u64 nr, 843 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 844 * 845 * # 846 * # The RAW record below is opaque data wrt the ABI 847 * # 848 * # That is, the ABI doesn't make any promises wrt to 849 * # the stability of its content, it may vary depending 850 * # on event, hardware, kernel version and phase of 851 * # the moon. 852 * # 853 * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 854 * # 855 * 856 * { u32 size; 857 * char data[size];}&& PERF_SAMPLE_RAW 858 * 859 * { u64 nr; 860 * { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX 861 * { u64 from, to, flags } lbr[nr]; 862 * } && PERF_SAMPLE_BRANCH_STACK 863 * 864 * { u64 abi; # enum perf_sample_regs_abi 865 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER 866 * 867 * { u64 size; 868 * char data[size]; 869 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 870 * 871 * { u64 weight; } && PERF_SAMPLE_WEIGHT 872 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 873 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION 874 * { u64 abi; # enum perf_sample_regs_abi 875 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR 876 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR 877 * { u64 size; 878 * char data[size]; } && PERF_SAMPLE_AUX 879 * }; 880 */ 881 PERF_RECORD_SAMPLE = 9, 882 883 /* 884 * The MMAP2 records are an augmented version of MMAP, they add 885 * maj, min, ino numbers to be used to uniquely identify each mapping 886 * 887 * struct { 888 * struct perf_event_header header; 889 * 890 * u32 pid, tid; 891 * u64 addr; 892 * u64 len; 893 * u64 pgoff; 894 * u32 maj; 895 * u32 min; 896 * u64 ino; 897 * u64 ino_generation; 898 * u32 prot, flags; 899 * char filename[]; 900 * struct sample_id sample_id; 901 * }; 902 */ 903 PERF_RECORD_MMAP2 = 10, 904 905 /* 906 * Records that new data landed in the AUX buffer part. 907 * 908 * struct { 909 * struct perf_event_header header; 910 * 911 * u64 aux_offset; 912 * u64 aux_size; 913 * u64 flags; 914 * struct sample_id sample_id; 915 * }; 916 */ 917 PERF_RECORD_AUX = 11, 918 919 /* 920 * Indicates that instruction trace has started 921 * 922 * struct { 923 * struct perf_event_header header; 924 * u32 pid; 925 * u32 tid; 926 * struct sample_id sample_id; 927 * }; 928 */ 929 PERF_RECORD_ITRACE_START = 12, 930 931 /* 932 * Records the dropped/lost sample number. 933 * 934 * struct { 935 * struct perf_event_header header; 936 * 937 * u64 lost; 938 * struct sample_id sample_id; 939 * }; 940 */ 941 PERF_RECORD_LOST_SAMPLES = 13, 942 943 /* 944 * Records a context switch in or out (flagged by 945 * PERF_RECORD_MISC_SWITCH_OUT). See also 946 * PERF_RECORD_SWITCH_CPU_WIDE. 947 * 948 * struct { 949 * struct perf_event_header header; 950 * struct sample_id sample_id; 951 * }; 952 */ 953 PERF_RECORD_SWITCH = 14, 954 955 /* 956 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and 957 * next_prev_tid that are the next (switching out) or previous 958 * (switching in) pid/tid. 959 * 960 * struct { 961 * struct perf_event_header header; 962 * u32 next_prev_pid; 963 * u32 next_prev_tid; 964 * struct sample_id sample_id; 965 * }; 966 */ 967 PERF_RECORD_SWITCH_CPU_WIDE = 15, 968 969 /* 970 * struct { 971 * struct perf_event_header header; 972 * u32 pid; 973 * u32 tid; 974 * u64 nr_namespaces; 975 * { u64 dev, inode; } [nr_namespaces]; 976 * struct sample_id sample_id; 977 * }; 978 */ 979 PERF_RECORD_NAMESPACES = 16, 980 981 /* 982 * Record ksymbol register/unregister events: 983 * 984 * struct { 985 * struct perf_event_header header; 986 * u64 addr; 987 * u32 len; 988 * u16 ksym_type; 989 * u16 flags; 990 * char name[]; 991 * struct sample_id sample_id; 992 * }; 993 */ 994 PERF_RECORD_KSYMBOL = 17, 995 996 /* 997 * Record bpf events: 998 * enum perf_bpf_event_type { 999 * PERF_BPF_EVENT_UNKNOWN = 0, 1000 * PERF_BPF_EVENT_PROG_LOAD = 1, 1001 * PERF_BPF_EVENT_PROG_UNLOAD = 2, 1002 * }; 1003 * 1004 * struct { 1005 * struct perf_event_header header; 1006 * u16 type; 1007 * u16 flags; 1008 * u32 id; 1009 * u8 tag[BPF_TAG_SIZE]; 1010 * struct sample_id sample_id; 1011 * }; 1012 */ 1013 PERF_RECORD_BPF_EVENT = 18, 1014 1015 PERF_RECORD_MAX, /* non-ABI */ 1016 }; 1017 1018 enum perf_record_ksymbol_type { 1019 PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0, 1020 PERF_RECORD_KSYMBOL_TYPE_BPF = 1, 1021 PERF_RECORD_KSYMBOL_TYPE_MAX /* non-ABI */ 1022 }; 1023 1024 #define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0) 1025 1026 enum perf_bpf_event_type { 1027 PERF_BPF_EVENT_UNKNOWN = 0, 1028 PERF_BPF_EVENT_PROG_LOAD = 1, 1029 PERF_BPF_EVENT_PROG_UNLOAD = 2, 1030 PERF_BPF_EVENT_MAX, /* non-ABI */ 1031 }; 1032 1033 #define PERF_MAX_STACK_DEPTH 127 1034 #define PERF_MAX_CONTEXTS_PER_STACK 8 1035 1036 enum perf_callchain_context { 1037 PERF_CONTEXT_HV = (__u64)-32, 1038 PERF_CONTEXT_KERNEL = (__u64)-128, 1039 PERF_CONTEXT_USER = (__u64)-512, 1040 1041 PERF_CONTEXT_GUEST = (__u64)-2048, 1042 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 1043 PERF_CONTEXT_GUEST_USER = (__u64)-2560, 1044 1045 PERF_CONTEXT_MAX = (__u64)-4095, 1046 }; 1047 1048 /** 1049 * PERF_RECORD_AUX::flags bits 1050 */ 1051 #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ 1052 #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ 1053 #define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ 1054 #define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ 1055 1056 #define PERF_FLAG_FD_NO_GROUP (1UL << 0) 1057 #define PERF_FLAG_FD_OUTPUT (1UL << 1) 1058 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ 1059 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ 1060 1061 #if defined(__LITTLE_ENDIAN_BITFIELD) 1062 union perf_mem_data_src { 1063 __u64 val; 1064 struct { 1065 __u64 mem_op:5, /* type of opcode */ 1066 mem_lvl:14, /* memory hierarchy level */ 1067 mem_snoop:5, /* snoop mode */ 1068 mem_lock:2, /* lock instr */ 1069 mem_dtlb:7, /* tlb access */ 1070 mem_lvl_num:4, /* memory hierarchy level number */ 1071 mem_remote:1, /* remote */ 1072 mem_snoopx:2, /* snoop mode, ext */ 1073 mem_rsvd:24; 1074 }; 1075 }; 1076 #elif defined(__BIG_ENDIAN_BITFIELD) 1077 union perf_mem_data_src { 1078 __u64 val; 1079 struct { 1080 __u64 mem_rsvd:24, 1081 mem_snoopx:2, /* snoop mode, ext */ 1082 mem_remote:1, /* remote */ 1083 mem_lvl_num:4, /* memory hierarchy level number */ 1084 mem_dtlb:7, /* tlb access */ 1085 mem_lock:2, /* lock instr */ 1086 mem_snoop:5, /* snoop mode */ 1087 mem_lvl:14, /* memory hierarchy level */ 1088 mem_op:5; /* type of opcode */ 1089 }; 1090 }; 1091 #else 1092 #error "Unknown endianness" 1093 #endif 1094 1095 /* type of opcode (load/store/prefetch,code) */ 1096 #define PERF_MEM_OP_NA 0x01 /* not available */ 1097 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */ 1098 #define PERF_MEM_OP_STORE 0x04 /* store instruction */ 1099 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ 1100 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ 1101 #define PERF_MEM_OP_SHIFT 0 1102 1103 /* memory hierarchy (memory level, hit or miss) */ 1104 #define PERF_MEM_LVL_NA 0x01 /* not available */ 1105 #define PERF_MEM_LVL_HIT 0x02 /* hit level */ 1106 #define PERF_MEM_LVL_MISS 0x04 /* miss level */ 1107 #define PERF_MEM_LVL_L1 0x08 /* L1 */ 1108 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ 1109 #define PERF_MEM_LVL_L2 0x20 /* L2 */ 1110 #define PERF_MEM_LVL_L3 0x40 /* L3 */ 1111 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ 1112 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ 1113 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ 1114 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ 1115 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ 1116 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 1117 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 1118 #define PERF_MEM_LVL_SHIFT 5 1119 1120 #define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */ 1121 #define PERF_MEM_REMOTE_SHIFT 37 1122 1123 #define PERF_MEM_LVLNUM_L1 0x01 /* L1 */ 1124 #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ 1125 #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ 1126 #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ 1127 /* 5-0xa available */ 1128 #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ 1129 #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ 1130 #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ 1131 #define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */ 1132 #define PERF_MEM_LVLNUM_NA 0x0f /* N/A */ 1133 1134 #define PERF_MEM_LVLNUM_SHIFT 33 1135 1136 /* snoop mode */ 1137 #define PERF_MEM_SNOOP_NA 0x01 /* not available */ 1138 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ 1139 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ 1140 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ 1141 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ 1142 #define PERF_MEM_SNOOP_SHIFT 19 1143 1144 #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ 1145 /* 1 free */ 1146 #define PERF_MEM_SNOOPX_SHIFT 37 1147 1148 /* locked instruction */ 1149 #define PERF_MEM_LOCK_NA 0x01 /* not available */ 1150 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ 1151 #define PERF_MEM_LOCK_SHIFT 24 1152 1153 /* TLB access */ 1154 #define PERF_MEM_TLB_NA 0x01 /* not available */ 1155 #define PERF_MEM_TLB_HIT 0x02 /* hit level */ 1156 #define PERF_MEM_TLB_MISS 0x04 /* miss level */ 1157 #define PERF_MEM_TLB_L1 0x08 /* L1 */ 1158 #define PERF_MEM_TLB_L2 0x10 /* L2 */ 1159 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ 1160 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ 1161 #define PERF_MEM_TLB_SHIFT 26 1162 1163 #define PERF_MEM_S(a, s) \ 1164 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 1165 1166 /* 1167 * single taken branch record layout: 1168 * 1169 * from: source instruction (may not always be a branch insn) 1170 * to: branch target 1171 * mispred: branch target was mispredicted 1172 * predicted: branch target was predicted 1173 * 1174 * support for mispred, predicted is optional. In case it 1175 * is not supported mispred = predicted = 0. 1176 * 1177 * in_tx: running in a hardware transaction 1178 * abort: aborting a hardware transaction 1179 * cycles: cycles from last branch (or 0 if not supported) 1180 * type: branch type 1181 */ 1182 struct perf_branch_entry { 1183 __u64 from; 1184 __u64 to; 1185 __u64 mispred:1, /* target mispredicted */ 1186 predicted:1,/* target predicted */ 1187 in_tx:1, /* in transaction */ 1188 abort:1, /* transaction abort */ 1189 cycles:16, /* cycle count to last branch */ 1190 type:4, /* branch type */ 1191 reserved:40; 1192 }; 1193 1194 #endif /* _UAPI_LINUX_PERF_EVENT_H */ 1195