1 /* 2 * Copyright (c) 2014-2015, Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU Lesser General Public License, 6 * version 2.1, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT ANY 9 * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 10 * FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for 11 * more details. 12 */ 13 #ifndef __NDCTL_H__ 14 #define __NDCTL_H__ 15 16 #include <linux/types.h> 17 18 struct nd_cmd_smart { 19 __u32 status; 20 __u8 data[128]; 21 } __packed; 22 23 struct nd_cmd_smart_threshold { 24 __u32 status; 25 __u8 data[8]; 26 } __packed; 27 28 struct nd_cmd_dimm_flags { 29 __u32 status; 30 __u32 flags; 31 } __packed; 32 33 struct nd_cmd_get_config_size { 34 __u32 status; 35 __u32 config_size; 36 __u32 max_xfer; 37 } __packed; 38 39 struct nd_cmd_get_config_data_hdr { 40 __u32 in_offset; 41 __u32 in_length; 42 __u32 status; 43 __u8 out_buf[0]; 44 } __packed; 45 46 struct nd_cmd_set_config_hdr { 47 __u32 in_offset; 48 __u32 in_length; 49 __u8 in_buf[0]; 50 } __packed; 51 52 struct nd_cmd_vendor_hdr { 53 __u32 opcode; 54 __u32 in_length; 55 __u8 in_buf[0]; 56 } __packed; 57 58 struct nd_cmd_vendor_tail { 59 __u32 status; 60 __u32 out_length; 61 __u8 out_buf[0]; 62 } __packed; 63 64 struct nd_cmd_ars_cap { 65 __u64 address; 66 __u64 length; 67 __u32 status; 68 __u32 max_ars_out; 69 __u32 clear_err_unit; 70 __u32 reserved; 71 } __packed; 72 73 struct nd_cmd_ars_start { 74 __u64 address; 75 __u64 length; 76 __u16 type; 77 __u8 flags; 78 __u8 reserved[5]; 79 __u32 status; 80 __u32 scrub_time; 81 } __packed; 82 83 struct nd_cmd_ars_status { 84 __u32 status; 85 __u32 out_length; 86 __u64 address; 87 __u64 length; 88 __u64 restart_address; 89 __u64 restart_length; 90 __u16 type; 91 __u16 flags; 92 __u32 num_records; 93 struct nd_ars_record { 94 __u32 handle; 95 __u32 reserved; 96 __u64 err_address; 97 __u64 length; 98 } __packed records[0]; 99 } __packed; 100 101 enum { 102 ND_CMD_IMPLEMENTED = 0, 103 104 /* bus commands */ 105 ND_CMD_ARS_CAP = 1, 106 ND_CMD_ARS_START = 2, 107 ND_CMD_ARS_STATUS = 3, 108 109 /* per-dimm commands */ 110 ND_CMD_SMART = 1, 111 ND_CMD_SMART_THRESHOLD = 2, 112 ND_CMD_DIMM_FLAGS = 3, 113 ND_CMD_GET_CONFIG_SIZE = 4, 114 ND_CMD_GET_CONFIG_DATA = 5, 115 ND_CMD_SET_CONFIG_DATA = 6, 116 ND_CMD_VENDOR_EFFECT_LOG_SIZE = 7, 117 ND_CMD_VENDOR_EFFECT_LOG = 8, 118 ND_CMD_VENDOR = 9, 119 }; 120 121 enum { 122 ND_ARS_VOLATILE = 1, 123 ND_ARS_PERSISTENT = 2, 124 }; 125 126 static inline const char *nvdimm_bus_cmd_name(unsigned cmd) 127 { 128 static const char * const names[] = { 129 [ND_CMD_ARS_CAP] = "ars_cap", 130 [ND_CMD_ARS_START] = "ars_start", 131 [ND_CMD_ARS_STATUS] = "ars_status", 132 }; 133 134 if (cmd < ARRAY_SIZE(names) && names[cmd]) 135 return names[cmd]; 136 return "unknown"; 137 } 138 139 static inline const char *nvdimm_cmd_name(unsigned cmd) 140 { 141 static const char * const names[] = { 142 [ND_CMD_SMART] = "smart", 143 [ND_CMD_SMART_THRESHOLD] = "smart_thresh", 144 [ND_CMD_DIMM_FLAGS] = "flags", 145 [ND_CMD_GET_CONFIG_SIZE] = "get_size", 146 [ND_CMD_GET_CONFIG_DATA] = "get_data", 147 [ND_CMD_SET_CONFIG_DATA] = "set_data", 148 [ND_CMD_VENDOR_EFFECT_LOG_SIZE] = "effect_size", 149 [ND_CMD_VENDOR_EFFECT_LOG] = "effect_log", 150 [ND_CMD_VENDOR] = "vendor", 151 }; 152 153 if (cmd < ARRAY_SIZE(names) && names[cmd]) 154 return names[cmd]; 155 return "unknown"; 156 } 157 158 #define ND_IOCTL 'N' 159 160 #define ND_IOCTL_SMART _IOWR(ND_IOCTL, ND_CMD_SMART,\ 161 struct nd_cmd_smart) 162 163 #define ND_IOCTL_SMART_THRESHOLD _IOWR(ND_IOCTL, ND_CMD_SMART_THRESHOLD,\ 164 struct nd_cmd_smart_threshold) 165 166 #define ND_IOCTL_DIMM_FLAGS _IOWR(ND_IOCTL, ND_CMD_DIMM_FLAGS,\ 167 struct nd_cmd_dimm_flags) 168 169 #define ND_IOCTL_GET_CONFIG_SIZE _IOWR(ND_IOCTL, ND_CMD_GET_CONFIG_SIZE,\ 170 struct nd_cmd_get_config_size) 171 172 #define ND_IOCTL_GET_CONFIG_DATA _IOWR(ND_IOCTL, ND_CMD_GET_CONFIG_DATA,\ 173 struct nd_cmd_get_config_data_hdr) 174 175 #define ND_IOCTL_SET_CONFIG_DATA _IOWR(ND_IOCTL, ND_CMD_SET_CONFIG_DATA,\ 176 struct nd_cmd_set_config_hdr) 177 178 #define ND_IOCTL_VENDOR _IOWR(ND_IOCTL, ND_CMD_VENDOR,\ 179 struct nd_cmd_vendor_hdr) 180 181 #define ND_IOCTL_ARS_CAP _IOWR(ND_IOCTL, ND_CMD_ARS_CAP,\ 182 struct nd_cmd_ars_cap) 183 184 #define ND_IOCTL_ARS_START _IOWR(ND_IOCTL, ND_CMD_ARS_START,\ 185 struct nd_cmd_ars_start) 186 187 #define ND_IOCTL_ARS_STATUS _IOWR(ND_IOCTL, ND_CMD_ARS_STATUS,\ 188 struct nd_cmd_ars_status) 189 190 #define ND_DEVICE_DIMM 1 /* nd_dimm: container for "config data" */ 191 #define ND_DEVICE_REGION_PMEM 2 /* nd_region: (parent of PMEM namespaces) */ 192 #define ND_DEVICE_REGION_BLK 3 /* nd_region: (parent of BLK namespaces) */ 193 #define ND_DEVICE_NAMESPACE_IO 4 /* legacy persistent memory */ 194 #define ND_DEVICE_NAMESPACE_PMEM 5 /* PMEM namespace (may alias with BLK) */ 195 #define ND_DEVICE_NAMESPACE_BLK 6 /* BLK namespace (may alias with PMEM) */ 196 197 enum nd_driver_flags { 198 ND_DRIVER_DIMM = 1 << ND_DEVICE_DIMM, 199 ND_DRIVER_REGION_PMEM = 1 << ND_DEVICE_REGION_PMEM, 200 ND_DRIVER_REGION_BLK = 1 << ND_DEVICE_REGION_BLK, 201 ND_DRIVER_NAMESPACE_IO = 1 << ND_DEVICE_NAMESPACE_IO, 202 ND_DRIVER_NAMESPACE_PMEM = 1 << ND_DEVICE_NAMESPACE_PMEM, 203 ND_DRIVER_NAMESPACE_BLK = 1 << ND_DEVICE_NAMESPACE_BLK, 204 }; 205 206 enum { 207 ND_MIN_NAMESPACE_SIZE = 0x00400000, 208 }; 209 210 enum ars_masks { 211 ARS_STATUS_MASK = 0x0000FFFF, 212 ARS_EXT_STATUS_SHIFT = 16, 213 }; 214 #endif /* __NDCTL_H__ */ 215